MC9S12ZVMRM: MC9S12ZVM-Family Reference Manual and Datasheet

MC9S12ZVMRM, S12, S12Z

NXP Semiconductors

MC9S12ZVMRM ?&fsrch=1&sr=8&pageNum=1
MC9S12ZVM-Family Reference Manual and Datasheet
S12 MagniV Microcontrollers
Rev. 2.13 29 Apr 2019 MC9S12ZVMRM
nxp.com

The ZVMC256, ZVML31, ZVM32 and ZVM16 devices are targeted for safety relevant systems and have been developed using an ISO26262 compliant development system under the NXP SafeAssure program. For details of device usage in safety relevant systems refer to the MC9S12ZVMB Safety Manual. The document revision on the Internet is the most current. To verify this is the latest revision, refer to: nxp.com. This document contains information for all modules except the CPU. For CPU information please refer to the CPU S12Z Reference Manual. This revision history table summarizes changes to this document. The individual module sections contain revision history tables with more detailed information.
NOTE This reference manual documents the S12ZVM-Family.
It contains a superset of features within the family. Some module versions differ from one part to another within the family. Section 1.2.1 MC9S12ZVM-Family Member Comparison provides support to access the
correct information for a particular part within the family.
NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP Semiconductors products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the NXP Semiconductors product could create a situation where personal injury or death may occur. Should Buyer purchase or use NXP Semiconductors products for any such unintended or unauthorized application, Buyer shall indemnify and hold NXP Semiconductors and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that NXP Semiconductors was negligent regarding the design or manufacture of the part.

Table 0-1. Revision History

Date 20 MAR 2015
22 APR 2015 27 APR 2015 20 NOV 2015

Revision

Description

2.0

Added ZVMC256 information

Added mask set 2N95G information

Added more detailed PTU minimum trigger spacing description

Updated CPMU, PIM and GDU chapters for ZVMC256

Improved CPMU specification clarity (see CPMU revision history)

Removed electrical parameter classification

Added reset startup timing parameter

Updated BATS parameters

Extended BKGD VIL condition from 3.15V to 3.13V Extended GDU operating range from 26V to 26.6V

Temperature sensor output at 150C changed from 2.25V to 2.33V.

Added GDU VBS current parameter

Updated package thermal information for ZVM32 and ZVM16 parts

Added VBG temperature and voltage dependency parameters

Added device stop current at 105C.

2.1

Updated Stop and Wait current parameter values (ISUPS, ISUPW)

Corrected 80LQFP-EP pin name from VSS2 to VSS1

Updated ZVMC256 VDDS regulator parameters.

Changed PL0 ESD specification

Minor corrections to PIM, PMF, SRAM and ADC chapters (see module revision histories)

2.2

Updated Stop current parameter values (ISUPS)

Updated LINPHY parameter range limit to 5.5V

Added more information about VDDS1, VDDS2, SNPS1, SNPS2 to CPMU chapter.

Reintroduced EPRES bit for GDU V4

Added 80LQFP-EP mechanical package information

2.3

Added devices to Part ID list Table 1-6

Added explanation of GSUF dependency on xN14N mask set Table 1-19

Minor corrections to reset source and interrupt vector tables Table 1-15

Added device level POR information Figure 1-8

Minor correction to PIM chapter

Added constraints to EXTCON, SCS2 and SCS1 bits in CPMU chapter

Added PMF version difference table Table 15-3

Corrected footnotes and parameter spelling in GDU register summary

Noted GDU sense amplifier dependence on GFDE bit

Documented that flash option (FOPT) register can be written in special mode

Added pulsed absolute maximum rating for HSx pins Table A-2

Extended VDDS1 and VDDS2 maximum ratings Table A-2

Added thermal resistance parameter values for 80LQFP-EP package

Added VREG configuration to Run/Wait/Stop current measurement configurationTable A-16

Removed de-saturation thresholds from electrical spec. tables

Added footnote for GDU tdelon/tdeloff electrical parameters

Added max. and min. values for GDU HD signal division through phase mux.

Removed incorrect limit from BATS electrical parameter table headers

Extended CANPHY maximum ratings to 175°C

Updated SRAM_ECC chapter to cover ZVMC256

Minor correction to PMF chapter

Updated typical Stop IDD and Pseudo Stop IDD values for ZVMC256 based on validation data

Added ZVMC256 parameter for Stop IDD with CANPHY and API enabled Table A-19

Renamed bit GSLEWMOD to TDEL (GDU V6). Removed GSLEWMOD bit (GDU V5)

Noted temperature sensor slope is subject to further characterization

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Table 0-1. Revision History

Date 14 DEC 2015 14 JAN 2016 07 MAR 2016
08 MAR 2016 19 APR 2016 06 JUN 2016
29 JUN 2016

Revision

Description

2.4

Added T1IC0RR to PIM MODRR2 register

Updated temperature sensor electrical specification, Table B-1

Added GDU current sense amp unity bandwidth parameter Table E-1, Table E-2

Added GDU current sense input resistance footnote Table E-1, Table E-2

2.5

Clarified non production mask sets Table 1-4, Table 1-6

Updated ordering information in Appendix L

Changed RESET pin input pulse passed parameter minimum specification value.Table A-13

Replaced Freescale with NXP in logo and page footers

Added maximum value for GDU parameter VBSx current whilst high side inactive Table E-2

2.6

Added 3N95G mask set information Table 1-19, Table 1-4, Table 1-6

Added list of ISO26262 compliant devices

Moved GDU mask set dependent features to device overview section Table 1-19

Added new 64LQFP-EP package diagrams Table K.2

Added minimum value for GDU parameter VBSx current whilst high side inactive Table E-2

Updated VCSAoff parameter limits for GDU V5 and GDU V6 Table E-1, Table E-2 Added ADCCMD1[7:6] device dependencies in register listing Section M.13, Section M.14

Simplified GDU device dependencies in register listing Section M.15

Corrected High Temperature Interrupt spec. (cannot wake up from STOP) Table 1-16

Added footnote to Table A-14

ZVMC256: added typical Run/Wait IDD values, updated 85°C Stop IDD Table A-18, Table A-19

Added bootstrap diode resistance parameter Table E-2

Updated GDU boost coil current limit specification Table E-2, Table E-1

Reverted to original current sense amp. offset values Table E-2, Table E-1

Added package to mask set mapping table Table K-1

2.7

Changed maximum value of VBSTOFF Table E-2, Table E-1

Updated 48LQFP-EP Mechanical Information Diagram Section K.1

2.8

Added PAD pin leakage specification at 125C Table A-12

Updated tHGON, tHGOFF parameter values Table E-1 Specified VRH drop when using VDDS1 or VDDS2 as VRH on ZVMC256 Section C.1.1.5

Added min. and max. desaturation comparator filter times to electrical spec. Table E-1

Updated 64LQFP-EP thermal parameters Table A-9, Table A-10

2.9

Fixed corrupted symbol fonts Table A-3, Table A-5

Corrected wrong IFR reference Section 20.3.2.10

Clarified PAD8 leakage better Table A-12

Added ISUPR and ISUPW maximum values at TJ = 175°C for ZVMC256 Table A-18 Added Pseudo STOP maximum current for ZVMC256 Table A-20

Removed bandgap temperature dependency footnote, Table B-1

Changed ZVMC256 SNPS monitor threshold min/max values Table B-2

Changed VLS current limit threshold to 112mA Table E-1, Table E-2

Removed desaturation comparator filter times from GDU chapter.

Added desaturation comparator levels to Table E-1, Table E-2

Added low side desaturation comparator functional range as footnote Table E-1, Table E-2

2.10 Updated GDU VBS filter Figure 18-20 Removed incorrect reference to temperature sensor influencing GDU outputs Section 1.13.3.4 Changed Stop IDD (ISUPS) specifications for ZVMC256 Table A-19

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Table 0-1. Revision History

Date 28 OCT 2016 25 Jul 2017
28 Apr 2019

Revision

Description

2.11 Added IOC0 signal mapping to 48LQFP package Figure 1-6 Fixed corrupted symbol fonts in PIM chapter Added diode to VDDC pin Figure 1-18 Updated Stop mode current ISUPS maximum values Table A-19 Updated tdelon, tdeloff values Table E-1
2.12 Updated Section 1.7.2.26.8, "VDDC (Only Available On S12ZVMC Versions)" Updated Chapter 20, "Flash Module (S12ZFTMRZ) Added note on HVI current injection in Table A-14 Updated Section C.1.1.4, "Current Injection" Updated footnotes ofTable E-1 Updated tdelon, tdeloff values Table E-2
2.13 Removed "pulse accumulator" references in Section Chapter 11, "Timer Module (TIM16B4CV3) Block Description" and Section Chapter 12, "Timer Module (TIM16B2CV3) Block Description" Updated footnote 1 in Table A-6 Removed obsolete footnotes in Table E-1 and Table E-2 Removed term "preliminary" from title of E.2, "GDU specifications for devices featuring GDU V5"

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MC9S12ZVM Family Reference Manual Rev. 2.13

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Chapter 1
Device Overview MC9S12ZVM-Family
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.2.1 MC9S12ZVM-Family Member Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.2.2 Module Version Differences Within The S12ZVM Family . . . . . . . . . . . . . . . . . . . . . . . 27 1.2.3 Functional Differences Between Masksets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.3 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.1 S12Z Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.2 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4.3 Clocks, Reset & Power Management Unit (CPMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.4.4 Main External Oscillator (XOSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.4.5 Timer (TIM0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.4.6 Timer (TIM1) (ZVMC256 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.4.7 Pulse width Modulator with Fault protection (PMF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.4.8 Programmable Trigger Unit (PTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.4.9 LIN physical layer transceiver (ZVML devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.4.10 Serial Communication Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.4.11 Multi-Scalable Controller Area Network (MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.4.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.4.13 Analog-to-Digital Converter Module (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.4.14 Supply Voltage Sensor (BATS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.4.15 On-Chip Voltage Regulator system (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.4.16 Gate Drive Unit (GDU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.4.17 Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.4.18 High Voltage Physical Interface (ZVM32, ZVM16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.4.19 CAN Physical Layer Module (ZVMC256 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.4.20 Pulse Width Modulation Module (PWM) (ZVMC256 only) . . . . . . . . . . . . . . . . . . . . . 36 1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.6 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.6.1 Flash Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 1.6.2 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.7 Signal Description and Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.7.1 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.7.2 Detailed External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.7.3 Power Supply And Voltage Regulator Related Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.7.4 Package and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1.8 Internal Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1.8.1 ADC Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1.8.2 Motor Control Loop Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.8.3 Device Level PMF Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1.8.4 BDC Clock Source Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1.8.5 LINPHY Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1.8.6 HVPHY Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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1.8.7 FTMRZ Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.8.8 CPMU Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.9 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.9.1 Chip Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.9.2 Debugging Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.9.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.10 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.10.2 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.10.3 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.10.4 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.10.5 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 1.10.6 Complete Memory Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 1.11 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1.11.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1.11.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1.11.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.12 Module device level dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.12.1 CPMU COP and GDU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.12.2 CPMU High Temperature Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.12.3 CPMU VDDC enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.12.4 Flash IFR Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.13 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.13.1 ADC Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.13.2 SCI Baud Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 1.13.3 Motor Control Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 1.13.4 BDCM Complementary Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1.13.5 BLDC Six-Step Commutation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 1.13.6 PMSM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 1.13.7 Power Domain Overview (All devices except ZVMC256) . . . . . . . . . . . . . . . . . . . . . . . 96 1.13.8 Power Domain Overview (ZVMC256) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Chapter 2
Port Integration Module (S12ZVMPIMV3)
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
2.3.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.3.2 PIM Registers 0x0200-0x020F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 2.3.3 PIM Generic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 2.3.4 PIM Generic Register Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

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2.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 2.4.3 Pin I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 2.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 2.4.5 Pin interrupts and Key-Wakeup (KWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 2.4.6 Over-Current Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 2.4.7 High-Voltage Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 2.5 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 2.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 2.5.2 Open Input Detection on HVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 2.5.3 Over-Current Protection on EVDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Chapter 3 Memory Mapping Control (S12ZMMCV1)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 3.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
3.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 3.4.1 Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 3.4.2 Illegal Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 3.4.3 Uncorrectable ECC Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Chapter 4 Interrupt (S12ZINTV0)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 4.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 4.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 4.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
4.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 4.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.4.1 S12Z Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.4.3 Priority Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 4.4.4 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

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4.4.5 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 4.4.6 Interrupt Vector Table Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 4.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 4.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 4.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 4.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Chapter 5 Background Debug Controller (S12ZBDCV2)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 5.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 5.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 5.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 5.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 5.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 5.4.2 Enabling BDC And Entering Active BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 5.4.3 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 5.4.4 BDC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 5.4.5 BDC Access Of Internal Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 5.4.6 BDC Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 5.4.7 Serial Interface Hardware Handshake (ACK Pulse) Protocol . . . . . . . . . . . . . . . . . . . . 216 5.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.4.9 Hardware Handshake Disabled (ACK Pulse Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 219 5.4.10 Single Stepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 5.4.11 Serial Communication Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 5.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 5.5.1 Clock Frequency Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Chapter 6 S12Z Debug (S12ZDBG) Module
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 6.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 6.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 6.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 6.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 6.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.2.1 External Event Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.2.2 Profiling Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

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6.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 6.4.1 DBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 6.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 6.4.3 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 6.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 6.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 6.4.6 Code Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 6.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
6.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 6.5.1 Avoiding Unintended Breakpoint Re-triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 6.5.2 Debugging Through Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 6.5.3 Breakpoints from other S12Z sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 6.5.4 Code Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Chapter 7 ECC Generation Module (SRAM_ECCV1)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
7.2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 7.2.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 7.2.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 7.3.1 Non-aligned Memory Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 7.3.2 Aligned 2 and 4 Byte Memory Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 7.3.3 Memory Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 7.3.4 Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 7.3.5 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 7.3.6 ECC Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 7.3.7 ECC Debug Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Chapter 8 S12 Clock, Reset and Power Management Unit (00.17)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 8.1.1 Differences between S12CPMU_UHV_V10 and S12CPMU_UHV_V6 . . . . . . . . . . . 289 8.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 8.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 8.1.4 S12CPMU_UHV_V10_V6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
8.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 8.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 8.2.2 EXTAL and XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 8.2.3 VSUP -- Regulator Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

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8.2.4 VDDA, VSSA -- Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 8.2.5 VDDX, VSSX-- Pad Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 8.2.6 VDDC-- CAN Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 8.2.7 VDDS1-- Sensor Supply1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 8.2.8 VDDS2-- Sensor Supply2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 8.2.9 BCTL-- Base Control Pin for external PNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 8.2.10 BCTLC -- Base Control Pin for external PNP for VDDC power domain . . . . . . . . . . 299 8.2.11 BCTLS1 -- Base Control Pin for external PNP for VDDS1 power domain . . . . . . . . 299 8.2.12 BCTLS2 -- Base Control Pin for external PNP for VDDS2 power domain . . . . . . . . 300 8.2.13 SNPS1 -- Sense Pin for VDDS1 power domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 8.2.14 SNPS2 -- Sense Pin for VDDS2 power domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 8.2.15 VSS1,2 -- Core Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 8.2.16 VDD-- Core Logic Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 8.2.17 VDDF-- NVM Logic Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 8.2.18 API_EXTCLK -- API external clock output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 8.2.19 TEMPSENSE -- Internal Temperature Sensor Output Voltage . . . . . . . . . . . . . . . . . . 301 8.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 8.4.1 Phase Locked Loop with Internal Filter (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 8.4.2 Startup from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 8.4.3 Stop Mode using PLLCLK as source of the Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . 348 8.4.4 Full Stop Mode using Oscillator Clock as source of the Bus Clock . . . . . . . . . . . . . . . 348 8.4.5 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 8.4.6 System Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 8.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 8.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 8.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 8.5.3 Oscillator Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 8.5.4 PLL Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 8.5.5 Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 354 8.5.6 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 8.5.7 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 8.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 8.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 8.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 8.7.1 General Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 8.7.2 Application information for COP and API usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 8.7.3 Application Information for PLL and Oscillator Startup . . . . . . . . . . . . . . . . . . . . . . . . 359
Chapter 9
Analog-to-Digital Converter (ADC12B_LBA)

9.1 Differences ADC12B_LBA V1 vs V2 vs V3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

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9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 9.3 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
9.3.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 9.3.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 9.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 9.4.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 9.5 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 9.5.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 9.5.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 9.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 9.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 9.6.2 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 9.6.3 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 9.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 9.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 9.8.1 ADC Conversion Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 9.8.2 ADC Sequence Abort Done Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 9.8.3 ADC Error and Conversion Flow Control Issue Interrupt . . . . . . . . . . . . . . . . . . . . . . . 421 9.9 Use Cases and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 9.9.1 List Usage -- CSL single buffer mode and RVL single buffer mode . . . . . . . . . . . . . . 422 9.9.2 List Usage -- CSL single buffer mode and RVL double buffer mode . . . . . . . . . . . . . 422 9.9.3 List Usage -- CSL double buffer mode and RVL double buffer mode . . . . . . . . . . . . . 423 9.9.4 List Usage -- CSL double buffer mode and RVL single buffer mode . . . . . . . . . . . . . 423 9.9.5 List Usage -- CSL double buffer mode and RVL double buffer mode . . . . . . . . . . . . . 424 9.9.6 RVL swapping in RVL double buffer mode and related registers ADCIMDRI and
ADCEOLRI 424 9.9.7 Conversion flow control application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 9.9.8 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 9.9.9 Triggered Conversion -- Single CSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 9.9.10 Fully Timing Controlled Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Chapter 10
Supply Voltage Sensor - (BATSV3)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 10.2.1 VSUP -- Voltage Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 10.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 10.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 10.4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

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Chapter 11 Timer Module (TIM16B4CV3) Block Description
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 11.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 11.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 11.2.1 IOC3 - IOC0 -- Input Capture and Output Compare Channel 3-0 . . . . . . . . . . . . . . . . 443
11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 11.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 11.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 11.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
11.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
11.6.1 Channel [3:0] Interrupt (C[3:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 11.6.2 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Chapter 12 Timer Module (TIM16B2CV3) Block Description
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 12.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 12.2.1 IOC1 - IOC0 -- Input Capture and Output Compare Channel 1-0 . . . . . . . . . . . . . . . . 461
12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 12.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 12.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 12.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
12.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
12.6.1 Channel [1:0] Interrupt (C[1:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 12.6.2 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
Chapter 13 Scalable Controller Area Network (S12MSCANV3)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 13.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

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13.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 13.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 13.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 13.2.1 RXCAN -- CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 13.2.2 TXCAN -- CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 13.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 13.3.3 Programmer's Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 13.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 13.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 13.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 13.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 13.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 13.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 13.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 13.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 13.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 13.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Chapter 14
Programmable Trigger Unit (PTUV3)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 14.2.1 PTUT0 -- PTU Trigger 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 14.2.2 PTUT1 -- PTU Trigger 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 14.2.3 PTURE -- PTUE Reload Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 14.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 14.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 14.4.2 Memory based trigger event list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 14.4.3 Reload mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 14.4.4 Async reload event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 14.4.5 Interrupts and error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 14.4.6 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

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Chapter 15
Pulse Width Modulator with Fault Protection (PMF15B6C00.17)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
15.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 15.2.1 PWM0­PWM5 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 15.2.2 FAULT0­FAULT5 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 15.2.3 IS0­IS2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 15.2.4 Global Load OK Signal -- glb_ldok . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 15.2.5 Commutation Event Signal -- async_event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 15.2.6 Commutation Event Edge Select Signal -- async_event_edge_sel[1:0] . . . . . . . . . . . 565 15.2.7 PWM Reload Event Signals -- pmf_reloada,b,c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 15.2.8 PWM Reload-Is-Asynchronous Signal -- pmf_reload_is_async . . . . . . . . . . . . . . . . . 565
15.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 15.4.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 15.4.2 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 15.4.3 PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 15.4.4 Independent or Complementary Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 15.4.5 Deadtime Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 15.4.6 Top/Bottom Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 15.4.7 Asymmetric PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 15.4.8 Variable Edge Placement PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 15.4.9 Double Switching PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 15.4.10Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 15.4.11Software Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 15.4.12PWM Generator Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 15.4.13Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
15.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 15.6 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 15.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 15.8 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
15.8.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 15.8.2 BLDC 6-Step Commutation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
Chapter 16
Serial Communication Interface (S12SCIV6)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 16.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 16.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

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16.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 16.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 16.2.1 TXD -- Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 16.2.2 RXD -- Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 16.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 16.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 16.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 16.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 16.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 16.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 16.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 16.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 16.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 16.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 16.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 16.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 16.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 16.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 16.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
Chapter 17
Serial Peripheral Interface (S12SPIV5)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 17.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 17.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 17.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 17.2.1 MOSI -- Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 17.2.2 MISO -- Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 17.2.3 SS -- Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 17.2.4 SCK -- Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
17.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 17.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 17.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 17.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 17.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 17.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

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17.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 17.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Chapter 18 Gate Drive Unit (GDU)
18.1 Differences GDUV4 vs GDUV5 vs GDUV6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 18.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701 18.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 18.2.1 HD -- High-Side Drain Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 18.2.2 VBS[2:0] -- Bootstrap Capacitor Connection Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 18.2.3 HG[2:0] -- High-Side Gate Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 18.2.4 HS[2:0] -- High-Side Source Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 18.2.5 VLS[2:0] -- Voltage Supply for Low-Side Pre-Drivers . . . . . . . . . . . . . . . . . . . . . . . . 703 18.2.6 LG[2:0] -- Low-Side Gate Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 18.2.7 LD[2:0] -- Low-Side Gate Pins (only on GDUV6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 18.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 18.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 18.4.2 Low-Side FET Pre-Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 18.4.3 High-Side FET Pre-Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 18.4.4 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 18.4.5 Desaturation Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 18.4.6 Phase Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 18.4.7 Fault Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 18.4.8 Current Sense Amplifier and Overcurrent Comparator . . . . . . . . . . . . . . . . . . . . . . . . . 738 18.4.9 GDU DC Link Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 18.4.10Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 18.4.11Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
18.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 18.5.1 FET Pre-Driver Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 18.5.2 GDU Intrinsic Dead Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 18.5.3 Calculation of Bootstrap Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 18.5.4 On Chip GDU tdelon and tdeloff Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Chapter 19 LIN/HV Physical Layer (S12LINPHYV3)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 19.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 19.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 19.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

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19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 19.2.1 LIN -- LIN Bus Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 19.2.2 LGND -- LIN Ground Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 19.2.3 VLINSUP -- Positive Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 19.2.4 LPTxD -- LIN Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 19.2.5 LPRxD -- LIN Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 19.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 19.4.2 Slew Rate and LIN Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 19.4.3 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 19.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
19.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 19.5.1 Module Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 19.5.2 Interrupt handling in Interrupt Service Routine (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Chapter 20
Flash Module (S12ZFTMRZ)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 20.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 20.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 20.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780 20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784 20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 20.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 20.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 20.4.3 Flash Block Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806 20.4.4 Internal NVM resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 20.4.5 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 20.4.6 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 812 20.4.7 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 20.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 20.4.9 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 20.4.10Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 20.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 20.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 20.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 831 20.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 831 20.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832

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Chapter 21
CAN Physical Layer (S12CANPHYV3)
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 21.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 21.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 21.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 21.2.1 CANH -- CAN Bus High Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 21.2.2 CANL -- CAN Bus Low Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 21.2.3 SPLIT -- CAN Bus Termination Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 21.2.4 VDDC -- Supply Pin for CAN Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 21.2.5 VSSC -- Ground Pin for CAN Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
21.3 Internal Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 21.3.1 CPTXD -- TXD Input to CAN Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 21.3.2 CPRXD -- RXD Output of CAN Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
21.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 21.4.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 21.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
21.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 21.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 21.5.2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 21.5.3 Configurable Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 21.5.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
21.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 21.6.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 21.6.2 Wake-up Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 21.6.3 Bus Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 21.6.4 CPTXD-Dominant Timeout Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
Chapter 22
Pulse-Width Modulator (S12PWM8B8CV2)
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 22.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 22.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 22.2.1 PWM7 - PWM0 -- PWM Channel 7 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
22.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 22.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 22.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
22.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880

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22.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
Appendix A MCU Electrical Specifications
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 A.2 General Purpose I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896 A.3 Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898 A.4 ADC Calibration Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Appendix B CPMU Electrical Specifications (VREG, OSC, IRC, PLL)
B.1 VREG Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903 B.2 Reset and Stop Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905 B.3 IRC and OSC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 B.4 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
Appendix C ADC Electrical Specifications
C.1 ADC Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
Appendix D LIN/HV PHY Electrical Specifications
D.1 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917 D.2 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
Appendix E GDU Electrical Specifications
E.1 GDU specifications for devices featuring GDU V4 or V6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 E.2 GDU specifications for devices featuring GDU V5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
Appendix F NVM Electrical Parameters
F.1 NVM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 F.2 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936 F.3 NVM Factory Shipping Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
Appendix G BATS Electrical Specifications
G.1 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937 G.2 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938

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Appendix H S12CANPHY Electrical Specifications
H.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 H.2 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 H.3 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Appendix I SPI Electrical Specifications
I.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
Appendix J MSCAN Electrical Specifications
J.1 MSCAN Wake-up Pulse Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Appendix K Package Information
K.1 48LQFP-EP Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 K.2 64LQFP-EP Mechanical Info (all mask sets except 1N95G, 2N95G) . . . . . . . . . . . . . . . . . . . . . 955 K.3 64LQFP-EP Mechanical Information (mask sets 1N95G, 2N95G) . . . . . . . . . . . . . . . . . . . . . . . 959 K.4 80LQFP-EP Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
Appendix L Ordering Information
Appendix M Detailed Register Address Map
M.1 0x0000­0x0003 Part ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 M.2 0x0010­0x001F S12ZINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 M.3 0x0070-0x00FF S12ZMMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 M.4 0x0100-0x017F S12ZDBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 M.5 0x0200-0x02FF PIM (See footnotes for part specific information) . . . . . . . . . . . . . . . . . . . . . . . 973 M.6 0x0380-0x039F FTMRZ128K512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979 M.7 0x03C0-0x03CF SRAM_ECC_32D7P. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 M.8 0x0400-0x042F TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982 M.9 0x0480-0x04AF PWM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 M.10 0x0500-x053F PMF15B6C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 M.11 0x0580-0x059F PTU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989 M.12 0x05C0-0x05FF TIM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 M.13 0x0600-0x063F ADC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993 M.14 0x0640-0x067F ADC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995 M.15 0x06A0-0x06BF GDU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997 M.16 0x06C0-0x06DF CPMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998 M.17 0x06F0-0x06F7 BATS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000

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M.18 0x0700-0x0707 SCI0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 M.19 0x0710-0x0717 SCI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001 M.20 0x0780-0x0787 SPI0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 M.21 0x0800­0x083F CAN0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 M.22 0x0980-0x0987 LINPHY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004 M.23 0x0990-0x0997 CANPHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004

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Chapter 1 Device Overview MC9S12ZVM-Family

Version Revision

Number

Date

1.8 04.Sep.2014 2.0 10.Oct.2014 2.01 06.Feb.2015

Sections Affected
Section 1.2.1 General General

2.02 25.Aug.2016 Figure 1-6, Table 1-8
Section 1.13.3.6

2.03 22.Aug.2017

Table 1-4

Table 1-1. Revision History
Description of Changes
· Added S12ZVML31 information to derivative table · Added ZVMC256 information · Added 2N95G maskset information. · Added TIM1 for ZVMC256 · Clarified IOC0 device pin mapping dependencies · Clarified IOC0 device pin mapping dependencies · Removed Temperature Sensor from list of Dynamic motor control fault inputs · Extended "N95G Option Table"

1.1 Introduction
The MC9S12ZVM-Family is an automotive 16-bit microcontroller family using the NVM + UHV technology that offers the capability to integrate 40 V analog components. This family reuses many features from the existing S12/S12X portfolio. The particular differentiating features of this family are the enhanced S12Z core, the combination of dual-ADC synchronized with PWM generation and the integration of "high-voltage" analog modules, including the voltage regulator (VREG), Gate Drive Unit (GDU), and either Local Interconnect Network (LIN) physical layer or CAN Physical layer. These features enable a fully integrated single chip solution to drive up to 6 external power MOSFETs for BLDC or PMSM motor drive applications.
The MC9S12ZVM-Family includes error correction code (ECC) on RAM and flash memory, EEPROM for diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase locked loop (IPLL) that improves the EMC performance. The MC9S12ZVM-Family allows the integration of several key system components into a single device, optimizing system architecture and achieving significant space savings. The MC9S12ZVM-Family delivers all the advantages and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of existing S12(X) families. The MC9S12ZVM-Family is available in different pin-out options, using 80-pin, 64-pin and 48-pin LQFP-EP packages to accommodate LIN, CAN and external PWM based application interfaces. In addition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes.
The MC9S12ZVM-Family is a general-purpose family of devices suitable for a range of applications, including:
· 3-phase sensorless BLDC motor control for
-- Fuel pump

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Chapter 1 Device Overview MC9S12ZVM-Family
-- Water pump -- Oil pump -- A/C compressor -- HVAC blower -- Engine cooling fan -- Electric vehicle battery cooling fan · Brush DC motor control requiring driving in 2 directions, along with PWM control for -- Reversible wiper -- Trunk opener
1.2 Features
This section describes the key features of the MC9S12ZVM-Family. It documents the superset of features within the family. Some module versions differ from one part to another within the family. Section 1.2.1 MC9S12ZVM-Family Member Comparison provides information to help access the correct information for a particular part within the family.
1.2.1 MC9S12ZVM-Family Member Comparison
Table 1-2 provides a summary of feature set differences within the MC9S12ZVM-Family.

Table 1-2. S12ZVM Family Feature Set Differences

Feature ZVMC256 ZVML128 ZVMC128 ZVML64 ZVMC64 ZVML32 ZVML31 ZVML31 ZVM32 ZVM32 ZVM16 ZVM16

Flash EEPROM
RAM Package LINPHY HVPHY SCI SPI ADC channels PMF channels TIM channels PWM channels

256 KB 128 KB 128 KB 1 KB 512 Bytes 512 Bytes

32 KB 80 pin
­ ­ 2 1 8+8

8 KB 64 pin
1 ­ 2 1 4+5

8 KB 64 pin
­ ­ 2 1 4+5

6

6

6

4 TIM0 +

4

4

2 TIM1

8

­

­

64 KB 512 Bytes 4 KB
64 pin 1 ­ 2 1
4+5
6
4
­

64 KB 512 Bytes 4 KB
64 pin ­ ­ 2 1
4+5
6
4
­

32 KB 512 Bytes 4 KB
64 pin 1 ­ 2 1
4+5
6
4
­

32 KB 128 Bytes 4 KB
64 pin 1 ­ 2 1
4+5
6
4
­

32 KB 128 Bytes 4 KB
48 pin 1 ­ 2 0
1+3

32 KB 32 KB 16 KB 16 KB

128 128 128 128 Bytes Bytes Bytes Bytes

4 KB 4 KB 2 KB 2 KB

64 pin 48 pin 64 pin 48 pin

­

­

­

­

1

1

1

1

2

2

2

2

1

0

1

0

4+5 1+3 4+5 1+3

6

6

6

6

6

3

4

3

4

3

­

­

­

­

­

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Table 1-2. S12ZVM Family Feature Set Differences

Feature ZVMC256 ZVML128 ZVMC128 ZVML64 ZVMC64 ZVML32 ZVML31 ZVML31 ZVM32 ZVM32 ZVM16 ZVM16

MSCAN
CAN VREG
CANPHY
External FET gate charge
GDU external bootstrap diode
Current sense op-amps
Auxiliary tracker VREGs

1 1 1
Needed
2 2

1 ­ ­
Needed
2 ­

1

1

1

1

­

­

­

­

­

­

1

­

1

­

­

­

­

­

­

­

­

­

­

­

­

­

­

­

­

­

Standard + 50%

Standard

Needed

Needed Needed Needed Not

Not

Not Not Not Not

Needed Needed Neede Neede Neede Neede

d

d

d

d

2

2

2

2

2

1

2

1

2

1

­

­

­

­

­

­

­

­

­

­

1.2.2 Module Version Differences Within The S12ZVM Family
Table 1-3 provides a summary of module version differences within the MC9S12ZVM-Family. The differences between the module versions are summarized in the individual module chapters. Modules that are not listed in this table have identical versions across all MC9S12ZVM-Family members.
Table 1-3. S12ZVM Module Version Table

Feature

ZVMC25 6

ZVML12 8

ZVMC12 8

ZVML64

ZVMC64

ZVML32

ZVML31

ZVM32

ZVM16

PIM

V3

CPMU_UH V10 V

PMF

V4

GDU

V6

DBG

V4

ADC

V3

V2

V2

V2

V2

V2

V2

V2

V2

V6

V6

V6

V6

V6

V6

V6

V6

V3 V4(1) V2 V1

V3 V4 (1)
V2 V1

V3 V4 (1)
V2 V1

V3 V4 (1)
V2 V1

V3 V4 (1)
V2 V1

V4

V4

V4

V5

V5

V5

V3 (Lite) V3 (Lite) V3 (Lite)

V1

V1

V1

1. Mask set differences listed in Section 1.2.3

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1.2.3 Functional Differences Between Masksets

The parts ZVML128, ZVMC128, ZVML64, ZVMC64 and ZVML32 have the following mask set options.
CAUTION The maskset 2N95G uses the VSUP pin as the LINPHY supply. Thus the BST function must not be used on this maskset because enabling it could cause a LINPHY supply voltage
offset with respect to other devices on the LIN bus. Further GDU configuration mask set dependencies are specified in Table 1-19.
Table 1-4. N95G Option Table

Feature LINPHY supply pin BST pin function available GDU low side driver state in HD over-voltage case Current Sense Amplifier and Overcurrent Comparator independent enable 1. 0N95G is not a production mask set

0N95G(1) HD Yes on No

1N95G HD Yes
GOCA1 Yes

2N95G VSUP
No GOCA1
Yes

3N95G HD Yes
GOCA1 Yes

1.3 Chip-Level Features
On-chip modules available within the family include the following features: · S12Z CPU core · 256, 128, 64, 32 or 16KB on-chip flash with ECC · 1K, 512 or 128 byte EEPROM with ECC · 32, 8, 4 or 2 KB on-chip SRAM with ECC · Phase locked loop (IPLL) frequency multiplier with internal filter · 1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range · 4-20MHz amplitude controlled pierce oscillator · Internal COP (watchdog) module · 6-channel, 15-bit pulse width modulator with fault protection (PMF) · Low side and high side FET pre-drivers for each phase -- Gate drive pre-regulator -- LDO (Low Dropout Voltage Regulator) (typically 11V) -- High side gate supply generated using bootstrap circuit with external diode and capacitor -- Sustaining charge pump with two external capacitors and diodes -- High side drain (HD) monitoring on internal ADC channel using HD/5 voltage · Two parallel analog-to-digital converters (ADC) with 12-bit resolution and up to 16 channels available on external pins · Programmable Trigger Unit (PTU) for synchronization of PMF and ADC · One serial peripheral interface (SPI) module

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· One serial communication interface (SCI) module with interface to internal LIN physical layer transceiver (with RX connected to a timer channel for frequency calibration purposes, if desired)
· Up to one additional SCI (not connected to LIN physical layer) · On-chip LIN physical layer transceiver fully compliant with the LIN 2.2 standard
(S12ZVML versions) · One High Voltage physical interface. (ZVM32, ZVM16 versions only) · 4-channel timer module (TIM0) with input capture/output compare · 2-channel timer module (TIM1) with input capture/output compare (ZVMC256 version only) · One 8-bit, 8-channel pulse width modulator (PWM) module. (ZVMC256 version only) · MSCAN (1 Mbit/s, CAN 2.0 A, B software compatible) module · On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages
-- Optional VREG ballast control output to supply an external CAN physical layer · CAN Physical Layer, ISO 11898-2 and ISO 11898-5 compliant. (ZVMC256 version only) · Two voltage regulator outputs to supply external loads. (ZVMC256 version only) · Two current sense circuits for overcurrent detection or torque measurement · Autonomous periodic interrupt (API) · 20mA high-current output for use as Hall sensor supply · Supply voltage sense with low battery warning · Chip temperature sensor · One High Voltage Input (ZVMC256 version only)
1.4 Module Features
The following sections provide more details of the integrated modules.
1.4.1 S12Z Central Processor Unit (CPU)
The S12Z CPU is a revolutionary high-speed core, with code size and execution efficiencies over the S12X CPU. The S12Z CPU also provides a linear memory map eliminating the inconvenience and performance impact of page swapping.
· Harvard Architecture - parallel data and code access · 3 stage pipeline · 32-Bit wide instruction and databus · 32-Bit ALU · 24-bit addressing, of 16MB linear address space · Instructions and Addressing modes optimized for C-Programming & Compiler
-- MAC unit 32bit += 32bit*32bit -- Hardware divider -- Single cycle multi-bit shifts (Barrel shifter)

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-- Special instructions for fixed point math · Unimplemented opcode traps · Unprogrammed byte value (0xFF) defaults to SWI instruction

1.4.1.1 Background Debug Controller (BDC)
· Background debug controller (BDC) with single-wire interface -- Non-intrusive memory access commands -- Supports in-circuit programming of on-chip nonvolatile memory

1.4.1.2

Debugger (DBG) ZVML31, ZVM32, ZVM16 feature subset listed in S12ZDBG chapter

· Enhanced DBG module including: -- Four comparators (A, B, C and D) each configurable to monitor PC addresses or addresses of data accesses -- A and C compare full address bus and full 32-bit data bus with data bus mask register -- B and D compare full address bus only -- Three modes: simple address/data match, inside address range, or outside address range -- Tag-type or force-type hardware breakpoint requests
· State sequencer control · 64 x 64-bit circular trace buffer to capture change-of-flow addresses or address and data of every
access -- Begin, End and Mid alignment of tracing to trigger · Profiling mode for external visibility of internal program flow

1.4.2 Embedded Memory

1.4.2.1 Memory Access Integrity
· Illegal address detection · ECC support on embedded NVM and system RAM

1.4.2.2 Flash
On-chip flash memory on the MC9S12ZVM-family on the features the following: · Up to 256KB of program flash memory -- 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit fault correction and double fault detection -- Erase sector size 512 bytes -- Automated program and erase algorithm -- User margin level setting for reads

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-- Protection scheme to prevent accidental program or erase
1.4.2.3 EEPROM
· Up to 1K byte EEPROM -- 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection -- Erase sector size 4 bytes -- Automated program and erase algorithm -- User margin level setting for reads
1.4.2.4 SRAM
· Up to 32 KB of general-purpose RAM with ECC -- Single bit error correction and double bit error detection
1.4.3 Clocks, Reset & Power Management Unit (CPMU)
· Real time interrupt (RTI) · Clock monitor, supervising the correct function of the oscillator (CM) · Computer operating properly (COP) watchdog
-- Configurable as window COP for enhanced failure detection -- Can be initialized out of reset using option bits located in flash memory · System reset generation · Autonomous periodic interrupt (API) (combination with cyclic, watchdog) · Low Power Operation -- RUN mode is the main full performance operating mode with the entire device clocked. -- WAIT mode when the internal CPU clock is switched off, so the CPU does not execute
instructions. -- Pseudo STOP - system clocks are stopped but the oscillator the RTI, the COP, and API modules
can be enabled -- STOP - the oscillator is stopped in this mode, all clocks are switched off and all counters and
dividers remain frozen, with the exception of the COP and API which can optionally run from ACLK.
1.4.3.1 Internal Phase-Locked Loop (IPLL)
· Phase-locked-loop clock frequency multiplier -- No external components required -- Reference divider and multiplier allow large variety of clock rates -- Automatic bandwidth control mode for low-jitter operation -- Automatic frequency lock detector

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-- Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) -- Reference clock sources:
­ Internal 1 MHz RC oscillator (IRC) ­ External 4-20 MHz crystal oscillator/resonator
1.4.3.2 Internal RC Oscillator (IRC) · Trimmable internal 1MHz reference clock. -- Trimmed accuracy over -40C to 150C junction temperature range: 1.3%max.
1.4.4 Main External Oscillator (XOSCLCP)
· Amplitude controlled Pierce oscillator using 4 MHz to 20 MHz crystal -- Current gain control on amplitude output -- Signal with low harmonic distortion -- Low power -- Good noise immunity -- Eliminates need for external current limiting resistor -- Trans conductance sized for optimum start-up margin for typical crystals -- Oscillator pins shared with GPIO functionality
1.4.5 Timer (TIM0)
· 4 x 16-bit channels Timer module for input capture or output compare · 16-bit free-running counter with 8-bit precision prescaler
1.4.6 Timer (TIM1) (ZVMC256 only)
· 2 x 16-bit channels Timer module for input capture or output compare · 16-bit free-running counter with 8-bit precision prescaler
1.4.7 Pulse width Modulator with Fault protection (PMF)
· 6 x 15-bit channel PWM resolution · Each pair of channels can be combined to generate a PWM signal (with independent control of
edges of PWM signal) · Dead time insertion available for each complementary pair · Center-aligned or edge-aligned outputs · Programmable clock select logic with a wide range of frequencies · Programmable fault detection

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1.4.8 Programmable Trigger Unit (PTU)
· Enables synchronization between PMF and ADC · 2 trigger input sources and software trigger source · 2 trigger outputs · One 16-bit delay register pre-trigger output · Operation in One-Shot or Continuous modes

Chapter 1 Device Overview MC9S12ZVM-Family

1.4.9 LIN physical layer transceiver (ZVML devices only)
· Compliant with LIN Physical Layer 2.2 specification. · Compliant with the SAE J2602-2 LIN standard. · Standby mode with glitch-filtered wake-up. · Slew rate selection optimized for the baud rates: 10.4kBit/s, 20kBit/s and Fast Mode (up to
250kBit/s). · Switchable 34k/330k pull-ups (in shutdown mode, 330k only) · Current limitation for LIN Bus pin falling edge. · Over-current protection. · LIN TxD-dominant timeout feature monitoring the LPTxD signal. · Automatic transmitter shutdown in case of an over-current or TxD-dominant timeout. · Fulfills the OEM "Hardware Requirements for LIN (CAN and FlexRay) Interfaces in Automotive
Applications" v1.3.

1.4.10 Serial Communication Interface Module (SCI)
· Full-duplex or single-wire operation · Standard mark/space non-return-to-zero (NRZ) format · Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths · 16-bit baud rate selection · Programmable character length · Programmable polarity for transmitter and receiver · Active edge receive wakeup · Break detect and transmit collision detect supporting LIN

1.4.11 Multi-Scalable Controller Area Network (MSCAN)
· Implementation of the CAN protocol -- Version 2.0A/B · Five receive buffers with FIFO storage scheme · Three transmit buffers with internal prioritization using a "local priority" concept · Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four
16-bit filters, or either 8-bit filters

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· Programmable wake-up functionality with integrated low-pass filter

1.4.12 Serial Peripheral Interface Module (SPI)
· Configurable 8- or 16-bit data size · Full-duplex or single-wire bidirectional · Double-buffered transmit and receive · Master or slave mode · MSB-first or LSB-first shifting · Serial clock phase and polarity options

1.4.13 Analog-to-Digital Converter Module (ADC)
· Dual ADC -- 12-bit resolution -- Up to 16 external channels & 8 internal channels -- 2.5us for single 12-bit resolution conversion -- Left or right aligned result data -- Continuous conversion mode
· Programmers model with list based command and result storage architecture ADC directly writes results to RAM, preventing stall of further conversions
· Internal signals monitored with the ADC module -- VRH, VRL, (VRL+VRH)/2, Vsup monitor, Vbg, TempSense, GDU phase, GDU DC-link
· External pins can also be used as digital I/O

1.4.14 Supply Voltage Sensor (BATS)
· Monitoring of supply (VSUP) voltage · Internal ADC interface from an internal resistive divider · Generation of low or high voltage interrupts

1.4.15 On-Chip Voltage Regulator system (VREG)
· Voltage regulator -- Linear voltage regulator directly supplied by VSUP -- Low-voltage detect on VSUP -- Power-on reset (POR) -- Low-voltage reset (LVR) for VDDX domain -- External ballast device support to reduce internal power dissipation -- Capable of supplying both the MCU internally plus external components -- Over-temperature interrupt

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· Internal voltage regulator -- Linear voltage regulator with bandgap reference -- Low-voltage detect on VDDA -- Power-on reset (POR) circuit -- Low-voltage reset for VDD domain
· Package option for VREG ballast control output to supply external CANPHY · Option for 2 further VREG ballast control outputs to supply external components (ZVMC256)
1.4.16 Gate Drive Unit (GDU)
· Low side and high side FET pre-drivers for each phase · Gate drive pre-regulator LDO (Low Dropout Voltage Regulator) · High side gate supply done via bootstrap circuit · External bootstrap diode replaced by internal circuit (GDUV5 only) · Sustaining charge pump with two external capacitors and diodes · Optional boost converter configuration with voltage feedback · FET-Predriver desaturation and error recognition · Monitoring of FET High Side drain (HD) voltage · Diagnostic failure management · Low side drain pins for monitoring desaturation of switch reluctance motor drivers (ZVMC256)
1.4.17 Current Sense
· 2 channel, integrated op-amp functionality
1.4.18 High Voltage Physical Interface (ZVM32, ZVM16)
· Single pin high voltage interface signal operating in the VSUP voltage range · Internal interface mapped to internal timer channel. · Compliant with the ISO9141 (K-line) standard. · Standby mode with glitch-filtered wake-up. · Slew rate selection optimized for: 5.2 kHz, 10 kHz and Fast Mode (up to 125 kHz). · Switchable 34 k/330 k pullup resistors (in shutdown mode, 330 konly · Current limitation for pin falling edge. · Overcurrent protection.
1.4.19 CAN Physical Layer Module (ZVMC256 only)
· High speed CAN interface for baud rates of up to 1 Mbit/s · ISO 11898-2 and ISO 11898-5 compliant for 12 V battery systems

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· SPLIT pin driver for bus recessive level stabilization · Low power mode with remote CAN wake-up handled by MSCAN module · Configurable wake-up pulse filtering · Over-current shutdown for CANH and CANL · Voltage monitoring on CANH and CANL · CPTXD-dominant timeout feature monitoring the CPTXD signal · Fulfills the OEM "Hardware Requirements for (LIN,) CAN (and FlexRay) Interfaces in
Automotive Applications" v1.3
1.4.20 Pulse Width Modulation Module (PWM) (ZVMC256 only)
· Configurable as 8 channels x 8-bit or 4 channels x 16-bit · Programmable period and duty cycle per channel · Center-aligned or edge-aligned outputs · Programmable clock select logic with a wide range of frequencies

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5V Analog Supply VDDA/VSSA
VDD VSS2 VDDF VSS1 VDDX1/VDDX2 VSUP BCTL VDDS1 BCTLS1 SNPS1 VDDS2 BCTLS2 SNPS2
BKGD
PE0 PE1
RESET TEST
LIN0 LGND BCTLC VDDC CANH0 SPLIT0 CANL0 VSSC PL0

PTE

32K, 64K, 128K, 256KB Flash with ECC

ADC0 12-bit Analog-Digital

AN0_[7:0]

Converter

VRH VRL

ADC1 12-bit Analog-Digital

AN1_[7:0]

Converter

VRH VRL

2K, 4K, 8K, 32KB RAM with ECC

AMPP0 AMPM0
AMP0

1K, 512 bytes EEPROM with ECC

AMPP1 AMPM1 Current Sense Circuits AMP1

Voltage Regulator (Nominal 12V)

GDU

HD

Gate Drive Unit

CP

VCP

VLS_OUT

Additional Voltage Regulator #1

BST VSSB

VBS[2:0]

Additional Voltage Regulator #2

HG[2:0] HS[2:0]

BATS Voltage Supply Monitor

VLS[2:0] LG[2:0] LS[2:0]

S12ZCPU

LD[2:0]

Interrupt Module

DBG Debug Module

PMF 15-bit Pulse

6 channel Width Modulator

PWM1_0 PWM1_1 PWM1_2

BDC Background Debug Controller

4 Comparators Trace Buffer

PWM1_3 PWM1_4 PWM1_5

EXTAL Low Power Pierce
XTAL Oscillator

Clock Monitor COP Watchdog Real Time Interrupt Auton. Periodic Int.

PLL with Frequency Modulation option

Internal RC Oscillator

TIM0

IOC0_0

16-bit 4-Channel Timer IOC0_1

IOC0_2

IOC0_3

PTU

PTURE

Programmable Trigger PTUT0

Reset Generation and Test Entry

Unit

PTUT1

LINPHY0 (S12ZVML versions only) OR HV Physical Interface
LIN0 LGND
CAN VREG

CANH0 SPLIT0 CANL0 VSSC

CANPHY0

High Voltage Input HV0

SCI1

RXD1

Asynchronous Serial IF TXD1

SCI0

RXD0

Asynchronous Serial IF TXD0

CAN0

RXCAN0

msCAN 2.0B

TXCAN0

SPI0

MISO0

MOSI0

SCK0 Synchronous Serial IF SS0

PWM0

PWM0_[7,5,3,1]

8-bit, 8-channel

Pulse Width Modulator

TIM1

IOC1_0

16-bit 2-Channel Timer IOC1_1

PTS / KWS

PTT

PTP / KWP

PTAD / KWAD

PAD[7:0]
PAD[15:8]
HD CP VCP VLS_OUT BST VSSB VBS[2:0] HG[2:0] HS[2:0] VLS[2:0] LG[2:0] LS[2:0] LD[2:0] PP0 PP1 PP2
PT0 PT1 PT2 PT3
PS0 PS1 PS2 PS3 PS4 PS5

PTL/KWL

Block Diagram shows the maximum configuration Not all pins or all peripherals are available on all devices and packages. Red highlighted features are ZVMC256 specific.
Rerouting options are not shown.
Figure 1-1. MC9S12ZVM-Family Block Diagram

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1.6 Device Memory Map

Table 1-5 shows the device register memory map. All modules that can be instantiated more than once on S12 devices are listed with an index number, even if they are only instantiated once on this device family.
Table 1-5. Module Register Address Ranges

Address
0x0000­0x0003 0x0004­0x000F 0x0010­0x001F 0x0020­0x006F 0x0070­0x008F 0x0090­0x00FF 0x0100­0x017F 0x0180­0x01FF 0x0200­0x033F 0x0340­0x037F 0x0380­0x039F 0x03A0­0x03BF 0x03C0­0x03CF 0x03D0­0x03FF 0x0400­0x043F 0x0440­0x047F 0x0480­0x04AF 0x04B0­0x04FF 0x0500­0x053F 0x0540­0x057F 0x0580­0x059F 0x05A0­0x05BF 0x05C0­0x05EF 0x05F0­0x05FF 0x0600­0x063F 0x0640­0x067F 0x0680­0x069F (2)0x06A0­0x06BF 0x06C0­0x06DF

Module
Part ID Register Section 1.6.2 Reserved INT Reserved MMC
MMC Reserved DBG
Reserved PIM
Reserved FTMRZ Reserved RAM ECC Reserved TIM1 (ZVMC256 only) Reserved PWM0 (ZVMC256 only) Reserved(1)
PMF Reserved
PTU Reserved
TIM0 Reserved
ADC0 ADC1 Reserved GDU CPMU

Size (Bytes)
4 12 16 80 32 112 128 128 320 64 32 32 16 48 64 64 48 80 64 64 32 32 48 16 64 64 32 32 32

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Table 1-5. Module Register Address Ranges

Address

Module

Size (Bytes)

0x06E0­0x06EF

Reserved

16

0x06F0­0x06F7

BATS

8

0x06F8­0x06FF

Reserved

8

0x0700­0x0707

SCI0

8

0x0708­0x070F

Reserved

8

0x0710­0x0717

SCI1

8

0x0718­0x077F

Reserved

104

0x0780­0x0787

SPI0

8

0x0788­0x07FF

Reserved

120

0x0800­0x083F

CAN0

64

0x0840­0x097F

Reserved

320

0x0980­0x0987

LINPHY (S12ZVML derivatives)

8

0x0980­0x0987

HV Physical Interface

8

(S12ZVM32, S12ZVM16 derivatives)

0x0988­0x098F

Reserved

8

0x0990­0x0997

CANPHY (ZVMC256 only)

8

0x0998­0x0FFF

Reserved

1640

1. Reading from the first 16 locations in this reserved range returns undefined data

2. Address range = 0x0690-0x069F on Maskset N06E

NOTE Reserved register space shown above is not allocated to any module. This register space is reserved for future use. Writing to these locations has no effect. Read access to these locations returns zero.
1.6.1 Flash Module
This device family instantiates different flash modules, depending on derivative. The flash documentation for the all devices is featured in the FTMRZ section.

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Register Space
4 KB

RAM
max. 1 MByte - 4 KB
EEPROM
max. 1 MByte - 48 KB
Reserved
Reserved (read only)
NVM IFR

0x00_0000 0x00_1000
0x10_0000
512 Byte 0x1F_4000 6 KB 0x1F_8000
256 Byte 0x1F_C000 0x20_0000

Unmapped
6 MByte

0x80_0000

Program NVM
max. 8 MB

Unmapped address range Low address aligned

High address aligned

0xFF_FFFF

Figure 1-2. MC9S12ZVM-Family Global Memory Map. (See Table 1-3 for individual device details)

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1.6.2 Part ID Assignments
The part ID is located in four 8-bit registers at addresses 0x0000-0x0003. The read-only value is a unique part ID for each revision of the chip. Table 1-6 shows the assigned part ID number and mask set number. The shaded part ID numbers are not production mask sets.
Table 1-6. Assigned Part ID Numbers

Device
MC9S12ZVMC256 MC9S12ZVMC256 MC9S12ZVML12 MC9S12ZVMC12 MC9S12ZVML12 MC9S12ZVMC12 MC9S12ZVML12 MC9S12ZVML64 MC9S12ZVML32 MC9S12ZVMC12 MC9S12ZVMC64 MC9S12ZVML12 MC9S12ZVML64 MC9S12ZVML32 MC9S12ZVMC12 MC9S12ZVMC64 MC9S12ZVML12 MC9S12ZVML64 MC9S12ZVML32 MC9S12ZVMC12 MC9S12ZVMC64 MC9S12ZVML31
MC9S12ZVM32 MC9S12ZVM16 MC9S12ZVML31 MC9S12ZVM32 MC9S12ZVM16

Mask Set Number
0N00R 1N00R N06E N06E 0N95G 0N95G 1N95G 1N95G 1N95G 1N95G 1N95G 2N95G 2N95G 2N95G 2N95G 2N95G 3N95G 3N95G 3N95G 3N95G 3N95G 0N14N 0N14N 0N14N 1N14N 1N14N 1N14N

Part ID
0x00180000 0x00180100 0x00170000 0x00170001 0x00172000 0x00172001 0x00172100 0x00172100 0x00172100 0x00172101 0x00172101 0x00172200 0x00172200 0x00172200 0x00172201 0x00172201 0x00172300 0x00172300 0x00172300 0x00172301 0x00172301 0x00150000 0x00150000 0x00150000 0x00150100 0x00150100 0x00150100

Option
CAN CAN LIN CAN-VREG LIN CAN-VREG LIN LIN LIN CAN-VREG CAN-VREG LIN LIN LIN CAN-VREG CAN-VREG LIN LIN LIN CAN-VREG CAN-VREG LIN HV Physical Interface HV Physical Interface LIN HV Physical Interface HV Physical Interface

1.7 Signal Description and Device Pinouts
This section describes signals that connect off-chip. It includes pin out diagrams a table of signal properties, and detailed discussion of signals. Internal inter module signal mapping at device level is described in 1.8 Internal Signal Mapping.

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1.7.1 Pin Assignment Overview
Table 1-7 provides a summary of which ports are available.

Port Port AD Port E Port L Port P Port S Port T sum of ports

Table 1-7. Port Availability by Option

80 LQFP PAD[15:0]
PE[1:0] PL[0] PP[1:0] PS[3:0] PT[3:0]
29

64 LQFP PAD[8:0] PE[1:0]
-- PP[2:0] PS[5:0] PT[3:0]
24

48LQFP PAD[8],PAD[2:0]
PE[1:0] --
PP[0] PS[1:0] PT[0]
10

NOTE To avoid current drawn from floating inputs, all non-bonded pins should be configured as output or configured as input with a pull up or pull down device enabled
1.7.2 Detailed External Signal Descriptions
This section describes the properties of signals available at device pins. Signal names associated with modules that can be instantiated more than once on an S12 are indexed, even if the module is only instantiated once on the MC9S12ZVM-Family. If a signal already includes a channel number, then the index is inserted before the channel number. Thus ANx_y corresponds to AN instance x, channel number y.
1.7.2.1 RESET -- External Reset Signal
The RESET signal is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has an internal pull-up device.
1.7.2.2 TEST -- Test Pin
This input only pin is reserved for factory test. This pin has an internal pull-down device.
NOTE The TEST pin must be tied to ground in all applications.

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1.7.2.3 MODC -- Mode C Signal The MODC signal is used as an MCU operating mode select during reset. The state of this signal is latched to the MODC bit at the rising edge of RESET. The signal has an internal pull-up device.
1.7.2.4 PAD[15:0] / KWAD[15:0] -- Port AD, Input Pins of ADC These are general-purpose input or output signals. The signals can be configured on per signal basis as interrupt inputs with wake-up capability (KWAD). These signals can have a pull-up or pull-down device selected and enabled on per signal basis. During and out of reset the pull devices are disabled.
1.7.2.5 PE[1:0] -- Port E I/O Signals PE[1:0] are general-purpose input or output signals. The signals can have a pull-down device, enabled by on a per pin basis. Out of reset the pull-down devices are enabled.
1.7.2.6 PL[0] -- Port L Input Signal PL[0] is a high voltage input port. The port can be configured as interrupt input with wake-up capability (KWL[0]). The input voltage is also scaled and mapped to an internal ADC channel.
1.7.2.7 PP[2:0] / KWP[2:0] -- Port P I/O Signals PP[2:0] are general-purpose input or output signals. The signals can be configured on per signal basis as interrupt inputs with wake-up capability (KWP[2:0]). They can have a pull-up or pull-down device selected and enabled on per signal basis. During and out of reset the pull devices are disabled.
1.7.2.8 PS[5:0] / KWS[5:0] -- Port S I/O Signals PS[5:0] are general-purpose input or output signals. The signals can be configured on per signal basis as interrupt inputs with wake-up capability (KWS[5:0]). They can have a pull-up or pull-down device selected and enabled on per signal basis. During and out of reset the pull-up devices are enabled.
1.7.2.9 PT[3:0] -- Port T I/O Signals PT[3:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. During and out of reset the pull devices are disabled.
1.7.2.10 AN0_[7:0], AN1_[7:0]-- ADC Input Signals These are the analog inputs of the Analog-to-Digital Converters. These are mapped to PAD port pins. The number of analog input channels connected to PAD port pins is package option dependent.
1.7.2.11 VRH0_[2:0], VRL0_[1:0] -- ADC0 Reference Signals VRH0_[2:0] and VRL0_[1:0] are the reference voltage signals for the analog-to-digital converter ADC0.

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1.7.2.12 VRH1_[2:0], VRL1_[1:0] -- ADC1 Reference Signals VRH1_[2:0] and VRL1_[1:0] are the reference voltage signals for the analog-to-digital converter ADC1.
1.7.2.13 SPI0 Signals
1.7.2.13.1 SS0 Signal This signal is associated with the slave select SS functionality of the serial peripheral interface SPI0.
1.7.2.13.2 SCK0 Signal This signal is associated with the serial clock SCK functionality of the serial peripheral interface SPI0.
1.7.2.13.3 MISO0 Signal This signal is associated with the MISO functionality of the serial peripheral interface SPI0. This signal acts as master input during master mode or as slave output during slave mode.
1.7.2.13.4 MOSI0 Signal This signal is associated with the MOSI functionality of the serial peripheral interface SPI0. This signal acts as master output during master mode or as slave input during slave mode
1.7.2.14 SCI[1:0] Signals
1.7.2.14.1 RXD[1:0] Signals These signals are associated with the receive functionality of the serial communication interfaces (SCI[1:0]).
1.7.2.14.2 TXD[1:0] Signals These signals are associated with the transmit functionality of the serial communication interfaces (SCI[1:0]).
1.7.2.15 CAN0 Signals
1.7.2.15.1 RXCAN0 Signal This signal is associated with the receive functionality of the scalable controller area network controller (MSCAN0).
1.7.2.15.2 TXCAN0 Signal This signal is associated with the transmit functionality of the scalable controller area network controller (MSCAN0).

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1.7.2.16 Timer IOC0_[3:0] Signals The signals IOC0_[3:0] are associated with the input capture or output compare functionality of the timer (TIM0) module.
1.7.2.17 Timer IOC1_[1:0] Signals (ZVMC256 only) The signals IOC1_[1:0] are associated with the input capture or output compare functionality of the timer (TIM1) module.
1.7.2.18 PWM1_[5:0] Signals The signals PWM1_[5:0] are associated with the PMF module digital channel outputs.
1.7.2.19 PWM0_[7,5,3,1] Signals (ZVMC256 only) The PWM0 signals are associated with the PWM0 module digital channel outputs.
1.7.2.20 PTU Signals
1.7.2.20.1 PTUT[1:0] Signals These signals are the PTU trigger output signals. These signals are routed to pins for debugging purposes.
1.7.2.20.2 PTURE Signal This signal is the PTU reload enable output signal. This signal is routed to a pin for debugging purposes.
1.7.2.21 Interrupt Signals -- IRQ and XIRQ IRQ is a maskable level or falling edge sensitive input. XIRQ is a non-maskable level-sensitive interrupt.
1.7.2.22 Oscillator and Clock Signals
1.7.2.22.1 Oscillator Pins -- EXTAL and XTAL EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the internal PLLCLK, independent of EXTAL and XTAL. XTAL is the oscillator output.
1.7.2.22.2 ECLK This signal is associated with the output of the bus clock (ECLK).
NOTE This feature is only intended for debug purposes at room temperature. It must not be used for clocking external devices in an application.

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1.7.2.23 BDC and Debug Signals
1.7.2.23.1 BKGD -- Background Debug signal The BKGD signal is used as a pseudo-open-drain signal for the background debug communication. The BKGD signal has an internal pull-up device.
1.7.2.23.2 PDO -- Profiling Data Output This is the profiling data output signal used when the DBG module profiling feature is enabled. This signal is output only and provides a serial, encoded data stream that can be used by external development tools to reconstruct the internal CPU code flow.
1.7.2.23.3 PDOCLK -- Profiling Data Output Clock This is the PDO clock signal used when the DBG module profiling feature is enabled. This signal is output only. During code profiling this is the clock signal that can be used by external development tools to sample the PDO signal.
1.7.2.23.4 DBGEEV -- External Event Input This signal is the DBG external event input. It is input only. Within the DBG module, it allows an external event to force a state sequencer transition, or trace buffer entry, or to gate trace buffer entries. A falling edge at the external event signal constitutes an event. Rising edges have no effect. The maximum frequency of events is half the internal core bus frequency.
1.7.2.24 FAULT5 -- External Fault Input This is the PMF fault input signal, with configurable polarity, that can be used to disable PMF operation when asserted. Asynchronous shutdown of the GDU outputs HG[2:0] and LG[2:0] is not supported. Select QSMPm[1:0] > 0 in PMF.
1.7.2.25 LIN Physical Layer Signals (Not Available On ZVMC256)
1.7.2.25.1 LIN0 On S12ZVML derivatives this pad is connected to the single-wire LIN data bus. On the S12ZVM32 and S12ZVM16 derivatives this is a single pin bidirectional high voltage physical interface. It operates in the VSUP voltage range. It can be connected to an external single-wire data bus.
1.7.2.25.2 LP0TXD This is the LIN physical layer (or HV physical interface) transmitter input signal.
1.7.2.25.3 LP0RXD This is the LIN physical layer (or HV physical interface) receiver output signal.

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1.7.2.25.4 LP0DR1 This is the LIN (or HV physical interface) LP0DR1 register bit, visible at the designated pin for debug purposes.
1.7.2.25.5 LGND -- LINPHY Ground Pin On S12ZVM(L) parts LGND is the ground pin for the LIN physical layer LINPHY. This signal must be connected to board ground, even if the LINPHY is not used. On S12ZVM32 and S12ZVM16 parts this the ground pin for the HV physical interface. It must be connected to board ground even when the HV physical interface is not used.
1.7.2.26 CAN Physical Layer Signals (ZVMC256 Only)
1.7.2.26.1 CANH0 -- CAN Bus High Pin0 The CANH0 signal either connects directly to CAN bus high line or through an optional external common mode choke.
1.7.2.26.2 CANL0 -- CAN Bus Low Pin0 The CANL0 signal either connects directly to CAN bus low line or through an optional external common mode choke.
1.7.2.26.3 SPLIT0 -- CAN Bus Termination Pin0 The SPLIT0 pin can drive a 2.5 V bias for bus termination purpose (CAN bus middle point). Usage of this pin is optional and depends on bus termination strategy for a given bus network.
1.7.2.26.4 CPTXD0 This is the CAN physical layer transmitter input signal.
1.7.2.26.5 CPRXD0 This is the CAN physical layer receiver output signal.
1.7.2.26.6 CPDR0 This is the CAN physical layer direct control output signal.
1.7.2.26.7 BCTLC BCTLC provides the base current of an external bipolar that supplies an external CAN physical interface. This signal is only available on S12ZVMC versions. If not used BCTLC should be left unconnected.

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1.7.2.26.8 VDDC (Only Available On S12ZVMC Versions) VDDC is the CANPHY supply. This is the output voltage of the external bipolar, whose base current is supplied by BCTLC. It is fed back to the MCU for regulation. A diode is recommended between VDDA and VDDC, whereby the anode is connected to VDDC.
1.7.2.26.9 VSSC (Only Available On ZVMC256) VSSC is the CANPHY ground.
1.7.2.27 Gate Drive Unit (GDU) Signals These are associated with driving the external FETs.
1.7.2.27.1 HD -- FET Predriver High side Drain Input This is the drain connection of the external high-side FETs. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC via an analog multiplexer.
1.7.2.27.2 VBS[2:0] - Bootstrap Capacitor Connections These signals are the bootstrap capacitor connections for phases HS[2:0]. The capacitor connected between HS[2:0] and these signals provides the gate voltage and current to drive the external FET.
1.7.2.27.3 HG[2:0] - High-Side Gate signals The pins are the gate drives for the three high-side power FETs. The drivers provide a high current with low impedance to turn on and off the high-side power FETs.
1.7.2.27.4 HS[2:0] - High-Side Source signals The pins are the source connection for the high-side power FETs and the drain connection for the low-side power FETs. The low voltage end of the bootstrap capacitor is also connected to this pin.
1.7.2.27.5 VLS[2:0] - Voltage Supply for Low -Side Drivers The pins are the voltage supply pins for the three low-side FET pre-drivers. These pins should be connected to the voltage regulator output pin VLS_OUT.
1.7.2.27.6 LG[2:0] - Low-Side Gate signals The pins are the gate drives for the low-side power FETs. The drivers provide a high current with low impedance to turn on and off the low-side power FETs.
1.7.2.27.7 LS[2:0] - Low-Side Source Signals The pins are the low-side source connections for the low-side power FETs. The pins are the power ground pins used to return the gate currents from the low-side power FETs.

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1.7.2.27.8 LD[2:0] - Low-Side Drain Signals (ZVMC256 Only) The pins are the low-side drain connections for the low-side power FETs. The pins can be used to monitor the low-side power FETs for desaturation conditions.
1.7.2.27.9 CP - Charge Pump Output Signal This pin is the switching node of the charge pump circuit. The supply voltage for charge pump driver is the output of the voltage regulator VLS_OUT. The output voltage of this pin switches typically between 0V and 11V. Must be left unconnected if not used.
1.7.2.27.10 VCP - Charge Pump Input For High-Side Driver Supply This is the charge pump input for the FET high-side gate drive supply circuit. The pin must be left unconnected if not used.
1.7.2.27.11 BST - Boost Signal This pin provides the basic switching elements required to implement a boost converter for low battery voltage conditions. This requires external diodes, capacitors and a coil. This pin must be left unconnected if not used. The boost function must not be used on devices of the maskset 2N95G, because these devices use the VSUP pin as the LINPHY supply. Thus boosting the VSUP voltage can cause LIN supply voltage offsets to other devices on the LIN bus.
1.7.2.27.12 VSSB - Boost Ground Signal This pin is a separate ground pin for the on chip boost converter switching device.
1.7.2.27.13 VLS_OUT - 11V Voltage Regulator Output This pin is the output of the integrated voltage regulator. The output voltage is typically VVLS=11V. The input voltage to the voltage regulator is the VSUP pin.
1.7.2.27.14 AMPP[1:0] - Current Sense Amplifier Non-Inverting Input These are the current sense amplifier non-inverting inputs.
1.7.2.27.15 AMPM[1:0] - Current Sense Amplifier Inverting Input These are the current sense amplifier inverting inputs.
1.7.2.27.16 AMP[1:0] - Current Sense Amplifier Output These are the current sense amplifier outputs.

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1.7.2.28 High Current Output -- EVDD1 This is a high current, low voltage drop output intended for supplying external devices in a range of up to 20mA. Configuring the pin direction as output automatically enables the high current capability.
1.7.3 Power Supply And Voltage Regulator Related Pins
The power and ground pins are described below. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible.
NOTE All ground pins must be connected together in the application.
1.7.3.1 VDDX1, VDDX2, VSSX1 -- Digital I/O Power and Ground Pins VDDX1, VDDX2 are voltage regulator outputs to supply the digital I/O drivers. The VSSX1 pin is the ground pin for the digital I/O drivers. Bypass requirements on VDDX2, VDDX1, VSSX1 depend on how heavily the MCU pins are loaded.
1.7.3.2 BCTL BCTL is the ballast connection for the on chip voltage regulator. It provides the base current of an external bipolar for the VDDX and VDDA supplies. If not used BCTL should be left unconnected.
1.7.3.3 VDDA, VSSA -- Power Supply Pins For ADC These are the power supply and ground pins for the analog-to-digital converter and the voltage regulator.
1.7.3.4 VDD, VSS2 -- Core Power And Ground Pins The VDD voltage supply of nominally 1.8V is generated by the internal voltage regulator. The return current path is through the VSS1 pin on ZVMC256, or VSS2 pin on other devices.
1.7.3.5 VDDF, VSS1-- NVM Power And Ground Pins The VDDF voltage supply of nominally 2.8V is generated by the internal voltage regulator. The return path is through the VSS1 pin. On ZVMC256, the return current path is through the VSS1 and VSSX pins.
1.7.3.6 VSUP -- Voltage Supply Pin for Voltage Regulator VSUP is the main supply pin typically coming from the car battery/alternator in the 12V supply voltage range. This is the voltage supply input from which the voltage regulator generates the on chip voltage supplies. It must be protected externally against a reverse battery connection.

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1.7.3.7 VDDS1 -- 5V Supply Pin For External Devices (ZVMC256 Only) This provides a regulated, short circuit protected, 5V supply for external devices. This is the output voltage of the external bipolar, whose base current is supplied by BCTLS1. It is fed back to the MCU for regulation.
1.7.3.8 BCTLS1 (ZVMC256 Only) BCTLS1 provides the base current of an external bipolar that supplies VDDS1. If not used BCTLS1 should be left unconnected.
1.7.3.9 SNPS1 (ZVMC256 Only) SNPS1 is the sense input associated with the VDDS1 regulator. The voltage regulator uses it to detect a short circuit or over current condition.
1.7.3.10 VDDS2 -- 5V Supply Pin For External Devices (ZVMC256 Only) This provides a regulated, short circuit protected, 5V supply for external devices. This is the output voltage of the external bipolar, whose base current is supplied by BCTLS2. It is fed back to the MCU for regulation.
1.7.3.11 BCTLS2 (ZVMC256 Only) BCTLS2 provides the base current of an external bipolar that supplies VDDS2. If not used BCTLS2 should be left unconnected.
1.7.3.12 SNPS2 (ZVMC256 Only) SNPS2 is the sense input associated with the VDDS2 regulator. The voltage regulator uses it to detect a short circuit or over current condition.
1.7.4 Package and Pinouts
The following package options are offered. · 80LQFP-EP (exposed pad) with internal CANPHY and CAN VREG. · 64LQFP-EP (exposed pad) with internal LINPHY or HV physical interface. · 64LQFP-EP (exposed pad) with CAN VREG to support a low cost external CANPHY. · 48LQFP-EP (exposed pad) with internal LINPHY or HV physical interface
The exposed pad must be connected to a grounded contact pad on the PCB. The exposed pad has an electrical connection within the package to VSSFLAG (VSSX die connection). The pin out details are shown in the following diagrams. Signals in brackets denote routing options.

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The exposed pad on the package bottom must be connected to a grounded contact pad on the PCB.

80 BKGD 79 VSSX1 78 VDDX1 77 PP0 76 PP1 75 VDD 74 VSS1 73 VDDF 72 PS0 71 PS1 70 PS2 69 PS3 68 TEST 67 PE0 66 PE1 65 RESET 64 PT3 63 PT2 62 PT1 61 PT0

VSUP 1 VLS_OUT 2
CP 3 VSSB 4
BST 5 VCP 6
HD 7 PL0 8 BCTL 9 SNPS1 10 BCTLS1 11 VDDS1 12 SNPS2 13 BCTLS2 14 VDDS2 15 LD0 16 LD1 17 LD2 18 PAD0 19 PAD1 20

S12ZVMC256 80-pin LQFP-EP
Top view

60 HS1 59 HG1 58 VBS1 57 VLS1 56 LG1 55 LS1 54 LS2 53 LG2 52 VLS2 51 VBS2 50 HG2 49 HS2 48 HS0 47 HG0 46 VBS0 45 VLS0 44 LG0 43 LS0 42 SPLIT0 41 CANL0

PAD2 21 PAD3 22 PAD4 23 PAD5 24 PAD6 25 PAD7 26 PAD8 27 VDDA 28 VSSA 29 PAD9 30 PAD10 31 PAD11 32 PAD12 33 PAD13 34 PAD14 35 PAD15 36 BCTLC 37 VDDC 38 CANH0 39 VSSC 40

Figure 1-3. S12ZVMC256 80-pin LQFP pin out

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64 LGND 63 VSSX1 62 VDDX1 61 PP0 / EVDD1 / KWP0 / (PWM0_0) / ECLK / FAULT5 / XIRQ 60 PP1 / KWP1 / (PWM0_1) / IRQ 59 PP2 / KWP2 / (PWM0_2) 58 VDDF 57 VSS1 56 PE0 / EXTAL 55 PE1 / XTAL 54 RESET 53 PT3 / IOC0_3 / (SS0) 52 PT2 / IOC0_2 / (PWM0_5) / (SCK0) 51 PT1 / IOC0_1 / (PWM0_4) / (MOSI0) / (TXD0) / LP0DR1 / PTURE 50 PT0 / IOC0_0 / (PWM0_3) / (MISO0) / (RXD0) 49 HS1

The exposed pad on the package bottom must be connected to a grounded contact pad on the PCB.
On MC9S12ZVM options the LIN0 pin is mapped to the HV physical interface function
IOC0_1 and IOC0_2 can be routed to Port S on the ZVMC256, ZVML31, ZVM32 and ZVM16 devices but not on other devices.

Chapter 1 Device Overview MC9S12ZVM-Family

LIN0

1

MODC / BKGD

2

PTUT0 / (IOC0_1) / (LP0RXD) / RXCAN0 / RXD1 / KWS0 / PS0

3

PTUT1 / (IOC0_2) / (LP0TXD) / TXCAN0 / TXD1 / KWS1 / PS1

4

MISO0 / (RXD1) / KWS2 / PS2

5

MOSI0 / (TXD1) / DBGEEV / KWS3 / PS3

6

PDOCLK / SCK0 / KWS4 / PS4

7

PDO / SS0 / KWS5 / PS5

8

BCTL

9

HD 10

VCP 11

BST 12

VSSB 13

CP 14

VLS_OUT 15

VSUP 16

S12ZVML and S12ZVM option 64-pin LQFP-EP

48 HG1 47 VBS1 46 VLS1 45 LG1 44 LS1 43 LS2 42 LG2 41 VLS2 40 VBS2 39 HG2 38 HS2 37 HS0 36 HG0 35 VBS0 34 VLS0 33 LG0

VDDX2 17 TEST 18 VSS2 19 VDD 20
AN0_0 / AMP0 / KWAD0 / PAD0 21 AN0_1 / AMPM0 / KWAD1 / PAD1 22 AN0_2 / AMPP0 / KWAD2 / PAD2 23
AN0_3 / KWAD3 / PAD3 24 AN0_4 / KWAD4 / PAD4 25 AN1_0 / AMP1 / KWAD5 / PAD5 26 (SS0) / AN1_1 / AMPM1 / KWAD6 / PAD6 27 AN1_2 / AMPP1 / KWAD7 / PAD7 28 VRH / AN1_3 / KWAD8 / PAD8 29
VDDA 30 VSSA 31
LS0 32

Figure 1-4. S12ZVM and S12ZVML option 64-pin LQFP pin out

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The exposed pad on the package bottom must be connected to a grounded contact pad on the PCB.

64 VDDC 63 VSSX1 62 VDDX1 61 PP0 / EVDD1 / KWP0 / (PWM0_0) / ECLK / FAULT5 / XIRQ 60 PP1 / KWP1 / (PWM0_1) / IRQ 59 PP2 / KWP2 / (PWM0_2) 58 VDDF 57 VSS1 56 PE0 / EXTAL 55 PE1 / XTAL 54 RESET 53 PT3 / IOC0_3 / (SS0) 52 PT2 / IOC0_2 / (PWM0_5) / (SCK0) 51 PT1 / IOC0_1 / (PWM0_4) / (MOSI0) / (TXD0) / PTURE 50 PT0 / IOC0_0 / (PWM0_3) / (MISO0) / (RXD0) 49 HS1

BCTLC

1

MODC / BKGD

2

PTUT0 / RXCAN0 / RXD1 / KWS0 / PS0

3

PTUT1 / TXCAN0 / TXD1 / KWS1 / PS1

4

MISO0 / (RXD1) / KWS2 / PS2

5

MOSI0 / (TXD1) / DBGEEV / KWS3 / PS3

6

PDOCLK / SCK0 / KWS4 / PS4

7

PDO / SS0 / KWS5 / PS5

8

BCTL

9

HD 10

VCP 11

BST 12

VSSB 13

CP 14

VLS_OUT 15

VSUP 16

S12ZVMC Option 64-pin LQFP-EP

48 HG1 47 VBS1 46 VLS1 45 LG1 44 LS1 43 LS2 42 LG2 41 VLS2 40 VBS2 39 HG2 38 HS2 37 HS0 36 HG0 35 VBS0 34 VLS0 33 LG0

VDDX2 17 TEST 18 VSS2 19 VDD 20
AN0_0 / AMP0 / KWAD0 / PAD0 21 AN0_1 / AMPM0 / KWAD1 / PAD1 22 AN0_2 / AMPP0 / KWAD2 / PAD2 23
AN0_3 / KWAD3 / PAD3 24 AN0_4 / KWAD4 / PAD4 25 AN1_0 / AMP1 / KWAD5 / PAD5 26 (SS0) / AN1_1 / AMPM1 / KWAD6 / PAD6 27 AN1_2 / AMPP1 / KWAD7 / PAD7 28 VRH / AN1_3 / KWAD8 / PAD8 29
VDDA 30 VSSA 31
LS0 32

Figure 1-5. S12ZVMC Option 64-pin LQFP pin out

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The exposed pad on the package bottom must be connected to a grounded contact pad on the PCB.
The LIN0 pin is mapped to the HV physical interface

Chapter 1 Device Overview MC9S12ZVM-Family

48 LGND 47 VSSX1 46 VDDX1 45 PP0 / EVDD1 / KWP0 / (PWM0_0) / ECLK / FAULT5 / XIRQ 44 VDDF 43 VSS1 42 PE0 / EXTAL 41 PE1 / XTAL 40 RESET 39 PT0 / IOC0_0 / (PWM0_3) / (RXD0) 38 HS1 37 HG1

LIN0 MODC / BKGD PTUT0 / (IOC0_1) / (LP0RXD) / RXD1 / KWS0 / PS0 PTUT1 / (IOC0_2) / (LP0TXD) / TXD1 / KWS1 / PS1
BCTL HD
VCP BST VSSB
CP VLS_OUT
VSUP

1

2

3

4 5

S12ZVML and S12ZVM

6 Options

7 48-pin LQFP-EP

8

9

10

11

12

36 VBS1 35 LG1 34 LS1 33 LS2 32 LG2 31 VLS2 30 VBS2 29 HG2 28 HS2 27 HS0 26 HG0 25 VBS0

VDDX2 13 TEST 14 VSS2 15 VDD 16
AN0_0 / AMP0 / KWAD0 / PAD0 17 AN0_1 / AMPM0 / KWAD1 / PAD1 18 AN0_2 / AMPP0 / KWAD2 / PAD2 19
VRH / AN1_3 / KWAD8 / PAD8 20 VDDA 21 VSSA 22 LS0 23 LG0 24

Figure 1-6. S12ZVM, S12ZVML Option 48-pin LQFP

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1.7.4.1 Pin Summary And Signal Mapping

Table 1-8. Pin Summary For 64-Pin and 48-Pin Package Options (Sheet 1 of 4)

LQFP Option

64 M/ ML

64 MC

48

1--1

Pin LIN0

-- 1 -- BCTLC

2

2

2

BKGD

3

3

3

PS0 (1)

4

4

4

PS1 (1)

5

5--

PS2

6

6--

PS3

7

7--

PS4

8

8--

PS5

9

9

5

BCTL

10 10 6

HD

11 11 7

VCP

12 12 8

BST

13 13 9

VSSB

14 14 10

CP

15 15 11 VLS_OUT

16 16 12

VSUP

17 17 13 VDDX2

18 18 14

TEST

19 19 15

VSS2

Function (Priority and device dependencies specified in PIM
chapter)

1st Func.

2nd Func.

3rd Func.

4th Func.

5th Func.

Power Supply

--

--

--

--

--

--

-- MODC KWS0
KWS1
KWS2

-- -- RXD1
TXD1
RXD1

-- -- RXCAN0

-- -- LP0RXD

TXCAN0 LP0TXD

MISO0

--

--
--
PTUT0 / IOC0_1
PTUT1 / IOC0_2
--

-- VDDX VDDX
VDDX
VDDX

KWS3 DBGEE

TXD1

MOSI0

--

VDDX

V

KWS4

SCK0 PDOCLK

--

--

VDDX

KWS5

SS0

PDO

--

--

VDDX

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

VSUP

--

--

--

--

--

VDDX

--

--

--

--

--

--

--

--

--

--

--

--

Internal Pull Resistor

CTRL

Reset State

--
-- -- PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS -- -- -- -- -- -- -- -- -- RESET --

Up (weak
) -- Up Up
Up
Up
Up
Up
Up
-- -- -- -- -- -- -- -- -- Down --

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Table 1-8. Pin Summary For 64-Pin and 48-Pin Package Options (Sheet 2 of 4)

LQFP Option

64 M/ ML

64 MC

48

20 20 16 21 21 17

22 22 18

23 23 19

24 24 --

25 25 --

26 26 --

27 27 --

28 28 --

29 29 20

30 30 21 31 31 22
32 32 23 33 33 24 34 34 -- 35 35 25

Pin VDD PAD0
PAD1
PAD2
PAD3
PAD4
PAD5
PAD6
PAD7
PAD8
VDDA VSSA LS0 LG0 VLS0 VBS0

Function (Priority and device dependencies specified in PIM
chapter)

1st Func.

2nd Func.

3rd Func.

4th Func.

5th Func.

Power Supply

Internal Pull Resistor

CTRL

Reset State

--

--

--

--

--

KWAD0 AN0_0

AMP0

--

--

KWAD1 AN0_1 AMPM0

--

--

KWAD2 AN0_2 AMPP0

--

--

KWAD3 AN0_3

--

--

--

KWAD4 AN0_4

--

--

--

KWAD5 AN1_0

AMP1

--

--

KWAD6 AN1_1 AMPM1

SS0

--

KWAD7 AN1_2 AMPP1

--

--

KWAD8 AN1_3 VRH0_0 VRH1_0

--

VRH0_1 VRH1_1

--

--

--

VRL0_ VRL1_

--

--

--

[1:0]

[1:0]

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

VDD

--

--

VDDA PERADL Off /PPSAD L

VDDA PERADL Off /PPSAD L

VDDA PERADL Off /PPSAD L

VDDA PERADL Off /PPSAD L

VDDA PERADL Off /PPSAD L

VDDA PERADL Off /PPSAD L

VDDA PERADL Off /PPSAD L

VDDA PERADL Off /PPSAD L

VDDA

PERAD

Off

H/PPSA

DH

VDDA

--

--

VDDA

--

--

--

--

--

--

--

--

--

--

--

--

--

--

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Table 1-8. Pin Summary For 64-Pin and 48-Pin Package Options (Sheet 3 of 4)

LQFP Option

64 M/ ML

64 MC

48

36 36 26 37 37 27 38 38 28 39 39 29 40 40 30 41 41 31 42 42 32 43 43 33 44 44 34 45 45 35 46 46 -- 47 47 36 48 48 37 49 49 38 50 50 39

51 51 --

52 52 --

53 53 --

54 54 40 55 55 41

56 56 42

57 57 43 58 58 44

Pin
HG0 HS0 HS2 HG2 VBS2 VLS2 LG2 LS2 LS1 LG1 VLS1 VBS1 HG1 HS1 PT0
PT1
PT2
PT3
RESET PE1
PE0
VSS1 VDDF

Function (Priority and device dependencies specified in PIM
chapter)

1st Func.

2nd Func.

3rd Func.

4th Func.

5th Func.

Power Supply

Internal Pull Resistor

CTRL

Reset State

-- -- -- -- -- -- -- -- -- -- -- -- -- -- IOC0_0

-- -- -- -- -- -- -- -- -- -- -- -- -- -- PWM1_3

-- -- -- -- -- -- -- -- -- -- -- -- -- -- MISO0

IOC0_1 PWM1_4 MOSI0

IOC0_2 PWM1_5 SCK0

IOC0_3

SS0

--

--

--

--

XTAL

--

--

EXTAL

--

--

--

--

--

--

--

--

-- -- -- -- -- -- -- -- -- -- -- -- -- -- RXD0
TXD0
--
--
-- --
--
-- --

-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
LP0DR1/ PTURE
--
--
-- --
--
-- --

-- -- -- -- -- -- -- -- -- -- -- -- -- -- VDDX
VDDX
VDDX
VDDX
VDDX VDDX
VDDX
-- VDDF

-- -- -- -- -- -- -- -- -- -- -- -- -- -- PERT/ PPST PERT/ PPST PERT/ PPST PERT/ PPST TEST pin PERE/ PPSE PERE/ PPSE -- --

-- -- -- -- -- -- -- -- -- -- -- -- -- -- Off
Off
Off
Off
Up Down
Down
-- --

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Table 1-8. Pin Summary For 64-Pin and 48-Pin Package Options (Sheet 4 of 4)

LQFP Option

64 M/ ML

64 MC

48

Pin

59 59 --

PP2

Function (Priority and device dependencies specified in PIM
chapter)

1st Func.

2nd Func.

3rd Func.

KWP2 PWM1_2

--

4th Func.
--

5th Func.
--

60 60 --

PP1

KWP1 PWM1_1

IRQ

--

--

61 61 45

PP0 / EVDD1

KWP0 PWM1_0 ECLK FAULT5

62 62 46 VDDX1

--

--

--

--

63 63 47 VSSX1

--

--

--

--

64 -- 48

LGND

--

--

--

--

-- 64 --

VDDC

--

--

--

--

1. IOC signal only available on ZVML31, ZVM32 and ZVM16 on this pin.

XIRQ
-- -- -- --

Power Supply

Internal Pull Resistor

CTRL

Reset State

VDDX

PERP/

Off

PPSP

VDDX

PERP/

Off

PPSP

VDDX

PERP/

Off

PPSP

VDDX

--

--

--

--

--

--

--

--

--

--

--

Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 1 of 5)

Pin Pin # Name

1 VSUP

2 VLS_O UT

3

CP

4 VSSB

5

BST

6

VCP

7

HD

8

PL0

9 BCTL

10 SNPS1

Function (Priority and routing options defined in PIM chapter)

1st Func.

2nd Func.

3rd Func.

4th Func.

5th Func.

6th Func.

7th Func.

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

HVI0

KWL0 IOC0_2

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

Supply
VSUP VSUP
-- -- -- -- -- -- -- --

Internal Pull Resistor

CTRL

Reset State

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

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Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 2 of 5)

Pin Pin # Name

Function (Priority and routing options defined in PIM chapter)

1st Func.

2nd Func.

3rd Func.

4th Func.

5th Func.

6th Func.

11 BCTLS

--

--

--

--

--

--

1

12 VDDS1 VRH0_1 VRH1_1

--

--

--

--

13 SNPS2

--

--

--

--

--

--

14 BCTLS

--

--

--

--

--

--

2

15 VDDS2 VRH0_2 VRH1_2

--

--

--

--

16 LD0

--

--

--

--

--

--

17 LD1

--

--

--

--

--

--

18 LD2

--

--

--

--

--

--

19 PAD0 KWAD0 AN0_0 AMP0

--

--

--

7th Func.

20 PAD1 KWAD1 AN0_1 AMPM0

--

--

--

21 PAD2 KWAD2 AN0_2 AMPP0

--

--

--

22 PAD3 KWAD3 AN0_3

--

--

--

--

23 PAD4 KWAD4 AN0_4

--

--

--

--

24 PAD5 KWAD5 AN1_0 AMP1

--

--

--

25 PAD6 KWAD6 AN1_1

SS0 AMPM1

--

--

26 PAD7 KWAD7 AN1_2 AMPP1

--

--

--

27 PAD8 KWAD8 AN1_3

--

--

--

--

Supply --

Internal Pull Resistor

CTRL --

Reset State
--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

VDDA PERAD Off L/PPSA DL

VDDA PERAD Off L/PPSA DL

VDDA PERAD Off L/PPSA DL

VDDA PERAD Off L/PPSA DL

VDDA PERAD Off L/PPSA DL

VDDA PERAD Off L/PPSA DL

VDDA PERAD Off L/PPSA DL

VDDA PERAD Off L/PPSA DL

VDDA PERAD Off H/PPS ADH

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Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 3 of 5)

Pin Pin # Name

Function (Priority and routing options defined in PIM chapter)

1st Func.

2nd Func.

3rd Func.

4th Func.

5th Func.

6th Func.

7th Func.

28 VDDA VRH0_0 VRH1_0

--

--

--

--

29 VSSA VRL0_ VRL1_

--

--

--

--

--

[1:0]

[1:0]

30 PAD9 KWAD9 AN1_4

--

--

--

--

--

31 PAD10 KWAD1 AN1_5

--

--

--

--

--

0

32 PAD11 KWAD1 AN1_6

--

--

--

--

--

1

33 PAD12 KWAD1 AN1_7

--

--

--

--

--

2

34 PAD13 KWAD1 AN0_5 PTURE

--

--

--

--

3

35 PAD14 KWAD1 AN0_6

PDO

--

--

--

--

4

36 PAD15 KWAD1 AN0_7 PDOCL

--

--

--

--

5

K

37 BCTLC

--

--

--

--

--

--

--

38 VDDC

--

--

--

--

--

--

--

39 CANH0

--

--

--

--

--

--

--

40 VSSC

--

--

--

--

--

--

--

41 CANL0

--

--

--

--

--

--

--

42 SPLIT0

--

--

--

--

--

--

--

43

LS0

--

--

--

--

--

--

--

44 LG0

--

--

--

--

--

--

--

45 VLS0

--

--

--

--

--

--

--

46 VBS0

--

--

--

--

--

--

--

47 HG0

--

--

--

--

--

--

--

Supply
VDDA VDDA

Internal Pull Resistor

CTRL
-- --

Reset State
--
--

VDDA PERAD Off H/PPS ADH

VDDA PERAD Off H/PPS ADH

VDDA PERAD Off H/PPS ADH

VDDA PERAD Off H/PPS ADH

VDDA PERAD Off H/PPS ADH

VDDA PERAD Off H/PPS ADH

VDDA PERAD Off H/PPS ADH

VDDC

--

--

VDDC

--

--

VDDC

--

--

VDDC

--

--

VDDC

--

--

VDDC

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

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Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 4 of 5)

Pin Pin # Name

48 HS0

49 HS2

50 HG2

51 VBS2

52 VLS2

53 LG2

54

LS2

55

LS1

56 LG1

57 VLS1

58 VBS1

59 HG1

60 HS1

61 PT0

62 PT1

63 PT2

64 PT3

65 RESET

Function (Priority and routing options defined in PIM chapter)

1st Func.
-- -- -- -- -- -- -- -- -- -- -- -- -- IOC0_0
IOC0_1
IOC0_2
IOC0_3
--

2nd Func.
-- -- -- -- -- -- -- -- -- -- -- -- -- PWM1_ 3 PWM1_ 4 PWM1_ 0 PWM1_ 2 --

3rd Func.
-- -- -- -- -- -- -- -- -- -- -- -- -- MISO0
MOSI0
SCK0
SS0
--

4th Func.
-- -- -- -- -- -- -- -- -- -- -- -- -- RXD0
TXD0
PWM0_ 7
PWM0_ 3 --

5th Func.
-- -- -- -- -- -- -- -- -- -- -- -- -- PWM0_ 5 --
--
--
--

6th Func.
-- -- -- -- -- -- -- -- -- -- -- -- -- --
--
--
--
--

7th Func.
-- -- -- -- -- -- -- -- -- -- -- -- -- --
--
--
--
--

66 PE1

XTAL

--

--

--

--

--

--

67

PE0

EXTAL

--

--

--

--

--

--

68 TEST

--

--

--

--

--

--

--

69 PS3

KWS3 TXD1 MOSI0 CPTXD DBGEE IOC1_1

--

0

V

70 PS2

KWS2 RXD1 MISO0 CPRXD IOC1_0

--

--

0

Supply

Internal Pull Resistor

CTRL

Reset State

-- -- -- -- -- -- -- -- -- -- -- -- -- VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
-- VDDX
VDDX

--
--
--
--
--
--
--
--
--
--
--
--
--
PERT/ PPST
PERT/ PPST
PERT/ PPST
PERT/ PPST
TEST pin
PERE/ PPSE
PERE/ PPSE
RESET
PERS/ PPSS
PERS/ PPSS

-- -- -- -- -- -- -- -- -- -- -- -- -- Off
Off
Off
Off
Up
Down
Down
Down Up
Up

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Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 5 of 5)

Pin Pin # Name
71 PS1
72 PS0
73 VDDF 74 VSS1 75 VDD 76 PP1
77 PP0/ EVDD1
78 VDDX1 79 VSSX1 80 BKGD

Function (Priority and routing options defined in PIM chapter)

1st Func.

2nd Func.

3rd Func.

4th Func.

5th Func.

6th Func.

7th Func.

Supply

KWS1
KWS0
-- -- -- KWP1
KWP0
-- -- MODC

TXD1
RXD1
-- -- -- PWM1_ 1 PWM1_ 5 -- -- --

SCK0 PTUT1 CPDR0

SS0
-- -- -- PWM0_ 1 ECLK

PTUT0
-- -- -- IRQ
FAULT5

RXCAN 0 -- -- -- --
XIRQ

--

--

--

--

--

--

--

--

--

TXCAN 0
IOC0_1
-- -- -- --
--
-- -- --

IOC0_2
--
-- -- -- --
--
-- -- --

VDDX
VDDX
VDDF VDD VDD VDDX
VDDX
VDDX VDDX VDDX

Internal Pull Resistor

CTRL
PERS/ PPSS PERS/ PPSS
-- -- -- PPRP/ PPSP PPRP/ PPSP -- -- --

Reset State
Up
Up
-- -- -- Off
Off
-- -- Up

1.8 Internal Signal Mapping
This section specifies the mapping of inter-module signals at device level.

1.8.1 ADC Connectivity

1.8.1.1 ADC Reference Voltages
The ZVMC256 includes ADC12B_LBA V3 which features VRH_2, VRH_1, VRH_0 and VRL_0. On these devices for each ADC instance VRH_0 is mapped to VDDA, VRH_1 is mapped to VDDS1 and VRH_2 is mapped to VDDS2. VRL_0 is mapped to VSSA. Both VDDS1 and VDDS2 must be enabled by bits in the CPMUVREGCTL register before they can be used as references. When using VDDS1 or VDDS2 as VRH reference, the reference is impacted by a voltage drop across the internal short circuit protection switch. This is specified in Section C.1.1.5.
All other devices in the family include ADC12B_LBA V1, which features VRH_1, VRH_0, VRL_1 and VRL_0. On these devices, for both ADC instances, VRL_0 and VRL_1 are mapped to VSSA, whereby VRL_0 is the preferred reference for low noise. For both ADC instances VRH_1 is mapped to VDDA and VRH_0 is mapped to PAD8.

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1.8.1.2 ADC Internal Channels
The ADC0 and ADC1 internal channel mapping is shown in Table 1-10 and Table 1-11 respectively.
The GDU current sense amplifier outputs are mapped to pins with ADC input functionality. Thus configuring the ADC to convert these pin channels automatically converts the current sense outputs.
The ADC internal temperature sensors must be calibrated by the user. No electrical parameters are specified for these sensors. The VREG temperature sensor electrical parameters are given in the appendices.
Table 1-10. Usage of ADC0 Internal Channels

ADCCMD_1 CH_SEL[5:0]

0

0

1

0

0

0

0

0

1

0

0

1

0

0

1

0

1

0

0

0

1

0

1

1

0

0

1

1

0

0

0

0

1

1

0

1

0

0

1

1

1

0

0

0

1

1

1

1

1. Selectable in CPMU

ADC Channel
Internal_0 Internal_1 Internal_2 Internal_3 Internal_4 Internal_5 Internal_6 Internal_7

2. ZVMC256 only. On other devices this channel is reserved.

Usage
ADC0 temperature sensor VREG temperature sensor or bandgap (VBG)(1)
GDU phase multiplexer voltage GDU DC link voltage monitor BATS VSUP sense voltage
HVI[0](2) Reserved Reserved

Table 1-11. Usage of ADC1 Internal Channels

ADCCMD_1 CH_SEL[5:0]

0

0

1

0

0

0

0

0

1

0

0

1

0

0

1

0

1

0

0

0

1

0

1

1

0

0

1

1

0

0

0

0

1

1

0

1

0

0

1

1

1

0

0

0

1

1

1

1

1. Selectable in CPMU

ADC Channel
Internal_0 Internal_1 Internal_2 Internal_3 Internal_4 Internal_5 Internal_6 Internal_7

Usage
ADC1 temperature sensor VREG temperature sensor or bandgap (VBG)(1)
GDU phase multiplexer voltage GDU DC link voltage monitor
Reserved Reserved Reserved Reserved

1.8.2 Motor Control Loop Signals
The motor control loop signals are described in 1.13.3.1 Motor Control Loop Overview

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Device Level PMF Connectivity

Table 1-12. Mapping of PMF signals

PMF Connection
Channel0 Channel1 Channel2 Channel3 Channel4 Channel5 FAULT5 FAULT4 FAULT3 FAULT2 FAULT1 FAULT0
IS2 IS1 IS0 async_event_edge_sel[1:0]

Usage
High-Side Gate and Source Pins HG[0], HS[0] Low-Side Gate and Source Pins LG[0], LS[0] High-Side Gate and Source Pins HG[1], HS[1] Low-Side Gate and Source Pins LG[1], LS[1] High-Side Gate and Source Pins HG[2], HS[2] Low-Side Gate and Source Pins LG[2], LS[2]
External FAULT5 pin HD Over voltage or GDU over current
VLS under voltage GDU Desaturation[2] or GDU over current GDU Desaturation[1] or GDU over current GDU Desaturation[0] or GDU over current
GDU Phase Status[2] GDU Phase Status[1] GDU Phase Status[0] Tied to b11 (both edges active)

1.8.4 BDC Clock Source Connectivity
The BDC clock, BDCCLK, is mapped to the IRCCLK generated in the CPMU module. The BDC clock, BDCFCLK is mapped to the device bus clock, generated in the CPMU module.

1.8.5 LINPHY Connectivity
The VLINSUP supply is device dependent.
On ZVML128, ZVMC128, ZVML64, ZVMC64 and ZVML32 devices with the maskset number 2N95G it is connected to VSUP
On all other devices it is connected to the device HD pin.
The LINPHY0 signals are mapped internally to SCI0. The receiver can be routed to TIM0 input capture channel3. These routing options are described in detail in the PIM section.

1.8.6 HVPHY Connectivity
The HVPHY signals (S12ZVM32 and S12ZVM16 derivatives only) are mapped internally to SCI0. The receiver can be routed to TIM0 input capture channel3.

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1.8.7 FTMRZ Connectivity
The soc_erase_all_req input to the flash module is driven directly by a BDC erase flash request resulting from the BDC ERASE_FLASH command.
The FTMRZ FCLKDIV register is forced to 0x05 by the BDC ERASE_FLASH command. This configures the clock frequency correctly for the initial bus frequency on leaving reset. The bus frequency must not be changed before launching the ERASE_FLASH command.
The device bus frequency, below which the flash wait states can be disabled, is specified in the device operating conditions table in Table A-6.

1.8.8 CPMU Connectivity
The API clock generated in the CPMU is not mapped to a device pin in the MC9S12ZVM-Family.
1.9 Modes of Operation
The MCU can operate in different modes. These are described in 1.9.1 Chip Configuration Modes. The MCU can operate in different power modes to facilitate power saving when full system performance is not required. These are described in 1.9.3 Low Power Modes. Some modules feature a software programmable option to freeze the module status whilst the background debug module is active to facilitate debugging. This is referred to as freeze mode at module level.

1.9.1 Chip Configuration Modes

The different modes and the security state of the MCU affect the debug features (enabled or disabled).
The operating mode out of reset is determined by the state of the MODC signal during reset (Table 1-13). The MODC bit in the MODE register shows the current operating mode and provides limited mode switching during operation. The state of the MODC signal is latched into this bit on the rising edge of RESET.
Table 1-13. Chip Modes

Chip Modes Normal single chip Special single chip

MODC 1 0

1.9.1.1 Normal Single-Chip Mode
This mode is intended for normal device operation. The opcode from the on-chip memory is being executed after reset (requires the reset vector to be programmed correctly). The processor program is executed from internal memory.

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1.9.1.2 Special Single-Chip Mode
This mode is used for debugging operation, boot-strapping, or security related operations. The background debug mode (BDM) is active on leaving reset in this mode
1.9.2 Debugging Modes
The background debug mode (BDM) can be activated by the BDC module or directly when resetting into Special Single-Chip mode. Detailed information can be found in the BDC module section.
Writing to internal memory locations using the debugger, whilst code is running or at a breakpoint, can change the flow of application code.
The MC9S12ZVM-Family supports BDC communication throughout the device Stop mode. During Stop mode, writes to control registers can alter the operation and lead to unexpected results. It is thus recommended not to reconfigure the peripherals during STOP using the debugger.
On the S12ZVML and S12ZVMC versions, the DBG module supports breakpoint, tracing and profiling features. At board level the profiling pins can use the same 6-pin connector typically used for the BDC BKGD pin. The connector pin mapping shown in Figure 1-7 is supported by device evaluation boards and leading development tool vendors.

GND 2 RST 4 VDDX 6

1 BKGD 3 PDO 5 PDOCLK

Figure 1-7. Standard Debug Connector Pin Mapping
1.9.3 Low Power Modes
The device has two dynamic-power modes (run and wait) and two static low-power modes stop and pseudo stop). For a detailed description refer to the CPMU section.
· Dynamic power mode: Run -- Run mode is the main full performance operating mode with the entire device clocked. The user can configure the device operating speed through selection of the clock source and the phase locked loop (PLL) frequency. To save power, unused peripherals must not be enabled.
· Dynamic power mode: Wait -- This mode is entered when the CPU executes the WAI instruction. In this mode the CPU does not execute instructions. The internal CPU clock is switched off. All peripherals can be active in system wait mode. For further power consumption the peripherals can individually turn off their local clocks. Asserting RESET, XIRQ, IRQ, or any other interrupt that is not masked, either locally or globally by a CCR bit, ends system wait mode.
· Static power modes: Static power (Stop) modes are entered following the CPU STOP instruction unless an NVM command is active. When no NVM commands are active, the Stop request is acknowledged and

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the device enters either Stop or Pseudo Stop mode. Further to the general system aspects of Stop mode discussed here, the motor control loop specific considerations are described in Section 1.13.3.10. -- Pseudo-stop: In this mode the system clocks are stopped but the oscillator is still running and
the real time interrupt (RTI), watchdog (COP) and Autonomous Periodic Interrupt (API) may be enabled. Other peripherals are turned off. This mode consumes more current than system STOP mode but, as the oscillator continues to run, the full speed wake up time from this mode is significantly shorter. -- Stop: In this mode the oscillator is stopped and clocks are switched off. The counters and dividers remain frozen. The autonomous periodic interrupt (API) may remain active but has a very low power consumption. The key pad, SCI and MSCAN transceiver modules can be configured to wake the device, whereby current consumption is negligible. If the BDC is enabled in Stop mode, the VREG remains in full performance mode and the CPMU continues operation as in run mode. With BDC enabled and BDCCIS bit set, then all clocks remain active to allow BDC access to internal peripherals. If the BDC is enabled and BDCCIS is clear, then the BDCSI clock remains active, but bus and core clocks are disabled. With the BDC enabled during Stop, the VREG full performance mode and clock activity lead to higher current consumption than with BDC disabled. If the BDC is enabled in Stop mode, then the BATS voltage monitoring remains enabled.
1.10 Security
The MCU security mechanism prevents unauthorized access to the flash memory. It must be emphasized that part of the security must lie with the application code. An extreme example would be application code that dumps the contents of the internal memory. This would defeat the purpose of security. Also, if an application has the capability of downloading code through a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the EEPROM and Flash memory contents even when the microcontroller is in the secure state. In this example, the security of the application could be enhanced by requiring a response authentication before any code can be downloaded.
Device security details are also described in the flash block description.
1.10.1 Features
The security features of the S12Z chip family are:
· Prevent external access of the non-volatile memories (Flash, EEPROM) content · Restrict execution of NVM commands
1.10.2 Securing the Microcontroller
The chip can be secured by programming the security bits located in the options/security byte in the Flash memory array. These non-volatile bits keep the device secured through reset and power-down.

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This byte can be erased and programmed like any other Flash location. Two bits of this byte are used for security (SEC[1:0]). The contents of this byte are copied into the Flash security register (FSEC) during a reset sequence.
The meaning of the security bits SEC[1:0] is shown in Table 1-14. For security reasons, the state of device security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to SEC[1:0] = `10'. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = `01'.

Table 1-14. Security Bits

SEC[1:0]
00 01 10 11

Security State
1 (secured) 1 (secured) 0 (unsecured) 1 (secured)

NOTE Please refer to the Flash block description for more security byte details.

1.10.3 Operation of the Secured Microcontroller
By securing the device, unauthorized access to the EEPROM and Flash memory contents is prevented. Secured operation has the following effects on the microcontroller:

1.10.3.1 Normal Single Chip Mode (NS)
· Background debug controller (BDC) operation is completely disabled. · Execution of Flash and EEPROM commands is restricted (described in flash block description).

1.10.3.2 Special Single Chip Mode (SS)
· Background debug controller (BDC) commands are restricted · Execution of Flash and EEPROM commands is restricted (described in flash block description).
In special single chip mode the device is in active BDM after reset. In special single chip mode on a secure device, only the BDC mass erase and BDC control and status register commands are possible. BDC access to memory mapped resources is disabled. The BDC can only be used to erase the EEPROM and Flash memory without giving access to their contents.

1.10.4 Unsecuring the Microcontroller
Unsecuring the microcontroller can be done using three different methods: 1. Backdoor key access 2. Reprogramming the security bits 3. Complete memory erase

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1.10.4.1 Unsecuring the MCU Using the Backdoor Key Access
In normal single chip mode, security can be temporarily disabled using the backdoor key access method. This method requires that:
· The backdoor key has been programmed to a valid value · The KEYEN[1:0] bits within the Flash options/security byte select `enabled'. · The application program programmed into the microcontroller has the capability to write to the
backdoor key locations
The backdoor key values themselves would not normally be stored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g. through a serial port)
The backdoor key access method allows debugging of a secured microcontroller without having to erase the Flash. This is particularly useful for failure analysis.
NOTE No backdoor key word is allowed to have the value 0x0000 or 0xFFFF.
1.10.5 Reprogramming the Security Bits
Security can also be disabled by erasing and reprogramming the security bits within the flash options/security byte to the unsecured value. Since the erase operation will erase the entire sector (0xFF_FE00­0xFF_FFFF) the backdoor key and the interrupt vectors will also be erased; this method is not recommended for normal single chip mode. The application software can only erase and program the Flash options/security byte if the Flash sector containing the Flash options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of preventing this method. The microcontroller enters the unsecured state after the next reset following the programming of the security bits to the unsecured value.
This method requires that: · The application software previously programmed into the microcontroller has been designed to have the capability to erase and program the Flash options/security byte. · The Flash sector containing the Flash options/security byte is not protected.
1.10.6 Complete Memory Erase
The microcontroller can be unsecured by erasing the entire EEPROM and Flash memory contents. If ERASE_FLASH is successfully completed, then the Flash unsecures the device and programs the security byte automatically.

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1.11.1 Reset
Table 1-15. lists all reset sources and the vector locations. Resets are explained in detail in the Chapter 8, "S12 Clock, Reset and Power Management Unit (00.17)".

Vector Address 0xFFFFFC

Table 1-15. Reset Sources and Vector Locations

Reset Source

CCR Mask

Local Enable

Power-On Reset (POR) Low Voltage Reset (LVR)
External pin RESET PLL clock monitor reset
Oscillator Clock monitor reset COP watchdog reset

None None None None None
None

None None None None OSCE in CPMUOSC register OMRE in CPMUOSC2 register CR[2:0] in CPMUCOP register

1.11.2 Interrupt Vectors
Table 1-16 lists all interrupt sources and vectors in the default order of priority. The interrupt module description provides an interrupt vector base register (IVBR) to relocate the vectors.
Table 1-16. Interrupt Vector Locations

Vector Address(1)

Interrupt Source

CCR Mask

Local Enable

Vector base + 0x1F8 Unimplemented page1 op-code trap (SPARE)

Vector base + 0x1F4 Unimplemented page2 op-code trap (TRAP)

Vector base + 0x1F0 Software interrupt instruction (SWI)

Vector base + 0x1EC

System call interrupt instruction (SYS)

Vector base + 0x1E8

Machine exception

Vector base + 0x1E4

Vector base + 0x1E0

Vector base + 0x1DC

Spurious interrupt

Vector base + 0x1D8

XIRQ interrupt request

Vector base + 0x1D4

IRQ interrupt request

Vector base + 0x1D0

RTI time-out interrupt

None

None

None

None

None None

None None

None

None

Reserved

Reserved

--

None

X bit

None

I bit

IRQCR(IRQEN)

I bit

CPMUINT (RTIE)

Wake up Wake up from STOP from WAIT

-

-

-

-

-

-

-

-

-

-

-

-

Yes

Yes

Yes

Yes

See CPMU

Yes

section

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Table 1-16. Interrupt Vector Locations

Vector Address(1)
Vector base + 0x1CC Vector base + 0x1C8 Vector base + 0x1C4 Vector base + 0x1C0 Vector base + 0x1BC
to Vector base + 0x1B0 Vector base + 0x1AC

Interrupt Source TIM0 timer channel 0 TIM0 timer channel 1 TIM0 timer channel 2 TIM0 timer channel 3
TIM0 timer overflow

CCR Mask

Local Enable

I bit

TIM0TIE (C0I)

I bit

TIM0TIE (C1I)

I bit

TIM0TIE (C2I)

I bit

TIM0TIE (C3I)

Reserved

I bit

TIM0TSCR2(TOI)

Wake up Wake up from STOP from WAIT

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

Vector base + 0x1A8 to
Vector base + 0x1A4

Reserved

Vector base + 0x1A0

SPI0

I bit

SPI0CR1 (SPIE, SPTIE)

No

Yes

Vector base + 0x19C

SCI0

I bit

SCI0CR2

RXEDIF

Yes

(TIE, TCIE, RIE, ILIE)

only

SCI0ACR1

(RXEDGIE, BERRIE, BKDIE)

Vector base + 0x198

SCI1

I bit

SCI1CR2

RXEDIF

Yes

(TIE, TCIE, RIE, ILIE)

only

SCI1ACR1

(RXEDGIE, BERRIE, BKDIE)

Vector base + 0x194

Reserved

Vector base + 0x190

Reserved

Vector base + 0x18C

ADC0 Error

I bit ADC0EIE (IA_EIE, CMD_EIE,

No

Yes

EOL_EIE, TRIG_EIE,

RSTAR_EIE, LDOK_EIE)

ADC0IE(CONIF_OIE)

Vector base + 0x188 ADC0 conversion sequence abort I bit

ADC0IE(SEQAD_IE)

No

Yes

Vector base + 0x184

ADC0 conversion complete

I bit

ADC0CONIE[15:0]

No

Yes

Vector base + 0x180

Oscillator status interrupt

I bit

CPMUINT (OSCIE)

No

Yes

Vector base + 0x17C
Vector base + 0x178 to
Vector base + 0x174
Vector base + 0x170
Vector base + 0x16C to
Vector base + 0x168
Vector base + 0x164
Vector base + 0x160

PLL lock interrupt
RAM error
FLASH error FLASH command

I bit

CPMUINT (LOCKIE)

Reserved

I bit

EECIE (SBEEIE)

Reserved

I bit

FERCNFG (SFDIE)

I bit

FCNFG (CCIE)

No

Yes

No

Yes

No

Yes

No

Yes

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Vector base + 0x15C Vector base + 0x158 Vector base + 0x154 Vector base + 0x150 Vector base + 0x14C
to Vector base + 0x148 Vector base + 0x144

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Table 1-16. Interrupt Vector Locations

Interrupt Source
CAN0 wake-up CAN0 errors CAN0 receive CAN0 transmit

CCR Mask

Local Enable

Wake up Wake up from STOP from WAIT

I bit

CAN0RIER (WUPIE)

Yes

Yes

I bit CAN0RIER (CSCIE, OVRIE)

No

Yes

I bit

CAN0RIER (RXFIE)

No

Yes

I bit

CAN0TIER (TXEIE[2:0])

No

Yes

Reserved

LINPHY over-current interrupt

I bit

LPIE (LPDTIE,LPOCIE)

No

Yes

Vector base + 0x140 BATS supply voltage monitor interrupt I bit

BATIE (BVHIE,BVLIE)

No

Yes

Vector base + 0x13C

GDU Desaturation Error

I bit

GDUIE (GDSEIE)

No

Yes

Vector base + 0x138

GDU Voltage Limit Detected

I bit GDUIE (GOCIE, GHHDIE,

No

Yes

GLVLSIE)

Vector base + 0x134 to
Vector base + 0x12C

Reserved

Vector base + 0x128

CAN Physical Layer (ZVMC256 Only)

I bit

CPIE

No

Yes

(CPVFIE, CPOCIE, CPDTIE)

Vector base + 0x124

Port S interrupt

I bit

PIES[5:0]

Yes

Yes

Vector base + 0x120

Reserved

Vector base + 0x11C

ADC1 Error

I bit ADC1EIE (IA_EIE, CMD_EIE,

No

Yes

EOL_EIE, TRIG_EIE,

RSTAR_EIE, LDOK_EIE)

ADC1IE(CONIF_OIE)

Vector base + 0x118 ADC1 conversion sequence abort I bit

ADC1IE(SEQAD_IE)

No

Yes

Vector base + 0x114

ADC1 conversion complete

I bit

ADC1CONIE[15:0]

No

Yes

Vector base + 0x110

Reserved

Vector base + 0x10C

Port P interrupt

I bit

PIEP[2:0]

Yes

Yes

Vector base + 0x108

EVDD1 over-current interrupt

I bit

PIEP(OCIE1)

No

Yes

Vector base + 0x104

Low-voltage interrupt (LVI)

I bit

CPMULVCTL (LVIE)

No

Yes

Vector base + 0x100

Autonomous periodical interrupt (API)

I bit

CPMUAPICTRL (APIE)

Yes

Yes

Vector base + 0xFC

High temperature interrupt

I bit

CPMUHTCTL(HTIE)

No

Yes

Vector base + 0xF8

VDDS integrity interrupt

I bit

CPMULVCTL(VDDSIE)

No

Yes

Vector base + 0xF4

Port AD interrupt

I bit

PIEADH(PIEADH0)

Yes

Yes

PIEADL(PIEADL[7:0])

Vector base + 0xF0

PTU Reload Overrun

I bit

PTUIEH(PTUROIE)

No

Yes

Vector base + 0xEC

PTU Trigger0 Error

I bit

PTUIEL(TG0AEIE,

TG0REIE,TG0TEIE)

No

Yes

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Table 1-16. Interrupt Vector Locations

Vector Address(1) Vector base + 0xE8

Interrupt Source PTU Trigger1 Error

Vector base + 0xE4 Vector base + 0xE0 Vector base + 0xDC
to Vector base + 0xD4 Vector base + 0xD0 Vector base + 0xCC Vector base + 0xC8 Vector base + 0xC4 Vector base + 0xC0

PTU Trigger0 Done PTU Trigger1 Done
PMF Reload A PMF Reload B PMF Reload C
PMF Fault PMF Reload Overrun

Vector base + 0xBC

Port L interrupt (ZVMC256 Only)

Vector base + 0xB8 to
Vector base + 0xB0

Vector base + 0xAC

TIM1 timer channel 0 (ZVMC256 Only)

Vector base + 0xA8

TIM1 timer channel 1 (ZVMC256 Only)

Vector base + 0xA4 to
Vector base + 0x90

Vector base + 0x8C

TIM1 timer overflow (ZVMC256 Only)

Vector base + 0x88 to
Vector base + 0x10

1. 15 bits vector address based

CCR Mask

Local Enable

Wake up Wake up from STOP from WAIT

I bit PTUIEL(TG1AEIE, TG1REIE,

No

Yes

TG1TEIE)

I bit

PTUIEL(TG0DIE)

I bit

PTUIEL(TG1DIE)

No

Yes

No

Yes

Reserved

I bit

PMFENCA(PWMRIEA)

No

Yes

I bit

PMFENCB(PWMRIEB)

No

Yes

I bit

PMFENCC(PWMRIEC)

No

Yes

I bit

PMFFIE(FIE[5:0])

No

Yes

I bit PMFROIE(PMFROIEA,PMF

No

Yes

ROIEB,PMFROIEC)

I bit

PIEL(PIEL0)

Yes

Yes

Reserved

I bit

TIM1TIE (C0I)

I bit

TIM1TIE (C1I)

Reserved

No

Yes

No

Yes

I bit

TIM1TSCR2(TOI)

No

Yes

Reserved

1.11.3 Effects of Reset
When a reset occurs, MCU registers are initialized. Refer to the respective block sections for register reset states. The initialization of I/O pins is specified in the PIM section.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers. If double faults are detected in the reset phase, Flash module protection and security may be active on leaving reset. This is explained in more detail in the Flash module description. If a reset occurs while any Flash command

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is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. The system RAM arrays, including their ECC syndromes, are initialized following a power on reset. All other RAM arrays are not initialized out of any type of reset. With the exception of a power-on-reset the RAM content is unaltered by a reset occurrence. The power on reset sequence including flash and SRAM initialization is shown in Figure 1-8
Figure 1-8. Device Power On Reset Sequence
Vsup

Vddx / Vddf / Vdd

POR monitors VDD

3V #1.6V POR

LVR monitors VDD, LVR
VDDF and VDDA/VDDX

5V 2.8V 1.8V

Bus Freq System Reset
RESET Pin
Device "state"

Fbus = Fvcorst/2 Fbus= 4Mhz min; 16Mhz max
768 Fvcorst cyc [24 ; 96] sec 512 Fvcorst cyc [16 ; 64] sec
RESET

Tlock= 406sec max Fbus changing to 6.25Mhz

Fbus = 6.25Mhz

396 to 510 bus cycles [24 ; 128] sec

Flash initialization

Vector fetch, program execution

SRAM initialization ­ SRAM not accessible

For S12ZVM128 : 8kBytes / 32bits = 2048 bus cycles [128; 456] sec For S12ZVM256 : 32kBytes / 64bits = 4096 bus cycles [255; 1024] sec

1.12 Module device level dependencies

1.12.1 CPMU COP and GDU Configuration
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register are loaded from the Flash configuration field byte at global address 0xFF_FE0E during the flash initialization phase of the

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reset sequence. The GSUF bit in the GDUF register is also loaded during the reset sequence. See Table 117, Table 1-18 and Table 1-19.
Table 1-17. Initial COP Rate Configuration

NV[2:0] in FOPT Register
000 001 010 011 100 101 110 111

CR[2:0] in CPMUCOP Register
111 110 101 100 011 010 001 000

Table 1-18. Initial WCOP Configuration

NV[3] in FOPT Register
1 0

WCOP in CPMUCOP Register
0 1

Table 1-19. GDU Configuration

Mask Set

GSUF (GDUF[7]) Initialization

0N95G, 1N95G 2N95G 3N95G 0N14N 1N14N
0N00R,1N00R 1. Note bit inversion

1 0 FOPT:NV[6] 1 FOPT:NV[7](1) FOPT:NV[7] (1)

EPRES (GDUE[5]) Inclusion
Not usable Not usable Not included Not included Not included Not included

GDUCTR1 Available bits
None None GDUCTR1[0] None None GDUCTR1[7,6,0]

HD nominal overvoltage time constant
300ns 2.7us 2.7us 2.7us 2.7us 2.7us

The EPRES bit was only included in early mask sets but was not usable. The implementation of GDUCTR1 register bits is also mask set dependent as shown in Table 1-19.
1.12.2 CPMU High Temperature Trimming
The value loaded from the flash into the CPMUHTTR register is a default value for the device family. There is no device specific trimming carried out during production. The specified VHT value is a typical value that is part dependent and should thus be calibrated.

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1.12.3 CPMU VDDC enable
On the ZVMC256 device, if the CANPHY is not used then the VDDC regulator can be disabled by clearing EXTCON. An external VDDC capacitor is however still required for power up.

1.12.4 Flash IFR Mapping

Table 1-20. Flash IFR Mapping
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC0 reference conversion using VRH_1/VSSA ADC0 reference conversion using VRH_0/VSSA ADC1 reference conversion using VRH_1/VSSA ADC1 reference conversion using VRH_0/VSSA
1.13 Application Information

IFR Byte Address
0x1F_C040 & 0x1F_C041 0x1F_C042 & 0x1F_C043 0x1F_C044 & 0x1F_C045 0x1F_C046 & 0x1F_C047

1.13.1 ADC Calibration
For applications that do not provide external ADC reference voltages, the VDDA/VSSA supplies can be used as sources for VRH/VRL respectively. Since the VDDA must be connected to VDDX at board level in the application, the accuracy of the VDDA reference is limited by the internal voltage regulator accuracy. In order to compensate for VDDA reference voltage variation in this case, the reference voltage is measured during production test using the internal reference voltage VBG, which has a narrow variation over temperature and external voltage supply. VBG is mapped to an internal channel of each ADC module (Table 1-10,Table 1-11). The resulting 12-bit right justified ADC conversion results of VBG are stored to the flash IFR for reference, as listed in Table 1-20.
The measurement conditions of the reference conversion are listed in the device electrical parameters appendix. By measuring the voltage VBG in the application environment and comparing the result to the reference value in the IFR, it is possible to determine the current ADC reference voltage VRH :
VRH = C-----o-S--n-t--o-v---re--e-r--dt--e-R--d---e-R--f--ee---fr--e-e--r-n--e-c--n-e--c---e-  5V

The exact absolute value of an analog conversion can be determined as follows:
Result = ConvertedADInput  -C----So---nt--o--v--r-e-e--r-d-t--eR---d--e--R-f--e-e--r-f--ee---n-r--ec---ne---c---e--5----V---2---n-

With:
ConvertedADInput: pin ConvertedReference:

Result of the analog to digital conversion of the desired Result of internal channel conversion

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StoredReference: n:

Value in IFR location ADC resolution (12 bit)

NOTE The ADC reference voltage VRH must remain at a constant level throughout the conversion process.

1.13.2 SCI Baud Rate Detection
The baud rate for SCI0 and SCI1 is achieved by using a timer channel to measure the data rate on the RXD signal.
1. Establish the link:
-- For SCI0: Set [T0IC3RR1:T0IC3RR0]=0b01 to disconnect IOC0_3 from TIM0 input capture channel 3 and reroute the timer input to the RXD0 signal of SCI0.
-- For SCI1: Set [T0IC3RR1:T0IC3RR0]=0b10 to disconnect IOC0_3 from TIM0 input capture channel 3 and reroute the timer input to the RXD1 signal of SCI1.
2. Determine pulse width of incoming data: Configure TIM0 IC3 to measure time between incoming signal edges.

1.13.3 Motor Control Application Overview
The following sections provide information for using the device in motor control applications. These sections provide a description of motor control loop considerations that are not detailed in the individual module sections, since they concern device level inter module operation specific for motor control. More detailed information is available in application notes. The applications described are as follows:
1. BDCM - wiper pumps fans 2. BLDCM - pumps, fans and blowers
­ based on Hall sensors ­ sensorless based on back-EMF zero crossing comparators ­ sensorless based on back-EMF ADC measurements 3. PMSM - high-end wiper, pumps, fans and blowers ­ simple sinewave commutation with position sensor Hall effect, sine-cos ­ FOC with sine-cos position sensor ­ sensorless 3-phase sinewave control

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1.13.3.1 Motor Control Loop Overview The mapping of motor control events at device level as depicted in Figure 1-9 is listed in Table 1-21, whereby the columns list the names used in the module level descriptions
Figure 1-9. Internal Control Loop Configuration

TIM0

OC0 commutation_event
PMF

GDU zero crossing comparators

SENSOR

GPHS

M

reloada async_reload

glb_ldok

dc_bus_current

dc_bus_voltage

async reload reload

PTU

If PTU enabled If PTU enabled

async reload ADC0 reload
glb_ldok trigger_0

async reload reload
trigger_1

ADC1

reload

PHMUX P1
back-EMF P2 P3

The control loop consists of the PMF, GDU, ADC and PTU modules. The control loop operates using either static, dynamic or asynchronous timing. In the following text the event names given in bold type correspond to those shown in Figure 1-9. The PTU and ADC operate using lists stored in memory. These lists define trigger points for the PTU, commands for the ADC and results from the ADC. If the PTU is enabled the reload and async_reload events are immediately passed through to the ADC and GDU modules.

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.
Table 1-21. Control Loop Events

Device Level Event

TIM0

PMF

PTU

commutation_event reload

OC0(1) --

commutation_event reloada(2)

-- reload

async_reload

--

async_reload

async_reload

trigger_0

--

--

trigger_0

trigger_1

--

--

trigger_1

glb_ldok

--

glb_ldok

1. TIM channel OC0 must be configured to toggle on both edges.

glb_ldok

2. PMF events reloadb and reloadc are not connected at device level

ADC0 --
Restart Seq_abort
Trigger --
LoadOK

ADC1 --
Restart Seq_abort
-- Trigger LoadOK

Each control loop cycle is started by a PMF reload event. The PMF reload event restarts the PTU time base. If the PTU is enabled, the reload is immediately passed through to the ADC and GDU modules.
The PMF generates the reload event at the required PWM reload frequency. The PMF reload event causes the PTU time base to restart, to acquire the first trigger times from the list and the ADCs to start loading the ADC conversion command from the Command Sequence List (CSL).
NOTE
In the PTU there is time window after the reload event assertion before the first trigger is permitted. This time can be up to 10 bus cycles.
Subsequent triggers also require a load time of 6 bus clock cycles (one trigger generator enabled) or 10 bus clock cycles (both trigger generators enabled). This defines the minimal spacing between triggers without causing a PTU trigger generator timing error.
In the ADC there is 10 bus cycle maximum time window after the reload event assertion to access the first ADC command from the list. In this window the ADC conversion can not be started. If the measurement is control loop related these delays are negligible due to much larger delays in the PWM-GDU-feedback loop.
When the trigger time is encountered the corresponding PTU trigger generates the trigger_x event for the associated ADC. For simultaneous sampling the PTU generates simultaneous trigger_x events for both ADCs. At the trigger_x event the ADC starts the first conversion of the next conversion sequence in the CSL (the first ADC command is already downloaded).
A commutation event is used by the PMF to generate an async_reload event. The async_reload is used by the PTU to update lists and re-initialize the trigger lists. If the PTU is enabled the async_reload is immediately passed through to the ADC.

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1.13.3.2 Control Loop Timing Considerations Delays within the separate control loop elements require consideration to ensure correct synchronization. Regarding the raw PWM0 signal as the starting point and stepping through the control loop stages, the factors shown in Figure 1-10 contribute to delays within the control loop, starting with the deadtime insertion, going through the external FETs and back into the internal ADC measurements of external voltages and currents.
Figure 1-10. Control Loop Delay Overview
PWM cycle
PWM base

PWM with deadtime
GDU propagation
FET turn on Current sense settling time (tcslsst) ADC delay

TDEAD_x tdelon tHGON

The PWM deadtime (TDEAD_X) is an integral number of bus clock cycles, configured by the PMF deadtime registers.
The GDU propagation delays (tdelon, tdeloff) are specified in the electrical parameter Table E-1. The FET turn on times (tHGON) are load dependent but are specified for particular loads in the electrical parameter Table E-1.
The current sense amplifier delay is highly dependent on external components.
The ADC delay until a result is available is specified as the conversion period NCONV in Table C-1.
1.13.3.3 Static Timing Operation
The timing frame is static if it is the same in every control cycle (defined by reload frequency) and is relative to start of the control cycle. The only settings modified from one control cycle to the next one are the PWM duty cycle registers.
The main control cycle synchronization event is the PMF reload event. The PMF reload event can be generated every n PWM periods. This mode can optionally be extended by a timer channel trigger to PMF to change the PWM channel operation (e.g. used for BLDCM commutation). In this case, the PMF configuration can propagate the

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trigger through the control loop or can prevent propagation so the static timing of the control cycle and inter-block coherency are not affected by the trigger.
At the end of the conversion sequence the first ADC command from the new sequence is loaded and the ADCx waits for the next trigger_x. The PTU continues to generate the trigger_x events for each trigger time from the list until a new reload or async_reload occurs.
Before the upcoming reload event the CPU: · reads the ADC results from the buffered Conversion Result List · clears the conversion complete flag · services the reload by setting new duty cycle values · sets the PTULDOK bit (corresponding to glb_ldok) to signal the duty cycle coherence
The CPU actions are typically performed in an ISR triggered by the conversion complete flag.
1.13.3.4 Static Timing Fault Handling
The following Faults and/or errors can occur: · Desaturation error, Overvoltage, Undervoltage, External fault
The application run-time error is handled by the GDU without CPU interaction. Firstly the FETs are disabled and the PMF signals switched to an inactive state. To re-enable the operation first the GDU fault and then PWM fault must be cleared, to automatically re-enable the FET driving at the next PWM boundary.
· PTU reload overrun error
This is an application run-time error caused by the CPU not setting PTULDOK on time. Servicing this type of error is application dependent and may range from a further reload attempt to a total shut down.
· PTU trigger generator reload error, PTU trigger generator error
Since all timing is static, this error should only occur during application debugging. This type of error occurring in a static timing configuration indicates possible data corruption. This can be serviced by a control loop shutdown.
· PTU memory access error, Memory access double bit ECC error
This type of error occurring in an application indicates data corruption. This can be serviced by a control loop shutdown.
· ADC sequence overrun, ADC command overrun, ADC command error
Since all timing is static, this error should only occur during application debugging. This type of error occurring in an application indicates possible data corruption. This can be serviced by a control loop shutdown.
1.13.3.5 Dynamic Timing Operation
The timing frame is dynamic if the following are modified on a cycle by cycle basis: · PMF - duty cycle value registers (PMF_VALx), modulo registers

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· PTU - Trigger Event List (PTU_TELx) · ADC - Command Sequence List (ADCx_CSL)
The main philosophy is that all cycle-by-cycle settings for cycle n need to be done within cycle n-1. The main control cycle synchronization event is the PMF reload event, which can be generated every n PWM periods.
This mode can optionally be extended by a timer channel trigger PMF to change PWM channel operation (e.g. used for BLDCM commutation).
The event flow is the same as for static timing.
Before the upcoming reload event the CPU: · reads the ADC results from the buffered Conversion Result List · clears the conversion complete flag · services the reload by setting new duty cycle values and a new PMF modulo value · updates the non-active PTU_TELx · updates the non-active ADCx_CSL · sets the PTULDOK bit (corresponding to glb_ldok) to signal the duty cycle coherence
The CPU actions are typically performed in an ISR triggered by the conversion complete flag.
1.13.3.6 Dynamic Timing Fault Handling
The following Faults and/or errors can occur: · Desaturation error, Overvoltage, Undervoltage, External fault
The application run-time error is handled by the GDU without CPU interaction. Firstly the FETs are disabled and the PMF signals switched to an inactive state. To re-enable the operation first the GDU fault and then PWM fault must be cleared, to automatically re-enable the FET driving at the next PWM boundary.
· PTU reload overrun error
This is an application run-time error caused by the CPU not setting PTULDOK on time. Servicing this type of error is application dependent and may range from a further reload attempt to a total shut down.
· PTU trigger generator reload error, PTU trigger generator error
This indicates an application run-time error caused by a settings mismatch. Servicing this type of error is application dependent. In some cases, the ADC values for the current control cycle can be ignored.
· PTU memory access error, Memory access double bit ECC error
This type of error occurring in an application indicates possible data corruption. This can be serviced by a control loop shutdown.
· ADC sequence overrun, ADC command overrun, ADC command error
This indicates an application run-time error caused by a settings mismatch. Servicing this type of error is application dependent. In some cases, the ADC values for the current control cycle can be ignored.

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1.13.3.7 Asynchronous Timing
This case is an extension of the dynamic timing case by an asynchronous event generated by the Timer. Note the asynchronous term is referenced to the control cycle.
The timing frame is the same as in dynamic timing case plus it can be asynchronously restarted at any time within the control cycle.
At the asynchronous commutation_event
· the PMF actions are: 1. counter re-start, re-initialization 2. PWM configuration re-initialization according to the selected PWM settings (center/edge-aligned
pattern, normal/inverted type etc.) 3. re-initialization of the dead time generators (in case the commutation takes place at a time when
one of the dead times is being generated) 4. re-initialization of the PWM outputs according to pre-set PWM channel output settings in double
buffered registers (mask, swap, output control) 5. re-initialization of the automatic fault clearing 6. generates async_reload event for the PTU 7. optionally updates the PWM duty cycle values based on LDOK state · the PTU actions are: 1. abortion of the trigger_x event generation 2. re-initialization and re-start the PTU counter 3. update of the current list index TGxList based on the glb_ldok state 4. fetch first trigger time from updated TGxList 5. passes the async_reload event immediately to the ADC (if the PTU is enabled) 6. generates the reload event for the ADC · the ADC actions are: 1. the conversion in progress is completed 2. the ADC conversion sequence is aborted and the SEQA flag is set to indicate that the final
conversion occurred during the abortion process (potentially coinciding with a commutation and is thus less precise than under normal conditions) 3. update of the current lists index ADxLists 4. re-start of the conversion sequencing upon successful abortion - fetches the first ADC command from the ADCx_CSL, re-sets the result pointer to the top of the list Note: in case the lists index ADxLists is not updated at the sequence abortion the new restarted A/D conversions will overwrite the previously converted results. · the GDU actions are: 1. standard operation

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1.13.3.8 Control Loop Startup Guidelines
The sequence for control loop start up is to firstly configure the signal measurement (inputs/feedback). Once the measurement is properly configured (correct value is measured at defined time) the output actuation (control action) is configured. The following modules are involved in signal measurements.
· TIM (to identify asynchronous commutation) [BLDC applications only] · PMF (to generate main synchronous events for PTU and ADC) · PTU (to generate delay relative to synchronous events generated by PMF) · ADC (to acquire analog signals under synchronous control) · GDU (zero crossing comparators, Back-EMF muxing) [application dependent]
The TIM OC0 channel identifies the commutation event and restarts the PMF counter. In order to establish this link TIM and PMF need to be configured and started. Then to sample accurately within one PMF cycle the PTU needs to be used, so the next step is to configure the PTU to establish PMF to PTU link. The PTU sends triggers to the ADC to perform a measurement of control signals. So the next step is to configure the ADC. In some cases the GDU involvement is required and therefore configured.
The control action involves the PMF (to generate the duty cycle for GDU) and the GDU (to propagate the signal to the MOSFETs). Since the PMF has already been configured for the measurements, only the GDU need be configured to complete startup. Sometimes the GDU can be configured earlier but the GDU output is always enabled last.
The recommended startup sequence is summarized as follows: · Configure TIM and PMF to establish the link between TIM OC0 commutation event and PMF · Configure PTU to establish the PMF to PTU link and ensure correct sampling within PMF cycle · Configure the ADC · Configure the GDU
1.13.3.9 Control Loop Shutdown Guidelines
1. Remove energy stored in the system after the power stage kinetic energy - stop all rotating/moving mass magnetic energy - gracefully drive currents to zero
2. Put GDU and PMF outputs to safe state
1.13.3.10 Control Loop Stop Mode Considerations
In Stop mode the PMF, PTU, ADC can not run because the bus clock is not running. Thus the GDU must transition to a disabled state. Before entering Stop mode the application must perform the following steps:
1. Remove energy stored in the system after the power stage kinetic energy - stop all rotating/moving mass magnetic energy - gracefully drive currents to zero
2. Put GDU and PMF outputs to safe state 3. Verify GDU and PMF safe states

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4. Verify fault flags and service if necessary 5. Execute the STOP instruction
The return from stop is expected in reverse order: 1. On returning from Stop mode the clocks are automatically enabled coherently 2. Initialize and check device proper functionality (charge pump etc.) 3. Check functionality of the external system 4. Initializes control loop operation, however with PMF and GDU outputs still in safe state 5. Read the ADC values to check the system 6. Start driving energy into the system based on the measurements from the previous step, the PWM duty cycle values are calculated 7. PMF and GDU outputs are enabled (actively driven)
The device does not support putting the FETs in an active driving state during STOP as the GDU charge pump clock is not running. This means the device cannot be put in stop mode if the FETS need to be in an active driving state to protect the system from external energy supply (e.g. externally driven motorgenerator).
NOTE It is imperative, that whatever the modules perform on entering/exiting Stop mode, the pre-set complementary mode of operation and dead time insertion must be guaranteed all the times.
1.13.3.11 Application Signal Visibility
In typical motor control applications, TIM OC0 is used internally to indicate commutation events. To switch off OC0 visibility at port pin PT0:
· Disable output compare signal on pin PT0 in TIM: OCPD[OCPD0]=0b1.
1.13.3.12 Debug Signal Visibility
Depending on required visibility of internal signals on port pins enable the following registers: · Set [PWMPRR]=0b1 in PIM if monitoring of internal PWM waveforms is needed. PWM0_[5:3] are driven out on pins PT[2:0] and PWM0_[2:0] on pins PP[2:0]. · Enable output compare channel OC0 to output commutation event on pin PT0 in TIM: OCPD[OCPD0]=0b0. · Set PTUDEBUG[PTUREPE]=0b1 in PTU to output the reload event. · Set PTUDEBUG[PTUTxPE]=0b1 with x=0,1 in PTU to output the trigger events.
1.13.4 BDCM Complementary Mode Operation
This section describes BDCM control using center aligned complementary mode with deadtime insertion.

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The DC Brushed motor power stage topology is a classical full bridge as shown in Figure 1-11. The DC Brushed motor is driven by the DC voltage source. A rotational field is created by means of commutator and brushes on the motor. These drives are still very popular because sophisticated calculations and algorithms such as commutation, waveform generation, or space vector modulation are not required.
Figure 1-11. DC Brushed Motor External Configuration
+ 1/2 U

PWM 0

PWM 2

A

B

- 1/2 U

PWM 1

PWM 3

Usually the control consists of an outer, speed control loop with inner current (torque) control loop. The inner loop controls DC voltage applied onto the motor winding. The control loop is calculated regularly within a given period. In most cases, this period matches the PWM reload period.
Driving the DC motor from a DC voltage source, the motor can work in all four quadrants. The complementary mode of operation with deadtime insertion is needed for smooth reversal of the motor

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current (motor torque), hence smooth full four quadrant control. Usually the center-aligned PWM is chosen to lower electromagnetic emissions.
Figure 1-12. BDCM Control Loop Configuration

PMF

GDU

dc_bus_voltage
M

sine/ cosine sensor

reloada

reload

dc_bus_current0

glb_ldok
PTU trigger_0

reload

trigger_1

ADC0 ADC1

The PWM frequency selection is always a compromise between audible noise, electromagnetic emissions, current ripples and power switching losses.
The BDCM control loop goal is to provide a controlled DC voltage to the motor winding, whereby it is controlled cycle-by-cycle using a speed, current or torque feedback loop.
The center aligned PWM waveforms generated by the PMF module are applied to the bridge as shown in Figure 1-13 whereby the base waveform for PWM0_0 and PWM0_1 is depicted at the top and the complementary PWM0_0 and PWM0_1 waveforms are shown with deadtime insertion depicted by the gray phases before the switching edges.

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PWM0_[1:0] base PWM0_0 PWM0_1

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Figure 1-13. BDCM Complementary Mode Waveform

TPWM

PWM0_[3:2] base PWM0_2

PWM0_3

Assuming first quadrant operation, forward accelerating operation, the applied voltage at node A must exceed the applied voltage at node B (Figure 1-11). Thus the PWM0_0 duty cycle must exceed the PWM0_2 duty cycle.
The duty cycle of PWM0_0 defines the voltage at the first power stage branch.
The duty cycle of PWM0_2 defines the voltage at the second power stage branch.
Modulating the duty cycle every period using the function FPWM then the duty cycle is expressed as: PWM0_0 duty-cycle = 0.5 + (0.5 * FPWM); For -1<=FPWM <= 1; PWM0_2 duty-cycle = 0.5 - (0.5 * FPWM)

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1.13.5 BLDC Six-Step Commutation

1.13.5.1 Hall Sensor Triggered Commutation

Figure 1-14. BLDC Configuration With Hall Sensors

TIM0
IC1
OC0 commutation_event
PMF

PIM
XOR PTIT
GDU

EVDD1 PT1 PT2 PT3

Hall Sensor

dc_bus_voltage
M

reload
PTU

async_reload
glb_ldok trigger_0

reload

async_reload

ADC0

dc_bus_current

This BLDC application uses Hall sensor signals to create commutation triggers. The integrated sense amplifier and an ADC module are used to measure DC bus current, for torque calculation. The DC bus voltage measurement is used in the control algorithm to counter-modulate the PWM such that the variation of the DC-bus voltage does not affect the motor current closed loop. The configuration is as follows:
1. Connect the three Hall sensor signals from the motor to input pins PT3-1.
2. Set [T0IC1RR=1] in the register MODRR2 to establish the link from Hall sensor input pins to TIM input capture channel 1.
3. Setup TIM IC1 for speed measurement of XORed Hall sensor signals. Enable interrupt on both edges.
4. Enable TIM OC0 and select toggle action on output compare event: TCTL2[OM0:OL0]=01.
5. Configure PMF for edge-aligned PWM mode with or without restart at commutation: PMFENCx[RSTRT]. If using the restart option, then select generator A as reload signal source and keep the following configurations at their default setting: multi timebase generators (PMFCFG0[MTG]=b0), reload frequency (PMFFQCx[LDFQx]=b0), prescaler (PMFFQCx[PRSCx]=b00).
6. Enable PMF commutation event input: PMFCFG1[ENCE]=1.

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7. Read port register PTIT[3:1] to determine starting sector. 8. Startup motor by applying PWM to the related motor phase. 9. In IC1 interrupt ISR calculate the delay to next commutation and store value to output compare
register. Update registers with next values of mask and swap. 10. On next output compare event the buffered mask and swap information is transferred to the active
PMF registers to execute the commutation.
1.13.5.2 Sensorless Commutation
Figure 1-15. Sensorless BLDC Configuration

TIM0
OC0 commutation_event
PMF

GDzUero crossing
comparators

dc_bus_voltage
M

GPHS dc_bus_current0 dc_bus_current1

reloada async_reload

reload

async_reload

glb_ldok
PTU trigger_0

reload

trigger_1 async_reload

PHMUX P1
back-EMF P2 P3
ADC0
ADC1

To calculate the commutation time in a sensorless motor system the back-EMF zero crossing event of the currently non-fed phase within an electrical rotation cycle must be determined. For fast motor rotation, the ADC is used to measure the back-EMF voltage and the DC bus voltage to determine the zero crossing time. For slow motor rotation the GPHS register can be polled. In either case the zero crossing event is handled

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by the CPU monitoring flags or responding to interrupts. The TIM then generates the commutation_event under CPU control, based on the zero crossing time.
1. Enable TIM OC0 and select toggle action on output compare event: TCTL2[OM0:OL0]=0b01. 2. Enable PMF commutation event input: PMFCFG1[ENCE]=0b1. 3. Enable internal ADC channel for measuring the phase voltages from the muxed GDU outputs. 4. Align rotor to stator field. Initialize phase MUX using register GDUPHMUX. 5. Startup motor by applying PWM to an arbitrary motor phase. 6. Take samples of the phase voltages periodically based on PWM cycle to detect zero crossing. 7. Calculate the delay to next commutation and store value to output compare register. Update
registers with next values of mask and swap. 8. On next output compare event the buffered mask and swap information are transferred to the active
PMF register to execute the commutation.
1.13.6 PMSM Control
PMSM control drives all 3 phases simultaneously with sinusoidal waveforms. Both sensorless and SineCosine position sensor control loop operation are supported.
1.13.6.1 PMSM Sensorless Operation
In this configuration the PMSM stator winding currents are driven sinusoidally and the back EMF waveform is also sinusoidal. Thus all 3 phases are active simultaneously. The rotor position and speed are determined by the current and calculated voltages respectively. The back EMF voltage is calculated based on the currents.
1. Configure PMF for complementary mode operation. 2. Configure PMF for center aligned or phase shifted operation. 3. Select correct PMF deadtime insertion based on external FET switches. 4. Enable GDU current sense opamps for measuring the phase currents from 2 external shunts. 5. Map the output pin of each current sense opamp to the ADC input. 6. Optionally use GDU phase comparators for zero crossing detection to correct deadtime distortion. 7. Fetch targeted motor speed parameter from external source (e.g. SCI) 8. Configure PMF period and duty cycle. 9. Startup motor by applying FOC startup algorithm. 10. Take samples of the phase currents periodically based on PWM cycle to determine motor speed. 11. Calculate FOC algorithm to determine back EMF and motor position.

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Figure 1-16. Sensorless PMSM Control Loop Configuration

IS0 IS1

zero crossing

GDU

phase comparison

IS2

dc_bus_voltage
M

dc_bus_current0 dc_bus_current1

reloada reload

glb_ldok
PTU trigger_0

ADC0

trigger_1 reload

ADC1

1.13.6.2 PMSM Operation With Sine-Cosine Position Sensor
In this configuration the PMSM stator winding currents are driven sinusoidally and the back EMF waveform is also sinusoidal. Thus all 3 phases are active simultaneously. The back EMF voltage is calculated based on the currents. The rotor position and speed are determined by a sine/cosine sensor, which generates sinusoidal sine/cosine signals, indicating the angle of the rotor in relation to sensor windings. The sensor is supplied by the EVDD1 pin.
1. Configure PMF for complementary mode operation. 2. Configure PMF for center aligned or phase shifted operation. 3. Select correct PMF deadtime insertion based on external FET switches. 4. Enable GDU current sense opamps for measuring the phase currents from external shunts. 5. Map the output pin of each current sense opamp to the ADC input.

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6. Map the sine/cosine input signals to ADC input channels. 7. Configure the EVDD1 pin as output. 8. Optionally use GDU phase comparators for zero crossing detection to correct dead time distortion. 9. Fetch targeted motor speed parameter from external source (e.g. SCI) 10. Configure PMF period and duty cycle. 11. Start motor by applying startup algorithm. 12. Sample the sine/cosine voltages periodically based on PWM cycle to determine motor position. 13. Use FOC algorithm to determine back EMF and motor speed.
Figure 1-17. PMSM Sine/Cosine Control Loop Configuration

PMF

IS0 IS1

zero crossing

GDU

phase comparison

IS2

dc_bus_voltage

M

dc_bus_current0 dc_bus_current1

reload

glb_ldok
PTU trigger_0

ADC0

trigger_1 reload

ADC1

sine/cosine sensor

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1.13.6.3 Dead time Distortion Correction
PMSM motor control applications driven by sinusoidal voltages by default require zero crossing information of phase currents to determine the point in time to change sign of deadtime compensation value to be added to duty cycles.
The GDU phase comparator signals are connected internally to the PMF ISx inputs. This allows the dead time distortion correction to be applied directly based on the phase status.
1. Align rotor to stator field. 2. Await phase comparator status change. 3. Switch to alternate duty cycle register to compensate distortion.

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1.13.7 Power Domain Overview (All devices except ZVMC256)

The power domains are illustrated in Figure 1-18. More detailed information is included in the individual module descriptions.

OPT L = LINPHY package option OPT C = CANPHY package option

Figure 1-18. Power Domain Overview

VRBATP L

VSSB

BST

VSUP (12V/18V)

VLINSUP

GHHDF

INT

LINPHY

LIN VRBATP

(OPT L)

LGND (OPT L)

BOOST GBOE EXTCON

BATS
ADC INT
INTXON EXTXON

VREG_AUTO

GFDE LDO

GCPE INT

CPS GLVLSF

VCP
CP VLS_OUT
(11V) VLS

(OPT C) BCTLC

VDDC (OPT C) (5V)
VDD VDDF

PORF

1.8V RES

VDDA PAD8
VSSA

VDDA

VRH

ADC

VRL_SEL VRH_SEL

VRL

VSSA

CORE RAM's
PLL IRC OSC

5V 2.8V
FLASH

LG

VRBATP

GDU
LVRF

LS

RES

BCTL VDDX

PADS

GPIO

VSSX

VSS
The system supply voltage VRBATP is a reverse battery protected input voltage. It must be protected against reverse battery connections and must not be connected directly to the battery voltage (VBAT).
The device supply voltage VSUP provides the input voltage for the internal regulator, VREG_AUTO, which generates the voltages VDDX, VDD and VDDF. The VDDX domain supplies the device I/O pins, VDDA supplies the ADC and internal bias current generators. The VDDA and VDDX pins must be connected at board level, they are not connected directly internally. ESD protection diodes exist between VDDX and VDDA, therefore forcing a common operating range. The VDD domain supplies the internal device logic. The VDDF domain supplies sections of the internal Flash NVM circuitry.

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The device supports the use of an external PNP to supplement the VDDX supply, for reducing on chip power dissipation. In this configuration, most of the current flowing from VRBATP to VDDX, flows through the external PNP. This configuration, using the BCTL pin, can be enabled by register bits EXTXON and INTXON.
The maximum current that can be sourced by the voltage regulator without the external PNP is specified as IDDX, for different VSUP ranges, in the electrical parameter appendices. Depending on activity and external loading, an application current may exceed this specification limit. In such cases the external PNP configuration must be used.
A supply for an external CANPHY is offered via external device pins BCTLC and VDDC, whereby BCTLC provides the base current of an external PNP and VDDC is the CANPHY supply (output voltage of the external PNP). This is only available in the CANPHY package option. This configuration can be enabled by the register bit EXTCON. An external diode is recommended between VDDC and VDDA. The purpose of this diode is to prevent over-voltage on VDDC during power-up, in case there is no load connected to VDDC and the regulator has a residual charge from the previous power-up.
The LINPHY pull-up resistor is internally connected to VLINSUP.
The ADC register bit VRH_SEL maps the ADC reference VRH to VDDA or to the device pin PAD8.

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1.13.8
VRBATP

Power Domain Overview (ZVMC256)

Figure 1-19. Power Domain Overview (ZVMC256)

VRBATP L

VSSB

BST

VSUP (12V/18V)

BCTLC VDDC
VRBATP VSSC
BCTLS1 SNPS1 VDDS1
VRBATP
BCTLS2 SNPS2 VDDS2 VDD VDDF VDDA
VSSA

CANPHY 5V

BOOST GBOE EXTCON

BATS
ADC INT
INTXON EXTXON

VREG_AUTO

5V 1.8V

5V 2.8V

GFDE LDO

GCPE INT

CPS GLVLSF

GDU

VCP
CP VLS_OUT
(11V) VLS
LG
LS VRBATP

PORF

5V RES

VDDA

VRH
ADC
VRL

VRL_SEL VRH_SEL

VSSA

CORE RAM's
PLL IRC OSC

FLASH

LVRF

RES

BCTL VDDX

PADS

GPIO

VSSX

VSS
The system supply voltage VRBATP is a reverse battery protected input voltage. It must be protected against reverse battery connections and must not be connected directly to the battery voltage (VBAT).
The device supply voltage VSUP provides the input voltage for the internal regulator, VREG_AUTO, which generates the voltages VDDX, VDD and VDDF. The VDDX domain supplies the device I/O pins, VDDA supplies the ADC and internal bias current generators. The VDDA and VDDX pins must be connected at board level, they are not connected directly internally. ESD protection diodes exist between VDDX and VDDA, therefore forcing a common operating range. The VDD domain supplies the internal device logic. The VDDF domain supplies sections of the internal Flash NVM circuitry.

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The device supports the use of an external PNP to supplement the VDDX supply, for reducing on chip power dissipation. In this configuration, most of the current flowing from VRBATP to VDDX, flows through the external PNP, using the BCTL pin for PNP base current control. The configuration can be selected by register bits EXTXON and INTXON.
The maximum current that can be sourced by the voltage regulator without the external PNP is specified as IDDX, for different VSUP ranges, in the electrical parameter appendices. Depending on activity and external loading, an application current may exceed this specification limit. In such cases the external PNP configuration must be used.
A supply for the internal CANPHY is offered via device pins BCTLC and VDDC, whereby BCTLC provides the base current of an external PNP and VDDC is the CANPHY supply (output voltage of the external PNP). This configuration can be enabled by the register bit EXTCON.
Two separate 5V range supplies (VDDS1 and VDDS2) are provided for external (sensor) components. These supplies also use external PNP configurations, whereby the PNP base current is controlled by BCTLS1 and BCTLS2 for VDDS1 and VDDS2 respectively.
The VDDS1 and VDDS2 supplies feature sense inputs SNPS1 and SNPS2, to detect a short circuit or over current condition and subsequently limit the current to avoid damage.
For each ADC instantiation, the ADC register bit VRH_SEL maps the ADC reference VRH to VDDA or to a VDDS of a tracker regulator. The Figure 1-19 example only shows one ADC to VDDS connection.
1.13.8.1 Voltage Domain Monitoring
The BATS module monitors the voltage on the VSUP pin, providing status and flag bits, an interrupt and a connection to the ADC, for accurate measurement of the scaled VSUP level.
The POR circuit monitors the VDD and VDDA domains, ensuring a reset assertion until an adequate voltage level is attained. The LVR circuit monitors the VDD, VDDF and VDDX domains, generating a reset when the voltage in any of these domains drops below the specified assert level. The VDDX LVR monitor is disabled when the VREG is in reduced power mode. A low voltage interrupt circuit monitors the VDDA domain.
The GDU high side drain voltage, pin HD, is monitored within the GDU and mapped to an interrupt. A connection to the ADC is provided for accurate measurement of a scaled HD level.
1.13.8.2 FET-Predriver (GDU) Supplies
A dedicated low drop regulator is used to generate the VLS_OUT voltage from VSUP. The VLS_OUT voltage is used to supply the low side drivers and can be directly connected to the VLS inputs of each low side driver. For FET-predriver operation at lower VSUP levels, a boost circuit can be enabled by the GBOE register bit. The boost circuit requires Shottky diodes, a coil and capacitors, as shown in Figure 1-18. More detailed information is included in the GDU module description.
1.13.8.2.1 Bootstrap Precharge
The FET-predriver high side driver must provide a sufficient gate-source voltage and sufficient charge for the gate capacitance of the external FETs. A bootstrap circuit is used to provide sufficient charge, whereby

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the capacitor CBS is first charged to VLS_OUT via an external diode (GDUV4) or internal transistor (GDUV5), when the low side driver is active Figure 1-20. When the high side driver switches on, the charge on this capacitor, supplies the FET-predriver via the VBSx pin. The CBS capacitor can only be charged if the low side driver is active, so after a long period of inactivity of the low side driver, the CBS capacitor becomes discharged. In this case, the low side driver must be switched on to charge CBS before commencing high side driving. The time it takes to discharge the bootstrap capacitor CBS can be calculated from the size of the bootstrap capacitor CBS and the current on VBSx pin in the high side inactive phase.
The bootstrap capacitors must be precharged before turning on the high-side drivers for the first time. This can be done by using the PMF software output control mechanism:

PMFOUTC = 0x3F; PMFOUTB = 0x2A;

// SW control on all outputs // All high-sides off, all low-sides on

The PWM0 signals should be configured to start with turning on the low-side before the high-side drivers in order to assure precharged bootstraps. Therefore invert the PWM0 signals:

PMFCINV = 0x3F;

// Invert all channels to precharge bootstraps

1.13.8.2.2 High Side Charge Pump
A charge pump voltage is used to supply the high side FET-predriver with enough current to maintain the gate source voltage. To generate this voltage an external charge pump is driven by the pin CP, switching between 0V and 11V. The pumped voltage is then applied to the pin VCP.
At 100% duty cycle operation the low-side turn on time is zero during a masked commutation cycle before the attempting to turn on the high side drivers. This can cause bootstrap charge to decay.
In order to speed-up the high-side gate voltage level directly after commutation, the software should drive the first PWM cycle with a duty cycle meeting an on-time of at least tminpulse for the low-side drivers and then switch back to 100% again.
The recommended procedure for BLDC applications is to use the manual correction method (PMFCCTL[ISENS]) as described below:
Set odd PMF values to alternative duty cycle. At commutation event when one of the three high-side drivers is turned on (every 120°) set the PMFCCTL[IPOLx] bits and clear them at the next PWM reload event.
Given unipolar switching mode:
// TIM OC0 ISR: if ((PMFOUTC == 0x1c) || (PMFOUTC == 0x07) || (PMFOUTC == 0x31)) // all high-side turn-on sectors
PMFCCTL = 0x17; // select odd PMF values

// PMF reload ISR:
PMFCCTL = 0x10; // select even PMF values
The GDU high side drain voltage, pin HD, is supplied from VBAT through a reverse battery protection circuit. In a typical application the charge pump is used to switch on an external NMOS, N1, with source connected to VBAT, by generating a voltage of VBAT+VLS-(2xVdiode). In a reverse battery scenario, the external bipolar turns on, ensuring that the HD pin is isolated from VBAT by the external NMOS, N1.

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Figure 1-20. High Side Supply and Charge Pump Concept

VBAT VLS_OUT (11V)

S N1
D
1nF

GCPCD GCPE

10nF CP
11V 0V
VCP

DIODE NOT REQUIRED WHEN USING GDUV5

HD

VBSx

HGx

CBS

HSx

HIGH SIDE

1000F (Motor Dependent)

LOW SIDE

Diode voltage drop = Vdiode

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Rev. No. (Item No.)
V03.08
V03.09 V03.10 V03.11 V03.12
V03.13 V03.14
V03.15 V03.16 V03.17 V03.18

Date 9 Jan 2015
22 Jan 2015 23 Jan 2015 27 Jan 2015 10 Feb 2015
16 Feb 2015 19 Feb 2015
16 Mar 2015 22 Apr 2015 12 Oct 2015 12 Dec 2015

Table 2-1. Revision History

Sections Affected

Substantial Change(s)

Table 2-5 Table 2-6 Table 2-7 2.3.1/116 Table 2-9 Table 2-11

· Corrections

· Minor changes in wording

Figure 2-5 · Corrected T0IC3RR1-0 description Table 2-13

2.3.1/116 · Changed T0C2RR1-0 specification 2.3.2.3/128

2.1.1/104 Table 2-5 Table 2-6

· Added TIM1 · Changed PWM0 routing

2.1.1/104 · Fixed typos and formatting

2.1.1/104 2.1.2/107 2.2/108 Table 2-39 Table 2-41

· Fixed typos and formatting

2.1.1/104 · Format updates 2.2/108

2.1.1/104 · Fixed typos and formatting

2.3.4/140 · Fixed typos and formatting

2.3.2.3/128 · Added bit description for T1IC0RR (MODRR2 register)

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2.1 Introduction

2.1.1 Overview

The S12ZVM-family port integration module establishes the interface between the peripheral modules and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins.

This document covers:

· Port E

GPIO

External Oscillator

Pins

PTE1

XTAL

PE1

PTE0

EXTAL

PE0

· Port T

GPIO
PTT3

PWM01
PWM0_3
1

TIM0
IOC0_3

PMF
PWM1_2
1

PTT2

PWM0_7
1

IOC0_2

PWM1_5PWM1_0

2

1

SPI0
SS0
SCK0

PTT1 PTT0

IOC0_1 PWM1_4

PWM0_5
1

IOC0_0

PWM1_3

MOSI0 MISO0

LINPHY0/ SCI0 HVPHY0 PTU

Pins
PT3

PT2

TXD0

LPDC03

PTURE2

PT1

RXD0

PT0

1. Only available for ZVMC256 2. Not available for ZVMC256 3. Only available for ZVML128, ZVML64, ZVML32, ZVML31, ZVM32, and ZVM16

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· Port S

GPIO/ KWU

DBG

PTS5

Chapter 2 Port Integration Module (S12ZVMPIMV3)

CANPHY0 LINPHY0/

SCI1 CAN01

4

HVPHY0 TIM1

TIM0

PTU

SPI0
SS0

DBG
PDO2

Pins
PS53

PTS4

PTS3

DBGEE V

TXD1

PTS2

RXD1

CPTXD0 CPRXD0

IOC1_14 IOC1_04

SCK0

PDOCLK
2

PS43

MOSI0

PS3

MISO0

PS2

PTS1

TXD1

TXCAN0

CPDR

LPTXD0
5

IOC0_26 PTUT1

SCK04

PS1

PTS0

RXD1 RXCAN0

LPRXD0
5

IOC0_16 PTUT0

SS04

PS0

1. Only available for ZVMC256, ZVMC128, ZVML128, ZVMC64, ZVML64, and ZVML32 2. Only available for ZVMC128, ZVML128, ZVMC64, ZVML64, and ZVML32 3. Not available for ZVMC256 4. Only available for ZVMC256 5. Only available for ZVML128, ZVML64, ZVML32, ZVML31, ZVM32, and ZVM16 6. Only available for ZVMC256, ZVML31, ZVM32, and ZVM16

· Port P
GPIO/KWU
PTP2

PWM01

PMF
PWM1_2

ECLK

PMF fault IRQ/XIRQ

Pins
PP22

PTP1

PWM0_1

PWM1_1

IRQ

PP1

PTP0

PWM1_0PWM1_5

2

1

ECLK

FAULT5

XIRQ

PP0

1. Only available for ZVMC256 2. Not available for ZVMC256

· Port L

HVI

TIM0

Pins

PTIL01

IC0_2

PL01

1. Only available for ZVMC256

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· Port AD
GPIO/KWU

ADC1

ADC0

PTADH7

AN0_7

SPI0

PTADH6

AN0_6

PTADH5

AN0_5

PTADH4

AN1_7

PTADH3

AN1_6

PTADH2

AN1_5

PTADH1

AN1_4

PTADH0

AN1_3

VRH2

GDU

PTU

DBG
PDOCLK

Pins
PAD151

PDO

PAD141

PTURE

PAD131

PAD121 PAD111 PAD101 PAD91

PAD8

PTADL7

AN1_2

AMPP1

PAD7

PTADL6

AN1_1

SS0

AMPM1

PAD6

PTADL5

AN1_0

AMP1

PAD5

PTADL4

AN0_4

PAD4

PTADL3

AN0_3

PAD3

PTADL2

AN0_2

AMPP0

PAD2

PTADL1

AN0_1

AMPM0

PAD1

PTADL0

AN0_0

AMP0

PAD0

1. Only available for ZVMC256 2. Not available for ZVMC256
Most I/O pins can be configured by register bits to select data direction and to enable and select pullup or pulldown devices.

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NOTE This document shows the superset of all available features offered by the S12ZVM device family. Refer to the package and pinout section in the device overview for functions not available for a particular device or package option.

2.1.2 Features
The PIM includes these distinctive registers:
· Data registers and data direction registers for ports E, T, S, P and AD when used as general-purpose I/O
· Control registers to enable pull devices and select pullups/pulldowns on ports E, T, S, P and AD · Control register to enable open-drain (wired-or) mode on port S · Control register to enable digital input buffers on port AD and L1 · Interrupt enable register for pin interrupts and key-wakeup (KWU) on port S, P, AD, and L1 · Interrupt flag register for pin interrupts andkey-wakeup (KWU) on port S, P, AD, and L1 · Control register to configure IRQ pin operation · Control register to enable ECLK output · Routing registers to support signal relocation on external pins and control internal routings:
-- SPI0 to alternative pins -- Various SCI0-LINPHY0 routing options supporting standalone use and conformance testing2 -- Various MSCAN0-CANPHY0 routing options for standalone use and conformance testing1 -- Internal RXD0 and RXD1 link to TIM0 input capture channel (IC0_3) for baud rate detection -- Internal ACLK link to TIM0 input capture channel -- 3 pin input mux to one TIM0 IC channel -- 2 TIM0 channels to alternative pins3 -- PMF channels to GDU and/or pins
A standard port pin has the following minimum features:
· Input/output selection · 5V output drive · 5V digital and analog input · Input with selectable pullup or pulldown device
Optional features supported on dedicated pins:
· Open drain for wired-or connections
· Interrupt input with glitch filtering
· High current drive strength from VDDX with over-current protection
1. Only available for ZVMC256 2. Only available for ZVML128, ZVML64, ZVML32, and ZVML31 3. Only available for S12ZVMC256, S12ZVML31, S12ZVM32, and S12ZVM16

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· Selectable drive strength for high current capable outputs
2.2 External Signal Description
This section lists and describes the signals that do connect off-chip.
Table 2-2 to Table 2-8 show all pins with the pins and functions that are controlled by the PIM. Routing options are denoted in parenthesis.
NOTE If there is more than one function associated with a pin, the output priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority).Inputs do not arbitrate priority unless noted differently in Table 2-40.

Table 2-2. BKGD Pin Functions and Priorities

ZVMC256 ZVMC128\64 ZVML128/64/32
ZVML31 ZVM32/16

Port

Pin Name

Pin &

Function Priority

I/O

- BKGD      MODC1 I      BKGD I/O

1. Function active when RESET asserted.

Description
MODC input during RESET S12ZBDC communication

Routing Pin Function Register Bit after Reset

--

BKGD

--

Table 2-3. Port E Pin Functions and Priorities

ZVMC256 ZVMC128\64 ZVML128/64/32
ZVML31 ZVM32/16

Port

Pin Name

Pin &

Function Priority

I/O

E PE1      XTAL      PTE[1] I/O
PE0      EXTAL      PTE[0] I/O

Description
CPMU OSC signal General-purpose CPMU OSC signal General-purpose

Routing Pin Function Register Bit after Reset

--

GPIO

--

-- --

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Table 2-4. Port AD Pin Functions and Priorities

ZVMC256 ZVMC128\64 ZVML128/64/32
ZVML31 ZVM32/16

Port

Pin Name

Pin Function & Priority1

I/O

Description

Routing Pin Function Register Bit after Reset

AD PAD15 

PDOCLK O

DBG profiling clock

--



AN0_7 I

ADC0 analog input

--



PTADH[7]/ I/O General-purpose; with interrupt and wakeup

--

KWADH[7]

PAD14 

PDO

O

DBG profiling data output

--



AN0_6 I

ADC0 analog input

--



PTADH[6]/ I/O General-purpose; with interrupt and wakeup

--

KWADH[6]

PAD13 

PTURE O

PTU reload event

--



AN0_5 I

ADC0 analog input

--



PTADH[5]/ I/O General-purpose; with interrupt and wakeup

--

KWADH[5]

PAD12 

AN1_7 I

ADC1 analog input

--



PTADH[4]/ I/O General-purpose; with interrupt and wakeup

--

KWADH[4]

PAD11 

AN1_6 I

ADC1 analog input

--



PTADH[3]/ I/O General-purpose; with interrupt and wakeup

--

KWADH[3]

PAD10 

AN1_5 I

ADC1 analog input

--



PTADH[2]/ I/O General-purpose; with interrupt and wakeup

--

KWADH[2]

PAD9 

AN1_4 I

ADC1 analog input

--



PTADH[1]/ I/O General-purpose; with interrupt and wakeup

--

KWADH[1]

PAD8     VRH

I

ADC0&1 voltage reference high

--

     AN1_3 I

ADC1 analog input

--



PTADH[0]/ KWADH[0]

I/O

General-purpose; with interrupt and wakeup

--

GPIO

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ZVMC256 ZVMC128\64 ZVML128/64/32
ZVML31 ZVM32/16

Port

Pin Name

Pin Function & Priority1

I/O

Description

Routing Pin Function Register Bit after Reset

AD PAD7      AMPP1 I

GDU AMP1 non-inverting input (+)

--

     AN1_2 I

ADC1 analog input

--



PTADL[7]/ KWADL[7]

I/O

General-purpose; with interrupt and wakeup

--

PAD6      AMPM1 I

GDU AMP1 inverting input (-)

     (SS0) I/O

SPI0 slave select

SPI0SSRR

     AN1_1 I

ADC1 analog input

--



PTADL[6]/ KWADL[6]

I/O

General-purpose; with interrupt and wakeup

--

PAD5      AMP1 O

GDU AMP1 output

--

     AN1_0 I

ADC1 analog input

--



PTADL[5]/ KWADL[5]

I/O

General-purpose; with interrupt and wakeup

--

PAD4      AN0_4 I

ADC0 analog input

--



PTADL[4]/ KWADL[4]

I/O

General-purpose; with interrupt and wakeup

--

PAD3      AN0_3 I

ADC0 analog input

--



PTADL[3]/ KWADL[3]

I/O

General-purpose; with interrupt and wakeup

--

PAD2      AMPP0 I

GDU AMP0 non-inverting input (+)

--

     AN0_2 I

ADC0 analog input

--



PTADL[2]/ KWADL[2]/

I/O

General-purpose; with interrupt and wakeup

--

PAD1      AMPM0 I

GDU AMP0 inverting input (-)

--

     AN0_1 I

ADC0 analog input

--



PTADL[1]/ KWADL[1]

I/O

General-purpose; with interrupt and wakeup

--

PAD0      AMP0 O

GDU AMP0 output

--

     AN0_0 I

ADC0 analog input

--



PTADL[0]/ KWADL[0]

I/O

General-purpose; with interrupt and wakeup

--

GPIO

1. Signals in parentheses denote alternative module routing pins.

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Table 2-5. Port T Pin Functions and Priorities

ZVMC256 ZVMC128\64 ZVML128/64/32
ZVML31 ZVM32/16

Port

Pin Name

Pin Function & Priority1

I/O

Description

Routing Pin Function Register Bit after Reset

T PT3      (SS0) I/O

SPI0 slave select

SPI0RR SPI0SSRR



PWM1_2 O

PMF channel 2

PWM32RR PWMPRR1-0

     IOC0_3 I/O

TIM0 channel 3

T0IC3RR1-0



PWM0_3 O

PWM0 channel 3

--

     PTT[3] I/O

General-purpose

--

PT2      (SCK0) I/O

SPI0 serial clock

SPI0RR

    (PWM1_5) O

PMF channel 5

PWM54RR PWMPRR1-0



(PWM1_0) O

PMF channel 0

PWM10RR PWMPRR1-0

     IOC0_2 I/O

TIM0 channel 2

T0C2RR



PWM0_7 O

PWM0 channel 7

--

     PTT[2] I/O

General-purpose

--

PT1     PTURE O      (TXD0)2 O

PTU reload event SCI0 transmit

-- S0L0RR2-0

   (LPDC0) O LPTXD0 direct control by LP0DR[LP0DR1] S0L0RR2-0

     (MOSI0) I/O

SPI0 master out/slave in

SPI0RR

     (PWM1_4) O

PMF channel 4

PWM54RR PWMPRR1-0

IOC0_1 I/O


TIM0 channel 1

T0C1RR T0IC1RR T0IC1RR0

     PTT[1] I/O

General-purpose

--

PT0      (RXD0)2 I

SCI0 receive

S0L0RR2-0

     (MISO0) I/O

SPI0 master in/slave out

SPI0RR

     (PWM1_3) O

PMF channel 3

PWM32RR PWMPRR1-0

     IOC0_0 I/O

TIM0 channel 0

--



PWM0_5 O

PWM0 channel 5

--

     PTT[0] I/O

General-purpose

--

GPIO

1. Signals in parentheses denote alternative module routing pins. 2. Default routing for ZVMC256

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Table 2-6. Port S Pin Functions and Priorities

ZVMC256 ZVMC128\64 ZVML128/64/32
ZVML31 ZVM32/16

Port

Pin Name

Pin Function & Priority1

I/O

Description

Routing Pin Function Register Bit after Reset

S PS5  

PDO

O

DBG profiling data output

--

    SS0 I/O

SPI0 slave select

SPI0RR SPI0SSRR



PTS[5]/ KWS[5]

I/O General-purpose; with interrupt and wakeup

--

PS4  

PDOCLK O

DBG profiling clock

--

    SCK0 I/O

SPI0 serial clock

SPI0RR


PS3        

PTS[4]/ KWS[4] MOSI0 IOC1_1 (CPTXD0) (TXD1)

I/O General-purpose; with interrupt and wakeup

I/O

SPI0 master out/slave in

I/O

TIM1 channel 1

I

CANPHY0 transmit input

O

SCI1 transmit

--
SPI0RR --
M0C0RR2-0 SCI1RR

     DBGEEV I

DBG external event

--


PS2        

PTS[3]/ KWS[3] MISO0 IOC1_0 (CPRXD0) (RXD1)

I/O General-purpose; with interrupt and wakeup

I/O

SPI0 master in/slave out

I/O

TIM1 channel 0

O

CANPHY0 receive output

I

SCI1 receive

--
SPI0RR --
M0C0RR2-0 SCI1RR



PS1 









PTS[2]/ KWS[2] SCK0 PTUT1 (IOC0_2) (LPTXD0)

I/O General-purpose; with interrupt and wakeup

I/O

SPI0 serial clock

O

PTU trigger 1

I/O

TIM0 channel 2

I

LINPHY0/HVPHY0 transmit input

--
SPI0RR --
T0C2RR S0L0RR2-0



(CPDR1) O



TXCAN02 O

     TXD1 O

CANPHY0 direct control output CP0DR[CPDR1]
MSCAN0 transmit
SCI1 transmit

M0C0RR2-0
M0C0RR2-0 SCI1RR



PTS[1]/ KWS[1]

I/O General-purpose; with interrupt and wakeup

--

GPIO

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ZVMC256 ZVMC128\64 ZVML128/64/32
ZVML31 ZVM32/16

Port

Pin Name

Pin Function & Priority1

I/O

Description

Routing Pin Function Register Bit after Reset

PS0 

SS0 I/O

     PTUT0 O

(IOC0_1) I/O





SPI0 slave select
PTU trigger 0 TIM0 channel 1

   (LPRXD0) O



RXCAN02 I

LINPHY0/HVPHY0 receive output MSCAN0 receive

     RXD1 I

SCI1 receive



PTS[0]/ KWS[0]

I/O General-purpose; with interrupt and wakeup

1. Signals in parentheses denote alternative module routing pins.

2. Routing option for ZVMC256

SPI0RR SPI0SSRR
--
T0C1RR T0IC1RR T0IC1RR0
S0L0RR2-0
M0C0RR2-0
SCI1RR
--

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Table 2-7. Port P Pin Functions and Priorities

ZVMC256 ZVMC128\64 ZVML128/64/32
ZVML31 ZVM32/16

Port

Pin Name

Pin Function & Priority1

I/O

Description

Routing Pin Function Register Bit after Reset

P PP2

    (PWM1_2) O

PMF channel 2

PWM32RR PWMPRR



PTP[2]/ KWP[2]

I/O General-purpose; with interrupt and wakeup

--

PP1      IRQ

I Maskable level- or falling edge-sensitive interrupt

--

     (PWM1_1) O

PMF channel 1

PWM10RR PWMPRR



PWM0_1 O

PWM0 channel 1

--



PTP[1]/ KWP[1]

I/O General-purpose; with interrupt and wakeup

--

PP0      XIRQ

I

Non-maskable level-sensitive interrupt2

--

     FAULT5 I

PMF fault

--

     ECLK O

Free-running clock

--

(PWM1_0) O PMF channel 0 with over-current interrupt; PWM10RR



high-current capable (20 mA)

PWMPRR

GPIO

(PWM1_5) O PMF channel 5 with over-current interrupt; PWM54RR



high-current capable (20 mA)

PWMPRR

PTP[0]/ I/O General-purpose; with interrupt and wakeup

--



KWP[0]/ EVDD1

Switchable external power supply output with over-current interrupt; high-current capable (20

mA)

1. Signals in parentheses denote alternative module routing pins.
2. The interrupt is enabled by clearing the X mask bit in the CPU CCR. The pin is forced to input upon first clearing of the X bit and is held in this state until reset. A stop or wait recovery with the X bit set (refer to S12ZCPU reference manual) is not available.

Table 2-8. Port L Pin Functions and Priorities

ZVMC256 ZVMC128\64 ZVML128/64/32
ZVML31 ZVM32/16

Port

Pin Name

L PL0 

Pin &

Function Priority

I/O

Description

Routing Pin Function Register Bit after Reset

PTIL[0]/ I General-purpose high-voltage input (HVI); with

--

KWL[0]

interrupt and wakeup; optional ADC link

GPI (HVI)

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2.3 Memory Map and Register Definition
This section provides a detailed description of all port integration module registers. Subsection 2.3.1 shows all registers and bits at their related addresses within the global SoC register map. A detailed description of every register bit is given in subsection 2.3.2 to 2.3.4.

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2.3.1 Register Map

Global Address

Register Name

0x0200

MODRR0

Bit 7
R0 W

6

5

4

3

0 SPI0SSRR SPI0RR SCI1RR

2

1

Bit 0

S0L0RR2-01

0x0201

R MODRR1
W

M0C0RR2-02

PWMPRR1-03 PWM54RR PWM32RR PWM10RR

0x0202

R MODRR2
W

T0C2RR1-04

T0C1RR4 T1IC0RR2

T0IC3RR1-0

T0IC1RR T0IC1RR04

0x0203­ 0x0207

Reserved

R W

0

0

0

0

0

0

0

0

R

0

0

0

0

0

0

0

0x0208

ECLKCTL

NECLK

W

R

0

0

0

0

0

0

0x0209

IRQCR

IRQE

IRQEN

W

R0

0

0

0

0

0

0

0x020A

PIMMISC

OCPE1

W

0x020B­ 0x020C

Reserved

R W

0

0

0

0

0

0

0

0

0x020D

Reserved

R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W

0x020E

Reserved

R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W

0x020F

Reserved

R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W

0x0210­ 0x025F

Reserved

R W

0

0

0

0

0

0

0

0

R0

0

0

0

0

0

0x0260

PTE

PTE1

PTE0

W

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Global Address

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

R0

0

0

0

0

0

0

0

0x0261

Reserved

W

R0

0

0

0

0

0

PTIE1

PTIE0

0x0262

PTIE

W

R0

0

0

0

0

0

0

0

0x0263

Reserved

W

R0

0

0

0

0

0

0x0264

DDRE

DDRE1 DDRE0

W

R0

0

0

0

0

0

0

0

0x0265

Reserved

W

R0

0

0

0

0

0

0x0266

PERE

PERE1 PERE0

W

R0

0

0

0

0

0

0

0

0x0267

Reserved

W

R0

0

0

0

0

0

0x0268

PPSE

PPSE1 PPSE0

W

0x0269­ 0x027F

Reserved

R W

0

0

0

0

0

0

0

0

0x0280

PTADH

R PTADH72 PTADH62 PTADH52 PTADH42 PTADH32 PTADH22 PTADH12 PTADH0 W

0x0281 0x0282

PTADL PTIADH

R PTADL7
W

PTADL6

PTADL5

PTADL4

PTADL3

PTADL2

PTADL1

PTADL0

R PTIADH72 PTIADH62 PTIADH52 PTIADH42 PTIADH32 PTIADH22 PTIADH12 PTIADH0 W

0x0283

PTIADL

R PTIADL7 PTIADL6 PTIADL5 PTIADL4 PTIADL3 PTIADL2 PTIADL1 PTIADL0 W

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Global Address

Register Name

0x0284

DDRADH

Bit 7

6

5

4

3

2

1

Bit 0

RDDRADH72DDRADH62DDRADH52DDRADH42DDRADH32DDRADH22 DDRADL12 DDRADH0 W

0x0285

DDRADL

R DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0
W

0x0286

PERADH

R PERADH72 PERADH62 PERADH52 PERADH42 PERADH32 PERADH22 PERADH12 PERADH0 W

0x0287

PERADL

R PERADL7 PERADL6 PERADL5 PERADL4 PERADL3 PERADL2 PERADL1 PERADL0
W

0x0288

PPSADH

R PPSADH72 PPSADH62 PPSADH52 PPSADH42 PPSADH32 PPSADH22 PPSADH12 PPSADH0 W

0x0289

PPSADL

R PPSADL7 PPSADL6 PPSADL5 PPSADL4 PPSADL3 PPSADL2 PPSADL1 PPSADL0
W

0x028A­ 0x028B

Reserved

R W

0

0

0

0

0

0

0

0

0x028C

PIEADH

R PIEADH72 PIEADH62 PIEADH52 PIEADH42 PIEADH32 PIEADH22 PIEADH12 PIEADH0 W

0x028D

PIEADL

R PIEADL7 PIEADL6 PIEADL5 PIEADL4 PIEADL3 PIEADL2 PIEADL1 PIEADL0
W

0x028E

PIFADH

R PIFADH72 PIFADH62 PIFADH52 PIFADH42 PIFADH32 PIFADH22 PIFADH12 PIFADH0 W

0x028F

PIFADL

R PIFADL7 PIFADL6 PIFADL5 PIFADL4 PIFADL3 PIFADL2 PIFADL1 PIFADL0
W

0x0290­ 0x0297

Reserved

R W

0

0

0

0

0

0

0

0

0x0298

DIENADH

R DIENADH72 DIENADH62 DIENADH52 DIENADH42 DIENADH32 DIENADH22 DIENADH12 DIENADH0 W

0x0299

DIENADL

R DIENADL7 DIENADL6 DIENADL5 DIENADL4 DIENADL3 DIENADL2 DIENADL1 DIENADL0
W

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Global Address

Register Name

Bit 7

0x029A­ 0x02BF

Reserved

R W

0

0x02C0

R0 PTT
W

0x02C1

PTIT

R0 W

0x02C2

DDRT

R0 W

0x02C3

PERT

R0 W

0x02C4

PPST

R0 W

0x02C5­ 0x02CF

Reserved

R W

0

0x02D0

R0 PTS
W

0x02D1

PTIS

R0 W

0x02D2

DDRS

R0 W

0x02D3

PERS

R0 W

0x02D4

PPSS

R0 W

R0

0x02D5

Reserved

W

Chapter 2 Port Integration Module (S12ZVMPIMV3)

6

5

4

3

2

1

Bit 0

0

0

0

0

0

0

0

0

0

0

PTT3

PTT2

PTT1

PTT0

0

0

0

PTIT3

PTIT2

PTIT1

PTIT0

0

0

0

DDRT3 DDRT2 DDRT1 DDRT0

0

0

0

PERT3 PERT2 PERT1 PERT0

0

0

0

PPST3 PPST2 PPST1 PPST0

0

0

0

0

0

0

0

0

PTS55

PTS45

PTS3

PTS2

PTS1

PTS0

0

PTIS55 PTIS45

PTIS3

PTIS2

PTIS1

PTIS0

0 DDRS55 DDRS45 DDRS3 DDRS2 DDRS1 DDRS0

0 PERS55 PERS45 PERS3 PERS2 PERS1 PERS0

0 PPSS55 PPSS45 PPSS3 PPSS2 PPSS1 PPSS0

0

0

0

0

0

0

0

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Global Address

Register Name

Bit 7

6

R0

0

0x02D6

PIES

W

R0

0

0x02D7

PIFS

W

0x02D8­ 0x02DE

Reserved

R W

0

0

R0

0

0x02DF

WOMS

W

0x02E0­ 0x02EF

Reserved

R W

0

0

R0

0

0x02F0

PTP

W

R0

0

0x02F1

PTIP

W

R0

0

0x02F2

DDRP

W

R0

0

0x02F3

PERP

W

R0

0

0x02F4

PPSP

W

R0

0

0x02F5

Reserved

W

R

0

0x02F6

PIEP

OCIE1

W

R

0

0x02F7

PIFP

OCIF1

W

5

4

3

2

1

Bit 0

PIES55 PIES45 PIES3

PIES2

PIES1

PIES0

PIFS55 PIFS45

PIFS3

PIFS2

PIFS1

PIFS0

0

0

0

0

0

0

WOMS55 WOMS45 WOMS3 WOMS2 WOMS1 WOMS0

0

0

0

0

0

0

0

0

0

PTP25

PTP1

PTP0

0

0

0

PTIP25

PTIP1

PTIP0

0

0

0

DDRP25 DDRP1 DDRP0

0

0

0

PERP25 PERP1 PERP0

0

0

0

PPSP25 PPSP1 PPSP0

0

0

0

0

0

0

0

0

0

PIEP25 PIEP1

PIEP0

0

0

0

PIFP25

PIFP1

PIFP0

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Global Address

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

0x02F8­ 0x02FC

Reserved

R W

0

0

0

0

0

0

0

0

R0

0

0

0

0

0

0

0x02FD

RDRP

RDRP0

W

0x02FE­ 0x0330

Reserved

R W

0

0

0

0

0

0

0

0

R0

0

0

0

0

0

0

PTIL0

0x0331

PTIL2

W

R0

0

0

0

0

0

0

0

0x0332

Reserved

W

R0

0

0

0

0

0

0

0x0333

PTPSL2

PTPSL0

W

R0

0

0

0

0

0

0

0x0334

PPSL2

PPSL0

W

R0

0

0

0

0

0

0

0

0x0335

Reserved

W

R0

0

0

0

0

0

0

0x0336

PIEL2

PIEL0

W

R0

0

0

0

0

0

0

0x0337

PIFL2

PIFL0

W

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Global Address

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

0x0338­ 0x0339

Reserved

R W

0

0

0

0

0

0

0

0

R0

0

0

0

0

0

0

0x033A

PTABYPL2

PTABYPL0

W

R0

0

0

0

0

0

0

0x033B

PTADIRL2

PTADIRL0

W

R0

0

0

0

0

0

0

0x033C

DIENL2

DIENL0

W

R0

0

0

0

0

0

0

0x033D

PTAENL2

PTAENL0

W

R0

0

0

0

0

0

0

0x033E

PIRL2

PIRL0

W

R0

0

0

0

0

0

0

0x033F

PTTEL2

PTTEL0

W

1. Only available for ZVML128, ZVML64, ZVML32, and ZVML31 2. Only available for ZVMC256 3. PWMPRR[1] only writable for ZVMC256 4. Only available for ZVMC256, ZVML31, ZVM32, ZVM16 5. Not available for ZVMC256

2.3.2 PIM Registers 0x0200-0x020F
This section details the specific purposes of register implemented in address range 0x0200-0x020F. These registers serve for specific PIM related functions not part of the generic port registers.
· If not stated differently, writing to reserved bits has no effect and read returns zero. · All register read accesses are synchronous to internal clocks. · Register bits can be written at any time if not stated differently.

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Chapter 2 Port Integration Module (S12ZVMPIMV3)
Module Routing Register 0 (MODRR0)

Address 0x0200

Access: User read/write1

7

R

0

W

6

5

4

3

0

SPI0SSRR SPI0RR

SCI1RR

2

1

0

S0L0RR2-02

--

--

SPI0 SS0

SPI0

SCI1

SCI0-LINPHY0/HVPHY0 (see Figure 2-2)

Reset

0

0

0

0

0

0

0

0

Figure 2-1. Module Routing Register 0 (MODRR0) 1. Read: Anytime
Write: Once in normal, anytime in special mode
2. Only available for ZVML128, ZVML64, ZVML32, and ZVML31

Table 2-9. MODRR0 Routing Register Field Descriptions

Field

Description

5

Module Routing Register -- SPI0 SS0 routing

SPI0SSRR Note: This bit takes precedence over SPI0RR.

1 SS0 on PAD6 0 SS0 based on SPI0RR

4 SPI0RR

Module Routing Register -- SPI0 routing
1 MISO0 on PT0; MOSI0 on PT1; SCK0 on PT2; SS0 on PT3 or on pin selected by SPI0SSRR 0 MISO0 on PS2; MOSI0 on PS3; SCK0 on PS4 (PS1 for S12ZVMC256); SS0 on PS5 (PS0 for S12ZVMC256)
or on pin selected by SPI0SSRR

3 SCI1RR

Module Routing Register -- SCI1 routing
1 TXD1 on PS3; RXD1 on PS2 0 TXD1 on PS1; RXD1 on PS0

2-0 S0L0RR2-0

Module Routing Register -- SCI0-LINPHY0/HVPHY0 routing
Selection of SCI0-LINPHY0/HVPHY0 interface routing options to support probing and conformance testing. Refer to Figure 2-2 for an illustration and Table 2-10 for preferred settings. SCI0 must be enabled for TXD0 routing to take effect on pins. LINPHY0/HVPHY0 must be enabled for LPRXD0 and LPDC0 routings to take effect on pins.

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S0L0RR0 S0L0RR1

S0L0RR2 0 1

SCI0

1

TXD0

0

0

1

LINPHY0/ HVPHY0 LPTXD0
LPDR1

0 RXD0
1

LPRXD0

0 T0IC3RR1-0

01

1

10 RXD1

TIM0 input capture channel 3

11 ACLK 00 PT3

Figure 2-2. SCI0-to-LINPHY0 Routing Options Illustration

PT1 / TXD0 / LPDC0 PS1 / LPTXD0
LIN
PS0 / LPRXD0 PT0 / RXD0

S0L0RR[2:0] 000
001

Table 2-10. Preferred Interface Configurations

Signal Routing

Description Default setting: SCI0 connects to LINPHY0/HVPHY0, interface internal only

Direct control setting:
LP0DR[LPDR1] register bit controls LPTXD0, interface internal only

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110

Signal Routing

Chapter 2 Port Integration Module (S12ZVMPIMV3)

Probe setting:

Description

SCI0 connects to LINPHY0/HVPHY0, interface accessible on 2 external pins

Conformance test setting: Interface opened and all 4 signals routed externally

NOTE
For standalone usage of SCI0 on external pins set [S0L0RR2:S0L0RR0]=0b110 and disable the LINPHY0/HVPHY0 (LPCR[LPE]=0). This releases PS0 and PS1 to other associated functions and maintains TXD0 and RXD0 signals on PT1 and PT0, respectively, if no other function with higher priority takes precedence.

2.3.2.2 Module Routing Register 1 (MODRR1)

Address 0x0201

Access: User read/write1

7

6

5

R

M0C0RR2-02

W

4

3

PWMPRR1-03

2
PWM54RR

MSCAN0-CANPHY0 interface

PWM probe

PWM1_4 PWM1_5 GDU/pins

Reset

0

0

0

0

0

0

Figure 2-3. Module Routing Register 1 (MODRR1) 1. Read: Anytime
Write: Once in normal, anytime in special mode
2. Only available for ZVMC256
3. PWMPRR[1] only writable for ZVMC256

1
PWM32RR
PWM1_2 PWM1_3 GDU/pins
0

0
PWM10RR
PWM1_0 PWM1_1 GDU/pins
0

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Table 2-11. MODRR1 Routing Register Field Descriptions

Field

Description

7-5 Module Routing Register -- MSCAN0-CANPHY0 routing

M0C0RR2- Selection of MSCAN0-CANPHY0 interface routing options to support probing and conformance testing. Refer to

0

Figure 2-4 for an illustration and Table 2-12 for preferred settings. MSCAN0 must be enabled for TXCAN0 routing

to take effect on pin. CANPHY0 must be enabled for CPRXD0 and CP0DR[CPDR1] routings to take effect on pins.

4-3 PWMPRR
1-0

Module Routing Register -- PMF probe
Internal PMF outputs can be probed on related external pins. Probing can be enabled independent of the PWM54RR, PWM32RR, and PWM10RR settings.

11 PMF channels 1, 3, 5 connected to related PWM1_x pins (only available for ZVMC256) 10 PMF channels 0, 2, 4 connected to related PWM1_x pins (only available for ZVMC256) 01 All PMF channels connected to related PWM1_x pins 00 No PMF channels connected to related PWM1_x pins

2

Module Routing Register -- PWM1_4 and PWM1_5 routing

PWM54RR

The PWM channel pair can be configured for internal use with the GDU or with its related external pins only. If set

the signal routing to the pins is established and the related GDU inputs are forced low.

1 PWM1_4 to PT1; PWM1_5 to PT2 (PP0 for S12ZVMC256) 0 PWM1_4 to GDU; PWM1_5 to GDU

1

Module Routing Register -- PWM1_2 and PWM1_3 routing

PWM32RR

The PWM channel pair can be configured for internal use with the GDU or with its related external pins only. If set

the signal routing to the pins is established and the related GDU inputs are forced low.

1 PWM1_2 to PP2 (PT3 for S12ZVMC256); PWM1_3 to PT0 0 PWM1_2 to GDU; PWM1_3 to GDU

0

Module Routing Register -- PWM1_0 and PWM1_1 routing

PWM10RR

The PWM channel pair can be configured for internal use with the GDU or with its related external pins only. If set

the signal routing to the pins is established and the related GDU inputs are forced low.

1 PWM1_0 to PP0 (PT2 for S12ZVMC256); PWM1_1 to PP1 0 PWM1_0 to GDU; PWM1_1 to GDU

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M0C0RR0 M0C0RR1

TXCAN

0

1

MSCAN0

RXCAN

1 0
0 1

M0C0RR2 0 1
CPTXD CPDR1
CANPHY0
CPRXD
0 1

TXCAN0/CPDR1 CPTXD0
CANH SPLIT CANL
CPRXD0 RXCAN0

Figure 2-4. CAN Routing Options Illustration .
Table 2-12. Preferred Interface Configurations

M0C0RR[2:0]

Description

000

Default setting:

MSCAN connects to CANPHY, interface internal only

001

Direct control setting:

CP0DR[CPDR1] connects to CPTXD, interface internal only

100

Probe setting:

MSCAN connects to CANPHY, interface visible on 2 external pins

110

Conformance test setting:

Interface opened and all 4 signals routed externally

NOTE
For standalone usage of MSCAN0 on external pins set M0C0RR[2:0]=0b110 and disable CANPHY0 (CPCR[CPE]=0). This releases the CANPHY0 associated pins to other shared functions.

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2.3.2.3 Module Routing Register 2 (MODRR2)
Address 0x0202

Access: User read/write1

7

6

R T0C2RR1-02
W

5
T0C1RR2

4
T1IC0RR3

3

2

T0IC3RR1-0

IOC0_2

IOC0_1

IC1_0

TIM0 IC3

Reset

0

0

0

0

0

0

Figure 2-5. Module Routing Register 2 (MODRR2) 1. Read: Anytime
Write: Once in normal, anytime in special mode
2. Only available for ZVMC256, ZVML31, ZVM32, and ZVM16
3. Only available for ZVMC256

1
T0IC1RR

0
T0IC1RR02

TIM0 IC1 0

TIM0 IC1 0

Table 2-13. MODRR2 Routing Register Field Descriptions

Field

Description

7-6 T0C2RR1-0

Module Routing Register -- TIM0 IOC0_2 routing (ZVMC256, ZVML31, ZVM32, and ZVM16 only)
11 reserved 101 TIM0 IC0_2 is routed to the HVI, OC0_2 is disconnected from GPIO 01 TIM0 IOC0_2 is routed to PS1 00 TIM0 IOC0_2 is routed to PT2

5 T0C1RR

Module Routing Register -- TIM0 IOC0_1 routing (ZVMC256, ZVML31, ZVM32, and ZVM16 only)
1 TIM0 IOC0_1 is routed to PS0 0 TIM0 IOC0_1 is routed to PT1

4 T1IC0RR

Module Routing Register -- TIM1 IOC1_0 routing (ZVMC256 only) 1 TIM1 IOC1_0 is routed to the GDU delay measurement feature (tdelon) 0 TIM1 IOC1_0 is routed to PS2

3-2

Module Routing Register -- TIM0 IC3 routing

T0IC3RR1-0

One out of four different sources can be selected as input to timer channel 3.

11 TIM0 input capture channel 3 is connected to ACLK 10 TIM0 input capture channel 3 is connected to RXD1 01 TIM0 input capture channel 3 is connected to RXD0 00 TIM0 input capture channel 3 is connected to PT3

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Table 2-13. MODRR2 Routing Register Field Descriptions

Field
1 T0IC1RR

Description
Module Routing Register -- TIM0 IC1 routing
Timer input capture channel 1 can be used to determine the asynchronous commutation event in BLDC motor applications with Hall sensors. An integrated XOR gate supports direct connection of the three sensor inputs to the device. Note: This bit takes precedence over T0C1RR.

1 TIM0 input capture channel 1 is connected to logically XORed input signals of pins PT3-1 0 TIM0 input capture channel 1 is connected to PT1 or to pin selected by T0C1RR0 (if available)

0 T0IC1RR0

Module Routing Register -- TIM0 IC1 routing option 0 (ZVMC256, ZVML31, ZVM32, and ZVM16 only)
Timer input capture channel 1 can be used to determine the asynchronous commutation event in BLDC motor applications with Hall sensors. An integrated XOR gate supports direct connection of the three sensor inputs to the device. Note: This bit takes precedence over T0C1RR and T0IC1RR.

1 TIM0 input capture channel 1 is connected to logically XORed input signals of pins PT0, PS0 and PS1 0 TIM0 input capture channel 1 is connected to pin selected by T0IC1RR
1. Only available for ZVMC256, Reserved forZVML31, ZVM32, and ZVM16

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2.3.2.4 ECLK Control Register (ECLKCTL)

Address 0x0208

R W Reset:

7
NECLK 1

1. Read: Anytime Write: Anytime

6

5

4

3

2

0

0

0

0

0

0

0

0

0

0

Figure 2-6. ECLK Control Register (ECLKCTL)

Access: User read/write1

1

0

0

0

0

0

Table 2-14. ECLKCTL Register Field Descriptions

Field

Description

7 NECLK

No ECLK -- Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the internal bus clock. 1 ECLK disabled 0 ECLK enabled

2.3.2.5 IRQ Control Register (IRQCR)

Address 0x0209

7

6

5

4

3

2

R

0

0

0

0

IRQE

IRQEN

W

Reset

0

0

0

0

0

0

1. Read: Anytime

Figure 2-7. IRQ Control Register (IRQCR)

Write:

IRQE: Once in normal mode, anytime in special mode

IRQEN: Anytime

Access: User read/write1

1

0

0

0

0

0

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Table 2-15. IRQCR Register Field Descriptions

Field 7
IRQE
6 IRQEN

IRQ select edge sensitive only --

Description

1 IRQ pin configured to respond only to falling edges. Falling edges on the IRQ pin are detected anytime when IRQE=1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0 IRQ configured for low level recognition
IRQ enable --

1 IRQ pin is connected to interrupt logic 0 IRQ pin is disconnected from interrupt logic

2.3.2.6 PIM Miscellaneous Register (PIMMISC)

Address 0x020A

7

R

0

W

Reset

0

1. Read: Anytime Write:Anytime

6

5

4

3

2

0

0

0

0

0

0

0

0

0

0

Figure 2-8. PIM Miscellaneous Register (PIMMISC)

Access: User read/write1

1

0

0 OCPE1

0

0

Table 2-16. PIM Miscellaneous Register Field Descriptions

Field

Description

1

Over-Current Protection Enable -- Activate over-current detector on PP0

OCPE1 Refer to Section 2.5.3, "Over-Current Protection on EVDD1"

1 PP0 over-current detector enabled 0 PP0 over-current detector disabled

2.3.2.7 Reserved Register

Address 0x020D

R W Reset

7
Reserved x

6
Reserved x

5
Reserved

4
Reserved

3
Reserved

x

x

x

Figure 2-9. Reserved Register

2
Reserved x

Access: User read/write1

1

0

Reserved Reserved

x

x

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1. Read: Anytime Write: Only in special mode.
This reserved register is designed for factory test purposes only and is not intended for general user access. Writing to this register when in special modes can alter the modules functionality.

2.3.2.8 Reserved Register

Address 0x020E

:
R W Reset

7
Reserved x

6
Reserved x

1. Read: Anytime Write: Only in special mode

5
Reserved

4
Reserved

3
Reserved

2
Reserved

x

x

x

x

Figure 2-10. Reserved Register

Access: User read/write1

1

0

Reserved Reserved

x

x

This reserved register is designed for factory test purposes only and is not intended for general user access. Writing to this register when in special modes can alter the modules functionality.

2.3.2.9 Reserved Register

Address 0x020F

R W Reset

7
Reserved x

6
Reserved x

1. Read: Anytime Write: Only in special mode

5
Reserved

4
Reserved

3
Reserved

2
Reserved

x

x

x

x

Figure 2-11. Reserved Register

Access: User read/write1

1

0

Reserved Reserved

x

x

NOTE
This reserved register is designed for factory test purposes only and is not intended for general user access. Writing to this register when in special modes can alter the modules functionality.

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2.3.3 PIM Generic Registers
This section describes the details of all configuration registers. · Writing to reserved bits has no effect and read returns zero. · All register read accesses are synchronous to internal clocks. · All registers can be written at any time, however a specific configuration might not become active. E.g. a pullup device does not become active while the port is used as a push-pull output. · General-purpose data output availability depends on prioritization; input data registers always reflect the pin status independent of the use. · Pull-device availability, pull-device polarity, wired-or mode, key-wake up functionality are independent of the prioritization unless noted differently. · For availability of individual bits refer to Section 2.3.1, "Register Map" and Table 2-39.

2.3.3.1 Port Data Register

Address 0x0260 PTE 0x0280 PTADH 0x0281 PTADL 0x02C0 PTT 0x02D0 PTS 0x02F0 PTP

7
R PTx7
W

6
PTx6

5
PTx5

4
PTx4

3
PTx3

Reset

0

0

0

0

0

Figure 2-12. Port Data Register 1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime

2
PTx2 0

Access: User read/write1

1
PTx1 0

0
PTx0 0

This is a generic description of the standard port data registers. Refer to Table 2-39 to determine the implemented bits in the respective register. Unimplemented bits read zero.
Table 2-17. Port Data Register Field Descriptions

Field

Description

7-0 PTx7-0

Port -- General purpose input/output data
This register holds the value driven out to the pin if the pin is used as a general purpose output. When not used with the alternative function (refer to Table 2-7), these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.

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2.3.3.2 Port Input Register

Address 0x0262 PTIE 0x0282 PTIADH 0x0283 PTIADL 0x02C1 PTIT 0x02D1 PTIS 0x02F1 PTIP

Access: User read only1

R W Reset

7
PTIx7
-

1. Read: Anytime Write:Never

6
PTIx6
-

5
PTIx5

4
PTIx4

3
PTIx3

2
PTIx2

-

-

-

-

Figure 2-13. Port Input Register

1
PTIx1
-

0
PTIx0
-

This is a generic description of the standard port input registers. Refer to Table 2-39 to determine the implemented bits in the respective register. Unimplemented bits read zero.
Table 2-18. Port Input Register Field Descriptions

Field

Description

7-0 PTIx7-0

Port Input -- Data input
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins.

2.3.3.3 Data Direction Register

Address 0x0264 DDRE 0x0284 DDRADH 0x0285 DDRADL 0x02C2 DDRT 0x02D2 DDRS 0x02F2 DDRP

R W Reset

7
DDRx7 0

6
DDRx6 0

1. Read: Anytime Write: Anytime

5
DDRx5

4
DDRx4

3
DDRx3

2
DDRx2

0

0

0

0

Figure 2-14. Data Direction Register

Access: User read/write1

1
DDRx1 0

0
DDRx0 0

This is a generic description of the standard data direction registers. Refer to Table 2-39 to determine the implemented bits in the respective register. Unimplemented bits read zero.

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Table 2-19. Data Direction Register Field Descriptions

Field

Description

7-0 DDRx7-0

Data Direction -- Select general-purpose data direction
This bit determines whether the pin is a general-purpose input or output. If a peripheral module controls the pin the content of the data direction register is ignored. Independent of the pin usage with a peripheral module this register determines the source of data when reading the associated data register address.

Due to internal synchronization circuits, it can take up to two bus clock cycles until the correct

value is read on port data and port input registers, when changing the data direction

register.

Eqn. 0-1

1 Associated pin is configured as output 0 Associated pin is configured as input

2.3.3.4 Pull Device Enable Register

Address 0x0266 PERE 0x0286 PERADH 0x0287 PERADL 0x02C3 PERT 0x02D3 PERS 0x02F3 PERP

Access: User read/write1

7
R PERx7
W

6
PERx6

5
PERx5

4
PERx4

3
PERx3

2
PERx2

Reset

Ports E:

0

0

0

0

0

0

Ports S:

0

0

12

12

1

1

Others:

0

0

0

0

0

0

1. Read: Anytime Write: Anytime

Figure 2-15. Pull Device Enable Register

2. Unimplemented (reads zero) for S12ZVMC256

1
PERx1
1 1 0

0
PERx0
1 1 0

This is a generic description of the standard pull device enable registers. Refer to Table 2-39 to determine the implemented bits in the respective register. Unimplemented bits read zero.

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Table 2-20. Pull Device Enable Register Field Descriptions

Field

Description

7-0 PERx7-0

Pull Enable -- Activate pull device on input pin
This bit controls whether a pull device on the associated port input or open-drain output pin is active. If a pin is used as push-pull output this bit has no effect. The polarity is selected by the related polarity select register bit. On opendrain output pins only a pullup device can be enabled.

1 Pull device enabled 0 Pull device disabled

2.3.3.5 Polarity Select Register

Address 0x0268 PPSE 0x0288 PPSADH 0x0289 PPSADL 0x02C4 PPST 0x02D4 PPSS

R W Reset Ports E: Others:

7
PPSx7
0 0

6
PPSx6
0 0

1. Read: Anytime Write: Anytime

5
PPSx5

4
PPSx4

3
PPSx3

2
PPSx2

0

0

0

0

0

0

0

0

Figure 2-16. Polarity Select Register

Access: User read/write1

1
PPSx1

0
PPSx0

1

1

0

0

This is a generic description of the standard polarity select registers. Refer to Table 2-39 to determine the implemented bits in the respective register. Unimplemented bits read zero.
Table 2-21. Polarity Select Register Field Descriptions

Field

Description

7-0 PPSx7-0

Pull Polarity Select -- Configure pull device and pin interrupt edge polarity on input pin
This bit selects a pullup or a pulldown device if enabled on the associated port input pin. If a port has interrupt functionality this bit also selects the polarity of the active edge. If MSCAN is active a pullup device can be activated on the RXCAN input; attempting to select a pulldown disables the pull-device.

1 Pulldown device selected; rising edge selected 0 Pullup device selected; falling edge selected

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2.3.3.6 Port Interrupt Enable Register
Read: Anytime
Address 0x028C PIEADH 0x028D PIEADL 0x02D6 PIES 0x0336 PIEL

Access: User read/write1

R W Reset

7
PIEx7 0

1. Read: Anytime Write: Anytime

6
PIEx6

5
PIEx5

4
PIEx4

3
PIEx3

2
PIEx2

0

0

0

0

0

Figure 2-17. Port Interrupt Enable Register

1
PIEx1 0

0
PIEx0 0

This is a generic description of the standard port interrupt enable registers. Refer to Table 2-39 to determine the implemented bits in the respective register. Unimplemented bits read zero.
Table 2-22. Port Interrupt Enable Register Field Descriptions

Field

Description

7-0 PIEx7-0

Port Interrupt Enable -- Activate pin interrupt (KWU)
This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.

1 Interrupt is enabled 0 Interrupt is disabled (interrupt flag masked)

2.3.3.7 Port Interrupt Flag Register

Address 0x028E PIFADH 0x028F PIFADL 0x02D7 PIFS 0x0337 PIFL

Access: User read/write1

R W Reset

7
PIFx7 0

6
PIFx6 0

1. Read: Anytime Write: Anytime, write 1 to clear

5
PIFx5

4
PIFx4

3
PIFx3

2
PIFx2

0

0

0

0

Figure 2-18. Port Interrupt Flag Register

1
PIFx1 0

0
PIFx0 0

This is a generic description of the standard port interrupt flag registers. Refer to Table 2-39 to determine the implemented bits in the respective register. Unimplemented bits read zero.

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Table 2-23. Port Interrupt Flag Register Field Descriptions

Field

Description

7-0 PIFx7-0

Port Interrupt Flag -- Signal pin event (KWU)
This flag asserts after a valid active edge was detected on the related pin (see Section 2.4.5, "Pin interrupts and KeyWakeup (KWU)"). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated interrupt enable bit is set.

Writing a logic "1" to the corresponding bit field clears the flag.

1 Active edge on the associated bit has occurred 0 No active edge occurred

2.3.3.8 Digital Input Enable Register

Address 0x0298 DIENADH 0x0299 DIENADL

R W Reset

7
DIENx7 0

1. Read: Anytime Write: Anytime

6
DIENx6

5
DIENx5

4
DIENx4

3
DIENx3

2
DIENx2

0

0

0

0

0

Figure 2-19. Digital Input Enable Register

Access: User read/write1

1
DIENx1 0

0
DIENx0 0

This is a generic description of the standard digital input enable registers. Refer to Table 2-39 to determine the implemented bits in the respective register. Unimplemented bits read zero.
Table 2-24. Digital Input Enable Register Field Descriptions

Field

Description

7-0 DIENx7-0

Digital Input Enable -- Input buffer control
This bit controls the digital input function. If set to 1 the input buffers are enabled and the pin can be used with the digital function. If a peripheral module is enabled which uses the pin with a digital function the input buffer is activated and the register bit is ignored. If the pin is used with an analog function this bit shall be cleared to avoid shoot-through current.

1 Associated pin is configured as digital input 0 Associated pin digital input is disabled

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Address 0x02FD RDRP

Access: User read/write1

R W Reset

7
RDRx7 0

1. Read: Anytime Write: Anytime

6
RDRx6 0

5
RDRx5

4
RDRx4

3
RDRx3

2
RDRx2

0

0

0

0

Figure 2-20. Reduced Drive Register

1
RDRx1 0

0
RDRx0 0

This is a generic description of the standard reduced drive registers. Refer to Table 2-39 to determine the implemented bits in the respective register. Unimplemented bits read zero.
Table 2-25. Reduced Drive Register Field Descriptions

Field

Description

7-0 Reduced Drive Register -- Select reduced drive for output pin RDRx7-0 This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.

1 Reduced drive selected (approx. 1/10 of the full drive strength) 0 Full drive strength enabled

2.3.3.10 Wired-Or Mode Register

Address 0x02DF WOMS

Access: User read/write1

R W Reset

7
WOMx7 0

1. Read: Anytime Write: Anytime

6
WOMx6 0

5
WOMx5

4
WOMx4

3
WOMx3

2
WOMx2

0

0

0

0

Figure 2-21. Wired-Or Mode Register

1
WOMx1 0

0
WOMx0 0

This is a generic description of the standard wired-or registers. Refer to Table 2-39 to determine the implemented bits in the respective register. Unimplemented bits read zero.

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Table 2-26. Wired-Or Mode Register Field Descriptions

Field

Description

7-0 WOMx7-0

Wired-Or Mode -- Enable open-drain output
This bit configures the output buffer as wired-or. If enabled the output is driven active low only (open-drain) while the active high drive is turned off. This allows a multipoint connection of several serial modules. These bits have no influence on pins used as inputs.

1 Output buffers operate as open-drain outputs 0 Output buffers operate as push-pull outputs

2.3.3.11 PIM Reserved Register

Address (any reserved)

7

6

R

0

0

W

Reset

0

0

1. Read: Always reads 0x00 Write: Unimplemented

5

4

3

2

0

0

0

0

0

0

0

0

Figure 2-22. PIM Reserved Register

Access: User read1

1

0

0

0

0

0

2.3.4 PIM Generic Register Exceptions
This section lists registers with deviations from the generic description in one or more register bits.

2.3.4.1 Port P Polarity Select Register (PPSP)

Address 0x02F4 PPSP

7

R

0

W

Reset

0

1. Read: Anytime Write: Anytime

6

5

4

3

2

0

0

0

0

PPSP2

0

0

0

0

0

Figure 2-23. Port P Polarity Select Register

Access: User read/write1

1

0

PPS1P

PPSP0

0

0

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Table 2-27. Port P Polarity Select Register Field Descriptions

Field
2-1 PPSP
0 PPSP

Description See Section 2.3.3.5, "Polarity Select Register"
Pull Polarity Select -- Configure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. This bit also selects the polarity of the active interrupt edge.

This bit selects if a high or a low level on FAULT5 generates a fault event in PMF.

1 Pulldown device selected; rising edge selected; active-high level selected on FAULT5 input 0 Pullup device selected; falling edge selected; active-low level selected on FAULT5 input

2.3.4.2 Port P Interrupt Enable Register (PIEP)

Read: Anytime
Address 0x02F6 PIEP

R W Reset

7
OCIE1 0

1. Read: Anytime Write: Anytime

6

5

4

3

2

0

0

0

0

PIEP2

0

0

0

0

0

Figure 2-24. Port P Interrupt Enable Register

Access: User read/write1

1

0

PIEP1

PIEP0

0

0

Table 2-28. Port P Interrupt Enable Register Field Descriptions

Field
7 OCIE1

Over-Current Interrupt Enable register --

Description

This bit enables or disables the over-current interrupt on PP0.

1 PP0 over-current interrupt enabled 0 PP0 over-current interrupt disabled (interrupt flag masked)
2-0 See Section 2.3.3.6, "Port Interrupt Enable Register" PIEP2-0

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2.3.4.3 Port P Interrupt Flag Register (PIFP)

Address 0x02F7 PIFP

7

6

R

0

OCIF1

W

Reset

0

0

1. Read: Anytime Write: Anytime, write 1 to clear

5

4

3

2

0

0

0

PIFP2

0

0

0

0

Figure 2-25. Port P Interrupt Flag Register

Access: User read/write1

1

0

PIFP1

PIFP0

0

0

Table 2-29. Port P Interrupt Flag Register Field Descriptions

Field
7 OCIF1

Description Over-Current Interrupt Flag register -- This flag asserts if an over-current condition is detected on PP0 (Section 2.4.6, "Over-Current Interrupt").

Writing a logic "1" to the corresponding bit field clears the flag.

1 PP0 Over-current event occurred 0 No PP0 over-current event occurred
2-0 See Section 2.3.3.7, "Port Interrupt Flag Register" PIFP2-0

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2.3.4.4 Port L Input Register (PTIL)

Address 0x0331

7

6

R

0

0

W

Reset

0

0

1. Read: Anytime Write: No Write
2. Only available for S12ZVMC256

5

4

3

2

0

0

0

0

0

0

0

0

Figure 2-26. Port L Input Register (PTIL)

Access: User read only1

1

0

0

PTIL02

0

-

Table 2-30. PTIL - Register Field Descriptions

Field

Description

0 PTIL0

Port Input Data Register Port L -- A read returns the synchronized input state if the associated pin is used in digital mode, that is the related DIENL bit is set to 1 and the pin is not used in analog mode (PTAENL[PTAENL0]=0). See Section 2.3.4.11, "Port L Input Divider Ratio Selection Register (PIRL)". A one is read in any other case1.

1. Refer to PTTEL bit description in Section 2.3.4.11, "Port L Input Divider Ratio Selection Register (PIRL) for an override condition.

2.3.4.5 Port L Pull Select Register (PTPSL)

Address 0x0333

7

6

5

4

3

2

R

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

1. Read: Anytime Write: Anytime

Figure 2-27. Port L Pull Select Register (PTPSL)

2. Only available for S12ZVMC256

Access: User read/write1

1

0

0 PTPSL02

0

0

Table 2-31. PTPSL Register Field Descriptions

Field

Description

1-0 PTPSL0

Port L Pull Select -- This bit selects a pull device on the HVI pin in analog mode for open input detection. By default a pulldown device is active as part of the input voltage divider. If this bit set to 1 and PTTEL=1 and not in stop mode a pullup to a level close to VDDX takes effect and overrides the weak pulldown device. Refer to Section 2.5.2, "Open Input Detection on HVI"). 1 Pullup enabled 0 Pulldown enabled

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2.3.4.6 Port L Polarity Select Register (PPSL)

Address 0x0334 PPSL

7

6

5

4

3

2

R

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

1. Read: Anytime

Figure 2-28. Port L Polarity Select Register (PPSL)

Write: Anytime

2. Only available for S12ZVMC256

Table 2-32. PPSL Register Field Descriptions

Field
1-0 PPSL0

Description
Polarity Select -- This bit selects the polarity of the active interrupt edge on the associated HVI pin. 1 Rising edge selected 0 Falling edge selected

Access: User read/write1

1

0

0

PPSL02

0

0

2.3.4.7 Port L ADC Bypass Register (PTABYPL)

Address 0x033A

7

6

5

4

3

2

R

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

1. Read: Anytime Write: Anytime

Figure 2-29. Port L ADC Bypass Register (PTABYPL)

2. Only available for S12ZVMC256

Access: User read/write1

1

0

0

PTABYPL02

0

0

Table 2-33. PTABYPL Register Field Descriptions

Field

Description

1-0

Port L ADC Connection Bypass --

PTABYPL0 This bit bypasses and powers down the impedance converter stage in the signal path from the analog input pin to

the ADC channel input. This bit takes effect only if using direct input connection to the ADC channel (PTADIRL=1).

1 Impedance converter bypassed

0 Impedance converter used

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2.3.4.8 Port L ADC Direct Register (PTADIRL)

Address 0x033B

7

6

5

4

3

2

R

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

1. Read: Anytime

Figure 2-30. Port L ADC Direct Register (PTADIRL)

Write: Anytime

2. Only available for S12ZVMC256

Access: User read/write1

1

0

0

PTADIRL02

0

0

Table 2-34. PTADIRL Register Field Descriptions

Field

Description

1-0 PTADIRL0

Port L ADC Direct Connection -- This bit connects the analog input signal directly to the ADC channel bypassing the voltage divider. This bit takes effect only in analog mode (PTAENL=1). 1 Input pin directly connected to ADC channel 0 Input voltage divider active on analog input to ADC channel

2.3.4.9 Port L Digital Input Enable Register (DIENL)

Address 0x33C

7

6

5

4

3

2

R

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

1. Read: Anytime Write: Anytime

Figure 2-31. Port L Digital Input Enable Register (DIENL)

2. Only available for S12ZVMC256

Access: User read/write1

1

0

0 DIENL02

0

0

Table 2-35. DIENL Register Field Descriptions

Field

Description

0 DIENL0

Digital Input Enable Port L -- Input buffer control This bit controls the HVI digital input function. If set to 1 the input buffers are enabled and the pin can be used with the digital function. If the analog input function is enabled (PTAENL[PTAENL0]=1) the input buffer of the selected HVI pin is forced off1 in run mode and is released to be active in stop mode only if DIENL=1. 1 Associated pin digital input is enabled if not used as analog input in run mode1 0 Associated pin digital input is disabled1

1. Refer to PTTEL bit description in Section 2.3.4.11, "Port L Input Divider Ratio Selection Register (PIRL) for an override condition.

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2.3.4.10 Port L ADC Connection Enable Register (PTAENL)

Address 0x033D

Access: User read/write1

7

6

5

4

3

2

1

R

0

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

0

1. Read: Anytime

Figure 2-32. Port L ADC Connection Enable Register (PTAENL)

Write: Anytime

2. Only available for S12ZVMC256

0
PTAENL02 0

Table 2-36. PTAENL Register Field Descriptions

Field

Description

1-0 PTAENL0

Port L ADC Connection Enable -- This bit enables the analog signal link to an ADC channel. If set to 1 the analog input function takes precedence over the digital input in run mode by forcing off the input buffer if not overridden by PTTEL=1. Note: When enabling the resistor paths to ground by setting PTAENL=1, a delay of tUNC_HVI + two bus cycles must
be accounted for.
1 ADC connection enabled 0 ADC connection disabled

2.3.4.11 Port L Input Divider Ratio Selection Register (PIRL)

Address 0x033E

Access: User read/write1

7

6

5

4

3

2

1

R

0

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

0

1. Read: Anytime

Figure 2-33. Port L Input Divider Ratio Selection Register (PIRL)

Write: Anytime

2. Only available for S12ZVMC256

0
PIRL02 0

Field
1-0 PIRL0

Table 2-37. PIRL Register Field Descriptions
Description
Port L Input Divider Ratio Select -- This bit selects one of two voltage divider ratios for the associated HVI pin in analog mode. 1 RatioL_HVI selected 0 RatioH_HVI selected

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2.3.4.12 Port L Test Enable Register (PTTEL)Port L Input Divider Ratio Selection

Address 0x033F

Access: User read/write1

7

6

5

4

3

2

R

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

1. Read: Anytime

Figure 2-34. Port L Test Enable Register (PTTEL)

Write: Anytime

2. Only available for S12ZVMC256

1

0

0

PTTEL02

0

0

Table 2-38. PTTEL Register Field Descriptions

Field

Description

1-0 PTTEL0

Port L Test Enable -- This bit forces the input buffer of the HVI pin active while using the analog function to support open input detection in run mode. Refer to Section 2.5.2, "Open Input Detection on HVI"). In stop mode this bit has no effect. Note: In direct mode (PTADIRL=1) the digital input buffer is not enabled.
1 Input buffer enabled when used with analog function and not in direct mode (PTADIRL=0) 0 Input buffer disabled when used with analog function

2.4 Functional Description

2.4.1 General
Each pin except BKGD can act as general-purpose I/O. In addition each pin can act as an output or input of a peripheral module.

2.4.2 Registers
Table 2-39 lists the implemented configuration bits which are available on each port. These registers except the pin input registers can be written at any time, however a specific configuration might not become active. For example a pullup device does not become active while the port is used as a push-pull output.
Unimplemented bits read zero.

Table 2-39. Bit Indices of Implemented Register Bits per Port

Port Data Register

Port Input Register

Data Direction Register

Pull Device Enable Register

Polarity Select Register

Port Interrupt Enable Register

Port Interrupt
Flag Register

Digital Input Enable Register

Reduced Wired-Or

Drive

Mode

Register Register

Port

PT

PTI

DDR

PER

PPS

PIE

PIF

DIE

RDR

WOM

E

1-0

1-0

1-0

1-0

1-0

-

-

-

-

-

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Table 2-39. Bit Indices of Implemented Register Bits per Port

ADH ADL
T S P L4

Port Data Register
01 7-0 3-0 5-02 2-03
-

Port Input Register
01 7-0 3-0 5-02 2-03 0

Data Direction Register
01 7-0 3-0 5-02 2-03
-

Pull Device Enable Register
01
7-0
3-0 5-02 2-03
-

Polarity Select Register
01 7-0 3-0 5-02 2-03 0

Port Interrupt Enable Register
01
7-0
5-02 2-03
0

Port Interrupt
Flag Register
01
7-0
5-02 2-03
0

Digital Input Enable Register
01
7-0
-
-
-
0

Reduced Drive
Register
0 -

Wired-Or Mode
Register
5-02 -

1. 7-0 for ZVMC256 2. 3-0 for ZVMC256 3. 1-0 for ZVMC256 4. Only available for ZVMC256

Table 2-40 shows the effect of enabled peripheral features on I/O state and enabled pull devices.

Table 2-40. Effect of Enabled Features

Enabled Feature1

Related Signal(s)

Effect on I/O state

CPMU OSC

EXTAL, XTAL

CPMU takes control

TIM0 output compare IOC0_x TIM0 input capture IOC0_x

Forced output None2

TIM1 output compare IOC1_x TIM1 input capture IOC1_x

Forced output None4

SPI0

MISO0, MOSI0, SCK0, SS0 Controlled input/output

SCIx transmitter

TXDx

Forced output

SCIx receiver

RXDx

Forced input

MSCAN0

TXCAN0

Forced output

RXCAN0

Forced input

S12ZDBG

PDO, PDOCLK DBGEEV

Forced output None2

PTU

PTURE, PTUT1-0

Forced output

PWM channel

PWMx_x

Forced output

PMF fault input

FAULT5

Forced input

Effect on enabled pull device
Forced off Forced off None3 Forced off None5 Forced off if output Forced off None3 Forced off Pulldown forced off Forced off None3 Forced off Forced off None3

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Table 2-40. Effect of Enabled Features

Enabled Feature1

Related Signal(s)

Effect on I/O state

Effect on enabled pull device

ADCx

ANx_y

None2 6

None3

VRH, VRL

AMPx

AMPx, AMPPx, AMPMx

None2 6

None3

IRQ

IRQ

Forced input

None3

XIRQ

XIRQ

Forced input

None3

LINPHY0/ HVPHY0

LPTXD0 LPRXD0

Forced input Forced output

None3 Forced off

1. If applicable the appropriate routing configuration must be set for the signals to take effect on the pins.

2. DDR maintains control

3. PER/PPS maintain control

4. DDR maintains control

5. PER/PPS maintain control

6. To use the digital input function the related bit in Digital Input Enable Register (DIENADx) must be set to logic level "1".

2.4.3 Pin I/O Control
Figure 2-35 illustrates the data paths to and from an I/O pin. Input and output data can always be read via the input register (PTIx, Section 2.3.3.2, "Port Input Register") independent if the pin is used as generalpurpose I/O or with a shared peripheral function. If the pin is configured as input (DDRx=0, Section 2.3.3.3, "Data Direction Register"), the pin state can also be read through the data register (PTx, Section 2.3.3.1, "Port Data Register").
The general-purpose data direction configuration can be overruled by an enabled peripheral function shared on the same pin (Table 2-40). If more than one peripheral function is available and enabled at the same time, the highest ranked module according the predefined priority scheme in Table 2-7 will take precedence on the pin.

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Periph. Module

PTIx
0 1
PTx
DDRx
data out output enable port enable data in

synch.
0 1 0 1

PIN

Figure 2-35. Illustration of I/O pin functionality
2.4.4 Interrupts
This section describes the interrupts generated by the PIM and their individual sources. Vector addresses and interrupt priorities are defined at MCU level.

Table 2-41. PIM Interrupt Sources

Module Interrupt Sources XIRQ IRQ Port AD pin interrupt
Port S pin interrupt Port P pin interrupt Port L pin interrupt PP0 over-current interrupt

Local Enable
None IRQCR[IRQEN] PIEADH[PIEADH7-PIEADH0] PIEADL[PIEADL7-PIEADL0] PIES[PIES5-PIES0] PIEP[PIEP2-PIEP0] PIEL[PIEL0] PIEP[OCIE1]

2.4.4.1 XIRQ, IRQ Interrupts
The XIRQ pin allows requesting non-maskable interrupts after reset initialization. During reset, the X bit in the condition code register is set and any interrupts are masked until software enables them.
The IRQ pin allows requesting asynchronous interrupts. The interrupt input is disabled out of reset. To enable the interrupt the IRQCR[IRQEN] bit must be set and the I bit cleared in the condition code register. The interrupt can be configured for level-sensitive or falling-edge-sensitive triggering. If IRQCR[IRQEN] is cleared while an interrupt is pending, the request will deassert.

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Both interrupts are capable to wake-up the device from stop mode. Means for glitch filtering are not provided on these pins.
2.4.5 Pin interrupts and Key-Wakeup (KWU)
Ports AD, S, P and L offer pin interrupt and key-wakeup capability. The related interrupt enable (PIE) as well as the sensitivity to rising or falling edges (PPS) can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag (PIF) and its corresponding port interrupt enable (PIE) are both set. The pin interrupt feature is also capable to wake up the CPU when it is in stop or wait mode (key-wakeup).
A digital filter on each pin prevents short pulses from generating an interrupt. A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level. Else the sampling logic is restarted.
In run and wait mode the filters are continuously clocked by the bus clock. Pulses with a duration of tPULSE < nP_MASK/fbus are assuredly filtered out while pulses with a duration of tPULSE > nP_PASS/fbus guarantee a pin interrupt.
In stop mode the filter clock is generated by an RC-oscillator. The minimum pulse length varies over process conditions, temperature and voltage (Figure 2-36). Pulses with a duration of tPULSE < tP_MASK are assuredly filtered out while pulses with a duration of tPULSE > tP_PASS guarantee a wakeup event. Please refer to the appendix table "Pin Timing Characteristics" for pulse length limits.
To maximize current saving the RC oscillator is active only if the following condition is true on any individual pin:
individual pin:
Sample count <= 4 (at active or passive level) and interrupt enabled (PIE[x]=1) and interrupt flag not set (PIF[x]=0).

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Glitch, filtered out, no interrupt flag set

Valid pulse, interrupt flag set

uncertain

tP_MASK

tP_PASS

Figure 2-36. Interrupt Glitch Filter (here: active low level selected)

2.4.6 Over-Current Interrupt
In case of an over-current condition on PP0 (see Section 2.5.3, "Over-Current Protection on EVDD1") the over-current interrupt flag PIFP[OCIF1] asserts. This flag generates an interrupt if the enable bit PIEP[OCIE1] is set.
An asserted flag immediately forces the output pin low to protect the device. The flag must be cleared to re-enable the driver.

2.4.7 High-Voltage Input
A high-voltage input (HVI) on port L has the following features:
· Input voltage proof up to VHVI · Digital input function with pin interrupt and wakeup from stop capability · Analog input function with selectable divider ratio routable to ADC channel. Optional direct input
bypassing voltage divider and impedance converter. Capable to wakeup from stop (pin interrupts in run mode not available). Open input detection.
Figure 2-37 shows a block diagram of the HVI.
NOTE The term stop mode (STOP) is limited to voltage regulator operating in reduced performance mode (RPM). Refer to "Low Power Modes" section in device overview.

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VHVI

REXT_HVI 10K

PL (HVI)

Chapter 2 Port Integration Module (S12ZVMPIMV3)

40K 500K PTAENL & STOP & PTADIRL
110K

PTAENL & PTTEL & PTPSL & STOP

VDDX

(DIENL & (PTAENL | STOP)) | (PTAENL & PTADIRL & PTTEL & STOP)

Input Buffer PTIL

PTAENL & STOP & PTADIRL PTAENL & STOP & PTADIRL

Impedance Converter
ADC

PIRL

440K

PTAENL & PTADIRL & PTABYPL

Figure 2-37. HVI Block Diagram

Voltages up to VHVI can be applied to the HVI pin. Internal voltage dividers scale the input signals down to logic level. There are two modes, digital and analog, where these signals can be processed.
2.4.7.1 Digital Mode Operation In digital mode (PTAENL=0) the input buffer is enabled if DIENL=1. The synchronized pin input state determined at threshold level VTH_HVI can be read in register PTIL. Interrupt flag (PIFL) is set on input transitions if enabled (PIEL=1) and configured for the related edge polarity (PPSL). Wakeup from stop mode is supported.
2.4.7.2 Analog Mode Operation In analog mode (PTAENL=1) the input buffer is forced off and the voltage applied to a selectable HVI pin can be measured on its related internal ADC channel(refer to device overview section for channel assignment). One of two input divider ratios (RatioH_HVI, RatioL_HVI) can be chosen (PIRL) on the analog

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input or the voltage divider can be bypassed (PTADIRL=1). Additionally in latter case the impedance converter in the ADC signal path can be used or bypassed in direct input mode (PTABYPL). Out of reset the digital input buffer of the selected pin is disabled to avoid shoot-through current. Thus pin interrupts can only be generated if DIENL=1. In stop mode (RPM) the digital input buffer is enabled only if DIENL=1 to support wakeup functionality. Table 2-42 shows the HVI input configuration depending on register bits and operation mode.

Table 2-42. HVI Input Configurations

Mode

DIENL PTAENL Digital Input Analog Input

Resulting Function

Run

0

0

off

off

Input disabled (Reset)

0

1

off1

enabled Analog input, interrupt not supported

1

0

enabled

off

Digital input, interrupt supported

1

1

off1

enabled Analog input, interrupt not supported

Stop2

0

X

off

off

Input disabled, wakeup from stop not supported

1

X

1. Enabled if PTTEL=1 & PTADIRL=0)

enabled

off

Digital input, wakeup from stop supported

2. The term "stop mode" is limited to voltage regulator operating in reduced performance mode (RPM; refer to "Low Power Modes" section in device overview). In any other case the HVI input configuration defaults to "run mode". Therefore set PTAENL=0 before entering stop mode in order to generally support wakeup from stop.

NOTE
An external resistor REXT_HVI must always be connected to the highvoltage input to protect the device pins from fast transients and to achieve the specified pin input divider ratios when using the HVI in analog mode.

2.5 Initialization and Application Information

2.5.1 Port Data and Data Direction Register writes
It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs.

2.5.2 Open Input Detection on HVI
The connection of an external pull device on a high-voltage input can be validated by using the built-in pull functionality of the HVI. Depending on the application type an external pull-down circuit can be detected with the internal pull-up device whereas an external pull-up circuit can be detected with the internal pull-down device which is part of the input voltage divider.
Note that the following procedures make use of a function that overrides the automatic disable mechanism of the digital input buffer when using the HVI in analog mode. Make sure to switch off the override function when using the HVI in analog mode after the check has been completed.

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External pulldown device (Figure 2-38): 1. Enable analog function on HVI in non-direct mode (PTAENL[PTAENL0]=1, PTAENL[PTADIRL0]=0) 2. Select internal pullup device on HVI (PTPSL[PTPSL0]=1) 3. Enable function to force input buffer active on HVI in analog mode (PTTEL[PTTEL0]=1) 4. Verify PTIL=0 for a connected external pulldown device; read PTIL=1 for an open input

110K / 550K PIRL=0 / PIRL=1
HV Supply

VDDX

500K 40K

min. 1/10 * VDDX

Digital in

HVI 10K

Figure 2-38. Digital Input Read with Pullup Enabled
External pullup device (Figure 2-39): 1. Enable analog function on HVI in non-direct mode (PTAENL[PTAENL0]=1, PTADIRL[PTADIRL0]=0) 2. Select internal pulldown device on HVI (PTPSL[PTPSL0]=0) 3. Enable function to force input buffer active on HVI in analog mode (PTTEL[PTTEL0]=1) 4. Verify PTIL0=1 for a connected external pullup device; read PTIL0=0 for an open input

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10K HVI

40K
610K / 1050K PIRL=0 / PIRL=1

max. 10/11 * VHVI (PIRL=0) max. 21/22 * VHVI (PIRL=1)
Digital in

Figure 2-39. Digital Input Read with Pulldown Enabled

2.5.3 Over-Current Protection on EVDD1
Pin PP0 can be used as general-purpose I/O or due to its increased current capability in output mode as a switchable external power supply pin (EVDD1) for external devices like Hall sensors.
EVDD1 is supplied by the digital pad supply VDDX.
An over-current monitor is implemented to protect the controller from short circuits or excess currents on the output which can only arise if the pin is configured for full drive. Although the full drive current is available on the high and low side, the protection is only available on the high side with a current direction from EVDD1 to VSSX. There is also no protection to voltages higher than VDDX.
To enable the over-current monitor set the related OCPE1 bit in register PIMMISC.
In stop mode the over-current monitor is disabled for power saving. The increased current capability cannot be maintained to supply the external device. Therefore when using the pin as power supply the external load must be powered down prior to entering stop mode by driving the output low.
An over-current condition is detected if the output current level exceeds the threshold IOCD in run mode. The output driver is immediately forced low and the over-current interrupt flag OCIFx asserts. Refer to Section 2.4.6, "Over-Current Interrupt".

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Revision Number

Revision Date

V01.03 V01.04 V01.05

27 Jul 2012 27 Jul 2012 6 Aug 2012

V01.06 12 Feb 2013

Table 3-1. Revision History

Sections Affected

Description of Changes

Figure 3-8 3.3.2.2/3-162

Corrected Table 3-9
Added feature tags
Fixed wording
· Changed "KByte:to "KB" · Corrected the description of the MMCECH/L register

3.1 Introduction
The S12ZMMC module controls the access to all internal memories and peripherals for the S12ZCPU, and the S12ZBDC module. It also provides access to the RAM for ADCs and the PTU module. The S12ZMMC determines the address mapping of the on-chip resources, regulates access priorities and enforces memory protection. Figure 3-1 shows a block diagram of the S12ZMMC module.

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3.1.1 Glossary

Table 3-2. Glossary Of Terms

Term

Definition

MCU

Microcontroller Unit

CPU

S12Z Central Processing Unit

BDC

S12Z Background Debug Controller

ADC

Analog-to-Digital Converter

PTU

Programmable Trigger Unit

unmapped address range

Address space that is not assigned to a memory

reserved address range

Address space that is reserved for future use cases

illegal access Memory access, that is not supported or prohibited by the S12ZMMC, e.g. a data store to NVM

access violation Either an illegal access or an uncorrectable ECC error

byte

8-bit data

word

16-bit data

3.1.2 Overview
The S12ZMMC provides access to on-chip memories and peripherals for the S12ZCPU, the S12ZBDC, the PTU, and the ADC. It arbitrates memory accesses and determines all of the MCU memory maps. Furthermore, the S12ZMMC is responsible for selecting the MCUs functional mode.
3.1.3 Features
· S12ZMMC mode operation control · Memory mapping for S12ZCPU and S12ZBDC, PTU and ADCs
-- Maps peripherals and memories into a 16 MByte address space for the S12ZCPU, the S12ZBDC, the PTU, and the ADCs
-- Handles simultaneous accesses to different on-chip resources (NVM, RAM, and peripherals) · Access violation detection and logging
-- Triggers S12ZCPU machine exceptions upon detection of illegal memory accesses and uncorrectable ECC errors
-- Logs the state of the S12ZCPU and the cause of the access error

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3.1.4.1 Chip configuration modes
The S12ZMMC determines the chip configuration mode of the device. It captures the state of the MODC pin at reset and provides the ability to switch from special-single chip mode to normal single chip-mode.

3.1.4.2 Power modes The S12ZMMC module is only active in run and wait mode.There is no bus activity in stop mode.

3.1.5
e

Block Diagram

S12ZCPU

S12ZBDC

ADCs, PTU

Register Block

Memory Protection Crossbar Switch

Run Mode Controller

Program Flash

EEPROM

RAM

Peripherals

Figure 3-1. S12ZMMC Block Diagram

3.2 External Signal Description
The S12ZMMC uses two external pins to determine the devices operating mode: RESET and MODC (Table 3-3) See device overview for the mapping of these signals to device pins.

Table 3-3. External System Pins Associated With S12ZMMC

Pin Name RESET MODC

Description External reset signal. The RESET signal is active low. This input is captured in bit MODC of the MODE register when the external RESET pin deasserts.

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3.3 Memory Map and Register Definition

3.3.1 Memory Map
A summary of the registers associated with the MMC block is shown in Figure 3-2. Detailed descriptions of the registers and bits are given in the subsections that follow.

Address Name

Bit 7

6

5

4

3

2

1

Bit 0

0x0070 MODE R

0

0

0

0

0

0

0

W MODC

0x0071- Reserved R

0

0x007F

W

0

0

0

0

0

0

0

0x0080 MMCECH R W
0x0081 MMCECL R W

ITR[3:0] ACC[3:0]

TGT[3:0] ERR[3:0]

0x0082 MMCCCRH R CPUU

0

0

0

0

0

0

0

W

0x0083 MMCCCRL R

0

CPUX

0

CPUI

0

0

0

0

W

0x0084 Reserved R

0

W

0

0

0

0

0

0

0

0x0085 MMCPCH R W

CPUPC[23:16]

0x0086 MMCPCM R W

CPUPC[15:8]

0x0087 MMCPCL R W

CPUPC[7:0]

0x0088- Reserved R

0

0x00FF

W

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 3-2. S12ZMMC Register Summary

3.3.2 Register Descriptions
This section consists of the S12ZMMC control and status register descriptions in address order.

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3.3.2.1 Mode Register (MODE)

Address: 0x0070

7

6

5

4

3

2

1

0

R W

MODC

0

0

0

0

0

0

0

Reset MODC1

0

0

0

0

0

0

0

1. External signal (see Table 3-3). = Unimplemented or Reserved Figure 3-3. Mode Register (MODE)

Read: Anytime. Write: Only if a transition is allowed (see Figure 3-4). The MODE register determines the operating mode of the MCU.
CAUTION

Table 3-4. MODE Field Descriptions

Field
7 MODC

Description
Mode Select Bit -- This bit determines the current operating mode of the MCU. Its reset value is captured from
the MODC pin at the rising edge of the RESET pin. Figure 3-4 illustrates the only valid mode transition from
special single-chip mode to normal single chip mode.

Reset with MODC pin = 1

Reset with MODC pin = 0

Normal Single-Chip Mode (NS)

write access to MODE: 1  MODC bit

Special Single-Chip Mode (SS)

Figure 3-4. Mode Transition Diagram

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3.3.2.2 Error Code Register (MMCECH, MMCECL)

Address: 0x0080 (MMCECH)

7

6

5

4

3

2

1

0

R W

ITR[3:0]

TGT[3:0]

Reset

0

0

0

0

0

0

0

0

Address: 0x0081 (MMCECL)

7

6

5

4

3

2

1

0

R ACC[3:0]
W

ERR[3:0]

Reset

0

0

0

0

0

0

0

0

Figure 3-5. Error Code Register (MMCEC)

Read: Anytime Write: Write of 0xFFFF to MMCECH:MMCECL resets both registers to 0x0000
Table 3-5. MMCECH and MMCECL Field Descriptions

Field

Description

7-4 (MMCECH) ITR[3:0]
3-0 (MMCECH) TGT[3:0]

Initiator Field -- The ITR[3:0] bits capture the initiator which caused the access violation. The initiator is captured in form of a 4 bit value which is assigned as follows: 0: none (no error condition detected) 1: S12ZCPU 2: reserved 3: ADC0 4: ADC1 5: PTU 6-15: reserved
Target Field -- The TGT[3:0] bits capture the target of the faulty access. The target is captured in form of a 4 bit value which is assigned as follows: 0: none 1: register space 2: RAM 3: EEPROM 4: program flash 5: IFR 6-15: reserved

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Field 7-4 (MMCECL)
ACC[3:0]
3-0 (MMCECL) ERR[3:0]

Description
Access Type Field -- The ACC[3:0] bits capture the type of memory access, which caused the access violation. The access type is captured in form of a 4 bit value which is assigned as follows: 0: none (no error condition detected) 1: opcode fetch 2: vector fetch 3: data load 4: data store 5-15: reserved
Error Type Field -- The EC[3:0] bits capture the type of the access violation. The type is captured in form of a 4 bit value which is assigned as follows: 0: none (no error condition detected) 1: access to an illegal access 2: uncorrectable ECC error 3-15:reserved

The MMCEC register captures debug information about access violations. It is set to a non-zero value if a S12ZCPU access violation or an uncorrectable ECC error has occurred. At the same time this register is set to a non-zero value, access information is captured in the MMCPCn and MMCCCRn registers. The MMCECn, the MMCPCn and the MMCCCRn registers are not updated if the MMCECn registers contain a non-zero value. The MMCECn registers are cleared by writing the value 0xFFFF.

3.3.2.3 Captured S12ZCPU Condition Code Register (MMCCCRH, MMCCCRL)

Address: 0x0082 (MMCCCRH)

7

6

5

4

3

2

1

0

R CPUU

0

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

0

0

Address: 0x0083 (MMCCCRL)

7

6

5

4

3

2

1

0

R

0

CPUX

0

CPUI

0

0

0

0

W

Reset

0

0

0

0

0

0

0

0

Figure 3-6. Captured S12ZCPU Condition Code Register (MMCCCRH, MMCCCRL)
Read: Anytime Write: Never

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Table 3-6. MMCCCRH and MMCCCRL Field Descriptions

Field

Description

7 (MMCCCRH) CPUU

S12ZCPU User State Flag -- This bit shows the state of the user/supervisor mode bit in the S12ZCPU's CCR at the time the access violation has occurred. The S12ZCPU user state flag is read-only; it will be automatically updated when the next error condition is flagged through the MMCEC register. This bit is undefined if the error code registers (MMCECn) are cleared.

6 (MMCCCRL) CPUX

S12ZCPU X-Interrupt Mask-- This bit shows the state of the X-interrupt mask in the S12ZCPU's CCR at the time the access violation has occurred. The S12ZCPU X-interrupt mask is read-only; it will be automatically updated when the next error condition is flagged through the MMCEC register. This bit is undefined if the error code registers (MMCECn) are cleared.

4 (MMCCCRL) CPUI

S12ZCPU I-Interrupt Mask-- This bit shows the state of the I-interrupt mask in the CPU's CCR at the time the access violation has occurred. The S12ZCPU I-interrupt mask is read-only; it will be automatically updated when the next error condition is flagged through the MMCEC register. This bit is undefined if the error code registers (MMCECn) are cleared.

3.3.2.4 Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL)

Address: 0x0085 (MMCPCH)

7

6

5

4

3

2

1

0

R

CPUPC[23:16]

W

Reset

0

0

0

0

0

0

0

0

Address: 0x0086 (MMCPCM)

7

6

5

4

3

2

1

0

R

CPUPC[15:8]

W

Reset

0

0

0

0

0

0

0

0

Address: 0x0087 (MMCPCL)

7

6

5

4

3

2

1

0

R

CPUPC[7:0]

W

Reset

0

0

0

0

0

0

0

0

Figure 3-7. Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL)
Read: Anytime Write: Never

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Table 3-7. MMCPCH, MMCPCM, and MMCPCL Field Descriptions

Field

Description

7­0 (MMCPCH) S12ZCPU Program Counter Value-- The CPUPC[23:0] stores the CPU's program counter value at the time 7­0 (MMCPCM) the access violation occurred. CPUPC[23:0] always points to the instruction which triggered the violation. These 7­0 (MMCPCL) bits are undefined if the error code registers (MMCECn) are cleared. CPUPC[23:0]

3.4 Functional Description
This section provides a complete functional description of the S12ZMMC module.
3.4.1 Global Memory Map
The S12ZMMC maps all on-chip resources into an 16MB address space, the global memory map. The exact resource mapping is shown in Figure 3-8. The global address space is used by the S12ZCPU, ADCs, PTU, and the S12ZBDC module.

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Register Space
4 KB

RAM
max. 1 MByte - 4 KB
EEPROM
max. 1 MByte - 48 KB
Reserved
Reserved (read only)
NVM IFR

0x00_0000 0x00_1000
0x10_0000
512 Byte 0x1F_4000 6 KBKB 0x1F_8000 256 Byte 0x1F_C000
0x20_0000

Unmapped
6 MByte

0x80_0000

Program NVM
max. 8 MByte

Unmapped address range Low address aligned

High address aligned

Figure 3-8. Global Memory Map

0xFF_FFFF

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3.4.2 Illegal Accesses
The S12ZMMC module monitors all memory traffic for illegal accesses. See Table 3-9 for a complete list of all illegal accesses.
Table 3-9. Illegal memory accesses

S12ZCPU

S12ZBDC

ADCs and PTU

Register space

Read access ok Write access ok

Code execution illegal access

RAM

Read access ok

Write access ok

EEPROM

Code execution ok Read access ok(1)

Write access illegal access Code execution ok1

Reserved Space

Read access ok Write access only permitted in SS mode

Code execution illegal access

Reserved Read-only
Space
NVM IFR

Read access ok Write access illegal access Code execution illegal access Read access ok1

Write access illegal access

Code execution illegal access Program NVM Read access ok1

Write access illegal access Code execution ok1

Unmapped Space

Read access illegal access Write access illegal access

Code execution illegal access

ok ok
ok ok
ok1 illegal access
ok ok
ok illegal access
ok1 illegal access
ok1 illegal access
illegal access illegal access

illegal access illegal access
ok ok
ok1 illegal access
illegal access illegal access
illegal access illegal access
illegal access illegal access
ok1 illegal access
illegal access illegal access

1. Unsupported NVM accesses during NVM command execution ("collisions"), are treated as illegal accesses.

Illegal accesses are reported in several ways:
· All illegal accesses performed by the S12ZCPU trigger machine exceptions. · All illegal accesses performed through the S12ZBDC interface, are captured in the ILLACC bit of
the BDCCSRL register.

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· All illegal accesses performed by an ADC or PTU module trigger error interrupts. See ADC and PTU section for details.
NOTE Illegal accesses caused by S12ZCPU opcode prefetches will also trigger machine exceptions, even if those opcodes might not be executed in the program flow. To avoid these machine exceptions, S12ZCPU instructions must not be executed from the last (high addresses) 8 bytes of RAM, EEPROM, and Flash.
3.4.3 Uncorrectable ECC Faults
RAM and flash use error correction codes (ECC) to detect and correct memory corruption. Each uncorrectable memory corruption, which is detected during a S12ZCPU, ADC or PTU access triggers a machine exception. Uncorrectable memory corruptions which are detected during a S12ZBDC access, are captured in the RAMWF or the RDINV bit of the BDCCSRL register.

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Table 4-1. Revision History

Version Number
V00.01 V00.02 V00.03

Revision Date
17 Apr 2009 14 Jul 2009 05 Oct 2009

V00.04

04 Jun 2010

V00.05 V00.06

12 Jan 2011 22 Mar 2011

V00.07

15 Apr 2011

V00.08 02 May 2011

V00.09 V00.10 V00.11 V00.12

12 Aug 2011 21 Feb 2012 02 Jul 2012 22 May 2013

Effective Date all all all
all
all all
all
all
all all all all

Description of Changes
Initial version based on S12XINT V2.06
Reduce RESET vectors from three to one.
Removed dedicated ECC machine exception vector and marked vector-table entry "reserved for future use". Added a second illegal op-code vector (to distinguish between SPARE and TRAP).
Fixed remaining descriptions of RESET vectors. Split non-maskable hardware interrupts into XGATE software error and machine exception requests. Replaced mentions of CCR (old name from S12X) with CCW (new name).
Corrected wrong IRQ vector address in some descriptions.
Added vectors for RAM ECC and NVM ECC machine exceptions. And moved position to 1E0..1E8. Moved XGATE error interrupt to vector 1DC. Remaining vectors accordingly. Removed illegal address reset as a potential reset source.
Removed illegal address reset as a potential reset source from Exception vector table as well. Added the other possible reset sources to the table. Changed register addresses according to S12Z platform definition.
Reduced machine exception vectors to one. Removed XGATE error interrupt. Moved Spurious interrupt vector to 1DC. Moved vector base address to 010 to make room for NVM non-volatile registers.
Added: Machine exceptions can cause wake-up from STOP or WAIT
Corrected reset value for INT_CFADDR register
Removed references and functions related to XGATE
added footnote about availability of "Wake-up from STOP or WAIT by XIRQ with X bit set" feature

4.1 Introduction
The INT module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to the CPU. The INT module supports:
· I-bit and X-bit maskable interrupt requests · One non-maskable unimplemented page1 op-code trap

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· One non-maskable unimplemented page2 op-code trap · One non-maskable software interrupt (SWI) · One non-maskable system call interrupt (SYS) · One non-maskable machine exception vector request · One spurious interrupt vector request · One system reset vector request
Each of the I-bit maskable interrupt requests can be assigned to one of seven priority levels supporting a flexible priority scheme. The priority scheme can be used to implement nested interrupt capability where interrupts from a lower level are automatically blocked if a higher level interrupt is being processed.

4.1.1 Glossary

The following terms and abbreviations are used in the document.
Table 4-2. Terminology

Term CCW DMA INT IPL ISR MCU IRQ XIRQ

Meaning Condition Code Register (in the S12Z CPU) Direct Memory Access Interrupt Interrupt Processing Level Interrupt Service Routine Micro-Controller Unit refers to the interrupt request associated with the IRQ pin refers to the interrupt request associated with the XIRQ pin

4.1.2 Features
· Interrupt vector base register (IVBR)
· One system reset vector (at address 0xFFFFFC). · One non-maskable unimplemented page1 op-code trap (SPARE) vector (at address vector base1 +
0x0001F8). · One non-maskable unimplemented page2 op-code trap (TRAP) vector (at address vector base1 +
0x0001F4). · One non-maskable software interrupt request (SWI) vector (at address vector base1 + 0x0001F0). · One non-maskable system call interrupt request (SYS) vector (at address vector base1 +
0x00001EC). · One non-maskable machine exception vector request (at address vector base1 + 0x0001E8. · One spurious interrupt vector (at address vector base1 + 0x0001DC). · One X-bit maskable interrupt vector request associated with XIRQ (at address vector base1 +
0x0001D8).
1. The vector base is a 24-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as the upper 15 bits of the address) and 0x000 (used as the lower 9 bits of the address).

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· One I-bit maskable interrupt vector request associated with IRQ (at address vector base1 + 0x0001D4).
· up to 113 additional I-bit maskable interrupt vector requests (at addresses vector base1 + 0x000010 .. vector base + 0x0001D0).
· Each I-bit maskable interrupt request has a configurable priority level. · I-bit maskable interrupts can be nested, depending on their priority levels. · Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or
whenever XIRQ is asserted, even if X interrupt is masked.
4.1.3 Modes of Operation
· Run mode This is the basic mode of operation.
· Wait mode In wait mode, the INT module is capable of waking up the CPU if an eligible CPU exception occurs. Please refer to Section 4.5.3, "Wake Up from Stop or Wait Mode" for details.
· Stop Mode In stop mode, the INT module is capable of waking up the CPU if an eligible CPU exception occurs. Please refer to Section 4.5.3, "Wake Up from Stop or Wait Mode" for details.
4.1.4 Block Diagram
Figure 4-1 shows a block diagram of the INT module.

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Peripheral Interrupt Requests

Wake Up CPU

Priority Decoder To CPU

Non I Bit Maskable Channels

One Set Per Channel (Up to 117 Channels)

PRIOLVL2 PRIOLVL1 PRIOLVL0

PRIOLVLnPriority Level = configuration bits from the associated channel configuration register IVBR = Interrupt Vector Base IPL = Interrupt Processing Level

Interrupt Requests Priority Level Filter
Highest Pending IPL

Vector Address
IVBR New IPL Current IPL

Figure 4-1. INT Block Diagram
4.2 External Signal Description
The INT module has no external signals.
4.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the INT module.

4.3.1 Module Memory Map
Table 4-3 gives an overview over all INT module registers.

Address 0x000010­0x000011 0x000012­0x000016
0x000017
0x000018

Table 4-3. INT Memory Map
Use
Interrupt Vector Base Register (IVBR) RESERVED
Interrupt Request Configuration Address Register (INT_CFADDR)
Interrupt Request Configuration Data Register 0 (INT_CFDATA0)

Access R/W -- R/W
R/W

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0x000019 0x00001A 0x00001B 0x00001C 0x00001D 0x00001E 0x00001F

Table 4-3. INT Memory Map
Interrupt Request Configuration Data Register 1 (INT_CFDATA1)
Interrupt Request Configuration Data Register 2 (INT_CFDATA2
Interrupt Request Configuration Data Register 3 (INT_CFDATA3)
Interrupt Request Configuration Data Register 4 (INT_CFDATA4)
Interrupt Request Configuration Data Register 5 (INT_CFDATA5)
Interrupt Request Configuration Data Register 6 (INT_CFDATA6)
Interrupt Request Configuration Data Register 7 (INT_CFDATA7)

Chapter 4 Interrupt (S12ZINTV0)
R/W R/W R/W R/W R/W R/W R/W

4.3.2 Register Descriptions
This section describes in address order all the INT module registers and their individual bits.

Address

Register Name

0x000010

IVBR

R

W

0x000011

R

W

0x000017 INT_CFADDR R W

0x000018 INT_CFDATA0 R W

0x000019 INT_CFDATA1 R W

0x00001A INT_CFDATA2 R W

0x00001B INT_CFDATA3 R W

0x00001C INT_CFDATA4 R W

Bit 7
0 0 0 0 0 0

6

5

4

3

IVB_ADDR[15:8]

IVB_ADDR[7:1]

INT_CFADDR[6:3]

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

= Unimplemented or Reserved Figure 4-2. INT Register Summary

2

1

Bit 0

0

0

0

0

PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0]

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Address

Register Name

Bit 7

6

5

4

3

0x00001D INT_CFDATA5 R

0

0

0

0

0

W

0x00001E INT_CFDATA6 R

0

0

0

0

0

W

0x00001F INT_CFDATA7 R

0

0

0

0

0

W

= Unimplemented or Reserved

Figure 4-2. INT Register Summary

4.3.2.1 Interrupt Vector Base Register (IVBR)

2

1

Bit 0

PRIOLVL[2:0]

PRIOLVL[2:0]

PRIOLVL[2:0]

Address: 0x000010

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

0

IVB_ADDR[15:1]

W

Reset 1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

Figure 4-3. Interrupt Vector Base Register (IVBR)

Read: Anytime

Write: Anytime

Table 4-4. IVBR Field Descriptions

Field
15­1 IVB_ADDR
[15:1]

Description
Interrupt Vector Base Address Bits -- These bits represent the upper 15 bits of all vector addresses. Out of reset these bits are set to 0xFFFE (i.e., vectors are located at 0xFFFE00­0xFFFFFF). Note: A system reset will initialize the interrupt vector base register with "0xFFFE" before it is used to
determine the reset vector address. Therefore, changing the IVBR has no effect on the location of the reset vector (0xFFFFFC­0xFFFFFF).

4.3.2.2 Interrupt Request Configuration Address Register (INT_CFADDR)

Address: 0x000017

7

6

5

4

3

2

1

0

R

0

W

INT_CFADDR[6:3]

0

0

0

Reset

0

0

0

0

1

0

0

0

= Unimplemented or Reserved

Figure 4-4. Interrupt Configuration Address Register (INT_CFADDR)

Read: Anytime

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Write: Anytime

Table 4-5. INT_CFADDR Field Descriptions

Field

Description

6­3

Interrupt Request Configuration Data Register Select Bits -- These bits determine which of the 128

INT_CFADDR[6:3] configuration data registers are accessible in the 8 register window at INT_CFDATA0­7.

The hexadecimal value written to this register corresponds to the upper 4 bits of the vector number

(multiply with 4 to get the vector address offset).

If, for example, the value 0x70 is written to this register, the configuration data register block for the 8

interrupt vector requests starting with vector at address (vector base + (0x70*4 = 0x0001C0)) is selected

and can be accessed as INT_CFDATA0­7.

4.3.2.3 Interrupt Request Configuration Data Registers (INT_CFDATA0­7)
The eight register window visible at addresses INT_CFDATA0­7 contains the configuration data for the block of eight interrupt requests (out of 128) selected by the interrupt configuration address register (INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt configuration data register of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt configuration data register of the vector with the highest address, respectively.

Address: 0x000018

7

6

5

4

3

2

1

0

R

0

0

0

0

0

W

PRIOLVL[2:0]

Reset

0

0

0

0

0

0

0

1(1)

= Unimplemented or Reserved

Figure 4-5. Interrupt Request Configuration Data Register 0 (INT_CFDATA0) 1. Please refer to the notes following the PRIOLVL[2:0] description below.

Address: 0x000019

7

6

5

4

3

2

1

0

R

0

0

0

0

0

W

PRIOLVL[2:0]

Reset

0

0

0

0

0

0

0

1(1)

= Unimplemented or Reserved

Figure 4-6. Interrupt Request Configuration Data Register 1 (INT_CFDATA1) 1. Please refer to the notes following the PRIOLVL[2:0] description below.

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Address: 0x00001A

7

6

5

4

3

2

1

0

R

0

0

0

0

0

W

PRIOLVL[2:0]

Reset

0

0

0

0

0

0

0

1(1)

= Unimplemented or Reserved

Figure 4-7. Interrupt Request Configuration Data Register 2 (INT_CFDATA2) 1. Please refer to the notes following the PRIOLVL[2:0] description below.

Address: 0x00001B

7

6

5

4

3

2

1

0

R

0

0

0

0

0

W

PRIOLVL[2:0]

Reset

0

0

0

0

0

0

0

1(1)

= Unimplemented or Reserved

Figure 4-8. Interrupt Request Configuration Data Register 3 (INT_CFDATA3) 1. Please refer to the notes following the PRIOLVL[2:0] description below.

Address: 0x00001C

7

6

5

4

3

2

1

0

R

0

0

0

0

0

W

PRIOLVL[2:0]

Reset

0

0

0

0

0

0

0

1(1)

= Unimplemented or Reserved

Figure 4-9. Interrupt Request Configuration Data Register 4 (INT_CFDATA4) 1. Please refer to the notes following the PRIOLVL[2:0] description below.

Address: 0x00001D

7

6

5

4

3

2

1

0

R

0

0

0

0

0

W

PRIOLVL[2:0]

Reset

0

0

0

0

0

0

0

1(1)

= Unimplemented or Reserved

Figure 4-10. Interrupt Request Configuration Data Register 5 (INT_CFDATA5) 1. Please refer to the notes following the PRIOLVL[2:0] description below.

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Address: 0x00001E

7

6

5

4

3

2

1

0

R

0

0

0

0

0

W

PRIOLVL[2:0]

Reset

0

0

0

0

0

0

0

1(1)

= Unimplemented or Reserved

Figure 4-11. Interrupt Request Configuration Data Register 6 (INT_CFDATA6) 1. Please refer to the notes following the PRIOLVL[2:0] description below.

Address: 0x00001F

7

6

5

4

3

2

1

0

R

0

0

0

0

0

W

PRIOLVL[2:0]

Reset

0

0

0

0

0

0

0

1(1)

= Unimplemented or Reserved

Figure 4-12. Interrupt Request Configuration Data Register 7 (INT_CFDATA7) 1. Please refer to the notes following the PRIOLVL[2:0] description below.

Read: Anytime Write: Anytime

Table 4-6. INT_CFDATA0­7 Field Descriptions

Field

Description

2­0

Interrupt Request Priority Level Bits -- The PRIOLVL[2:0] bits configure the interrupt request priority level of

PRIOLVL[2:0] the associated interrupt request. Out of reset all interrupt requests are enabled at the lowest active level ("1").

Please also refer to Table 4-7 for available interrupt request priority levels.

Note: Write accesses to configuration data registers of unused interrupt channels are ignored and read

accesses return all 0s. For information about what interrupt channels are used in a specific MCU, please

refer to the Device Reference Manual for that MCU.

Note: When non I-bit maskable request vectors are selected, writes to the corresponding INT_CFDATA registers are ignored and read accesses return all 0s. The corresponding vectors do not have configuration data registers associated with them.

Note: Write accesses to the configuration register for the spurious interrupt vector request (vector base + 0x0001DC) are ignored and read accesses return 0x07 (request is handled by the CPU, PRIOLVL = 7).

Priority low

Table 4-7. Interrupt Priority Levels

PRIOLVL2
0 0 0 0

PRIOLVL1
0 0 1 1

PRIOLVL0
0 1 0 1

Meaning
Interrupt request is disabled Priority level 1 Priority level 2 Priority level 3

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Priority high

Table 4-7. Interrupt Priority Levels

PRIOLVL2
1 1 1 1

PRIOLVL1
0 0 1 1

PRIOLVL0
0 1 0 1

Meaning
Priority level 4 Priority level 5 Priority level 6 Priority level 7

4.4 Functional Description
The INT module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below.

4.4.1 S12Z Exception Requests
The CPU handles both reset requests and interrupt requests. The INT module contains registers to configure the priority level of each I-bit maskable interrupt request which can be used to implement an interrupt priority scheme. This also includes the possibility to nest interrupt requests. A priority decoder is used to evaluate the relative priority of pending interrupt requests.

4.4.2 Interrupt Prioritization
After system reset all I-bit maskable interrupt requests are configured to be enabled, are set up to be handled by the CPU and have a pre-configured priority level of 1. Exceptions to this rule are the nonmaskable interrupt requests and the spurious interrupt vector request at (vector base + 0x0001DC) which cannot be disabled, are always handled by the CPU and have a fixed priority levels. A priority level of 0 effectively disables the associated I-bit maskable interrupt request.
If more than one interrupt request is configured to the same interrupt priority level the interrupt request with the higher vector address wins the prioritization.
The following conditions must be met for an I-bit maskable interrupt request to be processed.
1. The local interrupt enabled bit in the peripheral module must be set. 2. The setup in the configuration register associated with the interrupt request channel must meet the
following conditions: a) The priority level must be set to non zero. b) The priority level must be greater than the current interrupt processing level in the condition
code register (CCW) of the CPU (PRIOLVL[2:0] > IPL[2:0]). 3. The I-bit in the condition code register (CCW) of the CPU must be cleared. 4. There is no access violation interrupt request pending. 5. There is no SYS, SWI, SPARE, TRAP, Machine Exception or XIRQ request pending.

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NOTE All non I-bit maskable interrupt requests always have higher priority than Ibit maskable interrupt requests. If an I-bit maskable interrupt request is interrupted by a non I-bit maskable interrupt request, the currently active interrupt processing level (IPL) remains unaffected. It is possible to nest non I-bit maskable interrupt requests, e.g., by nesting SWI, SYS or TRAP calls.
4.4.2.1 Interrupt Priority Stack
The current interrupt processing level (IPL) is stored in the condition code register (CCW) of the CPU. This way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCW from the priority level of the highest priority active interrupt request channel which is configured to be handled by the CPU. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored from the stack by executing the RTI instruction.
4.4.3 Priority Decoder
The INT module contains a priority decoder to determine the relative priority for all interrupt requests pending for the CPU.
A CPU interrupt vector is not supplied until the CPU requests it. Therefore, it is possible that a higher priority interrupt request could override the original exception which caused the CPU to request the vector. In this case, the CPU will receive the highest priority vector and the system will process this exception first instead of the original request.
If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the CPU defaults to that of the spurious interrupt vector.
NOTE Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0001DC)).
4.4.4 Reset Exception Requests
The INT module supports one system reset exception request. The different reset types are mapped to this vector (for details please refer to the Clock and Power Management Unit module (CPMU)):
1. Pin reset 2. Power-on reset 3. Low-voltage reset 4. Clock monitor reset request 5. COP watchdog reset request

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4.4.5 Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT module upon request by the CPU are shown in Table 4-8. Generally, all non-maskable interrupts have higher priorities than maskable interrupts. Please note that between the four software interrupts (Unimplemented op-code trap page1/page2 requests, SWI request, SYS request) there is no real priority defined since they cannot occur simultaneously (the S12Z CPU executes one instruction at a time).

Table 4-8. Exception Vector Map and Priority

Vector Address(1)

Source

0xFFFFFC (Vector base + 0x0001F8) (Vector base + 0x0001F4) (Vector base + 0x0001F0) (Vector base + 0x0001EC) (Vector base + 0x0001E8) (Vector base + 0x0001E4) (Vector base + 0x0001E0) (Vector base + 0x0001DC) (Vector base + 0x0001D8) (Vector base + 0x0001D4) (Vector base + 0x000010
.. Vector base + 0x0001D0)

Pin reset, power-on reset, low-voltage reset, clock monitor reset, COP watchdog reset Unimplemented page1 op-code trap (SPARE) vector request Unimplemented page2 op-code trap (TRAP) vector request Software interrupt instruction (SWI) vector request System call interrupt instruction (SYS) vector request Machine exception vector request Reserved Reserved Spurious interrupt XIRQ interrupt request IRQ interrupt request Device specific I-bit maskable interrupt sources (priority determined by the associated configuration registers, in descending order)

1. 24 bits vector address based

4.4.6 Interrupt Vector Table Layout
The interrupt vector table contains 128 entries, each 32 bits (4 bytes) wide. Each entry contains a 24-bit address (3 bytes) which is stored in the 3 low-significant bytes of the entry. The content of the most significant byte of a vector-table entry is ignored. Figure 4-13 illustrates the vector table entry format.

Bits

[31:24]

(unused)

[23:0] ISR Address

Figure 4-13. Interrupt Vector Table Entry

4.5 Initialization/Application Information

4.5.1 Initialization
After system reset, software should: · Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFFFE00­0xFFFFFB).

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· Initialize the interrupt processing level configuration data registers (INT_CFADDR, INT_CFDATA0­7) for all interrupt vector requests with the desired priority levels. It might be a good idea to disable unused interrupt requests.
· Enable I-bit maskable interrupts by clearing the I-bit in the CCW. · Enable the X-bit maskable interrupt by clearing the X-bit in the CCW (if required).

4.5.2 Interrupt Nesting
The interrupt request priority level scheme makes it possible to implement priority based interrupt request nesting for the I-bit maskable interrupt requests.
· I-bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority, so that there can be up to seven nested I-bit maskable interrupt requests at a time (refer to Figure 414 for an example using up to three nested interrupt requests).
I-bit maskable interrupt requests cannot be interrupted by other I-bit maskable interrupt requests per default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the I-bit in the CCW (CLI). After clearing the I-bit, I-bit maskable interrupt requests with higher priority can interrupt the current ISR.
An ISR of an interruptible I-bit maskable interrupt request could basically look like this:
· Service interrupt, e.g., clear interrupt flags, copy data, etc. · Clear I-bit in the CCW by executing the CPU instruction CLI (thus allowing interrupt requests with
higher priority) · Process data · Return from interrupt by executing the instruction RTI

Stacked IPL

0

0

4

0

0

0

IPL in CCW Processing Levels

0

4

7

4

3

7

6

L7

RTI

5

4

3

2

L4

RTI L3 (Pending)

1 L1 (Pending)
0

Reset

Figure 4-14. Interrupt Processing Example

1 RTI

0 RTI

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4.5.3 Wake Up from Stop or Wait Mode
4.5.3.1 CPU Wake Up from Stop or Wait Mode
Every I-bit maskable interrupt request which is configured to be handled by the CPU is capable of waking the MCU from stop or wait mode. Additionally machine exceptions can wake-up the MCU from stop or wait mode.
To determine whether an I-bit maskable interrupts is qualified to wake up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode:
· If the I-bit in the CCW is set, all I-bit maskable interrupts are masked from waking up the MCU. · An I-bit maskable interrupt is ignored if it is configured to a priority level below or equal to the
current IPL in CCW.
The X-bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the X-bit in CCW is set1. If the X-bit maskable interrupt request is used to wake-up the MCU with the Xbit in the CCW set, the associated ISR is not called. The CPU then resumes program execution with the instruction following the WAI or STOP instruction. This feature works following the same rules like any interrupt request, i.e. care must be taken that the X-bit maskable interrupt request used for wake-up remains active at least until the system begins execution of the instruction following the WAI or STOP instruction; otherwise, wake-up may not occur.

1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is shared with other peripheral modules on the device. Please refer to the Port Integration Module (PIM) section of the MCU reference manual for details.

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Chapter 5 Background Debug Controller (S12ZBDCV2)

Table 5-1. Revision History

Revision Number
V2.04 V2.05 V2.06 V2.07 V2.08
V2.09
V2.10 V2.11

Revision Date
03.Dec.2012 22.Jan.2013 22.Mar.2013 11.Apr.2013 31.May.2013
29.Aug.2013
21.Oct.2013 02.Feb.2015

Sections Affected

Description of Changes

Section 5.1.3.3 Included BACKGROUND/ Stop mode dependency
Section 5.3.2.2 Improved NORESP description and added STEP1/ Wait mode dependency
Section 5.3.2.2 Improved NORESP description of STEP1/ Wait mode dependency
Section 5.1.3.3.1 Improved STOP and BACKGROUND interdepency description
Section 5.4.4.4 Removed misleading WAIT and BACKGROUND interdepency description Section 5.4.7.1 Added subsection dedicated to Long-ACK
Section 5.4.4.12 Noted that READ_DBGTB is only available for devices featuring a trace buffer.
Section 5.1.3.3.2 Improved description of NORESP dependence on WAIT and BACKROUND
Section 5.1.3.3.1 Corrected name of clock that can stay active in Stop mode Section 5.3.2

5.1 Introduction
The background debug controller (BDC) is a single-wire, background debug system implemented in onchip hardware for minimal CPU intervention. The device BKGD pin interfaces directly to the BDC.
The S12ZBDC maintains the standard S12 serial interface protocol but introduces an enhanced handshake protocol and enhanced BDC command set to support the linear instruction set family of S12Z devices and offer easier, more flexible internal resource access over the BDC serial interface.

5.1.1 Glossary

Table 5-2. Glossary Of Terms

Term DBG BDM CPU SSC NSC BDCSI EWAIT

Definition On chip Debug Module Active Background Debug Mode S12Z CPU Special Single Chip Mode (device operating mode Normal Single Chip Mode (device operating mode) Background Debug Controller Serial Interface. This refers to the single pin BKGD serial interface. Optional S12 feature which allows external devices to delay external accesses until deassertion of EWAIT

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5.1.2 Features
The BDC includes these distinctive features: · Single-wire communication with host development system · SYNC command to determine communication rate · Genuine non-intrusive handshake protocol · Enhanced handshake protocol for error detection and stop mode recognition · Active out of reset in special single chip mode · Most commands not requiring active BDM, for minimal CPU intervention · Full global memory map access without paging · Simple flash mass erase capability
5.1.3 Modes of Operation
S12 devices feature power modes (run, wait, and stop) and operating modes (normal single chip, special single chip). Furthermore, the operation of the BDC is dependent on the device security status.
5.1.3.1 BDC Modes
The BDC features module specific modes, namely disabled, enabled and active. These modes are dependent on the device security and operating mode. In active BDM the CPU ceases execution, to allow BDC system access to all internal resources including CPU internal registers.
5.1.3.2 Security and Operating mode Dependency
In device run mode the BDC dependency is as follows · Normal modes, unsecure device General BDC operation available. The BDC is disabled out of reset. · Normal modes, secure device BDC disabled. No BDC access possible. · Special single chip mode, unsecure BDM active out of reset. All BDC commands are available. · Special single chip mode, secure BDM active out of reset. Restricted command set available.
When operating in secure mode, BDC operation is restricted to allow checking and clearing security by mass erasing the on-chip flash memory. Secure operation prevents BDC access to on-chip memory other than mass erase. The BDC command set is restricted to those commands classified as Always-available.

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Chapter 5 Background Debug Controller (S12ZBDCV2)

5.1.3.3.1 Stop Mode
The execution of the CPU STOP instruction leads to stop mode only when all bus masters (CPU, or others, depending on the device) have finished processing. The operation during stop mode depends on the ENBDC and BDCCIS bit settings as summarized in Table 5-3

Table 5-3. BDC STOP Operation Dependencies

ENBDC

BDCCIS

Description Of Operation

0

0

0

1

1

0

1

1

BDC has no effect on STOP mode. BDC has no effect on STOP mode.
Only BDCCLK clock continues All clocks continue

A disabled BDC has no influence on stop mode operation. In this case the BDCSI clock is disabled in stop mode thus it is not possible to enable the BDC from within stop mode.

STOP Mode With BDC Enabled And BDCCIS Clear
If the BDC is enabled and BDCCIS is clear, then the BDC prevents the BDCCLK clock (Figure 5-5) from being disabled in stop mode. This allows BDC communication to continue throughout stop mode in order to access the BDCCSR register. All other device level clock signals are disabled on entering stop mode.
NOTE
This is intended for application debugging, not for fast flash programming. Thus the CLKSW bit must be clear to map the BDCSI to BDCCLK.
With the BDC enabled, an internal acknowledge delays stop mode entry and exit by 2 BDCSI clock + 2 bus clock cycles. If no other module delays stop mode entry and exit, then these additional clock cycles represent a difference between the debug and not debug cases. Furthermore if a BDC internal access is being executed when the device is entering stop mode, then the stop mode entry is delayed until the internal access is complete (typically for 1 bus clock cycle).
Accesses to the internal memory map are not possible when the internal device clocks are disabled. Thus attempted accesses to memory mapped resources are suppressed and the NORESP flag is set. Resources can be accessed again by the next command received following exit from Stop mode.
A BACKGROUND command issued whilst in stop mode remains pending internally until the device leaves stop mode. This means that subsequent active BDM commands, issued whilst BACKGROUND is pending, set the ILLCMD flag because the device is not yet in active BDM.
If ACK handshaking is enabled, then the first ACK, following a stop mode entry is long to indicate a stop exception. The BDC indicates a stop mode occurrence by setting the BDCCSR bit STOP. If the host attempts further communication before the ACK pulse generation then the OVRUN bit is set.

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STOP Mode With BDC Enabled And BDCCIS Set
If the BDC is enabled and BDCCIS is set, then the BDC prevents core clocks being disabled in stop mode. This allows BDC communication, for access of internal memory mapped resources, but not CPU registers, to continue throughout stop mode.
A BACKGROUND command issued whilst in stop mode remains pending internally until the device leaves stop mode. This means that subsequent active BDM commands, issued whilst BACKGROUND is pending, set the ILLCMD flag because the device is not yet in active BDM.
If ACK handshaking is enabled, then the first ACK, following a stop mode entry is long to indicate a stop exception. The BDC indicates a stop mode occurrence by setting the BDCCSR bit STOP. If the host attempts further communication before the ACK pulse generation then the OVRUN bit is set.
5.1.3.3.2 Wait Mode
The device enters wait mode when the CPU starts to execute the WAI instruction. The second part of the WAI instruction (return from wait mode) can only be performed when an interrupt occurs. Thus on entering wait mode the CPU is in the middle of the WAI instruction and cannot permit access to CPU internal resources, nor allow entry to active BDM. Thus only commands classified as Non-Intrusive or Always-Available are possible in wait mode.
On entering wait mode, the WAIT flag in BDCCSR is set. If the ACK handshake protocol is enabled then the first ACK generated after WAIT has been set is a long-ACK pulse. Thus the host can recognize a wait mode occurrence. The WAIT flag remains set and cannot be cleared whilst the device remains in wait mode. After the device leaves wait mode the WAIT flag can be cleared by writing a "1" to it.
A BACKGROUND command issued whilst in wait mode sets the NORESP bit and the BDM active request remains pending internally until the CPU leaves wait mode due to an interrupt. The device then enters BDM with the PC pointing to the address of the first instruction of the ISR.
With ACK disabled, further Non-Intrusive or Always-Available commands are possible, in this pending state, but attempted Active-Background commands set NORESP and ILLCMD because the BDC is not in active BDM state.
With ACK enabled, if the host attempts further communication before the ACK pulse generation then the OVRUN bit is set.
Similarly the STEP1 command issued from a WAI instruction cannot be completed by the CPU until the CPU leaves wait mode due to an interrupt. The first STEP1 into wait mode sets the BDCCSR WAIT bit.
If the part is still in Wait mode and a further STEP1 is carried out then the NORESP and ILLCMD bits are set because the device is no longer in active BDM for the duration of WAI execution.
5.1.4 Block Diagram
A block diagram of the BDC is shown in Figure 5-1.

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HOST SYSTEM BKGD

SERIAL INTERFACE CONTROL AND SHIFT REGISTER

INSTRUCTION DECODE AND
FSM
BDCCSR REGISTER AND DATAPATH CONTROL

CLOCK DOMAIN CONTROL

BDCSI CORE CLOCK

BUS INTERFACE AND
CONTROL LOGIC

ADDRESS
DATA
BUS CONTROL CPU CONTROL
ERASE FLASH FLASH ERASED FLASH SECURE

Figure 5-1. BDC Block Diagram
5.2 External Signal Description
A single-wire interface pin (BKGD) is used to communicate with the BDC system. During reset, this pin is a device mode select input. After reset, this pin becomes the dedicated serial interface pin for the BDC. BKGD is a pseudo-open-drain pin with an on-chip pull-up. Unlike typical open-drain pins, the external RC time constant on this pin due to external capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speed-up pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to Section 5.4.6" for more details.
5.3 Memory Map and Register Definition

5.3.1 Module Memory Map
Table 5-4 shows the BDC memory map.
Table 5-4. BDC Memory Map

Global Address Not Applicable

Module BDC registers

Size (Bytes)
2

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5.3.2 Register Descriptions
The BDC registers are shown in Figure 5-2. Registers are accessed only by host-driven communications to the BDC hardware using READ_BDCCSR and WRITE_BDCCSR commands. They are not accessible in the device memory map.

Global Address

Register Name

Bit 7

Not

BDCCSRH R

Applicable

ENBDC W

6

5

BDMACT BDCCIS

Not

BDCCSRL R

Applicable

WAIT W

STOP RAMWF

4

3

2

0 STEAL CLKSW

OVRUN NORESP RDINV

1 UNSEC
ILLACC

Bit 0 ERASE
ILLCMD

= Unimplemented, Reserved

0

= Always read zero

5.3.2.1

Figure 5-2. BDC Register Summary
BDC Control Status Register High (BDCCSRH)

Register Address: This register is not in the device memory map. It is accessible using BDC inherent addressing commands

R W Reset Secure AND SSC-Mode Unsecure AND SSC-Mode Secure AND NSC-Mode Unsecure AND NSC-Mode

7
ENBDC
1 1 0 0

6

5

4

BDMACT

0

BDCCIS

1

0

0

1

0

0

0

0

0

0

0

0

= Unimplemented, Reserved

3
STEAL

2
CLKSW

1
UNSEC

0
ERASE

0

0

0

0

0

0

1

0

0

0

0

0

0

0

1

0

0

= Always read zero

Figure 5-3. BDC Control Status Register High (BDCCSRH)

Read: All modes through BDC operation only.
Write: All modes through BDC operation only, when not secured, but subject to the following: -- Bits 7,3 and 2 can only be written by WRITE_BDCCSR commands. -- Bit 5 can only be written by WRITE_BDCCSR commands when the device is not in stop mode. -- Bits 6, 1 and 0 cannot be written. They can only be updated by internal hardware.

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Table 5-5. BDCCSRH Field Descriptions

Field 7
ENBDC
6 BDMACT
5 BDCCIS
3 STEAL
2 CLKSW
1 UNSEC
0 ERASE

Description
Enable BDC -- This bit controls whether the BDC is enabled or disabled. When enabled, active BDM can be entered and non-intrusive commands can be carried out. When disabled, active BDM is not possible and the valid command set is restricted. Further information is provided in Table 5-7. 0 BDC disabled 1 BDC enabled Note: ENBDC is set out of reset in special single chip mode.
BDM Active Status -- This bit becomes set upon entering active BDM. BDMACT is cleared as part of the active BDM exit sequence. 0 BDM not active 1 BDM active Note: BDMACT is set out of reset in special single chip mode.
BDC Continue In Stop -- If ENBDC is set then BDCCIS selects the type of BDC operation in stop mode (as shown in Table 5-3). If ENBDC is clear, then the BDC has no effect on stop mode and no BDC communication is possible.If ACK pulse handshaking is enabled, then the first ACK pulse following stop mode entry is a long ACK. This bit cannot be written when the device is in stop mode. 0 Only the BDCCLK clock continues in stop mode 1 All clocks continue in stop mode
Steal enabled with ACK-- This bit forces immediate internal accesses with the ACK handshaking protocol enabled. If ACK handshaking is disabled then BDC accesses steal the next bus cycle. 0 If ACK is enabled then BDC accesses await a free cycle, with a timeout of 512 cycles 1 If ACK is enabled then BDC accesses are carried out in the next bus cycle
Clock Switch -- The CLKSW bit controls the BDCSI clock source. This bit is initialized to "0" by each reset and can be written to "1". Once it has been set, it can only be cleared by a reset. When setting CLKSW a minimum delay of 150 cycles at the initial clock speed must elapse before the next command can be sent. This guarantees that the start of the next BDC command uses the new clock for timing subsequent BDC communications. 0 BDCCLK used as BDCSI clock source 1 Device fast clock used as BDCSI clock source Note: Refer to the device specification to determine which clock connects to the BDCCLK and fast clock inputs.
Unsecure -- If the device is unsecure, the UNSEC bit is set automatically. 0 Device is secure. 1 Device is unsecure. Note: When UNSEC is set, the device is unsecure and the state of the secure bits in the on-chip Flash EEPROM
can be changed.
Erase Flash -- This bit can only be set by the dedicated ERASE_FLASH command. ERASE is unaffected by write accesses to BDCCSR. ERASE is cleared either when the mass erase sequence is completed, independent of the actual status of the flash array or by a soft reset. Reading this bit indicates the status of the requested mass erase sequence. 0 No flash mass erase sequence pending completion 1 Flash mass erase sequence pending completion.

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5.3.2.2 BDC Control Status Register Low (BDCCSRL)

Register Address: This register is not in the device memory map. It is accessible using BDC inherent addressing commands

R W Reset

7
WAIT 0

6
STOP 0

5
RAMWF

4
OVRUN

3
NORESP

2
RDINV

0

0

0

0

1
ILLACC 0

0
ILLCMD 0

Figure 5-4. BDC Control Status Register Low (BDCCSRL)
Read: BDC access only.
Write: Bits [7:5], [3:0] BDC access only, restricted to flag clearing by writing a "1" to the bit position. Write: Bit 4 never. It can only be cleared by a SYNC pulse.
If ACK handshaking is enabled then BDC commands with ACK causing a BDCCSRL[3:1] flag setting condition also generate a long ACK pulse. Subsequent commands that are executed correctly generate a normal ACK pulse. Subsequent commands that are not correctly executed generate a long ACK pulse. The first ACK pulse after WAIT or STOP have been set also generates a long ACK. Subsequent ACK pulses are normal, whilst STOP and WAIT remain set.
Long ACK pulses are not immediately generated if an overrun condition is caused by the host driving the BKGD pin low whilst a target ACK is pending, because this would conflict with an attempted host transmission following the BKGD edge. When a whole byte has been received following the offending BKGD edge, the OVRUN bit is still set, forcing subsequent ACK pulses to be long.
Unimplemented BDC opcodes causing the ILLCMD bit to be set do not generate a long ACK because this could conflict with further transmission from the host. If the ILLCMD is set for another reason, then a long ACK is generated for the current command if it is a BDC command with ACK.

Table 5-6. BDCCSRL Field Descriptions

Field 7
WAIT
6 STOP
5 RAMWF

Description
WAIT Indicator Flag -- Indicates that the device entered wait mode. Writing a "1" to this bit whilst in wait mode has no effect. Writing a "1" after exiting wait mode, clears the bit.
0 Device did not enter wait mode 1 Device entered wait mode.
STOP Indicator Flag -- Indicates that the CPU requested stop mode following a STOP instruction. Writing a "1" to this bit whilst not in stop mode clears the bit. Writing a "1" to this bit whilst in stop mode has no effect. This bit can only be set when the BDC is enabled.
0 Device did not enter stop mode 1 Device entered stop mode.
RAM Write Fault -- Indicates an ECC double fault during a BDC write access to RAM. Writing a "1" to this bit, clears the bit.
0 No RAM write double fault detected. 1 RAM write double fault detected.

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Table 5-6. BDCCSRL Field Descriptions (continued)

Field 4
OVRUN
3 NORESP

Description
Overrun Flag -- Indicates unexpected host activity before command completion. This occurs if a new command is received before the current command completion. With ACK enabled this also occurs if the host drives the BKGD pin low whilst a target ACK pulse is pending To protect internal resources from misinterpreted BDC accesses following an overrun, internal accesses are suppressed until a SYNC clears this bit. A SYNC clears the bit.
0 No overrun detected. 1 Overrun detected when issuing a BDC command.
No Response Flag -- Indicates that the BDC internal action or data access did not complete. This occurs in the following scenarios:
a) If no free cycle for an access is found within 512 core clock cycles. This could typically happen if a code loop without free cycles is executing with ACK enabled and STEAL clear.
b) With ACK disabled or STEAL set, when an internal access is not complete before the host starts data/BDCCSRL retrieval or an internal write access is not complete before the host starts the next BDC command.
c) Attempted internal memory or SYNC_PC accesses during STOP mode set NORESP if BDCCIS is clear. In the above cases, on setting NORESP, the BDC aborts the access if permitted. (For devices supporting EWAIT, BDC external accesses with EWAIT assertions, prevent a command from being aborted until EWAIT is deasserted).
d) If a BACKGROUND command is issued whilst the device is in wait mode the NORESP bit is set but the command is not aborted. The active BDM request is completed when the device leaves wait mode. Furthermore subsequent CPU register access commands during wait mode set the NORESP bit, should it have been cleared.
e) If a command is issued whilst awaiting return from Wait mode. This can happen when using STEP1 to step over a CPU WAI instruction, if the CPU has not returned from Wait mode before the next BDC command is received.
f) If STEP1 is issued with the BDC enabled as the device enters Wait mode regardless of the BDMACT state.

2 RDINV
1 ILLACC

When NORESP is set a value of 0xEE is returned for each data byte associated with the current access. Writing a "1" to this bit, clears the bit. 0 Internal action or data access completed. 1 Internal action or data access did not complete.
Read Data Invalid Flag -- Indicates invalid read data due to an ECC error during a BDC initiated read access. The access returns the actual data read from the location. Writing a "1" to this bit, clears the bit.
0 No invalid read data detected. 1 Invalid data returned during a BDC read access.
Illegal Access Flag -- Indicates an attempted illegal access. This is set in the following cases: When the attempted access addresses unimplemented memory When the access attempts to write to the flash array When a CPU register access is attempted with an invalid CRN (Section 5.4.5.1). Illegal accesses return a value of 0xEE for each data byte
Writing a "1" to this bit, clears the bit. 0 No illegal access detected. 1 Illegal BDC access detected.

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Table 5-6. BDCCSRL Field Descriptions (continued)

Field
0 ILLCMD

Description
Illegal Command Flag -- Indicates an illegal BDC command. This bit is set in the following cases: When an unimplemented BDC command opcode is received. When a DUMP_MEM{_WS}, FILL_MEM{_WS} or READ_SAME{_WS} is attempted in an illegal sequence. When an active BDM command is received whilst BDM is not active When a non Always-available command is received whilst the BDC is disabled or a flash mass erase is ongoing. When a non Always-available command is received whilst the device is secure Read commands return a value of 0xEE for each data byte Writing a "1" to this bit, clears the bit. 0 No illegal command detected. 1 Illegal BDC command detected.

5.4 Functional Description

5.4.1 Security
If the device resets with the system secured, the device clears the BDCCSR UNSEC bit. In the secure state BDC access is restricted to the BDCCSR register. A mass erase can be requested using the ERASE_FLASH command. If the mass erase is completed successfully, the device programs the security bits to the unsecure state and sets the BDC UNSEC bit. If the mass erase is unsuccessful, the device remains secure and the UNSEC bit is not set.
For more information regarding security, please refer to device specific security information.

5.4.2 Enabling BDC And Entering Active BDM
BDM can be activated only after being enabled. BDC is enabled by setting the ENBDC bit in the BDCCSR register, via the single-wire interface, using the command WRITE_BDCCSR. After being enabled, BDM is activated by one of the following1:
· The BDC BACKGROUND command · A CPU BGND instruction · The DBG Breakpoint mechanism
Alternatively BDM can be activated directly from reset when resetting into Special Single Chip Mode.
The BDC is ready for receiving the first command 10 core clock cycles after the deassertion of the internal reset signal. This is delayed relative to the external pin reset as specified in the device reset documentation. On S12Z devices an NVM initialization phase follows reset. During this phase the BDC commands classified as always available are carried out immediately, whereas other BDC commands are subject to delayed response due to the NVM initialization phase.
NOTE After resetting into SSC mode, the initial PC address must be supplied by the host using the WRITE_Rn command before issuing the GO command.
1. BDM active immediately out of special single-chip reset.

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When BDM is activated, the CPU finishes executing the current instruction. Thereafter only BDC commands can affect CPU register contents until the BDC GO command returns from active BDM to user code or a device reset occurs. When BDM is activated by a breakpoint, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction.
NOTE Attempting to activate BDM using a BGND instruction whilst the BDC is disabled, the CPU requires clock cycles for the attempted BGND execution. However BACKGROUND commands issued whilst the BDC is disabled are ignored by the BDC and the CPU execution is not delayed.
5.4.3 Clock Source
The BDC clock source can be mapped to a constant frequency clock source or a PLL based fast clock. The clock source for the BDC is selected by the CLKSW bit as shown in Figure 5-5. The BDC internal clock is named BDCSI clock. If BDCSI clock is mapped to the BDCCLK by CLKSW then the serial interface communication is not affected by bus/core clock frequency changes. If the BDC is mapped to BDCFCLK then the clock is connected to a PLL derived source at device level (typically bus clock), thus can be subject to frequency changes in application. Debugging through frequency changes requires SYNC pulses to re-synchronize. The sources of BDCCLK and BDCFCLK are specified at device level.
BDC accesses of internal device resources always use the device core clock. Thus if the ACK handshake protocol is not enabled, the clock frequency relationship must be taken into account by the host.
When changing the clock source via the CLKSW bit a minimum delay of 150 cycles at the initial clock speed must elapse before a SYNC can be sent. This guarantees that the start of the next BDC command uses the new clock for timing subsequent BDC communications.

BDCCLK 0
BDCFCLK 1 Core clock

BDCSI Clock CLKSW

BDC serial interface and FSM
BDC device resource interface

Figure 5-5. Clock Switch
5.4.4 BDC Commands
BDC commands can be classified into three types as shown in Table 5-7.

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Command Type

Secure Status

Always-available

Secure or Unsecure

Non-intrusive

Unsecure

Active background Unsecure

Table 5-7. BDC Command Types

BDC Status

CPU Status

Command Set

Enabled or Disabled Enabled
Active

--
Code execution allowed
Code execution
halted

· Read/write access to BDCCSR · Mass erase flash memory using ERASE_FLASH · SYNC · ACK enable/disable
· Read/write access to BDCCSR · Memory access · Memory access with status · Mass erase flash memory using ERASE_FLASH · Debug register access · BACKGROUND · SYNC · ACK enable/disable
· Read/write access to BDCCSR · Memory access · Memory access with status · Mass erase flash memory using ERASE_FLASH · Debug register access · Read or write CPU registers · Single-step the application · Exit active BDM to return to the application program (GO) · SYNC · ACK enable/disable

Non-intrusive commands are used to read and write target system memory locations and to enter active BDM. Target system memory includes all memory and registers within the global memory map, including external memory.
Active background commands are used to read and write all memory locations and CPU resources. Furthermore they allow single stepping through application code and to exit from active BDM.
Non-intrusive commands can only be executed when the BDC is enabled and the device unsecure. Active background commands can only be executed when the system is not secure and is in active BDM.
Non-intrusive commands do not require the system to be in active BDM for execution, although, they can still be executed in this mode. When executing a non-intrusive command with the ACK pulse handshake protocol disabled, the BDC steals the next bus cycle for the access. If an operation requires multiple cycles, then multiple cycles can be stolen. Thus if stolen cycles are not free cycles, the application code execution is delayed. The delay is negligible because the BDC serial transfer rate dictates that such accesses occur infrequently.
For data read commands, the external host must wait at least 16 BDCSI clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDC shift register, ready to be shifted out. For write commands, the external host must wait 16 bdcsi cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDC shift register before the write has been completed. The external host must wait at least for 16 bdcsi cycles after a control command before starting any new serial command.

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If the ACK pulse handshake protocol is enabled and STEAL is cleared, then the BDC waits for the first free bus cycle to make a non-intrusive access. If no free bus cycle occurs within 512 core clock cycles then the BDC aborts the access, sets the NORESP bit and uses a long ACK pulse to indicate an error condition to the host.

Table 5-8 summarizes the BDC command set. The subsequent sections describe each command in detail and illustrate the command structure in a series of packets, each consisting of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8  16 target BDCSI clock cycles.

The nomenclature below is used to describe the structure of the BDC commands. Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first)

/

=

d

=

dack

=

ad24

=

rd8

=

rd16

=

rd24

=

rd32

=

rd64

=

rd.sz =

wd8

=

wd16

=

wd32

=

wd.sz =

ss

=

sz

=

crn

=

WS

=

separates parts of the command delay 16 target BDCSI clock cycles (DLY) delay (16 cycles) no ACK; or delay (=> 32 cycles) then ACK.(DACK) 24-bit memory address in the host-to-target direction 8 bits of read data in the target-to-host direction 16 bits of read data in the target-to-host direction 24 bits of read data in the target-to-host direction 32 bits of read data in the target-to-host direction 64 bits of read data in the target-to-host direction read data, size defined by sz, in the target-to-host direction 8 bits of write data in the host-to-target direction 16 bits of write data in the host-to-target direction 32 bits of write data in the host-to-target direction write data, size defined by sz, in the host-to-target direction the contents of BDCCSRL in the target-to-host direction memory operand size (00 = byte, 01 = word, 10 = long) (sz = 11 is reserved and currently defaults to long) core register number, 32-bit data width command suffix signaling the operation is with status
Table 5-8. BDC Command Summary

Command Mnemonic SYNC
ACK_DISABLE
ACK_ENABLE
BACKGROUND

Command Classification

ACK

Always

N/A

Available

Always

No

Available

Always

Yes

Available

Non-Intrusive Yes

Command Structure
N/A(1)
0x03/d
0x02/dack
0x04/dack

Description
Request a timed reference pulse to determine the target BDC communication speed
Disable the communication handshake. This command does not issue an ACK pulse.
Enable the communication handshake. Issues an ACK pulse after the command is executed.
Halt the CPU if ENBDC is set. Otherwise, ignore as illegal command.

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Command Mnemonic DUMP_MEM.sz
DUMP_MEM.sz_WS
FILL_MEM.sz
FILL_MEM.sz_WS
GO GO_UNTIL(2) NOP READ_Rn READ_MEM.sz READ_MEM.sz_WS READ_DBGTB

Table 5-8. BDC Command Summary (continued)

Command Classification Non-Intrusive
Non-Intrusive
Non-Intrusive
Non-Intrusive
Active Background
Active Background Non-Intrusive
Active Background Non-Intrusive Non-Intrusive Non-Intrusive

ACK Yes
No
Yes
No
Yes Yes Yes Yes Yes No Yes

Command Structure (0x32+4 x sz)/dack/rd.sz
(0x33+4 x sz)/d/ss/rd.sz
(0x12+4 x sz)/wd.sz/dack
(0x13+4 x sz)/wd.sz/d/ss
0x08/dack

Description
Dump (read) memory based on operand size (sz). Used with READ_MEM to dump large blocks of memory. An initial READ_MEM is executed to set up the starting address of the block and to retrieve the first result. Subsequent DUMP_MEM commands retrieve sequential operands.
Dump (read) memory based on operand size (sz) and report status. Used with READ_MEM{_WS} to dump large blocks of memory. An initial READ_MEM{_WS} is executed to set up the starting address of the block and to retrieve the first result. Subsequent DUMP_MEM{_WS} commands retrieve sequential operands.
Fill (write) memory based on operand size (sz). Used with WRITE_MEM to fill large blocks of memory. An initial WRITE_MEM is executed to set up the starting address of the block and to write the first operand. Subsequent FILL_MEM commands write sequential operands.
Fill (write) memory based on operand size (sz) and report status. Used with WRITE_MEM{_WS} to fill large blocks of memory. An initial WRITE_MEM{_WS} is executed to set up the starting address of the block and to write the first operand. Subsequent FILL_MEM{_WS} commands write sequential operands.
Resume CPU user code execution

0x0C/dack
0x00/dack (0x60+CRN)/dack/rd32

Go to user program. ACK is driven upon returning to active background mode.
No operation
Read the requested CPU register

(0x30+4 x sz)/ad24/dack/rd.sz Read the appropriately-sized (sz) memory value from the location specified by the 24bit address
(0x31+4 x sz)/ad24/d/ss/rd.sz Read the appropriately-sized (sz) memory value from the location specified by the 24bit address and report status
(0x07)/dack/rd32/dack/rd32 Read 64-bits of DBG trace buffer

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Table 5-8. BDC Command Summary (continued)

Command Mnemonic

Command Classification

ACK

Command Structure

Description

READ_SAME.sz
READ_SAME.sz_WS
READ_BDCCSR SYNC_PC WRITE_MEM.sz WRITE_MEM.sz_WS WRITE_Rn WRITE_BDCCSR ERASE_FLASH STEP1 (TRACE1)

Non-Intrusive
Non-Intrusive
Always Available Non-Intrusive Non-Intrusive
Non-Intrusive
Active Background
Always Available Always Available
Active Background

Yes

(0x50+4 x sz)/dack/rd.sz Read from location. An initial READ_MEM

defines the address, subsequent

READ_SAME reads return content of

same address

No

(0x51+4 x sz)/d/ss/rd.sz Read from location. An initial READ_MEM

defines the address, subsequent

READ_SAME reads return content of

same address

No

0x2D/rd16

Read the BDCCSR register

Yes

0x01/dack/rd24

Read current PC

Yes

(0x10+4 x

Write the appropriately-sized (sz) memory

sz)/ad24/wd.sz/dack

value to the location specified by the 24-bit

address

No (0x11+4 x sz)/ad24/wd.sz/d/ss Write the appropriately-sized (sz) memory value to the location specified by the 24-bit address and report status

Yes

(0x40+CRN)/wd32/dack Write the requested CPU register

No

0x0D/wd16

Write the BDCCSR register

No

0x95/d

Mass erase internal flash

Yes

0x09/dack

Execute one CPU command.

1. The SYNC command is a special operation which does not have a command code.

2. The GO_UNTIL command is identical to the GO command if ACK is not enabled.

5.4.4.1 SYNC
The SYNC command is unlike other BDC commands because the host does not necessarily know the correct speed to use for serial communications until after it has analyzed the response to the SYNC command.
To issue a SYNC command, the host:
1. Ensures that the BKGD pin is high for at least 4 cycles of the slowest possible BDCSI clock without reset asserted.
2. Drives the BKGD pin low for at least 128 cycles of the slowest possible BDCSI clock. 3. Drives BKGD high for a brief speed-up pulse to get a fast rise time. (This speedup pulse is typically
one cycle of the host clock which is as fast as the maximum target BDCSI clock). 4. Removes all drive to the BKGD pin so it reverts to high impedance.

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5. Listens to the BKGD pin for the sync response pulse.
Upon detecting the sync request from the host (which is a much longer low time than would ever occur during normal BDC communications), the target:
1. Discards any incomplete command 2. Waits for BKGD to return to a logic high. 3. Delays 16 cycles to allow the host to stop driving the high speed-up pulse. 4. Drives BKGD low for 128 BDCSI clock cycles. 5. Drives a 1-cycle high speed-up pulse to force a fast rise time on BKGD. 6. Removes all drive to the BKGD pin so it reverts to high impedance. 7. Clears the OVRRUN flag (if set).
The host measures the low time of this 128-cycle SYNC response pulse and determines the correct speed for subsequent BDC communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the serial protocol can easily tolerate this speed error.
If the SYNC request is detected by the target, any partially executed command is discarded. This is referred to as a soft-reset, equivalent to a timeout in the serial communication. After the SYNC response, the target interprets the next negative edge (issued by the host) as the start of a new BDC command or the start of new SYNC request.
A SYNC command can also be used to abort a pending ACK pulse. This is explained in Section 5.4.8.

5.4.4.2

ACK_DISABLE
Disable host/target handshake protocol

Always Available

0x03

host  target

D L

Y

Disables the serial communication handshake protocol. The subsequent commands, issued after the ACK_DISABLE command, do not execute the hardware handshake protocol. This command is not followed by an ACK pulse.

5.4.4.3 ACK_ENABLE

Enable host/target handshake protocol

Always Available

0x02
D
host  A target C
K

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Enables the hardware handshake protocol in the serial communication. The hardware handshake is implemented by an acknowledge (ACK) pulse issued by the target MCU in response to a host command. The ACK_ENABLE command is interpreted and executed in the BDC logic without the need to interface with the CPU. An ACK pulse is issued by the target device after this command is executed. This command can be used by the host to evaluate if the target supports the hardware handshake protocol. If the target supports the hardware handshake protocol, subsequent commands are enabled to execute the hardware handshake protocol, otherwise this command is ignored by the target. Table 5-8 indicates which commands support the ACK hardware handshake protocol.
For additional information about the hardware handshake protocol, refer to Section 5.4.7," and Section 5.4.8."

5.4.4.4

BACKGROUND
Enter active background mode (if enabled)

Non-intrusive

0x04
D
host  A target C
K
Provided ENBDC is set, the BACKGROUND command causes the target MCU to enter active BDM as soon as the current CPU instruction finishes. If ENBDC is cleared, the BACKGROUND command is ignored.
A delay of 16 BDCSI clock cycles is required after the BACKGROUND command to allow the target MCU to finish its current CPU instruction and enter active background mode before a new BDC command can be accepted.
The host debugger must set ENBDC before attempting to send the BACKGROUND command the first time. Normally the host sets ENBDC once at the beginning of a debug session or after a target system reset. During debugging, the host uses GO commands to move from active BDM to application program execution and uses the BACKGROUND command or DBG breakpoints to return to active BDM.
A BACKGROUND command issued during stop or wait modes cannot immediately force active BDM because the WAI instruction does not end until an interrupt occurs. For the detailed mode dependency description refer to Section 5.1.3.3.
The host can recognize this pending BDM request condition because both NORESP and WAIT are set, but BDMACT is clear. Whilst in wait mode, with the pending BDM request, non-intrusive BDC commands are allowed.

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5.4.4.5 DUMP_MEM.sz, DUMP_MEM.sz_WS

DUMP_MEM.sz
Read memory specified by debug address register, then increment address

Non-intrusive

0x32
host  target
0x36
host  target
0x3A
host  target

Data[7-0]

D

A target 

C

host

K

Data[15-8]

Data[7-0]

D

A target 

C

host

K

target  host

Data[31-24] Data[23-16]

Data[15-8]

D

A target 

C

host

K

target  host

target  host

Data[7-0]
target  host

DUMP_MEM.sz_WS
Read memory specified by debug address register with status, then increment address

Non-intrusive

0x33
host  target
0x37
host  target
0x3B
host  target

BDCCSRL

D L

target  host

Y

BDCCSRL

D L

target  host

Y

BDCCSRL

D L

target  host

Y

Data[7-0]

target  host

Data[15-8] Data[7-0]

target  host

target  host

Data[31-24] Data23-16]

target  host

target  host

Data[15-8]
target  host

Data[7-0]
target  host

DUMP_MEM{_WS} is used with the READ_MEM{_WS} command to access large blocks of memory. An initial READ_MEM{_WS} is executed to set-up the starting address of the block and to retrieve the first result. The DUMP_MEM{_WS} command retrieves subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent DUMP_MEM{_WS} commands use this address, perform the memory read, increment it by the current operand size, and store the updated address in the temporary register. If the with-status option is specified,

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the BDCCSRL status byte is returned before the read data. This status byte reflects the state after the memory read was performed. If enabled, an ACK pulse is driven before the data bytes are transmitted. The effect of the access size and alignment on the next address to be accessed is explained in more detail in Section 5.4.5.2".
NOTE
DUMP_MEM{_WS} is a valid command only when preceded by SYNC, NOP, READ_MEM{_WS}, or another DUMP_MEM{_WS} command. Otherwise, an illegal command response is returned, setting the ILLCMD bit. NOP can be used for inter-command padding without corrupting the address pointer.
The size field (sz) is examined each time a DUMP_MEM{_WS} command is processed, allowing the operand size to be dynamically altered. The examples show the DUMP_MEM.B{_WS}, DUMP_MEM.W{_WS} and DUMP_MEM.L{_WS} commands.

5.4.4.6 FILL_MEM.sz, FILL_MEM.sz_WS

FILL_MEM.sz
Write memory specified by debug address register, then increment address

Non-intrusive

0x12
host  target
0x16
host  target
0x1A
host  target

Data[7-0]

D
host  A target C
K
Data[15-8] Data[7-0]

host  target

D
host  A target C
K

Data[31-24] Data[23-16] Data[15-8]

host  target

host  target

host  target

Data[7-0]
D
host  A target C
K

FILL_MEM.sz_WS
Write memory specified by debug address register with status, then increment address

0x13

Data[7-0]

BDCCSRL

Non-intrusive

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FILL_MEM.sz_WS

host  target
0x17
host  target
0x1B
host  target

host  target

D L

target  host

Y

Data[15-8] Data[7-0]

BDCCSRL

host  target

host  target

D L

target  host

Y

Data[31-24] Data[23-16] Data[15-8] Data[7-0]

BDCCSRL

host  target

host  target

host  target

host  target

D L

target  host

Y

FILL_MEM{_WS} is used with the WRITE_MEM{_WS} command to access large blocks of memory. An initial WRITE_MEM{_WS} is executed to set up the starting address of the block and write the first datum. If an initial WRITE_MEM{_WS} is not executed before the first FILL_MEM{_WS}, an illegal command response is returned. The FILL_MEM{_WS} command stores subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent FILL_MEM{_WS} commands use this address, perform the memory write, increment it by the current operand size, and store the updated address in the temporary register. If the with-status option is specified, the BDCCSRL status byte is returned after the write data. This status byte reflects the state after the memory write was performed. If enabled an ACK pulse is generated after the internal write access has been completed or aborted. The effect of the access size and alignment on the next address to be accessed is explained in more detail in Section 5.4.5.2"
NOTE
FILL_MEM{_WS} is a valid command only when preceded by SYNC, NOP, WRITE_MEM{_WS}, or another FILL_MEM{_WS} command. Otherwise, an illegal command response is returned, setting the ILLCMD bit. NOP can be used for inter command padding without corrupting the address pointer.
The size field (sz) is examined each time a FILL_MEM{_WS} command is processed, allowing the operand size to be dynamically altered. The examples show the FILL_MEM.B{_WS}, FILL_MEM.W{_WS} and FILL_MEM.L{_WS} commands.

5.4.4.7 GO

Go

Non-intrusive

0x08
D
host  A target C
K

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This command is used to exit active BDM and begin (or resume) execution of CPU application code. The CPU pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC. If any register (such as the PC) is altered by a BDC command whilst in BDM, the updated value is used when prefetching resumes. If enabled, an ACK is driven on exiting active BDM.
If a GO command is issued whilst the BDM is inactive, an illegal command response is returned and the ILLCMD bit is set.

5.4.4.8

GO_UNTIL
Go Until

Active Background

0x0C
D
host  A target C
K
This command is used to exit active BDM and begin (or resume) execution of application code. The CPU pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC. If any register (such as the PC) is altered by a BDC command whilst in BDM, the updated value is used when prefetching resumes.
After resuming application code execution, if ACK is enabled, the BDC awaits a return to active BDM before driving an ACK pulse. timeouts do not apply when awaiting a GO_UNTIL command ACK.
If a GO_UNTIL is not acknowledged then a SYNC command must be issued to end the pending GO_UNTIL.
If a GO_UNTIL command is issued whilst BDM is inactive, an illegal command response is returned and the ILLCMD bit is set.
If ACK handshaking is disabled, the GO_UNTIL command is identical to the GO command.

5.4.4.9

NOP
No operation

Active Background

0x00
D
host  A target C
K
NOP performs no operation and may be used as a null command where required.

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5.4.4.10 READ_Rn
Read CPU register

Active Background

0x60+CRN Data [31-24] Data [23-16] Data [15-8]

host  target

D

A target 

C

host

K

target  host

target  host

Data [7-0]
target  host

This command reads the selected CPU registers and returns the 32-bit result. Accesses to CPU registers are always 32-bits wide, regardless of implemented register width. Bytes that are not implemented return zero. The register is addressed through the CPU register number (CRN). See Section 5.4.5.1 for the CRN address decoding. If enabled, an ACK pulse is driven before the data bytes are transmitted.
If the device is not in active BDM, this command is illegal, the ILLCMD bit is set and no access is performed.

5.4.4.11 READ_MEM.sz, READ_MEM.sz_WS

Read memory at the specified address

READ_MEM.sz

Non-intrusive

0x30
host  target
0x34
host  target
0x38
host  target

Address[23-0]
host  target
Address[23-0]
host  target
Address[23-0]
host  target

Data[7-0]

D

A target 

C

host

K

Data[15-8]

Data[7-0]

D

A target 

C

host

K

target  host

Data[31-24] Data[23-16]

Data[15-8]

D

A target 

C

host

K

target  host

target  host

Data[7-0]
target  host

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READ_MEM.sz_WS Read memory at the specified address with status

Non-intrusive

0x31
host  target
0x35
host  target
0x39
host  target

Address[23-0]
host  target
Address[23-0]
host  target
Address[23-0]
host  target

BDCCSRL Data[7-0]

D L

target  host

Y

BDCCSRL

target  host
Data [15-8]

Data [7-0]

D L

target  host

Y

BDCCSRL

target  host

target  host

Data[31-24] Data[23-16]

Data [15-8]

D L

target  host

Y

target  host

target  host

target  host

Data [7-0]
target  host

Read data at the specified memory address. The address is transmitted as three 8-bit packets (msb to lsb) immediately after the command.
The hardware forces low-order address bits to zero longword accesses to ensure these accesses are on 0modulo-size alignments. Byte alignment details are described in Section 5.4.5.2". If the with-status option is specified, the BDCCSR status byte is returned before the read data. This status byte reflects the state after the memory read was performed. If enabled, an ACK pulse is driven before the data bytes are transmitted.
The examples show the READ_MEM.B{_WS}, READ_MEM.W{_WS} and READ_MEM.L{_WS} commands.

5.4.4.12 READ_DBGTB

Read DBG trace buffer

Non-intrusive

0x07
host  target

TB Line [31- TB Line [23- TB Line [15- TB Line [7-

24]

16]

8]

0]

TB Line [63- TB Line [55- TB Line [47- TB Line [39-

56]

48]

40]

32]

D

A target 

C

host

K

target  host

target  host

D
target  A target  host C host
K

target  host

target  host

target  host

This command is only available on devices, where the DBG module includes a trace buffer. Attempted use of this command on devices without a traace buffer return 0x00.
Read 64 bits from the DBG trace buffer. Refer to the DBG module description for more detailed information. If enabled an ACK pulse is generated before each 32-bit longword is ready to be read by the host. After issuing the first ACK a timeout is still possible whilst accessing the second 32-bit longword, since this requires separate internal accesses. The first 32-bit longword corresponds to trace buffer line

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bits[31:0]; the second to trace buffer line bits[63:32]. If ACK handshaking is disabled, the host must wait 16 clock cycles (DLY) after completing the first 32-bit read before starting the second 32-bit read.

5.4.4.13 READ_SAME.sz, READ_SAME.sz_WS

READ_SAME Read same location specified by previous READ_MEM{_WS}

Non-intrusive

0x54
host  target

Data[15-8]

D

A target 

C

host

K

Data[7-0]
target  host

READ_SAME_WS Read same location specified by previous READ_MEM{_WS}

Non-intrusive

0x55
host  target

BDCCSRL

D L

target  host

Y

Data [15-8]
target  host

Data [7-0]
target  host

Read from location defined by the previous READ_MEM. The previous READ_MEM command defines the address, subsequent READ_SAME commands return contents of same address. The example shows the sequence for reading a 16-bit word size. Byte alignment details are described in Section 5.4.5.2". If enabled, an ACK pulse is driven before the data bytes are transmitted.
NOTE
READ_SAME{_WS} is a valid command only when preceded by SYNC, NOP, READ_MEM{_WS}, or another READ_SAME{_WS} command. Otherwise, an illegal command response is returned, setting the ILLCMD bit. NOP can be used for inter-command padding without corrupting the address pointer.

5.4.4.14 READ_BDCCSR
Read BDCCSR Status Register

Always Available

0x2D

BDCCSR [15:8]

host  target

D L

Y

target  host

BDCCSR [7-0]
target  host

Read the BDCCSR status register. This command can be executed in any mode.

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5.4.4.15 SYNC_PC
Sample current PC

Chapter 5 Background Debug Controller (S12ZBDCV2)
Non-intrusive

0x01
host  target

PC data[23­

PC

16]

data[15­8]

D

A target 

C

host

K

target  host

PC data[7­0]
target  host

This command returns the 24-bit CPU PC value to the host. Unsuccessful SYNC_PC accesses return 0xEE for each byte. If enabled, an ACK pulse is driven before the data bytes are transmitted. The value of 0xEE is returned if a timeout occurs, whereby NORESP is set. This can occur if the CPU is executing the WAI instruction, or the STOP instruction with BDCCIS clear, or if a CPU access is delayed by EWAIT. If the CPU is executing the STOP instruction and BDCCIS is set, then SYNC_PC returns the PC address of the instruction following STOP in the code listing.
This command can be used to dynamically access the PC for performance monitoring as the execution of this command is considerably less intrusive to the real-time operation of an application than a BACKGROUND/read-PC/GO command sequence. Whilst the BDC is not in active BDM, SYNC_PC returns the PC address of the instruction currently being executed by the CPU. In active BDM, SYNC_PC returns the address of the next instruction to be executed on returning from active BDM. Thus following a write to the PC in active BDM, a SYNC_PC returns that written value.

5.4.4.16 WRITE_MEM.sz, WRITE_MEM.sz_WS

Write memory at the specified address

WRITE_MEM.sz

Non-intrusive

0x10
host  target
0x14
host  target
0x18
host  target

Address[23-0] host  target Address[23-0] host  target Address[23-0] host  target

Data[7­0]

D
host  A target C
K
Data[15­8] Data[7­0]

host  target

D
host  A target C
K

Data[31­24] Data[23­16] Data[15­8]

host  target

host  target

host  target

Data[7­0]
D
host  A target C
K

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WRITE_MEM.sz_WS Write memory at the specified address with status

Non-intrusive

0x11
host  target
0x15
host  target
0x19
host  target

Address[23-0]
host  target
Address[23-0]
host  target
Address[23-0]
host  target

Data[7­0]

BDCCSRL

host  target

D L

target  host

Y

Data[15­8] Data[7­0]

BDCCSRL

host  target

host  target

D L

target  host

Y

Data[31­24] Data[23­16] Data[15­8] Data[7­0]

BDCCSRL

host  target

host  target

host  target

host  target

D L

target  host

Y

Write data to the specified memory address. The address is transmitted as three 8-bit packets (msb to lsb) immediately after the command.
If the with-status option is specified, the status byte contained in BDCCSRL is returned after the write data. This status byte reflects the state after the memory write was performed. The examples show the WRITE_MEM.B{_WS}, WRITE_MEM.W{_WS}, and WRITE_MEM.L{_WS} commands. If enabled an ACK pulse is generated after the internal write access has been completed or aborted.
The hardware forces low-order address bits to zero longword accesses to ensure these accesses are on 0modulo-size alignments. Byte alignment details are described in Section 5.4.5.2".

5.4.4.17 WRITE_Rn
Write general-purpose CPU register

Active Background

0x40+CRN Data [31­24] Data [23­16] Data [15­8]

host  target

host  target

host  target

host  target

Data [7­0]
D
host  A target C
K

If the device is in active BDM, this command writes the 32-bit operand to the selected CPU generalpurpose register. See Section 5.4.5.1 for the CRN details. Accesses to CPU registers are always 32-bits wide, regardless of implemented register width. If enabled an ACK pulse is generated after the internal write access has been completed or aborted.
If the device is not in active BDM, this command is rejected as an illegal operation, the ILLCMD bit is set and no operation is performed.

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Write BDCCSR

Chapter 5 Background Debug Controller (S12ZBDCV2)
Always Available

0x0D
host  target

BDCCSR Data [15-8]

D L

host  target

Y

BDCCSR Data [7-0]
host  target

16-bit write to the BDCCSR register. No ACK pulse is generated. Writing to this register can be used to configure control bits or clear flag bits. Refer to the register bit descriptions.

5.4.4.19 ERASE_FLASH
Erase FLASH

Always Available

0x95

host  target

D L

Y

Mass erase the internal flash. This command can always be issued. On receiving this command twice in succession, the BDC sets the ERASE bit in BDCCSR and requests a flash mass erase. Any other BDC command following a single ERASE_FLASH initializes the sequence, such that thereafter the ERASE_FLASH must be applied twice in succession to request a mass erase. If 512 BDCSI clock cycles elapse between the consecutive ERASE_FLASH commands then a timeout occurs, which forces a soft reset and initializes the sequence. The ERASE bit is cleared when the mass erase sequence has been completed. No ACK is driven.
During the mass erase operation, which takes many clock cycles, the command status is indicated by the ERASE bit in BDCCSR. Whilst a mass erase operation is ongoing, Always-available commands can be issued. This allows the status of the erase operation to be polled by reading BDCCSR to determine when the operation is finished.
The status of the flash array can be verified by subsequently reading the flash error flags to determine if the erase completed successfully.
ERASE_FLASH can be aborted by a SYNC pulse forcing a soft reset.
NOTE: Device Bus Frequency Considerations
The ERASE_FLASH command requires the default device bus clock frequency after reset. Thus the bus clock frequency must not be changed following reset before issuing an ERASE_FLASH command.

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5.4.4.20 STEP1
Step1

Active Background

0x09
D
host  A target C
K
This command is used to step through application code. In active BDM this command executes the next CPU instruction in application code. If enabled an ACK is driven.
If a STEP1 command is issued and the CPU is not halted, the command is ignored.
Using STEP1 to step through a CPU WAI instruction is explained in Section 5.1.3.3.2.

5.4.5 BDC Access Of Internal Resources
Unsuccessful read accesses of internal resources return a value of 0xEE for each data byte. This enables a debugger to recognize a potential error, even if neither the ACK handshaking protocol nor a status command is currently being executed. The value of 0xEE is returned in the following cases.
· Illegal address access, whereby ILLACC is set · Invalid READ_SAME or DUMP_MEM sequence · Invalid READ_Rn command (BDM inactive or CRN incorrect) · Internal resource read with timeout, whereby NORESP is set

5.4.5.1 BDC Access Of CPU Registers

The CRN field of the READ_Rn and WRITE_Rn commands contains a pointer to the CPU registers. The mapping of CRN to CPU registers is shown in Table 5-9. Accesses to CPU registers are always 32-bits wide, regardless of implemented register width. This means that the BDC data transmission for these commands is 32-bits long. The valid bits of the transfer are listed in the Valid Data Bits column. The other bits of the transmission are redundant.

Attempted accesses of CPU registers using a CRN of 0xD,0xE or 0xF is invalid, returning the value 0xEE for each byte and setting the ILLACC bit.
Table 5-9. CPU Register Number (CRN) Mapping

CPU Register
D0 D1 D2 D3 D4 D5 D6

Valid Data Bits
[7:0] [7:0] [15:0] [15:0] [15:0] [15:0] [31:0]

Command
WRITE_D0 WRITE_D1 WRITE_D2 WRITE_D3 WRITE_D4 WRITE_D5 WRITE_D6

Opcode
0x40 0x41 0x42 0x43 0x44 0x45 0x46

Command
READ_D0 READ_D1 READ_D2 READ_D3 READ_D4 READ_D5 READ_D6

Opcode
0x60 0x61 0x62 0x63 0x64 0x65 0x66

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D7 X Y SP PC CCR

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Table 5-9. CPU Register Number (CRN) Mapping

Valid Data Bits
[31:0] [23:0] [23:0] [23:0] [23:0] [15:0]

Command
WRITE_D7 WRITE_X WRITE_Y WRITE_SP WRITE_PC WRITE_CCR

Opcode
0x47 0x48 0x49 0x4A 0x4B 0x4C

Command
READ_D7 READ_X READ_Y READ_SP READ_PC READ_CCR

Opcode
0x67 0x68 0x69 0x6A 0x6B 0x6C

5.4.5.2 BDC Access Of Device Memory Mapped Resources

The device memory map is accessed using READ_MEM, DUMP_MEM, WRITE_MEM, FILL_MEM and READ_SAME, which support different access sizes, as explained in the command descriptions.

When an unimplemented command occurs during a DUMP_MEM, FILL_MEM or READ_SAME sequence, then that sequence is ended.

Illegal read accesses return a value of 0xEE for each byte. After an illegal access FILL_MEM and READ_SAME commands are not valid, and it is necessary to restart the internal access sequence with READ_MEM or WRITE_MEM. An illegal access does not break a DUMP_MEM sequence. After read accesses that cause the RDINV bit to be set, DUMP_MEM and READ_SAME commands are valid, it is not necessary to restart the access sequence with a READ_MEM.

The hardware forces low-order address bits to zero for longword accesses to ensure these accesses are realigned to 0-modulo-size alignments.

Word accesses map to 2-bytes from within a 4-byte field as shown in Table 5-10. Thus if address bits [1:0] are both logic "1" the access is realigned so that it does not straddle the 4-byte boundary but accesses data from within the addressed 4-byte field.
Table 5-10. Field Location to Byte Access Mapping

Address[1:0]
00 01 10 11 00 01 10 11 00 01 10 11

Access Size
32-bit 32-bit 32-bit 32-bit 16-bit 16-bit 16-bit 16-bit 8-bit 8-bit 8-bit 8-bit

00 Data[31:24] Data[31:24] Data[31:24] Data[31:24] Data [15:8]
Data [7:0]

01
Data[23:16] Data[23:16] Data[23:16] Data[23:16] Data [7:0] Data [15:8]

10 Data [15:8] Data [15:8] Data [15:8] Data [15:8]
Data [7:0] Data [15:8] Data [15:8]

11 Data [7:0] Data [7:0] Data [7:0] Data [7:0]
Data [7:0] Data [7:0]

Data [7:0] Data [7:0] Data [7:0]
Denotes byte that is not transmitted

Note Realigned Realigned Realigned
Realigned

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5.4.5.2.1 FILL_MEM and DUMP_MEM Increments and Alignment

FILL_MEM and DUMP_MEM increment the previously accessed address by the previous access size to calculate the address of the current access. On misaligned longword accesses, the address bits [1:0] are forced to zero, therefore the following FILL_MEM or DUMP_MEM increment to the first address in the next 4-byte field. This is shown in Table 5-11, the address of the first DUMP_MEM.32 following READ_MEM.32 being calculated from 0x004000+4.

When misaligned word accesses are realigned, then the original address (not the realigned address) is incremented for the following FILL_MEM, DUMP_MEM command.

Misaligned word accesses can cause the same locations to be read twice as shown in rows 6 and 7. The hardware ensures alignment at an attempted misaligned word access across a 4-byte boundary, as shown in row 7. The following word access in row 8 continues from the realigned address of row 7.

d

Table 5-11. Consecutive Accesses With Variable Size

Row
1 2 3 4 5 6 7 8

Command
READ_MEM.32 DUMP_MEM.32 DUMP_MEM.16 DUMP_MEM.16 DUMP_MEM.08 DUMP_MEM.16 DUMP_MEM.16 DUMP_MEM.16

Address
0x004003 0x004004 0x004008 0x00400A 0x00400C 0x00400D 0x00400E 0x004010

Address[1:0]
11 00 00 10 00 01 10 01

00 Accessed Accessed Accessed
Accessed
Accessed

01 Accessed Accessed Accessed
Accessed
Accessed

10 Accessed Accessed
Accessed
Accessed Accessed

11 Accessed Accessed Accessed
Accessed

5.4.5.2.2 READ_SAME Effects Of Variable Access Size

READ_SAME uses the unadjusted address given in the previous READ_MEM command as a base address for subsequent READ_SAME commands. When the READ_MEM and READ_SAME size parameters differ then READ_SAME uses the original base address buts aligns 32-bit and 16-bit accesses, where those accesses would otherwise cross the aligned 4-byte boundary. Table 5-12 shows some examples of this.

d

Table 5-12. Consecutive READ_SAME Accesses With Variable Size

Row
1 2 3 4 5 6 7 8 9

Command
READ_MEM.32 READ_SAME.32 READ_SAME.16 READ_SAME.08 READ_MEM.08 READ_SAME.08 READ_SAME.16 READ_SAME.32 READ_MEM.08

Base Address
0x004003 -- -- --
0x004000 -- -- --
0x004002

00 Accessed Accessed
Accessed Accessed Accessed Accessed

01 Accessed Accessed
Accessed Accessed

10 Accessed Accessed Accessed
Accessed Accessed

11 Accessed Accessed Accessed Accessed
Accessed

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Table 5-12. Consecutive READ_SAME Accesses With Variable Size

Row
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Command
READ_SAME.08 READ_SAME.16 READ_SAME.32 READ_MEM.08 READ_SAME.08 READ_SAME.16 READ_SAME.32 READ_MEM.16 READ_SAME.08 READ_SAME.16 READ_SAME.32 READ_MEM.16 READ_SAME.08 READ_SAME.16 READ_SAME.32

Base Address
-- -- -- 0x004003 -- -- -- 0x004001 -- -- -- 0x004003 -- -- --

00 Accessed Accessed Accessed Accessed

01
Accessed
Accessed Accessed Accessed Accessed Accessed
Accessed

10 Accessed Accessed Accessed
Accessed Accessed Accessed
Accessed Accessed Accessed
Accessed Accessed

11
Accessed Accessed Accessed Accessed Accessed Accessed
Accessed Accessed Accessed Accessed Accessed

5.4.6 BDC Serial Interface
The BDC communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDC.
The BDC serial interface uses an internal clock source, selected by the CLKSW bit in the BDCCSR register. This clock is referred to as the target clock in the following explanation.
The BDC serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if during a command 512 clock cycles occur between falling edges from the host. The timeout forces the current command to be discarded.
The BKGD pin is a pseudo open-drain pin and has a weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide brief drive-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases.
The timing for host-to-target is shown in Figure 5-6 and that of target-to-host in Figure 5-7 and Figure 5-8. All cases begin when the host drives the BKGD pin low to generate a falling edge. Since the host and target operate from separate clocks, it can take the target up to one full clock cycle to recognize this edge; this synchronization uncertainty is illustrated in Figure 5-6. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low

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to start the bit up to one target clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time.
Figure 5-6 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic requires the pin be driven high no later than eight target clock cycles after the falling edge for a logic 1 transmission.
Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals.
BDCSI clock (TARGET MCU)
HOST TRANSMIT 1

HOST TRANSMIT 0

SYNCHRONIZATION UNCERTAINTY
PERCEIVED START OF BIT TIME

10 CYCLES TARGET SENSES BIT LEVEL

EARLIEST START OF NEXT BIT

Figure 5-6. BDC Host-to-Target Serial Bit Timing

Figure 5-7 shows the host receiving a logic 1 from the target system. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low drive at the latest after 6 clock cycles, before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time.

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BDCSI clock (TARGET MCU)
HOST DRIVE TO BKGD PIN

HIGH-IMPEDANCE

TARGET MCU SPEEDUP PULSE PERCEIVED START
OF BIT TIME BKGD PIN

HIGH-IMPEDANCE R-C RISE

HIGH-IMPEDANCE

10 CYCLES 10 CYCLES

EARLIEST START OF NEXT BIT

HOST SAMPLES BKGD PIN

Figure 5-7. BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 5-8 shows the host receiving a logic 0 from the target. The host initiates the bit time but the target finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time.

BDCSI clock (TARGET MCU)

HOST DRIVE TO BKGD PIN

HIGH-IMPEDANCE

TARGET MCU DRIVE AND
SPEED-UP PULSE PERCEIVED START
OF BIT TIME BKGD PIN

SPEEDUP PULSE

10 CYCLES 10 CYCLES

EARLIEST START OF NEXT BIT

HOST SAMPLES BKGD PIN
Figure 5-8. BDC Target-to-Host Serial Bit Timing (Logic 0)

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5.4.7 Serial Interface Hardware Handshake (ACK Pulse) Protocol
BDC commands are processed internally at the device core clock rate. Since the BDCSI clock can be asynchronous relative to the bus frequency, a handshake protocol is provided so the host can determine when an issued command has been executed. This section describes the hardware handshake protocol.
The hardware handshake protocol signals to the host controller when a BDC command has been executed by the target. This protocol is implemented by a low pulse (16 BDCSI clock cycles) followed by a brief speedup pulse on the BKGD pin, generated by the target MCU when a command, issued by the host, has been successfully executed (see Figure 5-9). This pulse is referred to as the ACK pulse. After the ACK pulse has finished, the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command.
BDCSI clock (TARGET MCU)

TARGET TRANSMITS ACK PULSE
BKGD PIN

HIGH-IMPEDANCE

16 CYCLES

32 CYCLES

SPEED UP PULSE
MINIMUM DELAY FROM THE BDC COMMAND

HIGH-IMPEDANCE

16th CYCLE OF THE LAST COMMAND BIT

Figure 5-9. Target Acknowledge Pulse (ACK)

EARLIEST START OF NEXT BIT

The handshake protocol is enabled by the ACK_ENABLE command. The BDC sends an ACK pulse when the ACK_ENABLE command has been completed. This feature can be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol.

Unlike the normal bit transfer, where the host initiates the transmission by issuing a negative edge on the BKGD pin, the serial interface ACK handshake pulse is initiated by the target MCU by issuing a negative edge on the BKGD pin. Figure 5-9 specifies the timing when the BKGD pin is being driven. The host must follow this timing constraint in order to avoid the risk of an electrical conflict at the BKGD pin.

When the handshake protocol is enabled, the STEAL bit in BDCCSR selects if bus cycle stealing is used to gain immediate access. If STEAL is cleared, the BDC is configured for low priority bus access using free cycles, without stealing cycles. This guarantees that BDC accesses remain truly non-intrusive to not affect the system timing during debugging. If STEAL is set, the BDC gains immediate access, if necessary stealing an internal bus cycle.

NOTE
If bus steals are disabled then a loop with no free cycles cannot allow access. In this case the host must recognize repeated NORESP messages and then issue a BACKGROUND command to stop the target and access the data.

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Figure 5-10 shows the ACK handshake protocol without steal in a command level timing diagram. The READ_MEM.B command is used as an example. First, the 8-bit command code is sent by the host, followed by the address of the memory location to be read. The target BDC decodes the command. Then an internal access is requested by the BDC. When a free bus cycle occurs the READ_MEM.B operation is carried out. If no free cycle occurs within 512 core clock cycles then the access is aborted, the NORESP flag is set and the target generates a Long-ACK pulse.
Having retrieved the data, the BDC issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved. After detecting the ACK pulse, the host initiates the data read part of the command.
TARGET HOST

BKGD PIN

READ_MEM.B

ADDRESS[23­0]

HOST TARGET

BYTE IS RETRIEVED

NEW BDC COMMAND

HOST TARGET

BDC ISSUES THE ACK PULSE (NOT TO SCALE)

BDC DECODES THE COMMAND

MCU EXECUTES THE READ_MEM.B COMMAND

Figure 5-10. Handshake Protocol at Command Level
Alternatively, setting the STEAL bit configures the handshake protocol to make an immediate internal access, independent of free bus cycles.
The ACK handshake protocol does not support nested ACK pulses. If a BDC command is not acknowledged by an ACK pulse, the host needs to abort the pending command first in order to be able to issue a new BDC command. The host can decide to abort any possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted.
Commands With-Status do not generate an ACK, thus if ACK is enabled and a With-Status command is issued, the host must use the 512 cycle timeout to calculate when the data is ready for retrieval.

5.4.7.1 Long-ACK Hardware Handshake Protocol
If a command results in an error condition, whereby a BDCCSRL flag is set, then the target generates a "Long-ACK" low pulse of 64 BDCSI clock cycles, followed by a brief speed pulse. This indicates to the host that an error has occurred. The host can subsequently read BDCCSR to determine the type of error. Whether normal ACK or Long-ACK, the ACK pulse is not issued earlier than 32 BDCSI clock cycles after the BDC command was issued. The end of the BDC command is assumed to be the 16th BDCSI clock cycle of the last bit. The 32 cycle minimum delay differs from the 16 cycle delay time with ACK disabled.
If a BDC access request does not gain access within 512 core clock cycles, the request is aborted, the NORESP flag is set and a Long-ACK pulse is transmitted to indicate an error case.

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Following a STOP or WAI instruction, if the BDC is enabled, the first ACK, following stop or wait mode entry is a long ACK to indicate an exception.

5.4.8 Hardware Handshake Abort Procedure

The abort procedure is based on the SYNC command. To abort a command that has not responded with an ACK pulse, the host controller generates a sync request (by driving BKGD low for at least 128 BDCSI clock cycles and then driving it high for one BDCSI clock cycle as a speedup pulse). By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol, see Section 5.4.4.1", and assumes that the pending command and therefore the related ACK pulse are being aborted. After the SYNC protocol has been completed the host is free to issue new BDC commands.
The host can issue a SYNC close to the 128 clock cycles length, providing a small overhead on the pulse length to assure the sync pulse is not misinterpreted by the target. See Section 5.4.4.1".
Figure 5-11 shows a SYNC command being issued after a READ_MEM, which aborts the READ_MEM command. Note that, after the command is aborted a new command is issued by the host.

READ_MEM.B CMD
IS ABORTED BY THE SYNC REQUEST (NOT TO SCALE)

SYNC RESPONSE FROM THE TARGET (NOT TO SCALE)

BKGD PIN READ_MEM.B

ADDRESS[23-0]

READ_BDCCSR

NEW BDC COMMAND

HOST TARGET

HOST TARGET

HOST TARGET

BDC DECODES AND TRYS TO EXECUTE

NEW BDC COMMAND

Figure 5-11. ACK Abort Procedure at the Command Level (Not To Scale)

Figure 5-12 shows a conflict between the ACK pulse and the SYNC request pulse. The target is executing a pending BDC command at the exact moment the host is being connected to the BKGD pin. In this case, an ACK pulse is issued simultaneously to the SYNC command. Thus there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. As this is not a probable situation, the protocol does not prevent this conflict from happening.

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BDCSI clock (TARGET MCU)
TARGET MCU DRIVES TO BKGD PIN HOST
DRIVES SYNC TO BKGD PIN
BKGD PIN

AT LEAST 128 CYCLES

ACK PULSE HOST AND TARGET DRIVE TO BKGD PIN

HIGH-IMPEDANCE ELECTRICAL CONFLICT

HOST SYNC REQUEST PULSE

16 CYCLES

SPEEDUP PULSE

Figure 5-12. ACK Pulse and SYNC Request Conflict
5.4.9 Hardware Handshake Disabled (ACK Pulse Disabled)
The default state of the BDC after reset is hardware handshake protocol disabled. It can also be disabled by the ACK_DISABLE BDC command. This provides backwards compatibility with the existing host devices which are not able to execute the hardware handshake protocol. For host devices that support the hardware handshake protocol, true non-intrusive debugging and error flagging is offered.
If the ACK pulse protocol is disabled, the host needs to use the worst case delay time at the appropriate places in the protocol.
If the handshake protocol is disabled, the access is always independent of free cycles, whereby BDC has higher priority than CPU. Since at least 2 bytes (command byte + data byte) are transferred over BKGD the maximum intrusiveness is only once every few hundred cycles.
After decoding an internal access command, the BDC then awaits the next internal core clock cycle. The relationship between BDCSI clock and core clock must be considered. If the host retrieves the data immediately, then the BDCSI clock frequency must not be more than 4 times the core clock frequency, in order to guarantee that the BDC gains bus access within 16 the BDCSI cycle DLY period following an access command. If the BDCSI clock frequency is more than 4 times the core clock frequency, then the host must use a suitable delay time before retrieving data (see 5.5.1/5-221). Furthermore, for stretched read accesses to external resources via a device expanded bus (if implemented) the potential extra stretch cycles must be taken into consideration before attempting to obtain read data.
If the access does not succeed before the host starts data retrieval then the NORESP flag is set but the access is not aborted. The NORESP state can be used by the host to recognize an unexpected access conflict due to stretched expanded bus accesses. Although the NORESP bit is set when an access does not succeed before the start of data retrieval, the access may succeed in following bus cycles if the internal access has already been initiated.

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5.4.10 Single Stepping
When a STEP1 command is issued to the BDC in active BDM, the CPU executes a single instruction in the user code and returns to active BDM. The STEP1 command can be issued repeatedly to step through the user code one instruction at a time.
If an interrupt is pending when a STEP1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. In this case the stacking counts as one instruction. The device re-enters active BDM with the program counter pointing to the first instruction in the interrupt service routine.
When stepping through the user code, the execution of the user code is done step by step but peripherals are free running. Some peripheral modules include a freeze feature, whereby their clocks are halted when the device enters active BDM. Timer modules typically include the freeze feature. Serial interface modules typically do not include the freeze feature. Hence possible timing relations between CPU code execution and occurrence of events of peripherals no longer exist.
If the handshake protocol is enabled and BDCCIS is set then stepping over the STOP instruction causes the Long-ACK pulse to be generated and the BDCCSR STOP flag to be set. When stop mode is exited due to an interrupt the device enters active BDM and the PC points to the start of the corresponding interrupt service routine. Stepping can be continued.
Stepping over a WAI instruction, the STEP1 command cannot be finished because active BDM cannot be entered after CPU starts to execute the WAI instruction.
Stepping over the WAI instruction causes the BDCCSR WAIT and NORESP flags to be set and, if the handshake protocol is enabled, then the Long-ACK pulse is generated. Then the device enters wait mode, clears the BDMACT bit and awaits an interrupt to leave wait mode. In this time non-intrusive BDC commands are possible, although the STEP1 has actually not finished. When an interrupt occurs the device leaves wait mode, enters active BDM and the PC points to the start of the corresponding interrupt service routine. A further ACK related to stepping over the WAI is not generated.
5.4.11 Serial Communication Timeout
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target waits for a rising edge on BKGD in order to answer the SYNC request pulse. When the BDC detects the rising edge a soft reset is generated, whereby the current BDC command is discarded. If the rising edge is not detected, the target keeps waiting forever without any timeout limit.
If a falling edge is not detected by the target within 512 clock cycles since the last falling edge, a timeout occurs and the current command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft-reset. This timeout also applies if 512 cycles elapse between 2 consecutive ERASE_FLASH commands. The soft reset is disabled whilst the internal flash mass erase operation is pending completion.
timeouts are also possible if a BDC command is partially issued, or data partially retrieved. Thus if a time greater than 512 BDCSI clock cycles is observed between two consecutive negative edges, a soft-reset occurs causing the partially received command or data retrieved to be discarded. The next negative edge

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at the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDC command, or the start of a SYNC request pulse.
5.5 Application Information
5.5.1 Clock Frequency Considerations
Read commands without status and without ACK must consider the frequency relationship between BDCSI and the internal core clock. If the core clock is slow, then the internal access may not have been carried out within the standard 16 BDCSI cycle delay period (DLY). The host must then extend the DLY period or clock frequencies accordingly. Taking internal clock domain synchronizers into account, the minimum number of BDCSI periods required for the DLY is expressed by:
#DLY > 3(f(BDCSI clock) / f(core clock)) + 4 and the minimum core clock frequency with respect to BDCSI clock frequency is expressed by Minimum f(core clock) = (3/(#DLY cycles -4))f(BDCSI clock) For the standard 16 period DLY this yields f(core clock)>= (1/4)f(BDCSI clock)

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Table 6-1. Revision History Table

Revision Number

Revision Date

Sections Affected

Description Of Changes

2.08 16.NOV.2012 Section 6.5.1 Modified step over breakpoint information

2.09 19.DEC.2012

General

Formatting corrections

2.10

28.JUN.2013

General

Emphasized need to set TSOURCE for tracing or profiling

Section 6.3.2.21 Corrected DBGCDM write access dependency

Section 6.3.2.1 Corrrected ARM versus PTACT dependency

Section 6.3.2.5 Modified DBGTBH read access dependencies

2.11

15.JUL.2013 Section 6.3.2 Added explicit names to state control register bit fields

4.00

18.SEP.2013

General

Added PREND bit to improve usability of profiling format for debugging

4.01

18.OCT.2013 Section 6.4.5.4 Removed trace buffer read dependence on PROFILE bit

Section 6.4.6.3 Corrected reference to timestamp clock source in profiling mode

4.02

03.FEB.2015

Section 6.1 Updated Table 6-2 and preceding NOTE to support V2, V3 and V4

6.1

Introduction

NOTE
Device reference manuals specify which S12Z Debug module version is integrated on the device. Some reference manuals support families of devices, with device dependent Debug module versions. This chapter describes the superset. The feature differences are listed in Table 6-2.

Table 6-2. Comparison of S12Z Debug Module Versions

S12Z Debug V2

S12Z Debug V4

S12Z Debug V3 (Lite)

Tracing included Profiling included Comparator C included Match 2 trigger included PREND bit not included

Tracing included Profiling included Comparator C included Match 2 trigger included PREND bit included

Tracing not included Profiling not included
Comparator C not included Match 2 trigger not included
PREND bit not included

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The DBG module provides on-chip breakpoints and trace buffer with flexible triggering capability to allow non-intrusive debug of application software. The DBG module is optimized for the S12Z architecture and allows debugging of CPU module operations.
Typically the DBG module is used in conjunction with the BDC module, whereby the user configures the DBG module for a debugging session over the BDC interface. Once configured the DBG module is armed and the device leaves active BDM returning control to the user program, which is then monitored by the DBG module. Alternatively the DBG module can be configured over a serial interface using SWI routines.

6.1.1
Term COF
PC BDM
BDC WORD Data Line CPU Trigger

Glossary
Table 6-3. Glossary Of Terms
Definition
Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt Program Counter Background Debug Mode. In this mode CPU application code execution is halted. Execution of BDC "active BDM" commands is possible. Background Debug Controller 16-bit data entity 64-bit data entity S12Z CPU module A trace buffer input that triggers tracing start, end or mid point

6.1.2 Overview
The comparators monitor the bus activity of the CPU. A single comparator match or a series of matches can trigger bus tracing and/or generate breakpoints. A state sequencer determines if the correct series of matches occurs. Similarly an external event can trigger bus tracing and/or generate breakpoints.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads.

6.1.3 Features
· Four comparators (A, B, C, and D) -- Comparators A and C compare the full address bus and full 32-bit data bus -- Comparators A and C feature a data bus mask register -- Comparators B and D compare the full address bus only -- Each comparator can be configured to monitor PC addresses or addresses of data accesses -- Each comparator can select either read or write access cycles -- Comparator matches can force state sequencer state transitions

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· Three comparator modes -- Simple address/data comparator match mode -- Inside address range mode, Addmin  Address Addmax -- Outside address range match mode, Address Addminor Address  Addmax
· State sequencer control -- State transitions forced by comparator matches -- State transitions forced by software write to TRIG -- State transitions forced by an external event
· The following types of breakpoints -- CPU breakpoint entering active BDM on breakpoint (BDM) -- CPU breakpoint executing SWI on breakpoint (SWI)
· Trace control -- Tracing session triggered by state sequencer -- Begin, End, and Mid alignment of tracing to trigger
· Four trace modes -- Normal: change of flow (COF) PC information is stored (see Section 6.4.5.2.1) for change of flow definition. -- Loop1: same as Normal but inhibits consecutive duplicate source address entries -- Detail: address and data for all read/write access cycles are stored -- Pure PC: All program counter addresses are stored.
· 2 Pin (data and clock) profiling interface -- Output of code flow information
6.1.4 Modes of Operation
The DBG module can be used in all MCU functional modes.
The DBG module can issue breakpoint requests to force the device to enter active BDM or an SWI ISR. The BDC BACKGROUND command is also handled by the DBG to force the device to enter active BDM. When the device enters active BDM through a BACKGROUND command with the DBG module armed, the DBG remains armed.

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6.1.5 Block Diagram
B

EXTERNAL EVENT CPU BUS

BUS INTERFACE COMPARATOR MATCH CONTROL

REGISTERS COMPARATOR A COMPARATOR B COMPARATOR C COMPARATOR D

TRIG MATCH0 MATCH1 MATCH2 MATCH3

READ TRACE DATA (DBG READ DATA BUS)

STATE SEQUENCER AND
EVENT CONTROL

BREAKPOINT REQUESTS

TRACE CONTROL TRIGGER

TRACE BUFFER

PROFILE OUTPUT

Figure 6-1. Debug Module Block Diagram
6.2 External Signal Description

6.2.1 External Event Input
The DBG module features an external event input signal, DBGEEV. The mapping of this signal to a device pin is specified in the device specific documentation. This function can be enabled and configured by the EEVE field in the DBGC1 control register. This signal is input only and allows an external event to force a state sequencer transition, or trace buffer entry, or to gate trace buffer entries. With the external event function enabled, a falling edge at the external event pin constitutes an event. Rising edges have no effect. If configured for gating trace buffer entries, then a low level at the pin allows entries, but a high level suppresses entries. The maximum frequency of events is half the internal core bus frequency. The function is explained in the EEVE field description.
NOTE
Due to input pin synchronization circuitry, the DBG module sees external events 2 bus cycles after they occur at the pin. Thus an external event occurring less than 2 bus cycles before arming the DBG module is perceived to occur whilst the DBG is armed.
When the device is in stop mode the synchronizer clocks are disabled and the external events are ignored.

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6.2.2 Profiling Output
The DBG module features a profiling data output signal PDO. The mapping of this signal to a device pin is specified in the device specific documentation. The device pin is enabled for profiling by setting the PDOE bit. The profiling function can be enabled by the PROFILE bit in the DBGTCRL control register. This signal is output only and provides a serial, encoded data stream that can be used by external development tools to reconstruct the internal CPU code flow, as specified in Section 6.4.6. During code profiling the device PDOCLK output is used as a clock signal.
6.3 Memory Map and Registers

6.3.1 Module Memory Map
A summary of the registers associated with the DBG module is shown in Figure 6-2. Detailed descriptions of the registers and bits are given in the subsections that follow.

Address 0x0100

Name

DBGC1

R W

Bit 7 ARM

6
0 TRIG

5 reserved

4 BDMBP

0x0101

DBGC2

R W

0

0

0

0

0x0102

DBGTCRH

R W

reserved

TSOURCE

TRANGE

0x0103

DBGTCRL

R W

0

0

0

PREND

0x0104

DBGTB

R W

Bit 15

Bit 14

Bit 13

Bit 12

0x0105

DBGTB

R W

Bit 7

Bit 6

Bit 5

Bit 4

0x0106

DBGCNT

R W

0

0x0107

DBGSCR1

R W

C3SC1

C3SC0

C2SC1

C2SC0

0x0108

DBGSCR2

R W

C3SC1

C3SC0

C2SC1

C2SC0

0x0109

DBGSCR3

R W

C3SC1

C3SC0

C2SC1

C2SC0

0x010A

DBGEFR

R PTBOVF W

TRIGF

0

EEVF

0x010B

DBGSR

R W

TBF

0

0

PTACT

3

2

BRKCPU reserved

CDCM

TRCMOD

DSTAMP PDOE

Bit 11

Bit 10

Bit 3

Bit 2

CNT

C1SC1 C1SC0

C1SC1 C1SC0

C1SC1 ME3

C1SC0 ME2

0

SSF2

1

Bit 0

EEVE

ABCM

TALIGN

PROFILE STAMP

Bit 9

Bit 8

Bit 1

Bit 0

C0SC1 C0SC0

C0SC1 C0SC0

C0SC1 ME1

C0SC0 ME0

SSF1

SSF0

Figure 6-2. Quick Reference to DBG Registers

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Address
0x010C0x010F

Name

Reserved

R W

0x0110

DBGACTL

R W

0x01110x0114

Reserved

R W

0x0115

DBGAAH

R W

0x0116

DBGAAM

R W

0x0117

DBGAAL

R W

0x0118

DBGAD0

R W

0x0119

DBGAD1

R W

0x011A

DBGAD2

R W

0x011B

DBGAD3

R W

0x011C

DBGADM0

R W

0x011D

DBGADM1

R W

0x011E

DBGADM2

R W

0x011F

DBGADM3

R W

0x0120

DBGBCTL

R W

0x01210x0124

Reserved

R W

0x0125

DBGBAH

R W

0x0126

DBGBAM

R W

0x0127

DBGBAL

R W

Bit 7

6

5

4

0

0

0

0

0

NDB

INST

0

0

0

0

0

3

2

0

0

RW

RWE

0

0

DBGAA[23:16]

DBGAA[15:8]

DBGAA[7:0]

Bit 31

30

29

28

27

26

Bit 23

22

21

20

19

18

Bit 15

14

13

12

11

10

Bit 7

6

5

4

3

2

Bit 31

30

29

28

27

26

Bit 23

22

21

20

19

18

Bit 15

14

13

12

11

10

Bit 7

6

5

4

0

0

INST

0

0

0

0

0

3

2

RW

RWE

0

0

DBGBA[23:16] DBGBA[15:8] DBGBA[7:0] Figure 6-2. Quick Reference to DBG Registers

1

Bit 0

0

0

reserved COMPE

0

0

25

Bit 24

17

Bit 16

9

Bit 8

1

Bit 0

25

Bit 24

17

Bit 16

9

Bit 8

1

Bit 0

reserved COMPE

0

0

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Address
0x01280x012F

Name

Reserved

R W

0x0130

DBGCCTL

R W

0x01310x0134

Reserved

R W

0x0135

DBGCAH

R W

0x0136

DBGCAM

R W

0x0137

DBGCAL

R W

0x0138

DBGCD0

R W

0x0139

DBGCD1

R W

0x013A

DBGCD2

R W

0x013B

DBGCD3

R W

0x013C

DBGCDM0

R W

0x013D

DBGCDM1

R W

0x013E

DBGCDM2

R W

0x013F

DBGCDM3

R W

Bit 7 0 0 0
Bit 31 Bit 23 Bit 15 Bit 7 Bit 31 Bit 23 Bit 15 Bit 7

6 0 NDB 0
30 22 14 6 30 22 14 6

5 0 INST 0
29 21 13 5 29 21 13 5

4

3

2

0

0

0

0

RW

RWE

0

0

0

DBGCA[23:16]

DBGCA[15:8]

DBGCA[7:0]

28

27

26

20

19

18

12

11

10

4

3

2

28

27

26

20

19

18

12

11

10

4

3

2

0x0140 0x01410x0144 0x0145
0x0146

DBGDCTL

R W

Reserved

R W

DBGDAH

R W

DBGDAM

R W

0

0

INST

0

RW

RWE

0

0

0

0

0

0

DBGDA[23:16] DBGDA[15:8] Figure 6-2. Quick Reference to DBG Registers

1

Bit 0

0

0

reserved COMPE

0

0

25

Bit 24

17

Bit 16

9

Bit 8

1

Bit 0

25

Bit 24

17

Bit 16

9

Bit 8

1

Bit 0

reserved COMPE

0

0

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Address Name

Bit 7

6

5

4

3

2

0x0147

DBGDAL

R W

DBGDA[7:0]

0x01480x017F

Reserved

R W

0

0

0

0

0

0

Figure 6-2. Quick Reference to DBG Registers

1

Bit 0

0

0

6.3.2 Register Descriptions
This section consists of the DBG register descriptions in address order. When ARM is set in DBGC1, the only bits in the DBG module registers that can be written are ARM, and TRIG

6.3.2.1 Debug Control Register 1 (DBGC1)

Address: 0x0100

0x0100 Reset

7
ARM 0

6
0 TRIG
0

5
reserved 0

4
BDMBP 0

3
BRKCPU 0

2
reserved 0

Figure 6-3. Debug Control Register (DBGC1)

1

0

EEVE

0

0

Read: Anytime

Write: Bit 7 Anytime with the exception that it cannot be set if PTACT is set. An ongoing profiling session must be finished before DBG can be armed again. Bit 6 can be written anytime but always reads back as 0. Bits 5:0 anytime DBG is not armed and PTACT is clear.

NOTE
On a write access to DBGC1 and simultaneous hardware disarm from an internal event, the hardware disarm has highest priority, clearing the ARM bit and generating a breakpoint, if enabled.

NOTE
When disarming the DBG by clearing ARM with software, the contents of bits[5:0] are not affected by the write, since up until the write operation, ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required.

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Table 6-4. DBGC1 Field Descriptions

Field 7
ARM
6 TRIG
4 BDMBP
3 BRKCPU
1­0 EEVE

Description
Arm Bit -- The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by register writes and is automatically cleared when the state sequencer returns to State0 on completing a debugging session. On setting this bit the state sequencer enters State1. 0 Debugger disarmed. No breakpoint is generated when clearing this bit by software register writes. 1 Debugger armed
Immediate Trigger Request Bit -- This bit when written to 1 requests an immediate transition to final state independent of comparator status. This bit always reads back a 0. Writing a 0 to this bit has no effect. 0 No effect. 1 Force state sequencer immediately to final state.
Background Debug Mode Enable -- This bit determines if a CPU breakpoint causes the system to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDC is not enabled, then no breakpoints are generated. 0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint. 1 Breakpoint to BDM, if BDC enabled. Otherwise no breakpoint.
CPU Breakpoint Enable -- The BRKCPU bit controls whether the debugger requests a breakpoint to CPU upon transitions to State0. If tracing is enabled, the breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is generated immediately. Please refer to Section 6.4.7 for further details. 0 Breakpoints disabled 1 Breakpoints enabled
External Event Enable -- The EEVE bits configure the external event function. Table 6-5 explains the bit encoding.

EEVE
00 01 10 11

Table 6-5. EEVE Bit Encoding
Description External event function disabled External event forces a trace buffer entry if tracing is enabled External event is mapped to the state sequencer, replacing comparator channel 3 External event pin gates trace buffer entries

6.3.2.2 Debug Control Register2 (DBGC2)

Address: 0x0101

7

R

0

W

Reset

0

6

5

4

3

2

0

0

0

CDCM

0

0

0

0

0

= Unimplemented or Reserved

Figure 6-4. Debug Control Register2 (DBGC2)

Read: Anytime.

Write: Anytime the module is disarmed and PTACT is clear.

This register configures the comparators for range matching.

1

0

ABCM

0

0

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Table 6-6. DBGC2 Field Descriptions

Field

Description

3­2

C and D Comparator Match Control -- These bits determine the C and D comparator match mapping as

CDCM[1:0] described in Table 6-7.

1­0

A and B Comparator Match Control -- These bits determine the A and B comparator match mapping as

ABCM[1:0] described in Table 6-8.

Table 6-7. CDCM Encoding

CDCM

Description

00

Match2 mapped to comparator C match....... Match3 mapped to comparator D match.

01

Match2 mapped to comparator C/D inside range....... Match3 disabled.

10

Match2 mapped to comparator C/D outside range....... Match3 disabled.

11

Reserved(1)

1. Currently defaults to Match2 mapped to inside range: Match3 disabled.

Table 6-8. ABCM Encoding

ABCM

Description

00

Match0 mapped to comparator A match....... Match1 mapped to comparator B match.

01

Match0 mapped to comparator A/B inside range....... Match1 disabled.

10

Match0 mapped to comparator A/B outside range....... Match1 disabled.

11

Reserved(1)

1. Currently defaults to Match0 mapped to inside range: Match1 disabled

6.3.2.3 Debug Trace Control Register High (DBGTCRH)

Address: 0x0102

R W Reset

7
reserved 0

6
TSOURCE

5

4

TRANGE

3

2

TRCMOD

0

0

0

0

0

Figure 6-5. Debug Trace Control Register (DBGTCRH)

1

0

TALIGN

0

0

Read: Anytime.

Write: Anytime the module is disarmed and PTACT is clear.

WARNING DBGTCR[7] is reserved. Setting this bit maps the tracing to an unimplemented bus, thus
preventing proper operation.

This register configures the trace buffer for tracing and profiling.

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Table 6-9. DBGTCRH Field Descriptions

Field

Description

6

Trace Control Bits -- The TSOURCE enables the tracing session.

TSOURCE 0 No CPU tracing/profiling selected

1 CPU tracing/profiling selected

5­4 TRANGE

Trace Range Bits -- The TRANGE bits allow filtering of trace information from a selected address range when tracing from the CPU in Detail mode. These bits have no effect in other tracing modes. To use a comparator for range filtering, the corresponding COMPE bit must remain cleared. If the COMPE bit is set then the comparator is used to generate events and the TRANGE bits have no effect. See Table 6-10 for range boundary definition.

3­2 TRCMOD

Trace Mode Bits -- See Section 6.4.5.2 for detailed Trace Mode descriptions. In Normal Mode, change of flow information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. See Table 6-11.

1­0

Trigger Align Bits -- These bits control whether the trigger is aligned to the beginning, end or the middle of a

TALIGN tracing or profiling session. See Table 6-12.

TRANGE
00 01 10 11

Table 6-10. TRANGE Trace Range Encoding
Tracing Range Trace from all addresses (No filter) Trace only in address range from $00000 to Comparator D Trace only in address range from Comparator C to $FFFFFF Trace only in range from Comparator C to Comparator D

Table 6-11. TRCMOD Trace Mode Bit Encoding

TRCMOD
00 01 10 11

Description
Normal Loop1 Detail Pure PC

Table 6-12. TALIGN Trace Alignment Encoding

TALIGN
00 01 10 11(1) 1. Tracing/Profiling disabled.

Description
Trigger ends data trace Trigger starts data trace 32 lines of data trace follow trigger
Reserved

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6.3.2.4 Debug Trace Control Register Low (DBGTCRL)

Address: 0x0103

7

R

0

W

Reset

0

6

5

4

3

2

1

0

0

PREND

DSTAMP

PDOE

PROFILE

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 6-6. Debug Trace Control Register Low (DBGTCRL)

Read: Anytime.

Write: Anytime the module is disarmed and PTACT is clear.

This register configures the profiling and timestamp features

Table 6-13. DBGTCRL Field Descriptions

0
STAMP 0

Field 4
PREND
3 DSTAMP
2 PDOE
1 PROFILE
0 STAMP

Description
Profiling End -- This bit, when set, forces the profiling session to end when the trace buffer has been filled. This prevents a rollover of the trace buffer from overwriting the initial entry containing the start address 0 Trace buffer rollover is enabled during profiling. After the last line has been filled, the entries continue, starting
at line0 and overwriting the older data 1 Trace buffer rollover is disabled during profiling. When the trace buffer is full, the profilling session ends, the
PTBOVF bit is set and the ARM bit is cleared.
Comparator D Timestamp Enable -- This bit, when set, enables Comparator D matches to generate timestamps in Detail, Normal and Loop1 trace modes. 0 Comparator D match does not generate timestamp 1 Comparator D match generates timestamp if timestamp function is enabled
Profile Data Out Enable -- This bit, when set, configures the device profiling pins for profiling. 0 Device pins not configured for profiling 1 Device pins configured for profiling
Profile Enable -- This bit, when set, enables the profile function, whereby a subsequent arming of the DBG activates profiling. When PROFILE is set, the TRCMOD bits are ignored. 0 Profile function disabled 1 Profile function enabled
Timestamp Enable -- This bit, when set, enables the timestamp function. The timestamp function adds a timestamp to each trace buffer entry in Detail, Normal and Loop1 trace modes. 0 Timestamp function disabled 1 Timestamp function enabled

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6.3.2.5 Debug Trace Buffer Register (DBGTB)

Address: 0x0104, 0x0105

15

14

13

12

11

10

R W

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

POR X

X

X

X

X

X

Other Resets

--

--

--

--

--

--

9
Bit 9 X --

8
Bit 8 X --

7
Bit 7 X --

6
Bit 6 X --

5
Bit 5 X --

4
Bit 4 X --

Figure 6-7. Debug Trace Buffer Register (DBGTB)

3
Bit 3 X --

2
Bit 2 X --

1
Bit 1 X --

0
Bit 0 X --

Read: Only when unlocked AND not armed and the TSOURCE bit is set, otherwise an error code (0xEE) is returned. Only aligned word read operations are supported. Misaligned word reads or byte reads return the error code 0xEE for each byte.

Write: Aligned word writes when the DBG is disarmed and the PTACT is clear unlock the trace buffer for reading but do not affect trace buffer contents.

Table 6-14. DBGTB Field Descriptions

Field
15­0 Bit[15:0]

Description
Trace Buffer Data Bits -- The Trace Buffer Register is a window through which the lines of the trace buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer which points to the next address to be read. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when the module is disarmed. The DBGTB register can be read only as an aligned word. Byte reads or misaligned access of these registers returns 0xEE and does not increment the trace buffer pointer. Similarly word reads while the debugger is armed or trace buffer is locked return 0xEEEE. The POR state is undefined Other resets do not affect the trace buffer contents.

6.3.2.6 Debug Count Register (DBGCNT)

Address: 0x0106

7

R

0

W

Reset

0

POR

0

6

5

4

3

2

1

0

CNT

--

--

--

--

--

--

--

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 6-8. Debug Count Register (DBGCNT)

Read: Anytime.

Write: Never.

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Table 6-15. DBGCNT Field Descriptions

Field
6­0 CNT[6:0]

Description
Count Value -- The CNT bits [6:0] indicate the number of valid data lines stored in the trace buffer. Table 6-16 shows the correlation between the CNT bits and the number of valid data lines in the trace buffer. When the CNT rolls over to zero, the TBF bit in DBGSR is set. Thereafter incrementing of CNT continues if configured for endalignment or mid-alignment. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. If a reset occurs during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace buffer.

TBF (DBGSR) 0 0 0
0 1 1

Table 6-16. CNT Decoding Table

CNT[6:0]
0000000 0000001 0000010 0000100 0000110
.. 1111100 1111110 0000000
0000010 ..
1111110

Description
No data valid
32 bits of one line valid
1 line valid 2 lines valid 3 lines valid
.. 62 lines valid
63 lines valid
64 lines valid; if using Begin trigger alignment, ARM bit is cleared and the tracing session ends.
64 lines valid, oldest data has been overwritten by most recent data

6.3.2.7 Debug State Control Register 1 (DBGSCR1)

Address: 0x0107

R W Reset

7
C3SC1 0

6
C3SC0

5
C2SC1

4
C2SC0

3
C1SC1

2
C1SC0

0

0

0

0

0

Figure 6-9. Debug State Control Register 1 (DBGSCR1)

1
C0SC1 0

0
C0SC0 0

Read: Anytime.

Write: If DBG is not armed and PTACT is clear.

The state control register 1 selects the targeted next state whilst in State1. The matches refer to the outputs of the comparator match control logic as depicted in Figure 6-1 and described in Section 6.3.2.12". Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register.

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Table 6-17. DBGSCR1 Field Descriptions

Field

Description

1­0

Channel 0 State Control.

C0SC[1:0] These bits select the targeted next state whilst in State1 following a match0.

3­2 C1SC[1:0]
5­4 C2SC[1:0]
7­6 C3SC[1:0]

Channel 1 State Control. These bits select the targeted next state whilst in State1 following a match1.
Channel 2 State Control. These bits select the targeted next state whilst in State1 following a match2.
Channel 3 State Control. If EEVE !=10, these bits select the targeted next state whilst in State1 following a match3. If EEVE = 10, these bits select the targeted next state whilst in State1 following an external event.

Table 6-18. State1 Match State Sequencer Transitions

CxSC[1:0]

Function

00

Match has no effect

01

Match forces sequencer to State2

10

Match forces sequencer to State3

11

Match forces sequencer to Final State

In the case of simultaneous matches, the match on the higher channel number (3...0) has priority.

6.3.2.8 Debug State Control Register 2 (DBGSCR2)

Address: 0x0108

R W Reset

7
C3SC1 0

6
C3SC0

5
C2SC1

4
C2SC0

3
C1SC1

2
C1SC0

0

0

0

0

0

Figure 6-10. Debug State Control Register 2 (DBGSCR2)

1
C0SC1 0

0
C0SC0 0

Read: Anytime.

Write: If DBG is not armed and PTACT is clear.

The state control register 2 selects the targeted next state whilst in State2. The matches refer to the outputs of the comparator match control logic as depicted in Figure 6-1 and described in Section 6.3.2.12". Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register.

Table 6-19. DBGSCR2 Field Descriptions

Field

Description

1­0

Channel 0 State Control.

C0SC[1:0] These bits select the targeted next state whilst in State2 following a match0.

3­2

Channel 1 State Control.

C1SC[1:0] These bits select the targeted next state whilst in State2 following a match1.

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Table 6-19. DBGSCR2 Field Descriptions (continued)

Field

Description

5­4 C2SC[1:0]
7­6 C3SC[1:0]

Channel 2 State Control. These bits select the targeted next state whilst in State2 following a match2.
Channel 3 State Control. If EEVE !=10, these bits select the targeted next state whilst in State2 following a match3. If EEVE =10, these bits select the targeted next state whilst in State2 following an external event.

Table 6-20. State2 Match State Sequencer Transitions

CxSC[1:0]

Function

00

Match has no effect

01

Match forces sequencer to State1

10

Match forces sequencer to State3

11

Match forces sequencer to Final State

In the case of simultaneous matches, the match on the higher channel number (3...0) has priority.

6.3.2.9 Debug State Control Register 3 (DBGSCR3)

Address: 0x0109

R W Reset

7
C3SC1 0

6
C3SC0

5
C2SC1

4
C2SC0

3
C1SC1

2
C1SC0

0

0

0

0

0

Figure 6-11. Debug State Control Register 3 (DBGSCR3)

1
C0SC1 0

0
C0SC0 0

Read: Anytime.

Write: If DBG is not armed and PTACT is clear.

The state control register three selects the targeted next state whilst in State3. The matches refer to the outputs of the comparator match control logic as depicted in Figure 6-1 and described in Section 6.3.2.12". Comparators must be enabled by setting the comparator enable bit in the associated DBGxCTL control register.

Table 6-21. DBGSCR3 Field Descriptions

Field

Description

1­0

Channel 0 State Control.

C0SC[1:0] These bits select the targeted next state whilst in State3 following a match0.

3­2 C1SC[1:0]
5­4 C2SC[1:0]

Channel 1 State Control. These bits select the targeted next state whilst in State3 following a match1.
Channel 2 State Control. These bits select the targeted next state whilst in State3 following a match2.

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Table 6-21. DBGSCR3 Field Descriptions (continued)

Field

Description

7­6

Channel 3 State Control.

C3SC[1:0] If EEVE !=10, these bits select the targeted next state whilst in State3 following a match3.

If EEVE =10, these bits select the targeted next state whilst in State3 following an external event.

Table 6-22. State3 Match State Sequencer Transitions

CxSC[1:0]
00 01 10 11

Function
Match has no effect Match forces sequencer to State1 Match forces sequencer to State2 Match forces sequencer to Final State

In the case of simultaneous matches, the match on the higher channel number (3....0) has priority.

6.3.2.10 Debug Event Flag Register (DBGEFR)

Address: 0x010A

7

6

5

R PTBOVF

TRIGF

0

W

4
EEVF

3
ME3

2
ME2

1
ME1

Reset

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 6-12. Debug Event Flag Register (DBGEFR)

0
ME0
0

Read: Anytime.

Write: Never

DBGEFR contains flag bits each mapped to events whilst armed. Should an event occur, then the corresponding flag is set. With the exception of TRIGF, the bits can only be set when the ARM bit is set. The TRIGF bit is set if a TRIG event occurs when ARM is already set, or if the TRIG event occurs simultaneous to setting the ARM bit.All other flags can only be cleared by arming the DBG module. Thus the contents are retained after a debug session for evaluation purposes.

A set flag does not inhibit the setting of other flags.

Table 6-23. DBGEFR Field Descriptions

Field 7
PTBOVF
6 TRIGF

Description
Profiling Trace Buffer Overflow Flag -- Indicates the occurrence of a trace buffer overflow event during a profiling session. 0 No trace buffer overflow event 1 Trace buffer overflow event
TRIG Flag -- Indicates the occurrence of a TRIG event during the debug session. 0 No TRIG event 1 TRIG event

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Table 6-23. DBGEFR Field Descriptions

Field 4
EEVF
3­0 ME[3:0]

Description
External Event Flag -- Indicates the occurrence of an external event during the debug session. 0 No external event 1 External event
Match Event[3:0]-- Indicates a comparator match event on the corresponding comparator channel.

6.3.2.11 Debug Status Register (DBGSR)

Address: 0x010B

7

R

TBF

W

Reset

--

POR

0

Read: Anytime. Write: Never.

6

5

4

3

2

0

0

PTACT

0

SSF2

0

0

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 6-13. Debug Status Register (DBGSR)

1
SSF1
0 0

0
SSF0
0 0

Table 6-24. DBGSR Field Descriptions

Field 7
TBF
4 PTACT
2­0 SSF[2:0]

Description
Trace Buffer Full -- The TBF bit indicates that the trace buffer has been filled with data since it was last armed. If this bit is set, then all trace buffer lines contain valid data, regardless of the value of DBGCNT bits CNT[6:0]. The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit
Profiling Transmission Active -- The PTACT bit, when set, indicates that the profiling transmission is still active. When clear, PTACT then profiling transmission is not active. The PTACT bit is set when profiling begins with the first PTS format entry to the trace buffer. The PTACT bit is cleared when the profiling transmission ends.
State Sequencer Flag Bits -- The SSF bits indicate the current State Sequencer state. During a debug session on each transition to a new state these bits are updated. If the debug session is ended by software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer before disarming. If a debug session is ended by an internal event, then the state sequencer returns to State0 and these bits are cleared to indicate that State0 was entered during the session. On arming the module the state sequencer enters State1 and these bits are forced to SSF[2:0] = 001. See Table 6-25.

Table 6-25. SSF[2:0] -- State Sequence Flag Bit Encoding

SSF[2:0]
000 001 010 011

Current State
State0 (disarmed) State1 State2 State3

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Table 6-25. SSF[2:0] -- State Sequence Flag Bit Encoding

SSF[2:0] 100
101,110,111

Current State Final State Reserved

6.3.2.12 Debug Comparator A Control Register (DBGACTL)

Address: 0x0110

7

R

0

W

Reset

0

6

5

4

NDB

INST

0

3

2

RW

RWE

0

0

0

0

0

= Unimplemented or Reserved

Figure 6-14. Debug Comparator A Control Register

1
reserved 0

0
COMPE 0

Read: Anytime. Write: If DBG not armed and PTACT is clear.
Table 6-26. DBGACTL Field Descriptions

Field 6
NDB
5 INST
3 RW
2 RWE
0 COMPE

Description
Not Data Bus -- The NDB bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. This bit is ignored if the INST bit in the same register is set. 0 Match on data bus equivalence to comparator register contents 1 Match on data bus difference to comparator register contents
Instruction Select -- This bit configures the comparator to compare PC or data access addresses. 0 Comparator compares addresses of data accesses 1 Comparator compares PC address
Read/Write Comparator Value Bit -- The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is ignored if RWE is clear or INST is set. 0 Write cycle is matched 1 Read cycle is matched
Read/Write Enable Bit -- The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is ignored when INST is set. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison
Enable Bit -- Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled

Table 6-27 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, because matches based on opcodes reaching the execution stage are data independent.

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Table 6-27. Read or Write Comparison Logic Table

RWE Bit
0 0 1 1 1 1

RW Bit
x x 0 0 1 1

RW Signal
0 1 0 1 0 1

Comment
RW not used in comparison RW not used in comparison
Write match No match No match
Read match

6.3.2.13 Debug Comparator A Address Register (DBGAAH, DBGAAM, DBGAAL)

Address: 0x0115, DBGAAH

23

22

21

20

19

18

17

16

R W

DBGAA[23:16]

Reset

0

0

0

0

0

0

0

0

Address: 0x0116, DBGAAM

15

14

13

12

11

10

9

8

R W

DBGAA[15:8]

Reset

0

0

0

0

0

0

0

0

Address: 0x0117, DBGAAL

7

6

5

4

3

2

1

0

R W

DBGAA[7:0]

Reset

0

0

0

0

0

0

0

0

Figure 6-15. Debug Comparator A Address Register

Read: Anytime.

Write: If DBG not armed and PTACT is clear.

Table 6-28. DBGAAH, DBGAAM, DBGAAL Field Descriptions

Field
23­16 DBGAA [23:16]
15­0 DBGAA [15:0]

Description
Comparator Address Bits [23:16]-- These comparator address bits control whether the comparator compares the address bus bits [23:16] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one
Comparator Address Bits [15:0]-- These comparator address bits control whether the comparator compares the address bus bits [15:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one

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6.3.2.14 Debug Comparator A Data Register (DBGAD)

Address: 0x0118, 0x0119, 0x011A, 0x011B

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R W

Bit 31

Bit 30

Bit 29

Bit 28

Bit 27

Bit 26

Bit 25

Bit 24

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

Reset 0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

15

14

13

12

11

10

R W

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Reset 0

0

0

0

0

0

9
Bit 9 0

8
Bit 8 0

7
Bit 7 0

6
Bit 6 0

5
Bit 5 0

4
Bit 4 0

3
Bit 3 0

Figure 6-16. Debug Comparator A Data Register (DBGAD)

2
Bit 2 0

1
Bit 1 0

0
Bit 0 0

Read: Anytime.

Write: If DBG not armed and PTACT is clear.

This register can be accessed with a byte resolution, whereby DBGAD0, DBGAD1, DBGAD2, DBGAD3 map to DBGAD[31:0] respectively.

Table 6-29. DBGAD Field Descriptions

Field

Description

31­16 Bits[31:16] (DBGAD0, DBGAD1)

Comparator Data Bits -- These bits control whether the comparator compares the data bus bits to a logic one or logic zero. The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one

15­0 Bits[15:0] (DBGAD2, DBGAD3)

Comparator Data Bits -- These bits control whether the comparator compares the data bus bits to a logic one or logic zero. The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one

6.3.2.15 Debug Comparator A Data Mask Register (DBGADM)

Address: 0x011C, 0x011D, 0x011E, 0x011F

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R W

Bit 31

Bit 30

Bit 29

Bit 28

Bit 27

Bit 26

Bit 25

Bit 24

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

Reset 0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

15

14

13

12

11

10

R W

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Reset 0

0

0

0

0

0

9
Bit 9 0

8
Bit 8 0

7
Bit 7 0

6
Bit 6 0

5
Bit 5 0

4
Bit 4 0

3
Bit 3 0

Figure 6-17. Debug Comparator A Data Mask Register (DBGADM)

2
Bit 2 0

1
Bit 1 0

0
Bit 0 0

Read: Anytime.

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Write: If DBG not armed and PTACT is clear. This register can be accessed with a byte resolution, whereby DBGADM0, DBGADM1, DBGADM2, DBGADM3 map to DBGADM[31:0] respectively.

Table 6-30. DBGADM Field Descriptions

Field

Description

31­16 Comparator Data Mask Bits -- These bits control whether the comparator compares the data bus bits to the Bits[31:16] corresponding comparator data compare bits. (DBGADM0, 0 Do not compare corresponding data bit DBGADM1) 1 Compare corresponding data bit

15-0

Comparator Data Mask Bits -- These bits control whether the comparator compares the data bus bits to the

Bits[15:0] corresponding comparator data compare bits.

(DBGADM2, 0 Do not compare corresponding data bit

DBGADM3) 1 Compare corresponding data bit

6.3.2.16 Debug Comparator B Control Register (DBGBCTL)

Address: 0x0120

7

R

0

W

Reset

0

6

5

4

0

0

INST

3

2

RW

RWE

0

0

0

0

0

= Unimplemented or Reserved

Figure 6-18. Debug Comparator B Control Register

1
reserved 0

0
COMPE 0

Read: Anytime.

Write: If DBG not armed and PTACT is clear.
Table 6-31. DBGBCTL Field Descriptions

Field(1)

Description

5 INST

Instruction Select -- This bit configures the comparator to compare PC or data access addresses. 0 Comparator compares addresses of data accesses 1 Comparator compares PC address

3

Read/Write Comparator Value Bit -- The RW bit controls whether read or write is used in compare for the

RW

associated comparator. The RW bit is ignored if RWE is clear or INST is set.

0 Write cycle is matched

1 Read cycle is matched

2 RWE

Read/Write Enable Bit -- The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is ignored when INST is set. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison

0 COMPE

Enable Bit -- Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled

1. If the ABCM field selects range mode comparisons, then DBGACTL bits configure the comparison, DBGBCTL is ignored.

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Table 6-32 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, as matches based on instructions reaching the execution stage are data independent.

Table 6-32. Read or Write Comparison Logic Table

RWE Bit
0 0 1 1 1 1

RW Bit
x x 0 0 1 1

RW Signal
0 1 0 1 0 1

Comment
RW not used in comparison RW not used in comparison
Write match No match No match
Read match

6.3.2.17 Debug Comparator B Address Register (DBGBAH, DBGBAM, DBGBAL)

Address: 0x0125, DBGBAH

23

22

21

20

19

18

17

16

R W

DBGBA[23:16]

Reset

0

0

0

0

0

0

0

0

Address: 0x0126, DBGBAM

15

14

13

12

11

10

9

8

R W

DBGBA[15:8]

Reset

0

0

0

0

0

0

0

0

Address: 0x0127, DBGBAL

7

6

5

4

3

2

1

0

R DBGBA[7:0]
W

Reset

0

0

0

0

0

0

0

0

Figure 6-19. Debug Comparator B Address Register

Read: Anytime.

Write: If DBG not armed and PTACT is clear.

Table 6-33. DBGBAH, DBGBAM, DBGBAL Field Descriptions

Field
23­16 DBGBA [23:16]
15­0 DBGBA [15:0]

Description
Comparator Address Bits [23:16]-- These comparator address bits control whether the comparator compares the address bus bits [23:16] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one
Comparator Address Bits[15:0]-- These comparator address bits control whether the comparator compares the address bus bits [15:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one

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6.3.2.18 Debug Comparator C Control Register (DBGCCTL)

Address: 0x0130

7

R

0

W

Reset

0

6

5

4

NDB

INST

0

3

2

RW

RWE

0

0

0

0

0

= Unimplemented or Reserved

Figure 6-20. Debug Comparator C Control Register

1
reserved 0

0
COMPE 0

Read: Anytime. Write: If DBG not armed and PTACT is clear.
Table 6-34. DBGCCTL Field Descriptions

Field 6
NDB
5 INST
3 RW
2 RWE
0 COMPE

Description
Not Data Bus -- The NDB bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. This bit is ignored if the INST bit in the same register is set. 0 Match on data bus equivalence to comparator register contents 1 Match on data bus difference to comparator register contents
Instruction Select -- This bit configures the comparator to compare PC or data access addresses. 0 Comparator compares addresses of data accesses 1 Comparator compares PC address
Read/Write Comparator Value Bit -- The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is ignored if RWE is clear or INST is set. 0 Write cycle is matched 1 Read cycle is matched
Read/Write Enable Bit -- The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is not used if INST is set. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison
Enable Bit -- Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled

Table 6-35 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, because matches based on opcodes reaching the execution stage are data independent.

Table 6-35. Read or Write Comparison Logic Table

RWE Bit
0 0 1 1 1

RW Bit
x x 0 0 1

RW Signal
0 1 0 1 0

Comment
RW not used in comparison RW not used in comparison
Write match No match No match

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Table 6-35. Read or Write Comparison Logic Table

RWE Bit 1

RW Bit 1

RW Signal 1

Comment Read match

6.3.2.19 Debug Comparator C Address Register (DBGCAH, DBGCAM, DBGCAL)

Address: 0x0135, DBGCAH

23

22

21

20

19

18

17

16

R DBGCA[23:16]
W

Reset

0

0

0

0

0

0

0

0

Address: 0x0136, DBGCAM

15

14

13

12

11

10

9

8

R W

DBGCA[15:8]

Reset

0

0

0

0

0

0

0

0

Address: 0x0137, DBGCAL

7

6

5

4

3

2

1

0

R W

DBGCA[7:0]

Reset

0

0

0

0

0

0

0

0

Figure 6-21. Debug Comparator C Address Register

Read: Anytime.

Write: If DBG not armed and PTACT is clear.

Table 6-36. DBGCAH, DBGCAM, DBGCAL Field Descriptions

Field
23­16 DBGCA [23:16]
15­0 DBGCA
[15:0]

Description
Comparator Address Bits [23:16]-- These comparator address bits control whether the comparator compares the address bus bits [23:16] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one
Comparator Address Bits[15:0]-- These comparator address bits control whether the comparator compares the address bus bits [15:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one

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6.3.2.20 Debug Comparator C Data Register (DBGCD)

Address: 0x0138, 0x0139, 0x013A, 0x013B

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R W

Bit 31

Bit 30

Bit 29

Bit 28

Bit 27

Bit 26

Bit 25

Bit 24

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

Reset 0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

15

14

13

12

11

10

R W

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Reset 0

0

0

0

0

0

9
Bit 9 0

8
Bit 8 0

7
Bit 7 0

6
Bit 6 0

5
Bit 5 0

4
Bit 4 0

3
Bit 3 0

Figure 6-22. Debug Comparator C Data Register (DBGCD)

2
Bit 2 0

1
Bit 1 0

0
Bit 0 0

Read: Anytime.

Write: If DBG not armed and PTACT is clear.

This register can be accessed with a byte resolution, whereby DBGCD0, DBGCD1, DBGCD2, DBGCD3 map to DBGCD[31:0] respectively.

XGATE data accesses have a maximum width of 16-bits and are mapped to DBGCD[15:0].

Table 6-37. DBGCD Field Descriptions

Field

Description

31­16 Bits[31:16] (DBGCD0, DBGCD1)

Comparator Data Bits -- These bits control whether the comparator compares the data bus bits to a logic one or logic zero. The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one

15­0 Bits[15:0] (DBGCD2, DBGCD3)

Comparator Data Bits -- These bits control whether the comparator compares the data bus bits to a logic one or logic zero. The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one

6.3.2.21 Debug Comparator C Data Mask Register (DBGCDM)

Address: 0x013C, 0x013D, 0x013E, 0x013F

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
W

Reset 0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

15

14

13

12

11

10

R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
W

Reset 0

0

0

0

0

0

9
Bit 9 0

8
Bit 8 0

7
Bit 7 0

6
Bit 6 0

5
Bit 5 0

4
Bit 4 0

3
Bit 3 0

Figure 6-23. Debug Comparator C Data Mask Register (DBGCDM)

2
Bit 2 0

1
Bit 1 0

0
Bit 0 0

Read: Anytime.

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Write: If DBG not armed and PTACT is clear.
This register can be accessed with a byte resolution, whereby DBGCDM0, DBGCDM1, DBGCDM2, DBGCDM3 map to DBGCDM[31:0] respectively.
XGATE data accesses have a maximum width of 16-bits and are mapped to DBGCDM[15:0].

Table 6-38. DBGCDM Field Descriptions

Field

Description

31­16 Comparator Data Mask Bits -- These bits control whether the comparator compares the data bus bits to the Bits[31:16] corresponding comparator data compare bits. (DBGCDM0, 0 Do not compare corresponding data bit DBGCDM1) 1 Compare corresponding data bit
15­0 Comparator Data Mask Bits -- These bits control whether the comparator compares the data bus bits to the Bits[15:0] corresponding comparator data compare bits. (DBGCDM2, 0 Do not compare corresponding data bit DBGCDM3) 1 Compare corresponding data bit

6.3.2.22 Debug Comparator D Control Register (DBGDCTL)

Address: 0x0140

7

R

0

W

Reset

0

6

5

4

0

0

INST

3

2

RW

RWE

0

0

0

0

0

= Unimplemented or Reserved

Figure 6-24. Debug Comparator D Control Register

1
reserved 0

0
COMPE 0

Read: Anytime.

Write: If DBG not armed and PTACT is clear.

Table 6-39. DBGDCTL Field Descriptions

Field(1)

Description

5 INST
3 RW
2 RWE
0 COMPE

Instruction Select -- This bit configures the comparator to compare PC or data access addresses. 0 Comparator compares addresses of data accesses 1 Comparator compares PC address
Read/Write Comparator Value Bit -- The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is ignored if RWE is clear or INST is set. 0 Write cycle is matched 1 Read cycle is matched
Read/Write Enable Bit -- The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is ignored if INST is set. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison
Enable Bit -- Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled

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1. If the CDCM field selects range mode comparisons, then DBGCCTL bits configure the comparison, DBGDCTL is ignored.

Table 6-40 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, because matches based on opcodes reaching the execution stage are data independent.

Table 6-40. Read or Write Comparison Logic Table

RWE Bit
0 0 1 1 1 1

RW Bit
x x 0 0 1 1

RW Signal
0 1 0 1 0 1

Comment
RW not used in comparison RW not used in comparison
Write match No match No match
Read match

6.3.2.23 Debug Comparator D Address Register (DBGDAH, DBGDAM, DBGDAL)

Address: 0x0145, DBGDAH

23

22

21

20

19

18

17

16

R W

DBGDA[23:16]

Reset

0

0

0

0

0

0

0

0

Address: 0x0146, DBGDAM

15

14

13

12

11

10

9

8

R W

DBGDA[15:8]

Reset

0

0

0

0

0

0

0

0

Address: 0x0147, DBGDAL

7

6

5

4

3

2

1

0

R DBGDA[7:0]
W

Reset

0

0

0

0

0

0

0

0

Figure 6-25. Debug Comparator D Address Register

Read: Anytime.

Write: If DBG not armed and PTACT is clear.

Table 6-41. DBGDAH, DBGDAM, DBGDAL Field Descriptions

Field
23­16 DBGDA [23:16]

Description
Comparator Address Bits [23:16]-- These comparator address bits control whether the comparator compares the address bus bits [23:16] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one

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Table 6-41. DBGDAH, DBGDAM, DBGDAL Field Descriptions

Field
15­0 DBGDA
[15:0]

Description
Comparator Address Bits[15:0]-- These comparator address bits control whether the comparator compares the address bus bits [15:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one

6.4 Functional Description
This section provides a complete functional description of the DBG module.
6.4.1 DBG Operation
The DBG module operation is enabled by setting ARM in DBGC1. When armed it supports storing of data in the trace buffer and can be used to generate breakpoints to the CPU. The DBG module is made up of comparators, control logic, the trace buffer, and the state sequencer, Figure 6-1.
The comparators monitor the bus activity of the CPU. Comparators can be configured to monitor opcode addresses (effectively the PC address) or data accesses. Comparators can be configured during data accesses to mask out individual data bus bits and to use R/W access qualification in the comparison. Comparators can be configured to monitor a range of addresses.
When configured for data access comparisons, the match is generated if the address (and optionally data) of a data access matches the comparator value.
Configured for monitoring opcode addresses, the match is generated when the associated opcode reaches the execution stage of the instruction queue, but before execution of that opcode.
When a match with a comparator register value occurs, the associated control logic can force the state sequencer to another state (see Figure 6-26).
The state sequencer can transition freely between the states 1, 2 and 3. On transition to Final State bus tracing can be triggered. On completion of tracing the state sequencer enters State0. If tracing is disabled or End aligned tracing is enabled then the state sequencer transitions immediately from Final State to State0. The transition to State0 generates breakpoints if breakpoints are enabled.
Independent of the comparators, state sequencer transitions can be forced by the external event input or by writing to the TRIG bit in the DBGC1 control register.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads.
6.4.2 Comparator Modes
The DBG contains four comparators, A, B, C, and D. Each comparator compares the address stored in DBGXAH, DBGXAM, and DBGXAL with the PC (opcode addresses) or selected address bus (data

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accesses). Furthermore, comparators A and C can compare the data buses to values stored in DBGXD3-0 and allow data bit masking.
The comparators can monitor the buses for an exact address or an address range. The comparator configuration is controlled by the control register contents and the range control by the DBGC2 contents.
The comparator control register also allows the type of data access to be included in the comparison through the use of the RWE and RW bits. The RWE bit controls whether the access type is compared for the associated comparator and the RW bit selects either a read or write access for a valid match.
The INST bit in each comparator control register is used to determine the matching condition. By setting INST, the comparator matches opcode addresses, whereby the databus, data mask, RW and RWE bits are ignored. The comparator register must be loaded with the exact opcode address.
The comparator can be configured to match memory access addresses by clearing the INST bit.
Each comparator match can force a transition to another state sequencer state (see Section 6.4.3").
Once a successful comparator match has occurred, the condition that caused the original match is not verified again on subsequent matches. Thus if a particular data value is matched at a given address, this address may not contain that data value when a subsequent match occurs.
Comparators C and D can also be used to select an address range to trace from, when tracing CPU accesses in Detail mode. This is determined by the TRANGE bits in the DBGTCRH register. The TRANGE encoding is shown in Table 6-10. If the TRANGE bits select a range definition using comparator D and the COMPE bit is clear, then comparator D is configured for trace range definition. By setting the COMPE bit the comparator is configured for address bus comparisons, the TRANGE bits are ignored and the tracing range function is disabled. Similarly if the TRANGE bits select a range definition using comparator C and the COMPE bit is clear, then comparator C is configured for trace range definition.
Match[0, 1, 2, 3] map directly to Comparators [A, B, C, D] respectively, except in range modes (see Section 6.3.2.2"). Comparator priority rules are described in the event priority section (Section 6.4.3.5").

6.4.2.1 Exact Address Comparator Match

With range comparisons disabled, the match condition is an exact equivalence of address bus with the value stored in the comparator address registers. Qualification of the type of access (R/W) is also possible.

Code may contain various access forms of the same address, for example a 16-bit access of ADDR[n] or byte access of ADDR[n+1] both access n+1. The comparators ensure that any access of the address defined by the comparator address register generates a match, as shown in the example of Table 6-42. Thus if the comparator address register contains ADDR[n+1] any access of ADDR[n+1] matches. This means that a 16-bit access of ADDR[n] or 32-bit access of ADDR[n-1] also match because they also access ADDR[n+1]. The right hand columns show the contents of DBGxA that would match for each access.
Table 6-42. Comparator Address Bus Matches

Access Address

32-bit 16-bit 16-bit

ADDR[n] ADDR[n] ADDR[n+1]

ADDR[n] Match Match
No Match

ADDR[n+1] Match Match Match

ADDR[n+2] Match
No Match Match

ADDR[n+3] Match
No Match No Match

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Table 6-42. Comparator Address Bus Matches

Access 8-bit

Address ADDR[n]

ADDR[n] Match

ADDR[n+1] No Match

ADDR[n+2] No Match

ADDR[n+3] No Match

If the comparator INST bit is set, the comparator address register contents are compared with the PC, the data register contents and access type bits are ignored. The comparator address register must be loaded with the address of the first opcode byte.

6.4.2.2 Address and Data Comparator Match

Comparators A and C feature data comparators, for data access comparisons. The comparators do not evaluate if accessed data is valid. Accesses across aligned 32-bit boundaries are split internally into consecutive accesses. The data comparator mapping to accessed addresses for the CPU is shown in Table 6-43, whereby the Address column refers to the lowest 2 bits of the lowest accessed address. This corresponds to the most significant data byte.
Table 6-43. Comparator Data Byte Alignment

Address[1:0]
00 01 10 11

Data Comparator
DBGxD0 DBGxD1 DBGxD2 DBGxD3

The fixed mapping of data comparator bytes to addresses within a 32-bit data field ensures data matches independent of access size. To compare a single data byte within the 32-bit field, the other bytes within that field must be masked using the corresponding data mask registers. This ensures that any access of that byte (32-bit,16-bit or 8-bit) with matching data causes a match. If no bytes are masked then the data comparator always compares all 32-bits and can only generate a match on a 32-bit access with correct 32bit data value. In this case, 8-bit or 16-bit accesses within the 32-bit field cannot generate a match even if the contents of the addressed bytes match because all 32-bits must match. In Table 6-44 the Access Address column refers to the address bits[1:0] of the lowest accessed address (most significant data byte).
Table 6-44. Data Register Use Dependency On CPU Access Type

Memory Address[2:0]

Case
1 2 3 4 5 6 7

Access Access Address Size

00

32-bit

01

32-bit

10

32-bit

11

32-bit

00

16-bit

01

16-bit

10

16-bit

000 DBGxD0
DBGxD0

001 DBGxD1 DBGxD1
DBGxD1 DBGxD1

010 DBGxD2 DBGxD2 DBGxD2
DBGxD2 DBGxD2

011 DBGxD3 DBGxD3 DBGxD3 DBGxD3
DBGxD3

100
DBGxD0 DBGxD0 DBGxD0

101
DBGxD1 DBGxD1

110 DBGxD2

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Memory Address[2:0]

Case

Access Access Address Size

000

001

010

011

100

101

110

8

11

16-bit

DBGxD3 DBGxD0

9

00

8-bit DBGxD0

10

01

8-bit

DBGxD1

11

10

8-bit

DBGxD2

12

11

8-bit

DBGxD3

13

00

8-bit

DBGxD0

Denotes byte that is not accessed.

For a match of a 32-bit access with data compare, the address comparator must be loaded with the address of the lowest accessed byte. For Case1 Table 6-44 this corresponds to 000, for Case2 it corresponds to 001. To compare all 32-bits, it is required that no bits are masked.

6.4.2.3 Data Bus Comparison NDB Dependency
The NDB control bit allows data bus comparators to be configured to either match on equivalence or on difference. This allows monitoring of a difference in the contents of an address location from an expected value.
When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by clearing the corresponding mask bit, so that it is ignored in the comparison. A match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register bits are clear, then a match is based on the address bus only, the data bus is ignored.
When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored and prevents a match because no difference can be detected. In this case address bus equivalence does not cause a match. Bytes that are not accessed are ignored. Thus when monitoring a multi byte field for a difference, partial accesses of the field only return a match if a difference is detected in the accessed bytes.

NDB
0 0 1 1

Table 6-45. NDB and MASK bit dependency

DBGADM
0 1 0 1

Comment
Do not compare data bus bit. Compare data bus bit. Match on equivalence.
Do not compare data bus bit. Compare data bus bit. Match on difference.

6.4.2.4 Range Comparisons
Range comparisons are accurate to byte boundaries. Thus for data access comparisons a match occurs if at least one byte of the access is in the range (inside range) or outside the range (outside range). For opcode comparisons only the address of the first opcode byte is compared with the range.

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When using the AB comparator pair for a range comparison, the data bus can be used for qualification by using the comparator A data and data mask registers. Similarly when using the CD comparator pair for a range comparison, the data bus can be used for qualification by using the comparator C data and data mask registers. The DBGACTL/DBGCCTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access. The corresponding DBGBCTL/DBGDCTL bits are ignored. The DBGACTL/DBGCCTL COMPE/INST bits are used for range comparisons. The DBGBCTL/DBGDCTL COMPE/INST bits are ignored in range modes.
6.4.2.4.1 Inside Range (CompAC_Addr  address  CompBD_Addr)
In the Inside Range comparator mode, either comparator pair A and B or comparator pair C and D can be configured for range comparisons by the control register (DBGC2). The match condition requires a simultaneous valid match for both comparators. A match condition on only one comparator is not valid.
6.4.2.4.2 Outside Range (address < CompAC_Addr or address > CompBD_Addr)
In the Outside Range comparator mode, either comparator pair A and B or comparator pair C and D can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. Outside range mode in combination with opcode address matches can be used to detect if opcodes are from an unexpected range.
NOTE When configured for data access matches, an outside range match would typically occur at any interrupt vector fetch or register access. This can be avoided by setting the upper or lower range limit to $FFFFFF or $000000 respectively. Interrupt vector fetches do not cause opcode address matches.
6.4.3 Events
Events are used as qualifiers for a state sequencer change of state. The state control register for the current state determines the next state for each event. An event can immediately initiate a transition to the next state sequencer state whereby the corresponding flag in DBGSR is set.
6.4.3.1 Comparator Match Events
6.4.3.1.1 Opcode Address Comparator Match
The comparator is loaded with the address of the selected instruction and the comparator control register INST bit is set. When the opcode reaches the execution stage of the instruction queue a match occurs just before the instruction executes, allowing a breakpoint immediately before the instruction boundary. The comparator address register must contain the address of the first opcode byte for the match to occur. Opcode address matches are data independent thus the RWE and RW bits are ignored. CPU compares are disabled when BDM becomes active.

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6.4.3.1.2 Data Access Comparator Match
Data access matches are generated when an access occurs at the address contained in the comparator address register. The match can be qualified by the access data and by the access type (read/write). The breakpoint occurs a maximum of 2 instructions after the access in the CPU flow. Note, if a COF occurs between access and breakpoint, the opcode address of the breakpoint can be elsewhere in the memory map.
Opcode fetches are not classed as data accesses. Thus data access matches are not possible on opcode fetches.

6.4.3.2 External Event
The DBGEEV input signal can force a state sequencer transition, independent of internal comparator matches. The DBGEEV is an input signal mapped directly to a device pin and configured by the EEVE field in DBGC1. The external events can change the state sequencer state, or force a trace buffer entry, or gate trace buffer entries.
If configured to change the state sequencer state, then the external match is mapped to DBGSCRx bits C3SC[1:0]. In this configuration, internal comparator channel3 is de-coupled from the state sequencer but can still be used for timestamps. The DBGEFR bit EEVF is set when an external event occurs.

6.4.3.3 Setting The TRIG Bit
Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing the TRIG bit in DBGC1 to a logic "1". This forces the state sequencer into the Final State. If configured for End aligned tracing or for no tracing, the transition to Final State is followed immediately by a transition to State0. If configured for Begin- or Mid Aligned tracing, the state sequencer remains in Final State until tracing is complete, then it transitions to State0.
Breakpoints, if enabled, are issued on the transition to State0.
6.4.3.4 Profiling Trace Buffer Overflow Event
During code profiling a trace buffer overflow forces the state sequencer into the disarmed State0 and, if breakpoints are enabled, issues a breakpoint request to the CPU.

6.4.3.5 Event Priorities

If simultaneous events occur, the priority is resolved according to Table 6-46. Lower priority events are suppressed. It is thus possible to miss a lower priority event if it occurs simultaneously with an event of a higher priority. The event priorities dictate that in the case of simultaneous matches, the match on the higher comparator channel number (3,2,1,0) has priority.
If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm from an internal event, then the ARM bit is cleared due to the hardware disarm.
Table 6-46. Event Priorities

Priority Highest

Source TB Overflow

Action Immediate force to state 0, generate breakpoint and terminate tracing

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TRIG DBGEEV Match3 Match2 Match1 Match0

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Table 6-46. Event Priorities
Force immediately to final state Force to next state as defined by state control registers (EEVE=2'b10)
Force to next state as defined by state control registers Force to next state as defined by state control registers Force to next state as defined by state control registers Force to next state as defined by state control registers

6.4.4 State Sequence Control

State 0 (Disarmed)

ARM = 1

State1

State2

Final State

State3

Figure 6-26. State Sequencer Diagram
The state sequencer allows a defined sequence of events to provide a breakpoint and/or a trigger point for tracing of data in the trace buffer. When the DBG module is armed by setting the ARM bit in the DBGC1 register, the state sequencer enters State1. Further transitions between the states are controlled by the state control registers and depend upon event occurrences (see Section 6.4.3). From Final State the only permitted transition is back to the disarmed State0. Transition between the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. If breakpoints are enabled, then an event based transition to State0 generates the breakpoint request. A transition to State0 resulting from writing "0" to the ARM bit does not generate a breakpoint request.
6.4.4.1 Final State
On entering Final State a trigger may be issued to the trace buffer according to the trigger position control as defined by the TALIGN field (see Section 6.3.2.3").
If tracing is enabled and either Begin or Mid aligned triggering is selected, the state sequencer remains in Final State until completion of the trace. On completion of the trace the state sequencer returns to State0 and the debug module is disarmed; if breakpoints are enabled, a breakpoint request is generated.
If tracing is disabled or End aligned triggering is selected, then when the Final State is reached the state sequencer returns to State0 immediately and the debug module is disarmed. If breakpoints are enabled, a breakpoint request is generated on transitions to State0.

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6.4.5 Trace Buffer Operation
The trace buffer is a 64 lines deep by 64-bits wide RAM array. If the TSOURCE bit is set the DBG module can store trace information in the RAM array in a circular buffer format. Data is stored in mode dependent formats, as described in the following sections. After each trace buffer entry, the counter register DBGCNT is incremented. Trace buffer rollover is possible when configured for End- or Mid-Aligned tracing, such that older entries are replaced by newer entries. Tracing of CPU activity is disabled when the BDC is active.
The RAM array can be accessed through the register DBGTB using 16-bit wide word accesses. After each read, the internal RAM pointer is incremented so that the next read will receive fresh information. Reading the trace buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not incremented.
In Detail mode the address range for CPU access tracing can be limited to a range specified by the TRANGE bits in DBGTCRH. This function uses comparators C and D to define an address range inside which accesses should be traced. Thus traced accesses can be restricted, for example, to particular register or RAM range accesses.
The external event pin can be configured to force trace buffer entries in Normal or Loop1 trace modes. All tracing modes support trace buffer gating. In Pure PC and Detail modes external events do not force trace buffer entries.
If the external event pin is configured to gate trace buffer entries then any trace mode is valid.

6.4.5.1 Trace Trigger Alignment
Using the TALIGN bits (see Section 6.3.2.3") it is possible to align the trigger with the end, the middle, or the beginning of a tracing session.
If End or Mid-Alignment is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered. The transition to Final State if End-Alignment is selected, ends the tracing session. The transition to Final State if Mid-Alignment is selected signals that another 32 lines are traced before ending the tracing session. Tracing with Begin-Alignment starts at the trigger and ends when the trace buffer is full.

TALIGN 00 01 10
11

Table 6-47. Tracing Alignment

Tracing Begin On arming At trigger On arming

Tracing End
At trigger When trace buffer is full When 32 trace buffer lines have been filled after trigger Reserved

6.4.5.1.1 Storing with Begin-Alignment
Storing with Begin-Alignment, data is not stored in the trace buffer until the Final State is entered. Once the trigger condition is met the DBG module remains armed until 64 lines are stored in the trace buffer.

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Using Begin-Alignment together with opcode address comparisons, if the instruction is about to be executed then the trace is started. If the trigger is at the address of a COF instruction, whilst tracing COF addresses, then that COF address is stored to the trace buffer. If breakpoints are enabled, the breakpoint is generated upon entry into State0 on completion of the tracing session; thus the breakpoint does not occur at the instruction boundary.
6.4.5.1.2 Storing with Mid-Alignment
Storing with Mid-Alignment, data is stored in the trace buffer as soon as the DBG module is armed. When the trigger condition is met, another 32 lines are traced before ending the tracing session, irrespective of the number of lines stored before the trigger occurred, then the DBG module is disarmed and no more data is stored. Using Mid-Alignment with opcode address triggers, if the instruction is about to be executed then the trace is continued for another 32 lines. If breakpoints are enabled, the breakpoint is generated upon entry into State0 on completion of the tracing session; thus the breakpoint does not occur at the instruction boundary. When configured for Compressed Pure-PC tracing, the MAT info bit is set to indicate the last PC entry before a trigger event.
6.4.5.1.3 Storing with End-Alignment
Storing with End-Alignment, data is stored in the trace buffer until the Final State is entered. Following this trigger, the DBG module immediately transitions to State0. If the trigger is at the address of a COF instruction the trigger event is not stored in the trace buffer.
6.4.5.2 Trace Modes
The DBG module can operate in four trace modes. The mode is selected using the TRCMOD bits in the DBGTCRH register. Normal, Loop1 and Detail modes can be configured to store a timestamp with each entry, by setting the STAMP bit. The modes are described in the following subsections.
In addition to the listed trace modes it is also possible to use code profiling to fill the trace buffer with a highly compressed COF format. This can be subsequently read out in the same fashion as the listed trace modes (see Section 6.4.6).
6.4.5.2.1 Normal Mode
In Normal Mode, change of flow (COF) program counter (PC) addresses are stored.
CPU COF addresses are defined as follows: · Source address of taken conditional branches (bit-conditional, and loop primitives) · Destination address of indexed JMP and JSR instruction.s · Destination address of RTI and RTS instructions. · Vector address of interrupts
BRA, BSR, BGND as well as non-indexed JMP and JSR instructions are not classified as change of flow and are not stored in the trace buffer.
COF addresses stored include the full address bus of CPU and an information byte, which contains bits to indicate whether the stored address was a source, destination or vector address.

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NOTE
When a CPU indexed jump instruction is executed, the destination address is stored to the trace buffer on instruction completion, indicating the COF has taken place. If an interrupt occurs simultaneously then the next instruction carried out is actually from the interrupt service routine. The instruction at the destination address of the original program flow gets executed after the interrupt service routine.
In the following example an IRQ interrupt occurs during execution of the indexed JMP at address MARK1. The NOP at the destination (SUB_1) is not executed until after the IRQ service routine but the destination address is entered into the trace buffer to indicate that the indexed JMP COF has taken place.

LD MARK1: JMP MARK2: NOP

X,#SUB_1 (0,X)

; IRQ interrupt occurs during execution of this ;

SUB_1: NOP
NOP ADDR1: DBNE

D0,PART5

; JMP Destination address TRACE BUFFER ENTRY 1 ; RTI Destination address TRACE BUFFER ENTRY 3 ; ; Source address TRACE BUFFER ENTRY 4

IRQ_ISR: LD

D1,#$F0

; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2

ST

D1,VAR_C1

RTI

;

The execution flow taking into account the IRQ is as follows

LD

X,#SUB_1

MARK1: JMP

(0,X)

;

IRQ_ISR: LD

D1,#$F0

;

ST

D1,VAR_C1

RTI

;

SUB_1: NOP

NOP

;

ADDR1: DBNE

D0,PART5

;

The Normal Mode trace buffer format is shown in the following tables. Whilst tracing in Normal or Loop1 modes each array line contains 2 data entries, thus in this case the DBGCNT[0] is incremented after each separate entry. Information byte bits indicate if an entry is a source, destination or vector address.

The external event input can force trace buffer entries independent of COF occurrences, in which case the EEVI bit is set and the PC value of the last instruction is stored to the trace buffer. If the external event coincides with a COF buffer entry a single entry is made with the EEVI bit set.

Normal mode profiling with timestamp is possible when tracing from a single source by setting the STAMP bit in DBGTCRL. This results in a different format (see Table 6-49).

Table 6-48. Normal and Loop1 Mode Trace Buffer Format without Timestamp

8-Byte Wide Trace Buffer Line

Mode

7

6

5

4

3

2

1

0

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Table 6-48. Normal and Loop1 Mode Trace Buffer Format without Timestamp

CINF1 CINF3

CPCH1 CPCH3

CPCM1 CPCM3

CPCL1 CPCL3

CINF0 CINF2

CPCH0 CPCH2

CPCM0 CPCM2

CPCL0 CPCL2

Mode CPU

Table 6-49. Normal and Loop1 Mode Trace Buffer Format with Timestamp

8-Byte Wide Trace Buffer Line

7

6

Timestamp Timestamp Timestamp Timestamp

5 Reserved Reserved

4 Reserved Reserved

3 CINF0 CINF1

2 CPCH0 CPCH1

1 CPCM0 CPCM1

0 CPCL0 CPCL1

CINF contains information relating to the CPU.

CPU Information Byte CINF For Normal And Loop1 Modes

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

CET

0

0

CTI

EEVI

0

Figure 6-27. CPU Information Byte CINF

Bit 0 TOVF

Field 7­6 CET
3 CTI
2 EEVI
0 TOVF

Table 6-50. CINF Bit Descriptions
Description
CPU Entry Type Field -- Indicates the type of stored address of the trace buffer entry as described in Table 6-51
Comparator Timestamp Indicator -- This bit indicates if the trace buffer entry corresponds to a comparator timestamp. 0 Trace buffer entry initiated by trace mode specification conditions or timestamp counter overflow 1 Trace buffer entry initiated by comparator D match
External Event Indicator -- This bit indicates if the trace buffer entry corresponds to an external event. 0 Trace buffer entry not initiated by an external event 1 Trace buffer entry initiated by an external event
Timestamp Overflow Indicator -- Indicates if the trace buffer entry corresponds to a timestamp overflow 0 Trace buffer entry not initiated by a timestamp overflow 1 Trace buffer entry initiated by a timestamp overflow

Table 6-51. CET Encoding

CET 00 01

Entry Type Description Non COF opcode address (entry forced by an external event) Vector destination address

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Table 6-51. CET Encoding

CET 10 11

Source address of COF opcode Destination address of COF opcode

Entry Type Description

6.4.5.2.2 Loop1 Mode
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it however allows the filtering out of redundant information.
The intent of Loop1 Mode is to prevent the trace buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction. The DBG monitors trace buffer entries and prevents consecutive duplicate address entries resulting from repeated branches.
Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these could indicate a bug in application code that the DBG module is designed to help find.
The trace buffer format for Loop1 Mode is the same as that of Normal Mode.

6.4.5.2.3 Detail Mode
When tracing CPU activity in Detail Mode, address and data of data and vector accesses are traced. The information byte indicates the size of access and the type of access (read or write).
ADRH, ADRM, ADRL denote address high, middle and low byte respectively. The numerical suffix indicates which tracing step. DBGCNT increments by 2 for each line completed.
If timestamps are enabled then each CPU entry can span 2 trace buffer lines, whereby the second line includes the timestamp. If a valid PC occurs in the same cycle as the timestamp, it is also stored to the trace buffer and the PC bit is set. The second line featuring the timestamp is only stored if no further data access occurs in the following cycle. This is shown in Table 6-53, where data accesses 2 and 3 occur in consecutive cycles, suppressing the entry2 timestamp. If 2 lines are used for an entry, then DBGCNT increments by 4. A timestamp line is indicated by bit1 in the TSINF byte. The timestamp counter is only reset each time a timestamp line entry is made. It is not reset when the data and address trace buffer line entry is made.

Mode
CPU Detail

Table 6-52. Detail Mode Trace Buffer Format without Timestamp

8-Byte Wide Trace Buffer Line

7

6

5

4

3

2

1

0

CDATA31 CDATA21 CDATA11 CDATA01 CDATA32 CDATA22 CDATA12 CDATA02

CINF1 CINF2

CADRH1 CADRH2

CADRM1 CADRM2

CADRL1 CADRL2

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Table 6-53. Detail Mode Trace Buffer Format with Timestamp

8-Byte Wide Trace Buffer Line

7

6

5

4

3

2

1

0

CDATA31 Timestamp CDATA32 CDATA33 Timestamp

CDATA21 Timestamp CDATA22 CDATA23 Timestamp

CDATA11 Reserved CDATA12 CDATA13 Reserved

CDATA01 Reserved CDATA02 CDATA03 Reserved

CINF1 TSINF1 CINF2 CINF3 TSINF3

CADRH1 CPCH1 CADRH2 CADRH3 CPCH3

CADRM1 CPCM1 CADRM2 CADRM3 CPCM3

CADRL1 CPCL1 CADRL2 CADRL3 CPCL3

Detail Mode data entries store the bytes aligned to the address of the MSB accessed (Byte1 Table 6-54). Thus accesses split across 32-bit boundaries are wrapped around.
Table 6-54. Detail Mode Data Byte Alignment

Access Address
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11

Access Size
32-bit 32-bit 32-bit 32-bit 24-bit 24-bit 24-bit 24-bit 16-bit 16-bit 16-bit 16-bit 8-bit 8-bit 8-bit 8-bit

CDATA31 Byte1 Byte4 Byte3 Byte2 Byte1
Byte3 Byte2 Byte1
Byte2 Byte1

CDATA21 CDATA11 CDATA01

Byte2 Byte1 Byte4 Byte3 Byte2 Byte1
Byte3 Byte2 Byte1

Byte3 Byte2 Byte1 Byte4 Byte3 Byte2 Byte1
Byte2 Byte1

Byte4 Byte3 Byte2 Byte1
Byte3 Byte2 Byte1
Byte2 Byte1

Byte1 Byte1 Byte1
Denotes byte that is not accessed.

Information Bytes

BYTE

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CINF

CSZ

CRW

0

TSINF

0

0

0

0

0

0

CTI

PC

0

0

1

TOVF

Figure 6-28. Information Bytes CINF and XINF

When tracing in Detail Mode, CINF provides information about the type of CPU access being made.

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TSINF provides information about a timestamp. Bit1 indicates if the byte is a TSINF byte.
Table 6-55. CINF Field Descriptions

Field 7­6 CSZ
5 CRW

Description
Access Type Indicator -- This field indicates the CPU access size. 00 8-bit Access 0116-bit Access 10 24-bit Access 11 32-bit Access
Read/Write Indicator -- Indicates if the corresponding stored address corresponds to a read or write access. 0 Write Access 1 Read Access

Field 3
CTI
2 PC
0 TOVF

Table 6-56. TSINF Field Descriptions
Description
Comparator Timestamp Indicator -- This bit indicates if the trace buffer entry corresponds to a comparator timestamp. 0 Trace buffer entry initiated by trace mode specification conditions or timestamp counter overflow 1 Trace buffer entry initiated by comparator D match
Program Counter Valid Indicator -- Indicates if the PC entry is valid on the timestamp line. 0 Trace buffer entry does not include PC value 1 Trace buffer entry includes PC value
Timestamp Overflow Indicator -- Indicates if the trace buffer entry corresponds to a timestamp overflow 0 Trace buffer entry not initiated by a timestamp overflow 1 Trace buffer entry initiated by a timestamp overflow

6.4.5.2.4 Pure PC Mode
In Pure PC Mode, the PC addresses of all opcodes loaded into the execution stage, including illegal opcodes, are stored.
Tracing from a single source, compression is implemented to increase the effective trace depth. A compressed entry consists of the lowest PC byte only. A full entry consists of all PC bytes. If the PC remains in the same 256 byte range, then a compressed entry is made, otherwise a full entry is made. The full entry is always the last entry of a record.
Each trace buffer line consists of 7 payload bytes, PLB0-6, containing full or compressed CPU PC addresses and 1 information byte to indicate the type of entry (compressed or base address) for each payload byte.
Each trace buffer line is filled from right to left. The final entry on each line is always a base address, used as a reference for the previous entries on the same line. Whilst tracing, a base address is typically stored

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in bytes[6:4], the other payload bytes may be compressed or complete addresses as indicated by the info byte bits.

Table 6-57. Pure PC Mode Trace Buffer Format Single Source

8-Byte Wide Trace Buffer Line

Mode

7

6

5

4

3

2

1

0

CPU

CXINF

BASE

BASE

BASE

PLB3

PLB2

PLB1

PLB0

If the info bit for byte3 indicates a full CPU PC address, whereby bytes[5:3] are used, then the info bit mapped to byte[4] is redundant and the byte[6] is unused because a line overflow has occurred. Similarly a base address stored in bytes[4:2] causes line overflow, so bytes[6:5] are unused.
CXINF[6:4] indicate how many bytes in a line contain valid data, since tracing may terminate before a complete line has been filled.
CXINF Information Byte Source Tracing

CXINF

7
MAT

6

5

4

PLEC

3

2

1

0

NB3 NB2 NB1 NB0

Figure 6-29. Pure PC Mode CXINF

Table 6-58. CXINF Field Descriptions

Field

Description

MAT
PLEC[2:0] NBx

Mid Aligned Trigger-- This bit indicates a mid aligned trigger position. When a mid aligned trigger occurs, the next trace buffer entry is a base address and the counter is incremented to a new line, independent of the number of bytes used on the current line. The MAT bit is set on the current line, to indicate the position of the trigger. When configured for begin or end aligned trigger, this bit has no meaning. NOTE: In the case when ARM and TRIG are simultaneously set together in the same cycle that a new PC value is registered, then this PC is stored to the same trace buffer line and MAT set. 0 Line filled without mid aligned trigger occurrence 1 Line last entry is the last PC entry before a mid aligned trigger
Payload Entry Count-- This field indicates the number of valid bytes in the trace buffer line Binary encoding is used to indicate up to 7 valid bytes.
Payload Compression Indicator-- This field indicates if the corresponding payload byte is the lowest byte of a base PC entry 0 Corresponding payload byte is a not the lowest byte of a base PC entry 1 Corresponding payload byte is the lowest byte of a base PC entry

Pure PC mode tracing does not support timestamps or external event entries.
6.4.5.3 Timestamp When set, the STAMP bit in DBGTCRL configures the DBG to add a timestamp to trace buffer entries in Normal, Loop1 and Detail trace buffer modes. The timestamp is generated from a 16-bit counter and is stored to the trace buffer line each time a trace buffer entry is made.

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The number of core clock cycles since the last entry equals the timestamp + 1. The core clock runs at twice the frequency of the bus clock. The timestamp of the first trace buffer entry is 0x0000. With timestamps enabled trace buffer entries are initiated in the following ways:
· according to the trace mode specification, for example COF PC addresses in Normal mode
· on a timestamp counter overflow If the timestamp counter reaches 0xFFFF then a trace buffer entry is made, with timestamp= 0xFFFF and the timestamp overflow bit TOVF is set.
· on a match of comparator D If STAMP and DSTAMP are set then comparator D is used for forcing trace buffer entries with timestamps. The state control register settings determine if comparator D is also used to trigger the state sequencer. Thus if the state control register configuration does not use comparator D, then it is used solely for the timestamp function. If comparator D initiates a timestamp then the CTI bit is set in the INFO byte. This can be used in Normal/Loop1 mode to indicate when a particular data access occurs relative to the PC flow. For example when the timing of an access may be unclear due to the use of indexes.

NOTE If comparator D is configured to match a PC address then associated timestamps trigger a trace buffer entry during execution of the previous instruction. Thus the PC stored to the trace buffer is that of the previous instruction.The comparator must contain the PC address of the instruction's first opcode byte
Timestamps are disabled in Pure PC mode.
6.4.5.4 Reading Data from Trace Buffer
The data stored in the trace buffer can be read using either the background debug controller (BDC) module or the CPU provided the DBG module is not armed and is configured for tracing by TSOURCE. When the ARM bit is set the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by an aligned word write to DBGTB when the module is disarmed. The trace buffer can only be read through the DBGTB register using aligned word reads. Reading the trace buffer while the DBG module is armed, or trace buffer locked returns 0xEE and no shifting of the RAM pointer occurs. Any byte or misaligned reads return 0xEE and do not cause the trace buffer pointer to increment to the next trace buffer address.
Reading the trace buffer is prevented by internal hardware whilst profiling is active because the RAM pointer is used to indicate the next row to be transmitted. Thus attempted reads of DBGTB do not return valid data when the PTACT bit is set. To initialize the pointer and read profiling data, the PTACT bit must be cleared and remain cleared.
The trace buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid 64-bit lines can be determined. DBGCNT does not decrement as data is read.
Whilst reading, an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0. The

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pointer is initialized by each aligned write to DBGTB to point to the oldest data again. This enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. After reading all trace buffer lines, the next read wraps around and returns the contents of line0.
The least significant word of each 64-bit wide array line is read out first. All bytes, including those containing invalid information are read out.
6.4.5.5 Trace Buffer Reset State
The trace buffer contents are not initialized by a system reset. Thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out. The DBGCNT bits are not cleared by a system reset. Thus should a reset occur, the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer is cleared by a system reset. It can be initialized by an aligned word write to DBGTB following a reset during debugging, so that it points to the oldest valid data again. Debugging occurrences of system resets is best handled using mid or end trigger alignment since the reset may occur before the trace trigger, which in the begin trigger alignment case means no information would be stored in the trace buffer.
6.4.6 Code Profiling
6.4.6.1 Code Profiling Overview
Code profiling supplies encoded COF information on the PDO pin and the reference clock on the PDOCLK pin. If the TSOURCE bit is set then code profiling is enabled by setting the PROFILE bit. The associated device pin is configured for code profiling by setting the PDOE bit. Once enabled, code profiling is activated by arming the DBG. During profiling, if PDOE is set, the PDO operates as an output pin at a half the internal bus frequency, driving both high and low.
Independent of PDOE status, profiling data is stored to the trace buffer and can be read out in the usual manner when the debug session ends and the PTACT bit has been cleared.
The external debugger uses both edges of the clock output to strobe the data on PDO. The first PDOCLK edge is used to sample the first data bit on PDO.

Figure 6-30. Profiling Output Interface

TBUF DBG MCU

PDOCLK PDO

CLOCK DATA
DEV TOOL

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Figure 6-31 shows the profiling clock, PDOCLK, whose edges are offset from the bus clock, to ease setup and hold time requirements relative to PDO, which is synchronous to the bus clock.
Figure 6-31. PDO Profiling Clock Control
STROBE
BUS CLOCK
PDO
CLOCK ENABLE
PDOCLK
The trace buffer is used as a temporary storage medium to store COF information before it is transmitted. COF information can be transmitted whilst new information is written to the trace buffer. The trace buffer data is transmitted at PDO least significant bit first. After the first trace buffer entry is made, transmission begins in the first clock period in which no further data is written to the trace buffer. If a trace buffer line transmission completes before the next trace buffer line is ready, then the clock output is held at a constant level until the line is ready for transfer.
6.4.6.2 Profiling Configuration, Alignment and Mode Dependencies The PROFILE bit must be set and the DBG armed to enable profiling. Furthermore the PDOE bit must be set to configure the PDO and PDOCLK pins for profiling. If TALIGN is configured for Begin-aligned tracing, then profiling begins when the state sequencer enters Final State. If PREND is clear then profiling entries continue until a software disarm or trace buffer overflow occurs. If PREND is set then, when the trace buffer is full, the profiling session is terminated, the PTBOVF bit is set and the ARM bit is cleared. This prevents rollover from overwriting the initial PTS entry and thus allows the trace buffer contents, containing the start address, to be read out by a debugger. Mid-Align tracing is not supported whilst profiling; if the TALIGN bits are configured for Mid-Align tracing when PROFILE is set, then the alignment defaults to end alignment. If TALIGN is configured for End-Aligned tracing then profiling begins as soon as the module is armed. If PREND is clear then profiling entries continue until either a trace buffer overflow occurs or the DBG is disarmed by a state machine transition to State0. If PREND is set then, when the trace buffer is full, the profiling session is terminated, the PTBOVF bit is set and the ARM bit is cleared. The profiling output transmission continues, even after disarming, until all trace buffer entries have been transmitted. The PTACT bit indicates if a profiling transmission is still active. The PTBOVF indicates if a trace buffer overflow has occurred. The profiling timestamp feature is used only for the PTVB and PTW formats, thus differing from timestamps offered in other modes. Profiling does not support trace buffer gating. The external pin gating feature is ignored during profiling.

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When the DBG module is disarmed but profiling transmission is ongoing, register write accesses are suppressed and reading from the DBGTB returns the code 0xEEEE.

6.4.6.3 Code Profiling Internal Data Storage Format
When profiling starts, the first trace buffer entry is made to provide the start address. This uses a 4 byte format (PTS), including the INFO byte and a 3-byte PC start address. In order to avoid trace buffer overflow a fully compressed format is used for direct (conditional branch) COF information.
Table 6-59. Profiling Trace buffer line format

Format

8-Byte Wide Trace Buffer Line

7

6

5

4

3

2

1

PTS PTIB PTHF PTVB PTW

Indirect

Indirect

Timestamp Timestamp Timestamp Timestamp

Indirect 0
Vector 0

Direct Direct Direct Direct

PC Start Address

Direct

Direct

Direct

Direct

Direct

Direct

Direct

Direct

Direct

Direct

Direct

Direct

0
INFO INFO INFO INFO INFO

The INFO byte indicates the line format used. Up to 4 bytes of each line are dedicated to branch COFs. Further bytes are used for storing indirect COF information (indexed jumps and interrupt vectors). Indexed jumps force a full line entry with the PTIB format and require 3-bytes for the full 24-bit destination address. Interrupts force a full line entry with the PTVB format, whereby vectors are stored as a single byte and a 16-bit timestamp value is stored simultaneously to indicate the number of core clock cycles relative to the previous COF. At each trace buffer entry the 16-bit timestamp counter is cleared. The device vectors use address[8:0] whereby address[1:0] are constant zero for vectors. Thus the value stored to the PTVB vector byte is equivalent to (Vector Address[8:1]).
After the PTS entry, the pointer increments and the DBG begins to fill the next line with direct COF information. This continues until the direct COF field is full or an indirect COF occurs, then the INFO byte and, if needed, indirect COF information are entered on that line and the pointer increments to the next line.
If a timestamp overflow occurs, indicating a 65536 bus clock cycles without COF, then an entry is made with the TSOVF bit set, INFO[6] (Table 6-60) and profiling continues.
If a trace buffer overflow occurs, a final entry is made with the TBOVF bit set, profiling is terminated and the DBG is disarmed. Trace buffer overflow occurs when the trace buffer contains 64 lines pending transmission.
Whenever the DBG is disarmed during profiling, a final entry is made with the TERM bit set to indicate the final entry.
When a final entry is made then by default the PTW line format is used, except if a COF occurs in the same cycle in which case the corresponding PTIB/PTVB/PTHF format is used. Since the development tool receives the INFO byte first, it can determine in advance the format of data it is about to receive. The

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transmission of the INFO byte starts when a line is complete. Whole bytes are always transmitted. The grey shaded bytes of Table 6-59 are not transmitted.
Figure 6-32. INFO byte encoding

7

6

5

4

3

2

1

0

0

TSOVF

TBOVF

TERM

Line Format

INFO[3:0]
0000 0001 0010 0011 0111 Others
INFO[7:4]
INFO[7] INFO[6] INFO[5] INFO[4] Vector[7:0]

Table 6-60. Profiling Format Encoding

Line Format
PTS PTIB PTHF PTVB PTW Reserved
Bit Name
Reserved TSOVF TBOVF TERM Vector[7:0]

Source CPU CPU CPU CPU CPU CPU
CPU CPU CPU CPU CPU

Description
Initial CPU entry Indexed jump with up to 31 direct COFs
31 direct COFs without indirect COF Vector with up to 31 direct COFs Error (Error codes in INFO[7:4]) Reserved
Description
Reserved Timestamp Overflow Trace Buffer Overflow Profiling terminated by disarming Device Interrupt Vector Address [8:1]

6.4.6.4 Direct COF Compression
Each branch COF is stored to the trace buffer as a single bit (0=branch not taken, 1=branch taken) until an indirect COF (indexed jump, return, or interrupt) occurs. The branch COF entries are stored in the byte fields labelled "Direct" in Table 6-59. These entries start at byte1[0] and continue through to byte4[7], or until an indirect COF occurs, whichever occurs sooner. The entries use a format whereby the left most asserted bit is always the stop bit, which indicates that the bit to its right is the first direct COF and byte1[0] is the last COF that occurred before the indirect COF. This is shown in Table 6-61, whereby the Bytes 4 to 1 of the trace buffer are shown for 3 different cases. The stop bit field for each line is shaded.
In line0, the left most asserted bit is Byte4[7]. This indicates that all remaining 31 bits in the 4-byte field contain valid direct COF information, whereby each 1 represents branch taken and each 0 represents branch not taken. The stop bit of line1 indicates that all 30 bits to it's right are valid, after the 30th direct COF entry, an indirect COF occurred, that is stored in bytes 7 to 5. In this case the bit to the left of the stop bit is redundant. Line2 indicates that an indirect COF occurred after 8 direct COF entries. The indirect COF address is stored in bytes 7 to 5. All bits to the left of the stop bit are redundant.

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Line Line0 Line1 Line2

Byte4

Byte3

Byte2

Byte1

10010010010110010010000110000110

01100101100100101100100101100100

00000000000000000000000100010001

Table 6-61. Profiling Direct COF Format

6.4.7 Breakpoints
Breakpoints can be generated by state sequencer transitions to State0. Transitions to State0 are forced by the following events
· Through comparator matches via Final State. · Through software writing to the TRIG bit in the DBGC1 register via Final State. · Through the external event input (DBGEEV) via Final State. · Through a profiling trace buffer overflow event.
Breakpoints are not generated by software writes to DBGC1 that clear the ARM bit.

6.4.7.1 Breakpoints From Comparator Matches or External Events
Breakpoints can be generated when the state sequencer transitions to State0 following a comparator match or an external event.
If a tracing session is selected by TSOURCE, the transition to State0 occurs when the tracing session has completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace. If End aligned tracing or no tracing session is selected, the transition to State0 and associated breakpoints are immediate.

6.4.7.2 Breakpoints Generated Via The TRIG Bit
When TRIG is written to "1", the Final State is entered. If a tracing session is selected by TSOURCE, State0 is entered and breakpoints are requested only when the tracing session has completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace. If no tracing session is selected, the state sequencer enters State0 immediately and breakpoints are requested. TRIG breakpoints are possible even if the DBG module is disarmed.

6.4.7.3 DBG Breakpoint Priorities
If a TRIG occurs after Begin or Mid aligned tracing has already been triggered by a comparator instigated transition to Final State, then TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent comparator match, it has no effect, since tracing has already started.

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6.4.7.3.1 DBG Breakpoint Priorities And BDC Interfacing
Breakpoint operation is dependent on the state of the S12ZBDC module. BDM cannot be entered from a breakpoint unless the BDC is enabled (ENBDC bit is set in the BDC). If BDM is already active, breakpoints are disabled. In addition, while executing a BDC STEP1 command, breakpoints are disabled.
When the DBG breakpoints are mapped to BDM (BDMBP set), then if a breakpoint request, either from a BDC BACKGROUND command or a DBG event, coincides with an SWI instruction in application code, (i.e. the DBG requests a breakpoint at the next instruction boundary and the next instruction is an SWI) then the CPU gives priority to the BDM request over the SWI request.
On returning from BDM, the SWI from user code gets executed. Breakpoint generation control is summarized in Table 6-62.
Table 6-62. Breakpoint Mapping Summary

BRKCPU
0 1 1 1 1 1

BDMBP Bit (DBGC1[4])
X 0 0 1 1 1

BDC Enabled
X X 1 0 1 1

BDM Active
X 0 1 X 0 1

Breakpoint Mapping
No Breakpoint Breakpoint to SWI
No Breakpoint No Breakpoint Breakpoint to BDM No Breakpoint

6.5 Application Information

6.5.1 Avoiding Unintended Breakpoint Re-triggering
Returning from an instruction address breakpoint using an RTI or BDC GO command without PC modification, returns to the instruction that generated the breakpoint. If an active breakpoint or trigger still exists at that address, this can re-trigger, disarming the DBG. If configured for BDM breakpoints, the user must apply the BDC STEP1 command to increment the PC past the current instruction.
If configured for SWI breakpoints, the DBG can be re configured in the SWI routine. If a comparator match occurs at an SWI vector address then a code SWI and DBG breakpoint SWI could occur simultaneously. In this case the SWI routine is executed twice before returning.

6.5.2 Debugging Through Reset
To debug through reset, the debugger can recognize a reset occurrence and pull the device BKGD pin low. This forces the device to leave reset in special single chip (SSC) mode, because the BKGD pin is used as the MODC signal in the reset phase. When the device leaves reset in SSC mode, CPU execution is halted and the device is in active BDM. Thus the debugger can configure the DBG for tracing and breakpoints before returning to application code execution. In this way it is possible to analyze the sequence of events emerging from reset. The recommended handling of the internal reset scenario is as follows:

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· When a reset occurs the debugger pulls BKGD low until the reset ends, forcing SSC mode entry. · Then the debugger reads the reset flags to determine the cause of reset. · If required, the debugger can read the trace buffer to see what happened just before reset. Since the
trace buffer and DBGCNT register are not affected by resets other than POR. · The debugger configures and arms the DBG to start tracing on returning to application code. · The debugger then sets the PC according to the reset flags. · Then the debugger returns to user code with GO or STEP1.
6.5.3 Breakpoints from other S12Z sources
The DBG is neither affected by CPU BGND instructions, nor by BDC BACKGROUND commands.
6.5.4 Code Profiling
The code profiling data output pin PDO is mapped to a device pin that can also be used as GPIO in an application. If profiling is required and all pins are required in the application, it is recommended to use the device pin for a simple output function in the application, without feedback to the chip. In this way the application can still be profiled, since the pin has no effect on code flow.
The PDO provides a simple bit stream that must be strobed at both edges of the profiling clock when profiling. The external development tool activates profiling by setting the DBG ARM bit, with PROFILE and PDOE already set. Thereafter the first bit of the profiling bit stream is valid at the first rising edge of the profiling clock. No start bit is provided. The external development tool must detect this first rising edge after arming the DBG. To detect the end of profiling, the DBG ARM bit can be monitored using the BDC.

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Table 7-1. Revision History Table

Rev. No. (Item No.)
V01.00

Date 15-Oct-13

V01.10 19-March-15

Sections Affected
all
7.3.1

Substantial Change(s)
Initial Module Version add feature description for S12ZVMC256 in case of non-aligned write to memory data word containing a double bit ECC error

7.1 Introduction
The purpose of ECC logic is to detect and correct as much as possible memory data bit errors. These soft errors, mainly generated by alpha radiation, can occur randomly during operation. "Soft error" means that only the information inside the memory cell is corrupt; the memory cell itself is not damaged. A write access with correct data solves the issue. If the ECC algorithm is able to correct the data, then the system can use this corrected data without any issues. If the ECC algorithm is able to detect, but not correct the error, then the system is able to ignore the memory read data to avoid system malfunction.
The ECC value is calculated based on an aligned 2 byte memory data word. The ECC algorithm is able to detect and correct single bit ECC errors. Double bit ECC errors will be detected but the system is not able to correct these errors. This kind of ECC code is called SECDED code. This ECC code requires 6 additional parity bits for each 2 byte data word.
7.1.1 Features
The SRAM_ECC module provides the ECC logic for the system memory based on a SECDED algorithm. The SRAM_ECC module includes the following features:
· SECDED ECC code
­ Single bit error detection and correction per 2 byte data word
­ Double bit error detection per 2 byte data word
· Memory initialization function
· Byte wide system memory write access
· Automatic single bit ECC error correction for read and write accesses
· Debug logic to read and write raw use data and ECC values

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7.2 Memory Map and Register Definition
This section provides a detailed description of all memory and registers for the SRAM_ECC module.
7.2.1 Register Summary
Figure 7-1 shows the summary of all implemented registers inside the SRAM_ECC module.

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NOTE
Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level.

Address Offset Register Name

Bit 7

6

5

4

3

2

1

Bit 0

0x0000

R

0

0

0

0

0

0

0

RDY

ECCSTAT

W

0x0001

R

0

0

0

0

0

0

0

ECCIE

W

SBEEIE

0x0002

R

0

0

0

0

0

0

0

ECCIF

W

SBEEIF

0x0003 - 0x0006 R

0

0

0

0

0

0

Reserved

W

0x0007

R

ECCDPTRH W

DPTR[23:16]

0x0008

R

ECCDPTRM W

DPTR[15:8]

0x0009

R

ECCDPTRL

W

DPTR[7:1]

0x000A - 0x000B R

0

0

0

0

0

0

Reserved

W

0x000C

R

ECCDDH

W

DDATA[15:8]

0x000D

R

ECCDDL

W

DDATA[7:0]

0x000E

R

0

0

ECCDE

W

DECC[5:0]

0x000F

R

0

0

0

0

0

ECCDCMD

ECCDRR W

= Unimplemented, Reserved, Read as zero

0

0

0

0

0

ECCDW ECCDR

Figure 7-1. SRAM_ECC Register Summary

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7.2.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field functions follow the register diagrams, in bit order.

7.2.2.1 ECC Status Register (ECCSTAT)

Module Base + 0x00000

7

6

5

4

3

R

0

0

0

0

0

W

Reset

0

0

0

0

0

1. Read: Anytime Write: Never

Access: User read only(1)

2

1

0

0

0

RDY

0

0

0

Field
0 RDY

Figure 7-2. ECC Status Register (ECCSTAT)
Table 7-2. ECCSTAT Field Description
Description
ECC Ready-- Shows the status of the ECC module. 0 Internal SRAM initialization is ongoing, access to the SRAM is disabled 1 Internal SRAM initialization is done, access to the SRAM is enabled

7.2.2.2 ECC Interrupt Enable Register (ECCIE)

Module Base + 0x00001

7

6

5

4

3

2

R

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

1. Read: Anytime Write: Anytime

Access: User read/write(1)

1

0

0 SBEEIE

0

0

Figure 7-3. ECC Interrupt Enable Register (ECCIE)

Table 7-3. ECCIE Field Description

Field

Description

0

Single bit ECC Error Interrupt Enable -- Enables Single ECC Error interrupt.

SBEEIE 0 Interrupt request is disabled

1 Interrupt will be requested whenever SBEEIF is set

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7.2.2.3 ECC Interrupt Flag Register (ECCIF)

Module Base + 0x0002

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

SBEEIF

W

Reset

0

0

0

0

0

0

0

0

1. Read: Anytime Write: Anytime, write 1 to clear

Figure 7-4. ECC Interrupt Flag Register (ECCIF)

Table 7-4. ECCIF Field Description

Field

Description

0

Single bit ECC Error Interrupt Flag -- The flag is set to 1 when a single bit ECC error occurs.

SBEEIF 0 No occurrences of single bit ECC error since the last clearing of the flag

1 Single bit ECC error has occured since the last clearing of the flag

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7.2.2.4 ECC Debug Pointer Register (ECCDPTRH, ECCDPTRM, ECCDPTRL)

Module Base + 0x0007

Access: User read/write(1)

7

6

5

R

W

Reset

0

0

0

Module Base + 0x0008

4

3

DPTR[23:16]

0

0

2

1

0

0

0

0

Access: User read/write

7

6

5

R

W

Reset

0

0

0

Module Base + 0x0009

4

3

DPTR[15:8]

0

0

2

1

0

0

0

0

Access: User read/write

7

6

5

4

3

2

1

0

R

0

DPTR[7:1]

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented

Figure 7-5. ECC Debug Pointer Register (ECCDPTRH, ECCDPTRM, ECCDPTRL)
1. Read: Anytime Write: Anytime

Field
DPTR [23:0]

Table 7-5. ECCDPTR Register Field Descriptions
Description
ECC Debug Pointer -- This register contains the system memory address which will be used for a debug access. Address bits not relevant for SRAM address space are not writeable, so the software should read back the pointer value to make sure the register contains the intended memory address. It is possible to write an address value to this register which points outside the system memory. There is no additional monitoring of the register content; therefore, the software must make sure that the address value points to the system memory space.

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7.2.2.5 ECC Debug Data (ECCDDH, ECCDDL)

Module Base + 0x000C

Access: User read/write(1)

7

6

5

R

W

Reset

0

0

0

Module Base + 0x000D

4

3

DDATA[15:8]

0

0

2

1

0

0

0

0

Access: User read/write

7

6

5

4

3

2

1

0

R DDATA[7:0]
W

Reset

0

0

0

0

0

0

0

0

= Unimplemented

1. Read: Anytime Write: Anytime

Figure 7-6. ECC Debug Data (ECCDDH, ECCDDL)

Field
DDATA [23:0]

Table 7-6. ECCDD Register Field Descriptions
Description
ECC Debug Raw Data -- This register contains the raw data which will be written into the system memory during a debug write command or the read data from the debug read command.

7.2.2.6 ECC Debug ECC (ECCDE)

Module Base + 0x000E

7

6

5

4

R

0

0

W

Reset

0

0

0

0

1. Read: Anytime Write: Anytime

3

2

DECC[5:0]

0

0

Access: User read/write(1)

1

0

0

0

Figure 7-7. ECC Debug ECC (ECCDE)

Table 7-7. ECCDE Field Description

Field

Description

5:0 ECC Debug ECC -- This register contains the raw ECC value which will be written into the system memory DECC[5:0] during a debug write command or the ECC read value from the debug read command.

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7.2.2.7 ECC Debug Command (ECCDCMD)

Module Base + 0x000F

7

6

5

4

3

R

0

0

0

0

ECCDRR

W

Reset

0

0

0

0

0

1. Read: Anytime Write: Anytime, in special mode only

Access: User read/write(1)

2

1

0

0 ECCDW ECCDR

0

0

0

Figure 7-8. ECC Debug Command (ECCDCMD)

Table 7-8. ECCDCMD Field Description

Field

Description

7 ECCDRR

ECC Disable Read Repair Function-- Writing one to this register bit will disable the automatic single bit ECC error repair function during read access; see also chapter 7.3.7, "ECC Debug Behavior". 0 Automatic single ECC error repair function is enabled 1 Automatic single ECC error repair function is disabled

1 ECCDW

ECC Debug Write Command -- Writing one to this register bit will perform a debug write access, to the system memory. During this access the debug data word (DDATA) and the debug ECC value (DECC) will be written to the system memory address defined by DPTR. If the debug write access is done, this bit is cleared. Writing 0 has no effect. It is not possible to set this bit if the previous debug access is ongoing (ECCDW or ECCDR bit set).

0 ECCDR

ECC Debug Read Command -- Writing one to this register bit will perform a debug read access from the system memory address defined by DPTR. If the debug read access is done, this bit is cleared and the raw memory read data are available in register DDATA and the raw ECC value is available in register DECC. Writing 0 has no effect. If the ECCDW and ECCDR bit are set at the same time, then only the ECCDW bit is set and the Debug Write Command is performed. It is not possible to set this bit if the previous debug access is ongoing (ECCDW or ECCDR bit set).

7.3 Functional Description

The bus system allows 1, 2, 3 and 4 byte write access to a 4 byte aligned memory address, but the ECC value is generated based on an aligned 2 byte data word. Depending on the access type, the access is separated into different access cycles. Table 7-9 shows the different access types with the expected number of access cycles and the performed internal operations.

Table 7-9. Memory access cycles

Access type
2 and 4 byte aligned write
access

ECC access error cycle

--

1

Internal operation write to memory

Memory content new data

Error indication --

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Table 7-9. Memory access cycles

Access type

ECC access error cycle

no

2

1 or 3 byte write, non-aligned 2 byte write

single bit

2

double bit

2

no

1

read access

single bit

1

double bit

1

Internal operation
read data from the memory write old + new data to the memory
read data from the memory write corrected + new data to the
memory read data from the memory
ignore write data1 read from memory read data from the memory write corrected data back to memory
read from memory

Memory content
old + new data

Error indication --

corrected + new data

SBEEIF

unchanged1
unchanged corrected
data

initiator module is informed -
SBEEIF

unchanged data mark as invalid

The single bit ECC error generates an interrupt when enabled. The double bit ECC errors are reported by the SRAM_ECC module, but handled at MCU level. For more information, see the MMC description.

7.3.1 Non-aligned Memory Write Access
Non-aligned write accesses are separated into a read-modify-write operation. During the first cycle, the logic reads the data from the memory and performs an ECC check. If no ECC errors were detected then the logic generates the new ECC value based on the read and write data and writes the new data word together with the new ECC value into the memory. If required both 2 byte data words are updated.
If the module detects a single bit ECC error during the read cycle, then the logic generates the new ECC value based on the corrected read and new write read. In the next cycle, the new data word and the new ECC value are written into the memory. If required both 2 byte data words are updated. The SBEEIF bit is set. Hence, the single bit ECC error was corrected by the write access. Figure 7-9 shows an example of a 2 byte non-aligned memory write access.
If the module detects a double bit ECC error during the read cycle, then the write access to the memory is blocked and the initiator module is informed about the error1.

1. On S12ZVMC256 device only, the data are written into the memory even if a double bit ECC error was detected. The data word written to the memory is undefined due to the correction based on a double bit ECC error signature. The written data word is ECC clean.

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.

2 byte use data

ECC

read out data and correct if single bit ECC error was found

correct read data

2 byte use data

ECC

read out data and correct if single bit ECC error was found

correct read data

4 byte read data from system memory

write data

write data

2 byte write data

correct read data

write data

ECC

write data

correct read data

ECC

4 byte write data to system memory

Figure 7-9. 2 byte non-aligned write access
7.3.2 Aligned 2 and 4 Byte Memory Write Access
During an aligned 2 or 4 byte memory write access, no ECC check is performed. The internal ECC logic generates the new ECC value based on the write data and writes the data words together with the generated ECC values into the memory.
7.3.3 Memory Read Access
During each memory read access an ECC check is performed. If the logic detects a single bit ECC error, then the module corrects the data, so that the access initiator module receives correct data. In parallel, the logic writes the corrected data back to the memory, so that this read access repairs the single bit ECC error. This automatic ECC read repair function is disabled by setting the ECCDRR bit.
If a single bit ECC error was detected, then the SBEEIF flag is set.
If the logic detects a double bit ECC error, then the data word is flagged as invalid, so that the access initiator module can ignore the data.
7.3.4 Memory Initialization
To avoid spurious ECC error reporting, memory operations that allow a read before a first write (like the read-modify-write operation of the non-aligned access) require that the memory contains valid ECC values before the first read-modify-write access is performed. The ECC module provides logic to initialize the complete memory content with zero during the power up phase. During the initialization process the access to the SRAM is disabled and the RDY status bit is cleared. If the initialization process is done, SRAM access is possible and the RDY status bit is set.

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7.3.5 Interrupt Handling
This section describes the interrupts generated by the SRAM_ECC module and their individual sources. Vector addresses and interrupt priority are defined at the MCU level.
Table 7-10. SRAM_ECC Interrupt Sources

Module Interrupt Sources

Single bit ECC error

ECCIE[SBEEIE]

Local Enable

7.3.6 ECC Algorithm

The table below shows the equation for each ECC bit based on the 16 bit data word.
Table 7-11. ECC Calculation

ECC bit

Use data

ECC[0] ECC[1] ECC[2] ECC[3] ECC[4] ECC[5]

~ ( ^ ( data[15:0] & 0x443F ) ) ~ ( ^ ( data[15:0] & 0x13C7 ) ) ~ ( ^ ( data[15:0] & 0xE1D1 ) ) ~ ( ^ ( data[15:0] & 0xEE60 ) ) ~ ( ^ ( data[15:0] & 0x3E8A ) ) ~ ( ^ ( data[15:0] & 0x993C ) )

7.3.7 ECC Debug Behavior
For debug purposes, it is possible to read and write the uncorrected use data and the raw ECC value directly from the memory. For these debug accesses a register interface is available. The debug access is performed with the lowest priority; other memory accesses must be done before the debug access starts. If a debug access is requested during an ongoing memory initialization process, then the debug access is performed if the memory initialization process is done.
If the ECCDRR bit is set, then the automatic single bit ECC error repair function for all read accesses is disabled. In this case a read access from a system memory location with single bit ECC error will produce correct data and the single bit ECC error is flagged by the SBEEIF, but the data inside the system memory are unchanged.
By writing wrong ECC values into the system memory the debug access can be used to force single and double bit ECC errors to check the software error handling .
It is not possible to set the ECCDW or ECCDR bit if the previous debug access is ongoing (ECCDW or ECCDR bit active). This ensures that the ECCDD and ECCDE registers contains consistent data. The software should read out the status of the ECCDW and ECCDR register bit before a new debug access is requested.

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7.3.7.1 ECC Debug Memory Write Access
Writing one to the ECCDW bit performs a debug write access to the memory address defined by register DPTR. During this access, the raw data DDATA and the ECC value DECC are written directly into the system memory. If the debug write access is done, the ECCDW register bit is cleared. The debug write access is always a 2 byte aligned memory access, so that no ECC check is performed and no single or double bit ECC error indication is activated.
7.3.7.2 ECC Debug Memory Read Access
Writing one to the ECCDR bit performs a debug read access from the memory address defined by register DPTR. If the ECCDR bit is cleared then the register DDATA contains the uncorrected read data from the memory. The register DECC contains the ECC value read from the memory. Independent of the ECCDRR register bit setting, the debug read access will not perform an automatic ECC repair during read access. During the debug read access no ECC check is performed, so that no single or double bit ECC error indication is activated.
If the ECCDW and the ECCDR bits are set at the same time, then only the debug write access is performed.

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Table 8-1. Revision History

Rev. No. (Item No)

Date (Submitted By)

V10.01

3 Dec. 2014

V10.02 V10.03 V10.04 V10.05 V10.06

22 Jan. 2015 23 Jan. 2015 27 Jan. 2015 10 Feb. 2015 20 Feb. 2015

V10.07

3 Mar. 2015

V10.08 V10.09 V10.10 V10.11 V10.12

11 Mar. 2015 27 Mar. 2015 22 April 2015 24 April 2015 15 Sept. 2015

V10.13

6 Oct. 2015

Sections Affected

Substantial Change(s)
· Signal Description: added Figures to illustrate application of BCTL and BCTLS1
· VDDS1, VDDS2, SNPS1, SNPS2, BCTLS1, BCTLS2: added pins to Block Diagram and Signal Description
· correct typo in CPMUVREGTRIM0 register bits

· added section: differences between V10 and V6 · changed Framemaker variables to have V10_V6 instead of V10
· Diagram "BCTLS1 application example": added VRH switch · Added bits VRH2EN and VRH1EN to CPMUVREGCTL register
· Signal description of VDDS1/2: removed statement "monitored by LVR"
· Formal cleanup of header 1.2.6
· CPMUVREGCTL register: added footnote for bits only available in version V10
· CPMULVCTL register: added VDDSIE interrupt enable bit for VDDS1 and VDDS2 fail events
· Added CPMUVDDS register with 4 status bits and 4 interrupt flags
· CPMUVDDS register: added detailed register description · Interrupt chapter: Added VDDS Integrity Interrupt · Updated Differences V10 versus V6
· Syntax cleanup

· Removed blank page · Corrected typo in Application section
· Signal Description: Added more details to the description of the VDDS1, VDDS2, SNPS1, SNPS2 signals
· CPMUVDDS register: corrected reset values

· Section: Differences V10 versus V6: changed "VDD Integrity" to "VDDS Integrity"
· Improved EXTCON Bit description regarding presence of CANPHY
· CPMUVDDS register: Improved description of SCS1 and SCS2 Bits.

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8.1 Introduction
This specification describes the function of the Clock, Reset and Power Management Unit (S12_CPMU_UHV_V10 and S12CPMU_UHV_V6).
· The Pierce oscillator (XOSCLCP) provides a robust, low-noise and low-power external clock source. It is designed for optimal start-up margin with typical crystal oscillators.
· The Voltage regulator (VREGAUTO) operates from the range 6V to 18V. It provides all the required chip internal voltages and voltage monitors.
· The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter. · The Internal Reference Clock (IRC1M) provides a 1MHz internal clock.

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8.1.1 Differences between S12CPMU_UHV_V10 and S12CPMU_UHV_V6
· The following device pins exist only in V10: VDDS1, VDDS2, BCTLS1, BCTLS2, SNPS1, SNPS2,
· The feature of switching VDDS1/2 to VRH1/2 (which connects to ADC) exists only in V10 · The following register and bits exist only in V10:
CPMUVREGCTL register: Bits VRH2EN, VRH1EN, EXTS1ON, EXTS2ON CPMULVCTL register: Bit VDDSIE CPMUVDDS register · The VDDS Integrity Interrupt only exists in V10

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8.1.2 Features
The Pierce Oscillator (XOSCLCP) contains circuitry to dynamically control current gain in the output amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.
· Supports crystals or resonators from 4MHz to 20MHz. · High noise immunity due to input hysteresis and spike filtering. · Low RF emissions with peak-to-peak swing limited dynamically · Transconductance (gm) sized for optimum start-up margin for typical crystals · Dynamic gain control eliminates the need for external current limiting resistor · Integrated resistor eliminates the need for external bias resistor · Low power consumption: Operates from internal 1.8V (nominal) supply, Amplitude control limits
power · Optional oscillator clock monitor reset · Optional full swing mode for higher immunity against noise injection on the cost of higher power
consumption and increased emission
The Voltage Regulator (VREGAUTO) has the following features: · Input voltage range from 6 to 18V (nominal operating range) · Low-voltage detect (LVD) with low-voltage interrupt (LVI) · Power-on reset (POR) · Low-voltage reset (LVR) · On Chip Temperature Sensor and Bandgap Voltage measurement via internal ADC channel. · Voltage Regulator providing Full Performance Mode (FPM) and Reduced Performance Mode (RPM) · External ballast device support to reduce internal power dissipation · Capable of supplying both the MCU internally plus external components · Over-temperature interrupt
The Phase Locked Loop (PLL) has the following features: · Highly accurate and phase locked frequency multiplier · Configurable internal filter for best stability and lock time · Frequency modulation for defined jitter and reduced emission · Automatic frequency lock detector · Interrupt request on entry or exit from locked condition · PLL clock monitor reset · Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based. · PLL stability is sufficient for LIN communication in slave mode, even if using IRC1M as reference clock
The Internal Reference Clock (IRC1M) has the following features:

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· Frequency trimming (A factory trim value for 1MHz is loaded from Flash Memory into the IRCTRIM register after reset, which can be overwritten by application if required)
· Temperature Coefficient (TC) trimming. (A factory trim value is loaded from Flash Memory into the IRCTRIM register to turn off TC trimming after reset. Application can trim the TC if required by overwriting the IRCTRIM register).
Other features of the S12CPMU_UHV_V10_V6 include · Oscillator clock monitor to detect loss of crystal · Autonomous periodical interrupt (API) · Bus Clock Generator -- Clock switch to select either PLLCLK or external crystal/resonator based Bus Clock -- PLLCLK divider to adjust system speed · System Reset generation from the following possible sources: -- Power-on reset (POR) -- Low-voltage reset (LVR) -- COP system watchdog, COP reset on time-out, windowed COP -- Loss of oscillation (Oscillator clock monitor fail) -- Loss of PLL clock (PLL clock monitor fail) -- External pin RESET

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8.1.3 Modes of Operation
This subsection lists and briefly describes all operating modes supported by the S12CPMU_UHV_V10_V6.
8.1.3.1 Run Mode The voltage regulator is in Full Performance Mode (FPM).

NOTE
The voltage regulator is active, providing the nominal supply voltages with full current sourcing capability (see also Appendix for VREG electrical parameters). The features ACLK clock source, Low Voltage Interrupt (LVI), Low Voltage Reset (LVR) and Power-On Reset (POR) are available.

The Phase Locked Loop (PLL) is on.
The Internal Reference Clock (IRC1M) is on.
The API is available.
· PLL Engaged Internal (PEI) -- This is the default mode after System Reset and Power-On Reset. -- The Bus Clock is based on the PLLCLK. -- After reset the PLL is configured for 50MHz VCOCLK operation. Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 12.5MHz and Bus Clock is 6.25MHz. The PLL can be re-configured for other bus frequencies. -- The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M.
· PLL Engaged External (PEE) -- The Bus Clock is based on the PLLCLK. -- This mode can be entered from default mode PEI by performing the following steps: ­ Configure the PLL for desired bus frequency. ­ Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if necessary. ­ Enable the external oscillator (OSCE bit). ­ Wait for oscillator to start up (UPOSC=1) and PLL to lock (LOCK=1).
· PLL Bypassed External (PBE) -- The Bus Clock is based on the Oscillator Clock (OSCCLK). -- The PLLCLK is always on to qualify the external oscillator clock. Therefore it is necessary to make sure a valid PLL configuration is used for the selected oscillator frequency. -- This mode can be entered from default mode PEI by performing the following steps:

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­ Make sure the PLL configuration is valid for the selected oscillator frequency. ­ Enable the external oscillator (OSCE bit). ­ Wait for oscillator to start up (UPOSC=1). ­ Select the Oscillator Clock (OSCCLK) as source of the Bus Clock (PLLSEL=0). -- The PLLCLK is on and used to qualify the external oscillator clock.
8.1.3.2 Wait Mode
For S12CPMU_UHV_V10_V6 Wait Mode is the same as Run Mode.
8.1.3.3 Stop Mode
This mode is entered by executing the CPU STOP instruction.
The voltage regulator is in Reduced Performance Mode (RPM).
NOTE The voltage regulator output voltage may degrade to a lower value than in Full Performance Mode (FPM), additionally the current sourcing capability is substantially reduced (see also Appendix for VREG electrical parameters). Only clock source ACLK is available and the Power On Reset (POR) circuitry is functional. The Low Voltage Interrupt (LVI) and Low Voltage Reset (LVR) are disabled.

The API is available.
The Phase Locked Loop (PLL) is off.
The Internal Reference Clock (IRC1M) is off.
Core Clock and Bus Clock are stopped.
Depending on the setting of the PSTP and the OSCE bit, Stop Mode can be differentiated between Full Stop Mode (PSTP = 0 or OSCE=0) and Pseudo Stop Mode (PSTP = 1 and OSCE=1). In addition, the behavior of the COP in each mode will change based on the clocking method selected by COPOSCSEL[1:0].
· Full Stop Mode (PSTP = 0 or OSCE=0) External oscillator (XOSCLCP) is disabled.
-- If COPOSCSEL1=0: The COP and RTI counters halt during Full Stop Mode. After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). COP and RTI are running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0).
-- If COPOSCSEL1=1: The clock for the COP is derived from ACLK (trimmable internal RC-Oscillator clock). During Full Stop Mode the ACLK for the COP can be stopped (COP static) or running (COP active) depending on the setting of bit CSAD. When bit CSAD is set the ACLK clock source for the

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COP is stopped during Full Stop Mode and COP continues to operate after exit from Full Stop Mode. For this COP configuration (ACLK clock source, CSAD set) a latency time (please refer to CSAD bit description for details) occurs when entering or exiting (Full, Pseudo) Stop Mode. When bit CSAD is clear the ACLK clock source is on for the COP during Full Stop Mode and COP is operating. During Full Stop Mode the RTI counter halts. After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). The COP runs on ACLK and RTI is running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0).
· Pseudo Stop Mode (PSTP = 1 and OSCE=1) External oscillator (XOSCLCP) continues to run.
-- If COPOSCSEL1=0: If the respective enable bits are set (PCE=1 and PRE=1) the COP and RTI will continue to run with a clock derived from the oscillator clock. The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged.
-- If COPOSCSEL1=1: If the respective enable bit for the RTI is set (PRE=1) the RTI will continue to run with a clock derived from the oscillator clock. The clock for the COP is derived from ACLK (trimmable internal RC-Oscillator clock). During Pseudo Stop Mode the ACLK for the COP can be stopped (COP static) or running (COP active) depending on the setting of bit CSAD. When bit CSAD is set the ACLK for the COP is stopped during Pseudo Stop Mode and COP continues to operate after exit from Pseudo Stop Mode. For this COP configuration (ACLK clock source, CSAD set) a latency time (please refer to CSAD bit description for details) occurs when entering or exiting (Pseudo, Full) Stop Mode. When bit CSAD is clear the ACLK clock source is on for the COP during Pseudo Stop Mode and COP is operating. The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged.
NOTE
When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator tUPOSC before entering Pseudo Stop Mode.
8.1.3.4 Freeze Mode (BDM active)
For S12CPMU_UHV_V10_V6 Freeze Mode is the same as Run Mode except for RTI and COP which can be frozen in Active BDM Mode with the RSBCK bit in the CPMUCOP register. After exiting BDM Mode RTI and COP will resume its operations starting from this frozen status.
Additionally the COP can be forced to the maximum time-out period in Active BDM Mode. For details please see also the RSBCK and CR[2:0] bit description field of Table 8-14 in Section 8.3.2.12, "S12CPMU_UHV_V10_V6 COP Control Register (CPMUCOP)

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Chapter 8 S12 Clock, Reset and Power Management Unit (00.17)
S12CPMU_UHV_V10_V6 Block Diagram

VSUP

VDDA VSSA VDDX VSSX VSS1,2 VDD VDDF VDDC BCTL BCTLC

vsup monitor
ADC

RESET

VDDS1,2

BCTLS1,2

SNPS1,2

Low Voltage Detect VDDA

Voltage Regulator 6V to 18V

Low Voltage Detect

VDDX, VDD, VDDF
Power-On Detect

LVRF

(VREGAUTO)

PORF

PMRF OMRF

LVDS
COP time-out
COPRF

osc monitor fail

Reset Generator

LVIE Low Voltage Interrupt
S12CPMU_UHV
Power-On Reset System Reset

PLL monitor fail

IRCCLK

OSCCLK

EXTAL

Monitor Loop

Controlled

XTAL

Pierce Oscillator

REFDIV[3:0]

OSCCLK IRCTRIM[9:0]

UPOSC UPOSC=0 sets PLLSEL bit

OSCCLK
Oscillator status Interrupt OSCIE

(XOSCLCP) 4MHz-20MHz

Reference Divider

PSTP OSCMOD

Internal Reference
Clock (IRC1M)
IRCCLK

OSCE

POSTDIV[4:0]

PLLSEL

Post Divider 1,2,.32

PLLCLK

divide ECLK by 2 (Bus Clock)
ECLK2X (Core Clock)

Lock detect

REFCLK FBCLK

Phase locked Loop with internal Filter (PLL)

divide by 4 VCOCLK

HTDS

HTIE HT Interrupt

LOCK

REFFRQ[1:0] VCOFRQ[1:0]

High Temperature Sense
LOCKIE

PLL lock interrupt

UPOSC ACLK CSAD

Divide by 2*(SYNDIV+1)

Bus Clock divide by 2

Autonomous Periodic

API_EXTCLK

Interrupt (API)

divide by 2

SYNDIV[5:0] COPOSCSEL1

ACLK RC Osc.

IRCCLK OSCCLK

COPCLK COP Watchdog

COP time-out to Reset Generator IRCCLK

COPOSCSEL0

PCE CPMUCOP OSCCLK

APICLK

APIE RTIE

Real Time RTICLK Interrupt (RTI)

API Interrupt RTI Interrupt

UPOSC=0 clears

RTIOSCSEL PRE CPMURTI

Figure 8-1. Block diagram of S12CPMU_UHV_V10_V6

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Figure 8-2 shows a block diagram of the XOSCLCP.
OSCMOD

Peak Detector

+

Gain Control

_

VDD=1.8V

Clock monitor fail Monitor
OSCCLK

VSS Rf

EXTAL

Quartz Crystals or
Ceramic Resonators

XTAL

C1

C2

VSS

VSS

Figure 8-2. XOSCLCP Block Diagram

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8.2 Signal Description
This section lists and describes the signals that connect off chip as well as internal supply nodes and special signals.
8.2.1 RESET
Pin RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered.
8.2.2 EXTAL and XTAL
These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. If XOSCLCP is enabled, the MCU internal OSCCLK_LCP is derived from the EXTAL input frequency. If OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 k and the XTAL pin is pulled down by an internal resistor of approximately 700 k.
NOTE NXP recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. The loop controlled circuit (XOSCLCP) is not suited for overtone resonators and crystals.
8.2.3 VSUP -- Regulator Power Input Pin
Pin VSUP is the power input of VREGAUTO. All currents sourced into the regulator loads flow through this pin. A suitable reverse battery protection network can be used to connect VSUP to the car battery supply network.
8.2.4 VDDA, VSSA -- Regulator Reference Supply Pins
Pins VDDA and VSSA,are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. An off-chip decoupling capacitor (220 nF(X7R ceramic)) between VDDA and VSSA is required and can improve the quality of this supply. VDDA has to be connected externally to VDDX.
8.2.5 VDDX, VSSX-- Pad Supply Pins
VDDX is the supply domain for the digital Pads. An off-chip decoupling capacitor (10F plus 220 nF(X7R ceramic)) between VDDX and VSSX is required.

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This supply domain is monitored by the Low Voltage Reset circuit. VDDX has to be connected externally to VDDA.
8.2.6 VDDC-- CAN Supply Pin
VDDC is the supply domain for the CAN module. An off-chip decoupling capacitor (10F plus 220 nF(X7R ceramic)) between VDDC and VSSX is required. This supply domain is monitored by the Low Voltage Reset circuit.
8.2.7 VDDS1-- Sensor Supply1 Pin
VDDS1 is a short circuit protected supply domain which is suitable for sensors (which connect externally to the PCB). An off-chip decoupling capacitor (4.7F plus 220 nF(X7R ceramic)) between VDDS1 and VSSX is required. This supply domain is monitored by a Low Voltage Detect (LVDS1) circuit.
8.2.8 VDDS2-- Sensor Supply2 Pin
VDDS2 is a short circuit protected supply domain which is suitable for sensors (which connect externally to the PCB). An off-chip decoupling capacitor (4.7F plus 220 nF(X7R ceramic)) between VDDS2 and VSSX is required. This supply domain is monitored by a Low Voltage Detect (LVDS2) circuit.
8.2.9 BCTL-- Base Control Pin for external PNP
BCTL is the ballast connection for the on chip voltage regulator. It provides the base current of an external BJT (PNP) of the VDDX and VDDA supplies. An additional 1K resistor between emitter and base of the BJT is required. Figure 8-3 shows an application example for the external BCTL pin.

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MCU

VRBATP (reverse battery protected input voltage)

1K

Voltage

BCTL

E

Regulator

B

C VDDX

Figure 8-3. BCTL application example
8.2.10 BCTLC -- Base Control Pin for external PNP for VDDC power domain
BCTLC is the ballast connection for the on chip voltage regulator for the VDDC power domain. It provides the base current of an external BJT (PNP) of the VDDC supply. An additional 1K resistor between emitter and base of the BJT is required.
8.2.11 BCTLS1 -- Base Control Pin for external PNP for VDDS1 power domain
BCTLS1 is the ballast connection for the on chip voltage regulator for the VDDS1 power domain. It provides the base current of an external BJT (PNP) of the VDDS1 supply. An additional 1K resistor between emitter and base of the BJT is required. Figure 8-4 shows an application example for the external BCTLS1 pin.

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MCU

VRBATP (reverse battery protected input voltage)

Voltage

1K BCTLS1

E

Regulator

B

C SNPS1

ADC

VRH1

VRH1EN

VSNPSM

VDDS1

RSNPS1

Figure 8-4. BCTLS1 application example
8.2.12 BCTLS2 -- Base Control Pin for external PNP for VDDS2 power domain
BCTLS2 is the ballast connection for the on chip voltage regulator for the VDDS2 power domain. It provides the base current of an external BJT (PNP) of the VDDS2 supply. An additional 1K resistor between emitter and base of the BJT is required.
8.2.13 SNPS1 -- Sense Pin for VDDS1 power domain
SNPS1 is the sense input associated with the VDDS1 power domain regulator. The voltage regulator uses it to detect a short circuit or over current condition and subsequently limits the current to avoid damage. RSNPS1 = VSNPSM / (desired max current flowing)
8.2.14 SNPS2 -- Sense Pin for VDDS2 power domain
SNPS2 is the sense input associated with the VDDS2 power domain regulator. The voltage regulator uses it to detect a short circuit or over current condition and subsequently limits the current to avoid damage. RSNPS2 = VSNPSM / (desired max current flowing)
8.2.15 VSS1,2 -- Core Ground Pins
VSS1,2 are the core logic supply return pins. They must be grounded.

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8.2.16 VDD-- Core Logic Supply Pin
VDD is the supply domain for the core logic. An off-chip decoupling capacitor (220 nF(X7R ceramic)) between VDD and VSS is required and can improve the quality of this supply. This supply domain is monitored by the Low Voltage Reset circuit and The Power On Reset circuit.
8.2.17 VDDF-- NVM Logic Supply Pin
VDDF is the supply domain for the NVM logic. An off-chip decoupling capacitor (220 nF(X7R ceramic)) between VDDF and VSS is required and can improve the quality of this supply. This supply domain is monitored by the Low Voltage Reset circuit.
8.2.18 API_EXTCLK -- API external clock output pin
This pin provides the signal selected via APIES and is enabled with APIEA bit. See the device specification if this clock output is available on this device and to which pin it might be connected.
8.2.19 TEMPSENSE -- Internal Temperature Sensor Output Voltage
Depending on the VSEL setting either the voltage level generated by the temperature sensor or the VREG bandgap voltage is driven to a special channel input of the ADC Converter. See device level specification for connectivity of ADC special channels.

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8.3 Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12CPMU_UHV_V10_V6.
8.3.1 Module Memory Map
The S12CPMU_UHV_V10_V6 registers are shown in Figure 8-5.

Address Offset

Register Name

0x0000

CPMU

R

RESERVED00 W

RESERVED R

0x0001

CPMU VREGTRIM0

W

RESERVED R

0x0002

CPMU VREGTRIM1

W

R 0x0003 CPMURFLG
W

0x0004

CPMU

R

SYNR

W

0x0005

CPMU

R

REFDIV W

0x0006

CPMU

R

POSTDIV W

R 0x0007 CPMUIFLG
W

R 0x0008 CPMUINT
W

R 0x0009 CPMUCLKS
W

0x000A

R CPMUPLL
W

R 0x000B CPMURTI
W

R 0x000C CPMUCOP
W

0x000D

RESERVED CPMUTEST0

R W

Bit 7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

U

U

U

0

0

U

U

U

0

0

0

0

0

PORF

LVRF

COPRF

OMRF

VCOFRQ[1:0]

REFFRQ[1:0]

0

0

0 RTIF
0 RTIE

PLLSEL 0

PSTP 0

SYNDIV[5:0]

0

0

REFDIV[3:0]

0 POSTDIV[4:0]

0

LOCK

0

LOCKIF

OSCIF

0

0

LOCKIE

0 OSCIE

CSAD FM1

COP OSCSEL1
FM0

PRE 0

PCE 0

RTI OSCSEL
0

RTDEC WCOP
0

RTR6

RTR5

RTR4

0

0

RSBCK

WRTMASK

0

0

0

RTR3 0 0

RTR2 CR2
0

RTR1 CR1
0

= Unimplemented or Reserved Figure 8-5. CPMU Register Summary

Bit 0 0 U 0
PMRF
UPOSC 0
COP OSCSEL0
0 RTR0 CR0
0

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Address Offset

Register Name

Bit 7

6

5

4

3

2

0x000E

RESERVED CPMUTEST1

R W

0

0x000F

CPMU

R

ARMCOP W

0 Bit 7

0x0010

CPMU HTCTL

R Reserved W

0x0011

CPMU

R

LVCTL

W

0

0x0012

CPMU APICTL

R APICLK
W

R

0x0013 CPMUACLKTR

ACLKTR5

W

R

0x0014 CPMUAPIRH

APIR15

W

R 0x0015 CPMUAPIRL
W

APIR7

0x0016

RESERVED R CPMUTEST3 W

0

0x0017

R CPMUHTTR
W

HTOE

0x0018

CPMU

R

IRCTRIMH W

0x0019

CPMU

R

IRCTRIML W

R

0x001A CPMUOSC

OSCE

W

R

0

0x001B CPMUPROT

W

0x001C

RESERVED CPMUTEST2

R W

0

0x001D

CPMU VREGCTL

R VRH2EN
W

R

0

0x001E CPMUOSC2

W

R 0x001F CPMUVDDS
W

SCS2

0

0

0

0

0

0 Bit 6
0
0
0

0 Bit 5 VSEL
0
0

0 Bit 4
0
0

0 Bit 3 HTE
VDDSIE

0 Bit 2 HTDS
LVDS

APIES APIEA APIFE

ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0

APIR14 APIR13 APIR12 APIR11 APIR10

APIR6 0

APIR5 0

APIR4 0

APIR3 0

APIR2 0

0

0

0

TCTRIM[4:0]

HTTR3

HTTR2 0

IRCTRIM[7:0]

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0 VRH1EN EXTS2ON EXTS1ON

0

0

0

0

0
EXTCON 0

SCS1

LVDS2

LVDS1 SCS2IF SCS1IF

1 0
0 Bit 1 HTIE
LVIE
APIE 0

Bit 0 0
0 Bit 0 HTIF
LVIF
APIF 0

APIR9 APIR1
0

APIR8 APIR0
0

HTTR1 HTTR0 IRCTRIM[9:8]

0

0

0 PROT
0 0

EXTXON INTXON

OMRE OSCMOD

LVS2IF LVS1IF

= Unimplemented or Reserved Figure 8-5. CPMU Register Summary

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8.3.2 Register Descriptions
This section describes all the S12CPMU_UHV_V10_V6 registers and their individual bits. Address order is as listed in Figure 8-5

8.3.2.1

Reserved Register CPMUVREGTRIM0
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V10_V6's functionality.

.

Module Base + 0x0001

7

6

5

4

3

2

1

0

R

0

0

0

0

U

W

Reset

0

0

0

0

F

F

F

F

Power on Reset

0

0

0

0

0

0

0

0

Note: After de-assert of System Reset a value is automatically loaded from the Flash memory.

Figure 8-6. Reserved Register (CPMUVREGTRIM0)

Read: Anytime Write: Only in Special Mode

8.3.2.2

Reserved Register CPMUVREGTRIM1
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V10_V6's functionality.

.

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Module Base + 0x0002

7

6

5

4

3

2

1

0

R

0

0

U

U

U

0

0

0

W

Reset

0

0

F

F

F

0

0

0

Power on Reset

0

0

0

0

0

0

0

0

Note: After de-assert of System Reset a value is automatically loaded from the Flash memory.

Figure 8-7. Reserved Register (CPMUVREGTRIM1)

Read: Anytime Write: Only in Special Mode

8.3.2.3 S12CPMU_UHV_V10_V6 Reset Flags Register (CPMURFLG) This register provides S12CPMU_UHV_V10_V6 reset flags.

Module Base + 0x0003

7

R

0

W

6
PORF

5
LVRF

4

3

2

0

0

COPRF

1
OMRF

0
PMRF

Reset

0

Note 1

Note 2

0

Note 3

0

Note 4

Note 5

1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset. 2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset. 3. COPRF is set to 1 when COP reset occurs. Unaffected by System Reset. Cleared by power on reset. 4. OMRF is set to 1 when an oscillator clock monitor reset occurs. Unaffected by System Reset. Cleared by power on reset. 5. PMRF is set to 1 when a PLL clock monitor reset occurs. Unaffected by System Reset. Cleared by power on reset.

= Unimplemented or Reserved Figure 8-8. S12CPMU_UHV_V10_V6 Flags Register (CPMURFLG)

Read: Anytime

Write: Refer to each bit for individual write conditions

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Field 6
PORF
5 LVRF
3 COPRF
1 OMRF
0 PMRF

Table 8-2. CPMURFLG Field Descriptions
Description
Power on Reset Flag -- PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Power on reset has not occurred. 1 Power on reset has occurred.
Low Voltage Reset Flag -- LVRF is set to 1 when a low voltage reset occurs on the VDD, VDDF or VDDX domain. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Low voltage reset has not occurred. 1 Low voltage reset has occurred.
COP Reset Flag -- COPRF is set to 1 when a COP (Computer Operating Properly) reset occurs. Refer to 8.5.5, "Computer Operating Properly Watchdog (COP) Reset and 8.3.2.12, "S12CPMU_UHV_V10_V6 COP Control Register (CPMUCOP) for details.This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 COP reset has not occurred. 1 COP reset has occurred.
Oscillator Clock Monitor Reset Flag -- OMRF is set to 1 when a loss of oscillator (crystal) clock occurs. Refer to8.5.3, "Oscillator Clock Monitor Reset for details.This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Loss of oscillator clock reset has not occurred. 1 Loss of oscillator clock reset has occurred.
PLL Clock Monitor Reset Flag -- PMRF is set to 1 when a loss of PLL clock occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Loss of PLL clock reset has not occurred. 1 Loss of PLL clock reset has occurred.

8.3.2.4 S12CPMU_UHV_V10_V6 Synthesizer Register (CPMUSYNR)
The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency range.

Module Base + 0x0004

7

6

5

4

3

2

1

0

R VCOFRQ[1:0]
W

SYNDIV[5:0]

Reset

0

1

0

1

1

0

0

0

Figure 8-9. S12CPMU_UHV_V10_V6 Synthesizer Register (CPMUSYNR)

Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime. Else write has no effect.
NOTE Writing to this register clears the LOCK and UPOSC status bits.

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If PLL has locked (LOCK=1)

fVCO = 2  fREF  SYNDIV + 1

NOTE fVCO must be within the specified VCO frequency lock range. Bus frequency fbus must not exceed the specified maximum.
The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK frequency as shown in Table 8-3. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability).
Table 8-3. VCO Clock Frequency Selection

VCOCLK Frequency Ranges
32MHz <= fVCO <= 48MHz 48MHz < fVCO <= 80MHz
Reserved 80MHz < fVCO<= 100MHz

VCOFRQ[1:0]
00 01 10 11

8.3.2.5 S12CPMU_UHV_V10_V6 Reference Divider Register (CPMUREFDIV)
The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the external oscillator as reference.

Module Base + 0x0005

7

6

5

4

3

2

1

0

R REFFRQ[1:0]
W

0

0

REFDIV[3:0]

Reset

0

0

0

0

1

1

1

1

Figure 8-10. S12CPMU_UHV_V10_V6 Reference Divider Register (CPMUREFDIV)

Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime. Else write has no effect.
NOTE Write to this register clears the LOCK and UPOSC status bits.

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If XOSCLCP is enabled (OSCE=1) If XOSCLCP is disabled (OSCE=0)

fREF = ---R----E----F-f--O-D----S-I--V-C-----+-----1---fREF = fIRC1M

The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK frequency as shown in Table 8-4.
If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1MHz <= fREF <= 2MHz range. The bits can still be written but will have no effect on the PLL filter configuration.
For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability).

Table 8-4. Reference Clock Frequency Selection if OSC_LCP is enabled

REFCLK Frequency Ranges (OSCE=1)
1MHz <= fREF <= 2MHz 2MHz < fREF <= 6MHz 6MHz < fREF <= 12MHz
fREF >12MHz

REFFRQ[1:0]
00 01 10 11

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8.3.2.6 S12CPMU_UHV_V10_V6 Post Divider Register (CPMUPOSTDIV) The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
Module Base + 0x0006

7

6

5

4

3

2

1

0

R

0

0

0

W

POSTDIV[4:0]

Reset

0

0

0

0

0

0

1

1

= Unimplemented or Reserved

Figure 8-11. S12CPMU_UHV_V10_V6 Post Divider Register (CPMUPOSTDIV)

Read: Anytime Write: If PLLSEL=1 write anytime, else write has no effect

If PLL is locked (LOCK=1) If PLL is not locked (LOCK=0)

fPLL = ---P----O----S---f-T-V---D-C----I-O-V------+-----1---fPLL = f---V----4C-----O---

If PLL is selected (PLLSEL=1) fbus = f---P---2L----L---

When changing the POSTDIV[4:0] value or PLL transitions to locked stated (lock=1), it takes up to 32 Bus Clock cycles until fPLL is at the desired target frequency. This is because the post divider gradually changes (increases or decreases) fPLL in order to avoid sudden load changes for the on-chip voltage regulator.

8.3.2.7 S12CPMU_UHV_V10_V6 Interrupt Flags Register (CPMUIFLG) This register provides S12CPMU_UHV_V10_V6 status bits and interrupt flags.

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Module Base + 0x0007

7

6

R

0

RTIF

W

Reset

0

0

5

4

3

2

1

0

0

LOCK

0

UPOSC

LOCKIF

OSCIF

0

0

0

0

0

0

= Unimplemented or Reserved Figure 8-12. S12CPMU_UHV_V10_V6 Flags Register (CPMUIFLG)
Read: Anytime Write: Refer to each bit for individual write conditions
Table 8-5. CPMUIFLG Field Descriptions

Field 7
RTIF
4 LOCKIF
3 LOCK
1 OSCIF
0 UPOSC

Description
Real Time Interrupt Flag -- RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred.
PLL Lock Interrupt Flag -- LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (LOCKIE=1), LOCKIF causes an interrupt request. 0 No change in LOCK bit. 1 LOCK bit has changed.
Lock Status Bit -- LOCK reflects the current state of PLL lock condition. Writes have no effect. While PLL is unlocked (LOCK=0) fPLL is fVCO / 4 to protect the system from high core clock frequencies during the PLL stabilization time tlock. 0 VCOCLK is not within the desired tolerance of the target frequency.
fPLL = fVCO/4. 1 VCOCLK is within the desired tolerance of the target frequency.
fPLL = fVCO/(POSTDIV+1).
Oscillator Interrupt Flag -- OSCIF is set to 1 when UPOSC status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (OSCIE=1), OSCIF causes an interrupt request. 0 No change in UPOSC bit. 1 UPOSC bit has changed.
Oscillator Status Bit -- UPOSC reflects the status of the oscillator. Writes have no effect. Entering Full Stop Mode UPOSC is cleared. 0 The oscillator is off or oscillation is not qualified by the PLL. 1 The oscillator is qualified by the PLL.

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8.3.2.8 S12CPMU_UHV_V10_V6 Interrupt Enable Register (CPMUINT) This register enables S12CPMU_UHV_V10_V6 interrupt requests.

Module Base + 0x0008

7

6

R

0

RTIE

W

5

4

3

0

0

LOCKIE

2

1

0

0

0

OSCIE

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 8-13. S12CPMU_UHV_V10_V6 Interrupt Enable Register (CPMUINT)

Read: Anytime

Write: Anytime

Table 8-6. CPMUINT Field Descriptions

Field 7
RTIE
4 LOCKIE
1 OSCIE

Description
Real Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set.
PLL Lock Interrupt Enable Bit 0 PLL LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set.
Oscillator Corrupt Interrupt Enable Bit 0 Oscillator Corrupt interrupt requests are disabled. 1 Interrupt will be requested whenever OSCIF is set.

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8.3.2.9 S12CPMU_UHV_V10_V6 Clock Select Register (CPMUCLKS) This register controls S12CPMU_UHV_V10_V6 clock selection.

Module Base + 0x0009

R W Reset

7
PLLSEL

6
PSTP

5
CSAD

4
COP OSCSEL1

3
PRE

2
PCE

1
RTI OSCSEL

1

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 8-14. S12CPMU_UHV_V10_V6 Clock Select Register (CPMUCLKS)

0
COP OSCSEL0
0

Read: Anytime
Write:
· Only possible if PROT=0 (CPMUPROT register) in all MCU Modes (Normal and Special Mode).
· All bits in Special Mode (if PROT=0).
· PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal Mode (if PROT=0).
· CSAD: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
· COPOSCSEL0: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place. If COPOSCSEL0 was cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL0=1 or insufficient OSCCLK quality), then COPOSCSEL0 can be set once again.
· COPOSCSEL1: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place. COPOSCSEL1 will not be cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL1=1 or insufficient OSCCLK quality if OSCCLK is used as clock source for other clock domains: for instance core clock etc.).

NOTE
After writing CPMUCLKS register, it is strongly recommended to read back CPMUCLKS register to make sure that write of PLLSEL, RTIOSCSEL and COPOSCSEL was successful. This is because under certain circumstances writes have no effect or bits are automatically changed (see CPMUCLKS register and bit descriptions).

NOTE
When using the oscillator clock as system clock (write PLLSEL = 0) it is highly recommended to enable the oscillator clock monitor reset feature (write OMRE = 1 in CPMUOSC2 register). If the oscillator monitor reset feature is disabled (OMRE = 0) and the oscillator clock is used as system clock, the system will stall in case of loss of oscillation.

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Table 8-7. CPMUCLKS Descriptions

Field 7
PLLSEL
6 PSTP
5 CSAD

Description
PLL Select Bit This bit selects the PLLCLK as source of the System Clocks (Core Clock and Bus Clock). PLLSEL can only be set to 0, if UPOSC=1. UPOSC= 0 sets the PLLSEL bit. Entering Full Stop Mode sets the PLLSEL bit. 0 System clocks are derived from OSCCLK if oscillator is up (UPOSC=1, fbus = fosc / 2). 1 System clocks are derived from PLLCLK, fbus = fPLL / 2.
Pseudo Stop Bit This bit controls the functionality of the oscillator during Stop Mode. 0 Oscillator is disabled in Stop Mode (Full Stop Mode). 1 Oscillator continues to run in Stop Mode (Pseudo Stop Mode), option to run RTI and COP. Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the
resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator tUPOSC before entering Pseudo Stop Mode.
COP in Stop Mode ACLK Disable -- If this bit is set the ACLK for the COP in Stop Mode is disabled. Hence the COP is static while in Stop Mode and continues to operate after exit from Stop Mode.

For CSAD = 1 and COP is running on ACLK (COPOSCSEL1 = 1) the following applies: Due to clock domain crossing synchronization there is a latency time of 2 ACLK cycles to enter Stop Mode. After exit from STOP mode (when interrupt service routine is entered) the software has to wait for 2 ACLK cycles before it is allowed to enter Stop mode again (STOP instruction). It is absolutely forbidden to enter Stop Mode before this time of 2 ACLK cycles has elapsed.

4 COP OSCSEL1
3 PRE
2 PCE

0 COP running in Stop Mode (ACLK for COP enabled in Stop Mode). 1 COP stopped in Stop Mode (ACLK for COP disabled in Stop Mode)
COP Clock Select 1 -- COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP (see also Table 8-8). If COPOSCSEL1 = 1, COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit does not re-start the COP time-out period. COPOSCSEL1 selects the clock source to the COP to be either ACLK (derived from trimmable internal RC-
Oscillator) or clock selected via COPOSCSEL0 (IRCCLK or OSCCLK).
Changing the COPOSCSEL1 bit re-starts the COP time-out period. COPOSCSEL1 can be set independent from value of UPOSC. UPOSC= 0 does not clear the COPOSCSEL1 bit. 0 COP clock source defined by COPOSCSEL0 1 COP clock source is ACLK derived from a trimmable internal RC-Oscillator
RTI Enable During Pseudo Stop Bit -- PRE enables the RTI during Pseudo Stop Mode. 0 RTI stops running during Pseudo Stop Mode. 1 RTI continues running during Pseudo Stop Mode if RTIOSCSEL=1. Note: If PRE=0 or RTIOSCSEL=0 then the RTI will go static while Stop Mode is active. The RTI counter will not
be reset.
COP Enable During Pseudo Stop Bit -- PCE enables the COP during Pseudo Stop Mode. 0 COP stops running during Pseudo Stop Mode 1 COP continues running during Pseudo Stop Mode if COPOSCSEL=1 Note: If PCE=0 or COPOSCSEL=0 then the COP will go static while Stop Mode is active. The COP counter will
not be reset.

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Table 8-7. CPMUCLKS Descriptions (continued)

Field

Description

1

RTI Clock Select-- RTIOSCSEL selects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the

RTIOSCSEL RTIOSCSEL bit re-starts the RTI time-out period.

RTIOSCSEL can only be set to 1, if UPOSC=1.

UPOSC= 0 clears the RTIOSCSEL bit.

0 RTI clock source is IRCCLK.

1 RTI clock source is OSCCLK.

0 COP OSCSEL0

COP Clock Select 0 -- COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP (see also Table 8-8) If COPOSCSEL1 = 1, COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit does not re-start the COP time-out period. When COPOSCSEL1=0,COPOSCSEL0 selects the clock source to the COP to be either IRCCLK or OSCCLK. Changing the COPOSCSEL0 bit re-starts the COP time-out period. COPOSCSEL0 can only be set to 1, if UPOSC=1. UPOSC= 0 clears the COPOSCSEL0 bit. 0 COP clock source is IRCCLK. 1 COP clock source is OSCCLK

Table 8-8. COPOSCSEL1, COPOSCSEL0 clock source select description

COPOSCSEL1 0 0 1

COPOSCSEL0 0 1 x

COP clock source IRCCLK OSCCLK ACLK

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8.3.2.10 S12CPMU_UHV_V10_V6 PLL Control Register (CPMUPLL) This register controls the PLL functionality.

Module Base + 0x000A

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

FM1

FM0

W

Reset

0

0

0

0

0

0

0

0

Figure 8-15. S12CPMU_UHV_V10_V6 PLL Control Register (CPMUPLL)
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect.
NOTE Write to this register clears the LOCK and UPOSC status bits.
NOTE Care should be taken to ensure that the bus frequency does not exceed the specified maximum when frequency modulation is enabled.

Table 8-9. CPMUPLL Field Descriptions

Field

Description

5, 4

PLL Frequency Modulation Enable Bits -- FM1 and FM0 enable frequency modulation on the VCOCLK. This

FM1, FM0 is to reduce noise emission. The modulation frequency is fref divided by 16. See Table 8-10 for coding.

Table 8-10. FM Amplitude selection

FM1
0 0 1 1

FM0
0 1 0 1

FM Amplitude / fVCO Variation
FM off 1% 2% 4%

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8.3.2.11 S12CPMU_UHV_V10_V6 RTI Control Register (CPMURTI)
This register selects the time-out period for the Real Time Interrupt.
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else the RTI counter halts in Stop Mode.

Module Base + 0x000B

R W Reset

7
RTDEC

6
RTR6

5
RTR5

4
RTR4

3
RTR3

2
RTR2

1
RTR1

0

0

0

0

0

0

0

Figure 8-16. S12CPMU_UHV_V10_V6 RTI Control Register (CPMURTI)

Read: Anytime
Write: Anytime
NOTE A write to this register starts the RTI time-out period. A change of the RTIOSCSEL bit (writing a different value or loosing UPOSC status) restarts the RTI time-out period.

0
RTR0 0

Table 8-11. CPMURTI Field Descriptions

Field
7 RTDEC
6­4 RTR[6:4]
3­0 RTR[3:0]

Description
Decimal or Binary Divider Select Bit -- RTDEC selects decimal or binary based prescaler values. 0 Binary based divider value. See Table 8-12 1 Decimal based divider value. See Table 8-13
Real Time Interrupt Prescale Rate Select Bits -- These bits select the prescale rate for the RTI.See Table 812 and Table 8-13.
Real Time Interrupt Modulus Counter Select Bits -- These bits select the modulus counter target value to provide additional granularity.Table 8-12 and Table 8-13 show all possible divide values selectable by the CPMURTI register.

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Table 8-12. RTI Frequency Divide Rates for RTDEC = 0

RTR[3:0]
0000 (1) 0001 (2) 0010 (3) 0011 (4) 0100 (5) 0101 (6) 0110 (7) 0111 (8) 1000 (9) 1001 (10) 1010 (11) 1011 (12) 1100 (13) 1101 (14) 1110 (15) 1111 (16)

000 (OFF) OFF(1) OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF

001 (210) 210 2x210 3x210 4x210 5x210 6x210 7x210 8x210 9x210 10x210 11x210 12x210 13x210 14x210 15x210 16x210

010 (211) 211 2x211 3x211 4x211 5x211 6x211 7x211 8x211 9x211 10x211 11x211 12x211 13x211 14x211 15x211 16x211

RTR[6:4] =

011 (212) 212 2x212 3x212 4x212 5x212 6x212 7x212 8x212 9x212 10x212 11x212 12x212 13x212 14x212 15x212 16x212

100 (213) 213 2x213 3x213 4x213 5x213 6x213 7x213 8x213 9x213 10x213 11x213 12x213 13x213 14x213 15x213 16x213

101 (214) 214 2x214 3x214 4x214 5x214 6x214 7x214 8x214 9x214 10x214 11x214 12x214 13x214 14x214 15x214 16x214

110 (215) 215 2x215 3x215 4x215 5x215 6x215 7x215 8x215 9x215 10x215 11x215 12x215 13x215 14x215 15x215 16x215

111 (216) 216 2x216 3x216 4x216 5x216 6x216 7x216 8x216 9x216 10x216 11x216 12x216 13x216 14x216 15x216 16x216

1. Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.

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RTR[3:0]
0000 (1) 0001 (2) 0010 (3) 0011 (4) 0100 (5) 0101 (6) 0110 (7) 0111 (8) 1000 (9) 1001 (10) 1010 (11) 1011 (12) 1100 (13) 1101 (14) 1110 (15) 1111 (16)

Table 8-13. RTI Frequency Divide Rates for RTDEC=1

RTR[6:4] =

000 (1x103) 1x103 2x103 3x103 4x103 5x103 6x103 7x103 8x103 9x103 10 x103 11 x103 12x103 13x103 14x103 15x103 16x103

001 (2x103) 2x103 4x103 6x103 8x103 10x103 12x103 14x103 16x103 18x103 20x103 22x103 24x103 26x103 28x103 30x103 32x103

010 (5x103) 5x103 10x103 15x103 20x103 25x103 30x103 35x103 40x103 45x103 50x103 55x103 60x103 65x103 70x103 75x103 80x103

011 (10x103) 10x103 20x103 30x103 40x103 50x103 60x103 70x103 80x103 90x103 100x103 110x103 120x103 130x103 140x103 150x103 160x103

100 (20x103) 20x103 40x103 60x103 80x103 100x103 120x103 140x103 160x103 180x103 200x103 220x103 240x103 260x103 280x103 300x103 320x103

101 (50x103) 50x103 100x103 150x103 200x103 250x103 300x103 350x103 400x103 450x103 500x103 550x103 600x103 650x103 700x103 750x103 800x103

110 (100x103) 100x103 200x103 300x103 400x103 500x103 600x103 700x103 800x103 900x103
1x106 1.1x106 1.2x106 1.3x106 1.4x106 1.5x106 1.6x106

111 (200x103) 200x103 400x103 600x103 800x103
1x106 1.2x106 1.4x106 1.6x106 1.8x106 2x106 2.2x106 2.4x106 2.6x106 2.8x106 3x106 3.2x106

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8.3.2.12 S12CPMU_UHV_V10_V6 COP Control Register (CPMUCOP)
This register controls the COP (Computer Operating Properly) watchdog.
The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the COPOSCSEL0 and COPOSCSEL1 bit (see also Table 8-8). In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL0=1 and COPOSCEL1=0 and PCE=1 the COP continues to run, else the COP counter halts in Stop Mode with COPOSCSEL1 =0. In Full Stop Mode and Pseudo Stop Mode with COPOSCSEL1=1 the COP continues to run.

Module Base + 0x000C

7

6

5

4

R

0

0

WCOP

RSBCK

W

WRTMASK

3

2

1

0

0

CR2

CR1

CR0

Reset

F

0

0

0

0

F

F

F

After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for details.

= Unimplemented or Reserved

Figure 8-17. S12CPMU_UHV_V10_V6 COP Control Register (CPMUCOP)

Read: Anytime
Write: 1. RSBCK: Anytime in Special Mode; write to "1" but not to "0" in Normal Mode 2. WCOP, CR2, CR1, CR0: -- Anytime in Special Mode, when WRTMASK is 0, otherwise it has no effect -- Write once in Normal Mode, when WRTMASK is 0, otherwise it has no effect. ­ Writing CR[2:0] to "000" has no effect, but counts for the "write once" condition. ­ Writing WCOP to "0" has no effect, but counts for the "write once" condition.
When a non-zero value is loaded from Flash to CR[2:0] the COP time-out period is started.
A change of the COPOSCSEL0 or COPOSCSEL1 bit (writing a different value) or loosing UPOSC status while COPOSCSEL1 is clear and COPOSCSEL0 is set, re-starts the COP time-out period.
In Normal Mode the COP time-out period is restarted if either of these conditions is true: 1. Writing a non-zero value to CR[2:0] (anytime in special mode, once in normal mode) with WRTMASK = 0. 2. Writing WCOP bit (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0. 3. Changing RSBCK bit from "0" to "1".
In Special Mode, any write access to CPMUCOP register restarts the COP time-out period.

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Table 8-14. CPMUCOP Field Descriptions

Field

Description

7 WCOP

Window COP Mode Bit -- When set, a write to the CPMUARMCOP register must occur in the last 25% of the selected period. A write during the first 75% of the selected period generates a COP reset. As long as all writes occur during this window, $55 can be written as often as desired. Once $AA is written after the $55, the time-out logic restarts and the user must wait until the next window before writing to CPMUARMCOP. Table 8-15 shows the duration of this window for the seven available COP rates. 0 Normal COP operation 1 Window COP operation

6 RSBCK

COP and RTI Stop in Active BDM Mode Bit 0 Allows the COP and RTI to keep running in Active BDM mode. 1 Stops the COP and RTI counters whenever the part is in Active BDM mode.

5 WRTMASK

Write Mask for WCOP and CR[2:0] Bit -- This write-only bit serves as a mask for the WCOP and CR[2:0] bits while writing the CPMUCOP register. It is intended for BDM writing the RSBCK without changing the content of WCOP and CR[2:0]. 0 Write of WCOP and CR[2:0] has an effect with this write of CPMUCOP 1 Write of WCOP and CR[2:0] has no effect with this write of CPMUCOP.
(Does not count for "write once".)

2­0 CR[2:0]

COP Watchdog Timer Rate Select -- These bits select the COP time-out rate (see Table 8-15 and Table 8-16). Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter timeout causes a System Reset. This can be avoided by periodically (before time-out) initializing the COP counter via the CPMUARMCOP register. While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at highest time-out period (2 24 cycles) in normal COP mode (Window COP mode disabled):
1) COP is enabled (CR[2:0] is not 000) 2) BDM mode active 3) RSBCK = 0 4) Operation in Special Mode

Table 8-15. COP Watchdog Rates if COPOSCSEL1=0. (default out of reset)

CR2
0 0 0 0 1 1 1 1

CR1
0 0 1 1 0 0 1 1

CR0
0 1 0 1 0 1 0 1

COPCLK Cycles to time-out (COPCLK is either IRCCLK or OSCCLK depending on the COPOSCSEL0 bit)
COP disabled
2 14
2 16
2 18
2 20
2 22
2 23
2 24

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Table 8-16. COP Watchdog Rates if COPOSCSEL1=1.

CR2
0 0 0 0 1 1 1 1

CR1
0 0 1 1 0 0 1 1

CR0
0 1 0 1 0 1 0 1

COPCLK Cycles to time-out (COPCLK is ACLK divided by 2)
COP disabled 2 7 2 9 2 11 2 13 2 15 2 16 2 17

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8.3.2.13

Reserved Register CPMUTEST0
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V10_V6's functionality.

Module Base + 0x000D

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 8-18. Reserved Register (CPMUTEST0)

Read: Anytime

Write: Only in Special Mode

8.3.2.14

Reserved Register CPMUTEST1
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V10_V6's functionality.

Module Base + 0x000E

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 8-19. Reserved Register (CPMUTEST1)

Read: Anytime Write: Only in Special Mode

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8.3.2.15 S12CPMU_UHV_V10_V6 COP Timer Arm/Reset Register (CPMUARMCOP)
This register is used to restart the COP time-out period.

Module Base + 0x000F

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

0

W ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit

7

6

5

4

3

2

1

0

Reset

0

0

0

0

0

0

0

0

Figure 8-20. S12CPMU_UHV_V10_V6 CPMUARMCOP Register

Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = "000") writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period write $55 followed by a write of $AA. These writes do not need to occur back-to-back, but the sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset. Sequences of $55 writes are allowed. When the WCOP bit is set, $55 and $AA writes must be done in the last 25% of the selected time-out period; writing any value in the first 75% of the selected period will cause a COP reset.

8.3.2.16 High Temperature Control Register (CPMUHTCTL)
The CPMUHTCTL register configures the temperature sense features.

Module Base + 0x0010

R W Reset

7
Reserved
0

6

5

4

0

VSEL

0

0

0

0

= Unimplemented or Reserved

3
HTE 0

2
HTDS
0

1
HTIE 0

Figure 8-21. High Temperature Control Register (CPMUHTCTL)

0
HTIF 0

Read: Anytime Write: VSEL, HTE, HTIE and HTIF are write anytime, HTDS is read only

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Field 5
VSEL
3 HTE
2 HTDS
1 HTIE
0 HTIF

Table 8-17. CPMUHTCTL Field Descriptions
Description
Voltage Access Select Bit -- If set, the bandgap reference voltage VBG can be accessed internally (i.e. multiplexed to an internal Analog to Digital Converter channel). If not set, the die temperature proportional voltage VHT of the temperature sensor can be accessed internally. See device level specification for connectivity. For any of these access the HTE bit must be set. 0 An internal temperature proportional voltage VHT can be accessed internally. 1 Bandgap reference voltage VBG can be accessed internally.
High Temperature Sensor/Bandgap Voltage Enable Bit -- This bit enables the high temperature sensor and bandgap voltage amplifier. 0 The temperature sensor and bandgap voltage amplifier is disabled. 1 The temperature sensor and bandgap voltage amplifier is enabled.
High Temperature Detect Status Bit -- This read-only status bit reflects the temperature status. Writes have no effect. 0 Junction Temperature is below level THTID or RPM. 1 Junction Temperature is above level THTIA and FPM.
High Temperature Interrupt Enable Bit 0 Interrupt request is disabled. 1 Interrupt will be requested whenever HTIF is set.
High Temperature Interrupt Flag -- HTIF is set to 1 when HTDS status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (HTIE=1), HTIF causes an interrupt request. 0 No change in HTDS bit. 1 HTDS bit has changed.

NOTE The voltage at the temperature sensor can be computed as follows:
VHT(temp) = VHT(150) - (150 - temp) * dVHT

Figure 8-22. Voltage Access Select

VRBeGf
C
HTD

VSEL

TEMPSENSE ADC
Channel

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8.3.2.17 Low Voltage Control Register (CPMULVCTL) The CPMULVCTL register allows the configuration of the low-voltage detect features.

Module Base + 0x0011

7

6

5

4

3

R

0

0

0

0

VDDSIE(1)

W

Reset

0

0

0

0

0

The Reset state of LVDS and LVIF depends on the external supplied VDDA level

= Unimplemented or Reserved

2
LVDS
U

1. Only available in V10

Figure 8-23. Low Voltage Control Register (CPMULVCTL)

1
LVIE 0

0
LVIF U

Read: Anytime Write: LVIE and LVIF are write anytime, LVDS is read only

Field 3
VDDSIE
2 LVDS
1 LVIE
0 LVIF

Table 8-18. CPMULVCTL Field Descriptions
Description
VDDS Integrity Interrupt Enable Bit 0 Interrupt request is disabled. 1 Interrupt will be requested on VDDS integrity fails, that means whenever one of the following flags in
CPMUVDDS register is set: SCS2IF, SCS1IF, LVS2IF, LVS1IF.
Low-Voltage Detect Status Bit -- This read-only status bit reflects the voltage level on VDDA. Writes have no effect. 0 Input voltage VDDA is above level VLVID or RPM. 1 Input voltage VDDA is below level VLVIA and FPM.
Low-Voltage Interrupt Enable Bit 0 Interrupt request is disabled. 1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag -- LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request. 0 No change in LVDS bit. 1 LVDS bit has changed.

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8.3.2.18 Autonomous Periodical Interrupt Control Register (CPMUAPICTL) The CPMUAPICTL register allows the configuration of the autonomous periodical interrupt features.

Module Base + 0x0012

R W Reset

7

6

APICLK

0

5

4

3

2

1

0

APIES

APIEA

APIFE

APIE

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 8-24. Autonomous Periodical Interrupt Control Register (CPMUAPICTL)

Read: Anytime

Write: Anytime

Table 8-19. CPMUAPICTL Field Descriptions

0
APIF 0

Field 7
APICLK
4 APIES
3 APIEA
2 APIFE
1 APIE
0 APIF

Description
Autonomous Periodical Interrupt Clock Select Bit -- Selects the clock source for the API. Writable only if APIFE = 0. APICLK cannot be changed if APIFE is set by the same write operation. 0 Autonomous Clock (ACLK) used as source. 1 Bus Clock used as source.
Autonomous Periodical Interrupt External Select Bit -- Selects the waveform at the external pin API_EXTCLK as shown in Figure 8-25. See device level specification for connectivity of API_EXTCLK pin. 0 If APIEA and APIFE are set, at the external pin API_EXTCLK periodic high pulses are visible at the end of
every selected period with the size of half of the minimum period (APIR=0x0000 in Table 8-23). 1 If APIEA and APIFE are set, at the external pin API_EXTCLK a clock is visible with 2 times the selected API
Period.
Autonomous Periodical Interrupt External Access Enable Bit -- If set, the waveform selected by bit APIES can be accessed externally. See device level specification for connectivity. 0 Waveform selected by APIES can not be accessed externally. 1 Waveform selected by APIES can be accessed externally, if APIFE is set.
Autonomous Periodical Interrupt Feature Enable Bit -- Enables the API feature and starts the API timer when set. 0 Autonomous periodical interrupt is disabled. 1 Autonomous periodical interrupt is enabled and timer starts running.
Autonomous Periodical Interrupt Enable Bit 0 API interrupt request is disabled. 1 API interrupt will be requested whenever APIF is set.
Autonomous Periodical Interrupt Flag -- APIF is set to 1 when the in the API configured time has elapsed. This flag can only be cleared by writing a 1.Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request. 0 API time-out has not yet occurred. 1 API time-out has occurred.

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Figure 8-25. Waveform selected on API_EXTCLK pin (APIEA=1, APIFE=1) API min. period / 2
APIES=0 API period
APIES=1

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8.3.2.19 Autonomous Clock Trimming Register (CPMUACLKTR) The CPMUACLKTR register configures the trimming of the Autonomous Clock (ACLK - trimmable internal RC-Oscillator) which can be selected as clock source for some CPMU features.

Module Base + 0x0013

7

6

5

4

3

2

1

0

R W

ACLKTR5

ACLKTR4

ACLKTR3

ACLKTR2

ACLKTR1

ACLKTR0

0

0

Reset

F

F

F

F

F

F

0

0

After de-assert of System Reset a value is automatically loaded from the Flash memory.

Figure 8-26. Autonomous Clock Trimming Register (CPMUACLKTR)

Read: Anytime

Write: Anytime

Table 8-20. CPMUACLKTR Field Descriptions

Field

Description

7­2

Autonomous Clock Period Trimming Bits -- See Table 8-21 for trimming effects. The ACLKTR[5:0] value

ACLKTR[5:0] represents a signed number influencing the ACLK period time.

Table 8-21. Trimming Effect of ACLKTR[5:0]

ACLKTR[5:0]
100000 100001
.... 111111 000000 000001
.... 011110 011111

Decimal -32 -31
-1 0 +1
+30 +31

ACLK frequency lowest
increasing
mid increasing
highest

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8.3.2.20 Autonomous Periodical Interrupt Rate High and Low Register (CPMUAPIRH / CPMUAPIRL)
The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical interrupt rate.

Module Base + 0x0014

R W Reset

7
APIR15 0

6
APIR14

5
APIR13

4
APIR12

0

0

0

= Unimplemented or Reserved

3
APIR11 0

2
APIR10 0

1
APIR9 0

Figure 8-27. Autonomous Periodical Interrupt Rate High Register (CPMUAPIRH)

0
APIR8 0

Module Base + 0x0015

R W Reset

7
APIR7 0

6
APIR6 0

5
APIR5 0

4
APIR4 0

3
APIR3 0

2
APIR2 0

1
APIR1 0

Figure 8-28. Autonomous Periodical Interrupt Rate Low Register (CPMUAPIRL)

0
APIR0 0

Read: Anytime Write: Anytime if APIFE=0, Else writes have no effect.
Table 8-22. CPMUAPIRH / CPMUAPIRL Field Descriptions

Field

Description

15-0

Autonomous Periodical Interrupt Rate Bits -- These bits define the time-out period of the API. See Table 8-

APIR[15:0] 23 for details of the effect of the autonomous periodical interrupt rate bits.

The period can be calculated as follows depending on logical value of the APICLK bit:
APICLK=0: Period = 2*(APIR[15:0] + 1) * (ACLK Clock Period * 2) APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock Period
NOTE For APICLK bit clear the first time-out period of the API will show a latency time between two to three fACLK cycles due to synchronous clock gate release when the API feature gets enabled (APIFE bit set).

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Table 8-23. Selectable Autonomous Periodical Interrupt Periods

APICLK

APIR[15:0]

0

0000

0

0001

0

0002

0

0003

0

0004

0

0005

0

.....

0

FFFD

0

FFFE

0

FFFF

1

0000

1

0001

1

0002

1

0003

1

0004

1

0005

1

.....

1

FFFD

1

FFFE

1

FFFF

1. When fACLK is trimmed to 20KHz.

Selected Period 0.2 ms(1) 0.4 ms1 0.6 ms1 0.8 ms1 1.0 ms1 1.2 ms1 .....
13106.8 ms1 13107.0 ms1 13107.2 ms1 2 * Bus Clock period 4 * Bus Clock period 6 * Bus Clock period 8 * Bus Clock period 10 * Bus Clock period 12 * Bus Clock period
..... 131068 * Bus Clock period 131070 * Bus Clock period 131072 * Bus Clock period

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Reserved Register CPMUTEST3
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V10_V6's functionality.

Module Base + 0x0016

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 8-29. Reserved Register (CPMUTEST3)

Read: Anytime Write: Only in Special Mode

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8.3.2.22 High Temperature Trimming Register (CPMUHTTR) The CPMUHTTR register configures the trimming of the S12CPMU_UHV_V10_V6 temperature sense.

Module Base + 0x0017

7

6

5

4

3

2

1

0

R W

HTOE

0

0

0

HTTR3

HTTR2

HTTR1

HTTR0

Reset

0

0

0

0

F

F

F

F

After de-assert of System Reset a trim value is automatically loaded from the Flash memory. See Device specification for details.

= Unimplemented or Reserved

Figure 8-30. High Temperature Trimming Register (CPMUHTTR)

Read: Anytime Write: Anytime

Table 8-25. CPMUHTTR Field Descriptions

Field

Description

7 HTOE
3­0 HTTR[3:0]

High Temperature Offset Enable Bit -- If set the temperature sense offset is enabled. 0 The temperature sense offset is disabled. HTTR[3:0] bits don't care. 1 The temperature sense offset is enabled. HTTR[3:0] select the temperature offset.
High Temperature Trimming Bits -- See Table 8-26 for trimming effects.

Table 8-26. Trimming Effect of HTTR

HTTR[3:0]
0000 0001
.... 1110 1111

Temperature sensor voltage VHT
lowest

Interrupt threshold temperatures THTIA and THTID
highest

increasing

decreasing

highest

lowest

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S12CPMU_UHV_V10_V6 IRC1M Trim Registers (CPMUIRCTRIMH / CPMUIRCTRIML)

Module Base + 0x0018

15

14

13

12

11

10

R

0

TCTRIM[4:0]

W

9

8

IRCTRIM[9:8]

Reset

F

F

F

F

F

0

F

F

After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed Internal Reference Frequency fIRC1M_TRIM.
Figure 8-31. S12CPMU_UHV_V10_V6 IRC1M Trim High Register (CPMUIRCTRIMH)

Module Base + 0x0019

7

6

5

4

3

2

1

0

R IRCTRIM[7:0]
W

Reset

F

F

F

F

F

F

F

F

After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed Internal Reference Frequency fIRC1M_TRIM.
Figure 8-32. S12CPMU_UHV_V10_V6 IRC1M Trim Low Register (CPMUIRCTRIML)

Read: Anytime

Write: Anytime if PROT=0 (CPMUPROT register). Else write has no effect

NOTE
Writes to these registers while PLLSEL=1 clears the LOCK and UPOSC status bits.

Table 8-27. CPMUIRCTRIMH/L Field Descriptions

Field

Description

15-11 TCTRIM[4:0]

IRC1M temperature coefficient Trim Bits Trim bits for the Temperature Coefficient (TC) of the IRC1M frequency. Table 8-28 shows the influence of the bits TCTRIM[4:0] on the relationship between frequency and temperature. Figure 8-34 shows an approximate TC variation, relative to the nominal TC of the IRC1M (i.e. for TCTRIM[4:0]=0x00000 or 0x10000).

9-0

IRC1M Frequency Trim Bits -- Trim bits for Internal Reference Clock

IRCTRIM[9:0] After System Reset the factory programmed trim value is automatically loaded into these registers, resulting in a

Internal Reference Frequency fIRC1M_TRIM.See device electrical characteristics for value of fIRC1M_TRIM. The frequency trimming consists of two different trimming methods:

A rough trimming controlled by bits IRCTRIM[9:6] can be done with frequency leaps of about 6% in average.

A fine trimming controlled by bits IRCTRIM[5:0] can be done with frequency leaps of about 0.3% (this trimming

determines the precision of the frequency setting of 0.15%, i.e. 0.3% is the distance between two trimming

values).

Figure 8-33 shows the relationship between the trim bits and the resulting IRC1M frequency.

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IRC1M frequency (IRCCLK) 1.5MHz

IRCTRIM[9:6]

IRCTRIM[5:0] 1MHz

......

600KHz $000

Figure 8-33. IRC1M Frequency Trimming Diagram

IRCTRIM[9:0] $3FF

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frequency

TCTRIM[4:0] = 0x11111

0x11111 ... 0x10101 0x10100 0x10011 0x10010 0x10001

TCTRIM[4:0] = 0x10000 or 0x00000 (nominal TC)

TC increases

TCTRIM[4:0] = 0x01111

0x00001 0x00010 0x00011 0x00100 0x00101 ... 0x01111

TC decreases

- 40C

150C

temperature

Figure 8-34. Influence of TCTRIM[4:0] on the Temperature Coefficient

NOTE
The frequency is not necessarily linear with the temperature (in most cases it will not be). The above diagram is meant only to give the direction (positive or negative) of the variation of the TC, relative to the nominal TC.
Setting TCTRIM[4:0] at 0x00000 or 0x10000 does not mean that the temperature coefficient will be zero. These two combinations basically switch off the TC compensation module, which results in the nominal TC of the IRC1M.

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Table 8-28. TC trimming of the frequency of the IRC1M at ambient temperature

TCTRIM[4:0]
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111

IRC1M Indicative relative TC variation
0 (nominal TC of the IRC) -0.27% -0.54% -0.81% -1.08% -1.35% -1.63% -1.9% -2.20% -2.47% -2.77% -3.04 -3.33% -3.6% -3.91% -4.18%
0 (nominal TC of the IRC) +0.27% +0.54% +0.81% +1.07% +1.34% +1.59% +1.86% +2.11% +2.38% +2.62% +2.89% +3.12% +3.39% +3.62% +3.89%

IRC1M indicative frequency drift for relative TC variation
0% -0.5% -0.9% -1.3% -1.7% -2.0% -2.2% -2.5% -3.0% -3.4% -3.9% -4.3% -4.7% -5.1% -5.6% -5.9%
0% +0.5% +0.9% +1.3% +1.7% +2.0% +2.2% +2.5% +3.0% +3.4% +3.9% +4.3% +4.7% +5.1% +5.6% +5.9%

NOTE
Since the IRC1M frequency is not a linear function of the temperature, but more like a parabola, the above relative variation is only an indication and should be considered with care.

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Be aware that the output frequency varies with the TC trimming. A frequency trimming correction is therefore necessary. The values provided in Table 8-28 are typical values at ambient temperature which can vary from device to device.

8.3.2.24 S12CPMU_UHV_V10_V6 Oscillator Register (CPMUOSC) This registers configures the external oscillator (XOSCLCP).

Module Base + 0x001A

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

OSCE

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 8-35. S12CPMU_UHV_V10_V6 Oscillator Register (CPMUOSC)

Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect.
NOTE. Write to this register clears the LOCK and UPOSC status bits.

Field
7 OSCE

Table 8-29. CPMUOSC Field Descriptions
Description
Oscillator Enable Bit -- This bit enables the external oscillator (XOSCLCP). The UPOSC status bit in the CPMIUFLG register indicates when the oscillation is stable and when OSCCLK can be selected as source of the Bus Clock or source of the COP or RTI.If the oscillator clock monitor reset is enabled (OMRE = 1 in CPMUOSC2 register), then a loss of oscillation will lead to an oscillator clock monitor reset. 0 External oscillator is disabled.
REFCLK for PLL is IRCCLK. 1 External oscillator is enabled.
Oscillator clock monitor is enabled. External oscillator is qualified by PLLCLK. REFCLK for PLL is the external oscillator clock divided by REFDIV. If OSCE bit has been set (write "1") the EXTAL and XTAL pins are exclusively reserved for the oscillator and they can not be used anymore as general purpose I/O until the next system reset.
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator tUPOSC before entering Pseudo Stop Mode.

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8.3.2.25 S12CPMU_UHV_V10_V6 Protection Register (CPMUPROT) This register protects the clock configuration registers from accidental overwrite: CPMUSYNR, CPMUREFDIV, CPMUCLKS, CPMUPLL, CPMUIRCTRIMH/L, CPMUOSC and CPMUOSC2

Module Base + 0x001B

R W Reset

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 8-36. S12CPMU_UHV_V10_V6 Protection Register (CPMUPROT)

Read: Anytime Write: Anytime

0
PROT 0

Field PROT

Description
Clock Configuration Registers Protection Bit -- This bit protects the clock configuration registers from accidental overwrite (see list of protected registers above): Writing 0x26 to the CPMUPROT register clears the PROT bit, other write accesses set the PROT bit. 0 Protection of clock configuration registers is disabled. 1 Protection of clock configuration registers is enabled. (see list of protected registers above).

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Chapter 8 S12 Clock, Reset and Power Management Unit (00.17)
Reserved Register CPMUTEST2
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V10_V6's functionality.

Module Base + 0x001C

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 8-37. Reserved Register CPMUTEST2

Read: Anytime Write: Only in Special Mode

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8.3.2.27 Voltage Regulator Control Register (CPMUVREGCTL) The CPMUVREGCTL allows to enable or disable certain parts of the voltage regulator.This register must be configured after system startup.

Module Base + 0x001D

7

6

5

4

3

R VRH2EN1 VRH1EN1 EXTS2ON1 EXTS1ON(1)

0

W

Reset

0

0

0

0

0

= Unimplemented or Reserved

2
EXTCON 1

1
EXTXON 1

Figure 8-38. Voltage Regulator Control Register (CPMUVREGCTL) 1. Only available in V10

Read: Anytime
Write: VRH2EN, VRH1EN, EXTS2ON, EXTS1ON anytime Write: EXTCON, EXTXON, INTXON once in normal modes, anytime in special modes
Table 8-30. Effects of writing the EXTXON and INTXON bits

value of

value of

EXTXON

INTXON

to be written to be written

Write Access

0

0

blocked, no effect

0

1

legal access

1

0

legal access

1

1

blocked, no effect

0
INTXON 1

Table 8-31. CPMUVREGCTL Field Descriptions

Field

Description

7 VRH2EN
6 VRH1EN
5 EXTS2ON

VRH2 Enable Bit -- This bits switches VDDS2 pin to VRH2 of ADC. 0 VRH2 of ADC disconnected (open) 1 VRH2 of ADC connected to VDDS2. In RPM VRH2 is always disconnected from VDDS2 regardless of the value of the VRH2EN bit.
VRH1 Enable Bit -- This bits switches VDDS1 pin to VRH1 of ADC. 0 VRH1 of ADC disconnected (open) 1 VRH1 of ADC connected to VDDS1. In RPM VRH1 is always disconnected from VDDS1 regardless of the value of the VRH1EN bit.
External voltage regulator Enable Bit for VDDS2 domain -- Should be enabled after system startup if VDDS2 is used. 0 VDDS2 domain disabled 1 VDDS2 domain enabled. BCTLS2 pin is active.

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Table 8-31. CPMUVREGCTL Field Descriptions (continued)

Field

Description

4 EXTS1ON
2 EXTCON
1 EXTXON
0 INTXON

External voltage regulator Enable Bit for VDDS1 domain -- Should be enabled after system startup if VDDS1 is used. 0 VDDS1 domain disabled 1 VDDS1 domain enabled. BCTLS1 pin is active.
External voltage regulator Enable Bit for VDDC domain -- Should be disabled after system startup if VDDC domain is not used. Must be kept set, if an internal or external CANPHY is present in the application. 0 VDDC domain disabled 1 VDDC domain enabled. BCTLC pin is active.
External voltage regulator Enable Bit for VDDX domain -- Should be set to 1 if external BJT is present on the PCB, cleared otherwise. 0 VDDX control loop does not use external BJT 1 VDDX control loop uses external BJT
Internal voltage regulator Enable Bit for VDDX domain-- Should be set to 1 if no external BJT is present on the PCB, cleared otherwise. 0 VDDX control loop does not use internal power transistor 1 VDDX control loop uses internal power transistor

8.3.2.28 S12CPMU_UHV_V10_V6 Oscillator Register 2 (CPMUOSC2) This registers configures the external oscillator (XOSCLCP).

Module Base + 0x001E

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

OMRE

OSCMOD

W

Reset

0

0

0

0

0

0

0

0

Figure 8-39. S12CPMU_UHV_V10_V6 Oscillator Register 2 (CPMUOSC2)

Read: Anytime

Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect.

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Table 8-32. CPMUOSC2 Field Descriptions

Field

Description

1 OMRE

This bit enables the oscillator clock monitor reset. If OSCE bit in CPMUOSC register is 1, then the OMRE bit can not be changed (writes will have no effect).
0 Oscillator clock monitor reset is disabled 1 Oscillator clock monitor reset is enabled

0 OSCMOD

This bit selects the mode of the external oscillator (XOSCLCP) If OSCE bit in CPMUOSC register is 1, then the OSCMOD bit can not be changed (writes will have no effect). 0 External oscillator configured for loop controlled mode (reduced amplitude on EXTAL and XTAL)) 1 External oscillator configured for full swing mode (full swing amplitude on EXTAL and XTAL)

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8.3.2.29 VDDS Status Register (CPMUVDDS)
This register is only available in V10.
The CPMUVDDS register contains the status and flag bits for VDDS1 and VDDS2 to indicate integrity fails. Monitoring of VDDS1 and VDDS2 domain is only active in full performance mode (FPM) and if the respective supply is enabled in CPMUVREGCTL register. It is disabled in reduced performance mode (RPM).

Module Base + 0x001F

7
R SCS2
W

6
SCS1

5
LVDS2

4
LVDS1

3
SCS2IF

Reset

0

0

U

U

0

The Reset state of LVDS and LVIF depends on the external supplied VDDA level "U" = Unknown, either 0 or 1

2
SCS1IF 0

= Unimplemented or Reserved

Figure 8-40. VDDS Status Register (CPMUVDDS)

Read: Anytime

Write: SCS2IF, SCS1IF, LVS2IF and LVS1IF are write anytime, SCS2, SCS, LVS2 and LVS1 are read only

1
LVS2IF U

0
LVS1IF U

Field 7
SCS2
6 SCS1
5 LVDS2
4 LVDS1

Table 8-33. CPMUVDDS Field Descriptions
Description
Short circuit on VDDS2 Status Bit --This read-only status bit reflects short circuit status on VDDS2 supply. This feature only makes sense if the VDDS2 supply is enabled (EXT2SON=1). 0 VRH2EN=0 or RPM or VDDS2 voltage level is less than or equal to VDDA supply. 1 VRH2EN=1and FPM and the voltage level on VDDS2 is greater than on VDDA supply.
Short circuit on VDDS1 Status Bit --This read-only status bit reflects short circuit status on VDDS1 supply. This feature only makes sense if the VDDS1 supply is enabled (EXT1SON=1). 0 VRH1EN=0 or RPM or VDDS1 voltage level is less than or equal to VDDA supply. 1 VRH1EN=1and FPM and the voltage level on VDDS1 is greater than on VDDA supply.
Low Voltage on VDDS2 Status Bit --This read-only status bit reflects the voltage level on VDDS2 supply. If VDDS2 is enabled (EXTS2ON=1 in CPMUVREGCTL register), it is monitored that VDDS2 does not drop below a voltage threshold VDDSM. 0 VDDS2 voltage is above VDDSM threshold or VDDS2 is disabled or RPM. 1 EXTS2ON =1 and VDDS2 voltage is below VDDSM threshold and FPM.
Low Voltage on VDDS1 Status Bit --This read-only status bit reflects the voltage level on VDDS1 supply. If VDDS1 is enabled (EXTS1ON=1 in CPMUVREGCTL register), it is monitored that VDDS1 does not drop below a voltage threshold VDDSM. 0 VDDS1 voltage is above VDDSM threshold or VDDS1 is disabled or RPM. 1 EXTS1ON =1 and VDDS1 voltage is below VDDSM threshold and FPM.

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Table 8-33. CPMUVDDS Field Descriptions (continued)

Field 3
SCS2IF
2 SCS1IF
1 LVS2IF
0 LVS1IF

Description
Short circuit VDDS2 Interrupt Flag -- SCS2IF is set to 1 when SCS2 status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (VDDSIE = 1), SCS2IF causes an interrupt request. 0 No change in SCS2 bit. 1 SCS2 bit has changed.
Short circuit VDDS1 Interrupt Flag -- SCS1IF is set to 1 when SCS1 status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (VDDSIE = 1), SCS1IF causes an interrupt request. 0 No change in SCS1 bit. 1 SCS1 bit has changed.
Low-Voltage VDDS2 Interrupt Flag -- LVS2IF is set to 1 when LVDS2 status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (VDDSIE = 1), LVS2IF causes an interrupt request. 0 No change in LVDS2 bit. 1 LVDS2 bit has changed.
Low-Voltage VDDS1 Interrupt Flag -- LVS1IF is set to 1 when LVDS1 status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (VDDSIE = 1), LVS1IF causes an interrupt request. 0 No change in LVDS1 bit. 1 LVDS1 bit has changed.

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8.4.1 Phase Locked Loop with Internal Filter (PLL)
The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK.
The REFCLK is by default the IRCCLK which is trimmed to fIRC1M_TRIM=1MHz.
If using the oscillator (OSCE=1) REFCLK will be based on OSCCLK. For increased flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency REFCLK using the REFDIV[3:0] bits. Based on the SYNDIV[5:0] bits the PLL generates the VCOCLK by multiplying the reference clock by a 2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2, 3, 4, 5, 6,... to 32 to generate the PLLCLK.

If oscillator is enabled (OSCE=1) If oscillator is disabled (OSCE=0)

fREF = ---R----E----F-f--O-D----S-I--V-C-----+-----1---fREF = fIRC1M

fVCO = 2  fREF  SYNDIV + 1

If PLL is locked (LOCK=1) If PLL is not locked (LOCK=0)

fPLL = ---P----O----S---f-T-V---D--C---I-O-V------+-----1---fPLL = f---V----4C-----O---

If PLL is selected (PLLSEL=1) fbus = f---P---2L----L---

.
NOTE
Although it is possible to set the dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the MCU.

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Several examples of PLL divider settings are shown in Table 8-34. The following rules help to achieve optimum stability and shortest lock time:
· Use lowest possible fVCO / fREF ratio (SYNDIV value). · Use highest possible REFCLK frequency fREF.
Table 8-34. Examples of PLL Divider Settings

fosc REFDIV[3:0] fREF REFFRQ[1:0] SYNDIV[5:0]

off

$00

1MHz

00

$18

off

$00

1MHz

00

$18

4MHz

$00

4MHz

01

$05

fVCO VCOFRQ[1:0] POSTDIV[4:0] fPLL

50MHz

01

$03

12.5MHz

50MHz

01

$00

50MHz

48MHz

00

$00

48MHz

fbus 6.25MHz 25MHz 24MHz

The phase detector inside the PLL compares the feedback clock (FBCLK = VCOCLK/(SYNDIV+1)) with the reference clock (REFCLK = (IRC1M or OSCCLK)/(REFDIV+1)). Correction pulses are generated based on the phase difference between the two signals. The loop filter alters the DC voltage on the internal filter capacitor, based on the width and direction of the correction pulse which leads to a higher or lower VCO frequency.
The user must select the range of the REFCLK frequency (REFFRQ[1:0] bits) and the range of the VCOCLK frequency (VCOFRQ[1:0] bits) to ensure that the correct PLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK and the REFCLK. Therefore the speed of the lock detector is directly proportional to the reference clock frequency. The circuit determines the lock condition based on this comparison. So e.g. a failure in the reference clock will cause the PLL not to lock.
If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and for instance check the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during PLL start-up) or at periodic intervals. In either case, only when the LOCK bit is set, the VCOCLK will have stabilized to the programmed frequency.
· The LOCK bit is a read-only indicator of the locked state of the PLL.
· The LOCK bit is set when the VCO frequency is within the tolerance, Lock, and is cleared when the VCO frequency is out of the tolerance, unl.
Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit.In case of loss of reference clock (e.g. IRCCLK) the PLL will not lock or if already locked, then it will unlock. The frequency of the VCOCLK will be very low and will depend on the value of the VCOFRQ[1:0] bits.

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8.4.2 Startup from Reset
An example for startup of the clock system from Reset is given in Figure 8-41.
Figure 8-41. Startup of clock system after Reset

RESET Pin

256 cycles fVCORST 512 cycles fVCORST

System Reset

768 cycles fVCORST

PLLCLK =

fVCORST

Core Clock

) (

Bus Clock =

Core Clock/2

) (

LOCK

fPLL increasing ) (
fBUS increasing ) (
tlock

fPLL=12.5MHz fBUS=6.25MHz

fPLL=50MHz fBUS=25MHz

SYNDIV

POSTDIV

CPU

reset state

$18 (default target fVCO=50MHz) $03 (default target fPLL=fVCO/4 = 12.5MHz)

startup nSTAfBRUTUSP cycles

vector fetch, program execution

$00 example change of POSTDIV

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8.4.3 Stop Mode using PLLCLK as source of the Bus Clock
An example of what happens going into Stop Mode and exiting Stop Mode after an interrupt is shown in Figure 8-42. Disable PLL Lock interrupt (LOCKIE=0) before going into Stop Mode.
Figure 8-42. Stop Mode using PLLCLK as source of the Bus Clock wake up

CPU execution PLLCLK LOCK

STOP instruction tSTP_REC

interrupt continue execution tlock

Depending on the COP configuration there might be an additional significant latency time until COP is active again after exit from Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details).
8.4.4 Full Stop Mode using Oscillator Clock as source of the Bus Clock
An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is shown in Figure 8-43.
Disable PLL Lock interrupt (LOCKIE=0) and oscillator status change interrupt (OSCIE=0) before going into Full Stop Mode.

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Figure 8-43. Full Stop Mode using Oscillator Clock as source of the Bus Clock wake up

CPU execution Core Clock PLLCLK OSCCLK UPOSC
PLLSEL

STOP instruction

interrupt continue execution

tSTP_REC

tlock

crystal/resonator starts oscillating

tUPOSC select OSCCLK as Core/Bus Clock by writing PLLSEL to "0"

automatically set when going into Full Stop Mode

Depending on the COP configuration there might be a significant latency time until COP is active again after exit from Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details).

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8.4.5 External Oscillator
8.4.5.1 Enabling the External Oscillator An example of how to use the oscillator as source of the Bus Clock is shown in Figure 8-44.

Figure 8-44. Enabling the external oscillator

OSCE OSCCLK UPOSC
PLLSEL Core Clock

enable external oscillator by writing OSCE bit to one.

crystal/resonator starts oscillating UPOSC flag is set upon successful start of oscillation

tUPOSC

select OSCCLK as Core/Bus Clock by writing PLLSEL to zero

based on PLL Clock

based on OSCCLK

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System Clock Configurations

8.4.6.1 PLL Engaged Internal Mode (PEI)
This mode is the default mode after System Reset or Power-On Reset.
The Bus Clock is based on the PLLCLK, the reference clock for the PLL is internally generated (IRC1M). The PLL is configured to 50 MHz VCOCLK with POSTDIV set to 0x03. If locked (LOCK=1) this results in a PLLCLK of 12.5 MHz and a Bus Clock of 6.25 MHz. The PLL can be re-configured to other bus frequencies.
The clock sources for COP and RTI can be based on the internal reference clock generator (IRC1M) or the RC-Oscillator (ACLK).

8.4.6.2 PLL Engaged External Mode (PEE)
In this mode, the Bus Clock is based on the PLLCLK as well (like PEI). The reference clock for the PLL is based on the external oscillator.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock or the RC-Oscillator (ACLK).
This mode can be entered from default mode PEI by performing the following steps: 1. Configure the PLL for desired bus frequency. 2. Enable the external Oscillator (OSCE bit). 3. Wait for oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1). 4. Clear all flags in the CPMUIFLG register to be able to detect any future status bit change. 5. Optionally status interrupts can be enabled (CPMUINT register).
Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).
The impact of loosing the oscillator status (UPOSC=0) in PEE mode is as follows: · The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again.
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any time.

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8.4.6.3 PLL Bypassed External Mode (PBE)
In this mode, the Bus Clock is based on the external oscillator clock. The reference clock for the PLL is based on the external oscillator.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock or the RC-Oscillator (ACLK).
This mode can be entered from default mode PEI by performing the following steps: 1. Make sure the PLL configuration is valid. 2. Enable the external Oscillator (OSCE bit) 3. Wait for the oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1) 4. Clear all flags in the CPMUIFLG register to be able to detect any status bit change. 5. Optionally status interrupts can be enabled (CPMUINT register). 6. Select the Oscillator clock as source of the Bus clock (PLLSEL=0)
Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).
The impact of loosing the oscillator status (UPOSC=0) in PBE mode is as follows: · PLLSEL is set automatically and the Bus clock source is switched back to the PLL clock. · The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again.
NOTEApplication software needs to be prepared to deal with the impact of loosing the oscillator status at any time.
When using the oscillator clock as system clock (write PLLSEL = 0) it is highly recommended to enable the oscillator clock monitor reset feature (write OMRE = 1 in CPMUOSC2 register). If the oscillator monitor reset feature is disabled (OMRE = 0) and the oscillator clock is used as system clock, the system might stall in case of loss of oscillation.

8.5 Resets

8.5.1 General

All reset sources are listed in Table 8-35. There is only one reset vector for all these reset sources. Refer to MCU specification for reset vector address.
Table 8-35. Reset Summary

Reset Source
Power-On Reset (POR) Low Voltage Reset (LVR)
External pin RESET PLL Clock Monitor Reset

Local Enable
None None None None

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Table 8-35. Reset Summary

Reset Source Oscillator Clock Monitor Reset
COP Reset

Local Enable
OSCE Bit in CPMUOSC register and OMRE Bit in CPMUOSC2 register CR[2:0] in CPMUCOP register

8.5.2 Description of Reset Operation
Upon detection of any reset of Table 8-35, an internal circuit drives the RESET pin low for 512 PLLCLK cycles. After 512 PLLCLK cycles the RESET pin is released. The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK cycles long reset sequence.In case the RESET pin is externally driven low for more than these 768 PLLCLK cycles (External Reset), the internal reset remains asserted longer.
NOTE
While System Reset is asserted the PLLCLK runs with the frequency fVCORST.

RESET PLLCLK

Figure 8-45. RESET Timing

S12_CPMU drives

S12_CPMU releases

RESET pin low

RESET pin

fVCORST fVCORST

)

)

)

(

(

(

512 cycles

256 cycles
possibly RESET driven low

8.5.3 Oscillator Clock Monitor Reset
If the external oscillator is enabled (OSCE=1)and the oscillator clock monitor reset is enabled (OMRE=1), then in case of loss of oscillation or the oscillator frequency drops below the failure assert frequency fCMFA (see device electrical characteristics for values), the S12CPMU_UHV_V10_V6 generates an Oscillator Clock Monitor Reset. In Full Stop Mode the external oscillator and the oscillator clock monitor are disabled.

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8.5.4 PLL Clock Monitor Reset
In case of loss of PLL clock oscillation or the PLL clock frequency is below the failure assert frequency fPMFA (see device electrical characteristics for values), the S12CPMU_UHV_V10_V6 generates a PLL Clock Monitor Reset. In Full Stop Mode the PLL and the PLL clock monitor are disabled.

8.5.5 Computer Operating Properly Watchdog (COP) Reset
The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping the COP from timing out. If the COP times out it is an indication that the software is no longer being executed in the intended sequence; thus COP reset is generated.
The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the COPOSCSEL0 and COPOSCSEL1 bit.
Depending on the COP configuration there might be a significant latency time until COP is active again after exit from Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details).
Table 8-36 gives an overview of the COP condition (run, static) in Stop Mode depending on legal configuration and status bit settings:
Table 8-36. COP condition (run, static) in Stop Mode

COPOSCSEL1 CSAD PSTP PCE COPOSCSEL0 OSCE

1

0

x

x

x

x

1

1

x

x

x

x

0

x

1

1

1

1

0

x

1

1

0

0

0

x

1

1

0

1

0

x

1

0

0

x

0

x

1

0

1

1

0

x

0

1

1

1

0

x

0

1

0

1

0

x

0

1

0

0

0

x

0

0

1

1

0

x

0

0

0

1

0

x

0

0

0

1

0

x

0

0

0

0

UPOSC
x x 1 x x x 1 1 x 0 1 1 0 0

COP counter behavior in Stop Mode (clock source)
Run (ACLK) Static (ACLK) Run (OSCCLK) Static (IRCCLK) Static (IRCCLK) Static (IRCCLK) Static (OSCCLK) Static (OSCCLK) Static (IRCCLK) Static (IRCCLK) Satic (OSCCLK) Static (IRCCLK) Static (IRCCLK) Static (IRCCLK)

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Three control bits in the CPMUCOP register allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this order) to the CPMUARMCOP register during the selected time-out period. Once this is done, the COP time-out period is restarted. If the program fails to do this and the COP times out, a COP reset is generated. Also, if any value other than $55 or $AA is written, a COP reset is generated.
Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to the CPMUARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period. A premature write will immediately reset the part.
In MCU Normal Mode the COP time-out period (CR[2:0]) and COP window (WCOP) setting can be automatically pre-loaded at reset release from NVM memory (if values are defined in the NVM by the application). By default the COP is off and no window COP feature is enabled after reset release via NVM memory. The COP control register CPMUCOP can be written once in an application in MCU Normal Mode to update the COP time-out period (CR[2:0]) and COP window (WCOP) setting loaded from NVM memory at reset release. Any value for the new COP time-out period and COP window setting is allowed except COP off value if the COP was enabled during pre-load via NVM memory. The COP clock source select bits can not be pre-loaded via NVM memory at reset release. The IRC clock is the default COP clock source out of reset. The COP clock source select bits (COPOSCSEL0/1) and ACLK clock control bit in Stop Mode (CSAD) can be modified until the CPMUCOP register write once has taken place. Therefore these control bits should be modified before the final COP time-out period and window COP setting is written. The CPMUCOP register access to modify the COP time-out period and window COP setting in MCU Normal Mode after reset release must be done with the WRTMASK bit cleared otherwise the update is ignored and this access does not count as the write once.
8.5.6 Power-On Reset (POR)
The on-chip POR circuitry detects when the internal supply VDD drops below an appropriate voltage level. The POR is deasserted, if the internal supply VDD exceeds an appropriate voltage level (voltage levels not specified, because the internal supply can not be monitored externally).The POR circuitry is always active. It acts as LVR in Stop Mode.
8.5.7 Low-Voltage Reset (LVR)
The on-chip LVR circuitry detects when one of the supply voltages VDD, VDDX and VDDF drops below an appropriate voltage level. If LVR is deasserted the MCU is fully operational at the specified maximum speed. The LVR assert and deassert levels for the supply voltage VDDX are VLVRXA and VLVRXD and are specified in the device Reference Manual.The LVR circuitry is active in Run- and Wait Mode.

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8.6 Interrupts
The interrupt vectors requested by the S12CPMU_UHV_V10_V6 are listed in Table 8-37. Refer to MCU specification for related vector addresses and priorities.

Table 8-37. S12CPMU_UHV_V10_V6 Interrupt Vectors

Interrupt Source
RTI time-out interrupt PLL lock interrupt
Oscillator status interrupt Low voltage interrupt
VDDS integrity interrupt(1) High temperature interrupt
Autonomous Periodical Interrupt
1. Only available in V10

CCR Mask
I bit I bit I bit I bit I bit I bit I bit

Local Enable
CPMUINT (RTIE) CPMUINT (LOCKIE) CPMUINT (OSCIE) CPMULVCTL (LVIE) CPMULVCTL (VDDSIE) CPMUHTCTL (HTIE) CPMUAPICTL (APIE)

8.6.1 Description of Interrupt Operation
8.6.1.1 Real Time Interrupt (RTI)
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), RTIOSCSEL=1 and PRE=1 the RTI continues to run, else the RTI counter halts in Stop Mode.
The RTI can be used to generate hardware interrupts at a fixed periodic rate. If enabled (by setting RTIE=1), this interrupt will occur at the rate selected by the CPMURTI register. At the end of the RTI timeout period the RTIF flag is set to one and a new RTI time-out period starts immediately.
A write to the CPMURTI register restarts the RTI time-out period.
8.6.1.2 PLL Lock Interrupt
The S12CPMU_UHV_V10_V6 generates a PLL Lock interrupt when the lock condition (LOCK status bit) of the PLL changes, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to zero. The PLL Lock interrupt flag (LOCKIF) is set to1 when the lock condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
8.6.1.3 Oscillator Status Interrupt
When the OSCE bit is 0, then UPOSC stays 0. When OSCE=1 the UPOSC bit is set after the LOCK bit is set.

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Upon detection of a status change (UPOSC) the OSCIF flag is set. Going into Full Stop Mode or disabling the oscillator can also cause a status change of UPOSC.
Any change in PLL configuration or any other event which causes the PLL lock status to be cleared leads to a loss of the oscillator status information as well (UPOSC=0).
Oscillator status change interrupts are locally enabled with the OSCIE bit.
NOTE Loosing the oscillator status (UPOSC=0) affects the clock configuration of the system1. This needs to be dealt with in application software.

8.6.1.4 Low-Voltage Interrupt (LVI)
In FPM the input voltage VDDA is monitored. Whenever VDDA drops below level VLVIA, the status bit LVDS is set to 1. When VDDA rises above level VLVID the status bit LVDS is cleared to 0. An interrupt, indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE = 1.

8.6.1.5 VDDS Integrity Interrupt
This interrupt is only available in V10.
In FPM the input voltages VDDS1 and VSS2 are monitored for integrity. The flags in CPMUVDDS register indicate such a failing condition. When one the status bits changes, the respective flag is set in CPMUVDDS register. If interrupt is enabled (VDDSIE = 1) an interrupt is triggered by any of these flags.
See CPMUVDDS register description for details.

8.6.1.6 HTI - High Temperature Interrupt In FPM the junction temperature TJ is monitored. Whenever TJ exceeds level THTIA the status bit HTDS is set to 1. Vice versa, HTDS is reset to 0 when TJ get below level THTID. An interrupt, indicated by flag HTIF = 1, is triggered by any change of the status bit HTDS, if interrupt enable bit HTIE = 1.

8.6.1.7 Autonomous Periodical Interrupt (API)
The API sub-block can generate periodical interrupts independent of the clock source of the MCU. To enable the timer, the bit APIFE needs to be set.
The API timer is either clocked by the Autonomous Clock (ACLK - trimmable internal RC oscillator) or the Bus Clock. Timer operation will freeze when MCU clock source is selected and Bus Clock is turned off. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is not set.
The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE is cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. When the configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggered if interrupt enable bit APIE = 1. The timer is re-started automatically again after it has set APIF.
1. For details please refer to "8.4.6 System Clock Configurations"

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The procedure to change APICLK or APIR[15:0] is first to clear APIFE, then write to APICLK or APIR[15:0], and afterwards set APIFE.
The API Trimming bits ACLKTR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired.
See Table 8-21 for the trimming effect of ACLKTR[5:0].
NOTE The first period after enabling the counter by APIFE might be reduced by API start up delay tsdel. It is possible to generate with the API a waveform at the external pin API_EXTCLK by setting APIFE and enabling the external access with setting APIEA.
8.7 Initialization/Application Information
8.7.1 General Initialization Information
Usually applications run in MCU Normal Mode.
It is recommended to write the CPMUCOP register in any case from the application program initialization routine after reset no matter if the COP is used in the application or not, even if a configuration is loaded via the flash memory after reset. By doing a "controlled" write access in MCU Normal Mode (with the right value for the application) the write once for the COP configuration bits (WCOP,CR[2:0]) takes place which protects these bits from further accidental change. In case of a program sequencing issue (code runaway) the COP configuration can not be accidentally modified anymore.
8.7.2 Application information for COP and API usage
In many applications the COP is used to check that the program is running and sequencing properly. Often the COP is kept running during Stop Mode and periodic wake-up events are needed to service the COP on time and maybe to check the system status.
For such an application it is recommended to use the ACLK as clock source for both COP and API. This guarantees lowest possible IDD current during Stop Mode. Additionally it eases software implementation using the same clock source for both, COP and API.
The Interrupt Service Routine (ISR) of the Autonomous Periodic Interrupt API should contain the write instruction to the CPMUARMCOP register. The value (byte) written is derived from the "main routine" (alternating sequence of $55 and $AA) of the application software.
Using this method, then in the case of a runtime or program sequencing issue the application "main routine" is not executed properly anymore and the alternating values are not provided properly. Hence the COP is written at the correct time (due to independent API interrupt request) but the wrong value is written (alternating sequence of $55 and $AA is no longer maintained) which causes a COP reset.
If the COP is stopped during any Stop Mode it is recommended to service the COP shortly before Stop Mode is entered.

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8.7.3 Application Information for PLL and Oscillator Startup
The following C-code example shows a recommended way of setting up the system clock system using the PLL and Oscillator:

/* Procedure proposed by to setup PLL and Oscillator */ /* example for OSC = 4 MHz and Bus Clock = 25MHz, That is VCOCLK = 50MHz */
/* Initialize */ /* PLL Clock = 50 MHz, divide by one */ CPMUPOSTDIV = 0x00;
/* Generally: Whenever changing PLL reference clock (REFCLK) frequency to a higher value */ /* it is recommended to write CPMUSYNR = 0x00 in order to stay within specified */ /* maximum frequency of the MCU */ CPMUSYNR = 0x00;
/* configure PLL reference clock (REFCLK) for usage with Oscillator */ /* OSC=4MHz divide by 4 (3+1) = 1MHz, REFCLK range 1MHz to 2 MHz (REFFRQ[1:0] = 00) */ CPMUREFDIV = 0x03;
/* enable external Oscillator, switch PLL reference clock (REFCLK) to OSC */ CPMUOSC = 0x80;
/* multiply REFCLK = 1MHz by 2*(24+1)*1MHz = 50MHz */ /* VCO range 48 to 80 MHz (VCOFRQ[1:0] = 01) */ CPMUSYNR = 0x58;
/* clear all flags, especially LOCKIF and OSCIF */ CPMUIFLG = 0xFF;
/* put your code to loop and wait for the LOCKIF and OSCIF or */ /* poll CPMUIFLG register until both UPOSC and LOCK status are "1" */ /* that is CPMUIFLG == 0x1B */
/*...............continue to your main code execution here...............*/
/* in case later in your code you want to disable the Oscillator and use the */ /* 1MHz IRCCLK as PLL reference clock */
/* Generally: Whenever changing PLL reference clock (REFCLK) frequency to a higher value */ /* it is recommended to write CPMUSYNR = 0x00 in order to stay within specified */ /* maximum frequency of the MCU */ CPMUSYNR = 0x00;
/* disable OSC and switch PLL reference clock to IRC */ CPMUOSC = 0x00;
/* multiply REFCLK = 1MHz by 2*(24+1)*1MHz = 50MHz */ /* VCO range 48 to 80 MHz (VCOFRQ[1:0] = 01) */ CPMUSYNR = 0x58;
/* clear all flags, especially LOCKIF and OSCIF */ CPMUIFLG = 0xFF;

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/* put your code to loop and wait for the LOCKIF or */ /* poll CPMUIFLG register until both LOCK status is "1" */ /* that is CPMUIFLG == 0x18 */ /*...............continue to your main code execution here...............*/

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Revision Revision

Number

Date

V1.37 19. Apr 2013

V1.38 30. Apr 2013

V1.39 02. Jul 2013

Table 9-1. Revision History

Sections Affected -
9.5.2.13/9-389 9.5.2.6/9-378

Description of Changes
Updates from review of reference manual to fix typos etc. Provided more detailed information regarding captured information in bits RIDX_IMD[5:0] for different scenarios of Sequence Abort Event execution. Update of: Timing considerations for Restart Mode

V1.40 02. Oct 2013

V2.00 14. Oct. 2014

V3.00 V3.01

27. Feb. 2015 15. Oct 2015

entire document
9.3/9-363, 9.5.2.15/9-392, 9.5.2.17/9-397, Figure 9-2./9-367,
9.5.2.16/9-395, 9.1/9-361
9.5.2.16/9-395

Updated formatting and wording correction for entire document (for technical publications).
Added option bits to conversion command for top level SoC specific feature/function implementation option.
Changed ADCCMD_1 VRH_SEL, VRL_SEL Single document for all versions (V1,V2,V3) Added clarification: CMD_EIF not set for internal channels

9.1 Differences ADC12B_LBA V1 vs V2 vs V3

NOTE
Device reference manuals specify which module version is integrated on the device. Some reference manuals support families of devices, with device dependent module versions. This chapter describes the superset. The feature differences are listed in Table 9-2.

Table 9-2. Comparison of ADC12B_LBA Module Versions

Feature

V1

V2

V3

ADC Command Register 0 (ADCCMD_0), ADC Command Register 2 (ADCCMD_2): OPT[3:0] bits

No

Yes

Yes

ADC Command Register 1 (ADCCMD_1):VRH_SEL[1:0]

No

No

Yes

ADC Command Register 1 (ADCCMD_1):VRH_SEL,VRL_SEL

Yes

Yes

No

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9.2 Introduction
The ADC12B_LBA is an n-channel multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ADC parameters and accuracy.
The List Based Architecture (LBA) provides flexible conversion sequence definition as well as flexible oversampling. The order of channels to be converted can be freely defined. Also, multiple instantiations of the module can be triggered simultaneously (matching sampling point across multiple module instantiations).
There are four register bits which control the conversion flow (please refer to the description of register ADCFLWCTL). The four conversion flow control bits of register ADCFLWCTL can be modified in two different ways:
· Via data bus accesses · Via internal interface Signals (Trigger, Restart, LoadOK, and Seq_Abort; see also Figure 9-2).
Each Interface Signal is associated with one conversion flow control bit.
For information regarding internal interface connectivity related to the conversion flow control please refer to the device overview of the reference manual.
The ADCFLWCTL register can be controlled via internal interface only or via data bus only or by both depending on the register access configuration bits ACC_CFG[1:0].
The four bits of register ADCFLWCTL reflect the captured request and status of the four internal interface Signals (LoadOK, Trigger, Restart, and Seq_abort; see also Figure 9-2) if access configuration is set accordingly and indicate event progress (when an event is processed and when it is finished).
Conversion flow error situations are captured by corresponding interrupt flags in the ADCEIF register.
There are two conversion flow control modes (Restart Mode, Trigger Mode). Each mode causes a certain behavior of the conversion flow control bits which can be selected according to the application needs.
Please refer to Section 9.5.2.1, "ADC Control Register 0 (ADCCTL_0) and Section 9.6.3.2.4, "The two conversion flow control Mode Configurations for more information regarding conversion flow control.
Because internal components of the ADC are turned on/off with bit ADC_EN, the ADC requires a recovery time period (tREC) after ADC is enabled until the first conversion can be launched via a trigger.
When bit ADC_EN gets cleared (transition from 1'b1 to 1'b0) any ongoing conversion sequence will be aborted and pending results, or the result of current conversion, gets discarded (not stored). The ADC cannot be re-enabled before any pending action or action in process is finished respectively aborted, which could take up to a maximum latency time of tDISABLE (see device level specification for more details).

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9.3 Key Features
· Programmer's Model with List Based Architecture for conversion command and result value organization
· Selectable resolution of 8-bit, 10-bit, or 12-bit · Channel select control for n external analog input channels · Provides up to eight device internal channels (please see the device reference manual for
connectivity information and Figure 9-2) · Programmable sample time · A sample buffer amplifier for channel sampling (improved performance in view to influence of
channel input path resistance versus conversion accuracy) · Left/right justified result data · Individual selectable VRH_0/1 and VRL_0/1 inputs (ADC12B_LBA V1 and V2) or VRH_0/1/2
inputs (ADC12B_LBA V3) on a conversion command basis (please see Figure 9-2, Table 9-2) · Special conversions for selected VRH_0/1 (V1 and V2) or VRH_0/1/2 (V3), VRL_0/1 (V1 and
V2) or VRL_0 (V3), (VRL_0/1 + VRH_0/1) / 2 (V1 and V2) or (VRL_0 + VRH_0/1/2) / 2 (V3) (please see Table 9-2) · 15 conversion interrupts with flexible interrupt organization per conversion result · One dedicated interrupt for "End Of List" type commands · Command Sequence List (CSL) with a maximum number of 64 command entries · Provides conversion sequence abort · Restart from top of active Command Sequence List (CSL) · The Command Sequence List and Result Value List are implemented in double buffered manner (two lists in parallel for each function) · Conversion Command (CSL) loading possible from System RAM or NVM · Single conversion flow control register with software selectable access path · Two conversion flow control modes optimized to different application use cases · Four option bits in the conversion command for top level SoC specific feature/function implementation option (Please refer to the device reference manual for details of the top level feature/function if implemented)

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9.3.1 Modes of Operation
9.3.1.1 Conversion Modes
This architecture provides single, multiple, or continuous conversion on a single channel or on multiple channels based on the Command Sequence List.
9.3.1.2 MCU Operating Modes
· MCU Stop Mode Before issuing an MCU Stop Mode request the ADC should be idle (no conversion or conversion sequence or Command Sequence List ongoing). If a conversion, conversion sequence, or CSL is in progress when an MCU Stop Mode request is issued, a Sequence Abort Event occurs automatically and any ongoing conversion finish. After the Sequence Abort Event finishes, if the STR_SEQA bit is set (STR_SEQA=1), then the conversion result is stored and the corresponding flags are set. If the STR_SEQA bit is cleared (STR_SEQA=0), then the conversion result is not stored and the corresponding flags are not set. The microcontroller then enters MCU Stop Mode without SEQAD_IF being set. Alternatively, the Sequence Abort Event can be issued by software before an MCU Stop Mode request. As soon as flag SEQAD_IF is set the MCU Stop Mode request can be is issued. With the occurrence of the MCU Stop Mode Request until exit from Stop Mode all flow control signals (RSTA, SEQA, LDOK, TRIG) are cleared.
After exiting MCU Stop Mode, the following happens in the order given with expected event(s) depending on the conversion flow control mode: -- In ADC conversion flow control mode "Trigger Mode" a Restart Event is expected to
simultaneously set bits TRIG and RSTA, causing the ADC to execute the Restart Event (CMD_IDX and RVL_IDX cleared) followed by the Trigger Event. The Restart Event can be generated automatically after exit from MCU Stop Mode if bit AUT_RSTA is set. -- In ADC conversion flow control mode "Restart Mode", a Restart Event is expected to set bit RSTA only (ADC already aborted at MCU Stop Mode entry hence bit SEQA must not be set simultaneously) causing the ADC to execute the Restart Event (CDM_IDX and RVL_IDX cleared). The Restart Event can be generated automatically after exit from MCU Stop Mode if bit AUT_RSTA is set. -- The RVL buffer select (RVL_SEL) is not changed if a CSL is in process at MCU Stop Mode request. Hence the same buffer will be used after exit from Stop Mode that was used when the Stop Mode request occurred.

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· MCU Wait Mode Depending on the ADC Wait Mode configuration bit SWAI, the ADC either continues conversion in MCU Wait Mode or freezes conversion at the next conversion boundary before MCU Wait Mode is entered.
ADC behavior for configuration SWAI =1'b0: The ADC continues conversion during Wait Mode according to the conversion flow control sequence. It is assumed that the conversion flow control sequence is continued (conversion flow control bits TRIG, RSTA, SEQA, and LDOK are serviced accordingly).
ADC behavior for configuration SWAI = 1'b1: At MCU Wait Mode request the ADC should be idle (no conversion or conversion sequence or Command Sequence List ongoing). If a conversion, conversion sequence, or CSL is in progress when an MCU Wait Mode request is issued, a Sequence Abort Event occurs automatically and any ongoing conversion finish. After the Sequence Abort Event finishes, if the STR_SEQA bit is set (STR_SEQA=1), then the conversion result is stored and the corresponding flags are set. If the STR_SEQA bit is cleared (STR_SEQA=0), then the conversion result is not stored and the corresponding flags are not set. Alternatively the Sequence Abort Event can be issued by software before MCU Wait Mode request. As soon as flag SEQAD_IF is set, the MCU Wait Mode request can be issued. With the occurrence of the MCU Wait Mode request until exit from Wait Mode all flow control signals (RSTA, SEQA, LDOK, TRIG) are cleared. After exiting MCU Wait Mode, the following happens in the order given with expected event(s) depending on the conversion flow control mode:
-- In ADC conversion flow control mode "Trigger Mode", a Restart Event is expected to occur. This simultaneously sets bit TRIG and RSTA causing the ADC to execute the Restart Event (CMD_IDX and RVL_IDX cleared) followed by the Trigger Event. The Restart Event can be generated automatically after exit from MCU Wait Mode if bit AUT_RSTA is set.
-- In ADC conversion flow control mode "Restart Mode", a Restart Event is expected to set bit RSTA only (ADC already aborted at MCU Wait Mode entry hence bit SEQA must not be set simultaneously) causing the ADC to execute the Restart Event (CDM_IDX and RVL_IDX cleared). The Restart Event can be generated automatically after exit from MCU Wait Mode if bit AUT_RSTA is set.
-- The RVL buffer select (RVL_SEL) is not changed if a CSL is in process at MCU Wait Mode request. Hence the same RVL buffer will be used after exit from Wait Mode that was used when Wait Mode request occurred.

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NOTE
In principle, the MCU could stay in Wait Mode for a shorter period of time than the ADC needs to abort an ongoing conversion (range of µµµµs). Therefore in case a Sequence Abort Event is issued automatically due to MCU Wait Mode request a following Restart Event after exit from MCU Wait Mode can not be executed before ADC has finished this Sequence Abort Event. The Restart Event is detected but it is pending. This applies in case MCU Wait Mode is exited before ADC has finished the Sequence Abort Event and a Restart Event is issued immediately after exit from MCU Wait Mode. Bit READY can be used by software to detect when the Restart Event can be issued without latency time in processing the event (see also Figure 9-1).

Wait Mode request (SWAI=1'b1), Automatic Sequence Abort Event Wake-up Event

Begin from top of current CSL

Restart Event

Trigger

CSL_0

AN3 AN1 AN4 IN5 AN6 AN1

AN3 AN1 AN4 AN5 AN2 AN0

Sequence_n Active

Wait Mode entry Abort

Sequence_0

Sequence_1

READY=1'b1

EOS

Earliest point of time to issue Restart Event without latency

Idle

Active

t

Figure 9-1. Conversion Flow Control Diagram - Wait Mode (SWAI=1'b1, AUT_RSTA=1'b0)

· MCU Freeze Mode Depending on the ADC Freeze Mode configuration bit FRZ_MOD, the ADC either continues conversion in Freeze Mode or freezes conversion at next conversion boundary before the MCU Freeze Mode is entered. After exit from MCU Freeze Mode with previously frozen conversion sequence the ADC continues the conversion with the next conversion command and all ADC interrupt flags are unchanged during MCU Freeze Mode.

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9.3.2 Block Diagram

System Clock Data Bus

Clock Prescaler
(EN)

ADC Clock

LoadOK Trigger Restart Seq_abort

Control Unit (Conversion Flow, Timing, Interrupt)

Error handler

Error/ FlowCtrl Issue Int.

Option Bits Sequence Abort Int.
Conversion Int.

see reference manual for connectivity information regarding ADC internal interface
Internal_7 Internal_6 Internal_5 Internal_4 Internal_3 Internal_2
VREG_sense

ADC Temperature
Sense
int. Channel
MUX

DMA access

Comm_0

Comm_1

.......... .......... ........... .......... ...........

Idle/
Active Command Sequence Alternative-

...........

List

Command

........... ...........

(RAM/ NVM)

Sequence List

...........

(RAM/

Comm 63

NVM)

VRH_2 (V3) VRH_1 VRH_0
VRL_1 (V1, V2) VRL_0
VDDA VSSA
ANx ..... AN2 AN1 AN0

Successive Approximation Register (SAR)
and C-DAC

DMA access

Result_0

Result_1

..........

active

.......... Conversion

........... Result List

.......... ...........

(RAM)

...........
........... ...........

Alternative Result

...........

List

Result 63

(RAM)

Final

ext. Channel
MUX
PIM

+ Buffer
- AMP

Buffer

Sample & Hold ADC12B_LBA

Figure 9-2. ADC12B_LBA Block Diagram

+
Comparator

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Chapter 9 Analog-to-Digital Converter (ADC12B_LBA)
9.4 Signal Description
This section lists all inputs to the ADC12B_LBA block.
9.4.1 Detailed Signal Descriptions
9.4.1.1 ANx (x = n,..., 2, 1, 0) This pin serves as the analog input Channel x. The maximum input channel number is n. Please refer to the device reference manual for the maximum number of input channels.
9.4.1.2 VRH_0, VRH_1, VRH_2, VRL_0, VRL_1 VRH_0/1/2 are the high reference voltages, VRL0/1 are the low reference voltages for a ADC conversion selectable on a conversion command basis. Please refer to the device overview information for availability and connectivity of these pins. VRH_2 is only available on ADC12B_LBA V3. VRL_1 is only available on ADC12B_LBA V1 and V2. See also Table 9-2.
9.4.1.3 VDDA, VSSA These pins are the power supplies for the analog circuitry of the ADC12B_LBA block.

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Chapter 9 Analog-to-Digital Converter (ADC12B_LBA)
9.5 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ADC12B_LBA.

9.5.1 Module Memory Map
Figure 9-3 gives an overview of all ADC12B_LBA registers.
NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level.

Address Name

Bit 7

6

5

4

3

2

0x0000

ADCCTL_0

R W

ADC_EN

ADC_SR FRZ_MOD

SWAI

ACC_CFG[1:0]

0x0001

ADCCTL_1

R CSL_BMO RVL_BMO SMOD_AC AUT_RST

W

D

D

C

A

0

0

0x0002

ADCSTS

R CSL_SEL

RVL_SEL

DBECC_E RR

Reserved

READY

0

W

0x0003

ADCTIM

R W

0

PRS[6:0]

0x0004

ADCFMT

R W

DJM

0

0

0

0

0x0005

ADCFLWCTL

R W

SEQA

TRIG

RSTA

LDOK

0

0

0x0006

ADCEIE

R W

IA_EIE

CMD_EIE

EOL_EIE

Reserved

TRIG_EIE

RSTAR_EI E

0x0007

ADCIE

R W

SEQAD_IE

CONIF_OI E

Reserved

0

0

0

0x0008

ADCEiF

R W

IA_EIF

CMD_EIF

EOL_EIF

Reserved

TRIG_EIF

RSTAR_EI F

0x0009

ADCIF

R W

SEQAD_IF

CONIF_OI F

Reserved

0

0

0

0x000A

ADCCONIE_0

R W

CON_IE[15:8]

0x000B

ADCCONIE_1

R W

CON_IE[7:1]

0x000C

ADCCONIF_0

R W

CON_IF[15:8]

0x000D

ADCCONIF_1

R W

CON_IF[7:1]

0x000E ADCIMDRI_0 R CSL_IMD RVL_IMD

0

0

0

0

1 STR_SEQ
A 0 0
SRES[2:0] 0
LDOK_EIE 0
LDOK_EIF 0
0

Bit 0 MOD_CFG
0 0
0 0 0 0 0
EOL_IE
EOL_IF 0

0x000F

ADCIMDRI_1

R W

0

0

RIDX_IMD[5:0]

= Unimplemented or Reserved Figure 9-3. ADC12B_LBA Register Summary (Sheet 1 of 3)

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Address 0x0010 0x0011 0x0012 0x0013 0x0014 0x0014 0x0015 0x0015 0x0016 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 0x0021 0x0022 0x0023

Name ADCEOLRI
Reserved
Reserved
Reserved ADCCMD_0
(V1) ADCCMD_0
(V2, V3) ADCCMD_1
(V1, V2) ADCCMD_1
(V3) ADCCMD_2
(V1) ADCCMD_2
(V2, V3) ADCCMD_3
Reserved
Reserved
Reserved
Reserved
ADCCIDX
ADCCBP_0
ADCCBP_1
ADCCBP_2
ADCRIDX
ADCRBP_0
ADCRBP_1
ADCRBP_2

Bit 7

6

R CSL_EOL RVL_EOL

W

R

0

0

W

R

0

0

W

R Reserved

W

R W

CMD_SEL

R W

CMD_SEL

R W

VRH_SEL

VRL_SEL

R W

VRH_SEL[1:0]

R

W

R

W

R W

Reserved

Reserved

R

W

R

W

R

W

R

W

R

0

0

W

R

W

R

W

R

W

R

0

0

W

R

0

0

W

R

W

R

W

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Reserved

0

0

0

INTFLG_SEL[3:0]

OPT[1:0]

INTFLG_SEL[3:0]

CH_SEL[5:0]

SMP[4:0]

CH_SEL[5:0]

0

0

SMP[4:0]

OPT[3:2]

Reserved

Reserved

Reserved

Reserved

Reserved CMD_IDX[5:0]

CMD_PTR[23:16]

CMD_PTR[15:8]

CMD_PTR[7:2]

0

RES_IDX[5:0]

0

0

RES_PTR[19:16]

RES_PTR[15:8]

RES_PTR[7:2]

0

= Unimplemented or Reserved Figure 9-3. ADC12B_LBA Register Summary (Sheet 2 of 3)

Bit 0 0 0 0 0
Reserved Reserved
0
0

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Address Name

Bit 7

6

0x0024

ADCCROFF0

R W

0

0x0025

ADCCROFF1

R W

0

0x0026

Reserved

R W

0

0

0x0027

Reserved

R W

0x0028

Reserved

R W

0x0029

Reserved

R Reserved W

0

0x002A0x003F

Reserved

R W

0

0

5

4

3

2

1

CMDRES_OFF0[6:0]

CMDRES_OFF1[6:0]

0

0

Reserved

Reserved

Reserved

0

Reserved

0

0

0

0

0

= Unimplemented or Reserved Figure 9-3. ADC12B_LBA Register Summary (Sheet 3 of 3)

Bit 0
0 0

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9.5.2 Register Descriptions
This section describes in address order all the ADC12B_LBA registers and their individual bits.

9.5.2.1 ADC Control Register 0 (ADCCTL_0)

Module Base + 0x0000

R W Reset

15
ADC_EN 0

Read: Anytime

14
ADC_SR

13
FRZ_MOD

12
SWAI

11

10

ACC_CFG[1:0]

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-4. ADC Control Register 0 (ADCCTL_0)

9

8

STR_SEQA MOD_CFG

0

0

Write: · Bits ADC_EN, ADC_SR, FRZ_MOD and SWAI writable anytime · Bits MOD_CFG, STR_SEQA and ACC_CFG[1:0] writable if bit ADC_EN clear or bit SMOD_ACC set
Table 9-3. ADCCTL_0 Field Descriptions

Field

Description

15 ADC_EN
14 ADC_SR
13 FRZ_MOD
12 SWAI

ADC Enable Bit -- This bit enables the ADC (e.g. sample buffer amplifier etc.) and controls accessibility of ADC register bits. When this bit gets cleared any ongoing conversion sequence will be aborted and pending results or the result of current conversion gets discarded (not stored). The ADC cannot be re-enabled before any pending action or action in process is finished or aborted, which could take up to a maximum latency time of tDISABLE (see device reference manual for more details). Because internal components of the ADC are turned on/off with this bit, the ADC requires a recovery time period (tREC) after ADC is enabled until the first conversion can be launched via a trigger. 0 ADC disabled. 1 ADC enabled.
ADC Soft-Reset -- This bit causes an ADC Soft-Reset if set after a severe error occurred (see list of severe errors in Section 9.5.2.9, "ADC Error Interrupt Flag Register (ADCEIF) that causes the ADC to cease operation). It clears all overrun flags and error flags and forces the ADC state machine to its idle state. It also clears the Command Index Register, the Result Index Register, and the CSL_SEL and RVL_SEL bits (to be ready for a new control sequence to load new command and start execution again from top of selected CSL). A severe error occurs if an error flag is set which cause the ADC to cease operation. In order to make the ADC operational again an ADC Soft-Reset must be issued. Once this bit is set it can not be cleared by writing any value. It is cleared only by ADC hardware after the SoftReset has been executed. 0 No ADC Soft-Reset issued. 1 Issue ADC Soft-Reset.
Freeze Mode Configuration -- This bit influences conversion flow during Freeze Mode. 0 ADC continues conversion in Freeze Mode. 1 ADC freezes the conversion at next conversion boundary at Freeze Mode entry.
Wait Mode Configuration -- This bit influences conversion flow during Wait Mode. 0 ADC continues conversion in Wait Mode. 1 ADC halts the conversion at next conversion boundary at Wait Mode entry.

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Table 9-3. ADCCTL_0 Field Descriptions (continued)

Field

Description

11-10 ADCFLWCTL Register Access Configuration -- These bits define if the register ADCFLWCTL is controlled via ACC_CFG[1 internal interface only or data bus only or both. See Table 9-4. for more details.
:0]

9

Control Of Conversion Result Storage and RSTAR_EIF flag setting at Sequence Abort or Restart Event -- This

STR_SEQA bit controls conversion result storage and RSTAR_EIF flag setting when a Sequence Abort Event or Restart

Event occurs as follows:

If STR_SEQA = 1'b0 and if a:

· Sequence Abort Event or Restart Event is issued during a conversion the data of this conversion is not stored

and the respective conversion complete flag is not set

· Restart Event only is issued before the last conversion of a CSL is finished and no Sequence Abort Event is

in process (SEQA clear) causes the RSTA_EIF error flag to be asserted and bit SEQA gets set by hardware

If STR_SEQA = 1'b1 and if a:

· Sequence Abort Event or Restart Event is issued during a conversion the data of this conversion is stored and

the respective conversion complete flag is set and Intermediate Result Information Register is updated.

· Restart Event only occurs during the last conversion of a CSL and no Sequence Abort Event is in process

(SEQA clear) does not set the RSTA_EIF error flag

· Restart Event only is issued before the CSL is finished and no Sequence Abort Event is in process (SEQA

clear) causes the RSTA_EIF error flag to be asserted and bit SEQA gets set by hardware

8 MOD_CFG

(Conversion Flow Control) Mode Configuration -- This bit defines the conversion flow control after a Restart Event and after execution of the "End Of List" command type: - Restart Mode - Trigger Mode (For more details please see also section Section 9.6.3.2, "Introduction of the Programmer's Model and following.) 0 "Restart Mode" selected. 1 "Trigger Mode" selected.

Table 9-4. ADCFLWCTL Register Access Configurations

ACC_CFG[1] 0

ACC_CFG[0] 0

0

1

1

0

1

1

ADCFLWCTL Access Mode
None of the access paths is enabled (default / reset configuration)
Single Access Mode - Internal Interface (ADCFLWCTL access via internal interface only)
Single Access Mode - Data Bus (ADCFLWCTL access via data bus only)
Dual Access Mode (ADCFLWCTL register access via internal interface and data bus)

NOTE
Each conversion flow control bit (SEQA, RSTA, TRIG, LDOK) must be controlled by software or internal interface according to the requirements described in Section 9.6.3.2.4, "The two conversion flow control Mode Configurations and overview summary in Table 9-11.

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9.5.2.2 ADC Control Register 1 (ADCCTL_1)

Module Base + 0x0001

7

6

5

4

3

2

1

0

R

0

0

0

0

CSL_BMOD RVL_BMOD SMOD_ACC AUT_RSTA

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-5. ADC Control Register 1 (ADCCTL_1)

Read: Anytime

Write: · Bit CSL_BMOD and RVL_BMOD writable if bit ADC_EN clear or bit SMOD_ACC set · Bit SMOD_ACC only writable in MCU Special Mode · Bit AUT_RSTA writable anytime

Table 9-5. ADCCTL_1 Field Descriptions

Field

Description

7

CSL Buffer Mode Select Bit -- This bit defines the CSL buffer mode. This bit is only writable if ADC_EN is clear.

CSL_BMOD 0 CSL single buffer mode.

1 CSL double buffer mode.

6

RVL Buffer Mode Select Bit -- This bit defines the RVL buffer mode.

RVL_BMOD 0 RVL single buffer mode

1 RVL double buffer mode

5

Special Mode Access Control Bit -- This bit controls register access rights in MCU Special Mode. This bit is

SMOD_ACC automatically cleared when leaving MCU Special Mode.

Note: When this bit is set also the ADCCMD register is writeable via the data bus to allow modification of the

current command for debugging purpose. But this is only possible if the current command is not already

processed (conversion not started).

Please see access details given for each register.

Care must be taken when modifying ADC registers while bit SMOD_ACC is set to not corrupt a possible ongoing

conversion.

0 Normal user access - Register write restrictions exist as specified for each bit.

1 Special access - Register write restrictions are lifted.

4 AUT_RSTA

Automatic Restart Event after exit from MCU Stop and Wait Mode (SWAI set) -- This bit controls if a Restart Event is automatically generated after exit from MCU Stop Mode or Wait Mode with bit SWAI set. It can be configured for ADC conversion flow control mode "Trigger Mode" and "Restart Mode" (anytime during application runtime). 0 No automatic Restart Event after exit from MCU Stop Mode. 1 Automatic Restart Event occurs after exit from MCU Stop Mode.

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9.5.2.3 ADC Status Register (ADCSTS)
It is important to note that if flag DBECC_ERR is set the ADC ceases operation. In order to make the ADC operational again an ADC Soft-Reset must be issued. An ADC Soft-Reset clears bits CSL_SEL and RVL_SEL.

Module Base + 0x0002

7

6

5

4

3

2

1

0

R CSL_SEL

RVL_SEL

DBECC_ER R

Reserved

READY

0

0

0

W

Reset

0

0

0

0

1

0

0

0

= Unimplemented or Reserved

Read: Anytime

Figure 9-6. ADC Status Register (ADCSTS)

Write: · Bits CSL_SEL and RVL_SEL anytime if bit ADC_EN is clear or bit SMOD_ACC is set · Bits DBECC_ERR and READY not writable
Table 9-6. ADCSTS Field Descriptions

Field

Description

7 CSL_SEL

Command Sequence List Select bit -- This bit controls and indicates which ADC Command List is active. This bit can only be written if ADC_EN bit is clear. This bit toggles in CSL double buffer mode when no conversion or conversion sequence is ongoing and bit LDOK is set and bit RSTA is set. In CSL single buffer mode this bit is forced to 1'b0 by bit CSL_BMOD. 0 ADC Command List 0 is active. 1 ADC Command List 1 is active.

6 RVL_SEL

Result Value List Select Bit -- This bit controls and indicates which ADC Result List is active. This bit can only be written if bit ADC_EN is clear. After storage of the initial Result Value List this bit toggles in RVL double buffer mode whenever the conversion result of the first conversion of the current CSL is stored or a CSL got aborted. In RVL single buffer mode this bit is forced to 1'b0 by bit RVL_BMOD. Please see also Section 9.3.1.2, "MCU Operating Modes for information regarding Result List usage in case of Stop or Wait Mode. 0 ADC Result List 0 is active. 1 ADC Result List 1 is active.

5

Double Bit ECC Error Flag -- This flag indicates that a double bit ECC error occurred during conversion

DBECC_ER command load or result storage and ADC ceases operation.

R

In order to make the ADC operational again an ADC Soft-Reset must be issued.

This bit is cleared if bit ADC_EN is clear.

0 No double bit ECC error occurred.

1 A double bit ECC error occurred.

3 READY

Ready For Restart Event Flag -- This flag indicates that ADC is in its idle state and ready for a Restart Event. It can be used to verify after exit from Wait Mode if a Restart Event can be issued and processed immediately without any latency time due to an ongoing Sequence Abort Event after exit from MCU Wait Mode (see also the Note in Section 9.3.1.2, "MCU Operating Modes). 0 ADC not in idle state. 1 ADC is in idle state.

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9.5.2.4 ADC Timing Register (ADCTIM)

Module Base + 0x0003

7

6

5

4

3

2

1

0

R

0

W

PRS[6:0]

Reset

0

0

0

0

0

1

0

1

= Unimplemented or Reserved

Figure 9-7. ADC Timing Register (ADCTIM))

Read: Anytime

Write: These bits are writable if bit ADC_EN is clear or bit SMOD_ACC is set

Table 9-7. ADCTIM Field Descriptions

Field
6-0 PRS[6:0]

Description
ADC Clock Prescaler -- These 7bits are the binary prescaler value PRS. The ADC conversion clock frequency is calculated as follows:
fATDCLK = -2----x------fP--B---R-U----S-S----+-----1---- Refer to Device Specification for allowed frequency range of fATDCLK.

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9.5.2.5 ADC Format Register (ADCFMT)

Chapter 9 Analog-to-Digital Converter (ADC12B_LBA)

Module Base + 0x0004

R W Reset

7
DJM 0

Read: Anytime

6

5

4

3

2

1

0

0

0

0

0

SRES[2:0]

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-8. ADC Format Register (ADCFMT)

Write: Bits DJM and SRES[2:0] are writable if bit ADC_EN clear or bit SMOD_ACC set

Table 9-8. ADCFMT Field Descriptions

Field 7
DJM
2-0 SRES[2:0]

Description
Result Register Data Justification -- Conversion result data format is always unsigned. This bit controls justification of conversion result data in the conversion result list. 0 Left justified data in the conversion result list. 1 Right justified data in the conversion result list.
ADC Resolution Select -- These bits select the resolution of conversion results. See Table 9-9 for coding.

Table 9-9. Selectable Conversion Resolution

SRES[2]

SRES[1]

SRES[0]

ADC Resolution

0

0

0

0

0

1

8-bit data Reserved1.

0

1

0

0

1

1

10-bit data Reserved1.

1

0

0

1

x

x

12-bit data Reserved(1)

1. Reserved settings cause a severe error at ADC conversion start whereby the CMD_EIF flag is set and ADC ceases operation

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9.5.2.6 ADC Conversion Flow Control Register (ADCFLWCTL)
Bit set and bit clear instructions should not be used to access this register.
When the ADC is enabled the bits of ADCFLWCTL register can be modified after a latency time of three Bus Clock cycles. All bits are cleared if bit ADC_EN is clear or via ADC soft-reset.

Module Base + 0x0005

7

6

5

4

3

2

1

0

R

0

0

0

0

SEQA

TRIG

RSTA

LDOK

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-9. ADC Conversion Flow Control Register (ADCFLWCTL)

Read: Anytime

Write: · Bits SEQA, TRIG, RSTA, LDOK can only be set if bit ADC_EN is set. · Writing 1'b0 to any of these bits does not have an effect

Timing considerations (Trigger Event - channel sample start) depending on ADC mode configuration:
· Restart Mode When the Restart Event has been processed (initial command of current CSL is loaded) it takes two Bus Clock cycles plus two ADC conversion clock cycles (pump phase) from the Trigger Event (bit TRIG set) until the select channel starts to sample. During a conversion sequence (back to back conversions) it takes five Bus Clock cycles plus two ADC conversion clock cycles (pump phase) from current conversion period end until the newly selected channel is sampled in the following conversion period.
· Trigger Mode When a Restart Event occurs a Trigger Event is issued simultaneously. The time required to process the Restart Event is mainly defined by the internal read data bus availability and therefore can vary. In this mode the Trigger Event is processed immediately after the Restart Event is finished and both conversion flow control bits are cleared simultaneously. From de-assert of bit TRIG until sampling begins five Bus Clock cycles are required. Hence from occurrence of a Restart Event until channel sampling it takes five Bus Clock cycles plus an uncertainty of a few Bus Clock cycles.
For more details regarding the sample phase please refer to Section 9.6.2.2, "Sample and Hold Machine with Sample Buffer Amplifier.

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Field 7
SEQA
6 TRIG

Chapter 9 Analog-to-Digital Converter (ADC12B_LBA)
Table 9-10. ADCFLWCTL Field Descriptions
Description
Conversion Sequence Abort Event -- This bit indicates that a conversion sequence abort event is in progress. When this bit is set the ongoing conversion sequence and current CSL will be aborted at the next conversion boundary. This bit gets cleared when the ongoing conversion sequence is aborted and ADC is idle. This bit can only be set if bit ADC_EN is set. This bit is cleared if bit ADC_EN is clear. Data Bus Control: This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0]. Writing a value of 1'b0 does not clear the flag. Writing a one to this bit does not clear it but causes an overrun if the bit has already been set. See Section 9.6.3.2.6, "Conversion flow control in case of conversion sequence control bit overrun scenarios for more details. Internal Interface Control: This bit can be controlled via the internal interface Signal "Seq_Abort" if access control is configured accordingly via ACC_CFG[1:0]. After being set an additional request via the internal interface Signal "Seq_Abort" causes an overrun. See also conversion flow control in case of overrun situations. General: In both conversion flow control modes (Restart Mode and Trigger Mode) when bit RSTA gets set automatically bit SEQA gets set when the ADC has not reached one of the following scenarios: - A Sequence Abort request is about to be executed or has been executed. - "End Of List" command type has been executed or is about to be executed In case bit SEQA is set automatically the Restart error flag RSTA_EIF is set to indicate an unexpected Restart Request. 0 No conversion sequence abort request. 1 Conversion sequence abort request.
Conversion Sequence Trigger Bit -- This bit starts a conversion sequence if set and no conversion or conversion sequence is ongoing. This bit is cleared when the first conversion of a sequence starts to sample. This bit can only be set if bit ADC_EN is set. This bit is cleared if bit ADC_EN is clear. Data Bus Control: This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0]. Writing a value of 1'b0 does not clear the flag. After being set this bit can not be cleared by writing a value of 1'b1 instead the error flag TRIG_EIF is set. See also Section 9.6.3.2.6, "Conversion flow control in case of conversion sequence control bit overrun scenarios for more details. Internal Interface Control: This bit can be controlled via the internal interface Signal "Trigger" if access control is configured accordingly via ACC_CFG[1:0]. After being set an additional request via internal interface Signal "Trigger" causes the flag TRIG_EIF to be set. 0 No conversion sequence trigger. 1 Trigger to start conversion sequence.

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Field 5
RSTA
4 LDOK

Table 9-10. ADCFLWCTL Field Descriptions (continued)
Description
Restart Event (Restart from Top of Command Sequence List) -- This bit indicates that a Restart Event is executed. The ADC loads the conversion command from top of the active Sequence Command List when no conversion or conversion sequence is ongoing. This bit is cleared when the first conversion command of the sequence from top of active Sequence Command List has been loaded into the ADCCMD register. This bit can only be set if bit ADC_EN is set. This bit is cleared if bit ADC_EN is clear. Data Bus Control: This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0]. Writing a value of 1'b0 does not clear the flag. Writing a one to this bit does not clear it but causes an overrun if the bit has already been set. See also Section 9.6.3.2.6, "Conversion flow control in case of conversion sequence control bit overrun scenarios for more details. Internal Interface Control: This bit can be controlled via the internal interface Signal "Restart" if access control is configured accordingly via ACC_CFG[1:0]. After being set an additional request via internal interface Signal "Restart" causes an overrun. See conversion flow control in case of overrun situations for more details. General: In conversion flow control mode "Trigger Mode" when bit RSTA gets set bit TRIG is set simultaneously if one of the following has been executed: - "End Of List" command type has been executed or is about to be executed - Sequence Abort Event 0 Continue with commands from active Sequence Command List. 1 Restart from top of active Sequence Command List.
Load OK for alternative Command Sequence List -- This bit indicates if the preparation of the alternative Sequence Command List is done and Command Sequence List must be swapped with the Restart Event. This bit is cleared when bit RSTA is set (Restart Event executed) and the Command Sequence List got swapped. This bit can only be set if bit ADC_EN is set. This bit is cleared if bit ADC_EN is clear. This bit is forced to zero if bit CSL_BMOD is clear. Data Bus Control: This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0]. Writing a value of 1'b0 does not clear the flag. To set bit LDOK the bits LDOK and RSTA must be written simultaneously. After being set this bit can not be cleared by writing a value of 1'b1. See also Section 9.6.3.2.6, "Conversion flow control in case of conversion sequence control bit overrun scenarios for more details. Internal Interface Control: This bit can be controlled via the internal interface Signal "LoadOK" and "Restart" if access control is configured accordingly via ACC_CFG[1:0]. With the assertion of Interface Signal "Restart" the interface Signal "LoadOK" is evaluated and bit LDOK set accordingly (bit LDOK set if Interface Signal "LoadOK" asserted when Interface Signal "Restart" asserts). General: Only in "Restart Mode" if a Restart Event occurs without bit LDOK being set the error flag LDOK_EIF is set except when the respective Restart Request occurred after or simultaneously with a Sequence Abort Request. The LDOK_EIF error flag is also not set in "Restart Mode" if the first Restart Event occurs after: - ADC got enabled - Exit from Stop Mode - ADC Soft-Reset 0 Load of alternative list done. 1 Load alternative list.

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Table 9-11. Summary of Conversion Flow Control Bit Scenarios

RSTA
0 0 0 0 0 0 0 0 1 1 1 1 1

TRIG
0 0 0 0 1 1 1 1 0 0 0 0 1

SEQA
0 0 1 1 0 0 1 1 0 0 1 1 0

LDOK
0 1 0 1 0 1 0 1 0 1 0 1 0

1

1

0

1

1

1

1

0

1

1

1

1

1. Swap CSL buffer 2. Start conversion sequence 3. Prevent RSTA_EIF and LDOK_EIF 4. Load conversion command from top of CSL 5. Abort any ongoing conversion, conversion sequence and CSL 6. Bit TRIG set automatically in Trigger Mode

Conversion Flow Control Mode
Both Modes Both Modes Both Modes Both Modes Both Modes Both Modes Both Modes Both Modes Both Modes Both Modes Both Modes Both Modes "Restart Mode" "Trigger Mode" "Restart Mode" "Trigger Mode" "Restart Mode" "Trigger Mode" "Restart Mode" "Trigger Mode"

Conversion Flow Control Scenario
Valid
Can Not Occur 5.
Valid
Can Not Occur 2.
Valid
Can Not Occur
Can Not Occur
Can Not Occur 4.
Valid 1. 4.
Valid 3. 4. 5.
Valid 1. 3. 4. 5.
Valid
Error flag TRIG_EIF set 2. 4. 6.
Valid
Error flag TRIG_EIF set 1. 2. 4. 6.
Valid
Error flag TRIG_EIF set 2. 3. 4. 5. 6.
Valid
Error flag TRIG_EIF set (1) (2) (3) (4) (5) (6)
Valid

For a detailed description of all conversion flow control bit scenarios please see also Section 9.6.3.2.4, "The two conversion flow control Mode Configurations, Section 9.6.3.2.5, "The four ADC conversion flow control bits and Section 9.6.3.2.6, "Conversion flow control in case of conversion sequence control bit overrun scenarios

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9.5.2.7 ADC Error Interrupt Enable Register (ADCEIE)

Module Base + 0x0006

7

6

5

4

3

2

1

0

R

0

IA_EIE

CMD_EIE EOL_EIE Reserved TRIG_EIE RSTAR_EIE LDOK_EIE

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-10. ADC Error Interrupt Enable Register (ADCEIE)

Read: Anytime

Write: Anytime

Table 9-12. ADCEIE Field Descriptions

Field

Description

7 IA_EIE

Illegal Access Error Interrupt Enable Bit -- This bit enables the illegal access error interrupt. 0 Illegal access error interrupt disabled. 1 Illegal access error interrupt enabled.

6 CMD_EIE

Command Value Error Interrupt Enable Bit -- This bit enables the command value error interrupt. 0 Command value interrupt disabled. 1 Command value interrupt enabled.

5 EOL_EIE

"End Of List" Error Interrupt Enable Bit -- This bit enables the "End Of List" error interrupt. 0 "End Of List" error interrupt disabled. 1 "End Of List" error interrupt enabled.

3 TRIG_EIE

Conversion Sequence Trigger Error Interrupt Enable Bit -- This bit enables the conversion sequence trigger error interrupt. 0 Conversion sequence trigger error interrupt disabled. 1 Conversion sequence trigger error interrupt enabled.

2

Restart Request Error Interrupt Enable Bit-- This bit enables the restart request error interrupt.

RSTAR_EIE 0 Restart Request error interrupt disabled.

1 Restart Request error interrupt enabled.

1

Load OK Error Interrupt Enable Bit -- This bit enables the Load OK error interrupt.

LDOK_EIE 0 Load OK error interrupt disabled.

1 Load OK error interrupt enabled.

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Chapter 9 Analog-to-Digital Converter (ADC12B_LBA)
ADC Interrupt Enable Register (ADCIE)

Module Base + 0x0007

7

6

5

4

3

2

1

0

R

0

0

0

0

0

SEQAD_IE CONIF_OIE Reserved

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-11. ADC Interrupt Enable Register (ADCIE)

Read: Anytime

Write: Anytime

Table 9-13. ADCIE Field Descriptions

Field

Description

7 SEQAD_IE

Conversion Sequence Abort Done Interrupt Enable Bit -- This bit enables the conversion sequence abort event done interrupt. 0 Conversion sequence abort event done interrupt disabled. 1 Conversion sequence abort event done interrupt enabled.

6

ADCCONIF Register Flags Overrun Interrupt Enable -- This bit enables the flag which indicates if an overrun

CONIF_OIE situation occurred for one of the CON_IF[15:1] flags or for the EOL_IF flag.

0 No ADCCONIF Register Flag overrun occurred.

1 ADCCONIF Register Flag overrun occurred.

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9.5.2.9 ADC Error Interrupt Flag Register (ADCEIF)
If one of the following error flags is set the ADC ceases operation: · IA_EIF · CMD_EIF · EOL_EIF · TRIG_EIF
In order to make the ADC operational again an ADC Soft-Reset must be issued which clears above listed error interrupt flags.
The error interrupt flags RSTAR_EIF and LDOK_EIF do not cause the ADC to cease operation. If set the ADC continues operation. Each of the two bits can be cleared by writing a value of 1'b1. Both bits are also cleared if an ADC Soft-Reset is issued.
All bits are cleared if bit ADC_EN is clear. Writing any flag with value 1'b0 does not clear a flag. Writing any flag with value 1'b1 does not set the flag.

Module Base + 0x0008

7

6

5

4

3

2

1

0

R

0

IA_EIF

CMD_EIF EOL_EIF Reserved TRIG_EIF RSTAR_EIF LDOK_EIF

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-12. ADC Error Interrupt Flag Register (ADCEIF)

Read: Anytime

Write: · Bits RSTAR_EIF and LDOK_EIF are writable anytime · Bits IA_EIF, CMD_EIF, EOL_EIF and TRIG_EIF are not writable

Table 9-14. ADCEIF Field Descriptions

Field 7
IA_EIF
6 CMD_EIF
5 EOL_EIF

Description
Illegal Access Error Interrupt Flag -- This flag indicates that storing the conversion result caused an illegal access error or conversion command loading from outside system RAM or NVM area occurred. The ADC ceases operation if this error flag is set (issue of type severe). 0 No illegal access error occurred. 1 An illegal access error occurred.
Command Value Error Interrupt Flag -- This flag indicates that an invalid command is loaded (Any command that contains reserved bit settings) or illegal format setting selected (reserved SRES[2:0] bit settings).
The ADC ceases operation if this error flag is set (issue of type severe). 0 Valid conversion command loaded. 1 Invalid conversion command loaded.
"End Of List" Error Interrupt Flag -- This flag indicates a missing "End Of List" command type in current executed CSL. The ADC ceases operation if this error flag is set (issue of type severe). 0 No "End Of List" error. 1 "End Of List" command type missing in current executed CSL.

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Table 9-14. ADCEIF Field Descriptions (continued)

Field

Description

3 TRIG_EIF

Trigger Error Interrupt Flag -- This flag indicates that a trigger error occurred. This flag is set in "Restart" Mode when a conversion sequence got aborted and no Restart Event occurred before
the Trigger Event or if the Trigger Event occurred before the Restart Event was finished (conversion command has been loaded). This flag is set in "Trigger" Mode when a Trigger Event occurs before the Restart Event is issued to start conversion of the initial Command Sequence List. In "Trigger" Mode only a Restart Event is required to start conversion of the initial Command Sequence List. This flag is set when a Trigger Event occurs before a conversion sequence got finished. This flag is also set if a Trigger occurs while a Trigger Event is just processed - first conversion command of a sequence is beginning to sample (see also Section 9.6.3.2.6, "Conversion flow control in case of conversion sequence control bit overrun scenarios). This flag is also set if the Trigger Event occurs automatically generated by hardware in "Trigger Mode" due to a Restart Event and simultaneously a Trigger Event is generated via data bus or internal interface. The ADC ceases operation if this error flag is set (issue of type severe). 0 No trigger error occurred. 1 A trigger error occurred.

2

Restart Request Error Interrupt Flag -- This flag indicates a flow control issue. It is set when a Restart Request

RSTAR_EIF occurs after a Trigger Event and before one of the following conditions was reached:

- The "End Of List" command type has been executed

- Depending on bit STR_SEQA if the "End Of List" command type is about to be executed

- The current CSL has been aborted or is about to be aborted due to a Sequence Abort Request.

The ADC continues operation if this error flag is set.

This flag is not set for Restart Request overrun scenarios (see also Section 9.6.3.2.6, "Conversion flow control

in case of conversion sequence control bit overrun scenarios).

0 No Restart request error situation occurred.

1 Restart request error situation occurred.

1 LDOK_EIF

Load OK Error Interrupt Flag -- This flag can only be set in "Restart Mode". It indicates that a Restart Request occurred without LDOK. This flag is not set if a Sequence Abort Event is already in process (bit SEQA set) when the Restart Request occurs or a Sequence Abort Request occurs simultaneously with the Restart Request.
The LDOK_EIF error flag is also not set in "Restart Mode" if the first Restart Event occurs after: - ADC got enabled - Exit from Stop Mode - ADC Soft-Reset - ADC used in CSL single buffer mode The ADC continues operation if this error flag is set. 0 No Load OK error situation occurred. 1 Load OK error situation occurred.

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9.5.2.10 ADC Interrupt Flag Register (ADCIF)
After being set any of these bits can be cleared by writing a value of 1'b1 or via ADC soft-reset (bit ADC_SR). All bits are cleared if bit ADC_EN is clear. Writing any flag with value 1'b0 does not clear the flag. Writing any flag with value 1'b1 does not set the flag.

Module Base + 0x0009

7

6

5

4

3

2

1

0

R

0

0

0

0

0

SEQAD_IF CONIF_OIF Reserved

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-13. ADC Interrupt Flag Register (ADCIF)

Read: Anytime

Write: Anytime

Table 9-15. ADCIF Field Descriptions

Field

Description

7 SEQAD_IF

Conversion Sequence Abort Done Interrupt Flag -- This flag is set when the Sequence Abort Event has been executed except the Sequence Abort Event occurred by hardware in order to be able to enter MCU Stop Mode or Wait Mode with bit SWAI set.This flag is also not set if the Sequence Abort request occurs during execution of the last conversion command of a CSL and bit STR_SEQA being set.
0 No conversion sequence abort request occurred. 1 A conversion sequence abort request occurred.

6

ADCCONIF Register Flags Overrun Interrupt Flag -- This flag indicates if an overrun situation occurred for

CONIF_OIF one of the CON_IF[15:1] flags or for the EOL_IF flag. In RVL single buffer mode (RVL_BMOD clear) an overrun

of the EOL_IF flag is not indicated (For more information please see Note below).

0 No ADCCONIF Register Flag overrun occurred.

1 ADCCONIF Register Flag overrun occurred.

NOTE
In RVL double buffer mode a conversion interrupt flag (CON_IF[15:1]) or End Of List interrupt flag (EOL_IF) overrun is detected if one of these bits is set when it should be set again due to conversion command execution.
In RVL single buffer mode a conversion interrupt flag (CON_IF[15:1]) overrun is detected only. The overrun is detected if any of the conversion interrupt flags (CON_IF[15:1]) is set while the first conversion result of a CSL is stored (result of first conversion from top of CSL is stored).

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9.5.2.11

Chapter 9 Analog-to-Digital Converter (ADC12B_LBA)
ADC Conversion Interrupt Enable Register (ADCCONIE)

Module Base + 0x000A

15

14

13

12

11

10

9

8

7

6

5

4

3

2

R CON_IE[15:1]
W

Reset 0

0

0

0

0

0

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-14. ADC Conversion Interrupt Enable Register (ADCCONIE)

1

0

EOL_I E

0

0

Read: Anytime Write: Anytime

Table 9-16. ADCCONIE Field Descriptions

Field

Description

15-1

Conversion Interrupt Enable Bits -- These bits enable the individual interrupts which can be triggered via

CON_IE[15:1] interrupt flags CON_IF[15:1].

0 ADC conversion interrupt disabled.

1 ADC conversion interrupt enabled.

0 EOL_IE

End Of List Interrupt Enable Bit -- This bit enables the end of conversion sequence list interrupt. 0 End of list interrupt disabled. 1 End of list interrupt enabled.

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9.5.2.12 ADC Conversion Interrupt Flag Register (ADCCONIF)
After being set any of these bits can be cleared by writing a value of 1'b1. All bits are cleared if bit ADC_EN is clear or via ADC soft-reset (bit ADC_SR set). Writing any flag with value 1'b0 does not clear the flag. Writing any flag with value 1'b1 does not set the flag.

Module Base + 0x000C

15

14

13

12

11

10

9

8

7

6

5

4

3

2

R W

CON_IF[15:1]

Reset 0

0

0

0

0

0

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-15. ADC Conversion Interrupt Flag Register (ADCCONIF)

1

0

EOL_I F

0

0

Read: Anytime Write: Anytime

Table 9-17. ADCCONIF Field Descriptions

Field

Description

15-1

Conversion Interrupt Flags -- These bits could be set by the binary coded interrupt select bits

CON_IF[15:1] INTFLG_SEL[3:0] when the corresponding conversion command has been processed and related data has

been stored to RAM.

See also notes below.

0 EOL_IF

End Of List Interrupt Flag -- This bit is set by the binary coded conversion command type select bits CMD_SEL[1:0] for "end of list" type of commands and after such a command has been processed and the related data has been stored RAM.
See also second note below

NOTE
These bits can be used to indicate if a certain packet of conversion results is available. Clearing a flag indicates that conversion results have been retrieved by software and the flag can be used again (see also Section 9.9.6, "RVL swapping in RVL double buffer mode and related registers ADCIMDRI and ADCEOLRI.
NOTE
Overrun situation of a flag CON_IF[15:1] and EOL_IF are indicated by flag CONIF_OIF.

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9.5.2.13 ADC Intermediate Result Information Register (ADCIMDRI) This register is cleared when bit ADC_SR is set or bit ADC_EN is clear.

Module Base + 0x000E

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R CSL_I RVL_I MD MD

0

0

0

0

0

0

0

0

RIDX_IMD[5:0]

W

Reset 0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-16. ADC Intermediate Result Information Register (ADCIMDRI)

Read: Anytime Write: Never

Table 9-18. ADCIMDRI Field Descriptions

Field

Description

15 CSL_IMD

Active CSL At Intermediate Event -- This bit indicates the active (used) CSL at the occurrence of a conversion interrupt flag (CON_IF[15:1]) (occurrence of an intermediate result buffer fill event) or when a Sequence Abort Event gets executed.
0 CSL_0 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set. 1 CSL_1 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set.

14 RVL_IMD

Active RVL At Intermediate Event -- This bit indicates the active (used) RVL buffer at the occurrence of a conversion interrupt flag (CON_IF[15:1]) (occurrence of an intermediate result buffer fill event) or when a Sequence Abort Event gets executed.
0 RVL_0 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set. 1 RVL_1 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set.

5-0

RES_IDX Value At Intermediate Event -- These bits indicate the result index (RES_IDX) value at the

RIDX_IMD[5 occurrence of a conversion interrupt flag (CON_IF[15:1]) (occurrence of an intermediate result buffer fill event)

:0]

or occurrence of EOL_IF flag or when a Sequence Abort Event gets executed to abort an ongoing conversion

(the result index RES_IDX is captured at the occurrence of a result data store).

When a Sequence Abort Event has been processed flag SEQAD_IF is set and the RES_IDX value of the last stored result is provided. Hence in case an ongoing conversion is aborted the RES_IDX value captured in RIDX_IMD bits depends on bit STORE_SEQA:
- STORE_SEQA =1: The result index of the aborted conversion is provided - STORE_SEQA =0: The result index of the last stored result at abort execution time is provided In case a CSL is aborted while no conversion is ongoing (ADC waiting for a Trigger Event) the last captured result
index is provided. In case a Sequence Abort Event was initiated by hardware due to MCU entering Stop Mode or Wait Mode with
bit SWAI set, the result index of the last stored result is captured by bits RIDX_IMD but flag SEQAD_IF is not set.

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NOTE The register ADCIMDRI is updated and simultaneously a conversion interrupt flag CON_IF[15:1] occurs when the corresponding conversion command (conversion command with INTFLG_SEL[3:0] set) has been processed and related data has been stored to RAM.

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9.5.2.14 ADC End Of List Result Information Register (ADCEOLRI) This register is cleared when bit ADC_SR is set or bit ADC_EN is clear.

Module Base + 0x0010

7

6

5

4

3

2

1

0

R CSL_EOL RVL_EOL

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-17. ADC End Of List Result Information Register (ADCEOLRI)

Read: Anytime

Write: Never

Table 9-19. ADCEOLRI Field Descriptions

Field 7
CSL_EOL
6 RVL_EOL

Description
Active CSL When "End Of List" Command Type Executed -- This bit indicates the active (used) CSL when a "End Of List" command type has been executed and related data has been stored to RAM.
0 CSL_0 active when "End Of List" command type executed. 1 CSL_1 active when "End Of List" command type executed.
Active RVL When "End Of List" Command Type Executed -- This bit indicates the active (used) RVL when a "End Of List" command type has been executed and related data has been stored to RAM.
0 RVL_0 active when "End Of List" command type executed. 1 RVL_1 active when "End Of List" command type executed.

NOTE
The conversion interrupt EOL_IF occurs and simultaneously the register ADCEOLRI is updated when the "End Of List" conversion command type has been processed and related data has been stored to RAM.

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9.5.2.15 ADC Command Register 0 (ADCCMD_0)

Module Base + 0x0014

R W R W Reset

31

30

29

28

CMD_SEL

0

0

CMD_SEL

OPT[1:0](1)

0

0

0

0

= Unimplemented or Reserved

27

26

25

24

INTFLG_SEL[3:0]

INTFLG_SEL[3:0]

0

0

0

0

Figure 9-18. ADC Command Register 0 (ADCCMD_0) 1. Only available on ADC12B_LBA V2 and V3 (see Table 9-2 for details)

Read: Anytime
Write: Only writable if bit SMOD_ACC is set (see also Section 9.5.2.2, "ADC Control Register 1 (ADCCTL_1) bit SMOD_ACC description for more details)
Table 9-20. ADCCMD_0 Field Descriptions

Field

Description

31-30

Conversion Command Select Bits -- These bits define the type of current conversion described in Table 9-21.

CMD_SEL[1:0]

ADC12B_LBA V2 and V3 (includes OPT[1:0])

29-28 OPT[1:0]

Option Bits -- These two option bits can be used to control a SoC level feature/function. These bits are used together with Option bits OPT[2:3]. Please refer to the device reference manual for details of the feature/functionality controlled by these bits

27-24

Conversion Interrupt Flag Select Bits -- These bits define which interrupt flag is set in the ADCIFH/L register

INTFLG_SEL[ at the end of current conversion.The interrupt flags ADCIF[15:1] are selected via binary coded bits

3:0]

INTFLG_SEL[3:0]. See also Table 9-22

NOTE
If bit SMOD_ACC is set modifying this register must be done carefully only when no conversion and conversion sequence is ongoing.

CMD_SEL[1] 0 0

Table 9-21. Conversion Command Type Select

CMD_SEL[0] 0 1

Conversion Command Type Description
Normal Conversion
End Of Sequence (Wait for Trigger to execute next sequence or for a Restart)

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Table 9-21. Conversion Command Type Select

CMD_SEL[0] 0

Conversion Command Type Description
End Of List (Automatic wrap to top of CSL
and Continue Conversion)

1

End Of List

(Wrap to top of CSL and:

- In "Restart Mode" wait for Restart Event followed by a Trigger

- In "Trigger Mode" wait for Trigger or Restart Event)

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CON_IF[15:1] 0x0000 0x0001 0x0002 0x0004 0x0008 0x0010 .... 0x0800 0x1000 0x2000 0x4000

Table 9-22. Conversion Interrupt Flag Select

INTFLG_SEL[3] INTFLG_SEL[2] INTFLG_SEL[1] INTFLG_SEL[0]

Comment

0

0

0

0

No flag set

0

0

0

1

Only one flag can

be set

0

0

1

0

(one hot coding)

0

0

1

1

0

1

0

0

0

1

0

1

...

...

...

...

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

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9.5.2.16 ADC Command Register 1 (ADCCMD_1)
A command which contains reserved bit settings causes the error flag CMD_EIF being set and ADC cease operation. The CMD_EIF is never set for Internal_x channels, even if the channels are specified as reserved in the Device Overview section of the Reference Manual.

Module Base + 0x0015

23

22

21

20

19

18

17

16

R VRH_SEL(1) VRL_SEL1. W

CH_SEL[5:0]

R

VRH_SEL[1:0](2)

W

CH_SEL[5:0]

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-19. ADC Command Register 1 (ADCCMD_1) 1. Only available on ADC12B_LBA V1 and V2 (see Table 9-2 for details)

2. Only available on ADC12B_LBA V3 (see Table 9-2 for details)

Read: Anytime

Write: Only writable if bit SMOD_ACC is set (see also Section 9.5.2.2, "ADC Control Register 1 (ADCCTL_1) bit SMOD_ACC description for more details)

Table 9-23. ADCCMD_1 Field Descriptions

Field
23 VRH_SEL
22 VRL_SEL
23-22 VRH_SEL

Description
ADC12B_LBA V1 and V2 (includes VRH_SEL/VRL_SEL)
Reference High Voltage Select Bit -- This bit selects the high voltage reference for current conversion. 0 VRH_0 input selected as high voltage reference. 1 VRH_1 input selected as high voltage reference.
Reference Low Voltage Select Bit -- This bit selects the low voltage reference for current conversion. 0 VRL_0 input selected as low voltage reference. 1 VRL_1 input selected as low voltage reference.
ADC12B_LBA V3 (includes VRH_SEL[1:0])
Reference High Voltage Select Bit -- These bits select the high voltage reference for current conversion. 00 VRH_0 input selected as high voltage reference 01 VRH_1 input selected as high voltage reference 10 VRH_2 input selected as high voltage reference 11 Reserved

21-16

ADC Input Channel Select Bits -- These bits select the input channel for the current conversion. See Table 9-

CH_SEL[5:0] 24 for channel coding information.

NOTE
If bit SMOD_ACC is set modifying this register must be done carefully only when no conversion and conversion sequence is ongoing.

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Table 9-24. Analog Input Channel Select

CH_SEL[5] CH_SEL[4] CH_SEL[3] CH_SEL[2] CH_SEL[1] CH_SEL[0]

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

1

0

0

0

1

0

0

0

0

0

1

0

1

0

0

0

1

1

0

0

0

0

1

1

1

0

0

1

0

0

0

0

0

1

0

0

1

0

0

1

0

1

0

0

0

1

0

1

1

0

0

1

1

0

0

0

0

1

1

0

1

0

0

1

1

1

0

0

0

1

1

1

1

0

1

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

0

0

1

0

0

1

1

0

1

0

1

0

0

0

1

x

x

x

x

1

x

x

x

x

x

Analog Input Channel VRL_0/1 (V1, V2, see Table 9-2)
VRL_0 (V3, see Table 9-2) VRH_0/1 (V1, V2, see Table 9-2) VRH_0/1/2 (V3, see Table 9-2) (VRH_0/1 + VRL_0/1) / 2 (V1, V2, see Table 9-2) (VRH_0/1/2 + VRL_0) / 2 (V3, see Table 9-2)
Reserved Reserved Reserved Reserved Reserved Internal_0 (ADC temperature sense) Internal_1 Internal_2 Internal_3 Internal_4 Internal_5 Internal_6 Internal_7
AN0 AN1 AN2 AN3 AN4 ANx Reserved

NOTE
ANx in Table 9-24 is the maximum number of implemented analog input channels on the device. Please refer to the device overview of the reference manual for details regarding number of analog input channels.

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9.5.2.17 ADC Command Register 2 (ADCCMD_2)
A command which contains reserved bit settings causes the error flag CMD_EIF being set and ADC cease operation.

Module Base + 0x0016

15

14

13

12

11

10

9

R SMP[4:0]
W

0

0

R SMP[4:0]
W

OPT[3:2](1)

Reset

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-20. ADC Command Register 2 (ADCCMD_2)

1. Only available on ADC12B_LBA V2 and V3 (see Table 9-2 for details)

8
Reserved
Reserved 0

Read: Anytime

Write: Only writable if bit SMOD_ACC is set (see also Section 9.5.2.2, "ADC Control Register 1 (ADCCTL_1) bit SMOD_ACC description for more details)
Table 9-25. ADCCMD_2 Field Descriptions

Field 15-11 SMP[4:0]
10-9 OPT[3:2]

Description
Sample Time Select Bits -- These four bits select the length of the sample time in units of ADC conversion clock cycles. Note that the ADC conversion clock period is itself a function of the prescaler value (bits PRS[6:0]). Table 9-26 lists the available sample time lengths.
ADC12B_LBA V2 and V3 (includes OPT[3:2])
Option Bits -- These two option bits can be used to control a SoC level feature/function. These bits are used together with Option bits OPT[1:0]. Please refer to the device reference manual for details of the feature/functionality controlled by these bits.

NOTE
If bit SMOD_ACC is set modifying this register must be done carefully only when no conversion and conversion sequence is ongoing.

SMP[4]
0 0 0 0

Table 9-26. Sample Time Select

SMP[3]

SMP[2]

SMP[1]

SMP[0]

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

Sample Time in Number of ADC Clock Cycles
4
5
6
7

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Table 9-26. Sample Time Select

SMP[4]

SMP[3]

SMP[2]

SMP[1]

SMP[0]

0

0

1

0

0

0

0

1

0

1

0

0

1

1

0

0

0

1

1

1

0

1

0

0

0

0

1

0

0

1

0

1

0

1

0

0

1

0

1

1

0

1

1

0

0

0

1

1

0

1

0

1

1

1

0

0

1

1

1

1

1

0

0

0

0

1

0

0

0

1

1

0

0

1

0

1

0

0

1

1

1

0

1

0

0

1

0

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

x

x

x

Sample Time in Number of ADC Clock Cycles
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Reserved Reserved Reserved Reserved

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Chapter 9 Analog-to-Digital Converter (ADC12B_LBA)
ADC Command Register 3 (ADCCMD_3)

Module Base + 0x0017

7

6

5

4

3

2

1

0

R Reserved
W

Reserved

Reserved

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-21. ADC Command Register 3 (ADCCMD_3)

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9.5.2.19 ADC Command Index Register (ADCCIDX)
It is important to note that these bits do not represent absolute addresses instead it is a sample index (object size 32bit).

Module Base + 0x001C

7

6

5

4

3

2

1

0

R

0

0

CMD_IDX[5:0]

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-22. ADC Command Index Register (ADCCIDX)

Read: Anytime

Write: NA

Table 9-27. ADCCIDX Field Descriptions

Field
5-0 CMD_IDX
[5:0]

Description
ADC Command Index Bits -- These bits represent the command index value for the conversion commands relative to the two CSL start addresses in the memory map. These bits do not represent absolute addresses instead it is a sample index (object size 32bit). See also Section 9.6.3.2.2, "Introduction of the two Command Sequence Lists (CSLs) for more details.

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Chapter 9 Analog-to-Digital Converter (ADC12B_LBA)
ADC Command Base Pointer Register (ADCCBP)

Module Base + 0x001D

23

22

21

20

19

18

17

16

R CMD_PTR[23:16]
W

Reset

0

0

0

0

0

0

0

0

Module Base + 0x001E

15

14

13

12

11

10

9

8

R CMD_PTR[15:8]
W

Reset

0

0

0

0

0

0

0

0

Module Base + 0x001F

7

6

5

4

3

2

1

0

R CMD_PTR[7:2]
W

0

0

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-23. ADC Command Base Pointer Registers (ADCCBP_0, ADCCBP_1, ADCCBP_2))

Read: Anytime Write: Bits CMD_PTR[23:2] writable if bit ADC_EN clear or bit SMOD_ACC set
Table 9-28. ADCCBP Field Descriptions

Field
23-2 CMD_PTR
[23:2]

Description
ADC Command Base Pointer Address -- These bits define the base address of the two CSL areas inside the system RAM or NVM of the memory map. They are used to calculate the final address from which the conversion commands will be loaded depending on which list is active. For more details see Section 9.6.3.2.2, "Introduction of the two Command Sequence Lists (CSLs).

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9.5.2.21 ADC Result Index Register (ADCRIDX)
It is important to note that these bits do not represent absolute addresses instead it is a sample index (object size 16bit).

Module Base + 0x0020

7

6

5

4

3

2

1

0

R

0

0

RES_IDX[5:0]

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-24. ADC Result Index Register (ADCRIDX)

Read: Anytime

Write: NA

Table 9-29. ADCRIDX Field Descriptions

Field

Description

5-0

ADC Result Index Bits -- These read only bits represent the index value for the conversion results relative to

RES_IDX[5:0] the two RVL start addresses in the memory map. These bits do not represent absolute addresses instead it

is a sample index (object size 16bit). See also Section 9.6.3.2.3, "Introduction of the two Result Value Lists

(RVLs) for more details.

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Chapter 9 Analog-to-Digital Converter (ADC12B_LBA)
ADC Result Base Pointer Register (ADCRBP)

Module Base + 0x0021

23

22

21

20

19

18

17

16

R

0

0

0

0

W

RES_PTR[19:16]

Reset

0

0

0

0

0

0

0

0

Module Base + 0x0022

15

14

13

12

11

10

9

8

R RES_PTR[15:8]
W

Reset

0

0

0

0

0

0

0

0

Module Base + 0x0023

7

6

5

4

3

2

1

0

R RES_PTR[7:2]
W

0

0

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-25. ADC Result Base Pointer Registers (ADCRBP_0, ADCRBP_1, ADCRBP_2))

Read: Anytime Write: Bits RES_PTR[19:2] writeable if bit ADC_EN clear or bit SMOD_ACC set
Table 9-30. ADCRBP Field Descriptions

Field

Description

19-2 RES_PTR[19:2]

ADC Result Base Pointer Address -- These bits define the base address of the list areas inside the system RAM of the memory map to which conversion results will be stored to at the end of a conversion. These bits can only be written if bit ADC_EN is clear. See also Section 9.6.3.2.3, "Introduction of the two Result Value Lists (RVLs).

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9.5.2.23 ADC Command and Result Offset Register 0 (ADCCROFF0)

Module Base + 0x0024

7

6

5

4

3

2

1

0

R

0

CMDRES_OFF0[6:0]

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-26. ADC Command and Result Offset Register 0 (ADCCROFF0)

Read: Anytime

Write: NA

Table 9-31. ADCCROFF0 Field Descriptions

Field

Description

6-0

ADC Command and Result Offset Value -- These read only bits represent the conversion command and result

CMDRES_OF offset value relative to the conversion command base pointer address and result base pointer address in the

F0

memory map to refer to CSL_0 and RVL_0. It is used to calculate the address inside the system RAM to which

[6:0]

the result at the end of the current conversion is stored to and the area (RAM or NVM) from which the

conversion commands are loaded from. This is a zero offset (null offset) which can not be modified. These bits

do not represent absolute addresses instead it is a sample offset (object size 16bit for RVL, object size 32bit

for CSL). See also Section 9.6.3.2.2, "Introduction of the two Command Sequence Lists (CSLs) and

Section 9.6.3.2.3, "Introduction of the two Result Value Lists (RVLs) for more details.

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9.5.2.24 ADC Command and Result Offset Register 1 (ADCCROFF1)
It is important to note that these bits do not represent absolute addresses instead it is an sample offset (object size 16bit for RVL, object size 32bit for CSL).

Module Base + 0x0025

7

6

5

4

3

2

1

0

R

0

W

CMDRES_OFF1[6:0]

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 9-27. ADC Command and Result Offset Register 1 (ADCCROFF1)

Read: Anytime

Write: These bits are writable if bit ADC_EN clear or bit SMOD_ACC set

Table 9-32. ADCCROFF1 Field Descriptions

Field

Description

6-0

ADC Result Address Offset Value -- These bits represent the conversion command and result offset value

CMDRES_OF relative to the conversion command base pointer address and result base pointer address in the memory map

F1

to refer to CSL_1 and RVL_1. It is used to calculate the address inside the system RAM to which the result at

[6:0]

the end of the current conversion is stored to and the area (RAM or NVM) from which the conversion

commands are loaded from. These bits do not represent absolute addresses instead it is an sample offset

(object size 16bit for RVL, object size 32bit for CSL).,These bits can only be modified if bit ADC_EN is clear.

See also Section 9.6.3.2.2, "Introduction of the two Command Sequence Lists (CSLs) and Section 9.6.3.2.3,

"Introduction of the two Result Value Lists (RVLs) for more details.

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9.6 Functional Description
9.6.1 Overview
The ADC12B_LBA consists of an analog sub-block and a digital sub-block. It is a successive approximation analog-to-digital converter including a sample-and-hold mechanism and an internal charge scaled C-DAC (switched capacitor scaled digital-to-analog converter) with a comparator to realize the successive approximation algorithm.
9.6.2 Analog Sub-Block
The analog sub-block contains all analog circuits (sample and hold, C-DAC, analog Comparator, and so on) required to perform a single conversion. Separate power supplies VDDA and VSSA allow noise from the MCU circuitry to be isolated from the analog sub-block for improved accuracy.
9.6.2.1 Analog Input Multiplexer
The analog input multiplexers connect one of the external or internal analog input channels to the sample and hold storage node.
9.6.2.2 Sample and Hold Machine with Sample Buffer Amplifier
The Sample and Hold Machine controls the storage and charge of the storage node (sample capacitor) to the voltage level of the analog signal at the selected ADC input channel. This architecture employs the advantage of reduced crosstalk between channels.
The sample buffer amplifier is used to raise the effective input impedance of the A/D machine, so that external components (higher bandwidth or higher impedance connected as specified) are less significant to accuracy degradation.
During the sample phase, the analog input connects first via a sample buffer amplifier with the storage node always for two ADC clock cycles ("Buffer" sample time). For the remaining sample time ("Final" sample time) the storage node is directly connected to the analog input source. Please see also Figure 9-28 for illustration and the Appendix of the device reference manual for more details. The input analog signals are unipolar and must be within the potential range of VSSA to VDDA. During the hold process, the analog input is disconnected from the storage node.

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

Total Sample Time (N = SMP[4:0])

SAR Sequence (Resolution Dependent Length: SRES[2:0])

"Buffer" Sample Time
(2 cycles)

"Final" Sample Time (N - 2 cycles)

Sample CAP hold phase

ADC_CLK
Figure 9-28. Sampling and Conversion Timing Example (8-bit Resolution, 4 Cycle Sampling)
Please note that there is always a pump phase of two ADC_CLK cycles before the sample phase begins, hence glitches during the pump phase could impact the conversion accuracy for short sample times.
9.6.3 Digital Sub-Block
The digital sub-block contains a list-based programmer's model and the control logic for the analog subblock circuits.
9.6.3.1 Analog-to-Digital (A/D) Machine
The A/D machine performs the analog-to-digital conversion. The resolution is program selectable to be either 8- or 10- or 12 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the sampled and stored analog voltage with a series of binary coded discrete voltages. By following a binary search algorithm, the A/D machine identifies the discrete voltage that is nearest to the sampled and stored voltage. Only analog input signals within the potential range of VRL_0/1 to VRH_0/1/3 (availability of VRL_1 and VRH_2 see Table 9-2) (A/D reference potentials) will result in a non-railed digital output code.
9.6.3.2 Introduction of the Programmer's Model
The ADC_LBA provides a programmer's model that uses a system memory list-based architecture for definition of the conversion command sequence and conversion result handling. The Command Sequence List (CSL) and Result Value List (RVL) are implemented in double buffered manner and the buffer mode is user selectable for each list (bits CSL_BMOD, RVL_BMOD). The 32-bit wide conversion command is double buffered and the currently active command is visible in the ADC register map at ADCCMD register space.

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9.6.3.2.1 Introduction of The Command Sequence List (CSL) Format
A Command Sequence List (CSL) contains up to 64 conversion commands. A user selectable number of successive conversion commands in the CSL can be grouped as a command sequence. This sequence of conversion commands is successively executed by the ADC at the occurrence of a Trigger Event. The commands of a sequence are successively executed until an "End Of Sequence" or "End Of List" command type identifier in a command is detected (command type is coded via bits CMD_SEL[1:0]). The number of successive conversion commands that belong to a command sequence and the number of command sequences inside the CSL can be freely defined by the user and is limited by the 64 conversion commands a CSL can contain. A CSL must contain at least one conversion command and one "end of list" command type identifier. The minimum number of command sequences inside a CSL is zero and the maximum number of command sequences is 63. A command sequence is defined with bits CMD_SEL[1:0] in the register ADCCMD_M by defining the end of a conversion sequence. The Figure 929 and Figure 9-30 provides examples of a CSL.

Waiting for trigger to proceed
Waiting for trigger to proceed
Waiting for trigger to proceed
Wait for RSTA or LDOK+RSTA

CSL_0/1
Command_1 Command_2 Command_3 Command_4 Command_5 Command_6 Command_7 Command_8 Command_9 Command_10 Command_11 Command_12
Command_13

} Command Coding Information done by bits

normal conversion normal conversion normal conversion normal conversion

Sequence_1

normal conversion

normal conversion

End Of Sequence normal conversion normal conversion

} Sequence_2

End Of Sequence normal conversion normal conversion

} Sequence_3

End Of List

CMD_SEL[1:0]
00 00 00 00 00 00 01 00 00 01 00 00 11

Figure 9-29. Example CSL with sequences and an "End Of List" command type identifier

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CSL_0
Command_1 Command_2 Command_3 Command_4 Command_5 Command_6 Command_7 Command_8 Command_9 Command_10 Command_11 Command_12
Command_13

Command coding information done by bits CMD_SEL[1:0]

normal conversion normal conversion

00 00

normal conversion

00

normal conversion

00

normal conversion normal conversion normal conversion normal conversion

continuous conversion

00 00 00 00

normal conversion normal conversion

00 00

normal conversion

00

normal conversion

00

End Of List, wrap to top, continue

10

Figure 9-30. Example CSL for continues conversion

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9.6.3.2.2 Introduction of the two Command Sequence Lists (CSLs)
The two Command Sequence Lists (CSLs) can be referred to via the Command Base Pointer Register plus the Command and Result Offset Registers plus the Command Index Register (ADCCBP, ADCCROFF_0/1, ADCCIDX). The final address for conversion command loading is calculated by the sum of these registers (e.g.: ADCCBP+ADCCROFF_0+ADCCIDX or ADCCBP+ADCCROFF_1+ADCCIDX). Bit CSL_BMOD selects if the CSL is used in double buffer or single buffer mode. In double buffer mode, the CSL can be swapped by flow control bits LDOK and RSTA. For detailed information about when and how the CSL is swapped, please refer to Section 9.6.3.2.5, "The four ADC conversion flow control bits description of Restart Event + CSL Swap, Section 9.9.7.1, "Initial Start of a Command Sequence List and Section 9.9.7.3, "Restart CSL execution with new/other CSL (alternative CSL becomes active CSL) -- CSL swapping Which list is actively used for ADC command loading is indicated by bit CSL_SEL. The register to define the CSL start addresses (ADCCBP) can be set to any even location of the system RAM or NVM area. It is the user's responsibility to make sure that the different ADC lists do not overlap or exceed the system RAM or the NVM area, respectively. The error flag IA_EIF will be set for accesses to ranges outside system RAM area and cause an error interrupt if enabled.

Scenario with: CSL_SEL = 1'b0

0x00_0000

Memory Map Register Space

Scenario with: CSL_SEL = 1'b1

0x00_0000

Memory Map Register Space

RAM or NVM start address
ADCCBP+(ADCCROFF_0) ADCCBP+(ADCCROFF_0+
ADCCIDX(max)) ADCCBP+(ADCCROFF_1) ADCCBP+(ADCCROFF_1+
ADCCIDX(max))

RAM or NVM Space CSL_0 (active) CSL_1 (alternative)

RAM / NVM start address
ADCCBP+(ADCCROFF_0) ADCCBP+(ADCCROFF_0+
ADCCIDX(max)) ADCCBP+(ADCCROFF_1) ADCCMDP+(ADCCROFF_1+
ADCCIDX(max))

RAM or NVM Space CSL_0 (alternative) CSL_1 (active)

RAM or NVM end address

RAM or NVM end address

Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index
Figure 9-31. Command Sequence List Schema in Double Buffer Mode

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CSL_SEL = 1'b0 (forced by CSL_BMOD)

0x00_0000

Memory Map Register Space

RAM or NVM start address
ADCCBP+(ADCCROFF_0) ADCCBP+(ADCCROFF_0+
ADCCIDX(max))

RAM or NVM Space CSL_0 (active)

RAM or NVM end address
Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index
Figure 9-32. Command Sequence List Schema in Single Buffer Mode
While the ADC is enabled, one CSL is active (indicated by bit CSL_SEL) and the corresponding list should not be modified anymore. At the same time the alternative CSL can be modified to prepare the ADC for new conversion sequences in CSL double buffered mode. When the ADC is enabled, the command address registers (ADCCBP, ADCCROFF_0/2, ADCCIDX) are read only and register ADCCIDX is under control of the ADC.

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9.6.3.2.3 Introduction of the two Result Value Lists (RVLs)
The same list-based architecture as described above for the CSL has been implemented for the Result Value List (RVL) with corresponding address registers (ADCRBP, ADCCROFF_0/1, ADCRIDX). The final address for conversion result storage is calculated by the sum of these registers (e.g.: ADCRBP+ADCCROFF_0+ADCRIDX or ADCRBP+ADCCROFF_1+ADCRIDX). The RVL_BMOD bit selects if the RVL is used in double buffer or single buffer mode. In double buffer mode the RVL is swapped:
· Each time an "End Of List" command type got executed followed by the first conversion from top of the next CSL and related (first) result is about to be stored
· A CSL got aborted (bit SEQA=1'b1) and ADC enters idle state (becomes ready for new flow control events)
Using the RVL in double buffer mode the RVL is not swapped after exit from Stop Mode or Wait Mode with bit SWAI set. Hence the RVL used before entry of Stop or Wait Mode with bit SWAI set is overwritten after exit from the MCU Operating Mode (see also Section 9.3.1.2, "MCU Operating Modes). Which list is actively used for the ADC conversion result storage is indicated by bit RVL_SEL. The register to define the RVL start addresses (ADCRBP) can be set to any even location of the system RAM area. It is the user's responsibility to make sure that the different ADC lists do not overlap or exceed the system RAM area. The error flag IA_EIF will be set for accesses to ranges outside system RAM area and cause an error interrupt if enabled.

Scenario with: RVL_SEL = 1'b0

0x00_0000

Memory Map Register Space

Scenario with: RVL_SEL = 1'b1

0x00_0000

Memory Map Register Space

RAM start address
ADCRBP+(ADCCROFF_0) ADCRBP+(ADCCROFF_0+
ADCRIDX(max)) ADCRBP+(ADCCROFF_1) ADCRBP+(ADCCROFF_1+
ADCRIDX(max))

RAM Space RVL_0 (active) RVL_1 (alternative)

RAM start address
ADCRBP+(ADCCROFF_0) ADCRBP+(ADCCROFF_0+
ADCRIDX(max)) ADCRBP+(ADCCROFF_1) ADCRBP+(ADCCROFF_1+
ADCRIDX(max))

RAM Space RVL_0 (alternative) RVL_1 (active)

RAM end address

RAM end address

Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index
Figure 9-33. Result Value List Schema in Double Buffer Mode

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RVL_SEL = 1'b0 (forced by bit RVL_BMOD)

0x00_0000

Memory Map Register Space

RAM start address
ADCRBP+(ADCCROFF_0) ADCRBP+(ADCCROFF_0+
ADCRIDX(max))

RAM Space RVL_0 (active)

RAM end address

Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index
Figure 9-34. Result Value List Schema in Single Buffer Mode
While ADC is enabled, one Result Value List is active (indicated by bit RVL_SEL). The conversion Result Value List can be read anytime. When the ADC is enabled the conversion result address registers (ADCRBP, ADCCROFF_0/1, ADCRIDX) are read only and register ADCRIDX is under control of the ADC.
A conversion result is always stored as 16bit entity in unsigned data representation. Left and right justification inside the entity is selected via the DJM control bit. Unused bits inside an entity are stored zero.
Table 9-33. Conversion Result Justification Overview

Conversion Resolution (SRES[1:0]) 8 bit 10 bit 12 bit

Left Justified Result (DJM = 1'b0)
{Result[7:0],8'b00000000} {Result[9:0],6'b000000} {Result[11:0],4'b0000}

Right Justified Result (DJM = 1'b1)
{8'b00000000,Result[7:0]} {6'b000000,Result[9:0]} {4'b0000,Result[11:0]}

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9.6.3.2.4 The two conversion flow control Mode Configurations
The ADC provides two modes ("Trigger Mode" and "Restart Mode") which are different in the conversion control flow. The "Restart Mode" provides precise timing control about the sample start point but is more complex from the flow control perspective, while the "Trigger Mode" is more simple from flow control point of view but is less controllable regarding conversion sample start.
Following are the key differences:
In "Trigger Mode" configuration, when conversion flow control bit RSTA gets set the bit TRIG gets set automatically. Hence in "Trigger Mode" the applications should not set the bit TRIG and bit RSTA simultaneously (via data bus or internal interface), because it is a flow control failure and the ADC will cease operation.
In "Trigger Mode" configuration, after the execution of the initial Restart Event the current CSL can be executed and controlled via Trigger Events only. Hence, if the "End Of List" command is reached a restart of conversion flow from top of current CSL does not require to set bit RSTA because returning to the top of current CSL is done automatically. Therefore the current CSL can be executed again after the "End Of List" command type is executed by a Trigger Event only.
In "Restart Mode" configuration, the execution of a CSL is controlled via Trigger Events and Restart Events. After execution of the "End Of List" command the conversion flow must be continued by a Restart Event followed by a Trigger Event and the Trigger Event must not occur before the Restart Event has finished.
For more details and examples regarding flow control and application use cases please see following section and Section 9.9.7, "Conversion flow control application information.
9.6.3.2.5 The four ADC conversion flow control bits
There are four bits to control conversion flow (execution of a CSL and CSL exchange in double buffer mode). Each bit is controllable via the data bus and internal interface depending on the setting of ACC_CFG[1:0] bits (see also Figure 9-2). In the following the conversion control event to control the conversion flow is given with the related internal interface signal and corresponding register bit name together with information regarding:
-- Function of the conversion control event -- How to request the event -- When is the event finished -- Mandatory requirements to executed the event
A summary of all event combinations is provided by Table 9-11.
· Trigger Event Internal Interface Signal: Trigger Corresponding Bit Name: TRIG

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­ Function: Start the first conversion of a conversion sequence which is defined in the active Command Sequence List
­ Requested by: - Positive edge of internal interface signal Trigger - Write Access via data bus to set control bit TRIG
­ When finished: This bit is cleared by the ADC when the first conversion of the sequence is beginning to sample
­ Mandatory Requirements: - In all ADC conversion flow control modes bit TRIG is only set (Trigger Event executed) if the Trigger Event occurs while no conversion or conversion sequence is ongoing (ADC idle) - In ADC conversion flow control mode "Restart Mode" with a Restart Event in progress it is not allowed that a Trigger Event occurs before the background command load phase has finished (Restart Event has been executed) else the error flag TRIG_EIF is set - In ADC conversion flow control mode "Trigger Mode" a Restart Event causes bit TRIG being set automatically. Bit TRIG is set when no conversion or conversion sequence is ongoing (ADC idle) and the RVL done condition is reached by one of the following: * A "End Of List" command type has been executed * A Sequence Abort Event is in progress or has been executed The ADC executes the Restart Event followed by the Trigger Event. - In ADC conversion flow control mode "Trigger Mode" a Restart Event and a simultaneous Trigger Event via internal interface or data bus causes the TRIG_EIF bit being set and ADC cease operation.
· Restart Event (with current active CSL) Internal Interface Signal: Restart Corresponding Bit Name: RSTA
­ Function: - Go to top of active CSL (clear index register for CSL) - Load one background command register and wait for Trigger (CSL offset register is not switched independent of bit CSL_BMOD) - Set error flag RSTA_EIF when a Restart Request occurs before one of the following conditions was reached: * The "End Of List" command type has been executed * Depending on bit STR_SEQA if the "End Of List" command type is about to be executed * The current CSL has been aborted or is about to be aborted due to a Sequence Abort Request.
­ Requested by: - Positive edge of internal interface signal Restart - Write Access via data bus to set control bit RSTA

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­ When finished: This bit is cleared when the first conversion command of the sequence from top of active Sequence Command List is loaded
­ Mandatory Requirement: - In all ADC conversion flow control modes a Restart Event causes bit RSTA to be set. Bit SEQA is set simultaneously by ADC hardware if: * ADC not idle (a conversion or conversion sequence is ongoing and current CSL not finished) and no Sequence Abort Event in progress (bit SEQA not already set or set simultaneously via internal interface or data bus) * ADC idle but RVL done condition not reached The RVL done condition is reached by one of the following: * A "End Of List" command type has been executed * A Sequence Abort Event is in progress or has been executed (bit SEQA already set or set simultaneously via internal interface or data bus) The ADC executes the Sequence Abort Event followed by the Restart Event for the conditions described before or only a Restart Event. - In ADC conversion flow control mode "Trigger Mode" a Restart Event causes bit TRIG being set automatically. Bit TRIG is set when no conversion or conversion sequence is ongoing (ADC idle) and the RVL done condition is reached by one of the following: * A "End Of List" command type has been executed * A Sequence Abort Event is in progress or has been executed The ADC executes the Restart Event followed by the Trigger Event. - In ADC conversion flow control mode "Trigger Mode" a Restart Event and a simultaneous Trigger Event via internal interface or data bus causes the TRIG_EIF bit being set and ADC cease operation.
· Restart Event + CSL Exchange (Swap) Internal Interface Signals: Restart + LoadOK Corresponding Bit Names: RSTA + LDOK
­ Function: Go to top of active CSL (clear index register for CSL) and switch to other offset register for address calculation if configured for double buffer mode (exchange the CSL list)
Requested by: - Internal interface with the assertion of Interface Signal Restart the interface Signal LoadOK is evaluated and bit LDOK is set accordingly (bit LDOK set if Interface Signal LoadOK asserted when Interface Signal Restart asserts). - Write Access via data bus to set control bit RSTA simultaneously with bit LDOK.
­ When finished: Bit LDOK can only be cleared if it was set as described before and both bits (LDOK, RSTA) are cleared when the first conversion command from top of active Sequence Command List is loaded
­ Mandatory Requirement: No ongoing conversion or conversion sequence Details if using the internal interface:

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If signal Restart is asserted before signal LoadOK is set the conversion starts from top of currently active CSL at the next Trigger Event (no exchange of CSL list). If signal Restart is asserted after or simultaneously with signal LoadOK the conversion starts from top of the other CSL at the next Trigger Event (CSL is switched) if CSL is configured for double buffer mode.
· Sequence Abort Event Internal Interface Signal: Seq_Abort Corresponding Bit Name: SEQA
­ Function: Abort any possible ongoing conversion at next conversion boundary and abort current conversion sequence and active CSL
­ Requested by: - Positive edge of internal interface signal Seq_Abort - Write Access via data bus to set control bit SEQA
­ When finished: This bit gets cleared when an ongoing conversion is finished and the result is stored and/or an ongoing conversion sequence is aborted and current active CSL is aborted (ADC idle, RVL done)
­ Mandatory Requirement: - In all ADC conversion flow control modes bit SEQA can only be set if: * ADC not idle (a conversion or conversion sequence is ongoing) * ADC idle but RVL done condition not reached The RVL done condition is not reached if: * An "End Of List" command type has not been executed * A Sequence Abort Event has not been executed (bit SEQA not already set) - In all ADC conversion flow control modes a Sequence Abort Event can be issued at any time - In ADC conversion flow control mode "Restart Mode" after a conversion sequence abort request has been executed it is mandatory to set bit RSTA. If a Trigger Event occurs before a Restart Event is executed (bit RSTA set and cleared by hardware), bit TRIG is set, error flag TRIG_EIF is set, and the ADC can only be continued by a Soft-Reset. After the Restart Event the ADC accepts new Trigger Events (bit TRIG set) and begins conversion from top of the currently active CSL. - In ADC conversion flow control mode "Restart Mode" after a Sequence Abort Event has been executed, a Restart Event causes only the RSTA bit being set. The ADC executes a Restart Event only.
­ In both conversion flow control modes ("Restart Mode" and "Trigger Mode") when conversion flow control bit RSTA gets set automatically bit SEQA gets set when the ADC has not reached one of the following scenarios: * An "End Of List" command type has been executed or is about to be executed * A Sequence Abort request is about to be executed or has been executed. In case bit SEQA is set automatically the Restart error flag RSTA_EIF is set to indicate an unexpected Restart Request.

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9.6.3.2.6

Conversion flow control in case of conversion sequence control bit overrun scenarios

Restart Request Overrun: If a legal Restart Request is detected and no Restart Event is in progress, the RSTA bit is set due to the request. The set RSTA bit indicates that a Restart Request was detected and the Restart Event is in process. In case further Restart Requests occur while the RSTA bit is set, this is defined a overrun situation. This scenario is likely to occur when bit STR_SEQA is set or when a Restart Event causes a Sequence Abort Event. The request overrun is captured in a background register that always stores the last detected overrun request. Hence if the overrun situation occurs more than once while a Restart Event is in progress, only the latest overrun request is pending. When the RSTA bit is cleared, the latest overrun request is processed and RSTA is set again one cycle later.

LoadOK Overrun: Simultaneously at any Restart Request overrun situation the LoadOK input is evaluated and the status is captured in a background register which is alternated anytime a Restart Request Overrun occurs while Load OK Request is asserted. The Load OK background register is cleared as soon as the pending Restart Request gets processed.

Trigger Overrun: If a Trigger occurs whilst bit TRIG is already set, this is defined as a Trigger overrun situation and causes the ADC to cease conversion at the next conversion boundary and to set bit TRIG_EIF. A overrun is also detected if the Trigger Event occurs automatically generated by hardware in "Trigger Mode" due to a Restart Event and simultaneously a Trigger Event is generated via data bus or internal interface. In this case the ADC ceases operation before conversion begins to sample. In "Trigger Mode" a Restart Request Overrun does not cause a Trigger Overrun (bit TRIG_EIF not set).

Sequence Abort Request Overrun: If a Sequence Abort Request occurs whilst bit SEQA is already set, this is defined as a Sequence Abort Request Overrun situation and the overrun request is ignored.

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9.6.3.3

ADC List Usage and Conversion/Conversion Sequence Flow Description

It is the user's responsibility to make sure that the different lists do not overlap or exceed the system RAM area respectively the CSL does not exceed the NVM area if located in the NVM. The error flag IA_EIF will be set for accesses done outside the system RAM area and will cause an error interrupt if enabled for lists that are located in the system RAM.

Generic flow for ADC register load at conversion sequence start/restart:
· It is mandatory that the ADC is idle (no ongoing conversion or conversion sequence).
· It is mandatory to have at least one CSL with valid entries. See also Section 9.9.7.2, "Restart CSL execution with currently active CSL or Section 9.9.7.3, "Restart CSL execution with new/other CSL (alternative CSL becomes active CSL) -- CSL swapping for more details on possible scenarios.
· A Restart Event occurs, which causes the index registers to be cleared (register ADCCIDX and ADCRIDX are cleared) and to point to the top of the corresponding lists (top of active RVL and CSL).
· Load conversion command to background conversion command register 1.
· The control bit(s) RSTA (and LDOK if set) are cleared.
· Wait for Trigger Event to start conversion.

Generic flow for ADC register load during conversion: · The index registers ADCCIDX is incremented. · The inactive background command register is loaded with a new conversion command.

Generic flow for ADC result storage at end of conversion:
· Index register ADCRIDX is incremented and the conversion result is stored in system RAM. As soon as the result is successfully stored, any conversion interrupt flags are set accordingly.
· At the conversion boundary the other background command register becomes active and visible in the ADC register map.
· If the last executed conversion command was of type "End Of Sequence", the ADC waits for the Trigger Event.
· If the last executed conversion command was of type "End Of List" and the ADC is configured in "Restart Mode", the ADC sets all related flags and stays idle awaiting a Restart Event to continue.
· If the last executed conversion command was of type "End Of List" and the ADC is configured in "Trigger Mode", the ADC sets all related flags and automatically returns to top of current CSL and is awaiting a Trigger Event to continue.
· If the last executed conversion command was of type "Normal Conversion" the ADC continues command execution in the order of the current CSL (continues conversion).

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9.7 Resets
At reset the ADC12B_LBA is disabled and in a power down state. The reset state of each individual bit is listed within Section 9.5.2, "Register Descriptions" which details the registers and their bit-fields.
9.8 Interrupts
The ADC supports three types of interrupts: · Conversion Interrupt · Sequence Abort Interrupt · Error and Conversion Flow Control Issue Interrupt
Each of the interrupt types is associated with individual interrupt enable bits and interrupt flags.
9.8.1 ADC Conversion Interrupt
The ADC provides one conversion interrupt associated to 16 interrupt enable bits with dedicated interrupt flags. The 16 interrupt flags consist of:
· 15 conversion interrupt flags which can be associated to any conversion completion. · One additional interrupt flag which is fixed to the "End Of List" conversion command type within
the active CSL. The association of the conversion number with the interrupt flag number is done in the conversion command.
9.8.2 ADC Sequence Abort Done Interrupt
The ADC provides one sequence abort done interrupt associated with the sequence abort request for conversion flow control. Hence, there is only one dedicated interrupt flag and interrupt enable bit for conversion sequence abort and it occurs when the sequence abort is done.

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9.8.3 ADC Error and Conversion Flow Control Issue Interrupt
The ADC provides one error interrupt for four error classes related to conversion interrupt overflow, command validness, DMA access status and Conversion Flow Control issues, and CSL failure. The following error interrupt flags belong to the group of severe issues which cause an error interrupt if enabled and cease ADC operation:
· IA_EIF · CMD_EIF · EOL_EIF · TRIG_EIF
In order to make the ADC operational again, an ADC Soft-Reset must be issued which clears the above listed error interrupt flags.
NOTE It is important to note that if flag DBECC_ERR is set, the ADC ceases operation as well, but does not cause an ADC error interrupt. Instead, a machine exception is issued. In order to make the ADC operational again an ADC Soft-Reset must be issued.
Remaining error interrupt flags cause an error interrupt if enabled, but ADC continues operation. The related interrupt flags are:
· RSTAR_EIF · LDOK_EIF · CONIF_OIF

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9.9 Use Cases and Application Information
9.9.1 List Usage -- CSL single buffer mode and RVL single buffer mode
In this use case both list types are configured for single buffer mode (CSL_BMOD=1'b0 and RVL_BMOD=1'b0, CSL_SEL and RVL_SEL are forced to 1'b0). The index register for the CSL and RVL are cleared to start from the top of the list with next conversion command and result storage in the following cases:
· The conversion flow reaches the command containing the "End-of-List" command type identifier · A Restart Request occurs at a sequence boundary · After an aborted conversion or conversion sequence

CSL_0

RVL_0

CSL_1 (unused)

RVL_1 (unused)

Figure 9-35. CSL Single Buffer Mode -- RVL Single Buffer Mode Diagram
9.9.2 List Usage -- CSL single buffer mode and RVL double buffer mode
In this use case the CSL is configured for single buffer mode (CSL_BMOD=1'b0) and the RVL is configured for double buffer mode (RVL_BMOD=1'b1). In this buffer configuration only the result list RVL is switched when the first conversion result of a CSL is stored after a CSL was successfully finished or a CSL got aborted.

CSL_0

RVL_0

CSL_1 (unused)

RVL_1

Figure 9-36. CSL Single Buffer Mode -- RVL Single Buffer Mode Diagram
The last entirely filled RVL (an RVL where the corresponding CSL has been executed including the "End Of List " command type) is shown by register ADCEOLRI. The CSL is used in single buffer mode and bit CSL_SEL is forced to 1'b0.

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9.9.3 List Usage -- CSL double buffer mode and RVL double buffer mode
In this use case both list types are configured for double buffer mode (CSL_BMOD=1'b1 and RVL_BMOD=1'b1) and whenever a Command Sequence List (CSL) is finished or aborted the command Sequence List is swapped by the simultaneous assertion of bits LDOK and RSTA.

CSL_0

RVL_0

CSL_1

RVL_1

Figure 9-37. CSL Double Buffer Mode -- RVL Double Buffer Mode Diagram
This use case can be used if the channel order or CSL length varies very frequently in an application.
9.9.4 List Usage -- CSL double buffer mode and RVL single buffer mode
In this use case the CSL is configured for double buffer mode (CSL_BMOD=1'b1) and the RVL is configured for single buffer mode (RVL_BMOD=1'b0). The two command lists can be different sizes and the allocated result list memory area in the RAM must be able to hold as many entries as the larger of the two command lists. Each time when the end of a Command Sequence List is reached, if bits LDOK and RSTA are set, the commands list is swapped.

CSL_0

RVL_0

CSL_1

RVL_1 (unused)

Figure 9-38. CSL Double Buffer Mode -- RVL Single Buffer Mode Diagram

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9.9.5 List Usage -- CSL double buffer mode and RVL double buffer mode
In this use case both list types are configured for double buffer mode (CSL_BMOD=1'b1) and RVL_BMOD=1'b1).
This setup is the same as Section 9.9.3, "List Usage -- CSL double buffer mode and RVL double buffer mode but at the end of a CSL the CSL is not always swapped (bit LDOK not always set with bit RSTA). The Result Value List is swapped whenever a CSL is finished or a CSL got aborted.

CSL_0

RVL_0

CSL_1

RVL_1

Figure 9-39. CSL Double Buffer Mode -- RVL Double Buffer Mode Diagram

9.9.6 RVL swapping in RVL double buffer mode and related registers ADCIMDRI and ADCEOLRI
When using the RVL in double buffer mode, the registers ADCIMDRI and ADCEOLRI can be used by the application software to identify which RVL holds relevant and latest data and which CSL is related to this data. These registers are updated at the setting of one of the CON_IF[15:1] or the EOL_IF interrupt flags. As described in the register description Section 9.5.2.13, "ADC Intermediate Result Information Register (ADCIMDRI) and Section 9.5.2.14, "ADC End Of List Result Information Register (ADCEOLRI), the register ADCIMDRI, for instance, is always updated at the occurrence of a CON_IF[15:1] interrupt flag amongst other cases. Also each time the last conversion command of a CSL is finished and the corresponding result is stored, the related EOL_IF flag is set and register ADCEOLRI is updated. Hence application software can pick up conversion results, or groups of results, or an entire result list driven fully by interrupts. A use case example diagram is shown in Figure 9-40.

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Initial Restart Event

Stop Mode request while conversion ongoing and before EOL

Wake-up Event with AUT_RSTA= 1'b1

CSL Buffer

CSL_0

CSL_1

CSL_0

CSL_0

RVL Buffer

INT_1

EOL tdelay

INT_2 EOL

RVL_0

RVL_1

bits not valid until first EOL

bits are valid

Stop Mode entry

INT_1 return to execute from top of CSL

RVL swap due to EOL followed by first result of next CSL to store

no RVL swap

RVL_0

RVL values before Stop Mode entry are overwritten

RVL_EOL CSL_EOL EOL_IF

1'b0

1'b1

1'b0

1'b1

1'b1

1'b1

set by hardware

cleared by software before next EOL

should be cleared by software before Stop Mode entry

bits not valid until first INT

bits are valid

RVL_IMD

1'b0

1'b1

CSL_IMD

1'b0

1'b1

RIDX_IMD[5:0] 0x00 0x05

0x0A

0x08 0x0B

CON_IF[15:1] 0x0000 0x0001 0x0000

0x0010

1'b0 1'b0
0x05
0x0001

Flag should be cleared by software before it is set again

t

Comments:

EOL: INT_x: tdelay:

"End Of List" command type processed One of the CON_IF interrupt flags occurs Delay can vary depending on the DMA performance, and ADC configuration (conversion flow using the Trigger to proceed through the CSL)

Figure 9-40. RVL Swapping -- Use Case Diagram

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9.9.7 Conversion flow control application information
The ADC12B_LBA provides various conversion control scenarios to the user accomplished by the following features.
The ADC conversion flow control can be realized via the data bus only, the internal interface only, or by both access methods. The method used is software configurable via bits ACC_CFG[1:0].
The conversion flow is controlled via the four conversion flow control bits: SEQA, TRIG, RSTA, and LDOK.
Two different conversion flow control modes can be configured: Trigger Mode or Restart Mode
Single or double buffer configuration of CSL and RVL.
9.9.7.1 Initial Start of a Command Sequence List
At the initial start of a Command Sequence List after device reset all entries for at least one of the two CSL must have been completed and data must be valid. Depending on if the CSL_0 or the CSL_1 should be executed at the initial start of a Command Sequence List the following conversion control sequence must be applied:
If CSL_0 should be executed at the initial conversion start after device reset: A Restart Event and a Trigger Event must occur (depending to the selected conversion flow control mode the events must occur one after the other or simultaneously) which causes the ADC to start conversion with commands loaded from CSL_0.
If CSL_1 should be executed at the initial conversion start after device reset: Bit LDOK must be set simultaneously with the Restart Event followed by a Trigger Event (depending on the selected conversion flow control mode the Trigger events must occur simultaneously or after the Restart Event is finished). As soon as the Trigger Event gets executed the ADC starts conversion with commands loaded from CSL_1.
As soon as a new valid Restart Event occurs the flow for ADC register load at conversion sequence start as described in Section 9.6.3.3, "ADC List Usage and Conversion/Conversion Sequence Flow Description applies.
9.9.7.2 Restart CSL execution with currently active CSL
To restart a Command Sequence List execution it is mandatory that the ADC is idle (no conversion or conversion sequence is ongoing).
If necessary, a possible ongoing conversion sequence can be aborted by the Sequence Abort Event (setting bit SEQA). As soon as bit SEQA is cleared by the ADC, the current conversion sequence has been aborted and the ADC is idle (no conversion sequence or conversion ongoing).
After a conversion sequence abort is executed it is mandatory to request a Restart Event (bit RSTA set). After the Restart Event is finished (bit RSTA is cleared), the ADC accepts a new Trigger Event (bit TRIG can be set) and begins conversion from the top of the currently active CSL. In conversion flow control

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mode "Trigger Mode" only a Restart Event is necessary if ADC is idle to restart Conversion Sequence List execution (the Trigger Event occurs automatically).
It is possible to set bit RSTA and SEQA simultaneously, causing a Sequence Abort Event followed by a Restart Event. In this case the error flags behave differently depending on the selected conversion flow control mode:
· Setting both flow control bits simultaneously in conversion flow control mode "Restart Mode" prevents the error flags RSTA_EIF and LDOK_EIF from occurring.
· Setting both flow control bits simultaneously in conversion flow control mode "Trigger Mode" prevents the error flag RSTA_EIF from occurring.
If only a Restart Event occurs while ADC is not idle and bit SEQA is not set already (Sequence Abort Event in progress) a Sequence Abort Event is issued automatically and bit RSTAR_EIF is set.
Please see also the detailed conversion flow control bit mandatory requirements and execution information for bit RSTA and SEQA described in Section 9.6.3.2.5, "The four ADC conversion flow control bits.

9.9.7.3

Restart CSL execution with new/other CSL (alternative CSL becomes active CSL) -- CSL swapping

After all alternative conversion command list entries are finished the bit LDOK can be set simultaneously with the next Restart Event to swap command buffers.

To start conversion command list execution it is mandatory that the ADC is idle (no conversion or conversion sequence is ongoing).

If necessary, a possible ongoing conversion sequence can be aborted by the Sequence Abort Event (setting bit SEQA). As soon as bit SEQA is cleared by the ADC, the current conversion sequence has been aborted and the ADC is idle (no conversion sequence or conversion ongoing).

After a conversion sequence abort is executed it is mandatory to request a Restart Event (bit RSTA set) and simultaneously set bit LDOK to swap the CSL buffer. After the Restart Event is finished (bit RSTA and LDOK are cleared), the ADC accepts a new Trigger Event (bit TRIG can be set) and begins conversion from the top of the newly selected CSL buffer. In conversion flow control mode "Trigger Mode" only a Restart Event (simultaneously with bit LDOK being set) is necessary to restart conversion command list execution with the newly selected CSL buffer (the Trigger Event occurs automatically).

It is possible to set bits RSTA, LDOK and SEQA simultaneously, causing a Sequence Abort Event followed by a Restart Event. In this case the error flags behave differently depending on the selected conversion flow control mode:
· Setting these three flow control bits simultaneously in "Restart Mode" prevents the error flags RSTA_EIF and LDOK_EIF from occurring.
· Setting these three flow control bits simultaneously in "Trigger Mode" prevents the error flag RSTA_EIF from occurring.

If only a Restart Event occurs while ADC is not idle and bit SEQA is not set already (Sequence Abort Event in progress) a Sequence Abort Event is issued automatically and bit RSTAR_EIF is set.

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Please see also the detailed conversion flow control bit mandatory requirements and execution information for bit RSTA and SEQA described in Section 9.6.3.2.5, "The four ADC conversion flow control bits.

9.9.8 Continuous Conversion
Applications that only need to continuously convert a list of channels, without the need for timing control or the ability to perform different sequences of conversions (grouped number of different channels to convert) can make use of the following simple setup:
· "Trigger Mode" configuration · Single buffer CSL · Depending on data transfer rate either use single or double buffer RVL configuration · Define a list of conversion commands which only contains the "End Of List" command with
automatic wrap to top of CSL
After finishing the configuration and enabling the ADC an initial Restart Event is sufficient to launch the continuous conversion until next device reset or low power mode.
In case a Low Power Mode is used: If bit AUT_RSTA is set before Low Power Mode is entered the conversion continues automatically as soon as a low power mode (Stop Mode or Wait Mode with bit SWAI set) is exited.

Initial Restart Event

Stop Mode request, Wake-up

Automatic Sequence Abort Event with

Event

AUT_RSTA

AN3 AN1 AN4 IN5 AN3 AN1 AN4 IN5 AN3 AN1

AN3 AN1 AN4

CSL_0

EOL Active

EOL Stop Mode entry

Abort

Idle

Idle

Active

t

Figure 9-41. Conversion Flow Control Diagram -- Continuous Conversion (with Stop Mode)

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9.9.9 Triggered Conversion -- Single CSL
Applications that require the conversion of one or more groups of different channels in a periodic and timed manner can make use of a configuration in "Trigger Mode" with a single CSL containing a list of sequences. This means the CSL consists of several sequences each separated by an "End of Sequence" command. The last command of the CSL uses the "End Of List" command with wrap to top of CSL and waiting for a Trigger (CMD_SEL[1:0] =2'b11). Hence after the initial Restart Event each sequence can be launched via a Trigger Event and repetition of the CSL can be launched via a Trigger after execution of the "End Of List" command.

Initial Restart Event

Trigger

Trigger

Trigger

Repetition of CSL_0

AN3 AN1 AN4 IN5 AN2 AN0 AN4 IN3 AN6 AN1 IN1 AN3 AN1 AN4

Sequence_0 EOS

Sequence_1

Sequence_2

Sequence_0

EOS

EOL

CSL_0

Active

t

Figure 9-42. Conversion Flow Control Diagram -- Triggered Conversion (CSL Repetition)

initial Restart Event

Stop Mode request,

Automatic Sequence Abort

Trigger

Trigger Event

Wake-up Begin from top of current CSL

Event with AUT_RSTA

Trigger

AN3 AN1 AN4 IN5 AN21AN0 AN4 IN3 AN6 AN1

Sequence_0

Sequence_1

Sequence_2

EOS

EOS Stop Mode

entry

Abort

CSL_0

Active

Idle

AN3 AN1 AN4 AN5 AN2 AN0

Sequence_0

Sequence_1

EOS

Idle

Active

t

Figure 9-43. Conversion Flow Control Diagram -- Triggered Conversion (with Stop Mode)

In case a Low Power Mode is used: If bit AUT_RSTA is set before Low Power Mode is entered, the conversion continues automatically as soon as a low power mode (Stop Mode or Wait Mode with bit SWAI set) is exited.

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9.9.10 Fully Timing Controlled Conversion
As described previously, in "Trigger Mode" a Restart Event automatically causes a trigger. To have full and precise timing control of the beginning of any conversion/sequence the "Restart Mode" is available. In "Restart Mode" a Restart Event does not cause a Trigger automatically; instead, the Trigger must be issued separately and with correct timing, which means the Trigger is not allowed before the Restart Event (conversion command loading) is finished (bit RSTA=1'b0 again). The time required from Trigger until sampling phase starts is given (refer to Section 9.5.2.6, "ADC Conversion Flow Control Register (ADCFLWCTL), Timing considerations) and hence timing is fully controllable by the application. Additionally, if a Trigger occurs before a Restart Event is finished, this causes the TRIG_EIF flag being set. This allows detection of false flow control sequences.

any Restart Event Trigger

Stop Mode request,

Automatic Sequence Abort

Trigger

Trigger Event

Wake-up Begin from top of current CSL

Event with AUT_RSTA

Trigger

AN3 AN1 AN4 IN5 AN21AN0 AN4 IN3 AN6 AN1

Sequence_0

Sequence_1

Sequence_2

conversion command load phase

EOS

EOS Stop Mode entry Abort

CSL_0

Active

Idle

AN3 AN1 AN4 AN5 AN2 AN0

Sequence_0

Sequence_1

EOS

Idle

Active

t

Figure 9-44. Conversion Flow Control Diagram -- Fully Timing Controlled Conversion (with Stop Mode)
Unlike the Stop Mode entry shown in Figure 9-43 and Figure 9-44 it is recommended to issue the Stop Mode at sequence boundaries (when ADC is idle and no conversion/conversion sequence is ongoing).
Any of the Conversion flow control application use cases described above (Continuous, Triggered, or Fully Timing Controlled Conversion) can be used with CSL single buffer mode or with CSL double buffer mode. If using CSL double buffer mode, CSL swapping is performed by issuing a Restart Event with bit LDOK set.

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Table 10-1. Revision History Table

Rev. No. (Item No.)

Data

V01.00 15 Dec 2010 V02.00 16 Mar 2011

Sections Affected
all
10.3.2.1 10.4.2.1

Substantial Change(s)
Initial Version - added BVLS[1] to support four voltage level - moved BVHS to register bit 6

V03.00 26 Apr 2011

all

- removed Vsense

V03.10 04 Oct 2011

10.4.2.1 and 10.4.2.2

- removed BSESE

10.1 Introduction
The BATS module provides the functionality to measure the voltage of the chip supply pin VSUP.

10.1.1 Features
The VSUP pin can be routed via an internal divider to the internal Analog to Digital Converter. Independent of the routing to the Analog to Digital Converter, it is possible to route this voltage to a comparator to generate a low or a high voltage interrupt to alert the MCU.

10.1.2 Modes of Operation
The BATS module behaves as follows in the system power modes:
1. Run mode The activation of the VSUP Level Sense Enable (BSUSE=1) or ADC connection Enable (BSUAE=1) closes the path from VSUP pin through the resistor chain to ground and enables the associated features if selected.
2. Stop mode
During stop mode operation the path from the VSUP pin through the resistor chain to ground is opened and the low and high voltage sense features are disabled. The content of the configuration register is unchanged.

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10.1.3 Block Diagram
Figure 10-1 shows a block diagram of the BATS module. See device guide for connectivity to ADC channel.
Figure 10-1. BATS Block Diagram
VSUP

...

BVLS[1:0] BVHS
BSUSE
1

BVLC BVHC
Comparator

to ADC

BSUAE
1 automatically closed if BSUSE and/or BSUAE is active, open during Stop mode
10.2 External Signal Description
This section lists the name and description of all external ports.
10.2.1 VSUP -- Voltage Supply Pin
This pin is the chip supply. It can be internally connected for voltage measurement. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC or to a comparator.

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10.3 Memory Map and Register Definition
This section provides the detailed information of all registers for the BATS module.

10.3.1 Register Summary
Figure 10-2 shows the summary of all implemented registers inside the BATS module.
NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level.

Address Offset Register Name

Bit 7

6

5

4

3

2

1

Bit 0

0x0000 BATE

R

0

W

0x0001 BATSR

R

0

W

0x0002 BATIE

R

0

W

0x0003 BATIF

R

0

W

0x0004 - 0x0005 R

0

Reserved

W

BVHS 0 0 0 0

BVLS[1:0]

0

0

0

0

BSUAE BSUSE

0

0

BVHC

BVLC

0

0

0

0

BVHIE

BVLIE

0

0

0

0

BVHIF

BVLIF

0

0

0

0

0

0

0x0006 - 0x0007 R

Reserved

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W

= Unimplemented Figure 10-2. BATS Register Summary

10.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Unused bits read back zero.

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10.3.2.1 BATS Module Enable Register (BATE)

Module Base + 0x0000

7

R

0

W

Reset

0

1. Read: Anytime Write: Anytime

6
BVHS

5

4

BVLS[1:0]

3
BSUAE

2
BSUSE

0

0

0

0

0

= Unimplemented

Figure 10-3. BATS Module Enable Register (BATE)

Access: User read/write(1)

1

0

0

0

0

0

Table 10-2. BATE Field Description

Field

Description

6 BVHS

BATS Voltage High Select -- This bit selects the trigger level for the Voltage Level High Condition (BVHC). 0 Voltage level VHBI1 is selected 1 Voltage level VHBI2 is selected

5:4 BVLS[1:0]

BATS Voltage Low Select -- This bit selects the trigger level for the Voltage Level Low Condition (BVLC). 00 Voltage level VLBI1 is selected 01 Voltage level VLBI2 is selected 10 Voltage level VLBI3 is selected 11 Voltage level VLBI4 is selected

3 BSUAE

BATS VSUP ADC Connection Enable -- This bit connects the VSUP pin through the resistor chain to ground and connects the ADC channel to the divided down voltage. 0 ADC Channel is disconnected 1 ADC Channel is connected

2

BATS VSUP Level Sense Enable -- This bit connects the VSUP pin through the resistor chain to ground and

BSUSE enables the Voltage Level Sense features measuring BVLC and BVHC.

0 Level Sense features disabled 1 Level Sense features enabled

NOTE
When opening the resistors path to ground by changing BSUSE or BSUAE then for a time TEN_UNC + two bus cycles the measured value is invalid. This is to let internal nodes be charged to correct value. BVHIE, BVLIE might be cleared for this time period to avoid false interrupts.

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10.3.2.2 BATS Module Status Register (BATSR)

Module Base + 0x0001

Access: User read only(1)

7

R

0

W

Reset

0

1. Read: Anytime Write: Never

6

5

4

3

2

0

0

0

0

0

0

0

0

0

0

= Unimplemented

Figure 10-4. BATS Module Status Register (BATSR)

1
BVHC
0

0
BVLC
0

Field 1
BVHC
0 BVLC

Table 10-3. BATSR - Register Field Descriptions
Description
BATS Voltage Sense High Condition Bit -- This status bit indicates that a high voltage at VSUP, depending on selection, is present.
0 Vmeasured VHBI_A (rising edge) or Vmeasured VHBI_D (falling edge) 1 Vmeasured VHBI_A (rising edge) or Vmeasured VHBI_D (falling edge) BATS Voltage Sense Low Condition Bit -- This status bit indicates that a low voltage at VSUP, depending on selection, is present.
0 Vmeasured  VLBI_A (falling edge) or Vmeasured VLBI_D (rising edge) 1 Vmeasured VLBI_A (falling edge) or Vmeasured VLBI_D (rising edge)

V VVHHBBII__AD

Figure 10-5. BATS Voltage Sensing

VLBI_D VLBI_A
t

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10.3.2.3 BATS Interrupt Enable Register (BATIE)

Module Base + 0x0002

7

R

0

W

Reset

0

1. Read: Anytime Write: Anytime

6

5

4

3

2

0

0

0

0

0

0

0

0

0

0

= Unimplemented

Figure 10-6. BATS Interrupt Enable Register (BATIE)

Field 1
BVHIE
0 BVLIE

Table 10-4. BATIE Register Field Descriptions
Description BATS Interrupt Enable High -- Enables High Voltage Interrupt .
0 No interrupt will be requested whenever BVHIF flag is set . 1 Interrupt will be requested whenever BVHIF flag is set BATS Interrupt Enable Low -- Enables Low Voltage Interrupt .
0 No interrupt will be requested whenever BVLIF flag is set . 1 Interrupt will be requested whenever BVLIF flag is set .

10.3.2.4 BATS Interrupt Flag Register (BATIF)

Module Base + 0x0003

7

6

5

4

3

2

R

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

= Unimplemented

Figure 10-7. BATS Interrupt Flag Register (BATIF)
1. Read: Anytime Write: Anytime, write 1 to clear

Access: User read/write(1)

1

0

BVHIE

BVLIE

0

0

Access: User read/write(1)

1

0

BVHIF

BVLIF

0

0

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BVHIF
0 BVLIF

Chapter 10 Supply Voltage Sensor - (BATSV3)
Table 10-5. BATIF Register Field Descriptions
Description BATS Interrupt Flag High Detect -- The flag is set to 1 when BVHC status bit changes.
0 No change of the BVHC status bit since the last clearing of the flag. 1 BVHC status bit has changed since the last clearing of the flag. BATS Interrupt Flag Low Detect -- The flag is set to 1 when BVLC status bit changes.
0 No change of the BVLC status bit since the last clearing of the flag. 1 BVLC status bit has changed since the last clearing of the flag.

10.3.2.5 Reserved Register

Module Base + 0x0006 Module Base + 0x0007

R W Reset

7
Reserved x

6
Reserved x

1. Read: Anytime Write: Only in special mode

5
Reserved

4
Reserved

3
Reserved

2
Reserved

x

x

x

x

Figure 10-8. Reserved Register

Access: User read/write(1)

1
Reserved

0
Reserved

x

x

NOTE
These reserved registers are designed for factory test purposes only and are not intended for general user access. Writing to these registers when in special mode can alter the module's functionality.

10.4 Functional Description

10.4.1 General
The BATS module allows measuring the voltage on the VSUP pin. The voltage at the VSUP pin can be routed via an internal voltage divider to an internal Analog to Digital Converter Channel. Also the BATS module can be configured to generate a low and high voltage interrupt based on VSUP. The trigger level of the high and low interrupt are selectable.
10.4.2 Interrupts
This section describes the interrupt generated by the BATS module. The interrupt is only available in CPU run mode. Entering and exiting CPU stop mode has no effect on the interrupt flags.
To make sure the interrupt generation works properly the bus clock frequency must be higher than the Voltage Warning Low Pass Filter frequency (fVWLP_filter).

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The comparator outputs BVLC and BVHC are forced to zero if the comparator is disabled (configuration bit BSUSE is cleared). If the software disables the comparator during a high or low Voltage condition (BVHC or BVLC active), then an additional interrupt is generated. To avoid this behavior the software must disable the interrupt generation before disabling the comparator.
The BATS interrupt vector is named in Table 10-6. Vector addresses and interrupt priorities are defined at MCU level.
The module internal interrupt sources are combined into one module interrupt signal.

Module Interrupt Source BATS Interrupt (BATI)

Table 10-6. BATS Interrupt Sources
Module Internal Interrupt Source BATS Voltage Low Condition Interrupt (BVLI) BATS Voltage High Condition Interrupt (BVHI)

Local Enable BVLIE = 1 BVHIE = 1

10.4.2.1 BATS Voltage Low Condition Interrupt (BVLI)
To use the Voltage Low Interrupt the Level Sensing must be enabled (BSUSE =1).
If measured when a) VLBI1 selected with BVLS[1:0] = 0x0 Vmeasure VLBI1_A (falling edge) or Vmeasure VLBI1_D (rising edge)
or when b) VLBI2 selected with BVLS[1:0] = 0x1 at pin VSUP Vmeasure VLBI2_A (falling edge) or Vmeasure VLBI2_D (rising edge)
or when c) VLBI3 selected with BVLS[1:0] = 0x2 Vmeasure VLBI3_A (falling edge) or Vmeasure VLBI3_D (rising edge)
or when d) VLBI4 selected with BVLS[1:0] = 0x3 Vmeasure VLBI4_A (falling edge) or Vmeasure VLBI4_D (rising edge)

then BVLC is set. BVLC status bit indicates that a low voltage at pin VSUP is present. The Low Voltage Interrupt flag (BVLIF) is set to 1 when the Voltage Low Condition (BVLC) changes state . The Interrupt flag BVLIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVLIE the module requests an interrupt to MCU (BATI).
10.4.2.2 BATS Voltage High Condition Interrupt (BVHI)
To use the Voltage High Interrupt the Level Sensing must be enabled (BSUSE=1).

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If measured when a) VHBI1 selected with BVHS = 0 Vmeasure VHBI1_A (rising edge) or Vmeasure VHBI1_D (falling edge)
or when a) VHBI2 selected with BVHS = 1 Vmeasure VHBI2_A (rising edge) or Vmeasure VHBI2_D (falling edge)
then BVHC is set. BVHC status bit indicates that a high voltage at pin VSUP is present. The High Voltage Interrupt flag (BVHIF) is set to 1 when a Voltage High Condition (BVHC) changes state. The Interrupt flag BVHIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVHIE the module requests an interrupt to MCU (BATI).

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Chapter 11 Timer Module (TIM16B4CV3) Block Description

Table 11-1. Revision History

V03.03

Jan,14,2013

-single source generate different channel guide

11.1 Introduction
The basic scalable timer consists of a 16-bit, software-programmable counter driven by a flexible programmable prescaler.
This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform.
This timer could contain up to 4 input capture/output compare channels . The input capture function is used to detect a selected transition edge and record the time. The output compare function is used for generating output signals or for timer software delays.
A full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word.

11.1.1 Features
The TIM16B4CV3 includes these distinctive features: · Up to 4 channels available. (refer to device specification for exact number) · All channels have same input capture/output compare functionality. · Clock prescaling. · 16-bit counter.

11.1.2
Stop: Freeze: Wait: Normal:

Modes of Operation
Timer is off because clocks are stopped. Timer counter keeps on running, unless TSFRZ in TSCR1 is set to 1. Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Timer counter keep on running, unless TEN in TSCR1 is cleared to 0.

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11.1.3 Block Diagrams

Bus clock
Timer overflow interrupt
Timer channel 0 interrupt
Timer channel 1 interrupt
Timer channel 2 interrupt
Timer channel 3 interrupt

Prescaler 16-bit Counter Registers

Channel 0 Input capture Output compare
Channel 1 Input capture Output compare
Channel 2 Input capture Output compare
Channel 3 Input capture Output compare

IOC0 IOC1 IOC2 IOC3

Figure 11-1. TIM16B4CV3 Block Diagram

IOCn

Edge detector

16-bit Main Timer TCn Input Capture Reg.

Figure 11-2. Interrupt Flag Setting

Set CnF Interrupt

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Chapter 11 Timer Module (TIM16B4CV3) Block Description
11.2 External Signal Description
The TIM16B4CV3 module has a selected number of external pins. Refer to device specification for exact number.

11.2.1 IOC3 - IOC0 -- Input Capture and Output Compare Channel 3-0
Those pins serve as input capture or output compare for TIM16B4CV3 channel . NOTE
For the description of interrupts see Section 11.6, "Interrupts".
11.3 Memory Map and Register Definition
This section provides a detailed description of all memory and registers.

11.3.1 Module Memory Map
The memory map for the TIM16B4CV3 module is given below in Figure 11-3. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the TIM16B4CV3 module and the address offset for each register.

11.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.

Only bits related to implemented channels are valid.

Register Name
0x0000 TIOS
0x0001 CFORC
0x0004 TCNTH
0x0005 TCNTL
0x0006 TSCR1
0x0007 TTOV
0x0008 TCTL1

Bit 7

6

5

4

3

2

1

Bit 0

R RESERV W ED

R

0

W RESERV ED

R W

TCNT15

R W

TCNT7

R W

TEN

R RESERV W ED

R RESERV W ED

RESERV ED 0
RESERV ED
TCNT14
TCNT6
TSWAI
RESERV ED
RESERV ED

RESERV ED 0
RESERV ED
TCNT13
TCNT5
TSFRZ
RESERV ED
RESERV ED

RESERV ED 0
RESERV ED
TCNT12
TCNT4
TFFCA
RESERV ED
RESERV ED

IOS3 0
FOC3
TCNT11
TCNT3
PRNT
TOV3 RESERV
ED

IOS2 0
FOC2
TCNT10
TCNT2 0
TOV2 RESERV
ED

Figure 11-3. TIM16B4CV3 Register Summary (Sheet 1 of 2)

IOS1 0
FOC1
TCNT9
TCNT1 0
TOV1 RESERV
ED

IOS0 0
FOC0
TCNT8
TCNT0 0
TOV0 RESERV
ED

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Chapter 11 Timer Module (TIM16B4CV3) Block Description

Register Name 0x0009 TCTL2 0x000A TCTL3 0x000B TCTL4 0x000C TIE 0x000D TSCR2 0x000E TFLG1 0x000F TFLG2
0x0010­0x001F TCxH­TCxL(1)
0x0024­0x002B Reserved 0x002C OCPD 0x002D Reserved

Bit 7

6

5

4

3

2

1

Bit 0

R W

OM3

R RESERV W ED

R W

EDG3B

R RESERV W ED

R W

TOI

R RESERV W ED

R W

TOF

R W

Bit 15

OL3
RESERV ED
EDG3A
RESERV ED 0
RESERV ED 0
Bit 14

OM2
RESERV ED
EDG2B
RESERV ED 0
RESERV ED 0
Bit 13

OL2
RESERV ED
EDG2A
RESERV ED 0
RESERV ED 0
Bit 12

OM1 RESERV
ED EDG1B
C3I RESERV
ED C3F
0
Bit 11

OL1 RESERV
ED EDG1A
C2I
PR2
C2F 0
Bit 10

OM0 RESERV
ED EDG0B
C1I
PR1
C1F 0
Bit 9

OL0 RESERV
ED EDG0A
C0I
PR0
C0F 0
Bit 8

R W

Bit 7

R

W

R RESERV W ED

R

Bit 6
RESERV ED

Bit 5
RESERV ED

Bit 4
RESERV ED

Bit 3 OCPD3

Bit 2 OCPD2

Bit 1 OCPD1

Bit 0 OCPD0

0x002E PTPSR
0x002F Reserved

R W

PTPS7

R

W

PTPS6

PTPS5

PTPS4

PTPS3

PTPS2

Figure 11-3. TIM16B4CV3 Register Summary (Sheet 2 of 2) 1. The register is available only if corresponding channel exists.

PTPS1

PTPS0

11.3.2.1 Timer Input Capture/Output Compare Select (TIOS)

Module Base + 0x0000

7

6

5

4

R RESERVED RESERVED RESERVED RESERVED
W

3
IOS3

2
IOS2

1
IOS1

Reset

0

0

0

0

0

0

0

Figure 11-4. Timer Input Capture/Output Compare Select (TIOS)

0
IOS0 0

Read: Anytime Write: Anytime

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Table 11-2. TIOS Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.

Field
3:0 IOS[3:0]

Description
Input Capture or Output Compare Channel Configuration 0 The corresponding implemented channel acts as an input capture. 1 The corresponding implemented channel acts as an output compare.

11.3.2.2 Timer Compare Force Register (CFORC)

Module Base + 0x0001

7

6

5

4

3

2

R

0

0

0

0

0

0

W RESERVED RESERVED RESERVED RESERVED FOC3

FOC2

Reset

0

0

0

0

0

0

Figure 11-5. Timer Compare Force Register (CFORC)

Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime

1
0 FOC1
0

0
0 FOC0
0

Table 11-3. CFORC Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.

Field

Description

3:0 FOC[3:0]

Note: Force Output Compare Action for Channel 3:0 -- A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare "x" to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not get set. If forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt flag won't get set.

11.3.2.3 Timer Count Register (TCNT)

Module Base + 0x0004

R W Reset

15
TCNT15 0

14
TCNT14

13
TCNT13

12
TCNT12

11
TCNT11

10
TCNT10

0

0

0

0

0

Figure 11-6. Timer Count Register High (TCNTH)

9
TCNT9 0

9
TCNT8 0

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Module Base + 0x0005

7
R TCNT7
W

6
TCNT6

5
TCNT5

4
TCNT4

3
TCNT3

2
TCNT2

1
TCNT1

0
TCNT0

Reset

0

0

0

0

0

0

0

0

Figure 11-7. Timer Count Register Low (TCNTL)

The 16-bit main timer is an up counter.

A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word.

Read: Anytime

Write: Has no meaning or effect in the normal mode; only writable in special mode.

The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock.

11.3.2.4 Timer System Control Register 1 (TSCR1)

Module Base + 0x0006

7

6

5

4

3

2

1

0

R

0

0

0

TEN

TSWAI

TSFRZ

TFFCA

PRNT

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 11-8. Timer System Control Register 1 (TSCR1)

Read: Anytime

Write: Anytime

Table 11-4. TSCR1 Field Descriptions

Field
7 TEN
6 TSWAI

Description
Timer Enable 0 Disables the main timer, including the counter. Can be used for reducing power consumption. 1 Allows the timer to function normally.
Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait.

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Table 11-4. TSCR1 Field Descriptions (continued)

Field 5
TSFRZ
4 TFFCA
3 PRNT

Description
Timer Stops While in Freeze Mode 0 Allows the timer counter to continue running while in freeze mode. 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation.
Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally. 1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010­0x001F)
causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT register (0x0004, 0x0005) clears the TOF flag. This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses.
Precision Timer 0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler
selection. 1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and
all bits. This bit is writable only once out of reset.

11.3.2.5 Timer Toggle On Overflow Register 1 (TTOV)

Module Base + 0x0007

7

6

5

4

R RESERVED RESERVED RESERVED RESERVED
W

3
TOV3

2
TOV2

Reset

0

0

0

0

0

0

Figure 11-9. Timer Toggle On Overflow Register 1 (TTOV)

Read: Anytime

Write: Anytime

1
TOV1 0

0
TOV0 0

Table 11-5. TTOV Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.

Field
3:0 TOV[3:0]

Description
Toggle On Overflow Bits -- TOVx toggles output compare pin on overflow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled.

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11.3.2.6 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)

Module Base + 0x0008

7

6

5

4

3

2

1

0

R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
W

Reset

0

0

0

0

0

0

0

0

Figure 11-10. Timer Control Register 1 (TCTL1)

Module Base + 0x0009

7

6

5

4

3

2

1

0

R

OM3

OL3

OM2

OL2

OM1

OL1

OM0

OL0

W

Reset

0

0

0

0

0

0

0

0

Figure 11-11. Timer Control Register 2 (TCTL2)

Read: Anytime

Write: Anytime

Table 11-6. TCTL1/TCTL2 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero

Field 3:0 OMx
3:0 OLx

Description
Output Mode -- These four pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: For an output line to be driven by an OCx the OCPDx must be cleared.
Output Level -- These fourpairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: For an output line to be driven by an OCx the OCPDx must be cleared.

OMx 0
0 1 1

Table 11-7. Compare Result Output Action

OLx

Action

0

No output compare

action on the timer output signal

1

Toggle OCx output line

0

Clear OCx output line to zero

1

Set OCx output line to one

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11.3.2.7 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)

Module Base + 0x000A

7

6

5

4

3

2

1

0

R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
W

Reset

0

0

0

0

0

0

0

0

Figure 11-12. Timer Control Register 3 (TCTL3)

Module Base + 0x000B

R W Reset

7
EDG3B 0

Read: Anytime Write: Anytime.

6
EDG3A

5
EDG2B

4
EDG2A

3
EDG1B

2
EDG1A

0

0

0

0

0

Figure 11-13. Timer Control Register 4 (TCTL4)

1
EDG0B 0

0
EDG0A 0

Table 11-8. TCTL3/TCTL4 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.

Field
3:0 EDGnB EDGnA

Description
Input Capture Edge Control -- These four pairs of control bits configure the input capture edge detector circuits.

Table 11-9. Edge Detector Circuit Configuration

EDGnB
0 0 1 1

EDGnA
0 1 0 1

Configuration
Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling)

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11.3.2.8 Timer Interrupt Enable Register (TIE)

Module Base + 0x000C

7

6

5

4

3

2

1

0

R

RESERVED RESERVED RESERVED RESERVED

C3I

C2I

C1I

C0I

W

Reset

0

0

0

0

0

0

0

0

Figure 11-14. Timer Interrupt Enable Register (TIE)

Read: Anytime

Write: Anytime.

Table 11-10. TIE Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero

Field
3:0 C3I:C0I

Description
Input Capture/Output Compare "x" Interrupt Enable -- The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a interrupt.

11.3.2.9 Timer System Control Register 2 (TSCR2)

Module Base + 0x000D

7

6

5

4

3

2

1

0

R

0

0

0

TOI

RESERVED

PR2

PR1

PR0

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 11-15. Timer System Control Register 2 (TSCR2)

Read: Anytime

Write: Anytime.

Table 11-11. TSCR2 Field Descriptions

Field
7 TOI
2:0 PR[2:0]

Description
Timer Overflow Interrupt Enable 0 Interrupt inhibited. 1 Hardware interrupt requested when TOF flag set.
Timer Prescaler Select -- These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in Table 11-12.

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Table 11-12. Timer Clock Selection

PR2

PR1

PR0

Timer Clock

0

0

0

Bus Clock / 1

0

0

1

Bus Clock / 2

0

1

0

Bus Clock / 4

0

1

1

Bus Clock / 8

1

0

0

Bus Clock / 16

1

0

1

Bus Clock / 32

1

1

0

Bus Clock / 64

1

1

1

Bus Clock / 128

NOTE
The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero.

11.3.2.10 Main Timer Interrupt Flag 1 (TFLG1)

Module Base + 0x000E

7

6

5

4

3

2

1

0

R

RESERVED RESERVED RESERVED RESERVED

C3F

C2F

C1F

C0F

W

Reset

0

0

0

0

0

0

0

0

Figure 11-16. Main Timer Interrupt Flag 1 (TFLG1)

Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit.

Table 11-13. TRLG1 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.

Field
3:0 C[3:0]F

Description
Input Capture/Output Compare Channel "x" Flag -- These flags are set when an input capture or output compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN is set to one.

Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel (0x0010­0x001F) will cause the corresponding channel flag CxF to be cleared.

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11.3.2.11 Main Timer Interrupt Flag 2 (TFLG2)

Module Base + 0x000F

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

TOF

W

Reset

0

0

0

0

0

0

0

0

Unimplemented or Reserved

Figure 11-17. Main Timer Interrupt Flag 2 (TFLG2)

TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one while TEN bit of TSCR1 .

Read: Anytime

Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).

Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.

Table 11-14. TRLG2 Field Descriptions

Field
7 TOF

Description
Timer Overflow Flag -- Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 is set to one .

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Chapter 11 Timer Module (TIM16B4CV3) Block Description

11.3.2.12 Timer Input Capture/Output Compare Registers High and Low 0­ 3(TCxH and TCxL)

Module Base + 0x0010 = TC0H 0x0012 = TC1H 0x0014=TC2H 0x0016=TC3H

0x0018=RESERVD 0x001A=RESERVD 0x001C=RESERVD 0x001E=RESERVD

15
R Bit 15
W

14
Bit 14

13
Bit 13

12
Bit 12

11
Bit 11

10
Bit 10

9
Bit 9

0
Bit 8

Reset

0

0

0

0

0

0

0

0

Figure 11-18. Timer Input Capture/Output Compare Register x High (TCxH)

Module Base + 0x0011 = TC0L 0x0013 = TC1L 0x0015 =TC2L 0x0017=TC3L

0x0019 =RESERVD 0x001B=RESERVD 0x001D=RESERVD 0x001F=RESERVD

7
R Bit 7
W

6
Bit 6

5
Bit 5

4
Bit 4

3
Bit 3

2
Bit 2

1
Bit 1

0
Bit 0

Reset

0

0

0

0

0

0

0

0

Figure 11-19. Timer Input Capture/Output Compare Register x Low (TCxL)

1 This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes.

Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare.

Read: Anytime

Write: Anytime for output compare function.Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to 0x0000.

NOTE
Read/Write access in byte mode for high byte should take place before low byte otherwise it will give a different result.

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11.3.2.13 Output Compare Pin Disconnect Register(OCPD)

Module Base + 0x002C

7

6

5

4

R RESERVED RESERVED RESERVED RESERVED
W

3
OCPD3

2
OCPD2

1
OCPD1

Reset

0

0

0

0

0

0

0

Figure 11-20. Output Compare Pin Disconnect Register (OCPD)

Read: Anytime

Write: Anytime

All bits reset to zero.

0
OCPD0 0

Table 11-15. OCPD Field Description Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.

Field

Description

3:0 OCPD[3:0]

Output Compare Pin Disconnect Bits 0 Enables the timer channel port. Output Compare action will occur on the channel pin. These bits do not affect
the input capture . 1 Disables the timer channel port. Output Compare action will not occur on the channel pin, but the output
compare flag still become set.

11.3.2.14 Precision Timer Prescaler Select Register (PTPSR)

Module Base + 0x002E

7
R PTPS7
W

6
PTPS6

5
PTPS5

4
PTPS4

3
PTPS3

2
PTPS2

1
PTPS1

Reset

0

0

0

0

0

0

0

Figure 11-21. Precision Timer Prescaler Select Register (PTPSR)

Read: Anytime

Write: Anytime

All bits reset to zero.

0
PTPS0 0

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...
Table 11-16. PTPSR Field Descriptions

Field

Description

7:0 PTPS[7:0]

Precision Timer Prescaler Select Bits -- These eight bits specify the division rate of the main Timer prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 11-17 shows some selection examples in this case. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero.

The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit: PRNT = 1 : Prescaler = PTPS[7:0] + 1

PTPS7
0 0 0 0 0 0 0 1 1 1 1

Table 11-17. Precision Timer Prescaler Selection Examples when PRNT = 1

PTPS6
0 0 0 0 0 0 0 1 1 1 1

PTPS5
0 0 0 0 0 0 0 1 1 1 1

PTPS4
0 0 0 0 1 1 1 1 1 1 1

PTPS3
0 0 0 0 0 0 0 1 1 1 1

PTPS2
0 0 0 0 0 1 1 1 1 1 1

PTPS1
0 0 1 1 1 0 0 0 0 1 1

PTPS0
0 1 0 1 1 0 1 0 1 0 1

Prescale Factor
1 2 3 4 20 21 22 253 254 255 256

11.4 Functional Description
This section provides a complete functional description of the timer TIM16B4CV3 block. Please refer to the detailed timer block diagram in Figure 11-22 as necessary.

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tim source Clock PRNT

PTPSR[7:0] PRE-PRESCALER

PR[2:1:0] PRESCALER

1 MUX 0

TCNT(hi):TCNT(lo)

16-BIT COUNTER

CHANNEL 0 16-BIT COMPARATOR
TC0
EDG0A EDG0B CHANNEL 1
16-BIT COMPARATOR TC1
EDG1A EDG1B CHANNEL2

CxI CxF

TOF

INTERRUPT

TE

TOI

LOGIC

TOF

C0F EDGE DETECT

OM:OL0 TOV0

C0F IOC0

CH. 0 CAPTURE
IOC0 PIN LOGIC CH. 0COMPARE

IOC0 PIN

C1F EDGE DETECT

OM:OL1 TOV1

C1F IOC1

CH. 1 CAPTURE
IOC1 PIN LOGIC CH. 1 COMPARE

IOC1 PIN

CHANNELn-1 16-BIT COMPARATOR
TCn-1
EDG(n-1)A EDG(n-1)B

Cn-1F OM:OLn-1
EDGE TOVn-1 DETECT

Cn-1F IOCn-1

CH.n-1 CAPTURE

IOCn-1 PIN LOGIC CH.

IOCn-1 n-1COMPARE

PIN

n is channels number.

Figure 11-22. Detailed Timer Block Diagram
11.4.1 Prescaler
The prescaler divides the Bus clock by 1, 2, 4, 8, 16, 32, 64 or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
The prescaler divides the Bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled.

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By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this case, it is possible to set additional prescaler settings for the main timer counter in the present timer by using PTPSR[7:0] bits of PTPSR register generating divide by 1, 2, 3, 4,....20, 21, 22, 23,......255, or 256.
11.4.2 Input Capture
Clearing the I/O (input/output) select bit, IOSx, configures channel x as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, TCx.
The minimum pulse width for the input capture input is greater than two Bus clocks.
An input capture on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. Timer module must stay enabled (TEN bit of TSCR1 register must be set to one) while clearing CxF (writing one to CxF).
11.4.3 Output Compare
Setting the I/O select bit, IOSx, configures channel x when available as an output compare channel. The output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin if the corresponding OCPDx bit is set to zero. An output compare on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. Timer module must stay enabled (TEN bit of TSCR1 register must be set to one) while clearing CxF (writing one to CxF).
The output mode and level bits, OMx and OLx, select set, clear, toggle on output compare. Clearing both OMx and OLx results in no output compare action on the output compare channel pin.
Setting a force output compare bit, FOCx, causes an output compare on channel x. A forced output compare does not set the channel flag.
Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin.
11.4.3.1 OC Channel Initialization
The internal register whose output drives OCx can be programmed before the timer drives OCx. The desired state can be programmed to this internal register by writing a one to CFORCx bit with TIOSx, OCPDx and TEN bits set to one.
Set OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=1 and OCPDx=1 Clear OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=0 and OCPDx=1

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Setting OCPDx to zero allows the internal register to drive the programmed state to OCx. This allows a glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set to zero.

11.5 Resets
The reset state of each individual bit is listed within Section 11.3, "Memory Map and Register Definition" which details the registers and their bit fields

11.6 Interrupts

This section describes interrupts originated by the TIM16B4CV3 block. Table 11-18 lists the interrupts generated by the TIM16B4CV3 to communicate with the MCU.
Table 11-18. TIM16B4CV3 Interrupts

Interrupt

Offset Vector Priority

Source

Description

C[3:0]F

--

--

--

Timer Channel 3­0

Active high timer channel interrupts 3­0

TOF

--

--

--

Timer Overflow

Timer Overflow interrupt

The TIM16B4CV3 could use up to 5 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent.

11.6.1 Channel [3:0] Interrupt (C[3:0]F)
This active high outputs will be asserted by the module to request a timer channel 7 ­ 0 interrupt. The TIM block only generates the interrupt and does not service it. Only bits related to implemented channels are valid.

11.6.2 Timer Overflow Interrupt (TOF)
This active high output will be asserted by the module to request a timer overflow interrupt. The TIM block only generates the interrupt and does not service it.

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Table 12-1. Revision History

V03.03

Jan,14,2013

-single source generate different channel guide

12.1 Introduction
The basic scalable timer consists of a 16-bit, software-programmable counter driven by a flexible programmable prescaler.
This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform.
This timer could contain up to 2 input capture/output compare channels . The input capture function is used to detect a selected transition edge and record the time. The output compare function is used for generating output signals or for timer software delays.
A full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word.

12.1.1 Features
The TIM16B2CV3 includes these distinctive features: · Up to 2 channels available. (refer to device specification for exact number) · All channels have same input capture/output compare functionality. · Clock prescaling. · 16-bit counter.

12.1.2
Stop: Freeze: Wait: Normal:

Modes of Operation
Timer is off because clocks are stopped. Timer counter keeps on running, unless TSFRZ in TSCR1 is set to 1. Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Timer counter keep on running, unless TEN in TSCR1 is cleared to 0.

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12.1.3 Block Diagrams

Bus clock
Timer overflow interrupt
Timer channel 0 interrupt
Timer channel 1 interrupt

Prescaler 16-bit Counter Registers

Channel 0 Input capture Output compare
Channel 1 Input capture Output compare

IOC0 IOC1

Figure 12-1. TIM16B2CV3 Block Diagram

IOCn

Edge detector

16-bit Main Timer TCn Input Capture Reg.

Set CnF Interrupt

Figure 12-2. Interrupt Flag Setting
12.2 External Signal Description
The TIM16B2CV3 module has a selected number of external pins. Refer to device specification for exact number.

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12.2.1 IOC1 - IOC0 -- Input Capture and Output Compare Channel 1-0
Those pins serve as input capture or output compare for TIM16B2CV3 channel . NOTE
For the description of interrupts see Section 12.6, "Interrupts".
12.3 Memory Map and Register Definition
This section provides a detailed description of all memory and registers.

12.3.1 Module Memory Map
The memory map for the TIM16B2CV3 module is given below in Figure 12-3. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the TIM16B2CV3 module and the address offset for each register.

12.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.

Only bits related to implemented channels are valid.

Register Name
0x0000 TIOS
0x0001 CFORC
0x0004 TCNTH
0x0005 TCNTL
0x0006 TSCR1
0x0007 TTOV
0x0008 TCTL1
0x0009 TCTL2
0x000A TCTL3
0x000B TCTL4

Bit 7

6

5

4

3

2

1

Bit 0

R RESERV W ED

R

0

W RESERV ED

R W

TCNT15

R W

TCNT7

R W

TEN

R RESERV W ED

R RESERV W ED

R RESERV W ED

R RESERV W ED

R RESERV W ED

RESERV ED 0
RESERV ED
TCNT14
TCNT6
TSWAI
RESERV ED
RESERV ED
RESERV ED
RESERV ED
RESERV ED

RESERV ED 0
RESERV ED
TCNT13
TCNT5
TSFRZ
RESERV ED
RESERV ED
RESERV ED
RESERV ED
RESERV ED

RESERV ED 0
RESERV ED
TCNT12
TCNT4
TFFCA
RESERV ED
RESERV ED
RESERV ED
RESERV ED
RESERV ED

RESERV ED 0
RESERV ED
TCNT11
TCNT3
PRNT
RESERV ED
RESERV ED
OM1
RESERV ED
EDG1B

RESERV ED 0
RESERV ED
TCNT10
TCNT2
0
RESERV ED
RESERV ED
OL1
RESERV ED
EDG1A

Figure 12-3. TIM16B2CV3 Register Summary (Sheet 1 of 2)

IOS1 0
FOC1
TCNT9
TCNT1 0
TOV1 RESERV
ED OM0 RESERV ED EDG0B

IOS0 0
FOC0
TCNT8
TCNT0 0
TOV0 RESERV
ED OL0 RESERV ED EDG0A

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Register Name 0x000C TIE 0x000D TSCR2 0x000E TFLG1 0x000F TFLG2
0x0010­0x001F TCxH­TCxL(1)
0x0024­0x002B Reserved 0x002C OCPD 0x002D Reserved

Bit 7

6

5

4

3

2

R RESERV W ED

R W

TOI

R RESERV W ED

R W

TOF

R W

Bit 15

RESERV ED 0
RESERV ED 0
Bit 14

RESERV ED 0
RESERV ED 0
Bit 13

RESERV ED 0
RESERV ED 0
Bit 12

RESERV ED
RESERV ED
RESERV ED 0
Bit 11

RESERV ED
PR2
RESERV ED 0
Bit 10

R W

Bit 7

R

W

R RESERV W ED

R

Bit 6
RESERV ED

Bit 5
RESERV ED

Bit 4
RESERV ED

Bit 3
RESERV ED

Bit 2
RESERV ED

1 C1I PR1 C1F 0 Bit 9 Bit 1
OCPD1

Bit 0 C0I PR0 C0F 0 Bit 8 Bit 0
OCPD0

0x002E PTPSR
0x002F Reserved

R W

PTPS7

R

W

PTPS6

PTPS5

PTPS4

PTPS3

PTPS2

Figure 12-3. TIM16B2CV3 Register Summary (Sheet 2 of 2)

1. The register is available only if corresponding channel exists.

PTPS1

PTPS0

12.3.2.1 Timer Input Capture/Output Compare Select (TIOS)

Module Base + 0x0000

7

6

5

4

3

2

R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
W

1
IOS1

Reset

0

0

0

0

0

0

0

Figure 12-4. Timer Input Capture/Output Compare Select (TIOS)

Read: Anytime

Write: Anytime

0
IOS0 0

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Table 12-2. TIOS Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.

Field
1:0 IOS[1:0]

Description
Input Capture or Output Compare Channel Configuration 0 The corresponding implemented channel acts as an input capture. 1 The corresponding implemented channel acts as an output compare.

12.3.2.2 Timer Compare Force Register (CFORC)

Module Base + 0x0001

7

6

5

4

3

2

R

0

0

0

0

0

0

W RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

Reset

0

0

0

0

0

0

Figure 12-5. Timer Compare Force Register (CFORC)

Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime

1
0 FOC1
0

0
0 FOC0
0

Table 12-3. CFORC Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.

Field

Description

1:0 FOC[1:0]

Note: Force Output Compare Action for Channel 1:0 -- A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare "x" to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not get set. If forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt flag won't get set.

12.3.2.3 Timer Count Register (TCNT)

Module Base + 0x0004

R W Reset

15
TCNT15 0

14
TCNT14

13
TCNT13

12
TCNT12

11
TCNT11

10
TCNT10

0

0

0

0

0

Figure 12-6. Timer Count Register High (TCNTH)

9
TCNT9 0

9
TCNT8 0

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Module Base + 0x0005

7
R TCNT7
W

6
TCNT6

5
TCNT5

4
TCNT4

3
TCNT3

2
TCNT2

1
TCNT1

0
TCNT0

Reset

0

0

0

0

0

0

0

0

Figure 12-7. Timer Count Register Low (TCNTL)

The 16-bit main timer is an up counter.

A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word.

Read: Anytime

Write: Has no meaning or effect in the normal mode; only writable in special mode.

The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock.

12.3.2.4 Timer System Control Register 1 (TSCR1)

Module Base + 0x0006

7

6

5

4

3

2

1

0

R

0

0

0

TEN

TSWAI

TSFRZ

TFFCA

PRNT

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 12-8. Timer System Control Register 1 (TSCR1)

Read: Anytime

Write: Anytime

Table 12-4. TSCR1 Field Descriptions

Field
7 TEN
6 TSWAI

Description
Timer Enable 0 Disables the main timer, including the counter. Can be used for reducing power consumption. 1 Allows the timer to function normally.
Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait.

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Table 12-4. TSCR1 Field Descriptions (continued)

Field 5
TSFRZ
4 TFFCA
3 PRNT

Description
Timer Stops While in Freeze Mode 0 Allows the timer counter to continue running while in freeze mode. 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation.
Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally. 1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010­0x001F)
causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT register (0x0004, 0x0005) clears the TOF flag. This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses.
Precision Timer 0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler
selection. 1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and
all bits. This bit is writable only once out of reset.

12.3.2.5 Timer Toggle On Overflow Register 1 (TTOV)

Module Base + 0x0007

7

6

5

4

3

2

R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
W

Reset

0

0

0

0

0

0

Figure 12-9. Timer Toggle On Overflow Register 1 (TTOV)

Read: Anytime

Write: Anytime

1
TOV1 0

0
TOV0 0

Table 12-5. TTOV Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.

Field
1:0 TOV[1:0]

Description
Toggle On Overflow Bits -- TOVx toggles output compare pin on overflow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled.

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12.3.2.6 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)

Module Base + 0x0008

7

6

5

4

3

2

1

0

R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
W

Reset

0

0

0

0

0

0

0

0

Figure 12-10. Timer Control Register 1 (TCTL1)

Module Base + 0x0009

7

6

5

4

3

2

1

0

R

RESERVED RESERVED RESERVED RESERVED

OM1

OL1

OM0

OL0

W

Reset

0

0

0

0

0

0

0

0

Figure 12-11. Timer Control Register 2 (TCTL2)

Read: Anytime

Write: Anytime

Table 12-6. TCTL1/TCTL2 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero

Field 1:0 OMx
1:0 OLx

Description
Output Mode -- These two pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: For an output line to be driven by an OCx the OCPDx must be cleared.
Output Level -- These two pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: For an output line to be driven by an OCx the OCPDx must be cleared.

Table 12-7. Compare Result Output Action

OMx

OLx

0

0

0

1

1

0

1

1

Action
No output compare action on the timer output signal
Toggle OCx output line Clear OCx output line to zero
Set OCx output line to one

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12.3.2.7 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)

Module Base + 0x000A

7

6

5

4

3

2

1

0

R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
W

Reset

0

0

0

0

0

0

0

0

Figure 12-12. Timer Control Register 3 (TCTL3)

Module Base + 0x000B

7

6

5

4

R RESERVED RESERVED RESERVED RESERVED
W

3
EDG1B

2
EDG1A

Reset

0

0

0

0

0

0

Figure 12-13. Timer Control Register 4 (TCTL4)

Read: Anytime

Write: Anytime.

1
EDG0B 0

0
EDG0A 0

Table 12-8. TCTL3/TCTL4 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.

Field
1:0 EDGnB EDGnA

Description
Input Capture Edge Control -- These two pairs of control bits configure the input capture edge detector circuits.

Table 12-9. Edge Detector Circuit Configuration

EDGnB
0 0 1 1

EDGnA
0 1 0 1

Configuration
Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling)

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12.3.2.8 Timer Interrupt Enable Register (TIE)

Module Base + 0x000C

7

6

5

4

3

2

1

0

R

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

C1I

C0I

W

Reset

0

0

0

0

0

0

0

0

Figure 12-14. Timer Interrupt Enable Register (TIE)

Read: Anytime

Write: Anytime.

Table 12-10. TIE Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero

Field
1:0 C1I:C0I

Description
Input Capture/Output Compare "x" Interrupt Enable -- The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a interrupt.

12.3.2.9 Timer System Control Register 2 (TSCR2)

Module Base + 0x000D

7

6

5

4

3

2

1

0

R

0

0

0

TOI

RESERVED

PR2

PR1

PR0

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Figure 12-15. Timer System Control Register 2 (TSCR2)

Read: Anytime

Write: Anytime.

Table 12-11. TSCR2 Field Descriptions

Field
7 TOI
2:0 PR[2:0]

Description
Timer Overflow Interrupt Enable 0 Interrupt inhibited. 1 Hardware interrupt requested when TOF flag set.
Timer Prescaler Select -- These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in Table 12-12.

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Table 12-12. Timer Clock Selection

PR2

PR1

PR0

Timer Clock

0

0

0

Bus Clock / 1

0

0

1

Bus Clock / 2

0

1

0

Bus Clock / 4

0

1

1

Bus Clock / 8

1

0

0

Bus Clock / 16

1

0

1

Bus Clock / 32

1

1

0

Bus Clock / 64

1

1

1

Bus Clock / 128

NOTE
The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero.

12.3.2.10 Main Timer Interrupt Flag 1 (TFLG1)

Module Base + 0x000E

7

6

5

4

3

2

1

0

R

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

C1F

C0F

W

Reset

0

0

0

0

0

0

0

0

Figure 12-16. Main Timer Interrupt Flag 1 (TFLG1)

Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit.

Table 12-13. TRLG1 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.

Field
1:0 C[1:0]F

Description
Input Capture/Output Compare Channel "x" Flag -- These flags are set when an input capture or output compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN is set to one.

Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel (0x0010­0x001F) will cause the corresponding channel flag CxF to be cleared.

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12.3.2.11 Main Timer Interrupt Flag 2 (TFLG2)

Module Base + 0x000F

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

TOF

W

Reset

0

0

0

0

0

0

0

0

Unimplemented or Reserved

Figure 12-17. Main Timer Interrupt Flag 2 (TFLG2)

TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one while TEN bit of TSCR1 .

Read: Anytime

Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).

Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.

Table 12-14. TRLG2 Field Descriptions

Field
7 TOF

Description
Timer Overflow Flag -- Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 is set to one .

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12.3.2.12 Timer Input Capture/Output Compare Registers High and Low 0­ 1(TCxH and TCxL)

Module Base + 0x0010 = TC0H 0x0012 = TC1H 0x0014=RESERVD 0x0016=RESERVD

0x0018=RESERVD 0x001A=RESERVD 0x001C=RESERVD 0x001E=RESERVD

15
R Bit 15
W

14
Bit 14

13
Bit 13

12
Bit 12

11
Bit 11

10
Bit 10

9
Bit 9

0
Bit 8

Reset

0

0

0

0

0

0

0

0

Figure 12-18. Timer Input Capture/Output Compare Register x High (TCxH)

Module Base + 0x0011 = TC0L 0x0013 = TC1L 0x0015 =RESERVD 0x0017=RESERVD

0x0019 =RESERVD 0x001B=RESERVD 0x001D=RESERVD 0x001F=RESERVD

7
R Bit 7
W

6
Bit 6

5
Bit 5

4
Bit 4

3
Bit 3

2
Bit 2

1
Bit 1

0
Bit 0

Reset

0

0

0

0

0

0

0

0

Figure 12-19. Timer Input Capture/Output Compare Register x Low (TCxL)

1 This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes.

Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare.

Read: Anytime

Write: Anytime for output compare function.Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to 0x0000.

NOTE
Read/Write access in byte mode for high byte should take place before low byte otherwise it will give a different result.

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12.3.2.13 Output Compare Pin Disconnect Register(OCPD)

Module Base + 0x002C

7

6

5

4

3

2

R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
W

1
OCPD1

Reset

0

0

0

0

0

0

0

Figure 12-20. Output Compare Pin Disconnect Register (OCPD)

Read: Anytime

Write: Anytime

All bits reset to zero.

0
OCPD0 0

Table 12-15. OCPD Field Description Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.

Field

Description

1:0 OCPD[1:0]

Output Compare Pin Disconnect Bits 0 Enables the timer channel port. Output Compare action will occur on the channel pin. These bits do not affect
the input capture . 1 Disables the timer channel port. Output Compare action will not occur on the channel pin, but the output
compare flag still become set.

12.3.2.14 Precision Timer Prescaler Select Register (PTPSR)

Module Base + 0x002E

7
R PTPS7
W

6
PTPS6

5
PTPS5

4
PTPS4

3
PTPS3

2
PTPS2

1
PTPS1

Reset

0

0

0

0

0

0

0

Figure 12-21. Precision Timer Prescaler Select Register (PTPSR)

Read: Anytime

Write: Anytime

All bits reset to zero.

0
PTPS0 0

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...
Table 12-16. PTPSR Field Descriptions

Field

Description

7:0 PTPS[7:0]

Precision Timer Prescaler Select Bits -- These eight bits specify the division rate of the main Timer prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 12-17 shows some selection examples in this case. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero.

The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit: PRNT = 1 : Prescaler = PTPS[7:0] + 1

PTPS7
0 0 0 0 0 0 0 1 1 1 1

Table 12-17. Precision Timer Prescaler Selection Examples when PRNT = 1

PTPS6
0 0 0 0 0 0 0 1 1 1 1

PTPS5
0 0 0 0 0 0 0 1 1 1 1

PTPS4
0 0 0 0 1 1 1 1 1 1 1

PTPS3
0 0 0 0 0 0 0 1 1 1 1

PTPS2
0 0 0 0 0 1 1 1 1 1 1

PTPS1
0 0 1 1 1 0 0 0 0 1 1

PTPS0
0 1 0 1 1 0 1 0 1 0 1

Prescale Factor
1 2 3 4 20 21 22 253 254 255 256

12.4 Functional Description
This section provides a complete functional description of the timer TIM16B2CV3 block. Please refer to the detailed timer block diagram in Figure 12-22 as necessary.

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tim source Clock PRNT

PTPSR[7:0] PRE-PRESCALER

PR[2:1:0] PRESCALER

1 MUX 0

TCNT(hi):TCNT(lo)

16-BIT COUNTER

CHANNEL 0 16-BIT COMPARATOR
TC0
EDG0A EDG0B CHANNEL 1
16-BIT COMPARATOR TC1
EDG1A EDG1B CHANNEL2

CxI CxF

TOF

INTERRUPT

TE

TOI

LOGIC

TOF

C0F EDGE DETECT

OM:OL0 TOV0

C0F IOC0

CH. 0 CAPTURE
IOC0 PIN LOGIC CH. 0COMPARE

IOC0 PIN

C1F EDGE DETECT

OM:OL1 TOV1

C1F IOC1

CH. 1 CAPTURE
IOC1 PIN LOGIC CH. 1 COMPARE

IOC1 PIN

CHANNELn-1 16-BIT COMPARATOR
TCn-1
EDG(n-1)A EDG(n-1)B

Cn-1F OM:OLn-1
EDGE TOVn-1 DETECT

Cn-1F IOCn-1

CH.n-1 CAPTURE

IOCn-1 PIN LOGIC CH.

IOCn-1 n-1COMPARE

PIN

n is channels number.

Figure 12-22. Detailed Timer Block Diagram
12.4.1 Prescaler
The prescaler divides the Bus clock by 1, 2, 4, 8, 16, 32, 64 or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
The prescaler divides the Bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled.

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By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this case, it is possible to set additional prescaler settings for the main timer counter in the present timer by using PTPSR[7:0] bits of PTPSR register generating divide by 1, 2, 3, 4,....20, 21, 22, 23,......255, or 256.
12.4.2 Input Capture
Clearing the I/O (input/output) select bit, IOSx, configures channel x as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, TCx.
The minimum pulse width for the input capture input is greater than two Bus clocks.
An input capture on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. Timer module must stay enabled (TEN bit of TSCR1 register must be set to one) while clearing CxF (writing one to CxF).
12.4.3 Output Compare
Setting the I/O select bit, IOSx, configures channel x when available as an output compare channel. The output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin if the corresponding OCPDx bit is set to zero. An output compare on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. Timer module must stay enabled (TEN bit of TSCR1 register must be set to one) while clearing CxF (writing one to CxF).
The output mode and level bits, OMx and OLx, select set, clear, toggle on output compare. Clearing both OMx and OLx results in no output compare action on the output compare channel pin.
Setting a force output compare bit, FOCx, causes an output compare on channel x. A forced output compare does not set the channel flag.
Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin.
12.4.3.1 OC Channel Initialization
The internal register whose output drives OCx can be programmed before the timer drives OCx. The desired state can be programmed to this internal register by writing a one to CFORCx bit with TIOSx, OCPDx and TEN bits set to one.
Set OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=1 and OCPDx=1 Clear OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=0 and OCPDx=1

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Setting OCPDx to zero allows the internal register to drive the programmed state to OCx. This allows a glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set to zero.

12.5 Resets
The reset state of each individual bit is listed within Section 12.3, "Memory Map and Register Definition" which details the registers and their bit fields

12.6 Interrupts

This section describes interrupts originated by the TIM16B2CV3 block. Table 12-18 lists the interrupts generated by the TIM16B2CV3 to communicate with the MCU.
Table 12-18. TIM16B2CV3 Interrupts

Interrupt

Offset Vector Priority

Source

Description

C[1:0]F

--

--

--

Timer Channel 1­0

Active high timer channel interrupts 1­0

TOF

--

--

--

Timer Overflow

Timer Overflow interrupt

The TIM16B2CV3 could use up to 3 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent.

12.6.1 Channel [1:0] Interrupt (C[1:0]F)
This active high outputs will be asserted by the module to request a timer channel 7 ­ 0 interrupt. The TIM block only generates the interrupt and does not service it. Only bits related to implemented channels are valid.

12.6.2 Timer Overflow Interrupt (TOF)
This active high output will be asserted by the module to request a timer overflow interrupt. The TIM block only generates the interrupt and does not service it.

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Revision History

Revision Number

Revision Date

V03.14 12 Nov 2012

V03.15

12 Jan 2013

V03.16 08 Aug 2013

Sections Affected
Table 13-10
Table 13-2 Table 13-25 Figure 13-37 13.1/13-477 13.3.2.15/13-
499

Description of Changes
· Corrected RxWRN and TxWRN threshold values · Updated TIME bit description · Added register names to buffer map · Updated TSRH and TSRL read conditions · Updated introduction · Updated CANTXERR and CANRXERR register notes
· Corrected typos

13.1 Introduction
Scalable controller area network (S12MSCANV3) definition is based on the MSCAN12 definition, which is the specific implementation of the MSCAN concept targeted for the S12, S12X and S12Z microcontroller families.
The module is a communication controller implementing the CAN 2.0A/B protocol as defined in the Bosch specification dated September 1991. For users to fully understand the MSCAN specification, it is recommended that the Bosch specification be read first to familiarize the reader with the terms and concepts contained within this document.
Though not exclusively intended for automotive applications, CAN protocol is designed to meet the specific requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness, and required bandwidth.
MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplified application software.

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13.1.1 Glossary
ACK CAN CRC EOF FIFO IFS SOF CPU bus CAN bus oscillator clock bus clock CAN clock

Table 13-1. Terminology
Acknowledge of CAN message Controller Area Network Cyclic Redundancy Code End of Frame First-In-First-Out Memory Inter-Frame Sequence Start of Frame CPU related read/write data bus CAN protocol related serial bus Direct clock from external oscillator CPU bus related clock CAN protocol related clock

13.1.2 Block Diagram

Oscillator Clock Bus Clock

MSCAN

CANCLK

Tq Clk

MUX

Presc.

Receive/ Transmit Engine

Transmit Interrupt Req. Receive Interrupt Req.
Errors Interrupt Req. Wake-Up Interrupt Req.

Control and
Status

Message Filtering
and Buffering

Configuration Registers

Wake-Up Low Pass Filter

Figure 13-1. MSCAN Block Diagram

RXCAN TXCAN

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13.1.3 Features
The basic features of the MSCAN are as follows: · Implementation of the CAN protocol -- Version 2.0A/B -- Standard and extended data frames -- Zero to eight bytes data length -- Programmable bit rate up to 1 Mbps1 -- Support for remote frames · Five receive buffers with FIFO storage scheme · Three transmit buffers with internal prioritization using a "local priority" concept · Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four 16-bit filters, or eight 8-bit filters · Programmable wake-up functionality with integrated low-pass filter · Programmable loopback mode supports self-test operation · Programmable listen-only mode for monitoring of CAN bus · Programmable bus-off recovery functionality · Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus-off) · Programmable MSCAN clock source either bus clock or oscillator clock · Internal timer for time-stamping of received and transmitted messages · Three low-power modes: sleep, power down, and MSCAN enable · Global initialization of configuration registers
13.1.4 Modes of Operation
For a description of the specific MSCAN modes and the module operation related to the system operating modes refer to Section 13.4.4, "Modes of Operation".

1. Depending on the actual bit timing and the clock jitter of the PLL.

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13.2 External Signal Description
The MSCAN uses two external pins. NOTE
On MCUs with an integrated CAN physical interface (transceiver) the MSCAN interface is connected internally to the transceiver interface. In these cases the external availability of signals TXCAN and RXCAN is optional.
13.2.1 RXCAN -- CAN Receiver Input Pin
RXCAN is the MSCAN receiver input pin.
13.2.2 TXCAN -- CAN Transmitter Output Pin
TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the CAN bus:
0 = Dominant state 1 = Recessive state
13.2.3 CAN System
A typical CAN system with MSCAN is shown in Figure 13-2. Each CAN station is connected physically to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current needed for the CAN bus and has current protection against defective CAN or defective stations.

CAN node 1 MCU
CAN Controller (MSCAN)

CAN node 2

TXCAN

RXCAN

Transceiver

CANH

CANL

CAN Bus

CAN node n

Figure 13-2. CAN System

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13.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the MSCAN.
13.3.1 Module Memory Map
Figure 13-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and can be found in the MCU memory map description. The address offset is defined at the module level. The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset.
The detailed register descriptions follow in the order they appear in the register map.

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Register Name
0x0000 CANCTL0
0x0001 CANCTL1
0x0002 CANBTR0
0x0003 CANBTR1
0x0004 CANRFLG
0x0005 CANRIER
0x0006 CANTFLG
0x0007 CANTIER
0x0008 CANTARQ
0x0009 CANTAAK
0x000A CANTBSEL
0x000B CANIDAC
0x000C Reserved
0x000D CANMISC

Bit 7

6

5

4

3

2

1

Bit 0

R RXFRM
W

R CANE
W

R SJW1
W

R SAMP
W

R WUPIF
W

R WUPIE
W

R

0

W

R

0

W

R

0

W

R

0

W

R

0

W

R

0

W

R

0

W

R

0

W

RXACT

CSWAI

SYNCH

TIME

CLKSRC LOOPB LISTEN BORM

WUPE

SLPRQ INITRQ

WUPM

SLPAK

INITAK

SJW0

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10

CSCIF

RSTAT1 RSTAT0 TSTAT1 TSTAT0

OVRIF

RXF

CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE

RXFIE

0

0

0

0

TXE2

TXE1

TXE0

0

0

0

0

TXEIE2 TXEIE1 TXEIE0

0

0

0

0

ABTRQ2 ABTRQ1 ABTRQ0

0

0

0

0

ABTAK2 ABTAK1 ABTAK0

0

0

0

0

TX2

TX1

TX0

0

0

IDHIT2

IDHIT1

IDHIT0

IDAM1

IDAM0

0

0

0

0

0

0

0

0

0

0

0

0

0

BOHOLD

= Unimplemented or Reserved Figure 13-3. MSCAN Register Summary

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Register Name
0x000E CANRXERR

Bit 7

6

5

4

3

2

1

Bit 0

R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 W

0x000F CANTXERR

R TXERR7 W

TXERR6

TXERR5

TXERR4

TXERR3

TXERR2

TXERR1

TXERR0

0x0010­0x0013 R

CANIDAR0­3 W AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

0x0014­0x0017 R

CANIDMRx

W

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

0x0018­0x001B R

CANIDAR4­7 W AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

0x001C­0x001F R CANIDMR4­7 W

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

0x0020­0x002F R

CANRXFG

W

See Section 13.3.3, "Programmer's Model of Message Storage"

0x0030­0x003F R

CANTXFG

W

See Section 13.3.3, "Programmer's Model of Message Storage"

= Unimplemented or Reserved

Figure 13-3. MSCAN Register Summary (continued)

13.3.2 Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. All bits of all registers in this module are completely synchronous to internal clocks during a register read.

13.3.2.1 MSCAN Control Register 0 (CANCTL0) The CANCTL0 register provides various control bits of the MSCAN module as described below.

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Module Base + 0x0000

Access: User read/write(1)

7
R RXFRM
W

6
RXACT

5
CSWAI

4
SYNCH

3
TIME

2
WUPE

1
SLPRQ

0
INITRQ

Reset:

0

0

0

0

0

0

0

1

= Unimplemented

Figure 13-4. MSCAN Control Register 0 (CANCTL0)
1. Read: Anytime Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode)

NOTE
The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).

Table 13-2. CANCTL0 Register Field Descriptions

Field

Description

7 RXFRM
6 RXACT
5 CSWAI(2)
4 SYNCH
3 TIME

Received Frame Flag -- This bit is read and clear only. It is set when a receiver has received a valid message correctly, independently of the filter configuration. After it is set, it remains set until cleared by software or reset. Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode. 0 No valid message was received since last clearing this flag 1 A valid message was received since last clearing of this flag
Receiver Active Status -- This read-only flag indicates the MSCAN is receiving a message(1). The flag is controlled by the receiver front end. This bit is not valid in loopback mode. 0 MSCAN is transmitting or idle 1 MSCAN is receiving a message (including when arbitration is lost)
CAN Stops in Wait Mode -- Enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the CPU bus interface to the MSCAN module. 0 The module is not affected during wait mode 1 The module ceases to be clocked during wait mode
Synchronized Status -- This read-only flag indicates whether the MSCAN is synchronized to the CAN bus and able to participate in the communication process. It is set and cleared by the MSCAN. 0 MSCAN is not synchronized to the CAN bus 1 MSCAN is synchronized to the CAN bus
Timer Enable -- This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active TX/RX buffer. Right after the EOF of a valid message on the CAN bus, the time stamp is written to the highest bytes (0x000E, 0x000F) in the appropriate buffer (see Section 13.3.3, "Programmer's Model of Message Storage"). In loopback mode no receive timestamp is generated. The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization mode. 0 Disable internal MSCAN timer 1 Enable internal MSCAN timer

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Table 13-2. CANCTL0 Register Field Descriptions (continued)

Field

Description

2 WUPE(3)

Wake-Up Enable -- This configuration bit allows the MSCAN to restart from sleep mode or from power down mode (entered from sleep) when traffic on CAN is detected (see Section 13.4.5.5, "MSCAN Sleep Mode"). This bit must be configured before sleep mode entry for the selected function to take effect. 0 Wake-up disabled -- The MSCAN ignores traffic on CAN 1 Wake-up enabled -- The MSCAN is able to restart

1 SLPRQ(4)

Sleep Mode Request -- This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 13.4.5.5, "MSCAN Sleep Mode"). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry to sleep mode by setting SLPAK = 1 (see Section 13.3.2.2, "MSCAN Control Register 1 (CANCTL1)"). SLPRQ cannot be set while the WUPIF flag is set (see Section 13.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)"). Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN detects activity on the CAN bus and clears SLPRQ itself. 0 Running -- The MSCAN functions normally 1 Sleep mode request -- The MSCAN enters sleep mode when CAN bus idle

0

Initialization Mode Request -- When this bit is set by the CPU, the MSCAN skips to initialization mode (see

INITRQ(5),(6) Section 13.4.4.5, "MSCAN Initialization Mode"). Any ongoing transmission or reception is aborted and

synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1

(Section 13.3.2.2, "MSCAN Control Register 1 (CANCTL1)"). The following registers enter their hard reset state and restore their default values: CANCTL0(7), CANRFLG(8), CANRIER(9), CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL.

The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be

written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the

error counters are not affected by initialization mode.

When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the

MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN

is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits.

Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after

initialization mode is exited, which is INITRQ = 0 and INITAK = 0.

0 Normal operation

1 MSCAN in initialization mode

1. See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states.

2. In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the CPU enters wait (CSWAI = 1) or stop mode (see Section 13.4.5.2, "Operation in Wait Mode" and Section 13.4.5.3, "Operation
in Stop Mode").

3. The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see Section 13.3.2.6, "MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required.

4. The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1).

5. The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1).

6. In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before requesting initialization mode.

7. Not including WUPE, INITRQ, and SLPRQ.

8. TSTAT1 and TSTAT0 are not affected by initialization mode.

9. RSTAT1 and RSTAT0 are not affected by initialization mode.

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13.3.2.2 MSCAN Control Register 1 (CANCTL1) The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below.

Module Base + 0x0001

Access: User read/write(1)

7
R CANE
W

6
CLKSRC

5
LOOPB

4
LISTEN

3
BORM

2
WUPM

1
SLPAK

0
INITAK

Reset:

0

0

0

1

0

0

0

1

= Unimplemented

Figure 13-5. MSCAN Control Register 1 (CANCTL1)
1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except CANE which is write once in normal and anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1)

Table 13-3. CANCTL1 Register Field Descriptions

Field

Description

7 CANE
6 CLKSRC
5 LOOPB
4 LISTEN
3 BORM

MSCAN Enable 0 MSCAN module is disabled 1 MSCAN module is enabled
MSCAN Clock Source -- This bit defines the clock source for the MSCAN module (only for systems with a clock generation module; Section 13.4.3.2, "Clock System," and Section Figure 13-43., "MSCAN Clocking Scheme,"). 0 MSCAN clock source is the oscillator clock 1 MSCAN clock source is the bus clock
Loopback Self Test Mode -- When this bit is set, the MSCAN performs an internal loopback which can be used for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN input is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Both transmit and receive interrupts are generated. 0 Loopback self test disabled 1 Loopback self test enabled
Listen Only Mode -- This bit configures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN messages with matching ID are received, but no acknowledgement or error frames are sent out (see Section 13.4.4.4, "Listen-Only Mode"). In addition, the error counters are frozen. Listen only mode supports applications which require "hot plugging" or throughput analysis. The MSCAN is unable to transmit any messages when listen only mode is active. 0 Normal operation 1 Listen only mode activated
Bus-Off Recovery Mode -- This bit configures the bus-off state recovery mode of the MSCAN. Refer to Section 13.5.2, "Bus-Off Recovery," for details. 0 Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol specification) 1 Bus-off recovery upon user request

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WUPM
1 SLPAK
0 INITAK

Chapter 13 Scalable Controller Area Network (S12MSCANV3)
Table 13-3. CANCTL1 Register Field Descriptions (continued)
Description
Wake-Up Mode -- If WUPE in CANCTL0 is enabled, this bit defines whether the integrated low-pass filter is applied to protect the MSCAN from spurious wake-up (see Section 13.4.5.5, "MSCAN Sleep Mode"). 0 MSCAN wakes up on any dominant level on the CAN bus 1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of Twup
Sleep Mode Acknowledge -- This flag indicates whether the MSCAN module has entered sleep mode (see Section 13.4.5.5, "MSCAN Sleep Mode"). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will clear the flag if it detects activity on the CAN bus while in sleep mode. 0 Running -- The MSCAN operates normally 1 Sleep mode active -- The MSCAN has entered sleep mode
Initialization Mode Acknowledge -- This flag indicates whether the MSCAN module is in initialization mode (see Section 13.4.4.5, "MSCAN Initialization Mode"). It is used as a handshake flag for the INITRQ initialization mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0­CANIDAR7, and CANIDMR0­CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode. 0 Running -- The MSCAN operates normally 1 Initialization mode active -- The MSCAN has entered initialization mode

13.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0) The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.

Module Base + 0x0002

7
R SJW1
W

6
SJW0

5
BRP5

4
BRP4

3
BRP3

2
BRP2

Reset:

0

0

0

0

0

0

Figure 13-6. MSCAN Bus Timing Register 0 (CANBTR0)
1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Access: User read/write(1)

1

0

BRP1

BRP0

0

0

Table 13-4. CANBTR0 Register Field Descriptions

Field

Description

7-6 SJW[1:0]
5-0 BRP[5:0]

Synchronization Jump Width -- The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the CAN bus (see Table 13-5).
Baud Rate Prescaler -- These bits determine the time quanta (Tq) clock which is used to build up the bit timing (see Table 13-6).

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Table 13-5. Synchronization Jump Width

SJW1 0 0 1 1

SJW0 0 1 0 1

Synchronization Jump Width 1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles 4 Tq clock cycles

BRP5
0 0 0 0 : 1

BRP4
0 0 0 0 : 1

Table 13-6. Baud Rate Prescaler

BRP3
0 0 0 0 : 1

BRP2
0 0 0 0 : 1

BRP1
0 0 1 1 : 1

BRP0
0 1 0 1 : 1

Prescaler value (P)
1 2 3 4 : 64

13.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.

Module Base + 0x0003

7
R SAMP
W

6
TSEG22

5
TSEG21

4
TSEG20

3
TSEG13

2
TSEG12

Reset:

0

0

0

0

0

0

Figure 13-7. MSCAN Bus Timing Register 1 (CANBTR1)
1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Access: User read/write(1)

1

0

TSEG11 TSEG10

0

0

Field
7 SAMP

Table 13-7. CANBTR1 Register Field Descriptions
Description
Sampling -- This bit determines the number of CAN bus samples taken per bit time. 0 One sample per bit. 1 Three samples per bit(1). If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit rates, it is recommended that only one sample is taken per bit time (SAMP = 0).

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Table 13-7. CANBTR1 Register Field Descriptions (continued)

Field

Description

6-4

Time Segment 2 -- Time segments within the bit time fix the number of clock cycles per bit time and the location

TSEG2[2:0] of the sample point (see Figure 13-44). Time segment 2 (TSEG2) values are programmable as shown in

Table 13-8.

3-0

Time Segment 1 -- Time segments within the bit time fix the number of clock cycles per bit time and the location

TSEG1[3:0] of the sample point (see Figure 13-44). Time segment 1 (TSEG1) values are programmable as shown in

Table 13-9.

1. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).

Table 13-8. Time Segment 2 Values

TSEG22

TSEG21

TSEG20

Time Segment 2

0

0

0

1 Tq clock cycle(1)

0

0

1

2 Tq clock cycles

:

:

:

:

1

1

0

7 Tq clock cycles

1

1

1

8 Tq clock cycles

1. This setting is not valid. Please refer to Table 13-36 for valid settings.

Table 13-9. Time Segment 1 Values

TSEG13

TSEG12

TSEG11

TSEG10

Time segment 1

0

0

0

0

1 Tq clock cycle(1)

0

0

0

1

2 Tq clock cycles1

0

0

1

0

3 Tq clock cycles1

0

0

1

1

4 Tq clock cycles

:

:

:

:

:

1

1

1

0

15 Tq clock cycles

1

1

1

1

16 Tq clock cycles

1. This setting is not valid. Please refer to Table 13-36 for valid settings.

The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit (as shown in Table 13-8 and Table 13-9).

Eqn. 13-1
Bit Þ Time= ---P----r---e----s-f--Cc----a-A---l--Ne---r-C---Þ--L----vK----a---l--u----e----  1 + TimeSegment1 + TimeSegment2

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13.3.2.5 MSCAN Receiver Flag Register (CANRFLG)
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the CANRIER register.

Module Base + 0x0004

Access: User read/write(1)

7
R WUPIF
W

6
CSCIF

5
RSTAT1

4
RSTAT0

3
TSTAT1

2
TSTAT0

1
OVRIF

0
RXF

Reset:

0

0

0

0

0

0

0

0

= Unimplemented

Figure 13-8. MSCAN Receiver Flag Register (CANRFLG)
1. Read: Anytime Write: Anytime when not in initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears flag; write of 0 is ignored

NOTE
The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).

Field 7
WUPIF
6 CSCIF

Table 13-10. CANRFLG Register Field Descriptions
Description
Wake-Up Interrupt Flag -- If the MSCAN detects CAN bus activity while in sleep mode (see Section 13.4.5.5, "MSCAN Sleep Mode,") and WUPE = 1 in CANTCTL0 (see Section 13.3.2.1, "MSCAN Control Register 0 (CANCTL0)"), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set. 0 No wake-up activity observed while in sleep mode 1 MSCAN detected activity on the CAN bus and requested wake-up
CAN Status Change Interrupt Flag -- This flag is set when the MSCAN changes its current CAN bus status due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the system on the actual CAN bus status (see Section 13.3.2.6, "MSCAN Receiver Interrupt Enable Register (CANRIER)"). If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the current CSCIF interrupt is cleared again. 0 No change in CAN bus status occurred since last interrupt 1 MSCAN changed current CAN bus status

1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode.
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Table 13-10. CANRFLG Register Field Descriptions (continued)

Field

Description

5-4 RSTAT[1:0]

Receiver Status Bits -- The values of the error counters control the actual CAN bus status of the MSCAN. As

soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related CAN

bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:

00 RxOK:

0  receive error counter  96

01 RxWRN: 96  receive error counter 128

10 RxERR: 128  receive error counter 11 Bus-off(1): 256transmit error counter

3-2 TSTAT[1:0]

Transmitter Status Bits -- The values of the error counters control the actual CAN bus status of the MSCAN. As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is: 00 TxOK: 0 transmit error counter  96 01 TxWRN: 96  transmit error counter 128 10 TxERR: 128  transmit error counter 256 11 Bus-Off: 256 transmit error counter

1 OVRIF

Overrun Interrupt Flag -- This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 0 No data overrun condition 1 A data overrun detected

0 RXF(2)

Receive Buffer Full Flag -- RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier, matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt is pending while this flag is set. 0 No new message available within the RxFG 1 The receiver FIFO is not empty. A new message is available in the RxFG

1. Redundant Information for the most critical CAN bus status which is "bus-off". This only occurs if the Tx error counter exceeds a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state skips to RxOK too. Refer also to TSTAT[1:0] coding in this register.

2. To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs, reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition.

13.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER)

This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register.

Module Base + 0x0005

Access: User read/write(1)

7
R WUPIE
W

6
CSCIE

5

4

3

2

RSTATE1 RSTATE0 TSTATE1 TSTATE0

1
OVRIE

Reset:

0

0

0

0

0

0

0

Figure 13-9. MSCAN Receiver Interrupt Enable Register (CANRIER)
1. Read: Anytime Write: Anytime when not in initialization mode

0
RXFIE 0

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NOTE The CANRIER register is held in the reset state when the initialization mode is active (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0).
The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode.

Table 13-11. CANRIER Register Field Descriptions

Field

Description

7 WUPIE(1)

Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request.

6 CSCIE

CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request.

5-4

Receiver Status Change Enable -- These RSTAT enable bits control the sensitivity level in which receiver state

RSTATE[1:0 changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT flags continue to

]

indicate the actual receiver state and are only updated if no CSCIF interrupt is pending.

00 Do not generate any CSCIF interrupt caused by receiver state changes.

01 Generate CSCIF interrupt only if the receiver enters or leaves "bus-off" state. Discard other receiver state

changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the receiver enters or leaves "RxErr" or "bus-off"(2) state. Discard other

receiver state changes for generating CSCIF interrupt.

11 Generate CSCIF interrupt on all state changes.

3-2

Transmitter Status Change Enable -- These TSTAT enable bits control the sensitivity level in which transmitter

TSTATE[1:0] state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags

continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending.

00 Do not generate any CSCIF interrupt caused by transmitter state changes.

01 Generate CSCIF interrupt only if the transmitter enters or leaves "bus-off" state. Discard other transmitter

state changes for generating CSCIF interrupt.

10 Generate CSCIF interrupt only if the transmitter enters or leaves "TxErr" or "bus-off" state. Discard other

transmitter state changes for generating CSCIF interrupt.

11 Generate CSCIF interrupt on all state changes.

1 OVRIE

Overrun Interrupt Enable 0 No interrupt request is generated from this event. 1 An overrun event causes an error interrupt request.

0 RXFIE

Receiver Full Interrupt Enable 0 No interrupt request is generated from this event. 1 A receive buffer full (successful message reception) event causes a receiver interrupt request.

1. WUPIE and WUPE (see Section 13.3.2.1, "MSCAN Control Register 0 (CANCTL0)") must both be enabled if the recovery mechanism from stop or wait is required.

2. Bus-off state is only defined for transmitters by the CAN standard (see Bosch CAN 2.0A/B protocol specification). Because the only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK, the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (see Section 13.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)").

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13.3.2.7 MSCAN Transmitter Flag Register (CANTFLG) The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register.

Module Base + 0x0006

Access: User read/write(1)

7

6

5

4

3

2

R

0

0

0

0

0

TXE2

W

Reset:

0

0

0

0

0

1

= Unimplemented

Figure 13-10. MSCAN Transmitter Flag Register (CANTFLG)
1. Read: Anytime Write: Anytime when not in initialization mode; write of 1 clears flag, write of 0 is ignored

1
TXE1 1

0
TXE0 1

NOTE
The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0).

Table 13-12. CANTFLG Register Field Descriptions

Field
2-0 TXE[2:0]

Description
Transmitter Buffer Empty -- This flag indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort request (see Section 13.3.2.9, "MSCAN Transmitter Message Abort Request Register (CANTARQ)"). If not masked, a transmit interrupt is pending while this flag is set. Clearing a TXEx flag also clears the corresponding ABTAKx (see Section 13.3.2.10, "MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)"). When a TXEx flag is set, the corresponding ABTRQx bit is cleared (see Section 13.3.2.9, "MSCAN Transmitter Message Abort Request Register (CANTARQ)"). When listen-mode is active (see Section 13.3.2.2, "MSCAN Control Register 1 (CANCTL1)") the TXEx flags cannot be cleared and no transmission is started. Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared (TXEx = 0) and the buffer is scheduled for transmission. 0 The associated message buffer is full (loaded with a message due for transmission) 1 The associated message buffer is empty (not scheduled)

13.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER) This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.

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Module Base + 0x0007

Access: User read/write(1)

7

6

5

4

3

2

1

R

0

0

0

0

0

TXEIE2

TXEIE1

W

Reset:

0

0

0

0

0

0

0

= Unimplemented

Figure 13-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)
1. Read: Anytime Write: Anytime when not in initialization mode

0
TXEIE0 0

NOTE
The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0).

Table 13-13. CANTIER Register Field Descriptions

Field

Description

2-0 TXEIE[2:0]

Transmitter Empty Interrupt Enable 0 No interrupt request is generated from this event. 1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt
request.

13.3.2.9 MSCAN Transmitter Message Abort Request Register (CANTARQ) The CANTARQ register allows abort request of queued messages as described below.

Module Base + 0x0008

Access: User read/write(1)

7

6

5

4

3

2

1

R

0

0

0

0

0

ABTRQ2 ABTRQ1

W

Reset:

0

0

0

0

0

0

0

= Unimplemented

Figure 13-12. MSCAN Transmitter Message Abort Request Register (CANTARQ)
1. Read: Anytime Write: Anytime when not in initialization mode

0
ABTRQ0 0

NOTE
The CANTARQ register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0).

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Table 13-14. CANTARQ Register Field Descriptions

Field

Description

2-0

Abort Request -- The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx = 0) be

ABTRQ[2:0] aborted. The MSCAN grants the request if the message has not already started transmission, or if the

transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see

Section 13.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and abort acknowledge flags (ABTAK, see

Section 13.3.2.10, "MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)") are set and a

transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated

TXE flag is set.

0 No abort request

1 Abort request pending

13.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)
The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register.

Module Base + 0x0009

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

0

0

0

0

ABTAK2

ABTAK1

ABTAK0

W

Reset:

0

0

0

0

0

0

0

0

= Unimplemented

Figure 13-13. MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)
1. Read: Anytime Write: Unimplemented

NOTE
The CANTAAK register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1).

Table 13-15. CANTAAK Register Field Descriptions

Field

Description

2-0 ABTAK[2:0]

Abort Acknowledge -- This flag acknowledges that a message was aborted due to a pending abort request from the CPU. After a particular message buffer is flagged empty, this flag can be used by the application software to identify whether the message was aborted successfully or was sent anyway. The ABTAKx flag is cleared whenever the corresponding TXE flag is cleared. 0 The message was not aborted. 1 The message was aborted.

13.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL)
The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be accessible in the CANTXFG register space.

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Module Base + 0x000A

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

0

0

0

0

TX2

TX1

TX0

W

Reset:

0

0

0

0

0

0

0

0

= Unimplemented

Figure 13-14. MSCAN Transmit Buffer Selection Register (CANTBSEL)
1. Read: Find the lowest ordered bit set to 1, all other bits will be read as 0 Write: Anytime when not in initialization mode

NOTE
The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0).

Table 13-16. CANTBSEL Register Field Descriptions

Field
2-0 TX[2:0]

Description
Transmit Buffer Select -- The lowest numbered bit places the respective transmit buffer in the CANTXFG register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx bit is cleared and the buffer is scheduled for transmission (see Section 13.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)"). 0 The associated message buffer is deselected 1 The associated message buffer is selected, if lowest numbered bit

The following gives a short programming example of the usage of the CANTBSEL register:
To get the next available transmit buffer, application software must read the CANTFLG register and write this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1. Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. This mechanism eases the application software's selection of the next available Tx buffer.
· LDAA CANTFLG; value read is 0b0000_0110
· STAA CANTBSEL; value written is 0b0000_0110
· LDAA CANTBSEL; value read is 0b0000_0010
If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers.

13.3.2.12 MSCAN Identifier Acceptance Control Register (CANIDAC) The CANIDAC register is used for identifier acceptance control as described below.

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Module Base + 0x000B

Access: User read/write(1)

7

R

0

W

6

5

4

3

2

1

0

0

IDHIT2

IDHIT1

IDAM1

IDAM0

Reset:

0

0

0

0

0

0

0

= Unimplemented

Figure 13-15. MSCAN Identifier Acceptance Control Register (CANIDAC)
1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only

0
IDHIT0
0

Table 13-17. CANIDAC Register Field Descriptions

Field

Description

5-4 IDAM[1:0]

Identifier Acceptance Mode -- The CPU sets these flags to define the identifier acceptance filter organization (see Section 13.4.3, "Identifier Acceptance Filter"). Table 13-18 summarizes the different settings. In filter closed mode, no message is accepted such that the foreground buffer is never reloaded.

2-0

Identifier Acceptance Hit Indicator -- The MSCAN sets these flags to indicate an identifier acceptance hit (see

IDHIT[2:0] Section 13.4.3, "Identifier Acceptance Filter"). Table 13-19 summarizes the different settings.

IDAM1 0 0 1 1

Table 13-18. Identifier Acceptance Mode Settings

IDAM0 0 1 0 1

Identifier Acceptance Mode Two 32-bit acceptance filters Four 16-bit acceptance filters Eight 8-bit acceptance filters
Filter closed

Table 13-19. Identifier Acceptance Hit Indication

IDHIT2
0 0 0 0 1 1 1 1

IDHIT1
0 0 1 1 0 0 1 1

IDHIT0
0 1 0 1 0 1 0 1

Identifier Acceptance Hit
Filter 0 hit Filter 1 hit Filter 2 hit Filter 3 hit Filter 4 hit Filter 5 hit Filter 6 hit Filter 7 hit

The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.

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13.3.2.13 MSCAN Reserved Register This register is reserved for factory testing of the MSCAN module and is not available in normal system operating modes.

Module Base + 0x000C

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

0

W

Reset:

0

0

0

0

0

0

0

0

= Unimplemented

Figure 13-16. MSCAN Reserved Register
1. Read: Always reads zero in normal system operation modes Write: Unimplemented in normal system operation modes

NOTE
Writing to this register when in special system operating modes can alter the MSCAN functionality.

13.3.2.14 MSCAN Miscellaneous Register (CANMISC) This register provides additional features.

Module Base + 0x000D

Access: User read/write(1)

7

6

5

4

3

2

1

R

0

0

0

0

0

0

0

W

Reset:

0

0

0

0

0

0

0

= Unimplemented

Figure 13-17. MSCAN Miscellaneous Register (CANMISC)
1. Read: Anytime Write: Anytime; write of `1' clears flag; write of `0' ignored

0
BOHOLD 0

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Table 13-20. CANMISC Register Field Descriptions

Field

Description

0 BOHOLD

Bus-off State Hold Until User Request -- If BORM is set in MSCAN Control Register 1 (CANCTL1), this bit indicates whether the module has entered the bus-off state. Clearing this bit requests the recovery from bus-off. Refer to Section 13.5.2, "Bus-Off Recovery," for details. 0 Module is not bus-off or recovery has been requested by user in bus-off state 1 Module is bus-off and holds this state until user request

13.3.2.15 MSCAN Receive Error Counter (CANRXERR) This register reflects the status of the MSCAN receive error counter.

Module Base + 0x000E

Access: User read/write(1)

7
R RXERR7

6
RXERR6

5
RXERR5

4
RXERR4

3
RXERR3

2
RXERR2

1
RXERR1

0
RXERR0

W

Reset:

0

0

0

0

0

0

0

0

= Unimplemented

Figure 13-18. MSCAN Receive Error Counter (CANRXERR)
1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented

NOTE
Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition.

13.3.2.16 MSCAN Transmit Error Counter (CANTXERR) This register reflects the status of the MSCAN transmit error counter.

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Module Base + 0x000F

Access: User read/write(1)

7
R TXERR7

6
TXERR6

5
TXERR5

4
TXERR4

3
TXERR3

2
TXERR2

1
TXERR1

0
TXERR0

W

Reset:

0

0

0

0

0

0

0

0

= Unimplemented

Figure 13-19. MSCAN Transmit Error Counter (CANTXERR)
1. Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented

NOTE
Reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition.

13.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0­IDR3 registers (see Section 13.3.3.1, "Identifier Registers (IDR0­IDR3)") of incoming messages in a bit by bit manner (see Section 13.4.3, "Identifier Acceptance Filter").
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only the first two (CANIDAR0/1, CANIDMR0/1) are applied.

Module Base + 0x0010 to Module Base + 0x0013

R W Reset

7
AC7 0

6
AC6 0

5
AC5 0

4
AC4 0

3
AC3 0

2
AC2 0

Access: User read/write(1)

1

0

AC1

AC0

0

0

Figure 13-20. MSCAN Identifier Acceptance Registers (First Bank) -- CANIDAR0­CANIDAR3
1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

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Field
7-0 AC[7:0]

Table 13-21. CANIDAR0­CANIDAR3 Register Field Descriptions
Description
Acceptance Code Bits -- AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.

Module Base + 0x0018 to Module Base + 0x001B

7
R AC7
W

Reset

0

6
AC6 0

5
AC5 0

4
AC4 0

3
AC3 0

2
AC2 0

Access: User read/write(1)

1

0

AC1

AC0

0

0

Figure 13-21. MSCAN Identifier Acceptance Registers (Second Bank) -- CANIDAR4­CANIDAR7
1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Field
7-0 AC[7:0]

Table 13-22. CANIDAR4­CANIDAR7 Register Field Descriptions
Description
Acceptance Code Bits -- AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.

13.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0­CANIDMR7)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to "don't care." To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to "don't care."

Module Base + 0x0014 to Module Base + 0x0017

R W Reset

7
AM7 0

6
AM6 0

5
AM5 0

4
AM4 0

3
AM3 0

2
AM2 0

Access: User read/write(1)

1

0

AM1

AM0

0

0

Figure 13-22. MSCAN Identifier Mask Registers (First Bank) -- CANIDMR0­CANIDMR3
1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

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Field
7-0 AM[7:0]

Table 13-23. CANIDMR0­CANIDMR3 Register Field Descriptions
Description
Acceptance Mask Bits -- If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit

Module Base + 0x001C to Module Base + 0x001F

R W Reset

7
AM7 0

6
AM6 0

5
AM5 0

4
AM4 0

3
AM3 0

2
AM2 0

Access: User read/write(1)

1

0

AM1

AM0

0

0

Figure 13-23. MSCAN Identifier Mask Registers (Second Bank) -- CANIDMR4­CANIDMR7
1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Field
7-0 AM[7:0]

Table 13-24. CANIDMR4­CANIDMR7 Register Field Descriptions
Description
Acceptance Mask Bits -- If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit

13.3.3 Programmer's Model of Message Storage
The following section details the organization of the receive and transmit message buffers and the associated control registers.
To simplify the programmer interface, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.
An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Within the last two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an internal timer after successful transmission or reception of a message. This feature is only available for transmit and receiver buffers, if the TIME bit is set (see Section 13.3.2.1, "MSCAN Control Register 0 (CANCTL0)").
The time stamp register is written by the MSCAN. The CPU can only read these registers.

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Table 13-25. Message Buffer Organization

Offset Address

Register

0x00X0 0x00X1 0x00X2 0x00X3 0x00X4 0x00X5 0x00X6 0x00X7 0x00X8 0x00X9 0x00XA 0x00XB 0x00XC 0x00XD 0x00XE 0x00XF

IDR0 -- Identifier Register 0 IDR1 -- Identifier Register 1 IDR2 -- Identifier Register 2 IDR3 -- Identifier Register 3 DSR0 -- Data Segment Register 0 DSR1 -- Data Segment Register 1 DSR2 -- Data Segment Register 2 DSR3 -- Data Segment Register 3 DSR4 -- Data Segment Register 4 DSR5 -- Data Segment Register 5 DSR6 -- Data Segment Register 6 DSR7 -- Data Segment Register 7 DLR -- Data Length Register TBPR -- Transmit Buffer Priority Register(1) TSRH -- Time Stamp Register (High Byte) TSRL -- Time Stamp Register (Low Byte)

1. Not applicable for receive buffers

Access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R R

Figure 13-24 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 13-25.
All bits of the receive and transmit buffers are `x' out of reset because of RAM-based implementation1. All reserved or unused bits of the receive and transmit buffers always read `x'.

1. Exception: The transmit buffer priority registers are 0 out of reset.

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Figure 13-24. Receive/Transmit Message Buffer -- Extended Identifier Mapping

Register Name

0x00X0

R

IDR0

W

Bit 7 ID28

6 ID27

5 ID26

4 ID25

3 ID24

2 ID23

1 ID22

0x00X1 IDR1

R W

ID20

ID19

ID18

SRR (=1) IDE (=1)

ID17

ID16

0x00X2 IDR2

R W

ID14

ID13

ID12

ID11

ID10

ID9

ID8

0x00X3

R

IDR3

W

ID6

ID5

ID4

ID3

ID2

ID1

ID0

0x00X4 DSR0

R W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

0x00X5 DSR1

R W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

0x00X6 DSR2

R W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

0x00X7 DSR3

R W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

0x00X8 DSR4

R W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

0x00X9 DSR5

R W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

0x00XA DSR6

R W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

0x00XB DSR7

R W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

0x00XC

R

DLR

W

DLC3

DLC2

DLC1

Bit0 ID21 ID15 ID7 RTR DB0 DB0 DB0 DB0 DB0 DB0 DB0 DB0 DLC0

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Figure 13-24. Receive/Transmit Message Buffer -- Extended Identifier Mapping (continued)

Register Name

Bit 7

6

5

4

3

2

1

Bit0

= Unused, always read `x'

Read:
· For transmit buffers, anytime when TXEx flag is set (see Section 13.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 13.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)").
· For receive buffers, only when RXF flag is set (see Section 13.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)").
Write:
· For transmit buffers, anytime when TXEx flag is set (see Section 13.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 13.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)").
· Unimplemented for receive buffers.
Reset: Undefined because of RAM-based implementation

Figure 13-25. Receive/Transmit Message Buffer -- Standard Identifier Mapping

Register Name

Bit 7

6

5

4

3

2

1

IDR0 0x00X0

R W

ID10

ID9

ID8

ID7

ID6

ID5

ID4

Bit 0 ID3

IDR1

R

0x00X1

W

ID2

ID1

ID0

RTR

IDE (=0)

IDR2

R

0x00X2

W

IDR3

R

0x00X3

W

= Unused, always read `x'
13.3.3.1 Identifier Registers (IDR0­IDR3) The identifier registers for an extended format identifier consist of a total of 32 bits: ID[28:0], SRR, IDE, and RTR. The identifier registers for a standard format identifier consist of a total of 13 bits: ID[10:0], RTR, and IDE.

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13.3.3.1.1 IDR0­IDR3 for Extended Identifier Mapping

Module Base + 0x00X0

R W Reset:

7
ID28

6
ID27

5
ID26

4
ID25

3
ID24

2
ID23

1
ID22

x

x

x

x

x

x

x

Figure 13-26. Identifier Register 0 (IDR0) -- Extended Identifier Mapping

Table 13-26. IDR0 Register Field Descriptions -- Extended

0
ID21 x

Field

Description

7-0 ID[28:21]

Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.

Module Base + 0x00X1

R W Reset:

7
ID20

6
ID19

5
ID18

4
SRR (=1)

3
IDE (=1)

2
ID17

1
ID16

x

x

x

x

x

x

x

Figure 13-27. Identifier Register 1 (IDR1) -- Extended Identifier Mapping

0
ID15 x

Table 13-27. IDR1 Register Field Descriptions -- Extended

Field

Description

7-5 ID[20:18]
4 SRR
3 IDE
2-0 ID[17:15]

Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
Substitute Remote Request -- This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and is stored as received on the CAN bus for receive buffers.
ID Extended -- This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit)
Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.

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Module Base + 0x00X2

7

6

5

4

3

2

1

0

R

ID14

ID13

ID12

ID11

ID10

ID9

ID8

ID7

W

Reset:

x

x

x

x

x

x

x

x

Figure 13-28. Identifier Register 2 (IDR2) -- Extended Identifier Mapping

Field
7-0 ID[14:7]

Table 13-28. IDR2 Register Field Descriptions -- Extended
Description
Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.

Module Base + 0x00X3

7

6

5

4

3

2

1

0

R

ID6

ID5

ID4

ID3

ID2

ID1

ID0

RTR

W

Reset:

x

x

x

x

x

x

x

x

Figure 13-29. Identifier Register 3 (IDR3) -- Extended Identifier Mapping

Field
7-1 ID[6:0]
0 RTR

Table 13-29. IDR3 Register Field Descriptions -- Extended
Description
Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
Remote Transmission Request -- This flag reflects the status of the remote transmission request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame

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13.3.3.1.2 IDR0­IDR3 for Standard Identifier Mapping

Module Base + 0x00X0

7

6

5

4

3

2

1

0

R

ID10

ID9

ID8

ID7

ID6

ID5

ID4

ID3

W

Reset:

x

x

x

x

x

x

x

x

Figure 13-30. Identifier Register 0 -- Standard Mapping

Table 13-30. IDR0 Register Field Descriptions -- Standard

Field
7-0 ID[10:3]

Description
Standard Format Identifier -- The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 13-31.

Module Base + 0x00X1

7

6

5

4

3

2

1

0

R

ID2

ID1

ID0

RTR

IDE (=0)

W

Reset:

x

x

x

x

x

x

x

x

= Unused; always read `x' Figure 13-31. Identifier Register 1 -- Standard Mapping

Field 7-5 ID[2:0]
4 RTR
3 IDE

Table 13-31. IDR1 Register Field Descriptions
Description
Standard Format Identifier -- The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 13-30.
Remote Transmission Request -- This flag reflects the status of the Remote Transmission Request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame
ID Extended -- This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit)

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Module Base + 0x00X2

7

6

5

4

3

2

1

0

R

W

Reset:

x

x

x

x

x

x

x

x

= Unused; always read `x' Figure 13-32. Identifier Register 2 -- Standard Mapping

Module Base + 0x00X3

7

6

5

4

3

2

1

0

R

W

Reset:

x

x

x

x

x

x

x

x

= Unused; always read `x'
Figure 13-33. Identifier Register 3 -- Standard Mapping
13.3.3.2 Data Segment Registers (DSR0-7)
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received. The number of bytes to be transmitted or received is determined by the data length code in the corresponding DLR register.

Module Base + 0x00X4 to Module Base + 0x00XB

7
R DB7
W

6
DB6

5
DB5

4
DB4

3
DB3

2
DB2

1
DB1

0
DB0

Reset:

x

x

x

x

x

x

x

x

Figure 13-34. Data Segment Registers (DSR0­DSR7) -- Extended Identifier Mapping

Field
7-0 DB[7:0]

Table 13-32. DSR0­DSR7 Register Field Descriptions

Data bits 7-0

Description

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13.3.3.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame.

Module Base + 0x00XC

7

6

5

4

3

2

1

R

DLC3

DLC2

DLC1

W

Reset:

x

x

x

x

x

x

x

= Unused; always read "x" Figure 13-35. Data Length Register (DLR) -- Extended Identifier Mapping

0
DLC0 x

Table 13-33. DLR Register Field Descriptions

Field
3-0 DLC[3:0]

Description
Data Length Code Bits -- The data length code contains the number of bytes (data byte count) of the respective message. During the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 13-34 shows the effect of setting the DLC bits.

DLC3
0 0 0 0 0 0 0 0 1

Table 13-34. Data Length Codes

Data Length Code

DLC2
0 0 0 0 1 1 1 1 0

DLC1
0 0 1 1 0 0 1 1 0

DLC0
0 1 0 1 0 1 0 1 0

Data Byte Count
0 1 2 3 4 5 6 7 8

13.3.3.4 Transmit Buffer Priority Register (TBPR)
This register defines the local priority of the associated message buffer. The local priority is used for the internal prioritization process of the MSCAN and is defined to be highest for the smallest binary number. The MSCAN implements the following internal prioritization mechanisms:
· All transmission buffers with a cleared TXEx flag participate in the prioritization immediately before the SOF (start of frame) is sent.

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· The transmission buffer with the lowest local priority field wins the prioritization. In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins.

Module Base + 0x00XD

Access: User read/write(1)

7
R PRIO7
W

6
PRIO6

5
PRIO5

4
PRIO4

3
PRIO3

2
PRIO2

1
PRIO1

0
PRIO0

Reset:

0

0

0

0

0

0

0

0

Figure 13-36. Transmit Buffer Priority Register (TBPR)
1. Read: Anytime when TXEx flag is set (see Section 13.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 13.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)") Write: Anytime when TXEx flag is set (see Section 13.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 13.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)")

13.3.3.5 Time Stamp Register (TSRH­TSRL)
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active transmit or receive buffer right after the EOF of a valid message on the CAN bus (see Section 13.3.2.1, "MSCAN Control Register 0 (CANCTL0)"). In case of a transmission, the CPU can only read the time stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The CPU can only read the time stamp registers.

Module Base + 0x00XE

Access: User read/write(1)

7
R TSR15

6
TSR14

5
TSR13

4
TSR12

3
TSR11

2
TSR10

1
TSR9

0
TSR8

W

Reset:

x

x

x

x

x

x

x

x

Figure 13-37. Time Stamp Register -- High Byte (TSRH)
1. Read: For transmit buffers: Anytime when TXEx flag is set (see Section 13.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 13.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)"). For receive buffers: Anytime when RXF is set. Write: Unimplemented

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Module Base + 0x00XF

Access: User read/write(1)

7
R TSR7

6
TSR6

5
TSR5

4
TSR4

3
TSR3

2
TSR2

1
TSR1

0
TSR0

W

Reset:

x

x

x

x

x

x

x

x

Figure 13-38. Time Stamp Register -- Low Byte (TSRL)
1. Read: or transmit buffers: Anytime when TXEx flag is set (see Section 13.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 13.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)"). For receive buffers: Anytime when RXF is set. Write: Unimplemented

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13.4.1 General
This section provides a complete functional description of the MSCAN.

13.4.2 Message Storage

CAN Receive / Transmit Engine

MSCAN

Rx0
Rx1 Rx2 Rx3 Rx4

Receiver

Memory Mapped I/O
RXF
CPU bus

RxBG RxFG

Tx0

TXE0

TxBG

MSCAN

TxFG

PRIO

Tx1

TXE1

PRIO

Tx2

TXE2

CPU bus

TxBG

Transmitter

PRIO

Figure 13-39. User Model for Message Buffer Organization

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The MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.
13.4.2.1 Message Transmit Background
Modern application layer software is built upon two fundamental assumptions:
· Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration.
· The internal message queue within any CAN node is organized such that the highest priority message is sent out first, if more than one message is ready to be sent.
The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer must be reloaded immediately after the previous message is sent. This loading process lasts a finite amount of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt.
A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a message is finished while the CPU re-loads the second buffer. No buffer would then be ready for transmission, and the CAN bus would be released.
At least three transmit buffers are required to meet the first of the above requirements under all circumstances. The MSCAN has three transmit buffers.
The second requirement calls for some sort of internal prioritization which the MSCAN implements with the "local priority" concept described in Section 13.4.2.2, "Transmit Structures."
13.4.2.2 Transmit Structures
The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. The three buffers are arranged as shown in Figure 13-39.
All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see Section 13.3.3, "Programmer's Model of Message Storage"). An additional Transmit Buffer Priority Register (TBPR) contains an 8-bit local priority field (PRIO) (see Section 13.3.3.4, "Transmit Buffer Priority Register (TBPR)"). The remaining two bytes are used for time stamping of a message, if required (see Section 13.3.3.5, "Time Stamp Register (TSRH­TSRL)").
To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (TXEx) flag (see Section 13.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)"). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the CANTBSEL register (see Section 13.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)"). This makes the respective buffer accessible within the CANTXFG address space (see Section 13.3.3, "Programmer's Model of Message Storage"). The algorithmic feature associated with the CANTBSEL register simplifies the transmit buffer selection. In addition, this scheme makes the handler

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software simpler because only one address area is applicable for the transmit process, and the required address space is minimized.
The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag.
The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE flag. A transmit interrupt (see Section 13.4.7.2, "Transmit Interrupt") is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer.
If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software programs this field when the message is set up. The local priority reflects the priority of this particular message relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO field is defined to be the highest priority. The internal scheduling process takes place whenever the MSCAN arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error.
When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers. Because messages that are already in transmission cannot be aborted, the user must request the abort by setting the corresponding abort request bit (ABTRQ) (see Section 13.3.2.9, "MSCAN Transmitter Message Abort Request Register (CANTARQ)".) The MSCAN then grants the request, if possible, by:
1. Setting the corresponding abort acknowledge flag (ABTAK) in the CANTAAK register. 2. Setting the associated TXE flag to release the buffer. 3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the
setting of the ABTAK flag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).

13.4.2.3 Receive Structures
The received messages are stored in a five stage input FIFO. The five message buffers are alternately mapped into a single memory area (see Figure 13-39). The background receive buffer (RxBG) is exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the CPU (see Figure 13-39). This scheme simplifies the handler software because only one address area is applicable for the receive process.
All receive buffers have a size of 15 bytes to store the CAN control bits, the identifier (standard or extended), the data contents, and a time stamp, if enabled (see Section 13.3.3, "Programmer's Model of Message Storage").
The receiver full flag (RXF) (see Section 13.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)") signals the status of the foreground receive buffer. When the buffer contains a correctly received message with a matching identifier, this flag is set.
On reception, each message is checked to see whether it passes the filter (see Section 13.4.3, "Identifier Acceptance Filter") and simultaneously is written into the active RxBG. After successful reception of a valid message, the MSCAN shifts the content of RxBG into the receiver FIFO, sets the RXF flag, and
1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also.

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generates a receive interrupt1 (see Section 13.4.7.3, "Receive Interrupt") to the CPU. The user's receive handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO.
When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt, or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see Section 13.3.2.2, "MSCAN Control Register 1 (CANCTL1)") where the MSCAN treats its own messages exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver.
An overrun condition occurs when all receive message buffers in the FIFO are filled with correctly received messages with accepted identifiers and another message is correctly received from the CAN bus with an accepted identifier. The latter message is discarded and an error interrupt with overrun indication is generated if enabled (see Section 13.4.7.5, "Error Interrupt"). The MSCAN remains able to transmit messages while the receiver FIFO is being filled, but all incoming messages are discarded. As soon as a receive buffer in the FIFO is available again, new valid messages will be accepted.

13.4.3 Identifier Acceptance Filter
The MSCAN identifier acceptance registers (see Section 13.3.2.12, "MSCAN Identifier Acceptance Control Register (CANIDAC)") define the acceptable patterns of the standard or extended identifier (ID[10:0] or ID[28:0]). Any of these bits can be marked `don't care' in the MSCAN identifier mask registers (see Section 13.3.2.18, "MSCAN Identifier Mask Registers (CANIDMR0­CANIDMR7)").
A filter hit is indicated to the application software by a set receive buffer full flag (RXF = 1) and three bits in the CANIDAC register (see Section 13.3.2.12, "MSCAN Identifier Acceptance Control Register (CANIDAC)"). These identifier hit flags (IDHIT[2:0]) clearly identify the filter section that caused the acceptance. They simplify the application software's task to identify the cause of the receiver interrupt. If more than one hit occurs (two or more filters match), the lower hit has priority.
A very flexible programmable generic identifier acceptance filter has been introduced to reduce the CPU interrupt loading. The filter is programmable to operate in four different modes:
· Two identifier acceptance filters, each to be applied to:
-- The full 29 bits of the extended identifier and to the following bits of the CAN 2.0B frame:
­ Remote transmission request (RTR)
­ Identifier extension (IDE)
­ Substitute remote request (SRR)
-- The 11 bits of the standard identifier plus the RTR and IDE bits of the CAN 2.0A/B messages. This mode implements two filters for a full length CAN 2.0B compliant extended identifier. Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters.
1. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also.

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Figure 13-40 shows how the first 32-bit filter bank (CANIDAR0­CANIDAR3, CANIDMR0­ CANIDMR3) produces a filter 0 hit. Similarly, the second filter bank (CANIDAR4­ CANIDAR7, CANIDMR4­CANIDMR7) produces a filter 1 hit.
· Four identifier acceptance filters, each to be applied to:
-- The 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages.
-- The 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages. Figure 13-41 shows how the first 32-bit filter bank (CANIDAR0­CANIDAR3, CANIDMR0­ CANIDMR3) produces filter 0 and 1 hits. Similarly, the second filter bank (CANIDAR4­ CANIDAR7, CANIDMR4­CANIDMR7) produces filter 2 and 3 hits.
· Eight identifier acceptance filters, each to be applied to the first 8 bits of the identifier. This mode implements eight independent filters for the first 8 bits of a CAN 2.0A/B compliant standard identifier or a CAN 2.0B compliant extended identifier. Figure 13-42 shows how the first 32-bit filter bank (CANIDAR0­CANIDAR3, CANIDMR0­ CANIDMR3) produces filter 0 to 3 hits. Similarly, the second filter bank (CANIDAR4­ CANIDAR7, CANIDMR4­CANIDMR7) produces filter 4 to 7 hits.
· Closed filter. No CAN message is copied into the foreground buffer RxFG, and the RXF flag is never set.

CAN 2.0B Extended IdentifieIDr 28 StaCnAdaNrd2.I0dAe/nBtifieIrD10

IDR0 IDR0

ID21 ID20 ID3 ID2

IDR1 IDR1

ID15 ID14 IDE ID10

IDR2 IDR2

ID7 ID6 ID3 ID10

IDR3 IDR3

RTR ID3

AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0
ID Accepted (Filter 0 Hit)
Figure 13-40. 32-bit Maskable Identifier Acceptance Filter

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CAN 2.0B Extended IdentifieIrD28 StaCnAdNard2.I0dAe/nBtifieIrD10

IDR0 IDR0

ID21 ID20 ID3 ID2

IDR1 IDR1

ID15 ID14 IDE ID10

IDR2 IDR2

ID7 ID6 ID3 ID10

IDR3 IDR3

RTR ID3

AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0
ID Accepted (Filter 0 Hit)

AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0
AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0
ID Accepted (Filter 1 Hit)
Figure 13-41. 16-bit Maskable Identifier Acceptance Filters

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IDR0 IDR0

ID21 ID20 ID3 ID2

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IDR1 IDR1

ID15 ID14 IDE ID10

IDR2 IDR2

ID7 ID6 ID3 ID10

IDR3 IDR3

RTR ID3

AM7

CIDMR0 AM0

AC7

CIDAR0 AC0

ID Accepted (Filter 0 Hit)

AM7

CIDMR1 AM0

AC7

CIDAR1 AC0

ID Accepted (Filter 1 Hit)

AM7

CIDMR2 AM0

AC7

CIDAR2 AC0

ID Accepted (Filter 2 Hit)

AM7

CIDMR3 AM0

AC7

CIDAR3 AC0

ID Accepted (Filter 3 Hit)
Figure 13-42. 8-bit Maskable Identifier Acceptance Filters

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13.4.3.1 Protocol Violation Protection
The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features:
· The receive and transmit error counters cannot be written or otherwise manipulated. · All registers which control the configuration of the MSCAN cannot be modified while the MSCAN
is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK handshake bits in the CANCTL0/CANCTL1 registers (see Section 13.3.2.1, "MSCAN Control Register 0 (CANCTL0)") serve as a lock to protect the following registers: -- MSCAN control 1 register (CANCTL1) -- MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1) -- MSCAN identifier acceptance control register (CANIDAC) -- MSCAN identifier acceptance registers (CANIDAR0­CANIDAR7) -- MSCAN identifier mask registers (CANIDMR0­CANIDMR7) · The TXCAN is immediately forced to a recessive state when the MSCAN goes into the power down mode or initialization mode (see Section 13.4.5.6, "MSCAN Power Down Mode," and Section 13.4.4.5, "MSCAN Initialization Mode"). · The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which provides further protection against inadvertently disabling the MSCAN.
13.4.3.2 Clock System
Figure 13-43 shows the structure of the MSCAN clock generation circuitry.

Bus Clock

MSCAN

Oscillator Clock

CLKSRC

CANCLK

Prescaler (1 .. 64)
CLKSRC

Time quanta clock (Tq)

Figure 13-43. MSCAN Clocking Scheme
The clock source bit (CLKSRC) in the CANCTL1 register (13.3.2.2/13-486) defines whether the internal CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock.
The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the clock is required.
If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates.

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For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock).
A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN.

Tq= ---P----r---e----s---fc---C-a--A--l--eN---r-C---Þ-L----K-v----a---l--u----e--

Eqn. 13-2

A bit time is subdivided into three segments as described in the Bosch CAN 2.0A/B specification. (see Figure 13-44):
· SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section.
· Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta.
· Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.

Bit Þ Rate= ---n----u----m------b----e---r----Þ------o----f---Þ--f--T--T-q---i--m------e----Þ------Q-----u----a----n----t--a----

Eqn. 13-3

NRZ Signal

SYNC_SEG

Time Segment 1 (PROP_SEG + PHASE_SEG1)

Time Segment 2 (PHASE_SEG2)

1

4 ... 16

2 ... 8

8 ... 25 Time Quanta = 1 Bit Time

Transmit Point

Sample Point (single or triple sampling)

Figure 13-44. Segments within the Bit Time

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Table 13-35. Time Segment Syntax

Syntax

Description

SYNC_SEG Transmit Point Sample Point

System expects transitions to occur on the CAN bus during this period.
A node in transmit mode transfers a new value to the CAN bus at this point.
A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.

The synchronization jump width (see the Bosch CAN 2.0A/B specification for details) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter.
The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are set by programming the MSCAN bus timing registers (CANBTR0, CANBTR1) (see Section 13.3.2.3, "MSCAN Bus Timing Register 0 (CANBTR0)" and Section 13.3.2.4, "MSCAN Bus Timing Register 1 (CANBTR1)").
Table 13-36 gives an overview of the Bosch CAN 2.0A/B specification compliant segment settings and the related parameter values.
NOTE It is the user's responsibility to ensure the bit time settings are in compliance with the CAN standard.

Table 13-36. Bosch CAN 2.0A/B Compliant Bit Time Segment Settings

Time Segment 1
5 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 9 .. 16

TSEG1
4 .. 9 3 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15

Time Segment 2
2 3 4 5 6 7 8

TSEG2
1 2 3 4 5 6 7

Synchronization Jump Width
1 .. 2 1 .. 3 1 .. 4 1 .. 4 1 .. 4 1 .. 4 1 .. 4

SJW
0 .. 1 0 .. 2 0 .. 3 0 .. 3 0 .. 3 0 .. 3 0 .. 3

13.4.4 Modes of Operation

13.4.4.1 Normal System Operating Modes
The MSCAN module behaves as described within this specification in all normal system operating modes. Write restrictions exist for some registers.

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13.4.4.2 Special System Operating Modes
The MSCAN module behaves as described within this specification in all special system operating modes. Write restrictions which exist on specific registers in normal modes are lifted for test purposes in special modes.
13.4.4.3 Emulation Modes
In all emulation modes, the MSCAN module behaves just like in normal system operating modes as described within this specification.
13.4.4.4 Listen-Only Mode
In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames and valid remote frames, but it sends only "recessive" bits on the CAN bus. In addition, it cannot start a transmission.
If the MAC sub-layer is required to send a "dominant" bit (ACK bit, overload flag, or active error flag), the bit is rerouted internally so that the MAC sub-layer monitors this "dominant" bit, although the CAN bus may remain in recessive state externally.
13.4.4.5 MSCAN Initialization Mode
The MSCAN enters initialization mode when it is enabled (CANE=1).
When entering initialization mode during operation, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations, the MSCAN immediately drives TXCAN into a recessive state.
NOTE The user is responsible for ensuring that the MSCAN is not active when initialization mode is entered. The recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going message can cause an error condition and can impact other CAN bus devices.
In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the configuration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message filters. See Section 13.3.2.1, "MSCAN Control Register 0 (CANCTL0)," for a detailed description of the initialization mode.

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Bus Clock Domain

CPU Init Request

INITRQ

INITAK Flag

sync.
INITAK

SYNC

CAN Clock Domain

sync. INITRQ

INIT Flag

SYNC

INITAK

Figure 13-45. Initialization Request/Acknowledge Cycle
Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay (see Figure 13-45).
If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the INITAK flag is set. The application software must use INITAK as a handshake indication for the request (INITRQ) to go into initialization mode.
NOTE The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and INITAK = 1) is active.
13.4.5 Low-Power Options
If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving.
If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption is reduced by stopping all clocks except those to access the registers from the CPU side. In power down mode, all clocks are stopped and no power is consumed.
Table 13-37 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits.

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CPU Mode
RUN WAIT STOP 1. `X' means don't care.

Table 13-37. CPU vs. MSCAN Operating Modes

MSCAN Mode

Normal
CSWAI = X(1) SLPRQ = 0 SLPAK = 0 CSWAI = 0 SLPRQ = 0 SLPAK = 0

Reduced Power Consumption

Sleep

Power Down

Disabled (CANE=0)

CSWAI = X SLPRQ = 1 SLPAK = 1
CSWAI = 0 SLPRQ = 1 SLPAK = 1

CSWAI = 1 SLPRQ = X SLPAK = X
CSWAI = X SLPRQ = X SLPAK = X

CSWAI = X SLPRQ = X SLPAK = X
CSWAI = X SLPRQ = X SLPAK = X
CSWAI = X SLPRQ = X SLPAK = X

13.4.5.1 Operation in Run Mode
As shown in Table 13-37, only MSCAN sleep mode is available as low power option when the CPU is in run mode.
13.4.5.2 Operation in Wait Mode
The WAI instruction puts the MCU in a low power consumption stand-by mode. If the CSWAI bit is set, additional power can be saved in power down mode because the CPU clocks are stopped. After leaving this power down mode, the MSCAN restarts and enters normal mode again.
While the CPU is in wait mode, the MSCAN can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode).
13.4.5.3 Operation in Stop Mode
The STOP instruction puts the MCU in a low power consumption stand-by mode. In stop mode, the MSCAN is set in power down mode regardless of the value of the SLPRQ/SLPAK and CSWAI bits (Table 13-37).
13.4.5.4 MSCAN Normal Mode
This is a non-power-saving mode. Enabling the MSCAN puts the module from disabled mode into normal mode. In this mode the module can either be in initialization mode or out of initialization mode. See Section 13.4.4.5, "MSCAN Initialization Mode".

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13.4.5.5 MSCAN Sleep Mode
The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a fixed synchronization delay and its current activity:
· If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted successfully or aborted) and then goes into sleep mode.
· If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle.
· If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode.

Bus Clock Domain

CPU Sleep Request

SLPRQ

SLPAK Flag

sync.
SLPAK

SYNC

CAN Clock Domain

sync. SLPRQ

SLPRQ Flag

SYNC

SLPAK

MSCAN in Sleep Mode

Figure 13-46. Sleep Request / Acknowledge Cycle
NOTE The application software must avoid setting up a transmission (by clearing one or more TXEx flag(s)) and immediately request sleep mode (by setting SLPRQ). Whether the MSCAN starts transmitting or goes into sleep mode directly depends on the exact sequence of operations.
If sleep mode is active, the SLPRQ and SLPAK bits are set (Figure 13-46). The application software must use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode.
When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks that allow register accesses from the CPU side continue to run.
If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. TXCAN remains in a recessive state. If RXF = 1, the message can be read and RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does not take place while in sleep mode.
It is possible to access the transmit buffers and to clear the associated TXE flags. No message abort takes place while in sleep mode.

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If the WUPE bit in CANCTL0 is not asserted, the MSCAN will mask any activity it detects on CAN. RXCAN is therefore held internally in a recessive state. This locks the MSCAN in sleep mode. WUPE must be set before entering sleep mode to take effect.
The MSCAN is able to leave sleep mode (wake up) only when: · CAN bus activity occurs and WUPE = 1 or · the CPU clears the SLPRQ bit
NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active.
After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received.
The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it continues counting the 128 occurrences of 11 consecutive recessive bits.
13.4.5.6 MSCAN Power Down Mode
The MSCAN is in power down mode (Table 13-37) when · CPU is in stop mode or · CPU is in wait mode and the CSWAI bit is set
When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN immediately drives TXCAN into a recessive state.
NOTE The user is responsible for ensuring that the MSCAN is not active when power down mode is entered. The recommended procedure is to bring the MSCAN into Sleep mode before the STOP or WAI instruction (if CSWAI is set) is executed. Otherwise, the abort of an ongoing message can cause an error condition and impact other CAN bus devices.
In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. This causes some fixed delay before the module enters normal mode again.

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13.4.5.7 Disabled Mode The MSCAN is in disabled mode out of reset (CANE=0). All module clocks are stopped for power saving, however the register map can still be accessed as specified.

13.4.5.8 Programmable Wake-Up Function
The MSCAN can be programmed to wake up from sleep or power down mode as soon as CAN bus activity is detected (see control bit WUPE in MSCAN Control Register 0 (CANCTL0). The sensitivity to existing CAN bus action can be modified by applying a low-pass filter function to the RXCAN input line (see control bit WUPM in Section 13.3.2.2, "MSCAN Control Register 1 (CANCTL1)").
This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines. Such glitches can result from--for example--electromagnetic interference within noisy environments.

13.4.6 Reset Initialization
The reset state of each individual bit is listed in Section 13.3.2, "Register Descriptions," which details all the registers and their bit-fields.

13.4.7 Interrupts
This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated flags. Each interrupt is listed and described separately.

13.4.7.1 Description of Interrupt Operation
The MSCAN supports four interrupt vectors (see Table 13-38), any of which can be individually masked (for details see Section 13.3.2.6, "MSCAN Receiver Interrupt Enable Register (CANRIER)" to Section 13.3.2.8, "MSCAN Transmitter Interrupt Enable Register (CANTIER)").
Refer to the device overview section to determine the dedicated interrupt vector addresses.

Table 13-38. Interrupt Vectors

Interrupt Source
Wake-Up Interrupt (WUPIF) Error Interrupts Interrupt (CSCIF, OVRIF) Receive Interrupt (RXF) Transmit Interrupts (TXE[2:0])

CCR Mask

Local Enable

I bit

CANRIER (WUPIE)

I bit

CANRIER (CSCIE, OVRIE)

I bit

CANRIER (RXFIE)

I bit

CANTIER (TXEIE[2:0])

13.4.7.2 Transmit Interrupt
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx flag of the empty message buffer is set.

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13.4.7.3 Receive Interrupt
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the foreground buffer.
13.4.7.4 Wake-Up Interrupt
A wake-up interrupt is generated if activity on the CAN bus occurs during MSCAN sleep or power-down mode.
NOTE This interrupt can only occur if the MSCAN was in sleep mode (SLPRQ = 1 and SLPAK = 1) before entering power down mode, the wake-up option is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).
13.4.7.5 Error Interrupt
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition occurs. MSCAN Receiver Flag Register (CANRFLG) indicates one of the following conditions:
· Overrun -- An overrun condition of the receiver FIFO as described in Section 13.4.2.3, "Receive Structures," occurred.
· CAN Status Change -- The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rxwarning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change, which caused the error condition, is indicated by the TSTAT and RSTAT flags (see Section 13.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)" and Section 13.3.2.6, "MSCAN Receiver Interrupt Enable Register (CANRIER)").
13.4.7.6 Interrupt Acknowledge
Interrupts are directly associated with one or more status flags in either the MSCAN Receiver Flag Register (CANRFLG) or the MSCAN Transmitter Flag Register (CANTFLG). Interrupts are pending as long as one of the corresponding flags is set. The flags in CANRFLG and CANTFLG must be reset within the interrupt handler to handshake the interrupt. The flags are reset by writing a 1 to the corresponding bit position. A flag cannot be cleared if the respective condition prevails.
NOTE It must be guaranteed that the CPU clears only the bit causing the current interrupt. For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt flags. These instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine.

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13.5 Initialization/Application Information
13.5.1 MSCAN initialization
The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the configuration registers in initialization mode 3. Clear INITRQ to leave initialization mode
If the configuration of registers which are only writable in initialization mode shall be changed: 1. Bring the module into sleep mode by setting SLPRQ and awaiting SLPAK to assert after the CAN bus becomes idle. 2. Enter initialization mode: assert INITRQ and await INITAK 3. Write to the configuration registers in initialization mode 4. Clear INITRQ to leave initialization mode and continue
13.5.2 Bus-Off Recovery
The bus-off recovery is user configurable. The bus-off state can either be left automatically or on user request.
For reasons of backwards compatibility, the MSCAN defaults to automatic recovery after reset. In this case, the MSCAN will become error active again after counting 128 occurrences of 11 consecutive recessive bits on the CAN bus (see the Bosch CAN 2.0 A/B specification for details).
If the MSCAN is configured for user request (BORM set in MSCAN Control Register 1 (CANCTL1)), the recovery from bus-off starts after both independent events have become true:
· 128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored · BOHOLD in MSCAN Miscellaneous Register (CANMISC) has been cleared by the user
These two events may occur in any order.

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Rev. No. (Item No.)

Data

01.00 02.00

21 Oct. 2011 22. Mar. 2012

3.0 16. Jul. 2013

Table 14-1. Revision History Table

Sections Affected
all
14.3.2.1, 14.3.2.7, 14.3.2.10, 14.3.2.14 14.3.2.17

Substantial Change(s)
Initial Version
- removed PTUWP bit (now: PTUPTR is write protected if both TGs are disabled, TGxLxIDX is write protected if the associated TG is disabled) - TGxLIST bits are writeable if associated TG is disabled - PTULDOK bit is writable if both TGs are disabled - TGxLIST swap at every reload with LDOK set

minor corrections

Term TG EOL

Trigger Generator End of trigger list

Table 14-2. Terminology Meaning

14.1 Introduction
In PWM driven systems it is important to schedule the acquisition of the state variables with respect to PWM cycle.
The Programmable Trigger Unit (PTU) is intended to completely avoid CPU involvement in the time acquisitions of state variables during the control cycle that can be half, full, multiple PWM cycles.
All acquisition time values are stored inside the global memory map, basically inside the system memory; see the MMC section for the supported memory area. In such cases the pre-setting of the acquisition times needs to be completed during the previous control cycle to where the actual acquisitions are to be made.

14.1.1 Features
The PTU module includes these distinctive features: · One 16 bit counter as time base for all trigger events · Two independent trigger generators (TG0 and TG1) · Up to 32 trigger events per trigger generator

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· Global Load OK support, to guarantee coherent update of all control loop modules · Trigger values stored inside the global memory map, basically inside system memory · Software generated reload event and Trigger event generation for debugging
14.1.2 Modes of Operation
The PTU module behaves as follows in the system power modes: 1. Run mode All PTU features are available. 2. Wait mode All PTU features are available. 3. Freeze Mode Depends on the PTUFRZ register bit setting the internal counter is stopped and no trigger events will be generated. 4. Stop mode The PTU is disabled and the internal counter is stopped; no trigger events will be generated. The content of the configuration register is unchanged.

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14.1.3 Block Diagram
Figure 14-1 shows a block diagram of the PTU module.

Chapter 14 Programmable Trigger Unit (PTUV3)

Global Memory Map

Trigger 1
Trig.g..er 2

Trigger 1
Trig.g..er 2

Trigger n

Trigger n

Module A

Bus Clock
reload_is_async reload

Time Base Counter

Trigger Generator (TG0) Trigger Generator (TG1)

Control Logic
PTU

trigger_0

PTUT0

trigger_1

PTUT1

Module B

ptu_reload_is_async ptu_reload
glb_ldok

PTURE

Figure 14-1. PTU Block Diagram
14.2 External Signal Description
This section lists the name and description of all external ports.
14.2.1 PTUT0 -- PTU Trigger 0
If enabled (PTUT0PE is set) this pin shows the internal trigger_0 event.
14.2.2 PTUT1 -- PTU Trigger 1
If enabled (PTUT1PE is set) this pin shows the internal trigger_1 event.

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14.2.3 PTURE -- PTUE Reload Event
If enabled (PTUREPE is set) this pin shows the internal reload event.
14.3 Memory Map and Register Definition
This section provides the detailed information of all registers for the PTU module.

14.3.1 Register Summary
Figure 14-2 shows the summary of all implemented registers inside the PTU module.
NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level.

Address Offset Register Name

Bit 7

6

5

4

3

2

1

Bit 0

0x0000

R

0

0

0

0

0

PTUE

W

PTUFRZ

TG1EN TG0EN

0x0001

R

0

0

0

0

0

0

0

PTUC

W

PTULDOK

0x0002

R

0

0

0

0

0

0

0

PTUIEH

W

PTUROIE

0x0003 PTUIEL

R TG1AEIE TG1REIE TG1TEIE
W

TG1DIE

TG0AEIE TG0REIE TG0TEIE

TG0DIE

0x0004

R

0

0

0

0

0

0

PTUIFH

W

PTUDEEF PTUROIF

0x0005 PTUIFL
0x0006 TG0LIST

R TG1AEIF TG1REIF TG1TEIF
W

R

0

0

0

W

TG1DIF 0

TG0AEIF TG0REIF TG0TEIF TG0DIF

0

0

0

TG0LIST

0x0007

R

0

0

0

TG0TNUM

W

0x0008

R

TG0TVH

W

TG0TNUM[4:0] TG0TV[15:8]

= Unimplemented Figure 14-2. PTU Register Summary

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Address Offset Register Name

Bit 7

6

5

4

3

2

1

0x0009

R

TG0TVL

W

TG0TV[7:0]

0x000A

R

0

0

0

0

0

0

0

TG1LIST

W

0x000B

R

0

0

0

TG1TNUM

W

TG1TNUM[4:0]

0x000C

R

TG1TVH

W

TG1TV[15:8]

0x000D

R

TG1TVL

W

TG1TV[7:0]

0x000E

R

PTUCNTH

W

PTUCNT[15:8]

0x000F

R

PTUCNTL

W

PTUCNT[7:0]

0x0010

R

0

0

0

0

0

0

0

Reserved

W

0x0011

R

PTUPTRH

W

PTUPTR[23:16]

0x0012

R

PTUPTRM

W

PTUPTR[15:8]

0x0013

R

PTUPTRL

W

PTUPTR[7:1]

0x0014

R

0

TG0L0IDX

W

TG0L10DX[6:0]

0x0015

R

0

TG0L1IDX

W

TG0L1IDX[6:0]

0x0016

R

0

TG1L0IDX

W

TG1L0IDX[6:0]

0x0017

R

0

TG1L1IDX

W

TG1L1IDX[6:0]

= Unimplemented Figure 14-2. PTU Register Summary

Bit 0 TG1LIST
0 0

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Address Offset Register Name

0x0018 - 0x001E R

Reserved

W

Bit 7 0

0x001F

R

0

PTUDEBUG W

6

5

4

3

0

0

0

0

PTUREPE PTUT1PE

PTUT0P E

0

= Unimplemented Figure 14-2. PTU Register Summary

2

1

Bit 0

0

0

0

0

0

PTUFRE TG1FTE

0 TG0FTE

14.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Unused bits read back zero.

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14.3.2.1 PTU Module Enable Register (PTUE)
Module Base + 0x0000

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

0

0

0

0

PTUFRZ

TG1EN

TG0EN

W

Reset

0

0

0

0

0

0

0

0

1. Read: Anytime Write: Anytime

= Unimplemented Figure 14-3. PTU Module Enable Register (PTUE)

Table 14-3. PTUE Register Field Description

Field

Description

6 PTUFRZ

PTU Stop in Freeze Mode -- In freeze mode, there is an option to disable the input clock to the PTU time base counter. If this bit is set, whenever the MCU is in freeze mode, the input clock to the time base counter is disabled. In this way, the counters can be stopped while in freeze mode so that once normal program flow is continued, the counter is re-enabled. 0 Allow time base counter to continue while in freeze mode 1 Disable time base counter clock whenever the part is in freeze mode

1 TG1EN

Trigger Generator 1 Enable -- This bit enables trigger generator 1. 0 Trigger generator 1 is disabled 1 Trigger generator 1 is enabled

0 TG0EN

Trigger Generator 0 Enable -- This bit enables trigger generator 0. 0 Trigger generator 0 is disabled 1 Trigger generator 0 is enabled

14.3.2.2 PTU Module Control Register (PTUC)

Module Base + 0x0001

7

6

5

4

3

2

R

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

= Unimplemented

Figure 14-4. PTU Module Control Register (PTUC)
1. Read: Anytime Write: write 1 anytime, write 0 if TG0EN and TG1EN is cleared

Access: User read/write(1)

1

0

0 PTULDOK

0

0

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Table 14-4. PTUC Register Field Descriptions

Field
0 PTULDOK

Description
Load Okay -- When this bit is set by the software, this allows the trigger generator to switch to the alternative list and load the trigger time values at the next reload event from the new list. If the reload event occurs when the PTULDOK bit is not set then the trigger generator generates a reload overrun event and uses the previously used list. At the next reload event this bit is cleared by control logic. Write 0 is only possible if TG0EN and TG1EN is cleared. The PTULDOK can be used by other module as global load OK (glb_ldok).

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14.3.2.3 PTU Interrupt Enable Register High (PTUIEH)
Module Base + 0x0002

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

PTUROIE

W

Reset

0

0

0

0

0

0

0

0

1. Read: Anytime Write: Anytime

= Unimplemented Figure 14-5. PTU Interrupt Enable Register High (PTUIEH)

Table 14-5. PTUIEH Register Field Descriptions

Field
0 PTUROIE

Description
PTU Reload Overrun Interrupt Enable -- Enables PTU reload overrun interrupt. 0 No interrupt will be requested whenever PTUROIF is set 1 Interrupt will be requested whenever PTUROIF is set

14.3.2.4 PTU Interrupt Enable Register Low (PTUIEL)
Module Base + 0x0003

Access: User read/write(1)

R W Reset

7
TG1AEIE 0

6
TG1REIE 0

5
TG1TEIE 0

4
TG1DIE 0

3
TG0AEIE

2
TG0REIE

1
TG0TEIE

0

0

0

0
TG0DIE 0

1. Read: Anytime Write: Anytime

= Unimplemented Figure 14-6. PTU Interrupt Enable Register Low (PTUIEL)

Field 7
TG1AEIE
6 TG1REIE

Table 14-6. PTUIEL Register Field Descriptions
Description
Trigger Generator 1 Memory Access Error Interrupt Enable -- Enables trigger generator memory access error interrupt. 0 No interrupt will be requested whenever TG1AEIF is set 1 Interrupt will be requested whenever TG1AEIF is set
Trigger Generator 1 Reload Error Interrupt Enable -- Enables trigger generator reload error interrupt. 0 No interrupt will be requested whenever TG1REIF is set 1 Interrupt will be requested whenever TG1REIF is set

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Table 14-6. PTUIEL Register Field Descriptions

Field 5
TG1TEIE
4 TG1DIE
3 TG0AEIE
2 TG0REIE
1 TG0TEIE
0 TG0DIE

Description
Trigger Generator 1 Timing Error Interrupt Enable -- Enables trigger generator timing error interrupt. 0 No interrupt will be requested whenever TG1TEIF is set 1 Interrupt will be requested whenever TG1TEIF is set
Trigger Generator 1 Done Interrupt Enable -- Enables trigger generator done interrupt. 0 No interrupt will be requested whenever TG1DIF is set 1 Interrupt will be requested whenever TG1DIF is set
Trigger Generator 0 Memory Access Error Interrupt Enable -- Enables trigger generator memory access error interrupt. 0 No interrupt will be requested whenever TG0AEIF is set 1 Interrupt will be requested whenever TG0AEIF is set
Trigger Generator 0 Reload Error Interrupt Enable -- Enables trigger generator reload error interrupt. 0 No interrupt will be requested whenever TG0REIF is set 1 Interrupt will be requested whenever TG0REIF is set
Trigger Generator 0 Timing Error Interrupt Enable -- Enables trigger generator timing error interrupt. 0 No interrupt will be requested whenever TG0TEIF is set 1 Interrupt will be requested whenever TG0TEIF is set
Trigger Generator 0 Done Interrupt Enable -- Enables trigger generator done interrupt. 0 No interrupt will be requested whenever TG0DIF is set 1 Interrupt will be requested whenever TG0DIF is set

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14.3.2.5 PTU Interrupt Flag Register High (PTUIFH)
Module Base + 0x0004

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

PTUDEEF PTUROIF

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented
Figure 14-7. PTU Interrupt Flag Register High (PTUIFH) 1. Read: Anytime
Write: Anytime, write 1 to clear

Table 14-7. PTUIFH Register Field Descriptions

Field 1
PTUDEEF
0 PTUROIF

Description
PTU Double bit ECC Error Flag -- This bit is set if the read data from the memory contains double bit ECC errors. While this bit is set the trigger generation of both trigger generators stops. 0 No double bit ECC error occurs 1 Double bit ECC error occurs
PTU Reload Overrun Interrupt Flag -- If reload event occurs when the PTULDOK bit is not set then this bit will be set. This bit is not set if the reload event was forced by an asynchronous commutation event. 0 No reload overrun occurs 1 Reload overrun occurs

14.3.2.6 PTU Interrupt Flag Register Low (PTUIFL)

Module Base + 0x0005

R W Reset

7
TG1AEIF 0

6
TG1REIF 0

5
TG1EIF 0

4
TG1DIF

3
TG0AEIF

2
TG0REIF

0

0

0

= Unimplemented
Figure 14-8. PTU Interrupt Flag Register Low (PTUIFL) 1. Read: Anytime
Write: Anytime, write 1 to clear

Access: User read/write(1)

1

0

TG0EIF

TG0DIF

0

0

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Table 14-8. PTUIFL Register Field Descriptions

Field 7
TG1AEIF
6 TG1REIF
5 TG1TEIF
4 TG1DIF
3 TG0AEIF
2 TG0REIF
1 TG0TEIF
0 TG0DIF

Description
Trigger Generator 1 Memory Access Error Interrupt Flag -- This bit is set if trigger generator 1 uses a read address outside the memory address range, see the MMC section for the supported memory area. 0 No trigger generator 1 memory access error occurs 1 Trigger generator 1 memory access error occurs
Trigger Generator 1 Reload Error Interrupt Flag -- This bit is set if a new reload event occurs when the trigger generator has neither reached the end of list symbol nor the maximum possible triggers. This bit is not set if the reload event was forced by an asynchronous commutation event. 0 No trigger generator 1 reload error occurs 1 Trigger generator 1 reload error occurs
Trigger Generator 1 Timing Error Interrupt Flag -- This bit is set if the trigger generator receives a time value which is below the current counter value. 0 No trigger generator 1 error occurs 1 Trigger generator 1 error occurs
Trigger Generator 1 Done Interrupt Flag --This bit is set if the trigger generator receives the end of list symbol or the maximum number of generated trigger events was reached. 0 Trigger generator 1 is running 1 Trigger generator 1 is done
Trigger Generator 0 Memory Access Error Interrupt Flag -- This bit is set if trigger generator 0 uses a read address outside the memory address range, see the MMC section for the supported memory area. 0 No trigger generator 0 memory access error occurred 1 Trigger generator 0 memory access error occurred
Trigger Generator 0 Reload Error Interrupt Flag -- This bit is set if a new reload event occurs when the trigger generator has neither reached the end of list symbol nor the maximum possible triggers. This bit is not set if the reload event was forced by an asynchronous commutation event. 0 No trigger generator 0 reload error occurs 1 Trigger generator 0 reload error occurs
Trigger Generator 0 Timing Error Interrupt Flag -- This bit is set if the trigger generator receives a time value which is below the current counter value. 0 No trigger generator 0 error occurs 1 Trigger generator 0 error occurs
Trigger Generator 0 Done Interrupt Flag --This bit is set if the trigger generator receives the end of list symbol or the maximum number of generated trigger events was reached. 0 Trigger generator 0 is running 1 Trigger generator 0 is done

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14.3.2.7 Trigger Generator 0 List Register (TG0LIST)
Module Base + 0x0006

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

TG0LIST

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented
Figure 14-9. Trigger Generator 0 List Register (TG0LIST) 1. Read: Anytime
Write: Anytime, if TG0EN bit is cleared

Field
0 TG0LIST

Table 14-9. TG0LIST Register Field Descriptions
Description
Trigger Generator 0 List -- This bit shows the number of the current used list. 0 Trigger generator 0 is using list 0 1 Trigger generator 0 is using list 1

14.3.2.8 Trigger Generator 0 Trigger Number Register (TG0TNUM)

Module Base + 0x0007

Access: User read only(1)

7

6

5

4

3

2

1

0

R

0

0

0

TG0TNUM[4:0]

W

Reset

0

0

0

0

0

0

0

0

1. Read: Anytime Write: Never

= Unimplemented Figure 14-10. Trigger Generator 0 Trigger Number Register (TG0TNUM)

Table 14-10. TG0TNUM Register Field Descriptions

Field

Description

4:0

Trigger Generator 0 Trigger Number -- This register shows the number of generated triggers since the last

TG0TNUM[4:0] reload event. After the generation of 32 triggers this register shows zero. The next reload event clears this

register. See also Figure 14-22.

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14.3.2.9 Trigger Generator 0 Trigger Value (TG0TVH, TG0TVL)

Module Base + 0x0008

Access: User read only(1)

7

6

5

4

3

2

1

0

R

TG0TV[15:8]

W

Reset

0

0

0

0

0

0

0

0

Module Base + 0x0009

Access: User read only

7

6

5

4

3

2

1

0

R

TG0TV[7:0]

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented
Figure 14-11. Trigger Generator 0 Trigger Value Register (TG0TVH, TG0TVL) 1. Read: Anytime
Write: Never

Table 14-11. TG0TV Register Field Descriptions

Field

Description

TG0TV[15:0]

Trigger Generator 0 Trigger Value -- This register contains the trigger value to generate the next trigger. If the time base counter reach this value the next trigger event is generated. If the trigger generator reached the end of list (EOL) symbol then this value is visible inside this register. If the last generated trigger was trigger number 32 then the last used trigger value is visible inside this register. See also Figure 14-22.

14.3.2.10 Trigger Generator 1 List Register (TG1LIST)
Module Base + 0x000A

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

TG1LIST

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented
Figure 14-12. Trigger Generator 1 List Register (TG1LIST) 1. Read: Anytime
Write: Anytime, if TG1EN bit is cleared

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Table 14-12. TG1LIST Register Field Descriptions
Description
Trigger Generator 1 List -- This bit shows the number of the current used list. 0 Trigger generator 1 is using list 0 1 Trigger generator 1 is using list 1

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14.3.2.11 Trigger Generator 1 Trigger Number Register (TG1TNUM)

Module Base + 0x000B

Access: User read only(1)

7

6

5

4

3

2

1

0

R

0

0

0

TG1TNUM[4:0]

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented

1. Read: Anytime Write: Never

Figure 14-13. Trigger Generator 1 Trigger Number Register (TG1TNUM)

Table 14-13. TG1TNUM Register Field Descriptions

Field

Description

4:0

Trigger Generator 1 Trigger Number -- This register shows the number of generated triggers since the last

TG1TNUM[4:0] reload event. After the generation of 32 triggers this register shows zero. The next reload event clears this

register. See also Figure 14-22.

14.3.2.12 Trigger Generator 1 Trigger Value (TG1TVH, TG1TVL)

Module Base + 0x000C

Access: User read only(1)

7

6

5

4

3

2

1

0

R

TG1TV[15:8]

W

Reset

0

0

0

0

0

0

0

0

Module Base + 0x000D

7

6

5

R

W

Reset

0

0

0

4

3

TG1TV[7:0]

0

0

Access: User read only

2

1

0

0

0

0

= Unimplemented
Figure 14-14. Trigger Generator 1 Trigger Value Register (TG1TVH, TG1TVL) 1. Read: Anytime
Write: Never

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Table 14-14. TG1TV Register Field Descriptions

Field

Description

TG1TV[15:0]

Trigger Generator 1 Next Trigger Value -- This register contains the currently used trigger value to generate the next trigger. If the time base counter reach this value the next trigger event is generated. If the trigger generator reached the end of list (EOL) symbol then this value is visible inside this register. If the last generated trigger was trigger number 32 then the last used trigger value is visible inside this register. See also Figure 1422.

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14.3.2.13 PTU Counter Register (PTUCNTH, PTUCNTL)
Module Base + 0x000E

Access: User read only(1)

7

6

5

R

W

Reset

0

0

0

Module Base + 0x000F

4

3

PTUCNT[15:8]

0

0

2

1

0

0

0

0

Access: User read only

7

6

5

4

3

2

1

0

R

PTUCNT[7:0]

W

Reset

0

0

0

0

0

0

0

0

1. Read: Anytime Write: Never

= Unimplemented Figure 14-15. PTU Counter Register (PTUCNTH, PTUCNTL)

Table 14-15. PTUCNT Register Field Descriptions

Field

Description

PTUCNT[15:0] PTU Time Base Counter value -- This register contains the current status of the internal time base counter. If both TG are done with the execution of the trigger list then the counter also stops. The counter is restarted by the next reload event.

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14.3.2.14 PTU Pointer Register (PTUPTRH, PTUPTRM, PTUPTRL)

Module Base + 0x0011

Access: User read/write(1)

7

6

5

4

3

2

1

0

R PTUPTR[23:16]
W

Reset

0

0

0

0

0

0

0

0

Module Base + 0x0012

7

6

5

R

W

Reset

0

0

0

4

3

PTUPTR[15:8]

0

0

Access: User read/write

2

1

0

0

0

0

Module Base + 0x0013

Access: User read/write

7

6

5

4

3

2

1

0

R

0

PTUPTR[7:1]

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented
Figure 14-16. PTU List Add Register (PTUPTRH, PTUPTRM, PTUPTRL) 1. Read: Anytime
Write: Anytime, if TG0En and TG1EN bit are cleared

Field
PTUPTR [23:0]

Table 14-16. PTUPTR Register Field Descriptions
Description
PTU Pointer -- This register cannot be modified if TG0EN or TG1EN bit is set. This register defines the start address of the used list area inside the global memory map. For more information see Section 14.4.2, "Memory based trigger event list".

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14.3.2.15 Trigger Generator 0 List 0 Index (TG0L0IDX)
Module Base + 0x0014

Access: User read only(1)

7

6

5

4

3

2

1

0

R

0

TG0L0IDX[6:0]

W

Reset

0

0

0

0

0

0

0

0

1. Read: Anytime Write: Never

= Unimplemented Figure 14-17. Trigger Generator 0 List 0 Index (TG0L0IDX)

Table 14-17. TG0L0IDX Register Field Descriptions

Field
6:0 TG0L0IDX
[6:0]

Description
Trigger Generator 0 List 0 Index Register -- This register defines offset of the start point for the trigger event list 0 used by trigger generator 0. This register is read only, so the list 0 for trigger generator 0 will start at the PTUPTR address. For more information see Section 14.4.2, "Memory based trigger event list".

14.3.2.16 Trigger Generator 0 List 1 Index (TG0L1IDX)

Module Base + 0x0015

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

W

TG0L1IDX[6:0]

Reset

0

0

0

0

0

0

0

0

= Unimplemented

Figure 14-18. Trigger Generator 0 List 1 Index (TG0L1IDX)
1. Read: Anytime Write: Anytime, if TG0EN bit is cleared

Table 14-18. TG0L1IDX Register Field Descriptions

Field
6:0 TG0L1IDX
[6:0]

Description
Trigger Generator 0 List 1 Index Register -- This register cannot be modified after the TG0EN bit is set. This register defines offset of the start point for the trigger event list 1 used by trigger generator 0. For more information see Section 14.4.2, "Memory based trigger event list".

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14.3.2.17 Trigger Generator 1 List 0 Index (TG1L0IDX)

Module Base + 0x0016

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

W

TG1L0IDX[6:0]

Reset

0

0

0

0

0

0

0

0

= Unimplemented

Figure 14-19. Trigger Generator 1 List 0 Index (TG1L0IDX)
1. Read: Anytime Write: Anytime, if TG1EN bit is cleared

Table 14-19. TG0L1IDX Register Field Descriptions

Field
6:0 TG1L0IDX
[6:0]

Description
Trigger Generator 1 List 0 Index Register -- This register cannot be modified after the TG1EN bit is set. This register defines offset of the start point for the trigger event list 0 used by trigger generator 1. For more information see Section 14.4.2, "Memory based trigger event list".

14.3.2.18 Trigger Generator 1 List 1 Index (TG1L1IDX)

Module Base + 0x0017

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

W

TG1L1IDX[6:0]

Reset

0

0

0

0

0

0

0

0

= Unimplemented

Figure 14-20. Trigger Generator 1 List 1 Index (TG1L1IDX)
1. Read: Anytime Write: Anytime, if TG1EN bit is cleared

Table 14-20. TG1L1IDX Register Field Descriptions

Field
6:0 TG1L1IDX
[6:0]

Description
Trigger Generator 1 List 1 Index Register -- This register cannot be modified after the TG1EN bit is set. This register defines offset of the start point for the trigger event list 1 used by trigger generator 1. For more information see Section 14.4.2, "Memory based trigger event list".

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14.3.2.19 PTU Debug Register (PTUDEBUG)

Module Base + 0x001F

Access: User read/write(1)

7

6

5

4

3

2

R

0

0

0

PTUREPE PTUT1PE PTUT0PE

W

PTUFRE

Reset

0

0

0

0

0

0

= Unimplemented

1. Read: Anytime Write: only in special mode

Figure 14-21. PTU Debug Register (PTUDEBUG)

1
0 TG1FTE
0

0
0 TG0FTE
0

Table 14-21. PTUDEBUG Register Field Descriptions

Field 6
PTUREPE
5 PTUT1PE
4 PTUT0PE
2 PTUFRE
1 TG1FTE
0 TG0FTE

Description
PTURE Pin Enable -- This bit enables the output port for pin PTURE. 0 PTURE output port are disabled 1 PTURE output port are enabled
PTU PTUT1 Pin Enable -- This bit enables the output port for pin PTUT1. 0 PTUT1 output port are disabled 1 PTUT1 output port are enabled
PTU PTUT0 Pin Enable -- This bit enables the output port for pin PTUT0. 0 PTUT0 output port are disabled 1 PTUT0 output port are enabled
Force Reload event generation -- If one of the TGs is enabled then writing 1 to this bit will generate a reload event. The reload event forced by PTUFRE does not set the PTUROIF interrupt flag. Also the ptu_reload signal asserts for one bus clock cyclet. Writing 0 to this bit has no effect. Always reads back as 0. This behavior is not available during stop or freeze mode.
Trigger Generator 1 Force Trigger Event -- If TG1 is enabled then writing 1 to this bit will generate a trigger event independent on the list based trigger generation. Writing 0 to this bit has no effect. Always reads back as 0.This behavior is not available during stop or freeze mode.
Trigger Generator 0 Force Trigger Event -- If TG0 is enabled then writing 1 to this bit will generate a trigger event independent on the list based trigger generation. Writing 0 to this bit has no effect. Always reads back as 0. This behavior is not available during stop or freeze mode.

14.4 Functional Description

14.4.1 General
The PTU module consists of two trigger generators (TG0 and TG1). For each TG a separate enable bit is available, so that both TGs can be enabled independently.
If both trigger generators are disabled then the PTU is disabled, the trigger generation stops and the memory accesses are disabled.

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The trigger generation of the PTU module is synchronized to the incoming reload event. This reload event resets and restarts the internal time base counter and makes sure that the first trigger value from the actual trigger list is loaded. Furthermore the corresponding module is informed that a new control cycle has started.
If the counter value matches the current trigger value then a trigger event is generated. In this way, the reload event is delayed by the number of bus clock cycles defined by the current trigger value. After this, a new trigger value is loaded from the memory and the TG waits for the next match. So up to 32 trigger events per control cycle can be generated. If the trigger value is 0x0000 or 32 trigger events have been generated during this control cycle, the TGxDIF bit is set and the TG waits for the next reload event. Figure 14-22 shows an example of the trigger generation using the trigger values shown in Figure 14-23.
Figure 14-22. TG0 trigger generation example
Control Cycle

reload event

Delay T0

Delay T2 Delay T1

reload event

t outgoing trigger events

PTUCNT

TG0LIST

TG0TV

T0

TG0TNUM

0

TG0DIF

T1

T2

0x0000

T0

1

2

3

0

NOTE
If the trigger list contains less than 32 trigger values a delay between the generation of the last trigger and the assertion of the done interrupt flag will be visible. During this time the PTU loads the next trigger value from the memory to evaluate the EOL symbol.

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14.4.2 Memory based trigger event list

The lists with the trigger values are located inside the global memory map. The location of the trigger lists in the memory map is configured with registers PTUPTR and TGxLxIDX. If one of the TGs is enabled then the PTUPTR register is locked. If the TG is enabled then the associated TGxLxIDX registers are locked.

The trigger values inside the trigger list are 16 bit values. Each 16 bit value defines the delay between the reload event and the trigger event in bus clock cycles. A delay value of 0x0000 will be interpreted as End Of trigger List (EOL) symbol. The list must be sorted in ascending order. If a subsequent value is smaller than the previous value or the loaded trigger value is smaller than the current counter value then the TGxTEIF error indication is generated and the trigger generation of this list is stopped until the next reload event. For more information about these error scenario see Section 14.4.5.5, "Trigger Generator Timing Error".

The module is not able to access memory area outside the 256 byte window starting at the memory address defined by PTUPTR.
Figure 14-23. Global Memory map usage

0x00_0000

Global Memory Map

PTUPTR + TG0L0IDX PTUPTR + TG0L1IDX PTUPTR + TG1L0IDX PTUPTR + TG1L1IDX

Delay T0 Delay T1 Delay T2 0x0000 (EOL symbol) unused Delay T0 Delay T1 Delay T2 0x0000 (EOL symbol) unused Delay T0 Delay T1 0x0000 (EOL symbol)
unused Delay T0 Delay T1 0x0000 (EOL symbol)
unused

start address TG0 trigger event list 0 start address TG0 trigger event list 1 start address TG1 trigger event list 0 start address TG1 trigger event list 1 max accessible memory area: 256 byte

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14.4.3 Reload mechanism
Each trigger generator uses two lists to load the trigger values from the memory. One list can be updated by the CPU while the other list is used to generate the trigger events. After enabling, the TG uses the lists in alternate order. When the update of alternate trigger list is done, the SW must set the PTULDOK bit. If the load OK bit is set at the time of reload event, the TG switches to the alternate list and loads the first trigger value from this trigger event list. The reload event clears the PTULDOK bit.
The TG0LIST and TG1LIST bits shows the currently use list number. These bits are writeable if the associated TG is disabled.
If the PTULDOK bit was not set before the reload event then the reload overrun error flag is set (PTUROIF)and both TGs do not switch to the alternative list. The current trigger list is used to load the trigger values. Figure 14-24 shows an example. The PTULDOK bit can be used by other modules as glb_ldok.
To reduce the used memory size, it is also possible to set TG0L0IDX equal to TG0L1IDX or to set TG1L0IDX equal to TG1L1IDX. In this case the trigger generator is using only one physical list of trigger events even if the trigger generator logic is switching between both pointers. The SW must make sure, that the CPU does not update the trigger list before the execution of the trigger list is done. The time window to update the trigger list starts at the trigger generator done interrupt flag (TGxDIF) and ends with the next reload event. Even if only one physical trigger event list is used the TGxLIST shows a swap between list 0 and 1 at every reload event with set PTULDOK bit.
Figure 14-24. TG0 Reload behavior with local PTULDOK

reload event

set by SW

PTULDOK bit was not set by CPU

PTULDOK

TG0LIST PTUROIF

switch to new list index

stay at current list index set reload overrun error flag

TG0DIF

TG0DIF

14.4.4 Async reload event
If the reload and reload_is_async are active at the same time then an async reload event happens. The PTU behavior on an async reload event is the same like on the reload event described in Section 14.4.3, "Reload

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mechanism" above. The only difference is, that during an async reload event the error interrupt flags PTUROIF and TGxREIF are not generated.

14.4.5 Interrupts and error handling
This section describes the interrupts generated by the PTU module and their individual sources, Vector addresses and interrupt priority are defined by MCU level.
Table 14-22. PTU Interrupt Sources

Module Interrupt Sources

Local Enable

PTU Reload Overrun Error TG0 Error TG1 Error TG0 Done TG1 Done

PTUIEH[PTUROIE] PTUIEL[TG0AEIE,TG0REIE,TG0TEIE] PTUIEL[TG1AEIE,TG1REIE,TG1TEIE] PTUIEL[TG0DIE] PTUIEL[TG1DIE]

14.4.5.1 PTU Double Bit ECC Error
If one trigger generator reads trigger values from the memory which contains double bit ECC errors then the PTUDEEF is set. These read data are ignored and the execution of both trigger generators is stopped until the PTUDEEF flag was cleared. To make sure the trigger generator starts in a define state it is required to execute follow sequence:
1. disable both trigger generators 2. configure the PTU if required 3. clear the PTUDEEF 4. enable the desired trigger generators

14.4.5.2 PTU Reload Overrun Error
If the PTULDOK bit is not set during the reload event then the PTUROIF bit is set. If enabled (PTUROIE is set) an interrupt is generated. For more information see Section 14.4.3, "Reload mechanism". During an async reload event the PTUROIF interrupt flag is not set.

14.4.5.3 Trigger Generator Memory Access Error
The trigger generator memory access error flag (TGxAEIF) is set if the used read address is outside the accessible memory address area; see the MMC section for the supported memory area. The loaded trigger values are ignored and the execution of this trigger list is stopped until the next reload event. If enabled (TGxAEIE is set) an interrupt will be generated.

14.4.5.4 Trigger Generator Reload Error
The trigger generator reload error flag (TGxREIF) is set if a new reload event occurs before the trigger generator reaches the EOL symbol or the maximum number of generated triggers. Independent of this

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error condition the trigger generator reloads the new data from the trigger list and starts to generate the trigger. During an async reload event the TGxREIF interrupt flag is not set.
If the trigger value loaded from the memory contains double bit ECC errors (PTUDEEF flag is set) then the data is ignored and the trigger generator reload error flag (TGxREIF) is not set.
14.4.5.5 Trigger Generator Timing Error
The PTU module requires a defined number of bus clock cycle to load the next trigger value from the memory. This load time defines the minimum possible distance between consecutive trigger values within one trigger list or the distance between the reload event and the first trigger value. If a smaller distance is used then it is possible, depending on device conditions, that the TGxTEIF event is generated. To evaluate the TGxTEIF handling a distance of 1 should be used. This value will generate the TGxTEIF condition independent from the device conditions.
For the specification of this number, please see the Device Overview chapter.
The trigger generator timing error flag (TGxTEIF) is set if the loaded trigger value is smaller than the current counter value. The execution of this trigger list is stopped until the next reload event. There are different reasons for the trigger generator error condition:
· reload time exceeds time of next trigger event · reload time exceeds the time between two consecutive trigger values · a subsequent trigger value is smaller than the predecessor trigger value
If the trigger value loaded from the memory contains double bit ECC errors (PTUDEEF flag is set) then the data are ignored and the trigger generator timing error flag (TGxTEIF) is not set.
If enabled (TGxEIE is set) an interrupt will be generated.
14.4.5.6 Trigger Generator Done
The trigger generator done flag (TGxDIF) is set if the loaded trigger value contains 0x0000 or if the number of maximum trigger events (32) was reached. Please note, that the time which is required to load the next trigger value defines the delay between the generation of the last trigger and the assertion of the done flag. If enabled (TGxDIE is set) an interrupt is generated.If the trigger value loaded from the memory contains double bit ECC errors (PTUDEEF flag is set) then the data are ignored and the trigger generator done flag (TGxDIF) is not set.
14.4.6 Debugging
To see the internal status of the trigger generator the register TGxLIST, TGxTNUM, and TGxTV can be used. The TGxLIST register shows the number of currently used list. The TGxTNUM shows the number of generated triggers since the last reload event. If the maximum number of triggers was generated then this register shows zero. The trigger value loaded from the memory to generate the next trigger event is visible inside the TGxTV register. If the execution of the trigger list is done then these registers are unchanged until the next reload event. The next PWM reload event clears the TGxTNUM register and toggles the used trigger list if PTULDOK was set.

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To generate a reload event or trigger event independent from the PWM status the debug register bits PTUFRE or TGxFTE can be used. A write one to this bits will generate the associated event.This behavior is not available during stop or freeze mode.

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Table 15-1. Revision History

Rev. No.

Date

(Item No.) (Submitted By)

Sections Affected

Substantial Change(s)

V03.22

02 Sep 2013 15.3.2.4/15-574 · Corrected PINVx bit descriptions 15.3.2.11/15-579 · Improved read description of PMFOUTB

V03.23

10 Oct 2013

15.2.8/15-565 15.3.2.18/15-585 15.3.2.22/15-589 15.8.1.1/15-629

· Corrected pmf_reload_is_async signal description · Enhanced note at PMFCINV register · Corrected write value limitations for PMFMODx registers · Corrected register write protection bit names · Orthographical corrections after review

V03.24

08 Nov 2013

15.3.2.8/15-577 Table 15-15 15.4.7/15-613

· Updated PMFFIF bit description · Updated note to QSMP table · Updated Asymmetric PWM output description · Replaced `fault clearing' with `fault recovery' to avoid ambiguity with flags · Various minor corrections. ·

V03.25 03 Dec 2013 15.3.2.18/15-585 · Updated note at PMFCINV register

V04.00 V04.1

03 Dec 2013 05 Nov 2015

15.3.2.3/15-573 · Added write protection to REV1-0 bits (WP) 15.3.2.11/15-579 · Added PWM read through PMFOUTB (generator output read option) 15.3.2.18/15-585 · Updated note at CINVn bits

Figure 15-51./15606
Figure 15-52./15607Figure 1553./15-607

· correct figure Figure 15-51./15-606, Figure 15-52./15-607,Figure 1553./15-607
· update DMPx register description

Glossary
Term Set Clear Pin Signal

Table 15-2. Glossary of Terms
Definition Discrete signal is in active logic state. A discrete signal is in inactive logic state. External physical connection. Electronic construct whose state or change in state conveys information.

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Table 15-2. Glossary of Terms

Term

Definition

PWM active state Normal output Positive polarity

PWM logic level high causing external power device to conduct

PWM inactive or disabled state Inverted output Negative polarity

PWM logic level low causing external power device not to conduct

PWM clock

Clock supplied to PWM and deadtime generators. Based on core clock. Rate depends on prescaler setting.

PWM cycle

PWM period determined by modulus register and PWM clock rate. Note the differences in edge- or centeraligned mode.

PWM reload cycle A.k.a. control cycle. Determined by load frequency which is 1 to n-times the PWM cycle. PWM reload cycle triggered double-buffered registers take effect at the next PWM reload event.

Commutation cycle For 6-step motor control only. Started by an event external to the PMF module (async_event). This may be a delayed Hall effect or back-EMF zero crossing event determining the rotor position. Commutation cycle triggered double-buffered registers take effect at the next commutation event and optionally the PWM counters are restarted.

Index x

Related to time bases. x = A, B or C

Index n

Related to PWM channels. n = 0, 1, 2, 3, 4, or 5

Index m

Related to fault inputs. m = 0, 1, 2, 3, 4, or 5

15.1

Introduction
NOTE
Device reference manuals specify which module version is integrated on the device. Some reference manuals support families of devices, with device dependent module versions. This chapter describes the superset. The feature differences are listed in Table 15-3.

Table 15-3. Comparison of PMF15B6C Module Versions

Feature
Write protection (WP) on REV1-0 bits
Ability to read the PWM output value through PMFOUTB register

V3 not available not available

V4 available available

The Pulse width Modulator with Fault protection (PMF) module can be configured for one, two, or three complementary pairs. For example:
· One complementary pair and four independent PWM outputs · Two complementary pairs and two independent PWM outputs

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· Three complementary pairs and zero independent PWM outputs · Zero complementary pairs and six independent PWM outputs
All PWM outputs can be generated from the same counter, or each pair can have its own counter for three independent PWM frequencies. Complementary operation permits programmable deadtime insertion, distortion correction through current sensing by software, and separate top and bottom output polarity control. Each counter value is programmable to support a continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width-control and full range modulation from 0 percent to 100 percent, are supported. The PMF is capable of controlling most motor types: AC induction motors (ACIM), both brushless (BLDC) and brush DC motors (BDC), switched (SRM) and variable reluctance motors (VRM), and stepper motors.
15.1.1 Features
· Three complementary PWM signal pairs, or six independent PWM signals · Edge-aligned or center-aligned mode · Features of complementary channel operation:
-- Deadtime insertion -- Separate top and bottom pulse width correction via current status inputs or software -- Three variants of PWM output:
­ Asymmetric in center-aligned mode ­ Variable edge placement in edge-aligned mode ­ Double switching in center-aligned mode · Three 15-bit counters based on core clock · Separate top and bottom polarity control · Half-cycle reload capability · Integral reload rates from 1 to 16 · Programmable fault protection · Link to timer output compare for 6-step BLDC commutation support with optional counter restart Reload overrun interrupt · PWM compare output polarity control Software-controlled PWM outputs, complementary or independent
15.1.2 Modes of Operation
Care must be exercised when using this module in the modes listed in Table 15-4. Some applications require regular software updates for proper operation. Failure to do so could result in destroying the hardware setup. Because of this, PWM outputs are placed in their inactive states in STOP mode, and optionally under WAIT and FREEZE modes. PWM outputs will be reactivated (assuming they were active to begin with) when these modes are exited.

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Mode STOP WAIT FREEZE

Table 15-4. Modes When PWM Operation is Restricted
Description PWM outputs are disabled PWM outputs are disabled as a function of the PMFWAI bit PWM outputs are disabled as a function of the PMFFRZ bit

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15.1.3 Block Diagram
Figure 15-1 provides an overview of the PMF module.

PRSC

CORE CLOCK
PRESCALER

PMFMOD REGISTERS
PMFVAL0-5 REGISTERS
PMFCNT REGISTERS

PWM GENERATORS
A,B,C

async_event with restart

Reset

MTG

MULTIPLE REGISTERS OR BITS FOR TIMEBASE A, B, OR C

Single-underline denotes buffered registers taking effect at PWM reload (pmf_reloada,b,c) Double-underline denotes buffered registers taking effect at commutation event (async_event)

pmf_reloada,b,c (PWM reload) pmf_reload_is_async (PWM reload qualifier)

PWMRF RSTRT EDGE HALF LDOK PWMEN LDFQ

IPOL INDEP OUT0 OUT2 OUT4 OUTCTL0 OUTCTL2 OUTCTL4

DT 0--5

OUT1 OUT3 OUT5 OUTCTL1 OUTCTL3 OUTCTL5

MUX, SWAP & CURRENT SENSE

DEADTIME INSERTION
TOP/BOTTOM GENERATION

6

async_event (Commutation Event)

OUTCTL0-5 OUTC0-5 MSK0-5

IS0 IS1 IS2 ISENS
PMFDMAP REGISTERS

FAULT PROTECTION

glb_ldok (Global load OK)
pmf_reloada,b,c (PWM reload)

PINVA,B,C PRSCA,B,C PECA,B,C PMFMODA,B,C PMFVAL0-5

PMFFEN REGISTER
FMOD0 FMOD1 FMOD2

FMOD3

FMOD4

PWMRF PWMRIE
FIE0-5 FIF0-5 PMFROIE

INTERRUPT CONTROL

RELOAD A INTERRUPT REQUEST RELOAD B INTERRUPT REQUEST RELOAD C INTERRUPT REQUEST
FAULT0-5 INTERRUPT REQUEST

FMOD5

FIF0 FIF1 FIF2 FIF3 FIF4

PMFROIF

RELOAD OVERRUN A or B or C INTERRUPT REQUEST

FIF5

PMFDTM REGISTER
TOPNEG BOTNEG

POLARITY CONTROL
FAULT PIN
FILTERS

PWM0 PWM1 PWM2 PWM3 PWM4 PWM5
FAULT0
FAULT1 FAULT2
FAULT3
FAULT4 FAULT5

QSMP0 QSMP1 QSMP2 QSMP3 QSMP4 QSMP5

Figure 15-1. PMF Block Diagram

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15.2 Signal Descriptions
If the signals are not used exclusively internally, the PMF has external pins named PWM0­5, FAULT0­5, and IS0­IS2. Refer to device overview section.
15.2.1 PWM0­PWM5 Pins
PWM0­PWM5 are the output signals of the six PWM channels. NOTE
On MCUs with an integrated gate drive unit the PWM outputs are connected internally to the GDU inputs. In these cases the PWM signals may optionally be available on pins for monitoring purposes. Refer to the device overview section for routing options and pin locations.
15.2.2 FAULT0­FAULT5 Pins
FAULT0­FAULT5 are input signals for disabling selected PWM outputs (FAULT0-3) or drive the outputs to a configurable active/inactive state (FAULT4-5).
NOTE On MCUs with an integrated gate drive unit (GDU) either one or more FAULT inputs may be connected internally or/and available on an external pin. Refer to the device overview section for availability and pin locations.
15.2.3 IS0­IS2 Pins
IS0­IS2 are current status signals for top/bottom pulse width correction in complementary channel operation while deadtime is asserted.
NOTE Refer to the device overview section for signal availability on pins.
15.2.4 Global Load OK Signal -- glb_ldok
This device-internal PMF input signal is connected to the global load OK bit at integration level. For each of the three PWM generator time bases the use of the global load OK input can be enabled individually (GLDOKA,B,C).
15.2.5 Commutation Event Signal -- async_event
This device-internal PMF input signal is connected to the source of the asynchronous event generator (preferably timer output compare channel) at integration level. The commutation event input must be enabled to take effect (ENCE=1). When this bit is set the PMFOUTC, PMFOUT, and MSKx registers switch from non-buffered to async_event triggered double

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Chapter 15 Pulse Width Modulator with Fault Protection (PMF15B6C00.17)
buffered mode. In addition, if restart is enabled (RSTRTx=1), the commutation event generates both "PWM reload event" and "PWM reload-is-asynchronous event" simultaneously.

15.2.6 Commutation Event Edge Select Signal -- async_event_edge_sel[1:0]
These device-internal PMF input signals select the active edge for the async_event input. Refer to the device overview section to determine if the selection is user configurable or tied constant at integration level.
Table 15-5. Commutation Event Edge Selection

async_event_edge-sel[1:0] 00 01 10 11

async_event active edge direct input rising edge falling edge both edges

15.2.7 PWM Reload Event Signals -- pmf_reloada,b,c
These device-internal PMF output signals assert once per control cycle and can serve as triggers for other implemented IP modules. Signal pmf_reloadb and pmf_reloadc are related to time base B and C, respectively, while signal pmf_reloada is off out of reset and can be programmed for time base A, B, or C. Refer to the device overview section to determine the signal connections.
15.2.8 PWM Reload-Is-Asynchronous Signal -- pmf_reload_is_async
This device-internal PMF output signal serves as a qualifier to the PMF reload event signal pmf_reloada. Whenever the async_event signal causes pmf_reloada output to assert also the pmf_reload_is_async output asserts for the same duration, except if asynchronous event and generated PWM reload event occur in the same cycle.

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15.3 Memory Map and Registers

15.3.1 Module Memory Map
A summary of the registers associated with the PMF module is shown in Figure 15-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level.

Address Offset
0x0000

Register Name
R PMFCFG0
W

Bit 7 WP

6

5

4

3

2

1

Bit 0

MTG

EDGEC EDGEB EDGEA INDEPC INDEPB INDEPA

R

0

0x0001 PMFCFG1

W

ENCE BOTNEGC TOPNEGC BOTNEGB TOPNEGB BOTNEGA TOPNEGA

0x0002

R PMFCFG2
W

REV1

REV0

MSK5

MSK4

MSK3

MSK2

MSK1

MSK0

R

0

0x0003 PMFCFG3

PMFWAI PMFFRZ

W

VLMODE

PINVC PINVB PINVA

R

0

0

0x0004 PMFFEN

FEN5

FEN4

FEN3

FEN2

FEN1

FEN0

W

R

0

0

0x0005 PMFFMOD

FMOD5

FMOD4 FMOD3 FMOD2 FMOD1 FMOD0

W

R

0

0

0x0006 PMFFIE

FIE5

FIE4

FIE3

FIE2

FIE1

FIE0

W

R

0

0

0x0007 PMFFIF

FIF5

FIF4

FIF3

FIF2

FIF1

FIF0

W

R

0

0

0

0

0x0008 PMFQSMP0

W

QSMP5

QSMP4

R 0x0009 PMFQSMP1
W

QSMP3

QSMP2

QSMP1

QSMP0

0x000A0x000B

R Reserved
W

0

0

0

0

0

0

0

0

= Unimplemented or Reserved Figure 15-2. Quick Reference to PMF Registers (Sheet 1 of 5)

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Address Register

Offset

Name

R 0x000C PMFOUTC
W

Bit 7 0

6

5

4

3

2

1

Bit 0

0 OUTCTL5 OUTCTL4 OUTCTL3 OUTCTL2 OUTCTL1 OUTCTL0

R

0

0x000D PMFOUTB

W

0

OUT5

OUT4

OUT3

OUT2

OUT1

OUT0

R

0

0x000E PMFDTMS

W

0

DT5

DT4

DT3

DT2

DT1

DT0

R

0

0

0x000F PMFCCTL

W

ISENS

0

IPOLC

IPOLB

IPOLA

0x0010

R PMFVAL0
W

PMFVAL0

0x0011

R PMFVAL0
W

PMFVAL0

0x0012

R PMFVAL1
W

PMFVAL1

0x0013

R PMFVAL1
W

PMFVAL1

0x0014

R PMFVAL2
W

PMFVAL2

0x0015

R PMFVAL2
W

PMFVAL2

0x0016

R PMFVAL3
W

PMFVAL3

0x0017

R PMFVAL3
W

PMFVAL3

0x0018

R PMFVAL4
W

PMFVAL4

0x0019

R PMFVAL4
W

PMFVAL4

0x001A

R PMFVAL5
W

PMFVAL5

= Unimplemented or Reserved Figure 15-2. Quick Reference to PMF Registers (Sheet 2 of 5)

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Address Register

Offset

Name

Bit 7

6

5

4

3

2

1

Bit 0

0x001B

R PMFVAL5
W

PMFVAL5

R

0

0x001C PMFROIE

W

0

0

0

0

PMFROIE PMFROIE PMFROIE

C

B

A

R

0

0x001D PMFROIF

W

0

0

0

0

PMFROIF PMFROIF PMFROIF

C

B

A

R

0

0x001E PMFICCTL

W

0

PECC

PECB

PECA

ICCC

ICCB

ICCA

R

0

0x001F PMFCINV

W

0

CINV5

CINV4

CINV3

CINV2

CINV1

CINV0

R

0

0

0

0x0020 PMFENCA

PWMENA GLDOKA

RSTRTA LDOKA PWMRIEA

W

R 0x0021 PMFFQCA
W

LDFQA

HALFA

PRSCA

PWMRFA

R

0

0x0022 PMFCNTA

W

PMFCNTA

0x0023

R PMFCNTA
W

PMFCNTA

R

0

0x0024 PMFMODA

W

PMFMODA

R 0x0025 PMFMODA
W

PMFMODA

R

0

0

0

0

0x0026 PMFDTMA

W

PMFDTMA

R 0x0027 PMFDTMA
W

PMFDTMA

R

0

0

0

0x0028 PMFENCB

PWMENB GLDOKB

RSTRTB LDOKB PWMRIEB

W

R 0x0029 PMFFQCB
W

LDFQB

HALFB

PRSCB

PWMRFB

= Unimplemented or Reserved Figure 15-2. Quick Reference to PMF Registers (Sheet 3 of 5)

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Address Register

Offset

Name

Bit 7

6

5

4

3

2

1

Bit 0

R

0

0x002A PMFCNTB

W

PMFCNTB

R 0x002B PMFCNTB
W

PMFCNTB

R

0

0x002C PMFMODB

W

PMFMODB

R 0x002D PMFMODB
W

PMFMODB

R

0

0

0

0

0x002E PMFDTMB

W

PMFDTMB

R 0x002F PMFDTMB
W

PMFDTMB

R

0

0

0

0x0030 PMFENCC

PWMENC GLDOKC

RSTRTC LDOKC PWMRIEC

W

R 0x0031 PMFFQCC
W

LDFQC

HALFC

PRSCC

PWMRFC

= Unimplemented or Reserved Figure 15-2. Quick Reference to PMF Registers (Sheet 4 of 5)

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Address Register

Offset

Name

Bit 7

6

5

4

3

2

1

R

0

0x0032 PMFCNTC

W

PMFCNTC

R 0x0033 PMFCNTC
W

PMFCNTC

R

0

0x0034 PMFMODC

W

PMFMODC

R 0x0035 PMFMODC
W

PMFMODC

R

0

0

0

0

0x0036 PMFDTMC

W

PMFDTMC

R 0x0037 PMFDTMC
W

PMFDTMC

R 0x0038 PMFDMP0
W

DMP05

DMP04

DMP03 DMP02 DMP01

R 0x0039 PMFDMP1
W

DMP15

DMP14

DMP13 DMP12 DMP11

R 0x003A PMFDMP2
W

DMP25

DMP24

DMP23 DMP22 DMP21

R 0x003B PMFDMP3
W

DMP35

DMP34

DMP33 DMP32 DMP31

R 0x003C PMFDMP4
W

DMP45

DMP44

DMP43 DMP42 DMP41

R 0x003D PMFDMP5
W

DMP55

DMP54

DMP53 DMP52 DMP51

R

0

0x003E PMFOUTF

W

0 OUTF5 OUTF4 OUTF3 OUTF2 OUTF1

R

0

0

0

0

0

0

0

0x003F Reserved

W

= Unimplemented or Reserved Figure 15-2. Quick Reference to PMF Registers (Sheet 5 of 5)

Bit 0
DMP00 DMP10 DMP20 DMP30 DMP40 DMP50 OUTF0
0

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15.3.2.1 PMF Configure 0 Register (PMFCFG0)

Address: Module Base + 0x0000

7

R W

WP

Reset

0

6
MTG 0

5
EDGEC 0

4
EDGEB 0

3
EDGEA 0

2
INDEPC 0

Figure 15-3. PMF Configure 0 Register (PMFCFG0)
1. Read: Anytime Write: This register cannot be modified after the WP bit is set

Access: User read/write(1)

1

0

INDEPB

INDEPA

0

0

Table 15-6. PMFCFG0 Field Descriptions

Field 7
WP
6 MTG
5 EDGEC
4 EDGEB
3 EDGEA
2 INDEPC

Description
Write Protect-- This bit enables write protection to be used for all write-protectable registers. While clear, WP allows write-protected registers to be written. When set, WP prevents any further writes to write-protected registers. Once set, WP can be cleared only by reset. 0 Write-protectable registers may be written 1 Write-protectable registers are write-protected
Multiple Timebase Generators -- This bit determines the number of timebase counters used. This bit cannot be modified after the WP bit is set. If MTG is set, PWM generators B and C and registers 0x0028 ­ 0x0037 are availabled.The three generators have their own variable frequencies and are not synchronized. If MTG is cleared, PMF registers from 0x0028 ­ 0x0037 can not be written and read zeroes, and bits EDGEC and EDGEB are ignored. Pair A, Pair B, and Pair C PWMs are synchronized to PWM generator A and use registers from 0x0020 ­ 0x0027. 0 Single timebase generator 1 Multiple timebase generators
Edge-Aligned or Center-Aligned PWM for Pair C -- This bit determines whether PWM4 and PWM5 channels will use edge-aligned or center-aligned waveforms. This bit has no effect if MTG bit is cleared. This bit cannot be modified after the WP bit is set. 0 PWM4 and PWM5 are center-aligned PWMs 1 PWM4 and PWM5 are edge-aligned PWMs
Edge-Aligned or Center-Aligned PWM for Pair B -- This bit determines whether PWM2 and PWM3 channels will use edge-aligned or center-aligned waveforms. This bit has no effect if MTG bit is cleared. This bit cannot be modified after the WP bit is set. 0 PWM2 and PWM3 are center-aligned PWMs 1 PWM2 and PWM3 are edge-aligned PWMs
Edge-Aligned or Center-Aligned PWM for Pair A-- This bit determines whether PWM0 and PWM1 channels will use edge-aligned or center-aligned waveforms. It determines waveforms for Pair B and Pair C if the MTG bit is cleared. This bit cannot be modified after the WP bit is set. 0 PWM0 and PWM1 are center-aligned PWMs 1 PWM0 and PWM1 are edge-aligned PWMs
Independent or Complementary Operation for Pair C-- This bit determines if the PWM channels 4 and 5 will be independent PWMs or complementary PWMs. This bit cannot be modified after the WP bit is set. 0 PWM4 and PWM5 are complementary PWM pair 1 PWM4 and PWM5 are independent PWMs

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Table 15-6. PMFCFG0 Field Descriptions (continued)

Field 1
INDEPB
0 INDEPA

Description
Independent or Complementary Operation for Pair B-- This bit determines if the PWM channels 2 and 3 will be independent PWMs or complementary PWMs. This bit cannot be modified after the WP bit is set. 0 PWM2 and PWM3 are complementary PWM pair 1 PWM2 and PWM3 are independent PWMs
Independent or Complementary Operation for Pair A-- This bit determines if the PWM channels 0 and 1 will be independent PWMs or complementary PWMs. This bit cannot be modified after the WP bit is set. 0 PWM0 and PWM1 are complementary PWM pair 1 PWM0 and PWM1 are independent PWMs

15.3.2.2 PMF Configure 1 Register (PMFCFG1)

Address: Module Base + 0x0001

7

R

0

W

Reset

0

6
ENCE 0

5
BOTNEGC

4
TOPNEGC

3
BOTNEGB

2
TOPNEGB

0

0

0

0

Figure 15-4. PMF Configure 1 Register (PMFCFG1)
1. Read: Anytime Write: This register cannot be modified after the WP bit is set

Access: User read/write(1)

1

0

BOTNEGA TOPNEGA

0

0

A normal PWM output or positive polarity means that the PWM channel outputs high when the counter value is smaller than or equal to the pulse width value and outputs low otherwise. An inverted output or negative polarity means that the PWM channel outputs low when the counter value is smaller than or equal to the pulse width value and outputs high otherwise.
NOTE
The TOPNEGx and BOTNEGx are intended for adapting to the polarity of external predrivers on devices driving the PWM output directly to pins. If an integrated GDU is driven it must be made sure to keep the reset values of these bits in order not to violate the deadtime insertion.

Table 15-7. PMFCFG1 Field Descriptions

Field

Description

6 ENCE

Enable Commutation Event -- This bit enables the commutation event input and activates buffering of registers PMFOUTC and PMFOUTB and MSKx bits.This bit cannot be modified after the WP bit is set.If set to zero the commutation event input is ignored and writes to the above registers and bits will take effect immediately. If set to one, the commutation event input is enabled and the value written to the above registers and bits does not take effect until the next commutation event occurs. 0 Commutation event input disabled and PMFOUTC, PMFOUTB and MSKn not buffered 1 Commutation event input enabled and PMFOUTC, PMFOUTB and MSKn buffered

5 BOTNEGC

Pair C Bottom-Side PWM Polarity -- This bit determines the polarity for Pair C bottom-side PWM (PWM5). This bit cannot be modified after the WP bit is set. 0 Positive PWM5 polarity 1 Negative PWM5 polarity

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Table 15-7. PMFCFG1 Field Descriptions (continued)

Field

Description

4 TOPNEGC

Pair C Top-Side PWM Polarity -- This bit determines the polarity for Pair C top-side PWM (PWM4). This bit cannot be modified after the WP bit is set. 0 Positive PWM4 polarity 1 Negative PWM4 polarity

3 BOTNEGB

Pair B Bottom-Side PWM Polarity -- This bit determines the polarity for Pair B bottom-side PWM (PWM3). This bit cannot be modified after the WP bit is set. 0 Positive PWM3 polarity 1 Negative PWM3 polarity

2 TOPNEGB

Pair B Top-Side PWM Polarity -- This bit determines the polarity for Pair B top-side PWM (PWM2). This bit cannot be modified after the WP bit is set. 0 Positive PWM2 polarity 1 Negative PWM2 polarity

1 BOTNEGA

Pair A Bottom-Side PWM Polarity -- This bit determines the polarity for Pair A bottom-side PWM (PWM1). This bit cannot be modified after the WP bit is set. 0 Positive PWM1 polarity 1 Negative PWM1 polarity

0 TOPNEGA

Pair A Top-Side PWM Polarity -- This bit determines the polarity for Pair A top-side PWM (PWM0). This bit cannot be modified after the WP bit is set. 0 Positive PWM0 polarity 1 Negative PWM0 polarity

15.3.2.3 PMF Configure 2 Register (PMFCFG2)

Address: Module Base + 0x0002

R W Reset

7
REV1 0

6
REV0 0

5
MSK5 0

4
MSK4 0

3
MSK3 0

2
MSK2 0

Figure 15-5. PMF Configure 2 Register (PMFCFG2) 1. Read: Anytime
Write: Anytime except REV[1:0] which cannot be modified after the WP bit is set1.

Access: User read/write(1)

1

0

MSK1

MSK0

0

0

Table 15-8. PMFCFG2 Field Descriptions

Field
7-6 REV[1:0]

Description
Select timebase counter to output reload event on pmf_reloada These bits select if timebase generator A, B or C provides the reload event on output signal pmf_reloada. This register cannot be modified after the WP bit is set.(1) 00 Reload event generation disabled 01 PWM generator A generates reload event 10 PWM generator B generates reload event 11 PWM generator C generates reload event

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Table 15-8. PMFCFG2 Field Descriptions (continued)

Field

Description

5­0 MSK[5:0]

Mask PWMn -- Note: MSKn are buffered if ENCE is set. The value written does not take effect until the next commutation cycle
begins. Reading MSKn returns the value in the buffer and not necessarily the value the output control is currently using.
0 PWMn is unmasked 1 PWMn is masked and the channel is set to a value of 0 percent duty cycle n is 0, 1, 2, 3, 4, and 5.

1. only valid for module version V4

WARNING
When using the TOPNEG/BOTNEG bits and the MSKn bits at the same time, when in complementary mode, it is possible to have both PMF channel outputs of a channel pair set to one.

15.3.2.4 PMF Configure 3 Register (PMFCFG3)

Address: Module Base + 0x0003

Access: User read/write(1)

7

6

5

R

0

PMFWAI PMFFRZ

W

Reset

0

0

0

4

3

VLMODE

0

0

2
PINVC 0

1
PINVB 0

0
PINVA 0

Figure 15-6. PMF Configure 3 Register (PMFCFG3)
1. Read: Anytime Write: This register cannot be modified after the WP bit is set, except for bits PINVA, PINVB and PINVC

Table 15-9. PMFCFG3 Field Descriptions

Field 7
PMFWAI
6 PMFFRZ

Description
PMF Stops While in WAIT Mode -- When set to zero, the PWM generators will continue to run while the chip is in WAIT mode. In this mode, the peripheral clock continues to run but the CPU clock does not. If the device enters WAIT mode and this bit is one, then the PWM outputs will be switched to their inactive state until WAIT mode is exited. At that point the PWM outputs will resume operation as programmed in the PWM registers. This bit cannot be modified after the WP bit is set. 0 PMF continues to run in WAIT mode 1 PMF is disabled in WAIT mode
PMF Stops While in FREEZE Mode -- When set to zero, the PWM generators will continue to run while the chip is in FREEZE mode. If the device enters FREEZE mode and this bit is one, then the PWM outputs will be switched to their inactive state until FREEZE mode is exited. At that point the PWM outputs will resume operation as programmed in the PWM registers. This bit cannot be modified after the WP bit is set. 0 PMF continues to run in FREEZE mode 1 PMF is disabled in FREEZE mode

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Table 15-9. PMFCFG3 Field Descriptions (continued)

Field

Description

4­3 VLMODE
[1:0]
2 PINVC
1 PINVB
0 PINVA

Value Register Load Mode -- This field determines the way the value registers are being loaded. This register cannot be modified after the WP bit is set. 00 Each value register is accessed independently 01 Writing to value register zero also writes to value registers one to five 10 Writing to value register zero also writes to value registers one to three 11 Reserved (defaults to independent access)
PWM Invert Complement Source Pair C -- This bit controls PWM4/PWM5 pair. When set, this bit inverts the COMPSRCC signal. This bit has no effect in independent mode. Note: PINVC is buffered. The value written does not take effect until the LDOK bit or global load OK is set and
the next PWM load cycle begins. Reading PINVC returns the value in the buffer and not necessarily the value in use.
0 No inversion 1 COMPSRCC inverted only in complementary mode
PWM Invert Complement Source Pair B -- This bit controls PWM2/PWM3 pair. When set, this bit inverts the COMPSRCB signal. This bit has no effect in independent mode. Note: PINVB is buffered. The value written does not take effect until the LDOK bit or global load OK is set and
the next PWM load cycle begins. Reading PINVB returns the value in the buffer and not necessarily the value in use.
0 No inversion 1 COMPSRCB inverted only in complementary mode
PWM Invert Complement Source Pair A -- This bit controls PWM0/PWM1 pair. When set, this bit inverts the COMPSRCA signal. This bit has no effect on in independent mode. Note: PINVA is buffered. The value written does not take effect until the LDOKA bit or global load OK is set and
the next PWM load cycle begins. Reading PINVA returns the value in the buffer and not necessarily the value in use.
0 No inversion 1 COMPSRCA inverted only in complementary mode

15.3.2.5 PMF Fault Enable Register (PMFFEN)

Address: Module Base + 0x0004

7

6

5

4

3

2

R

0

0

FEN5

FEN4

FEN3

FEN2

W

Reset

0

0

0

0

0

0

Figure 15-7. PMF Fault Enable Register (PMFFEN)
1. Read: Anytime Write: This register cannot be modified after the WP bit is set

Access: User read/write(1)

1

0

FEN1

FEN0

0

0

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Table 15-10. PMFFEN Field Descriptions

Field
6,4-0 FEN[5:0]

Description
Fault m Enable -- This register cannot be modified after the WP bit is set. 0 FAULTm input is disabled 1 FAULTm input is enabled for fault protection m is 0, 1, 2, 3, 4 and 5

15.3.2.6 PMF Fault Mode Register (PMFFMOD)

Address: Module Base + 0x0005

7

6

5

4

3

2

R

0

0

FMOD5

FMOD4

FMOD3

FMOD2

W

Reset

0

0

0

0

0

0

1. Read: Anytime Write: Anytime

Figure 15-8. PMF Fault Mode Register (PMFFMOD)

Access: User read/write(1)

1

0

FMOD1

FMOD0

0

0

Table 15-11. PMFFMOD Field Descriptions

Field

Description

6,4-0 FMOD[5:0]

Fault m Pin Recovery Mode -- This bit selects automatic or manual recovery of FAULTm input faults. See Section 15.4.13.2, "Automatic Fault Recovery" and Section 15.4.13.3, "Manual Fault Recovery" for more details. 0 Manual fault recovery of FAULTm input faults 1 Automatic fault recovery of FAULTm input faults m is 0, 1, 2, 3, 4 and 5.

15.3.2.7 PMF Fault Interrupt Enable Register (PMFFIE)

Address: Module Base + 0x0006

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

W

FIE5

0

FIE4

FIE3

FIE2

FIE1

FIE0

Reset

0

0

0

0

0

0

0

0

1. Read: Anytime Write: Anytime

Figure 15-9. PMF Fault Interrupt Enable Register (PMFFIE)

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Chapter 15 Pulse Width Modulator with Fault Protection (PMF15B6C00.17)

Field
6,4-0 FIE[5:0]

Table 15-12. PMFFIE Field Descriptions
Description
Fault m Pin Interrupt Enable -- This bit enables CPU interrupt requests to be generated by the FAULTm input. The fault protection circuit is independent of the FIEm bit and is active when FENm is set. If a fault is detected, the PWM outputs are disabled or switched to output control according to the PMF Disable Mapping registers. 0 FAULTm CPU interrupt requests disabled 1 FAULTm CPU interrupt requests enabled m is 0, 1, 2, 3, 4 and 5.

15.3.2.8 PMF Fault Interrupt Flag Register (PMFFIF)

Address: Module Base + 0x0007

7

6

5

4

3

2

R

0

W

FIF5

0

FIF4

FIF3

FIF2

Reset

0

0

0

0

0

0

Figure 15-10. PMF Fault Interrupt Flag Register (PMFFIF) 1. Read: Anytime
Write: Anytime. Write 1 to clear.

Access: User read/write(1)

1

0

FIF1

FIF0

0

0

Table 15-13. PMFFIF Field Descriptions

Field

Description

6,4-0 FIF[5:0]

Fault m Interrupt Flag -- This flag is set after the required number of samples have been detected after an edge to the active level(1) on the FAULTm input. Writing a logic one to FIFm clears it. Writing a logic zero has no effect. If a set flag is attempted to be cleared and a flag setting event occurs in the same cycle, then the flag remains set. The fault protection is enabled when FENm is set even when the PWMs are not enabled; therefore, a fault will be latched in, requiring to be cleared in order to prevent an interrupt. 0 No fault on the FAULTm input 1 Fault on the FAULTm input Note: Clearing FIFm satisfies pending FIFm CPU interrupt requests.
m is 0, 1, 2, 3, 4 and 5.

1. The active input level may be defined or programmable at SoC level. The default for internally connected resources is activehigh. For availability and configurability of fault inputs on pins refer to the device overview section.

15.3.2.9 PMF Fault Qualifying Samples Register 0-1 (PMFQSMP0-1)

Address: Module Base + 0x0008

Access: User read/write(1)

7

6

5

4

3

2

1

0

R

0

0

0

0

W

QSMP5

QSMP4

Reset

0

0

0

0

0

0

0

0

Figure 15-11. PMF Fault Qualifying Samples Register (PMFQSMP0)

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1. Read: Anytime Write: This register cannot be modified after the WP bit is set.

Address: Module Base + 0x0009

Access: User read/write(1)

R W Reset

7

6

QSMP3

0

0

5

4

QSMP2

0

0

3

2

QSMP1

0

0

1

0

QSMP0

0

0

Figure 15-12. PMF Fault Qualifying Samples Register (PMFQSMP1)
1. Read: Anytime Write: This register cannot be modified after the WP bit is set.

Table 15-14. PMFQSMP0-1 Field Descriptions

Field

Description

7­0

Fault m Qualifying Samples -- This field indicates the number of consecutive samples taken at the FAULTm

QSMPm[1:0] input to determine if a fault is detected. The first sample is qualified after two bus cycles from the time the fault

is present and each sample after that is taken every four core clock cycles. See Table 15-15. This register cannot

be modified after the WP bit is set.

m is 0, 1, 2, 3, 4 and 5.

Table 15-15. Qualifying Samples

QSMPm[1:0] 00

Number of Samples 1 sample(1)

01

5 samples

10

10 samples

11

15 samples

1. There is an asynchronous path from fault inputs FAULT3-0, FAULT4 if DMPn4=b10, and FAULT5 if DMPn5=b10 to disable PWMs immediately but the fault is qualified in two bus cycles.

15.3.2.10 PMF Output Control Register (PMFOUTC)

Address: Module Base + 0x000C

7

R

0

W

Reset

0

6

5

4

3

2

0 OUTCTL5 OUTCTL4 OUTCTL3 OUTCTL2

0

0

0

0

0

1. Read: Anytime Write: Anytime

Figure 15-13. PMF Output Control Register (PMFOUTC)

Access: User read/write(1)

1

0

OUTCTL1 OUTCTL0

0

0

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Table 15-16. PMFOUTC Field Descriptions

Field

Description

5­0

OUTCTLn Bits -- These bits enable software control of their corresponding PWM output. When OUTCTLn is

OUTCTL[5:0] set, the OUTn bit takes over the directly controls the level of the PWMn output.

Note: OUTCTLn is buffered if ENCE is set. If ENCE is set, then the value written does not take effect until the

next commutation cycle begins. Reading OUTCTLn returns the value in the buffer and not necessarily the

value the output control is currently using.If ENCE is not set, then the OUTn bits take immediately effect

when OUTCTLn bit is set. If the OUTCTLn bit is cleared then the OUTn control is disabled at the next

PMF cycle start.

When operating the PWM in complementary mode, these bits must be switched in pairs for proper operation. That is OUTCTL0 and OUTCTL1 must have the same value; OUTCTL2 and OUTCTL3 must have the same value; and OUTCTL4 and OUTCTL5 must have the same value. Otherwise see the behavior described on chapter Section 15.8.2, "BLDC 6-Step Commutation". 0 Software control disabled 1 Software control enabled n is 0, 1, 2, 3, 4 and 5.

15.3.2.11 PMF Output Control Bit Register (PMFOUTB)

Address: Module Base + 0x000D

Access: User read/write(1)

7

R

0

W

Reset

0

6

5

4

3

2

1

0

0

OUT5

OUT4

OUT3

OUT2

OUT1

OUT0

0

0

0

0

0

0

0

1. Read: Anytime Write: Anytime

Figure 15-14. PMF Output Control Bit Register (PMFOUTB)

a

Table 15-17. PMFOUTB Field Descriptions

Field

Description

5­0 OUT[5:0]

OUTn Bits -- If the corresponding OUTCTLn bit is set, these bits control the PWM outputs, illustrated in Table 15-18. If the related OUTCTLn=1 a read returns the register contents OUTn else the current PWM output states are returned(1) On module version V3 the read returns always the register value. Note: OUTn is buffered if ENCE is set. The value written does not take effect until the next commutation cycle
begins. Reading OUTn (with OUTCTLn=1) returns the value in the buffer and not necessarily the value the output control is currently using.
n is 0, 1, 2, 3, 4 and 5.

1. only valid for module version V4

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OUTn Bit OUT0 OUT1 OUT2 OUT3 OUT4 OUT5

Table 15-18. Software Output Control

Complementary Channel Operation
1 -- PWM0 is active 0 -- PWM0 is inactive
1 -- PWM1 is complement of PWM0 0 -- PWM1 is inactive
1 -- PWM2 is active 0 -- PWM2 is inactive
1 -- PWM3 is complement of PWM2 0 -- PWM3 is inactive
1 -- PWM4 is active 0 -- PWM4 is inactive
1 -- PWM5 is complement of PWM4 0 -- PWM5 is inactive

Independent Channel Operation
1 -- PWM0 is active 0 -- PWM0 is inactive
1 -- PWM1 is active 0 -- PWM1 is inactive
1 -- PWM2 is active 0 -- PWM2 is inactive
1 -- PWM3 is active 0 -- PWM3 is inactive
1 -- PWM4 is active 0 -- PWM4 is inactive
1 -- PWM5 is active 0 -- PWM5 is inactive

15.3.2.12 PMF Deadtime Sample Register (PMFDTMS)

Address: Module Base + 0x000E

Access: User read/write(1)

7

R

0

W

Reset

0

6

5

4

3

2

1

0

0

DT5

DT4

DT3

DT2

DT1

DT0

0

0

0

0

0

0

0

1. Read: Anytime Write: Never

Figure 15-15. PMF Deadtime Sample Register (PMFDTMS)