LC717A00AJ - Capacitance‐Digital‐Converter LSI for Electrostatic Capacitive Touch Sensors

The LC717A00AJ is a high‐performance, low‐cost capacitance‐digital‐converter LSI for electrostatic capacitive touch sensor, especially focused on usability. It has 8 channels capacitance‐sensor input. The built‐in logic circuit can detect the state (ON/OFF) of each input and output the result. This makes it ideal for various switch applications. The calibration function is automatically performed by the built‐in logic circuit during power activation or whenever there are environmental changes. In addition,

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LC717A00AJ

Capacitance-Digital-Converter LSI for Electrostatic Capacitive Touch Sensors

Overview The LC717A00AJ is a high-performance, low-cost capacitance-
digital-converter LSI for electrostatic capacitive touch sensor, especially focused on usability. It has 8 channels capacitance-sensor input. The built-in logic circuit can detect the state (ON/OFF) of each input and output the result. This makes it ideal for various switch applications.
The calibration function is automatically performed by the built-in logic circuit during power activation or whenever there are environmental changes. In addition, since initial settings of parameters, such as gain, are configured, LC717A00AJ can operate as stand-alone when the recommended switch pattern is applied.
Also, since LC717A00AJ has a serial interface compatible with I2Ct and SPI bus, parameters can be adjusted using external devices whenever necessary. Moreover, outputs of the 8-input capacitance data can be detected and measured as 8-bit data.
Features
· Detection System: Differential Capacitance Detection
(Mutual Capacitance Type)
· Input Capacitance Resolution: Can Detect Capacitance Changes in
the Femto Farad Order
· Measurement Interval (8 Differential Inputs):
18 ms (Typ) (at Initial Configuration) 3 ms (Typ) (at Minimum Interval Configuration)
· External Components for Measurement: Not Required · Current Consumption:
320 mA (Typ) (VDD = 2.8 V) 740 mA (Typ) (VDD = 5.5 V)
· Supply Voltage: 2.6 V to 5.5 V · Detection Operations: Switch · Interface: I2C Compatible Bus or SPI Selectable

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SSOP30 (225 mil) CASE 565AZ
MARKING DIAGRAM
XXXXXXXXXX YMDDD
XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of this data sheet.

October, 2017 - Rev. 1

Publication Order Number: LC717A00AJ/D

LC717A00AJ

Specifications

Table 1. ABSOLUTE MAXIMUM RATINGS (TA = 25°C, VSS = 0 V)

Parameter

Symbol

Ratings

Unit

Remarks

Supply Voltage

VDD

-0.3 to +6.5

Input Voltage

VIN

-0.3 to VDD + 0.3

V (Note 1)

Output Voltage

VOUT

-0.3 to VDD + 0.3

V (Note 2)

Power Dissipation

Pd max

160

mW TA = +105_C, Mounted on a substrate (Note 3)

Peak Output Current

IOP

±8

mA Per terminal, 50% Duty ratio (Note 2)

Total Output Current

IOA

±40

mA Output total value of LSI, 25% Duty ratio

Storage Temperature

Tstg

-55 to +125

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Apply to Cin0 to 7, Cref, nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN. 2. Apply to Cdrv, Pout0 to 7, SDA, SO, ERROR, INTOUT. 3. Single-layer glass epoxy board (76.1 × 114.3 × 1.6t mm).

Table 2. RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Remarks

Operating Supply Voltage

VDD

2.6

5.5

Supply Ripple + Noise

VPP

±20

(Note 4)

Operating Temperature

Topr

-40

105

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended. In this case, the small-valued capacitor should be at least 0.1 mF, and is mounted near the LSI.

Table 3. ELECTRICAL CHARACTERISTICS (VSS = 0 V, VDD = 2.6 to 5.5 V, TA = -40 to +105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143 kHz. Not tested at low temperature before shipment.)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Remarks

Capacitance Detection Resolution

bit

Output Noise RMS
Input Offset Capacitance Adjustment Range

NRMS Minimum gain setting

CoffRANGE

±1.0

LSB

(Notes 5, 7)

±8.0

(Notes 5, 7)

Input Offset Capacitance Adjustment Resolution

CoffRESO

bit

Cin Offset Drift
Cin Detection Sensitivity
Cin Pin Leak Current
Cin Allowable Parasitic Input Capacitance

CinDRIFT Minimum gain setting

±8

LSB

(Note 5)

CinSENSE Minimum gain setting 0.04

0.12

LSB/fF

(Note 6)

ICin

Cin = Hi-Z

±25

±500

CinSUB

Cin against VSS

(Notes 5, 7)

Cdrv Drive Frequency Cdrv Pin Leak Current nRST Minimum Pulse Width Power-on Reset Time Power-on Reset Operation Condition: Hold Time

fCDRV ICDRV tNRST tPOR tPOROP

Cdrv = Hi-Z

100

143

186

kHz

±25

±500

(Note 5)

Power-on Reset Operation Condition: Input Voltage

VPOROP

0.1

(Note 5)

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LC717A00AJ

Table 3. ELECTRICAL CHARACTERISTICS (continued) (VSS = 0 V, VDD = 2.6 to 5.5 V, TA = -40 to +105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143 kHz. Not tested at low temperature before shipment.)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Remarks

Power-on Reset Operation Condition: Power Supply Rise Rate

tVDD

0 V to VDD

V/ms

(Note 5)

Pin Input Voltage

VIH

High input

0.8 VDD

(Notes 5, 8)

VIL

Low input

0.2 VDD

Pin Output Voltage

VOH

High output

0.8 VDD

(Note 9)

(IOH = +3 mA)

VOL

Low output

0.2 VDD

(IOL = -3 mA)

SDA Pin Output Voltage

VOL I2C

SDA Low output

(IOL = -3 mA)

0.4

Pin Leak Current

ILEAK

±1

(Note 10)

Current Consumption

IDD

When stand-alone

configuration and

non-touch

VDD = 2.8 V

320

390

(Notes 5, 7)

When stand-alone

configuration and

non-touch

VDD = 5.5 V

740

900

ISTBY

During Sleep process

(Note 7)

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Design-guaranteed values (not tested before shipment). 6. Measurements conducted using the test mode in the LSI. 7. TA = +25_C. 8. Apply to nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN. 9. Apply to Cdrv, Pout0 to 7, SO, ERROR, INTOUT. 10. Apply to nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN.

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LC717A00AJ

Table 4. I2C COMPATIBLE BUS TIMING CHARACTERISTICS (VSS = 0 V, VDD = 2.6 to 5.5 V, TA = -40 to +105°C, Not tested at low temperature before shipment.)

Parameter

Symbol Pin Name Conditions Min

Typ

Max Unit Remarks

SCL Clock Frequency

fSCL

SCL

400

kHz

START Condition Hold Time
SCL Clock Low Period SCL Clock High Period Repeated START Condition Setup Time

tHD;STA tLOW tHIGH
tSU;STA

SCL, SDA SCL SCL
SCL, SDA

0.6

1.3

0.6

(Note 11)

Data Hold Time Data Setup Time

tHD;DAT tSU;DAT

SCL, SDA SCL, SDA

0.9

100

(Note 11)

SDA, SCL Rise/Fall Time STOP Condition Setup Time

tr / tf tSU;STO

SCL, SDA SCL, SDA

300

(Note 11)

0.6

STOP-to-START Bus Release Time

tBUF

SCL, SDA

1.3

(Note 11)

Table 5. SPI BUS TIMING CHARACTERISTICS (VSS = 0 V, VDD = 2.6 to 5.5 V, TA = -40 to +105°C, Not tested at low temperature before shipment.)

Parameter

Symbol Pin Name Conditions Min

Typ

Max Unit Remarks

SCK Clock Frequency

fSCK

SCK

MHz

SCK Clock Low Time SCK Clock High Time Input Signal Rise/Fall Time nCS Setup Time

tLOW tHIGH tr / tf tSU;NCS

SCK SCK nCS, SCK, SI nCS, SCK

(Note 12)

300

(Note 12)

SCK Clock Setup Time

tSU;SCK

nCS, SCK

(Note 12)

Data Setup Time Data Hold Time nCS Hold Time SCK Clock Hold Time

tSU;SI tHD;SI tHD;NCS tHD;SCK

SCK, SI SCK, SI nCS, SCK nCS, SCK

(Note 12)

nCS Standby Pulse Width
Output High Impedance Time from nCS

tCPH tCHZ

nCS nCS, SO

(Note 12)

Output Data Determination Time Output Data Hold Time

tv tHD;SO

SCK, SO SCK, SO

(Note 12)

Output Low Impedance Time from SCK Clock

tCLZ

SCK, SO

(Note 12)

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LC717A00AJ

Power-On Reset (POR) When power is turned on, power-on reset is enabled inside
the LSI and its state is released after a certain power-on reset time, tPOR. Power-on reset operation condition: Power supply rise rate tVDD must be at least 1 V/ms.

Since INTOUT pin changes from "High" to "Low" at the same time as the released of power-on reset state, it is possible to verify the tPOR externally.
During power-on reset state, Cin, Cref and Pout are unknown.

VDD
POR (LSI Internal
Signal)

tVDD tPOR

RESET

RELEASE

VPOROP

tPOROP

tPOR

UNKNOWN RESET

RELEASE

INTOUT

VALID UNKNOWN

Cin, Cref, Pout

UNKNOWN

VALID

UNKNOWN

I2C Compatible Bus Data Timing

Figure 1.

90%

SDA

10%

SCL

tLOW

tHD;DAT tSU;DAT

90% 90%

90%

10% 10%

10%

tHIGH

10%

tHD;STA

START condition

tSU;STA 90%

90% 10%
tHD;STA 90%

Repeated START condition

Figure 2.

I2C Compatible Bus Communication Formats
· Write format (data can be written into sequentially incremented addresses)

90% 10% tSU;STO

tBUF

90% 10%

90%

STOP START condition condition

START

Slave Address

Write=L ACK Slave

ACK Data written to Register Address (N) ACK Data written to Register Address (N+1) ACK STOP

Slave

Figure 3.

· Read format (data can be read from sequentially incremented addresses)

START

Slave Address

RESTART

Slave Address

Write=L ACK Slave

ACK Slave

Read=H ACK Data read from Register Address (N) ACK Data read from Register Address (N+1) ACK Data read from Register Address (N+2) NACK STOP

Slave

Master

Figure 4.

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LC717A00AJ

I2C Compatible Bus Slave Address Selection of two kinds of addresses is possible through the SA terminal.

Table 6. SA Pin Input Low
High

7-bit Slave Address 0x16
0x17

Binary Notation 00101100b (Write) 00101101b (Read) 00101110b (Write) 00101111b (Read)

8-bit Slave Address 0x2C 0x2D 0x2E 0x2F

SPI Data Timing (SPI Mode 0 / Mode 3)

nCS

tSU;SCK tSU;NCS tHIGH tLOW

tCPH

tf tHD;NCS tHD;SCK

SCK SI

tSU;SI tHD;SI VALID

SO Hi-Z

tCLZ
tV Figure 5.

tHD;SO VALID

tCHZ

SPI Communication Formats (Example of Mode 0)
· Write format (data can be written into sequentially incremented addresses while holding nCS = L)

nCS SCK
SI SO

Write=L 765432107654321076543210

Data written to Register Address(N)
Figure 6.

Data written to Register Address(N+1)

· Read format (data can be read from sequentially incremented addresses while holding nCS = L)

nCS SCK
SI SO

Read=H 76543210

Hi-Z

76543210765432107

Data read from Register Address(N)
Figure 7.

Data read from Register Address(N+1)

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Block Diagram

LC717A00AJ

Cref
Cin0 Cin1 Cin2 Cin3 Cin4 Cin5 Cin6 Cin7

MUX

+
1st AMP -

nCS SCL/SCK
SDA/SI SA/SO

I2C/SPI

+
2nd AMP -

A/D CONVERTER

CONTROL LOGIC

POR

OSCILLATOR

Pout0 Pout1 Pout2 Pout3 Pout4 Pout5 Pout6 Pout7 Cdrv
ERROR INTOUT nRST GAIN
VDD V SS

Figure 8. Simplified Block Diagram

LC717A00AJ is capacitance-digital-converter LSI capable of detecting changes in capacitance in the femto Farad order. It consists of an oscillation circuit that generates the system clock, a power-on reset circuit that resets the system when the power is turned on, a multiplexer that selects the input channels, a two-stage amplifier that detects

the changes in the capacitance and outputs analog-amplitude values, a A/D converter that converts the analog-amplitude values into digital data, and a control logic that controls the entire chip. Also, it has an I2C compatible bus or SPI that enables serial communication with external devices as necessary.

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Pin Assignment

LC717A00AJ

Cin3 Cin2 Cin1 Cin0 Non Connect nRST nCS SA/SO SDA/SI SCL/SCK GAIN INTOUT Cdrv ERROR Cref

VDD VSS Non Connect Cin4 Cin5 Cin6 Cin7 Pout0 Pout1 Pout2 Pout3 Pout4 Pout5 Pout6 Pout7

Figure 9. Pin Assignment (Top View)

Table 7. PIN ASSIGNMENT Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
13. Connect to GND when mounted.

Pin Name VDD VSS
Non Connect (Note 13) Cin4 Cin5 Cin6 Cin7 Pout0 Pout1 Pout2 Pout3 Pout4 Pout5 Pout6 Pout7

Pin No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Pin Name Cref
ERROR Cdrv
INTOUT GAIN
SCL/SCK SDA/SI SA/SO nCS nRST
Non Connect (Note 13) Cin0 Cin1 Cin2 Cin3

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Table 8. PIN FUNCTION

Pin Name

I/O

Cin0

I/O

Cin1

I/O

Cin2

I/O

Cin3

I/O

Cin4

I/O

Cin5

I/O

Cin6

I/O

Cin7

I/O

Cref

I/O

Pout0

Pout1

Pout2

Pout3

Pout4

Pout5

Pout6

Pout7

ERROR

Cdrv

INTOUT

SCL/SCK

GAIN

nCS

nRST

SDA/SI

I/O

LC717A00AJ

Pin Functions Capacitance sensor input Capacitance sensor input Capacitance sensor input Capacitance sensor input Capacitance sensor input Capacitance sensor input Capacitance sensor input Capacitance sensor input Reference capacitance input Cin0 judgment result output Cin1 judgment result output Cin2 judgment result output Cin3 judgment result output Cin4 judgment result output Cin5 judgment result output Cin6 judgment result output Cin7 judgment result output Error occurrence status output Output for capacitance sensors drive
Interrupt output Clock input (I2C) / Clock input (SPI)
Selection pin of the initial value of gain of the 2nd-amplifier
Interface selection / Chip select inverting input (SPI)
External reset signal inverting input
Data input and output (I2C) / Data input (SPI)

VDD
VSS VDD
VSS VDD
VSS VDD

Pin Type AMP
R Buffer
Buffer
R
R

VSS

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LC717A00AJ

Table 8. PIN FUNCTION (continued)

Pin Name

I/O

Pin Functions

SA/SO

I/O

Slave address selection (I2C) / Data output (SPI)

VDD

Pin Type R

VSS

Buffer

VDD

Power supply (2.6 V to 5.5 V) (Note 14)

VSS

Ground (Earth) (Notes 14, 15)

14. Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended. In this case, the small-valued capacitor should be at least 0.1 mF, and is mounted near the LSI.
15. When VSS terminal is not grounded in battery-powered mobile equipment, detection sensitivity may be degraded.

Details of Pin Functions
Cin0 to Cin7 These are the capacitance-sensor-input pins. These pins
are used by connecting them to the touch switch pattern. Cin and the Cdrv wire patterns should be close to each other. By doing so, Cdrv and Cin patterns are capacitively coupled. Therefore, LSI can detect capacitance change near each pattern as 8-bit digital data.
However, if the shape of each pattern or the capacitively coupled value of Cdrv is not appropriate, it may not be able to detect the capacitance change correctly.
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude values. Cin0 to Cin7 are connected to the inverting input of the 1st amplifier in the LSI.
During measurement process, channels other than the one being measured are all in "Low" condition.
Leave the unused terminals open.
Cref It is the reference-capacitance-input pin. It is used by
connecting to the wire pattern like Cin pins or is used by connecting any capacitance between this pin and Cdrv pin.
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude values. Cref is connected to the non-inverting input of the 1st amplifier in the LSI.
Due to the parasitic capacitance generated in the wire connections of Cin pins and their patterns, as well as the one generated between the wire patterns of Cin and Cdrv pins, Cref may not detect capacitance change of each Cin pin accurately. In this case, connect an appropriate capacitance between Cref and Cdrv to detect capacitance change accurately.

However, if the difference between the parasitic capacitance of each Cin pin is extremely large, it may not detect capacitance change in each Cin pin correctly.
Pout0 to Pout7 These are the detection-result-output pins. The
capacitance detection results of Cin0 to Cin7 are compared with the threshold of the LSI. The pin outputs a "High" or a "Low" depending on the result.
ERROR It is the error-occurrence-status-output pin. It outputs
"Low" during normal operation. If there is a calibration error or a system error, it outputs "High" to indicate that an error occurred.
Cdrv It is the output pin for capacitance sensors drive. It outputs
the pulse voltage which is needed to detect capacitance at Cin0 to Cin7.
Cdrv and Cin wire patterns should be close to each other so that they are capacitively coupled.
INTOUT It is the interrupt-output pin. It outputs "High" when
a measurement process is completed. Connect to a main microcomputer if necessary, and use as
interrupt signal. Leave the terminal open if not in used.
SCL/SCK Clock input (I2C)/Clock input (SPI). It is the clock input
pin of the I2C compatible bus or the SPI depending on the mode of operation.
If interface is not to be used, fix the pin to "High". However, even if interface is not to be used, providing a communication terminal on board is still recommended.

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LC717A00AJ

GAIN In this LSI, there is a two-stage amplifier that detects the
changes in the capacitance and outputs analog-amplitude values. It is the selection pin of the initial value of gain of the 2nd amplifier.
Even if this LSI is used alone, gain setting can still be selected through this terminal. At initialization of the LSI, it is set to 7-times higher than the minimum setting when GAIN pin is "Low", and is set to 14-times higher than the minimum setting when GAIN pin is "High".
nCS Interface selection/Chip-select-inverting input (SPI).
Selection of I2C compatible bus mode or SPI mode is through this terminal. After initialization, the LSI is automatically in I2C compatible bus mode. To continually use I2C compatible bus mode, fix nCS pin to "High". To switch to SPI mode after LSI initialization, change the nCS input "High" "Low". The nCS pin is used as the chip-select-inverting input pin of SPI, and SPI mode is kept until LSI is again initialized.
If interface is not to be used, fix the pin to "High".

nRST It is the external-reset-signal-inverting-input pin. When
nRST pin is "Low", LSI is in the reset state. Each pin (Cin0 to 7, Cref, Pout0 to 7, ERROR) is "Hi-Z"
during reset state.
SDA/SI Data input and output (I2C)/Data input (SPI). It is the data
input and output pin of the I2C compatible bus or the data input pin of the SPI depending on the mode of operation.
If interface is not to be used, fix the pin to "High". However, even if interface is not to be used, providing a communication terminal on board is still recommended.
SA/SO Slave address selection (I2C)/Data output (SPI). It is the
slave address selection pin of the I2C compatible bus or the data output pin of the SPI depending on the mode of operation.
If interface is not to be used, fix the pin to "High". However, even if interface is not to be used, providing a communication terminal on board is still recommended.

Table 9. ORDERING INFORMATION Device

Package

Shipping (Qty / Packing)

LC717A00AJ-AH

SSOP30 (225 mil) (Pb-Free / Halogen Free)

1000 / Tape & Reel

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

I2C Bus is a trademark of Philips Corporation.

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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SSOP30 (225 mil) CASE 565AZ ISSUE A

DATE 25 OCT 2013

1.00 5.80

SOLDERING FOOTPRINT* (Unit: mm)

GENERIC MARKING DIAGRAM*
XXXXXXXXXX YMDDD

0.50

0.32

NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data
*This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present.

DOCUMENT NUMBER: 98AON80824E DESCRIPTION: SSOP30 (225 MIL)

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