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IMXRT1020IEC Rev3

i.MXRT1020, RT1020, i.MX, Arm Cortex, industrial

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NXP Semiconductors Data Sheet: Technical Data

Document Number: IMXRT1020IEC Rev. 3, 08/2021

MIMXRT1021CAG4A MIMXRT1021CAG4B

MIMXRT1021CAF4A MIMXRT1021CAF4B

i.MX RT1020 Crossover Processors for Industrial Products

Package Information Plastic Package
144-Pin LQFP, 20 x 20 mm, 0.5 mm pitch 100-Pin LQFP, 14 x 14 mm, 0.5 mm pitch

Ordering Information

1 i.MX RT1020 introduction

See Table 2 on page 6

The i.MX RT1020 is a processor of i.MX RT family 1. i.MX RT1020 introduction . . . . . . . . . . . . . . . . . . . . . . . . 1

featuring NXP's advanced implementation of the Arm� 1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Cortex�-M7 core, which operates at speeds up to 396

1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6 2. Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

MHz to provide high CPU performance and real-time

2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

response.

3. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1. Special signal considerations . . . . . . . . . . . . . . . 16

The i.MX RT1020 processor has 256 KB on-chip RAM,

3.2. Recommended connections for unused analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

which can be flexibly configured as TCM or

4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 18

general-purpose on-chip RAM. The i.MX RT1020 integrates advanced power management module with

4.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 18 4.2. System power and clocks . . . . . . . . . . . . . . . . . . 25 4.3. I/O parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 30

DCDC and LDO that reduces complexity of external power supply and simplifies power sequencing. The

4.4. System modules . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5. External memory interface . . . . . . . . . . . . . . . . . 41 4.6. Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

i.MX RT1020 also provides various memory interfaces, 4.7. Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

including SDRAM, RAW NAND FLASH, NOR FLASH, SD/eMMC, Quad SPI, and a wide range of

4.8. Communication interfaces . . . . . . . . . . . . . . . . . . 61 4.9. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 75

connectivity interfaces including UART, SPI, I2C, USB, 5.1. Boot mode configuration pins . . . . . . . . . . . . . . . 75

and CAN; for connecting peripherals including WLAN,

5.2. Boot device interface allocation . . . . . . . . . . . . . . 75 Package information and contact assignments . . . . . . . 81

BluetoothTM, and GPS. The i.MX RT1020 also has rich 6.1. 20 x 20 mm package information . . . . . . . . . . . . 81

audio features, including SPDIF and I2S audio interface.

6.2. 14 x 14 mm package information . . . . . . . . . . . . 90 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Various analog IP integration, including ADC, analog

comparator, temperature sensor, etc.

NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
� 2018-2021 NXP B.V.

i.MX RT1020 introduction
The i.MX RT1020 is specifically useful for applications such as: � Industrial � Motor Control � Home Appliance � IoT
1.1 Features
The i.MX RT1020 processors are based on Arm Cortex-M7 CoreTM Platform, which has the following features:
� Supports single Arm Cortex-M7 with: -- 16 KB L1 Instruction Cache -- 16 KB L1 Data Cache -- Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture -- Support the Armv7-M Thumb instruction set
� Integrated MPU, up to 16 individual protection regions � Up to 256 KB I-TCM and D-TCM in total � Target frequency of 396 MHz � Cortex M7 CoreSightTM components integration for debug � Frequency of the core, as per Table 11, "Operating ranges," on page 21.
The SoC-level memory system consists of the following additional components: -- Boot ROM (96 KB) -- On-chip RAM (256 KB) � Configurable RAM size up to 256 KB shared with CM7 TCM
� External memory interfaces: -- 8/16-bit SDRAM, up to SDRAM-133 -- 8/16-bit SLC NAND FLASH, with ECC handled in software -- SD/eMMC -- SPI NOR/NAND FLASH -- Parallel NOR FLASH with XIP support -- Single/Dual channel Quad SPI FLASH with XIP support
� Timers and PWMs: -- Two General Programmable Timers � 4-channel generic 32-bit resolution timer � Each support standard capture and compare operation -- Four Periodical Interrupt Timers � Generic 32-bit resolution timer � Periodical interrupt generation

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i.MX RT1020 introduction
-- Two Quad Timers � 4-channel generic 16-bit resolution timer each � Each support standard capture and compare operation � Quadrature decoder integrated
-- Two FlexPWMs � Up to 12 individual PWM channels per each � 16-bit resolution PWM suitable for Motor Control applications
-- Two Quadrature Encoders/Decoders
Each i.MX RT1020 processor enables the following interfaces to external devices (some of them are multiplexed and not available simultaneously):
� Audio: -- S/PDIF input and output -- Three synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and codec/DSP interfaces -- MQS interface for medium quality audio via GPIO pads
� Connectivity: -- One USB 2.0 OTG controller with integrated PHY interface -- Two Ultra Secure Digital Host Controller (uSDHC) interfaces � MMC 4.5 compliance support up to 100 MB/sec � SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec � Support for SDXC (extended capacity) -- One 10/100 M Ethernet controller with IEEE1588 supported -- Eight universal asynchronous receiver/transmitter (UARTs) modules -- Four I2C modules -- Four SPI modules -- Two FlexCAN modules
� GPIO and Pin Multiplexing: -- General-purpose input/output (GPIO) modules with interrupt capability -- Input/output multiplexing controller (IOMUXC) to provide centralized pad control -- 96 GPIOs for 144-pin LQFP package, 57 GPIOs for 100-pin LQFP package -- One FlexIO
The i.MX RT1020 processors integrate Analog module: -- Two Analog-Digital-Converters (ADC), up to 19 channels -- Four Analog Comparators (ACMP)
The i.MX RT1020 processors integrate advanced power management unit and controllers: � Full PMIC integration, including on-chip DCDC and LDOs � Temperature sensor with programmable trip points

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i.MX RT1020 introduction
� GPC hardware power management controller
The i.MX RT1020 processors support the following system debug: � Arm CortexM7 CoreSight debug and trace architecture � Trace Port Interface Unit (TPIU) to support off-chip real-time trace � Support for 5-pin (JTAG) and SWD debug interfaces selected by eFuse
Security functions are enabled and accelerated by the following hardware: � High Assurance Boot (HAB) � Data Co-Processor (DCP): -- AES-128, ECB, and CBC mode -- SHA-1 and SHA-256 -- CRC-32 � Bus Encryption Engine (BEE) -- AES-128, ECB, and CTR mode -- On-the-fly QSPI Flash decryption � True random number generation (TRNG) � Secure Non-Volatile Storage (SNVS) -- Secure real-time clock (RTC) -- Zero Master Key (ZMK) � Secure JTAG Controller (SJC)
Table 1 demonstrates the comparison between 100 LQFP and 144 LQFP package.

Table 1. The comparison between 100 LQFP and 144 LQFP package

RAM/KB USB OTG ENET port KPP number
SEMC SPDIF uSDHC1 FlexIO GPIO FlexPWM Channel XBAR IN/OUT
SAI

144 LQFP 256 1
MII/RMII 8 x 8 Yes Yes 2 32 96 24 16 3

100 LQFP 256 1 RMII 4 x 4 No Yes 1 22 57 16 9 3

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i.MX RT1020 introduction

Table 1. The comparison between 100 LQFP and 144 LQFP package (continued)

144 LQFP

100 LQFP

ACMP

ADC channel

FLEXCAN

I2C

LPUART

FlexSPI

LPSPI

1 SD is 3.3 V in the 100 LQFP package, while it supports both 3.3 V and 1.8 V in the 144 LQFP package.

NOTE
The actual feature set depends on the part numbers as described in Table 2. Functions such as display and camera interfaces, connectivity interfaces, and security features are not offered on all derivatives.

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i.MX RT1020 introduction
1.2 Ordering information
Table 2 provides examples of orderable part numbers covered by this data sheet.
Table 2. Ordering information

Part Number

Feature

Package

MIMXRT1021CAG4A MIMXRT1021CAF4A

Features supports: � 396 MHz, industrial grade for general
purpose � 256K RAM � CAN x2 � Ethernet � eMMC 4.5/SD 3.0 x2 � USB OTG x1 � SAI x3 � SPDIF x1 � Timer x2 � PWM x2 � UART x8 � I2C x4 � SPI x4 � ADC x2 � ACMP x4 � 96 GPIOs
Features supports: � 396 MHz, industrial grade for general
purpose � 256K RAM � CAN x2 � Ethernet � eMMC 4.5/SD 3.0 x1 � USB OTG x1 � SAI x3 � SPDIF x1 � Timer x2 � PWM x2 � UART x8 � I2C x4 � SPI x4 � ADC x2 � ACMP x4 � 57 GPIOs

20 x 20 mm, 0.5 mm pitch, 144-pin LQFP
14 x 14 mm, 0.5 mm pitch, 100-pin LQFP

Junction Temperature Tj (C) -40 to +105
-40 to +105

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Part Number MIMXRT1021CAG4B
MIMXRT1021CAF4B

i.MX RT1020 introduction

Table 2. Ordering information

Feature

Package

20 x 20 mm, 0.5 mm pitch, 144-pin LQFP
14 x 14 mm, 0.5 mm pitch, 100-pin LQFP

Junction Temperature Tj (C) -40 to +105
-40 to +105

Figure 1 describes the part number nomenclature so that characteristics of a specific part number can be identified (for example, cores, frequency, temperature grade, fuse options, and silicon revision). The primary characteristic which describes which data sheet applies to a specific part is the temperature grade (junction) field.
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field and matching it to the proper data sheet. If there are any questions, visit the web page nxp.com/IMXRT or contact an NXP representative for details.

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i.MX RT1020 introduction

M IMX X X @ ## % + VV $ A

Qualification Level Prototype Samples Mass Production Special
Part # series i.MX RT
Family First Generation RT family Reserved
Sub-Family RT101x RT102x RT104x RT105x RT106x

Silicon Rev

XX RT
@ 1 2-8
## 01 02 04 05 06

Tie

Standard Feature

Full Feature

4MB Flash SIP

Enhanced Feature

Far Field AFE

Facial Recognition

Local Voice Control (audio input models)

Local Voice Control (text input models)

Core Frequency

400 MHz

500 MHz

600 MHz

Package Type

225MAPBGA, 13 x 13 mm, 0.8 mm pitch

196MAPBGA, 12 x 12 mm, 0.8 mm pitch

196MAPBGA, 10 x 10 mm, 0.65 mm pitch VL

169MAPBGA, 11 x 11 mm, 0.8 mm pitch

169MAPBGA, 9 x 9 mm, 0.65 mm pitch

144LQFP, 20 x 20 mm, 0.5 mm pitch

100LQFP, 14 x 14 mm, 0.5 mm pitch

80LQFP, 12 x 12 mm, 0.5 mm pitch

Temperature (Tj)

Consumer: 0 to + 95 �C

Industrial: -40 to +105 �C

Extended Industrial: -40 to +125 eC

Figure 1. Part number nomenclature--i.MX RT10XX family

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Architectural overview
2 Architectural overview
The following subsections provide an architectural overview of the i.MX RT1020 processor system.
2.1 Block diagram
Figure 2 shows the functional modules in the i.MX RT1020 processor system1.

System Control Secure JTAG PLL / OSC RTC and Reset
Enhanced DMA IOMUX
GP Timer x6 Quadrature ENC x2
QuadTimer (4-Channel) x2
FlexPWM (12-Channel) x2 Watch Dog x4
Internal Memory 256 KB OCRAM shared with TCM
96 KB ROM
Power Management DCDC
LDO Temp Monitor

CPU Platform

ARM Cortex-M7

16 KB I-cache

16 KB D-cache

FPU

MPU

NVIC

Up to 256 KB TCM

External Memory
FlexSPI (dual-Channel QuadSPI NAND and NOR, Octal Flash, and RAM)
External Memory Controller 8/16 bit SDRAM
Parallel NOR Flash NAND Flash PSRAM

Security HAB

Ciphers

RNG

Secure RTC

eFuse

Connectivity eMMC 4.5 / SD 3.0 x2
UART x8 8 x 8 Keypad
I2C x4 SPI x4 GPIO I2S / SAI x3 S/PDIF Tx / Rx FlexCAN x2
USB2.0 OTG with PHY 10 / 100 ENET with IEEE 1588 x1 ADC ADC x2 ACMP x4

.
Figure 2. i.MX RT1020 system block diagram

1. Some modules shown in this block diagram are not offered on all derivatives. See Table 2 for details.

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Modules list

3 Modules list

The i.MX RT1020 processors contain a variety of digital and analog modules. Table 3 describes these modules in alphabetical order.
Table 3. i.MX RT1020 modules list

Block mnemonic

Block name

Subsystem

Brief description

ACMP1 ACMP2 ACMP3 ACMP4

Analog Comparator

Analog

The comparator (CMP) provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation).

ADC1 ADC2 AOI
Arm
BEE CCM GPC SRC CSU
DAP
DCDC

Analog to Digital Converter

Analog

The ADC is a 12-bit general purpose analog to digital converter.

And-Or-Inverter

Cross Trigger

The AOI provides a universal boolean function generator using a four team sum of products expression with each product term containing true or complement values of the four selected inputs (A, B, C, D).

Arm Platform

Arm

The Arm Core Platform includes 1x Cortex-M7 core. It also includes associated sub-blocks, such as Nested Vectored Interrupt Controller (NVIC), Floating-Point Unit (FPU), Memory Protection Unit (MPU), and CoreSight debug modules.

Bus Encryption Engine Security

On-The-Fly FlexSPI Flash Decryption

Clock Control Module, General Power Controller, System Reset Controller

Clocks, Resets, and Power Control

These modules are responsible for clock and reset distribution in the system, and also for the system power management.

Central Security Unit

Security

The Central Security Unit (CSU) is responsible for setting comprehensive security policy within the i.MX RT1020 platform.

Debug Access Port

System Control Peripherals

The DAP provides real-time access for the debugger without halting the core to: � System memory and peripheral registers � All debug configuration registers The DAP also provides debugger access to JTAG scan chains. The DAP module is internal to the Cortex-M7 Core Platform.

DCDC Converter

Analog

The DCDC module is used for generating power supply for core logic. Main features are: � Adjustable high efficiency regulator � Supports 3.3 V input voltage � Supports nominal run and low power standby modes � Supports at 0.9 ~ 1.3 V output in run mode � Supports at 0.9 ~ 1.0 V output in standby mode � Over current and over voltage detection

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Modules list

Table 3. i.MX RT1020 modules list (continued)

Block mnemonic

Block name

Subsystem

eDMA

enhanced Direct Memory System Control

Access

Peripherals

ENC

Quadrature Encoder/Decoder

Timer Peripherals

ENET

Ethernet Controller

Connectivity Peripherals

EWM

External Watchdog Monitor

Timer Peripherals

FLEXCAN1 FLEXCAN2

Flexible Controller Area Connectivity

Network

Peripherals

FlexIO1

Flexible Input/output

Connectivity and Communications

Brief description
There is an enhanced DMA (eDMA) engine and two DMA_MUX. � The eDMA is a 32 channel DMA engine, which is
capable of performing complex data transfers with minimal intervention from a host processor. � The DMA_MUX is capable of multiplexing up to 128 DMA request sources to the 32 DMA channels of eDMA.
The enhanced quadrature encoder/decoder module provides interfacing capability to position/speed sensors. There are five input signals: PHASEA, PHASEB, INDEX, TRIGGER, and HOME. This module is used to decode shaft position, revolution count, and speed.
The Ethernet Media Access Controller (MAC) is designed to support 10/100 Mbit/s Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The module has dedicated hardware to support the IEEE 1588 standard. See the ENET chapter of the reference manual for details.
The EWM modules is designed to monitor external circuits, as well as the software flow. This provides a back-up mechanism to the internal WDOG that can reset the system. The EWM differs from the internal WDOG in that it does not reset the system. The EWM, if allowed to time-out, provides an independent trigger pin that when asserted resets or places an external circuit into a safe mode.
The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the Electromagnetic interference (EMI) environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0 B, which supports both standard and extended message frames.
The FlexIO is capable of supporting a wide range of protocols including, but not limited to: UART, I2C, SPI, I2S, camera interface, display interface, PWM waveform generation, etc. The module can remain functional when the chip is in a low power mode provided the clock it is using remain active.

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Modules list

Table 3. i.MX RT1020 modules list (continued)

Block mnemonic

Block name

Subsystem

FlexPWM1 FlexPWM2

Pulse Width Modulation Timer Peripherals

FlexRAM

RAM

Memories

FlexSPI
GPIO1 GPIO2 GPIO3 GPIO5 GPT1 GPT2

Quad Serial Peripheral Connectivity and

Interface

Communications

General Purpose I/O Modules

System Control Peripherals

General Purpose Timer Timer Peripherals

KPP

Keypad Port

Human Machine Interfaces

LPI2C1 LPI2C2 LPI2C3 LPI2C4

Low Power Inter-integrated Circuit

Connectivity and Communications

Brief description
The pulse-width modulator (PWM) contains four PWM sub-modules, each of which is set up to control a single half-bridge power stage. Fault channel support is provided. The PWM module can generate various switching patterns, including highly sophisticated waveforms.
The i.MX RT1020 has 256 KB of on-chip RAM which could be flexible allocated to I-TCM, D-TCM, and on-chip RAM (OCRAM) in a 32 KB granularity. The FlexRAM is the manager of the 256 KB on-chip RAM array. Major functions of this blocks are: interfacing to I-TCM and D-TCM of Arm core and OCRAM controller; dynamic RAM arrays allocation for I-TCM, D-TCM, and OCRAM.
FlexSPI acts as an interface to one or two external serial flash devices, each with up to four bidirectional data lines.
Used for general purpose input/output to external ICs. Each GPIO module supports up to 32 bits of I/O.
Each GPT is a 32-bit "free-running" or "set and forget" mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in "set and forget" mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock.
The KPP is a 16-bit peripheral that can be used as a keypad matrix interface or as general purpose input/output (I/O). It supports 8 x 8 external key pad matrix. Main features are: � Multiple-key detection � Long key-press detection � Standby key-press detection � Supports a 2-point and 3-point contact key matrix
The LPI2C is a low power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a master. The I2C provides a method of communication between a number of external devices. More detailed information, see Section 4.8.2, LPI2C module timing parameters.

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Modules list

Table 3. i.MX RT1020 modules list (continued)

Block mnemonic

Block name

Subsystem

Brief description

LPSPI1 LPSPI2 LPSPI3 LPSPI4

Low Power Serial Peripheral Interface

Connectivity and Communications

The LPSPI is a low power Serial Peripheral Interface (SPI) module that support an efficient interface to an SPI bus as a master and/or a slave. � It can continue operating while the chip is in stop
modes, if an appropriate clock is available � Designed for low CPU overhead, with DMA off
loading of FIFO register access

LPUART1 LPUART2 LPUART3 LPUART4 LPUART5 LPUART6 LPUART7 LPUART8

UART Interface

Connectivity Peripherals

Each of the UART modules support the following serial data transmit/receive protocols and configurations: � 7- or 8-bit data words, 1 or 2 stop bits, programmable
parity (even, odd or none) � Programmable baud rates up to 20 Mbps.

MQS
QuadTimer1 QuadTimer2

Medium Quality Sound QuadTimer

Multimedia Peripherals
Timer Peripherals

MQS is used to generate 2-channel medium quality PWM-like audio via two standard digital GPIO pins.
The quad-timer provides four time channels with a variety of controls affecting both individual and multi-channel features.Specific features include up/down count, cascading of counters, programmable module, count once/repeated, counter preload, compare registers with preload, shared use of input signals, prescaler controls, independent capture/compare, fault input control, programmable input filters, and multi-channel synchronization.

ROMCP RTC OSC RTWDOG

ROM Controller with Patch
Real Time Clock Oscillator
Watch Dog

Memories and Memory Controllers

The ROMCP acts as an interface between the Arm advanced high-performance bus and the ROM. The on-chip ROM is only used by the Cortex-M7 core during boot up. Size of the ROM is 96 KB.

Clock Sources and Control

The RTC OSC provides the clock source for the Real-Time Clock module. The RTC OSC module, in conjunction with an external crystal, generates a 32.768 kHz reference clock for the RTC.

Timer Peripherals

The RTWDG module is a high reliability independent timer that is available for system to use. It provides a safety feature to ensure software is executing as planned and the CPU is not stuck in an infinite loop or executing unintended code. If the WDOG module is not serviced (refreshed) within a certain period, it resets the MCU. Windowed refresh mode is supported as well.

SAI1 SAI2 SAI3
SA-TRNG

Synchronous Audio Interface

Multimedia Peripherals

Standalone True Random Security Number Generator

The SAI module provides a synchronous audio interface (SAI) that supports full duplex serial interfaces with frame synchronization, such as I2S, AC97, TDM, and codec/DSP interfaces.
The SA-TRNG is hardware accelerator that generates a 512-bit entropy as needed by an entropy consuming module or by other post processing functions.

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Modules list

Table 3. i.MX RT1020 modules list (continued)

Block mnemonic

Block name

Subsystem

Brief description

SEMC

Smart External Memory Controller

Memory and Memory Controller

The SEMC is a multi-standard memory controller optimized for both high-performance and low pin-count. It can support multiple external memories in the same application with shared address and data pins. The interface supported includes SDRAM, NOR Flash, SRAM, and NAND Flash, as well as 8080 display interface.

SJC
SNVS SPDIF Temp Monitor USBO2

System JTAG Controller System Control Peripherals

Secure Non-Volatile Storage
Sony Philips Digital Interconnect Format
Temperature Monitor

Security
Multimedia Peripherals Analog

Universal Serial Bus 2.0 Connectivity Peripherals

The SJC provides JTAG interface, which complies with JTAG TAP standards, to internal logic. The i.MX RT1020 processors use JTAG port for production, testing, and system debugging. In addition, the SJC provides BSR (Boundary Scan Register) standard support, which complies with IEEE1149.1 and IEEE1149.6 standards. The JTAG port is accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. The i.MX RT1020 SJC incorporates three security modes for protecting against unauthorized accesses. Modes are selected through eFUSE configuration.
Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, and Master Key Control.
A standard audio file transfer format, developed jointly by the Sony and Phillips corporations. Has Transmitter and Receiver functionality.
The temperature sensor implements a temperature sensor/conversion function based on a temperature-dependent voltage to time conversion.
USBO2 (USB OTG1) contains: � One high-speed OTG 2.0 module with integrated HS
USB PHY � Support eight Transmit (TX) and eight Receive (Rx)
endpoints, including endpoint 0

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Modules list

Table 3. i.MX RT1020 modules list (continued)

Block mnemonic

Block name

Subsystem

uSDHC1 uSDHC2

SD/MMC and SDXC

Connectivity

Enhanced Multi-Media Peripherals

Card / Secure Digital Host

Controller

WDOG1 WDOG2

Watch Dog

XBAR

Cross BAR

Timer Peripherals Cross Trigger

Brief description
i.MX RT1020 specific SoC characteristics: All four MMC/SD/SDIO controller IPs are identical and are based on the uSDHC IP. They are: � Fully compliant with MMC command/response sets
and Physical Layer as defined in the Multimedia Card System Specification, v4.5/4.2/4.3/4.4/4.41/ including high-capacity (size > 2 GB) cards HC MMC. � Fully compliant with SD command/response sets and Physical Layer as defined in the SD Memory Card Specifications, v3.0 including high-capacity SDXC cards up to 2 TB. � Fully compliant with SDIO command/response sets and interrupt/read-wait mode as defined in the SDIO Card Specification, Part E1, v3.0 Two ports support: � 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR104 mode (104 MB/s max) � 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max) � 4-bit transfer mode specifications for eMMC chips up to 100 MHz in HS200 mode (100 MB/s max)
The Watch Dog Timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the Arm core, and a second point evokes an external event on the WDOG line.
Each crossbar switch is an array of muxes with shared inputs. Each mux output provides one output of the crossbar. The number of inputs and the number of muxes/outputs are user configurable and registers are provided to select which of the shared inputs are routed to each output.

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Modules list

3.1 Special signal considerations
Table 4 lists special signal considerations for the i.MX RT1020 processors. The signal names are listed in alphabetical order.
The package contact assignments can be found in Section 6, Package information and contact assignments. Signal descriptions are provided in the i.MX RT1020 Reference Manual (IMXRT1020RM).
Table 4. Special signal considerations

Signal name

Remarks

DCDC_PSWITCH

PAD is in DCDC_IN domain and connected the ground to bypass DCDC. To enable DCDC function, assert to DCDC_IN with at least 1ms delay for DCDC_IN rising edge.

RTC_XTALI/RTC_XTALO

If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO. Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO to either power or ground (>100 M). This will debias the amplifier and cause a reduction of startup margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V. If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin must remain unconnected or driven with a complimentary signal. The logic level of this forcing clock should not exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical conditions. In case when high accuracy real time clock are not required system may use internal low frequency ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO unconnected.

XTALI/XTALO

A 24.0 MHz crystal should be connected between XTALI and XTALO. External load capacitance value depends on the typical load capacitance of crystal used and PCB design. The crystal must be rated for a maximum drive level of 250 W. An ESR (equivalent series resistance) of typical 80 is recommended. NXP SDK software requires 24 MHz on XTALI/XTALO. The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this case, XTALO must be directly driven by the external oscillator and XTALI mounted with 18 pF capacitor. The logic level of this forcing clock cannot exceed NVCC_PLL level. If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter requirements. See OSC24M chapter and relevant interface specifications chapters for details.

GPANAIO

This signal is reserved for NXP manufacturing use only. This output must remain unconnected.

JTAG_nnnn

The JTAG interface is summarized in Table 5. Use of external resistors is unnecessary. However, if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is followed. For example, do not use an external pull down on an input that has on-chip pull-up.

JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and should be avoided.

JTAG_MOD is referenced as SJC_MOD in the i.MX RT1020 reference manual. Both names refer to the same signal. JTAG_MOD must be externally connected to GND for normal operation. Termination to GND through an external pull-down resistor (such as 1 k) is allowed. JTAG_MOD set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard. JTAG_MOD set to low configures the JTAG interface for common SW debug adding all the system TAPs to the chain.

These signals are No Connect (NC) and should be disconnected by the user.

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Signal name POR_B ONOFF
TEST_MODE WAKEUP

Modules list
Table 4. Special signal considerations (continued)
Remarks
This cold reset negative logic input resets all modules and logic in the IC. May be used in addition to internally generated power on reset signal (logical AND, both internal and external signals are considered active low).
ONOFF can be configured in debounce, off to on time, and max time-out configurations. The debounce and off to on time configurations supports 0, 50, 100 and 500 ms. Debounce is used to generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than the debounce time, the power off interrupt is generated. Off to on time supports the time it takes to request power on after a configured button press time has been reached. While in the OFF state, if ONOFF button is pressed longer than the off to on time, the state will transition from OFF to ON. Max time-out configuration supports 5, 10, 15 seconds and disable. Max time-out configuration supports the time it takes to request power down after ONOFF button has been pressed for the defined time.
TEST_MODE is for NXP factory use. The user can leave this signal floating or tie it to ground.
A GPIO powered by SNVS domain power supply which can be configured as wakeup source in SNVS mode.

JTAG JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRSTB JTAG_MOD

Table 5. JTAG controller interface summary

Input Input Input 3-state output Input Input

I/O type

On-chip termination
100 kpull-down 47 kpull-up 47 kpull-up
Keeper
47 kpull-up 100 kpull-down

3.2 Recommended connections for unused analog interfaces
Table 6 shows the recommended connections for unused analog interfaces.
Table 6. Recommended connections for unused analog interfaces

Module

Pad name

USB ADC

USB_OTG1_CHD_B, USB_OTG1_DN, USB_OTG1_DP, USB_OTG1_VBUS VDDA_ADC_3P3

Recommendations if unused
Not connected
VDDA_ADC_3P3 must be powered even if the ADC is not used.

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Electrical characteristics
4 Electrical characteristics
This section provides the device and module-level electrical characteristics for the i.MX RT1020 processors.

4.1 Chip-level conditions
This section provides the device-level electrical characteristics for the IC. See Table 7 for a quick reference to the individual tables and sections.
Table 7. i.MX RT1020 chip-Level conditions

For these characteristics Absolute maximum ratings Thermal resistance Operating ranges External clock sources Maximum supply currents Low power mode supply currents USB PHY current consumption

Topic appears on page 18 on page 19 on page 20 on page 22 on page 23 on page 24 on page 24

4.1.1 Absolute maximum ratings
CAUTION
Stress beyond those listed under Table 8 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Table 8 shows the absolute maximum operating ratings.

Table 8. Absolute maximum ratings

Parameter Description

Symbol

Min

Core supplies input voltage

VDD_SOC_IN

-0.3

VDD_HIGH_IN supply voltage

VDD_HIGH_IN

-0.3

Power for DCDC

DCDC_IN

-0.3

Supply input voltage to Secure Non-Volatile Storage VDD_SNVS_IN

-0.3

and Real Time Clock

USB VBUS supply

USB_OTG1_VBUS

Supply for 12-bit ADC

VDDA_ADC

Max 1.6 3.7 3.6 3.6
5.5 3.6

Unit V V V V
V V

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Table 8. Absolute maximum ratings (continued)

IO supply for GPIO in SDIO1 bank (3.3 V mode) NVCC_SD0

IO supply for GPIO in SDIO1 bank (1.8 V mode)

1.65

IO supply for GPIO bank (3.3 V mode)

NVCC_GPIO

ESD Damage Immunity:

Vesd

Human Body Model (HBM)

Charge Device Model (CDM)

Input/Output Voltage range

Vin/Vout

-0.5

Storage Temperature range

TSTORAGE

-40

1 OVDD is the I/O supply voltage.

Electrical characteristics

3.6

1.95

3.6

1000

500

OVDD + 0.31 V

150

o C

4.1.2 Thermal resistance
Following sections provide the thermal resistance data.

4.1.2.1 20 x 20 mm package thermal resistance
Table 9 displays the 20 x 20 mm LQFP package thermal resistance data.
Table 9. 20 x 20 mm package thermal resistance data

Rating

Board type

Symbol

Value

Unit

Junction to Ambient Natural convection

Single-layer board (1s)

RJA

oC/W 1,2

Junction to Ambient Natural convection

Four-layer board (2s2p)

RJA

oC/W 1,2

Junction to Ambient (@200 Single layer board (1s) ft/min)

RJMA

oC/W 1,3

Junction to Ambient (@200 Four layer board (2s2p) ft/min)

RJMA

oC/W 1,3

Junction to Board

RJB

oC/W 4

Junction to Case

RJC

oC/W 5

Junction to Package Top Natural Convection

oC/W 6

1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2 Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.
3 Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.
4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.
5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

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Electrical characteristics
6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

4.1.2.2 14 x 14 mm package thermal resistance
Table 9 displays the 14 x 14 mm LQFP package thermal resistance data.
Table 10. 14 x 14 mm package thermal resistance data

Rating

Test Conditions

Symbol

Value

Unit Notes

Junction to Ambient Natural convection
Junction to Ambient Natural convection

Single-layer board (1s) Four-layer board (2s2p)

RJA RJA

oC/W 1,2

Junction to Ambient (@200 Single layer board (1s) ft/min)

RJMA

oC/W 1,3

Junction to Ambient (@200 Four layer board (2s2p) ft/min)

RJMA

oC/W 1,3

Junction to Board

RJB

oC/W 4

Junction to Case

RJC

oC/W 5

Junction to Package Top Natural Convection

oC/W 6

4.1.3 Operating ranges
Table 11 provides the operating ranges of the i.MX RT1020 processors. For details on the chip's power structure, see the "Power Management Unit (PMU)" chapter of the i.MX RT1020 Reference Manual (IMXRT1020RM).

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Electrical characteristics

Table 11. Operating ranges

Parameter Description

Symbol

Operating Conditions

Min Typ Max1 Unit

Comment

Run Mode IDLE Mode

VDD_SOC_IN VDD_SOC_IN
VDD_SOC_IN

M7 core at 396 1.15 -- 1.26 V --

MHz

M7 core at 132 1.15 -- 1.26 MHz

M7 core at 24 0.925 -- 1.26 MHz

M7 core

1.15 -- 1.26 V --

operation at 396

MHz or below

SUSPEND (DSM) VDD_SOC_IN

Mode

SNVS Mode

VDD_SOC_IN

Power for DCDC DCDC_IN

VDD_HIGH

VDD_HIGH_IN2 --

internal regulator

Backup battery supply range

VDD_SNVS_IN3 --

USB supply voltages
GPIO supplies

USB_OTG1_VBUS --

NVCC_GPIO

NVCC_SD0

A/D converter

VDDA_ADC_3P3 --

0.925 -- 1.26 V

1.26 V

3.0 3.3 3.6

3.0 -- 3.6 V

2.40 -- 3.6 V

4.40 -- 5.5 V

Refer to Table 14 Low power mode current and power consumption
--
--
Must match the range of voltages that the rechargeable backup battery supports.
Can be combined with VDDHIGH_IN, if the system does not require keeping real time and other data on OFF state.
--

3.0 3.3 3.6 V 1.65 1.8, 3.6 V
3.3
3.0 3.3 3.6 V

All digital I/O supplies (NVCC_xxxx) must be powered (unless otherwise specified in this data sheet) under normal conditions whether the associated I/O pins are in use or not.
VDDA_ADC_3P3 must be powered even if the ADC is not used. VDDA_ADC_3P3 cannot be powered when the other SoC supplies (except VDD_SNVS_IN) are off.

System frequency/ FSYS/FBUS Bus frequency

Junction

temperature

396/ --/-- 24/ MHz --

132

Temperature Operating Ranges

Industrial

-40 -- 105

oC See the application note, i.MX RT1020 Product Lifetime Usage Estimates for information on product lifetime (power-on years) for this processor.

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Electrical characteristics
1 Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set point = (Vmin + the supply tolerance). This result in an optimized power/speed ratio.
2 Applying the maximum voltage results in shorten lifetime. 3.6 V usage limited to < 1% of the use profile. Reset of profile limited to below 3.49 V.
3 In setting VDD_SNVS_IN voltage with regards to Charging Currents and RTC, refer to the i.MX RT1020 Hardware Development Guide (IMXRT1020HDG).

4.1.4 External clock sources

Each i.MX RT1020 processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency (XTALI).
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real time clock operation, and slow system and watch-dog counters. The clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important.
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier.
Table 12 shows the interface frequency requirements.
Table 12. External input clock frequency

Parameter Description

Symbol

Min

Typ

Max

Unit

RTC_XTALI Oscillator1,2

fckil

32.7683/32.0

kHz

XTALI Oscillator2,4

fxtal

MHz

1 External oscillator or a crystal with internal oscillator amplifier. 2 The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware
Development Guide for i.MX RT1020 Crossover Processors (IMXRT1020HDG). 3 Recommended nominal frequency 32.768 kHz. 4 External oscillator or a fundamental frequency crystal with internal oscillator amplifier.

The typical values shown in Table 12 are required for use with NXP SDK to ensure precise time keeping and USB operation. For RTC_XTALI operation, two clock sources are available.
� On-chip 40 kHz ring oscillator--this clock source has the following characteristics: -- Approximately 25 �A more Idd than crystal oscillator -- Approximately �50% tolerance -- No external component required -- Starts up quicker than 32 kHz crystal oscillator
� External crystal oscillator with on-chip support circuit: -- At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit switches over to the crystal oscillator automatically. -- Higher accuracy than ring oscillator -- If no external crystal is present, then the ring oscillator is utilized

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Electrical characteristics
The decision of choosing a clock source should be taken based on real-time clock use and precision time-out.

4.1.5 Maximum supply currents
The data shown in Table 13 represent a use case designed specifically to show the maximum current consumption possible. All cores are running at the defined maximum frequency and are limited to L1 cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited practical use case, if at all, and be limited to an extremely low duty cycle unless the intention was to specifically show the worst case power consumption.
See the i.MX RT1020 Power Consumption Measurement Application Note for more details on typical power consumption under various use case definitions.
Table 13. Maximum supply currents

DCDC_IN

Power Rail

VDD_HIGH_IN VDD_SNVS_IN USB_OTG1_VBUS VDDA_ADC_3P3

NVCC_GPIO NVCC_SD0

Conditions

Max Current

Unit

Max power for chip at 105oC with core 90

mark run on FlexRAM

Include internal loading in analog

250

25 mA for each active USB interface 25

3.3 V power supply for 12-bit ADC, 600 40

A typical, 750 A max, for each ADC.

100 Ohm max loading for touch panel,

cause 33 mA current.

Imax = N x C x V x (0.5 x F) Where: N--Number of IO pins supplied by the power line C--Equivalent external capacitive load V--IO voltage (0.5 x F)--Data change rate. Up to 0.5 of the clock rate (F) In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.

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Electrical characteristics

4.1.6 Low power mode supply currents

Table 14 shows the current core consumption (not including I/O) of i.MX RT1020 processors in selected low power modes.
Table 14. Low power mode current and power consumption

Mode

Test Conditions

Supply

Typical1 Units

SYSTEM IDLE

� LDO_ARM and LDO_SOC set to the Bypass DCDC_IN (3.3 V)

mode � LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.1 V

VDD_HIGH_IN (3.3 V)

� CPU in WFI, CPU clock gated � 24 MHz XTAL is ON

VDD_SNVS_IN (3.3 V)

� System PLL is active, other PLLs are power down Total

� Peripheral clock gated, but remain powered

5.2

0.036

30.479 mW

LOW POWER IDLE

� LDO_SOC is in the Bypass mode, LDO_ARM is in the PG mode
� LDO_2P5 and LDO_1P1 are set to Weak mode � CPU in Power Gate mode � All PLLs are power down � 24 MHz XTAL is off, 24 MHz RCOSC used as
clock source � Peripheral are powered off

DCDC_IN (3.3 V) VDD_HIGH_IN (3.3 V) VDD_SNVS_IN (3.3 V) Total

0.4

0.05

8.085 mW

SUSPEND (DSM)

� LDO_SOC is in the Bypass mode, LDO_ARM is in the PG mode
� LDO_2P5 and LDO_1P1 are shut off � CPU in Power Gate mode � All PLLs are power down � 24 MHz XTAL is off, 24 MHz RCOSC is off � All clocks are shut off, except 32 kHz RTC � Peripheral are powered off

DCDC_IN (3.3 V) VDD_HIGH_IN (3.3 V) VDD_SNVS_IN (3.3 V) Total

0.3 mA 0.09 0.03 1.386 mW

SNVS (RTC)

� All SOC digital logic, analog module are shut off DCDC_IN (0 V)

� 32 kHz RTC is alive

VDD_HIGH_IN (0 V)

VDD_SNVS_IN (3.3 V)

0.020

Total

0.066 mW

1 The typical values shown here are for information only and are not guaranteed. These values are average values measured on a typical process wafer at 25oC.

4.1.7 USB PHY current consumption

4.1.7.1 Power down mode
In power down mode, everything is powered down, including the USB VBUS valid detectors in typical condition. Table 15 shows the USB interface current consumption in power down mode.
Table 15. USB PHY current consumption in power down mode

Current

VDD_USB_CAP (3.0 V) 5.1 A

VDD_HIGH_CAP (2.5 V) 1.7 A

NVCC_PLL (1.1 V) < 0.5 A

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Electrical characteristics
NOTE The currents on the VDD_HIGH_CAP and VDD_USB_CAP were identified to be the voltage divider circuits in the USB-specific level shifters.
4.2 System power and clocks
This section provide the information about the system power and clocks.
4.2.1 Power supplies requirements and restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations:
� Excessive current during power-up phase � Prevention of the device from booting � Irreversible damage to the processor (worst-case scenario)
4.2.1.1 Power-up sequence
The below restrictions must be followed: � VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply. � If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other supply is switched on. � When internal DCDC is enabled, external delay circuit is required to delay the "DCDC_PSWITCH" signal 1 ms after DCDC_IN is stable. � Need to ensure DCDC_IN ramps to 3.0 V within 0.2 x RC, RC is from external delay circuit used for DCDC_PSWITCH and RC must be longer than 1 ms. � POR_B should be held low during the entire power up sequence.
NOTE The POR_B input (if used) must be immediately asserted at power-up and remain asserted until after the last power rail reaches its working voltage. In the absence of an external reset feeding the POR_B input, the internal POR module takes control. See the i.MX RT1020 Reference Manual (IMXRT1020RM) for further details and to ensure that all necessary requirements are being met.
NOTE Need to ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 V supply (for example, from the external components that use both the 1.8 V and 3.3 V supplies).

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Electrical characteristics
NOTE USB_OTG1_VBUS and VDDA_ADC_3P3 are not part of the power supply sequence and may be powered at any time.
4.2.1.2 Power-down sequence
The following restrictions must be followed: � VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply. � If a coin cell is used to power VDD_SNVS_IN, then ensure that it is removed after any other supply is switched off.
4.2.1.3 Power supplies usage
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see "Power Rail" columns in pin list tables of Section 6, Package information and contact assignments.
4.2.2 Integrated LDO voltage regulator parameters
Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins named *_CAP must be connected to external capacitors. The on-board LDOs are intended for internal use only and should not be used to power any external circuitry. See the i.MX RT1020 Reference Manual (IMXRT1020RM) for details on the power tree scheme.
NOTE The *_CAP signals should not be powered externally. These signals are intended for internal LDO operation only.
4.2.2.1 Digital regulators (LDO_SNVS)
There are one digital LDO regulator ("Digital", because of the logic loads that they drive, not because of their construction). The advantages of the regulator is to reduce the input supply variation because of its input supply ripple rejection and its on-die trimming. This translates into more stable voltage for the on-chip logics.
The regulator has two basic modes: � Power Gate. The regulation FET is switched fully off limiting the current draw from the supply. The analog part of the regulator is powered down here limiting the power consumption. � Analog regulation mode. The regulation FET is controlled such that the output voltage of the regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV steps.
For additional information, see the i.MX RT1020 Reference Manual (IMXRT1020RM).

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4.2.2.2 Regulators for analog modules

Electrical characteristics

4.2.2.2.1 LDO_1P1
The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see Table 11 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the USB Phy, and PLLs. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this feature.
For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX RT1020 Crossover Processors (IMXRT1020HDG).
For additional information, see the i.MX RT1020 Reference Manual (IMXRT1020RM).

4.2.2.2.2 LDO_2P5
The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see Table 11 for minimum and maximum input requirements). Typical Programming Operating Range is 2.25 V to 2.75 V with the nominal default setting as 2.5 V. LDO_2P5 supplies the USB PHY, E-fuse module, and PLLs. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded, to take the necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased low-precision weak-regulator is included that can be enabled for applications needing to keep the output voltage alive during low-power modes where the main regulator driver and its associated global bandgap reference module are disabled. The output of the weak-regulator is not programmable and is a function of the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output is 2.525 V and its output impedance is approximately 40 .
For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX RT1020 Crossover Processors (IMXRT1020HDG).
For additional information, see the i.MX RT1020 Reference Manual (IMXRT1020RM).

4.2.2.2.3 LDO_USB
The LDO_USB module implements a programmable linear-regulator function from the USB VUSB voltages (4.4 V�5.5 V) to produce a nominal 3.0 V output voltage. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded, to take the necessary steps. This regulator has a built in power-mux that allows the user to select to run the regulator from either USB VBUS supply, when both are present. If only one of the USB VBUS voltages is present, then, the regulator automatically selects this supply. Current limit is also included to help the system meet in-rush current targets.
For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX RT1020 Crossover Processors (IMXRT1020HDG).

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For additional information, see the i.MX RT1020 Reference Manual (IMXRT1020RM).
4.2.2.2.4 DCDC DCDC can be configured to operate on power-save mode when the load current is less than 50 mA. During the power-save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. DCDC can detect the peak current in the P-channel switch. When the peak current exceeds the threshold, DCDC will give an alert signal, and the threshold can be configured. By this way, DCDC can roughly detect the current loading. DCDC also includes the following protection functions:
� Over current protection. In run mode, DCDC shuts down when detecting abnormal large current in the P-type power switch. In power save mode, DCDC stop charging inductor when detecting large current in the P-type power switch. The threshold is also different in run mode and in power save mode: the former is 1 A�2A, and the latter is 200 mA�250 mA.
� Over voltage protection. DCDC shuts down when detecting the output voltage is too high. � Low voltage detection. DCDC shuts down when detecting the input voltage is too low. For additional information, see the i.MX RT1020 Reference Manual (IMXRT1020RM).
4.2.3 PLL's electrical characteristics
This section provides PLL electrical characteristics.
4.2.3.1 Audio/Video PLL's electrical parameters

Clock output range Reference clock Lock time

Table 16. Audio/video PLL's electrical parameters

Parameter

Value

650 MHz ~1.3 GHz 24 MHz < 11250 reference cycles

4.2.3.2 System PLL

Clock output range Reference clock Lock time

Table 17. System PLL's electrical parameters

Parameter

Value 528 MHz PLL output 24 MHz < 11250 reference cycles

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4.2.3.3 Ethernet PLL

Electrical characteristics

Clock output range Reference clock Lock time

Table 18. Ethernet PLL's electrical parameters

Parameter

Value 1 GHz 24 MHz < 11250 reference cycles

4.2.3.4 USB PLL

Clock output range Reference clock Lock time

Table 19. USB PLL's electrical parameters

Parameter

480 MHz PLL output 24 MHz < 383 reference cycles

Value

4.2.4 On-chip oscillators
4.2.4.1 OSC24M
This block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implement an oscillator. The oscillator is powered from NVCC_PLL.
The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight forward biased-inverter implementation is used.
4.2.4.2 OSC32K
This block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implement a low power oscillator. It also implements a power mux such that it can be powered from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes power from VDD_HIGH_IN when that supply is available and transitions to the backup battery when VDD_HIGH_IN is lost.
In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 K will automatically switch to a crude internal ring oscillator. The frequency range of this block is approximately 10�45 kHz. It highly depends on the process, voltage, and temperature.
The OSC32k runs from VDD_SNVS_CAP supply, which comes from the VDD_HIGH_IN/VDD_SNVS_IN. The target battery is a ~3 V coin cell. Proper choice of coin cell type is necessary for chosen VDD_HIGH_IN range. Appropriate series resistor (Rs) must be used when connecting the coin cell. Rs depends on the charge current limit that depends on the chosen coin cell. For example, for Panasonic ML621:

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� Average Discharge Voltage is 2.5 V � Maximum Charge Current is 0.6 mA For a charge voltage of 3.2 V, Rs = (3.2-2.5)/0.6 m = 1.17 k.
Table 20. OSC32K main characteristics

Min

Typ

Max

Comments

Fosc

-- 32.768 KHz --

Current consumption -- 4 A

This frequency is nominal and determined mainly by the crystal selected. 32.0 K would work as well.
The 4 A is the consumption of the oscillator alone (OSC32k). Total supply consumption will depend on what the digital portion of the RTC consumes. The ring oscillator consumes 1 A when ring oscillator is inactive, 20 A when the ring oscillator is running. Another 1.5 A is drawn from vdd_rtc in the power_detect block. So, the total current is 6.5 A on vdd_rtc when the ring oscillator is not running.

Bias resistor

-- 14 M

Crystal Properties

Cload

-- 10 pF

This integrated bias resistor sets the amplifier into a high gain state. Any

leakage through the ESD network, external board leakage, or even a

scope probe that is significant relative to this value will debias the amp. The

debiasing will result in low gain, and will impact the circuit's ability to start

up and maintain oscillations.

Usually crystals can be purchased tuned for different Cloads. This Cload

value is typically 1/2 of the capacitances realized on the PCB on either side

of the quartz. A higher Cload will decrease oscillation margin, but

increases current oscillating through the crystal.

ESR

-- 50 k

100 k Equivalent series resistance of the crystal. Choosing a crystal with a higher value will decrease the oscillating margin.

4.3 I/O parameters
This section provide parameters on I/O interfaces.

4.3.1 I/O DC parameters
This section includes the DC parameters of the following I/O types: � XTALI and RTC_XTALI (Clock Inputs) DC Parameters � General Purpose I/O (GPIO)
NOTE The term `NVCC_XXXX' in this section refers to the associated supply rail of an input or output.

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Figure 3. Circuit for parameters Voh and Vol for I/O cells

4.3.1.1 XTALI and RTC_XTALI (clock inputs) DC parameters Table 21 shows the DC parameters for the clock inputs.
Table 21. XTALI and RTC_XTALI DC parameters1

Parameter

Symbol Test Conditions

Min

XTALI high-level DC input voltage

Vih

0.8 x NVCC_PLL

XTALI low-level DC input voltage

Vil

RTC_XTALI high-level DC input voltage Vih

0.8

RTC_XTALI low-level DC input voltage Vil

1 The DC parameters are for external clock input only.

Max NVCC_PLL 0.2 1.1 0.2

Unit V V V V

4.3.1.2 Single voltage general purpose I/O (GPIO) DC parameters
Table 22 shows DC parameters for GPIO pads. The parameters in Table 22 are guaranteed per the operating ranges in Table 11, unless otherwise noted.
Table 22. Single voltage GPIO DC parameters

Parameter High-level output voltage1

Symbol VOH

Low-level output voltage1

VOL

Test Conditions

Min

Max

Ioh= -0.1mA (ipp_dse=001,010) NVCC_XXXX - �

Ioh= -1mA

0.2

(ipp_dse=011,100,101,110,111)

Iol= 0.1mA (ipp_dse=001,010) �

0.2

Iol= 1mA

(ipp_dse=011,100,101,110,111)

Units V
V

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Table 22. Single voltage GPIO DC parameters (continued)

Parameter High-level output current

Symbol IOH

Low-level output current

IOL

High-Level input voltage1,2 VIH Low-Level input voltage1,2 VIL

Test Conditions

Min

VDDE = 3.3 V, VOH = VDDE - 0.45

V, ipp_dse as follows:

001

010

011

110

101

110

111

VDDE = 3.3 V, VOL = 0.45 V,

ipp_dse as follows:

001

010

011

110

101

110

111

0.7 x

NVCC_XXXX

Input Hysteresis (NVCC_XXXX= 1.8V) Input Hysteresis (NVCC_XXXX=3.3V) Schmitt trigger VT+2,3
Schmitt trigger VT-2,3

VHYS_LowVDD NVCC_XXXX=1.8V

VHYS_HighVDD NVCC_XXXX=3.3V

VTH+

VTH-

250
250
0.5 x NVCC_XXXX --

Pull-up resistor (22_k PU) RPU_22K

Vin=0V

Pull-up resistor (22_k PU) RPU_22K

Vin=NVCC_XXXX

Pull-up resistor (47_k PU) RPU_47K

Vin=0V

Pull-up resistor (47_k PU) RPU_47K

Vin=NVCC_XXXX

Pull-up resistor (100_k PU) RPU_100K

Vin=0V

Pull-up resistor (100_k PU) RPU_100K

Vin=NVCC_XXXX

Pull-down resistor (100_k RPD_100K

Vin=NVCC_XXXX

PD)

Pull-down resistor (100_k RPD_100K

Vin=0V

PD)

Max

Units

-1 -1 -2 -2 -2 -4 -4
--

1 1 2 2 2 4 4
NVCC_XXXX V

0.3 x

NVCC_XXXX

0.5 x

NVCC_XXXX

212

100

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Table 22. Single voltage GPIO DC parameters (continued)

Parameter

Symbol

Test Conditions

Min

Max

Units

Input current (no PU/PD)

IIN

VI = 0, VI = NVCC_XXXX

-1

Keeper Circuit Resistance R_Keeper

VI =0.3 x NVCC_XXXX, VI = 0.7 105 x NVCC_XXXX

175

1 Overshoot and undershoot conditions (transitions above NVCC_XXXX and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
2 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

4.3.2 I/O AC parameters
This section includes the AC parameters of the following I/O types: � General Purpose I/O (GPIO)
Figure 4 shows load circuit for output, and Figure 5 show the output transition time waveform.

From Output Under Test

Test Point CL

CL includes package, probe and fixture capacitance Figure 4. Load circuit for output

Output (at pad)

80%

20%

Figure 5. Output transition time waveform

OVDD 80%
20% 0V

4.3.2.1 General purpose I/O AC parameters
The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 23 and Table 24, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the IOMUXC control registers.

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Table 23. General purpose I/O AC parameters 1.8 V mode

Parameter

Symbol

Test Condition

Min Typ

Max

Output Pad Transition Times, rise/fall tr, tf (Max Drive, ipp_dse=111)

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

Output Pad Transition Times, rise/fall tr, tf (High Drive, ipp_dse=101)

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

Output Pad Transition Times, rise/fall tr, tf (Medium Drive, ipp_dse=100)

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

Output Pad Transition Times, rise/fall tr, tf (Low Drive. ipp_dse=011)

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

Input Transition Times1

trm

----

1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

2.72/2.79 1.51/1.54
3.20/3.36 1.96/2.07
3.64/3.88 2.27/2.53
4.32/4.50 3.16/3.17
25

Table 24. General purpose I/O AC parameters 3.3 V mode

Parameter

Symbol

Test condition

Min Typ

Max

Output Pad Transition Times, rise/fall tr, tf (Max Drive, ipp_dse=101)

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

Output Pad Transition Times, rise/fall tr, tf (High Drive, ipp_dse=011)

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

Output Pad Transition Times, rise/fall tr, tf (Medium Drive, ipp_dse=010)

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

Output Pad Transition Times, rise/fall tr, tf (Low Drive. ipp_dse=001)

15 pF Cload, slow slew rate 15 pF Cload, fast slew rate

Input Transition Times1

trm

----

1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

1.70/1.79 1.06/1.15
2.35/2.43 1.74/1.77
3.13/3.29 2.46/2.60
5.14/5.57 4.77/5.15
25

Unit ns
ns Unit
ns ns ns

4.3.3 Output buffer impedance parameters
This section defines the I/O impedance parameters of the i.MX RT1020 processors for the following I/O types:
� Single Voltage General Purpose I/O (GPIO)
NOTE GPIO I/O output driver impedance is measured with "long" transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to NVCC_XXXX. Output driver impedance is calculated from this voltage divider (see Figure 6).

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ipp_do predriver
U,(V) VDD

OVDD PMOS (Rpu)
pad
NMOS (Rpd) OVSS

Electrical characteristics

Ztl , L = 20 inches

Cload = 1p

Vin (do)

0 U,(V)
OVDD
Vref

Vref1

Vref2

0 Rpu =

Vovdd - Vref1 Vref1

Ztl

t,(ns) Vout (pad)

t,(ns)

Rpd =

Vref2

Ztl

Vovdd - Vref2

Figure 6. Impedance matching load for measurement

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4.3.3.1 Single voltage GPIO output buffer impedance Table 25 shows the GPIO output buffer impedance (NVCC_XXXX 1.8 V).
Table 25. GPIO output buffer average impedance (NVCC_XXXX 1.8 V)

Parameter
Output Driver Impedance

Symbol

001

010

Rdrv

011

100

101

110

111

Drive strength (DSE)

Typ value
260 130 88 65 52 43 37

Table 26 shows the GPIO output buffer impedance (NVCC_XXXX 3.3 V).
Table 26. GPIO Output buffer average impedance (NVCC_XXXX 3.3 V)

Parameter

Symbol

Drive strength (DSE)

Typ value

001

157

010

Output Driver

Rdrv

011

Impedance

100

101

110

111

Unit
Unit

4.4 System modules
This section contains the timing and electrical parameters for the modules in the i.MX RT1020 processor.

4.4.1 Reset timings parameters
Figure 7 shows the reset timing and Table 27 lists the timing parameters.

ID CC1

POR_B (Input)

CC1

Figure 7. Reset timing diagram

Table 27. Reset timing parameters

Parameter Duration of POR_B to be qualified as valid.

Min Max

Unit

RTC_XTALI cycle

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4.4.2 WDOG reset timing parameters
Figure 8 shows the WDOG reset timing and Table 28 lists the timing parameters.

ID CC3

WDOGn_B (Output)

CC3
Figure 8. WDOGn_B timing diagram

Table 28. WDOGn_B timing parameters

Parameter Duration of WDOGn_B Assertion

Min Max

Unit

RTC_XTALI cycle

NOTE RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or approximately 30 s.
NOTE WDOGn_B output signals (for each one of the Watchdog modules) do not have dedicated pins, but are multiplexed out through the IOMUX. See the IOMUX manual for detailed information.

4.4.3 SCAN JTAG Controller (SJC) timing parameters
Figure 9 depicts the SJC test clock input timing. Figure 10 depicts the SJC boundary scan timing. Figure 11 depicts the SJC test access port. Signal parameters are listed in Table 29.

JTAG_TCK (Input)

VIH SJ3

SJ2
VM VIL

SJ1 SJ2 VM
SJ3

Figure 9. Test clock input timing diagram

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JTAG_TCK (Input)
Data Inputs
Data Outputs
Data Outputs
Data Outputs

VIL SJ6 SJ7

VIH

SJ4

SJ5

Input Data Valid

Output Data Valid

SJ6 Output Data Valid
Figure 10. Boundary scan (JTAG) timing diagram

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JTAG_TCK (Input)
JTAG_TDI JTAG_TMS
(Input)
JTAG_TDO (Output)
JTAG_TDO (Output)
JTAG_TDO (Output)

VIL SJ10 SJ11

VIH

SJ8

SJ9

Input Data Valid

Output Data Valid

SJ10 Output Data Valid
Figure 11. Test access port timing diagram

JTAG_TCK (Input)

JTAG_TRST_B

SJ13

(Input)

SJ12

Electrical characteristics

ID
SJ0 SJ1 SJ2 SJ3 SJ4 SJ5 SJ6 SJ7 SJ8

Figure 12. JTAG_TRST_B timing diagram

Table 29. JTAG timing

Parameter1,2
JTAG_TCK frequency of operation 1/(3�TDC)1 JTAG_TCK cycle time in crystal mode JTAG_TCK clock pulse width measured at VM2 JTAG_TCK rise and fall times Boundary scan input data set-up time Boundary scan input data hold time JTAG_TCK low to output data valid JTAG_TCK low to output high impedance JTAG_TMS, JTAG_TDI data set-up time

All frequencies

Min 0.001 45 22.5 -- 5 24 -- -- 5

Max 22 -- -- 3 -- -- 40 40 --

Unit
MHz ns ns ns ns ns ns ns ns

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Table 29. JTAG timing (continued)

Parameter1,2

SJ9

JTAG_TMS, JTAG_TDI data hold time

SJ10

JTAG_TCK low to JTAG_TDO data valid

SJ11

JTAG_TCK low to JTAG_TDO high impedance

SJ12

JTAG_TRST_B assert time

SJ13

JTAG_TRST_B set-up time to JTAG_TCK low

1 TDC = target frequency of SJC 2 VM = mid-point voltage

All frequencies

Min

Max

100

4.4.4 Debug trace timing specifications

Table 30. Debug trace operating behaviors

Symbol T1 T2 T3 T4 T5 T6 T7 T8

Description ARM_TRACE_CLK frequency of operation ARM_TRACE_CLK period Low pulse width High pulse width Clock and data rise time Clock and data fall time Data setup Data hold

Min

Max

1/T1

0.7

Unit
ns ns ns ns ns
Unit MHz MHz ns ns ns ns ns ns

!2-?42!#%?#,+

Figure 13. ARM_TRACE_CLK specifications

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ARM_TRACE_CLK ARM_TRACE0-3

Figure 14. Trace data specifications
4.5 External memory interface
The following sections provide information about external memory interfaces.

4.5.1 SEMC specifications
The following sections provide information on SEMC interface. Measurements are with a load of 15 pf and an input slew rate of 1 V/ns.

4.5.1.1 SEMC output timing There are ASYNC and SYNC mode for SEMC output timing.

4.5.1.1.1 SEMC output timing in ASYNC mode Table 31 shows SEMC output timing in ASYNC mode.
Table 31. SEMC output timing in ASYNC mode

Symbol

Parameter

Min.

Max.

Unit

Comment

Frequency of operation

133

MHz

TCK

Internal clock period

7.5

TAVO TAHO TADVL

Address output valid time Address output hold time ADV# low time

(TCK - 2) 1

(TCK - 1) 2

These timing parameters

apply to Address and ADV#

for NOR/PSRAM in ASYNC

mode.

TDVO TDHO TWEL

Data output valid time Data output hold time WE# low time

(TCK - 2) 3

(TCK - 1) 4

These timing parameters

apply to Data/CLE/ALE and

WE# for NAND, apply to

Data/DM/CRE for

NOR/PSRAM, apply to

Data/DCX and WRX for DBI

interface.

1 Address output hold time is configurable by SEMC_*CR0.AH. AH field setting value is 0x0 in above table. When AH is set with value N, TAHO min time should be ((N + 1) x TCK). See the i.MX RT1020 Reference Manual (IMXRT1020RM) for more detail about SEMC_*CR0.AH register field.

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2 ADV# low time is configurable by SEMC_*CR0.AS. AS field setting value is 0x0 in above table. When AS is set with value N, TADL min time should be ((N + 1) x TCK - 1). See the i.MX RT1020 Reference Manual (IMXRT1020RM) for more detail about SEMC_*CR0.AS register field.
3 Data output hold time is configurable by SEMC_*CR0.WEH. WEH field setting value is 0x0 in above table. When WEH is set with value N, TDHO min time should be ((N + 1) x TCK). See the i.MX RT1020 Reference Manual (IMXRT1020RM) for more detail about SEMC_*CR0.WEH register field.
4 WE# low time is configurable by SEMC_*CR0.WEL. WEL field setting value is 0x0 in above table. When WEL is set with value N, TWEL min time should be ((N + 1) x TCK - 1). See the i.MX RT1020 Reference Manual (IMXRT1020RM) for more detail about SEMC_*CR0.WEL register field.
Figure 15 shows the output timing in ASYNC mode.

)NTERNALCLOCK !$$2
!$6

4#+ 4!6/

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$!4! 7%

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Figure 15. SEMC output timing in ASYNC mode

4.5.1.1.2 SEMC output timing in SYNC mode Table 32 shows SEMC output timing in SYNC mode.
Table 32. SEMC output timing in SYNC mode

Symbol
TCK TDVO TDHO

Parameter

Min.

Frequency of operation --

Internal clock period

7.5

Data output valid time 1

Data output hold time -1

Max. 133 -- -- --

Unit MHz ns ns ns

Comment
--
--
These timing parameters apply to Address/Data/DM/CKE/control signals with SEMC_CLK for SDRAM.

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Figure 16 shows the output timing in SYNC mode.

Electrical characteristics

3%-#?#,+ $!4!

4$6/

4$(/
$

Figure 16. SEMC output timing in SYNC mode

4.5.1.2 SEMC input timing There are ASYNC and SYNC mode for SEMC input timing.

4.5.1.2.1 SEMC input timing in ASYNC mode Table 33 shows SEMC output timing in ASYNC mode.
Table 33. SEMC output timing in ASYNC mode

Symbol TIS TIH

Parameter Data input setup Data input hold

Min. 8.67 0

Max. -- --

Unit

Comment

For NAND/NOR/PSRAM/DBI,

these timing parameters apply

to RE# and Read Data.

Figure 17 shows the input timing in ASYNC mode.

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.!.$NON
%$/MODEAND./2032!-TIMING

$!4! /%

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4)3 4)(

Figure 17. SEMC input timing in ASYNC mode

4.5.1.2.2 SEMC input timing in SYNC mode Table 34 and Table 35 show SEMC input timing in SYNC mode.
Table 34. SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x0)

Symbol TIS TIH

Parameter Data input setup Data input hold

Min. 8.67 0

Max. -- --

Unit

Comment

Table 35. SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x1)

Symbol TIS TIH

Parameter Data input setup Data input hold

Min. 0.6 1

Max. -- --

Unit

Comment

Figure 18 shows the input timing in SYNC mode.

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3%-#?#,+

$!4! 3%-#?$13

$ 4)3 4)(

Figure 18. SEMC input timing in SYNC mode

4.5.2 FlexSPI parameters
Measurements are with a load 15 pf and input slew rate of 1 V/ns.

4.5.2.1 FlexSPI input/read timing
There are four sources for the internal sample clock for FlexSPI read data:
� Dummy read strobe generated by FlexSPI controller and looped back internally
(FlexSPIn_MCR0[RXCLKSRC] = 0x0)
� Dummy read strobe generated by FlexSPI controller and looped back through the
DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1)
� Read strobe provided by memory device and input from DQS pad
(FlexSPIn_MCR0[RXCLKSRC] = 0x3)
The following sections describe input signal timing for each of these four internal sample clock sources.

4.5.2.1.1 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
Table 36. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0

Symbol -- TIS TIH

Parameter Frequency of operation Setup time for incoming data Hold time for incoming data

Min

Max

Unit

MHz

8.67

Table 37. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X1

Symbol -- TIS TIH

Parameter Frequency of operation Setup time for incoming data Hold time for incoming data

Min

Max

Unit

133

MHz

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SCK SIO[0:7]

TIS

TIH

TIS

TIH

Internal Sample Clock
Figure 19. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1
NOTE Timing shown is based on the memory generating read data on the SCK falling edge, and FlexSPI controller sampling read data on the falling edge.
4.5.2.1.2 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3 There are two cases when the memory provides both read data and the read strobe in SDR mode:
� A1�Memory generates both read data and read strobe on SCK rising edge (or falling
edge)
� A2�Memory generates read data on SCK falling edge and generates read strobe on SCK rising edgeSCK rising edge

Table 38. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1)

Symbol
-- TSCKD TSCKDQS TSCKD - TSCKDQS

Parameter
Frequency of operation Time from SCK to data valid Time from SCK to DQS Time delta between TSCKD and TSCKDQS

Value

Min

Max

166

-2

Unit
MHz ns ns ns

SCK SIO[0:7]
DQS

TSCKD TSCKDQS

Figure 20. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (Case A1)

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NOTE Timing shown is based on the memory generating read data and read strobe on the SCK rising edge. The FlexSPI controller samples read data on the DQS falling edge.

Table 39. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)

Symbol
-- TSCKD TSCKDQS TSCKD - TSCKDQS

Parameter
Frequency of operation Time from SCK to data valid Time from SCK to DQS Time delta between TSCKD and TSCKDQS

Value

Min

Max

166

-2

Unit
MHz ns ns ns

SCK SIO[0:7]
DQS

TSCKD

TSCKDQS

TSCKD

TSCKDQS

TSCKD

TSCKDQS

Internal Sample Clock

Figure 21. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (Case A2)
NOTE Timing shown is based on the memory generating read data on the SCK falling edge and read strobe on the SCK rising edge. The FlexSPI controller samples read data on a half cycle delayed DQS falling edge.

4.5.2.1.3 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

Table 40. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0

Symbol -- TIS TIH

Parameter Frequency of operation Setup time for incoming data Hold time for incoming data

Min

Max

8.67

Unit MHz ns ns

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Table 41. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1

Symbol -- TIS TIH

Parameter Frequency of operation Setup time for incoming data Hold time for incoming data

Min

Max

Unit MHz ns ns

SCLK SIO[0:7] Internal Sample Clock

TIS

TIH

TIS

TIH

Figure 22. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
4.5.2.1.4 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in DDR mode:
� B1�Memory generates both read data and read strobe on SCK edge � B2�Memory generates read data on SCK edge and generates read strobe on SCK2
edge

Table 42. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B1)

Symbol -- TSCKD TSCKDQS TSCKD - TSCKDQS

Parameter Frequency of operation Time from SCK to data valid Time from SCK to DQS Time delta between TSCKD and TSCKDQS

Min

Max

166

-1

Unit MHz
ns ns ns

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SCK SIO[0:7]
DQS

TSCKD TSCKDQS

Figure 23. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B1)

Table 43. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2)

Symbol -- TSCKD TSCKD - TSCKDQS

Parameter Frequency of operation Time from SCK to data valid Time delta between TSCKD and TSCKDQS

Min

Max

166

-1

Unit MHz
ns ns

SCK SIO[0:7]

TSCKD

SCK2 DQS

TSCK2DQS

Figure 24. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2)

4.5.2.2 FlexSPI output/write timing
The following sections describe output signal timing for the FlexSPI controller including control signals and data outputs.

4.5.2.2.1

SDR mode

Table 44. FlexSPI output timing in SDR mode

Symbol -- Tck TDVO TDHO

Parameter Frequency of operation SCK clock period Output data valid time Output data hold time

Min

Max

Unit

1661

MHz

6.0

-1

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Table 44. FlexSPI output timing in SDR mode (continued)

Symbol

Parameter

Min

Max

Unit

TCSS

Chip select output setup time

3 x TCK -1

TCSH

Chip select output hold time

3 x TCK + 2

1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing

specifications.

NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX RT1020 Reference Manual (IMXRT1020RM) for more details.

SCK

T CSS

T CK

TCSH

TDVO

SIO[0:7]

TDHO

Figure 25. FlexSPI output timing in SDR mode

4.5.2.2.2

DDR mode

Table 45. FlexSPI output timing in DDR mode

Symbol

Parameter

Min

Max

Unit

Frequency of operation1

166

MHz

Tck

SCK clock period (FlexSPIn_MCR0[RXCLKSRC] = 0x0)

6.0

TDVO

Output data valid time

2.2

TDHO

Output data hold time

0.8

TCSS

Chip select output setup time

3 x TCK / 2 - 0.7

TCSH

Chip select output hold time

3 x TCK / 2 + 0.8

1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing

specifications.

NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX RT1020 Reference Manual (IMXRT1020RM) for more details.

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SCK
T CSS
CS

TDVO

T CK

TDVO

TCSH

SIO[0:7]

TDHO

Figure 26. FlexSPI output timing in DDR mode

4.6 Audio
This section provide information about SAI/I2S and SPDIF.

4.6.1 SAI/I2S switching specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes. All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP] = 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 46. Master mode SAI timing

Num S1 S2 S3 S4 S5 S6 S7 S8 S9 S10

Characteristic SAI_MCLK cycle time SAI_MCLK pulse width high/low SAI_BCLK cycle time SAI_BCLK pulse width high/low SAI_BCLK to SAI_FS output valid SAI_BCLK to SAI_FS output invalid SAI_BCLK to SAI_TXD valid SAI_BCLK to SAI_TXD invalid SAI_RXD/SAI_FS input setup before SAI_BCLK SAI_RXD/SAI_FS input hold after SAI_BCLK

Min 2 x tsys 40% 4 x tsys 40% -- 0 -- 0 15 0

Max -- 60% -- 60% 15 -- 15 -- -- --

Unit ns MCLK period ns BCLK period ns ns ns ns ns ns

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Num S11 S12 S13 S14 S15 S16 S17 S18

Figure 27. SAI timing--master modes

Table 47. Slave mode SAI timing

Characteristic SAI_BCLK cycle time (input) SAI_BCLK pulse width high/low (input) SAI_FS input setup before SAI_BCLK SAI_FA input hold after SAI_BCLK SAI_BCLK to SAI_TXD/SAI_FS output valid SAI_BCLK to SAI_TXD/SAI_FS output invalid SAI_RXD setup before SAI_BCLK SAI_RXD hold after SAI_BCLK

Min 4 x tsys 40% 10 2 -- 0 10 2

Max -- 60% -- -- 20 -- -- --

Unit ns BCLK period ns ns ns ns ns ns

Figure 28. SAI timing--slave modes

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4.6.2 SPDIF timing parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 48 and Figure 29 and Figure 30 show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Table 48. SPDIF timing parameters

Characteristics
SPDIF_IN Skew: asynchronous inputs, no specs apply SPDIF_OUT output (Load = 50pf) � Skew � Transition rising � Transition falling SPDIF_OUT1 output (Load = 30pf) � Skew � Transition rising � Transition falling
Modulating Rx clock (SPDIF_SR_CLK) period SPDIF_SR_CLK high period SPDIF_SR_CLK low period Modulating Tx clock (SPDIF_ST_CLK) period SPDIF_ST_CLK high period SPDIF_ST_CLK low period

Symbol

Timing parameter range

Min

Max

0.7

Unit ns

1.5

24.2

31.3

ns 1.5 13.6 18.0

srckp

40.0

srckph 16.0

srckpl

16.0

stclkp

40.0

stclkph 16.0

stclkpl 16.0

SPDIF_SR_CLK (Output)

srckpl VM

srckp

srckph VM

Figure 29. SPDIF_SR_CLK timing diagram

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SPDIF_ST_CLK (Input)

stclkpl VM

stclkp

stclkph VM

Figure 30. SPDIF_ST_CLK timing diagram

4.7 Analog
The following sections provide information about analog interfaces.

4.7.1 DCDC
Table 49 introduces the DCDC electrical specification.
Table 49. DCDC electrical specifications

Mode Input voltage Output voltage Max loading Loading in low power modes Efficiency Low power mode Run mode
Inductor Capacitor Over voltage protection
Over Current protection
Low battery detection

Buck mode only, one output 3.3 V 1.1 V 500 mA 200 A ~ 30 mA 90% max Open loop mode � Always continuous mode � Support discontinuous mode 4.7 H 33 F 1.6 V
1 A
2.6 V

Notes
� 10% Configurable 0.8 ~ 1.575 with 25 mV one step -- -- @150 mA Ripple is about 15 mV Configurable by register
-- -- Detect VDDSOC, when the voltage is higher than 1.6 V, shutdown DCDC. Detect the peak current � Run mode: when the current is larger than
1 A, shutdown DCDC. � Stop mode: when the current is larger than
250 mA, stop charging the inductor. Detect the battery, when battery is lower than 2.6 V, shutdown DCDC.

4.7.2 A/D converter
This section introduces information about A/D converter.

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4.7.2.1 12-bit ADC electrical characteristics The section provide information about 12-bit ADC electrical characteristics.

Electrical characteristics

4.7.2.1.1 12-bit ADC operating conditions

Table 50. 12-bit ADC operating conditions

Characteristic

Conditions

Symb

Min

Typ1

Max

Unit Comment

Supply voltage

Absolute Delta to VDD (VDD-VDDA)2

VDDA

3.0

VDDA

-100

3.6

100

Ground voltage

Delta to VSS (VSS-VSSAD)

VSSAD -100

100

Ref Voltage High Ref Voltage Low Input Voltage Input Capacitance Input Resistance

-- -- -- 8/10/12 bit modes ADLPC=0, ADHSC=1 ADLPC=0, ADHSC=0

VDDA VSS VADIN CADIN RADIN

1.13 VSS VSS -- -- --

VDDA VSS -- 1.5 5 12.5

VDDA VSS VDDA 2 7 15

kohms

ADLPC=1, ADHSC=0

kohms

Analog Source

12 bit mode fADCK =

RAS

Resistance

40MHz ADLSMP=0,

ADSTS=10, ADHSC=1

kohms

Tsamp=150 ns

RAS depends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum Sample Time vs RAS

ADC Conversion Clock ADLPC=0, ADHSC=1 fADCK

Frequency

12 bit mode

MHz

ADLPC=0, ADHSC=0 12 bit mode

MHz

ADLPC=1, ADHSC=0 12 bit mode

MHz

1 Typical values assume VDDAD = 3.0 V, Temp = 25�C, fADCK=20 MHz unless otherwise stated. Typical values are for reference only and are not tested in production.
2 DC potential differences

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Figure 31. 12-bit ADC input impedance equivalency diagram

12-bit ADC characteristics

Characteristic

Table 51. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD)

Conditions1

Symb

Min

Typ2

Max

Unit

Comment

Supply Current

ADLPC=1, ADHSC=0

IDDA

250

�A

ADLSMP = 0, ADSTS

= 10, ADCO = 1

ADLPC=0,

350

ADHSC=0

ADLPC=0,

400

ADHSC=1

Supply Current

Stop, Reset, Module IDDA

Off

0.01

0.8

�A

ADC Asynchronous Clock Source

ADHSC=0 ADHSC=1

fADACK

MHz

tADACK = 1/fADACK

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Table 51. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD) (continued)

Characteristic

Conditions1

Symb

Min

Typ2

Max

Unit

Comment

Sample Cycles

ADLSMP=0, ADSTS=00

Csamp --

cycles --

ADLSMP=0,

ADSTS=01

ADLSMP=0,

ADSTS=10

ADLSMP=0,

ADSTS=11

ADLSMP=1,

ADSTS=00

ADLSMP=1,

ADSTS=01

ADLSMP=1,

ADSTS=10

ADLSMP=1,

ADSTS=11

Conversion Cycles ADLSMP=0 ADSTS=00

Cconv --

cycles --

ADLSMP=0

ADSTS=01

ADLSMP=0

ADSTS=10

ADLSMP=0

ADSTS=11

ADLSMP=1

ADSTS=00

ADLSMP=1

ADSTS=01

ADLSMP=1

ADSTS=10

ADLSMP=1,

ADSTS=11

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Table 51. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD) (continued)

Characteristic

Conditions1

Symb

Min

Typ2

Max

Unit

Comment

Conversion Time

ADLSMP=0 ADSTS=00
ADLSMP=0 ADSTS=01
ADLSMP=0 ADSTS=10
ADLSMP=0 ADSTS=11
ADLSMP=1 ADSTS=00
ADLSMP=1 ADSTS=01
ADLSMP=1 ADSTS=10

Tconv --

0.7

�s

Fadc = 40 MHz

0.75

0.8

0.85

0.95

1.05

1.15

Total Unadjusted Error

ADLSMP=1, ADSTS=11
12 bit mode
10 bit mode
8 bit mode

TUE

1.25

3.4

1.5

1.2

Differential Non-Linearity

12 bit mode 10bit mode

DNL

0.76

0.36

8 bit mode

0.14

Integral Non-Linearity 12 bit mode

INL

2.78

10bit mode

0.61

8 bit mode

0.14

Zero-Scale Error

12 bit mode 10bit mode

EZS

-1.14

-0.25

8 bit mode

-0.19

Full-Scale Error

12 bit mode 10bit mode

EFS

-1.06

-0.03

8 bit mode

-0.02

Effective Number of 12 bit mode Bits

ENOB 10.1

10.7

Signal to Noise plus See ENOB Distortion

SINAD SINAD = 6.02 x ENOB + 1.76

1 All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD

LSB 1 LSB = (VREFH VREFL)/2 N

AVGE = 1, AVGS = 11

LSB

AVGE = 1, AVGS = 11

LSB

AVGE = 1, AVGS = 11

LSB

AVGE = 1, AVGS = 11

LSB

AVGE = 1, AVGS = 11

Bits

AVGE = 1, AVGS = 11

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Electrical characteristics 2 Typical values assume VDDAD = 3.0 V, Temp = 25�C, Fadck=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
NOTE The ADC electrical spec is met with the calibration enabled configuration.
Figure 32. Minimum Sample Time Vs Ras (Cas = 2pF)
Figure 33. Minimum Sample Time Vs Ras (Cas = 5 pF)

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Figure 34. Minimum Sample Time Vs Ras (Cas = 10 pF)

4.7.3 ACMP
Table 52 lists the ACMP electrical specifications.
Table 52. Comparator and 6-bit DAC electrical specifications

Symbol VDD IDDHS IDDLS VAIN VAIO VH
VCMPOH VCMPOI tDHS tDLS tDInit IDAC6b

Description

Min.

Supply voltage

3.0

Supply current, High-speed mode -- (EN = 1, PMODE = 1)

Supply current, Low-speed mode -- (EN = 1, PMODE = 0)

Analog input voltage

VSS

Analog input offset voltage

Analog comparator hysteresis1

� CR0[HYSTCTR] = 00

� CR0[HYSTCTR] = 01

� CR0[HYSTCTR] = 10

� CR0[HYSTCTR] = 11

Output high Output low

VDD - 0.5 --

Propagation delay, high-speed -- mode (EN = 1, PMODE = 1)2

Propagation delay, low-speed

mode (EN = 1, PMODE = 0)2

Analog comparator initialization -- delay3

6-bit DAC current adder (enabled) --

Typ. -- 347
42
-- --
1 21 42 64 -- -- 25
50
1.5
5

Max. 3.6 --
--
VDD 21
2 54 108 184 -- 0.5 40
90
--
--

Unit V A A V mV mV
V V ns ns s A

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Table 52. Comparator and 6-bit DAC electrical specifications (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

RDAC6b

6-bit DAC reference inputs

VDD

INLDAC6b

6-bit DAC integral non-linearity -0.3

0.3

LSB4

DNLDAC6b

6-bit DAC differential non-linearity -0.15

0.15

LSB4

1 Typical hysteresis is measured with input voltage range limited to 0.7 to VDD - 0.7 V in high speed mode. 2 Signal swing is 100 mV. 3 Comparator initialization delay is defined as the time between software writes to the enable comparator module and the
comparator output setting to a stable level. 4 1 LSB = Vreference / 64

4.8 Communication interfaces
The following sections provide the information about communication interfaces.

4.8.1 LPSPI timing parameters

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes.

All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.
Table 53. LPSPI Master mode timing

Number Symbol

Description

Min.

Max.

Units

Note

fSCK

Frequency of operation

tSCK

SCK period

fperiph / 2

2 x tperiph

tLead

Enable lead time

tperiph

tLag

Enable lag time

tperiph

tWSCK Clock (SCK) high or low time

tSCK / 2 - 3

tSU

Data setup time (inputs)

tHI

Data hold time (inputs)

Data valid (after SCK edge)

tHO

Data hold time (outputs)

1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be guaranteed this limit is not exceeded.
2 tperiph = 1 / fperiph

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3&6 287387

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Figure 35. LPSPI Master mode timing (CPHA = 0)

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&32/

287387

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,1387

06%,1

%,7

6287 287387

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Figure 36. LPSPI Master mode timing (CPHA = 1)

3257'$7$

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Electrical characteristics

s
Table 54. LPSPI Slave mode timing

Number Symbol

Description

Min.

Max.

Units

Note

fSCK

Frequency of operation

tSCK

SCK period

fperiph / 2

2 x tperiph

tLead

Enable lead time

tperiph

tLag

Enable lag time

tperiph

tWSCK Clock (SCK) high or low time

tSCK / 2 - 5

tSU

Data setup time (inputs)

2.7

tHI

Data hold time (inputs)

Slave access time

tdis

Slave MISO disable time

3.8

tperiph

Data valid (after SCK edge)

14.5

tHO

Data hold time (outputs)

1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be guaranteed this limit is not exceeded.
2 tperiph = 1 / fperiph 3 Time to data active from high-impedance state 4 Hold time to high-impedance state

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Figure 37. LPSPI Slave mode timing (CPHA = 0)

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 3, 08/2021

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Electrical characteristics

3&6 ,1387

6&.

&32/

,1387

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,1387

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Figure 38. LPSPI Slave mode timing (CPHA = 1)

4.8.2 LPI2C module timing parameters
This section describes the timing parameters of the LPI2C module.
Table 55. LPI2C module timing parameters

Symbol

Description

Min

fSCL

SCL clock frequency

Standard mode (Sm)

Fast mode (Fm)

Fast mode Plus (Fm+)

Ultra Fast mode (UFm)

High speed mode (Hs-mode) 0
1 Hs-mode is only supported in slave mode. 2 See General switching specifications.

Max 100 400 1000 5000 3400

Unit kHz

Notes
1, 2

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4.8.3 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single Data Rate) timing, eMMC4.4/4.41/4.5 (Dual Date Rate) timing and SDR104/50(SD3.0) timing.
4.8.3.1 SD/eMMC4.3 (single data rate) AC timing Figure 39 depicts the timing of SD/eMMC4.3, and Table 56 lists the SD/eMMC4.3 timing characteristics.
SD4
SD2 SD1
SD5

SDx_CLK

SD3 SD6

Output from uSDHC to card SDx_DATA[7:0]

SD7 SD8

Input from card to uSDHC SDx_DATA[7:0]

Figure 39. SD/eMMC4.3 timing

ID
SD1
SD2 SD3 SD4 SD5 SD6

Table 56. SD/eMMC4.3 interface timing specification

Parameter

Symbols

Min

Max

Card Input Clock

Clock Frequency (Low Speed)

fPP1

Clock Frequency (SD/SDIO Full Speed/High Speed)

fPP2

Clock Frequency (MMC Full Speed/High Speed)

fPP3

Clock Frequency (Identification Mode)

fOD

Clock Low Time

tWL

Clock High Time

tWH

Clock Rise Time

tTLH

Clock Fall Time

tTHL

400

25/50

20/52

100

400

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

uSDHC Output Delay

tOD

-6.6

3.6

Unit
kHz MHz MHz kHz ns ns ns ns
ns

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Table 56. SD/eMMC4.3 interface timing specification (continued)

Parameter

Symbols

Min

Max

Unit

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD7 uSDHC Input Setup Time

tISU

2.5

SD8 uSDHC Input Hold Time4

tIH

1.5

1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2 In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0�25 MHz. In high-speed mode, clock frequency can be any value between 0�50 MHz.
3 In normal (full) speed mode for MMC card, clock frequency can be any value between 0�20 MHz. In high-speed mode, clock frequency can be any value between 0�52 MHz.
4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

4.8.3.2 eMMC4.4/4.41 (dual data rate) AC timing Figure 40 depicts the timing of eMMC4.4/4.41. Table 57 lists the eMMC4.4/4.41 timing characteristics. Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).
SD1

SDx_CLK

SD2

Output from eSDHCv3 to card SDx_DATA[7:0]

......

SD3 SD4

Input from card to eSDHCv3

SDx_DATA[7:0]

......

ID
SD1 SD1
SD2
SD3 SD4

Figure 40. eMMC4.4/4.41 timing Table 57. eMMC4.4/4.41 interface timing specification

Parameter

Symbols

Min

Max

Card Input Clock

Clock Frequency (eMMC4.4/4.41 DDR)

fPP

Clock Frequency (SD3.0 DDR)

fPP

uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

uSDHC Output Delay

tOD

2.5

7.1

uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

uSDHC Input Setup Time uSDHC Input Hold Time

tISU

1.7

tIH

1.5

Unit
MHz MHz
ns
ns ns

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4.8.3.3 SDR50/SDR104 AC timing Figure 41 depicts the timing of SDR50/SDR104, and Table 58 lists the SDR50/SDR104 timing characteristics.

SCK 4-bit output from uSDHC to card
4-bit input from card to uSDHC

SD1

SD2

SD3

SD4/SD5

SD6

SD7

SD8

Figure 41. SDR50/SDR104 timing

Table 58. SDR50/SDR104 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency Period SD2 Clock Low Time SD3 Clock High Time

tCLK tCL tCH

5.0

0.46 x tCLK 0.54 x tCLK ns 0.46 x tCLK 0.54 x tCLK ns

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD4 uSDHC Output Delay

tOD

�3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)

SD5 uSDHC Output Delay

tOD

�1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD6 uSDHC Input Setup Time

tISU

2.5

SD7 uSDHC Input Hold Time

tIH

1.5

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1

SD8 Card Output Data Window

tODW

0.5 x tCLK --

1Data window in SDR104 mode is variable.

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Electrical characteristics
4.8.3.4 HS200 mode timing Figure 42 depicts the timing of HS200 mode, and Table 59 lists the HS200 timing characteristics.

SCK 8-bit output from uSDHC to eMMC

SD1

SD2

SD3

SD4/SD5

8-bit input from eMMC to uSDHC SD8

Figure 42. HS200 mode timing

Table 59. HS200 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency Period SD2 Clock Low Time SD3 Clock High Time

tCLK tCL tCH

5.0

0.46 x tCLK 0.54 x tCLK ns 0.46 x tCLK 0.54 x tCLK ns

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)

SD5 uSDHC Output Delay

tOD

�1.6

0.74

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1

SD8 Card Output Data Window

tODW

0.5 x tCLK --

1HS200 is for 8 bits while SDR104 is for 4 bits.

4.8.3.5 Bus operation condition for 3.3 V and 1.8 V signaling Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50 mode is 1.8 V. The DC parameters for the NVCC_SD1 supply are identical to those shown in Table 22, "Single voltage GPIO DC parameters," on page 31.
4.8.4 Ethernet controller (ENET) AC electrical specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface.

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Electrical characteristics
4.8.4.1 ENET MII mode timing This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal timings.
4.8.4.1.1 MII receive signal timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER, and ENET_RX_CLK)
The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_RX_CLK frequency. Figure 43 shows MII receive signal timings. Table 60 describes the timing parameters (M1�M4) shown in the figure.
M3
ENET_RX_CLK (input)

ENET_RX_DATA3,2,1,0 (inputs)

ENET_RX_EN ENET_RX_ER

Figure 43. MII receive signal timing diagram

ID M1
M2
M3 M4

Table 60. MII receive signal timing

Characteristic1

Min.

ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to

ENET_RX_CLK setup

ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER hold

ENET_RX_CLK pulse width high

35%

ENET_RX_CLK pulse width low

35%

Max.

Unit

65% 65%

ENET_RX_CLK period ENET_RX_CLK period

1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

4.8.4.1.2 MII transmit signal timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN, ENET_TX_ER, and ENET_TX_CLK)
The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_TX_CLK frequency.

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Electrical characteristics
Figure 44 shows MII transmit signal timings. Table 61 describes the timing parameters (M5�M8) shown in the figure.
M7

ENET_TX_CLK (input)

ENET_TX_DATA3,2,1,0 (outputs)
ENET_TX_EN ENET_TX_ER

M5 M8
M6 Figure 44. MII transmit signal timing diagram

ID M5
M6
M7 M8

Table 61. MII transmit signal timing

Characteristic1

Min.

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN, 5 ENET_TX_ER invalid

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN, -- ENET_TX_ER valid

ENET_TX_CLK pulse width high

35%

ENET_TX_CLK pulse width low

35%

Max.

Unit

65% 65%

ENET_TX_CLK period ENET_TX_CLK period

1 ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

4.8.4.1.3 MII asynchronous inputs signal timing (ENET_CRS and ENET_COL)
Figure 45 shows MII asynchronous input timings. Table 62 describes the timing parameter (M9) shown in the figure.

ENET_CRS, ENET_COL

Figure 45. MII async inputs timing diagram

ID M91

Table 62. MII asynchronous inputs signal timing

Characteristic ENET_CRS to ENET_COL minimum pulse width

Min. 1.5

Max.

Unit

ENET_TX_CLK period

1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode.

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Electrical characteristics
4.8.4.1.4 MII serial management channel timing (ENET_MDIO and ENET_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification. However the ENET can function correctly with a maximum MDC frequency of 15 MHz. Figure 46 shows MII asynchronous input timings. Table 63 describes the timing parameters (M10�M15) shown in the figure.

ENET_MDC (output)

M14 M15

M10

ENET_MDIO (output)

M11

ENET_MDIO (input)

ID M10
M11
M12 M13 M14 M15

M12 M13 Figure 46. MII serial management channel timing diagram

Table 63. MII serial management channel timing

Characteristic
ENET_MDC falling edge to ENET_MDIO output invalid (min. propagation delay) ENET_MDC falling edge to ENET_MDIO output valid (max. propagation delay) ENET_MDIO (input) to ENET_MDC rising edge setup ENET_MDIO (input) to ENET_MDC rising edge hold ENET_MDC pulse width high ENET_MDC pulse width low

Min. 0
--
18 0 40% 40%

Max.

Unit

-- -- 60% 60%

ns ns ENET_MDC period ENET_MDC period

4.8.4.2 RMII mode timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz � 50 ppm continuous reference clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0] and ENET_RX_ER.

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Electrical characteristics
Figure 47 shows RMII mode timings. Table 64 describes the timing parameters (M16�M21) shown in the figure.

ENET_CLK (input)

M16 M17

M18
ENET_TX_DATA (output) ENET_TX_EN

ENET_RX_EN (input) ENET_RX_DATA[1:0] ENET_RX_ER

M19
M20 M21 Figure 47. RMII mode signal timing diagram

ID M16 M17 M18 M19 M20
M21

Table 64. RMII signal timing

Characteristic

Min.

ENET_CLK pulse width high ENET_CLK pulse width low ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid

35% 35% 4

ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid

ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER 2 to ENET_CLK setup

ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER 2 hold

Max.

Unit

65% 65% --

ENET_CLK period ENET_CLK period ns

4.8.5 Flexible Controller Area Network (FLEXCAN) AC electrical specifications
Please refer to Section 4.3.2.1, General purpose I/O AC parameters.

4.8.6 LPUART electrical specifications
Please refer to Section 4.3.2.1, General purpose I/O AC parameters.

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Electrical characteristics
4.8.7 USB PHY parameters
This section describes the USB-OTG PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision 2.0 OTG with the following amendments.
� USB ENGINEERING CHANGE NOTICE -- Title: 5V Short Circuit Withstand Requirement Change -- Applies to: Universal Serial Bus Specification, Revision 2.0
� Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000 � USB ENGINEERING CHANGE NOTICE
-- Title: Pull-up/Pull-down resistors -- Applies to: Universal Serial Bus Specification, Revision 2.0 � USB ENGINEERING CHANGE NOTICE -- Title: Suspend Current Limit Changes -- Applies to: Universal Serial Bus Specification, Revision 2.0 � USB ENGINEERING CHANGE NOTICE -- Title: USB 2.0 Phase Locked SOFs -- Applies to: Universal Serial Bus Specification, Revision 2.0 � On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification -- Revision 2.0 plus errata and ecn June 4, 2010 � Battery Charging Specification (available from USB-IF) -- Revision 1.2, December 7, 2010 -- Portable device only

4.9 Timers
This section provide information on timers.

4.9.1 Pulse Width Modulator (PWM) characteristics

This section describes the electrical information of the PWM.
Table 65. PWM timing parameters

Parameter

Symbo

Min

Typ

Max

PWM Clock Frequency Power-up Time

120

tpu

Unit MHz s

4.9.2 Quad timer timing
Table 66 listed the timing parameters.

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Electrical characteristics

Table 66. Quad Timer Timing

Characteristic

Symbo

Min1

Max

Timer input period

TIN

2T + 6

Timer input high/low period

TINHL

1T + 3

Timer output period

TOUT

Timer output high/low period

TOUTHL

16.7

1 T = clock cycle. For 60 MHz operation, T = 16.7 ns.

Unit ns ns ns ns

4IMER)NPUTS 4 ).

4).(,

See Figure

4IMER/UTPUTS

4 /54

4 /54(,

Figure 48. Quad timer timing

4 /54(,

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Boot mode configuration
5 Boot mode configuration
This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation.

5.1 Boot mode configuration pins
Table 67 provides boot options, functionality, fuse values, and associated pins. Several input pins are also sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse. The boot option pins are in effect when BT_FUSE_SEL fuse is `0' (cleared, which is the case for an unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX RT1020 Fuse Map document and the System Boot chapter in i.MX RT1020 Reference Manual (IMXRT1020RM).
Table 67. Fuses and associated pins used for boot

Pad GPIO_EMC_16 GPIO_EMC_17 GPIO_EMC_18 GPIO_EMC_19 GPIO_EMC_20 GPIO_EMC_21 GPIO_EMC_22 GPIO_EMC_23 GPIO_EMC_24 GPIO_EMC_25 GPIO_EMC_26 GPIO_EMC_27

Default setting on reset 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down 100 K pull-down

eFuse name src.BOOT_MODE0 src.BOOT_MODE1 src.BT_CFG[0] src.BT_CFG[1] src.BT_CFG[2] src.BT_CFG[3] src.BT_CFG[4] src.BT_CFG[5] src.BT_CFG[6] src.BT_CFG[7] src.BT_CFG[8] src.BT_CFG[9]

Details
Boot Options, Pin value overrides fuse settings for BT_FUSE_SEL = `0'. Signal Configuration as Fuse Override Input at Power Up. These are special I/O lines that control the boot up configuration during product development. In production, the boot configuration can be controlled by fuses.

5.2 Boot device interface allocation
The following tables list the interfaces that can be used by the boot process in accordance with the specific boot mode configuration. The tables also describe the interface's specific modes and IOMUXC allocation, which are configured during boot when appropriate.
Table 68. Boot trough NAND

PAD Name GPIO_EMC_00 GPIO_EMC_01 GPIO_EMC_02 GPIO_EMC_03 GPIO_EMC_04

IO Function semc.DATA[0] semc.DATA[1] semc.DATA[2] semc.DATA[3] semc.DATA[4]

ALT ALT 0 ALT 0 ALT 0 ALT 0 ALT 0

Comments -- -- -- -- --

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Boot mode configuration
GPIO_EMC_05 GPIO_EMC_06 GPIO_EMC_07 GPIO_EMC_32 GPIO_EMC_33 GPIO_EMC_34 GPIO_EMC_35 GPIO_EMC_36 GPIO_EMC_37 GPIO_EMC_38 GPIO_EMC_39 GPIO_EMC_25 GPIO_EMC_26 GPIO_EMC_27 GPIO_EMC_14 GPIO_EMC_40
PAD Name GPIO_EMC_00 GPIO_EMC_01 GPIO_EMC_02 GPIO_EMC_03 GPIO_EMC_04 GPIO_EMC_05 GPIO_EMC_06 GPIO_EMC_07 GPIO_EMC_32 GPIO_EMC_33 GPIO_EMC_34 GPIO_EMC_35 GPIO_EMC_36 GPIO_EMC_37

Table 68. Boot trough NAND

semc.DATA[5] semc.DATA[6] semc.DATA[7] semc.DATA[8] semc.DATA[9] semc.DATA[10] semc.DATA[11] semc.DATA[12] semc.DATA[13] semc.DATA[14] semc.DATA[15] semc.ADDR[9] semc.ADDR[11] semc.ADDR[12] semc.BA1 semc.CSX[0]

ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0

Table 69. Boot trough NOR
IO Function semc.DATA[0] semc.DATA[1] semc.DATA[2] semc.DATA[3] semc.DATA[4] semc.DATA[5] semc.DATA[6] semc.DATA[7] semc.DATA[8] semc.DATA[9] semc.DATA[10] semc.DATA[11] semc.DATA[12] semc.DATA[13]

ALT ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0

-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Comments -- -- -- -- -- -- -- -- -- -- -- -- -- --

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GPIO_EMC_38 GPIO_EMC_39 GPIO_EMC_16 GPIO_EMC_17 GPIO_EMC_18 GPIO_EMC_19 GPIO_EMC_20 GPIO_EMC_21 GPIO_EMC_22 GPIO_EMC_23 GPIO_EMC_26 GPIO_EMC_27 GPIO_EMC_13 GPIO_EMC_14 GPIO_EMC_40
PAD Name GPIO_SD_B1_00 GPIO_SD_B1_03 GPIO_SD_B1_04 GPIO_SD_B1_02 GPIO_SD_B1_01 GPIO_SD_B0_05 GPIO_SD_B0_04 GPIO_SD_B0_01 GPIO_SD_B1_05 GPIO_SD_B1_11 GPIO_SD_B0_00 GPIO_SD_B1_07 GPIO_SD_B1_08 GPIO_SD_B1_10 GPIO_SD_B1_09 GPIO_SD_B1_06

Table 69. Boot trough NOR semc.DATA[14] semc.DATA[15] semc.ADDR[0] semc.ADDR[1] semc.ADDR[2] semc.ADDR[3] semc.ADDR[4] semc.ADDR[5] semc.ADDR[6] semc.ADDR[7] semc.ADDR[11] semc.ADDR[12] semc.BA0 semc.BA1 semc.CSX[0]

ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0

Boot mode configuration
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --

Table 70. Boot through FlexSPI

IO Function

Mux Mode

flexspi.B_DATA[3] flexspi.B_DATA[2] flexspi.B_DATA[1] flexspi.B_DATA[0] flexspi.B_SCLK flexspi.B_DQS flexspi.B_SS0_B flexspi.B_SS1_B flexspi.A_DQS flexspi.A_SS0_B flexspi.A_SS1_B flexspi.A_SCLK flexspi.A_DATA[0] flexspi.A_DATA[1] flexspi.A_DATA[2] flexspi.A_DATA[3]

ALT 1 ALT 1 ALT 1 ALT 1 ALT 1 ALT 6 ALT 6 ALT 6 ALT 1 ALT 1 ALT 6 ALT 1 ALT 1 ALT 1 ALT 1 ALT 1

Comments -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

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Boot mode configuration
PAD Name GPIO_AD_B1_00 GPIO_AD_B1_01 GPIO_AD_B1_02 GPIO_AD_B1_03 GPIO_AD_B1_04 GPIO_AD_B1_05
PAD Name GPIO_AD_B1_13
PAD Name GPIO_SD_B0_06 GPIO_AD_B0_04 GPIO_AD_B1_07 GPIO_AD_B1_06 GPIO_SD_B0_02 GPIO_SD_B0_03 GPIO_SD_B0_04 GPIO_SD_B0_05 GPIO_SD_B0_00 GPIO_SD_B0_01
PAD Name GPIO_SD_B1_06 GPIO_AD_B1_13 GPIO_SD_B1_07 GPIO_SD_B1_02 GPIO_SD_B1_03 GPIO_SD_B1_04 GPIO_SD_B1_05

Table 71. Boot through FlexSPI (second option)

IO Function flexspi.A_DATA[3] flexspi.A_SCLK flexspi.A_DATA[0] flexspi.A_DATA[2] flexspi.A_DATA[1] flexspi.A_SS0_B

ALT 1 ALT 1 ALT 1 ALT 1 ALT 1 ALT 1

Mux Mode

Table 72. FlexSPI reset

IO Function gpio1.IO[29]

ALT 5

Mux Mode

Table 73. Boot through SD1

IO Function usdhc1.CD_B usdhc1.WP usdhc1.VSELECT usdhc1.RESET_B usdhc1.CMD usdhc1.CLK usdhc1.DATA0 usdhc1.DATA1 usdhc1.DATA2 usdhc1.DATA3

ALT 0 ALT 2 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0

Mux Mode

Table 74. Boot through SD2

IO Function usdhc2.CD_B usdhc2.WP usdhc2.RESET_B usdhc2.CMD usdhc2.CLK usdhc2.DATA0 usdhc2.DATA1

ALT 0 ALT 3 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0

Mux Mode

Comments -- -- -- -- -- --
Comments --
Comments -- -- -- -- -- -- -- -- -- --
Comments -- -- -- -- -- -- --

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PAD Name GPIO_SD_B1_00 GPIO_SD_B1_01 GPIO_SD_B1_08 GPIO_SD_B1_09 GPIO_SD_B1_10 GPIO_SD_B1_11
PAD Name GPIO_AD_B0_10 GPIO_AD_B0_11 GPIO_AD_B0_12 GPIO_AD_B0_13

Boot mode configuration

Table 74. Boot through SD2 (continued)

IO Function usdhc2.DATA2 usdhc2.DATA3 usdhc2.DATA4 usdhc2.DATA5 usdhc2.DATA6 usdhc2.DATA7

ALT 0 ALT 0 ALT 0 ALT 0 ALT 0 ALT 0

Mux Mode

Comments -- -- -- -- -- --

Table 75. Boot through SPI-1

IO Function lpspi1.SCK lpspi1.PCS0 lpspi1.SDO lpspi1.SDI

ALT 1 ALT 1 ALT 1 ALT 1

Mux Mode

Comments -- -- -- --

PAD Name GPIO_SD_B1_07 GPIO_SD_B1_08 GPIO_SD_B1_09 GPIO_SD_B1_06
PAD Name GPIO_AD_B1_12 GPIO_AD_B1_13 GPIO_AD_B1_14 GPIO_AD_B1_15
PAD Name GPIO_EMC_32 GPIO_EMC_33

Table 76. Boot through SPI-2

IO Function lpspi2.SCK lpspi2.SDO lpspi2.SDI lpspi2.PCS0

ALT 4 ALT 4 ALT 4 ALT 4

Mux Mode

Table 77. Boot through SPI-3

IO Function lpspi3.SCK lpspi3.PCS0 lpspi3.SDO lpspi3.SDI

ALT 2 ALT 2 ALT 2 ALT 2

Mux Mode

Table 78. Boot through SPI-4

IO Function lpspi4.SCK lpspi4.PCS0

ALT 4 ALT 4

Mux Mode

Comments -- -- -- --
Comments -- -- -- --
Comments -- --

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Boot mode configuration
PAD Name GPIO_EMC_34 GPIO_EMC_35
PAD Name GPIO_EMC_28 GPIO_EMC_41
PAD Name GPIO_AD_B0_06 GPIO_AD_B0_07 GPIO_AD_B0_08 GPIO_AD_B0_09
PAD Name GPIO_AD_B1_06 GPIO_AD_B1_07 GPIO_AD_B1_08 GPIO_AD_B1_09

Table 78. Boot through SPI-4 (continued)

IO Function lpspi4.SDO lpspi4.SDI

ALT 4 ALT 4

Mux Mode

Table 79. Boot through SEMC

IO Function

Mux Mode

semc.DQS semc.RDY

ALT 0 ALT 0

Table 80. Boot through UART1

IO Function lpuart1.TX lpuart1.RX lpuart1.CTS_B lpuart1.RTS_B

ALT 2 ALT 2 ALT 2 ALT 2

Mux Mode

Table 81. Boot through UART2

IO Function lpuart2.CTS_B lpuart2.RTS_B lpuart2.TX lpuart2.RX

ALT 2 ALT 2 ALT 2 ALT 2

Mux Mode

Comments -- --
Comments -- --
Comments -- -- -- --
Comments -- -- -- --

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Package information and contact assignments
6 Package information and contact assignments
This section includes the contact assignment information and mechanical package drawing.
6.1 20 x 20 mm package information
6.1.1 20 x 20 mm, 0.5 mm pitch, ball matrix
Figure 49 shows the top, bottom, and side views of the 20 x 20 mm LQFP package.

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Package information and contact assignments

69 /9 9 &9 9 !9

.',9
9 ',!"79

69 9 2'.19 /9
9 9 9 !9
9

69 /9
99

.*,"9

Figure 49. 20 x 20 mm LQFP, case x package top and side views

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Package information and contact assignments

6.1.2 20 x 20 mm supplies contact assignments and functional contact assignments
Table 82 shows the device connection list for ground, sense, and reference contact signals.
Table 82. 20 x 20 mm supplies contact Assignment

Supply Rail Name

Pin(s) Position(s)

DCDC_IN DCDC_IN_Q DCDC_GND DCDC_LP DCDC_PSWITCH GPANAIO NGND_KEL0 NVCC_GPIO NVCC_PLL NVCC_SD0 VDDA_ADC_3P3 VDD_HIGH_CAP VDD_HIGH_IN VDD_SNVS_CAP VDD_SNVS_IN VDD_SOC_IN VDD_USB_CAP VSS

34 38 35 36 37 71 64 11, 20, 29, 77, 104, 112, 144 72 44 73 65 69 56 55 5, 31, 39, 86, 102, 114, 134 61 6, 40, 60, 70, 85, 103, 113, 135

Remark -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

Table 83 shows an alpha-sorted list of functional contact assignments for the 20 x 20 mm package.
Table 83. 20 x 20 mm functional contact assignments

Pin Name GPIO_AD_B0_00 GPIO_AD_B0_01 GPIO_AD_B0_02

20 x 20 Pin

Power Group

111

NVCC_GPIO

110

NVCC_GPIO

109

NVCC_GPIO

Pin Type

Default Mode

Default Setting

Default Function

Input/ Output

Value

Digital GPIO
Digital GPIO
Digital GPIO

ALT0 ALT0 ALT0

jtag_mux.TMS jtag_mux.TCK jtag_mux.MOD

Input 47 K PU Input 100 K PD Input 100 K PD

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Package information and contact assignments

GPIO_AD_B0_03 GPIO_AD_B0_04 GPIO_AD_B0_05 GPIO_AD_B0_06 GPIO_AD_B0_07 GPIO_AD_B0_08 GPIO_AD_B0_09 GPIO_AD_B0_10 GPIO_AD_B0_11 GPIO_AD_B0_12 GPIO_AD_B0_13 GPIO_AD_B0_14 GPIO_AD_B0_15 GPIO_AD_B1_00 GPIO_AD_B1_01 GPIO_AD_B1_02 GPIO_AD_B1_03 GPIO_AD_B1_04 GPIO_AD_B1_05 GPIO_AD_B1_06 GPIO_AD_B1_07

Table 83. 20 x 20 mm functional contact assignments (continued)

108

NVCC_GPIO

Digital ALT0 jtag_mux.TDI

GPIO

107

NVCC_GPIO

Digital ALT0 jtag_mux.TDO

GPIO

106

NVCC_GPIO

Digital ALT0 jtag_mux.TRSTB

GPIO

105

NVCC_GPIO

Digital ALT5 GPIO1.IO[6]

GPIO

101

NVCC_GPIO

Digital ALT5 GPIO1.IO[7]

GPIO

100

NVCC_GPIO

Digital ALT5 GPIO1.IO[8]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[9]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[10]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[11]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[12]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[13]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[14]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[15]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[16]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[17]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[18]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[19]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[20]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[21]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[22]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[23]

GPIO

Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input

47 K PU Keeper 47 K PU Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper

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GPIO_AD_B1_08 GPIO_AD_B1_09 GPIO_AD_B1_10 GPIO_AD_B1_11 GPIO_AD_B1_12 GPIO_AD_B1_13 GPIO_AD_B1_14 GPIO_AD_B1_15 GPIO_EMC_00 GPIO_EMC_01 GPIO_EMC_02 GPIO_EMC_03 GPIO_EMC_041 GPIO_EMC_05 GPIO_EMC_06 GPIO_EMC_07 GPIO_EMC_08 GPIO_EMC_09 GPIO_EMC_10 GPIO_EMC_11 GPIO_EMC_12

Package information and contact assignments

Table 83. 20 x 20 mm functional contact assignments (continued)

NVCC_GPIO

Digital ALT5 GPIO1.IO[24]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[25]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[26]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[27]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[28]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[29]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[30]

GPIO

NVCC_GPIO

Digital ALT5 GPIO1.IO[31]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[0]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[1]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[2]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[3]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[4]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[5]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[6]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[7]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[8]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[9]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[10]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[11]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[12]

GPIO

Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input

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Package information and contact assignments

GPIO_EMC_13 GPIO_EMC_14 GPIO_EMC_15 GPIO_EMC_16 GPIO_EMC_17 GPIO_EMC_18 GPIO_EMC_19 GPIO_EMC_20 GPIO_EMC_21 GPIO_EMC_22 GPIO_EMC_23 GPIO_EMC_24 GPIO_EMC_25 GPIO_EMC_26 GPIO_EMC_27 GPIO_EMC_28 GPIO_EMC_29 GPIO_EMC_30 GPIO_EMC_31 GPIO_EMC_32 GPIO_EMC_33

Table 83. 20 x 20 mm functional contact assignments (continued)

NVCC_GPIO

Digital ALT5 GPIO2.IO[13]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[14]

GPIO

143

NVCC_GPIO

Digital ALT5 GPIO2.IO[15]

GPIO

142

NVCC_GPIO

Digital ALT6 SRC_BOOT_MODE0

GPIO

141

NVCC_GPIO

Digital ALT6 SRC_BOOT_MODE1

GPIO

140

NVCC_GPIO

Digital ALT5 GPIO2.IO[18]

GPIO

139

NVCC_GPIO

Digital ALT5 GPIO2.IO[19]

GPIO

138

NVCC_GPIO

Digital ALT5 GPIO2.IO[20]

GPIO

137

NVCC_GPIO

Digital ALT5 GPIO2.IO[21]

GPIO

136

NVCC_GPIO

Digital ALT5 GPIO2.IO[22]

GPIO

133

NVCC_GPIO

Digital ALT5 GPIO2.IO[23]

GPIO

132

NVCC_GPIO

Digital ALT5 GPIO2.IO[24]

GPIO

131

NVCC_GPIO

Digital ALT5 GPIO2.IO[25]

GPIO

130

NVCC_GPIO

Digital ALT5 GPIO2.IO[26]

GPIO

129

NVCC_GPIO

Digital ALT5 GPIO2.IO[27]

GPIO

128

NVCC_GPIO

Digital ALT5 GPIO2.IO[28]

GPIO

127

NVCC_GPIO

Digital ALT5 GPIO2.IO[29]

GPIO

126

NVCC_GPIO

Digital ALT5 GPIO2.IO[30]

GPIO

125

NVCC_GPIO

Digital ALT5 GPIO2.IO[31]

GPIO

124

NVCC_GPIO

Digital ALT5 GPIO3.IO[0]

GPIO

123

NVCC_GPIO

Digital ALT5 GPIO3.IO[1]

GPIO

Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input

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GPIO_EMC_34 GPIO_EMC_35 GPIO_EMC_36 GPIO_EMC_37 GPIO_EMC_38 GPIO_EMC_39 GPIO_EMC_40 GPIO_EMC_41 GPIO_SD_B0_00 GPIO_SD_B0_01 GPIO_SD_B0_02 GPIO_SD_B0_03 GPIO_SD_B0_04 GPIO_SD_B0_05 GPIO_SD_B0_06 GPIO_SD_B1_00 GPIO_SD_B1_01 GPIO_SD_B1_02 GPIO_SD_B1_03 GPIO_SD_B1_04 GPIO_SD_B1_05

Package information and contact assignments

Table 83. 20 x 20 mm functional contact assignments (continued)

122

NVCC_GPIO

Digital ALT5 GPIO3.IO[2]

GPIO

121

NVCC_GPIO

Digital ALT5 GPIO3.IO[3]

GPIO

120

NVCC_GPIO

Digital ALT5 GPIO3.IO[4]

GPIO

119

NVCC_GPIO

Digital ALT5 GPIO3.IO[5]

GPIO

118

NVCC_GPIO

Digital ALT5 GPIO3.IO[6]

GPIO

117

NVCC_GPIO

Digital ALT5 GPIO3.IO[7]

GPIO

116

NVCC_GPIO

Digital ALT5 GPIO3.IO[8]

GPIO

115

NVCC_GPIO

Digital ALT5 GPIO3.IO[9]

GPIO

NVCC_SD0

Digital ALT5 GPIO3.IO[13]

GPIO

NVCC_SD0

Digital ALT5 GPIO3.IO[14]

GPIO

NVCC_SD0

Digital ALT5 GPIO3.IO[15]

GPIO

NVCC_SD0

Digital ALT5 GPIO3.IO[16]

GPIO

NVCC_SD0

Digital ALT5 GPIO3.IO[17]

GPIO

NVCC_SD0

Digital ALT5 GPIO3.IO[18]

GPIO

NVCC_SD0

Digital ALT5 GPIO3.IO[19]

GPIO

NVCC_GPIO

Digital ALT5 GPIO3.IO[20]

GPIO

NVCC_GPIO

Digital ALT5 GPIO3.IO[21]

GPIO

NVCC_GPIO

Digital ALT5 GPIO3.IO[22]

GPIO

NVCC_GPIO

Digital ALT5 GPIO3.IO[23]

GPIO

NVCC_GPIO

Digital ALT5 GPIO3.IO[24]

GPIO

NVCC_GPIO

Digital ALT5 GPIO3.IO[25]

GPIO

Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input

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Package information and contact assignments

GPIO_SD_B1_06 GPIO_SD_B1_07 GPIO_SD_B1_08 GPIO_SD_B1_09 GPIO_SD_B1_10 GPIO_SD_B1_11 ONOFF PMIC_ON_REQ PMIC_STBY_REQ

Table 83. 20 x 20 mm functional contact assignments (continued)

NVCC_GPIO

Digital ALT5 GPIO3.IO[26]

GPIO

NVCC_GPIO

Digital ALT5 GPIO3.IO[27]

GPIO

NVCC_GPIO

Digital ALT5 GPIO3.IO[28]

GPIO

NVCC_GPIO

Digital ALT5 GPIO3.IO[29]

GPIO

NVCC_GPIO

Digital ALT5 GPIO3.IO[30]

GPIO

NVCC_GPIO

Digital ALT5 GPIO3.IO[31]

GPIO

VDD_SNVS_IN Digital ALT0 src.RESET_B

GPIO

VDD_SNVS_IN Digital ALT0 snvs_lp.PMIC_ON_REQ

GPIO

VDD_SNVS_IN Digital ALT0 ccm.PMIC_VSTBY_REQ

GPIO

POR_B

VDD_SNVS_IN Digital ALT0

GPIO

RTC_XTALI

RTC_XTALO

TEST_MODE

VDD_SNVS_IN Digital ALT0

GPIO

USB_OTG1_CHD_B

USB_OTG1_DN

USB_OTG1_DP

USB_OTG1_VBUS

XTALI

XTALO

WAKEUP

VDD_SNVS_IN Digital ALT5

GPIO

1 This pin output is in a high level until the system reset is complete.

src.POR_B
-- -- tcu.TEST_MODE
-- -- -- -- -- -- GPIO5.IO[0]

Input Keeper

Input 100 K PU

Output 100 K PU (PKE disabled)
Input 100 K PU

-- -- Input

-- -- 100 K PD

-- -- -- -- -- -- Input

-- -- -- -- -- -- 100 K PU

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 3, 08/2021

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Package information and contact assignments
6.1.3 20 x 20 mm package pin assignments
Figure 50 shows the pin assignments of the 20 x 20 mm package.

144 NVCC_GPIO 143 GPIO_EMC_15 142 GPIO_EMC_16 141 GPIO_EMC_17 140 GPIO_EMC_18 139 GPIO_EMC_19 138 GPIO_EMC_20 137 GPIO_EMC_21 136 GPIO_EMC_22 135 VSS 134 VDD_SOC_IN 133 GPIO_EMC_23 132 GPIO_EMC_24 131 GPIO_EMC_25 130 GPIO_EMC_26 129 GPIO_EMC_27 128 GPIO_EMC_28 127 GPIO_EMC_29 126 GPIO_EMC_30 125 GPIO_EMC_31 124 GPIO_EMC_32 123 GPIO_EMC_33 122 GPIO_EMC_34 121 GPIO_EMC_35 120 GPIO_EMC_36 119 GPIO_EMC_37 118 GPIO_EMC_38 117 GPIO_EMC_39 116 GPIO_EMC_40 115 GPIO_EMC_41 114 VDD_SOC_IN 113 VSS 112 NVCC_GPIO 111 GPIO_AD_B0_00 110 GPIO_AD_B0_01 109 GPIO_AD_B0_02

GPIO_EMC_14 1 GPIO_EMC_13 2 GPIO_EMC_12 3 GPIO_EMC_11 4
VDD_SOC_IN 5 VSS 6
GPIO_EMC_10 7 GPIO_EMC_09 8 GPIO_EMC_08 9 GPIO_EMC_07 10
NVCC_GPIO 11 GPIO_EMC_06 12 GPIO_EMC_05 13 GPIO_EMC_04 14 GPIO_EMC_03 15 GPIO_EMC_02 16 GPIO_EMC_01 17 GPIO_EMC_00 18 GPIO_SD_B1_11 19
NVCC_GPIO 20 GPIO_SD_B1_10 21 GPIO_SD_B1_09 22 GPIO_SD_B1_08 23 GPIO_SD_B1_07 24 GPIO_SD_B1_06 25 GPIO_SD_B1_05 26 GPIO_SD_B1_04 27 GPIO_SD_B1_03 28
NVCC_GPIO 29 GPIO_SD_B1_02 30
VDD_SOC_IN 31 GPIO_SD_B1_01 32 GPIO_SD_B1_00 33
DCDC_IN 34 DCDC_GND 35
DCDC_LP 36

108 GPIO_AD_B0_03 107 GPIO_AD_B0_04 106 GPIO_AD_B0_05 105 GPIO_AD_B0_06 104 NVCC_GPIO 103 VSS 102 VDD_SOC_IN 101 GPIO_AD_B0_07 100 GPIO_AD_B0_08
99 GPIO_AD_B0_09 98 GPIO_AD_B0_10 97 GPIO_AD_B0_11 96 GPIO_AD_B0_12 95 GPIO_AD_B0_13 94 GPIO_AD_B0_14 93 GPIO_AD_B0_15 92 GPIO_AD_B1_00 91 GPIO_AD_B1_01 90 GPIO_AD_B1_02 89 GPIO_AD_B1_03 88 GPIO_AD_B1_04 87 GPIO_AD_B1_05 86 VDD_SOC_IN 85 VSS 84 GPIO_AD_B1_06 83 GPIO_AD_B1_07 82 GPIO_AD_B1_08 81 GPIO_AD_B1_09 80 GPIO_AD_B1_10 79 GPIO_AD_B1_11 78 GPIO_AD_B1_12 77 NVCC_GPIO 76 GPIO_AD_B1_13 75 GPIO_AD_B1_14 74 GPIO_AD_B1_15 73 VDDA_ADC_3P3

DCDC_PSWITCH 37 DCDC_IN_Q 38
VDD_SOC_IN 39 VSS 40
GPIO_SD_B0_06 41 GPIO_SD_B0_05 42 GPIO_SD_B0_04 43
NVCC_SD0 44 GPIO_SD_B0_03 45 GPIO_SD_B0_02 46 GPIO_SD_B0_01 47 GPIO_SD_B0_00 48
ONOFF 49 POR_B 50 TEST_MODE 51 WAKEUP 52 PMIC_ON_REQ 53 PMIC_STBY_REQ 54 VDD_SNVS_IN 55 VDD_SNVS_CAP 56 RTC_XTALI 57 RTC_XTALO 58 USB_OTG1_VBUS 59
VSS 60 VDD_USB_CAP 61 USB_OTG1_DN 62 USB_OTG1_DP 63
NGND_KEL0 64 VDD_HIGH_CAP 65 USB_OTG1_CHD_B 66
XTALI 67 XTALO 68 VDD_HIGH_IN 69
VSS 70 GPANAIO 71 NVCC_PLL 72

Figure 50. The pin assignments of the 20 x 20 mm package

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 3, 08/2021

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Package information and contact assignments
6.2 14 x 14 mm package information
6.2.1 14 x 14 mm, 0.5 mm pitch, ball matrix
Figure 51 shows the top and side views of the 14 x 14 mm LQFP package.

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 3, 08/2021

NXP Semiconductors

EM 3M M %M M M 7'0M M '0FKM

Package information and contact assignments EM M <'6:M 3M M M M M

A'DM L

EM I
MJM MMJ

:<'0#M 6+0M

Figure 51. 14 x 14 mm LQFP, case x package top and side Views

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 3, 08/2021

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Package information and contact assignments

6.2.2 14 x 14 mm supplies contact assignments and functional contact assignments
Table 84 shows the device connection list for ground, sense, and reference contact signals.
Table 84. 14 x 14 mm supplies contact assignment

Supply Rail Name

Pin(s) Position(s)

DCDC_IN DCDC_IN_Q DCDC_GND DCDC_LP DCDC_PSWITCH NVCC_GPIO NGND_KEL0 NVCC_PLL VDD_HIGH_CAP VDD_HIGH_IN VDD_SNVS_CAP VDD_SNVS_IN VDD_SOC_IN VDD_USB_CAP VDDA_ADC_3P3 VSS

23 27 24 25 26 5, 20, 58, 71, 80, 95 43 50 44 48 35 34 18, 28, 69, 81, 91 40 51 19, 29, 39, 49, 59, 70, 79, 92

Remark -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

Table 85 shows an alpha-sorted list of functional contact assignments for the 14 x 14 mm package.
Table 85. 14 x 14 mm functional contact assignments

Pin Name
GPIO_AD_B0_00 GPIO_AD_B0_01 GPIO_AD_B0_02 GPIO_AD_B0_03 GPIO_AD_B0_04

14 x 14 Pin

Power Group

NVCC_GPIO

Pin Type
Digital GPIO
Digital GPIO
Digital GPIO
Digital GPIO
Digital GPIO

Default Setting

Default Mode

Default Function

ALT0 jtag_mux.TMS

Input/ Output

Value

Input 47 K PU

ALT0 jtag_mux.TCK

Input 100 K PD

ALT0 jtag_mux.MOD

Input 100 K PD

ALT0 jtag_mux.TDI

Input 47 K PU

ALT0 jtag_mux.TDO

Input Keeper

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 3, 08/2021

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GPIO_AD_B0_05 GPIO_AD_B0_06 GPIO_AD_B0_07 GPIO_AD_B0_08 GPIO_AD_B0_09 GPIO_AD_B0_10 GPIO_AD_B0_11 GPIO_AD_B0_12 GPIO_AD_B0_13 GPIO_AD_B0_14 GPIO_AD_B0_15 GPIO_AD_B1_10 GPIO_AD_B1_11 GPIO_AD_B1_12 GPIO_AD_B1_13 GPIO_AD_B1_14 GPIO_AD_B1_15 GPIO_EMC_041 GPIO_EMC_05 GPIO_EMC_06 GPIO_EMC_07

Package information and contact assignments

Table 85. 14 x 14 mm functional contact assignments (continued)

NVCC_GPIO

Digital GPIO

ALT0 jtag_mux.TRSTB

NVCC_GPIO

Digital GPIO
Digital GPIO
Digital GPIO

ALT5 GPIO1.IO[6] ALT5 GPIO1.IO[7] ALT5 GPIO1.IO[8]

NVCC_GPIO

Digital GPIO
Digital GPIO

ALT5 GPIO1.IO[9] ALT5 GPIO1.IO[10]

NVCC_GPIO

Digital GPIO
Digital GPIO

ALT5 GPIO1.IO[11] ALT5 GPIO1.IO[12]

NVCC_GPIO

Digital GPIO
Digital GPIO

ALT5 GPIO1.IO[13] ALT5 GPIO1.IO[14]

NVCC_GPIO

Digital GPIO
Digital GPIO
Digital GPIO

ALT5 GPIO1.IO[15] ALT5 GPIO1.IO[26] ALT5 GPIO1.IO[27]

NVCC_GPIO

Digital GPIO
Digital GPIO

ALT5 GPIO1.IO[28] ALT5 GPIO1.IO[29]

NVCC_GPIO

Digital GPIO
Digital GPIO

ALT5 GPIO1.IO[30] ALT5 GPIO1.IO[31]

NVCC_GPIO

Digital ALT5 GPIO2.IO[4]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[5]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[6]

GPIO

NVCC_GPIO

Digital ALT5 GPIO2.IO[7]

GPIO

Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input

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Package information and contact assignments

GPIO_EMC_08 GPIO_EMC_09 GPIO_EMC_16 GPIO_EMC_17 GPIO_EMC_18 GPIO_EMC_19 GPIO_EMC_20 GPIO_EMC_21 GPIO_EMC_22 GPIO_EMC_23 GPIO_EMC_24 GPIO_EMC_25 GPIO_EMC_26 GPIO_EMC_27 GPIO_EMC_32 GPIO_EMC_33 GPIO_EMC_34 GPIO_EMC_35 GPIO_SD_B1_00 GPIO_SD_B1_01 GPIO_SD_B1_02

Table 85. 14 x 14 mm functional contact assignments (continued)

NVCC_GPIO

Digital ALT5 GPIO2.IO[8]

GPIO

NVCC_GPIO

100 NVCC_GPIO

NVCC_GPIO

Digital GPIO
Digital GPIO
Digital GPIO

ALT5 GPIO2.IO[9] ALT6 src.BOOT_MODE[0] ALT6 src.BOOT_MODE[1]

NVCC_GPIO

Digital GPIO
Digital GPIO

ALT5 GPIO2.IO[18] ALT5 GPIO2.IO[19]

NVCC_GPIO

Digital GPIO
Digital GPIO

ALT5 GPIO2.IO[20] ALT5 GPIO2.IO[21]

NVCC_GPIO

Digital GPIO
Digital GPIO

ALT5 GPIO2.IO[22] ALT5 GPIO2.IO[23]

NVCC_GPIO

Digital GPIO
Digital GPIO
Digital GPIO

ALT5 GPIO2.IO[24] ALT5 GPIO2.IO[25] ALT5 GPIO2.IO[26]

NVCC_GPIO

Digital GPIO
Digital GPIO

ALT5 GPIO2.IO[27] ALT5 GPIO3.IO[0]

NVCC_GPIO

Digital GPIO
Digital GPIO

ALT5 GPIO3.IO[1] ALT5 GPIO3.IO[2]

NVCC_GPIO

Digital GPIO
Digital GPIO

ALT5 GPIO3.IO[3] ALT5 GPIO3.IO[20]

NVCC_GPIO

Digital GPIO

ALT5 GPIO3.IO[21]

NVCC_GPIO

Digital GPIO

ALT5 GPIO3.IO[22]

Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input

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Package information and contact assignments

Table 85. 14 x 14 mm functional contact assignments (continued)

GPIO_SD_B1_03 GPIO_SD_B1_04 GPIO_SD_B1_05 GPIO_SD_B1_06 GPIO_SD_B1_07 GPIO_SD_B1_08 GPIO_SD_B1_09 GPIO_SD_B1_10 GPIO_SD_B1_11

NVCC_GPIO

Digital GPIO
Digital GPIO
Digital GPIO
Digital GPIO
Digital GPIO
Digital GPIO
Digital GPIO
Digital GPIO
Digital GPIO

ALT5 GPIO3.IO[23] ALT5 GPIO3.IO[24] ALT5 GPIO3.IO[25] ALT5 GPIO3.IO[26] ALT5 GPIO3.IO[27] ALT5 GPIO3.IO[28] ALT5 GPIO3.IO[29] ALT5 GPIO3.IO[30] ALT5 GPIO3.IO[31]

Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper

ONOFF

VDD_SNVS_IN Digital ALT0

GPIO

PMIC_ON_REQ

VDD_SNVS_IN Digital ALT0

GPIO

POR_B

VDD_SNVS_IN Digital ALT0

GPIO

RTC_XTALI

RTC_XTALO

TEST_MODE

VDD_SNVS_IN Digital ALT0

GPIO

USB_OTG1_CHD_B

USB_OTG1_DN

USB_OTG1_DP

USB_OTG1_VBUS

XTALI

XTALO

1 This pin output is in a high level until the system reset is complete.

src.RESET_B

Input 100 K PU

snvs_lp.PMIC_ON_REQ Input 100 K PU

src.POR_B

Output 100 K PU

-- -- tcu.TEST_MODE

-- -- Input

-- -- 100 K PD

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 3, 08/2021

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Package information and contact assignments
6.2.3 14 x 14 mm package pin assignments
Figure 52 shows the pin assignments of the 14 x 14 mm package.

GPIO_AD_B0_02

GPIO_AD_B0_01

GPIO_AD_B0_00

NVCC_GPIO

VDD_SOC_IN

GPIO_EMC_35

GPIO_EMC_34

GPIO_EMC_33

GPIO_EMC_32

GPIO_EMC_27

GPIO_EMC_26

GPIO_EMC_25

GPIO_EMC_24

GPIO_EMC_23

VDD_SOC_IN

GPIO_EMC_22

GPIO_EMC_21

NVCC_GPIO

GPIO_EMC_20

GPIO_EMC_19

GPIO_EMC_18

GPIO_EMC_17

GPIO_EMC_16

VSS

100

GPIO_EMC_09

GPIO_EMC_08

GPIO_EMC_07

GPIO_EMC_06

NVCC_GPIO

GPIO_EMC_05

GPIO_EMC_04

GPIO_SD_B1_11

GPIO_SD_B1_10

GPIO_SD_B1_09

GPIO_SD_B1_08

GPIO_SD_B1_07

GPIO_SD_B1_06

GPIO_SD_B1_05

GPIO_SD_B1_04

GPIO_SD_B1_03

GPIO_SD_B1_02

VDD_SOC_IN

VSS

NVCC_GPIO

GPIO_SD_B1_01

GPIO_SD_B1_00

DCDC_IN

DCDC_GND

DCDC_LP

GPIO_AD_B0_03

GPIO_AD_B0_04

GPIO_AD_B0_05

GPIO_AD_B0_06

NVCC_GPIO

VSS

VDD_SOC_IN

GPIO_AD_B0_07

GPIO_AD_B0_08

GPIO_AD_B0_09

GPIO_AD_B0_10

GPIO_AD_B0_11

GPIO_AD_B0_12

GPIO_AD_B0_13

GPIO_AD_B0_14

GPIO_AD_B0_15

VSS

NVCC_GPIO

GPIO_AD_B1_10

GPIO_AD_B1_11

GPIO_AD_B1_12

GPIO_AD_B1_13

GPIO_AD_B1_14

GPIO_AD_B1_15

VDDA_ADC_3P3

NVCC_PLL

VSS

VDD_HIGH_IN

XTALO

XTALI

USB_OTG1_CHD_B

VDD_HIGH_CAP

NGND_KEL0

USB_OTG1_DP

USB_OTG1_DN

VDD_USB_CAP

VSS

USB_OTG1_VBUS

RTC_XTALO

RTC_XTALI

VDD_SNVS_CAP

VDD_SNVS_IN

PMIC_ON_REQ

TEST_MODE

POR_B

ONOFF

VSS

VDD_SOC_IN

DCDC_IN_Q

DCDC_PSWITCH

Figure 52. The pin assignments of the 14 x 14 mm package

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 3, 08/2021

NXP Semiconductors

Revision history

7 Revision history

Table 86 provides a revision history for this data sheet.
Table 86. i.MX RT1020 data sheet document revision history

Rev. Number

Date

Substantive Change(s)

Rev. 3 Rev. 2
Rev. 1

08/2021 � Added new part numbers for silicon Rev B in the Section 1.2, Ordering information

03/2021

� Updated the M7 core, external memory, and ADC descriptions in the Section 1.1, Features � Updated the Figure 1, "Part number nomenclature--i.MX RT10XX family" � Updated the baud rates of LPUART and frequency of RTC OSC in the Table 3 i.MX RT1020 modules
list � Updated the remarks of TEST_MODE in the Table 4, Special signal considerations � Added system and bus frequencies in the Table 11, Operating ranges; updated the junction
temperature descriptions in the Table 11, Operating ranges � Updated the test conditions and max current of DCDC_IN in the Table 13, Maximum supply currents � Added a note in the Section 4.2.1.1, Power-up sequence � Updated the value of reference clock in the Table 18, Ethernet PLL's electrical parameters � Added the high-level and low level output current in the Table 22, Single voltage GPIO DC parameters � Updated the frequency of operation and internal clock period in the Table 31, SEMC output timing in
ASYNC mode � Updated the frequency of operation and internal clock period in the Table 32, SEMC output timing in
SYNC mode � Added a footnote for GPIO_EMC_04 in the Table 83, 20 x 20 mm functional contact assignments and
Table 85, 14 x 14 mm functional contact assignments

04/2019

� Added analog descriptions in the Section 1.1, Features � Added ADC channel number in the Table 1, The comparison between 100 LQFP and 144 LQFP
package � Updated the RT website link in the Section 1.2, Ordering information � Updated the ADC descriptions in the Figure 2, "i.MX RT1020 system block diagram" � Updated the RAM size, SNVS descriptions, and USB descriptions in the Table 3, i.MX RT1020
modules list � Updated the on-chip termination values of JTAG_TCK and JTAG_MOD in the Table 5, JTAG controller
interface summary � Updated the maximum values of VDD_SOC_IN in the Table 8, Absolute maximum ratings � Removed the USB_OTG2_VBUS from the Table 8, Absolute maximum ratings, Table 11, Operating
ranges, and Section 4.2.1.1, Power-up sequence � Changed 528 MHz PLL to System PLL in the Table 17, System PLL's electrical parameters � Changed 480 MHz PLL to USB PLL in the Table 19, USB PLL's electrical parameters � Updated the Section 4.8.1, LPSPI timing parameters � Added the Figure 32, "Minimum Sample Time Vs Ras (Cas = 2pF)", Figure 33, "Minimum Sample
Time Vs Ras (Cas = 5 pF)", and Figure 34, "Minimum Sample Time Vs Ras (Cas = 10 pF)" in the Section 4.7.2, A/D converter

Rev. 0.1 07/2018 � Updated the Table 14, Low power mode current and power consumption � Added the Section 4.4.4, Debug trace timing specifications
Rev. 0 06/2018 � Initial version

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 3, 08/2021

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Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes - NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
Security -- Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer's applications and products. Customer's responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer's applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately.
Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.
Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
Suitability for use � Automotive Product (Functional Safety) Suitability for use in automotive applications --This NXP product has been qualified for use in automotive applications. It has been developed in accordance with ISO 26262, and has been ASIL-classified accordingly. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as "Critical
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Applications"), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys' fees) that NXP may incur related to customer's incorporation of any product in a Critical Application.
Non-automotive products for restricted use in automotive onlySuitability for use in automotive applications -- The use of this NXP Semiconductors product is restricted to automotive applications only. It has not been fully qualified for use in automotive applications. The customer of this NXP Semiconductors product therefore understands and accepts that:
� The Customer shall only use this NXP Semiconductors product for automotive applications.
� This product was not originally designed for automotive use. It will therefore, not be possible to achieve the levels of quality and failure analysis that are normally associated with products explicitly designed for automotive use.
� With respect to test-coverage, this product is not fully compliant to AEC-Q100.
� All product manufacturing locations are certified according to ISO/TS16949.
� Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect.
Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
Terms and conditions of commerical sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
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No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
Hazardous voltage -- Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V may appear when operating this product, depending on settings and application. Customers incorporating or otherwise using these products in applications where such high voltages may appear during operation, assembly, test etc. of such application, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages.
Bare die -- All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department.
Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
Evaluation products --This product is provided on an "as is" and "with all faults" basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages.
Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer's exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose.
Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX,EMBRACE, GREENCHIP, HITAG, ICODE, JCOP, LIFE, VIBES, MIFARE, MIFARE CLASSIC, MIFARE DESFire, MIFARE PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT, MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET, TRENCHMOS, UCODE, Freescale, the Freescale logo, CodeWarrior, ColdFire, ColdFire+, the Energy Efficient Solutions logo, Kinetis, Layerscape, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast, BeeKit, BeeStack, CoreNet, Flexis, MXC, Platform in a Package, QUICC Engine, Tower, TurboLink, EdgeScale, EdgeLock, eIQ, and Immersive3D are trademarks of NXP B.V. All other product or service names are the property of their respective owners. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight,
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Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, �Vision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. M, M Mobileye and other Mobileye trademarks or logos appearing herein are trademarks of Mobileye Vision Technologies Ltd. in the United States, the EU and/or other jurisdictions.

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Date of release: 08/2021 Document identifier: IMXRT1020IEC