HIP4080A Datasheet
80V/2.5A Peak, High Frequency Full Bridge FET Driver
HIP4080A, high frequency, medium voltage full bridge N-Channel FET driver IC, FET driver, charge pump, input comparator
Renesas Electronics Corporation
REN hip4080a DST 20040119 DATASHEET
HIP4080A
80V/2.5A Peak, High Frequency Full Bridge FET Driver
FN3658 Rev.8.00 Dec 11, 2019
The HIP4080A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4080A includes an input comparator, used to facilitate the "hysteresis" and PWM modes of operation. Its HEN (high enable) lead can force current to freewheel in the bottom two external power MOSFETs, maintaining the upper power MOSFETs off. Since it can switch at frequencies up to 1MHz, the HIP4080A is well suited for driving Voice Coil Motors, switching power amplifiers and power supplies.
HIP4080A can also drive medium voltage brush motors, and two HIP4080As can be used to drive high performance stepper motors, since the short minimum "on-time" can provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximize control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in precise control of the driven load.
The similar HIP4081A IC allows independent control of all 4 FETs in a Full Bridge configuration.
The Application Note for the HIP4080A is AN9404.
Ordering Information
PART NUMBER
TEMPERATURE
PACKAGE
PKG.
RANGE (°C) (RoHS Compliant) DWG. #
HIP4080AIPZ (Note 1)
-40 to +85
20 Ld PDIP
E20.3
HIP4080AIBZ (Note 1)
-40 to +85
20 Ld SOIC
M20.3
NOTES:
1. Intersil Pb-Free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-Free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J Std-020B.
2. Add "T" suffix for Tape and Reel packing option. HIP4080AIP not available in Tape and Reel.
Features
· Drives N-Channel FET Full Bridge Including High Side Chop Capability
· Bootstrap Supply Max Voltage to 95VDC
· Drives 1000pF Load at 1MHz in Free Air at +50°C with Rise and Fall Times of Typically 10ns
· User-Programmable Dead Time
· Charge-Pump and Bootstrap Maintain Upper Bias Supplies
· DIS (Disable) Pin Pulls Gates Low
· Input Logic Thresholds Compatible with 5V to 15V Logic Levels
· Very Low Power Consumption
· Undervoltage Protection
· Pb-Free (RoHS Compliant)
Applications
· Medium/Large Voice Coil Motors · Full Bridge Power Supplies · Switching Power Amplifiers · High Performance Motor Controls · Noise Cancellation Systems · Battery Powered Vehicles · Peripherals · U.P.S.
Pinout
HIP4080A (PDIP, SOIC)
TOP VIEW
BHB 1 HEN 2 DIS 3 VSS 4 OUT 5
IN+ 6 IN- 7 HDEL 8 LDEL 9 AHB 10
20 BHO 19 BHS 18 BLO 17 BLS 16 VDD 15 VCC 14 ALS 13 ALO 12 AHS 11 AHO
FN3658 Rev.8.00 Dec 11, 2019
Page 1 of 19
HIP4080A
Application Block Diagram
12V
BHO
BHS
HEN
BLO
DIS HIP4080A
IN+
ALO
IN-
AHS
AHO
GND
80V LOAD GND
Functional Block Diagram (1/2 HIP4080A)
UNDERVOLTAGE
VDD 16 HEN 2
CHARGE PUMP
DIS 3
LEVEL SHIFT AND LATCH
TURN-ON DELAY
OUT 5
IN+ 6
+
IN_ 7
-
HDEL 8
LDEL 9
VSS 4
TURN-ON DELAY
AHB 10
DRIVER
AHO
11
AHS 12
15 VCC
DRIVER
ALO
13
ALS 14
HIGH VOLTAGE BUS 80VDC CBS
DBS
TO VDD (PIN 16)
+12VDC BIAS
SUPPLY CBF
FN3658 Rev.8.00 Dec 11, 2019
Page 2 of 19
HIP4080A
Typical Application (Hysteresis Mode Switching)
1 BHB BHO 20
12V
2 HEN
BHS 19
DIS
3 DIS
BLO 18
HIP4080A/HIP4080
4 VSS
BLS 17
5 OUT
VDD 16
6V
6 IN+
VCC 15
12V
7 IN-
ALS 14
IN
8 HDEL ALO 13
9 LDEL AHS 12
10 AHB AHO 11
GND
-
+
6V
80V
LOAD
GND
FN3658 Rev.8.00 Dec 11, 2019
Page 3 of 19
HIP4080A
Absolute Maximum Ratings
Supply Voltage, VDD and VCC. . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25°C to 125°C) Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55°C to 125°C) Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHB . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD Voltage on ALO, BLO. . . . . . . . . . . . VALS, BLS -0.3V to VCC +0.3V Voltage on AHO, BHO . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns All Voltages relative to VSS, unless otherwise specified.
Operating Conditions
Supply Voltage, VDD and VCC. . . . . . . . . . . . . . . . . . +9.5V to +15V Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . VAHS, BHS +5V to VAHS, BHS +15V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . -500µA to -50µA Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
Thermal Information
Thermal Resistance (Typical, Note 3)
JA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Power Dissipation at +85°C
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470mW
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530mW
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Max. Junction Temperature. . . . . . . . . . . . . . . . . . +125°C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C
(For SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETERS
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25°C, Unless Otherwise Specified
TJ = +25°C
TJ = - 40°C TO +125°C
SYMBOL
TEST CONDITIONS
MIN TYP MAX MIN MAX UNITS
SUPPLY CURRENTS AND CHARGE PUMPS
VDD Quiescent Current
IDD
IN- = 2.5V, Other Inputs = 0V
8
11 14
7
14 mA
VDD Operating Current
IDDO
Outputs switching f = 500kHz, No Load
9
12 15
8
15 mA
VCC Quiescent Current
ICC
IN- = 2.5V, Other Inputs = 0V,
IALO = IBLO = 0
-
25 80
-
100 A
VCC Operating Current
ICCO
f = 500kHz, No Load
1 1.25 2.0 0.8
3
mA
AHB, BHB Quiescent Current Qpump Output Current
IAHB, IBHB
IN- = 2.5V, Other Inputs = 0V, IAHO = IBHO = 0, VDD = VCC =VAHB = VBHB = 10V
-50 -25 -11 -60 -10 A
AHB, BHB Operating Current
IAHBO, IBHBO
f = 500kHz, No Load
0.62 1.2 1.5 0.5 1.9 mA
AHS, BHS, AHB, BHB Leakage Current
IHLK
VBHS = VAHS = 80V, VAHB = VBHB = 93V
- 0.02 1.0
-
10
A
AHB-AHS, BHB-BHS Qpump Output Voltage
VAHB VAHS VBHB VBHS
IAHB = IAHB = 0, No Load
11.5 12.6 14.0 10.5 14.5 V
INPUT COMPARATOR PINS: IN+, IN-, OUT
Offset Voltage Input Bias Current Input Offset Current Input Common Mode Voltage Range
VOS IIB IOS
CMVR
Over Common Mode Voltage Range
-10
0
+10 -15 +15 mV
0
0.5
2
0
4
A
-1
0
+1
-2
+2
A
1
-
VDD
1
VDD
V
-1.5
-1.5
FN3658 Rev.8.00 Dec 11, 2019
Page 4 of 19
HIP4080A
Electrical Specifications
PARAMETERS
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25°C, Unless Otherwise Specified (Continued)
TJ = +25°C
TJ = - 40°C TO +125°C
SYMBOL
TEST CONDITIONS
MIN TYP MAX MIN MAX UNITS
Voltage Gain
AVOL
10 25
-
10
- V/mV
OUT High Level Output Voltage
VOH
IN+ > IN-, IOH = -250A
VDD
-
-
VDD
-
V
-0.4
- 0.5
OUT Low Level Output Voltage Low Level Output Current High Level Output Current INPUT PINS: DIS
VOL
IN+ < IN-, IOL = +250A
IOL
VOUT = 6V
IOH
VOUT = 6V
-
-
0.4
-
0.5
V
6.5 14 19
6
20 mA
-17 -10 -3 -20 -2.5 mA
Low Level Input Voltage High Level Input Voltage Input Voltage Hysteresis
VIL
Full Operating Conditions
VIH
Full Operating Conditions
-
-
1.0
-
0.8
V
2.5
-
-
2.7
-
V
-
35
-
-
-
mV
Low Level Input Current High Level Input Current INPUT PINS: HEN
IIL
VIN = 0V, Full Operating Conditions
IIH
VIN = 5V, Full Operating Conditions
-130 -100 -75 -135 -65 A
-1
-
+1 -10 +10 A
Low Level Input Voltage High Level Input Voltage Input Voltage Hysteresis
VIL
Full Operating Conditions
VIH
Full Operating Conditions
-
-
1.0
-
0.8
V
2.5
-
-
2.7
-
V
-
35
-
-
-
mV
Low Level Input Current
IIL
High Level Input Current
IIH
TURN-ON DELAY PINS: LDEL AND HDEL
VIN = 0V, Full Operating Conditions VIN = 5V, Full Operating Conditions
-260 -200 -150 -270 -130 A
-1
-
+1 -10 +10 A
LDEL, HDEL Voltage
VHDEL,V IHDEL = ILDEL = -100A
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO
4.9 5.1 5.3 4.8 5.4
V
Low Level Output Voltage High Level Output Voltage Peak Pullup Current Peak Pulldown Current Under Voltage, Rising Threshold
VOL
IOUT = 100mA
VCC - VOH IOUT = -100mA
IO+
VOUT = 0V
IO-
VOUT = 12V
UV+
0.7 0.85 1.0 0.5 1.1
V
0.8 0.95 1.1 0.5 1.2
V
1.7 2.6 3.8 1.4 4.1
A
1.7 2.4 3.3 1.3 3.6
A
8.1 8.8 9.4 8.0 9.5
V
Under Voltage, Falling Threshold
UV-
7.6 8.3 8.9 7.5 9.0
V
Under Voltage, Hysteresis
HYS
0.25 0.4 0.65 0.2 0.7
V
FN3658 Rev.8.00 Dec 11, 2019
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HIP4080A
Switching Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K,
CL = 1000pF, and TA = +25°C, Unless Otherwise Specified
TJ = +25°C
TJ = - 40°C TO +125°C
PARAMETERS
SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS
Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO) Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO) Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO) Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO) Rise Time Fall Time Turn-on Input Pulse Width Turn-off Input Pulse Width Disable Turn-off Propagation Delay (DIS - Lower Outputs)
TLPHL THPHL TLPLH THPLH
TR TF TPWIN-ON TPWIN-OFF TDISLOW
-
40 70
-
90
ns
- 50 80 - 110 ns
-
40 70
-
90
ns
- 70 110 - 140 ns
-
10 25
-
35
ns
-
10 25
-
35
ns
50 -
- 50 -
ns
40 -
- 40 -
ns
-
45 75
-
95
ns
Disable Turn-off Propagation Delay (DIS - Upper Outputs)
TDISHIGH
- 55 85 - 105 ns
Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO)
TDLPLH
-
45 70
-
90
ns
Refresh Pulse Width (ALO and BLO) Disable to Upper Enable (DIS - AHO and BHO) HEN-AHO, BHO Turn-off, Propagation Delay HEN-AHO, BHO Turn-on, Propagation Delay
TREF-PW
240 380 500 200 600 ns
TUEN
- 480 630 - 750 ns
THEN-PHL RHDEL = RLDEL = 10K -
40 70
-
90
ns
THEN-PLH RHDEL = RLDEL = 10K -
60 90
- 110 ns
IN+ > INX 0 1 0 1 X
INPUT
HEN
U/V
X
X
0
0
1
0
1
0
0
0
X
1
TRUTH TABLE
DIS
ALO
1
0
0
1
0
0
0
1
0
0
X
0
OUTPUT
AHO
BLO
0
0
0
0
1
1
0
0
0
1
0
0
BHO 0 0 0 1 0 0
FN3658 Rev.8.00 Dec 11, 2019
Page 6 of 19
HIP4080A
Pin Descriptions
PIN NUMBER
1
2
3
4 5 6
7 8
9
10
11 12 13 14 15 16 17 18 19 20
SYMBOL BHB
HEN
DIS
VSS OUT IN+
INHDEL
LDEL
AHB
AHO AHS ALO ALS VCC VDD BLS BLO BHS BHO
DESCRIPTION
B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers (Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).
DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).
Chip negative supply, generally will be ground.
OUTput of the input control comparator. This output can be used for feedback and hysteresis.
Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs. HEN (Pin 2) low level will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9).
Inverting input of control comparator. See IN+ (Pin 6) description.
High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.
Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.
A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
A High-side Output. Connect to gate of A High-side power MOSFET.
A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.
A Low-side Output. Connect to gate of A Low-side power MOSFET.
A Low-side Source connection. Connect to source of A Low-side power MOSFET.
Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes. Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4). B Low-side Source connection. Connect to source of B Low-side power MOSFET.
B Low-side Output. Connect to gate of B Low-side power MOSFET.
B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.
B High-side Output. Connect to gate of B High-side power MOSFET.
FN3658 Rev.8.00 Dec 11, 2019
Page 7 of 19
HIP4080A
Timing Diagrams
U/V = DIS 0 HEN 1
IN+ > INALO AHO BLO BHO
THPHL TLPHL
TDT TLPLH
THPLH TDT
TR
TF
(10% - 90%) (90% - 10%)
FIGURE 1. BISTATE MODE
U/V = DIS 0 HEN
IN+ > INALO AHO BLO BHO
THEN-PHL THEN-PLH
FIGURE 2. HIGH SIDE CHOP MODE
U/V or DIS HEN
IN+ > INALO AHO BLO BHO
TDLPLH TREF-PW
TDIS
TUEN
FIGURE 3. DISABLE FUNCTION
FN3658 Rev.8.00 Dec 11, 2019
Page 8 of 19
HIP4080A
IDD SUPPLY CURRENT (mA)
IDD SUPPLY CURRENT (mA)
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K, and TA = +25°C, Unless Otherwise Specified
13 14.0
12.5 12.0
12.0 10.0
8.0
11.5
6.0
11.0
4.0
2.0
8
10
12
14
VDD SUPPLY VOLTAGE (V)
FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE
20.0 15.0 10.0
10.5
10
200
400
600
800
1000
SWITCHING FREQUENCY (kHz)
FIGURE 5. IDDO NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (kHz)
5.0 +125°C
+75°C 4.0
+25°C
3.0
0°C
-40°C
2.0
ICC SUPPLY CURRENT (mA)
5.0
1.0
FLOATING SUPPLY BIAS CURRENT (mA)
0.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz)
FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 1000pF)
2.5
2
0.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz)
FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs FREQUENCY (kHz) TEMPERATURE
1.0
1.5
1 0.5
0.5
COMPARATOR INPUT CURRENT (A)
FLOATING SUPPLY BIAS CURRENT (mA)
0
200
400
600
800
1000
SWITCHING FREQUENCY (kHz)
FIGURE 8. IAHB, IBHB NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY
FN3658 Rev.8.00 Dec 11, 2019
-40 -20
0
20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 9. COMPARATOR INPUT CURRENT IL vs TEMPERATURE AT VCM = 5V
Page 9 of 19
HIP4080A
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K, and TA = +25°C, Unless Otherwise Specified (Continued)
-90
-180
LOW LEVEL INPUT CURRENT (A)
LOW LEVEL INPUT CURRENT (A)
-100
-190 -200
-210 -110
-220
-120
-50 -25
0
25
50
75
100 125
JUNCTION TEMPERATURE (°C)
FIGURE 10. DIS LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE
15.0
NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V)
14.0
13.0
12.0
11.0
10.0
-40 -20
0
20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 12. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE
525
PROPAGATION DELAY (ns)
500
475
450
425 -50 -25
0
25
50
75 100 125 150
JUNCTION TEMPERATURE (°C)
FIGURE 14. DISABLE TO UPPER ENABLE TUEN PROPAGATION DELAY vs TEMPERATURE
FN3658 Rev.8.00 Dec 11, 2019
-230
-40 -20
0
20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 11. HEN LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE
80
70
PROPAGATION DELAY (ns)
60
50
40
30 -40 -20 0
20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 13. UPPER DISABLE TURN-OFF PROPAGATION DELAY TDISHIGH vs TEMPERATURE
80
PROPAGATION DELAY (ns)
70
60
50
40
30
-40 -20
0
20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 15. LOWER DISABLE TURN-OFF PROPAGATION DELAY TDISLOW vs TEMPERATURE
Page 10 of 19
HIP4080A
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
10K, and TA = +25°C, Unless Otherwise Specified
450
80
PROPAGATION DELAY (ns)
REFRESH PULSE WIDTH (ns)
70 425
60
400
50
375
350 -50 -25
0
25
50
75 100
JUNCTION TEMPERATURE (°C)
FIGURE 16. TREF-PW REFRESH PULSE WIDTH vs TEMPERATURE
125 150
40
30
20 -40 -20
0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C)
FIGURE 17. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE
90.0
PROPAGATION DELAY (ns)
80.0
70.0
60.0
50.0
40.0
-40 -20
0
20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY THPHL vs TEMPERATURE
90.0
PROPAGATION DELAY (ns)
80.0
70.0
60.0
50.0
40.0
-40 -20
0
20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 19. UPPER TURN-ON PROPAGATION DELAY THPLH vs TEMPERATURE
90.0
PROPAGATION DELAY (ns)
80.0
70.0
60.0
50.0
40.0
-40 -20
0
20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY TLPHL vs TEMPERATURE
FN3658 Rev.8.00 Dec 11, 2019
90.0
PROPAGATION DELAY (ns)
80.0
70.0
60.0
50.0
40.0
-40 -20
0
20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 21. LOWER TURN-ON PROPAGATION DELAY TLPLH vs TEMPERATURE
Page 11 of 19
HIP4080A
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K, and TA = +25°C, Unless Otherwise Specified
13.5
13.5
TURN-ON RISE TIME (ns)
GATE DRIVE FALL TIME (ns)
12.5
12.5
11.5
11.5
10.5
10.5
9.5
9.5
HDEL, LDEL INPUT VOLTAGE (V)
8.5 -40 -20
0
20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 22. GATE DRIVE FALL TIME TF vs TEMPERATURE
6.0
5.5
5.0
4.5
4.0 -40 -20
0
20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 24. VLDEL, VHDEL VOLTAGE vs TEMPERATURE
8.5 -40 -20
0
20 40
60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 23. GATE DRIVE RISE TIME TR vs TEMPERATURE
1500
1250
VCC - VOH (mV)
1000
750 -40°C
500
0°C
+25°C
250
+75°C
+125°C
0
10
12
14
BIAS SUPPLY VOLTAGE (V)
FIGURE 25. HIGH LEVEL OUTPUT VOLTAGE, VCC - VOH vs BIAS SUPPLY AND TEMPERATURE AT 100A
1500
1250
1000
VOL (mV)
750
-40°C
500
0°C
+25°C 250
+75°C
+125°C 0
10
12
14
BIAS SUPPLY VOLTAGE (V)
FIGURE 26. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS SUPPLY AND TEMPERATURE AT 100A
FN3658 Rev.8.00 Dec 11, 2019
GATE DRIVE SINK CURRENT (A)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
6 7 8 9 10 11 12 13 14 15 16 VCC, VDD, VAHG, VBHB (V)
FIGURE 27. PEAK PULLDOWN CURRENT IO- BIAS SUPPLY VOLTAGE
Page 12 of 19
HIP4080A
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K, and TA = +25°C, Unless Otherwise Specified (Continued)
3.5
500
GATE DRIVE SINK CURRENT (A)
3.0 2.5 2.0 1.5 1.0 0.5 0.0
6 7 8 9 10 11 12 13 14 15 16 VCC, VDD, VABH, VBHB (V)
FIGURE 28. PEAK PULLUP CURRENT IO+ vs SUPPLY VOLTAGE
LOW VOLTAGE BIAS CURRENT (mA)
200
100
10,000
50
3,000
20
1,000
10
100
5
2 1 0.5
0.2
0.1 12
5 10 20
50 100 200 500 1000
SWITCHING FREQUENCY (kHz)
FIGURE 29. LOW VOLTAGE BIAS CURRENT IDD AND ICC (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE
1000 500
LEVEL-SHIFT CURRENT (A)
200 100
50
20
10
10
20
50
100
200
500 1000
SWITCHING FREQUENCY (kHz)
FIGURE 30. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE
150
BIAS SUPPLY VOLTAGE, VDD (V)
9 UV+
8.8
8.6
UV8.4
8.2
50 25
0
25 50 75 100 125 150
TEMPERATURE (°C)
FIGURE 31. UNDERVOLTAGE LOCKOUT vs TEMPERATURE
120
DEAD-TIME (ns)
90
60
FN3658 Rev.8.00 Dec 11, 2019
30
0
10
50
100
150
200
250
HDEL/LDEL RESISTANCE (k)
FIGURE 32. MINIMUM DEAD-TIME vs DEL RESISTANCE
Page 13 of 19
HIP4080A
FN3658 Rev.8.00 Dec 11, 2019
IN2 IN1
+12V
CONTROL LOGIC
SECTION
R29
1 U2
JMPR1
2
OUT/BLI
CD4069UB
13
12
U2
JMPR2 IN+/ALI
CD4069UB
5
U2
6
JMPR3 HEN/BHI
CD4069UB
11
U2
10
JMPR4 IN-/AHI
CD4069UB
JMPR5
+
DRIVER SECTION
C6
CR2
HIP4080A/81A C4 U1
1 BHB
BHO 20
2 HEN/BHI BHS 19
3 DIS
BLO 18
4 VSS
BLS 17
5 OUT/BLI VDD 16
6 IN+/ALI VCC 15
7 IN-/AHI ALS 14
+12V
8 HDEL ALO 13
9 LDEL AHS 12
R33
R34
10 AHB AHO 11
3
3
2
2
CR1
CW 1 CW 1
C3
C5
POWER SECTION
2 R21 1 Q1
3 R22
2 R23 1 Q2
3
R24
C8
2 1 Q3
3 L1
C1
L2
2 1 Q4
3
CX
CY
R30
R31
ALS
BLS
B+
AO BO C2
COM
NOTES:
1. DEVICE CD4069UB PIN 7 = COM. PIN 14 = +12V.
2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, ARE NOT SUPPLIED. REFER TO APPLICATION NOTE FOR HELP IN DETERMINING JMPR1 - JMPR4 JUMPER LOCATIONS.
Page 14 of 19
FIGURE 33. HIP4080A EVALUATION PC BOARD SCHEMATIC
HIP4080A
FN3658 Rev.8.00 Dec 11, 2019
GND
+12V
B+
COM
C1
R32 R29
C7 JMPR5
R27 R28 R26 C6
C8
CR2
+
+
AO
Q1
Q3
U1
C4
R22
1
1
BHO
C2
R24
HIP4080/81
U2
DIS
BLO
IN1
BLS
L1
L2
BO
I
JMPR1
O
JMPR2 JMPR3
ALS
R23
Q2
Q4
IN2
JMPR4
ALO
1
1
O LDEL
R21 AHO
C3
ALS BLS
R33 R34
CR1
HDEL C5 CX R30 CY
R31
FIGURE 33. HIP4080A EVALUATION BOARD SILKSCREEN
Page 15 of 19
HIP4080A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision.
DATE
REVISION
CHANGE
Dec 11, 2019
FN3658.8
Removed retired parts. Added Revision History section. Updated POD M20.3 to the latest revision. Changes are as follows:
Rev 2. - Removed "u" symbol from drawing (overlaps the "a" on Side View). Rev 3. - Top View: Corrected "7.50 BSC" to "7.60/7.40" (no change from rev 2; error was introduced in conversion) Changed "10.30 BSC" to "10.65/10.00" (no change from rev 2; error was introduced in conversion) Side View: Changed "12.80 BSC" to "13.00/12.60" (no change from rev 2; error was introduced in conversion) Changed "2.65 max" to "2.65/2.35" (no change from rev 2; error was introduced in conversion) Changed Note 1 from "ANSI Y14.5M-1982." to "ASME Y14.5M-1994" Updated to new POD format by moving dimensions from table onto drawing and adding land pattern Updated disclaimer.
FN3658 Rev.8.00 Dec 11, 2019
Page 16 of 19
HIP4080A
Package Outline Drawings
INDEX AREA
N 12 3
E1 N/2
-B-
-A-
D
E
BASE PLANE SEATING PLANE
-C- A2 A
L
CL
D1
B1 B
e
D1
A1
eC
0.010 (0.25) M C A B S
eA
C
eB
NOTES:
3. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.
4. Dimensioning and tolerancing per ANSI Y14.5M-1982.
5. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95.
6. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
7. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
8. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
9. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
10. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).
11. N is the maximum number of terminal positions.
12. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE (PDIP)
INCHES
MILLIMETERS
SYMBOL MIN
MAX
MIN
MAX NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115 0.195 2.93 4.95
-
B
0.014 0.022 0.356 0.558
-
B1
0.045 0.070 1.55 1.77
8
C
0.008 0.014 0.204 0.355
-
D
0.980 1.060 24.89 26.9
5
D1
0.005
-
0.13
-
5
E
0.300 0.325 7.62 8.25
6
E1
0.240 0.280 6.10 7.11
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
6
eB
-
0.430
-
10.92
7
L
0.115 0.150 2.93 3.81
4
N
20
20
9
Rev. 0 12/93
FN3658 Rev.8.00 Dec 11, 2019
Page 17 of 19
HIP4080A
M20.3 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev 3, 2/11
20
INDEX AREA
7.60 7.40
3
10.65 10.00
0.25 (0.10) M B M
1 23
TOP VIEW
2 13.00 12.60
2.65 2.35
SEATING PLANE
1.27 BSC
7
0.49 0.35
0.25 (0.10) M C A M B S
SIDE VIEW
0.30 MAX
0.10 (0.004)
8° MAX
5 1.27 0.40
0.75 x 45° 0.25
DETAIL "X"
0.32 0.23
(0.60) 20
(9.40mm)
1.27 BSC (2.00)
12 3 TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
3. Dimension does not include interlead lash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
5. Dimension is the length of terminal for soldering to a substrate.
6. Terminal numbers are shown for reference only.
7. The lead width as measured 0.36mm (0.14 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch)
8. Controlling dimension: MILLIMETER.
9. Dimensions in ( ) for reference only.
10. JEDEC reference drawing number: MS-013-AC.
FN3658 Rev.8.00 Dec 11, 2019
Page 18 of 19
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