NEC uPD72070 Datasheet

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NEC Inc.

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uPD72070

Chapter 1 General
1.1 System Overview
The uPD72070 Floppy Disk Controller (FDC) is a new advanced Floppy Disk Controller that can support four standard Floppy Disk Drives (FDD)'s and two Apple specific FDDs, respectively. For the standard FDDs, the uPD72070 FDC is compatible with the NEC µPD765A and therefore maintaining compatibility with all uPD765A existing software and copy ·protection schemes ..
The uPD72070 FDC has the special capability to support both writing and reading the Apple proprietary GCR format. In addition the uPD72070 can support conventional MFM and FM formats in the 2DD, 2HD, 2ED and 2TD typed FDDs. These features make the uPD72070 FDC easily adaptable into Apple Macintosh computers.
By having the same register set as in the IBM PS/2 and PC/AT computers, the uPD72070 FDC can easily be adapted in these PCs and compatible PCs.
The external circuits necessary to support both Apple Computers standard Super Drive FDD's and conventional MFM FDDs are fully implemented into the uPD72070 FDC.
1.2 Features
The 72070 Advanced Floppy Disk Controller or "New Age FDC" has the following features.
·General - Functional superset of µPD765A and Intel 82077 - Supports Apple GCR format - Supports lMB, 2MB, 4MB and 13MB FDDs -Automatic wake up from standby mode· Host Interface - 8-bit BUS width - 16-byte FIFO in the Data register - Implements PS/2 and PC/AT registers
1

- Intel Interface · Drive Interface
- Supports both the Apple specific FDDs and standard FDDs - Analog PLL based on µPD72069 - Precompensator - Clock Generator - FDD drivers and receivers · Additional commands - Apple specific commands
( These should be disclosed only to Apple Computer)
2

1.3 Recording Formats
This FDC can support the following two formats:
1) GCR recording format used on special FDDs in Apple Macintosh Computers
2) MFM and FM recording formats used on conventional FDDs and Super Drives in Apple Macintosh Computers

1.3.1 GCR Format Description (Group Code Recording)
GCR is the older of the two floppy disk formats used in Macintosh computers. Disks formatted with GCR can store up to SOOK bytes on a double sided disk. In the GCR encoding scheme, only binary l's generate transitions (Figure 1.3.1). A long run of zeroes, leading to an absence of transitions, can make the data recovery process very difficult and unreliable. In order to improve the reliability of data recovery, the software driver code (referred to as the driver), encodes the data to limit the maximum number of non-transitions to 2. Apple calls this process nibblizing, and if effectively encodes 3 bits of raw data into 4. When the driver reads data from the disk, it decodes it by a process called denibblizing.
RawData 1 0 O 1 O 0 1 O 1

Encoded

Read Data

j Encoded
Write Data

Fig. 1.3.1 GCR Encoded Read and Write Data

1.3.1.1 GCR Traclc and Sedor Format

In order to maximiz.e the storage capacity of a GCR floppy disk, GCR drives vary their spindle speed by making automatic adjustments based on the cylinder. This permits greater storage for the outer cylinders than could be achieved if the spindle speed were held constant. As a simplification, the 80 cylinders on a GCR drive are split up into 5 speed zones, each with a different number of formatted sectors(Table 1.3.1).

Table 1.3.1 GCR Speed Groups

Speed Z.One Cylinders Sectors

Oto 15 12

16to31 11

32 to47 10

48to63

64to79

The driver formats a disk so that the sectors are evenly distributed around each track(Figure 1.3.2). This is accomplished by varying the number of sync groups between the sectors of the track. A sync group is composed of a 6 byte sequence(FF 3F CF F3 FC FF) which guarantees that the hardware is synchronized prior to the beginning of an address or data mark.

During the format process, the driver initially tries to format the track with 6 or 7 sync groups between sectors. If that is successful, the driver will increment the number of sync groups and reformat the track. If that format is successful, the process is repeated until the format fails. Once the format has failed, the driver uses the last successful number of sync groups to format the track.
la= IFF 13F IF3 fFC jFF j Self Sync bytes

Self Sync byt Self Sync byt

Self Sync byt s Variable # of Self Sync Grc

- - - Sector N Gap Sector o Gap Sector 1 Gap Sector 2 Gap - - Fig. 1.3.2 GCR Track Format

Figure 1.3.3 shows the GCR sector format. Both parts of the sector begin with six self sync bytes. The address field consists of three mark bytes($D5, $AA, $96); the track, sector, side, format and checksum bytes(encoded as GCR nibbles); and two bit slip bytes ($DE, $AA). The track and side information are combined into a 16-bit word that puts the side number into bit 11 and the track number into bits 0-10. Although 11 bits are specified for the track number, only 8 bits are used. The remaining 3 bits, track 10-8, are always O.

The data field consists of three mark bytes($D5, $AA, $AD), the sector number, sector data, and two bit slip bytes($DE, $AA). The sector data consists of: 12 tag bytes (used by the operating system), 512 data bytes (containing user data), and 3 checksum bytes. When encoded as GCR nibbles, the data tales up 703 bytes:4·[(12+512)/3 groups]=699 data+4 checksum bytes.

track(trS:eJI...._e_._e_.._l_tr5_.l.._t_r4...l.._tr_3"""1t_r.2...l_t_r1..f.._tr__.el
I I I I I sector1ss:e1l e e ss s4 s3 I s2 s1 Ise ::=:::=:::::::::::::::::::::==:=::::=:::::~
slde,track:(trl e:d_l_e_e_Is_1d_,_tr_1_q_tr9_It_re_l_t_r1..l.._tr6_.I

format byteCfS:..,.hJ8__.._e_.l....t_s...l.._r4_1_f_:s...l.._12....l....1_1...l.._10.....I

____ __ checksum(ckS:e..,_e.......

...__

~...__

~------.

self Sync byte

Address mark

address header

Bit slip byte

self Sync byte

data mark

Tag Bit slip

d;a

byte

FF 3F CF F3 FC FF D5 AA 96 tr s str f CX DE AA FF 3F CF F3 FC FF D5 AA MJ s XX... DE AA

Fig. 1.3.3 GCR Sector Format

1.3.1.2 Nibblizing and Denibblizing
As mentioned· in the previous section, data written to the disk must be encoded in order to limit the "O" run length of the serial bit stream. When data is written it is nibblized, and when it is read it is denibblized. Because of the size of the address field, the driver encodes the data and address header differently. The nibblizing and denibblizing processes for each will be discussed separately.

1.3.L3 Nibblizing Sector Data
GCR sector data contains two parts: Tag Bytes and Sector Data (see the section on GCR sector format for more details}. The operating system uses the 12 bytes for various functions. While, the sector data merely contains 512 bytes of user data. Between the two, the total length of the sector data field is 524 bytes. Therefore, the driver must nibblize 524 bytes when it writes the sector data.
The nibblizing process(US patent #4,564,941 Wooley et al, Apple Computer Inc.} begins by reading 3 bytes of data in order to encode them into 4 bytes. The encoding guarantees that the four bytes do not exceed the run length restriction of the GCR encoding specification. As a convention, the bytes in this 3 byte group are referred to as the A byte, B byte, and C byte.
Nibblizing is performed in a two stage process. In the first stage the driver accumulates the checksums for the 3 bytes of data. When computing the

overall checksum for the data, the driver maintains three checksums; the A, B, and C checksum, that correspond to the A, B, and C bytes. The algorithm for this is shown below on pseudocode:

/'"' Reads Data from the System Memory ·I

For (n=O; n=<Ox20b; n++) /· repeats 524 times ·I

Read( Data(n) );

/· reads data from the System
Memory into Data (n) ·I

Data(Ox20c)=O;
/·Initialization·I

/· the only last data should be set to
'ZX!ro *I

ChecksumA =0 ;

ChecksumB =0 ;

ChecksumC =0 ;

Carry_ChecksumCx =0 ; /*the Carry bit of ChecksumCx *I

For ( n=O; n=< OxOae; n++) /*repeats to calculate 175 times*/

ByteA=Data(n); ByteB=Data(n+1); ByteC=Data(n+2);

ChecksumA=ChecksumA + ByteA + Carry_ChecksumCx; ByteA =ByteA XOR ChecksumC;

ChecksumB=ChecksumB + ByteB + Carry_ChecksumA; ByteB =ByteB XOR ChecksumA;

ChecksumCx=ChecksumC + ByteC + Carry_ChecksumB; ByteC =ByteC XOR ChecksumB;

ChecksumC=Rotate Left 1, not through Carry_ChecksumCx;

It is important to notice in the pseudocode above that there is interaction 6

amongst both the checksums and the data. This is done to improve the error detection capability of the algorithm. In order to properly encode the data, the driver must adhere to this exact sequence of operations. Violating the sequence will cause encoding errors.
In the second stage of the process, the 3 bytes are encoded to limit the "O" run length of the data prior to writing in to disk. Fig. 1.3.4 shows the second stage of the nibblizing process.
The driver strips of the two upper bits of each of the three bytes and accumulates them in a fourth byte, called the Hi-Bits byte. The driver then encodes each of these four bytes with the Nibblizing look up table shown in Table 1.3.2. For example, applying the byte $0F(001ll1 in binary) to the table yields an encoded byte of B3H. After the driver encodes each byte, they are written to the disk serially, with the most significant bit written first. Because the driver computes the checksums prior to the Hi-Bits byte.
Table 13.2 Nibblizing Look-Up Table
Bits 2:8 888 881 818 811 188 181 118 111
BBB $96 $97 $9R $9B $90 $9E $9F $R6 881 SR7 SAS SAC SAD SAE SAF SB2 $83 818 $84 $BS $86 SB7 $89 SBA SBB SBC
Bits 811 SBD $8E SBF see Seo sa $CF $03 5:3 188 $06 $07 $09 SOR SOB soc $00 SOE
181 SDF SES $E6 sa SE9 SER SEB SEC
11B sm SEE $EF SF2 $F3 $F4 SFS $F6 111 sn $F9 SFR SFB SFC $FD $FE $FF
The encoding process described above assumes that data portion of the sector is evenly divisible by 3. Unfortunately this is not the case. Because
7

the sector data field is 512 bytes long, the driver must handle the residual 2 bytes as a special case. In order to properly encode the last 2 bytes of the sector data, the driver assumes that a 513th byte is zero. .Therefore, the driver encodes that last two bytes assuming a third byte which is zero. The driver dose not write this zero byte to the disk.
After the driver wries that last data to the disk, the driver nibblizes the three checksum bytes(as shown in Figure 1.3.4), and writes them to the disk.

L3.L4 Denibblizing
When the driver reads data from the disk it must be decoded before it can be used. Apple calls this process denibblizing. The driver denibblizes the read data in two stages.
In the first stage the driver reads four data bytes from the disk. The driver must work in blocks of four bytes because the nibblizing process encoded three byres into four. As the bytes are read from the disk, the driver initially decodes them with the look-up table in Table 1.3.3. For example, a data byte of $B9 is decoded to $14.

Bits 7:4

$9 SR SB SC SD SE SF

$8 - - - - - - -

$1 - - - - - - -

$2 - - BE - - - 33

Bits 3:9

$3
$4

- - - BF - 1F

- - - 1B - - 35

- - SS

- 11

- 29 36

- $6 BB B7 12

28 2R 37

- S7 Bl BB 13

21 28 38

$8 - - - - - - -

- - - $9

22 2C 39

- - SR 82

23 20 3R

$8 B3 89 16 18 24 2E 38

- - SC

BR 17

25 2F 3C

SD B4 88 18 lC 26 3B 30

SE BS BC 19 10 27 31 3E

SF B6 BO 1R 1£ 28 32 3F

Table 1.3.3 Denibblizing look-up table

After the decode through the look-up table, the data is now composed of 4 bytes with their two most significant bits to zero. The driver then takes the first of the 4 bytes(the Hi-Bits byte) and re-distributes the data, in two bit chunks, across the remaining three bytes. Figure 1.3.5 shows the complete decoding process.

1ID61osp!l[ij02P1 l[)(j -+

- + o o A7 s e es

1lEijESi341EijE21¥1 IECj -+ oenlbbl~-+ Io Io lA51A4IA31A21#'1IACj
1lFSIF5f4IF3jF2f1 !Fol-+ Table -+lo Ioles@le3le2181leij

1 1G@IG4IG31G2@1IG~ -+

_. Io IolcsjC4l§IC21C1 ICXJ ~ P5 P41C31C2 p1 ICOI

Fig. 1.3.5 Denibblizing process for Sector Data

Now that the original three have been reassembled, the driver must compute and compare the checksums. The pseudocode example below shows the algorithm for computing the checksum during a read.

/·Reads Read-Data from the FDD ·I

For (n=O; n=<Ox2bb; n++) /·repeats 700 ·I

Read( Byte(n) );

/· reads Read-data from the FDD

into Data (n) after denibblization ·I

I· Initialization ·I

Checksum.A =0 ;

ChecksumB =0 ;

ChecksumC =O ;

For ( n=O; n=< OxOae ; n++) /· repeats to calculate 175 times ·I
Carry_CheksumC =ChecksumC(bit7); ChecksumC=Rotate Left 1, not through carry (ChecksumC);

Byte(n)=Byte(n) XOR Checksum.C; ChecksumA=ChecksumA + Byte(n) + Carry_ChecksumC;

Byte(n+l)=Byte(n+1) XOR Checksum.A; ChecksumA=ChecksumA + Byte(n+l) + Carry_ChecksumA;

Byte(n+2)=Byte(n+2) XOR ChecksumB; ChecksumA=ChecksumA + Byte(n+2) + Carry_ChecksumB;
Data(n) =Byte(n); Data(n+l)=Byte(n+1); Data(n+2)=Byte(n+2);
The denibblizing process assumes that the number of bytes the data field are evenly divisible by 4. Unfortunately, because of the assumed 513th data byte (see the previous section, which was not written when the driver encoded the data, there will be a residual of 3 bytes during the read. In order to properly decode the last three bytes, the driver assumes a "O" byte that is not read from the disk. The driver decodes that last three bytes and the assumed ..O" byte the same process shown in Figure 1.3.5.
After the driver has read, decoded, and reassembled all the data bytes, the four checksum bytes are denibblized by the same process that is shown in Figure 1.3.5. The driver then compares the computed checksum against the reassembled three checksum bytes.
1.3.1.5 Nibblizing and Denibblizing for the Address Header Because of the small number of bytes in the address header, the driver encodes the address header differently from the data field. In general, the process for the address header is much less complicated. As shown in Figure 1.3.3, the driver formats the of the address header so that they have their upper two bits set to zero, with the data occupying the lower 6bits of the byte. This format simplifies the nibblizing process by making the HiBits byte process unnecessary. The driver can simply encode the 4 bytes directly through the nibblizing table. In addition the checksum computation is also significantly simplified. To compute the checksum, the driver merely xor's all four bytes into a longitudinal checksum according to the following algorithm: Checksum : = track byte xor sector byte xor side, track byte xor format byte; All four bytes and the checksum byte are then encoded with the look-up table in Table 1.3.2 and written to the disk. Figure 1.3.6 shows the nibblizing process for the address header and its checksum.
10

track(tr5:0) o o Itrsl tr41 tQI tr?I tr1 I tro I-+ sector(s5:0) o o I ssl s4l s3l s2I sl I sol-+
side,track(tr1o:s> o o lsiddtr1d tr9I trsl tr1I trsl-+
format byte(fS:O) o o I ts ! f4 I f3 t t2 ! t1 I to I -+

~~b~~e

-+ 1 Asl Asl A4I A31 A?I A1I Aol
-+ 1 esi esl 84! B3i 02101! sol
-+ 1 csi csl C4! C3! 02101! col
-+ 1 os! osl 041 ool 021 01 I ool

checksum(ck5:0) o o tckijck4ckiJcki)ck1lckd _ .

_ . 1 Est Es! E4t E3i E2t E1l Eoi

Fig. 1.3.6 Address Header Nibblizing Process

To FDD

When the driver reads the address header, the driver simply decodes each byte with the denibble table shown in Table 2-3. Figure 2-7 shows the denibblizing process for the Address header.

From FDD

1 Aff A@ AM Aiil A2I Ali Aol -+
ea + Bl 1 Bff B4J eiil e1! eol ca 1 C6I C4J Ci @ 011 rnl....
mt 1 OSI D5I D4J fu! p1I ool _.

_ . o o I trsl tr41 tra! tr?! trl I trol track(tr5:0)
+ O O t 5sl Mt 53t 52 t 51 t 5ol sector(sS:O)
Denlbble .... Q Q ls;ddtrld trsl ical ial trSI side,track(tr10:6)
Table
_ . o o I ts I t4 I t3 ! 12 ! f1 I to !format byte(fS:O)

1 Efil r:51 r:dl 1=;d Eiil E1l Eal-+

-+ o o lpk32kJc1s3c1sac1s1lpkdchecksum(ckS:O)

Fig. 1.3.7 Address Header Denibblizing Process

The driver then computes and compares the checksum according algorithm shown above.

1.3.1.6 Error Detection for GCR

The following conditions should be reported as errors: · Partial Address Mark The address mark found is not romplete. · Bad Address Checksum The computed checksum does not match the checksum stored at the end of the address header of the sector. · Bad Address Bitslip Marks The bitslip bytes at the end of the address header do not meet the format specification. · Bad Data Mark The data mark of the sector is not complete.

· Bad Data Checksum. The computed checksum. dose not match the checksum stored at the end of the data portion of the sector.
· Bad Data Bitslip Marks The bitslip bytes at the end of the data portion of the sector do not meet the format specification.
12

1.3.2 MFM Description
Unlike GCR drivers, MFM drivers do not vary their spindle speed while writing or reading data on a disk. Instead, the driver puts the same number of sectors on each track. For the 720K format, there are 9 sectors per track and for the 1440K format, there are 18 sectors per track. The disk drive does vary its spindle speed for the different MFM densities; 600 rpm for 720k, or 300 rpm for 1440k.

1.3.2.1 MFM Track and Sector Format
Fig. 1.3.2.1 shows the MFM track format The driver uses the index pulse to detel'IIl:ine where the track physically begins. In order to maintain compatibility with the NEC µPD765A disk controller format, the driver writes index information during the time that the index pulse is asserted. The index field is made up of 12 bytes of zeroes which is followed by the index mark. The index mark is composed of three special characters($C2) and the byte pattern $FC. These special characters violate the MFM encoding standard by missing a transition. Once the index information is written is ignored by any subsequent operations.
physical Index pulse

4E--4E
Gap to Index mark (GAP4A)

0--0 Sync field
(128)

C2 C2 C2 FC 4E- - 4E Sector1 Sector2 Sector3

Index mark
(48)

Gapto first
sector (GAP4A)

Fig. 1.3.21 MFM Track Format

Sector N 4E- - 4E
Gap to end of track (GAP4B)

Following the index information, the MFM track format contains a gap that acts as a buffer to allow for drive variations. Depending on density, the driver formats either 9{720K) or 18(1440K) sectors following the gap. Following the last sector, the driver writes gap bytes to the end of the track. Fig. 1.3.2.2 shows the MFM sector format.

ID field

.,..-4~--- Data field

Sync byte

Address
mark

address header

GAP2

Sync data address

byte

mark

data

GAP3

00·.·0 A1 A1 A1 FE C H S N alC 4E --- 4E 00··.0 A1 A1 A1 FB XXX.··X ale 4E --- 4E

Fig. 1.3.2.2 MFM Sector Format

A track contains 5 distinct gaps that vary depending upon format density. Table 1.3.2.1 shows the gap sizes for all the gaps shown in Figures 1.3.2.1 and 1.3.22, organized according to the disk density.

Disk Capacity

Gap length in Bytes

Unformatted Formatted Ga121 Ga122 Ga123 GaRiA GaRiB

lMB

720KB

50 22 84

182

2MB

1.44KB

50 22 101

204

4MB

288MB

50 41

518

Table 1.3.21 Gap sizes for Various MFM disk capacities

1.3.2.2 CRC Computation for MFM The CRC computation for both the address header and sector data follow the CCITI-CRC16 algorithm.
1.3.2.3 Precompensation of MFM Data For industry standards, one precompensation value is used with MFM. The lMbyte and 2Mbyte disks(720K and 1.44M formatted disks) require 125ns for inner cylinders. The 4MByte disk standard does not require any precompensation. The precompensation values are defined by the bits in the Data Rate register.

1.4 Operation Modes
This FDC can support the following operation modes by using the external PCTYPl,O pins:

PCTYPl PCTYPO

OJ?eration Mode Apple - Selects Active Low Reset General - Standard Mode
PS/2 - Standard Mode
PC/AT - Standard Mode

In each mode, there are different ways available for Registers and Commands to be used. Therefore, the host should use the following functions according to the operation mode:

- Formats - Drive Select

- Data rates - Precompensation

- Motor On/Off

1.4.1 Apple Mode
This Apple mode implemented into the uPD72070 FDC is available only for Apple Computer and may not be available for other users of this FDC.

Under Apple mode, only the Status register (STR), Data register (DTR) and Data rate register (DRR) can be used.

GCR recording formats are support on the Macintosh FDD's which include the Apple Super Drive and emerging Apple 4MB Super Drive FDD. MFM recording formats are supported on lMB, 2MB, and 4MB FDD's. (There is no support for FM recording formats)

As for the commands, the FDC can support the all commands except the

following commands:

- Read Deleted data - Scan Low or Equal - Relative Seek

- Write Deleted data - Scan High or Equal -Dumpreg

-Scan Equal - Verify - Version

As for the Data Rates, the bits (DRATEl, DRATEO) in the Data Rate Register should be set.

As for the target drive, the bits (DRl, ORO) in the issued commands can automatically select the desired drive so that the polling function can be supported.

As for the formats, the (FM) bit in the issued commands can automatically select either GCR or MFM formats.

As for turning the FDD motor On or Off, the Set Motor Control command should be used.

GCR recording requires no preshifting of the Write Data signal from the FDC.

The Data Register with FIFO will always be available in the Execution phase of the Read/Write commands group after the EFO bit and the FIFOnID bits in the Configure command are set.

The combination of Select Drive Type and Perpendicular Mode commands, in conjunction with the setting of the proper bits in the Data Rate Register (DRR) register are used to select the types Floppy Disk Drive to be used. Selection can be one of the following drives; 2DD, 2HD, 2ED, 2TD and GCR. Please refer to Table 1.4.1.2.

Also, the reference table of various media for different disk capacity, data rate, & track num~r is shown on table 1.4.1.1.
USA (IBM DOS)
Media Capacity RPM Data Rate Traclc (Cylinder) Sector Byte/Sector

S.25" 1.2M (1.6M) 360 SOOK

160 (80)

512

3.5" 720K(1M) 300 250K

160 (80)

512

3.S" 1.44M (2M) 300 SOOK

160 (80)

512

3.S" 288M(4M) 300

160 (80)

S12

JAPAN

5.25" 640K

360 300K

160 (80)

512

5.25" 1.2M

360 SOOK

154(77)

1024

3.5" 640K

360 300K

160 (80)

S12

3.5" 1.2M

360 SOOK

154 (77)

1024

Table 1.4.1.1 Capacity, RPM, Data rate, & Traclc Number

Format T

Pins

DriveT

ORR

APPLE MODE

l MB yte (MFM) Horizontal

10 cc 01

2MByte (MFM) Horizontal

4MByte (MFM) Horizontal

INVALID CONFIGURATION

13MByte(MFM) Horizontal

lMByte (MFM) Perpendicular 11

2MByte (MFM) Perpendicular 11

4MByte (MFM) Perpendicular 11

400K (GCR)

Horizontal

800K (GCR)

Horizontal

400K (GCR)

Perpendicular 11

SOOK (GCR)

Perpendicular 11

PS/2MODE

lMByte (MFM) Horizontal

10 cc 01

2MByte (MFM) Horizontal

4MByte (MFM) Horizontal

INVALID CONFIGURATION

13MByte(MFM) Horizontal

IMByte (MFM) Perpendicular 00

2MByte (MFM) Perpendicular 00

4MByte (MFM) Perpendicular 00

PC/AT MODE

lMByte (MFM) Horizontal

10or01

2MByte (MFM) Horizontal

4MByte (MFM) Horizontal

INVALID CONFIGURATION

13MByte(MFM) Horizontal

()()

lMByte (MFM) Perpendicular 01

()()

2MByte (MFM) Perpendicular 01

()()

4MByte (MFM) Perpendicular 01

GENERAL MODE

lMByte (MFM) Horizontal

()()

lOorOl

2MByte (MFM) Horizontal

()()

4MByte (MFM) Horizontal

INVALID CONFIGURATION

13MByte(MFM) Horizontal

()()

lMByte (MFM) Perpendicular 10

2MByte (MFM) Perpendicular 10

4MByte (MFM)

Perpendicular 10

400K (GCR)

Horizontal

SOOK (GCR)

Horizontal

400K (GCR)

Perpendicular 10

SOOK (GCR)

Perpendicular 10

Table 1.4.1.2. Selecting Floppy Drive Types

FM Bit
0 0
1 1 1 1 0 0

1.4.2 PS/2 Mode Under PS/2 mode, all registers, which have the same functions as that in

IBM PS/2, are available. The supported formats are MFM and FM recording formats to be supported by the world wide standard FDC µPD765A. As for the commands, the FDC can support the all commands except the following commands, which should be disclosed to Apple Computer only:

- Format/Write

- Disable/Enable DPLL - Eject Disk

- Set Drive Mode

- Set Motor Control

- Raw Dump

As for the Data Rates, the bits (DRATEl, DRATEO) in the Data Rate Register or the bits (DRATEl, DRATEO) in the Configuration Control Register should be set. If one register is set and then the other register is set, the register that was set last has the priority.

As for the target drive, the bits (DSl, DSO) in the Digital output Register can automatically select the desired drive so that the polling function can not be supported.

As for the formats, the (FM) bit in the issued commands can automatically select either FM or MFM formats.
As for turning the FDD motor On of Off, the bits (EM3, EM2, EMl, EMO) in the Digital output Register should be used.

As for the value of the preshifted Write Data signal, the bits (PCS2, PCSl, PCSO) in the Data Rate Register should be defined and the cylinder to be written with the preshifted Write Data signal should be defined by the PRETRK bits in the Configure command. The reset default of this PRETRK bits is set to the zero so that every cylinder is written with the preshifted Write Data signal.

On the other hand, the Data Register with FIFO can always be available in the only Execution phase of the Read/Write commands group after the EFO bit and the FIFOTHD bits in the Configure command are set.

The combination of Select Drive Type and Perpendicular Mode commands, in conjunction with the setting of the proper bits in the Data Rate Register (ORR} register are used to select the types Floppy Disk Drive to be used. Selection can be one of the following drives; 2DD, 2HD, 2ED, 2TD and GCR. Please refer to Table 1.4.1.2.

1.4.3 PC/AT Mode Under PC/AT mode, the following registers, which have the same

functions as that in IBM PC/ATI, are available;
- Status resister (STR) - Data register (DTR) - Data Rate Register (ORR) - Digital output register (DOR) - Digital Input register (DIR) - Configuration Control register (CCR) - Tape Drive Register (TDR)
Status A, B register are not available in this mode.

As for the supported formats, MFM and FM recording formats as same as that supported by the world wide standard FDC µPD765A are can be supported.

As for the commands, the FDC can support the all commands except the

following commands, which should be disclosed to Apple Computer only:

- Format/Write

- Disable/Enable DPLL - Eject Disk

- Set Drive Mode - Set Motor Control

- Raw Dump

As for the Data Rates, the bits (DRATEl, DRATEO) in the Data Rate Register or the bits (DRATEl, DRATEO) in the Configuration Control Register should be set. H one register is set and then the other register is set, the register that was set last has the priority.

As for the target drive, the bits (051, DSO) in the Digital output Register can automatically select the desired drive so that the polling function can not be supported.

As for the formats, the (FM) bit in the issued commands can automatically select either FM or MFM formats.

As for turning the FDD motor On or Off, the bits (EM3, EM2, EMl, EMO) in the Digital output Register should be used.

As for the value of the preshifted Write Data signal, the bits (PCS2, PCS1, PCSO) in the Data Rate Register should be defined and the cylinder to be written with the preshifted Write Data signal should be defined by the PRETRK bits in the Configure command. The reset default of this PRETRK

bits is set to the zero so that every cylinder is written with the preshifted Write Data signal.

On the other hand, the Data Register with FIFO can always be available in the only Execution phase of the Read/Write commands group after the EFO bit and the FIFOTIID bits in the Configure command are set.

The combination of Select Drive Type and Perpendicular Mode commands, in conjunction with the setting of the proper bits in the Data Rate Register (ORR) register are used to select the types Floppy Disk Drive to be used. Selection can be one of the following drives; 2DD, 2HD, 2ED, 2TD and GCR. Please refer to Table 1.4.1.2.

1.4.4 General Mode Under General mode, the following registers are available: - Status resister (STR) - Data register (DTR) - Data Rate Register (ORR) The IBM "PS/2 and "PC/AT registers are not available.

As for the supported formats, MFM and FM recording formats as same as that supported by the world wide standard FDC µPD765A are can be supported.

As for the commands, the FDC can support the all commands except the following commands, which should be disclosed to Apple Computer only:

- Format/Write

- Disable/Enable DPLL - Eject Disk

- Set Drive Mode

- Set Motor Control

- Raw Dump

As for the Data Rates, the bits (DRATEl, DRATEO) in the Data Rate Register should be set.

As for the target drive, the bits (DRl, ORO) in the issued commands can automatically select the desired drive so that the polling function can be available.

As for the formats, the (FM) bit in the issued commands can automatically select either FM or MFM formats.

The control to turn the FDD motor On or Off can not be supported.
As for the value of the preshifted Write Data signal, the bits (PCS2, PCSl, PCSO) in the Data Rate Register should be defined and the cylinder to be written with the preshifted Write Data signal should be defined by the PRETRK bits in the Configure command. The reset default of this PRETRK bits is set to the zero so that every cylinder is written with the preshifted Write Data signal.
On the other hand, the Data Register with FIFO can always be available in the only Execution phase of the Read/Write commands group after the EFO bit and the FIFOTIID bits in the Configure command are set. The Select Capacity command can be used to select the types of drives, 2DD, 2HD, 2ED, 2TD except GCR. Please refer to Table 1.4.1.2.
1.5 Data Transfer Modes The FDC has the three phases according to the internal operating state in the FDC. One is the Command phase to set the required parameter into the FDC, second is the Execution phase to be performing the issued command and final is the result phase to inform of the host about the result for the executed command.
In these phases, the ways to transfer data between th.is FDC and the host are the following data transfer modes.
1) OMA transfer mode; This transfer mode can be used in the only Execution phase.
2) Non OMA transfer mode; This transfer mode, maybe called as the Programmed I/0 mode, can be used in all phases but mainly in only Command and Result phases.
21

Chapter 2 Pin Functions

2.1 Host Interface Pins

Isymbol

1/0 Signal Function

RESET

In RESET. Sets FDC to idle state.

XA1,XA2

In CRYSTAL INPUTS. For internal oscillator frequency control, a crystal resonator is connected to XAl and XA2. For external dock input at XAl, XA2 are open. Frequency=24MHz. Supported data transfer rates lMbps, SOOKbps, 300Kbps and 250Kbps.

In TTL EXTERNAL CLOCK INPUT.

Frequency =15.6672MHz, for GCR FDD.

Frequency =20MHz, for 13Mbyte FDD. When

external clock is not supplied, XB pin must be

connected to ground.

CS_b

In CHIP SELECT. Validates RD_b and WR_b signals.

DO-D7

1/0 DATA BUS. Bidirectional three-state data bus with 12mA drive.

AO-A2

In ADDRESS 0-2. Selects a register in FDC.

A2 Al AO R/W Register

0 0 R Status Register A (SRA)

0 1 R Status Register B (SRB)

1 0 R/W Digital Output Register (DOR)

1 1 R/W Tape Drive Register(TDR)

0 0 R Status Register (STR)

w Data Rate Register (DRR)

0 1 R/W Data Register with FIFO (DATA)

1 0

Reserved

1 1 R Digital Input Register (DIR)

w Configuration Control register (CCR)

Isymbol

1/0 Signal Function

RD_b WR_b DMARQ

In READ DATA. This Control signal causes the host to read data from FDC to the data bus.
In WRITE DATA. This Control signal causes the host to write data from the data bus to the FDC.
Out DMA REQUEST. Requests data transfer in DMA
mode. Normally active high, but in PC/ATfM
Mode,this signal goes to high impedance when the 03 bit of DOR is O.

DMAAK_b In DMA ACKNOWLEDGE .Enables DMA cycle.
Normally active low, but in PC/ATfM Mode, this
signal is disabled when the D3 bit of DOR is 0.

In TERMINAL COUNT. Terminates data transfer.TC

is accepted only while DMAAK_b is active. TC is

active high in PC/ATfM Mode and Apple/general

Mode,and active low in PS/2TM Mode.

Note: H TC signal is not used as an input signal at the completion of the command, the Abnoraml Termination will be set (STO = 40) and End of
Cylinder will be set (STO =80). Also, see 3.1.9 Status
Register 0 and 3.1.10 Status Register 1.

INT

Out INTERRUPT REQUEST. Requests host to process

transferred data and execution results. Normally

active high,but in PC/ATfM Mode,this signal goes

to high impedance when the 03 bit of DOR is 0.

PCTYPO,

PCTYPl

PC TYPE PINS. Selects host interface mode.
PCTYPO Host l/F Mode I/F Registers

0 PS/2TM Mode

All Registers

1 PC/ATTMMode

DOR, TDR, STR,DRR, DATA,CCR

0 General Mode

DATA,STR, ORR

APPLE Mode

DATA, STR, DOR

--~====- =============:=============:==========

2.2 FDD Interface Pins (All outputs have 48m.A drive capability)

nSymbol

1/0 Signal Function

DSO-DS3_b Out DRIVE SELECT. Selects up to four standard FDDs.

MEO_b,MEl_b Out MOTOR ENABLE. Controls the M.FM FDD spindle motor on/off ; also can be used as a general-purpose

ENBLO_b /ME2_b, ENBLl_b /ME3_b.

Out DRIVE ENABLE. In Apple mode Enable 0,1 enables all communication with the Apple FDD. In other modes Motor Enable Controls the MFM FDD spindle motor on/off.

SEL/HDLD_b Out SELECT/HEAD LOAD, CAO/DIR_b, CAl/STEP_b,

CAO/DIR b

CA2/SIDE_B. Multiplexed signals defined as

CAl/STEP_B

follows:

CA2/SIDE_B

In Apple mode: SELECT_B

COMMAND ADDRESS 0-2

These lines are used for 2 reasons in Apple Mode:

1) To multiplex status to RDATA LINE during a

Read operation, and 2) To select addressable latches

on the Disk Drive during a command operation.

In other modes: HEAD LOAD. Sets drive head in the load state. DIRECTION. Specifies the seek direction.

DIR Direction

0 Inward

1 Outward

STEP PULSE. Generates seek pulses. SIDE. Selects double-sided drive head.

SIDE Drive Head

0 Head 1

1 HeadO

LSTRB

Out LINE STROBE. In Apple mode, this line is used to send a command to the drive.

Isymbol
WDATA_b

1/0 Signal Function

Out WRITE DATA. Write Data and Oock bits to FDD.

WGATE_b WPRT b (*)

Out WRITE GATE. Requests FDD to write data.
In WRITE PROTECT. Indicates medium is writeprotected.

RDATA_b In READ DATA. Read data and clock bits from FDD.

DENO_b (*), DENl_b (*)

Out DENSITY. Specifies the density of a drive that can support more than one density. The output is a value corresponding to the selected data transfer rate.

INDEX_b (*) In TRKO_b (*) In DKCG_b (*) In /READY b (*)
ENDKCG_b (*) In

INDEX PUISE. Indicates drive head is positioned at physical start point of track on the medium.

TRACK 0. Indicates drive head is positioned at cylinder O.

DISK CHANGE/READY. Indicates drive status. ENDKCG DKCG/READY

DKCG

READY

ENABLE DISK CHANGE. Enables the disk change signal (DKCG).

DRV2_b (*) In DRIVE 2 Indicates whether a second drive is installed and is reflected in Status register A (SRA).
~==================-=--=-=-~===========
= ( 11') Indicates Standard (non-Apple) FDD interface signal

2.3 Analog PLL Signals

USymbol

1/0 Signal Fundion

u>Fl, LPF2

Out LOW PASS FILTER. Phase difference of main PLL devices.

CGP1,CGP2 ======-

Out CHARGE PUMP. Phase difference of sub PLL devices.
- - - - =-==== -=--=--====--==

2.4 Other Pins
Ii symbol
DVDD
DGND
BGND

1/0 Signal Fundion

DIGITAL Voo. +5-volt power for digital circuits.

DIGITAL GROUND. Ground for digital circuits.

BUFFER GROUND. Ground for high current drivers.

AVDD

ANALOG Voo. +5-volt supply for analog PLL.

AGND

ANALOG GROUND. Ground for analog PLL.

The following four pins are used for the Boundary Scan circuit

TCK

I Cock Input

TOI

I Data Input

TMS

I Used to select modes in this test circuit

TOO

0 Data Output

======:============================--~--

2.S Output Pin Reset Status

II P i n

Reset Status

D0-07

INPUT

DMARQ, INT

In PC/ATfM Mode: In other modes :

ffiGH IMPEDANCE LOW

LPF1,LPF2, CGP1,CGP2

UNDEFINED

DSO-DS3, MEO, MEl,

ffiGH IMPEDANCE

ENBLO/ME2, ENBL1/ME3,

WDATA, WGATE, SEL/HDLD,

CAO/DIR, CAl/STEP,

CA2/SIDE, I.STRB

DENO,DENl

Depends on the data transfer rate.

=------=-======---=== -=======

2.6 Recommended Filter Parameters LPF21------------~----~-----
LPF1.______~---------.
CM2
AGN

RS1 = 6.BK
RS2 = 1.0K CS 1 = 1,BOOpF
CS2 = 22,000pF
CM1 · 4,700pF CM2 · 68,000pF

RS2 RS1 CGPl
Note: The value on CM1 & CM2 sometimes will be required to adjust depending on user's machine.

2.7 Pin Connection Diagram

DENO_B DEN1_8
TOO
TCK TMS TOI DVDD XB XA2 XA1
DGND RESET DMAAK_B

rmC/-J

1:o0r-

0
CtJ

~ l

m z

-g .~...

0
52

-m~

.~...

- -l;JJ .,,
CD 1m

47 4 45 44 43 42 41

3 35 34 33

ttiEC 55

JAPAN

29
28

58
59

uPD72070GF

2e
25

:o62 9177KK7777

22
~~

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1E 17 18 19

(WPRT_B) RDATA_B (DKCG_BIREADY_B) AVDO
LPF2 LPF1
AGND
CGP2
CGP1 PCTYPE1
PCTYPEO
DRV2
ENDKCG_B

( ) : For Standard Modes Only _B: Active Low Pins
28

Chapter 3 Internal Configuration
3.1 Registers These following registers are available on the FDC. The Status Registers (STR) may contain one of five (5) different register contents. On the resultant phase of commands, it may contain the value for STO, STI, 51'2, or ST3. Please refer to the specific command for this information.
REGISTERS 1) Status resister (STR) 2) Data register (DTR) 3) Data Rate Register (ORR) 4) PS/2 (TM) register set 4-1) Status A register (SRA) 4-2) Status B register (SRB) 4-3) Digital output register (DOR) 4-4) Digital Input register (DIR) 4-5) Configuration Control register (CCR) 5) Tape Drive Register (TOR)
STATUS REGISTERS (Available only on the Result Phase) 6) Status 0 resister (STO) 7) Status 1 resister (STl) 8) Status 2 resister (51'2) 9) Status 3 register (ST3)
29

Under Apple mode, only 3 registers are available: the Status Register (STR), Data Register (DTR) and Data Rate Register (ORR). Table 3.1 shows how to select a register by setting address signals under an operation mode.

Table 3.1 Register Selection under Operation Modes Mode PCTYPl PCTYPO CS A2 Al AO R/W Register

Apple 1

0 1 0 0 w Data Rate Register
0 1 0 0 R Status Register 0 1 0 1 W/R Data Register

PS/2 0

0 0 0 0 R Status A Register 0 0 0 1 R Status B Register 0 0 1 0 R/W Digital Output Register 0 0 1 1 W/R Tape Drive Register
0 1 0 0 w Da~ Rate Register
0 1 0 0 R Status Register 0 1 0 1 W/R Data Register
0 1 1 1 w Config. Cntl. Register
0 1 1 1 R Digital Input Register

PC/AT 0

General 1

x x

0 0 1 0 R/W Digital Output Register 0 0 1 1 W/R Tape Drive Register
0 1 0 0 w Data Rate Register
0 1 0 0 R Status Register
0 1 0 1 W/R Data Register
0 1 1 1 w Config. Cntl. Register
0 1 1 1 R Digital Input Register

0 1 .o 0 w Data Rate Register
0 1 0 0 R Status Register 0 1 0 1 W/R Data Register

1xx x

No registers accessed

3.1.1 Status Resister (STR) Apple Mode

Standard Mode

No.

Bit Name

Symbol

07 Request for Master ROM

No.

Bit Name

S_y_mbol

D7 Request for Master ROM

06 Data input/Output

DIC

D5 Execution mode

EXM

FDCbusy

D3 Drive 1 Installed

011

Drive oInstalled

DOI

FOO 1 Busy

D1B

FDDOBu~

DOB

06 Data input/Output

DIC

DS Execution mode

EXM

FDC busy

FDD3 Busy

038

FDD2Busy

028

FOO 1 Busy

018

FDDOBu~

DOB

Fig. 3.1.1 Bit Function in the Status Register

This register is a Read Only register. The function of this register is changed depending on the operation mode.

UNDER APPLE MODE:

RMQ: This bit indicates the ready state to transfer data for host. Depending on the 010 bit state, RQM bit is set as follows:

When DIO=O;

The host sends data to FDC. When the host writes data into the FDC, RQM bit is reset to 0. When FDC receives this data, RQM bit is set to a high(l). When DIO=l; FDC sends data to the host. When FDC sets data in the Data Register, RQM bit is set to a high (1). When the host reads this data from the Data register, RQM bit is reset to 0.

DIO:

This bit indicates the direction of the data transferred between the host and the FDC. When this bit is reset as 0, data is transferred from the host to the FDC. When this bit is set as a high (1), data is transferred from the FDC to the host.

EXM: This bit indicates that data is being transferred by using the Non-OMA mode during the Execution phase. This bit is reset during the command phase.

CB: This bit indicates that the FDC is in the command phase, the execution phase if the read/write groups commands or the result phase. When this bit is set, no commands should be written to the Data Register.

DU: This bit indicates a second floppy disk drive is installed in the system.

DOI: This bit indicates the first floppy disk drive is installed in the system.

DlB: DlB:

This bit indicates the the Seek Group commands are being performed on the second drive or a Seek Operation termination interrupt is pending. Read/Write commands must not be issued when this bit is active.
This bit indicates the the Seek Group commands are being performed on the first drive or a Seek Operation termination interrupt is pending. Read/Write commands must not be issued when this bit is active.

UNDER STANDARD MODES:
RMQ: This bit indicates the Ready state to transfer data for host. Depending on the DIO bit state, RQM bit is set as follows: When DIO=O; The host sends data to FDC. When the host writes data into the FDC, RQM bit is reset to O. When FDC receives this data, RQM bit is set to a high(l). When 010=1; The FDC sends data to the host. When FDC sets data in the Data Register, the RQM bit is set to a high (1). When the host reads this data from the Data Register, RQM bit is reset to 0.
DIO: This bit indicates the direction of the data transferred between the host and the FDC. When this bit is reset as 0, data is transferred from the host to the FDC. When this bit is set as a high(l), data is transferred from the FDC to the host.
EXM: This bit indicates that data is being transferred by using the Non-DMA mode during the Execution phase. This bit is reset during the command phase.
CB: This bit indicates that the FDC is in the command phase, the execution phase if the read/write groups commands or the result phase. When this bit is set, no commands should be written to the Data Register.
D3B: This bit indicates the the Seek Group commands is being performed on the fourth drive or a Seek Operation termination interrupt is pending. Read/Write commands must not be issued when this bit is active.
D2B: This bit indicates the the Seek Group commands is being performed on the third drive or a Seek Operation termination interrupt is pending. Read/Write commands must not be issued when this bit is active.
DlB: This bit indicates the the Seek Group commands is being performed on the second drive or a Seek Operation termination interrupt is pending. Read/Write commands must not be issued when this bit is active.
DOB: This bit indicates the the Seek Group commands is being performed on the first drive or a ~ Operation termination interrupt is pending. Read/Write commands must not be issued when this bit is active.

3.1.2 Data Register (DTR)
This register consists of programmable length data FIFO with a maximum length of 16-bytes for data. Commands are also sent to this register but only one command byte is stored at one time.

3.1.3 Data Rate Register (DRR)

No.

Bit Name

Symbol

D7 Resets b_y_ Software SIWRST

D6 enters standb_y mode STDBY

reserved

PCS2

sets values for precompensation

PCS1

PCSO

sets Data rate

DRATE1

DRATEO

Fig. 3.1.3.1 Bit function

This Write Only register is available under any operation mode.

S/WRST: When this bits is set high (1), the FDC enters into the reset condition. This bit is automatically reset by itself.

STDBY:

When this bit is set high (1), the FDC enters into the power down mode. In power down mode, all circuits are turned off. The FDC will terminate this mode after the reset condition, or when any register is read or written by the host.

PCS2-0: These bits select the preshift value of the write precompensator the FDC will use on the WDATA disk interface output. Table 3.1.8.1 shows the values for these bits.

In Apple Mode while recording in GCR, the precompensation value is always set to zero, independent of the bits (PCS2-PCSO) in the ORR register.

Table 3.1.8.1 PCS bits v.s. Preshift values

2ED/2IID/2DD

2TD

PCS2 PCSl PCSO Value{nsl

Value(ns}

0 0 0

Reset default

0 0 1

41.7

50.0

0 1 0

83.3

100.0

0 1 1

125.0

150.0 Apple's MFM value

1 0 0

166.7

200.0

1 0 1

208.3

Not used

,1 1 0

250.0

Not used

1 1 1

0.0

Table 3.1.8.2 preshift values after reset condition

2ED/2IID/2DD 2TD

Data RateCkb;es} 1000 500 300 250

value{ns}
41.7 - 125.0
- 125.0 - 125.0

value{ns}

1250

50.0

DRATEl-0: These bits determine the c:lata rate to be used. The data rates for MFM format are shown in Table 3.1.8.3. For FM format, the data rates become a half of the shown values in this figure. For data rates under Apple mode, these bits should be set as (DRATEl, DRATEO) = (O,O) or (DRATEl, DRATEO)=(l,1).

Table 3.1.8.3 ORATE bits v.s. Data Rates

DRATEl DRATEO ·Data rateCkbj:>s)

500/489.6

300

250 (Reset default)

1000/1250 (lOOOkbps is for 2ED media, 4MB)

(1250kbs is for 2TD media; 13MB)

3.1.4 Status Register A (SRA)

No.

Bit Name

Symbol

07 Pend~ lnterru--2.t

PINT

06 Installed drive 2 DRV2 B

Step sig_nal

STEP

TrackO~nal

TRKO B

03 Side select signal

SIDE

Index signal

INDEX_B

01 Write--2.rotect si_gnal WPRT B

Direction s.!9._nal

DIR

Fig. 3.1.4 SRA Bit Function

This Read Only register is available under Standard Modes only.

Symbol Active Level Description

PINT

High

Reflects the state of the INT pin.

DRV2_B Low

Reflects if a second drive has been installed or not.

STEP

High

Reflects the state of the STEP_B pin in the drive interface.

TRKO_B

Low

Reflects the state of the TRKO_B pin in the drive interface.

SIDE

High

Reflects the state of the SIDE pin in the drive interface.

INDEX_B Low

Reflects the state of the INDEX_B pin in the drive interface.

WPRT_B Low

Reflects the state of the WPRT_B pin in the drive interface.

DIR

High

Reflects the state of the DIR pin in the drive

interface.

3.LS Status Register B (SRB)

No.

Bit Name

reserved

Symbol 1

reserved

Drive SelectO

DSO

04 Write Data signal WDATA

D3 Read Data signal RDATA

D2 Write Gate ~nal WGATE

Motor On 1

M01

MotorOnO

MOO

Fig. 3.1.5 SRB Bit Function

This Read only Register is available under Standard Modes only.

Smibol DSO WDATA RDATA WGATE MOl-0

Active Level High High High High High

0eScri]2tiQn
Reflects the state of the DSO_B pin in the drive interface.
Reflects the state of the WDATA_B pin in the drive interface.
Reflects the state of the RDATA_B pin in the drive interface.
Reflects the state of the WGATE_B pin in the drive interface.
Reflects the state of the MEl-O_B pins in the drive interface.

3.L6 Digital Output Register (DOR)

No.

Bit Name

s_ymbol

07 Enables Motor On 3 06 Enables Motor On 2 05 Enables Motor On 1

EM3 EM2 EM1

04 Enables Motor On O 03 Enables host interface

EMO EHIF

Enables FDC

selects drives

RST_B 0$1 DSO

Fig. 3.1.6 DOR Bit Function

This Write Only register is available under Standard Modes only.

Symbol EM3-0 EHIF RST_B
DSl-0:

Active Level
High High
Low
See Chart

Description
Enable the Motor Enable Signals (ME3-0_B).
Enables the host interface signals INT, DMARQ, DMAAK_B and TC.
Resets the FDC. Setting this bit to a "O" resets the controller. Setting this bit to a "l" enables the controller for operation.
These bits select a floppy disk drive as the target to be read or written. The external Drive Select signals (DS3-0_B) become active according to the EM3-0bits.

bits in the Digital Output register
EM3 EM2 EM1 EMO DS1 DSO
0 0 0 0 xx
0 00 100 0 01001 0 10010 1 000 11

extemal signals from FDC

DS3 B DS2 B 081 B DSO B

3.1.7 Digital Input Register (DIR)

No.

Bit Name

Symbol

OiskCh~e

OSK CHG

reserved

Fig. 3.1.7 DIR Bit Function

This Read only Register is available under Standard Modes only.

Symbol Active Leve! DSKCHG High

Description
Reflects the state of the external pin,
DKCG/READY_B, when the external pin, ENDKCG_B is set low. If this ENDKCG_B is set high, this register can not be accessed from the host.

3.1.8 Configuration Control Register (CCR)

No.

Bit Name

reserved

Symbol
-
-

selects data rate

ORATE1

ORATEO

Fig. 3.1.8.1 CCR Bit Function

This Write Only register is available under Standard Modes only.

Symbol DRATEl-0

Active Level See Chart

Description
Determines the data rate to be transferred. The data rates for MFM format are shown in Figure 3.1.8.2. For FM format, these data rates become a half of the values shown.

Fig. 3.1.8.2 ORATE bits v.s. Data Rates for MFM format

DRATEl ORATED Data rate(kbps)

0 0

500

0 1

300

1 0

250 (reset default)

1 1

1000/1250 (lOOOkbps is for 2ED media, 4MB)

(1250kbs is for 2TD media, 13MB)

3.1.9 Tape Drive Register (TOR)

No.

Bit Name

reserved

01 selects Tape drives DO

S}'ll"lbol
-
-
-
TDS1
TOSO

Fig. 3.1.9 TDR Bit Function

This Read and Write register is available under Standard Modes only.

Symbol TDSI-0:

Active Level

Description
These bits are not used in this FDC. These bits are
necessary for this FDC to be compatible with the
INTEL 82077.

3.1.9 Status Register 0 (STO)

NO.

Bit Name

07:6 Interrupt Code

Symbol IC

Seek End

04 Equipment Check

Not Ready

l'R

Head Address

Floppy in

FIN

Drive

lJ:t

Symbol 07-06

Active Level Description · See Chart Indicates the causes of the INT request

D7 D6 0 0 0 1 1 0 1 1

Indicated causes Normal termination of command execution Abnormal termination of command execution Invalid command issued Under Apple Mode:
/CSTIN state change, floppy media inserted or removed Under standard modes:
Indicates a changed status of FDO

High

This bit is set when a seek operation by Seek or

Recalibrate command is terminated normally or

abnormally

High

Under Apple mode, this bit is set when errors at

the FOO occur. Under Standard modes, this bit is

set when the TR.KO signal can not be detected

within a certain period in execution if the

Recalibrate command.

High

Under Apple mode, this bit reflects the /Ready

status in the drive interface. Under standard

modes, this bit reflects the READY_B pin.

High

This bit indicates the head status at the time of the

INT request. This bit is set to zero when Sense

Interrupt Status command is executed.

High

Under Apple mode, this bit reflects the /CSTIN

status in the drive interface. Under standard

modes, this bit indicates the drive number (DRl),

as same as the drive select bit (DRl) in the

command, at the time of the INT request.

High

Under all modes, this indicates the drive number

(ORO), as same as the drive select bit (ORO) in the

command, at the time of the INT request.

3.1.10 Status Register 1 (STI) No. Bit Name D7 End of Cylinder

Swbol EN

DS Data Error

Overrun

No Data

Function

This bit is set when read or write is attempted beyond the last sector specified by the EOT byte. (TC signal is NOT INPUT)

This bit is always set to zero.

Under Apple mode, this bit is set when the checksum error at the ID field or Data field is detected. DD bit (DS) of Status Register (ST2) specifies either ID or Data field.

This bit is set when data transfer service by the host is not performed within the specified amount of time at the data transfer.

This bit is always set to zero.

1) This bit is set if the sector specified

by the IDR can not be detected on the

track when any one of the following

five commands is executed:

-Read Data

- Read Deleted Data

-Write Data - Write Deleted Data

- Scan group commands

2) This bit is set when an ID with no

CRC error or no checksum error is

Not Writable

DO Missing Address Mark MA

not detected on the track in the execution of Read ID command.
3) This bit is set when the sector ID and the contents of the specified IDR does not matched at the Read a Track command execution.
This bit is set when the write protect signal is detected by execution of a write group commands.
l)This bit is set when the IDAM can not be found before two index pulses (or the allowable period ) are detected by the execution of a command that accesses the ID of the disk. 2)This bit is set when the DAM or ODAM can not be found after the IDAM is found. MD bit of Status register (51'2) is also set at this time.

3.1.11 Status 2 Register (ST2) No. Bit Name 07 D6 Control Mark

S;mibol CM

05 Data Error in Data field DD

D4 No Cylinder

Scan Equal Hit

02 Scan Not Satisfied SN

Function
This bit is always set to zero.
This bit is set when the ODAM is detected at the Read Data, Read a Track or Scan group commands execution or when the DAM is detected at the Read Deleted Data execution under MFM format.
This bit is set when the checksum error at the Data field is detected.
When either C byte of ID matches nor $FF, this bit is set together with ND bit of Status register 1 (STI).
This bit indicates the Equal condition to be occurred at the scan group commands.
This bit is set when the condition is not satisfied at the scan group commands.

Bad Cylinder

Missing DAM MD

3.L12 Status Register 3 (ST3) Apple Mode No. §it Name
07 2MB/4 MB Media

S~bol
Media

D6 Write Protect

Ready

Track 0

03 2MB-4MB drive

Drive

Mode ID

Mode

Dl Select media

SelMedia

MFMmode

This bit is set together with the ND bit of Status register 1 (STl) when the C byte of ID field is $FF. This bit is set when the Data Address Mark (DAM) or ODAM can not be found after the IDAM is found.
Function
This bit reflects the /2MB or I 4MB
media status from the drive. This bit reflects the /Write protect status from the drive. This bit reflects the /Ready status from the drive. This bit reflects the TrackO status from the drive. This bit reflects the 2MB-4MB drive status from the drive. This bit reflects the Mode ID status from the drive. This bit reflects the Select Media status from the drive. This bit reflects the MFM Mode status from the drive.

Standard Modes

No. Bit Name

Fault

D6 Write protect

Ready

TrackO

Two Side

02 Head Address

Symbol FI' WP
RY
TO
TS HD

Function This bit is always set to zero.
This bit reflects the WPRT_B pin in the drive interface.
This bit reflects the READY_B pin in the drive interface.
This bit reflects the TRI<O_B pin in the drive interface.
This bit is always set to high (1).
This bit reflects the SIDE_B pin in t

Dl Drive Select 1 DO Drive select 0

he drive interface.

DRl

This bit reflects the DRl bit in the

issued command.

ORO

This bit reflects the ORO bit in the

issued command.

3.2 System Interface Control
The block diagram shown in Figure 3.2.1 shows the functional blocks that handle the transfer of data between the host and this FDC.

Fig. 3.2.1 72077 System Block Diagram

XA._~

"'""''--~ Clock

Generator

(OSO)
~OS1)
DS2) DS3)

Status Register

Command Registers
Drive Interface Control
Systemco

Drive Interface

(MEO) (ME1)
EENNBBLL11EE23~
SEL D ) CAO DIBl CA1 STEP) CA2 (SIDE) LSTRB
DENO
DEN1
INDE~ ~i) CKGC/RGE)ADY)

087

FIFO

Data · Register

ntrol

(DRV2)

Tape Drive Register
System

Serial Interface Control

Precomp Control

WDATA

1-------...- WGATE

Analog VFO

RDATA

Interface

Control

RESET

PClYPO

PC1YP1

( ) : For standard FOO

3.3 Serial Interface Control This block is used to change data from bytes to serial bits and from serial bits to bytes for the read/write groups commands.
3.4 Drive Interface Control This block is used to handle the output signals to FDDs and the input signals from FDDs.
3.5 Drive Interface This block consists of the high current drivers and the receivers for FDD signals.
3.6 Analog PLL This block generates the Read-clock to be synchronized with the RDATA signal from FDD.
3.7 System Cock Generator This block generates the internal clocks required for the internal blocks from XA and XB clock source.
3.8 Precompensator Control This block generates the WDATA signal to be preshifted according to the programmed value. Under GCR mode, this block is always disabled.
46

Chapter 4 Commands
The following is an explanation of Common Parameters in commands used in the FDC:
FM (Recording Mode Format) Under Apple mode, the FDC can operate in MFM recording mode when this bit is set l(high) and the FDC can operate in GCR recording mode when this is set O(low). Under Standard modes, the FDC can operate in MFM recording mode when this is set l(high) and the FDC can operate in FM recording mode when this is set O(low).
MT (Multi Track) When this bit is !(high), the operation to Read or Write for multi tracks is specified.
TB (Tag Byte for GCR recording) During operations that write data to the FDD, when this is !(high), the data for the Tag byte field must be transferred from the host to the FDC. During operations that write data to the FDD, when this is O(low), the Tag byte field is automatically filled with "O". This does not require any transfer from the host. During operations that read data from the FDD, when this is 1(high), the Tag byte field is transferred from the FDC to the host. During operations that read data from the FDD, when this is O(low), the Tag byte field is not transferred.
SK (SKIP under standard modes) When this bit is l(high) and FDC detects the DDAM during operating the Read Data command or when this is !(high) and FDC detects the DAM during operating the Read Deleted Data command, the data in the data field to be transferred are skipped. When this bit is O(low), the data in the data field are transferred.
HD(Head) Specifies the physical head number. When this bit is l(high), side 1 is selected and when this is OOow), side 0 is selected.
DRl,0 (Drive Select) Specifies the drive number from 0 to 3.
CYLINDER Indicates the cylinder number
47

Gap4 is located from the last position of the last sector from the index position.
49

.Configure

Phase command
Execution

RN/ 07 06 05 04 03 02 01 DO

Remarks

w 0 0 0 1 0 0 1 1 command code

w 000 00 0 00

w 0 EIS EFOPOLI FIFOTHR

PRETRK

Sets parameters as specified.

FUNCTION The host uses this command to set several internal parameters in the FDC.

PARAMETERS

EIS

Under only Standard modes, the EIS enables the FDC to

perform the Seek command before the FDC performs the

Read/Write groups commands without issued Seek command. When EIS is set a high(l), this implied seek function becomes active.

EFO

The EFO bit is used to enable the Data FIFO in the FDC. When

this EFO is set a low (0), the Data FIFO is enabled. When this

EFO is high (1), the Data FIFO is disabled.

POL

The POL bits is irrelevant to the FDC operation.

FIFOTHR Once the EFO bit is set a high(l), the FIFOTHR bits is used to determine the threshold of the Data FIFO during the FDC is operating the Read/Write groups commands in the Execution phase. This threshold can be programmed from 1 to 16 bytes.

PRETRK The PRETRK bits are used to specify the track to begin precompensation of the FDD write data .

ERROR CONDmONS There are no error condition for this command.

Disable/Enable DPLL

Phase command
Execution

R/W D7 D6 D5 D4 D3 D2 D1 DO

Remarks

w DL 0 0 0 1 0 1 1 command code

w x x x x x x X DR

/DPLL sets to specified value

FUNCTION
Under Apple mode only, the effect of this command is to set the /DPLL command bit in the FDD. This disables the integrated Digital Phase Lock Loop (DPLL) in the FDD. The FOC will not handshake this command.

DL = "O" DPLL DISABLED DL = "1" DPLL ENABLED
ERROR CONDmONS This command has no error condition because this command is used only in a development environment.

Dump reg

Phase command
Result

RMI D7 D6 D5 D4 D3 D2 D1 DO

Remarks

w 0 0 0 0 1 1 1 0 command code

PCNO

Dumps internal used

PCN1

parameters.

PCN2

PCN3

I Step Rate

Head Unload time

Head Load time

I ND

Number of Sectors per Track

(or End of Track)

reserved

A 0 EIS EFOPO~ FIFOTHR

PRETRK

FUNCTION The host can get the internal parameters to be used in the FDC by using this command. This command can be used under Standard modes.
ERROR CONDmONS This command has no error conditions.

Phase command
Execution

Eject Disk

RAf.I 07 06 05 04 03 02 01 DO

Remarks

w 0 1 0 1 0 0 1 0 command code

w x x x x x x x DR

Floppy disk is ejected from FDD by asserting /EJECT control sj_g_nal

FUNCTION
Under Apple mode only, this command is used to programmatically eject the floppy in the selected drive. This is done by writing the /Eject control bit in the specified drive. Immediately after asserting the /Eject command to the FDD, the FDC will issue a normal termination interrupt.

ERROR CONDmONS
Due to the extremely long time, it takes to execute an Eject command, there is no handshaking done by the FDC. In normal operation, the host will be notified of the completion of the Eject command via an interrupt indicating the change in the /CSTIN status line. This can be used to verify that the media has been properly ejected.

Format A Track

Phase Command
Execution

WW 07 06 05 04 03 02 01 DO

Remarks

w 0 FM TB 0 1 1 0 1 command code

w x x x x x HD DR1 ORO

w (Bytes/Sector) I Format Byte

Sectors/Track

w GAP3(MFM) I #Sync Groups(GCR}

Filler B_rte

FOC formats the entire track

Status Regisiter O

status information

Status Regisiter 1

after this command

Status Regisiter 2

Cylinde r(irrelevant)

Head(irrelevant)

Sector(irrelevant)

lBvtes/~· ;tur:ll. FJ2rmat Bvte

FUNCTION
This command allows an entire track to be formatted. The host must send new values for the cylinder, head, sector and the number of data bytes, to the FDC for each sector to be formatted during the execution phase of this command. If the FDC is in OMA transfer mode, it will issue four OMA requests per sector for the cylinder, head, sector and the number of data bytes for each formatted sector.
If the FDC is in non-OMA transfer mode, it will issue four interrupts per sector and the host must supply the cylinder, head, sector and the number of data bytes for each formatted sector.
For MFM or FM recording, data is written on the disk after the index hole is detected. But for GCR recording, the write can begin anywhere on the track. The host specifies the format of the track by the parameters passed during the command phase. Tag bytes transfer is controlled by the TB parameter.

PARAMETERS

BYTES/SECTOR This is used as the number of bytes in a sector. For GCR recording, this byte should be either 12H, 22H

or 24H. All these hexidecimal values (12H, 22H or 24H ) represent 512 bytes of data and 12 Tag bytes. For MFM recording, see the following;

Bytes/Sector(16) 00 01 02 03 04 05 06

Bytes in a sector

MFM

inhibited

128

256

512

1024

2048

4096

8192

Note ·1: GAP3 in this case should be set less than 128bytes.

SECTORS/TRACK

This is used as the number of sectors in a track.

# SYNC GROUPS(GCR) I GAP3(MFM)

For GCR recording, this specifies the number of the Self Sync byte group. And for MFM recording, this specifies the number of the bytes in the GAP3.

FILLER BYTE

This byte is written into the data field as the data pattern.

ERROR CONDmONS
Errors occur under the following conditions: - The WPRT status becomes active. - The overrun or underrun occur during the data transfer. - When utilizing the TC input, it does not meet the correct timing period.
Under Apple mode: - The /CSTIN status in the drive interface is inactive before this is operated.
Under any mode: - The Ready status at the drive interface iS inactive before this is operated.

Format/Write

Phase command
Execution

RN/ 07 06 05 04 03 02 01 DO

Remarks

w OFMTBO 0 0 0 1 command code
w x x x x x HD DR1 ORO

w (Bytes/Sedor) I Format Byte

Sectors/Track

w GAP3J_MFMJ_/# S_ync Grou_Q_s_{_GCfU

track data is passed to FDC as in a write operation

Status Regisiter O

status information

Status Regisiter 1

after this command

Status Regisiter 2

Cylinder(irrelevant)

Head(irrelevant)

Sector(irrelevant)

1B~es/Sedori I Format B_yte

FUNCTION
This command is virtually the same as the Format a Track command with the exception that the filler byte in not specified. Instead, the host transfers the data as in the Write Data command. This capability is required to optimize when writing data and to support GCR recording on perpendicular FOO drives.
This command allows an entire track to be formatted.
The host must send new values for the cylinder, head, sector and the number of data bytes, to the FOC for each sector to be formatted.

PARAMETERS These parameters are same as that of the Format a Track command.

ERROR CONDmONS Errors occur under the following conditions:
- The WRITE PROTECT status is active.
- The overrun or underrun occur during the data transfer.
- Under Standard I Apple modes, the drive interface indicates a
NON_READY drive status.

Invalid
In the following two cases, 10(2) (IC: Invalid Command) is set to the Interrupt code (high bits) of STO, and is set to all remaining bits (ST0=80H).
· When an undefined command code is issued · When the Sense Interrupt Status command is activated even though
an INT request by termination of the seek group commands or by a drive status change is not generated.
57

Perpendicular Mode

Phase command
command

FWI D7 D6 05 D4 D3 D2 D1 DO
w 00 0 10 0 10
x x x x x x D1 DO

Remarks
command code Echo back for this command.

FUNCTION
The Perpendicular Mode command should be issued prior to executing
READ I WRITE I FORMAT commands that access a disk drive with
perpendicular recording capability. With this command, the length of the GAP2 field and VCO enable timing can be altered to accommodate the unique requirements of these disk drives. Please refer to the following table for the perferred settings. Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate register. The User must ensure that the two data rates remain consistent.

D1 00

MODE

VCOL.aw l.englhol Portion of Gap2 Gllp2VCO

Tmeaflllr Gap21onnat WrittenDy Write Law time/

NlEX

Fielcl Data Opera.lion Read()p.

0 ponventional Mode 33 Bytes 22 Bytes O Bytes 24 Bytes

133 1

Perpendicular Mode SOOKbps

Bytes 22 Bytes 19Bytes 24 Bytes

1 0 RESERVED

133 o Bytes 22 Bytes Bytes ~4 Bytes

Perpendicular Mode 18 Bytes 41 Bytes 38 Bytes 43 Bytes 1Mbps

Write Gate

\_____ Effects of Perpendicular Mode in GCR and MFM Formats Write Gate

Write Data

Valid Write Data

Write Data
Read Data ------<(Valid Read Data

T1 VALUES GCB 1MB <MEM) 2MB IMFMI 4MQ (MEM)
154 usec 304 usec 304 usec 304 usec

T1 VALUES GCR 1MB (MfM) 2MB (MFM) 4MQ fMfMl 190 usec 190 usec 340 usec 340 usec

Raw Dump

Phase command
Execution

'RNtl D7 D6 DS D4 D3 D2 D1 DO

Remarks

I I w 0 FM 0 1 1 1 1 0 command code
w x x x ROM HD OR1 ORO

Cylinder

Head

Sector

Sector Number

Bytes to dump{MSB)

# of bytes is a 16-bit

B_rtes to dum_Q_{_LSBl

unsigned long integer

Data is passed back to Host. GCR is returned encoded.

Status Regisiter O

status information

Status Regisiter 1

after this command

Status Regisiter 2

Cylinder(irrelevant)

Head(irrelevant)

Sector(i rrelevant)

Number of data bytes

.h iI u.firr"'1""' ·1.ntl

FUNCTION Under Apple mode only, this command supports the following three dump modes:
- Dump from the Index Address Mark - Dump after the specified ID Address Mark - Dump after the Data Address Mark

In addition, the FDC begins to transfer data after the FDC is synchronized to the nearest available mark in incoming Data from FDD. After the FDC starts to transfer data, it may be possible for the FDC to lose synchronization with the incoming data because of write splices. If this occurs, meaningless data will be transfered to the host.
The detected mark byte, which the FDC starts to dump data from, is defined under the MFM format that this mark byte is located after the SYNC bytes and the Data and Clock bytes of this mark byte is equal to either $Al for Data byte and $0A for Oock byte or $C2 for Data byte and $14

for Cock byte.
On the other hand, the detected mark byte is also defined under the GCR format that this mark byte is located after the SYNC bytes and the Data byte of this mark byte is equal to $05, which is the.first data of either Address mark bytes or Data Address mark bytes.
Regarding transfered data under the ONLY MFM FORMAT, the FDC transfers one Data byte and one Clock byte from FDD to the host repeatedly. The host should check what Clock byte has missing clock bits by itself. This transfer is called as the 8 X 8 data transfer and is described later for further detailed. Under the GCR format, the raw data from the FDD should be transfered to the host without denibbling.

1) DUMP FROM INDEX ADDRESS MARK
Under MFM format only, this dumps the requested number of bytes from the track specified, immediately after the Index pulse is input to the FDC and the SYNC bytes are detected and then the Index Address mark, which consists of both the data byte with $C2 and the Cock byte with $14, is detected. The data that is transfered to the host will include the Index address mark itself and the track data according to the rule of the 8 X 8 data transfer.
But under the GCR format, this mode is illegal because the FDD can not output the Index pulse from itself.
When the RDM bits are set to "00", this mode can be entered.
In this mode, the FDC ignores the following errors after the first Address mark is found.
- Read error for CRC for the MFM format
- Read error for Address Mark in the Data field
INDEX
Pulse

GAP 4E ··· 4E

Sync byte

INDEX markbyte

GAP

00···o C2 C2 C2 FC 4E ··· 4E

ID field - - - -.....-~

Sync byte

Address mark

address header

GAP2

.... 00···o A1 A1 A1 FE c H s N a:c 4E -·· 4E

transfered data from this point from
Fig. 4.18.1 Transferred Data for Dump From Index Address Mark

2) DUMP AFI'ER SPECIFIED ID ADDRESS MARK When the RDM bits are set to "01 ", this mode can be entered under the only Apple mode. This dumps the requested number of bytes from the specified track. Especially under the MFM format, after the FDC finds out the specified ID address mark and then the nearest SYNC bytes, the FDC checks whether the next data after these SYNC bytes is equal to the Mark byte, which is expected as the $Al for Data byte and the $0A for Clock byte. If this mark is hit, the FDC should start to dump data from and including this Mark byte. But if the Mark byte can not be hit, the FDC changes the expected Data for the Mark byte from the above data to the $C2 for Data byte and the $14 for Clock byte and then the FDC resumes to sear.ch the same specified ID field. After the FOC finds out the specified ID address mark and then the nearest SYNC bytes, the FDC checks whether the next data after these SYNC bytes is equal to the Mark byte, which is expected as the $C2 for Data byte and the $14 for Clock byte. If this mark is hit, the FDC should start to dump data from and including this Mark byte. But if the mark byte can not be hit, the FDC abnormally terminates the command and interrupts to inform to the host this abnormal termination. For GCR format, after the FDC finds out the specified ID address mark, the FDC is waiting to receive the Mark byte with the $D5 for Data byte. If this mark is hit, the FDC should immediately start to dump data from and including this Mark byte. But if the mark byte can not be hit, the FDC abnormally terminates the command and interrupts to inform to the host this abnormal termination. In addition, the FDC dumps the data without denibblizing the read-data from the FDD. The Fig. 4. 18. 2 is shown as a example of this mode. In this example, the Data Address mark is located after the specified ID field and the SYNC bytes. In this dumped mode, the FDC ignores the following errors after the first Address header is found out - Read error for CRC for the MFM format or Checksum for the GCR format - Read error for Bit slip byte for the GCR format - Read error for Address mark in the Data field
61

Symbol
BC CB CM DOB D01 D1B D11 DD DE DIO DR DRATEO DRATE1 Drive EC EN
EXM
FIN HD IC{1) IC(2) MA MO Media MFM Mode NC ND NR NW OR
PCSO PCS1 PCS2
RQM RY
S/WRST SE
SelMedia SH SN STD BY
TO
WP

Name
Reserved Reserved Reserved Reserved
Bad Cylinder FDC Busy Control Mark Drive 0 Busy
Drive 0 Installed
Drive 1 Busy Drive 1 Installed Data Error in Data Field Data Error Data Input/Output Drive Data Rate(O) Data Rate(1 ) 2MB/4MB Drive Equipment Cleek End of Cylinder Execution Mode
Roppy In
Head Address Interrupt Code(1) Interrupt Code(O) t.tssing Address Mark Mssing Data Mark 2MB/4MB Mecla MFMMode Mode ID No Cylinder No Data Not Ready Not Writable Overrun Precompensation(O) Precompensation(1) Precompensation(2) Request for Master Ready FDC Software Reset Seek End Select Media Scan Equal Hit Scan not Satisfied Standby Mode
Track 0 Write Protect

Location
DRR(S) . ST1(6) ST1(6) ST2(7)
ST2(1) STR(4) ST2(6) STR(O) STR(2) STR(1) STR(3) ST2(5) ST1(5) STR(6) STO(O) DRR(O) DRR(1)
ST3(3) ST0(4) ST1(7) STR(S) ST0(1) ST0(2) ST0(7) ST0(6) ST1(0) ST2(0) ST3(7)
ST3(0)
ST3(2) ST2(4) ST1(2) ST0(3) ST1(1) ST1(4) DRR(2)
DRR(3)
DRR(4) STR(7)
ST3(5)
DRR(7) STO(S) ST3(1) STZ(3) ST2(2) DRR(6)
ST3{4)
ST3(6)

199

8.4.1.2 State Description.
The Behavior of the TAP controller in each of the controller states is briefly described as follows:
Test-Logic-Reset The JTAG implemented into the FDC is disabled so that normal operation of the FDC system logic can continue unhindered. This is achieved by initializing the instruction register to contain the BYPASS instruction. No matter what the original state of the TAP controller, it will enter Test-LogicReset when TMS is held high for at least five rising edges of TCK. The TAP controller remains in this state while TMS is high. If the TAP controller should leave the Test-Logic-Reset TAP controller state as a result of an erroneous low signal on the TMS line at the time of a rising edge on TCK (for example, a glitch due to external interference), it will return to the Test-Logic-Reset state following three rising edges of TCK with the TMS line at the intended high logic level. The operation of the test logic is such that no disturbance is caused to the FDC logic operation as the result of such an error. On leaving the Test-Logic-Reset controller state, the TAP controller moves into the Run-Test/Idle controller state where no action will occur because the current instruction has been set to select operation of the bypass register. This JTAG logic is also inactive in the Select-DR-Scan and Select-IRScan controller states.
Run-Test/Idle
This is a TAP controller state between scan operations. Once entered, the TAP controller will remain in the Run-Test/Idle state as long as TMS is held low. When TMS is high and a rising edge is applied at TCK, the TAP controller moves to the Select-DR-Scan state. In the Run-Test/Idle controller state, activity in a certain selected instruction occurs only when certain instructions are present. For instructions that do not cause functions to execute in the Run-Test/Idle controller state, all test data registers selected by the current instruction retains their previous state (i.e., Idle).
The instruction does not change while the TAP controller is in this state.
Select-DR-Scan This is a temporary controller state in which Boundary -Scan and Bypass registers selected by the current instruction retain their previous state.
If TMS is held low and a rising edge is applied to TCK when the TAP controller is in this state, then the TAP controller moves into the Capture-DR
182

state and a scan sequence for the selected register is initiated. If TMS is held high and a rising edge is applied to TCK, the TAP controller moves on to the Select-IR-Scan state. The instruction does not change while the TAP controller is in this state.
Select-IR-Scan This is a temporary controller state in which Boundary-Scan and Bypass registers selected by the current instruction retain their previous state. If TMS is held low and a rising edge is applied to TCK when the TAP controller is in this state, then the TAP controller moves into the Capture-IR state and a scan sequence for the Instruction register is initiated. If TMS is held high and a rising edge is applied to TCK, the TAP controller returns to the Test-Logic-Reset state. The instruction does not change while the TAP controller is in this state.
Capture-DR In this controller state, data are parallel-loaded into Boundary-Scan registers selected by the current instruction on the rising edge of TCK. The instruction does not change while the TAP controller is in this state. When the TAP controller is in this state and a rising edge is applied to TCK, the TAP controller enters either the Exitl-DR state if TMS is held at 1 or the Sift-DR state if TMS is held at 0.
Shift-DR In this controller state, either Boundary-Scan or Bypass register connected between TDI and TDD as a result of the current instruction shifts data one stage towards its serial output on each rising edge of TCK. Boundary-Scan and Bypass register that are selected by the current instruction, but are not placed in the serial path, retains their previous state unchanged. The instruction does not change while the TAP controller is in this state. When the TAP controller is in this state and a rising edge is applied to TCK, the TAP controller enters either the Exitl-DR state if TMS is held at 1 or remains in the Shift-DR state if TMS is held at 0.
Exitl-DR This is a temporary controller state. If TMS is held high, a rising edge applied to TCK while in this state causes the TAP controller to enter the Update-DR state, which terminates the scanning process. If TMS is held low and a rising edge si applied to TCK, the TAP controller enters the Pause-DR state.
183

Boundary-Scan and Bypass registers selected by the current instruction retain their previous state unchanged. The instruction does not change while the TAP controller is in this state.
Pause-DR This controller state allows shifting of either Bypass or Boundary-Scan register in the serial path between TOI and TOO to be temporarily halted. These registers selected by the current instruction retain their previous state unchanged. The TAP controller remains in this state while TMS is low. When TMS goes high and a rising edge is applied to TCK, the TAP controller moves on to the Exit2-DR state. The instruction does not change while the TAP controller is in this state.
Exit2-DR This is a temporary controller state. If TMS is held high and a rising edge is applied to TCK while in this state, the scanning process terminates and the TAP controller enters the Update-DR controller state. IF TMS is held low and a rising edge is applied to TCK, the TAP controller enters the Shift-DR state. Bypass and Boundary-Scan registers selected by the current instruction retain their previous state unchanged. The instruction does not change while the TAP controller is in this state.
Update-DR Boundary-Scan register is provided with a latched parallel output to prevent changes at the parallel output while data is shifted in the associated shiftregister path in response to certain instructions (e.g., EXTESTI. Data is latched onto the parallel output of this register from the shift-register path on the falling edge of TCK in the Update-DR controller state. The data held at the ·1atched parallel output should not change other than in this controller state. All shift-register stages in Boundary-Scan register selected by the current instruction retain their previous state unchanged. The instruction does not change while the TAP controller is in this state. When the TAP controller is in this state and a rising edge is applied to TCK, the TAP controller enters either the Select-DR-Scan state if TMS is held at 1 or the Run-Test/Idle state if TMS is held at 0.
Capture-IR
184

In this controller state, the shift-register contained in the instruction register loads the pattern (01 binary) of fixed logic values on the rising edge of TCK. Either Bypass or Boundary-Scan register selected by the current instruction retain their previous state. The instruction does not change while the TAP controller is in this state. When the TAP controller is in this state and a rising edge si applied to TCK, the TAP controller enters either the Exitl-IR state if TMS is held at 1 or the Shift-IR state if TMS is held at 0.
Shift-IR In this controller state, the shift-register contained in the instruction register is connected between IDI and TOO and shifts data one stage towards its serial output on each rising edge of TCK. Either Bypass or Boundary-Scan register selected by the current instruction retain their previous state. The instruction does not change while the TAP controller is in this state. When the TAP controller is in this state and a rising edge is applied to TCK, the TAP controller enters either the Exitl-IR state if TMS is held at 1 or remains in the Shift-IR state if TMS is held at 0.
Exitl-IR This is a temporary controller state. H TMS is held high, a rising edge applied to TCK while in this state causes the TAP controller to enter the Update-IR state, which terminates the scanning process. H TMS is held low and a rising edge is applied to TCK, the TAP controller enters the Pause-IR state. Either Bypass or Boundary-Scan register selected by the current instruction retain their previous state. The instruction does not change while the TAP controller is in this state and the instruction register retains its state.
Pause-IR This TAP controller state allows shifting of the instruction register to be halted temporarily. Either Bypass or Boundary-Scan register selected by the current instruction retain their previous state. The instruction does not change while the TAP controller is in this state and the instruction register retains its state. The TAP controller remains in this state while TMS is low. When TMS goes high and a rising edge is applied to TCK, the TAP controller moves on to the Exit2-IR state. Exit2-IR
185

This is a temporary controller state. If TMS is held high and a rising edge is applied to TCK while in this state, termination of the scanning process results, and the TAP controller enters the Update-IR controller state. If TMS is held low and a rising edge is applied to TCK, the TAP controller enters the Shift-IR state. Either Bypass or Boundary-Scan register selected by the current instruction retain their previous state. The instruction does not change while the TAP controller is in this state and the instruction register retains its state.
Update-IR The instruction shifted into the instruction register is latched onto the parallel output from the shift-register path on the falling edge of TCK in this controller state. Once the new instruction has been latched, is becomes the current instruction. Either Bypass or Boundary-Scan register selected by the current instruction retain their previous state. When the TAP controller is in this state and a rising edge is applied to TCK, the TAP controller enters the Select-DR-Scan state if TMS is held at 1 or the Run-Test/Idle state if 1MS is held at O.
The Pause-DR and Pause-IR controller states are included so that shifting of data through Bypass, Boundary-Scan or instruction register can be temporarily halted.
186

8.4.1.3 TAP Controller Operation
The operation of this TAP controller is as follows:
The TAP controller shall only change state in response to the following events: (i) A rising edge of TCK or (ii) Power-up.
The TAP controller generates signals to control the operation of Bypass, Boundary-Scan and instruction registers as defined in this standard (Figs 8.4-3 and 8.4-4).
The TOO output buffer and the circuitry that selects the register output fed to TOO are controlled as shown in Table 8.4-1.
Changes at TOO defined in Table 8.4-1 occur on the falling edge of TCK following entry into the state.

Table 8.4-1 Operation in Each Controller State

Controller State
----
Test-Logic-Reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-IR Shift-IR Exitl-IR Pause-IR Exit2-IR Update-IR Capture-DR Shift-DR Exitl-DR Pause-DR Exit2-DR Update-DR

Register Selected to Drive TOO
Undefined Undefined Undefined Undefined Undefined Instruction Undefined Undefined Undefined Undefined Undefined Test data Undefined Undefined Undefined Undefined

TDO Driver
Inactive Inactive Inactive Inactive Inactive Active Inactive Inactive Inactive Inactive Inactive Active Inactive Inactive Inactive Inactive

The assignment of controller states in the example implementation is given in Table 8.4.-2 (see the section 8.4.3) .

187

TCK TMSU

n n

~ Cl) Ill
rt

~
::s
I

(II
.C..l)..
C1>

(II 0
~ .C.1.>..
C1>

'O Ill i::

(II
.:.:.r.

Ill

1-11

:iii
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I

I t"'

~ Cl)

i::
~

Cl)

~ Cl)

Ill

Cl)

Ill

Controller state

'.0°...
r I
Ill

.r...t..

0 :iii

H ::ti

I H

e H

(II

I
(II
0

Cl) I::lsl I::lsl

:iii

.r...t..
e H
ti>

Cl)

TDI·-------------()()------------cx::x::x::>----------------------Data input to IRWf%f&.#.J.ifJiJ.$.i~%%@ IR shift-register ~~!f{tf#J.fl.Jf#J.ifti~· Parallel output of IR~B_Y_P_A__ss___________________________________________X~--~N~e~w....:I~n~s~t~r~u~c~t~i~o~n.;...._ _~

Register selectedMMi@@@M\WMfaMHl Instruction re ister '-....;;;;;.;.;;..;;;.;;.;;;;.;;.~;.;;.;;;.;._.;;;..;:;.&,;;;.;;.,~;.;;;..~~~~~~---'

TOO enable _I_n_a_c_t_i_·v__ e ___.X Act X Inactive

X Active X~_I_n_a_c_t_i_v_e_ _ _ _ _ _ _ _ __

T001------------()(}------------cx::::x:x:::>----------------------

l@l.l.i.t:i§~~fdM@WM = Don't care or undefined

TCK

TMS

::c:x:s:i
..I,,

Cll

Controller state

.r...t..

en n

.I.D...
gID

Ill
~ c::
11

:>'
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I

I ID

t1 I

:xi

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H
~

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0

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Cl 'O Q.

~ ::s

en
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Ill rt

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Cll

t1 :<!

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t1 :xi

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eIn
0

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>'I ID
Cll rt
I I:"' 0 IQ
"0I""
~
Cll
ID

C X J O T D I - - - - - - - - - - - - - - - - - - -

CXXX)

Parallel output of IR___In__s_t_r_u_c_t_i_o_n____________________________________________~XBYPASS
Data input to TDRM\liM#Mt@MlMMWNWMMfN·
TDR shift-register iNHM!:HW@!HfWH#.fi.@i@.@MMk
X Parallel output of TDR~O_l_d__d_a_t_a ___________________________________________ New data

TDO enable __In_a_c_t_i_v_e_____XActiveX Inactive

x Active x'"_I_n_a_c_t_i_v_e________

TDO--------------CXJ(J------------CXJC)(J------------------

:\\@M@W@@ii@iHi = Don't care or undefined

8.4.1.4 TAP Controller Initialization
The initialization for this TAP controller is as follows:
(a) The TAP controller is forced into the Test-Logic-Reset controller state at power-up by the power-on-reset circuitry built into the FDC.
(b) The TAP controller is not initialized by operation of any system input, such as a system reset.
(c) The TAP controller can synchronously enter into the Test-LogicReset controller state following five rising edges at TCI< (provided TMS is held high).

8.4.2 Instruction Register
As this register is described at the section 8.2, this register is specified by the following;
1) The Instruction shifted into the instruction register is latched such that changes in the effect of an instruction occur only in the Update-IR and the Test-Logic-Reset controller states
2) There is no inversion of data between the serial input and the serial output of the instruction register.
3) This register cell loads a fixed binary "01" pattern data, the 1 into the least significant bit location, in the Capture -IR controller state.
4) This register is set to a fixed binary "01" pattern data, the 1 into the least significant bit location, during the Test-Logic-Reset controller state.
5) When this register is read, the data from the ISB(Least Significant Bit) to the MSB(Most Significant Bit) are output to the TOO pin at each falling edge of the TCK pin.

This JTAG circuitry in this FDC can support the only following three
instructions by setting the specified data into this Instruction register:

-Bypass

- Sample/Preload

-Extest

Bits in the Instruction Register

02 Dl DO

Supported Instructions

0 0

EXTEST

0 1

Bypass (after the Reset condition)

0 10

SAMPLE/PRELOAD

1 1

CLAMP-IO

190

0 0

0 1

reserved (BYPASS) reserved (BYPASS) reserved (BYPASS) BYPASS

8.4.2.1 Bypass Instruction
This instruction, which is assigned the instruction data "11" or "01", is used to select the only Boundary Scan register for the serial access between the TDI and the TOO pins in the Shift-DR controller state.
When this instruction is selected, the operation of this JTAG circuitry does not effect on the operation of the FDC.
During the Test-Logic-Reset controller state, this Bypass instruction is selected.

8.4.2.2 Sample/Preload Instruction
This instruction, which is assigned the instruction data "10", is used to select the only Boundary Scan register and to have a snap-shot of the normal operation of the FDC to be taken and examined. The data to be had a snapshot can be latched into the Boundary Scan register.
When this instruction is selected, the JTAG circuitry can operate the following:
1) The operation of this JTAG circuitry does not give effects on the operation of the FDC or on the flow of signals between the FDC pins and the on-chip circuitry.
2) The states of all signals flowing through the FDC pins are loaded into the Boundary Scan register on the rising edge of the TCK pin in the Capture-DR controller state. In this case, the loaded data can not loaded to the input and output pins in the FDC. These only data can be shifted toward the TOO pin in the Shift-DR controller state.
3) Each output bit of the Boundary Scan register can update the data from the old data to the already held data on the falling edge of the TCK pin in the Update-DR controller state. But these data can not be shifted toward the TDO in the Shift-DR controller state.

8.4.2.3 Extest Instruction
This instruction, which is assigned the instruction data "00", also is used to select the only Boundary Scan register for the serial access between the TDI and the TOO pins in the Shift-DR controller state.

191

When this instruction is selected, the state of all signals driven from system outputpins is completely defined by the data shifted into the Boundary-Scan register and change only on the falling edge of TCK in the Update-DR controller state.
When this instruction is selected, the state of all signals received at system input pins is loaded into the Boundary-scan register on the rising edge of TCK in the Capture-DR controller state.
8.4.3 Boundary Scan register
The function of the assigned bits in this register are described in this section.
This register consists of the following four types of cells:

Cell Type I 0
oz
I/O

Table 8.4-2 Cells Types for Pins Functions
This cell type is for all input pins. This cell type is only for the output pins to be set to a logical high or low. This cell type is only for DMARQ and INT pins to be set to the logical high, low or the high impedance. This cell type is only for data bus pins.

The following pins do not have cell type: - Digital and Analog Voltage Supplies (VDD, GND, AVDD and AGND) - Cock Output Pin (XA2) - Analog Pins (I.PF!, LPF2, CGPl and CGP2)

Because it is meaningless for the voltage supplies to have Boundary Scan registers in order to be able to check these pins by checking whether a -instruction. can be operated or not.
On the other ~d, it also is meaningless for the Analog pins to have Boundary Scan registers in order not to be able to output logically.
The Boundary Scan register for the I typed and 0 typed cells is consisted of the circuitry at the shown in Fig. 8.4.3.1 and Fig 8.4.3.2.
The Boundary Scan register for the I typed cell is consisted of the circuitry at the shown in Fig. 8.4.3.2. As you know from this figure, the input pin is directly connected with the internal logic circuit in the FDC. Because there is some capabilities for the oscillator not to oscillate the self oscillation when the crystal resonator is connected with the XAl and XA2 pins if some gates are inserted between the pin and the internal logic circuitry in the FDC.

192

The Boundary Scan register for the OZ typed cells is consisted of the circuitry at the shown in Fig. 8.4.3.3. In this typed cell, the two registers are for the data to be output from the pins and the signal to enable the pins to be output. These OZ typed cells are adapted to the only DMARQ and INT pins.
The Boundary Scan register for the I/O typed cells is consisted of the circuitry at the shown in Fig. 8.4.3.4. In this typed cell, the three registers are for the data to be output from the pins to the internal circuitry in the FDC, the signal to enable the pins to be output and the data to be input from the pins to the internal circuitry in the FDC. These 1/0 cell types are adapted to the only from DBO to DB7 pins.

to the next cell

from the internal logic

from the previous cell
typed O cell for all output pins
Fig 8.4.3.1 the 0 typed cells
pin
0 1 - -......-----------1~ to the internal logic
to the next cell

from the previous cell
Fig 8.4.3.2 the I typed cell

193

VDD
pin QJ<---9

to the next cell

1-----------IPO

Enable signal

s r

from the Internal logic

.,___ _ _ _ _ ___.Po

so
PI

Data signal

s I

from the internal logic

from the previous cell
Fig 8.4.3.3 the three states typed cell

VDD pin
a

to the next cell

Input data signal

to the Internal logic

PI Enable signal

from the Internal logic

OUtput data signal

from the Internal logic

from the previous cell
Fig 8.4.3.4 the 110 typed cell

194

Bit# DO Dl D2 D3 D4 DS D6 D7
DB D9 DlO D11 D12 D13 D14 D15
D16 D17 D18 D19 D20 D21 D22 D23
024 D25 D26 D27 D28 D29

Function Data to be output from the DENl_B Data to be output from the DENO_B Data to be output from the SEL (HDLD_B} Data to be output from the D5.3_B Data to be output from the INDEX_B Data to be output from the DSO_B Data to be output from the DSl_B Data to be output from the DS2_B
Data to be output from the MEO_B Data to be output from the MEl_B Data to be output from the CAO (DIR_B} Data to be output from the CAl (STEP_B) Data to be output from the CA2 (SIDE_B) Data to be output from the ISTR&(NC) Data to be output from the ENBLO_B CME2_B} Data to be output from the ENBLl_B (:ME3_B}
Data to be output from the WDATA_B Data to be output from the WGATE_B Data to be output from the (TRKO_B} Data to be output from the (WPRT_B) Data to be output from the RDATA_B)
Data to be output from the (DKCG_B I READY_B}
Data to be output from the PCTYP1 Data to be output from the PCTYPO
Data to be output from the DRV2 Data to be output from the XB Data to be output from the XAl Data to be output from the ENDKCG_B Data to be output from the TC Data to be output from the DMARQ
195

Bit# D30 D31

Function Signal to enable the DMARQ active Data to be output from the INT

D32

Signal to enable the INT active

D33

Data to be input from the DB7

D34

Signal to enable the DB7 active

D35

Data to be output from the DB7

D36

Data to be input from the DB6

D37

Signal to enable the DB6 active

D38

Data to be output from the DB6

D39

Data to be input from the DBS

040

Signal to enable the DBS active

041

Data to be output from the DBS

042

Data to be input from the DB4

D43

Signal to enable the DB4 active

D44

Data to be output from the DB4

04S

Data to be input from the DB3

046

Signal to enable the DB3 active

047

Data to be output from the DB3

D48

Data to be input from the DB2

049

Signal to enable the DB2 active

DSO

Data to be output from the DB2

DSl

Data to be input from the DBl

D52

Signal to enable the DBl active

D53

Data to be output from the DBl

D54

Data to be input from the DBO

DSS

Signal to enable the DBO active

D56

Data to be output from the DBO

D57

Data to be input from the A2

DSB

Data to be input from the Al

D59

Data to be input from the AO

196

Bit# 060 061 062 D63
064

Function Data to be input from the CS_B Data to be input from the WR_B Data to be input from the RD_B Data to be input from the DMAAK_B
Data to be input from the RESET

197

NEC CONFIDENTIAL
Appendix uPD72070 Package Specifications

tu-Pin Plastic QFP (2.7 mm thit:k}

ll1m Mllllm111rs

Z!.6 :1:0.4

20.0 :l:o.2

14.0 :1:0.2

17.11 ::!:0.4

1.0

0.40 :1:0.10

0.20

t.o (l'P)

1.8 :1:0.2

L o.a :1:0.2

M 0.15 -+o0..o1s0

0.tS

2.7

0.1 :1:0.t

0.1 :1:0.1

3.0 max

Inc: hes .929 :t.018
009
·795 -·.·ooa
.551 · ,009 -.008
.693 ::.016 .039 .039
004 ·018 -·.·005 .008 .039 (11')
.o7t · .DOii
-.009
.oa1 -+.o.0o0a9
.0011 +.004 -.003
.0011 .1011 .004 ::.004 .004 ::!:.004 .119 max

B
g ggggggg
SI
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Enlugld detail of Ind ltld

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Preliminary Floppy Disk Controller Specification Version 2.0

CC:l C:onvri2ht of NEC Corporation, October 1991

198

3) DUMP AFTER DATA ADDRESS MARK When the ROM bits are set to "10", this mode can be entered under the only Apple mode. This dumps the requested number of bytes from the specified track. Especially under the MFM format, after the FDC finds out the specified ID address mark, the Data Address mark of this specified ID field and then the nearest SYNC bytes, the FDC checks whether the next data after these SYNC bytes is equal to the Mark byte, which is expected as the $Al for Data byte and the $0A for Clock byte. H this mark is hit, the FDC should start to dump data from and including this Mark byte. But if the Mark byte can not be hit, the FDC changes the expected Data for the Mark byte from the above data to the $C2 for Data byte and the $14 for Clock byte and then the FDC resumes to search the same specified ID field. After the FDC finds out the specified ID address mark and then the nearest SYNC bytes, the FDC checks whether the data after these SYNC bytes is equal to the Mark byte, which is expected as the $C2 for Data byte and the $14 for Clock byte. H this mark is hit, the FDC should start to dump data from and including this Mark byte. But if the mark byte can not be hit, the FDC abnormally terminates the command and interrupts to inform to the host this abnormal termination. For GCR format, after the FDC finds out the specified ID address mark and then the Data header of this specified ID field, the FDC is waiting to received the Mark byte with the $D5 for Data byte. H this mark is hit, the FDC should immediately start to dump data from and including this Mark byte. But if the mark byte can not be hit, the FDC abnormally terminates the command and interrupts to inform to the host this abnormal termination. In addition, the FDC dumps the data without denibblizing the read-data from the FDD. The Fig. 4. 18. 3 is shown as a example of this mode. In this example, the ID Address mark is located after the specified ID field, the Data Address mark and the SYNC bytes. In this dumped mode, the FDC ignores the following errors after the first Address mark in the data field is found out. - Read error for CRC for the MFM format or Checksum for the GCR format - Read error for Bit slip byte for the GCR format · Read error for Address mark in the Data field
63

Sync byte

ID field - - - - - ·...-...

Address mark

address header

---·lllllP'- .~ .. ------Data field

GAP2

Sync data address

byte

mark

data

00..·0 A1 A1 A1 FE C H S N CRC 4E · · 4E 00.··0 A1 A1 A1 B XXX·.·X CRC

GAP3

transfered data from this point from

self Sync byte

ID field - - - - - - - - - - · - - - - - - D a t a field ------·~

Address mark

address header

self Sync byte

data mark

Tag

Bit slip

data

byte

96trsstrf

AD s XX. ·. X DE

transfered data from this point from
Fig. 4.18.3 Transferred Data for Dump After Data Address Mark

Transferred Data

FOR MFM FORMAT
The FDC starts to dump data to the host according to the following transfer rule shown in the Fig. 4.18.4 after the mark byte is detected. This transfer is called the 8 x 8 data transfer format and the FDC should transfer the Data byte and the Oock byte, repeatedly.

Data from the FOO
Transferred bytes Data bytes

Clock bytes

#1(Data) - A 1 -

#2(Data) #3(Data)

-A1-A1-

llllbAR~d
1BbAi11!ll

included Missing clock bits

#4(Data) -FE-

-oo-

#S(Data) - 0 3 -

-FC-

#6(Data) - A 1 -

-OE-

#7(Data) - 0 5 -

-F8-

#S(Data) - A 1 -

included Missing clock bits

Data from the FDC to the host
#1 (Data) #2(Data) #3(Data) #4(Data) #5(Data) #6(Data) #7(Data) #8(Data)
I A~ li.QA. A1 l~·QA.lf A11[9.A.il A1 OA 03 FC A1 OE A1 FB A1 fil!li/q

Fig. 4.18.4 The 8 X 8 Data Transfer Format for MFM

The following charts illustrate the MFM clock byte for the dumped data pattern. The chart shows two clock bytes for each data pattern. The clockO column illustrates the clock byte if the previous data bit was a "O". The clock.I column illustrates the clock byte if the previous data bit was a "l".

data clockO clockl data c!ockO clpck 1 data clpckO clpckl data c!pckO c!pckl

00 ff fe 01 7f 7e
02 3f 3e
03 3f 3e 04 9f 9e 05 1f le
06 1f le 07 1f le
08 cf ce 09 4f 4e
Oa Of Oe Ob Of Oe Oc Sf Se Od Of Oe
Oe Of Oe Of Of Oe 10 e7 e6 11 67 66 12 27 26 13 27 26 14 87 86 lS 07 06 16 07 06 17 07 06 18 c7 c6 19 47 46 la 07 06 lb 07 06 le 87 86 ld 07 06 le 07 06
1f 07 06

20 f3 f2 21 73 72 22 33 32
23 33 32 24 93 92 25 13 12 26 13 12 27 13 12 28 c3 c2 29 43 42
2a 03 02 2b 03 02 2c 83 82 2d 03 02 2e 03 02 2f 03 02 30 e3 e2 31 63 62 32 23 22 33 23 22 34 83 82 3S 03 02 36 03 02 37 03 02 3S c3 c2 39 43 42 3a 03 02 3b 03 02 3c 83 82 3d 03 02 3e 03 02 3f 03 02

40 f9 f8 41 79 78 42 39 38 43 39 38 44 99 98 45 19 18 46 19 18
47 19 18 48 c9 cs
49 49 48 4a 09 08 4b 09 08 4c 89 88 4d 09 08 4e 09 08 4f 09 08 50 el eO
51 61 60
52 21 20 S3 21 20 S4 81 80 SS 01 00 56 01 00 S7 01 00 58 cl co 59 41 40 Sa 01 00
Sb 01 00 Sc 81 80 Sd 01 00 Se 01 00 Sf 01 00

60 f1 fO 61 71 70 62 31 30
63 31 30 64 91 90 65 11 10 66 11 10 67 11 10 68 cl co 69 41 40
Ga 01 00 6b 01 00 6c 81 80 6d 01 00
6e 01 00 Gf 01 00 70 el eO 71 61 60 72 21 20 73 21 20 74 81 80 7S 01 00 76 01 00 77 01 00 78 cl co 79 41 40 7a 01 00 7b 01 00 7c 81 80 7d 01 00 7e 01 00 7f 01 00

data c!ockO clock 1 data c!gckO c!gckl

80 f c fc 81 7c 7c 82 3c 3c 83 3c 3c S4 9c 9c 8S le le S6 le le 87 le le SS cc cc 89 4c 4c Sa Oc Oc Sb Oc Oc 8c Sc Sc 8d Oc Oc Se Oc Oc Sf Oc Oc 90 e4 e4 91 64 64 92 24 24 93 24 24 94 84 84 95 04 04 96 04 04 97 04 04 98 c4 c4 99 44 44 9a 04 04 9b 04 04 9c S4 84 9d 04 04 9e 04 04 9f 04 04

aO fO fO al 70 70 a2 30 30 a3 30 30 a4 90 90 as 10 10 a6 10 10 a7 10 10 as co co a9 40 40 aa 00 00 ab 00 00 ac so 80 ad 00 00 ae 00 00 af 00 00 bO eO eO bl 60 60 b2 20 20 b3 20 20 b4 80 80 bS 00 00 b6 00 00 b7 00 00 b8 co co b9 40 40 ba 00 00 bb 00 00 be 80 so bd 00 00 be 00 00 bf 00 00

data c!gckO c!gckl data c!pckO c!pckl

co fS f8 cl 7S 78 c2 38 3S c3 38 3S c4 9S 98 cs lS 18 c6 18 lS c7 18 18 c8 c8 c8 c9 4S 48 ca OS 08 cb 08 08 cc SS S8 cd 08 08 ce 08 08 cf OS 08 dO eO eO dl 60 60 d2 20 20 d3 20 20 d4 80 80 dS 00 00 d6 00 00 d7 00 00 d8 cO co d9 40 40 da 00 00 db 00 00 de 80 80 dd 00 00 de 00 00 df 00 00

eO fO fO el 70 70 e2 30 30 e3 30 30 e4 90 90 es 10 10 e6 10 10 e7 10 10 e8 co co e9 40 40 ea 00 00 eb 00 00 ec so so ed 00 00 ee 00 00 ef 00 00 fO eO eO f1 60 60 f2 20 20 f3 20 20 f4 80 80 fS 00 00 f6 00 00 f7 00 00 f8 co co f9 40 40 fa 00 00
fb 00 00 fc 80 80 fd 00 00 fe 00 00 ff 00 00

FOR GCR FORMAT
The FDC starts to dump the raw data from FDD to the host without denibblizing, this disables the 3 - 4 conversion process. In addition, the data that is transferred from the FDC to the host is in the 8x8 format. The difference is that the clock byte that is transferred is a duplicate of the data byte. This additional Dummy Clock byte is meaningless. Please refer to the following diagram.

Data from the FOO
Transferred bytes Data bytes
#1(Data) -FA#2(Data) - 9 0 #3(Data) -A7#4(Data) -FE#5(Data) -FB#6(Data) -AB#7(Data) -BA#8(Data) -DD-

Dummy Clock bytes
I-FA-90-A7-FE-FB-
-AB-
-BA-DD-

Data from the FDC to the host
#1 (Data) #2(Data) #3(Data) #4(Data) #5(Data) #6(Data) #7(Data) #8(Data)
I FAI FAI 9DI 9DI A71 A7 FEI FEI FBI FBI ABI Asl BAI BAI ool ool

Fig. 4.18.5 The 8 X 8 Data Transfer Format for GCR

ERROR CONDmONS 1) DUMP AFTER THE ID ADDRESS MARK:
68

If the recording format is GCR and the FDC can not find the ID Address Mark within the 400msec. If the recording format is MFM and the FDC can not find the ID Address Mark within two Index pulses. 2) DUMP AFI'ER THE DATA ADDRESS MARK:
If the recording format is GCR and the FDC can not find a Data Address Mark within the 400msec. If the recording format is MFM and the FDC can not find the Data Address Mark within two Index pulses. 3) WHEN THE FOLLOWING CONDmONS OCCUR: - The overrun or underrun occur during the data transfer. - The TC does not be input for the allowable period. - Under Standard modes, the READY_B pin in the drive interface is inactive before this is operated under Standard modes.
69

Under Standard modes: This command is similar to the above function under the Apple mode, except that this is a continuous read operation from the data field of the sectors immediately after the Index pulse.
PARAMETERS IN THE RESULTANT PHASE
·1) # OF SECTOR TO BE READ For Apple mode, this byte indicates the number of remaining sectors to be read when this command has failed by some error.
#of Sector to be Read" (Resultant Phase)=# of Sectors to be Read - #of Sector Read"
For example, the host has set 5 to the byte "# of Sectors to be Read" in the Command Phase. When the FDC detects some error while it is reading the third sector to be read (after the first and second sectors were successfully read), the FDC reports in the resultant phase that this"# of Sector to be read" byte is set "3" ( 5-2).
The parameters in this command are same functions as the Read Data Commands except the parameters specified above.
ERROR CONDmONS
1) When the FDC can not find the following within 400msec for the GCR format, or when the FDC can not find the following before two Index pulses are detected for MFM and FM format:
- Address mark in the Address header ( ID field) - Desired Address header ( Data in the ID field )
2) When the FDC detects a Read Error in the following: - CRC bytes or the Checksum bytes - Address Mark in the Data field - Bits slip bytes (Under GCR format only)
3) When the following conditions occur: - Overrun or Underrun occur during Data transfer. - When utilizing the TC input, it does not meet the correct
71

timing period. - Under Standard/Apple mode, when the status of the FDD indicates a NOT READY condition prior to command execution. - Under Standard modes, when the ODAM (Deleted Data Address Mark) is detected, the CM bit of the Status Register 2 (ST2) is set. and one of the following two conditions occur according to the contents of the TB bit in the command phase.
(1) When TB=O: command execution terminates normally after data transfer of that sector. The ID bytes of the sector in which ODAM is detected will be the value· in the result phase. (2) When TB=l: the sector is skipped and the next sector is read. 4) When the FDC continues to read even if the following errors occur: - The CRC bytes or the Checksum bytes - The Bits slip bytes (only under GCR format) but the FDC will mark the error in the Status register 0-2 at the result phase.
72

Read Data

Phase command
Execution

RN/ 07 06 05 04 03 02 01 DO

Remarks

W MT FM TB O O 1 1 O command code

w X X X X X HD DR1 DAO

Cylinder

Head

Sector

w (Bytes/Sector) I Format Byte

w Last Sector in Muliti Sector Read

w GSL(MFM) I don't care (GCR)

Data Length in Bytes

data transfer between
Host and FOO

Status Regisiter O

status information

Status Regisiter 1

after this command

Status Regisiter 2

Cylinder

Head

Sector

R _1B_rtes/Sectotl_ I Format B_rte

FUNCTION
GENERAL: The host can use this command to read the data in the Data field from the specified sector. After this command has been issued, the FDC begins reading ID address header (or data in the ID field).
When the specified sector number equals the sector number read off the disk, the FDC transfers the data from the Data field byte by byte via the data bus.
After completion of this operation from the current sector, the internal sector number is incremental by one, and the data from the next sector is read and output on the data bus.

MULTI-TRACK READ: If the MT (Multi-track) bit is set, the read will continue with data on the other side of the disk, for the specified cylinder only.

TAG BYfE FOR THE ONLY GCR FORMAT: While in the GCR format, the FDC will ignore the Tag bytes at the

beginning of the sector, unless the TB bit is set to high(l). When the TB bit is set to high(l), the FDC will transfer 524 bytes to the host. If the TB bit is not set, the FDC will transfer only the 512 data bytes of the sector.

PARAMETERS a.) GCR format
The values for the EOT (Last Sector in the Multi-sector Read) and N (bytes/sector) should be set as:
N should be set as 02H, 22H, or 24H EOT should be set from SH to CH b.) MFM or FM format: The reference value for the EOT, N, and GSL are shown in Table 4.8.1

Format Bytes/sector N(16)

25"""6"

512

MFM

512

1024

2048

4096

8192

EOT(16)
1A 09 OF 12 24 08
04
oz
01

GSL(16)

Notes

l8M-CiiSJ<ette £ 0

720K8

1.2MB

1.44MB

2.88M8

IBM diskette 20

Undetennined

Undetermined

128

256

512

1024

2048

4096

IBM diskette 1

IBM dskette Z

Undetermined

Table4.8.1 Reference Values forN and EOT

DATA LENGnl IN A SECTOR:
For Standard modes, only when the "Number of data bytes in the Sector" byte ( N ) is Zero for the FM format, this data length in the sector is determined by the "Data length in bytes" byte (DTL). This "DTL" should be set the less than SOH and 128bytes/sector is specified when this "DTL" is set the bigger than 80H.
When the "Number of data bytes in the Sector" byte ( N ) is not zero, this data length is determined by the only "Number of data bytes in the Sector" byte ( N) (see the above table 4.8.1).

NORMAL TERMINATION
When this command normally terminates, the values in Table 4.8.1 are set at the resultant phase:

MT Head

0 0

0 1

last sector
<EOT =EOT <EOT =EOT <EOT ·EOT <EOT ·EOT

ID infonnation at the result phase

C_ylinder Head Sector

S+1

C+1

S+1

C+1

S+1

C+1

Table 4.8.1 Normally Terminated Values for Read Data Command

No Change

BOT

Maximum number of sectors to be written on the disk

LAST SECTOR Number of the "last sector in the Multi sector read" byte at the command phase

Number of the "Cylinder" bytes at the command phase

Number of the "Sector" bytes at the command phase

"Number of data bytes written" at the command phase

PARAMETERS

Under Apple mode, this bit indicates the following

format mode:

MFM format mode, when this bit is set.

GCR format mode, when this bit is reset.

Under Standard modes, this bit indicates the following

format mode:

MFM format mode (when this bit is set).

FM format mode

(when this bit is reset).

Under Apple mode, this bit determines whether the data

in Tag bytes should be transferred or not.

Transfers the data

(when this bit is set).

Don't transfer the data (when this bit is reset.

Under Standard modes, this bit determines whether the data in the Data field are skipped or not.

Skips the data

(when this bit is set).

Transfers the data

(when this bit is reset).

Under Standard modes, the issued command requests the

FDC to perform the Seek command without specially

issuing the Seek command and then to perform this Read

Data command, when this bit is set.

ERROR CONDmONS 1) When the FDC can not find the following within the 400msec. in Apple
mode or when the FDC can not find the following before two Index pulses
are input for MFM and FM format in standard mode:
- Address mark in the Address header ( ID field)
- Desired Address header ( data in the ID field )
2) When the FDC detects a read error in the following:
- the CRC bytes or the Checksum bytes
- the address mark in the Data field
- the Bits slip bytes under only GCR format
3) When the following conditions occur:
- The overrun or underrun occur during the data transfer.
- When utilizing the TC input, it does not meet the correct timing period.
- Under Standard modes, the READY_B pin in the drive interface is inactive before this is operated under Standard modes.
- Under Standard modes, when the DDAM (Deleted Data Address Mark) is detected, the CM bit of the Status Register 2 (ST2) is set and one of the following two conditions occur according to the contents of the TB bit in the command phase.
(1) When TB=O: Command execution terminates normally after data transfer of that sector. The ID bytes of the sector in which ODAM is detected will be the value in the result phase.
(2) When TB=l: The sector is skipped and the next sector is read.

Read Deleted Data

Phase command
Execution Result

R/N 07 06 05 04 03 02 01 DO

Remarks

W MT FM SK O 1 1 0 0 command code

W X X X X X HD DR1 ORO

Cylinder

Head

Sector

W Number of data bytes in the Sector

W Last Sector in Muliti Sector Read

GSL

Data Length in B_ytes

data transfer between

Host and FOO

o Status Regisiter

status information

Status Regisiter 1

after this command

Status Regisiter 2

Cylinder

Head

Sector

Number of data b_yt~es read

FUNCTION
This command can be used only under Standard modes and can not be supported under Apple mode.
DAM and ODAM explained in the Read Data functions under standard modes are replaced with ODAM and DAM, respectively.

Read ID

Phase command
Execution

BM 07 06 05 04 03 02 01 DO

R..am...arks

w 0 FM 0 0 1 0 1 0 command code

w x x x x x HD DR1 ORO

The first correct ID information found on the track is returned

Status Regisiter O

status information

Status Regisiter 1

after this command

Status Regisiter 2

Cylinder

Head

Sector

R _(B_.rtes/Sectotl. I Format B_yt_e

FUNCTION
The host uses this command to read the present position of the Read/Write head of the FDD. The FDC returns the first available address header (or data in the ID field), after a sync byte field, during the result phase.

ERROR CONDmONS
FOR MFM FORMAT:
If the FDC can not find the requested data in the ID field before two Index pulses have passed, the FDC will terminate this command and inform the host via the status passed in the result phase.
FOR GCR FORMAT:
If the FDC can not find the requested address header before two revolutions have occurred within 400msec, the FDC will terminate this command and inform the host via the status passed in the result phase.

Recalibrate

Command Execution

07 06 05 04 03 02 01 DO
W o O O O O 1 1 1 command code
W X X X X X X DR1 ORO
Head is recalibrated cylinder 0.

FUNCTION
This command causes the FDD to retract the Read/Write head to Cylinder 0.
Under Apple mode: After the FDC receives this command and resets the internal parameter of PCN byte:
(1) The FDC first issues the /Step command toward the outside to the FDD for 80 steps and then checks the status of /TrackO from the FDD.
(2) After the status of /TrackO becomes active, the FDC issues the /Step command toward the inside to the FDD until the status of /TrackO becomes inactive.
(3) After the status of /TrackO becomes inactive and then the FDC issues a /Step command toward the outside to the FDD, the FDC confirms the active status of /TrackO.
(4) The interrupt (INT) is asserted to inform of the host about the termination of this command.
(5) Finally, the result for this command is reflected in the Status Register 0 (STO) and this STO should be read by issuing the Sense Interrupt Status command.

Under Standard modes: After the FDC resets the internal parameter of PCN byte, a Seek Operation is performed toward the outside until TRKO_B signal in the drive interface becomes active.
When the TRKO_B signal becomes active, the SE bit in the Status Register 0 is set and the command execution is normally terminated. However, this Status Register 0 should need to be read by issued the Sense Interrupt Status command.

ERROR CONDmONS UNDER APPLE MODE: The FDC informs the host of a abnormal terminations by setting the INT pin active after the EC bit in the Status register 0 in the result phase is set. (1) The FDC first issues the /Step command toward the outside to the FDD

for a maximum of 80 steps, the FDC can not check the active status of /Ready in the drive interface within 800msec after the last /STEP command is issued. (2) After the FDC checks the active status of /Ready in the drive interface within 800msec after the last /STEP, the FDC can not check the active status of /TrackO in the drive interface. (3) After the status of /TrackO becomes active and the FDC issues the /Step command toward the inside to the FDD for a maximum of 80 steps, the FDC can not check the inactive status of /TrackO. (4) After the FDC issues a /Step command to the FDD in the above sequence, the FDC can not check the active status of /Ready in the drive interface within 18msec. (5) After the status of /TrackO becomes inactive and then the FDC issues a /Step command toward the outside to the FDD, the FDC can not confirms the active status of /TrackO. (6) After the FDC issues a /Step command to the FDD in the above sequence, the FDC can not check the active status of /Ready in the drive interface within 18msec..
UNDER STANDARD MODE: (1) When the TRKO_B signal does not become active after issuing the
maximum of 80 steps to FDD, the FDC sets the SE ·and EC bits in the Status register 0. (2) When the READY_B signal becomes inactive during the execution phase, the FDC sets the SE and NR bits in the Status register 0.
80

Relative Seek

Phase command
Execution

RN/ D7 D6 D5 D4 03 D2 D1 DO

Remarks

w 1 DIR 0 0 1 1 1 1 command code w x x x x x HO DR1 ORO

Relative cylinderNumber

Head is positioned over relative cylinder.

FUNCTION
This command is used under Standard modes. The FDC relatively seeks the Read/Write head to the destination cylinder according to the number of the "Relative cylinder Number" byte. The direction is defined by the DIR bit.

Revision

Phase command
Result
Result

RN/ D7 06 D5 04 03 D2 01 DO

Remarks

w 0 0 1 0 0 0 0 0 command code

D7 D6 D5 04 D3 D2 D1 DO Echo back the revision of installed Firmware.

D7 D6 D5 D4 D3 D2 D1 DO

Echo back the revision of installed Hardware.

FUNCTION Under all modes, the result of this command indicates the revision number of both the firmware and hardware installed into this FDC. The number starts from the zero to "FF'. The Operating System can easily know what number the installed firmware is running in the FDC.
ERROR CONDmONS There are no error conditions for this command.

Scan Equal

Phase command
Execution Result

Rm 07 06 05 04 03 02 01 DO

Remarks

W MT FM SK 1 O O O 1 command code W X X X X X HD DR1 ORO

Cylinder

Head

Sector

w Number of data bytes in the Secto~

W Last Sector in Muliti Sector Read

GSL

STP

data transfer between
Host and FOO

Status Regisiter O

status information

Status Regisiter 1

after this command

Status Regisiter 2

Cylinder

Head

Sector

Number of data b_yj_es read

FUNCTION
This command is used under Standard modes. This has the same function as the Read Data command.
Data Comparison
When a data byte transferred from the host is set to FFH, the FDC does not compare with a data from the FDD. Ot is assumed to be equal.)
Comparison Method
A check is made to see if the data byte string on the sector to be compared is equal to the system data string. If equal, command execution terminates normally.

DISK HOST

Data Address Mark

MSB 01 02 03 FF 05 06 - - - - - - - - FE 01 02 03 FF 05 06 --------FE
1-> Disk=host (not compared) Fig. 4.22.1

SECTOR UPDATE When a data string on one sector is compared with the host data string and the comparison condition is not satisfied, the internal sector number (S) to be found out is updated ( S <- S + STP, where STP should be 1 or 2), and the data string on the sector specified in the sector number is compared with the host data string. Therefore, the host should send the same data string repeatedly for each sector.
STP The STP parameter should be set to OlH or 02H. When it is set to 02H, the sector number (S) and the Last Sector in Multi Sector Read (EOT) must be set so as to satisfy the following expression: S + 2(n-l)=EOT Where n is the number of sectors to be read.
EXECUTION TERMINATION When a comparison is made on a sector and if the sector satisfies the comparison co:ndition, then command execution terminates normally.
H the equal condition is satisfied, SH bit in the Status register 2 (ST2) is set. When there are no sectors satisfying the comparison condition although a comparison is made from the first to last sector, the SN bit in the Status register is set and command execution terminates normally.
83

Scan High or Equal

Phase command
Execution Result

RNJ 07 06 05 04 03 02 01 DO

Remarks

W MT FM SK 1 1 1 O 1 command code W X X X X X HD DR1 ORO

Cylinder

Head

Sector

W Number of data bytes in the Sector

W Last Sector in Muliti Sector Read

GSL

STP

data transfer between
Host and FOO

Status Regisiter O

status information

Status Regisiter 1

after this command

Status Regisiter 2

Cylinder

Head

Sector

Number of data b_rtes read

FUNCTION
This command is used under Standard modes. This command has the same function as the Read Data command.
Data comparison
When a data byte transferred from the host is set to FFH, the FDC does not compare with a data from the FDD. Ot is assumed to be equal.)
Comparison method
When the data byte string on the sector to be compared is greater than or equal to the host data string, command execution terminates normally.

DISK HOST

MSB Data Address Mark 01 02 03 44 05 06 - - - - - - - - FE
01 02 03 40 05 06 - - - - - - - - FE 1-> Disk>host (compared)
Fig. 4.24.1

SECTOR UPDATE When a data string on one sector is compared with the host data string and the comparison condition is not satisfied, the internal sector number (S) to be found out is updated ( S <- S + STP, where STP should be 1or2), and the data string on the sector specified in the sector number is compared with the host data string. Therefore, the host should send the same data string repeatedly for each sector.
STP The STP parameter should be set to OlH or 02H. When it is set to 02H, the sector number (S) and the Last Sector in Multi Sector Read (EOT) must be set so as to satisfy the following expression: S + 2(n-l)=EOT Where n is the number of sectors to be read.
EXECUTION TERMINATION When a comparison is made on a sector and if the sector satisfies the comparison condition, then command execution terminates normally. If the equal condition is satisfied, SH bit in the Status register 2 (ST2) is set. When there are no sectors satisfying the comparison condition although a comparison is made from the first to last sector, the SN bit in the Status register is set and command execution terminates normally.
85

Scan Low or Equal

Phase command
Execution Result

FWI 07 06 05 04 03 02 D1 DO

Remarks

W MT FM SK 1 1 O O 1 command code W X X X X X HD DR1 ORO

Cylinder

Head

Sector

W Number of data bytes in the Sector
w Last Sector in Muliti Sector Read

GSL

STP

data transfer between

Host and FOO

o Status Regisiter

status information

Status Regisiter 1

after this command

Status Regisiter 2

Cylinder

Head

Sector

Number of data bytes read

FUNCTION
This command is used under Standard modes. This command has the same function as the Read Data command.
Data Comparison When a data byte transferred from the host is set to FFH, the FDC does not compare with a data from the FDD. Ot is assumed to be equal.)
Comparison Method When the data byte string on the sector to be compared is less than or equal to the host data string, command execution terminates normally.

DISK Data Address Mark HOST

MSB 01 02 03 04 05 06 - - - - - - - - FE 01 02 03 40 05 06 --------FE
1-> Disk<host (compared) Fig. 4.23.1

SECTOR UPDATE When a data string on one sector is compared with the host data string and the comparison condition is not satisfied, the internal sector number (S) to be found out is updated ( S <- S + STP, where STP should be 1or2), and the data string on the sector specified in the sector number is compared with the host data string. Therefore, the host should send the same data string repeatedly for each sector.
STP The S'I'P parameter should be set to OlH or 02H. When it is set to 02H, the sector number (S) and the Last Sector in Multi Sector Read (EOT) must be set so as to satisfy the following expression:
S + 2(n -1) =EOT
Where n is the number of sectors to be read. EXECUTION TERMINATION
When a comparison is made on a sector and if the sector satisfies the comparison condition, then command execution terminates normally. H the equal condition is satisfied, SH bit in the Status register 2 (ST2) is set. When there are no sectors satisfying the comparison condition although a comparison is made from the first to last sector, the SN bit in the Status register is set and command execution terminates normally.
87

inform this termination of the host. This status register 0 should be read by issued the Sense Interrupt Status command.
Since the FDC is not busy in the Execution phase, seek or recalibrate commands given to other FDDs are accepted and seek operation can be performed on up to four FOO at the same time. But Read/Write groups commands must not be issued during the seek operation.

ERROR CONDmONS
UNDER APPLE MODE
H the /Ready line does not become active following a /Step command,
within the allowable time specified in following table 4.4.1, the FDC will terminate this command. Upon termination, the FDC will assert an interrupt, set the EC bit in the status register 0 and indicate an abnormal termination. The maximum timeout for all possible condition is 800msec.

Max Waiting Time

Conditions

18msec

When the Seek operation to move one track without speed block change under GCR and MFM

250msec

When the Seek operation to move one track with speed block change (only GCR mode)

800msec

When the Seek operation to move tracks with more than two speed block changes under both GCRandMFM

Table 4.4.1 Allowable Waiting Time for /Ready Status after /Step Command is Issued

UNDER STANDARD MODES:
When the READY_B signal becomes inactive during the execution phase, the FDC sets the SE and NR bits in the Status register 0.

Sense Drive Status

Phase command
Result

RMI 07 06 05 04 03 02 01 DO

Remarks

w 0 0 0 0 0 1 0 0 command code

w x x x x x HD DR1 ORO

Status Register 3

Status information

for FOO

FUNCTION
This command reports the status of the FDD by reading the Status Register 3 (ST3} from the Data register.

PARAMETERS IN THE RESULTANT PHASE Under Apple mode:
The Status Register 3 (ST3} is shown in the following diagram:

07 Media

D6 DS D4 03

WP RY TO DRIVE MODE SEL MEDIA

Status Register 3 (ST3} under Apple Mode

DO
MFM

MEDIA WP RY
TO
DRIVE MODE SEL MEDIA MFMM

Reflects the /2MB or I 4MB media status from FOO
Reflects the /WRTPRT status from FDD Reflects the /READY status from FOO Reflects the /TKO status from FOO Reflects the 2MB-4MB Drive status from FOD Reflects the /Mode ID status from FDD Reflects the /Select Media status from FOD Reflects the /MFM mode status from FOO

Under Standard Modes: The Status Register 3 (ST3} is shown in the following diagram:

07 06 05 D4 03 02

0 WP RY TO

1 HD

DRl

ORO

Status Register 3 (ST3} under Standard Modes

WP
RY
TO
HD
DRl, ORO

Reflects the state of the WPRT_B pin in the drive interface
Reflects the state of the READY_B pin in the drive interface
Reflects the state of the TRKO_B pin in the drive interface
Reflects the
Reflects the

ERROR CONDmONS There are no error conditions for this command under both Apple and Standard modes.
Note: Under Apple mode only, this command should be issued to get the correct status from the FDD only after the H Set Enable Control" command is issued. In the other word, if this command is issued to the FDC more than one time after the "Set Enable Control" command is issued, the FDC can not correctly inform to the host the content of the Status register 3 (ST3) at the result phase. Because the specific FDD of Apple has the same codes between the Motor off and the Select Media command to the FDD.

Sense Interrupt Status

Phase command
Result

FWI 07 06 05 04 03 02 01 DO

Remarks

w 0 0 0 0 1 0 0 0 command code

Status Register O

Status for Interrupt

Present C_ylinderNumber

FUNCTION
By using this command, the host can check why the FDC has interrupted the host. The interrupts between Apple and Standard operation modes occur for different reasons.

Under Apple mode: (1) Upon entering the result phase of any commands that passes back some
status information. (2) End of Seek and Recalibrate commands. (3) End of the following commands:

- Disable/Enable DPLL - Set Motor Control

- Set Drive Mode - EJECT Command

The host should issue this command to the FDC within lOOms after the above interrupt occurs. Unless this command can not be issued within this lOOms, these maybe be some capability to miss the already occurred interrupt.
(4) During the execution phase in the non-DMA transfer mode to request more data
(5) /CSTIN status bit from the FDD changes status.
(6) The FDC interrupts when the FDC detects the issued command was invalid. In this c~, the host should read the only Status register 0 from the FDC because the FDC can not set the "Present Cylinder Number" (PCN)byte.

Under standard modes:

(1) Upon entering the result phase of any comm.ands that passes back some

status information.

(2) The status of READY_B signal in the drive interface is changed for the

target of the standard FDDs.

(3) End of Seek and Recalibrate commands

(4) During the execution phase in the non-OMA transfer mode to request more data
(5) The FDC interrupts when the FOC detects the issued command was invalid. In this case, the host should read the only Status register 0 from the FDC because the FDC can not set the "Present cylinder Number" byte.

Talking about the result parameters, this command has two types of result parameters after the FDC suddenly interrupts to the host and then the host issues this command to the FDC.
- One Byte Parameters
- Two Byte Parameters

One Byte Parameters

Regarding one byte parameter in the result parameter, this case occurs after the following:

- The FDC interrupts to the host to inform to detect the status of the target FOO in the polling routine to be waiting for the issued command. Especially, this status means the /CSTIN status from the FOO during the Apple operation mode and the REAOY_B pin during other operation modes.

- The host issues the Sense Interrupt Status command to the FDC after the interrupts for the following command occur.

- Disable/Enable OPLL

- Set Drive Mode

- Set Motor Control

- EJECT Command

- The host issues the Sense Interrupt Status command to the FDC in spite of not interrupted by the FDC.

Two Byte Parameters
Regarding two byte parameters in the result parameter, this case occurs after the following:
- The FDC interrupts to the host to inform to detect the termination of the Seek or Recalibrate command.

How to Receive Parameter in the Result Phase
The host should know how may bytes should be received from the FDC at the result phase of the Sense Interrupt Status command by checking the first byte at this result parameter. If this first byte indicates either the changed status for the target FOO or the invalid command received from

the host, the host should read only one byte from the FDC at this result phase. On the other hand, if this first byte indicates the termination of either the Seek or Recalibrate command, the host should read only two byte from the FDC at this result phase. ERROR CONDITIONS There are no error conditions for this command under both Apple and Standard modes.
95

Set Enable Control

Phase command
Execution

RN/ D7 D6 DS D4 D3 D2 D1 DO
w EN 0 0 1 1 0 1 1 w x x x x x x X DR

Remarks command code
Sets or resets Enable Pin according to ~pecified value.

FUNCTION
Under Apple mode only, this command is used to turn on or off the Enable Pin of the specified drive. Once the ENBL_B pin is set active by this command, the ENBL_B pin keeps the same state until this command makes this ENBL_B pin inactive. Only after this command is issued to reset the ENBL_B pin to inactive while this pin is active, this pin is then reset to inactive.
On the other hand, Immediately after asserting or deasserting the ENBL_B Pin of the specified FOO, the FDC will issue a normal termination interrupt to the host.
Note that the ENBL_B Pins of two FDD's can not be set to active at the same time by using this command. In addition, the host should remember which ENBL_B Pin is active because the FDC does not save the status for which FDD is enabled.
Regarding the polling sequence, the FDC can not poll the status for the two FDD's while one ENBL_B Pin is active after this command is issued. This means that the FDC can not detect the event that the media is inserted into another FDD while the ENBL_B Pin is active on another drive. After the ENBL_B Pin is reset to inactive by issuing this command, the FDC can then detect that the media is inserted into another FDD.

PARAMETERS

EN=l

The ENBL_B Pin of the FDD specified by the DR bit in the second byte is set to the active state.

EN=O

The ENBL_B Pin of the FDD specified by the DR bit in the second byte is reset to the inactive state.

ERROR CONDmONS
This command checks no status of the specified FDD therefore this command has no error conditions and the FDC always informs the host of a normal termination.

Set Drive Mode

Phase command
Execution

RMI D7 D6 05 D4 D3 D2 D1 DO

Remarks

w 0 FM 0 1 1 1 0 0 command code

w x x x x x x X DR

Sets drive mode to GCf or MFM via the /MFM command according to specified value.

FUNCTION
Under Apple mode only, this command is used to set the drive to either GCR or MFM mode. This is done by writing the /MFM mode control bit in the specified drive. After the /MFM command has been sent to the FDD, the FDC will monitor the /Ready status line to determine whether this command was completed or not. At the completion of the command, the FDC will issue a normal termination interrupt

ERROR CONDmONS
H the /Ready line is not asserted within 800msec after the command is asserted, the FDC should abort the command and issue an interrupt. When the interrupt is asserted, the FDC should mark the command as abnormally terminated and assert the EC bit in the Status register 0 (STO). The host will then issue a Sense Interrupt Status command to be read the EC bit

Set Motor Control

Phase command
Execution

RN/ 07 06 05 04 03 02 01 DO

Remarks

w MO 0 0 1 1 0 1 0 command code

w x x x x x x X DR

Sets /MOTOR ON command according to

S_Q_ecified value.

FUNCTION
Under Apple mode only, this command is used to turn the FDD motor on or off. This is done by writing the /MOTOR ON mode control bit in the specified drive. After the /MOTOR ON command has been sent to the FDD, the FDC will monitor the /READY status line to verify that th~ command was completed. At the completion of the command, the FDC will issue a normal termination interrupt.

MO= ..O" MO= "1"

Motor OFF Motor ON

ERROR CONDmONS
If the /Ready line is not asserted within 1 second after the command is asserted, the FDC should abort the command and issue an interrupt. When the interrupt is asserted, the FDC should mark the command as abnormally terminated and assert the EC bit in the Status register 0 (STO). The host will then issue a Sense Interrupt Status command to be read the EC bit.

Specify

Phase command

RNJ 07 06 05 04 03 02 01 DO

Remarks

w w

I 0 0 0 0 0 0 1 1

Step rate

Head Unload

command code

Head load

IND

FUNCTION
The Specify command is used to specify the initial values for several configuration parameters. There is no result phase and no error condition for this command.

PARAMETERS

STEP RATE
Under Apple mode, it is not necessary to specify the Step Rate, because the STEP command is fully handshaked with the FDO.
Under other modes, this Step Rate specifies the following interval of the step pulses generated by Seek, Recalibrate and Relative commands:

· for 200 FDO with 250kbps · for 200 FDO with 300kbps · for2HDFDO · for2EOFDO · for21DFDO

TSRT = 2msec
TSRT =1.67msec
TSRT = lmsec
TSRT = 0.5msec
TSRT =0.4msec

Step Rate(16)
0
1 2 3 4 5 6 7

time
16*TsRT 15*TsRT 14*TsRT 13*TsRT 12*TsRT 11*TsRT 10*TsRT
9*TSRT

Step Rate(16)
8
9 A
B
c
D
E F

time
8*TsRT 7*TsRT 6*TsRT 5*TsRT 4*TsRT 3*TsRT 2*TsRT 1*TsRT

HEAD UNLOAD TIME
Under Apple mode, it is unnecessary to specify this Head Unload time. Under other modes, this Head Unload specifies the following time to set the read/write head to unloaded state after the Read/Write group commands is executed:

· for 200 FDO with 250kbps · for 200 FDO with 300kbps · for2HDFDO · for2EOFDO ·for21DFDO

Head Unload(16)

time

Inhibited

16*THUL

32*THUL

48*THUL

64*THUL

80*THUL

96*THUL

112*THUL

1HUL=2msec 1HUL = 1.67msec THUL= lmsec 1HUL = O.Smsec THUL = 0.4msec

Head Unload(16)
8 9 A
B ·c
D
E ·F

time
128*THUL 144*THUL 160*THUL 176*THUL 192*THUL 208*THUL 224*THUL 240*THUL

HEAD LOAD

Under Apple mode, it is unnecessary to specify the Head Load time. Under other modes, this Head load specifies the following stabilizing time of the read/write head after loading at the start of the Read/Write group commands:

· for 200 FDO with 250kbps

1HLD=2msec

· for 200 FDD with 300kbps

1HLD = 1.67msec

·for2HDFDO

lHLD= lmsec

· for2EDFDO

1HLD = O.Smsec

· for21DIDO

1HLD = 0.4msec

100

Head Load(16)
00 01 02 03 04 05 06 07

time
Inhibited 2*THLD 4*THLD 6*THLD 8*THLD
10*THLD 12*THLD 14*THLD

Head Load(16)
08
09
I
70
7E 7F

time
16*THLD 18*THLD
· HLD
I
: HLD I HLD 250*THLD 252*THLD 254*THLD

ND The ND (Non-OMA) field, when set to 1, specifies that the FDC will transfer data to the host in interrupt mode under all operational modes.

101

Write Data

Phase Command
Execution

RAN 07 06 05 04 03 02 01 DO

Remarks

W MT FM TB O O 1 O 1 command code

W X X X X X HD DR1 ORO

Cylinder

Head

Sector

w (Bytes/Sector) I Format Byte

w Last Sector in Multi Sector Write

w GSL(MFM) I don't care(GCR)

Data Length in B_rtes

data transfer between Host and FOO

Status Regisiter o

status information

Status Regisiter 1

after this command

Status Regisiter 2

Cylinder

Head

Sector

JBv4-... ,C!.,..--rlLEo_rmat-8vte_

FUNCTION
The host can use this command to write sector data to the specified sector. After this command has been issued, the FDC begins reading the address header (or ID field). When all four bytes loaded during parameters, cylinder, head, sector and Number of data bytes in the sector, written at the command phase match the four bytes of the address header (or the ID field) from the disk, the FOC takes data from the processor byte-by-byte via the data bus and outputs it to the FDD.
After writing data into the current sector, the specified sector number is incremented by one, and the next data field is written into. The FDC continues this "Multi-sector write" operation until the issuance of a Terminal Count Signal or until the last sector is meet. If the Terminal Count Signal is sent to the FDC it continues writing into the current sector to complete the data field. If the host asserts the Terminal Count signal, while a data field is being written, the FDC will fill the remainder of the data field with zeros.
The Multi-sector Write operation of the FDC must support l:n

102

interleaving on all formats and transfer rates. Multi-sector Write operations while recording in GCR can accommodate any interleaving including 1:1. (When writing data in GCR, the write-splice occurs after the bit-slip bytes)

TAG BYTES

For GCR format;

TB =1

Data in the 12 Tag bytes should be transferred from the host.

TB =0

Data in the 12 Tag bytes are automatically filled with zeroes.

ERROR CONDmONS 1) When the FDC can not find the following within the 400msec for the GCR format, or when the FDC can not find out the following before two Index pulses are input for the MFM and FM format.
- Address Mark in the Address header (ID field) - Desired Address header (Data in the ID field )
2) When the FDC detects the read error in the following:
- CRC bytes or the Checksum bytes in the address header (or ID field)
- Bit Slip bytes only under GCR format 3) When the following conditions occur:
- WPRT_B pin becomes active - Overrun or Underrun occur during the data transfer. - When utilizing the TC input, it does not meet the correct timing period. - Under Standard modes, the READY_B pin in the drive interface is inactive before this is operated under Standard modes.

103

Write Deleted Data

Phase command
Execution Result

RftN 07 06 05 04 03 02 01 DO

Remarks

W MT FM O O 1 O O 1 command code W X X X X X HD DR1 ORO

Cylinder

Head

Sector

w Number of data bytes in the Sector

W Last Sector in Muliti Sector Read

GSL

Data Length in B}'tes

data transfer between
Host and FOO

Status Regisiter O

status information

Status Regisiter 1

after this command

Status Regisiter 2

Cylinder

Head

Sector

Number of data bytes read

FUNCTION
This command is used under Standard modes only and can not be supported under Apple mode. DAM and ODAM explained in the Write Data functions under standard modes are replaced with DDAM and DAM, respectively.

104

Verify

Phase command
Execution Result

RMI 07 06 05 04 03 02 01 DO

Remarks

W MT FM SK 1 O 1 1 O command code W EC X X X X HD DR1 ORO

Cylinder

Head

Sector

W Number of data bytes in the Sector
w Last Sector in Muliti Sector Read

GSL

Data Length in Bytes

data transfer between
Host and FOO

Status Regisiter O

status information

Status Regisiter 1

after this command

Status Regisiter 2

Cylinder

Head

Sector

Number of data bytes read

FUNCTION
This command is used under Standard modes.
This command has the same function as the Read Data command except that the OMA controller is set to the verify mode to transfer no data from the FDC to the host and to response the only DMAAK_B signal for the DMARQ signal without the active RD_B signal.

105

Version

Phase command
Result

PJN 07 06 05 04 03 02 01 DO

Remarks

w 0 0 0 1 0 0 0 0 command code

1 0 0 1 0 0 0 0 Echo back for this
command.

FUNCTION
This command is used under Standard modes. This command echoes back the '990H" at the result phase.

106

Chapter 5 Interface Timings
5.1.1 Host System Interface Timing
The host system interface timing diagrams for each command are shown in Figs.5.1-1 to 5.1-10. On the host side, in Command phase, check that RQM=l and 010=0 before writing data; in Result phase, check that RQM=l and 010=1 before reading data.
The timing of the READ DATA, READ ID, READ A TRACK, and RAW DUMP commands are shown in Fig.5.1-1.
· COMMAND PHASE
With the condition that RQM=l and 010=0, the RQM bit is reset when the command code is written to the data register of the FDC from the host. However, when contents of the data register are transferred to the FDC's internal command register, the RQM bit is set again and writing of the nex~ parameter will be requested to the host. When the HD,DRl and ORO bits are written from the host, then the RQM bit is reset. When those bits are transferred to the FDC's command register, the RQM bit is set, and writing of the next parameter will be requested.
The 010 bit remains 0 until the command code and all required parameters are written. Consequently, the host monitors the RQM bit for when it becomes 1, and writes parameters in sequence in response. However, upon receiving the last parameter, the FDC enters E-phase without setting the RQM bit. The FIFO is disabled during the command phase to retain compatibility with the µPD765, and to provide for proper handling of the" Invalid Command" condition.
· EXECUTION PHASE
The process differs depending on whether the data transfer mode is the Non-OMA mode (interrupt process) or the OMA mode. After reset, the FIFO is disabled (FIFO Depth = 1). The FIFO is available only in the Execution Phase of the FDCs operation. The CONFIGURE command is used to enable the FIFO and also set the FIFO threshold. After reset, each data byte is transfered then by an INT or DRQ depending on the OMA mode. For more information on OMA modes and FIFO operations, please refer to FIFO Operations in section 5.1.2.
In the interrupt process, first the 010 bits is set to 1, and when the first data of the data field read from the disk is set in the data register, the RQM bit is set and an INT request is output. After receiving the INT request, the host confirms that both the RQM and 010 bits are 1, then reads the contents of the data register. When the contents of the data register are read, the FDC
107

resets the RQM bit. In the same way, the data transfer is performed until the last data is transferred. When that data is read by the host, the DIO bit is reset after reset of the RQM bit.
When this process is performed in the OMA mode, before entering Cphase the host sets the data transfer direction in the OMA controller by program. In E-phase, the FDC outputs the DRQ signal each time the FDC sets data read from the disk to the data register. Upon receiving the DRQ signal, the host carries out the following sequence; it returns the DACK_B signal, outputs the RD_B signal, reads the contents of the data register, stores the contents in memory, and stops the DACK_B signal. When the DACK_B signal is input from the host, the FDC resets the DRQ signal.
In Execution phase, the RQM and DIO bits remain reset. When the last data is transferred, Execution phase terminates. At this time the FDC set the result status and the parameters to the internal register, outputs the INT signal to request the host to read those data, and enters R-phase. The NDM bit(DS) of the status register is then reset.
· RESULTANT PHASE
The FDC first sets the 010 bit, and when contents of the STO register have been transferred to the data register, the FDC sets the RQM bit and requests reading of the contents (the result status STO) of the data register. Upon receiving the INT signal, the host confirms that both the 010 and RQM bits are 1, then reads the contents (STO) of the data register. When the contents of the data register are read, the RQM and 010 bits are reset, then the INT signal is reset. After reading the STO, the host waits until the DIO
and RQM bits become 1, then reads the result status sn. In this way, when all necessary result status (STO, sn, and ST2) and parameters (C, H, S, and
N) are read from the FDC, the FDC sets dummy data, then sets the RQM bit and waits for the next command.
The FIFO is disabled during the resultant phase to retain compatility with the µPD765. The resultant parameters of the executed command are immediately available, without the FIFO.
The timing of the WRITE DATA, FORMAT A TRACK, and FORMAT/WRITE commands are shown in Fig.5.1-2. This timing is the same as that of the Read Data group commands except for the different data transfer direction (010=0) in Execution phase.
The timing of the SENSE DRIVE STATUS command is shown in Fig. 5.13. In the Command phase, only the command code and data specified by the HD, DRl, and ORO bit are written. There is no Execution phase for this command. In the Resultant phase, the INT signal is not output; therefore after Command phase, the host side confirms that both the DIO and RQM bits are 1, then reads the contents of the ST3 set to the data register and terminates command execution.
108

parameters,the FDC clears any.FIFO data to ensure the validity, and enters into the execution phase. In execution phase, the FDC can support the single and demand transfer, and allow the system some latency defined by threshold value When the data transfer terminates norm.ally or abnormally, the FDC enters into the result phase.At the beginning of result phase, the INT signal is generated. For each command, a defined set of result bytes has to be read from the FDC. The result byte may be read from the FDC after RQM=l and DIO=l of status register. When the HOST read the all parameters, the status register of FDC becomes RQM=l, DIO+O,CB=O,and result phase end.

5.1.2 1 FIFO Threshold
In using the FIFO, the HOST is allowed a large service latency without causing a overrun or underrun error. The user can program this latency to adjust his purpose. 'IHRESHOLD is defined as the number of available bytes to the FDC until the HOST starts to service the data from a FDC request (i.e.DMARQ is active).

ex: FIFO STATES WHEN DMARQ BECOMES ACTIVE (THRESHOLD=2)

FROM HOST TO FDC

0 1

13 14 15

H-~--T_L___I- -I Io Io IF~DC

0 data exist

t threshold position

The FDC takes out data bytes from the FIFO. When two data bytes are left in the FIFO, the FDC will activate the DMARQ. and request service from the HOST.

FROM FDC TO HOST

F.2:

0
l _

1
_

_Io_I-13-Io14

I1o5

I~ST

0 data exist ! threshold T position

The FDC takes data bytes into the FIFO. When the number of data bytes in the FIFO is 14 (the open cells are two), the FDC will activate the DMARQ and request service from the HOST.

110

Fig.5.1·1
'"cO:
~~
4E :: 0 (.)
fl)
gj ..cc:.
d:

READ DATA, READ ID, READ A TRACK, and RAW DUMP Commands

- Sets dummy data

Sets N Sets S Sets H Sets C Sets ST2 Sets ST1 Sets STO

co;0O<:::o:>:

<(W<(

wa:a:

a: Cll Cll

---<1>:5:5
.-.c:o...o...

~
E

m.l.!-!:2!

x]!x]?
<11<1>

<~~"ctCi~C:oco:

0e:< .:c::ti"0C-8
zo:o:!~5<:1a>:>lj

. . . ££*.~'(E.
f~C?~&i>

- Sets the last data
I

fl)
gj
w..cc:.
fl)
~
..c:
0..
0
'"cO:
~ ·~
E ~
0 (.)

.C')

- Sets the 3rd data
- Sets the 2nd data
- Sets the 1st data of the data field

- ..,_Receives DTL")It)

- ..,_Receives Gs!.)·

- ..,_Receives EOT/Bytes(LSB
- ..,_Receives N/Bytes(MSB) :=t

- ..,_Receives S

- ..,_Receives H

- ..,_Receives C

- ~eceives HD and DP/(RDM)

~eceives the command

'-......

_,/

Data register

I~ la:o . 0a:
0

(.) I-

~
a0 :

0
Ci

~
z 0

CD (.)

..!!? ~ c:: E

r§oi -E ·e-n..o.:

·rE-o

iai>i >-
Cl)

..../ '-...,,,_

113

__. Command

C-phase

wait

Signals( INT

to the

main

system

DAO

Command wait

C-phase
~

Slgmls( INT

to the

main

system

DAO

15ACK

Signals from the
main system
Status

-·"11
(C
..U1

-' I

(/)

ROM

m"'tJ

010

-0
-"1<1

(')

I I

0
3

I I

ttt

D> :J 0.

::D ::D :ti

fO Ill GI

0
Ill

00 0
I<ll. <Ill. ;G;:I·

fir

<D C'D CD
I/) fl) (/)

@
-(Q
iif
.I.l.l

!:f (/) :c 8CD ~::IJ ~r3 3~I o

~ * ·: Don't care in Apple mode.

Signals from the
main system

WR
tm

Status

ROM
010
CB
0
Ill
lit
@
(Q
![ .C..D,

I I I I I I
I I I

Ill <D

0 0

m!<!!.

~·
CD

I/)

g :c

Ill 0

0 Ill

3 0

:I
a.

30
~ ::D
a.

~ ~
01

A-phase

Command wait

.::!!
(C
!..J..I. I
(,.)

(/)
m z
(/)
m

0
<:mD

CJ)
-t
)>
c-t
CJ)

(/) {/J

:::s

~ !2.
(/)

{/J
(j

ac:. 3

Ill

iii'

Command wait
Signal'( INT
to the main system ORO

C-phase

E-phase --l~r-41--C-phase

._A-phase~

Command wait

"5ACK

Signals from the
main system

WR
A
D

Status

ROM
I I I

010

I I

I I I

DxB

I I I

I I

'l'i' CD i'

-· -· 0 0 0

CD
~

:C;D::·
(J)

GI
~

!2.
Ill

(I) (I) (I)
g :I: z

iil
Unl ·
.(.J..)

CD 0 0

0
0

Ill :J

3 a.

Ill JJ

:a:J.

*;This does not exist for RECALIBRATE

'JJ
CD 0 CD
-~·
(I)
::r
CD

en m O>

~ ~ !a.

(I)

en
~ 0

-0
0 z

ac . 3

0 0
3

!!!.
Ill

Ill

:aJ .

::;: Fig.5.1·5 SEEK and RECALIBRATE commands Fig.5.1-6 SENSE INTERRUPT STATUS command
°"

Command wait

Signals( to the main system

INT DAO

C-phase

Signals

from the

main

system

Status

ROM
I I

DIO

I I

'':D:D

CD CD

a 0

22
an~·

Ill

fll fll

cioil g--o:D

~ !!."
.C..D..

3 ~

E-phase

Fig 5.1-7 Disable/Enable DPLL, SET DRIVE MODE, SET MOTOR CONTROL and Set Enable Control commands

Command wait

Command

wait

s;gnals( INT

to the

main

system

DAO

---1~4'-- C-phas;e---..+..~Command wait

DACK

Signals

from the

main

system

ROM

Status

mo
CB

I I I I I I II II II II II

-0
Ill
I...l.l.
(I) (C
§.'

'''':D :II :II :D

<D <D CD <D

2~·

2
;§'

2~·

a8l'

fll fll tJI U1

agen.

0
_..

!!! en

:.n,,

~m ~

3 Q, 'Tl :D

I...l.l. 3gp;ii:;

[

·1~
r

·1: Don't care for the

o. CONFIGURE

s ~

·2: These do not exist for the SELECT CAPACITY

I \.'J2__.I *2
Fig.5.1-8 CONFIGURE and SELECT CAPACITY commands

Command --t~~i--C-phase --11..,,.__E-phase -;...,~I-- Command

wait

Signals( to the main\ system\

INT ORO

This signal is set Immediately.

Command wait

C-phase -phase __,....,..t-·+....1-1~4-
Command ~tt

Signals ( to the

INT - - - t - - - - t - - - - 1 -

main\

system\ ORO _ __..._ _-+--+--

Signals from the
main system

Status

ROM 010 CB
e 0
I»
al
<C ~·
9?

I I I I I I I I
tt
:::0 :::0 nCD nCD
C<D .<CD.
CD CD In In
:ro
CD :::0 n
0
3 3
I»
;a:I.

Fig.5.1-9 EJECT DISK command

Signals

from the

main

system

ROM

______ Status 010

....

CB _ _ __,

Fig.5.1-10

0
!!?.

':::0
nCD
«(1)

I..»..
(1)
co

-(1)
In :::T

~·
.C..D..

<II
n
0

I»

;a:I.

- *en en
(1)

en
d

ac . 3

I»

INVALID command

5.2 Drive Interface Timing Under Apple mode, drive interface side timing diagrams for each command are shown from Fig. 5.2-1to5.2-10. Under Standard modes, the Drive Interface timing is almost the same timing as that of the µPD76SA.
119

+Note ·1
---
ENBL_B

fNote ·1

--lx SEL, CAo-2__

/READY ~---------R-DD_A_T_A___________.~.....'-R_E_A_D_v______

ADATA_e-----c{ /READY ~ RDDATA ) t - - - - - - - - - - - - - - - - 8 ' R E A D Y ),__ _ _ __

LSTRB

WGATE_B

address header

GCR sync

sync

Track format

AM cksm

bit slip

MFM lsvNq I1011 GAP ~YN~ I

I I

AM CRC

Data Data

sync cks
bit slip
11 GAP
I CRC

Note *1 : This signal can be controlled by the only "Set Enable Control" command.

Fig.5.2-2 WRITE DATA

--t. ENBL_B __Nq_t_e_·1-------------------------------------------------~---'~.NmIe·1

-..1x x_____________ x SEL, CA0·2__

/READY ~INDEX

1c_s_T_IN________________ /READY

RDATA_s----( /READY ~INDEX ) 1 - - - - - - - - - - - - - - - - - - - - - - B / R E A D Y } - -

INDEX from RDATA_B
( for MFM format )

WGATE_B

WDATAwR.._________________--<~

"\,i_~i-----------------

1~--~~~~~~~-~ I

address

I
!

header

I
j

GCR

sync

Track format

AM cksm

cks

bit slip

MFM lsvN~ I1011 GAP ~YN~ I

Data

11 GAP

AM CRC

CRC

Note ·1 : This signal can be controlled by the only "Set Enable Control" command.

Fig.5.2-3 FORMAT A TRACK and FORMAT/WRITE

+Note *1

- - ENBL_B

....

SEL, CA0-2 ADATA_B
LSTAB

/STEP

DIRT /STEP

/STEP

( /STEP )

n
Set Direction

n
Step pulse

'Note *1

x/READY

//-ID)

( ) /READY

n II
II last Step pulse

Note *1 : This signal can be controlled by the only "Set Enable Control" command.

Fig.5.2-4 SEEK and RECALIBRATE

ENBL_B

+Note *1

SEL, CA0-2

ADATA_B LSTAB

fNote *1

/WRTPRT /READY

/TKO

/WATPAT /READY

/TKO

Mode ID or Select Media MFM mode

2MS..4MB

Mode ID Select Media MFM mode

SELECT MEDIA

Note *1 : This signal can be controlled by the only "Set Enable Control" command.

Fig.5.2-5 SENSE DRIVE STATUS

Fig.5.2-6 SENSE INTERRUPT STATUS

+Note *1

ENBL_B

x SEL, CA0-2_ _ _ _ /CSTIN X.__/R_E_Ao_v_ _ _ _ _ __

x )>------ RDATA_B - - - - - ( /CSTIN

/READY

·Note *1 : This signal can be controlled by the only "Set Enable Control" command.

125

Fig.5.2-11 Set Motor Control for Motor OFF

--*1~. Y_j ENBL_B

N-o-te_·_1_ _ _ _ _ _ Note ·1

X. . SEL, CA0·2J ./MOTOR OFF

_JR_E_A_o_v_ _ __

)>--- RDATA_B ---------<(/READY
LSTRB ____.n.._.n____
SEL MEDIA ./MOTOR OFF

f f Fig.5.2-12 Set Enable Control

Note *2

Note *3

- -... ENBL_B

SEL, CA0-2 Not defined

Not defined

LSTRB

Note *1 : This signal can be controlled by the only "Set Enable Control" command. Note *2 : The ENBL_B is set to the active state by the "Set Eanble Control" Note "3 : The ENBL_B is reset to the inactive state by the "Set Eanble
Control"
128

COMMAND WAIT STATE

Standard Modes
Star

Initialize FDC

Commandwai

Reset CB

y
N

Reset INT,Set CB

Reset HOLD signal

SendSTO
r---

· 1: Register Set are defined
= by PC Type Pins ·11 ·
(Apple Mode)

·1 I
Apple mode

Apple Mode

Initialize FDC
Check Drive Install If drive is not -------installed, set Oxl

1
Command wait

y
Reset INT,Set CB N
Reset INVALID Send STO

130

FORMAT A TRACK (GCR Format)
FORMAT A TRAC Receives HD, DR Receives parameters

rma in

- Address mark

- Address header When TB is set to

- Checksum

zero, write Tag byte

- Bit slip bytes

as all zero

- Self-sector bytes

- Data mark

- Sector

When TB is set to one,

-Tag bytes

Tag Bytes are

- Sector data

transfered

- Checksum

by host

Set NW

Set AT, NR

-----Abnormal termination SetAT

Set AT, NA
Set INT signal Send result statu Command wait

132

FORMAT/WRITE Receives HD, DR

FORMAT/WRITE (GCR Format)

Write self-sync bytes
ormattmg - Address mark - Address header -Checksum

Data formatting - Self-sync bytes - Data mark - Sector - Tag bytes(transfer) - Sector data(transfer) -Checksum - Bit sli b es

When TB is set to zero, write Tag byte as all zero
When TB is set to one, Tag Bytes are transfered by host

Set NW

Set AT, NR

__ ..Abnormal ....te_r_mination Set AT

Set INT signal Send Result status
Command wait
134

FORMAT/WRITE (MFM Format)
FORMAT/WRITE Receives HD, DR Receives parameters
N

Check for Index Pulse Preamble formatting
-SYNC
- INDEX address mark
ID formatting
-SYNC
- ID address mark -ID
-CRC

Set NW

Set AT, NR

- Data address mark - Data(transfer)
N y
Write GAP4 : 1byte

Write GAP3

Abnormal .___,___. termination
Set INT signal Send Result status
Command wait
135

POLLING

Drive scan Set#O
Status check Set #1
Status check
RET

Status check
Set INT
Wait 100ms
RET

136

RAW DUMP Receives HD.DR
Receives ROM

RAW DUMP
Set AT, NR Set AT, FIN

L
Set AT, EC

*1, *2

DMPfromAH

*1: for GCR format

...

Set INVALID ·2: for MFM format _ ___.,___ _ *See Diagrams on

send result status Following Pages

Command wait

N N Transfers Raw data

Set AT, AM

Set EN

Abnormal

Set AT

termination..__ __,._ __.

Set INT signal Send result status
Command wait

*3, ·4 DMPfrom DH *3: for GCR format ..4: for MFM format * See Diagrams on Following Pages
137

RAW DUMP
*1 : Dump from Address Header (GCR Format)
DMPfrom AH

Set DE

Transfer Raw data

SetMD,MA

Set EN Set AT

Abnormal termination

Set INT signal Send result status
Command wait

138

DMPfromAH

RAW DUMP
*2 : Dump from Address Header (MFM Format)

: 400ms
y

Transfers 8 x 8 data

Set MD, AM

Set EN Set AT

Abnormal termination

Set INT signal Send result status
Command wait
139

RAW DUMP
*3 : Dump from Data Header (GCR Format)
Set AM

Transfer Raw data

Set MD, MA, CM

Set EN Set AT

Abnormal termination

Set INT signal Send result status
Command wait
140

DMPfrom AH

RAW DUMP
*4 : Dump from Data Header (MFM Format)

$A1 for Data byte Set MD, AM, CM

____..$..0._A_ for

Clock

byte-~----
~~~~~~~~-t11~

Transfers Bx 8 data

Set EN

Set AT

Abnormal termination

Note 1: No set CM bit even if ODAM is detected

Set INT signal Send result status
Command wait
141

READ A TRAC

READ A TRACK (GCR Format)

Receives HD, DR

Receives parameters

Check ID Check checksum
Check bit slip

If checksum is NG, set DE.
If checksum is NG, set DE.

Set MA

Transfer data

- - - - - - If checksum is NG, Check checksum set DD, DE.

--Check

B-it

-slip

If checksum is NG, set DD· DE·

y
EOT=EOT-1

Ris#of remaining
sectors

Update ID

--------i~ Abnormal termination
Set AT

Read next sector regardless of number
Skip self-sync

Set EN

Set INT signal y
end result status
Command wait

* : Search the specified sector at first. If it be couldn't find by time out, set ND and terminate. Since 2nd sector, check ID
and set ND if the ID is NG · and continue the command processing.
142

READ A TRACK (MFM Format)
READ A TRAC Receives HD, DR Receives parameter

N N

Check ID Check CRC SkipGAP2

If CRC is NG, set DE.

Set MA

Transfer data

CheckCRC

If CRC is NG, set
DD.DE.
y

y
EOT:EOT-1
y

Ris#of - - - - - . '--------...i Abnormal

remaining Update ID

.----1....i termination

sectors

Set AT

SkipGAP3

Set EN

Set INT signal end result statu Command wait

* : Search the specified sector at first. If it be co1.1ldn't find by time out, set ND and terminate. Since 2nd sector,
check ID and set NO if the ID is NG, and continue the command processing.

143

READ DATA Receives HD, DR Receives parameters

READ DATA (GCR Format)
Set AT, NR Set AT, FIN

Skip seH-sync

y
Set EN

Abnormal ---1~ termination
Set AT
Set INT signal end result statu Command wait
144

READ DATA Receives HD, DR

READ DATA (MFM Format)

Receives parameters

S=S+1 SkipGAP3

Command wait
145

READ ID (MFM Format)

READ ID Receives HO, DR Receives parameter
N

N
y Abnormal termination,...__s_et_A_T__,

Set INT signal end result statu Command wait
147

N Set EC

RECALIBRATE
RECALIBRATE Receives DR Set DxB Set/DIRTN Wait 1µs
Generate 80 STEP pulses Wait 150µs
Generate 1 STEP towards the center of the disk

: MFM 18ms GCR 800ms

Generate 1 STEP towards the outer edge of the disk
N
y
Set SE Set INT Command wait

N : 18ms
N :18ms
Set NA
148

SEEK
SEEK Receives DR
Set DxB Receives NCN y
Set/DIRTN M +-I NCN - PCN I -1
Wait 1µs Calculate the time out for /READY

M=M-1 Wait 72µs

Wait 150µs
Set SE Set INT Command wait

Set EC

: 1Sms, 250ms or BOOms

Set NA

: 1Srns, 250ms or BOOms

149

SENSE DRIVE STATUS
SENSE DRIVE
Receives DR
Set /ENBL signal
Read FOO status bits -/2MB or /4MB Media -J\IVRTPRT -/READY -/TKO -2MB-4MB Drive -Mode ID -Select Media -MFM mode
Reset /ENBL signal
Send ST3
Command wait

SENSE INTERRUPT STATUS
ENSEINTERRUPT N N

Set SE Check EC

Set At RKO,/STE

Set INVALID Send STO

Check /CSTIN Check /READY

If a disk is not in the drive, FIN is set.
If not ready, NA is set.

SendSTO

Reset DxB

SendPCN

Command wait

150

SET DRIVE MODE
SET DRIVE MODE Receives DR Receives FM
SeVreset MFM mode signal
Set 800ms Timer
Set INT Command wait
SET ENABLE
Set Enable Control Rec:elveEN
Set or Reset ENBL_b Signal
Set INT Convnand Wait
151

SET MOTOR CONTROL

SET MOTOR CONTROL Receives DR Receive MO N
Set /MOTOR ON signal
Set 600msec Timer

Reset /MOTOR ON signal
Wait 5µsec

Set INT Command wait

SPECIFY
SPECIFY Receives ND Command wait

152

WRITE DATA Receives HD, DR

WRITE DATA (GCR Format)

Set NW

Set AT, NR

y
Write data Write checksum

R=R+1 Skip self-sync

r----''----. '----------------!~ Abnormal
.---~termination
Set AT
nd result statu Command wait
153

WRITE DATA Receives HD, DR

WRITE DATA (MFM Format)

N y
N Set NW

Skip GAP2 Write SYNC, DAM
Transfer Data Write CRC, GAP
y y
y
S=S+1 Skip GAP3
SIDE=1, 8=1

Abnormal termination Set AT
Set INT signal end result status Command wait
154

Chapter 7 DC I AC Specification

Absolute Maximum Ratings
TA=+25 °c
Supply voltage,Voo Voltage on any pin (except Voo> Operating temperature,ToPT Storage temperature,TsTG

-0.5 to +7.0 V
·0.5 to Voo+0.5 v
-10 to +70 oc ·65 to +150 oc

Capacitance
TA= +25 °c ; Voo =OV ; f = 1 MHz

Parameter

Symbol

Min Max Unit Conditions

Clock capacitance Cg Input capacitance CJN Output capacitance CQUT

20 pF Unmeasured pins returned to 0 V
20 pF
20 pF

155

DC Characteristics
°c; TA·-10to + 70 Voo-+SV± 10%

Parameter

Symbol Min

Low-level input voltage V1L

High-level input voltage

V IL1 V1H

V1H1

Low-level output voltage VOL

-0.5 -0.5
2.2
0.8VDD

VoL1

High-level output voltage VOH 3.0 (Note1)

Input leakage current

I 1L

Output leakage current IOL

Voo supply current Standby current

I CD
I~

Max

Unit Conditions

0.8

v Except XA1

o.2v 00 v XA1

Voo+0.5 v ExceptXA1

Voo+0.5 v XA1

0.45 0.45

v IOL= 12mA
00-07,0MARO,INT, TOO
v la.=48mA
All other outputs

Voo

v I OH=-4.0mA

00-07,DMARO,INT,

TOO

+10

µA ·v1N=Voo

-10

µA VIN=OV

+10

v µA OUT= Voo, Host l/F

-10 + 100

µA V OUT= 0.45 V ,Host l/F
v µA our= Voo' FOO l/F

-100

µA VoUT· 0.45 V ,FOO l/F

100

µA

Note 1 : All of FOO interface outputs are Open Drain outputs. In PC/ATTN Mode, OMARO and INT outputs become Open Drain outputs.

156

Clock Specifications
TA .. -10 to + 70 °c ; Voo =+SV ±10%

Parameter

Symbol Min Typ

Max Unit Conditions

Crystal Resonator Source

Clock cycle

tcYA

41.66

(24MHz)

Clock cycle permitted

± 0.5 %

Oscillator

tKS

stabilization time

External Clock Flg.1

Clock cycle

tcvA 41.46 41.66 41.87 ns
(24MHz)

tcve

63.42 63.82 64.42 ns (15.6672 MHz)

49.75 50.00 50.25 ns (20MHz)

XA1,XA2.
XA1 pin. XB pin. ForGCRFDD XB pin. For 13Mbyte FOO

Clock high-level width IKKH 12

Clock low-level width tKKL 12

Clock rise time

tKR

Clock fall time

tKF

Recomm.nded Circuit ..

ClyNI Clack Oecll.aan.

24MHz N.C.

15.6672MHz 20MHz

MUX

XA1 XA2
)IPD72070
DENO X8 DEN1

"'-n.-ndedCln:ulll!

Clyatal RHonllOf

·24Yiz 15.8672M-lz
20t.l-lz

XA2
j&PD72070 DENO
XB DEN1

157

AC Characteristics
°c; TA= -10 to+ 70 Voo= +SV ±10%

Parameter

Symbol Min Max Unit Conditions

Host Read Timing Flg.2

AO·A2,CS_b,DMAAK_b setup to RD_b active tAR

AO-A2,CS_b.DMAAK_b hold from RO_b inadive tRA

RD_b adive pulse width

tRR 50

DATAv~idfrom RD_badive

!RD

40 ns

DATA float delay from RD_b inadive

toF

50 ns

DATA hold from RO_b inactive

tRoH 5

RD_b inadive pulse width

tRH 50

INT delay from RD_b inactive

IRI

50 ns

----
---

Host Write Timing Flg.3

AO-A2,CS_b,DMAAK_b setup to WR_b active tAW 5

AO-A2,CS_b,DMAAK_b hold from WR_b inadive twA 5

WR_b adive pulse width

tWN 50

DATA setup to WR_b inadive

tow 50

DATA hold from WR_b inadive

two 5

WR_b inactive pulse width INT delay from WR_b inactive

twti 50

twl

so ns

158

Parameter

Symbol Min Max Unit Conditions

OMA Timing Flg.4
DMARQ cycle period DMAAK_b active to DMARQ inadive RO_b I WR_b adive to DMARQ inactive OMAAK_b setup to RO_b I WR_b active OMAAK_b hold from RD_b I WR_b inactive DMARQ adive to RO_b I WR_b active
TC pulse width TC active to DMARQ inadive
OMAAK_b active pulse width DMAAK_b inadive pulse width OMARQ active to DMAAK_b adive DMARQ active to RD_b I WR_b inactive DMARQ adive to TC adive
Reset Timing Flg.5
RESET pulse width RESET to control inactive

tMCY 8/DTR

µs Note 1

tAM

50 ns

tRWM

50 ns

tARW 5

tRWA 5

tMRWA 0

lTC 50

tTM

50 ns

tAA 50

tAI

tMA 0

tMRW

6.5/0TR µs Note2

tMT

6.5/0TR µs Note2

110 tcvA Note3
2 µs

Note1 : DTR means Data Transfer Rate.For example ,when Data Transfer Rate is 500Kbps,DMARQ cycle period is as follows. tAW· 8/DTR-8/500000·16µ.s
Note2 : OTR means Data Transfer Rate.This value , 6.5 / DTR , appear Over-Run error timing with the FIFO disabled. When the FIFO enabled , add (FIFO-threshold x 8 / DTR) to the this value.
Note3 : This value include Hardware Reset pulse width , waiting term after the SOFTWARE RESET command wrote and waiting term the FOCRST_b bit of Digital Output Register (DOR) adivated.

159

Parameter

Symbol Min Max Unit Conditions

MFU FDD Write Data Timing WDATA_b pulse width SIDE_b setup to WGATE_B active

Flg.6 twoo 0.125/0TR tsoWG 100

-----s Note1 -----
µs

SIDE_b hold from WGATE_b inactive MFAf FDD Read Data Timing

twGSO 750
Flg.7

µs ------

RDATA_b pulse width

tRDO 50

RDATA_bcycle period

tRDCY

800 ns 1.25Mbit I sec

AfFM FOO Control Timing Flg.8

DIR_b setup to STEP_B active

tDST 0.5/DTR

DIR_b hold from STEP_B inactive

tSTD 12JOTR

STEP_b pulse width

tsTP 3'0TR

STEP_b cycle period INDEX_b pulse width

tsc

500/DTR

s Note2

taox 100

Note1 : DTR means Data Transfer Rate.For example ,when Data Transfer Rate is 500Kbps,WDATA pulse width is as follows.
twoo · o.125n:>TR - o.1251500 ooo - 250 ns
Note2 : DTR means Data Transfer Rate.For example ,when Data Transfer Rate is 500Kbps, Step pulse width is as follows.
tsc · 500/DTR · 500 / 500 000 · 1ms

160

Flg.1 External Clock XA1,XB

M---tCYA,tCYB --...t tKF

Flg.2 Host Read Timing

AO-A2
cs
DMAAK

----~~!c'o--tA-R--~--~---------t--R--R-------~..... ------

00-07

Vaid DATA

---------------------------~~--
INT

161

Flg.3 Host Write Timing

00-07

tWD Valid DATA

INT

Flg.4 OMA Timing

OMARO DMAAK

,_.-----------tMCY--------~

WRNA

....- . . - + - - tMA

tAM

-----i

. . - - . . . . - - tAA----~l..L

Ro/WR

tMT-~:~~~~-tTC-_-_tTM_--~-~~~~~-~----

162

Flg.5 Reset Timing

RESET
DRQ
INT
WGATE

1 i - - - - tRST --~

)

tRC-x

Flg.6 MFM FDD Write Data Timing

tWGSD
WGATE
---O-v
WDATA
Flg.7 MFM FDD Read Data Timing
RDATA

163

7.1 AC Timing Diagrams for the Apple Disk Interface

READJNG DRIVE STATUS
The following timing applies to /DIRTIN, /STEP, /MOTOR ON, EJECT, 2MB DRIVE, 4MB DRIVE, Mode ID, RDDATA, /DAVIN, /TACH, or INDEX, /READY, /CSTIN, /WRTPRT, /TK0, /2MB MEDIA, /4MB MEDIA, MFM MODE.

ENBL_B SEL, CA0-2
LSTRB RDATA_B

' J

!\.

J \.

T1 ~ f-4- ~ f-4- T2

'_J
~ ~T3

T1: O.Sµs max T2: O.Sµs max
T3: O.Sµs max for high impedance state

165

READING RDATA

READY_B
T1 SEL

WGATE_B

RDDATA

GCR mode

T1: 0.5µsec max T2: 1OOµsec max T3: 190µsec max T4: 0.15µsec min, O.Bµsec max T5: 2.4,6µsec nomal T6: 1OOµsec min
MFM, 1MB mode

MFM, 2MB mode

T1: 0.5µsec max T2: 1OOµsec max T3: 190µsec max T4: 0.15µsec min, O.Sµsec max TS: 2,3,4µsec normal T6: 1OOµsec min

T1: 0.5µsec max T2: 1OOµsec max T3: 340µsec max T4: 0.15µsec min, O.Sµsec max TS: 2,3,4µsec normal T6: 1OOµsec min

MFM, 4MB mode
T1: 0.5µsec max T2: 1OOµsec max T3: 340µsec max T4: 0.15µsec min, O.Bµsec max TS: 1,1.5,2µsec normal T6: 1OOµsec min

166

SENDING A CONTROL COMMAND
ENBL_B SEL, CA0-2
LSTRB T3 T4
T1: O.Sµsec min T2: 1.0µsec min T3: 1.0µsec max T4: O.Sµsec max TS: O.Sµsec min
167

/STEP AND /DIRTIN TIMING

ENBL_B

DIRTN_B ----+--I
STEP_B

T4
TS

T1: 1.0µs min T2: 0.5µs min T3: 72µsmin T4: See NOTE T5: 37µs min T6: 0.5µs min
NOTE: It is not allowed to change /DIRTN during head movement or head setting.

168

/STEP AND WGATE TIMING
WGATE_B
STEP_B
T1 GCR mode
T1: ~ 90µs min MFM mode
(1MB) T1: 190µsec min (2MB) T1: 340µsec min (4MB) T1: 340µsec min

/READY FOR TRACK ACCESS

STEP_B

READY_B

- .. - T1 ..

T1: 1SOµsec max.
T2: 1Smsec max. to move one track without speed block change 250msec max. to move one track with speed block change ( GCR mode ) SOOmsec max. for any case when step pulses are sent at the maximum rate

169

/READY FOR MOTOR-ON OR DISK-IN

ENBL_B

MOTOR ON_B

CSTIN_B

READY_B

T1: 600msec max. T2: 0.5µsec max. T3: 1.0sec max. T4: Sµsec max.

170

/WGATE, WDATA, AND /ERASE TIMING

ENBL_B
REAOY_B T1
WGATE_B T2
ERASE_B
WDATA (GCRshown>~~~~~~~r-~
WDATA ( MFM shown)

T5 T6~

Note: ERASE_B is a signal internal to the drive.

GCR mode
T1: 0.5 µsec min.after stepping 600msec min.after motor on
T2: Same as T1 T3: 1.Sµsec min. T4: 2µsec min. T5: 0.5 µsec min. T6: Same as T5

MFM; 1MB, 2M8, and 4MB mode
T1: 0.5 µsec min.after stepping 600msec min.after motor on
T2: Same as T1 T3: 4µsec min. T4: 2µsec min. TS: 0.5 µsec min. T6: Same as T5

171

TKO TIMING

ENBL_B DIRTN_B
STEP_B
TKO_B
T3 T4
T1: 3.0msec max. T2: 3.0msec max. T3: 150µsec max.
T4: 1Smsec max.

T3 T4

172

/CSTIN AND /MOTOR ON

MOTOR ON_B _ _ _~~

LSTRB

l T1

for the Ejecting - - - - - - -

CSTIN_B -------1------------1
T3
ENBL_B ------------------+----!

T4
T1: 200msec min. T2: 1.0µsec min. T3: 1.5sec max. T4: 150µsec min.

173

MOTOR START

MOTOR ON

READY_B

Motor Speed settled in +1.5%

T1: 600msec max
T2: 1sec max

.-.

174

SPEED ZONE BOUNDARY CROSSING, MOTOR SPEED SETTLING TIME

STEP_B
READY_B Motor Speed settled in ~ 1.So/o

J
J

T1: 250msec max. T2: 250msec max.

-.-
__.,

175

SEL, CA0-2 LSTRB
READT_B

/READY FOR MODE CHANGE (MFM TO GCR OR VISE-VERSA)
,,~~ode change
l

~ ~T2

T1: 800msec max. T2: 20msec max.

SPECIAL CONDITION FOR INDEX WHEN WRITING DATA

ENBL_B----..

x___ x___ SEL, CA0-2___

,_ND_E_X_ _ _

An_yt_hin_g_bu_tJN_D_E_ x _ _ _ __

'( RDATA_B _ ___,x~~A--'~

x____:-

Assertion of INDEX

WGATE_B

Natural De-assertion of INDEX

WDATA

176

Chapter 8 JTAG Specification
8.1 Features
This JTAG implementation into the FDC has the following features:
1) Compatibility with IEEE1149.1 }TAG Boundary Scan Standard 2) Only three Registers:
- Instruction - Bypass - Boundary Scan (There is no Identification or other Test Data registers in the FDC) 3) Supports the following instructions: - Bypass instruction - Sample/Preload instruction - Extest instruction - No support for RUNBIST, Intest and other instructions 4) Special pins for }TAG: -TCK
- TMS
-TDI
-TOO
8.2 Block Diagram Fig. 8.2 shows the block diagram of this implemented }TAG, which is mainly consisted of the TAP controller, the Instruction register, the Instruction decoder, the Bypass register and the Boundary Scan register. The Instruction register is consisted of the two bits shift registers and the instruction data to be written should be transfered through the TDI pin. The written data as instruction can determine what register should be selected or what a kind of instruction should be operated. The TAP controller can change its operated state according to the data of the TMS latched at the rising clock of the TCK pin. The Bypass register is consisted of one shifted register to be connected between the TDI and the TOO pins in the Shift-DR state of the TAP controller and to be shifted toward the TDO pin at each the falling of the TCK pin when this register is selected during the shift-DR state in the TAP. Especially, when this instruction is selected, the operation of this JTAG circuitry does not effect on
177

the _operation of the FDC.
The Boundary Scan register is located between the external pins and the internal logic in the FDC and this register can latch or load data according to the instruction from the TAP controller when this register is selected.
This register is to be shifted toward the TDO pin at each the falling of the TCK pin and to output the LSB (Least Significant Bit) from the TDO pin when this register is selected during the shift-DR state in the TAP. Especially, when this instruction is selected, the operation of this }TAG circuitry does not effect on the operation of the FDC.

VDD TOI

Boundary-scan register

Bypass register
Instruction decode

Output TDO
MPX buffer

Instruction register~---~-

VDD

TAP

controller

....~~--t---~----~------~----------------
TCK Fig 8.2 A Block Schematic of the Test Logic

8.3 Pin Functions There are four pins to be needed for this JTAG circuitry; TCK, TMS, TDI and TOO. The TCK pin can be used to provide the clock signal for only this JTAG circuitry. This clock signal is separated from the FDC system clocks in this
178

chip. The TMS pin can be used to define the operated TAP controller according to the value of this pin latched at the rising of the TCK pin. In addition, this pin is internally pulled up by the resistor with approximately from SOk Ohm to 200k Ohm. The TOI can be used to transfer data into the internal registers implemented in this }TAG circuitry. This pin also internally pulled up by the resistor with approximately from 50k Ohm to 200k Ohm. The TOO can be used to be provided the output data from internal registers. The output signal is changed at the falling of the TCK pin. In addition, the output of this pin have three states; high, low and high impedance in logical states to be controlled by the TAP controller.
8.4 Operations
8.4.1 TAP Controller The TAP controller is a synchronous finite state machine that responds to changes at the TMS and TCK signals of the TAP and controls the sequence of operations of the circuitry defined by the IEEE standard 1149.1.
8.4.1.1 TAP Controller State Diagram The state diagram for the TAP controller is as shown in Fig 8.4.-1. All state transitions of the TAP controller occurs based on the value of TMS at the time of a rising edge of TCK. Actions of Instruction, Boundary-Scan and Bypass registers occur on either the rising or the falling edge of TCK in each controller state as shown by Fig 8.4.-2
179

Test-Logic

-Reset

Run-Test/ 1

Idle

Select-

DR-Scan

0
1 Capture-DR

0
Shift-DR

Select-

IR-Scan

0
1 Capture-IR

0
Shift-IR

1
Exitl-DR

0
Pause-DR

1
0 Exit2-DR

1
Update-DR

1
Exitl-IR

0
Pause-IR

1
O Exit2-IR

1
Update-IR

NOTE: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edqe at TCK.
Fig 8.4-1 TAP Controller State Diagram

180

TCKj 1 L

Controller state =x::...-~~~...-~...--xr...-...-,..._~-

t
State entered

t
Actions occurring on the rising
edge of TCK in the state

Actions occurring on the fglling edge of TCK in the state

Fig 8.4-2 TAP Controller State Diagram

181

HEAD Indicates the logical head number on the written data in media
SECTOR Indicates the sector number
BYTES/SECTOR (MFM) I FORMAT BYTE (GCR)"
Code to indicate the data length in a sector (MFM). Code to indicate the data length in a sector (GCR). LAST SECTOR IN MULTI-SECTOR READ(or WRITE) Indicates the last sector number to be accessed on the track GAP3 (GAP3 Length) Indicates the number of bytes to be written in GAP3 GSL (Gap3 Skip Length) Indicates the number of bytes to be skipped in GAP3 DATA LENGTH IN BYTES Specifies the data length per sector to be accessed only when the 'Number of data bytes in the sector" is set to 0 in the FM format. NCN (New Cylinder Number) Indicates the cylinder number being seeked PCN (Present Cylinder Number) Indicates the cylinder number where the read/write head is located ND (Non OMA transfer) When this bit is l(high), Non-OMA transfer mode is specified. # SYNC GROUPS(GCR) Under Apple mode, specifies the number of the Self sync groups.
PARAMETERS USED IN THE MFM AND FM FORMATS JAM is the special Address mark immediately after the Index position. SYNC is the bytes that the PLL needs to synchronize with the input data from FOO before FDC read the ID field or the Data field. IDAM is the special address mark in the ID field. r;>AM is the special address mark in the Data field. ODAM is the special address mark in the Data field, which is written by the Write Deleted Data. CRC is the Check Redundancy Cyclic bytes. Gapl is located between the "JAM" and the SYNC bytes in the first sector immediately after the Index position. Gap2 is located between the ID and Data fields. Gap3 is located between Sectors.
48

ID field ------1.~ ..

----1..,,_... ..~ .. ------ Datafield

Sync byte

Address mark

address header

GAP2

Sync data address

byte

mark

data

GAP3

00.·.o A1 A1 A1 FE c H s N CAC 4E ·· 4E 00···o A1 A1 A1 FB xxx...x CAC 4E ·· 4E

self Sync byte

transfered data from this point from

--------11.. .,. .,..._______ ID field

Data field -----~.~ ..

Address mark

address header

Bit slip byte

self Sync byte

data mark

T_:9 data

Bit slip byte

... XX···X DE AA

transfered data from this point from
Fig. 4.18.2 Transferred Data for Dump After Specified ID Address Mark

Read A Track

Phase Command
Execution

RAN 07 06 05 04 03 02 01 DO

Remarks

W O FM TB O O O 1 o command code
w X X X X X HD DR1 ORO

Cylinder

Head

Sector

w (Bytes/Sector) I Format Byte

# of Sectors to be read

w GSL(MFM) I don't care (GCR)

Data Len_g_th in Bytes

data transfer between

Host and FOO

Status Regisiter O

status information

Status Regisiter 1

after this command

Status Regisiter 2

Cylinder

Head

# of Sectors to be read

·1

R l_B_yt_e_sLS_ectorl I F_o_rmat B_yt_e

FUNCTION
Under Apple Mode:
This command is similar to the Read Data command, except that this is a continuous read operation where the data field in each of the sectors is read. Unlike multi-sector reads with the Read Data command, this command will read the sectors as they are encountered on the disk. However, by this command, FDC can only read the media with the sector number in physically sequential order (like 1, 2, 3, 4, ....). So, in the case of interleaved media (like 1, 9, 2, 10, ....),the FDC can not read the sectors sequentially, but will read the sectors as they encounter, which will set ND bit (also see the description of Status Register 1 on p. 42). Immediately after finding the sector specified in the command phase, the FDC starts reading all data fields on the track as continuous blocks of data. Even if the FDC finds an error in the Address header or Data Checksum bytes, it will continue to read the data from the track, but will mark the error in the Status register 0-2 in the result phase.
This command terminates when the number of sectors read is equal to the number specified in the command phase.

Seek

..r"':.oase Command
Execution

_BNi_ 07 06 05 04 03 02 01 DO

RJtm..ark...s.

w 0 0 0 0 1 1 1 1 command code w x x x x x X DR1 ORO

New C_l1inderNumber

Head is positioned over specified cylinder.

FUNCTION
This command causes the FDD to retract the Read/Write head to the cylinder to be programmed in the ''New cylinder Number" byte.

Under Apple mode:
The FDC executes this command by issuing the /Step command to the FDD. To determine that the /Step command has completed, the FDC reads the /Ready status line from the FDD. This provides a full handshake for the step operation. The following conditions are not supported by this command: ·
- Seek with no media installed
- Seek on more than one drive simultaneously
- Check status of the /DIR.TIN signal during the seek operation

Under Standard modes:
The FDC operates this command if the internal parameter of ''PCN" is not equivalent to the "New Cylinder Number"(NCN).
When NCN > PCN:
The DIR_B signal in the drive interface becomes active low and then the required number of the step pulses are issued to the FDD and the number of this PCN will be incremented per step pulse.
When NCN < PCN;
The DIR_B signal in the drive interface becomes inactive high and then the required number of the step pulses are issued to the FDD and finally the number of this PCN will be decremented per step pulse.

The interval time between the step pulses should set by the Step rate parameter in the Specify command. When PCN becomes equal to NCN, the SE bit in the Status register 0 is set and the FDC interrupts to

Select Drive Type

Phase command
command

RN/ 07 06 05 04 03 02 01 DO
w 00110010
x x x x x x 01 DO

Remarks
command code Echo back for this command.

FUNCTION
The Select Drive Type command selects the type of drive that the next command· will be executed on.

01 DO

FOO Conventional FOO ( Reset Default ) FOO =<4MB 13 MB FOO RESERVED APPLE FOO

The timing of SPECIFY command is shown in Fig.5.1-4. This command has only Command phase. The command codes, (SRT/HUT, and HLT under only Standard modes) and ND are written to the FDC in that order, and command execution terminates.
The timing of the SEEK and RECALIBRATE commands are shown in Fig.5.1-5. However, for the RECALIBRATE command the cylinder number to be sought is fixed (cylinder 0), and therefore the NCN parameter is not necessary. For either command, when the seeking operation to the desired location is confirmed, the FDC outputs the INT signal to the host to inform that seek operation is completed. In addition, these commands differ from other commands in that they have no Resultant phase. Consequently, result status are output in the R-phase of the SENSE INTERRUPT STATUS command given after the INT signal is confirmed.
The timing of the SENSE INTERRUPT STATUS command is shown in Fig.5.1-6. When the INT signal is output from the FDC and bit 4 (FDC Busy) of the status register is 0, this command checks the cause of the interrupt request. When this command is written, the FDC resets the RQM bit and INT signal and enters R-phase. The status at the time the interrupt is generated can be found by reading the contents of the STO and the PCN in the R- phase of this command.
The timing of the TMVALID command is shown in Fig.5.1-10. The Invalid command is activated when either of the following occurs;
·If a command code not defined as a valid command is written in Command phase.
·If the SENSE INTERRUPT STATUS command is written but the cause of the interrupt no longer remains.
In either instance, 80(16) is set to the STO register to be read in Resultant phase as an invalid command and the FDC waits for the next command.
5.1.2 FIFO Operations
The FDC has the FIFO and all the data transfer can go through the FIFO. The FIFO is 16 bytes in size and programmable threshold value. In this description, "threshold" is defined as the number of available bytes to the FDC until the HOST starts the service from the FDC request, and range from 1 to 16. The threshold parameter which the user programs is one less and range from 0 to 15. The FDC can support the single and demand transfer. After a reset, the FIFO is no available. This reset default is changed by issued "CONFIGURE" command, and the FIFO operation becomes available with threshold control. The effectivity of FIFO is that it can allow the system a larger OMA latency without causing a overrun/underrun error.
In command phase, the command and their parameters must be sent by checking RQM=l and 010=1 of status register. After receives all
109

MAX SERVICE DELAY

The service latency is defined by the following formula:

Delay = Threshold x (Sbits/data rate)-12 x internal clock period

for example

Threshold = 8 bytes Data Rate=0.5Mbps

from HOST to FDC

Bbyte x (8bits/0.5µsec)-12x0.125usec = 126.6uSec

5.1.2.2 OMA Modes There are two OMA Data Transfer modes: (1) Single Transfer mode (2) Demand Transfer mode

DMARQ

- - - _j

4\_

DMAAK_B ~ -i__r - - - ~ -L_r

RD_B(WR_B)--uL_J - - LI - - - ~ - - Lr

Single Transfer Mode

DMARQ _}
DMAAK_B RD_B{WR_B)

4\_

,_________r

Demand Transfer Mode Fig. 5.1.2.1 Host Interface During the OMA transfers
Data Transfers from FDC to HOST When the number of bytes in FIFO is less than or equal to <16 - threshold>, a DMARQ is activated. By the FDC request, a OMA controller starts data transfer from FIFO to HOST. The FDC will deactivate the DMARQ when FIFO becomes empty. DMARQ goes inactive after DMAAI< goes active for the last byte of a data transfer (in OMA controller's single transfer mode) or on

111

the active edge of RD_B on the last byte( in OMA controller's demand transfer mode).
DataTransfers from HOST to FDC When then number of bytes in FIFO is greater than of equal to <threshold>, a DMARQ is actives. By the FDC request, a OMA controller starts data transfer from HOST to FIFO. The FDC will deactivate the DMARQ when FIFO become full. DMARQ goes inactive after DMAAK goes active for the last byte of a data transfer (in OMA controller's single transfer mode) or on the active edge of WR_B the last byte(in OMA controller's demand transfer mode).
5.1.3 Non-DMA mode Data Transfers from FDC to HOST
The INT and RQM bit in the Main Status Register are activated when the number of bytes in FIFO is less than or equal to the <16-threshold>. The HOST must start to read the data from the FIFO by request the FDC, and repeat until the data in the FIFO is empty. The FDC will deactivate the INT and RQM bit when the FIFO becomes empty.
Data Transfers from HOST to FDC The INT and RQM bit in the Main Status Register are activated when the number of bytes in FIFO is greater than or equal to the <threshold>. The HOST must start to write the data to the FIFO by request the FDC, and repeat until the data in FIFO are full. The FDC will deactivate the INT and the RQM bit when the FIFO becomes full.
112

Fig.5.1·2 WRITE DATA, FORMAT A TRACK, and FORMAT/WRITE commands

Q) VI
.«acI.
ci:

Q) VI
w.a«cI.

Q) VI
.«ccI.
0

"'C t: IC_.

a
0:

E "iii

E 3:

(.)

I~ I~

-Sets N -Sets S -Sets H - Sets C -Sets ST2 -Sets ST1 -sets STO
-Receives the last data
I

-Receives the 3rd data

-Receives the 2nd data

-Receives the 1st data of the data/ID fie d
~Receives DTLJol:t"
.......Receives GSUGPL ~Receives EOT
~ReceivesN
~Receives s)(I')
~Receives Hr ~Receives CJ .,..Receives HD and OR ~~ceives the com~

:ae
0:

0
Ci

:e
0 z

CD
(.)

'-.......--~~~~~~-__,.,,/

Data register

114

tNote *1
ENBL_B

tNote ·1

_,X X.. _________ SEL, cAo-_2__

/READY

R_o_o_A_TA_ _ _ _ _ _ _ ___.~__,_RE_A_o_v_ _ _ _ __

X. . ________ RDATA_e----( JREADY

R_o_o_A_T_ A _ _ _ _ _ _ _ _ _~ /READY)>-----

LSTRB

WGATE_B

WDATA_B

address header

GCA sync

Track format

AM cksm

bit slip

MFM lsvN4 I1011 GAP ~vNg I

AM CRC

Note *1 : This signal can be controlled by the only "Set Enable Control" command.

Data Data

11 sync ck~t
bit slip
11 GAP I
CRC

Fig.5.2-1 READ DATA, READ ID, READ A TRACK, and RAW DUMP

Fig.5.2·7 Disable/Enable DPLL

ENBL_B SEL, CA0-2

~Note ·1
x /DPLL

f Note *1
I

RDATA_B LSTRB

n
/DPLL

Note *1 : This signal can be controlled by the only "Set Enable Control" command.

Fig.5.2-8 SET DRIVE MODE

ENBL_B

I Note ·1
I

+Note *1
I

SEL, CA0-2

XIMFMmodeX /READY

RDATA_B LSTRB

) { /READY
n
IMFMmode

126

Fig.5.2-9 SET MOTOR CONTROL for Motor ON
rote., rote·1
ENBL_B

SEL, CA0-2 RDATA_B
LSTRB

*OTORONX /READY
) (/READY
n
/MOTOR ON

Note *1 : This signal can be controlled by the only ·set Enable Control" command.

Fig.5.2-10 EJECT

fNote ·1

f Note ·1

ENBL_B----.
x__ SEL, CA0-2_ _ _ IE_J_ec_r_ _ _ _ _ __

RDATA_B - - - - - - - - - - - - -
LSTRB ____.n._________
/EJECT

127

Chapter 6 Firmware Flowcharts
Under Apple mode, abstract firmware algorithms for each command are shown at the following pages. Under Standard modes, the abstract firmware algorithms are the same as that of the µPD765A.
129

CONFIGURE
CONFIGURE Receives parameters
- EFIFO - FIFOTHR -PRETRK
Command wait
DISABLE/ENABLE DPLL
Disable/Enable DPL Receives DR Receives DL
et/reset /DPLL signa Set INT
Command wait
EJECT DISK
EJECT DISK Receives DR Set EJECT signal
Set INT Command wait
131

FORMAT A TRACK (MFM Format)
FORMAT A TRAC Receives HD, DR Receives parameters

Preamble formatting ·SYNC · INDEX Address Mark
ID formatting -SYNC · ID address mark - ID ·CRC

Set NW

· Data address mark ·Data
N
y Write GAP4 : 1byte

Write GAP3

Abnormal termination
Set INT signal Send Result status
Command wait
133

READ ID (GCR Format)
READ ID Receives HD, DR Receives parameters
N
Abnormal termination Set AT
Set AT, FIN
Set INT signal end result statu Command wait
146

Flg.8 MFM FDD Control Timing

INDEX

v--scV

Fig. 9 Negative Reset

. . - - - tRST --~

RESET
ORO INT WGATE

,.._ .. _ _ _ tRC---~

164

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