Zynq UltraScale Device Packaging and Pinouts Product Specification User Guide
File info: application/pdf · 265 pages · 15.45MB
Zynq UltraScale Device Packaging and Pinouts Product Specification User Guide
Describes the packaging and pinout specifications for the Zynq® UltraScale ™ MPSoCs and Zynq UltraScale RFSoCs.
ZU, EG, EV, A53, R5, XA
Full PDF Document
If the inline viewer fails, it will open the original document in compatibility mode automatically. You can also open the file directly.
Extracted Text
Zynq UltraScale+ Device Packaging and Pinouts
Product Specification User Guide
UG1075 (v1.9) June 24, 2020
Revision History
The following table shows the revision history for this document.
Date
6/24/2020
7/12/2019
Version
1.9
1.8
Revision
Added the XCZU43DR, XCZU47DR, XCZU46DR, XCZU48DR, and XCZU49DR devices throughout document. Added the FFVH1760 and FSVH1760 packages throughout document. Chapter 2, PS Memory Interface Pin Guidelines: Updated the DDR3/3L Pinout Example for Supported Configurations, DDR4 Pin Rules, DDR4 Pinout Example for Supported Configurations, and LPDDR3 Pinout Example for Supported Configurations sections. Clarified the headings in Table 2-4 and updated the LPDDR3 64-bit column for PS_DDR_CKE0, PS_DDR_CKE1, PS_DDR_CS_N0, and PS_DDR_ODT0. Chapter 6, Package Marking: Added a new top-mark diagram (Figure 6-1). Chapter 8, Soldering Guidelines: Updated and removed notes linking to data sheets for reflow body temperatures. Chapter 10, Thermal Specifications: Added links to Package Thermal Data Query for thermal simulation data.
Added the XAZU7EV, XAZU11EG, XCZU39DR, XQZU3EG, XQZU9EG, XQZU11EG, XQZU19EG, XQZU21DR, XQZU28DR, and XQZU29DR devices throughout. Added the SFRA484, FFRD1156, FFRE1156, FFRB1517, FFRG1517, FFRC1760, and FFRF1760 packages where applicable. Updated the recommended applied pressure range on page 252.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
2
Send Feedback
Date
1/31/2019
Version
1.7
Revision
Chapter 1: Added an Important Note about XQ devices with eutectic BGA balls on page 12. Added the XQZU5EV (SFRC784, FFRB900), XQZU7EV (FFRB900, FFRC1156), and XQZU15EG (FFRC900, FFRB1156) device/package combinations to Table 1-1, Table 1-2, Table 1-3, Table 1-6, Table 1-7, and the associated bank diagram figures in this section. In Table 1-4, added the type and direction data for VCCO_PSIO[0:3]_ [500:503] and VCCO_PSDDR. Added a note for XQ ruggedized packages to VCCAUX_IO. Revised the GTH Quad 229 coordinates in Figure 1-15. Fixed GTH Quad location errors in Figure 1-21 through Figure 1-23. Chapter 2: Updated the DDR3/3L Pinout Example for Supported Configurations description and added VCCO_PSDDR and Note 1 to Table 2-1. Updated the DDR4 Pinout Example for Supported Configurations description and added VCCO_PSDDR to Table 2-2 and Note 1. Also in Table 2-2, added to guidelines for PS_DDR_A17, and PS_DDR_DQ32 to PS_DDR_DQ63. Updated the LPDDR4 Pinout Example for Supported Configurations description and added VCCO_PSDDR to Table 2-3 and Note 1. Updated the LPDDR3 Pinout Example for Supported Configurations description and added VCCO_PSDDR to Table 2-4 and Note 1. Chapter 3: Added an Important Note about XQ devices with eutectic BGA balls on page 114. Added the XQZU5EV (SFRC784, FFRB900), XQZU7EV (FFRB900, FFRC1156), and XQZU15EG (FFRC900, FFRB1156) device/package combinations to Table 3-1 labeled as production. Chapter 4: Added an Important Note about XQ devices with eutectic BGA balls on page 117. In Table 4-1, added the XQZU5EV (SFRC784, FFRB900), XQZU7EV (FFRB900, FFRC1156), and XQZU15EG (FFRC900, FFRB1156) device/package combinations. Chapter 5: Added an Important Note about XQ devices with eutectic BGA balls on page 195. In Table 5-1, added the XQZU5EV (SFRC784, FFRB900), XQZU7EV (FFRB900, FFRC1156), and XQZU15EG (FFRC900, FFRB1156) device/package combinations. Added Figure 5-4, Figure 5-9, Figure 5-12, and Figure 5-13. Chapter 6: Updated Table 6-1 and added Figure 6-3. Chapter 7: Added an Important Note about XQ devices with eutectic BGA balls on page 233. In Table 7-1, added the ruggedized packages (SFRC784, FFRB900, FFRC900, FFRB1156, and FFRC1156). Chapter 8: Updated the chapter with more information on eutectic packages including adding the Sn/Pb Reflow Soldering section. In Table 8-2, added the ruggedized packages (SFRC784, FFRB900, FFRC900, FFRB1156, and FFRC1156). Chapter 10: Added an Important Note about XQ devices with eutectic BGA balls on page 243. In Table 10-1, added the XQZU5EV (SFRC784, FFRB900), XQZU7EV (FFRB900, FFRC1156), and XQZU15EG (FFRC900, FFRB1156) device/package combinations.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
3
Send Feedback
Date
8/20/2018
4/10/2018
Version
1.6
1.5
Revision
Chapter 1: Added the XAZU4EV and XAZU5EV devices in the SFVC784 package. This includes updates to Table 1-2, Table 1-3, Table 1-5, Table 1-6, Table 1-7, Figure 1-6, and Figure 1-7. Corrected the VCCO_PSDDR pin name (from VCCO_PSDDR_504) in Table 1-4. Added a note to Figure 1-3 on page 45. Chapter 2: Clarified what a byte lane includes in the pin swapping restrictions discussions on page 91 and page 95. Chapter 3: Added the XAZU4EV and XAZU5EV devices to Table 3-1. Labeled all of the devices in Table 3-2 as production. Chapter 4: In Table 4-1, added the XAZU4EV and XAZU5EV devices and changed the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR device labels to production. Added a note above Figure 4-1 on page 121. Added the XAZU4EV and XAZU5EV devices in the SFVC784 package to Figure 4-9 and Figure 4-10. Chapter 5: Added the XAZU4EV and XAZU5EV devices to Table 5-1 and Figure 5-5. Labeled all of the devices in Table 5-2 as production. Chapter 10: Added the XAZU4EV and XAZU5EV devices to Table 10-1.
Chapter 1: Added the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR devices. This includes updates to Table 1-1, Table 1-2, Table 1-3, Table 1-4, Table 1-5, Table 1-6, and Table 1-7. Added Figure 1-30 through Figure 1-41. Chapter 3: Added the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR ASCII file links, see Table 3-2. Chapter 4: Added the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR devices to Table 4-1. Chapter 5: Added the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR mechanical drawings, see Table 5-2. Chapter 7: Added the FFVD1156, FFVE1156, FSVE1156, FFVG1517, FSVG1517, FFVF1760, and FSVF1760 packages to Table 7-1. Chapter 8: Revised the guidelines in Table 8-1 for Ramp-up rate, Peak temperature (lead/ball), and Peak temperature (body). Revised the same information in Figure 8-2. Added the FFVD1156, FFVE1156, FSVE1156, FFVG1517, FSVG1517, FFVF1760, and FSVF1760 packages to Table 8-2. Chapter 10: Added the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR devices to Table 10-1 and added Note 1. Chapter 11: Updated the System Level Heat Sink Solutions section and added the Heat Sink Removal and Measurement Debug sections.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
4
Send Feedback
Date
12/21/2017
8/29/2017
1/13/2017
Version
1.4
1.3
1.2
Revision
Added the XAZU2EG and XAZU3EG devices throughout the document. Chapter 1: Revise the VCCINT_VCU description in Table 1-4. Updated the ZU11EG (Figure 1-16 through Figure 1-20) PCIE4 bank coordinates. Chapter 2: Updated LPDDR4 Pin Swapping Restrictions and DDR4 Pin Swapping Restrictions and removed Figure 2-1: DDR Controller Implementation of DQ Mapping. In Table 2-2, updated the PS_DDR_ZQ connections. Chapter 5: Revised Figure 5-6: Symbol A from (2.57/2.77/2.97) to (2.48/2.68/2.88) and Symbol A2 from (1.27/1.42/1.62) to (1.18/1.33/1.48). Chapter 6: Revised the top mark diagram to show both older device versions and newer ones with a 2D bar code. Chapter 8: Added an Important note on page 234 about reflow rework. Chapter 10: Updated the SFVC784, FFVC900, FFVB1156, FFVC1156, FFVB1517, FFVF1517 data to account for the stamped lid in Table 10-1.
In Chapter 1, updated Figure 1-3, Figure 1-13, Figure 1-14, Figure 1-15, Figure 1-21, Figure 1-22, Figure 1-23, Figure 1-24, Figure 1-25, Figure 1-26, Figure 1-27, and Figure 1-28. Revise the VCCINT_VCU description in Table 1-4. In Chapter 2, updated the DDR4 Pin Rules and the DDR4 Pin Swapping Restrictions. In Table 2-2, updated the configurations for PS_DDR_CK_N1 (DDR4 1Rank). In Chapter 3, updated the package specification designation of many of the packages listed in Table 3-1. In Chapter 4, updated Table 4-1 and added the following device diagrams: SFVC784 Package�XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG, SFVC784 Package�XCZU4EV, XCZU5EV, XAZU4EV, and XAZU5EV, FBVB900 Package�XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG, FBVB900 Package�XCZU4EV and XCZU5EV, FFVF1517 Package�XCZU7CG and XCZU7EG, FFVC1156 Package�XCZU7EV, FFVC1156 Package�XCZU11EG, FFVB1517 Package�XCZU11EG, FFVF1517 Package�XCZU11EG, and FFVC1760 Package�XCZU11EG. In Chapter 5, replace Figure 5-5, added Figure 5-6, Figure 5-7, Figure 5-20, and Figure 5-29. In Table 8-2, update the FFV packages to a mass reflow of 245�C.
Added the following devices throughout: XCZU2CG, XCZU3CG, XCZU4CG, XCZU4EG, XCZU5CG, XCZU5EG, XCZU6CG, XCZU7CG, XCZU7EG, and XCZU9CG. In Table 1-3, revised the available PS I/O pin values for the SBVA484 and SFVA625 packages. In Table 1-4, updated the PS_MODE directions and the pin descriptions in the Power/Ground Pins section. In Table 1-6, revised the XCZU4 bank numbers and updated the FBVB900 mapping. Revised the mapping for the FBVB900 package in Table 1-7. Revised the Bank Locations of Dedicated and Multi-Function Pins section. Updated the HD I/O bank numbers in Figure 1-20. Added Chapter 2, PS Memory Interface Pin Guidelines. Added the Chapter 3, Package Specifications Designations section. In Table 3-1, updated links. Chapter 4, Device Diagrams and Chapter 5, Mechanical Drawings have updated tables and new diagrams. Revised the Bar Code section of Table 6-1 to include changes outlined in XCN16014: Top Marking change for 7 Series, UltraScale, and UltraScale+ Products. Updated the AUTOMOTIVE APPLICATIONS DISCLAIMER.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
5
Send Feedback
Date
6/14/2016
1/20/2016 12/18/2015 11/24/2015
Version
1.1
1.0.2 1.0.1 1.0
Revision
In Table 1-3, updated Note 1 and the SBVA484 package total user HP I/Os. Clarified the I2C_SCLK and I2C_SDA descriptions and added SMBALERT and VCCINT_VCU to Table 1-4. Also updated the Multi-gigabit Serial Transceiver Pins (GTHE4, GTYE4, and PS-GTR) descriptions, Added further descriptions in the Die Level Bank Numbering Overview including adding an example device diagram (Figure 1-1). In Chapter 4, added new figures and updated all of the graphics because the PERSTN pins and SMBALERT pins have moved. Updated Figure 5-12 and added Figure 5-14. Added the bar code description in Chapter 6. Replaced the missing graphics in Chapter 1. Updated the package file links in Chapter 3. Initial Xilinx release.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
6
Send Feedback
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Packaging Overview
Introduction to the UltraScale Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Zynq UltraScale+ Device Packaging and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Differences from Previous Generations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device/Package Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Gigabit Transceiver Channels by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 User I/O Pins by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Footprint Compatibility between Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Die Level Bank Numbering Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Chapter 2: PS Memory Interface Pin Guidelines
Introduction to PS Memory Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 DDR3/3L Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 DDR4 Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LPDDR4 Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 LPDDR3 Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Chapter 3: Package Files
About ASCII Package Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Package Specifications Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 ASCII Pinout Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Chapter 4: Device Diagrams
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SBVA484 Package�XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG . . . . . . . 121 SFVA625 Package�XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG . . . . . . . 123 SFVC784 Package�XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG . . . . . . . 125 SFVC784 Package�XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG . . . . . . . . . . . . . . . . . . . . . . . . . 127 SFVC784 Package�XCZU4EV, XCZU5EV, XAZU4EV, and XAZU5EV . . . . . . . . . . . . . . . . . . . . . . . . . 129 FBVB900 Package�XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG . . . . . . . . . . . . . . . . . . . . . . . . . 131
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
7
Send Feedback
FBVB900 Package�XCZU4EV and XCZU5EV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 FBVB900 Package�XCZU7CG and XCZU7EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 FBVB900 Package�XCZU7EV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 FFVC900 Package�XCZU6EG, XCZU9EG, and XCZU15EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 FFVB1156 Package�XCZU6EG, XCZU9EG, and XCZU15EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 FFVC1156 Package�XCZU7CG and XCZU7EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 FFVC1156 Package�XCZU7EV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 FFVC1156 Package�XCZU11EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 FFVD1156 Package�XCZU21DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 FFVE1156 and FSVE1156 Packages�XCZU25DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 FFVE1156 and FSVE1156 Packages�XCZU27DR and XCZU28DR . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 FFVE1156 and FSVE1156 Packages�XCZU43DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 FFVE1156 and FSVE1156 Packages�XCZU47DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 FFVE1156 and FSVE1156 Packages�XCZU48DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 FFVB1517 Package�XCZU11EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 FFVB1517 Package�XCZU17EG and XCZU19EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 FFVF1517 Package�XCZU7CG and XCZU7EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 FFVF1517 Package�XCZU7EV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 FFVF1517 Package�XCZU11EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 FFVG1517 and FSVG1517 Packages�XCZU25DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 FFVG1517 and FSVG1517 Packages�XCZU27DR and XCZU28DR . . . . . . . . . . . . . . . . . . . . . . . . . . 173 FFVG1517 and FSVG1517 Packages�XCZU43DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 FFVG1517 and FSVG1517 Packages�XCZU47DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 FFVG1517 and FSVG1517 Packages�XCZU48DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 FFVC1760 Package�XCZU11EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 FFVC1760 Package�XCZU17EG and XCZU19EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 FFVD1760 Package�XCZU17EG and XCZU19EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 FFVF1760 and FSVF1760 Packages�XCZU29DR and XCZU39DR . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 FFVF1760 and FSVF1760 Packages�XCZU49DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 FFVH1760 and FSVH1760 Packages�XCZU46DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 FFVE1924 Package�XCZU17EG and XCZU19EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Chapter 5: Mechanical Drawings
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 SBVA484 Flip-Chip, Fine-Pitch BGA (XCZU2, XCZU3, XAZU2EG, and XAZU3EG) . . . . . . . . . . . . . . 200 SFRA484 Flip-Chip, Fine-Pitch BGA (XQZU3EG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 SFVA625 Flip-Chip, Fine-Pitch BGA (XCZU2, XCZU3, XAZU2EG, and XAZU3EG). . . . . . . . . . . . . . . 202 SFRC784 Ruggedized Flip-Chip BGA (XQZU3EG and XQZU5EV) . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 SFVC784 Flip-Chip, Fine-Pitch BGA (XCZU2, XAZU2EG, XCZU3, XAZU3EG, XCZU4, XAZU4EV, XCZU5,
and XAZU5EV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
8
Send Feedback
FBVB900 Flip-Chip, Fine-Pitch BGA (XCZU4CG, XCZU4EG, XCZU4EV, XCZU5CG, XCZU5EG, and XCZU5EV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
FBVB900 Flip-Chip, Fine-Pitch BGA (XCZU7CG, XCZU7EG, XCZU7EV, and XAZU7EV) . . . . . . . . . . 206 FFRB900 (XQZU7EV) Ruggedized Flip-Chip BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 FFRB900 (XQZU5EV) and FFRC900 (XQZU9EG and XQZU15EG) Ruggedized Flip-Chip BGA . . . . . 208 FFVC900 Flip-Chip, Fine-Pitch BGA (XCZU6CG, XCZU6EG, XCZU9CG, XCZU9EG, and XCZU15EG). 209 FFRB1156 Ruggedized Flip-Chip BGA (XQZU9EG and XQZU15EG) . . . . . . . . . . . . . . . . . . . . . . . . . 210 FFVB1156 Flip-Chip, Fine-Pitch BGA (XCZU6CG, XCZU6EG, XCZU9CG, XCZU9EG, and XCZU15EG) 211 FFRC1156 Ruggedized Flip-Chip BGA (XQZU7EV and XQZU11EG) . . . . . . . . . . . . . . . . . . . . . . . . . 212 FFVC1156 Flip-Chip, Fine-Pitch BGA
(XCZU7CG, XCZU7EG, XCZU7EV, and XCZU11EG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 FFRD1156 (XQZU21DR) Ruggedized Flip-Chip BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 FFRE1156 (XQZU28DR) Ruggedized Flip-Chip BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 FFVD1156 (XCZU21DR) and FFVE1156
(XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 FSVE1156 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 FFRB1517 (XQZU19EG) Ruggedized Flip-Chip BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 FFVB1517 (XCZU11EG, XCZU17EG, and XCZU19EG) and FFVF1517 (XCZU7CG, XCZU7EG, XCZU7EV, XCZU11EG, and XAZU11EG) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 FFRG1517 (XQZU28DR) Ruggedized Flip-Chip BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 FFVG1517 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 FSVG1517 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 FFVC1760 and FFVD1760 Flip-Chip, Fine-Pitch BGA (XCZU11EG, XCZU17EG, and XCZU19EG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 FFRC1760 Ruggedized Flip-Chip BGA (XQZU11EG and XQZU19EG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 FFVF1760 (XCZU29DR, XCZU39DR, XCZU49DR) and FFVH1760 (XCZU46DR) Flip-Chip, Fine-Pitch BGA 225 FFRF1760 (XQZU29DR) Ruggedized Flip-Chip BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 FSVF1760 (XCZU29DR, XCZU39DR, XCZU49DR) and FSVH1760 (XCZU46DR) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 FFVE1924 Flip-Chip, Fine-Pitch BGA (XCZU17EG, and XCZU19EG) . . . . . . . . . . . . . . . . . . . . . . . . . 228
Chapter 6: Package Marking
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Chapter 7: Packing and Shipping
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
9
Send Feedback
Chapter 8: Soldering Guidelines
Soldering Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Chapter 9: Recommended PCB Design Rules for BGA Packages
BGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Chapter 10: Thermal Specifications
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Thermal Resistance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Support for Thermal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Chapter 11: Thermal Management Strategy
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Thermal Interface Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Heat Sink Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Measurement Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Chapter 12: Heat Sink Guidelines for Bare-die Flip-Chip Packages
Heat Sink Attachments for Bare-die FB Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Types of Heat Sink Attachments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Appendix A: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
10
Send Feedback
Chapter 1
Packaging Overview
Introduction to the UltraScale Architecture
The Xilinx� UltraScaleTM architecture is the first ASIC-class architecture to enable multi-hundred gigabit-per-second levels of system performance with smart processing, while efficiently routing and processing data on-chip. UltraScale architecture-based devices address a vast spectrum of high-bandwidth, high-utilization system requirements by using industry-leading technical innovations, including next-generation routing, ASIC-like clocking, 3D-on-3D ICs, multiprocessor SoC (MPSoC) technologies, and new power reduction features. The devices share many building blocks, providing scalability across process nodes and product families to leverage system-level investment across platforms.
Virtex� UltraScale+TM devices provide the highest performance and integration capabilities in a FinFET node, including both the highest serial I/O and signal processing bandwidth, as well as the highest on-chip memory density. As the industry's most capable FPGA family, the Virtex UltraScale+ devices are ideal for applications including 1+Tb/s networking and data center and fully integrated radar/early-warning systems.
Virtex UltraScale devices provide the greatest performance and integration at 20 nm, including serial I/O bandwidth and logic capacity. As the industry's only high-end FPGA at the 20 nm process node, this family is ideal for applications including 400G networking, large scale ASIC prototyping, and emulation.
Kintex� UltraScale+ devices provide the best price/performance/watt balance in a FinFET node, delivering the most cost-effective solution for high-end capabilities, including transceiver and memory interface line rates as well as 100G connectivity cores. Our newest mid-range family is ideal for both packet processing and DSP-intensive functions and is well suited for applications including wireless MIMO technology, Nx100G networking, and data center.
Kintex UltraScale devices provide the best price/performance/watt at 20 nm and include the highest signal processing bandwidth in a mid-range device, next-generation transceivers, and low-cost packaging for an optimum blend of capability and cost-effectiveness. The family is ideal for packet processing in 100G networking and data centers applications as well as DSP-intensive processing needed in next-generation medical imaging, 8k4k video, and heterogeneous wireless infrastructure.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
11
Send Feedback
Chapter 1: Packaging Overview
Zynq� UltraScale+ devices provide 64-bit processor scalability while combining real-time control with soft and hard engines for graphics, video, waveform, and packet processing. Integrating an Arm�-based system for advanced analytics and on-chip programmable logic for task acceleration creates unlimited possibilities for applications including 5G Wireless, next generation ADAS, and Industrial Internet-of-Things.
This user guide is part of the Zynq UltraScale+ MPSoC documentation suite.
Zynq UltraScale+ Device Packaging and Pinouts
This section describes the packages and pinouts for the in various organic flip-chip 0.8 mm and 1.0 mm pitch BGA packages.
IMPORTANT: All standard packages are lead-free (signified by an additional V in the package name). All devices supported in a particular package are footprint compatible. Each device is split into I/O banks to allow for flexibility in the choice of I/O standards. See the UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 6].
The flip-chip assembly materials for the Zynq UltraScale+ devices are manufactured using ultra-low alpha (ULA) materials defined as <0.002 cph/cm2 or materials that emit less than 0.002 alpha-particles per square centimeter per hour.
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q.
Differences from Previous Generations
The packaging and pinout specifications for Zynq UltraScale+ devices differ from past generations, including the Zynq-7000 SoCs. These details are outlined in this section.
� All package and die components, including flip-chip solder bumps, are lead-free. � Package names contain a single-character alphabetic designator followed by the exact
number of pins found on the package. � VCCAUX_IO pins are not divided into bank groups. VCCAUX_IO must be connected to
VCCAUX at the board level. � Internal logic is separated from I/O logic by the addition of the VCCINT_IO power pins.
VCCINT_IO must be connected to VCCBRAM (depending on the device speed grade and voltage settings) at the board level.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
12
Send Feedback
Chapter 1: Packaging Overview
� Groups of gigabit serial transceiver (GT) power pins are separated by column for each column of GT Quads.
� Standard HP I/O banks each have a total of 52 SelectIOTM pins, optionally configurable as (up to) 24 differential pairs.
� Standard HD I/O banks each have a total of 24 SelectIO pins, optionally configurable as (up to) 12 differential pairs.
� Each bank has one dedicated VREF pin. These pins cannot be used as user I/Os.
� Four differential clock pin pairs per bank consist of a single type of global clock (GC or HDGC) input.
� Four memory byte groups per HP I/O bank are each separated into an upper and a lower memory byte group.
� Multiple PL configuration pins are removed.
� A POR_OVERRIDE pin is used to override the default power-on-reset delay. See Table 1-4.
Device/Package Combinations
Table 1-1 shows the size and BGA pitch of the Zynq UltraScale+ device packages. All packages are available with eutectic BGA balls. For these packages, the Pb-free signifier in the package name is a Q.
Table 1-1: Package Specifications
Packages
Description
SBVA484 SFRA484 SFVA625 SFVC784 SFRC784 FBVB900 FFRB900 FFVC900 FFRC900
Flip-chip, bare-die Ruggedized flip-chip, bare-die Flip-chip Flip-chip Ruggedized flip-chip Flip-chip, bare-die Ruggedized flip-chip Flip-chip Ruggedized flip-chip
Package Specifications
Package Type Pitch (mm) Size (mm)
19 x 19
19 x 19
0.8
21 x 21
23 x 23 BGA
1.0
31 x 31
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
13
Send Feedback
Table 1-1: Package Specifications (Cont'd)
Packages
Description
FFVB1156 FFRB1156 FFVC1156 FFRC1156 FFVD1156 FFRD1156 FFVE1156 FFRE1156 FFVB1517 FFRB1517 FFVF1517 FFVG1517 FFRG1517 FFVC1760 FFRC1760 FFVD1760 FFVF1760 FFVH1760 FFRF1760 FFVE1924 FSVE1156 FSVG1517 FSVF1760 FSVH1760
Flip-chip Ruggedized flip-chip Flip-chip Ruggedized flip-chip Flip-chip Ruggedized flip-chip Flip-chip Ruggedized flip-chip Flip-chip Ruggedized flip-chip Flip-chip Flip-chip Ruggedized flip-chip Flip-chip Ruggedized flip-chip Flip-chip Flip-chip Flip-chip Ruggedized flip-chip Flip-chip
Flip-chip, lidless with stiffener ring
Chapter 1: Packaging Overview Package Specifications Package Type Pitch (mm) Size (mm)
35 x 35
40 x 40
BGA
1.0
42.5 x 42.5
45 x 45 35 x 35 40 x 40 42.5 x 42.5
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
14
Send Feedback
Chapter 1: Packaging Overview
Gigabit Transceiver Channels by Device/Package
Table 1-2 lists the quantity of gigabit transceiver channels for the Zynq UltraScale+ devices. In all devices, a PS-GTR, GTH, or GTY channel is one set of MGTRXP, MGTRXN, MGTTXP, and MGTTXN pins. All packages are available with eutectic BGA balls. For these packages, the device type is XQ and the Pb-free signifier in the package name is a Q.
Table 1-2: Serial Transceiver Channels (PS-GTR, GTH, and GTY) by Device/Package
Device
XCZU2CG
Package
PS-GTR Channels
4
GTH Channels
0
GTY Channels
0
XCZU2EG
4
0
0
XCZU3CG
4
0
0
SBVA484
XCZU3EG
4
0
0
XAZU2EG
4
0
0
XAZU3EG
4
0
0
XQZU3EG
SFRA484
4
0
0
XCZU2CG
4
0
0
XCZU2EG
4
0
0
XCZU3CG
4
0
0
SFVA625
XCZU3EG
4
0
0
XAZU2EG
4
0
0
XAZU3EG
4
0
0
XCZU2CG
4
0
0
XCZU2EG
4
0
0
XCZU3CG
4
0
0
XCZU3EG
4
0
0
XCZU4CG
4
4
0
XCZU4EG
4
4
0
XCZU4EV
4
4
0
SFVC784
XCZU5CG
4
4
0
XCZU5EG
4
4
0
XCZU5EV
4
4
0
XAZU2EG
4
0
0
XAZU3EG
4
0
0
XAZU4EV
4
4
0
XAZU5EV
4
4
0
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
15
Send Feedback
Chapter 1: Packaging Overview
Table 1-2: Serial Transceiver Channels (PS-GTR, GTH, and GTY) by Device/Package (Cont'd)
Device
XQZU21DR XQZU5EV
Package
SFRC784
PS-GTR Channels
4 4
GTH Channels
0 4
GTY Channels
0 0
XCZU4CG
4
16
0
XCZU4EG
4
16
0
XCZU4EV
4
16
0
XCZU5CG XCZU5EG XCZU5EV XCZU7CG XCZU7EG
FBVB900
4
16
0
4
16
0
4
16
0
4
16
0
4
16
0
XCZU7EV
4
16
0
XAZU7EV
4
16
0
XQZU5EV XQZU7EV
FFRB900
4
16
0
4
16
0
XCZU6CG
4
16
0
XCZU6EG
4
16
0
XCZU9CG
FFVC900
4
16
0
XCZU9EG
4
16
0
XCZU15EG XQZU9EG XQZU15EG XCZU6CG XCZU6EG
FFRC900
4
16
0
4
16
0
4
16
0
4
24
0
4
24
0
XCZU9CG
FFVB1156
4
24
0
XCZU9EG
4
24
0
XCZU15EG
4
24
0
XQZU9EG
4
24
0
FFRB1156
XQZU15EG
4
24
0
XCZU7CG
4
20
0
XCZU7EG
4
20
0
FFVC1156
XCZU7EV
4
20
0
XCZU11EG
4
XQZU7EV
4
FFRC1156
XQZU11EG
4
XCZU21DR
FFVD1156
4
20
0
20
0
20
0
0
16
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
16
Send Feedback
Chapter 1: Packaging Overview
Table 1-2: Serial Transceiver Channels (PS-GTR, GTH, and GTY) by Device/Package (Cont'd)
Device
XQZU21DR
Package
FFRD1156
PS-GTR Channels
4
GTH Channels
0
GTY Channels
16
XCZU25DR
4
0
8
XCZU27DR
4
0
8
XCZU28DR
4
FFVE1156
XCZU43DR
4
0
8
0
8
XCZU47DR
4
XCZU48DR
4
XQZU28DR
FFRE1156
4
XCZU25DR
4
XCZU27DR
4
0
8
0
8
0
8
0
8
0
8
XCZU28DR
4
FSVE1156
XCZU43DR
4
0
8
0
8
XCZU47DR
4
0
8
XCZU48DR
4
0
8
XCZU11EG
4
16
0
XCZU17EG
FFVB1517
4
16
0
XCZU19EG
4
16
0
XQZU19EG
FFRB1517
4
16
0
XCZU7CG
4
24
0
XCZU7EG
4
24
0
XCZU7EV
FFVF1517
4
24
0
XCZU11EG
4
32
0
XAZU11EG
4
32
0
XCZU25DR
4
0
8
XCZU27DR
4
0
16
XCZU28DR
4
FFVG1517
XCZU43DR
4
0
16
0
16
XCZU47DR
4
0
16
XCZU48DR
4
0
16
XQZU28DR
FFRG1517
4
0
16
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
17
Send Feedback
Chapter 1: Packaging Overview
Table 1-2: Serial Transceiver Channels (PS-GTR, GTH, and GTY) by Device/Package (Cont'd)
Device
XCZU25DR
Package
PS-GTR Channels
4
GTH Channels
0
GTY Channels
8
XCZU27DR
4
0
16
XCZU28DR
4
FSVG1517
XCZU43DR
4
0
16
0
16
XCZU47DR
4
0
16
XCZU48DR
4
0
16
XCZU11EG
4
32
16
XCZU17EG
FFVC1760
4
32
16
XCZU19EG
4
32
16
XQZU11EG
4
32
16
FFRC1760
XQZU19EG
4
32
16
XCZU17EG
4
FFVD1760
XCZU19EG
4
44
28
44
28
XCZU29DR
4
0
16
XCZU39DR
FFVF1760
4
0
16
XCZU49DR
4
0
16
XCZU46DR
FFVH1760
4
0
16
XQZU29DR
FFRF1760
4
0
16
XCZU29DR
4
XCZU39DR
FSVF1760
4
XCZU49DR
4
XCZU46DR
FSVH1760
4
XCZU17EG
4
FFVE1924
XCZU19EG
4
0
16
0
16
0
16
0
16
44
0
44
0
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
18
Send Feedback
Chapter 1: Packaging Overview
User I/O Pins by Device/Package
Table 1-3 lists the number of available PS I/Os, 3.3V-capable high-density (HD), and 1.8V-capable high-performance (HP) I/Os and the number of HD or HP differential I/O for each device/package combination. All packages are available with eutectic BGA balls. For these packages, the device type is XQ and the Pb-free signifier in the package name is a Q.
Table 1-3: Available I/O Pins by Device/Package
Device
XCZU2CG XCZU2EG XCZU3CG XCZU3EG XAZU2EG XAZU3EG XQZU3EG XCZU2CG XCZU2EG XCZU3CG XCZU3EG XAZU2EG XAZU3EG XCZU2CG XCZU2EG
Package
SBVA484 SFRA484 SFVA625
PS I/Os
170 170 170 170 170 170 170 170 170 170 170 170 170 214 214
Total User I/O
HD(1)
HP(1)
24
58
24
58
24
58
24
58
24
58
24
58
24
58
24
156
24
156
24
156
24
156
24
156
24
156
96
156
96
156
XCZU3CG
214
96
156
XCZU3EG
214
96
156
XCZU4CG
214
96
156
XCZU4EG
214
96
156
XCZU4EV
214
96
156
SFVC784
XCZU5CG
214
96
156
XCZU5EG
214
96
156
XCZU5EV XAZU2EG XAZU3EG XAZU4EV XAZU5EV
214
96
156
214
96
156
214
96
156
214
96
156
214
96
156
Differential I/O
HD
HP
24
52
24
52
24
52
24
52
24
52
24
52
24
52
24
144
24
144
24
144
24
144
24
144
24
144
96
144
96
144
96
144
96
144
96
144
96
144
96
144
96
144
96
144
96
144
96
144
96
144
96
144
96
144
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
19
Send Feedback
Chapter 1: Packaging Overview
Table 1-3: Available I/O Pins by Device/Package (Cont'd)
Device
XQZU3EG XQZU5EV
Package
SFRC784
PS I/Os
214 214
Total User I/O
HD(1)
HP(1)
96
156
96
156
XCZU4CG
214
48
156
XCZU4EG
214
48
156
XCZU4EV
214
48
156
XCZU5CG
214
48
156
XCZU5EG
214
48
156
FBVB900
XCZU5EV
214
48
156
XCZU7CG
214
48
156
XCZU7EG
214
48
156
XCZU7EV
214
48
156
XAZU7EV
214
48
156
XQZU5EV
214
48
156
FFRB900
XQZU7EV
214
48
156
XCZU6CG
214
48
156
XCZU6EG
214
48
156
XCZU9CG
FFVC900
214
48
156
XCZU9EG
214
48
156
XCZU15EG
214
48
156
XQZU9EG
214
48
156
FFRC900
XQZU15EG
214
48
156
XCZU6CG
214
120
208
XCZU6EG
214
120
208
XCZU9CG
FFVB1156
214
120
208
XCZU9EG
214
120
208
XCZU15EG
214
120
208
XQZU9EG
214
120
208
FFRB1156
XQZU15EG
214
120
208
XCZU7CG
214
48
312
XCZU7EG
214
48
312
FFVC1156
XCZU7EV
214
48
312
XCZU11EG
214
48
312
XQZU7EV
214
48
312
FFRC1156
XQZU11EG
214
48
312
Differential I/O
HD
HP
96
144
96
114
48
144
48
144
48
144
48
144
48
144
48
144
48
144
48
144
48
144
48
144
48
144
48
144
48
144
48
144
48
144
48
144
48
144
48
144
48
144
120
192
120
192
120
192
120
192
120
192
120
192
120
192
48
288
48
288
48
288
48
288
48
288
48
288
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
20
Send Feedback
Chapter 1: Packaging Overview
Table 1-3: Available I/O Pins by Device/Package (Cont'd)
Device
XCZU21DR
Package
FFVD1156
PS I/Os
214
Total User I/O
HD(1)
HP(1)
72
208
XQZU21DR
FFRD1156
214
72
208
XCZU25DR
214
48
104
XCZU27DR
214
48
104
XCZU28DR
214
48
104
FFVE1156
XCZU43DR
214
48
104
XCZU47DR
214
48
104
XCZU48DR
214
48
104
XQZU28DR
FFRE1156
214
48
104
XCZU25DR
214
48
104
XCZU27DR
214
48
104
XCZU28DR
214
48
104
FSVE1156
XCZU43DR
214
48
104
XCZU47DR
214
48
104
XCZU48DR
214
48
104
XCZU11EG
214
72
416
XCZU17EG
FFVB1517
214
72
572
XCZU19EG
214
72
572
XQZU19EG
FFRB1517
214
72
572
XCZU7CG
214
48
416
XCZU7EG
214
48
416
XCZU7EV
FFVF1517
214
48
416
XCZU11EG
214
48
416
XAZU11EG
214
48
416
XCZU25DR
214
48
299
XCZU27DR
214
48
299
XCZU28DR
214
48
299
FFVG1517
XCZU43DR
214
48
299
XCZU47DR
214
48
299
XCZU48DR
214
48
299
XQZU28DR
FFRG1517
214
48
299
Differential I/O
HD
HP
72
192
72
192
48
96
48
96
48
96
48
96
48
96
48
96
48
96
48
96
48
96
48
96
48
96
48
96
48
96
72
384
72
528
72
528
72
528
48
384
48
384
48
384
48
384
48
384
48
276
48
276
48
276
48
276
48
276
48
276
48
276
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
21
Send Feedback
Chapter 1: Packaging Overview
Table 1-3: Available I/O Pins by Device/Package (Cont'd)
Device
XCZU25DR XCZU27DR XCZU28DR XCZU43DR XCZU47DR XCZU48DR XCZU11EG XCZU17EG XCZU19EG XQZU11EG XQZU19EG XCZU17EG XCZU19EG XCZU29DR XCZU39DR XCZU49DR XCZU46DR XQZU29DR XCZU29DR XCZU39DR XCZU46DR XCZU17EG XCZU19EG
Package
FSVG1517
FFVC1760 FFRC1760 FFVD1760 FFVF1760 FFVH1760 FFRF1760 FSVF1760 FSVH1760 FFVE1924
PS I/Os
214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214
Total User I/O
HD(1)
HP(1)
48
299
48
299
48
299
48
299
48
299
48
299
96
416
96
416
96
416
96
416
96
416
48
260
48
260
96
312
96
312
96
312
48
312
96
312
96
312
96
312
48
312
96
572
96
572
Differential I/O
HD
HP
48
276
48
276
48
276
48
276
48
276
48
276
96
384
96
384
96
384
96
384
96
384
48
240
48
240
96
288
96
288
96
288
48
288
96
288
96
288
96
288
48
288
96
528
96
528
Notes: 1. The maximum user I/O numbers do not include the GT serial transceiver pins or the PUDC_B and POR_OVERRIDE
pins used for configuration.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
22
Send Feedback
Chapter 1: Packaging Overview
Pin Definitions
Table 1-4 lists the pin definitions.
Table 1-4: Pin Definitions
Pin Name
Type
Direction
Description
User I/O Pins
IO_L[1 to 24][P or N]_T[0 to 3] [U or L]_N[0 to 12]_ [multi-function]_[bank number] or IO_T[0 to 3][U or L]_N[0 to 12]_[multi-function]_[bank number]
Most user I/O pins are capable of differential signaling and can be implemented as pairs. Each user I/O pin name consists of several indicator labels, where:
Dedicated
Input/ Output
� IO indicates a user I/O pin. � L[1 to 24] indicates a unique differential pair with
P (positive) and N (negative) sides. User I/O pins without the L indicator are single-ended. � T[0 to 3][U or L] indicates the assigned byte group and nibble location (upper or lower portion) within that group for the pin.
� N[0 to 12] the number of the I/O within its byte group.
� [multi-function] indicates any other functions that the pin can provide. If not used for this function, the pin can be a user I/O.
� [bank number] indicates the assigned bank for the user I/O pin.
User I/O Multi-Function Pins
GC or HDGC
Multifunction
VRP(1)
Multifunction
Input N/A
Four global clock (GC or HDGC) pin pairs are in each bank. HDGC pins have direct access to the global clock buffers. GC pins have direct access to the global clock buffers and the MMCMs and PLLs that are in the clock management tile (CMT) adjacent to the same I/O bank. GC and HDGC inputs provide dedicated, high-speed access to the internal global and regional clock resources. GC and HDGC inputs use dedicated routing and must be used for clock inputs where the timing of various clocking features is imperative. Up-to-date information about designing with the GC (or HDGC) pin is available in the UltraScale Architecture Clocking Resources User Guide (UG572) [Ref 7] This pin is for the DCI voltage reference resistor of P transistor (per bank, to be pulled Low with a reference resistor).
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
23
Send Feedback
Chapter 1: Packaging Overview
Table 1-4: Pin Definitions (Cont'd)
Pin Name
DBC QBC PERSTN[0 to 1]
Type
Multifunction
Multifunction
Direction
Input Input
Description
Byte lane clock (DBC and QBC) input pin pairs are clock inputs directly driving source synchronous clocks to the bit slices in the I/O banks. In memory applications, these are also known as DQS. For more information, consult the UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 6]. Default reset pin locations for the integrated block for PCI Express.
Configuration Pins
For more information on configuration and recommended external pull-up/pull-down resistors, see the Zynq UltraScale+ Device Technical Reference Manual (UG1085) [Ref 10] and the UltraScale Architecture PCB and Pin Planning User Guide (UG583) [Ref 14].
PUDC_B
Dedicated
Input
Active-Low input enables internal pull-ups during configuration on all SelectIO pins: 0 = Weak preconfiguration I/O pull-up resistors enabled. 1 = Weak preconfiguration I/O pull-up resistors disabled. PUDC_B is powered by VCCAUX. Power-on reset delay override.
POR_OVERRIDE
Dedicated
Input
0 = Standard PL power-on delay time (recommended default). 1 = Faster PL power-on delay time.
CAUTION! Do not allow this pin to float before and during configuration. This pin must be tied to VCCINT or GND.
PS_DONE
PS_ERROR_OUT PS_ERROR_STATUS
PS_INIT_B
PS_JTAG_TCK PS_JTAG_TDI PS_JTAG_TDO PS_JTAG_TMS PS_MODE PS_PADI PS_PADO
Dedicated
Dedicated Dedicated
Dedicated
Dedicated Dedicated Dedicated Dedicated Dedicated Dedicated Dedicated
Output
PS DONE signal. Requires an external pull-up resistor.
Output PS error indication.
Output PS error status.
Initialization completion indicator after POR. High Input/Output voltage indicates completion of initialization (PL).
Requires an external pull-up resistor.
Input
JTAG data clock.
Input
JTAG data input.
Output JTAG data output.
Input
JTAG mode select.
Input/Output PS MIO mode selection pins.
Input
Crystal pad input. Real-time clock (RTC).
Output Crystal pad output. Real-time clock (RTC).
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
24
Send Feedback
Chapter 1: Packaging Overview
Table 1-4: Pin Definitions (Cont'd)
Pin Name
PS_POR_B
PS_PROG_B PS_REF_CLK PS_SRST_B
Type
Dedicated
Dedicated Dedicated Dedicated
Direction
Input
Input Input Input
Description
Power on reset. PS_POR_B must be held at 0 until all PS power supplies meet voltage requirements and the PS_CLK reference is within specification. When deasserted the PS begins the boot process. PROG_B signal to reset configuration block. Requires an external pull-up resistor. System reference clock. PS_CLK must be between 27 MHz and 60 MHz. System reset. For use when debugging. When 0, forces the PS to enter the system reset sequence.
Power/Ground Pins
For more information on voltage specifications see the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics [Ref 8] or the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics [Ref 9].
GND
Dedicated
N/A
Ground.
RSVDGND
Dedicated
N/A
Reserved pins that must be tied to GND.
Note: These pins are labeled differently depending upon
the device. They can serve a different purpose between footprint compatible devices. To migrate to a footprint compatible device, account for any variation in pin functionality.
RSVD
Dedicated
N/A
Reserved pin. Leave floating.
VCCINT
Dedicated
N/A
Power-supply pins for the PL internal logic.
VCCINT_IO
Dedicated
N/A
Power-supply pins for the I/O banks. VCCINT_IO must be connected to VCCBRAM on the board.
Power-supply pins for the video codec unit (EV devices only).
Note: If the video codec unit is not used, then connect the VCCINT_VCU pins to GND to reduce power. In the CG and EG devices, the EV device VCCINT_VCU pins appear as RSVDGND pins.
VCCINT_VCU
Dedicated
Note: When migrating from an EV device to a CG or EG
device in the same package, Xilinx recommends
connecting the VCCINT_VCU pins to GND to reduce
N/A
power. Further VCCINT_VCU migration guidelines are
available in UltraScale Architecture PCB and Pin
Planning User Guide (UG583) [Ref 14].
VCCAUX
Dedicated
IMPORTANT: VCCINT_VCU requires its own dedicated power supply. Do not combine with other power rails on the PCB.
N/A
Power-supply pins for auxiliary circuits.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
25
Send Feedback
Chapter 1: Packaging Overview
Table 1-4: Pin Definitions (Cont'd)
Pin Name
Type
Direction
Description
Auxiliary power-supply pins for the I/O banks. VCCAUX_IO must be connected to VCCAUX on the board.
VCCAUX_IO
Dedicated
VCCBRAM VCCO_[bank number](2) VREF_[bank number] VCCADC GNDADC VCC_PSADC GND_PSADC VCC_PSAUX
VCC_PSBATT
VCC_PSDDR_PLL
VCC_PSPLL
VCC_PSINTFP VCC_PSINTFP_DDR VCC_PSINTLP VCCO_PSIO[0:3]_ [500:503] VCCO_PSDDR
Dedicated Dedicated Dedicated Dedicated Dedicated Dedicated Dedicated Dedicated
Dedicated
Dedicated
Dedicated
Dedicated Dedicated Dedicated
Dedicated
Dedicated
N/A
Note: Package files for XQ ruggedized devices
(for example: FFRC784) have unique pin names
for VCCAUX_HPIO and VCCAUX_HDIO. These pins
can be connected to a common VCCAUX_IO
supply.
N/A
Power-supply pins for PL block RAM logic.
N/A
Power-supply pins for the output drivers (per bank).
N/A
Voltage reference for input pins (per bank).
N/A
System Monitor analog supply voltage.
N/A
System Monitor analog ground.
N/A
PS ADC supply voltage.
N/A
PS ADC analog ground.
N/A
PS auxiliary circuits supply voltage.
N/A
PS RTC battery supply voltage. When not used, tie to GND.
N/A
PS DDR PLL supply voltage.
N/A
PS PLL (DPLL, RPLL, APLL, VPLL, IOPLL) supply voltage.
N/A
PS full-power domain supply voltage.
N/A
PS DDR full-power domain supply voltage.
N/A
PS low-power domain supply voltage.
N/A
PS I/O supply voltage.
N/A
PS DDR controller I/O supply voltage.
PS MIO Pins
PS_MIO
Multi-function
Input/Output
Multiplexed I/O can be configured to support multiple I/O interfaces. These interfaces include SPI and Quad-SPI flash, NAND, USB, Ethernet, SDIO, UART, SPI, and GPIO interfaces.
PS DDR Pins
PS_DDR_DQ PS_DDR_DQS_P PS_DDR_DQS_N PS_DDR_ALERT_N PS_DDR_ACT_N
Dedicated Dedicated Dedicated Dedicated Dedicated
Input/Output DRAM data.
Input/Output DRAM differential data strobe positive.
Input/Output DRAM differential data strobe negative.
Input
DRAM alert signal.
Output DRAM activation command.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
26
Send Feedback
Chapter 1: Packaging Overview
Table 1-4: Pin Definitions (Cont'd)
Pin Name
PS_DDR_A PS_DDR_BA PS_DDR_BG PS_DDR_CK_N PS_DDR_CK PS_DDR_CKE PS_DDR_CS PS_DDR_DM PS_DDR_ODT PS_DDR_PARITY PS_DDR_RAM_RST_N PS_DDR_ZQ
Type
Dedicated Dedicated Dedicated Dedicated Dedicated Dedicated Dedicated Dedicated Dedicated Dedicated Dedicated Dedicated
System Monitor Pins(3)
AD[0 to 15][P or N]
Multifunction
VREFP
Dedicated
VREFN
Dedicated
VP
Dedicated
VN
Dedicated
I2C_SCLK
Multifunction
Direction
Description
Output DRAM row and column address.
Output DRAM bank address.
Output DRAM bank group.
Output DRAM differential clock negative.
Output DRAM differential clock positive.
Output DRAM clock enable.
Output DRAM chip select.
Output DRAM data mask.
Output DRAM termination control.
Output DRAM parity signal
Output DRAM reset signal, active low.
Input/Output ZQ calibration signal.
Input N/A N/A Input
Input
System Monitor differential auxiliary analog inputs 0�15. Voltage reference input. Voltage reference GND. System Monitor dedicated differential analog input (positive side). System Monitor dedicated differential analog input (negative side). I2C serial clock. Directly connected to the System Monitor DRP interface for I2C operation configuration.
Bidirectional
IMPORTANT: Because the SYSMON I2C interface is active after power-on, this pin should only be used for I2C access until after configuration.
I2C_SDA
Multifunction
I2C serial data line. Directly connected to the System Monitor DRP interface for I2C operation configuration.
Bidirectional
IMPORTANT: Because the SYSMON I2C interface is active after power-on, this pin should only be used for I2C access until after configuration.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
27
Send Feedback
Chapter 1: Packaging Overview
Table 1-4: Pin Definitions (Cont'd)
Pin Name
Type
Direction
Description
Optional PMBus alert, interrupt signal. When Low, indicates a system fault that must be cleared using PMBus commands. Connect to SMBALERT_TS. For more information, see the UltraScale Architecture System Monitor User Guide [Ref 13].
SMBALERT
Multifunction
Bidirectional
IMPORTANT: By default, the PMBus is active prior to configuration. Only use as a multi-functional I/O pin in designs that can tolerated this pin being driven prior to configuration.
This pin is present on Kintex UltraScale+ and Virtex UltraScale+ devices.
Multi-gigabit Serial Transceiver Pins (GTHE4, GTYE4, and PS-GTR)
For more information on the GTH and GTY transceivers, see the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 11] or UltraScale Architecture GTY Transceivers User Guide [Ref 12]. For more information on the PS-GTR transceivers, see the Zynq UltraScale+ Device Technical Reference Manual [Ref 10].
MGTHRX[P or N][0 to 3] _[GT quad number]
Dedicated
Input
RXP and RXN are the differential input pairs for each of the receivers in the GTH Quad.
MGTHTX[P or N][0 to 3] _[GT quad number]
Dedicated
Output
TXP and TXN are the differential output pairs for each of the transmitters in the GTH Quad.
MGTYRX[P or N][0 to 3] _[GT quad number]
Dedicated
Input
RXP and RXN are the differential input pairs for each of the receivers in the GTY Quad.
MGTYTX[P or N][0 to 3] _[GT quad number]
Dedicated
Output
TXP and TXN are the differential output pairs for each of the transmitters in the GTY Quad.
PS_MGTRRX[P or N][0 to 3] _[GT quad number]
Dedicated
Input
RXP and RXN are the differential input pairs for each of the receivers in the PS-GTR Quad.
PS_MGTRTX[P or N][0 to 3] _[GT quad number]
Dedicated
Output
TXP and TXN are the differential output pairs for each of the transmitters in the PS-GTR Quad.
MGTAVCC_[L or R] [N or S](4)
Dedicated
Input
Analog power-supply pin for the receiver and transmitter internal circuits for the GTH or GTY transceivers.
PS_MGTRAVCC
Dedicated
Analog power-supply pin for the receiver and
N/A
transmitter internal circuits for the PS-GTR
transceivers.
MGTAVTT_[L or R] [N or S](4)
Dedicated
Input
Analog power-supply pin for the transmitter and receiver termination circuits for the GTH or GTY transceivers.
MGTVCCAUX_[L or R] [N or S](4)
Dedicated
Input
Auxiliary analog Quad PLL (QPLL) voltage supply for the transceivers.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
28
Send Feedback
Chapter 1: Packaging Overview
Table 1-4: Pin Definitions (Cont'd)
Pin Name
Type
PS_MGTRAVTT
Dedicated
MGTREFCLK[0 or 1] [P or N]
PS_MGTREFCLK[0 to 3] [P or N] MGTAVTTRCAL_[L or R] [N or S](4) MGTRREF_[L or R] [N or S](4)
PS_MGTRREF
Dedicated Dedicated Dedicated Dedicated Dedicated
Zynq UltraScale+ RFSoC Dedicated Pins
VCCSDFEC
Dedicated
VCCINT_AMS
Dedicated
ADC_AVCC
Dedicated
ADC_AVCCAUX
Dedicated
ADC_GND
Dedicated
ADC_SUB_GND
Dedicated
ADC_CLK_[P or N]
Dedicated
VCM01/VCM23 ADC_VIN_[0 to 3]_[P or N] ADC_REXT DAC_AVCC DAC_AVCCAUX DAC_AVTT
Dedicated Dedicated Dedicated Dedicated Dedicated
Dedicated
DAC_GND DAC_SUB_GND DAC_CLK_[P or N]
Dedicated Dedicated
Dedicated
SYSREF_[P or N]
DAC_VOUT[0 to 3]_[P or N] DAC_REXT
Dedicated
Dedicated Dedicated
Direction
Description
Analog power-supply pin for the transmitter and
N/A
receiver termination circuits for the PS-GTR
transceivers.
Configured as either reference clock input pins or as Input/Output RX recovered clock output pins for the GTH or GTY
transceivers.
Input
Differential reference clock for the PS-GTR transceivers.
N/A
Bias current supply for the termination resistor calibration circuit.
Input
Calibration resistor pin for the termination resistor calibration circuit for the GTH or GTY transceivers.
Input
Calibration resistor pin for the termination resistor calibration circuit for the PS-GTR transceivers.
N/A N/A N/A N/A N/A N/A
Input
N/A Input N/A N/A N/A
N/A
N/A N/A
Input
Input
Output Input
Power supply for the FEC blocks. Digital power supply for the DDC. Core ADC and PLL power supply. Input buffer and PLL power supply. Analog ground for the ADC. Digital ground for the ADC. External reference clock for PLL or ADC direct sampling clock input. ADC common mode voltage. Analog input signal to the ADC. ADC external resistor. Core DAC and PLL power supply. DAC and PLL power supply. Termination voltage for on-die 50 termination resistors. Analog ground for the DAC. Digital ground for the DAC. External reference clock for PLL or DAC direct sampling clock input. External reference clock/trigger for synchronizing timing of the data converters. Analog output signals from the DAC. DAC external resistor.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
29
Send Feedback
Chapter 1: Packaging Overview
Table 1-4: Pin Definitions (Cont'd)
Pin Name
Type
Direction
Description
Other Dedicated Pins
DXN
DXP
Dedicated
Temperature-sensing diode pins (Anode: DXP;
Cathode: DXN). The thermal diode is accessed by
using the DXP and DXN pins. When not used, tie to
N/A
GND. To use the thermal diode an appropriate external
thermal monitoring IC must be added. Consult the
external thermal monitoring IC data sheet for usage
guidelines.
Notes: 1. See the DCI sections in UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 6] for more information on the
VRP pins. 2. VCCO pins in unbonded banks must be connected to the VCCO for that bank (for package migration). Do NOT connect
unbonded VCCO pins to different supplies. Without a package migration requirement, VCCO pins in unbonded banks can be tied to a common supply (VCCO or GND). 3. See the UltraScale Architecture System Monitor User Guide (UG580) [Ref 13] for the default connections required to support on-chip monitoring.
4. L (left), R (right), N (north), and S (south) signify the GT transceiver quad power supply groups.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
30
Send Feedback
Chapter 1: Packaging Overview
Footprint Compatibility between Packages
Zynq UltraScale+ devices are footprint compatible only with other Zynq UltraScale+ devices with the same number of package pins and the same preceding alphabetic designator. For example, XCZU9EG-FFVB1156 is compatible with the XCZU15EG-FFVB1156, but not with the XCZU9EG-FFVC900. Pins that are available in one device but are not available in another device are labeled as No Connects in the other device's package file.
IMPORTANT: Footprint compatibility does not necessarily imply that all pins will function in the same manner for different devices in a package. For limitations and guidelines on designing for footprint compatible packages, refer to the Migration Between the Zynq UltraScale+ Devices and Packages section of UltraScale Architecture PCB and Pin Planning User Guide (UG583) [Ref 14].
Table 1-5 shows the footprint compatible devices available for each package. See the Zynq UltraScale+ MPSoC Overview (DS891) [Ref 1] for specific package letter code options. All packages are available with eutectic BGA balls. For these packages, the device type is XQ and the Pb-free signifier in the package name is a Q.
Table 1-5: Footprint Compatibility
Packages
SBVA484 SFRA484
XCZU2CG, XCZU2EG, XAZU2EG
Footprint Compatible Devices
XCZU3CG, XCZU3EG, XAZU3EG, XQZU3EG
SFVA625
SFVC784 SFRC784
XCZU2CG, XCZU2EG, XAZU2EG XCZU2CG, XCZU2EG, XAZU2EG
XCZU3CG, XCZU3EG, XAZU3EG XCZU3CG, XCZU3EG, XAZU3EG, XQZU3EG
XCZU4CG, XCZU4EG, XCZU4EV, XAZU4EV
XCZU5CG, XCZU5EG, XCZU5EV, XAZU5EV, XQZU5EV
FBVB900 FFRB900
XCZU4CG, XCZU4EG, XCZU4EV
XCZU5CG, XCZU5EG, XCZU5EV, XQZU5EV
XCZU7CG, XCZU7EG, XCZU7EV, XAZU7EV, XQZU7EV
FFVC900 FFRC900
XCZU6CG, XCZU6EG
XCZU9CG, XCZU9EG, XQZU9EG
XCZU15EG, XQZU15EG
FFVB1156 FFRB1156
FFVC1156 FFRC1156
XCZU6CG, XCZU6EG XCZU7CG, XCZU7EG, XCZU7EV, XQZU7EV
XCZU9CG, XCZU9EG, XQZU9EG
XCZU15EG, XQZU15EG
XCZU11EG, XQZU11EG
FFVD1156 XCZU21DR, XQZU21DR
FFVE1156 FSVE1156 FFVB1517
XCZU25DR XCZU11EG
XCZU27DR, XCZU43DR, XCZU28DR, XQZU28DR XCZU47DR, XCZU49DR
XCZU17EG
XCZU19EG, XQZU19EG
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
31
Send Feedback
Chapter 1: Packaging Overview
Table 1-5: Footprint Compatibility (Cont'd)
Packages
FFVF1517
XCZU7CG, XCZU7EG, XCZU7EV
Footprint Compatible Devices
XCZU11EG, XAZU11EG
FFVG1517 FSVG1517
XCZU25DR
XCZU27DR, XCZU43DR, XCZU28DR, XQZU28DR XCZU47DR, XCZU49DR
FFVC1760 XCZU11EG, XQZU11EG XCZU17EG
XCZU19EG, XQZU19EG
FFVD1760
FFVF1760 FSVF1760 FFRF1760
XCZU17EG
XCZU19EG
XCZU29DR, XCZU39DR, XCZU49DR
XQZU29DR
FFVH1760 XCZU46DR
FSVH1760 XCZU46DR
FFVE1924 XCZU17EG
XCZU19EG
Many Zynq UltraScale+ devices that are footprint compatible in a package have different I/O bank and transceiver quad numbers connected to the same package pins. Due to these differences, when migrating between devices in a specific package, the type of bank (HD vs. HP) or quad (PS-GTR, GTH, or GTY), whether a bank is connected or NC at the package pins, and where the bank or quad is located on the die must be taken into consideration. Table 1-6 and Table 1-7 show how the banks and transceiver quads are numbered between devices in each package.
For all grouped-together footprint-compatible packages, the bank and quad numbers in the same column (indicated by the letters A through Z) for each device are connected to the same package pins. For example, in the FFVB1517 packages, bank 88 for the XCZU11 is connected to the same pins as bank 90 for the XCZU17 and XCZU19.
A limited number of HP I/O banks have fewer than 52 SelectIO pins. For a visual representation of all of this information, see the Die Level Bank Numbering Overview section.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
32
Send Feedback
Chapter 1: Packaging Overview
Table 1-6: I/O Bank Migration (HD Banks are Shaded)
Package
Device
Package to Device I/O Mapping(1) A B C D E F G H I J K L MNO P Q R S T U VWX Y Z
Unbonded I/O Banks
SBVA484
XCZU2 XAZU2 XCZU3 XAZU3
26 65 66(2) 26 65 66(2)
25, 24, 44, 64 25, 24, 44, 64
SFRA484 XQZU3
26 65 66(2)
25, 24, 44, 64
SFVA625
XCZU2 XAZU2 XCZU3 XAZU3
64 65 66 26 64 65 66 26
25, 24, 44 25, 24, 44
XCZU2 XAZU2
64 65 66 25 26
24 44
XCZU3 XAZU3
64 65 66 25 26
24 44
SFVC784
XCZU4 XAZU4
64 65 66 45 46
44 43
63
XCZU5 XAZU5
64 65 66 45 46
44 43
63
XQZU3
64 65 66 25 26
24 44
SFRC784
XQZU5
64 65 66 45 46
44 43
63
FBVB900 FFRB900
XCZU4 XCZU5 XCZU7 XAZU7 XQZU5 XQZU7
64 65 66 64 65 66 64 65 66 64 65 66 64 65 66 64 65 66
46 45 46 45 47 48 47 48 46 45 47 48
44, 43, 63 44, 43, 63 28, 27, 68, 67, 63, 88, 87 28, 27, 68, 67, 63, 88, 87 44, 43, 63 28, 27, 68, 67, 63, 88, 87
Zynq UltraScale+ Packaging and Pinouts
33
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 1: Packaging Overview
Table 1-6: I/O Bank Migration (HD Banks are Shaded) (Cont'd)
Package
Device
Package to Device I/O Mapping(1) A B C D E F G H I J K L MNO P Q R S T U VWX Y Z
Unbonded I/O Banks
XCZU6
64 65 66
48 47
50, 49, 44, 67
FFVC900 XCZU9
64 65 66
48 47
50, 49, 44, 67
XCZU15
64 65 66
48 47
50, 49, 44, 67
FFRC900
XQZU9 XQZU15
64 65 66 64 65 66
48 47 48 47
50, 49, 44, 67 50, 49, 44, 67
FFVB1156 FFRB1156
XCZU6 XCZU9 XCZU15 XQZU9 XQZU15
44 64 65 66 67 44 64 65 66 67 44 64 65 66 67 44 64 65 66 67 44 64 65 66 67
47 48 49 50 47 48 49 50 47 48 49 50 47 48 49 50 47 48 49 50
FFVC1156 FFRC1156
XCZU7 XCZU11 XQZU7 XQZU11
64 65 66 64 65 66 64 65 66 64 65 66
87 88 68 67 28 88 89 69 68 67 87 88 68 67 28 88 89 69 68 67
27, 48, 47, 63 71, 70, 91, 90 27, 48, 47, 63 71, 70, 91, 90
FFVD1156 XCZU21 FFRD1156 XQZU21
65 66 67 68 65 66 67 68
87 88 89 87 88 89
71, 70, 69, 64, 91, 90, 84 71, 70, 69, 64, 91, 90, 84
Zynq UltraScale+ Packaging and Pinouts
34
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 1: Packaging Overview
Table 1-6: I/O Bank Migration (HD Banks are Shaded) (Cont'd)
Package
Device
Package to Device I/O Mapping(1) A B C D E F G H I J K L MNO P Q R S T U VWX Y Z
Unbonded I/O Banks
XCZU25
65 66
88 89
69, 68, 67, 64, 87, 84
XCZU27
65 66
88 89
71, 70, 69, 68, 67, 64, 91, 90, 87, 84
FFVE1156 FSVE1156
XCZU28 XCZU43
65 66 65 66
88 89 88 89
71, 70, 69, 68, 67, 64, 91, 90, 87, 84 71, 70, 69, 68, 67, 64, 91, 90, 87, 84
XCZU47
65 66
88 89
71, 70, 69, 68, 67, 64, 91, 90, 87, 84
XCZU48
65 66
88 89
71, 70, 69, 68, 67, 64, 91, 90, 87, 84
FFRE1156 XQZU28
65 66
88 89
71, 70, 69, 68, 67, 64, 91, 90, 87, 84
FFVB1517 FFRB1517
XCZU11 XCZU17 XCZU19 XQZU19
65 64 66 65 64 66 65 64 66 65 64 66
88 89 90
71 70 69 68 67
91
90 91 93 74 73 72 71 70 69 68 67
94
90 91 93 74 73 72 71 70 69 68 67
94
90 91 93 74 73 72 71 70 69 68 67
94
FFVF1517
XCZU7 XCZU11 XAZU11
65 66 64 63 65 66 67 64 65 66 67 64
87 88 67 68 28 27 88 89 70 71 69 68 88 89 70 71 69 68
48, 47 91, 90 91, 90
Zynq UltraScale+ Packaging and Pinouts
35
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 1: Packaging Overview
Table 1-6: I/O Bank Migration (HD Banks are Shaded) (Cont'd)
Package
Device
Package to Device I/O Mapping(1) A B C D E F G H I J K L MNO P Q R S T U VWX Y Z
Unbonded I/O Banks
XCZU25 84 64 65 66
87
67 68 69
89, 88
XCZU27 84 64 65 66
87
67 68 69
71, 70, 91, 90, 89, 88
FFVG1517 XCZU28 FSVG1517 XCZU43
84 64 65 66 84 64 65 66
87
67 68 69
87
67 68 69
71, 70, 91, 90, 89, 88 71, 70, 91, 90, 89, 88
XCZU47 84 64 65 66
87
67 68 69
71, 70, 91, 90, 89, 88
XCZU48 84 64 65 66
87
67 68 69
71, 70, 91, 90, 89, 88
FFRG1517 XQZU28 84 64 65 66
87
67 68 69
71, 70, 91, 90, 89, 88
FFVC1760 FFRC1760
XCZU11 XCZU17 XCZU19 XQZU11 XQZU19
65 64 66 67 65 64 66 67 65 64 66 67 65 64 66 67 65 64 66 67
88 89 90 91 71 70 69 68 90 91 93 94 71 70 69 68 90 91 93 94 71 70 69 68 88 89 90 91 71 70 69 68 90 91 93 94 71 70 69 68
74, 73, 72 74, 73, 72
74, 73, 72
XCZU17 FFVD1760
XCZU19
65 66 65 66
90 91 71 70 69 90 91 71 70 69
74, 73, 72, 68, 67, 64, 94, 93 74, 73, 72, 68, 67, 64, 94, 93
FFVF1760 FSVF1760
FFRF1760
XCZU29 XCZU39 XCZU49 XQZU29
84 64 65 66 84 64 65 66 84 64 65 66 84 64 65 66
87 88 89 87 88 89 87 88 89 87 88 89
67 68 69 67 68 69 67 68 69 67 68 69
71, 70, 91, 90 71, 70, 91, 90 71, 70, 91, 90 71, 70, 91, 90
FFVH1760 FSVH1760
XCZU46
64 65 66
90 91 69 71 70
67, 68, 84, 87, 88, 89
Zynq UltraScale+ Packaging and Pinouts
36
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 1: Packaging Overview
Table 1-6: I/O Bank Migration (HD Banks are Shaded) (Cont'd)
Package
Device
Package to Device I/O Mapping(1) A B C D E F G H I J K L MNO P Q R S T U VWX Y Z
Unbonded I/O Banks
XCZU17 FFVE1924
XCZU19
65 64 66 67 65 64 66 67
90 91 93 94 74 73 72 71 70 69 68 90 91 93 94 74 73 72 71 70 69 68
Notes: 1. An alphabetical designator, A through Z, is assigned to every bank in a package. I/Os from banks with the same designator are bonded out to the same pins in
that package. For example, in the FFVF1517 package, the E designator is assigned to bank 67 for the XCZU11 and bank 64 for the XCZU7. These banks are bonded to the same pins, regardless of where they appear on the XCZU11 and XCZU7 device. 2. Bank 66 is partially bonded out in the SBVA484 package (see Figure 1-3).
Zynq UltraScale+ Packaging and Pinouts
37
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 1: Packaging Overview
For each grouped set of footprint compatible packages listed in Table 1-7, there is a row detailing the power supply group for each Quad. These groups are labeled according to the regions for the transceiver power supply pins, as listed in the ASCII Pinout Files linked from Chapter 3, Package Files. For a visual representation of all of this information, see the Die Level Bank Numbering Overview section.
Table 1-7: Transceiver Quad Migration (GTY Quads are in Shaded)
Package to Die Transceiver Mapping(1) Package Device
A B C D E F G H I J K L M N O P Q R S-Z AA-AF
SBVA484
XCZU2 XAZU2
XCZU3 XAZU3
SFRA484 XQZU3
SFVA625
XCZU2 XAZU2
XCZU3 XAZU3
Power Supply Group
R
XCZU2 XAZU2
XCZU3
SFVC784
XAZU3
XCZU4 XAZU4
224
XCZU5 XAZU5
224
SFRC784 XQZU3
XQZU5
224
226, 225, 223 226, 225, 223 226, 225, 223
Unbonded Quads
Zynq UltraScale+ Packaging and Pinouts
38
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 1: Packaging Overview
Table 1-7: Transceiver Quad Migration (GTY Quads are in Shaded) (Cont'd)
Package to Die Transceiver Mapping(1) Package Device
A B C D E F G H I J K L M N O P Q R S-Z AA-AF
Power Supply Group XCZU4
R 223 224 225 226
FBVB900
XCZU5 XCZU7 XAZU7
223 224 225 226 224 225 226 227 224 225 226 227
228, 223 228, 223
FFRB900
XQZU5 XQZU7
223 224 225 226 224 225 226 227
228, 223
Unbonded Quads
Power Supply Group
XCZU6
FFVC900 XCZU9
XCZU15
FFRC900
XQZU9 XQZU15
R
L
228 229 230 128
228 229 230 128
228 229 230 128
228 229 230 128
228 229 230 128
130, 129, 127 130, 129, 127 130, 129, 127 130, 129, 127 130, 129, 127
Power Supply Group
R
L
XCZU6
228 229 230 128 129 130
127
FFVB1156 XCZU9
228 229 230 128 129 130
127
XCZU15 228 229 230 128 129 130
127
FFRB1156
XQZU9 XQZU15
228 229 230 128 129 130 228 229 230 128 129 130
127 127
Power Supply Group
XCZU7 FFVC1156 XCZU11
FFRC1156
XQZU7 XQZU11
R 223 224 225 226 227 224 225 226 227 228 223 224 225 226 227 224 225 226 227 228
228 131, 130, 129, 128, 127, 229, 231, 230 228 131, 130, 129, 128, 127, 229, 231, 230
Power Supply Group
L
FFVD1156 XCZU21 128 129 130 131
127
FFRD1156 XQZU21 128 129 130 131
127
Zynq UltraScale+ Packaging and Pinouts
39
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 1: Packaging Overview
Table 1-7: Transceiver Quad Migration (GTY Quads are in Shaded) (Cont'd)
Package to Die Transceiver Mapping(1) Package Device
A B C D E F G H I J K L M N O P Q R S-Z AA-AF
Power Supply Group
L
FFVE1156 FSVE1156
XCZU25 XCZU27 XCZU28 XCZU43
128 129 128 129 128 129 128 129
127 131, 130, 127 131, 130, 127 131, 130, 127
XCZU47 128 129
131, 130, 127
XCZU48 128 129
131, 130, 127
FFRE1156 XCZU28 128 129
131, 130, 127
Unbonded Quads
Power Supply Group XCZU11
FFVB1517
XCZU17 XCZU19
XAZU11
FFRB1517 XQZU19
R 224 225 226 227 224 225 226 227
224 225 226 227 224 225 226 227 224 225 226 227
131, 130, 129, 128, 127, 231, 230, 229, 228
134, 133, 132, 131, 130, 129, 128, 127, 234, 233, 232, 231, 230, 229, 228
134, 133, 132, 131, 130, 129, 128, 127, 234, 233, 232, 231, 230, 229, 228
131, 130, 129, 128, 127, 231, 230, 229, 228
134, 133, 132, 131, 130, 129, 128, 127, 234, 233, 232, 231, 230, 229, 228
Power Supply Group
FFVF1517
XCZU7 XCZU11
RS
RN
223 224 225 226 227 228
224 225 226 227 228 229 230 231
131, 130, 129, 128, 127
Power Supply Group
L
XCZU25 128 129
127
XCZU27 128 129 130 131
127
FFVG1517 XCZU28 128 129 130 131
127
FSVG1517 XCZU43 128 129 130 131
127
XCZU47 128 129 130 131
127
XCZU48 128 129 130 131
127
Zynq UltraScale+ Packaging and Pinouts
40
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 1: Packaging Overview
Table 1-7: Transceiver Quad Migration (GTY Quads are in Shaded) (Cont'd)
Package to Die Transceiver Mapping(1) Package Device
A B C D E F G H I J K L M N O P Q R S-Z AA-AF
FFRG1517 XQZU28 128 129 130 131
127
Unbonded Quads
Power Supply Group XCZU11
FFVC1760 XCZU17 XCZU19 XQZU11
FFRC1760 XQZU19
RS
RN
224 225 226 227 228 229 230 231
224 225 226 227 228 229 230 231
224 225 226 227 228 229 230 231
224 225 226 227 228 229 230 231
224 225 226 227 228 229 230 231
L 128 129 130 131 128 129 130 131 128 129 130 131 128 129 130 131 128 129 130 131
127 127 134, 133, 132, 127, 234, 233, 232 127 134, 133, 132, 127, 234, 233, 232
Power Supply Group
RS
RN
L
FFVD1760 XCZU17
224 225 226 227 228 229 230 231 232 233 234 128 129 130 131 132 133 134
127
XCZU19 224 225 226 227 228 229 230 231 232 233 234 128 129 130 131 132 133 134
127
Power Supply Group
L
XCZU29 128 129 130 131
127
FFVF1760 FSVF1760
XCZU39
128 129 130 131
127
XCZU49 128 129 130 131
127
FFVH1760 FSVH1760
XCZU46
128 129 130 131
127
FFRF1760 XQZU29 128 129 130 131
127
Power Supply Group XCZU17
FFVE1924 XCZU19
RS
RN
224 225 226 227 228 229 230 231 232 233 234
224 225 226 227 228 229 230 231 232 233 234
134, 133, 132, 131, 130, 129, 128, 127 134, 133, 132, 131, 130, 129, 128, 127
Notes: 1. An alphabetical designator, A through Z, is assigned to every Quad in a package. Transceivers from Quads with the same designator are bonded out to the same pins in
that package. For example, in the FFVF1517 package, the E designator is assigned to Quad 228 for the XCZU11 and Quad 227 for the XCZU7. These Quads are bonded to the same pins, regardless of where they appear on the XCZU11 and XCZU7 device.
Zynq UltraScale+ Packaging and Pinouts
41
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 1: Packaging Overview
Die Level Bank Numbering Overview
Banking and Clocking Summary
� For each device, not all banks are bonded out in every package.
GTH/GTY Columns
� One GT Quad = Four transceivers = Four GTHE4 or GTYE4 primitives. � Not all GT Quads are bonded out in every package. � Also shown are quads labeled with RCAL. This specifies the location of the RCAL
masters for each device. With respect to the package, the RCAL masters are located on the same package pin for each package, regardless of the device. � The XY coordinates shown in each quad correspond to the transceiver channel number found in the pin names for that quad, as shown in Figure 1-2. � An alphabetic designator is shown in each quad. Each letter corresponds to the columns in Table 1-6 and Table 1-7. � The power supply group is shown in brackets [ ] for each quad.
I/O Banks
� Each user HP I/O bank has a total of 52 I/Os where 48 can be used as differential (24 differential pairs) or single-ended I/Os. The remaining four function only as single-ended I/Os. All 52 pads of a bank are not always bonded out to pins.
� A limited number of HP I/O banks have fewer than 52 SelectIO pins. These banks are labeled as partial.
� Each user HD I/O bank has a total of 24 I/Os that can be used as differential (12 differential pairs) or single-ended I/Os.
� Adjacent to each bank is a physical layer (PHY) containing a CMT and other clock resources.
� Adjacent to each bank and PHY is a tile of logic resources that makes up a clock region. � Banks are arranged in columns and separated into rows which are pitch-matched with
adjacent PHY, clock regions, and GT blocks. � An alphabetic designator is shown in each bank. Each letter corresponds to the
columns in Table 1-6 and Table 1-7.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
42
Send Feedback
Chapter 1: Packaging Overview
Clocking
� Each bank has four pairs of global clock (GC or HDGC) inputs for four differential or four single-ended clock inputs. Single-ended clock inputs should be connected to the P-side of the differential pair.
� Clock signals are distributed through global buffers driving routing and distribution networks to reach any clock region, I/O, or GT.
� Global clock inputs can connect to an MMCM and two PLLs within the horizontally adjacent CMT.
Bank Locations of Dedicated and Multi-Function Pins
� All dedicated configuration I/Os and HD I/Os are 3.3V capable.
Processor (PS) Blocks
� MIO pins are shared between banks 500, 501, and 502. � Configuration pins are in bank 503. � DDR memory pins are in bank 504. � Transceiver pins are in the PS-GTR quad 505.
SYSMON, Configuration, PCIe, Interlaken, and 100GE Integrated Blocks
� Configuration: Configuration block. � SYSMON/Configuration: Block shared between the SYSMONE4 and configuration. � PCIe: Integrated block for PCIe.
Note: PCIe blocks with an additional (Tandem) label support tandem configuration. � ILKN: Interlaken block. � CMAC: 100G Ethernet block.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
43
Send Feedback
Chapter 1: Packaging Overview
Device Diagrams
Figure 1-1 shows an example diagram with a brief explanation for each component.
X-Ref Target - Figure 1-1
*7<4XDG ;<;<
0>/@ *7<4XDG ;<;<
/>/@ *7<4XDG ;<;< .>/@5&$/ *7<4XDG
;<;< ->/@
*7<4XDG X0Y0-X0Y3
3&,( ;<
&0$& X0Y1
,/.1 X0Y0
3&,( ;<
&0$& X0Y0
36*75
360,2
36''5
360,2
36&21),* 360,2
+3,2%DQN 5
+3,2%DQN S
+3,2%DQN 7
+3,2%DQN U
+3,2%DQN F
+3,2%DQN E
+3,2%DQN C
+3,2%DQN D
+',2%DQN Q
+',2%DQN 3
+',2%DQN 2
+',2%DQN 1
3&,( X1Y1
6<6021 &RQILJXUDWLRQ
&RQILJXUDWLRQ
3&,( X1Y0 WDQGHP
*7+4XDG ;<;<
+>51@ *7+4XDG ;<;<
*>51@ *7+4XDG ;<;<
)>51@ *7+4XDG ;<;<
(>51@ *7+4XDG ;<;<
'>56@ *7+4XDG ;<;< &>56@5&$/ *7+4XDG
;<;< %>56@
*7+4XDG X0Y0-X0Y3 $>56@
;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B
7UDQVFHLYHU3RZHU 6XSSO\*URXS
;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B ;<0*7+>7;RU5;@>3RU1@B
;
,2%DQN7\SH {+3RU+'`
,QWHJUDWHG%ORFNV DQG7UDQVFHLYHU ;<&RRUGLQDWHV
Alphabetic Bank/Quad 'HVLJQDWRU&RUUHVSRQGV WRFROXPQVLQ7DEOH DQG7DEOH
Figure 1-1: Example Device Diagram
Figure 1-2 through Figure 1-41 show a die view of each device followed by a view with respect to each available package. The available resources by device and package are detailed in the Zynq UltraScale+ MPSoC Overview (DS891) [Ref 1] or Zynq UltraScale+ RFSoC Overview (DS889) [Ref 2].
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
44
Send Feedback
Chapter 1: Packaging Overview
XCZU2, XAZU2, XCZU3, XAZU3, and XQZU3 Bank Diagram Overview
X-Ref Target - Figure 1-2
PS GTR 505
PS MIO 502
HD I/O Bank 26
SYSMON Configuration
HP I/O Bank 66
PS DDR 504
PS MIO 501
HD I/O Bank 25 Configuration HP I/O Bank 65
PS CONFIG 503 PS MIO 500
HD I/O Bank 24 HD I/O Bank 44 HP I/O Bank 64
X15118-060720
Figure 1-2: XCZU2, XAZU2, XCZU3, XAZU3, and XQZU3 Banks
Bank Diagram by Package for XCZU2, XAZU2, XCZU3, XAZU3, and XQZU3
X-Ref Target - Figure 1-3
PS GTR 505
PS MIO 502
HD I/O Bank 26 B
SYSMON Configuration
HP I/O Bank 66 D (Partial)
PS DDR 504 (Partial)
PS MIO 501
HD I/O Bank 25 Configuration
HP I/O Bank 65 C
PS CONFIG 503 PS MIO 500
HD I/O Bank 24 HD I/O Bank 44 HP I/O Bank 64
X15119-060720
Figure 1-3: XCZU2, XAZU2, XCZU3, and XAZU3 Banks in SBVA484 Package
IMPORTANT: For the devices in the SBVA484 package shown in Figure 1-3, the HP I/Os in bank 66 are powered by VCCO_65.
X-Ref Target - Figure 1-4
PS GTR 505
PS MIO 502
HD I/O Bank 26 E
SYSMON Configuration
HP I/O Bank 66 D
PS DDR 504 (Partial)
PS MIO 501
HD I/O Bank 25
Configuration
HP I/O Bank 65 C
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 HD I/O Bank 24 HD I/O Bank 44
B
X15120-060720
Figure 1-4: XCZU2, XAZU2, XCZU3, and XAZU3 Banks in SFVA625 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
45
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-5
PS GTR 505
PS MIO 502
HD I/O Bank 26 F
SYSMON Configuration
HP I/O Bank 66 D
PS DDR 504
PS MIO 501
HD I/O Bank 25 E
Configuration
HP I/O Bank 65 C
PS CONFIG 503 PS MIO 500
HD I/O Bank 24 HD I/O Bank 44 HP I/O Bank 64
N
O
B
X15121-060720
Figure 1-5: XCZU2, XAZU2, XCZU3, XAZU3, and XQZU3 Banks in SFVC784 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
46
Send Feedback
Chapter 1: Packaging Overview
XCZU4, XAZU4, XCZU5, XAZU5, and XQZU5 Bank Diagram Overview
X-Ref Target - Figure 1-6
PS GTR 505
PS MIO 502
HD I/O Bank 46 HP I/O Bank 66
SYSMON Configuration
GTH Quad 226 X0Y12-X0Y15
PS DDR 504
PS MIO 501
PS CONFIG 503 PS MIO 500
HD I/O Bank 45 HP I/O Bank 65 Configuration
HD I/O Bank 44 HP I/O Bank 64 HD I/O Bank 43 HP I/O Bank 63
PCIE4 X0Y1 (tandem)
PCIE4 X0Y0
Figure 1-6: XCZU4, XAZU4, XCZU5, XAZU5, and XQZU5 Banks
GTH Quad 225 X0Y8-X0Y11
GTH Quad 224 X0Y4-X0Y7 (RCAL)
GTH Quad 223 X0Y0-X0Y3
X15122-060720
Bank Diagram by Package for XCZU4, XAZU4, XCZU5, XAZU5, and XQZU5
X-Ref Target - Figure 1-7
PS GTR 505
PS MIO 502
HD I/O Bank 46 HP I/O Bank 66
F
D
SYSMON Configuration
GTH Quad 226 X0Y12-X0Y15
PS DDR 504
PS MIO 501
HD I/O Bank 45 HP I/O Bank 65
E
C
Configuration
GTH Quad 225 X0Y8-X0Y11
PS CONFIG 503 PS MIO 500
HD I/O Bank 44 HP I/O Bank 64
N
B
PCIE4 X0Y1 (tandem)
GTH Quad 224 X0Y4-X0Y7 A [R] (RCAL)
HD I/O Bank 43 HP I/O Bank 63
O
PCIE4 X0Y0
GTH Quad 223 X0Y0-X0Y3
X15124-111316
Figure 1-7: XCZU4, XAZU4, XCZU5, and XAZU5 Banks in SFVC784 Package and XQZU5 Banks in SFRC784 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
47
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-8
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
PS CONFIG 503 PS MIO 500
HD I/O Bank 46 HP I/O Bank 66
N
D
HD I/O Bank 45 HP I/O Bank 65
O
C
HP I/O Bank 64 HD I/O Bank 44
B
HD I/O Bank 43 HP I/O Bank 63
SYSMON Configuration
Configuration
PCIE4 X0Y1
PCIE4 X0Y0
Figure 1-8: XCZU4 and XCZU5 Banks in FBVB900 Package and XQZU5 Banks in FFRB900 Package
GTH Quad 226 X0Y12-X0Y15
D [R] GTH Quad 225 X0Y8-X0Y11
C [R] GTH Quad 224
X0Y4-X0Y7 B [R] (RCAL) GTH Quad 223 X0Y0-X0Y3
A [R]
X15123-112916
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
48
Send Feedback
Chapter 1: Packaging Overview
XCZU7, XAZU7, and XQZU7 Bank Diagram Overview
X-Ref Target - Figure 1-9
GTH Quad 228 HP I/O Bank 28 HD I/O Bank 48 HP I/O Bank 68 HD I/O Bank 88
X0Y20-X0Y23
GTH Quad 227 HP I/O Bank 27 HD I/O Bank 47 HP I/O Bank 67 HD I/O Bank 87
X0Y16-X0Y19
PS GTR 505
PS MIO 502
HP I/O Bank 66
SYSMON Configuration
GTH Quad 226 X0Y12-X0Y15
PS DDR 504
PS MIO 501
HP I/O Bank 65 Configuration
PS CONFIG 503 PS MIO 500
HP I/O Bank 64
PCIE4 X0Y1 (tandem)
X15125-111316
HP I/O Bank 63
PCIE4 X0Y0
Figure 1-9: XCZU7, XAZU7, and XQZU7 Banks
Bank Diagram by Package for XCZU7, XAZU7, and XQZU7
GTH Quad 225 X0Y8-X0Y11
GTH Quad 224 X0Y4-X0Y7 (RCAL)
GTH Quad 223 X0Y0-X0Y3
X-Ref Target - Figure 1-10
HD I/O Bank 48
GTH Quad 228
HP I/O Bank 28
HP I/O Bank 68 HD I/O Bank 88
O
X0Y20-X0Y23
HD I/O Bank 47 HP I/O Bank 27
N
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
PS CONFIG 503 PS MIO 500
HP I/O Bank 67
HP I/O Bank 66 D
HP I/O Bank 65 C
HP I/O Bank 64 B
HD I/O Bank 87
SYSMON Configuration
Configuration
PCIE4 X0Y1
GTH Quad 227 X0Y16-X0Y19
D [R] GTH Quad 226 X0Y12-X0Y15
C [R] GTH Quad 225 X0Y8-X0Y11
B [R] GTH Quad 224
X0Y4-X0Y7 A [R] (RCAL)
HP I/O Bank 63
PCIE4 X0Y0
GTH Quad 223 X0Y0-X0Y3
X15126-112916
Figure 1-10: XCZU7 and XAZU7 Banks in FBVB900 Package and XQZU7 Banks in FFRB900 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
49
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-11
HP I/O Bank 28
HP I/O Bank 68 HD I/O Bank 88 GTH Quad 228
HD I/O Bank 48
R
P
O
X0Y20-X0Y23
HP I/O Bank 27 HD I/O Bank 47
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
PS CONFIG 503 PS MIO 500
X15127-111316
HP I/O Bank 67 Q
HP I/O Bank 66 D
HP I/O Bank 65 C
HP I/O Bank 64 B
HP I/O Bank 63
HD I/O Bank 87 N
SYSMON Configuration
Configuration
PCIE4 X0Y1 (tandem) PCIE4 X0Y0
GTH Quad 227 X0Y16-X0Y19
E [R] GTH Quad 226 X0Y12-X0Y15
D [R] GTH Quad 225 X0Y8-X0Y11
C [R] GTH Quad 224
X0Y4-X0Y7 B [R] (RCAL) GTH Quad 223 X0Y0-X0Y3
A [R]
Figure 1-11: XCZU7 Banks in FFVC1156 Package and XQZU7 Banks in FFRC1156 Package
X-Ref Target - Figure 1-12
HP I/O Bank 28 HD I/O Bank 48
R HP I/O Bank 27
HD I/O Bank 47 S
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
PS CONFIG 503 PS MIO 500
X15128-111316
HP I/O Bank 68 Q
HP I/O Bank 67 P
HP I/O Bank 66 D
HP I/O Bank 65 C
HP I/O Bank 64 E
HP I/O Bank 63 F
HD I/O Bank 88 O
HD I/O Bank 87 N
SYSMON Configuration
Configuration
PCIE4 X0Y1 (tandem) PCIE4 X0Y0
GTH Quad 228 X0Y20-X0Y23
F [RN] GTH Quad 227 X0Y16-X0Y19
E [RN] GTH Quad 226 X0Y12-X0Y15
D [RS] GTH Quad 225 X0Y8-X0Y11
C [RS] GTH Quad 224
X0Y4-X0Y7 B [RS] (RCAL) GTH Quad 223
X0Y0-X0Y3 A [RS]
Figure 1-12: XCZU7 Banks in FFVF1517 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
50
Send Feedback
Chapter 1: Packaging Overview
XCZU6, XCZU9, and XQZU9 Bank Diagram Overview
X-Ref Target - Figure 1-13
GTH Quad 130 X0Y12-X0Y15
GTH Quad 230 HD I/O Bank 50
X1Y12-X1Y15
GTH Quad 129 X0Y8-X0Y11
GTH Quad 128 X0Y4-X0Y7 (RCAL)
GTH Quad 127 X0Y0-X0Y3
HD I/O Bank 49 HD I/O Bank 48
GTH Quad 229 X1Y8-X1Y11
GTH Quad 228 X1Y4-X1Y7 (RCAL)
HD I/O Bank 47 HP I/O Bank 67
PS GTR 505
PS MIO 502
SYSMON Configuration
HP I/O Bank 66
PS DDR 504
PS MIO 501
Configuration HP I/O Bank 65
PS CONFIG 503 PS MIO 500
HD I/O Bank 44 HP I/O Bank 64
X15129-061420
Figure 1-13: XCZU6, XCZU9, and XQZU9 Banks
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
51
Send Feedback
Chapter 1: Packaging Overview
Bank Diagram by Package for XCZU6, XCZU9, and XQZU9
X-Ref Target - Figure 1-14
GTH Quad 130 X0Y12-X0Y15
GTH Quad 129 X0Y8-X0Y11
GTH Quad 128 X0Y4-X0Y7 D [L] (RCAL)
GTH Quad 127 X0Y0-X0Y3
HD I/O Bank 50
HD I/O Bank 49
HD I/O Bank 48 N
HD I/O Bank 47 O
GTH Quad 230 X1Y12-X1Y15
C [R] GTH Quad 229 X1Y8-X1Y11
B [R] GTH Quad 228
X1Y4-X1Y7 A [R] (RCAL)
HP I/O Bank 67
PS GTR 505
PS MIO 502
SYSMON Configuration
HP I/O Bank 66 D
PS DDR 504
PS MIO 501
Configuration
HP I/O Bank 65 C
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 HD I/O Bank 44
B
X15130-061420
Figure 1-14: XCZU6 and XCZU9 Banks in FFVC900 Package and XQZU9 in FFRC900 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
52
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-15
GTH Quad 130 X0Y12-X0Y15
F [L] GTH Quad 129 X0Y8-X0Y11
E [L] GTH Quad 128
X0Y4-X0Y7 D [L] (RCAL)
GTH Quad 127 X0Y0-X0Y3
HD I/O Bank 50 Q
HD I/O Bank 49 P
HD I/O Bank 48 O
HD I/O Bank 47 N
GTH Quad 230 X1Y12-X1Y15
C [R] GTH Quad 229 X1Y8-X1Y11
B [R] GTH Quad 228
X1Y4-X1Y7 A [R] (RCAL)
HP I/O Bank 67 E
PS GTR 505
PS MIO 502
SYSMON Configuration
HP I/O Bank 66 D
PS DDR 504
PS MIO 501
Configuration
HP I/O Bank 65 C
PS CONFIG 503 PS MIO 500
HD I/O Bank 44 HP I/O Bank 64
A
B
X15131-061420
Figure 1-15: XCZU6 and XCZU9 Banks in FFVB1156 Package and XQZU9 in FFRB1156 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
53
Send Feedback
Chapter 1: Packaging Overview
XCZU11, XAZU11, and XQZU11 Bank Diagram Overview
X-Ref Target - Figure 1-16
GTY Quad 131 X0Y16-X0Y19
PCIE4 X0Y3
GTH Quad 231 HP I/O Bank 71 HD I/O Bank 91
X0Y28-X0Y31
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y2
GTH Quad 230 HP I/O Bank 70 HD I/O Bank 90
X0Y24-X0Y27 GTH Quad 229 HP I/O Bank 69 HD I/O Bank 89 X0Y20-X0Y23 GTH Quad 228 HP I/O Bank 68 HD I/O Bank 88 X0Y16-X0Y19
GTY Quad 127 X0Y0-X0Y3
CMAC X0Y0
HP I/O Bank 67
PCIE4 X1Y1
GTH Quad 227 X0Y12-X0Y15
PS GTR 505
PS MIO 502
HP I/O Bank 66
SYSMON Configuration
GTH Quad 226 X0Y8-X0Y11
(RCAL)
PS DDR 504
PS MIO 501
HP I/O Bank 65
Configuration
GTH Quad 225 X0Y4-X0Y7
PS CONFIG 503 PS MIO 500
X15132-121517
HP I/O Bank 64
PCIE4 X1Y0 (tandem)
GTH Quad 224 X0Y0-X0Y3
Figure 1-16: XCZU11, XAZU11, and XQZU11 Banks
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
54
Send Feedback
Chapter 1: Packaging Overview
Bank Diagram by Package for XCZU11, XAZU11, and XQZU11
X-Ref Target - Figure 1-17
GTY Quad 131 X0Y16-X0Y19
PCIE4 X0Y3
GTH Quad 231 HP I/O Bank 71 HD I/O Bank 91
X0Y28-X0Y31
GTY Quad 130 X0Y12-X0Y15
CMAC X0Y1
GTH Quad 230 HP I/O Bank 70 HD I/O Bank 90
X0Y24-X0Y27
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
GTY Quad 127 X0Y0-X0Y3
ILKN X0Y0
PCIE4 X0Y2
CMAC X0Y0
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
PS CONFIG 503 PS MIO 500
X15133-121517
HP I/O Bank 69 P
HP I/O Bank 68 Q
HP I/O Bank 67 R
HP I/O Bank 66 D
HP I/O Bank 65 C
HP I/O Bank 64 B
HD I/O Bank 89 O
HD I/O Bank 88 N
PCIE4 X1Y1
SYSMON Configuration
Configuration
PCIE4 X1Y0 (tandem)
GTH Quad 229 X0Y20-X0Y23
GTH Quad 228 X0Y16-X0Y19
E [R] GTH Quad 227 X0Y12-X0Y15
D [R] GTH Quad 226 X0Y8-X0Y11 C [R] (RCAL) GTH Quad 225
X0Y4-X0Y7 B [R]
GTH Quad 224 X0Y0-X0Y3 A [R]
Figure 1-17: XCZU11 Banks in FFVC1156 Package and XQZU11 Banks in FFRC1156 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
55
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-18
GTY Quad 131 X0Y16-X0Y19
PCIE4 X0Y3
HP I/O Bank 71
GTH Quad 231
HD I/O Bank 91
T
X0Y28-X0Y31
GTY Quad 130 X0Y12-X0Y15
CMAC X0Y1
HP I/O Bank 70 HD I/O Bank 90 GTH Quad 230
U
P
X0Y24-X0Y27
GTY Quad 129 X0Y8-X0Y11
(RCAL)
ILKN X0Y0
HP I/O Bank 69 HD I/O Bank 89 GTH Quad 229
V
O
X0Y20-X0Y23
GTY Quad 128 X0Y4-X0Y7
PCIE4 X0Y2
HP I/O Bank 68 HD I/O Bank 88 GTH Quad 228
W
N
X0Y16-X0Y19
GTY Quad 127 X0Y0-X0Y3
CMAC X0Y0
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
PS CONFIG 503 PS MIO 500
X15134-121517
HP I/O Bank 67 X
HP I/O Bank 66 E
HP I/O Bank 65 C
HP I/O Bank 64 D
PCIE4 X1Y1
SYSMON Configuration
Configuration
PCIE4 X1Y0 (tandem)
GTH Quad 227 X0Y12-X0Y15
D [R] GTH Quad 226 X0Y8-X0Y11 C [R] (RCAL) GTH Quad 225
X0Y4-X0Y7 B [R]
GTH Quad 224 X0Y0-X0Y3 A [R]
Figure 1-18: XCZU11 Banks in FFVB1517 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
56
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-19
GTY Quad 131 X0Y16-X0Y19
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y3
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y2
CMAC X0Y0
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
PS CONFIG 503 PS MIO 500
X15135-121517
HP I/O Bank 71 Q
HP I/O Bank 70 P
HP I/O Bank 69 R
HP I/O Bank 68 S
HP I/O Bank 67 E
HP I/O Bank 66 D
HP I/O Bank 65 C
HP I/O Bank 64 F
HD I/O Bank 91
HD I/O Bank 90
HD I/O Bank 89 O
HD I/O Bank 88 N
PCIE4 X1Y1
SYSMON Configuration
Configuration
PCIE4 X1Y0 (tandem)
GTH Quad 231 X0Y28-X0Y31
H [RN] GTH Quad 230 X0Y24-X0Y27
G [RN] GTH Quad 229 X0Y20-X0Y23
F [RN] GTH Quad 228 X0Y16-X0Y19
E [RN] GTH Quad 227 X0Y12-X0Y15
D [RS] GTH Quad 226 X0Y8-X0Y11 C [RS] (RCAL) GTH Quad 225
X0Y4-X0Y7 B [RS]
GTH Quad 224 X0Y0-X0Y3 A [RS]
Figure 1-19: XCZU11 and XAZU11 Banks in FFVF1517 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
57
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-20
GTY Quad 131 X0Y16-X0Y19
M [L] GTY Quad 130 X0Y12-X0Y15
L [L] GTY Quad 129 X0Y8-X0Y11 K [L] (RCAL) GTY Quad 128
X0Y4-X0Y7 J [L]
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y3
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y2
CMAC X0Y0
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
PS CONFIG 503 PS MIO 500
X15136-121517
HP I/O Bank 71 R
HP I/O Bank 70 S
HP I/O Bank 69 T
HP I/O Bank 68 U
HP I/O Bank 67 F
HP I/O Bank 66 E
HP I/O Bank 65 C
HP I/O Bank 64 D
HD I/O Bank 91 Q
HD I/O Bank 90 P
HD I/O Bank 89 O
HD I/O Bank 88 N
PCIE4 X1Y1
SYSMON Configuration
Configuration
PCIE4 X1Y0 (tandem)
GTH Quad 231 X0Y28-X0Y31
H [RN] GTH Quad 230 X0Y24-X0Y27
G [RN] GTH Quad 229 X0Y20-X0Y23
F [RN] GTH Quad 228 X0Y16-X0Y19
E [RN] GTH Quad 227 X0Y12-X0Y15
D [RS] GTH Quad 226 X0Y8-X0Y11 C [RS] (RCAL) GTH Quad 225
X0Y4-X0Y7 B [RS]
GTH Quad 224 X0Y0-X0Y3 A [RS]
Figure 1-20: XCZU11 Banks in FFVC1760 Package and XQZU11 Banks in FFRC1760 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
58
Send Feedback
Chapter 1: Packaging Overview
XCZU15 and XQZU15 Bank Diagrams
X-Ref Target - Figure 1-21
GTH Quad 130 X0Y12-X0Y15
HD I/O Bank 50
GTH Quad 230 X1Y12-X1Y15
GTH Quad 129 X0Y8-X0Y11
GTH Quad 128 X0Y4-X0Y7 (RCAL)
GTH Quad 127 X0Y0-X0Y3
HD I/O Bank 49 HD I/O Bank 48
GTH Quad 229 X1Y8-X1Y11
GTH Quad 228 X1Y4-X1Y7 (RCAL)
HD I/O Bank 47 HP I/O Bank 67
PS GTR 505
PS MIO 502
SYSMON Configuration
HP I/O Bank 66
PS DDR 504
PS MIO 501
Configuration HP I/O Bank 65
PS CONFIG 503 PS MIO 500
HD I/O Bank 44 HP I/O Bank 64
Figure 1-21: XCZU15 and XQZU15 Banks
X15137-061420
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
59
Send Feedback
Chapter 1: Packaging Overview
Bank Diagram by Package for XCZU15 and XQZU15
X-Ref Target - Figure 1-22
GTH Quad 130 X0Y12-X0Y15
GTH Quad 129 X0Y8-X0Y11
GTH Quad 128 X0Y4-X0Y7 D [L] (RCAL)
GTH Quad 127 X0Y0-X0Y3
HD I/O Bank 50
HD I/O Bank 49
HD I/O Bank 48 N
HD I/O Bank 47 O
GTH Quad 230 X1Y12-X1Y15
C [R] GTH Quad 229 X1Y8-X1Y11
B [R] GTH Quad 228
X1Y4-X1Y7 A [R] (RCAL)
HP I/O Bank 67
PS GTR 505
PS MIO 502
SYSMON Configuration
HP I/O Bank 66 D
PS DDR 504
PS MIO 501
Configuration
HP I/O Bank 65 C
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 HD I/O Bank 44
B
X15138-061420
Figure 1-22: XCZU15 Banks in FFVC900 Package and XQZU15 Banks in FFRC900 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
60
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-23
GTH Quad 130 X0Y12-X0Y15
F [L] GTH Quad 129 X0Y8-X0Y11
E [L] GTH Quad 128
X0Y4-X0Y7 D [L] (RCAL)
GTH Quad 127 X0Y0-X0Y3
HD I/O Bank 50 Q
HD I/O Bank 49 P
HD I/O Bank 48 O
HD I/O Bank 47 N
GTH Quad 230 X1Y12-X1Y15
C [R] GTH Quad 229 X1Y8-X1Y11
B [R] GTH Quad 228
X1Y4-X1Y7 A [R] (RCAL)
HP I/O Bank 67 E
PS GTR 505
PS MIO 502
SYSMON Configuration
HP I/O Bank 66 D
PS DDR 504
PS MIO 501
Configuration
HP I/O Bank 65 C
PS CONFIG 503 PS MIO 500
HD I/O Bank 44 HP I/O Bank 64
A
B
X15139-061420
Figure 1-23: XCZU15 Banks in FFVB1156 Package and XQZU15 Banks in FFRB1156 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
61
Send Feedback
Chapter 1: Packaging Overview
XCZU17, XCZU19, and XQZU19 Bank Diagram Overview
X-Ref Target - Figure 1-24
GTY Quad 134 X0Y28-X0Y31
CMAC X0Y3
GTH Quad 234 HP I/O Bank 74 HD I/O Bank 94
X0Y40-X0Y43
GTY Quad 133 X0Y24-X0Y27
ILKN X0Y2
GTH Quad 233 HP I/O Bank 73 HD I/O Bank 93
X0Y36-X0Y39
GTY Quad 132 X0Y20-X0Y23
CMAC X0Y2
HP I/O Bank 72
ILKN X1Y1
GTH Quad 232 X0Y32-X0Y35
GTY Quad 131 X0Y16-X0Y19
PCIE4 X0Y3
GTH Quad 231 HP I/O Bank 71 HD I/O Bank 91
X0Y28-X0Y31
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y2
GTH Quad 230 HP I/O Bank 70 HD I/O Bank 90
X0Y24-X0Y27
HP I/O Bank 69
ILKN X1Y0
GTH Quad 229 X0Y20-X0Y23
HP I/O Bank 68
PCIE4 X1Y2
GTH Quad 228 X0Y16-X0Y19
GTY Quad 127 X0Y0-X0Y3
CMAC X0Y0
HP I/O Bank 67
PCIE4 X1Y1
GTH Quad 227 X0Y12-X0Y15
PS GTR 505
PS MIO 502
HP I/O Bank 66
SYSMON Configuration
GTH Quad 226 X0Y8-X0Y11
(RCAL)
PS DDR 504
PS MIO 501
HP I/O Bank 65
Configuration
GTH Quad 225 X0Y4-X0Y7
PS CONFIG 503 PS MIO 500
HP I/O Bank 64
PCIE4 X1Y0 (tandem)
GTH Quad 224 X0Y0-X0Y3
X15140-071417
Figure 1-24: XCZU17, XCZU19, and XQZU19 Banks
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
62
Send Feedback
Chapter 1: Packaging Overview
Bank Diagram by Package for XCZU17, XCZU19, and XQZU19
X-Ref Target - Figure 1-25
GTY Quad 134 X0Y28-X0Y31
CMAC X0Y3
HP I/O Bank 74 HD I/O Bank 94 GTH Quad 234
Q
X0Y40-X0Y43
GTY Quad 133 X0Y24-X0Y27
ILKN X0Y2
HP I/O Bank 73 HD I/O Bank 93 GTH Quad 233
R
P
X0Y36-X0Y39
GTY Quad 132 X0Y20-X0Y23
CMAC X0Y2
HP I/O Bank 72 S
ILKN X1Y1
GTH Quad 232 X0Y32-X0Y35
GTY Quad 131 X0Y16-X0Y19
PCIE4 X0Y3
HP I/O Bank 71 HD I/O Bank 91 GTH Quad 231
T
O
X0Y28-X0Y31
GTY Quad 130 X0Y12-X0Y15
CMAC X0Y1
HP I/O Bank 70 HD I/O Bank 90 GTH Quad 230
U
N
X0Y24-X0Y27
GTY Quad 129 X0Y8-X0Y11
(RCAL)
ILKN X0Y0
HP I/O Bank 69 V
ILKN X1Y0
GTH Quad 229 X0Y20-X0Y23
GTY Quad 128 X0Y4-X0Y7
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y2
CMAC X0Y0
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
PS CONFIG 503 PS MIO 500
HP I/O Bank 68 W
HP I/O Bank 67 X
HP I/O Bank 66 E
HP I/O Bank 65 C
HP I/O Bank 64 D
PCIE4 X1Y2
PCIE4 X1Y1
SYSMON Configuration
Configuration
PCIE4 X1Y0 (tandem)
GTH Quad 228 X0Y16-X0Y19
GTH Quad 227 X0Y12-X0Y15
D [R] GTH Quad 226 X0Y8-X0Y11 C [R] (RCAL) GTH Quad 225
X0Y4-X0Y7 B [R]
GTH Quad 224 X0Y0-X0Y3 A [R]
X15141-071417
Figure 1-25: XCZU17 and XCZU19 Banks in FFVB1517 Package and XQZU19 Banks in FFRB1517 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
63
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-26
GTY Quad 134 X0Y28-X0Y31
CMAC X0Y3
HD I/O Bank 94 GTH Quad 234
HP I/O Bank 74
Q
X0Y40-X0Y43
GTY Quad 133 X0Y24-X0Y27
ILKN X0Y2
HD I/O Bank 93 GTH Quad 233
HP I/O Bank 73
P
X0Y36-X0Y39
GTY Quad 132 X0Y20-X0Y23
CMAC X0Y2
HP I/O Bank 72
ILKN X1Y1
GTH Quad 232 X0Y32-X0Y35
GTY Quad 131 X0Y16-X0Y19
M [L]
GTY Quad 130 X0Y12-X0Y15
L [L] GTY Quad 129 X0Y8-X0Y11 K [L] (RCAL) GTY Quad 128
X0Y4-X0Y7 J [L]
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y3
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y2
CMAC X0Y0
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
PS CONFIG 503 PS MIO 500
HP I/O Bank 71 R
HP I/O Bank 70 S
HP I/O Bank 69 T
HP I/O Bank 68 U
HP I/O Bank 67 F
HP I/O Bank 66 E
HP I/O Bank 65 C
HP I/O Bank 64 D
HD I/O Bank 91 O
HD I/O Bank 90 N
ILKN X1Y0
PCIE4 X1Y2
PCIE4 X1Y1
SYSMON Configuration
Configuration
PCIE4 X1Y0 (tandem)
GTH Quad 231 X0Y28-X0Y31
H [RN] GTH Quad 230 X0Y24-X0Y27
G [RN] GTH Quad 229 X0Y20-X0Y23
F [RN] GTH Quad 228 X0Y16-X0Y19
E [RN] GTH Quad 227 X0Y12-X0Y15
D [RS] GTH Quad 226 X0Y8-X0Y11 C [RS] (RCAL) GTH Quad 225
X0Y4-X0Y7 B [RS]
GTH Quad 224 X0Y0-X0Y3 A [RS]
X15142-071417
Figure 1-26: XCZU17 and XCZU19 Banks in FFVC1760 Package and XQZU19 Banks in FFRC1760 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
64
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-27
GTY Quad 134 X0Y28-X0Y31
R [L] GTY Quad 133 X0Y24-X0Y27
Q [L] GTY Quad 132 X0Y20-X0Y23
P [L] GTY Quad 131 X0Y16-X0Y19
O [L] GTY Quad 130 X0Y12-X0Y15
N [L] GTY Quad 129 X0Y8-X0Y11 M [L] (RCAL) GTY Quad 128
X0Y4-X0Y7 L [L]
GTY Quad 127 X0Y0-X0Y3
CMAC X0Y3
ILKN X0Y2
CMAC X0Y2
PCIE4 X0Y3
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y2
CMAC X0Y0
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
PS CONFIG 503 PS MIO 500
HP I/O Bank 74
HP I/O Bank 73
HP I/O Bank 72
HP I/O Bank 71 P
HP I/O Bank 70 Q
HP I/O Bank 69 R
HP I/O Bank 68
HP I/O Bank 67
HP I/O Bank 66 D
HP I/O Bank 65 C
HP I/O Bank 64
HD I/O Bank 94
HD I/O Bank 93
ILKN X1Y1
HD I/O Bank 91 O
HD I/O Bank 90 N
ILKN X1Y0
PCIE4 X1Y2
PCIE4 X1Y1
SYSMON Configuration
Configuration
PCIE4 X1Y0 (tandem)
GTH Quad 234 X0Y40-X0Y43
K [RN] GTH Quad 233 X0Y36-X0Y39
J [RN] GTH Quad 232 X0Y32-X0Y35
I [RN] GTH Quad 231 X0Y28-X0Y31
H [RN] GTH Quad 230 X0Y24-X0Y27
G [RN] GTH Quad 229 X0Y20-X0Y23
F [RS] GTH Quad 228 X0Y16-X0Y19
E [RS] GTH Quad 227 X0Y12-X0Y15
D [RS] GTH Quad 226 X0Y8-X0Y11 C [RS] (RCAL) GTH Quad 225
X0Y4-X0Y7 B [RS]
GTH Quad 224 X0Y0-X0Y3 A [RS]
X15143-071417
Figure 1-27: XCZU17 and XCZU19 Banks in FFVD1760 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
65
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-28
GTY Quad 134 X0Y28-X0Y31
GTY Quad 133 X0Y24-X0Y27
GTY Quad 132 X0Y20-X0Y23
GTY Quad 131 X0Y16-X0Y19
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
GTY Quad 127 X0Y0-X0Y3
CMAC X0Y3
ILKN X0Y2
CMAC X0Y2
PCIE4 X0Y3
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y2
CMAC X0Y0
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
PS CONFIG 503 PS MIO 500
HP I/O Bank 74 R
HP I/O Bank 73 S
HP I/O Bank 72 T
HP I/O Bank 71 U
HP I/O Bank 70 V
HP I/O Bank 69 W
HP I/O Bank 68 X
HP I/O Bank 67 F
HP I/O Bank 66 E
HP I/O Bank 65 C
HP I/O Bank 64 D
HD I/O Bank 94 Q
HD I/O Bank 93 P
ILKN X1Y1
HD I/O Bank 91 O
HD I/O Bank 90 N
ILKN X1Y0
PCIE4 X1Y2
PCIE4 X1Y1
SYSMON Configuration
Configuration
PCIE4 X1Y0 (tandem)
GTH Quad 234 X0Y40-X0Y43
K [RN] GTH Quad 233 X0Y36-X0Y39
J [RN] GTH Quad 232 X0Y32-X0Y35
I [RN] GTH Quad 231 X0Y28-X0Y31
H [RN] GTH Quad 230 X0Y24-X0Y27
G [RN] GTH Quad 229 X0Y20-X0Y23
F [RS] GTH Quad 228 X0Y16-X0Y19
E [RS] GTH Quad 227 X0Y12-X0Y15
D [RS] GTH Quad 226 X0Y8-X0Y11 C [RS] (RCAL) GTH Quad 225
X0Y4-X0Y7 B [RS]
GTH Quad 224 X0Y0-X0Y3 A [RS]
X15144-071417
Figure 1-28: XCZU17 and XCZU19 Banks in FFVE1924 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
66
Send Feedback
Chapter 1: Packaging Overview
XCZU21DR and XQZU21DR Bank Diagram Overview
X-Ref Target - Figure 1-29
GTY Quad 131 X0Y16-X0Y19
PCIE4 X0Y1
SD-FEC
HP I/O Bank 71 HD I/O Bank 91
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
SD-FEC SD-FEC SD-FEC
HP I/O Bank 70 HD I/O Bank 90 HP I/O Bank 69 HD I/O Bank 89 HP I/O Bank 68 HD I/O Bank 88
GTY Quad 127 X0Y0-X0Y3
CMAC X0Y0
SD-FEC
HP I/O Bank 67 HD I/O Bank 87
PS GTR 505
PS MIO 502
SD-FEC
HP I/O Bank 66
SYSMON Configuration
PS DDR 504
PS MIO 501
SD-FEC
HP I/O Bank 65 Configuration
PS CONFIG 503 PS MIO 500
SD-FEC
HP I/O Bank 64 HD I/O Bank 84
Figure 1-29: XCZU21DR and XQZU21DR Banks
X19543-101518
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
67
Send Feedback
Chapter 1: Packaging Overview
Bank Diagram by Package for XCZU21DR and XQZU21DR
X-Ref Target - Figure 1-30
GTY Quad 131 X0Y16-X0Y19
D [L] GTY Quad 130 X0Y12-X0Y15
C [L] GTY Quad 129 X0Y8-X0Y11
B [L] (RCAL) GTY Quad 128
X0Y4-X0Y7 A [L]
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
SD-FEC
HP I/O Bank 71 HD I/O Bank 91
SD-FEC SD-FEC SD-FEC SD-FEC SD-FEC SD-FEC
HP I/O Bank 70 HD I/O Bank 90
HD I/O Bank 89 HP I/O Bank 69
P
HP I/O Bank 68 HD I/O Bank 88
F
O
HP I/O Bank 67 HD I/O Bank 87
E
N
HP I/O Bank 66 D
SYSMON Configuration
HP I/O Bank 65 C
Configuration
PS CONFIG 503 PS MIO 500
SD-FEC
HP I/O Bank 64 HD I/O Bank 84
X19545-014001252108
Figure 1-30: XCZU21DR Banks in FFVD1156 Package and XQZU21DR Banks in FFRD1156 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
68
Send Feedback
Chapter 1: Packaging Overview
XCZU25DR Bank Diagram Overview
X-Ref Target - Figure 1-31
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
ILKN X0Y0
PCIE4 X0Y0
HP I/O Bank 69 HD I/O Bank 89 DAC Bank 229 HP I/O Bank 68 HD I/O Bank 88 DAC Bank 228
GTY Quad 127 X0Y0-X0Y3
CMAC X0Y0
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
PS GTR 505
PS MIO 502
HP I/O Bank 66
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
HP I/O Bank 65 Configuration ADC Bank 225
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X19546-042720
Figure 1-31: XCZU25DR Banks
Bank Diagram by Package for XCZU25DR
X-Ref Target - Figure 1-32
GTY Quad 129 X0Y8-X0Y11 B [L] (RCAL) GTY Quad 128 X0Y4-X0Y7
A [L]
GTY Quad 127 X0Y0-X0Y3
PS GTR 505
PS DDR 504
ILKN X0Y0 PCIE4 X0Y0 CMAC X0Y0
PS MIO 502
PS MIO 501
HP I/O Bank 69
HD I/O Bank 89 O
DAC Bank 229
HP I/O Bank 68
HD I/O Bank 88 N
DAC Bank 228
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
HP I/O Bank 66 D
HP I/O Bank 65 C
SYSMON Configuration
Configuration
ADC Bank 226 ADC Bank 225
PS CONFIG 503 PS MIO 500 HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X19547-042720
Figure 1-32: XCZU25DR Banks in FFVE1156 and FSVE1156 Packages
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
69
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-33
GTY Quad 129 X0Y8-X0Y11 B [L] (RCAL) GTY Quad 128 X0Y4-X0Y7
A [L]
GTY Quad 127 X0Y0-X0Y3
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
HP I/O Bank 69 S
HD I/O Bank 89
DAC Bank 229
HP I/O Bank 68 R
HD I/O Bank 88
DAC Bank 228
HP I/O Bank 67 Q
HD I/O Bank 87 N
ADC Bank 227
PS GTR 505
PS MIO 502
HP I/O Bank 66 D
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
HP I/O Bank 65 C
Configuration
ADC Bank 225
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 B (Partial)
HD I/O Bank 84 A
ADC Bank 224
X19548-040720
Figure 1-33: XCZU25DR Banks in FFVG1517 and FSVG1517 Packages
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
70
Send Feedback
Chapter 1: Packaging Overview
XCZU27DR Bank Diagram Overview
X-Ref Target - Figure 1-34
GTY Quad 131 X0Y16-X0Y19
PCIE4 X0Y1
HP I/O Bank 71 HD I/O Bank 91
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
HP I/O Bank 70 HD I/O Bank 90 HP I/O Bank 69 HD I/O Bank 89 DAC Bank 229 HP I/O Bank 68 HD I/O Bank 88 DAC Bank 228
GTY Quad 127 X0Y0-X0Y3
CMAC X0Y0
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
PS GTR 505
PS MIO 502
HP I/O Bank 66
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501 HP I/O Bank 65 Configuration ADC Bank 225
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
Figure 1-34: XCZU27DR Banks
X19549-040320
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
71
Send Feedback
Chapter 1: Packaging Overview
Bank Diagram by Package for XCZU27DR
X-Ref Target - Figure 1-35
GTY Quad 131 X0Y16-X0Y19
GTY Quad 130 X0Y12-X0Y15 GTY Quad 129 X0Y8-X0Y11 B [L] (RCAL) GTY Quad 128 X0Y4-X0Y7
A [L] GTY Quad 127
X0Y0-X0Y3
PS GTR 505
PS DDR 504
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
PS MIO 502
PS MIO 501
HP I/O Bank 71 HD I/O Bank 91
HP I/O Bank 70 HD I/O Bank 90
HP I/O Bank 69
HD I/O Bank 89 O
DAC Bank 229
HP I/O Bank 68
HD I/O Bank 88 N
DAC Bank 228
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
HP I/O Bank 66 D
HP I/O Bank 65 C
SYSMON Configuration
Configuration
ADC Bank 226 ADC Bank 225
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X19550-040320
Figure 1-35: XCZU27DR Banks in FFVE1156 and FSVE1156 Packages
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
72
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-36
GTY Quad 131 X0Y16-X0Y19
D [L] GTY Quad 130 X0Y12-X0Y15
C [L] GTY Quad 129 X0Y8-X0Y11 B [L] (RCAL) GTY Quad 128
X0Y4-X0Y7 A [L]
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
HP I/O Bank 71 HD I/O Bank 91
HP I/O Bank 70 HD I/O Bank 90
HP I/O Bank 69 S
HD I/O Bank 89
DAC Bank 229
HP I/O Bank 68 R
HD I/O Bank 88
DAC Bank 228
HP I/O Bank 67 Q
HD I/O Bank 87 N
ADC Bank 227
PS GTR 505
PS MIO 502
HP I/O Bank 66 D
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
HP I/O Bank 65 C
Configuration
ADC Bank 225
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 B (Partial)
HD I/O Bank 84 A
ADC Bank 224
X19551-040320
Figure 1-36: XCZU27DR Banks in FFVG1517 and FSVG1517 Packages
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
73
Send Feedback
Chapter 1: Packaging Overview
XCZU28DR and XQZU28DR Bank Diagram Overview
X-Ref Target - Figure 1-37
GTY Quad 131 X0Y16-X0Y19
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
PS GTR 505
PS MIO 502
SD-FEC
HP I/O Bank 71 HD I/O Bank 91
SD-FEC
HP I/O Bank 70 HD I/O Bank 90
SD-FEC
HP I/O Bank 69 HD I/O Bank 89 DAC Bank 229
SD-FEC
HP I/O Bank 68 HD I/O Bank 88 DAC Bank 228
SD-FEC SD-FEC
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
HP I/O Bank 66
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
SD-FEC
HP I/O Bank 65 Configuration ADC Bank 225
PS CONFIG 503 PS MIO 500
SD-FEC
HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
Figure 1-37: XCZU28DR and XQZU28DR Banks
X19552-040320
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
74
Send Feedback
Chapter 1: Packaging Overview
Bank Diagram by Package for XCZU28DR and XQZU28DR
X-Ref Target - Figure 1-38
GTY Quad 131 X0Y16-X0Y19
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11 B [L] (RCAL) GTY Quad 128 X0Y4-X0Y7
A [L]
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
SD-FEC
HP I/O Bank 71 HD I/O Bank 91
SD-FEC SD-FEC SD-FEC SD-FEC SD-FEC SD-FEC
HP I/O Bank 70 HD I/O Bank 90
HP I/O Bank 69
HD I/O Bank 89 O
DAC Bank 229
HP I/O Bank 68
HD I/O Bank 88 N
DAC Bank 228
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
HP I/O Bank 66 D
HP I/O Bank 65 C
SYSMON Configuration
Configuration
ADC Bank 226 ADC Bank 225
PS CONFIG 503 PS MIO 500
SD-FEC
HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
Figure 1-38: XCZU28DR Banks in FFVE1156 and FSVE1156 Packages and XQZU28DR in FFRE1156 Package
X19553-042720
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
75
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-39
GTY Quad 131 X0Y16-X0Y19
D [L] GTY Quad 130 X0Y12-X0Y15
C [L] GTY Quad 129 X0Y8-X0Y11 B [L] (RCAL) GTY Quad 128
X0Y4-X0Y7 A [L]
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
SD-FEC
HP I/O Bank 71 HD I/O Bank 91
SD-FEC SD-FEC SD-FEC SD-FEC
HP I/O Bank 70 HD I/O Bank 90
HP I/O Bank 69 S
HD I/O Bank 89
DAC Bank 229
HP I/O Bank 68 R
HD I/O Bank 88
DAC Bank 228
HP I/O Bank 67 Q
HD I/O Bank 87 N
ADC Bank 227
PS GTR 505
PS MIO 502
SD-FEC
HP I/O Bank 66 D
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
SD-FEC
HP I/O Bank 65 C
Configuration
ADC Bank 225
PS CONFIG 503 PS MIO 500
SD-FEC
HP I/O Bank 64 B (Partial)
HD I/O Bank 84 A
ADC Bank 224
Figure 1-39: XCZU28DR Banks in FFVG1517 and FSVG1517 Packages and XQZU28DR in FFRG1517 Package
X19554-042720
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
76
Send Feedback
Chapter 1: Packaging Overview
XCZU29DR, XQZU29DR, and XCZU39DR Bank Diagram Overview
X-Ref Target - Figure 1-40
GTY Quad 131 X0Y16-X0Y19
PCIE4 X0Y1
HP I/O Bank 71 HD I/O Bank 91 DAC Bank 231
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
HP I/O Bank 70 HD I/O Bank 90 DAC Bank 230 HP I/O Bank 69 HD I/O Bank 89 DAC Bank 229 HP I/O Bank 68 HD I/O Bank 88 DAC Bank 228
GTY Quad 127 X0Y0-X0Y3
CMAC X0Y0
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
PS GTR 505
PS MIO 502
HP I/O Bank 66
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
HP I/O Bank 65 Configuration ADC Bank 225
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
Figure 1-40: XCZU29DR, XQZU29DR, and XCZU39DR Banks
X19555-040620
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
77
Send Feedback
Chapter 1: Packaging Overview
Bank Diagram by Package for XCZU29DR, XQZU29DR, and XCZU39DR
X-Ref Target - Figure 1-41
GTY Quad 131 X0Y16-X0Y19
D [L] GTY Quad 130 X0Y12-X0Y15
C [L] GTY Quad 129 X0Y8-X0Y11 B [L] (RCAL) GTY Quad 128
X0Y4-X0Y7 A [L]
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
HP I/O Bank 71 HD I/O Bank 91 DAC Bank 231
HP I/O Bank 70 HD I/O Bank 90 DAC Bank 230
HP I/O Bank 69 T
HD I/O Bank 89 P
DAC Bank 229
HP I/O Bank 68 S
HD I/O Bank 88 O
DAC Bank 228
HP I/O Bank 67 R
HD I/O Bank 87 N
ADC Bank 227
PS GTR 505
PS MIO 502
HP I/O Bank 66 D
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
HP I/O Bank 65 C
Configuration
ADC Bank 225
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 B
HD I/O Bank 84 A
ADC Bank 224
X19556-042620
Figure 1-41: XCZU29DR and XCZU39DR Banks in FFVF1760 and FSVF1760 Packages and XQZU29DR Banks in FFRF1760 Package
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
78
Send Feedback
Chapter 1: Packaging Overview
XCZU43DR Bank Diagram Overview
X-Ref Target - Figure 1-42
GTY Quad 131 X0Y16-X0Y19
PCIE4 X0Y1
HP I/O Bank 71
HD I/O Bank 91
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
HP I/O Bank 70
HD I/O Bank 90
HP I/O Bank 69
HD I/O Bank 89
HP I/O Bank 68
HD I/O Bank 88
GTY Quad 127 X0Y0-X0Y3
CMAC X0Y0
HP I/O Bank 67
HD I/O Bank 87
PS GTR 505
PS MIO 502
HP I/O Bank 66
SYSMON Configuration
DAC Bank 231 DAC Bank 230 DAC Bank 229 DAC Bank 228 ADC Bank 227 ADC Bank 226
PS DDR 504
PS MIO 501
HP I/O Bank 65
Configuration
ADC Bank 225
PS CONFIG 503
PS MIO 500
HP I/O Bank 64
HD I/O Bank 84
Figure 1-42: XCZU43DR Banks
ADC Bank 224
X23814-042620
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
79
Send Feedback
Bank Diagram by Package for XCZU43DR
X-Ref Target - Figure 1-43
GTY Quad 131 X0Y16-X0Y19
PCIE4 X0Y1
HP I/O Bank 71
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11 B [L] (RCAL) GTY Quad 128 X0Y4-X0Y7
A [L]
GTY Quad 127 X0Y0-X0Y3
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
HP I/O Bank 70 HP I/O Bank 69 HP I/O Bank 68 HP I/O Bank 67
PS GTR 505
PS MIO 502
HP I/O Bank 66 D
PS DDR 504
PS MIO 501
HP I/O Bank 65 C
Chapter 1: Packaging Overview
HD I/O Bank 91
DAC Bank 231
HD I/O Bank 90
HD I/O Bank 89 O
HD I/O Bank 88 N
HD I/O Bank 87
SYSMON Configuration
Configuration
DAC Bank 230 DAC Bank 229 DAC Bank 228 ADC Bank 227 ADC Bank 226 ADC Bank 225
PS CONFIG 503
PS MIO 500
HP I/O Bank 64
HD I/O Bank 84
ADC Bank 224
Figure 1-43: XCZU43DR Banks in FFVE1156 Packages
X23816-042720
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
80
Send Feedback
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-44
GTY Quad 131 X0Y16-X0Y19
D [L] GTY Quad 130 X0Y12-X0Y15
C [L] GTY Quad 129 X0Y8-X0Y11
B [L] (RCAL) GTY Quad 128
X0Y4-X0Y7 A [L]
GTY Quad 127 X0Y0-X0Y3
PS GTR 505
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
PS MIO 502
PS DDR 504
PS MIO 501
PS CONFIG 503
PS MIO 500
HP I/O Bank 71
HD I/O Bank 91
HP I/O Bank 70
HD I/O Bank 90
HP I/O Bank 69 S
HP I/O Bank 68 R
HP I/O Bank 67 Q
HP I/O Bank 66 D
HP I/O Bank 65 C
HP I/O Bank 64 B (Partial)
HD I/O Bank 89
HD I/O Bank 88
HD I/O Bank 87 N
SYSMON Configuration
Configuration
HD I/O Bank 84 A
Figure 1-44: XCZU43DR Banks in FFVG1517 Packages
DAC Bank 231 DAC Bank 230 DAC Bank 229 DAC Bank 228 ADC Bank 227 ADC Bank 226 ADC Bank 225 ADC Bank 224
X23817-042720
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
81
Send Feedback
Chapter 1: Packaging Overview
XCZU46DR Bank Diagram Overview
X-Ref Target - Figure 1-45
GTY Quad 131 X0Y16-X0Y19
PCIE4 X0Y1
SD-FEC
HP I/O Bank 71 HD I/O Bank 91 DAC Bank 231
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
SD-FEC SD-FEC SD-FEC
HP I/O Bank 70 HD I/O Bank 90 DAC Bank 230 HP I/O Bank 69 HD I/O Bank 89 DAC Bank 229 HP I/O Bank 68 HD I/O Bank 88 DAC Bank 228
GTY Quad 127 X0Y0-X0Y3
CMAC X0Y0
SD-FEC
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
PS GTR 505
PS MIO 502
SD-FEC
HP I/O Bank 66
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
SD-FEC
HP I/O Bank 65 Configuration ADC Bank 225
PS CONFIG 503 PS MIO 500
SD-FEC
HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
Figure 1-45: XCZU46DR Banks
X23818-042720
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
82
Send Feedback
Chapter 1: Packaging Overview
Bank Diagram by Package for XCZU46DR
X-Ref Target - Figure 1-46
GTY Quad 131 X0Y16-X0Y19
D [L]
GTY Quad 130 X0Y12-X0Y15
C [L]
GTY Quad 129 X0Y8-X0Y11 B [L] (RCAL)
GTY Quad 128 X0Y4-X0Y7 A [L]
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
SD-FEC SD-FEC SD-FEC SD-FEC SD-FEC
HP I/O Bank 71 S
HD I/O Bank 91 P
DAC Bank 231
HP I/O Bank 70 T
HD I/O Bank 90 O
DAC Bank 230
HP I/O Bank 69 R
HD I/O Bank 89
DAC Bank 229
HP I/O Bank 68 HD I/O Bank 88 DAC Bank 228
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
PS GTR 505
PS MIO 502
SD-FEC
HP I/O Bank 66 D
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
SD-FEC
HP I/O Bank 65 C
Configuration
ADC Bank 225
PS CONFIG 503
PS MIO 500
SD-FEC
HP I/O Bank 64 B
HD I/O Bank 84
ADC Bank 224
Figure 1-46: XCZU46DR Banks in FFVH1760 Packages
X238198-042720
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
83
Send Feedback
Chapter 1: Packaging Overview
XCZU47DR Bank Diagram Overview
X-Ref Target - Figure 1-47
GTY Quad 131 X0Y16-X0Y19
PCIE4 X0Y1
HP I/O Bank 71 HD I/O Bank 91 DAC Bank 231
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
HP I/O Bank 70 HD I/O Bank 90 DAC Bank 230 HP I/O Bank 69 HD I/O Bank 89 DAC Bank 229 HP I/O Bank 68 HD I/O Bank 88 DAC Bank 228
GTY Quad 127 X0Y0-X0Y3
CMAC X0Y0
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
PS GTR 505
PS MIO 502
HP I/O Bank 66
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
HP I/O Bank 65
Configuration
ADC Bank 225
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
Figure 1-47: XCZU47DR Banks
X23820-042720
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
84
Send Feedback
Chapter 1: Packaging Overview
Bank Diagram by Package for XCZU47DR
X-Ref Target - Figure 1-48
GTY Quad 131 X0Y16-X0Y19
GTY Quad 130 X0Y12-X0Y15 GTY Quad 129 X0Y8-X0Y11 B [L] (RCAL) GTY Quad 128 X0Y4-X0Y7
A [L] GTY Quad 127
X0Y0-X0Y3
PS GTR 505
PS DDR 504
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
PS MIO 502
PS MIO 501
HP I/O Bank 71 HD I/O Bank 91 DAC Bank 231
HP I/O Bank 70 HD I/O Bank 90 DAC Bank 230
HP I/O Bank 69
HD I/O Bank 89 O
DAC Bank 229
HP I/O Bank 68
HD I/O Bank 88 N
DAC Bank 228
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
HP I/O Bank 66 D
HP I/O Bank 65 C
SYSMON Configuration
Configuration
ADC Bank 226 ADC Bank 225
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
Figure 1-48: XCZU47DR Banks in FFVE1156 Packages
X23821-042720
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
85
Send Feedback
X-Ref Target - Figure 1-49
Chapter 1: Packaging Overview
GTY Quad 131 X0Y16-X0Y19
D [L] GTY Quad 130 X0Y12-X0Y15
C [L] GTY Quad 129 X0Y8-X0Y11
B [L] (RCAL) GTY Quad 128
X0Y4-X0Y7 A [L]
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
HP I/O Bank 71 HD I/O Bank 91 DAC Bank 231
HP I/O Bank 70 HD I/O Bank 90 DAC Bank 230
HP I/O Bank 69 S
HD I/O Bank 89
DAC Bank 229
HP I/O Bank 68 R
HD I/O Bank 88
DAC Bank 228
HP I/O Bank 67 Q
HD I/O Bank 87 N
ADC Bank 227
PS GTR 505
PS MIO 502
HP I/O Bank 66 D
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
HP I/O Bank 65 C
Configuration
ADC Bank 225
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 B (Partial)
HD I/O Bank 84 A
ADC Bank 224
Figure 1-49: XCZU47DR Banks in FFVG1517 Packages
X23822-042720
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
86
Send Feedback
Chapter 1: Packaging Overview
XCZU48DR Bank Diagram Overview
X-Ref Target - Figure 1-50
GTY Quad 131 X0Y16-X0Y19
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11
(RCAL)
GTY Quad 128 X0Y4-X0Y7
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
PS GTR 505 PS MIO 502
SD-FEC
HP I/O Bank 71 HD I/O Bank 91 DAC Bank 231
SD-FEC
HP I/O Bank 70 HD I/O Bank 90 DAC Bank 230
SD-FEC
HP I/O Bank 69 HD I/O Bank 89 DAC Bank 229
SD-FEC
HP I/O Bank 68 HD I/O Bank 88 DAC Bank 228
SD-FEC SD-FEC
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
HP I/O Bank 66
SYSMON Configuration
ADC Bank 226
PS DDR 504 PS MIO 501
SD-FEC
HP I/O Bank 65 Configuration ADC Bank 225
PS CONFIG 503 PS MIO 500
SD-FEC
HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
Figure 1-50: XCZU48DR Banks
X23823-042720
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
87
Send Feedback
Chapter 1: Packaging Overview
Bank Diagram by Package for XCZU48DR
X-Ref Target - Figure 1-51
GTY Quad 131 X0Y16-X0Y19
GTY Quad 130 X0Y12-X0Y15
GTY Quad 129 X0Y8-X0Y11 B [L] (RCAL) GTY Quad 128 X0Y4-X0Y7
A [L]
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
PS GTR 505
PS MIO 502
PS DDR 504
PS MIO 501
FEC FEC FEC FEC FEC FEC FEC
HP I/O Bank 71 HD I/O Bank 91 DAC Bank 231
HP I/O Bank 70 HD I/O Bank 90 DAC Bank 230
HP I/O Bank 69 HD I/O Bank 89 DAC Bank 229 O
HP I/O Bank 68 HD I/O Bank 88 DAC Bank 228 N
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
HP I/O Bank 66
SYSMON
D
Configuration
HP I/O Bank 65 Configuration C
ADC Bank 226 ADC Bank 225
PS CONFIG 503 PS MIO 500
FEC
HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X-Ref Target - Figure 1-52
Figure 1-51: XCZU48DR Banks in FFVE1156 Packages
X23824-042720
GTY Quad 131 X0Y16-X0Y19
D [L] GTY Quad 130 X0Y12-X0Y15
C [L] GTY Quad 129 X0Y8-X0Y11
B [L] (RCAL) GTY Quad 128
X0Y4-X0Y7 A [L]
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
SD-FEC
HP I/O Bank 71 HD I/O Bank 91 DAC Bank 231
SD-FEC SD-FEC SD-FEC SD-FEC
HP I/O Bank 70 HD I/O Bank 90 DAC Bank 230
HP I/O Bank 69
S
HD I/O Bank 89 DAC Bank 229
HP I/O Bank 68 HD I/O Bank 88 DAC Bank 228 R
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
Q
N
PS GTR 505
PS MIO 502
SD-FEC
HP I/O Bank 66 D
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
SD-FEC
HP I/O Bank 65 C
Configuration
ADC Bank 225
PS CONFIG 503 PS MIO 500
SD-FEC
HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
B (Partial)
A
X23825-042720
Figure 1-52: XCZU48DR Banks in FFVG1517 Packages
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
88
Send Feedback
Chapter 1: Packaging Overview
XCZU49DR Bank Diagram Overview
X-Ref Target - Figure 1-53
GTY Quad 131 X0Y16-X0Y19
GTY Quad 130 X0Y12-X0Y15 GTY Quad 129 X0Y8-X0Y11
(RCAL) GTY Quad 128
X0Y4-X0Y7
GTY Quad 127 X0Y0-X0Y3
PS GTR 505
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
PS MIO 502
HP I/O Bank 71 HD I/O Bank 91 DAC Bank 231
HP I/O Bank 70 HD I/O Bank 90 DAC Bank 230
HP I/O Bank 69 HD I/O Bank 89 DAC Bank 229
HP I/O Bank 68 HD I/O Bank 88 DAC Bank 228
HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
HP I/O Bank 66
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
HP I/O Bank 65 Configuration
ADC Bank 225
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
Figure 1-53: XCZU49DR Banks
X23826-042720
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
89
Send Feedback
Chapter 1: Packaging Overview
Bank Diagram by Package for XCZU49DR
X-Ref Target - Figure 1-54
GTY Quad 131 X0Y16-X0Y19
D [L] GTY Quad 130 X0Y12-X0Y15
C [L] GTY Quad 129 X0Y8-X0Y11
B [L] (RCAL) GTY Quad 128
X0Y4-X0Y7 A [L]
GTY Quad 127 X0Y0-X0Y3
PCIE4 X0Y1
CMAC X0Y1
ILKN X0Y0
PCIE4 X0Y0
CMAC X0Y0
HP I/O Bank 71 HD I/O Bank 91 DAC Bank 231
HP I/O Bank 70 HD I/O Bank 90 DAC Bank 230
HP I/O Bank 69 T
HD I/O Bank 89 P
DAC Bank 229
HP I/O Bank 68 S
HD I/O Bank 88 O
DAC Bank 228
HP I/O Bank 67 R
HD I/O Bank 87 N
ADC Bank 227
PS GTR 505
PS MIO 502
HP I/O Bank 66 D
SYSMON Configuration
ADC Bank 226
PS DDR 504
PS MIO 501
HP I/O Bank 65 C
Configuration ADC Bank 225
PS CONFIG 503 PS MIO 500
HP I/O Bank 64 B
HD I/O Bank 84 A
ADC Bank 224
Figure 1-54: XCZU49DR Banks in FFVF1760 Packages
X23815-042720
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
90
Send Feedback
Chapter 2
PS Memory Interface Pin Guidelines
Introduction to PS Memory Interface Pins
This chapter shows what is needed to support the broad requirements of various memory interfaces using the Zynq� UltraScale+TM device DDR subsystem. It covers DDR3/3L, DDR4, LPDDR4, and LPDDR3.
IMPORTANT: SBVA484 and SFVA625 packages only support 32-bit data buses for the PS DDR controller. The Zynq UltraScale+ device DDR subsystem can only be configured for 32-bit or 32-bit plus ECC DDR3/DDR4/LPDDR4 designs when using these packages.
DDR3/3L Guidelines
DDR3/3L Pin Rules
The DDR3/3L pin rules are for single and dual-rank memory interfaces. � All unused DDR pins can be left unconnected. For example, in a 64-bit interface without
ECC, the PS_DDR_DQ64 to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, and PS_DDR_DM8 pins can be left unconnected. � Connect the PS_DDR_ZQ pin to GND using a 240 resistor. There should be separate 240 resistors at the MPSoC or RFSoC and at the DRAM.
DDR3/3L Pin Swapping Restrictions
� Address/command/control bits cannot be swapped. � DQ byte lane swapping is allowed. A byte lane includes any signals associated with the
aligned 8-bits of DQ, such as DM, DQS, DQS_N, and DQ signals. � DQ bits swapping within a byte lane is allowed.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
91
Send Feedback
Chapter 2: PS Memory Interface Pin Guidelines
DDR3/3L Pinout Example for Supported Configurations
Table 2-1 shows a pinout example for the DDR3/3L supported configurations. For termination details, see the UltraScale Architecture PCB Design Guide [Ref 14]. When not being used for a memory interface, all pins should be left unconnected with the exception of VCCO_PSDDR and VCC_PSDDR_PLL, which should be tied to GND.
IMPORTANT: VCC_PSINTFP must be tied to VCC_PSINTFP_DDR. This requirement is in Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics [Ref 8] and Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics [Ref 9], where both VCC_PSINTFP and VCC_PSINTFP_DDR must be connected to the same supply and thus both must be powered to avoid MBIST failure.
Table 2-1: DDR3/3L Supported Pinout Configurations
Pin Name
VCCO_PSDDR(1)
PS_DDR_A0 to PS_DDR_A15
PS_DDR_A16 PS_DDR_A17 PS_DDR_ACT_N PS_DDR_ALERT_N
PS_DDR_BA0 PS_DDR_BA1 PS_DDR_BG0 PS_DDR_BG1
PS_DDR_CK_N0 PS_DDR_CK_N1
PS_DDR_CK0 PS_DDR_CK1
PS_DDR_CKE0 PS_DDR_CKE1
PS_DDR_CS_N0
DDR3/3L 64-bit 1Rank
Set to 1.5V (1.35V for DDR3L) Connect A0 to PS_DDR_A0, A1 to PS_DDR_A1, and so on. WE# CAS# RAS# Can be left unconnected. BA[0] BA[1] BA[2] Can be left unconnected. CK# Can be left unconnected. CK. Can be left unconnected. CKE Can be left unconnected. CS#
DDR3/3L 64-bit 2Rank
Set to 1.5V (1.35V for DDR3L) Connect A0 to PS_DDR_A0, A1 to PS_DDR_A1, and so on. WE# CAS# RAS# Can be left unconnected. BA[0] BA[1] BA[2] Can be left unconnected. CK#[0] CK#[1]
CK[0] CK[1]
CKE[0] CKE[1]
CS#[0]
DDR3/3L 32-bit 1Rank
Set to 1.5V (1.35V for DDR3L) Connect A0 to PS_DDR_A0, A1 to PS_DDR_A1, and so on. WE# CAS# RAS# Can be left unconnected. BA[0] BA[1] BA[2] Can be left unconnected. CK# Can be left unconnected. CK. Can be left unconnected. CKE Can be left unconnected. CS#
DDR3/3L 32-bit 2Rank
Set to 1.5V (1.35V for DDR3L) Connect A0 to PS_DDR_A0, A1 to PS_DDR_A1, and so on. WE# CAS# RAS# Can be left unconnected. BA[0] BA[1] BA[2] Can be left unconnected. CK#[0] CK#[1]
CK[0] CK[1]
CKE[0] CKE[1]
CS#[0]
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
92
Send Feedback
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-1: DDR3/3L Supported Pinout Configurations (Cont'd)
Pin Name
PS_DDR_CS_N1 PS_DDR_DM0 to PS_DDR_DM3
DDR3/3L 64-bit 1Rank
Can be left unconnected.
Connect DM0 to PS_DDR_DM0, DM1 to PS_DDR_DM1, and so on.
DDR3/3L 64-bit 2Rank
CS#[1]
Connect DM0 to PS_DDR_DM0, DM1 to PS_DDR_DM1, and so on.
DDR3/3L 32-bit 1Rank
Can be left unconnected.
Connect DM0 to PS_DDR_DM0, DM1 to PS_DDR_DM1, and so on.
PS_DDR_DM4 to PS_DDR_DM7
Connect DM4 to PS_DDR_DM4, DM5 to PS_DDR_DM5, and so on.
Connect DM4 to PS_DDR_DM4, DM5 to PS_DDR_DM5, and so on.
Can be left unconnected.
PS_DDR_DM8
DM8, can be left unconnected without ECC.
DM8, can be left unconnected without ECC.
DM4, can be left unconnected without ECC.
PS_DDR_DQ0 to PS_DDR_DQ31
Connect DQ0 to PS_DDR_DQ0, DQ1 to PS_DDR_DQ1, and so on.
Connect DQ0 to PS_DDR_DQ0, DQ1 to PS_DDR_DQ1, and so on.
Connect DQ0 to PS_DDR_DQ0, DQ1 to PS_DDR_DQ1, and so on.
PS_DDR_DQ32 to PS_DDR_DQ63
Connect DQ32 to PS_DDR_DQ32, DQ33 to PS_DDR_DQ33, and so on.
Connect DQ32 to PS_DDR_DQ32, DQ33 to PS_DDR_DQ33, and so on.
Can be left unconnected.
PS_DDR_DQ64
DQ64 (ECC_bit[0]), can be left unconnected without ECC.
DQ64 (ECC_bit[0]), can be left unconnected without ECC.
DQ32 (ECC_bit[0]), can be left unconnected without ECC.
PS_DDR_DQ65 PS_DDR_DQ66
DQ65 (ECC_bit[1]), can be left unconnected without ECC. DQ66 (ECC_bit[2]), can be left unconnected without ECC.
DQ65 (ECC_bit[1]), can be left unconnected without ECC. DQ66 (ECC_bit[2]), can be left unconnected without ECC.
DQ33 (ECC_bit[1]), can be left unconnected without ECC. DQ34 (ECC_bit[2]), can be left unconnected without ECC.
PS_DDR_DQ67
DQ67 (ECC_bit[3]), can be left unconnected without ECC.
DQ67 (ECC_bit[3]), can be left unconnected without ECC.
DQ35 (ECC_bit[3]), can be left unconnected without ECC.
PS_DDR_DQ68 PS_DDR_DQ69
DQ68 (ECC_bit[4]), can be left unconnected without ECC. DQ69 (ECC_bit[5]), can be left unconnected without ECC.
DQ68 (ECC_bit[4]), can be left unconnected without ECC. DQ69 (ECC_bit[5]), can be left unconnected without ECC.
DQ36 (ECC_bit[4]), can be left unconnected without ECC. DQ37 (ECC_bit[5]), can be left unconnected without ECC.
DDR3/3L 32-bit 2Rank
CS#[1]
Connect DM0 to PS_DDR_DM0, DM1 to PS_DDR_DM1, and so on. Can be left unconnected.
DM4, can be left unconnected without ECC. Connect DQ0 to PS_DDR_DQ0, DQ1 to PS_DDR_DQ1, and so on. Can be left unconnected.
DQ32 (ECC_bit[0]), can be left unconnected without ECC. DQ33 (ECC_bit[1]), can be left unconnected without ECC. DQ34 (ECC_bit[2]), can be left unconnected without ECC. DQ35 (ECC_bit[3]), can be left unconnected without ECC. DQ36 (ECC_bit[4]), can be left unconnected without ECC. DQ37 (ECC_bit[5]), can be left unconnected without ECC.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
93
Send Feedback
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-1: DDR3/3L Supported Pinout Configurations (Cont'd)
Pin Name
PS_DDR_DQ70
DDR3/3L 64-bit 1Rank
DQ70 (ECC_bit[6]), can be left unconnected without ECC.
DDR3/3L 64-bit 2Rank
DQ70 (ECC_bit[6]), can be left unconnected without ECC.
DDR3/3L 32-bit 1Rank
DQ38 (ECC_bit[6]), can be left unconnected without ECC.
PS_DDR_DQ71 PS_DDR_DQS_N0 to PS_DDR_DQS_N3
DQ71 (ECC_bit[7]), can be left unconnected without ECC. Connect DQS#0 to PS_DDR_DQS_N0, DQS#1 to PS_DDR_DQS_N1, and so on.
DQ71 (ECC_bit[7]), can be left unconnected without ECC. Connect DQS#0 to PS_DDR_DQS_N0, DQS#1 to PS_DDR_DQS_N1, and so on.
DQ39 (ECC_bit[7]), can be left unconnected without ECC. Connect DQS#0 to PS_DDR_DQS_N0, DQS#1 to PS_DDR_DQS_N1, and so on.
PS_DDR_DQS_N4 to PS_DDR_DQS_N7 PS_DDR_DQS_N8
Connect DQS#4 to PS_DDR_DQS_N4, DQS#5 to PS_DDR_DQS_N5, and so on. DQS#8, can be left unconnected without ECC.
Connect DQS#4 to PS_DDR_DQS_N4, DQS#5 to PS_DDR_DQS_N5, and so on. DQS#8, can be left unconnected without ECC.
Can be left unconnected. DQS#4, can be left unconnected without ECC.
PS_DDR_DQS_P0 to PS_DDR_DQS_P3
Connect DQS0 to PS_DDR_DQS_P0, DQS1 to PS_DDR_DQS_P1, and so on.
Connect DQS0 to PS_DDR_DQS_P0, DQS1 to PS_DDR_DQS_P1, and so on.
Connect DQS0 to PS_DDR_DQS_P0, DQS1 to PS_DDR_DQS_P1, and so on.
PS_DDR_DQS_P4 to PS_DDR_DQS_P7
Connect DQS4 to PS_DDR_DQS_P4, DQS5 to PS_DDR_DQS_P5, and so on.
Connect DQS4 to PS_DDR_DQS_P4, DQS5 to PS_DDR_DQS_P5, and so on.
Can be left unconnected.
PS_DDR_DQS_P8 PS_DDR_ODT0 PS_DDR_ODT1 PS_DDR_PARITY
PS_DDR_RAM_RST_N
DQS8, can be left unconnected without ECC. ODT Can be left unconnected. Par_In for RDIMMs. Can be left unconnected for components and UDIMMs. RESET#
DQS8, can be left unconnected without ECC. ODT[0] ODT[1]
Par_In for RDIMMs. Can be left unconnected for components and UDIMMs. RESET#
DQS4, can be left unconnected without ECC. ODT Can be left unconnected. Par_In for RDIMMs. Can be left unconnected for components and UDIMMs. RESET#
DDR3/3L 32-bit 2Rank
DQ38 (ECC_bit[6]), can be left unconnected without ECC. DQ39 (ECC_bit[7]), can be left unconnected without ECC. Connect DQS#0 to PS_DDR_DQS_N0, DQS#1 to PS_DDR_DQS_N1, and so on. Can be left unconnected.
DQS#4, can be left unconnected without ECC. Connect DQS0 to PS_DDR_DQS_P0, DQS1 to PS_DDR_DQS_P1, and so on. Can be left unconnected.
DQS4, can be left unconnected without ECC. ODT[0] ODT[1]
Par_In for RDIMMs. Can be left unconnected for components and UDIMMs. RESET#
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
94
Send Feedback
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-1: DDR3/3L Supported Pinout Configurations (Cont'd)
Pin Name
PS_DDR_ZQ
DDR3/3L 64-bit 1Rank
Connect a 240 resistor to GND.(2)
DDR3/3L 64-bit 2Rank
Connect a 240 resistor to GND.(2)
DDR3/3L 32-bit 1Rank
Connect a 240 resistor to GND.(2)
DDR3/3L 32-bit 2Rank
Connect a 240 resistor to GND.(2)
Notes: 1. For VCCO_PSDDR decoupling guidelines, see the UltraScale Architecture PCB Design Guide [Ref 14]. 2. There should be separate 240 resistors at the FPGA and at the DRAM.
DDR4 Guidelines
DDR4 Pin Rules
The DDR4 pin rules are for single and dual-rank memory interfaces.
� All unused DDR pins can be left unconnected. For example, in a 64-bit interface without ECC, the PS_DDR_DQ64 to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, and PS_DDR_DM8 pins can be left unconnected.
� The PS_DDR_ALERT_N can be left floating at the DRAM. For component interfaces, connect the PS_DDR_ALERT_N pin to the ALERT_N pins of the DDR4 devices in fly-by routing, and terminate to VDD with a 50 pull-up resistor. For DIMM designs, connect the PS_DDR_ALERT_N pin to the ALERT_N pin of the connector.
� Connect the PS_DDR_ZQ pin to GND using a 240 resistor. There should be separate 240 resistors at the FPGA and at the DRAM.
� Component interfaces with the same component for all components in the interface. The x16 components have a different number of bank groups than the x8 components. For example, create a 72-bit wide component interface by using nine x8 components or five x16 components, where half of one component is not used. Creating four x16 components and one x8 component is not permissible.
DDR4 Pin Swapping Restrictions
� Address/command/control bits cannot be swapped.
� DQ byte lane swapping is allowed. A byte lane includes any signals associated with the aligned 8-bits of DQ, such as DM, DQS, DQS_N, and DQ signals.
� DQ bits swapping within a byte lane is allowed.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
95
Send Feedback
Chapter 2: PS Memory Interface Pin Guidelines
DDR4 Pinout Example for Supported Configurations
Table 2-2 shows a pinout example for the DDR4 supported configurations. For termination details, see the UltraScale Architecture PCB Design Guide [Ref 14]. When not being used for a memory interface, all pins should be left unconnected with the exception of VCCO_PSDDR and VCC_PSDDR_PLL, which should be tied to GND.
IMPORTANT: VCC_PSINTFP must be tied to VCC_PSINTFP_DDR. This requirement is in Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics [Ref 8] and Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics [Ref 9], where both VCC_PSINTFP and VCC_PSINTFP_DDR must be connected to the same supply and thus both must be powered to avoid MBIST failure.
Table 2-2: DDR4 Supported Pinout Configurations
Pin Name
VCCO_PSDDR(1) PS_DDR_A0 to PS_DDR_A16
PS_DDR_A17 PS_DDR_ACT_N PS_DDR_ALERT_N PS_DDR_BA0 PS_DDR_BA1 PS_DDR_BG0
DDR4 64-bit 1Rank
Set to 1.2V. Connect A0 to PS_DDR_A0, A1 to PS_DDR_A1, and so on. WE_N can be shared with PS_DDR_A14, CAS_N can be shared with PS_DDR_A15, and RAS_N can be shared with PS_DDR_A16. Can be left unconnected ACT_n ALERT_n BA[0] BA[1] BG[0]
DDR4 64-bit 2Rank
Set to 1.2V. Connect A0 to PS_DDR_A0, A1 to PS_DDR_A1, and so on. WE_N can be shared with PS_DDR_A14, CAS_N can be shared with PS_DDR_A15, and RAS_N can be shared with PS_DDR_A16. Can be left unconnected ACT_n ALERT_n BA[0] BA[1] BG[0]
DDR4 32-bit 1Rank
Set to 1.2V. Connect A0 to PS_DDR_A0, A1 to PS_DDR_A1, and so on. WE_N can be shared with PS_DDR_A14, CAS_N can be shared with PS_DDR_A15, and RAS_N can be shared with PS_DDR_A16. Can be left unconnected ACT_n ALERT_n BA[0] BA[1] BG[0]
DDR4 32-bit 2Rank
Set to 1.2V. Connect A0 to PS_DDR_A0, A1 to PS_DDR_A1, and so on. WE_N can be shared with PS_DDR_A14, CAS_N can be shared with PS_DDR_A15, and RAS_N can be shared with PS_DDR_A16. Can be left unconnected ACT_n ALERT_n BA[0] BA[1] BG[0]
DDR4 16-bit 1Rank
Set to 1.2V. Connect A0 to PS_DDR_A0, A1 to PS_DDR_A1, and so on. WE_N can be shared with PS_DDR_A14, CAS_N can be shared with PS_DDR_A15, and RAS_N can be shared with PS_DDR_A16. Can be left unconnected ACT_n ALERT_n BA[0] BA[1] BG[0]
DDR4 16-bit 2Rank
Set to 1.2V. Connect A0 to PS_DDR_A0, A1 to PS_DDR_A1, and so on. WE_N can be shared with PS_DDR_A14, CAS_N can be shared with PS_DDR_A15, and RAS_N can be shared with PS_DDR_A16. Can be left unconnected ACT_n ALERT_n BA[0] BA[1] BG[0]
Zynq UltraScale+ Packaging and Pinouts
96
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-2: DDR4 Supported Pinout Configurations (Cont'd)
Pin Name
PS_DDR_BG1(2) PS_DDR_CK_N0 PS_DDR_CK_N1 PS_DDR_CK0 PS_DDR_CK1 PS_DDR_CKE0 PS_DDR_CKE1 PS_DDR_CS_N0 PS_DDR_CS_N1 PS_DDR_DM0 to PS_DDR_DM1
PS_DDR_DM2 to PS_DDR_DM3
DDR4 64-bit 1Rank
BG[1] CK_c[0] Can be left unconnected. CK_t[0] Can be left unconnected. CKE Can be left unconnected. CS_n Can be left unconnected. Connect DM_n[0]/DBI_n[0] to PS_DDR_DM0, DM_n[1]/DBI_n[1] to PS_DDR_DM1, and so on. Connect DM_n[2]/DBI_n[2] to PS_DDR_DM2, DM_n[3]/DBI_n[3] to PS_DDR_DM3, and so on.
DDR4 64-bit 2Rank
BG[1] CK_c[0] CK_c[1]
CK_t[0] CK_t[1]
CKE[0] CKE[1]
CS_n[0] CS_n[1]
Connect DM_n[0]/DBI_n[0] to PS_DDR_DM0, DM_n[1]/DBI_n[1] to PS_DDR_DM1, and so on. Connect DM_n[2]/DBI_n[2] to PS_DDR_DM2, DM_n[3]/DBI_n[3] to PS_DDR_DM3, and so on.
DDR4 32-bit 1Rank
BG[1] CK_c[0] Can be left unconnected. CK_t[0] Can be left unconnected. CKE Can be left unconnected. CS_n Can be left unconnected. Connect DM_n[0]/DBI_n[0] to PS_DDR_DM0, DM_n[1]/DBI_n[1] to PS_DDR_DM1, and so on. Connect DM_n[2]/DBI_n[2] to PS_DDR_DM2, DM_n[3]/DBI_n[3] to PS_DDR_DM3, and so on.
DDR4 32-bit 2Rank
BG[1] CK_c[0] CK_c[1]
CK_t[0] CK_t[1]
CKE[0] CKE[1]
CS_n[0] CS_n[1]
Connect DM_n[0]/DBI_n[0] to PS_DDR_DM0, DM_n[1]/DBI_n[1] to PS_DDR_DM1, and so on. Connect DM_n[2]/DBI_n[2] to PS_DDR_DM2, DM_n[3]/DBI_n[3] to PS_DDR_DM3, and so on.
DDR4 16-bit 1Rank
BG[1] CK_c[0] Can be left unconnected. CK_t[0] Can be left unconnected. CKE Can be left unconnected. CS_n Can be left unconnected. Connect DM_n[0]/DBI_n[0] to PS_DDR_DM0, DM_n[1]/DBI_n[1] to PS_DDR_DM1, and so on. Can be left unconnected.
DDR4 16-bit 2Rank
BG[1] CK_c[0] CK_c[1]
CK_t[0] CK_t[1]
CKE[0] CKE[1]
CS_n[0] CS_n[1]
Connect DM_n[0]/DBI_n[0] to PS_DDR_DM0, DM_n[1]/DBI_n[1] to PS_DDR_DM1, and so on. Can be left unconnected.
Zynq UltraScale+ Packaging and Pinouts
97
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-2: DDR4 Supported Pinout Configurations (Cont'd)
Pin Name
PS_DDR_DM4 to PS_DDR_DM7
PS_DDR_DM8
DDR4 64-bit 1Rank
Connect DM_n[4]/DBI_n[4] to PS_DDR_DM4, DM_n[5]/DBI_n[5] to PS_DDR_DM5, and so on. DM_n[8]/DBI_n[8], can be left unconnected without ECC.
DDR4 64-bit 2Rank
Connect DM_n[4]/DBI_n[4] to PS_DDR_DM4, DM_n[5]/DBI_n[5] to PS_DDR_DM5, and so on. DM_n[8]/DBI_n[8], can be left unconnected without ECC.
DDR4 32-bit 1Rank
Can be left unconnected.
DM_n[4]/DBI_n[4], can be left unconnected without ECC.
DDR4 32-bit 2Rank
Can be left unconnected.
DM_n[4]/DBI_n[4], can be left unconnected without ECC.
DDR4 16-bit 1Rank
Can be left unconnected.
DM_n[2]/DBI_n[2], can be left unconnected without ECC.
PS_DDR_DQ0 to PS_DDR_DQ15
Connect DQ0 to PS_DDR_DQ0, DQ1 to PS_DDR_DQ1, and so on.
Connect DQ0 to PS_DDR_DQ0, DQ1 to PS_DDR_DQ1, and so on.
Connect DQ0 to PS_DDR_DQ0, DQ1 to PS_DDR_DQ1, and so on.
Connect DQ0 to PS_DDR_DQ0, DQ1 to PS_DDR_DQ1, and so on.
Connect DQ0 to PS_DDR_DQ0, DQ1 to PS_DDR_DQ1, and so on.
PS_DDR_DQ16 to PS_DDR_DQ31
Connect DQ16 to PS_DDR_DQ16, DQ17 to PS_DDR_DQ17, and so on.
Connect DQ16 to PS_DDR_DQ16, DQ17 to PS_DDR_DQ17, and so on.
Connect DQ16 to PS_DDR_DQ16, DQ17 to PS_DDR_DQ17, and so on.
Connect DQ16 to PS_DDR_DQ16, DQ17 to PS_DDR_DQ17, and so on.
Can be left unconnected. Do not swap with PS_DDR_DQ0 to PS_DDR_DQ15.
PS_DDR_DQ32 to PS_DDR_DQ63
Connect DQ32 to PS_DDR_DQ32, DQ33 to PS_DDR_DQ33, and so on.
Connect DQ32 to PS_DDR_DQ32, DQ33 to PS_DDR_DQ33, and so on.
Can be left unconnected. Do not swap with PS_DDR_DQ0 to PS_DDR_DQ31.
Can be left unconnected. Do not swap with PS_DDR_DQ0 to PS_DDR_DQ31.
Can be left unconnected. Do not swap with PS_DDR_DQ0 to PS_DDR_DQ31.
PS_DDR_DQ64 PS_DDR_DQ65
DQ64 (ECC_bit[0]), can be left unconnected without ECC. DQ65 (ECC_bit[1]), can be left unconnected without ECC.
DQ64 (ECC_bit[0]), can be left unconnected without ECC. DQ65 (ECC_bit[1]), can be left unconnected without ECC.
DQ32 (ECC_bit[0]), can be left unconnected without ECC. DQ33 (ECC_bit[1]), can be left unconnected without ECC.
DQ32 (ECC_bit[0]), can be left unconnected without ECC. DQ33 (ECC_bit[1]), can be left unconnected without ECC.
DQ16 (ECC_bit[0]), can be left unconnected without ECC. DQ17 (ECC_bit[1]), can be left unconnected without ECC.
DDR4 16-bit 2Rank
Can be left unconnected.
DM_n[2]/DBI_n[2], can be left unconnected without ECC. Connect DQ0 to PS_DDR_DQ0, DQ1 to PS_DDR_DQ1, and so on. Can be left unconnected. Do not swap with PS_DDR_DQ0 to PS_DDR_DQ15. Can be left unconnected. Do not swap with PS_DDR_DQ0 to PS_DDR_DQ31. DQ16 (ECC_bit[0]), can be left unconnected without ECC. DQ17 (ECC_bit[1]), can be left unconnected without ECC.
Zynq UltraScale+ Packaging and Pinouts
98
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-2: DDR4 Supported Pinout Configurations (Cont'd)
Pin Name
PS_DDR_DQ66
DDR4 64-bit 1Rank
DQ66 (ECC_bit[2]), can be left unconnected without ECC.
DDR4 64-bit 2Rank
DQ66 (ECC_bit[2]), can be left unconnected without ECC.
DDR4 32-bit 1Rank
DQ34 (ECC_bit[2]), can be left unconnected without ECC.
PS_DDR_DQ67 PS_DDR_DQ68 PS_DDR_DQ69
DQ67 (ECC_bit[3]), can be left unconnected without ECC. DQ68 (ECC_bit[4]), can be left unconnected without ECC. DQ69 (ECC_bit[5]), can be left unconnected without ECC.
DQ67 (ECC_bit[3]), can be left unconnected without ECC. DQ68 (ECC_bit[4]), can be left unconnected without ECC. DQ69 (ECC_bit[5]), can be left unconnected without ECC.
DQ35 (ECC_bit[3]), can be left unconnected without ECC. DQ36 (ECC_bit[4]), can be left unconnected without ECC. DQ37 (ECC_bit[5]), can be left unconnected without ECC.
PS_DDR_DQ70
DQ70 (ECC_bit[6]), can be left unconnected without ECC.
DQ70 (ECC_bit[6]), can be left unconnected without ECC.
DQ38 (ECC_bit[6]), can be left unconnected without ECC.
PS_DDR_DQ71 PS_DDR_DQS_N0 to PS_DDR_DQS_N1
DQ71 (ECC_bit[7]), can be left unconnected without ECC. Connect DQS_c0 to PS_DDR_DQS_N0, DQS_c1 to PS_DDR_DQS_N1, and so on.
DQ71 (ECC_bit[7]), can be left unconnected without ECC. Connect DQS_c0 to PS_DDR_DQS_N0, DQS_c1 to PS_DDR_DQS_N1, and so on.
DQ39 (ECC_bit[7]), can be left unconnected without ECC. Connect DQS_c0 to PS_DDR_DQS_N0, DQS_c1 to PS_DDR_DQS_N1, and so on.
DDR4 32-bit 2Rank
DQ34 (ECC_bit[2]), can be left unconnected without ECC. DQ35 (ECC_bit[3]), can be left unconnected without ECC. DQ36 (ECC_bit[4]), can be left unconnected without ECC. DQ37 (ECC_bit[5]), can be left unconnected without ECC. DQ38 (ECC_bit[6]), can be left unconnected without ECC. DQ39 (ECC_bit[7]), can be left unconnected without ECC. Connect DQS_c0 to PS_DDR_DQS_N0, DQS_c1 to PS_DDR_DQS_N1, and so on.
DDR4 16-bit 1Rank
DQ18 (ECC_bit[2]), can be left unconnected without ECC. DQ19 (ECC_bit[3]), can be left unconnected without ECC. DQ20 (ECC_bit[4]), can be left unconnected without ECC. DQ21 (ECC_bit[5]), can be left unconnected without ECC. DQ22 (ECC_bit[6]), can be left unconnected without ECC. DQ23 (ECC_bit[7]), can be left unconnected without ECC. Connect DQS_c0 to PS_DDR_DQS_N0, DQS_c1 to PS_DDR_DQS_N1, and so on.
DDR4 16-bit 2Rank
DQ18 (ECC_bit[2]), can be left unconnected without ECC. DQ19 (ECC_bit[3]), can be left unconnected without ECC. DQ20 (ECC_bit[4]), can be left unconnected without ECC. DQ21 (ECC_bit[5]), can be left unconnected without ECC. DQ22 (ECC_bit[6]), can be left unconnected without ECC. DQ23 (ECC_bit[7]), can be left unconnected without ECC. Connect DQS_c0 to PS_DDR_DQS_N0, DQS_c1 to PS_DDR_DQS_N1, and so on.
Zynq UltraScale+ Packaging and Pinouts
99
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-2: DDR4 Supported Pinout Configurations (Cont'd)
Pin Name
PS_DDR_DQS_N2 to PS_DDR_DQS_N3
DDR4 64-bit 1Rank
Connect DQS_c2 to PS_DDR_DQS_N2, DQS_c3 to PS_DDR_DQS_N3, and so on.
DDR4 64-bit 2Rank
Connect DQS_c2 to PS_DDR_DQS_N2, DQS_c3 to PS_DDR_DQS_N3, and so on.
DDR4 32-bit 1Rank
Connect DQS_c2 to PS_DDR_DQS_N2, DQS_c3 to PS_DDR_DQS_N3, and so on.
PS_DDR_DQS_N4 to PS_DDR_DQS_N7
Connect DQS_c4 to PS_DDR_DQS_N4, DQS_c5 to PS_DDR_DQS_N5, and so on.
Connect DQS_c4 to PS_DDR_DQS_N4, DQS_c5 to PS_DDR_DQS_N5, and so on.
Can be left unconnected.
PS_DDR_DQS_N8
DQS_c8, can be left unconnected without ECC.
DQS_c8, can be left unconnected without ECC.
DQS_c4, can be left unconnected without ECC.
PS_DDR_DQS_P0 to PS_DDR_DQS_P1 PS_DDR_DQS_P2 to PS_DDR_DQS_P3 PS_DDR_DQS_P4 to PS_DDR_DQS_P7 PS_DDR_DQS_P8
Connect DQS_t0 to PS_DDR_DQS_P0, DQS_t1 to PS_DDR_DQS_P1, and so on. Connect DQS_t2 to PS_DDR_DQS_P2, DQS_t3 to PS_DDR_DQS_P3, and so on. Connect DQS_t4 to PS_DDR_DQS_P4, DQS_t5 to PS_DDR_DQS_P5, and so on. DQS_t8, can be left unconnected without ECC.
Connect DQS_t0 to PS_DDR_DQS_P0, DQS_t1 to PS_DDR_DQS_P1, and so on. Connect DQS_t2 to PS_DDR_DQS_P2, DQS_t3 to PS_DDR_DQS_P3, and so on. Connect DQS_t4 to PS_DDR_DQS_P4, DQS_t5 to PS_DDR_DQS_P5, and so on. DQS_t8, can be left unconnected without ECC.
Connect DQS_t0 to PS_DDR_DQS_P0, DQS_t1 to PS_DDR_DQS_P1, and so on. Connect DQS_t2 to PS_DDR_DQS_P2, DQS_t3 to PS_DDR_DQS_P3, and so on. Can be left unconnected.
DQS_t4, can be left unconnected without ECC.
PS_DDR_ODT0
ODT
ODT[0]
ODT
DDR4 32-bit 2Rank
Connect DQS_c2 to PS_DDR_DQS_N2, DQS_c3 to PS_DDR_DQS_N3, and so on. Can be left unconnected.
DQS_c4, can be left unconnected without ECC. Connect DQS_t0 to PS_DDR_DQS_P0, DQS_t1 to PS_DDR_DQS_P1, and so on. Connect DQS_t2 to PS_DDR_DQS_P2, DQS_t3 to PS_DDR_DQS_P3, and so on. Can be left unconnected.
DQS_t4, can be left unconnected without ECC. ODT[0]
DDR4 16-bit 1Rank
Can be left unconnected.
Can be left unconnected.
DQS_c2, can be left unconnected without ECC. Connect DQS_t0 to PS_DDR_DQS_P0, DQS_t1 to PS_DDR_DQS_P1, and so on. Can be left unconnected.
Can be left unconnected.
DQS_t2, can be left unconnected without ECC. ODT
DDR4 16-bit 2Rank
Can be left unconnected.
Can be left unconnected.
DQS_c2, can be left unconnected without ECC. Connect DQS_t0 to PS_DDR_DQS_P0, DQS_t1 to PS_DDR_DQS_P1, and so on. Can be left unconnected.
Can be left unconnected.
DQS_t2, can be left unconnected without ECC. ODT[0]
Zynq UltraScale+ Packaging and Pinouts
100
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-2: DDR4 Supported Pinout Configurations (Cont'd)
Pin Name
PS_DDR_ODT1
PS_DDR_PARITY PS_DDR_RAM_RST_N PS_DDR_ZQ
DDR4 64-bit 1Rank
Can be left unconnected. PAR RESET_n Connect to GND through a 240 resistor. Connect DRAM ZQ pins to VSSQ through a 240 resistor.
DDR4 64-bit 2Rank
ODT[1]
PAR RESET_n Connect to GND through a 240 resistor. Connect DRAM ZQ pins to VSSQ through a 240 resistor.
DDR4 32-bit 1Rank
Can be left unconnected. PAR RESET_n Connect to GND through a 240 resistor. Connect DRAM ZQ pins to VSSQ through a 240 resistor.
DDR4 32-bit 2Rank
ODT[1]
PAR RESET_n Connect to GND through a 240 resistor. Connect DRAM ZQ pins to VSSQ through a 240 resistor.
DDR4 16-bit 1Rank
Can be left unconnected. PAR RESET_n Connect to GND through a 240 resistor. Connect DRAM ZQ pins to VSSQ through a 240 resistor.
DDR4 16-bit 2Rank
ODT[1]
PAR RESET_n Connect to GND through a 240 resistor. Connect DRAM ZQ pins to VSSQ through a 240 resistor.
Notes: 1. For VCCO_PSDDR decoupling guidelines, see the UltraScale Architecture PCB Design Guide [Ref 14]. 2. The PS_DDR_BG1 pin can be left unconnected when targeting x16 component interfaces without a BG1 pin, but it should always be connected for DIMM applications.
Zynq UltraScale+ Packaging and Pinouts
101
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 2: PS Memory Interface Pin Guidelines
LPDDR4 Guidelines
LPDDR4 Pin Rules
The LPDDR4 pin rules are for single and dual-rank memory interfaces.
� All unused DDR pins can be left unconnected. For example, in an 64-bit interface without ECC, the PS_DDR_DQ64 to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, and PS_DDR_DM8 pins can be left unconnected.
� Connect the PS_DDR_ZQ pin to GND using a 240 resistor. There should be separate 240 resistors at the FPGA and at the DRAM.
� To achieve maximum performance, address copy mode is suggested.
LPDDR4 Pin Swapping Restrictions
� Command/address bits cannot be swapped. � To support write DQS to DQ training, DQ byte lane swapping is not allowed. � To support write DQS to DQ training, DQ bits with bytes 0, 2, and 8 are not allowed to
be swapped. � Bits within bytes 1 and 3 can be swapped.
LPDDR4 Pinout Example for Supported Configurations
Table 2-3 shows a pinout example for the LPDDR4 supported configurations. For termination details, see the UltraScale Architecture PCB Design Guide [Ref 14]. When not being used for a memory interface, all pins should be left unconnected with the exception of VCCO_PSDDR and VCC_PSDDR_PLL, which should be tied to GND.
IMPORTANT: VCC_PSINTFP must be tied to VCC_PSINTFP_DDR. This requirement is in Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics [Ref 8] and Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics [Ref 9], where both VCC_PSINTFP and VCC_PSINTFP_DDR must be connected to the same supply and thus both must be powered to avoid MBIST failure.
Table 2-3: LPDDR4 Supported Pinout Configurations
Pin Name
VCCO_PSDDR(1)
LPDDR4 32-bit 1Rank
Set to 1.1V
LPDDR4 32-bit 1Rank ECC
Set to 1.1V
PS_DDR_A0
CA0_A
CA0_A
PS_DDR_A1
CA1_A
CA1_A
PS_DDR_A2
CA2_A
CA2_A
LPDDR4 32-bit 2Rank
Set to 1.1V CA0_A CA1_A CA2_A
LPDDR4 32-bit 2Rank ECC
Set to 1.1V CA0_A CA1_A CA2_A
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
102
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-3: LPDDR4 Supported Pinout Configurations (Cont'd)
Pin Name
PS_DDR_A3
LPDDR4 32-bit 1Rank
CA3_A
LPDDR4 32-bit 1Rank ECC
CA3_A
LPDDR4 32-bit 2Rank
CA3_A
PS_DDR_A4
CA4_A
CA4_A
CA4_A
PS_DDR_A5
CA5_A
CA5_A
CA5_A
PS_DDR_A6 to PS_DDR_A9
Can be left unconnected.
Can be left unconnected.
Can be left unconnected.
PS_DDR_A10
CA0_B
CA0_B
CA0_B
PS_DDR_A11
CA1_B
CA1_B
CA1_B
PS_DDR_A12
CA2_B
CA2_B
CA2_B
PS_DDR_A13
CA3_B
CA3_B
CA3_B
PS_DDR_A14
CA4_B
CA4_B
CA4_B
PS_DDR_A15
CA5_B
CA5_B
CA5_B
PS_DDR_A16
Can be left unconnected.
Can be left unconnected.
Can be left unconnected.
PS_DDR_A17
Can be left unconnected.
Can be left unconnected.
Can be left unconnected.
PS_DDR_ACT_N
Can be left unconnected.
Can be left unconnected.
Can be left unconnected.
PS_DDR_ALERT_N PS_DDR_BA0 PS_DDR_BA1
Can be left unconnected. Can be left unconnected. Can be left unconnected.
Can be left unconnected. Can be left unconnected. Can be left unconnected.
Can be left unconnected. Can be left unconnected. Can be left unconnected.
PS_DDR_BG0
Can be left unconnected.
Can be left unconnected.
Can be left unconnected.
PS_DDR_BG1
Can be left unconnected.
Can be left unconnected.
Can be left unconnected.
PS_DDR_CK_N0
CK_c_A
CK_c_A
CK_c_A
PS_DDR_CK_N1
CK_c_B
CK_c_B
CK_c_B
PS_DDR_CK0
CK_t_A
CK_t_A
CK_t_A
PS_DDR_CK1
CK_t_B
CK_t_B
CK_t_B
PS_DDR_CKE0
CKE_A and CKE_B
CKE_A
CKE0_A and CKE0_B
PS_DDR_CKE1
Can be left unconnected.
Can be left unconnected.
CKE1_A and CKE1_B
PS_DDR_CS_N0
CS_A and CS_B
CS_A
CS0_A and CS0_B
PS_DDR_CS_N1
Can be left unconnected.
Can be left unconnected.
CS1_A and CS1_B
PS_DDR_DM0
DMI0_A
DMI0_A
DMI0_A
LPDDR4 32-bit 2Rank ECC
CA3_A CA4_A CA5_A Can be left unconnected. CA0_B CA1_B CA2_B CA3_B CA4_B CA5_B Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. CK_c_A CK_c_B CK_t_A CK_t_B CKE0_A CKE1_A
CS0_A CS1_A
DMI0_A
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
103
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-3: LPDDR4 Supported Pinout Configurations (Cont'd)
Pin Name
PS_DDR_DM1
LPDDR4 32-bit 1Rank
DMI1_A
LPDDR4 32-bit 1Rank ECC
DMI1_A
LPDDR4 32-bit 2Rank
DMI1_A
PS_DDR_DM2
DMI0_B
DMI0_B
DMI0_B
PS_DDR_DM3
DMI1_B
DMI1_B
DMI1_B
PS_DDR_DM4 to PS_DDR_DM7
Can be left unconnected.
Can be left unconnected.
Can be left unconnected.
PS_DDR_DM8 PS_DDR_DQ0 to PS_DDR_DQ15
Can be left unconnected. Connect DQ0_A to PS_DDR_DQ0, DQ1_A to PS_DDR_DQ1, and so on.
DMI_ECC Connect DQ0_A to PS_DDR_DQ0, DQ1_A to PS_DDR_DQ1, and so on.
Can be left unconnected. Connect DQ0_A to PS_DDR_DQ0, DQ1_A to PS_DDR_DQ1, and so on.
PS_DDR_DQ16 to PS_DDR_DQ31
PS_DDR_DQ32 to PS_DDR_DQ63 PS_DDR_DQ64
Connect DQ0_B to PS_DDR_DQ16, DQ1_B to PS_DDR_DQ17, and so on. Can be left unconnected. Can be left unconnected.
Connect DQ0_B to PS_DDR_DQ16, DQ1_B to PS_DDR_DQ17, and so on. Can be left unconnected. DQ_ECC0 (ECC_bit[0])
Connect DQ0_B to PS_DDR_DQ16, DQ1_B to PS_DDR_DQ17, and so on. Can be left unconnected. Can be left unconnected.
PS_DDR_DQ65
Can be left unconnected.
DQ_ECC1 (ECC_bit[1])
Can be left unconnected.
PS_DDR_DQ66
Can be left unconnected.
DQ_ECC2 (ECC_bit[2])
Can be left unconnected.
PS_DDR_DQ67 PS_DDR_DQ68 PS_DDR_DQ69 PS_DDR_DQ70
Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected.
DQ_ECC3 (ECC_bit[3]) DQ_ECC4 (ECC_bit[4]) DQ_ECC5 (ECC_bit[5]) DQ_ECC6 (ECC_bit[6])
Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected.
PS_DDR_DQ71
Can be left unconnected.
DQ_ECC7 (ECC_bit[7])
Can be left unconnected.
PS_DDR_DQS_N0
DQS0_c_A
DQS0_c_A
DQS0_c_A
PS_DDR_DQS_N1
DQS1_c_A
DQS1_c_A
DQS1_c_A
PS_DDR_DQS_N2
DQS0_c_B
DQS0_c_B
DQS0_c_B
PS_DDR_DQS_N3 PS_DDR_DQS_N4 to PS_DDR_DQS_N7
DQS1_c_B Can be left unconnected.
DQS1_c_B Can be left unconnected.
DQS1_c_B Can be left unconnected.
LPDDR4 32-bit 2Rank ECC
DMI1_A DMI0_B DMI1_B Can be left unconnected. DMI_ECC
Connect DQ0_A to PS_DDR_DQ0, DQ1_A to PS_DDR_DQ1, and so on. Connect DQ0_B to PS_DDR_DQ16, DQ1_B to PS_DDR_DQ17, and so on. Can be left unconnected. DQ_ECC0 (ECC_bit[0]) DQ_ECC1 (ECC_bit[1]) DQ_ECC2 (ECC_bit[2]) DQ_ECC3 (ECC_bit[3]) DQ_ECC4 (ECC_bit[4]) DQ_ECC5 (ECC_bit[5]) DQ_ECC6 (ECC_bit[6]) DQ_ECC7 (ECC_bit[7]) DQS0_c_A DQS1_c_A DQS0_c_B DQS1_c_B Can be left unconnected.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
104
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-3: LPDDR4 Supported Pinout Configurations (Cont'd)
Pin Name
PS_DDR_DQS_N8
PS_DDR_DQS_P0 PS_DDR_DQS_P1 PS_DDR_DQS_P2 PS_DDR_DQS_P3 PS_DDR_DQS_P4 to PS_DDR_DQS_P7 PS_DDR_DQS_P8
PS_DDR_ODT0
PS_DDR_ODT1
PS_DDR_PARITY
PS_DDR_RAM_RST_N PS_DDR_ZQ
LPDDR4 32-bit 1Rank
Can be left unconnected. DQS0_t_A DQS1_t_A DQS0_t_B DQS1_t_B Can be left unconnected. Can be left unconnected. Unconnected at FPGA. Can be left unconnected. Can be left unconnected. RESET_n Connect to GND through a 240 resistor. Connect DRAM ZQ pins to VDDQ through a 240 resistor.
LPDDR4 32-bit 1Rank ECC
DQS_c_ECC
DQS0_t_A DQS1_t_A DQS0_t_B DQS1_t_B Can be left unconnected. DQS_t_ECC
Unconnected at FPGA. Can be left unconnected. Can be left unconnected. RESET_n Connect to GND through a 240 resistor. Connect DRAM ZQ pins to VDDQ through a 240 resistor.
LPDDR4 32-bit 2Rank
Can be left unconnected. DQS0_t_A DQS1_t_A DQS0_t_B DQS1_t_B Can be left unconnected. Can be left unconnected. Unconnected at FPGA. Can be left unconnected. Can be left unconnected. RESET_n Connect to GND through a 240 resistor. Connect DRAM ZQ pins to VDDQ through a 240 resistor.
LPDDR4 32-bit 2Rank ECC
DQS_c_ECC
DQS0_t_A DQS1_t_A DQS0_t_B DQS1_t_B Can be left unconnected. DQS_t_ECC
Unconnected at FPGA. Can be left unconnected. Can be left unconnected. RESET_n Connect to GND through a 240 resistor. Connect DRAM ZQ pins to VDDQ through a 240 resistor.
Notes: 1. For VCCO_PSDDR decoupling guidelines, see the UltraScale Architecture PCB Design Guide [Ref 14].
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
105
Chapter 2: PS Memory Interface Pin Guidelines
LPDDR3 Guidelines
LPDDR3 Pin Rules
The LPDDR3 pin rules are for single and dual-rank memory interfaces.
� All unused DDR pins can be left unconnected. For example, in an 64-bit interface without ECC, the PS_DDR_DQ64 to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, and PS_DDR_DM8 pins can be left unconnected.
� Connect the PS_DDR_ZQ pin to GND using a 240 resistor. There should be separate 240 resistors at the FPGA and at the DRAM.
� To achieve maximum performance, address copy mode is suggested.
LPDDR3 Pin Swapping Restrictions
� Command/address bits cannot be swapped. � To support command/address training, DQ byte lane swapping is not allowed. � To support command/address training, DQ bits swapping within a byte lane is not
allowed.
LPDDR3 Pinout Example for Supported Configurations
Table 2-4 shows a pinout example for the LPDDR3 supported configurations. For termination details, see the UltraScale Architecture PCB Design Guide [Ref 14]. When not being used for a memory interface, all pins should be left unconnected with the exception of VCCO_PSDDR and VCC_PSDDR_PLL, which should be tied to GND.
IMPORTANT: VCC_PSINTFP must be tied to VCC_PSINTFP_DDR. This requirement is in Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics [Ref 8] and Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics [Ref 9], where both VCC_PSINTFP and VCC_PSINTFP_DDR must be connected to the same supply and thus both must be powered to avoid MBIST failure.
Table 2-4: LPDDR3 Supported Pinout Configurations)
Pin Name
VCCO_PSDDR(1) PS_DDR_A0 PS_DDR_A1 PS_DDR_A2 PS_DDR_A3
LPDDR3 64-bit
Set to 1.2V CA0_A CA1_A CA2_A CA3_A
LPDDR3 64-bit (Dual Rank)
Set to 1.2V CA0_A CA1_A CA2_A CA3_A
LPDDR3 32-bit (Dual Rank)
Set to 1.2V CA0 CA1 CA2 CA3
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
106
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-4: LPDDR3 Supported Pinout Configurations) (Cont'd)
Pin Name
PS_DDR_A4
LPDDR3 64-bit
CA4_A
LPDDR3 64-bit (Dual Rank)
CA4_A
PS_DDR_A5
CA5_A
CA5_A
PS_DDR_A6
CA6_A
CA6_A
PS_DDR_A7
CA7_A
CA7_A
PS_DDR_A8
CA8_A
CA8_A
PS_DDR_A9
CA9_A
CA9_A
PS_DDR_A10
CA0_B
CA0_B
PS_DDR_A11 PS_DDR_A12 PS_DDR_A13 PS_DDR_A14 PS_DDR_A15
CA1_B CA2_B CA3_B CA4_B CA5_B
CA1_B CA2_B CA3_B CA4_B CA5_B
PS_DDR_A16
Can be left unconnected. Can be left unconnected.
PS_DDR_A17
Can be left unconnected. Can be left unconnected.
PS_DDR_ACT_N
CA9_B
CA9_B
PS_DDR_ALERT_N
Can be left unconnected. Can be left unconnected.
PS_DDR_BA0
CA6_B
CA6_B
PS_DDR_BA1
CA7_B
CA7_B
PS_DDR_BG0
CA8_B
CA8_B
PS_DDR_BG1
Can be left unconnected. Can be left unconnected.
PS_DDR_CK_N0 PS_DDR_CK_N1 PS_DDR_CK0 PS_DDR_CK1 PS_DDR_CKE0
CK_c_A CK_c_B CK_t_A CK_t_B CKE_A and CKE_B
CK_c_A CK_c_B CK_t_A CK_t_B CKE0_A and CKE0_B
PS_DDR_CKE1
Can be left unconnected. CKE1_A and CKE1_B
PS_DDR_CS_N0
CS_n_A and CS_n_B
CS0_n_A and CS0_n_B
PS_DDR_CS_N1
Can be left unconnected. CS1_n_A and CS1_n_B
PS_DDR_DM0
DM0_A
DM0_A
PS_DDR_DM1
DM1_A
DM1_A
PS_DDR_DM2
DM2_A
DM2_A
PS_DDR_DM3
DM3_A
DM3_A
PS_DDR_DM4 PS_DDR_DM5
DM0_B DM1_B
DM0_B DM1_B
LPDDR3 32-bit (Dual Rank)
CA4 CA5 CA6 CA7 CA8 CA9 Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. CK_c Can be left unconnected. CK_t Can be left unconnected. CKE0 CKE1 CS0_n CS1_n DM0 DM1 DM2 DM3 Can be left unconnected. Can be left unconnected.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
107
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-4: LPDDR3 Supported Pinout Configurations) (Cont'd)
Pin Name
PS_DDR_DM6
LPDDR3 64-bit
DM2_B
LPDDR3 64-bit (Dual Rank)
DM2_B
PS_DDR_DM7
DM3_B
DM3_B
PS_DDR_DM8
DM_ECC, can be left
DM_ECC, can be left
unconnected without ECC. unconnected without ECC.
PS_DDR_DQ0
DQ0_A
DQ0_A
PS_DDR_DQ1
DQ1_A
DQ1_A
PS_DDR_DQ2
DQ2_A
DQ2_A
PS_DDR_DQ3
DQ3_A
DQ3_A
PS_DDR_DQ4
DQ4_A
DQ4_A
PS_DDR_DQ5
DQ5_A
DQ5_A
PS_DDR_DQ6
DQ6_A
DQ6_A
PS_DDR_DQ7 PS_DDR_DQ8 PS_DDR_DQ9 PS_DDR_DQ10 PS_DDR_DQ11
DQ7_A DQ8_A DQ9_A DQ10_A DQ11_A
DQ7_A DQ8_A DQ9_A DQ10_A DQ11_A
PS_DDR_DQ12
DQ12_A
DQ12_A
PS_DDR_DQ13
DQ13_A
DQ13_A
PS_DDR_DQ14
DQ14_A
DQ14_A
PS_DDR_DQ15
DQ15_A
DQ15_A
PS_DDR_DQ16
DQ16_A
DQ16_A
PS_DDR_DQ17
DQ17_A
DQ17_A
PS_DDR_DQ18
DQ18_A
DQ18_A
PS_DDR_DQ19
DQ19_A
DQ19_A
PS_DDR_DQ20 PS_DDR_DQ21 PS_DDR_DQ22 PS_DDR_DQ23 PS_DDR_DQ24 PS_DDR_DQ25
DQ20_A DQ21_A DQ22_A DQ23_A DQ24_A DQ25_A
DQ20_A DQ21_A DQ22_A DQ23_A DQ24_A DQ25_A
PS_DDR_DQ26
DQ26_A
DQ26_A
PS_DDR_DQ27
DQ27_A
DQ27_A
PS_DDR_DQ28
DQ28_A
DQ28_A
PS_DDR_DQ29
DQ29_A
DQ29_A
LPDDR3 32-bit (Dual Rank)
Can be left unconnected. Can be left unconnected. DM_ECC, can be left unconnected without ECC. DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
108
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-4: LPDDR3 Supported Pinout Configurations) (Cont'd)
Pin Name
PS_DDR_DQ30
LPDDR3 64-bit
DQ30_A
LPDDR3 64-bit (Dual Rank)
DQ30_A
PS_DDR_DQ31
DQ31_A
DQ31_A
PS_DDR_DQ32
DQ0_B
DQ0_B
PS_DDR_DQ33
DQ1_B
DQ1_B
PS_DDR_DQ34
DQ2_B
DQ2_B
PS_DDR_DQ35
DQ3_B
DQ3_B
PS_DDR_DQ36
DQ4_B
DQ4_B
PS_DDR_DQ37 PS_DDR_DQ38 PS_DDR_DQ39 PS_DDR_DQ40 PS_DDR_DQ41
DQ5_B DQ6_B DQ7_B DQ8_B DQ9_B
DQ5_B DQ6_B DQ7_B DQ8_B DQ9_B
PS_DDR_DQ42
DQ10_B
DQ10_B
PS_DDR_DQ43
DQ11_B
DQ11_B
PS_DDR_DQ44
DQ12_B
DQ12_B
PS_DDR_DQ45
DQ13_B
DQ13_B
PS_DDR_DQ46
DQ14_B
DQ14_B
PS_DDR_DQ47
DQ15_B
DQ15_B
PS_DDR_DQ48
DQ16_B
DQ16_B
PS_DDR_DQ49
DQ17_B
DQ17_B
PS_DDR_DQ50 PS_DDR_DQ51 PS_DDR_DQ52 PS_DDR_DQ53 PS_DDR_DQ54
DQ18_B DQ19_B DQ20_B DQ21_B DQ22_B
DQ18_B DQ19_B DQ20_B DQ21_B DQ22_B
PS_DDR_DQ55
DQ23_B
DQ23_B
PS_DDR_DQ56
DQ24_B
DQ24_B
PS_DDR_DQ57
DQ25_B
DQ25_B
PS_DDR_DQ58
DQ26_B
DQ26_B
PS_DDR_DQ59
DQ27_B
DQ27_B
PS_DDR_DQ60
DQ28_B
DQ28_B
PS_DDR_DQ61
DQ29_B
DQ29_B
PS_DDR_DQ62 PS_DDR_DQ63
DQ30_B DQ31_B
DQ30_B DQ31_B
LPDDR3 32-bit (Dual Rank)
DQ30 DQ31 Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected. Can be left unconnected.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
109
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-4: LPDDR3 Supported Pinout Configurations) (Cont'd)
Pin Name
PS_DDR_DQ64
LPDDR3 64-bit
DQ_ECC0 (ECC_bit[0]), can be left unconnected without ECC.
LPDDR3 64-bit (Dual Rank)
DQ_ECC0 (ECC_bit[0]), can be left unconnected without ECC.
LPDDR3 32-bit (Dual Rank)
DQ_ECC0 (ECC_bit[0]), can be left unconnected without ECC.
PS_DDR_DQ65
DQ_ECC1 (ECC_bit[1]), can DQ_ECC1 (ECC_bit[1]), can DQ_ECC1 (ECC_bit[1]), can
be left unconnected without be left unconnected without be left unconnected without
ECC.
ECC.
ECC.
PS_DDR_DQ66 PS_DDR_DQ67
DQ_ECC2 (ECC_bit[2]), can be left unconnected without ECC. DQ_ECC3 (ECC_bit[3]), can be left unconnected without ECC.
DQ_ECC2 (ECC_bit[2]), can be left unconnected without ECC. DQ_ECC3 (ECC_bit[3]), can be left unconnected without ECC.
DQ_ECC2 (ECC_bit[2]), can be left unconnected without ECC. DQ_ECC3 (ECC_bit[3]), can be left unconnected without ECC.
PS_DDR_DQ68 PS_DDR_DQ69
DQ_ECC4 (ECC_bit[4]), can be left unconnected without ECC. DQ_ECC5 (ECC_bit[5]), can be left unconnected without ECC.
DQ_ECC4 (ECC_bit[4]), can be left unconnected without ECC. DQ_ECC5 (ECC_bit[5]), can be left unconnected without ECC.
DQ_ECC4 (ECC_bit[4]), can be left unconnected without ECC. DQ_ECC5 (ECC_bit[5]), can be left unconnected without ECC.
PS_DDR_DQ70 PS_DDR_DQ71
DQ_ECC6 (ECC_bit[6]), can be left unconnected without ECC. DQ_ECC7 (ECC_bit[7]), can be left unconnected without ECC.
DQ_ECC6 (ECC_bit[6]), can be left unconnected without ECC. DQ_ECC7 (ECC_bit[7]), can be left unconnected without ECC.
DQ_ECC6 (ECC_bit[6]), can be left unconnected without ECC. DQ_ECC7 (ECC_bit[7]), can be left unconnected without ECC.
PS_DDR_DQS_N0
DQS0_c_A
DQS0_c_A
DQS0_c
PS_DDR_DQS_N1
DQS1_c_A
DQS1_c_A
DQS1_c
PS_DDR_DQS_N2 PS_DDR_DQS_N3 PS_DDR_DQS_N4 PS_DDR_DQS_N5 PS_DDR_DQS_N6
DQS2_c_A DQS3_c_A DQS0_c_B DQS1_c_B DQS2_c_B
DQS2_c_A DQS3_c_A DQS0_c_B DQS1_c_B DQS2_c_B
DQS2_c DQS3_c Can be left unconnected. Can be left unconnected. Can be left unconnected.
PS_DDR_DQS_N7
DQS3_c_B
DQS3_c_B
Can be left unconnected.
PS_DDR_DQS_N8
PS_DDR_DQS_P0 PS_DDR_DQS_P1
DQS_c_ECC, can be left unconnected without ECC. DQS0_t_A DQS1_t_A
DQS_c_ECC, can be left unconnected without ECC. DQS0_t_A DQS1_t_A
DQS_c_ECC, can be left unconnected without ECC. DQS0_t DQS1_t
PS_DDR_DQS_P2
DQS2_t_A
DQS2_t_A
DQS2_t
PS_DDR_DQS_P3
DQS3_t_A
DQS3_t_A
DQS3_t
PS_DDR_DQS_P4
DQS0_t_B
DQS0_t_B
Can be left unconnected.
PS_DDR_DQS_P5
DQS1_t_B
DQS1_t_B
Can be left unconnected.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
110
Chapter 2: PS Memory Interface Pin Guidelines
Table 2-4: LPDDR3 Supported Pinout Configurations) (Cont'd)
Pin Name
LPDDR3 64-bit
PS_DDR_DQS_P6 PS_DDR_DQS_P7 PS_DDR_DQS_P8
PS_DDR_ODT0 PS_DDR_ODT1 PS_DDR_PARITY PS_DDR_RAM_RST_N PS_DDR_ZQ
DQS2_t_B DQS3_t_B DQS_t_ECC, can be left unconnected without ECC. ODT_A and ODT_B ODT_CA_B Can be left unconnected. Can be left unconnected. Connect a 240 resistor to GND.(2)
LPDDR3 64-bit (Dual Rank)
DQS2_t_B DQS3_t_B DQS_t_ECC, can be left unconnected without ECC. ODT_A and ODT_B Can be left unconnected. Can be left unconnected. Can be left unconnected. Connect a 240 resistor to GND.(2)
LPDDR3 32-bit (Dual Rank)
Can be left unconnected. Can be left unconnected. DQS_t_ECC, can be left unconnected without ECC. ODT Can be left unconnected. Can be left unconnected. Can be left unconnected. Connect a 240 resistor to GND.(2)
Notes: 1. For VCCO_PSDDR decoupling guidelines, see the UltraScale Architecture PCB Design Guide [Ref 14]. 2. There should be separate 240 resistors at the FPGA and at the DRAM.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
111
Chapter 3
Package Files
About ASCII Package Files
The ASCII package files for each Zynq� UltraScale+TM device include a comma-separated-values (CSV) version and a text version optimized for a browser or text editor in fixed-width fonts. The information in each of the files includes: � Device/Package name (family-device-package), with date and time of creation � Seven columns containing data for each pin:
� Pin--Pin location on the package. � Pin Name--The name of the assigned pin. � Memory Byte Group--Memory byte group between 0 and 3 split into upper (U) and
lower (L) halves. For more information on the memory byte group, see the UltraScale Architecture-Based Memory Interface Solutions Product Guide (PG150) [Ref 15]. � Bank--Bank number. � I/O Type--CONFIG, HD, HP, GTH, GTY, PS-GTR, PSMIO, PSDDR, or PSCONFIG depends on the I/O type. For more information on the I/O type, see the UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 6]. � Super Logic Region--Number corresponding to the super logic region (SLR) in the devices implemented with stacked silicon interconnect (SSI) technology. � Total number of pins in the package.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
112
Chapter 3: Package Files
Package Specifications Designations
Package specifications are designated as evaluation only, engineering sample, or production. Each designation is defined as follows.
Evaluation Only
These package specifications are based on initial device specifications, package routability analysis and mechanical package construction. Package specifications with this designation are not stable and package pinouts are likely to change and these specifications should only be used for initial system level design feasibility.
Engineering Sample
These package specifications are based on a released package design and validated with ES engineering sample (ES) devices. Package specifications with this designation are considered stable, however some pinout and mechanical specifications might change prior to the production release of the particular device. Package pinouts with this designation are to be used for PCB and Vivado� designs using ES devices.
Production
These package specifications are released coincident with production release of a particular device. Customers receive formal notification of any subsequent changes.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
113
Chapter 3: Package Files
ASCII Pinout Files
Links to the ASCII pinout information device/package combinations are listed in Table 3-1. Download all available package/device/pinout files at:
www.xilinx.com/support/package-pinout-files/zynq-ultrascale-plus-pkgs.html Note: All package files are ASCII files in TXT and CSV file format. Only the available files listed in
Table 3-1 are linked and consolidated in this ZIP file:
www.xilinx.com/support/packagefiles/zuppackages/zupall.zip
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q.
Table 3-1: Package/Device Pinout Files for CG, EG, and EV devices
Packages
Footprint Compatible Devices
SBVA484
XCZU2CG XCZU2EG XAZU2EG Production
XCZU3CG XCZU3EG XAZU3EG Production
SFRA484 SFVA625 SFVC784
XQZU3EG Production XCZU2CG XCZU2EG XAZU2EG Production
XCZU2CG XCZU2EG XAZU2EG Production
XCZU3CG XCZU3EG XAZU3EG Production
XCZU3CG XCZU3EG XAZU3EG Production
XCZU4CG XCZU4EG XCZU4EV XAZU4EV Production
SFRC784
XQZU3EG Production
XQZU5EV Production
FBVB900
XCZU4CG XCZU4EG XCZU4EV Production
XCZU5CG XCZU5EG XCZU5EV Production
XCZU7CG XCZU7EG XCZU7EV Production
FFRB900
XQZU5EV Production
XQZU7EV Production
XCZU5CG XCZU5EG XCZU5EV XAZU5EV Production
XAZU7EV Production
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
114
Chapter 3: Package Files
Table 3-1: Package/Device Pinout Files for CG, EG, and EV devices (Cont'd)
Packages
FFVC900 FFRC900
XCZU6CG XCZU6EG Production
XQZU9EG Production
Footprint Compatible Devices
XCZU9CG XCZU9EG Production
XCZU15EG Production
XQZU15EG
Production
FFVB1156 FFRB1156
XCZU6CG XCZU6EG Production
XQZU9EG Production
XCZU9CG XCZU9EG Production
XQZU15EG Production
XCZU15EG Production
FFVC1156
XCZU7CG XCZU7EG XCZU7EV Production
XCZU11EG Production
FFRC1156 FFVB1517
XQZU7EV Production
XCZU11EG Production
XQZU11EG Production
XCZU17EG Production
XCZU19EG Production
FFRB1517
XCZU19EG Production
FFVF1517
XCZU7CG XCZU7EG XCZU7EV Production
XCZU11EG Production
XAZU11EG Production
FFVC1760 FFRC1760
FFVD1760 FFVE1924
XCZU11EG Production
XQZU11EG Production XCZU17EG Production
XCZU17EG Production
XCZU17EG Production
XQZU19EG Production XCZU19EG Production
XCZU19EG Production
XCZU19EG Production
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
115
Chapter 3: Package Files
Table 3-2: Package/Device Pinout Files for Zynq UltraScale+ RFSoCs
Package
FFVD1156
XCZU21DR Production
Footprint Compatible Devices
FFRD1156 FFVE1156 FFRE1156
XQZU21DR Production
XCZU25DR Production
XQZU28DR Production
XCZU27DR Production
XCZU28DR Production
XCZU43DR Engineering
Sample
FSVE1156
XCZU25DR Production
XCZU27DR Production
XCZU28DR Production
XCZU43DR Engineering
Sample
FFVG1517
XCZU25DR Production
XCZU27DR Production
XCZU28DR Production
XCZU43DR Engineering
Sample
FFRG1517 FSVG1517
XQZU28DR Production
XCZU25DR Production
XCZU27DR Production
XCZU28DR Production
XCZU43DR Engineering
Sample
FFVF1760
XCZU29DR Production
XCZU39DR Production
XCZU49DR Engineering
Sample
FFVH1760
XCZU46DR Engineering
Sample
FFRF1760
XQZU29DR Production
FSVF1760 FSVH1760
XCZU29DR Production
XCZU46DR Engineering
Sample
XCZU39DR Production
XCZU49DR Engineering
Sample
XCZU47DR Engineering
Sample
XCZU47DR Engineering
Sample XCZU47DR Engineering
Sample
XCZU47DR Engineering
Sample
XCZU48DR Engineering
Sample
XCZU48DR Engineering
Sample XCZU48DR Engineering
Sample
XCZU48DR Engineering
Sample
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
116
Chapter 4
Device Diagrams
Summary
The diagrams in this chapter show top-view perspective of the package pinout of each Zynq� UltraScale+TM device/package combination. Table 4-1 is a cross reference to the device/package diagrams. The I/O-bank diagram shows the location of each user I/O, PSMIO, PSDDR, PSCONFIG, and PS-GTR, GTH, and GTY transceiver and the respective bank or GT quad. The configuration-power diagram shows the location of every power pin and dedicated as well as multi-function configuration pin in the package. See Package Specifications Designations in Chapter 3 for definitions of Evaluation Only, Engineering Sample, and Production device diagrams.
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q.
Table 4-1: Cross-Reference to Zynq UltraScale+ Device Diagrams by Package
Packages
SBVA484
XCZU2CG, XCZU2EG, XAZU2EG Production page 121
XCZU3CG, XCZU3EG, XAZU3EG Production page 121
Footprint Compatible Devices
SFRA484 SFVA625
XCZU2CG, XCZU2EG, XAZU2EG Production page 123
XQZU3EG Production page 121
XCZU3CG, XCZU3EG, XAZU3EG Production page 123
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
117
Chapter 4: Device Diagrams
Table 4-1: Cross-Reference to Zynq UltraScale+ Device Diagrams by Package (Cont'd)
Packages
SFVC784
XCZU2CG, XCZU2EG, XAZU2EG Production page 125
XCZU3CG, XCZU3EG, XAZU3EG Production page 125
Footprint Compatible Devices
XCZU4CG, XCZU4EG, XCZU5CG, XCZU5EG
XCZU4EV, XCZU5EV, XAZU4EV, XAZU5EV
Production
Production
page 127
page 129
SFRC784 FBVB900 FFRB900
XCZU4CG, XCZU4EG, XCZU5CG, XCZU5EG Production page 131
XQZU3EG Production page 125
XCZU4EVand XCZU5EV Production page 133
XQZU5EV Production page 133
XCZU7CG, XCZU7EG Production page 135
XQZU5EV Production page 129
XCZU7EV XAZU7EV Production page 137
XQZU7EV Production page 137
FFVC900 FFRC900
XCZU6CG, XCZU6EG Production page 139
XCZU9CG, XCZU9EG Production page 139
XQZU9EG Production page 139
XCZU15EG Production page 139
XQZU15EG Production page 139
FFVB1156
XCZU6CG, XCZU6EG Production page 141
FFRB1156
XCZU9CG, XCZU9EG Production page 141
XQZU9EG Production page 141
XCZU15EG Production page 141
XQZU15EG Production page 141
FFVC1156
XCZU7CG, XCZU7EG Production page 143
XCZU7EV Production page 145
XCZU11EG Production page 147
FFRC1156
XQZU7EV Production page 145
XQZU11EG Production page 147
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
118
Chapter 4: Device Diagrams
Table 4-1: Cross-Reference to Zynq UltraScale+ Device Diagrams by Package (Cont'd)
Packages
FFVD1156
FFRD1156
FFVE1156 FSVE1156
XCZU21DR Production page 149
XQZU21DR Production page 149
XCZU25DR Production page 151
Footprint Compatible Devices
XCZU27DR Production page 153
XCZU28DR Production page 153
XCZU43DR Production page 155
XCZU47DR Production page 157
FFRE1156
XQZU28DR Production page 153
FFVB1517
XCZU11EG Production page 161
XCZU17EG Production page 163
XCZU19EG Production page 163
FFRB1517
XQZU19EG Production page 163
FFVF1517
FFVG1517 FSVG1517
XCZU7CG, XCZU7EG Production page 165
XCZU25DR Production page 171
XCZU7EV Production page 167
XCZU27DR Production page 173
XCZU11EG Production page 169
XCZU28DR Production page 173
XAZU11EG Production page 169
XCZU43DR Production page 175
XCZU47DR Production page 177
FFRG1517
XQZU28DR Production page 173
FFVC1760 FFRC1760
XCZU11EG Production page 181
XQZU11EG Production page 181
XCZU17EG Production page 183
XCZU19EG Production page 183
XQZU19EG Production page 183
FFVD1760
XCZU17EG Production page 185
XCZU19EG Production page 185
XCZU48DR Production page 159
XCZU48DR Production page 179
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
119
Chapter 4: Device Diagrams
Table 4-1: Cross-Reference to Zynq UltraScale+ Device Diagrams by Package (Cont'd)
Packages
FFVF1760 FSVF1760
FFVH1760 FSVH1760
XCZU29DR Production page 187
XCZU46DR Production page 191
XCZU39DR Production page 187
Footprint Compatible Devices
XCZU49DR Production page 189
FFRF1760
XQZU29DR Production page 187
FFVE1924
XCZU17EG Production page 193
XCZU19EG Production page 193
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
120
Chapter 4: Device Diagrams
SBVA484 Package�XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG
IMPORTANT: For the devices in the SBVA484 package, the HP I/Os in bank 66 are powered by VCCO_65.
X-Ref Target - Figure 4-1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A
S 12 12 12 10 10 9
45 48 50 58
69 70
B 11 11 6V5CCO
11 11 12 2V6CCO 9 41 44 47
57 65 68 75 77
C 24 22 7
8 8 38 39 5V01CCO 46 51 55 62 5V02CCO 72
D 21 24 22
7556
36 40 42 49 5V02CCO 60 66 73 74
E 21
20 20 3 3 2V6CCO 6 33 35 37
43 56 59 64
F 19 23 23 S
2 4 4 29 5V01CCO 31 32 34 53
63 71 76
G 19 17 6V5CCO 18 1 1 2
26 30 27 28 5V03CCO 52 54 61 67
H 17 S 18 16
DI
CK
RC
MD 5V03CCO
PI
MD
33 505
22 505
3 3
505
2 2
505
A
B 3 3 505 C
D 2 2 505 E
F 1 1 505 G
H 1 1 505
J 15 13 13 16 K 15 6V5CCO 14 14
MS DO
MD MD PO
PR SR PG IN EO
ES
1 1
505
J K 0 0
505
L 11 11 12 12
DN
0 0
L
505
M 9 9 10 10
G0 0M 505
N 7S88
70 71
N
P7
2 6 6V5CCO
P 69 5V04CCO P 67 65
R5
246
T5114
21 23
68 DM N 66
R
T RS
ZQ 5V04CCO AL
64
U3 3
0 3 4 20
DM 22 24 25
29 AC BG BA
U PA CS CE CE
V
2
8
7
9 5V00CCO 18
N
P 19
P
N
28 31 5V04CCO BA
C
CN
C
5V04CCO CS
V
W 1 11 13
14 21 17 16
3 27 26 DM
30 A A BG
W CN OD OD
Y6
16 15 18 25
5P19
P
12 14
A
5V04CCO
A
A
A
Y A
5V04CCO
AA 5 10 17 19 5V00CCO 22 7 4 N
8 10 N 13
AAAA
A A AA
AB 12
20 23 24 6
DM 2 0 11
DM 15 A
A
5V04CCO
A
A
A
AB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Bank 26 Bank 65 Bank 66 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504
PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
V
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-1: SBVA484 Package--XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
121
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-2
V
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
12345
A
B
C 35
D 34
E
F
33
G
H
J
K
L
M
N
P
R
38
T
U
V
W
Y
AA
AB
12345
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
VA
V
B
C
V
D
E
E
F
G
E
H
J
E
K
24 21
PL PL
AU AU
L
22 23
PL
DP DP AU AU
M
87
L P L P F P BT
D D
N
LP LP
AD AD D D
P
LP LP FP FP
R
13 15
FP FP FP
FP DD
T
U
V
W
Y
AA
AB
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Dedicated Pins
Multi-Function I/O Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
PS Pins
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-2: SBVA484 Package--XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
122
Chapter 4: Device Diagrams
SFVA625 Package�XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG
X-Ref Target - Figure 4-3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A
8 8 S 19 19 24 22 22 3
2 30 39 41
57 58 60 65
33
A
505
B 7 10 10 21 23 24 20
4 3 2 29
43 47 55 59
69
B 3 3 505
C7
12 12 21 23 20 6 4 5
31 38 46 48
61 62 70
D 9 9 11 11 6V6CCO 14 14 S 6 5 2V6CCO 1 32 36 5V01CCO 51 56 63 66 5V02CCO
E33
2 13 13 S 6V6CCO 7 8 8 1 5V01CCO 34 44 50 53 5V02CCO 71 72
F
5 4 2 15
18 16 7 10 2V6CCO 12 33 35 42
54 64 75 73
G 1 5 4 6V6CCO 15 17 18 16
10 11 12 27 5V01CCO 40 49 52 68 5V02CCO 74
22 505
3 3
505
2 2
505
C
D 2 2 505 E
F 1 1 505 G
H1
6 6 17
J 15 17 17 23 24 24
K 15 18 23 21 21 22
L
18 13 S 19 6V5CCO 22
9 9 11
26 28 37 45
67 77 76
MD
MD
MD
EO 5V03CCO
RC CK
PI
5V03CCO PO
MD
DI
DO MS IN ES
1 1
505
G
0 0
505
H 1 1 505 J
K 0 0 505 L
M 16 16 13 20 19 S
PG
PR
M 0 0 505
N 3 14 14 20
SR DN 69
N
P 3 5 5 11 6V5CCO 10 10
70 P DM 67
P
R 1 1 11 12 12 8
71 N
65 66 R
T
699
8
U 2 6 4 7 6V5CCO 7 S
V2
4SS
6V4CCO
0
W 23 20 20 22
12 10 10 3 5V00CCO
Y 23 19 22 11 12 8
AA
19 24 24 11 6V4CCO 8
AB 21 21 13 14 1 9
46
77 5 9 6V4CCO 9
AC S 13 14 1
66 8
AD 17 15 16 16 5 5 2 2 4
AE 17 15 18 18 3 3
4 11
2 5V00CCO 16 1 10 15
7 13
20 7
12 18 6
14
5
17 21 4
19 25
23 22 5V00CCO 24 23 DM 21
0 P2 N
31
T 68 64 CE CS
RS ZQ AL
AU
AC
BG
BA
BG 5V04CCO PA
OD
A
V
19 DM 16 A 22 P 5V04CCO 17
N 20 18
A BA
AAC
A
5V04CCO CN
9 DM 14
26 29 A
8 5V04CCO 15 27 P
N
10 P 13 25 5V04CCO DM 31
11 N
12 24 28 30
CS CE
W
Y OD A
AA C CN A
AB A
5V04CCO
A
A A A AC
AA
AD
AE A
5V04CCO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Bank 26 Bank 64 Bank 65 Bank 66 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503
PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
V
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-3: SFVA625 Package--XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
123
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-4
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VA
V
B
C
V
D
E
E
F
G
E
H
35 34
J
33
K
L
PL PL PL
M
24 21
DP DP
AU BT
N
22 23
L P
L P AU AU
P
87
LP LP LP
AU D D
R
F P
L P AD AD D D
T
38
FP FP FP FP
D D
U
15 13
FP FP
V
W
Y
AA
AB
AC
AD
AE
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
V
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-4: SFVA625 Package--XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
124
Chapter 4: Device Diagrams
SFVC784 Package�XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG
X-Ref Target - Figure 4-5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A 8 8 9 10 19 21 21 23 23 10 11 11 3 2 1 57 62 65 75
3 3
3 3
A
B7
9 10 19 20 6V6CCO 22 24 9 10 2V5CCO 3 2 1 55
505 67 71 76
33
505
B 2 2
C 7 12 12 11 20 S 22 24
9 12 4 4 2V6CCO 56 60 68 70
505
2 2
22
505
C
D 2 S 6V6CCO 11 14 13 13
18 7 8 12
5 5 53 61 5V02CCO 69 74
505
11
505
D 1 1
E 2 3 5 5 14 6V6CCO S 17 18 7 2V5CCO 8 6 6 8
59 63 64
505
1 1
00
505
E
F134
6 15 16 17
5 6 6 7 8 2V6CCO 30 54 58
505
505
77
G0 0
F 0 0
G1
4
6 15 16 3 5
7 9 9 29 5V02CCO 52 66 72 73
505
505
61 60
G
H 8 S 10 10 6V5CCO 20 21 24 24
3 4 10 10
31 35 38 39 5V01CCO 47 45 DM 40
DM 59 58 H
J 8 9 6V5CCO 19 19 20 21
23 1 1 4
11 27 32 37
41 44 48 44
41 63 P N 56 J
K 7 9 11 11 S 22 22 23 L 7 12 12 6V5CCO 14 13 13 18
M
14 18
2 2 11 28
36 40 43 45
46 N 43 62
57 52 K
12 12 26 33 34 42 5V01CCO 46 51 47 P
50 51 DM 53 L
5V03CCO 49 50 ES DN
N 42 48 49
54 M
N
15 15 17 17
P
16 16 S
PI PO SR
MS 35 P 39
P N 55 N
P PR
EO 5V03CCO MD
MD
IN
34 5V04CCO 37 70 68 67 66
R
654
T
654
U
32
V
32
RC PG DI CK MD
33 DM 38 69
P 65 R
T MD DO 32 36 5V04CCO 71 DM N 64
RS ZQ AL OD
U OD
BG
BA
PA 5V04CCO CS
CE
CE
V
W
1 10 11 11 9 9
BA
W BG C CN CS A
Y
1 11 10 12 10 10
A
AC
C
CN 5V04CCO
A
AY
AA
11
9 9 12 7 2V4CCO
AA
AA A A A A
AB 18 17 15 15 S 6 5 3 12 12 8
788
5V00CCO 23 24 22 25 5V04CCO A
A
A
A
A AB
AC 18 17 14 14 6V4CCO 6 5 3 1 8 4V4CCO 6 6 6
9 12 17 18
21 A A A
16 28 31 AC
AD 16 16 13 13
4 1 6V4CCO 7 7 6 5 2V4CCO 5 5 10
20 2 0 11 5V04CCO 19 18 17 29 30 AD
AE 22 21 S 12 4 2 2 4
5 4 1 1 5V00CCO 11 15 19 1
10 DM 14 DM
P DM AE
AF 24 22 21 12 11 11 8
4254
2 6 8 16
3
P
8
P
5V04CCO
P
N
N 26 AF
AG 24
20 19 10 10 6V4CCO 8 7 1 2 3 4V4CCO 2
0
1 5V00CCO 14
7
DM
N
N 15 23 20
27 AG
AH 23 23 20 19
S 9 9 7 1 3 3 3 2 3 4 7 13 6 5 4 9 12 13 21 22 24 25 AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Bank 24 Bank 25 Bank 26 Bank 44 Bank 64 Bank 65 Bank 66 PS Bank 500
PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
V
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-5: SFVC784 Package--XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
125
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A
V
A
B
E
B
C
V
C
D
E
V
D
E
V
E
F
F
G
G
H
35 34
H
J
J
K
33
K
L
L
M
M
Nn n n n
N
Pnn
n
P
R
nn
38
24 21
R
Tnn
n
22 23
PL PL PL
T
U
n n n 15
87
DP
n DP AU AU
U
Vnn
nnn
n n L P L P L P AU
V
W
n n n 13
LP LP LP
n AU AD
W
Ynn
nnn
F P
n F P BT D D AD
Y
AA
FP FP FP FP
DD DD
AA
AB
F P
AB
AC
AC
AD
AD
AE
AE
AF
AF
AG
AG
AH
AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
V
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
Dedicated Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
Multi-Function I/O Pins
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
PS Pins
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-6: SFVC784 Package--XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
126
Chapter 4: Device Diagrams
SFVC784 Package�XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG
X-Ref Target - Figure 4-7
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A 8 8 9 10 19 21 21 23 23 10 11 11 3 2 1 57 62 65 75
3 3
3 3
A
B7
9 10 19 20 6V6CCO 22 24 9 10 4V5CCO 3 2 1 55
505 67 71 76
33
505
B 2 2
C 7 12 12 11 20 S 22 24
9 12 4 4 4V6CCO 56 60 68 70
505
2 2
22
505
C
D 2 S 6V6CCO 11 14 13 13
18 7 8 12
5 5 53 61 5V02CCO 69 74
505
11
505
D 1 1
E 2 3 5 5 14 6V6CCO S 17 18 7 4V5CCO 8 6 6 8
59 63 64
505
1 1
00
505
E
F134
6 15 16 17
5 6 6 7 8 4V6CCO 30 54 58
505
505
77
G0 0
F 0 0
G1
4
6 15 16 3 5
7 9 9 29 5V02CCO 52 66 72 73
505
505
61 60
G
H 8 S 10 10 6V5CCO 20 21 24 24
3 4 10 10
31 35 38 39 5V01CCO 47 45 DM 40
DM 59 58 H
J 8 9 6V5CCO 19 19 20 21
23 1 1 4
11 27 32 37
41 44 48 44
41 63 P N 56 J
K 7 9 11 11 S 22 22 23 L 7 12 12 6V5CCO 14 13 13 18
M
14 18
2 2 11 28
36 40 43 45
46 N 43 62
57 52 K
12 12 26 33 34 42 5V01CCO 46 51 47 P
50 51 DM 53 L
5V03CCO 49 50 ES DN
N 42 48 49
54 M
N
G3
3
224
P3 3 224
15 15 17 17 16 16 S
PI PO SR
MS 35 P 39
P N 55 N
P PR
EO 5V03CCO MD
MD
IN
34 5V04CCO 37 70 68 67 66
R
2
2
224
T2 2 224
654 654
RC PG DI CK MD
33 DM 38 69
P 65 R
T MD DO 32 36 5V04CCO 71 DM N 64
U
1
1
224
V1 1 224
1 1
224
32 32
RS ZQ AL OD
U OD
BG
BA
PA 5V04CCO CS
CE
CE
V
W
Y0 0 224
AA
0
0
224
0 0
224
1 10 11 11 9 9
1 11 10 12 10 10
11
9 9 12 7 4V4CCO
BA
BG C CN CS
A
AC
C
CN 5V04CCO
A
AA
AAA
AW AY A AA
AB 18 17 15 15 S 6 5 3 12 12 8
788
5V00CCO 23 24 22 25 5V04CCO A
A
A
A
A AB
AC 18 17 14 14 6V4CCO 6 5 3 1 8 4V3CCO 6 6 6
9 12 17 18
21 A A A
16 28 31 AC
AD 16 16 13 13
4 1 6V4CCO 7 7 6 5 4V4CCO 5 5 10
20 2 0 11 5V04CCO 19 18 17 29 30 AD
AE 22 21 S 12 4 2 2 4
5 4 1 1 5V00CCO 11 15 19 1
10 DM 14 DM
P DM AE
AF 24 22 21 12 11 11 8
4254
2 6 8 16
3
P
8
P
5V04CCO
P
N
N 26 AF
AG 24
20 19 10 10 6V4CCO 8 7 1 2 3 4V3CCO 2
0
1 5V00CCO 14
7
DM
N
N 15 23 20
27 AG
AH 23 23 20 19
S 9 9 7 1 3 3 3 2 3 4 7 13 6 5 4 9 12 13 21 22 24 25 AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Bank 43 Bank 44 Bank 45 Bank 46 Bank 64 Bank 65 Bank 66 Quad 224
PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-7: SFVC784 Package--XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
127
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A
V
A
B
E
B
C
V
C
D
E
V
D
E
V
E
F
F
G
G
H
35 34
H
J
J
K
33
K
L
L
M
M
N
N
P
V
P
R
38
24 21
R
T
V
22 23
PL PL PL
T
U
15
87
DP
R DP AU AU
U
V
E
R R L P L P L P AU
V
W
13
LP LP LP
R AU AD
W
Y
E
F P
R F P BT D D AD
Y
AA
FP FP FP FP
DD DD
AA
AB
F P
AB
AC
AC
AD
AD
AE
AE
AF
AF
AG
AG
AH
AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
V
V V
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
Dedicated Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
Multi-Function I/O Pins
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
PS Pins
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-8: SFVC784 Package--XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
128
Chapter 4: Device Diagrams
SFVC784 Package�XCZU4EV, XCZU5EV, XAZU4EV, and XAZU5EV
X-Ref Target - Figure 4-9
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A 8 8 9 10 19 21 21 23 23 10 11 11 3 2 1 57 62 65 75
3 3
3 3
A
B7
9 10 19 20 6V6CCO 22 24 9 10 4V5CCO 3 2 1 55
505 67 71 76
33
505
B 2 2
C 7 12 12 11 20 S 22 24
9 12 4 4 4V6CCO 56 60 68 70
505
2 2
22
505
C
D 2 S 6V6CCO 11 14 13 13
18 7 8 12
5 5 53 61 5V02CCO 69 74
505
11
505
D 1 1
E 2 3 5 5 14 6V6CCO S 17 18 7 4V5CCO 8 6 6 8
59 63 64
505
1 1
00
505
E
F134
6 15 16 17
5 6 6 7 8 4V6CCO 30 54 58
505
505
77
G0 0
F 0 0
G1
4
6 15 16 3 5
7 9 9 29 5V02CCO 52 66 72 73
505
505
61 60
G
H 8 S 10 10 6V5CCO 20 21 24 24
3 4 10 10
31 35 38 39 5V01CCO 47 45 DM 40
DM 59 58 H
J 8 9 6V5CCO 19 19 20 21
23 1 1 4
11 27 32 37
41 44 48 44
41 63 P N 56 J
K 7 9 11 11 S 22 22 23 L 7 12 12 6V5CCO 14 13 13 18
M
14 18
2 2 11 28
36 40 43 45
46 N 43 62
57 52 K
12 12 26 33 34 42 5V01CCO 46 51 47 P
50 51 DM 53 L
5V03CCO 49 50 ES DN
N 42 48 49
54 M
N
G3
3
224
P3 3 224
15 15 17 17 16 16 S
PI PO SR
MS 35 P 39
P N 55 N
P PR
EO 5V03CCO MD
MD
IN
34 5V04CCO 37 70 68 67 66
R
2
2
224
T2 2 224
654 654
RC PG DI CK MD
33 DM 38 69
P 65 R
T MD DO 32 36 5V04CCO 71 DM N 64
U
1
1
224
V1 1 224
1 1
224
32 32
RS ZQ AL OD
U OD
BG
BA
PA 5V04CCO CS
CE
CE
V
W
Y0 0 224
AA
0
0
224
0 0
224
1 10 11 11 9 9
1 11 10 12 10 10
11
9 9 12 7 4V4CCO
BA
BG C CN CS
A
AC
C
CN 5V04CCO
A
AA
AAA
AW AY A AA
AB 18 17 15 15 S 6 5 3 12 12 8
788
5V00CCO 23 24 22 25 5V04CCO A
A
A
A
A AB
AC 18 17 14 14 6V4CCO 6 5 3 1 8 4V3CCO 6 6 6
9 12 17 18
21 A A A
16 28 31 AC
AD 16 16 13 13
4 1 6V4CCO 7 7 6 5 4V4CCO 5 5 10
20 2 0 11 5V04CCO 19 18 17 29 30 AD
AE 22 21 S 12 4 2 2 4
5 4 1 1 5V00CCO 11 15 19 1
10 DM 14 DM
P DM AE
AF 24 22 21 12 11 11 8
4254
2 6 8 16
3
P
8
P
5V04CCO
P
N
N 26 AF
AG 24
20 19 10 10 6V4CCO 8 7 1 2 3 4V3CCO 2
0
1 5V00CCO 14
7
DM
N
N 15 23 20
27 AG
AH 23 23 20 19
S 9 9 7 1 3 3 3 2 3 4 7 13 6 5 4 9 12 13 21 22 24 25 AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Bank 43 Bank 44 Bank 45 Bank 46 Bank 64 Bank 65 Bank 66 Quad 224
PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-9: SFVC784 Package--XCZU4EV, XCZU5EV, XAZU4EV, and XAZU5EV I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
129
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A
V
A
B
E
B
C
V
C
D
E
V
D
E
V
E
F
F
G
G
H
35 34
H
J
J
K
33
K
L
L
M
M
N
N
P
V
P
R
38
24 21
R
T
V
22 23
PL PL PL
T
U
15
87
DP
DP AU AU
U
V
E
L P L P L P AU
V
W
13
LP LP LP
AU AD
W
Y
E
F P
F P BT D D AD
Y
AA
FP FP FP FP
DD DD
AA
AB
F P
AB
AC
AC
AD
AD
AE
AE
AF
AF
AG
AG
AH
AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
V
V V
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-10: SFVC784 Package--XCZU4EV, XCZU5EV, XAZU4EV, and XAZU5EV Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
130
Chapter 4: Device Diagrams
FBVB900 Package�XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG
X-Ref Target - Figure 4-11
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
3 3
226
B2 2 226
C
1 1
226
D0 0 226
E
3 3
225
F2 2 225
G
1 1
225
H0 0 225
J
3 3
224
K2 2 224
L
2
2
224
M1 1 224
N
0 0
224
P3 3 223
R
3
3
223
T2 2 223
U
1 1
223
V0 0 223
W
0
0
223
YS
AA 24 24 22 6V6CCO
AB 23 22 17
AC 23 21 21 17 AD 20 19 6V6CCO 16
AE 20 19 S 16
AF S 24 24
AG 23 22 22
AH 23 21 21 S
2
2
226
0
0
226
2
2
225
0
0
225
3
3
224
1
1
224
0
0
224
2
2
223
1
1
223
18 18 14 14
8 15 8 15 18 18 14 14
13
3
3
226
1
1
226
3
3
225
1
1
225
1 1
224
G
0 0
224
1 1
226
0 0
226
1 1
225
0 0
225
1 1
223
0 0
223
9S
10 9
6
10 12 6
12 5 5
11 11 7 13 7 6V6CCO 4
13 10 10
99
6
11 S 6V5CCO 6
12 11 8 6V5CCO
12 11 11
12 10
9 8 10 9 8 4V6CCO
677
65 5 4 4V6CCO
334
2
3
1122
1
2214
3
14
31
3
41
6V5CCO
22
3
22 S 6V4CCO
3
7 11
3 1 7 11
12 11 11 24 20 1 28 31 54 52 56 57 59 58
12 10
25 2 26 27 5V01CCO 35 34 53 55 5V02CCO 62
9 10 17 5
30 33 38 40
60 66 67
8
9
7 5V00CCO 3
6 29 36 5V01CCO 41 65 70 69 5V02CCO
8 7 4V5CCO
14 7
8 5V01CCO 39 42 44 77 5V02CCO 72 76
6 6 22 10 5V00CCO 9 37 43 45
55 4 4V5CCO
34
11 13 32 49
0 12 21
51
4 5V00CCO 15 50 48
3 3
505
33 505
22 505
2 2
505
2 19 16 18 23 46 47
2 2
505
11 505
1
CK DI MS
1 1
505
PG DO PI
G 0 0
IN
PR 5V03CCO PO
DN
505
00 505
5V03CCO RC SR MD MD 40 47
P
43 62 DM
MD MD ES
EO 41 DM N
63 P
42
44 46 61 60
45 32 34 48
50
33 35
49 51 DM
P N 71 69
39 DM 36
70 P
5 16
37 5V04CCO 38 68 DM N
5 16
ZQ
AL
RS
PA 5V04CCO CE
6V4CCO 15 17 17 S
P
28 29 31 5V04CCO BA BG BG
6 15 14 18 20 N 16
P
30 AC
BA 5V04CCO
6
14 24 18 22
17 27
N
DM 5V04CCO
A
A
12 13 13 24
21 DM 18 25
26
12 19 6V4CCO 23 S 23 19
24 10 14
AAC
A
5V04CCO CN
19 21 23 7
108P
15 A A
63
A
61 64 B
68
C
75 71 D
74 73 E
F
G 3 3 505 H
J 1 1 505 K
L 0 0 505 M
N
59 58 P
N 56 R
57 T
P 52 U
N 53 V
55 54 W
67 66 Y
65 AA
64 OD AB
AC OD CE
AD CS CS
A C AE
CN AF
A A AG
A A AH
AJ 20 20 17 16 13 12 8 5 4 1
9 10 20 21
5 DM P 2
N DM 12 A
A A AJ
AK
19 19 17 16 15 15 7 7 5 4 8 8 9 10 20 22 22 6 4 N 3 9 11 13 5V04CCO A A A
AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Bank 45 Bank 46 Bank 64 Bank 65 Bank 66 Quad 223 Quad 224 Quad 225
Quad 226 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-11: FBVB900 Package--XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
131
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-12
V
V V
1234 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 35 34 AG 33 AH AJ AK
1234
5678 V V V V V E V E V V E V E V V 15 13
5678
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
E
A
B
E
C
D
E
F
G
V
H
E
J
V
K
E
V
L
M
N
P
R
24 21
PL
PL PL AU
T
22 23
DP DP BT AU
U
87
LP LP LP
AU AU
V
L P
L P L P AD AD
W
FP FP FP FP FP
D D
Y
F P
FP DD DD
AA
RRRR
AB
AC
AD
AE
AF
AG
AH
38
AJ
AK
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-12: FBVB900 Package--XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
132
Chapter 4: Device Diagrams
FBVB900 Package�XCZU4EV and XCZU5EV
X-Ref Target - Figure 4-13
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A B2
2 226
3 3
226
2
2
226
3
3
226
1 1
226
12 11 11 12 11 11 24 20 1 28 31 54 52 56 57 59 58 63
A
12 10 12 10
B 25 2 26 27 5V01CCO 35 34 53 55 5V02CCO 62 61 64
C
D0 0 226
E
F2 2 225
G
H0 0 225
J
1 1
226
3 3
225
1 1
225
3 3
224
0
0
226
2
2
225
0
0
225
1
1
226
3
3
225
1
1
225
1 1
224
0 0
226
1 1
225
0 0
225
9 8 10
9 10 17 5
30 33 38 40
60 66 67 68
C
9 8 8 9 7 D 4V6CCO
5V00CCO 3
6 29 36 5V01CCO 41 65 70 69 5V02CCO 75 71
6
7
7
8 7 4V5CCO
14 7
E 8 5V01CCO 39 42 44 77 5V02CCO 72 76 74 73
65
6 6 22 10 5V00CCO 9 37 43 45
F
5 4V6CCO 33 2
455 4 4 4V5CCO
334
11 13 32 49
0 12 21
51
4 5V00CCO 15 50 48
3 3
505
33 505
22 505
2 2
505
G 3 3 505 H
J 1 1 505
K2 2 224
3
3
G
224
1 1 2 2 2 19 16 18 23 46 47
2 2
505
11
K
505
L
2
2
224
0 0
224
11
CK DI MS
1 1
505
L 0 0 505
M1 1 224
N
P3 3 223
0 0
224
1
1
224
0
0
224
1 1
223
PG DO PI
G 0 0
00
M
IN
PR 5V03CCO PO
DN
505
505
N
P 5V03CCO RC SR MD MD 40 47 P 43 62 DM 59 58
R
3
3
223
0 0
223
MD MD ES
EO 41 DM N
63 P N 56 R
T2 2 223
2
2
223
42
44 46 61 60
57 T
U
1 1
223
45 32 34 48
50 P 52 U
V0 0 223
1
1
223
33 35
49 51 DM N 53 V
W
0
0
223
9S
P N 71 69
55 54 W
YS
10 9
6
39 DM 36
70 P 67 66 Y
AA 24 24 22 6V6CCO 18 18 10 12
622
AB 23 22 17 14 14 12 5 5 3
AC 23 21 21 17 8 11 11 7
31
AD 20 19 6V6CCO 16 15 8 13 6V6CCO 7 4 4 1
AE 20 19 S 16 15
13 10 10
6V5CCO
AF S 24 24 18 18 9 9
622
1 4 5 16
37 5V04CCO 38 68 DM N
65 AA
1 4 5 16
AB ZQ
AL
RS
PA 5V04CCO CE
64 OD
3 6V4CCO 15 17 17 S
AC P
28 29 31 5V04CCO BA
BG BG OD CE
3 6 15 14 18 20 N 16
P
30 AC
BA 5V04CCO CS
CS AD
226
14 24 18 22
17 27
N
DM 5V04CCO
A
A
A
C AE
S 6V4CCO 12 13 13 24
21 DM 18 25
26 A A C
CN AF
AG 23
22 22 14 14 6V5CCO 11 S 6 3
7 11 12 19 6V4CCO 23 S 23 19
24 10 14
A
5V04CCO CN
A
AH 23 21 21 S
13 12 11 8 6V5CCO 3 1 7 11
19 21 23 7
108P
15 A A A
A AG A AH
AJ 20 20 17 16 13 12 8 5 4 1
9 10 20 21
5 DM P 2
N DM 12 A
A A AJ
AK
19 19 17 16 15 15 7 7 5 4 8 8 9 10 20 22 22 6 4 N 3 9 11 13 5V04CCO A A A
AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Bank 45 Bank 46 Bank 64 Bank 65 Bank 66 Quad 223 Quad 224 Quad 225
Quad 226 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-13: FBVB900 Package--XCZU4EV and XCZU5EV I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
133
X-Ref Target - Figure 4-14
Chapter 4: Device Diagrams
V
V V
1234 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 35 34 AG 33 AH AJ AK
1234
5678 V V V V V E V E V V E V E V V 15 13
5678
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
E
A
B
E
C
D
E
F
G
V
H
E
J
V
K
E
V
L
M
N
P
R
24 21
PL
PL PL AU
T
22 23
DP DP BT AU
U
87
LP LP LP
AU AU
V
L P
L P L P AD AD
W
FP FP FP FP FP
D D
Y
F P
FP DD DD
AA
AB
AC
AD
AE
AF
AG
AH
38
AJ
AK
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-14: FBVB900 Package--XCZU4EV and XCZU5EV Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
134
Chapter 4: Device Diagrams
FBVB900 Package�XCZU7CG and XCZU7EG
V V
X-Ref Target - Figure 4-15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A B2
2 227
C D0
0 227
E F2
2 226
G H0
0 226
J K2
2 225
L M1
1 225
N P3
3 224
R T2
2 224
U V0
0 224
W
YS
AA 24 24 AB 23
AC 23 21
AD 20 19
AE 20 19
AF S 24
AG 23 AH 23 21
3 3
227
1 1
227
3 3
226
1 1
226
3 3
225
2
2
225
0 0
225
3
3
224
1 1
224
0
0
224
2
2
227
0
0
227
2
2
226
0
0
226
3
3
225
1
1
225
0
0
225
2
2
224
1
1
224
22 6V6CCO 18 18 22 17 14 14 21 17 8 6V6CCO 16 15 8 S 16 15 24 18 18 22 22 14 14 21 S 13
3
3
227
1
1
227
3
3
226
1
1
226
1 1
225
G
0 0
225
1 1
227
0 0
227
1 1
226
0 0
226
1 1
224
0 0
224
9S
10 9
6
10 12 6
12 5 5
11 11 7 13 7 6V6CCO 4
13 10 10
99
6
11 S 6V5CCO 6
12 11 8 6V5CCO
12 11 11 12 11 11 24 20 1 28 31 54 52 56 57 59 58
12 10 12 10
25 2 26 27 5V01CCO 35 34 53 55 5V02CCO 62
9 8 10
9 10 17 5
30 33 38 40
60 66 67
9 8 4V7CCO
8
9
7 5V00CCO 3
6 29 36 5V01CCO 41 65 70 69 5V02CCO
67 65 5 4V7CCO
33
2
7 8 7 4V8CCO
14 7 8 5V01CCO 39 42 44 77 5V02CCO 72 76
6 6 22 10 5V00CCO 9 37 43 45
455 4 4 4V8CCO
334
11 13 32 49
0 12 21
51
4 5V00CCO 15 50 48
3 3
505
33 505
22 505
2 2
505
1 1 2 2 2 19 16 18 23 46 47
2 2
11
505
505
11
CK DI MS
1 1
505
PG DO PI
G 0 0
IN
PR 5V03CCO PO
DN
505
00 505
5V03CCO RC SR MD MD 40 47
P
43 62 DM
MD MD ES
EO 41 DM N
63 P
42
44 46 61 60
45 32 34 48
50
33 35
49 51 DM
P N 71 69
22 3 31 41
6V5CCO
22 3 31
39 DM 36
70 P
1 4 5 16
37 5V04CCO 38 68 DM N
1 4 5 16
ZQ
AL
RS
PA 5V04CCO CE
3 6V4CCO 15 17 17 S
P
28 29 31 5V04CCO BA
BG BG
3 6 15 14 18 20 N 16
P
30 AC
BA 5V04CCO
226
14 24 18 22
17 27
N
DM 5V04CCO
A
A
S 6V4CCO 12 13 13 24
21 DM 18 25
26 A A C
7 11 12 19 6V4CCO 23 S 23 19
24 10 14
A
5V04CCO CN
7 11 19 21 23 7
108P
15 A A
63
A
61 64 B
68
C
75 71 D
74 73 E
F
G 3 3 505 H
J 1 1 505 K
L 0 0 505 M
N
59 58 P
N 56 R
57 T
P 52 U
N 53 V
55 54 W
67 66 Y
65 AA
64 OD AB
AC OD CE
AD CS CS
A C AE
CN AF
A A AG
A A AH
AJ 20 20 17 16 13 12 8 5 4 1
9 10 20 21
5 DM P 2
N DM 12 A
A A AJ
AK
19 19 17 16 15 15 7 7 5 4 8 8 9 10 20 22 22 6 4 N 3 9 11 13 5V04CCO A A A
AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Bank 47 Bank 48 Bank 64 Bank 65 Bank 66 Quad 224 Quad 225 Quad 226
Quad 227 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-15: FBVB900 Package--XCZU7CG and XCZU7EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
135
X-Ref Target - Figure 4-16
Chapter 4: Device Diagrams
V
V V
1234 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 35 34 AG 33 AH AJ AK
1234
5678 V V V V V E V E V V E V E V V 15 13
5678
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
E
A
B
E
C
D
E
F
G
V
H
E
J
V
K
E
V
L
M
N
P
R
24 21
PL
PL PL AU
T
22 23
DP DP BT AU
U
87
LP LP LP
AU AU
V
L P
L P L P AD AD
W
FP FP FP FP FP
D D
Y
F P
FP DD DD
AA
RRRR
AB
AC
AD
AE
AF
AG
AH
38
AJ
AK
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-16: FBVB900 Package--XCZU7CG and XCZU7EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
136
Chapter 4: Device Diagrams
FBVB900 Package�XCZU7EV
X-Ref Target - Figure 4-17
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
3 3
3
3
227
227
B2 2 227
2
2
227
C
1 1
1
1
227
227
D0 0 227
0
0
227
E
3 3
3
3
226
226
F2 2 226
2
2
226
G
1 1
1
1
226
226
H0 0 226
0
0
226
J
3 3
225
1 1
225
K2 2 225
3
3
G
225
L
2
2
225
0 0
225
M1 1 225
1
1
225
N
0 0
225
1 1
224
P3 3 224
0
0
225
R
3
3
224
0 0
224
T2 2 224
2
2
224
U
1 1
224
V0 0 224
1
1
224
W
0
0
9
224
YS
10 9
AA 24 24 22 6V6CCO 18 18 10 12
1 1
227 0
0 227 1
1 226 0
0 226
S 6 6
AB 23 22 17 14 14 12 5 5
AC 23 21 21 17 8 11 11 7 AD 20 19 6V6CCO 16 15 8 13 6V6CCO 7 4
AE 20 19 S 16 15 13 10 10
AF S 24 24 18 18 9 9
6
AG 23
22 22 14 14 6V5CCO 11 S 6
AH 23 21 21 S
13 12 11 8 6V5CCO
12 11 11 12 11 11 24 20 1 28 31 54 52 56 57 59 58
12 10 12 10
25 2 26 27 5V01CCO 35 34 53 55 5V02CCO 62
9 8 10
9 10 17 5
30 33 38 40
60 66 67
9 8 4V7CCO
8
9
7 5V00CCO 3
6 29 36 5V01CCO 41 65 70 69 5V02CCO
67 65 5 4V7CCO
33
2
7 8 7 4V8CCO
14 7 8 5V01CCO 39 42 44 77 5V02CCO 72 76
6 6 22 10 5V00CCO 9 37 43 45
455 4 4 4V8CCO
334
11 13 32 49
0 12 21
51
4 5V00CCO 15 50 48
3 3
505
33 505
22 505
2 2
505
1 1 2 2 2 19 16 18 23 46 47
2 2
11
505
505
11
CK DI MS
1 1
505
PG DO PI
G 0 0
IN
PR 5V03CCO PO
DN
505
00 505
5V03CCO RC SR MD MD 40 47
P
43 62 DM
MD MD ES
EO 41 DM N
63 P
42
44 46 61 60
45 32 34 48
50
33 35
49 51 DM
P N 71 69
22 3 31 41
6V5CCO
22 3 31
39 DM 36
70 P
1 4 5 16
37 5V04CCO 38 68 DM N
1 4 5 16
ZQ
AL
RS
PA 5V04CCO CE
3 6V4CCO 15 17 17 S
P
28 29 31 5V04CCO BA
BG BG
3 6 15 14 18 20 N 16
P
30 AC
BA 5V04CCO
226
14 24 18 22
17 27
N
DM 5V04CCO
A
A
S 6V4CCO 12 13 13 24
21 DM 18 25
26 A A C
7 11 12 19 6V4CCO 23 S 23 19
24 10 14
A
5V04CCO CN
7 11 19 21 23 7
108P
15 A A
63
A
61 64 B
68
C
75 71 D
74 73 E
F
G 3 3 505 H
J 1 1 505 K
L 0 0 505 M
N
59 58 P
N 56 R
57 T
P 52 U
N 53 V
55 54 W
67 66 Y
65 AA
64 OD AB
AC OD CE
AD CS CS
A C AE
CN AF
A A AG
A A AH
AJ 20 20 17 16 13 12 8 5 4 1
9 10 20 21
5 DM P 2
N DM 12 A
A A AJ
AK
19 19 17 16 15 15 7 7 5 4 8 8 9 10 20 22 22 6 4 N 3 9 11 13 5V04CCO A A A
AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Bank 47 Bank 48 Bank 64 Bank 65 Bank 66 Quad 224 Quad 225 Quad 226
Quad 227 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins Transceiver Pins
PS Pins
VREF MGTAVTTRCAL G MGTRREF
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-17: FBVB900 Package--XCZU7EV I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
137
X-Ref Target - Figure 4-18
Chapter 4: Device Diagrams
V
V V
1234 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 35 34 AG 33 AH AJ AK
1234
5678 V V V V V E V E V V E V E V V 15 13
5678
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
E
A
B
E
C
D
E
F
G
V
H
E
J
V
K
E
V
L
M
N
P
R
24 21
PL
PL PL AU
T
22 23
DP DP BT AU
U
87
LP LP LP
AU AU
V
L P
L P L P AD AD
W
FP FP FP FP FP
D D
Y
F P
FP DD DD
AA
AB
AC
AD
AE
AF
AG
AH
38
AJ
AK
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-18: FBVB900 Package--XCZU7EV Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
138
Chapter 4: Device Diagrams
FFVC900 Package�XCZU6EG, XCZU9EG, and XCZU15EG
X-Ref Target - Figure 4-19
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
B2 2 230
C
D0 0 230
E
F3 3 229
G
H1 1 229
J
K0 0 229
L
M2 2 228
N
P1 1 228
R
T6
3 3
230
1 1
230
3
3
229
2 2
229
0
0
229
3 3
228
1
1
228
0 0
228
U6 5 5 9
V44
8
W3 3
8
Y2211
AA 24 23 23
G
2
2
230
0
0
230
2
2
229
1
1
229
3
3
228
2
2
228
0
0
228
3
3
230
1
1
230
1 1
230
0 0
230
1 1
229
0 0
229
1 1
228
0 0
228
3 2 2 3 2 1 19 17 7 26 44 45 52 66
31
3 2 1 20
10 28 37 46
67
4144
18 15 0 27
49 54 68
645
5 5 21 16 5V00CCO 30 34 47 53 5V02CCO
6
5667
14 2 29 36 5V01CCO 56 69
8778
7 23 13 3
38 48 55 70
8 10
8 9 9 25 5V00CCO 4
11 4V8CCO 10 12 12 4V7CCO 22 1 6
12 12 11 11 4V7CCO 10 24 5
11 40 50 39 5V01CCO 57
31 51 58
71
60 75 64 5V02CCO
24 9 4V8CCO 9 11 10 5V00CCO 12 24 23 23 22 21
8 32 41
63 72
9 5V01CCO 43 59 76 77 33 42 61 5V02CCO 74
22 S 21
35
62 65 73
20 20 19 19 18
SR RC EO ES
MS
CK 5V03CCO
PI
PO
DN 5V03CCO DO
DI
PG
IN
9 10 10 13 17 18 15
6V6CCO 11 11 13 17
15
7 12 12 6V6CCO
16 16
7 6V6CCO S 14 14 S
15 15 10 10 6V5CCO
55
MD MD MD MD
PR 47 DM 42 32
G
1 1
128
0 0
128
3 3
505
2 2
505
1 1
505
0 0
505
G
46 44 P
43 41 33 34 35
33 128
22 128
11 128
00 128
33 505
22 505
11 505
00 505
45 N 62 40 59 58 57 56
A
B 3 3 128 C
D 2 2 128 E
F 1 1 128 G
H 0 0 128 J
K 3 3 505 L
M 2 2 505 N
P 1 1 505 R
T 0 0 505 U
63 61 V
P 60 W
Y N DM
48 AA
AB 24 19 18 13 13 12 7 6 6
1
P N DM
51 49 50 AB
AC 22 21 19 18 6V5CCO 14 11 12 7
4
1 PA
RS AC
ZQ 39
36 52 P N DM AC
AD 22 21
17 16 14 11 6V5CCO 9 8 4 3
20 22 21 23
AL A A A
37 38 BG 53
54 55 AD
AE S 20 20 17 16 S S 9 8
3 2 DM P
24 25 27 26 5V04CCO A
A
A
AE A 5V04CCO 64 67 DM 71
AF 24 24 23
16 16 7 7 8 6V4CCO 1
2
N 19 P N
DM A A A
BA BG
65
69 AF
AG 22
23 S 13 13
12 S 8 1 6V4CCO 2 16 17 18
28 30 31
A
5V04CCO
C
CN
CS
BA 5V04CCO 66
P
70 AG
AH 22 20 20 18
14 11 12 9 6V4CCO
327
3 1 29 11
14
AA
OD CE
N 68 AH
AJ S 21 18 17 14 11 9 6 5 3
6PN2
10 P
N
15 5V04CCO CS CE
C
CN 5V04CCO OD
A AJ
AK 21 19 19 17 15 15 10 10 6 5 4 4 5 4 DM 0 9 8 DM 12 13
AA
A
A
5V04CCO
AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Bank 47 Bank 48 Bank 64 Bank 65 Bank 66 Quad 128 Quad 228 Quad 229
Quad 230 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins Transceiver Pins
PS Pins
VREF MGTAVTTRCAL G MGTRREF
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-19: FFVC900 Package--XCZU6EG, XCZU9EG, and XCZU15EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
139
X-Ref Target - Figure 4-20
Chapter 4: Device Diagrams
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
E
A
B
V
V
V
B
V V
C
V
C
D
V
E
V
D
E
V
E
F
V
E
V
F
G
E
E
G
V V
H
V
H
J
V
E
J
K
V
V
K
L
E
E
L
M
V
E
V
M
N
V
E
N
P
V
E
V
P
R
E
R
T
T
U
24 21
U
V
22 23
PL PL
PL AU AU
V
W
87
L P DP DP AU AU
W
Y
LP LP LP
AD
Y
AA 34 33
L P
L P F P AD BT
AA
AB 35
13 15
FP FP FP FP DD
AB
AC
38
FP FP
DD DD
AC
AD
AD
AE
AE
AF
AF
AG
AG
AH
AH
AJ
AJ
AK
AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
V
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-20: FFVC900 Package--XCZU6EG, XCZU9EG, and XCZU15EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
140
Chapter 4: Device Diagrams
FFVB1156 Package�XCZU6EG, XCZU9EG, and XCZU15EG
V
V V
X-Ref Target - Figure 4-21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
3 3
G3
3
230
230
99
4 3 12 12 12 11 11 57 64
B2 2 230
2
2
230
1 1
230
10 8 7 4 3
10 10 12 10 55 59 67
C
1 1
230
0 0
230
D0 0 230
1
1
230
E
0
0
230
1 1
229
F3 3 229
3
3
229
G
2
2
229
0 0
229
H2 2 229
1
1
229
J
1 1
229
1 1
228
10 8 7
2 9 11 11 10 9 56 61
4 4 11 6 5 2 9
7 8 9 7 5V02CCO 63 75
3
11 12 6 5 8 4V9CCO 8 7 8 7 4V7CCO 53 60 72
3 6 6 12 4V9CCO 1 1 6 6
6 5 52 54 5V02CCO 77
2 5 8 5V0CCO 9 9 11 4V8CCO 5 5 6 5 5V02CCO 58 62 74
2 5 7 8 10
11 2 1 1 3 4V7CCO 32 33 73 76
1 1 7 5V0CCO 10 12 12 2 4V8CCO 4 4 3 31
41 46
K0 0 229
L
M2 2 228
3 3
228
0
0
229
3
3
228
0 0
228
S
18 23 S 24 19 4 3 2 1
29 36 43 49
15 17 18 23
24 19 4 3 2 1 30 34 38 5V01CCO 47
15 17 22 20 20
27 5V01CCO 40 42 48
N
2
2
228
P1 1 228
1
1
228
16 16 13 21 22 6V7CCO 14 14 13 21
28 37 39 44 51
26 35
45 50
R
0
0
12 11 11 4 2
228
T0 0
10 10 12 6V7CCO 3 6 4 2
228
U
18 18 8 6V7CCO 9 9 3 6
ES MD MD MS CK
EO
MD
MD 5V03CCO DO
PG 5V03CCO SR
RC
DI
V 23 23 17 17 8 7 7 S
55
W 24 24
15 15 9 9 6V6CCO
11
Y 22 22 13 13 14
11 11 6 6 5 6V6CCO
AA 21 21 S
14 12 12 S 6V6CCO 3 3 5
PI PO PR IN DN
AB S 20 16 10 10 8 4 2 2
AC 19 19 20 16 7 7 8 4
11
AD 23 23
18 S 9 9 6V5CCO
6
2 7 20 23 22
AE 24 24 17 18 13 12 10 6 1
3 9 12 12 5V00CCO 8 18 25 24
AF 21 21 17
13 11 12 10 6V5CCO 1 4 3 9 11 4V4CCO 0 11 21
PA RS AL ZQ
A
AG S
20 14 14 11 6V5CCO 8 5 5 4
10 10 11 3 5V00CCO 23 22 20 24
27 26 AC
65 66 68 69 70 71
1 1
130
0 0
130
1 1
129
0 0
129
1 1
128
0 0
128
2 2
505
1 1
505
0 0
505
G
45 44 40 P
41 BA 5V04CCO 35
G
22 130
11 130
00 130
22 129
00 129
33 128
22 128
00 128
33 505
11 505
00 505
46 47 N DM
42 34 33
33 130
2 2
130
0 0
130
33 129
11 129
0 0
129
2 2
128
11 128
3 3
505
22 505
1 1
505
60 61 P
43 58 32
A
B 3 3 130 C
D 1 1 130 E
F 3 3 129 G
H 2 2 129 J
K 1 1 129 L
M 3 3 128 N
P 1 1 128 R
T 0 0 128 U
V 3 3 505 W
Y 2 2 505 AA
0 0 AB 505 AC
63 62 AD
N DM AE
59 AF
56 57 AG
AH 22 19 20 15 7 7 8 S
2277
AJ 22 19
15 16 16 S 6V4CCO 9 6
1 8 4V4CCO
AK 23 24 24 18 18
11 11 9 6 1 6V4CCO 6 5
AL 23 22 22
13 13 12 12 6V4CCO 3 2 6 4
4 10 21 P
25 P N DM
8 1 12
N 18 29 30
5V04CCO
A
5 5V00CCO 13 19 DM 17
28 31 A A
6 14 19 7
16 12 13 15 5V04CCO A
BA BG P N
DM 51 48 50 AH
OD CE 5V04CCO 39 36 DM
P
49 AJ
A BG 37 38
N 53 52 AK
C
CN
A 5V04CCO CS 55 54 71
AL
AM 21 S 17 14 14 8 8 3 2
4 2 5 16
6 5 4 DM
14 A A A
A A OD 68
69 70 AM
AN 21 19 20 17 16 10 7 5
321
15 DM P N
P
N
11
A
5V04CCO
C
CN
CS
CE 5V04CCO 64
P
N DM AN
AP S 19 20 15 15 16 10 7 5 4 4 3
1 9 17 3 1 2 0 9 8
10 A A A
A A 65 66 67
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Bank 44 Bank 47 Bank 48 Bank 49 Bank 50 Bank 64 Bank 65 Bank 66
Bank 67 Quad 128 Quad 129 Quad 130 Quad 228 Quad 229 Quad 230 PS Bank 500
PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins Transceiver Pins
PS Pins
VREF MGTAVTTRCAL G MGTRREF
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-21: FFVB1156 Package--XCZU6EG, XCZU9EG, and XCZU15EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
141
X-Ref Target - Figure 4-22
Chapter 4: Device Diagrams
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
E
A
B
V
E
V
B
C
E
V
C
D
V
E
V
D
E
E
V
E
V V
F
V
E
V
F
G
E
E
G
H
V
E
V
H
J
V
V
J
V V
K
V
E
V
K
L
V
E
L
M
V
V
M
N
V
V
N
P
V
E
V
P
R
E
R
T
T
U
24 21
U
V
22 23
E
V
V
W
87
PL
PL PL
E
W
Y
AU AU DP DP
E
V
Y
AA
L P BT AU
AU
E
AA
AB
L P
L P AD AD
V
AB
AC
L P L P L P F P AD AD
AC
AD 33
13 15
FP FP
DD FP FP
AD
AE 35 34
FP FP DD DD
AE
AF
38
nn
AF
AG
AG
AH
AH
AJ
AJ
AK
AK
AL
AL
AM
AM
AN
AN
AP
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
V
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-22: FFVB1156 Package--XCZU6EG, XCZU9EG, and XCZU15EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
142
Chapter 4: Device Diagrams
FFVC1156 Package�XCZU7CG and XCZU7EG
X-Ref Target - Figure 4-23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
3
B2
C2 5
D1 5
E14
F
G3 3 227
H
J2 2 227
K
L1 1 227
M
N0 0 227
P
R2 2 226
T
U1 1 226
V
W3 3 225
Y
AA 2 2 225
AB
AC 0 0 225
AD
AE 3 3 224
AF
AG 1 1 224
AH
AJ 0 0 224
AK
AL 2 2 223
AM
AN 1 1 223
AP
12
3 67 67 8 8V8CCO 48
9
3
3
227
2
2
227
0
0
227
3 3
226
1
1
226
0 0
226
2
2
225
1 1
225
3
3
224
2 2
224
0
0
224
3 3
223
1
1
223
0 0
223
34
10 21 23 23 S 22 24 5 5 3 3 1 1 19 19 21 21 23 23 0 4 6 14 16 26 27 28 29 30
A
10 21 20 20 22 24
4422
22 22 24 24
S 2 7 11
19 23 31 32 5V01CCO 33 34 B
19 19 8 8 18 6 6
7 8 20 20
15 15 17 1 5V00CCO 9 12 21 17
35 36 37 38 C
11 11 S
10 16 16 18 6V7CCO 11 11 7 8
7 9 9 17
16 5 8 13 5V00CCO 25 39 40 41
42 D
12 7 8V8CCO 9 10 14
17 S 12 12 6V7CCO 9 9 7 S 2V8CCO 11 13 16 3
15 24 20 43 5V01CCO 44 45 46 E
9 12 7 9 6V8CCO 12 14 17 10
14 13 13 17
10 12 11 13 2V8CCO S 10 18 22
47 48 49 50 51 F
10 11 12 11 12 13 6V8CCO S 10 14 18
17 15 10 12
14 14 18 18 5V03CCO DO 52 53 54
55 56 G
10 11 12 11
13 15 15
6V7CCO 18 16 16 15 2V8CCO 8 8
6
5 H MD MS 57 5V02CCO 58 59 60 61
9 9 8 8V7CCO 2 4
5 20 20 21 S S 3 3
6 5 MD DI
J 62 63 64 65 5V02CCO 66
7 8 2 4 6V8CCO 6 5 22
21 23 23 19
4 4 2 MD MD CK 67 68 69 70 71 72 73 K
1
1
227
3
3
226
2
2
226
0
0
226
3
3
225
1
1
225
0
0
225
2
2
224
1
1
224
3
3
223
2
2
223
7
6 3 3 1 6 22 24 24
19 1 1 2
PO
74 75
76 77 L
556431 2 2 4 8V7CCO 1 3
PR PI DN 5V03CCO
2 2
505
33 505
3 3
505
M N 3
3 505
1
IN SR
1 1
22
P
505
505
1 1
227
RC ES
11 505
R 2 2 505
0 0
227
PG EO
0 0
505
1 1
T
505
1 1
226
G 0 0 505
U 0 0 505
0 0
226
47
V
1 1
225
44 46 45 59 P N 61 62 W
0 0
225
P N DM 57
DM 60 63 Y
1 1
224
23 22 22 S 22 24 24
PA 41 42
56 58 48 49 50 AA
0 0
224
24 23 21 21 22 20
AL
43 32 33 53
P N AB
1 1
223
22 24 S 20 20 23 20
ZQ 40 38 34
36 DM 55 54 AC
0 0
223
G 22 20 19 24 24 23 21
RS BG
DM P N 35
52 AD
23 21 20 19 6V4CCO 15 19 19 21
S 18 18 AE AC 5V04CCO BA BA 39 37 5V04CCO 65 67 51
18 6V6CCO 19 19 23 21
17 17 15 14 6V5CCO S 17 17 16
16 A BG A
A A 64 68 DM AF
18 16 17 17 6V6CCO 15 18 18
14 15 15 14 16 6V5CCO 20 17 18 5V04CCO A A A
S 16
14 13 15 16 6V4CCO S 13 13 S
14 13 13 DM
P 25 24 30
A
5V04CCO
P
N AG
A CE 66 69 AH
12 11 14 13
16 12 12 11 6V4CCO 9 11 12 12
22 19
N
26 5V04CCO DM
A
AJ A
OD 5V04CCO 70
10 12 11 6V6CCO 9 7 10 10
11 9 9 11 6V5CCO 10 10 23 21
27 P N A
CS A 71 AK
10 8 8 9 7
88S9
7788
5 28 29 31 5V04CCO C
C CN A
A AL
6655
S477
32
4
67 6 3
8 DM 15 12
A A AM
0
0
223
44
3124
6632
4 5 6 DM
PN9P
AN 14 CN CE A
22312
5 5 1 1 1 1 3 3 5 4 1 2 0 11 10 N 13 OD CS
AP
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Bank 28 Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 87 Bank 88
Quad 223 Quad 224 Quad 225 Quad 226 Quad 227 PS Bank 500 PS Bank 501 PS Bank 502
PS Bank 503 PS Bank 504 PS Quad 505
V V
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-23: FFVC1156 Package--XCZU7CG and XCZU7EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
143
X-Ref Target - Figure 4-24
Chapter 4: Device Diagrams
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
V
M
N
E
V
N
P
V
V
P
R
E
E
R
T
V
E
24 21
V
T
U
E
22 23
DP
U
V
V
87
L P
PL DP AU
V
W
E
LP LP
PL AU AU
W
Y
V
L P L P BT PL AU
Y
AA
E
13 15
34 35
L P F P AD AD
AA
AB
V
E
FP FP FP FP DD
AB
AC
E
33
FP FP
DD DD
AC
AD
V
RRRR
AD
AE
AE
AF
V
AF
AG
AG
AH
V
AH
AJ
AJ
AK
V
AK
AL
AL
AM
V
38
AM
AN
AN
AP
V
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
V
V V
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-24: FFVC1156 Package--XCZU7CG and XCZU7EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
144
Chapter 4: Device Diagrams
FFVC1156 Package�XCZU7EV
X-Ref Target - Figure 4-25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
3
B2
C2 5
D1 5
E14
F
G3 3 227
H
J2 2 227
K
L1 1 227
M
N0 0 227
P
R2 2 226
T
U1 1 226
V
W3 3 225
Y
AA 2 2 225
AB
AC 0 0 225
AD
AE 3 3 224
AF
AG 1 1 224
AH
AJ 0 0 224
AK
AL 2 2 223
AM
AN 1 1 223
AP
12
3 67 67 8 8V8CCO 48
9
3
3
227
2
2
227
0
0
227
3 3
226
1
1
226
0 0
226
2
2
225
1 1
225
3
3
224
2 2
224
0
0
224
3 3
223
1
1
223
0 0
223
34
10 21 23 23 S 22 24 5 5 3 3 1 1 19 19 21 21 23 23 0 4 6 14 16 26 27 28 29 30
A
10 21 20 20 22 24
4422
22 22 24 24
S 2 7 11
19 23 31 32 5V01CCO 33 34 B
19 19 8 8 18 6 6
7 8 20 20
15 15 17 1 5V00CCO 9 12 21 17
35 36 37 38 C
11 11 S
10 16 16 18 6V7CCO 11 11 7 8
7 9 9 17
16 5 8 13 5V00CCO 25 39 40 41
42 D
12 7 8V8CCO 9 10 14
17 S 12 12 6V7CCO 9 9 7 S 2V8CCO 11 13 16 3
15 24 20 43 5V01CCO 44 45 46 E
9 12 7 9 6V8CCO 12 14 17 10
14 13 13 17
10 12 11 13 2V8CCO S 10 18 22
47 48 49 50 51 F
10 11 12 11 12 13 6V8CCO S 10 14 18
17 15 10 12
14 14 18 18 5V03CCO DO 52 53 54
55 56 G
10 11 12 11
13 15 15
6V7CCO 18 16 16 15 2V8CCO 8 8
6
5 H MD MS 57 5V02CCO 58 59 60 61
9 9 8 8V7CCO 2 4
5 20 20 21 S S 3 3
6 5 MD DI
J 62 63 64 65 5V02CCO 66
7 8 2 4 6V8CCO 6 5 22
21 23 23 19
4 4 2 MD MD CK 67 68 69 70 71 72 73 K
1
1
227
3
3
226
2
2
226
0
0
226
3
3
225
1
1
225
0
0
225
2
2
224
1
1
224
3
3
223
2
2
223
7
6 3 3 1 6 22 24 24
19 1 1 2
PO
74 75
76 77 L
556431 2 2 4 8V7CCO 1 3
PR PI DN 5V03CCO
2 2
505
33 505
3 3
505
M N 3
3 505
1
IN SR
1 1
22
P
505
505
1 1
227
RC ES
11 505
R 2 2 505
0 0
227
PG EO
0 0
505
1 1
T
505
1 1
226
G 0 0 505
U 0 0 505
0 0
226
47
V
1 1
225
44 46 45 59 P N 61 62 W
0 0
225
P N DM 57
DM 60 63 Y
1 1
224
23 22 22 S 22 24 24
PA 41 42
56 58 48 49 50 AA
0 0
224
24 23 21 21 22 20
AL
43 32 33 53
P N AB
1 1
223
22 24 S 20 20 23 20
ZQ 40 38 34
36 DM 55 54 AC
0 0
223
G 22 20 19 24 24 23 21
RS BG
DM P N 35
52 AD
23 21 20 19 6V4CCO 15 19 19 21
S 18 18 AE AC 5V04CCO BA BA 39 37 5V04CCO 65 67 51
18 6V6CCO 19 19 23 21
17 17 15 14 6V5CCO S 17 17 16
16 A BG A
A A 64 68 DM AF
18 16 17 17 6V6CCO 15 18 18
14 15 15 14 16 6V5CCO 20 17 18 5V04CCO A A A
S 16
14 13 15 16 6V4CCO S 13 13 S
14 13 13 DM
P 25 24 30
A
5V04CCO
P
N AG
A CE 66 69 AH
12 11 14 13
16 12 12 11 6V4CCO 9 11 12 12
22 19
N
26 5V04CCO DM
A
AJ A
OD 5V04CCO 70
10 12 11 6V6CCO 9 7 10 10
11 9 9 11 6V5CCO 10 10 23 21
27 P N A
CS A 71 AK
10 8 8 9 7
88S9
7788
5 28 29 31 5V04CCO C
C CN A
A AL
6655
S477
32
4
67 6 3
8 DM 15 12
A A AM
0
0
223
44
3124
6632
4 5 6 DM
PN9P
AN 14 CN CE A
22312
5 5 1 1 1 1 3 3 5 4 1 2 0 11 10 N 13 OD CS
AP
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Bank 28 Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 87 Bank 88
Quad 223 Quad 224 Quad 225 Quad 226 Quad 227 PS Bank 500 PS Bank 501 PS Bank 502
PS Bank 503 PS Bank 504 PS Quad 505
V V
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins Transceiver Pins
PS Pins
VREF MGTAVTTRCAL G MGTRREF
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-25: FFVC1156 Package--XCZU7EV I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
145
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
V
M
N
E
V
N
P
V
V
P
R
E
E
R
T
V
E
24 21
V
T
U
E
22 23
DP
U
V
V
87
L P
PL DP AU
V
W
E
LP LP
PL AU AU
W
Y
V
L P L P BT PL AU
Y
AA
E
13 15
34 35
L P F P AD AD
AA
AB
V
E
FP FP FP FP DD
AB
AC
E
33
FP FP
DD DD
AC
AD
V
AD
AE
AE
AF
V
AF
AG
AG
AH
V
AH
AJ
AJ
AK
V
AK
AL
AL
AM
V
38
AM
AN
AN
AP
V
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
V
V V
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-26: FFVC1156 Package--XCZU7EV Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
146
Chapter 4: Device Diagrams
FFVC1156 Package�XCZU11EG
X-Ref Target - Figure 4-27
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
3
B2
C2 5
D1 5
E14
F
G3 3 228
H
J2 2 228
K
L1 1 228
M
N0 0 228
P
R2 2 227
T
U1 1 227
V
W3 3 226
Y
AA 2 2 226
AB
AC 0 0 226
AD
AE 3 3 225
AF
AG 1 1 225
AH
AJ 0 0 225
AK
AL 2 2 224
AM
AN 1 1 224
AP
12
3 67 67 8 8V9CCO 48
9
3
3
228
2
2
228
0
0
228
3 3
227
1
1
227
0 0
227
2
2
226
1 1
226
3
3
225
2 2
225
0
0
225
3 3
224
1
1
224
0 0
224
34
10 21 23 23 S 22 24 5 5 3 3 1 1 19 19 21 21 23 23 0 4 6 14 16 26 27 28 29 30
A
10 21 20 20 22 24
4422
22 22 24 24
S 2 7 11
19 23 31 32 5V01CCO 33 34 B
19 19 8 8 18 6 6
7 8 20 20
15 15 17 1 5V00CCO 9 12 21 17
35 36 37 38 C
11 11 S
10 16 16 18 6V8CCO 11 11 7 8
7 9 9 17
16 5 8 13 5V00CCO 25 39 40 41
42 D
12 7 8V9CCO 9 10 14
17 S 12 12 6V8CCO 9 9 7 S 6V7CCO 11 13 16 3
15 24 20 43 5V01CCO 44 45 46 E
9 12 7 9 6V9CCO 12 14 17 10
14 13 13 17
10 12 11 13 6V7CCO S 10 18 22
47 48 49 50 51 F
10 11 12 11 12 13 6V9CCO S 10 14 18
17 15 10 12
14 14 18 18 5V03CCO DO 52 53 54
55 56 G
10 11 12 11
13 15 15
6V8CCO 18 16 16 15 6V7CCO 8 8
6
5 H MD MS 57 5V02CCO 58 59 60 61
9 9 8 8V8CCO 2 4
5 20 20 21 S S 3 3
6 5 MD DI
J 62 63 64 65 5V02CCO 66
7 8 2 4 6V9CCO 6 5 22
21 23 23 19
4 4 2 MD MD CK 67 68 69 70 71 72 73 K
1
1
228
3
3
227
2
2
227
0
0
227
3
3
226
1
1
226
0
0
226
2
2
225
1
1
225
3
3
224
2
2
224
7
6 3 3 1 6 22 24 24
19 1 1 2
PO
74 75
76 77 L
556431 2 2 4 8V8CCO 1 3
PR PI DN 5V03CCO
2 2
505
33 505
3 3
505
M N 3
3 505
1
IN SR
1 1
22
P
505
505
1 1
228
RC ES
11 505
R 2 2 505
0 0
228
PG EO
0 0
505
1 1
T
505
1 1
227
G 0 0 505
U 0 0 505
0 0
227
47
V
1 1
226
44 46 45 59 P N 61 62 W
0 0
226
P N DM 57
DM 60 63 Y
1 1
225
23 22 22 S 22 24 24
PA 41 42
56 58 48 49 50 AA
0 0
225
24 23 21 21 22 20
AL
43 32 33 53
P N AB
1 1
224
22 24 S 20 20 23 20
ZQ 40 38 34
36 DM 55 54 AC
0 0
224
G 22 20 19 24 24 23 21
RS BG
DM P N 35
52 AD
23 21 20 19 6V4CCO 15 19 19 21
S 18 18 AE AC 5V04CCO BA BA 39 37 5V04CCO 65 67 51
18 6V6CCO 19 19 23 21
17 17 15 14 6V5CCO S 17 17 16
16 A BG A
A A 64 68 DM AF
18 16 17 17 6V6CCO 15 18 18
14 15 15 14 16 6V5CCO 20 17 18 5V04CCO A A A
S 16
14 13 15 16 6V4CCO S 13 13 S
14 13 13 DM
P 25 24 30
A
5V04CCO
P
N AG
A CE 66 69 AH
12 11 14 13
16 12 12 11 6V4CCO 9 11 12 12
22 19
N
26 5V04CCO DM
A
AJ A
OD 5V04CCO 70
10 12 11 6V6CCO 9 7 10 10
11 9 9 11 6V5CCO 10 10 23 21
27 P N A
CS A 71 AK
10 8 8 9 7
88S9
7788
5 28 29 31 5V04CCO C
C CN A
A AL
6655
S477
32
4
67 6 3
8 DM 15 12
A A AM
0
0
224
44
3124
6632
4 5 6 DM
PN9P
AN 14 CN CE A
22312
5 5 1 1 1 1 3 3 5 4 1 2 0 11 10 N 13 OD CS
AP
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 69 Bank 88 Bank 89
Quad 224 Quad 225 Quad 226 Quad 227 Quad 228 PS Bank 500 PS Bank 501 PS Bank 502
PS Bank 503 PS Bank 504 PS Quad 505
V V
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-27: FFVC1156 Package--XCZU11EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
147
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
V
M
N
E
V
N
P
V
V
P
R
E
E
R
T
V
E
24 21
V
T
U
E
22 23
DP
U
V
V
87
L P
PL DP AU
V
W
E
LP LP
PL AU AU
W
Y
V
L P L P BT PL AU
Y
AA
E
13 15
L P F P AD AD
AA
AB
V
E
FP FP FP FP DD
AB
AC
E
33
FP FP
DD DD
AC
AD
V
34 n n n n
AD
AE
35
AE
AF
V
AF
AG
AG
AH
V
38
AH
AJ
AJ
AK
V
AK
AL
AL
AM
V
AM
AN
AN
AP
V
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
V
V V
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
Dedicated Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
Multi-Function I/O Pins
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
PS Pins
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-28: FFVC1156 Package--XCZU11EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
148
Chapter 4: Device Diagrams
FFVD1156 Package�XCZU21DR
X-Ref Target - Figure 4-29
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
12 20 21 21 23 24 24 24 23 29 26 43
52 54 55 59 63
B 11 11 12 20 22 22 23 24 22 21 23 20
42 45 48 53
61 62
22
C 10 10
19 19 17 17
18 19 22 21
20 27 44 46 5V01CCO 56 57 60 64
131
D
799S
16 16 18 19 6V8CCO S 18 18 41
49 51 74 58 5V02CCO 67
00
E 6 6 7 8V9CCO 15 13 14 14
17 17 16 16 6V8CCO 32 34 47 50
76 66 69
131
F5
8 8 15 13 6V7CCO 12 S 15 15
14 14 S 33 5V01CCO 39 40 75 65
22
G5 3 3 4
11 11 12 9 6V7CCO 13 13 12 12
31 37 36 38 5V02CCO 73 68
130
H 2 2 4 8V9CCO 7 10 10
9
11 11 6V8CCO 8 6 28 30
35 70 72 71 77 PI
J
1 1 S 7 8 6V7CCO 8 6 6
7 10 8 6
233
PO
33 131
11 131
33 130
1 1
131
G
K 2 4 4 10 2 4 4
L 2 6 8V8CCO 8 10 2
3
M 1 5 6 8 1 8V8CCO 1 3
5 9 7 10 5 4 4 2
59
S5
11
MD
EO MD ES MD 5V03CCO MD
N1 5
7 9 11 11
P
3 3 7 9 12 12
CK DI MS
RC
PG 5V03CCO
R2 3 3
6 7 10 10
PR DO
T2
4
U1 1 4
V 24 24
567 5 8 8V7CCO
SS9
11 11
8 12 12 9 8V7CCO
IN SR DN
W 23 23 18 18 15 17 17
Y 21 22 22 14 14 15 16
AA 21 19 12 13 13 16
AB 20 20 19 12 6V6CCO 11 11 10 10
AC 2 2
5 S 9 9 8 6V6CCO
AD 3 4 5 6
778
11 9 7 4
0
AE 1 3 4 6 6V6CCO
24 24
5V00CCO 8
532
AF 1
10 22 23 23 6V5CCO 20
15 13
10 6 1 BA
AG 8 8 10 22
21 21 20 19 5V00CCO 17 16 14 12
A A PA AL
35
40 45 44
36 32 41 P 46
ZQ 37 P N
N DM
AH 9 9
17 17 S 18 19 18 19 20
DM 23 22 A
A BG RS DM
33 43 42 47
AJ
12 12 14 14 6V5CCO 18 16 16 21
23 21 N
P
5V04CCO
A
A
AC BA 5V04CCO 39 38 34 53
48
AK 7 11 11
13 13 15 15 6V5CCO 22 24 25 20
19 18 A C
BG A 64 65
54 P 50
AL 7
S5
S
DM 7 9 8
25 24 17 16 5V04CCO CN
A
CS
A 5V04CCO 66
P
55
N
49
AM 4 6 6 5
6 P 43
P 15 27 P
31 C A A
OD CE 68 N
DM 51
AN 4 3
225 N
10 12 N DM
N
DM 30 CN 5V04CCO A
A
CS OD 5V04CCO DM 71 52 57
2 2
131
3 3
130
3 3
131
0 0
131
1 1
130
11 130
0 0
131
00 130
1 1
130
33 129
0 0
130
22 129
1 1
129
11 129
0 0
129
00 129
1 1
128
33 128
0 0
128
22 128
11 128
00 128
3 3
505
2 2
505
1 1
505
G
33 505
22 505
11 505
00 505
58
P DM
A
B 1 1 131 C
D 2 2 130 E
F 0 0 130 G
H 3 3 129 J
K 2 2 129 L
M 1 1 129 N
P 0 0 129 R
T 3 3 128 U
V 2 2 128 W
Y 1 1 128 AA
0 0 AB 128 AC
3 3 AD 505 AE
2 2 AF 505 AG
1 1 AH 505 AJ
0 0 AK 505 AL
0 0 AM 505 AN
AP 3 1 1 1
2 0 11 13
14 26 29 28
AAAA
CE 67 70 69
56 59 60 N 61 63 62
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Bank 65 Bank 66 Bank 67 Bank 68 Bank 87 Bank 88 Bank 89 Quad 128
Quad 129 Quad 130 Quad 131 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504
PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-29: FFVD1156 Package--XCZU21DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
149
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-30
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
V
A
B
V
B
C
V
C
D
V
D
E
V
E
F
E
F
G
E
G
H
E
H
J K L M N P R T U V W Y AA AB AC AD AE AF
n n n
24 21
n
22 23
87
35 34 33
13 15
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
E E
V
V
E
V
AU
AU
E
AU AD AD
V
AU PL
E
BT
PL L P
V
DP PL L P
D D DP
LP LP LP
V
FP FP FP FP LP
DD DD FP
FP FP
V
J K L M N P R T U V W Y AA AB AC AD AE AF
AG
E
AG
AH
V
AH
AJ
E
AJ
AK
V
AK
AL
AL
AM 38
AM
AN
AN
AP
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Power Pins
Dedicated Pins Multi-Function I/O Pins PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-30: FFVD1156 Package--XCZU21DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
150
Chapter 4: Device Diagrams
FFVE1156 and FSVE1156 Packages�XCZU25DR
X-Ref Target - Figure 4-31
V V
12
A
B
C1 1 229
D
E00 229
F
G3 3 228
H
J22 228
K L11
228
M
N0 0 228
P
R
T33 227
U
V11 227
W
Y33 226
AA AB 1 1
226
AC
AD 3 3 225
AE
AF 1 1 225
AG AH 3 3
224
AJ
AK 1 1 224
AL
AM
AN 6 6 AP 5
12
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
2
3
229
229
2
3
R
CC 229
CC 228
SS 228
CC 227
CC 226
CC 225
33
12 11 11 14
24 40 43 46
50 60 71 73
2 1 12 10
421 4 5 8V9CCO
665
9 10
897 8 7 8V8CCO
77
655
8 8V9CCO 8 6 4
9 9 11 8V8CCO 4 2
12 20 25 10 19 5V00CCO
15 23
8 17 22 9 5V00CCO 21
4 11 16
26
38
45 51
36 41 44 48 34 39 5V01CCO 47
37 42 49
18 32 35 13 5V01CCO 31 33
5 27 30 29
58 62
70 75
63 65 72 74
55 59 64
77
61 5V02CCO 69 68 76
53 57 66 67
52 56
5V02CCO
54
11 12 3 3
2 0 1 28
EO
10 10 12 1 1 3 7
26
MD PO PI
MD
MD
MD RC DI
PR
MS 5V03CCO
PG CK
IN SR ES DN 5V03CCO DO
3 3
129
33 129
22 129
11 129
1 1
129
G
0 0
129
00 129
33 128
1 1
128
22 128
0 0
128
11 128
3 3
505
00 128
2 2
505
33 505
G
1 1
505
22 505
0 0
505
11 505
46 44
00 505
19 22 22 23
47 45 P N
A
B 2 2 129 C
D 1 1 129 E
F 0 0 129 G
H 3 3 128 J
K 2 2 128 L
M 1 1 128 N
P 0 0 128 R
T 3 3 505 U
V 2 2 505 W
Y 1 1 505 AA
0 0 AB 505 AC
CC 224
VV 227
VV 226
VV 225
VV 224
19 21 23 S 24
43 42
41 DM 60 63 62 AD
24 6V6CCO 20 20 21 17
24
24 27 26 AL
34 32 40 61
DM 59 AE
R
24 23 23 15 15 6V5CCO 17 18 18
25 P 5V04CCO ZQ RS 35 33
57 P N 58 AF
21 21 19 19
16 13 S 14
21 22 20 DM
N
A
BA
PA 5V04CCO
P
N DM 56
48 AG
20 20 6V6CCO S 7 16 13
14 10 23 DM
29 28 31 A
AC 39 37 38
51 49 50 AH
22 22 18 S 7 6V5CCO 11 11 12 10
P N 16 30
A A BG BG
36 DM P N
AJ
17 17 18
15 8 8 12 6V5CCO 9 19 18 17
9 12 A
A 5V04CCO BA CE 55 54
53 52 AK
13 6V6CCO 16 16 15
S49 7
3 8 DM 13
A
C
A
AL A 5V04CCO 66 67 DM 71
3 3 10 10 13 12 14 14 1 2 4 5
6 DM 1 10
15 A A CN
A CS OD 65
69 AM
44
9 9 S 12 8 8 1 2
565 P
11
P
14
A
5V04CCO
A
C
A CS
P N 70 AN
5
2 2 1 1 11 11 7 7
3364
N20N
A
A
A
CN 5V04CCO OD CE 64 68
AP
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Bank 65 Bank 66 Bank 88 Bank 89 Quad 128 Quad 129 Bank 224 Bank 225
Bank 226 Bank 227 Bank 228 Bank 229 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503
PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP VREF
ADC/DAC Pins
# ADC_VIN_#_P # ADC_VIN_#_N C ADC_CLK_P C ADC_CLK_N R ADC_REXT V VCM01 V VCM23 # DAC_VOUT_#_P # DAC_VOUT_#_N C DAC_CLK_P C DAC_CLK_N R DAC_REXT S SYSREF_P S SYSREF_N
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
MGTAVTTRCAL G MGTRREF
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-31: FFVE1156 and FSVE1156 Packages--XCZU25DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
151
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-32
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A DAC DAC DAC
DAC
DAC
E
A
B DAC DAC DAC
DAC
DAC
B
C
DAC DAC DAC DAC DAC
E
C
D DAC
DAC
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
E
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
F DAC
DAC
DAC
DAC VTT
DAC
DAC
G
DAC
DAC VTT
DAC
DAC VCC
DAC VCC
H DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
J
DAC
DAC
DAC VCC
DAC
K DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
L
DAC
DAC
DAC VCC
DAC SUB
M DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
N
DAC
DAC
DAC VCC
DAC
P DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
R ADC ADC ADC DAC DAC DAC DAC DAC
T
ADC
ADC
ADC
DAC
DAC
DAC
VCC AMS
U ADC ADC ADC ADC ADC ADC DAC DAC
V
ADC
ADC
ADC
ADC
VCC AMS
W ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
Y
ADC
ADC
ADC VCC
ADC
VCC AMS
AA ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
AB
ADC
ADC
ADC VCC
ADC
VCC AMS
AC ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC SUB
AD
ADC
ADC
ADC VCC
ADC
VCC AMS
AE ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
AF
ADC
ADC
ADC
AG ADC ADC ADC
ADC
ADC AUX
AH
ADC
ADC
ADC AUX
AJ ADC ADC ADC
ADC
ADC AUX
AK
ADC
ADC
ADC
ADC
ADC AUX
AL ADC ADC ADC
15 13
24 21 22 23 87
33 34 35
38
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
V
E
V
n
nnn
V
n
V
V E
E
AU AU AU
E
BT AU
V
AD AD PL
E
F P DP DP PL PL
V
FP LP
LP LP
FP FP LP LP LP
V
FP FP DD
F P
DD DD
D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL
AM
AM
AN
AN
AP
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Power Pins
Dedicated Pins Multi-Function I/O Pins PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
VCC AMS
VCCINT_AMS
ADC VCC
ADC_AVCC
ADC AUX
ADC_AVCCAUX
ADC ADC_GND
ADC SUB
ADC_SUB_GND
DAC VCC
DAC_AVCC
DAC AUX
DAC_AVCCAUX
DAC VTT
DAC_AVTT
DAC DAC_GND
DAC SUB
DAC_SUB_GND
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-32: FFVE1156 and FSVE1156 Packages--XCZU25DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
152
Chapter 4: Device Diagrams
FFVE1156 and FSVE1156 Packages�XCZU27DR and XCZU28DR
V V
X-Ref Target - Figure 4-33
12
A
B
C1 1 229
D
E00 229
F
G3 3 228
H
J22 228
K L11
228
M
N0 0 228
P
R
T33 227
U
V11 227
W
Y33 226
AA AB 1 1
226
AC
AD 3 3 225
AE
AF 1 1 225
AG AH 3 3
224
AJ
AK 1 1 224
AL
AM
AN 6 6 AP 5
12
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
2 229
2
3 229
3
R
CC
229
CC
228
SS 228
CC
227
CC
226
CC
225
33
12 11 11 14
24 40 43 46
50 60 71 73
2 1 12 10
421 4 5 8V9CCO
665
9 10
897 8 7 8V8CCO
77
655
8 8V9CCO 8 6 4
9 9 11 8V8CCO 4 2
12 20 25 10 19 5V00CCO
15 23
8 17 22 9 5V00CCO 21
4 11 16
26
38
45 51
36 41 44 48 34 39 5V01CCO 47
37 42 49
18 32 35 13 5V01CCO 31 33
5 27 30 29
58 62
70 75
63 65 72 74
55 59 64
77
61 5V02CCO 69 68 76
53 57 66 67
52 56
5V02CCO
54
11 12 3 3
2 0 1 28
EO
10 10 12 1 1 3 7
26
MD PO PI
MD
MD
MD RC DI
PR
MS 5V03CCO
PG CK
IN SR ES DN 5V03CCO DO
3 3
129
33 129
22 129
11 129
1 1
129
G
0 0
129
00 129
33 128
1 1
128
22 128
0 0
128
11 128
3 3
505
00 128
2 2
505
33 505
G
1 1
505
22 505
0 0
505
11 505
46 44
00 505
19 22 22 23
47 45 P N
A
B 2 2 129 C
D 1 1 129 E
F 0 0 129 G
H 3 3 128 J
K 2 2 128 L
M 1 1 128 N
P 0 0 128 R
T 3 3 505 U
V 2 2 505 W
Y 1 1 505 AA
0 0 AB 505 AC
CC
224
VV R 227
VV 226
VV 225
VV 224
19 21 23 S 24
43 42
41 DM 60 63 62 AD
24 6V6CCO 20 20 21 17
24
24 27 26 AL
34 32 40 61
DM 59 AE
24 23 23 15 15 6V5CCO 17 18 18
25 P 5V04CCO ZQ RS 35 33
57 P N 58 AF
21 21 19 19
16 13 S 14
21 22 20 DM
N
A
BA
PA 5V04CCO
P
N DM 56
48 AG
20 20 6V6CCO S 7 16 13
14 10 23 DM
29 28 31 A
AC 39 37 38
51 49 50 AH
22 22 18 S 7 6V5CCO 11 11 12 10
P N 16 30
A A BG BG
36 DM P N
AJ
17 17 18
15 8 8 12 6V5CCO 9 19 18 17
9 12 A
A 5V04CCO BA CE 55 54
53 52 AK
13 6V6CCO 16 16 15
S49 7
3 8 DM 13
A
C
A
AL A 5V04CCO 66 67 DM 71
3 3 10 10 13 12 14 14 1 2 4 5
6 DM 1 10
15 A A CN
A CS OD 65
69 AM
44
9 9 S 12 8 8 1 2
565 P
11
P
14
A
5V04CCO
A
C
A CS
P N 70 AN
5
2 2 1 1 11 11 7 7
3364
N20N
A
A
A
CN 5V04CCO OD CE 64 68
AP
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Bank 65 Bank 66 Bank 88 Bank 89 Quad 128 Quad 129 Bank 224 Bank 225
Bank 226 Bank 227 Bank 228 Bank 229 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503
PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP VREF
ADC/DAC Pins
# ADC_VIN_#_P # ADC_VIN_#_N C ADC_CLK_P C ADC_CLK_N R ADC_REXT V VCM01 V VCM23 # DAC_VOUT_#_P # DAC_VOUT_#_N C DAC_CLK_P C DAC_CLK_N R DAC_REXT S SYSREF_P S SYSREF_N
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
MGTAVTTRCAL G MGTRREF
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-33: FFVE1156 and FSVE1156 Packages--XCZU27DR and XCZU28DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
153
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-34
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A DAC DAC DAC
DAC
DAC
E
A
B DAC DAC DAC
DAC
DAC
B
C
DAC DAC DAC DAC DAC
E
C
D DAC
DAC
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
E
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
F DAC
DAC
DAC
DAC VTT
DAC
DAC
G
DAC
DAC VTT
DAC
DAC VCC
DAC VCC
H DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
J
DAC
DAC
DAC VCC
DAC
K DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
L
DAC
DAC
DAC VCC
DAC SUB
M DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
N
DAC
DAC
DAC VCC
DAC
P DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
R ADC ADC ADC DAC DAC DAC DAC DAC
T
ADC
ADC
ADC
DAC
DAC
DAC
VCC AMS
U ADC ADC ADC ADC ADC ADC DAC DAC
V
ADC
ADC
ADC
ADC
VCC AMS
W ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
Y
ADC
ADC
ADC VCC
ADC
VCC AMS
AA ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
AB
ADC
ADC
ADC VCC
ADC
VCC AMS
AC ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC SUB
AD
ADC
ADC
ADC VCC
ADC
VCC AMS
AE ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
AF
ADC
ADC
ADC
AG ADC ADC ADC
ADC
ADC AUX
AH
ADC
ADC
ADC AUX
AJ ADC ADC ADC
ADC
ADC AUX
AK
ADC
ADC
ADC
ADC
ADC AUX
AL ADC ADC ADC
15 13
24 21 22 23 87
33 34 35
38
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
V
E
V
n
nnn
V
n
V
V E
E
AU AU AU
E
BT AU
V
AD AD PL
E
F P DP DP PL PL
V
FP LP
LP LP
FP FP LP LP LP
V
FP FP DD
F P
DD DD
D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL
AM
AM
AN
AN
AP
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
VCC AMS
VCCINT_AMS
ADC VCC
ADC_AVCC
ADC AUX
ADC_AVCCAUX
ADC ADC_GND
ADC SUB
ADC_SUB_GND
DAC VCC
DAC_AVCC
DAC AUX
DAC_AVCCAUX
DAC VTT
DAC_AVTT
DAC DAC_GND
DAC SUB
DAC_SUB_GND
Dedicated Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
Multi-Function I/O Pins PS Pins
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-34: FFVE1156 and FSVE1156 Packages--XCZU27DR and XCZU28DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
154
Chapter 4: Device Diagrams
FFVE1156 and FSVE1156 Packages�XCZU43DR
X-Ref Target - Figure 4-35
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A B C D E0 0
230
F G H J00
229
K L M N0 0
228
P R T U V1 1
227
W Y AA AB 1 1
226
AC
0 231
0
R
CC 230
CC 228
SS 228
CC 227
CC 226
CC 225
33
12 11 11 14
24 40 43 46
50 60 71 73
21
421 4 8V9CCO 5
665
77
8V9CCO 8
8
9 9 11
12 10
9 10
897 8 8V8CCO 7
655
64
8V8CCO 4
2
12 20 25 38
45 51
10 19 5V00CCO 36 41 44 48 15 23 34 39 5V01CCO 47
8 17 22
37 42 49
9 5V00CCO 21 18 32 35 4 11 16 13 5V01CCO 31 33
26
5 27 30 29
58 62
70 75
63 65 72 74
55 59 64
77
61 5V02CCO 69 68 76
53 57 66 67
52 56
5V02CCO
54
11 12 3 3
2 0 1 28
EO
10 10 12
1137
26
MD PO PI
MD
MD
MD RC DI
PR
MS 5V03CCO
PG CK
IN SR ES DN 5V03CCO DO
3 3
129
33 129
22 129
11 129
1 1
129
00 129
G
0 0
129
33 128
1 1
128
22 128
0 0
128
11 128
3 3
505
00 128
2 2
505
33 505
G
1 1
505
22 505
0 0
505
11 505
00 505
46 44
19
22 22 23
47 45 P N
A
B 2 2 129 C
D 1 1 129 E
F 0 0 129 G
H 3 3 128 J
K 2 2 128 L
M 1 1 128 N
P 0 0 128 R
T 3 3 505 U
V 2 2 505 W
Y 1 1 505 AA
0 0 AB 505 AC
AD AE AF 1 1
225
AG AH AJ AK 1 1
224
AL
CC 224
V V V V
19
21 23 S 24
43 42
41 DM 60 63 62 AD
24 6V6CCO 20 20 21 17
24
24 27 26 AL
34 32 40 61
DM 59 AE
R
24 23 23 15 15 6V5CCO 17 18 18
25
P
5V04CCO ZQ
RS
35 33
57 P N 58 AF
21 21 19 19
16 13 S 14
21 22 20 DM
N
A
BA
PA 5V04CCO
P
N DM 56
48 AG
20 20 6V6CCO S 7 16 13
14 10 23 DM
29 28 31 A
AC 39 37 38
51 49 50 AH
22 22 18 S 7 6V5CCO 11 11 12 10
P N 16 30
A
A BG BG
36 DM P N
AJ
17 17 18
15 8
13 6V6CCO 16 16 15
8 12 6V5CCO 9 19 18 17
9 12 A
S4 9 7
3 8 DM 13
A
5V04CCO BA
CE
55 54
53 52 AK
A
C
A
AL A 5V04CCO 66 67 DM 71
AM
3 3 10 10 13 12 14 14
1245
6 DM 1 10
15 A A CN
A CS OD 65
69 AM
AN 6 6
44
9 9 S 12
8812
565P
11
P
14
A
5V04CCO
A
C
A CS
P N 70 AN
AP
55
2211
11 11 7 7
3364
N20N
A
A
A
CN 5V04CCO OD CE 64 68
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Bank 65 Bank 66 Bank 88 Bank 89
Quad 128 Quad 129 Bank 224 Bank 225
Bank 226 Bank 227 Bank 228 Bank 230
PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503
PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP VREF
ADC/DAC Pins
# ADC_VIN_#_P # ADC_VIN_#_N C ADC_CLK_P C ADC_CLK_N R ADC_REXT V VCM01 V VCM23 # DAC_VOUT_#_P # DAC_VOUT_#_N C DAC_CLK_P C DAC_CLK_N R DAC_REXT S SYSREF_P S SYSREF_N
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
MGTAVTTRCAL G MGTRREF
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-35: FFVE1156 and FSVE1156 Packages--XCZU43DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
155
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-36
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A DAC DAC DAC
DAC n DAC
E
A
B DAC DAC DAC
DAC
DAC
B
Cn
n DAC DAC DAC DAC DAC
E
C
D DAC
DAC
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
E
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
F DAC
DAC
DAC
DAC VTT
DAC
DAC
Gn
n
DAC
DAC VTT
DAC
DAC VCC
DAC VCC
H DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
J
DAC
DAC
DAC VCC
DAC
K DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
L n n DAC
DAC
DAC VCC
DAC SUB
M DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
N
DAC
DAC
DAC VCC
DAC
P DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
R ADC ADC ADC DAC DAC DAC DAC DAC
T
n
n
ADC
ADC
ADC
DAC
DAC
DAC
VCC AMS
U ADC ADC ADC ADC ADC ADC DAC DAC
V
ADC
ADC
ADC
ADC
VCC AMS
W ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
Y n n ADC
ADC
ADC VCC
ADC
VCC AMS
AA ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
AB
ADC
ADC
ADC VCC
ADC
VCC AMS
AC ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC SUB
AD n n ADC
ADC
ADC VCC
ADC
VCC AMS
AE ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
AF
ADC n
ADC
ADC
AG ADC ADC ADC n
ADC
ADC AUX
AH n n ADC n
ADC
ADC AUX
AJ ADC ADC ADC n
ADC
ADC AUX
AK
ADC
ADC
ADC
ADC
ADC AUX
AL ADC ADC ADC
15 13
24 21 22 23 87
33 34 35
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
38
V
E
V
n
nnn
V
n
V
V E
E
AU AU AU
E
BT AU
V
AD AD PL
E
F P DP DP PL PL
V
FP LP
LP LP
FP FP LP LP LP
V
FP FP DD
F P
DD DD
D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL
AM
AM
AN
AN
AP
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Power Pins
Dedicated Pins Multi-Function I/O Pins PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC r RSVD R RSVDGND E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
VCC AMS
VCCINT_AMS
ADC VCC
ADC_AVCC
ADC AUX
ADC_AVCCAUX
ADC ADC_GND
ADC SUB
ADC_SUB_GND
DAC VCC
DAC_AVCC
DAC AUX
DAC_AVCCAUX
DAC VTT
DAC_AVTT
DAC DAC_GND
DAC SUB
DAC_SUB_GND
n NC
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-36: FFVE1156 and FSVE1156 Packages--XCZU43DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
156
Chapter 4: Device Diagrams
FFVE1156 and FSVE1156 Packages�XCZU47DR
X-Ref Target - Figure 4-37
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
B
C2 2 230
D
E0 0 230
F
G2 2
229
H
J0 0 229
K
L2 2 228
M
N0 0 228
P
R
T3 3 227
U
V1 1 227
W
Y3 3 226
AA
AB 1 1 226
AC
0 231
0
2 231
2
R
CC 230
CC 228
SS 228
CC 227
CC 226
CC 225
33
12 11 11 14
24 40 43 46
50 60 71 73
21
421
4
8V9CCO
5
665
77
8V9CCO
8
8
9 9 11
12 10
9 10
897
8
8V8CCO
7
655
64
8V8CCO
4
2
12 20 25 38
45 51
10 19 5V00CCO 36 41 44 48 15 23 34 39 5V01CCO 47
8 17 22
37 42 49
9 5V00CCO 21 18 32 35 4 11 16 13 5V01CCO 31 33
26
5 27 30 29
58 62
70 75
63 65 72 74
55 59 64
77
61 5V02CCO 69 68 76
53 57 66 67
52 56
5V02CCO
54
11 12 3 3
2 0 1 28
EO
10 10 12
1137
26
MD PO PI
MD
MD
MD RC DI
PR
MS 5V03CCO
PG CK
IN SR ES
DN
5V03CCO
DO
3 3
129
33 129
22 129
11 129
1 1
129
G
0 0
129
00 129
33 128
1 1
128
22 128
0 0
128
11 128
3 3
505
00 128
2 2
505
33 505
G
1 1
505
22 505
0 0
505
11 505
46 44
00 505
19
22 22 23
47 45 P N
A
B 2 2 129 C
D 1 1 129 E
F 0 0 129 G
H 3 3 128 J
K 2 2 128 L
M 1 1 128 N
P 0 0 128 R
T 3 3 505 U
V 2 2 505 W
Y 1 1 505 AA
0 0 AB 505 AC
AD 3 3 225
AE
AF 1 1 225
AG
AH 3 3 224
AJ
AK 1 1 224
AL
CC 224
VV 227
VV 226
VV 225
VV 224
19
21 23 S 24
43 42
41 DM 60 63 62 AD
24 6V6CCO 20 20 21 17
24
24 27 26 AL
34 32 40 61
DM 59 AE
R
24 23 23 15 15 6V5CCO 17 18 18
25
P
5V04CCO
ZQ
RS 35 33
57 P N 58 AF
21 21 19 19
16 13 S 14
21 22 20 DM
N
A
BA
PA 5V04CCO
P
N DM 56
48 AG
20 20 6V6CCO S
7 16 13
14 10 23 DM
29 28 31 A
AC 39 37 38
51 49 50 AH
22 22 18 S 7 6V5CCO 11 11 12 10
P N 16 30
A
A BG BG
36 DM P N
AJ
17 17 18
15 8
13 6V6CCO 16 16 15
8 12 6V5CCO 9 19 18 17
9 12 A
S497
3 8 DM 13
A
5V04CCO
BA
CE
55 54
53 52 AK
A
C
A
AL A 5V04CCO 66 67 DM 71
AM
3 3 10 10 13 12 14 14
1245
6 DM 1 10
15 A A CN
A CS OD 65
69 AM
AN 6 6
44
9 9 S 12
8812
565P
11
P
14
A
5V04CCO
A
C
A CS
P N 70 AN
AP
55
2211
11 11 7 7
3364
N 20 N
A
A
A
CN
5V04CCO
OD
CE
64 68
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Bank 65 Bank 66 Bank 88 Bank 89 Dual 128 Dual 129 Bank 224 Bank 225
Bank 226 Bank 227 Bank 228 Bank 229 Bank 230 Bank 231 PS Bank 500 PS Bank 501
PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP VREF
ADC/DAC Pins
# ADC_VIN_#_P # ADC_VIN_#_N C ADC_CLK_P C ADC_CLK_N R ADC_REXT V VCM01 V VCM23 # DAC_VOUT_#_P # DAC_VOUT_#_N C DAC_CLK_P C DAC_CLK_N R DAC_REXT S SYSREF_P S SYSREF_N
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
MGTAVTTRCAL G MGTRREF
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-37: FFVE1156 and FSVE1156 Packages--XCZU47DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
157
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-38
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A DAC DAC DAC
DAC
DAC
E
A
B DAC DAC DAC
DAC
DAC
B
C
DAC DAC DAC DAC DAC
E
C
D DAC
DAC
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
E
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
F DAC
DAC
DAC
DAC VTT
DAC
DAC
G
DAC
DAC VTT
DAC
DAC VCC
DAC VCC
H DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
J
DAC
DAC
DAC VCC
DAC
K DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
L
DAC
DAC
DAC VCC
DAC SUB
M DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
N
DAC
DAC
DAC VCC
DAC
P DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
R ADC ADC ADC DAC DAC DAC DAC DAC
T
ADC
ADC
ADC
DAC
DAC
DAC
VCC AMS
U ADC ADC ADC ADC ADC ADC DAC DAC
V
ADC
ADC
ADC
ADC
VCC AMS
W ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
Y
ADC
ADC
ADC VCC
ADC
VCC AMS
AA ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
AB
ADC
ADC
ADC VCC
ADC
VCC AMS
AC ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC SUB
AD
ADC
ADC
ADC VCC
ADC
VCC AMS
AE ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
AF
ADC
ADC
ADC
AG ADC ADC ADC
ADC
ADC AUX
AH
ADC
ADC
ADC AUX
AJ ADC ADC ADC
ADC
ADC AUX
AK
ADC
ADC
ADC
ADC
ADC AUX
AL ADC ADC ADC
15 13
24 21 22 23 87
33 34 35
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
38
V
E
V
n
nnn
V
V
V E
E
AU AU AU
E
BT AU
V
AD AD PL
E
F P DP DP PL PL
V
FP LP
LP LP
FP FP LP LP LP
V
FP FP DD
F P
DD DD
D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL
AM
AM
AN
AN
AP
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC r RSVD R RSVDGND E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
VCC AMS
VCCINT_AMS
ADC VCC
ADC_AVCC
ADC AUX
ADC_AVCCAUX
ADC ADC_GND
ADC SUB
ADC_SUB_GND
DAC VCC
DAC_AVCC
DAC AUX
DAC_AVCCAUX
DAC VTT
DAC_AVTT
DAC DAC_GND
DAC SUB
DAC_SUB_GND
n NC
Dedicated Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
Multi-Function I/O Pins PS Pins
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-38: FFVE1156 and FSVE1156 Packages--XCZU47DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
158
Chapter 4: Device Diagrams
FFVE1156 and FSVE1156 Packages�XCZU48DR
X-Ref Target - Figure 4-39
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
B
C2 2 230
D
E0 0 230
F
G2 2
229
H
J0 0 229
K
L2 2 228
M
N0 0 228
P
R
T3 3 227
U
V1 1 227
W
Y3 3 226
AA
AB 1 1 226
AC
0 231
0
2 231
2
R
CC 230
CC 228
SS 228
CC 227
CC 226
CC 225
33
12 11 11 14
24 40 43 46
50 60 71 73
21
421
4
8V9CCO
5
665
77
8V9CCO
8
8
9 9 11
12 10
9 10
897
8
8V8CCO
7
655
64
8V8CCO
4
2
12 20 25 38
45 51
10 19 5V00CCO 36 41 44 48 15 23 34 39 5V01CCO 47
8 17 22
37 42 49
9 5V00CCO 21 18 32 35 4 11 16 13 5V01CCO 31 33
26
5 27 30 29
58 62
70 75
63 65 72 74
55 59 64
77
61 5V02CCO 69 68 76
53 57 66 67
52 56
5V02CCO
54
11 12 3 3
2 0 1 28
EO
10 10 12
1137
26
MD PO PI
MD
MD
MD RC DI
PR
MS 5V03CCO
PG CK
IN SR ES
DN
5V03CCO
DO
3 3
129
33 129
22 129
11 129
1 1
129
G
0 0
129
00 129
33 128
1 1
128
22 128
0 0
128
11 128
3 3
505
00 128
2 2
505
33 505
G
1 1
505
22 505
0 0
505
11 505
46 44
00 505
19
22 22 23
47 45 P N
A
B 2 2 129 C
D 1 1 129 E
F 0 0 129 G
H 3 3 128 J
K 2 2 128 L
M 1 1 128 N
P 0 0 128 R
T 3 3 505 U
V 2 2 505 W
Y 1 1 505 AA
0 0 AB 505 AC
AD 3 3 225
AE
AF 1 1 225
AG
AH 3 3 224
AJ
AK 1 1 224
AL
CC 224
VV 227
VV 226
VV 225
VV 224
19
21 23 S 24
43 42
41 DM 60 63 62 AD
24 6V6CCO 20 20 21 17
24
24 27 26 AL
34 32 40 61
DM 59 AE
R
24 23 23 15 15 6V5CCO 17 18 18
25
P
5V04CCO
ZQ
RS 35 33
57 P N 58 AF
21 21 19 19
16 13 S 14
21 22 20 DM
N
A
BA
PA 5V04CCO
P
N DM 56
48 AG
20 20 6V6CCO S
7 16 13
14 10 23 DM
29 28 31 A
AC 39 37 38
51 49 50 AH
22 22 18 S 7 6V5CCO 11 11 12 10
P N 16 30
A
A BG BG
36 DM P N
AJ
17 17 18
15 8
13 6V6CCO 16 16 15
8 12 6V5CCO 9 19 18 17
9 12 A
S497
3 8 DM 13
A
5V04CCO
BA
CE
55 54
53 52 AK
A
C
A
AL A 5V04CCO 66 67 DM 71
AM
3 3 10 10 13 12 14 14
1245
6 DM 1 10
15 A A CN
A CS OD 65
69 AM
AN 6 6
44
9 9 S 12
8812
565P
11
P
14
A
5V04CCO
A
C
A CS
P N 70 AN
AP
55
2211
11 11 7 7
3364
N 20 N
A
A
A
CN
5V04CCO
OD
CE
64 68
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Bank 65 Bank 66 Bank 88 Bank 89 Dual 128 Dual 129 Bank 224 Bank 225
Bank 226 Bank 227 Bank 228 Bank 229 Bank 230 Bank 231 PS Bank 500 PS Bank 501
PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP VREF
ADC/DAC Pins
# ADC_VIN_#_P # ADC_VIN_#_N C ADC_CLK_P C ADC_CLK_N R ADC_REXT V VCM01 V VCM23 # DAC_VOUT_#_P # DAC_VOUT_#_N C DAC_CLK_P C DAC_CLK_N R DAC_REXT S SYSREF_P S SYSREF_N
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
MGTAVTTRCAL G MGTRREF
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-39: FFVE1156 and FSVE1156 Packages--XCZU48DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
159
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-40
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A DAC DAC DAC
DAC
DAC
E
A
B DAC DAC DAC
DAC
DAC
B
C
DAC DAC DAC DAC DAC
E
C
D DAC
DAC
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
E
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
F DAC
DAC
DAC
DAC VTT
DAC
DAC
G
DAC
DAC VTT
DAC
DAC VCC
DAC VCC
H DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
J
DAC
DAC
DAC VCC
DAC
K DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
L
DAC
DAC
DAC VCC
DAC SUB
M DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
N
DAC
DAC
DAC VCC
DAC
P DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
VCC AMS
R ADC ADC ADC DAC DAC DAC DAC DAC
T
ADC
ADC
ADC
DAC
DAC
DAC
VCC AMS
U ADC ADC ADC ADC ADC ADC DAC DAC
V
ADC
ADC
ADC
ADC
VCC AMS
W ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
Y
ADC
ADC
ADC VCC
ADC
VCC AMS
AA ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
AB
ADC
ADC
ADC VCC
ADC
VCC AMS
AC ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC SUB
AD
ADC
ADC
ADC VCC
ADC
VCC AMS
AE ADC
ADC
ADC
ADC
ADC
ADC
ADC VCC
ADC
AF
ADC
ADC
ADC
AG ADC ADC ADC
ADC
ADC AUX
AH
ADC
ADC
ADC AUX
AJ ADC ADC ADC
ADC
ADC AUX
AK
ADC
ADC
ADC
ADC
ADC AUX
AL ADC ADC ADC
15 13
24 21 22 23 87
33 34 35
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
38
V
E
V
n
nnn
V
V
V E
E
AU AU AU
E
BT AU
V
AD AD PL
E
F P DP DP PL PL
V
FP LP
LP LP
FP FP LP LP LP
V
FP FP DD
F P
DD DD
D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL
AM
AM
AN
AN
AP
AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Power Pins
Dedicated Pins Multi-Function I/O Pins PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC r RSVD R RSVDGND E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
VCC AMS
VCCINT_AMS
ADC VCC
ADC_AVCC
ADC AUX
ADC_AVCCAUX
ADC ADC_GND
ADC SUB
ADC_SUB_GND
DAC VCC
DAC_AVCC
DAC AUX
DAC_AVCCAUX
DAC VTT
DAC_AVTT
DAC DAC_GND
DAC SUB
DAC_SUB_GND
n NC
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-40: FFVE1156 and FSVE1156 Packages--XCZU48DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
160
Chapter 4: Device Diagrams
FFVB1517 Package�XCZU11EG
X-Ref Target - Figure 4-41
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
24 22 23 23 24 22 20 20 18 18 24 24 S 22 22 24 A
B
24 22 21 19 24 22 23 23 16 16 23 20 20 22 24 B
C
20 20 21 19 S 19 21 21 17 17 23 21 22 21 S 20 C
D
S 18 18 7V1CCO 15 18 18 19
S 14 14 15 21 23 23 21 20 D
E
S
17 17 15 16 7V0CCO 15 15 13 13 6V9CCO 15 19 18 18 6V8CCO 17 19 19 E
F
13 13 16 16 16 14 S 13 12 12 S 19 14 14 17 16 F
G
10 11
9 14 14 7V1CCO 7 17 17 14
13 10 11 11
8 S 13 13 16 15 G
H
10 11 9V0CCO
9
12 12 7 S 7V0CCO 12 12 11 10 6V9CCO 9 8 10 10 6V8CCO 12 6 6 15 H
J
9 12
S 11 11 8 10 10 11 7 7 9
11 11 12
4J
K
8 8 9 12
10 8 7V1CCO 8 8 7
9966
58S9
224K
L
7 7 4 9V0CCO 2
10
5 5 7 7V0CCO 6
5 4 6V9CCO 1 5 8 9 6V8CCO 5 3 3
L
M
66342
33
6446
54
1
775
1 1M
N3 3 227
P R1
1 227
T U3
3 226
V W1
1 226
Y AA 3 3
225
AB AC 1 1
225
AD AE 3 3
224
AF AG 1 1
224
AH AJ AK 1 3 AL 1 3 AM AN 4 4 AP 2 2 AR 2 AT 1 2 AU 1 3 AV 3
2 2
227
3
3
227
2
2
227
1 1
227
553
1
11 8V9CCO 12 12 1
1
1
227
0 0
227
11 10 10
0 0
227
0
0
227
99
3
3
226
1 1
226
865
2 2
226
1
1
226
2
2
226
G
0 0
226
865 7 1 8V9CCO
0 0
226
0
0
226
731
3
3
225
1 1
225
43
2 2
225
2
2
225
422
0 0
225
1
1
225
0
0
225
0 0
225
12 10 10 12 9 8V8CCO
3
3
224
1 1
224
11 11 9
2 2
224
2
2
224
88
0 0
224
1
1
224
0
0
224
0 0
224
7755 4 6 6 1 8V8CCO
21 21 4
3155
8 8 10 15 15 17 17 19 23 3 2 2
14
5 6V5CCO 10 11 13 13 6V5CCO 19 22 23
3314
5 S 11 12
S 16 S 22 6V5CCO 24 6 6
8 6V6CCO
1162
44
2
28 30 27 38 42 26 33 5V01CCO 39 43
32 35 40 44
2 31 34 37
45
2 29 5V01CCO 36 41 46
0 3 10 12
82 1
14 20
6 6 12 14 14 16 20 20 24 9
7 7 10 10
4 13 17 22
7 7 9 9 18 18 21
9 11 12 12
S 5 16 15 5V00CCO 21
488
10 17 17 21
23 23 S 11 6V6CCO 14 14 16 6
19 23 23
4 6V4CCO 12 12 10 13 6V4CCO 15 S 19 19
15 13 13 16
18 7 20 25
6 11 11
13 S 15 24 6V4CCO 20 19 15 20
17 17 18 9 5V00CCO 22 3
56
9 14 14 18
24 22 20 19 6V6CCO 20 S 22 22
11 18 24 DM
2222
3399
7
33
19 S 15 15 6V7CCO 11 11 7 5
1 1 23 S 19 17
13 13 12 12 6V7CCO 5
23 21 21 17 18 18 14 S 8 6
24 24 16 16 6V7CCO 14 10 10 8
20 20 22 22
72 69 73 70 5V02CCO 53 60
MD SR MD 5V03CCO 64 65 68 74
58 54 61 63
RC
PG EO 59 67 5V02CCO 55 56 52 57 71 75
MD MD DO ES
PI
PO 5V03CCO PR
MS DN IN DI
CK
47 48
1 1
505
0 0
505
33 505
11 505
G
2 2
505
22 505
00 505
3 3
505
1 1
505
47 46 44 45
62 P
49
P
N 5V04CCO DM 63 61
N
50 51 19 27 26
42 43 41 40
60
A
AL AC ZQ 5V04CCO 32 33 48
DM 18
P 31 A BG
BG 34 35 P
17 25
N
30 5V04CCO A
BA
RS
DM 5V04CCO
N
DM
P 16 24
28 A A PA
37 38 36 52
N
14 DM 29 BA 5V04CCO A
A
OD 39 5V04CCO 69
2 0 13 12
15 A A C
CE 68 70
1P
DM P
N
A
5V04CCO CN
A
CS DM
N 9 8 11
A A C CN
64 65
3 3N
1P
6 1R
4
T
4 2U
62 2 V
66 W
77 76 Y
AA
3 3 AB 505 AC
2 2 AD 505 AE
0 0 AF 505 AG
59 58 AH
56 AJ
DM 57 AK
50 AL
49 51 AM
P N AN
54 AP
53 55 AR
71
AT
P N AU
66 67 AV
AW
5 S 9 7 7 18 16 16 22 21 21 23 23 24 24 8 21
6547
10 A A A
A A CS CE OD
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 69 Bank 70 Bank 71
Bank 88 Bank 89 Bank 90 Quad 224 Quad 225 Quad 226 Quad 227 PS Bank 500
PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-41: FFVB1517 Package--XCZU11EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
161
X-Ref Target - Figure 4-42
Chapter 4: Device Diagrams
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
nn
nnnn
nnnn
nnnn
A
Bn
nnnn
nnnn
nnnn
nn
B
Cn n n n n n n n n
nnnn
nnnn
C
Dn n
nnnnnnnnn
nnnnnn
D
E
nnnn
nnnnnnnnn
nnn
E
Fnnn
nnnn
nnnn
nnnn
F
Gn
nnnnnnnnn
nn
n
G
Hn n n n
nnnnnnn
nnn
H
Jnnnnnnn
nnnn
nnnn
J
K
nnnn
nnnn
nnn
K
Lnnnnnnnnnnn
nn
L
M
nnn
M
N
E
nnn
N
P
V
E
n
n
P
R
E
R
T
V
E
T
U
V
U
V
V
V
W
V
W
Y
V
24 21
Y
AA
V
22 23
AA
AB
V
87
E
AB
AC
V
V
AC
AD
V
E
PL PL BT
E
AD
AE
E
PL
DP DP
V
AE
AF
V
E
L P L P L P AU AU
AF
AG
E
L P
AD AD AU AU
AG
AH
V
15 13
LP LP FP FP
AH
AJ
FP FP
FP DD
AJ
AK
33
FP FP DD DD
AK
AL
34
AL
AM
38
35
AM
AN
AN
AP
AP
AR
AR
AT
AT
AU
AU
AV
AV
AW
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
Dedicated Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
Multi-Function I/O Pins
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
PS Pins
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-42: FFVB1517 Package--XCZU11EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
162
Chapter 4: Device Diagrams
FFVB1517 Package�XCZU17EG and XCZU19EG
X-Ref Target - Figure 4-43
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 23 23 S 17 17 S
8 10 10 4
2 2 10 10 24 22 23 23 24 22 20 20 18 18 24 24 S 22 22 24 A
B 21 19 19 15 15 11 9 9 8
466S
8 8 24 22 21 19 24 22 23 23 16 16 23 20 20 22 24 B
C 21 20 20 S 7V4CCO 13 13 11 12
7711
11 11 7 7
20 20 21 19
S 19 21 21 17 17 23 21 22 21 S 20 C
D 24 24
18 16 14 14 7V4CCO 12 3 3 1
3 3 12 12 7V2CCO 9 S 18 18 7V1CCO 15 18 18 19
S 14 14 15 21 23 23 21 20 D
E 22 22 18 16
5 5 4 1 7V4CCO 5 5
14 14 9 S
17 17 15 16 7V0CCO 15 15 13 13 6V9CCO 15 19 18 18 6V8CCO 17 19 19 E
F 23 23 21 19 19 6 6
GS
21 20 20 11 7V3CCO 9
H 24 24 22 22 11 7 7 J 17 17 7V3CCO 13 13 12 12
K 15 15 14 14 10 8
L S 18 18 16 16 S 10 8
M
42 955 3 7V3CCO 362 16 144
2
16 16 13 13 13 13 16 16 16 14 S 13 12 12 S 19 14 14 17 16 F
10 11 18 18
S 9 14 14 7V1CCO 7 17 17 14
13 10 11 11
8 S 13 13 16 15 G
10 11 9V3CCO 15 17 17 9
12 12 7 S 7V0CCO 12 12 11 10 6V9CCO 9 8 10 10 6V8CCO 12 6 6 15 H
2
9 12 15 19 7V2CCO 24 S 11 11
8 10 10 11
779
11 11 12
4J
8 8 9 12
19 20 24 10 7V1CCO 8 8 8 7
9966
58S9
224K
7 7 4 9V3CCO 2 21 20
10
5 5 7 7V0CCO 6
5 4 6V9CCO 1 5 8 9 6V8CCO 5 3 3
L
6 6 3 4 2 7V2CCO 21 22 3 3
6446
54
1
775
1 1M
N3 3 227
P R1
1 227
T U3
3 226
V W1
1 226
Y AA 3 3
225
AB AC 1 1
225
AD AE 3 3
224
AF AG 1 1
224
AH AJ AK 1 3 AL 1 3 AM AN 4 4 AP 2 2 AR 2 AT 1 2 AU 1 3 AV 3
2 2
227
3
3
227
2
2
227
1 1
227
553
1 23 23 22 1 1 6 2
11 9V1CCO 12 12 1
S44
2
1
1
227
0 0
227
11 10 10
0 0
227
0
0
227
99
3
3
226
1 1
226
865
2 2
226
1
1
226
2
2
226
G
0 0
226
865 7 1 9V1CCO
0 0
226
0
0
226
731
3
3
225
1 1
225
43
2 2
225
2
2
225
422
0 0
225
1
1
225
0
0
225
0 0
225
12 10 10 12 9 9V0CCO
3
3
224
1 1
224
11 11 9
2 2
224
0 0
224
1
1
224
2
2
224
0
0
224
0 0
224
88
7755 4 6 6 1 9V0CCO
28 30 27 38 42 26 33 5V01CCO 39 43
32 35 40 44
21 21 4
3155
2 31 34 37
45
8 8 10 15 15 17 17 19 23 3 2 2
1 4 2 29 5V01CCO 36 41 46
5 6V5CCO 10 11 13 13 6V5CCO 19 22 23
3314
0 3 10 12
5 S 11 12
S 16 S 22 6V5CCO 24 6 6
8 8 6V6CCO
21
14 20
6 6 12 14 14 16 20 20 24 9
7 7 10 10
4 13 17 22
7 7 9 9 18 18 21
9 11 12 12
S 5 16 15 5V00CCO 21
488
10 17 17 21
23 23 S 11 6V6CCO 14 14 16 6
19 23 23
4 6V4CCO 12 12 10 13 6V4CCO 15 S 19 19
15 13 13 16
18 7 20 25
6 11 11
13 S 15 24 6V4CCO 20 19 15 20
17 17 18 9 5V00CCO 22 3
56
9 14 14 18
24 22 20 19 20 6V6CCO S 22 22
11 18 24 DM
2222
3399
7
33
19 S 15 15 6V7CCO 11 11 7 5
1 1 23 S 19 17
13 13 12 12 6V7CCO 5
23 21 21 17 18 18 14 S 8 6
24 24 16 16 6V7CCO 14 10 10 8
20 20 22 22
72 69 73 70 5V02CCO 53 60
MD SR MD 5V03CCO 64 65 68 74
58 54 61 63
RC
PG EO 59 67 5V02CCO 55 56 52 57 71 75
MD MD DO ES
PI
PO 5V03CCO PR
MS DN IN DI
CK
47 48
1 1
505
0 0
505
33 505
11 505
G
2 2
505
22 505
00 505
3 3
505
1 1
505
47 46 44 45
62 P
49
P
N 5V04CCO DM 63 61
N
50 51 19 27 26
42 43 41 40
60
A
AL AC ZQ 5V04CCO 32 33 48
DM 18
P 31 A BG
BG 34 35 P
17 25
N
30 5V04CCO A
BA
RS
DM 5V04CCO
N
DM
P 16 24
28 A A PA
37 38 36 52
N
14 DM 29 BA 5V04CCO A
A
OD 39 5V04CCO 69
2 0 13 12
15 A A C
CE 68 70
1P
DM P
N
A
5V04CCO CN
A
CS DM
N 9 8 11
A A C CN
64 65
3 3N
1P
6 1R
4
T
4 2U
62 2 V
66 W
77 76 Y
AA
3 3 AB 505 AC
2 2 AD 505 AE
0 0 AF 505 AG
59 58 AH
56 AJ
DM 57 AK
50 AL
49 51 AM
P N AN
54 AP
53 55 AR
71
AT
P N AU
66 67 AV
AW
5 S 9 7 7 18 16 16 22 21 21 23 23 24 24 8 21
6547
10 A A A
A A CS CE OD
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 69 Bank 70 Bank 71
Bank 72 Bank 73 Bank 74 Bank 90 Bank 91 Bank 93 Quad 224 Quad 225
Quad 226 Quad 227 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins Transceiver Pins
PS Pins
VREF MGTAVTTRCAL G MGTRREF
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-43: FFVB1517 Package--XCZU17EG and XCZU19EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
163
X-Ref Target - Figure 4-44
Chapter 4: Device Diagrams
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
N
E
N
P
V
E
P
R
E
R
T
V
E
T
U
V
U
V
V
V
W
V
W
Y
V
24 21
Y
AA
V
22 23
AA
AB
V
87
E
AB
AC
V
V
AC
AD
V
E
PL PL BT
E
AD
AE
E
PL
DP DP
V
AE
AF
V
E
L P L P L P AU AU
AF
AG
E
L P
AD AD AU AU
AG
AH
V
15 13
LP LP FP FP
AH
AJ
FP FP
FP DD
AJ
AK
33
FP FP DD DD
AK
AL
34
AL
AM
38
35
AM
AN
AN
AP
AP
AR
AR
AT
AT
AU
AU
AV
AV
AW
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-44: FFVB1517 Package--XCZU17EG and XCZU19EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
164
Chapter 4: Device Diagrams
FFVF1517 Package�XCZU7CG and XCZU7EG
X-Ref Target - Figure 4-45
V V
12 A B C D E F G H J K2
2 228
L M0
0 228
N P2
2 227
R T0
0 227
U V2
2 226
W Y0
0 226
AA AB 2 2
225
AC AD 0 0
225
AE AF 2 2
224
AG AH 0 0
224
AJ AK 2 2
223
AL AM 0 0
223
AN AP 6 6 AR 3 AT 4 3 AU 4 AV 2 AW 2
12
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
11 12 12 11 12 23 22 22 24 3 1 1
4422
3 3 18 18 22 22 24 24 A
11 10 11 10 12 23 20 20 24 3
6622
6 5 5 1 16 16 23 S 21 B
10 9 9 10
21 21 19 19 6V7CCO 5 5
10 6V8CCO
6 4 4 2V8CCO 1 17 S 23
19 21 20 20 C
889
9 8 17 17
SS9 9
10 7 10 10
9 9 S 17 2V7CCO 14 13 19
4D
6 7 8V7CCO 7 7 8
15 16 16 18
S 12 7 8
12 12 8 8
15 15 14 13 2V7CCO 6 2 4 E
6 5 7 5 8V8CCO 6 13 13 15 6V7CCO 18 11 11 12 6V8CCO 8 17 11 11 2V8CCO 7 7 10 10
12 12 6 2
F
45
5 4 6 11
14 14 15 15
13 14 14 17
13 13 15 15 2V7CCO 9 9 11 11
5 5G
4 8V7CCO 3 3 4
9 11 12 12 17 18 13 16 16 16 14 14 8 8 7 S
3 3 1 1H
3 3
228
3
3
1 2 3 3 8V8CCO 7 9 8 10 6V7CCO S 17 18 6V8CCO 16 20 18 18 2V8CCO 21 S
7
J 41 40 51 45 5V01CCO 46
228
2
2
1
2227
8 S 10 23
S 20 20 20
S 21 19 19
29 44 35 36
26 28 50 K
228
1 1
1
1
11
5446
23 21 22 22 24 22 23 23
33 47 34 27 5V01CCO 43 38 39 42
L
228
228
0
0
228
153
6 21 19
24 22
14 12 67 57
37 30 31 32
48 49 M
3 3
227
2
2
227
3
3
227
1
3
2 2 19 24 24
3 18 24
52 76 62 73
63 59 60 58 N
P 20 5V00CCO 5 72 74 66 5V02CCO 53 69 64 61 5V02CCO 54
1 1
227
1
1
227
16 1 13 65
77 68 70 56
71 55 75 R
0
0
227
1 1
228
25 15
11
T
3 3
226
3
3
226
0 0
228
23 9 4
G 33 505
U 3 3 505
1 1
226
2
2
226
1
1
226
1 1
227
0 0
227
2 21 22
7 5V00CCO 6
8
3 3
505
22 505
2 2
505
V W 1
1 505
0
0
226
1 1
226
10 0 19
2 2
505
11
Y
505
3 3
225
3
3
225
0 0
226
17
1 1
0 0 AA
505
505
2
2
225
1 1
225
0 0
505
00 505
AB
1 1
1
1
G
225
225
AC
0
0
225
0 0
225
46 42
45 57 56 P
63 AD
3 3
224
2
2
224
3
3
224
0 0
224
1 1
224
MS DI
40 P DM 58
N 60 61 AE
5V03CCO PR DO 41
N
44 59 DM 62
AF
1 1
224
1
1
224
1 1
223
20 20 23 20 20
RC SR PG CK
43 47 53 48
54 49 AG
3 3
223
1 1
223
0
0
224
2
2
223
3
3
223
1
1
223
0 0
223
23 22 S S 22 23 22 S 23
MD MD MD
ES EO 35 38
52 P N 51 AH
21
23 24 22 20
22 21 21 22
23 21 21 MD 5V03CCO PO
PI
DN
A
37 DM 55 DM
50 AJ
23
21 19 19 24 6V5CCO 20 24 24 19
24 24 19 19
22 21 RS IN
A 36 P N
71 64 65 AK
23 21 S 17
15 18 9 9 19 6V3CCO 8 16 16 6V4CCO 17 S 23 18
ZQ
A
BG AC 5V04CCO 32 39 70 DM
AL
0
0
223
21 24 17 15 16 18
7 7S8
18 18 17 15
P DM A A
PA AL 34 33
P N AM
6V6CCO 24 13 13 16 6V5CCO 14 11 12 12
10 14 13 13
15 17 N 20
26 BG A BA
BA 69 68 66 AN
18 18 S 17 19 19 22 22 9
11 12 14 11 13 6V3CCO 14 10 14 12 6V4CCO 11 11 19
16 27 24 25 5V04CCO CS CN A
5 16 16 6V6CCO 17 S 20 20
9 10 11 12
S 15 13 14
8 10 12 9
4 2 1 DM
PNAC
AP A 5V04CCO 67 A A A AR
5
14 14 13 13 6V6CCO 7 8 8 10 6V5CCO S 17 17 15
18 16 8 10
9 7S 5
31 30 29 28 5V04CCO CE A
A
AT A
5V04CCO
1 9 9 11 15 15 7 1
55
1 6 18 16 6V3CCO
6V4CCO
557
P N DM 15
P 11 OD A
A A AU
1 10 11 12 12 7
1644
5316
2266
336 3
8
9
N
14 5V04CCO CE
C
CN
AV
10 S 8 8
7336
2253
4422
4411
7 0 12 DM
10 13 CS OD
AW
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 27 Bank 28 Bank 63 Bank 64 Bank 65 Bank 66 Bank 67 Bank 68
Bank 87 Bank 88 Quad 223 Quad 224 Quad 225 Quad 226 Quad 227 Quad 228
PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-45: FFVF1517 Package--XCZU7CG and XCZU7EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
165
X-Ref Target - Figure 4-46
Chapter 4: Device Diagrams
V
V V V V V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
nn
Vnn
A
Bnn
nn
V
B
C
nn
Vnn
C
Dn n
nn
V
D
E
nn
Vnn
E
Fnn
nn
V
F
G
nn
Vnn
G
Hn n
nn
E
H
J
V
J
K
E
K
L
V
L
M
Enn
M
N
V
Enn
N
P
Vnn
E
P
R
V
Enn
R
T
V
T
U
V
E
U
V
V
V
V
W
V
E
24 21
E
W
Y
V
22 23
V
Y
AA
V
E
87
PL
PL PL DP DP
E
V
AA
AB
V
LP LP LP LP
AD AU
E
AB
AC
V
E
LP LP
F P BT AD AU
AC
AD
V
FP FP FP FP
AU AU
AD
AE
V
E
FP FP DD
DD DD
AE
AF
V
R RRR
AF
AG
V
E
13 15
RR
AG
AH
E
33
AH
AJ
V
34
AJ
AK
E
35
AK
AL
V
AL
AM
E
AM
AN
AN
AP
AP
AR
AR
AT
AT
AU
AU
AV
38
AV
AW
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
Dedicated Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
Multi-Function I/O Pins
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
PS Pins
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-46: FFVF1517 Package--XCZU7CG and XCZU7EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
166
Chapter 4: Device Diagrams
FFVF1517 Package�XCZU7EV
X-Ref Target - Figure 4-47
V V
12 A B C D E F G H J K2
2 228
L M0
0 228
N P2
2 227
R T0
0 227
U V2
2 226
W Y0
0 226
AA AB 2 2
225
AC AD 0 0
225
AE AF 2 2
224
AG AH 0 0
224
AJ AK 2 2
223
AL AM 0 0
223
AN AP 6 6 AR 3 AT 4 3 AU 4 AV 2 AW 2
12
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
11 12 12 11 12 23 22 22 24 3 1 1
4422
3 3 18 18 22 22 24 24 A
11 10 11 10 12 23 20 20 24 3
6622
6 5 5 1 16 16 23 S 21 B
10 9 9 10
21 21 19 19 6V7CCO 5 5
10 6V8CCO
6 4 4 2V8CCO 1 17 S 23
19 21 20 20 C
889
9 8 17 17
SS9 9
10 7 10 10
9 9 S 17 2V7CCO 14 13 19
4D
6 7 8V7CCO 7 7 8
15 16 16 18
S 12 7 8
12 12 8 8
15 15 14 13 2V7CCO 6 2 4 E
6 5 7 5 8V8CCO 6 13 13 15 6V7CCO 18 11 11 12 6V8CCO 8 17 11 11 2V8CCO 7 7 10 10
12 12 6 2
F
45
5 4 6 11
14 14 15 15
13 14 14 17
13 13 15 15 2V7CCO 9 9 11 11
5 5G
4 8V7CCO 3 3 4
9 11 12 12 17 18 13 16 16 16 14 14 8 8 7 S
3 3 1 1H
3 3
228
3
3
1 2 3 3 8V8CCO 7 9 8 10 6V7CCO S 17 18 6V8CCO 16 20 18 18 2V8CCO 21 S
7
J 41 40 51 45 5V01CCO 46
228
2
2
1
2227
8 S 10 23
S 20 20 20
S 21 19 19
29 44 35 36
26 28 50 K
228
1 1
1
1
11
5446
23 21 22 22 24 22 23 23
33 47 34 27 5V01CCO 43 38 39 42
L
228
228
0
0
228
153
6 21 19
24 22
14 12 67 57
37 30 31 32
48 49 M
3 3
227
2
2
227
3
3
227
1
3
2 2 19 24 24
3 18 24
52 76 62 73
63 59 60 58 N
P 20 5V00CCO 5 72 74 66 5V02CCO 53 69 64 61 5V02CCO 54
1 1
227
1
1
227
16 1 13 65
77 68 70 56
71 55 75 R
0
0
227
1 1
228
25 15
11
T
3 3
226
3
3
226
0 0
228
23 9 4
G 33 505
U 3 3 505
1 1
226
2
2
226
1
1
226
1 1
227
0 0
227
2 21 22
7 5V00CCO 6
8
3 3
505
22 505
2 2
505
V W 1
1 505
0
0
226
1 1
226
10 0 19
2 2
505
11
Y
505
3 3
225
3
3
225
0 0
226
17
1 1
0 0 AA
505
505
2
2
225
1 1
225
0 0
505
00 505
AB
1 1
1
1
G
225
225
AC
0
0
225
0 0
225
46 42
45 57 56 P
63 AD
3 3
224
2
2
224
3
3
224
0 0
224
1 1
224
MS DI
40 P DM 58
N 60 61 AE
5V03CCO PR DO 41
N
44 59 DM 62
AF
1 1
224
1
1
224
1 1
223
20 20 23 20 20
RC SR PG CK
43 47 53 48
54 49 AG
3 3
223
1 1
223
0
0
224
2
2
223
3
3
223
1
1
223
0 0
223
23 22 S S 22 23 22 S 23
MD MD MD
ES EO 35 38
52 P N 51 AH
21
23 24 22 20
22 21 21 22
23 21 21 MD 5V03CCO PO
PI
DN
A
37 DM 55 DM
50 AJ
23
21 19 19 24 6V5CCO 20 24 24 19
24 24 19 19
22 21 RS IN
A 36 P N
71 64 65 AK
23 21 S 17
15 18 9 9 19 6V3CCO 8 16 16 6V4CCO 17 S 23 18
ZQ
A
BG AC 5V04CCO 32 39 70 DM
AL
0
0
223
21 24 17 15 16 18
7 7S8
18 18 17 15
P DM A A
PA AL 34 33
P N AM
6V6CCO 24 13 13 16 6V5CCO 14 11 12 12
10 14 13 13
15 17 N 20
26 BG A BA
BA 69 68 66 AN
18 18 S 17 19 19 22 22 9
11 12 14 11 13 6V3CCO 14 10 14 12 6V4CCO 11 11 19
16 27 24 25 5V04CCO CS CN A
5 16 16 6V6CCO 17 S 20 20
9 10 11 12
S 15 13 14
8 10 12 9
4 2 1 DM
PNAC
AP A 5V04CCO 67 A A A AR
5
14 14 13 13 6V6CCO 7 8 8 10 6V5CCO S 17 17 15
18 16 8 10
9 7S 5
31 30 29 28 5V04CCO CE A
A
AT A
5V04CCO
1 9 9 11 15 15 7 1
55
1 6 18 16 6V3CCO
6V4CCO
557
P N DM 15
P 11 OD A
A A AU
1 10 11 12 12 7
1644
5316
2266
336 3
8
9
N
14 5V04CCO CE
C
CN
AV
10 S 8 8
7336
2253
4422
4411
7 0 12 DM
10 13 CS OD
AW
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 27 Bank 28 Bank 63 Bank 64 Bank 65 Bank 66 Bank 67 Bank 68
Bank 87 Bank 88 Quad 223 Quad 224 Quad 225 Quad 226 Quad 227 Quad 228
PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-47: FFVF1517 Package--XCZU7EV I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
167
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-48
V
V V V V V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
nn
Vnn
A
Bnn
nn
V
B
C
nn
Vnn
C
Dn n
nn
V
D
E
nn
Vnn
E
Fnn
nn
V
F
G
nn
Vnn
G
Hn n
nn
E
H
J
V
J
K
E
K
L
V
L
M
Enn
M
N
V
Enn
N
P
Vnn
E
P
R
V
Enn
R
T
V
T
U
V
E
U
V
V
V
V
W
V
E
24 21
E
W
Y
V
22 23
V
Y
AA
V
E
87
PL
PL PL DP DP
E
V
AA
AB
V
LP LP LP LP
AD AU
E
AB
AC
V
E
LP LP
F P BT AD AU
AC
AD
V
FP FP FP FP
AU AU
AD
AE
V
E
FP FP DD
DD DD
AE
AF
V
AF
AG
V
E
13 15
AG
AH
E
33
AH
AJ
V
34
AJ
AK
E
35
AK
AL
V
AL
AM
E
AM
AN
AN
AP
AP
AR
AR
AT
AT
AU
AU
AV
38
AV
AW
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
Dedicated Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
Multi-Function I/O Pins
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
PS Pins
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-48: FFVF1517 Package--XCZU7EV Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
168
Chapter 4: Device Diagrams
FFVF1517 Package�XCZU11EG
X-Ref Target - Figure 4-49
V V
12
A
B2 2 231
C D0
0 231
E F2
2 230
G
H0 0 230
J K2
2 229
L
M0 0 229
N P2
2 228
R T0
0 228
U
V2 2 227
W Y0
0 227
AA AB 2 2
226
AC
AD 0 0 226
AE AF 2 2
225
AG AH 0 0
225
AJ
AK 2 2 224
AL AM 0 0
224
AN
AP 6 6
AR 3
AT 4 3
AU 4
AV 2
AW 2
12
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
3 3
231
3
3
231
11 12 12 11
12 23 22 22
24 3 1 1
4422
3 3 18 18 22 22 24 24 A
1 1
231
3 3
230
1 1
230
3 3
229
2
2
231
0
0
231
2
2
230
0
0
230
1
1
231
3
3
230
1
1
230
3
3
229
11 10 11 10 12 23 20 20 24 3
6622
6 5 5 1 16 16 23 S 21 B
10 9 9 10
21 21 19 19 7V0CCO 5 5
10 7V1CCO
6 4 4 6V9CCO 1 17 S 23
19 21 20 20 C
889
9 8 17 17
SS9 9
10 7 10 10
9 9 S 17 6V8CCO 14 13 19
4D
6 7 8V8CCO 7 7 8
15 16 16 18
S 12 7 8
12 12 8 8
15 15 14 13 6V8CCO 6 2 4 E
6 5 7 5 8V9CCO 6 13 13 15 7V0CCO 18 11 11 12 7V1CCO 8 17 11 11 6V9CCO 7 7 10 10
12 12 6 2
F
45
5 4 6 11
14 14 15 15
13 14 14 17
13 13 15 15 6V8CCO 9 9 11 11
5 5G
4 8V8CCO 3 3 4
9 11 12 12 17 18 13 16 16 16 14 14 8 8 7 S
3 3 1 1H
1 2 3 3 8V9CCO 7 9 8 10 7V0CCO S 17 18 7V1CCO 16 20 18 18 6V9CCO 21 S
7
J 41 40 51 45 5V01CCO 46
2
2
1
2227
8 S 10 23
S 20 20 20
S 21 19 19
29 44 35 36
26 28 50 K
229
1 1
1
1
11
5446
23 21 22 22 24 22 23 23
33 47 34 27 5V01CCO 43 38 39 42
L
229
229
0
0
229
1 1
231
153
6 21 19
24 22
14 12 67 57
37 30 31 32
48 49 M
3 3
228
2
2
228
3
3
228
1 1
230
0 0
231
1
3
2 2 19 24 24
3 18 24
52 76 62 73
63 59 60 58 N
P 20 5V00CCO 5 72 74 66 5V02CCO 53 69 64 61 5V02CCO 54
1 1
228
1
1
228
0 0
230
16 1 13 65
77 68 70 56
71 55 75 R
0
0
228
1 1
229
25 15
11
T
3 3
227
3
3
227
0 0
229
23 9 4
G 33 505
U 3 3 505
1 1
227
2
2
227
1
1
227
1 1
228
0 0
228
2 21 22
7 5V00CCO 6
8
3 3
505
22 505
2 2
505
V W 1
1 505
0
0
227
1 1
227
10 0 19
2 2
505
11
Y
505
3 3
226
3
3
226
0 0
227
17
1 1
0 0 AA
505
505
2
2
226
1 1
226
0 0
505
00 505
AB
1 1
1
1
G
226
226
AC
0
0
226
0 0
226
46 42
45 57 56 P
63 AD
3 3
225
2
2
225
3
3
225
0 0
225
1 1
225
MS DI
40 P DM 58
N 60 61 AE
5V03CCO PR DO 41
N
44 59 DM 62
AF
1 1
225
1
1
225
1 1
224
20 20 23 20 20
RC SR PG CK
43 47 53 48
54 49 AG
3 3
224
1 1
224
0
0
225
2
2
224
3
3
224
1
1
224
0 0
224
23 22 S S 22 23 22 S 23
MD MD MD
ES EO 35 38
52 P N 51 AH
21
23 24 22 20
22 21 21 22
23 21 21 MD 5V03CCO PO
PI
DN
A
37 DM 55 DM
50 AJ
23
21 19 19 24 6V5CCO 20 24 24 19
24 24 19 19
22 21 RS IN
A 36 P N
71 64 65 AK
23 21 S 17
15 18 9 9 19 6V4CCO 8 16 16 6V7CCO 17 S 23 18
ZQ
A
BG AC 5V04CCO 32 39 70 DM
AL
0
0
224
21 24 17 15 16 18
7 7S8
18 18 17 15
P DM A A
PA AL 34 33
P N AM
6V6CCO 24 13 13 16 6V5CCO 14 11 12 12
10 14 13 13
15 17 N 20
26 BG A BA
BA 69 68 66 AN
18 18 S 17 19 19 22 22 9
11 12 14 11 13 6V4CCO 14 10 14 12 6V7CCO 11 11 19
16 27 24 25 5V04CCO CS CN A
5 16 16 6V6CCO 17 S 20 20
9 10 11 12
S 15 13 14
8 10 12 9
4 2 1 DM
PNAC
AP A 5V04CCO 67 A A A AR
5
14 14 13 13 6V6CCO 7 8 8 10 6V5CCO S 17 17 15
18 16 8 10
9 7S 5
31 30 29 28 5V04CCO CE A
A
AT A
5V04CCO
1 9 9 11 15 15 7 1
55
1 6 18 16 6V4CCO
6V7CCO
557
P N DM 15
P 11 OD A
A A AU
1 10 11 12 12 7
1644
5316
2266
336 3
8
9
N
14 5V04CCO CE
C
CN
AV
10 S 8 8
7336
2253
4422
4411
7 0 12 DM
10 13 CS OD
AW
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 69 Bank 70 Bank 71
Bank 88 Bank 89 Quad 224 Quad 225 Quad 226 Quad 227 Quad 228 Quad 229
Quad 230 Quad 231 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-49: FFVF1517 Package--XCZU11EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
169
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-50
V
V V V V V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
V
A
B
V
B
C
V
C
D
V
D
E
V
E
F
V
F
G
V
G
H
E
H
J
V
J
K
E
K
L
V
L
M
E
M
N
V
E
N
P
V
E
P
R
V
E
R
T
V
T
U
V
E
U
V
V
V
V
W
V
E
24 21
E
W
Y
V
22 23
V
Y
AA
V
E
87
PL
PL PL DP DP
E
V
AA
AB
V
LP LP LP LP
AD AU
E
AB
AC
V
E
LP LP
F P BT AD AU
AC
AD
V
FP FP FP FP
AU AU
AD
AE
V
E
FP FP DD
DD DD
AE
AF
V
n
nnn
AF
AG
V
E
13 15
nn
AG
AH
E
33
35
AH
AJ
V
34
AJ
AK
E
AK
AL
V
AL
AM
E
AM
AN
AN
AP
AP
AR
AR
AT
38
AT
AU
AU
AV
AV
AW
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-50: FFVF1517 Package--XCZU11EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
170
Chapter 4: Device Diagrams
FFVG1517 and FSVG1517 Packages�XCZU25DR
V V
X-Ref Target - Figure 4-51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
10 11 11 12 12 23 23 24 24 24 24 20 24 24 22 20 S 32 33 46
A
B
10 7 8V7CCO 7 8 8
19 21 21 22
22 22 20 23
22 19 20 29 5V01CCO 34 39 49
B
C3 3
9 9 5 5 4 8V7CCO S 19 20
22 21 21 19
23 21 21 19
27 31 36 41 47
C
229
D
3
6 6 4 S 6V8CCO 20 18 23 23
19 S S 18 6V7CCO 16 16 30 40
43 48
D
E22
1322
17 16 16 18 6V9CCO 17 18 18 S
18 17 17 15 5V01CCO 35 38 42 51
E
229
F
1
6 9 9 17
15 15 17 13 6V9CCO 16 14 13 13
15 28 37 44
50
F
G1 1 229
H
J00 229
K
5 5 4 6 S 6V8CCO 13 13 15 15
13 14 16 14 6V7CCO 11 12 S 26
45 61 63
G
334
12 12 14 14 6V8CCO 7 11 11 14
10 9 11 12 5V02CCO 57 58 59 71 68
H
1 1 2 11 11
10 10 7 9 6V9CCO 12 12 10 9
7 7 55 60 5V02CCO 67 72
33
J
28877
9 8 10 10 6V7CCO 4 4
8
62 64 70 73
G
129
3 3
K
129
L33 228
5
44
8
6 6 3 5 5 8 53 56 65
77
22
129
L 2 2 129
M
5312
6S23
54 69 74 76
1 1
M
129
N2 2 228
CC 229
312
6
211
52 66 75 12
11 129
N 0 0 129
P
1
11 14
00
P
129
R1 1 228
CC 228
0 9 13 16
33 128
R 3 3 128
T U0 0
228
SS 228
73 5V00CCO 8
17 15 23
22 128
T U 2
2 128
V
W
R
4 10 20 21 6 5V00CCO 19 25
1 1
129
0 0
129
11 128
V W 1
1 128
Y33 227
CC 227
2 18 22 24
1 1
00
Y
128
128
AA
5 PG
CK
0 0
128
0 0 AA 128
AB 1 1 C C
R
227
226
AC
IN DN SR PR MD MD
5V03CCO RC
MD
ES
3 3
505
AB 3 3 AC
505
AD 3 3 226
AE
CC 225
MS DI DO
5V03CCO PI
MD
2 2
505
33 505
AD 2 2 AE
505
AF 1 1 226
CC 224
S 18 18 24 24
EO PO 62
22
AF
505
AG AH 3 3
225
AJ AK 1 1
225
VV 227
VV 226
VV 225
23 S
16 23 22
23 24 6V5CCO 17 17 16 23
22
21 24 22 15 15 6V4CCO 19 21 21
21 19 22
14 14 19 S 6V6CCO 20 20 23 21
63
61
60 P N
59 58 DM
24 27 26 A
57 56
1 1
505
0 0
505
G
11 505
00 505
1 1 AG 505 AH
0 0 AJ 505 AK
AL
AM 3 3 224
AN
VV 224
18 18 17 9 S 19 20 13 13 12 17 18 18 16 DM 25 P N
A AC BG AL
48 AL
15 15 17 9 6V5CCO 7 10 20 11 6V4CCO 12 15 17 13
16 P N 20
DM 31 A
AM A 5V04CCO BA RS 53 52 DM
P
49 50
16 16
12 11 7 10
11 10 10 15 6V6CCO 13 14 S 22
19 29 28 30
BA PA BG ZQ
55 54 N 51
AN
AP 1 1 224
AR
12 12 8V4CCO 13 14 12 11
79S8
11 12 12 14
18 17 16
9
5V04CCO
A
A
A OD 5V04CCO 46 47 67 70
69 71 AP
11 11 13 14 6V5CCO 8 8 7 9 8 6V4CCO 7 11 9
8 10 7 6
P 11 A C
CS CE 45 44
65 P DM 68 AR
AT
788 S644
5 5 7 9 6V6CCO S 8 10
P
8
N
DM 5V04CCO CN
A
A
A
5V04CCO
P
DM 64
N
66 AT
AU 4 4 6 6 7 10 8V4CCO 9
6
2366
3566
DM N 10
12 A A C
A 40 N 35
34 33 32 AU
AV 3 3
5 5 10 9
1323
2435
245 4
2
13 14
A
5V04CCO CN
A
OD 41 5V04CCO 38 DM
P
36
AV
AW
2211
5513
1124
1124
3 1 0 15
A CS CE A
43 42 39 37 N
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 69 Bank 84 Bank 87
Quad 128 Quad 129 Bank 224 Bank 225 Bank 226 Bank 227 Bank 228 Bank 229
PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP VREF
ADC/DAC Pins
# ADC_VIN_#_P # ADC_VIN_#_N C ADC_CLK_P C ADC_CLK_N R ADC_REXT V VCM01 V VCM23 # DAC_VOUT_#_P # DAC_VOUT_#_N C DAC_CLK_P C DAC_CLK_N R DAC_REXT S SYSREF_P S SYSREF_N
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
MGTAVTTRCAL G MGTRREF
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-51: FFVG1517 and FSVG1517 Packages--XCZU25DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
171
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-52
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
DAC
V
rr
A
B DAC DAC DAC
r rV
RR
B
C
DAC
V
rr
RRC
D DAC DAC DAC
r rV
RR
D
E
DAC DAC
V
rr
RRE
F DAC DAC DAC DAC
r rV
RR
F
G
DAC DAC
V
rr
RRG
H DAC
DAC
DAC
DAC VTT
J
DAC
DAC VTT
K DAC
DAC
DAC
DAC VTT
DAC
L
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
M DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
N
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
P DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC SUB
R
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
T DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
U
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
V DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
W ADC ADC ADC ADC ADC ADC DAC
DAC VCC
DAC
VCC AMS
Y
ADC
ADC DAC DAC DAC DAC
AA ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
VCC AMS
AB
ADC
ADC
ADC AUX
ADC VCC
ADC
AC ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
AD
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
AE ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC SUB
VCC AMS
AF
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
13
15
AG 33 ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
AH
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
34
AJ ADC ADC ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
35
AK
ADC
24 21 22 23 87
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
BT AU AU AU
DP DP
PL AU
L P PL PL AD
F P DP L P
AD
F P
LP LP DD
FP FP FP DD
FP FP
DD DD
r rV
RR
H
V
RR J
V
K
E
L
r rE
M
E
N
r rV
P
V
R
r rV
T
r rV
U
E
V
E
V
W
E
Y
V
AA
AB
V
AC
E
AD
V
AE
E
AF
V
AG
E
AH
V
AJ
AK
AL ADC ADC ADC
AL
AM
ADC ADC ADC
AM
AN ADC ADC ADC
AN
AP
ADC
AP
AR ADC ADC ADC
AR
AT
38
AT
AU
AU
AV
AV
AW
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC r RSVD R RSVDGND E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
VCC AMS
VCCINT_AMS
ADC VCC
ADC_AVCC
ADC AUX
ADC_AVCCAUX
ADC ADC_GND
ADC SUB
ADC_SUB_GND
DAC VCC
DAC_AVCC
DAC AUX
DAC_AVCCAUX
DAC VTT
DAC_AVTT
DAC DAC_GND
DAC SUB
DAC_SUB_GND
n NC
Dedicated Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
Multi-Function I/O Pins PS Pins
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-52: FFVG1517 and FSVG1517 Packages--XCZU25DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
172
Chapter 4: Device Diagrams
FFVG1517 and FSVG1517 Packages�XCZU27DR and XCZU28DR
X-Ref Target - Figure 4-53
V V
12
A
B
C3 3 229
D
E22 229
F
G1 1 229
H
J00 229
K L33
228
M
N2 2 228
P
R1 1 228
T U0 0
228
V
W
Y33 227
AA AB 1 1
227
AC
AD 3 3 226
AE
AF 1 1 226
AG AH 3 3
225
AJ
AK 1 1 225
AL
AM 3 3 224
AN AP 1 1
224
AR
AT
AU 4 4
AV 3 AW
12
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
10 11 11 12 12 23 23 24 24 24 24 20 24 24 22 20 S 32 33 46
10 7 8V7CCO 7 8 8
19 21 21 22
22 22 20 23
22 19 20 29 5V01CCO 34 39 49
9 9 5 5 4 8V7CCO S 19 20
22 21 21 19
23 21 21 19
27 31 36 41 47
3
6 6 4 S 6V8CCO 20 18 23 23
19 S S 18 6V7CCO 16 16 30 40
43 48
1322
17 16 16 18 6V9CCO 17 18 18 S
18 17 17 15 5V01CCO 35 38 42 51
1
6 9 9 17
15 15 17 13 6V9CCO 16 14 13 13
15 28 37 44
50
5 5 4 6 S 6V8CCO 13 13 15 15
13 14 16 14 6V7CCO 11 12 S 26
45 61 63
334
12 12 14 14 6V8CCO 7 11 11 14
10 9 11 12 5V02CCO 57 58 59 71 68
1 1 2 11 11
10 10 7 9 6V9CCO 12 12 10 9
7 7 55 60 5V02CCO 67 72
28877
9 8 10 10 6V7CCO 4 4
8
62 64 70 73
22 131
00 131
22 130
00 130
G
33 131
11 131
33 130
11 130
33 129
3 3
131
1 1
131
3 3
130
1 1
130
3 3
129
5
44
8
6 6 3 5 5 8 53 56 65
77
22
129
5312
6S23
54 69 74 76
1 1
131
1 1
129
CC
229
312
6
211
52 66 75 12
1
11 14
0 0
131
11 129
00 129
CC
228
SS 228
0 9 13 16
73 5V00CCO 8
17 15 23
1 1
130
33 128
0 0
130
22 128
4 10 20 21
1 1
11
R
6 5V00CCO 19 25
129
128
0 0
129
CC
227
2 18 22 24
5 PG
CK
1 1
128
0 0
128
00 128
CC
R
IN DN SR PR MD MD
226
5V03CCO RC
MD
ES
3 3
505
CC
225
MS DI DO
5V03CCO PI
MD
2 2
505
33 505
CC
224
VV 227
VV 226
VV 225
S 18 18 24 24
23 S
16 23 22
23 24 6V5CCO 17 17 16 23
22
21 24 22 15 15 6V4CCO 19 21 21
21 19 22
14 14 19 S 6V6CCO 20 20 23 21
EO PO 62
63
61
60 P N
59 58 DM
24 27 26 A
57 56
1 1
505
0 0
505
G
22 505
11 505
00 505
VV 224
18 18 17 9 S 19 20 13 13 12 17 18 18 16 DM 25 P N
A AC BG AL
15 15 17 9 6V5CCO 7 10 20 11 6V4CCO 12 15 17 13
16 P N 20
DM 31 A
A 5V04CCO BA RS 53 52 DM
P
16 16
12 11 7 10
11 10 10 15 6V6CCO 13 14 S 22
19 29 28 30
BA PA BG ZQ
55 54 N
12 12 8V4CCO 13 14 12 11
79S8
11 12 12 14
18 17 16
9
5V04CCO
A
A
A OD 5V04CCO 46 47 67 70
11 11 13 14 6V5CCO 8 8 7 9 8 6V4CCO 7 11 9
8 10 7 6
P 11 A C
CS CE 45 44
65 P
788 S644
5 5 7 9 6V6CCO S 8 10
P
8
N
DM 5V04CCO CN
A
A
A
5V04CCO
P
DM 64
N
6 6 7 10 8V4CCO 9
6
2366
3566
DM N 10
12 A A C
A 40 N 35
34
3
5 5 10 9
1323
2435
245 4
2
13 14
A
5V04CCO CN
A
OD 41 5V04CCO 38 DM
P
A
B C 2
2 131
D E 0
0 131
F G 2
2 130
H J 0
0 130
K L 2
2 129
M N 0
0 129
P R 3
3 128
T U 2
2 128
V W 1
1 128
Y 0 0 AA
128
AB 3 3 AC
505
AD 2 2 AE
505
AF 1 1 AG
505
AH 0 0 AJ
505
AK
48 AL
49 50 AM
51 AN
69 71 AP
DM 68 AR
66 AT
33 32 AU
36 AV
2211
5513
1124
1124
3 1 0 15
A CS CE A
43 42 39 37 N
AW
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 69 Bank 84 Bank 87
Quad 128 Quad 129 Quad 130 Quad 131 Bank 224 Bank 225 Bank 226 Bank 227
Bank 228 Bank 229 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP VREF
ADC/DAC Pins
# ADC_VIN_#_P # ADC_VIN_#_N C ADC_CLK_P C ADC_CLK_N R ADC_REXT V VCM01 V VCM23 # DAC_VOUT_#_P # DAC_VOUT_#_N C DAC_CLK_P C DAC_CLK_N R DAC_REXT S SYSREF_P S SYSREF_N
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
MGTAVTTRCAL G MGTRREF
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-53: FFVG1517 and FSVG1517 Packages--XCZU27DR and XCZU28DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
173
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-54
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
DAC
V
A
B DAC DAC DAC
V
B
C
DAC
V
C
D DAC DAC DAC
V
D
E
DAC DAC
V
E
F DAC DAC DAC DAC
V
F
G
DAC DAC
V
G
H DAC
DAC
DAC
DAC VTT
J
DAC
DAC VTT
K DAC
DAC
DAC
DAC VTT
DAC
L
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
M DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
N
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
P DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC SUB
R
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
T DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
U
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
V DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
W ADC ADC ADC ADC ADC ADC DAC
DAC VCC
DAC
VCC AMS
Y
ADC
ADC DAC DAC DAC DAC
AA ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
VCC AMS
AB
ADC
ADC
ADC AUX
ADC VCC
ADC
AC ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
AD
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
AE ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC SUB
VCC AMS
AF
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
13
15
AG 33 ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
AH
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
34
AJ ADC ADC ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
35
AK
ADC
24 21 22 23 87
V
E
VCC FEC
VCC FEC
E
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
E
VCC FEC
VCC FEC
VCC FEC
VCC FEC
BT AU AU AU
VCC FEC
DP DP
PL AU
VCC FEC
L P PL PL AD
VCC FEC
F P DP L P
AD
VCC FEC
F P
LP LP DD
VCC FEC
FP FP FP DD
VCC FEC
FP FP
DD DD
V
V
E
V V
V V
E V
E V
V E
V E
V E
V
H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
AL ADC ADC ADC
AL
AM
ADC ADC ADC
AM
AN ADC ADC ADC
AN
AP
ADC
AP
AR ADC ADC ADC
AR
AT
38
AT
AU
AU
AV
AV
AW
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Power Pins
Dedicated Pins Multi-Function I/O Pins PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
VCC AMS
VCCINT_AMS
ADC VCC
ADC_AVCC
ADC AUX
ADC_AVCCAUX
ADC ADC_GND
ADC SUB
ADC_SUB_GND
DAC VCC
DAC_AVCC
DAC AUX
DAC_AVCCAUX
DAC VTT
DAC_AVTT
DAC DAC_GND
DAC SUB
DAC_SUB_GND
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-54: FFVG1517 and FSVG1517 Packages--XCZU27DR and XCZU28DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
174
Chapter 4: Device Diagrams
FFVG1517 and FSVG1517 Packages�XCZU43DR
X-Ref Target - Figure 4-55
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A B C D E0 0
231
F G H J00
230
K
10 11 11
12 12 23 23
24 24 24 24
20 24 24 22
20 S 32 33
46
10 8V7CCO 7 995
788 5 8V7CCO 4
19 21 21 22
22 22 20 23
22 19 20 29 5V01CCO 34 39 49
S 19 20
22 21 21 19
23 21 21 19
27 31 36 41 47
3
6 6 4 S 6V8CCO 20 18 23 23
19 S S 18 6V7CCO 16 16 30 40
43 48
1322
17 16 16 18 6V9CCO 17 18 18 S
18 17 17 15 5V01CCO 35 38 42 51
1
6 9 9 17
15 15 17 13 6V9CCO 16 14 13 13
15 28 37 44
50
5 5 4 6 S 6V8CCO 13 13 15 15
13 14 16 14 6V7CCO 11 12 S 26
45 61 63
334
12 12 14 14 6V8CCO 7 11 11 14
10 9 11 12 5V02CCO 57 58 59 71 68
1 1 2 11 11
10 10 7 9 6V9CCO 12 12 10 9
7
7 55 60 5V02CCO 67 72
28877
9
8 10 10 6V7CCO 4
4
8
62 64 70 73
22 131
00 131
22 130
00 130
G
33 131
11 131
33 130
11 130
33 129
3 3
131
1 1
131
3 3
130
1 1
130
3 3
129
A
B
C 2 2 131 D
E 0 0 131 F
G 2 2 130 H
J 0 0 130 K
L
5
44
8
6 6 3 5 5 8 53 56 65
77
22
L 2 2
129
129
M
5312
6S23
54 69 74 76
1 1
1 1
M
131
129
N0 0 229
CC 230
312
6
211
52 66 75 12
11 129
N 0 0 129
P
1
11 14
0 0
00
P
131
129
R
CC
228
0 9 13 16
33 128
R 3 3 128
T U0 0
228
SS 228
73 5V00CCO 8
17 15 23
1 1
130
0 0
130
22 128
T U 2
2 128
V
W
R
4 10 20 21 6 5V00CCO 19 25
1 1
129
0 0
129
11 128
V W 1
1 128
Y
CC
227
2 18 22 24
1 1
00
Y
128
128
AA
5 PG
CK
0 0
128
0 0 AA 128
AB 1 1
CC
R
227
226
AC
IN DN SR PR MD MD
5V03CCO RC
MD
ES
3 3
505
AB 3 3 AC
505
AD
CC
225
AE
MS DI DO
5V03CCO
PI
MD
2 2
505
33 505
AD 2 2 AE
505
AF 1 1 226
CC 224
S 18 18
24 24
EO PO 62
22 505
AF
AG
AH
V
AJ
V
AK 1 1
V
225
23
S
16 23
22
23 24 6V5CCO 17 17 16 23
22
21 24 22 15 15 6V4CCO 19 21 21
21 19 22
14 14 19 S 6V6CCO 20 20 23 21
63
61
60 P N
59 58 DM
24 27 26 A
57 56
1 1
505
0 0
505 G
11 505
00 505
1 1 AG 505 AH
0 0 AJ 505 AK
AL
V
18 18 17 9 S 19
20 13 13 12
17 18 18 16
DM 25 P N
A AC BG AL
48 AL
AM
15 15 17 9 6V5CCO 7 10 20 11 6V4CCO 12 15 17 13
16 P N 20
DM 31 A
A
5V04CCO BA
RS
53 52 DM
P
49 50 AM
AN
16 16
12 11 7 10
11 10 10 15 6V6CCO 13 14 S 22
19 29 28 30
BA PA BG ZQ
55 54 N 51
AN
AP 1 1 224
AR
12 12 8V4CCO 13 14 12 11
7 9S8
11 12 12 14
18 17 16
9
5V04CCO
A
A
A
OD 5V04CCO 46 47 67 70
69 71 AP
11 11 13 14 6V5CCO 8
8
7
9 6V4CCO 8
7 11 9
8 10 7 6
P 11 A C
CS CE 45 44
65 P DM 68 AR
AT
788
S644
5
5
7 6V6CCO 9
S
8 10
P
8
N
DM 5V04CCO CN
A
A
A
5V04CCO
P
DM 64
N
66 AT
AU 4 4 6 6 7 8V4CCO 10 9
6
2366
3566
DM N 10
12 A A C
A 40 N 35
34 33 32 AU
AV
33
5 5 10 9
1323
2435
2454
2
13 14
A
5V04CCO CN
A
OD 41 5V04CCO 38 DM
P
36
AV
AW
2211
5513
1124
1124
3 1 0 15
A CS CE A
43 42 39 37 N
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 64 Bank 65 Bank 66 Bank 67
Bank 68 Bank 69 Bank 84 Bank 87
Quad 128 Quad 129 Quad 130 Quad 131
Bank 224 Bank 225 Bank 226 Bank 227
Bank 228 Bank 230 PS Bank 500 PS Bank 501
PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP VREF
ADC/DAC Pins
# ADC_VIN_#_P # ADC_VIN_#_N C ADC_CLK_P C ADC_CLK_N R ADC_REXT V VCM01 V VCM23 # DAC_VOUT_#_P # DAC_VOUT_#_N C DAC_CLK_P C DAC_CLK_N R DAC_REXT S SYSREF_P S SYSREF_N
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
MGTAVTTRCAL G MGTRREF
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-55: FFVG1517 and FSVG1517 Packages--XCZU43DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
175
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-56
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
DAC
V
A
B DAC DAC DAC
V
B
Cn
DAC
V
C
D DAC DAC DAC
V
D
E
DAC DAC
V
E
F DAC DAC DAC DAC
V
F
G n n DAC DAC
V
G
H DAC
DAC
DAC
DAC VTT
J
DAC
DAC VTT
K DAC
DAC
DAC
DAC VTT
DAC
L
n
n
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
M DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
N
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
P DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC SUB
R n n DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
T DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
U
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
V DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
W ADC ADC ADC ADC ADC ADC DAC
DAC VCC
DAC
VCC AMS
Y n n ADC
ADC DAC DAC DAC DAC
AA ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
VCC AMS
AB
ADC
ADC
ADC AUX
ADC VCC
ADC
AC ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
AD n n ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
AE ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC SUB
VCC AMS
AF
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
13
15
AG ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
33
AH n n ADC n
ADC
ADC AUX
ADC
ADC VCC
ADC
34
AJ ADC ADC ADC n
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
35
AK
ADC n
24 21 22 23 87
V
E
VCC FEC
VCC FEC
E
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
E
VCC FEC
VCC FEC
VCC FEC
VCC FEC
BT AU AU AU
VCC FEC
DP DP
PL AU
VCC FEC
L P PL PL AD
VCC FEC
F P DP L P
AD
VCC FEC
F P
LP LP DD
VCC FEC
FP FP FP DD
VCC FEC
FP FP
DD DD
V
V
E
V V
V V
E V
E V
V E
V E
V E
V
H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
AL ADC ADC ADC n
AL
AM n n ADC ADC ADC
AM
AN ADC ADC ADC
AN
AP
ADC
AP
AR ADC ADC ADC
AR
AT
38
AT
AU
AU
AV
AV
AW
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC r RSVD R RSVDGND E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
VCC AMS
VCCINT_AMS
ADC VCC
ADC_AVCC
ADC AUX
ADC_AVCCAUX
ADC ADC_GND
ADC SUB
ADC_SUB_GND
DAC VCC
DAC_AVCC
DAC AUX
DAC_AVCCAUX
DAC VTT
DAC_AVTT
DAC DAC_GND
DAC SUB
DAC_SUB_GND
n NC
Dedicated Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
Multi-Function I/O Pins PS Pins
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-56: FFVG1517 and FSVG1517 Packages--XCZU43DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
176
Chapter 4: Device Diagrams
FFVG1517 and FSVG1517 Packages�XCZU47DR
X-Ref Target - Figure 4-57
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
B
C2 2 231
D
E0 0 231
F
G2 2 230
H
J0 0 230
K
10 11 11
12 12 23 23
24 24 24 24
20 24 24 22
20 S 32 33
46
10 8V7CCO 7 995
788
5
8V7CCO
4
19 21 21 22
22 22 20 23
22 19 20 29 5V01CCO 34 39 49
S 19 20
22 21 21 19
23 21 21 19
27 31 36 41 47
3
6
6
4
S 6V8CCO 20 18 23 23
19 S S 18 6V7CCO 16 16 30 40
43 48
1322
17 16 16 18 6V9CCO 17 18 18 S
18 17 17 15 5V01CCO 35 38 42 51
1
6 9 9 17
15 15 17 13 6V9CCO 16 14 13 13
15 28 37 44
50
5
5
4
6
S 6V8CCO 13 13 15 15
13 14 16 14 6V7CCO 11 12 S 26
45 61 63
334
12 12 14 14 6V8CCO 7 11 11 14
10 9 11 12 5V02CCO 57 58 59 71 68
1 1 2 11 11
10 10 7 9 6V9CCO 12 12 10 9
7
7 55 60 5V02CCO 67 72
28877
9
8 10 10 6V7CCO 4
4
8
62 64 70 73
22 131
00 131
22 130
00 130
G
33 131
11 131
33 130
11 130
33 129
3 3
131
1 1
131
3 3
130
1 1
130
3 3
129
A
B
C 2 2 131 D
E 0 0 131 F
G 2 2 130 H
J 0 0 130 K
L2 2 229
5
44
8
6 6 3 5 5 8 53 56 65
77
22 129
L 2 2 129
M
5312
6S23
54 69 74 76
1 1
1 1
M
131
129
N0 0 229
CC 230
312
6
211
52 66 75 12
11 129
N 0 0 129
P
1
11 14
0 0
00
P
131
129
R2 2 228
CC 228
0 9 13 16
33 128
R 3 3 128
T U0 0
228
SS 228
73
5V00CCO
8
17 15 23
1 1
130
0 0
130
22 128
T U 2
2 128
V
W
R
4 10 20 21 6 5V00CCO 19 25
1 1
129
0 0
129
11 128
V W 1
1 128
Y3 3 227
CC 227
2 18 22 24
1 1
00
Y
128
128
AA
5 PG
CK
0 0
128
0 0 AA 128
AB 1 1
CC
R
227
226
AC
IN DN SR PR MD MD
5V03CCO
RC
MD
ES
3 3
505
AB 3 3 AC
505
AD 3 3 226
AE
CC 225
MS DI DO
5V03CCO
PI
MD
2 2
505
33 505
AD 2 2 AE
505
AF 1 1 226
CC 224
S 18 18
24 24
EO PO 62
22
AF
505
AG AH 3 3
225
AJ AK 1 1
225
VV 227
VV 226
VV 225
23
S
16 23
22
23 24 6V5CCO 17 17 16 23
22
21 24 22 15 15 6V4CCO 19 21 21
21 19 22
14 14 19 S 6V6CCO 20 20 23 21
63
61
60 P N
59 58 DM
24 27 26 A
57 56
1 1
505
0 0
505 G
11 505
00 505
1 1
505
AG AH
0 0 AJ 505 AK
AL
AM 3 3 224
AN
VV 224
18 18 17 9 S 19
20 13 13 12
17 18 18 16
DM 25 P N
A AC BG AL
48 AL
15 15 17
9
6V5CCO
7
10 20 11 6V4CCO 12 15 17 13
16 P N 20
DM 31 A
A
5V04CCO
BA
RS 53 52 DM
P
49 50 AM
16 16
12 11 7 10
11 10 10 15 6V6CCO 13 14 S 22
19 29 28 30
BA PA BG ZQ
55 54 N 51
AN
AP 1 1 224
AR
12 12 8V4CCO 13 14 12 11
79S8
11 12 12 14
18 17 16
9
5V04CCO
A
A
A
OD 5V04CCO 46 47 67 70
69 71 AP
11 11 13 14 6V5CCO 8
8
7
9
6V4CCO
8
7 11 9
8 10 7 6
P 11 A C
CS CE 45 44
65 P DM 68 AR
AT
788
S644
5
5
7 6V6CCO 9
S
8 10
P
8
N
DM
5V04CCO
CN
A
A
A
5V04CCO
P
DM 64
N
66 AT
AU 4
4
6
6
7 8V4CCO 10
9
6
2366
3566
DM N 10
12 A A C
A 40 N 35
34 33 32 AU
AV
33
5 5 10 9
1323
2435
2454
2
13 14
A
5V04CCO
CN
A
OD 41 5V04CCO 38 DM
P
36
AV
AW
2211
5513
1124
1124
3 1 0 15
A CS CE A
43 42 39 37 N
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 69 Bank 84 Bank 87
Dual 128 Dual 129 Dual 130 Dual 131 Bank 224 Bank 225 Bank 226 Bank 227
Bank 228 Bank 229 Bank 230 Bank 231 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503
PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP VREF
ADC/DAC Pins Transceiver Pins
# ADC_VIN_#_P # ADC_VIN_#_N C ADC_CLK_P C ADC_CLK_N R ADC_REXT V VCM01 V VCM23 # DAC_VOUT_#_P # DAC_VOUT_#_N C DAC_CLK_P C DAC_CLK_N R DAC_REXT S SYSREF_P S SYSREF_N
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
MGTAVTTRCAL G MGTRREF
PS Pins
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-57: FFVG1517 and FSVG1517 Packages--XCZU47DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
177
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-58
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
DAC
V
A
B DAC DAC DAC
V
B
C
DAC
V
C
D DAC DAC DAC
V
D
E
DAC DAC
V
E
F DAC DAC DAC DAC
V
F
G
DAC DAC
V
G
H DAC
DAC
DAC
DAC VTT
J
DAC
DAC VTT
K DAC
DAC
DAC
DAC VTT
DAC
L
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
M DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
N
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
P DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC SUB
R
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
T DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
U
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
V DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
W ADC ADC ADC ADC ADC ADC DAC
DAC VCC
DAC
VCC AMS
Y
ADC
ADC DAC DAC DAC DAC
AA ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
VCC AMS
AB
ADC
ADC
ADC AUX
ADC VCC
ADC
AC ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
AD
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
AE ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC SUB
VCC AMS
AF
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
13
15
AG ADC ADC ADC ADC ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
33
AH
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
34
AJ ADC ADC ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
35
AK
ADC
24 21 22 23 87
V
E
VCC FEC
VCC FEC
E
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
E
VCC FEC
VCC FEC
VCC FEC
VCC FEC
BT AU AU AU
VCC FEC
DP DP
PL AU
VCC FEC
L P PL
AD
VCC FEC
F P DP L P
AD
VCC FEC
F P
LP LP DD
VCC FEC
FP FP FP DD
VCC FEC
FP FP
DD DD
V
V
E
V V
V V
E V
E V
V E
V E
V E
V
H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
AL ADC ADC ADC
AL
AM
ADC ADC ADC
AM
AN ADC ADC ADC
AN
AP
ADC
AP
AR ADC ADC ADC
AR
AT
38
AT
AU
AU
AV
AV
AW
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC r RSVD R RSVDGND E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
VCC AMS
VCCINT_AMS
ADC VCC
ADC_AVCC
ADC AUX
ADC_AVCCAUX
ADC ADC_GND
ADC SUB
ADC_SUB_GND
DAC VCC
DAC_AVCC
DAC AUX
DAC_AVCCAUX
DAC VTT
DAC_AVTT
DAC DAC_GND
DAC SUB
DAC_SUB_GND
n NC
Dedicated Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
Multi-Function I/O Pins PS Pins
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-58: FFVG1517 and FSVG1517 Packages--XCZU47DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
178
Chapter 4: Device Diagrams
FFVG1517 and FSVG1517 Packages�XCZU48DR
V V
X-Ref Target - Figure 4-59
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
B
C2 2 231
D
E0 0 231
F
G2 2 230
H
J0 0 230
K
10 11 11
12 12 23 23
24 24 24 24
20 24 24 22
20 S 32 33
46
10 8V7CCO 7 995
788
5
8V7CCO
4
19 21 21 22
22 22 20 23
22 19 20 29 5V01CCO 34 39 49
S 19 20
22 21 21 19
23 21 21 19
27 31 36 41 47
3
6
6
4
S 6V8CCO 20 18 23 23
19 S S 18 6V7CCO 16 16 30 40
43 48
1322
17 16 16 18 6V9CCO 17 18 18 S
18 17 17 15 5V01CCO 35 38 42 51
1
6 9 9 17
15 15 17 13 6V9CCO 16 14 13 13
15 28 37 44
50
5
5
4
6
S 6V8CCO 13 13 15 15
13 14 16 14 6V7CCO 11 12 S 26
45 61 63
334
12 12 14 14 6V8CCO 7 11 11 14
10 9 11 12 5V02CCO 57 58 59 71 68
1 1 2 11 11
10 10 7 9 6V9CCO 12 12 10 9
7
7 55 60 5V02CCO 67 72
28877
9
8 10 10 6V7CCO 4
4
8
62 64 70 73
22 131
00 131
22 130
00 130
G
33 131
11 131
33 130
11 130
33 129
3 3
131
1 1
131
3 3
130
1 1
130
3 3
129
A
B
C 2 2 131 D
E 0 0 131 F
G 2 2 130 H
J 0 0 130 K
L2 2 229
5
44
8
6 6 3 5 5 8 53 56 65
77
22 129
L 2 2 129
M
5312
6S23
54 69 74 76
1 1
1 1
M
131
129
N0 0 229
CC 230
312
6
211
52 66 75 12
11 129
N 0 0 129
P
1
11 14
0 0
00
P
131
129
R2 2 228
CC 228
0 9 13 16
33 128
R 3 3 128
T U0 0
228
SS 228
73
5V00CCO
8
17 15 23
1 1
130
0 0
130
22 128
T U 2
2 128
V
W
R
4 10 20 21 6 5V00CCO 19 25
1 1
129
0 0
129
11 128
V W 1
1 128
Y3 3 227
CC 227
2 18 22 24
1 1
00
Y
128
128
AA
5 PG
CK
0 0
128
0 0 AA 128
AB 1 1
CC
R
227
226
AC
IN DN SR PR MD MD
5V03CCO
RC
MD
ES
3 3
505
AB 3 3 AC
505
AD 3 3 226
AE
CC 225
MS DI DO
5V03CCO
PI
MD
2 2
505
33 505
AD 2 2 AE
505
AF 1 1 226
CC 224
S 18 18
24 24
EO PO 62
22
AF
505
AG AH 3 3
225
AJ AK 1 1
225
VV 227
VV 226
VV 225
23
S
16 23
22
23 24 6V5CCO 17 17 16 23
22
21 24 22 15 15 6V4CCO 19 21 21
21 19 22
14 14 19 S 6V6CCO 20 20 23 21
63
61
60 P N
59 58 DM
24 27 26 A
57 56
1 1
505
0 0
505 G
11 505
00 505
1 1
505
AG AH
0 0 AJ 505 AK
AL
AM 3 3 224
AN
VV 224
18 18 17 9 S 19
20 13 13 12
17 18 18 16
DM 25 P N
A AC BG AL
48 AL
15 15 17
9
6V5CCO
7
10 20 11 6V4CCO 12 15 17 13
16 P N 20
DM 31 A
A
5V04CCO
BA
RS 53 52 DM
P
49 50 AM
16 16
12 11 7 10
11 10 10 15 6V6CCO 13 14 S 22
19 29 28 30
BA PA BG ZQ
55 54 N 51
AN
AP 1 1 224
AR
12 12 8V4CCO 13 14 12 11
79S8
11 12 12 14
18 17 16
9
5V04CCO
A
A
A
OD 5V04CCO 46 47 67 70
69 71 AP
11 11 13 14 6V5CCO 8
8
7
9
6V4CCO
8
7 11 9
8 10 7 6
P 11 A C
CS CE 45 44
65 P DM 68 AR
AT
788
S644
5
5
7 6V6CCO 9
S
8 10
P
8
N
DM
5V04CCO
CN
A
A
A
5V04CCO
P
DM 64
N
66 AT
AU 4
4
6
6
7 8V4CCO 10
9
6
2366
3566
DM N 10
12 A A C
A 40 N 35
34 33 32 AU
AV
33
5 5 10 9
1323
2435
2454
2
13 14
A
5V04CCO
CN
A
OD 41 5V04CCO 38 DM
P
36
AV
AW
2211
5513
1124
1124
3 1 0 15
A CS CE A
43 42 39 37 N
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 69 Bank 84 Bank 87
Dual 128 Dual 129 Dual 130 Dual 131 Bank 224 Bank 225 Bank 226 Bank 227
Bank 228 Bank 229 Bank 230 Bank 231 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503
PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP VREF
ADC/DAC Pins
# ADC_VIN_#_P # ADC_VIN_#_N C ADC_CLK_P C ADC_CLK_N R ADC_REXT V VCM01 V VCM23 # DAC_VOUT_#_P # DAC_VOUT_#_N C DAC_CLK_P C DAC_CLK_N R DAC_REXT S SYSREF_P S SYSREF_N
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
MGTAVTTRCAL G MGTRREF
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-59: FFVG1517 and FSVG1517 Packages--XCZU48DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
179
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-60
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A
DAC
V
A
B DAC DAC DAC
V
B
C
DAC
V
C
D DAC DAC DAC
V
D
E
DAC DAC
V
E
F DAC DAC DAC DAC
V
F
G
DAC DAC
V
G
H DAC
DAC
DAC
DAC VTT
J
DAC
DAC VTT
K DAC
DAC
DAC
DAC VTT
DAC
L
DAC
DAC VTT
DAC
DAC AUX
DAC AUX
M DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
N
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
P DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC SUB
R
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
T DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
U
DAC
DAC
DAC AUX
DAC
DAC VCC
DAC
VCC AMS
V DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC VCC
DAC
W ADC ADC ADC ADC ADC ADC DAC
DAC VCC
DAC
VCC AMS
Y
ADC
ADC DAC DAC DAC DAC
AA ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
VCC AMS
AB
ADC
ADC
ADC AUX
ADC VCC
ADC
AC ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
AD
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
AE ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC SUB
VCC AMS
AF
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
13
15
AG ADC ADC ADC ADC ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
33
AH
ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
34
AJ ADC ADC ADC
ADC
ADC AUX
ADC
ADC VCC
ADC
VCC AMS
35
AK
ADC
24 21 22 23 87
V
E
VCC FEC
VCC FEC
E
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
E
VCC FEC
VCC FEC
VCC FEC
VCC FEC
BT AU AU AU
VCC FEC
DP DP
PL AU
VCC FEC
L P PL
AD
VCC FEC
F P DP L P
AD
VCC FEC
F P
LP LP DD
VCC FEC
FP FP FP DD
VCC FEC
FP FP
DD DD
V
V
E
V V
V V
E V
E V
V E
V E
V E
V
H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
AL ADC ADC ADC
AL
AM
ADC ADC ADC
AM
AN ADC ADC ADC
AN
AP
ADC
AP
AR ADC ADC ADC
AR
AT
38
AT
AU
AU
AV
AV
AW
AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC r RSVD R RSVDGND E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
VCC AMS
VCCINT_AMS
ADC VCC
ADC_AVCC
ADC AUX
ADC_AVCCAUX
ADC ADC_GND
ADC SUB
ADC_SUB_GND
DAC VCC
DAC_AVCC
DAC AUX
DAC_AVCCAUX
DAC VTT
DAC_AVTT
DAC DAC_GND
DAC SUB
DAC_SUB_GND
n NC
Dedicated Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
Multi-Function I/O Pins PS Pins
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-60: FFVG1517 and FSVG1517 Packages--XCZU48DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
180
Chapter 4: Device Diagrams
FFVC1760 Package�XCZU11EG
X-Ref Target - Figure 4-61
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
10 12 12 10 11 12 12 16 17 17 S 22 24 21 21 23 24 24 24 20 20 9 9 10 18 18 17 21 21 22 22
A
B 9 9 10
11 11 10 11 9V0CCO 10 11 11 16
18 20 22 24
20 22 23 24
22 22 21 19
8 10 14 14 6V9CCO 17 20 20 S
23 23 24 B
C 6 8 9V1CCO 8 7 7
8 12 10 9 15 8V9CCO S 18 20 6V8CCO 23 19 20 22 7V1CCO S 23 23 21 7V0CCO 19 8 12 12
15 16 S 19 19
24 C
D 4 6 5 5 9 9V1CCO 7 8 12
9 8 15 14 19 21 23 19 17 18 S S
S 17 17 7 6V9CCO 11 13 15 16
3 3
D
131
E4332297
4 7 7 8 13 14 19 21 15 16 17 18 18 14 16 16 7 S 11 13
33
F
1115645
6 6 13 12 6V8CCO 11 10 15 16 7V1CCO 14 14 18 14 7V0CCO 15 15 5 4 3 3
131 22
G3 3
1 5 6 5 9V0CCO 2 3 4
7 12 11 10
12 13 13 10
12 13 13 5 6V9CCO 4
131 11
231
H
3
3
2 3 1 2 3 8V9CCO 4 7 8
9 11 11 12 10 12 11 11 6
2
131 00
231
J2 2
2
2
23
1 12 12 11 6V8CCO 8 S 9 7 7V1CCO 9 10 9 9 8 7V0CCO 7 6 1 2
131
1 1
33
231
231
131
130
1 1
131
3 3
130
E 2 2 131 F
G 0 0 131 H
J 2 2 130
K
1
1
231
L1 1 231
0
0
231
M
0 0
3
3
231
230
N3 3 230
2
2
230
10 10 7 11 5 5 6
7 8 9 10 4 S 8 7
1
9 7 8V8CCO 8 8 4
6238
S642
26 28 27 30
9 6 6 5 4 8V8CCO 3 3 2
3666
2
29 31
32
1125412
1445
5 3 3 1 5V01CCO 33 35 37
0 0
131
1 1
130
22 130
00 130
11 130
33 129
1 1
130
3 3
129
K L 0
0 130
M N 2
2 129
P
2 2
1
1
23412
1
5
5
1 34 40 39 41
22
230
230
129
1 1
P
129
R1 1
0
0
1 1
3
230
230
231
38
44 43
0 0
130
11 129
R 0 0 129
T U3
3 229
0 0
230
2
2
229
3
3
229
1 1
230
0 0
231
36 47 45 42 EO 46 49 5V01CCO
G
1 1
129
00 129
33 128
3 3
128
T U 2
2 128
V W1
1 229
2 2
229
0
0
229
1
1
229
1 1
229
0 0
230
IN ES 50 48 PR 5V03CCO 52 51
0 0
129
22 128
11 128
1 1
128
V W 0
0 128
Y
0 0
3
3
0 0
229
228
229
PG DN 54 53
00
Y
128
AA 3 3 228
2
2
228
1 1
228
MD MD
56
1 1
128
3 3
505
3 3 AA 505
AB
AC 1 1 228
AD
2 2
228
0 0
228
0
0
228
1
1
228
3
3
227
1 1
227
0 0
228
0 0
227
SR MD 55 57 CK RC MD 58 5V02CCO 59 61
0 0
128
DI MS DO 5V03CCO 60 63 62 64 66 13 15
2 2
505
33 505
22 505
AB
2 2 AC 505 AD
AE 3 3 227
AF
AG 1 1 227
2 2
227
2
2
227
0
0
227
1
1
227
1 1
226
1 1
225
G
0 0
226
PO PI 65 67
69 68 18 19
70 71 72 75 5V00CCO 21 73 77 5V02CCO 74 25 23
1 1
505
0 0
505
11 505
G
1 1 AE 505 AF
0 0 AG 505
AH
0 0
227
3
3
226
0 0
225
76 22 24 20
00 505
AH
AJ 3 3 226
2
2
226
1 1
224
24 20 22 19 23 23 24 24
17 16 14
12 46 44 P
60 AJ
AK
2 2
226
1
1
226
0 0
224
24 20 22 19 22 22 24 23 24
10
11 8 9 47
N 42 43 62 63 61 AK
AL 1 1 226
AM
AN 3 3 225
AP
AR 1 1 225
0 0
226
2 2
225
0
0
226
2
2
225
0
0
225
3
3
225
1
1
225
21 19 23 S 20 S 21 21 23
7654
45 DM 40 41
AL P N DM
18 17
23 21 19 23
20 19 20 20
22 21 S 15
17 1
3
2 5V00CCO 0
RS
PA AL
57 56 58 59
AM
18 17 16 23 22 24 21 21 19 16 15 22 21 15 16 17 16
31 30 28 ZQ 5V04CCO BA BA 39 36
32 33 AN
14 S 16 6V7CCO 22 S 24 S 6V6CCO 18 17 16 15
20 20 S 16
17 18 19 29
A BG BG A
38 P 35 34 AP
14
13 13 15 15
17 16 18 17 6V4CCO S 19 14 14 6V5CCO 13 18 DM
P
5V04CCO
P
DM
A
A 5V04CCO AC 37 DM
N
48 AR
AT
0 0
3
3
12 12 11 11
14 18 17 16
14 13 13 19
12 12 13 18
N 20 N 26
A
AU 3 3
225 2
224 2
S 8 6V7CCO 10 12 14 18
15 14 12 11
7 7 11 11
10 23 21 22 5V04CCO 25 27 A
224
224
AV
2 2
10 10
8 7 10 12 6V6CCO 13 13 15 12 6V4CCO 11 8 7 7 8 6V5CCO 9 10 0
12 14 15 24
224
AW 1 1
1
1
3 1 9 9 7 11 11 3 3
99S8
1S8 9
2
1
3 13 5V04CCO A
A
224
AY
0
224 0
31
7 6V7CCO
55
1 10 10 4
2213
5 5 DM P
P N DM A
224
BA 0 0
544
9 8 7 6 4 6V6CCO 2 1 6 4 6V4CCO 3 3 1 3 6V5CCO 4
6
N 7 9 10
A
224
A OD CE
51 49 50 AT
A
5V04CCO CS
DM
P
N
AU
C CN 55 54
53 52 AV
A
AW A 5V04CCO 71 69 70 68
CS CE P N
DM AY
C CN A
67 65 66 BA
BB
665
2298
6S4 2
655
1224
66 5 4
8 11 A A
A OD 64
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 69 Bank 70 Bank 71
Bank 88 Bank 89 Bank 90 Bank 91 Quad 128 Quad 129 Quad 130 Quad 131
Quad 224 Quad 225 Quad 226 Quad 227 Quad 228 Quad 229 Quad 230 Quad 231
PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-61: FFVC1760 Package--XCZU11EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
181
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-62
V
V V V V V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
A
B
B
C
C
D
D
E
E
F
V
F
G
V
G
H
E
V
H
J
V
J
K
V
E
V
K
L
V
V
L
M
V
E
V
M
N
V
V
N
P
V
V
P
R
V
V
R
T
V
E
V
T
U
V
V
U
V
V
E
V
V
W
V
E
W
Y
V
E
E
Y
AA
V
E
24 21
E
E
AA
AB
V
E
22 23
V
AB
AC
V
E
87
V
AC
AD
V
E
V
AD
AE
V
PL
E
AE
AF
V
E
F P PL PL DP
E
AF
AG
V
F P AU AD DP AU
AG
AH
V
E
13 15
L P AU BT AD AU
AH
AJ
V
F P F P L P AD AD
AJ
AK
V
E
33
F P
DD LP LP
AK
AL
V
34
FP FP DD DD
AL
AM
V
35
AM
AN
V
AN
AP
V
AP
AR
V
AR
AT
V
AT
AU
AU
AV
V
AV
AW
38
AW
AY
AY
BA
BA
BB
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-62: FFVC1760 Package--XCZU11EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
182
Chapter 4: Device Diagrams
FFVC1760 Package�XCZU17EG and XCZU19EG
X-Ref Target - Figure 4-63
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
10 12 12 10 11 12 12 16 17 17 S 22 24 21 21 23 24 24 24 20 20 9 9 10 18 18 17 21 21 22 22
A
B 9 9 10 11 11 10 11 9V3CCO 10 11 11 16 18 20 22 24 20 22 23 24 22 22 21 19
8 10 14 14 6V9CCO 17 20 20 S
23 23 24 B
C 6 8 9V4CCO 8 7 7
8 12 10 9 15 9V1CCO S 18 20 6V8CCO 23 19 20 22 7V1CCO S 23 23 21 7V0CCO 19 8 12 12
15 16 S 19 19
24 C
D 4 6 5 5 9 9V4CCO 7 8 12
9 8 15 14 19 21 23 19 17 18 S S
S 17 17 7 6V9CCO 11 13 15 16
3 3
D
131
E4332297
4 7 7 8 13 14 19 21 15 16 17 18 18 14 16 16 7 S 11 13
33
F
1115645
6 6 13 12 6V8CCO 11 10 15 16 7V1CCO 14 14 18 14 7V0CCO 15 15 5 4 3 3
131 22
G3 3
1 5 6 5 9V3CCO 2 3 4
7 12 11 10
12 13 13 10
12 13 13 5 6V9CCO 4
131 11
231
H
3
3
2 3 1 2 3 9V1CCO 4 7 8
9 11 11 12 10 12 11 11 6
2
131 00
231
J2 2
2
2
23
1 12 12 11 6V8CCO 8 S 9 7 7V1CCO 9 10 9 9 8 7V0CCO 7 6 1 2
131
1 1
33
231
231
131
130
1 1
131
3 3
130
E 2 2 131 F
G 0 0 131 H
J 2 2 130
K
1
1
231
L1 1 231
0
0
231
M
0 0
3
3
231
230
N3 3 230
2
2
230
10 10 7 11 5 5 6
7 8 9 10 4 S 8 7
1
9 7 9V0CCO 8 8 4
6238
S642
26 28 27 30
9 6 6 5 4 9V0CCO 3 3 2
3666
2
29 31
32
1125412
1445
5 3 3 1 5V01CCO 33 35 37
0 0
131
1 1
130
22 130
00 130
11 130
33 129
1 1
130
3 3
129
K L 0
0 130
M N 2
2 129
P
2 2
1
1
23412
1
5
5
1 34 40 39 41
22
230
230
129
1 1
P
129
R1 1
0
0
1 1
3
230
230
231
38
44 43
0 0
130
11 129
R 0 0 129
T U3
3 229
0 0
230
2
2
229
3
3
229
1 1
230
0 0
231
36 47 45 42 EO 46 49 5V01CCO
G
1 1
129
00 129
33 128
3 3
128
T U 2
2 128
V W1
1 229
2 2
229
0
0
229
1
1
229
1 1
229
0 0
230
IN ES 50 48 PR 5V03CCO 52 51
0 0
129
22 128
11 128
1 1
128
V W 0
0 128
Y
0 0
3
3
0 0
229
228
229
PG DN 54 53
00
Y
128
AA 3 3 228
2
2
228
1 1
228
MD MD
56
1 1
128
3 3
505
3 3 AA 505
AB
AC 1 1 228
AD
2 2
228
0 0
228
0
0
228
1
1
228
3
3
227
1 1
227
0 0
228
0 0
227
SR MD 55 57 CK RC MD 58 5V02CCO 59 61
0 0
128
DI MS DO 5V03CCO 60 63 62 64 66 13 15
2 2
505
33 505
22 505
AB
2 2 AC 505 AD
AE 3 3 227
AF
AG 1 1 227
2 2
227
2
2
227
0
0
227
1
1
227
1 1
226
1 1
225
G
0 0
226
PO PI 65 67
69 68 18 19
70 71 72 75 5V00CCO 21 73 77 5V02CCO 74 25 23
1 1
505
0 0
505
11 505
G
1 1 AE 505 AF
0 0 AG 505
AH
0 0
227
3
3
226
0 0
225
76 22 24 20
00 505
AH
AJ 3 3 226
2
2
226
1 1
224
24 20 22 19 23 23 24 24
17 16 14
12 46 44 P
60 AJ
AK
2 2
226
1
1
226
0 0
224
24 20 22 19 22 22 24 23 24
10
11 8 9 47
N 42 43 62 63 61 AK
AL 1 1 226
AM
AN 3 3 225
AP
AR 1 1 225
0 0
226
2 2
225
0
0
226
2
2
225
0
0
225
3
3
225
1
1
225
21 19 23 S 20 S 21 21 23
7654
45 DM 40 41
AL P N DM
18 17
23 21 19 23
20 19 20 20
22 21 S 15
17 1
3
2 5V00CCO 0
RS
PA
AL
57 56 58 59
AM
18 17 16 23 22 24 21 21 19 16 15 22 21 15 16 17 16
31 30 28 ZQ 5V04CCO BA BA 39 36
32 33 AN
14 S 16 6V7CCO 22 S 24 S 6V6CCO 18 17 16 15
20 20 S 16
17 18 19 29
A BG BG A
38 P 35 34 AP
14
13 13 15 15
17 16 18 17 6V4CCO S 19 14 14 6V5CCO 13 18 DM
P
5V04CCO
P
DM
A
A 5V04CCO AC 37 DM
N
48 AR
AT
0 0
3
3
12 12 11 11
14 18 17 16
14 13 13 19
12 12 13 18
N 20 N 26
A
AU 3 3
225 2
224 2
S 8 6V7CCO 10 12 14 18
15 14 12 11
7 7 11 11
10 23 21 22 5V04CCO 25 27 A
224
224
AV
2 2
10 10
8 7 10 12 6V6CCO 13 13 15 12 6V4CCO 11 8 7 7 8 6V5CCO 9 10 0
12 14 15 24
224
AW 1 1
1
1
3 1 9 9 7 11 11 3 3
99S8
1S8 9
2
1
3
13 5V04CCO A
A
224
AY
0
224 0
31
7 6V7CCO
55
1 10 10 4
2213
5 5 DM P
P N DM A
224
BA 0 0
544
9 8 7 6 4 6V6CCO 2 1 6 4 6V4CCO 3 3 1 3 6V5CCO 4
6
N 7 9 10
A
224
A OD CE
51 49 50 AT
A
5V04CCO CS
DM
P
N
AU
C CN 55 54
53 52 AV
A
AW A 5V04CCO 71 69 70 68
CS CE P N
DM AY
C CN A
67 65 66 BA
BB
665
2298
6S4 2
655
1224
66 5 4
8 11 A A
A OD 64
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 69 Bank 70 Bank 71
Bank 90 Bank 91 Bank 93 Bank 94 Quad 128 Quad 129 Quad 130 Quad 131
Quad 224 Quad 225 Quad 226 Quad 227 Quad 228 Quad 229 Quad 230 Quad 231
PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins Transceiver Pins
PS Pins
VREF MGTAVTTRCAL G MGTRREF
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-63: FFVC1760 Package--XCZU17EG and XCZU19EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
183
X-Ref Target - Figure 4-64
Chapter 4: Device Diagrams
V
V V V V V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
A
B
B
C
C
D
D
E
E
F
V
F
G
V
G
H
E
V
H
J
V
J
K
V
E
V
K
L
V
V
L
M
V
E
V
M
N
V
V
N
P
V
V
P
R
V
V
R
T
V
E
V
T
U
V
V
U
V
V
E
V
V
W
V
E
W
Y
V
E
E
Y
AA
V
E
24 21
E
E
AA
AB
V
E
22 23
V
AB
AC
V
E
87
V
AC
AD
V
E
V
AD
AE
V
PL
E
AE
AF
V
E
F P PL PL DP
E
AF
AG
V
F P AU AD DP AU
AG
AH
V
E
13 15
L P AU BT AD AU
AH
AJ
V
F P F P L P AD AD
AJ
AK
V
E
33
F P
DD LP LP
AK
AL
V
34
FP FP DD DD
AL
AM
V
35
AM
AN
V
AN
AP
V
AP
AR
V
AR
AT
V
AT
AU
AU
AV
V
AV
AW
38
AW
AY
AY
BA
BA
BB
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-64: FFVC1760 Package--XCZU17EG and XCZU19EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
184
Chapter 4: Device Diagrams
FFVD1760 Package�XCZU17EG and XCZU19EG
X-Ref Target - Figure 4-65
V
V V
12
A
B1 1 234
C
D3 3 233
E
F1 1 233
G
H3 3 232
J
K1 1 232
L
M3 3 231
N
P1 1 231
R
T3 3 230
U
V1 1 230
W
Y3 3 229
AA
AB 1 1 229
AC
AD 3 3 228
AE
AF 1 1 228
AG
AH 3 3 227
AJ
AK 1 1 227
AL
AM 3 3 226
AN
AP 1 1 226
AR
AT 3 3 225
AU
AV 1 1 225
AW
AY 3 3 224
BA
BB
12
34
3 3
234
0 0
234
2 2
233
0 0
233
2 2
232
0 0
232
2 2
231
0 0
231
2 2
230
0 0
230
2 2
229
0 0
229
2 2
228
0 0
228
2 2
227
0 0
227
2 2
226
0 0
226
2 2
225
0 0
225
1 1
224
34
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
2 2
234
1
1
234
2
2
233
2
2
232
0
0
232
2
2
231
0
0
231
2
2
230
0
0
230
2
2
229
0
0
229
2
2
228
0
0
228
2
2
227
0
0
227
2
2
226
0
0
226
1
1
225
2
2
224
2 2
224
0 0
224
56
3
3
234
2
2
234
3
3
233
0
0
233
1
1
232
3
3
231
1
1
231
3
3
230
1
1
230
3
3
229
1
1
229
3
3
228
1
1
228
3
3
227
1
1
227
3
3
226
1
1
226
2
2
225
3
3
224
1
1
224
0
0
224
78
12 12 11 10 10 24 23 23 24 24 23 24 24 23 22 52 53
9 9 8 8 11 9V1CCO 24 22 22 21
22 23 21 21
23 22 20 54 55
7
6 6 20 20 7V1CCO 21 22 20 21 7V0CCO 21 19 19 20 6V9CCO 56 57
0
0
234
1
1
233
3
3
232
1 1
234
0 0
234
0 0
233
0 0
232
0 0
231
0 0
230
0 0
229
0 0
228
0 0
227
G
0 0
226
0 0
225
0 0
224
3
3
225
7 5 5 4 19 19 S 20 19 19 S S 18 18 58 59
3 3 4 9V1CCO S 18 18
S S 17 17
17 17 16 16 5V02CCO 60
2 1 1 17 7V1CCO 16 16 18 18 7V0CCO 16 16 15 15 6V9CCO 14 61 62
12 12 2 17 15 15 14 15 15 14 14 13 14 12 63 64
11 9V0CCO 10 10 13 13
14 13 13 12
11 13 11 12
65 66
11 9 9 7 7V1CCO 12 11 11 10 7V0CCO 12 11 9 11 6V9CCO 10 10 67 68
88
7 10 10 12 10 8 8 9
9 9 8 8 5V02CCO 69
66559
8777
S
77
S 70 71
4 9 S 9V0CCO
8
7665
6 6 72 73
1 1
233
4366
5544
5455
74 75
23
3442
3 3 1 4 3 2 2 76 77
1 1
232
1 1
231
21113
2
221
311
EO
1
PR ES
PG 5V03CCO
MD IN
1 1
230
SR DN MD
1 1
229
1 1
228
RC MD MD 5V03CCO CK MS
DI DO PI
1 1
PO
227
1 1
226
24
24 24 23 26 27 28 29 0 1
1 1
225
24 23 22 23 21 30 31 10 11
22 23 21 22 21 32 33 34
12 13
1 1
224
22 21
20 20 19 35 5V01CCO 36 14 15 16
20 20 S S 19
37 38 39 17 5V00CCO 18 19 2 20
S S 19 19 18 17 17 40 41
21 22 23 24 5V00CCO 25 3
17 18 18 6V6CCO 18 16 16 15 5V01CCO 42 43 4 5
6789
17
16 16 14 14 6V5CCO 15 44 45 46
P 19 24 30 5V04CCO PA BA
1 1
134
0 0
134
1 1
133
0 0
133
1 1
132
0 0
132
1 1
131
0 0
131
1 1
130
0 0
130
1 1
129
G
0 0
129
1 1
128
0 0
128
33 134
11 134
33 133
11 133
33 132
11 132
33 131
11 131
33 130
11 130
33 129
11 129
33 128
11 128
22 134
00 134
22 133
00 133
22 132
00 132
22 131
00 131
22 130
00 130
22 129
00 129
22 128
00 128
G
2 2
505
0 0
505
3 3
505
1 1
505
22 505
00 505
33 505
11 505
AL ZQ RS 32 33 34 36 47
3 3
134
1 1
134
3 3
133
1 1
133
3 3
132
1 1
132
3 3
131
1 1
131
3 3
130
1 1
130
3 3
129
1 1
129
3 3
128
1 1
128
2 2
505
0 0
505
46 60
A
B 2 2 134 C
D 0 0 134 E
F 2 2 133 G
H 0 0 133 J
K 2 2 132 L
M 0 0 132 N
P 2 2 131 R
T 0 0 131 U
V 2 2 130 W
Y 0 0 130 AA
2 2 AB 129 AC
0 0 AD 129 AE
2 2 AF 128 AG
0 0 AH 128 AJ
3 3 AK 505 AL
1 1 AM 505 AN
62 AP
61 63 AR
0
0
225
15 15 14 14 13 13 12 47
23 DM N 17
26 31 A A
13 13 6V6CCO 12 11 11 12
48 49 22 21
18 P
N
DM 5V04CCO
A
AC BG P N
DM 45 44 DM
P AT
A
A
A 5V04CCO 38 35
P
N
56 59 N AU
11 11
10 12 9 10 6V5CCO 9 9 50 51
20 6 16 27
28 CN A A
BA BG 39 37
DM 42 57 58
AV
8 8 10 7 9 10 8 8 7
67 5 4
25 29 12
C
5V04CCO
A
CE
A
OD 5V04CCO 71 40 41 43
50 48 AW
S
7 6 6V6CCO 6 S
7 5 6 DM
P 9 DM 13
CN OD A A
CS 67 70 69
52 P DM 49 AY
5
2 4 4 1 4 6V5CCO 4 3 5
32N8
P 14 C
A
5V04CCO
A
CS
CE
DM 5V04CCO
P
N 55 N
51 BA
5233
1223
111 0
10 11 N 15
AAAA
64 65 66 68
54 53
BB
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Bank 65 Bank 66 Bank 69 Bank 70 Bank 71 Bank 90 Bank 91 Quad 128
Quad 129 Quad 130 Quad 131 Quad 132 Quad 133 Quad 134 Quad 224 Quad 225
Quad 226 Quad 227 Quad 228 Quad 229 Quad 230 Quad 231 Quad 232 Quad 233
Quad 234 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-65: FFVD1760 Package--XCZU17EG and XCZU19EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
185
X-Ref Target - Figure 4-66
Chapter 4: Device Diagrams
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
E
V
A
B
E
B
C
E
V
C
D
V
E
D
E
V
E
V
E
F
V
E
F
G
V
V
E
V
G
H
V
V
H
J
V
E
E
V
J
K
V
V
K
L
V
E
E
V
L
M
V
V
M
N
V
E
E
V
N
P
V
E
V
P
V
R
V
E
V
R
T
V
E
V
T
V
V
U
V
V
U
V
V
V
V
V
V
W
V
E
V
W
Y
V
E
V
Y
V
AA
V
E
24 21
V
AA
AB
V
E
22 23
V
AB
AC
V
E
87
V
AC
AD
V
E
E
AD
V V
AE
V
L P PL BT
E
V
AE
AF
V
L P PL AD AD AU
E
AF
AG
V
13 15
L P PL DP DP AU
E
V
AG
AH
V
E
33
L P
F P AU AU
E
AH
AJ
V
E
34
F P F P F P AD AD
AJ
AK
V
E
FP FP
D D
V
AK
AL
V
E
FP DD DD
E
AL
AM
V
35
E
V
AM
AN
V
E
E
V
AN
AP
V
AP
AR
V
V
AR
AT
V
AT
AU
V
AU
AV
V
AV
AW
AW
AY
V
38
AY
BA
BA
BB
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
V
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-66: FFVD1760 Package--XCZU17EG and XCZU19EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
186
Chapter 4: Device Diagrams
FFVF1760 and FSVF1760 Packages�XCZU29DR and XCZU39DR
X-Ref Target - Figure 4-67
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
CC
228
230
B
CC
C
CC
229
231
DSS C C 228
E
F33 231
G
22 231
H1 1 231
J
00 231
K33 230
L
22 230
M1 1 230
N
00 230
P33 229
R
22 229
T11 229
U
00 229
V33 228
W
22 228
Y11 228
AA
00 228
AB
AC 3 3 227
AD
22 227
AE 1 1 227
AF
00 227
AG 3 3 226
AH
AJ 1 1 226
AK
22 226
00 226
VV 227
VV 226
AL 3 3 225
AM
22 225
AN 1 1 225
AP
00 225
AR 3 3 224
AT
22 224
AU 1 1 224
AV
00 224
AW AY
CC
225
227
CC
BA
CC
224
226
BB
CC
12 12 5 5 11 11 22 24 23 23 24 24 23 23 20 22 24 24 23 28 26
11 10 4 4 8 8V7CCO 8 22 24
21 21 22 22
21 19 20 22
21 21 23 29 27
9 11 10 3 7 7 10 20 20 S 19 18 20 21 19 S 17 19 19 35 30
9 8 8V9CCO 2 2 3
10 16 18 18 6V9CCO 19 16 18 20
17 18 S 17
34 33 31 32
7 7 8 1 6 8V7CCO 9 9 16
S 17 17 16 6V8CCO S S 17 18 6V7CCO 15 13 36 37
66
1 12 12 6
12 14 14 15
12 14 14 15
16 16 15 13 5V01CCO 40
00
4 8V9CCO 5 5 10
12 12 12 10 6V9CCO 13 15 12 10
15 13 14 14
11 43 38
131
3 3 4 8V8CCO 10 11 11 8
10 9 13 11 6V8CCO 10 11 11 13 6V7CCO 12 12 11 42
2 2 9 9 8 8V8CCO 8 8 9
11 8 S 9
8 10 10 9 5V01CCO 46 39
1 1
131
11
6 6 7 7 S 6V9CCO 7 7 8
968S
9 44 49 41
55
46
5 6V8CCO
7 7 6 6V7CCO
7 7 45
47
0 0
131
32146
5366
4355
50 51 48
321
4333
5543
54 56 53 DN 5V03CCO
2
4
1
24
1 52 55
IN PG
2
1112
4 2 2 1 5V02CCO 57 58 SR PR
1 1
130
0 0
130
61 63 59
CK
1 1
129
R
60
64 DI RC
62 66 65 DO
67 69 5V02CCO MS
PI
0 0
129
33 131
22 131
11 131
33 130
11 130
33 129
11 129
33 128
11 128
G
3 3
131
1 1
131
3 3
130
22 130
00 130
22 129
00 129
22 128
00 128
68 74 MD PO
70 73 77
MD
71
76 MD MD
72 75 EO ES 5V03CCO
1 1
128
3 3
505
1 1
505
0 0
128
2 2
505
3 3
128
1 1
128
33
505
R
0 0
22
505
505
11
505
VV 225
22 24 24 23
24
G 0 0 505
1 1
505
VV 224
24
20 22
23 19 23 24 22
24 23 23 20
19 21 21 19 6V6CCO 23 21 22
38 P 36 33 32 43
20 22 18 18 19 S
S 17 20 21 5V00CCO 22 24
20
22 21 S 16 6V5CCO 17 17 S 17
20 16 23 25
39 37 N
34 41 44 DM
16 18 BA PA
BG DM 35 40
P
18 S 21 19
16 15 13 13 6V6CCO 15 18 18 16
21 DM 19 17
A A AC BG
BA 62 63
12 12 11 18 S 6V4CCO 19 14 14 15
11 13 15 14 6V6CCO 12 20 18 P
28 31 30 A
A A A DM
10 11 9
16 17 17 15 6V5CCO 12 12 11 13
14 10 12 19 5V00CCO 22
N
29 DM 5V04CCO OD
AL
ZQ
RS 5V04CCO 57 56
10 8V4CCO 9 12 16 14
15 8 10 10 6V5CCO 9 11 11 10
15 17 23 21
P N A CS
A 53 51 P
7 8 8 12 6V4CCO 14 13 13 8
9997
8 13 14 16
20 24 25 26 5V04CCO C
A
A
54 5V04CCO N
675
8 10 11 11 6V4CCO 4 6
S
7 6 8 10 5V00CCO 12 3 2 0
27 15 CN CE
55 52 DM
6 5 8V4CCO S 8 10
9946
7
S6
9 8 11 4
1 12 14 13 5V04CCO A
A
CE 70 5V04CCO
344
6677
3575
446 7
DM P N DM
P CN C A
DM P
32
3355
2235
5332
1456
8 11 N
A
5V04CCO
A
CS 64 66
21111
4422
1111
22 0 3
7 5 9 10
A OD A A
65
A
B C 2
2 131
D E 0
0 131
F G 2
2 130
H J 1
1 130
K L 0
0 130
M N 3
3 129
P R 2
2 129
T U 1
1 129
V W 0
0 129
Y 2 2 AA
128
AB 0 0 AC
128
AD 3 3 AE
505
AF 2 2 AG
505
AH 0 0 AJ
505
AK
42 47 AL
N 46 AM
61 45 AN P 60 AP
N 59 AR
58 AT
50 48 AU
49 AV 69 71 AW
N 67 AY
68 BA
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 69 Bank 84 Bank 87
Bank 88 Bank 89 Quad 128 Quad 129 Quad 130 Quad 131 Bank 224 Bank 225
Bank 226 Bank 227 Bank 228 Bank 229 Bank 230 Bank 231 PS Bank 500 PS Bank 501
PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP VREF
ADC/DAC Pins
# ADC_VIN_#_P # ADC_VIN_#_N C ADC_CLK_P C ADC_CLK_N R ADC_REXT V VCM01 V VCM23 # DAC_VOUT_#_P # DAC_VOUT_#_N C DAC_CLK_P C DAC_CLK_N R DAC_REXT S SYSREF_P S SYSREF_N
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
MGTAVTTRCAL G MGTRREF
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-67: FFVF1760 and FSVF1760 Packages--XCZU29DR and XCZU39DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
187
Chapter 4: Device Diagrams
X-Ref Target - Figure 4-68
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
DAC
DAC
DAC DAC
A
B DAC DAC
DAC
DAC DAC
V
B
C DAC DAC DAC
DAC
DAC
C
D
DAC
DAC
DAC
V
D
E DAC DAC DAC DAC DAC DAC DAC
E
F
DAC
DAC DAC
V
F
G DAC DAC DAC DAC DAC DAC DAC
E
G
H
DAC
DAC DAC
V
H
J DAC DAC DAC DAC DAC DAC DAC
E
V
J
K
DAC
DAC DAC DAC DAC
E
K
L DAC DAC DAC DAC DAC DAC DAC DAC DAC
E
V
L
M
DAC
DAC DAC DAC DAC DAC DAC DAC
E
M
N DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC
V
N
P
DAC
DAC
DAC AUX
DAC AUX
DAC AUX
DAC AUX
DAC
DAC
VCC AMS
R DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC AUX
DAC AUX
DAC AUX
DAC
DAC SUB
T
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
VCC AMS
U DAC
DAC
DAC
DAC
DAC
DAC
DAC VTT
DAC VTT
DAC VCC
DAC VCC
DAC
V
DAC
DAC
DAC VTT
DAC VTT
DAC
DAC VCC
DAC VCC
DAC
VCC AMS
W DAC
DAC
DAC
DAC
DAC
DAC
DAC VTT
DAC VTT
DAC
DAC VCC
DAC VCC
DAC
Y
DAC
DAC
DAC VTT
DAC VTT
DAC
DAC VCC
DAC VCC
DAC
VCC AMS
AA DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC
24 21
E
P
V
R
E
T
E
V
U
V
E
W
Y
AA
AB ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
VCC AMS
AC
ADC
ADC
ADC AUX
ADC AUX
ADC
ADC VCC
ADC VCC
ADC
AD ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC AUX
ADC
ADC VCC
ADC VCC
ADC
VCC AMS
AE
ADC
ADC
ADC AUX
ADC AUX
ADC
ADC VCC
ADC VCC
ADC
AF ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC AUX
ADC VCC
ADC VCC
ADC
VCC AMS
AG
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC SUB
AH ADC ADC ADC ADC ADC ADC
ADC
ADC
VCC AMS
AJ
ADC
ADC
ADC
ADC
13 15
22 23 87
35 34 33
E
AU AU
AU AU
BT AD AD PL
E
F P DP DP AD
PL
FP LP
AD PL PL
E
FP LP LP LP
FP FP FP
LP LP
V V
V
AB AC AD AE AF AG AH AJ
AK ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
VCC AMS
AL
ADC
ADC ADC ADC ADC ADC ADC
F P
DD DD DD DD
DD DD
D D
AK AL
AM ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC
AM
AN
ADC
ADC ADC ADC
AN
AP ADC ADC ADC ADC ADC ADC ADC ADC
AP
AR
ADC
ADC ADC ADC
AR
AT ADC ADC ADC ADC ADC ADC ADC ADC
AT
AU
ADC
ADC ADC
AU
AV ADC ADC ADC ADC ADC ADC ADC
38
AV
AW ADC ADC ADC
ADC
ADC
AW
AY ADC ADC ADC
ADC
ADC
AY
BA ADC ADC
ADC
ADC ADC
BA
BB
ADC
ADC
ADC ADC
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Power Pins
Dedicated Pins Multi-Function I/O Pins PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
VCC AMS
VCCINT_AMS
ADC VCC
ADC_AVCC
ADC AUX
ADC_AVCCAUX
ADC ADC_GND
ADC SUB
ADC_SUB_GND
DAC VCC
DAC_AVCC
DAC AUX
DAC_AVCCAUX
DAC VTT
DAC_AVTT
DAC DAC_GND
DAC SUB
DAC_SUB_GND
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-68: FFVF1760 and FSVF1760 Packages--XCZU29DR and XCZU39DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
188
Chapter 4: Device Diagrams
FFVF1760 and FSVF1760 Packages�XCZU49DR
X-Ref Target - Figure 4-69
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
C
C
228
230
B
C
C
C
C
C
DS S 228
229 C
231 C
E
F3 3 231
G
22 231
H1 1 231
J
00 231
K3 3 230
L
22 230
M1 1 230
N
00 230
P3 3 229
R
22 229
T1 1 229
U
00 229
V3 3 228
W
22 228
Y1 1 228
AA
00 228
AB
AC 3 3 227
AD
22 227
AE 1 1 227
AF
00 227
AG 3 3 226
AH
AJ 1 1 226
AK
22 226
00 226
VV 227
VV 226
AL 3 3 225
AM
22 225
AN 1 1 225
AP
00 225
AR 3 3 224
AT
22 224
AU 1 1 224
AV
00 224
AW AY
C 225
C
C 227
C
BA
C
C
224
226
BB
C
C
12 12
5
11 10 4
5 11 11
22 24 23 23
24 24 23
4
8V7CCO
8
8 22 24
21 21 22 22
9 11 10
37
9
8V9CCO
8
2
2
3
7
7
8
1
8V7CCO
6
7 10
20 20 S 19
18 20
10 16 18 18 6V9CCO 19 16 18 20
9 9 16
S 17 17 16 6V8CCO S
66
8V9CCO
4
33
1 12 12 6
12 14 14 15
12 14 14
5 5 10
12 12 12 10 6V9CCO 13 15 12 10
4 8V8CCO 10 11 11 8
10 9 13 11 6V8CCO 10 11
2
2
9
9
8V8CCO
8
8
8
9
11 8 S 9
11
6
6
7
7 6V9CCO S
7
7
8
9
55
46
5
6V8CCO
77
32146
5366
321
4333
55
2
4
1
24
2
1112
4
R
R
VV 225
VV 224
22 24 24 23
24
24
20 22
23 19 23 24
24 23 23 20
19 21 21 19 6V6CCO 23
20 22
18 18 19 S
S 17 20
20
22 21 S 16 6V5CCO 17 17 S 17
18 S 21 19
16 15 13 13 6V6CCO 15 18
12 12 11 18 S 6V4CCO 19 14 14 15
11 13 15 14
10 11 9
16 17 17 15 6V5CCO 12 12 11 13
14
10 8V4CCO 9 12 16 14
15 8 10 10 6V5CCO 9 11 11
7
8
8 12 6V4CCO 14 13 13 8
9997
675
8 10 11 11 6V4CCO 4
6
S
76
6
8V4CCO
5
S
8 10
9946
7
S6
344
6677
3575
4
32
3355
2235
533
21111
4422
1111
23
20 22 24 24
23 28
21 19 20 22
21 21 23 29
21 19
S 17 19 19
35
17 18 S 17
34 33 31
S 17 18 6V7CCO 15 13 36 37
15
16 16 15 13 5V01CCO 40
15 13 14 14
11 43 38
11 13 6V7CCO 12 12 11 42
8 10 10 9 5V01CCO 46 39
68S
9 44 49 41
6
6V7CCO
7 7 45
47
4355
50 51 48
43
54 56 53 DN 5V03CCO
1 52 55
IN PG
2
2
1 5V02CCO 57 58
SR
PR
61 63 59
CK
60
64 DI RC
62 66 65 DO
67 69 5V02CCO MS
PI
68 74 MD PO
70 73 77
MD
71
76 MD MD
72 75
EO
ES
5V03CCO
22
21 22
21 5V00CCO 22 24
39
26
33
131
27
30
22
131
32
00 131
1 1
131
0 0
131
1 1
130
0 0
130
1 1
129
0 0
129
11 131
33 130
11 130
33 129
11 129
33 128
11 128
G
3 3
131
1 1
131
3 3
130
22 130
00 130
22 129
00 129
22 128
00 128
1 1
128
3 3
505
1 1
505
0 0
128
2 2
505
0 0
505
33 505
11 505
00
G
505
3 3
128
1 1
128
22 505
1 1
505
38 P 36 33 32 43
37 N
34 41 44 DM
A
B
C 2 2 131 D
E 0 0 131 F
G 2 2 130 H
J 1 1 130 K
L 0 0 130 M
N 3 3 129 P
R 2 2 129 T
U 1 1 129 V
W 0 0 129 Y
2 2 AA 128 AB
0 0 AC 128 AD
3 3 AE 505 AF
2 2
505
AG AH
0 0 AJ 505 AK
42 47 AL
20 16 23 25
16 18 BA PA
BG DM 35 40
P N 46 AM
18 16
21 DM 19 17
A
A AC BG
BA 62 63 61 45 AN
6V6CCO 12 20 18
P
28 31 30 A
A
A
A DM
P 60 AP
10 12 19 5V00CCO 22
N
29
DM
5V04CCO
OD
AL
ZQ
RS 5V04CCO 57 56
N
59 AR
10
15 17 23 21
P
N
A CS
A 53 51 P
58 AT
8 13 14 16
20 24 25 26 5V04CCO C
A
AU A
54 5V04CCO
N
50 48
8
10 5V00CCO 12
3
2
0
27 15 CN CE
55 52 DM 49
AV
9 8 11 4
1 12 14 13 5V04CCO A
A
AW CE 70 5V04CCO 69 71
467
DM P
N DM
P CN C
A
DM P N 67 AY
2
1456
8 11 N
A
5V04CCO
A
CS 64 66 68
BA
2203
7 5 9 10
A OD A
A
65
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 69 Bank 84 Bank 87
Bank 88 Bank 89 Dual 128 Dual 129 Dual 130 Dual 131 Bank 224 Bank 225
Bank 226 Bank 227 Bank 228 Bank 229 Bank 230 Bank 231 PS Bank 500 PS Bank 501
PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP VREF
ADC/DAC Pins
# ADC_VIN_#_P # ADC_VIN_#_N C ADC_CLK_P C ADC_CLK_N R ADC_REXT V VCM01 V VCM23 # DAC_VOUT_#_P # DAC_VOUT_#_N C DAC_CLK_P C DAC_CLK_N R DAC_REXT S SYSREF_P S SYSREF_N
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
MGTAVTTRCAL G MGTRREF
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-69: FFVF1760 and FSVF1760 Packages--XCZU49DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
189
X-Ref Target - Figure 4-70
Chapter 4: Device Diagrams
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
DAC
DAC
DAC DAC
A
B DAC DAC
DAC
DAC DAC
V
B
C DAC DAC DAC
DAC
DAC
C
D
DAC
DAC
DAC
V
D
E DAC DAC DAC DAC DAC DAC DAC
E
F
DAC
DAC DAC
V
F
G DAC DAC DAC DAC DAC DAC DAC
E
G
H
DAC
DAC DAC
V
H
J DAC DAC DAC DAC DAC DAC DAC
E
V
J
K
DAC
DAC DAC DAC DAC
E
K
L DAC DAC DAC DAC DAC DAC DAC DAC DAC
E
V
L
M
DAC
DAC DAC DAC DAC DAC DAC DAC
E
M
N DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC
V
N
P
DAC
DAC
DAC AUX
DAC AUX
DAC AUX
DAC AUX
DAC
DAC
VCC AMS
R DAC
DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC AUX
DAC AUX
DAC AUX
DAC
DAC SUB
T
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
VCC AMS
U DAC
DAC
DAC
DAC
DAC
DAC
DAC VTT
DAC VTT
DAC VCC
DAC VCC
DAC
V
DAC
DAC
DAC VTT
DAC VTT
DAC
DAC VCC
DAC VCC
DAC
VCC AMS
W DAC
DAC
DAC
DAC
DAC
DAC
DAC VTT
DAC VTT
DAC
DAC VCC
DAC VCC
DAC
Y
DAC
DAC
DAC VTT
DAC VTT
DAC
DAC VCC
DAC VCC
DAC
VCC AMS
AA DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC
24 21
E
P
V
R
E
T
E
V
U
V
E
W
Y
AA
AB ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
VCC AMS
AC
ADC
ADC
ADC AUX
ADC AUX
ADC
ADC VCC
ADC VCC
ADC
AD ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC AUX
ADC
ADC VCC
ADC VCC
ADC
VCC AMS
AE
ADC
ADC
ADC AUX
ADC AUX
ADC
ADC VCC
ADC VCC
ADC
AF ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC AUX
ADC VCC
ADC VCC
ADC
VCC AMS
AG
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC SUB
AH ADC ADC ADC ADC ADC ADC
ADC
ADC
VCC AMS
AJ
ADC
ADC
ADC
ADC
13 15
22 23 87
35 34 33
E
AU AU
AU AU
BT AD AD PL
E
F P DP DP AD
PL
FP LP
AD PL
E
FP LP LP LP
FP FP FP
LP LP
V V
V
AB AC AD AE AF AG AH AJ
AK ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
VCC AMS
AL
ADC
ADC ADC ADC ADC ADC ADC
F P
DD DD DD DD
DD DD
D D
AK AL
AM ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC
AM
AN
ADC
ADC ADC ADC
AN
AP ADC ADC ADC ADC ADC ADC ADC ADC
AP
AR
ADC
ADC ADC ADC
AR
AT ADC ADC ADC ADC ADC ADC ADC ADC
AT
AU
ADC
ADC ADC
AU
AV ADC ADC ADC ADC ADC ADC ADC
38
AV
AW ADC ADC ADC
ADC
ADC
AW
AY ADC ADC ADC
ADC
ADC
AY
BA ADC ADC
ADC
ADC ADC
BA
BB
ADC
ADC
ADC ADC
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Power Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC r RSVD R RSVDGND E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
VCC AMS
VCCINT_AMS
ADC VCC
ADC_AVCC
ADC AUX
ADC_AVCCAUX
ADC ADC_GND
ADC SUB
ADC_SUB_GND
DAC VCC
DAC_AVCC
DAC AUX
DAC_AVCCAUX
DAC VTT
DAC_AVTT
DAC DAC_GND
DAC SUB
DAC_SUB_GND
n NC
Dedicated Pins
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
Multi-Function I/O Pins PS Pins
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-70: FFVF1760 and FSVF1760 Packages--XCZU49DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
190
Chapter 4: Device Diagrams
FFVH1760 and FSVH1760 Packages�XCZU46DR
X-Ref Target - Figure 4-71
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A B C D E F G H J K0 0
230
L M N2 2
229
P R T3 3
228
U V W1 1
228
Y AA AB AC AD 1 1
227
AE AF AG 1 1
226
AH AJ AK 2 2
225
AL AM AN 3 3
224
AP AR AT AU AV AW AY BA BB
22 231
00 231
22 230
33 229
11 229
00 229
22 228
00 228
33 227
33 226
33 225
11 225
00 225
22 224
11 224
00 224
12 12
11 11 9 9
22 24 23 23
24 24 23 23
20 22 24 24
23 28 26
33
A
9V1CCO
8
10 10
5
7 7 22 24
21 19 22 22
21 19 20 22
21 21 23 29
131
3 3
B
131
SS 228
668
5331
S 17 21 19
18 20 21 19
S 17 19 19
27 30
9V1CCO
4
4
2
2
1 20 20 17 7V0CCO 16 S 18 20
18 18 S 17
34 33 31 32
10
12 12 18 18
15 15 16 S 7V1CCO 17 17 14 16 6V9CCO 15 13 35 36
10 11 11 8
9
9
9V0CCO
8
16 16 S 13
14 15 15 14
16 12 15 13 5V01CCO 37
12 14 14 7V0CCO 13 12 14 13
8 10 10 12
9 40 38
1 1
131
67
65
9V0CCO
4
4
7 12
9 11 11 12 7V1CCO 13 11 8
S 6V9CCO 11 9 42 43
10 10 9 7
10 10 11 9
6
11 7 5V01CCO 46 39
5
8
8 7V0CCO S
7
8
S
9463
7 44 49 41
3
65
8
7V1CCO
7
5
5
4
6V9CCO
3
5
5 45
47
0 0
131
1 1
130
22 131
11 131
33 130
11 130
00 130
1 1
131
00 131
22 130
1 1
130
C 2 2 131 D
E 0 0 131 F
G 3 3 130 H
J 2 2 130 K
L 0 0 130
23465
6
74
214
3363
4
211
50 51 48
2
77 75 73 72 5V02CCO
0 0
130
33 129
3 3
129
M N 2
2 129
1
2
1
3
2
76 74
71 70
1 1
22
P
129
129
2
1112
66 67 68 69
11 129
R 1 1 129
65 64
63
0 0
00
T
129
129
R
60 61 62
33
U 0 0
59 58 57 5V02CCO
128
1 1
3 3
129
V
128
128
54
55 56
22 128
W 2 2 128
53 52 ES EO
0 0
128
1 1
Y
128
PG SR
DN
5V03CCO
IN
CK
DI
G
MD
RC
DO 5V03CCO
11 128
00 128
0 0 AA 128 AB
3 3 AC 505
MD
MS PI PO
3 3
505
33 505
AD
MD MD
2 2
505
2 2 AE 505
R
PR
1 1
22
AF
505
505
11 505
1 1 AG 505
VV 227
24 24
0
0G
505
00 505
AH
VV 226
24
22
20
23
0 0 AJ 505
VV 225
VV 224
24 23 23 22
20 23 21 24
P 36 33 32 43 44
AK
21 21 6V5CCO 18 S S 21
23 24 22 22
39 37 N
34 41 42 DM 47 46 AL
22 19 18 16 6V4CCO 19 19 23 21
20 22 24 25
16
PA 38
DM BG 35 40
P N 45 AM
22 19 17
16 14 17 17 6V6CCO 21 18 20 23
21 19 18 BA
A
A AC BG
BA 62 63 61
AN
20 6V5CCO 17 12 12 14
15 19 19 18
20 18 19 DM
17 31 30 A
A A A 56
P 60 AP
18 18
20 15 15 10 6V4CCO 13 15 S S
16 16 17 16 5V00CCO P
N
29 28 5V04CCO OD
AL
ZQ
RS 5V04CCO 57
DM
N
59 AR
S 16 S 13 13
10 11 13 13 6V6CCO 17 17 14 14
15 14 23 22
P
N
A CS
A 53 51 P
58 AT
12 16 14 6V5CCO 11 11 8 11
13 15 15 12 6V6CCO 10 13 12 11
21 25 DM 26 5V04CCO C
A
AU A
54 5V04CCO
N
50 48
12
14 9
9
8
6V4CCO
9
9 11 11
12 8 10 10 5V00CCO 9
3 20 24
27 15 CN CE
55 52 DM 49
AV
8 10 10 7 7
6
S7
7998
8762
0
12
14
DM
5V04CCO
C
A
AW A
70 5V04CCO 69 71
86 46
S
3465
7 5 7S
6654
P N 1 13
P CN CE A
DM P N 67 AY
5534
5335
442
3 2 DM 6
8 11 N
A
5V04CCO
A
CS 64 66 68
BA
42211
2211
3311
2104
7 5 9 10
A OD A
A
65
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Bank 64 Bank 65 Bank 66 Bank 69 Bank 70 Bank 71 Bank 90 Bank 91
Dual 128 Dual 129 Dual 130 Dual 131 Bank 224 Bank 225 Bank 226 Bank 227
Bank 228 Bank 229 Bank 230 Bank 231 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503
PS Bank 504 PS Quad 505
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP VREF
ADC/DAC Pins
# ADC_VIN_#_P # ADC_VIN_#_N C ADC_CLK_P C ADC_CLK_N R ADC_REXT V VCM01 V VCM23 # DAC_VOUT_#_P # DAC_VOUT_#_N C DAC_CLK_P C DAC_CLK_N R DAC_REXT S SYSREF_P S SYSREF_N
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
MGTAVTTRCAL G MGTRREF
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-71: FFVH1760 and FSVH1760 Packages--XCZU49DR I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
191
X-Ref Target - Figure 4-72
Chapter 4: Device Diagrams
V
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
DAC DAC DAC DAC DAC DAC
A
B DAC DAC DAC DAC DAC DAC DAC
B
C DAC DAC DAC DAC DAC DAC DAC
C
D DAC DAC DAC DAC DAC DAC DAC
E
D
E DAC DAC DAC DAC DAC DAC DAC DAC
E
F DAC DAC DAC
DAC DAC DAC DAC DAC
E
F
G DAC DAC DAC DAC DAC DAC
DAC DAC
E
V
G
H DAC DAC DAC
DAC DAC DAC DAC DAC
V
H
J DAC DAC DAC DAC DAC DAC
DAC DAC DAC
E
J
K
DAC
DAC DAC DAC DAC DAC DAC
V
K
L DAC DAC DAC DAC DAC DAC
DAC
DAC AUX
DAC
M DAC DAC DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC
DAC
N
DAC DAC DAC DAC
DAC
DAC AUX
DAC AUX
DAC
VCC AMS
P DAC DAC DAC
DAC
DAC
DAC
DAC
DAC AUX
DAC AUX
DAC
VCC AMS
R DAC DAC DAC DAC DAC DAC
DAC
DAC AUX
DAC AUX
DAC SUB
T
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
VCC AMS
U DAC
DAC
DAC
DAC
DAC
DAC
DAC VTT
DAC VTT
DAC VCC
DAC VCC
DAC
VCC AMS
V DAC DAC DAC
DAC
DAC VTT
DAC VTT
DAC
DAC VCC
DAC VCC
DAC
W
DAC
DAC
DAC
DAC
DAC VTT
DAC VTT
DAC
DAC VCC
DAC VCC
DAC
VCC AMS
Y DAC DAC DAC
DAC
DAC VTT
DAC VTT
DAC
DAC VCC
DAC VCC
DAC
VCC AMS
AA DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC
AB ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
VCC AMS
AC ADC ADC ADC
ADC
ADC AUX
ADC AUX
ADC
ADC VCC
ADC VCC
ADC
VCC AMS
AD
ADC
ADC
ADC
ADC
ADC AUX
ADC AUX
ADC
ADC VCC
ADC VCC
ADC
AE ADC ADC ADC
ADC
ADC AUX
ADC AUX
ADC
ADC VCC
ADC VCC
ADC
VCC AMS
AF ADC
ADC
ADC
ADC
ADC
ADC
ADC AUX
ADC AUX
ADC VCC
ADC VCC
ADC
VCC AMS
AG
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC SUB
AH ADC ADC ADC ADC ADC ADC
ADC
ADC
VCC AMS
13 15
AJ ADC ADC ADC
ADC ADC ADC ADC
ADC
VCC AMS
34
AK
ADC ADC ADC ADC
ADC
ADC
35
33
AL ADC ADC ADC
ADC ADC ADC ADC
ADC
24 21 22 23 87
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
VCC FEC
E V
V V
V E
V E
V
E
DP DP
E
V
PL
AD AD
V
BT PL
PL AD AD AU
E
V
LP LP
F P
AU
LP LP LP
F P AU AU
L P
FP FP FP DD
FP FP FP DD
D D
L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL
AM ADC ADC ADC ADC ADC ADC
ADC ADC ADC ADC
D D
AM
AN
ADC
ADC ADC ADC ADC ADC ADC ADC
AN
AP ADC ADC ADC ADC ADC ADC
ADC
AP
AR ADC ADC ADC
ADC ADC ADC ADC
AR
AT ADC ADC ADC ADC ADC ADC
ADC
AT
AU ADC ADC ADC
ADC ADC ADC ADC
AU
AV ADC ADC ADC ADC ADC ADC ADC ADC
AV
AW ADC ADC ADC ADC ADC ADC ADC
AW
AY ADC ADC ADC ADC ADC ADC ADC
AY
BA ADC ADC ADC ADC ADC ADC ADC
38
BA
BB
ADC ADC ADC ADC ADC ADC
BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Power Pins
Dedicated Pins Multi-Function I/O Pins PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC r RSVD R RSVDGND E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
VCC FEC
VCCSDFEC
VCC AMS
VCCINT_AMS
ADC VCC
ADC_AVCC
ADC AUX
ADC_AVCCAUX
ADC ADC_GND
ADC SUB
ADC_SUB_GND
DAC VCC
DAC_AVCC
DAC AUX
DAC_AVCCAUX
DAC VTT
DAC_AVTT
DAC DAC_GND
DAC SUB
DAC_SUB_GND
n NC
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-72: FFVH1760 and FSVH1760 Packages--XCZU49DR Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
192
Chapter 4: Device Diagrams
FFVE1924 Package�XCZU17EG and XCZU19EG
X-Ref Target - Figure 4-73
12
A
B
C1 1 234
D
E3 3 233
F
G1 1 233
H
J3 3 232
K
L1 1 232
M
N3 3 231
P
R1 1 231
T
U3 3 230
V
W1 1 230
Y
AA 3 3 229
AB
AC 1 1 229
AD
AE 3 3 228
AF
AG 1 1 228
AH
AJ 3 3 227
AK
AL 1 1 227
AM
AN 3 3 226
AP
AR 1 1 226
AT
AU 3 3 225
AV
AW 1 1 225
AY
BA 0 0 225
BB
BC
BD
12
34
3 3
234
0 0
234
2 2
233
0 0
233
2 2
232
0 0
232
2 2
231
0 0
231
2 2
230
0 0
230
2 2
229
0 0
229
2 2
228
0 0
228
2 2
227
0 0
227
2 2
226
0 0
226
2 2
225
3 3
224
1 1
224
0 0
224
34
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
3
2 2
234
3
3
234
1
1
234
3
3
233
1
1
233
2
2
232
0
0
232
0
0
231
1
1
230
2
2
229
3
3
228
0
0
228
1
1
227
2
2
226
0
0
226
2
2
225
0
0
225
2
2
224
0
0
224
2 2
224
1
34 2 2 1
2
2
234
0
0
234
2
2
233
0
0
233
1
1
232
2
2
231
3
3
230
0
0
230
1
1
229
2
2
228
3
3
227
0
0
227
1
1
226
3
3
225
1
1
225
3
3
224
1
1
224
9 9
33
4 6 12 12 12 12 10 10 22 22 24 23 23 24 24 24 23 23 17 17 18 24 23 23 22 17 S
A
5 6 8 11 9V4CCO 11 11 9 9 9V3CCO 21 21 23 24
21 24 22 22
21 21 19 15
18 24 21 21
22 17 24 S
B
5 9V4CCO 8 11 8 8
7 7 20 20 19 23 19 21 22 22 20 20 19 15 16 16 19 19 20 16 24 23 23 C
177
6655
17 S S 19
19 S 20 20 7V2CCO S S 18 18
14 14 S S
20 16 15 22 21 21 D
9 9 10 4 9V3CCO 2 2 1 17 7V3CCO 16 18 18 S 7V4CCO 18 18 17 17
16 16 13 13 7V1CCO 11 12 12 14
15 22 20 20
E
10 4 3 3
1 15 15 16 14 17 17 15 15 15 14 14 10 10 9 11 12 14 13 13 19 18 18 F
1 1
234
1 1
233
1 1
232
3
3
232
3
3
231
1
1
231
2
2
230
3
3
229
0 0
234
0 0
233
0 0
232
1 1
231
0 0
231
1 1
230
0 0
230
1 1
229
12 12 11 11
11 13 13 14
14 15 16 13 7V2CCO 11 12 12 7
9 8 8 12 7V0CCO 11 11 10 19
24 G
9 9V1CCO 10 10 10 11 7V3CCO 12 12 14 13 7V4CCO 16 13 11 9
10 7 S
8 7V1CCO 8 9 9
10 23 23 24 H
988
10 9 9 8
11 13 12 12
7 9 8 10 7V1CCO 6 6 6 6
S 7 7 20 22 22 J
57766
7 8 9 11
10 10 S 7 8 7V2CCO 4 4 3
455
7V0CCO 19 20 21 21
K
53
4 4 S 7 9 7V3CCO 8 8 7 5 7V4CCO
66
3 5 5 4 7V0CCO 3 12 12 19
S 18 18 L
1 3 2 2 3 9V1CCO
66
57S5
4422
1 2 2 3 11 14 14 S 17 M
1 9V0CCO 12 12 11 3
5553
6
33
11
1
9 9 11 13 15 16 16 17 N
9 10 10 11 1 4 4
1326
221
5
8 8 6V9CCO 10 13 15 9
55P
98877122
1
244
1 3 3 5 S 6V9CCO 7 7 10
12 9 S 4
R
6 6 5 9V0CCO 5
1 4 6V9CCO 4 6 6
15 13 13 12
42T
4433
122
19 18 18 15 6V8CCO 11 8 8 6
2U
122
22 22 19 6V8CCO 17 17 14 11
7631V
1
24 23 6V8CCO 21 21 16 16
14 10 10 7
3 1W
24 23 20 20
S S 13 13 6V7CCO 9 S
6
Y
22 22 S S 6V7CCO 14 12 12 9
5 6 4 AA
23 23 6V7CCO 20 18 18 14
11 8 8 5
4 AB
0
0
229
24 21 21 20 16 16 15 11 7 3 3 2 AC
1
1
228
2
2
227
0 0
229
1 1
228
24 CK MD EO ES 28
19 19 17 17
15 10 10 7
1 2 AD
PR MD MD 5V03CCO 30 29 31 26 5V01CCO 33 32 52 53
55 58 60 1
AE
PG MD MS DI 27 5V01CCO 40 39 37 34
54 56 57 61 5V02CCO 66 67 69 AF
AG SR RC 5V03CCO PI 47 46 50 5V01CCO 35 38 36 59 5V02CCO 63 62 64 65 5V02CCO 68
0 0
228
DN IN DO PO
48 51 45 44 42 41 70 71 72 75 73 77 74 76 AH
3
3
226
43 49
AJ
1 1
227
24 24 24
19
3 3
505
G 33 505
3 3 AK 505
0 0
227
G 24 24 21 23 23 24 23 23 21 13
2 2
505
22 505
2 2
AL
505
1 1
226
23 23 22 21 22 22 22 22 18 15
1 1
505
11 505
1 1 AM 505
0 0
226
0 0
225
0 0
224
1 1
225
21 22 19 19 20 20 21 21 23
21 20 19 6V5CCO 18 20 S 20
19 19 14
6V6CCO 20 19 17 18
S 18 18 S 5V00CCO 16 20 22 20
0 0
505
00 505
29 30 31 ZQ
38 36 32 33
0 0
505
AN
AP
47 46 62 63
AR
1 1
224
SS
17 15 15 16 6V4CCO 15 S 17 17
23 21 P 28
DM RS AL 37
P 34 45 44
60 61 P AT
18 16 16 13 6V5CCO 14 16 16 15
17 25 22 DM
N P N 26
BG 39 DM N
P N DM DM
N AU
17 17 18 6V6CCO 15 13 12 14
16 14 14 13 5V00CCO 24 19 17 16
25 27
A
BA 5V04CCO PA BA 35 43
42 57 56 59 AV
12 12 6V6CCO 14 13 13 15
12 11 12 12 6V4CCO 11 13 1 12
18 0 14 24 5V04CCO A BG A
A 5V04CCO 40 41 53 52
48 58 AW
10 11 11 14
9 9 10 11 6V5CCO 10 10 9 11
4 10 3 2
13 15 A A
AC
A
CE OD 5V04CCO 54 DM
P
50
AY
8 10 7 7 7 7 10 8 8 8
9 7 7 3 5V00CCO 11 1 P 12
DM A A C
A CS 67 55
N 51 49 BA
866S
55
S
S 8 5 5 1 6V4CCO 2 7 8
N
P
N
11 5V04CCO A
A CN OD
66 DM 70 71
BB
2
5
33
662
6331
6 9 DM 7
8 10 A
A
5V04CCO
C
A
CE 65 5V04CCO 68 69
BC
1
2445
1144
2226
440 5
6549
A A A CN
CS 64 P N
BD
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Bank 64 Bank 65 Bank 66 Bank 67 Bank 68 Bank 69 Bank 70 Bank 71
Bank 72 Bank 73 Bank 74 Bank 90 Bank 91 Bank 93 Bank 94 Quad 224
Quad 225 Quad 226 Quad 227 Quad 228 Quad 229 Quad 230 Quad 231 Quad 232
Quad 233 Quad 234 PS Bank 500 PS Bank 501 PS Bank 502 PS Bank 503 PS Bank 504 PS Quad 505
V V
SelectIO Pins
# IO_L#P # IO_L#N S IO (single-ended) # IO_L#P_GC # IO_L#N_GC
VRP
Dedicated Pins
VREF MGTAVTTRCAL G MGTRREF
Transceiver Pins
PS Pins
# MGT[R, H or Y]RXP# # MGT[R, H or Y]RXN# # MGT[R, H or Y]TXP# # MGT[R, H or Y]TXN# # MGTREFCLK#P # MGTREFCLK#N
# PS_MIO # PS_DDR_DQ P PS_DDR_DQS_P N PS_DDR_DQS_N AL PS_DDR_ALERT_N AC PS_DDR_ACT_N A PS_DDR_A BA PS_DDR_BA BG PS_DDR_BG CN PS_DDR_CK_N C PS_DDR_CK CE PS_DDR_CKE CS PS_DDR_CS DM PS_DDR_DM OD PS_DDR_ODT PA PS_DDR_PARITY RS PS_DDR_RAM_RST_N ZQ PS_DDR_ZQ
DN PS_DONE EO PS_ERROR_OUT ES PS_ERROR_STATUS IN PS_INIT_B CK PS_JTAG_TCK DI PS_JTAG_TDI DO PS_JTAG_TDO MS PS_JTAG_TMS MD PS_MODE PI PS_PADI PO PS_PADO PR PS_POR_B PG PS_PROG_B RC PS_REF_CLK SR PS_SRST_B
Figure 4-73: FFVE1924 Package--XCZU17EG and XCZU19EG I/O Bank Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
193
X-Ref Target - Figure 4-74
Chapter 4: Device Diagrams
V
V V V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A
A
B
B
C
C
D
D
E
E
F
V
F
G
V
G
H
V
E
H
J
V
E
J
K
V
E
K
L
V
E
L
M
V
E
M
N
V
E
N
P
V
V
P
R
V
E
R
T
V
V
T
U
V
E
U
V
V
V
V
W
V
W
Y
V
V
Y
AA
V
AA
AB
V
V
24 21
AB
AC
V
22 23
AC
AD
V
V
87
AD
AE
V
AE
AF
V
V
AF
AG
V
E
AG
AH
V
V
AH
AJ
V
E
PL
PL DP AU AU
AJ
AK
V
E
13 15
F P PL DP
AD AU
AK
AL
V
34 33
F P BT AD AU AD
E
V
AL
AM
V
E
FP FP
L P AD L P
E
AM
AN
V
E
FP LP FP LP
L P
V
AN
AP
V
E
35
F P
DD DD DD LP
AP
AR
V
E
AR
AT
V
E
AT
AU
V
AU
AV
V
AV
AW
AW
AY
AY
BA
BA
BB
38
BB
BC
BC
BD
BD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Power Pins
Dedicated Pins
Multi-Function I/O Pins
PS Pins
GND VCCAUX_IO VCCAUX VCCINT VCCINT_IO VCCINT_VCU VCCO_[bank number] VCCBRAM VCCADC GNDADC R RSVDGND n NC E MGTAVCC_[R or L] V MGTAVTT_[R or L] MGTVCCAUX_[R or L]
7 DXP 8 DXN 13 POR_OVERRIDE 15 PUDC_B 21 VP 22 VN 23 VREFP 24 VREFN
33 I2C_SCLK 34 I2C_SDA & PERSTN1 35 PERSTN0 38 SMBALERT
AD VCC_PSADC AD GND_PSADC AU VCC_PSAUX E PS_MGTRAVCC V PS_MGTRAVTT BT VCC_PSBATT DP VCC_PSDDR_PLL PL VCC_PSPLL F P VCC_PSINTFP D D VCC_PSINTFP_DDR L P VCC_PSINTLP
Figure 4-74: FFVE1924 Package--XCZU17EG and XCZU19EG Power, Dedicated, and Multi-function Pin Diagram
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
194
Chapter 5
Mechanical Drawings
Summary
This chapter provides mechanical drawings (package specifications) of the Zynq� UltraScale+TM devices. Table 5-1 and Table 5-2 cross-reference to the mechanical drawings by device and package combination. See Package Specifications Designations in Chapter 3 for definitions of Evaluation Only, Engineering Sample, and Production mechanical drawings.
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q. For the mechanical drawings, refer to the Pb-free version of these packages.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
195
Chapter 5: Mechanical Drawings
Table 5-1: Cross-Reference to Zynq UltraScale+ MPSoC Mechanical Drawings by Package
Device
Package
SBVA484
XCZU2CG XCZU2EG XAZU2EG
XCZU3CG XCZU3EG XAZU3EG XQZU3EG
XCZU4CG XCZU4EG XCZU4EV XAZU4EV
XCZU5CG XCZU5EG XCZU5EV
XAZU5EV XQZU5EV
Figure 5-1
Production
XCZU6CG XCZU6EG
XCZU7CG XCZU7EG XCZU7EV XAZU7EV XQZU7EV
XCZU9CG XCZU9EG
XCZU11EG XAZU11EG
XCZU15EG XQZU15EG
XCZU17EG
XCZU19EG
SFRA484
Figure 5-2 Production
SFVA625 SFRC784 SFVC784
Figure 5-3 Production
Figure 5-4 Production
Figure 5-5 Production
Figure 5-4 Production
FBVB900 FFRB900 FFRC900 FFVC900
Figure 5-6 Production
Figure 5-9 Production
Figure 5-10 Production
Figure 5-7 Production
Figure 5-8 Production
Figure 5-9 Production
Figure 5-10 Production
Figure 5-9 Production
Figure 5-10 Production
FFRB1156
Figure 5-11 Production
Figure 5-11 Production
FFVB1156
Figure 5-12 Production
Figure 5-12 Production
Figure 5-12 Production
Zynq UltraScale+ Packaging and Pinouts
196
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 5: Mechanical Drawings
Table 5-1: Cross-Reference to Zynq UltraScale+ MPSoC Mechanical Drawings by Package (Cont'd)
Device
Package
FFRC1156 FFVC1156
XCZU2CG XCZU2EG XAZU2EG
XCZU3CG XCZU3EG XAZU3EG XQZU3EG
XCZU4CG XCZU4EG
XCZU4EV XAZU4EV
XCZU5CG XCZU5EG XCZU5EV XAZU5EV XQZU5EV
XCZU6CG XCZU6EG
XCZU7CG XCZU7EG XCZU7EV XAZU7EV XQZU7EV
Figure 5-13 Production
Figure 5-14 Production
XCZU9CG XCZU9EG
XCZU11EG XAZU11EG
XCZU15EG XQZU15EG
XCZU17EG
XCZU19EG
Figure 5-13 Production
Figure 5-14 Production
FFRB1517
Figure 5-19 Production
FFVB1517 FFVF1517
Figure 5-20 Production
Figure 5-20 Production
Figure 5-20 Production
Figure 5-20 Production
FFRC1760
Figure 5-25 Production
Figure 5-25 Production
FFVC1760
Figure 5-24 Production
Figure 5-24 Production
FFVD1760
Figure 5-24 Production
FFVE1924
Figure 5-29 Production
Zynq UltraScale+ Packaging and Pinouts
197
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 5: Mechanical Drawings
Table 5-2: Cross-Reference to Zynq UltraScale+ RFSoC Mechanical Drawings by Package
Package
FFRD1156
Device
XCZU21DR XCZU25DR XCZU27DR XCZU28DR XCZU29DR XCZU39DR XCZU43DR XCZU46DR XCZU47DR XCZU48DR XCZU49DR
Figure 5-15 Production
FFVD1156
Figure 5-17 Production
FFRE1156
Figure 5-16 Production
FFVE1156
Figure 5-17 Figure 5-17 Figure 5-17 Production Production Production
Figure 5-17 Production
Figure 5-17 Figure 5-17 Production Production
FSVE1156 FFRG1517
Figure 5-18 Figure 5-18 Figure 5-18 Production Production Production
Figure 5-21 Production
Figure 5-18 Production
Figure 5-18 Figure 5-18 Production Production
FFVG1517
Figure 5-22 Figure 5-22 Figure 5-22 Production Production Production
Figure 5-22 Production
Figure 5-22 Figure 5-22 Production Production
FSVG1517
Figure 5-23 Figure 5-23 Figure 5-23 Production Production Production
Figure 5-23 Production
Figure 5-23 Figure 5-23 Production Production
FFRF1760
Figure 5-27 Production
FFVF1760 FSVF1760
Figure 5-26 Figure 5-26 Production Production
Figure 5-28 Figure 5-28 Production Production
Figure 5-26 Production
Figure 5-28 Production
Zynq UltraScale+ Packaging and Pinouts
198
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 5: Mechanical Drawings
Table 5-2: Cross-Reference to Zynq UltraScale+ RFSoC Mechanical Drawings by Package (Cont'd)
Package
FFVH1760
Device
XCZU21DR XCZU25DR XCZU27DR XCZU28DR XCZU29DR XCZU39DR XCZU43DR XCZU46DR XCZU47DR XCZU48DR XCZU49DR
Figure 5-26 Production
FSVH1760
Figure 5-28 Production
Zynq UltraScale+ Packaging and Pinouts
199
UG1075 (v1.9) June 24, 2020
www.xilinx.com
Chapter 5: Mechanical Drawings
SBVA484 Flip-Chip, Fine-Pitch BGA (XCZU2, XCZU3, XAZU2EG, and XAZU3EG)
X-Ref Target - Figure 5-1
ug1075_c5_112918
Figure 5-1: Package Dimensions for SBVA484 (XCZU2, XCZU3, XAZU2EG, and XAZU3EG)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
200
Chapter 5: Mechanical Drawings
SFRA484 Flip-Chip, Fine-Pitch BGA (XQZU3EG)
X-Ref Target - Figure 5-2
Figure 5-2: Package Dimensions for SFRA484 (XQZU3EG)
ug1085_c5_061419
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
201
Chapter 5: Mechanical Drawings
SFVA625 Flip-Chip, Fine-Pitch BGA (XCZU2, XCZU3, XAZU2EG, and XAZU3EG)
X-Ref Target - Figure 5-3
ug1075_c5_073116
Figure 5-3: Package Dimensions for SFVA625 (XCZU2, XCZU3, XAZU2EG, and XAZU3EG)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
202
Chapter 5: Mechanical Drawings
SFRC784 Ruggedized Flip-Chip BGA (XQZU3EG and XQZU5EV)
X-Ref Target - Figure 5-4
ug1075_c5_121918
Figure 5-4: Package Dimensions for SFRC784 (XQZU3EG and XQZU5EV)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
203
Chapter 5: Mechanical Drawings
SFVC784 Flip-Chip, Fine-Pitch BGA (XCZU2, XAZU2EG, XCZU3, XAZU3EG, XCZU4, XAZU4EV, XCZU5, and XAZU5EV)
X-Ref Target - Figure 5-5
ug1075_c5_073117
Figure 5-5: Package Dimensions for SFVC784 (XCZU2, XAZU2EG, XCZU3, XAZU3EG, XCZU4, XAZU4EV, XCZU5, and XAZU5EV)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
204
Chapter 5: Mechanical Drawings
FBVB900 Flip-Chip, Fine-Pitch BGA (XCZU4CG, XCZU4EG, XCZU4EV, XCZU5CG, XCZU5EG, and XCZU5EV)
X-Ref Target - Figure 5-6
Figure 5-6: Package Dimensions for FBVB900 (XCZU4CG, XCZU4EG, XCZU4EV, XCZU5CG, XCZU5EG, and XCZU5EV)
ug1075_c5_120717
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
205
Chapter 5: Mechanical Drawings
FBVB900 Flip-Chip, Fine-Pitch BGA (XCZU7CG, XCZU7EG, XCZU7EV, and XAZU7EV)
X-Ref Target - Figure 5-7
ug1075_c5_073117
Figure 5-7: Package Dimensions for FBVB900 (XCZU7CG, XCZU7EG, XCZU7EV, and XAZU7EV)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
206
Chapter 5: Mechanical Drawings
FFRB900 (XQZU7EV) Ruggedized Flip-Chip BGA
X-Ref Target - Figure 5-8
Figure 5-8: Package Dimensions for FFRB900 (XQZU7EV)
ug1075_c5_080818
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
207
Chapter 5: Mechanical Drawings
FFRB900 (XQZU5EV) and FFRC900 (XQZU9EG and XQZU15EG) Ruggedized Flip-Chip BGA
X-Ref Target - Figure 5-9
ug1075_c5_100318
Figure 5-9: Package Dimensions for FFRB900 (XQZU5EV) and FFRC900 (XQZU9EG and XQZU15EG)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
208
Chapter 5: Mechanical Drawings
FFVC900 Flip-Chip, Fine-Pitch BGA (XCZU6CG, XCZU6EG, XCZU9CG, XCZU9EG, and XCZU15EG)
X-Ref Target - Figure 5-10
ug1075_c5_073116
Figure 5-10: Package Dimensions for FFVC900 (XCZU6CG, XCZU6EG, XCZU9CG, XCZU9EG, and XCZU15EG)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
209
Chapter 5: Mechanical Drawings
FFRB1156 Ruggedized Flip-Chip BGA (XQZU9EG and XQZU15EG)
X-Ref Target - Figure 5-11
ug1075_c5_100318
Figure 5-11: Package Dimensions for FFRB1156 (XQZU9EG and XQZU15EG)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
210
Chapter 5: Mechanical Drawings
FFVB1156 Flip-Chip, Fine-Pitch BGA (XCZU6CG, XCZU6EG, XCZU9CG, XCZU9EG, and XCZU15EG)
X-Ref Target - Figure 5-12
ug1075_c5_073116
Figure 5-12: Package Dimensions for FFVB1156 (XCZU6CG, XCZU6EG, XCZU9CG, XCZU9EG, and XCZU15EG)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
211
Chapter 5: Mechanical Drawings
FFRC1156 Ruggedized Flip-Chip BGA (XQZU7EV and XQZU11EG)
X-Ref Target - Figure 5-13
ug1075_c5_100318
Figure 5-13: Package Dimensions for FFRC1156 (XQZU7EV and XQZU11EG)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
212
Chapter 5: Mechanical Drawings
FFVC1156 Flip-Chip, Fine-Pitch BGA (XCZU7CG, XCZU7EG, XCZU7EV, and XCZU11EG)
X-Ref Target - Figure 5-14
ug1075_c5_073116
Figure 5-14: Package Dimensions for FFVC1156 (XCZU7CG, XCZU7EG, XCZU7EV, and XCZU11EG)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
213
Chapter 5: Mechanical Drawings
FFRD1156 (XQZU21DR) Ruggedized Flip-Chip BGA
X-Ref Target - Figure 5-15
Figure 5-15: Package Dimensions for FFRD1156 (XQZU21DR)
ug1085_c5_061419
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
214
Chapter 5: Mechanical Drawings
FFRE1156 (XQZU28DR) Ruggedized Flip-Chip BGA
X-Ref Target - Figure 5-16
Figure 5-16: Package Dimensions for FFRE1156 (XQZU28DR)
ug1085_c5_061419
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
215
Chapter 5: Mechanical Drawings
FFVD1156 (XCZU21DR) and FFVE1156 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 5-17
ug1075_ffvd1156_ffve1156_030518
Figure 5-17: Package Dimensions for FFVD1156 (XCZU21DR) and FFVE1156 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
216
Chapter 5: Mechanical Drawings
FSVE1156 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring BGA
X-Ref Target - Figure 5-18
ug1075_fsve1156_040120
Figure 5-18: Package Dimensions for FSVE1156 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
217
Chapter 5: Mechanical Drawings
FFRB1517 (XQZU19EG) Ruggedized Flip-Chip BGA
X-Ref Target - Figure 5-19
Figure 5-19: Package Dimensions for FFRB1517 (XQZU19EG)
ug1085_c5_061419
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
218
Chapter 5: Mechanical Drawings
FFVB1517 (XCZU11EG, XCZU17EG, and XCZU19EG) and FFVF1517 (XCZU7CG, XCZU7EG, XCZU7EV, XCZU11EG, and XAZU11EG) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 5-20
ug1075_c5_073117
Figure 5-20: Package Dimensions for FFVB1517 (XCZU11EG, XCZU17EG, and XCZU19EG) and FFVF1517 (XCZU7CG, XCZU7EG, XCZU7EV, XCZU11EG, and XAZU11EG)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
219
Chapter 5: Mechanical Drawings
FFRG1517 (XQZU28DR) Ruggedized Flip-Chip BGA
X-Ref Target - Figure 5-21
Figure 5-21: Package Dimensions for FFRG1517 (XQZU28DR)
ug1085_c5_061419
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
220
Chapter 5: Mechanical Drawings
FFVG1517 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 5-22
ug1075_ffvg1517_040120
Figure 5-22: Package Dimensions for FFVG1517 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
221
Chapter 5: Mechanical Drawings
FSVG1517 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring BGA
X-Ref Target - Figure 5-23
ug1075_fsvg1517_040120
Figure 5-23: Package Dimensions for FSVG1517 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
222
Chapter 5: Mechanical Drawings
FFVC1760 and FFVD1760 Flip-Chip, Fine-Pitch BGA (XCZU11EG, XCZU17EG, and XCZU19EG)
X-Ref Target - Figure 5-24
ug1075_c5_073116
Figure 5-24: Package Dimensions for FFVC1760 and FFVD1760 (XCZU11EG, XCZU17EG, and XCZU19EG)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
223
Chapter 5: Mechanical Drawings
FFRC1760 Ruggedized Flip-Chip BGA (XQZU11EG and XQZU19EG)
X-Ref Target - Figure 5-25
ug1085_c5_061419
Figure 5-25: Package Dimensions for FFRC1760 (XQZU11EG and XQZU19EG)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
224
Chapter 5: Mechanical Drawings
FFVF1760 (XCZU29DR, XCZU39DR, XCZU49DR) and FFVH1760 (XCZU46DR) Flip-Chip, Fine-Pitch BGA
X-Ref Target - Figure 5-26
ug1075_c5_040120
Figure 5-26: Package Dimensions for FFVF1760 (XCZU29DR, XCZU39DR, XCZU49DR) and FFVH1760 (XCZU46DR)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
225
Chapter 5: Mechanical Drawings
FFRF1760 (XQZU29DR) Ruggedized Flip-Chip BGA
X-Ref Target - Figure 5-27
ug1085_c5_061419
Figure 5-27: Package Dimensions for FFRF1760 (XQZU29DR)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
226
Chapter 5: Mechanical Drawings
FSVF1760 (XCZU29DR, XCZU39DR, XCZU49DR) and FSVH1760 (XCZU46DR) Flip-Chip, Fine-Pitch, Lidless with Stiffener Ring BGA
X-Ref Target - Figure 5-28
ug1075_c5_040120
Figure 5-28: Package Dimensions for FSVF1760 (XCZU29DR, XCZU39DR, XCZU49DR) and FSVH1760 (XCZU46DR)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
227
Chapter 5: Mechanical Drawings
FFVE1924 Flip-Chip, Fine-Pitch BGA (XCZU17EG, and XCZU19EG)
X-Ref Target - Figure 5-29
ug1075_c5_073117
Figure 5-29: Package Dimensions for FFVE1924 (XCZU17EG and XCZU19EG)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
228
Chapter 6
Package Marking
Introduction
The package top-markings for the XC and XA Zynq� UltraScale+TM devices are similar to the examples shown in Figure 6-1 and Figure 6-2. In addition to the markings explained in Table 6-1, refer to the FAQ: Top Marking Change for 7 Series, UltraScale, and UltraScale+ Products (XTP424) [Ref 17] and (XTP544) [Ref 18]. The package top-markings for the XQ Zynq UltraScale+ devices are as shown in Figure 6-3. On XQ products only the Xilinx logo and the 2D bar code are marked.
X-Ref Target - Figure 6-1
ug1075_c6_032920
Figure 6-1: XC and XA Zynq UltraScale+ Devices Package Marking
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
229
X-Ref Target - Figure 6-2
Chapter 6: Package Marking
Device Type Package
Mask Code 2D Bar Code
Device Type Package
Speed Grade Operating Range
Country of Origin
XILINX�
ZYNQ� UltraScale +TM
XCZU9EGTM
FFVB1156xxxXXXX DxxxxxxA 1E ES9839
Date Code Lot Code Engineering Sample
ug1075_ch6_01_121517
Figure 6-2: XC and XA Zynq UltraScale+ Devices Package Marking
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
230
X-Ref Target - Figure 6-3
Chapter 6: Package Marking
ug1075_c6_121918
Figure 6-3: XQ Zynq UltraScale+ Devices Package Marking
Table 6-1: XC and XA Device Marking Definition--Example
Item
Definition
Xilinx Logo Xilinx logo, Xilinx name with trademark, and trademark-registered status.
Family
Device family name with trademark and trademark-registered status. This line is optional and could
Brand Logo appear blank.
1st Line
Device name. This line is not marked on some devices. Refer to the bar code for more information.
2nd Line
This line is not marked on some devices. Refer to the bar code for more information. � Package code: FF
1st digit: F for flip-chip BGA, S for flip-chip BGA with 0.8 mm ball pitch. 2nd digit: F for lidded, B for bare-die. � 3rd digit: Pb-free code: V for RoHS 6/6, R or Q for packages with eutectic BGA balls. All Zynq UltraScale+ devices are available with Pb-free RoHS compliant packaging. For more details on Xilinx Pb-free and RoHS compliant products, see: www.xilinx.com/pbfree. � 4th digit: This is the pin out (net list) identifier. � 5th�8th digits: These are the physical pin count identifiers: B1156 is shown in the Figure 6-2 example marking drawing. Example: A package code of FFVB1517 and FFVF1517 means they have a different pinout (net list) but the same physical ball count and physical dimensions. � Three letter circuit design revision, the location code for the wafer fab, and the geometry code (xxx). � When marked, the date code: YYWW. This code is not marked on some devices. Refer to the bar code for more information.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
231
Chapter 6: Package Marking
Table 6-1: XC and XA Device Marking Definition--Example (Cont'd)
Item
3rd Line
Definition
When marked, this line describes ten alphanumeric characters for assembly location, 7-digit lot number, and step information. The last digit is usually an A or an M if a stepping version does not exist. This line is not marked on some devices. Refer to the bar code for more information.
4th Line
When marked, this line describes the device speed grade (1) and temperature operating range (E). When not marked on the package, the product is considered to operate at the extended (E) temperature range. If a bar code is present on the device, the 4th line might be blank or unmarked. In this case, refer to the bar code for speed grade and temperature range information. For more information on the ordering codes, see the Zynq UltraScale+ MPSoC Overview (DS891) [Ref 1]. Other variations for the 4th line:
L1I
The L1I indicates a -1LI device. The -1LI speed grade offers reduced maximum power
consumption. For more information, see the Zynq UltraScale+ MPSoC data sheet
[Ref 8].
1E xxxx 1E ES 2I ES L1I ES
The xxxx indicates a 4-digit SCD device option. An SCD is a special ordering code that is not always marked in the device top mark. The addition of an ES after the operating temperature range code indicates an engineering sample.
Bar Code
A device-specific bar code is marked on each device. Refer to the FAQ: Top Marking Change for 7 Series, UltraScale, and UltraScale+ Products (XTP424) [Ref 17].
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
232
Chapter 7
Packing and Shipping
Introduction
Zynq� UltraScale+TM devices are packed in trays. Trays are used to pack most of Xilinx surface-mount devices since they provide excellent protection from mechanical damage. In addition, they are manufactured using antistatic material to provide limited protection against ESD damage and can withstand a bake temperature of 125�C.
Table 7-1: Standard Device Counts per Tray and Box
Package
SBVA484, SFRA484
Maximum Number of Maximum Number of Devices Per Tray Units In One Internal Box
84
420
SFVA625
60
300
SFVC784, SFRC784
60
300
FBVB900, FFVC900, FFRB900, FFRC900
27
135
FFVB1156, FFRB1156, FFVC1156, FFRC1156 FFVD1156, FFRD1156, FFVE1156, FFRE1156
24
120
FSVE1156
24
72
FFVB1517, FFRB1517, FFVF1517
21
105
FFVG1517, FFRG1517
21
63
FSVG1517
21
63
FFVC1760, FFRC1760 FFVD1760, FFVF1760, FFVH1760, FFRF1760
12
60
FSVF1760, FSVH1760
12
36
FFVE1924
12
36
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q (for example: FFQE1156).
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
233
Chapter 8
Soldering Guidelines
Soldering Guidelines
To implement and control the production of surface-mount assemblies, the dynamics of the solder reflow process and how each element of the process is related to the end result must be thoroughly understood.
RECOMMENDED: Xilinx recommends that customers qualify their custom PCB assembly processes using package samples.
The primary phases of the reflow process are:
� Melting the particles in the solder paste � Wetting the surfaces to be joined � Solidifying the solder into a strong metallurgical bond
The peak reflow temperature of a surface-mount component body should not be more than 250�C maximum (260�C for dry rework only) for Pb-free packages and 220�C for eutectic packages, and is package size dependent. For multiple BGAs in a single board and because of surrounding component differences, Xilinx recommends checking all BGA sites for varying temperatures.
The infrared reflow (IR) process is strongly dependent on equipment and loading. Components might overheat due to lack of thermal constraints. Unbalanced loading can lead to significant temperature variation on the board. These guidelines are intended to assist users in avoiding damage to the components; the actual profile should be determined by those using these guidelines. For complete information on package moisture / reflow classification and package reflow conditions, refer to the Joint IPC/JEDEC Standard J-STD-020C.
IMPORTANT: Following the initial reflow process, devices should not be reworked more than once. Any additional rework beyond that is likely to cause irreparable damage to the device.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
234
Chapter 8: Soldering Guidelines
Sn/Pb Reflow Soldering
Figure 8-1 shows typical conditions for solder reflow processing of Sn/Pb soldering using IR/convection. Both IR and convection furnaces are used for BGA assembly. The moisture sensitivity of surface-mount components must be verified prior to surface-mount flow.
X-Ref Target - Figure 8-1
Temperature (�C)
2�3�C/s
T = 183�C t183
Preheat & drying dwell 120�180 s between 95�180�C (Note 2)
<1�C/s
TMAX (body) = 220�C TMAX (leads) = 235�C Ramp down 1�3�C/s
60s < t183< 120s applies to lead area
Time (s)
ug1075_c7_02_111218
Figure 8-1: Typical Conditions for IR Reflow Soldering of Sn/Pb Solder
Notes for Figure 8-1:
1. Maximum temperature range = 220�C (body). Minimum temperature range before 205�C (leads/balls).
2. Preheat dwell 95�180�C for 120�180 seconds.
3. IR reflow must be performed on dry packages.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
235
Chapter 8: Soldering Guidelines
Pb-Free Reflow Soldering
Xilinx uses SnAgCu solder balls for commercial-grade (XC) and automotive-grade (XA) BGA packages. In addition, suitable package materials are qualified for the higher reflow temperatures (250�C maximum, 260�C for dry rework only) required by Pb-free soldering processes.
Xilinx does not support soldering SnAgCu BGA packages with SnPb solder paste using a Sn/Pb soldering process. Traditional Sn/Pb soldering processes have a peak reflow temperature of 220�C. At this temperature range, the SnAgCu BGA solder balls do not properly melt and wet to the soldering surfaces. As a result, reliability and assembly yields can be compromised.
The optimal profile must take into account the solder paste/flux used, the size of the board, the density of the components on the board, and the mix between large components and smaller, lighter components. Profiles should be established for all new board designs using thermocouples at multiple locations on the component. In addition, if there is a mixture of devices on the board, then the profile should be checked at various locations on the board. Ensure that the minimum reflow temperature is reached to reflow the larger components and at the same time, the temperature does not exceed the threshold temperature that might damage the smaller, heat sensitive components.
Table 8-1 and Figure 8-2 provide guidelines for profiling Pb-free solder reflow.
In general, a gradual, linear ramp into a spike has been shown by various sources to be the optimal reflow profile for Pb-free solders (Figure 8-2). This profile has been shown to yield better wetting and less thermal shock than conventional ramp-soak-spike profile for the Sn/Pb system. SnAgCu alloy reaches full liquidus temperature at 235�C. When profiling, identify the possible locations of the coldest solder joints and ensure that those solder joints reach a minimum peak temperature of 235�C for at least 10 seconds. Reflowing at high peak temperatures of 260�C and above can damage the heat sensitive components and cause the board to warp. Users should reference the latest IPC/JEDEC J-STD-020 standard for the allowable peak temperature on the component body. The allowable peak temperature on the component body is dependent on the size of the component. Refer to Table 8-1 for peak package reflow body temperature information. In any case, use a reflow profile with the lowest peak temperature possible.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
236
Chapter 8: Soldering Guidelines
Table 8-1: Pb-Free Reflow Soldering Guidelines
Profile Feature
Ramp-up rate
Preheat temperature 150��200�C Temperature maintained above 217�C
Convection, IR/Convection
2�C/s maximum. 1�C/s maximum for lidless packages with stiffener ring. 60�120 seconds. 60�150 seconds (60�90 seconds typical).
Time within 5�C of actual peak temperature 30 seconds maximum.
Peak temperature (lead/ball)
Peak temperature (body) Ramp-down rate
230�C--245�C typical (depends on solder paste, board size, component mixture). 240�C--250�C, package body size dependent. 2�C/s maximum.
Time 25�C to peak temperature
3.5 minutes minimum, 5.0 minutes typical, 8 minutes maximum.
X-Ref Target - Figure 8-2
Tbody (MAX) = 240�250�C (package type dependent) See data sheet for maximum value by package type Tlead (MIN) = 230�245�C (10s minimum)
Temperature (�C)
150�200�C
Preheating 60�120s
217�C
t 217 Wetting time = 60�150 s
Ramp down 2�C/s max
Ramp up 2�C/s maximum 1�C/s maximum for lidless packages with stiffener ring
Time (s)
ug1075_c7_01_022818
Figure 8-2: Typical Conditions for Pb-Free Reflow Soldering
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
237
Chapter 8: Soldering Guidelines
Peak Package Reflow Temperatures
Table 8-2: Peak Package Reflow Body Temperature (Based on J-STD-020 Standard)
Package
SBVA484 SFVA625 SFVC784
FBVB900, FFVC900 FFVB1156, FFVC1156 FFVD1156, FFVE1156 FFVB1517, FFVF1517, FFVG1517 FFVC1760, FFVD1760, FFVF1760, FFVH1760 FFVE1924
FSVE1156 FSVG1517 FSVF1760, FSVH1760
SFRA484, SFRC784 FFRB900, FFRC900 FFRB1156, FFRC1156 FFRD1156, FFRE1156 FFRB1517, FFRG1517 FFRC1760, FFRF1760
Product Category
XC XA
All
All
XQ(1)
Peak Package Reflow JEDEC Moisture Sensitivity
Body Temperature
Level (MSL)
Mass reflow: 250�C
4
Dry rework: 260�C
3
Mass reflow: 245�C Dry rework: 260�C
4
Mass reflow: 240�C Dry rework: 260�C
4
Mass reflow: 220�C Dry rework: 235�C
4
Notes: 1. For devices with the Pb-free signifier in the package name (labeled as Q vs. V) use the temperatures and MSL
listed for the XQ product category.
For sophisticated boards with a substantial mix of large and small components, it is critical to minimize the T across the board (<10�C) to minimize board warpage and thus, attain higher assembly yields. Minimizing the T is accomplished by using a slower rate in the warm-up and preheating stages. Xilinx recommends a heating rate of less than 1�C/s during the preheating and soaking stages, in combination with a heating rate of not more than 3�C/s throughout the rest of the profile.
It is also important to minimize the temperature gradient on the component, between top surface and bottom side, especially during the cooling down phase. The key is to optimize cooling while maintaining a minimal temperature differential between the top surface of the package and the solder joint area. The temperature differential between the top surface of the component and the solder balls should be maintained at less than 7�C during the critical region of the cooling phase of the reflow process. This critical region is in the part of the cooling phase where the balls are not completely solidified to the board yet, usually between the 200�C�217�C range. To efficiently cool the parts, divide the cooling section into multiple zones, with each zone operating at different temperatures.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
238
Chapter 8: Soldering Guidelines
Post Reflow/Cleaning/Washing
Many PCB assembly subcontractors use a no-clean process in which no post-assembly washing is required. Although a no-clean process is recommended, if cleaning is required, Xilinx recommends a water-soluble paste and a washer using a deionized-water. Baking after the water wash is recommended to prevent fluid accumulation.
Cleaning solutions or solvents are not recommended because some solutions contain chemicals that can compromise the lid adhesive, thermal compound, or components inside the package.
Conformal Coating
Xilinx does not have information regarding the reliability of flip-chip BGA packages on a board after exposure to any specific conformal coating process. Therefore, any process using conformal coating should be qualified for the specific use case to cover the materials and process steps.
Note: Ruggedized XQ packages are designed to support conformal coating, with vented lids that
ensure proper cleaning can occur after the etching process and prior to conformal coating.
IMPORTANT: When a conformal coating is required, Parylene-based material should be used to avoid potential risk of weakening the lid or stiffener ring adhesive used in Xilinx packages.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
239
Chapter 9
Recommended PCB Design Rules for BGA Packages
BGA Packages
Xilinx provides the diameter of a land pad on the package side. This information is required prior to the start of the board layout so the board pads can be designed to match the component-side land geometry. The typical values of these land pads are described in Figure 9-1 and summarized in Table 9-1 for 1.0 mm pitch packages. For Xilinx BGA packages, non-solder mask defined (NSMD) pads on the board are suggested to allow a clearance between the land metal (diameter L) and the solder mask opening (diameter M) as shown in Figure 9-1. An example of an NSMD PCB pad solder joint is shown in Figure 9-2. It is recommended to have the board land pad diameter with a 1:1 ratio to the package solder mask defined (SMD) pad for improved board level reliability. The space between the NSMD pad and the solder mask as well as the actual signal trace widths depend on the capability of the PCB vendor. The cost of the PCB is higher when the line width and spaces are smaller.
X-Ref Target - Figure 9-1
M L
Opening in Solder Mask (M)
Solder Land (L)
Solder Mask
e
UG1075_c8_01_101315
Figure 9-1: Suggested Board Layout of Soldered Pads for BGA Packages
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
240
Chapter 9: Recommended PCB Design Rules for BGA Packages
X-Ref Target - Figure 9-2
BGA Package
BGA Solder Ball Solder Mask
SMD L
Land Pad
PCB
M
UG1075_c8_02_101315
Figure 9-2: Example of an NSMD PCB Pad Solder Joint
Table 9-1: BGA Package Design Rules
Flip-Chip BGA Packages
Design Rule
Package land pad opening (SMD) Maximum PCB solder land (L) diameter Opening in PCB solder mask (M) diameter Solder ball land pitch (e)
Notes: 1. Controlling dimension in mm.
1.0 mm Pitch
0.8 mm Pitch
Dimensions in mm (mils)
0.53 mm (20.9 mils) 0.53 mm (20.9 mils) 0.63 mm (24.8 mils) 1.00 mm (39.4 mils)
0.40 mm (15.7 mils) 0.40 mm (15.7 mils) 0.50 mm (19.7 mils) 0.80 mm (31.5 mils)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
241
Chapter 10
Thermal Specifications
Introduction
Zynq� UltraScale+TM devices are offered exclusively in thermally efficient flip-chip BGA packages. These flip-chip packages range in pin-count from the smaller 19 x 19 mm SBVA484 to the 45 x 45 mm FFVE1924. This suite of packages is used to address the various power requirements of the Zynq UltraScale+ devices. Zynq UltraScale+ devices are implemented in the 16 nm process technology.
Unlike features in an ASIC, the combination of Zynq UltraScale+ device features used in a user application is not known to the component supplier. Therefore, it remains a challenge for Xilinx to predict the power requirements of a given Zynq UltraScale+ device when it leaves the factory. Accurate estimates are obtained when the board design takes shape. For this purpose, Xilinx offers and supports a suite of integrated device power analysis tools to help users quickly and accurately estimate their design power requirements. Zynq UltraScale+ devices are supported similarly to previous products. The uncertainty of design power requirements makes it difficult to apply canned thermal solutions to fit all users. Therefore, Xilinx devices do not come with preset thermal solutions. Your design's operating conditions dictate the appropriate solution.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
242
Chapter 10: Thermal Specifications
Thermal Resistance Data
Table 10-1 shows the thermal resistance data for Zynq UltraScale+ devices (grouped in the packages offered). The data includes junction-to-ambient in still air, junction-to-case, and junction-to-board data based on standard JEDEC four-layer measurements.
IMPORTANT: The data in Table 10-1 is for device/package comparison purposes only. Attempts to recreate this data are only valid using the transient 2-phase measurement techniques outlined in JESD51-14. Do not use these values for thermal simulations. Use the Package Thermal Models [Ref 22].
TIP: The thermal data query for all available devices by package is available on the Xilinx website: www.xilinx.com/cgi-bin/thermal/thermal.pl.
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q (for example: FFQE1156). Refer to the Pb-free version of these packages for their thermal resistance data and thermal models.
Table 10-1: Package
SBVA484 SFRA484 SFVA625
SFVC784
Thermal Resistance Data
Package Body Size
Devices
JB(1) (�C/W)
XCZU2
2.46
XCZU3
2.46
19 x 19
XAZU2EG
2.46
XAZU3EG
2.46
19 x 19 XQZU3EG
2.70
XCZU2
2.22
XCZU3
2.22
21 x 21
XAZU2EG
2.22
XAZU3EG
2.22
XCZU2
2.67
XCZU3
2.67
XCZU4
2.28
XCZU5
2.28
23 x 23
XAZU2EG
2.67
XAZU3EG
2.67
XAZU4EV
2.28
XAZU5EV
2.28
JC(1) (�C/W)
0.06 0.06 0.06 0.06 0.43 0.38 0.38 0.38 0.38 0.50 0.50 0.27 0.27 0.50 0.50 0.27 0.27
JA(1)
JA-Effective (�C/W)(2)
(�C/W) @250 LFM @500 LFM @750 LFM
14.9
11.5
9.6
8.9
14.9
11.5
9.6
8.9
14.9
11.5
9.6
8.9
14.9
11.5
9.6
8.9
15.3
11.7
9.8
9.1
13.2
9.9
8.3
7.8
13.2
9.9
8.3
7.8
13.2
9.9
8.3
7.8
13.2
9.9
8.3
7.8
12.8
9.2
7.8
7.2
12.8
9.2
7.8
7.2
12.2
8.9
7.4
7.0
12.2
8.9
7.4
7.0
12.8
9.2
7.8
7.2
12.8
9.2
7.8
7.2
12.2
8.9
7.4
7.0
12.2
8.9
7.4
7.0
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
243
Chapter 10: Thermal Specifications
Table 10-1: Package
SFRC784
FBVB900
FFRB900 FFVC900 FFRC900 FFVB1156 FFRB1156 FFVC1156 FFRC1156 FFVD1156 FFRD1156
FFVE1156
FFRE1156
Thermal Resistance Data (Cont'd)
Package Body Size
Devices
JB(1) JC(1) (�C/W) (�C/W)
XQZU3EG
2.44
0.42
23 x 23
XQZU5EV
2.26
0.27
XCZU4
2.62
0.04
31 x 31
XCZU5 XCZU7
2.62
0.04
2.32
0.03
XAZU7
2.32
0.03
XQZU5EV
2.26
0.27
31 x 31
XQZU7EV
2.14
0.19
XCZU6
2.33
0.25
31 x 31 XCZU9
2.33
0.25
XCZU15
2.25
0.18
XQZU9EG
2.10
0.18
31 x 31
XQZU15EG 2.07
0.17
XCZU6
2.40
0.20
35 x 35 XCZU9
2.40
0.20
XCZU15
2.09
0.23
XQZU9EG
2.09
0.18
35 x 35
XQZU15EG 2.06
0.17
35 x 35
XCZU7 XCZU11
2.39
0.21
2.20
0.16
XQZU7EV
2.12
0.19
35 x 35
XQZU11EG 2.01
0.15
35 x 35 XCZU21DR 1.94
0.16
35 x 35 XQZU21DR 1.94
0.16
XCZU25DR 1.94
0.16
XCZU27DR 1.94
0.16
XCZU28DR 1.94
0.16
35 x 35
XCZU43DR 1.94
0.16
XCZU47DR 1.94
0.16
XCZU48DR 1.94
0.16
35 x 35 XQZU28DR 1.93
0.11
JA(1)
JA-Effective (�C/W)(2)
(�C/W) @250 LFM @500 LFM @750 LFM
12.4
9.0
7.6
7.1
12.1
8.9
7.4
7.0
9.6
6.3
5.3
5.0
9.6
6.3
5.3
5.0
9.2
6.1
5.1
4.8
9.2
6.1
5.1
4.8
9.1
6.1
5.1
4.8
8.9
6.0
5.0
4.8
9.2
6.1
5.1
4.9
9.2
6.1
5.1
4.9
9.1
6.1
5.1
4.8
8.9
6.0
5.0
4.7
8.9
6.0
5.0
4.7
8.3
5.3
4.5
4.2
8.3
5.3
4.5
4.2
7.9
5.1
4.3
4.1
7.9
5.1
4.3
4.1
7.9
5.1
4.3
4.1
8.3
5.3
4.5
4.2
8.0
5.2
4.3
4.1
7.9
5.2
4.3
4.1
7.8
5.1
4.3
4.1
7.8
5.1
4.2
4.0
7.8
5.1
4.2
4.0
7.8
5.1
4.2
4.0
7.8
5.1
4.2
4.0
7.8
5.1
4.2
4.0
7.8
5.1
4.2
4.0
7.8
5.1
4.2
4.0
7.8
5.1
4.2
4.0
7.7
5.1
4.2
4.0
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
244
Chapter 10: Thermal Specifications
Table 10-1: Thermal Resistance Data (Cont'd)
Package
Package Body Size
Devices
JB(1) JC(1) (�C/W) (�C/W)
XCZU25DR 2.40
0.02
XCZU27DR 2.40
0.02
XCZU28DR 2.40
0.02
FSVE1156 35 x 35
XCZU43DR 2.40
0.02
XCZU47DR 2.40
0.02
XCZU48DR 2.40
0.02
XCZU11
2.22
0.16
FFVB1517 40 x 40 XCZU17
2.17
0.11
XCZU19
2.17
0.11
FFRB1517 40 x 40 XQZU19EG 1.90
0.11
XCZU7
2.38
0.21
FFVF1517 40 x 40 XCZU11
2.22
0.16
XAZU11
2.22
0.16
XCZU25DR 1.93
0.16
XCZU27DR 1.93
0.16
XCZU28DR 1.93
0.16
FFVG1517 40 x 40
XCZU43DR 1.93
0.16
XCZU47DR 1.93
0.16
XCZU48DR 1.93
0.16
FFRG1517 40 x 40 XQZU28DR 1.93
0.16
XCZU25DR 2.43
0.02
XCZU27DR 2.43
0.02
XCZU28DR 2.43
0.02
FSVG1517 40 x 40
XCZU43DR 2.43
0.02
XCZU47DR 2.43
0.02
XCZU48DR 2.43
0.02
XCZU11
1.96
0.14
FFVC1760 42.5 x 42.5 XCZU17
1.77
0.10
XCZU19
1.77
0.10
XQZU11EG 1.96
0.14
FFRC1760 42.5 x 42.5
XQZU19EG 1.77
0.10
XCZU17 FFVD1760 42.5 x 42.5
XCZU19
1.77
0.10
1.77
0.10
JA(1)
JA-Effective (�C/W)(2)
(�C/W) @250 LFM @500 LFM @750 LFM
8.3
5.3
4.4
4.2
8.3
5.3
4.4
4.2
8.3
5.3
4.4
4.2
8.3
5.3
4.4
4.2
8.3
5.3
4.4
4.2
8.3
5.3
4.4
4.2
7.1
4.4
3.7
3.5
7.0
4.4
3.7
3.5
7.0
4.4
3.7
3.5
6.8
4.3
3.5
3.4
7.3
4.5
3.8
3.6
7.1
4.4
3.7
3.5
7.1
4.4
3.7
3.5
6.8
4.3
3.6
3.4
6.8
4.3
3.6
3.4
6.8
4.3
3.6
3.4
6.8
4.3
3.6
3.4
6.8
4.3
3.6
3.4
6.8
4.3
3.6
3.4
6.8
4.3
3.6
3.4
7.3
4.5
3.8
3.6
7.3
4.5
3.8
3.6
7.3
4.5
3.8
3.6
7.3
4.5
3.8
3.6
7.3
4.5
3.8
3.6
7.3
4.5
3.8
3.6
6.4
4.0
3.3
3.2
6.3
3.9
3.2
3.1
6.3
3.9
3.2
3.1
6.4
4.0
3.3
3.2
6.3
3.9
3.2
3.1
6.3
3.9
3.2
3.1
6.3
3.9
3.2
3.1
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
245
Chapter 10: Thermal Specifications
Table 10-1: Thermal Resistance Data (Cont'd)
Package
Package Body Size
Devices
JB(1) JC(1) (�C/W) (�C/W)
XCZU29DR 2.04
0.17
FFVF1760 42.5 x 42.5 XCZU39DR 2.04
0.17
XCZU49DR 2.04
0.17
FFVH1760 42.5 x 42.5 XCZU46DR 2.04
0.17
FFRF1760 42.5 x 42.5 XQZU29DR 2.04
0.17
XCZU29DR 2.47
0.02
FSVF1760 42.5 x 42.5 XCZU39DR 2.47
0.02
XCZU49DR 2.47
0.02
FSVH1760 42.5 x 42.5 XCZU46DR 2.47
0.02
FFVE1924
45 x 45
XCZU17 XCZU19
1.77
0.10
1.77
0.10
JA(1)
JA-Effective (�C/W)(2)
(�C/W) @250 LFM @500 LFM @750 LFM
6.5
4.0
3.3
3.2
6.5
4.0
3.3
3.2
6.5
4.0
3.3
3.2
6.5
4.0
3.3
3.2
6.5
4.0
3.3
3.2
7.0
4.3
3.5
3.6
7.0
4.3
3.5
3.6
7.0
4.3
3.5
3.6
7.0
4.3
3.5
3.6
5.9
3.6
3.0
2.9
5.9
3.6
3.0
2.9
Notes: 1. This data is for device/package comparison purposes only. Attempts to recreate this data are only valid using the
transient 2-phase measurement techniques outlined in JESD51-14. Do not use these values for thermal simulations. Use the Package Thermal Models [Ref 22]. 2. All JA-Effective values assume no heat sink and include thermal dissipation through a standard JEDEC four-layer board. The Xilinx power estimation tools (Vivado� Power Analysis, and Xilinx Power Estimator), which require detailed board dimensions and layer counts, are useful for deriving more precise JA-Effective values.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
246
Chapter 10: Thermal Specifications
Support for Thermal Models
Table 10-1 provides the traditional thermal resistance data for Zynq UltraScale+ devices. These resistances are measured using a prescribed JEDEC standard that might not necessarily reflect your actual board conditions and environment. The quoted JA and JC numbers are environmentally dependent, and JEDEC has traditionally recommended that these be used with that awareness. For more accurate junction temperature prediction, these might not be enough, and a system-level thermal simulation might be required.
Though Xilinx continues to support these figures of merit data, for Zynq UltraScale+ devices, boundary conditions independent thermal resistor network (Delphi) models are offered for all Zynq UltraScale+ devices. These compact models seek to capture the thermal behavior of the packages more accurately at predetermined critical points (junction, case, top, leads, and so on) with the reduced set of nodes as illustrated in Figure 10-1.
Unlike a full 3D model, these are computationally efficient and work well in an integrated system simulation environment. Delphi models are available for download on the Xilinx website (under the Device Model tab).
X-Ref Target - Figure 10-1
DELPHI BCI-CTM Topology for
Flip-Chip BGA
TI
TO
Two Resistor Model
Junction
SIDE
Rjc Junction Rjb
BI
BO
UG1075_c9_01_101415
Figure 10-1: Thermal Model Topologies
RECOMMENDED: Xilinx recommends the use of the Delphi thermal model. Xilinx also recommends a best practice review of manufacturing variations on the thermal performance of the device from both the thermal interface material parameters and thermal solution variations. Examples of manufacture variations include the tolerance in airflow from a fan, the tolerance on performance of the heat pipe and vapor chamber, and manufacturing variations of the attachment of fins to the heat-sink base and the flatness of the surface.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
247
Chapter 11
Thermal Management Strategy
Introduction
As described in this section, Xilinx relies on a multi-pronged approach to consuming less power and dissipating heat for systems using Zynq� UltraScale+TM devices.
Flip-Chip Packages
Zynq UltraScale+ devices are offered in flip-chip BGA packages, which present a low thermal path. With the exception of the bare-die packages, the flip-chip BGA packages incorporate a heat spreader with an additional thermal interface material (TIM), as shown in Figure 11-1.
X-Ref Target - Figure 11-1
Thermal Interface Material (TIM)
Lid-Heat Spreader Die
Substrate
UG1075_c10_01_101415
Figure 11-1: Heat Spreader with Thermal Interface Material
Materials with better thermal conductivity and consistent process deliver low thermal resistance to the heat spreader.
A parallel effort to ensure optimized package electrical return paths produces the added benefit of enhanced power and ground plane arrangement in the packages. A boost in copper density on the planes improves the overall thermal conductivity through the laminate. In addition, the extra dense and distributed via fields in the package increase the vertical thermal conductivity.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
248
Chapter 11: Thermal Management Strategy
System Level Heat Sink Solutions
To complete a comprehensive thermal management strategy, an overall thermal budget that includes custom or OEM heat sink solutions depends on the physical and mechanical constraints of the system. A heat-sink solution, managed by the system-level designer, should be tailored to the design and specific system constraints. This includes understanding the inherent device capabilities for delivering heat to the surface.
By considering the system's physical, mechanical, and environmental constraints, the overall thermal budget is maintained and does not exceed the device's maximum operating temperature. The heat sink is an integral part of the thermal management solution to maintain a safe operating temperature. As a result, the system-level designer must be aware of the following:
� For lidless packages, the nominal stiffener height can be different from the height of the die. Therefore, the heat sink must have an island to contact the die.
� Especially for lidless packages, Xilinx advises against direct use of the JC parameters (see Table 10-1) to determine the thermal performance of the device in your application. The calculation of these parameters are done in accordance with the JEDEC standard JESD51 where system parameters differ greatly from most applications. Instead, run thermal simulations of the system in worst-case environmental conditions using Delphi thermal models, which more accurately represent the device thermal performance under all boundary conditions.
� Consider the mechanical specifications of the package as well as the selection of the thermal interface between the die and the thermal management solution to ensure the lowest thermal contact resistance.
� The total thermal contact of the thermal interface material is determined based on parameters from the thermal interface supplier's data sheet.
� See the applied pressure recommendation on page 252. Lower pressure runs the risk of poor thermal contact and higher pressure runs the risk of damaging the device; therefore, strict control of pressure is required.
� Consider all uncertainties in thermal modeling, including manufacturing variations from the thermal solutions (for example, fan airflow tolerance, heat pipe or vapor chamber performance tolerance, variation of the attachment of fins to heat sink base, and surface flatness).
Thermal Interface Material
When installing heat sinks for Zynq UltraScale+ devices, a suitable thermal interface material (TIM) must be used. This thermal material significantly aids the transfer of heat from the component to the heat sink.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
249
Chapter 11: Thermal Management Strategy
For bare-die flip-chip BGAs, the surface of the silicon contacts the heat sink. For lidded flip-chip BGAs, the lid contacts the heat sink. The surface size of the bare-die flip-chip BGA and lidded flip-chip BGAs are different. Xilinx recommends a different type of thermal material for long-term use with each type of flip-chip BGAs package.
Thermal interface material is needed because even the largest heat sink and fan cannot effectively cool an Zynq UltraScale+ device unless there is good physical contact between the base of the heat sink and the top of the Zynq UltraScale+ device. The surfaces of both the heat sink and the Zynq UltraScale+ device silicon are not absolutely smooth. This surface roughness is observed when examined at a microscopic level. Because surface roughness reduces the effective contact area, attaching a heat sink without a thermal interface material is not sufficient due to inadequate surface contact.
A thermal interface material such as phase-change material, thermal grease, or thermal pads fills these gaps and allows effective transference of heat between the Zynq UltraScale+ device die and the heat sink.
The selection of the thermal interface (TIM) between the package and the thermal management solution is critical to ensure the lowest thermal contact resistance. Therefore, the following parameters must be considered.
1. The flatness of the lid and the flatness of the contact surface of the thermal solution.
2. The applied pressure of the thermal solution on the package, which must be within the allowable maximum pressure that can be applied on the package.
3. The total thermal contact of the thermal interface material. This value is determined based on the parameters in step 1 and step 2, which are published in the data sheet of the thermal interface supplier.
Types of TIM
There are many type of TIM available for sale. The most commonly used thermal interface materials are listed.
� Thermal grease
� Thermal pads
� Phase change material
� Thermal paste
� Thermal adhesives
� Thermal tape
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
250
Chapter 11: Thermal Management Strategy
Guidelines for Thermal Interface Materials
Five factors affect the choice, use, and performance of the interface material used between the processor and the heat sink:
� Thermal Conductivity of the Material
� Electrical Conductivity of the Material
� Spreading Characteristics of the Material
� Long-Term Stability and Reliability of the Material
� Ease of Application
� Applied Pressure from Heat Sink to the Package via Thermal Interface Materials
Thermal Conductivity of the Material
Thermal conductivity is the quantified ability of any material to transfer heat. The thermal conductivity of the interface material has a significant impact on its thermal performance. The higher the thermal conductivity, the more efficient the material is at transferring heat. Materials that have a lower thermal conductivity are less efficient at transferring heat, causing a higher temperature differential to exist across the interface. To overcome this less efficient heat transfer, a better cooling solution (typically, a more costly solution) must be used to achieve the desired heat dissipation.
Electrical Conductivity of the Material
Some metal-based TIM compounds are electrically conductive. Ceramic-based compounds are typically not electrically conductive. Manufacturers produce metal-based compounds with low-electrical conductivity, but some of these materials are not completely electrically inert. Metal-based thermal compounds are not hazardous to the Zynq UltraScale+ device die itself, but other elements on the Zynq UltraScale+ device or motherboard can be at risk if they become contaminated by the compound. For this reason, Xilinx does not recommend the use of electrically conductive thermal interface material.
Spreading Characteristics of the Material
The spreading characteristics of the thermal interface material determines its ability, under the pressure of the mounted heat sink, to spread and fill in or eliminate the air gaps between the Zynq UltraScale+ device and the heat sink. Because air is a very poor thermal conductor, the more completely the interface material fills the gaps, the greater the heat transference.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
251
Chapter 11: Thermal Management Strategy
Long-Term Stability and Reliability of the Material
The long-term stability and reliability of the thermal interface material is described as the ability to provide a sufficient thermal conductance even after an extended time or extensive. Low-quality compounds can harden or leak out over time (the pump-out effect), leading to overheating or premature failure of the Zynq UltraScale+ device. High-quality compounds provide a stable and reliable thermal interface material throughout the lifetime of the device. Thermal greases with higher viscosities are typically more resistant to pump out effects on bare-die devices.
Ease of Application
A spreadable thermal grease requires the surface mount supplier to carefully use the appropriate amount of material. Too much or too little material can cause problems. The thermal pad is a fixed size and is therefore easier to apply in a consistent manner.
Applied Pressure from Heat Sink to the Package via Thermal Interface Materials
RECOMMENDED: Xilinx recommends that the applied pressure on the package be in the range of 20 to 50 PSI for optimum performance of the thermal interface material (TIM) between the package and the heat sink. Thermocouples should not be present between the package and the heat sink, as their presence will degrade the thermal contact and result in incorrect thermal measurements. The best practice is to select the appropriate pressure (in the 20 to 50 PSI range) for the optimum thermal contact performance between the package and the thermal system solution, and the mechanical integrity of the package (with the thermal solution to pass all mechanical stress and vibration qualification tests).
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
252
Chapter 11: Thermal Management Strategy
RECOMMENDED: Xilinx recommends using dynamic mounting around the four corners of the device package. On the PCB, use a bracket clip as part of the heat sink attachment to provide mechanical package support. See Figure 11-2.
X-Ref Target - Figure 11-2
HS Base
Heat Sink
PKG
X15431-111316
Figure 11-2: Dynamic Mounting and Bracket Clips on Heat Sink Attachment
Heat Sink Removal
When removing or reworking heat sinks, the phase-change material residue must be removed from the surface of the die. Laird Technologies, Inc. provides the following guidance for complete removal of the phase-change material from the component.
Instructions for Removal of Phase-change Material
1. Separate the Components 2. Scrape Away Thick Residue 3. Clean Remaining Residue with Solvent 4. Working with Laird Material
Separate the Components
At room temperature, if possible, use a back and forth twisting motion to break the bond between the phase-change thermal interface material and mated components (i.e., heat sink and Zynq UltraScale+ device). See Figure 11-3.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
253
X-Ref Target - Figure 11-3
Chapter 11: Thermal Management Strategy
Phase Change Thermal Interface
Material
Zynq UltraScale+
Device
Heat Sink
X20431-022818
Figure 11-3: Breaking the Bond between Thermal Interface Material and Mated Components
For smaller components (typically 15 mm x 15 mm or less), the bond usually breaks free easily at room temperature. For larger components, in situations where minimal movement is available, or if using fragile components, heat the component (preferred) or heat sink to about 40�C�60�C before removal.
The guideline is 40�C�60�C, however, you might find that for your application, heating to 35�C is adequate. You might prefer to heat to 70�C which makes the phase-change thermal interface material very soft and the components can be easily separated.
Scrape Away Thick Residue
For a faster clean-up once components are separated, scrape away any large residual material amounts with a plastic spatula or a wooden tongue depressor. A clean dry rag can be used to wipe away excess material.
Clean Remaining Residue with Solvent
Using a clean cloth/wipe, wet it with your choice of solvent (see the following list) and wipe away any remaining residue.
� Toluene (easiest) � Acetone (very good) � Isoparaffinic hydrocarbon: Isopar, Soltrol (trade names) (very good) � Isopropyl alcohol (OK)
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
254
Chapter 11: Thermal Management Strategy
Working with Laird Material
Safe handling, disposal, and first-aid measures for working with phase-change material are included in the Laird Technologies material safety data sheet (MSDS). Read the MSDS before using or handling. See the Laird Technologies, Inc. website, www.lairdtech.com.
Measurement Debug
When performing in-system thermal testing, to ensure accurate data and not incur damage to the device, do not place a thermocouple in between the device and the heat sink. On the extreme side, it might cause additional mechanical and/or thermal stress to the device, leading to damage. Even if damage does not occur, it often leads to a thicker and or uneven thermal interface material thickness, leading to a thermal performance difference from a system without a thermocouple. To obtain the device temperature, use the System Monitor as a non-invasive means to get accurate device measurements while debugging the system.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
255
Chapter 12
Heat Sink Guidelines for Bare-die Flip-Chip Packages
Heat Sink Attachments for Bare-die FB Packages
Heat sinks can be attached to the package in multiple ways. For heat to dissipate effectively, the advantages and disadvantages of each heat sink attachment method must be considered. Factors influencing the selection of the heat sink attachment method include the package type, contact area of the heat source, and the heat sink type.
Silicon and Decoupling Capacitors Height Consideration
When designing heat sink attachments for bare-die flip-chip BGA packages, the height of the die above the substrate and also the height of decoupling capacitors must be considered (Figure 12-1). This is to prevent electrical shorting between the heat sink (metal) and the decoupling capacitors.
X-Ref Target - Figure 12-1
Decoupling Capacitor
Silicon
Underfill
Substrate
UG1075_c11_01_101415
Figure 12-1: Cross Section of Bare-die Flip-chip BGA
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
256
Chapter 12: Heat Sink Guidelines for Bare-die Flip-Chip Packages
Types of Heat Sink Attachments
There are six main methods for heat sink attachment. Table 12-1 lists their advantages and disadvantages.
� Thermal tape � Thermally conductive adhesive or glue � Wire form Z-clips � Plastic clip-ons � Threaded stand-offs (PEMs) and compression springs � Push-pins and compression springs
Table 12-1: Heat Sink Attachment Methods
Attachment Method
Thermal tape
Advantages
Disadvantages
� Generally easy to attach and is inexpensive. � Lowest cost approach for aluminum heat
sink attachment. � No additional space required on the PCB.
� The surfaces of the heat sink and the chip must be very clean to allow the tape to bond correctly.
� Because of the small contact area, the tape might not provide sufficient bond strength.
� Tape is a moderate to low thermal conductor that could affect the thermal performance.
Thermally conductive adhesive or glue
� Outstanding mechanical adhesion. � Fairly inexpensive, costs a little more than
tape. � No additional space required on the PCB.
� Adhesive application process is challenging and it is difficult to control the amount of adhesive to use.
� Difficult to rework. � Because of the small contact area, the
adhesive might not provide sufficient bond strength.
Wire form Z-clips
� It provides a strong and secure mechanical attachment. In environments that require shock and vibration testing, this type of strong mechanical attachment is necessary.
� Easy to apply and remove. Does not cause the semiconductors to be destroyed (epoxy and occasionally tape can destroy the device).
� It applies a preload onto the thermal interface material (TIM). Pre-loads actually improve thermal performance.
� Requires additional space on the PCB for anchor locations.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
257
Chapter 12: Heat Sink Guidelines for Bare-die Flip-Chip Packages
Table 12-1: Heat Sink Attachment Methods (Cont'd)
Attachment Method
Plastic clip-ons
Advantages
Disadvantages
� Suitable for designs where space on the PCB is limited.
� Easy to rework by allowing heat sinks to be easily removed and reapplied without damaging the PCB board.
� Can provide a strong enough mechanical attachment to pass shock and vibration test.
� Needs a keep out area around the silicon devices to use the clip.
� Caution is required when installing or removing clip-ons because localized stress can damage the solder balls or chip substrate.
Threaded stand-offs (PEMs) and compression springs
� Provides stable attachments to heat source and transfers load to the PCB, backing plate, or chassis.
� Suitable for high mass heat sinks. � Allows for tight control over mounting
force and load placed on chip and solder balls.
� Holes are required in the PCB taking valuable space that can be used for trace lines.
� Tends to be expensive, especially since holes need to be drilled or predrilled onto the PCB board to use stand-offs.
Push-pins and compression springs
� Provides a stable attachment to a heat source and transfers load to the PCB.
� Allows for tight control over mounting force and load placed on chip and solder balls.
� Requires additional space on the PCB for push-pin locations.
Heat Sink Attachment
Component Pick-up Tool Consideration
For pick-and-place machines to place bare-die flip-chip BGAs onto PCBs, Xilinx recommends using soft tips or suction cups for the nozzles. This prevents chipping, scratching, or even cracking of the bare die (Figure 12-2).
X-Ref Target - Figure 12-2
Decoupling Capacitor
Preferred
Metal Tip
Nozzle
Silicon
Soft Tips
Substrate
Incorrect Pickup Method
Decoupling Capacitor
Metal Tip
Nozzle
Silicon
Substrate
Metal Pick Up Tip Nozzle with Soft Tips or Suction Cups is Preferred
Metal Pick Up Tip Nozzle Can Damage the Exposed Silicon
UG1075_c11_02_101415
Figure 12-2: Recommended Method For Using Pick-up Tools
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
258
Chapter 12: Heat Sink Guidelines for Bare-die Flip-Chip Packages
Heat Sink Attachment Process Considerations
After the component is placed onto the PCBs, when attaching a heat sink to the bare-die package, the factors in Table 12-2 must be carefully considered (see Figure 12-3).
Table 12-2: Heat Sink Attachment Considerations
Consideration(s)
Effect(s)
Recommendation(s)
In heat sink attach process, what factors can cause damage to the exposed die and passive capacitors?
� Uneven heat sink placement � Uneven TIM thickness � Uneven force applied when
placing heat sink placement
� Even heat sink placement � Even TIM thickness � Even force applied when placing heat sink
placement
Does the heat sink tilt or tip the post attachment?
Uneven heat sink placement will damage the silicon and can cause field failures.
� Careful handling not to contact the heat sink with the post attachment.
� Use a fixture to hold the heat sink in place with post attachment until it is glued to the silicon.
X-Ref Target - Figure 12-3
Even Force
Preferred
Silicon Substrate
Even Force
Decoupling Capacitor
Incorrect Alignment
Silicon Substrate
Decoupling Capacitor
Even Force
Preferred
Even Force
Incorrect Force
Heat Sink Silicon
Substrate
Mother Board
Silicon Substrate
Decoupling Capacitor
Preferred application of heat sink
1. Heat sink is aligned parallel to silicon 2. Even bond line thickness of TIM 3. Even compressive force is applied on all sides
Improper application of heat sink can cause damage to heat sink
1. Heat sink is not aligned parallel to silicon 2. Uneven bond line thickness of TIM 3. Uneven force is applied
UG1075_c11_03_101415
Figure 12-3: Recommended Application of Heat Sink
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
259
Chapter 12: Heat Sink Guidelines for Bare-die Flip-Chip Packages
Standard Heat Sink Attach Process with Thermal Conductive Adhesive
Prior to attaching the heat sink, the Zynq UltraScale+ device needs be surface mounted on the motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent any movement during the heat sink attachment process.
2. Thermoset material (electrically non-conductive) is applied over the backside surface of silicon in a pattern using automated dispensing equipment. Automated dispensers are often used to provide a stable process speed at a relatively low cost. The optimum dispensing pattern needs to be determined by the SMT supplier.
Note: Minimal volume coverage of the backside of the silicon can result in non-optimum heat
transfer.
3. The heat sink is placed on the backside of the silicon with a pick and place machine. A uniform pressure is applied over the heat sink to the backside of the silicon. As the heat sink is placed, the adhesive spreads to cover the backside silicon. A force transducer is normally used to measure and limit the placement force.
4. The epoxy is cured with heat at a defined time.
Note: The epoxy curing temperature and time is based on manufacturer's specifications.
Standard Heat Sink Attach Process with Thermal Adhesive Tape
Prior to attaching the heat sink, the Zynq UltraScale+ device needs be surface mounted on the motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent any movement during the heat sink attachment process.
2. Thermal adhesive tape cut to the size of the heat sink is applied on the underside of the heat sink at a modest angle with the use of a squeegee rubber roller. Apply pressure to help reduce the possibility of air entrapment under the tape during application.
3. The heat sink is placed on the backside of the silicon with a pick and place machine. A uniform pressure is applied over the heat sink to the backside of the silicon. As the heat sink is placed, the thermal adhesive tape is glued to the backside of the silicon. A force transducer is normally used to measure and limit the placement force.
4. A uniform and constant pressure is applied uniformly over the heat sink and held for a defined time.
Note: The thermal adhesive tape hold time is based on manufacturer's specifications.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
260
Chapter 12: Heat Sink Guidelines for Bare-die Flip-Chip Packages
Push-Pin and Shoulder Screw Heat Sink Attachment Process with Phase Change Material (PCM) Application
Prior to attaching the heat sink, the Zynq UltraScale+ device needs be surface mounted on the motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent any movement during the heat sink attachment process.
Note: The jig or fixture needs to account for the push pin depth of the heat sink. 2. PCM tape, cut to the size of the heat sink, is applied on the underside of the heat sink
at a modest angle with the use of a squeegee rubber roller. Apply pressure to help reduce the possibility of air entrapment under the tape during application.
3. Using the push-pin tool, heat sinks are applied over the packages ensuring a pin locking action with the PCB holes. The compression load from springs applies the appropriate mounting pressure required for proper thermal interface material performance.
Note: Heat sinks must not tilt during installation. This process cannot be automated due to the
mechanical locking action which requires manual handling. The PCB drill hole tolerances need to be close enough to eliminate any issues concerning the heat sink attachment.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
261
Appendix A
Additional Resources and Legal Notices
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support.
Solution Centers
See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips.
Documentation Navigator and Design Hubs
Xilinx� Documentation Navigator provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open the Xilinx Documentation Navigator (DocNav): � From the Vivado� IDE, select Help > Documentation and Tutorials. � On Windows, select Start > All Programs > Xilinx Design Tools > DocNav. � At the Linux command prompt, enter docnav. Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs: � In the Xilinx Documentation Navigator, click the Design Hubs View tab. � On the Xilinx website, see the Design Hubs page. Note: For more information on Documentation Navigator, see the Documentation Navigator page
on the Xilinx website.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
262
Appendix A: Additional Resources and Legal Notices
References
1. Zynq UltraScale+ MPSoC Overview (DS891) 2. Zynq UltraScale+ RFSoC Overview (DS889) 3. XQ UltraScale Architecture Data Sheet: Overview (DS895) 4. XA Zynq UltraScale+ MPSoC Data Sheet: Overview (DS894) 5. Zynq UltraScale+ device Packaging Specifications 6. UltraScale Architecture SelectIO Resources User Guide (UG571) 7. UltraScale Architecture Clocking Resources User Guide (UG572) 8. Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) 9. Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) 10. Zynq UltraScale+ Device Technical Reference Manual (UG1085) 11. UltraScale Architecture GTH Transceiver User Guide (UG576) 12. UltraScale Architecture GTY Transceiver User Guide (UG578) 13. UltraScale Architecture System Monitor User Guide (UG580) 14. UltraScale Architecture PCB Design Guide (UG583) 15. UltraScale Architecture-Based Memory Interface Solutions Product Guide (PG150) 16. UltraScale Architecture Configuration User Guide (UG570) 17. FAQ: Top Marking Change for 7 Series, UltraScale, and UltraScale+ Products (XTP424) 18. FAQ: Top Marking Change for 7 Series, UltraScale, and UltraScale+ Products (XTP544) 19. The following websites contain additional information on heat management and contact
information. � Wakefield: www.wakefield-vette.com � Aavid: www.aavid.com � Advanced Thermal Solutions: www.qats.com � Radian Thermal Products: www.radianheatsinks.com � Thermo Cool: www.thermocoolcorp.com � CTS: www.ctscorp.com
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
263
Appendix A: Additional Resources and Legal Notices
20. Refer to the following websites for interface material sources:
� Henkel: www.henkel.com � Bergquist Company: www.bergquistcompany.com � AOS Thermal Compound: www.aosco.com � Chomerics: www.chomerics.com � Kester: www.kester.com 21. Refer to the following websites for CFD tools Xilinx supports with thermal models.
� Mentor Flotherm: www.mentor.com/products/mechanical/flotherm/flotherm/ � ANSYS Icepak: www.ansys.com 22. Refer to the Package Thermal Models on xilinx.com.
23. The following papers are referenced for more information on thermal modeling.
� Lemczyk, T.F., Mack, B., Culham, J.R. and Yovanovich, M.M., 1992, "Printed Circuit Board Trace Thermal Analysis and Effective Conductivity", ASME J. Electronic Packaging, Vol. 114, pp. 413 - 419.50.
� Refai-Ahmed, G. and Karimanal, K., 2003, "Validation of Compact Conduction Models of BGA Under Realistic Boundary," J. of Components and Packaging Technology, Vol. 26, No. 3, pp. 610-615.
� Sansoucy, E, Refai-Ahmed, G., and Karimanal, K., 2002, "Thermal Characterization of TBGA Package for an integration in Board Level Analysis," Eighth Intersociety on Thermal Conference Phenomena in Electronic Systems, San Diego., USA.
� Karimanal,K and Refai-Ahmed, G., and., 2002, "Validation of Compact Conduction Models of BGA Under Realistic Boundary Conditions," Eighth Intersociety on Thermal Conference Phenomena in Electronic Systems, San Diego, USA.
� Karminal, K. and Refai-Ahmed, G., 2001, "Compact conduction Model (CCM) of Microelectronic Packages- A BGA Validation Study," APACK Conference on Advance in Packaging, Singapore.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
264
Appendix A: Additional Resources and Legal Notices
Please Read: Important Legal Notices
The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos. AUTOMOTIVE APPLICATIONS DISCLAIMER AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. � Copyright 2015�2020 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, Arm, ARM1176JZ-S, CoreSight, Cortex, PrimeCell, Mali, and MPCore are trademarks of Arm Limited in the EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Zynq UltraScale+ Packaging and Pinouts UG1075 (v1.9) June 24, 2020
www.xilinx.com
Send Feedback
265