SLG47004 dialog r01
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SLG47004 dialog r01
SLG47004 Datasheet - Dialog Semiconductor
Optional Vref Voltage Connection for Input Pins. ▫ Two 1024 Position Digital Rheostats. ▫ User Defined Auto-Trim Option. ▫ Manual Control ...
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
General Description
The SLG47004 provides a small, low power component for commonly used analog signal processing and mixed-signal functions. Individual, tunable, analog components used in conjunction with configurable logic provide a way to solve a wide variety of tasks with minimal costs. The user creates their circuit design by programming the multiple time Non-Volatile Memory (NVM) to configure the interconnect logic, the analog and digital macrocell, and the IO Pins of the SLG47004.
Key Features
Two Programmable Bandwidth Op Amps 3-Op Amp Instrumentation Amplifier Function (including Additional Internal Op Amp) Rail to Rail Input Low Quiescent Current Low Offset Voltage Analog Comparator Mode Optional Vref Voltage Connection for Input Pins
Two 1024 Position Digital Rheostats User Defined Auto-Trim Option Manual Control Option I2C Control Option Potentiometer Mode
Two Single-Pole/Single-Throw Analog Switches Voltage or Current Source/Sink Mode
One Low Offset Chopper Comparator Two Low Power General Purpose ACMPs
ACMP Sampling Mode Hysteresis with Independently-Selectable Thresholds Three Voltage References Two ACMP Vref Output Buffers One High Drive Buffer Thirteen Combination Function Macrocells Three Selectable DFF/LATCH or 2-bit LUTs One Selectable Programmable Pattern Generator or
2-bit LUT Seven Selectable DFF/LATCH or 3-bit LUTs One Selectable Pipe Delay or Ripple Counter or
3-bit LUT One Selectable DFF/LATCH or 4-bit LUT Seven Multi-Function Macrocells Six Selectable DFF/LATCH or 3-bit LUTs + 8-bit
Delay/Counters One Selectable DFF/LATCH or 4-bit LUT + 16-bit
Delay/Counter Serial Communications
I2C Protocol Interface 2-kbit (256 x 8) I2C-Compatible (2-Wire) Serial EEPROM
Emulation with Software Write Protection Programmable Delay with Edge Detector Output Deglitch Filter or Edge Detector Three Oscillators
2.048 kHz Oscillator 2.048 MHz Oscillator 25 MHz Oscillator Analog Temperature Sensor Power-On Reset In-System Programmability Multiple Time Programmable Memory Wide Range Power Supply 2.5 V (�4 %) to 5 V (�10 %) VDD Operating Temperature Range: -40 �C to +85 �C RoHS Compliant/Halogen-Free Package Available 24-pin STQFN: 3 mm x 3 mm x 0.55 mm, 0.4 mm pitch
Applications
Adjust Precision Threshold Sensor Offset Trimming/Calibration Tunable Analog Filters Operational Amplifier Adjustable Gain and Offset Adjustable Voltage-to-Current Conversions Personal Computers and Servers PC Peripherals Consumer Electronics Data Communications Equipment Handheld and Portable Electronics Smartphones and Fitness Bands Notebook and Tablet PCs
Datasheet
CFR0011-120-00
Revision 2.3 1 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Contents
General Description .................................................................................................................................................................1
Key Features ............................................................................................................................................................................1
Applications.............................................................................................................................................................................. 1
1 Block Diagram ....................................................................................................................................................................12
2 Pinout ..................................................................................................................................................................................13 2.1 Pin Configuration - STQFN-24L ...........................................................................................................................13
3 Characteristics ...................................................................................................................................................................16 3.1 Absolute Maximum Ratings .................................................................................................................................16 3.2 Electrostatic Discharge Ratings ...........................................................................................................................16 3.3 Recommended Operating Conditions ..................................................................................................................16 3.4 Electrical Characteristics ......................................................................................................................................17 3.5 I2C Pins Electrical Characteristics ........................................................................................................................22 3.6 Macrocells Current Consumption .........................................................................................................................24 3.7 Timing Characteristics .........................................................................................................................................25 3.8 Oscillator Characteristics .....................................................................................................................................26 3.9 ACMP Characteristics ..........................................................................................................................................27 3.10 Internal Vref Characteristics ...............................................................................................................................28 3.11 Output Buffers Characteristics ...........................................................................................................................28 3.12 Analog Temperature Sensor Characteristics .....................................................................................................29 3.13 Programmable Operational Amplifier Characteristics ........................................................................................30 3.14 100K Digital Rheostat Characteristics ...............................................................................................................33 3.15 Analog Switches Characteristics .......................................................................................................................35
4 User Programmability ........................................................................................................................................................36
5 IO Pins .................................................................................................................................................................................37 5.1 GPIO Pins ............................................................................................................................................................37 5.2 GPI Pins ...............................................................................................................................................................37 5.3 Pull-Up/Down Resistors .......................................................................................................................................37 5.4 Fast Pull-Up/Down during Power-Up ...................................................................................................................37 5.5 I2C Mode IO Structure .........................................................................................................................................38 5.6 Matrix OE IO Structure .........................................................................................................................................39 5.7 GPI Structure .......................................................................................................................................................40 5.8 IO Pins Typical Performance ...............................................................................................................................41
6 Connection Matrix ..............................................................................................................................................................44 6.1 Matrix Input Table ................................................................................................................................................45 6.2 Matrix Output Table .............................................................................................................................................46 6.3 Connection Matrix Virtual Inputs ..........................................................................................................................49 6.4 Connection Matrix Virtual Outputs .......................................................................................................................50
7 Combination Function Macrocells ....................................................................................................................................51 7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................51 7.2 2-bit LUT or Programmable Pattern Generator ....................................................................................................54 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells .............................................................................................56 7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell ...............................................................................................64 7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell ..............................................................................................66
8 Multi-Function Macrocells .................................................................................................................................................70 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells ..............................................................................70 8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell ..............................................................................79 8.3 CNT/DLY/FSM Timing Diagrams .........................................................................................................................82 8.4 Wake and Sleep Controller ..................................................................................................................................91
9 Analog Comparators ..........................................................................................................................................................95 9.1 Analog Comparators Overview ............................................................................................................................95 9.2 Chopper Analog Comparator ...............................................................................................................................97 9.3 ACMP Sampling Mode .........................................................................................................................................98 9.4 ACMP Typical Performance .................................................................................................................................99
10 Programmable Operational Amplifiers .........................................................................................................................102 10.1 General Description .........................................................................................................................................102
Datasheet
CFR0011-120-00
Revision 2.3 2 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
10.2 Modes of Operation ..........................................................................................................................................104 10.3 Op Amps Typical Performance ........................................................................................................................108
11 Analog Switch Macrocell ...............................................................................................................................................154 11.1 Analog Switch General Description ..................................................................................................................154 11.2 Half Bridge Mode .............................................................................................................................................156 11.3 Analog Switches Typical Performance .............................................................................................................157
12 Digital Rheostats and Programmable Trim Block .......................................................................................................159 12.1 Potentiometer Mode .........................................................................................................................................161 12.2 Calculating Actual Resistance ..........................................................................................................................161 12.3 Digital Rheostat Value Self-programming into the NVM ..................................................................................162 12.4 Trimming process Using Programmable Trim Block ........................................................................................165 12.5 Using Chopper ACMP ......................................................................................................................................171
13 Programmable Delay/Edge Detector ............................................................................................................................177 13.1 Programmable Delay Timing Diagram - Edge Detector Output .......................................................................177
14 Additional Logic Function. Deglitch Filter ...................................................................................................................178
15 Voltage Reference ..........................................................................................................................................................179 15.1 Voltage Reference Overview ...........................................................................................................................179 15.2 Vref Selection Table ........................................................................................................................................179 15.3 Vref Block Diagram ..........................................................................................................................................181 15.4 Voltage Reference Typical Performance .........................................................................................................185
16 r.Clocking ........................................................................................................................................................................186 16.1 OSC General Description .................................................................................................................................187 16.2 Oscillator0 (2.048 kHz) .....................................................................................................................................189 16.3 Oscillator1 (2.048 MHz) ...................................................................................................................................190 16.4 Oscillator2 (25 MHz) ........................................................................................................................................191 16.5 CNT/DLY Clock Scheme ..................................................................................................................................191 16.6 External Clocking .............................................................................................................................................192 16.7 Oscillators Power-On Delay .............................................................................................................................193 16.8 Oscillators Accuracy .........................................................................................................................................195 16.9 Oscillators Settling time ....................................................................................................................................197 16.10 Oscillators Current Consumption ..................................................................................................................199
17 Power-On Reset ..............................................................................................................................................................203 17.1 General Operation ............................................................................................................................................203 17.2 POR Sequence ................................................................................................................................................204 17.3 Macrocells Output States During POR Sequence ...........................................................................................204
18 I2C Serial Communications Macrocell ..........................................................................................................................207 18.1 I2C Serial Communications Macrocell Overview ..............................................................................................207 18.2 I2C Serial Communications Device Addressing ...............................................................................................207 18.3 I2C Serial General Timing ................................................................................................................................208 18.4 I2C Serial Communications Commands ...........................................................................................................208 18.5 Chip Configuration Data Protection ..................................................................................................................211 18.6 I2C Serial Command Register Map ..................................................................................................................212 18.7 I2C Additional Options ......................................................................................................................................215
19 Non-Volatile Memory ......................................................................................................................................................217 19.1 Serial NVM Write Operations ...........................................................................................................................217 19.2 Serial NVM Read Operations ...........................................................................................................................219 19.3 Serial NVM Erase Operations ..........................................................................................................................219 19.4 Acknowledge Polling ........................................................................................................................................220 19.5 Low power standby mode ................................................................................................................................220 19.6 Emulated EEPROM Write Protection ...............................................................................................................220
20 Analog Temperature Sensor .........................................................................................................................................222
21 Register Definitions .......................................................................................................................................................225 21.1 Register Map ....................................................................................................................................................225
22 Package Top Marking System Definition .....................................................................................................................284 22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package ............................................................................284
23 Package Information ......................................................................................................................................................285 23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package ......................................285
Datasheet
CFR0011-120-00
Revision 2.3 3 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
23.2 STQFN Handling ..............................................................................................................................................285 23.3 Soldering Information .......................................................................................................................................285
24 Ordering Information .....................................................................................................................................................286 24.1 Tape and Reel Specifications ..........................................................................................................................286 24.2 Carrier Tape Drawing and Dimensions ............................................................................................................286
25 Layout Guidelines ..........................................................................................................................................................287 25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package ...........................................................................287
Glossary ................................................................................................................................................................................ 288
Revision History...................................................................................................................................................................291
Datasheet
CFR0011-120-00
Revision 2.3 4 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Figures
Figure 1: Block Diagram...........................................................................................................................................................12 Figure 2: Steps to Create a Custom GreenPAK Device...........................................................................................................39 Figure 3: IO with I2C Mode IO Structure Diagram....................................................................................................................41 Figure 4: Matrix OE IO Structure Diagram ...............................................................................................................................42 Figure 5: IO0 GPI Structure Diagram .......................................................................................................................................43 Figure 6: Typical High Level Output Current vs. High Level Output Voltage at T = 25 �C .......................................................44 Figure 7: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 �C, Full Range ......................44 Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 �C .........................................45 Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 �C, Full Range ......................45 Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 �C .......................................46 Figure 11: Connection Matrix ...................................................................................................................................................47 Figure 12: Connection Matrix Example ....................................................................................................................................47 Figure 13: 2-bit LUT0 or DFF0 .................................................................................................................................................54 Figure 14: 2-bit LUT1 or DFF1 .................................................................................................................................................55 Figure 15: 2-bit LUT2 or DFF2 .................................................................................................................................................55 Figure 16: DFF Polarity Operations..........................................................................................................................................57 Figure 17: 2-bit LUT3 or PGen.................................................................................................................................................58 Figure 18: PGen Timing Diagram.............................................................................................................................................58 Figure 19: 3-bit LUT0 or DFF3 .................................................................................................................................................60 Figure 20: 3-bit LUT1 or DFF4 .................................................................................................................................................61 Figure 21: 3-bit LUT2 or DFF5 .................................................................................................................................................61 Figure 22: 3-bit LUT3 or DFF6 .................................................................................................................................................62 Figure 23: 3-bit LUT4 or DFF7 .................................................................................................................................................62 Figure 25: 3-bit LUT6 or DFF9 .................................................................................................................................................63 Figure 24: 3-bit LUT5 or DFF8 .................................................................................................................................................63 Figure 26: DFF Polarity Operations with nReset......................................................................................................................66 Figure 27: DFF Polarity Operations with nSet..........................................................................................................................67 Figure 28: 4-bit LUT0 or DFF10 ...............................................................................................................................................68 Figure 29: 3-bit LUT13/Pipe Delay/Ripple Counter ..................................................................................................................70 Figure 30: Example: Ripple Counter Functionality ...................................................................................................................71 Figure 31: Possible Connections Inside Multi-Function Macrocell ...........................................................................................73 Figure 32: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT7/DFF11, CNT/DLY1) ...................................................74 Figure 33: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF12, CNT/DLY2) ...................................................75 Figure 34: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF13, CNT/DLY3) ...................................................76 Figure 35: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF14, CNT/DLY4) .................................................77 Figure 36: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF15, CNT/DLY5) .................................................78 Figure 37: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF16, CNT/DLY6) .................................................79 Figure 38: 4-bit LUT1 or CNT/DLY0.........................................................................................................................................83 Figure 39: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3 ........................................................................85 Figure 40: Delay Mode Timing Diagram for Different Edge Select Modes...............................................................................86 Figure 41: Counter Mode Timing Diagram without Two DFFs Synced Up ..............................................................................86 Figure 42: Counter Mode Timing Diagram with Two DFFs Synced Up ...................................................................................87 Figure 43: One-Shot Function Timing Diagram........................................................................................................................88 Figure 44: Frequency Detection Mode Timing Diagram...........................................................................................................89 Figure 45: Edge Detection Mode Timing Diagram ...................................................................................................................90 Figure 46: Delayed Edge Detection Mode Timing Diagram .....................................................................................................91 Figure 47: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3 .....91 Figure 48: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3 .........92 Figure 49: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3 .....92 Figure 50: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3 .........93 Figure 51: Counter Value, Counter Data = 3............................................................................................................................93 Figure 52: Wake and Sleep Controller .....................................................................................................................................94 Figure 53: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used ...................................................95 Figure 54: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used ......................................................95 Figure 55: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used .......................................................96
Datasheet
CFR0011-120-00
Revision 2.3 5 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Figure 56: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Set is Used ..........................................................96 Figure 57: ACMP0L Block Diagram .........................................................................................................................................99 Figure 58: ACMP1L Block Diagram .......................................................................................................................................100 Figure 59: Chopper ACMP Block Diagram.............................................................................................................................101 Figure 60: Propagation Delay vs. Vref for ACMPx at T = 25 �C, VDD = 2.4 V to 5.5 V, Hysteresis = 0 .................................102 Figure 61: ACMPx Power-On Delay vs. VDD at BG - Forced.................................................................................................102 Figure 62: ACMPx Input Offset Voltage vs. Vref at T = -40 �C to 85 �C, VDD = 2.4 V to 5.5 V, Gain = 1 ..............................103 Figure 63: Chopper ACMP Input Offset Voltage vs. Vref at T = -40 �C to 85 �C, VDD = 2.4 V to 5.5 V, Gain = 1 .................103 Figure 64: ACMPx Current Consumption vs. VDD................................................................................................................................................104 Figure 65: Chopper ACMP Current Consumption vs. VDD (with 2.048 kHz Clock)................................................................104 Figure 66: Programmable Operational Amplifier OA0, OA1 Internal Circuit ..........................................................................105 Figure 67: Internal Operational Amplifier Circuit ....................................................................................................................106 Figure 68: Example of Input Offset Voltage Compensation ...................................................................................................107 Figure 69: Instrumentation Amplifier Structure.......................................................................................................................108 Figure 70: Instrumentation Operational Amplifier Configuration for Users Trim.....................................................................109 Figure 71: Typical Implementation of Voltage Regulator (A) and Current Sources (B, C) .....................................................110 Figure 72: Constant Current Sink...........................................................................................................................................111 Figure 73: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 128 kHz............................................. 111 Figure 74: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 512 kHz............................................. 112 Figure 75: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 2 MHz ............................................... 112 Figure 76: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 8 MHz ............................................... 113 Figure 77: Internal Op Amp Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 128 kHz ................................. 113 Figure 78: Internal Op Amp Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 512 kHz ................................. 114 Figure 79: Internal Op Amp Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 2 MHz .................................... 114 Figure 80: Internal Op Amp Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 8 MHz .................................... 115 Figure 81: OpAmp0, 1 Input Offset Voltage vs. Input CM Voltage at T = 25 �C, VDDA = 2.4 V ............................................115 Figure 82: OpAmp0, 1 Input Offset Voltage vs. Input CM Voltage at T = 25 �C, VDDA = 5.5 V ............................................116 Figure 83: Internal OpAmp Input Offset Voltage vs. Input CM Voltage at T = 25 �C, VDDA = 2.4 V .....................................116 Figure 84: Internal OpAmp Input Offset Voltage vs. Input CM Voltage at T = 25 �C, VDDA = 5.5 V .....................................117 Figure 85: Quiescent Current vs. Power Supply Voltage for BW = 128 kHz.......................................................................... 117 Figure 86: Quiescent Current vs. Power Supply Voltage for BW = 512 kHz.......................................................................... 118 Figure 87: Quiescent Current vs. Power Supply Voltage for BW = 2 MHz ............................................................................ 118 Figure 88: Quiescent Current vs. Power Supply Voltage for BW = 8 MHz ............................................................................ 119 Figure 89: OA0 Open Loop Gain and Phase vs. Frequency for BW = 128 kHz .................................................................... 119 Figure 90: OA0 Open Loop Gain and Phase vs. Frequency for BW = 512 kHz ....................................................................120 Figure 91: OA0 Open Loop Gain and Phase vs. Frequency for BW = 2 MHz .......................................................................120 Figure 92: OA0 Open Loop Gain and Phase vs. Frequency for BW = 8 MHz .......................................................................121 Figure 93: OA1 Open Loop Gain and Phase vs. Frequency for BW = 128 kHz ....................................................................121 Figure 94: OA1 Open Loop Gain and Phase vs. Frequency for BW = 512 kHz ....................................................................122 Figure 95: OA1 Open Loop Gain and Phase vs. Frequency for BW = 2 MHz .......................................................................122 Figure 96: OA1 Open Loop Gain and Phase vs. Frequency for BW = 8 MHz .......................................................................123 Figure 97: PSRR vs. Frequency VDD = 2.4 V to 5.5 V ..........................................................................................................123 Figure 98: 0.1 Hz to 10 Hz Noise, BW = 128 kHz ..................................................................................................................124 Figure 99: 0.1 Hz to 10 Hz Noise, BW = 512 kHz ..................................................................................................................124 Figure 100: 0.1 Hz to 10 Hz Noise, BW = 2 MHz...................................................................................................................125 Figure 101: 0.1 Hz to 10 Hz Noise, BW = 2 MHz...................................................................................................................125 Figure 102: Channel Separation vs. Frequency.....................................................................................................................126 Figure 103: Op Ampx Noise Voltage Density vs. Frequency..................................................................................................126 Figure 104: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 k for BW = 128 kHz ................................................127 Figure 105: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 k for BW = 512 kHz ................................................127 Figure 106: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 k for BW = 2 MHz ...................................................128 Figure 107: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 k for BW = 8 MHz....................................................128 Figure 108: Small Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 128 kHz..............................129 Figure 109: Small Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 512 kHz..............................129 Figure 110: Small Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 2 MHz ................................130 Figure 111: Small Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 8 MHz ................................130 Figure 112: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 128 kHz......................131
Datasheet
CFR0011-120-00
Revision 2.3 6 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Figure 113: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 512 kHz......................131 Figure 114: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 2 MHz.........................132 Figure 115: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 8 MHz.........................132 Figure 116: Large Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 80 pF, BW = 128 kHz .............................133 Figure 117: Large Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 80 pF, BW = 512kHz ..............................133 Figure 118: Large Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 80 pF, BW = 2 MHz ................................134 Figure 119: Large Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 80 pF, BW = 8 MHz ................................134 Figure 120: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 128 kHz......................135 Figure 121: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 512 kHz......................135 Figure 122: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 2 MHz ........................136 Figure 123: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 8 MHz ........................136 Figure 124: Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 128 kHz ............................................137 Figure 125: Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 512 kHz ............................................137 Figure 126: Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 2 MHz ...............................................138 Figure 127: Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 8 MHz ...............................................138 Figure 128: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 128 kHz.....................................139 Figure 129: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 512 kHz.....................................139 Figure 130: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 2 MHz .......................................140 Figure 131: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 8 MHz .......................................140 Figure 132: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 128 kHz .......................................141 Figure 133: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 512 kHz .......................................141 Figure 134: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 2 MHz..........................................142 Figure 135: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 8 MHz..........................................142 Figure 136: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 128 kHz, RLOAD = 600 ....................................143 Figure 137: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 128 kHz, RLOAD = 50 k ....................................143 Figure 138: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 128 kHz, RLOAD = 600 ....................................144 Figure 139: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 128 kHz, RLOAD = 50 k....................................144 Figure 140: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 512 kHz, RLOAD = 50 k ....................................145 Figure 141: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 512 kHz, RLOAD = 50 k ....................................145 Figure 142: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 512 kHz, RLOAD = 600 ....................................146 Figure 143: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 512kHz, RLOAD = 50 k .....................................146 Figure 144: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 2 MHz, RLOAD = 600 .......................................147 Figure 145: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 2 MHz, RLOAD = 50 k .......................................147 Figure 146: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 2 MHz, RLOAD = 600 ......................................148 Figure 147: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 2 MHz, RLOAD = 50 k.......................................148 Figure 148: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 8MHz, RLOAD = 600 ........................................149 Figure 149: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 8 MHz, RLOAD = 50 k .......................................149 Figure 150: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 8 MHz, RLOAD = 600 ......................................150 Figure 151: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 8 MHz, RLOAD = 50 k.......................................150 Figure 152: Overload Recovery Time vs. Power Supply Voltage RL= 50 k; G = 1 V/V, Rising...........................................151 Figure 153: Overload Recovery Time vs. Power Supply Voltage RL= 50 k; G = 1 V/V, Falling ..........................................151 Figure 154: Output Response to Power Down Signal G = 1 V/V; RL = 50 k; CL = 20 pF; VIN = VS/2, BW = 128 kHz ......152 Figure 155: Output Response to Power Down Signal G = 1 V/V; RL = 50 k; CL = 20 pF; VIN = VS/2, BW = 512 kHz ......152 Figure 156: Output Response to Power Down Signal G = 1 V/V; RL = 50 k; CL = 20 pF; VIN = VS/2, BW = 2 MHz .........153 Figure 157: Output Response to Power Down Signal G = 1 V/V; RL = 50 k; CL = 20 pF; VIN = VS/2, BW = 8 MHz .........153 Figure 158: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 128 kHz ................................................................154 Figure 159: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 512 kHz ................................................................154 Figure 160: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 2 MHz ...................................................................155 Figure 161: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 8MHz ....................................................................155 Figure 162: Opamps Quiescent Current Consumption vs. VDD ......................................................................................................................156 Figure 163: Analog Switch 0 Control Circuit...........................................................................................................................157 Figure 164: Analog Switch 1 Control Circuit...........................................................................................................................158 Figure 165: Structure of Half Bridge.......................................................................................................................................159 Figure 166: Typical RON vs. Input Voltage (Vi) for Vi = 0 to VDDA, ILOAD = 1 mA, VDDA = 2.4 V................................................ 160 Figure 167: Typical RON vs. Input Voltage (Vi) for Vi = 0 to VDDA, ILOAD = 1 mA, VDDA = 5.5 V................................................ 160 Figure 168: Turn-On Time vs. VDD at RLOAD = 100 to GND, VIN = VDD/2 .......................................................................................................161 Figure 169: Turn-Off Time vs. VDD at RLOAD = 100 to GND, VIN = VDD/2 .......................................................................................................161
Datasheet
CFR0011-120-00
Revision 2.3 7 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Figure 170: Programmable Trim Blocks and Digital Rheostat's Internal Circuit.....................................................................163 Figure 171: Rheostats in Potentiometer Mode......................................................................................................................164 Figure 172: Rheostat Tolerance Registers............................................................................................................................165 Figure 173: Flowchart of "Program" and "Reload" Signals ....................................................................................................166 Figure 174: Example of Latching and Processing "Program" and "Reload" Signals..............................................................167 Figure 175: Example of Auto-Trim Process for a Single Rheostat.........................................................................................169 Figure 176: Example of Auto-Trim Process with External Clock Signal.................................................................................170 Figure 177: Example of Auto-Trim Process for Two Rheostats .............................................................................................171 Figure 178: Example of Auto-Trim Process via I2C................................................................................................................172 Figure 179: Example of Hardware Configuration ...................................................................................................................173 Figure 180: Example of User Specific Trimming Process under I2C Master Control .............................................................174 Figure 181: DNL vs. Digital Code, Rheostat Mode (VAB = 1 V) at T = 25 �C .........................................................................175 Figure 182: INL vs. Digital Code, Rheostat Mode (VAB = 1 V) at T = 25 �C ..........................................................................175 Figure 183: DNL vs. Digital Code, Potentiometer Mode (VAB = 1 V) at T = 25 �C .................................................................176 Figure 184: INL vs. Digital Code, Potentiometer Mode (VAB = 1 V) at T = 25 �C ..................................................................176 Figure 185: (RAB/RAB)/TA Rheostat Mode Tempco...........................................................................................................177 Figure 186: RHx Zero Scale Error vs. Temperature (VIN = 1 V) ............................................................................................177 Figure 187: Transition Glitch in Worst Case (Code = 511 to Code = 512).............................................................................178 Figure 188: Gain vs. Frequency (Code = 512) at T = 25 �C, VDDA = 5 V...............................................................................178 Figure 189: RHx Settling Time vs. VDD at ILOAD = 1 mA, T = 25 �C .........................................................................................179 Figure 190: Programmable Delay ..........................................................................................................................................180 Figure 191: Edge Detector Output .........................................................................................................................................180 Figure 192: Deglitch Filter or Edge Detector ..........................................................................................................................181 Figure 193: Generalized Vref Structure..................................................................................................................................184 Figure 194: ACMP0L, ACMP1L Voltage Reference Block Diagram ......................................................................................185 Figure 195: HD Buffer and Chopper ACMP Reference Block Diagram .................................................................................186 Figure 196: Operational Amplifiers Voltage Reference Block Diagram..................................................................................187 Figure 197: Typical Load Regulation, Vref = 320 mV, T = -40 �C to +85 �C, Buffer - Enable................................................188 Figure 198: Typical Load Regulation, Vref = 640 mV, T = -40 �C to +85 �C, Buffer - Enable................................................188 Figure 199: Typical Load Regulation, Vref = 1280 mV, T = -40 �C to +85 �C, Buffer - Enable..............................................189 Figure 200: Typical Load Regulation, Vref = 2048 mV, T = -40 �C to +85 �C, Buffer - Enable..............................................189 Figure 201: Oscillator0 Block Diagram...................................................................................................................................191 Figure 202: Oscillator1 Block Diagram...................................................................................................................................192 Figure 203: Oscillator2 Block Diagram...................................................................................................................................193 Figure 204: Clock Scheme.....................................................................................................................................................194 Figure 205: Oscillator Startup Diagram ..................................................................................................................................195 Figure 206: OSC0 Maximum Power-On Delay vs. VDD at T = 25 �C, OSC0 = 2.048 kHz ....................................................195 Figure 207: OSC1 Oscillator Maximum Power-On Delay vs. VDD at T = 25 �C, OSC1 = 2.048 MHz....................................196 Figure 208: OSC2 Maximum Power-On Delay vs. VDD at T = 25 �C, OSC2 = 25 MHz.........................................................196 Figure 209: OSC0 Frequency vs. Temperature, OSC0 = 2.048 kHz .....................................................................................197 Figure 210: OSC1 Frequency vs. Temperature, OSC1 = 2.048 MHz....................................................................................197 Figure 211: OSC2 Frequency vs. Temperature, OSC2 = 25 MHz.........................................................................................198 Figure 212: Oscillators Total Error vs. Temperature ..............................................................................................................198 Figure 213: Oscillator0 Settling Time, VDD = 3.3 V, T = 25 �C, OSC0 = 2 kHz......................................................................199 Figure 214: Oscillator1 Settling Time, VDD = 3.3 V, T = 25 �C, OSC1 = 2 MHz ....................................................................199 Figure 215: Oscillator2 Settling Time, VDD = 3.3 V, T = 25 �C, OSC2 = 25 MHz (Normal Start) ...........................................200 Figure 216: Oscillator2 Settling Time, VDD = 3.3 V, T = 25 �C, OSC2 = 25 MHz (Start with Delay) ......................................200 Figure 217: OSC1 Current Consumption vs. VDD (Pre-Divider = 1).......................................................................................201 Figure 218: OSC1 Current Consumption vs. VDD (Pre-Divider = 4).......................................................................................202 Figure 219: OSC1 Current Consumption vs. VDD (Pre-Divider = 8).......................................................................................202 Figure 220: OSC2 Current Consumption vs. VDD (Pre-Divider = 1).......................................................................................203 Figure 221: OSC2 Current Consumption vs. VDD (Pre-Divider = 4).......................................................................................203 Figure 222: OSC2 Current Consumption vs. VDD (Pre-Divider = 8).......................................................................................204 Figure 223: POR Sequence ...................................................................................................................................................206 Figure 224: Internal Macrocell States During POR Sequence ...............................................................................................207 Figure 225: Power-Down........................................................................................................................................................208 Figure 226: Basic Command Structure ..................................................................................................................................209
Datasheet
CFR0011-120-00
Revision 2.3 8 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Figure 227: I2C General Timing Characteristics.....................................................................................................................210 Figure 228: Byte Write Command, R/W = 0...........................................................................................................................210 Figure 229: Sequential Write Command ................................................................................................................................211 Figure 230: Current Address Read Command, R/W = 1........................................................................................................211 Figure 231: Random Read Command ...................................................................................................................................212 Figure 232: Sequential Read Command ................................................................................................................................212 Figure 233: Reset Command Timing .....................................................................................................................................213 Figure 234: Example of I2C Byte Write Bit Masking...............................................................................................................219 Figure 235: Page Write Command.........................................................................................................................................221 Figure 236: I2C Block Addressing ..........................................................................................................................................222 Figure 237: Analog Temperature Sensor Structure Diagram.................................................................................................226 Figure 238: TS Output vs. Temperature, VDD = 3.3 V ...........................................................................................................227
Datasheet
CFR0011-120-00
Revision 2.3 9 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Tables
Table 1: Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2: Pin Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4: Electrostatic Discharge Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 6: EC at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . . . . . . . . . . . . . . . . . . . . 17 Table 7: EC of the I2C Pins at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . . . . . . . . . . . . 22 Table 8: I2C Pins Timing Characteristics at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted. . . . . . 23 Table 9: Typical Current Estimated for Each Macrocell at T = 25�C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 10: Typical Delay Estimated for Each Macrocell at T = 25 �C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 11: Programmable Delay Expected Typical Delays and Widths at T = 25 �C . . . . . . . . . . . . . . . . . . . . . 25 Table 12: Typical Filter Rejection Pulse Width at T = 25 �C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 13: Typical Counter/Delay Offset Measurements at T = 25 �C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 14: Oscillators Frequency Limits, VDD = 2.4 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 15: Oscillators Power-On Delay at T = 25 �C, OSC Power Setting: "Auto Power-On" . . . . . . . . . . . . . . . . . 27 Table 16: ACMP Specifications at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . . . . . . . . . . 27 Table 17: Internal Vref Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 18: HD Buffer Electrical Characteristics at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . . . 28 Table 19: Vref0 Output Buffer at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . . . . . . . . . . . 28 Table 20: TS Output vs Temperature (Output Range 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 21: TS Output vs Temperature (Output Range 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 22: EC of OA, VDDA = 2.4 V to 5.5 V, VCM = VDDA/2, VOUT VDDA/2, RL = 100 k to VDDA/2, CL = 50 pF, T = 25 �C 30 Table 23: 100K Digital Rheostat EC at VA=VDD, VB=GND, T=-40�C to +85�C, VDD= 2.4V to 5.5V Unless Otherwise Noted33 Table 24: Analog Switch0/Voltage Regulator E at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . 35 Table 25: Analog Switch1/Current Sink E at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted . . . . 35 Table 26: Matrix Input Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 27: Matrix Output Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 28: Connection Matrix Virtual Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 29: 2-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 30: 2-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 31: 2-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 32: 2-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 33: 2-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 34: 2-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 35: 3-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 36: 3-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 37: 3-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 38: 3-bit LUT3 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 39: 3-bit LUT4 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 40: 3-bit LUT5 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 41: 3-bit LUT6 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 42: 3-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 43: 4-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 44: 4-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 45: 3-bit LUT13 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 46: 3-bit LUT7 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 47: 3-bit LUT8 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 48: 3-bit LUT9 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 49: 3-bit LUT10 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 50: 3-bit LUT11 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 51: 3-bit LUT12 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 52: 4-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 53: 4-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 54: Op Amp Bandwidth Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 55: Analog Switch 0 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 56: Analog Switch 1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 57: Vref Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Table 58: Oscillator Operation Mode Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 59: RPR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Table 60: RPR Bit Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Table 61: NPR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Datasheet
CFR0011-120-00
Revision 2.3 10 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 62: NPR Bit Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 63: Read/Write Register Protection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 64: Erase Register Bit Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Table 65: Erase Register Bit Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Table 66: Write/Erase Protect Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Table 67: Write/Erase Protect Register Bit Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Table 68: Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Datasheet
CFR0011-120-00
Revision 2.3 11 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
1 Block Diagram
Preliminary
AGND
OA1-
OA1+
OA1_OUT
IO7
IO6
VDDA
1024 Position Rheostat
1024 Position Rheostat
Programmable Trim Block
HD Buffer
2.048 kHz
Oscillators
2.048 MHz
25 MHz
In-System Programmability
Multiple Time Programmable
Memory
2K bits EEPROM Emulation
IO5
Combination Function Macrocells
OA0+
ACMP0L
ACMP1L
Chopper ACMP
2-bit LUT2_0 or DFF0
2-bit LUT2_1 or DFF1
2-bit LUT2_2 or DFF2
2-bit LUT2_3 or PGen
IO4
OA0-
Prog, OA0
Int. OA OA0_OUT
Prog, OA1
3bit
3-bit
3-bit
3-bit
LUT3_0
LUT3_1
LUT3_2
LUT3_3
or DFF3
or DFF4
or DFF5
or DFF6
IO3
3-bit LUT3_4 or DFF7
3-bit LUT3_5 or DFF8
3-bit LUT3_6 or DFF9
4-bit LUT4_0 or DFF10
3-bit LUT3_13
IO2
or Pipe Delay
or Ripple CNT
RH0_A RH0_B
Low Power Vref
Temperature Sensor
Analog Switch 0/ Voltage Regulator Mode
Analog Switch 1/ Current Sink Mode
3-bit LUT3_7 /DFF11 +8bit
CNT/DLY1
Multi-Function Macrocells
3-bit LUT3_8 /DFF12 +8bit
CNT/DLY2
3-bit LUT3_9 /DFF13 +8bit
CNT/DLY3
3-bit LUT3_10 /DFF14 +8bit
CNT/DLY4
3-bit LUT3_11 /DFF15 +8bit
CNT/DLY5
3-bit LUT3_12 /DFF16 +8bit
CNT/DLY6
4-bit LUT4_1 /DFF17+ 16bit CNT/DLY0
IO1 VDD
I2C Serial Communication
Programmable Delay or Edge
Detect
RH1_A
RH1_B
SCL
Filter with Edge Detect
POR
SDA
IO0
GND
Figure 1: Block Diagram
Datasheet
CFR0011-120-00
Revision 2.3 12 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
2 Pinout
2.1 PIN CONFIGURATION - STQFN-24L
OA1OA1+ OA1_OUT I0 IO6 IO5
VDDA AGND
OA0OA0+ OA0_OUT RH0_A
24 1
23
22
21
20
19 18
2
17
3
16
4
15
5
14
6
13
7 8 9 10 11 12
IO4 IO3 IO2 IO1 GND VDD
RH0_B RH1_A RH1_B
SCL SDA IO0
STQFN-24 (Top View)
Pin # Signal Name Pin Functions
1
VDDA Analog Power Supply
2
AGND Analog Ground
3
OA0- Op Amp0 Inverting Input
4
OA0+ Op Amp0 Non-Inverting Input
5 OA0_OUT Op Amp0_OUT/ACMP0L+ /
6
RH0_A Digital Rheostat 0 Terminal A
7
RH0_B Digital Rheostat 0 Terminal B
8
RH1_A Digital Rheostat 1 Terminal A
9
RH1_B Digital Rheostat 1 Terminal B
10
SCL
I2C_SCL
11
SDA
I2C_SDA
GPIO, ACMP0L-, ACMP1L-, EXT_OSC0_IN,
12
IO0
Vref0_Out or Temp_Sens_Out
13
VDD Digital Power Supply
14
GND Digital Ground
15
IO1
GPIO, Chop_ACMP+, Vref1_OUT or Temp_Sens_Out, EXT_OSC1_IN or SLA_0
16
IO2
GPIO, ACMP0L+, EXT_OSC2_IN, SLA_1
17
IO3
GPIO, AS_1_A, ACMP1L+ or SLA_2
18
IO4
GPIO, AS_1_B, Chop_ACMP-or SLA_3
19
IO5
GPIO, AS_0_B
20
IO6
GPIO, AS_0_A, HD_Buff_Out, In Amp_Vref
21
I0
GPI, In Amp_OUT
22 OA1_OUT Op Amp1_OUT, ACMP1L+
23
OA1+ Op Amp1 Non-inverting Input
24
OA1- Op Amp1 Inverting Input
Legend:
ACMPx+: ACMPx Positive Input ACMPx-: ACMPx Negative Input SCL: I2C Clock Input SDA: I2C Data Input/Output Vrefx: Voltage Reference Output SLA: Slave Address
Table 1: Functional Pin Description
Pin No.
STQFN 24L 1 2
Pin Name
VDDA AGND
Signal Name
VDDA AGND
3
OA0-
OA0-
4
OA0+
OA0+
OA0_OUT
5
OA0_OUT
ACMP0L+
6
RH0_A
RH0_A
Datasheet
CFR0011-120-00
Function
Analog Power Supply Analog Ground Op Amp0 Inverting Input Op Amp0
Non-Inverting Input Op Amp0 Output
Analog Comparator 0 Positive Input
Digital Rheostat 0 Terminal A
Revision 2.3
13 of 292
Input Options
--Analog
Analog --
Analog
--
Output Options
----
-Analog
--
--
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 1: Functional Pin Description(Continued)
Pin No. STQFN 24L
7 8 9 10 11
12 13 14
15
16
17
18
Pin Name
RH0_B
Signal Name
RH0_B
RH1_A
RH1_A
RH1_B
SCL SDA
RH1_B
SCL SDA IO0
ACMP0L-
IO0
VDD GND
ACMP1L-
EXT_OSC0_IN
Vref0_Out VDD GND IO1
CHOP_ACMP+
IO1
Temp_Sens_Out
EXT_OSC1_IN
SLA_0
IO2
ACMP0L+
IO2
EXT_OSC2_IN
SLA_1
IO3 AS_1_A
IO3
ACMP1L+
SLA_2
IO4 AS_1_B IO4
SLA_3
Function
Digital Rheostat 0 Terminal B
Digital Rheostat 1 Terminal A
Digital Rheostat 1 Terminal B
I2C Serial Clock I2C Serial Data General Purpose IO Analog Comparator 0 Negative Input Analog Comparator 1 Negative Input External Clock
Connection Voltage Reference 0 Output
Digital Power Supply Digital Ground
General Purpose IO Chopper ACMP Positive Input
Temperature Sensor Output External Clock Connection Slave Address 0
General Purpose IO Analog Comparator 0
Positive Input External Clock
Connection Slave
Address 1 General Purpose IO Analog Switch 1Input A Analog Comparator 1
Positive Input Slave
Address 2 General Purpose IO Analog Switch 1 Input B
Chopper ACMP Negative Input
Slave Address 3
Input Options
--
--
----Analog
Analog
-----Analog ---
--Analog
--
--Analog --
--Analog Analog
--
Preliminary
Output Options
--
--
------
--
-Analog
----Analog --
----
--
--Analog --
--Analog --
--
Datasheet
CFR0011-120-00
Revision 2.3 14 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 1: Functional Pin Description(Continued)
Pin No. STQFN 24L
19
20
Pin Name
IO5
IO6
Signal Name
IO5 AS_0_B
IO6 AS_0_A HD_Buffer_Out
In Amp_Vref
I0
21
I0
In Amp Out
OA1_OUT
22
OA1_OUT
ACMP1L+
23
OA1+
OA1+
24
OA1-
OA1-
Function
General Purpose IO Analog Switch 0 Input B
General Purpose IO Analog Switch 0 Input A High Drive Buffer Out put
Instrumentation Amplifier
Voltage Reference General Purpose Input
Instrumentation Amplifier Output Op Amp1 Output Analog Comparator 1
Positive Input Op Amp1
Non-inverting Input Op Amp1
Inverting Input
Input Options
-Analog
-Analog
--
Analog
-Analog
-Analog
Analog
Analog
Table 2: Pin Type Definitions
Pin Type VDDA AGND OAOA+ OA_OUT RH_A RH_B SCL SDA IO VDD GND I
Description Analog Power Supply Analog Ground Op Amp Inverting Input Op Amp Non-Inverting Input Op Amp Output Digital Rheostat Terminal A Digital Rheostat Terminal B I2C Serial Clock I2C Serial Data General Purpose Input/Output Digital Power Supply Digital Ground General Purpose Input
Preliminary
Output Options
-Analog
-Analog Analog
---Analog ----
Datasheet
CFR0011-120-00
Revision 2.3 15 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
3 Characteristics
3.1 ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Analog and digital grounds must be connected together on the PCB board. The place of connection depends on users schematic. For application cases with low digital current of SLG47004, both AGND and GND should be connected to analog ground plane.
Table 3: Absolute Maximum Ratings
Parameter
VDD to GND, VDDA to AGND (Note 1) Maximum Slew Rate of VDDA Voltage at Input Pin
Current at Input Pin
Maximum Average or DC Current through VDDA or AGND Pin (Per chip side)
TJ = 85 �C TJ = 110�C
Maximum Average or DC Current through VDD or GND Pin (Per chip side)
TJ = 85 �C TJ = 110�C
Input leakage (Absolute Value)
Storage Temperature Range
Junction Temperature
Thermal Resistance (Note 2)
Moisture Sensitivity Level
Note 1 VDDA must be equal to VDD Note 2 Measurements based on Analog Switches
Min
Max
-0.3
7
--
2
GND-0.3 -1.0
VDD+0.3 1.0
--
110
--
50
--
100
--
50
--
1000
-65
150
--
150
--
132
1
Unit V
V/�s V mA mA mA mA mA nA �C �C
�C/W
3.2 ELECTROSTATIC DISCHARGE RATINGS
Table 4: Electrostatic Discharge Ratings
Parameter ESD Protection (Human Body Model) ESD Protection (Charged Device Model)
3.3 RECOMMENDED OPERATING CONDITIONS Table 5: Recommended Operating Conditions Parameter
Condition
Supply Voltage (VDDA)
Operating Temperature Capacitor Value at VDD Analog Input Common Mode Range
During NVM Write and Erase commands Allowable Input Voltage at Analog Pins
Min
Max
Unit
2000
--
V
1300
--
V
Min
Max
Unit
2.4
5.5
V
2.5
5.5
V
-40
85
�C
0.1
--
�F
-0.2
VDDA+0.2
V
Datasheet
CFR0011-120-00
Revision 2.3 16 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
3.4 ELECTRICAL CHARACTERISTICS
Table 6: EC at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter Description
Condition
Logic Input (Note 1)
VIH
HIGH-Level Input Voltage Logic Input with Schmitt Trigger
Low-Level Logic Input (Note 1)
Logic Input (Note 1)
VIL VHYS
VO
VOH
LOW-Level Input Voltage Logic Input with Schmitt Trigger
Low-Level Logic Input (Note 1)
Schmitt Trigger Hysteresis Voltage Maximal Voltage Applied to any PIN in High Impedance State
HIGH-Level Output Voltage
VDD = 2.5 V +/- 8 % (Note 1) VDD = 3.3 V +/- 10 % (Note 1) VDD = 5 V +/- 10 % (Note 1)
Push-Pull, 1x Drive, IOH = 1 mA, VDD = 2.4 V (Note 1) Push-Pull, 1x Drive, IOH = 1 mA, VDD = 2.5 V (Note 1) Push-Pull, 1x Drive, IOH = 1 mA, VDD = 2.7 V (Note 1) Push-Pull, 1x Drive, IOH = 3 mA, VDD = 3.0 V (Note 1) Push-Pull, 1x Drive, IOH = 3 mA, VDD = 3.3 V (Note 1) Push-Pull, 1x Drive, IOH = 3 mA, VDD = 3.6 V (Note 1) Push-Pull, 1x Drive, IOH = 5 mA, VDD = 4.5 V (Note 1) Push-Pull, 1x Drive, IOH = 5 mA, VDD = 5.0 V (Note 1) Push-Pull, 1x Drive, IOH = 5 mA, VDD = 5.5 V (Note 1) Push-Pull, 2x Drive, IOH = 1 mA, VDD = 2.4 V (Note 1) Push-Pull, 2x Drive, IOH = 1 mA, VDD = 2.5 V (Note 1) Push-Pull, 2x Drive, IOH = 1 mA, VDD = 2.7 V (Note 1) Push-Pull, 2x Drive, IOH = 3 mA, VDD = 3.0 V (Note 1) Push-Pull, 2x Drive, IOH = 3 mA, VDD = 3.3 V (Note 1) Push-Pull, 2x Drive, IOH = 3 mA, VDD = 3.6 V (Note 1)
Min 0.7x VDD 0.8x VDD 1.25 GND0.3 GND0.3 GND0.3 0.28 0.34 0.50
--
2.178
2.389
2.598
2.712
3.039
3.36
4.157
4.678
5.201
2.239
2.443
2.648
2.854
3.165
3.474
Preliminary
Typ --
----
--
-0.43 0.46 0.63
--
Max Unit VDD+ 0.3 V
VDD+ 0.3 V
VDD+ 0.3 V
0.3x VDD
V
0.2x VDD
V
0.5
V
0.54
V
0.56
V
0.74
V
VDD+ 0.3
V
--
--
V
--
--
V
--
--
V
--
--
V
--
--
V
--
--
V
--
--
V
--
--
V
--
--
V
--
--
V
--
--
V
--
--
V
--
--
V
--
--
V
--
--
V
Datasheet
CFR0011-120-00
Revision 2.3 17 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 6: EC at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter VOH
VOL
Description HIGH-Level Output Voltage
LOW-Level Output Voltage
Condition
Push-Pull, 2x Drive, IOH = 5 mA, VDD = 4.5 V (Note 1) Push-Pull, 2x Drive, IOH = 5 mA, VDD = 5.0 V (Note 1) Push-Pull, 2x Drive, IOH = 5 mA, VDD = 5.5 V (Note 1) Push-Pull, 1x Drive, IOL= 1 mA, VDD = 2.4 V (Note 1) Push-Pull, 1x Drive, IOL= 1 mA, VDD = 2.5 V (Note 1) Push-Pull, 1x Drive, IOL= 1 mA, VDD = 2.7 V (Note 1) Push-Pull, 1x Drive, IOL = 3 mA, VDD = 3.0 V (Note 1) Push-Pull, 1x Drive, IOL = 3 mA, VDD = 3.3 V (Note 1) Push-Pull, 1x Drive, IOL = 3 mA, VDD = 3.6 V (Note 1) Push-Pull, 1x Drive, IOL= 5 mA, VDD = 4.5 V (Note 1) Push-Pull, 1x Drive, IOL= 5 mA, VDD = 5.0 V (Note 1) Push-Pull, 1x Drive, IOL= 5 mA, VDD = 5.5 V (Note 1) Push-Pull, 2x Drive, IOL= 1 mA, VDD = 2.4 V (Note 1) Push-Pull, 2x Drive, IOL = 1 mA, VDD = 2.5 V (Note 1) Push-Pull, 2x Drive, IOL = 1 mA, VDD = 2.7 V (Note 1) Push-Pull, 2x Drive, IOL= 3 mA, VDD = 3.0 V (Note 1) Push-Pull, 2x Drive, IOL= 3 mA, VDD = 3.3 V (Note 1) Push-Pull, 2x Drive, IOL= 3 mA, VDD = 3.6 V (Note 1) Push-Pull, 2x Drive, IOL = 5 mA, VDD = 4.5 V (Note 1) Push-Pull, 2x Drive, IOL = 5 mA, VDD = 5.0 V (Note 1) Push-Pull, 2x Drive, IOL = 5 mA, VDD = 5.5 V (Note 1) NMOS OD, 1x Drive, IOL= 1 mA, VDD = 2.4 V (Note 1) NMOS OD, 1x Drive, IOL = 1 mA, VDD = 2.5 V (Note 1) NMOS OD, 1x Drive, IOL = 1 mA, VDD = 2.7 V (Note 1) NMOS OD, 1x Drive, IOL = 3 mA, VDD = 3.0 V (Note 1)
Min 4.314 4.821 5.329
-----------------------
Datasheet
CFR0011-120-00
Revision 2.3 18 of 292
Typ
Max Unit
--
--
V
--
--
V
--
--
V
--
0.085
V
--
0.079
V
--
0.074
V
--
0.210
V
--
0.195
V
--
0.183
V
--
0.271
V
--
0.256
V
--
0.246
V
--
0.046
V
--
0.043
V
--
0.040
V
--
0.114
V
--
0.107
V
--
0.102
V
--
0.152
V
--
0.145
V
--
0.140
V
--
0.038
V
--
0.035
V
--
0.033
V
--
0.094
V
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 6: EC at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter VOL
IOH
Description LOW-Level Output Voltage
HIGH-Level Output Current (Note 2)
Condition
NMOS OD, 1x Drive, IOL = 3 mA, VDD = 3.3 V (Note 1) NMOS OD, 1x Drive, IOL = 3 mA, VDD = 3.6 V (Note 1) NMOS OD, 1x Drive, IOL = 5 mA, VDD = 4.5 V (Note 1) NMOS OD, 1x Drive, IOL = 5 mA, VDD = 5.0 V (Note 1) NMOS OD, 1x Drive, IOL = 5 mA, VDD = 5.5 V (Note 1) NMOS OD, 2x Drive, IOL= 1 mA, VDD2 = 2.4 V (Note 1) NMOS OD, 2x Drive, IOL = 1 mA, VDD = 2.5 V (Note 1) NMOS OD, 2x Drive, IOL = 1 mA, VDD = 2.7 V (Note 1) NMOS OD, 2x Drive, IOL = 3 mA, VDD = 3.0 V (Note 1) NMOS OD, 2x Drive, IOL = 3 mA, VDD = 3.3 V (Note 1) NMOS OD, 2x Drive, IOL = 3 mA, VDD = 3.6 V (Note 1) NMOS OD, 2x Drive, IOL = 5 mA, VDD = 4.5 V (Note 1) NMOS OD, 2x Drive, IOL = 5 mA, VDD = 5.0 V (Note 1) NMOS OD, 2x Drive, IOL = 5 mA, VDD = 5.5 V (Note 1) Push-Pull, 1x Drive, VOH = VDD - 0.2 VDD = 2.4 V (Note 1) Push-Pull, 1x Drive, VOH = VDD - 0.2 VDD = 2.5 V (Note 1) Push-Pull, 1x Drive, VOH = VDD - 0.2 VDD = 2.7 V (Note 1) Push-Pull, 1x Drive, VOH = 2.4 V, VDD = 3.0 V (Note 1) Push-Pull, 1x Drive, VOH = 2.4 V, VDD = 3.3 V (Note 1) Push-Pull, 1x Drive, VOH = 2.4 V, VDD = 3.6 V (Note 1) Push-Pull, 1x Drive, VOH = 2.4 V, VDD = 4.5 V (Note 1) Push-Pull, 1x Drive, VOH = 2.4 V, VDD = 5.0 V (Note 1) Push-Pull, 1x Drive, VOH = 2.4 V, VDD = 5.5 V (Note 1) Push-Pull, 2x Drive, VOH = VDD - 0.2 VDD = 2.4 V (Note 1) Push-Pull, 2x Drive, VOH = VDD - 0.2 VDD = 2.5 V (Note 1)
Min ---------------
1.60 1.76 1.92 5.64 8.56 11.51 20.46 25.12 29.34 3.10 3.40
Datasheet
CFR0011-120-00
Revision 2.3 19 of 292
Typ
Max Unit
--
0.088
V
--
0.084
V
--
0.127
V
--
0.121
V
--
0.117
V
--
0.032
V
--
0.03
V
--
0.029
V
--
0.064
V
--
0.062
V
--
0.059
V
--
0.085
V
--
0.081
V
--
0.08
V
--
--
mA
--
--
mA
--
--
mA
--
--
mA
--
--
mA
--
--
mA
--
--
mA
--
--
mA
--
--
mA
--
--
mA
--
--
mA
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 6: EC at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter IOH
IOL
Description HIGH-Level Output Current (Note 2)
LOW-Level Output Current (Note 2)
Condition
Push-Pull, 2x Drive, VOH = VDD - 0.2 VDD = 2.7 V (Note 1) Push-Pull, 2x Drive, VOH = 2.4 V, VDD = 3.0 V (Note 1) Push-Pull, 2x Drive, VOH = 2.4 V, VDD = 3.3 V (Note 1) Push-Pull, 2x Drive, VOH = 2.4 V, VDD = 3.6 V (Note 1) Push-Pull, 2x Drive, VOH = 2.4 V, VDD = 4.5 V (Note 1) Push-Pull, 2x Drive, VOH = 2.4 V, VDD = 5.0 V (Note 1) Push-Pull, 2x Drive, VOH = 2.4 V, VDD = 5.5 V (Note 1) Push-Pull, 1x Drive, VOL = 0.15 V, VDD = 2.4 V (Note 1) Push-Pull, 1x Drive, VOL = 0.15 V, VDD = 2.5 V (Note 1) Push-Pull, 1x Drive, VOL = 0.15 V, VDD = 2.7 V (Note 1) Push-Pull, 1x Drive, VOL = 0.4 V, VDD = 3.0 V (Note 1) Push-Pull, 1x Drive, VOL = 0.4 V, VDD = 3.3 V (Note 1) Push-Pull, 1x Drive, VOL = 0.4 V, VDD = 3.6 V (Note 1) Push-Pull, 1x Drive, VOL = 0.4 V, VDD = 4.5 V (Note 1) Push-Pull, 1x Drive, VOL = 0.4 V, VDD = 5.0 V (Note 1) Push-Pull, 1x Drive, VOL = 0.4 V, VDD = 5.5 V (Note 1) Push-Pull, 2x Drive, VOL = 0.15 V, VDD = 2.4 V (Note 1) Push-Pull, 2x Drive, VOL = 0.15 V, VDD = 2.5 V (Note 1) Push-Pull, 2x Drive, VOL = 0.15 V, VDD = 2.7 V (Note 1) Push-Pull, 2x Drive, VOL = 0.4 V, VDD = 3.0 (Note 1) Push-Pull, 2x Drive, VOL = 0.4 V, VDD = 3.3 (Note 1) Push-Pull, 2x Drive, VOL = 0.4 V, VDD = 3.6 (Note 1) Push-Pull, 2x Drive, VOL = 0.4 V, VDD = 4.5 (Note 1) Push-Pull, 2x Drive, VOL = 0.4 V, VDD = 5.0 (Note 1)
Min
Typ
3.69
--
10.89
--
16.54
--
22.28
--
39.61
--
48.49
--
56.39
--
1.73
--
1.87
--
2.00
--
5.45
--
5.90
--
6.29
--
7.25
--
7.67
--
8.01
--
3.20
--
3.44
--
3.65
--
10.01
--
10.73
--
11.36
--
12.85
--
13.52
--
Preliminary
Max Unit
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
Datasheet
CFR0011-120-00
Revision 2.3 20 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 6: EC at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter
IOL
TSU TWR TER PONTHR POFFTHR
Description
LOW-Level Output Current (Note 2)
Startup Time NVM Page Write Time NVM Page Erase Time Power-On Threshold Power-Off Threshold
Condition
Push-Pull, 2x Drive, VOL = 0.4 V, VDD = 5.5 (Note 1) NMOS OD, 1x Drive, VOL = 0.15 V, VDD = 2.4 V (Note 1) NMOS OD, 1x Drive, VOL = 0.15 V, VDD = VDD2 = 2.5 V (Note 1) NMOS OD, 1x Drive, VOL = 0.15 V, VDD = 2.7 V (Note 1) NMOS OD, 1x Drive, VOL = 0.4 V, VDD = 3.0 V (Note 1) NMOS OD, 1x Drive, VOL = 0.4 V, VDD = 3.3 V (Note 1) NMOS OD, 1x Drive, VOL = 0.4 V, VDD = 3.6 V (Note 1) NMOS OD, 1x Drive, VOL = 0.4 V, VDD = 4.5 V (Note 1) NMOS OD, 1x Drive, VOL = 0.4 V, VDD = 5.0 V (Note 1) NMOS OD, 1x Drive, VOL = 0.4 V, VDD = 5.5 V (Note 1) NMOS OD, 2x Drive, VOL = 0.15 V, VDD = 2.4 V (Note 1) NMOS OD, 2x Drive, VOL = 0.15 V, VDD = 2.5 V (Note 1) NMOS OD, 2x Drive, VOL = 0.15 V, VDD = 2.7 V (Note 1) NMOS OD, 2x Drive, VOL = 0.4 V, VDD = 3.0 V (Note 1) NMOS OD, 2x Drive, VOL = 0.4 V, VDD = 3.3 V (Note 1) NMOS OD, 2x Drive, VOL = 0.4 V, VDD = 3.6 V (Note 1) NMOS OD, 2x Drive, VOL = 0.4 V, VDD = 4.5 V (Note 1) NMOS OD, 2x Drive, VOL = 0.4 V, VDD = 5.0 V (Note 1) NMOS OD, 2x Drive, VOL = 0.4 V, VDD = 5.5 V (Note 1) From VDD rising past PONTHR VDD = 2.5 V to 5.5 V VDD = 2.5 V to 5.5 V VDD Level Required to Start Up the Chip VDD Level Required to Switch Off the Chip
Min 14.05 3.91 4.19 4.44 12.18 13.02 13.75 15.47 16.19 16.80 6.28 6.68 7.02 20.14 21.23 22.12 24.84 26.08 26.72
---1.60 0.97
Typ --------------------
1.904 -----
Max Unit
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
--
mA
2.651 ms
20
ms
20
ms
2.07
V
1.531
V
Datasheet
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� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 6: EC at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
RPULL
Pull-up or Pull-down Resistance
1 M for Pull-up: VIN = GND; for Pull-down: VIN = VDD (Note 1) 100 k for Pull-up: VIN = GND; for Pull-down: VIN = VDD (Note 1) 10 k For Pull-up: VIN = GND; for Pull-down: VIN = VDD (Note 1) PINs 10, 11
0.72
1.12
1.4
72
110
134.4
6.32
10
13.5
--
2.905
--
PIN 12
--
3.476
--
CIN
Input Capacitance
PINs 15, 16 PINs 17, 18, 19
--
3.677
--
--
10.228
--
PIN 20
--
27.964
--
PIN 21
--
5.671
--
Note 1 No hysteresis. Note 2 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
3.5 I2C PINS ELECTRICAL CHARACTERISTICS
Table 7: EC of the I2C Pins at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter Description
Condition
Fast-Mode
Min
Max
Fast-Mode Plus
Min
Max
VIL
LOW-level Input Voltage
-0.5
0.3xVDD
-0.5
0.3xVDD
VIH
HIGH-level Input Voltage
0.7xVDD
5.5
0.7xVDD
5.5
VHYS
Hysteresis of Schmitt Trigger Inputs
0.05xVDD
--
0.05xVDD
--
VOL1 VOL2 IOL
tof
LOW-Level Output Voltage 1 LOW-Level Output Voltage 2
LOW-Level Output Current (Note 1) Output Fall Time from VIHmin to VILmax (Note 1)
(Open-Drain) at 3 mA sink current VDD > 2 V (Open-Drain) at 2 mA sink current VDD 2 V VOL = 0.4 V, VDD = 2.4 V VOL = 0.4 V, VDD = 3.0 V VOL = 0.4 V, VDD = 4.5 V VOL= 0.6 V
0
0
3 3 3 6 14x (VDD/5.5 V)
0.4
0.2xVDD -----
250
0
0
16.75 20 20 -10x
(VDD/5.5 V)
0.4
0.2xVDD -----
120
Pulse Width of Spikes
tSP
that must be suppressed by the
Input Filter
0
50
0
50
Ii
Input Current (each IO Pin)
0.1xVDD < VI < 0.9xVDDmax
-10
+10
-10
+10
Ci
Capacitance (each IO Pin)
--
10
--
10
Unit M k k pF pF pF pF pF pF
Unit V V V
V
V mA mA mA mA ns
ns
�A pF
Datasheet
CFR0011-120-00
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� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 7: EC of the I2C Pins at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Fast-Mode
Min
Max
Fast-Mode Plus
Unit
Min
Max
Note 1 Does VOL = 0.4 V.
not
meet
standard
I2C
specifications:
tof
=
20x(VDD/5.5
V)
(min);
For
Fast-mode
Plus
IOL
=
20
mA
(min)
at
Note 2 For Fast-mode Plus SDA pin must be configured as NMOS 2x Open-Drain, see register [1155] in Section 21.
Table 8: I2C Pins Timing Characteristics at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter Description
Condition
Fast-Mode Min Max
Fast-Mode Plus
Min Max
FSCL tLOW tHIGH
tI
Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Input Filter Spike Suppression (SCL, SDA)
--
400
1300
--
600
--
--
50
--
1000
500
--
260
--
--
50
tAA
Clock Low to Data Out Valid
tBUF
Bus Free Time between Stop and Start
--
900
--
450
1300
--
500
--
tHD_STA Start Hold Time
tSU_STA Start Set-up Time
tHD_DAT Data Hold Time
tSU_DAT Data Set-up Time
tR
Inputs Rise Time
tF
Inputs Fall Time
tSU_STD Stop Set-up Time
tDH
Data Out Hold Time
Note 1 Timing diagram can be found in Figure 227.
600
--
260
--
600
--
260
--
0
--
0
--
100
--
50
--
--
300
--
120
--
300
--
120
600
--
260
--
50
--
50
--
Unit
kHz ns ns
ns
ns
ns
ns ns ns ns ns ns ns ns
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
3.6 MACROCELLS CURRENT CONSUMPTION
Table 9: Typical Current Estimated for Each Macrocell at T = 25�C
Parameter Description Note Chip Quiescent, BG disabled
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
0.056
0.079
0.13
Unit �A
Chip Quiescent, BG enabled
0.357
0.391
0.472
�A
OSC2 25 MHz, pre-divider = 1
40.954
49.907
71.075
�A
OSC2 25 MHz, pre-divider = 4
31.716
37.448
51.515
�A
OSC2 25 MHz, pre-divider = 8
29.897
34.998
47.664
�A
OSC1 2.048 MHz, pre-divider = 1
18.951
19.751
21.507
�A
OSC1 2.048 MHz, pre-divider = 4
18.255
18.809
20.023
�A
OSC1 2.048 MHz, pre-divider = 8
18.116
18.622
19.730
�A
OS00 2.048 kHz, pre-divider = 1
0.330
0.363
0.443
�A
OSC0 2.048 kHz, pre-divider = 4
0.327
0.359
0.437
�A
OSC0 2.048 kHz, pre-divider = 8
0.326
0.359
0.436
�A
Push-Pull 1x + 4 pF @ 2.048 kHz
0.384
0.436
0.554
�A
Push-Pull 1x + 4 pF @ 2.048 MHz
66.582
82.354
115.785
�A
Temperature Sensor, range 1
11.001
11.050
11.356
�A
Temperature Sensor, range 2
11.140
11.188
11.493
�A
One ACMPx_L (includes internal Vref)
6.198
6.260
6.484
�A
Two ACMPx_L (includes internal Vref)
8.530
8.616
8.954
�A
I
Current Op AmpX Quiescent Current
(128 kHz bandwidth)
31.663
32.227
33.005
�A
Op AmpX Quiescent Current (8.192 MHz bandwidth)
604.144 607.979 609.342
�A
In Amp Quiescent Current (three Op
Amps are ON, Rf1 = Rf2 = 50 k, Rg =1 k, 128 kHz bandwidth, Charge
95.33
97.105
99.895
�A
Pump - Disabled)
In Amp Quiescent Current (three Op
Amps are ON, Rf1 = Rf2 = 50 k, Rg =1 k, 128 kHz bandwidth, Charge
72.352
73.973
76.688
�A
Pump - Enabled)
In Amp Quiescent Current (three Op
Amps are ON, Rf1 = Rf2 = 50 k, Rg =1 k, 8.192 MHz bandwidth,
1810.631 1821.938 1826.541
�A
Charge Pump - Disabled)
In Amp Quiescent Current (three Op
Amps are ON, Rf1 = Rf2 = 50 k, Rg =1 k, 8.192 MHz bandwidth,
1229.011 1236.282 1241.784
�A
Charge Pump - Enabled)
Chopper ACMP (with 2.048 kHz clock)
31.719
33.940
38.717
�A
Datasheet
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� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
3.7 TIMING CHARACTERISTICS
Table 10: Typical Delay Estimated for Each Macrocell at T = 25 �C
Parameter Description Conditions
tpd
Delay
Digital Input to PP 1x
tpd
Delay
Digital Input with Schmitt Trigger to PP 1x
tpd
Delay
Digital Input to PP 2x
tpd
Delay
Low Voltage Digital input to PP 1x
tpd
Delay
Digital input to NMOS output
tpd
Delay
Output enable from Pin, OE Hi-Z to 1
tpd
Delay
Output enable from Pin, OE Hi-Z to 0
tpd
Delay
Digital input to 1x3-State (Z to 1)
tpd
Delay
Digital input to x3-State (Z to 0)
tpd
Delay
Digital input to 2x3-State (Z to 1)
tpd
Delay
Digital input to 2x3-State (Z to 0)
tpd
Delay
LUT2bt
tpd
Delay
LUT3bit
tpd
Delay
LUT4bit
tpd
Delay
LATCH
tpd
Delay
DFF
tpd
Delay
CNT/DLY
tw
Width
Edge detect
tpd
Delay
Edge detect
tpd
Delay
Edge detect Delayed
tpd
Delay
Ripple Counter
tpd
Delay
PGen
tpd
Delay
Filter
tpd
Delay
Inverter Filter
tpd
Delay
Pipe Delay
VDD = 2.5 V
VDD = 3.3 V
VDD = 5.0 V Unit
Rising Falling Rising Falling Rising Falling
26
27
18
20
13
15 ns
27
28
19
21
15
15 ns
24
25
17
18
12
28
246
20
163
15
--
24
--
18
--
14 ns 95 ns 13 ns
26
--
19
--
13
--
ns
--
26
--
19
--
14 ns
26
--
19
--
13
--
ns
--
26
--
17
--
14 ns
24
--
17
--
13
--
ns
--
24
--
19
--
12 ns
17
17
12
12
8
8
ns
19
20
13
14
9
10 ns
20
21
15
14
9
10 ns
25
25
17
18
12
12 ns
24
25
16
18
11
12 ns
107 107
77
74
48
70 ns
206 205 161 160 116 116 ns
19
20
13
13
8
8
ns
241 241 175 175 125 125 ns
45
60
32
44
22
31 ns
20
20
14
14
9
177 177 121 121
77
10 ns 78 ns
115
115
83
83
57
57 ns
36
37
25
26
17
18 ns
Table 11: Programmable Delay Expected Typical Delays and Widths at T = 25 �C
Parameter Description Note
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V Unit
tw
Pulse Width, 1 cell mode: (any) edge detect, edge detect output
223
163
118
ns
tw
Pulse Width, 2 cell mode: (any) edge detect, edge detect output
444
324
233
ns
tw
Pulse Width, 3 cell mode: (any) edge detect, edge detect output
663
484
347
ns
tw
Pulse Width, 4 cell mode: (any) edge detect, edge detect output
882
643
461
ns
time1
Delay, 1 cell
mode: (any) edge detect, edge detect output
18
12
8
ns
Datasheet
CFR0011-120-00
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� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 11: Programmable Delay Expected Typical Delays and Widths at T = 25 �C (Continued)
Parameter time1 time1 time1 time2 time2 time2 time2
Description Delay, 2 cell Delay, 3 cell Delay, 4 cell Delay, 1 cell Delay, 2 cell Delay, 3 cell Delay, 4 cell
Note
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V Unit
mode: (any) edge detect, edge detect output
18
12
8
ns
mode: (any) edge detect, edge detect output
18
12
8
ns
mode: (any) edge detect, edge detect output
18
12
8
ns
mode: both edge delay, edge detect output
243
176
126
ns
mode: both edge delay, edge detect output
464
337
241
ns
mode: both edge delay, edge detect output
683
497
356
ns
mode: both edge delay, edge detect output
902
655
470
ns
Table 12: Typical Filter Rejection Pulse Width at T = 25 �C
Parameter Filtered Pulse Width
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
< 177
< 122
< 78
Unit ns
Table 13: Typical Counter/Delay Offset Measurements at T = 25 �C
Parameter Power-On time Power-On time Power-On time frequency settling time frequency settling time frequency settling time variable (CLK period) variable (CLK period) variable (CLK period)
tpd (non-delayed edge)
OSC Freq 25 MHz
2.048 MHz 2.048 kHz
25 MHz 2.048 MHz 2.048 kHz
25 MHz 2.048 MHz 2.048 kHz
25 MHz/ 2.048 kHz
OSC Power auto auto auto auto auto auto forced forced forced
either
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
Unit
<0.04
<0.13
<0.13
�s
<0.5
<0.5
<0.5
�s
<500
<500
<500
�s
4
4
4
�s
0.3
0.4
0.4
�s
660
570
480
�s
0-40
0-40
0-40
�s
0-0.5
0-0.5
0-0.5
�s
0-488
0-488
0-488
�s
35
14
10
ns
3.8 OSCILLATOR CHARACTERISTICS
Table 14: Oscillators Frequency Limits, VDD = 2.4 V to 5.5 V
Temperature Range
OSC
2.048 kHz OSC0 2.048 MHz OSC1
25 MHz OSC2
Minimum Value, kHz
2.007
+25 �C Maximum Value, kHz
2.089
2007
2089
24500
25500
Error, %
+2.00 -2.00 +2.00 -2.00 +2.00 -2.00
-40 �C to +85 �C
Minimum Value, kHz
Maximum Value, kHz
1.902
2.110
2003.017
2081.296
23799.64
25900.32
Error, %
+3.03 -7.13 +1.63 -2.20 +3.60 -4.80
Datasheet
CFR0011-120-00
Revision 2.3 26 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
3.8.1 OSC Power-On Delay
Table 15: Oscillators Power-On Delay at T = 25 �C, OSC Power Setting: "Auto Power-On"
Power Supply Range (VDD) V
2.40
2.50
3.30
5.00
5.50
OSC0 2.048 kHz
Typical Value, �s
688.658
Maximum Value, �s
890.850
673.305
862.190
584.854
716.920
494.549
582.281
470.605
549.359
OSC1 2.048 MHz
Typical Value, ns
521.838
Maximum Value, ns
534.426
511.273
524.612
461.524
476.126
417.841
433.196
410.224
425.767
OSC2 25 MHz
Typical Value, ns
47.316
Maximum Value, ns
52.408
44.580
49.272
31.229
34.985
21.331
24.667
19.924
23.143
OSC2 25 MHz Start with Delay
Typical Value, ns
149.854
Maximum Value, ns
156.326
148.574
154.942
143.901
149.772
142.340
147.284
142.158
147.092
3.9 ACMP CHARACTERISTICS
Table 16: ACMP Specifications at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter Description
Conditions
Note
Min Typ Max Unit
VACMP Voffset
ACMP Input Voltage Positive Input
Range
Negative Input
ACMP Input Offset Chopper ACMP Input Offset
ACMPxL, Vhys = 0 mV, Gain = 1, Vref = 32 mV to 2048 mV
0
--
0
--
T = -40 �C to +85 �C -6.364 --
VDD
V
VDD
V
3.709 mV
T = 25 �C
-5.853 -1.025 3.425 mV
T = -40 �C to +85 �C -4.30
--
2.61 mV
T = 25 �C
-2.74 -0.79 1.37 mV
ACMP Startup Time ACMP Power-On delay,
tstart
when BG ON
Minimal required wake time
ACMP Startup Time for the "Wake and Sleep
T = -40 �C to +85 �C
when BG OFF
function", for ACMPxL
---
--
91.02 �s
-- 2797.95 �s
Gain = 1x
--
10
--
G
Rsin
Series Input Resistance
Gain = 0.5x Gain = 0.33x
--
1.627
--
M
--
1.626
--
M
Gain = 0.25x
--
1.625
--
M
PROP
Propagation Delay, Response Time
ACMPxL, Vref =1.024 V, Gain = 1, Overdrive = 100 mV ACMPxL, Vref = 32 mV to 2048 mV, Gain = 1, Overdrive = 100 mV
Low to High High to Low Low to High
High to Low
--
2.593 3.647 �s
--
2.829 5.127 �s
--
2.808 5.143 �s
--
2.937 7.486 �s
G = 1
1
1
1
G
Gain Error
G = 0.5 G = 0.33
0.496 0.5 0.331 0.334
0.504 0.337
G = 0.25
0.248 0.25 0.253
Datasheet
CFR0011-120-00
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� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
3.10 INTERNAL VREF CHARACTERISTICS Table 17: Internal Vref Characteristics
Parameter Vref
Accuracy and
Loading
Description Internal Vref Accuracy at Vref > 1216 mV
Conditions VDD = 2.4 V to 5.5 V, No loading
Note T = 25 �C
Min Typ Max Unit
-0.2
--
0.2
%
T = -40 �C to +85 �C -0.7
--
0.7
%
3.11 OUTPUT BUFFERS CHARACTERISTICS Table 18: HD Buffer Electrical Characteristics at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter Description
Conditions
Min
Typ
Max
Unit
VOFFSET
Input Offset Voltage
dVOFFSET/dt
Offset Drift with Temperature
Offset
VDDA = 5 V, VOUT = 0.5 V to 4 V, T = 25 �C
--
VDDA = 5 V, VOUT = 0.5 V to 4 V, T = -40 �C to +85 �C
--
VOUT = VDDA/2, T = -40 �C to +85 �C
--
0.088 --
1.033
9.936 10.503 33.564
mV mV �V/C
VOUT(I)
Load Regulation
Output VDDA = 5 V, VOUT = 2.048 V, ILOAD = 0.5 mA to 2 mA, T = 25 �C
--
-0.146
0.718
mV
VOUT(U) IS
Line Regulation Short Circuit Current
VDDA = 2.5 V to 5 V, VOUT = 2.048 V, T = 25 �C VDDA = 2.4 V to 5.5 V, T = -40 �C to +85 �C
--
0.803
3.781
mV
--
--
25
mA
Shutdown Characteristics
ton
Buffer Turn-On Time
RLOAD = 5 k, T = 25 �C,
toff
Buffer Turn-Off Time
RLOAD = 5 k, T = 25 �C
--
--
42.583
�s
--
0.076
--
�s
Table 19: Vref0 Output Buffer at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter Description
Conditions
Note
Min Typ
Vref0 Buffer Output Accuracy, Vref = 32 mV to 2048 mV, Buffer Enabled
T = 25 �C Loading = 200 �A Loading = 1 mA
-1
--
-5
--
Vref0 Buffer Accuracy and Loading
Vref0 Buffer Output Capacitance Loading
Load Resistance = 1 M --
--
Load Resistance = 560 k
--
--
Load Resistance = 100 k
--
--
Load Resistance = 10 k
--
--
Load Resistance = 2 k --
--
Load Resistance = 1 k, Vref = 32 mV to 1024 mV
--
--
Max Unit
1
%
5
%
5
pF
10
pF
40
pF
80
pF
120 pF
150 pF
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
3.12 ANALOG TEMPERATURE SENSOR CHARACTERISTICS
Table 20: TS Output vs Temperature (Output Range 1)
T, �C
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85
VDD = 2.5 V
Typical, mV Accuracy, %
1004
�1.29
978
�1.31
955
�.1.33
933
�1.34
910
�1.34
886
�1.36
863
�1.39
840
�1.43
817
�1.48
793
�1.52
769
�1.58
746
�1.62
722
�1.67
710
�1.69
VDD = 3.3 V
Typical, mV Accuracy, %
999
�1.28
976
�1.30
954
�1.32
931
�1.33
908
�1.34
885
�1.36
862
�1.37
838
�1.42
815
�1.46
792
�1.51
768
�1.55
744
�1.61
721
�1.65
709
�1.68
VDD = 5.0 V
Typical, mV Accuracy, %
998
�1.25
976
�1.28
953
�1.29
930
�1.31
907
�1.32
884
�1.33
861
�1.36
838
�1.40
814
�1.44
791
�1.48
767
�1.53
744
�1.59
720
�1.63
708
�1.66
Table 21: TS Output vs Temperature (Output Range 2)
T, �C
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85
VDD = 2.5 V
Typical, mV Accuracy, %
1208
�1.36
1181
�1.37
1153
�1.39
1126
�1.42
1098
�1.42
1070
�1.44
1042
�1.45
1014
�1.49
986
�1.53
957
�1.58
929
�1.63
900
�1.68
872
�1.72
857
�1.76
VDD = 3.3 V
Typical, mV Accuracy, %
1206
�1.35
1179
�1.35
1151
�1.37
1124
�1.40
1096
�1.40
1068
�1.42
1040
�1.44
1012
�1.48
984
�1.52
956
�1.56
927
�1.62
898
�1.66
870
�1.71
855
�1.74
VDD = 5.0 V
Typical, mV Accuracy, %
1205
�1.32
1178
�1.33
1150
�1.35
1123
�1.38
1095
�1.38
1067
�1.41
1039
�1.42
1011
�1.46
983
�1.50
955
�1.54
926
�1.60
898
�1.64
869
�1.69
855
�1.71
Datasheet
CFR0011-120-00
Revision 2.3 29 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
3.13 PROGRAMMABLE OPERATIONAL AMPLIFIER CHARACTERISTICS
Table 22: EC of OA, VDDA = 2.4 V to 5.5 V, VCM = VDDA/2, VOUT VDDA/2, RL = 100 k to VDDA/2, CL = 50 pF, T = 25 �C
Parameter Description
Conditions (Note 1)
Min
Typ
Max
Unit
Input Voltage Offset (without Customers Trimming, Included Factory Block Offset Trim)
VOFFSET
Input Offset Voltage
dVOFFSET/dt
Offset Drift with Temperature
VCM = VDD/2 VCM = VDD/2, T = -40 �C to +85 �C VCM = GND, T = -40 �C to +85 �C
--
500
1000
--
1
5
--
1
5
�V �V/�C �V/�C
Trimmed Input Offset (Customer Perspective after Using Digital Rheostats with Gain = 200x) (Note 2)
VOFFSET
Input Offset Voltage
VDD = 3.3 V, VCM = 0 V to VDD
--
50
--
�V
Input Voltage Range
VCMR
Input Common-Mode Voltage Range
T = -40 �C to +85 �C
-0.2
--
VDD + 0.2
V
CMRR
Common-Mode Rejection Ratio
GND + 0.8 V < VCM < VDD - 0.8 V, T = -40 �C to +85 �C
80
110
GND < VCM< GND+ 0.8 V or VDD - 0.8 V < VCM < VDD
75
90
PSRR
Power Supply Rejection Ratio
VCM = VDD/2, T = -40 �C to +85 �C VCM = GND, T = -40 �C to +85 �C
85
95
80
90
--
dB
--
dB
--
dB
--
dB
CS
Channel Separation
VDD = 5 V, f = 10 Hz
VDD = 5 V, f = 1 kHz
--
100
--
dB
--
80
--
dB
Input Current and Impedance
T = 25 �C
IB
Input Bias Current
T = +85 �C
--
--
4
pA
--
--
125
pA
IOFFSET
Input Offset Current
T = 25 �C T = +85 �C
--
--
1.804
pA
--
32.864
pA
RCM RDIFF
Common-Mode Input Resistance Differential Input Resistance
--
10^13
--
--
10^13
--
CCM CDIFF
Input Capacitance Common-Mode Input Capacitance Differential
--
5
7
pF
--
1.949
2.274
pF
Open-Loop Gain
RLOAD = 1 M,
GND + 0.1 V < VOUT < VDD - 0.1 V,
100
123.796
--
dB
T = -40 �C to +85 �C
AOL
DC Open Loop Gain
RLOAD = 50 k,
GND + 0.5 V < VOUT < VDD - 0.5 V
100
124.093
--
dB
T = -40 �C to +85 �C
Output
Datasheet
CFR0011-120-00
Revision 2.3 30 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 22: EC of OA, VDDA = 2.4 V to 5.5 V, VCM = VDDA/2, VOUT VDDA/2, RL = 100 k to VDDA/2, CL = 50 pF, T = 25 �C
Parameter Description
Conditions (Note 1)
Min
Typ
Max
Unit
RLOAD = 50 k, T = -40 �C to +85 �C
VOH
BW = 8.192 MHz,
Maximum Voltage
RLOAD = 600 , T = -40 �C to +85 �C
Swing
RLOAD = 50 k, T = -40 �C to +85 �C
VOL
BW = 8.192 MHz,
RLOAD = 600 , T = -40 �C to +85 �C
-6.7
--
--
mV
-143
--
--
mV
--
--
4.8
mV
--
--
101
mV
VOSR
Linear Output Swing Range
VOVR from Rail RLOAD = 1 M
BW = 128 kHz, T = -40 �C to +85 �C
GND + 100 --
--
VDD - 100 mV
10.693
--
mA
BW = 512 kHz, T = -40 �C to +85 �C
--
14.288
--
mA
ISC to GND
BW = 2.048 MHz, T = -40 �C to +85 �C
--
22.230
--
mA
IS
Short Circuit Current
BW = 8.192 MHz, T = -40 �C to +85 �C
--
51.489
--
mA
BW = 128 kHz, T = -40 �C to +85 �C
20.010
--
mA
ISC to VDD
BW = 512 kHz, T = -40 �C to +85 �C BW = 2.048 MHz, T = -40 �C to +85 �C
26.206
--
mA
39.910
--
mA
BW = 8.192 MHz, T = -40 �C to +85 �C
89.567
--
mA
CLOAD
Capacitive Load Drive
--
--
pF
Power Supply
VDD
Supply Voltage
Quiescent Current per Amplifier, BW = 128 kHz
IQ (including charge pump
current consumption)
Quiescent Current per Amplifier, BW = 512 kHz Quiescent Current per Amplifier, BW = 2.048 MHz
Quiescent Current per Amplifier, BW = 8.192 MHz
Guaranteed by PSRR Test
T = 25 �C, VDDA = 2.5 V to 5.5 V T = -40 �C to +85 �C, VDDA = 2.5 V to 5.5 V T = 25 �C, VDDA = 2.5 V to 5.5 V T = -40 �C to +85 �C, VDDA = 2.5 V to 5.5 V T = 25 �C, VDDA = 2.5 V to 5.5 V T = -40 �C to +85 �C, VDDA = 2.5 V to 5.5 V T = 25 �C, VDDA = 2.5 V to 5.5 V T = -40 �C to +85 �C, VDDA = 2.5 V to 5.5 V
2.4
--
5.5
V
--
32.558
--
�A
--
32.160
--
�A
--
87.576
--
�A
--
86.940
--
�A
--
236.020
--
�A
--
233.160
--
�A
--
608.094
--
�A
--
594.150
--
�A
Datasheet
CFR0011-120-00
Revision 2.3 31 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 22: EC of OA, VDDA = 2.4 V to 5.5 V, VCM = VDDA/2, VOUT VDDA/2, RL = 100 k to VDDA/2, CL = 50 pF, T = 25 �C
Parameter Description
Conditions (Note 1)
Min
Typ
Max
Unit
IQ (including charge pump
current consumption)
Full Shutdown
Partial Shutdown (Note 3), BW = 128 kHz Partial Shutdown (Note 3), BW = 8.192 MHz
T = -40 �C to +85 �C, VDDA = 2.5 V to 5.5 V T = 25 �C
T = 25 �C
--
103.352
--
nA
--
14.916
--
�A
--
14.916
--
�A
GBW PM
SR tOR
THD en Vn In
Frequency Response
Gain Bandwidth Product
RLOAD = 10 k, CLOAD = 20 pF, G = +1 V/V
BW = 128 kHz BW = 512 kHz BW = 2.048 MHz BW = 8.192 MHz
Phase Margin
G = +1 V/V, BW = 128 kHz 8.192 MHz; RLOAD = 10 k, CLOAD = 20 pF
BW = 128 kHz, T = -40 �C to +85 �C
Slew Rate
RLOAD = 50 k, CLOAD = 85 pF
BW = 512 kHz, T = -40 �C to +85 �C BW = 2.048 MHz, T = -40 �C to +85 �C
BW = 8.192 MHz, T = -40 �C to +85 �C
Overload Recovery Time
T = -40 �C to +85 �C RLOAD = 50 k
Noise
Total Harmonic Distortion
AV = 1, RLOAD = 50 k, VOUT(PP) = VDD/2
f = 1 kHz, BW = 128 kHz f = 1 kHz, BW = 512 kHz f = 1 kHz, BW = 2.048 MHz
f = 1 kHz, BW = 8.192 MHz
Input Voltage Noise
f = 0.1 to 10 Hz
Input Voltage Noise Density
f = 1 kHz
BW = 128 kHz BW = 512 kHz BW = 2.048 MHz
BW = 8.192 MHz
Input Current Noise Density
f = 1 kHz
90 358 1434 5734
44
------
-----------
128 512 2048 8192
70
166
kHz
666
kHz
2662
kHz
10650 kHz
--
degree
0.091 0.380 1.834 6.310 500
--
V/�s
--
V/�s
--
V/�s
--
V/�s
--
�s
1.3
--
%
0.2
--
%
0.7
--
%
0.1
--
%
4
--
�Vpp
--
130
--
125
nV/
--
120
Hz
--
75
fA/
1
--
Hz
Shutdown Characteristics
Datasheet
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Revision 2.3 32 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 22: EC of OA, VDDA = 2.4 V to 5.5 V, VCM = VDDA/2, VOUT VDDA/2, RL = 100 k to VDDA/2, CL = 50 pF, T = 25 �C
Parameter ton toff tPHL
Description Amplifier Turn-On Time Amplifier Turn-Off Time Propagation Delay Output High to Low
Conditions (Note 1)
BW = 8.192 MHz, T = -40 �C to +85 �C BW = 128 kHz, T = -40 �C to +85 �C
VCM = VDDA/2, RL = 50 k VDDA > VCM > (VDDA - 1.3) VCM = VDDA/2, RL = 50 k VDDA > VCM > (VDDA - 1.3) --
Comparator Mode
VID = 100 mV, BW = 128 kHz VID = 100 mV, BW = 512 kHz VID = 100 mV, BW = 2.048 MHz
Min
Typ
Max
Unit
--
2.121
5.363
�s
--
2.145
5.330
�s
--
25.458 43.158
�s
--
35.134 70.602
�s
--
0.671
1.015
�s
--
15
--
�s
--
3.5
--
�s
--
1.2
--
�s
VID = 100 mV, BW = 8.192 MHz
VID = 100 mV, BW = 128 kHz
VID = 100 mV, BW = 512 kHz
tPLH
Propagation Delay Output Low to High
VID = 100 mV, BW = 2.048 MHz
VID = 100 mV, BW = 8.192 MHz
--
4.2
--
�s
--
14
--
�s
--
3.5
--
�s
--
1.2
--
�s
--
4.2
--
�s
3 Op Amp Instrumentation Amplifier Mode
RINT_TL
Mismatch Between Internal Resistors (R1, R2, R3, R4)
--
--
0.15
%
Note 1 AGND = GND, unless otherwise noted Note 2 Equivalent offset voltage of the amplifier after user's trim using digital rheostat. Gain of the amplifier is G=200 and the zero output voltage level Vzero = VDD/2 (See Section 10.2.1) Note 3 Op amps analog supporting blocks are always turned on.
3.14 100K DIGITAL RHEOSTAT CHARACTERISTICS
Table 23: 100K Digital Rheostat EC at VA=VDD, VB=GND, T=-40�C to +85�C, VDD= 2.4V to 5.5V Unless Otherwise Noted
Parameter Description
Conditions
Min
Typ
Max
Unit
VDR
Rheostat Pin Voltage Range
Voltage between any (A or B) pins and AGND
AGND
--
VDDA
V
RDR
Digital Rheostat Resistance
Full resistance with all switches open (Note 1)
80
100
120
k
RDR_MIN
Minimal Rheostat Resistance
Code = 0x00
44.381
--
110
RMATCH
Mismatch between rheostats
Code = 0x3FF, T = 25 �C
--
0.043
--
%
Number of taps
1024
Datasheet
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� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 23: 100K Digital Rheostat EC at VA=VDD, VB=GND, T=-40�C to +85�C, VDD= 2.4V to 5.5V Unless Otherwise Noted
Parameter Description
Conditions
Min
Typ
Max
Unit
Frequency applied on one
side of resistor chain and
BWDTDR
Digital Rheostat Bandwidth
-3 dB frequency measured at the other side with full 100
--
50
--
kHz
K, assume no additional
load
RS IDR_MAX
Step Resistance Max current through Rheostat
T = 25 �C
--
98.266
--
--
--
2
mA
ESW_N
Resistor Noise Voltage
RAB = 25 k, f = 1 kHz
--
30
--
nV/ Hz
fChACMP
Chopper Comparator Switching Frequency
--
--
30
kHz
VCh_offset
Chopper comparator offset when Auto-Trim process is active
--
100
300
�V
fDR_CLK
Counter Frequency independent from the Rheostat
The counter frequency is determined by user selection
0
--
25
MHz
fDR_SWCH
Rheostat Switch Speed (Note 2)
VA = 5 V, VB = 0 V, �1 LSB error band, Auto-Trim mode VA = 5 V, VB = 0 V, �1 LSB error band, regular mode
---
--
10
kHz
--
1
kHz
DR
Maximum Capacitance of A, B pins Measured to AGND
All switches are ON, f = 200 kHz
--
33.461
--
pF
ILKG
Leakage Current
Including active charge pump current consumption
--
--
1000
nA
Error ZScale
Zero-Scale Error
Code = 0x00
--
--
1.203
LSB
INL
Integral Non-linearity
--
--
�1
LSB
DNL
Differential Non-linearity
--
--
�1
LSB
RLOAD <12.5 k
--
240
--
kHz
BWDTCAP
Bandwidth -3 dB (Load = 30 pF)
RLOAD = 12.5 k to 25 k
--
120
--
kHz
RLOAD = 25 k to 50 k
--
60
--
kHz
RLOAD = 50 k to 100 k
--
30
--
kHz
R(T)
Resistance Temperature Coefficient
VAB = const,
--
--
110
ppm/ �C
Potentiometer Mode
INLPOT
Integral Non-linearity in Potentiometer Mode
--
--
�1
LSB
DNLPOT
Differential Non-linearity in Potentiometer Mode
--
--
�1
LSB
Note 1 User can calculate actual Digital Rheostat value using calibration data from NVM (see Section 12.2). Note 2 Includes internal timing. External circuit should be counted separately.
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
3.15 ANALOG SWITCHES CHARACTERISTICS
Table 24: Analog Switch0/Voltage Regulator E at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter Description
Conditions
Min
Typ
Max
Unit
VAS
Maximum Voltage At Pins Voltage between any Analog Switch pin to AGND
0
--
VDD + 0.3
V
fMAX
Maximum Switching Frequency
RL = 50 k
3
--
--
MHz
RON
ON Resistance
VDD = 3.3 V, VIN < 1.2 V, N-ch FET, T = 25 �C VDD = 3.3 V, VDD - 1.2 < VIN < VDD, P-ch FET, T = 25 �C
--
29.621
--
--
3.857
--
IPWROFF
OFF Leakage Current
Switch OFF; from IN to OUT VA = VDD or VB = VDD
--
ON Leakage Current
Switch ON,
IPWRON
(Including Charge Pump quiescent current
--
Current Consumption)
consumption
--
7.456
nA
--
0.1
�A
ISW_MAX
Maximum ON-state Switch VA = VDD, load connected to
Current
ground, VAB= 0.4 V
100
--
--
mA
Table 25: Analog Switch1/Current Sink E at T = -40 �C to +85 �C, VDD = 2.4 V to 5.5 V Unless Otherwise Noted
Parameter Description
Conditions
Min
Typ
Max
Unit
VAS
Maximum Voltage At Pins Voltage between any Analog Switch pin to AGND
0
--
VDD + 0.3
V
fMAX
Maximum Switching Frequency
RL = 50 k
3
--
--
MHz
RON
ON Resistance
VDD = 3.3 V, VIN < 1.2 V, N-ch FET, T = 25 �C VDD = 3.3 V, VDD - 1.2 < VIN < VDD, P-ch FET, T = 25 �C
--
0.809
--
--
95.5
--
IPWROFF
OFF Leakage Current
Switch OFF; from IN to OUT, VA = VDD or VB = VDD
--
ON Leakage Current
Switch ON
IPWRON
(including charge pump quiescent current
--
current consumption)
consumption
--
8.073
nA
--
0.1
�A
ISW_MAX
Maximum ON-state Switch VA = VDD, load connected to
Current
ground, VAB= 0.4 V
100
--
--
mA
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
4 User Programmability
The SLG47004 is a user programmable device with Multiple-Time-Programmable (MTP) memory elements that are able to configure the connection matrix and macrocells. A programming development kit allows the user the ability to create initial devices. Once the design is finalized, the programming code (.gpx file) is forwarded to Dialog Semiconductor to integrate into a production process.
Product Definition
Customer creates their own design in GreenPAK Designer
E-mail Product Idea, Definition, Drawing or Schematic to
CMBUGreenPAK@diasemi.com
Customer verifies GreenPAK in system design
GreenPAK Design approved
Dialog Semiconductor Applications Engineer will review design specifications
with customer
Samples, Design and Characterization Report send to customer
GreenPAK Design approved
Customers verifies GreenPAK design
Custom GreenPAK part enters production
GreenPAK Design Approved in system test
Figure 2: Steps to Create a Custom GreenPAK Device
Datasheet
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� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
5 IO Pins
The SLG47004 has a total of 7 GPIO Pins which can function as either a user-defined Input or Output, as well as serve as a special function (such as outputting the voltage reference) and 1 GPI Pin.
5.1 GPIO PINS IO0, IO1, IO2, IO3, IO4, IO5, and IO6 serve as General Purpose IO Pins.
5.2 GPI PINS I0 serve as General Purpose Input Pin.
5.3 PULL-UP/DOWN RESISTORS All IO Pins have the option of user-selectable resistors that can be connected to the pin structure. The selectable values on these resistors are 10 k, 100 k, and 1 M. The internal resistors can be configured as either Pull-up or Pull-downs.
5.4 FAST PULL-UP/DOWN DURING POWER-UP During power-up, IO Pull-up/down resistance will switch to 2.6 k initially and then it will switch to normal setting value. This function is enabled by register [1207].
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
5.5 I2C MODE IO STRUCTURE 5.5.1 I2C Mode Structure (for SCL and SDA)
Input Mode [1:0] 00: Digital In without Schmitt Trigger, wosmt_en = 1 01: Reserved 10: Low Voltage Digital In mode 1, lv_en = 1 11: Reserved
PAD
VDD Non-Schmitt Trigger Input
WOSMT_EN
VDD Low Voltage Input 1
LV_EN
Preliminary
Digital IN
I2C SDA (SCL) Signal
not available for direct user control
Figure 3: IO with I2C Mode IO Structure Diagram
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
5.6 MATRIX OE IO STRUCTURE
Input Mode registers [1153:1152] 00: Digital In without Schmitt Trigger, wosmt_en = 1 01: Digital In with Schmitt Trigger, smt_en = 1 10: Low Voltage Digital In mode, lv_en = 1 11: analog IO mode
Output Mode [1:0] 00: Push-Pull 1x mode, pp1x_en = 1 01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1 10: NMOS 1x Open-Drain mode, od1x_en = 1 11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1
Note 1: Digital Out and OE are Matrix Output, Digital In is Matrix Input. Note 2: Can be varied over PVT, for reference only.
Digital OUT OE
PP1x_EN
172 (Note 2) VDD
VDD
WOSMT_EN SMT_EN LV_EN
Non-Schmitt Trigger Input
Schmit t Trigger Input
Low Voltage Input
Digital IN
Analog IO
Fl oat ing s0
s1
s2
s3 900 k 90 k
Res_sel [1:0] 00: Floating 01: 10 k 10: 100 k 11: 1 M
10 k
VDD s1 s0
Pull-up_EN
Digital OUT
OE
OD1x_EN
VDD
PAD
Digital OUT OE
PP2x_EN
Digital OUT OE OD2x_EN
Figure 4: Matrix OE IO Structure Diagram
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
5.7 GPI STRUCTURE 5.7.1 GPI Structure (for I0)
Input Mode [1:0] 00: Digital In without Schmitt Trigger, wosmt_en = 1, OE=0 01: Digital In with Schmitt Trigger, smt_en = 1, OE = 0 10: Low Voltage Digital In mode, lv_en = 1, OE = 0 11: Reserved
Note 1: OE cannot be selected by user. Note 2: OE is Matrix output, Digital In is Matrix input.
WOSMT_EN OE
SMT_EN OE
LV_EN OE
Non-Schmitt Trigger Input
Schmitt Trigger Input
Low Voltage Input
Preliminary
Digital IN
PAD
Floating s0
s1
s2
s3 900 k 90 k
Res_sel [1:0] 00: Floating 01: 10 k 10: 100 k 11: 1 M
Figure 5: IO0 GPI Structure Diagram
10 k
VDD s1 s0
Pull-up_EN
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
5.8 IO PINS TYPICAL PERFORMANCE
60
Push-Pull 2x @ VDD = 5 V
Push-Pull 1x @ VDD = 5 V
50
Push-Pull 2x @ VDD = 3.3 V
Push-Pull 1x @ VDD = 3.3 V
Push-Pull 2x @ VDD = 2.5 V
40
Push-Pull 1x @ VDD = 2.5 V
Preliminary
IOH (mA)
30
20
10
0 5.00 4.75 4.50 4.25 4.00 3.75 3.50 3.25 3.00 2.75 2.50 2.25 2.00 1.75 1.50 1.25 VOH (V)
Figure 6: Typical High Level Output Current vs. High Level Output Voltage at T = 25 �C
80
Open Drain 1x @ VDD = 5 V
70
Open Drain 1x @ VDD = 3.3 V
Open Drain 1x @ VDD = 2.5 V
60
Push-Pull 1x @ VDD = 5 V
Push-Pull 1x @ VDD = 3.3 V
Push-Pull 1x @ VDD = 2.5 V 50
IOL (mA)
40
30
20
10
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
VOL (V)
Figure 7: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 �C, Full Range
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
30
Open Drain 1x @ VDD = 5 V
25
Open Drain 1x @ VDD = 3.3 V
Open Drain 1x @ VDD = 2.5 V
Push-Pull 1x @ VDD = 5 V
20
Push-Pull 1x @ VDD = 3.3 V
Push-Pull 1x @ VDD = 2.5 V
15
IOL (mA)
10
5
0
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 �C
140
130 Open Drain 2x @ VDD = 5 V
120
Open Drain 2x @ VDD = 3.3 V
110
Open Drain 2x @ VDD = 2.5 V
100
Push-Pull 2x @ VDD = 5 V
Push-Pull 2x @ VDD = 3.3 V
90 Push-Pull 2x @ VDD = 2.5 V
80
IOL (mA)
70
60
50
40
30
20
10
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
VOL (V)
Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 �C, Full Range
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IOL (mA)
50
45
Open Drain 2x @ VDD = 5 V
Open Drain 2x @ VDD = 3.3 V 40
Open Drain 2x @ VDD = 2.5 V
Push-Pull 2x @ VDD = 5 V 35
Push-Pull 2x @ VDD = 3.3 V
30
Push-Pull 2x @ VDD = 2.5 V
25
20
15
10
5
0
0
0.1
0.2
0.3
0.4
0.5
VOL (V)
Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 �C
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6 Connection Matrix
The Connection Matrix in the SLG47004 is used to create an internal routing for internal functional macrocells of the device once it is programmed. The output of each functional macrocell within the SLG47004 has a specific digital bit code assigned to it, that is either set to active "High" or inactive "Low", based on the design that is created. Once the 2048 register bits within the SLG47004 are programmed, a fully custom circuit will be created.
The Connection Matrix has 64 inputs and 99 outputs. Each of the 64 inputs to the Connection Matrix is hard-wired to the digital output of a particular source macrocell, including IOs, LUTs, analog comparators, other digital resources, such as VDD and GND. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines.
For a complete list of the SLG47004's register table, see Section 21.
Matrix Input Signal Functions
N
GND
0
LUT2_0/DFF0 output 1
LUT2_1/DFF1 output 2
LUT2_2/DFF2 output 3
VDD
62
VDD
63
Matrix Inputs
Matrix Outputs
N Registers Function
0
registers [5:0] Matrix OUT: IN0 of LUT2_0 or Clock
Input of DFF0
1
registers [11:6] Matrix OUT: IN1 of
LUT2_0 or Data Input of DFF0
2
registers [17:12] Matrix Out: IN0 of LUT2_1 or Clock
Input of DFF1
Figure 11: Connection Matrix
99 registers [599:594] OP Vref ENABLE
IO13 IO12
Function LUT
IO14
IO12 IO13
Connection Matrix
LUT
IO14
Figure 12: Connection Matrix Example
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6.1 MATRIX INPUT TABLE Table 26: Matrix Input Table
Matrix Input Number
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Matrix Input Signal Function
GND LUT2_0/DFF0 output LUT2_1/DFF1 output LUT2_2/DFF2 output LUT2_3/PGen output LUT3_0/DFF3 output LUT3_1/DFF4 output LUT3_2/DFF5 output LUT3_3/DFF6 output LUT3_4/DFF7 output LUT3_5/DFF8 output LUT3_6/DFF9 output CNT_DLY0 output MLT0_LUT4_1/DFF17_OUT CNT_DLY1 output MLT1_LUT3_7/DFF11_OUT CNT_DLY2 output MLT2_LUT3_8/DFF12_OUT CNT_DLY3 output MLT3_LUT3_9/DFF13_OUT CNT_DLY4 output MLT4_LUT3_10/DFF14_OUT CNT_DLY5 output MLT5_LUT3_11/DFF15_OUT CNT_DLY6 output MLT6_LUT3_12/DFF16_OUT LUT3_13/Pipe Delay/RippleCNT_out0 Pipe Delay/RippleCNT_out1 Pipe Delay/RippleCNT_out2 LUT4_0/DFF10 output Programmable Delay Edge Detect Output Edge Detect Filter Output I2C_virtual_0 Input I2C_virtual_1 Input I2C_virtual_2 Input I2C_virtual_3 Input I2C_virtual_4 Input I2C_virtual_5 Input
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Matrix Decode
543210 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101
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Table 26: Matrix Input Table(Continued)
Matrix Input Number
38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Matrix Input Signal Function
I2C_virtual_6 Input I2C_virtual_7 Input RH0 Idle/Active RH1 Idle/Active Output of Op Amp0 in ACMP mode Output of Op Amp1 in ACMP mode IO0 Digital Input IO1 Digital Input IO2 Digital Input IO3 Digital Input IO4 Digital Input IO5 Digital Input IO6 Digital Input I0 Digital Input Oscillator0 output 0 Oscillator1 output 0 Oscillator2 output Chopper ACMP Out ACMP0 Output (low speed) ACMP1 Output (low speed) Oscillator0 output 1 Oscillator1 output 1 POR OUT VDD VDD VDD
6.2 MATRIX OUTPUT TABLE Table 27: Matrix Output Table
Register Bit Address [5:0] [11:6] [17:12] [23:18] [29:24] [35:30] [41:36] [47:42] [53:48]
Matrix Output Signal Function
IN0 of LUT2_0 or Clock Input of DFF0 IN1 of LUT2_0 or Data Input of DFF0 IN0 of LUT2_1 or Clock Input of DFF1 IN1 of LUT2_1 or Data Input of DFF1 IN0 of LUT2_2 or Clock Input of DFF2 IN1 of LUT2_2 or Data Input of DFF2 IN0 of LUT2_3 or Clock Input of PGen IN1 of LUT2_3 or nRST of PGen IN0 of LUT3_0 or CLK Input of DFF3
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Preliminary
Matrix Decode 543210 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111
Matrix Output Number 0 1 2 3 4 5 6 7 8
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Table 27: Matrix Output Table(Continued)
Register Bit Address [59:54] [65:60] [71:66] [77:72] [83:78] [89:84] [95:90] [101:96] [107:102] [113:108] [119:114] [125:120] [131:126] [137:132] [143:138] [149:144] [155:150] [161:156] [167:162] [173:168] [179:174]
[185:180]
[191:186]
[197:192]
[203:198]
[209:204]
[215:210]
[221:216]
[227:222]
[233:228]
[239:234]
Matrix Output Signal Function
IN1 of LUT3_0 or Data of DFF3 IN2 of LUT3_0 or nRST (nSET) of DFF3 IN0 of LUT3_1 or CLK Input of DFF4 IN1 of LUT3_1 or Data of DFF4 IN2 of LUT3_1 or nRST (nSET) of DFF4 IN0 of LUT3_2 or CLK Input of DFF5 IN1 of LUT3_2 or Data of DFF5 IN2 of LUT3_2 or nRST(nSET) of DFF5 IN0 of LUT3_3 or CLK Input of DFF6 IN1 of LUT3_3 or Data of DFF6 IN2 of LUT3_3 or nRST (nSET) of DFF6 IN0 of LUT3_4 or CLK Input of DFF7 IN1 of LUT3_4 or Data of DFF7 IN2 of LUT3_4 or nRST (nSET) of DFF7 IN0 of LUT3_5 or CLK Input of DFF8 IN1 of LUT3_5 or Data of DFF8 IN2 of LUT3_5 or nRST (nSET) of DFF8 IN0 of LUT3_6 or CLK Input of DFF9 IN1 of LUT3_6 or CLK Input of DFF9 IN2 of LUT3_6 or nRST (nSET) of DFF9 IN0 of LUT3_7 or CLK Input of DFF11 Delay1 Input (or Counter1 nRST Input) IN1 of LUT3_7 or nRST (nSET) of DFF11 Delay1 Input (or Counter1 nRST Input) IN2 of LUT3_7 or Data of DFF11 Delay1 Input (or Counter1 nRST Input) IN0 of LUT3_8 or CLK Input of DFF12 Delay2 Input (or Counter2 nRST Input) IN1 of LUT3_8 or nRST (nSET) of DFF12 Delay2 Input (or Counter2 nRST Input) IN2 of LUT3_8 or Data of DFF12 Delay2 Input (or Counter2 nRST Input) IN0 of LUT3_9 or CLK Input of DFF13 Delay3 Input (or Counter3 nRST Input) IN1 of LUT3_9 or nRST (nSET) of DFF13 Delay3 Input (or Counter3 nRST Input) IN2 of LUT3_9 or Data of DFF13 Delay3 Input (or Counter3 nRST Input) IN0 of LUT3_10 or CLK Input of DFF14 Delay4 Input (or Counter4 nRST Input) IN1 of LUT3_10 or nRST (nSET) of DFF14 Delay4 Input (or Counter4 nRST Input)
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Preliminary
Matrix Output Number 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
30
31
32
33
34
35
36
37
38
39
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Table 27: Matrix Output Table(Continued)
Register Bit Address [245:240]
[251:246]
[257:252]
[263:258]
[269:264]
[275:270]
[281:276] [287:282] [293:288] [299:294] [305:300] [311:306] [317:312] [323:318] [329:324]
[335:330]
[341:336]
[347:342]
[353:348] [359:354] [365:360] [371:366] [377:372] [383:378] [389:384] [395:390] [401:396] [407:402] [413:408]
Matrix Output Signal Function
IN2 of LUT3_10 or Data of DFF14 Delay4 Input (or Counter4 nRST Input) IN0 of LUT3_11 or CLK Input of DFF15 Delay5 Input (or Counter5 nRST Input) IN1 of LUT3_11 or nRST (nSET) of DFF15 Delay5 Input (or Counter5 nRST Input) IN2 of LUT3_11 or nRST (nSET) of DFF15 Delay5 Input (or Counter5 nRST Input) IN0 of LUT3_12 or CLK Input of DFF16 Delay6 Input (or Counter6 nRST Input) IN1 of LUT3_12 or nRST (nSET) of DFF16 Delay6 Input (or Counter6 nRST Input) IN2 of LUT3_12 or Data of DFF16 Delay6 Input (or Counter6 nRST Input) IN0 of LUT3_13 or Input of Pipe Delay or UP signal of RIPP CNT IN1 of LUT3_13 or nRST of Pipe Delay or nSet of RIPP CNT IN2 of LUT3_13 or CLK of Pipe Delay_RIPP CNT IN0 of LUT4_0 or CLK of DFF10 IN1 of LUT4_0 or Data of DFF10 IN2 of LUT4_0 or nRST (nSET) of DFF10 IN3 of LUT4_0 IN0 of LUT4_1 or CLK Input of DFF17 Delay0 Input (or Counter0 nRST Input) IN1 of LUT4_1 or nRST of DFF17 Delay0 Input (or Counter0 nRST Input) Delay/Counter0 External CLK source IN2 of LUT4_1 or nSet of DFF17 Delay0 Input (or Counter0 nRST Input) Delay/Counter0 External CLK source KEEP Input of FSM0 IN3 of LUT4_1 or Data of DFF17 Delay0 Input (or Counter0 nRST Input) UP Input of FSM0 Programmable delay/edge detect input Filter/Edge detect input IO0 DOUT IO0 DOUT OE IO1 DOUT IO1 DOUT OE IO2 DOUT IO2 DOUT OE IO3 DOUT IO3 DOUT OE IO4 DOUT
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Preliminary
Matrix Output Number 40
41
42
43
44
45
46
47 48 49 50 51 52 53 54
55
56
57
58 59 60 61 62 63 64 65 66 67 68
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Table 27: Matrix Output Table(Continued)
Register Bit Address
Matrix Output Signal Function
[419:414]
IO4 DOUT OE
[425:420]
IO5 DOUT
[431:426]
IO5 DOUT OE
[437:432]
IO6 DOUT
[443:438]
IO6 DOUT OE
[449:444]
Set of PT0 block
[455:450]
Clock of PT0 block
[461:456]
Reload of PT0 block
[467:462]
Program of PT0 block
[473:468]
Up/Down of PT0 block
[479:474]
Set of PT1 block
[485:480]
Clock of PT1 block
[491:486]
Reload of PT1 block
[497:492]
Program of PT1 block
[503:498]
Up/Down of PT1 block
[509:504]
FIFO Reset of PT blocks
[515:510]
Power Up of Chopper ACMP
[521:516]
Rheostats Charge Pump Enable
[527:522]
ASW0 enable/Half bridge Enable
[533:528]
ASW1 enable/Half bridge data
[539:534]
ACMP0 Power Up
[545:540]
ACMP1 Power Up
[551:546]
Oscillator0 Enable
[557:552]
Oscillator1 Enable
[563:558]
Oscillator2 Enable
[569:564]
VrefO, Temp sensor, VrefO Power Up
[575:570]
HDBUF Enable
[581:576]
Op Amp0 Power Up
[587:582]
Op Amp1 Power Up
[593:588]
Op Amp2 Power Up
[599:594]
Op amps Vref Enable
Note 1 For each Address, the two most significant bits are unused.
Matrix Output Number 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
6.3 CONNECTION MATRIX VIRTUAL INPUTS
As mentioned previously, the Connection Matrix inputs come from the outputs of various digital macrocells on the device. Eight of the Connection Matrix inputs have the special characteristic that the state of these signal lines comes from a corresponding data bit written as a register value via I2C. This gives the user the ability to write data via the serial channel, and have this information translated into signals that can be driven into the Connection Matrix and from the Connection Matrix to the digital inputs of other macrocells on the device. The I2C address for reading and writing these register values is at 0x7C (124).
An I2C write command to these register bits will set the signal values going into the Connection Matrix to the desired state. A read command to these register bits will read either the original data values coming from the NVM memory bits (that were
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loaded during the initial device startup), or the values from a previous write command (if that has happened).
See Table 28.
Table 28: Connection Matrix Virtual Inputs
Matrix Input Number 32 33 34 35 36 37 38 39
Matrix Input Signal Function
I2C_virtual_0 Input I2C_virtual_1 Input I2C_virtual_2 Input I2C_virtual_3 Input I2C_virtual_4 Input I2C_virtual_5 Input I2C_virtual_6 Input I2C_virtual_7 Input
Register Bit Addresses (d)
[992] [993] [994] [995] [996] [997] [998] [999]
6.4 CONNECTION MATRIX VIRTUAL OUTPUTS
The digital outputs of the various macrocells are routed to the Connection Matrix to enable interconnections to the inputs of other macrocells in the device. At the same time, it is possible to read the state of each of the macrocell outputs as a register value via I2C. This option, called Connection Matrix Virtual Outputs, allows the user to remotely read the values of each macrocell output. The I2C addresses for reading these register values are bytes 0xC4 (196) to 0xCA (202). Write commands to these same register values will be ignored (with the exception of the Virtual Input register bits at byte 0x7C (124)).
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7 Combination Function Macrocells
The SLG47004 has 13 combination function macrocells that can serve as more than one logic or timing function. In each case, they can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be implemented in these macrocells:
Three macrocells that can serve as either 2-bit LUT or as D Flip-Flop Seven macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset Input One macrocell that can serve as either 3-bit LUT or as Pipe Delay/Ripple Counter One macrocell that can serve as either 2-bit LUT or as Programmable Pattern Generator (PGen) One macrocell that can serve as either 4-bit LUT or as D Flip-Flop with Set/Reset Input
Inputs/Outputs for the 13 combination function macrocells are configured from the connection matrix with specific logic functions being defined by the state of configuration bits.
When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user-defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
7.1 2-BIT LUT OR D FLIP-FLOP MACROCELLS
There is one macrocell that can serve as either 2-bit LUT or as D Flip-Flop. When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection matrix and produces a single output, which goes back into the connection matrix. When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (D) and clock (CLK) inputs for the Flip-Flop, with the output going back to the connection matrix.
The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:
DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change.
LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is High).
From Connection Matrix Output [1] S0
0: 2-bit LUT0 IN1 1: DFF0 Data
S1
From Connection Matrix Output [0] S0
0: 2-bit LUT0 IN0
1: DFF0 CLK
S1
1-bit NVM register [1492]
IN1
2-bit LUT0 OUT
IN0 LUT Truth Table
4-bits NVM registers [1483:1480]
D
DFF/Latch Registers
DFF0
Q/nQ
CLK
register [1483] DFF or LATCH Select register [1482] Output Select (Q or nQ) register [1481] DFF Initial Polarity Select
S0
To Connection Matrix Input [1]
S1
0: 2-bit LUT0 Out 1: DFF0 Out
Figure 13: 2-bit LUT0 or DFF0
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From Connection Matrix Output [3] S0
0: 2-bit LUT1 IN1 1: DFF1 Data
S1
From Connection Matrix Output [2] S0
0: 2-bit LUT1 IN0
1: DFF1 CLK
S1
1-bit NVM register [1493]
From Connection Matrix Output [5] S0
0: 2-bit LUT2 IN1 1: DFF2 Data
S1
From Connection Matrix Output [4] S0
0: 2-bit LUT2 IN0
1: DFF2 CLK
S1
1-bit NVM register [1494]
IN1
2-bit LUT1 OUT
IN0 LUT Truth Table
4-bits NVM registers [1487:1484]
D
DFF/Latch Registers
DFF1
Q/nQ
CLK
register [1487] DFF or LATCH Select register [1486] Output Select (Q or nQ) register [1485] DFF Initial Polarity Select
S0
To Connection Matrix Input [2]
S1
0: 2-bit LUT1 Out 1: DFF1 Out
Figure 14: 2-bit LUT1 or DFF1
IN1
2-bit LUT2 OUT
IN0 LUT Truth Table
4-bits NVM registers [1491:1488]
D
DFF/Latch Registers
DFF2
Q/nQ
CLK
register [1491] DFF or LATCH Select register [1490] Output Select (Q or nQ) register [1489] DFF Initial Polarity Select
S0
To Connection Matrix Input [3]
S1
0: 2-bit LUT2 Out 1: DFF2 Out
Figure 15: 2-bit LUT2 or DFF2
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7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT
Preliminary
Table 29: 2-bit LUT0 Truth Table
IN1
IN0
0
0
0
1
1
0
1
1
OUT register [1480] register [1481] register [1482] register [1483]
Table 30: 2-bit LUT1 Truth Table
IN1
IN0
0
0
0
1
1
0
1
1
OUT register [1484] register [1485] register [1486] register [1487]
Table 31: 2-bit LUT2 Truth Table
IN1
IN0
0
0
0
1
1
0
1
1
OUT register [1488] register [1489] register [1490] register [1491]
LSB MSB LSB MSB LSB MSB
This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-Bit LUT0 is defined by registers [1483:1480]
2-Bit LUT1 is defined by registers [1487:1484]
2-Bit LUT2 is defined by registers [1491:1488]
Table 32 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created within each of the 2-bit LUT logic cells.
Table 32: 2-bit LUT Standard Digital Functions
Function AND-2 NAND-2 OR-2 NOR-2 XOR-2 XNOR-2
MSB
1
0
0
1
1
1
0
0
0
1
1
0
LSB
0
0
1
1
1
0
0
1
1
0
0
1
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7.1.2 Initial Polarity Operations VDD Data Clock
POR
Initial Polarity: High Q with nReset (Case 1)
Preliminary
Initial Polarity: Low Q with nReset (Case 1)
Figure 16: DFF Polarity Operations
7.2 2-BIT LUT OR PROGRAMMABLE PATTERN GENERATOR
The SLG47004 has one combination function macrocell that can serve as a logic or a timing function. This macrocell can serve as a Look Up Table (LUT), or a Programmable Pattern Generator (PGen).
When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection matrix and produces a single output, which goes back into the connection matrix. When used as a LUT to implement combinatorial logic functions, the outputs of the LUT can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR). The user can also define the combinatorial relationship between inputs and outputs to be any selectable function.
It is possible to define the RST level for the PGen macrocell. There are both high level reset (RST) and a low level reset (nRST) options available, which are selected by register [1517]. When operating as the Programmable Pattern Generator, the output of the macrocell will clock out a sequence of two to sixteen bits that are user selectable in their bit values, and user selectable in the number of bits (up to sixteen) that are output before the pattern repeats.
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From Connection Matrix Output [6] From Connection Matrix Output [7]
In0
2-bit LUT3 OUT
In1
LUT Truth
Table
S0
registers [1515:1512]
S1
Pattern size
nRST
PGen OUT
CLK PGen Data
register [1516]
registers [1511:1496]
Figure 17: 2-bit LUT3 or PGen
To Connection Matrix Input [4] 0: 2-bit LUT3 OUT 1: PGen OUT
VDD
t nRST
t
CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
t OUT
D0
D0
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
t
Figure 18: PGen Timing Diagram
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7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT
Table 33: 2-bit LUT1 Truth Table
IN1
IN0
0
0
0
1
1
0
1
1
OUT register [1512] register [1513] register [1514] register [1515]
LSB MSB
This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-Bit LUT3 is defined by [1515:1512]
Table 34 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created within each of the 2-bit LUT logic cells.
Table 34: 2-bit LUT Standard Digital Functions
Function AND-2 NAND-2 OR-2 NOR-2 XOR-2 XNOR-2
MSB
1
0
0
1
1
1
0
0
0
1
1
0
LSB
0
0
1
1
1
0
0
1
1
0
0
1
7.3 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELLS
There are seven macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset inputs. When used to implement LUT functions, the 3-bit LUTs each takes in three input signals from the connection matrix and produces a single output, which goes back into the connection matrix. When used to implement D Flip-Flop function, the three input signals from the connection matrix go to the data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop, with the output going back to the connection matrix. It is possible to define the active level for the reset/set input of DFF/LATCH macrocell. There are both active high level reset/set (RST/SET) and active low level reset/set (nRST/nSET) options available, which are selected by register [1523].
The DFF3 operation will flow the functional description:
If register [1522] = 0, and the CLK is rising edge triggered, then Q = D, otherwise Q will not change. If register [1522] = 1, then data from D is written into the DFF by the rising edge on CLK and output to Q by the falling edge on
CLK.
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Preliminary
From Connection Matrix Output [10]
S0
S1
From Connection Matrix Output [9]
S0
S1
From Connection Matrix Output [8]
S0
S1
IN2
IN1 3-bit LUT0 OUT
IN0
LUT Truth
Table
register [1527] DFF or Latch Select register [1526] Output Select (Q or nQ) register [1525] DFF Initial Polarity Select register [1524] DFF nRST or nSET Select register [1523] Active level selection for RST/SET register [1522] Q1 or Q2 Select
To Connection Matrix
S0
Input [5]
S1
8-bits NVM registers [1527:1520]
DFF/Latch Registers
D nRST/nSET
DFF
D
Q
nRST/ CL nSET
DFF
D
Q
nRST/ CL nSET
0
Q/nQ
1
CLK
register [1522]
1-bit NVM register [1518]
Figure 19: 3-bit LUT0 or DFF3
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
From Connection Matrix Output [13]
S0
S1
From Connection Matrix Output [12]
S0
S1
From Connection Matrix Output [11]
S0
S1
1-bit NVM register [1519]
From Connection Matrix Output [16]
S0
S1
From Connection Matrix Output [15]
S0
S1
From Connection Matrix Output [14]
S0
S1
1-bit NVM register [824]
IN2
IN1 3-bit LUT1 OUT
IN0
LUT Truth
Table
8-bits NVM
register [1535] DFF or LATCH Select register [1534] Output Select (Q or nQ) register [1533] DFF Initial Polarity Select register [1532] DFF nRST or nSET Select register [1531] Active level selection for RST/SET
To Connection Matrix
S0
Input [6]
registers [1535:1528]
S1
D
DFF/Latch Registers
nRST/nSET DFF4
CLK
Q/nQ
Figure 20: 3-bit LUT1 or DFF4
IN2
IN1 3-bit LUT2 OUT
IN0
LUT Truth
Table
8-bits NVM
register [791] DFF or LATCH Select register [790] Output Select (Q or nQ) register [789] DFF Initial Polarity Select register [788] DFF nRST or nSET Select register [787] Active level selection for RST/SET
S0
To Connection Matrix Input [7]
registers [791:784]
S1
DFF/Latch
D
Registers
nRST/nSET DFF5
CLK
Q/nQ
Figure 21: 3-bit LUT2 or DFF5
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
From Connection Matrix Output [19]
S0
S1
From Connection Matrix Output [18]
S0
S1
From Connection Matrix Output [17]
S0
S1
1-bit NVM register [825]
From Connection Matrix Output [22]
S0
S1
From Connection Matrix Output [21]
S0
S1
From Connection Matrix Output [20]
S0
S1
1-bit NVM registers [826]
IN2
IN1 3-bit LUT3 OUT
register [799] DFF or LATCH Select register [798] Output Select (Q or nQ) register [797] DFF Initial Polarity Select register [796] DFF nRST or nSET Select register [795] Active level selection for RST/SET
IN0
LUT Truth
Table
8-bits NVM registers [799:792]
D
DFF Registers
S0
To Connection Matrix Input [8]
S1
nRST/nSET DFF6
CLK
Q/nQ
Figure 22: 3-bit LUT3 or DFF6
IN2
IN1 3-bit LUT4 OUT
register [807] DFF or LATCH Select register [806] Output Select (Q or nQ) register [805] DFF Initial Polarity Select register [804] DFF nRST or nSET Select register [803] Active level selection for RST/SET
IN0
LUT Truth
Table
8-bits NVM registers [807:800]
D
DFF/Latch Registers
S0
To Connection Matrix Input [9]
S1
nRST/nSET DFF7
CLK
Q/nQ
Figure 23: 3-bit LUT4 or DFF7
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
From Connection Matrix Output [25]
S0
S1
From Connection Matrix Output [24]
S0
S1
From Connection Matrix Output [23]
S0
S1
1-bit NVM register [827]
From Connection Matrix Output [28]
S0
S1
From Connection Matrix Output [27]
S0
S1
From Connection Matrix Output [26]
S0
S1
1-bit NVM register [828]
IN2
IN1 3-bit LUT5 OUT
register [815] DFF or LATCH Select register [814] Output Select (Q or nQ) register [813] DFF Initial Polarity Select register [812] DFF nRST or nSET Select register [811] Active level selection for RST/SET
IN0
LUT Truth
Table
8-bits NVM registers [815:808]
D
DFF Registers
S0
To Connection Matrix Input [10]
S1
nRST/nSET DFF8
CLK
Q/nQ
Figure 24: 3-bit LUT5 or DFF8
IN2
IN1 3-bit LUT6 OUT
register [823] DFF or LATCH Select register [822] Output Select (Q or nQ) register [821] DFF Initial Polarity Select register [820] DFF nRST or nSET Select register [819] Active level selection for RST/SET
IN0
LUT Truth
Table
8-bits NVM registers [823:816]
D
DFF Registers
S0
To Connection Matrix Input [11]
S1
nRST/nSET DFF9
CLK
Q/nQ
Figure 25: 3-bit LUT6 or DFF9
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7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs
Preliminary
Table 35: 3-bit LUT0 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [1520] register [1521] register [1522] register [1523] register [1524] register [1525] register [1526] register [1527]
Table 36: 3-bit LUT1 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [1528] register [1529] register [1530] register [1531] register [1532] register [1533] register [1534] register [1535]
Table 37: 3-bit LUT2 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [784] register [785] register [786] register [787] register [788] register [789] register [790] register [791]
Table 38: 3-bit LUT3 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [792] register [793] register [794] register [795] register [796] register [797] register [798] register [799]
LSB
MSB LSB
MSB LSB
MSB LSB
MSB
Table 39: 3-bit LUT4 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [800] register [801] register [802] register [803] register [804] register [805] register [806] register [807]
Table 40: 3-bit LUT5 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [808] register [809] register [810] register [811] register [812] register [813] register [814] register [815]
Table 41: 3-bit LUT6 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [816] register [817] register [818] register [819] register [820] register [821] register [822] register [823]
LSB
MSB LSB
MSB LSB
MSB
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Each macrocell, when programmed for a LUT function, uses an 8-bit register to define their output function:
3-Bit LUT0 is defined by registers [1527:1520]
3-Bit LUT1 is defined by registers [1535:1528]
3-Bit LUT2 is defined by registers [791:784]
3-Bit LUT3 is defined by registers [799:792]
3-Bit LUT4 is defined by registers [807:800]
3-Bit LUT5 is defined by registers [815:808]
3-Bit LUT6 is defined by registers [823:816]
Table 42 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created within each of the four 3-bit LUT logic cells.
Table 42: 3-bit LUT Standard Digital Functions
Function
MSB
LSB
AND-3
1
0
0
0
0
0
0
0
NAND-3
0
1
1
1
1
1
1
1
OR-3
1
1
1
1
1
1
1
0
NOR-3
0
0
0
0
0
0
0
1
XOR-3
1
0
0
1
0
1
1
0
XNOR-3
0
1
1
0
1
0
0
1
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7.3.2 Initial Polarity Operations VDD Data Clock POR
Initial Polarity: High nReset (Case 1) Q with nReset (Case 1) nReset (Case 2) Q with nReset (Case 2)
Initial Polarity: Low nReset (Case 1) Q with nReset (Case 1)
nReset (Case 2) Q with nReset (Case 2)
Figure 26: DFF Polarity Operations with nReset
Preliminary
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Preliminary
VDD Data Clock POR Initial Polarity: High nSet (Case 1) Q with nSet (Case 1) nSet (Case 2) Q with nSet (Case 2) Initial Polarity: Low nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2) Q with nSet (Case 2)
Figure 27: DFF Polarity Operations with nSet
7.4 4-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELL There is one macrocell that can serve as either a 4-bit LUT or as a D Flip-Flop with Set/Reset inputs. When used to implement LUT functions, the 4-bit LUT takes in four input signals from the connection matrix and produces a single output, which goes back into the connection matrix. When used to implement D Flip-Flop function, the input signals from the connection matrix go to the data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop, with the output going back to the connection matrix.
If register [842] = 0, and the CLK is rising edge triggered, then Q = D, otherwise Q will not change.
If register [842] = 1, then data from D is written into the DFF by the rising edge on CLK and output to Q by the falling edge on CLK. It is possible to define the active level for the reset/set input of DFF/LATCH macrocell. There are both active high level reset/set (RST/SET) and active low level reset/set (nRST/nSET) options available, which are selected by register [843].
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
From Connection Matrix Output [53]
S0
S1
From Connection Matrix Output [52]
S0
S1
From Connection Matrix Output [51]
S0
S1
From Connection Matrix Output [50]
S0
S1
1-bit NVM register [829]
register [847] DFF or LATCH Select
register [846] Output Select (Q or nQ)
register [845] DFF Initial Polarity Select
register [844] DFF nRST or nSET Select
register [843]Active level selection for RST/SET
IN3
register [842] Q1 or Q2 Select
IN2
IN1 4-bit LUT0 OUT
IN0
LUT Truth
Table
16-bits NVM registers [847:832]
D
DFF/Latch Registers
nRST/nSET RST/SET
DFF10
CLK
Q1/Q2 Select
register [842]
Q/nQ
To Connection Matrix
S0
Input [29]
S1
Figure 28: 4-bit LUT0 or DFF10 7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT
Table 43: 4-bit LUT0 Truth Table
IN3
IN2
IN1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
IN0
OUT
0
register [832]
LSB
1
register [833]
0
register [834]
1
register [835]
0
register [836]
1
register [837]
0
register [838]
1
register [839]
0
register [840]
1
register [841]
0
register [842]
1
register [843]
0
register [844]
1
register [845]
0
register [846]
1
register [847]
MSB
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Preliminary
This macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:
4-Bit LUT0 is defined by registers [847:832]
Table 44: 4-bit LUT Standard Digital Functions
Function MSB
LSB
AND-4
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NAND-4
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OR-4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
NOR-4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
XOR-4
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
XNOR-4
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
7.5 3-BIT LUT OR PIPE DELAY/RIPPLE COUNTER MACROCELL There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay/Ripple Counter.
When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a single output, which goes back into the connection matrix.
When used as a Pipe Delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK), and Reset (nRST). The Pipe Delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell input (IN). Both of the two outputs (OUT0 and OUT1) provide user selectable options for 1 to 16 stages of delay. There are delay output points for each set of the OUT0 and OUT1 outputs to a 4-input mux that is controlled by registers [851:848] for OUT0 and registers [855:852] for OUT1. The 4-input MUX is used to control the selection of the amount of delay.
The overall time of the delay is based on the clock used in the SLG47004 design. Each DFF cell has a time delay of the inverse of the clock time (either external clock or the internal Oscillator within the SLG47004). The sum of the number of DFF cells used will be the total time delay of the Pipe Delay logic cell. OUT1 Output can be inverted (as selected by register [859]).
In the Ripple Counter mode, there are 3 options for setting, which use 7 bits. There are 3 bits to set nSET value (SV) in range from 0 to 7. It is a value, which will be set into the Ripple Counter outputs when nSET input goes LOW. End value (EV) will use 3 bits for setting outputs code, which will be last code in the cycle. After reaching the EV, the Ripple Counter goes to the first code by the rising edge on CLK input. The Functionality mode option uses 1 bit. This setting defines how exactly Ripple Counter will operate.
The user can select one of the functionality modes by register: RANGE or FULL. If the RANGE option is selected, the count starts from SV. If UP input is LOW the count goes down: SVEVEV-1 to SV+1SV, and others (if SV is smaller than EV), or SVSV1 to EV+1EVSV (if SV is bigger than EV). If UP input is HIGH, count starts from SV up to EV, and others.
In the FULL range configuration the Ripple Counter functions as follows. If UP input is LOW, the count starts from SV and goes down to 0. Then current counter value jumps to EV and goes down to 0, and others.
If UP input is HIGH, count goes up starting from SV. Then current counter value jumps to 0 and counts up to EV, and others. See Ripple Counter functionality example in Figure 30.
Every step is executed by the rising edge on CLK input.
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
registers [855:848]
From Connection Matrix Output [47] From Connection Matrix Output [48] From Connection Matrix Output [49]
IN0
IN1 3-bit LUT13 OUT
IN2
Pipe Delay registers [855:852]
register [859]
From Connection Matrix Output [47] From Connection Matrix Output [48] From Connection Matrix Output [49]
IN
nRST 16 Flip-Flops
CLK
0
OUT1
1
OUT0
0
registers [851:848]
1 Pipe OUT
1
register [858]
From Connection Matrix Output [47] From Connection Matrix Output [49] From Connection Matrix Output [48]
Ripple Counter
UP CLK
UP/DOWN Control
nSET
SET Control
3 Flip-Flops
D
Q
DFF1 CL nQ
D
Q
DFF2 CL nQ
OUT0 OUT1
Datasheet
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Mode & SET/END Value Control
registers [854:848]
D
Q
DFF3 CL nQ
OUT2
Figure 29: 3-bit LUT13/Pipe Delay/Ripple Counter
Revision 2.3 67 of 292
0
OUT2
1
register [858]
To Connection Matrix Input[28]
0 1
register [858]
OUT1 To Connection Matrix Input [27]
0 1
register [857]
OUT0 To Connection Matrix Input [26]
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Figure 30: Example: Ripple Counter Functionality 7.5.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT
Table 45: 3-bit LUT13 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [848] register [849] register [850] register [851] register [852] register [853] register [854] register [855]
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Each macrocell, when programmed for a LUT function, uses an 8-bit register to define their output function: 3-Bit LUT13 is defined by registers [855:848]
Preliminary
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Preliminary
8 Multi-Function Macrocells
The SLG47004 has seven Multi-Function macrocells that can serve as more than one logic or timing function. In each case, they can serve as a LUT, DFF with flexible settings, or as CNT/DLY with multiple modes such as One Shot, Frequency Detect, Edge Detect, and others. Also, the macrocell is capable to combine those functions: LUT/DFF connected to CNT/DLY or CNT/DLY connected to LUT/DFF, see Figure 31.
See the list below for the functions that can be implemented in these macrocells:
Six macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays One macrocell that can serve as a 4-bit LUT/D Flip-Flop and as 16-Bit Counter/Delay/FSM
To Connection Matrix
To Connection Matrix
From Connection
Matrix
LUT or
DFF
CNT/DLY
From
To Connection Connection
Matrix
Matrix
CNT/DLY
LUT or
DFF
To Connection Matrix
Figure 31: Possible Connections Inside Multi-Function Macrocell
Inputs/Outputs for the seven Multi-Function macrocells are configured from the connection matrix with specific logic functions being defined by the state of NVM bits.
When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
8.1 3-BIT LUT OR DFF/LATCH WITH 8-BIT COUNTER/DELAY MACROCELLS
There are six macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays.
When used to implement LUT functions, the 3-bit LUTs each takes in three input signals from the connection matrix and produces a single output, which goes back into the connection matrix or can be connected to CNT/DLY's input.
When used to implement D Flip-Flop function, the three input signals from the connection matrix go to the data (D), clock (CLK), and Reset/Set (nRST/nSET) inputs of the Flip-Flop, with the output going back to the connection matrix or to the CNT/DLY's input.
When used to implement Counter/Delays, each macrocell has a dedicated matrix input connection. For flexibility, each of these macrocells has a large selection of internal and external clock sources, as well as the option to chain from the output of the previous (N-1) CNT/DLY macrocell, to implement longer count/delay circuits. These macrocells can also operate in a One-Shot mode, which will generate an output pulse of user-defined width. They can also operate in a Frequency Detection or Edge Detection mode.
Counter/Delay macrocell has an initial value, which defines its initial value after SLG47004 is powered up. It is possible to select initial Low or initial High, as well as initial value defined by a Delay In signal.
For example, in case initial LOW option is used, the rising edge delay will start operation.
For timing diagrams refer to Section 8.3.
Note: After two DFF � counters initialize with counter data = 0 after POR. Initial state = 1 � counters initialize with counter data = 0 after POR. Initial state = 0 And After two DFF is bypass � counters initialize with counter data after POR.
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Preliminary
CNT5 and CNT6 current count value can be read via I2C. However, it is possible to change the counter data (value counter starts operating from) for any macrocell using I2C write commands. In this mode, it is possible to load count data immediately (after two DFF) or after counter ends counting. See Section 18.7.1 for further details.
8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams
From Connection Matrix Output [31] From Connection Matrix Output [30] From Connection Matrix Output [29]
S0
S0
S1
S1
S0
S0
S1
S1
S0
S0
S1
S1
register [1244] LUT/DFF Sel
IN2 3-bit LUT7
register [1391] DFF or LATCH Select register [1390] Output Select (Q or nQ) register [1389] (nRST or nSET) from matrix Output register [1388] DFF Initial Polarity Select
IN1
OUT
IN0
LUT Truth
Table
8-bits NVM registers [1391:1384]
D
DFF Registers
nRST/nSET DFF/
Q/nQ
LATCH11
CLK
S0
To Connection Matrix Input [15]
S1
registers [1243:1240] Mode Sel
S0 S1 S2 0 S3
0 S0 S1 S2 S3
registers [1399:1392]
ext_CLK
CNT Data
CNT/DLY1 OUT
DLY_IN/CNT Reset Config Data
registers [1255:1245], [1339:1338]
To Connection Matrix Input [14]
Figure 32: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT7/DFF11, CNT/DLY1)
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
From Connection Matrix Output [34] From Connection Matrix Output [33] From Connection Matrix Output [32]
S0
S0
S1
S1
S0
S0
S1
S1
S0
S0
S1
S1
register [1260] LUT/DFF Sel
IN2 3-bit LUT8
register [1407] DFF or LATCH Select register [1406] Output Select (Q or nQ) register [1405] (nRST or nSET) from matrix Output register [1404] DFF Initial Polarity Select
IN1
OUT
IN0
LUT Truth
Table
8-bits NVM registers [1407:1400]
D
DFF Registers
nRST/nSET DFF/ Q/nQ Latch12
CLK
S0
To Connection Matrix Input [17]
S1
registers [1259:1256] Mode Sel
S0 S1 S2 0 S3
registers [1415:1408]
ext_CLK
CNT Data
0 S0
CNT/DLY2 OUT
S1
S2
DLY_IN/CNT Reset Config
S3
Data
registers [1271:1261], [1345:1344]
To Connection Matrix Input [16]
Figure 33: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF12, CNT/DLY2)
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
From Connection Matrix Output [37]
S0 S1
From Connection Matrix Output [36]
S0 S1
From Connection Matrix Output [35]
S0 S1
register [1423] DFF or LATCH Select
register [1422] Output Select (Q or nQ)
register [1421] (nRST or nSET) from
matrix Output
S0
IN2 3-bit LUT9
register [1420] DFF Initial Polarity Select
IN1
OUT
S1
IN0
LUT Truth
Table
S0
8-bits NVM
S0
To Connection Matrix Input [19]
S1
registers [1423:1416]
S1
D
DFF Registers
S0
nRST/nSET DFF/
Q/nQ
S1
Latch13
CLK
register [1276] LUT/DFF Sel
registers [1275:1272] Mode Sel
S0 S1 S2 0 S3
registers [1431:1424]
ext_CLK
CNT Data
0 S0 S1 S2 S3
CNT/DLY3 OUT
DLY_IN/CNT Reset Config Data
registers [1287:1277], [1347:1346]
To Connection Matrix Input [18]
Figure 34: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF13, CNT/DLY3)
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
From Connection Matrix Output [40] From Connection Matrix Output [39] From Connection Matrix Output [38]
S0
S0
S1
S1
S0
S0
S1
S1
S0
S0
S1
S1
register [1292] LUT/DFF Sel
IN2 3-bit LUT10
register [1439] DFF or LATCH Select register [1438] Output Select (Q or nQ) register [1437] (nRST or nSET) from matrix Output register [1436] DFF Initial Polarity Select
IN1
OUT
IN0
LUT Truth
Table
8-bits NVM registers [1439:1432]
D
DFF Registers
nRST/nSET DFF/
Q/nQ
Latch14
CLK
S0
To Connection Matrix Input [21]
S1
registers [1291:1288] Mode Sel
S0 S1 S2 0 S3
registers [1447:1440
ext_CLK
CNT Data
0 S0 S1 S2 S3
CNT/DLY4 OUT
DLY_IN/CNT Reset Config Data
registers [1303:1293], [1349:1348]
To Connection Matrix Input [20]
Figure 35: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF14, CNT/DLY4)
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
From Connection Matrix Output [43]
S0 S1
From Connection Matrix Output [42]
S0 S1
From Connection Matrix Output [41]
S0 S1
register [1455] DFF or LATCH Select
register [1454] Output Select (Q or nQ)
register [1453] (nRST or nSET) from
matrix Output
S0
IN2 3-bit LUT11
register [1452] DFF Initial Polarity Select
IN1
OUT
S1
IN0
LUT Truth
Table
S0
8-bits NVM
S0
To Connection Matrix Input [23]
S1
registers [1455:1448]
S1
D
DFF Registers
S0
nRST/nSET DFF/
Q/nQ
S1
Latch15
CLK
register [1308] LUT/DFF Sel
registers [1307:1304] Mode Sel
S0 S1 S2 0 S3
registers [1463:1456]
ext_CLK
CNT Data
0 S0 S1 S2 S3
CNT/DLY5 OUT
DLY_IN/CNT Reset Config Data
registers [1319:1309], [1351:1350]
To Connection Matrix Input [22]
Figure 36: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF15, CNT/DLY5)
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
From Connection Matrix Output [46] From Connection Matrix Output [45] From Connection Matrix Output [44]
S0
S0
S1
S1
S0
S0
S1
S1
S0
S0
S1
S1
register [1324] LUT/DFF Sel
IN2 3-bit LUT12
register [1471] DFF or LATCH Select register [1470] Output Select (Q or nQ) register [1469] (nRST or nSET) from matrix Output register [1468] DFF Initial Polarity Select
IN1
OUT
IN0
LUT Truth
Table
8-bits NVM registers [1471:1464]
D
DFF Registers
nRST/nSET DFF/ Latch16
CLK
Q/nQ
S0
To Connection Matrix Input [25]
S1
registers [1323:1320] Mode Sel
S0 S1 S2 0 S3
registers [1479:1472]
ext_CLK
CNT Data
0 S0
CNT/DLY6 OUT
S1
S2
DLY_IN/CNT Reset Config
S3
Data
registers [1335:1325], [1341:1340]
To Connection Matrix Input [24]
Figure 37: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF16, CNT/DLY6)
As shown in Figure 32 to Figure 37 there is a possibility to use LUT/DFF and CNT/DLY simultaneously.
Note: It is not possible to use LUT and DFF at once, one of these macrocells must be selected.
Case 1. LUT/DFF in front of CNT/DLY. Three input signals from the connection matrix go to previously selected LUT or DFF's inputs and produce a single output which goes to a CND/DLY input. In its turn Counter/Delay's output goes back to the matrix.
Case 2. CNT/DLY in front of LUT/DFF. Two input signals from the connection matrix go to CND/DLY's inputs (IN and CLK). Its output signal can be connected to any input of previously selected LUT or DFF, after which the signal goes back to the matrix.
Case 3. Single LUT/DFF or CNT/DLY. Also, it is possible to use a standalone LUT/DFF or CNT/DLY. In this case, all inputs and output of the macrocell are connected to the matrix.
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8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs
Preliminary
Table 46: 3-bit LUT7 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [1384] register [1385] register [1386] register [1387] register [1388] register [1389] register [1390] register [1391]
Table 47: 3-bit LUT8 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [1400] register [1401] register [1402] register [1403] register [1404] register [1405] register [1406] register [1407]
Table 48: 3-bit LUT9 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [1416] register [1417] register [1418] register [1419] register [1420] register [1421] register [1422] register [1423]
Table 49: 3-bit LUT10 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [1432] register [1433] register [1434] register [1435] register [1436] register [1437] register [1438] register [1439]
LSB
MSB LSB
MSB LSB
MSB LSB
MSB
Table 50: 3-bit LUT11 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [1448] register [1449] register [1450] register [1451] register [1452] register [1453] register [1454] register [1455]
Table 51: 3-bit LUT12 Truth Table
IN2
IN1
IN0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUT register [1464] register [1465] register [1466] register [1467] register [1468] register [1469] register [1470] register [1471]
LSB MSB LSB MSB
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Each macrocell, when programmed for a LUT function, uses an 8-bit register to define their output function: 3-Bit LUT7 is defined by registers [1391:1384] 3-Bit LUT8 is defined by registers [1407:1400] 3-Bit LUT9 is defined by registers [1423:1416] 3-Bit LUT10 is defined by registers [1439:1432] 3-Bit LUT11 is defined by registers [1455:1448] 3-Bit LUT12 is defined by registers [1471:1464]
Preliminary
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Preliminary
8.2 4-BIT LUT OR DFF/LATCH WITH 16-BIT COUNTER/DELAY MACROCELL
There is one macrocell that can serve as either 4-bit LUT/D Flip-Flops or as 16-bit Counter/Delay.
When used to implement LUT function, the 4-bit LUT takes in four input signals from the Connection Matrix and produces a single output, which goes back into the Connection Matrix.
When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (D) and clock (CLK) inputs for the Flip-Flop, with the output going back to the connection matrix.
When used to implement 16-Bit Counter/Delay function, two of the four input signals from the connection matrix go to the external clock (EXT_CLK) and reset (DLY_IN/CNT Reset) for the Counter/Delay, with the output going back to the connection matrix.
This macrocell has an optional Finite State Machine (FSM) function. There are two additional matrix inputs for Up and Keep to support FSM functionality
This macrocell can also operate in a one-shot mode, which will generate an output pulse of user-defined width. This macrocell can also operate in a frequency detection or edge detection mode. This macrocell can have its active count value read via I2C. See Section 18.7.1 for further details. Note: After two DFF � counters initialize with counter data = 0 after POR.
Initial state = 1 � counters initialize with counter data = 0 after POR. Initial state = 0 And After two DFF is bypass � counters initialize with counter data after POR.
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram
From Connection Matrix Output [57]
S1 S0
From Connection Matrix Output [56]
S1 S0
From Connection Matrix Output [55]
S1 S0
S0
IN3
S1
S1
IN2
register [1367] DFF or LATCH Select register [1366] DFF Output Select (Q or nQ) register [1365] DFF Initial Polarity Select
S1 0 S0
4-bit LUT1
S0
IN1
0 S0
OUT
S1
IN0
LUT Truth
S1
Table
S0
1 S0
registers [1217:1216] = 00, 10, 11
16-bits NVM
S0
To Connection Matrix Input [13]
S1
registers [1367:1352] S1
From Connection Matrix Output [54]
S1 S0
S0
S1
S1
1 S0
D nSET nRST
CLK
DFF Registers
DFF17
Q/nQ
LUT/DFF Sel register [1220]
registers [1219:1216]
registers [1222:1221]
registers [1383:1368]
Mode Selection
CMO* [57]
S0
CMO* [56]
S1
CMO* [55]
S2
CMO* [54]
S3
0
S0
CNT
0
S0 S1
CMO* [56]
S1
CMO* [55]
S2
0
S3
S0
ext_CLK Data
S2 S3
S1
S1
CMO* [55]
CNT/DLY0 OUT
From Connection
DLY_IN/CNT Reset
Matrix Output [56]
0
S0
From Connection
Matrix Output [57] S1
KEEP UP
FSM
Config Data
Note: CMO - Connection Matrix Output
0
S0
registers [1217:1216] = 01
registers [1238:1223], [1337:1336]
To Connection Matrix Input [12]
Figure 38: 4-bit LUT1 or CNT/DLY0
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8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs
Table 52: 4-bit LUT1 Truth Table
IN3
IN2
IN1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
IN0
OUT
0
register [1352]
1
register [1353]
0
register [1354]
1
register [1355]
0
register [1356]
1
register [1357]
0
register [1358]
1
register [1359]
0
register [1360]
1
register [1361]
0
register [1362]
1
register [1363]
0
register [1364]
1
register [1365]
0
register [1366]
1
register [1367]
Preliminary LSB
MSB
This macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:
4-Bit LUT1 is defined by registers [1367:1352]
Table 53: 4-bit LUT Standard Digital Functions
Function MSB
AND-4
1
0
0
0
0
0
0
0
0
0
0
0
0
0
NAND-4
0
1
1
1
1
1
1
1
1
1
1
1
1
1
OR-4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NOR-4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XOR-4
0
1
1
0
1
0
0
1
1
1
0
0
1
1
XNOR-4
1
0
0
1
0
1
1
0
0
0
1
1
0
0
LSB
0
0
1
1
1
0
0
1
1
0
0
1
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8.3 CNT/DLY/FSM TIMING DIAGRAMS 8.3.1 Delay Mode CNT/DLY0 to CNT/DLY6
Preliminary
Delay In
OSC: force Power-On (always running)
Delay Output
Asynchronous delay variable
Asynchronous delay variable
delay = period x (counter data + 1) + variable variable is from 0 to 1 clock period
delay = period x (counter data + 1) + variable variable is from 0 to 1 clock period
Delay In
OSC: auto Power-On (powers up from delay in)
offset
offset
Delay Output
delay = offset + period x (counter data + 1) See offset in table 3
delay = offset + period x (counter data + 1) See offset in table 3
Figure 39: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
The macrocell shifts the respective edge to a set time and restarts by appropriate edge. It works as a filter if the input signal is shorter than the delay time.
Delay time Delay time Delay time One-Shot/Freq. DET/Delay IN
Delay time Delay time
Delay time
t
Delay Function Rising Edge Detection
t
Delay Function Falling Edge Detection
t
Delay Function Both Edge Detection
t Figure 40: Delay Mode Timing Diagram for Different Edge Select Modes
8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY6
RESET_IN
CLK
Counter OUT
4 CLK period pulse
Count start in first rising edge CLK
Figure 41: Counter Mode Timing Diagram without Two DFFs Synced Up
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
RESET_IN
CLK
Counter OUT
4 CLK period pulse
Count start in 0 CLK after reset
Figure 42: Counter Mode Timing Diagram with Two DFFs Synced Up
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY6
This macrocell will generate a pulse whenever a selected edge is detected on its input. Register bits set the edge selection. The pulse width is determined by counter data and clock selection properties.
The output pulse polarity (non-inverted or inverted) is selected by register bit. Any incoming edges will be ignored during the pulse width generation. The following diagram shows one-shot function for non-inverted output.
Delay time Delay time Delay time One-Shot/Freq. DET/Delay IN
Delay time Delay time
Delay time
t
One-Shot Function Rising Edge Detection
t
One-Shot Function Falling Edge Detection
t
One-Shot Function Both Edge Detection
t Figure 43: One-Shot Function Timing Diagram
This macrocell generates a high level pulse with a set width (defined by counter data) when detecting the respective edge. It does not restart while pulse is high.
8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6
Rising Edge: The output goes high if the time between two successive edges is less than the delay. The output goes low if the second rising edge has not come after the last rising edge in specified time.
Falling Edge: The output goes high if the time between two falling edges is less than the set time. The output goes low if the second falling edge has not come after the last falling edge in specified time.
Both Edge: The output goes high if the time between the rising and falling edges is less than the set time, which is equivalent to the length of the pulse. The output goes low if after the last rising/falling edge and specified time, the second edge has not come.
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Delay time Delay time Delay time One-Shot/Freq. DET/Delay IN
Delay time Delay time
Delay time
Frequency Detector Function Rising Edge Detection
Frequency Detector Function Falling Edge Detection
Frequency Detector Function Both Edge Detection
Figure 44: Frequency Detection Mode Timing Diagram
Preliminary
t t t t
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY6 The macrocell generates high level short pulse when detecting the respective edge. See Table 10.
Delay time Delay time Delay time One-Shot/Freq. DET/Delay IN
Delay time Delay time
Preliminary
t
Edge Detector Function Rising Edge Detection
t
Edge Detector Function Falling Edge Detection
t Edge Detector Function
Both Edge Detection
t Figure 45: Edge Detection Mode Timing Diagram 8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY6 In Delayed Edge Detection Mode, High-level short pulses are generated on the macrocell output after the configured delay time, if the corresponding edge was detected on the input. If the input signal is changed during the set delay time, the pulse will not be generated.
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Delay time Delay time Delay time One-Shot/Freq. DET/Delay IN
Delay time Delay time
t
Delayed Edge Detector Function Rising Edge Detection
t
Delayed Edge Detector Function Falling Edge Detection
t
Delayed Edge Detector Function Both
Edge Detection
t Figure 46: Delayed Edge Detection Mode Timing Diagram
8.3.7 CNT/FSM Mode CNT/DLY0
RESET IN KEEP
COUNT END
CLK
Q 3 2 10 3 2 1 0
3
2 1 03 2 10
Note: Q = current counter value
Figure 47: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
SET IN KEEP
COUNT END
CLK
Q 3 2 13 2 1 0 3
2
1 0 32 1 03
Note: Q = current counter value
Figure 48: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3
RESETI N KEEP
COUNT END
CLK
Q 3 4 50 1 2 3 4
5
6 7 89
65533 65534 65535
3
4
5
Note: Q = current counter value
Figure 49: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
SET IN KEEP
COUNT END
CLK
Q 3 4 53 4 5 6 7
8
9 10 11 12
65533 65534 65535
3
4
5
Note: Q = current counter value
Figure 50: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3
8.3.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes
There is a difference in counter value for Counter and Delay/One-Shot/Frequency Detect modes. Compared to Counter mode, in Delay/One-Shot/Frequency Detect modes the counter value is shifted for two rising edges of the clock signal. See Figure 51.
One-Shot/Freq. SET/Delay IN
Datasheet
CFR0011-120-00
CLK
CNT Out
CNT Data
0
3
2
1
0
3
2
DLY Out Delay Data
3
3
3
2
1
3
3
One-Shot Out
One-Shot Data
3
3
3
2
1
3
3
Figure 51: Counter Value, Counter Data = 3
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8.4 WAKE AND SLEEP CONTROLLER
The SLG47004 has a Wake and Sleep (WS) function for ACMP. The macrocell CNT/DLY0 can be reconfigured for this purpose registers [1224:1223] = 11 and register [1232] = 1. The WS serves for power saving, it allows to switch on and off selected ACMPs on selected bit of 16-bit counter.
Note 1: BG/Analog_Good time is long and should be considered in the wake and sleep timing in case it dynamically powers on/off.
Note 2: Wake time should be long enough to make sure ACMP and Vref have enough time to get a sample before going to sleep.
Power Control From Connection Matrix Output [91] for 2 kHz OSC0.
OSC0 CK_OSC
WS Controller
Divider
CNT ck
cnt_end
CNT0_out
To Connection Matrix Input [12]
ACMPs WS EN [1:0] register [612], register [634]
2
Analog Control Block
WS_PD
WS_PD
(from OSC PD)
WS_PD to WS out state selection register [1233]
registers [1230:1227] WS clock freq. selection
registers [1383:1368] WS ratio control data
WS_out
From Connection Matrix Output [90:89]
ACMPs_PD 2
WS_out
registers [633], [611] WS mode: normal or short wake Note: WS_PD is High at OSC0 power-down
BG/Analog_Good
ACMPs_PD 2 WS_out
ACMPs
+ -
0 1
nRST
bg/regulator pd
ACMP0, ACMP1 OUT 2
To Connection Matrix Input [57:56]
Figure 52: Wake and Sleep Controller
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Preliminary
CNT_RST (From Connection Matrix)
ACMP_PD is High (From Connection Matrix)
CNT0_out (To Connection Matrix)
Force Wake
time between Reset goes low and 1st WS clock rising edge
WS_out (internal signal)
BG/Analog_Good (internal signal)
Data is latched
Sleep Mode
Normal ACMP
ACMP Latches Last Data
Operation
ACMP follows input
Sleep Mode ACMP Latches New Data
Normal ACMP Operation
ACMP follows input
BG/Analog Startup time*
BG/Analog Startup time*
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.
Sleep Mode ACMP Latches
New Data
Figure 53: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used
Force Wake
time between Reset goes low and 1st WS clock rising edge
CNT_RST (From Connection Matrix)
ACMP_PD is High (From Connection Matrix)
CNT0_out (To Connection Matrix)
WS_out (internal signal)
BG/Analog_Good (internal signal)
Data is latched
Data is latched
Sleep Mode ACMP Latches Last Data
BG/Analog Startup time*
Sleep Mode ACMP Latches New Data Normal ACMP Operation for short time ACMP follows input
Normal ACMP Operation for short time
ACMP follows input
Sleep Mode ACMP Latches
New Data
BG/Analog Startup time*
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.
Figure 54: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used
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Preliminary
CNT_SET (From Connection Matrix)
ACMP_PD is High (From Connection Matrix)
CNT0_out (To Connection Matrix)
WS_out (internal signal)
BG/Analog_Good (internal signal)
Force Sleep
time between Reset goes low and 1st WS clock rising edge
Data is latched
Sleep Mode
Normal ACMP
ACMP Latches Last Data
Operation
ACMP follows input
Sleep Mode ACMP Latches New Data
BG/Analog Startup time*
Note: CNT0_out is a delayed WS_out signal for 1 us to make sure the data is correct during LATCH.
Figure 55: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used
CNT_RST (From Connection Matrix)
Force Sleep
time between Reset goes low and 1st WS clock rising edge
ACMP_PD is High (From Connection Matrix)
CNT0_out (To Connection Matrix)
WS_out (internal signal)
BG/Analog_Good (internal signal)
Data is latched
Sleep Mode ACMP Latches Last Data
BG/Analog Startup time*
Normal ACMP Operation for short time
ACMP follows input
Sleep Mode ACMP Latches New Data
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.
Figure 56: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Set is Used
Note: If low power BG is powered on/off by WS, the wake time should be longer than 2.1 ms. The BG/analog start up time will take maximal 2 ms. If low power BG is always on, OSC0 period is longer than required wake time. The short wake mode can be used to reduce the current consumption. The short wake mode is edge triggered, when the wake signal is latched by rising edge and released the Power-On signal after the ACMP output data is latched. This allows to have a valid ACMP data for any type of wake signal and have the optimized current consumption.
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To use any ACMP under WS controller, the following settings must be done:
CNT/DLY0 must be set to Wake and Sleep Controller function (for all ACMPs); Register WS => enable (for each ACMP separately); CNT/DLY0 set/reset input = 0 (for all ACMPs).
As the OSC any oscillator with any pre-divider can be used. The user can select a period of time while the ACMP is sleeping in a range of 1 - 65535 clock cycles. Before they are sent to sleep their outputs are latched, so the ACMPs remain their state (High or Low) while sleeping.
WS controller has the following settings:
Wake and Sleep Output State (High/Low) If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = High, the ACMP is continuously on. If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = Low, the ACMP is continuously off. Both cases WS function is turned off.
Counter Data (Range: 1 to 65535) User can select wake and sleep ratio of the ACMP; counter data = sleep time, one clock = wake time.
Q mode - defines the state of WS counter data when Set/Reset signal appears Reset - when active signal appears, the WS counter will reset to zero and High level signal on its output will turn on the ACMPs. When Reset signal goes out, the WS counter will go Low and turn off the ACMPs until the counter counts up to the end. Set - when active signal appears, the WS counter will stop and Low level signal on its output will turn off the ACMPs. When Set signal goes out, the WS counter will go on counting and High level signal will turn on the ACMPs while counter is counting up to the end.
Note: The OSC0 matrix power down to control ACMP WS is not supported for short wait time option.
Edge Select defines the edge for Q mode High level Set/Reset - switches mode Set/Reset when level is High
Note: Q mode operates only in case of "High Level Set/Reset".
Wake time selection - time required for wake signal to turn the ACMPs on
Normal Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on until WS signal is Low again. Wake time is one clock period. It should be longer than BG turn on time and minimal required comparing time of the ACMP.
Short Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on for 1 �s and turn off regardless of WS signal. The WS signal width does not matter. Keep - pauses counting while Keep = 1 Up - reverses counting
If Up = 1, CNT is counting up from user selected value to 65535. If Up = 0, CNT is counting down from user selected value to 0.
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Preliminary
9 Analog Comparators
9.1 ANALOG COMPARATORS OVERVIEW
There are two Low Power Rail-to-Rail General Purpose Analog Comparators (ACMP) macrocells in the SLG47004. For the ACMP macrocells to be used in a GreenPAK design, the power-up signals (ACMP0_L_pdb and ACMP1_L_pdb) need to be active. By connecting to signals coming from the Connection Matrix, it is possible to have each ACMP be ON continuously, OFF continuously, or switched on periodically, based on a digital signal coming from the Connection Matrix. When ACMP is powered down, its output is low. Two General Purpose Analog Comparators are optimized for low power operation.
Each of the General Purpose ACMP cells has a positive input signal that can be provided by a variety of external sources, and can also have a selectable gain stage (1x, 0.5x, 0.33x, 0.25x) before connection to the analog comparator. The gain divider is unbuffered and has an input resistance of 2 M (typ) for 0.5x, 0.33x, 0.25x, and 10 G for 1x. Each of the General Purpose ACMP macrocells has a negative input signal that is either created from an internal Vref or provided by any external source (from external pins). Note that the external Vref signal is filtered with a 2nd order low pass filter with 8 kHz typical bandwidth, see in Figure 57 and Figure 58.
Input bias current < 1 nA (typ).
PWR UP = 1 => ACMP is powered up.
PWR UP = 0 => ACMP is powered down.
Both General Purpose Analog Comparators have "Low Energy Power Up" setting (register [608] - AMP0, register [630] AMP1). When enabled, it allows reducing average power consumption during ACMP power up process. This setting changes power up sequence of analog macrocells:
Low Energy Power Up register [608], register [630] = 0 - all analog macrocells associated with ACMP turns on simultaneously.
Low Energy Power Up register [608], register [630] = 1 - the first macrocell that begins to turn on is Bandgap. Other analog macrocells begin to turn on only after BG_OK signal is valid. This option slightly increases general ACMP Power-On time, while reducing the average current consumption.
During power-up, the ACMP output will remain LOW, and then becomes valid after power up signal goes high for ACMP0_L and ACMP1_L (see parameter tstart in Table 16).
Each cell also has a flexible hysteresis selection, to offer hysteresis of 32 steps, but not more than Vref voltage. It means that there are 6-bits to select Vref and independent 6-bits to select the hysteresis (no need to have an adder logic).
It's possible to enable low pass filter at the Vref input. But it's highly recommended to enable this LPF only when hysteresis Vhys > 196 mV.
ACMP0_L IN+ options are OA0_out, GPIOx (PIN), VDD.
ACMP1_L IN+ options are OA1, GPIOx (PIN), ACMP0L_IN+, Temp Sensor OUT.
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9.1.1 ACMP0L Block Diagram
Preliminary
to ACMP1_L
registers [629:624] registers [623:618]
OA0_Out
00
GPIO
01
Internal VDD
10
registers [617:616]
registers [615:614]
6-bit Hysteresis Selection
Selectable Gain
+
Vref
pUp
-
Low Power ACMP
GPIO register [613]
Vref
LPF
1000000
01111110000000
From Connection Matrix Output [89]
ACMP Ready
0
Latch
1
To Connection Matrix Input [56]
register [612] W/S Control
registers [629:624] registers [623:618]
Figure 57: ACMP0L Block Diagram
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9.1.2 ACMP1L Block Diagram
Preliminary
registers [651:646] registers [645:640]
OA1_Out
00
GPIO
01
From ACMP0_L_IN+
10
Temp Sensor
11
registers [639:638]
registers [637:636]
6-bit Hysteresis Selection
Selectable Gain
+
Vref
pUp
-
Low Power ACMP
GPIO register [635]
Vref
LPF
1000000
01111110000000
From Connection Matrix Output [90]
ACMP Ready
0
Latch
1
To Connection Matrix Input [57]
register [634] W/S Control
registers [651:646] registers [645:640]
Figure 58: ACMP1L Block Diagram
9.2 CHOPPER ANALOG COMPARATOR
There is one Chopper Rail-to-Rail Analog Comparator (ACMP) macrocells in the SLG47004. It is possible to use Chopper ACMP to do in system trim by changing the Rheostat resistance in Auto-Trim mode. It is also possible to use a Chopper ACMP as a general purpose analog comparator.
The chopper ACMP power up signal is controlled either by internal Auto-Trim logic (Set 0/1 of Digital Rheostat 0/1) or by matrix input.
The chopper ACMP is automatically powered on during the calibration time to control the up/down signal of the counter/rheostat, when the Auto-Trim is enabled (register [909]= 0).
In order to use Chopper ACMP as a standalone comparator (Auto-Trim mode is disabled, register [909] = 1) user should provide the clock signal to this macrocell. Clock source can be internal oscillators or any pulses from the connection matrix.
Note that clock frequency for the Chopper ACMP shouldn't be greater than fChACMP. Please refer to Table 23.
Output of Chopper ACMP can be optionally inverted by register [882].
The matrix output [85] is used to control chopper ACMP power up signal for the general purpose usage, see Figure 59. It is possible to use the chopper ACMP as a general purpose ACMP after Auto-Trim procedure is completed, since the power up signal is a logic OR of the latched Set (Digital Rheostat 0/1) signal and matrix signal. If Auto-Trim (Set 0/1 of Digital Rheostat 0/1) is disabled and chopper ACMP channel is set to Auto (Channel 0/1), then ACMP output defaults to Channel 0 while Channel 1 is ignored.
The power-up signals need to be active high in order to use the Chopper ACMP. By connecting to signals coming from the Connection Matrix, it is possible to have ACMP be ON continuously, OFF continuously, or switched on periodically based on a
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Preliminary
digital signal coming from the Connection Matrix. When ACMP is powered down, its output is low.
There are no Gain and Hysteresis selection for chopper ACMP compared to the ACMP0L and ACMP1L.
It's possible to select different reference sources for Chopper ACMP. It can be:
external voltage from pin; divided internal voltage from internal reference source (from 32 mV to 2048 mV); divided internal reference voltage from HD Buffer (64 steps); divided VDDA voltage (64 steps). For more information see Section 15.
The positive input of the Chopper ACMP can be connected to the Op Amp0 out or Op Amp1 out or In Amp out, or to the external PIN.
The inputs of Chopper ACMP can be reconfigured while operating in AutoTrim mode. There is one configuration of inputs (Figure 59) for case when Set0 (Digital Rheostat 0) signal is latched, and another configuration of Chopper ACMP inputs when Set1 (Digital Rheostat 1) signal is latched. For example, M1 MUX can be configured to operate with In Amp out when Set0 (Digital Rheostat 0) is latched and Chopper_ACMP+ pin when Set1 (Digital Rheostat 1) is latched. The same way, "-" input of Chopper ACMP can be configured to work with any of possible inputs when Set0 (Digital Rheostat 0) or Set1 (Digital Rheostat 1) are latched.
Note that the default configuration is the configuration for Set0 (Digital Rheostat 0) signal. When Chopper ACMP operates as separate ACMP and AutoTrim function is disabled, inputs of Chopper ACMP are defined by registers [893:892].
Figure 59: Chopper ACMP Block Diagram
9.3 ACMP SAMPLING MODE Both General Purpose Analog Comparators (ACMPL0 and ACMPL1) have an optional sampling mode. In this mode, ACMP is enabled for the shortest amount of time after rising edge at Power Up input to get a valid data. Then ACMP latches its value and goes sleep again.
Registers [610], [632] enable sampling mode for two comparators.
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9.4 ACMP TYPICAL PERFORMANCE
12
Preliminary
10
Propagation Delay (s)
8
High To Low, Overdrive = 10 mV 6
Low to High, Overdrive = 10 mV
High to Low, Overdrive = 100 mV
4
Low to High, Overdrive = 100 mV
2
0
0
512
1024
1536
2048
Vref (mV)
Figure 60: Propagation Delay vs. Vref for ACMPx at T = 25 �C, VDD = 2.4 V to 5.5 V, Hysteresis = 0
190 ACMPx (T = -40�C)
ACMPx (T = 25�C)
170
ACMPx (T = 85�C)
150
Power-On Delay (s)
130
110
90
70 2.4
Datasheet
CFR0011-120-00
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 61: ACMPx Power-On Delay vs. VDD at BG - Forced
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6
4
2
VOFFSET (mV)
0
-2
-4
-6
-8 32
480
1024
1600
2048
Vref (mV)
Figure 62: ACMPx Input Offset Voltage vs. Vref at T = -40 �C to 85 �C, VDD = 2.4 V to 5.5 V, Gain = 1
500
450
400
350
300
250
VOFFSET (V)
200
150
100
50
0
-50
-100
-150
-200
-250 32
480
1024
1600
2048
Vref (mV)
Figure 63: Chopper ACMP Input Offset Voltage vs. Vref at T = -40 �C to 85 �C, VDD = 2.4 V to 5.5 V, Gain = 1
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IDD (A)
8 T = 85 �C T = 25 �C
7.5 T = -40 �C
7
6.5
6
5.5
5
2.5
3
3.5
4
4.5
5
5.5
VDD (V) Figure 64: ACMPx Current Consumption vs. VDD
50
T = 85 �C
T = 25 �C
45
T = -40 �C
40
IDD (A)
35
30
25
2.5
3
3.5
4
4.5
5
5.5
VDD (V) Figure 65: Chopper ACMP Current Consumption vs. VDD (with 2.048 kHz Clock)
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Preliminary
10 Programmable Operational Amplifiers
10.1 GENERAL DESCRIPTION
The SLG47004 contains three operational amplifiers with rail-to-rail input and output. Two of them (Programmable Op Amps) have the additional functions of driving internal analog FETs (Voltage Regulator and Current Sink modes) and Comparator mode. The third Internal Op Amp is an amplifier with internal resistors, and can be configured as a difference amplifier with Gain = 1. All three op amps can function as instrumentation amplifiers. The structures of the op amps are shown in Figure 66 and Figure 67.
Figure 66: Programmable Operational Amplifier OA0, OA1 Internal Circuit
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Figure 67: Internal Operational Amplifier Circuit
Each of the two Programmable Op Amp inputs has a hardware connection to the external pin and an optional connection to the internal voltage reference source, which makes it possible to create precise voltage or current source. For more detailed description of op amp Vref sources see Section 15. The output of the operational amplifier is hardwired to an external pin. This output can also be connected to the Programmable Trim block of rheostat macrocell, ACMP non-inverting input (ACMP0_L+ for OA0, ACMP1_L+ for OA1), or control the corresponding Analog Switch, depending on the mode of operation. Each Programmable Op Amp can also be configured as an analog comparator, in which case its output signal is connected to the Connection Matrix through a dedicated buffer.
Each Programmable Op Amp has a programmable bandwidth that can be set by two register bits. In addition, internal charge pump setting for each Op Amp must be changed according to bandwidth selection, see Table 54.
The bandwidths may vary up to +/-30 % over PVT. Each operational amplifier is factory trimmed. This trimming is independent of the trimming associated with the onboard digital rheostat (system calibration).
The Internal operational amplifier shares its inputs with the Programmable Op Amps outputs. The voltage reference for the internal amplifier can be sourced from either the internal or external Vref. Note that if the internal Vref is used as a source for the instrumentation amplifier Vref, the user can optionally connect this Vref to the output pin, or disconnect the Vref from output pin and use this pin as GPIO.
Also, if the Internal Op Amp is inactive (In Amp Mode is disabled), the user can use the In Amp_Vref pin as GPIO. The In Amp_Out pin can be configured as GPI.
Table 54: Op Amp Bandwidth Settings
Op Amp Bandwidth Selection
Register Bit 128 kHz 512 kHz
2.048 MHz 8.192 MHz
Op Amp0
Bandwidth Selection
Charge Pump Frequency
745 744 955 954
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Op Amp1
Bandwidth Selection
Charge Pump Frequency
747 746 963 962
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
0
Op Amp2 (Internal)
Bandwidth Selection
Charge Pump Frequency
749 748 971 970
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
0
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10.2 MODES OF OPERATION In order to use any of the op amp macrocells in the GreenPAK Designer, the power up signal (PWR_UP) must be set to logic High. By default, all op amp macrocells are turned off after SLG47004 startup. During power-up, outputs of all op amps will remain in a Hi-Z state and then become valid (see parameter ton in Table 22).
Operational amplifiers turn-on time can be decreased by setting register bits [759:757] to 1. In this case op amps analog supporting blocks are always turned on. Note that current consumption of op amp will be increased when op amp is powered down and bits [759:757] is 1 (see Section 3.13).
See the list below for the op amp operation modes:
Operational Amplifier mode; Instrumentation Amplifier mode; Analog Comparator mode; Voltage Regulator mode; Current Sink mode.
10.2.1 Operational Amplifier Mode
In this mode, the Programmable Op Amp operates as a conventional operational amplifier. Also, the Programmable Op Amp can source the corresponding non-inverting ACMP input (see ACMP macrocell settings). The output of the Programmable Op Amp macrocell is in a Hi-Z state while the macrocell is turned off.
Figure 68 shows the example of differential amplifier with input offset voltage compensation with help of digital rheostat and programmable trim block. Zero input voltage equal to output voltage VOUT = VDD/2.
Figure 68: Example of Input Offset Voltage Compensation
10.2.2 Instrumentation Amplifier Mode If this mode is active (Matrix Output [98] is High level), the two Programmable Op Amps and the single Internal Op Amp work together in Instrumentation Amplifier configuration, shown in Figure 69. When power up signal is logic LOW the output of In Amp is in Hi-Z state.
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Figure 69: Instrumentation Amplifier Structure
The absolute value of internal resistors R1, R2, R3, R4 is <RINT> k �20 %. The mismatch between resistors in one IC is <RINT_TL> %. The resistors Rf and Rg are user defined external resistors. The output voltage VOUT of the instrumentation amplifier shown in Figure 69 is
VOUT = (1 + 2Rf / Rg)(VIN+ - VIN-) + VREF
The user can trim both the gain and the offset error of the instrumentation amplifier using two of the Rheostats from the SLG47004. Figure 70 shows the configuration of the instrumentation amplifier in this scenario.
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Figure 70: Instrumentation Operational Amplifier Configuration for Users Trim
Note that in Figure 70, the Demux connects to the Vref external input with an internal buffer (register [756] = 1). This allows us to eliminate the influence of resistor divider Rdiv and Rheostat0 on instrumentation amplifier.
It is possible to use a built-in Auto-Trim function for either setting the zero point of the Wheatstone bridge sensor using the In Amp or tuning a system output voltage to the desired level. However, the following limitations exist for using the built-in AutoTrim function to trim both total system offset and system gain errors:
- The Auto-Trim procedures of total offset compensation and system gain error must be done iteratively starting and finishing with the total offset compensation: 1st iteration - offset compensation, 2nd iteration - gain trim, 3rd iteration - offset compensation. Extra iterations can be added to achieve a better accuracy. The last iteration should be an offset compensation.
- Total system offset (sensor offset + Op Amp1 offset + Op Amp2 offset) must not be greater than Vsensor_output_range/2.
It's possible to power external components like bridge or ADC from internal HD Buffer of SLG47004 to improve accuracy of system.
10.2.3 Analog Comparator Mode Both operational amplifiers have an Analog Comparator mode in which they work as conventional rail-to-rail comparators.
10.2.4 Voltage Regulator Mode
In this mode, the op amp output drives P-FET (part of Analog Switch). Note that FETs of Analog Switches have different resistances. Analog Switch 0 has Rds_PMOS << Rds_NMOS, while Analog Switch 1 has Rds_NMOS << Rds_PMOS. That's why it is recommended to implement voltage regulator mode using Analog Switch 0. In this mode the op amp output is High when the macrocell is turned off. Figure 71 (A) shows the typical implementation of the voltage source function. Optionally, the
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
user can use this mode to implement a constant current source with load connected to ground (Figure 71, B, C). Note that op amp must operate in operational amplifier mode (register 750 = 0 for Op Amp0, register 751 = 0 for Op Amp1).
Figure 71: Typical Implementation of Voltage Regulator (A) and Current Sources (B, C)
Note that in this mode only an enhanced P channel FET of An_Sw_0 is used.
10.2.5 Current Sink Mode
Also, the op amp output can drive the N-FET (part of the Analog Switch) in order to implement a constant current sink. Note that FETs of Analog Switches have different resistances. Analog Switch 0 has Rds_PMOS << Rds_NMOS, while Analog Switch 1 has Rds_NMOS << Rds_PMOS. That's why it is recommended to implement current sink mode using Analog Switch 1. In this mode, the op amp output is LOW when the macrocell is turned off. Figure 72 (A) shows a typical implementation of this Current Sink Function. Note that op amp must operate in operational amplifier mode (register 750 = 0 for Op Amp0, register 751 = 0 for Op Amp1).
Datasheet
CFR0011-120-00
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Figure 72: Constant Current Sink Note that in this mode only an enhanced N channel FET of An_Sw_1 is used.
10.3 OP AMPS TYPICAL PERFORMANCE TA = 25 �C, VDDA = 5.0 V, VSS = GND, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 80 pF, unless otherwise stated.
Offset Voltage (�V) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
275
250 Opampx, 128 kHz, 2.4 V
225
Opampx, 128 kHz, 5.5 V
200
175
150
125
100
75
50
25
0
T (�C) Figure 73: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 128 kHz
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Offset Voltage (�V) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
250
225
Opampx, 512 kHz, 5.5 V
Opampx, 512 kHz, 2.4 V 200
175
150
125
100
75
50
25
0
T (�C) Figure 74: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 512 kHz
Offset Voltage (�V) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
225
200
175
Opampx, 2 MHz, 5.5 V
Opampx, 2 MHz, 2.4 V 150
125
100
75
50
25
0
T (�C) Figure 75: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 2 MHz
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Offset Voltage (�V) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
200 Opampx, 8 MHz, 2.4 V
175 Opampx, 8 MHz, 5.5 V
150
125
100
75
50
25
0
T (�C) Figure 76: Op Ampx Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 8 MHz
Offset Voltage (�V) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
250
225
200
175
150
125
100
75 Internal OA, 128 kHz, 2.4 V
50 Internal OA, 128 kHz, 5.5 V
25
0
T (�C)
Figure 77: Internal Op Amp Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 128 kHz
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Offset Voltage (�V) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
225
200
175
150
125
100
75
Internal OA, 512 kHz, 2.4 V
50
Internal OA, 512 kHz, 5.5 V
25
0
T (�C) Figure 78: Internal Op Amp at Input CM Voltage = VDD/2, BW = 512 kHz
250 225 200 175 150 125 100
75 50 25
0
Datasheet
CFR0011-120-00
Offset Voltage (�V) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
Internal OA, 2 MHz, 2.4 V Internal OA2, 2 MHz, 5.5 V
T (�C)
Figure 79: Internal Op Amp at Input CM Voltage = VDD/2, BW = 2 MHz
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Offset Voltage (�V) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
200
Internal OA, 8 MHz, 2.4 V
175
Internal OA, 8 MHz, 5.5 V
150
125
100
75
50
25
0
T (�C) Figure 80: Internal Op Amp Input Offset Voltage vs. TA at Input CM Voltage = VDD/2, BW = 8 MHz
110
100
90
80
70
Input Offset Voltage (V)
60
50
40
OAx, 128 kHz, 2.4 V
30
OAx, 512 kHz, 2.4 V
OAx, 2 MHz, 2.4 V
20
OAx, 8 MHz, 2.4 V
10
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Input CM Voltage (V)
Figure 81: OpAmp0, 1 Input Offset Voltage vs. Input CM Voltage at T = 25 �C, VDDA = 2.4 V
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Input Offset Voltage (V)
110
100
90
80
70
60
50
40
OAx, 128 kHz, 5.5 V
30
OAx, 512 kHz, 5.5 V
OAx, 2 MHz, 5.5 V
OAx, 8 MHz, 5.5 V 20
10
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
Input CM Voltage (V)
Figure 82: OpAmp0, 1 Input Offset Voltage vs. Input CM Voltage at T = 25 �C, VDDA = 5.5 V
Input Offset Voltage (V)
130
120
110
100
90
80
70
60
50
Internal OA, 512 kHz, 2.4 V 40
Internal OA, 8 MHz, 2.4 V
30
Internal OA, 2 MHz, 2.4 V
Internal OA, 128 kHz, 2.4 V 20
10
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Input CM Voltage (V)
Figure 83: Internal OpAmp Input Offset Voltage vs. Input CM Voltage at T = 25 �C, VDDA = 2.4 V
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Input Offset Voltage (V)
130
120
110
100
90
80
70
60
50
Internal OA, 512 kHz, 5.5 V 40
Internal OA, 8 MHz, 5.5 V
30
Internal OA, 2 MHz, 5.5 V
Internal OA, 128 kHz, 5.5 V 20
10
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
Input CM Voltage (V)
Figure 84: Internal OpAmp Input Offset Voltage vs. Input CM Voltage at T = 25 �C, VDDA = 5.5 V
40
T = -40�C 39
T = 25�C
38
T = 85�C
Quiescent Current (A)
37
36 35 34
33 32 31
30
2.5
2.8
3.1
3.4
3.7
4
4.3
4.6
4.9
5.2
5.5
VDD (V)
Figure 85: Quiescent Current vs. Power Supply Voltage for BW = 128 kHz
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
96 T = -40�C T = 25�C
94 T = 85�C
92
Quiescent Current (A)
90
88
86
84
82
2.5
2.8
3.1
3.4
3.7
4
4.3
4.6
4.9
5.2
5.5
VDD (V)
Figure 86: Quiescent Current vs. Power Supply Voltage for BW = 512 kHz
Quiescent Current (A)
246
T = -40�C
244
T = 25�C
242
T = 85�C
240
238
236
234
232
230
228
226
2.5
2.8
3.1
3.4
3.7
4
4.3
4.6
4.9
5.2
5.5
VDD (V)
Figure 87: Quiescent Current vs. Power Supply Voltage for BW = 2 MHz
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
650 T = -40�C
640
T = 25�C
T = 85�C
630
Quiescent Current (A)
620
610
600
590
580
570
2.5
2.8
3.1
3.4
3.7
4
4.3
4.6
4.9
5.2
5.5
VDD (V)
Figure 88: Quiescent Current vs. Power Supply Voltage or BW = 8 MHz
Phase (�)
Gain (dB)
140
200
130
Gain, BW = 128 kHz, VDD = 2.4 V
Gain, BW = 128 kHz, VDD = 3.3 V
120
150
Gain, BW = 128 kHz, VDD = 5.5 V
110 Phase, BW = 128 kHz, VDD = 2.4 V
100
Phase, BW = 128 kHz, VDD = 3.3 V
100
90
Phase, BW = 128 kHz, VDD = 5.5 V
80
70
50
60
50
0
40
30
-50
20
10 -100
0
-10
-20
-150
-30
-40 0.001
0.01
0.1
1
10
100
1000
10000
100000 1000000 10000000
Frequency (Hz)
Figure 89: OA0 Open Loop Gain and Phase vs. Frequency for BW = 128 kHz
-200 100000000
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Phase (�)
Gain (dB)
140
200
130
Gain, BW = 512 kHz, VDD = 2.4 V
120
Gain, BW = 512 kHz, VDD = 3.3 V 150
110
Gain, BW = 512 kHz, VDD = 5.5 V
Phase, BW = 512 kHz, VDD = 2.4 V
100
Phase, BW = 512 kHz, VDD = 3.3 V
100
90
Phase, BW = 512 kHz, VDD = 5.5 V
80
70
50
60
50
0
40
30
-50
20
10 -100
0
-10
-20
-150
-30
-40
-200
0.001
0.01
0.1
1
10
100
1000
10000
100000 1000000 10000000 100000000
Frequency (Hz)
Figure 90: OA0 Open Loop Gain and Phase vs. Frequency for BW = 512 kHz
Phase (�)
Gain (dB)
140
200
130
Gain, BW = 2 MHz, VDD = 2.4 V
Gain, BW = 2 MHz, VDD = 3.3 V 120
150 Gain, BW = 2 MHz, VDD = 5.5 V
110 Phase, BW = 2 MHz, VDD = 2.4 V
100
Phase, BW = 2 MHz, VDD = 3.3 V
100
90
Phase, BW = 2 MHz, VDD = 5.5 V
80 50
70
60
50
0
40
30 -50
20
10 -100
0
-10 -150
-20
-30
-40
-200
0.001
0.01
0.1
1
10
100
1000
10000
100000
1000000
10000000
Frequency (Hz)
Figure 91: OA0 Open Loop Gain and Phase vs. Frequency for BW = 2 MHz
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Phase (�)
Gain (dB)
140 130 120 110 100
90 80 70 60 50 40 30 20 10
0 -10 -20 -30 -40
0.001
200 Gain, BW = 8 MHz, VDD = 2.4 V Gain, BW = 8 MHz, VDD = 3.3 V
150 Gain, BW = 8 MHz, VDD = 5.5 V Phase, BW = 8 MHz, VDD = 2.4 V Phase, BW = 8 MHz, VDD = 3.3 V
100 Phase, BW = 8 MHz, VDD = 5.5 V
50
0
-50
-100
-150
-200
0.01
0.1
1
10
100
1000
10000
100000 1000000 10000000
Frequency (Hz)
Figure 92: OA0 Open Loop Gain and Phase vs. Frequency for BW = 8 MHz
140 130 120 110 100
90 80 70 60 50 40 30 20 10
0 -10 -20 -30 -40
0.001
Datasheet
CFR0011-120-00
Gain (dB)
200 Gain, BW = 128 kHz, VDD = 2.4 V
Gain, BW = 128 kHz, VDD = 3.3 V
Gain, BW = 128 kHz, VDD = 5.5 V
150
Phase, BW = 128 kHz, VDD = 2.4 V
Phase, BW = 128 kHz, VDD = 3.3 V
Phase, BW = 128 kHz, VDD = 5.5 V
100
50
Phase (�)
0
-50
-100
-150
-200
0.01
0.1
1
10
100
1000
10000
100000 1000000 10000000
Frequency (Hz)
Figure 93: OA1 Open Loop Gain and Phase vs. Frequency for BW = 128 kHz
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Phase (�)
Gain (dB)
140 130 120 110 100
90 80 70 60 50 40 30 20 10
0 -10 -20 -30 -40
0.001
200 Gain, BW = 512 kHz, VDD = 2.4 V
Gain, BW = 512 kHz, VDD = 3.3 V
Gain, BW = 512 kHz, VDD = 5.5 V
150
Phase, BW = 512 kHz, VDD = 2.4 V
Gain, BW = 512 kHz, VDD = 3.3 V
Gain, BW = 512 kHz, VDD = 5.5 V
100
50
0
-50
-100
-150
-200
0.01
0.1
1
10
100
1000
10000
100000
1000000 10000000
Frequency (Hz)
Figure 94: OA1 Open Loop Gain and Phase vs. Frequency for BW = 512 kHz
Phase (�)
Gain (dB)
140
200
Gain, BW = 2 MHz, VDD = 2.4 V 130
Gain, BW = 2 MHz, VDD = 3.3 V
120
Gain, BW = 2 MHz, VDD = 5.5 V
150
110
Phase, BW = 2 MHz, VDD = 2.4 V
100
Phase, BW = 2 MHz, VDD = 3.3 V
Gain, BW = 2 MHz, VDD = 5.5 V
100
90
80
70
50
60
50
0
40
30
-50
20
10 -100
0
-10
-20
-150
-30
-40
-200
0.001
0.01
0.1
1
10
100
1000
10000
100000
1000000 10000000
Frequency (Hz)
Datasheet
CFR0011-120-00
Figure 95: OA1 Open Loop Gain and Phase vs. Frequency for BW = 2 MHz
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Phase (�)
Gain (dB)
140
200
Gain, BW = 8 MHz, VDD = 2.4 V 130
Gain, BW = 8 MHz, VDD = 3.3 V
120
Gain, BW = 8 MHz, VDD = 5.5 V
150
110
Phase, BW = 8 MHz, VDD = 2.4 V
100
Phase, BW = 8 MHz, VDD = 3.3 V
Phase, BW = 8 MHz, VDD = 5.5 V
100
90
80
70
50
60
50
0
40
30
-50
20
10 -100
0
-10
-20
-150
-30
-40
-200
0.001
0.01
0.1
1
10
100
1000
10000
100000
1000000
10000000
Frequency (Hz)
Figure 96: OA1 Open Loop Gain and Phase vs. Frequency for BW = 8 MHz
10 0
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100
0.01
Datasheet
CFR0011-120-00
PSRR (dB)
BW = 128 kHz BW = 512 kHz BW = 2 MHz BW = 8 MHz
0.10
1.00
10.00
100.00
f (kHz)
Figure 97: PSRR vs. Frequency VDD = 2.4 V to 5.5 V
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (5 V/div)
Time (2 s/div)
Figure 98: 0.1 Hz to 10 Hz Noise, BW = 128 kHz
Voltage (5 V/div)
Datasheet
CFR0011-120-00
Time (2 s/div)
Figure 99: 0.1 Hz to 10 Hz Noise, BW = 512 kHz
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (5 V/div)
Time (2 s/div)
Figure 100: 0.1 Hz to 10 Hz Noise, BW = 2 MHz
Voltage (5 V/div)
Datasheet
CFR0011-120-00
Time (2 s/div)
Figure 101: 0.1 Hz to 10 Hz Noise, BW = 2 MHz
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Channel Separation (dB)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
10
BW = 128 kHz BW = 512 kHz BW = 2 MHz BW = 8 MHz
100
1 000
10 000
100 000
f (Hz)
Figure 102: Channel Separation vs. Frequency
1 000 000
10 000 000
700 600 500 400 300 200 100
0 10
Datasheet
CFR0011-120-00
Input Voltage Noise Density (nV/Hz)
BW = 128 kHz BW = 512 kHz BW = 2 MHz BW = 8 MHz
100
1 000
10 000
100 000
f (Hz)
Figure 103: Op Ampx Noise Voltage Density vs. Frequency
1 000 000
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Slew Rate (mV/s) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
85
80
75
70
65
128 kHz, 5.5 V, Falling
60
128 kHz, 5.5 V, Rising
128 kHz, 3.3 V, Falling
128 kHz, 3.3 V, Rising 55
128 kHz, 2.4 V, Falling
128 kHz, 2.4 V, Rising
50
T (�C) Figure 104: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 k for BW = 128 kHz
Slew Rate (mV/�s) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
340
320
300
280
260
512 kHz, 5.5 V, Falling
512 kHz, 5.5 V, Rising
512 kHz, 3.3 V, Falling
240
512 kHz, 3.3 V, Rising
512 kHz, 2.4 V, Falling
512 kHz, 2.4 V, Rising
220
T (�C) Figure 105: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 k for BW = 512 kHz
Datasheet
CFR0011-120-00
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Slew Rate (mV/�s) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
2100 1900 1700 1500
2 MHz, 5.5 V, Falling 2 MHz, 5.5 V, Rising 2 MHz, 3.3 V, Rising 2 MHz, 2.4 V, Rising 2 MHz, 3.3 V, Falling 2 MHz, 2.4 V, Falling
1300
1100
900
700
T (�C) Figure 106: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 k for BW = 2 MHz
Slew Rate (mV/�s) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
5400 4900 4400 3900 3400 2900 2400 1900 1400
900
8 MHz, 5.5 V, Rising 8 MHz, 3.3 V, Rising 8 MHz, 2.4 V, Rising 8 MHz, 5.5 V, Falling 8 MHz, 2.4 V, Falling 8 MHz, 3.3 V, Falling
T (�C) Figure 107: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 k for BW = 8 MHz
Datasheet
CFR0011-120-00
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (10 mV/div)
Time (20 s/div)
Figure 108: Small Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 128 kHz
Voltage (10 mV/div)
Time (20 s/div)
Figure 109: Small Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 512 kHz
Datasheet
CFR0011-120-00
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (10 mV/div)
Time (10 s/div)
Figure 110: Small Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 2 MHz
Voltage (10 mV/div)
Time (10 s/div)
Figure 111: Small Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 8 MHz
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (10 mV/div)
Time (5 s/div)
Figure 112: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 128 kHz
Voltage (10 mV/div)
Time (5 s/div)
Figure 113: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 512 kHz
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (10 mV/div)
Time (5 s/div)
Figure 114: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 2 MHz
Voltage (10 mV/div)
Time (0.2 s/div)
Figure 115: Small Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 8 MHz
Datasheet
CFR0011-120-00
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (500 mV/div)
Time (20 s/div)
Figure 116: Large Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 80 pF, BW = 128 kHz
Voltage (500 mV/div)
Time (20 s/div)
Figure 117: Large Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 80 pF, BW = 512kHz
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (500 mV/div)
Time (20 s/div)
Figure 118: Large Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 80 pF, BW = 2 MHz
Voltage (500 mV/div)
Time (20 s/div)
Figure 119: Large Signal Inverting Step Response G = -1 V/V, RL = 50 k, CL = 80 pF, BW = 8 MHz
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (500 mV/div)
Time (20 s/div)
Figure 120: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 128 kHz
Voltage (500 mV/div)
Time (20 s/div)
Figure 121: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 512 kHz
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (500 mV/div)
Time (5 s/div)
Figure 122: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 2 MHz
Voltage (500 mV/div)
Time (2.5 s/div)
Figure 123: Large Signal Non-Inverting Step Response G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 8 MHz
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (1 V/div)
Time (60 s/div)
Figure 124: Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 128 kHz
Voltage (1 V/div)
Time (60 s/div)
Figure 125: Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 512 kHz
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (1 V/div)
Time (30 s/div)
Figure 126: Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 2 MHz
Voltage (1 V/div)
Time (15 s/div)
Figure 127: Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 8 MHz
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (1 V/div)
Time (60 s/div)
Figure 128: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 128 kHz
Voltage (1 V/div)
Time (60 s/div)
Figure 129: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 512 kHz
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (1 V/div)
Time (30 s/div)
Figure 130: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 2 MHz
Voltage (1 V/div)
Time (15 s/div)
Figure 131: Non-Inverting Overload Recovery G = -1 V/V, RL = 50 k, CL = 60 pF, BW = 8 MHz
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Overshoot (%)
80
Overshoot (40 mV p-p)
70
Overshoot (100 mV p-p)
Undershoot (40 mV p-p) 60
Undershoot (100 mV p-p)
50
40
30
20
10
0 100
1000 CLOAD (pF)
10000
Figure 132: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 128 kHz
80
Overshoot (40 mV p-p)
70
Overshoot (100 mV p-p)
Undershoot (40 mV p-p) 60
Undershoot (100 mV p-p)
50
Overshoot (%)
40
30
20
10
0 100
1000 CLOAD (pF)
10000
Figure 133: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 512 kHz
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Overshoot (%)
90
Overshoot (40 mV p-p) 80
Overshoot (100 mV p-p)
70
Undershoot (100 mV p-p)
Undershoot (40 mV p-p) 60
50
40
30
20
10
0 100
1000 CLOAD (pF)
10000
Figure 134: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 2 MHz
Overshoot (%)
90
80
70
60
50
40
Undershoot (40 mV p-p) 30
Overshoot (40 mV p-p) 20
10
0
100
470
CLOAD (pF)
Figure 135: Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V, G = 1 V/V, BW = 8 MHz
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
220
Output CM Voltage Low, Rload = 600 , VDD = 5.5 V
210
Output CM Voltage Low, Rload = 600 , VDD = 3.3 V
200
Output CM Voltage Low, Rload = 600 , VDD = 2.4 V
190
180
Output Voltage (mV)
170
160
150
140
130
120
110
100
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 136: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 128 kHz, RLOAD = 600
Output Voltage (mV)
2.9
2.6
2.3
2
1.7
1.4
Output CM Voltage Low, Rload = 50 k, VDD = 5.5 V 1.1
Output CM Voltage Low, Rload = 50 k, VDD = 3.3 V Output CM Voltage Low, Rload = 50 k, VDD = 2.4 V 0.8
0.5
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 137: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 128 kHz, RLOAD = 50 k
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Output Voltage (mV)
360
350
Output CM Voltage High, Rload = 600 , VDD = 5.5 V
340
Output CM Voltage High, Rload = 600 , VDD = 3.3 V
Output CM Voltage High, Rload = 600 , VDD = 2.4 V 330
320
310
300
290
280
270
260
250
240
230
220
210
200
190
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 138: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 128 kHz, RLOAD = 600
5
4.5
Output Voltage (mV)
4
3.5
Output CM Voltage High, Rload = 50 k, VDD = 5.5 V Output CM Voltage High, Rload = 50 k, VDD = 2.4 V 3 Output CM Voltage High, Rload = 50 k, VDD = 3.3 V
2.5
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 139: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 128 kHz, RLOAD = 50 k
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Output Voltage (mV)
180
Output CM Voltage Low, Rload = 600 , VDD = 5.5 V
170
Output CM Voltage Low, Rload = 600 , VDD = 3.3 V
Output CM Voltage Low, Rload = 600 , VDD = 2.4 V
160
150
140
130
120
110
100
90
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 140: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 512 kHz, RLOAD = 50 k
2.5
2
Output Voltage (mV)
1.5
Output CM Voltage Low, Rload = 50 k, VDD = 5.5 V 1
Output CM Voltage Low, Rload = 50 k, VDD = 3.3 V
Output CM Voltage Low, Rload = 50 k, VDD = 2.4 V
0.5
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 141: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 512 kHz, RLOAD = 50 k
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
290
Output CM Voltage High, Rload = 600 , VDD = 5.5 V Output CM Voltage High, Rload = 600 , VDD = 3.3 V 270 Output CM Voltage High, Rload = 600 , VDD = 2.4 V
250
Output Voltage (mV)
230
210
190
170
150
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 142: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 512 kHz, RLOAD = 600
4.4
4.1
3.8
Output Voltage (mV)
3.5
3.2
2.9
2.6
Output CM Voltage High, Rload = 50 k, VDD = 5.5 V
Output CM Voltage High, Rload = 50 k, VDD = 2.4 V
Output CM Voltage High, Rload = 50 k, VDD = 3.3 V 2.3
2
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 143: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 512kHz, RLOAD = 50 k
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Output Voltage (mV)
140 Output CM Voltage Low, Rload = 600 , VDD = 5.5 V Output CM Voltage Low, Rload = 600 , VDD = 3.3 V
130 Output CM Voltage Low, Rload = 600 , VDD = 2.4 V
120
110
100
90
80
70
60
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 144: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 2 MHz, RLOAD = 600
2.5
2
Output Voltage (mV)
1.5
1
Output CM Voltage Low, Rload = 50 k, VDD = 5.5 V
0.5
Output CM Voltage Low, Rload = 50 k, VDD = 3.3 V
Output CM Voltage Low, Rload = 50 k, VDD = 2.4 V
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 145: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 2 MHz, RLOAD = 50 k
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
220
200
180
Output Voltage (mV)
160
140
120
Output CM Voltage High, Rload = 600 , VDD = 5.5 V
Output CM Voltage High, Rload = 600 , VDD = 2.4 V
Output CM Voltage High, Rload = 600 , VDD = 3.3 V
100
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 146: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 2 MHz, RLOAD = 600
3.6
3.4
3.2
3
Output Voltage (mV)
2.8
2.6
2.4
2.2
2
Output CM Voltage High, Rload = 50 k, VDD = 5.5 V
Output CM Voltage High, Rload = 50 k, VDD = 2.4 V
1.8
Output CM Voltage High, Rload = 50 k, VDD = 3.3 V
1.6
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 147: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 2 MHz, RLOAD = 50 k
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Output Voltage (mV)
100
Output CM Voltage Low, Rload = 600 , VDD = 5.5 V
Output CM Voltage Low, Rload = 600 , VDD = 3.3 V
90
Output CM Voltage Low, Rload = 600 , VDD = 2.4 V
80
70
60
50
40
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 148: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 8MHz, RLOAD = 600
1.7
1.5
1.3
Output Voltage (mV)
1.1
0.9
0.7
Output CM Voltage Low, Rload = 50 k, VDD = 5.5 V
Output CM Voltage Low, Rload = 50 k, VDD = 3.3 V
Output CM Voltage Low, Rload = 50 k, VDD = 2.4 V 0.5
0.3
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 149: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 8 MHz, RLOAD = 50 k
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
130
Output CM Voltage High, Rload = 600 , VDD = 5.5 V
Output CM Voltage High, Rload = 600 , VDD = 3.3 V
120
Output CM Voltage High, Rload = 600 , VDD = 2.4 V
110
Output Voltage (mV)
100
90
80
70
60
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 150: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 8 MHz, RLOAD = 600
16
14
12
Output Voltage (mV)
10
8 Output CM Voltage High, Rload = 50 k, VDD = 5.5 V
Output CM Voltage High, Rload = 50 k, VDD = 2.4 V
6
Output CM Voltage High, Rload = 50 k, VDD = 3.3 V
4
2
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (�C)
Figure 151: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 8 MHz, RLOAD = 50 k
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Overload Recovery Time (s)
60
50
128 kHz, Rising 40
512 kHz, Rising 2 MHz, Rising 8 MHz, Rising 30
20
10
0
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 152: Overload Recovery Time vs. Power Supply Voltage RL= 50 k; G = 1 V/V, Rising
1.4
128 kHz, Falling
1.2
512 kHz, Falling
2 MHz, Falling
8 MHz, Falling
1
Overload Recovery Time (s)
0.8
0.6
0.4
0.2
0
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 153: Overload Recovery Time vs. Power Supply Voltage RL= 50 k; G = 1 V/V, Falling
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (1 V/div)
Time (10 s/div)
Figure 154: Output Response to Power Down Signal G = 1 V/V; RL = 50 k; CL = 20 pF; VIN = VS/2, BW = 128 kHz
Voltage (1 V/div)
Time (2 s/div)
Figure 155: Output Response to Power Down Signal G = 1 V/V; RL = 50 k; CL = 20 pF; VIN = VS/2, BW = 512 kHz
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Voltage (1 V/div)
Time (1 s/div)
Figure 156: Output Response to Power Down Signal G = 1 V/V; RL = 50 k; CL = 20 pF; VIN = VS/2, BW = 2 MHz
Voltage (1 V/div)
Time (1 s/div)
Figure 157: Output Response to Power Down Signal G = 1 V/V; RL = 50 k; CL = 20 pF; VIN = VS/2, BW = 8 MHz
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
40
Turn-On Time @ T = -40 �C
Turn-On Time @ T = 25 �C
Turn-On Time @ T = 85 �C
35
Turn-Off Time @ T = -40 �C
Turn-Off Time @ T = 25 �C
Turn-Off Time @ T = 85 �C
30
Turn -On/Off Time (s)
25
20
15 2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 158: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 128 kHz
20
18
16
Turn-Off Time @ T = -40 �C
14
Turn-Off Time @ T = 25 �C
Turn-Off Time @ T = 85 �C
Turn-On Time @ T = -40 �C
12
Turn-On Time @ T = 25 �C
Turn -On/Off Time (s)
10
8
6
4
2
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 159: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 512 kHz
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Turn -On/Off Time (s)
18 16 14 12 10
8 6 4 2 0
2.4
Turn-Off Time @ T = -40 �C Turn-Off Time @ T = 25 �C Turn-Off Time @ T = 85 �C Turn-On Time @ T = -40 �C Turn-On Time @ T = 25 �C Turn-On Time @ T = 85 �C
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 160: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 2 MHz
18
16
14
Turn -On/Off Time (s)
12
10
Turn-Off Time @ T = -40 �C
Turn-Off Time @ T = 25 �C
Turn-Off Time @ T = 85 �C
8
Turn-On Time @ T = -40 �C
Turn-On Time @ T = 25 �C
Turn-On Time @ T = 85 �C
6
4
2
0 2.4
Datasheet
CFR0011-120-00
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 161: Opampx Turn-On/Off Time vs. VDD at VIN = VDD/2, BW = 8MHz
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
IDD (A)
600
500 BW = 8 MHz
BW = 2 MHz 400
BW = 512 kHz
BW = 128 kHz 300
200
100
0
2.5
3
3.5
4
4.5
5
5.5
VDD (V) Figure 162: Opamps Quiescent Current Consumption vs. VDD
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
11 Analog Switch Macrocell
11.1 ANALOG SWITCH GENERAL DESCRIPTION The SLG47004 contains two single-pole/single throw (SPST) normally open analog switches (AS). The structure of the Analog Switches is shown in Figure 163 and Figure 164. Each analog switch can be controlled from the following sources: Connection matrix Operational Amplifier macrocell.
Small NMOS (small PMOS) of Analog Switch must be enabled when macrocell is controlled by logic signal from connection matrix. Otherwise, small NMOS (small PMOS) must be disabled when macrocell is controlled by op amp.
Table 55 and Table 56 show possible operation modes of analog switches.
Figure 163: Analog Switch 0 Control Circuit
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Figure 164: Analog Switch 1 Control Circuit
Table 55: Analog Switch 0 Modes of Operation
Mode of Operation Analog Switch mode with big pMOS only (control from connection matrix) Analog Switch mode with all FETs enabled (control from connection matrix) Voltage Regulator mode Half Bridge mode with big pMOS only (control from connection matrix) Half Bridge mode with all FETs enabled (control from connection matrix)
Half Bridge Mode Enable Register [740]
0
0 0 1
1
Matrix/Op Amp Control Register [738]
0
0 1 x
x
Small nMOS Enable
Register [736]
0
1 0 0
1
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 56: Analog Switch 1 Modes of Operation
Mode of Operation Analog Switch mode with big nMOS only (control from connection matrix) Analog Switch mode with all FETs enabled (control from connection matrix) Current Sink mode Half Bridge mode with big nMOS only (control from connection matrix) Half Bridge mode with all FETs enabled (control from connection matrix)
Half Bridge Mode Enable Register [740]
0
0 0 1
1
Matrix/Op Amp Control Register [739]
0
0 1 x
x
Small pMOS Enable
Register [737]
0
1 0 0
1
11.2 HALF BRIDGE MODE
Two switches can be externally connected in series to create a half bridge. Please refer to tables Table 55 and Table 56 to enable half bridge mode. Additional logic will be connected to the analog switches to simplify control. Figure 165 shows the half bridge structure with two analog switches.
Datasheet
CFR0011-120-00
Figure 165: Structure of Half Bridge
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
11.3 ANALOG SWITCHES TYPICAL PERFORMANCE
70
Preliminary
60 AS0 VDD = 2.4 V
50
AS1 VDD = 2.4 V
RDS(ON) ()
40
30
20
10
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
VIN (V)
Figure 166: Typical RON vs. Input Voltage (Vi) for Vi = 0 to VDDA, ILOAD = 1 mA, VDDA = 2.4 V
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Figure 167: Typical RON vs. Input Voltage (Vi) for Vi = 0 to VDDA, ILOAD = 1 mA, VDDA = 5.5 V
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Turn -On Time (ns)
240
220
AS0 (T = -40 �C)
AS0 (T = 25 �C)
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Figure 168: Turn-On Time vs. VDD at RLOAD = 100 to GND, VIN = VDD/2
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Figure 169: Turn-Off Time vs. VDD at RLOAD = 100 to GND, VIN = VDD/2
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12 Digital Rheostats and Programmable Trim Block
The SLG47004 contains two 10-bit Digital Rheostats. The structure of both macrocells is shown in Figure 170. The range of digital code that corresponds to the rheostat resistance ranges from 0 to 1023 (1024 taps). Code 0 corresponds to the minimum resistance between the RHx_A and RHx_B terminals. As the code value increases, the resistance between the RHx_A and RHx_B terminals monotonically increases. Consequently, when the code value decreases, the resistance between the RH0_A and RH0_B terminals decreases as well (see Section 12.2). The voltage on any rheostat pin can be in the range from AGND to VDDA, as well as be dynamically changed during operation.
To guarantee proper operation of digital rheostats charge pump must be turned on (matrix input [86] must be logic High or registers [912] = 1, [913] = 1). Optionally user can turn off rheostats charge pump to decrease energy consumption. But it's strongly recommended to use the charge pump if VDD < 4.5 V.
It is possible to use the rheostat in the following different modes:
Changing the Rheostat value using the I2C interface; Manually changing the rheostat value using clock and up/down signals, similar to the counter; Using the Built-in Auto-Trim mode, where the rheostat value change is done using a special logic based on the signal from
the Chopper ACMP.
The Programmable Trim (PT) blocks of rheostats macrocell contain analog MUXs, digital MUXs, Chopper ACMP, and additional logic. The two analog MUXs (M1 and M2) and the Chopper ACMP are both shared between the two rheostats. All analog and digital MUXs are set by NVM bits and can be overwritten with I2C.
The M_CK0 and M_CK1 MUXs select the clock source from internal pre-dividers of the internal oscillators or from the connection matrix. The internal clock sources for the rheostats are OSC0, OSC0/8, OSC0/64, OSC0/512, OSC0/4096, OSC0/32768, OSC0/262144, OSC1, OSC1/8, OSC1/64, and OSC1/512. The PT blocks of the rheostat use the same clock scheme as Counter/Delay Macrocells (refer to 16.5). M_CH0 and M_CH1 select the Chopper comparator or a matrix output as the signal source for the main rheostat up/down counter direction. The output of the Chopper ACMP is connected with the Up/Down inputs of the PT blocks by default. The output of the Chopper ACMP can be optionally inverted by setting register [882] to "1".
M1 MUX selects the input for the Chopper comparator to be connected either internally to one of 3 integrated op amps (Op Amp0 out, Op Amp1 out, In Amp Out) or externally to a PIN. M2 MUX is simplified symbol of Chopper ACMP reference selection blocks. The Chopper ACMP reference ("-" input) can be: analog signal from pin, divided internal Vref voltage (6-bit divider), or divide VDDA voltage (6-bit divider). In Auto-Trim mode each of Rheostats has it own settings for Chopper ACMP inputs. For more information about Chopper ACMP Vref see Section 9.2.
The power-up signal for the Chopper ACMP can be handled either by matrix output signal or Set0/Set1 signal from the PT macrocell. In Auto-Trim mode (Auto_Cal _Dis_RHx NVM bit = 0) additional internal logic enables the clocking of the corresponding PT macrocell counter and disables clocking when one of the stop conditions is reached. See a detailed description in Section 12.4. In Figure 170 when Auto_Cal _Dis_RHx NVM bit = 0 (Auto-Trim mode is enabled), the clocking pulses for the internal PT macrocell counter are under control of additional logic. When Auto_Cal _Dis_RHx NVM bit = 1 (AutoTrim mode is disabled), all additional logics (Set signal, internal Set signal, Idle/Active signal) operate the same way, but clock pulses are always enabled and generated externally by the user. Calibration channel can be selected automatically (1st channel is channel 0, second channel is channel 1) or can be set manually by registers [893:892].
The inputs of Chopper ACMP can be reconfigured while operating in Auto-Trim mode. There is one configuration of inputs (M1, M2 configuration, Figure 170) for the case when Set0 signal is latched, and another configuration of M1, M2 MUXs when Set1 signal is latched. For example, M1 MUX can be configured to operate with In Amp out when Set0 is latched and Chopper_ACMP+ pin when Set1 is latched. The same way, M2 can be configured to work with any of M2 inputs when Set0 or Set1 are latched. Note that the default configuration is the configuration for Set0 signal. When Chopper ACMP operates as separate ACMP and Auto-Trim function is disabled, M1 and M2 MUXs operates with configuration for Set0 signal.
Keep in mind that two Auto-Trim processes cannot be done simultaneously. When the Auto-Trim process for one rheostat is active, all signals on the Set input for another rheostat will be ignored. See a detailed description in 12.4.1. The initial user defined value of Digital Rheostat resistance can be programmed into the NVM. The initial value will be loaded during the PowerOn event and this value will be used as the initial rheostat resistance, as well as a starting point for count down or count up.
Both read and write operations are allowed for rheostat resistance value, stored in NVM. Also, both read and write operations are allowed for current rheostat resistance value. RH0 read operation - registers [1561:1552], write operation - registers [1545:1536]. RH1 read operation - registers [1689:1680], write operation - registers [1673:1664].
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Figure 170: Programmable Trim Blocks and Digital Rheostat's Internal Circuit
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PT macrocell signals:
"Set": external Set signal begins the Auto-Trim process when Auto_Cal _Dis_RHx bit is cleared (registers [901]). Otherwise, this signal has no effect. The behavior of the PT macrocell in Auto-Trim mode is described below.
"Reload": when Reload goes high the rheostat value stored in the MTP NVM will be loaded into the rheostat (Register and Counter) overwriting any current setting. This signal is edge sensitive. It has no effect while the Auto-Trim procedure is active. For detailed information see Section 12.3.
"Program": when Program goes high the Internal Counter value of the rheostat will be programmed into the MTP overwriting any current value in the NVM. This procedure can be done up to 1000 times. This signal is also edge sensitive. It has no effect while the Auto-Trim procedure is active. For detailed information see 12.3. To enable "Program" signal from connection matrix RH_PRB register must be cleared (RH_PRB [1796] = 0). If RH_PRB [1796] register is set to 1, the access to NVM is disabled for "Program" signal. Refer to Section 19.6 for more details.
"Clock": this input has the following options: the PT macrocell can be clocked internally or from matrix. When clocked internally, the clock is automatically enabled/disabled by the Set input logic in Auto-Trim mode. The internal clock is synchronized with the Chopper ACMP clock.
"Up/Down": the rheostat counter counts up when the signal is High and down when the signal is Low. "Idle/Active": this is the connection matrix input, that is logic HIGH by default. It goes LOW with rising edge on SET input if Auto-Trim mode is enabled (Auto_Cal _Dis_RHx NVM bit = 0). After the end of Auto-Trim procedure (one of stop conditions occurs) this signal sets to logic HIGH again. "FIFO nReset": low level at this input clears internal FIFO buffer for commands Reload and Program for both rheostats. User
should provide high logic level at this input for the normal rheostat operation.
There is also an overflow protection option, for which the counter will stop counting up when the maximum value (0x3FF) is reached or stop counting down when the minimum value (0x00) is reached. The digital rheostat is initialized/powered in the first place. The rheostat value is Hi-Z (or highest resistance if it is impossible to disconnect the rheostat) during the Power-On sequence.
12.1 POTENTIOMETER MODE
This mode allows two 2-pin rheostats to work as one 3-pin potentiometer. When this mode is active (register [917] = 1), user changes the value of RH0 internal counter. In this mode, the value of RH1 counter is the inverted value of RH0 counter (Figure 171). Note that the RH0_B pin and the RH1_A pin must be connected externally. Also, note that the Auto-Trim function isn't allowed in Potentiometer Mode.
Figure 171: Rheostats in Potentiometer Mode
12.2 CALCULATING ACTUAL RESISTANCE
In applications where the absolute rheostat resistance is critical, the user can calculate it using the rheostat tolerance data, the minimum rheostat resistance, and the desired code. The 16-bit tolerance data for both rheostats has been programmed into registers 0xE6 to 0xE9. These registers can be used to calculate the total rheostat resistance. The 16th bit defines the sign (0 = +, 1 = -) of the tolerance. The other fifteen bits correspond to the absolute value of the rheostat tolerances variation from 100 k measured at 25 �C.
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B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Tolerance Sign (0 : +) | (1 : -)
Tolerance Magnitude
Figure 172: Rheostat Tolerance Registers
Note that the rheostat tolerance data is programmed into registers 0xE6 to 0xE9. To avoid losing this tolerance data, special attention must be paid when erasing and reprogramming page 14 in the NVM.
The rheostat value at a given code depends on the total digital rheostat resistance. The equations below can be used to calculate the rheostat resistance.
RCode = (RDR - RDR MIN) x (code/1023) + RDR MIN
RDR = 100 x 103 + (signRH_Tolerance x RRH_Tolerance)
where: RCode - Rheostat Resistance at a Given Code; RDR - Total Digital Rheostat Resistance; RDR MIN - Minimum Rheostat Resistance; code - Rheostat Position Ranging from 0x000 to 0x3FF; signRH_Tolerance - the MSB of the Rheostat's Tolerance Data; RRH_Tolerance - the 15 LSBs of the Rheostat's Tolerance Data.
For example, let's say that 0x2B67 has been written into the rheostat tolerance registers within the GreenPAK's NVM. B15 corresponds to a positive sign while B14:0 translates into a decimal value of 11111. RDR calculates to approximately 111,111 and can be used with the minimum rheostat resistance to calculate the resistance at a given code. Note that the minimum rheostat resistance must be measured to obtain precise results, but a range is provided in Table 23.
12.3 DIGITAL RHEOSTAT VALUE SELF-PROGRAMMING INTO THE NVM
The current value of rheostat is stored in the Internal Counter. This value can be programmed into the MTP by setting logic HIGH at "Program" input. In this case, SLG47004 will generate a specific memory control sequence to rewrite a new value into the NVM. There is a separate NVM page that is dedicated for the Digital Rheostat value.
There is a dedicated bit RH_PRB, that enables/disables "Program" signal of PT block to change NVM rheostats resistance values. If RH_PRB[1796] = 0, "Program" signal is enabled. If RH_PRB[1796] = 1, "Program" signal is disabled. Note that RH_PRB bit has no effect on I2C access to NVM. To enable/disable I2C access to rheostat resistance value, stored in NVM, user must change NPRB0, NPRB1 bits. Refer to Section 18.5.
SLG47004 can latch up to four "Program" and "Reload" signals of RH0 and RH1 (Reload RH0, Program RH0, Reload RH1, Program RH1). The same signal can't be latched second time, until it is processed. All latched signals will be processed in the order of arrival (FIFO buffer), since only one signal can access NVM at the same time. If Auto-Trim process of RH0 or RH1 is active and one or more "Reload", "Program" signals for corresponding rheostat come, SLG47004 will wait until the end of AutoTrim process and then process will latch "Reload", "Program" signals. Set0 or Set1 signal can be latched at any time and processed when rheostat clocking isn't disabled by "Program" or "Reload" signals.
User can clear the FIFO buffer by setting low logic level at FIFO nReset input of PT blocks.
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Figure 173: Flowchart of "Program" and "Reload" Signals
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Figure 174: Example of Latching and Processing "Program" and "Reload" Signals
Since the access to the MTP NVM is disabled during NVM self-programming procedure, the device will not acknowledge it via I2C interface. This can be used to determine when the erase/programming cycle is completed (this feature can be used to maximize bus throughput). ACK polling can be used in this case.
If the device is still busy during the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and control byte must be re-sent. Once the cycle is complete, then the device will return the ACK and the master can proceed with the next Read or Write command.
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12.4 TRIMMING PROCESS USING PROGRAMMABLE TRIM BLOCK There are several ways of implementing the trimming process using the PT block. One of the essential features of the PT macrocell is the Auto-Trim function described below. It allows the user to design simple calibration circuits for a wide variety of applications.
12.4.1 Trimming Process with Auto-Trim Option Enabled
For using the Auto-Trim function the following preliminary steps must be taken:
Clear Auto_Cal _Dis_RHx NVM bit (0 is default value). This enables Auto-Trim function. Configure M1 MUX (registers [875:872]). It can be user system voltage feedback. If Auto-Trim function is used for two
rheostats, M1 MUX must be configured for both rheostats (for cases when Set0 is latched and when Set1 is latched). Configure M2 MUX. It can be user desired set point threshold. If Auto-Trim function is used for two rheostats, M2 MUX must
be configured for both rheostats (for cases when Set0 is latched and when Set1 is latched). Remember, that M2 MUX is simplified symbol of Chopper ACMP reference selection blocks. Configure M_CH0 (M_CH1) MUX to work with Chopper ACMP (M_CH0,1 MUXs are configured to work with Chop ACMP by default). Configure inverting or non-inverting Chopper ACMP output (registers [923], [920] and [882]); Select clock source (internal clock from internal pre-dividers or from connection matrix). Note that in Auto-Trim mode clock source frequency for the PT Block is limited by the Chopper Comparator time response. Therefore, the clock source frequency must not be greater than <fChACMP> kHz. Start the Auto-Trim process by setting the Set0 (Set1) input of PT block to a High level. The Auto-Trim process stops if one of three stop conditions occur:
1) 2nd time change on Up/Down input at the moment of rising edge on Clock input (see Figure 175).
2) the value of rheostat reaches its maximum (1023).
3) the value of rheostat reaches its minimum (0).
Stop conditions result in a change of the Idle/Active signal, which resets the internal Auto-Trim logic.
Note that the Set input is edge sensitive, but if the user keeps a High logic level at this input after reaching the set point, the PT block will continue to operate and continue to switch rheostat around the set point.
To start new Auto-Trim process user should reapply a High level on Set input.
The detailed flow of Auto-Trim process is shown in Figure 175, Figure 176, Figure 177.
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Figure 175: Example of Auto-Trim Process for a Single Rheostat
The key events of the Auto-Trim process are the following (see Figure 175):
1. During the startup event the SLG47004 loads the rheostat value from NVM to Internal Counter. In this example this value is 512.
2. The Trim process starts with a rising edge on Set input. This Set signal is latched until the end of the Auto-Trim process. The Set signal will enable the Chopper ACMP and the Vref, if they were not enabled earlier. After a ready signal from analog blocks (BG_OK & Vref_OK), the clock pulses for the internal counter are enabled. The counter starts to count up or down depending on the level at the Up/Down input. If user selected the "Internal Clock" option for Clock input, these clock pulses are generated automatically during trim time. Each rising edge of the Clock pulse changes the value of the counter and, consequently, the value of the rheostat.
3. There are three stop conditions for the Auto-Trim process:
1) A subsequent change on Up/Down input at the moment of rising edge on Clock input.
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2) The value of the rheostat reaches its maximum (1023).
3) The value of the rheostat reaches its minimum (0).
If the Set input signal is shorter than the trim time, the Auto-Trim process stops automatically after a stop condition occurs (event 3, Figure 175). However, if a stop condition comes and High logic level holds on the Set input, the rheostat value will be switched near the set point until a Low level on the Set input occurs (event 7, Figure 175). Note that the Idle/Active signal changes its level to High (Auto-Trim is done) even if the user keeps a High logic level at the Set input.
After the end of the Auto-Trim process, Chopper ACMP powers down and its output goes to a Low logic level.
4. After a rising edge at the "Reload" signal, the value from NVM is copied to the rheostat Internal Counter overwriting current rheostat settings.
5. During this event user starts Auto-Trim process, but holds High logic level at Set input for a time longer than Auto-Trim process.
6. A "Program" signal comes. The "Program" command is latched and will be executed at the end of the Auto-Trim process.
7. The Auto-Trim process stops when the signal at the Set input goes to Low level. Note that a logic High level at the Set input was held longer than the time that was needed for the Auto-Trim process. At the end of the Auto-Trim process, the SLG47004 starts the NVM self-programming routine to copy the rheostat value from Reg LATCH to MPT NVM.
Figure 176 shows a similar Auto-Trim example. The only difference is that the user defined clock source as "External clock" from connection matrix. The clock pulses are present at the Clock input all the time, but have effect (rheostat value changes) during Trim time only. The stop condition for this case is the following: PT block reaches boundary value of 1023 and the logic level at change Set input is Low.
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Figure 176: Example of Auto-Trim Process with External Clock Signal
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Figure 177 shows Auto-Trim process flow for two rheostats.
Preliminary
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Figure 177: Example of Auto-Trim Process for Two Rheostats
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12.4.2 I2C Controlled Trimming Process with Auto-Trim Option Enabled
It's possible to start the Auto-Trim process via I2C interface. In this case the user must configure the SLG47004 PT macrocell as described in Section 12.4.1. To start the Auto-Trim process via I2C interface the user can use I2C virtual inputs.
Also, an external I2C master device can force the SLG47004 to reload the rheostat value from NVM ("Reload" command) or to copy rheostat value to NVM ("Program" command) using I2C virtual inputs.
See Figure 178 for an example of the Auto-Trim process under external I2C master control.
Figure 178: Example of Auto-Trim Process via I2C
The key events of the Auto-Trim process under external I2C master control are as follows:
1. During the startup event the SLG47004 loads the rheostat value from the NVM to the Internal Counter. In the example this value is 512.
2. I2C master sends the message to set High one of the I2C virtual inputs that is connected with Set input of the PT macrocell.
3. After the I2C message is received and processed, the I2C virtual input and the Set input will be at a High logic level. The AutoTrim process begins.
4. I2C master clears the virtual input and, consequently, the Set input. The Auto-Trim process goes on until a trim stop condition occurs.
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5. The Auto-Trim process ends. The stop condition in this example is a 2nd change on Up/Down input at the moment of rising edge on the Clock input and Low level at the Set input.
12.4.3 Changing Rheostat Value Directly via I2C The user can perform their own trim algorithm setting the rheostat value directly via I2C interface. In the example below, a microcontroller uses a user defined trim algorithm to change SLG47004`s rheostat via I2C interface (Figure 179). Note that during Auto-Trim process SLG47004 will return nACK, if master tries to get access (both read and write) to rheostats registers via I2C.
Figure 179: Example of Hardware Configuration
Note that the PT Registers are allowed to read and write via communication interface, if not protected.
The preliminary configuration of system shown in Figure 179 is the following:
Auto_Cal _Dis_RHx bit is set to 1 (disable Auto-Trim mode); M1 MUX (registers [875:872])) is configured to work with user system voltage feedback (pin Chop_ACMP+); M2 MUX is configured to work with SLG47004 programmable Vref. Note that M2 MUX is simplified symbol of Chopper ACMP
reference selection blocks (see Section 9.2); Chopper ACMP is powered up from connection matrix. Chopper ACMP out is connected to output pin; No Clock source for PT block.
The example of a system trim via I2C is shown in the figure below. In this example the I2C master uses a simple approximation algorithm for reaching the set point. Every next step the rheostat code is changed by �(Previous rheostat code step value/2). The sign depends on the Chopper ACMP output. The algorithm steps are as follows:
Set rheostat code to 1024/2 = 512; Wait until the system settles down and check if Chopper ACMP output = 1, then Next_rheostat_code = 512 + (512/2). If
Chopper ACMP output = 0, then Next_rheostat_code = 512 - (512/2); Repeat previous step until Next_rheostat_code = Prev_rheostat_code � 1;
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Figure 180: Example of User Specific Trimming Process under I2C Master Control
The key events of a user specific trimming process under I2C master control are as follows:
1. During the startup event the SLG47004 loads the rheostat value from NVM to Internal Counter. In the example this value is 512.
2. I2C master writes a new value to the Rheostat's Internal Counter according to Chopper ACMP output. Note that the minimum time for changing the rheostat code depends on the time response of the user system.
3. After the trim process is completed, the I2C master sets the I2C virtual input to logic "1". This input is connected to the "Reload" signal of the PT macrocell. The rising edge on this input starts the NVM self-programming routine.
4. The I2C master clears the I2C virtual input.
Additionally, the I2C Master macrocell can use internal resources such as an ADC to read the system data, find the error, and then adjust the Rheostat value. Also, it is possible to change the Rheostat value for different conditions. For example, the I2C Master macrocell can change the Rheostat value based on the temperature change to reduce the system error.
12.5 USING CHOPPER ACMP
When the Auto-Trim Function is disabled, the Chopper comparator can be used as a standalone analog comparator. Inputs of the Chopper ACMP are selected by the M1 and M2 analog MUXs. Output of the Chopper ACMP can be optionally inverted by register [882]. This comparator output is the input [55] of the connection matrix. In case of a disabled Auto-Trim Function, the power up source for the Chopper ACMP comes from connection matrix. Please refer to Section 9 for more details.
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DNL (LSB)
0.2
VDD = 2.4 V
0.15
VDD = 5.5 V
0.1
0.05
0
-0.05
-0.1
-0.15 0
64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024
Code (Decimal)
Figure 181: DNL vs. Digital Code, Rheostat Mode (VAB = 1 V) at T = 25 �C
0.8
VDD = 2.4 V 0.7
VDD = 5.5 V
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2 0
64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 Code (Decimal)
Figure 182: INL vs. Digital Code, Rheostat Mode (VAB = 1 V) at T = 25 �C
INL (LSB)
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DNL (LSB)
0.2
VDD = 2.4 V
0.15
VDD = 5.5 V
0.1
0.05
0
-0.05
-0.1
-0.15 0
64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 Code (Decimal)
Figure 183: DNL vs. Digital Code, Potentiometer Mode (VAB = 1 V) at T = 25 �C
1
VDD = 2.4 V 0.9
VDD = 5.5 V 0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0 0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 Code (Decimal) Figure 184: INL vs. Digital Code, Potentiometer Mode (VAB = 1 V) at T = 25 �C
INL (LSB)
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Rheostat Mode TempCo (ppm/�C)
600 550 500 450 400 350 300 250 200 150 100
50 0 0
64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 Code (Decimal)
Figure 185: (RAB/RAB)/TA Rheostat Mode Tempco
1
0.9 VDD = 5.5 V
0.8
VDD = 2.4 V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
T (�C) Figure 186: RHx Zero Scale Error vs. Temperature (VIN = 1 V)
Zero-Scale Error (LSB) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
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Voltage (0.2 V/div)
Gain (dB)
Time (50 s/div)
Figure 187: Transition Glitch in Worst Case (Code = 511 to Code = 512)
10 0
-10 -20 -30 -40
-50 10
100
1 000
10 000
100 000
1 000 000
f (Hz)
Figure 188: Gain vs. Frequency (Code = 512) at T = 25 �C, VDDA = 5 V
10 000 000
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Preliminary
Settling Time (s)
6.0
UP 5.5
DOWN 5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VDD (V)
Figure 189: RHx Settling Time vs. VDD at ILOAD = 1 mA, T = 25 �C
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Preliminary
13 Programmable Delay/Edge Detector
The SLG47004 has a programmable time delay logic cell available, that can generate a delay that is selectable from one of four timings (time 2) configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay patterns, rising edge detection, falling edge detection, both edge detection, and both edge delay. These four patterns can be further modified with the addition of delayed edge detection, which adds an extra unit of delay, as well as glitch rejection during the delay period. See Figure 191 for further information.
Note: The input signal must be longer than the delay, otherwise it will be filtered out.
registers [865:864] Delay Value Selection
registers [867:866] Edge Mode Selection
From Connection Matrix Output [58]
Programmable
IN
Delay OUT
To Connection Matrix Input [30]
Figure 190: Programmable Delay 13.1 PROGRAMMABLE DELAY TIMING DIAGRAM - EDGE DETECTOR OUTPUT
IN
Rising Edge Detector time1
Falling Edge Detector
width
time1
width
Both Edge Detector
Both Edge Delay time2
Please refer to Table 11.
time2 time1 is a fixed value time2 delay value is selected via register
Figure 191: Edge Detector Output
Edge Detector Output
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Preliminary
14 Additional Logic Function. Deglitch Filter
The SLG47004 has one Deglitch Filter macrocell with inverter function that is connected directly to the Connection Matrix inputs and outputs. In addition, this macrocell can be configured as an Edge Detector, with the following settings:
Rising Edge Detector Falling Edge Detector Both Edge Detector Both Edge Delay
From Connection Matrix Output [59]
Filter
R 0
C
1 Edge Detector Logic
registers [871:870] register [868]
0 1 register [869]
To Connection Matrix Input [31]
Figure 192: Deglitch Filter or Edge Detector
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
15 Voltage Reference
15.1 VOLTAGE REFERENCE OVERVIEW
The SLG47004 has a Voltage Reference (Vref) Macrocell to provide reference to analog comparators and operational amplifiers. The macrocell also has the option to output reference voltages on external pins (see Table 1). Vref0 and Vref1 share output buffers with Temperature sensor. Note that user can use any of output buffers, but Temperature sensor is calibrated for Vref1 output buffer. See Table 57 for the available selections for each analog comparator. Also, see Figure 193, Figure 194, and Figure 195, which show the reference output structure.
Also there is a high drive voltage reference macrocell called HD Buffer. The purpose of this macrocell is to provide stable voltage to the relatively high-power load (Please refer to the Table 18). HD Buffer has shared voltage reference source with the Op Amp0 Vref. User can select output voltage in the range from VDD/64 to VDD with a step VDD/64, or output voltage in a range from 32 mV to 2.048 V with a step 32 mV (see Figure 195).
15.2 VREF SELECTION TABLE
Table 57: Vref Selection Table
SEL[5:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Vref 0.032 0.064 0.096 0.128 0.16 0.192 0.224 0.256 0.288 0.32 0.352 0.384 0.416 0.448 0.48 0.512 0.544 0.576 0.608 0.64 0.672 0.704 0.736 0.768
0.8 0.832 0.864 0.896 0.928 0.96
SEL[5:0] 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
Vref 1.088 1.12 1.152 1.184 1.216 1.248 1.28 1.312 1.344 1.376 1.408 1.44 1.472 1.504 1.536 1.568
1.6 1.632 1.664 1.696 1.728 1.76 1.792 1.824 1.856 1.888 1.92 1.952 1.984 2.016
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Table 57: Vref Selection Table(Continued)
SEL[5:0] 30 31 32
Vref 0.992 1.024 1.056
SEL[5:0] 63 64
Preliminary
Vref 2.048 External
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15.3 VREF BLOCK DIAGRAM
Preliminary
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Figure 193: Generalized Vref Structure
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Figure 194: ACMP0L, ACMP1L Voltage Reference Block Diagram
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Figure 195: HD Buffer and Chopper ACMP Reference Block Diagram
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Figure 196: Operational Amplifiers Voltage Reference Block Diagram
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15.4 VOLTAGE REFERENCE TYPICAL PERFORMANCE
Preliminary
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16 r.Clocking
350
Preliminary
300
250
VREF OUT, mV
200
150
VDD = 5 V
100
VDD = 3.3 V
VDD = 2.5 V 50
0
0
1
2
3
4
5
I, mA
Figure 197: Typical Load Regulation, Vref = 320 mV, T = -40 �C to +85 �C, Buffer - Enable
700
600
500
VREF OUT, mV
400
300
200 VDD = 5 V
100
VDD = 3.3 V
VDD = 2.5 V
0
0
1
2
3
4
5
I, mA
Figure 198: Typical Load Regulation, Vref = 640 mV, T = -40 �C to +85 �C, Buffer - Enable
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Preliminary
VREF OUT, mV
1400
1200
1000
800
600
400 VDD = 5 V
VDD = 3.3 V 200
VDD = 2.5 V
0
0
1
2
3
4
5
I, mA
Figure 199: Typical Load Regulation, Vref = 1280 mV, T = -40 �C to +85 �C, Buffer - Enable
2100
1800
1500
VREF OUT, mV
1200
900
600 VDD = 5 V
300
VDD = 3.3 V
VDD = 2.5 V
0
0
1
2
3
4
5
I, mA
Figure 200: Typical Load Regulation, Vref = 2048 mV, T = -40 �C to +85 �C, Buffer - Enable
16.1 OSC GENERAL DESCRIPTION
The SLG47004 has three internal oscillators to support a variety of applications:
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Oscillator0 (2.048 kHz) Oscillator1 (2.048 MHz) Oscillator2 (25 MHz)
There are two divider stages for each oscillator that give the user flexibility for introducing clock signals to connection matrix, as well as various other Macrocells. The pre-divider (first stage) for Oscillator allows the selection of /1, /2, /4, or /8 to divide down frequency from the fundamental. The second stage divider has an input of frequency from the pre-divider, and outputs one of eight different frequencies divided by /1, /2, /3, /4, /8, /12, /24, or /64 on Connection Matrix Input lines [52], [53], and [54]. Please see Figure 204 for more details on the SLG47004 clock scheme.
Oscillator2 (25 MHz) has an additional function of 100 ns delayed startup, which can be enabled/disabled by register [713]. This function is recommended to use when analog blocks are used along with the Oscillator.
The Matrix Power-down/Force On function allows switching off or force on the oscillator using an external pin. The Matrix Powerdown/Force On (Connection Matrix Output [91], [92], [93]) signal has the highest priority. The OSC operates according to the Table 58.
Table 58: Oscillator Operation Mode Configuration Settings
POR
External Clock
Selection
Signal From Connection
Matrix
Register: Power-Down or Force On by Matrix In-
put
0
X
X
X
Register: Auto PowerOn or Force
On
X
1
1
X
X
X
1
0
1
0
X
1
0
1
1
X
1
0
0
X
1
1
0
0
X
0
1
0
0
X
0
Note 1 The OSC will run only when any macrocell that uses OSC is powered on.
OSC Enable Signal from
CNT/DLY Macrocells
X X
X X X CNT/DLY requires OSC CNT/DLY does not require OSC
OSC Operation
Mode
OFF Internal OSC
is OFF, logic is ON
OFF ON ON ON
OFF
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16.2 OSCILLATOR0 (2.048 KHZ)
From Connection Matrix Output [91]
OSC Power Mode register [720]
Power-down/Force On Matrix Output control register [721]
Auto Power-On 0 Force Power-On 1
PD/FORCE ON
OSC0 (2.048 kHz)
OUT
Ext. Clock
registers [725:724]
0
DIV /1 /2 /4 /8
1
Pre-divider
2.048 kHz Pre-divided Clock
0
/ 2
1
Preliminary
Ext. CLK Sel register [722]
/ 3
2
To Connection Matrix
/ 4
3
Input [52]
OUT0
/ 8
4
OUT1
To Connection Matrix
Input [58]
/ 12
5
/ 24
6
/ 64
7
registers [728:726] Second Stage registers [733:731]
Divider
Figure 201: Oscillator0 Block Diagram
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16.3 OSCILLATOR1 (2.048 MHZ)
From Connection Matrix Output [92]
OSC Power Mode register [688]
Power-down/Force On Matrix Output control register [689]
Auto Power-On 0 Force Power-On 1
PD/FORCE ON
OSC1 (2.048 MHz)
OUT
Ext. Clock
registers [692:691]
0
DIV /1 /2 /4 /8
1
Pre-divider
2.048 MHz Pre-divided Clock
0
/ 2
1
Preliminary
Ext. CLK Sel register [690]
/ 3
2
/ 4
3
To Connection Matrix Input [53]
OUT0
/ 8
4
OUT1
To Connection Matrix Input [59]
/ 12
5
/ 24
6
/ 64
7
registers [695:693]
Second Stage Divider
registers [703:701]
Figure 202: Oscillator1 Block Diagram
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16.4 OSCILLATOR2 (25 MHZ)
From Connection Matrix Output [93]
OSC Power Mode register [704]
Power-down/Force On Matrix Output control register [705]
Auto Power-On 0 Force Power-On 1
PD/FORCE ON
OSC2 (25 MHz)
OUT
Startup delay
registers [709:708]
0
DIV /1 /2 /4 /8
register [713]
1
Pre-divider
Ext. Clock
Ext. CLK Sel [706]
25 MHz Pre-divided Clock
0
/ 2
1
/ 3
2
/ 4
3
To Connection Matrix Input [54]
/ 8
4
/ 12
5
/ 24
6
/ 64
7
registers [712:710] Second Stage
Divider
Figure 203: Oscillator2 Block Diagram
16.5 CNT/DLY CLOCK SCHEME
Each CNT/DLY within Multi-Function macrocell has its own additional clock divider connected to oscillators pre-divider. Available dividers are: OSC0/1, OSC0/8, OSC0/64, OSC0/512, OSC0/4096, OSC0/32768, OSC0/262144 OSC1/1, OSC1/8, OSC1/64, OSC1/512 OSC2/1, OSC2/4
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25 MHz Pre-divided clock
Div4
2.048 MHz Pre-divided clock
Div8 Div64 Div512
2.048 kHz Pre-divided clock
Div8 Div64
Div512
Div4096
Div32768
CNT (x-1) overflow
Div262144
from Connection Matrix Out (separate for each CNT/DLY macrocell)
none
[3:0]
0
1
2
3
CNT/DLY/
4
ONESHOT/
5
FREQ_DET/
6
DLY_EDGE_DET
7
CNT overflow
8
9
10
11
12
13
14 15
CNT0/CNT1/CNT2/CNT3/CNT4/ CNT5/CNT6/RH0 CLK/RH1 CLK
Figure 204: Clock Scheme 16.6 EXTERNAL CLOCKING The SLG47004 supports several ways to use an external, higher accuracy clock as a reference source for internal operations.
16.6.1 IO1 Source for Oscillator0 (2.048 kHz)
When register [722] is set to 1, an external clocking signal on IO0 will be routed in place of the internal oscillator derived 2.048 kHz clock source. See Figure 201. The high and low limits for frequency that can be selected are 0 MHz and 10 MHz.
16.6.2 IO3 Source for Oscillator1 (2.048 MHz)
When register [690] is set to 1, an external clocking signal on IO1 will be routed in place of the internal oscillator derived 2.048 MHz clock source. See Figure 202. The high and low limits for frequency that can be selected are 0 MHz and 10 MHz.
16.6.3 IO2 Source for Oscillator2 (25 MHz)
When register [706] is set to 1, an external clocking signal on IO2 will be routed in place of the internal oscillator derived 25 MHz clock source. See Figure 203. The external frequency range is 0 MHz to 20 MHz at VDD = 2.4 V, 0 MHz to 30 MHz at VDD = 3.3 V, 0 MHz to 50 MHz at VDD = 5.0 V.
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16.7 OSCILLATORS POWER-ON DELAY
Preliminary
OSC enable CLK
Power-On Delay
Power-On Delay (s)
Figure 205: Oscillator Startup Diagram Note 1 OSC power mode: "Auto Power-On". Note 2 "OSC enable" signal appears when any macrocell that uses OSC is powered on
950 900 850 800 750 700 650 600 550 500
2.4 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
VDD (V)
Figure 206: OSC0 Maximum Power-On Delay vs. VDD at T = 25 �C, OSC0 = 2.048 kHz
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Power-On Delay (ns)
560 540 520 500 480 460 440 420 400
2.4 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
VDD (V)
Figure 207: OSC1 Oscillator Maximum Power-On Delay vs. VDD at T = 25 �C, OSC1 = 2.048 MHz
Power-On Delay (ns)
160 140 120 100
80 60 40 20
0 2.4 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
VDD (V)
Figure 208: OSC2 Maximum Power-On Delay vs. VDD at T = 25 �C, OSC2 = 25 MHz
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16.8 OSCILLATORS ACCURACY Note: OSC power setting: Force Power-On; Clock to matrix input - enable; Bandgap: turn on by register - enable.
2.2 2.18
Fmax @ VDD = 2.5 V to 5 V 2.16
Ftyp @ VDD = 3.3 V 2.14
Fmin @ VDD = 2.5 V to 5 V 2.12
2.1 2.08 2.06 2.04 2.02
2 1.98 1.96 1.94 1.92
1.9
f (kHz) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
T (�C) Figure 209: OSC0 Frequency vs. Temperature, OSC0 = 2.048 kHz
f (MHz) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
2.15
2.13
2.11
2.09
2.07
2.05
2.03
2.01 Fmax @ VDD = 2.5 V to 5 V
1.99 Ftyp @ VDD = 3.3 V
1.97 Fmin @ VDD = 2.5 V to 5.5 V
1.95
T (�C) Figure 210: OSC1 Frequency vs. Temperature, OSC1 = 2.048 MHz
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26.1 25.9 25.7 25.5 25.3 25.1 24.9 24.7 24.5 24.3 24.1 23.9 23.7
8 7 6 5 4 3 2 1
Datasheet
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�% -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
f (MHz) -40 -30 -20 -10
0 10 20 30 40 50 60 70 80
Fmax @ VDD = 2.5 V to 5 V Ftyp @ VDD = 3.3 V Fmin @ VDD = 3.3 V
T (�C) Figure 211: OSC2 Frequency vs. Temperature, OSC2 = 25 MHz
2.048 kHz Total Error @ VDD = 2.3 V to 5.5 V 25 MHz Total Error @ VDD = 2.3 V to 5.5 V 2.048 MHz Total Error @ VDD = 2.3 V to 5.5 V
T (�C)
Figure 212: Oscillators Total Error vs. Temperature
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Note: For more information see Section 3.8. 16.9 OSCILLATORS SETTLING TIME
488
Preliminary
487
Time (s)
486
485
484
0
1
2
3
4
Period
Figure 213: Oscillator0 Settling Time, VDD = 3.3 V, T = 25 �C, OSC0 = 2 kHz
510
500
490
Time (ns)
480
470
460
450 0
Datasheet
CFR0011-120-00
1
2
3
4
5
6
Period
Figure 214: Oscillator1 Settling Time, VDD = 3.3 V, T = 25 �C, OSC1 = 2 MHz
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Time (ns)
60
55
50
45
40
35
30
25
20
0
1
2
3
4
5
6
7
8
9
10
11
Period
Figure 215: Oscillator2 Settling Time, VDD = 3.3 V, T = 25 �C, OSC2 = 25 MHz (Normal Start)
160
140
120
100
80
60
40
20
0
1
2
3
4
5
6
7
8
Period
Figure 216: Oscillator2 Settling Time, VDD = 3.3 V, T = 25 �C, OSC2 = 25 MHz (Start with Delay)
Time (ns)
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16.10 OSCILLATORS CURRENT CONSUMPTION
Preliminary
IDD (A)
24 22 20 18 16 14 12 10
2.5
24 22 20 18 16 14 12 10
2.5
Datasheet
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IDD (A)
T = 85 �C T = 25 �C T = -40 �C
3
3.5
4
4.5
5
5.5
VDD (V) Figure 217: OSC1 Current Consumption vs. VDD (Pre-Divider = 1)
T = 85 �C T = 25 �C T = -40 �C
3
3.5
4
4.5
5
5.5
VDD (V) Figure 218: OSC1 Current Consumption vs. VDD (Pre-Divider = 4)
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IDD (A)
24
22
20
18
16
T = 85 �C
14
T = 25 �C
T = -40 �C 12
10
2.5
3
3.5
4
4.5
5
5.5
VDD (V) Figure 219: OSC1 Current Consumption vs. VDD (Pre-Divider = 8)
80 75 70 65 60 55 50 45 40 35
2.5
Datasheet
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IDD (A)
T = 85 �C T = 25 �C T = -40 �C
3
3.5
4
4.5
5
5.5
VDD (V) Figure 220: OSC2 Current Consumption vs. VDD (Pre-Divider = 1)
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IDD (A)
60 55 50 45 40 35 30 25 20 15 10
2.5
T = 85 �C T = 25 �C T = -40 �C
3
3.5
4
4.5
5
VDD (V) Figure 221: OSC2 Current Consumption vs. VDD (Pre-Divider = 4)
Preliminary
5.5
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IDD (A)
55
50
45
40
35
T = 85 �C
T = 25 �C
30
T = -40 �C
25 2.5
3
3.5
4
4.5
5
VDD (V) Figure 222: OSC2 Current Consumption vs. VDD (Pre-Divider = 8)
Preliminary
5.5
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Preliminary
17 Power-On Reset
The SLG47004 has a Power-On Reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first ramping to the device, and also while the VDD is falling during Power-down. To accomplish this goal, the POR drives a defined sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of the IOs.
17.1 GENERAL OPERATION
The SLG47004 is guaranteed to be powered down and non-operational when the VDD voltage (voltage on PIN13) is less than Power-Off Threshold (see in Table 6), but not less than -0.6 V. Another essential condition for the chip to be powered down is that no voltage higher (Note) than the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3 V, applying a voltage higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior.
Note: There is a 0.6 V margin due to forward drop voltage of the ESD protection diodes.
To start the POR sequence in the SLG47004, the voltage applied on the VDD should be higher than the Power-On Threshold (Note). The full operational VDD range for the SLG47004 is 2.4 V to 5.5 V. This means that the VDD voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power-On Threshold. After the POR sequence has started, the SLG47004 will have a typical Startup Time (see in Table 6) to go through all the steps in the sequence, and will be ready and completely operational after the POR sequence is complete.
Note: The Power-On Threshold is defined in Table 6.
To power down the chip, the VDD voltage should be lower than the operational and to guarantee that chip is powered down, it should be less than Power-Off Threshold.
All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin configuration at this point in time is defined by the design programmed into the chip. Also, as it was mentioned before, the voltage on PINs can't be bigger than the VDD, this rule also applies to the case when the chip is powered on.
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17.2 POR SEQUENCE The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 223.
VDD
t POR_NVM
(reset for NVM)
t NVM_ready_out
t POR_GPI
(reset for input enable, Digital Rheostat (default value))
t POR_LUT
(reset for LUT/FILTER)
POR_CORE
t
(reset for DLY/OSC/DFF /LATCH/Pipe DLY/ACMP/
Edge Detector in Filter)
t
POR_OUT
(generate low to high to matrix)
t POR_GPO
(reset for output enable)
t
Figure 223: POR Sequence
As can be seen from Figure 223 after the VDD has started ramping up and crossed the Power-On Threshold, first, the on-chip NVM memory is reset. Next, the chip reads the data from NVM and transfers this information to a CMOS LATCH, that serves to configure each macrocell, and the Connection Matrix, which routes signals between macrocells. The third stage causes the reset of the input pins, and then enables them. At that time Digital Rheostats value is set to its default value. After that, the LUTs are reset and become active. After LUTs, the Delay cells, OSCs, DFFs, LATCHES, and Pipe Delay are initialized. Only after all macrocells are initialized, internal POR signal (POR macrocell output) goes from LOW to HIGH (POR_OUT in Figure 223). The last portion of the device to be initialized is the output pins, which transition from high impedance to active at this point.
The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many environmental factors, such as: slew rate, VDD value, temperature, and even will vary from chip to chip (process influence).
17.3 MACROCELLS OUTPUT STATES DURING POR SEQUENCE
To have a full picture of SLG47004 operation during powering and POR sequence refer to Figure 224, which describes the macrocell output states during the POR sequence.
First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output pins which are in high impedance state). On the next step, some of the macrocells start initialization: input pins output state becomes LOW; Digital Rheostats value is set to its default value; LUTs also output LOW. After that input pins are enabled. Next, only LUTs are configured. Then, all other macrocells are initialized. After macrocells are initialized, internal POR matrix signal switches from LOW to HIGH. The last are output pins that become active and determined by the input signals.
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VDD
Guaranteed HIGH before POR_GPI
t
VDD _out to matrix
Unpredictable
Input PIN _out to matrix
t
Unpredictable
Determined by External Signal
t
Digital Rheostats Resistance
LUT/FILTER_out to matrix
Programmable Delay_out to matrix
DFF/LATCH/ACMP/Edge Detector in Filter_out to matrix
Delay_out to matrix
POR_out to matrix
Ext. GPO
Hi-Z
Default Value from NVM
t
Unpredictable
Determined by Input signals
Determined by input signals OUT = IN without Delay
t
Unpredictable
Determined by Input signals Starts to detect input edges
Determined by initial state
t
Unpredictable
Determined by Input signals
Determined by input signals OUT = IN without Delay
t
Unpredictable
Determined by Input signals Starts to detect input edges
t
Unpredictable
Tri-state
t
Determined by input signals
t
Output State Unpredictable
Figure 224: Internal Macrocell States During POR Sequence
17.3.1 Initialization
All internal macrocells by default have initial low level. Starting from indicated power-up time of 1.6 V to 2.07 V, macrocells in SLG47004 are powered on while forced to the reset state. All outputs are in Hi-Z and chip starts loading data from NVM. Then the reset signal is released for internal macrocells and they start to initialize according to the following sequence:
1. Input pins, Pull-up/down, Digital Rheostats, Op Amps. 2. LUTs. 3. DFFs, Delays/Counters, Pipe Delay, OSCs, ACMPs. 4. POR output to matrix. 5. Output pin corresponds to the internal logic.
The Vref output pin driving signal can precede POR output signal going high by 3 �s to 5 �s. The POR signal going high indicates the mentioned power-up sequence is complete.
Note: The maximum voltage applied to any pin should not be higher than the VDD level. There are ESD Diodes between pin
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VDD and pin GND on each pin. Exceeding VDD results in leakage current on the input pin, and VDD will be pulled up, following the voltage on the input pin.
17.3.2 Power-Down
VDD (V)
2 V 1 V
1 V Vref Out Signal
1.53 V 0.97 V
Time
Not guaranteed output state
Figure 225: Power-Down During Power-down macrocells in SLG47004 are powered off after VDD falling down below Power-Off Threshold. Please note, that during a slow rampdown outputs can possibly switch state.
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18 I2C Serial Communications Macrocell
18.1 I2C SERIAL COMMUNICATIONS MACROCELL OVERVIEW
In the standard use case for the GreenPAK devices, the configuration choices made by the user are stored as bit settings in the Non-Volatile Memory (NVM), and this information is transferred at startup time to volatile RAM registers that enable the configuration of the macrocells. Other RAM registers in the device are responsible for setting the connections in the Connection Matrix to route signals in the manner most appropriate for the user's application.
The I2C Serial Communications Macrocell in this device allows an I2C bus Master to read and write this information via a serial channel directly to the RAM registers, allowing the remote re-configuration of macrocells, and remote changes to signal chains within the device.
The I2C bus Master is also able to read and write other register bits that are not associated with NVM memory. As an example, the input lines to the Connection Matrix can be read as digital register bits. These are the signal outputs of each of the macrocells in the device, giving the I2C bus Master the capability to remotely read the current value of any macrocell.
The user has the flexibility to control read access and write access via registers bits registers [1795:1792]. See Section 19 for more details on I2C read/write memory protection.
18.2 I2C SERIAL COMMUNICATIONS DEVICE ADDRESSING
Each command to the I2C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are shown in Figure 226. After the Start bit, the first four bits are a control code. Each bit in a control code can be sourced independently from the register or by value defined externally by IO1, IO2, IO3, and IO4. The LSB of the control code is defined by the value of IO1, while the MSB is defined by the value of IO4. The address source (either register bit or PIN) for each bit in the control code is defined by registers [1019:1016]. This gives the user flexibility on the chip level addressing of this device and other devices on the same I2C bus.The default control code is 0001. The Block Address is the next three bits (A10, A9, A8), which will define the most significant bits in the addressing of the data to be read or written by the command. The last bit in the Control Byte is the R/W bit, which selects whether a read command or write command is requested, with a "1" selecting for a Read command, and a "0" selecting for a Write command. This Control Byte will be followed by an Acknowledge bit (ACK), which is sent by this device to indicate successful communication of the Control Byte data.
In the I2C-bus specification and user manual there are two groups of eight addresses (0000 xxx and 1111 xxx) that are reserved for the special functions, such as a system General Call address. If the user of this device choses to set the Control Code to either "1111" or "0000" in a system with other slave device, please consult the I2C-bus specification and user manual to understand the addressing and implementation of these special functions, to ensure reliable operation.
In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of information, resulting in a total address space of 2K bytes. The valid addresses are shown in the memory map in Figure 236.
With the exception of the Current Address Read command, all commands will have the Control Byte followed by the Word Address.
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Start bit
Control Byte
Acknowledge bit
Word Address
S
X
X
X
X
A 10
A 9
A 8
R/W ACK
A 7
A 0
Control Code
Block Address
Read/Write bit
Figure 226: Basic Command Structure
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18.3 I2C SERIAL GENERAL TIMING
General timing characteristics for the I2C Serial Communications macrocell are shown in Figure 227. Timing specifications can be found in the AC Characteristics, section 3.4.
SCL
tSU STA
SDA IN
SDA OUT
tF tHD STA tAA
tHIGH tHD DAT
tLOW
tSU DAT
tDH
tR
tSU STO tBUF
Figure 227: I2C General Timing Characteristics
18.4 I2C SERIAL COMMUNICATIONS COMMANDS
18.4.1 Byte Write Command
Following the Start condition from the Master, the Control Code [4 bits], the Block Address [3 bits], and the R/W bit (set to "0") are placed onto the I2C bus by the Master. After the SLG47004 sends an Acknowledge bit (ACK), the next byte transmitted by the Master is the Word Address. The Block Address (A10, A9, A8), combined with the Word Address (A7 through A0), together set the internal address pointer in the SLG47004, where the data byte is to be written. After the SLG47004 sends another Acknowledge bit, the Master will transmit the data byte to be written into the addressed memory location. The SLG47004 again provides an Acknowledge bit and then the Master generates a Stop condition. The internal write cycle for the data will take place at the time that the SLG47004 generates the Acknowledge bit.
It is possible to latch all IOs during I2C write command to the register configuration data (block address A10, A9, A8 = 000), register [985] = 1 - Enable. It means that IOs will remain their state until the write command is done.
Bus Activity
Start bit
Control Byte
Acknowledge
Acknowledge
bit
Word Address
bit
SDA LINE
S
X
X
X
X
A 10
A 9
A 8
W
ACK
A 7
A 0
ACK
D 7
Control Code
Block Address
R/W bit = 0
Figure 228: Byte Write Command, R/W = 0
Data
Acknowledge bit
D 0
ACK
P
Stop bit
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18.4.2 Sequential Write Command
The write Control Byte, Word Address, and the first data byte are transmitted to the SLG47004 in the same way as in a Byte Write command. However, instead of generating a Stop condition, the Bus Master continues to transmit data bytes to the SLG47004. Each subsequent data byte will increment the internal address counter, and will be written into the next higher byte in the command addressing. As in the case of the Byte Write command, the internal write cycle will take place at the time that the SLG47004 generates the Acknowledge bit.
Bus Activity
Start bit
Acknowledge
bit
Control Byte
Word Address (n)
SDA LINE
S
X
X
X
X
A 10
A 9
A 8
W ACK
ACK
Data (n)
Data (n + 1)
Acknowledge bit
Data (n + x)
ACK
ACK
ACK P
Control Block Code Address
Write bit
Stop bit
Figure 229: Sequential Write Command
18.4.3 Current Address Read Command
The Current Address Read Command reads from the current pointer address location. The address pointer is incremented at the first STOP bit following any write control byte. For example, if a Sequential Read command (which contains a write control byte) reads data up to address n, the address pointer would get incremented to n + 1 upon the STOP of that command. Subsequently, a Current Address Read that follows would start reading data at n + 1. The Current Address Read Command contains the Control Byte sent by the Master, with the R/W bit = "1". The SLG47004 will issue an Acknowledge bit, and then transmit eight data bits for the requested byte. The Master will not issue an Acknowledge bit, and follow immediately with a Stop condition
Bus Activity
Start bit
Control Byte
Acknowledge bit
Data (n)
Stop bit
SDA LINE
S
X
X
X
X
A 10
A 9
A 8
R ACK
P
Control Code
Block Address
R/W bit = 1
Figure 230: Current Address Read Command, R/W = 1
No Ack bit
18.4.4 Random Read Command
The Random Read command starts with a Control Byte (with R/W bit set to "0", indicating a write command) and Word Address to set the internal byte address, followed by a Start bit, and then the Control Byte for the read (exactly the same as the Byte Write command). The Start bit in the middle of the command will halt the decoding of a Write command, but will set the internal address counter in preparation for the second half of the command. After the Start bit, the Bus Master issues a second control byte with the R/W bit set to "1", after which the SLG47004 issues an Acknowledge bit followed by the requested eight data bits.
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Bus Activity
Start bit
Acknowledge
bit
Control Byte
Word Address (n)
Control Byte
SDA LINE
S
X
X
X
X
A 10
A 9
A 8
W ACK
ACK S
X
X
X
X
A 10
A 9
A 8
R ACK
Data (n)
Stop bit
P
Control Block Code Address
Control Block Code Address
Write bit
Read bit
Figure 231: Random Read Command
No Ack bit
18.4.5 Sequential Read Command
The Sequential Read command is initiated in the same way as a Random Read command, except that once the SLG47004 transmits the first data byte, the Bus Master issues an Acknowledge bit as opposed to a Stop condition in a random read. The Bus Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition.
Bus Activity
Start bit
Acknowledge
bit Control Byte
Data (n)
Data (n + 1)
Data (n + 2)
Data (n + x)
SDA LINE
S
X
X
X
X
A 10
A 9
A 8
R ACK
ACK
ACK
ACK
P
Control Block Code Address
Read bit
Figure 232: Sequential Read Command
Stop bit
No Ack bit
18.4.6 I2C Serial Reset Command
If I2C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including configuration of all macrocells and all connections provided by the Connection Matrix. This is implemented by setting register [984] I2C reset bit to "1", which causes the device to re-enable the Power-On Reset (POR) sequence, including the reload of all register data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has taken place, the contents of register [984] will be set to "0" automatically. The Figure 233 illustrates the sequence of events for this reset function.
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Bus Activity
Start bit
Control Byte
Acknowledge
Acknowledge
bit
Word Address
bit
Data
Acknowledge bit
SDA LINE
S
X
X
X
X
A 10
A 9
A 8
W
ACK
A 7
Not used, set to 0
Control Code
Block Address
Write bit
A 0
ACK
D 7
Internal Reset bit
D 0
ACK
P
Stop bit
by I2C Stop Signal
Reset-bit register output
DFF output gated by stop signal
Internal POR for core only
Figure 233: Reset Command Timing
18.5 CHIP CONFIGURATION DATA PROTECTION
The SLG47004 utilizes a scheme that allows a portion or the entire Register and NVM to be inhibited from being read or written/erased. There are two bytes that define the register and NVM access or change. The second byte NPR defines the chip NVM data configuration read and write protection. The first byte RPR defines the register read and write protection. If desired, the protection lock bit (PRL) can be set so that protection may no longer be modified, thereby making the current protection scheme permanent. The status of the RPR and NPR can be determined by following a Random Read sequence. Changing the state of the RPR and NPR is accomplished with a Byte Write sequence with the requirements outlined in this section.
Special care must be taken when NVM page 14 is rewritten (registers [1919:1792]). This page contains rheostats tolerance data that can be permanently lost during write/erase operation.
The RPR register is located on H'E0 address, while NPR is located on H'E1 address.
The RPR format is shown in Table 59, and the RPR bit functions are included in Table 60.
Table 59: RPR Format
b7
b6
RPR
b5
b4
b3
b2
b1
b0
RH_PRB
RPRB3
RPRB2
RPRB1
RPRB0
* Becomes read only after PRL is high. The content is permanently locked for write and erase after PRL is high.
Table 60: RPR Bit Function Description
Bit
Name
Type
4
RH_PRB
--
R/W*
RPRB3 2k Register R/W*
3:2 RPRB2
Write Selection
Bits
R/W*
Description 0: Program signal from connection matrix is enabled 1: Program signal from connection matrix is disabled
00: 2k register data is unprotected for write; 01: 2k register data is partly protected for write; Please refer to the Table 63. 10: 2k register data is fully protected for write.
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Table 60: RPR Bit Function Description(Continued)
Bit
Name
Type Description
1:0
RPRB1 RPRB0
2k Register Read
Selection Bits
R/W* R/W*
00: 2k register data is unprotected for read; 01: 2k register data is partly protected for read; Please refer to the Table 63. 10: 2k register data is fully protected for read.
The NPR format is shown in Table 61, and the NPR bit functions are included in Table 62.
Table 61: NPR Format
b7
b6
b5
b4
b3
b2
b1
b0
NPR
NPRB1
NPRB0
Table 62: NPR Bit Function Description
Bit
Name
Type Description
1:0
NPRB1 NPRB0
2k NVM Configuration Selection Bits
R/W* R/W*
00: 2k NVM Configuration data is unprotected for read and write/erase; 01: 2k NVM Configuration data is fully protected for read; 10: 2k NVM Configuration data is fully protected for write/erase; 11: 2k NVM Configuration data is fully protected for read and write/erase.
* Becomes read only after PRL is high. The content is permanently locked for write and erase after PRL is high.
The protection selection bits allow different levels of protection of the register and NVM Memory Array.
There is a dedicated bit RH_PRB, that enables/disables "Program" signal of PT block to change NVM rheostats resistance values. If RH_PRB [1796] = 0, "Program" signal is enabled. If RH_PRB [1796] = 1, "Program" signal is disabled. Note that RH_PRB bit has no effect on I2C access to NVM. To enable/disable I2C access to rheostat resistance value, stored in NVM, user must change NPRB0, NPRB1 bits.
The Protect Lock Bit (PRL) is used to permanently lock (for write and erase) the current state of the RPR and NPR,as well as EEPROM protection. A Logic 0 indicates that the protection byte can be modified, whereas a Logic 1 indicates the byte has been locked and can no longer be modified.
In this case it is impossible to erase the whole page E with protection bytes. The PRL is located at E4 address (register [1824]).
18.6 I2C SERIAL COMMAND REGISTER MAP There are nine read/write protect modes for the design sequence from being corrupted or copied. See Table 63 for details.
Table 63: Read/Write Register Protection Options
Protection Modes Configuration
Configurations
Unlock
Partly Lock Read
Partly Lock Write
Partly Lock Read/ Write
Partly Lock Read & Lock Write
Lock Read & Partly
Lock Write
Lock Read
RPR[1:0]
00
01
00
01
01
10
10
RPR[3:2]
00
00
01
01
10
01
00
I2C Byte Write Bit
Masking
R/W R/W R/W R/W
R
W
W
(section 18.7.2)
I2C Serial Reset
Command
R/W R/W R/W R/W
R
W
W
(section 18.4.6)
Lock Write
00 10
R
R
Lock Read/ Write
10 10
-
-
Test Mode
Register Address
-
F6
-
7Bb'0
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Table 63: Read/Write Register Protection Options(Continued)
Protection Modes Configuration
Configurations
Unlock
Partly Lock Read
Partly Lock Write
Partly Lock Read/ Write
Partly Lock Read & Lock Write
Lock Read & Partly
Lock Write
Lock Read
RPR[1:0]
00
01
00
01
01
10
10
RPR[3:2]
00
00
01
01
10
Outputs Latching
During I2C Write
R/W
R/W
R/W
R/W
R
(section18.7)
Connection Matrix
Virtual Inputs
R/W R/W R/W R/W
R
(section 6.3)
RH0_CNT Data
R/W R/W R/W R/W
R
RH1_CNT Data
R/W R/W R/W R/W
R
Macrocells Output
Values (Connection Matrix Inputs,
R
R
R
R
R
section
Counter Current Value
R
R
R
R
R
RH0_CNT Value
R
R
R
R
R
RH1_CNT Value
R
R
R
R
R
Protection Mode
Selection (sections 18.6,
R/W R/W
R
R
R
19.6)
I2C Slave Address R/W
R/W
R
R
R
01
00
W
W
W
W
W
W
W
W
-
-
-
-
R
R
R
R
R
R/W
R
R/W
Pin slave address select
Service page lock RH0 Tolerance Data RH1 Tolerance Data
Protect Mode Config
(RH_PRB,RPR, NPR,WPR)
Page Erase byte Macrocells Inputs
Configuration (Connection Matrix
Outputs)
(section 6.2)
Configuration Bits for All Macrocells
(IOs, ACMPs, Combination
Function Macrocells, and
others)
R/W R R R
R/W* W** R/W
R/W
R/W R R R
R/W* W** W
W
R R R R/W* W** R
R
R R R R/W* W** -
-
R R R R/W* W** -
-
R R R R/W* W** -
-
R/W R R R
R/W* W** W
W
Lock Write
00 10
R
R R R R
R R R R
R
R R R R/W* W**
R
R
Lock Read/ Write
10 10
-
-
R R R7
R
R R R R/W* W**
-
-
Test Mode
Register Address
-
7Bb'1
-
7C
R/W
C0,C1
R/W
D0,D1
R
C4~CA
R
CB~CE
R
C2,C3
R
D2,D3
R
E4'b0
R
7Fb'3~7F b'0
7Fb'7~7F b'4
R
F3b'0
R
E6,E7
R
E8,E9
R/W* E0, E1, E2
W**
E3
-
00~4A (4B rev)
-
R/W W W**
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Allow Read and Write Data Allow Write Data Only
Pages that can be erased are defined by NVM write protection
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R
Allow Read Data Only
-
The Data is protected for Read and Write
Note 1 R/W becomes read only if protection mode selection (lock bit) is set to 1.
Note 2 R/W Readable/writable depend on the "Trim mode enable" bit. If "Trim mode enable" bit value = 1, then trim bits are enable.
It is possible to read some data from macrocells, such as counter current value, connection matrix, and connection matrix virtual inputs. The I2C write will not have any impact on data in case data comes from macrocell output, except Connection Matrix Virtual Inputs. The silicon identification service bits allow identifying silicon family, its revision, and others.
R/W* - Becomes read only after PRL is high.See Section 21 for detailed information on all registers.
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Preliminary
18.7 I2C ADDITIONAL OPTIONS
When Output latching during I2C write to the register configuration data (block address A10, A9, A8 = 000), registers [985] = 1 allows all PINs output value to be latched while register content is changing. It will protect the output change due to configuration process during I2C write in case multiple register bytes are changed. Inputs and internal macrocells retain their status during I2C write.
See Section 21 for detailed information on all registers.
18.7.1 Reading Counter Data via I2C
The current count value in three counters in the device can be read via I2C. The counters that have this additional functionality are 16-bit CNT0, and 8-bit counters CNT2 and CNT4.
18.7.2 I2C Byte Write Bit Masking
The I2C macrocell inside SLG47004 supports masking of individual bits within a byte that is written to the RAM memory space. This function is supported across the entire RAM memory space. To implement this function, the user performs a Byte Write Command (see Section 18.4.1 for details) on the I2C Byte Write Mask Register (address 0F6H) with the desired bit mask pattern. This sets a bit mask pattern for the target memory location that will take effect on the next Byte Write Command to this register byte. Any bit in the mask that is set to "1" in the I2C Byte Write Mask Register will mask the effect of changing that particular bit in the target register, during the next Byte Write Command. The contents of the I2C Byte Write Mask Register are reset (set to 00h) after valid Byte Write Command. If the next command received by the device is not a Byte Write Command, the effect of the bit masking function will be aborted, and the I2C Byte Write Mask Register will be reset with no effect. Figure 234 shows an example of this function.
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User Actions
Byte Write Command, Address = C9, Data = 11110000b [sets mask bits] Byte Write Command, Address = 74h, Data = 10101010b [writes data with mask]
Mask to choose bit from new write command
Memory Address 74h (original contents)
1
1
0
0
1
1
0
0
Mask to choose bit from original register contents
Bit from new write command
Bit from original register contents
Memory Address 74h (new data in write command)
1
0
1
0
1
0
1
0
Memory Address C9 (mask register)
1
1
1
1
0
0
0
0
Memory Address 74h (new contents after write command)
1
1
0
0
1
0
1
0
Figure 234: Example of I2C Byte Write Bit Masking
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19 Non-Volatile Memory
The SLG47004 provides 2,048 bits of Serial Electrically Erasable Configuration Register memory that is used for device configuration, and 2,048 bits Programmable Read-Only Memory (emulated EEPROM). Each of these memory spaces is internally organized as 16 pages of 16 bytes. The device features a Software Write Protection feature with five different programmable levels of protection for the emulated EEPROM array. The protection settings of the device can be made permanent if desired. The emulated EEPROM memory operates with a supply voltage ranging from 2.4 V to 5.5 V for Read and 2.5 V to 5.5 V for Write.
The emulated EEPROM inside the SLG47004 operates as a slave device and utilizes a simple I2C compatible 2-wire digital serial interface to communicate with a host controller commonly referred to as the bus Master. The Master initiates and controls all read and write operations to the Slave devices on the serial bus, and both the Master and the Slave devices can transmit and receive data on the bus.
Key features:
Low-voltage Operation for Read: VCC = 2.4 V to 5.5 V for Write: VCC = 2.5 V to 5.5 V
I2C-Compatible (2-Wire) Serial Interface 100 kHz Standard Mode 400 kHz Fast Mode (FM)
Software Write Protection of the EEPROM Emulation Array Five configuration options Protection settings can be made permanent
Low Current Consumption Read Current 0.5 mA max Page Write Current 3.0 mA max Chip Erase Current 3.0 mA max Standby Current (1.0 A max)
16-byte Page Write Mode Self-timed Write/Erase Cycle (20 ms max) Reliability
Endurance: 1,000 write cycles Data retention: 10 years at 125 �C
19.1 SERIAL NVM WRITE OPERATIONS
Write access to the NVM is possible by setting A3, A2, A1, A0 to "0000", which allows serial write data for a single page only. Upon receipt of the proper Control Byte and Word Address bytes, the SLG47004 will send an ACK. The device will then be ready to receive page data, which is 16 sequential writes of 8-bit data words. The SLG47004 will respond with an ACK after each data word is received. The addressing device, such as a bus Master, must then terminate the write operation with a Stop condition after all page data is written. At that time the device will enter an internally self-timed write cycle, which will be completed within tWR (20 ms). While the data is being written into the NVM Memory Array, all inputs, outputs, internal logic, and I2C access to the Register data will be operational/valid. Please refer to Figure 236 for the SLG47004 Memory Map.
Note: The 16 programmed bytes should be in the same page. Any I2C command that does not meet specific requirements will be ignored and NVM will remain unprogrammed. Note: Special care must be taken when NVM page 14 is rewritten (registers [1919:1792]). This page contains rheostats tolerance data that can be permanently lost during write/erase operation.
SLG47004 will ignore the Serial NVM Write command in case the self-programming procedure for programming rheostat value into the NVM is in progress. The SLG47004 will respond with NACK in this case. Please refer to the Acknowledge Polling section for more details.
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Data "1" cannot be re-programmed as data "0" without erasure. Each byte can only be programmed one time without erasure.
Bus Activity
Start bit
Acknowledge
bit
Control Byte
Word Address (n)
SDA LINE
S
X
X
X
X
A 10
A 9
A 8
A W ACK 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0 ACK
Data (n)
Data (n + 1)
Acknowledge bit
Data (n + 15)
ACK
ACK
ACK P
Control Block Code Address
R/W bit
Stop bit
Figure 235: Page Write Command
A10 will be ignored during communication to SLG47004.
A9 = 1 will enable access to the NVM.
A9 = 1 and A8 = 0 corresponds to the 2K bits chip configuration NVM data.
A9 = 1 and A8 = 1 corresponds to the 2K bits of emulated EEPROM data.
A3, A2, A1, and A0 should be 0000 for the page write operation.
In a single page, if the data written to any byte is 00H, the contents of the matching byte in NVM memory will not be altered.
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Lowest I2C Address = 000h
I2C Block Address
Memory Space
A10 = 0
A9 = 0
A8 = 0 2 kbits Register Data Configuration
A10 = 0
A9 = 0
A8 = 1
Not Used
A10 = 0
A9 = 1
A8 = 0
2 kbits NVM Data Configuration
A10 = 0
A9 = 1
A8 = 1
2 kbits EEPROM
Highest I2C Address = 7FFh
A10 = 1
A9 = X
A8 = X
Not Used
Figure 236: I2C Block Addressing
19.2 SERIAL NVM READ OPERATIONS There are three read operations:
Current Address Read Random Address Read Sequential Read
Please refer to the Section 18 for more details.
19.3 SERIAL NVM ERASE OPERATIONS
The erase scheme allows a portion or the entire emulated EEPROM including the 2K bits NVM chip configuration to be erased by modifying the contents of the Erase Registers (ERSE <2:0>). Changing the state of the ERSE is accomplished with a Byte Write sequence with the requirements outlined in this section.
The ERSE registers are located on byte E3h.
The ERSE format is shown in Table 64, and the ERSE bit functions are included in Table 65.
Table 64: Erase Register Bit Format
Page Erase Register
b7 ERSE2
b6 ERSE1
b5 ERSE0
b4 ERSEB4
b3 ERSEB3
b2 ERSEB2
b1 ERSEB1
b0 ERSEB0
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Table 65: Erase Register Bit Function Description
Bit
Name
Type Description
7
ERSE2
W
000: erase disable
6
ERSE1
Erase Enable
W
110: cause the NVM erase: full NVM (4k bits) erase for ERSCHIP = 1 if DIS_ERSCHIP = 0 or page erase for
5
ERSE0
W
ERSCHIP = 0
4
ERSEB4
W
3
ERSEB3
Page
W
Define the page address, which will be erased:
2
ERSEB2
Selection
W
ERSB4 = 0 corresponds to the Upper 2K NVM used for chip configuration;
1
ERSEB1
for Erase
W
ERSB4 = 1 corresponds to the 2-k emulated EEPROM
0
ERSEB0
W
Upon receipt of the proper Device Address and Erase Registers Address, the SLG47004 will send an ACK. The device will then
be ready to receive Erase Registers data. The SLG47004 will respond with an ACK after Erase Registers data word is received.
The addressing device, such as a bus Master, must then terminate the write operation with a Stop condition. At that time the
device will enter an internally self-timed erase cycle, which the Memory Array, all inputs, outputs, internal logic, and I2C
will be completed within tER access to the Register data
ms. will
While the data is being be operational/valid.
written
into
After the erase has taken place, the contents of ERSE bits will be set to "0" automatically. The internal erase cycle will be triggered at the time the Stop Bit in the I2C command is received.
19.4 ACKNOWLEDGE POLLING
An Acknowledge Polling routine can be implemented to optimize time sensitive applications that would prefer not to wait the fixed maximum write cycle time (tWR) or erase maximum cycle time (tER). This method allows the application to know immediately when the Serial EEPROM emulation write/erase cycle has completed, so a subsequent operation can be started. Once the internally self-timed write/erase cycle has started, an Acknowledge Polling routine can be initiated. This involves repeatedly sending a Start condition followed by a valid Device Address byte (NVM block address) with the R/W bit set at Logic 0. The device will not respond with an ACK while the write cycle is ongoing. Once the internal write/erase cycle has completed, emulated EEPROM will respond with an ACK, allowing a new read, erase, or write operation to be immediately initiated.
The same behavior will happen during the self-programming procedure when the rheostat value is written into the NVM.
The length of the self-timed write cycle (tWR) and self-timed erase cycle (tER) is defined as the amount of time from the Stop condition that begins the internal write operation to the Start condition of the first Device Address byte that includes NVM address (A9 = 1; A8 = X) sent to the SLG47004, that it subsequently responds to with an ACK.
19.5 LOW POWER STANDBY MODE
Emulated EEPROM inside the SLG47004 has a low power standby mode which is enabled when any one of the following occurs:
A valid power-up sequence is performed A Stop condition is received by the devices unless it initiates an internal write/erase cycle At the completion of an internal write/erase cycle An unsuccessful match of the device type identifier or hardware address in the Device Address byte occurs
19.6 EMULATED EEPROM WRITE PROTECTION
The SLG47004 utilizes a software scheme that allows a portion or the entire emulated EEPROM to be inhibited from being written or erased by modifying the contents of the Write Protection Register (WPR). If desired, the WPR can be set so that it may no longer be modified/erased, thereby making the current protection scheme permanent. The status of the WPR can be determined by following a Random Read sequence. Changing the state of the WPR is accomplished with a Byte Write sequence with the requirements outlined in this section.
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The WPR register is located at E2 Address.
The WPR format is shown in Table 66, and the WPR bit functions are included in Table 67.
Table 66: Write/Erase Protect Register Format
b7
b6
b5
b4
b3
b2
b1
b0
WPR
WPRE
WPB1
WPB0
Table 67: Write/Erase Protect Register Bit Function Description
Bit
Name
Type Description
2
WPRE
Write Protect Register Enable
R/W
0: No Software Write Protection enabled (default) 1: Write Protection is set by the state of WPB [1:0] bits
WPB1
R/W 00: Upper quarter of emulated EEPROM is write protected (default)
1:0
WPB0
Write Protect Block Bits
01: Upper half of emulated EEPROM is write protected R/W 10: Upper 3/4 of emulated EEPROM is write protected.
11: Entire emulated EEPROM is write protected.
Write Protect Enable (WPRE): The Write Protect Enable Bit is used to enable or disable the device Software Write/Erase Protect. A Logic 0 in this position will disable Software Write/Erase Protection, and a Logic 1 will enable this function.
Write Protect Block Bits (WPB1:WPB0): The Write Protect Block bits allow four levels of protection of the Memory Array, provided that the WPRE bit is a Logic 1. If the WPRE bit is a Logic 0, the state of the WPB1:0 bits have no impact on device protection.
Protect Lock Bit (PRL): The Protect Lock Bit is used to permanently lock the current state of the WPR, as well as RPR and NPR (see Section 18.5). A Logic 0 indicates that the WPR, RPR, and NPR can be modified, whereas a Logic 1 indicates the WPR, RPR, and NPR has been locked and can no longer be modified. The PRL register bit is located at register [1824] address.
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20 Analog Temperature Sensor
The SLG47004 has an Analog Temperature sensor (TS) with an output voltage linearly-proportional to the Centigrade temperature. The TS cell shares buffer with Vref 0, so it is impossible to use both cells simultaneously, its output can be connected directly to the IO0 or IO1 or the ACPM1_L positive input. Using buffer causes low-output impedance, linear output and makes interfacing to readout or control circuitry especially easy. Vref0 and Vref1 share output buffers with Temperature sensor. Note, that user can use any of output buffers, but Temperature sensor is calibrated for Vref1 output buffer. The TS is rated to operate over a -40 �C to 85 �C temperature range. The error in the whole temperature range does not exceed �1.76 %. For more details refer to Section 3.12.
where: VTS1 (mV) - TS Output Voltage, range 1 VTS2 (mV) - TS Output Voltage, range 2 T (�C) - Temperature
VTS1 = -2.3 x T + 907.4 VTS2 = -2.8 x T + 1095.4
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Figure 237: Analog Temperature Sensor Structure Diagram
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TS OUT (V) -40 -35 -30 -25 -20 -15 -10
-5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
1.25 1.2 Output Range 2
1.15 Output Range 1
1.1 1.05
1 0.95
0.9 0.85
0.8 0.75
0.7 T (�C)
Figure 238: TS Output vs. Temperature, VDD = 3.3 V
Preliminary
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21 Register Definitions
21.1 REGISTER MAP
Table 68: Register Map
Address
Byte
Register Bit
Signal Function
Matrix Output
0
1
2
0
3 4
5
6
7
8
9
10
1
11 12
13
14
15
16
17
18
2
19 20
21
22
23
24
25
26
3
27 28
29
30
31
32
33
34
4
35 36
37
38
39
LUT2_0 & DFF0 LUT2_1 & DFF1 LUT2_2 & DFF2 LUT2_3 & PGen
Register Bit Definition OUT0: IN0 of LUT2_0 or Clock Input of DFF0 OUT1: IN1 of LUT2_0 or Data Input of DFF0 OUT2: IN0 of LUT2_1 or Clock Input of DFF1 OUT3: IN1 of LUT2_1 or Data Input of DFF1 OUT4: IN0 of LUT2_2 or Clock Input of DFF2 OUT5: IN1 of LUT2_2 or Data Input of DFF2 OUT6: IN0 of LUT2_3 or Clock Input of PGen
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Table 68: Register Map (Continued)
Address
Byte 5 6 7 8 9 A
Register
Bit 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
Signal Function LUT2_3 & PGen LUT3_0 & DFF3
LUT3_1 & DFF4
Register Bit Definition OUT6: IN0 of LUT2_3 or Clock Input of PGen OUT7: IN1 of LUT2_3 or nRST of PGen OUT8: IN0 of LUT3_0 or CLK Input of DFF3 OUT9: IN1 of LUT3_0 or Data Input of DFF3 OUT10: IN2 of LUT3_0 or nRST (nSET) of DFF3 OUT11: IN0 of LUT3_1 or CLK Input of DFF4 OUT12: IN1 of LUT3_1 or Data Input of DFF4 OUT13: IN2 of LUT3_1 or nRST (nSET) of DFF4
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Table 68: Register Map (Continued)
Address
Byte A B C D E F
Register
Bit 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
Signal Function LUT3_2 & DFF5
LUT3_3 & DFF6 LUT3_4 & DFF7
Register Bit Definition OUT14: IN0 of LUT3_2 or CLK Input of DFF5 OUT15: IN1 of LUT3_2 or Data Input of DFF5 OUT16: IN2 of LUT3_2 or nRST (nSET) of DFF5 OUT17: IN0 of LUT3_3 or CLK Input of DFF6 OUT18: IN1 of LUT3_3 or Data Input of DFF6 OUT19: IN2 of LUT3_3 or nRST (nSET) of DFF6 OUT20: IN0 of LUT3_4 or CLK Input of DFF7 OUT21: IN1 of LUT3_4 or Data Input of DFF7
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Table 68: Register Map (Continued)
Address
Byte 10 11 12 13 14 15
Register
Bit 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173
Signal Function LUT3_4 & DFF7 LUT3_5 & DFF8
LUT3_6 & DFF9
Register Bit Definition OUT21: IN1 of LUT3_4 or Data Input of DFF7 OUT22: IN2 of LUT3_4 or nRST (nSET) of DFF7 OUT23: IN0 of LUT3_5 or CLK Input of DFF8 OUT24: IN1 of LUT3_5 or Data Input of DFF8 OUT25: IN2 of LUT3_5 or nRST (nSET) of DFF8 OUT26: IN0 of LUT3_6 or CLK Input of DFF9 OUT27: IN1 of LUT3_6 or Data Input of DFF9 OUT28: IN2 of LUT3_6 or nRST (nSET) of DFF9
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Table 68: Register Map (Continued)
Address
Byte 15 16
17
18
19
1A
Register
Bit 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215
Signal Function Multi_function1
Multi_function2 Multi_function3
Register Bit Definition OUT29: IN0 of LUT3_7 or CLK Input of DFF11 Delay1 Input (or Counter1 nRST Input) OUT30: IN1 of LUT3_7 or nRST (nSET) of DFF11 Delay1 Input (or Counter1 nRST Input) OUT31: IN2 of LUT3_7 or Data of DFF11 Delay1 Input (or Counter1 nRST Input) OUT32: IN0 of LUT3_8 or CLK Input of DFF12 Delay2 Input (or Counter2 nRST Input) OUT33: IN1 of LUT3_8 or nRST (nSET) of DFF12 Delay2 Input (or Counter2 nRST Input) OUT34: IN2 of LUT3_8 or Data of DFF12 Delay2 Input (or Counter2 nRST Input) OUT35: IN0 of LUT3_9 or CLK Input of DFF13 Delay3 Input (or Counter3 nRST Input)
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Table 68: Register Map (Continued)
Address
Byte 1B 1C 1D 1E 1F 20
Register
Bit 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263
Signal Function Multi_function3 Multi_function4
Multi_function5
Register Bit Definition OUT36: IN1 of LUT3_9 or nRST (nSET) of DFF13 Delay3 Input (or Counter3 nRST Input) OUT37: IN2 of LUT3_9 or Data of DFF13 Delay3 Input (or Counter3 nRST Input) OUT38: IN0 of LUT3_10 or CLK Input of DFF14 Delay4 Input (or Counter4 nRST Input) OUT39: IN1 of LUT3_10 or nRST (nSET) of DFF14 Delay4 Input (or Counter4 nRST Input) OUT40: IN2 of LUT3_10 or Data of DFF14 Delay4 Input (or Counter4 nRST Input) OUT41: IN0 of LUT3_11 or CLK Input of DFF15 Delay5 Input (or Counter5 nRST Input) OUT42: IN1 of LUT3_11 or nRST (nSET) of DFF15 Delay5 Input (or Counter5 nRST Input) OUT43: IN2 of LUT3_11 or Data of DFF15 Delay5 Input (or Counter5 nRST Input)
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Table 68: Register Map (Continued)
Address
Byte 21 22 23 24 25 26
Register
Bit 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311
Signal Function Multi_function6
LUT3_13 & Pipe Delay (RIPP CNT) LUT4_DFF10
Register Bit Definition OUT44: IN0 of LUT3_12 or CLK Input of DFF16 Delay6 Input (or Counter6 nRST Input) OUT45: IN1 of LUT3_12 or nRST (nSET) of DFF16 Delay6 Input (or Counter6 nRST Input) OUT46: IN2 of LUT3_12 or Data of DFF16 Delay6 Input (or Counter6 nRST Input) OUT47: IN0 of LUT3_13 or Input of Pipe Delay or UP signal of RIPP CNT OUT48: IN1 of LUT3_13 or nRST of Pipe Delay or nSET of RIPP CNT OUT49: IN2 of LUT3_13 or Clock of Pipe Delay_RIPP CNT OUT50: IN0 of LUT4_0 or CLK Input of DFF10 OUT51: IN1 of LUT4_0 or Data of DFF10
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Table 68: Register Map (Continued)
Address
Byte 27 28 29 2A 2B 2C
Register
Bit 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359
Signal Function LUT4_DFF10
Multi_function0
Programmable delay Filter/Edge detector
Register Bit Definition OUT52: IN2 of LUT4_0 or nRST (nSET) of DFF10 OUT53: IN3 of LUT4_0 OUT54: IN0 of LUT4_1 or CLK Input of DFF17 Delay0 Input (or Counter0 nRST Input) OUT55: IN1 of LUT4_1 or nRST of DFF17 Delay0 Input (or Counter0 nRST Input) Delay/Counter0 External CLK source OUT56: IN2 of LUT4_1 or nSET of DFF17 Delay0 Input (or Counter0 nRST Input) Delay/Counter0 External CLK source KEEP Input of FSM0 OUT57: IN3 of LUT4_1 or Data of DFF17 Delay0 Input (or Counter0 nRST Input) UP Input of FSM OUT58: Programmable delay/edge detect input
OUT59: Filter/Edge detect input
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Table 68: Register Map (Continued)
Address
Byte 2D 2E 2F 30 31 32
Register
Bit 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407
Signal Function IO0 IO1 IO2 IO3
Register Bit Definition OUT60: IO0 DOUT OUT61: IO0 DOUT OE OUT62: IO1 DOUT OUT63: IO1 DOUT OE OUT64: IO2 DOUT OUT65: IO2 DOUT OE OUT66: IO3 DOUT OUT67: IO3 DOUT OE
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Table 68: Register Map (Continued)
Address
Byte 33 34 35 36 37 38
Register
Bit 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455
Signal Function IO4 IO5 IO6 Programmable Trim Block0
Register Bit Definition OUT68: IO4 DOUT OUT69: IO4 DOUT OE OUT70: IO5 DOUT OUT71: IO5 DOUT OE OUT72: IO6 DOUT OUT73: IO6 DOUT OE OUT74: set0 of Auto Calibration OUT75: clock0 of Auto Calibration
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte 39 3A 3B 3C 3D 3E
Register
Bit 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503
Signal Function Programmable Trim Block0 Digital Rheostat
Programmable Trim Block1
Digital Rheostat
Register Bit Definition OUT76: reload0 of Auto Calibration OUT77: program0 of Auto Calibration OUT78: Rheostat Counter0 up/down 0: down, 1: up. (register [920] = 0) 0: up, 1: down. (register [920] = 1) OUT79: set1 of Auto Calibration OUT80: clock1 of Auto Calibration OUT81: reload1 of Auto Calibration OUT82: program1 of Auto Calibration OUT83: Rheostat Counter1 up/down 0: down, 1: up. (register [923] = 0) 0: up, 1: down. (register [923] = 1)
Datasheet
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Revision 2.3 235 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
Signal Function
504
505
3F
506 507
FIFO Reset of PT blocks
508
509
510
511
512 513
Chopper ACMP
514
40
515 516
517
518 519
Digital Rheostat
520
521
522
41
523
524 525
Analog Switch0
526
527
528
529
42
530 531
Analog Switch1
532
533
534
535
536 537
ACMP0
538
43
539 540
541
542 543
ACMP1
544
545
546
44
547
548 549
OSC0
550
551
Register Bit Definition OUT84: FIFO nRST of the control logic of reload0/reload1/auto program0/auto program1 OUT85: Chopper ACMP Power Up OUT86: Rheostat Charge pump enable OUT87: ASW0 enable/Half bridge enable OUT88: ASW1 enable/Half bridge data OUT89: ACMP0 Power Up OUT90: ACMP1 Power Up OUT91: OSC0 ENABLE
Datasheet
CFR0011-120-00
Revision 2.3 236 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
Signal Function
552
553
45
554 555
OSC1
556
557
558
559
560 561
OSC2
562
46
563 564
565
566 567
Temperature Sensor
568
569
570
47
571
572 573
HDBUF
574
575
576
577
48
578 579
Op Amp0
580
581
582
583
584 585
Op Amp1
586
49
587 588
589
590 591
Op Amp2
592
593
594
4A
595
596 597
Op amps
598
599
Register Bit Definition OUT92: OSC1 ENABLE OUT93: OSC2 ENABLE OUT94: VREFO TEMPSEN/VREFO Power Up OUT95: HDBUF ENABLE OUT96: OP0(Op Amp ACMP0) Power Up OUT97: OP1(Op Amp ACMP1) Power Up OUT98: OP2 Power Up (In Amp Mode) OUT99: OP VREF ENABLE
Datasheet
CFR0011-120-00
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� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte 4B
Register
Bit 600 601 602 603 604 605 606 607
Signal Function
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
ACMP0
608
609 610
ACMP Low Energy Power Up enable (ACMP power after bg_ok) ACMP input path LPF enable ACMP sampling mode enable
611 ACMP short time wake sleep mode disable
4C
612 ACMP wake sleep function enable
613
ACMP Vref path LPF enable (when ACMP hysteresis > 196 mV)
614
615 ACMP input divider selection
616 617
618
4D
619
620
621
622
623
624
625
4E
626 627
628
629
ACMP1
4E
630
631
632
633
634
4F
635
636
637
ACMP input mux selection
ACMP Low to High Vref selection
ACMP High to Low Vref selection
ACMP Low Energy Power Up enable (ACMP power after bg_ok) ACMP input path LPF enable ACMP sampling mode enable ACMP short time wake sleep mode disable ACMP wake sleep function enable ACMP Vref path LPF enable (when ACMP hysteresis > 196 mV) ACMP input divider selection
Register Bit Definition
1: enable 1: enable 1: enable 0: short time wake sleep enable 1: short time wake sleep disable 1: enable 1: enable 00: 1 01: 0.5 10: 1/3 11: 1/4 00: OP0 output 01: from Pin 10: tie VDD
000000-111111: 32 mV ~2.048 V/step = 32 mV
000000-111111: 32 mV ~2.048 V/step = 32 mV
1: enable 1: enable 1: enable 0: short time wake sleep enable 1: short time wake sleep disable 1: enable 1: enable 00: 1 01: 0.5 10: 1/3 11: 1/4
Datasheet
CFR0011-120-00
Revision 2.3 238 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
638
4F
639
Signal Function ACMP input mux selection
640
641
50
642 643
ACMP Low to High Vref selection
644
645
646
647
51
648 649
ACMP High to Low Vref selection
650
651
Vref
652 Reserved
51
653 Reserved 654 Reserved
655 Reserved
656 Reserved
657 Reserved
658 VREFO0 input source selection
659 VREFO0 output buffer enable
52
660 VREFO0 register Power Up
661 VREFO0 Power Up selection
662 Reserved
663
VREFO1's temp sensor to ACMP1 input path enable
664 VREFO1's temp sensor range selection
665 VREFO1 input source selection
666 VREFO1 output buffer enable
667 VREFO1 register Power Up
53
668 VREFO1 Power Up selection
669 ACMP Vrefs source selection
670 ACMP0 external Vref enable
671 ACMP1 external Vref enable
54
672 Reserved
54
673 Reserved 674 Reserved
Register Bit Definition 00: OP1 output 01: from Pin 10: ACMP0 input mux output 11: VrefO1 Temp sensor output
000000-111111: 32 mV ~2.048 V/step = 32 mV
000000-111111: 32 mV ~2.048 V/step = 32 mV
0: ACMP0 VREF 1: Temp Sensor 1: enable VREFO0 register power on signal 0: Power Up from reg 1: from matrix no use Temp Sensor output to ACMP1 enable 1: enable 0:1V; 1:1.2V 0: ACMP1 Vref 1: TS 1: enable VrefO1 register power on signal 0: Power Up from reg 1: from matrix ACMP Vref gen source selection (0: VBG, 1: VDD) 1:enable 1:enable
Datasheet
CFR0011-120-00
Revision 2.3 239 of 292
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� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte 54
55
Register
Bit 675 676 677 678 679 680 681 682 683 684 685 686 687
Signal Function
Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
OSC1
688 OSC1 turn on by register
689 OSC1 matrix power down or on select
690 OSC1 external clock source enable
691
56
692 OSC1 post divider ratio control
693 694
OSC1 matrix divider ratio control 695
696 OSC1 matrix out enable
697 Reserved 698 Reserved 699 Reserved
700 OSC1 2nd output to matrix enable
57
701
702
OSC1 2nd matrix divider ratio control 703
OSC2
Register Bit Definition
when matrix output enable/pd control signal = 0: 0: auto on by delay cells 1: always on 0: matrix down 1: matrix on 0: internal OSC1 1: external clock from PAD15 00: div 1 01: div 2 10: div 4 11: div8 000: /1 001:/2 010:/4 011: /3 100: /8 101: /12 110: /24 111: /64 0: disable 1: enable
0: disable 1: enable 000: /1 001: /2 010: /4 011: /3 100: /8 101: /12 110: /24 111: /64
Datasheet
CFR0011-120-00
Revision 2.3 240 of 292
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� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
Signal Function
704 OSC2 turn on by register
705 OSC2 matrix power down or on select
706 OSC2 external clock source enable
58
707 OSC2 matrix out enable
708 709 OSC2 post divider ratio control
710 711
OSC2 matrix divider ratio control 712
59
713
714
715
716
717
718
719
OSC0
720
OSC2 startup delay with 100ns Reserved Reserved Reserved Op Amp0 sr boost for OP 8 MHz Op Amp1 sr boost for OP 8 MHz Op Amp2 sr boost for OP 8 MHz
OSC0 turn on by register
721 OSC0 matrix power down or on select
722 OSC0 external clock source enable
5A
723 OSC0 matrix out enable
724 725 OSC0 post divider ratio control
726 727
OSC0 matrix divider ratio control
5B
728
Register Bit Definition
when matrix output enable/pd control signal = 0: 0: auto on by delay cells 1: always on 0: matrix down 1: matrix on 0: internal OSC2 1: external clock from IO2 0: disable 1: enable 00: div 1 01: div 2 10: div 4 11: div8 000: /1 001: /2 010: /4 011: /3 100: /8 101: /12 110: /24 111: /64 0: enable 1: disable
0: enable, 1: disable 0: enable, 1: disable 0: enable, 1: disable
when matrix output enable/pd control signal = 0: 0: auto on by delay cells 1: always on 0: matrix down 1: matrix on 0: internal OSC0 1: external clock from IO0 0: disable 1: enable 00: div 1 01: div 2 10: div 4 11: div8 000: /1 001: /2 010: /4 011: /3 100: /8 101: /12 110: /24 111: /64
Datasheet
CFR0011-120-00
Revision 2.3 241 of 292
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� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
729
730
731
5B
732
733
734 735
Signal Function
Register Bit Definition
enable OSC0 output gating by wake_sleep signal (note: the wake_sleep clock is separated path, so it is not gated)
0: no gating 1: enable
OSC0 2nd output to matrix enable
0: disable 1: enable
OSC0 2nd matrix divider ratio control
000: /1 001: /2 010: /4 011: /3 100: /8 101: /12 110: /24 111: /64
Reserved
Reserved
Analog Switch 736 ASW0 small NMOS enable selection
737 ASW1 small PMOS enable selection
738 ASW0 big PMOS control selection
5C
739 ASW1 big NMOS control selection
740 ASW half bridge mode enable
741 742 ASW half bridge dead time select
743 Reserved
0: small NMOS disable 1: small NMOS enable by matrix87 0: small PMOS disable 1: small PMOS enable by matrix88 0: control by matrix87 1:control by Op Amp0 0: control by matrix88 1:control by Op Amp1 0: analog switch mode 1: half bridge (enable from matrix87; data from matrix88) 00: bypass 01: 20ns 10: 100ns 11: 500ns
Op Amp0/1/2 744
745
746
747
5D
748
749
750 751
Op Amp0 bandwidth selection
Op Amp1 bandwidth selection
Op Amp2 bandwidth selection ACMP/Op Amp0 mode ACMP/Op Amp1 mode
5E
752 Op Amp0 charge pump disable
00: 128 kHz 01: 512 kHz 10: 2 MHz 11: 8 MHz
00: 128 kHz 01: 512 kHz 10: 2 MHz 11: 8 MHz
00: 128 kHz 01: 512 kHz 10: 2 MHz 11: 8 MHz
0: Op amp mode 1: ACMP mode
0: Op amp mode 1: ACMP mode
0: Op amp enable CP
input
common
voltage
higher
than
VDD-1.5V,
1: Op amp disable CP
input
common
voltage
lower
than
VDD-1.5V,
Datasheet
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Revision 2.3 242 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
Signal Function
753 Op Amp1 charge pump disable
754 Op Amp2 charge pump disable
755 Path between Op Amp0/1 and Op Amp2
5E
756 Op Amp2's Vref buffer bypass control
757 Supporting blocks for Op Amp0 on/off
758 Supporting blocks for Op Amp1 on/off
759 Supporting blocks for Op Amp2 on/off
760 Op amp ACMP Vref0 output selection[0]
761 Op amp ACMP Vref0 output selection[1]
762 Op amp ACMP Vref0 output selection[2]
763 Op amp ACMP Vref0 output selection[3]
5F
764 Op amp ACMP Vref0 output selection[4]
765 Op amp ACMP Vref0 output selection[5]
766
Op amp ACMP Vref0 register enable (select by register [782])
767 Vref0 to op amp/ACMP input enable
768 Op amp ACMP Vref1 output selection[0]
769 Op amp ACMP Vref1 output selection[1]
770 Op amp ACMP Vref1 output selection[2]
771 Op amp ACMP Vref1 output selection[3]
60
772 Op amp ACMP Vref1 output selection[4]
773 Op amp ACMP Vref1 output selection[5]
774
Op amp ACMP Vref1 register enable (select by register [783])
775 Vref1 to op amp/ACMP input enable
776 Op amp ACMP Vref0 output selection
777 Op amp ACMP Vref1 output selection
778 Op amp Vref0 LPF enable
61
779 Op amp Vref1 LPF enable
780 Op amp ACMP Vref0 input voltage selection
781 Op amp ACMP Vref1 input voltage selection
782 Op amp ACMP vref0 enable selection
Register Bit Definition
0: Op amp input enable CP;
common
voltage
higher
than
VDD-1.5V,
1: Op amp disable CP
input
common
voltage
lower
than
VDD-1.5V,
0: Op amp enable CP
input
common
voltage
higher
than
VDD-1.5V,
1: Op amp disable CP
input
common
voltage
lower
than
VDD-1.5V,
0: path on (for normal function) 1: path off (for trim function)
0: without buffer 1: with buffer
0: on/off follows op amp 1: always on except input common voltage of op amp lower than VDD-1.5 V 0: on/off follows op amp 1: always on except input common voltage of op amp lower than VDD-1.5V 0: on/off follows op amp 1: always on except input common voltage of op amp lower than VDD-1.5V
000000-111111: 32 mV ~2.048 V/step = 32 mV
0: dynamic on/off 1: Vref enable 0:disable; 1: enable
000000-111111: 32 mV ~2.048 V/step = 32 mV
0: dynamic on/off 1: Vref enable 0:disable; 1: enable 0: Vref to ACMP negative input 1: Vref to ACMP positive input 0: Vref to ACMP negative input 1: Vref to ACMP positive input 0: disable 1: enable 0: disable 1: enable 0: 2.048 V 1: VDD 0: 2.048 V 1: VDD 0: from register [766] 1: from matrix99
Datasheet
CFR0011-120-00
Revision 2.3 243 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
Signal Function
61
783 Op amp ACMP vref1 enable selection
LUT3_2/DFF5 784 785 786
787
62
788 LUT3_2_DFF5 setting
789
790
791
LUT3_3/DFF6 792 793 794
795
63
796 LUT3_3_DFF6 setting
797
798
799
LUT3_4/DFF7 800 801 802
803
64
LUT3_4_DFF7 setting
804
805
806
64
807
LUT3_5/DFF8
LUT3_4_DFF7 setting
Register Bit Definition
0: from register [774] 1: from matrix99
<2:0>: LUT3_2 <2:0>
<3>:LUT3_2 <3>/DFF5 Active level selection for RST/SET 0: Active low level reset/set, 1: Active high level reset/set <4>:LUT3_2<4>/DFF5 0: RSTB from Matrix Output, 1: SETB from Matrix Output <5>:LUT3_2 <5>/DFF5 Initial Polarity Select 0: Low, 1: High <6>:LUT3_2 <6>/DFF5 Output Select 0: Q output, 1: QB output <7>:LUT3_2 <7>/DFF5 or Latch Select 0: DFF function, 1: Latch function
<2:0>: LUT3_3 <2:0>
<3>:LUT3_3 <3>/DFF6 Active level selection for RST/SET 0: Active low level reset/set, 1: Active high level reset/set <4>:LUT3_3<4>/DFF6
0: RSTB from Matrix Output, 1: SETB from Matrix Output <5>:LUT3_3 <5>/DFF6 Initial Polarity Select
0: Low, 1: High <6>:LUT3_3 <6>/DFF6 Output Select
0: Q output, 1: QB output <7>:LUT3_3 <7>/DFF6 or Latch Select
0: DFF function, 1: Latch function
<2:0>: LUT3_4 <2:0>
<3>:LUT3_4 <3>/DFF7 Active level selection for RST/SET 0: Active low level reset/set, 1: Active high level reset/set <4>:LUT3_4<4>/DFF7 0: RSTB from Matrix Output, 1: SETB from Matrix Output <5>:LUT3_4 <5>/DFF7 Initial Polarity Select 0: Low, 1: High <6>:LUT3_4 <6>/DFF7 Output Select 0: Q output, 1: QB output <7>:LUT3_4 <7>/DFF7 or Latch Select 0: DFF function, 1: Latch function
Datasheet
CFR0011-120-00
Revision 2.3 244 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit 808 809 810
Signal Function
811
65
812
813
814
815
LUT3_6/DFF9 816 817 818
819
LUT3_5_DFF8 setting
66
820 LUT3_6_DFF9 setting
821
822
823
824 LUT3_2 or DFF5 Select
825 LUT3_3 or DFF6 Select
826 LUT3_4 or DFF7 Select
67
827 LUT3_5 or DFF8 Select
828 LUT3_6 or DFF9 Select
829
830 831 LUT4_0/DFF10
LUT4_0 or DFF10 Select
Reserved Reserved
Register Bit Definition
<2:0>: LUT3_5 <2:0>
<3>:LUT3_5 <3>/DFF8 Active level selection for RST/SET 0: Active low level reset/set, 1: Active high level reset/set <4>:LUT3_5<4>/DFF8 0: RSTB from Matrix Output, 1: SETB from Matrix Output <5>:LUT3_5 <5>/DFF8 Initial Polarity Select 0: Low, 1: High <6>:LUT3_5 <6>/DFF8 Output Select 0: Q output, 1: QB output <7>:LUT3_5 <7>/DFF8 or Latch Select 0: DFF function, 1: Latch function
<2:0>: LUT3_6 <2:0>
<3>:LUT3_6 <3>/DFF9 Active level selection for RST/SET 0: Active low level reset/set, 1: Active high level reset/set <4>:LUT3_6<4>/DFF9
0: RSTB from Matrix Output, 1: SETB from Matrix Output <5>:LUT3_6 <5>/DFF9 Initial Polarity Select
0: Low, 1: High <6>:LUT3_6 <6>/DFF9 Output Select
0: Q output, 1: QB output <7>:LUT3_6 <7>/DFF9 or Latch Select
0: DFF function, 1: Latch function 0: LUT3_2 1: DFF5 0: LUT3_3 1: DFF6 0: LUT3_4 1: DFF7 0: LUT3_5 1: DFF8 0: LUT3_5 1: DFF8 0: LUT4_0 1: DFF10
Datasheet
CFR0011-120-00
Revision 2.3 245 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte 68
Register
Bit 832 833 834 835 836 837 838 839 840 841
Signal Function
842 LUT4_0_DFF10 setting
843
69
844
845
846
847
Register Bit Definition
<9:0>: LUT4_0 <9:0>
<10>:LUT4_0 <10>/DFF10 stage selection 0: Q of first DFF; 1 Q of second DFF <11>:LUT4_0 <11>/DFF10 Active level selection for RST/SET 0: Active low level reset/set, 1: Active high level reset/set <12>:LUT4_0 <12>/DFF10 0: RSTB from Matrix Output, 1: SETB from Matrix Output <13>:LUT4_0 <13> /DFF10 Initial Polarity Select 0: Low, 1: High <14>:LUT4_0 <14>/DFF10 Output Select 0: Q output, 1: QB output <15>:LUT4_0 <15>/DFF10 or Latch Select 0: DFF function, 1: Latch function
LUT3_13/Pipe Delay (RIPP CNT)
848
at LUT/pipe delay mode
849
bit<7:4>: LUT3_13 <7:4> / REG_S1<3:0> pipe delay out1
850 851
sel bit<3:0>: LUT3_13 <3:0> / REG_S0<3:0> pipe delay out0 sel
6A
852 LUT value or pipe delay out sel or nSET/END value at RIPP CNT mode
853
bit<2:0> is the nSET value.
854
bit<5:3> is the END value
bit<6> is the range control:
855
0: full cycle, 1: range cycle
bit<7> No used
856 Active level selection for RST/SET
0: Active low level reset/set 1: Active high level reset/set
857
Out of LUT3_13 or Out0 of Pipe Delay/RIPP CNT 0: LUT3_13
Select
1: OUT0 of Pipe Delay or RIPP CNT
858 PIPE_RIPP_CNT_S 6B
859 Pipe Delay OUT1 Polarity Select
0: Pipe delay mode selection 1: Ripple Counter mode selection 0: Non-inverted 1: Inverted
860 Reserved
861 Reserved
862 Reserved
863 Reserved
Programmable Delay
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte
Register Bit 864
865
Signal Function Delay Value Select for Programmable Delay & Edge Detector
6C
866
Select the Edge Mode of Programmable Delay &
867 Edge Detector
Register Bit Definition
00: 125ns 01: 250ns 10: 375ns 11: 500ns 00: Rising Edge Detector 01: Falling Edge Detector 10: Both Edge Detector 11: Both Edge Delay
Filter/Edge Detector 868 Filter or Edge Detector selection
869 Output Polarity Select
6C
870
871 Select the edge mode
0: filter 1: edge detect 0: output non-invert 1: output invert 00: Rising Edge Detect 01: Falling Edge Detect 10: Both Edge Detect 11: Both Edge DLY
Chopper ACMP
872
00: from In Amp out
Chopper ACMP positive input selection for calibra- 01: from Op Amp0 out
873 tion channel0
10: from Op Amp1 out
11: IO1
874
00: from In Amp out
Chopper ACMP positive input selection for calibra- 01: from Op Amp0 out
6D
875 tion channel1
10: from Op Amp1 out
11: IO1
876 Reserved
877 Reserved
878 Reserved
879 Reserved
880 Reserved
881 Reserved
882 Output Polarity Select
0: output non-invert 1: output invert
6E
883
884
885 Reserved
886
887
888
889 Reserved
6F 890 Reserved
891 Reserved
Calibration
Preliminary
Datasheet
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� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
892
893
6F
894
895
896 897 898
899 70
900
901 902 903 904 905 906
907 71
908 909 910 911
Signal Function
Register Bit Definition
auto calibration channel selection by register
0: calibration channel0 1: calibration channel1
auto calibration channel selection source selection
0:calibration channel auto selection 1: from register [892]
RH_CNT1 clock source selection
0: From Chopper ACMP (Chopper ACMP changes one time per rheostat clock) 1: from matrix directly
RH_CNT0 clock source selection
0: From Chopper ACMP (Chopper ACMP changes one time per rheostat clock) 1: from matrix directly
Calibration0 clock divider
0000: OSC1 0001:OSC1/8 0010:OSC1/64 0011: OSC1/512 0100: OSC0 0101:OSC0/8 0110: OSC0/64 0111: OSC0/512 1000: OSC0/4096 1001: OSC0/32768 1010: OSC0/262144 1011/1100/1101/1110: GND 1111: EXTCLK
Up/down selection
0: chopper ACMP 1: matrix83
auto_calibration disable
0: auto calibration enable 1: disable
Reserved
Reserved
Calibration1 clock divider
0000: OSC1 0001:OSC1/8 0010:OSC1/64 0011: OSC1/512 0100: OSC0 0101: OSC0/8 0110: OSC0/64 0111: OSC0/512 1000: OSC0/4096 1001: OSC0/32768 1010: OSC0/262144 1011/1100/1101/1110: GND 1111: EXTCLK
Up/down selection
0: chopper ACMP 1: matrix83
auto_calibration disable
0: auto calibration enable 1: disable
Reserved
Reserved
Digital Rheostats
Datasheet
CFR0011-120-00
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� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
Signal Function
912 POTCP0 turn on by register
913 POTCP1 turn on by register
914 POTCP0/1 clock source selection
72
915 POTCP0/1 clock source select from register
Register Bit Definition
0: control by matrix86 1: on 0: control by matrix86 1: on 0: from LPBG chopper OSC 1: from OSC1 0: by register [914] 1: calibration auto on
916 Reserved
917 Reserved 918 Reserved 919 Reserved
920 Polarity selection of RH_CNT0 UP signal
921 Reserved 922 Reserved
73
923 Polarity selection of RH_CNT1 UP signal
924 Reserved 925 Reserved 926 Reserved 927 Reserved
0: default (up = 0 down mode, up = 1 up mode) 1: (up = 0 up mode, up = 1 down mode) 0: default (up = 0 down mode, up = 1 up mode) 1: (up = 0 up mode, up = 1 down mode)
HD Buffer
928
929
930
931
74
932
933
934
935
936
937
938
939
75
940
941
942
943
Chop ACMP Vref selection for calibration channel 0
000000-111111: 1/64 ~ 64/64 (divider input select by register [946])
Chop ACMP calibration channel0 external Vref se- 0: external Vref (pin18)
lection
1: internal Vref
Reserved
Chop ACMP Vref selection for calibration channel 1
000000-111111: 1/64 ~ 64/64 (divider input select by register [946])
Chop ACMP calibration channel1 external Vref se- 0: external Vref (pin18)
lection
1: internal Vref
Reserved
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
944
Signal Function HD buffer register enable (select by register [945])
945 HD buffer enable selection
946 Chop ACMP Vref divider input selection 76
947 Reserved 948 Reserved 949 Reserved 950 Reserved 951 Reserved
CP OSC/Regulator
952 CPOSC single or multiple mode select
953 Reserved
954
77
955 CPOSC0 frequency select
956 Reserved
957 958
Reserved
959 Reserved
960 Reserved
961 Reserved
962
963 CPOSC1 frequency select 78
964 Reserved
965 966
Reserved
967 Reserved
968 Reserved
969 Reserved
970
79
971 CPOSC2 frequency select
972 Reserved
973 974
Reserved
975 Reserved
Register Bit Definition
0: disable 1: enable
0: from register [944] 1: from matrix95
0: from HD buffer output
1: in
from Vref
op amp block)
Vref
voltage
(2.048/VDD
selection
register
0: multiple OSC mode 1: single OSC mode 00: 250 kHz 01: 1 MHz 10: 4 MHz 11: 8 MHz
00: 250 kHz 01: 1 MHz 10: 4 MHz 11: 8 MHz
00: 250 kHz 01: 1 MHz 10: 4 MHz 11: 8 MHz
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
976
977
Signal Function Buffer Vref select
978 Reserved
7A
979 Reserved
980 Reserved
981 Reserved
982 Reserved
983 Reserved
984 I2C soft reset
985 IO latch enable during I2C write
986 Reserved
7B
987 Reserved
988 Reserved
989 Reserved
990 Reserved
991 Reserved
992 Matrix Input 32
993 Matrix Input 33
994 Matrix Input 34
7C
995 Matrix Input 35 996 Matrix Input 36
997 Matrix Input 37
998 Matrix Input 38
999 Matrix Input 39
1000
1001
1002
7D
1003 1004
Reserved
1005
1006
1007
1008
1009
1010
7E
1011 1012
Reserved
1013
1014
1015
Register Bit Definition 00: none 01: internal Vref 10: Rheostat Vref 11: external Vref
0: Keep existing condition 1: Reset execution, reload NVM to registers 0: disable 1: enable
I2C_virtual_0 Input I2C_virtual_1 Input I2C_virtual_2 Input I2C_virtual_3 Input I2C_virtual_4 Input I2C_virtual_5 Input I2C_virtual_6 Input I2C_virtual_7 Input
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte
Register
Bit 1016 1017 1018 1019
Signal Function I2C slave address
1020 slave address selection bit0 7F
1021 slave address selection bit1
1022 slave address selection bit2
1023 slave address selection bit3
1024
1025
1026
80
1027 1028
Reserved
1029
1030
1031
1032
1033
1034 1035
Reserved
81 1036
1037
1038 Reserved
1039 Reserved
1040
1041
1042 1043
Reserved
82 1044
1045
1046 Reserved
1047 Reserved
1048
1049
1050 1051
Reserved
83 1052
1053
1054 Reserved
1055 Reserved
Register Bit Definition
0: from register [1016] 1: from PAD15 0: from register [1017] 1: from PAD16 0: from register [1018] 1: from PAD17 0: from register [1019] 1: from PAD18
Preliminary
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte 84 85 86 87 88
Register
Bit 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095
Signal Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register Bit Definition
Preliminary
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte 89 8A 8B 8C 8D 8E
Register
Bit 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140
Signal Function Reserved
Reserved
Reserved
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved
Reserved Reserved
Register Bit Definition
Preliminary
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte 8E
8F
Register
Bit 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150
Signal Function Reserved Reserved
1151 Reserved
SCL/SDA 1152
1153 90
1154
1155
input mode configuration
Reserved I2C mode selection
IO0 1156
1157 input mode configuration
90
1158
1159 output mode configuration
1160
91
1161 Pull-up/down resistance selection
1162 Pull-up/down selection
IO1 1163
1164 input mode configuration
91 1165 1166 output mode configuration
1167
1168 Pull-up/down resistance selection 92
1169 Pull-up/down selection
IO2
Register Bit Definition
00: digital without Schmitt trigger 01: digital with Schmitt trigger 10: low voltage digital in 11: analog IO
0: 1:
II22CC
fast mode + standard/fast
mode
00: digital without Schmitt Trigger 01: digital with Schmitt Trigger 10: low voltage digital in 11: analog IO 00: Push-Pull 1x 01: Push-Pull 2x 10: 1x Open-Drain 11: 2x Open-Drain 00: floating 01: 10k 10: 100k 11: 1M 0: Pull-down 1: Pull-up
00: digital without Schmitt Trigger 01: digital with Schmitt Trigger 10: low voltage digital in 11: analog IO 00: Push-Pull 1x 01: Push-Pull 2x 10: 1x Open-Drain 11: 2x Open-Drain 00: floating 01: 10K 10: 100K 11: 1M 0: Pull-down 1: Pull-up
Preliminary
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte
Register Bit
1170
1171
Signal Function input mode configuration
1172
92
output mode configuration 1173
1174 1175
Pull-up/down resistance selection
93 1176 Pull-up/down selection
IO3 1177
1178 input mode configuration
1179
93
1180 output mode configuration
1181
1182 Pull-up/down resistance selection
1183 Pull-up/down selection
IO4 1184
1185 input mode configuration
1186
94
1187 output mode configuration
1188
1189 Pull-up/down resistance selection
1190 Pull-up/down selection IO5
Register Bit Definition
00: digital without Schmitt Trigger 01: digital with Schmitt Trigger 10: low voltage digital in 11: analog IO 00: Push-Pull 1x 01: Push-Pull 2x 10: 1x Open-Drain 11: 2x Open-Drain 00: floating 01: 10K 10: 100K 11: 1M 0: Pull-down 1: Pull-up
00: digital without Schmitt Trigger 01: digital with Schmitt Trigger 10: low voltage digital in 11: analog IO 00: Push-Pull 1x 01: Push-Pull 2x 10: 1x Open-Drain 11: 2x Open-Drain 00: floating 01: 10K 10: 100K 11: 1M 0: Pull-down 1: Pull-up
00: digital without Schmitt Trigger 01: digital with Schmitt Trigger 10: low voltage digital in 11: analog IO 00: Push-Pull 1x 01: Push-Pull 2x 10: 1x Open-Drain 11: 2x Open-Drain 00: floating 01: 10K 10: 100K 11: 1M 0: Pull-down 1: Pull-up
Preliminary
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte
Register Bit
94 1191
Signal Function
1192 input mode configuration
1193
1194 output mode configuration 95
1195
1196 Pull-up/down resistance selection
1197 Pull-up/down selection
IO6 1198
95
1199 input mode configuration
1200 1201
output mode configuration
96
1202
1203 Pull-up/down resistance selection
1204 Pull-up/down selection
I0 1205
96
1206 input mode configuration
1207 IO fast Pull-up/down enable
1208 Reserved
1209 Reserved
1210 Reserved
97
1211 Reserved 1212 Reserved
1213 Reserved
1214 Reserved
1215 Reserved
Register Bit Definition
00: digital without Schmitt Trigger 01: digital with Schmitt Trigger 10: low voltage digital in 11: analog IO 00: Push-Pull 1x 01: Push-Pull 2x 10: 1x Open-Drain 11: 2x Open-Drain 00: floating 01: 10K 10: 100K 11: 1M 0: Pull-down 1: Pull-up
00: digital without Schmitt Trigger 01: digital with Schmitt Trigger 10: low voltage digital in 11: analog IO 00: Push-Pull 1x 01: Push-Pull 2x 10: 1x Open-Drain 11: 2x Open-Drain 00: floating 01: 10K 10: 100K 11: 1M 0: Pull-down 1: Pull-up
00: digital without Schmitt Trigger 01: digital with Schmitt Trigger 10: low voltage digital in 11: analog IO 0: disable 1: enable
Preliminary
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register
Bit 1216 1217 1218 1219
98
1220
Signal Function Multi0 register configure
1221 1222 1223
1224
DLY/CNT0 Mode Selection
1225 1226
DLY/CNT0 edge Mode Selection
1227 1228 1229
99
1230
DLY/CNT0 Clock Source Select
1231 FSM0 SET/RST Selection
1232 wake sleep mode selection
1233 Wake sleep power down state selection
1234 Keep signal sync selection
9A
1235 UP signal sync selection
1236 CNT0 CNT mode SYNC selection
1237 CNT0 output pol selection
1238 CNT0 DLY EDET FUNCTION Selection 1239 Reserved
Register Bit Definition
mulit_function selection
dly2lut selection
output selection of LUT4_1/DFF17: 0: LUT4_1 1: DFF17
external clock selection
00: DLY 01: one shoot 10: frequency detect 11: CNT register [1238] = 0 00: both edge 01: falling edge 10: rising edge 11: High Level Reset (only in CNT mode) Clock source sel[3:0] 0000: 25M(OSC2) 0001: 25M/4 0010: 2M(OSC1) 0011: 2M/8 0100: 2M/64 0101: 2M/512 0110: 2K(OSC0) 0111: 2K/8 1000: 2K/64 1001: 2K/512 1010: 2K/4096 1011: 2K/32768 1100: 2K/262144 1101: CNT6_END 1110: External 1111: Not used 0: Reset to 0 1: Set to data 0: Default Mode, 1: Wake Sleep Mode (registers [1224:1223] = 11) 0: low 1: high 0: bypass 1: after two DFF 0: bypass 1: after two DFF 0: bypass 1: after two DFF 0: Default Output 1: Inverted Output 0: normal 1: DLY function edge detection (registers [1224:1223] = 00)
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register
Bit 1240 1241 1242 1243
Signal Function Multi1 register configure
1244 9B
1245 CNT1 DLY EDET FUNCTION Selection
1246 CNT1 CNT mode SYNC selection
1247
1248 1249 1250
CNT1 output pol selection
1251
CNT1 function and edge mode selection
9C
1252 1253
1254
1255
DLY/CNT1 Clock Source Select
Register Bit Definition
mulit_function selection
dly2lut selection output selection of LUT3_7/DFF11: 0: LUT3_7 1: DFF11 0: normal 1: DLY function edge detection (registers [1251:1248] = 0000/0001/0010) 0: bypass 1: after two DFF 0: Default Output 1: Inverted Output 0000: both edge Delay 0001: falling edge delay 0010: rising edge delay 0011: both edge One Shot 0100: falling edge One Shot 0101: rising edge One Shot 0110: both edge freq detect 0111: falling edge freq detect 1000: rising edge freq detect 1001: both edge detect 1010: falling edge detect 1011: rising edge detect 1100: both edge reset CNT 1101: falling edge reset CNT 1110: rising edge reset CNT 1111: high level reset CNT Clock source sel[3:0] 0000: 25M(OSC2) 0001: 25M/4 0010: 2M(OSC1) 0011: 2M/8 0100: 2M/64 0101: 2M/512 0110: 2K(OSC0) 0111: 2K/8 1000: 2K/64 1001: 2K/512 1010: 2K/4096 1011: 2K/32768 1100: 2K/262144 1101: CNT0_END 1110: External 1111: Not used
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register
Bit 1256 1257 1258 1259
Signal Function Multi2 register configure
1260 9D
1261 CNT2 DLY EDET FUNCTION Selection
1262 CNT2 CNT mode SYNC selection
1263
1264 1265 1266
CNT2 output pol selection
9E
CNT2 function and edge mode selection
1267
1268 1269 1270
9E
DLY/CNT2 Clock Source Select
1271
Register Bit Definition
mulit_function selection
dly2lut selection output selection of LUT3_8/DFF12: 0: LUT3_8 1: DFF12 0: normal 1: DLY function edge detection (registers [1267:1264] = 0000/0001/0010) 0: bypass 1: after two DFF 0: Default Output 1: Inverted Output 0000: both edge Delay 0001: falling edge delay 0010: rising edge delay 0011: both edge One Shot 0100: falling edge One Shot 0101: rising edge One Shot 0110: both edge freq detect 0111: falling edge freq detect 1000: rising edge freq detect 1001: both edge detect 1010: falling edge detect 1011: rising edge detect 1100: both edge reset CNT 1101: falling edge reset CNT 1110: rising edge reset CNT 111: high level reset CNT Clock source sel[3:0] 0000: 25M(OSC2) 0001: 25M/4 0010: 2M(OSC1) 0011: 2M/8 0100: 2M/64 0101: 2M/512 0110: 2K(OSC0) 0111: 2K/8 1000: 2K/64 1001: 2K/512 1010: 2K/4096 1011: 2K/32768 1100: 2K/262144 1101: CNT1_END 1110: External 1111: Not used
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register
Bit 1272 1273 1274 1275
Signal Function Multi3 register configure
1276 9F
1277 CNT3 DLY EDET FUNCTION Selection
1278 CNT3 CNT mode SYNC selection
1279
1280 1281 1282
CNT3 output pol selection
1283
CNT3 function and edge mode selection
A0
1284 1285
1286
1287
DLY/CNT3 Clock Source Select
Register Bit Definition
mulit_function selection
dly2lut selection output selection of LUT3_9/DFF13: 0: LUT3_9 1: DFF13 0: normal 1: DLY function edge detection(registers [1283:1280] = 0000/0001/0010) 0: bypass; 1: after two DFF 0: Default Output, 1: Inverted Output 0000: both edge Delay 0001: falling edge delay 0010: rising edge delay 0011: both edge One Shot 0100: falling edge One Shot 0101: rising edge One Shot 0110: both edge freq detect 0111: falling edge freq detect 1000: rising edge freq detect 1001: both edge detect 1010: falling edge detect 1011: rising edge detect 1100: both edge reset CNT 1101: falling edge reset CNT 1110: rising edge reset CNT 1111: high level reset CNT Clock source sel[3:0] 0000: 25M(OSC2) 0001: 25M/4 0010: 2M(OSC1) 0011: 2M/8 0100: 2M/64 0101: 2M/512 0110: 2K(OSC0) 0111: 2K/8 1000: 2K/64 1001: 2K/512 1010: 2K/4096 1011: 2K/32768 1100: 2K/262144 1101: CNT2_END 1110: External 1111: Not used
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register
Bit 1288 1289 1290 1291
Signal Function Multi4 register configure
1292 A1
1293 CNT4 DLY EDET FUNCTION Selection
1294 CNT4 CNT mode SYNC selection
1295
1296 1297 1298
CNT4 output pol selection
1299
CNT4 function and edge mode selection
A2
1300 1301
1302
1303
DLY/CNT4 Clock Source Select
Register Bit Definition
mulit_function selection
dly2lut selection output selection of LUT3_10/DFF14: 0: LUT3_10 1: DFF14 0: normal 1: DLY function edge detection (registers [1299:1296] = 0000/0001/0010) 0: bypass 1: after two DFF 0: Default Output 1: Inverted Output 0000: both edge Delay 0001: falling edge delay 0010: rising edge delay 0011: both edge One Shot 0100: falling edge One Shot 0101: rising edge One Shot 0110: both edge freq detect; 0111: falling edge freq detect 1000: rising edge freq detect 1001: both edge detect 1010: falling edge detect 1011: rising edge detect 1100: both edge reset CNT 1101: falling edge reset CNT 1110: rising edge reset CNT 1111: high level reset CNT Clock source sel[3:0] 0000: 25M(OSC2) 0001: 25M/4 0010: 2M(OSC1) 0011: 2M/8 0100: 2M/64 0101: 2M/512 0110: 2K(OSC0) 0111: 2K/8 1000: 2K/64 1001: 2K/512 1010: 2K/4096 1011: 2K/32768 1100: 2K/262144 1101: CNT3_END 1110: External 1111: Not used
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register
Bit 1304 1305 1306 1307
Signal Function Multi5 register configure
1308 A3
1309 CNT5 DLY EDET FUNCTION Selection
1310 CNT5 CNT mode SYNC selection
1311
1312 1313 1314
CNT5 output pol selection
1315
CNT5 function and edge mode selection
A4
1316 1317
1318
1319
DLY/CNT5 Clock Source Select
Register Bit Definition
mulit_function selection
dly2lut selection output selection of LUT3_11/DFF15: 0: LUT3_11 1: DFF15 0: normal 1: DLY function edge detection (registers [1315:1312] = 0000/0001/0010) 0: bypass 1: after two DFF 0: Default Output 1: Inverted Output 0000: both edge Delay 0001: falling edge delay 0010: rising edge delay 0011: both edge One Shot 0100: falling edge One Shot 0101: rising edge One Shot 0110: both edge freq detect 0111: falling edge freq detect 1000: rising edge freq detect 1001: both edge detect 1010: falling edge detect 1011: rising edge detect 1100: both edge reset CNT 1101: falling edge reset CNT 1110: rising edge reset CNT 1111: high level reset CNT Clock source sel[3:0] 0000: 25M(OSC2) 0001: 25M/4 0010: 2M(OSC1) 0011: 2M/8 0100: 2M/64 0101: 2M/512 0110: 2K(OSC0) 0111: 2K/8 1000: 2K/64 1001: 2K/512 1010: 2K/4096 1011: 2K/32768 1100: 2K/262144 1101: CNT4_END 1110: External 1111: Not used
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register
Bit 1320 1321 1322 1323
Signal Function Multi6 register configure
1324 A5
1325 CNT6 DLY EDET FUNCTION Selection
1326 CNT6 CNT mode SYNC selection
1327
1328 1329 1330
CNT6 output pol selection
1331
CNT6 function and edge mode selection
A6 1332 1333 1334
1335
DLY/CNT6 Clock Source Select
Register Bit Definition
mulit_function selection
dly2lut selection output selection of LUT3_12/DFF16: 0: LUT3_12 1: DFF16 0: normal 1: DLY function edge detection (registers [1331:1328] = 0000/0001/0010) 0: bypass 1: after two DFF 0: Default Output 1: Inverted Output 0000: both edge Delay 0001: falling edge delay 0010: rising edge delay 0011: both edge One Shot 0100: falling edge One Shot 0101: rising edge One Shot 0110: both edge freq detect 0111: falling edge freq detect 1000: rising edge freq detect 1001: both edge detect 1010: falling edge detect 1011: rising edge detect 1100: both edge reset CNT 1101: falling edge reset CNT 1110: rising edge reset CNT 1111: high level reset CNT Clock source sel[3:0] 0000: 25M(OSC2) 0001: 25M/4 0010: 2M(OSC1) 0011: 2M/8 0100: 2M/64 0101: 2M/512 0110: 2K(OSC0) 0111: 2K/8 1000: 2K/64 1001: 2K/512 1010: 2K/4096 1011: 2K/32768 1100: 2K/262144 1101: CNT5_END 1110: External 1111: Not used
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
1336
1337
Signal Function CNT0 initial value selection
1338 1339 CNT1 initial value selection A7 1340 1341 CNT6 initial value selection
1342 1343 1344
1345
Reserved Reserved
CNT2 initial value selection
1346
1347 CNT3 initial value selection
A8
1348
1349 CNT4 initial value selection
1350 1351
CNT5 initial value selection
1352
1353
1354
A9
1355 1356
1357
1358
1359
1360 1361 Multi0_LUT4_DFF setting
1362
1363
1364 AA
1365
1366
1367
Register Bit Definition 00: bypass the initial 01: initial 0 10: initial 1 11: initial 1 00:bypass the initial 01: initial 0 10: initial 1 11: initial 1 00: bypass the initial 01: initial 0 10: initial 1 11: initial 1
00: bypass the initial 01: initial 0 10: initial 1 11: initial 1 00: bypass the initial 01: initial 0 10: initial 1 11: initial 1 00: bypass the initial 01: initial 0 10: initial 1 11: initial 1 00:bypass the initial 01: initial 0 10: initial 1 11: initial 1
<12:0>:LUT4_1 <12:0>
<13>:LUT4_1 <13>/DFF17 Initial Polarity Select 0: Low, 1: High <14>:LUT4_1 <14>/DFF17 Output Select 0: Q output, 1: QB output <15>:LUT4_1 <15>/DFF17 or Latch Select 0: DFF function, 1: Latch function
Datasheet
CFR0011-120-00
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
Signal Function
1368
1369
1370
AB
1371 1372
1373
1374
1375 1376
REG_CNT0_D<15:0>
1377
1378
AC
1379 1380
1381
1382
1383
1384
1385
1386
1387
1388
AD
Multi1_LUT3_DFF setting
1389
1390
1391
Multi1_CNT1
1392
1393
1394
AE
1395 1396
1397
1398
1399
1400
1401
1402
1403
1404 AF
1405
REG_CNT1_D<7:0> Multi2_LUT3_DFF setting
1406
1407
Register Bit Definition
Data[15:0]
<3:0>:LUT3_7 <3:0> <4>:LUT3_7 <4>/DFF11 Initial Polarity Select 0: Low, 1: High <5>:LUT3_7 <5>/DFF11 0: RSTB from Matrix Output, 1: SETB from Matrix Output <6>:LUT3_7 <6>/DFF11 Output Select 0: Q output, 1: QB output <7>:LUT3_7 <7>/DFF11 or Latch Select 0: DFF function, 1: Latch function
Data[7:0]
<3:0>:LUT3_8 <3:0> <4>:LUT3_8 <4>/DFF12 Initial Polarity Select 0: Low, 1: High <5>:LUT3_8 <5>/DFF12 0: RSTB from Matrix Output, 1: SETB from Matrix Output <6>:LUT3_8 <6>/DFF12 Output Select 0: Q output, 1: QB output <7>:LUT3_8 <7>/DFF12 or Latch Select 0: DFF function, 1: Latch function
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte B0
Register
Bit 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419
Signal Function REG_CNT2_D<7:0>
1420
B1
Multi3_LUT3_DFF setting
1421
1422
1423
1424
1425
1426
B2
1427 1428
REG_CNT3_D<7:0>
1429
1430
1431
1432
1433
1434
1435
1436
B3
Multi4_LUT3_DFF setting
1437
1438
1439
1440
1441
1442
B4
1443 1444
REG_CNT4_D<7:0>
1445
1446
1447
Register Bit Definition
Data[7:0]
<3:0>:LUT3_9 <3:0> <4>:LUT3_9 <4>/DFF13 Initial Polarity Select 0: Low, 1: High <5>:LUT3_9 <5>/DFF13 0: RSTB from Matrix Output, 1: SETB from Matrix Output <6>:LUT3_9 <6>/DFF13 Output Select 0: Q output, 1: QB output <7>:LUT3_9 <7>/DFF13 or Latch Select 0: DFF function, 1: Latch function
Data[7:0]
<3:0>:LUT3_10 <3:0> <4>:LUT3_10 <4>/DFF14 Initial Polarity Select 0: Low, 1: High <5>:LUT3_10 <5>/DFF14 0: RSTB from Matrix Output, 1: SETB from Matrix Output <6>:LUT3_10 <6>/DFF14 Output Select 0: Q output, 1: QB output <7>:LUT3_10 <7>/DFF14 or Latch Select 0: DFF function, 1: Latch function
Data[7:0]
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register
Bit 1448 1449 1450 1451
Signal Function
1452
B5
Multi5_LUT3_DFF setting
1453
1454
1455
1456
1457
1458
B6
1459 1460
REG_CNT5_D<7:0>
1461
1462
1463
1464
1465
1466
1467
1468
B7
Multi6_LUT3_DFF setting
1469
1470
1471
1472
1473
1474
B8
1475 1476
REG_CNT6_D<7:0>
1477
1478
1479
Register Bit Definition
<3:0>:LUT3_11<3:0> <4>:LUT3_11<4>/DFF15 Initial Polarity Select 0: Low, 1: High <5>:LUT3_11 <5>/DFF15 0: RSTB from Matrix Output, 1: SETB from Matrix Output <6>:LUT3_11 <6>/DFF15 Output Select 0: Q output, 1: QB output <7>:LUT3_11 <7>/DFF15 or Latch Select 0: DFF function, 1: Latch function
Data[7:0]
<3:0>:LUT3_12 <3:0> <4>:LUT3_12 <4>/DFF16 Initial Polarity Select 0: Low, 1: High <5>:LUT3_12 <5>/DFF16 0: RSTB from Matrix Output, 1: SETB from Matrix Output <6>:LUT3_12 <6>/DFF16 Output Select 0: Q output, 1: QB output <7>:LUT3_12 <7>/DFF16 or Latch Select 0: DFF function, 1: Latch function
Data[7:0]
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
1480
Signal Function
1481
1482 LUT2_0/DFF0 setting
1483
B9
1484
1485
1486 LUT2_1/DFF1 setting
1487 1488 1489
1490
LUT2_2/DFF2 setting
1491 BA
1492 LUT2_0 or DFF0 Select
1493 LUT2_1 or DFF1 Select
1494 LUT2_2 or DFF2 Select
1495 Reserved
1496
1497
1498
BB
1499 1500
1501
1502
1503 1504
PGen data
1505
1506
BC
1507 1508
1509
1510
1511
Register Bit Definition
<0>:LUT2_0 <0> <1>:LUT2_0 <1>/DFF0 Initial Polarity Select 0: Low, 1: High <2>:LUT2_0 <2>/DFF0 Output Select 0: Q output, 1: QB output <3>:LUT2_0 <3>/DFF0 or Latch Select 0: DFF function, 1: Latch function <0>:LUT2_0 <0> <1>:LUT2_0 <1>/DFF0 Initial Polarity Select
0: Low, 1: High <2>:LUT2_0 <2>/DFF0 Output Select
0: Q output, 1: QB output <3>:LUT2_0 <3>/DFF0 or Latch Select
0: DFF function, 1: Latch function <0>:LUT2_0 <0> <1>:LUT2_0 <1>/DFF0 Initial Polarity Select
0: Low, 1: High <2>:LUT2_0 <2>/DFF0 Output Select
0: Q output, 1: QB output <3>:LUT2_0 <3>/DFF0 or Latch Select
0: DFF function, 1: Latch function 0: LUT2_0 1: DFF0 0: LUT2_1 1: DFF1 0: LUT2_2 1: DFF2
PGen Data[15:0]
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register
Bit 1512 1513 1514 1515
Signal Function LUT2_3_VAL or PGen_data
1516 LUT2_3 or PGen Select BD
1517 Active level selection for RST/SET
1518 LUT3_0 or DFF3 Select
1519
1520 1521
1522
LUT3_1 or DFF4 Select
1523
BE
LUT3_0_DFF3 setting
1524
1525
1526
1527 1528 1529 1530
1531
BF
1532 LUT3_1_DFF4 setting
1533 1534 1535
Register Bit Definition
LUT2_3<3:0> or PGen 4bit counter data<3:0>
0: LUT2_3 1: PGen 0: Active low level reset/set 1: Active high level reset/set 0: LUT3_0 1: DFF3 0: LUT3_1 1: DFF4
<1:0>: LUT3_0 <1:0>
<2>:LUT3_0 <2>/DFF3 stage selection 0: Q of first DFF; 1 Q of second DFF
<3>:LUT3_0 <3>/DFF3 Active level selection for RST/SET
0: Active low level reset/set, 1: Active high level reset/set <4>:LUT3_0 <4>/DFF3
0: RSTB from Matrix Output, 1: SETB from Matrix Output <5>:LUT3_0 <5>/DFF3 Initial Polarity Select
0: Low, 1: High <6>:LUT3_0 <6>/DFF3 Output Select
0: Q output, 1: QB output <7>:LUT3_0 <7>/DFF3 or Latch Select
0: DFF function, 1: Latch function
<2:0>: LUT3_1 <2:0>
<3>:LUT3_1 <3>/DFF4 Active level selection for RST/SET
0: Active low level reset/set, 1: Active high level reset/set <4>:LUT3_1 <4>/DFF4
0: RSTB from Matrix Output, 1: SETB from Matrix Output <5>:LUT3_1 <5>/DFF4 Initial Polarity Select
0: Low, 1: High <6>:LUT3_1 <6>/DFF4 Output Select
0: Q output, 1: QB output <7>:LUT3_1 <7>/DFF4 or Latch Select
0: DFF function, 1: Latch function
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte C0 C1 C2 C3 C4 C5
Register
Bit 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583
Signal Function
Rheostat0 data selection
Reserved Reserved Reserved Reserved Reserved Reserved
Rheostat0 current value (read only)
Reserved Reserved Reserved Reserved Reserved Reserved Matrix Input 0 Matrix Input 1 Matrix Input 2 Matrix Input 3 Matrix Input 4 Matrix Input 5 Matrix Input 6 Matrix Input 7 Matrix Input 8 Matrix Input 9 Matrix Input 10 Matrix Input 11 Matrix Input 12 Matrix Input 13 Matrix Input 14 Matrix Input 15
Register Bit Definition 0000000000: 0 ~ 1111111111:100k
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte C6 C7 C8 C9 CA
Register
Bit 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623
Signal Function
Matrix Input 16 Matrix Input 17 Matrix Input 18 Matrix Input 19 Matrix Input 20 Matrix Input 21 Matrix Input 22 Matrix Input 23 Matrix Input 24 Matrix Input 25 Matrix Input 26 Matrix Input 27 Matrix Input 28 Matrix Input 29 Matrix Input 30 Matrix Input 31 Matrix Input 40 Matrix Input 41 Matrix Input 42 Matrix Input 43 Matrix Input 44 Matrix Input 45 Matrix Input 46 Matrix Input 47 Matrix Input 48 Matrix Input 49 Matrix Input 50 Matrix Input 51 Matrix Input 52 Matrix Input 53 Matrix Input 54 Matrix Input 55 Matrix Input 56 Matrix Input 57 Matrix Input 58 Matrix Input 59 Matrix Input 60 Matrix Input 61 Matrix Input 62 Matrix Input 63
Register Bit Definition
Preliminary
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte
Register Bit
Signal Function
1624
1625
1626
CB
1627 1628
1629
1630
1631 1632
CNT0_Q
1633
1634
CC
1635 1636
1637
1638
1639
1640
1641
1642
CD
1643 1644
CNT5_Q
1645
1646
1647
1648
1649
1650
CE
1651 1652
CNT6_Q
1653
1654
1655
1656 Reserved
1657 Reserved
1658 Reserved
CF
1659 Reserved 1660 Reserved
1661 Reserved
1662 Reserved
1663 Reserved
Register Bit Definition
Preliminary
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte D0 D1 D2 D3 D4 D5
Register
Bit 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711
Signal Function
Rheostat1 data selection
Reserved Reserved Reserved Reserved Reserved Reserved
Rheostat1 current value (read only)
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register Bit Definition 0000000000: 0 ~ 1111111111:100k
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte D6 D7 D8 D9 DA DB
Register
Bit 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759
Signal Function
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register Bit Definition
Datasheet
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Preliminary
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
Signal Function
1760 Reserved
1761 Reserved
1762 Reserved
DC
1763 Reserved 1764 Reserved
1765 Reserved
1766 Reserved
1767 Reserved
1768 ID[24]: Reserved
1769 ID[25]: Reserved
1770 ID[27:26]: Reserved for Silicon Identification DD 1771 Service Bits (metal hard code)
1772
1773 1774
Reserved
1775
1776
1777
1778
DE
1779 1780
Reserved
1781
1782
1783
1784
1785
1786
DF
1787 1788
Reserved
1789
1790
1791
1792 1793
RPR<1:0> (2k register read selection bits)
1794
RPR<3:2>
E0
1795 (2k register write selection bits)
1796
1797 1798 1799
RH_PRB
Reserved Reserved Reserved
Register Bit Definition Reserved for NVM Power-Up Check Pattern Status (A55A match from Flag)
00: 2k register data is unprotected for read 01: 2k register data is partly protected for read 10: 2k register data is fully protected for read 11: reserved 00: 2k register data is unprotected for write 01: 2k register data is partly protected for write 10: 2k register data is fully protected for write 11: reserved 0: Rheostat Program Input from matrix enabled 1: Rheostat Program Input from matrix disabled
Datasheet
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Table 68: Register Map (Continued)
Address
Byte
Register Bit
1800
Signal Function
NPR<1:0> 1801 (2k NVM configuration selection bits)
1802
NPR<3:2> 1803 (Rheostat0 NVM configuration selection bits) E1
1804
NPR<5:4> 1805 (Rheostat1 NVM configuration selection bits)
1806 1807 1808
1809
Reserved Reserved
WPR<1:0> (EEPROM Write protect block bits range: page31~16)
E2
1810
WPRE (EEPROM Write protect register enable)
1811 Reserved
1812 Reserved
1813 Reserved
1814 Reserved
1815 Reserved
1816
1817 1818 1819
ERSE<4:0> (Page selection for erase)
E3 1820
1821
1822 1823
ERSE <2:0> (Erase enable)
1824
PRL (Protection lock)
1825 Reserved
1826 Reserved
E4 1827 Reserved 1828 Reserved
1829 Reserved
1830 Reserved
1831 Reserved
Register Bit Definition 00: 2k NVM Configuration data is unprotected for read and write/erase 01: 2k NVM Configuration data is fully protected for read 10: 2k NVM Configuration data is fully protected for write/erase 11: 2k NVM Configuration data is fully protected for read and write/erase 00: Rheosta0 NVM Configuration data is unprotected for read and write/erase 01: Rheosta0 NVM Configuration data is fully protected for read 10: Rheosta0 NVM Configuration data is fully protected for write/erase 11: Rheosta0 NVM Configuration data is fully protected for read and write/erase 00: Rheosta1 NVM Configuration data is unprotected for read and write/erase 01: Rheosta1 NVM Configuration data is fully protected for read 10: Rheosta1 NVM Configuration data is fully protected for write/erase 11: Rheosta1 NVM Configuration data is fully protected for read and write/erase
00: Upper 1/4 (page16~19) of EEPROM is write protected (default) 01: Upper 2/4 (page16~23) of EEPROM is write protected 10: Upper 3/4 (page16~27) of EEPROM is write protected 11: Entire (page16~31) EEPROM is write protected 0: No Software Write Protection enabled (default) 1: Write Protection is set by the state of the WPR<1:0> bits
Define the page address which will be erased ERSE<4> = 0 corresponds to the upper 2k NVM used for chip configuration ERSE<4> = 1 corresponds to the 2k EEPROM 000/001/010/011/100/101/111: erase disable 110: cause the NVM erase: full NVM (4k bits) erase for ERSCHIP = 1 if DIS_ERSCHIP=0 or page erase for ERSCHIP=0. 0: RPR/WPR/NPR setting can be changed 1: RPR/WPR/NPR setting cannot be changed
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte E5 E6 E7
Register
Bit 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854
Signal Function
Reserved
Rheostat0 tolerance data <0> Rheostat0 tolerance data <1> Rheostat0 tolerance data <2> Rheostat0 tolerance data <3> Rheostat0 tolerance data <4> Rheostat0 tolerance data <5> Rheostat0 tolerance data <6> Rheostat0 tolerance data <7> Rheostat0 tolerance data <8> Rheostat0 tolerance data <9> Rheostat0 tolerance data <10> Rheostat0 tolerance data <11> Rheostat0 tolerance data <12> Rheostat0 tolerance data <13> Rheostat0 tolerance data <14>
1855 Sign of Rheostat0 tolerance data
1856 Rheostat1 tolerance data <0>
1857 Rheostat1 tolerance data <1>
1858 Rheostat1 tolerance data <2>
E8
1859 Rheostat1 tolerance data <3> 1860 Rheostat1 tolerance data <4>
1861 Rheostat1 tolerance data <5>
1862 Rheostat1 tolerance data <6>
1863 Rheostat1 tolerance data <7>
1864 Rheostat1 tolerance data <8>
1865 Rheostat1 tolerance data <9>
1866 Rheostat1 tolerance data <10>
1867 Rheostat1 tolerance data <11> E9 1868 Rheostat1 tolerance data <12>
1869 Rheostat1 tolerance data <13>
1870 Rheostat1 tolerance data <14>
1871 Sign of Rheostat1 tolerance data
1872
EA
1873 1874
Reserved
1875
Register Bit Definition 0: "+" 1: "-" 0: "+"; 1: "-"
Preliminary
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte EA
EB
Register
Bit 1876 1877 1878 1879 1880 1881 1882 1883 1884
Signal Function Reserved
Reserved Reserved
1885 Reserved
1886 Reserved
1887 Reserved
1888 Reserved
1889 Reserved
1890 Reserved
EC
1891 Reserved 1892 Reserved
1893 Reserved
1894 Reserved
1895 Reserved
1896 Reserved
1897 Reserved
1898 Reserved
ED
1899 Reserved 1900 Reserved
1901 Reserved
1902 Reserved
1903 Reserved
1904 Reserved
1905 Reserved
1906 Reserved
EE
1907 Reserved 1908 Reserved
1909 Reserved
1910 Reserved
1911 Reserved
1912 Reserved
1913 Reserved
1914 Reserved
EF
1915 Reserved 1916 Reserved
1917 Reserved
1918 Reserved
1919 Reserved
Register Bit Definition
Preliminary
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte
Register Bit
Signal Function
1920
1921
1922
F0
1923 1924
Reserved
1925
1926
1927
1928
1929
1930
F1
1931 1932
Reserved
1933
1934
1935
1936
1937
1938
F2
1939 1940
Reserved
1941
1942
1943
1944 Service page lock bit
1945 BG Chopper off
1946 Reserved F3 1947 Reserved
1948 BG register power down
1949 Reserved
1950 Reserved
1951 Reserved
1952 Reserved
1953 Reserved
1954 Reserved
F4
1955 Reserved
1956 Reserved
1957 Reserved
1958 Reserved
1959 Reserved
Register Bit Definition
0: Service page can be changed 1: Service page is locked 0: chopper enable 1: chopper off 0: power on 1: power off
Preliminary
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte F5 F6 F7 F8 F9
Register
Bit 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999
Signal Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
I2C write mask bits
Reserved
Reserved
Reserved
Reserved
Register Bit Definition 0: overwrite; 1: mask the bit which set to high
Preliminary
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte FA
Register Bit 2000 2001 2002 2003 2004
2005
Signal Function Reserved Reserved
2006 Reserved
2007 Reserved
2008
2009
2010 Reserved
FB
2011 2012
2013 Reserved
2014 Reserved
2015 Reserved
2016
2017
2018 Reserved
FC
2019 2020
2021 Reserved
2022 Reserved
2023 Reserved
2024
2025
2026 Reserved
FD
2027 2028
2029 Reserved
2030 Reserved
2031 Reserved
2032
2033
2034 Reserved
FE
2035 2036
2037 Reserved
2038 Reserved
2039 Reserved
Register Bit Definition
Preliminary
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Table 68: Register Map (Continued)
Address
Byte FF
Register
Bit 2040 2041 2042 2043 2044 2045 2046 2047
Signal Function
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register Bit Definition
Preliminary
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
22 Package Top Marking System Definition
22.1 STQFN-24L 3 MM X 3 MM X 0.55 MM, 0.4P FCD PACKAGE
Preliminary
Part Code
Date Code Pin 1
Identifier
PPPPP WWNNN
ARR
S/N Code
Assembly House Code + Revision Code
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
23 Package Information
23.1 PACKAGE OUTLINES FOR STQFN 24L 3 MM X 3 MM X 0.55 MM 0.4P GREEN PACKAGE JEDEC MO-220
Preliminary
Top View
Side View
Bottom View
23.2 STQFN HANDLING Be sure to handle STQFN package only in a clean, ESD-safe environment. Tweezers or vacuum pick-up tools are suitable for handling. Do not handle STQFN package with fingers as this can contaminate the package pins and interface with solder reflow.
23.3 SOLDERING INFORMATION Please see IPC/JEDEC J-STD-020: for relevant soldering information. More information can be found at www.jedec.org.
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
24 Ordering Information
SLG47004V SLG47004VTR
Part Number
Type 24-pin STQFN 24-pin STQFN - Tape and Reel (5k units)
24.1 TAPE AND REEL SPECIFICATIONS
Package Type
# of Pins
Nominal Package Size
(mm)
Max Units per Reel per Box
Reel & Hub Size
(mm)
Leader (min)
Pockets
Length (mm)
Trailer (min)
Pockets
Length (mm)
Tape Width (mm)
Part Pitch (mm)
STQFN 24L
3 mm x3 mm Ta0p.4ePanFdCReel
24 3 x 3 x 0.55 Specifications:
Green
5.000
10.000 330 / 100
24.2
CARRIPEaRckaTgAe PTyEpeDRAWING
AND
oDf IPMinEs NSNIOomNSiinSzael
Package (mm)
Units per Reel
42
336
42
336
12
8
Maximum Units Reel & Hub per pizza box Size (mm)
Trailer (Minimum) Pockets Length (mm)
Leader (Minimum)
Pockets
Length (mm)
TSSOP 20L 173 mPiloGcrkeeentBTM PocketBTM P20ocket
Package Length
Width
Depth
CarTriyepr eTape
(mm) Drawing
&
(mm) Dimension:
(mm) Unit:mm
In6.d5xe6x.4Hole Pitch (mm)
4,P00o0cket Pitch (mm)
4,I0n0d0 ex Ho3l3e0 Diameter (mm)
/I1n0d0 ex Ho4l2e to Tape
Edge
(mm)
Index33H6ole to Pocket
Center
(mm)
42
Tape Width
(mm)
336
Pocke Width
16
DAe0finition/ SymboBl 0
STQFN 24L
3 mm x3 mm PK0G.4tyPpeFC
6.8
6.9
Green
TSSOP 20L 173 mil Green
Pocket BKT0M
Length
P0
Pocket BTM Width
1.6
4
Ao
Bo
PockePt 1
Depth
8
Ko
Index HoleD0
Pitch
Pocket
Pitch
EIndex Hole
Diameter
IndeFx hole to
Tape edge
Index hWole to
Pocket
nter
Tape Width
Tape Thickne
1.5
1.75
7.5
16
Po
P1
Do
6.8
6.9
1.6
1.5
1.75
7.5
16
0.3
Note: Orientation in carrier: Pin1 is at upper left corner (Quadrant1). Note: 1.Orientation in carrier: Pin1 is at upper left corner (Quadrant 1).
Refer to EIA-481 specification
Datasheet
CFR0011-120-00
Revision 2.3 286 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
25 Layout Guidelines
SLG47004 has two analog supply pins and two ground pins: VDD, VDDA, GND and AGND. Separating analog supply voltage from digital one helps to minimize noise generated by the digital part of IC.
Analog supply voltage domain: operational amplifiers, charge pumps for op amps, charge pumps for Oscillators, bias generators and regulators for op amps, digital rheostats, Chopper ACMP, HD Buffer, Vref of op amp and HD Buffer, Low Power Bandgap.
Digital supply voltage domain: ACMPs, Vref of ACMPs, Vref output buffers, Oscillator 0, Oscillator 1, Oscillator 2, I2C macrocell, NVM logic, Multi-function and Combination Function macrocells.
Analog and digital grounds must be connected together on the PCB board. The place of connection depends on users schematic. For application cases with low digital current of SLG47004, both AGND and GND should be connected to analog ground plane.
25.1 STQFN 24L 3 MM X 3 MM X 0.55 MM 0.4P GREEN PACKAGE
Datasheet
CFR0011-120-00
Revision 2.3 287 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Glossary
A ACK ACMP ACMPH ACMPL AS
Acknowledge bit Analog Comparator Analog Comparator High Speed Analog Comparator Low Power Analog Switch
B
BG
Bandgap
C CLK CMO CNT
Clock Connection matrix output Counter
D DFF DLY DNL DR
D Flip-Flop Delay Differential Non-Linearity Digital Rheostat
E EC ERSE ERSR ESD EV
Electrical Characteristics Erase Enable Erase Register Electrostatic discharge End Value
F FSM
Finite State Machine
G GPI GPIO GPO
General Purpose Input General Purpose Input/Output General Purpose Output
I IN In Amp DNL
Input Instrumentation Amplifier Differential Non-Linearity
Datasheet
CFR0011-120-00
Revision 2.3 288 of 292
Preliminary
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
INL
Integral Non-Linearity
IO
Input/Output
L
LPF
Low Pass Filter
LSB
Least Significant Bit
LUT
Look Up Table
LV
Low Voltage
M MSB MTP MUX
Most Significant Bit Multiple-Time-Programmable Multiplexer
N NPR nRST NVM
Non-Volatile Memory Read/Write/Erase Protection Reset Non-Volatile Memory
O OA OD OE Op Amp OSC OUT
Operational Amplifier Open-Drain Output Enable Operational Amplifier Oscillator Output
P PD PGen POR PP PRL PT PWR P DLY
Power-down Pattern Generator Power-On Reset Push-Pull Protect Lock Bit Programmable Trim Power Programmable Delay
R RPR RPRB RPRL
Register Read/Write Protection Register Read/Write Protection Bit Register Protection Read/Write/Erase Lock
Datasheet
CFR0011-120-00
Revision 2.3 289 of 292
Preliminary
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
R/W
Read/Write
S SCL SDA SLA SMT SPST SV
I2C Clock Input I2C Data Input/Output Slave Address With Schmitt Trigger Single-pole/Single throw nSET Value
T
TS
Temperature Sensor
V
Vref
Voltage Reference
W WOSMT WPB WPR WPRE WS
Without Schmitt Trigger Write Protect Bit Write Protection Register Write Protect Enable Wake and Sleep Controller
Preliminary
Datasheet
CFR0011-120-00
Revision 2.3 290 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Revision History
Revision
2.3
2.2 2.1 2.0
Date
2-Mar-2021
3-Dec-2020 13-Nov-2020 9-Nov-2020
Description Updated Tape and Reel Specification Added Op Amps, Analog Switches, Rheostats, OSCs, ACMPs, TS, Vref Typical Performance Updated Thermal Resistance parameter in Absolute Maximum Ratings Table Updated Op Amp Typical Performance Updated 100K Digital Rheostat EC Updated table Read/Write Register Protection Options Updated Analog Switch Spec Conditions Fixed typos Removed TSSOP Package Preliminary version
Datasheet
CFR0011-120-00
Revision 2.3 291 of 292
2-Mar-2021
� 2021 Dialog Semiconductor
SLG47004
GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features
Preliminary
Status Definitions
Revision Datasheet Status
1.<n>
Target
Product Status Development
2.<n>
Preliminary
Qualification
3.<n>
Final
Production
4.<n>
Obsolete
Archived
Definition
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
This datasheet contains the specifications and preliminary characterization data for products in pre-production. Specifications may be changed at any time without notice in order to improve the design.
This datasheet contains the final specifications for products in volume production. The specifications may be changed at any time in order to improve the design, manufacturing and supply. Major specification changes are communicated via Customer Product Notifications. Datasheet changes are communicated via www.dialog-semiconductor.com.
This datasheet contains the specifications for discontinued products. The information is provided for reference only.
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Datasheet
CFR0011-120-00
Revision 2.3 292 of 292
2-Mar-2021
� 2021 Dialog Semiconductor