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Zynq UltraScale RFSoC RF Data Converter LogiCORE IP Product Guide

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Provides a configurable wrapper to allow the RF-DAC and RF-ADC blocks to be used in IP integrator designs.

ultrascale , rfsoc, digital-analog, digital to analog, analog to digital, rfadc, rfdac, up-converter, down converter, cable, HSADC, HSDAC, ADC, DAC, Zynq, RFSoC, RF, PLL, FIFO, API, Logic Interface, Clock Inputs, Tile Structure, Libmetal, wireless, mmwave, millimeter wave, radio

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Zynq UltraScale+ RFSoC RF Data Converter v2.2
LogiCORE IP Product Guide
Vivado Design Suite
PG269 (v2.2) October 30, 2019

Table of Contents
Chapter 1: IP Facts......................................................................................................... 5
Features........................................................................................................................................ 5 IP Facts..........................................................................................................................................6
Chapter 2: Overview......................................................................................................7
RF-ADC.......................................................................................................................................... 9 RF-DAC........................................................................................................................................ 13 Applications................................................................................................................................15 Licensing and Ordering............................................................................................................ 15
Chapter 3: Product Specification......................................................................... 16
Performance.............................................................................................................................. 18 Resource Use............................................................................................................................. 18 Port Descriptions.......................................................................................................................18 Register Space........................................................................................................................... 25
Chapter 4: Designing with the Core................................................................... 36
IP Core Configuration in the Vivado Design Suite.................................................................36 Software Driver..........................................................................................................................36 RF-ADC........................................................................................................................................ 37 RF-DAC........................................................................................................................................ 75 Quadrature Modulator Correction .........................................................................................98 Coarse Delay............................................................................................................................ 101 Dynamic Update Events......................................................................................................... 102 PLL............................................................................................................................................. 104 Interrupt Handling.................................................................................................................. 105 Clocking.................................................................................................................................... 110 Resets........................................................................................................................................115 Power-up Sequence................................................................................................................ 116 Bitstream Reconfiguration.....................................................................................................118 Interfacing to the AXI4-Stream Interface............................................................................. 118 Applications Overview............................................................................................................ 119

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Chapter 5: Design Flow Steps...............................................................................138
Customizing and Generating the Core................................................................................. 138 Simulation................................................................................................................................ 152 Synthesis and Implementation............................................................................................. 152
Chapter 6: Example Design................................................................................... 153
RF-ADC Data Capture Block................................................................................................... 154 RF-DAC Data Stimulus Block.................................................................................................. 156 Digital Data Format.................................................................................................................158
Chapter 7: Test Bench...............................................................................................159
Analog Signaling..................................................................................................................... 161
Appendix A: Upgrading........................................................................................... 164
Changes from V2.1 to V2.2 .................................................................................................... 164 Changes from V2.0 to V2.1..................................................................................................... 164 Changes from V1.2 to V2.0..................................................................................................... 166 Changes from V1.1 to V1.2..................................................................................................... 166
Appendix B: Debugging...........................................................................................168
Finding Help on Xilinx.com.................................................................................................... 168 Debug Tools............................................................................................................................. 169 Hardware Debug..................................................................................................................... 170 Interface Debug...................................................................................................................... 170
Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Baremetal/Linux Driver................................................................................................ 172
Overview...................................................................................................................................172 Data Structures........................................................................................................................173 User API Functions.................................................................................................................. 190 Interrupt Handling.................................................................................................................. 228 In-line Functions......................................................................................................................234
Appendix D: RF Analyzer.........................................................................................250
Clocking.................................................................................................................................... 252 Address Space..........................................................................................................................254 User Interface.......................................................................................................................... 254 Hardware Trigger.................................................................................................................... 255

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Appendix E: Additional Resources and Legal Notices............................257
Xilinx Resources.......................................................................................................................257 Documentation Navigator and Design Hubs...................................................................... 257 References................................................................................................................................257 Revision History....................................................................................................................... 258 Please Read: Important Legal Notices................................................................................. 260

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Chapter 1
IP Facts
The Xilinx� LogiCORETM IP Zynq� UltraScale+TM RFSoC RF Data Converter IP core provides a configurable wrapper to allow the RF-DAC and RF-ADC blocks to be used in IP integrator designs.
IMPORTANT! In this guide reference is made to the Dual and Quad tiles; for the actual sampling rate specifications, see the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926). Note that Dual and Quad refers to the tile configuration and not the number of converters.
Features
� Up to 16 14-bit RF-DACs � Eight 12-bit Dual RF-ADCs, or 16 12-bit Quad RF-ADCs, depending on device � Supports alignment between multiple converters � Pre-programs RF-DAC and RF-ADC with key user-defined parameters � Multiple AXI4-Stream data interfaces for RF-ADCs and RF-DACs � Single AXI4-Lite configuration interface � 1x (bypass), 2x, 4x, 8x interpolation � 1x (bypass), 2x, 4x, 8x decimation � Digital complex mixers � Numerical Controlled Oscillator (NCO) � Quadrature Modulation Correction (QMC) � On-chip PLL and VCO per tile

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Chapter 1: IP Facts

IP Facts

LogiCORE IP Facts Table

Supported Device Family1

Core Specifics Zynq� UltraScale+TM RFSoC

Supported User Interfaces

AXI4-Stream, AXI4-Lite Control/Status

Resources

Performance and Resource Use web page

Provided with Core

Design Files

RTL

Example Design

Verilog

Test Bench

Verilog

Constraints File

Xilinx Design Constraints (XDC)

Simulation Model Supported S/W Driver2

Verilog Standalone and Linux Tested Design Flows3

Design Entry

Vivado� IP Integrator

Simulation

For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

Synthesis

Vivado Synthesis

Support

Release Notes and Known Issues

Master Answer Record: 69907

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

Xilinx Support web page

Notes:
1. For a complete list of supported devices, see the Vivado� IP catalog.
2. Stand-alone driver details can be found in the software development kit <Install Directory>/Vitis/<Release>/data/ embeddedsw/doc/Xilinx_drivers.htm.
Bare Meta/Linux documentation is available in Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/ Linux Driver.
3. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.

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Chapter 2
Overview
The Xilinx� Zynq� UltraScale+TM RFSoC family integrates the key subsystems required to implement a complete software-defined radio including direct RF sampling data converters, enabling eCPRI and Gigabit Ethernet-to-RF on a single, highly programmable SoC.
Each RFSoC offers multiple RF-sampling analog-to-digital (RF-ADC) and RF-sampling digital-toanalog (RF-DAC) data converters. The data converters are high-precision, high-speed and powerefficient. Both are highly configurable and tightly integrated with the programmable logic (PL) resources of the Zynq UltraScale+ RFSoC.
The RF-ADC supports device-dependent sample rates and input signal frequencies listed in the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889), with excellent dynamic range performance.
The RF-DAC generates output carrier frequencies at rates defined in the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926), depending on the device (see the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) for device information.
The RF data converters also include power efficient digital down converters (DDCs) and digital up converters (DUCs) that include programmable interpolation and decimation rates, a numerically controlled oscillator (NCO), and a complex mixer. The DDCs and DUCs can also support multiband operation. The following figure shows the block diagram of the Zynq� UltraScale+TM RFSoC RF Data Converter.
The RF-ADCs and RF-DACs are organized into tiles, each containing two or four RF-ADCs or four RF-DACs. Multiple tiles are available in each Zynq� UltraScale+TM RFSoC (see the specific device data sheet for the number of tiles and converters per device). Each tile also includes a block with a PLL and all the necessary clock handling logic and distribution routing for the analog and digital logic.
This guide describes the Zynq� UltraScale+TM RFSoC RF Data Converter IP core and software drivers that are used to configure the data converters and instantiate them for use in a design.
For device specifications and additional information, see:
� Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) � Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) � Zynq UltraScale+ Device Technical Reference Manual (UG1085).

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Chapter 2: Overview

Figure 1: Zynq� UltraScale+TM RFSoC RF Data Converter IP Core in Zynq UltraScale+ RFSoC

Zynq UltraScale+ RFSoC

Data Converter IP Core

Processing System Quad ARM Cortex-A53 Dual ARM Cortex-R5

AXI4-Stream AXI4-Stream

DUC
DAC
DUC
DAC

4 to 16 TX Channels

Programmable Logic
GTY Serial Transceivers

AXI4-Lite AXI4-Stream AXI4-Stream

Control and Configuration
DDC
ADC
DDC
ADC

4 to 16 RX Channels

Figure 2: RF-ADC Tile Structure

X19532-062819

mX3_axis mX2_axis

Data Path Data Path

ADC

VinX3 mX3_axis

Data Path

ADC

VinX2 mX2_axis

Data Path

ADC ADC

VinX_23

mX1_axis

Data Path

ADC

mX0_axis

Data Path

ADC

Quad RF-ADC Tile

VinX1 mX1_axis VinX0 mX0_axis

Data Path

ADC

Data Path

ADC

Dual RF-ADC Tile

VinX_01
X23275-100919

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Chapter 2: Overview

Figure 3: RF-DAC Tile Structure

sX3_axis sX2_axis

Data Path Data Path

DAC DAC

sX1_axis sX0_axis

Data Path Data Path

DAC DAC

Quad RF-DAC Tile

VoutX3 VoutX2 VoutX1 VoutX0
X23274-092319

RF-ADC
There are two types of RF-ADC tile, the Dual RF-ADC and the Quad RF-ADC tile. The type of tile available is device dependent (see the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889)). Each tile includes a PLL and clocking instance. All RF-ADCs within a tile share this common clocking infrastructure.

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Chapter 2: Overview

The Quad RF-ADC tile consists of four RF-ADCs, arranged in two pairs. Each of these converters can be configured individually for real input signals or, as a pair, for I/Q input signals. The following figure shows an overview of the Quad RF-ADC tile.
Figure 4: Quad RF-ADC Tile Overview

VCM
VIN_P VIN_N

BUF

VIN_P VIN_N

BUF

Sampling Clock/ PLL Reference Clock
ADC_CLK_P
ADC_CLK_N
PLL

ADC
Quad Tile
ADC
Quad Tile
Sampling Clock

0� 90�

0�

90�

Q NCO

NCO

DDC

VIN_P VIN_N
VIN_P VIN_N VCM

BUF BUF

ADC
Quad Tile
ADC
Quad Tile

0� 90� 0� 90�
NCO
NCO

I Q Q
X18282-090419

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Chapter 2: Overview
The Dual RF-ADC tile consists of two RF-ADCs. These converters can be configured individually for real input signals or, as a pair, for I/Q input signals. The following figure shows an overview of the Dual RF-ADC tile.
Figure 5: Dual RF-ADC Tile Overview

VCM

VIN_P VIN_N

100

BUF

RFADACDC
D4uGaSl T/sile121-2b-ibtsits

Sampling Clock/ PLL Reference Clock
ADC_CLK_P
100
ADC_CLK_N
PLL

Sampling Clock

I
0� 90�
Q NCO
DDC

VIN_P VIN_N

100

BUF

VCM

RFADACDC
D4uGaSl T/sile121-2b-ibtsits

0� 90�
NCO

I Q
X18283-070219

RF-ADC Features
� Tile configuration Four or two RF-ADCs and one PLL per tile 12-bit RF-ADC resolution, with 16-bit digital signal processing datapath; each 12-bit data stream is MSB-aligned to 16 bit samples at the output of the RF-ADC core before passing to the DDC block

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Chapter 2: Overview
Implemented as either four channels (Quad) or two channels (Dual) (the sampling rate is device dependent; for the actual sampling rate specifications, see the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926))
� Decimation filters 1x (bypass filter), 2x, 4x, 8x 80% of Nyquist bandwidth, 89 dB stop-band attenuation
� Digital Complex Mixers Full complex mixers support real or I/Q inputs from the RF-ADC 48-bit Numeric Controlled Oscillator (NCO) per RF-ADC Fixed Fs/4, Fs/2 low power frequency mixing mode, where Fs is the sample frequency I/Q and real input signals supported
� Single/multi-band flexibility 2x bands per RF-ADC pair 4x bands per Quad RF-ADC tile Can be configured for real or I/Q inputs
� Full bandwidth of the RF-ADC can be accessed in bypass mode � Input signal amplitude threshold: Two programmable threshold flags per RF-ADC � Built-in digital correction for external analog quadrature modulators:
Supports gain, phase, and offset correction for an I/Q input pair (two RF-ADCs) � SYSREF input signal for multi-channel synchronization � Flexible AXI4-Stream interface supports a wide range of programmable logic clock rates and
converter sample rates � Per tile current-mode logic (CML) clock input buffer with on-chip calibrated 100
termination; supplies the RF-ADC sampling clocks or provides a reference clock for the onchip PLL � Dedicated high-speed, high-performance, differential input buffer per RF-ADC with on-chip calibrated 100 termination (on-die termination) � Output common mode reference voltage for DC-coupling RF-ADC inputs

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Chapter 2: Overview

RF-DAC
Each RF-DAC tile consists of four RF-DACs that can be configured individually for real output signals or, as a pair, for I/Q output signal generation. Each RF-DAC runs at a data rate specified in the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926). The RF-DAC tile has one PLL and a clocking instance. The following figure shows an overview of the RF-DAC.
Figure 6: RF-DAC Overview

0�

90�

Q NCO
Q NCO

0�

90�

DUC

0�

90�

Q NCO

0�

90�

Q NCO

DAC DAC

DAC_AVTT
VOUT_P VOUT_N

VOUT_P VOUT_N

Sampling Clock/ PLL Reference Clock
DAC_CLK_P
100
DAC_CLK_N
PLL

DAC DAC

VOUT_P VOUT_N

VOUT_P VOUT_N
DAC_AVTT
X18281-082019

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Chapter 2: Overview
RF-DAC Features
� Tile configuration Four RF-DACs and one PLL per tile 14-bit RF-DAC resolution with 16-bit digital signal processing path; the data is MSBaligned to 16 bits Device-dependent sampling speed; see the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) Device-dependent full power output bandwidth; see the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889)
� Interpolation 1x (bypass filter), 2x, 4x, 8x 80% pass band, 89 dB stop band attenuation
� Digital Complex Mixers Full complex mixers support real or I/Q output signals to the RF-DACs 48-bit NCO per RF-DAC Fixed Fs/4, Fs/2 low-power frequency mixing mode Supports mixed mode RF-DAC functionality which maximizes RF-DAC power in the second Nyquist zone
� Single/multi-band flexibility 2x bands per RF-DAC pair 4x bands per RF-DAC tile Can be configured for real or I/Q outputs
� Full Nyquist bandwidth in bypass mode � Digital Correction for external analog quadrature modulators:
Supports gain, phase, and offset correction for an I/Q output pair (two RF-DACs) � Sinc correction for first Nyquist zone � External input signal (SYSREF) for multi-channel synchronization of data converter channels � Per tile current mode logic (CML) clock input buffer with on-chip calibrated 100 termination;
supplies the RF-DAC sampling clocks or provides a reference clock for the on-chip PLL � Supports 20 mA or 32 mA output power mode
For the RF-ADC and RF-DAC operating and absolute maximum/minimum parameters see:

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Chapter 2: Overview
� Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) � Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)
Applications
� Multi-band, multi-mode 3G, 4G, and 5G cellular radios � Multiple antenna systems (Massive MIMO, AAS, AAA) � Cable infrastructure (DOCSIS 3.x) � Software defined radios � Microwave and millimeter wave radios � Test and measurement applications
Related Information Applications Overview
Licensing and Ordering
This Xilinx� LogiCORETM IP module is provided at no additional cost with the Xilinx Vivado� Design Suite under the terms of the Xilinx End User License. Note: To verify that you need a license, check the License column of the IP Catalog. Included means that a license is included with the Vivado� Design Suite; Purchase means that you have to purchase a license to use the core. Information about other Xilinx� LogiCORETM IP modules is available at the Xilinx Intellectual Property page. For information about pricing and availability of other Xilinx� LogiCORE IP modules and tools, contact your local Xilinx sales representative.

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Chapter 3: Product Specification
Chapter 3
Product Specification
The Zynq� UltraScale+TM RFSoC RF Data Converter IP core provides a way of instantiating all the RF-DAC and RF-ADC blocks in Zynq UltraScale+ RFSoCs in IP integrator. A single IP core instance allows access to all converters in the device. The IP ensures that all enabled blocks are powered up and that unused converters are disabled.

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Chapter 3: Product Specification

AXI4-Stream x4 or x2 AXI4-Stream x4 or x2 AXI4-Stream x4 or x2
AXI4-Stream x4 or x2 AXI4-Lite Real-Time

Figure 7: IP Core Overview

Zynq UltraScale+ RFSoC RF Data Converter IP Core

Power-On Sequencer

RF-ADC Tile 224

AXIS Out

Analog

Inputs

Power-On Sequencer

RF-ADC Tile 225

AXIS Out

Analog

Inputs

Power-On Sequencer

RF-ADC Tile 226

AXIS Out

Analog

Inputs

Power-On Sequencer

RF-ADC Tile 227

AXIS Out

Analog

Inputs

Control & Status IF

Control & Status Signals

VIN x4 or x2 VIN x4 or x2 VIN x4 or x2 VIN x4 or x2

AXI4-Stream x4 or x2

Power-On Sequencer

RF-DAC Tile 228

AXIS Data Inputs

Analog Outputs

VOUT x4

AXI4-Stream x4 or x2

Power-On Sequencer

RF-DAC Tile 229

AXIS Data Inputs

Analog Outputs

VOUT x4

AXI4-Stream x4 or x2

Power-On Sequencer

RF-DAC Tile 230

AXIS Data Inputs

Analog Outputs

VOUT x4

AXI4-Stream x4 or x2

Power-On Sequencer

RF-DAC Tile 231

AXIS Data Inputs

Analog Outputs

VOUT x4
X18850-082019

An RF-ADC tile has two or four RF-ADCs; an RF-DAC tile has four RF-DACs. The number of converters and the maximum sample rate depend on the device and package. The converters in each tile are the same type.

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Related Information Power-up Sequence

Chapter 3: Product Specification

Performance
To see the performance of the RF-ADC and RF-DAC blocks, see the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
Related Information Clocking

Resource Use
For full details about performance and resource utilization, visit the Performance and Resource Utilization web page (registration required).

Port Descriptions

Configuration Interface Ports

Table 1: Configuration Interface Ports

Port Name
s_axi_aclk
s_axi_aresetn
s_axi_awaddr[17:0] s_axi_awvalid s_axi_awready s_axi_wdata[31:0] s_axi_wstrb[3:0] s_axi_wvalid s_axi_wready s_axi_bresp[1:0] s_axi_bvalid s_axi_bready

I/O

Clock

N/A

s_axi_aclk

Out

s_axi_aclk

Out

s_axi_aclk

Out

s_axi_aclk

Out

s_axi_aclk

Description
AXI clock input (continuous clock) Reset for the aclk domain. The deassertion of the reset should be synchronous to s_axi_aclk. Write Address Write Address Valid Write Address Ready Write Data Write Data Byte Strobe Write Data Valid Write Data Ready Write Response Write Response Valid Write Response Ready

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Chapter 3: Product Specification

Table 1: Configuration Interface Ports (cont'd)

Port Name
s_axi_araddr[17:0] s_axi_arvalid s_axi_arready s_axi_rdata[31:0] s_axi_rresp[1:0] s_axi_rvalid s_axi_rready irq

I/O

Clock

s_axi_aclk

Out

s_axi_aclk

Out

s_axi_aclk

Out

s_axi_aclk

Out

s_axi_aclk

Out

s_axi_aclk

Description
Read Address Read Address Valid Read Address Ready Read Data Read Response Read Data Valid Read Data Ready Interrupt output

Multi-Tile Synchronization Ports

Table 2: Multi-Tile Synchronization Ports

Port Name

I/O

Clock

Description1

sysref_in_p

N/A

External analog SYSREF input

sysref_in_n

N/A

External analog SYSREF input

user_sysref_adc

RF-ADC SYSREF input from programmable logic

m0_axis_aclk (PL)/ user design; synchronous to RF-ADC tile 0 PL

clock

user_sysref_dac

RF-DAC SYSREF input from programmable logic

s0_axis_aclk (PL)/user design; synchronous to RF-DAC tile 0 PL

clock

Notes: 1. See the Multi-Tile Synchronization section in the Applications sub-section for more information.

Related Information Multi-Tile Synchronization

Clock Ports Common to RF-DAC Tile

Table 3: Clock Ports Common to RF-DAC Tile

Port Name1

I/O

Clock

dacX_clk_p

N/A

dacX_clk_n

N/A

clk_dacX

Out

N/A

Notes: 1. X refers to the location of the tile in the converter column.

Description
RF-DAC on-chip PLL reference clock or sampling clock input
RF-DAC on-chip PLL reference clock or sampling clock input
Output clock to user logic

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Chapter 3: Product Specification

AXI4-Stream Related Ports for RF-DACs

Table 4: AXI4-Stream Related Ports for RF-DACs

Port Name1

I/O

Clock

Description

sX_axis_aclk

N/A

Clock input for RF-DAC data input

sX_axis_aresetn

N/A

Synchronous reset for the sX_axis_aclk domain. This should be held low until sX_axis_aclk is stable.

sXY_axis_tdata[M:0]

sX_axis_aclk AXI4-Stream data input

sXY_axis_tvalid

sX_axis_aclk AXI4-Stream valid

sXY_axis_tready

Out

sX_axis_aclk AXI4-Stream ready

voutXZ_p

Out

N/A

Analog output

voutXZ_n

Out

N/A

Analog output

Notes:
1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC block in the tile (0 to 3). Z refers to the location of the RF-DAC in the tile (0 to 3). M is the number of samples per AXI4-Stream word * 16 for converter XY.

Real-Time Signal Interface Ports for RF-DACs

Table 5: Real-Time Signal Interface Ports for RF-DACs

Port Name1

I/O

Clock

Description

dacXZ_fast_shutdown[2:0]

RF-DAC fast shutdown

001 - Scale output data by 0.5

N/A

011 - Scale output data by 0.25

111 - Scale output data by 0

Others - Normal operation

dacXY_pl_event

RF-DAC PL event

clk_dacX

Assert to update RF-DAC settings from the PL

Notes:
1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC block in the tile (0 to 3). Z refers to the location of the RF-DAC in the tile (0 to 3).

Real-Time NCO Signal Interface Ports for RF-DACs

Table 6: Real Time NCO Signal Interface Ports for RF-DACs

Port Name1
dacXY_nco_freq[47:0] dacXY_nco_phase[17:0]

I/O

Clock

Description

Requested NCO frequency setting. This is a 48 bit

s_axi_aclk

signed input representing the NCO frequency. The value ranges from -Fs/2 to Fs/2, where Fs is the

sampling rate.

Requested NCO Phase setting. This is a 18 bit

s_axi_aclk signed number representing the NCO phase. The

value ranges from -180 to 180 degrees.

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Chapter 3: Product Specification

Table 6: Real Time NCO Signal Interface Ports for RF-DACs (cont'd)

Port Name1

I/O

Clock

Description

dacXY_nco_phase_rst

s_axi_aclk

NCO phase reset. Used to align the NCO phases across the converter.

dacXY_update_enable[5:0]

Enable register writes

� Bit 5: Enable write to phase reset

� Bit 4: Enable write to NCO phase bits 17:16

s_axi_aclk

� Bit 3: Enable write to NCO phase bits 15:0

� Bit 2: Enable write to NCO frequency bits 47:32

� Bit 1: Enable write to NCO frequency bits 31:16

� Bit 0: Enable write to NCO frequency bits 15:0

dacX_update_request

s_axi_aclk

Asserted High to request an update of the NCO settings.

dacX_nco_update_busy[1:0]

Update busy register

� Bit 1: High while SYSREF is disabled. Applicable

Out

s_axi_aclk

for RF-DAC tile 228 when multi-tile

synchronization has been selected

� Bit 0: High when the NCO update is in progress.

dac0_sysref_int_gating

Applicable for RF-DAC tile 228 when multi-tile

s_axi_aclk

synchronization is enabled. When asserted the disabling of the SYSREF is carried out by the IP

core.

dac0_sysref_int_reenable

Applicable for RF-DAC tile 228 when multi-tile

synchronization is enabled. When asserted the IP

s_axi_aclk core re-enables the SYSREF after the NCO update

process has completed. In multi-device systems all

devices should be re-enabled at the same time.

Notes: 1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC block in the tile (0 to 3).

Clock Ports Common to RF-ADC Tile

Table 7: Clock Ports Common to RF-ADC Tile

Port Name1

I/O

Clock

adcX_clk_p

N/A

adcX_clk_n

N/A

clk_adcX Notes:

Out

N/A

1. X refers to the location of the tile in the converter column.

Description
RF-ADC on-chip PLL reference clock or sampling clock input
RF-ADC on-chip PLL reference clock or sampling clock input
Output clock to user logic

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Chapter 3: Product Specification

AXI4-Stream Related Ports for RF-ADCs

Table 8: AXI4-Stream Related Ports for RF-ADCs

Port Name1

I/O

Clock

Description

mX_axis_aclk

N/A

Clock input for RF-ADC data output

mX_axis_aresetn

N/A

Synchronous reset for the mX_axis_aclk domain.

This should be held low until mX_axis_aclk is stable.

mXY_axis_tdata[M:0]

Out

mX_axis_aclk AXI4-Stream data output

mXY_axis_tvalid

Out

mX_axis_aclk AXI4-Stream valid

mXY_axis_tready

mX_axis_aclk AXI4-Stream ready

Quad RF-ADC Tile

vinXZ_p vinXZ_n

N/A

Analog input

N/A

Analog input

Dual RF-ADC

vinX_ZZ_p

N/A

Analog input

Tile

vinX_ZZ_n

N/A

Analog input

Notes:
1. X refers to the location of the tile in the converter column. Y refers to the location of the DDC block in the tile (0 to 3). In Quad RF-ADC tile devices, Z refers to the location of the RF-ADC in the tile (0 to 3). In Dual RF-ADC tile devices, ZZ is either 01 (the lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile). M is the number of samples per AXI4Stream word * 16 for converter XY.

Real-Time Signal Interface Ports for Quad RF-ADCs

Table 9: Real-Time Signal Interface Ports for Quad RF-ADCs

Port Name1,2

I/O

Clock

Description

adcXY_pl_event

RF-ADC PL event

clk_adcX

Assert to update RF-ADC settings from the PL

adcXZ_over_range

Over range output. A High on this output indicates

Out

Async

that the signal exceeds the full-scale input of the

RF-ADC.

adcXZ_over_threshold1

Over threshold1 output

Out

clk_adcX

Signal amplitude level is above programmable

threshold 1

adcXZ_over_threshold2

Over threshold2 output

Out

clk_adcX

Signal amplitude level is above programmable

threshold 2

adcXZ_over_voltage

Over voltage output

Out

Async

An Over Voltage condition occurs when a signal far

exceeds the normal operating input-range.

Related Information RF-ADC Threshold and Over Range Settings

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Chapter 3: Product Specification

Real-Time Signal Interface Ports for Dual RF-ADCs

Table 10: Real-Time Signal Interface Ports for Dual RF-ADCs

Port Name1,2

I/O

Clock

Description

adcXY_pl_event

clk_adcX

RF-ADC PL event

Assert to update RF-ADC settings from the PL

adcX_ZZ_over_range

Over range output. A High on this output indicates

Out

Async

that the signal exceeds the full-scale input of the

RF-ADC.

adcX_ZZ_over_threshold1

Over threshold1 output

Out

clk_adcX

Signal amplitude level is above programmable

threshold 1

adcX_ZZ_over_threshold2

Over threshold2 output

Out

clk_adcX

Signal amplitude level is above programmable

threshold 2

adcX_ZZ_over_voltage

Over voltage output

Out

Async

An Over Voltage condition occurs when a signal far

exceeds the normal operating input-range.

Notes:
1. X refers to the location of the tile in the converter column. Y refers to the location of the DDC block in the tile (0 to 3). ZZ is either 01 (the lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile)
2. See RF-ADC Threshold and Over Range Settings for details on the real-time signals.

Related Information RF-ADC Threshold and Over Range Settings

Real-Time NCO Signal Interface Ports for Quad RFADCs

Table 11: Real-Time NCO Signal Interface Ports for Quad RF-ADCs

Port Name1
adcXY_nco_freq[47:0] adcXY_nco_phase[17:0] adcXY_nco_phase_rst

I/O

Clock

Description

Requested NCO frequency setting. This is a 48-bit

s_axi_aclk

signed input representing the NCO frequency. The value ranges from -Fs/2 to Fs/2, where Fs is the

sampling rate

Requested NCO phase setting. This is a 18-bit

s_axi_aclk signed number representing the NCO phase. The

value ranges from -180 to 180 degrees

s_axi_aclk

NCO phase reset. Used to align the phases across the converter

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Chapter 3: Product Specification

Table 11: Real-Time NCO Signal Interface Ports for Quad RF-ADCs (cont'd)

Port Name1

I/O

Clock

Description

adcXY_update_enable[5:0]

Enable register writes

� Bit 5: Enable write to phase reset

� Bit 4: Enable write to NCO phase bits 17:16

s_axi_aclk

� Bit 3: Enable write to NCO phase bits 15:0

� Bit 2: Enable write to NCO frequency bits 47:32

� Bit 1: Enable write to NCO frequency bits 31:16

� Bit 0: Enable write to NCO frequency bits 15:0

adcX_update_request

s_axi_aclk

Asserted High to request an update of the NCO settings

adcX_update_busy

Out

s_axi_aclk

Update busy register. High when the NCO update is in progress

Notes: 1. X refers to the location of the tile in the converter column. Y refers to the location of the DDC block in the tile (0 to 3).

Real-Time NCO Signal Interface Ports for Dual RFADCs

Table 12: Real-Time NCO Signal Interface Ports for Dual RF-ADCs

Port Name1

I/O

Clock

Description

adcX_ZZ_nco_freq[47:0]

Requested NCO frequency setting. This is a 48-bit

s_axi_aclk

signed input representing the NCO frequency. The value ranges from -Fs/2 to Fs/2, where Fs is the

sampling rate.

adcX_ZZ_nco_phase[17:0]

Requested NCO phase setting. This is a 18-bit

s_axi_aclk signed number representing the NCO phase. The

value ranges from -180 to 180 degrees.

adcX_ZZ_nco_phase_rst

s_axi_aclk

NCO phase reset. Used to align the phases across the converter.

adcX_ZZ_update_enable[5:0]

Enable register writes

� Bit 5: Enable write to phase reset

� Bit 4: Enable write to NCO phase bits 17:16

s_axi_aclk

� Bit 3: Enable write to NCO phase bits 15:0

� Bit 2: Enable write to NCO frequency bits 47:32

� Bit 1: Enable write to NCO frequency bits 31:16

� Bit 0: Enable write to NCO frequency bits 15:0

adcX_update_req

s_axi_aclk

Asserted High to request an update of the NCO settings.

adcX_nco_update_busy

Out

s_axi_aclk

Update busy register. High when the NCO update is in progress.

Notes:
1. X refers to the location of the tile in the converter column. ZZ is either 01 (the lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile)

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Chapter 3: Product Specification

Calibration Freeze Ports for Quad RF-ADC Tiles

Table 13: Calibration Freeze Ports for Quad RF-ADC Tiles

Port Name1

I/O

Clock

Description

adcXY_int_cal_freeze

Signal from the PL to indicate that IP should freeze

s_axi_aclk the calibration. This is typically asserted when the

RF-ADC output is below a certain threshold.

adcXY_cal_frozen

Out

s_axi_aclk Asserted when the calibration is frozen.

Notes: 1. X refers to the location of the tile in the converter column. Y refers to the converter location in the tile (0 to 3).

Calibration Freeze Ports for Dual RF-ADC Tiles

Table 14: Calibration Freeze Ports for Dual RF-ADC Tiles

Port Name1

I/O

Clock

Description

adcX_ZZ_int_cal_freeze

Signal from the PL to indicate that IP should freeze

s_axi_aclk the calibration. This is typically asserted when the

RF-ADC output is below a certain threshold.

adcX_ZZ_cal_frozen

Out

s_axi_aclk Asserted when the calibration is frozen.

Notes:
1. X refers to the location of the tile in the converter column. ZZ is either 01 (the lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).

Register Space
The address map, shown in the following table, is split on a per-tile basis. All banks are 16 KB. The first bank contains the functions common to all tiles. Each tile has a bank for control and status.

Table 15: Address Space
AXI4-Lite Address Range ADDR[17:0]
0x00000 - 0x03FFF 0x04000 - 0x07FFF 0x08000 - 0x0BFFF 0x0C000 - 0x0FFFF 0x10000 - 0x13FFF 0x14000 - 0x17FFF 0x18000 - 0x1BFFF 0x1C000 - 0x1FFFF

Function
IP Common Control and Status RF-DAC Tile 0 registers (Tile <n> Registers) RF-DAC Tile 1 registers (Tile <n> Registers) RF-DAC Tile 2 registers (Tile <n> Registers) RF-DAC Tile 3 registers (Tile <n> Registers) RF-ADC Tile 0 registers (Tile <n> Registers) RF-ADC Tile 1 registers (Tile <n> Registers) RF-ADC Tile 2 registers (Tile <n> Registers)

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Chapter 3: Product Specification

Table 15: Address Space (cont'd)
AXI4-Lite Address Range ADDR[17:0]
0x20000 - 0x23FFF 0x24000 - 0x3FFFF

Function
RF-ADC Tile 3 registers (Tile <n> Registers) Reserved

IP Common Control and Status

Table 16: IP Common Control and Status
Address Range ADDR[13:0]
0x0000 0x0004 0x0100 0x0104

Function
IP Versioning Information Master Reset Register Common Interrupt Status Register Common Interrupt Enable Register

IP Version Information (0x0000)

Table 17: IP Version Information (0x0000)

Bit
31:24 23:16 15:8
7:0

Default Value
02 00 00 00

Access Type
RO

Major Minor Revision Reserved

Description

Master Reset Register (0x0004)

Table 18: Master Reset Register (0x0004)

Bit

Default Value

Access Type

Description

31:1

Reserved

Reset All Tiles. Write 1 to this bit to reset all logic in the core and restart the power-on sequence of all converters in the core.

Each converter is configured as per the settings chosen during core generation. The

R/W Auto AXI4-Lite registers are unaffected by this reset with the exception of bits 15:8 in the

Clear

Restart State Register for each tile which is set to 0 automatically. The end state (bits

7:0) is not affected by this reset so the power-up sequence for each tile starts from

state 0 and runs to the value programmed in bits 7:0 of the Restart State register for

each tile (the default end state is 0x0F).

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Chapter 3: Product Specification

Related Information Restart State Register (0x0008) XRFdc_Reset

Common Interrupt Status Register (0x0100)

Table 19: Common Interrupt Status Register (0x0100)

Bit

Default Value

Access Type

RO, Clear on Read

AXI timeout interrupt

30:8

Reserved (read 0)

RF-ADC Tile 3 interrupt

RF-ADC Tile 2 interrupt

RF-ADC Tile 1 interrupt

RF-ADC Tile 0 interrupt

RF-DAC Tile 3 interrupt

RF-DAC Tile 2 interrupt

RF-DAC Tile 1 interrupt

RF-DAC Tile 0 interrupt

Description

Related Information Interrupt Handling

Common Interrupt Enable Register (0x0104)

Table 20: Common Interrupt Enable Register (0x0104)

Bit

Default Value

30:8

Access Type
R/W

AXI timeout interrupt enable Reserved RF-ADC Tile 3 interrupt enable RF-ADC Tile 2 interrupt enable RF-ADC Tile 1 interrupt enable RF-ADC Tile 0 interrupt enable RF-DAC Tile 3 interrupt enable RF-DAC Tile 2 interrupt enable RF-DAC Tile 1 interrupt enable RF-DAC Tile 0 interrupt enable

Description

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Chapter 3: Product Specification

Related Information Interrupt Handling XRFdc_IntrEnable

Tile <n> Registers
Do not attempt to write to any tile specific registers while the power-on state machine is operating. To ensure the power-on state machine is not running prior to any register access, poll the Restart Power-On State Machine register (for tile <n>) and wait for it to read all zeros.

Table 21: Tile <n> Registers

ADDR[12:0]

Function

0x0000

Reserved

0x0004

Restart Power-On State Machine Register

0x0008

Restart State Register

0x000C

Current State Register

0x0010 - 0x0034

Reserved

0x0038

Reset Count Register

0x003C - 0x00FC

Reserved

0x0100

Post-Implementation Simulation Speedup Register

0x0104 - 0x01FC

Reserved

0x0200

Interrupt Status Register

0x0204

Interrupt Enable Register

0x0208

Converter 0 Interrupt Register

0x020C

Converter 0 Interrupt Enable Register

0x0210

Converter 1 Interrupt Register

0x0214 0x0218 0x021C 0x0220 0x0224

Converter 1 Interrupt Enable Register Converter 2 Interrupt Register1 Converter 2 Interrupt Enable Register1 Converter 3 Interrupt Register1 Converter 3 Interrupt Enable Register1

0x0228

RF-DAC/RF-ADC Tile <n> Common Status Register

0x022C

Reserved

0x0230

RF-DAC/RF-ADC Tile <n> Disable Register

0x0234-0x3FFF

Reserved

Notes: 1. Converter 2 and 3 registers are not applicable for Dual RF-ADC tiles.

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Chapter 3: Product Specification

Restart Power-On State Machine Register (0x0004)

Table 22: Restart Power-On State Machine Register (0x0004)

Bit

Default Value

Access Type

Description

31:1

Reserved

R/W Auto Write 1 to this bit to start the power-on state machine. The state machine starts and

Clear stops at the stages programmed in the Restart State Register. This bit stays High until

the state machine has reached the chosen end state.

Related Information Restart State Register (0x0008)

Restart State Register (0x0008)

Table 23: Restart State Register (0x0008)

Bit
31:16 15:8

Default Value
-
00

Access Type
-
R/W

7:0

R/W

Start End

Description
Reserved
Enabled tiles only. Start and End states for the power-on sequence. The default start state of 0x00 and end state of 0x0F should be used to enable the converters and a start state of 0x00 and an end state of 0x03 should be used to stop the converters. When a 1 is written to the bit in the Restart Power-on State Machine Register for tile<n>, the power-on state machine is started from the start state and runs to the end of the end state specified in this register. See Power-up Sequence for details about restarting and power-down.

Related Information Power-up Sequence

Current State Register (0x000C)

Table 24: Current State Register (0x000C)

Bit

Default Value

31:8

7:0

Access Type
-
RO

Description
Reserved Current state of Power-on state machine. See Power-on Sequence Steps.

Related Information Power-on Sequence Steps XRFdc_GetIPStatus

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Chapter 3: Product Specification

Reset Count Register (0x0038)

Table 25: Reset Count Register (0x0038)

Bit

Default Value

Access Type

Description

31:8

Reserved

7:0

RO Clear on Reset

If the IP automatically restarts due to instability in the supply power, a loss of clock integrity or a loss of PLL lock, the reset counter is incremented. The counter saturates at 255 resets.

Post-Implementation Simulation Speedup Register (0x0100)

Table 26: Post-Implementation Simulation Speedup Register (0x0100)

Bit

Default Value

31:1

Access Type
-
RW

Description
Reserved Simulation speed-up for post-implementation simulations. Set High to speed up postimplementation simulations. This register must not be set in hardware.

Interrupt Status Register (0x0200)

Table 27: Interrupt Status Register (0x0200)

Bit

Default Value

Access Type

Description

31:5

Reserved (read back 0)

RO Clear On Common interrupt bit. Asserted when the power-on state machine has

Read

encountered an error during the start up process

Converter 3 interrupt bit

Converter 2 interrupt bit RO
Converter 1 interrupt bit

Converter 0 interrupt bit

Related Information Interrupt Handling XRFdc_IntrClr XRFdc_GetIntrStatus

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Chapter 3: Product Specification

Interrupt Enable Register (0x0204)

Table 28: Interrupt Enable Register (0x0204)

Bit

Default Value

31:5

Access Type
-
R/W

Reserved (read back 0) Common interrupt enable bit Converter 3 interrupt enable bit Converter 2 interrupt enable bit Converter 1 interrupt enable bit Converter 0 interrupt enable bit

Description

Converter 0 Interrupt Register (0x0208)

Table 29: Converter 0 Interrupt Register (0x0208)

Bit

Default Value

Access Type

Description

31:16

Reserved Enable Read back 0

RO Clear on Flags a FIFO overflow in converter when High

Reset

Flags a datapath overflow in converter when High1

13:4

Reserved (read back 0)

RO Clear on Reset

Flags an Over Range interrupt in converter2

RO Clear on Read

Flags an Over Voltage interrupt in converter2

1:0

N/A

Reserved (read back 0)

Notes:
1. A datapath overflow indicates one of the following conditions has occurred:
� Interpolation filter overflow in the RF-DAC � Decimation filter overflow in the RF-ADC � Overflow in the Quadrature Modulation Correction block � Overflow in the RF-DAC Inverse Sinc filter
2. RF-ADC only.

Converter 0 Interrupt Enable Register (0x020C)

Table 30: Converter 0 Interrupt Enable Register (0x020C)

Bit
31:16

Default Value
-

Access Type
-

Reserved (read back 0)

Description

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Chapter 3: Product Specification

Table 30: Converter 0 Interrupt Enable Register (0x020C) (cont'd)

Bit

Default Value

13:4

1:0

Notes: 1. RF-ADC only.

Access Type
R/W -
R/W -

Description
Enable FIFO overflow interrupt in converter Enable datapath overflow interrupt in converter Reserved (read back 0) Enable Over Range interrupt in converter1 Enable Over Voltage interrupt in converter1 Reserved (read back 0)

Converter 1 Interrupt Register (0x0210)

Table 31: Converter 1 Interrupt Register (0x0210)

Bit
31:16 15 14 13:4

Default Value
0 0 -

1:0

Notes: 1. RF-ADC only.

Access Type

Description

Reserved (read back 0)

RO Clear on Flags a FIFO overflow in converter when High

Reset

Flags a datapath overflow in converter when High

Reserved (read back 0)

RO Clear on Reset

Flags an Over Range interrupt in converter1

RO Clear on Read

Flags an Over Voltage interrupt in converter1

Reserved (read back 0)

Converter 1 Interrupt Enable Register (0x0214)

Table 32: Converter 1 Interrupt Enable Register (0x0214)

Bit
31:16 15 14 13:4 3 2

Default Value
1 1 1 1

Access Type
-
R/W
-
R/W

Description
Reserved (read back 0) Enable FIFO overflow interrupt in converter Enable datapath overflow interrupt in converter Reserved (read back 0) Enable Over Range interrupt in converter1 Enable Over Voltage interrupt in converter1

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Chapter 3: Product Specification

Table 32: Converter 1 Interrupt Enable Register (0x0214) (cont'd)

Bit

Default Value

1:0

Notes: 1. RF-ADC only.

Access Type
-

Reserved (read back 0)

Description

Converter 2 Interrupt Register (0x0218)

Table 33: Converter 2 Interrupt Register (0x0218)

Bit
31:16 15 14 13:4

Default Value
0 0 -

1:0

Notes: 1. RF-ADC only.

Access Type

Description

Reserved (read back 0)

RO Clear on Flags a FIFO overflow in converter when High

Reset

Flags a datapath overflow in converter when High

Reserved (read back 0)

RO Clear on Reset

Flags an Over Range interrupt in converter1

RO Clear on Read

Flags an Over Voltage interrupt in converter1

Reserved (read back 0)

Converter 2 Interrupt Enable Register (0x021C)

Table 34: Converter 2 Interrupt Enable Register (0x021C)

Bit

Default Value

31:16

13:4

1:0

Notes: 1. RF-ADC only.

Access Type
-
R/W
-
R/W
-

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Chapter 3: Product Specification

Converter 3 Interrupt Register (0x0220)

Table 35: Converter 3 Interrupt Register (0x0220)

Bit
31:16 15 14 13:4

Default Value
0 0 -

1:0

Notes: 1. RF-ADC only.

Access Type

Description

Reserved (read back 0)

RO Clear on Flags a FIFO overflow in converter when High

Reset

Flags a datapath overflow in converter when High

Reserved (read back 0)

RO Clear on Reset

Flags an Over Range interrupt in converter1

RO Clear on Read

Flags an Over Voltage interrupt in converter1

Reserved (read back 0)

Converter 3 Interrupt Enable Register (0x0224)

Table 36: Converter 3 Interrupt Enable Register (0x0224)

Bit

Default Value

31:16

13:4

1:0

Notes: 1. RF-ADC only.

Access Type
-
R/W
-
R/W
-

Description
Reserved (read back 0) Enable FIFO overflow interrupt in Converter Enable datapath overflow interrupt in Converter Reserved (read back 0) Enable Over Range interrupt in converter1 Enable Over Voltage interrupt in converter1 Reserved (read back 0)

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Chapter 3: Product Specification

RF-DAC/RF-ADC Tile <n> Common Status Register (0x0228)

Table 37: RF-DAC/RF-ADC Tile <n> Common Status Register (0x0228)

Bit

Default Value

Access Type

Description1,2

31:4

Reserved

PLL locked. Asserted when the tile PLL has achieved lock.

Power-up state. Asserted when the tile is in operation.

Supplies up. Asserted when the external supplies to the tile are stable.

Clock present. Asserted when the reference clock for the tile is present.

Notes: 1. <n> is 0 to 3. 2. See Register Space for register <n> address.

Related Information Register Space XRFdc_GetIPStatus XRFdc_GetBlockStatus

RF-DAC/RF-ADC Tile <n> FIFO Disable Register (0x0230)

Table 38: RF-DAC/RF-ADC Tile <n> FIFO Disable Register (0x0230)

Bit

Default Value

Access Type

Description1,2

31:1

Reserved

R/W

Disable the interface FIFO for converter <n>

Notes: 1. <n> is 0 to 3. 2. See Register Space for register <n> address.

Related Information Register Space

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Chapter 4: Designing with the Core
Chapter 4
Designing with the Core
The RF Data Converter solution consists of the Zynq� UltraScale+TM RFSoC RF Data Converter IP core configuration in the Vivado� Integrated Design Environment (IDE) and the RF data converter (RFdc) driver Application Programming Interface (API).
IP Core Configuration in the Vivado Design Suite
The Zynq� UltraScale+TM RFSoC RF Data Converter IP core configuration screen in the Vivado� IDE sets up the physical configuration of the RF-ADCs and RF-DACs in the Zynq UltraScale+ RFSoC. The configuration screen is used to enable tiles, configure decimation, interpolation, and mixing, set up converter sample rates, the Programmable Logic (PL) interface word widths and data types, and enables the optional interface ports. The IP core also handles the configuration and power-up of the data converters. This ensures that the settings specified in the Vivado IDE are applied to the RF-ADCs and RF-DACs immediately after the PL configuration completes.
Software Driver
The RFdc driver API provides runtime interaction and monitoring of the data converters. This includes responding to interrupts, changing some settings, such as mixer frequency, and also interacting with the IP core to power up or down RF-ADC or RF-DAC tiles. The RFdc driver API is available as a bare-metal or Linux driver validated on both MicroBlazeTM and Zynq� UltraScale+TM RFSoC Processing System (PS) APU or RPU processors. Your application should always use these driver APIs to read status from or change the configuration of the IP core on the fly. Accessing internal registers directly is not allowed with the exception of some status/ interrupt registers which have been identified in this document.
Related Information Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver

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Chapter 4: Designing with the Core

RF-ADC
Every RF-ADC in a tile has its own dedicated high-performance input buffer and includes features optimized for direct RF applications including quadrature modulator correction (QMC), full complex mixers, and decimation filters.
Figure 8: RF-ADC Functionality Block Diagram (Simplified)

VIN0_N VIN0_P

ADC

Gearbox FIFO
Crossbar Threshold
Detect

QMC Gain/Phase

I and Q Mixer

I Decimation Q Decimation

STATUS_ADC0[15:0] DATA_ADC0[127:0] CONTROL_ADC0[15:0]

X18254-091117

Certain functions can only be executed when the RF-ADCs in a tile are paired. The evennumbered RF-ADCs are used for I datapaths and the odd-numbered RF-ADCs are used for Q datapaths. All of the available built-in functionality of a tile and each of the RF-ADCs within a tile are configured with the supporting RFdc driver API and/or core configuration screen in the Vivado� IDE.

Related Information Quadrature Modulator Correction

RF-ADC Analog Input
Every RF-ADC in a tile has its own differential analog input buffer. This input is optimized for performance and requires source impedance matching for best dynamic performance.

Figure 9: RF-ADC Analog Input

VCCINT_AMS (0.85) ADC_AVCC (0.925V) ADC_AVCCAUX (1.8V)

Vin

VP-VN = 1V pk-pk

Digital
die package
GND

ADC Pair

BUF

50 50

Z0=100

VCM

1.2V

VCM

ADC_GND

250 mV
X19533-082819

Note: In the figure above the waveform diagram is an oscilloscope representation with a DC offset.

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Chapter 4: Designing with the Core
There are several ways to drive an RF-ADC in a tile. Driving the RF-ADC can be either active or passive. However, optimum performance is achieved by driving the analog input differentially. Using a differential amplifier, AC- or DC-coupled, to drive the RF-ADC provides a flexible interface with excellent performance. For AC-coupled mode, the input signals should be ACcoupled in using capacitors. For DC-coupled mode, the output VCM buffer is enabled as shown in the figure above. This buffer is only enabled when DC-coupled mode is selected. This VCM buffer allows the user to align the common mode of the external active driving circuit with the ADC internal common requirements. Two VCM buffers (VCM01, VCM23) are available for each tile.
For all applications where the signal-to-noise ratio (SNR) is a key parameter, Xilinx recommends using a differential transformer or balun configuration. See the UltraScale Architecture PCB Design User Guide (UG583) for details on how to design the input networks and PCB.
RF-ADC Digital Datapath
An RF-ADC component in a tile has integrated DSP features which can be enabled by the user to pre-process the sampled data from the RF-ADC device before it is passed to the PL. The different DSP function blocks are as follows:
� Detection functionality: Contains a dual level programmable threshold that provides two flags to the internal interconnect logic, and is asserted when the absolute output value of the RFADC is greater or smaller than the programmed threshold values.
� Compensation functionality: Contains a quadrature modulator correction (QMC) block with a coarse delay adjustment block
� Digital Down Converter (DDC): consists of
� Mixer--coarse (quarter and half rate) and fine (NCO with 48-bit frequency resolution)
� Signal decimation functionality--decimation by 1 (bypass), 2, 4, or 8 is supported
Single, multiple, or all DSP functions can be used or bypassed. Some functions, such as the QMC, require activation of the same function in both I and Q RF-ADCs. Even numbered RF-ADCs are always used for I datapaths, and odd numbered RF-ADCs are used for Q datapaths. You can implement, configure, or modify the functionality of one or multiple functions using the IP core. The following figure shows the available functions in an RF-ADC and the functions are described in this section.

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Figure 10: Signal Treatment of the RF-ADC Peripherals

Gearbox FIFO

ADC_1

Threshold Detect

HQMSACDC Gain/Phase

Crossbar

I and Q Mixer

I Decimation Q Decimation

Gearbox FIFO

ADC_0

Threshold Detect

HQMSACDC Gain/Phase

Crossbar

I and Q Mixer

I Decimation Q Decimation

X18259-091117
RF-ADC Threshold and Over Range Settings
As with any ADC, the input analog signals must be kept within the full-scale range of the ADC, and at the correct input levels. Any signals that do not comply with these conditions result in data loss. To help prevent this, the threshold-detector feature can be used to adjust signal chain gains to keep the signal within the ideal full-scale ranges. However, in the event that a signal does exceed the full-scale range, each RF-ADC channel has built-in detection and protection for this with the Over Range and Over Voltage features.
The Over Voltage and Over Range signals are provided to both the interrupt feature on the IP core, as well as to the RF-ADC real-time signals bus on the IP core for direct access to the PL design.
Over Range
An Over Range condition occurs when a signal exceeds the full-scale input of the RF-ADC. When this condition is detected, the converted data is saturated (clipped) to limit the data corruption, and the signal is flagged to the user by both the interrupt mechanism, and by asserting the Over Range real-time output signal. Because Over Range events can be as short as one RF-ADC sample, the output signal is sticky. To clear the Over Range output and the associated interrupt, the API interrupt handling mechanism is used.
Related Information Interrupt Hierarchy Real-Time Signal Interface Ports for Quad RF-ADCs Real-Time Signal Interface Ports for Dual RF-ADCs

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Over Voltage
An Over Voltage condition occurs when a signal far exceeds the normal operating input range. Because an excessive voltage on the inputs can damage the device, automatic protection mechanisms are provided.
An Over Voltage event results in the automatic shutdown of the input buffer to protect it. The Over Voltage circuit monitors each of the signals of the differential inputs independently, and flags the condition when any individual input signal exceeds the maximum input voltage or is less than the minimum input voltage of the RF-ADC input buffer.
The Over Voltage feature offers protection for signals in the range defined in the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926). Signals exceeding this maximum are not permitted, and care must be taken externally to ensure that such voltages are not presented to the RF-ADC inputs.
When an Over Voltage condition is detected the signal is flagged to the user by both the interrupt mechanism, and by asserting the Over Voltage real-time output signal. The Over Voltage real-time output is asserted and deasserted asynchronously, and provides immediate notification of the event. As a result, the Over Voltage output self-clears when the Over Voltage condition is no longer present. The associated interrupt is sticky, so requires clearing by the API interrupt handling routines.
After an Over Voltage event the input buffer automatically re-enables and the RF-ADC resumes operation as before. However, an over voltage condition should be considered as grounds to stop the traffic and restart the receiver chain. In the event of an Over Voltage condition, the buffer shuts down and the resulting RF-ADC output digital codes are mostly just noise. As a result, the threshold information become irrelevant and this can affect an AGC implementation. Therefore it is important that an AGC implementation takes account of the Over Voltage signal and sets up the two threshold detectors accordingly.
The following figure shows the Threshold, Over Range, and Over Voltage levels and the response of these with an increasing input analog signal.

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Figure 11: Threshold, Over Range, and Over Voltage Levels

Max. voltage rating

2.10V

Nominal supply voltage

1.80V

VCM+0.45V

VCM+0.25V

VCM VCM-0.25V

VCM-0.45V

Over Voltage
Over Range
Normal Range
Over Range

Not supported
Fully reliable range

Min. voltage rating

0.00V -0.30V

Over Range Flag

Over Voltage Flag
Over Range Flag interrupt clear

Over Voltage

Not supported

X20472-050919

Related Information Interrupt Hierarchy Real-Time Signal Interface Ports for Quad RF-ADCs Real-Time Signal Interface Ports for Dual RF-ADCs

Threshold Settings
Instead of waiting for a signal to propagate through the signal processing blocks, the threshold feature provides an early indication of the incoming signal level. This early indication of the signal level can be used by the automatic gain control (AGC) implemented in the PL. Threshold levels used to indicate the input signal level are set using the RFdc driver API.
Threshold monitoring occurs when the RF-ADC sampled data enters the datapath. This data is compared to a user-defined threshold. A threshold status signal is sent to the outputs on the IP core, to indicate that a user-defined threshold has been exceeded. There are two real-time over threshold output signals for each RF-ADC. The modes of the threshold monitoring circuit are listed in the following table.

Table 39: Threshold Signaling Modes

Mode
Off Sticky over

Description
The threshold circuit is disabled and the status outputs are Low. The threshold status signal is High when the data from the RF-ADC exceeds the programmed upper threshold value. The status is kept until a clear action is sent.1

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Table 39: Threshold Signaling Modes (cont'd)

Mode

Description

Sticky under

The threshold status signal is High when the data from the RF-ADC remains below the programmed lower threshold value for the duration of a user-specified time or delay. The status is kept until a clear action is sent1. This delay value for the lower threshold is defined by a 32-bit counter. The counter is set using the RFdc driver API. Using this mechanism prevents short duration excursions triggering a threshold event.

Hysteresis

The status output is set when the programmed upper threshold value is exceeded, and is cleared when the signal remains below the lower threshold value for the duration of a user-specified delay value. This delay value for the lower threshold is defined by a 32-bit counter. The counter is set using the RFdc driver API. The delay adds hysteresis to the threshold detection to prevent short duration excursions triggering a threshold event.

Notes: 1. To clear see Clearing Threshold Flags.

Threshold levels are set as 14-bit unsigned values, with any value from 0 to 16383 allowed. The maximum value, 16383 represents the absolute value of the full-scale input of the RF-ADC. The 32-bit programmable delay counts RF-ADC samples. To relate this count to a specific time, the following equation can be used:
Counter Value = (delay(ms) x ADCSampleRate (GSPS) x 106) / Interleaving Factor
where the Interleaving Factor is 4 for the Quad RF-ADC tile and is 8 for the Dual RF-ADC tile.
The delay can also be expressed in samples instead of ms as below:
Counter Value = delay (RF-ADC samples) / Interleaving Factor = delay (sub-ADC samples)

Related Information Real-Time Signal Interface Ports for Quad RF-ADCs Real-Time Signal Interface Ports for Dual RF-ADCs

Clearing Threshold Flags
After the threshold values assert in the Sticky Over and Sticky Under modes, the flags can be cleared in two ways; by issuing the clear command directly, or by using the AutoClear feature. The AutoClear mode clears the threshold whenever the QMC Gain value associated with that RF-ADC is updated.

Threshold Operation Example
The following figure illustrates the threshold unit operation. The diagram shows three thresholds, a, b, and c, each configured in a different threshold mode. In hardware all threshold units have independent threshold levels and delay values. In this example the threshold levels are indicated by the dashed horizontal lines, and all units use the same levels for the purpose of illustration. The delay value is set to 5 (the delay value has no effects for Sticky Over mode), and the sticky thresholds have been set up to be cleared by different clear modes. The behavior is described in the following sections.

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Note: In the following figure, samples are counted by one sub-ADC, but not RF-ADC. Figure 12: Threshold Operation

X20238-012219
Threshold-A, Sticky Over Mode The flag asserts when the first sample exceeds the upper threshold value. In this example, the flag is cleared using a call to the XRFdc_ThresholdStickyClear API function.
Threshold-B, Sticky Under Mode The flag asserts when the samples have been continuously below the lower threshold for the delay number of samples (6, in the example). In this example, the flag is cleared through an update of the QMC Gain value, which is issued using a call to the XRFdc_SetQMCSettings API function, followed by an Update event, which applies the QMC gain update.
Threshold-C, Hysteresis Mode The flag asserts when the first sample exceeds the upper threshold value. The flag is cleared when the samples have been continuously below the lower threshold for the delay number of samples.
Related Information Dynamic Update Events

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Threshold RFdc Driver API Commands The threshold levels and delay values are configured using the RFdc driver API.
// Initial Setup XRFdc_Threshold_Settings Threshold_Settings; Threshold_Settings.UpdateThreshold = XRFDC_UPDATE_THRESHOLD_BOTH; // Setup values for threshold 0 and 1 Threshold_Settings.ThresholdMode[0] = XRFDC_TRSHD_STICKY_UNDER; // Set threshold0 mode to Sticky Under Threshold_Settings.ThresholdUnderVal[0] = 1000; // Measured in 14-bit unsigned LSBs Threshold_Settings.ThresholdAvgVal[0] = 10; // Data must be below lower threshold for 10*8 4 GSPS RF-ADC samples // Write threshold values to the selected Tile / RF-ADC XRFdc_SetThresholdSettings(ptr, Tile, Block, &Threshold_Settings); The threshold clear operation is shown in the following code examples. � Clear the thresholds by writing directly using the RFdc driver API: // Initial Setup XRFdc_SetThresholdClrMode(ptr, Tile, Block, Threshold#, XRFDC_THRESHOLD_CLRMD_MANUAL_CLR); .... // During application run-time (after a threshold asserts) XRFdc_ThresholdStickyClear(ptr, Tile, Block, Threshold#); � Clear the thresholds using the AutoClear function; the threshold clears with the QMC Gain
Update: // Initial Setup XRFdc_QMC_Settings QMC_Settings; XRFdc_SetThresholdClrMode(ptr, Tile, Block, Threshold#, XRFDC_THRESHOLD_CLRMD_AUTO_CLR); .... // During application run-time (after a threshold asserts - update t) QMC_Settings.GainCorrectionFactor = new_gain_value; XRFdc_SetQMCSettings(ptr, XRFDC_ADC_TILE, Tile, Block, &QMC_Settings); ... // QMC Gain applied by an Update Event

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Related Information XRFdc_SetThresholdSettings XRFdc_SetThresholdClrMode XRFdc_ThresholdStickyClear XRFdc_SetQMCSettings
Threshold Applications A common use for threshold detectors is in Automatic Gain Control (AGC) applications.
Related Information Automatic Gain Control Systems
Over Range Settings There are two types of Over Range signals available as status outputs to the programmable logic, Over Voltage and Over Range. The IP core exposes these signals using the interrupt mechanism, so any violation is immediately flagged to the user application. These are triggered when normal or expected operating levels are exceeded.
Over Voltage Signal An Over Voltage signal is detected whenever the input signal exceeds a safe input range from the RF-ADC input buffers.
Over Range Signal � When the input signal exceeds the � digital full-scale range of an RF-ADC, an Over Range
signal is detected. � An Over Range signal is measured at the raw digital output of the RF-ADC.
RF-ADC Mixer with Numerical Controlled Oscillator
The mixer function has three modes: bypass (no mixing), coarse mixing or fine mixing. Fine mixing automatically enables the NCO which is used to generate the carrier frequency. The mixer supports full quadrature mixing, with both real to I/Q and I/Q to I/Q modes supported.

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Figure 13: RF-ADC Mixer with NCO DSP Block

Coarse Mixer N0, Fs/4, Fs/2, or -Fs/4

IIN

IOUT

3 dB

Fine Mixer

NCO

QIN

3 dB

QOUT

X18261-032318
Coarse Mixer: � The coarse mixer allows the data to be mixed with a carrier of 0, Fs/2, Fs/4, or �Fs/4.
Note: The selection of 0 is only available using the RFdc driver API. � Mixing with a 0 carrier bypasses the mixer component. Fine Mixer: � The fine mixer allows the data to be shifted up or down in frequency by an arbitrary amount. � The frequency shift amount is obtained by programming the mixer frequency generated in the
NCO. The fine mixer also supports 18-bit phase adjustment. � The NCO phase can be synchronized within a tile using XRFdc_UpdateEvent. � The NCO phase can be synchronized across tiles using an external event signal (SYSREF or
MARKER).

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� To manage potential overflow, the fine mixer output includes 3 dBV attenuation, as shown in the figure above. This attenuation is not relevant in R2C mode, so the automatic mode selection from the API selects the correct attenuation level following the RF-ADC mixer scaling output factor (see the table below). A manual selection is also possible, allowing 0 dBV or -3 dBV.

Table 40: RF-ADC Mixer Scaling Output Factor

Tile Usage
IQ (C2C) Real (R2C)

Coarse Mixer
1 (0 dBV) 1 (0 dBV)

Auto Fine Mixer
0.707 (-3 dBV) 0.997 (~0 dBV)

The mixer settings can be configured in the core, or by using the RFdc driver API. The core is used to set the initial mixer settings (for example, mixer type and mixer mode), and the RFdc driver API is used to adjust the settings at runtime. Both the RFdc driver API and the core compute the required register settings based on the supplied sample rates and desired frequencies. A sample configuration screen is shown in the following figure. See the RF-ADC Converter Configuration section for information on the settings.

Figure 14: RF-ADC Mixer Settings Configuration

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Related Information XRFdc_UpdateEvent RF-ADC Converter Configuration
RF-ADC Mixer RFdc API Example Related RFdc driver API functions are shown in the following code. This code illustrates the use of the NCO Phase reset function. This function must be used at startup to initialize the phase of the fine mixer to a valid state. Note that the following code resets the NCOs in all tiles.
XRFdc_Mixer_Settings Mixer_Settings; for(tile=0;tile<4; tile++) {
// Make sure the mixer settings update use the Tile event for(block=0; block<2; block++) {
XRFdc_GetMixerSettings (ptr, XRFDC_ADC_TILE, tile, block, &Mixer_Settings);
Mixer_Settings.EventSource = XRFDC_EVNT_SRC_TILE; //Mixer Settings are updated
with a tile event XRFdc_SetMixerSettings (ptr, XRFDC_ADC_TILE, tile, block, &Mixer_Settings); } // Reset NCO phase of both DDCs in Tile0 (assuming both are active) XRFdc_ResetNCOPhase(ptr, XRFDC_ADC_TILE, tile, 0); // DDC Block0 XRFdc_ResetNCOPhase(ptr, XRFDC_ADC_TILE, tile, 1); // DDC Block1 XRFds_UpdateEvent(ptr, XRFDC_ADC_TILE, tile, 1, XRFDC_EVENT_MIXER); // Generate a Tile Event }
Related Information XRFdc_GetMixerSettings XRFdc_SetMixerSettings XRFdc_ResetNCOPhase
NCO Setting Example The NCO is in the digital domain and its effective frequency range is always from -Fs/2 to Fs/2. When the RF-ADC or the RF-DAC operates at sub-sampling frequencies (Fc>Fs/2), the application must first calculate the signal location at the 1st Nyquist band and then set the effective NCO value to shift signals.
Xilinx defines the Zynq UltraScale+ RFSoC NCO frequency range from -10 GHz to 10 GHz in the API and in the IP configuration for convenience, so the application does not need to calculate the frequency in the 1st Nyquist band, to set any required NCO value in -10 GHz to 10 GHz, the API or the Vivado� Design Suite converts it to an effective NCO configuration automatically. This works for both RF-ADCs and RF-DACs.

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In the digital domain, the spectrum shows inverse in adjacent Nyquist bands, set NCO frequency as positive or negative to pick up particular spectrum base on applications. For example, the DDC, in general, shifts the carrier from Fc to DC, so with this absolute NCO range (-10 GHz to 10 GHz), setting the NCO to -Fc always shifts the desired signal at DC; setting the NCO to Fc always shifts the inverse signal to DC, no matter which Nyquist band the signal is located in. When setting the NCO within the effective NCO range (-Fs/2 to Fs/2), to convert the carrier to DC, the NCO frequency should be positive when the signal is at even Nyquist bands, and negative when the signal is at odd Nyquist bands. The DUC works similarly to the DDC but with a reverse signal flow direction. Setting the NCO to Fc always up-converts the signal from DC to Fc, and setting the NCO to -Fc always gets an inverse signal at Fc, no matter in which Nyquist band the carrier is located. The following figure shows an example of down conversion.
Figure 15: Down Conversion Example

RF-ADC Decimation Filters
Decimation filters are required to implement the down-sampling and filtering part of the digitaldown conversion (DDC) process. The overall filter response is determined by the number of decimation stages used. The decimation chain consists of three FIR filter stages which can be combined to implement variable decimation rates. When a FIR stage is not used it is automatically powered down. The decimation filters allow for the creation of the following:
� 1x: All filter stages are bypassed
� 2x: Decimation filtering using a single stage

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� 4x: Decimation filtering using two stages
� 8x: Decimation filtering using all three available stages
Each decimation filter element has a different number of taps and the stop-band attenuation and ripple are shown in Decimation Filter Details. The decimation filter chains can operate on either I/Q data or real data. Unused filter chains are powered down.
Each of the filter stages can overflow given the step-response of a FIR filter, especially when fullscale data is on the input. To detect and protect the datapath from overflow, each filter stage and sub-phase has a signed overflow status signal and saturation at the output. When a filter stage is not used, the flag is forced zero. These flags are connected to the datapath interrupt mechanism which is described in Interrupt Handling. The multiplexer in the following figure shows the decimation level selected in the IP configuration with the corresponding selection of decimation filter blocks.
Figure 16: RF-ADC Digital Down Converter

FIR2

Data In

FIR1

FIR2

DataOut

FIR0

FIR1

FIR2

X21610-050919

Table 41: Decimation Filter Operating Modes

Mode

Description

Quad and Dual RF-ADC Tile

OFF

The entire filter is disabled/powered down (applies when RF-ADC is disabled)

The entire filter is bypassed

2x decimation, 80% Nyquist passband1

4x decimation, 80% Nyquist passband

8x decimation, 80% Nyquist passband

Notes: 1. 80% Nyquist passband is 0.4*Fs

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Related Information Interrupt Hierarchy Decimation Filter Details
Decimation Filter Use The IP core is used to set the decimation rate. This is set in the Vivado� IDE because changing the decimation rate directly affects the physical interface as the bandwidth to the PL changes. The filters that are enabled are as shown in the following figure. Enable the RF-ADC by checking the Enable ADC check box. See RF-ADC Converter Configuration for information on the settings.
Figure 17: RF-ADC Decimation Filter Configuration

Related Information RF-ADC Converter Configuration
Related API Commands The RFdc driver API can be used to get the decimation rate set in the IP core using the following code.
// Get Decimation factor for Tile0, DDC Block1 int Tile = 0; u32 Block = 1; u32 Decimation_Factor; if( XRFdc_GetDecimationFactor (ptr, Tile, Block, &DecimationFactor) == XST_SUCCESS) {
xil_printf("ADC Tile%1d,%1d Decimation Factor is: %d", Tile, Block, Decimation_Factor); }
Decimation Filter Details The decimation filter chain consists of three FIR filters: FIR2, FIR1, and FIR0, which can be enabled to give successive decimation by a factor of two per stage. The filter transfer functions are as shown in the following figures.

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Chapter 4: Designing with the Core Figure 18: FIR2 and FIR1 Frequency Response
Figure 19: FIR0 and 2x Decimation Frequency Response

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Chapter 4: Designing with the Core Figure 20: 4x Decimation and 8x Decimation Frequency Response

The filter coefficients for the decimation filters are shown in the following tables.

1st

0 -17 0 44

Half

0 1401 0 -2112 0

FIR2

Center Tap

65536

2nd

0 -17 0 44

Half

0 1401 0 -2112 0

0 -96 0 187 0 -335

565 0 -906

3145 0 -4723 0 7415 0 -13331 0 41526

0 -96 0 187 0 -335

565 0 -906

3145 0 -4723 0 7415 0 -13331 0 41526

1st Half

-12

-337

1008

-2693

10142

FIR1 Center Tap 16384

2nd Half

-12

-337

1008

-2693

10142

1st Half

-6

-254

1230

FIR0

Center Tap

2048

2nd Half

-6

-254

1230

RF-ADC Calibration Mechanism
Each of the RF-ADCs in the Zynq UltraScale+ RFSoC is built on multiple sub-RF-ADCs in an interleaving architecture. The nature of the interleaving process requires that an intricate calibration algorithm to be carried out to obtain the best dynamic range performance from the RF-ADC. Each of the RF-ADCs (Dual or Quad variant) in the RFSoC has a built-in calibration process that includes a foreground calibration (FG CAL) step and a background calibration (BG

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CAL) step. The FG CAL step gets executed during the RF-ADC power-on state machine (startup initialization) only. The BG CAL step is a process that is designed to operate optionally during the RF-ADC run-time. Both of the calibration steps for each RF-ADC is carried out in parallel and independently. The following figure shows the block diagram of one of the RF-ADCs with the internal calibration blocks for each of the N sub-RF-ADCs.
Figure 21: RF-ADC Calibration Block Diagram

Vin0_P Vin0_N

Input Buffer

Skew adjust

Sub-ADC 0

Skew adjust

Sub-ADC N

OCB1 OCB1

OCB2

GCB

Sub ADC 0 out
TSCB

Init Bypass/ Freeze

Freeze

OCB2

GCB

Sub ADC N out
TSCB

ADC0 OUTPUT N 16-bit data streams @ Fs/N samples/sec

QMC

Cross Bar

IQ Mixer

Threshold Detect

DDC

Control and Status

FIFO

DATA ADC0[127:0]

Init Bypass/ Freeze

Freeze

X21770-050919

The calibration sub-system comprises of three major blocks that are designed to estimate and correct the various imperfections and mismatches of the interleaving sub-RF-ADCs.

Time Interleaved Offset Calibration Block (OCB)
This block corrects for the DC offset of each of the sub-RF-ADCs. Any residual DC offset not corrected appears as a spur at k*Fs/N, where Fs is the composite sampling rate of the RF-ADC, N is the number of sub-RF-ADCs interleaved together, and k = 0, 1, 2, ... N. N is 8 for the Dual RFADC tile variant and N is 4 for the Quad RF-ADC tile variant. This block is further divided down to two sub-blocks called OCB1 and OCB2. OCB2 only runs during FG CAL while OCB1 runs during both FG and BG CAL. The OCB2 block cancels offsets of the sub RF-ADCs at start-up. The OCB1 block cancels sub-RF-ADC offsets continuously in the BG calibration process without affecting the input signal content at the offset locations.

Gain Calibration Block (GCB)
This block corrects for the gain difference among the interleaving sub-RF-ADCs. Any residual difference results in spurious signal at +/-fin + (k/N)*Fs, where Fs is the sample rate of the RFADC, N is the number of sub-RF-ADCs, and fin is the frequency of the input signal. The GCB requires the presence of an input signal with power greater than -40 dBFs for an accurate correction of the gain skews. Signal bins at f = k*Fs/(2N) are ignored and do not count towards the signal power. This block should be in the freeze mode whenever the input signal power drops below -40 dBFs for longer than 100 s.

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Time Skew Calibration Block (TSCB)
This block corrects for the time skews among the interleaving sub-RF-ADCs. Any residual difference can result in spurious signal at +/-fin + (k/N)*Fs, where Fs is the sample rate of the RFADC, N is the number of sub-RF-ADCs, fin is the frequency of the input signal The TSCB also relies on the presence of an input signal with input power greater than -40 dBFs to provide accurate estimate and correction of the time skews among sub RF-ADCs. This block should be in the freeze mode whenever the input signal power drops below -40 dBFs for longer than 100 s.
Foreground Calibration Process
The foreground calibration step is part of the RF-ADC startup initialization state machine sequence. This is managed and carried out by the startup IP. The purpose of the foreground calibration is to provide correction through the OCB1 and OCB2 blocks for sub-RF-ADC offsets and skews of the sampling switches. The OCB2 block is then frozen and not updated again during operation mode. During this process there should ideally be no signal energy at any of the interleaving offset locations, namely frequency = k*Fs/N. Thus the input should be muted during this process. This is typically accomplished by sequencing the receiver front end enable after the RF-ADC startup process is complete. At the end of the foreground calibration process the OCB2 block is frozen, and OCB1, Time Skew and Gain Calibration blocks are set to enable to run in the background.
Background Calibration Process
At the end of a successful startup initialization of the RF-ADC the background calibration is enabled. The purpose of the background calibration is to provide real time adjustment for the various skews and mismatches introduced by environmental changes to the sub-RF-ADCs, primarily that of temperature. The blocks that are running in the background (in real time) include OCB1, GCB, and TSCB. As noted, OCB1 runs in the background to adjust for residual sub-RFADC offset levels introduced by temperature change without affecting the input signal content. Signal content present at k*Fs/N is unaffected by this block.
The gain calibration block (GCB) and the time skew calibration block (TSCB) provide correction to the sub-RF-ADC gain and time skews respectively. Both blocks use and depend on the input signal to estimate and correct for the skews. When the input signal drops below -40 dBFs it is no longer effective to use the signal for the computation. Thus the optimal usage of these two blocks is to dynamically control the coefficient update (freeze and resume) of these two blocks. The control of these two blocks for freezing and resuming is implemented using the Vivado� IP port RF-ADC calibration freeze ports in the ADVANCE control panel. The CAL freeze port is independently available for each RF-ADC and includes a freeze control signal (int_cal_freeze) and a status signal (cal_frozen). An active-High on the freeze control signal freezes both blocks for computation and coefficient update. Coefficients computed prior to the freeze event continue to be in effect until the next enable (unfreeze) event, which

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Chapter 4: Designing with the Core
corresponds to a Low signal on the freeze control port. The time it takes the blocks to change state is approximately 7 s upon a change in the control signal level. Note that this is significantly shorter than the time constants for both the GCB and TSCB. Care does have to be taken so that the freeze control port does not change faster than 7 s intervals. The freeze control mechanism can be provided in one of many different methods, depending on application needs.
A simple signal level detector can be implemented in the PL to monitor the digital output level of the RF-ADC and control the state of the background calibration. Typically a leaky integrator of the absolute value of the RF-ADC output and a hysteresis counter will suffice.
For applications that have a pre-determined duty cycle on the receiver, such as TDD-LTE wireless radios, the TX/RX switching signal can be used in conjunction with the level detector to provide more precise control of the GCB and TSCB blocks.
Note that at the initial startup of the RF-ADC the GCB and TSCB are not at the optimal performance because they both need the presence of some signal to train up the coefficients. The time constant for the convergence for these two blocks is approximately 222 RF-ADC sampling clocks. For applications that requires fast convergence, consider providing a training signal that can be eventually shut off to train the GCB and TSCB blocks right after the startup state machine is completed. This is particularly useful for applications where the input signal is very bursty and with low duty cycle and low power during system startup.
Sub-RF-ADC Outputs
As shown in the block diagram, each of the sub-RF-ADCs are independently in separate data streams until they get mixed by the QMC block, complex mixer, and then filtered by the DDC. The OCB2, GCB, and TSCB coefficients are applied to each sub-RF-ADC independently and can be effectively disabled if you permanently sets the freeze port to active-High. If the QMC block and the DDC block (hence the mixer) are bypassed, then the sub-RF-ADC data streams are output to the logic independently.
Key CAL Features and Guidance Summary
Input signal contents at Fs/N, where N = 8 and 4 for the Dual and Quad RF-ADC tile respectively, must be muted during foreground calibration of OCB2. The signal component at the k*Fs/N bins should be less than -95 dBFs. Gain and Time Skew calibration blocks (GCB, TSCB) should be put in freeze mode when the input signal drops below -40 dBFs level for longer than 100 s. A simple detector block can be used to manage the dynamic control of the freeze port. Dithering mode should be disabled when operating the RF-ADC at 0.75 times the maximum sampling rate or slower for the Dual and Quad parts. For applicable systems, a training signal can also be used to calibrate the GCB and TSCB before switching the system to real time operation. Sub-RF-ADC data output streams are available at the programmable logic interface if the DDC features are not used.

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Chapter 4: Designing with the Core
Getting/Setting Calibration Coefficients
As well as automatic calibration, all four calibration blocks (OCB1, OCB2, GCB, TSCB) are available for getting and setting user coefficients. The application reads back the coefficients generated when calibration is un-frozen, and restores them when needed; this helps to maintain the RF-ADC performance when the input signal does not meet calibration requirements. This feature is available for each RF-ADC in the IP wizard. Enabling this feature increases the size of the IP.
Restoring calibration coefficients disables the real-time calibration control port automatically; an API is provided to disable this user coefficients override mode and re-enable the real-time calibration control port.
Note: The following two limitations apply::
1. The user coefficients getting/setting for GCB is only valid when the DDC channel is in 1x (bypass), NCO off mode, and the samples per AXI4-Stream must be four samples for Quad RF-ADC and eight samples for Dual RF-ADC
2. The calibration block OCB1 does not support calibration coefficients get/set.
Related Information XRFdc_GetCalCoefficients XRFdc_SetCalCoefficients XRFdc_GetCalFreeze XRFdc_SetCalFreeze XRFdc_DisableCoefficientsOverride
Setting Coefficients RFdc API Example The following example code shows the setting of user coefficients for TSCB.
u32 Status = XRFDC_FAILURE; XRFdc_Calibration_Coefficients Coeffs; /*use sample coeffs below*/ Coeffs.Coeff0 = 146; Coeffs.Coeff1 = 255; Coeffs.Coeff2 = 255; Coeffs.Coeff3 = 255; Coeffs.Coeff4 = 113; Coeffs.Coeff5 = 255; Coeffs.Coeff6 = 255 Coeffs.Coeff7 = 255; Status = XRFdc_SetCalCoeffients( RFdcInstPtr, Tile, Block, XRFDC_CAL_BLOCK_TSCB, &Coeffs); If (Status != XRFDC_SUCCESS) {
/*handle error*/ }

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RF-ADC Programmable Logic Data Interface
The data interface between the RF-ADC tiles and the PL is implemented using parallel data streams, using the AXI4-Stream protocol. These data streams are output through the gearbox FIFOs which provide a flexible interface between the user application and the RF-ADC tile. The maximum interface width is 128 bits per stream, representing up to eight 16-bit little endian words. The data streams and associated FIFOs have a configurable number of words which provide the flexibility to choose between the number of words and clock frequency to interface with the PL design. There are four streams per tile, and the naming convention is mXY_axis, where X represents the RF-ADC tile number and Y represents a stream (FIFO) output from that tile. The following figure shows the interfaces.
Figure 22: Dual RF-ADC Tile Programmable Logic Data Interface

Vin1

Decimation

m03_axis

ADC

Mixer/NCO

Decimation

m02_axis

Vin0

Decimation

m01_axis

ADC

Mixer/NCO

Decimation

m00_axis

X19538-082819
Interface Data Formats
The data streams represent real or I/Q data, depending on the RF-ADC tile configuration. For Dual RF-ADC tiles, a given stream is either real, I or Q. If an RF-ADC is configured with I/Q output data, then the streams with an even number represent I data and the streams with an odd number represent Q data. These Dual real and I/Q configurations are shown in RF-ADC IP Configuration .
For Quad RF-ADC tiles, a given stream is either real or I/Q interleaved. If an RF-ADC is configured with I/Q output data, then the even-numbered samples of the stream represent I data and the odd-numbered samples represent Q data. These Quad real and I/Q configurations are illustrated in the following sections.
Related Information RF-ADC IP Configuration

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Chapter 4: Designing with the Core
RF-ADC Interface Data and Clock Rates
The total data rate per channel to the PL is determined by a number of factors, RF-ADC sample rate, decimation factor, and I/Q/Real data formats. The gearbox FIFOs provide a way of interfacing this data rate to the clock frequency of the PL design, by allowing the number of words per clock to be altered. The only requirements are that the number of words and clock rate combine to match the output data rate of the RF-ADC and the decimation rate, if enabled. All RF-ADCs in a tile share a common interface clock frequency. This is shown by the following equations, where 2GIQMode is set to 2 for a Quad RF-ADC tile and I/Q mode is enabled and set to 1 otherwise.
PLDataRate = (ADCDataRate x 2GIQMode) / DecimationRate AXI4-Stream Clock x PLNumWords = PLDataRate AXI4-Stream Clock = PLDataRate / PLNumWords The core automatically calculates the data rates based on the RF-ADC sample rate and datapath settings. This is shown in the following figure. See the RF-ADC Converter Configuration for information on the settings.
Figure 23: RF-ADC Interface Data and Clock Rates Configuration

Because each tile has independent clocking, sample rates, clock rates, PL rates, and configurations can be specified on a per-tile basis.
Related Information RF-ADC Converter Configuration

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Chapter 4: Designing with the Core
PL Clock Interface
The AXI4-Stream data for all four tile streams is synchronous to a clock from the PL, which has a naming convention of mX_axis_aclk, where X represents the RF-ADC tile number. This clock must be at the frequency specified by the Required AXI4-Stream clock displayed on the IP core configuration screen.
The RF-ADC tile also outputs a clock that can be used by the PL. This output clock is a divided version of the RF-ADC sample clock, and is therefore frequency locked to it. This clock has a naming convention of clk_adcX, where X represents the RF-ADC tile number.
Interface FIFO Overflow
The data rate through the interface gearbox FIFOs must be constant during runtime of the RFADC tile, with no frequency drift between the PL clock and RF-ADC sample clock domains. If there is a frequency mismatch between these domains, a FIFO overflow might occur. The interface FIFOs have a built-in feature to determine if FIFO overflow has occurred, which is flagged to the PL using the IP interrupt mechanism.
There are two types of overflow, actual and marginal. Actual overflow indicates that the FIFO read/write pointers are overlapping, which means data is not being transferred safely between domains, and action must be taken. Marginal overflow is a warning and indicates that the FIFO read/write pointers are close to overlapping. Overflow should not occur during normal operation, and if overflow is observed it is an indication that the clocking infrastructure of the PL /PCB/ IP is incorrectly configured.
Related Information Interrupt Hierarchy
Synchronization
The gearbox FIFOs provide a flexible data and clock interface for the RF-ADC tiles. However, as with all dual clock FIFOs, latency can vary between one tile and another. While all channels within a tile have the same latency, some applications might require more than one RF-ADC tile to be used, and require the latencies to be matched across all RF-ADC channels. These applications can use the multi-tile synchronization (MTS) feature to achieve this inter-tile synchronization.
Related Information Multi-Tile Synchronization

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Chapter 4: Designing with the Core

RF-ADC Multi-Band Operation
The RF-ADC can be configured to operate in multi-band mode. This is where the incoming analog input consists of baseband signals up-converted (mixed) to different carrier frequencies. Multiple DDC blocks are used to down-convert the analog input to recover the separate baseband signals.
The RF-ADC multi-band feature supports the following configurations:
� 2x multi-band real data per pair. One RF-ADC analog input is active. Both RF-ADC outputs are enabled.
� 2x multi-band I/Q data per pair. Both RF-ADC inputs are active, one for I and one for Q. Both RF-ADC outputs are enabled.
� 4x multi-band real data per tile (Quad ADC tile only). One RF-ADC analog input is active. All 4 RF-ADC outputs are enabled.
� 4x multi-band I/Q data per tile (Quad ADC tile only). Two RF-ADC inputs are active, one for I and one for Q. All 4 RF-ADC outputs are enabled.
When multi-band is off the I and Q inputs pass straight through the multi-band routing logic. When multi-band is on the I and Q inputs are routed to multiple DDC blocks in the tile.
Figure 24: Multi-Band Routing Logic for Quad RF-ADC tile

IIN
I Datapath

IIN

QIN

DDC

QIN

IIN

DDC

QIN

Q Datapath

X21703-100818

RF-ADC multi-band is implemented by routing the output of one RF-ADC analog block to multiple RF-ADC DDC blocks. Each block handles one band of data, and can mix from multiple carriers to baseband. This is shown for a Quad ADC tile in the following figure.

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Chapter 4: Designing with the Core Figure 25: RF-ADC Multi-Band Configurations

Here, tile 224 is configured in real input to I/Q output mode. ADC0 converts the dual-band signal; ADC1 is off. The top pair can be configured as independent RF-ADCs. The dual-band output is routed to the DDC blocks of ADC0 and ADC1. The mixers in the DDC blocks can be configured to extract the correct band from the incoming data. Tile 225 is configured in 4x multiband I/Q input to I/Q output mode. Here ADC0 carries the quad-band I signal and ADC1 carries the Q data. ADC2 and ADC3 are off. The outputs of the RF-ADCs are routed to all four DDC blocks. Each DDC can be configured to extract the data from the desired frequency band.
RF-ADC Nyquist Zone Operation
Each RF-ADC channel can sample signals in the first or second Nyquist zones. To ensure the RFADC performance is optimal the RF-ADC configuration settings should indicate the intended zone of operation.

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Chapter 4: Designing with the Core

� First Nyquist zone is defined as a signal between 0 and Fs/2 � Second Nyquist zone is defined as a signal between Fs/2 and Fs
Other Nyquist zones can also be used as long as the signal meets the RF-ADC input bandwidth requirements. Zones 1, 3, 5, ... are referred to as odd zones, and zones 2, 4, ... are referred to as even zones.
Related Information RF-ADC Converter Configuration XRFdc_GetNyquistZone XRFdc_SetNyquistZone

RF-ADC IP Configuration
The RF-ADC tile can be configured in several modes. The basic configuration options are available on the IP core configuration screen in the Vivado� IDE and advanced operating modes can be configured using the RFdc driver API.
The RF-ADC is available in Quad or Dual configurations depending on the tile (see the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) and the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)).
Dual RF-ADC Configuration Options
Dual RF-ADC Real Input to Real Output
Figure 26: Dual RF-ADC Real Input to Real Output

Vin1 (Real)

Decimation

m03_axis

ADC

Mixer/NCO (Bypass)

Decimation

m02_axis (Real)

Vin0 (Real)

ADC

Mixer/NCO (Bypass)

Decimation Decimation

m01_axis
m00_axis (Real)
X18274-082019

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Chapter 4: Designing with the Core Figure 27: Dual RF-ADC Real Input to Real Output IP Configuration

The following figure shows a Dual RF-ADC with real data input to real data output, 1x decimation, the mixer bypassed and running at a 500 MHz AXI4-Stream clock.
Figure 28: Dual RF-ADC Real Input to Real Output Data Timing

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Chapter 4: Designing with the Core

Dual RF-ADC Real Input to I/Q Output

Figure 29: Dual RF-ADC Real Input to I/Q Output

Vin1 (Real)

ADC

Mixer/NCO

Q Decimation
I Decimation

Vin0 (Real)

ADC

Mixer/NCO

Q Decimation
I Decimation

m03_axis (Q) m02_axis (I) m01_axis (Q) m00_axis (I)
X18273-082719

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Chapter 4: Designing with the Core Figure 30: Dual RF-ADC Real Input to I/Q Output IP Core Configuration

The following figure shows a Dual RF-ADC with real data input to I/Q data output, 1x decimation, the mixer enabled, and running at a 500 MHz AXI4-Stream clock.

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Chapter 4: Designing with the Core Figure 31: Dual RF-ADC Real Input to I/Q Output Data Timing

Dual RF-ADC I/Q Input to I/Q Output For I/Q input to I/Q output, the RF-ADCs are paired.
Figure 32: Dual RF-ADC I/Q Input to I/Q Output

Vin1 (Q)

ADC

Mixer

Decimation Decimation

m03_axis m02_axis

Vin0 (I)

ADC

Mixer/NCO

Q Decimation
I Decimation

m01_axis (Q)
m00_axis (I)
X18275-082719

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Chapter 4: Designing with the Core Figure 33: Dual RF-ADC I/Q Input to I/Q Output IP Core Configuration

The following figure shows a Dual RF-ADC with I/Q input to I/Q output, 1x decimation, the mixer enabled, and running at a 500 MHz AXI4-Stream clock.

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Chapter 4: Designing with the Core Figure 34: Dual RF-ADC I/Q Input to I/Q Output Timing

Quad RF-ADC Configuration Options
This option is only available on selected devices (see the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) for device information).

Quad RF-ADC Real Input to Real Output

Figure 35: Quad RF-ADC Real Input to Real Output

Vin3 (Real)

ADC

Mixer/NCO (Bypass)

Decimation

m03_axis (Real)

Vin2 (Real)

ADC

Mixer/NCO (Bypass)

Decimation

m02_axis (Real)

Vin1 (Real)

ADC

Mixer/NCO (Bypass)

Decimation

m01_axis (Real)

Vin0 (Real)

ADC

Mixer/NCO (Bypass)

Decimation

m00_axis (Real)
X18276-082719

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Chapter 4: Designing with the Core Figure 36: Quad RF-ADC Real Input to Real Output IP Core Configuration

The following figure shows a Quad RF-ADC real data input to real data output, 1x decimation, the mixer bypassed, and running at a 500 MHz AXI4-Stream clock.

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Chapter 4: Designing with the Core Figure 37: Quad RF-ADC Real Input to Real Output Timing

Quad RF-ADC Real Input to I/Q Output

Figure 38: Quad RF-ADC Real Input to I/Q Output

Vin3 (Real)

ADC

Mixer/NCO

I/Q Decmation

Vin2 (Real)

ADC

Mixer/NCO

I/Q Decimation

Vin1 (Real)

ADC

Mixer/NCO

I/Q Decimation

Vin0 (Real)

ADC

Mixer/NCO

I/Q Decimation

m03_axis (I/Q) m02_axis (I/Q) m01_axis (I/Q) m00_axis (I/Q)
X18277-082719

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Chapter 4: Designing with the Core Figure 39: Quad RF-ADC Real Input to I/Q Output IP Core Configuration

The following figure shows a Quad RF-ADC real input data to I/Q output data, 1x decimation, the mixer enabled, and running at a 500 MHz AXI4-Stream clock. Note that each I/Q channel is interleaved on the output data stream.

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Chapter 4: Designing with the Core Figure 40: Quad RF-ADC Real Input to I/Q Output Timing

Quad RF-ADC I/Q Input to I/Q Output For I/Q input to I/Q output, the RF-ADCs are paired.
Figure 41: Quad RF-ADC I/Q Input to I/Q Output

Vin3 (Q)

ADC

Mixer/NCO

Decimation

Vin2 (I)

ADC

Mixer/NCO

I/Q Decimation

Vin1 (Q)

ADC

Mixer/NCO

Decimation

Vin0 (I)

ADC

Mixer/NCO

I/Q Decmation

m03_axis
m02_axis (I/Q)
m01_axis
m00_axis (I/Q)
X18278-082719

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Chapter 4: Designing with the Core Figure 42: Quad RF-ADC I/Q Input to I/Q Output IP Core Configuration

The following figure shows a Quad RF-ADC I/Q to I/Q, 1x decimation, the mixer enabled, and running at a 500 MHz AXI4-Stream clock.
Figure 43: Quad RF-ADC I/Q Input to I/Q Output Timing

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RF-DAC
Each RF-DAC tile includes a complete clocking support structure with a PLL and the necessary synchronization logic. Every RF-DAC in a tile has a highly configurable FIFO allowing the internal interconnect logic to have direct high-speed access to the RF-DAC (see figure below).
Figure 44: Simplified RF-DAC Functionality Block Diagram

STATUS_DAC0[15:0] DATA_DAC0[255:0]
CONTROL_DAC0[15:0]

I Interpolation Q Interpolation

QMC Threshold Output Filter
Coarse Delay QMC Gain/Phase Crossbar I and Q Mixer
Gearbox FIFO

DAC

VOUT0_P VOUT0_N

X18263-101819

Certain functions can only be executed when the RF-DACs in a tile are paired. Even numbered RF-DACs are used for I datapaths and the odd numbered RF-DACs are used for Q datapaths.
All of the available built-in functionality of a tile and each of the RF-DACs in a tile are user programmable. The Zynq� UltraScale+TM RFSoC RF Data Converter core configuration screen in the Vivado� IDE and the RFdc driver API can be used to configure the digital and analog functionality of the RF-DACs.

RF-DAC Analog Outputs
Each RF-DAC in a tile has its own differential analog current output buffer/driver. The output currents are complementary; the sum of the two currents always equals the full-scale current of the RF-DAC. The digital input code determines the effective differential current delivered to the load. The differential RF-DAC outputs are typically AC-coupled out using capacitors. RF-DAC output DC-coupling is also supported, assuming that the correct common mode biasing and load impedance requirements are met. See UltraScale Architecture PCB Design User Guide (UG583) for more details.
Transmit Transfer Function
The differential output provides the maximum output current when all digital input bits are High. The output current (using binary format) is shown in the following equations.
IVOUTP = (BinDataIn / 2N-1) x IOUTFS
IVOUTN = IOUTFS - IVOUTP
where:

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1. BInDataIn = 14-bit digital input 2. IOUTFS = Full-scale output current The output current (using a twos complement) is shown in the following equations. IVOUTP = (TwosDataIN + 2N-1) / 2N-1) x IOUTFS IVOUTN = IOUTFS - IVOUTP where: 1. TwosDataIN = 14-bit digital twos complement input ranging from (�2N-1) to (2N-1�1) 2. IOUTFS = Full-scale output current.
RF-DAC Output Current Mode
The RF-DAC output current is configurable, with an option of operating in either 20 mA or 32 mA modes. In the 20 mA mode, set the DAC_AVTT to 2.5V and in the 32 mA mode, set it to 3.0V to maintain the linearity performance.
CAUTION! A 3.0V DAC_AVTT should not be used in the 20 mA mode. This risks exceeding the maximum ratings of the device and also risks affecting device reliability. The output current can be set in the Advanced tab in the IP core configuration screen (see the following figure).
Figure 45: RF-DAC Output Current Configuration

RFdc Driver API Commands
// Get output current of RF-DAC Tile1, Block2 to 32mA XRFdc_GetOutputCurr(ptr, 1, 2, XRFDC_OUTPUT_CURRENT_32MA);

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Chapter 4: Designing with the Core
Related Information XRFdc_GetOutputCurr
RF-DAC Nyquist Zone Operation
Each RF-DAC can optimize its output response in the second Nyquist zone by using the mixmode feature. This feature mixes the RF-DAC data with the sample clock, and, as a result, increases the output power in the second Nyquist zone, while attenuating it in the first Nyquist zone. This is shown in the following figure.
Figure 46: RF-DAC Nyquist Zone Operation

For normal (non-mix mode) operation, the blue line represents the ideal RF-DAC output roll-off sinc response. As can be seen, an output image in the second Nyquist zone in this mode would be severely attenuated. An inverse sinc filter is available to compensate for the roll-off in the first Nyquist zone for this mode. See RF-DAC Inverse Sinc Filter for more information.
In RF-DAC mix-mode, the red line represents the ideal RF-DAC output response. In this mode, the output power of the image in the second Nyquist zone is significantly increased, and it also has an approximately flat response across the majority of the zone. The Nyquist zone can be set in the Vivado� IDE.
Related Information RF-DAC Inverse Sinc Filter XRFdc_GetNyquistZone XRFdc_SetNyquistZone

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RF-DAC Inverse Sinc Filter
The analog output response of the RF-DAC follows a characteristic sinx/x, or sinc shape. For applications that require flat-output response over a wide bandwidth, an inverse sinc filter is available to achieve this. The inverse sinc filter is an 11-tap FIR, which provides a flat-response with less than �0.05 dB of ripple up to 89% of Nyquist, or � 0.033 dB of ripple up to 80% of Nyquist. The following figure shows the inverse sinc performance.
Figure 47: Inverse Sinc Frequency Response

The line in blue represents the frequency response of the filter itself. As can be seen, it increases with frequency to compensate for the sinc response of the output, as shown by the red line. The composite output response is given by the yellow trace, and shows a flat pass-band up to 89% of Nyquist. The following figure shows the detail of the corrected response, with ripple specification levels highlighted in red.

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Chapter 4: Designing with the Core Figure 48: Inverse Sinc Detail

Inverse Sinc Filter Use
The filter can be enabled or disabled per RF-DAC in the Vivado� IDE by using the Inverse Sinc Filter check box, as shown in the following figure.
Figure 49: Inverse Sinc Configuration

RFdc Driver API Commands
The RFdc driver API can be used to get the inverse sinc enable state using the following code.
// Get Inverse Sinc State for Tile0, DAC Block1 int Tile = 0; u32 Block = 1; u32 isinc_enabled; isinc_enabled = XRFdc_GetInverseSincFilter (ptr, Tile, Block); xil_printf("DAC%d,%d Inverse Sinc Enabled: %d\n\r", Tile, Block, isinc_enabled);

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Related Information XRFdc_GetInverseSincFilter XRFdc_GetInvSincFIR XRFdc_SetInvSincFIR

Overflow
As seen in the Inverse Sinc Frequency response, the filter gain is >1, and increases with frequency up to approximately 2.4 dB at 80% of Nyquist. To ensure that the filter output does not overflow, the input signal amplitude must be backed-off to account for this gain factor. The inverse sinc block has automatic overflow detection and saturation, and if overflow is detected, it is flagged using the interrupt mechanism to the RFdc driver API, using the XRFDC_DAC_IXR_INVSNC_OF_MASK interrupt. For more details see Interrupt Handling.
Related Information Interrupt Hierarchy

Inverse Sinc Filter Details

Inverse Sinc FIR

-1

-6

-52

594

-52

-6

-1

RF-DAC Digital Datapath
Each RF-DAC in a tile has a number of optimized DSP features that can be used to implement Digital Up Conversion (DUC) and transmit signal filtering. These features are:
� Signal interpolation functionality--interpolation by 1 (bypass), 2, 4, or 8 is supported � Coarse mixing (quarter and half rate) or fine mixing with a 48-bit frequency resolution
numerically controlled oscillator (NCO) � Compensation functionality containing a quadrature modulator correction (QMC) block with
coarse delay adjustment block � Signal conditioning containing an inverse sinc FIR filter
Single, multiple, or all DSP functions can be used or bypassed, using the Vivado� IDE.
The following figure shows the available functions in an RF-DAC. Each function is described in the following sections.

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Figure 50: Signal Treatment of the RF-DAC Peripherals

STATUS_DAC0[15:0]

Output Filter Crossbar
Gearbox FIFO

I Interpolation

DATA_DAC0[255:0]

I and Q Mixer

QMC Gain/Phase and Delay

DAC

Q Interpolation

CONTROL_DAC0[15:0]

X18266-091117

RF-DAC Interpolation Filters
Interpolation filters are required to implement the up-sampling and filtering portions of the DUC process. The implemented filter operation consists of three low pass FIR filters, each with a predetermined, fixed set of coefficients, shown in the following figure. Each filter block can be bypassed and the output of each filter block can be routed to the output of the filter.
� 1x--all filter stages are bypassed � 2x--interpolation using a single stage � 4x--interpolation using two stages � 8x--interpolation using all three available stages
Figure 51: RF-DAC Interpolation Filter

FIR2

Data In

FIR2

FIR1

DataOut

FIR2

FIR1

FIR0

X18267-092118

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The output of an interpolated signal is the exact representation of the original signal presented at a higher sampling rate. Up-sampling of a signal sampled at F1 to a higher sample rate (N*F1) results in N replications of the original spectrum. Low pass filtering of the result helps to remove unwanted replications resulting in the preservation of the original signal at the required higher sample rate.

Table 46: Interpolation Filter Operating Modes

Mode
OFF 1x 2x 4x 8x

Description
Filter is disabled, RF-DAC is not available. Filter is bypassed. 2x interpolation, 80% Nyquist passband. 4x interpolation, 80% Nyquist passband. 8x interpolation, 80% Nyquist passband.

Each of the filter stages can overflow--given the step-response of a FIR filter, especially when full-scale data is on the input. Each filter stage has an overflow status signal and output saturation to detect an overflow and protect the datapath. When a filter stage is not used, the overflow flag is pulled Low. These flags are connected to the datapath interrupts mechanism.

Related Information Interrupt Hierarchy

Interpolation Filter Use
The IP core is used to set the interpolation rate. This is an IP core setting because changing the interpolation rate directly affects the physical interface as the bandwidth to the PL changes. The filters that are enabled are shown in the following figure.

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Chapter 4: Designing with the Core Figure 52: RF-DAC Interpolation Filter Configuration

Note: I/Q input data and mixing requires a minimum of 2x interpolation. If full bandwidth I/Q data is required, two RF-DAC data converters can be operated as independent real streams, containing the I and Q data respectively. Phase adjustment cannot be done when using QMC.
Related Information RF-DAC Converter Configuration
RFdc Driver API Commands The RFdc driver API can be used to get the interpolation rate set in the Vivado� IDE using the following code.
// Get Interpolation factor for Tile0, DUC Block1 int Tile = 0; u32 Block = 1; u32 Interpolation_Factor; if( XRFdc_GetInterpolationFactor (ptr, Tile, Block, &Interpolation_Factor) == XST_SUCCESS) {
xil_printf("DAC Tile%1d,%1d Interpolation Factor is: %d", Tile, Block, Interpolation_Factor); }

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Chapter 4: Designing with the Core Related Information XRFdc_GetInterpolationFactor XRFdc_SetInterpolationFactor
Interpolation Filter Details The interpolation filter chain consists of three FIR filters, FIR2, FIR1, and FIR0, which can be enabled to give successive interpolation by a factor of two per stage. The filter transfer functions are shown in the following figures.
Figure 53: FIR2 and FIR1 Frequency Response
Figure 54: FIR0 and 2x Interpolation Frequency Response

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Chapter 4: Designing with the Core Figure 55: 4x Interpolation and 8x Interpolation Frequency Response

The filter coefficients for the interpolation filters are shown in the following tables.

0 -17

1st Half

0 1401 0

FIR Center 2 Tap

65536

2nd

0 -17

Half

0 1401 0

0 -2112
0 -2112

44 0 -96 0 187 0 -335 0 3145 0 -4723 0 7415 0
44 0 -96 0 187 0 -335 0 3145 0 -4723 0 7415 0

565 0 -906

-13331 0 41526

565 0 -906

-13331 0 41526

1st Half

-12

-337

1008

-2693

10142

FIR1

Center Tap 16384

2nd Half

-12

-337

1008

-2693

10142

1st Half

-6

-254

1230

FIR0

Center Tap

2048

2nd Half

-6

-254

1230

The interpolation filter chains can operate in real or I/Q modes, depending on the data type selected for the RF-DAC interface.

Related Information RF-DAC Programmable Logic Data Interface

RF-DAC Numerical Controlled Oscillator and Mixer
The mixer function has three modes, bypass (no mixing), coarse mixing or fine mixing. Fine mixing automatically enables the NCO which is used to generate the carrier frequency. The mixer supports full quadrature mixing, with both real to I/Q and I/Q to I/Q modes supported.

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Chapter 4: Designing with the Core

Figure 56: RF-DAC Mixer with NCO DSP Block

Coarse Mixer N0, Fs/4, Fs/2, or -Fs/4

IIN

IOUT

3 dB

Fine Mixer

NCO

QIN

3 dB

QOUT

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Chapter 4: Designing with the Core
� To manage potential overflow, the fine mixer output includes 3 dBV attenuation, as shown in the figure above. This attenuation is set to -3 dBV (multiplication factor = 0.707) regardless of the RF-DAC setting in the RFdc driver API. A manual selection is also possible, allowing 0 dBV or -3 dBV.
The mixer settings can be configured in the core, or by using the RFdc driver API. The core is used to set the initial mixer settings (for example, mixer type and mixer mode), and the RFdc driver API is used to adjust the settings at runtime. Both the RFdc driver API and the core compute the required register settings based on the supplied sample rates and desired frequencies.See the RF-DAC Converter Configuration section for information on the settings.
Related Information RF-DAC Converter Configuration
RF-DAC Multi-Band Operation
Multi-band operation is where two or more baseband signals are up-converted (mixed) to individual carriers and then combined to generate a single composite analog output. In the RFDAC tiles, this involves combining multiple DUC blocks together to drive the analog outputs.
The RF-DAC multi-band feature supports the following configurations:
� 2x multi-band real data per pair. One RF-DAC output of the pair is enabled; the other is off. � 2x multi-band I/Q data per pair. Both RF-DACs in the pair are enabled, one for I and one for
Q. � 4x multi-band real data per tile. Four input streams are combined to drive the DAC0 output in
real mode. All other RF-DACs are off. � 4x multi-band I/Q data per tile. Four input streams are combined to drive the DAC0 output as
I and DAC1 output as Q. All other RF-DACs are off.
Latency between outputs in a multi-band pair is matched and latency between pairs is matched, irrespective of the mode.
When multi-band is off, the I and Q datapaths pass straight through the multi-band logic block (as shown below). When multi-band is on, I and Q of each datapath are combined and passed to the next DSP block in the chain in front of the RF-DAC. Multi-band can be turned on per RFDAC, for only the I datapath or the Q datapath, or for both I and Q.

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Figure 57: Multi-Band Logic
IIN IOUT
QIN I Datapath
Q Datapath IIN
QOUT QIN

X18269-081017
RF-DAC multi-band is implemented by connecting multiple RF-DAC DUC blocks to an RF-DAC analog block. Each DUC block handles one band of data, and can mix this up to any carrier frequency. The output is then summed before being sent to the analog datapath and RF-DAC output. This is shown in the following figure.
Figure 58: RF-DAC Digital Datapaths

s03_axis s02_axis

Data Path 3 Q
I Q
Data Path 2
I

DAC3 DAC2

Vout3: 1 band s03_axis Vout2: 1 band s02_axis

Data Path 3 Q
I
Data Path 2 Q
I

DAC3 DAC2

Vout3: Off Vout2: Off

s01_axis s00_axis

Data Path 1 Q
I
Data Path 0 Q
I

DAC1 DAC0

Vout1: Off

s01_axis

Vout0: 2x bands s00_axis

DAC_X0Y0

RF-DAC Tile 2xReal MB, 2x Real

Q
Data Path 1 I

DAC1

Data Path 0 Q
I

DAC0

DAC_X0Y0

RF-DAC Tile 2x I/Q MB

Vout1: 2x bands Vout0: 2x bands -I
X19542-011918

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Chapter 4: Designing with the Core

Two example multi-band configurations are shown. The RF-DAC tile consists of four DUC blocks (digital datapaths) and four RF-DAC-analog blocks (analog datapaths). In the left hand example, the lower RF-DAC pair in the tile is configured as 2x real multi-band, while the top pair are independent RF-DACs. Because the bottom pair uses two DUC blocks, DAC1 is off, and DAC0 outputs the dual-band signal. In the right hand example, the lower pair is configured as 2x I/Q multi-band, while the top pair is off.

RF-DAC Programmable Logic Data Interface
The data interface between the RF-DAC tiles and the PL is implemented using parallel data streams, using the AXI4-Stream protocol. These data streams are input to gearbox FIFOs that provide a flexible interface between the user application and the RF-DAC tile. The maximum interface width is 256 bits per stream, representing up to 16 16-bit little endian words. The data streams and associated FIFOs have a configurable number of words which provide the flexibility to choose between the number of words and the clock frequency to interface with the PL design. There are four streams per tile, and the naming convention is sXY_axis, where X represents the RF-DAC tile number, and Y represents a stream input to the FIFO in that tile. The following figure shows the interfaces.

Figure 59: RF-DAC Data Interfaces

s03_axis 256-bit

Interpolation

Mixer/NCO (Bypass)

DAC

Vout3

s02_axis 256-bit

Interpolation

Mixer/NCO (Bypass)

DAC

Vout2

s01_axis 256-bit

Interpolation

Mixer/NCO (Bypass)

DAC

Vout1

s00_axis 256-bit

Interpolation

Mixer/NCO (Bypass)

DAC

Vout0
X19539-081919

Interface Data Formats
The data streams represent real or I/Q data, depending on the RF-DAC tile configuration. For RFDAC tiles, a given stream is either real or I/Q interleaved. If an RF-DAC is configured with I/Q input data then the even numbered samples of the stream represent I data and the oddnumbered samples represent Q data. These real and I/Q configurations are shown in RF-DAC IP Configuration.

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Chapter 4: Designing with the Core
In each configuration all the enabled RF-DAC FIFOs in a tile begin to accept data when the power-up sequence has completed. This is indicated by the assertion of the sXY_axis_tready outputs. If the data for any stream is not valid at this point, logic to suppress it should be included in the PL.
Related Information RF-DAC IP Configuration
RF-DAC Interface Data and Clock Rates
The total data rate per channel to the PL is determined by a number of factors, RF-DAC sample rate, interpolation factor, and I/Q or Real data formats. The gearbox FIFOs provide a way of interfacing this data rate to the clock frequency of the PL design, by allowing the number of words per clock to be chosen. The only requirements are that the interface number of words and clock rate combine to match the data rate required by the RF-DAC channel, and all RF-DACs in a tile share a common interface clock frequency. This is shown by the following equations:
PLDataRate = (DACDataRate x IQMode) / InterpolationRate PLFclock x PLNumWords = PLDataRate PLFclock = PLDataRate / PLNumWords The IP core automatically calculates the data rates based on the RF-DAC sample rate and datapath settings. This is shown in the following figure.
Figure 60: RF-DAC Data Interface Data and Clock Configuration

Each tile has independent clocking; sample rates, clock rates, PL rates, and configurations can be specified on a per-tile basis.
Related Information RF-DAC Converter Configuration

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Chapter 4: Designing with the Core
PL Clock Interface
The AXI4-Stream data for all four tile streams is synchronous to a clock from the PL, which has a naming convention of sX_axis_aclk, where X represents the RF-DAC tile number. This clock must be at the frequency specified by the Required AXI4-Stream clock displayed on the IP core configuration screen.
The RF-DAC tile also outputs a clock that can be used by the PL. This output clock is a divided version of the RF-DAC sample clock and therefore is frequency locked to it. This clock has a naming convention of clk_dacX, where X represents the RF-DAC tile number.
Related Information Clocking
Interface FIFO Overflow
The data rate through the interface gearbox FIFOs must be constant during runtime of the RFDAC tile, with no frequency drift between the PL clock and RF-DAC analog sample clock domains. If there is a frequency mismatch between these domains, a FIFO overflow can occur. The interface FIFOs have a built-in feature to determine if FIFO overflow has occurred, which is flagged to the PL through the IP interrupt mechanism.
There are two types of overflow: actual and marginal. Actual overflow indicates that the FIFO read/write pointers are overlapping, which means data is not being transferred safely between domains, and action must be taken. Marginal overflow is a warning and indicates that the FIFO read/write pointers are close to overlapping. Overflow should not occur during normal operation, and if overflow is seen it is an indication that the clocking infrastructure of the PL/PCB/IP core is incorrectly configured.
Related Information Interrupt Hierarchy
Synchronization
The gearbox FIFOs provide a flexible data and clock interface for the RF-DAC tiles. However, as with all dual-clock FIFOs, latency might vary between one tile and another. While all channels within a tile have the same latency, some applications might require more than one RF-DAC tile to be used, and require the latencies to be matched across all RF-DAC channels. These applications can use the Multi-Tile Synchronization (MTS) feature to achieve this inter-tile synchronization.
Related Information Multi-Tile Synchronization

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RF-DAC IP Configuration
The RF-DAC can be configured in several modes. The basic configuration options are available on the IP core configuration screen in the Vivado� IDE and advanced operating modes can be configured using the RFdc driver API.

RF-DAC Real Input to Real Output

Figure 61: RF-DAC Real Input to Real Output

s03_axis (Real)

Interpolation

Mixer/NCO (Bypass)

DAC

Vout3 (Real)

s02_axis (Real)

Interpolation

Mixer/NCO (Bypass)

DAC

Vout2 (Real)

s01_axis (Real)

Interpolation

Mixer/NCO (Bypass)

DAC

Vout1 (Real)

s00_axis (Real)

Interpolation

Mixer/NCO (Bypass)

DAC

Vout0 (Real)
X18284-082719

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Chapter 4: Designing with the Core Figure 62: RF-DAC Real Input to Real Output IP Configuration

The following figure shows an RF-DAC with real input to real output, 1x interpolation, the mixer bypassed, and running at a 400 MHz AXI4-Stream clock.

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Chapter 4: Designing with the Core Figure 63: RF-DAC Real Input to Real Output Data Timing

RF-DAC I/Q Input to Real Output

Figure 64: RF-DAC I/Q Input to Real Output

s03_axis (I & Q)

I/Q Interpolation

Mixer/NCO

DAC

s02_axis (I & Q)

I/Q Interpolation

Mixer/NCO

DAC

s01_axis (I & Q)

I/Q Interpolation

Mixer/NCO

DAC

s00_axis (I & Q)

I/Q Interpolation

Mixer/NCO

DAC

Vout3 (Real) Vout2 (Real) Vout1 (Real) Vout0 (Real)
X18279-082719

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Chapter 4: Designing with the Core Figure 65: RF-DAC I/Q Input to Real Output IP Core Configuration

The following figure shows an RF-DAC with I/Q input to real output, 2x interpolation, the mixer bypassed, and running at a 400 MHz AXI4-Stream clock.

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Chapter 4: Designing with the Core Figure 66: RF-DAC I/Q Input to Real Output Timing

Note: Interpolation is x2 because the bandwidth available on the AXI4-Stream interface is limited.

RF-DAC I/Q Input to I/Q Output
For I/Q input to I/Q output, the RF-DACs are paired. An I/Q output signal requires a pair of RFDACs, one for I data and one for Q data. As shown in the following figure, a single DUC block outputs I and Q data and these signals are sent to the two RF-DACs.
Figure 67: RF-DAC I/Q Input to I/Q Output

s03_axis

Interpolation

Mixer/NCO

DAC

Vout3 (Q)

s02_axis (I & Q)

I/Q Interpolation

Mixer/NCO

DAC

Vout2 (I)

s01_axis

Interpolation

Mixer/NCO

DAC

Vout1 (Q)

s00_axis (I & Q)

I/Q Interpolation

Mixer/NCO

DAC

Vout0 (I)
X18280-082719

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Chapter 4: Designing with the Core Figure 68: RF-DAC I/Q Input to I/Q Output IP Core Configuration

The following figure shows an RF-DAC with I/Q input data to I/Q output data with 2x interpolation, the mixer bypassed, and with a 400 MHz AXI4-Stream clock.

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Chapter 4: Designing with the Core
Figure 69: RF-DAC I/Q Input to I/Q Output Data Timing
Note: Interpolation is x2 because the bandwidth available on the AXI4-Stream interface is limited.
Quadrature Modulator Correction
When using an external analog quadrature mixer device, a pair of converters (either RF-ADC or RF-DAC) must be used to handle the I and Q datapaths after conversion. Due to external events or circumstances, errors or imbalances can be introduced in the analog I and Q signal paths which, if not corrected, can lead to system performance degradation. The necessary corrections to restore any system from degrading are accomplished using the quadrature modulator correction (QMC) circuit. As shown in the following figure, the QMC circuit is for correction only. Error and/or imbalance detection must be done by application-specific code in the internal interconnect logic.

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IIN IGAIN

Chapter 4: Designing with the Core

Figure 70: Converter QMC Circuitry

OVR Flag

IOFFSET

IOUT OVR
Flag

QGAIN QIN

Phase OVR

QMC I Datapath
QMC Q Datapath
Flag

QOFFSET

QMC I Datapath
QMC Q Datapath
Flag

OVR

QOUT

X18260-082819
The QMC circuit can compensate for the following:
� Gain correction is done by multiplying the signal by a gain factor. This factor has a range of 0 to 2.0, and individual factors can be applied to the I and Q datapaths. The output resolution of the block is 16 bits.
� Phase correction is achieved by adding a scaled fraction of Q to the I value. The result of this addition can result in a gain error that must be corrected by the gain error correction block. Phase correction has a range of approximately �26 degrees.
� Offset correction is done by adding a fixed LSB value to the sampled signal. Range is -2048 to 2047
For full QMC functionality, a pair of converters need to be set up and used in I/Q mode. When disabling the phase correction factor, the QMC block can supply gain and offset correction to a converter used in real mode. In this case, the converters do not need to be paired to make use of the QMC block functions.

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Update QMC Settings
The gain, phase, and offset correction factor values can be set using the RFdc driver API. An example of using the API is as follows.

// Initial Setup

XRFdc_QMC_Settings QMC_Settings_I, QMC_Settings_Q; // RF-ADC block0 is I, RF-ADC block1 is Q QMC_Settings_I.EventSource = XRFDC_EVNT_SRC_TILE; // QMC Settings are updated with a tile event QMC_Settings_Q.EventSource = XRFDC_EVNT_SRC_TILE;

.... // Update Gain/Phase/Offset for I/Q RF-DACs in tile0

QMC_Settings_I.GainCorrectionFactor = 0.9; // Set Gain for I

QMC_Settings_I.PhaseCorrectionFactor = -5.0; // I/Q imbalance factor

applied to I

side, approx in degrees.

QMC_Settings_I.EnableGain

= 1;

QMC_Settings_I.EnablePhase

= 1;

QMC_Settings_Q.GainCorrectionFactor = 0.95;

QMC_Settings_Q.EnableGain

= 1;

XRFdc_SetQMCSettings(ptr, XRFDC_ADC_TILE, 0, 0, &QMC_Settings_I); // Write

settings

for ADC0,0 - I ADC

XRFdc_SetQMCSettings(ptr, XRFDC_ADC_TILE, 0, 1, &QMC_Settings_Q); //Write

settings

for ADC0,1 - Q ADC

XRFdc_UpdateEvent(ptr, XRFDC_ADC_TILE, 0, 0, XRFDC_EVENT_QMC); //Generate a

Tile

Update Event - applies all QMC Settings at once

It is also possible to read back the QMC settings from any converter, using the XRFdc_GetQMCSettings RFdc driver API command. This populates the QMC_Settings structure with the values from the hardware.

Related Information XRFdc_GetQMCSettings XRFdc_SetQMCSettings XRFdc_UpdateEvent

I/Q RF-ADC Naming Convention
When converters are used in an I/Q pair, the I channel always uses the even block numbers, and the Q channel always uses the odd block numbers. For example, in a Dual RF-ADC tile, the I RFADC is block0, and the Q RF-ADC is block1. For Quad RF-ADC tiles, or RF-DAC tiles, the I channels are block0 and block2, while the related Q channels are block1 and block3, respectively.

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Chapter 4: Designing with the Core
QMC Overflow
Setting excessive gain, phase or offset correction factors relative to the input signal can cause the datapath to overflow. To aid system debug, the QMC block contains built-in overflow detection and saturation blocks. These blocks generate flags which are connected to the IP interrupt mechanism using the datapath interrupt. The related interrupt flags for the QMC block are: XRFDC_IXR_QMC_GAIN_PHASE_MASK XRFDC_IXR_QMC_OFFST_MASK These interrupts can be enabled per converter channel. � The gain correction multiplier range is between 0 and 2.0. � The range of the phase correction multiplier is approximately �26 degrees, or �0.5 in terms of
magnitude.
Related Information Interrupt Hierarchy

Coarse Delay
Coarse delay allows the adjusting of the delay in the digital datapath which can be useful to compensate for delay mismatch in a system implementation. The compensation here is limited to some period of the sampling clock. For PCB design and flight time information for correct delay adjustment see the UltraScale Architecture PCB Design User Guide (UG583). The following table shows the number of periods of the sampling clock (T1 or T2 = 2*T1) for this delay tuning capability.

Table 50: Delay Tuning Sampling Clock Periods

Tile Type
Dual RF-ADC Quad RF-ADC
RF-DAC

Digital Control
0 to 7 0 to 7 0 to 7

Coarse Delay Step
T2 T1 T1

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Dynamic Update Events
Certain datapath features in the RF-ADC and RF-DAC tiles can be updated during runtime. Depending on the application, it might be required to update a setting immediately or to wait for a certain event to apply the update. For example, when resetting the NCO phase, using the SYSREF event allows the phase reset action to be applied at the same time across multiple tiles. The following table shows the available events types.

Table 51: Event Types

Event Name

Function

Immediate

Updates the settings of a given feature immediately after writing.

Block

Updates when the block event register is written. Allows features of a given block to update at the same time.

Updates when the tile event register is written.

Tile

Allows features in all blocks in a tile to update at

the same time.

Updates when the PL_event input on a tile is asserted. Allows features across multiple blocks/ tiles to be updated. PL
Note: This event does not guarantee synchronized updates across tiles.

Event Source
RFdc Driver RFdc Driver
RFdc Driver
dacXY_pl_event or adcXY_pl_event input

Comment
Does not apply for Dual RF-ADC tiles Does not apply for Dual RF-ADC tiles
Asserted from user design in the PL1

SYSREF2

Updates when a SYSREF is received through the SYSREF_p/n input pins. Allows features across
multiple blocks/tiles/devices to update at the same time. The updates are requested using a corresponding API function call, such as XRFDC_ResetNCOPhase to arm the event for all
the block/tiles being requested/armed. The host processor checks the return of the API call to ensure that all of the events arming are completed before issuing the SYSREF pulse if synchronization is wanted across blocks, tiles and devices.

SYSREF_p/n input

Asserted from the SYSREF generator on the PCB (Single or Multidevice) or from API call (Single device only)

PL Marker

Updates when the user_sysref_dac signal is
asserted. This signal is synchronous and aligned to the RF-DAC data. For Multi-Tile Synchronization (MTS), this trigger is not recommended because of FIFO skew adjustment between tiles and devices.

user_sysref_dac IP input

Applies only to RF-DAC tiles

Notes:
1. These signals are synchronous to the converter output clocks, clk_dacX and clk_adcX. These clocks are on local routing. A small amount of logic can be clocked on the output clocks and used to drive the PL event signals. This logic should be placed near the converter to facilitate timing closure. Alternatively the PL event signals can be generated on a global clock and then synchronized to the output clock of the relevant converter.
2. The SYSREF signal used here is coming from analog SYSREF in the RF-DAC tile master. When using SYSREF as a trigger event for dynamic updates to synchronize multiples devices, analog SYSREF must be DC-coupled with the ability to operate in pulse mode; that is, the SYSREF signal is a gapped pulse instead of a continuous clock. This is different from the SYSREF requirement for the MTS function which requires a continuous clock for the duration of the MTS process. In order to support both MTS and SYSREF dynamic updates, the external SYSREF clock supplied has to support both modes. See the Multi-Tile Synchronization section for further details.

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Features that are intended to be dynamically updated must be programmed to be sensitive to one of these update events. The update is a one-shot event. The first trigger latches in the update after it has been armed. The event source for each feature is flexible and can be individually set. The following features support this dynamic update: � Fine Mixer / NCO � Quadrature Modulator Correction (QMC) � Coarse Delay
Related Information Multi-Tile Synchronization
Update Event Use
The RFdc driver API uses the EventSource parameter of a particular function to set up the trigger event for that function. It can also issue a subset of the events. The following code shows an example of the setup of a tile event source followed by the tile event.
// Initial Setup - Mixer settings for 2 DDC blocks XRFdc_Mixer_Settings Mixer_Settings_0; XRFdc_Mixer_Settings Mixer_Settings_1; // Mixer Settings for both DDC blocks are updated with a tile event Mixer_Settings_0.EventSource = XRFDC_EVNT_SRC_TILE; Mixer_Settings_1.EventSource = XRFDC_EVNT_SRC_TILE; .... // Make changes to mixer settings and write them to both DDCs Mixer_Settings_0.freq = 1.23; Mixer_Settings_1.freq = 1.43; XRFdc_SetMixerSettings (ptr, XRFDC_ADC_TILE, 0, 0, &Mixer_Settings_0); XRFdc_SetMixerSettings (ptr, XRFDC_ADC_TILE, 0, 1, &Mixer_Settings_1); // Generate the event for DDC block 0 // This maps to the Tile event, which updates both DDCs at the same moment XRFdc_UpdateEvent(ptr, XRFDC_ADC_TILE, 0, 0, XRFDC_EVENT_MIXER);
Related Information XRFdc_SetMixerSettings XRFdc_UpdateEvent

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PLL
Each RF-ADC and RF-DAC tile includes a clocking system with an input clock divider, a PLL, and an output divider. When used with the SYSREF input, the clocking system can be synchronized in multi-tile or multi-device designs. When the PLL is used, the output sampling clock is fed to the multiplexer, which can also be used by a direct input clock before it is routed into the clock network of the tile (as shown below). The clock from the PLL is used in both the analog and digital portions of the RF-ADC or RF-DAC in a tile. Each RF-ADC or RF-DAC in a tile has a local divider to divide and distribute the very low jitter clock from the PLL or a direct input to the different functions in each RF-ADC or RF-DAC function.

Figure 71: Tile PLL Clocking Structure

adc/dac_clk_p
100 adc/dac_clk_n

CML

Clock Detector

PLL

PLL Div

SYSREF

SYSREF Capture

Demux Mux

SYSREF distribution to adjacent tiles
SYSREF Sync Logic
SYSREF distribution to adjacent tiles

Datapath logic Divider

CLK_adc/dac

Datapath logic

X18215-051319

The operating parameters of the PLL are set using the Vivado� IDE to specify the default PLL configuration or by the RFdc driver API if runtime adjustment of the PLL is required. The PLL must first be enabled in the Vivado IDE if runtime adjustment using the API is required.

The internal PLL block diagram is shown in the following figure. When the internal PLL is used, the IP wizard or the API function dedicated to configuring the PLL system sets a reference divider value as an integer, a feedback divider value as an integer, and an output divider value as an integer to achieve the best performance of the PLL using the VCO in the correct range. In any frequency configuration, the best performance of phase noise is achieved when the PLL system is able to select a reference divider of 1. Allowed value for frequency ranges and integer values of dividers are specified in Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926). For any internal PLL use, the frequency system has the formula Fs = (Fin/R)*(FBDiv/M) as shown in the diagram below where Fs is the PLL frequency output and Fin is the reference frequency.

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Reference Divider (R)
Input (Reference Frequency)

Figure 72: PLL System

PFD

Output (PLL Frequency Output)
CP (VCO Frequency)

VCO

LPF

Output Divider (M)

Feedback Divider

X20569-050919

PLL Parameters
The following table shows key parameters of the on-chip PLL.

Table 52: PLL Parameters

Reference Divider (R)
1 to 4

Feedback Divider (N)
13 to 160

Output Divider (M)
2,4,6,8...,(even number 64)

VCO Frequency (GHz)
8.5 to 13.2

Interrupt Handling
The RF-ADC and RF-DAC tiles can generate interrupts during operation which can help debug or avoid potential issues. The interrupts are shown in the following table.

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Table 53: Interrupts

Interrupt
RF-ADC/RF-DAC datapath interrupt

Description
IP register interrupt at register 0x208 0x210 0x218 0x220
This interrupt indicates that one of the datapath interrupts is active. To clear this interrupt, all datapath sub-interrupts must be cleared.

Overflow in RF-DAC Interpolation Stage 0/1/2/3 I or Q datapath

Indicates that one of the interpolation stages has overflowed/saturated. Flags are per-stage and I / Q paths to indicate where the overflow has occurred. Data amplitude is too high.

Overflow in RF-ADC Decimation Stage 0/1/2/3 I or Q datapath

Indicates one of the RF-ADC decimation stages has overflowed/saturated. Flags are per-stage and I/Q paths to indicate where the overflow has occurred. Data amplitude is too high.

Overflow in RF-DAC/RF-ADC QMC Gain/Phase
Overflow in RF-DAC/RF-ADC QMC Offset
Overflow in RF-DAC Inverse Sinc Filter

Indicates the QMC gain/ phase correction has overflowed/saturated. Data amplitude, or correction factors are too high and should be reduced.
Indicates the QMC offset correction has overflowed/ saturated. Data amplitude, or correction factors are too high and should be reduced.
Indicates the RF-DAC inverse Sinc filter has overflowed/ saturated. Data amplitude is too high and should be reduced. See "RF DAC Inverse Sinc Filter, Overflow"

Sub RF-ADC0/1/2/3 Over/ Under range Interrupt

Indicates the analog input is exceeding the full-scale range of the Sub-RF-ADC. The input signal amplitude should be reduced. See "Over Range"

Interrupt Mask Macro
XRFDC_ADC_DAT_OVR_MASK
XRFDC_DAC_IXR_INTP_I_STG0_MASK XRFDC_DAC_IXR_INTP_I_STG1_MASK XRFDC_DAC_IXR_INTP_I_STG2_MASK XRFDC_DAC_IXR_INTP_Q_STG0_MASK XRFDC_DAC_IXR_INTP_Q_STG1_MASK XRFDC_DAC_IXR_INTP_Q_STG2_MASK XRFDC_ADC_IXR_DMON_I_STG0_MASK XRFDC_ADC_IXR_DMON_I_STG1_MASK XRFDC_ADC_IXR_DMON_I_STG2_MASK XRFDC_ADC_IXR_DMON_Q_STG0_MASK XRFDC_ADC_IXR_DMON_Q_STG1_MASK XRFDC_ADC_IXR_DMON_Q_STG2_MASK
XRFDC_IXR_QMC_GAIN_PHASE_MASK
XRFDC_IXR_QMC_OFFST_MASK
XRFDC_DAC_IXR_INVSNC_OF_MASK
XRFDC_SUBADC0_IXR_DCDR_OF_MASK XRFDC_SUBADC0_IXR_DCDR_UF_MASK XRFDC_SUBADC1_IXR_DCDR_OF_MASK XRFDC_SUBADC1_IXR_DCDR_UF_MASK XRFDC_SUBADC2_IXR_DCDR_OF_MASK XRFDC_SUBADC2_IXR_DCDR_UF_MASK XRFDC_SUBADC3_IXR_DCDR_OF_MASK XRFDC_SUBADC3_IXR_DCDR_UF_MASK

Mask Value
0x40000000U
0x00000010U 0x00000020U 0x00000040U 0x00000080U 0x00000100U 0x00000200U 0x00000010U 0x00000020U 0x00000040U 0x00000080U 0x00000100U 0x00000200U
0x00000400U
0x00000800U
0x00001000U
0x00010000U 0x00020000U 0x00040000U 0x00080000U 0x00100000U 0x00200000U 0x00400000U 0x00800000U

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Table 53: Interrupts (cont'd)

Interrupt
RF-ADC over range
RF-ADC over voltage
RF-ADC/RF-DAC FIFO over/ underflow
RF-ADC/RF-DAC Overflow RF-ADC/RF-DAC Underflow RF-ADC/RF-DAC Marginal Overflow RF-ADC/RF-DAC Marginal Underflow

Description
Indicates the analog input is exceeding the full-scale range of the RF-ADC. The input signal amplitude should be reduced. To clear this interrupt, the sub-RF-ADC Over range interrupts must be cleared. See "Over Range".
Indicates the analog input is exceeding the safe input range of the RF-ADC input buffer and the buffer has been shut down. The input signal amplitude and common mode should be brought within range. See "Over Voltage".
IP register interrupt at register 0x208 0x210 0x218 0x220
This interrupt indicate one of the datapath interrupts is active. To clear this interrupt, all datapath sub-interrupts must be cleared.
Indicates that the FIFO interface is incorrectly setup, clocks/data throughput mismatch.

Interrupt Mask Macro
XRFDC_ADC_OVR_RANGE_MASK
XRFDC_ADC_OVR_VOLTAGE_MASK
XRFDC_ADC_FIFO_OVR_MASK XRFDC_IXR_FIFOUSRDAT_OF_MASK XRFDC_IXR_FIFOUSRDAT_UF_MASK XRFDC_IXR_FIFOMRGNIND_OF_MASK XRFDC_IXR_FIFOMRGNIND_UF_MASK

Mask Value
0x08000000U
0x04000000U
0x80000000U 0x00000001U 0x00000002U 0x00000004U 0x00000008U

Interrupt Hierarchy
The following figure shows the interrupt hierarchy within the IP core.

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Figure 73: Interrupt Hierarchy Zynq UltraScale+ RFSoC RF Data Converter

Programmable Logic

ADC Tile 0

ADC Tile0, 0 Interrupt Status
OverVoltage OverRange DataPath FIFO
Enable[3:0]

DAC Tile 0

DAC Tile0, 0 Interrupt Status DataPath FIFO
Enable[1:0]

ADC Tile0 Interrupt Status
Converter0 Converter2 Converter1 Converter0
Enable[3:0]
DAC Tile0 Interrupt Status
Converter0 Converter2 Converter1 Converter0
Enable[3:0]

Common Interrupt Status
ADC3 ADC2 ADC1 ADC0
DAC3 DAC2 DAC1 DAC0

irq
To PS/MicroBlaze Interrupt Controller

Enable[7:0]

X19541-050919
Datapath overflow indicates that a sub-block in the signal chain has detected that the output signal amplitude has exceeded full scale, and has been saturated. If overflow is detected it indicates that either the signal amplitude is too high, or the block settings are incorrect for the signal amplitude. For example, using a large gain correction factor on a signal that is close to fullscale causes a QMC gain overflow.
All of the interrupts shown in the previous figure are enabled and handled by the interrupt functions of the RFdc driver API. The default interrupt status handler (XRFdc_IntrHandler) automatically follows the interrupt hierarchy in the previous figure to determine the source of the interrupt, and then passes this information to the user-defined status handler to respond.
Related Information Quadrature Modulator Correction RF-ADC Decimation Filters RF-DAC Interpolation Filters Clocking

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Interrupt Setup and Handling Example
The following code shows an interrupt setup and handling example.
// // Handler // // User-Defined interrupt status handler void RFdcHandler (void *CallBackRef, u32 Type, int Tile, u32 Block, u32 Event) { // Check the type of interrupt event
if (Type == XRFDC_DAC_TILE) { xil_printf("\nInterrupt occurred for ADC%d,%d :", Tile_Id, Block_Id); if(Event & (XRFDC_IXR_FIFOUSRDAT_OF_MASK |
XRFDC_IXR_FIFOUSRDAT_UF_MASK)) { xil_printf("FIFO Actual Overflow\r\n");
} if(Event & (XRFDC_IXR_FIFOMRGNIND_OF_MASK | XRFDC_IXR_FIFOMRGNIND_UF_MASK)){
xil_printf("FIFO Marginal Overflow\r\n"); } if(Event & XRFDC_DAC_IXR_INTP_STG_MASK)) {
xil_printf("Interpolation Stages Overflow\r\n"); } // ... Other handling code ... } else {
xil_printf("\nInterrupt occurred for ADC%d,%d :\r\n", Tile_Id, Block_Id);
// ... ADC handling code ... } } // // Setup // // Register the user-defined interrupt handler XRFdc_SetStatusHandler(ptr, ptr, (XRFdc_StatusHandler) RFdcHandler); // // Setup for RF-DAC tile 0, block 0 - FIFO Interrupt // XRFdc_IntrEnable(ptr, XRFDC_DAC_TILE, 0, 0, XRFDC_IXR_FIFOUSRDAT_MASK); // // Test // // Force a FIFO interrupt by setting the FIFO write words to a different value from the design requirements. // Note: Assumes a value of 1 is invalid for this design. XRFdc_SetFabRdVldWords(ptr, 0, 0, 1); This example shows the RFdc driver-specific interrupt handling and the forcing of an interrupt by changing the FIFO parameters. The setup and registration of the RF Data Converter irq output with the PS or MicroBlazeTM interrupt controller is not shown. For more details, see the examples provided with the RFdc driver API (see the Zynq UltraScale+ Device Technical Reference Manual (UG1085)).

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Related Information XRFdc_IntrEnable XRFdc_SetFabRdVldWords

Chapter 4: Designing with the Core

Clocking
The following table describes the clocks associated with the Zynq� UltraScale+TM RFSoC RF Data Converter IP core.

Table 54: IP Core Clocks

Clock
s_axi_aclk dac[3:0]_clk_p/n adc[3:0]_clk_p/n clk_dac[3:0] clk_adc[3:0]
s[3:0]_axis_aclk
m[3:0]_axis_aclk

Description
AXI4-Lite clock. This clock is common to all tiles in the core and should be driven by the system CPU used for the AXI4-Stream interconnect connected to the AXI4-Lite interface. This clock frequency range is specified in Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
Sampling Clock or Reference Clock to internal PLL for the RF-DAC tiles. There are up to four differential clock inputs on the core because there is a maximum of four RF-DAC tiles available. This clock must be driven with the frequency chosen on the IP core configuration screen.
Sampling Clock or Reference Clock to internal PLL for the RF-ADC tiles. There are up to four differential clock inputs on the core because there is a maximum of four RF-ADC tiles available. This clock must be driven with the frequency chosen on the IP core configuration screen.
Output clock to interconnect logic from the RF-DAC tiles. This is a user-configurable output clock from the core to the user logic. The use of this clock is optional. It can be used to drive the PL design if another frequency-locked RF-DAC sample clock is not available in the PL. The frequency of this clock output can be chosen from a list of values, related to the sample rate, in the IP core configuration screen.
Output clock to interconnect logic from the RF-ADC tiles. This is a user-configurable output clock from the core to the user logic. It can be used to drive the PL design if another frequency-locked RF-ADC sample clock is not available in the PL. The frequency of this clock output can be chosen from a list of values, related to the sample rate, in the IP core configuration screen.
Slave AXI4-Stream clocks for RF-DAC data interfaces. There are up to 16 AXI4-Stream interfaces on the core, one per RF-DAC. Each RF-DAC tile has a single clock common to up to four AXI4-Stream data interfaces. All AXI4-Stream data interfaces on a tile must operate at the same clock rate but the bandwidth of each interface can be different because each AXI4-Stream interface can have a different width as specified in the IP core configuration screen. This clock must be frequency-locked to the RF-DAC sample clock as outlined in Interface FIFO Overflow.
Master AXI4-Stream clocks for RF-ADC data interfaces. There are up to eight or 16 AXI4Stream interfaces on the core depending on the chosen device, one per RF-ADC. Each RFADC tile has a single clock common to up to two or four AXI4-Stream data interfaces. All AXI4-Stream data interfaces on a tile must operate at the same clock rate; however the bandwidth of each interface can be different because each AXI4-Stream interface can have a different width as specified in the IP core configuration screen. This clock must be frequency-locked to the RF-ADC sample clock as outlined in Interface FIFO Overflow.

Related Information Interface FIFO Overflow

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Clock Inputs
Each RF-ADC or RF-DAC tile has its own clock input. There is no need to instantiate a clock input buffer in your design because the current-mode logic (CML) clock input buffer is implemented in the tile architecture. The clock input buffer can be used as a sampling clock for the tile or as a reference for the tile PLL. The CML clock input has an on-die differential termination of 100 .
The clock input buffer has a detection circuit for measuring activity at the external clock inputs. When a clock is present, the input buffer is activated. When no clock is present, the outputs of the clock buffer are forced into a steady state. If the clock is lost, the core shuts the tile down but will restart the tile without user intervention when the clock returns. The Reset Count Register increments each time the core shuts the tile down.
When the PLL is not used, the clock buffer output is passed through a multiplexer into the RFADC or RF-DAC tile clock network. When the PLL is used, the output of the clock buffer is driven to the PLL to serve as the reference clock.
In each Zynq� UltraScale+TM RFSoC, there is a dedicated input SYSREF pin pair per package. The SYSREF clocks the multi-tile and multi-device synchronization. For multi-tile designs, the SYSREF connects into a master tile and the signal must be distributed from inside that tile to all other tiles used in the design.
The presence of a clock at the input pins can be checked by using the RFdc software API. If no clock is detected the RF-ADC and RF-DAC blocks affected do not start up and stay in the Clock Detection state.
Related Information Power-up Sequence XRFdc_GetIPStatus Reset Count Register (0x0038)
Tile Clocking Structure
The following figures show the tile high-level clocking structure. The clocking structure in a tile starts from a single clock source coming from the tile PLL or straight from the clock input pins.
For a tile to keep a low-jitter and high-speed clocking structure, a single input clock is routed to each RF-ADC or RF-DAC in the tile and divided for the dedicated signal conditioning functions within the RF-ADC or RF-DAC.

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RF-ADC

Figure 74: RF-ADC Clock Structure in a Tile
SYSREF Clock

RF-ADC

PLL Divider

CLK Drive
Clk Sync

CLK Drive

Sync

Analog Clock

Sync DIV Sync

CLK Drive

Digital Clock Domain

Digital Functions Clock Domain

clk_adcX Sync_Flag

Internal Logic Clock Domain
m_axis_aclk
X18249-080917

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RF-DAC

Figure 75: RF-DAC Clock Structure in a Tile
SYSREF Clock

RF-DAC

PLL Divider

CLK Drive
Clk Sync

CLK Drive

Sync Sync
DIV

Analog Clock

Sync

CLK Drive

Digital Clock Domain

Digital Functions Clock Domain

Internal Logic Clock Domain

clk_dacX Sync_Flag

s_axis_aclk

X18216-080917

The clock coming out from the divider of the master tile can be used to drive the PL. A BUFG_GT buffer is automatically instantiated by the IP core when the output clock is used.
The following figure shows the clock connections for a typical Zynq� UltraScale+TM RFSoC RF Data Converter IP core. The IP core automatically instantiates and connects the constituent RFADC and RF-DAC tiles based on the selections in the Vivado� IDE.

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Sampling Clock or Reference Clock
AXI4-Stream Clock (Sample Clock) AXI4-Lite Clock (CPU Clock)

BUFG BUFG

Figure 76: IP Core Clocking

Zynq UltraScale+ RFSoC RF Data Converter IP

adc0_clk_p adc0_clk_n s0_axis_aclk
s_axi_aclk

RF-ADC Tile

ADC_CLK_P ADC_CLK_N

CLK_ADC

FABRIC_CLK

DCLK

clk_adc0

Sampling Clock or Reference Clock

adc1_clk_p adc1_clk_n
s01_axis_aclk

RF-ADC Tile

ADC_CLK_P ADC_CLK_N

CLK_ADC

FABRIC_CLK

DCLK

clk_adc1

X18271-081117
In most applications the AXI4-Stream clock is common to multiple converters and is supplied from an external clock as shown in the previous figure. This clock must be derived from the same master clock source as the sampling and/or reference clocks to the RF-ADC and RF-DAC tiles. Alternatively, it is possible to use the output of one of the RF-DAC or RF-ADC tiles to generate the AXI4-Stream clocks as shown in the following figure.

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Figure 77: Typical Clocking Scheme Using RF-ADC Output Clock as Data Clock

Sampling Clock or Reference Clock AXI4-Lite Clock BUFG (CPU Clock)

Zynq UltraScale+ RFSoC RF Data Converter

adc0_clk_p adc0_clk_n s0_axis_aclk
s_axi_aclk

RF-ADC Tile

ADC_CLK_P ADC_CLK_N

CLK_ADC

FABRIC_CLK

DCLK

clk_adc0
BUFG_GT

MMCM
(Optional)

BUFG

Sampling Clock or Reference Clock

adc1_clk_p adc1_clk_n
s01_axis_aclk

RF-ADC Tile

ADC_CLK_P ADC_CLK_N

CLK_ADC

FABRIC_CLK

DCLK

clk_adc1

To User Logic AXI4-Stream
Interface

X18272-081117

Resets
Standard AXI4-Stream resets are provided for each clock domain. Reset of the RF-ADC and RFDAC is done using the AXI4-Lite interface. A full tile reset is carried out by asserting bit 0 of the Master Reset Register. Individual tiles can be reset and disabled by writing to the Restart registers. Disabling the tile is achieved in a similar way. Follow the individual tile reset procedure to restart the tile after it has been disabled.
Related Information Master Reset Register (0x0004) Restart All Tiles Restart Tile Power-Down Tile

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Power-up Sequence
Tiles consist of different independent blocks, powered from different power supplies and clocked by different versions of the main clock. Tiles must be brought up in a known sequence for the converters to function correctly. The power-up state machine is run automatically when the device is configured or reconfigured with a bitstream but it can also be rerun at any time under software control.
IMPORTANT! The IP should only be started when all external clocks are running and stable (glitch-free). The IP AXI4-Lite reset (s_axi_aresetn) can be held Low if the startup needs to be delayed until the external clocks are valid.

Figure 78: POR Finite State Machine
Device Power Up and Configuration

Power Supply Adjustment

Supply Detectors

Clock Configuration

Clock Detector

Converter Calibration Done

X18500-081117

Power-on Sequence Steps

Table 55: Power-on Sequence Numbers

Sequence Number
0-2
3-5 6-10 11-13

State

Description

Device Power-up and Configuration
Power Supply Adjustment
Clock Configuration Converter Calibration (ADC only)

The configuration parameters set in the Vivado� IDE are programmed into the converters. The state machine then waits for the external supplies to be powered up. In hardware this can take up to 25 ms. However this is reduced to 200 s in behavioral simulations.
The configuration settings are propagated to the analog sections of the converters. In addition the regulators, bias settings in the RFDAC, and the common-mode output buffer in the RF-ADC are enabled.
The state machine first detects the presence of a good clock into the converter. Then, if the PLL is enabled, it checks for PLL lock. The clocks are then released to the digital section of the converters.
Calibration is carried out in the RF-ADC. In hardware this can take approximately 10 ms, however this is reduced to 10 s in behavioral simulations.

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Table 55: Power-on Sequence Numbers (cont'd)

Sequence Number

State

Wait for deassertion of AXI4Stream reset

Done

Description
The AXI4-Stream reset for the tile should be asserted until the AXI4Stream clocks are stable. For example, if the clock is provided by a MMCM, the reset should be held until it has achieved lock. The state machine waits in this state until the reset is deasserted.
The state machine has completed the power-up sequence.

Related Information Interrupt Hierarchy RF-DAC/RF-ADC Tile <n> FIFO Disable Register (0x0230)

Restart All Tiles
To restart all tiles and perform the complete power-on sequence after initialization under software control, perform the following steps:
1. Write 0x0000_0001 to the Master Reset register to restart all tiles (start and end states revert to their default so there is no need to write 0x0000_000F to the individual tile Restart State register).
2. Poll the tile Restart Power-On State Machine register for each individual tile to check operation is complete. The power-on sequence is complete when this register reads all zeros.
Related Information Master Reset Register (0x0004) Restart State Register (0x0008) Restart Power-On State Machine Register (0x0004)

Restart Tile
To restart a tile and perform the complete power-on sequence after initialization under software control, perform the following steps:
1. Write 0x0000_000F to the tile<n> Restart State register. 2. Write 0x0000_0001 to the tile<n> Restart Power-On State Machine register to restart the
tile. 3. Poll the tile<n> Restart Power-On State Machine register to check operation is complete; the
power-on sequence is complete when this register reads all zeros.
Related Information Restart State Register (0x0008) Restart Power-On State Machine Register (0x0004)

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Power-Down Tile
To power down a tile, the power-on sequence is rerun in the same way as restarting a tile but with the End State set to 3 rather than F. Setting the End State to 3 makes the power-on sequencer clear all the registers without performing a full power-on sequence. Perform the following steps to power down a tile:
1. Write 0x0000_0003 to the individual tile Restart State register. 2. Write 0x0000_0001 to the tile<n> Restart Power-On State Machine register to restart the
tile. 3. Poll the tile<n> Restart Power-On State Machine register to check operation is complete; the
power-down sequence is complete when this register reads all zeros.
Related Information Restart State Register (0x0008) Restart Power-On State Machine Register (0x0004)

Bitstream Reconfiguration
To load a new bitstream or reload the current bitstream into the Zynq� UltraScale+TM RFSoC when there are one or more tiles in operation then the following steps must be followed to ensure safe operation.
1. Mute the analog front end to avoid TX and RX signaling. 2. Individually shut down all RF-ADC and RF-DAC tiles used using the XRFDC_Shutdown API
command or the Power-Down Tile registers. 3. Load the new bitstream or reload the existing bitstream. 4. Proceed with the normal Power-up sequencing.

Interfacing to the AXI4-Stream Interface
The number of AXI4-Stream interfaces and the width of each bus depends on the bandwidth required by the mode of operation selected in the Vivado� IDE. Interpolation and decimation allow the AXI4-Stream bandwidth requirements to be reduced and the width of each AXI4Stream interface can be selected on the IP core configuration screen in conjunction with the clock rate and interpolation/decimation settings.
The following figure shows a single RF-DAC data input at 4 GSPS with 8x interpolation with I and Q on a single AXI4-Stream interface running at 500 MHz.

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The following figure shows an RF-ADC at 4 GSPS with 4x decimation with I and Q on a single AXI4-Stream interface running at 500 MHz.
Figure 80: Single RF-ADC Output
The following figure shows 2x32-bit RF-DACs at 4 GSPS with real data, 8x interpolation, and running at a 250 MHz AXI4-Stream clock.
Figure 81: Two RF-DACs with Real Data on Separate Interfaces at 250 MHz

Applications Overview
This section gives an overview of how the Zynq� UltraScale+TM RFSoC RF Data Converter features can be used in a system.

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Multi-Tile Synchronization
The Zynq� UltraScale+TM RFSoC has a very flexible clocking and data interface to enable a multitude of different applications within the same device. Each RF-ADC/RF-DAC tile has its own independent clocking and data infrastructure, which allows each tile to be driven with individual sample rates, and PL data-word widths. The converters within a single tile share the clocking and data infrastructure, so the sample rates and latency are fixed. However, certain applications might require more than one tile, or even more than one Zynq UltraScale+ RFSoC to be used together. For these applications, matching converter latency across tiles is critical. The multi-tile synchronization (MTS) feature can be used to achieve this multi-tile and device alignment.
Note: In this documentation multi-tile synchronization (MTS) is synonymous with multi-converter synchronization.
Related Information Clocking
Detailed Description
In any system with multiple independent converters and clocking structures, there are several potential sources of latency uncertainty, such as the clock divider phase, NCO phase, FIFO latencies, clock skew, and data skew. Discrete converters have standardized the use of the JESD204B SYSREF scheme for synchronization, and as a result the Zynq� UltraScale+TM RFSoCs have implemented a complementary, simplified scheme using SYSREF.

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Figure 82: Zynq� UltraScale+TM RFSoC Multi-Tile Synchronization Example

RFSoC Device
User Design/ PL Signals

RF Data Converter IP Core

s13_axis_tdata s12_axis_tdata

Data Path 3 Data Path 2

DAC3 DAC2

FIFO FIFO

s1_axis_aclk clk_dac1 s11_axis_tdata s10_axis_tdata

FIFO FIFO

FIFO CTRL

Sync

PLL

Data Path 1 Data Path 0

DAC1 DAC0
DAC_X0Y1

PCB Signals
Clock Generation
DAC1_CLK_p/n Analog Clock

s03_axis_tdata
s02_axis_tdata user_sysref_dac
IP Sync SM
s0_axis_aclk
clk_dac0 s01_axis_tdata
s00_axis_tdata

FIFO FIFO

Data Path 3 Data Path 2

DAC3 DAC2

FIFO

Sync

CTRL

PLL

Data Path 1 Data Path 0

DAC1
DAC0
DAC_X0Y0 SYSREF Distribution

SYSREF_p/n

Analog SYSREF

DAC0_CLK_p/n Analog Clock

PL_clock PL_SysRef

AXI Interface

PL Clock PL SYSREF

X19517-032118
The integration of the converters in the Zynq� UltraScale+TM RFSoCs results in the elimination of the serial transceiver links for data communication. However, to provide a flexible clocking and number of data words for the PL design, each RF-ADC and RF-DAC incorporates independent gearbox FIFOs. These FIFOs allow data to be transferred between the PL clock domain to the converter sample clock domain, but this results in a non-deterministic latency that must also be measured and corrected for by using SYSREF.

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The Zynq� UltraScale+TM RFSoC RF Data Converter and RFdc driver API solution provide an easy to use and integrated way to synchronize each of the tiles in a given device. The previous figure shows an example system with multiple tiles which are to be synchronized. The following applies to the previous figure:
� Two RF-DAC tiles are shown for the purposes of illustration, but the method applies equally to any number of RF-ADC or RF-DAC tiles.
� A single analog SYSREF input per device is distributed internally to all RF-ADCs and RF-DACs.
� There is an internal analog SYSREF delay adjust per tile, to ease PCB requirements by allowing SYSREF setup/hold time to be optimized on-chip.
� There is an analog clock input per tile; these are shown as DAC0_CLK and DAC1_CLK. � The common clock for the PL user design and tiles is shown as PL Clock (PL_clock). � The SYSREF for the PL is shown as PL SYSREF (PL_SysRef). There is a separate PL SYSREF
for RF-ADCs and RF-DACs if both are in the synchronization group. � The synchronization state machine is contained within the core, which, with the RFdc driver
API, implements the synchronization solution. � For RF-DAC multi-tile synchronization (MTS), the RF-DAC tile master is always used as the
reference tile for all other RF-DAC tiles to synchronize to. As a result, RF-DAC tile 0 must be an active tile in the application of MTS for the RF-DAC. � Similarly, the RF-ADC tile master is always used as the reference tile for the synchronization of all other RF-ADC tiles. As a result, RF-ADC tile 0 must be an active tile in the application of MTS for the RF-ADC. � If it is required to disable a tile that is present in the SYSREF chain it should be powered down to state 3 in the power-on sequence. This ensures that the SYSREF is still propagated along the chain. � Package flight time skew for each converter should be taken into account and adjusted for during PCB design.
Synchronization Steps
At a high level, the synchronization steps that are carried out are as follows:
1. Enable all clocks and SYSREF generators a. Both analog and digital clocks must be running and locked before synchronization begins b. Any change to the clocks requires resynchronization
2. SYSREF analog capture a. Ensures SYSREF is safely captured by auto-adjusting the internal SYSREF programmable delay for setup/hold

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b. This is done for each tile and requires a number of periodic SYSREF pulses so that the optimal delay value can be determined. As a result, a periodic SYSREF clock is needed for the MTS process.
3. Clock divider reset � When all tiles are safely capturing SYSREF, a subsequent SYSREF edge is used to synchronize all divider phases
4. FIFO latency measure and adjust a. Use the PL_SysRef signal to measure the latency through each FIFO b. Use the measurements across all tiles to adjust the latencies so that they match
Steps 2, 3, and 4 are handled automatically by the IP core and RFdc driver API.

RFdc Driver API Use
The RFdc driver API is used to initiate the synchronization procedure and check the status. The following example applies to the RF-DAC synchronization group. The same procedure should be run on the RF-ADC synchronization group.

int status_dac; XRFdc_MultiConverter_Sync_Config DAC_Sync_Config; Settings structure

// Declare DAC MTS

XRFdc_Multiconverter_Init (&DAC_Sync_Config, 0, 0); DAC MTS Settings DAC_Sync_Config.Tiles = 0x3; Tiles to sync bit-mask: DAC tiles 0 and 1

// Initialize //

// Run Multi-Tile-Sync for the DAC Group status_dac = XRFdc_Multiconverter_Sync(RFdcInstPtr, XRFDC_DAC_TILE, &DAC_Sync_Config);

After synchronization, the synchronization status can be reported:

if(status_dac == XRFDC_MTS_OK) xil_printf("INFO : DAC Multi-Tile-Sync completed successfully\n");
else xil_printf("ERROR : DAC Multi-Tile-Sync Issue - check metal_log for
error information\n");

// // Report Overall Latency in Sample Clocks and delay adjustments made in terms of PL words added to each Tile/FIFO // xil_printf("\n\n=== Multi-Tile Sync Report ===\n"); for(i=0; i<4; i++) {
if((1<<i)&DAC_Sync_Config.Tiles) { XRFdc_GetInterpolationFactor(RFdcInstPtr, i, 0, &factor); xil_printf(" DAC%d: Latency(T1) =%3d, Adjusted Delay (T%d) =%3d

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\n", i, DAC_Sync_Config.Latency[i], factor,
DAC_Sync_Config.Offset[i]); }
}
Note: The apparent latency value reported must not be confused with the absolute FIFO or tile data latency; it is a relative measure of the alignment between tiles.

Advanced Multi-Tile Synchronization API Use
The multi-tile API use outlined in the previous section guarantees alignment between tiles in each group. However, the total latency through the tiles can vary by a number of words related to the FIFO read-clock period divided by the number of read-words. For applications where the total latency must be constant, the Target_Latency setting in the API can be enabled. This setting adjusts all delays less than the target to the target value; any measured values greater than the target results in an error. To prevent this error, the Target_Latency value must first be determined for the user FIFO and tile configuration by running XRFdc_MultiConverter_Sync with the target set to zero. The returned latency value (plus some margin) must be set as the target value for future runs.
The margin value to be applied is specified in terms of sample clocks. For the RF-ADC tiles, this value must be a multiple of the number of FIFO read-words times the decimation factor, and for RF-DAC tiles this value can be a constant of 16. An example of setting the target latency is as follows:

XRFdc_MultiConverter_Init (&DAC_Sync_Config, 0, 0); DAC MTS Settings DAC_Sync_Config.Tiles = 0x3; Tiles to sync bit-mask: DAC tiles 0 and 1 DAC_Sync_Config.Target_Latency = 296; latency - measured value (280 + 16 margin)

// Initialize //
// Target

SYSREF Signal Requirements
The SYSREF signal is the timing reference for the system and must therefore be handled correctly to ensure it does not degrade the synchronization. This signal has the following requirements.
1. The SYSREF signal must be a high-quality, free-running, low-jitter square wave, to allow it to be captured consistently by the analog sample clock.
2. The SYSREF frequency must meet the following requirements: a. If synchronizing RF-ADC and RF-DAC tiles with different sample frequencies, the frequency must be an integer submultiple of: GCD(DAC_Sample_Rate/16, ADC_Sample_Rate/16)

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b. SYSREF must also be an integer submultiple of all PL clocks that sample it. This is to ensure the periodic SYSREF is always sampled synchronously.
c. Less than 10 MHz. 3. SYSREF must be safely captured by the PL, before passing to the core:
a. Setup/hold of PL_SysRef to PL_clock must be handled as part of the user design. b. Clock generation on the PCB can be used to facilitate this, if supported. 4. Analog SYSREF and PL SYSREF must be the same frequency and be synchronized in phase at the Zynq� UltraScale+TM RFSoC package pin inputs. 5. For MTS synchronization, which covers both divider phase sync and FIFO latency sync, the analog SYSREF and PL SYSREF must be a continuous clock for the duration of the MTS procedure. It can be either AC-coupled or DC-coupled. The SYSREF signals can be shut down after the completion of the MTS procedure. Note that they should be turned on and stabilized prior to the MTS function call. 6. If analog SYSREF is being used to synchronize the phase of the DUC/DDC mixer NCOs across multiple Zynq� UltraScale+TM RFSoCs, then it must be DC-coupled with the ability to generate single or multiple pulse waveforms.
Related Information Example SYSREF Frequency Calculation PL SYSREF Capture
Example SYSREF Frequency Calculation ADCSampleRate = 3.93216 GHz
DACSampleRate = 4.91520 GHz
GCD(ADCSampleRate/16 , DACSampleRate/16) = 61.44 MHz
Integer Sub - Multiple AND < 10 MHz = 7.68 MHz
These equations generate a SYSREF frequency that satisfies the requirements of the RFADC/RF-DAC internal clocking. The SYSREF signal is also being captured synchronously by the PL; because of this, the SYSREF frequency must also be a submultiple of the PL clock driving the IP interfaces or any other clock interacting with the PL SYSREF.

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PL SYSREF Capture
To guarantee effective synchronization between tiles, it is important to reliably capture the PL SYSREF input in the device logic. The PL SYSREF and PL clock inputs must be differential signals that obey the clock and banking rules for the device. The PL clock input must be on a dedicated clock pin. The AXI4-Stream clocks for the Zynq� UltraScale+TM RF Data Converter core must be generated from the PL clock input and not from the clock outputs from the core itself. The following figure shows an example PL SYSREF capture circuit where the RF-ADC and RF-DAC are operating at the same AXI4-Stream clock frequency.

PL_SYSREF_P PL_SYSREF_N

Figure 83: Example PL SYSREF Capture

IBUFDS

RF Data Converter IP Core
user_sysref_adc user_sysref_dac

PL_CLK_P PL_CLK_N

IBUFDS BUFG

mX_axis_aclk

sX_axis_aclk
X22866-051319
The report_datasheet command can be used in the Vivado� IDE to calculate the required setup and hold times for the PL SYSREF input at the device pins. The following figure shows an example calculation for a -1 speed grade device with a 500 MHz PL clock.
Figure 84: Setup and Hold Report

Table 56: Setup and Hold Report

Reference Clock
pl_clk
pl_clk

Input Port
pl_sysref_n pl_sysref_p

Setup (ns) to Clk (Edge)
0.965 (r) 0.965 (r)

Hold (ns) to Clk (Edge)
0.285 (r) 0.285 (r)

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In the example above, the PL SYSREF must be delayed to arrive at least 0.285 ns after the rising edge of the PL clock to ensure the hold requirement is met. The delay must be added externally to the device. For each new design, or when the design is changed, the report_datasheet step should be run to reevaluate the setup and hold requirements. If the RF-ADC and RF-DAC are operating at different AXI4-Stream clock frequencies, the circuit shown in the following figure can be used to capture PL SYSREF.

Figure 85: Example PL SYSREF Capture for Different Clock Rates
RF Data Converter IP Core

user_sysref_adc

PL_SYSREF_P PL_SYSREF_N

IBUFDS

user_sysref_dac

PL_CLK_P PL_CLK_N

IBUFDS BUFG

CLKOUT
MMCM (ADC) CLKINCLKFB CLKFBIN
BUFG
CLKOUT MMCM (DAC) CLKINCLKFB CLKFBIN

BUFG BUFG

mX_axis_aclk sX_axis_aclk

BUFG

X22830-050919

Here, clock network de-skew MMCMs are used to divide down the frequency of the PL clock to the required rates. The RF-ADC and RF-DAC AXI4-Stream clocks must be common sub-multiples of the PL clock. In addition, the PL SYSREF frequency must be a common sub-multiple of all the clocks in the system.

Digital Feature Synchronization
After the synchronization is complete, a common state for the clocking is shared between all tiles. The same synchronization infrastructure can also be used by the digital datapath features using Dynamic Update Events.

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One example of this is the NCOs that make up the fine mixer features in the DDC and DUC chains. The NCO settings can be applied at the exact same moment across multiple tiles and multiple Zynq UltraScale+ RFSoCs using SYSREF. Each NCO supports the dynamic setting of frequency and phase with the changes being applied on a SYSREF or other update event. Similarly, there is an option to reset the phase of the NCO on a SYSREF or other update event. For a single-tile synchronization, the tile event can be used to synchronize the NCOs within a tile. For multiple tile synchronization, SYSREF events should be used.
Related Information Dynamic Update Events
Analog Synchronization
Analog SYSREF Capture/Receive
The receiver of the analog SYSREF in Tile228 (RF-DAC tile 0) is designed to capture a rising edge at the input pins and generate a sync pulse that gets distributed internally in a balanced way to all RF-DAC and RF-ADC tiles for the MTS function and the dynamic update event triggering function. The MTS function requires a continuous analog SYSREF clock that generates a continuous sequence of sync pulses during the duration of the MTS procedural call. The Dynamic Update event trigger function, on the other hand, only uses the first detected rising edge after the event is armed (an event update being requested). The arming, which is done using a corresponding API function call, should complete without seeing any sync pulses generated. Otherwise, some blocks will be latched in with the new update value while other blocks do not. As a result, the sequencing of events and the analog SYSREF waveform must adhere to the following guidance for the proper operation of each of the two functions. To simplify the implementation of some clocking designs, an API function call, XRFdc_sysrefConfig, is made available to enable and disable the analog SYSREF receiver, providing a way to gap the SYSREF sync pulses. Note that this API function is not a timed function, and therefore does not easily sync across multiple devices. As a result, theAPI XRFdc_sysrefConfig is not meant to be used solely to synchronize the first rising edge of the SYSREF across multiple devices.
Analog SYSREF AC- and DC-Coupling
The analog SYSREF supports both AC- and DC-coupling (see the UltraScale Architecture PCB Design User Guide (UG583) for electrical characteristic requirements). In AC-coupled mode, the analog SYSREF receiver is sensitive to noise glitches during the OFF state of the output analog SYSREF clock and during the initial turning on of the clock. During these times the receiver unpredictability generates sync pulse due to the glitches. Therefore you must allow the clock to stabilize prior to enabling the SYSREF receiver to avoid incorrect triggering of events.

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Operating in DC-coupled mode has the potential to avoid these glitch states if the analog SYSREF transmitter stays in a known logic state when it is OFF. Clock outputs that have a pulse function, such as the TI LMK04826 clock device, have the ability to predictably generate pulses on demand. This is required if a dynamic update event using the analog SYSREF is required across multiple devices; the same rising edge is required at all of the devices that are armed for an update.
MTS Sequencing
Sequence for AC- or DC-Coupling on Analog SYSREF for Single or Multiple Devices � Enable PL SYSREF and analog SYSREF clocks in continuous clock mode � Wait for clocks to stabilize, typically in the order of microseconds, depending on what clock
device is used. � Enable the analog SYSREF receiver with the API command � Run RF-ADC and/or RF-DAC MTS API functions as described in previous example code � Wait for completion of API return value � Disable the analog SYSREF receiver with the API command � Disable PL SYSREF and analog SYSREF clocks at the clock device
Figure 86: AC- or DC-Coupling on Analog SYSREF for Single or Multiple Devices

Dynamic Update Event Trigger Using SYSREF for Single Device with AC- or DC-Coupling
� Disable the analog SYSREF receiver with the API command � Run all API commands for event update request (such as NCO reset); this is the arming
process � Wait for successful return of API calls to make sure all register writes have been completed � Enable the analog SYSREF clock in continuous mode � Wait for clock to be stabilized � Enable the analog SYSREF receiver with the API command � Wait long enough to ensure a rising edge has been detected, at this point the update would
commence. � Disable the analog SYSREF receiver with the API command

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� Disable the analog SYSREF clock Figure 87: Dynamic Update Event Trigger using SYSREF for Single Device with AC- or DC-Coupling

Dynamic Update Event Trigger Using SYSREF for Multiple Devices with DC-Coupling
DC-coupling and a pulse SYSREF clock are required
� Program the clock generator device to use pulse SYSREF mode; place in idle state (no pulses being generated)
� Wait for analog coupling to be stabilized � Enable the analog SYSREF receiver for all devices involved (there should be no pulse detected
at this point) � Run all API command for event update request (such as NCO reset) for all tiles and devices;
this is the arming process � Wait for successful return of API calls to make sure all register writes have been completed � Issue a single synchronized pulse from the analog SYSREF to all devices involved. � Wait long enough to ensure a rising edge has been detected; at this point the update starts. � Disable the analog SYSREF receiver with the API command
Figure 88: Dynamic Update Event Trigger Using SYSREF for Multiple Devices with DCCoupling

Automatic Gain Control Systems
Automatic gain control (AGC) is commonly used in RF-ADC applications where the dynamic range of the input can vary considerably. It provides a way of using the input range of the RFADC and maximizing Signal-to-Noise ratio (SNR), while at the same time offering the flexibility to respond to varying signal amplitudes.
AGC systems consist of the following components:
� Variable Gain Amplifier (VGA)

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� RF-ADC
� Signal amplitude monitoring
� AGC Algorithm / Decision logic
� Digital gain compensation
The Zynq� UltraScale+TM RFSoC RF-ADC channels allow the implementation of custom AGC solutions by integrating the signal amplitude monitoring and compensation features into the RFADC tiles. These features can be used in conjunction with an external VGA and AGC logic embedded in the FPGA PL. This is shown in the following figure.

RFSoC Device

Figure 89: Automatic Gain Control

PCB Signals

Analog Gain

User Design/ Programmable Logic Signals

AGC Algorithm

Digital Gain

RF Data Converter IP Core RF-ADCs

Threshold

adc00_over_threshold0 clk_adc0 adc00_pl_event adc00_over_threshold1
m00_axis

Data Path 1

ADC1

Reg

Data Path 0

ADC0

Threshold

ADC_X0Y0

VIN_01_P/N

VGA

Processor

AXI Interface

X19531-082819
This figure shows an example AGC application. The signal amplitude monitoring is implemented within each RF-ADC channel using the threshold feature. This feature provides two thresholds that can be programmed per RF-ADC channel. When a threshold level is violated, this is indicated directly in the PL, thereby bypassing any latency within the datapath.
A sample high level operation of the AGC is as follows:
1. At system initialization, the threshold levels and modes are set by the RFdc driver API. 2. If a threshold level is violated:
a. The real-time over threshold output flags assert.

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b. The PL-based AGC algorithm makes a decision and computes the new VGA gain and compensation gain
c. Gain values are programmed into the VGA and digital compensation logic d. adcXY_pl_event is asserted by the AGC logic. e. Thresholds are cleared.
Related Information Threshold Settings Threshold RFdc Driver API Commands Digital Gain Compensation Clearing Threshold Flags
Digital Gain Compensation
As the VGA adjusts the analog signal level, it might be required to compensate this digitally after the RF-ADC to keep the overall signal-level constant. To minimize the disturbance on the received signal, it is possible to align the gain adjustments so that the digital compensation is applied at the same point in time relative to the analog gain being applied. This application moment must account for relative latencies between the propagation of the analog gain change through the VGA, RF-ADC and digital logic. There are a number of ways this gain adjustment and synchronized application can be achieved.
Compensation Using QMC Gain
The QMC Gain features are built into the RF-ADC tiles and offer a programmable gain between 0 and 2.0, with 16-bit output resolution. Using this, the 12-bit RF-ADC output signal can be placed to give a flexible dynamic range through the digital datapath. The application moment of the gain value in the QMC block can be controlled by the adcXY_pl_event signal. This signal is controlled directly from the user design in the PL and should be delayed to account for the latency required by the external VGA adjustment and RF-ADC conversion. When using this option, the sticky threshold outputs can be auto-cleared when the gain is applied.
Related Information Clearing Threshold Flags
Compensation Using PL Gain
For wider dynamic range digital gain adjustment, the FPGA PL can be used. Similarly to the QMC Gain method, the latency through the VGA, RF-ADC and datapath should be used to delay the application of the gain change in the PL. After the PL gain change, the thresholds can be cleared by using the RFdc driver API, or by issuing a adcXY_pl_event.

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Determining Gain-Change Latency
To apply the digital gain compensation at the correct moment, the relative latency between the propagation of the gain change through the analog path must be aligned with the propagation of the digital gain update code through the digital path. Because the external VGA communication and response time is specific to the user application, these relative delays must be measured insystem. For the digital path, each tile has a dedicated input called adcXY_pl_event that can be used to apply a setting, such as gain, at a deterministic time. To determine the relative delay between the digital and analog paths, a test signal of constant amplitude should be applied during the design phase, and digital and analog gain adjustments applied. Looking at the output data, the delta time between the digital and analog gain application moments can be observed as a hump/through in the output signal amplitude. This delta time should be added to the adcXY_pl_event assertion in by counting periods of the RF-ADC output clock (clk_adcX). Using this predetermined delay during normal operation of the design ensures that the gain application moments are aligned.
The following figure illustrates the stages of responding to a threshold event for an example AGC application. The middle region of the diagram represents signals related to the analog/VGA path, while the lower region represents signals related to the digital path.
Figure 90: Example AGC Threshold Event Response

As shown in this figure, the AGC update is initiated by the assertion of a threshold. In response to this the AGC algorithm in the PL calculates gain adjustments to be made for both the analog and digital paths. The propagation of the delay through the analog path is shown by the VGA update write, VGA settling response, and RF-ADC latency. The propagation delay through the digital path is shown by the API write of the new gain value, denoted by TRFdc_API, and the adcXY_pl_event assertion, denoted by TDelta_Latency. TDelta_Latency is chosen by the user application to match the Digital and Analog latencies. After the digital gain update has been applied, the threshold can be automatically deasserted, if the Auto-Clear function is enabled.

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It should be noted that the application of the QMC gain using the RFdc driver API might incur some driver overhead. In applications where this latency is undesirable, the PL Digital Gain Compensation method can be used.
Related Information Digital Gain Compensation
NCO Frequency Hopping
When the RF-ADC or RF-DAC mixer with numerically controlled oscillator is in use the frequency of the NCO can be tuned in real-time using the RF-ADC and RF-DAC real-time NCO interfaces. This section describes the operation of these interfaces.
When carrying out frequency hopping information on the required phase and frequency of the NCO must be conveyed to the IP core. The NCO frequency is set by the 48-bit twos complement signed number nco_freq. The nco_freq signal has a range of -Fs/2 to Fs/2. The maximum positive value (0x7FFF_FFFF_FFFF) results in a NCO frequency of Fs/2 while the maximum negative value (0x8000_0000_0000) produces a NCO frequency of -Fs/2.
If the required NCO frequency is higher than Fs/2 the frequency should be folded down into the -Fs/2 to Fs/2 range by subtracting the sampling frequency as required. Similarly, for large negative frequencies, the sampling frequency is added to the required NCO frequency until it is in range. For NCO frequencies in even Nyquist zones the resultant frequency should be negated. For RF-ADCs where calibration mode 1 is selected the mixer frequency should be reduced by Fs/2.
The phase information is carried by nco_phase. This is a phase offset added to the output of the NCO accumulator. The nco_phase input is an 18-bit twos complement signed number in the range -180 to 180 degrees. The maximum positive value (0x1_FFFF) gives a phase shift of 180 degrees. The maximum negative value (0x2_0000) gives a phase shift of -180 degrees.
The nco_update_en signal is used to determine what frequency and phase words are modified on an update event. The bits in the nco_update_en vector are set High to modify the following bits of the frequency and phase numbers.
� Bit 5: Reset the phase offset to 0
� Bit 4: nco_phase[17:16] � Bit 3: nco_phase[15:0] � Bit 2: nco_freq[47:32] � Bit 1: nco_freq[31:16] � Bit 0: nco_freq[15:0]

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Chapter 4: Designing with the Core
For example, if only bits 2:0 of nco_update_en are set High, only the frequency value is changed on an update event.
Single Converter Mode
When multi-tile synchronization (MTS) is not supported all the converters are independent. An NCO update state machine is instantiated for each converter. Before a NCO update can be performed the event source must be set to Tile. See Dynamic Update Events for more information on setting the event source. The process for updating the NCO settings is shown below.
Figure 91: Single Converter NCO Update

1. Firstly the required frequency, phase, and phase reset values are set on the real-time NCO signal interface ports.
2. The update enable port is set to indicate which converter register values are to be updated. The more values that are required to be updated increases T2 (the time to write the NCO values into the converter registers). Each register write takes five s_axi_aclk cycles.
3. A pulse is then sent to the update request port. If the IP state machine has completed the start up process the access to the requested NCO registers commences. T1 indicates the wait time for the IP state machine to complete.
4. The busy signal remains High until the NCO update process is complete. The frequency, phase, and phase reset values should be held until the busy signal is deasserted.
Related Information Dynamic Update Events

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Chapter 4: Designing with the Core
Multi-Tile Mode
When multi-tile synchronization is selected the SYSREF is used to update the NCO settings. This ensures that the mixer updates are synchronized across all the converters. Before an NCO update can take place the event source must be set to SYSREF. See Dynamic Update Events (link below) for more information on setting the event source.
Because the SYSREF is used to trigger the NCO update it should be gated to ensure that an edge does not arrive during the update process. If the SYSREF is gated externally the IP core works in the same way as the single converter case. The SYSREF should be turned off before the NCO update process is started and re-enabled when the IP has deasserted the busy signal.
Alternatively, the IP core can gate the SYSREF signal internally. This is achieved by writing to registers in RF-DAC 228. In this case, the process for updating the NCO settings is shown below.
Figure 92: Multi-tile NCO Update

� First, the required NCO frequency, phase, and phase reset values are set on the Real-Time NCO signal interface ports for all NCO channels that are to be updated.
� dac0_sysref_int_gating is driven High to indicate to the IP that it should gate the SYSREF internally.
� The update enable port is set to indicate which register values are to be updated. The more values that are required to be updated increases T2 (the time to write the NCO values into the converter registers). Each register write takes 5 s_axi_aclk cycles.
� A pulse is sent to the update request port. If the IP state machine has completed the start up process the access to the requested NCO registers starts. T1 indicates the wait time for the IP state machine to complete.
� Bit 1 of the dac0_nco_update_busy output is asserted when the SYSREF has been stopped. The other converters in the multi-tile synchronization group wait for this output to go High before requesting their NCO updates through the Real-Time NCO signal interface.

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Chapter 4: Designing with the Core
� When all the update busy outputs for the converter in the multi-tile synchronization group are Low, with the exception of dac0_nco_update_busy[1], the NCO register writes have been completed.
� A pulse is sent to the dac0_sysref_int_reenable port to indicate that SYSREF can be restarted. The process is complete when dac0_nco_update_busy[1] goes Low. T3 indicates the time taken for the process to complete from the start of the initial register updates. This time depends on the SYSREF frequency, the number of register values to be updated, and the number of converters in the tile synchronization group.
Related Information Dynamic Update Events Real-Time NCO Signal Interface Ports for RF-DACs Real-Time NCO Signal Interface Ports for Quad RF-ADCs Real-Time NCO Signal Interface Ports for Dual RF-ADCs

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Chapter 5: Design Flow Steps
Chapter 5

Design Flow Steps
This section describes customizing and generating the core, constraining the core, and the simulation, synthesis, and implementation steps that are specific to this IP core. More detailed information about the standard Vivado� design flows and the IP integrator can be found in the following Vivado Design Suite user guides:
� Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) � Vivado Design Suite User Guide: Designing with IP (UG896) � Vivado Design Suite User Guide: Getting Started (UG910) � Vivado Design Suite User Guide: Logic Simulation (UG900)
Customizing and Generating the Core
This section includes information about using Xilinx� tools to customize and generate the core in the Vivado� Design Suite.
If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:
1. Select the IP from the IP catalog. 2. Double-click the selected IP or select the Customize IP command from the toolbar or right-
click menu.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).
Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.

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Basic Tab

Chapter 5: Design Flow Steps Figure 93: Basic Tab

Presets
The Vivado� IDE IP core configuration screen provides a method of saving and applying preset configurations. From the Presets menu, several fixed configurations are available.
� 4x4: ADC:R2C DAC C2R: 4 RF-ADCs and 4 RF-DACs enabled. The RF-ADCs are configured in real to I/Q mode. The RF-DACs are configured in I/Q to real mode.
� 8x8: ADC:R2C DAC C2R: 8 RF-ADCs and 8 RF-DACs enabled. The RF-ADCs are configured in real to I/Q mode. The RF-DACs are configured in I/Q to real mode.
� R2C/C2R Multi x2: ADC:R2C Multi x 2 DAC: C2R Multi x2. The RF-ADCs are configured in x2 multi-band using real to I/Q data. The RF-DACs are configured in x2 multi-band using IQ to real data.

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� C2C Multi x2: ADC:C2C Multi x 2 DAC: C2C Multi x2. The RF-ADCs are configured in x2 multi-band using IQ to I/Q data. The RF-DACs are configured in x2 multi-band using I/Q to I/Q data.
� C2R Multi 2x2: DAC: C2R Multi 2x2. 2x2 multi-band on a single RF-DAC tile using I/Q to real data.
� C2C Multi 2x2: DAC: C2C Multi 2x2. 2x2 multi-band on a single RF-DAC tile using I/Q to I/Q data.
� C2R Multi x4: DAC: C2C Multi x4. 1x4 multi-band on a single RF-DAC tile using I/Q to real data.
In addition to these fixed presets, the current configuration can be saved by selecting Save Configuration... from the Presets menu. After the configuration is saved it can be reloaded at any time by selecting Apply Configuration....
Component Name
The component name is used as the base name of the output files generated for the core. Names must begin with a letter and must be composed from these characters: a through z, 0 through 9 and "_" (underscore).
System Configuration
Configuration Preset: This menu allows the user to select from a list of predefined configurations to avoid having to enter all settings manually.
Converter Setup
The converter setup menu provides advanced and simple options for setting up the IP configuration.
� Advanced: All tiles are independently configurable.
� Simple: The user is presented with the configuration options for a single RF-ADC and RF-DAC tile. After the tile is set up the RF-ADC configuration can be applied to any RF-ADC in the device by selecting the tile from the given tile list. Similarly the RF-DAC configuration can be applied to any RF-DAC tile.
It is possible to change from simple to advanced setup without losing configuration information. However, it is not possible to change from advanced to simple.

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RF-ADC Tab

Chapter 5: Design Flow Steps Figure 94: RF-ADC Tab

RF-ADC Tile Configuration
These parameters are common to every RF-ADC in a tile.
� Link Coupling: This determines if the input signal to the RF-ADC is AC or DC-coupled. Typical applications use AC-coupling, but for certain applications such as Zero IF, DC-coupling is also supported. When DC link coupling mode is selected, the common mode voltage of the external driving circuit needs to be aligned with the RF-ADC internal common mode voltage by using the externally driven VCM pin (see RF-ADC Analog Input)). The VCM pin is only enabled for DC-coupling mode, and can be left floating if AC-coupling mode is chosen.
� Converter Band Mode: Each RF-ADC can operate either independently (single band mode) or together with other converters in the tile (multi-band mode). The following modes are available for the RF-ADC.
� Single: The converter operates in single band mode.

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� Multi x2 (pair 01): The output from ADC 0 is routed through the DDC channel of both ADC 0 and 1. Digital settings, such as mixer mode and type, are available for each DDC channel. In Quad devices the other two RF-ADCs in the tile operate in single band mode.
� Multi x2 (pair 23): This option is similar to the previous mode. Here the output from ADC 2 is routed to DDC channels 2 and 3. The other converters in the tile operate in single band mode. This option is only available on Quad devices.
� Multi x2 (both): A combination of the previous multi-band options. The data from ADC 0 provides the input for DDC channels 0 and 1. The data from ADC 2 supplies DDC channels 2 and 3. This option is only available on Quad devices.
� Multi x4: All DDC channels in the tile are supplied from ADC 0. This option is only available on Quad devices.
� Multi Tile Sync: When enabled, the tile is included in a multi-tile synchronization group. Tile 224 must be enabled and present in the group along with converter 0 of the tile being confiigured to enable this option. A reference clock must also be provided to tile 224. See Multi-Tile Synchronization for details.
Related Information RF-ADC Analog Input Multi-Tile Synchronization RF-ADC Multi-Band Operation
RF-ADC Converter Configuration
� Enable ADC: Select if the selected converter within the selected tile is enabled. Valid values are True and False.
� Invert Q Output: This parameter is configurable only when I/Q output data is selected and the fine mixer is enabled. When set, the quadrature output of the mixer is negated. This allows -Q data to be generated.
� Dither: Selects if dither is enabled for the selected tile. Dither should be enabled unless the sample rate is under 0.75 times the maximum sampling rate for the RF-ADC.
� Bypass Background Calibration: If checked the background calibration logic is implemented in the IP core. The driver can be used to download a fixed set of calibration coefficients to the IP. This option is only available in Real input to Real output mode with further restrictions on the decimation mode and the number of samples per AXI4-Stream cycle.
Data Settings
� Digital Output Data: Sets the data type of the selected converter within the selected tile. The parameter is only configurable when the converter is enabled. Valid values are Real and I/Q. When converter 0 is set to I/Q, converter 1 must also be enabled and when converter 2 is set to I/Q, converter 3 must also be enabled; otherwise the configuration is invalid.

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� Decimation Mode: Sets the decimation values of the selected converter within the selected tile. The parameter is only configurable when the converter is enabled. Values 1x, 2x, 4x, 8x are selected from a drop-down menu. When the converter is not enabled, the value is Off.
� Samples per AXI4-Stream Word: Sets the number of words per cycle. This parameter is configurable when the specific converter has been enabled. Valid values are between 1 and 8 and can be selected using a drop-down list. The range of values is limited depending on the selected sample rate to keep the AXI4-Stream clock within the specification. The required AXI4-Stream clock is an input to the IP core and its value, based on the selected bus width, is displayed.
Mixer Settings
� Mixer Type: Set the type of Mixer to be used. Valid options are bypassed, coarse, and fine. Selectable options depend on the selection in the converter Digital Output Data field.
� Mixer Mode: Set the mixer mode of the selected converter within the selected tile. The parameter is only configurable when the converter is enabled. The choice of mixer modes depends on the mixer type and the format of the digital output data selected. When real data is output the mixer is bypassed. When I/Q data is output the mixer can be set to Real to I/Q or I/Q to I/Q.
� Coarse Mixer Frequency: Sets the frequency of the coarse mixer. The parameter is configurable only when coarse is selected as the Mixer Type. Valid options are Fs/2, Fs/4 and Fs/4.
� Fine Mixer Frequency: Sets the frequency of the fine mixer. The parameter is only available when fine is selected as the mixer type. The valid range of frequencies is -10 GHz to 10 GHz.
� Fine Mixer Phase: Sets the phase of the fine mixer. The parameter is only available when fine is selected as the mixer type. Valid range is -180 to 180.
Analog Settings
� Nyquist Zone: Selects between even and odd Nyquist zone operation.
� Calibration Mode: Selects between different calibration optimization schemes depending on the features of the input signals. Mode 1 is optimal for input frequencies Fsamp/2(Nyquist) +/10%. Otherwise, use Mode 2.

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RF-DAC Tab

Chapter 5: Design Flow Steps Figure 95: RF-DAC Tab

RF-DAC Tile Configuration
These parameters are common to every RF-DAC in a tile.
� Converter Band Mode: Each RF-DAC can operate either independently (single band mode) or together with other converters in the tile (multi-band mode). The following modes are available for the RF-DAC. See RF-DAC Multi-Band Operation. � Single: The converter operates in single band mode. � Multi x2 (pair 01): DUC channels 0 and 1 drive the input of DAC0. Digital settings, such as mixer mode and type, are available for each DUC channel. The other two RF-DACs in the tile operate in single band mode. � Multi x2 (pair 23): This option is similar to the previous mode. Here DAC2 is driven by DUC channels 2 and 3. The other converters in the tile operate in single band mode.

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� Multi x2 (both): A combination of the previous multi-band options. DAC0 converts the data from DUC channels 0 and 1. DAC2 is driven by DUC channels 2 and 3.
� Multi x4: DAC0 accepts data from all the DUC channels in the tile.
� Multi Tile Sync: When enabled the tile is included in a multi-tile synchronization group. Tile 228 must be enabled and present in the group along with converter 0 of the tile being confiigured to enable this option. A reference clock must also be provided to tile 228. See Multi-Tile Synchronization for details.
Related Information Multi-Tile Synchronization RF-DAC Multi-Band Operation
RF-DAC Converter Configuration
� Enable DAC: Select if the selected converter within the selected tile is enabled. Valid values are True and False.
� Invert Q Output: When enabled, the Q output of the converter is inverted. This parameter is configurable only when I/Q output data is selected. A follow-on analog mixer must implement a subtraction, I x cos(f) - Q x sin(f) so the option to provide a -Q signal (negative quadrature) is provided so that the external mixer can perform the addition, I x cos(f) + (-Q)sin(f)
� Inverse Sinc Filter: Select whether the inverse sinc filter is enabled or not. The parameter is only configurable when the converter is enabled. Valid values are True and False.
Data Settings � Analog Output Data: Sets the data type of the selected converter within the selected tile. The
parameter is only configurable when the converter is enabled. Valid values are Real and I/Q. When converter 0 is set to I/Q, converter 1 must also be enabled and when converter 2 is set to I/Q, converter 3 must also be enabled; otherwise the configuration is invalid.
� Interpolation Mode: Sets the interpolation values of the current converter. The parameter is only configurable when the converter is enabled. Values 1x, 2x, 4x, 8x are selected from a drop-down menu. When the converter is not enabled, the value is Off.
� Samples per AXI4-Stream Word: Sets the number of words per cycle. This parameter is configurable when at least one converter in the tile is enabled. Valid values are between 1 and 16 and can be selected using a drop-down list. The range of values is limited depending on the selected sample rate in order to keep the AXI4-Stream clock within the specification. The required AXI4-Stream clock is an input to the IP core and its value, based on the selected bus width, is displayed.
Mixer Settings � Mixer Type: Sets the type of Mixer to be used. Valid options are bypassed, coarse, and fine.
Selectable options depend on the selection in the converter Analog Output Data field.

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� Mixer Mode: Sets the mixer mode of the selected converter within the selected tile. The parameter is only configurable when the converter is enabled. The choice of mixer modes depends on the selected Mixer Type and the format of the analog output data selected. When real data is output the mixer can be set to I/Q -> Real or Bypass and when I/Q data is output the mixer can be set to I/Q to I/Q.
� Coarse Mixer Frequency: Sets the frequency of the coarse mixer. The parameter is configurable only when coarse is selected as the mixer type. Valid options are: Fs/2, Fs/4 and Fs/4.
� Fine Mixer Frequency: Sets the frequency of the fine mixer. This parameter is only available when fine is selected as the mixer type. The valid range of frequencies is -10 GHz to 10 GHz.
� Fine Mixer Phase: Sets the phase of the fine mixer. The parameter is only available when fine is selected as the mixer type. Valid range is -180 to 180 degrees.
Analog Settings � Nyquist Zone: Selects between even and odd Nyquist zone operation. � Decoder Mode: The RF-DAC decoder can be optimized for low signal-to-noise ratio or for
high linearity.
System Clocking Tab
Figure 96: System Clocking Tab

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Chapter 5: Design Flow Steps
The System Clocking tab is present when the Converter Setup is set to Advanced. This screen enables the user to enter information on the system sample rates and clock frequencies.When the Converter Setup is set to Simple this information is entered on the main RF-ADC and RFDAC tabs.
AXI4-Lite Interface Configuration
� AXI Clock Frequency (MHz): The core requires information on the frequency of the AXI4-Lite clock input to ensure the correct timing of the power-on sequence of the RF-ADC and RFDAC blocks. The speed of the clock should be entered in MHz. The maximum allowed frequency is given by the DRP clock maximum frequency specified in the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
Tile Clock Settings
The sampling rate and clock frequencies are set in this section.These settings are shared by each converter in a tile.
� Sampling Rate (GSPS): Sets the sampling rate for each tile. It is configurable when at least one of the converters in the tile is enabled. Valid values depend on the selected device and package. These values can be found in Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
� Max Fs (GSPS): The maximum sample rate for each tile is given for reference.
� PLL: Selects whether the PLL within the tile is being used or bypassed. It is configurable when at least one of the converters in the tile is enabled. If it is required to dynamically reconfigure the PLL using the RFdc driver API, the PLL must be enabled in the Vivado� IDE. Valid values are True or False.
� Reference Clock (MHz): Sets the frequency of the clock input for the tile. It is configurable when the PLL and at least one of the converters in the tile is enabled. Its values depend on the sampling rate of the tile. A drop-down list of values based on the sample rate selected is presented. It is recommended to use the correct reference frequency at the PLL input for optimum phase noise performance. See the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) for the FREF specification.
� PLL Reference Clock: Sets the frequency of the PLL input clock if the PLL is enabled for a specific tile.
� Reference Clock Divider: Sets the divider on the PLL reference clock input.
� Fabric Clock (MHz): This is the frequency of the clock to be supplied on the AXI4-Stream clock input for the selected tile. The required frequency is determined by the sample rate and the settings in the Converter Configuration. Because all AXI4-Stream ports on a tile share a common AXI4-Stream clock all converter configurations on a tile must require the same clock frequency.

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Chapter 5: Design Flow Steps

� Clock Out (MHz): Sets the frequency of the output clock on the tile. This clock can be used to drive the AXI4-Stream clock inputs. It is configurable when at least one of the converters in the tile is enabled. The values depend on the sampling rate of the tile. A drop-down list of values based on the sample rate selected is presented.
Related Information RF-ADC Converter Configuration RF-DAC Converter Configuration
PLL Summary Settings
The PLL Summary gives information on the frequency and divider settings of the enabled PLLs. The following information is displayed: � Vco(MHz): The frequency of the voltage controlled oscillator. � Fb Div: The feedback divider setting � M: The output divider setting � R: The reference clock divider setting

Advanced Tab

Figure 97: Advanced Tab

� RF Analyzer: The RF Analyzer provides a hardware test system. The system contains data stimulus and capture blocks configured for this instance of the IP core.

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Chapter 5: Design Flow Steps
� PL Clock Frequency (MHz): If multi-tile sync is selected then the user must supply a PL clock and PL SYSREF to the system. For acurate SYSREF capture the frequency must be a common integer multiple of the RF-ADC and RF-DAC AXI4-Stream clocks.
� Analog Clock Detection: Not available for customer use.
Related Information Multi-Tile Synchronization RF Analyzer
RF-ADC
� Enable Real Time Ports: Enables the RF-ADC Over Threshold, Over Voltage, Over Range and pl_event ports.
� Enable Cal Freeze Ports: Enables the calibration freeze logic. Calibration is frozen when the analog input is over voltage or the relevant int_cal_freeze input is asserted.
� Auto Cal Freeze: If this option is selected, the calibration is frozen when the analog input is over range, in addition to the manual calibration freeze process.
� Enable Real Time NCO Ports: The frequency and phase of the mixer NCO in the DDC can be modified in real time. Selecting this option enables the real time NCO interface for the RFADC. The operation of this interface is described in NCO Frequency Hopping.
RF-DAC
� Enable Real Time Ports: Enables the RF-DAC Fast Shutdown and pl_event ports.
� Enable Real Time NCO Ports: The frequency and phase of the mixer NCO in the DUC can be modified in real time. Selecting this option enables the real time NCO interface for the RFDAC. The operation of this interface is described in NCO Frequency Hopping.
� Output Current: Select between 20 mA and 32 mA RF-DAC output current. In 20 mA mode, DAC_AVTT is equal to 2.5V. In 32 mA mode, DAC_AVTT is equal to 3.0V.
Related Information Real-Time Signal Interface Ports for RF-DACs Real-Time Signal Interface Ports for Dual RF-ADCs Real-Time Signal Interface Ports for Quad RF-ADCs RF-DAC Output Current Mode NCO Frequency Hopping
User Parameters
The following table shows the relationship between the fields in the Vivado� IDE and the user parameters (which can be viewed in the Tcl Console).

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Chapter 5: Design Flow Steps

Table 57: User Parameters

Vivado IDE Parameter/Value

User Parameter/Value

RF-ADC ADC Tile n Enable1

C_ADCn_Enable

ADC Tile n Feedback Divider

C_ADCn_FBDIV

ADC Tile n Fabric Frequency ADC Tile n Outclk Frequency

C_ADCn_Fabric_Freq C_ADCn_Outclk_Freq

ADC Tile n PLL Enable

C_ADCn_PLL_Enable

ADC Tile n Refclk Frequency ADC Tile n Sampling Rate

C_ADCn_Refclk_Freq C_ADCn_Sampling_Rate

ADC Tile n Link Coupling

C_ADCn_Link_Coupling

ADC Tile n Multi Tile Sync ADC Tile n Multiband setting

C_ADCn_Multi_Tile_Sync C_ADCn_Band

ADC Tile n Reference Clock input divider
ADC Tile n Clock Source

C_ADCn_Refclk_Div C_ADCn_Clock_Source

ADC Tile n Clock Distribution ADC Tile y Converter z Data Type2 ADC Tile y Converter z Data Width

C_ADCn_Clock_Dist C_ADC_Data_Typeyz C_ADC_Data_Widthyz

ADC Tile y Converter z Decimation Mode
ADC Tile y Converter z Mixer Mode

C_ADC_Decimation_Modeyz C_ADC_Mixer_Modeyz

ADC Tile y Converter z Nyquist Zone

C_ADC_Nyquistyz

ADC Tile y Converter z Calibration Optimization

C_ADC_CalOpt_Modeyz

ADC Tile y Converter z Enable

C_ADC_Sliceyz_Enable

ADC Tile y Converter z Mixer Type
ADC Tile y Converter z Fine Mixer Frequency

C_ADC_Mixer_Typeyz C_ADC_NCO_Freqyz

ADC Tile y Converter z Fine Mixer Phase C_ADC_NCO_Phaseyz

ADC Tile y Converter z Coarse Mixer Phase

C_ADC_Coarse_Mixer_Freqyz

ADC Tile y Converter z Invert Q Output C_ADC_Neg_Quadratureyz

ADC Tile y Converter z Dither

C_ADC_Ditheryz

ADC Tile y Converter z background calibration bypass
Common

C_ADC_Bypass_BG_Calyz

AXI Clock Frequency

C_Axiclk_Freq

Component Name Converter_Setup

C_COMPONENT_NAME C_Converter_Setup

Enable RF-ADC Real-Time Signals

C_ADC_RTS

Enable RF-ADC NCO Real-Time Signals Enable RF-DAC Real-Time Signals

C_ADC_NCO_RTS C_DAC_RTS

Default Value
0 10 0 250 FALSE 2000 2 0 FALSE 0 1
n 0 0 8 1
2 1 0
TRUE 3 0.0
0 0
FALSE TRUE FALSE
100 usp_rf_data_converter_0 Advanced FALSE FALSE FALSE

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Chapter 5: Design Flow Steps

Table 57: User Parameters (cont'd)

Vivado IDE Parameter/Value

User Parameter/Value

Enable RF-DAC NCO Real-Time Signals C_DAC_NCO_RTS

Enable RF-ADC Calibration Freeze

C_Calibration_Freeze

Enable RF-ADC Auto Calibration Freeze C_Auto_Calibration_Freeze

DAC Output Current

C_DAC_Output_Current

RF-DAC

DAC Tile n Enable

C_DACn_Enable

DAC Tile n Feedback Divider

C_DACn_FBDIV

DAC Tile n Fabric Frequency

C_DACn_Fabric_Freq

DAC Tile n Outclk Frequency

C_DACn_Outclk_Freq

DAC Tile n PLL Enable

C_DACn_PLL_Enable

DAC Tile n Refclk Frequency

C_DACn_Refclk_Freq

DAC Tile n reference clock input divider C_DAC_Refclk_Div

DAC Tile n Sampling Rate

C_DACn_Sampling_Rate

DAC Tile n Multi Tile Sync

C_DACn_Multi_Tile_Sync

DAC Tile n Multiband configuration mode

C_DACn_Mode

DAC Tile n Output Current

C_DACn_VOP

DAC Tile n Clock source

C_DACn_Clock_Source

DAC Tile n Clock distribution

C_DACn_Clock_Distr

DAC Tile y Converter z Data Type

C_DAC_Data_Typeyz

DAC Tile y Converter z Data Width

C_DAC_Data_Widthyz

DAC Tile y Converter z Interpolation Mode

C_DAC_Interpolation_Modeyz

DAC Tile y Converter z Decoder Mode C_DAC_Decoder_Modeyz

DAC Tile y Converter z Invsinc Ctrl

C_DAC_Invsinc_Ctrlyz

DAC Tile y Converter z Mixer Mode

C_DAC_Mixer_Modeyz

DAC Tile y Converter z Nyquist Zone

C_DAC_Nyquistyz

DAC Tile y Converter z Enable

C_DAC_Sliceyz_Enable

DAC Tile y Converter z Mixer Type

C_DAC_Mixer_Typeyz

DAC Tile y Converter z Fine Mixer Frequency

C_DAC_NCO_Freqyz

DAC Tile y Converter z Fine Mixer Phase C_DAC_NCO_Phaseyz

DAC Tile y Converter z Coarse Mixer Phase

C_DAC_Coarse_Mixer_Freqyz

DAC Tile y Converter z Invert Q Output C_DAC_Neg_Quadratureyz

Notes: 1. n = 0 to 3. 2. y = 0 to 3, z = 0 to 3.

FALSE FALSE FALSE 0

Default Value

0 10 0 400 FALSE 6400 1 6.5 FALSE 0
20 n+4 0 0 16 0
0 FALSE 2 1 FALSE 3 0.0
0 0
FALSE

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Chapter 5: Design Flow Steps
Output Generation
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896).
Simulation
Simulation is supported using Mentor Graphics Questa Advanced Simulator in the Vivado� Design Suite. For comprehensive information about Vivado simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900). The RF-ADC and RF-DAC blocks have bit-accurate real number simulation models. This means that each of the datapath features can be simulated and the related analog signals observed. Related Information Example Design
Synthesis and Implementation
For details about synthesis and implementation, see the Vivado Design Suite User Guide: Designing with IP (UG896).

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Chapter 6
Example Design
The following figure shows the example design that is provided with the core. Figure 98: Example Design

The complete example design can be opened as a separate project by right-clicking the core in the project hierarchy after it has been customized using the IP catalog. Right-click the <component_name>.xci file in the Design Sources hierarchy in the Sources window and select Open IP Example Design. This opens a new Vivado� IP integrator project in a new window with a complete RF Data Converter IP example design.
The Zynq� UltraScale+TM RFSoC RF Data Converter example design consists of the following:
� An instance of the Zynq� UltraScale+TM RF Data Converter IP core
� Data stimulus block for RF-DAC input
� Data capture block for RF-ADC output
� Smartconnect for AXI4-Lite addressing of the design
� An example device-level wrapper containing BUFGs

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Chapter 6: Example Design

RF-ADC Data Capture Block
The RF-ADC data capture block enables the capture of the data converted by the RF-ADC(s) in the Zynq� UltraScale+TM RF Data Converter core.
The data from each enabled AXI4-Stream output on the Zynq� UltraScale+TM RF Data Converter is stored in a separate channel in the data capture block. As each converter can have up to four AXI4-Stream interfaces, there are a maximum of 16 channels present in the data capture block. The enabled AXI4-Stream interfaces are mapped into consecutive channels starting with ADC0. The storage in each channel consists of 128 kbits of block RAM.
The address map for the data capture block is shown below.

Table 58: RF-ADC Data Capture Address Map

Address

0x0000_0000

Memory ID code

0x0000_0004

Start Data

0x0000_0008

Channel Enable

0x0000_0010 - 0x0000_004C

Samples to capture (channel 0 to 15)

0x0000_4000 - 0x0000_7FFC Channel 0 memory

0x0000_8000 - 0x0000_BFFC Channel 1 memory

0x0000_C000 - 0x0000_FFFC Channel 2 memory

Access Type
RO
R/W
R/W
R/W R/W R/W R/W

Description
Memory Information Bit 31. High. Signaling a data capture block. Bits 30:24. Number of channels in the data capture block. Bits 23:0. Total memory size of the data capture block.
Starts the data capture. Bits 31:1. Reserved Bit 0. Writing a 1 to this register starts the storage of data in to the block RAM. This register remains high until the capture has been completed.
Enables each channel. Bits 31:16. Reserved Bits 15:0. Channel enable. Each bit controls one channel (bit n controlling channel n). The channel should be enabled before starting a capture. When the capture is complete the channel should be disabled before the next capture can start.
The number of samples to capture from the RF-ADC. One address per channel.
Channel 0 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 1 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 2 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample

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Chapter 6: Example Design

Table 58: RF-ADC Data Capture Address Map (cont'd)

Address

0x0001_0000 - 0x0001_3FFC Channel 3 memory

0x0001_4000 - 0x0001_7FFC Channel 4 memory

0x0001_8000 - 0x0001_BFFC Channel 5 memory

0x0001_C000 - 0x0001_FFFC Channel 6 memory

0x0002_0000 - 0x0002_3FFC Channel 7 memory

0x0002_4000 - 0x0002_7FFC Channel 8 memory

0x0002_8000 - 0x0002_BFFC Channel 9 memory

0x0002_C000 - 0x0002_FFFC Channel 10 memory

0x0003_0000 - 0x0003_3FFC Channel 11 memory

0x0003_4000 - 0x0003_7FFC Channel 12 memory

0x0003_8000 - 0x0003_BFFC Channel 13 memory

0x0003_C000 - 0x0003_FFFC Channel 14 memory

0x0004_0000 - 0x0004_3FFC Channel 15 memory

Access Type
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Description
Channel 3 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 4 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 5 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 6 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 7 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 8 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 9 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 10 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 11 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 12 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 13 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 14 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 15 data capture Bits 31:16. Odd data sample Bits 15:0. Even data sample

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Chapter 6: Example Design

RF-DAC Data Stimulus Block
The RF-DAC data stimulus block consists of a 128 kbits block RAM that can be loaded with samples which are then sent to the RF-DAC (s) in the Zynq� UltraScale+TM RF Data Converter core.
Each channel in the stimulus block drives an AXI4-Stream on the Zynq� UltraScale+TM RF Data Converter IP core. As each converter can have up to four AXI4-Stream interfaces, there are a maximum of 16 channels in the data stimulus block. Each enabled AXI4-Stream interface is mapped into consecutive channels starting with DAC0.
The address map for the data stimulus block is shown below.

Table 59: RF-DAC Data Stimulus Address Map

Address

0x0000_0000

Memory ID code

0x0000_0004

Start data

0x0000_0008

Channel enable

0x0000_0010 - 0x0000_004C Samples to generate 0x0000_4000 - 0x0000_7FFC Channel 0 memory 0x0000_8000 - 0x0000_BFFC Channel 1 memory

Access Type
RO
R/W
R/W R/W R/W R/W

Description
Memory Information Bit 31. Low. Signaling a data stimulus block. Bits 30:24. Number of channels in the data stimulus block. Bits 23:0. Total memory size of the data stimulus block.
Starts the transmission of data Bits 31:1. Reserved Bit 0. Start data (self clearing). Setting this bit high starts the transmission of the data stored in memory to the RFDAC. To stop transmission the channel is disabled using the channel enable register.
Enables each channel. Bits 31:16. Reserved Bits 15:0. Channel enable. Each bit controls one channel (bit n controlling channel n). The channel should be enabled before issuing a start data command. To stop the test the channel should be disabled.
The number of samples to transmit before wrapping around to the beginning of the sequence. One address per channel.
Channel 0 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 1 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample

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Chapter 6: Example Design

Table 59: RF-DAC Data Stimulus Address Map (cont'd)

Address

0x0000_C000 - 0x0000_FFFC Channel 2 memory

0x0001_0000 - 0x0001_3FFC Channel 3 memory

0x0001_4000 - 0x0001_7FFC Channel 4 memory

0x0001_8000 - 0x0001_BFFC Channel 5 memory

0x0001_C000 - 0x0001_FFFC Channel 6 memory

0x0002_0000 - 0x0002_3FFC Channel 7 memory

0x0002_4000 - 0x0002_7FFC Channel 8 memory

0x0002_8000 - 0x0002_BFFC Channel 9 memory

0x0002_C000 - 0x0002_FFFC Channel 10 memory

0x0003_0000 - 0x0003_3FFC Channel 11 memory

0x0003_4000 - 0x0003_7FFC Channel 12 memory

0x0003_8000 - 0x0003_BFFC Channel 13 memory

0x0003_C000 - 0x0003_FFFC Channel 14 memory

0x0004_0000 - 0x0004_3FFC Channel 15 memory

Access Type
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Description
Channel 2 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 3 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 4 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 5 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 6 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 7 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 8 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 9 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 10 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 11 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 12 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 13 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 14 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample
Channel 15 data stimulus Bits 31:16. Odd data sample Bits 15:0. Even data sample

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Chapter 6: Example Design

Digital Data Format
Each word interface to the RF-DAC and RF-ADC is 16 bits wide, even though the RF-DAC resolution is 14 bits and the RF-ADC 12 bits. The word is in twos complement format, giving the range shown in the following table.
The RF-ADC and RF-DAC hex values are displayed appropriately left shifted to align to the input most significant bit.

Table 60: RF-ADC and RF-DAC Word Interface

Max positive Zero Min negative

AXI4-Stream I/F

Hex

Dec

0x7FFF

32767

0x0001

0x0000

0xFFFF

-1

0x8000

-32768

RF-ADC Resolution (<<4)

Hex

Dec

0x7FF0

2047

0x0010

0x0000

0xFFF0

-1

0x8000

-2048

RF-DAC Resolution (<<2)

Hex

Dec

0x7FFC

8191

0x0004

0x0000

0xFFFC

-1

0x8000

-8192

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Chapter 7

Test Bench
This chapter contains information about the test bench provided in the Vivado� Design Suite.
For information on setting up and running simulations in the Vivado Design Suite, see the Vivado Design Suite User Guide: Logic Simulation (UG900). Zynq� UltraScale+TM RFSoC RF Data Converter core supports behavioral simulation along with post-implementation functional simulation.
The following figure shows the structure of the Zynq� UltraScale+TM RFSoC RF Data Converter test bench.
Figure 99: Demonstration Test Bench

Sequencer

AXI4-Lite Decode Smartconnect

REAL/force probes
Clock Gen

DAC Source
ADC Sink

Stimulus Block
Capture Block

RF Data Converter
IP

<component_name>_example_design

DAC Sink
ADC Source

demo_tb
X21611-092519
The following blocks are present in the demonstration test bench. � Clock Generator: This block produces the required AXI4-Lite and AXI4-Stream clocks for the
design. � DAC Source: This block outputs a series of samples representing a tone at a set frequency.
These samples are written in to the data stimulus block in the example design. � DAC Sink: This block performs a FFT on the RF-DAC analog output. It checks that the input
tone appears at the expected frequency.

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Chapter 7: Test Bench
� ADC Source: The RF-ADC analog inputs are driven by a tone at a set frequency. If the mixers in the RF-ADC are enabled the tone is mixed with a sine wave before being input to the RFADC . The mixer in the ADC source block is set to run at the negative of the mixer frequency in the converter.
� ADC Sink: This block performs a FFT on the RF-ADC digital output. It checks that the input tone appears at the expected frequency.
� Sequencer: This block is responsible for managing accesses to the test bench components through an AXI4-Lite interface. It contains examples of how to access and configure the basic test harness.
The sequencer in the demonstration test bench runs through the following stages. At some stages the Power-up sequence state machine is stopped despite the sequence not being complete. This is in order to speed up the simulation. It is not essential to follow the steps in the demonstration test bench for simulation of the converters. The state machine can be allowed to run from start to finish without being restarted.
1. The test bench components are set up. The sources and sinks are set up with the configuration information from the IP core. The power-up sequence state machine is started and the initial configuration stage is completed.
2. Sine waves from the DAC Source block are written into the memory in the stimulus block for each enabled channel.
3. Some of the configuration registers are then changed to help speed up the simulation. For example, in the RF-ADC the dither is disabled. This allows the calibration step in the powerup sequence to be skipped, saving simulation time. When the fine mixers are enabled they can also be reprogrammed at this point to minimize any spectral leakage in the FFT.
4. The RF-DACs and RF-ADCs are then run to the stage before the converter clocks are released to the digital section of the converters. The simulation is slowed when the converter clocks are enabled and stopping the state machine at this stage helps to reduce run time.
5. The RF-DACs are fully powered up and the transmission of data from the stimulus block is started.
6. The sequencer waits for the DAC Sink blocks for each RF-DAC output to report their FFT results. The RF-DACs are then powered down.
7. The RF-ADCs are powered up to the start of the foreground calibration stage and data capture is started for each of the enabled channels.
8. When data capture is complete the RF-ADCs are powered down. The sequencer then reads the captured data back and sends it to the ADC Sink block.
9. The sequencer waits for the ADC Sink blocks for each enabled channel to report their FFT results. The simulation then completes.
When Fs/2 mixing is enabled output similar to that in the following figures should be visible on the analog I/O.

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Figure 100: RF-ADC Analog I/O

Chapter 7: Test Bench

Figure 101: RF-DAC Analog I/O

Analog Signaling
The RF-DAC and RF-ADC analog I/O are differential and are driven as shown in the following figure in the test bench.
Figure 102: Test Bench Analog Signaling
V_P

VCM

VFS/2

VCM

V_N GND

X18809-072817

The internal RF-DAC and RF-ADC model analog functions using Real Number models. In the Verilog example design these must be passed as 64-bit wires, using force and hierarchical assignments to set and read the values.

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Chapter 7: Test Bench
The simulated transfer function uses a full-scale voltage swing (VFS) of 1.14V and a common mode voltage (VCM) of 1.25V for the RF-ADC. For the actual full-scale input voltage range see the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926). A code excerpt from the demo_tb.v file is shown below. This is generated when you generate the example design. This can be used as a guide to show how to drive and read data into RF-DAC and RF-ADC primitives.
//---------------------------------------------------------------------------// Force the analog signals. //---------------------------------------------------------------------------`ifndef DO_NOT_USE_RFAMS_REAL_SIGNAL_FORCE // RF-ADC real adc00_p; real adc00_n; always @ (*) begin
// Map the RF-ADC signals to top level adc00_p = $bitstoreal(adc_source.vout_00_p); adc00_n = $bitstoreal(adc_source.vout_00_n); // Force the RF-ADC analog input force DUT.i_rf_dut_block.inst.rf_dut_rf_wrapper_i.rx0_u_adc.SIP_HSADC_INST.VIN0_P = adc00_p; force DUT.i_rf_dut_block.inst.rf_dut_rf_wrapper_i.rx0_u_adc.SIP_HSADC_INST.VIN0_N = adc00_n; end // RF-DAC real dac00_p; real dac00_n; always @ (*) begin // Map the RF-DAC signals to the top level dac00_p = DUT.i_rf_dut_block.inst.rf_dut_rf_wrapper_i.tx0_u_dac.SIP_HSDAC_INST.VOUT0_P ; dac00_n = DUT.i_rf_dut_block.inst.rf_dut_rf_wrapper_i.tx0_u_dac.SIP_HSDAC_INST.VOUT0_N ; // force the RF-DAC output onto the RF-DAC sink force dac_sink.vin_00_p = $realtobits(dac00_p); force dac_sink.vin_00_n = $realtobits(dac00_n); end `endif

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Chapter 7: Test Bench
The code excerpt below shows analog data loopback from the RF-DAC to the RF-ADC on a Gen 1 device. Care must be taken to map the RF-DAC analog data output to within the correct range for the RF-ADC data input. real dac00_p; real dac00_n; always @ (*) begin
dac00_p = DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf _data_converter_0_0_rf_wrapper_i.tx0_u_dac.SIP_HSDAC_INST.VOUT0_P;
dac00_n = DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf _data_converter_0_0_rf_wrapper_i.tx0_u_dac.SIP_HSDAC_INST.VOUT0_N;
// Force the ADC analog input force DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf _data_converter_0_0_rf_wrapper_i.rx0_u_adc.SIP_HSADC_INST.VIN_I01_P = 1.25 + (dac00_p-dac00_n); // ADC VCM = 1.25V force DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf _data_converter_0_0_rf_wrapper_i.rx0_u_adc.SIP_HSADC_INST.VIN_I01_N = 1.25 - (dac00_p-dac00_n); // ADC VCM = 1.25V end

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Upgrading

Appendix A: Upgrading
Appendix A

Changes from V2.1 to V2.2

Parameter Changes
The RF-ADC and RF-DAC output divide parameters have been removed from version 2.2 of the IP. These are set internally by the IP.

Table 61: Parameter Changes

Parameter1

Upgrade Action

ADCX_Outdiv

Do not set manually. Allow the IP to set this parameter.

DACX_Outdiv

Do not set manually. Allow the IP to set this parameter.

Notes: 1. X refers to the location of the tile in the converter column.

Changes from V2.0 to V2.1

Port Changes
In version 2.1 a new port has been added in the Debug group. The powerup_state output will be asserted when the POR Finite State Machine detects an error in the power-up sequence.

Table 62: Port Changes

Port1

Direction

adcX_powerup_state

Out

Leave open

dacX_powerup_state

Out

Leave open

Notes: 1. X refers to the location of the tile in the converter column

Upgrade Action

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Appendix A: Upgrading

Parameter Changes
The mapping of the decimation and interpolation settings into the C_ADC_Decimation_Mode and C_DAC_Interpolation_Mode IP variables has been changed in version 2.1. The changes are shown below.

Table 63: Decimation and Interpolation Parameter Mode Changes

Parameter1

Version 2.0

Version 2.1

C_ADC_Decimation_ModeXY

� 0 = Decimation off � 1 = Decimation x1 � 2 = Decimation x2 � 3 = Decimation x4 � 4 = Decimation x8

� 0 = Decimation off � 1 = Decimation x1 � 2 = Decimation x2 � 4 = Decimation x4 � 8 = Decimation x8

C_DAC_Interpolation_ModeXY

� 0 = Interpolation off � 1 = Interpolation x1 � 2 = Interpolation x2 � 3 = Interpolation x4 � 4 = Interpolation x8

� 0 = Interpolation off � 1 = Interpolation x1 � 2 = Interpolation x2 � 4 = Interpolation x4 � 8 = Interpolation x8

Notes:
1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC/DDC block in the tile (0 to 3).

A new option has been added to the C_ADC_Mixer_Type and C_DAC_Mixer_Type parameters, The mixers can now be set to "Off" in addition to the previously defined settings.

Table 64: Mixer Type Parameter Changes

Parameter1

Version 2.0

Version 2.1

C_ADC_Mixer_TypeXY

� 0 = Bypassed � 1 = Coarse � 2 = Fine

� 0 = Bypassed � 1 = Coarse � 2 = Fine � 3 = Off

C_DAC_Mixer_TypeXY

� 0 = Bypassed � 1 = Coarse � 2 = Fine

� 0 = Bypassed � 1 = Coarse � 2 = Fine � 3 = Off

Notes:
1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC/DDC block in the tile (0 to 3).

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Appendix A: Upgrading

Changes from V1.2 to V2.0

Port Changes
Separate RF-ADC and RF-DAC versions of the user_sysref port have been added. This change affects cores with multi-tile synchronization enabled.

Table 65: Port Changes in Version 2.0

Port
user_sysref_adc user_sysref_dac

Direction
In In

Upgrade Action
Connect to user_sysref, if required Connect to user_sysref, if required

Changes from V1.1 to V1.2

Port Changes
When the RF-ADC real-time signals are enabled the ports in the following table have been added.

Table 66: Port Changes in Version 1.2

Port

Direction

Upgrade Action

2 GSPS RF-ADC1

adcXZ_over_range

Out

Leave open

adcXZ_over_voltage

Out

Leave open

4 GSPS RF-ADC2

adcX_ZZ_over_range

Out

Leave open

adcX_ZZ_over_voltage

Out

Leave open

Notes:
1. X refers to the location of the tile in the converter column. Z refers to the location of the RF-ADC in the tile (0 to 3).
2. X refers to the location of the tile in the converter column. ZZ is either 01 (the lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile)

When the RF-ADC real-time signals are enabled the ports in the following table have been renamed.

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Appendix A: Upgrading

Table 67: Ports Renamed in Version 1.2

Port

Previous Name (v1.1) Direction

Upgrade Action

2 GSPS RF-ADC1

adcXZ_over_threshold1

adcXY_over_threshold1

Out

Leave open

adcXZ_over_threshold2

adcXY_over_threshold2

Out

Leave open

4 GSPS RF-ADC2

adcX_ZZ_over_threshold1

adcXY_over_threshold1

Out

Leave open

adcX_ZZ_over_threshold2

adcXY_over_threshold2

Out

Leave open

Notes:
1. X refers to the location of the tile in the converter column. Y refers to the location of the DDC block in the tile (0 to 3). Z refers to the location of the RF-ADC in the tile (0 to 3).
2. X refers to the location of the tile in the converter column. Y refers to the location of the DDC block in the tile (0 to 3). ZZ is either 01 (the lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).

Parameter Changes There are no parameter changes.

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Appendix B: Debugging
Appendix B
Debugging
This appendix includes details about resources available on the Xilinx Support website and debugging tools.
Finding Help on Xilinx.com
To help in the design and debug process when using the core, the Xilinx Support web page contains key resources such as product documentation, release notes, answer records, information about known issues, and links for obtaining further product support. The Xilinx Community Forums are also available where members can learn, participate, share, and ask questions about Xilinx solutions.
Documentation
This product guide is the main document associated with the core. This guide, along with documentation related to all products that aid in the design process, can be found on the Xilinx Support web page or by using the Xilinx� Documentation Navigator. Download the Xilinx Documentation Navigator from the Downloads page. For more information about this tool and the features available, open the online help after installation.
Answer Records
Answer Records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a Xilinx product. Answer Records are created and maintained daily ensuring that users have access to the most accurate information available. Answer Records for this core can be located by using the Search Support box on the main Xilinx support web page. To maximize your search results, use keywords such as: � Product name � Tool message(s) � Summary of the issue encountered

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Appendix B: Debugging
A filter search is available after results are returned to further target the results.
Master Answer Record for the Core
AR 69907.
Technical Support
Xilinx provides technical support on the Xilinx Community Forums for this LogiCORETM IP product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support if you do any of the following: � Implement the solution in devices that are not defined in the documentation. � Customize the solution beyond that allowed in the product documentation. � Change any section of the design labeled DO NOT MODIFY. To ask questions, navigate to the Xilinx Community Forums.
Debug Tools
There are many tools available to address Zynq� UltraScale+TM RF Data Converter design issues. It is important to know which tools are useful for debugging various situations.
Vivado Design Suite Debug Feature
The Vivado� Design Suite debug feature inserts logic analyzer and virtual I/O cores directly into your design. The debug feature also allows you to set trigger conditions to capture application and integrated block port signals in hardware. Captured signals can then be analyzed. This feature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx� devices. The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including: � ILA 2.0 (and later versions) � VIO 2.0 (and later versions) See the Vivado Design Suite User Guide: Programming and Debugging (UG908).

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Appendix B: Debugging

Hardware Debug
Hardware issues can range from link bring-up to problems seen after hours of testing. This section provides debug steps for common issues. The Vivado� debug feature is a valuable resource to use in hardware debug. The signal names mentioned in the following individual sections can be probed using the debug feature for debugging the specific problems.
General Checks
Ensure that all the timing constraints for the core were properly incorporated from the example design and that all constraints were met during implementation.
� Does it work in post-place and route timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue. Ensure that all clock sources are active and clean.
� If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the locked port.
� If your outputs go to 0, check your licensing.

Interface Debug
AXI4-Lite Interfaces
Read from a register that does not have all 0s as a default to verify that the interface is functional. Output s_axi_arready asserts when the read address is valid, and output s_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:
� The s_axi_aclk and aclk inputs are connected and toggling. � The interface is not being held in reset, and s_axi_areset is an active-Low reset. � The interface is enabled, and s_axi_aclken is active-High (if used). � The main core clocks are toggling and that the enables are also asserted. � If the simulation has been run, verify in simulation and/or a debug feature capture that the
waveform is correct for accessing the AXI4-Lite interface.
AXI4-Stream Interfaces
If data is not being transmitted or received, check the following conditions:

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Appendix B: Debugging
� If transmit <interface_name>_tready is stuck Low following the <interface_name>_tvalid input being asserted, the core cannot send data.
� If the receive <interface_name>_tvalid is stuck Low, the core is not receiving data. � Check that the aclk inputs are connected and toggling. � Check that the AXI4-Stream waveforms are being followed. � Check core configuration.
Related Information Interfacing to the AXI4-Stream Interface

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
Appendix C
Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
Overview
The RFdc driver API functions for the Zynq� UltraScale+TM RFSoC RF Data Converter are described in this chapter. The same driver is used for both bare metal and Linux. The driver for both software platforms runs on the libmetal software layer provided by Xilinx. The driver is composed of the following files: � API
xrfdc.c: The user interface API functions are implemented in this file. xrfdc.h: The user interface API prototypes are provided in this file. The file provides
prototypes of the driver instance structure and all other structures used across the APIs. The file implements utility in-line functions to access various data in the driver and IP. xrfdc_mts.c: The multi-tile synchronization API functions are implemented in this file. xrfdc_mts.h: The multi-tile synchronization API prototypes are provided in this file. xrfdc_mixer.c: The mixer API functions are implemented in this file. xrfdc_clock.c: The clock related API functions are implemented in this file. xrfdc_mb.c: The multi-band API functions are implemented in this file. � Hardware Register Map xrfdc_hw.h: Definitions for the hardware register maps are provided in this file. The file also provides masks for various relevant fields for the Zynq UltraScale+ RFSoC register interface. � Interrupt Handling xrfdc_intr.c: Implements functions for the handling of various interrupts and errors from the IP core.

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver

Figure 103: Linux and Bare-metal Software Flow Block Diagram

Linux Flow

Bare-metal Flow

User App

User/Test App

XRFdc Driver

Atomics Locks Shmem Bus Libmetal IOMEM IRQ DMA Device Atomics Locks Shmem Bus Libmetal IOMEM IRQ DMA Device

UIO

Kernel

UIO

Hardware

X186756-037278187

About Libmetal
Libmetal is a Xilinx developed open source software stack that provides common user APIs to access devices, handle device interrupts, and request memory across the following operating environments:
� Linux user space (based on Userspace IO and Virtual Function IO support in the kernel)
� RTOS (with and without virtual memory)
� Bare-metal environments
The libmetal I/O region abstraction provides access to memory mapped I/O and shared memory regions. This includes primitives to read and write memory with ordering constraints and the ability to translate between physical and virtual addressing on systems that support virtual memory.

Data Structures
All the data structures used in the driver are defined in the xrfdc.h and xrfdc_mts.h files.

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
struct XRFdc
This is the instance structure for internal use. XRFdc_Config RFdc_Config; u32 IsReady; u32 ADC4GSPS; metal_phys_addr_t BaseAddr; struct metal_io_region *io; struct metal_device *device; XRFdc_DAC_Tile DAC_Tile[4]; XRFdc_ADC_Tile ADC_Tile[4]; XRFds_StatusHandler StatusHandler; void *CallBackRef; u8 UpdateMixerScale;
Description � XRFdc_Config RFdc_Config: Driver structure configuration. � u32 IsReady: This flag is used to indicate that the driver is ready. � u32 ADC4GSPS: This flag is used to indicate if RF-ADC is 4 GSPS. � metal_phys_addr_t BaseAddr: Base address. � struct metal_io_region: Libmetal IO structure. � struct metal_device *device: Libmetal device structure. � XRFdc_DAC_Tile DAC_Tile[4]: RF-DAC tile structure for four tiles. � XRFdc_ADC_Tile ADC_Tile[4]: RF-ADC tile structure for four tiles. � XRFds_StatusHandler StatusHandler: Event handler function. � void *CallBackRef: Callback reference for event handler. � u8 UpdateMixerScale: Set to 1 to overwrite mixer scale.
struct XRFdc_Config
This structure is for internal driver use (metal_phys_addr_t represents unsigned long). u32 DeviceId; metal_phys_addr_t BaseAddr; u32 ADCType; u32 MasterADCTile; u32 MasterDACTile; u32 ADCSysRefSource; u32 DACSysRefSource; XRFdc_DACTile_Config DACTile_Config[4]; XRFdc_ADCTile_Config ADCTile_Config[4];

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
Description � u32 ADCType: Quad RF-ADC part or Dual RF-ADC part. � u32 MasterADCTile: Corresponds to the C_ADC_Master IP parameter. � u32 MasterDACTile : Corresponds to the C_DAC_Master IP parameter. � u32 ADCSysRefSource : Corresponds to the C_ADC_Sysref_Source IP parameter. � u32 DACSysRefSource: Corresponds to the C_DAC_Sysref_Source IP parameter.
struct XRFdc_PLL_Settings
This structure is for internal driver use. u32 Enabled; double RefClkFreq; double SampleRate; u32 RefClkDivider; u32 FeedbackDivider; u32 OutputDivider; u32 FractionalMode; u64 FractionalData; u32 FractWidth;
Description � u32 Enabled: Indicates if the PLL is enabled (1) or disabled (0). � double RefClkFreq: Reference clock frequency (MHz). � double SampleRate: Sampling rate (GHz). � u32 RefClkDivider: Reference clock divider. � u32 FeedbackDivider: Feedback divider. � u32 OutputDivider: Output divider. � u32 FractionalMode: Fractional mode. Currently not supported. � u64 FractionalData: Fractional part of the feedback divider. Currently not supported. � u32 FractWidth: Fractional data width. Currently not supported.

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver

struct XRFdc_QMC_Settings
This structure is used to set or get the QMC settings.
u32 EnablePhase; u32 EnableGain; double GainCorrectionFactor; double PhaseCorrectionFactor; s32 OffsetCorrectionFactor; u32 EventSource;

Description � u32 EnablePhase: Indicates if phase is enabled (1) or disabled (0). � u32 EnableGain: Indicates if gain is enabled(1) or disabled (0). � double GainCorrectionFactor: Gain correction factor. Range: 0 to 2.0 (Exclusive). � double PhaseCorrectionFactor: Phase correction factor. Range: +/- 26.5 degrees (Exclusive). � s32 OffsetCorrectionFactor: Offset correction factor is adding a fixed LSB value to the
sampled signal. � u32 EventSource: Event source for QMC settings. XRFDC_EVNT_SRC_* represents valid
values.

Table 68: Valid Macros for EventSource
Macro
XRFDC_EVNT_SRC_IMMEDIATE XRFDC_EVNT_SRC_SLICE XRFDC_EVNT_SRC_TILE XRFDC_EVNT_SRC_SYSREF XRFDC_EVNT_SRC_MARKER XRFDC_EVNT_SRC_PL

Description
Update after register write Update using SLICE event source Update using TILE event source Update using SYSREF event source Update using MARKER event source Update using PL event source

struct XRFdc_CoarseDelay_Settings
This structure is used to set or get coarse delay settings. u32 CoarseDelay; u32 EventSource;
Description � u32 CoarseDelay: Coarse delay in the number of samples. Range: 0 to 7.

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� u32 EventSource: Event source for coarse delay settings. XRFDC_EVNT_SRC_* represents valid values. Note: See QMC_Settings structure for valid EventSource macros.
Related Information struct XRFdc_QMC_Settings

struct XRFdc_Mixer_Settings
This structure is used to set or get mixer settings.
double Freq; double PhaseOffset; u32 EventSource; u32 CoarseMixFreq; u32 MixerMode; u8 FineMixerScale; u8 MixerType;

Description � double Freq: NCO frequency. Range: -Fs to Fs (MHz). � double PhaseOffset: NCO phase offset. Range: -180 to 180 (Exclusive). � u32 EventSource: Event source for mixer settings. XRFDC_EVNT_SRC_* represents valid
values. Note: See QMC_Settings structure for valid EventSource macros � u32 CoarseMixFreq: Coarse mixer frequency. XRFDC_COARSE_MIX_* represents valid values.

Table 69: Valid Macros for CoarseMixFreq
Macro
XRFDC_COARSE_MIX_OFF XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_TWO XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_FOUR XRFDC_COARSE_MIX_MIN_SAMPLE_FREQ_BY_FOUR XRFDC_COARSE_MIX_BYPASS

Description
Coarse Mixer frequency is OFF Coarse Mixer frequency is Fs/2 Coarse Mixer frequency is Fs/4 Coarse Mixer frequency is -Fs/4 Coarse Mixer frequency is BYPASS

� u32 MixerMode: Mixer mode for fine or coarse mixer. XRFDC_MIXER_MODE_* represents valid values.

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver

Table 70: Valid Macros for MixerMode
Macro
XRFDC_MIXER_MODE_OFF XRFDC_MIXER_MODE_C2C XRFDC_MIXER_MODE_C2R XRFDC_MIXER_MODE_R2C

Description
Mixer mode is OFF (only for Fine Mixer) Mixer mode is Complex to Complex Mixer mode is Complex to Real Mixer mode is Real to Complex

� u8 FineMixerScale: NCO output scale. XRFDC_MIXER_SCALE_* represents valid values.

Table 71: Valid Macros for FineMixerScale

Macro
XRFDC_MIXER_SCALE_AUTO XRFDC_MIXER_SCALE_1P0 XRFDC_MIXER_SCALE_0P7

Description
Fine Mixer scale will be auto updated Fine Mixer Scale is set to 1.0 Fine Mixer Scale is set to 0.7

� u8 MixerType: Mixer Type indicates coarse or fine mixer. XRFDC_MIXER_TYPE_* represents valid values.

Table 72: Valid Macros for MixerType
Macro
XRFDC_MIXER_TYPE_COARSE XRFDC_MIXER_TYPE_FINE XRFDC_MIXER_TYPE_OFF XRFDC_MIXER_TYPE_DISABLED

Description
Mixer Type is Coarse Mixer Mixer Type is Fine Mixer The Mixer is Off The Mixer is permanently off (from hardware design)

Related Information struct XRFdc_QMC_Settings

struct XRFdc_Threshold_Settings
This structure is used to set or get RF-ADC threshold settings. u32 UpdateThreshold; u32 ThresholdMode[2]; u32 ThresholdAvgVal[2]; u32 ThresholdUnderVal[2]; u32 ThresholdOverVal[2];
Description � u32 UpdateThreshold: Selects which threshold to update. XRFDC_UPDATE_THRESHOLD_*
represents valid values.

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver

Table 73: Valid Macros for UpdateThreshold

Macro
XRFDC_UPDATE_THRESHOLD_0 XRFDC_UPDATE_THRESHOLD_1 XRFDC_UPDATE_THRESHOLD_BOTH

Description
Update for Threshold0 Update for Threshold1 Update for Threshold0 and Threshold1

� u32 ThresholdMode[2]: Entry 0 is for Threshold0 and 1 for Threshold1. Range: 0 to 3 (0-OFF, 1-sticky-over, 2-sticky-under and 3-hysteresis)
� u32 ThresholdAvgVal[2]: Threshold average value. Entry 0 is for Threshold0 and 1 for Threshold1.
� u32 ThresholdUnderVal[2]: Under threshold value. Entry 0 is for Threshold0 and 1 for Threshold1.
� u32 ThresholdOverVal[2]: Over threshold value. Entry 0 is for Threshold0 and 1 for Threshold1.

struct XRFdc_TileStatus
This structure is for internal driver use. u32 IsEnabled; u32 TileState; u8 BlockStatusMask; u32 PowerUpState; u32 PLLState;
Description � u32 IsEnabled: Indicates tile is enabled (1) or disabled (0). � u32 TileState: Indicates current tile state. � u8 BlockStatusMask: Bit mask for converter status. 1 indicates converter enable. � u32 PowerUpState: Indicates power-up status. � u32 PLLState: Indicates if PLL is locked or unlocked.

struct XRFdc_IPStatus
This structure is used to get the IP core status.
XRFdc_TileStatus DACTileStatus[4]; XRFdc_TileStatus ADCTileStatus[4]; u32 State;

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
Description � XRFdc_TileStatus DACTileStatus[4]: Tile status for four RF-DAC tiles. � XRFdc_TileStatus ADCTileStatus[4]: Tile status for four RF-ADC tiles. � u32 State: Not currently supported.
struct XRFdc_BlockStatus
This structure is used to get the status of RF-DACs or RF-ADCs. double SamplingFreq; u32 AnalogDataPathStatus; u32 DigitalDataPathStatus; u8 DataPathClocksStatus; u8 IsFIFOFlagsEnabled; u8 IsFIFOFlagsAsserted;
Description � double SamplingFreq: Sampling frequency. � u32 AnalogDataPathStatus:
� RF-ADC bit[0] Converter enable/disable.
� RF-DAC [3:0] Inverse sinc enable/disable. [7:4] Decoder mode.
� u32 DigitalDataPathStatus: � RF-ADC [3:0] FIFO status (enable/disable). [7:4] Decimation factor. [11:8] Mixer mode. � RF-DAC [3:0] FIFO status. [7:4] Interpolation factor. [11:8] Adder status. [15:12] Mixer mode.

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� u8 DataPathClocksStatus: Indicates if all required datapath clocks are enabled; 1 if all clocks enabled, 0 otherwise.
� u8 IsFIFOFlagsEnabled: FIFO flags enabled mask; 1 is enabled, otherwise 0. � u8 IsFIFOFlagsAsserted: FIFO flags asserted mask; 1 is enabled, otherwise 0.
struct XRFdc_DACBlock_AnalogDataPath_Config
This structure is for internal driver use. u32 BlockAvailable; u32 InvSyncEnable; u32 MixMode; u32 DecoderMode;
Description � u32 BlockAvailable: Corresponds to the C_DAC_Slice{xy}_Enable IP parameter. � u32 InvSyncEnable: Corresponds to the C_DAC_Invsinc_Ctrl{xy} IP parameter. � u32 MixMode: Corresponds to the C_DAC_Mixer_Mode{xy} IP parameter. � u32 DecoderMode: Corresponds to the C_DAC_Decoder_Mode{xy} IP parameter.
struct XRFdc_DACBlock_DigitalDataPath_Config
This structure is for internal driver use. u32 DataType; u32 DataWidth; u32 InterpolationMode; u32 FifoEnable; u32 AdderEnable; u32 MixerType;
Description � u32 DataType: Corresponds to the C_DAC_Data_Type{xy} IP parameter. � u32 DataWidth: Corresponds to the C_DAC_Data_Width{xy} IP parameter. � u32 InterpolationMode: Corresponds to the C_DAC_Interpolation_Mode{xy} IP
parameter. � u32 FifoEnable: Corresponds to the C_DAC_Fifo{xy} IP parameter. � u32 AdderEnable: Corresponds to the C_DAC_Adder{xy} IP parameter. � u32 MixerType: Corresponds to the C_DAC_Mixer_Type{xy} IP parameter.

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
struct XRFdc_ADCBlock_AnalogDataPath_Config
This structure is for internal driver use. u32 BlockAvailable; u32 MixMode;
Description � u32 BlockAvailable: Corresponds to the C_ADC_Slice{xy}_Enable IP parameter. � u32 MixMode: Corresponds to the C_ADC_Mixer_Mode{xy} IP parameter.
struct XRFdc_ADCBlock_DigitalDataPath_Config
This structure is for internal driver use. u32 DataType; u32 DataWidth; u32 DecimationMode; u32 FifoEnable; u32 MixerType;
Description � u32 DataType: Corresponds to the C_ADC_Data_Type{xy} IP parameter. � u32 DataWidth: Corresponds to the C_ADC_Data_Width{xy} IP parameter. � u32 DecimationMode: Corresponds to the C_ADC_Decimation_Mode{xy} IP parameter. � u32 FifoEnable: Corresponds to the C_ADC_Fifo{xy} IP parameter. � u32 MixerType: Corresponds to the C_ADC_Mixer_Type{xy} IP parameter.
struct XRFdc_DACTile_Config
This structure is for internal driver use. u32 Enable; u32 PLLEnable; double SamplingRate; double RefClkFreq; double FabClkFreq; u32 FeedbackDiv; u32 OutputDiv; u32 RefClkDiv; u32 MultibandConfig; XRFdc_DACBlock_AnalogDataPath_Config DACBlock_Analog_Config[4]; XRFdc_DACBlock_DigitalDataPath_Config DACBlock_Digital_Config[4];

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Description � u32 Enable: Corresponds to the C_DAC{x}_Enable IP parameter. � u32 PLLEnable: Corresponds to the C_DAC{x}_PLL_Enable IP parameter. � double SamplingRate: Corresponds to the C_DAC{x}_Sampling_Rate IP parameter. � double RefClkFreq: Corresponds to the C_DAC{x}_RefClk_Freq IP parameter. � double FabClkFreq: Corresponds to the C_DAC{x}_FabClk_Freq IP parameter. � u32 FeedbackDiv: Corresponds to the C_DAC{x}_FBDIV IP parameter. � u32 OutputDiv: Corresponds to the C_DAC{x}_OutDiv IP parameter. � u32 RefClkDiv: Corresponds to the C_DAC{x}_Refclk_Div IP parameter. � u32 MultibandConfig: Corresponds to the C_DAC{x}_Multiband IP parameter.
struct XRFdc_ADCTile_Config
This structure is for internal driver use. u32 Enable; u32 PLLEnable; double SamplingRate double RefClkFreq; double FabClkFreq; u32 FeedbackDiv; u32 OutputDiv; u32 RefClkDiv; u32 MultibandConfig; XRFdc_ADCBlock_AnalogDataPath_Config ADCBlock_AnalogConfig[4]; XRFdc_ADCBlock_DigitalDataPath_Config ADCBlock_Digital_Config[4];
Description � u32 Enable: Corresponds to the C_ADC{x}_Enable IP parameter. � u32 PLLEnable: Corresponds to the C_ADC{x}_PLL_Enable IP parameter. � double SamplingRate: Corresponds to the C_ADC{x}_Sampling_Rate IP parameter. � double RefClkFreq: Corresponds to the C_ADC{x}_RefClk_Freq IP parameter. � double FabClkFreq: Corresponds to the C_ADC{x}_FabClk_Freq IP parameter. � u32 FeedbackDiv: Corresponds to the C_ADC{x}_FBDIV IP parameter. � u32 OutputDiv: Corresponds to the C_ADC{x}_OutDiv IP parameter. � u32 RefClkDiv: Corresponds to the C_ADC{x}_Refclk_Div IP parameter.

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
� u32 MultibandConfig: Corresponds to the C_ADC{x}_Multiband IP parameter.
struct XRFdc_DACBlock_AnalogDataPath
This structure is for internal driver use. u32 Enabled; u32 MixedMode; double TerminationVoltage; double OutputCurrent; u32 InverseSincFilterEnable; u32 DecoderMode; void *FuncHandler; u32 NyquistZone; u8 AnalogPathEnabled; u8 AnalogPathAvailable; XRFdc_QMC_Settings QMC_Settings; XRFdc_CoarseDelay_Settings CoarseDelay_Settings;
Description � u32 Enabled: RF-DAC enable (1) or disable (0). � u32 MixedMode: Mixer mode. � double TerminationVoltage: Termination voltage. � double OutputCurrent: Output current. � u32 InverseSincFilterEnable: Inverse sinc filter enable (1) or disable (0). � u32 DecoderMode: Decoder mode. � void *FuncHandler: Function handler (currently not used in the driver). � u32 NyquistZone: RF-DAC Nyquist Zone. � u8 AnalogPathEnabled: Flag to indicate AnalogPath is enabled(1) or disabled(0). � u8 AnalogPathAvailable: Flag to indicate AnalogPath is available or not. � XRFdc_QMC_Settings QMC_Settings: QMC settings structure. � XRFdc_CoarseDelay_Settings CoarseDelay_Settings: CoarseDelay settings structure.

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver

struct XRFdc_DACBlock_DigitalDataPath
This structure is for internal driver use. u32 DataType; u32 DataWidth; int ConnectedIData; int ConnectedQData; u32 InterpolationFactor; u8 DigitalPathEnabled; u8 DigitalPathAvailable; XRFdc_Mixer_Settings Mixer_Settings;
Description � u32 DataType: Digital input datatype. � u32 DataWidth: Data width (samples per AXI4-Stream word). � int ConnectedIData: Data converter connected for I datapath. Valid values are 0-3 and -1. � int ConnectedQData: Data converter connected for Q datapath. Valid values are 0-3 and -1. � u32 InterpolationFactor: Interpolation factor. � u8 DigitalPathEnabled: Flag to indicate DataPath is enabled(1) or disabled(0). � u8 DigitalPathAvailable: Flag to indicate DigitalPath is available or not. � XRFdc_Mixer_Settings Mixer_Settings: Mixer Settings structure
struct XRFdc_ADCBlock_AnalogDataPath
This structure is for internal driver use. u32 Enabled; XRFdc_QMC_Settings QMC_Settings; XRFdc_CoarseDelay_Settings CoarseDelay_Settings; XRFdc_Threshold_Settings Threshold_Settings; u32 NyquistZone; u8 CalibrationMode; u8 AnalogPathEnabled; u8 AnalogPathAvailable;
Description � u32 Enabled: RF-ADC Enable (1) or Disable (0). � XRFdc_QMC_Settings QMC_Settings: QMC settings structure. � XRFdc_CoarseDelay_Settings CoarseDelay_Settings: Coarse delay settings structure. � XRFdc_Threshold_Settings Threshold_Settings: Threshold settings structure.

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� u32 NyquistZone: Nyquist zone. � u8 CalibrationMode: Calibration mode, set by the XRFdc_SetCalibrationMode API
function. � u8 AnalogPathEnabled: Flag to indicate AnalogPath is enabled(1) or disabled(0). � u8 AnalogPathAvailable: Flag to indicate AnalogPath is available or not.
struct XRFdc_ADCBlock_DigitalDataPath
This structure is for internal driver use. u32 DataType; u32 DataWidth; u32 DecimationFactor; int ConnectedIData; int ConnectedQData; u8 DigitalPathEnabled; u8 DigitalPathAvailable; XRFdc_Mixer_Settings Mixer_Settings;
Description � u32 DataType: Analog input data type. � u32 DataWidth: Data width (samples per AXI4-Stream word). � u32 DecimationFactor: Decimation factor. � int ConnectedIData: Data converter connected for I datapath. Valid values are 0-3 and -1. � int ConnectedQData: Data converter connected for Q datapath. Valid values are 0-3 and -1. � u8 DigitalPathEnabled: Flag to indicate DataPath is enabled(1) or disabled(0). � u8 DigitalPathAvailable: Flag to indicate DigitalPath is available or not. � XRFdc_Mixer_Settings Mixer_Settings: Mixer settings structure.
struct XRFdc_DAC_Tile
This structure is for internal driver use. u32 TileBaseAddr; u32 NumOfDACBlocks; XRFdc_PLL_Settings PLL_Settings; u8 MultibandConfig; XRFdc_DACBlock_AnalogDataPath DACBlock_Analog_Datapath[4]; XRFdc_DACBlock_DigitalDataPath DACBlock_Digital_Datapath[4];

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Description � u32 TileBaseAddr: Tile base address. � u32 NumOfDACBlocks: Number of RF-DACs enabled. � XRFdc_PLL_Settings PLL_Settings: PLL settings structure. � u8 MultibandConfig: Multi-band configuration for RF-DAC tile. � XRFdc_DACBlock_AnalogDataPath DACBlock_Analog_Datapath[4]:
DACBlock_AnalogDataPath structure for four RF-DACs. � XRFdc_DACBlock_DigitalDataPath DACBlock_Digital_Datapath[4]:
DACBlock_DigitalDataPath structure for four RF-DACs.
struct XRFdc_ADC_Tile
This structure is for internal driver use.
u32 TileBaseAddr; u32 NumOfADCBlocks; XRFdc_PLL_Settings PLL_Settings; u8 MultibandConfig; XRFdc_ADCBlock_AnalogDataPath ADCBlock_Analog_Datapath[4]; XRFdc_ADCBlock_DigitalDataPath ADCBlock_Digital_Datapath[4];
Description � u32 TileBaseAddr: Tile base address. � u32 NumOfADCBlocks: Number of RF-ADCs enabled. � XRFdc_PLL_Settings PLL_Settings: PLL settings structure. � u8 MultibandConfig: Multiband configuration for ADC Tile. � XRFdc_ADCBlock_AnalogDataPath ADCBlock_Analog_Datapath[4]:
ADCBlock_AnalogDataPath structure for four RF-ADCs. � XRFdc_ADCBlock_DigitalDataPath ADCBlock_Digital_Datapath[4]:
ADCBlock_DigitalDataPath structure for four RF-ADCs.

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struct XRFdc_MultiConverter_Sync_Config
This structure is used to configure the MTS algorithm. Indicated files can be configured in the code.
u32 RefTile; u32 Tiles; int Target_Latency; int Offset[4]; int Latency[4]; int Marker_Delay; int SysRef_Enable; XRFdc_MTS_DTC_Settings DTC_Set_PLL; XRFdc_MTS_DTC_Settings DTC_Set_T1;
Description � u32 RefTile: Reference tile (must be 0). � u32 Tiles: Bitmask indicating which tiles to align. BitX enables MTS for TileX. Tile0 must
always be enabled. � int Target_Latency: Sets the target relative latency. This is required to be set for multi-device
alignment, or deterministic latency use-cases. It is not required to be set for single-device alignment. � int Offset[4]: Status � indicates the value the interface data was delayed by to achieve alignment, per tile. � int Latency[4]: Status � indicates the measured relative-latency value of each tile. � int Marker_Delay: Marker delay is for internal use. � int SysRef_Enable: Set to 1 (default) to keep SYSREF capture enabled after MTS runs. Set to 0 to disable SYSREF capture.
struct XRFdc_MTS_Marker
This structure is for internal driver use. There are no user-configurable fields.
u32 Count[4]; u32 Loc[4];

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struct XRFdc_MTS_DTC_Settings
This structure is for internal driver use. There are no user-configurable fields. u32 RefTile; u32 IsPLL; int Target[4]; int Scan_Mode; int DTC_Code[4]; int Num_Windows[4]; int Max_Gap[4]; int Min_Gap[4]; int Max_Overlap[4];
struct XRFdc_Calibration_Coefficients
Generic calibration coefficient structure. u32 Coeff0; u32 Coeff1; u32 Coeff2; u32 Coeff3; u32 Coeff4; u32 Coeff5; u32 Coeff6; u32 Coeff7;
Description � u32 Coeff{N}: Nth Coefficient Note: Coeff{4-7} applies when chopping is active and is only relevant to the time skew calibration block.
struct XRFdc_Cal_Freeze_Settings
Generic calibration freezing settings structure u32 CalFrozen; u32 DisableFreezePin; u32 FreezeCalibration;
Description � u32 CalFrozen: Status that indicates that the calibration has been frozen � u32 DisableFreezePin: Disables the calibration freeze pin � u32 FreezeCalibration: Freezes the calibration using the freeze port

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
User API Functions
All user API functions are implemented in the source file xrfdc.c. The prototypes for these are provided in header file xrfdc.h. All driver API functions have InstancePtr as an argument. It is a pointer to the XRFdc structure that contains information about the base address, the structure pointing to RFdc default configurations, and structures for RF-ADC and RF-DAC tile configurations. The InstancePtr argument is initialized in the XRFdc_CfgInitialize API function. Call the XRFdc_CfgInitialize API function to initialize InstancePtr before calling any other functions.
XRFdc_CfgInitialize
Function Prototype u32 XRFdc_CfgInitialize(XRFdc *InstancePtr, XRFdc_Config *ConfigPtr);
Arguments � XRFdc * InstancePtr: Pointer to the driver instance. � XRFdc_Config *ConfigPtr: Pointer to the configuration structure.
Description This API function populates appropriate entries in the driver instance by copying relevant entries from the configuration structure. This function is required for any software interaction with the RFdc driver API and must be called first before using any other API functions.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_LookupConfig
Function Prototype XRFdc_Config *XRFdc_LookupConfig(u16 DeviceId);

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Arguments � u16 DeviceId: ID of the device whose configuration information is required.
Description This API function looks up the device configuration based on the unique ID of the device. A table contains the configuration information for each device in the system.
Return Value The function returns a pointer to the configuration found, or NULL if the specified device ID was not found.
XRFdc_RegisterMetal
Function Prototype u32 XRFdc_RegisterMetal(XRFdc *InstancePtr, u16 DeviceId, struct metal_device **DevicePtr);
Arguments � XRFdc * InstancePtr: Pointer to the driver instance. � u16 Device_Id: The device id for the driver. � struct metal_device **DevicePtr: Pointer to the metal device.
Description This API function registers RFDC with Libmetal
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_StartUp
Function Prototype u32 XRFdc_StartUp(XRFdc *InstancePtr, u32 Type, int Tile_Id);

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Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � int Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3 and -1 (for all tiles).
Description This API function restarts the tile as requested through Tile_Id. If -1 is passed as Tile_Id, the function restarts all the enabled tiles. Existing register settings are not lost or altered in the process.
Return Value XRFDC_SUCCESS XRFDC_FAILURE (returned when the tile is not enabled or available)
XRFdc_Shutdown
Function Prototype u32 XRFdc_Shutdown(XRFdc *InstancePtr, u32 Type, int Tile_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � int Tile_Id: Valid values are 0-3 and -1 (for all tiles).
Description This API function stops the tile as requested through Tile_Id. If -1 is passed as Tile_Id, the function stops all the enabled tiles. The existing register settings are not cleared. Note: This is a common API function for RF-ADC and RF-DAC tiles.
Return Value XRFDC_SUCCESS XRFDC_FAILURE (returned when the tile is not enabled or available)

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XRFdc_Reset
Function Prototype u32 XRFdc_Reset(XRFdc *InstancePtr, u32 Type, int Tile_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � int Tile_Id: Valid values are 0-3 and -1 (for all tiles).
Description This API function resets the tile as requested through Tile_Id. If -1 is passed as Tile_Id, it resets all the enabled tiles. All existing register settings are cleared and are replaced with the settings initially configured. Note: This is a common API function for RF-ADC and RF-DAC tiles.
Return Value XRFDC_SUCCESS XRFDC_FAILURE (returned when the tile is not enabled or available)
XRFdc_GetIPStatus
Function Prototype u32 XRFdc_GetIPStatus(XRFdc *InstancePtr, XRFdc_IPStatus *IPStatusPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � XRFdc_IPStatus *IPStatusPtr: Pointer to the XRFdc_IPStatus structure through which the
status is returned.
Description This API function returns the IP status.

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Return Value XRFDC_SUCCESS
XRFdc_GetBlockStatus
Function Prototype u32 XRFdc_GetBlockStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_BlockStatus *BlockStatusPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC block number inside the tile. Valid values are 0-3. � XRFdc_BlockStatus *BlockStatusPtr: Pointer to the XRFdc_BlockStatus structure through
which the RF-ADC/RF-DAC block status is returned.
Description This API function returns the requested block status. Note: This is a common API function for RF-ADCs/RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE (Converter not enabled)
XRFdc_SetMixerSettings
Function Prototype u32 XRFdc_SetMixerSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_Mixer_Settings *MixerSettingsPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC.

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� u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC number inside the tile. Valid values are 0-3. � XRFdc_Mixer_Settings *MixerSettingsPtr: Pointer to the XRFdc_Mixer_Settings
structure that passes the mixer/NCO settings.
Description Mixer/NCO settings passed are used to update the corresponding block level registers. The driver structure is updated with the new values. Note: This is a common API function for RF-ADCs/RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetMixerSettings
Function Prototype u32 XRFdc_GetMixerSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_Mixer_Settings *MixerSettingsPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC number inside the tile. Valid values are 0-3. � XRFdc_Mixer_Settings *MixerSettingsPtr: Pointer to the XRFdc_Mixer_Settings
structure in which the existing mixer/NCO settings are returned.
Description Mixer/NCO settings from corresponding registers are returned to the caller. Note: This is a common API function for RF-ADCs/RF-DACs.
Return Value XRFDC_SUCCESS

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XRFDC_FAILURE
XRFdc_SetQMCSettings
Function Prototype u32 XRFdc_SetQMCSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_QMC_Settings *QMCSettingsPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC number inside the tile. Valid values are 0-3. � XRFdc_QMC_Settings *QMCSettingsPtr: Pointer to the XRFdc_QMC_Settings structure used
to update the corresponding registers.
Description QMC settings from the passed structure are populated into the corresponding registers. The driver structure is updated with the new values. Note: This is a common API function for RF-ADCs/RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetQMCSettings
Function Prototype u32 XRFdc_GetQMCSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_QMC_Settings *QMCSettingsPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC.

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� u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC number inside the tile. Valid values are 0-3. � XRFdc_QMC_Settings *QMCSettingsPtr: Pointer to the XRFdc_QMC_Settings structure
that returns the corresponding register values.
Description QMC settings from the relevant registers are returned back to the caller. Note: This is a common API function for RF-ADCs/RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetCoarseDelaySettings
Function Prototype u32 XRFdc_GetCoarseDelaySettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC number inside the tile. Valid values are 0-3. � XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr: Pointer to the
XRFdc_CoarseDelay_Settings structure which returns the corresponding register values.
Description Coarse delay settings from the relevant registers are returned back to the caller. Note: This is a common API function for RF-ADCs/RF-DACs.
Return Value XRFDC_SUCCESS

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XRFDC_FAILURE
XRFdc_SetCoarseDelaySettings
Function Prototype u32 XRFdc_SetCoarseDelaySettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC number inside the tile. Valid values are 0-3. � XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr: Pointer to the
XRFdc_CoarseDelay_Settings structure through which the coarse delay settings are passed.
Description Coarse delay settings passed from the caller are updated in the relevant registers. The driver structure is updated with the new values. Note: This is a common API function for RF-ADCs/RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_UpdateEvent
Function Prototype u32 XRFdc_UpdateEvent(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 Event);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC.

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� u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC number inside the tile. Valid values are 0-3. � u32 Event: Event can be mixer, QMC, or coarse delay.

Table 74: Valid Macros for Event Argument

Macro
XRFDC_EVENT_MIXER XRFDC_EVENT_CRSE_DLY XRFDC_EVENT_QMC

Mixer event Coarse delay event QMC event

Description

Description Use this function to trigger the update event for an event if the event source is Slice or Tile. Note: This is a common API function for RF-ADCs/RF-DACs.

Return Value XRFDC_SUCCESS XRFDC_FAILURE

XRFdc_SetInterpolationFactor

Function Prototype u32 XRFdc_SetInterpolationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 InterpolationFactor);

Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-DAC number. Valid values are 0-3. � u32 InterpolationFactor: Interpolation factor to be set for the RF-DAC.

Table 75: Valid Macros for InterpolationFactor Argument

Macro
XRFDC_INTERP_DECIM_OFF XRFDC_INTERP_DECIM_1X XRFDC_INTERP_DECIM_2X

Description
Interpolation is OFF 1X interpolation factor 2X interpolation factor

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Table 75: Valid Macros for InterpolationFactor Argument (cont'd)

Macro
XRFDC_INTERP_DECIM_4X XRFDC_INTERP_DECIM_8X

Description
4X interpolation factor 8X interpolation factor

Description
This API function sets the interpolation factor for the requested RF-DAC and also updates the FIFO read width based on the interpolation factor.
Dynamic change in interpolation has an impact on the block throughput. The AXI4-Stream clock rate can be dynamically changed to account for this change of throughput. In non-MTS mode, the recommended procedure is to turn off the FIFO (Xrfdc_setupfifo), change the clock rate (Xrfdc_SetfabClkOutDiv), clear the FIFO interrupt, and restart the FIFO (Xrfdc_SetupFifo).

Return Value XRFDC_SUCCESS XRFDC_FAILURE

XRFdc_GetInterpolationFactor
Function Prototype u32 XRFdc_GetInterpolationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *InterpolationFactorPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-DAC number inside the tile. Valid values are 0-3. � u32 *InterpolationFactorPtr: Pointer to return the interpolation factor for the RF-DAC.
Description The interpolation factor for the requested RF-DAC is returned back to the caller. Note: This API function is only applicable for RF-DACs.

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Return Value XRFDC_SUCCESS XRFDC_FAILURE

XRFdc_SetDecimationFactor

Function Prototype u32 XRFdc_SetDecimationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 DecimationFactor);

Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC number. Valid values are 0-3. � u32 DecimationFactor: Decimation factor to be set for the RF-ADC.

Table 76: Valid Macros for DecimationFactor Argument

Macro
XRFDC_INTERP_DECIM_OFF XRFDC_INTERP_DECIM_1X XRFDC_INTERP_DECIM_2X XRFDC_INTERP_DECIM_4X XRFDC_INTERP_DECIM_8X

Description
Decimation is OFF 1X Decimation factor 2X Decimation factor 4X Decimation factor 8X Decimation factor

Description
This API function sets the decimation factor for the requested RF-ADC and also updates the FIFO write width based on the decimation factor.
Dynamic change in decimation has an impact on the block throughput. The AXI4-Stream clock rate can be dynamically changed to account for this change of throughput. In non-MTS mode, the recommended procedure is to turn off the FIFO (Xrfdc_setupfifo), change the clock rate (Xrfdc_SetfabClkOutDiv), clear the FIFO interrupt, and restart the FIFO (Xrfdc_SetupFifo).
Note: This function is only applicable for RF-ADCs.

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Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetDecimationFactor
Function Prototype u32 XRFdc_GetDecimationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *DecimationFactorPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC number inside the tile. Valid values are 0-3. � u32 *DecimationFactorPtr: Pointer to return the decimation factor for the RF-ADC.
Description Decimation factor for the requested RF-ADC is returned back to the caller. Note: This API function is only applicable for RF-ADCs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_SetFabClkOutDiv
Function Prototype u32 XRFdc_SetFabClkOutDiv(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u16 FabClkDiv);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3.

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� u16 FabClkDiv: PL clock divider to be set for a tile.

Table 77: Valid Macros for FabClkDiv Argument

XRFDC_FAB_CLK_DIV1 XRFDC_FAB_CLK_DIV2 XRFDC_FAB_CLK_DIV4 XRFDC_FAB_CLK_DIV8 XRFDC_FAB_CLK_DIV16

Macro

Divided by 1 Divided by 2 Divided by 4 Divided by 8 Divided by 16

Description Use this function to set the divider for PL clock out. Note: This is a common function for RF-ADCs and RF-DACs.

Return Value XRFDC_SUCCESS XRFDC_FAILURE

Description

XRFdc_GetFabClkOutDiv
Function Prototype u32 XRFdc_GetFabClkOutDiv(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u16 *FabClkDivPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u16 *FabClkDivPtr: Pointer to get the PL clock divider for a tile.
Description Use this function to get the clock divider for the PL. Note: This is a common function for the RF-ADC and the RF-DAC.

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Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_SetFabWrVldWords
Function Prototype u32 XRFdc_SetFabWrVldWords(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 FabricWrVldWords);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-DAC number inside the tile. Valid values are 0-3. � u32 FabricWrVldWords: Write fabric data rate to be set for RF-DAC.
Description This API function sets the write fabric data rate for the requested RF-DAC by writing to the corresponding register. Note: This API function is only applicable for RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetFabWrVldWords
Function Prototype u32 XRFdc_GetFabWrVldWords(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *FabricWrVldWordsPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC.

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� u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC number inside the tile. Valid values are 0-3. � u32 *FabricWrVldWordsPtr: Pointer to return the write PL data rate for the RF-ADCs/RF-
DACs.
Description Write PL data rate for the requested RF-ADC/RF-DAC is returned back to the caller. Note: This is a common API function for RF-ADCs and RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_SetFabRdVldWords
Function Prototype u32 XRFdc_SetFabRdVldWords(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 FabricRdVldWords);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC number inside the tile. Valid values are 0-3. � u32 FabricRdVldWords: Read PL data rate to be set for RF-ADC.
Description This API function sets the read PL data rate for the requested RF-ADC by writing to the corresponding register. Note: This API function is only applicable for RF-ADCs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE

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XRFdc_GetFabRdVldWords
Function Prototype u32 XRFdc_GetFabRdVldWords(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *FabricRdVldWordsPtr);
Arguments � XRFdc* InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC number inside the tile. Valid values are 0-3. � u32 *FabricRdVldWordsPtr: Pointer to return the read PL data rate for the RF-ADC/RF-DACs.
Description Read PL data rate for the requested RF-ADC/RF-DAC is returned back to the caller. Note: This is a common API function for RF-ADCs and RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_ThresholdStickyClear
Function Prototype u32 XRFdc_ThresholdStickyClear(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 ThresholdToUpdate);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC number inside the tile. Valid values are 0-3. � u32 ThresholdToUpdate: Select which Threshold (Threshold0 or Threshold1 or both) to
update.

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Note: See Threshold_Settings structure for valid macros.
Description This API function clears the sticky bit in threshold configuration registers based on the ThresholdToUpdate parameter. Note: This API function is applicable only for RF-ADCs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
Related Information struct XRFdc_Threshold_Settings

XRFdc_SetThresholdClrMode

Function Prototype u32 XRFdc_SetThresholdClrMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 ThresholdToUpdate, u32 ClrMode);

Arguments � XRFdc *InstancePtr: Pointer to the driver instance
� u32 Tile_Id: RF-ADC tile number. Valid values are 0-3.
� u32 Block_Id: RF-ADC number inside the tile. Valid values are 0-3.
� u32 ThresholdToUpdate: Select which Threshold (Threshold0 or Threshold1 or both) to update.
Note: See Threshold_Settings structure for valid macros.
� u32 ClrMode: Clear mode can be manual (register write) or auto clear (QMC gain update event).

Table 78: Valid Macros for ClrMode Argument

Macro
XRFDC_THRESHOLD_CLRMD_MANUAL_CLR XRFDC_THRESHOLD_CLRMD_AUTO_CLR

Manual clear Auto clear

Description

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Description This API function sets the threshold clear mode. Note: This API function is only applicable for RF-ADCs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE Related Information struct XRFdc_Threshold_Settings
XRFdc_GetThresholdSettings
Function Prototype u32 XRFdc_GetThresholdSettings(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Threshold_Settings *ThresholdSettingsPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC number inside the tile. Valid values are 0-3. � XRFdc_Threshold_Settings *ThresholdSettingsPtr: Pointer through which the register settings
for thresholds are passed back.
Description This API function reads threshold settings from the corresponding registers. Note: This API function is only applicable for RF-ADCs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE

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XRFdc_SetThresholdSettings
Function Prototype u32 XRFdc_SetThresholdSettings(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Threshold_Settings *Threshold_Settings);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC number inside the tile. Valid values are 0-3. � XRFdc_Threshold_Settings *Threshold_Settings: Pointer through which the register settings
for thresholds are passed to the API.
Description This API function writes the threshold settings to the relevant registers. The driver structure is updated with the new values. Note: This API function is only applicable for RF-ADCs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_SetDecoderMode
Function Prototype u32 XRFdc_SetDecoderMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 DecoderMode);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-DAC number inside the tile. Valid values are 0-3. � u32 DecoderMode: Decoder mode settings. Valid values are:
� Maximum linearity, for randomized decoder

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� Maximum SNR, for non-randomized decoder

Table 79: Valid Macros for DecoderMode Arguments

Macro
XRFDC_DECODER_MAX_SNR_MODE XRFDC_DECODER_MAX_LINEARITY_MODE

Description
Maximum SNR mode Maximum Linearity mode

Description This API function writes the decoder mode to the relevant registers. The driver structure is updated with the new values.
Note: This API function is used only for the RF-DACs.

Return Value XRFDC_SUCCESS XRFDC_FAILURE

XRFdc_GetDecoderMode
Function Prototype u32 XRFdc_GetDecoderMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *DecoderModePtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-DAC number inside the tile. Valid values are 0-3. � u32 *DecoderModePtr: Pointer in which decoder mode settings to be returned back to the
caller. Valid values are: � Maximum linearity, for randomized decoder � Maximum SNR, for non-randomized decoder
Description This API function reads the decoder mode from the relevant registers. Note: This API function is used only for the RF-DACs.

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Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_ResetNCOPhase
Function Prototype u32 XRFdc_ResetNCOPhase(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC number inside the tile. Valid values are 0-3.
Description This API function resets the NCO phase of the current block phase accumulator.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_SetupFIFO
Function Prototype u32 XRFdc_SetupFIFO(XRFdc *InstancePtr, u32 Type, int Tile_Id, u8 Enable);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � int Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3 and -1 (for all tiles). � u8 Enable: Valid values are 1 (FIFO enable) and 0 (FIFO Disable).

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Description This API function enables and disables the RF-ADC/RF-DAC FIFO.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetOutputCurr
Function Prototype u32 XRFdc_GetOutputCurr(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *OutputCurrPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-DAC number inside the tile. Valid values are 0-3. � u32 *OutputCurrPtr: OutputCurr pointer to return the output current. Description This API function gets the output current. Note: This API function is used only for the RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetFIFOStatus
Function Prototype u32 XRFdc_GetFIFOStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 *EnablePtr);

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Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u8 *EnablePtr: Valid values are 1 (FIFO enable) and 0 (FIFO Disable).
Description This API function gets the current status of the RF-ADC/RF-DAC FIFO.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_DumpRegs
Function Prototype void XRFdc_DumpRegs (XRFdc *InstancePtr, u32 Type, int Tile_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � int Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3 and -1.
Description This function is intended for debug purposes. It prints the contents of registers to the console for the passed Tile_Id. If -1 is passed, it prints the contents of the registers for all the tiles for the respective RF-ADC or RF-DAC. It prints the offset of the register as well as the content.
Return Value None.

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XRFdc_SetNyquistZone
Function Prototype u32 XRFdc_SetNyquistZone(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 NyquistZone);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-DAC number inside the tile. Valid values are 0-3. � u32 NyquistZone: Valid values are 1 (Odd), 2 (Even).
Description This API function sets the Nyquist zone for the RF-ADC/RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetNyquistZone
Function Prototype u32 XRFdc_GetNyquistZone(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *NyquistZonePtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-DAC number inside the tile. Valid values are 0-3. � u32 *NyquistZonePtr: Pointer to return Nyquist Zone.

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Description This API function gets the Nyquist zone for the RF-ADCs/RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_SetInvSincFIR
Function Prototype u32 XRFdc_SetInvSincFIR(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u16 Mode);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-DAC number. Valid values are 0-3. � u16 Mode: Valid values are 0 (disable) and 1 (First Nyquist Zone). Description This API function is used to enable or disable the inverse sinc filter. Note: This API function is used only for the RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetInvSincFIR
Function Prototype u32 XRFdc_GetInvSincFIR(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u16 *ModePtr);

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Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-DAC tile number. Valid values are 0-3. � u16 *ModePtr: Enable pointer is used to get the status. Valid values are 0 (disable) and 1 (first
Nyquist zone).
Description This API function is used to get the inverse sinc filter status. Note: This API function is used only for the RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_SetCalibrationMode
Function Prototype u32 XRFdc_SetCalibrationMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u8 CalibrationMode);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC number. Valid values are 0-3. � u8 CalibrationMode: Valid values are 1 (Mode1) and 2 (Mode2).
Description This API function sets the calibration mode for the RF-ADC. After calling this API, you have to restart the entire tile for the new calibration mode to operate correctly. Note: This API function is used only for the RF-ADCs.After changing the calibration mode of a slice, the commands Xrfdc_Shutdown and Xrfdc_startup must be issued.

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Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetCalibrationMode
Function Prototype u32 XRFdc_GetCalibrationMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u8 *CalibrationModePtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC block number. Valid values are 0-3. � u8 *CalibrationModePtr: Pointer to get the calibration mode.
Description This API function sets the calibration mode for the RF-ADCs. Note: This API function is used only for RF-ADCs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_DisableCoefficientsOverride
Function Prototype u32 XRFdc_DisableCoefficientsOverride(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock);
Arguments � XRFdc * InstancePtr: Pointer to the driver instance � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3 � u32 Block_Id: RF-ADC block number inside the tile. Valid values are 0-3

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� u32 CalibrationBlock: The calibration block whose override is to be disabled. Valid values are 1-3 representing the OCB2, GCB, and TSCB respectively.

Table 80: Valid Macros for CalibrationBlock Argument

Macro
XRFDC_CAL_BLOCK_OCB2 XRFDC_CAL_BLOCK_GCB XRFDC_CAL_BLOCK_TSCB

Description
Offset Calibration Block (Foreground) Gain Calibration Block (Background) Time Skew Calibration Block (Background)

Description This API function disables the coefficient override for the selected block. The clock is selected using the CalibrationBlock parameter.

Return Value XRFDC_SUCCESS XRFDC_FAILURE

XRFdc_SetCalCoefficients

Function Prototype u32 XRFdc_SetCalCoefficients(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock, XRFdc_Calibration_Coefficients *CoeffPtr);

Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC block number inside the tile. Valid values are 0-3. � u32 CalibrationBlock: The calibration block whose override is to be disabled. Valid values are
1-3 representing the OCB2, GCB, and TSCB respectively. � XRFdc_Calibration_Coefficients *CoeffPtr: Pointer to generic calibration coefficients structure

Table 81: Valid Macros for CalibrationBlock Argument

Macro
XRFDC_CAL_BLOCK_OCB2 XRFDC_CAL_BLOCK_GCB

Description
Offset Calibration Block (Foreground) Gain Calibration Block (Background)

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Table 81: Valid Macros for CalibrationBlock Argument (cont'd)

Macro
XRFDC_CAL_BLOCK_TSCB

Description
Time Skew Calibration Block (Background)

Description
This API function enables the coefficient override and programs the provided coefficients for the selected block.
The block is selected using the CalibrationBlock parameter.

Return Value XRFDC_SUCCESS XRFDC_FAILURE

XRFdc_GetCalCoefficients

u32 XRFdc_GetCalCoefficients(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock, XRFdc_Calibration_Coefficients *CoeffPtr);

Arguments � XRFdc * InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC block number inside the tile. Valid values are 0-3. � u32 CalibrationBlock: The calibration block whose override is to be disabled. Valid values are
1-3 representing the OCB2, GCB, and TSCB respectively. � XRFdc_Calibration_Coefficients *CoeffPtr: Pointer to generic calibration coefficients structure

Table 82: Valid Macros for Calibration Block Argument

Macro
XRFDC_CAL_BLOCK_OCB2 XRFDC_CAL_BLOCK_GCB XRFDC_CAL_BLOCK_TSCB

Description
Offset Calibration Block (Foreground) Gain Calibration Block (Background) Time Skew Calibration Block (Background)

Description This API function populates the provided coefficients structure for the selected block.

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The block is selected using the Calibration Block parameter.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_SetCalFreeze
Function Prototype u32 XRFdc_SetCalFreeze(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Cal_Freeze_Settings *CalFreezePtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC block number inside the tile. Valid values are 0-3. � XRFdc_Cal_Freeze_Settings *CalFreezePtr: Pointer to generic calibration freeze settings
structure
Description This API function freezes/unfreezes the calibration via the calibration port and disables/enables the calibration freeze pin.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetCalFreeze
Function Prototype u32 XRFdc_GetCalFreeze(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Cal_Freeze_Settings *CalFreezePtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance.

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� u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC block number inside the tile. Valid values are 0-3. � XRFdc_Cal_Freeze_Settings *CalFreezePtr: Pointer to generic calibration freeze settings
structure
Description This API function populates the provided settings structure with the calibration freeze settings/ status.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_SetDither
Function Prototype u32 XRFdc_SetDither(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC block number inside the tile. Valid values are 0-3. � u32 Mode: Disable (0) or enable (1) dither
Description This API function enables/disables the dither.
Return Value XRFDC_SUCCESS XRFDC_FAILURE

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XRFdc_GetDither
Function Prototype u32 XRFdc_GetDither(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC block number inside the tile. Valid values are 0-3. � u32 *ModePtr: Pointer to be populated with mode
Description This API function populates the pointer provided with the dither mode.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_MultiBand
Function Prototype u32 XRFdc_MultiBand(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 DigitalDataPathMask, u32 DataType, u32 DataConverterMask);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u8 DigitalDataPathMask: Represents the datapath mask for multi-band. The first four bits
represent four datapaths; 1 is enabled and 0 is disabled. � u32 DataType: DataType is the mixer data type; valid values are XRFDC_MB_DATATYPE_*.

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Table 83: Valid Macros for DataType Argument

Macro
XRFDC_MB_DATATYPE_C2C XRFDC_MB_DATATYPE_R2C XRFDC_MB_DATATYPE_C2R

Description
DataType is Complex to Complex DataType is Real to Complex DataType is Complex to Real

� u32 DataConverterMask: DataConverterMask is a block-enabled mask (input/output driving blocks); 1 means enabled and 0 means disabled.

Description This API function is used to set up single-band and multi-band configuration.

Return Value XRFDC_SUCCESS XRFDC_FAILURE

XRFdc_MultiConverter_Init
Function Prototype
void XRFdc_MultiConverter_Init(XRFdc_MultiConverter_Sync_Config *ConfigPtr, int *PLL_CodesPtr, int *T1_CodesPtr);
Arguments � XRFdc_MultiConverter_Sync_Config *ConfigPtr: Multi-tile synchronization configuration
structure. � int *PLL_CodesPtr: Optional target codes for PLL analog SYSREF capture. Set to 0 (NULL)
when not used. � int *T1_CodesPtr: Optional target codes for T1 analog SYSREF capture. Set to 0 (NULL) when
not used.
Description This API function initializes the multi-tile synchronization configuration structures; it must be called before XRFdc_MultiConverter_Sync. Optionally, it allows previously determined target codes to be provided for the PLL/T1 analog SYSREF capture.
Return Value None.

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XRFdc_MultiConverter_Sync
Function Prototype u32 XRFdc_MultiConverter_Sync(XRFdc *InstancePtr, u32 Type, XRFdc_MultiConverter_Sync_Config *ConfigPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � XRFdc_MultiConverter_Sync_Config *ConfigPtr: Multi-tile sync config structure.
Description This is the top-level API function used for multi-tile synchronization.
Return Value XRFDC_MTS_OK XRFDC_MTS_TIMEOUT XRFDC_MTS_MARKER_RUN XRFDC_MTS_MARKER_MISM XRFDC_MTS_NOT_SUPPORTED
XRFdc_DynamicPLLConfig
Function Prototype u32 XRFdc_DynamicPLLConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 Source, double RefClkFreq, double SamplingRate);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u8 Source: Internal PLL or external clock source.

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Table 84: Valid Macros for Source Argument

Macro
XRFDC_EXTERNAL_CLK XRFDC_INTERNAL_PLL_CLK

For external clock For internal PLL

Description

� double RefClkFreq: Reference clock frequency in MHz (FREF min to FREF max). � double SamplingRate: Sampling rate frequency in MHz (Fs min to Fs max).
IMPORTANT! For the FREF and Fs specifications see the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).

Description This API function is used for dynamic switching between the internal PLL and the external clock sources, and for configuring the internal PLL for the RF-ADCs/RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE

XRFdc_GetClockSource
Function Prototype u32 XRFdc_GetClockSource(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 *ClockSourcePtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 *ClockSourcePtr: Pointer to return the clock source.
Description This API function gets the clock source for the RF-ADCs/RF-DACs.
Return Value XRFDC_SUCCESS

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XRFDC_FAILURE
XRFdc_GetPLLConfig
Function Prototype u32 XRFdc_GetPLLConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, XRFdc_PLL_Settings *PLLSettings);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: Valid values are 0-3 and -1 (for all tiles). � XRFdc_PLL_Settings *PLLSettings: Pointer to the XRFdc_PLL_Settings to be populated
with the PLL settings.
Description This API function reads the PLL settings from the registers and populates the XRFdc_PLL_Settings structure.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetPLLLockStatus
Function Prototype u32 XRFdc_GetPLLLockStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 *LockStatusPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 *LockStatusPtr: Pointer to return the PLL lock status.

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Description This API function gets the PLL lock status for the RF-ADCs/RF-DACs.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetLinkCoupling
Function Prototype u32 XRFdc_GetLinkCoupling(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC block number. Valid values are 0-3. � u32 *ModePtr: Pointer to get the Link coupling mode. Description This API function gets the Link Coupling mode for the RF-ADC block.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_MTS_Sysref_Config
Function Prototype u32 XRFdc_MTS_Sysref_Config(XRFdc *InstancePtr, XRFdc_MultiConverter_Sync_Config *DACSyncConfigPtr, XRFdc_MultiConverter_Sync_Config *ADCSyncConfigPtr, u32 SysRefEnable)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance.

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� XRFdc_MultiConverter_Sync_Config *DACSyncConfigPtr: Pointer to RF-DAC Multi-Tile Sync config structure.
� XRFdc_MultiConverter_Sync_Config *ADCSyncConfigPtr: Pointer to ADC Multi-Tile Sync config structure.
� u32 SysRefEnable: 0 for disable and 1 for enable.
Description This API is used to enable and disable the sysref.
Return Value XRFDC_MTS_OK
Interrupt Handling
All interrupt handling functions are implemented in the xrfdc_intr.c file. The prototypes for these are provided through xrfdc.h.
XRFdc_IntrEnable
Function Prototype u32 XRFdc_IntrEnable(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC or RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC or RF-DAC number inside the tile. Valid values are 0-3. � u32 IntrMask: Interrupts to be enabled. The valid masks are: � XRFDC_IXR_FIFOUSRDAT_MASK 0x0000000FU � XRFDC_IXR_FIFOUSRDAT_OF_MASK 0x00000001U � XRFDC_IXR_FIFOUSRDAT_UF_MASK 0x00000002U � XRFDC_IXR_FIFOMRGNIND_OF_MASK 0x00000004U

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� XRFDC_IXR_FIFOMRGNIND_UF_MASK 0x00000008U � XRFDC_ADC_IXR_DATAPATH_MASK 0x00000FF0U � XRFDC_ADC_IXR_DMON_STG_MASK 0x000003F0U � XRFDC_DAC_IXR_DATAPATH_MASK 0x00001FF0U � XRFDC_DAC_IXR_INTP_STG_MASK 0x000003F0U � XRFDC_DAC_IXR_INTP_I_STG0_MASK 0x00000010U � XRFDC_DAC_IXR_INTP_I_STG1_MASK 0x00000020U � XRFDC_DAC_IXR_INTP_I_STG2_MASK 0x00000040U � XRFDC_DAC_IXR_INTP_Q_STG0_MASK 0x00000080U � XRFDC_DAC_IXR_INTP_Q_STG1_MASK 0x00000100U � XRFDC_DAC_IXR_INTP_Q_STG2_MASK 0x00000200U � XRFDC_ADC_IXR_DMON_I_STG0_MASK 0x00000010U � XRFDC_ADC_IXR_DMON_I_STG1_MASK 0x00000020U � XRFDC_ADC_IXR_DMON_I_STG2_MASK 0x00000040U � XRFDC_ADC_IXR_DMON_Q_STG0_MASK 0x00000080U � XRFDC_ADC_IXR_DMON_Q_STG1_MASK 0x00000100U � XRFDC_ADC_IXR_DMON_Q_STG2_MASK 0x00000200U � XRFDC_IXR_QMC_GAIN_PHASE_MASK 0x00000400U � XRFDC_IXR_QMC_OFFST_MASK 0x00000800U � XRFDC_DAC_IXR_INVSNC_OF_MASK 0x00001000U � XRFDC_SUBADC_IXR_DCDR_MASK 0x00FF0000U � XRFDC_SUBADC0_IXR_DCDR_OF_MASK 0x00010000U � XRFDC_SUBADC0_IXR_DCDR_UF_MASK 0x00020000U � XRFDC_SUBADC1_IXR_DCDR_OF_MASK 0x00040000U � XRFDC_SUBADC1_IXR_DCDR_UF_MASK 0x00080000U � XRFDC_SUBADC2_IXR_DCDR_OF_MASK 0x00100000U � XRFDC_SUBADC2_IXR_DCDR_UF_MASK 0x00200000U � XRFDC_SUBADC3_IXR_DCDR_OF_MASK 0x00400000U � XRFDC_SUBADC3_IXR_DCDR_UF_MASK 0x00800000U � XRFDC_ADC_OVR_VOLTAGE_MASK 0x04000000U � XRFDC_ADC_OVR_RANGE_MASK 0x08000000U

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
� XRFDC_ADC_DAT_OVR_MASK 0x40000000U � XRFDC_ADC_FIFO_OVR_MASK 0x80000000U
Description This API function enables the interrupt for the corresponding converter by taking the IntrMask as an input and writing to the corresponding register bit.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_IntrDisable
Function Prototype u32 XRFdc_IntrDisable(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC or RF-DAC tile number. Valid values are 0-3 � u32 Block_Id: RF-ADC or RF-DAC number inside the tile. Valid values are 0-3. � u32 IntrMask: Interrupts to be disabled. The valid masks are described in the API for
XRFdc_IntrEnable.
Description This function disables the interrupt for the corresponding converter by taking the IntrMask as an input and writing to the corresponding register bit.
Return Value XRFDC_SUCCESS XRFDC_FAILURE Related Information XRFdc_IntrEnable

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
XRFdc_SetStatusHandler
Function Prototype void XRFdc_SetStatusHandler(XRFdc *InstancePtr, void *CallBackRefPtr, XRFdc_StatusHandler FunctionPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � void *CallBackRefPtr: Upper layer callback reference passed back when the callback function
is invoked. � XRFdc_StatusHandler FunctionPtr: Pointer to the callback function.
Description This function sets the status callback function, the status handler, which the driver calls when it encounters conditions that must be reported to the higher layer software. The handler executes in an interrupt context to minimize the amount of processing.
Return Value None.
XRFdc_IntrClr
Function Prototype u32 XRFdc_IntrClr(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC or RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC or RF-DAC number inside the tile. Valid values are 0-3 � u32 IntrMask: Interrupts to be cleared. The valid masks are described in the API for
XRFdc_IntrEnable.

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Description This function clears the interrupt for the corresponding converter by taking the IntrMask as an input and writing to the corresponding register bit.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetIntrStatus
Function Prototype u32 XRFdc_GetIntrStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *IntrStsPtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC or RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC or RF-DAC number inside the tile. Valid values are 0-3. � u32 *IntrStsPtr: The interrupt status mask
Description This function returns the status of the interrupts through the masks. Valid masks are described in the API for XRFdc_IntrEnable.
Return Value XRFDC_SUCCESS XRFDC_FAILURE Related Information XRFdc_IntrEnable

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XRFdc_IntrHandler
Function Prototype u32 XRFdc_IntrHandler(u32 Vector, void *XRFdcPtr);
Arguments � u32 Vector: Interrupt Vector number. � void *XRFdcPtr: Pointer to the driver instance that caused the interrupt.
Description This function is used internally by the driver. This is the master interrupt handler for the Zynq� UltraScale+TM RF Data Converter driver. This routine must be connected to an interrupt controller using OS/BSP-specific APIs. It clears the source of the interrupt and prints the cause of the interrupt.
Return Value METAL_IRQ_HANDLED (to inform Libmetal library, IRQ is handled).
XRFdc_GetEnabledInterrupts
Function Prototype u32 XRFdc_GetEnabledInterrupts(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *IntrMask)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC or RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC or RF-DAC number inside the tile. Valid values are 0-3. � u32 *IntrMask: IntrMask is a pointer to the mask of enabled interrupts. 1 denotes an enabled
interrupt, and 0 denotes a disabled interrupt.:
Description This API function populates IntrMask with the enabled interrupts for a given block.

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
Return Value XRFDC_SUCCESS XRFDC_FAILURE

In-line Functions
All in-line functions are defined in the xrfdc.h file. These are available to programmers and are also used internally by other driver API functions. These in-line functions provide a set of utility APIs.
XRFdc_Get_IPBaseAddr
Function Prototype static inline u32 XRFdc_Get_IPBaseAddr(XRFdc *InstancePtr);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance.
Description None.
Return Value Base address of the IP.
XRFdc_Get_TileBaseAddr
Function Prototype static inline u32 XRFdc_Get_TileBaseAddr(XRFdc *InstancePtr, u32 Type, u32 Tile_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: Valid values, 0-3.

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Description None.
Return Value Base address of the requested tile.
XRFdc_Get_BlockBaseAddr
Function Prototype static inline u32 XRFdc_Get_BlockBaseAddr(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: Valid values are 0-3. � u32 Block_Id: Valid values are 0-3.
Description None.
Return Value Base address of the requested converter.
XRFdc_GetNoOfDACBlock
Function Prototype static inline u32 XRFdc_GetNoOfDACBlock(XRFdc *InstancePtr, u32 Tile_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: Valid values are 0-3.
Description None.

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Return Value This function returns the number of RF-DACs enabled in the tile.
XRFdc_GetNoOfADCBlocks
Function Prototype static inline u32 XRFdc_GetNoOfADCBlocks(XRFdc *InstancePtr, u32 Tile_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: Valid values are 0-3. Description None.
Return Value This function returns the number of RF-ADCs enabled in the tile.
XRFdc_IsDACBlockEnabled
Function Prototype static inline u32 XRFdc_IsDACBlockEnabled(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: Valid values are 0-3. � u32 Block_Id: Valid values are 0-3. Description None.
Return Value If the requested RF-DAC is enabled, the function returns 1; otherwise, it returns 0.

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XRFdc_IsADCBlockEnabled
Function Prototype static inline u32 XRFdc_IsADCBlockEnabled(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id);
Arguments � XRFdc* InstancePtr: Pointer to the driver instance. � u32 Tile_Id: Valid values are 0-3. � u32 Block_Id: Valid values are 0-3. Description None.
Return Value If the requested RF-ADC is enabled, the function returns 1; otherwise, it returns 0.
XRFdc_IsHighSpeedADC
Function Prototype static inline u32 XRFdc_IsHighSpeedADC(XRFdc *InstancePtr, int Tile)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � int Tile: RF-ADC/RF-DAC tile number. Valid values are 0-3. Description This returns whether the tile is high speed or not.
Return Value 1 if high speed, otherwise 0.

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XRFdc_GetDataType
Function Prototype static inline u32 XRFdc_GetDataType(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: Valid values are 0-3. � u32 Block_Id: Valid values are 0-3.
Description None.
Return Value If the data type is real, the function returns 0; otherwise, it returns 1.
XRFdc_GetDataWidth
Function Prototype static inline u32 XRFdc_GetDataWidth(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: Valid values are 0-3. � u32 Block_Id: Valid values are 0-3.
Description None.
Return Value This function returns the programmed data width for the RF-ADC.

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XRFdc_GetInverseSincFilter
Function Prototype static inline u32 XRFdc_GetInverseSincFilter(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: Valid values are 0-3. � u32 Block_Id: Valid values are 0-3. Description None.
Return Value If the inverse sinc filter is enabled for the RF-DAC, the function returns 1; otherwise, it returns 0.
XRFdc_GetMixedMode
Function Prototype static inline u32 XRFdc_GetMixedMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: Valid values are 0-3. � u32 Block_Id: Valid values are 0-3. Description None.
Return Value This function returns the mixed mode setting for the RF-DAC.

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
XRFdc_GetMasterTile
Function Prototype static inline u32 XRFdc_GetMasterTile(XRFdc *InstancePtr, u32 Type);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. Description None. Return Value The function returns the master tile ID.
XRFdc_GetSysRefSource
Function Prototype static inline u32 XRFdc_GetSysRefSource(XRFdc *InstancePtr, u32 Type);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. Description None. Return Value The function returns the source of the SYSREF (internal or external).
XRFdc_GetFabClkFreq
Function Prototype static inline double XRFdc_GetFabClkFreq(XRFdc *InstancePtr, u32 Type, u32 Tile_Id);

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Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: Valid values are 0-3.
Description None.
Return Value The function returns the programmed PL clock frequency.
XRFdc_IsFifoEnabled
Function Prototype static inline u32 XRFdc_IsFifoEnabled(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: Valid values are 0-3. � u32 Block_Id: Valid values are 0-3.
Description None.
Return Value If the FIFO is enabled, the function returns 1; otherwise, it returns 0.
XRFdc_GetDriverVersion
Function Prototype static inline double XRFdc_GetDriverVersion();

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Arguments None.
Description Gets the driver version.
Return Value Driver version number.
XRFdc_GetConnectedIData
Function Prototype static inline int XRFdc_GetConnectedIData(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC number. Valid values are 0-3. Description Get converter connected for I digital data path.
Return Value Converter number.
XRFdc_GetConnectedQData
Function Prototype static inline int XRFdc_GetConnectedQData(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id);
Arguments � XRFdc *InstancePtr: Pointer to the driver instance.

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� u32 Type: RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC number. Valid values are 0-3.
Description Get converter connected for Q digital data path.
Return Value Converter number.
XRFdc_ClrSetReg
Function Prototype static inline void XRFdc_ClrSetReg(XRFdc *InstancePtr, u32 BaseAddr, u32 RegAddr, u16 Mask, u16 Data)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 BaseAddr: Address for a Block. � u32 RegAddr: Register Offset value. � u16 Mask: Bit mask value. � u16 Data: Value to be written to the register.
Description This API performs Read Modify Write.
Return Value None
XRFdc_ClrReg
Function Prototype static inline void XRFdc_ClrReg(XRFdc *InstancePtr, u32 BaseAddr, u32 RegAddr, u16 Mask)

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Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 BaseAddr: Address for a Block. � u32 RegAddr: Register Offset value. � u16 Mask: Bit mask value.
Description This API performs Read and Clear.
Return Value None
XRFdc_RDReg
Function Prototype static inline u16 XRFdc_RDReg(XRFdc *InstancePtr, u32 BaseAddr, u32 RegAddr, u16 Mask)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 BaseAddr: Address for a Block. � u32 RegAddr: Register Offset value. � u16 Mask: Bit mask value.
Description This API performs Read and Mask with the value.
Return Value None

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XRFdc_IsDACDigitalPathEnabled
Function Prototype static inline u32 XRFdc_IsDACDigitalPathEnabled(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-DAC block number. Valid values are 0-3.
Description This API checks whether RF-DAC digital path is enabled or not.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_IsADCDigitalPathEnabled
Function Prototype static inline u32 XRFdc_IsADCDigitalPathEnabled(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Tile_Id: RF-ADC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC block number. Valid values are 0-3.
Description This API checks whether ADC Digital path is enabled or disabled.
Return Value XRFDC_SUCCESS

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XRFDC_FAILURE
XRFdc_CheckDigitalPathEnabled
Function Prototype static inline u32 XRFdc_CheckDigitalPathEnabled(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC block number. Valid values are 0-3.
Description This API checks whether RF-ADC/RF-DAC digital path is enabled or not.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_SetConnectedIQData
Function Prototype static inline void XRFdc_SetConnectedIQData(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, int ConnectedIData, int ConnectedQData)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC block number. Valid values are 0-3 � int ConnectedIData: Converter Id to which DigitalPathI connected � int ConnectedQData: Converter Id to which DigitalPathQ connected

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Description This API set Data Converter connected for digital data path I and Q.
Return Value None
XRFdc_GetMultibandConfig
Function Prototype static inline u32 XRFdc_GetMultibandConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. Description This API is to get Multiband Config data
Return Value This API returns Multiband configuration.
XRFdc_CheckBlockEnabled
Function Prototype static inline u32 XRFdc_CheckBlockEnabled(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � u32 Block_Id: RF-ADC/RF-DAC block number. Valid values are 0-3.

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Description This API checks whether RF-ADC/RF-DAC block is enabled or disabled.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_CheckTileEnabled
Function Prototype static inline u32 XRFdc_CheckTileEnabled(XRFdc *InstancePtr, u32 Type, u32 Tile_Id)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. Description This API checks whether RF-ADC/RF-DAC tile is enabled or disabled.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetMaxSampleRate
Function Prototype static inline u32 XRFdc_GetMaxSampleRate(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, double *MaxSampleRatePtr)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: 0 for RF-ADC and 1 for RF-DAC.

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Appendix C: Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
� u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � double *MaxSampleRatePtr: Pointer to be populated with maximum sampling rate for tile
Description This API is used to get the tile's maximum sampling rate.
Return Value XRFDC_SUCCESS XRFDC_FAILURE
XRFdc_GetMinSampleRate
Function Prototype static inline u32 XRFdc_GetMinSampleRate(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, double *MinSampleRatePtr)
Arguments � XRFdc *InstancePtr: Pointer to the driver instance. � u32 Type: 0 for RF-ADC and 1 for RF-DAC. � u32 Tile_Id: RF-ADC/RF-DAC tile number. Valid values are 0-3. � double *MinSampleRatePtr: Pointer to be populated with minimum sampling rate for tile
Description This API is used to get the tile's minimum sampling rate.
Return Value XRFDC_SUCCESS XRFDC_FAILURE

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Appendix D: RF Analyzer
Appendix D
RF Analyzer
The RF Analyzer provides a method of evaluating and monitoring the converters in hardware. An overview of the system is given below. The IP example design blocks are outlined in yellow.
Figure 104: RF Analyzer

The RF Analyzer GUI provides access to the data stimulus and capture blocks together with data analysis tools for processing the data. The MicroBlazeTM provides system configuration and control.
The major changes to the existing example design are:
� The addition of a MicroBlaze to facilitate the configuration and control of the IP subsystem. � The inclusion of a JTAG to AXI IP core to enable communication between the RF Analyzer
GUI and the IP subsystem. � Clocking logic to generate the AXI4-Stream clocks from the converter output clocks. � Clocking logic to generate the AXI4-Lite clock from the FPGA startup component.
A block diagram of the expanded example design is shown below.

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Appendix D: RF Analyzer

Figure 105: RF Analyzer Example Design Verilog Example Design Wrapper
STARTUP

Extended IP Integrator Example Design Base IP Integrator Example Design

BRAM

DAC3

BRAM

DAC2

BRAM

DAC1

Clocking
Smartconnect MicroBlaze JTAG-2-AXI

Smartconnect

BRAM AXI I/F Data Stimulus
BRAM

DAC0 ADC3

BRAM

ADC2

BRAM

ADC1

BRAM

ADC0

AXI I/F Data Capture

AXI I/F RF Data Converter IP

X21660-051319
The base IP integrator example design is as described in the Example Design Chapter. The extended IP integrator example design includes the MicroBlazeTM, JTAG to AXI, and clocking blocks to support the RF Analyzer.
Related Information Example Design

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Appendix D: RF Analyzer

Clocking
When multi-tile synchronization (MTS) is not enabled the AXI4-Stream clocks for each RF-ADC and RF-DAC are generated from the respective converter output clock. Any combination of output clock frequency and AXI4-Stream clock frequency is supported. The clock wizard IP core is used to generate a MMCM to provide the correct AXI4-Stream clock. The MMCM is programmable using the AXI4-Lite interface, allowing changes to the decimation and interpolation factors of the converters. The default clocking is shown below.

Figure 106: RF Analyzer Clocking RF Data Converter IP

Clocking

BUFG_GT

MMCM

BUFG

CLKOUT = CLKIN * Fabric_Freq / Outclk_Freq

CLK_DAC/ADC FABRIC_CLK
RF-DAC/RF-ADC

X21612-092718
When the user selects multi-tile sync all the fabric clocks for the converters in the multi-tile sync group are driven from the same source. The programmable logic clock and user SYSREF are inputs. The user will input a PL clock frequency from the GUI. The pin placement of the PL clock and SYSREF is left to the user. The clocking for the DAC when multi-tile sync has been selected is shown below.

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PL_CLK PL_SYSREF

Appendix D: RF Analyzer

Figure 107: Clocking for Multi-Tile Synchronization

Clocking BUFG

RF Data Converter IP

MMCM

BUFG

CLKOUT = CLKIN * Fabric_Freq / PL_Clk_Freq

FABRIC_CLK
DDAACC0

user_sysref_dac

FABRIC_CLK
DAC1

FABRIC_CLK
DAC2

FABRIC_CLK
DAC3
X22865-050919
For accurate SYSREF capture the PL clock frequency must be a common integer multiple of the RF-ADC and RF-DAC AXI4-Stream clock frequencies.

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Appendix D: RF Analyzer

Address Space
The RF Analyzer address space is shown in the following table.

Table 85: RF Analyzer Address Space

Address
0xE000_0000 0xC000_0000 0x44B0_0000 0x44C0_0000 0x44C1_0000 0x44C2_0000 0x44C3_0000 0x44C4_0000 0x44C5_0000 0x44C6_0000 0x44C7_0000

Size
1024kbytes 1024kbytes 256kbytes
64kbytes 64kbytes 64kbytes 64kbytes 64kbytes 64kbytes 64kbytes 64kbytes

Component
RF-ADC Data Capture RF-DAC Data Stimulus Converter IP DAC0 MMCM DAC1 MMCM DAC2 MMCM DAC3 MMCM ADC0 MMCM ADC1 MMCM ADC2 MMCM ADC3 MMCM

The register maps for the data capture and data stimulus blocks are described in the Example Design Chapter. The converter IP register maps are described in the Product Specification Chapter.
Related Information Example Design Register Space

User Interface
The RF Analyzer IP integrator design can be integrated into user designs. Access to the RF-DAC AXI4-Stream interface is provided through the following ports.

Table 86: RF-DAC User Interface

Port Name1
sX_axis_aclk
sXY_0_tdata sXY_0_tvalid sXY_0_tready

I/O

Clock

Description

Out

N/A

AXI4-Stream clock output from the MMCM in the clocking

block

sX_axis_aclk AXI4-Stream data input

sX_axis_aclk AXI4-Stream valid

Out

sX_axis_aclk AXI4-Stream ready

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Appendix D: RF Analyzer

Table 86: RF-DAC User Interface (cont'd)

Port Name1

I/O

Clock

Description

user_select_XY_0

sX_axis_aclk When this input is driven High the RF-DAC is driven from the

user interface. When Low the RF-DAC is driven by the data

stimulus block in the RF Analyzer.

Notes: 1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC block in the tile (0 to 3).

The AXI4-Stream interface is routed out to the user design through the ports described in the following table.

Table 87: RF-ADC User Interface

Port Name1

I/O

Clock

Description

mX_axis_aclk

Out

N/A

AXI4-Stream clock output from the MMCM in the clocking

block

mXY_0_tdata

Out

mX_axis_aclk AXI4-Stream data output

mXY_0_tvalid

Out

mX_axis_aclk AXI4-Stream valid

mXY_0_tready

mX_axis_aclk AXI4-Stream ready. Tie Low when the user interface is not in

use. The RF Analyzer data capture block should be disabled

when the user interface is in use.

Notes: 1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC block in the tile (0 to 3).

Hardware Trigger
Hardware trigger inputs are available. When enabled, asserting the hardware trigger will start the data transmission or capture. This overrides the writes to the Start Data register.

Table 88: RF-DAC Hardware Trigger Interface

Port Name1

I/O

Clock

Description

dacX_hw_trigger

s_axi_aclk Hardware trigger. Assert to enable data

transmission.Deassert before starting any subsequent data

transmission.

dacX_hw_trigger_en

s_axi_aclk Hardware trigger enable. Assert to enable the hardware

trigger

Notes: 1. X refers to the location of the tile in the converter column.

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Appendix D: RF Analyzer

Table 89: RF-ADC Hardware Trigger Interface

Port Name1

I/O

adcX_hw_trigger

s_axi_aclk Hardware trigger. Assert to enable data capture. The input

should be deasserted before any subsequent data capture.

adcX_hw_trigger_en

s_axi_aclk Hardware trigger enable. Assert to enable the hardware

trigger

Notes: 1. X refers to the location of the tile in the converter column.

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Appendix E
Additional Resources and Legal Notices

Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support.

Documentation Navigator and Design Hubs
Xilinx� Documentation Navigator (DocNav) provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open DocNav:
� From the Vivado� IDE, select HelpDocumentation and Tutorials. � On Windows, select StartAll ProgramsXilinx Design ToolsDocNav. � At the Linux command prompt, enter docnav.
Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs:
� In DocNav, click the Design Hubs View tab. � On the Xilinx website, see the Design Hubs page.
Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.

References
These documents provide supplemental material useful with this product guide:

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Appendix E: Additional Resources and Legal Notices
1. Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) 2. Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) 3. Zynq UltraScale+ Device Technical Reference Manual (UG1085) 4. UltraScale Architecture PCB Design User Guide (UG583) 5. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) 6. Vivado Design Suite User Guide: Designing with IP (UG896) 7. Vivado Design Suite User Guide: Getting Started (UG910) 8. Vivado Design Suite User Guide: Logic Simulation (UG900) 9. Vivado Design Suite User Guide: Programming and Debugging (UG908) 10. Zynq UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG1075) 11. RF Data Converter Interface User Guide (UG1309)

Revision History
The following table shows the revision history for this document.

Section
All Background Calibration Process PLL Parameters Detailed Description NCO Frequency Hopping Multi-Tile Mode User Parameters Chapter 7: Test Bench Analog Signaling struct XRFdc_Mixer_Settings User API Functions
XRFdc_RegisterMetal XRFdc_GetPLLConfig Interrupt Handling XRFdc_GetEnabledInterrupts struct XRFdc
NCO Frequency Hopping Over Voltage

Revision Summary
10/30/2019 v2.2 Terminology updated to Quad and Dual converter types Signal name update New topic Updated Updated Updated Updated Updated Updated Valid macros for MixerType updated New
Updated driver title 05/22/2019 v2.1
Updated content Updated content

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Section
Interrupt Handling System Clocking Tab Clocking Address Space Hardware Trigger Overview Summary Tab struct XRFdc_Calibration_Coefficients struct XRFdc_Cal_Freeze_Settings XRFdc_DisableCoefficientsOverride XRFdc_SetCalCoefficients XRFdc_GetCalCoefficients XRFdc_SetCalFreeze XRFdc_GetCalFreeze XRFdc_SetDither XRFdc_GetDither XRFdc_GetPLLConfig XRFdc_GetMaxSampleRate XRFdc_GetMinSampleRate XRFdc_IsHighSpeedADC XRFdc_SetInvSincFIR XRFdc_GetInvSincFIR XRFdc_IntrEnable XRFdc_IntrDisable XRFdc_IntrClr XRFdc_GetIntrStatus XRFdc_IntrHandler
Appendix D: RF Analyzer Reset Count Register (0x0038) Over Voltage PLL Summary Tab Chapter 6: Example Design Chapter 7: Test Bench User API Functions In-line Functions
Data Structures User API Functions In-line Functions
Port Descriptions

Appendix E: Additional Resources and Legal Notices
Revision Summary
Interrupt handling updated New tab in Vivado� IDE Updated content Address space updated New topic Updated driver files list Removed tab in Vivado IDE New driver topics
Replaces XRFdc_IsADC4GSPS Updated driver information
12/05/2018 v2.1 Added RF Analyzer appendix. Added register. Updated section. Updated section. New tab documented. Example Design chapter updated. Test Bench chapter updated. Added to and updated section. Added in-line functions.
04/17/2018 v2.0 Added and updated driver commands.
04/04/2018 v2.0 Added clarification to the notes in the Port Description tables.

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Appendix E: Additional Resources and Legal Notices

Section
Multi-Tile Synchronization Ports Calibration Freeze Ports for Quad RF-ADC Tiles Calibration Freeze Ports for Dual RF-ADC Tiles Basic Tab Advanced Tab RF-ADC Tab RF-DAC Tab Chapter 6: Example Design RF-DAC Data Stimulus Block
Major content addition and IP core updates.
Initial release.

Revision Summary
Added Multi Converter Synchronization Ports table. Added Calibration Freeze Ports tables.
Added Basic and Advanced Vivado IDE tab descriptions.
Improved description of RF-ADC and RF-DAC Vivado IDE tabs. Added information on IP Integrator example design. Added information on RF-DAC source register map. 10/04/2017 v1.1 Major content addition and IP core updates. 04/05/2017 v1.0

Please Read: Important Legal Notices
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Appendix E: Additional Resources and Legal Notices
AUTOMOTIVE APPLICATIONS DISCLAIMER
AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
Copyright
� Copyright 2017-2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

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