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For example, routing resources distributed in CFU and IOB connect resources in CFU and IOB. Routing resources can automatically be.
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GW1NZ series of FPGA Products Datasheet DS841-1.6E,06/30/2020 Copyright©2020 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI. Disclaimer GOWINSEMI®, LittleBee®, Arora, and the GOWINSEMI logos are trademarks of GOWINSEMI and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders, as described at www.gowinsemi.com. GOWINSEMI assumes no liability and provides no warranty (either expressed or implied) and is not responsible for any damage incurred to your hardware, software, data, or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale. All information in this document should be treated as preliminary. GOWINSEMI may make changes to this document at any time without prior notice. Anyone relying on this documentation should contact GOWINSEMI for the current documentation and errata. Revision History Date Version 01/23/2019 1.0E 02/12/2019 1.1E 04/03/2019 1.2E 09/25/2019 11/06/2019 01/06/2020 06/30/2020 1.3E 1.4E 1.5E 1.6E Description Initial version published. Figures of part naming updated. I/O BANK view updated; The description of I3C bus and SPMI added; the precision of the on chip OSC added; Changerd "Operating Temperature" to "Junction Temperature". The note of "GW1NZ-1 I/Os support differential output, rather than differential input" added; Power supply ramp rate modified. Number of Max. I/O updated. The static current of ZV devices added; Low power description of user flash added. GW1NZ-1 FN32F added. Contents Contents Contents ............................................................................................................... i List of Figures .................................................................................................... iv List of Tables...................................................................................................... vi 1 About This Guide ............................................................................................. 1 1.1 Purpose .............................................................................................................................. 1 1.2 Related Documents ............................................................................................................ 1 1.3 Abbreviations and Terminology........................................................................................... 2 1.4 Support and Feedback ....................................................................................................... 2 2 General Description......................................................................................... 3 2.1 Features.............................................................................................................................. 3 2.2 Product Resources ............................................................................................................. 5 2.3 Package Information........................................................................................................... 5 3 Architecture...................................................................................................... 6 3.1 Architecture Overview......................................................................................................... 6 3.2 Configurable Function Unit ................................................................................................. 7 3.2.1 Look-up Table .................................................................................................................. 8 3.2.2 Register ........................................................................................................................... 9 3.2.3 CRU ................................................................................................................................. 9 3.3 IOB.................................................................................................................................... 10 3.3.1 I/O Buffer ....................................................................................................................... 10 3.3.2 I/O Logic ........................................................................................................................ 12 3.3.3 I/O Logic Modes............................................................................................................. 14 3.4 I3C Bus ............................................................................................................................. 18 3.4.1 Overview ........................................................................................................................ 18 3.4.2 Port Signal ..................................................................................................................... 19 3.5 SPMI ................................................................................................................................. 21 3.5.1 Overview ........................................................................................................................ 21 3.5.2 Port Signal ..................................................................................................................... 22 3.6 Block SRAM (B-SRAM) .................................................................................................... 22 3.6.1 Introduction .................................................................................................................... 22 3.6.2 Configuration Mode ....................................................................................................... 23 DS841-1.6E i Contents 3.6.3 Mixed Data Bus Width Configuration............................................................................. 25 3.6.4 Byte-enable.................................................................................................................... 25 3.6.5 Parity Bit ........................................................................................................................ 25 3.6.6 Synchronous Operation ................................................................................................. 26 3.6.7 Power up Conditions ..................................................................................................... 26 3.6.8 B-SRAM Operation Modes ............................................................................................ 26 3.6.9 Clock Operations ........................................................................................................... 28 3.7 User Flash ........................................................................................................................ 29 3.7.1 Introduction .................................................................................................................... 29 3.7.2 Mode .............................................................................................................................. 29 3.7.3 Port Signal ..................................................................................................................... 30 3.7.4 Operation Modes ........................................................................................................... 31 3.8 Clock ................................................................................................................................. 31 3.8.1 Global Clock .................................................................................................................. 31 3.8.2 PLL ................................................................................................................................ 34 3.8.3 HCLK ............................................................................................................................. 35 3.9 Long Wire (LW)................................................................................................................. 35 3.10 Global Set/Reset (GSR) ................................................................................................. 36 3.11 Programming Configuration ............................................................................................ 36 3.11.1 SRAM Configuration .................................................................................................... 36 3.11.2 Flash Configuration ...................................................................................................... 36 3.12 On Chip Oscillator........................................................................................................... 36 4 AC/DC Characteristic..................................................................................... 38 4.1 Operating Conditions ........................................................................................................ 38 4.1.1 Absolute Max. Ratings ................................................................................................... 38 4.1.2 Recommended Operating Conditions ........................................................................... 38 4.1.3 Power Supply Ramp Rates ........................................................................................... 38 4.1.4 Hot Socket Specifications .............................................................................................. 39 4.1.5 POR Specification.......................................................................................................... 39 4.2 ESD................................................................................................................................... 39 4.3 DC Characteristic.............................................................................................................. 39 4.3.1 DC Electrical Characteristics over Recommended Operating Conditions .................... 39 4.3.2 Static Current ................................................................................................................. 41 4.3.3 I/O Operating Conditions Recommended ..................................................................... 42 4.3.4 Single-Ended IO DC Electrical Characteristic ............................................................. 43 4.4 Switching Characteristic ................................................................................................... 44 4.4.1 CFU Block Internal Timing Parameters ......................................................................... 44 4.4.2 Clock and I/O Switching Characteristics ....................................................................... 44 4.4.3 B-SRAM Switching Characteristics ............................................................................... 44 DS841-1.6E ii Contents 4.4.4 On chip Oscillator Output Frequency ............................................................................ 44 4.4.5 PLL Switching Characteristics ....................................................................................... 45 4.5 User Flash Characteristic ................................................................................................. 45 4.5.1 DC Characteristic........................................................................................................... 45 4.5.2 Timing Parameters......................................................................................................... 47 4.5.3 Operation Timing Diagrams ........................................................................................... 48 4.6 Configuration Interface Timing Specification .................................................................... 49 5 Ordering Information ..................................................................................... 50 5.1 Part Name......................................................................................................................... 50 5.2 Package Mark ................................................................................................................... 51 DS841-1.6E iii List of Figures List of Figures Figure 3-1 GW1NZ Architecture Overview ........................................................................................ 6 Figure 3-2 CFU View.......................................................................................................................... 8 Figure 3-3 Register in CFU ................................................................................................................ 9 Figure 3-4 IOB Structure View ........................................................................................................... 10 Figure 3-5 I/O Bank Distribution of GW1NZ series of FPGA Products.............................................. 11 Figure 3-6 I/O Logic Output ............................................................................................................... 12 Figure 3-7 I/O Logic Input .................................................................................................................. 12 Figure 3-8 IODELAY .......................................................................................................................... 13 Figure 3-9 Register Structure in I/O Logic ......................................................................................... 13 Figure 3-10 IEM Structure.................................................................................................................. 14 Figure 3-11 I/O Logic in Basic Mode .................................................................................................. 14 Figure 3-12 I/O Logic in SDR Mode................................................................................................... 15 Figure 3-13 I/O Logic in DDR Input Mode ......................................................................................... 15 Figure 3-14 I/O Logic in DDR Output Mode....................................................................................... 16 Figure 3-15 I/O Logic in IDES10 Mode .............................................................................................. 16 Figure 3-16 I/O Logic in OSER4 Mode .............................................................................................. 16 Figure 3-17 I/O Logic in IVideo Mode ................................................................................................ 17 Figure 3-18 I/O Logic in OVideo Mode .............................................................................................. 17 Figure 3-19 I/O Logic in IDES8 Mode ................................................................................................ 17 Figure 3-20 I/O Logic in OSER8 Mode .............................................................................................. 18 Figure 3-21 I/O Logic in IDES10 Mode .............................................................................................. 18 Figure 3-22 I/O Logic in OSER10 Mode ............................................................................................ 18 Figure 3-27 Pipeline Mode in Single Port, Dual Port and Semi Dual Port......................................... 26 Figure 3-28 Independent Clock Mode ............................................................................................... 28 Figure 3-29 Read/Write Clock Mode.................................................................................................. 28 Figure 3-30 Single Port Clock Mode .................................................................................................. 29 Figure 3-31 GW1NZ-1 User Flash Ports ........................................................................................... 30 Figure 3-32 GW1NZ-1 Clock Resources ........................................................................................... 31 Figure 3-33 GCLK Quadrant Distribution........................................................................................... 32 Figure 3-34 DQCE Concepts ............................................................................................................. 32 Figure 3-35 DCS Concept.................................................................................................................. 33 Figure 3-36 DCS Rising Edge............................................................................................................ 33 DS841-1.6E iv List of Figures Figure 3-37 DCS Falling Edge ........................................................................................................... 33 Figure 3-38 PLL Structure.................................................................................................................. 34 Figure 3-39 GW1NZ-1 HCLK Distribution.......................................................................................... 35 Figure 4-1 Read Mode ....................................................................................................................... 48 Figure 4-2 Write Mode ....................................................................................................................... 48 Figure 4-3 Erasure Mode ................................................................................................................... 49 Figure 5-1 Part Naming ExampleES................................................................................................ 50 Figure 5-2 Part Naming ExampleProduction ................................................................................... 51 Figure 5-3 Package Mark................................................................................................................... 51 DS841-1.6E v List of Tables List of Tables Table 1-1 Abbreviations and Terminologies ....................................................................................... 2 Table 2-1 Product Resources............................................................................................................. 5 Table 2-2 Package Information and Max. User I/O............................................................................ 5 Table 3-1 Register Description in CFU .............................................................................................. 9 Table 3-2 Output I/O Standards and Configuration Options .............................................................. 11 Table 3-3 Output I/O Standards and Configuration Options .............................................................. 12 Table 3-4 I3C Port Signals ................................................................................................................. 20 Table 3-5 SPMI Port Signal ................................................................................................................ 22 Table 3-6 B-SRAM Signals ................................................................................................................ 23 Table 3-7 Memory Size Configuration................................................................................................ 23 Table 3-8 Dual Port Mixed Read/Write Data Width Configuration ..................................................... 25 Table 3-9 Semi Dual Port Mixed Read/Write Data Width Configuration ............................................ 25 Table 3-14 Clock Operations in Different B-SRAM Modes ................................................................ 28 Table 3-15 User Flash Modes ............................................................................................................ 30 Table 3-16 Flash Module Signal Description ..................................................................................... 30 Table 3-17 Truth Table in User Mode ................................................................................................. 31 Table 3-18 PLL Ports Definition.......................................................................................................... 34 Table 3-19 Oscillator Output Frequency Options ............................................................................... 37 Table 4-1 Absolute Max. Ratings ....................................................................................................... 38 Table 4-2 Recommended Operating Conditions ................................................................................ 38 Table 4-3 Power Supply Ramp Rates ................................................................................................ 38 Table 4-4 Hot Socket Specifications .................................................................................................. 39 Table 4-5 POR Specification .............................................................................................................. 39 Table 4-6 GW1NZ ESD - HBM........................................................................................................... 39 Table 4-7 GW1NZ ESD - CDM .......................................................................................................... 39 Table 4-8 DC Electrical Characteristics over Recommended Operating Conditions ......................... 39 Table 4-9 Static Supply Current (LV Device) ..................................................................................... 41 Table 4-10 Static Supply Current (ZV Device) ................................................................................... 41 Table 4-11 I/O Operating Conditions Recommended ........................................................................ 42 Table 4-12 Single-Ended IO DC Electrical Characteristic ............................................................... 43 Table 4-13 CFU Block Internal Timing Parameters............................................................................ 44 Table 4-14 Clock and I/O Switching Characteristics .......................................................................... 44 DS841-1.6E vi List of Tables Table 4-15 B-SRAM Internal Timing Parameters............................................................................... 44 Table 4-16 On chip Oscillator Output Frequency............................................................................... 44 Table 4-17 PLL Switching Characteristics.......................................................................................... 45 Table 4-18 User Flash DC Characteristics......................................................................................... 45 Table 4-19 User Flash Timing Parameters ........................................................................................ 47 DS841-1.6E vii 1 About This Guide 1.1 Purpose 1About This Guide 1.1 Purpose This data sheet describes the features, product resources and structure, AC/DC characteristics, timing specifications of the configuration interface, and the ordering information of the GW1NZ series of FPGA product. It is designed to help you understand the GW1NZ series of FPGA products quickly and select and use devices appropriately. 1.2 Related Documents The latest user guides are available on the GOWINSEMI Website. You can find the related documents at www.gowinsemi.com: 1. DS841, GW1NZ series of FPGA Products Data Sheet 2. UG290, Gowin FPGA Products Programming and Configuration User Guide 3. UG843, GW1NZ series of FPGA Products Package and Pinout 4. UG842, GW1NZ-1 Pinout DS841-1.6E 1(51) 1 About This Guide 1.3 Abbreviations and Terminology 1.3 Abbreviations and Terminology The abbreviations and terminology used in this manual are as shown in Table 1-1 below. Table 1-1 Abbreviations and Terminologies Abbreviations and Terminology FPGA CFU CLS CRU LUT4 LUT5 LUT6 LUT7 LUT8 REG ALU IOB B-SRAM SP SDP DP DQCE DCS PLL SPMI GPIO CS30 FN32 LQ100 LQ144 MG160 PG204 Full Name Field Programmable Gate Array Configurable Functional Unit Configurable Logic Slice Configurable Routing Unit Four-input Look-up Table Five-input Look-up Tables Six-input Look-up Tables Seven-input Look-up Tables Eight-input Look-up Tables Register Arithmetic Logic Unit Input/output Bank Block SRAM Signal Port Semi Dual Port Dual Port Dynamic Quadrant Clock Enable Dynamic Clock Selector Phase Locked Loop System Power Management Interface Gowin Programmable IO WLCSP30 QFN32 LQFP100 LQFP144 MBGA160 PBGA204 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail: support@gowinsemi.com DS841-1.6E 2(51) 2 General Description 2.1 Features 2General Description The GW1NZ series of FPGA products are the first generation products in the LittleBee® family. They offer ultra-low power consumption, instant on, low cost, non-volatile, high security, various packages, and flexible usage. They can be widely used in communication, industry control, consumer, video control, etc. GOWINSEMI provides a new generation of FPGA hardware development environment through market-oriented independent research and development that supports the GW1NZ series of FPGA products and applies to FPGA synthesizing, layout, place and routing, data bitstream generation and download, etc. 2.1 Features Zero power consumption - 55nm embedded flash technology - LV: Supports 1.2V core voltage - ZV: Supports 0.9V core voltage. Please refer to Table 4-10 Static Supply Current (ZV Device) for the lowest power consumption. - Power Management Module - Clock dynamically turns on and off - User Falsh dynamically turns on and off Power Management Module - SPMI: System power management interface - VCC and VCCM are independent in the device User Flash - Dynamically turns on and off - 64K bits - Data Width: 32 - 10,000 write cycles - Greater than ten years' data retention at +85 - Supports page erasure: 2048 bytes per page - Duration: Max. 25ns - Electric current a). Read Operation: 2.19 mA/25 ns (VCC) & 0.5 mA/25 ns (VCCX) (MAX); b). Write operation/erase operation: 12/12 mA (MAX) DS841-1.6E 3(51) 2 General Description 2.1 Features - Quick page erasure/Write operation - Clock frequency: 40MHz - Write operation time: 16s - Page erasure time: 120 ms Multiple I/O Standards - LVCMOS33/25/18/15/12;LVTTL33; PCI; - LVDS25E, BLVDSE, MLVDSE, LVPECLE, RSDSE - Input hysteresis option - Supports 4mA,8mA,16mA,24mA,etc. drive options - Slew Rate option - Output drive strength option - Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option - Hot Socket - I3C hard core, supports SDR mode - Support differential output, rather than differential input Abundant Slices - Four input LUT (LUT4) - Double-edge flip-flops - Supports shifter register - Supports shadow SRAM Block SRAM with multiple modes - Supports Dual Port, Single Port, and Semi Dual Port - Supports bytes write enable Flexible PLLs - Frequency adjustment (multiply and division) and phase adjustment - Supports global clock Built-in Flash programming - Instant-on - Supports security bit operation - Supports AUTO BOOT and DUAL BOOT Configuration - JTAG configuration - Offers up to six GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT DS841-1.6E 4(51) 2 General Description 2.2 Product Resources 2.2 Product Resources Table 2-1 Product Resources Device LUT4 Flip-Flop (FF) Shadow SRAM S-SRAM (bits) Block SRAM B-SRAM (bits) PLLs User Flash (bits) Max. I/O VCC GW1NZ-1 1,152 864 4K 72K 1 64K 48 1.2V(LV); 0.9V(ZV) 2.3 Package Information Table 2-2 Package Information and Max. User I/O Package FN32 FN32F CS16 QN48 Pitch (mm) 0.4 0.4 0.4 0.4 Size (mm) 4 x 4 4 x 4 1.8 x 1.8 6 x 6 GW1NZ-1 25 25 11 40 Note! In this manual, abbreviations are employed to refer to the package types. See 5.1 Part Name. The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O plus one. DS841-1.6E 5(51) 3 Architecture 3.1 Architecture Overview 3Architecture 3.1 Architecture Overview Figure 3-1 GW1NZ Architecture Overview DS841-1.6E I/OBAnk0/1 I/OBAnk0/1 I/OBank0 SPMI CFU CFU Block SRAM CFU User Flash PLL Block SRAM OSC CFU CFU I3C I/OBank1 SPMI CFU CFU User Flash IOB IOB Block SRAM IOB PLL IOB Block SRAM IOB OSC IOB CFU CFU CFU CFU IOB IOB CFU CFU CFU IOB I3C IOB Figure 3-1 shows the GW1NZ devices architecture view.The core of the GW1NZ devices is the array of configurable logic unit (CFU) surrounded by IO blocks. GW1NZ also provides B-SRAM, DSP, PLL, user Flash, and on chip oscillator and supports Instant-on. SPMI and I3C are also embedded in the GW1NZ devices. See Table 2-1 for more detailed information on internal resources. Configurable Function Unit (CFU) is the base cell for the array of the GW1NZ series of FPGA Products. These CFUs arrange in rows and columns. CFU can be configured as LUT4 mode, ALU mode, and memory mode. See 3.2Configurable Function Unit for further detailed information. The I/O resources in the GW1NZ series of FPGA products are arranged around the periphery of the devices in groups referred to as banks, including Bank0 and Bank1. The I/O resources support multiple level standards, and support basic mode, SRD mode, and generic DDR mode. See 3.3IOB for further detailed information. The B-SRAM is embedded as a row in the GW1NZ series of FPGA 6(51) 3 Architecture 3.2 Configurable Function Unit products. In the FPGA array, each B-SRAM occupies three columns of CFU. Each B-SRAM has 18,432 bits (18 Kbits) and supports multiple configuration modes and operation modes. See 3.6Block SRAM (B-SRAM) for further detailed information. The User Flash is embedded in the GW1NZ series of FPGA products, without loss of data even if power off. See Table 2-1 for further detailed information. See 3.7User Flash for further detailed information. GW1NZ provides one PLL. PLL blocks provide the ability to synthesize clock frequencies. Frequency adjustment (multiply and division), phase adjustment, and duty cycle can be adjusted using the configuration of parameters. See 3.8Clock for further detailed information. FPGA provides abundant CRUs, connecting all the resources in FPGA. For example, routing resources distributed in CFU and IOB connect resources in CFU and IOB. Routing resources can automatically be generated by Gowin software. In addition, the GW1NZ series of FPGA Products also provide abundant GCLKs, long wires (LW), global set/reset (GSR), and programming options, etc. See 3.9Long Wire (LW), 3.10Global Set/Reset (GSR), 3.11Programming Configuration for further detailed information. 3.2 Configurable Function Unit The configurable function unit (CFU) is the base cell for the array of the GW1NZ series of FPGA Products. Each CFU consists of a configurable logic unit (CLU) and its routing resource configurable routing unit (CRU). In each CLU, there are four configurable logic slices (CLS). Each CLS contains look-up tables (LUT) and registers, as shown in Figure 3-2 below. DS841-1.6E 7(51) 3 Architecture Figure 3-2 CFU View CFU Carry to Right CLU LUT LUT REG/ SREG REG/ SREG CLU CLS3 CRU LUT REG LUT REG CLS2 LUT REG LUT REG CLS1 LUT REG LUT REG CLS0 3.2 Configurable Function Unit Carry from left CLU Note! SERG needs special patch supporting. Please contact Gowin technical support or local O ffice for this patch. 3.2.1 Look-up Table The CLU supports three operation modes: Basic logic mode, ALU mode, and ROM mode. Basic Logic Mode Each LUT can be configured as one four-input LUT. Higher input number of LUT can be formed by combining the LUT4 together. - Each CLS can form one five-input LUT5. - Two CLSs can form one six-input LUT6. - Four CLSs can form one seven-input LUT7. - Eight CLSs (two CLUs) can form one eight-input LUT8. ALU Mode When combined with carry chain logic, the LUT can be configured as the ALU mode to implement the following functions. - Adder and subtractor - Up/down counter - Comparator,including greater-than, less-than, and not-equal-to - MULT DS841-1.6E 8(51) 3 Architecture 3.2 Configurable Function Unit Memory mode In this mode, a 16 x 4 S-SRAM or ROM can be constructed by using CLSs. This SRAM can be initialized during the device configuration stage. The initialization data can be generated in the bit stream file from Gowin Yunyuan software. 3.2.2 Register Each configurable logic slice (CLS) has two registers (REG), as shown in Figure 3-3 below. Figure 3-3 Register in CFU D CE CLK Q SR GSR Table 3-1 Register Description in CFU Signal I/O Description D I Data input 1 CE I CLK enable, can be high or low effective 2 CLK I SR I GSE3,4 I Clock, can be rising edge or falling edge trigging 2 Set/Reset, can be configured as 2: Synchronized reset Synchronized set Asynchronous reset Asynchronous set Non Global Set/Reset, can be configured as4: Asynchronous reset Asynchronous set Non Q O Register 3.2.3 CRU Note! [1] The source of the signal D can be the output of a LUT, or the input of the CRU; as such, the register can be used alone when LUTs are in use. [2] CE/CLK/SR in CFU is independent. [3] In the GW1NZ series of FPGA products, GSR has its own dedicated network. [4] When both SR and GSR are effective, GSR has higher priority. The main functions of the CRU are as follows: Input selection: Select input signals for the CFU. Configurable routing: Connect the input and output of the CFUs, including inside the CFU, CFU to CFU, and CFU to other functional blocks in FPGA. DS841-1.6E 9(51) 3 Architecture 3.3 IOB 3.3 IOB The IOB in the GW1NZ series of FPGA products includes IO buffer, IO logic, and its routing unit. As shown in Figure 3-4, each IOB connects to two Pins (Marked as A and B). As input, they can be used as a single-end signal; as output, they can be used as an output differential pair or as a single end input/output. Note! GW1NZ-1 I/Os support differential output, rather than differential input. Figure 3-4 IOB Structure View "True" PAD A "Comp" PAD B "True" PAD A "Comp" PAD B Buffer Pair A & B Buffer Pair A & B DI DO TO DI DO TO DI DO TO DI DO TO IO Logic A IO Logic B IO Logic A IO Logic B CLK Routing Output Routing Input CLK Routing Output Routing Input CLK Routing Output Routing Input CLK Routing Output Routing Input Routing Routing IOB Features: VCCO supplied with each bank Supports multiple levels: LVCMOS, PCI, LVTTL, etc. Input hysteresis option Output drive strength option Slew Rate option Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option Hot Socket IO Logic supports basic mode, SRD mode, and generic DDR mode I3C hard core embedded, supports SDR mode Supports differential output, rather than differential input 3.3.1 I/O Buffer GW1NZ series of FPGA products include Bank0 and Bank1, as shown in Figure 3-5. VCCO can be 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V. DS841-1.6E 10(51) 3 Architecture Figure 3-5 I/O Bank Distribution of GW1NZ series of FPGA Products I/O Bank0 3.3 IOB GW1NZ I/O Bank1 GW1NZ series FPGA products contain both LV and UV. LV devices support 1.2V core voltage to meet users' low power needs. ZV devices support 0.9V core voltage. Zero-power consumption can be available for ZV devices. VCCO supplied with I/O Bank can be set as 1.2V, 1.5V, 1.8V, 2.5V, or 3.3V according to requirements. VCCX supports 1.8V, 2.5 V, and 3.3 V power supply. Note! By default, the Gowin Programmable IO is tri-stated weak pull-up. For the VCCO requirements of different I/O standards, see Table 3-2. Table 3-2 Output I/O Standards and Configuration Options I/O output standard LVTTL33 Single/Differ Single end Bank VCCO (V) 3.3 Driver Strength (mA) 4,8,12,16,24 LVCMOS33 Single end 3.3 4,8,12,16,24 LVCMOS25 Single end 2.5 4,8,12,16 LVCMOS18 Single end 1.8 4,8,12 LVCMOS15 Single end 1.5 4,8 LVCMOS12 Single end 1.2 4,8 PCI33 Single end 3.3 N/A LVPECL33E Differential 3.3 16 MLVDS25E Differential 2.5 16 BLVDS25E Differential 2.5 16 RSDS25E Differential 2.5 8 LVDS25E Differential 2.5 8 DS841-1.6E 11(51) 3 Architecture 3.3 IOB Table 3-3 Output I/O Standards and Configuration Options I/O Input Standard LVTTL33 Single/Differ Bank VCCO (V) Single end 1.5/1.8/2.5/3.3 Hysteresis Yes LVCMOS33 Single end 1.5/1.8/2.5/3.3 Yes LVCMOS25 Single end 1.5/1.8/2.5/3.3 Yes LVCMOS18 Single end 1.5/1.8/2.5/3.3 Yes LVCMOS15 Single end 1.2/1.5/1.8/2.5/3.3 Yes LVCMOS12 Single end 1.2/1.5/1.8/2.5/3.3 Yes PCI33 Single end 3.3 Yes Need VREF No No No No No No No 3.3.2 I/O Logic Figure 3-6 shows the I/O logic output of the GW1NZ series of FPGA products. Figure 3-6 I/O Logic Output TCTRL TCFF GND SER TDATA ISI OUTFF IODELAY Figure 3-7 shows the I/O logic input of the GW1NZ series of FPGA products. Figure 3-7 I/O Logic Input CI DI IODELAY INFF DIN IEM IDES Rate Sel Q DS841-1.6E A description of the I/O logic modules of the GW1NZ series of FPGA products is presented below: 12(51) 3 Architecture 3.3 IOB IODELAY See Figure 3-8 for an overview of the IODELAY. Each I/O of the GW1NZ series of FPGA products has an IODELAY cell. A total of 128(0~127) step delay is provided, with one-step delay time of about 30ps. Figure 3-8 IODELAY DI DO DLY UNIT SDTAP SETN DLY ADJ DF VALUE There are two ways to control the delay cell: Static control Dynamic control: usually used to sample delay window together with IEM. The IODELAY cannot be used for both input and output at the same time I/O Register See Figure Figure 3-9 for the I/O register in the GW1NZ series of FPGA products. Each I/O provides one input register, INFF, one output register, OUTFF, and a tristate Register, TCFF. Figure 3-9 Register Structure in I/O Logic D Q CE CLK SR Note! CE can be either active ow (0: enable)or active high (1: enable). CLK can be either rising edge trigger or falling edge trigger. SR can be either synchronous/asynchronous SET or RESET or disable. The register can be programmed as register or latch. IEM IEM is for sampling clock edge and is used in the generic DDR mode, as shown in Figure 3-10. DS841-1.6E 13(51) 3 Architecture 3.3 IOB Figure 3-10 IEM Structure CLK LEAD D IEM MCLK RESET LAG De-serializer DES and Clock Domain Transfer The GW1NZ series of FPGA products provide a simple DES for each input I/O to support advanced I/O protocols. Serializer SER The GW1NZ series of FPGA products provide a simple Serializer SER for each output I/O to support advanced I/O protocols. 3.3.3 I/O Logic Modes The I/O Logic in the GW1NZ series of FPGA products supports several modes. In each operation, the I/O can be configured as output, input, and INOUT or tristate output (output signal with tristate control). The GW1NZ-1 pins IOR6 (A,B,C....J) do not support IO logic. Basic Mode In basic mode, the I/O Logic is as shown in Figure 3-11, and the TC, DO, and DI signals can connect to the internal cores directly through CRU. Figure 3-11 I/O Logic in Basic Mode TC DO IO PAD DI DS841-1.6E 14(51) 3 Architecture 3.3 IOB SDR Mode In comparison with the basic mode, SDR utilizes the IO register, as shown in Figure 3-12. This can effectively improve IO timing. Figure 3-12 I/O Logic in SDR Mode TCTRL D Q CE >CLK SR DOUT O_CE O_CLK O_SR DIN I_CE I_CLK I_SR D Q CE >CLK SR D Q CE >CLK SR IO PAD Note! CLK enable O_CE and I_CE can be configured as active-high or active-low. O_CLK and I_CLK can be either rising edge trigger or falling edge trigger. Local set/reset signal O_SR and I_SR can be synchronized reset, synchronized set, asynchronous reset, asynchronous set, or no-function. I/O in SDR mode can be configured as basic register or latch. Generic DDR Mode Higher speed I/O protocols can be supported in generic DDR mode. Figure 3-13 shows generic DDR input, with the speed ratio of internal logic to PAD 1:2. Figure 3-13 I/O Logic in DDR Input Mode D CLK RESET IDDR CE 2 Q[1:0] Figure 3-14 shows generic DDR output, with a speed ratio of PAD to FPGA internal logic 2:1. DS841-1.6E 15(51) 3 Architecture Figure 3-14 I/O Logic in DDR Output Mode D[1:0] 2 CE ODDR Q CLK RESET 3.3 IOB IDES4 In IDES4 mode, higher I/O speed signals can be supported. The frequency of input signal (D) and the signal Q which is transferred to Pin has a ratio of 4:1. Figure 3-15 I/O Logic in IDES10 Mode D FCLK PCLK RESET IDES4 CE 4 Q[3:0] OSER4 Mode In OSER4 mode, higher speed signals can be supported. The frequency of input signal (D) and the signal Q which is transferred to Pin has a ratio of 4:1. Figure 3-16 I/O Logic in OSER4 Mode TX[1:0] 2 D[3:0] 4 FCLK PCLK RESET OSER4 CE 2 Q[1:0] DS841-1.6E 16(51) 3 Architecture 3.3 IOB IVideo Mode In IVideo mode, higher speed signals can be supported. The signal (D) frequency at the input of this block vs the signal Q which is transferred to core has a ratio of 7:1. Figure 3-17 I/O Logic in IVideo Mode D FCLK PCLK CALIB RESET IVideo CE 7 Q[6:0] Note! IVideo and IDES8/10 will occupy the neighboring I/O logic. If the I/O logic of a single port is occupied, the pin can only be programmed in SDR or BASIC mode. OVideo Mode In OVideo mode, higher speed signals can be supported. The signal (D) frequency at the input of this block vs the signal Q which is transferred to core has a ratio of 7:1. Figure 3-18 I/O Logic in OVideo Mode D[6:0] 7 CE FCLK OVideo PCLK Q RESET IDES8 Mode In IDES8 mode, higher I/O speed signals can be supported. The signal (D) frequency at the input of this block vs the signal Q which is transferred to Pin has a ratio of 1:8. Figure 3-19 I/O Logic in IDES8 Mode D FCLK PCLK RESET IDES8 CE 8 Q[7:0] DS841-1.6E 17(51) 3 Architecture 3.4 I3C Bus OSER8 Mode In OSER8 mode, higher I/O speed signals can be supported. The signal (D) frequency at the input of this block vs the signal Q which is transferred to Pin has a ratio of 1:8. Figure 3-20 I/O Logic in OSER8 Mode TX[3:0] 4 D[7:0] 8 FCLK PCLK RESET OSER8 CE 2 Q[1:0] IDES10 Mode In IDES10 mode, higher I/O speed signals can be supported. The signal (D) frequency at the input of this block vs the signal Q which is transferred to Pin has a ratio of 1:10. Figure 3-21 I/O Logic in IDES10 Mode D FCLK PCLK RESET IDES10 CE 10 Q[9:0] OSER10 Mode In OSER10 mode, higher I/O speed signals can be supported. The signal (D) frequency at the input of this block vs the signal Q which is transferred to Pin has a ratio of 1:10. Figure 3-22 I/O Logic in OSER10 Mode D[9:0] 10 CE FCLK Q OSER10 PCLK RESET 3.4 I3C Bus 3.4.1 Overview GW1NZ series of FPGA products includes a hard core of I3C bus controller, which supports SDR mode. The I3C controller is backwards compatible with I2C features low power, and is high speed and extensible. The I3C bus is compliant with MIPI I3C protocol, adopts register interfaces, and supports operation modes of I3C SDR Master and I3C SDR Slave. DS841-1.6E 18(51) 3 Architecture 3.4 I3C Bus I3C SDR Master Compliance with MIPI I3C protocol; Supports I3C address arbitration detection; Supports Single Data Rate (SDR) mode; The max. data transmission rate can up to 12.5Mbps; Start / Stop / Repeated Start / Acknowledge generation; Start / Stop / Repeated Start detection; Support dynamically allocating address via SETDASA or ENTDAA; Supports Receive/Send data; Supports In-band Interrupts; Supports Hot-Join; Supports dynamically allocating address when hot-join; Supports CCC's command; Supports dynamic adjusting SCL frequency; Compatible with I2C Slave; Adopts register interfaces. I3C SDR Slave Compliance with MIPI I3C protocol; Start / Acknowledge generation; Start / Stop / Repeated Start detection; Support dynamically allocating address via SETDASA or ENTDAA; Receive/Send data; Send an IBI or hot-join request. If more than one slaves send the IBI or hot-join requests, the min. address obtains the arbitration; Static address of Slave configuration; Adopts register interfaces. 3.4.2 Port Signal For the detailed information about I3C port signals, working principle, timing, and examples, please refer to IPUG508-1.2_Gowin I3C SDR IP User Guide. DS841-1.6E 19(51) 3 Architecture 3.4 I3C Bus DS841-1.6E Table 3-4 I3C Port Signals Port Name I/O AAC Input AAO AAS output Input ACC Input ACKHS ACKLS ACO Input Input output ACS Input ADDRS CE CLK CMC CMO CMS DI[7:0] DO[7:0] DOBUF[7:0] Input Input Input Input output Input Input output output LGYC Input LGYO output LGYS PARITYERROR RECVDHS RECVDLS RESET SCLI SCLO SCLOEN SCLPULLO SCLPULLOEN SDAI SDAO SDAOEN SDAPULLO SDAPULLOEN Input output Input Input Input Input output output output output Input output output output output Description The setting to clear ACK response, single pulse signal Output ACK signal Set ACK response, single pulse signal The setting to clear continuous operation mode, single pulse signal Set ACK high-level time Set ACK low-level time Continuous operation mode output Set continuous operation mode, single pulse signal Set slave address Clock enable signal Clock input Clear the current Master role, single pulse signal Output the flag of current master role Set the current Master role, single pulse signal Data input Data output Buffer data output Clear the setting of I2C as the current communication object, single pulse signal Output of I2C as the current communication object Set I2C as the current communication object, single pulse signal Parity error signal Set high-level time of receiving data Set low-level time of receiving data Asynchronous reset, active high I3C serial clock input I3C serial clock line I3C serial clock output enable I3C serial clock pullup output I3C serial clock pullup output enable I3C serial data input I3C serial data output I3C serial data output enable I3C serial data pullup output I3C serial data pullup output enable 20(51) 3 Architecture 3.5 SPMI Port Name SENDAHS SENDALS SENDDHS SENDDLS SIC SIO STRTC STRTO STRTS STATE STRTHDS STOPC STOPO STOPS STOPSUS STOPHDS I/O Input Input Input Input Input output Input output Input output Input Input output Input Input Input Description Set high-level time of sending address Set low-level time of sending address Set high-level time of sending data Set low-level time of sending data Signal of clearing interrupt flag Signal of output signal interrupt Setting of clearing the START command, single pulse signal Output START command Set START command, single pulse signal Output internal state Set the holding time of the START command Clear the STOP command setting, single pulse signal Output the STOP command Set the STOP command, single pulse signal Set the setting time of the STOP command Set the holding time of the STOP command 3.5 SPMI 3.5.1 Overview The GW1NZ series of FPGA products provides SPMI and the SPMI controller IP. As a Master, the GW1NZ device supports for the power management of the external Slave devices via the SPMI interface. As a Slave, it also supports for the FPGA power management. The GW1NZ series of FPGA products supports two ways to control the main power: Using hardware I/O VCCEN: The main power is turned off when VCCEN is 0. The main power is on when VCCEN is 1; Sending the command of shut down by Master: Master sends reset / sleep / wakeup to recover FPGA main power. The main power can also be recovered at low pulse of SPMI_EN. Note! For the detailed information of operation modes, communication modes, commands, and timing, etc, please refer to IPUG529, Gowin SPMI User Guide. DS841-1.6E 21(51) 3 Architecture 3.6 Block SRAM (B-SRAM) 3.5.2 Port Signal Table 3-5 SPMI Port Signal Name SPMI_EN SPMI_CLK SPMI_SCLK SPMI_SDATA I/O input intput inout inout Description SPMI enable signal System clock signal SPMI serial clock signal SPMI serial data signal 3.6 Block SRAM (B-SRAM) 3.6.1 Introduction GW1NZ series FPGA products provide abundant SRAM. The Block SRAM (B-SRAM) is embedded as a row in the FPGA array and is different from S-SRAM (Shadow SRAM). Each B-SRAM occupies three columns of CFU in the FPGA array. Each B-SRAM has 18,432 bits (18Kbits). There are five operation modes: Single Port, Dual Port, Semi-dual Port, ROM, and FIFO. Table 3-6 lists the signals and functional descriptions of B-SRAM. An abundance of B-SRAM resources provide a guarantee for the user's high-performance design. B-SRAM features: Max.18,432 bits per B-SRAM B-SRAM itself can run at 170MHz at max (typical, Read-before-write is 100MHz) Single Port Dual Port Semi-dual Port Parity bits ROM Data width from 1 to 36 bits Mixed clock mode Mixed data width mode Enable Byte operation for double byte or above Normal read and write mode Read-before-write mode Write-through Mode DS841-1.6E 22(51) 3 Architecture 3.6 Block SRAM (B-SRAM) Table 3-6 B-SRAM Signals Port Name DIA DIB ADA ADB CEA CEB RESETA RESETB WREA WREB BLKSELA, BLKSELB CLKA CLKB OCEA OCEB DOA DOB I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Description Port A data input Port B data input Port A address Port B address Clock enable, Port A Clock enable, Port B Register reset, Port A Register reset, Port B Read/write enable, Port A Read/write enable, Port B Block select Read/write cycle clock for Port A input registers Read/write cycle clock for Port B input registers Output enable for Port A registers Output enable for Port B registers Port A data output Port B data output 3.6.2 Configuration Mode The B-SRAM mode in the GW1NZ series of FPGA products supports different data bus widths. See Table 3-7. Table 3-7 Memory Size Configuration Single Port Mode 16K x 1 8K x 2 4K x 4 2K x 8 1K x 16 512 x 32 2K x 9 1K x 18 512 x 36 Dual Port Mode 16K x 1 8K x 2 4K x 4 2K x 8 1K x 16 2K x 9 1K x 18 - Semi-Dual Port Mode 16K x 1 8K x 2 4K x 4 2K x 8 1K x 16 512 x 32 2K x 9 1K x 18 512 x 36 Single Port Mode In the single port mode, B-SRAM can write to or read from one port at one clock edge. During the write operation, the data can show up at the output of B-SRAM. Normal-Write Mode and Writethrough Mode can be supported. When the output register is bypassed, the new data will show at DS841-1.6E 23(51) 3 Architecture 3.6 Block SRAM (B-SRAM) the same write clock rising edge. For further information about Single Port Block Memory ports and the related description, please refer to SUG283E, Gowin Primitives User Guide > 3 Memory. Dual Port Mode B-SRAM support dual port mode. The applicable operations are as follows: Two independent read Two independent write An independent read and an independent write at different clock frequencies For further information about Dual Port Block Memory ports and the related description, please refer to SUG283E, Gowin Primitives User Guide > 3 Memory. Semi-Dual Port Mode Semi-Dual Port supports read and write at the same time on different ports, but it is not possible to write and read to the same port at the same time. The system only supports write on Port A, read on Port B. For further information about Semi-Dual Port Block Memory ports and the related description, please refer to SUG283E, Gowin Primitives User Guide > 3 Memory. Read Only B-SRAM can be configured as ROM. The ROM can be initialized during the device configuration stage, and the ROM data needs to be provided in the initialization file. Initialization completes during the device power-on process. Each B-SRAM can be configured as one 16 Kbits ROM. For further information about Read Only Port Block Memory ports and the related description, please refer to SUG283E, Gowin Primitives User Guide > 3 Memory. DS841-1.6E 24(51) 3 Architecture 3.6 Block SRAM (B-SRAM) 3.6.3 Mixed Data Bus Width Configuration B-SRAM in the GW1NZ series of FPGA products supports mixed data bus width operation. In the dual port and semi-dual port modes, the data bus width for read and write can be different. For the configuration options that are available, please see Table 3-8 and Table 3-9 below. Table 3-8 Dual Port Mixed Read/Write Data Width Configuration Read Port 16K x 1 8K x 2 4K x 4 2K x 8 1K x 16 2K x 9 1K x 18 Write Port 16K x 1 8K x 2 * * * * * * * * * * 4K x 4 * * * * * 2K x 8 * * * * * 1K x 16 * * * * * 2K x 9 * * 1K x 18 * * Note! "*"denotes the modes supported. Table 3-9 Semi Dual Port Mixed Read/Write Data Width Configuration Read Port Write Port 16K x 1 8K x 2 4K x 4 2K x 8 1K x 16 512 x 32 2K x 9 1K x 18 512 x 36 16K x 1 * 8K x 2 * 4K x 4 * 2K x 8 * 1K x 16 * 512 x 32 * 2K x 9 1K x 18 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Note! "*"denotes the modes supported. 3.6.4 Byte-enable The B-SRAM in the GW1NZ series of FPGA products supports byte-enable. For data longer than a byte, the additional bits can be blocked, and only the selected portion can be written into. The blocked bits will be retained for future operation. Read/write enable ports (WREA, WREB), and byte-enable parameter options can be used to control the B-SRAM write operation. 3.6.5 Parity Bit There are parity bits in B-SRAM. The 9th bit in each byte can be used DS841-1.6E 25(51) 3 Architecture 3.6 Block SRAM (B-SRAM) as a parity bit or for data storage. However, the parity operation is not yet supported. 3.6.6 Synchronous Operation All the input registers of B-SRAM support synchronous write; The output registers can be used as pipeline register to improve design performance; The output registers are bypass-able. 3.6.7 Power up Conditions B-SRAM initialization is supported when powering up. During the power-up process, B-SRAM is in standby mode, and all the data outputs are "0". This also applies in ROM mode. 3.6.8 B-SRAM Operation Modes B-SRAM supports five different operations, including two read operations (Bypass Mode and Pipeline Read Mode) and three write operations (Normal Write Mode, Write-through Mode, and Read-before-write Mode). Read Mode Read data from the B-SRAM via output registers or without using the registers. Pipeline Mode While writing in the B-SRAM, the output register and pipeline register are also being written. The data bus can be up to 36 bits in this mode. Bypass Mode The output register is not used. The data is kept in the output of memory array. Figure 3-23 Pipeline Mode in Single Port, Dual Port and Semi Dual Port AD DI Input Memory Pipeline Register Array Register DO WRE CLK OCE DS841-1.6E 26(51) 3 Architecture 3.6 Block SRAM (B-SRAM) CLKA DIA Input Register ADA Memory Array Input Register ADB CLKB Pipeline Register OCEB DIA ADA WREA Input Register CLKA OCEA Pipeline Register Memory Array DOB Input Register Pipeline Register DIB ADB WREB CLKB OCEB DOA DOB Write Mode NORMAL WRITE MODE In this mode, when the user writes data to one port, and the output data of this port does not change. The data written in will not appear at the read port. WRITE-THROUGH MODE In this mode, when the user writes data to one port, and the data written in will also appear at the output of this port. READ-BEFORE-WRITE MODE In this mode, when the user writes data to one port, and the data written in will be stored in the memory according to the address. The original data in this address will appear at the output of this port. DS841-1.6E 27(51) 3 Architecture 3.6 Block SRAM (B-SRAM) 3.6.9 Clock Operations Table 3-10 lists the clock operations in different B-SRAM modes: Table 3-10 Clock Operations in Different B-SRAM Modes Clock Operations Independent Clock Mode Read/Write Clock Mode Single Port Clock Mode Dual Port Mode Yes Yes No Semi-Dual Port Mode No Yes No Single Port Mode No No Yes Independent Clock Mode Figure 3-24 shows the independent clocks in dual port mode with each port with one clock. CLKA controls all the registers at Port A; CLKB controls all the registers at Port B. Figure 3-24 Independent Clock Mode WREA WREB ADA DIA CLKA DOA Input Register Output Register Memory Array ADB Input Register DIB CLKB Output Register DOB WREA WREB Read/Write Clock Operation Figure 3-25 shows the read/write clock operations in the semi-dual port mode with one clock at each port. The write clock (CLKA) controls Port A data inputs, write address and write enable signals. The read clock (CLKB) controls Port B data output, read address, and read enable signals. Figure 3-25 Read/Write Clock Mode Input Register Input Memory CLKA Register Array CLKB Pipeline Register DS841-1.6E 28(51) 3 Architecture 3.7 User Flash Single Port Clock Mode Figure 3-26shows the clock operation in single port mode. Figure 3-26 Single Port Clock Mode WRE AD DI Input Register CLK DO Output Register Memory Array WRE 3.7 User Flash 3.7.1 Introduction GW1NZ-1 offers User Flash, the features are shown below: 10,000 write cycles Capacity: 64K bits Greater than ten years' data retention at +85 Supports page erasure: 2,048 bytes per page Quick page erasure/Write operation Clock frequency: 40MHz Write operation time: 16s Page erasure time: 120 ms Electric current - Read Operation: 2.19 mA/25 ns (VCC) & 0.5 mA/25 ns (VCCX) (MAX). - Write operation/erase operation: 12/12 mA(MAX) 3.7.2 Mode The User Flash in GW1NZ series of FPGA products contains two modes: Normal mode and sleep mode. Normal mode: User flash is turned on by default. Users can perform erase/write/read operations after the device is power on. It cannot be turned off. Sleep mode: User flash is turned off by default to save power. Users can turn on/turn off the user flash mode using "Sleep" port. When the user flash is turned on, it's the same as the normal mode user flash, and users can perform erase/write/read operations. The GW1NZ LV/ZV devices with different speeds offer different user flash modes. For further detailed information, please refer to Table 3-11. DS841-1.6E 29(51) 3 Architecture 3.7 User Flash Mode Table 3-11 User Flash Modes Default Status Turn on/Turn off Device Version LV Normal mode On No ZV Sleep mode Off Yes ZV Speed Grade C6/I5 C5/I4 C5/I4 I2 I3 3.7.3 Port Signal SeeFigure 3-27 for the User Flash signal diagram of GW1NZ-1. Figure 3-27 GW1NZ-1 User Flash Ports XADR[n:0] n+1 YADR[5:0] 6 DIN[31:0] 32 DOUT[31:0] 32 NVSTR NVM XE YE SE PROG ERASE SLEEP ** Table 3-12 Flash Module Signal Description Pin name1 I/O XADR[5:0]2 I YADR[5:0]2 I DIN[31:0] I Description X address bus, used to select one row within a page of main memory block. Y address bus, used to select one column within a row of memory block. Data input bus. DOUT[31:0] O XE2 I YE2 I SE2 I Data output bus. X address enable signal, if XE is 0, all of row addresses are not enabled. Y address enable signal, if YE is 0, all of column addresses are not enabled. Detect amplifier enable signal, active high. ERASE I Erase port, active-high. PROG I Programming port, active-high. NVSTR I SLEEP** I4 Flash data storage port, active-high. Used to turn on/turn off user falsh. High level: On; Low level: Off. Note! [1] Port names of Control, address, and data signals. [2] The read operation is valid only if XE = YE = VCC and SE meets the pulse timing requirements (Tpws, Tnws). The address of read data is determined by XADR [5: 0] and YADR [5: 0]. [3] The power pin and the ground pin connect in FPGA. DS841-1.6E 30(51) 3 Architecture 3.8 Clock [4] Only supported in user flash in sleep mode. 3.7.4 Operation Modes Table 3-13 Truth Table in User Mode Mode XE YE SE PROG Read mode H H H L Programming mode H H L H Page Mode Erasure H L L L Note! "H" and "L" means high level and low level of VCC. ERASE L L H NVSTR L H H 3.8 Clock 3.8.1 Global Clock The GCLK is distributed in GW1NZ-1 as two quadrants, L and R. Each quadrant provides eight GCLKs. Each GCLK has 12 optional clock sources. The optional clock resources of GCLK can be pins or CRU. Users can employ dedicated pins as clock resources to achieve better timing. Figure 3-28 GW1NZ-1 Clock Resources I/O Bank0 T R I/O Bank1 IO Bank HCLK DS841-1.6E 31(51) 3 Architecture Figure 3-29 GCLK Quadrant Distribution CE GCLK0 CE GCLK1 CE GCLK2 CE GCLK3 56:1 DQCE 56:1 DQCE 56:1 DQCE DQCE 56:1 DQCE 56:1 DQCE 56:1 CE GCLK0 CE GCLK1 CE GCLK2 CE GCLK3 DQCE 56:1 56:1 DQCE L CE GCLK4 CE GCLK4 DQCE 56:1 56:1 DQCE CE GCLK5 CE GCLK5 DQCE 56:1 56:1 DQCE SELECTOR[3:0] 4 SELECTOR[3:0] 4 56:1 56:1 56:1 56:1 GCLK6 GCLK6 R DCS DCS 56:1 56:1 56:1 56:1 SELECTOR[3:0] 4 SELECTOR[3:0] 4 56:1 56:1 56:1 56:1 GCLK7 GCLK7 3.8 Clock DCS DCS 56:1 56:1 56:1 56:1 GCLK0~GCLK5 can be turned on or off by Dynamic Quadrant Clock Enable (DQCE). When GCLK0~GCLK5 in the quadrant is off, all the logic driven by it will not toggle; therefore, lower power can be achieved. Figure 3-30 DQCE Concepts DQCE CE D Q CLK CLKIN CLKOUT DS841-1.6E 32(51) 3 Architecture 3.8 Clock GCLK6~GCLK7 of each quadrant is controlled by the DCS, as shown in Figure 3-31. Select dynamically between CLK0~CLK3 by CRU, and output a glitch-free clock. Figure 3-31 DCS Concept CLKSEL [3:0] SELFORCE CLK0 CLK1 CLK2 CLK3 4 DCS CLKOUT DCS can be configured in the following modes: 1. DCS Rising Edge Stay as 1 after current selected clock rising edge, and the new select clock will be effective after its first rising edge, as shown in Figure 3-32. Figure 3-32 DCS Rising Edge 2. DCS Falling Edge Stay as 0 after current selected clock falling edge, and the new select clock will be effective after its first falling edge, as shown in Figure 3-33. Figure 3-33 DCS Falling Edge 3. Clock Buffer Mode In this mode, the DCS acts as a clock buffer. DS841-1.6E 33(51) 3 Architecture 3.8 Clock 3.8.2 PLL PLL (Phase-locked Loop) is one kind of a feedback control circuit. The frequency and phase of the internal oscillator signal is controlled by the external input reference clock. PLL blocks provide the ability to synthesize clock frequencies. Frequency adjustment (multiply and division), phase adjustment, and duty cycle can be adjusted by configuring the parameters. See Figure 3-34 for the PLL structure. Figure 3-34 PLL Structure IDSEL[5:0] ODSEL[5:0] CLKIN CLKFB FBDSEL[5:0] 6 6 IDIV FBDIV PFD + ICP VCO VCODIV LPF PS&DCA 6 LOCK Detector /3 DIV SDIV 4 4 4 LOCK CLKOUT CLKOUTP CLKOUTD3 CLKOUTD DS841-1.6E RESET RESET_P DUTYDA[3:0] PSDA[3:0] FDLY[3:0] Table 3-14 PLL Ports Definition Port Name CLKIN[5:0] CLKFB RESET RESET_P IDSEL [5:0] FBDSEL [5:0] PSDA [3:0] DUTYDA [3:0] FDLY[3:0] CLKOUT CLKOUTP CLKOUTD Signal I I I I I I I I I Output Output Output CLKOUTD3 LOCK Output Output Description Reference clock input Feedback clock input PLL reset PLL Power Down Dynamic IDIV control: 1~64 Dynamic FBDIV control:1~64 Dynamic phase control (rising edge effective) Dynamic duty cycle control (falling edge effective) CLKOUTP dynamic delay control Clock output with no phase and duty cycle adjustment Clock output with phase and duty cycle adjustment Clock divider from CLKOUT and CLKOUTP (controlled by SDIV) clock divider from CLKOUT and CLKOUTP (controlled by DIV3 with the constant division value 3) PLL lock status: 1 locked, 0 unlocked The PLL reference clock source can come from an external PLL pin or from internal routing GCLK, HCLK, or general data signal. PLL feedback 34(51) 3 Architecture 3.9 Long Wire (LW) signal can come from the external PLL feedback input or from internal routing GCLK, HCLK, or general data signal. For PLL features of GW1NZ series of FPGA products, please refer to 4.4.5 PLL Switching Characteristics. PLL can adjust the frequency of the input clock CLKIN (multiply and division). The formulas for doing so are as follows: 1. fCLKOUT = (fCLKIN*FBDIV)/IDIV; 2. fVCO = fCLKOUT*ODIV; 3. fCLKOUTD = fCLKOUT/SDIV; 4. fPFD = fCLKIN/IDIV = fCLKOUT/FBDIV. Note! fCLKIN: The frequency of input clock CLKIN; fCLKOUT: The clock frequency of CLKOUT and CLKOUTP fCLKOUTD: The clock frequency of CLKOUTD, and CLKOUTD is the clock CLKOUT after division fPFD: PFD Frequency, and the minimum value of fPFD should be no less than 3MHz. Adjust IDIV, FBDIV, ODIV, and SDIV to achieve the required clock frequency. 3.8.3 HCLK HCLK is the high-speed clock in the GW1NZ series of FPGA products. It can support high-performance data transfer and is mainly suitable for source synchronous data transfer protocols. See Figure Figure 3-35. HCLK can be used for the whole I/O Bank. Figure 3-35 GW1NZ-1 HCLK Distribution I/O Bank0 T R I/O Bank1 I/O Bank1 IO Bank HCLK 3.9 Long Wire (LW) As a supplement to the CRU, the GW1NZ series of FPGA products provides another routing resource, Long wire, which can be used as clock, clock enable, set/reset,or other high fan out signals. DS841-1.6E 35(51) 3 Architecture 3.10 Global Set/Reset (GSR) 3.10 Global Set/Reset (GSR) A global set/reset (GSR) network is built in the GW1NZ series of FPGA product. There is a direct connection to core logic. It can be used as asynchronous/synchronous set. The registers in CFU and I/O can be individually configured to use GSR. 3.11 Programming Configuration The GW1NZ series of FPGA products support SRAM and Flash. The Flash programming mode supports on-chip Flash and off-chip Flash. The GW1NZ series of FPGA products support DUAL BOOT, providing a selection for users to backup data to off chip Flash according to requirements. Besides JTAG, the GW1NZ series of FPGA products also supports GOWINSEMI's own configuration mode: GowinCONFIG (AUTO BOOT, SSPI, MSPI, DUAL BOOT, SERIAL, and CPU). All the devices support JTAG and AUTO BOOT. For the detailed information, please refer to UG290, Gowin FPGA Products Programming and Configureation User Guide. 3.11.1 SRAM Configuration When you adopt SRAM to configure the device, every time the device is powered on, the bit stream file needs to be downloaded to configure the device. 3.11.2 Flash Configuration The Flash configuration data is stored in the on-chip flash. Each time the device is powered on, the configuration data is transferred from the Flash to the SRAM, which controls the working of the device. This mode can complete configuration within a few ms, and is referred to as "Quick Start". The GW1NZ series of FPGA products also support off-chip Flash configuration and dual-boot. Please refer to UG290, Gowin FPGA Products Programming and Configuration User Guide for more detailed information. 3.12 On Chip Oscillator There is an on chip oscillator in each of the GW1NZ series of FPGA product. The on chip oscillator provides a programmable user clock with precision of ±5%. During the configuration process, it can provide a clock for the MSPI mode. See Table 3-15 for the output frequency. DS841-1.6E 36(51) 3 Architecture 3.12 On Chip Oscillator Table 3-15 Oscillator Output Frequency Options Mode 0 1 2 3 4 5 6 7 Frequency 2.5MHz1 5.4MHz 5.7MHz 6.0MHz 6.3MHz 6.6MHz 6.9MHz 7.4MHz Mode 8 9 10 11 12 13 14 15 Frequency 7.8MHz 8.3MHz 8.9MHz 9.6MHz 10.4MHz 11.4MHz 12.5MHz 13.9MHz Mode 16 17 18 19 20 21 22 23 Frequency 15.6MHz 17.9MHz 21MHz 25MHz 31.3MHz 41.7MHz 62.5MHz 125MHz2 Note! [1] The default frequency is 2.5MHz. [2] 125 MHz is not suitable for MSPI. The on-chip oscillator also provides a clock resource for user designs. Up to 64 clock frequencies can be obtained by setting the parameters. The following formula is employed to get the output clock frequency: fout=250MHz/Param. "Param" is the configuration parameter with a range of 2~128. It supports even number only. DS841-1.6E 37(51) 4 AC/DC Characteristic 4.1 Operating Conditions 4AC/DC Characteristic 4.1 Operating Conditions 4.1.1 Absolute Max. Ratings Table 4-1 Absolute Max. Ratings Name VCC VCCO VCCX Storage Temperature Junction Temperature Description Core voltage I/O Bank Power Auxiliary Power Storage Temperature Junction Temperature Min. -0.5V -0.5V -0.5V -65 -40 Max. 1.32V 3.75V 3.75V +150 +125 4.1.2 Recommended Operating Conditions Table 4-2 Recommended Operating Conditions Name Description LV: Core Power VCC VCCO ZV: Core Power I/O Bank Power VCCX Auxiliary voltage TJCOM Junction temperature Commercial operation TJIND Junction temperature Industrial operation 4.1.3 Power Supply Ramp Rates Table 4-3 Power Supply Ramp Rates Name Description Min. TRAMP Power supply ramp rates for all power supplies 0.6mV/s Min. 1.14V 0.855V 1.14V 1.71V 0 -40 Typ. - Max. 1.26V 0.945V 3.465V 3.465V +85 +100 Max. 6mV/s DS841-1.6E 38(51) 4 AC/DC Characteristic 4.2 ESD 4.1.4 Hot Socket Specifications Table 4-4 Hot Socket Specifications Name IHS IHS Description Input or I/O leakage current Input or I/O leakage current Condition 0<VIN<VIH(MAX) 0<VIN<VIH(MAX) I/O Type I/O TDI,TDO, TMS,TCK Max. 150uA 120uA 4.1.5 POR Specification Table 4-5 POR Specification Name POR Voltage Value Description Power on reset voltage of Vcc Min. TBD Max. TBD 4.2 ESD Table 4-6 GW1NZ ESD - HBM Device GW1NZ-1 CS16 TBD FN32 HBM>1,000V FN32F HBM>1,000V Table 4-7 GW1NZ ESD - CDM Device GW1NZ-1 CS16 TBD FN32 CDM>500V FN32F CDM>500V 4.3 DC Characteristic 4.3.1 DC Electrical Characteristics over Recommended Operating Conditions Table 4-8 DC Electrical Characteristics over Recommended Operating Conditions Name IIL,IIH IPU IPD IBHLS IBHHO IBHLO IBHHO Description Input or I/O leakage I/O Active Pull-up Current (I/O Active Pull-up Current) I/O Active Pull-down Current Bus Hold Low Sustaining Current Bus Hold High Sustaining Current Bus HoldLow Overdrive Current Bus HoldHigh Overdrive Current Condition VCCO<VIN<VIH (MAX) 0V<VIN<VCCO 0<VIN<0.7VCCO VIL (MAX)<VIN<VCCO VIN=VIL (MAX) VIN=0.7VCCO 0VINVCCO 0VINVCCO Min. Typ. - - - - -30 µA - Max. 210 µA 10µA -150 µA 30 µA - 30 µA - -30 µA - - - - - 150 µA 150 µA -150 µA DS841-1.6E 39(51) 4 AC/DC Characteristic 4.3 DC Characteristic Name VBHT C1 VHYST Description Bus hold trigger points I/O Capacitance (I/O Capacitance) Hysteresis for Schmitt Trigge inputs (Hysteresis for Schmitt Trigger inputs) Condition VCCO=3.3V, Hysteresis= Large VCCO=2.5V, Hysteresis= Large VCCO=1.8V, Hysteresis= Large VCCO=1.5V, Hysteresis= Large VCCO=3.3V, Hysteresis= Small VCCO=2.5V, Hysteresis= Small VCCO=1.8V, Hysteresis= Small VCCO=1.5V, Hysteresis= Small Min. Typ. VIL (MAX) - 5 pF - 482mV - 302mV - 152mV - 94mV - 240mV - 150mV - 75mV - 47mV Max. VIH (MIN) 8 pF - DS841-1.6E 40(51) 4 AC/DC Characteristic 4.3 DC Characteristic 4.3.2 Static Current Table 4-9 Static Supply Current (LV Device) Name ICC ICCX ICCO Description Core current (Vcc=1.2V) VCCX current (VCCX=3.3V) VCCX current (VCCX=2.5V) I/O Bank current (VCCO=2.5V) Device GW1NZ-1 GW1NZ-1 GW1NZ-1 GW1NZ-1 Typ. 3mA - Table 4-10 Static Supply Current (ZV Device) Name ICC ICCX ICCO Description Core current (Vcc=0.9V) VCCX current (VCCX floating) VCCX current (VCCX=1.8V~3.3V) I/O Bank current (VCCO=3.3V) Device GW1NZ-ZV1FN32C5/I4 GW1NZ-ZV1CS16C5/I4 GW1NZ-ZV1FN32I3 GW1NZ-ZV1CS16I3 GW1NZ-ZV1FN32I2 GW1NZ-ZV1CS16I2 GW1NZ-ZV1FN32C5/I4 GW1NZ-ZV1CS16C5/I4 GW1NZ-ZV1FN32I3 GW1NZ-ZV1CS16I3 GW1NZ-ZV1FN32I2 GW1NZ-ZV1CS16I2 GW1NZ-ZV1FN32C5/I4 GW1NZ-ZV1CS16C5/I4 GW1NZ-ZV1FN32I3 GW1NZ-ZV1CS16I3 GW1NZ-ZV1FN32I2 GW1NZ-ZV1CS16I2 GW1NZ-ZV1FN32C5/I4 GW1NZ-ZV1CS16C5/I4 GW1NZ-ZV1FN32I3 GW1NZ-ZV1CS16I3 GW1NZ-ZV1FN32I2 GW1NZ-ZV1CS16I2 Typ. 50uA 40uA 30uA 0uA 0uA 0uA 1uA 1uA 1uA 0uA 0uA 0uA Note! After device wake up, user can turn off external Vccx when they do not use user flash and chip still functional. The typical values in the table above are tested at room temperature. In zero power cirucumstance, if users use MODE pin, the PULL_MODE of this pin must be configured as KEEPER. DS841-1.6E 41(51) 4 AC/DC Characteristic 4.3 DC Characteristic 4.3.3 I/O Operating Conditions Recommended Table 4-11 I/O Operating Conditions Recommended Name LVTTL33 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL15 SSTL18_I SSTL18_II SSTL25_I SSTL25_II SSTL33_I SSTL33_II HSTL18_I HSTL18_II HSTL15 PCI33 LVPECL33E MLVDS25E BLVDS25E RSDS25E LVDS25E SSTL15D SSTL18D_I SSTL18D_II SSTL25D_I SSTL25D_II SSTL33D_I SSTL33D_II HSTL15D HSTL18D_I HSTL18D_II Output VCCO (V) Min. Typ. 3.135 3.3 3.135 3.3 2.375 2.5 1.71 1.8 1.425 1.5 1.14 1.2 1.425 1.5 1.71 1.8 1.71 1.8 2.375 2.5 2.375 2.5 3.135 3.3 3.135 3.3 1.71 1.8 1.71 1.8 1.425 1.5 3.135 3.3 3.135 3.3 2.375 2.5 2.375 2.5 2.375 2.5 2.375 2.5 1.425 1.5 1.71 1.8 1.71 1.8 2.375 2.5 2.375 2.5 3.135 3.3 3.135 3.3 1.425 1.575 1.71 1.8 1.71 1.8 Max. 3.465 3.465 2.625 1.89 1.575 1.26 1.575 1.89 1.89 2.645 2.645 3.465 3.465 1.89 1.89 1.575 3.465 3.465 2.625 2.625 2.625 2.625 1.575 1.89 1.89 2.625 2.625 3.465 3.465 1.89 1.89 1.89 Input VREF (V) Min. Typ. - - - - - - - - - - - - 0.68 0.75 0.833 0.9 0.833 0.9 1.15 1.25 1.15 1.25 1.3 1.5 1.3 1.5 0.816 0.9 0.816 0.9 0.68 0.75 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Max. 0.9 0.969 0.969 1.35 1.35 1.7 1 1.08 1.08 0.9 - DS841-1.6E 42(51) 4 AC/DC Characteristic 4.3 DC Characteristic 4.3.4 Single-Ended IO DC Electrical Characteristic Table 4-12 Single-Ended IO DC Electrical Characteristic Name VIL Min Max LVCMOS33 LVTTL33 -0.3V 0.8V LVCMOS25 -0.3V 0.7V LVCMOS18 -0.3V 0.35 x VCCO VIH VOL Min Max (Max) 2.0V 0.4V 3.6V 0.2V 1.7V 0.4V 3.6V 0.2V 0.4V 0.65 x VCCO 3.6V VOH (Min) VCCO-0.4V VCCO-0.2V VCCO-0.4V VCCO-0.2V VCCO0.4V IOL (mA) 4 8 12 16 24 0.1 4 8 12 16 0.1 4 8 12 IOH (mA) -4 -8 -12 -16 -24 -0.1 -4 -8 -12 -16 -0.1 -4 -8 -12 0.2V VCCO-0.2V 0.1 -0.1 4 -4 LVCMOS15 -0.3V 0.35 x VCCO 0.4V 0.65 x VCCO 3.6V VCCO-0.4V 8 -8 0.2V VCCO-0.2V 0.1 -0.1 2 -2 LVCMOS12 -0.3V 0.35 x VCCO 0.4V 0.65 x VCCO 3.6V VCCO-0.4V 6 -6 PCI33 SSTL33_I -0.3V 0.3 x VCCO -0.3V VREF-0.2V 0.2V VCCO-0.2V 0.1 -0.1 0.5 x VCCO 3.6V 0.1 VCCO x 0.9 x VCCO 1.5 -0.5 VREF+0.2V 3.6V 0.7 VCCO-1.1V 8 -8 SSTL25_I -0.3V VREF-0.18V VREF+0.18V 3.6V 0.54V VCCO-0.62V 8 -8 SSTL25_II -0.3V VREF-0.18V VREF+0.18V 3.6V NA NA NA NA SSTL18_II -0.3V VREF-0.125V VREF+0.125V 3.6V NA NA NA NA SSTL18_I -0.3V VREF-0.125V VREF+0.125V 3.6V 0.40V VCCO-0.40V 8 -8 SSTL15 -0.3V VREF-0.1V VREF+ 0.1V 3.6V 0.40V VCCO-0.40V 8 -8 HSTL18_I -0.3V VREF-0.1V VREF+ 0.1V 3.6V 0.40V VCCO-0.40V 8 -8 HSTL18_II -0.3V VREF-0.1V VREF+ 0.1V 3.6V NA NA NA NA HSTL15_I -0.3V VREF-0.1V VREF+ 0.1V 3.6V 0.40V VCCO-0.40V 8 -8 HSTL15_II -0.3V VREF-0.1V VREF+ 0.1V 3.6V NA NA NA NA DS841-1.6E 43(51) 4 AC/DC Characteristic 4.4 Switching Characteristic 4.4 Switching Characteristic 4.4.1 CFU Block Internal Timing Parameters Table 4-13 CFU Block Internal Timing Parameters Name tLUT4_CFU tLUT5_CFU tLUT6_CFU tLUT7_CFU tLUT8_CFU tSR_CFU tCO_CFU Description LUT4 delay LUT5 delay LUT6 delay LUT7 delay LUT8 delay Set/Reset to Register output Clock to Register output Speed Grade Unit Min Max - 0.674 ns - 1.388 ns - 2.01 ns - 2.632 ns - 3.254 ns - 1.86 ns - 0.76 ns 4.4.2 Clock and I/O Switching Characteristics Table 4-14 Clock and I/O Switching Characteristics Name Clocks Descri ption Device -5 Min -6 Max Min Unit Max TBD TBD TBD TBD TBD TBD Pin-LUT-Pin Delay TBD TBD TBD TBD TBD TBD General I/O Pin Parameters TBD TBD TBD TBD TBD TBD 4.4.3 B-SRAM Switching Characteristics Table 4-15 B-SRAM Internal Timing Parameters Name Description tCOAD_BSRAM tCOOR_BSRAM Clock to output from read address/data Clock to output from output register 4.4.4 On chip Oscillator Output Frequency Table 4-16 On chip Oscillator Output Frequency Speed Grade Unit Min Max - 5.10 ns - 0.56 ns Name fMAX tDT tOPJIT Description Min. Output Frequency (0 to 85) Output Frequency (-40 to +100) Output Clock Duty Cycle 106.25MHz 100MHz 43% Output Clock Period Jitter 0.01UIPP Typ. 125MHz 125MHz 50% 0.012UIPP Max. 143.75MHz 150MHz 57% 0.02UIPP DS841-1.6E 44(51) 4 AC/DC Characteristic 4.5 User Flash Characteristic 4.4.5 PLL Switching Characteristics Table 4-17 PLL Switching Characteristics Device LV/ZV LV GW1NZ-1 ZV Speed Grade C6/I5 C5/I4 C5/I4 I3 I2 Name CLKIN PFD VCO CLKOUT CLKIN PFD VCO CLKOUT CLKIN PFD VCO CLKOUT CLKIN PFD VCO CLKOUT CLKIN PFD VCO CLKOUT Min. 3MHZ 400MHZ 3MHZ 400MHZ 400MHZ 800MHZ 3.125MHZ 400MHZ 3MHZ 320MHZ 3MHZ 320MHZ 320MHZ 640MHZ 2.5MHZ 360MHZ 3MHZ 200MHZ 3MHZ 200MHZ 200MHZ 400MHZ 1.5625MHZ 200MHZ 3MHZ 150MHZ 3MHZ 150MHZ 150MHZ 300MHZ 1.171875MHZ 150MHZ 3MHZ 100MHZ 3MHZ 100MHZ 100MHZ 200MHZ 0.78125MHZ 100MHZ 4.5 User Flash Characteristic 4.5.1 DC Characteristic Table 4-18 User Flash DC Characteristics Name Parame Max. ter VCC3 VCCX Unit Read mode (w/I 25ns)1 2.19 0.5 mA Write mode Erase mode ICC12 0.1 12 0.1 12 mA mA Page Erasure Mode 0.1 12 mA Read mode static current ICC2 (25-50ns) 980 25 A Standby mode ISB 5.2 20 A Wake-up Time NA NA NA NA NA 0 Condition Min. Clcok period, duty cycle 100%, VIN = "1/0" XE=YE=SE="1", between T=Tacc and T=50ns, I/O=0mA; later than T=50ns, read mode is turned off, and I/O current is the current of standby mode. VSS, VCCX, and VCC DS841-1.6E 45(51) 4 AC/DC Characteristic 4.5 User Flash Characteristic Floating mode3 IPD 0 0 A 7us Typical Value (Room temperature: 25) VCCX=0 Standby mode ISB Floating mode3 IPD 0.4 7.5 A 0 0 A 0 3.5us VSS, VCCX, and VCC VCCX=0 Note! [1] means the average current, and the peak value is higher than the average one. [2] Calculated in different Tnew clock periods. - Tnew< Tacc is not allowed - Tnew = Tacc - Tacc< Tnew - 50ns: ICC1 (new) = (ICC1 - ICC2)(Tacc/Tnew) + ICC2 - Tnew>50ns: ICC1 (new) = (ICC1 - ICC2)(Tacc/Tnew) + 50ns x ICC2/Tnew + ISB - t > 50ns, ICC2 = ISB [3] Only supported in user flash in sleep mode. DS841-1.6E 46(51) 4 AC/DC Characteristic 4.5 User Flash Characteristic 4.5.2 Timing Parameters Table 4-19 User Flash Timing Parameters User Modes Parameter Name WC1 TC Access time2 BC LT Tacc3 WC Program/Erase to data storage Data storage hold time Data storage hold time (Overall erase) Time from data storage to program setup Program hold time Write time Write ready time Erase hold time Time from control signal to write/Erase setup Time from SE to read setup E pulse high level time Adress/data setup time Adress/data hold time Data hold-up time WC1 Read mode TC address hold BC time3 LT Tnvs Tnvh Tnvh1 Tpgs Tpgh Tprog Twpr Twhd Tcps Tas Tpws Tads Tadh Tdh Tah WC SE pulse low level time Recovery time Data storage time Erasure time Overall erase time Wake-up time from power down to standby mode Standby hold time VCC setup time VCCX hold time Tnws Trcv Thv4 Terase Tme Twk_pd Tsbh Tps Tph Min. 5 5 100 10 20 8 >0 >0 -10 0.1 5 20 20 0.5 25 22 21 21 25 2 10 100 100 7 100 0 0 Note! [1] The parameter values may change; [2] The values are simulation data only. DS841-1.6E Max. Unit 25 ns 22 ns 21 ns 21 ns 25 ns - s - s - s - s - ns 16 s - ns - ns - ns - ns - ns - ns - ns - ns - ns - ns - ns - ns - ns - ns - s 6 ms 120 ms 120 ms - s - ns - ns - ns 47(51) 4 AC/DC Characteristic 4.5 User Flash Characteristic [3]After XADR, YADR, XE, and YE are valid, Tacc start time is SE rising edge. DOUT is kept until the next valid read operation; [4]Thv is the time between write and the next erasure.The same address can not be written twice before erasure, so does the same register. This limitation is for safety; [5]Both the rising edge time and falling edge time for all waveform is 1ns; [6] TX, YADR, XE, and YE hold time need to be Tacc at leaset, and Tacc start from SE rising edge. 4.5.3 Operation Timing Diagrams Figure 4-1 Read Mode Figure 4-2 Write Mode DS841-1.6E 48(51) 4 AC/DC Characteristic Figure 4-3 Erasure Mode 4.6 Configuration Interface Timing Specification 4.6 Configuration Interface Timing Specification The GW1NZ series of FPGA products GowinCONFIG support six configuration modes: AUTO BOOT, DUAL BOOT, MSPI, SSPI, SERIAL, and CPU. For more detailed information, please refer to UG290, Gowin FPGA Products Programming and Configuration User Guide. DS841-1.6E 49(51) 5 Ordering Information 5.1 Part Name 5Ordering Information 5.1 Part Name Figure 5-1 Part Naming ExampleES GW1NZ - XX X XXXXXX ES Product Series GW1NZ Core Supply Voltage LV 1.2V ZV 0.9V Logic Density 1 1,152 LUTs Optional Suffix ES Engineering Sample Package Type FN32F (QFN32F, 0.4mm) CS16 (WLCSP16, 0.4mm) QN48 (QFN48, 0.4mm) DS841-1.6E 50(51) 5 Ordering Information 5.2 Package Mark Figure 5-2 Part Naming ExampleProduction GW1NZ - XX X XXXXXX CX/IX Product Series GW1NZ Core Supply Voltage LV 1.2V ZV 0.9V Logic Density 1 1,152 LUTs Grade C Commercial 0 to 85 I Industrial -40 to100 Speed 2 Slowest /3 /4 /5 /6 Fastest Package Type FN321 (QFN32, 0.4mm) FN32F (QFN32F, 0.4mm) CS16 (WLCSP16, 0.4mm) QN48 (QFN48, 0.4mm) Note! [1] FN32 is the legacy version. For the further detailed information about the package type and pin number, please refer to 2.2 Product Resources and 2.3 Package Information. The LittleBee® family devices and Arora family devices of the same speed level have different speed. Both "C" and "I" are used in partial GW1NZ device part name marking. GOWIN devices are screened using industrial standards, so one same device can be used for both industrial (I) and commercial (C) applications. The maximum temperature of the industrial grade is 100, and the maximum temperature of the commercial grade is 85. Therefore, if the same chip meets the speed level 5 in the commercial grade application, the speed level is 4 in the industrial grade application. 5.2 Package Mark The device information of GOWINSEMI is marked on the chip surface, as shown in Figure 5-3. Figure 5-3 Package Mark Part Number Date Code Lot Number GW1NZ-ZV1FN32C6/I5 YYWW LLLLLLLLL GW1NZ-ZV1 F N 3 2 C 6 / I 5 YY WW L LL L LL L LL Part Number Date Code Lot Number Note! The first two lines in the right figure above are the "Part Number". DS841-1.6E 51(51)Microsoft Word 2010 Microsoft Word 2010