1994 Philips IC13 Programmable Logic Devices

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INTEGRATED CIRCUITS

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Electronics Group

. (408) 942-4600

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Philips Semiconductors
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PHILIPS

Programmable Logic Devices

CONTENTS

page

PREFACE

3

SECTION 1 GENERAL INFORMATION

5

SECTION2 INTRODUCTION

15

SECTION3 PAL DEVICES

35

SECTION4 PROGRAMMABLE LOGIC ARRAY DEVICES 177

SECTION5 PROGRAMMABLE LOGIC SEQUENCER

DEVICES

235

SECTIONS LOW VOLT DEVICES

431

SECTION7 PROGRAMMABLE MACRO LOGIC DEVICES 489

SECTIONS MILITARY SELECTION GUIDE

453

SECTION9 DEVELOPMENT SOFTWARE

507

SECTION 10 PROGRAMMER/SOFTWARE SUPPORT

511

SECTION 11 APPLICATION NOTES

535

SECTION 12 PACKAGE OUTLINE DRAWINGS

875

SECTION 13 SALES OFFICES, REPRESENTATIVES,

AND DISTRIBUTORS

893

---

APPENDIX A DATA HANDBOOK SYSTEM

896

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance.. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North American Philips Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors and Philips Electronics North America Corporation registers eligible circuits under the Semiconductor Chip Protection Act
© Copyright Philips Electronics North America Corporation 1993
All rights reserved

Progranvnable Logic Devices

Preface

The 1994 Philips Semiconductors Programmable Logic Devices Data Handbook contains all the information a designer needs to implement virtually any logic design in a PLO.
Philips offers a variety of programmable logic devices which have been tailored to implement a wide range of applications.
In addition to a full complement of industry standard PAL-type devices, Philips offers several application specnic devices.
For ultra high speed applications, the Philips PLAs are the right solution. The logical power of two programmable arrays makes complex decoding easy. The PLUS153 and the PLUS173 offer 32 input wide AND-OR decoding, with a worst case TPD of 1Ons.
Designers using high performance DRAM, VRAM and graphics devices will appreciate the variety of complex state machines which include the PLC42VA12, PLC415, PLUS405 and the PLUS105. Check out the new 70 MHz PLUS105 in Section 5.
The PLC18V8Z can replace virtually all 20 PALs and GALs. The zero standby power of 20 micro amps is the lowest of any available PLO.
For maximum density in truly compact systems, the Programmable Macro Logic family is the right choice. These field programmable gate arrays are ideal for bus interface applications which require very wide gates.
The newest addition to the Philips PLO line is a family of low voltage devices (2.7 to 3.6 volts). Refer to Section 6 for details on the zero standby power P3C18V8Z Universal PAL device and the 3 very high speed BiCMOS devices.
Designing and programming of Philips PLDs is easy; many third party software and programmer vendors support the entire line of Philips devices. Section 1O details information on the approved software and programmer vendors, as well as all the latest software and firmware revisions.
For ideas on how to implement your designs, take a look at all the application notes in Section 11 of this manual.
Philips provides a high level of customer service via our 24-hour computer bulletin board and our staff of applications engineers who are ready to answer all your design and software related questions. The toll free bulletin board number (from the USA only) is (800) 451-6644. It may also be reached at (408) 991-2406.

Programmable Logic Devices

Section 1
General Information

CONTENTS Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . · · . . . · . . . . . . . . . . . . . . . . . . . . . . . . . 7 Alphanumeric index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · · . . . . . · . . . . . . . . · . . . . . . . . 1O Product Slaws Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · · . 11 Selection guide .............................·............................. 12 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . 14

Programmable Logic Devices

Contents

Section 1 - General Information Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Alphanumeric index......................................................................................... 10 Product Status Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Section 2 - Introduction Introduction

Programmable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Section 3 - PAL °19vlces

PHD16N8-5 !

Programmable high-speed decoder logic (16 x 16 x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

PLC18V8Z35/PLC18V8ZI

Zero standby power CMOS versatile PAL devices . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . 45

PLC18V8Z25/PLC18V8ZIA Zero standby power CMOS versatile PAL devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

PLUS16R80/-7Series

PAL devices 16L8, 16R8, 16R6, 16R4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

PLUS20R80/-7 Series

PAL devices 20L8, 20R8, 20R6, 20R4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

PL22V10-10

CMOS programmable electrically erasable logic device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

PL22V10-12/-15, PL22V10115 CMOS programmable electrically erasable logic device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

ABT22V10-7

BiCMOS versatile PAL device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

10H20EV8/10020EV8

ECL programmable array logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

PHD48N22-7

Programmable high-speed decoder logic (48 x 73 x 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Section 4 - Programmable Logic Arrays Devices

PLS153/A

Programmable logic arrays (18 x 42 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

PLUS153B/D

Programmable logic arrays (18 x 42 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

PLUS153--10

Programmable logic array (18 x 42 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

PLS173

Programmable logic array (22 x 42 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

PLUS173B/D

Programmable logic arrays (22 x 42 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

PLUS173--10

Programmable logic array (22 x 42 x 10) ........................................ , . . . . . 219

PLS100/PLS101

Programmable logic arrays (16 x48 x 8).......................... . . . . . . . . . . . . . . . . . . . . . 227

Section 5 - Programmable Logic Sequencers .Devices

PLS155

Programmable logic sequencer (16 x 45 x 12).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

PLS157

Programmable logic sequencer (16 x 45 x 12)................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

PLS159A

Programmable logic sequencer (16 x 45 x 12)....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

PLS167/A

Programmable logic sequencers (14 x 48 x 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

PLS168/A

Programmable logic sequencers (12 x 48 x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

PLS179

Programmable logic sequencer (20 x 45 x 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

PLC42VA12

CMOS programmable multi-function PLO (42 x 105 x 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

PLC415-16

CMOS programmable logic sequencer (17 x 68 x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

PLS105/A

Programmable logic sequencers (16 x 48 x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

PLUS105-45

Programmable logic sequencer (16 x48 x 8)................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

PLUS105-55

Programmable logic sequencer (16 x48 x 8)....................... . . . . . . . . . . . . . . . . . . . . . . 373

PLUS105-70

Programmable logic sequencer (16 x 48 x 8)...................... . . . . . . . . . . . . . . . . . . . . . . . 386

PLUS405-37/-45

Programmable logic sequencers (16 x 64 x 8) . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

PLUS405-55

Programmable logic sequencer (16 x 64 x 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

October 1993

7

Philips Semiconductors Programmable Logic Devices
Contents

Section 6 - Low Yoh Devices

P3C18V8z35/P3C 18V8ZI 3 Volt zero standby power universal PAL devices . . . . . . · . . . · . . . . . · . . . . · . . · . . . . . . . . . . . . . . . . 433

LVT16V8-7

3 Volt BiCMOS Versatile GAL-type PLO · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . · . . . · . . . . . . 447

LVT22V10-7

3 Volt BiCMOS Versatile PAL . . . . . . · . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . 449

LVT20V8-7

3 Volt BiCMOS Versatile GAL-type PLO . . . . . . . . . . . . · . . · · . . · · . . . · . . . . . . . . · . . . . · · · . . . · . · . 451

Section 7 - Programmable Macro Logic Devices

i·

PLHS501/PLHS501 I

Programmable macro logic . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . · . · . . . . · . . · . · . · . . . . . . . . . . . . 455

PML2552

CMOS high density programmable macro logic . . . · . . . . . . . . . . · . . . . . · . . . . . . · . · . . . . . . . . . . . . . 467

PML2852

CMOS high density programmable macro logic . . . . . . . . . . . . . . . . . . . . . . · . . · . . . . . . . . . . . . . . . . . 486

Section 8 - Miiitary selectlon guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

Section 9- Development Software

SNAP 1.9

Synthesis Nedist Analysis Program

513

Section 10 - Programmer/Software Support Philips Semiconductors PLO programming guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 PAL Devices . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 PLA Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 PLS Devices . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . · · · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 PML Devices . . . . . . . . . . · . . . . . . . . . . · . . . . . . . . . · . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . 522 PLO programmer reference guide - Data 1/0 Corporation . . . . · . . · . . · . . . . . . · . . . . . . . . . . . . . . . · . · . . . · · . . . . . . . . . . . . . . . . . 524 PLO programmer reference guide - Stag Micro Systems, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . 527 PLO programmer vendors contact guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 Approved software support . . . . . . · . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · · . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 Third-party software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 ABEL ·................................................................................................ 530 CUPL ....................................................·..............·............................. 532 PLDesigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 PLO software vendors contact guide ........................... .":................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

Section 11 -Appllcation Notes

PAL Devices

Introduction . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

AN043

10H/10020EV8 high-speed (4.4ns) ECL PLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . 542

AN031

PH048N22 high speed (7.Sns) 32-bit programmable decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

AN044

68030 system decoding . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

AN045

High speed 8-bit parallel to serial converter . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

AN219

A Metastability Primer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568

PLADevlces

Introduction . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . · . . . . . . 571

AN046

Quick PLA . . . . . . . . . . . . · . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . 575

AN014

Latches and flip-flops with PLS153 . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580

AN024

PLS173 as a 10-bit comparator, 74LS460 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

AN021

9-Bitparity generator/checker with PLS153/153A . . . . · . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . , . 584

Sequencer Devices

Introduction . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . 590

AN023

PLS168/168A Primer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

AN047

Alarm Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

AN028

High-speed 12-bit tracking AID converter using PLS179 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622

AN048

Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

AN034

PLUS405-55 - the ideal high speed interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · 637

AN032

Minimize metastability in 50MHz state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

ANOSO

Implementing Counters in Sequencer Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · 660

October 1993

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Philips Semiconductors Programmable Logic Devices
Contents

CMOS Sequencers

Introduction ......... .

666

AN0301

CMOS power in PLDs ................... .

673

AN0302

Microcontroller power management .......... .

676

AN0303

Motor controller .. .

680

AN0304

OMA controller .. .

685

AN036

12c bus expander

688

AN037

ISDN peripheral control .......... .

710

PMLDevices

Introduction: Designing with programmable macro logic ....................... .

724

AN029

Programmable macro logic primer ............................................ .

737

AN049

PLHS501 design examples .............. .

750

8-Bit Barrel Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . ........... .

756

12-Bit Comparator with Dual 1-of-8 Decoders

761

8-Bit Carry Look-Ahead Adder ....

764

32- to 5-Bit Priority Encoder

767

4-Bit Synchronous Counter

770

VME Bus EPROM Interface

772

Micro Channel Interface

779

NuBus Interlace ...

784

Data Bus Parity ..... .

791

16-Bit Comparator

795

AN038

12c 110 ports ....................... .

797

AN039

12c bus monitor ......................................... .

813

AN040

Switching control unit for data communication via RS232 ....... .

819

AN035

Microcontroller acceleration

831

AN042

Implementing counters in PML2X52 devices ...

845

AN041

Serial data encoder and decoder

853

Section 12 - Package Outline Drawings

0400E

20-Pin (350 mils wide) Plastic Leaded Chip Carrier (A) Package

877

0401 F

28-Pin (300 mils wide) Plastic Leaded Chip Carrier (A) Package

878

0397E

52-Pin Plastic Leaded Chip Carrier (A) Package

879

0398E

68-Pin Plastic Leaded Chip Carrier (A) Package ..

880

0399F

84-Pin Plastic Leaded Chip Carrier (A) Package ........ .

881

0584B

20-Pin (300 mils wide) Ceramic Dual In-line (F) Package (with window (FA) Package)

882

0586B

24-Pin (300 mils wide) Ceramic Dual In-line (F) Package (with Window (FA) Package)

883

0589B

28-Pin (600 mils wide) Ceramic Dual In-line (F) Package (with Window (FA) Package)

884

1473A

68-Pin CerOuad J-Bend (K) Package

885

1551

84-Pin CerQuad J-Bend (K) package .................. .

886

0408B

20-Pin (300 mils wide) Plastic Dual In-Line (N) Package ... .

887

0410D

24-Pin (300 mils wide) Plastic Dual In-Line (N) Package

888

0413B

28-Pin (600 mils wide) Plastic Dual In-Line (N) Package ... .

889

08640 01720

28-Pin (300 mils wide) Plastic Dual In-Line (N) Package ... .

890

20-Pin (300 mils wide) Plastic SOL {Small Outline Large) Dual In-Line (D) Package

891

01730

24-Pin (300 mils wide) Plastic SOL (Small Outline Large) Dual In-Line (D) Package

892

Section 13 - North American Sales Offices, Representatives and Distributors

895

Appendix A - Data Handbook System

896

October 1993

9

Philips Semiconductors Programmable Logic Devices
Alphanumeric index

ABT22V10-7

Series 24

LVT16V8·8

Series 20

LVT20V8-8

Series 24

LVT22V10·7

Series 24

PHD16NB-5

Series 20

PHD48N22·7

Series 68

PLC18VSZ25/TA

Series 20

PLC1 SVSZ35/I

Series 20

PLC42VA12

Series 24

PLC415·16

Series 28

PLHS501

PLS100/101

Series 28

PLS105/A

Series 28

PLS153/A

Series 20

PLS155

Series 20

PLS157

Series 20

PLS159A

Series 20

PLS1671A

Series 24

PLS1681A

Series 24

PLS173

Series 24

PLS179

Series 24

PLUS16RSDI· 7

Series 20

PLUS20RSDl-7

Series 24

PLUS105·45

Series 28

PLUS105·55

Series 28

PLUS105-70

Series 28

PLUS153B/D

Series 20

PLUS153-10

Series 20

PLUS1738/0

Series 24

PLUS173·10

Series 24

PLUS405·371-45

Series 28

PLUS405·55

Series 28

PL22V10-101-121·15

PL22V10115

Series 24

PML2552-351-50

PML2852-351-50

P3C18V8Z35

Series 20

10H20EV8110020EV8 Series 24

BiCMOS Versatile PLO Device; 7.Sns ................................................. . 133

3 Volt BiCMOS Versatile GAL-type PLO ............................................ . 447

3 Volt BiCMOS Versatile GAL-type PLO ............................................... . 451

3 Volt BiCMOS Versatile PAL ....................................................... . 449

Programmable High-Speed Decoder (16 x 16 x 8); 5ns ................................... . 37

Programmable High-Speed Decoder (48 x 73 x 22); 7.Sns ................................. . 165

Zero Standby Power CMOS Versatile PAL Devices; 25, 40ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Zero Standby Power CMOS Versatile PAL Devices; 35, 40ns . . . . . . . . . . . . . . . . . . . . . . . . . . . .

45

CMOS Programmable Multi-function PLO (42 x 105 x 12); 25MHz ........................... 309

CMOS Programmable Logic Sequencer (17 x 68 x8); 16MHz ............................... 329

Programmable Macro Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

Programmable Logic Arrays (16 x 48 x 8); SOns .......................................... 227

Programmable Logic Sequencers (16 x 48 x 8); 14, 20MHz ................................. 348

Programmable Logic Arrays (18 x 42 x 10); 40130ns ...................................... 179

Programmable Logic Sequencer (16 x 45 x 12); 14MHz ........... .

237

Programmable Logic Sequencer (16 x 45 x 12); 14MHz ........... .

249

Programmable Logic Sequencer (16x45x12); 18MHz ........ .

261

Programmable Logic Sequencers (14 x 48 x 6); 14, 20MHz .... .

273

Programmable Logic Sequencers (12 x 48 x 8); 14, 20MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Programmable Logic Array (22 x 42 x 10); 30ns . . . . . . . . . . . . . .

.. . .. ... .. ...

203

Programmable Logic Sequencer (20 x 45 x 12); 18MHz . .

297

PAL Devices (16L8, 16R4, 16R6 and 16R8); 7.Sns & 10ns . . . . . . . . . . . . . . . . . . . . .

71

PAL Devices (20L8, 20R4, 20R6 and 20R8); 7.Sns & 1Ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Programmable Logic Sequencer (16 x 48 x 8); 45MHz ..................................... 360

Programmable Logic Sequencer (16 x 48 x 8); 55MHz ..................................... 373

Programmable Logic Sequencer (16 x 48 x 8); 70MHz ..................................... 386

Programmable Logic Arrays (18 x 42 x 10); 15112ns ............ .

187

Programmable Logic Array (18 x 42 x 10); 10ns .......................................... 195

Programmable Logic Arrays (22 x 42 x 10); 15112ns ...................................... 211

Programmable Logic Array (22 x 42 x 10); 10ns

219

Programmable Logic Sequencers (16 x 64 x 8); 37, 45MHz ................................ . 399

Programmable Logic Sequencer (16 x 64 x 8); SSMHz ................ .

415

CMOS Programmable Electrically Erasable Logic Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

CMOS High Density Programmable Macro Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

CMOS High Density Programmable Macro Logic ........................................ . 486

3 Volt zero standby power universal PAL Devices

433

EGL Programmable Array Logic; 4.Sns ..... .

148

April 1992

10

Programmable Logic Devices

Product Status

DEFINITIONS

Data Sheet Identification

Product Status

Definition

Objective Spec/6caUon Formative or in Deatgn

This dalasheet contains thedesign targel or goal specHlcallons for product development. Specifications may change In any manner without notice.

Ptellmln"'Y SpeclllcaUon Preproduction Product

This data sheet contains preliminary data, and s~lementary data will be published al a later dale. Signetics RISOMlll the right to make changes at any time wtthout notice In order to In-prove design and supply the best possble product.

Product Specification

Full Production

This dala sheet contains Final Specifications. Slgnetics reserves
the right to make changes at My time without nal:ioe, in order to
irrprove design and supply the best pooslble product.

11

Philips Semiconductors Programmable Logic Devices
Selection guide

INTERNAL

PHILIPS

ARCHITECTURE

TOTAL PRODUCT

STATE

SElllCONIUCTORS (Inputs x Terms·

INPUTS TERMS PER REGISTERS

OUTPUTS

PART NUMBER

xOutputs) PACKAGE (#Dedicated) OR GATE (#Dedicated) C, llO, R, R l/O IPD(Max) llW[

lcc(Mu)

PAL DEVICES

1OH20EVB-4/

I~

10020EV~

20x90x8

24-Pin

20(12)

Bio 12

0

8varied

4.5ns 208MHz -250mA

PHD16N8-5

16x16xS

20-Pin

16(10)

h

0

2C,6 l/O

5ns

PHD4SN22-7

48x73x22 68-Pin 48(36)

7to 12

0

10 c, 121/0 7.5ns

180mA 420mA

PLUS16L8-7

16 x64 xS

20-Pin

16(10)

7

0

2C,61/0

7.5ns

1SOmA

PLUS16R4-7

16x64xS

20-Pin

16(8)

7toS

4(0)

4V0,4R

7.5ns 74MHz 180mA

PLUS16R6-7

16x64xS

20-Pin

16(S)

7to8

6(0)

2 V0,6 R

7.5ns 74MHz 180mA

PLUS16R8-7

16x64x8

20-Pin

16(8)

8

8(0)

8R

74MHz 1SOmA

PLUS16L80

16x64x8

20-Pin

16(10)

7

0

2C,61/0

10ns

180mA

PLUS16R4D

16x64x8

20-Pin

16 (8)

7to8

4(0)

4 V0,4 R

10ns 60MHz 180mA

PLUS16R6D

16x64x8

20-Pin

16(8)

7to8

6(0)

2 V0,6R

10ns 60MHz 180mA

PLUS16RBD

16x64x8

20-Pin

16(8)

8

8(0)

8R

60MHz 1SOmA

PLUS20L8-7

20x64x8

24-Pin

20 (14)

7

0

2C,61Kl

7.Sns

210mA

PLUS20R4-7

20x64x8

24-Pin

20 (12)

7to8

4(0)

4 V0,4 R

7.Sns 74MHz 210mA

PLUS20R6-7

20x64x8

24-Pin

20 (12)

7to8

6(0)

2 V0,6 R

7.5ns 74MHz 210mA

PLUS20R8-7

20x64x8

24-Pin

20 (12)

8

8(0)

8R

74MHz 210mA

PLUS20L8D

20x64xB

24-Pin

20 (14)

7

0

2C,600

10ns

210mA

PLUS20R4D

20x64x8

24-Pin

20(12)

7to8

4(0)

4 V0,4R

10ns 60MHz 210mA

PLUS20R6D

20x64x8

24-Pin

20 (12)

7to8

6(0)

2 V0,6R

10ns 60MHz 210mA

PLUS20RBD

20x64x8

24-Pin

20 (12)

8

8(0)

8R

60MHz 210mA

ABT22V10-7

22x130x10 24-Pin 22 (12)

Sta 16

10(0)

10varied

7.5ns 87MHz 210mA

PL22V10-15/115 22x130x10 24-Pin 22 (12)

Bto 16

10(0)

10varied

90mA, 15ns 53MHz O.SmAIMHz

PL22V10-12

22x130x10 24-Pin 22 (12)

Bto16

10(0)

10varied

90mA, 12ns 67MHz O.SmAIMHz

PL22V10-10

22x 130x 10 24-Pin 22 (12)

Sta 16

10 (0)

10varied

110mA, 10ns 77MHz O.SmAIMHz

PLC18V8Z35

PLC18V8ZI

18x74x8

20-Pin

18(8)

8

100µA,

8(0)

8varied

35,40ns 21MHz 1.SmAIMHz

PLC18VBZ25

PLC18VBZAI

18x74x8

20-Pin

18(8)

8

100µA,

8(0)

8varied

25ns 30MHz 1.SmAIMHz

P3C18V8Z25 #

P3C18V8ZAI#

18x74x8

20-Pin

18(8)

8

35ns 25MHz 60µA,

8(0)

8varied

· 40ns 20MHz 0.8mA/MHz

P3C 16V8-7 + #

18x64x8

20-Pin

18 (10)

7

8(0)

8varied

7.5ns 100MHz 150inA

P3C20VB-7 + #

22x64x8

24-Pin

22 (14)

7

8(0)

&varied

7.5ns 100MHz 150mA

LVT22V10-7 + # 22x130x10 28-Pin 22 (12)

Bio 16

10(0)

10varied

7.5ns 100MHz 150mA

PLA

PLS100/101

16x48x8

28-Pin

16(16)

Up to 48

0

PLS153

18x42x10 20-Pin

18(8)

Up to 32

0

PLS153A

18x42x10 20-Pin

18(8)

Up to 32

0

PLUS153B

18x42x10 20-Pin

18(8)

Up to 32

0

PLUS153D

18x42x10 20-Pin

18(8)

Up to 32

0

PLUS153-10

18x42x10 20-Pin

18(8)

Up to 32

0

PLS173

22x42x10

24-Pin

22(12)

Up to 32

0

PLUS173B

22x42x10

24-Pin

22 (12)

Up to 32

0

PLUS173D

22x42x10

24-Pin

22 (12)

Up to 32

0

PLUS173-10

22x42x10

24-Pin

22 (12)

Up to 32

0

SC
101/0 101/0 101/0 101/0 101/0 101/0 10 l/O 10 l/O 10 l/O

sons 40ns 30ns 15ns 12ns 10ns 30ns 15ns 12ns 10ns

170mA 155mA 155mA 200mA 200mA 200mA 170mA 200mA 200mA 210mA

December 1993

12

Philips Semiconductors Programmable Logic Devices
Selection guide

PHILIPS SEMICONDUCTORS PART NUMBER
PLS
PLS105 PLS105A PLUS105-45 PLUS105--55 PLUS405-37 PLUS405-45 PLUS405--55 PLS155 PLS157 PLS159A PLS167 PLS167A PLS168 PLS168A PLS179 PLC42VA12/I

ARCHITECTURE (Inputs x Ttnna'
xOutputs)

PACKAGE TOTAL

PRODUCT

INPUTS TERMS PER

(# Otdlcattd) OR GATE

INTERNAL
STATE
REGISTERS (# Dedicated)

22x48x8 22x48x8 22x48x8 22x48x8 24x64x8 24x64x8 24x64x8 16x45x12 16x45x12 16x45x12 22x48x6 22x48x6 22x48x8 22x48x8 20x45x12 42x105x12

28-Pin 28-Pin 28-Pin 28-Pin 28-Pin 28-Pin 28-Pin 20-Pin 20-Pin 20-Pin 24-Pin 24-Pin 24-Pin 24-Pin 24-Pin 24-Pin

22(16) 22(16) 22(16) 22(16) 24(16) 24(16) 24(16) 16(4) 16(4) 16(4) 22(14) 22(14) 22(12) 22(12) 20(8) 42(10)

Upto48 Up to 48 Up to 48 Up to 48 Up to64 Up to64 Up to64 Up to32 Up to32 Up to 32 Up to48 Up to 48 Up to 48 Up to 48 Up to 32 Up to 64

6(6) 6(6) 6(6) 6(6) 8(8) 8(8) 8(8) 4(0) 6(0) 8(0) 8(6) 8(6) 10(6) 10 (6) 8(0) 10(0)

PLC415-16

25x68x8

28-Pin

25(17)

Up to 64

8(8)

PML PLHS501 PML2552--35

104x116x24 205x210x24

52-Pin 68-Pin

32(24) 53(29)

Up to 136· Up to 258·

0 36(20)

PML2552--50

205x210x24 68-Pin

53(29) Up to 258. 36(20)

PML2852--35

205x210x40 84-Pin

53(29) Up to 258. 36(20)

PML2852--50

205 x210 x40 84-Pin

53(29) Upto258· 36(20)

PAL Device = Programmable Array Logic (Fixed OR Array)-Type
PHO= Programmable High-Speed Decoder PLA = Programmable Logic Array PLS =Programmable Logic Sequencer PML =Programmable Macro Logic
OUTPUTS: C = Combinatorial output

R = Registered output 1/0 = Combinatorial 1/0
R 1/0 = Registered 110
NOTES:
IMAX = 1/(t1s + lcKol worst case
· Includes control product terms

OUTPUTS lpo(Max) IMAX
C, llO, R, R llO

lcc(Max)

8R 8R 8R 8R 8R 8R 8R 800,4R1/0 600,6R1/0 400,8Rl/O 6R 6R 8R 8R
41/0, 8 R VO
1000orRl/O, 21/0 SR

sons sons 35ns
35ns 35ns

14MHz 20MHz 45MHz 55MHz 37MHz 45MHz 55MHz 14MHz 14MHz 18MHz 14MHz 20MHz 14MHz 20MHz 18MHz 25MHz

180mA 180mA 200mA 200mA 225mA 225mA 225mA 190mA 190mA 190mA 180mA 180mA 180mA 180mA 210mA 135mA

16MHz

100µAI 80mA

16C, 81/0 81/0, 16 R l/O
81/0, 16Rl/O
16C,8 VO, 16 R l/O
16C, 81/0, 16 R l/O

22ns 35ns sons 35ns sons

50MHz 35MHz 50MHz 35MHz

295mA
10mAI 100mA
10mAI 100mA
10mAI 100mA
10mAI 100mA

· Product terms per NANO gate PAL is a registered trademark of AMO.
PML is a trademark of Philips Semiconductors.
+ Under development .# 3 Volt devices

All packages refer to DIP configurations except PHD48N22, PML2552 and PML2852, which are offered in PLCC only.

December 1993

13

,Philips Semiconductors Programmable Logic Products
Ordering Information

PLO PRODUCTS

Example:

Package Code

,

A= 20-, 28-, 52-, 68-, 84-lead Plastic Leaded Chip Carrier (PLCC)

D = 20-, 24-Pin Plastic SO (300-mil)

F = 20-, 24-, 28-Pin Ceramic Dual In-Line

I·

N = 20-, 24-, 28-Pin Plastic Dual In-Line

FA= 20-, 24-Pin Ceramic Dual In-Line with Quartz Window

KA = CerOuad (window)

Performance indicator Z = Zero standby power devices blank, A, B, D, -35, -7, etc. =propagation delay (ns) -37, -45, -55, etc. =operating frequency (MHz)

Basic Part Number (3 to 8 characters) (e.g,, 100, 105, 153, 168, 173, 18P8, 42VA12)

Process/Architecture Indicator

S

Bipolar Junction Isolated Schottky - Nichrome fuses

C

CMOS - EPROM cells

HS High Speed Bipolar Oxide Isolated - Vertical Fuse

US High Speed Bipolar Oxide Isolated - Lateral Fuse

HD High Speed Decoder

ML Macro Logic

(Blank for ECL devices)

lndicatorfor Philips Programmable Logic (Can be either P, PL, P3, or blank) (P for PHO and PML and blank for ECL devices)

o Operating temperature range= to +70°C
EXCEPT: PLC18V8ZI = -40 to +85°C
PL22V10115= -40to+85°C

GAL is a registered trademark of Lattice Corp, PAL is a registered trademark of MMI, Corp., a wholly--0wned subsidiary of Advanced Micro Devices (AMO), Inc.

December 1993

14

Programmable Logic Devices

Section 2
Introduction

Introduction Programmable logic ................. · · · ... · · · · · · · · · · 17

i
j'·

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

WHAT IS PROGRAMMABLE
LOGIC?
In 1975, Philips Semiconductors developed a new product family by combining its expertise in semi-custom gate array products and fuse-link Programmable Read Only Memories (PROMs). Out of this marriage came Philips Semiconductors Programmable Logic Family. The PLS100 Field-Programmable Logic Array (FPLA) was the first member of this family. The FPLA was an important industry first in two ways. First, the AND/OR/INVERT

architecture allowed the custom implementations of Sum of Product logic equations. Second, the three-level fusing allows complete flexibility in the use of this device family. All logic interconnections from input to output are programmable.
Figure 1 shows the architecture of a high performance sequencer combining a PLA architecture with JK ftip-ffops. The Selection Guide shown on pages 12 and 13 of this data handbook shows the current spectrum of

Philips Semiconductors PLDs. Parts fi>r every need are available in nearly every architecture and across at least three technologies. The PLUS and PLHS prefixes describe bipolar parts, the PLC and P3C prefix describes EPLD (CMOS) parts and the PLO and P3Q prefix refers to the new Philips Semiconductors QUBiC BiCMOS process. Figure 2 shows a shorthand image of the PLUS153 programmable logic array (PLA), which was derived from the original PLS100.

PR

K

Op

STATE REGISTER

48ANDGATES

NOTES: I, P, C, N, F and PIE are user-programmable connections.

Figure 1. High Speed Sequencer

OUTPUTS

November 1993

17

Philips Semiconductors Programmable Logic Devices
Programmable logic

p 1

Po

Introduction
D9

Figure 2. PLUS153 20-Pin Functional Diagram

November 1993

18

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

PLO LOGIC SYNTHESIS
No intermediate step is required to implement Boolean Logic Equations with PLDs. Each term in each equation simply becomes a direct entry into the Logic Program Table. The following example illustrates this straightforward concept:
Xo = AB + "CD + BU
X1 = Jl:B +"CD+ EFG

T

AND

E~ !---------I-NPU-T~-mJ----------~

P-Terms

r.s~ "i4113r.'211tr"1QT"9'8 ·7 5r-5 4r-3 21 rQi

Po :AB

H H

P1 ="CD

L H-

P2:BU

H- L -

Pa ::A"B

L H

P4:EFG ,__4~~~~~~~~~~~~~~~---+---~H~~H~H~

· · ·

44

45

X0 :P0 +P1 +P2 ,_~4~6-1--t~+--+--t--t~+--1---+--t~+--+--+--+~+--+--1
X1 = Pa+ P1 + P4 P~~

NO. 20212223242526'Z7 2 3 4 5 6 7 8

A BCDEFG

~I:ci:t:'r:EI!!:
117--&--r0-s0---:-tTla':~r2r1-.-r-oAA A . A . A . A
10 11 12 13 15 16 17 18
X1 Xo

Figure 3. Field Programmable Logic Array

A

B

Xo

c

D

E F G

Figure 4. Equivalent Fixed Logic Diagram

X1 X1 :llB+CD+EFG

November 1993

19

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

In the previous example, the two Boolean Logic equations were broken into Product terms. Each P-term was then programmed into the P-term section of the PLA Program Table. This was accomplished in the following manner:

Step 1 Select which Input pins lo -115 wlll
correspond to the Input variables. In this
case A - G are the input variable names. 16 through 10 were selected to accept inputs A - G respectively.

T

AND

E R
M

r---------------------~ INPUT(lm)

'to t-;-5·14' 13 r-12 'tt

9 8 7 6 r-5 ......3,.2'11 T"'Q1

0

1

2

3

4
· · ·

44

45

46

47

PIN NO.

20 21 22 23 24 25 26 27 2 3 4 5 6 7 8 9

w_.w

ABc DEF G

m::;;

:a!:<zC ~

::1:cIIIJ::1I~
1------<OU>T.P!U!T.~.-.-----1
1-1-, & 5 4 3 2 1 rjj1
10 11 12 13 15 18 17 18

Step 2
Transfer the Boolean Terms to the PLA Program Table. This is done simply by defining each term and entering it on the Program Table.
e.g., Po=AB

Figures.
This P-term translates to the Program Table by selecting A = 16 = H and B = 15 = H and entering the information in the appropriate column.

This term is defined by selecting C = 14 = L and D = 13 = H, and entering the data into the Program Table. Continue this operation until all P-terms are entered into the Program Table.

T
E ~

1------------AND -----------1 INPUT(lm)

f-;5 ·ui1a..-12' 1i'"io '8'8.,..7 6 r-;i 4'3 21 ·ii1

H Ji L H-
H- L

H -

- - HH H
· · ·
44

45

46

47

PIN NO.

2021222324252627 2 3

w .m...:l:w;;

ABC DEF G

:a!:<zC

~

~I:CIIIJ:!Ii!:
1------2!!._____
l-1- e;-5;0!l~J;r2'11 'ii
10 11 12 13 15 16 17 18

Figure&.

November 1993

20

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

Step 3
Select which output pins correspond to each output function. In this case F0 = Pin 18 = X0, and F1 =Pin 17 = X,.

T
R E

1-----------AND ------------

M

H H -

H

H- L

H

- - HH H
· · ·
44

45

46

47

PIN NO.

20 21 22 23 24 25 26 27 2 3

A BCDEF G

:=r:ct:J:1r:::i:r~
t------_9.!!. ____ --1 1-, -r-_..\!.U_ri;l!!.~- - r-1
76543210
10 11 12 13 15 16 17 18
X1 Xo

Figure 7.

Step 4
Select the Output Active Level desired for each Output Function. For Xo the active level is high for a positive logic expression of

this equation. Therefore, it is only necessary to place an (H) in the Active Level box above Output Function 0, (Fo). Conversely, X1 can

be expressed as X1 by placing an (L) in the Active Level box above Output Function 1,
(F1).

T

AND

E ~

~----------------------
INPUT(lm)

'15'""141a'""12''1'10T"9'8 "7'6'5 4r3i 2 1 "i)

H H H
H- L

H - - HH H
· · ·
44 45 46

47

PIN NO.

2021222324252627 2 3

A BCDEF G

~r:ct:J:1r:::i:br~

1-------9.!!.____ -I

!-_-,

OUTPUT l'p_

.--I

7654 32 10

10 11 12 13 15 16 17 18
X1 Xo

Figure 8.

November 1993

21

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

Step 5
Select the P·Terms you wish to make active for each Output Function. In this
case Xo =Po+ P1 + P2, so an A has been
placed in the intersection box for Po and Xo.
P1 and Xo and P2 and X0.

Terms which are not active for a given output are made inactive by placing a(·) in the box under that P-term. Leave all unused P-terms unprogrammed.
Continue this operation until all outputs have been defined in the Program Table.

Step6
Enter the data into a Philips Semiconductors approved programmer. The input format is identical to the Philips Semiconductors Program Table. You specify the P-terms, Output Active Level, and which P-terms are active for each output exactly the way It appears on the Program Table.

Xo = Po+ P1 + P2
= X1 Ps + P1 + P4

T

AND

R E
M

~---------~-----------INPUT~m)
l-;?"ii 1sr12 1i,.....1.o... -1...,..a·..,..,-1.,-& ,...; 7r-3i 2'1' r-ii'

H H L H-
H- L -
L H-
- - HH H
· · ·
44
45
46
47
PIN NO.

ABCDEF G

::r:cr:Cr:JJ;r~

1--
1-7.,

--
6

-

..
5

.o!u:>P.U!~!\.

.

-

-

-
1

-T-'"1~

. A
A A

. A
. A

. A

10 11 12 13 15 16 17 18
X1 Xo

Figure9.

November 1993

22

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

PLO LOGIC SYNTHESIS (Continued)
When fewer inputs and outputs are required in a logic design and low cost is most important, the Philips Semiconductors 20-pin PLO should be considered first choice. The

PLUS153 is a PL.A with 8 inputs, 10 1/0 pins, and 42 product terms. The user can configure the device by defining the direction of the 1/0 pins. This is easily accomplished by using the direction control terms Do - 09 to establish

the direction of pins Bo - B9. The D-lerms control the 3-State buffers found on the outputs of the Ex-OR gales. Figures 10 and 11 show how the D-lerm configures each Bx pin.

p 1

p

Sci --+--____J'----+--l

" > - - - - - - - + - L o Bo
3-STATE BUFFER

Figure 10. PLUS153 Functional Diagram

lo

a. De Active Makes B9 Appear as an Output with Feedback

Figure 11.

INPUT Ilg
3.STATE -::- BUFFER INACTIVE
(OPEN>
b. D9 Inactive Makes B9 Appear as an Input

November 1993

23

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

To control each D-term, it is necessary to
understand that each control gate is a
36-input AND gate. To make the 3-State
buffer active (Bx pin an output), the output of
the control gate must be at logic HIGH (1). This can be accomplished in one of two

ways. A HIGH can be forced on all control gate input nodes, or fuses can be programmed. When a fuse is programmed, that control gate input node is internally pulled up to HIGH (1). See Figure 12 and Figure 13.

Programming the fuse permanendy places a HIGH (1) on the input to the control gate. The input pin no longer has any effect on that state.

L

CONTROL GATE
TO AND ARRAY

TO AND ARRAY

. . A~:;.y.0---1 ~--.--STA~T-E--0 Bx:OUTPUT
BUFFER

3-STATE BUFFER

Figure 12. Input Effect on Control Gates (Fuse Intact)

Bx:INPUT

I= HIGH (1) o - - - + - H - - - -.H..
CONTROL GATE TO AND ARRAY
>-3-S-<t>-AT-E--o Bx= OUTPUT BUFFER
Figure 13. Effect on Control Gate if Fuse is Programmed

November 1993

24

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

DEDICATING Bx PIN DIRECTION
Since each input to the D-terms is true and complement buffered (see Figure 11), when the device is shipped with all fuses intact, all control gates have half of the 36 input lines at logic low (0). The result of this is all Control Gate outputs are low (0) and the 3-State buffers are inactive. This results in all Bx pins being in the input condition. the resultant device is, therefore, an 18-input, 0-output FPLA. While useful as a bit bucket or

Write-Only-Memory (WOM), most applications require at least one output. Clearly, the first task is to determine which of the Bx pins are to be outputs. The next step is to condition the control gate to make the 3-State buffer for those gates active. To
dedicate Bo and B1 as outputs, it is necessary
to program all fuses to the inputs to Control Gates Do and D1. This internally pulls all inputs to those gates to HIGH (1)
permanently. since all inputs to the Control

Gates are HIGH (1), the output is HIGH (1)
and the 3-State buffers for Bo and B1 are
active. This permanently enables Bo and B1
as outputs. Note that even though Bo and B1
are outputs, the output data is available to the AND array via the internal feedback (see Figure 11a).
To program this data, the PLUS153 Program Table is used as shown in Figure 14.

AND

B(t)

7 6543 210 987 6543 210

I

I

POLARITY
1
OR B(O) 6543210
I

i

· · ·

... o :i: _, I

!jl.

::!

30 31

T

I

J.

J.

'1 t i~

~ ~

: ;-2 -~ 1 -~ o0

t--;:0080:--<r0o:-t0~o-+0-:o:0-t-~0o+-:0co-+0-:o:0-t-~0o+-o0-+-:;o-+0--o+0-o-+0-:o-0+--o:+-0o+-o0-+-o-+-0-l--0o_P]
01 o o o o o o o o o o j--1o o o o·i, o o o o · - - - - '

i-~~~~~~~~~~D~·=f~o4~o~to~~~o}1~0+~04=o~t-o~r~-o~++-~011=oj~o~t~ot~o~1~01~oj=o~to~:~---~

05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0·-----~

04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D · - - - - - - -
a - - - - - - - - - 03 0 o o o o o o o o olo o o Olo o o
02 0 0 0 ':.! 0 0 0 0 0 O_i 0 0 0 O 0 0 0 0 - - - - - - - - - - - '
_ _ _ _ _ _ _ _ _ ___, ~oo0;1;::---t----t--t--_--r_-+-_-t--_-t--_-+-_-t--_-+--_-+_--f-_--+--_-+_--J--_-+--_-1--_-f:-~!· ...- ._ ----------~

PIN 8 7 6 5 4 3 2 1 19 18 17 16 15 14 13 12 11 9

19 18 17 16 15 14 13 12 11 9

Figure 14. Dedicating Bo and 8 1 as Outputs and 8 2 Through 8 9 as Inputs

November 1993

25

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

By placing a(-) Don't Care in each input

inactive and the B2 - Elg pins are enabled as

Control Gate to respond to one or more input

box you are specifying that the True and

inputs. All Bx pin directions can be controlled pins. It is only necessary to select which Ix

Complement fuses are programmed on each in this manner.

and Bx pins will control the pin directions and

Control Gate, thus permanently dedicating

the active level HIGH (H) or LOW (L) that will

the Bo and B1 pins as outputs. By placing a

be used. The PLUS153 Program Table in

(0) in all input boxes for ~ - Elg, you are specifying that both True and Complement

ACTIVE DIRECTION CONTROL
Sometimes it is necessary to be able to

Figure 15 shows the method of controlling
Bo- Elg with 17. When 17 is LOW (L), pins

I,

fuses are intact. This causes a low (0) to be forced on half of the Control Gate inputs,

actively change the direction of the Bx pins without permanently dedicating them. Some

B0 - B9 are outputs; when 17 is HIGH (H),
pins Bo - B9 are inputs. Note that by

guaranteeing the output of the Control Gate

applications which require this include 3-State programming all other Ix and Bx pins as

will be low (0). When the Control Gate

bus enable, multi-function decoding, etc. This DON'T CARE(-). they are permanently

outputs are low (0), the 3-State buffer is

can easily be done by programming the

disconnected from control of Bx pin direction.

POLARITY

T

AND

E R

B(I)

M 7 6 54 3 2 10 98 7 6 54 3 21 0

"T

"T

"T

OR B(O) 98 7 6 5 4 3 2 1 0

"T

"T

j_

j_

j_

j_

-'- - - - -'- -' - - - -

l

l

l

l

'

· · ·

w

0:

~

~

~-ct m Im ~

...: \...: 0

30

31

!

09

:i:

DB

-1-

07

I

I

PJ

06

-1-

05

D4

-'-

03

_:r_

-1- - -1-

02 01 L DO L -

-_r --_i-

PIN 8 7 6 5 4 3 2 1 19 18 17 16 15 14 13 12 11 9

19 18 17 16 15 14 13 12 11 9

w
a-c~a':w:<:z;: ~

Figure 15. Active Control of 8 0 - 8 1 Using 17 Active Low (L)

November 1993

26

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

The previous 28-pin logic synthesis example could be done on the PLUS153 as follows:
Xo=AB+C"D+BU
X1 = Jl:B + C"D +EFG
Note that Bo was used as a CHANGE input. When Bo is HIGH (H) the outputs appear on
B8 and B9. When Bo is LOW (L), the outputs
appear on Ba and B7. B1 through B5 are not used and therefore left unprogrammed.

Philips Semiconductors offers two packages for user-friendly design assistance. The first package, AMAZE, has evolved over 10 years to support Philips Semiconductors programmable products with logic equation, state equation, and schematic entry. AMAZE can compile designs quite well for Philips Semiconductors lower density parts. However, to satisfy the needs of

Programmable Macro Logic users, Philips Semiconductors developed an additional software package called SNAP. SNAP expands upon the capabilities of AMAZE in its approach to design implementation, more closely resembling a gate array methodology. Both of these products are described in more depth at a later point in this handbook.

POLARITY

L H L H

I

~

I

I

::J

g :~, t

Oa·:~:~i= :·!~Z:·ffifil..

·~<.>1015;:

g ~ ~ I

: f 1 0 0 0 0

: '---'---J

T

AND

~

B(I)

M 7 6543 210 987 6543 210

~ HH_

-!- - - -!- -
_I_ - - _I_ -

2 -H-L---

3 L H-

- :- - - - - I - 1 - - - - ..__4_,_-_.._-_._-_..._-_.._H-'-H-'--'-H_.._-_._-_...-_._-_._-_..._-_.._-......_-_...-_._-_._-_,

OR B(O) 987654 3 2 1 0
· A!· A
A A A A· A· A·

'

...'
!j!,' '

o ::z: ...1 I
I~:~~~

· · ·

30

!

31

I

j_

J t-::c::--t--=+-=-t-=-+=-.:..i=--t--=+-=-t-=-t-=-+=-+-=+-=-t-=-t-=-+=-+=-+-=-t-=-11:µ

t-"'~~~~~-;-=06,...+:_=+=_+=_+_=,~-::+=-+-::+=-=i-=-+-::.i-:1-=i-::.:-::.i..=-+-~l~-+=-+-::+=-:.r~~--' 05 o o o o o o o o o o o o o o o o o o-------~

04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O·------~
03 o o o oo o o ooo o o oo!o o 00---------~ 02 o o o oTo o o o o o.J.o o o o.J..o o o o ·--------~ 01 0 0 0 O_LO o o o o oJ_o o o o o o o o · - - - - - - - - - - - '
DO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0-------------~

PIN 8 7 6 5 4 3 2 1 19 18 17 16 15 14 13 12 11 9

19 18 17 16 15 14 13 12 11 9

ABCDEFG

X1 Xo X1 Xo

c cc
H HH A AA N NN G GG E EE

Figure 16. PLUS153 Example

November 1993

27

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

SEQUENTIAL LOGIC CONSIDERATIONS
The PLUS405, PLUS105 and PLC42VA12 represent significant increases in complexity

sequential operations in relatively high-speed processor systems. By placing repetitive sequential operations on the PLUS405, processor overhead is reduced.

The logic output of the machine is also programmable, and is stored in the Output Register. The PLUS105 is a subset of the PLUS405.

when compared to the combinatorial logic

The following pages summarize the

Clocked Sequence

devices previously discussed. By combining

PLUS405 architecture and features.

A synchronous logic sequence can be

,,1

the AND/OR combinatorial logic with clock output flip-flops and appropriate feedback,

Sequencer Architecture

represented as a group of circles interconnected with arrows. The circles

Philips Semiconductors has created the first The PLUS405 Logic Sequencer is a

represent stable states, labeled with an

family of totally flexible sequential logic machines.

programmable state machine, in which the output is a function of the present state and

arbitrary numerical code (binary, hex, etc.) corresponding to discrete states of a suitable

the present input.

The PLUS405 (Programmable Logic

register. The arrows represent state

Sequencer) is an example of a high-order

With the PLUS405, a user can program any

transitions, labeled with symbols denoting the

machine whose applications are many.

logic sequence expressed as a series of

jump condition and the required change in

Application areas for this device include

jumps between stable states, triggered by a

output. The number of states in the sequence

VRAM, DRAM, Bus and LAN control. The

valid input condition (I) at clock time (t). All

depends on the length and complexity of the

PLUS405 is fully capable of performing fast

stable states are stored in the State Register. desired algorithm.

CLOCK-----+-------~

STATE REGISTER

PR
N COMBIN.
LOGIC

OUTPUT REGISTER

0 :INPUT ® = PRESENT STATE ® =NEXT STATE ® = NEXT OUTPUT

PR

Figure 17. Basic Architecture of PLS105 FPLS. I, P, N, and Fare Multi-line Paths Denoting Groups of Binary Variables Programmed by the User.

11-3 are jump conditions which must be satisfied before any transitions take place. F, are changes in output triggered by Im. and stored in the output register. State transitions a -> b and c -> d involve no output change.
Figure 18. Typical State Diagram.

The arrow connecting the two states gives rise to a transition term Tn· I is the jump condition.
Figure 19. Typical State Transition Between Any Two States of Figure 18.

November 1993

28

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

State Jumps
The state from which a jump originates is referred to as the Present state (P), and the state to which a jump terminates is defined as the Next state (N). A state jump always causes a change in state, but may or may not cause a change in machine output (F).
State jumps can occur only via '1ransition terms" T0· These are logical AND functions of the clock (t), the Present state (P), and a valid input (I). Since the clock is actually applied to the State Register, Tn; l·P. When Tn is "true", a control signal is generated and used at clock time (1) to force the contents of the State Register from (P) to (N), and to change the contents of the Output Register (if necessary). The simple state jump in Figure 20, involving 2 inputs, 1 state bit, and 1 output bit, illustrates the equivalence of discrete and programmable logic implementations.
Sequencer Logic Structure
The Sequencer consists of programmable AND and OR gate arrays which control the Set and Reset inputs of a State Register, as well as monitor its output via an internal feedback path. The arrays also control an independent Output Register, added to store output commands generated during state transitions, and to hold the output constant during state sequences involving no output changes. If desired, any number of bits of the Output Register can be used to extend the width of the State Register, via external feedback.

A A B
B

T:ABO
Figure 20. Typical State Jump From State (0) to State (1), If Inputs A= B = "1"'. The Jump Also Forces F = "1"', as Required.

I I - - - LOGIC TERMS T - - 9

OPTIONS

Po~-+--+-~~~~~~~~--+~:0-~~1-'--,
c~-+--+-~~~~~~~~--+-<,,,_,

November 1993

47 46

0

Figure 21. Simplified Logic Diagram of PLUS105

29

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

Figure 22. Typical AND Gate Coupled to (I) and (P) Inputs. If at Least One Link Pair Remains Intact, Tn is Unconditionally Forced Low.

JJ,.

1--D-

D-

Figure 23. Choice of Input Polarity Coupling to a Typical AND Gate. With Both Links Open, (I) is Logically Don't Care.

Figure 24. Typical Transition Terms Involving Arbitrary Inputs and State Variables. All Remaining Gate Inputs Are Programmed Don't Care. Note That T2 Output is State Independent.

Input Buffers
16 external inputs (Im) and 6 internal inputs (P 5 ), fed back from the State Register, are combined in the AND array through two sets of True/Complement (T/C) buffers. There are a total of 22 TIC buffers, all connected to multi-input AND gates via fusible links which are initially intact.
Selective fusing of these links allows coupling either True, Complement, or Don't Care values of (Im) and (P5).
"AND" Array
State jumps and output changes are triggered at clock time by valid transition terms Tn. These are logical AND functions of the present state (P) and the present input (I).
The PLUS105 AND Array contains a total of 48 AND gates. Each gate has 45 inputs 44 connected to 22 TIC input buffers, and 1 dedicated to the Complement Array. The outputs of all AND gates are propagated through the OR Array, and used at clock time (t) to force the contents of the State Register from (P) to (N). they are also used to control the Output Register, so that the FPLS 8-bit output F, is a function of the inputs and the present state. The PLUS405 contains 64 AND gates in its' AND array.

November 1993

30

Philips Semiconductors Programmable Logic Devices
Programmable logic

Introduction

"OR" Array
In general, a clocked sequence will consist of several stable states and transitions, as determined by the complexity of the desired algorithm. All state and output changes in the state diagram imply changes in the contents of State and Output Registers.
Thus, each flip-flop in both registers may need to be conditionally set or reset several times with Tn commands. This is accomplished by selectively ORing through a programmable OR Array all AND gate outputs Tn necessary to activate the proper flip-flop control inputs.
The PLUS105 OR Array consists of 14 pairs of OR gates, controlling the S/R inputs of 14 State and Output Register stages, and a single NOR gate for the Complement Array. All gates have 48 inputs for connecting to all 48 AND gates. The PLUS405 uses 64 input gates.
The PLUS405 contains 16 pairs of OR gates controlling state transitions and output stages and two additional NOR gates for dual complement arrays.

F3
CK
CK
Figure 25. Typical OR Array Gating of Transition Terms T ,,2,3 Controlling Arbitrary State and Output Register Stages.

COMPLEMENT ARRAY LOGIC
PATH

,-

1

I

I

I

I

I

I

OR ARRAY

Figure 26. The COMPLEMENT Array is Logically Constructed from a Multiple Input Programmable NOR Gate. All AND Terms Coupled to the OR Gate are Complemented at the Inverter Output, and Can be Fed Back
as Inputs to the AND Array.

November 1993

31

Philips Semiconductors Programmable Logic Devices
Pmgrammable logic

~
A TRANSITION TERMS

PgX PoY
L ______ J COMPLEMENT ARRAY
T3 = Po(PgX + f'oY) T3 = Po[Po(X + Y)] T3=Poff'o+(X+Y)) T3 =0 + Po(lr+Yj T3:Poilt.'i')

a. Typical State Sequence

b. Complement Jump

Figure27.
a. X and Y Specify the Conditional Logic for Direct Jump Transition Terms T1 and T2. The Complement Jump Term T3 ls True Only When Both T1 and T2 are False.
b. Note that the Complementary Logic Expression for T3, 'T;""'+Tii, Corresponds
Exactly to the Logic Structure of the Complement Array.

Complement Array
The Complement Array provides an asynchronous feedback path from the OR Array back to the AND Array.
This structure enables the sequencer to perform both direct and complement sequential state jumps with a minimum of transition (AND) terms.
Typically direct jumps. such as T1 and T2 in Figure 27 require only a single AND gate each.
But a complement jump such as T3 generally requires many AND gates if implemented as a direct jump. However. by using the Complement Array, the logic requirements for this type of jump can be handled with just one more gate from the AND Array. Because it can be split into separate machines (2 clocks). the PLUS405 incorporates two Complement Arrays.

As indicated in Figure 28, the single Complement Array gate may be used for many states of the state diagram. This happens because all transition terms linked to the OR gate include the present state as a part of their conditional logic. In any particular state. only those transition terms which are a function of that state are enabled; all other terms coupled to different states are disabled and do not influence the output of the Complement Array. As a general rule of thumb, the Complement Array can be used as many times as there are states.

Introduction

November 1993

32

Philips Semiconductors Programmable Logic Devices
Programmable logic
, START
a. State Diagram

Introduction
Td1 =lol1 Po
Td2='2Po Te3= (Td1 + Td2) Po= (lo l1 +l2) Po
Tc14=l2 P3 Td6=lol1 Po Tes= (Tc14 + Tc1&) P3=(lo1, +12) P3 Ten= COMPLEMENT STATE TRANSITION TERM Tdn = DIRECT STATE TRANSITION TERM P8 =PRESENT STATE
b. Logic Definition
1, o----~=~t==t::=t:=l~t:

l
COMPLEMENT ARRAY
t-+---+----cr----+--+--+---t--+-J

l
COMPLEMENT ARRAY
J 1 - - - + - - + - - t - - - + - - + - - - + -

8 TRANSITION TERMS USED
c. State Logic without Using the Complement Array

ld1 ld2 Tc3 ld4 Tds Tes 6 TRANSITION TERMS USED
d. State Logic Using the Complement Array

Figure 28. Logic Reduction with the Complement Array. The Logic State Diagram in (a) Includes Complement Jumps Tc3 and Tcs Defined in (b). When Using the Complement Array, a Savings of 2 Transition Terms Results, as Shown in (c) and (d).

Additional features are available depending on a specific part. In particular, the PLC42VA 12 has everything mentioned here, and more. More details on PLAs, PAL devices and Sequencers can be found in the application section later in the manual.
Programmable Macro Logic, Philips Semiconductors very high density logic is fully described in detail in its own section.

November 1993

33

Programmable Logic Devices

Section 3
PAL Devices

PHD16N8-5 PLC18V8z35/PLC18V8ZI PLC18V8Z25/PLC18V8ZIA PLUS16R8D/-7 Series PLUS20R8D/-7 Series PL22V10-10 PL22V10-12/-15, PL22V10115 ABT22V10-7 10H20EV8/10020EV8 PHD48N22-7

CONTENTS Programmable high-speed decoder logic (16 x 16 x 8) .. 37 Zero standby power CMOS versatile PAL devices . . . . . 45 Zero standby power CMOS versatile PAL devices . . . . . 58 PAL devices 16L8, 16R8, 16R6, 16R4 ............... 71 PAL devices 20L8, 20R8, 20R6, 20R4 . . . . . . . . . . . . . . . 87 CMOS programmable electrically erasable logic device . 103 CMOS programmable electrically erasable logic device . 118 BiCMOS versatile PAL device . . . . . . . . . . . . . . . . . . . . . 133 ECL programmable array logic . . . . . . . . . . . . . . . . . . . . 148 Programmable high-speed decoder logic (48 x 73 x 22) 165

Phillps Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (16x16 x 8)

Product specification
PHD16N8-5

DESCRIPTION
The PHD16NB-5 is an ultra fast Programmable High-speed Decoder featuring a 5ns maximum propagation delay. The architecture has been optimized using Philips Semiconductors state-of-the-art bipolar oxide isolation process coupled with titanium-tungsten fuses to achieve superior speed in any design.
The l'HD1 SNB-5 is a single level logic element comprised of 10 fixed inputs, BAND gates, and B outputs of which 6 are bidirectional. This gives the device the ability to have as many as 16 inputs. Individual 3-State control of all outputs is also provided.
The device is field-programmable, enabling the user to quickly generate custom patterns using standard programming equipment. Proprietary designs can be protected by programming the security fuse.
The SLICE software package from Philips Semiconductors supports easy design entry for the PHD16NB-5 as well as other PLD devices.
Order codes are listed below.

FEATURES
· Ideal for high speed system decoding · Super high speed at 5ns lpD · 10 dedicated inputs · B outputs
- 6 bidirectional 1/0 - 2 dedicated outputs · Security fuse to prevent duplication of proprietary designs. · Individual 3-State control of all outputs · Field-programmable on industry standard programmers · Available in 20-pin Plastic Dual In-Line and 20-Pin PLCC
APPLICATIONS
· High speed memory decoders · High speed code detectors · Random logic · Peripheral selectors · Machine state decoders
· Footprint compatible to 16LB
· Fuse/Footprint compatible to TIBPAD

PIN CONFIGURATIONS
N Package Vee 07
B6 85 84 B3 82 81 00 GND N ... Plastic Dual In-Line Package (300mil-wide)
A Package
B6 85 84 83
a2
18 GND 19 00 81 A - Plastic Leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Dual In Line Package; (300 mil-wide) 20-Pin Plastic Leaded Chip Carrier; (350 mil square)

ORDER CODE PHD16N8-5N PHD16N8-5A

DRAWING NUMBER 01730 0400E

October 22, 1993

37

85~141711164

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (16x16x8)
LOGIC DIAGRAM
Jllo.4--·l.12·-i-20

Product specification
PHD16N8-5
I'

--·1~~~-----IJ~'--1-l;>o-------.---j18 v
---mJ~J 1 '---lv)lK>--<p---i

.....,_y-++~·····II+-t-IIill-+-i~~!-+'~+--l~l-+-l~~-=~~~~-u~'---lv)~--113
---1 ~ ---IJ~'---lv·~12 ~ 11
NOTES: 1·.~I.I. \.mprogrammed or virgin MAND" gate locations are pulled to logic "O" 2.::::::::::: Programmable connections

October 22, 1993

38

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (16 x 16 x 8)
FUNCTIONAL DIAGRAM
Ill 19

Product specification
PHD16N8-5

81-86 00,07

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL

PARAMETER

Min

Max

UNIT

Vee

Supply voltage

--0.5

+7

Voc

V1N

Input voltage

--0.5

+5.5

Voc

Vmn

Output voltage

+5.5

Voc

l1N

Input currents

-30

+30

mA

lour

Output currents

Tarro

Operating temperature range

+100

mA

0

+75

oc

Tstg

Storage temperature range

-65

+150

"C

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS

TEMPERATURE

Maximum junction

150°C

Maximum ambient

75°C

Allowable thermal rise ambient to junction

75°C

OPERATING RANGES

SYMBOL Vee Tamb

PARAMETER Supply voltage Operating free-air temperature

RATINGS

Min

Max

+4.75 +5.25

0

+75

UNIT Voc "C

October 22, 1993

39

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic
(16 x 16 x 8)

Product specification
PHD16N8-5

DC ELECTRICAL CHARACTERISTICS 0°C s Tamb :S +75°C, 4.75 s Vee :S 5.25V

SYMBOL Input vollage2

PARAMETER

TEST CONDITIONS

LIMITS

MIN

TYP1

MAX

V1L

Low

V1H

High

Vic

Clamp

Output voltage

VOL

Low

VoH

High

Input current

Vee= MIN Vee= MAX Vee= MIN, 11N = -18mA
v,l Vee= MIN, V1N = v,H or
loL =+24mA loH =-3.2mA

0.8

2.0

-0.8

-1.5

0.5 2.4

f1L

Low

,f1, H

High High

Output current

Yee= MAX V1N = +0.40V V1N = +2.7V V1N =Vee= Vee MAX

-20

-250

25

100

lozH

Output leakage3

lozL

Output leakage3

los

Short circuit4

Ice

Vee supply current

Capacitance5

Vee= MAX Your= +2.7V Your= +0.40V
Vour = ov
Yee= MAX

100 -100

-30

-90

115

180

C1N

Input

Vee= +5V

V1N = 2.0V@f = 1MHz

8

Gour

l/0(8)

Vour = 2.0V@ f = 1MHz

8

NOTES:
1. Typical limits are at Vee= 5.0Vand Tamb = +25°C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3. Leakage current for bidirectional pins is the worst case of 11L and fozL or l1H and loZH4. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. 5. These parameters are not 100% tested, but are periodically sampled.

UNIT
v
v
v
v v
µA µA µA
µA µA mA mA
pF pF

October 22, 1993

40

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (16x16 x 8)

Product specification
PHD16N8-5

AC ELECTRICAL CHARACTERISTICS
o·c :s; Tami> :s; +75°C, 4.75 :s; Vee :s; 5.25V, R1 = 200'1, R:! = 390'1

TEST

LIMITS

SYMBOL

PARAMETER

FROM

TO

CONDITIONS

MIN

MAX

UNIT

tpo1

Propagation delay

(I, B)±

Output±

CL =50pF

5

ns

loE2

Output Enable

(I, B)±

Output enable

CL =50pF

10

ns

loo2

Output Disable

(I, B)±

Input disable

CL=5pf

10

ns

NOTES:
1. !po is tested with switch S1 closed and CL = 50pF. 2. For 3-State output; output enable times are tested with CL= 50pF to the 1.5V level, and S1is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL. 5pF. High-to-High impedance tests are made to an output
voltage of VT= (VoH - 0.5V) with S1open, and Low-to-High impedance tests are made to the VT = (Vol+ 0.5V) level with S1closed.

VIRGIN STATE A factory shipped virgin device contains all fusible links open, such that: 1. All outputs are disabled.
2. All p-terms are disabled in the AND array.

TIMING DEFINITIONS

SYMBOL

PARAMETER

tpo

Input to output propagation delay.

Input to Output Disable

loo

(3-State) delay (Output

Disable).

Input to Output Enable

loE

delay (Output Enable).

l! 8

J

s I 5

~

Izll 4

0

I~ 3 2

0

3 4

TEST CONDITIONS: Tamb · 75"C:
Vee· 4.75V; ct.. 50pF;
R1 · 2000; R2 · 390'1

7 8

Worst-Case Propagation Delay vs. Number of Outputs Switching

TIMING DIAGRAM

WAVEFORM

INPUTS
MUST BE STEADY

OUTPUTS
WILLBE STEADY

WAVEFORM
~

INPUTS
DON'T CARE; ANY CHANGE PERMITTED

OUTPUTS
CHANGING; STATE UNKNOWN

}1)--{K DOES NOT APPLY

CENTER UNEISHIGH IMPEDANCE "OFF' STATE

October 22, 1993

41

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (16x16x8)

Product specification
PHD16N8-5

AC TEST LOAD CIRCUIT

VOLTAGE WAVEFORMS

C1YC2 INPUTS
NOTE:
C1 and C2 are to bypass Vee to GND.

ByVee t::__> R1

ID

BBwx Bz 19 OUT

CL

GND

OUTPUTS ':"

':"

2.Sna

2.Sns

MEASUREMENTS: All circuit delays are measured at the+ 1.5V level of inputs and outputs, unless otherwise specified.

Input Pulses

LOGIC PROGRAMMING
The PHD16N8-5 is fully supported by industry standard {JEDEC compatible) PLO CAD tools, including Philips Semiconductors' SNAP design software package. ABEL'" CUPLTM and PALASM® 90 design software packages also support the PHD16N8-5 architecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.

PHD16N8-5 logic designs can also be generated using the program table entry format, which is detailed on the following page. This program table entry format is supported by SNAP only.
To implement the desired logic functions, each logic variable {I, B, P and D) from the logic equations is assigned a symbol. TRUE {High), COMPLEMENT {Low), DON'T CARE and INACTIVE symbols are defined below.

PROGRAMMING/SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/ Software Support) of this data handbook for additional information.

"AND" ARRAY - (I, B)
l,B l,B i l,B

il,B I, B l,B

il,B 1,8 l,B

il,B l,B l,B

,D
STATE INACTIVE1
NOTE: 1. This is the initial state.

,D
STATE TRUE

,D
L l STATE I [ COMPLEMENT

,D
STATE DON'T CARE

ABEL is a trademark of Data 110 Corp. CUPL is a trademark of Logical Devices, Inc. PALASM is a registered trademark of AMO Corp.

October 22, 1993

42

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (16x16 x 8)

Product specification
PHD16N8-5

PROGRAM TABLE
_, 5l '
>< '
!£'
O a: ,'
--' -------------' o ::c ~ I
Co
~·
'"' "' 1..:
~
>><<
Li:
(.)

w
:::;;
z < :aw::;:;
ef2n
::l

aw"":
a0 : 0 w
~ ~
a:
::l

w""
(.)
> w
0
en
:0::.:.;
:c

.mw".."..
j!
:::;;
<a:
Cl 0a:

(.) 0.. 0..

0..

AND

T

E

INPUT(I)

INPUTS(B)

R M

413 2 1 0 6 5

2 1

l

l

]

]

]

l

]

l

l

I

l

l

!

!

l

10

I

11

12

13

]

14

15
! PIN 11 9le 1 6 5 4 3 2 1 w u wl~ u ~

I

I

~.amw~...:. <:zw::;;

I I I I I

I I
I I I

l l

OR(RXED) OUTPUTS (B, 0)
19 1a 11 1& !ts 14 13 12
I I I I I I I
J

NOTES: 1. The PHD16N8-5 is shipped with all links intact. 2. Unused I and B bits in the AND array exist as INACTIVE in the virgin state. 3. All p-terms are inactive until programmed otherwise. 4. Data cannot be entered into the OR array field due to the fixed nature of the device architecture.

October 22, 1993

43

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (16x16 x 8)
DECODING 1/2 MEG STATIC MEMORY

AH31

AL1& AH31

AL1& AH31

· · · ·

AL1& AH31

AL1&

SNAP RESOURCE SUMMARY DESIGNATIONS

Product specification
PHD16N8-5

October 22, 1993

81-86 00,07
44

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z35/PLC18V8ZI

DESCRIPTION
The PLC1BVBZ35 and PLC18V8ZI are universal PAL®1 devices featuring high performance and virtually zero-standby power for Opower sensitive applications. They are reliable, user-configurable substitutes for discrete TTUCMOS logic. While compatible with TTL and HGT logic, the PLC18V8ZI can also replace HC logic over the Vee range of 4.5 to 5.5V.
The PLC 18V8Z is a two-level logic element comprised of 10 inputs, 74 AND gates (product terms) and 8 output Macro cells.
Each output features an "Output Macro Cell" which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. As a result, the PLC 18V8Z is capable of emulating all common 20-pin PAL devices to reduce documentation, inventory, and manufacturing costs.
A power-up reset function and a Register Preload function have been incorporated in the PLC18V8Z architecture to facilitate state machine design and testing.
With a standby current of less than 1OOµA and active power consumption of 1.5mA/MHz, the PLC 18V8Z is ideally suited for power sensitive applications in battery operated/backed portable instruments and computers.
The PLC18V8Z is also processed to industrial requirements for operation over an extended temperature range of -40°C to +85°C and supply voltage of 4.5V to 5.5V.
Ordering information can be found below.

FEATURES
· 20-pin Universal Programmable Array Logic
· Virtually Zero-Standby-power - 20µA (typical)
·Available in 300mil-wide DIP with quartz window, plastic DIP (OTP), PLCC (OTP), and SOL (OTP)
· Functional replacement for Series 20 PAL devices - loL = 24mA
· High-performance CMOS EPROM cell technology - Erasable - Reconfigurable - 100% testable
· 35ns Max propagation delay (comm)
· 40ns Max propagation delay (Industrial) ·Up to 18 inputs and 8 inpuVoutput macro
cells · Programmable output polarity
· Power-up reset on all registers
· Register Preload capability
· Synchronous PreseVAsynchronous Reset
· Security fuse to prevent duplication of proprietary designs
· Design support provided using SLICE software development package and other CAD tools for PLDs
APPLICATIONS
· Battery powered instruments

PIN CONFIGURATIONS
D, N, and FA Packages Vee
F1 Fs Fs F4 F3 F2 F1 Fo GNO N = Plastic Dual Jn-Line Package (DIP) (300mil-wide) FA .. Ceramic DIP with Quartz Window (300mil-wide) D .. Plasitc Small Outline Large Package (300mll-wide)
A Package
I()'
12 11 eLKVee F1
la GNO lg! Fo F1 OE
A= Plastic Leaded Chi Carrier
PIN LABEL DESCRIPTIONS
I Dedicated input B Bidirectional inpuVoutput 0 Dedicated output D Registered output (D-type flip-flop)

ORDERING INFORMATION

· Laptop and pocket computers · Industrial control · Medical Instruments · Portable communications equipment

F CLK OE Vee GND

Macrocell lnpuVOutput Clock input Output Enable Supply voltage Ground

DESCRIPTION

OPERATING CONDITIONS

ORDER CODE

DRAWING NUMBER

20-Pin (300mil-wide) Plastic Dual In-Line Package {!po= 35ns)

Commercial

PLC18V8Z35N 0408B

20-Pin (300mil-wide) Ceramic Dual In-Line Package with quartz window {!po= 35ns) Temperature Range PLC18V8Z35FA 0584B

20-Pin {350mil square) Plastic Leaded Chip Carrier Package {!po= 35ns)

±5% Power

PLC18V8Z35A 0400E

20-Pin {300mil-wide) Plastic Small Outline Large Package {!po= 35ns)

Supplies

PLC18V8Z35D 0172D

20-Pin {300mil-wide) Plastic Dual In-Line Package {!po= 40ns)

Industrial

PLC18VBZIN

0408B

20-Pin {300mil-wide) Ceramic Dual In-Line Package with quartz window (!po= 40ns) Temperature Range PLC18V8ZIFA

0584B

20-Pin (350mil square) Plastic Leaded Chip Carrier Package (tpo = 40ns)

± 10%Power

PLC18V8ZIA

0400E

20-Pin (300mil-wide) Plastic Small Outline Large Package {tpo = 40ns)

Supplies

PLC18V8ZID

01720

1. PAL is a registered trademark of Monolithic Memories, Inc., a wholly owneQ subsidiary of Adv~nced Micro Devices, Inc.

October 22, 1993

45

853-1396 11164

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices
LOGIC DIAGRAM

Product specification
PLC18V8Z35/PLCt8V8ZI

NOTES: In the unprogrammed or virgin ·state:
All cells are in a conductive state. All AND gate locations are pulled to a logic "O'' (low). Output polarity is inverting.
October 22, 1993

Pins l and 11 are configured as Inputs o and 9, respectively, via the configuration cell. The clock and OE functions are disabled. All output macro cells (OMC) are configured as bidirectional 110, with the outputs disabted via the direction terrn
.·.·. Denotes a programmable cell location.
46

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z35/PLC18V8ZI

PAL DEVICE TO PLC18V8Z OUTPUT PIN CONFIGURATION CROSS REFERENCE

PIN NO.

PLC 18V8Z

16L8 16H8 16PB 16P8

16R4 16R6 16R8 16RP4 16RP6 16RP8

16L2 16H2 16P2

14L4 14H4 14P4

12L6 12H6 12P6

1

lo/CLK

I

CLK CLK CLK

I

I

I

19

F7

B

B

B

D

I

I

I

18

F6

B

B

D

D

I

I

0

17

F5

B

D

D

D

I

0

0

16

F4

B

D

D

D

0

0

0

15

F3

B

D

D

D

0

0

0

14

F2

B

D

D

D

I

0

0

13

F1

B

B

D

D

I

I

0

12

FO

B

B

B

D

I

I

I

11

li;IOE

I

OE OE OE

I

I

I

10L8 10H8 10P8
I 0 0 0 0 0 0 0 0 I

FUNCTIONAL DIAGRAM

The Philips Semiconductors' state-of-the-art Floating-Gate CMOS EPROM process yields bipolar equivalent performance at less than one-quarter the power consumption. The erasable nature of the EPROM process enables Philips Semiconductors to functionally test the devices prior to shipment
OUTPUT MACRO CELL (OMC)

to the customer. Additionally, this allows Philips Semiconductors to extensively stress test, as well as ensure the threshold voltage of each individual EPROM cell. 100% programming yield is subsequently guaranteed.

r---------
I 1 DIRECTION CONTROL TERM
I I I I
{ I
:R~~~ ::+::::::":/--~"'----..·-~

FROM AND

ARRAY · TO ALL OMCs

--+-------,

:

I

:

I

I I
I

I
I I I

I I II AC1n :.:· I AC2n...;:1<-1 :::ioo----~-~-+----1-
1

L - - - - - - - - - + -' t - 1''' '-
f H
TOALLOMCs NOTE: ~~;;: Denotes a programmable cell location.

THE OUTPUT MACRO CELL (OMC)
The PLC 18V8Z series devices have 8 individually programmable Output Macro Cells. The 72 AND inputs (or product terms) from the programmable AND array are connected to the 8 OMCs in groups of 9. Eight of the AND terms are dedicated to logic functions; the ninth is for asynchronous direction control. which enables/disables the respective bidirectional 1/0 pin. Two product terms are dedicated for the Synchronous Preset and Asynchronous Reset functions.
Each OMC can be independently programmed via 16 architecture control bits, AC 1n and AC2n (one pair per macro cell). Similarly, each OMC has a programmable output polarity control bit (Xn). By configuring the pair of architecture control bits according to the configuration cell table, 4 different configurations may be implemented. Note that the configuration cell is automatically programmed based on the OMC configuration.
DESIGN SECURITY
The PLC 18V8Z series devices have a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature. proprietary designs implemented in the device cannot be copied or retrieved.

October 22, 1993

47

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specificatiOn
PLC18V8Z35fPLC18V8ZI

CONFIGURATION CELL A single configuration cell controls lhe funclions of Pins 1 and 11. Referto Functional Diagram. When the configuration cell is programmed, Pin 1 is a dedicated clock and Pin 11 is dedicaled for output enable. When the configuration cell is unprogrammed, Pins 1 and 11 are both dedicated inputs. Note that the output enable

for all registered OMCs is common-from Pin 11 only. Output enable control of the bidirectional VO OMCs is provided from the AND array via the direction product term.
If any one OMC is configured as registered, the configuration cell will be automatically configured (via the design software) to ensure that the clock and output enable functions are

enabled on Pins 1 and 11, respectively. If none of the OMCs are registered, the configuration cell will be programmed such that Pins 1 and 11.are dedicated inputs. The programming codes are as follows:

Pin 1 = CLK; Pin 11 ='CE

L

Pin 1 and Pin 11 = Input

H

FUNCTION Registered mode

CONTROL CELL CONFIGURATIONS

AC11

AC2N

CONFIG. CELL

Programmed

Programmed

Programmed

Bidirectional 1/0 mode 1 Unprogrammed

Unprogrammed

Fixed input mode

Un programmed

Programmed

Fixed output mode

Programmed

Unprogrammed

NOTE: 1. This is the virgin state as shipped from the factory.

ARCHITECTURE CONTROL--AC1 and AC2

Un programmed Un programmed Un programmed

COMMENTS
Dedicated clock from Pin 1. 'CE Control
for all registerd OMCs from Pin 11 only.
Pins 1 and 11 are dedicated inputs. 3-State control from AND array only.
Pins 1 and 11 are dedicated inputs.
Pins 1 and 11 are dedicated inputs. The feedback path (via FMux) is disabled.

F(D). l' (D)

F(B).1'(11)

~ ;

F(O),l'(O)

OMC CONFIGURATION
BIDIRECTIONAL 1101 COMBINATORIAL

CODE B

OMC CONFIGURATION FIXED OUTPUT

CODE 0

~
F(O), l' (D) F(I)

~

OMC CONFIGURATION FIXED INPUT

CODE

CONFIGURATION CELL
PIN 1 ·CLK PIN 11 ·tlE

CODE

CONFIGURATION CELL
PIN 1 ·INPUT PIN 11 ·INPUT

CODE H6

NOTES:
A factory shipped unprogrammed device is configured such that: 1. This is the initial unprogrammed state. All cells are in a conductive state. 2. All _AND gates are pulled to a logic 'O" (Low). 3. Output polarity is inverting.
4. Pins 1 and 11 are configured as inputs Oand 9. The clock and OE functions are disabled.
5. All Output Macro Cells (OMCs) are qonfigured as bidirectional 110, with lhe outputs cisabled via the direction term. 6. This configuration cannot be used if any OMCs are configured as registered (Code = D). The configuration cell will be automatically
configured to ensure that the clock and output enable functions are enabled on Pins 1and 11, respectively, if any one OMC is programmed as registered.

October 22, 1993

48

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z35/PLC18V8ZI

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

PARAMETER

RATINGS

UNIT

Vee

Supply voltage

Vee

Operating supply voltage

-0.5 to +7

Vrx;

4.5 to 5.5 (Industrial) 4.75 to 5.25 (Commercial)

Vrx;

V1N Vour tJ.lltN

Input voltage Output voltage Input/clock transition rise or fall2

-0.5 to Vee+ 0.5 -0.5 to Vee+ 0.5
250

Vrx;
Vrx;
nsN
maximum

l1N

Input currents

-10to+10

mA

lour

Output currents

+24

mA

Tamt> Tstg

Operating temperature range Storage temperature range

-40 to +85 (Industrial)

oc

0 to +75 (Commercial)

--65to+150

oc

NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those
indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS
TEMPERATURE Maximum junction Maximum ambient
Allowable thermal rise
ambient to junction

150°C 75°C 75°C

2. All digital circuits can oscillate ortrigger prematurely when input rise and fall times are very long. When the input signal to a device is at or near the switching threshold, noise on the line will be amplified and can cause oscillation which, if the frequency is low enough, can cause subsequent stages to switch and give erroneous results. For this reason, Schmitt-triggers are
recommended if rise/fall times are likely to exceed 250ns at Vee= 4.5V.

AC TEST CONDITIONS
C1YC2 INPUTS
NOTE: C1 and C2 are to bypass Vee to GND.

Vee L.>

lo

By

lg OUT Bw

R1 CL

Bx

Bz

GND

':"

OUTPUTS ':"

VOLTAGE WAVEFORMS

+3.0V~---
L J90% 10%

OV __J5ns

IA IF

5nsl...-

+3.0V~

F

___LL_d!L
ov-=:i:-ns~ ~5ns

MEASUREMENTS: All circuit delays are measured at the +1.SV level of Inputs and outputs, unless otherwise specified.

Input Pulses

October 22, 1993

49

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z35/PLC18V8ZI

DC ELECTRICAL CHARACTERISTICS
Commercial= 0°C s Taroo s +75°C, 4.75V s Vee S5.25V;
Industrial= -40°C s Tamb s +85°C, 4.SV s Vee s 5.SV

SYMBOL

PARAMETER

Input voltage

V1L

Low

V1H

High

Output voltage'

VoL

Low

VoH

High

Input current

l1L

Low7

l1H

High

Output current

/o(OFF)

Hi-Z state

las

Short-circuit3

Ice

Vee supply current (Standby)

lcc/f

Vee supply current (Active)4

Capacitance

c,

Input

Cs

110

TEST CONDITION
Vcc=MIN Vee= MAX
Vee= MIN, loL = 20µA Vee= MIN, loL = 24mA Vee= MIN, loH = -3.2mA Vee= MIN, loH =-20µA
V1N = GND V1N =Vee
VouT= Vee VouT = GND VouT=GND Vee= MAX, V1N = O or Vcc8 Vee= MAX (CMOS inputs)S,6
Vee= 5V V1N = 2.0V Vs= 2.0V

LIMITS

MIN

TVP1

MAX

UNIT

--0.3

0.8

v

2.0

Vee +0.3

v

2.4 Vcc-0.1V

0.100

v

0.500

v

v v

-10

µA

10

µA

10

µA

-10

µA

-130

mA

20

100

µA

1.5

mAIMHz

12

pF

15

pF

100µA

12

18

f(MHz)

24 30

Figure 1. Ice vs Frequency5· s (Worst Case)

4

~
l7

~

~ 2
<i 1

.J'1
V1

E

~ -1
-2 0 20 40 60 80 100 120 140 160 180 200

OUTPUT CAPACITANCE LOADING (pF)

Figure 2. t.lpo vs Output Capacitance Loading (Typical)

NOTES:
1. All typical values are at Vee= 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Duration of short-circuit should not exceed one second. Test one at a time.
4. Tested with TIL input levels: V1L = 0.45V, V1H = 2.4V. Measured with all outputs switching. 5. t.lccITTL input= 2mA. 6. t.lcc vs frequency (registered configuration) = 2mA/MHz. 7. l1L for Pin 1 (/ofCLK) is± 1OµA with V1N = 0.4V. 8. V1N includes CLK and OE if applicable.

October 22, 1993

50

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z35/PLC18V8ZI

AC ELECTRICAL CHARACTERISTICS4
Commercial= 0°C s Tamb s +75°C, 4.75V s Vee s 5.25V;
Industrial= -40°C s Tamb s +85°C, 4.5V s Vee s 5.5V; R2 = 390'1

TEST CONDITION'

PLC18V8Z35 (Commercial)

PLC18V8ZI (Industrial)

SYMBOL

PARAMETER

Pulse width

Clock period

lcKP

(Minimum

tis+ teKo)

lcKH

Clock width High

lcKL

Clock width Low

tARW

Async reset pulse width

FROM

TO

CLK+
CLK+ CLKI±, F±

CLK+
CLKCLK+ I+. F+

R1 (Q)
200 200 200

CL (pf)

MIN

MAX

MIN

MAX UNIT

50

47

57

ns

50

20

25

ns

50

20

25

ns

35

40

ns

Hold time

Input or feedback

t1H

data hold time

CLK +

Input±

200

50

0

0

ns

Setup time

Input or feedback

tis

data setup time

1±, F±

CLK+

200

50

25

30

ns

Propagation delay

Delay from input

lpo

to active output

1±, F±

F±

200

50

35

40

ns

Clock High to

lcKO

output valid

access nme

CLK +

F±

200

50

22

27

ns

loE1 3

Product term enable to outputs off

1±, F±

F±

Active-High R = 1.5k Active-Low R = 550

50

35

40

ns

Product term

loo1 2

disable to outputs off

1±,F±

F±

From VoH R = oo From VoL R = 200

5

35

40

ns

tool

Pin 11 output disable High to outputs off

OE-

F±

From VoH R = oo
From VoL R = 200

5

25

30

ns

loE23

Pin 11 output enable to active output

OE+

F±

Active-High R = 1.5k

Active-Low R = 550

50

25

30

ns

tARD

Async reset delay

Async reset recov-

fARR

ery time

1±, F± 1±, F±

F+ CLK+

35

40

ns

25

30

ns

Sync preset recov-

lsPR

ery time

I±, F±

CLK+

25

30

ns

lppR

Power-up reset

Frequency of operation

Vee+

F+

35

40

ns

IMAX

Maximum frequency

l/(tlS + lcKO)

200

50

21

18 MHz

NOTES: 1. Refer also to AC Test Conditions. (Test Load Circuit) 2. For 3-State output; output enable times are tested with CL= 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL. 5pF. High-to-High impedance tests are made to an output voltage of VT= (VoH -0.5V) with S1 open, and Low-to-High impedance tests are made to the VT= (VoL + 0.5V) level with S1 closed. 3. Resistor values of 1.5k and 550'1 provide 3-State levels of 1.0V and 2.0V, respectively. Output timing measurements are to 1.5V level. 4. Leave all the cells on unused product terms intact (unprogrammed) for all patterns.

October 22, 1993

51

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z35/PLC18V8ZI

POWER-UP RESET
In order to facilitate state machine design and testing, a power-up reset function has been incorporated in the PLC18VBZ. All internal registers will reset to Active-Low (logical "O") after a specified period of time (tPPR).

Therefore, any OMC that has been configured as a registered output will always produce an Active-High on the associated output pin because of the inverted output buffer. The internal feedback (Q) of a

registered OMC will also be set Low. The programmed polarity of OMC will not affect the Active-High output condition during a system power-up condition.

TIMING DIAGRAMS

I····

INPUTS 110, REG.· FEEDBACK

CLK

PIN 11 OE
REGISTERED OUTPUTS
ANYINPUT"7'7".,,,"'7'7".,..,"'7'7".,..,"'7'7".,..,"'7'7".,..,"'7'7".,..,"'7'7".,..,"'7'7".,..,"'7'7".,..,"'7"7"7"1.,r---,,,.----""\.
PROGRAMMED FOR
DIRECTION CONTROL -"-'~'-"''-"-'J...'-"''-"-'J...'-"''-"-'J...'-"''-"-'J...'-"''-"-'J...'-"''-"-'J..."-''-"-'J...U I' - - - - . . I
COMBINATORIAL OUTPUTS"-''-"-'J...'-"''-"-'J...""''-"-'.I ' - - - - - - - - - - - - - - - - - - - - - -
Switching Waveforms
+SV

Vee
F (OUTPUTS)
I, B (INPUTS)
CLK
NOTE: Diagram presupposes that the outputs (F) are enabled. The reset occurs regardless of the output condition (enabled or disabled).
Power-Up Reset

ov
VoH Vol +3V
ov
+3V
ov

October 22. 1993

52

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z35/PLC18V8ZI

TIMING DIAGRAMS (Continued)
ASYNCHRONOUS RESET INPUT

1+----1A~r----ot

...... ............ ..... ...... REGISTERED OUTPUT

~~

~~~:.....~~

~

~---'

CLOCK

Asynchronous Reset

SYNCHRONOUS PRESET INPUT

CLOCK

REGISTERED OUTPUT

Synchronous Preset

October 22, 1993

53

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z35/PLC18V8ZI

REGISTER PRELOAD FUNCTION (DIAGNOSTIC MODE ONLY)
In order to facilitate the testing of state machine/controller designs, a diagnostic mode register preload feature has been incorporated into the PLC18V8Z series device. This feature enables the user to load

the registers with predetermined states while a super voltage is applied to Pins 11 and 6 (lg/OE and 15). (See diagram for timing and sequence.)
To read the data out, Pins 11 and 6 must be returned to normal TTL levels. The outputs, F0 _ 7, must be enabled in order to read data

out. The Q outputs of the registers will reflect data in as input via F0 _ 7 during preload. Subsequently, the register Q output via the feedback path will reflect the data in as input via F0 _ 7.
Refer to the voltage waveform for timing and
voltage references. IPL = 1Oµsec.

REGISTER PRELOAD (DIAGNOSTIC MODE)

lg/OE
(PIN 11)

5.0V

12.0V

IPL IPL

Is (PIN6)

lo/CLK (PIN1)

- - -------- -- - --+-

-

-------- -

------+----

-----rI-----"'\
---..;.!______...,___,

,---------

lo/CLK

~

;,-~~~~~~1---....

F o - 1 - - - - - - - - C PRELOAD DATA IN

October 22, 1993

54

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z35/PLC18V8ZI

LOGIC PROGRAMMING The PLC1BVBZ series is fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips Semiconductors' SNAP design software package. ABELT· and CUPLTM 90 design software packages also support the PLC18VBZ architecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.

PLC18VBZ logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only.
With Logic programming, the AND/OR/EX-OR gate input connections necessary to implement the desired logic function are coded directly from logic equations using the Program Table. Similarly,

various OMC configurations are implemented by programming the Architecture Control bits AC 1 and AC2. Note that the configuration cell is automatically programmed based on the OMC configuration.
In this table, the logic state of variables I, P and B associated with each Sum Term S is assigned a symbol which results in the proper fusing pattern of corresponding link pairs, defined as follows:

OUTPUT POLARITY - (0, B)

O,IJ

s-x-=p-·[)--{>o- o.B

l[ I J ACTIVE LEVEL

CODE

1 l INVERTING1

L

"AND" ARRAY - (I, B)

f j ACTIVE LEVEL

CODE ]

r 1 l NON-INVERTING

H

l,B

l.B

I. B i l , B

1.B i l , B

1.IJ

· T,IJ

T,IJ

i

STATE DON'T CARE

p
STATE INACTIVE 1

p
STATE l,B

NOTE: 1. A factory shipped unprogrammed device is configured such that all cells are in a conductive state.

1.B i l , B 1,IJ
. STATE
1,IJ

ERASURE CHARACTERISTICS (For Quartz Window Packages Only) The erasure characteristics of the PLC18VBZ Series devices are such that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lighting could erase a typical PLC18V8Z in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. If the PLC1 BVSZ is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the window to prevent unintentional erasure.

The recommended erasure procedure for the PLC18VBZ is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15Wsec/cm2. The erasure time with this dosage is approximately 30 to 35 minutes using an ultraviolet lamp with a 12,000µW/cm2 power rating. The device should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose a CMOS EPLD can be exposed to without damage is 7258Wsec/cm2). Exposure of these CMOS EPLDs to high intensity UV light for longer periods may cause permanent damage.

The maximum number of guaranteed erase/write cycles is 50. Data retention exceeds 20 years.
PROGRAMMING/SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 1O(Third-Party Programmer! Software Support) of this data handbook for additional information.

ABEL is a trademark of Data 110 Corp. CUPL is a trademark of Logical Devices, Inc.

October 22, 1993

55

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices
PROGRAM TABLE

Product specification
PLC18V8Z35/PLC18V8ZI

CONAGURATION CELL_iCLKIOE CONTRO!,!_D
AR~~T<;,,~,~~1-tl-t-+-t--1----t--+-i

AND

OR_iAXEQl_ F(B,O, D)

October 22, 1993

cxxx
LL.
..()

Icc~

. . w cwc

w 0
!::::!
...J
0
CD

:::?
z ~ cwc
:::?
~ en

0cc
0 wen :~c
(cc)

w
()
> w
0
en
CL
;;;!

:e>::n-? cwc
:::?
e~n

=> => :c =>

() CL CL ()

AND ARRAY
INACTIVE 0 I, t], !!)_ H
I EJ1 fil_ L
''DON'T CARE -

OMC ARCH.
REGISTERED _@-TYfil
AXED INPUT AXED OUTPUT BIDIRECTIONAL 1/0

CONTROL OUTPUT POLARITY

D . [NON-INVERTING · [INVERTING

j H] j Lj

I

CONRG.CELL'

L 0 , PIN h CLK; PIN lh laj_ Lj

I B I ' PIN PIN 11 · INPUT H]

IL 1

OR ARRA'U_AXE!1)_
DATA CANNOT BE EN'TERED
~~ T~~H%~~~A~A~~~~

OF THE DEVICE ARCHITEC~TU_RE_ . _ _~~

[ DIRECTION CON'TROL[ D

L l ACTIVE OUTPUT

A

IZI [NOT USED

· THE CONAGURATION CELL IS AUTOMATICALLY PROGRAMMED BASED ON THE OMC ARCHITECTURE. ··FOR SP, AR: ,,_·· IS NOT ALLOWED.

56

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices
SNAP RESOURCE SUMMARY DESIGNATIONS

Product specification
PLC18V8Z35/PLC18V8ZI

r----------
1
I I I I I I I

FROM ANO

ARRAY · TO ALL OMCs

---' !-------....,

:

I

""-'<a:

I

I

I AC1n I

I AC2n

I I

=

NOTE:

L - - - - - - - - - - - { - - : -'' :' -

~1.~~ Denotes a programmable cell location.

J fY

TOALLOMCs

October 22, 1993

57

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z25/PLC18V8ZIA

DESCRIPTION

FEATURES

PIN CONFIGURATIONS

The PLC18VBZ is a universal PAL® device featuring high performance and virtually

· 20-pin Universal Programmable Array Logic

zero-standby power for power sensitive applications. They are reliable, user-configurable substitutes for discrete TTUCMOS logic. While compatible with TTL and HCT logic, the PLC1 BVBZ can also replace HC logic over the Vcc range of 4.5 to 5.5V.
The PLC18VBZ is a two-level logic element comprised of 10 inputs, 74 AND gates (product terms) and 8 output Macro cells.

· Virtually Zero-Standby-power - 20µA (typical)
· Available in 300mil-wide DIP with quartz window, plastic DIP (OTP), PLCC (OTP), and SOL (OTP)
· Functional replacement for Series 20 PAL devices
- loL= 24mA · High-performance CMOS EPROM cell
technology

F7

F6

F5

I'

F4

F3

F2

F1

FO

Each output features an "Output Macro Cell" which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. As a result, the PLC18V8Z is capable of emulating all common 20-pin PAL devices to reduce documentation, inventory, and manufacturing costs.

- Erasable - Reconfigurable - 100% testable · 25ns Max propagation delay (comm) · Up to 18 inputs and 8 inpuVoutput macro cells · Programmable output polarity

N =Plastic Dual In-Line Package (DIP) (300mil-wide) FA= Ceramic DIP with Quartz Window (300mil-wide)
D =Plasitc Small Outline Large Package (300mil-wide)
A Package IOI CLKvcc F7
12 1

A power-up reset function and a Register Preload function have been incorporated in the PLC18V8Z architecture to facilitate state machine design and testing.
With a standby current of less than 1OOµA and active power consumption of 1.5mA/MHz, the PLC18V8Z is ideally suited for power sensitive applications in battery operated/backed portable instruments and computers.
The PLC18VBZ is also processed to industrial requirements for operation over an extended temperature range of -40°C to +85°C and supply voltage of 4.5V to 5.5V.
Ordering information can be found below.

· Power-up reset on all registers · Register Preload capability · Synchronous PreseVAsynchronous Reset · Security fuse to prevent duplication of
proprietary designs · Design support provided using SLICE
software development package and other CAD tools for PLDs
APPLICATIONS
· Battery powered instruments · Laptop and pocket computers · Industrial control · Medical Instruments · Portable communications equipment

18 GND 19/ FO F1 OE
A = Plastic Leaded Chip Carrier

PIN LABEL DESCRIPTIONS

I

Dedicated input

B

Bidirectional inpuVoutput

0

Dedicated output

D

Registered output

(D-type flip-flop)

F

Macrocell lnpuVOutput

CLK Clock Input

O'E

Output Enable

Vee Supply Voltage

GND Ground

ORDERING INFORMATION

DESCRIPTION
20-Pin (300mil-wide) Plastic Dual In-Line Package (tpo = 25ns) 20-Pin (300mil-wide) Ceramic Dual In-Line Package with quartz window (tpo = 25ns) 20-Pin (350mil square) Plastic Leaded Chip Carrier (tpo = 25ns) 20-Pin (300mil-wide) Plastic Small Outline Large Package (tpo = 25ns) 20-Pin (300mil-wide) Plastic Dual In-Line Package (tp0 = 25ns) 20-Pin (300mil-wide) Ceramic Dual In-Line Package with quartz window (tpo = 25ns) 20-Pin (350mil square) Plastic Leaded Chip Carrier Package (tpo = 25ns) 20-Pin (300mil-wide) Plastic Small Outline Large Package (tpo = 25ns)

OPERATING CONDITIONS
Commercial Temperature Range
±5% Power Supplies Industrial
Temperature Range ± 10% Power Supplies

ORDER CODE
PLC18V8Z25N PLC18V8Z25FA PLC18V8Z25A PLC18V8Z25D PLC18V8ZIAN PLC18V8ZIAFA PLC18V8ZIAA PLC18V8ZIAD

DRAWING NUMBER
0408B 0584B 0400E 0172D 0408B 0584B 0400E 01720

PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc.

October 22, 1993

58

853-1580 11164

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices
LOGIC DIAGRAM

Product specification
PLC 18V8Z25/ PLC 18V8ZIA

NOTES: In the unprogrammed or virgin state:
All ceUs are In a conductive state. All AND gate locations are pulled to a logic 'O" (low). Output polarity Is lnvettlng.
October 22, 1993

Pins 1 and 11 are configured as Inputs o and 9, respectively, via the configuration ceD. The clock and UE functions are disabled. AH output macro oells (OMC) are configured as bldlrectlonal 1/0, with the outputs disabled via the direction term. ~~::· Denotes a programmable cell location.
59

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z25/ PLC18V8ZIA

PAL DEVICE TO PLC18V8Z OUTPUT PIN CONFIGURATION CROSS REFERENCE

PIN NO.

PLC 18V8Z

16l8 16H8 16P8 16P8

16R4 16R6 16R8 16RP4 16RP6 16RP8

16L2 16H2 16P2

14L4 14H4 14P4

12L6 12H6 12P6

1

lofCLK

I

CLK CLK CLK

I

I

I

19

F7

B

B

B

D

I

I

I

18

F6

B

B

D

D

I

I

0

17

FS

B

D

D

D

I

0

0

16

F4

B

D

D

D

0

0

0

15

F3

B

D

D

D

0

0

0

14

F2

B

D

D

D

I

0

0

13

F1

B

B

D

D

I

I

0

12

FO

B

B

B

D

I

I

I

11

lg/OE

I

OE OE OE

I

I

I

10L8 10H8 10P8
I 0 0 0 0 0 0 0 0 I

FUNCTIONAL DIAGRAM

The Philips Semiconductors' state-of-the-art Floating-Gate CMOS EPROM process yields bipolar equivalent performance at less than one-quarter the power consumption. The erasable nature of the EPROM process enables Philips Semiconductors to functionally test the
OUTPUT MACRO CELL (OMC)

devices prior to shipment to the customer. Additionally, this allows Philips Semiconductors to extensively stress test, as well as ensure the threshold voltage of each individual EPROM cell. 100% programming yield is subsequently guaranteed.

r---------
1
I I I I I
{ I
:R~~~ :::::E:=::l-_.,>-"'---..<r-~

t FROM AND ARRAY TO ALL OMCs !-------, '

I I II AC1 n~~··Hl>:>-----l-+-1--+---+
I AC2n: I ':'

' ' '
L-----------i--t-~
t tt
TOALLOMCs

_____ ::::_J

NOTE: :::~ Denotes a programmable cell location.

THE OUTPUT MACRO CELL (OMC)
The PLC 18V8Z series devices have 8 individually programmable Output Macro Cells. The 72 AND inputs (or product terms) from the programmable AND array are connected to the 8 OMCs in groups of 9. Eight of the AND terms are dedicated to logic functions; the ninth is for asynchronous direction control, which enables/disables the respective bidirectional 1/0 pin. Two product terms are dedicated for the Synchronous Preset and Asynchronous Reset functions.
Each OMC can be independenHy programmed via 16 architecture control bits, AC1n and AC2n (one pair per macro cell). Similarly, each OMC has a programmable output polarity control bit (Xn). By configuring the pair of architecture control bits according to the configuration cell table, 4 different configurations may be implemented. Note that the configuration cell is automatically programmed based on the OMC configuration.
DESIGN SECURITY
The PLC18V8Z series devices have a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved.

October 22, 1993

60

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z25/ PLC18V8ZIA

CONFIGURATION CELL A single configuration cell controls the functions of Pins 1 and 11. Refer to Functional Diagram. When the configuration cell is programmed, Pin 1 is a dedicated clock and Pin 11 is dedicated for output enable. When the configuration cell is unprogrammed, Pins 1 and 11 are both dedicated inputs. Note that the output enable

for all registered OMCs is common-from Pin 11 only. Output enable control of the bidirectional 1/0 OMCs is provided from the AND array via the direction product term.
If any one OMC is configured as registered, the configuration cell will be automatically configured (via lhe design software) to ensure that the clock and output enable functions are

enabled on Pins 1 and 11, respectively. If none of the OMCs are registered, the configuration cell will be programmed such that Pins 1 and 11 are dedicated inputs. The programming codes are as follows:

Pin 1 = CLK, Pin 11 =OE

L

Pin 1 and Pin 11 = Input

H

FUNCTION Registered mode

CONTROL CELL CONFIGURATIONS

AC1 1

AC!it

CONFIG. CELL

Programmed

Programmed

Programmed

Bidirectional 1/0 mode1 Unprogrammed

Unprogrammed

Fixed input mode

Un programmed

Programmed

Fixed output mode

Programmed

Unprogrammed

NOTE: 1. This is the virgin state as shipped from the factory.

ARCHITECTURE CONTROL-AC1 and AC2

Unprograrnmed Unprogrammed Unprogrammed

COMMENTS
Dedicated clock from Pin 1. OE Control for all registerd OMCs from Pin 11 only.
Pins 1 and 11 are dedicated inputs. 3-State control from AND array only.
Pins 1 and 11 are dedicated inputs.
Pins 1 and 11 are dedicated inputs. The feedback path (via FMuxl is disabled.

F(O), F(D)

F(B), F (B)

CODE B

OMC CONFIGURATION FIXED OUTPUT

CODE 0

3':]1--------- F(I)

N SP n L K Q
A N OE

OMC CONFIGURATION FIXED INPUT

CODE

PIN 1 ·CLK PIN 11 · tlE

CODE

CONFIGURATION CELL
PIN1 ·INPUT PIN11 ·INPUT

NOTES:
A factory shipped unprogrammed device is configured such that: 1. This is the initial unprogrammed state. All cells are in a conductive state. 2. All AND gates are pulled to a logic "O" (Low). 3. Output polarity is inverting. 4. Pins 1 and 11 are configured as inputs O and 9. The clock and OE functions are disabled. 5. All Output Macro Cells (OMCs) are configured as bidirectional 1/0, with the outputs disabled via the direction term.
6. This configuration cannot be used if any OMCs are configured as registered (Code =D).

CODE

October 22, 1993

61

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z25/PLC18V8ZIA

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

PARAMETER

RATINGS

UNIT

Vee

Supply voltage

Vee

Operating supply voltage

--0.5 to +7

Voe

4.5 to 5.5 (Industrial)

4.75 to 5.25 (Commercial)

Voe

V1N Vour
!itl!iv

Input voltage Output voltage
Input/clock transition rise or fall2

--0.5 to Vee+ 0.5 --0.5 to Vee+ 0.5
250

Voe
Voe
nsN
maximum

l1N

Input currents

-10to+10

mA

lour

Output currents

+24

mA

Tamb Ts1g

Operating temperature range Storage temperature range

--40 to +85 (Industrial)

oc

Oto +75 (Commercial)

-S5 to +150

oc

NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS
TEMPERATURE
Maximum junction Maximum ambient Allowable thermal rise ambient to junction

2. All digital circuits can oscillate ortriggerprematurelywhen input rise and fall times are very long. When the input signal to a device is at or near the switching threshold, noise on the line will be amplified and can cause oscillation which, if the frequency is low enough, can cause subsequent stages to switch and give erroneous results. Forthis reason, Schmitt-triggers are recommended if rise/fall times are likely to exceed 250ns at Vee= 4.5V.

150°C 75°C 75°C

AC TEST CONDITIONS
'·y'·
INPUTS
NOTE:
C1 and~ are to bypass Vee to GND.

Vee t:___>

R1

JO

By

CL

19

OUT

Bw

Bx

Bz

GNO

-=

OUTPUTS ':'

VOLTAGE WAVEFORMS

L J l- +3.0V~- . - 90%-

10%

__.J OV

Sns

IR IF

Sns

+3.ov~10L%90%

ov-- nsl---

--lsns

MEASUREMENTS: All circuit delays are measured at the +1.SV level of inputs and outputs, unless otherwise specified.

Input Pulses

October 22, 1993

62

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z25/PLC18V8ZIA

DC ELECTRICAL CHARACTERISTICS Commercial= oog: s T.,..., s +75"C, 4.75V s Vee s 5.25V; lndusbial =--40"C ST.,...,s +85"C, 4.5V s Vee s5.5V

SYMBOL

PARAMETER

Input voltage

V1L

Low

V1H

High

Output voltage2

VOL

Low

VOH

High

Input current

l1L

Low7

l1H

High

Output current

lo(OFF)

Hi-Z state

las

Short-circuit3

Ice

Vee supply current (Standby)

Ice/I

Vee supply current (Active)4

Cepacltance

C1

Input

Ce

1/0

TEST CONDITION
Vcc=MIN Vee= MAX
Vee= MIN, loL = 20µA Vee= MIN, loL = 24mA Vee = MIN, IOH = ~.2mA Vee= MIN, loH =-20µA
V1N =GND V1N =Vee
VouT= Vee VouT=GND VouT=GND Vee = MAX, V1N = 0 or Vcc8 Vcc = MAX (Cl\AOS inputs)5· 6
Vcc=5V V1N=2.0V Ve= 2.0V

LIMITS

MIN

TYP1

MAX

UNIT

-0.3

0.8

v

2.0

Vcc+0.3

v

2.4 Vcc-0.1V

0.100

v

0.500

v

v v

-10

µA

10

µA

10

µA

-10

µA

-130

mA

20

100

µA

1.5

mA/MHz

12

pF

15

pF

100p.A 0 0"-~'--~,2'--~,s'--~~...___,~
!(MHz)
Figure 1. Ice vs Frequency&. 6 (Worst Case)

v IL1
lLv lZ"
Y1
I
-1 IL1
-2 0 20 40 60 80 100 120 140 160 180 200 OUTPUT CAPACITANCE LOADING (pF)
Figure 2. &tpo vs Output Capacitance Loading (Typical)

NOTES:
1. All typical values are at Vee = 5V, Tarm = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Duration of short-circuit should not exceed one second. Test one at a time. 4. Tested with TTL input levels: V1L = 0.45V, V1H = 2.4V. Measured with all outputs switching. 5. &Ice/TTL input = 2mA. 6. &Ice vs frequency (registered configuration) = 2mA/MHz. 7. l1L for Pin 1 (lo/CLK) is± 1OµA with V1N= 0.4V. 8. V1N includes CLK and OE if applicable.

October 22, 1993

63

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18VSZ25/PLC18V8ZIA

AC ELECTRICAL CHARACTERISTICS4 Commercial= 0°C s; Tant> s; +75°C, 4.75V s; Vee .s 5.25V; lndusbial = --40°C s Tant> s +as·c, 4.5V s Vee s 5.5V; R2 = 3900

TEST CONDITION'

PLC18VBZ25 PLC18V8ZIA (Commercial) (Industrial)

SYMBOL

PARAMETER

FROM

TO

R, (Q)

CL (pF)

MIN

MAX

MIN

MAX UNIT

1, 4,

Pulse width

Clock period

lcKP

(Minimum tis + lcKol

CLK+ CLK+

200

50

33

33

ns

lcKH

Clock width High

CLK+ CLK-

200

50

15

15

ns

lcKL

Clock width Low

CLK- CLK+

200

50

15

15

ns

IARW

Async reset pulse width

1±, F± I+, F +

25

25

ns

Hold time

t1H

Input or feedback data hold time

CLK+ Input±

200

50

0

0

ns

Setup time

Input or feedback

tis

data setup time

1±, F± CLK+

200

50

18

18

ns

Propagation delay

lpD

Delay from input to active output

1±,F±

F±

200

50

25

25

ns

lcKO

Clock High to output valid access lime

CLK+

F±

200

50

15

15

ns

loE1 3·

Product term enable to outputs off

I±, F±

F±

Active-High R = 1.5k Active-Low R = 550

50

25

25

ns

loDt 2

Product term disable to outputs off

1±, F±

F±

From VoH R = oo From Vol R = 200

5

25

25

ns

loD22

Pin 11 output disable High to outputs off

OE-

F±

From VoH R = oo From Vol R = 200

5

20

20

ns

loE23

Pin 11 output enable to active output

OE+

F±

Active-High R = 1.5k Active-Low R = 550

50

20

20

ns

tARD

Async reset delay

1±,F±

F+

30

30

ns

IARR

Async reset recovery time

ls PR

Sync preset recovery time

tppR

Power-up reset

Frequency of operation

1±, F± 1±, F± Vee+

CLK+ CLK+
F+

20

20

ns

20

20

ns

25

25

ns

IMAX

Maximum frequency

l/(t1s + lcKo)

200

50

30

30 MHz

NOTES:
1. Refer also to AC Test Conditions. (Test Load Circuit).
s 2. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and 1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of Vr = (VoH -0.5V) with 8 1 open, and Low-to-High impedance tests are made to the Vr =(Vol+ 0.5V) level with 8 1closed. 3. Resistor values of 1.5k and 550Q provide 3-State levels of 1.0V and 2.0V, respectively. Output timing measurements are to 1.5V level.
4. Leave all the cells on unused product terms intact (unprogrammed) for all patterns.

October 22, 1993

64

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z25/PLC18V8ZIA

POWER-UP RESET In order to facilitate state machine design and testing, a power-up reset function has been incorporated in the PLC1BVBZ. All internal registers will reset to Active-Low (logical "O") after a specified period of time (tppR)·

Therefore, any OMC that has been configured as a.registered output will always produce an Active-High on the associated output pin because of the inverted output buffer. The internal feedback (0) of a

registered OMC will also be set Low. The programmed polarity of OMC will not affect the Active-High output condition during a system power-up condition.

TIMING DIAGRAMS

,r-----------------, INPUTS "7''7"lL1-------,

l"'T7""'7'T:,..,"'T7""'7'7'7

VO, REG. FEEDBACK

CUC

PIN 11 OE

r---"°' r - - - - ANY INPUT "7''T:l"17"'T7""'7'T:,..,"'T7""'7''7"'.:,..,"'T,...,"'7'.,..,"'7''7"l,..,"'T7""'7'T:,..,"'T.,..,"'7"- ..
PROGRAMMED FOR
' - - - - - DIRECTION CONTROL ;...&.-'-4111~"'-'~-'-""'~"'-'~-'-""'~"'-'~..L..~~""'~"'-'~-'-""'~"'-'~.ll'----.1
COMBINATORIAL
OUTPUTS"-11~..L..~~LJ.~..L..~~l"I.--------------------''
Switching Waveforms

Vee

ov

F (OUTPUTS)
Vol
+3V l,B (INPUTS)
ov
+3V CLK
ov

NOTE: Diagram presupposes that the outputs (F) are enabled. The reset occurs regardless of the output condition (enabled or disabled).
Power-Up Reset

October 22, 1993

65

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices
TIMING DIAGRAMS (Continued)
ASYNCHRONOUS RESET INPUT

Product specification
PLC18V8Z25/PLC18V8ZIA

CLOCK
SYNCHRONOUS PRESET INPUT
CLOCK
REGISTERED OUTPUT

Asynchronous Reset tis - + 1 4 - - - t1H1---+t----1sp~---+1
KO
Synchronous Preset

October 22, 1993

66

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC18V8Z25/PLC18V8ZIA

REGISTER PRELOAD FUNCTION (DIAGNOSTIC MODE ONLY)
In order to facilitate the testing of state machine/controller designs, a diagnostic mode register preload feature has been incorporated into the PLC18V8Z series device. This feature enables the user to load

the registers with predetermined states while a super voltage is applied to Pins 11 and 6 (19/0E and 15). (See diagram for timing and sequence.)
To read the data out, Pins 11 and 6 must be returned to normal TTL levels. The outputs, FO - F7, must be enabled in order to read

data out The Q outputs of the registers will
reflect data in as input via FO - Fl during preload. Subsequently, the register Q output via the feedback path will reflect the data in as input via FO - F7.
Refer to the voltage waveform for timing and
voltage references. lpL = 1Oµsec.

REGISTER PRELOAD (DIAGNOSTIC MODE)

IS/OE (PIN 11)

5.0V

12.0V

15 (PING)

- - - - - - - - - ~~--------

I -----r-----~

(PIN1J--------+---------+-----..;l------I""---'
~ ;,-~~~~~-i~°""I
PRELOAD DATA IN

DATA OUT

IQ/CLK F0-7

11-4, fHl

11-4, fHl

October 22, 1993

67

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices

Product specification
PLC 18V8Z25/ PLC18V8ZIA

LOGIC PROGRAMMING
The PLC 1SVSZ series is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semic<>nductors' SNAP design software package. ABELTM and CUPLTM design software packages also support the PLC18V8Zarchitecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.

PLC 1SVSZ logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only.
With Logic programming, the AND/OR/EX-OR gate input connections necessary to implement the desired logic function are coded directly from logic equations using the Program Table. Similarly,

various OMC configurations are implemented by programming the Architecture Control bits AC 1 and AC2, Note that the configuration cell is automatically programmed based on the OMC configuration.
In this table, the logic state of variables I, P and B associated with each Sum Term S is assigned a symbol which results in the proper fusing pattern of corresponding link pairs, defined as follows:

OUTPUT POLARITY - (0, B)

0,1>

O,B

l ACTIVE LEVEL ] l INVERTING1 ]

J CODE L 1

f l j ACTIVE LEVEL
r 1 NON-INVERTING

CODE H

l,Bi l,B I,Bil,B I,Bil,B "AND"ARRAY- (I,B)

1.ll

1,ll

1,1>

STATE DON'T CARE

p
STATE INACTIVE1

p
STATE I, B

NOTE: 1. A factory shipped unprogrammed device is configured such that all cells are in a conductive state.

l,B il,B 1,1>
p STATE
1.1>

ERASURE CHARACTERISTICS (For Quartz Window Packages Only)
The erasure characteristics of the PLC18V8Z Series devices are such.that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lighting could erase a typical PLC18V8Z in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. If the PLC18V8Z is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the window to prevent unintentional erasure.

The recommended erasure procedure for the PLC 18V8Z is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15Wsecicrn2. The erasure time with this dosage is approximately 30 to 35 minutes using an ultraviolet lamp with a 12,000µW/cm2 power rating. The device should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose a CMOS EPLD can be exposed to without damage is 7258Wsec/cm2). Exposure of these CMOS EPLDs to high intensity UV light for longer periods may cause permanent damage.

The maximum number of guaranteed erase/write cycles is 50. Data retention exceeds 20 years.
PROGRAMMING/SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer! Software Support) of this data handbook for additional information.

ABEL is a trademark of Data 1/0 Corp. CUPL is a trademark of Logical Devices, Jnc.

October 22, 1993

68

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices
PROGRAM TABLE

Product specification
PLC18V8Z25/PLC18V8ZIA

CONAGURATIOll CELL (CLl<IOE CONTROL)I::J
A~ic,.~~r--<--+-+-+--+--+--+---<

AND
f(I)
_jJ_ _LJ ...6-...5.. J_ _a_ _2.___]_ :_a_

OR(AXED) F(B, 0, D)

15
:I
23

October 22, 1993

xxxx
LC
.()

U.I
t: ~'!-+--t---+--+--+-+-1----l--+-+-+-+--+-+-+-l----l--+-1
a l--'!~--+~--+--+--+-+--1----1--+-+--+--+--+-~+--1----1---J

Ia-:

it

U.I ~
z<t: a:
U.I ~
~
(/)
:::>
()

.
a: Uaa.:I
0
U.I
(/)
:<ct:
()
a:
:::>
0...

.
U.I ()
>
Ua.I
(/)
0...
;J :c
0...

a
U.I
N::::; 0
CD ~
>-
(/)
a:
U.I ~
~
(/)
:::>
()

(/)
Ia-:
<t:
0...
LL
0
a:
U.I CD ~
:z::>
--'
f:!'
:2

'*" ~~-+-+--+-+-+-i--j1--+--+-+--+--+--+-It-i--j1--+---J
U.I .._,,,.....;--+--t--+--+-+-+-j--+-+-+--+--+--+---+--+-<--+---i
f:!' ~~~~=~=~~~~=~=~~~~=~=~=~~=~=I~=~~~~~ 115 ~.--+-+--+---+---+-+-+-j--+-+-+--+--+--+---+--+-<--+---i

~ ~~-+-+-+--+-+-f--jl--+--+-+--+--+--+-+-f--jl--+---j
<t: ,.......,~-+~--+---+-+-,.......,--+-+-+--+--+--+---~+-<--+---i
ffi lf/l, lli ::n:D_n: ::n:~.r:I ::aJ::2:

0a:

~uJ .,:=;

a... ~~

>

AND ARRAY

INACTIVE 0

l,F 1,11)

H

l!.£jl II)_ L

"DON'T CARE -

CONTROL

OMC ARCH.

OUTPUT POLARITY

R.0-ETYGISP,T}RED

L D : NON-INVERTING

f-'-"""-'-~,..,_,___--+--1 , [INVERTING

II HL]J

AXED INPUT

I

CONRG.CELL'

AXED OUTPUT

0

BIDIRECTIONAL 1/0 B

[PIN 1· CLK: PIN 11. UET L]
LPIN PIN - INPUT l~ Hj 1 "-

OR ARRAYJ:AXEQL
DATA CANNOT BE ENTERED INTO THE OR ARRAY AELD DUE TO THE AXED NATURE OF THE DEVICE ARCHITEC~TU_R_ E _ _ __

[ DIRECTION CONTROU DJ

J I [ ACTIVE OUTPUT

A

.l:'.:J LNOTUSED

· THE CONAGURATION CELL IS AUTOMATICALLY PROGRAMMED BASED ON THE OMC ARCHITECTURE. ··FOR SP, AR:"-" IS NOT ALLOWED.

69

Philips Semiconductors Programmable Logic Device Products
Zero standby power CMOS versatile PAL devices
SNAP RESOURCE SUMMARY DESIGNATIONS
11
12
17
18

Product specification
PLC18V8Z25/PLC18V8ZIA

r----------
1
I I I I I I I

FROM AND
ARRAY · TO ALL OMCs
---' t--------, I I I

I I
I AC1n I I AC2n
I I

' ' ' ' '

I

:

NOTE:

L------------1--,-,-

~ Denotes a programmable cell location.

Y YY

TOALL0MCs

I I ·'::l"!lMUJI,' - I ------=-_J
::'®.UY!!:

October 22, 1993

70

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8,16R8,16R6,16R4

Product specification
PLUS16R8D/·7 SERIES

FEATURES
· Ultra high-speed - !po = 7.5ns and IMAX = 74MHz for the PLUS1SR8-7 Series
- tpo = 1Ons and IMAX = SO MHz for the
PLUS1SR8D Series
· 100% functionally and pin-for-pin compatible with industry standard 20-pin PAL®ICs
· Power-up reset function to enhance state machine design and testability
· Design support provided via SNAP and other CAD tools for Series 20 PAL devices
· Field-programmable on industry standard programmers
·Security fuse
· Individual 3-State control of all outputs

DESCRIPTION
The Philips Semiconductors PLUS1SXX family consists of ultra high-speed 7.5ns and 1Ons versions of Series 20 PAL devices.
The PLUS1SXX family is 100% functional and pin-compatible with the 1SL8, 1SR8, 1SRS, and 1SR4 Series devices.
The sum of products (AND-OR) architecture is comprised of S4 programmable AND gates and 8 fixed OR gates. Multiple bidirectional pins provide variable input'output pin ratios. Individual 3-State control of all outputs and registers with feedback (RS, RS, R4) is also provided. Proprietary designs can be protected by programming the security fuse.
The PLUS16R8, RS, and R4 have D-type flip-flops which are loaded on the Low-to-High transition of the clock input.
In order to facilitate state machine design and testing, a power-up reset function has been incorporated into these devices to reset all

internal registers to Active-Low after a specific period of time.
The Philips Semiconductors State-of-the-Art oxide isolation Bipolar fabrication process is employed to achieve high-performance operation.
The PLUS1SXX family of devices are field programmable, enabling the user to quickly generate custom patterns using standard programming equipment. See the programmer chart for qualified programmers.
The SNAP software package from Philips Semiconductors supports easy design entry for the PLUS1SXX series as well as other PLD devices from Philips Semiconductors. The PLUS1 SXX series are also supported by other standard CAD tools for PAL-type devices.
Order codes are listed in the Ordering Information table.

DEVICE NUMBER
PLUS1Sl8 PLUS1SR8 PLUS1SR6 PLUS16R4

DEDICATED INPUTS 10 8 8 8

COMBINATORIAL OUTPUTS
S(Sl/O) 0
21/0 41/0

REGISTERED OUTPUTS
0
8
s
4

ORDERING INFORMATION

DESCRIPTION

ORDER CODE

20-Pin Plastic Dual-In-Line 300mil-wide

PLUS16R8DN PLUS16RSDN PLUS1SR4DN PLUS16l8DN PLUS16R8-7N PLUS16R6-7N PLUS1SR4-7N PLUS16L8-7N

20-Pin Plastic Leaded Chip Carrier (PLCC)

PLUS1SRBDA PLUS1SRSDA PLUS1SR4DA PLUS1SL8DA PLUS16R8-7A PLUS16R6-7A PLUS1SR4-7A PLUS16LB-7A

NOTE:
The PLUS1SXX series of devices are also processed to military requirements for operation over the military temperature range. For specifications and ordering information, consult the Philips Semiconductors Military Data Book.

DRAWING NUMBER 0408B
0400E

®PAL Is a registered trademark of Advanced Micro Devices, Inc.

September 10, 1993

71

853-135810777

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8,16R8,16R6, 16R4

PIN CONFIGURATIONS
PLUS16L8

lo
11

12

13

'4

AND

OR

ARRAY

Is

Is

17

la

Vee
0-,
Os
85 84 83 B2 81
Oo
11 19

PLUS16L8

PLUS16R8 PLUS16R8

Product specification
PLUS16R8D/-7 SERIES

la GND lg 0o 81

SYMBOL I 0 Q
B CLK OE
Vee
GND

DESCRIPTION Dedicated Input Dedicated corrbinatorial Output Registered output Bidirectional (inplJl/output) Clock Input Output Enable
Supply Voltage Ground

17 GND OE <lo 01

SYMBOL I 0 Q
B CLK OE
Vee
GND

DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable
Supply Voltage
Ground

September 10, 1993

72

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8, 16R8, 16R6, 16R4
PIN CONFIGURATIONS
PLUS16R6

PLUS16R4

Product specification
PLUS16R8D/-7 SERIES

PLUS16R6

PLUS16R4

1-, GND OE Bo 01

SYMBOL
I
0
a
B
eLK
OE
Vee
GND

DESCRIPTION Dedicated tnput Dedicated combinatorial Output Registered output Bidirectional (inpuUoutput) Clock input Output Enable
Supply Voltage Ground

17 GND OE Bo B1

SYMBOL I 0
Q B CLK OE
Vee
GND

DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (inpuVoutput) Clock input Output Enable
suwly Voltage
Ground

September 10, 1993

73

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8, 16R8, 16R6, 16R4
LOGIC DIAGRAM

Product specification
PLUS16R8D/-7 SERIES
PLUS16L8
I I~

INPUTS (0-31)

31

NOTES:

t t 1. A!I. unprogrammed or virgin "AND" gate locations are pulled to logic "O".

2.

Programmable connections.

September 10, 1993

74

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8, 16R8, 16R6, 16R4
LOGIC DIAGRAM

Product specification
PLUS16R8D/-7 SERIES
PLUS16R8

INPUTS(~1)

31

NOTES: 1. .N.1. unprogrammed or virgin ·AND" gate locations are pulled to logic "0''. 2. ···:····· Programmable connections.

September 10, 1993

75

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8, 16R8, 16R6, 16R4
LOGIC DIAGRAM

Product specification
PLUS16R8D/-7 SERIES
PLUS16R6

0

INPUTS (0-31)

31

NOTES:
1. 1!)._unprogrammed or virgin "AND" gate locatfons are pulled to logic "0". 2. :f} Programmable connections.

September 10, 1993

76

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8, 16R8, 16R6, 16R4
LOGIC DIAGRAM

Product specification
PLUS16R8D/-7 SERIES
PLUS16R4

INPUTS (G-31)

31

NOTES:
1. "IJ unprogrammed or virgin "AND" gate locations are pulled to logic "O". 2. :::;:;:::: Programmable connections.

September 10, 1993

77

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8,16R8, 16R6, 16R4

Product specification
PLUS16R8D/-7 SERIES

FUNCTIONAL DESCRIPTIONS
The PLUS16XX series utilizes the familiar sum-of-products implementation consisting of a programmable AND array and a fixed OR array. These devices are capable of replacing an equivalent of four or more SSl/MSI integrated circuits to roouce package count and board area occupancy, consequently improving reliability and design cyde over Standard Cell or gate array options. By programming the security fuse, proprietary designs can be protected from duplication.
The PLUS16XX series consists of four PAL-type devices. Depending on the particular device type, there are a variable number of combinatorial and registered outputs available to the designer. The PLUS16L8 is a combinatorial part with 8 user configurable outputs (6 bidirectional), while the other three devices, PLUS16R8, PLUS16R6, PLUS16R4, have respectively 8, 6, and 4 output registers.
3-State Outputs
The PLUS16XX series devices also feature 3-State output buffers on each output pin which can be programmed for individual control of all outputs. The registered outputs (On) are controlled by an external input (/OE), and the combinatorial outputs (On, Bn)

use a product term to control the enable function.
Programmable Bidirectional Pins
The PLUS16XX products feature variable Input/Output ratios. In addition to 8 dedicatoo inputs, each combinatorial output pin of the registered devices can be individually programmed as an input or output. The PLUS16L8 provides 10 dedicated inputs and 6 Bidirectional 1/0 lines that can be individually configured as inputs or outputs.
Output Registers
The PLUS16RB has 8 output registers, the 16R6 has 6, and the 16R4 has 4. Each output register is a D-type flip-flop which is loaded on the Low-to-High transition of the clock input. These output registers are capable of feeding the outputs of the registers back into the array to facilitate design of synchronous state machines.
Power-up Reset
By resetting all flip-flops to a logic Low, as the power is turned on, the PLUS16R8, R6, R4 enhance state machine design and initialization capability.
Software Support
Like other Programmable Logic Devices from Philips Semiconductors, the PLUS16XX

series are supported by SLICE, the PC-based software development tool from Philips Semiconductors. The PLUS16XX family of devices are also supported by standard CAD tools for PAL devices, including ABEL and CUPL.
SLICE is available free of charge to qualified users.
Logic Programming
The PLUS16XX series is fully supportoo by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL'" CUPLTM and PALASM® 90 design software packages also support the PLUS16XX architecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
Programming/Software Support
Ref to Section 9 (Development Software) and Section 10. (Third-Party Programmer/ Software Support) of the PLD data handbook for additional information.

AND ARRAY - (I, 8)

4 " l,B 1.0

P,D

t J STATE

j CODEj

INACT1VE1· 2 j 0

4'" l,B 1.0

ESTATE l,B

P,D
IC~DE I

VIRGIN STATE
A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at "H" polarity.
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.

4 " l,B

i, e

P, D

I I I STATE

C~E

i, B

4'" l,B 1.0

P,D

I I I STATE DON'T CARE

C~DE

ABEL is a trademark of Data 1/0 Corp. CUPL is a trademark of Logical Devices, Inc. PALASM is a registered trademark of AMO Corp.

September 10, 1993

78

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8,16R8, 16R6, 16R4

Product specification
PLUS16R8D/-7 SERIES

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee

Supply voltage

--0.5

+7

Voe

V1N

Input voltage

-1.2

+8.0

Voe

Vour

Output voltage

--0.5

Vee +0.5V

Voe

l1N

Input currents

-30

+30

mA

lour

Output currents

+100

mA

Tstg

Storage temperature range

-BS

+150

oc

NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS

TEMPERATURE

Maximum junction

c 1so0

Maximum ambient

75°C

Allowable thermal rise ambient to junction

75°C

OPERATING RANGES

SYMBOL Vee Tamb

PARAMETER Supply voltage Operating free-air temperature

RATINGS

MIN

MAX

+4.75

+5.25

0

+75

UNIT
Voe
oc

September 10, 1993

79

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8, 16R8,16R6, 16R4

Product specification
PLUS16R8D/-7 SERIES

DC ELECTRICAL CHARACTERISTICS
0°c s Tanti s +75°C, 4.75 s Vee s5.25V

SYMBOL

PARAMETER

TEST CONDITIONS

Input voltage2

V1L

Low

V1H

High

Vic

Clamp

Output voltage

Vee= MIN Vee =MAX Vee= MIN, l1N = -18mA

Vol

Low

VoH

High

Input current

Vee= MIN, V1N = V1H or V1L loL = 24mA
loH=-3.2mA

l1L

Low3

l1H

High3

11

Maximum input current

Output current

Vee=MAX V1N = 0.40V V1N = 2.7V V1N =Vee= VccMAX

loZH

Output leakage

lozL

Output leakage

los

Short circuit 4· 5

Ice

Vee supply current

Capacitance6

Vee=MAX Vour = 2.7V Vour=0.4V
Vour= ov
Vee =MAX

C1N

Input

Vee= 5V

Vour = 2.0V

Ca

1/0(8)

Vour = 2V, f = 1MHz

NOTES:
1. All typical values are at Vee= 5V, Tarrt> = +25°C. 2. All voltage values are with respect to network ground terminal.
3. Leakage current for bidirectional pins is the worst case of 11L and lozL or l1H and lozH· 4. Test one at a time. 5. Duration of short circuit should not exceed 1 second. 6. These parameters are not 100% tested but periodically sampled.

LIMITS

MIN

TYP1

MAX

0.8

2.0

--0.8

-1.5

0.5 2.4

-250 25 100

100

-100

-30

-90

160

180

8 8

UNIT
v v v
v v
µA µA µA
µA µA mA mA
pF pF

September 10, 1993

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Philips Semiconductors Programmable Logic Devices
PAL devices 16L8, 16R8, 16R6, 16R4

Product specification
PLUS16R8D/-7 SERIES

AC ELECTRICAL CHARACTERISTICS
R1 = 2000, R2 = 3900, 0°C 5Tamb5 +75°C, 4.75:;; Vee5 5.25V

LIMITS

SYMBOL

PARAMETER

FROM

TO

-7

D

UNIT

MIN1

TVP

MAX

MIN1

MAX

Pulse Width

lcKH

Clock High

lcKL

Clock Low

lcKP

Period

Setup & Hold time

CK+ CKCK+

CK-

5

CK+

5

CK+

10

7

ns

7

ns

14

ns

tis

Input

Input or feedback

CK+

7

9

ns

t1H

Input

CK+

Input or feedback

0

0

ns

Propagation delay

lcKO lcKF tpo foE1 foE2 too1

Clock Clock3 Output (16L8, R6, R4)2 Output enable4 Output enable4,5 Output disable4

CK± CK± I, B
OE
I
OE

0±

3

0

Output

3

Output enable

3

Output enable

3

Output disable

3

6.5

3

7.5

ns

3

6.5

ns

7.5

3

10

ns

8

3

10

ns

10

3

10

ns

8

3

10

ns

too2

Output disable4,5

!sKW

Output

tppR

Power-Up Reset

Frequency (16R8, R6, R4)

I Q Vee+

Output disable

3

Q

O+

10

3

10

ns

1

1

ns

10

10

ns

No feedback 1/ (lcKL + lcKH)6

100

71.4

MHz

IMAX

Internal feedback 1/ (t1s + teKF)6

90

64.5

MHz

External feedback 1I (t1s + teKo)6

74

60.6

MHz

· For def1rnt1ons of the terms, please refer to the Timing/Frequency Definitions tables. NOTES:
1. CL= OpF while measuring minimum output delays.
2. !po test conditions: CL= 50pF (with jig and scope capacitance), V1H = 3V, V1L = OV, VoH = VoL = 1.5V. 3. lcKF was calculated from measured Internal IMAX· 4. For 3-State output; output enable times are tested with CL= 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output voltage of VT= (VoH-0.5V) with S 1open, and Low-to-High impedance tests are made to the VT= (VoL + 0.5V) level with S 1 closed. 5. Same function as toE1 and too1, with the difference of using product term control.
6. Not 100% tested, but calculated at initial characterization and at any time a modification in design takes place which may affect the frequency.

September 10, 1993

81

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8, 16R8,16R6, 16R4
TEST LOAD CIRCUIT

Product specification
PLUS16R8D/-7SERIES

<>--r- lo
I I
I I
INPUTS I
o-1- In

lln/On

OUT

<lo

o--- CLK

OE

GND

NOTE: C1 and~ are to bypass Vee to GND.

OUTPUT REGISTER SKEW

CLK

~r--------------~

_ _ _._ - - - - - - - - - - - - - - - - - - ov

-----------...Jz- a,,
(REGISTERED OUTPUT)

~1.SV

---------~

On+1 (REGISTERED OUTPUT)

1.SV

3V
ov
3V
ov

CLOCK TO FEEDBACK PATH

September 10, 1993

tcKF 82

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8,16R8, 16R6, 16R4

Product specification
PLUS16R8D/-7 SERIES

TIMING DIAGRAMS1, 2
l,B (INPUTS)
CLK
Q (REGISTERED OUTPUTS)
~~.;i...:i..~~.:i.j

Flip-Flop Outputs
1------------------------+3V (INPU~:i1_.s_v_______________________ ov

----1po-----..i

0,B (COMBINATORIAL
OUTPUTS)

VoH

'LtoD2

l,B (OUTPUT

...__-_-_-_-_-_-_---~----_-_-..1)1(~--------::v

ENABLE) _ _ _ _ _--J

Gate Outputs

Q

.....,........ . . . . . - - - - - - - . . . - - - - - - - - - - - - - VoH

(REGISTERED

1.sv

1.SV

OUTPUTS)~....... . - . _ ........

' - - - - - - - - - - - - Vol

'· B----~ '1-.s-v---t---, , - - - - - - - - - - +3V

,------- +3V -------J (INPUTS)

~-----+------J ~------------------ov

CLK

1.SV

Power-Up Reset
NOTES: 1. Input pulse amplitude is OV to 3V. 2. Input rise and fall times are 2.5ns.

TIMING DEFINITIONS

SYMBOL PARAMETER

lcKH

Width of input clock pulse.

leKL

Interval between clock pulses.

le KP

Clock period.

Required delay between

Its

beginning of valid input and

positive transition of clock.

Required delay between

l1H

positive transition of clock and

end of valid input data.

Delay between positive

transition of clock and when

lcKF

internal 0 output of flip-flop

becomes valid.

lcKO

Delay between positive transition of clock and when outputs become valid (with OE Low).

Delay between beginning of

loE1

Output Enable Low and when

outputs become valid.

Delay between beginning of

loD1

Output Enable High and when

outputs are in the Off-State.

Delay between predefined

Output Enable High, and

loE2

when combinational outputs

become valid.

Delay between predefined

Output Enable Low and when

loo2

combinational outputs are in

the Off-State.

Delay between Vee (after

tppR

power-on) and when flip-flop outputs become preset at "1"

(internal Q outputs at "0").

Propagation delay between

tpo

combinational inputs and

outputs .

FREQUENCY DEFINITIONS
No feedback: Determined by the minimum clock period, 1/(lcKL + tcKH)lnternal feedback: Determined by the internal delay from flip-flop outputs through the internal feedback and array to the flip-flop inputs, 1/(t1s + lcKF)External feedback: Determined by clock-to-output delay and input setup time, 1/(t1s + lcKO)-

September 10, 1993

83

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8, 16R8,16R6, 16R4

Product specification
PLUS16R8D/-7 SERIES

OUTPUT REGISTER PRELOAD

The output registers can be preloaded to any desired state during devioe testing. This permits any state to be tested without having to step through the entire state-machine sequenoe. Each register is preloaded individually by following the steps given below.

Step 1. Step 2. Step 3. Step 4.

With Vee at 5V and Pin 1 at V1L. raise Pin 11 to ViHH· Apply either V1L or V1H to the output corresponding to the register to be preloaded. Pulse Pin 1, clocking in preload data. Remove output voltage, then lower Pin 11 to VIL· Preload can be verified by observing the voltage level at the output pin.

PIN1~

'\J"------ V1HH

.-----.i ----r-:------ I

fsu

l(j

I

I

V1L

lI 1<t

tw I

I I

V1H

PIN 1_c_Loc_K_ _-r-I_ __..__ __.

.

I I

ViL

I

I I

I I

I I _ _ _ _ _ _ _ _ _ ,_ V1H

I I

'd 11 _.,.__ _ _ VQH

REGISTERED 1/0

INPUT

><·~

- - - - - - - - - - - V1L

VQL

NOTE: 'd. tsu. t,v. 100ns to 1000ns.
V1HH · 10.25Vto 10.75V. Pin number references for DIP package.

September 10, 1993

84

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8, 16R8, 16R6, 16R4

Product specification
PLUS16R8D/-7 SERIES

PROGRAMMING/SOFTWARE
Refer to Section 9 (Development Software) and Section 1o (Third-Party Programmer/Software Support) of this data handbook for additional information.
SNAP RESOURCE SUMMARY DESIGNATIONS

PROGRAMMABLE AND ARRAY

·t11NPAL1:

00,07

PLUS16L8

81-86

)DINPAL7·

PROGRAMMABLE AND ARRAY

September 10, 1993

QO

Q7

PLUS16R8

85

Philips Semiconductors Programmable Logic Devices
PAL devices 16L8, 16R8, 16R6, 16R4
SNAP RESOURCE SUMMARY DESIGNATIONS (Continued)

Product specification
PLUS16R8D/-7 SERIES

PROGRAMMABLE AND ARRAY

BO, 87

PLUS16R6

01-06

PROGRAMMABLE AND ARRAY

BO, 81, 86, 87 September 10, 1993

PLUS16R4 86

02-05

Phlllps Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4

Product specification
PLUS20R8D/-7 SERIES

FEATURES
· Ultra high-speed - !po = 7.5ns and IMAX= 74MHz for the PLUS20RB-7 Series - !po = 1Ons and IMAX = 60 MHz for the PLUS20RBD Series
· 100% functionally and pin-for-pin compatible with industry standard 24-pin PAL®ICs
· Power-up reset function to enhance state machine design and testability
· Design support provided via SLICE and other CAD tools for Series 24 PAL devices
· Field-programmable on industry standard programmers
· Security fuse
· Individual 3-State control of all outputs

DESCRIPTION
The Philips Semiconductors PLUS20XX family consists of ultra high-speed 7.5ns and 1Ons versions of Series 24 PAL devices.
The PLUS20XX family is 100% functional and pin-compatible with the 20L8, 20R8, 20R6, and 20R4 Series devices.
The sum of products (AND-OR) architecture is comprised of 64 AND gates and 8 fixed OR gates. Multiple bidirectional pins provide variable input/output pin ratios. Individual 3-State control of all outputs and registers with feedback (RB, R6, R4) is also provided. Proprietary designs can be protected by programming the security fuse.
The PLUS20R8, RS, and R4 have D-type flip-flops which are loaded on the Low-to-High transition of the clock input.
In order to facilitate state machine design and testing, a power-up reset function has been incorporated into these devices to reset all

internal registers to active-Low alter a specific period of time.
The Philips Semiconductors State-of-the-Art oxide isolation Bipolar fabrication process is employed to achieve high-performance operation.
The PLUS20XX family of devices are field programmable, enabling the user to quickly generate custom patterns using standard programming equipment. See the programmer chart for qualified programmers.
The SNAP software package from Philips Semiconductors supports easy design entry for the PLUS20XX series as well as other PLO devices from Philips Semiconductors. The PLUS20XX series are also supported by other standard CAD tools for PAL-type devices.
Order codes are listed in the Ordering Information table.

DEVICE NUMBER
PLUS20L8 PLUS20RB PLUS20R6 PLUS20R4

DEDICATED INPUTS 14 12 12 12

ORDERING INFORMATION DESCRIPTION

24-Pin {300mils-wide) Plastic Dual-In-Line Package {DIP)

28-Pin {300mils-wide) Plastic Leaded Chip Carrier {PLCC)

COMBINATORIAL OUTPUTS
8(61/0)
0
21/0
41/0
ORDER CODE
PLUS20R8DN PLUS20R6DN PLUS20R4DN PLUS20L8DN PLUS20R8-7N PLUS20R6-7N PLUS20R4-7N PLUS20L8-7N
PLUS20R8DA PLUS20R6DA PLUS20R4DA PLUS20L8DA PLUS20R8-7A PLUS20R6-7A PLUS20R4-7A PLUS20L8-7A

REGISTERED OUTPUTS 0 8 6 4
DRAWING NUMBER
04100
0401F

apAL Is a registered trademark of Advanced Micro Devices, Inc.

September 10, 1993

87

853--135910778

Philips Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4

Product specification
PLUS20R8D/-7 SERIES

PIN CONFIGURATIONS
PLUS20L8

PLUS20R8

lo

Vee

Vee

11

113

lo

111

,,

0-,

11

Q7

Bs

12

Os

85

Q5

84

04

Is

83

03

82

Is

02

la

B1

o1

lg

Bo

la

Oo

110

112

lg

110

GND

111

GND

OE

PLUS20L8

PLUS20R8

SYMBOL I 0
a
B CLK OE
Vee GND NC

DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable
Supply Voltage Ground No Connec1ion

la lg GNDNC OE 110 0o

SYMBOL I 0 0 B CLK OE
Vee
GND NC

DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable
Supply Voltage
Ground No Connection

September 10, 1993

88

Philips Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4

Product specification
PLUS20R8D/-7 SERIES

PIN CONFIGURATIONS
PLUS20R6

PLUS20R4

Vee

Vee

In

In

87

87

°'

Ila

Os

05

a.

a.

~

03

<l:z

<l:z

01

81

la

Bo

la

Bo

19

110

19

110

GND

llE

GND

l:IE

PLUS20R6 lo CLKNCVeeln 87

PLUS20R4 lo ClKNCVeeln 87

la

SYMBOL I 0
a
B CLK OE
Vee GND NC

DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock Input Output Enable
Supply Voltage Ground No Connection

02 17
18
la lg GNDNC OE 110 87

SYMBOL I 0
a
B CLK OE
Vee GND NC

DESCRIPTION Dedicated Input Dedlcated corrl>lnatorial Output Registered output Bld/rec:t/onal (inpuVoutput) Clock Input Output Enable
Supply Voltage
Ground No Connecthn

September 10, 1993

89

Philips Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4
LOGIC DIAGRAM

Product specification
PLUS20R8D/-7 SERIES
PLUS20L8

'\----l"»-----+---l20 85

I

19 84

"':..aw..I..:!..

0

::>

0
a0 :

18 83

Q.

">------r:»-----o---11s 01
~---l''>o-------l1s 0o
lg 110
0. ·3 4 ·· 7 8. ·11 12· ·15 16· ·18 20· ·23 24· ·27 28· ·31 32· ·35 36· ·38 INPUTS (Q-.39)
NOTES: 1. /\~I unprograrnmed or virgin ~AND" gate locations are pulled to logic "0". 2. ~~tr Programmable connections.

September 10, 1993

90

Philips Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4
LOGIC DIAGRAM

Product specification
PLUS20R8D/-7 SERIES
PLUS20R8

0 .. ·3 4 ·· 7 8. ·11 12· ·15 16· ·19 20· ·23 24· ·27 aJ· ·31 32· ·35 36· ·39 INPUTS (0-39)

NOTES:

t t 1. -~-!l unprogrammed or virgin "AND'' gate locations are pulled to logic "0",

2.

Programmable connections.

September 10, 1993

91

Philipi; Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4

Product specification
PLUS20R8D/-7 SERIES

LOGIC DIAGRAM
0 ·· 3 4 ·· 7 8. ·11 12· ·15 11· ·11 211· ·211 24· ·'II 28· ·31 32· ·35 31· ·31

PLUS20R6

0. ·3 4 ·· 7 8. ·11 12· ·15 16.. 19 20· ·23 24· ·27 · · ·31 32· ·35 36· ·31 INPUTS (D-49)
NOTES:
1. All unprogrammed or virgin "AND" ga18 loca11ons are pulled to logic ·o-.
;!. ~D) Programnabte connections.

September 10, 1993

92

Philips Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4
LOGIC DIAGRAM

Product specification
PLUS20R8D/-7 SERIES
PLUS20R4

0··3 4··7 8··11 12··15 16··19 20··23 24··27 28··31 32··35 36··39 OE
INPUTS (G-39)

NOTES:

. N! ~:

t~:{

unprogrammed or virgin "AND" Programmable connections.

gate

locations

are

pulled

to

logic

"O'' ·

September 10, 1993

93

Philips Semiconci.lctors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4

Product specification
PLUS20R8D/-7 SERIES

FUNC"TIONAL DESCRIPTIONS
The PLUS20XX series· utilizes the familiar sum-of-products implementation consisting of a programmable AND array and a fixed OR array. These devices are capable of replacing an equivalent of four or more SSl/MSI. integrated circuits to reduce package count and board area occupancy, consequently improving reliability and design cycle over Standard Cell or gate array options. By programming the security fuse, proprietary designs can be protected from duplication.
Tile PLUS20XX series consists of four PAL-type devices. Depending on the particular device type, there are a variable number of combinatorial and registered outputs available to the designer. The PLUS20l.8 is a combinatorial part with 8 user configurable outputs (6 bidirectional), while the other three devices, PLUS20R8, PLUS20R6, PLUS20R4, have respectively 8, 6, and 4 output registers.
3-State Outputs
The PLUS20XX series devices also feature 3-State output buffers on each output pin which can be programmed for individual control of all outputs. The registered outputs (On) are controlled by an external input (/OE), and the combinatorial outputs (On, Bn) use a product term to control the enable function.

Programmable Bidlrectlonal Pins
The PLUS20XX products feature variable Input/Output ratios. In addition to 12 dedicated inputs, each combinatorial output pin of the registered devices can be individually programmed as an input or output. The PLUS20l.8 provides 14 dedicated inputs and 6 Bidirectional 1/0 lines that can be individually configured as inputs or outputs.
Output Registers
The PLUS20RB has 8 output registers, the 20R6 has 6, and the 20R4 has 4. Each output register is a D-type flip-flop which is loaded on the Low-to-High transition of the clock input. These output registers are capable of feeding the outputs of the registers back into the array to facilitate design of s,ynchronous state machines.
Power-up Reset
By resetting all flip-flops to a logic Low, as the power is turned on, the PLUS20R8, RS, R4 enhance state machine design and initialization capability.
Software Suppon
Like other Prc)grammable Logic Devices from Philips Semiconductors, the PLUS20XX

series are supported by SLICE, the PC-based software development tool from Philips Semiconductors. The PLUS20XX family of devices are also supported by standard CAD tools for PAL devices, including ABEL and CUPL.
SLICE is available free of charge to qualified users.
Logic Programming
The PLUS20XX series is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL1" CUPLTM and PALASM® 90 design software packages also support the PLUS20XX architecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PROGRAMMING/SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/ Software Support) of the PLD data handbook for additional information.

AND ARRAY - (I, B)

4 " ~B

--

1,B

I STATE INACTIVE1· 2

P,D
I I cc:,DE

4 " ~B i.i

I STATE l,B

P,D
I I cc:E

4 " l,B

__

~B

I STATE i,i

.P,D
l~Ei

4 " ~B i,i

I STATE DOll'TCARE

P,D
IC~DE I

VIRGIN STATE
A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at "H" polarity.
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.

ABEL Is a tralemark of Data 1/0 Corp. CUPL le a trademark al Logical Devices, Inc. PALASM la a registered trademark ol AMO Corp.

September 10, 1993

94

Philips Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4

Product specification
PLUS20R80/-7 SERIES

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee

Supply voltage

-0.5

+7

Voc,

V1N

Input voltage

-1.2

+8.0

Voc,

VouT

Output voltage

-0.5

Vee +0.5V

Voc,

l1N

Input currents

-30

+30

mA

louT

Output currents

+100

mA

Tstg

Storage temperature range

-65

+150

oc

NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not
implied.

THERMAL RATINGS

TEMPERATURE

Maximum junction

150°C

Maximum ambient

75°C

Allowable thermal rise ambient to junction

75°C

OPERATING RANGES

SYMBOL Vee Tamb

PARAMETER Supply voltage Operating free-air temperature

RATINGS

MIN

MAX

+4.75

+5.25

0

+75

UNIT
Voc,
oc

September 10, 1993

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Philips Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4

Product specification
PLUS20R8D/-7 SERIES

DC ELECTRICAL CHARACTERISTICS 0°C s;Tamb s; +75°C, 4.75s;Vee s;5.25V

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP1

MAX

UNIT

Input voltage2

V1L

Low

V1H

High

Vic

Clamp

Output voltage

Vee=MIN

0.8

v

: ~

Vee= MAX

2.0

v

Vee= MIN, l1N = -18mA

--0.8

-1.5

v

Vol

Low

VoH

High

Input current

Vee= MIN, V1N = V1H or VIL

loL=24mA

loH=-3.2mA

2.4

0.5

v

v

l1L

Low3

l1H

High3

11

Maximum input current

Output current

Vee= MAX V1N =0.40V V1N =2.7V V1N =Vee= VccMAX

-250

µA

25

µA

100

µA

lozH

Output leakage

lozL

Output leakage

los

Short circuit 4· 5

Vee= MAX

Vour= 2.7V

100

µA

Vour=0.4V

-100

µA

Vour =OV

-30

-90

mA

Ice

Vcc supply current

Capacltance6

Vee=MAX

150

210

mA

C1N

Input

Vee =5V

Vour= 2.0V

8

pF

Ce

l/O(B)

Vour = 2V, f = 1MHz

8

pF

NOTES:
1. All typical values are at Vee= 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal.
3. Leakage current for bidirectional pins is the worst case of 11Land lozL or l1H and lozH· 4. Test one at a time.
5. Duration of short circuit should not exceed 1 second. 6. These parameters are not 100% tested but periodically sampled.

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96

Philips Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4

Product specification
PLUS20R8D/-7 SERIES

AC ELECTRICAL CHARACTERISTICS
R1 =2000, R2 = 3900, 0°c sTambs +75°C, 4.75 s VccS 5.25V

LIMITS

SYMBOL

PARAMETER

FROM

TO

-7

D

UNIT

MIN1 TYP MAX MIN1 MAX

Pulse Width

lcKH

Clock High

lcKL

Clock Low

lcKP

Period

Setup & Hold time

CK+ CKCK+

CK-

5

CK+

5

CK+

10

7

ns

7

ns

14

ns

!1s

Input

Input or feedback

CK+

7

9

ns

l1H

Input

CK+

Input or feedback

0

0

ns

Propagation delay

lcKO

Clock

CK±

lcKF

Clock3

CK±

tpo

Output (20LB, R6, R4)2

I, B

0±

3

0

Output

3

6.5

3

7.5

ns

3

6.5

ns

7.5

3

10

ns

loE1

Output enable4

loE2

Output enable4·5

OE

Output enable

3

I

Output enable

3

B

3

10

ns

10

3

10

ns

loo1

Output disable4

OE

Output disable

3

B

3

10

ns

lo02

Output disable4.5

lsKW

Output

tppR

Power-Up Reset

Frequency (20R8, R6, R4)

I
a
Vee+

Output disable

3

a

O+

10

3

10

ns

1

1

ns

10

10

ns

No feedback 1/ (lcKL + lcKH)6

100

71.4

MHz

IMAX

Internal feedback 1/ (t1s + lcKF)6

90

64.5

MHz

. .. External feedback 1/ (tis + lcKo)6

74

· For def1nit1ons of the terms, please refer to the Timing/Frequency Definitions tables.

NOTES:

60.6

MHz

1. CL= OpF while measuring minimum output delays.
2. tp0 test conditions: CL= 50pF (with jig and scope capacitance), V1H= 3V, V1L = OV, VoH =Vol= 1.5V. 3. lcKF was calculated from measured Internal IMAX· 4. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL_ 5pF. High-to-High impedance tests are made to an output
voltage of Vr = (VoH -0.5V) with S 1open, and Low-to-High impedance tests are made to the Vr = (Vol+ 0.5V) level with S1closed. 5. Same function as taE1and tao1. with the difference of using product term control.
6. Not 100% tested, but calculated at initial characterization and at any time a modification in design takes place which may affect the frequency.

September 10, 1993

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Philips Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4

Product specification
PLUS20R8D/-7 SERIES

OUTPUT REGISTER PRELOAD

The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below.

Step 1. With Vee at SV and Pin 1 at V1L, raise Pin 13 to ViHH·

Step 2. Apply either V1L or V1H to the output corresponding to the register to be preloaded.

Step 3. Pulse Pin 1, clocking in preload data.

I ~

Step 4. Remove output voltage, then lower Pin 13 to VIL· Preload can be verified by observing the voltage level at the output pin.

PIN1~,..:---------------.~------ V1HH

I I td I

PIN 1 CLOCK

I I

I I I ----..

REGISTERED 110

lsu

Id

I

ViL

tw

l

I

- - - - 1 - 1 - - - - - - V1H

I I .____...1.__-+I------ V1L

I I

I

I Id

I I

-t- v 1H I ",,,...,,.---- VoH

INPUT

- - - - - - - - - - - - V1L

VoL

NOTE:

td"" tsu"' tw = lOOns to 1000ns.
V1HH = 10.25Vlo 10.75V. Pin and number reference for DIP package

TEST LOAD CIRCUIT

L > Vee

'·y~ lo
I I I I INPUTS I
o--1- In

Bol<Jo

BnlOn

OUT

Clo

On

NOTE:

CLK

OE

GND

C1 and C2 are to bypass Vee to GND.

=

R1

R2

CL

=

September 10, 1993

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Philips Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4

Product specification
PLUS20R8D/-7 SERIES

OUTPUT REGISTER SKEW

CLK__ ,_ __/r-------------- 3V

------------------~

3V

(REGISTERED OUTP'*

l1.5V

~~~~~~~~-

ov

On+t (REGISTERED OUTPUT)

~~KW
UV

3V

ov

CLOCK TO FEEDBACK PATH

tcKF-------..1

September 10. 1993

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Philips Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4

Product specification
PLUS20R8D/-7 SERIES

TIMING DIAGRAMS1, 2
l,B (INPUTS)
CLK
Q (REGISTERED OUTPUTS)
~~"......~~"'! ..·""'>I

Flip·Flop Outputs
1--------------------------------------------+3Y
(INPui:i·_.s_Y__________________________________________ DY

----·po·----~

0,B (COMBINATORIAL
OUTPUTS)

~

f, (ourJu;__________

0-Y----------- '<>E2

~ too2

~--------------- +3v

ENABLE)________ _

· _

DY

Gate Outputs

.4..-SY------------------------------------------Yee Vee _
----------------------DY
.... tpp
Q"'"-~~~~~~-.; ...- - - - - - - - - - - -. . . .-
(REGISTERED OUTPUTS) ........_.._...-.,,,

CLK
Power-Up Reset NOTES: 1. Input pulse amplitude is OV to 3V. 2. Input rise and fall times are 2.5ns.

- - - - - - - - +3Y

TIMING DEFINITIONS

SYMBOL PARAMETER

lcKH lcKL lcKP
tis

Width of input clock pulse.
Interval between clock pulses.
Clock period.
Required delay between beginning of valid input and positive transition of clock.

Required delay between

l1H

positive transition of clock and

end of valid input data.

Delay between positive

transition of clock and when

lcKF

internal 0 output of flip-flop

becomes valid.

lcKO

Delay between positive transition of clock and when outputs become valid (with OE Low).

Delay between beginning of

loe1

Output Enable Low and when

outputs become valid.

Delay between beginning of

lo01

Output Enable High and when

outputs are in the Off-State.

Delay between predefined

Output Enable High, and

loe2

when combinational outputs

become valid.

Delay between predefined

Output Enable Low and when

loo2

combinational outputs are in

the Off-State.

Delay between Vee (after

lppR

power-on) and when flip-flop outputs become preset at "1"

(internal Q outputs at "O").

Propagation delay between

!po

combinational inputs and

outputs.

FREQUENCY DEFINITIONS

IMAX

No feedback: Determined by the minimum clock period, 1/(lcKL + leKH)· Internal feedback: Determined by the internal delay from flip-flop outputs through the internal feedback and array to the flip-flop inputs, 1/(t1s + lcKF). External feedback: Determined by clock-to-output delay and input setup time,
1/(t1s + lcKo).

September 10, 1993

100

Philips Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4
SNAP RESOURCE SUMMARY DESIGNATIONS

ProdUct specification
PLUS20R8D/-7 SERIES

PROGRAMMABLE AND ARRAY

00,07

PLUS20L8

e1-B6

PROGRAMMABLE AND ARRAY

September 10, 1993

07
PLUS20R8
101

Philips Semiconductors Programmable Logic Devices
PAL devices 20L8,20R8,20R6,20R4

Product specification
PLUS20R8D/-7 SERIES

SNAP RESOURCE SUMMARY DESIGNATIONS (Continued)
I0-111
1~
PROGRAMMABLE AND ARRAY

BO,B7

PLUS20R6

01-06

PROGRAMMABLE AND ARRAY

BO, B1, B6, B7
September 10, 1993

PLUS20R4 102

02-05

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10-10

FEATURES
· Advanced CMOS EE PROM technology
· Ultra high performance - 10ns, (tpo) commercial version - IMAX as fast as 83.3MHz
· Available in Dual In-Line, Small Outline Large, and Plastic Leaded Chip Carrier packages
· Low power consumption - 110mA + 0.5mA/MHz max
· EE reprogrammability - Low-risk reprogrammable inventory - Superior programming and functional yield - 100% testable - Erases and programs in seconds - 100 guaranteed erase cycles
· Development and programming support - Third-party software and program mers - SLICE development software
· Architectural flexibility - 132 product term x 44 input AND array - Up to 22 inputs and 10 outputs - Variable product term distribution (8 to 16 per output) for greater logic flexibility - Independently programmable
4-configuration )10 macrocells
- Synchronous p\eset, asynchronous clear - Independently programmable output
enables
· Application versatility - Pin-for-pin and JEDEC-file compatible with the bipolar AmPAL22V10, CMOS PALC22V10 and PEEL22CV10A

DESCRIPTION
The Philips Semiconductors PL22V10-10 is a CMOS programmable electrically erasable logic device that provides a high-performance, low-power, reprogrammable, and architecturally enhanced alternative to early generation programmable logic devices (PLDs). Designed in advanced CMOS EEPROM technology, the PL22V1 Orivals speed parameters of comparable bipolar PLDs while providing a dramatic improvement in active power consumption. The EE reprogrammability of the PL22V10 allows cost effective plastic packaging, low risk inventory, reduced development and retrofit costs, and enhanced testability to ensure 100% field programmability and function. The PL22V1 O's flexible architecture offers complete function and JEDEC-lile compatibility with the bipolar AmPAL22V10 and the CMOS PALC22V10. Applications for the PL22V10 include: replacement of random SSl/MSI logic circuitry and user customized sequential and combinatorial functions such as counters, shift registers, state machines, address decoders, multiplexers, etc. Development and programming support for the PL22V10 is provided by Philips Semiconductors and third-party manufacturers.

PIN LABEL DESCRIPTIONS

11-111

Dedicated Input

NC

Not Connected

FO-F9

Macro Cell Input/Output

CLK/10

Clock Input/Dedicated Input

Vee

Supply Voltage

GND

Ground

PIN CONFIGURATIONS

D and N Packages

Vee
F9

FB

F7

F6

FS

F4

F3

F2

F1

FO

GND

111

N,,. Plastic Dual ln·Line Package (300mll-wlde) D .. Plastic Small Outline Large (300mil-wide)
Package
A Package

A = Plastic Leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION 24-Pin (300mil-wide) Plastic DIP (Dual-In-Line Package) 28-Pin (300mil-wide) PLCC (Plastic Leaded Chip Carrier Package) 24-Pin (300mil-wide) Plastic SOL (Small Outline Large) Package

ORDER CODE PL22V10--10N PL22V10--1 OA PL22V10--10D

DRAWING NUMBER 0410D 0401F 0173D

October 22, 1993

103

853-1581 11164

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device
LOGIC DIAGRAM
0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43

Product specification
PL22V10-10
§]Vee

GND~

3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43

NOTE: ·i~~:;:~Ji Programmable conneciion.

October 22, 1993

104

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device
CLKllO
PROGRAMMABLE AND ARRAY (44x132)

Product specification
PL22V10-10
11-111

Figure 1. Functional Diagram

FUNCTION DESCRIPTION
The PL22V10 implements logic functions as sum-of-products expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of 1/0 macrocells further increase logic flexibility.
ARCHITECTURE OVERVIEW
The PL22V10 architecture is illustrated in the Figure 1. Twelve dedicated inputs and 10 I/Os provide up to 22 inputs and 1Ooutputs for creation of logic functions. At the core of the device is a programmable electrically-erasable AND array which drives a fixed OR array. With this structure, the PL22V10 can implement up to 10 sum-of-products logic expressions.
Associated with each of the 10 OR functions is an 1/0 macro cell which can be independently programmed to one of 4 different configurations. The programmable macro cells allow each 1/0 to create sequential or combinatorial logic functions with either Active-High or Active-Low polarity.

AND/OR LOGIC ARRAY
The programmable AND array of the PL22V10 (shown in the Logic Diagram) is formed by input lines intersecting product terms. The input lines and product terms are used as follows:
44 input lines:
24 input lines carry the True and Complement of the signals applied to the 12 input pins
20 additional lines carry the True and Complement values of feedback or input signals from the 1O I/Os
132 product terms:
120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16) used to form logical sums
10 output enable terms (one for each 1/0)
1 global synchronous preset term
1 global asynchronous clear term
At each input-line/product-term intersection there is an EEPROM memory cell which determines whether or not there is a logical connection at that intersection. Each product term is essentially a 44-input AND gate. A

product term which is connected to both the True and Complement of an input signal will always be FALSE, and thus will not effect the OR function that it drives. When all the connections on a product term are opened, a Don't Care state exists and that term will always be TRUE.
When programming the PL22V10, the device programmer first performs a bulk erase to instantly remove the previous pattern. The erase cycle opens every logical connection in the array. The device is then configured to perform the user-defined function by programming selected connections in the AND array. (Note that EE PROM device programmers automatically program the connections on unused product terms so that they will have no effect on the output function.)
VARIABLE PRODUCT TERM DISTRIBUTION
The PL22V10 provides 120 product terms to drive the 10 OR functions. These product terms are distributed among the outputs in groups of 8, 10, 12, 14, and 16 to form logical sums (see Logic Diagram). This distribution allows optimum use of device resources.

October 22, 1993

105

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10~10

s,

So

OUTPUT CONFIGURATION

0

0

Registered/Active-LOW

0

1

Registered/Active-HIGH

I,

1

0

Combinatorial/Active-LOW

CLK

1

1

Combinatorial/Active-HIGH

0 = Unprogrammed fuse
1 = Programmed fuse

Figure 2. Output Macro Cell Logic Diagram

a. Registered/Active-LOW

c. Combinatorial/Active-LOW

b. Registered/Active-HIGH

Flgure3.

d. Combinatorial/Active-HIGH

October 22, 1993

106

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10-10

PROGRAMMABLE 1/0 MACROCELL
The output macrocell provides complete control over the architecture of each output. The ability to configure each output independently permits users to tailor the configuration of the PL22V10 to the precise requirements of their designs.
MACROCELL ARCHITECTURE
Each 1/0 macrocell, as shown in Figure 2, consists of a D-type flip-flop and two signal-select multiplexers. The configuration of each macrocell of the PL22V1 O is determined by the two EEPROM bits controlling these multiplexers. These bits determine output polarity, and output type (registered or non-registered). Equivalent circuits for the macrocell configurations are illustrated in Figure 3.
OUTPUT TYPE
The signal from the OR array can be fed directly to the output pin (combinatorial function) or latched in the D-type flip-flop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register will be set HIGH at the next rising edge of the clock input. Satisfying the asynchronous clear term will set Q LOW, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset.
PROGRAM/ERASE CYCLES
The PL22V10 is 100% testable, erases/programs in seconds, and has 100 guaranteed erase cycles.

OUTPUT ENABLE
The output of each 1/0 macrocell can be enabled or disabled under the control of its associated programmable output enable product term. When the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the 1/0 pin. Otherwise, the output buffer is driven into the high-impedance state.
Under the control of the output enable term, the 1/0 pin can function as a dedicated input, a dedicated output, or a bi-directional 1/0. Opening every connection on the output enable term will permanently enable the output buffer and yield a dedicated output. Conversely, if every connection is intact, the enable term will always be logically FALSE and the 1/0 will function as a dedicated input.
REGISTER FEEDBACK SELECT When the 1/0 macrocell is configured to
implement a registered function (S1 =0) (Figures 3.a or 3.b), the feedback signal to
the AND array is taken from the 0 output.
Bl-DIRECTIONAL 1/0 SELECT
When configuring an 1/0 macrocell to implement a combinatorial function (S1 =1) (Figures 3.c or 3.d), the feedback signal is taken from the 1/0 pin. In this case, the pin can be used as a dedicated input, a dedicated output, or a bi-directional 1/0.
POWER-ON RESET
To ease system initialization, all flip-flops will power-up to a reset condition and the Q output will be low. The actual output of the PL22V10 will depend on the programmed output polarity. The Vee rise must be monotonic and the reset delay time is 5µs maximum.

DESIGN SECURITY
The PL22V10 provides a special EEPROM security bit that prevents unauthorized reading or copying of designs programmed into the device. The security bit is set by the PLD programmer, either at the conclusion of the programming cycle or as a separate step, after the device has been programmed. Once the security bit is set it is impossible to verify (read) or program the PL22V1 Ountil the entire device has first been erased with the bulk-erase function.
PROGRAM AND ERASE
The PL22V10 can be programmed on standard logic programmers. If a device needs to be reprogrammed, simply place back into the programmer, at which point it will be automatically erased, then repatterned.
Approved programmers are listed in the Philips Semiconductors Programmer Reference Guide.
SOFTWARE SUPPORT
The PL22V10 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors' SNAP design software package. ABELTM, CUPL'", and PALASM® 90 design software packages also support the PL22V10 architecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PL22V10 logic designs can also be generated using the prograr table entry format. This program table entry format is supported by SNAP only.

OUTPUT POLARITY
Each macrocell can be configured to implement Active-High or Active-Low logic. Programmable polarity eliminates the need for external inverters.

ABEL is a trademark of Data l/O Corp. CUPL is a trademark of Logical Devices, Inc. PALASM is a registered trademark of AMO Corp.
October 22, 1993

107

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10-10

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL Vee

PARAMETER Supply voltage

CONDITIONS Relative to GND

MIN

MAX

UNIT

--0.5

+7.0

v

VIN· VouT Voltage applied to any pin3

Relative to GND2

-1.2

Vee +0.5

Voe

!''

louT Tsrg TLT

Output current Storage temperature range Lead temperature

Per pin (loL. loHl Soldering 10 seconds

±25

mA

-65

+125

oc

+300

oc

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these
or any other condition above those indicated in the operational and programming specification of the device is not implied. 2. Minimum DC input is --0.5V, however inputs may undershoot to -2.0V for periods less than 20ns. 3. V1N and VouT are not specified for program/Verify operation.

OPERATING RANGES

SYMBOL

PARAMETER

CONDITIONS

Vee

Supply voltage

Commercial1

Industrial

Tamb

Ambient temperature

Commercial1

Industrial

tR

Clock Rise Time

See note 2

If

Clock Fall Time

See note 2

tRvee

Vee Rise Time

See note 2

NOTES.

1. Voltage applied to input or output must not exceed Vee +0.3V. 2. Test points for Clock and Vee in tR. tF. lcL. lcH. and tRESET are referenced at 10% and 90% levels.

RATINGS

MIN

MAX

+4.75

+5.25

+4.5

+5.5

0

+70

-40

+85

250

250

250

UNIT Voe Voe
oc oc
ns ns ms

October 22, 1993

108

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10-10

DC ELECTRICAL CHARACTERISTICS Commercial= O"C STantiS+75°C, 4.75V SVa; S5.25V

SYMBOL

PARAMETER

CONDITIONS

LIMITS

MIN

fYp4

1 MAX

UNIT

Input voltage

V1L

Low

V1H

High

--0.3

0.8

v

2.0

Vee+0.3

v

Output voltage

Va.

Low-TTL

Va.c

Low-CMOS

VoH

High-TTL

VoHC

High-CMOS

Input current

Vee = MIN, IOL = 16mA Va; s MIN, la.= 10µA Vee= MIN, IOH = -4.0mA Va;= MIN, loH = -10µA

2.4 Vcc-0.1

0.5

v

0.1

v

v

v

l1L/llH

Input leakage current

Vee = MAX, GND S V1N S Vee

1

±10

µA

Output current

loz

Output leakage

lsc5

Short circuit

1/0 = Hi-Z, GND SVo SVcc

2

Vee= sv. Vour = o.sv1

-30

±10

µA

-130

mA

Ice

Vee active curren~ CMOS (commercial)

V1N = Va; or GND2. 3

80+ O.SmA/MHz

110+ O.SmAIMHz

mA

Vee active current, CMOS (industrial)

V1N = Vee or GND2·3

90+ O.SmAIMHz

120+ O.SmAIMHz

mA

Vee active current, TTL (commercial)

V1N = V1L or V1H2. 3

90+ O.SmAIMHz

120+ O.SmAIMHz

mA

Vcc active current, TTL (industrial)

V1N = V1L or V1H2' 3

100+ O.SmAIMHz

130+ O.SmAIMHz

mA

NOTES:
1. No more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. 2. 1/0 pins open (no load). 3. Ice for a typical application: This parameter is tested with the device programmed as a 10-bit Counter. 4. Typical values are at Vee= SV. Typical values are guaranteed by design. 5. Room temperature only.

October 22, 1993

109

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10-10

AC ELECTRICAL CHARACTERISTICS Commercial= 0°C s; Tamb s; +75°C, 4.75V s; Vee s; 5.25V1·2

SYMBOL !po

PARAMETER lnput3 to non-registered output

TEST

PL22V111-10

CONDITIONS

MIN

MAX

UNIT

50pF

10

ns

1' 1

tEA

lnput3 to Output Enable4

50pF

10

ns

tER

lnput3 to Output Disable4

SpF

10

ns

lco

Clock to output

50pF

8

ns

Clock to combinatorial output delay via internal registered feed-

lc02

back

50pF

14

ns

Is

lnput3 or feedback setup to clock

50pF

7

ns

lsF

Internal feedbacks

50pF

5

ns

IH

lnput3 hold after clock

50pF

0

ns

tWL, !wH

Clock width - clock low time, clock high times

SOpF

6

ns

leP

MIN clock period External (Is + Ice)

SOpF

15

ns

fMAX1

MAX operating frequency; Internal feedbacks

(iSF:lco)

SOpF

76.9

MHz

fMAX2

MAX operating frequency; External (1ftcp)

SOpF

66.6

MHz

fMAX3

MAX clock frequency; No feedbacks

(tWL:twH)

50pF

83.3

MHz

tARW

Asynchronous Reset pulse width

tAR

lnput3 to Asynchronous Reset

tARR

Asynchronous Reset recovery time

tsPR

Synchronous Preset recovery time

tRESET

Power-on reset time for registers in clear state5

Capacitance&

50pF 50pF 50pF SOpF SOpF

10

ns

12

ns

8

ns

10

ns

5

µs

C1N

Input Capacitance7

Tarrb = 25°C, Vee =5.0V

6

pF

CouT

Output Capacitance7

@f=1MHz

12

pF

NOTES:
1. Test conditions assume: signal transition times of 2.5ns or less from the 10% and 90% points, timing reference levels of 1.5V (unless otherwise specified).
2. Device test loads are specified at the end of this section. 3. "Input" refers to an Input pin signal.
4. loE is measured from ihputtransition to VREF ± 0.1V, too is measured from input transition to VoH -0.1V or Vol+ 0.1 V. 5. Test points for Clock and Vee in tR. IF, lcL. tcH. and !RESET are referenced at 10% and 90% levels.
6. Parameters are not 100% tested. Specifications are based on initial characterization and are tested after any design or process modification which may affect operational frequency.
7. Capacitances are tested on a sample basis.

October 22, 1993

110

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

TEST LOAD CIRCUIT

C > Vee

lo

Fo

INPUTS
NOTES:
C1 and C2 are to bypass Vee to GNO.
R1·235", R2 · 159'1. CL· SOpF.
THEVENIN EQUIVALENT

OUT

In

Fn

CK GND OE

-=-

VOLTAGE WAVEFORM

2.5ns

2.5ns

MEASUREMENTS: AU circuit delays are measured at the +1.5V level of Inputs and outputs, unless otherwise spec:Hied.
Input Pulses

Product specification
PL22V10-10

October 22, 1993

111

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10-10

SWITCHING WAVEFORMS

'_~=tp\~ '.: INPUT OR

)!(VT

FEEDBACK _ _ _ _ _

,..V_T_ __

INPUT OR FEEDBACK

ltJ

COMBINATORIAL OUTPUT

CLOCK

Combinatorial Output
CLK Q
REGISTER
a
ISF CLK Q
REGISTER
tco) fMAX· ; Internal Feedback ( lsF :

REGISTERED OUTPUT

Registered Output
CLK Q
REGISTER
a

LOGIC

OUTPUT

Clock to Combinatorial Output (tc02)

CLOCK

Clock Width

INPUT

OUTPUT

Input to Output Disable/Enable

INPUT ASSERTING ASYNCHRONOUS
RESET

REGISTERED OUTPUT
CLOCK

IARR

Asynchronous Reset
NOTES: 1. VT= 1.5V. 2. Input pulse amplitude OV to 3.0V. 3. Input rise and fall times 2.5ns max.

October 22, 1993

INPUT ASSERTING SYNCH RO NOUS PRESET

CLOCK

---------'C-0~:.r REGISTERED OUTPUT

__ _

Synchronous Preset

112

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

l,Bi l,B l,Bil,B l,Bil,B "AND"ARRAY- (I,B)

1, B"

l, B"

1, B"

Product specification
PL22V10-10
1,B il,B 1, B"

,D
STATE INACTIVE 1
NOTE: 1. This is the initial state.

,D

STATE TRUE

'~'

I STATE

,D

,D STATE DON'T CARE

POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and

parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways Vee can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are:

1. The Vee rise must be monotonic.
2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met

SYMBOL
lpR
Is, lsF lwL

Power-up Reset Time Input or Feedback Setup lime Clock Width LOW

PARAMETER

LIMITS

l MIN

MAX

l 1

See AC Electrical

UNIT µs

Characteristics

POWER-4Vf~1~4------t-p-R-=:-j----------vcc
/ / I RAEGCISTTER~EDG~~------------~· ~ ~1
..: t - - - - CLOCK-------p~.,....1-

Power-Up Reset Waveform

October 22, 1993

113

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10-10

PRELOAD TEST CONDITION

SYMBOL lpe lpz
lpH
lpsu
lpLH VHH

PARAMETER
Valid data out
Output 3-State delay time after assertion of Preload (Pin2 = VHH)
Hold time of all preload inputs with respect to Clock rising edge
Setup time of all preload inputs with respect to Clock rising edge
Hold time for Preconditioning input
Preload enable voltage

PRELOAD WAVEFORM.

CLK PIN1

PIN2

ALL OTHER INPUTS VO PINS

CONDITIONS

-""
LIMITS
MIN TYP
100 100

MAX

15

100

50 14.50 14.75 15.0

UNIT ns ns
ns
ns
ns
v

V1H 3.aV
v1L av
VHH 14.75V
v1L av
V1H 3.aV
v1L av
, - - - - - - - - - - - V\H 3JN VALID DATA-OUT
" " - - - - - - - - - - v1L av

October 22, 1993

114

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

PROGRAM TABLE

LJL-COMBJJWORJAL

[

CONTROL WORD

Product specification
PL22V10-10
POLARITY [H -+ATIVEJ:llil! ...± l111.LOW
POLARITY
I III I

PIN 13 11 10 9 8 7 6 5 4 3 2 1 23 22 21 20 19 18 17 16 15 14

October 22, 1993

115

Philips Serniconductors Prograrnrnable Logic Devices
CMOS programmable electrically erasable logic device
PROGRAM TABLE (Continued)

Product specification
PL22V10-10

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

:-!

109

110

111

112

113

114

115

116

117

118

119

120

121 122 123

T
±

124

125

126 127 128

T
+

129

AR

SP

PIN 13 11 10 9 8 7 6 5 4 3 2 1 23 22 21 20 19 18 17 16 15 14

October 22, 1993

116

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device
SNAP RESOURCE SUMMARY DESIGNATIONS
OINV\O

Product specification
PL22V10-10
11-111 'NINV10

October 22, 1993

117

Phillps Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10-12/-15, PL22V10115

FEATURES
· Advanced CMOS EEPROM technology
· Ultra high performance - 12ns, and 1Sns (!po) commercial versions - 15ns (lp0 ) industrial version - IMAX as fast as 71.4MHz
· Available in Dual In-Line, Small Outiine Large, and Plastic Leaded Chip Carrier packages
· Low power consumption - 90mA + O.SmA/MHz max
· EE reprogrammability - Low-risk reprogrammable inventory - Superior programming and functional yield - 100% testable - Erases and programs in seconds - 100 guaranteed erase cycles
· Development and programming support - Third-party software and programmers - SLICE development software
· Architectural flexibility - 132 product term x 44 input AND array - Up to 22 inputs and 1Ooutputs - Variable product term distribution (B to 16 per output) for greater logic flexibility - Independently programmable 4-configuration 1/0 macrocells - Synchronous preset, asynchronous clear - Independently programmable output enables
· Application versatility - Pin-for-pin and JEDEC-file compatible with the bipolar AmPAL22V10, CMOS PALC22V10 and PEEL22CV1 OA

DESCRIPTION
The Philips Semiconductors PL22V10-12 and PL22V10-15 are CMOS programmable electrically erasable logic devices that provide a high-performance, low-power, reprogrammable, and architecturally enhanced alternative to early generation programmable logic devices (PLDs). Designed in advanced CMOS EEPROM technology, the PL22V10 rivals speed parameters of comparable bipolar PLDs while providing a dramatic improvement in active power consumption. The EE reprogrammability of the PL22V10 allows cost effective plastic packaging, low risk inventory, reduced development and retrofit costs, and enhanced testability to ensure 100% field programmability and function. The PL22V10's flexible architecture offers complete function and JEDEC-file compatibility with the bipolar AmPAL22V10 and the CMOS PALC22V10. Applications for the PL22V10 include: replacement of random SSl/MSI logic circuitry and user customized sequential and combinatorial functions such as counters, shift registers, state machines, address decoders, multiplexers, etc. Development and programming support for the PL22V10 is provided by Philips Semiconductors and third-party manufacturers.

PIN LABEL DESCRIPTIONS

11-111

Dedicated Input

NC

Not Connected

FO-F9

Macro Cell Input/Output

CLK/10

Clock Input/Dedicated Input

Vee

Supply Voltage

GND

Ground

PIN CONFIGURATIONS

D and N Packages

GND

Vee
F9 FS F7 F6 F5 F4 F3 F2 F1 FO 111

N .. Plastic Dual In-Line Package (300mH-wide) D · Plastic Small Outline Large (300mll-wide)
Package
A Package
CLK/ 12 11 I() NC Vee F9 FS

A · Plastic Leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION 24-Pin (300mil-wide) Plastic DIP (Dual-In-Line Package) 28-Pin (300mil-wide) PLCC (Plastic Leaded Chip Carrier Package)
24-Pin (300mil-wide) Plastic SOL (Small Outline Large) Package

ORDER CODE
PL22V1CH2N PL22V10-15N PL22V10115N (Industrial)
PL22V10-12A PL22V10-15A PL22V1011 SA (Industrial)
PL22V10--10D PL22V10--12D PL22V10--15D PL22V10115D (Industrial)

DRAWING NUMBER 0410D 0401F 0173D

October 22, 1993

118

853--1719 11164

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device
LOGIC DIAGRAM
3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43

Product specification
PL22V10-12/-15, PL22V10I15

GND~

3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43

NOTE:
Ko!@ Programmable connection.

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device
CLK!IO
PROGRAMMABLE AND ARRAY (44x132)

Product specification
PL22V10-12/-15, PL22V10I15
11-111
I,,

Figure 1. Functional Diagram

FUNCTION DESCRIPTION
The PL22V10 implements logic functions as sum-of-products expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of 1/0 macrocells further increase logic flexibility.
ARCHITECTURE OVERVIEW
The PL22V10 architecture is illustrated in the Figure 1. Twelve dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs for creation of logic functions. At the core of the device is a programmable electrically-erasable AND array which drives a fixed OR array. With this structure, the PL22V10 can implement up to 10 sum-of-products logic expressions.
Associated with each of the 1OOR functions is an 1/0 macro cell which can be independently programmed to one of 4 different configurations. The programmable macro cells allow each 1/0 to create sequential or combinatorial logic functions with either Active-High or Active-Low polarity.

AND/OR LOGIC ARRAY
The programmable AND array of the PL22V10 (shown in the Logic Diagram) is formed by input lines intersecting product terms. The input lines and product terms are used as follows:
44 input lines:
24 input lines carry the True and Complement of the signals applied to the 12 input pins
20 additional lines carry the True and Complement values of feedback or input signals from the 10 I/Os
132 product terms:
120 product terms (arranged in 2 groups of 8, 10, 12, 14, and16) used to form logical sums
10 output enable terms (one for each 1/0)
1 global synchronous preset term
1 global asynchronous clear term
At each input-line/product-term intersection there is an EEPROM memory cell which determines whether or not there is a logical connection at that intersection. Each product term is essentially a 44-input AND gate. A

product term which is connected to both the True and Complement of an input signal will always be FALSE, and thus will not effect the OR function that it drives. When all the connections on a product term are opened, a Don't Care state exists and that term will always be TRUE.
When programming the PL22V10, the device programmer first performs a bulk erase to instantly remove the previous pattern. The erase cycle opens every logical connection in the array. The device is then configured to perform the user-defined function by programming selected connections in the AND array. (Note that EEPROM device programmers automatically program the connections on unused product terms so that they will have no effect on the output function.)
VARIABLE PRODUCT TERM DISTRIBUTION
The PL22V10 provides 120 product terms to drive the 10 OR functions. These product terms are distributed among the outputs in groups of 8, 10, 12, 14, and 16 to form logical sums (see Logic Diagram). This distribution allows optimum use of device resources.

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V1Q.,12/-15, PL22V10115

AR
CLK SP

s,

So

OUTPUT CONFIGURATION

0

0

Registered/Active-LOW

0

1

Re.gistered/Activ&-H IGH

1

0

Combinatorial/Active-LOW

1

1

Combinatorial/Active-HIGH

0 = Unprogrammed fuse
1 = Programmed fuse

Figure 2. Output Macro Cell Logic Diagram
So=O
s,.o
AR

a. Registered/Active-LOW

c. Combinatorial/Active-LOW

b. Registered/Active-HIGH

Figure3.

d. Combinatorial/Active-HIGH

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10~ 12/-15, PL22V10I15

PROGRAMMABLE 1/0

OUTPUT ENABLE

DESIGN SECURITY

MACROCELL

The output of each 1/0 macrocell can be

The PL22V10 provides a special EEPROM

The output macrocell provides complete

enabled or disabled under the control of its · security bit that prevents unauthorized

control over the architecture of each output. associated programmable output enable

~eading or copying of designs programmed

The ability to configure each output

product term. When 'the logical conditions

into the device. The security bit is set by the

independently permits users to tailor the

programmed on the output enable term are PLD programmer, either at the conclusion of

I

configuration of the PL22V10 to the precise requirements of their designs.

satisfied, the output signal is propagated to the 1/0 pin. Otherwise, the output buffer is

the programming cycle or as a separate step, after the device has been programmed. Once

!''

driven into the high-impedance state.

the security bit is set it is impossible to verify

MACROCELL ARCHITECTURE Each 1/0 macrocell, as shown in Figure 2, consists of a D-type flip-flop and two signal-select multiplexers. The configuration of each macrocell of the PL22V10 is determined by the two EEPROM bits controlling these multiplexers. These bits determine output polarity, and output type (registered or non-registered). Equivalent

Under the control of the output enable term, the 1/0 pin can function as a dedicated input, a dedicated output, or a bi-directional 1/0. Opening every connection on the output enable term will permanenUy enable the output buffer and yield a dedicated output. Conversely, if every connection is intac~ the enable term will always be logically FALSE and the 1/0 will function as a dedicated input.

(read) or program the PL22V1 O until the entire device has first been erased with the bulk-erase function.
PROGRAM AND ERASE The PL22V10 can be programmed on standard logic programmers. If a device needs to be reprogrammed, simply place back into the programmer, at which point it

circuits for the macrocell configurations are illustrated in Figure 3.

REGISTER FEEDBACK SELECT

will be automatically erased, then repaiterned.

When the 1/0 macrocell is configured to

Approved programmers are listed in the

OUTPUT TYPE The signal from the OR array can be fed directly to the output pin (combinatorial

implement a registered function (S1 =0) (Figures 3.a or 3.b), the feedback signal to
the AND array is taken from the 0 output.

Philips Semiconductors Programmer Reference Guide.

function) or latched in the D-type flip-flop (registered function). The D-fype flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register will be set HIGH at the next rising edge of the clock input. Satisfying the asynchronous clear term will set Q LOW, regardless of the clock

Bl-DIRECTIONAL 1/0 SELECT When configuring an 1/0 macrocell to implement a combinatorial function (S1 =1) (Figures 3.c or 3.d), the feedback signal is taken from the 1/0 pin. In this case, the pin can be used as a dedicated input, a dedicated output, or a bi-directional 1/0.

SOFTWARE SUPPORT The PL22V10 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors' SNAP design software package. ABEL'"· CUPLTM, and PALASM® 90 design software packages also support the PL22V10 architecture.

state. If both terms are satisfied

All packages allow Boolean and state

simultaneously, the clear will override the preset.
PROGRAM/ERASE CYCLES The PL22V10 is 100% testable, erases/programs in seconds, and has 100 guaranteed erase cycles.

POWER-ON RESET To ease system initialization, all flip-flops will
a power-up to a reset condition and the
output will be low. The actual output of the PL22V10 will depend on the programmed output polarity. The Vee rise must be monotonic and the reset delay time is 5µs maximum.

equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PL22V1 Ologic designs can also be generated using the program table entry format. This program table entry format is supported by SNAP only.

OUTPUT POLARITY Each macrocell can be configured to implement Active-High or Active-Low logic. Programmable polarity eliminates the need for external inverters.

ABEL Is a trademark. of Data VO Corp. CUPL is a trademark of Logical Devices, Inc. PALASM Is a registered trademark of AMO Corp.
October 22, 1993

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Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10-12/-15, PL22V10I15

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL
Vee
v,N, VouT

PARAMETER Supply voltage Voltage applied to any pin3

CONDITIONS Relative to GND Relative to GND2

MIN

MAX

UNIT

-0.5

+7.0

v

-1.2

Vee+ 0.5

Voe

louT Tstg TLT

Output current Storage temperature range Lead temperature

Per pin (Im, loH) Soldering 10 seconds

±25

mA

-<55

+125

oc

+300

oc

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these
or any other condition above those indicated in the operational and programming specification of the device is not implied. 2. Minimum DC input is -0.5V, however inputs may undershoot to -2.0V for periods less than 20ns. 3. V1N and VouT are not specified for program/verify operation.

OPERATING RANGES

SYMBOL

PARAMETER

CONDITIONS

Vee

Supply voltage

Commercial1

Industrial

Tamb

Ambient temperature

Commercial1

Industrial

!R

Clock Rise Time

See note 2

tF

Clock Fall Time

See note 2

tRvee

Vee Rise Time

See note 2

NOTES: 1. Voltage applied to input or output must not exceed Vee +0.3V. 2. Test points for Clock and Vee in tR, IF, lcL, lcH. and !RESET are referenced at 10% and 90% levels.

RATINGS

MIN

MAX

+4.75

+5.25

+4.5

+5.5

0

+70

-40

+85

250

250

250

UNIT
Voe Voe
oc oc
ns ns ms

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10-12/-15, PL22V10115

DC ELECTRICAL CHARACTERISTICS
Commercial= 0°C 5 Tamb 5 +75°C, 4.75V 5 Vee 5 5.25V; Industrial= -40°C 5 Tamb 5 +85°C, 4.5V 5 Vee 5 5.SV

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP4

MAX

Input voltage

V1L

Low

V1H

High

Output voltage

--0.3 2.0

0.8 Vee+ 0.3

Vol

Low-TIL

Vee= MIN, Im= 16mA

0.5

VoLc

Low-CMOS

Vee =MIN, Im= 10µA

0.1

VoH

High-TIL

Vee =MIN, loH = -4.0mA

2.4

VoHc

High-CMOS

Vee= MIN, loH = -10µA

Vcc-0.1

Input current

l1L/l1H

Input leakage current

Vee= MAX, GND 5 V1N 5 Vee

1

±10

Output current

loz

Output leakage

lsc5

Short circuit

1/0 = Hi-Z, GND 5 Vo 5 Vee

Vee= 5V, VouT = o.sv1

--30

Ice

Vee active current, CMOS (commercial)

V1N = Vee or GND2· 3

2
70 + O.SmA/MHz

±10
-130
90 + O.SmAIMHz

Vee active current, CMOS (industrial)

V1N =Vee or GND2· 3

80+ O.SmA/MHz

100 + O.SmA/MHz

Vee active current, TIL (commercial)

V1N = V1L or V1H2' 3

80 + O.SmA/MHz

100 + 0.SmAIMHz

Vee active current, TIL (industrial)

V1N = V1L or V1H2' 3

90 + O.SmA/MHz

110 + O.SmAIMHz

NOTES: 1. No more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. 2. 1/0 pins open (no load). 3. Ice for a typical application: This parameter is tested with the device programmed as a 10-bit Counter. 4. Typical values are at Vcc = SV. Typical values are guaranteed by design. 5. Room temperature only.

UNIT
v. v
v v v v
µA
µA mA mA
mA
mA
mA

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10-12/-15, PL22V10I15

AC ELECTRICAL CHARACTERISTICS Commercial= 0°c s Tamb s +75°C, 4.75V s Vee s 5.25V1· 2; Industrial= -40°C s; Tamb s +85°C, 4.5V s Vee s; 5.5V

SYMBOL lpo lf:A Im lco lco2 Is lsF ii, lwL. lwH lcP
fMAX1

PARAMETER

lnput3 to non-registered output

lnput3 to Output Enable4

lnput3 to Output Disable4

Clock to output

Clock to combinatorial output delay via internal registered feedback

lnput3 or feedback setup to clock

Internal feedbacka

lnput3 hold after clock

Clock width - clock low time, clock high time5

MIN clock period External (ts+ lco)

MAX operating frequency; Internal feedbacka

( ~F~lco)

TEST CONDITIONS
50pF 50pF 5pF 50pF
50pF
50pF 50pF 50pF 50pF 50pF
50pF

PL22V10·12 MIN MAX
12 12 12 9
16
8 6 0 7 17

PL22V10·15 PL22V10115 MIN MAX
15 15 15 10
19
10 9 0 8 20

UNIT ns ns ns ns
ns
ns ns ns ns ns

66.7

52.6

MHz

fMAX2

MAX operating frequency; External (1/tep)

fMAX3

MAX clock frequency; No feedback6

(iWL ~lwH)

50pF

58.8

50.0

MHz

50pF

71.4

62.5

MHz

IARW

Asynchronous Reset pulse width

!AR

lnput3 to Asynchronous Reset

!ARR

Asynchronous Reset recovery time

50pF 50pF 50pF

12

15

ns

15

18

ns

10

10

ns

~PR

Synchronous Preset recovery time

!RESET

Power-on reset time for registers in clear states

Capacitance&

50pF 50pF

10

10

ns

5

5

µs

C1N

Input Capacitance7

Tamb = 25°C, Vee= 5.0V

6

6

pF

Cour

Output Capacitance7

@f= 1MHz

12

12

pF

NOTES:
1. Test conditions assume: signal transition times of 2.5ns or less from the 10% and 90% points, timing reference levels of 1.5V (unless otherwise specified).
2. Device test loads are specified at the end of this section. 3. "lnpur' refers to an Input pin signal.
4. loE is measured from input transition to VREF ±0.1V, too is measured from input transition to VoH -0.1V or Vol+ 0.1 V.
5. Test points for Clock and Vee in IA. If;. lcL. lcH. and !RESET are referenced at 10% and 90% levels. 6. Parameters are not 100% tested. Specifications are based on initial characterization and are tested after any design or process modification
which may affect operational frequency. 7. Capacitances are tested on a sample basis.

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

TEST LOAD CIRCUIT

L > Vee

~

Fo

INPUTS
NOTES:
C1 and C2 are to bypass Vee to GND.
R1·235n, R2 · 1590, CL= 50pF.
THEVENIN EQUIVALENT

OUT

In

Fn

CK GND OE

":"

VOLTAGE WAVEFORM

Product specification
PL22V10-12/-15, PL22V1 OI15

2.5ns

2.5ns

MEASUREMENTS: All circuit delays are measured at the +1.5V level of Inputs and outputs, unless otherwise specified.
Input Pulses

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10-12/-15, PL22V10115

SWITCHING WAVEFORMS
Combinatorial Output
CLK
a
REGISTER 0
tsF CLK
a
REGISTER
~ IMAX·; Internal Feedback ( lsF tco)

INPUT OR
- - - J FEEDBACK
CLOCK

REGISTERED OUTPUT

Registered Output
CLK
a
REGISTER 0

LOGIC

OUTPUT

Clock to Combinatorial Output (tco>l

CLOCK

Clock Width

INPUT

OUTPUT

Input to Output Disable/Enable

INPUT ASSERTING ASYNCHRONOUS
RESET
REGISTERED OUTPUT
CLOCK
Asynchronous Reset NOTES: 1. VT= 1.5V. 2. Input pulse amplitude OV to 3.0V. 3. Input rise and fall times 2.5ns max.
October 22, 1993

INPUT ASSERTING SYNCHRONOUS PRESET

CLOCK

----------------'C~O~~: REGISTERED OUTPUT

______

Synchronous Preset

127

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

l,Bi l,B l,Bil,B l,Bil,B "AND"ARRAY- (I,B)

1,1!

T,lJ

T,lJ

Product specification
PL22V10-12/-15, PL22V10I15
il,B
~B
T,lJ

,D
STATE INACTIVE 1
NOTE: 1. This is the initial state.

,D STATE TRUE

I STATE

,D

,D STATE DDN'TeARE

POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and

parameter table are shown below. Due to the synchronous operation of the power-up reset
and the wide range of ways Vee can rise to
its steady state, two conditions are required to ensure a valid power-up reset. These conditions are:

1. The Vee rise must be monotonic.
2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met.

SYMBOL
IPR
Is, lsF lwL

Power-up Reset Time Input or Feedback Setup Time Clock Width LOW

PARAMETER

LIMITS

I MIN

MAX

l 1

See AC Electrical

UNIT µs

Characteristics

~~~~~~~~~~~~~~~~~~~vee

POWER _ _____.4V'~....---tpR~

l RAECGTIISVTEE-LROEWD OUTPUT _

_..........

1::t....---- eLOeK----~-i..

Power-Up Reset Waveform

October 22, 1993

128

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device

Product specification
PL22V10-12/-15, PL22V1OI15

PRELOAD TEST CONDITION

SYMBOL tpE tpz
!pH
trsu
tpLH VHH

PARAMETER
Valid data out
Output 3-State delay time after assertion of Preload (Pin 2 = VHH)
Hold time of all preload inputs with respect to Clock rising edge
Setup time of all preload inputs with respect to Clock rising edge
Hold time for Preconditioning input
Preload enable voltage

PRELOAD WAVEFORM

CLK PIN 1

PIN2

CONDITIONS

LIMITS
MIN TYP MAX
100 100
15
100
50 14.50 14.75 15.0

UNIT ns ns
ns
ns
ns
v

V1H 3.0V VHH 14.75V

ALL OTHER INPUTS
l/OPINS

V1H 3.0V
, , - - - - - - - - - - - - V1H 3.0V
VALID DATA-OUT
' - - - - - - - - - - - - V1L OV

October 22, 1993

129

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable· logic device

PROGRAM TABLE

~-W-OiiD--~

Product specification
PL22V10-12/-15, PL22V10I15
:I II::I II::I

October 22, 1993

130

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device
PROGRAM TABLE (Continued)

Product specification
PL22V10-12/-15, PL22V10115

SP PIN 13 11 10 9 8 7 6 5 4 3 2 1 23 22 21 20 19 18 17 16 15 14

October 22, 1993

131

Philips Semiconductors Programmable Logic Devices
CMOS programmable electrically erasable logic device
SNAP RESOURCE SUMMARY DESIGNATIONS

Product specification
PL22V10-12/-15, PL22V10I15

October 22, 1993

132

Phillps Semiconductors Programmable Logic Devices
BiCMOS versatile PAL device

Prellmlnary specification
ABT22V10-7

DESCRIPTION The ABT22V1 Ois a versatile PAL1 device fabricated with the Philips BiCMOS process known as QUBiC. The QUBiC process produces a very high speed device (7.Sns worst case) which has excellent noise immunily. The ground bounce, with 9 outputs switching and the 10th held low is, typically, less than 0.8V.
The ABT22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-product equations. This device has a programmable AND array which drives a fixed OR array. The AND array is programmed to create custom product terms while the fixed OR array sums selected terms at the output.
The OR sum of the products feeds the "Output Macro Cell" (OMC) which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. In other words, the architecture provides maximum design flexibility by allowing the Output Macro Cell to be configured by the user.
The ABT22V1Ois designed so the outputs can never display a metastable state due to set up and hold time violations. If set up and hold times are violated, the outputs will not glitch or display a metastable state (the propagation delays may, however, be extended).
This device is pin and JEDEC file compatible with industry standard 22V10 and can be used in all standard applications where speed is to be maximized.
Order codes can be found in the Ordering Information table.
FEATURES
· Ultra fast 7.Sns tPD and 6ns lco
· Pin and JEDEC file compatible to industry standard 22V10

· 10 input/output macro cells for architectural flexibility
· Metastable immune flip-flops
· Low ground bounce (<0.8V typical)
· Varied product term distribution with up to 16 product terms per output for complex functions
· Programmable output polarity
· Power-up reset on all registers
· Synchronous Preset/Asynchronous Reset
· Programmable on standard PAL-type device programmers
· Design support provided using SNAP software development package and other CAD tools for PLDs
· Available in 300mil-wide 24-Pin Plastic Dual In-Line Package and 28-Pin Plastic Leaded Chip Carrier

APPLICATIONS · OMA control · State machine implementation · High speed graphics processing · Counters/shift registers · SSl/MSI random logic replacement · High speed memory decoder

PIN LABEL DESCRIPTIONS

11-111

Dedicated Input

NC

Not Connected

FO-F9

Macro Cell Input/Output

CLK/10

Clock Input/Dedicated Input

Vee

Supply Voltage

GND

Ground

PIN CONFIGURATIONS
NPackage
N · Plastic DIP (300ml~wlde)
A Package
A - Plastic Leaded Chip Carrier

ORDERING INFORMATION DESCRIPTION
24-Pin Plastic Dual-In-Line Package 300mil-wide 28-Pin Plastic Leaded Chip Carrier

ORDER CODE ABT22V10-7N ABT22V10-7A

DRAWING NUMBER 0410D 0401F

1. !M'AL is a registered tiademark of Advanced Miao Devices. Inc.

Philips Semiconductors Programmable Logic Devices
BiCMOS versatile PAL device
LOGIC DIAGRAM
3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43

Preliminary specification
ABT22V10-7
§]Vee

19

110
GND @}--~

3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43

NOTE' ~~~:;~~~ Programmable connection.

October 1993

134

Philips Semiconductors Programmable Logic Devices
BiCMOS versatile PAL device
CLK/10
programmable and array (441 132)

Preliminary specification
ABT22V10-7
11-111

Figure 1. Functional Diagram

FUNCTIONAL DESCRIPTION
The ABT22V 1O allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function.
Product terms with all fuses opened assume the logical HIGH state; product terms connected to both True and Complement of any single input assume the logical LOW state.
The ABT22V10 has 12 inputs and 10 110
Macro Cells (Figure 1). The Macro Cell allows one of four potential output configurations, registered output or combinatorial 1/0, Active-HIGH or Active-LOW (see Figure 7). The configuration choice is made according to the user's design specification and corresponding programming of the configuration bits S0 - S 1. Multiplexer controls are connected to ground (0) through a programmable fuse link, selecting the "O" path through the multiplexer. Programming the fuse disconnects the control line from GND and it floats to Vee (1), selecting the "1" path.
The device is produced with a fuse link at each input to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easily-implemented programming algorithm, these products can be rapidly

programmed to any customized pattern. Information on approved programmers can be found in the Programmer Reference Guide. Extra test fuses are pre-programmed during manufacturing to ensure extremely high field programming yields, and provide extra test paths to achieve excellent parametric correlation.
Metastable Immune Characteristics
Philips Semiconductors uses the term 'metstable immune' to describe the output characteristics of registered logic devices. This term means that the outputs will not gitch or display an output anomaly under any circumstances, including set up and hold time violations. This claim is easily verified by following 74F5074 Synchronizing Dual flip-flop example. The ABT22V10 device has been designed using the same metastable immune flip-flop.

Signal generator
Signal generator

Trigger
D\jital scope
Input

Figure 2. Test Set-up

By running two independent signal generators (see Figure 2) at nearly the same

frequency (in this case 1OMHz clock and 10.02MHz data) the device-under-test can be often be driven into a metastable state. If the Q output is then used to trigger a digital
scope set to infinite persistence, the 0 output
will build a waveform. An experiment was run by continuously operating the devices in the region where metastability will occur.
When the device-under-test is an 74F74 (which was not designed with metastable immune characteristics) the waveform will appear as in Figure [3].
Figure 3 shows clearly that the 0 output can
vary in time with respect to the Q trigger point. This also implies that the Q or 0 output waveshapes may be distorted. This can be verified on an analog scope with a charge plate CRT. Perhaps of even greater interest are the dots running along the 3.5V volt line in the upper right hand quadrant. These show
that the 0 output did not change state even
though the Q output glitched to at least 1.5 volts, the trigger point of the scope.
When the device-under-test is a metastable immune part, such as the 74F5074, the waveform will appear as in Figure 4. The 74F5074 output will not vary with respect to the Q trigger point even when the a part is driven into a metastable state. Any tendency towards internal metastability is resolved by Philips Semiconductors patented circuitry. If a metastable event occurs within the flop the

rirtnhor 1 QQ'=l

135

Philips Semiconductors Programmable Logic Devices
BiCMOS versatile PAL device

Preliminary specification
ABT22V10-7

COMPARISON OF METASTABLE IMMUNE AND NON-IMMUNE CHARACTERISTICS

....... ·u '·· ... Jr"!·:;.

IIII IIII

I I I It I I

r I I I I Ir I I I I I I I I

Time base= 2.00ns/div Trigger level= 1.5 Volts Trigger slope= positive_
Figure 3. 74F74 Q output triggered by Q output, Setup and Hold times violated

= = = Time base 2.00ns/div Trigger level 1.5 Volts Trigger slope positive
Figure 4. 74F5074 Q output triggered by Q output, Setup and Hold times violated

only outward manifestation of the event will be an increased clock-to-QR'.) propagation delay. This propagation delay is, of course, a Junction of the metastability characteristics of the part defined by ~ and To.
The metastability characteristics of the ABT22V10-7 and related part types represent state-of-the-art BiCMOS technology.
After determining the To and t of the flop, calculating the mean time between failures (MTBF) is simple. Suppose a designer wants to use the 74F5074 for synchronizing

asynchronous data that is arriving at 10MHz (as measured by a frequency counter), has a clock frequency of 50MHz, and has decided that he would like to sample the output of the 74F5074 10ns after the clock edge. He simply plugs his number into the equation below:
MTBF = eWn)/ T0fef1
In this formula, le is the frequency of the clock, f1is the average input event frequency, and t' is the time after the clock pulse that the

output is sampled (t' < h, h being the normal propagation delay). In this situation the 11will be twice the data frequency of (20 MHz) because input events consist of both of low and high transitions. Multiplying 11by le gives an answer of 1015 Hz2. From Figure 5 it is clear that the MTBF for the 74F5074 device is greater than 1010 seconds. Using the above formula the actual MTBF is 1.51 X 1010 seconds or about 480 years. The MTBF for the ABT22V10-7, under the same condition is 5.6 trillion years.

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BiCMOS versatile PAL device
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t'

Preliminary specification
ABT22V10-7

MTBF in seoonds

NOTE: Vee · 5V, Tamb - 25"C
Fe - clock frequency
Fj · input event frequency

t' in nanoseconds

MTBF = exp(t'/t)/(to*Fc*Fi)

Figure 5. MTBF versus t' for ABT22V10-7 at~= 83ps and T0 = 2.2 x 1017 sec

TYPICAL VALUES FOR t AND To AT VARIOUS VccS AND TEMPERATURES

Tomb= 0°C

Tamb = 25°C

Vee 5.5V 5.0V 4.5V

~
83ps 80ps 85ps

To 8.1 X 1018 sec 4.0 X 1018 sec 3.4 X 1014 sec

~
82ps 83ps 91ps

To 7.5 X 1018 sec 2.2 X 1011 sec 2.5 X 1012 sec

~
101ps 98ps 106ps

Tamb = 70°C
To 3.0 X 1012 sec 4.4X 1011 sec 1.1X10s sec

OUTPUT MACRO CELL
AR CLK
SP

s,

Sa

OUTPUT CONFIGURATION

0

0

Registered/Active-LOW

0

1

Registered/Active-HIGH

1

0

CorrbinatorlaVActlve-LOW

1

1

Corrt>inatOflaVActlve-LOW

Unprogrammed fuse Programmed fuse

October 1993

Figure 6. Output Macro Cell Logic Diagram 137

Philips Semiconductors Programmable Logic Devices
BiCMOS versatile PAL device

Preliminary specification
ABT22V10-7

a. Registered/Active-LOW

c. Combinatorial/Active-LOW

b. Registered/Active-HIGH

d. Combinatorial/Active-HIGH

Figure 7. Output Macro Cell Configurations

Registered Output Configuration
Each Macro Cell of the ABT22V10 includes a D-type flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In
a the registered configuration (S1 = 0), the
array feedback is from of the flip-flop.

Combinatorial 1/0 Configuration
Any Macro Cell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (S1 = 1). In the combinatorial configuration, the feedback is from the pin.

Variable Input/Output Pin Ratio
The ABT22V1 O has twelve dedicated input lines. and each Macro Cell output can be an 1/0 pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to Vee or GND.

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BiCMOS versatile PAL device

Preliminary specification
ABT22V10-7

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee

Supply voltage

V1N

Input voltage

-0.5

+7.0

Voe

-1.2

Vee+ 0.5

Voe

VouT l1N

Output voltage Input currents

-0.5

Vee +0.5

Voe

~o

+30

mA

louT

Output currents

Ts!!!_

Storage temperature range

+100

mA

-SS

+150

oc

NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This

is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS

TEMPERATURE

Maximum junction

c 1so0

Maximum ambient

75°C

Allowable thermal rise ambient to junction

75°C

OPERATING RANGES

SYMBOL Vee Tamb

PARAMETER Supply voltage Operating free-air temperature

RATINGS

MIN

MAX

+4.75

+5.25

0

+75

UNIT
Voe
oc

DC ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

Input voltage

V1L

Low

V1H

High

V1

Clamp

Output voltage

TEST CONDITIONS'
Vce=MIN Vee= MAX Vee= MIN, 11N =-18mA

LIMITS

MIN

MAX

0.8 2.0
-1.2

UNIT
v v v

Vol

Low

VoH

High

Input current

Vee= MIN, V1N = V1H or V1L IOL= 16mA
loH =~.2 mA

0.5

v

2.4

v

l1L (except Pin 1)

Low

Vee= MAX V1N = 0.40V

-100

µA

l1L (Pin 1) Low

l1H

High

11

Maximum input current

Output current

V1N = 0.40V V1N = 2.7V V1N = 5.5V

-150

µA

25

µA

1.0

mA

Vee= MAX

loZH

Output leakage3

V1N = V1L or V1H. VouT = 2.7V

100

µA

lozL

Output leakage3

V1N = V1L or V1H. VouT = 0.4V

-100

µA

lsc

Short circuit2

VouT = 0.5V

~o

-130

mA

Ice

Vee supply current

Vee= MAX

210

mA

NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. No more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. VouT = O.SV has been
chosen to avoid test problems caused by tester ground degradation. 3. 1/0 pin leakage is the worst case of lozx or 11x (where X = H or L).

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BiCMOS versatile PAL device

Preliminary specification
ABT22V10-7

AC ELECTRICAL CHARACTERISTICS
Over commercial operating range unless otherwise specified.

TEST

LIMITS1

SYMBOL

PARAMETER

CONDITIONS

MIN

TVP

MAX

UNIT

lpo

Input or feedback to non-registered output2

Active-LOW

7.5

i ~I

Active-HIGH

7.5

ns

Is

Setup time from input, feedback or SP to Clock

tH

Hold time

5.5

ns

0

ns

!co

Clock to output

lcF

Clock to feedback3

tAR

Asynchronous Reset to registered output

6.0

ns

2.5

ns

10.0

ns

tARW

Asynchronous Reset width

7.5

ns

tARR

Asynchronous Reset recovery time

5.5

ns

ts PR

Synchronous Preset recovery time

5.5

ns

tWL

Width of Clock LOW

4.0

ns

tWH

Width of Clock HIGH

4.0

ns

IMAX

Maximum frequency; External feedback 1/(ts + lco)4

87

MHz

Maximum frequency; Internal feedback 1/(ls + lcFf

125

MHz

~A

Input to Output Enable5

9.0

ns

~R

Input to Output Disable5

Capacitance&

9.0

ns

C1N

Input Capacitance (Pin 1)

V1N = 2.0V

Vee =5.0V

6

pF

Input Capacitance (Others)

V1N =2.0V

Tamti = 25°C

6

pF

CouT

Output Capacitance

VouT= 2.0V

I= 1MHz

8

pF

NOTES:

1. Commercial Test Conditions: R1 = 3000, R2 = 3900 (see Test Load Circuit).

2. lpo is tested with switch S1 closed and CL= 50pF (including jig capacitance). V1H = 3V, V1L = OV, VT= 1.5V. 3. Calculated from measured IMAX internal.

4. These parameters are not 1000/o tested, but are calculated at initial characterization and at any time the design is modified where frequency

may be affected.

5. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL_ 5pF. High-to-High impedance tests are made to an output

voltage of Vr = (VoH -0.5V) with S 1open, and Low-to-High impedance tests are made to the Vr = (VoL + 0.5V) level with S1 closed.

6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance

may be affected.

TEST LOAD CIRCUIT
C1YC2

L > Vee

lo

Fo

VOLTAGE WAVEFORM

OUT

INPUTS

In

Fn

CK

'CE

GND

NOTE:
C1 and C2 are to bypass Vee to GND.

-=

2.5ns

2.5ns

MEASUREMENTS: All circuit delays are measured at the +1.5V level of in· puts and outputs, unless otherwise specified.

Input Pulses

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BiCMOS versatile PAL device
SWITCHING WAVEFORMS
INPUT OR FEEDBACK COMBINATORIAL OUTPUT
Combinatorial Output

CLOCK

tg+tcF

Clock to Feedback (fMAX Internal) {See Path at Right)

Preliminary specification
ABT22V10-7

INPUT OR FEEDBACK

REGISTERED OUTPUT

Registered Output

CLK

r---------- -----,

1

I

I

I

I

LOGIC ts

REGISTER

I

I

I

I I

~--~ tcF ~----

I I

L---------------~

CLOCK

Clock Width

INPUT ASSERTING ASYNCHRONOUS RESET
REGISTERED OUTPUT
CLOCK
Asynchronous Reset NOTES: 1. VT= 1.5V. 2. Input pulse amplitude OV to 3.0V. 3. Input rise and fall times 2.5ns max.
October 1993

INPUT OUTPUT
Input to Output Disable/Enable

INPUT ASSERTING SYNCHRONOUS PRESET

CLOCK

-----tc-o~:_T REGISTERED
OUTPUT

__

Synchronous Preset

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BiCMOS versatile PAL device

Preliminary specification
ABT22V10-7

Programmable 3-State Outputs
Each output has a 3-State output buffer with 3-State control. A product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feedback. The combinatorial output provides a bidirectional 1/0 pin, and may be configured as a dedicated input if the buffer is always disabled.
Programmable Output Polarity
The polarity of each macro cell output can be Active-HIGH or Active-LOW, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save "DeMorganizing" efforts.
Selection is controlled by programmable bit S0 in the Output Macro Cell, and affects both registered and combinatorial outputs. Selection is automatic, based on the design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be Active-HIGH (So= 1).
Preset/Reset
For initialization, the ABT22V10 has additional Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous Preset (SP) product term is asserted high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the Asynchronous Reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW, independent of the clock.
Note that Preset and Reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected.
Metastable Immune Flip-Flops
The D-type flip-flops have been designed such that the outputs will not glitch or display an output anomaly if the input set up or hold times are violated. Based on a~ of < 90 ps, and sampling the output Sns after the clock

edge, the typical MTBF is 170.3 years. If the sample is taken 10ns after the clock the MTBF is 5.6 trllion years.
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable system initialization. Outputs of the ABT22V10 will depend on the programmed output polarity. The Vee rise must be monotonic and the reset delay time is 1-10µs maximum.
Security Fuse
After programming and verification, a ABT22V10 design can be secured by programming the security fuse link. Once programmed, this fuse defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the security fuse is programmed, the array will read as if every fuse is programmed.
Quality and Testability
The ABT22V1 Ooffers a very high level of built-in quality. Extra programmable fuses provide a means of verifying performance of all AC and DC parameters. In addition, this verifies programmability and functionality of the device to provide the highest programming and post-programming functional yields.
Low Ground Bounce
The Philips Semiconductors BiCMOS QUBiC process produces exceptional noise immunity. The typical ground bounce, with 9 outputs simultaneously switching and the
o.av. 10th output held low, is less than
Technology
The BiCMOS ABT22V10 is fabricated with the Philips Semiconductors process known as QUBiC. QUBiC combines an advanced, state-of-the-art 1.0µm (drawn feature size) CMOS process with an ultra fast bipolar process to achieve superior speed and drive capabilities. OUBiC incorporates three layers of Al/Cu interconnects for reduced chip size, and our proven Ti-W fuse technology ensures highest programming yields.

Programming
The ABT22V10-7 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, induding Philips Semiconductors SNAP design software package. ABEL1" CUPLTM and PALASM® 90 design software packages also support the ABT22V10-7 architecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PROGRAMMING/SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Support Material) of this data handbook for additional information.
OUTPUT REGISTER PRELOAD The register on the ABT22V10 can be
preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. The procedure for preloading follows:
1. Raise Vee to 5.0V ± 0.25V.
2. Set Pin 2 or 3 to VHH to disable outputs and enable preload.
3. Apply the desired value (V1LPIV1HPl to all registered output pins. Leave combinatorial output pins floating.
4. Clock Pin 1 from V1LP to V1HP·
5. Remove ViLP/VIHP from all registered output pins.
6. Lower Pin 2 or 3 to V1LP·
7. Enable the output registers according to the programmed pattern.
8. Verify VoL!VoH at all registered output pins. Note that the output pin signal will depend on the output polarity.

ABEL is a trademark of Data llO Corp. CUPL is a trademark of Logical Devices, Inc. PALASM Is a registered trademark ci AMO Corp.

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BiCMOS versatile PAL device

Preliminary specification
ABT22V10-7

"AND" ARRAY - (I, B)

l,B

l,B

T.ll

i

,D

[

STATE

1 l CODE

I J L INACTIVE 1

o

I, B i l , B l, ll
,D STATE TRUE

SYMBOL VHH V1LP V1HP to 1110

PARAMETER Super-level input voltage Low-level input voltage High-level input voltage Delay time 1/0 valid after Pin 2 or 3 drops from VHH to V1LP

I, B i l , B T, ll

I, B i l , B l, ll

,D

r 1 l STATE

CODE

I 1 [ COMPLEMENT

L

,D STATE DON'T CARE

LIMITS

MIN

REC

MAX

9.5

9.5

10

0

0

0.8

2.4

5.0

5.5

100

200

1000

100

UNIT
v v v
ns
ns

PINS 2, 3
REGISTERED OUTPUTS
CLOCK
NOTE: 1. This is the initial state.

V1LP
to
V1HP ' - - - - - - - - - - - - V1LP Output Register Preload Waveform

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BiCMOS versatile PAL device

Preliminary specification
ABT22V10-7

REGISTERED ACTIVE-LOW OUTPUT

Power-Up Reset Waveform

SYMBOL lpR Is lwL

Power-up Reset Time Input or Feedback Setup Time Clock Width LOW

PARAMETER

LIMITS

I MIN

MAX

1 1

See AC Electrical

Characteristics

UNIT µs

POWER-UP RESET
The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and

parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways Vee can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are:

1. The Vee rise must be monotonic.
2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met.

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BiCMOS versatile PAL device

PROGRAM TABLE

[

CONTROL WORD

Preliminary specification
ABT22V10-7

:r 1

1 POLARITY ..,. ..,.

63 64 PIN 13 11 10 9 8 7 6

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Philips Semiconductors Programmable Logic Devices
BiCMOS versatile PAL device
PROGRAM TABLE (Continued)

Preliminary specification
ABT22V10-7

, SP PIN 13 11 10 9 8 7 6 5 4 3 2 1 23 22 21 20 19 18 17 16 15 14

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BiCMOS versatile PAL device
SNAP RESOURCE SUMMARY DESIGNATIONS
piogram.and array (44 I 132)

Preliminary specification
ABT22V10-7

October 1993

CLK
Output Macro Cell 147

Philips Semiconductors Programmable Logic Devices
ECL programmable array logic

Product specification
10H20EV8/10020EV8

DESCRIPTION
The 10H20EVB/10020EV8 is an ultra
high-speed universal ECL PAL® device. Combining versatile output macrocells with a standard AND/OR single programmable array, this device is ideal in implementing a user's custom logic. The use of Philips Semiconductors state-of-the-art bipolar oxide isolation process enables the 1OH20EV8/10020EV8 to achieve optimum speed in any design. The SNAP design software package from Philips Semiconductors simplifies design entry based upon Boolean or state equations.
The 10H20EVB/10020EV8 is a two-level logic element comprised of 11 fixed inputs, an input pin that can either be used as a clock or 12th input, 90 AND gates, and 8 Output Logic Macrocells. Each Output Macrocell can be individually configured as a dedicated input, dedicated output with polarity control, a bidirectional 1/0, or as a registered output that has both output polarity control and feedback to the AND array. This gives the part the capability of having up to 20 inputs and eight outputs.
The 10H20EV8/10020EV8 has a variable number of product terms that can be OR'd per output. Four of the outputs have 12 AND terms available and the other four have 8 terms per output. This allows the designer the extra flexibility to implement those functions that he couldn't in a standard PAL device. Asynchronous Preset and Reset product terms are also included for system design ease. Each output has a separate output enable product term. Another feature added for the system designer is a power-up Reset on all registered outputs.

The 10H20EV8/10020EV8 also features the ability to Preload the registers to any desired state during testing. The Preload is not affected by the pattern within the device, so can be performed at any step in the testing sequence. This permits full logical verification even after the device has been patterned.
FEATURES
· Ultra high speed ECL device - !po = 4.5ns (max) - tis= 2.6ns (max) - lcKo = 2.3ns (max) - IMAX= 208MHz
· Universal ECL Programmable Array Logic - 8 user programmable output macrocells - Up to 20 inputs and 8 outputs - Individual user programmable output polarity
· Variable product term distribution allows increased design capability
· Asynchronous Preset and Reset capability
· 1OKH and 1OOK options
· Power-up Reset and Preload function to enhance state machine design and testing
· Design support provided via SNAP and other CAD tools
· Security fuse for preventing design duplication
·Available in 24-Pin 300mil-wide DIP and 28-Pin PLCC.

PIN CONFIGURATIONS
F Package
14 15 VEE ,_ _ _ __,- . F = Ceramic DIP (300mil*wide)
A Package
A= Plastic Leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION 24-Pin Ceramic Dual In-Line (300mil-wide)
28-Pin Plastic Leaded Chip Carrier

ORDER CODE
10H20EV8-4F 10020EV8-4F
1OH20EV8-4A 10020EV8-4A

DRAWING NUMBER 05868 0401F

®PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc.

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Philips Semiconductors Programmable Logic Devices
ECL programmable array logic
LOGIC DIAGRAM

Product specification
1OH20EV8/10020EV8

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
ECL programmable array logic
FUNCTIONAL DIAGRAM
CU<ll

Product specification
1OH20EV8/10020EV8

PROGRAMMABLE AND ARRAY (90 x40)

FUNCTIONAL DESCRIPTION
The 1OH20EV8/10020EV8 is an ultra high-speed universal ECL PAL-type device. Combining versatile Output Macrocells with a standard AND/OR single programmable array, this device is ideal in implementing a user's custom logic.

As can be seen in the Logic Diagram, the device is a two-level logic element with a programmable AND array. The 20EV8 can have up to 20 inputs and 8 outputs. Each output has a versatile Macrocell whereby the output can either be configured as a dedicated input, a dedicated combinatorial output with polarity control, a bidirectional· 1/0, or as a registered output that has both output polarity control and feedback into the AND array.

The device also features 90 product terms. Two of the product terms can be used for a global asynchronous preset and/or reset. Eight of the product terms can be used for individual output enable control of each Macrocell. The other 80 product terms are distributed among the outputs. Four of the outputs have eight product terms, while the other four have 12. This arrangement allows the utmost in flexibility when implementing user patterns.

Output Logic Macrocell
The 10H20EV8/10020EV8 incorporates an extremely versatile Output Logic Macrocell that allows the user complete flexibility when configuring outputs.

Figure 1. Output Logic Macrocell

As seen in Figure 1, the 10H20EV8/ 10020EV8 Output Logic Macrocell consists of an edge-triggered D-type flip-flop, an output select MUX, and a feedback select MUX. Fuses S0 and S1 allow the user to select between the various cells. S 1 controls whether the output will be either registered with internal feedback or combinatorial 1/0. S0 controls the polarity of the output (ActiveHIGH or Active-LOW). This allows the user to achieve the following configurations: Registered Active-HIGH output, Registered Active-LOW output, Combinatorial ActiveHIGH output, and Combinatorial Active-LOW output. With the output enable product term, this list can be extended by adding the configurations of a Combinatorial 1/0 with Polarity or another input.

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ECL programmable array logic

Product specification
1OH20EV8/10020EV8

ABSOLUTE MAXIMUM RATINGS1

SYMBOL VEE V1N

PARAMETER Supply voltage Input voltage (V1Nshould never be more negative than VEE)

RATING -8.0
0 to VEE

UNIT
v v

lo

Output source current

-50

mA

Ts

Operating Temperature range

-55to+150

·c

TJ

Storage Temperature range

L Ceramic Package

+165

·c

l

Plastic Package

+150

·c

NOTE:

1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at

these or any other condition above those indicated in the operational and programming specification of the device is not implied.

DC OPERATING CONDITIONS 10H20EV8

TEST

LIMITS

SYMBOL Vee. Vc01. Vco2 VEE

PARAMETER Circuit ground Supply voltage (negative)

CONDITIONS

MIN NOM MAX

0

0

0

--5.2

UNIT
v v

Tamb =0°C

-1170

-840

mV

V1H

High level input voltage

Tamb = +25°C

-1130

-810

mV

Tami>= +75°C
Tamb = o·c

-1070 -1950

-735

mV

-1480

mV

V1L

Low level input voltage

Tamb = +25°C

-1950

-1480

mV

Tamb = +75°C

-1980

-1450

mV

Tamb

Operating ambient temperature range

0

+25

+75

°C

NOTE: When operating at other than the specified VEE voltage (-5.2V), the DC and AC Electrical Characteristics will vary slightly from specified values.

DC OPERATING CONDITIONS 10020EV8

SYMBOL Vee. Vco1o Vco2 VEE VEE

PARAMETER Circuit ground
Supply voltage
Supply voltage when opetating with the 1OK or 10KH ECL family

TEST CONDITIONS

LIMITS

MIN NOM MAX

0

0

0

-4.8 -4.5 -4.2

-5.7

UNIT
v v v

VEE=-4.2V

-1150

V1H

High level in put voltage

VEE =-4.5V

-1165

-880

mV

VEE=-4.8V

-1165

VEE=-4.2V

-1475

mV

V1L

Low level input voltage

VEE=-4.5V

-1810

-1475

mV

VEE=-4.8V

-1490

mV

Tamb

Operating ambient temperature range

0

+25

+85

·c

NOTE:
When operating at other than the specified VEE voltages (--4.2V, --4.5V, --4.BV), the DC and AC Electrical Characteristics will vary slightly from their specified values.

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ECL programmable array logic
D
Registered Active-HIGH
D

Product specification
1OH20EV8/1 0020EV8
D
I.I
Registered Active-LOW
D

Combinatorial Active-HIGH

Combinatorial Active-LOW

Figure 2. Output Macro Cell Configurations

OUTPUT MACRO CELL CONFIGURATION
Shown in Figure 2 are the four possible configurations of the output macrocell using fuses So and S1. As seen. the output can either be registered Active-HIGH/LOW with feedback or combinatorial Active-HIGH/LOW with feedback. If the registered mode is
chosen. the feedback from the 0 output to
the AND array enables one to make state machines or shift registers without having to tie the output to one of the inputs. If a combinatorial output is chosen. the feedback gate is enabled from the pin and allows one to create permanent outputs. permanent inputs. or 110 pins through the use of the output enable (D) product term.
OUTPUT ENABLE
Each output on the 1OH20EV8/10020EV8 has its own individual product term for output enable. The use of the D product term (direction control) allows the user three possible configurations of the outputs. They are: always enabled, always disabled, and

controlled by a programmed pattern. A HIGH on the D term enables the output, while a LOW performs the disable function. Output enable control can be achieved by programming a pattern on the D term.
The output enable control can also be used to expand a designer's possibilities once a combinatorial output has been chosen. If the D term is always HIGH. the pin becomes a permanent Active-HIGH/LOW output. If the D term is always LOW (all fuses left intact). the pin now becomes an extra input.
PRESET AND RESET
The 1OH20EV8/10020EV8 also includes a separate product term for asynchronous Preset and asynchronous Reset. These lines are common for all registers and are asserted when the specific product term goes HIGH. Being asynchronous. they are independent of the clock. It should be noted that the actual state of the output is dependent on how the polarity of the particular output has been chosen. If the outputs are a mix of

Active-HIGH and Active-LOW, a Preset signal will force the Active-HIGH outputs HIGH while the Active-LOW outputs would go LOW. even though the Q output of all flip-flops would go HIGH. A Reset signal would force the opposite conditions.
PRE LOAD
To simplify testing. the 10H20EV8/10020EV8 has also included PRELOAD circuitry. This allows a user to load any particular data desired into the registers regardless of the programmed pattern. This means that the PRELOAD can be done on a blank part and after that same part has been programmed to facilitate any post-fuse testing desired.
It can also be used by a designer to help debug a circuit. This could be important if a state machine was implemented in the 10H20EV8/ 10020EV8. The PRELOAD would allow the entry of any state in the sequence desired and start clocking from that particular point. Any or all transitions could be verified.

October 22. 1993

152

Philips Semiconductors Programmable Logic Devices
ECL programmable array logic

Product specification
1OH20EV8/10020EV8

DC ELECTRICAL CHARACTERISTICS 10H20EV8
0°C STarrb :s; +75°C, VEE =-5.2V±5%, Vee= Veo1 = Ve02 = GND

SYMBOL

PARAMETERt

VoH

High level output voltage

TEST CONDITIONS2 V1N = V1H MIN or V1L MAX

Vol

Low level output voltage

V1N = V1H MIN or V1L MAX

ltH

High level input current

ltl

Low level input current

-IEE

Supply current

V1N=V1H MAX
V1N=V1LMIN Except 1/0 Pins VEE= MAX All inputs = V1H MAX

Tamb
0°C +25°C +75°C
0°C +25°C +75°C
0°C +75°C
0°C +75°C
0°C to +75°C

UMITS4

MIN

MAX

-1020 -980 -920

-840 -810 -735

-1950 -1950 -1950

-1630 -1630 -1600

UNITS mV mV

220

µA

0.3

µA

250

mA

DC ELECTRICAL CHARACTERISTICS 10020EV8
0°c STamb :s; +85°C, -4.8V :s; VEE S-4.2V, Vee= Veo1 = Veo2 = GND

LIMITS4

SYMBOL

PARAMETER,

TEST CONDITIONS2

MIN TYP MAX UNITS

VEE =-4.2V -1020

-870 mV

VoH

High level output voltage

V1N = V1H MAX or Vil MIN VEE =-4.5V -1025 -955 -880 mV

VEE =-4.8V -1035

-880 mV

Outputs Apply V1HMIN or V1lMAX to VEE =-4.2V -1030

mV

VoHT

High level output threshold voltage Loaded one input at a time, other VEE =-4.5V -1035

mV

son with

inuts at V1HMAX or VtlMIN. VEE =-4.8V -1045

mV

to-2.0V Apply V1HMIN or V1LMAX to VEE =-4.2V

-1595 mV

Vou

Low level output threshold voltage ±0.010V one input at a time, other VEE =-4.5V

-1610 mV

inuts at V1HMAX or VtlMIN. VEE =-4.8V

-1610 mV

VEE =-4.2V -1810

-1605 mV

Vol

Low level output voltage

lnuts at ViHMAX or V1lMIN. VEE =-4.5V -1810 -1705 -1620 mV

VEE =-4.8V -1830

-1620 mV

l1H

High level input current

One input under test at V1HMAX· Other inputs at V1LMIN·

220

µA

ltl

Low level input current

One input under test at V1lMIN· Other inputs at V1HMAX· 0.5

µA

-IEE

VEE supply current

All inputs at V1HMAX·

230

mA

NOTES: 1. All voltage measurements are referenced to the ground terminal. 2. Each ECL 10KH/100K series device has been designed to meet the DC specification after thermal equilibrium has been established.
Thermal equilibrium is established by applying power for at least 2 minutes, while maintaining transverse airflow of 2.5 meters/sec (500 linear feet/min.) over the device, mounted either in a test socket or on a printed circuit board. Test voltage values are given in the DC operating conditions table. Conditions for testing shown in the tables are not necessarily worst case. For worst case testing guidelines, refer to DC Testing, Chapter 1, Section 3, of the Philips Semiconductors 10/100K ECL Data Handbook. 3. Terminals not specifically referenced can be left electrically open. Open inputs assume a logic LOW state. Any unused pins can be terminated to -2V. If tied to VEE· it must be through a resistor> 10K. It is recommended that pins that have been programmed as RESET, PRESET, or CLOCK inputs not be left open due to the possibility of false triggering from internally and externally generated switching transients. 4. The specified limits represent the worst case values for the parameter. Since these worst case values normally occur at the supply voltage and temperature extremes, additional noise immunity can be achieved by decreasing the allowable operating condition ranges.

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
ECL programmable array logic

Product specification
1OH20EV8/10020EV8

AC ELECTRICAL CHARACTERISTICS (for Ceramic Dual In-Line Package)
10H20EV8: 0°C S Tamb S +75°C, VEE= -5.2V ± 5%, Vee= Veo1 = Vco2 = GND 10020EV8: 0°C s Tamb s +85°C, -4.8V s VEE s -4.2V, Vee= Ve01 = Vco2 = GND
UMITS1

SYMBOL

PARAMETER

FROM

TO

O"C

+25"C

+75°C/+85"C

UNIT

I'

MIN2 TYP3 MAX2 MIN2 TYP3 MAX2 MIN2 TYP3 MAX2

Pulse Width

lcKH

Clock High

CLK+ CLK- 2.0 0.6

2.0 0.6

2.0 0.6

ns

lcKL

Clock Low

CLK- CLK+ 2.0 0.9

2.0 0.9

2.0 0.9

ns

lcKP

Clock Period

CLK+ CLK+ 4.0

4.0

4.0

ns

tPRH

Preset/Reset Pulse (l,1/0)± (I, 1/0)± 4.5

-

4.5 -

4.5 -

ns

Setup and Hold Time

tis

Input

(l,1/0)± CLK+ 2.6 1.0

2.6 1.1

2.7 1.4

ns

t1H

Input

CLK+ (I, l/0)± 0.1

<0

0.1

<0

0.1

<0

ns

tPRS

Clock Resume after (l,l/0)± CLK+

4.6

1.0

4.6 0.9

4.6 0.8

ns

Preset/Reset

Propagation Delay

tpo

Input

(1,1/0)± 1/0±

2.85 4.7

2.95 4.7

3.35 4.7

ns

lcKO loE loo tPRD tppR

Clock Output Enable Output Disable Preset/Reset Power-on Reset

CLK+ (l,1/0)± (l,1/0)± (l,l/0)±
VEE

110± 1/0 1/0 1/0± 1/0

1.65 2.4

2.0 4.2

2.0 4.2

2.8 4.7

-

10

1.7 2.4

2.1 4.2

2.1 4.2

3.0 4.7

-

10

2.0

2.5

ns

2.2

4.2

ns

2.2

4.2

ns

3.5

4.7

ns

-

10

ns

IMAX

212 377

212 357

204 294

MHz

NOTES: 1. Refer to AC Test Circuit and Voltage Wafeforms diagrams. 2. Maximum loading conditions: 89 fuses intact per row. 3. Typical loading conditions: 15 fuses intact per row. (All "inactive" fuses, except those necessary for correct functionality, are removed.)

October 22, 1993

154

Philips Semiconductors Programmable Logic Devices
ECL programmable array logic

Product specification
1OH20EV8/10020EV8

AC ELECTRICAL CHARACTERISTICS (for Plastic Leaded Chip Carrier) 10H20EV8: 0°C !>Tami>!> +75°C, VEE= -5.2V ± 5%, Vee= Vc01 = Vco2 = GND
10020EV8: O°C !>Tami>!> +85°C, -4.8V !>VEE!> -4.2V, Vee= Vco1 = Vco2 = GND
UMITS1

SYMBOL

PARAMETER

FROM

TO

O"C

+25"C

+75"Ct+85°c

UNIT

MIN TYP3 MAX2 MIN TYP3 MAX' MIN TYP3 MAX2

Pulse Width

lcKH

Clock High

CLK+

CLK-

2.0 0.6

2.0 0.6

2.0 0.6

ns

lcKL

Clock Low

CLK- CLK+ 2.0 0.9

2.0 0.9

2.0 0.9

ns

lcKP

Clock Period

CLK+ CLK+ 4.0

4.0

4.0

ns

lpRH

Preset/Reset Pulse (l,110)± (I, 1/0)± 4.5

-

- 4.5

- 4.5

ns

Setup and Hold Time

tis

Input

(I, 1/0)± CLK+ 2.5 1.0

2.5 1.1

2.6 1.4

ns

t1H

Input

CLK+ (I, 1/0)± 0

<0

0

<0

0

<0

ns

IPRS

Clock Resume after (1,110)± CLK+ 4.5 1.0

4.5 0.9

4.5 0.8

ns

Preset/Reset

Propagation Delay

!po

Input

(1,110)± 110±

2.85 4.5

2.95 4.5

3.35 4.5

ns

lcKO

Clock

CLK+

110±

1.65 2.2

1.7 2.2

2.0 2.3 ns

loE

Output Enable

(I, 1/0)±

1/0

2.0 4.0

2.1 4.0

2.2 4.0

ns

loo

Output Disable

(1,110)±

110

2.0 4.0

2.1 4.0

2.2

4.0

ns

lpRO

Preset/Reset

(1,110)± 110±

2.8 4.5

3.0 4.5

3.5

4.5

ns

tppR

Power-on Reset

VEE

110

-

10

-

10

-

10

ns

IMAX

212 377

212 357

204 294

MHz

NOTES: 1. Refer to AC Test Circuit and Voltage Wafeforms diagrams. 2. Maximum loading conditions: 89 fuses intact per row. 3. Typical loading conditions: 15 fuses intact per row. (All "inactive" fuses, except those necessary for correct functionality, are removed.)

October 22, 1993

155

Philips Semiconductors Programmable Logic Devices
ECL programmable array logic

Product specification
1OH20EV8/10020EV8

AC TEST CIRCUIT

+2.0V ± 0.010V

25µF J

0.1µF
J

r-L1

PULSE

,-,

GENERATOR

:t

11.3

SCOPE

,-,
\I
*';'

Vco1 Vee Vco2 1 4 - - - - - - L 2 - - - - - - - ' 1 - - - - - - .

,,

Fx

SCOPE

111

DUT

CLKn12 Fy
FM

FN

VEE

25µFJ

0.01µF J

-2.SV ± o.01ov FOR 10020EV8
-3.2V ± o.01ov FOR 10H20EV8

NOTES:
1. Use decoupling capacitors of Q.1µF and 2SµF from GND to Vee, and Q.Q1 µF and 2SµF from GND to VEE (Q.Q1 and Q.1 µF capacitors should be NPO Ceramic or MLC tyf,9)- Decoupling capacitors should be placed as close as physically possible to the DUT and lead length should be kept to less than /4 inch (6mm).
2. All unused inputs should be connected to either HIGH or LOW state consistent with the LOGIC function required. 3. All unused outputs are loaded with SQQ to GND.
4. L1 and L2 are equal length SQQ impedance lines. L3, the distance from the DUT pin to the junction of the cable from the Pulse Generator and the cable to the Scope, should not exceed 1/4 inch (6mm).
S. Rr =SQQ terminator internal to Scope. 6. The unmatched wire stub between coaxial cable and pins under test must be less than 1/4 inch (6mm) long for proper test. 7. CL = Fixture and stray capacitance ,;; 3pF.
8. Any unterminated stubs connected anywhere along the transmission line between the Pulse Generator and the DUT or between the DUT and the Scope should not exceed 1/4 inch (6mm) in length (refer to section on AC setup procedure).
9. All SQQ resistors should have tolerance of± 1% or better.
1Q. Test procedures are shown for only one input or set of input conditions. Other inputs are tested in the same manner.

October 22, 1993

1S6

Philips Semiconductors Programmable Logic Devices
ECL programmable array logic

Product specification
1OH20EV8/10020EV8

VOLTAGE WAVEFORMS

NEGATIVE PULSE
POSITIVE PULSE

-trHL 80%
20%
80% 20%
-trLH

tw(L) tw(H)

trLH80%
20%
80%

trHL-

+111DmV (10H20EV8) +1050mV (10020EV8)
+310mV
+1110mV (10H20EV8) +1050mV (10020EV8)
+310mV

INPUT PULSE REQUIREMENTS

Vee= Vco1 = Vc02 =+2.0V .:t0.01ov. VEE= -3.2V :t 0.010V, Yr= GNO (OV)

I I I I I FAMILY AMPLITUDE REP RATE PULSE WIDTH

·rLH

·rHL

I J 10KHECLI 800mVp_p

1MHz

500ns

l 1.3±0.2ns 11.3+0.2ns

INPUT PULSE REQUIREMENTS

Vee= Vco1 = Vc02 = +2.0V ._o.01ov, Vee= -2.SV ± 0.010V, Yr= GND (OV)

I I I I FAMILY AMPLITUDE 1 l l I 100KECLj 740mVp_p

REP RATE 1MHz

PULSE WIDTH 500ns

ITLH

ITHL

0.7±0.1ns.I_ 0.7±0.1ns

Input Pulse Definition

October 22, 1993

157

Philips Semiconductors Programmable Logic Devices
ECL programmable array logic

TIMING DIAGRAMS
1,110 (INPUT)

-~H

Product specification
1OH20EV8/10020EV8

110 (REGISTERED
OUTPUT)

1-------·PD-----~-

________________ (COMBINATORI~~----------------- ~,.....·--------

OUTPUT)

___,

Flip-Flop and Gate Outputs

ov

REGISTERED ACTIVE-LOW
OUTPUT
1,110 (INPUT)

October 22, 1993

Power-On Reset 158

Philips Semiconductors Programmable Logic Devices
ECL programmable array logic
TIMING DIAGRAMS (Continued)

Product specification
1OH20EV8/10020EV8

Output Enable/Oleable
CLK--------_-_=f
ASYNCllAONOUS PRESET.tlESET

l/O (OUTPUT)

Asynchronous PreHl/Reset

October 22, 1993

159

Philips Semiconductors Programmable Logic Devices
ECL programmable array logic

Product specification
1OH20EV8/1 0020EV8

REGISTER PRELOAD
The 10H20EV8/10020EV8 has included circuitry that allows a user to load data into the output registers. Register PRELOAD can be done at any time and is not dependent on any particular pattern programmed into the device. This simplifies the ability to fully verify logic states and sequences even after the device has been patterned. The pin levels and sequence necessary to perform the register PRELOAD are shown below.
PIN3
PIN 23

OUTPUTS
DISABLE OUTPUTS ENABLE PRELOAD

APPLY EXTERNAL INPUTS TOBE
PRELOADED

DATA PRELOADED AND PRELOAD DISABLED

REMOVE EXTERNAL INPUTS

LIMITS

SYMBOL

PARAMETER

MIN

TYP

Input HIGH level during

V1H

PRELOAD and Verify

-1.1

--0.9

Input LOW level during

V1L

PRELOAD and Verify

-1.85 -1.65

Vpp

PRELOAD enable voltage applied to 111

1.45

1.6

NOTE: 1. Unused inputs should be handled as follows:
- Set at V1H or V1L - Terminated to -2V - Tied to VEE through a resistor> 10K - Open

MAX --0.7 -1.45 1.75

UNIT
v v v

October 22, 1993

160

Philips Semiconductors Programmable Logic Devices
ECL programmable array logic

Product specification
1OH20EV8/10020EV8

LOGIC PROGRAMMING
The 1OH20EVB/10020EVB is fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips Semiconductors SNAP design software package. ABELTM and CUPLTM design software packages also support the 10H20EVB/10020EVB.

All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
10H20EVB/10020EVB logic designs can also be generated using the program table entry format detailed on the following page. This

program table entry format is supported by SNAP only.
To implement the desired logic functions, the state of each logic variable from logic equations (I, F, Q, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.

-4"' -4"' 4'"' -4"' - "AND"ARRAY (I)'(F)'(Q:!!!)

LF,Q

l,f,Q
I, F, a

1,F,o
I, F, a

__ LF,Q

l,F,Q

I, F,a

P, D,AP,AR

L STATE

j CODEj

I J [ INACTIVE1·2

o

P,D,AP,AR

I

STATE 11 F,Q

IC~E I

P,D,AP,AR

I

STATE l,F,Q

l~EI

P,D,AP,AR

I STATE
I DON'T CARE

C~DE I

NOTES: 1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates. 2. Any gate (P, D, AP, AR) will be unconditionally inhibited if any one of the I, For Q link pairs is left intact.

OUTPUT MACROCELL CONFIGURATIONS

OUTPUT MACROCELL CONFIGURATION

CONTROL WORD FUSE

POLARITY FUSE

Registered Output, Active-HIGH Registered Output, Active-LOW

D

H

01

L1

Combinatorial 1/0, Active-HIGH

B

H

Combinatorial 1/0, Acitve-LOW

B

L

NOTE: 1. This is the initial (unprogrammed) state of the device.

PROGRAMMING AND SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ SoftwareSuppon)ofthe 1992 PLO Data Handbook for additional information.

ABEL Is a trademark ol Data l/O COrp. CUPL Is a trademark ol Logical Devices, Inc.

October 22, 1993

161

Philips Semiconductors Programmable Logic Devices
ECL programmable array logic

Product specification
1OH20EV8/10020EV8

PROGRAM TABLE

f

CONTROL WORD

_Illlll

T

AND

E
~

12 11 10 ( I a

I 1 6

s::I 4

a

2

1

a

1

6

F(I)
s::I 4

a

2

1

::r :P:rOL]ARIT::Yr ::r ::r OR_lFIXEl1!_

10

24 36 48

62 74

PIN 3 23 22 16 15 14 13 11 10 9 2 1 21 20 18 17 8 7 5 4 w
-~'w~
~z

October 22, 1993

162

Philips Semiconductors Programmable Logic Devices
ECL programmable array logic

Product specification
1OH20EV8/10020EV8

SNAP Features · Schematic entry using DASHTM 4.0 or
above or OrCADTM SDT Ill
· State Equation Entry
· Boolean Equation Entry
· Allows design entry in any combination of above formats
·Simulator - Logic and fault simulation - liming model generation for device timing simulation - Synthetic logic analyzer format
· Macro library for standard TTL and user defined functions
· Device independent netlist generation

· JEDEC fuse map generated from netlist
SNAP (Synthesis, Netlist, Analysis and Program) is a versatile development tool that speeds the design and testing of PML. SNAP combines a user-friendly environment and powerful modules that make designing with PML simple. The SNAP environment gives the user the freedom to design independent of the device architecture.
The flexibility in the variations of design entry methodologies allows design entry in the most appropriate terms. SNAP merges the inputs, regardless of the type, into a highlevel netlist for simulation or compilation into a JEDEC fuse map. The JEDEC fuse map can then be transferred from the host computer to the device programer.

SNAP's simulator uses a synthetic logic analyzer format to display and set the nodes of the design. The SNAP simulator provides complete timing information, setup and hold-time checking, plus toggle and fault grading analysis.
SNAP operates on an IBM® PC/XT, PC/AT, PS/2, or any compatible system with DOS 2. 1 or higher. A minimum of 640K bytes of RAM is required together with a hard disk.
DESIGN SECURITY The 10H20EV8/10020EV8 has a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved.

October 22, 1993

163

Philips Semiconductors Programmable Logic Devices
ECL programmable array logic

Product specification
1OH20EV8/10020EV8

SNAP RESOURCE SUMMARY DESIGNATIONS ·
CLI<ll
I*

PROGRAMMABLE AND ARRAY (90 x 40)

'''Ami'

F

F

F

F

F

F

October 22, 1993

Output Logic Macrocell 164

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic
(48 x 73 x 22)

Product specification
PHD48N22-7

DESCRIPTION The PHD48N22-7 is an ultra fast Programmable High-speed Decoder featuring a 7.5ns maximum propagation delay. The architecture has been optimized using Philips Semiconductors state-of-the-art bipolar oxide isolation process coupled with titanium-tungsten fuses to achieve superior speed in any design.
The PHD48N22-7 is a two level logic element comprised of 36 fixed inputs, 73 AND gates, 10 outputs, and 12 bidirectional I/Os. This gives the device the ability to have as many as 48 inputs. Individual 3-State control of all outputs is also provided.
The device is field-programmable, enabling the user to quickly generate custom patterns using standard programming equipment. Proprietary designs can be protected by programming the security fuse.
The SLICE and SNAP software packages from Philips Components-Philips Semiconductors support easy design entry for the PHD48N22-7 as well as other PLO devices.
Order codes are listed below.

FEATURES·· · Ideal for high speed system decoding · Super high speed at 7.5ns !po · 36 dedicated inputs · 22outputs
- 12 bidirectional 1/0
- 1odedicated outputs
· Security tuse to prevent duplication of proprietary designs.
· Individual 3-State control of all outputs · Field-programmable on industry standard
programmers · Available in 68-Pin Plastic Leaded Chip
Carrier (PLCC)
APPLICATIONS · High speed memory decoders · High speed code detectors · Random logic · Peripheral selectors · Machine state decoders

PIN CONFIGURATION A Package

26

A = Plastic Leaded Chip Carrier

Pin Function 1 10 2 11 12
Vcc3 5 13
14 15 8 16 9 17 10 18 11 19 12 110 13 111 14 GND5 15 GND1 18 112 17 113 18 114 19 115 20 116 21 Vcc2 22 117 23 118 24 119 25 120 26 121 27 122 28 123 29 124 30 125 31 126 32 GN03 33 127 34 128

Pin Function 35 129 36 130 37 131 38 VcC4 39 132 40 133 41 134 42 135 43 BO 44 01 45 82 46 83 47 B4 48 GND6 49 GND2 50 05 51 86 52 87 53 00 54 01 55 Vcc1 56 02 57 03 58 04 59 05 60 06 61 07 62 08 63 09 64 ORO 65 OR1 66 GND4 67 OR2 68 OR3

ORDERING INFORMATION DESCRIPTION
68-Pin Plastic Leaded Chip Carrier

ORDER CODE PHD48N22-7A

DRAWING NUMBER 0398E

October 22. 1993

165

853--1588 11164

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (48 x 73 x 22)
LOGIC DIAGRAM

Product specification
PHD48N22-7

-<>-----....--__,.., 00 ::g:===i>--lliil 00
::g:===i>---i~ 05
-<>----......- -....... 04 ::g:===i>--llffl 03 -<>-----....-----· 02
-<>----p---jMI 01 -<>----p>----1'<'100
:::::====:r..--.--im 87
15

18
110
111@]f-'~:::+l:ll=l:IU::ttl1l=ll:ll=l:IU::ttl1l=ll:ll=l:IU::ttl1l=ll:ll=li!!l::Ut.l=llll=li!!l::ttl1l=llll=l:l1:l=:ttl1l=llll=l+ll::tl+l=llll=lml=:ml=:==~:1--112(!Il-1~:m1::tttt=tttt::!tlt::tltt:tt:lt:1~:1til=ll1rl::tltt:lttl::m~tt:1ttt:tt!l::J:ll:l::Utf::::tttt::!tlt::tltt:tt:lt:1~:1til=ll1~==~:1-----{illl35
113
114 }-t~mt:1:jjj::j:jjj::jltf::::t:l+l=t11+1=t1+1=11tt=lf:tt=lf:lt:ll11t:tt:l+=ttlt:mt=Uti~=+t:t:l:::tm=lttl:=lttl::tttt::tttt::t11:\::t11:\:==~1--~-1ID~ J-t~mt=mt=mt=mt=mt=mt=mt=mt=mt=mt=mt=mt=mt=mt=mt=Un::::mt=mt=mt=mt=mt=mt=mt=mt===:::3:1--~-i!Jm
118
119

I~ ~J-O::::::j:jj~ltt=mJ::j:j:j:l::Ult=lttJ::llf+:j:jtt:tt:jj:jfll+:j:j:jj::IJjil=11ltt=lttl::jj:jjf:l:l;~ltt=mJ::j:j:j:l::Ult=lttJ::llf+:j:jtt=U,t+=====i3----l!!J
NOTES: 1. AJJ. unprogrammed or virgin "ANO" gate locations are pulled to logic "O" 2. :;.~~~ Programmable connections

October 22, 1993

166

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (48 x 73 x 22)
FUNCTIONAL DIAGRAM

Product specification
PHD48N22-7

B0-87
00-09 ORO OR1-0R3

ABSOLUTE MAXIMUM RATINGS1

SYMBOL Vee

PARAMETER Supply voltage

RATINGS

MIN

MAX

--0.5

+7

UNIT Voc

V1N

Input voltage

--0.5

+5.5

Vrx;

VouT

Output voltage

+5.5

Voe

l1N

Input currents

-30

+30

mA

louT lamb Tstg

Output currents Operating temperature range Storage temperature range

+100

mA

0

+75

oc

--<55

+150

oc

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

OPERATING RANGES

SYMBOL Vee Tamb

PARAMETER Supply voltage Operating free-air temperature

RATINGS

MIN

MAX

+4.75

+5.25

0

+75

UNIT
Voe
oc

THERMAL RATINGS

TEMPERATURE

Maximum junction

150°C

Maximum ambient
Allowable thermal rise ambient to junction

75°C 75°C

October 22, 1993

167

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic
(48 x 73 x 22}

Product specification
PHD48N22-7

DC ELECTRICAL CHARACTERISTICS
- O"C .s: Ta.m .s: +75°C, 4.75 < Vcc.s:5.25V

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP1

MAX

UNIT

Input voltage2

I~

V1L

Low

V1H

High

Vic

Clamp

Vcc=MIN Vee= MAX Vee= MIN, l1N = -18mA

0.8

v

2.0

v

--0.8

-1.5

v

Output voltage

Vol

Low

VoH

High

Input current

Vee= MIN, Vr.1 = V1H or V1L

IOL=+24mA

loH = --3.2mA

2.4

0.5

v

v

l1L

Low

l1H

High

11

High

Output current

Vee=MAX V1N = +0.40V V1N =+2.7V V1N =Vee= Vee MAX

-20

-250

µA

25

µA

too

µA

lozH

Output leakage 3

lozL

Output leakage 3

los

Short circuit 4

Ice

Vee current

Capacitance5

Vee= MAX Vour=+2.7V Vour = +0.40V Vour = +OV
Vee= MAX

100

µA

-100

µA

--30

-00

-90

mA

420

mA

C1N

Input

Vee= +5V V1N = 2.0V@f = 1MHz

8

pF

Cour

1/0

Vour = 2.0V@f = 1MHz

8

pF

NOTES:
1. Typical limits are at Vee = 5.0V and Tamb = +25°C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3. Leakage current for bidirectional pins is the worst cas.e of l1L and loZL or l1H and lozL· 4. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. 5. These parameters are not 100% tested, but are periodically sampled.

October 22, 1993

168

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (48 x 73 x 22)

Product specification
PHD48N22-7

AC ELECTRICAL CHARACTERISTICS
0°C s TarroS +75°C, 4.75s Vccs 5.25V, R1 = 200Q, R2 = 390Q
Operating temerature at 200 CFM Minimum air flow.

TEST

LIMITS

SYMBOL

PARAMETER

FROM

TO

CONDITIONS

MIN

MIN

UNIT

lpo1 1

Propagation delay through BIO outputs

(I, B,OR)±

Output±

CL= 50pF

7.5

ns

tpo2 1

Propagation delay through OR outputs

(I, B,OR)±

Output±

CL= 50pF

8.0

ns

loE2

Output Enable

(l,B,OR)± Output enable

CL= 50pF

10

ns

loo2

Output Disable

(I, B,OR)± Output disable

CL= 5pF

10

ns

NOTES:
1. tp01 ,2 are tested with switch S1 closed and CL = 50pF. 2. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL. 5pF. High-to-High impedance tests are made to an output voltage of VT= (VoH - 0.5V) with S1open, and Low-to-High impedance tests are made to the VT= (VOL+ 0.5V) level with S1closed.

VIRGIN STATE
A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are disabled.
2. All p-terms are disabled in the AND array.

TIMING DEFINITIONS

SYMBOL

PARAMETER

tpo1

Input to output propagation

delay (through 8/0 outputs).

tpo2

Input to output propagation

delay (through OR outputs).

too

Input to Output Disable

(3-State) delay (Output

Disable).

toE

Input to Output Enable delay

(Output Enable).

TIMING DIAGRAM

INPUTS,1/0

OUTPUTS

WAVEFORM

INPUTS
MUSTOE STEADY

OUTPUTS
WILLBE STEADY

WAVEFORM
~

INPUTS
DON'T CARE; ANY CHANGE PERMITTED

OUTPUTS
CHANGING; STATE UNKNOWN

}»--«{ DOES NOT APPLY

CENTER UNEISHIGH IMPEDANCE "OFF" STATE

October 22, 1993

169

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (48 x 73 x 22}

Product specification
PHD48N22-7

! 9f---O---+-,.....-'l'---'l---f--f--T--'l'-'l--+--+--+---!~f--+--+--+-+~f--+-~
I ~ 7f--+--+--+-t~t--+--+--+---!~t--+--t--+---!~t--+--t--+-+~t---t--~
w
zQ &t--+--t--+-+~t--+--+--+---!~t--+--+--+---!~t--+--t--+-+~t--+-~ 2 5>-+---+---+-+~t--+---+---+-+~t--+---+---+-+~1----+---+---+-+~t--+--~
~c 4f--+--t--+-t~t--+--t--+---!~f--+--t--+---!~f--+--t--+-+~t--+-~ ~ 3f--+--+--+-+~!--+--+--+---!~f--+--+--+---!~f--+--+--+-+~f--+-~

0

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

NOTE: o =OR Outputs o = BK> Outputs

TEST CONDITIONS: Tamb = 7S"C; Vee· 4.75V; CL· SOpF;

R1 · 200n; R2 · 3900

Worst-Case Propagation Delay vs. Number of Outputs Switching

AC TEST LOAD CIRCUIT
C1YC2 INPUTS
NOTE:
c, and C:! are to bypass Vee to GND.

Vee t:__/

R1

lo

By

CL 19 DUT Bw

Bx

Bz

GND

=

= OUTPUTS

VOLTAGE WAVEFORMS

L. .J - ~ _.j ~~~

2.Sns

2.Sns

~-J\ ·fL-

2.Sna

2.Sna

MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses

October 22, 1993

170

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic
(48 x 73 x 22)

Product specification
PHD48N22-7

LOGIC PROGRAMMING

PHD48N22-7 logic designs can also be

PROGRAMMING/SOFTWARE

The PHD48N22-7 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL'" and

generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only.

SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/ Software Support) of this data handbook for

CUPLTM 90 design software packages also support the architecture.

To implement the desired logic functions, each logic variable (I, B, P and D) from the

additional information.

All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic

logic equations is assigned a symbol. TRUE (High), COMPLEMENT (Low), DON'T CARE and INACTIVE symbols are defined below.

l,Bi l,B I,Bil,B I,Bil,B l,Bil,B captureformat.
"AND" ARRAY - (I, B)

T,B

T,B

T,IJ

T,IJ

I STATE INACTIVE1

,D
I I CODE 0

NOTE: 1. This is the initial state.

I

STATE TRUE

,D
I I CODE H

,D

STATE
LL 1l JJ COMPLEMENT

CODE L

, D

I I I STATE DON'T CARE

CODE
-

ABEL is a trademark of Data 110 Corp. CUPL is a trademark of Logical Devices, Inc.

October 22, 1993

171

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic
(48 x 73 x 22)

Product specification
PHD48N22-7

PROGRAM TABLE

T

INPUTS

E R

I

B

OR

II 35 34 33 32 31 30 Ill 28 f1 26 25 26 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 3 2 1 0

0

1 2

i+

3

4

5

' 7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

26

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

58

60

61

62

63

64

65

66

67

58

69

70

71

72

PIN 42 41 40 39 37 36 36 34 33 31 30 Ill 28 ZI 26 25 26 23 22 20 19 18 17 16 13 12 11 10 9 8 7 6 5 3 2 1 52 51 50 47 46 45 44 43 58 67 65 64

w
~w
i~
;::

October 22, 1993

172

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (48x73x22)

PROGRAM TABLE (Continued)

OUTPUTS

0

B

OR

Product specification
PHD48N22-7

October 22, 1993

173

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (48 x73 x 22)

Product specification
PHD48N22-7

TYPICAL SYSTEM APPLICATION

r---- I OPTIONAL ------------------,

I

RCLOCK ENERATOR

I

I

I~ ="" I
,-
PHD48N22
I

CACHE CONTROL

RESET CLK2

I

I

I-
ADDRESS

I J.
-L~--

1(1-
['..,-
11
Jj

~ 0
;)1
~

CACHE TAG SAAM
ll
CACHE
DATA

__: :__ J

80386 CPU
K DATA INTRN

I-
l I-
L t-
t-

t--
+-

DRAM CONTROL

is

~, /

DRAM

.A

-v

A.

UO INTERFACE

.A

"

-v

.A

v
ADVANCED OMA
.A

-v'

-1'
; ) MULTIBUS 1/0
LOCAL BUS
CONTROL
l

,______

l ]

tJJ

llJTI QlTI J TI 1

'--

INTERRUPT CONTROLLER

TI
EXTERNAL INTERRUPTS

TIMER/ COUNTER

FLOPPY DISK
CONTROL
]
ii FLOPPY

FIXED DISK CONTROL
J
FIXED DISK

J

JJ JJ

l il llil 11 il 11

LAN CONTROL

SERIAL PORTS

GRAPHICS COPROCESSOR

1 1 ] 1
l I ~ 1 MM 11 ~
LAN CABLE KEYBOARD M O U S E .

EPROM

CRT

October 22, 1993

174

Philips Semiconductors Programmable Logic Devices
Programmable high-speed decoder logic (48 x 73 x 22)

SNAP RESOURCE SUMMARY DESIGNATIONS

I

,...,

~DI~~

IO y----i-6-)iiitMa~2+---+--+--+---+--+--+--

·

135

-+--+--+--+--+---+---·DIN<I&~ -+--+--+----+--+---+--~/J'j!N<J&~:

Product specification
PHD48N22-7

B0-87
00-09 ORO OR1-0R3

October 22, 1993

175

Programmable Logic Devices

Section 4
PLA Devices

CONTENTS

PLS153/A

Programmable logic arrays (18 x 42 x 10)

179

PLUS153B/D

Programmable logic arrays (18 x 42 x 10)

187

PLUS153-10

Programmable logic array (18 x 42 x 10) ...

195

PLS173

Programmable logic array (22 x 42 x 10) ......

203

PLUS173B/D

Programmable logic arrays (22 x 42 x 10)

211

PLUS173-10

Programmable logic array (22 x 42 x 10)

219

PLS100/PLS101

Programmable logic arrays (16 x 48 x 8) .............

227

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (18x42x10)

Product specification
PLS153/A

DESCRIPTION
The PLS153 and PLS153A are two-level logic elements, consisting of 42 AND gates and 10 OR gates with fusible link connections for programming 1/0 polarity and direction.
All AND gates are linked to 8 inputs (I) and 1Obidirectional 1/0 lines (B). These yield variable 1/0 gate configurations via 1O direction control gates (D), ranging from 18 inputs to 10 outputs.
On-chip TIC buffers couple either True (I, B) or Complement (T, B) input polarities to all AND gates, whose outputs can be optionally linked to all OR gates. Their output polarity, in tum, is individually programmable through a set of EX-OR gates for implementing AND/OR or AND/NOR logic functions.
The PLS153 and PLS153A are field-programmable, enabling the user to quickly generate custom patterns using standard programming equipment.

FEATURES
· Field-Programmable (Ni-Cr links) · 8 inputs · 42 AND gates · 100Rgates · 1Obidirectional 1/0 lines · Active-High or -Low outputs · 42 product terms:
- 32 logic terms - 1o control terms · 1/0 propagation delay: - PLS153: 40ns (max) - PLS153A: 30ns (max) ·Input loading: -100µA (max) · Power dissipation: 650mW (typ) · 3-State outputs · TIL compatible

APPLICATIONS
· Random logic · Code converters · Fault detectors · Function generators · Address mapping
· Multiplexing

ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Dual In-Line, 300mil-wide
20-Pin Plastic Leaded Chip Carrier

ORDER CODE
PLS153N, PLS153AN
PLS153A, PLS153AA

DRAWING NUMBER 0408B
0400E

PIN CONFIGURATIONS
N Package
N · Plastic DIP (300mil-wide)
A Package 12 1, 10 Vee 89
Ba
Bo GND 81 82 83
A. Plastic Leaded Chip carrier
LOGIC FUNCTION
TYPICAL PRODUCT TERM: Pn:A·8·C·D· ...
TYPICAL LOGIC FUNCTION: AT OUTPUT POLARITY= H Z:PO+P1 +P2 ··· AT OUTPUT POLARITY = L Z:PO+P1+P2 + ...
Z:Jl!l·l'f·!'2-. ..
NOTES: 1. For each of the 1o outputs, either function Z
(Active-High) or Z (Active-Low) is available, but not both. The desired output polarity Is programmed via
z.the Ex-OR gates.
2. A. B, C, etc. are user defined connections to fixed inputs (I) and bidirectional pins (B).

October 22, 1993

179

853-0311 11164

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (18x42x10)
LOGIC DIAGRAM

Product specification
PLS153/A

BB B8 B7 B& B5 B4 B3 B2 B1

NOTES:

1. All prograrrined 'AND' gate locations are pulled to !ogle ·1".

2. 3.

1)11
=::t:

programmed 'OR' gate locations Programmable connection.

are

pulled

to

logic ·er.

October 22, 1993

180

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays
(18 x 42 x 10)

FUNCTIONAL DIAGRAM

p 1

Po

Product specification
PLS153/A
D9

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee

Supply voltage

+7

Voe

VrN

Input voltage

+5.5

Voe

Vour

Output voltage

+5.5

Voe

lrN

Input currents

-30

+30

mA

louT

Output currents

+100

mA

Tamb

Operating temperature range

0

+75

oc

Tstg

Storage temperature range

-SS

+150

oc

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal rise ambient to junction

150°C 75°C 75°C

The PLS 153/A devices are also processed to military requirements for operation over the military temperature range. For specifications and ordering information consult the Philips Semiconductors Military Data Handbook.

October 22, 1993

181

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays
(18 x 42 x 10)

Product specification
PLS153/A

DC ELECTRICAL CHARACTERISTICS 0°c STam1>S+75°C, 4.75V s Vee S5.25V

SYMBOL Input voltagr

PARAMETER

TEST CONDITIONS

V1L

Low

V1H

High

Vic

Clamp3

Output voltagr

Vee= MIN Vcx;=MAX Vee= MIN, l1N = -12mA

Vol

Low4

VoH

High5

Input current9

Vcc=MIN loL= 15mA loH=-2mA

l1L

Low

l1H

High

Output current

Vee= MAX V1N=0.45V V1N =5.5V

lo( OFF)

Hi-Z states

las

Short circuit3· 5, s

Ice

Vee supply current7

Capacitance

Vcc=MAX Vour=5.5V Vour=0.45V Vour =OV Vee= MAX

Vcc=5V

C1N

Input

V1N = 2.0V

Ce

1/0

Ve =2.0V

NOTES:
1. All typical values are at Vee = 5V, Tarrb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with +10V applied to 17. 5. Measured with +10V applied to la-7. Output sink current is supplied through a resistor to Vcc6. Duration of short circuit should not exceed 1 second.
7. Ice is measured with lo, 11 at OV, 12 - 17 and BIHi at 4.5V. 8. Leakage values are a combination of input and output leakage. 9. l1L and l1H limits are for dedicated inputs only (lo -17).

LIMITS MIN TYP1 MAX
0.8 2.0
-0.8 -1.2

0.5 2.4

-100 40

80

-140

-15

-70

130

155

8 15

UNIT
v v v
v v
µA µA
µA mA mA
pF pF

October 22, 1993

182

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays
(18 x 42 x 10)

Product specification
PLS153/A

AC ELECTRICAL CHARACTERISTICS
0°C ;:; Tarro ;:; +75°C, 4.75V ;:; Vee ;:; 5.25V, R1 = 300'1, R2 = 390'1

LIMITS

SYMBOL

PARAMETER

FROM

TO

TEST

PLS153

PLS153A

UNIT

CONDITION MIN TYP1 MAX MIN TYP1 MAX

tpo

Propagation delay

Input±

Output±

CL= 30pF

30

40

20

30

ns

loE

Output enable2

Input±

Output-

CL= 30pF

25

35

20

30

ns

loo

Output disable2

Input±

Output+

CL=5pF

25

35

20

30

ns

NOTES:
1. All typical values are at Vee = 5V, Tarro= +25°C. 2. For 3-State output; output enable times are tested with CL= 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output
voltage of VT= (VoH-0.5V) with S 1 open, and Low-to-High impedance tests are made to the VT= (Vol+ 0.5V) level with S 1 closed. 3. All propagation delays are measured and specified under worst case conditions.

VOLTAGE WAVEFORMS
- w _jl.~ .J~c

TEST LOAD CIRCUIT
c1 y c 2

: __ji\ 1&%AL90% Sna~ -lsna
MEASUREMENTS: Alt circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses

INPUTS
NOTE: C1 and C2areto bypass Vee to GND.

Vee L::__>

R1

lo

By

CL
17 OUT Bw

Bx GND Dz
=

OUTPUTS =

TIMING DEFINITIONS

SYMBOL

PARAMETER

!po

Propagation delay between

input and output.

loo

Delay between input change

and when output is off (Hi-Z

or High).

loE

Delay between input change

and when output reflects

specified output level.

TIMING DIAGRAM
l,B
B

October 22, 1993

183

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays
(18 x 42 x 10)

Product specification
PLS153/A

LOGIC PROGRAMMING The PLS153/A is fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips Semiconductors SNAP, Data I/O's ABELTM and Logical Devices, Inc. C,UPLTM design software packages.
All packages allow.Boolean and state equation entry .formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
OUTPUT POLARITY - J_B)

PLS153/A logic designs can also be generated using the program table entry format detailed on the following page. This program table entry format is supported by the Philips Semiconductors SNAP PLO design sol!Ware package.
To implement the desired logic functi()ns, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE,

COMPLEMENT, INACTIVE, PRESET, etc.,. are defined below.
PROGRAMMING/SOFTWARE SUPPORT Refer to Section 9 (DeV9/opment Software) and Section 1O(Third-Party Programmer! Software Support) of this data handbook for additional information

J ( ACTIVE LEVEL ] CODE
lNo..!~~~TINJ lH

f 1 J ACTIVE LEVEL

CODE

1 J r (IN~i~NG) L

l,B, l,B l,B,l,B 1,B,l,B ANDARRAY- {I,B)

l,B

l,B

l,B

1,B ,l,B l,B

,D
I STATE

l,B P,D
STATE

,D
STATE l,B

,D
STATE DON'T CARE

OR ARRAY - (B)

+>--·

PnSTATUS ACTIVE1

CODE A

PnSTATUS INACTIVE

CODE
·

NOTES: 1. This is the initial unprogrammed state of all links.
2. Any gate Pn will be unconditioanlly inhibited if both the True and Complement of an input(either I or B) are left intact.

ABEL Is a trademark of Data l/O Corp. CUPL is a trademark of Logical Devices, Inc.

VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at "H" polarity.
2. All Pn terms are disabled.
3. All Pn leims are active on all outputs.
CAUTION: PLS153A TEST COLUMNS The PLS153A incorporates two columns not shown in the logic block diagram. These columns are used for in-house testing of the device in the unprogrammed state. These columns must be disabled prior to using the PLS153A in your application. If you are using a Philips Semiconductors-approved programmer, the disabling is accomplished during the device programming sequence. If these columns are not disabled, abnormal operation is possible.
Furthermore, because of these test columns, the PLS153A cannot be programmed using the programmer algorithm for the PLS153.

October 22, 1993

184

~

-a
:II

[

0
G')

.,-""''
!2

:II

--------A-ND--------'' -------OR-------

ACTIVE A

INACTIVE 0

' '

8(0) INACTIVE ·

l,B
I.ii

H I, 8(1)

,.'.-. -__- _- _- _-c_ot_irii_ci"_L_- _-_-_-_-

L

- ~ DON'T CARE

' ' '

(POL) L

'

NOTES In the unprogrammed state:
· Att AND gates aro pulled to a logic ·o· (low).
· Output polarity Is non-inverting. · Unused I and B bits In the AND array should be programmed
as Don~ Care (-). · Unused product terms In the OR array should be
programmed as INACTIVE (0).

VARIABLE
........ s .. - - ...-. .... . "' - .... ...-. ... .. - ........ - NAME

~ 15 ~ g 51 5: i !:! i c w l!l Ill Ill !!l Ill Ill ~ ~ ~ ~ ~ ;

CUSTOMER NAME

PURCHASE ORDER It

PHILIPS DEVICE#

CE(XXXX)

CUSTOMER SYMBOLIZED PART#

TOTAL NUMBER OF PARTS

PROGRAM TABLE IL_ REV_ DATE_ _ _

...

cs ..

"'

o 1:::1:1m-1

l>3::
~ Irmll

w

-"'
;

co
"'

:=::

=

.=:

;;I

_,....
I-·I-·I- 1-- I-

;;

.:::
;

u

:=::

'---i

-

=

.=:
;;I

---

;;

.:::

-"'

. 0 ..·..

>cz

. ~

,......,.:.

-"'

0

-

.....

H
I-
I-

:§ ~ Iii- ill
. I- ::;!

I-

-"' II-

0

-:::: -u
<X>o
x c..o... ~NIl3l x 3

..";;tri.
.g=
(/)
"3 '
('j" 0
:ac:l.
1t

....... Ill Ci!

-co a QC" "ti IQ

"' c0o

iii 3 3

('5" 2:

I....l....l.. ~
(/)

"b '
IQ
O" 0
."~.'·

-r u

"ti
8.

.. {/)
.......

c g

01 al

(,.)

Sl.

)> "£"

0~-

::l

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays
(18 x 42 x 10)

SNAP RESOURCE SUMMARY DESIGNATIONS

P?t

Po

D9

IO~.\DIH1~~
~ I L-6- ~t~~·~,- - - - - - + - - - - - + - - - + -

!

I

I

I

I

17

Product specification
PLS153/A

TOTIT1li!J
/_B9
I I I
BO

October 22, 1993

186

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (18x42x10)

Product specification
PLUS1538/D

DESCRIPTION
The PLUS153 PLDs are high speed, combinatorial Programmable Logic Arrays. The Philips Semiconductors state-of-the-art Oxide Isolated Bipolar fabrication process is employed to produce propagation delays as short as 12ns.
The 20-pin PLUS153 devices have a programmable AND array and a
programmable OR array. Unlike PAL® devices, 100% product term sharing is supported. Any of the 32 logic product terms can be connected to any or all of the 10 output OR gates. Most PAL ICs are limited to 7 AND terms per OR function; the PLUS153 devices can support up to 32 input wide OR functions.
The polarity of each output is user-programmable as either active-High or active-Low, thus allowing AND-OR or AND-NOR logic implementation. This feature adds an element of design flexibility, particularly when implementing complex decoding functions.
The PLUS 153 devices are user-programmable using one of several commercially available, industry standard PLO programmers.

FEATURES
· 1/0 propagation delays (worst case) - PLUS153B- 15ns max. - PLUS153D-12nsmax.
· Functional superset of 16LB and most other 20-pin combinatorial PAL devices
·Two programmable arrays - Supports 32 input wide OR functions
· B inputs · 1Obi-directional 1/0 · 42 AND gates
- 32 logic product terms - 10 direction control terms · Programmable output polarity - Active-High or Active-Low · Security fuse · 3-State outputs · Power dissipation: 750mW (typ.)
· TTL Compatible

PIN CONFIGURATIONS

N Package

GND

Vee
89 88 87 86 BS B4 B3 B2 B1

N = Plastic Dual In-Line Package (300mil-wide)

A Package

APPLICATIONS
· Random logic · Code converters · Fault detectors · Function generators · Address mapping · Multiplexing

88 B7 B6 BS B4
A :s: Plastic Leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Dual-In-Line 300mil-wide 20-Pin Plastic Dual-In-Line 300mil-wide 20-Pin Plastic Leaded Chip Carrier 20-Pin Plastic Leaded Chip Carrier

tpo(MAX) 15ns 12ns 15ns 12ns

ORDER CODE PLUS153BN PLUS153DN PLUS153BA PLUS153DA

DRAWING NUMBER 04080 04080 0400E 0400E

®PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices Corporation.

October 22, 1993

187

853--1285 11164

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays
(18 x 42 x 10)
LOGIC DIAGRAM

Product specification
PLUS153B/D

NOTES: 1. All programmed 'AND' gate locations are pulled to logic "1".
2. ~!I programmed 'OR' gate locations are pulled to logic ·a·.
3. :;~;:;;: Programmable connection.

October 22, 1993

188

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (18 x 42 x 10)

FUNCTIONAL DIAGRAM

p 1

Po

10

17

Product specification
PLUS153B/D

ABSOLUTE MAXIMUM RATINGS1

RATING

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee

Supply voltage

+7

Voe

V1N

Input voltage

+5.5

Voe

Vour

Output voltage

+5.5

Voe

l1N

Input currents

--30

+30

mA

lour

Output currents

+100

mA

Tamb

Operating free-air temperature range

0

+75

oc

Tstg

Storage temperature range

~5

+150

oc

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS
TEMPERATURE Maximum junction
Maximum ambient
Allowable thermal rise ambient to junction

1so0 c
75°C 75°C

October 22, 1993

189

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays
(18 x 42 x 10)

Product specification
PLUS153B/D

DC ELECTRICAL CHARACTERISTICS
0°C STambs +75°C, 4.75S Vccs5.25V

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS MIN yyp1 MAX

UNIT

Input voltage2

V1L

Low

V1H

High

Vic

Clamp

Output voltage2

Vee= MIN Vcc=MAX Vee= MIN, llN =-12mA

0.8

v

2.0

v

--0.8 -1.2

v

Vol

Low4

VOH

High5

Input current'

Vee= MIN loL= 15mA IOH=-2mA

0.5

v

2.4

v

l1L

Low

l1H

High

Output current

Vee =MAX V1N = 0.45V V1N =Vee

-100

µA

40

µA

lo( OFF)

Hi-Z states

Vcc=MAX VouT=2.7V Vour=0.45V

80

µA

-140

los

Short circuit3· 5·6

Ice

Vee supply current7

Capacitance

VouT=OV Vee= MAX

-15

-70

mA

150

200

mA

C1N

Input

Vcc=5V V1N=2.0V

8

pF

Ca

1/0

Va =2.0V

15

pF

NOTES:
1. All typical values are at Vee = 5V, Tant> = +25°C. 2. All voltage values are wilh respect to network ground terminal. 3. Test one at a time. 4. Measured wilh inputs 10 -12 = OV, inputs 13 -15 = 4.5V, inputs 17 = 4.5V and 16 = 10V. For outputs BO - 84 and for outputs 85 - 89 apply lhe
same conditions except 17 = OV. 5. Same conditions as Note 4 except 17 = +1OV. 6. Duration of short circuit should not exceed 1 second. 7. Ice is measured wilh inputs 10 -17 and BO - 89 = OV. 8. Leakage values are a combination of input and output leakage. 9. l1L and l1H limits are for dedicated inputs only (10 -17).

October 22, 1993

190

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays {18x42x 10)

Product specification
PLUS153B/D

AC ELECTRICAL CHARACTERISTICS 0°C s Taims +75°C, 4.75V s Vee s 5.25V, R1 = 300Q, R2 = 390Q

LIMITS

SYMBOL

PARAMETER

FROM

TO

TEST

PLUS153B

PLUS1530

UNIT

CONDITION MIN TYP MAX MIN TYP MAX

tpo

Propagation Delay2

Input+/- Output+/- CL =30pF

11

15

10

12

ns

toE

Output Enable1

Input+/- Output- CL= 30pF

11

15

10

12

ns

too Output Disable1

Input+/- Output+

CL= 5pF

11

15

10

12

ns

NOTES:
1. For 3-State output; output enable times are tested with CL= 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output voltage of VT= (VoH -0.SV) with S1open, and Low-to-High impedance tests are made to the VT= (Vol+ 0.5V) level with S1 closed.
2. All propagation delays are measured and specified under worst case conditions.

VOLTAGE WAVEFORMS

TEST LOAD CIRCUIT

MEASUREMENTS: All circuit delays are measured at the+ 1.5V level of inputs and ou1puts, unless otherwise specified.
Input Pulses

C1YC2
INPUTS
NOTE:
C1 and C2 are to bypass Vee to GND.

L > Vee
R1

10

By

CL

17

DUT

Bw

Bx

Bz

GND

':"

OUTPUTS ':"

TIMING DEFINITIONS

SYMBOL

PARAMETER

!po

Propagation delay between

input and output.

too

Delay between input change

and when output is off (Hi-Z

or High).

toE

Delay between input change

and when output reflects

specified output level.

TIMING DIAGRAM

+3V

1,8

1.SV

1.SV

e-l___., -k__,Jj~~: 1.___1.sv

October 22, 1993

191

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays
(18 x 42 x 10)

Product specification
PLUS1538/D

LOGIC PROGRAMMING

PROGRAMMING AND

The PLUS 1530/D is fully supported by

SOFTWARE SUPPORT

industry standard (JEDEC compatible) PLD

CAD tools, including Philips Semiconductors Refer to Section 9 (Development Software)

SNAP design software package. ABEL'" and and Section 10 (Third-Party

CUPLTM design software packages also support the PLUS153B/D architecture.

Programmer/Software Support) of this data handbook for additional information.

1,,

All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.

OUTPUT POLARITY - B

PLUS1530/D logic designs can also be generated using the program table entry format, which is detailed on the following page. This program table entry format is supported by SNAP only.

To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.

ACTIVE LEVEL
HIGH1 NON-INVERTING)

CODE H

ACTIVE LEVEL
LOW (INVERTING)

CODE L

1 1,B AND ARRAY - (I, B) l,B l,B

_,l,B
l,B 1,B

_,l,B _,l,B

1,8

1,8

l,B

l,B

,D

I J STATE
t I J INACTIVE1· 2

CODE
o

l,BI STATE

,D
I I CODE H

I

STATE 1,B

,D
I I CODE L

,D

I I - I STATE DON'T CARE

CODE

OR ARRAY - (B)
-fr>-·

-fr>-·

VIRGIN STATE
A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at "H" polarity.
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.

~

l J PnSTATUS

CODE

I J ACTIVE1

A

I J [ PnSTATUS L l · J INACTIVE

CODE

NOTES:
1. This is the initial unprogrammed state of all links. 2. Any gate Pn will be unconditionally inhibited if both the true and complement of an input (either
I or B) are left intact.

ABEL is a trademark of Data VO Corp. CUPL is a trademark of Logical Devices, Inc.

October 22, 1993

192

§

"C
:0

~

0
G')

Fl
<D
~

a-

-

-

-

-

--
VE

-A-NO-

-

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-

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1 INACTIVEI ·

-

--
B(O)

-

H ~B(I)

,.'_- -__- _- _- _-c_ot_iT_iio_L_-_-_-_- -_

NOTES In the unprogrammed state:
· All AND gates are pulled to a logic "O" (Low). · Output polarity Is non-invening. · Unused I and B bits in the AND array should be programmed

CUSTOMER NAME_ _ _ _ _ _ _ __

PURCHASEORDER~-------

PHILIPS DEVICE#

CFIXXXXI

CUSTOMER SYMBOLIZED PART_..__ _ __

:0 :I>
=:::
;;!
mrm

as Don't Care (-).

OONTCARE

HIGH I ; (POL)

· Unused product terms in the OR array should be

TOTAL NUMBER OF PARTS..__ _ _ __

LOW L

programmed as INACTIVE (o).

PROGRAM TABLE It__ REV_ DATE_ __

VARIABLE NAME

~lgl~l~I ~lil~l~l~I ilil~I ~l~l~l~I ~I ~l~l~l~I ~l~l~l~l~l~l~l~I ~1~1=1~1 ~1 ~1~1~1~1 ·1w1~1~1a l::Cm-t

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'.I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 1:1~ -~~~+~~-rr++~~-rr++~~-rr++~~-rr++~~-rr++~~-rr++~-+:t

o:l-EFff3~Ffff3-EFtf3~Fff33-Eff33-EFff~

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Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (18 x 42 x 10)
SNAP RESOURCE SUMMARY DESIGNATIONS
17

Product specification
PLUS153B/D
09

~-----<>-'--oeo

October 22, 1993

194

Phillps Semiconductors Programmable Logic Devices
Programmable logic array (18x42x10)

Product specification
PLUS153-10

DESCRIPTION
The PLUS 153-10 PLO is a high speed, combinatorial Programmable Logic Array. The Philips Semiconductors state-of-the-art Oxide Isolated Bipolar fabrication process is employed to produce maximum propagation delays of 1Ons or less.
The 20-pin PLUS153 device has a programmable AND array and a
programmable OR array. Unlike PAL® devices, 100% product term sharing is supported. Any of the 32 logic product terms can be connected to any or all of the 10 output OR gates. Most PAL ICs are limited to 7 AND terms per OR function; the PLUS 153-1 Ocan support up to 32 input wide OR functions.
The polarity of each output is userprogrammable as either Active-High or Active-Low, thus allowing AND-OR or AND-NOR logic implementation. This feature adds an element of design flexibility, particularly when implementing complex decoding functions.
The PLUS153-10 device is userprogrammable using one of several commercially available, industry standard PLO programmers.

FEATURES
· 1/0 propagation delays (worst case) - PLUS153-10 - 10ns max.
· Functional superset of 16L8 and most other 20-pin combinatorial PAL devices
· Two programmable arrays - Supports 32 input wide OR functions
· 8 inputs · 10 bi-directional 1/0 · 42 AND gates
- 32 logic product terms - 10 direction control terms · Programmable output polarity - Active-High or Active-Low · Security fuse · 3-State outputs · Power dissipation: 825mW (typ.) · TTL Compatible
APPLICATIONS
· Random logic · Code converters · Fault detectors · Function generators · Address mapping · Multiplexing

PIN CONFIGURATIONS
N Package Vee B9
B8 B7 BG BS B4 B3 B2 81
N = Plastic DIP (300mil-wide)
A Package 12 11 10 Vee B9
B8 B7 BG 85 B4
A = Plastic leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Dual-In-Line 300mil-wide 20-Pin Plastic Leaded Chip Carrier

tpo(MAX) 10ns 10ns

ORDER CODE PLUS153-10N PLUS153-10A

DRAWING NUMBER 04080 0400E

®PAL Is a registered trademark of Advanced Micro Devices Corporation.

October 22, 1993

195

853-1508 11164

Philips Semiconductors Programmable Logic Devices
Programmable logic array
(18 x 42 x 10)
LOGIC DIAGRAM
16

Product specification
PLUS153-10
I''

B9 B9 B7 BS BS B4 B3 B2 B1
Xo ::::.
31 · · · · · ·24 23· ···· ·16 15· · · · · · 8 7 · · · · · · 0

NOTES: 1. All programmed 'AND' gate locations are pulled to logic "1tt.
ua·. 2. ~!I programmed 'OR' gate locations are pulled to logic
3. :::::::· Programmable connection.

October 22, 1993

196

Philips Semiconductors Programmable Logic Devices
Programmable logic array (18 x 42 x 10)
FUNCTIONAL DIAGRAM
p 1

Product specification
PLUS153-10
Do

ABSOLUTE MAXIMUM RATINGS1

RATING

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee

Supply voltage

+7

Voe

Vin

Input voltage

+5.5

Voe

VOUT

Output voltage

+5.5

Voe

l1N

Input currents

-30

+30

mA

loUT

Output currents

+100

mA

Tami>

Operating free-air temperature range

0

+75

·c

Tatg

Storage temperature range

--05

+150

·c

NOTES: 1. Stresses abow those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS TEMPERATURE
Maximum junction
Maximum ambient Allowable thermal rise ambient to junction

150°C 75°C 75°C

October 22, 1993

197

Philips Semiconductors Programmable Logic Devices
Programmable logic array
(18 x 42 x 10)

Product specification
PLUS153-10

DC ELECTRICAL CHARACTERISTICS
0°C s Tamb s +75°C, 4.75 s Vee s 5.25V

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP1

MAX

UNIT

Input voltage2

V1L

Low

V1H

High

Vic

Clamp

Output voltage2

Vee= MIN Vcc=MAX Vee= MIN, 11N =-12mA

0.8

v

2.0

v

--0.8

-1.2

v

Vol

Low"

VoH

High5

Input current9

Vee= MIN loL = 15mA loH = -2mA

0.4

0.5

v

2.4

2.9

v

l1L

Low

l1H

High

Output current

Vee =MAX V1N = 0.45V V1N =Vee

-20

-100

µA

1

40

µA

lo(OFF)

Hi-Z state8

las

Short circuit3· 5, 6

Ice

Vee supply current7

Capacitance

Vcc=MAX Vour = 2.7V Vour = 0.45V VouT =OV Vee =MAX

0

80

µA

-15

-140

-15

-30

-70

mA

165

200

mA

Vee= 5V

C1N

Input

V1N = 2.0V

8

pF

Ce

1/0

Va= 2.0V

15

pF

NOTES:
1. All typical values are at Vee= 5V, Tarro = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with inputs 10 - 12 = OV, inputs 13 -15 = 4.5V, inputs 17 = 4.5V and 16 = 10V. For outputs BO - B4 and for outputs B5 - B9 apply the
same conditions except 17 = OV. 5. Same conditions as Note 4 except 17 = +1OV. 6. Duration of short circuit should not exceed 1 second. 7. Ice is measured with inputs 10 - 17 and BO - B9 = OV. 8. Leakage values are a combination of input and output leakage. 9. l1L and l1H limits are for dedicated inputs only (10 -17).

October 22, 1993

198

Philips Semiconductors Programmable Logic Devices
Programmable logic array
(18 x 42 x 10)

Product specification
PLUS153-10

AC ELECTRICAL CHARACTERISTICS 0°C s; Tamb s; +75°C, 4.75V s; Vee s; 5.25V, R1 = 3000, R2 = 3900

TEST

LIMITS

SYMBOL

PARAMETER

FROM

TO

CONDITION

MIN

TYP

MAX

UNIT

tpD

Propagation Delay2

Input+/-

Output+/-

CL= 30pF

8

10

ns

loE

Output Enable1

Input+/-

Output-

CL= 30pF

8

10

ns

loD

Output Disable1

Input+/-

Output+

CL= 5pF

8

10

ns

NOTES:
1. For 3-State output; output enable times are tested with CL= 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output
voltage of VT= (VoH -0.5V) with S1 open, and Low-to-High impedance tests are made to the VT= (VoL + 0.5V) level with S1 closed. 2. All propagation delays are measured and specified under worst case conditions.

VOLTAGE WAVEFORMS
- ov __jsnsL ·R~ tfJ~l-0%

TEST LOAD CIRCUIT
C1YC2

:__lt\ 10%AL90% Snsl _.!sns
MEASUREMENTS: All circuit delays are asured at the+ 1.5V level of inputs and outputs, Unless otherwise specified.
Input Pulses

INPUTS
NOTE:
C1 and C2 are to bypass Vee to GND.

Vee L__>

R1

10

By

17 OUT Bw

R2

CL

Bx

Bz

GND

=

= OUTPUTS

TIMING DEFINITIONS

SYMBOL

PARAMETER

tpD

Propagation delay between

input and output.

loD

Delay between input change

and when output is off (Hi-Z

or High).

loE

Delay between input change

and when output reflects

specified output level.

TIMING DIAGRAM
l,B
B

October 22, 1993

199

Philips Semiconductors Programmable Logic Devices
Programmable logic array
(18 x 42 x 10)

Product specification
PLUS153-10

LOGIC PROGRAMMING
The PLUS153--10 is fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips Semiconductors SNAP design software package. ABELTM and CUPLTM design software packages also support the PLUS153--1 Oarchitecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PLUS 153--1 O logic designs can also be generated using the program table entry format, which is detailed on the following page. This program table entry format is supported by SNAP only.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.

PROGRAMMING AND SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer!Scftware Support) of this data handbook for additional information.
OUTPUT POLARITY - B
CODE H

l,B, 1,8 1,8,1,8 1,8,l,B ANDARRAY- (I, B)

1,B

1,B

l,B

ACTIVE LEVEL LOW
(INVERTING)

CODE

1,8 ,l,B l,B

,D

I J STATE
t I J INACTIVE1, 2

CODE o

1,8I STATE

,D
I I CODE H

I STATE l,B

,D
I I CODE L

,D

I I - I STATE DONTCARE

CODE

OR ARRAY - (B)
-fr>-·

-fr>-·

VIRGIN STATE
A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at "H" polarity.
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.

l PnSTATUS
t I J ACTIVE1

CODE j
A

t ± · j PnSTATUS INACTIVE

CODE

NOTES:
1. This is the initial unprogrammed state of all links. 2. Any gate Pn will be unconditionally inhibited if both the true and complement of an input (either
I or B) are left intact.

ABEL is a trademark of Data 1/0 Corp. CUPL is a trademark of Logical Devices, tnc.

October 22, 1993

200

§

"'O :II

~

0 Cl

-~
<D

- - - - - - - - -AND- - - - - - -,I- - - - - - -O-R- - - - - - - NOTES

:II

CUSTOMER NAME_ _ _ _ _ _ _ __

:)s>:

~

INACTIVE
1,B
11:0

Io
I H
IL 1 1,e(1)

ACTIVE A
B(O) I INACTIVE! ·
,'- - - - - -CONTROL - - - - -
'---------------

ln the unprogrammed state:
· All AND gates are pulled to a logic "O" (Low). · Output polarlty is non-inverting. · Unused I and B bits in the AND array should be programmed
as Don't Care (-).

PURCHASEORDER~-------

PHILIPS DEVICE #

CF!XXXXl

CUSTOMER SYMBOLIZED PART~----

~
mrtO

DON'T CARE i -

HIGH I ~ (POL)

· Unused product terms in the OR auay should be

TOTAL NUMBER OF PART..__ _ _ _ __

LOW L

programmed as INACTIVE (o).

PROGRAM TABLE IL_ REV_ DATE_ __

VARIABLE NAME

~l8l~ISI ~l~l~lgl9lgl~l~l~l~l~l~I ~l~l~l~l~l~l~l~l~l~l;l~l~I ~l~l:Jgl ~I ml~lml~I ~I wl~l~lol~~m~

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Philips Semiconductors Programmable Logic Devices
Programmable logic array (18 x 42 x 10)

SNAP RESOURCE SUMMARY DESIGNATIONS

p~

Po

D9

lll~i· ..18
- I "6--,,!llM1o:~,- - - - + - - - - - - + - - - + -

!

I

I

I

I

Product specification
PLUS153-10

> - - - - -........-oeo

October 22, 1993

202

Phillps Semiconductors Programmable Logic Device·
Programmable logic array (22x42x10)

Product specification
PLS173

DESCRIPTION
The PLS 173 is a two-level logic element consisting of 42 AND gates and 10 OR gates with fusible link connections for programming l/O polarity and direction.
All AND gates are linked to 12 inputs (I) and 10 bidirectional l/O lines (8). These yield
variable 1/0 gate configurations via 1o
direction control gates (D), ranging from 22 inputs to 10 outputs.
On-chip TIC buffers couple either True (I, B) or Complement (l, B) input polarities to all AND gates, whose outputs can be optionally Jinked to all OR gates. Their output polarity, in tum, is individually programmable 1hrough a set of EX-OR gates for implementing AND/OR or AND/NOR logic !unctions.
The PLS173 is field programmable, enabling the user to quickly generate custom patterns using standard programming equipment.
Order codes for this device are listed below.

FEATURES
· 1/0 propagation delay: 30ns (max.) · 12inputs · 42 AND gates · 100Rgates · 10 bidirectional 1/0 lines · Active-High or -Low outputs · 42 product terms:
- 32 logic terms
- 1ocontrol terms
· Ni-Cr programmable links ·Input loading: -100µA (max.) · Power dissipation: 750mW (typ.) · 3-State outputs · TIL compatible

APPLICATIONS
· Random logic · Code converters · Fault detectors · Function generators · Address mapping · Multiplexing

PIN CONFIGURATIONS
NPackage
N · Plastic DIP (300mil·wlda)
A Package 13 12 11 ID Vee B9 88
A - Plastic Leaded Chi> Carrier

ORDERING INFORMATION
DESCRIPTION 24-Pin Plastic Dual-In-Line 300mil-wide
28-Pin Plastic Leaded Chip Carrier

ORDER CODE PLS173N PLS173A

DRAWING N'IMBER 0410D 0401F

October 22, 1993

203

Philips Semiconductors Programmable Logic Devices
Programmable logic array (22 x 42 x 10)
LOGIC DIAGRAM

Product specification
PLS173

89 BS 87 86 85 B4 83 82 81 BO

NOTES:
1. All prograrrrood 'AND' gate locations are pulled to logic ·1". 2. ~!I programmed 'OR' gate locations are pulled to logic ·a". 3. :::::::: Programmable connection.

October 22, 1993

204

Philips Semiconductors Programmable Logic Devices
Programmable logic array
(22 x 42 x 10)
FUNCTIONAL DIAGRAM
Po IO

Product specification
PLS173

@

LOGIC FUNCTION
TYPICAL PRODUCT TERM: Pn:A·ll".C·D· ···
TYPICAL LOGIC FUNCTION: AT OUTPUT POLARITY= H Z:PO+P1 +P2 ···
AT OUTPUT POLARITY + L Z:PO+P1+P2+ .. . Z= J>lj. JS1. J'.! ... .
NOTES: 1. For each of the 1O outputs, either function Z
(Active-High) orZ (Active-Low) is available, but not both. The desired output Polarity is programmed
via the EX-OR gates.
2. zx, A, B, C, etc. are user defined connections to
fixed inputs (I), and bidirectional pins (8).

ABSOLUTE MAXIMUM RATINGS1

RATING

SYMBOL

PARAMETER

Min

Max

UNIT

Vee

Supply voltage

+7

Voe

V1N

Input voltage

+5.5

Voe

VouT

Output voltage

+5.5

Voe

l1N

Input currents

--30

+30

mA

louT Tanti Tstg

Output currents

+100

mA

Operating free-air temperature range

0

+75

oc

Storage temperature range

-S5

+150

oc

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS
TEMPERATURE Maximum junction
Maximum ambient
Allowable thermal rise ambient to junction

150°C 75°C 75°C

The PLS 173 is also processed to military requirements for operation over the military temperature range. For specifications and ordering information, consult the Philips Semiconductors Military Data Handbook.

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic array (22 x 42 x 10)

Product specification
PLS173

DC ELECTRICAL CHARACTERISTICS
0°C s Tami> s +75°C, 4.75 s Vee s 5.25V

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

Input voltage2

V1L

Low

V1H

High

V1c

Clamp3

Output voltage2

Vcc=MIN

Vee=MAX

2.0

Vee= MIN, llN =-12mA

Vol

Low4

VoH

High5

Input current9

Vcc=MIN

loL = 15mA

loH=-2mA

2.4

l1L

Low

l1H

High

Output current

Vcc=MAX V1N = 0.45V V1N= Vee

lo{OFF)

Hi-Z stateB

Vcc=MAX Vour=5.5V

los

Short circuit3· 5, 6

Ice

Vee supply current7

Capacitance

Vour =0.45V

Vour=OV

-15

Vee=MAX

Vee =5V

l1N

Input

V1N =2.0V

Ce

1/0

Ve =2.0V

NOTES:
1. All typical values are at Vee = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time.
4. Measured with inputs V1Lapplied to 111 . Pins 1-5 = OV, Pins 6--10 = 4.5V, Pin 11 = OVand Pin 13 = 10V. 5. Same conditions as Note 4 except Pin 11 = +1OV.
6. Duration of short circuit should not exceed 1 second.
7. Ice is measured with 10 and 11 = OV, and 12 -111 and Bo- 89 = 4.5V. Part in Virgin State.
8. Leakage values are a combination of input and output leakage.
9. l1L and l1H limits are for dedicated inputs only (lo -111 ).

LIMITS TYP1 MAX
0.8 --0.8 -1.2
0.5

-100 40

80

-140

-70

150

170

8 15

UNIT
v v v
v v
µA µA
µA mA mA
pF pF

October 22, 1993

206

Philips Semiconductors Programmable Logic Devices
Programmable logic array (22 x 42 x 10)

Product specification
PLS173

AC ELECTRICAL CHARACTERISTICS
0°C STamb s +75°C, 4.75 s Vee s 5.25V, R1 =4700, R2 = 1kQ

TEST

LIMITS

SYMBOL

PARAMETER

FROM

TO

CONDITION

MIN TYP MAX

UNIT

!po

Propagation delay2

Input±

Output±

CL= 30pF

20

30

ns

loE

Output enable1

Input±

Output-

CL= 30pF

20

30

ns

loo

Output disable1

Input±

Output+

CL= 5pF

20

30

ns

NOTES:
1. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S 1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output voltage of Vr = (VoH -0.5V) with S1 open, and Low-to-High impedance tests are made to the Vr = (VoL + 0.5V) level with S 1 closed.
2. All propagation delays are measured and specified under worst case conditions.

VOLTAGE WAVEFORM
- . -Jl.~ .J_c
~--1~ 1~AL90% Sns~ ~sna
MEASUREMENTS: AU circuit delays are measured at the + 1.5V level ~inputs and outputs, unless otherwise specified.
Input Pulses

TEST LOAD CIRCUIT
'·y'·
INPUTS
NOTE:
C1 and C2 are to bypass Vee to GND.

Vee L___.>

10

By

111 OUT Bw

R1 CL

Bx

Bz

GND

-=

-= OUTPUTS

TIMING DEFINITIONS

SYMBOL

PARAMETER

!po

Propagation delay between

input and output.

loo

Delay between input change

and when output is off (Hi-Z

or High).

foE

Delay between input change

and when output reflects

specified output level.

TIMING DIAGRAM

1.SV l,B

1.SV

+3V

B-l-.J-1.SV-l-,1'1~~:

October 22, 1993

207

Philips Semiconductors Programmable Logic Devices
Programmable logic array (22x42x10)

Product specification
PLS173

LOGIC PROGRAMMING

PROGRAMMING AND

The PLS173 is fully supported by industry

SOFTWARE SUPPORT

standard (JEDEC compatible) PLO CAD

Refer to Section 9 (Development Software)

tools, including Philips Semiconductors

and Section 10 (Third-Party

SNAP, Data 1/0 Corporation's ABELTM, and

Programmer/Software Support) of this data

Logical Devices lncorporated's CUPLTM design software packages.

handbook for addtional information.

I;

All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture formal
PLS173 logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors SNAP PLO design software package.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.

OUTPUT POLARITY - (B)
l L J ACTIVE LEVEL CODE
~ON-~~:~TINGJ H J

x!s

D-u

L ACTIVE LEVEL l CODE J

[ 1 LOW (INVERTING)

_I

AND ARRAY - (I, B)

l,B ,

l,B
l,B

1,B, l , B l,B

1,B ,~B l,B

~B, l , B l,B

,D

I I I STATE INAC11VE1· 2

CODE
0

I l,BSTATE

,D
I I CODE H

I STATE l,B

,D
I I CODE L

,D

I I I STATE DON'T CARE

CODE
-

OR ARRAY - (B)
~ s

~·

VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at "H" polarity.
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.

PnSTATUS ACTIVE I

CODE A

J I [ PnSTATUS

CODE

· L INACTIVE l

J

NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates Pn. Dn.
2. Any gate Pn. Dn will be unconditionally inhibited if both the True and Complement of any input (I, B) are left intact.

ABEL Is atrademarkofData1 0Corp.
CUPL is a trademark of Logical Devlces, Inc.

October 22, 1993

208

Philips Semiconductors Programmable Logic Devices
Programmable logic array
(22 x 42 x 10)

Product specification
PLS173

PROGRAM TABLE

T

AND

E R

8(1)

I

111110887 6543210 187&5432t0 0

w

~ c

2

!

!

d 3 4

a:

j ·

8 9
to
11 t2 t3 14 15

POLARITY
OR 8(0) 9876543210

I

I

I

I

- 1- - - - - 1- ~ ...... ' '

D1
I I I I - - - - - - - - - - - ' > 1--~1--t--t--..._.,___,,__,,__,........ --l_..._..._._._._.-+-+-<--+-+-+-K DO PIN t3 11 10 9 8 7 & 5 4 3 2 t 23 22 21 20 19 18 17 16 15 14 23 22 21 20 19 ta 17 16 15 14

C·'
~:
' ' '

October 22, 1993

209

Philips Semiconductors Programmable Logic Devices
Programmable logic array (22 x 42 x 10)

SNAP RESOURCE SUMMARY DESIGNATIONS

P31

Po

~ll:il,_' D

----+------+---+-

! I I I
111

Product specification
PLS173

so ---t--~---+---1

i'(ffN'fJtiJ
> - + - - - I >----!--,-{) B9

October 22. 1993

210

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (22x42x10)

Product specification
PLUS1738/D

DESCRIPTION
The PLUS173 PLDs are high speed, combinatorial Programmable Logic Arrays. The Philips Semiconductors state-of-the-art Oxide Isolated Bipolar fabrication process is employed to produce propagation delays as short as 12ns.
The 24-pin PLUS173 devices have a programmable AND array and a programmable OR array. Unlike PAL® devices, 100% product term sharing is supported. Any of the 32 logic product terms can be connected to any or all oi the 1O output OR gates. Most PAL ICs are limited to 7 AND terms per OR function; the PLUS173 devices can support up to 32 input wide OR functions.
The polarity of each output is userprogrammable as either Active-High or Active-Low, thus allowing AND-OR or AND-NOR logic implementation. This feature adds an element of design flexibility, particularly when implementing complex decoding functions.
The PLUS173 devices are userprogrammable using one of several commercially available, industry standard PLO programmers.

FEATURES · 110 propagation delays (worst case)
- PLUS173B-15ns max. - PLUS173D-12nsmax. · Functional superset of 20L10 and most other 24-pin combinatorial PAL devices · Two programmable arrays - Supports 32 input wide OR functions · 12 inputs · 10 bi-directional 1/0 · 42 AND gates - 32 logic product terms - 10 direction control terms · Programmable output polarity - Active-High or Active-Low · Security fuse · 3-State outputs · Power dissipation: 750mW (typ.) · TTL Compatible
APPLICATIONS
· Random logic · Code converters · Fault detectors · Function generators · Address mapping · Multiplexing

PIN CONFIGURATIONS
N Package
N = Plastic Dual In-Line (300mil-wide) A Package
13 12 11 IO Vee B9 B8
A= Plastic Leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION 24-Pin Plastic Dual In-Line 300mil-wide 24-Pin Plastic Dual In-Line 300mil-wide 28-Pin Plastic Leaded Chip Carrier 28-Pin Plastic Leaded Chip Carrier

tpo(MAX) 15ns 12ns 15ns 12ns

ORDER CODE PLUS173BN PLUS173DN PLUS173BA PLUS173DA

DRAWING NUMBER 04100 04100 0401F 0401F

®PAL is a registered trademark of Advanced Micro Devices Corporation.

f"'lr>tnhar ')') 100".t

211

853-1298 11164

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (22 x 42 x 10)
LOGIC DIAGRAM
12 13 14
19 110 111

Product specification
PLUS173B/D

89
B8 87 86 BS B4 83 82
B1 BO XO·· 31· ···· ·2423· ···· ·16 15· ····· 8 7 ······ 0
NOTES: 1. All programmed 'AND' gate locations are pulled to logic "1", 2. ~!I programmed 'OR' gate locations are pulled to logic "O". 3..:::::::- Programmable connection.

October 22, 1993

212

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (22 x 42 x 10)

FUNCTIONAL DIAGRAM

P31

PO

10

Product specification
PLUS173B/D

DO

09

111

=

ABSOLUTE MAXIMUM RATINGS1

RATING

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee

Supply voltage

+7

Voe

V1N

Input voltage

+5.5

Voe

Vour

Output voltage

+5.5

Voe

l1N

Input currents

--30

+30

mA

lour

Output currents

+100

mA

lamb

Operating free-air temperature range

0

+75

oc

lstg

Storage temperature range

--B5

+150

oc

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those
indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal rise ambient to junction

150°C 75°C 75°C

213

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (22 x 42x 10)

Product specification
PLUS173B/D

DC ELECTRICAL CHARACTERISTICS ooc sTarr1> s +75°C, 4.75 s Vee s5.25V

LIMITS

SYMBOL

Input voltage2

V1L

Low

V1H

High

Vic

Clamp

Output voltage2

PARAMETER

TEST CONDITIONS
Vcc=MIN Vcc=MAX Vee= MIN, llN = -12mA

MIN TYP1 MAX
0.8 2.·
--0.8 -1.2

UNIT
v v v

Vol

Low"

VoH

High5

Input current9

Vcc=MIN IOL= 15mA loH=-2mA

0.5

v

2.4

v

l1L

Low

l1H

High

Output current

Vcc=MAX V1N =0.45V V1N =Vee

-100

µA

40

µA

IO(OFF)

Hi-Z state8

los

Short circuit3· 5·8

Ice

Vee supply current7

Capacitance

Vcc=MAX VoUT=2.7V Your =0.45V Vour=OV Vee=MAX

80

µA

-140

-15

-70

mA

150

200

mA

Vee=5V

l1N

Input

V1N =2.0V

8

pF

Ce

1/0

Ve =2.0V

15

pF

NOTES:
1. All typical values are at Vee = 5V, Tarr1> = +25"C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a lime.
4. Measured with inputs 10-14 = OV, inputs 15 -19 =·4.5V, 111 = 4.5V and 119 = 10V. For outputs BO- 84 and for outputs BS - 89 apply the same conditions except 111 = OV.
5. Same conditions as Note 4 except input 111 = +10V. 6. Duration of short circuit should not exceed 1 second. 7. Ice is measured with inputs 10 - 111 and BO - 89 = OV. Part in Virgin State. 8. Leakage values are a combination of input and output leakage.
9. l1L and l1H limits are for dedicated inputs only (10 -111 ).

October 22, 1993

214

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (22 x 42 x 10)

Product specification
PLUS173B/D

AC ELECTRICAL CHARACTERISTICS o·c s Tam1i s +75°C, 4.75 s Vrx; s 5.25V, R1=3000, R2 = 3900

LIMITS

SYMBOL PARAMETER

FROM

TO

TEST

PLUS173B

PLUS173D

UNIT

CONDITION MIN TYP MAX MIN TYP MAX

lpo Propagation Delay2 Input+/- Output+/- CL= 30pF

11

15

10 12

ns

toe Output Enable1

Input+/- Output- CL =30pF

11

15

10 12

ns

loo Output Disable 1

Input+/- Output+ CL=5pF

11

15

10 12

ns

NOTES:
1. For 3-State outputs; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output
voltage of Vr = (VoH -0.5V) with S1open, and Low-to-High impedance tests are made to the Vr =(Vol+ 0.5V) level with S1closed. 2. All propagation delays are measured and specified under worst case conditions.

VOLTAGE WAVEFORM

TEST LOAD CIRCUIT

Vee t::_/

INPUTS

In

Bz

In DUT By

R1 CL

IEASUREMENTS: All circuit detays are measured at the +1.SV level d inputs and outputs. unless otherwise specffled.
Input Pulses

NOTE:
C1 and ~ are 1o bypass Vrx; 1o GNO.

By

Bz

GND

....

Test Load Circuit

.... OUTPUTS

TIMING DEFINITIONS

SYMBOL
lpo

PARAMETER
Propagation delay between input and output

loo

Delay between input change

and when output is off (Hi-Z

or High).

toe

Delay between input change

and when output reflects

specified output level.

TIMING DIAGRAM
l,B
B

215

PhiUps Semiconductors Programmable Logic Devices
Programmable logic arrays (22 x 42 x 10)

Product specification
PLUS173B/D

LOGIC PROGRAMMING The PLUS173 series is fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips Semiconductors SNAP design software package. ABELTM and CUPLTMdesign software packages also support the PLUS173 architecture.

PROGRAMMING AND
SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 1O(Third-Party Programmer/ Software Suppon) of this data handbook for · additional information.

All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.

OUTPUT POLARITY -_llll

PLUS173 logicdesigns can also be generated using the program table entry format, which is detailed on the following page. This program table entry format is supported by SNAP only.

To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.

L I J ACTIVE LEVEL
l l J HIGH1
...i.NON-INVERTINGl

CODE H

l j [ ACTIVE LEVEL

CODE

l l (INV~~NG) L

1,8, 1,8 1,8,1,8 1,8,1,8 ANDARRAY- (I,B) l,B

l,B ,~B

~B

l,B

~B

,D
I STATE INACTIVE1· 2

1,8 ,D
STATE

,D
STATE
l,B

,D
STATE DON"TCARE

OR ARRAY - (B)

VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at "H" polarity.
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.

PnSTATUS ACTIVEf.

CODE A

PnSTATUS INACTIVE

CODE
·

NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates P0 , 0 0.
2. Any gate P0 , Dn will be unconditionally inhibited if both the true and complement of any input (I, B) are left intact.

ABEL is a trademark of Data llO Corp. CUPL Is a trademark Of Logk:al Devices, Inc.

October 22, 1993

216

&er
!!l -~

________A_N_D ______

t
'

_ _ _ _ _ _ O_R_ _ _ _ _ _

_

ACTIV~

NOTES 1. The PLA Is shipped with alt !Inks intact. Thus a background

CUSTOMER NAME~~~~~~~~-

~

~~ 1,8(1)

of entries corresponding to states of virgin links exists in the table. (Shown BLANK tor clarity.)
2. Unused I and B bits In the AND array must be programmed

PHILIPS DEVICE#

--"-~ .· ,(POL)

Don't Care (-). 3. Unused product terms can be left blank.

PROGRAM TABLE It__ REV_ DATE _ __

-a
JJ 0 G') JJ
l=>:: j;!
mmr-

VARIABLE NAME

.. lml ... ~l8l~lglgl~lglil~lilil~l~l~l~l~l~I ~l~l~l~l!::!l~l~l;l~l~l~l~l~l~l=lsl

1~1 .. 1... 1w1 .. 1-1otc=m~

~

:

:
cs

. 0

;

I

Im l-l-l-+-+-+-l-l-l-+-+-+-l-l-!-+-+-+-l-l-!-+-+-+-l-l-!-+-+-+-l-l-!-+-+-+-1-1-1-+-+-1--1-..;

-

.~..,,

I

~-
~

-.. ... -... :-:: ~-1-1-~+-+-1-1-1-~+-+-1-1-1-~+-+-1-1-1-~+-+-1-1-1-~+-1--1-1-1-~+-+-1-1-1-~+-l--+-f

. -w

-

.. §ij~0

I- . ~

!!::!1~-1-1-~+-+-1-1-1-~+-+-l-l-!-+-+-+-l-l-!-+-+-+-l-l-!-+-+-+-l-l-f-+-+-+~-1-1-~+-+-+-:; f;

i.;;i~; -l-+-+-+-+-l-l-!-+-+-+-l-l-!-+-+-+-l-l-!-+-+-+-l-l-!-+-+-+-1-1-l-+-+-+~-l-!-+-+~ -+~ ~s

~

~

~
...

:w-
ii
!::1

~--r-tttj=j~++++-~++++-+-~+++-+-~++++_.._....

.

.

.

.
::t:.:.J.

I

~ .

;;;

...

I

. ~
.j-l-+-+-+~-1-f-+-+-+~-f-+-+-+~-l-f-J....j....J.....j_i-.j....j....j....i- ~+-+-+

= 0

~ ~ i!!
:!

.~ .

~

"'

,,

~

-f\) .'".U,
xf\)Q (.Q.,
.j:::i. Ill

-6'
"e'n
"3o'·
0

f\:>3
x 3
...... Ill
-0 aOr'"

"'Q.
c
0
,,6'
iil
a "ii'l

0 3

(Q 3

ff "g':

I....l,,l

5"' '
IQ.

Ill "<
(J)

0
0 ~

fJ'

"'

'"U

c r (.../..).

,,
a
~

-w....J
--OJ
0

~
~"'
£g·

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (22x42x10)

SNAP RESOURCE SUMMARY DESIGNATIONS

Pa1

Po

Dg

~ ~~~~=~~----+-------1--.......--

1
I I I

Product specification
PLUS173B/D

/*'(ilW~/
>-+----I >-----+.---0 Be
. > - - - - - . . - - - < l 11o

nr.tnber 22. 1993

218

Philips Semiconductors Programmable Logic Devices
Programmable logic array (22x42x10)

Product specification
PLUS173-10

DESCRIPTION The PLUS173-10 PLO is a high speed, combinatorial Programmable Logic Array. The Philips Semiconductors state-of-the-art Oxide Isolated Bipolar fabrication process is employed to produce maximum propaga1ion delays of 1Ons or less.
The 24-pin PLUS173-10 device has a programmable AND array and a programmable OR array. Unlike PAL® devices, 100% product term sharing is supported. Any of the 32 logic product terms can be connected to any or all of the 10 output OR gates. Most PAL ICs are limited to 7 AND terms per OR function; the PLUS173-10 device can support up to 32 input wide OR functions.
The polarity of each output is userprogrammable as either Active-High or Active-Low, thus allowing AND-OR or AND-NOR logic implementation. This feature adds an element of design flexibility, particularly when implementing complex decoding functions.
The PLUS173-10 device is userprogrammable using one of several commercially available, industry standard PLO programmers.

FEATURES · 1/0 propagation delays
- 10ns (worst case) · Functional superset of 20L10 and most
other 24-pin combinatorial PAL devices · Two programmable arrays
- Supports 32 input wide OR functions · 12 inputs · 10 bi-directional 1/0 · 42 AND gates
- 32 logic product terms - 10 direction control terms · Programmable output polarity - Active-High or Active-Low · Security fuse · 3-State outputs · Power dissipation: 850mW (typ.) · TTL Compatible
APPLICATIONS · Random logic · Code converters · Fault detectors · Function generators · Address mapping · Multiplexing

PIN CONFIGURATIONS N Package
N .. Plastic Dual ln·Line (300mi1·wide)
A Package
A .. Plastic leaded Chip Carrier

ORDERING INFORMATION DESCRIPTION
24-Pin Plastic Dual In-Line 300mil-wide 28-Pin Plastic Leaded Chip Carrier

lpD(MAX) 10ns 10ns

ORDER CODE PLUS173-10N PLUS173-10A

DRAWING NUMBER 04100 0401F

®PAL Is a registered trademark of Advanced Micro Devices Corporation.

October 22, 1993

219

Philips Semiconductors Programmable Logic Devices
Programmable logic array (22x42x10)
LOGIC DIAGRAM

Product specification
PLUS173-10

89 88 87 86 85 B4 83 82 81 BO
NOTES: 1. All progranmed 'AND' gate locations are pulled to logic ~1·. 2. All programmed 'OR' gate locations are pulled to logic ·rr. 3. -:@ Programmable connection.

October 22, 1993

220

Philips Semiconductors Programmable Logic Devices
Programmable logic array (22x42x10)

FUNCTIONAL DIAGRAM

P31

PO

IO

Product specification
PLUS173-10

DO

09

ABSOLUTE MAXIMUM RATINGS1

RATING

SYMBOL

PARAMETER

Min

Max

UNIT

Vee

Supply voltage

+7

Voe

V1N

Input voltage

+5.5

Voe

Your

Output voltage

+5.5

Vrx;

l1N

Input currents

-30

+30

mA

lour Tarrb

Output currents Operating free-air temperature range

+100.0

mA

0

+75

oc

Tstg

Storage temperature range

-65

+150

oc

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS TEMPERAl"URE
Maximum junction
Maximum ambient
Allowable thermal rise ambient to junction

1so0 c 75°C 75°C

October 22, 1993

221

Philips Semiconductors Programmable Logic Devices
Programmable logic array
(22 x 42 x 10)

Product specification
PLUS173-10

DC ELECTRICAL CHARACTERISTICS 0°C STamb S+75°C, 4.75S VccS5.25V

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN TYP1 MAX

UNIT

Input vollage2

V1L

Low

V1H

High

Vic

Clamp

Vee= MIN

0.8

v

I~

Vee =MAX

2.0

v

Vee = MIN, l1N = -12mA

--0.8 -1.2

v

Output voltage2

VoL

Low4

VoH

High5

Input current9

Vcc=MIN IOL= 15mA loH=-2mA

0.4

0.5

v

2.4

2.9

v

l1L

Low

l1H

High

Output current

Vee= MAX V1N = 0.45V V1N =Vee

-20 -100

µA

1

40

µA

lo(OFF)

Hi-Z state8

los

Short circuit3· 5, 6

Ice

Vcc supply current7

Capacitance

Vee =MAX Vour =2.7V VouT =0.45V Vour=OV Vcc=MAX

0

80

µA

-15 -140

-15

--,'30

-70

mA

170

210

mA

Vcc.=5V

l1N

Input

V1N =2.0V

8

pF

Ca

1/0

Va= 2.0V

15

pF

NOTES:
1. All typical values are at Vee = 5V, Tant> = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time.
4. Measured with inputs 10-14 = OV, inputs 15 -19 = 4.5V, 111 = 4.5Vand 110 = 10V. For outputs BO- B4 and for outputs 05- 09 apply the same conditions except 111 = OV.
5. Same conditions as Note 4 except input 111 = +10V. 6. Duration of short circuit should not exceed 1 second. 7. Ice is measured with inputs 10 -111 and BO- B9 = OV. Part in Virgin State. 8. Leakage values are a combination of input and output leakage. 9. l1L and l1H limits are for dedicated inputs only (10-111).

October 22, 1993

222

Philips Semiconductors Programmable Logic Devices
Programmable logic array (22 x 42 x 10)

Product specification
PLUS173-10

AC ELECTRICAL CHARACTERISTICS 0°C s;Tarro s;+75"C, 4.75s; Vee s;S.25V, R1 =3000, Rp 3900

TEST

LIMITS

SYMBOL

PARAMETER

FROM

TO

CONDITION

MIN

TYP

MAX

UNIT

tpo

Propagation Delay2

Input+/-

Output+/-

CL= 30pF

8

10

ns

loE

Output Enable1

Input+/-

Output-

CL=30pF

8

10

ns

loo

Output Disable1

Input+!-

Output+

CL =5pF

8

10

ns

NOTES:
1. For 3-State outputs; output enable times are tested with CL= 30pF to the 1.5V level, and S1is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = SpF. High-to-High impedance tests are made to an output
voltage of VT= (VoH -0.SV) with S1open, and Low-to-High impedance tests are made to the VT= (Vol+ O.SV) level with S1closed. 2. All propagation delays are measured and specified under worst case conditions.

VOLTAGE WAVEFORM

TEST LOAD CIRCUIT

Vee t:__>

INPUTS

In

Bz

In

DUT

BM

R1 CL

MEASUREMENTS: All circuit delays are measured at the +1.5V lever c:A inputs and outputs, unless otherwise specified.
Input Pulses

NOTE:
e1 and e2 are to bypass Vee to GNO.

BM

Bz

GND

':"

Test Load Circuit

OUTPUTS ':"

TIMING DEFINITIONS

SYMBOL

PARAMETER

lpo

Propagation delay between

input and output.

loo

Delay between input change

and when output is off (Hi-Z

or High).

loE

Delay between input change

and when output reflects

specified output level.

TIMING DIAGRAM
l,B
e

October 22, 1993

223

Philips Semiconductors Programmable Logic Devices
Programmable logic array
(22 x 42 x 10)

Product specification
PLUS173-10

LOGIC PROGRAMMING

PROGRAMMING AND

The PLUS173-10 is fully supported by

SOFTWARE SUPPORT

industry standard (JEDEC compatible) PLD

Refer to Section 9 (Development Software)

CAD tools, including Philips Semiconductors and Section 10 (Third-party Programmer/

SNAP design software package. ABELT· and Software Support) of this data handbook for

CUPLTM design software packages also

additional information.

support the PLUS173-10 architecture.

I~

All packages allow Boolean and state

equation entry formats. SNAP, ABEL and CUPL also accep~ as input, schematic

OUTPUT POLARITY - B

capture format.

PLUS173-10 logic designs can also be generated using the program table entry format, which is detailed on the following page. This program table entry format is supported by SNAP only.

To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE,

COMPLEMENT, INACTIVE, PRESET, etc., are defined below.

l,B 1 AND ARRAY - (I, B) ~8 J,B

1,8 11,B l,B

,D

[ STATE _l CODE j

l l INACTIVE1, 2

0 j

l,BI STATE

,D
I I CODE H

CODE
H

ACTIVE LEVEL LOW
(INVERTING)

CODE
L

l,B11,B 11,B

~B

l,B

l,B

I STATE u

,D
I I CODE L

,D

I I I STATE DON'T CARE

CODE
-

OR ARRAY - (B)

+=>-·

VIRGIN STATE
A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at "H" polarity.
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.

J [ Pn STATUS

CODE j

L ACTIVE1 l A J

~ J l PnSTATUS

CODE j

I INACTIVE ·

NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates Pn. Dn.
2. Any gate Pn. Dn will be unconditionally inhibited if both the true and complement of any input (I, B) are left intact.

ABEL is a trademark of Data 110 Corp. CUPL is a trademark of Logical Devices, Inc.

October 22, 1993

224

Philips Semiconductors Programmable Logic Devices
Programmable logic array
(22 x 42 x 10)

Product specification
PLUS173-10

PLA PROGRAM TABLE

POLARITY

T

AND

OR

E R

B(I)

B(O)

M 11 10 9 8 7 6 5
I
w
!;;:
c

2 1 0 98 7 6 5 4 3 21 0

!

!

:r!

98 7 6 5 4 3 2 10

Jaw:

w :::;:
z<(
a:
w :::;:
~
:::> 0

.
w
>c0w
Ul
:c:C::l:.;.
Cl..

j

w
..J

Cll
~

:::;: 10

a<:(

11

Cl
a0 :

12 13

Cl..

i

!

+ I

!

l

]

!

!

l

!

14

]

1

15

]

16

17

18

]

19

:l:;:

j_

21

i

i

22

23

24

l

25

!

26

:r

j_

27

j_

j_

28 29

+ i

~

'§:''

09

OTI

, ., : 5 1-o_a-+-+-+-+-+-+-+-+----'!--!--!--!--l--+--l--l---l---l---+--+--+--+--lr

.:~t1t1 :g : : : I ·

~~ u~ ~

101 101

~:::c

~

l--+--+--+--+--1---+--l--l--<--l--l--+--+-+->--l--l--l-<----ll--!--!--W 1-0c40~3,-t-t-t-f~~---11--1--l--l--l--+--l-+-+--l--l--l-+---+----+----+-----.~---------' --

D2

' ' _, _____ ,_J ____

01

:

~oo-:--+-+--+-+-!l!-+-+--l-+l-+--+-+-!~-+l--l-+-l-fl-+-+--1-1~~~~~~~~

PIN 13 11 10 9 8 7 6 5 4 3 2 1 23 22 21 20 19 18 17 16 15 14

23 22 21 20 19 18 17 16 15 14

co

o :::c ...1 I

:i;

;>w::
~ m Im
~ ....: 1..:

October 22, 1993

225

Philips Semiconductors Programmable Logic Devices
Programmable logic array
(22 x 42 x 10)

SNAP RESOURCE SUMMARY DESIGNATIONS

P31

Po

Dg

~ ~::~;=----+--------+------t-

1

.. ,_.·..

I I I
I

111

Product specification
PLUS173-10

October 22, 1993

226

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays
(16 x 48 x 8)

Product specification
PLS1OO/PLS101

DESCRIPTION
The PLS100 (3-State) and PLS101 (Open Collector) are bipolar, fuse Programmable Logic Arrays (PLAs). Each device utilizes the standard AND/OR/Invert architecture to directly implement custom sum of product equations.
Each device consists of 16 dedicated inputs and 8 dedicated outputs. Each output is capable of being actively controlled by any or all of the 48 product terms. The True, Complement, or Don't Care condition of each of the 16 inputs and be ANDed together to comprise one P-term. All 48 P-terms can be selectively ORed to each output.
The PLS100 and PLS101 are fully TTL compatible, and chip enable control for expansion of input variables and output inhibit. They feature either Open Collector or 3-State outputs for ease of expansion of product terms and application in bus-organized systems.
Order codes are listed in the Ordering Information Table.

FEATURES
· Field-programmable (Ni-Cr link) · Input variables: 16 · Output functions: 8 · Product terms: 48 · 1/0 propagation delay: 50ns (max.) · Power dissipation: 600mW (typ.) ·Input loading:-100µA (max.) · Chip Enable input · Output option:
- PLS100: 3-State - PLS101: Open-Collector ·Output disable function: - 3-State: Hi-Z - Open-Collector: High
APPLICATIONS
· CRT display systems · Code conversion · Peripheral controllers · Function generators · Look-up and decision tables · Microprogramming · Address mapping · Character generators · Data security encoders · Fault detectors · Frequency synthesizers · 16-bit to 8-bit bus interface · Random logic replacement

PIN CONFIGURATIONS
N Package
Vee

11D

111

112

113

114 115

F7

CE

FD

F5

F1

F4

F2

F3

* Fuse Enable Pin: It is recommended that this pin
be left open or connected to ground during normal operation.
N = Plastic DIP {600mil-wide}

A Package
15 16 17 FE Vee 18 19

110

111

112

113

114

F7

115

F6

F5 F4 GND F3 F2 F1 FD A= Plastic Leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION 28-Pin Plastic Dual In-Line 600mil-wide 28-Pin Plastic Leaded Chip Carrier

3-STATE PLS100N PLS100A

OPEN COLLECTOR PLS101N PLS101A

DRAWING NUMBER 0413D 0401F

Odnh1>r ?? 1993

227

853--0308 11164

Philips Semiconductors Programmable Logic Devices
Progfammable logic arrays {16x48x8)
LOGIC DIAGRAM

Product specification
PLS1OO' /PLS101
I''

NOTES:

1. All AND gate Inputs with a blown link float to a logic "1".

:n 2. All OR gate Inputs wnh a blown fuse f/oal to logic "0".

3.

Programmable connection.

October 22. 1993

228

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (16x48x8)

Product specification
PLS1OO/PLS101

FUNCTIONAL DIAGRAM
~--·_~-+--+---------+~TYPICAL CONNECTION

TYPICAL CONNECTION FO
F6

=

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

PARAMETER

RATINGS

UNIT

Vee

Supply voltage

+7.0

Vrx;

V1N

Input voltage

+5.5

Voe

Vo

Output voltage

+5.5

Voc

l1N

Input current

±30

mA

lour

Output current

+100

mA

Tarro

Operating temperature range

0 to +75

'C

Tstg

Storage temperature range

-S5 to +150

'C

NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other conditions above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS
TEMPERATURE Maximum junction
Maximum ambient
Allowable thermal rise ambient to junction

150°C 75°C 75°C

The PLS100 device is also processed to military requirements for operation over the military temperature range. For specifications and ordering information consult the Philips Semiconductors Military Data Handbook.

October 22, 1993

229

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (16 x 48 x 8)

Product specification
PLS1OO/PLS101

DC ELECTRICAL CHARACTERISTICS 0°C !> Tamb !> +75°C, 4.75V !>Vee!> 5.25V

LIMITS

SYMBOL PARAMETER

Input voltage!

V1H

High

V1L

Low

Vic

Clamp3

TEST CONDITIONS

MIN

TYP1

MAX

UNIT

1'

Vcc=MAX Vee= MIN Vee= MIN, l1N =-12mA

2.0

v

0.8

v

--0.8

-1.2

v

Output voltage!

VoH

High (PLS100)4

Vol

Low5

Input current

Vee= MIN loH=-2mA loL =9.6mA

2.4

v

0.35

0.45

v

l1H

High

l1L

Low

Output current

V1N = 5.5V V1N = 0.45V

< 1

25

µA

-10

-100

µA

lo(OFF)

Hi-Z state (PLS100)

'CE'= High, Vee = MAX Vour= 5.5V

1

40

µA

los

Short circuit (PLS100) 3. 6

Vour= 0.45V 'CE' = Low, Vour = OV

-1

-40

µA

-15

-70

mA

Ice

Vee supply current7

Vee =MAX

120

170

mA

Capacitance

'CE'= High, Vee = 5.0V

C1N

Input

V1N= 2.0V

8

pF

Cour

Output

Vour= 2.0V

17

pF

NOTES:
1. All typical values are at Vee= 5V, Tarro= +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one pin at a time. 4. Measured with Vil applied to 'CE' and a logic high stored. 5. Measured with a programmed logic condition for which the output test is at a low logic level. Output sink current is applied through a resistor
to Vee. 6. Duration of short circuit should not exceed 1 second. 7. Ice is measured with the Chip Enable input grounded, all other inputs at 4.5V and the outputs open.

October 22, 1993

230

Philips Semiconductors Programmable logic Devices
Programmable logic arrays (16x48x8)

Product specification
PLS100/PLS101

AC ELECTRICAL CHARACTERISTICS O"C .s.Tant>S+75"C, 4.75.s. Vees5.25V, R1 =470'2,~=1kn

LIMITS

SYMBOL

PARAMETER

TO

FROM

MIN

TYP1

MAX

UNIT

Propagation delay2

!po

Input

OUtput

Input

35

50

ns

tee

Chip Enable3

Disable time

OUtput

Chip Eneble

15

30

ns

tco

Chip Disable3

OUtput

Chip Eneble

15

30

ns

NOTES:
1. All typical values are at Vee = 5V. Tant> = +25"C. 2. All propagation delays are measured and specified under worst case conditions. 3. For 3-Stale output; output enable times are lesled with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High lests and
closed for high-impedance to Low lests. OUtput disable times are lesled with CL= 5pF. High-to-High impedance tests are made to an output voltage of VT= (VoH -0.5V) with S1 open, and Low-to-High impedance lests are made to the VT= (Vol+ 0.5V) level with S1 closed.

VOLTAGE WAVEFORMS
~ --Ji.~ .J_c

TEST LOAD CIRCUIT
~y~

:__1 -AL=r-~ -l-
llEASUREllENTS: All circuit delays are measured at the+1.5V level of input& and output&, unless otherwise specified.
Input Pulses

INPUTS
NOTE:
e, and Ci are to bypass Vee to GNO.

Yee t:__/

lo

Fo

115 OUT

R1 CL

'CE

F7

GND

....

.... OUTPUTS

TIMING DEFINITIONS

SYMBOL

PARAMETER

tee

Delay between beginning of

Chip Enable Low (with Input

valid) and when Data Output

becomes valid.

!co

Delay between when Chip

Enable becomes High and

Data Output is in off stale

(Hi-Z or High).

!po

Delay between beginning of

valid Input (with Chip Enable

Low) and when Data Output

becomes valid.

TIMING DIAGRAM
---------------+3.0V
INPUT '1-.5V--------------ov
Read Cycle

October 22, 1993

231

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays {16 x 48 x 8)

Product specification
PLS1OO/PLS101

LOGIC PROGRAMMING
PLS100/PLS101 is fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips Semiconductors' SNAP, Data 1/0 Corporation's ABEL'" and Logical Devices lnc.'s CUPLTM design software packages.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
OUTPUT POLARITY - (F)

PLS100/PLS101 logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors' SNAP PLO design software package.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The sumbols for TRUE,

COMPLEMENT, INACTIVE, PRESET, etc., are defined below.
PROGRAMMING AND SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer! Software Support) of this dat handbook for additional informational.

I J [ ACTIVE LEVEL

CODE

l I [ (INV~i~NG)

"AND" ARRAY - (I)
'i:

r T l ACTIVE LEVEL

CODE

J [ (NON~H~~~RTING)l H

'i: '~~:

'i:

t ± 4 STATE INACTIVE1·2

CODE 0

"OR" ARRAY - (F)

I

STATE I

I I CODE H

I

STATE I

I I CODE L

I I I STATE DON'T CARE

CODE
-

l j Pn STATUS

CODE

I l ACTIVE1

A

I Pn STATUS

CODE ]

l · ] INACTIVE

NOTES: 1. This is the initial unprogrammed state of all links. It is normally associated with all unused
(inactive) AND gates Pn. 2. Any gate Pn will be unconditionally inhibited if any one of its (I) link pairs is left intact.

VIRGIN STATE
The PLS100/101 virgin devices are factory shipped in an unprogrammed state, with all fuses intact, such that: 1. All Pn terms are disabled (inactive) in the
AND array.
2. All Pn terms are active in the OR array.
3. All outputs are Active-High.
ABEL Is a trademark of Data 1/0 Corp. CUPL is a trademark of Logical Devices, Inc.

October 22, 1993

232

~

CUSTOMER NAME

er

~

PURCHASE ORDER #

!"'>'

PHILIPS DEVICE#

CF(XXXXl

""co''

CUSTOMER SYMBOLIZED PART#

TOTAL NUMBER OF PARTS

INPUT VARIABLE

PROGRAM TABLE ENTRIES OUTPUT FUNCTION

Prod. Term

Prod. Term Not

Im

Im Don't Care Present in Fp

Present in Fp

H

l

-(dash)

A

· (period)

NOTE Enter{-) for unused inputs

NOTES 1. Entries independent of output polarity.

"C

JJ

OUTPUT ACTIVE LEVEL

0
G)

Active High

Active Low

JJ
s)>:

H

l ii!

NOTES 1. Polarity programmed once only.

m m r

PROGRAM TABLE#

REV _ _ DATE _ _ _ of used P-terms.

2. Enter (A) for unused outputs of used P-terms.

2. Enter (H) for all unused outputs.

.... . . VARIABLE ~i ~ ill ll: t fl fl :: $ ill ~ !:l 8l bl~ !:l f:! !:! !!! Ill ~ ~ tll ~ ~ tl ::l ~ ~ NAME

... ., '" "'" - 0 <O .. ... ., '" "'" - 0 J:;am-i

~

;:;; I

~

:;: I

::l

.: ]

tl

;;; I

~

:::J

tl1

tll

~

~

"

."'

"' .,
....

<O

i5 I

"'J ,.. z

co I

"cC:l
-i

z
0

"j [

., I

'"I
"]
"'I
"J
-I
o}

;";Cr.l
-...... .".".',O -[

Oxl c0..o.,
~m

(/)
Cl>
3r;·
0

xCX>3

:::>
"c:-

3

0
0

CX>ll> Ol

a - Q : "Cl CD co

c0o

iil 3 3

"' ()" !2:

m......,, m
'<

Cl> r 0
~-
0 Cl>

(/) 5·

~

."er.".n'.O..
0 0....__
e."r.".n.'O.. ~"' Q .
0...... "a£"· :::>

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays (16 x 48 x 8)
SNAP RESOURCE SUMMARY DESIGNATIONS

Product specification
PLS1OO/PLS101
,,,

October 22, 1993

234

Programmable Logic Devices

Section 5
Programmable Logic Sequencer Devices

PLS155 PLS157 PLS159A PLS167/A PLS168/A PLS179 PLC42VA12 PLC41S-16 PLS105/A PLUS105-45 PLUS105-55 PLUS105-70 PLUS405-37/-45 PLUS405-55

CONTENTS
Programmable logic sequencer (16 x 45 x 12); 14MHz ....... 237 Programmable logic sequencer (16 x45 x 12); 14MHz ....... 249 Programmable logic sequencer (16 x45 x 12); 18MHz ....... 261 Programmable logic sequencer (14 x 48 x 6); 14, 20MHz ..... 273 Programmable logic sequencer (12 x 48 x 8); 14, 20MHz ..... 285 Programmable logic sequencer (20 x 45 x 12); 18MHz ....... 297 CMOS programmable multi-function PLO (42 x 105 x 12); 25MHz 309 CMOS programmable logic sequencer (17 x 68 x 8); 16MHz .. 329 Programmable logic sequencer (16 x 48 x 8); 14, 20MHz ..... 348 Programmable logic sequencer (16 x 48 x 8); 45MHz ........ 360 Programmable logic sequencer (16 x 48 x 8); 55MHz ........ 373 Programmable logic sequencer (16 x 48 x 8); 70MHz ........ 386 Programmable logic sequencer (16 x 64 x 8); 37, 45MHz ..... 399 Programmable logic sequencer (16 x 64 x 8); 55MHz ........ 415

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x45x12)

Product specification
PLS155

DESCRIPTION
The PLS155 is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K flip-flops are dynamically convertible to D-type via a "fold-back" inverting buffer and control gate Fe. It features 4 registered 1/0 outputs (F) in conjunction with 8 bidirectional 1/0 lines (8). These yield variable 1/0 gate and register configurations via control gates (D, L) ranging from 16 inputs to 12 outputs.
The AND/OR arrays consist of 32 logic AND gates, 13 control AND gates, and 21 OR gates with fusible link connections for programming 1/0 polarity and direction. All AND gates are linked to 4 inputs (I), bidirectional 1/0 lines (B), internal flip-flop outputs (Q), and Complement Array output
(t'). The Complement Array consists of a
NOR gate optionally linked to all AND gates for generating and propagating complementary AND terms.
On-chip TIC buffers couple either True (I, B,
Q) or Complement (T, 'B, 0, ~) input polarities
to all AND gates, whose outputs can be optionally linked to all OR gates. Any of the 32 AND gates can drive bidirectional 110 lines (B), whose output polarity is individually programmable through a set of Ex-OR gates for implementing AND-OR or AND-NOR logic functions. Similarly, any of the AND gates can drive the J-K inputs of all flip-flops. The Asynchronous Preset and Reset lines (P, R), are driven from the OR matrix.
All flip-flops are positive edge-triggered and can be used as input, output or 1/0 (for interfacing with a bidirectional data bus) in conjunction with load control gates (L), steering inputs (I), ( B), (Q) and programmable output select lines (E).
The PLS155 is field programmable, enabling the user to quickly generate custom patterns using standard programming equipment.
Order codes are listed below.

FEATURES · IMAX = 14MHz
- 18.2MHz clock rate · Field-Programmable (Ni-Cr link) · 4 dedicated inputs · 13 control gates · 32 AND gates · 21 OR gates · 45 product terms:
- 32 logic terms - 13 control terms · 8 bidirectional 1/0 lines · 4 bidirectional registers · J-K, T, or D-type flip-flops · Asynchronous Preset/Reset · Complement Array · Active-High or -Low outputs
· Programmable 'OE control
· Positive edge-triggered clock ·Input loading:-100µA (max.) · Power dissipation: 750mW (typ.) · TTL compatible · 3-State outputs
APPLICATIONS
· Random sequential logic · Synchronous up/down counters · Shift registers · Bidirectional data buffms · Timing function generators · System controllers/synchronizers · Priority encoder/registers

PIN CONFIGURATIONS

N Package

Vee
87

86

F3

F2

F1

FO

85

B4

GND

OE

N = Plastic Dual In-Line Package (300mil-wide)

A Package 11 10 CLKVcc 87
86 F3 F2 F1 BO
03 GND OE 84 85 A= Plastic Leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Dual In-Line Package (300mil-wide) 20-Pin Plastic Leaded Chip Carrier

ORDER CODE PLS155N PLS155A

DRAWING NUMBER 0408D 0400E

October 22, 1993

237

853--031711164

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 45 x 12)

Product specification
PLS155

LOGIC DIAGRAM
· · e - - - - - - - (LOGIC TERMS-1) - - - - - · · - - - - - - - - (CONTROL TERMS) - - - - - - ·

31······2423· · · · · ·16 15· · · · · · 8 7 · · · · · · 0 Fe
NOTES: 1. All OR gate inputs with a blown link float to logic "O". 2. All other gates and control Inputs with a blown Rnk float to logic ·1 ·· 3. e denotes WIRE-OR.
4. 4' Programmable connection.

October 22, 1993

238

CK'o-o--<>----<12] CLK

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 45 x 12)
FUNCTIONAL DIAGRAM
(LOGIC TERMS)

(CONTIIOL TERMS) L L D

Product specification
PLS155

cKo----<:}--0 CLK

FLIP-FLOP TRUTH TABLE
m: L CK p R J K Q F

H

Hi-Z

L x x HLxxH L

L x x L Hx xL H

L L i L L L La 0

L L i L LLHL H

L L i L LHLH L
L L i L L H H0 a

H H i L L L H L H*

H Hi
+10V x i x i

L L H L H L·
x x L H L w· x x H L H L..

NOTES: 1. Positive Logic:
J-K=To+ T1 +T2 ·...·............. T31 Tn = ~- (lo· 11 · 12 .··) · (Oo · 01 .·.) · (Bo· B1 · ...)
2. i denotes transition from Low to High level. 3. X = Don't care
4. · = Forced at Fn pin for loading the J-K flip-flop in the Input mode. The load
control term, Ln must be enabled (HIGH)
and the p-terms that are connected to the
associated flip-flop must be forced LOW (disabled) during Preload.
5. At P = R = H, Q = H. The final state of Q depends on which is released first.
6. · · = Forced at Fn pin to load J-K flip-flop independent of program code (Diagnostic
mode), 3-State B outputs.

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x45x 12)

LOGIC FUNCTION

I I I J: I ~ Q3 Q2 Qt QO 10 1

PRESENTSTATE

STATE REGISTER

Ji· IJ · C · ···

I I I I tt Bn+t 0 0 0

NEXTSTATE

SETQo:Jo:(C)a· lJ:!·01·tloJ·)(·IJ·C ...
Ko=D
RESET01:J1 ·D Kt =(1>3·"02' 0t ·tloJ ·Ji ·IJ· C ...
HOLD Oz: J2 =0
Kz1;0
TOGGLEQ3: J3= (C)a · ?J:! · 0t · lJol ·ll" · IJ · C ··· K3=(C)a·?J:! · 01 · tioJ ·ll"· IJ · C ···

NOTE: Similar logic functions are applicable for D and T mode flip-flops.

VIRGIN STATE The factory sllipped virgin device contains all fusible links intact, such !hat: 1. OE is always enabled.
2. Preset and Reset are always disabled.
3. All transition terms are disabled.
A. All flip-flops are in 0-mode unless otherwise programmed to J-K only or J-K or D (controlled).
5. All B pins are inputs and all F pins are outputs unless otherwise programmed.

THERMAL RATINGS

TEMPERATURE

Maximum junction

1so·c

Maximum ambient

75·c

Allowable thermal rise ambient to junction

75°c

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL

PARAMETER

Min

Max

UNIT

Vee

Supply voltage

+7

Voe

V1N Vour

Input voltage Output voltage

+5.5

Voe

+5.5

Voe

l1N

Input currents

-30

+30

mA

lour

Output currents

Tami>

Operating temperature range

+100

mA

0

+75

°C

T!!!t.

Storage temperature range

-65

+150

°C

NOTES:

1. Stresses above !hose listed may cause malfunction or permanent damage to !he device. This

is a stress rating only. Functional operation at lhese or any olher condition above those

indicated in the operational and programming specification of the device is not implied.

Product specification
PLS155
I'

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x45x12)

Product specification
PLS155

DC ELECTRICAL CHARACTERISTICS
0°c sTarro s +75°C, 4.75V s Vee s 5.25V

SYMBOL

Input voltage2

V1H

High

V1L

Low

Vic

Clamp

Output voltage2

PARAMETER

TEST CONDITION
Vcc=MAX Vee= MIN Vee= MIN, l1N = -12mA

VoH

High

VoL

Low

Input currents

Vee= MIN IOH=-2mA loL= 10mA

Vcc=MAX

l1H

High

V1N =5.5V

l1L

Low

Output current

V1N =0.45V

lo(OFF)

Hi-Z states, s

Vcc=MAX Vour =5.5V

VouT =0.45V

los

Short circuit3· 7

Ice

Vee supply current4

Capacitance

VouT =OV Vee= MAX

Vee=5.0V

C1N

Input

V1N =2.0V

Gour

Output

Vour=2.0V

NOTES:

1. All typical values are at Vee = 5V, Tarro = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time.
4. Ice is measured with the OE input grounded, all other inputs at 4.5V and the outputs open.
5. Leakage values are a combination of input and output leakage.
6. Measured with V1H applied to OE. 7. Duration of short circuit should not exceed 1 second.

LIMITS MIN TYP1 MAX
2.0 0.8
-0.8 -1.2

UNIT
v v v

2.4

v

0.35

0.5

v

<1

80

µA

-10

-100

µA

1

80

µA

-1

-140

µA

-15

-70

mA

150

190

mA

8

pF

15

pF

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 45 x 12)

Product specification
PLS155

AC ELECTRICAL CHARACTERISTICS 0°C s Tami> s +75°C, 4.75V s Vee s 5.25V, R1 =470Q, R2 = 1kQ

LIMITS

SYMBOL

PARAMETER

FROM

TO

TEST CONDITION MIN TYP1 MAX UNIT

Pulse width

I'

icKH

Clock2 High

CK+

CK-

CL= 30pF

25

20

ns

icKL

Clock Low

CK-

CK+

CL= 30pf

30

20

ns

icKP

Period

CK+

CK+

CL= 30pf

70

50

ns

lrRH

Preset/Reset pulse

(1,8)-

(l,B)+

CL= 30pF

40

30

ns

Setuptime5

t1s1

Input

(l,B)±

CK+

CL= 30pF

40

30

ns

t1s2

Input (through Fn)

F±

CK+

CL= 30pF

20

10

ns

Input (through

t1s3

Complement Array)4

(l,B)±

CK+

CL= 30pF

65

40

ns

Hold time

l1H1

Input

t1H2

Input

Propagation delays

(l,B):t

CK+

CL= 30pF

0

-10

ns

F±

CK+

CL= 30pF

15

10

ns

icKO

Clock

CK+

F±

CL= 30pF

25

30

ns

loE1

Output enable3

OE-

F-

CL= 30pF

20

30

ns

loo1

Output disable3

OE+

F+

CL= 5pF

20

30

ns

lpo

Output

(l,B)±

B±

CL= 30pF

40

50

ns

loE2

Output enabJe3

(l,B)+

B±

CL= 30pF

35

55

ns

too2

Output disabfe3

(l,B)-

B+

CL= 5pF

30

35

ns

tpRO

Preset/Reset

(l,B)+

F±

CL= 30pF

50

55

ns

NOTES:

1. All typical values are at Vee= 5V, Tamb = +25°C.
2. To prevent spurious clocking, clock rise time (10% -90%) .s 10ns.

3. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output
voltage of VT= (VoH -0.5V) with S 1open, and Low-to-High impedance tests are made to the VT= (Vol+ 0.5V) level with S1 closed. 4. When using the Complement Array icKP = 95ns (min). 5. Limits are guaranteed with 12 product terms maximum connected to each sum term line. 6. For test circuits, waveforms and timing diagrams see the following pages.

VOLTAGE WAVEFORMS

TEST LOAD CIRCUIT

MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses

c1yc2
INPUTS
NOTE: C1 and C2 are to bypass Vee to GND.

L > Vee

R1

OE

lo

By

In DUT Bw

R2

CL

Bx Bz
CLK GND

OUTPUTS '=

'=

October 22, 1993

242

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 45 x 12)
TIMING DIAGRAMS
1,B
~NPUTS)
CK
F (OUTPUTS)
Flip-Flop Outputs

B (OUTPUTS)

Gate Outputs

Product specification
PLS155

TIMING DEFINITIONS

SYMBOL PARAMETER

lcKH

Width of input clock pulse.

lcKL

Interval between clock pulses.

lcKP

Clock period.

IPRH

Width of preset input pulse.

Required delay between

l1s1

beginning of valid input and

positive transition of clock.

Required delay between

beginning of valid input forced

t1s2

at flip-flop output pins, and

positive transition of clock.

Required delay between

t1H1

positive transition of clock and

end of valid input data.

Required delay between

ov

positive transition of clock and

t1H2

end of valid input data forced

at flip-flop output pins.

lcKO

Delay between positive transition of clock and when
outputs become valid (with
OE' Low).

Delay between beginning of

loE1

Output Enable Low and when

outputs become valid.

Delay between beginning of

Output Enable High and

loo1

when outputs are in the

OFF-State.

Propagation delay between

!po

combinational inputs and

outputs.

Delay between predefined

Output Enable High, and

loE2

when combinational outputs

become valid.

Delay between predefined

Output Enable Low and when

loo2

combinational outputs are in

the OFF-State.

lpRO

Delay between positive transition of predefined Preset/Reset input, and when flip-flop outputs become valid.

October 22, 1993

243

Philips Semicondudors Programmable Logic Devices
Programmable logic sequencer (16 x 45 x 12)
TIMING DIAGRAMS (Continued)

CLK
*PRESET RESET
p, BINPUTS)

Ona MN.

Q

F (OUTPUTS;.)-----------.J

___ voH
1.SV
---voL

·The leading edge of preset/reset must occur only when the Input clock is ·low", and must rerraln "high· as long as required to override clock. The falling edge of preset/reset can never go ·low'' when the Input clock Is "high".

Asynchronous Preset/Reset

~B (LOAD SELECT)

1.SV

+3V
1.SV
ov

llE

I.SY

L

+3V
ov
', '--

F PNPUTS)

+3V YOH OV VOL

+3V CLK
'<:KH ~Ht
Q~~~~~~==

Flip-Flop Input Mode

October 22, 1993

244

Produd specification
PLS155
I·

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x45x12)

Product specification
PLS155

LOGIC PROGRAMMING The PLS155 is fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips' Semiconductors SNAP, Data 1/0 Corporation's ABELT· and Logical Devices lnc.'s CUPL"' design software packages.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.

PLS 155 logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors SNAP PLO design software package only.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE,

COMPLEMENT, INACTIVE, PRESET, etc., are defined below.
PROGRAMMING AND SOFTWARE SUPPORT Reier to Section 9 (Development Software)
and Section 1o (Third-party Programmer/
Software Support) of this data handbook for additional information.

"AND" ARRAY - (I), (8), (Qp)

¢'" ¢"" ¢'" '"··¢'"'. l,B,Q

--- LB,O I, B,Q

___ 1,8,Q l,B,Q

--1,8,Q

1,8,Q

(T, Fe. 1.., P, R, D)n

L l J STATE

CODE

I J [ INACTIVE1· 2

o

(T, Fe. 1.., P, R, D)n

I

STATE l,B,Q

I I CODE H

"COMPLEMENT" ARRAY - (C)
c:t: c:t:

<Tn. Fe)

l l J ACTION

CODE

J J [ INACTIVE1·3. 5

0

[

ACTION

L GENERATE5

(T,.Fcl
I J CODE l AJ

"OR" ARRAY - (F-F CONTROL MODE)

("I; Fe. I.., P, R, Dln

I I I STATE

CODE

1.e.o

L

c:t:

(T,.Fcl

[

I J ACTION

CODE

l l · J PROPAGATE

(T, Fe, I.., P, R. llln

I I - I STATE DON"TCARE

CODE

c:t:

(Tn,Fc)

[

ACTION

J CODE]

L l - J TRANSPARENT

L I J ACTION
I J [ (COJN-TKROORLLDED)

CODE A

Notes on following page.

ACTION J-K

CODE
·

October 22, 1993

245

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (t6x45x 12)

Product specification
PLS155

= "OR" ARRAY -(Qn D-Type)

+~ -DlQ LI. Tn

Q

i'

TnSTATUS ACTIVE(Set)

CODE A

Tn STATUS INACTIVE (lleaet)

CODE ·

= "OR" ARRAY - (Qn J·K Type)

Tn Q

~Q Tn
Q

Q

-H3=lLi

ACTION TOGGLE

ACTION SET

"OR" ARRAY- (Sor B), (P), (R)

CODE H

ACTION RESET

CODE L

"EX-OR" ARRAY - (B)

ACTION HOLD

CODE

~IP,R,S 1.-/

(ORB)

~IP,R,S 1.-/

(ORB)

[ TnSTATUS L ACTIVE1

I J CODE l AJ

"OE" ARRAY - (E)
~~

[ l j TnSTATUS

CODE

l l · J INACTIVE

~~

POLARITY LOW

CODE

'~~

POLARITY HIGH

CODE H

~~

En

En

En

I

ACTION IDLE1· 4

I I CODE 0

[ I J ACTION

CODE

l 1 J CONTROL

A

I ACTION ENABLE4

I I CODE ·

I

ACTION DISABLE

NOTES: 1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates. 2. Any gate (T, Fe. L, P, R, D)n will be unconditionally inhibited if both of the I, B, or Q links are left intact. 3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn· Fe.
4. En = 0 and En = · are logically equivalent states, since both cause Fn outputs to be unconditionally enabled. 5. These states are not allowed for control gates (L, P, R, D)n due to their lack of "OR" array links.

En
I I CODE -

October 22, 1993

246

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 45 x 12)

Product specification
PLS155

PROGRAM TABLE

- - - - - - AND - - -Tr:- - - -OR- - - - 1 T - - - - - -C-ONT-RO-L - - - - -1!

INACTIVE I B Q
1B a

IIJ_

0 H L

l J l J I ACTIVE J_ A P. R, B(O) I JIK J_ · F/F

I ·] I I, B(I), I [INACTIVE

(Q · D) I JIK or D A]MODE IDLE

I o

Q(P) I

I ("""°'""U

CONTROrJ_ A

I I I

DON'T CAREJ_ _

I

I

ENABLE I · EA, BI

NOTES 1. Thodovico is shipped wah all links intacl. Thus aback-
ground of entries corresponding to states of virgin links exists in tho table, shown BLANK.lo'. clarity.
=;';:)'.':, 2- Program unused c. I, B, and a b~s ·.n tho AND array as (-). ';~~~· P, and R bits in tho OR array as(-)

I o INACTIVE I GENERATE A
PROPAGATE j_ ·
I - TRANSPARENT

I

c

I I TOGGLE 0

I 1 SET

H

I - 1 RESET J_ L
i HOLD

I I
I HIGH 10 _ J/K) 1 _ LOW
1 ..l

IH I L (POL)

DISABLE J_ FIF MODE

I 3. Unused Terms can be Iott blank. I a a 4. (P) and (N) are respectively the present and next states ..l of flip-flops a.

Ee EA

POLARITY
l

T

AND

4I E
A

C1--..-~'-.--+-.--.--.--B(l~)....,......,.....,....-+-...,....~....-"P)-.--I

M

3 2 1o1, s

3 2 , o3 2 , o

OR

~N)

p

R

3 2 1 0 BABA7 6 5

8(0) 2 1 0

o

T

I

1

T

I

=II:

w aw:

:iE
zC(

aQ : 0

aw: ewn

e:iE

C(
:c

en 0a:

:::> :::>

0 0.

2

_l

...J_

3

J_

J_

4

I

J_

5

I

I

7

:

T

8

i

9

i

j_

10

I

tt

I

12

I

Q
w

I

>
jjj
a0 w : w

~z 14

_J_

1--1=5 ---t--t--t--1--1--11--11--11--J1_--'f-11--11--1-t-+-+-+-l

w l-'1~6-+--+--+--+--+--+--+--1--1-~l--l--l-+-t-+-+-+-l

::iE!Et-1-1---+--t-+-lr-+-t--+--t-t-TI +-lr-+-t-+-t-+--+-,

T

!CC 0 1--'8'--t--t--1--1--1--11--11--11--11--1:1--11--1-t-t-+-+-+-l

Q 0 19

j_

T

20

j_

I

21

j_

j_

22

I

23

I

J_

24

I

W 0-2--5 0--0---+-+-+-+-+-+-+1-+-+-+-+-+-+-+-1

!CC t---t--t---+-+-+-+-+--1--1---t-+-+-+-+-+-+-t

T

IQ l-'28"--1-t--+-+-+-+--+--+--+-4_1_-t-+-+-t--+--+--+--i

~

i

T

,__28_,__,__,___,,___,-+-+-+--l--il-4-4-4-+-+-+-+-I

> 29

I

l-'30'--t--1--1--11--11--11--11--1--t---t,--t--t-+-t-+-t-+-l

..l

Ii:! l-"31=---t--t--l--ll--lf-11--1r-lr-lr-l!r-lr-l-t-t-t-t-t-I

af!:!
~
IL
0

I l--F-e "~-t--t--1---+--t--1--t-It--1-~J_-+-+--+-+-+--+-+-~t--~~
=wII: t--DL1=A-+--+--+--+--+--+--+--+--+-T-~1___,___,___,_,-+-+-+--m c --------~

maw:

m...J D6

T

t----11--11--11--11--11--11--1--t--t--t--t-+-+-t-+-+-+--c

~ D5

------------~

:iE
:z::>
...J
e ~

:!Et-=-~'-+-l--+-+-+-41-+-+--+-~J_-+-l--+-+-+-1-+--C

C( D3

j

m------------~

0Ca:J

t

-

-D-2 D1

l

-

t-+-+-+-

-

t

-

-

+

-

-

+

-

-

+

-

--i~I-

+-

+

-

+

-

-

t

-

-

1

-

-

1

-

-

t

-

C-: --------------~

If l--DO-Pl-'N'-11--5-+-4-+-3-+-2-+-1-19-184-134-12-i~-94-84-7-1-6-1-17-i-16-i-15-l-1-4~

October 22, 1993

247

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 45 x 12)

SNAP RESOURCE SUMMARY DESIGNATIONS

(LOGIC TERMS)

(CONTROL TERMS)

~:mai1'1----+----------+--+L---L lr-

Product specification
PLS155
B

CK

October 22, 1993

248

Phillps Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x45x12)

Product specification
PLS157

DESCRIPTION The PLS157 is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K flip-flops are dynamically convertible to D-type via a 'fold-back" inverting buffer and control gate Fe. It features 6 registered 1/0 outputs (F) in conjunction with 6 bidirectional 1/0 lines (B). These yield variable 110 gate and register configurations via control gates (D, L) ranging from 16 inputs to 12 outputs.
The AND/OR arrays consist of 32 logic AND gates, 13 control AND gates, and 21 OR gates with fusible link connections for programming 110 polarity and direction. All AND gates are linked to 4 inputs (I), bidirectional 110 lines (B), internal flip-flop outputs (0), and Complement Array output ("C°). The Complement Array consists of a NOR gate optionally linked to all AND gates for generating and propagating complementary AND terms.
On-chip TIC buffers couple either True (I, B, OJ or Complement (T, B, 0, "C"J input polarities to all AND gates, whose outputs can be optionally linked to all OR gates. Any of the 32 AND gates drives bidirectional 110 lines (B), whose output polarity is individually programmable through a set of Ex-OR gates for implementing AND-OR or AND-NOR logic functions. Similarly, any of the 32 AND gates can drive the J-K inputs of all flip-flops. The Asynchronous Preset and Reset lines (P, R), are driven from the AND array for 4 of the B registers. The Preset and Reset lines (P, R) controlling the lower four registers are driven from the OR matrix.
All flip-flops are positive edge-triggered and can be used as input, output or 1/0 (for interfacing with a bidirectional data bus) in conjunction with load control gates (l), steering inputs (I), (B), (Q) and programmable output select lines (E).
The PLS157 is field programmable, enabling the user to quickly generate custom patterns using standard programming equipment.
Order codes are listed below.

FEATURES e IMAX= 14MHz
- 18.2MHz clock rate · Field-Programmable (Ni-Cr link) · 4 dedicated inputs · 13 control gates · 32 AND gates · 21 OR gates · 45 product terms:
- 32 logic terms - 13 control terms · 6 bidirectional 1/0 lines · 6 bidirectional registers · J-K, T, or D-type flip-flops · 3-State outputs · Asynchronous Preset/Reset · ComplementArray · Active-High or -Low outputs · Programmable OE control · Positive edge-triggered clock ·Input loading:-100µA (max.) · Power dissipation: 750mW (typ.) · TTL compatible
APPLICATIONS · Random sequential logic · Synchronous up/down counters · Shilt registers · Bidirectional data buffers · liming function generators · System controllers/synchronizers · Priority encoder/registers

ORDERING INFORMATION DESCRIPTION
20-Pin Plastic Dual In-Line Package (300mil-wide) 20-Pin Plastic Leaded Chip Carrier

ORDER CODE PLS157N PLS157A

PIN CONFIGURATIONS NPackage
Vee 85 FS F4
F3 F2 F1 FO B4 GND N - Plastic Dual ln~Line Package (300mil-wide)
A Package
11 IO CLKVcc BS FS F4 F3 F2 F1
83 GND OE B4 FO A · Plastic Loaded Chi> Carrier
DRAWING NUMBER 04080 0400E

October 22, 1993

249

853-0318 11164

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 45 x 12)

Product specification
PLS157

LOGIC DIAGRAM

··>------- m - - - - - - - (LOGIC TERMS-1) - - - - - · ·

(CONTROL TERMS) - - - - - - - -

I*

31······2423· · · · · ·16 15· · · · · · 8 7 · · · · · · 0 Fe

NOTES: 1. All OR gate lnpulB with a blown link float to logic "0". 2. All other gates and control Inputs with a blown link float to logic "1"'. 3. e denotes WIRE-OR.
4. · Programmable connection.

October 22, 1993

250

--4---m Cl('o-·

CLK

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 45 x 12)

FUNCTIONAL DIAGRAM

(LOGIC TERMS)

(CONTROL TERMS)

PR L

L

D

lo<S='+-~-+~+-~~~~~~--1~+---1~--1~-t-i

h<"-+-~-+~+-~~~~~~--t~+---t~--1~--t-b

b

i-o-+-~-+~+-~~~~~~--t~-t---t~-;~--;-6

Product specification
PLS157
=

VIRGIN STATE The factoiy shipped virgin device contains all fusible links intact such that: 1. OE is always enabled.
2. Preset and Reset are always disabled.

3. All transition terms are disabled.
4. All flip-flops are in 0-mode unless otherwise programmed to J-K only or J-K or D (controlled).
5. All B pins are inputs and all F pins are outputs unless otherwise programmed.

LOGIC FUNCTION

I~ I~ I~\~ ~R I

PRESENT STATE

STATE REGISTER

ll: · B · C · · · ·

I I I I 0 0 0 l t Sn+t NEXTSTATE

SET<lg:Jo=l<l:I· tJ:i·01·1Jol·ll:·B·C ··· Ko=O
RESETO,:J1 .o
Kt =(Cl:!' 02 · 01 · lJo) ·ll:· B· C ·.·
HOLD02:J2·0 K2·0
TOGGLEO:i: Jp(03·tJ:i·01 ·lJo)·ll:·B·C ···
K3 -C03· Oz· Ot ·lJo) · ll:·B· C ·.·

NOTE: Similar logic functions are applicable for D and T mode flip-flops.

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 45 x 12)

Product specification
PLS157

FLIP-FLOP TRUTH TABLE

OE

L

CK

p

R

J

.K

Q

F

H

Hl·Z

L

x

x

HL xxH

L

L

x

x

L HxxL

H

L

L

't

L

L

L

L

a

0

L

L

't

L

L

L

H

L

H

L

L

't

L

L

H

L

H

L

L

L

't

L

L

H

H 0

a

H

H

't

L

L

L

H

L

H*

H

H

't

L

L

H

L

H

L*

+10V

x

't

xxL H L

H**

x

't

xxH L H

L* ·

NOTES:
1. Positive Logic: J-K =Tu+ T1+ T2 ··..····.··..·.·.· Ts1
TQ = C· (lo· 11 · ll! ,··) · (Oo · 01 .··) · (Bo· 81 · ...)
2. 't denotes transition from Low to High level.
3. X =Don't care
4. · = Forced at Fn pin for loading the J-K flip-flop in the Input mode. The load control term, Ln must be enabled (HIGH) and the p-terms that are connected to the associated flip-flop must be forced LOW (disabled) during Preload.
5. At P = R = H, Q = H. The final state of Q depends on which is released first. 6. · · = Forced at Fn pin to load J-K flip-flop independent of program code (Diagnostic mode),
3-State B outputs.

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee

Supply voltage

+7

Vrx;

V1N

Input voltage

+5.5

Vrx;

Vour

Output voltage

+5.5

Vrx;

l1N

Input currents

-30

+30

mA

lour

Output currents

Tamb

Operating temperature range

+100

mA

0

+75 ..

"C

Tsig

Storage temperature range

-65

+150

"C

NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal rise ambient to junction

150°C 75°C 75°C

October 22, 1993

252

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 45 x 12)

Product specification
PLS157

DC ELECTRICAL CHARACTERISTICS
0°C s Tarm S +75°C, 4.75V s Vee s 5.25V

SYMBOL

PARAMETER

Input voltage2

V1H

High

V1L

Low

Vic

Clamp

Output voltage2

VoH

High

VOL

Low

Input current

TEST CONDITION
Vcc=MAX Vee= MIN Vee= MIN, l1N =-12mA
Vee= MIN IOH=-2mA loL = 10mA

l1H

High

l1L

Low

Output current

lo( OFF)

Hi-Z states. 6

V1N =5.5V V1N =0.45V
Vcc=MAX Vour=5.5V

Vour=0.45V

los

Short circuit3· 7

Ice

Vcc supply current4

Capacitance

Vour =OV Vcc=MAX

Vee =5.0V

C1N

Input

V1N = 2.0V

Cour

Output

Vour = 2.0V

NOTES:
1. All typical values are at Vee= 5V, Tarm = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Ice is measured with the OE input grounded, all other inputs at 4.5V and the outputs open. 5. Leakage values are a combination of input and output leakage. 6. Measured with V1H applied to OE. 7. Duration of short circuit should not exceed 1 second.

LIMITS MIN TYP1 MAX

2.0

0.8

--0.8

-1.2

UNIT
v v v

2.4

v

0.35

0.5

v

<1

80

µA

-10

-100

µA

1

80

µA

-1

-140

µA

-15

-70

mA

150

190

mA

8

pF

15

pF

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x45x 12)

Product specification
PLS157

AC ELECTRICAL CHARACTERISTICS 0°C s Tair1> s +75°C, 4.75V s Vee s 5.25V, R1=4700, R2 = 1k'2

LIMITS

SYMBOL

PARAMETER

FROM

TO

TEST CONDITION MIN TYP1 MAX UNIT

Pulse width

lcKH

Clock2 High

CK+

CK-

CL=30pF

25

20

ns

lcKL

Clock Low

CK-

CK+

CL =30pF

30

20

ns

lcKP

Period

CK+

CK+

CL=30pF

70

50

ns

tpRH

Preset/Reset pulse

(l,B)-

(l,B)+

CL= 30pF

40

30

ns

Setup times

t1s1

Input

(l,B)±

CK+

CL =30pF

40

30

ns

t1s2

Input (through Fn)

F±

CK+

CL= 30pF

20

10

ns

Input (through

t1s3

Complement Array)4

(l,B)±

CK+

CL= 30pF

65

40

ns

Hold time

t1H1

Input

t1H2

Input

Propagation delays

(l,Bj±

CK+

CL= 30pF

0

-10

ns

F±

CK+

CL= 30pF

15

10

ns

lcKO

Clock

CK+

F±

CL= 30pF

25

30

ns

foE1

Output enable3

OE-

F-

CL=30pF

20

30

ns

loo1

Output disable3

OE+

F+

CL =5pF

20

30

ns

!po

Output

(l,B)±

B±

CL= 30pF

40

50

ns

foE2

Output enable3

(l,B)+

B±

CL= 30pF

35

55

ns

loo2

Output disable3

(l,B)-

B+

CL= 5pF

30

35

ns

lpRQ

Preset/Reset

(l,B)+

F±

CL= 30pF

50

55

ns

NOTES:
1. All typical values are at Vee= 5V, Tarm = +25°C. 2. To prevent spurious clocking, clock rise time (10% -900/o)s 10ns.

3. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and 8 1is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output
voltage of VT= (VoH-0.5V) with 8 1open, and Low-to-High impedance tests are made to the VT= (Vol+ 0.5V) level with 8 1 closed. 4. When using the Complement Array lcKP = 95ns (min).
5. Limits are guaranteed with 12 product terms maximum connected to each sum term.line.

VOLTAGE WAVEFORMS

TEST LOAD CIRCUIT

- w _j1.~ .J~c c1yc2

j L +3.0V~ 90%

ov--
ns~

. .
1~0%Sns

MEASUREMENTS: All circuit delays are measured at the +1.5V level of Inputs and outputs, unless otherwise specHled.
Input Pulses

INPUTS
NOTE: C1 andC2are10bypass Vee to GND.

Vee L:___>

R1

OE

lo

By

In OUT
Bw

Rz

CL

Bx Bz
CUC GND
=

= OUTPUTS

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 45 x 12)
TIMING DIAGRAMS
l,B
~NPUTS) CU<
F (OUTPUTS)
Flip-Flop Outputs

B (OUTPUTS)

Gate Outputs

Product specification
PLS157

TIMING DEFINITIONS

SYMBOL PARAMETER

lcKH

Width of input clock pulse.

lcKL

Interval between clock pulses.

lcKP

Clock period.

lpRH

Width of preset input pulse.

Required delay between

t1s1

beginning of valid input and

positive transition ol clock.

Required delay between

beginning of valid input forced

t1s2

at flip-flop output pins, and

positive transition of clock.

Required delay between

t1H1

positive transition of clock and

end of valid input data.

Required delay between

positive transition of clock and

t1H2

end of valid input data forced

at flip-flop output pins.

lcKD

Delay between positive transition of clock and when outputs become valid (with OE Low).

Delay between beginning of

loE1

Output Enable Low and when

outputs become valid.

Delay between beginning of

Output Enable High and

lo01

when outputs are in the

OFF-State.

Propagation delay between

tpo

combinational inputs and

outputs.

Delay between predefined

Output Enable High, and

loE2

when combinational outputs

become valid.

Delay between predefined

Output Enable Low and when

lo02

combinational outputs are in

the OFF-State.

tpRQ

Delay between positive transition of predefined Preset'Reset input, and when flip-flop outputs become valid.

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 45 x 12)

TIMING DIAGRAMS (Continued)

l,B (INPUTS)
-~~~~~~~~~~~~_,

·~~~~~~~~~~-ov

CLK
*PRESET RESET (I, B INPUTS) Q

Ona MIN.

----ov

F (OUTPUTS)
~~~~~~~~~~-'

(RESET) (PRESET)

*The leading edge of preset/reset must occur only when the input clock is "low'', and must remain khighk as long as required to override clock. The falling edge of preset/reset can never go "low'' when the input clock is "high".

Asynchronous Preset/Reset

l,B (LOAD SELECT)

1.SV

'OE

1.SV

+3V 1.SV
ov
+3V
ov

L

' \

'--

F (INPUTS)

+3V VoH
ov VoL

+3V CLK
tcKH
Q~~~=~~==

Flip-Flop Input Mode

October 22, 1993

256

Product specification
PLS157

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x45x 12)

Product specification
PLS157

LOGIC PROGRAMMING
The PLS157 is fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips Semiconductors' SNAP, Data 1/0 Corporation's ABEL'" and Logical Devices lnc.'s CUPLTM design software packages.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.

PLS157 logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors SNAP PLO design software package only.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE,

COMPLEMENT. INACTIVE, PRESET, etc., are defined below.
PROGRAMMING AND SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information.

"AND" ARRAY - (I), (B), (Qp)

¢"' ¢"' ¢'"·' ¢"' 1,8,Q

--- LB,Q 1,8,Q

--- LB,O 1,8,Q

- - - L~O 1,8,Q

--I, B, Q

(T, Fe, I.., P, R, D)n

STATE

T 1 CODE

f T 1 INACTIVE1. 2

o

(T, Fe, I.., P, R, D)n

I

STATE 1,8,Q

I I CODE H

"COMPLEMENT" ARRAY - (C)
~: ~:

(Tn,Fc)

[

1 1 ACTION

CODE

r l l INACTIVE1, 3, 5

0

(T,. Fe)

[ l 1 ACTION l ] J GENERATES

CODE A

"OR" ARRAY - (F·F CONTROL MODE)

(T, Fe, I.., P, R, D)n

I I I STATE 1.e.o

CODE L

~:

(T,.Fc)

r ACTION

] CODE

J · J [ PROPAGATE

(T, Fe, I.., P, R, D)n

STATE

J ] CODE

f 1 - 1 DON'TCARE

~:

(Tn,Fcl

[ l l ACTION
I l - l TRANSPARENT

CODE

1 l [

ACTION

r 1 l (COJN-TKROORLLDED)

CODE A

Notes on following page.

ACTION

CODE
·

October 22, 1993

257

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 45 x 12)

"OR" ARRAY - (Qn = D·Type)

~Q

Q

~

T0 STATUS ACTIVE(Set)

CODE A

Tn STATUS
INACTIVE t - i

CODE
·

"OR" ARRAY - (Qn = J·K Type)

Q

Q

Product specification
PLS157

Q

Q

ACTION TOGGLE

CODE 0

ACTION SET.

"OR" ARRAY - (Sor B), (P), (R)

CODE H

ACTION RESET

CODE L

"EX-OR" ARRAY - (B)

~IP,R,S I..-'

(ORB)

~ I ~ I..-'

.· R,S (ORB)

ACTION HOLD

CODE

TnSTATUS ACTIVE1

I J CODE
l AJ

''OE" ARRAY - (E)
~~

[ I J TnSTATUS

CODE

l l · J INACTIVE

~~

POLARITY LOW

CODE

POLARITY HIGH

CODE H

~~ ~~

En

En

En

ACTION
I IDLE1· 4

CODE
I0 I

ACTION
I CONTROL

CODE
IA I

I J ACTION
t I . J ENABLE4

CODE

I

ACTION DISABLE

NOTES: 1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates. 2. Any gate (T, Fe, L, P, R, D)n will be unconditionally inhibited if both of the I, B, or Q links are left intact. 3. To prevent oscillations, this state is not allowed for Clink pairs coupled to active gates Tn. Fe. 4. En = 0 and En = ·are logically equivalent states, since both cause Fn outputs to be unconditionally enabled. 5. These states are not allowed for control gates (l, P, R, D)n due to their lack of "OR" array links.

En
CODE
I- I

October 22, 1993

258

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 45 x 12)

Product specification
PLS157

PROGRAM TABLE

AND

-------

I INACTIVE

0

I I Ba

H

T 'EJ a

I L

DON'T CAREI -

1

oR

· r

coNTROL

- -1- - ---- - - -1,- - - -- - - - - - - - -

I I · ] I [ACTIVE

I A] P,R,8(0) [J/K

F/F

I J l,8(1), I LlNACTIV~L. (0-D) I JIKorD A MODE IDLE J_ 0

O(P) I

I (cooldl~

CONTRO!I A

I

J

l · ENABLE

1 NOTEs

- 1 -

1. The device is shipped with all links intact. Thus aback-

I groundofentriescorrespondingtostatesofvirginfinks

I existsinthetable,shownBLANKforclarity.
I 2. Program unused c. t. B, and a bits in the AND array as EA, B I ~(~r~~~~ ~~=i~~~.P, and R bits in the OR array

INACTIVE J_ 0
I GENERATE A
PROPAGATE I ·
TAANSPAAEITT_l -

I

C

I I TOGGLEJ. O

I SET

H

RESET I L

lHOLDJ:-

I·I
I
I (Q · JIK)

HIGH LOW

_j

IH I

I - DISABLE

. L . (POL)

L

FIF MODE

[I

I 3. Unused Terms can be k>ft blank.

I 4. 0 (P) and 0 (N) are respectively the present and next

1 states offh' p-flops Q.

Ee

EA

I

POLARITY
l

T

AND

tn 0

E R M

I

8(1)

Q(P)

c~a-r-2-r--1ro-t--5.,.-·J.,.-a-r-2-r-1-r-o-t-5-r-4~J-a-r-2-r-1-r-o-f

ziw==
(!)

o

I

I

1

I

I

Cii

2

...L

...L

>

3

_L

_L

fll

0 w

'iii

· s

I

I

I

I

1w -
....I Q.

la-: ~

s
7

:ii: 0 0
w

w 0
N
:::i

8 9
w

fll

0

11

l

T

T

I

...J..

j_

i

_L

_L

_L

I

I

~ z
0 i==
0a:
Q.
:c(/)

>xx<
~
u..

fll
:ii:
t>n aw :
:ii:
~
(/)
::::>

0 w > uiawi:i
w
~

12

I

I

n

l

T

M

T

T

~ffi~1=516=~=:=:=~~=~=:=i_L~~~~=:=:=~~._lL=~=:=:~

:ii: ,__1_1_,_-+-+-+-+-+-+-+l__,__,--<--<1--1--~I-+--+--+--<

:ii: 1a

I

I

81--19-t--t--+--1--+-t--+-T.--t--l--+-+-t--rr-+--t--+-1

I- 0 0 0

~

I

I

OR

Q(N)

p R

B(O)

·I. ·1 · 5

2 1 0 AA5

2 10

I

I

I

I

..l

i

.l

l

l

T

T

T

.l

.l

J.

l

I

T

T

T

_L

.l

_L

.l

I

I

T

I

~

L

J.

T

~

l

l

_L

_L

w~t-,=_2_52-_+·--t1----+1----t+----++--1+1--+--++--}l-;--+--t--+--!--l--J--1--l--1-1t---~1}1--+--1+----++---l~

_L

_L

I0 l--"26--f--ff-j--f--f--1--+--+l--+-+-+-+-+-+-l+-+-+-t

v

!

I I
T

I T

t-2_·-1--1--t--t--l--l--l-4.l--f--f--t--f--t--+.l-+-+-+--l

>i--"29'---t---+--t--+--+--+-+-.l"--f--1--+-+-t-~.l--f-+--t-4

i

_J_

w :<zii: aw :
:ii:
~
(/)
::::>
(.)

a'w*:"
a0 :
0
w
CJ)
<
J:
0a:
::::>
Q.

~

a:

~

u>ww'*"

u.. 0
aw :

0 fll

utn
j::

:ii:
:z:::>

z w
(!)
Cii

....I
~ ~

aw: I I ao 1--'3=1-t--+--+-+-+-+-+--+1--l--ll--l--l--l--~l-f--t--t--~

I Fe ~

T

T

,

T

·

J. r-

±

l---"-l--t-+--t--t--t--+-t--t--+-l-+-+-l-+-+--1--mt--

'*" , wo--':-B..--.-+--1--+--1--J-+--.l..l,__1--1-+-+-+-~.l~-.l+--+---1----e. al l-'!oA~1--t--f-jf-j--f--f--+l--f--f--f--f-+-+l-+-+-+-C_: _ _ _ _--f

~ D5

I

I

------------<

~

I

T

~ 1--D-a-+-+-+-+-+-+--+-T-+--+--+--+--+--+--T+--+--+-+-!1-------------~

ffi l--D_2-l--l--+--+--+--+--l-4..l.--+--+--+--f-+-+..l-+-+-+-C:

0 D1

_L

_L

-------------~

a:oo a.. 1---~-N~+-s+-4+-a+-2+-1·+-1.J_+-9_-+L-a-+-1-+-s-+-1-a~1-1J~l1-·r1-5r1-·r1-,-r

October 22, 1993

259

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 45 x 12)

SNAP RESOURCE SUMMARY DESIGNATIONS

(LOGIC TERMS)

(CONTROL TERMS)

PR L L D

::mf.lt5i:i'--+-------+---+--+----<-~

jiji~+~·- l - - - - - - - - + - + - - + - - + - - - + -

b

Product specification
PLS157

B

October 22, 1993

260

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 45 x 12)

Product specification
PLS159A

DESCRIPTION
The PLS159A is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K flip-flops are dynamically convertible to D-type via a "fold-back" inverting buffer and control gate Fe. It features 8 registered 1/0 outputs (F) in conjunction with 4 bidirectional 1/0 lines (B). These yield variable 1/0 gate and register configurations via control gates (D, L) ranging from 16 inputs to 12outputs.
The AND/OR arrays consist of 32 logic AND gates, 13 control AND gates, and 21 OR gates with fusible link connections for programming 1/0 polarity and direction. All AND gates are linked to 4 inputs (I), bidirectional 1/0 lines (B), internal flip-flop outputs (Q), and Complement Array output
(C"). The Complement Array consists of a
NOR gate optionally linked to all AND gates for generating and propagating complementary AND terms.
On-chip TIC buffers couple either True (I, B, Q) or Complement (T, "S, 0, C") input polarities
to all AND gates, whose outputs can be optionally linked to all OR gates. Any of the 32 AND gates can drive bidirectional 1/0 lines (B), whose output polarity is individually programmable through a set of Ex-OR gates for implementing AND-OR or AND-NOR logic functions. Similarly, any of the 32 AND gates can drive the J-K inputs of all flip-flops. There are 4 AND gates for the Asynchronous Preset/Reset functions.
All flip-flops are positive edge-triggered and can be used as input, output or 1/0 (for interfacing with a bidirectional data bus) in conjunction with load control gates (L), steering inputs (I), (B), (Q) and programmable output select lines (E).
The PLS159A is field-programmable, enabling the user to quickly generate custom patterns using standard programming equipment.

FEATURES
· High-speed version of PLS159 ·IMAX= 18MHz
- 25MHz clock rate · Field-Programmable (Ni-Cr link) · 4 dedicated inputs · 13 control gates · 32 AND gates · 21 OR gates · 45 product terms:
- 32 logic terms - 13 control terms · 4 bidirectional 1/0 lines · 8 bidirectional registers · J-K, T, or D-type flip-flops · Power-on reset feature on all flip-flops
<Fn = 1)
·Asynchronous Preset/Reset · Complement Array · Active-High or-Low outputs
· Programmable OE control
· Positive edge-triggered clock ·Input loading:-100µA (max.) ·Power dissipation: 750mW (typ.) · TTL compatible · 3-State outputs
APPLICATIONS
· Random sequential logic · Synchronous up/down counters · Shift registers · Bidirectional data buffers · Timing function generators · System controllers/synchronizers · Priority encoder/registers

ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Dual In-Line Package (300mil-wide) 20-Pin Plastic Leaded Chip Carrier

ORDER CODE PLS159AN PLS159AA

PIN CONFIGURATIONS
N Package Vee F7 F6
FS F4 F3 F2 F1 FO GND N =Plastic Dual ln·Line Package (300mil~wide)
A Package 11 ID CLKVccF7
F6 FS F4 F3 F2 83 GND llE FO F1 A = Plastic Leaded Chip Carrier
DRAWING NUMBER 0408D 0400E

October 22, 1993

261

853-115911164

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 45 x 12)

Product specification
PLS159A

LOGIC DIAGRAM

· · 1 - - - - - - - - - - - - - - - (LOGIC TERMS-1) - - - - - - · ·

(CONTROL TERMS) - - - - - - -

31 · · · · · ·24 23· · · · · ·16 15· · · · · · 8 7 · · · · · · 0 Fe
NOTES: 1. All OR gate inputs with a blown link float to logic "0". 2. All other gates and control inputs with a blown link float to logic·1".
3. e denotes WIRE-OR. 4. 0W Programmable connection.

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 45 x 12)

Product specification
PLS159A

FUNCTIONAL DIAGRAM

(LOGIC TERMS)

(CONTROL TERMS) Pa Ra PA RA La LA

D
· ·
b
6

EA Ea

~I--

~

<h

"C

L<Jt--t-----+--+-- c

I~

s -+---+--1--1 x

v

a

>---~---.-f,H

'p-'R J o

.

1--+

-

--t

-

-+-+

-----+

+ - - t - ivt '>o~---t

M-1-----<~H

(4)

-1-----+-+-t >----4-...,_--~.-.-.-0;1-~_---_-~-K--t---<-tu-.-~-+1t--CK+--'"~~-t------r-i---~

1 M -=-

T31

1 Fc

"'p-R J 0
(4)
1 ,K___<j-CK 'c_ ::>-...l.

"'

....... F

CK o----<J--0 CLK

LOGIC FUNCTION

I I~· ,~t~ I 03

1

6 R PRESENT STATE

I I I r. I STATE REGISTER

)(' B · C · ...

00 0

Sn+1 NEXTSTATE

SETOo:Jo= (03. 02· o,. Ou>·)(. B· c ...
Ko=·
RESET01:J1 :0 Kj=(Qa·02·01 ·Og)')(·B·C ...
HOLD 02:J2 = 0 K2=0
TOGGLE 03: Ja= (03 · 0:2 . o, . Oo) . )(. B. c .. . K3=(03· ll:2 · o, ·Ou)')(· B · c .. .
NOTE: Similar logic functions are applicable for D and T mode flip-flops.

FLIP-FLOP TRUTH TABLE

OE L CK p R J K Q F

H

Hi-Z

L x x L xxxL H

L x x H L xxH L

L x x L HxxL H

a a L L i L L L L

L L i L LL HL H

L L i L LH LH L

a L L i L L H H

a

H H i L L L H L H'

H Hi

x +10V

i

x i

L L H L H L'
x x L H L H" x x H L H L"

NOTES: 1. Positive Logic:
J-K=To+ T, + T2 .................. T31 Tn=C°·(IO·l1 ·12 ...)·(0o·01 ...)· (BO· 81 · ...) 2. T denotes transition from Low to High level. 3. X =Don't care 4. · = Forced at Fn pin for loading the J-K flip-flop in the Input mode. The load control term, Ln must be enabled (HIGH) and the p-terms that are connected to the
associated flip-flop must be forced LOW (disabled) during Preload. 5. At P = R = H, Q = H. The final state of Q
depends on which is released first. 6. · · = Forced at Fn pin to load J-K flip-flop
independent of program code (Diagnostic mode), 3-State B outputs.

October 22, 1993

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Philips Semiconductors Programmable Logic DevLces
Programmable logic sequencer
(16 x 45 x 12)

Product specification
PLS159A

VIRGIN STATE
The factory shipped virgin device contains all fusible links intact, such that: 1. OE is always enabled.
2. Preset and Reset are always disabled.
3. All transition terms are disabled.
4. All flip-flops are in D-mode unless otherwise programmed to J-K only or J-K or D (controlled).
5. All B pins are inputs and all F pins are outputs unless otherwise programmed.

CAUTION: PLS159A PROGRAMMING ALGORITHM
The programming voltage required to program the PLS159A is higher (17.5V) than
that required to program the PLS159 (14.5V).
ConsequenHy, the PLS159 programming algorithm will not program the PLS159A. Please exercise caution when accessing programmer device codes to insure that the correct algorithm is used.

THERMAL RATINGS
TEMPERATURE
Maximum junction
Maximum ambient Allowable thermal rise ambient to junction

150°C 75°C 75°C

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee

Supply voltage

+7

Voe

V1N

Input voltage

+5.5

Voe

Vour

Output voltage

+5.5

Voe

l1N

Input currents

-30

+30

mA

lour

Output currents

+100

mA

Tamb Tstg

Operating temperature range Storage temperature range

0

+75

oc

~5

+150

oc

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at
these or any other condition above those indicated in the operational and programming specification of the device is not implied.

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 45 x 12)

Product specification
PLS159A

DC ELECTRICAL CHARACTERISTICS 0°C s Ta;ro s +75°C, 4.75V s Vee s 5.25V

SYMBOL

Input voltage2

V1H

High

V1L

Low

Vic

Clamp

Output voltage2

VoH

High

Vol

Low

Input current

PARAMETER

TEST CONDITION
Vcc=MAX Vee= MIN Vee= MIN, l1N =-12mA
Vee= MIN, loH = -2mA loL = 10mA

l1H

High

l1L

Low

Output current

Vee= MAX, V1N = 5.5V V1N = 0.45V

lo( OFF)

Hi-Z state4· 1

Vee =MAX, Vour = 5.5V VouT =0.45V

las

Short circuit3· 5

VouT =OV

Ice

Vee supply current6

Vcc=MAX

Capacitance

C1N

Input

Vee = 5.0V, V1N = 2.0V

Cour

Output

VouT =2.0V

NOTES: 1. All typical values are at Vee = 5V, Tarrb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with V1H applied to OE. 5. Duration of short circuit should not exceed 1 second. 6. Ice is measured with the OE input grounded, all other inputs at 4.5V and the outputs open. 7. Leakage values are a combination of input and output leakage.

LIMITS MIN TYP1 MAX

2.0 0.8

--0.8

-1.2

2.4

0.35

0.5

UNIT
v v v
v v

<1

80

µA

-10

-100

µA

1

80

µA

-1

-140

µA

-15

-70

mA

150

190

mA

8

pF

15

pF

October 22, 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 45 x 12)

Product specification
PLS159A

AC ELECTRICAL CHARACTERISTICS
0°C s TambS +75°C, 4.75Vs Vee s5.25V, R1 =470'1, R2 = 11<.Q

LIMITS

SYMBOL

PARAMETER

FROM

TO

TEST CONDITION MIN TYP1 MAX UNIT

Pulse width

I''

lcKH

Clock2 High

CK+

CK-

CL= 30pF

20

15

ns

lcKL

Clock Low

CK-

CK+

CL= 30pF

20

15

ns

lcKP

Period

CK+

CK+

CL= 30pF

55

45

ns

lpRH

Preset/Reset pulse

(l,B)-

(l,B)+

CL= 30pF

35

30

ns

Setup times

t1s1

Input

(l,B)±

CK+

CL= 30pF

35

30

ns

t1s2

Input (through F0 )

F±

CK+

CL= 30pF

15

10

ns

t1s3

Input (through Complement Array)4

(l,B)±

CK+

CL= 30pF

55

45

ns

Hold time

t1H1

Input

t1H2

Input (through Fn)

Propagation delay

(1,B)±

CK+

CL= 30pF

0

-5

ns

F±

CK+

CL= 30pF

15

10

ns

lcKO

Clock

loE1

Output enable3

loo1

Output disable3

tpo

Output

CK+

F±

OE-

F-

OE+

F+

(l,B)±

B±

CL= 30pF CL= 30pF CL= 5pF CL= 30pF

15

20

ns

20

30

ns

20

30

ns

25

35

ns

loE2

Output enable3

(l,B) +

B±

CL= 30pF

20

30

ns

loo2

Output disable3

tpRQ

Preset/Reset

(l,B)-

B+

(l,B)+

F±

CL= 5pF CL= 30pF

20

30

ns

35

45

ns

tppR

Power-on/preset

Vee+

F-

CL= 30pF

0

10

ns

NOTES:

1. All typical values are at Vee = 5V, Tarro= +25°C.
2. To prevent spurious clocking, clock rise time (10%-90%) s 10ns.
3. For 3-State output; output enable times are tested with CL= 30pF to the 1.SV level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output

voltage of VT= (VoH -0.5V) with S 1 open, and Low-to-High impedance tests are made to the VT= (VoL + 0.5V) level with S1 closed. 4. When using the Complement Array lcKP = 75ns (min). 5. Limits are guaranteed with 12 product terms maximum connected to each sum term line.

VOLTAGE WAVEFORMS

TEST LOAD CIRCUIT

MEASUREMENTS: All circuit delays are measured at the +1.SV level of inputs and outputs, unless otherwise specified.
Input Pulses

yc2 c1
INPUTS
NOTE: C1 and C2 are to bypass Vee to GND.

L > Vee

R1

OE

lo

By

CL

In

OUT

Bw

Bx

Bz

=

= OUTPUTS

October 22. 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 45 x 12)
TIMING DIAGRAMS
1,8 (INPUTS)
CLK
F (OUTPUTS)
Flip-Flop Outputs

+3V
ov
+3V 1.SV
ov YOH
Vol +3V
ov

8 (OUTPUTS)

Gate Outputs

---------------------~+5V
4.5V

Vee
F (OUTPUTS)

ov ~~~~~~~~~~~~~~~~~~~~~~~
'PPR

1,8 (INPUTS)

r----+3V 1.5V

Power-On Reset

Product specification
PLS159A

TIMING DEFINITIONS
SYMBOL PARAMETER

lcKH lcKL lcKP lpRH
t1s1

Width of input clock pulse.
Interval between clock pulses.
Clock period.
Width of preset input pulse.
Required delay between beginning of valid input and positive transition of clock.

Required delay between

beginning of valid input forced

t1s2

at flip-flop output pins, and

positive transition of clock.

Required delay between

t1H1

positive transition of clock and

end of valid input data.

Required delay between

positive transition of clock and

t1H2

end of valid input data forced

at flip-flop output pins.

lcKO

Delay between positive transition of clock and when outputs become valid (with m:'Low).

Delay between beginning of

loE1

Output Enable Low and when

outputs become valid.

Delay between beginning of

Output Enable High and

lo01

when outputs are in the

OFF-State.

Delay between Vee (after

power-on) and when flip-flop

tppR

outputs become preset at "1"

(internal Q outputs at "O").

Propagation delay between

tpo

combinational inputs and

outputs.

Delay between predefined

Output Enable High, and

loE2

when combinational outputs

become valid.

Delay between predefined

Output Enable Low and when

loD2

combinational outputs are in

the OFF-State.

tpRQ

Delay between positive transition of predefined Preset/Reset input, and when flip-flop outputs become valid.

October 22, 1993

267

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 45 x 12)

TIMING DIAGRAMS (Continued)
+3V 1,8
~NPUTS)
ov

+3V CLK
ov

______ PRESET/RESET

_,

+3V

ov

(I, B INPUTS)

a

(PRESET)

'--_J~i:_~--' '-I,.___

. _ lPRO
F ( O U T P U T S ) - - - - - - - - - - - - - ' .__ _,_PR_E_s_E_ TJ ___,

VoH

· Preset and Reset functions override Clock. However, F outputs may glitch with the first positive Clock Edge if t1s1 cannot be guaranteed by the user.

Asynchronous Preset/Reset

+3V

l,B (LOAD SELECT)

1.sv

ov

+3V

UE

1.5V

ov

L

"""\

'--

F (INPUTS)

+3V VoH DV VoL

+3V CLK
'cKH
a~~~~~~~==

Flip-Flop Input Mode

October 22, 1993

268

Product specification
PLS159A

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 45 x 12)

Product specification
PLS159A

LOGIC PROGRAMMING
The PLS159A is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors' SNAP, Data 1/0 Corporation's ABE Lr· and Logical Devices lnc.'s CUPLTM design software packages.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.

PLS159A logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors SNAP PLD design software package.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE,

COMPLEMENT, INACTIVE, PRESET, etc., are defined below.
PROGRAMMING AND SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 1O(Third-party Programmer/ Software Support) of this data handbook for additional information.

~--' ~,., ~--' ~ .. "AND" ARRAY - (I), (B), (Qp)

1,8,Q

___ L~O 1,8,Q

- - - L~O
1,8,Q

--- 1,8,Q
1,8,Q

,- - -
1,8,Q

(T, Fe, I.., P, R, D)n

1 l STATE
I ] J INACTIVE1,2

CODE 0

(T, Fe, I.., P, R, D)n

I

STATE 1,8,Q

I I CODE H

(T, Fe, I.., P, II. D)n

I STATE 1,e,o

I I CODE L

(T, Fe, I.., P, II. D)n

r 1 l STATE

CODE

1 - J [ DoN·TcARE

"COMPLEMENT" ARRAY - (C)
~: ~:

(Tn,Fc)

[ T l ACTION I I J INACTIVE'· 3· 5

CODE 0

(T.,, Fe)

I J [

ACTION

r T J GENERATES

CODE A

~:

(T,,, Fe)

~

l J ACTION I . J PROPAGATE

CODE

~:

<Tn· Fe)

I J [

ACTION

T - l [ TRANSPARENT

CODE

"OR" ARRAY - (F·F CONTROL MODE)

"OR" ARRAY - (Qn = D-Type)

Fe

Fe

Q

Q

Q

Q

ACTION
J-KORD (CONTROLLED) 1

CODE A

Notes on following page.

ACTION J-KONLY

CODE
·

TnSTATUS ACTIVE (Set)1

CODE A

Tn STATUS INACTIVE (Reset)

CODE ·

CAUTION: THE PLS159A Programming Algorithm is different from the PLS159.

October 22, 1993

269

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 45 x 12)

Product specification
PLS159A

"OR" ARRAY - (On = J·K Type)
Q ~Q
+i5=lLi

Tn Q

Q
II'

ACTION TOGGLE

CODE 0

"OR" ARRAY - (S or B)
f-D-s.e

ACTION SET

CODE H

ACTION RESET

CODE

"EX-OR" ARRAY - (B)

ACTION HOLD

CODE

t Tn STATUS
ACTIVE'

J JJ I CODE A

TnSTATUS
l . J INACTIVE

[ POLARITY
I L Low1

L J

POLARITY

HIGH

I

H J

"OE" ARRAY - (E)
oc~

«~k

oc~

«~

En

En

En

[ I J ACTION

CODE

l l J IDLE11 4

0

[ ACTION L CONTROL

l J CODE
l AJ

I J ACTION
t l · J ENABLE4

CODE

[ ACTION
l DISABLE

NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates.
2. Any gate (T, Fe. L, P, R, D)n will be unconditionally inhibited if both of the I, B, or Q links are left intact. 3. To prevent oscillations, this state is not allowed for Clink pairs coupled to active gates T0 , Fe.
4. En = 0 and En = · are logically equivalent states, since both cause Fn outputs to be unconditionally enabled.
5. These states are not allowed for control gates (L, P, R, D)n due to their lack of "OR" array links.

En
I J CODE l -J

October 22, 1993

270

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 45 x 12)

Product specification
PLS159A

PROGRAM TABLE

AND

--- - - - -

I INACTIVE ~ 0

I B Q

H

T, Tl', a

I L

I - DON'T CARE

-

!
-1,- -

-

OR
--

-

-

-rI- - - -

--

- - - - - CONTROL

--

-

I ----i

I I [ACTIVE

I A] P, R, B(O) [JA<

~ ·] F/F

I [ I I, B(I), INACTIVE_l_ · ] (Q · D)

JA< or D [ AJMODE IDLE

J. o

I
f

Q(P) I

I (CO'l·oledil

CONTRotI A

I

I

I

J · ENABLE

EA, al

NOTES 1. The device is shipped w~h all links intact. Thus aback·
ground of entries corresponding to states of virgin links exists in the table, shown BLANK for clarity.
a 2. Program unused C, I, B, and bits in the AND array as(-).
::~;~u;;~~~~· P, and A bits in the OR array as(-)

[INACTIVE Io]
. l c LGENERATE Aj L J I · PROPAGATE J. - [TRANSPARENT j

I

.l TOGGLE 1 0
I _.;_

I SET

H

1 RESET I L
J. HOLD J.-

I I
I HIGH
10 · JIK) I LOW
l

IH I

J - DISABLE

L (POL)

I 3. Unused Terms can be left blank. I 4. Q (P) and Q (N) are re.~...·....·..+ivefy the present and next states

. · .--------_i--o.,1r11"_.T11ops_o_._ _ _r - - - - - . - - - - - - 1

FIF MODE

Ee

EA

POLARITY

(/)
0 j::
z w

(!l

(ii

>

Ill

c

w

:iii

Iw-
..J Q.

Ia-: ~

::!: 0 0

c
w
N

m w

:J
0

0
I-
z
0 j::
a: 0a. !!2
J: I-

~ >><<
~ u. 0

Ill
:>:!:
(/)
aw :
::!: 0
I-
(/)
:::> 0

c w >
jjj
0 aw :
w
!;( c

(/)
Iz -
w ::!: :::!: 0 0

T

AND

E R
M

I

B(I)

Q(P)

Ct---,--r-.--1t--.,-...,--,---1-T""""-,--r-"T-~"T'""""""l""-1

3210321076543210

10 11 12 13 14 15 16 17 18 19

(OR)

Q(N)

B(O)

765432103210

20

21

22

23

w

24

!;( 25

c

26

27

w ::!:
<z ( wa:
::!:
~
(/)
:::> 0

:ii:
a: caw:
0 w
(/) <(
J:
0a:
:::>
Q.

~
a: ~

u.

:ii: 0

w a:

>c0w
(/)

w
Ill
::!:
:z::>

Q. ..J

:J J:
Q.

~ ~

I
>aw:
I
:ii:
w
..J Ill
~
::!:
<(
a:
(!l
a0 :
Q.

28 29 30 31 Fe
Pe
Re Le
D3 D2 D1 DO

PIN

5 4 3 2 9 8 7 6 19 19 17 16 15 14 13 12

October 22, 1993

271

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x45x 12)

SNAP RESOURCE SUMMARY DESIGNATIONS

(LOGIC TERMS)

(CONTROL TERMS) Pe Re PA RA Le LA D

::::=i\;.-.+-------+---+--1---+--+---+--+-i

b

--ii---+--+-------+----1---i--t--Hi",~~r --ii---+--+-------+----t---i--t--H?J!·~~I:

Product specification
PLS159A

e

F
CK~CLK

October 22, 1993

272

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (14x48x6)

Product specification
PLS167/A

DESCRIPTION
The PLS167 and PLS167A are bipolar, Programmable Logic State machines of the Mealy type. The Programmable Logic Sequencers (PLS) contain logic AND/OR gate arrays with user programmable connections which control the inputs of on-chip State and Output Registers. These consist respectively of 8 Op, and 4 QF edge-triggered, clocked S/R flip-flops, with an asynchronous Preset Option.
All flip-flops are unconditionally preset to "1" during power turn-on.
The AND array combines 14 external inputs, 10-13, with 8 internal inputs, P0-7, fed back from the State Register to form up to 48 transition terms (AND terms). In addition, PO and P1 of the internal State Register are brought off-chip to allow extending the Output Register to 6 bits, if so desired.
All transition terms can include True, False, or Don't Care states of the controlling variables, and are merged in the OR array to issue next-state and next-output commands to their respective registers on the Low-to-High transition of the Clock pulse.
Both True and Complement transition terms can be generated by optional use of the internal variable (C) from the Complement Array. Also, if desired, the Preset input can be converted to output-enable function, as an additional user programmable option.
Order codes are listed in the Ordering Information Table.

FEATURES
· PLS167 - IMAX= 13.9MHz - 20MHz clock rate
· PLS167A
- IMAX = 20MHz
- 25MHz clock rate · Field-Programmable (Ni-Cr link) · 14 True/Complement buffered inputs · 48 programmable AND gates · 25 programmable OR gates · 8-bit State Register · 2-bit shared State/Output Register · 4-bit Output Register · Transition Complement Array · Programmable Asynchronous
Preset/Output Enable · Positive edge-triggered clock · Power-on preset to logic "1" of all registers · Automatic logic "HOLD" state via SIR
flip-flops · On-chip Test Array · Power: 600mW (typ.) · TTL compatible · 3-State outputs · Single +5V supply

PIN CONFIGURATIONS
N Package

F1 GND

110 111 112 113 PR/OE P1 PO F3

N = Plastic Dual In-Line Package (300mil·wide)

A Package
14 15 16 CLK Vee 17 18

NIC

19

110

111

112

FO

113

NIC

APPLICATIONS
· Interface protocols · Sequence detectors · Peripheral controllers
· TIming generators
· Sequential circuits · Security locking systems

A"" Plastic Leaded Chip Carrier

PR/OE

ORDERING INFORMATION
DESCRIPTION 24-Pin Plastic Dual In-Line Package (300mil-wide) 28-Pin Plastic Leaded Chip Carrier

ORDER CODE PLS167N,PLS167AN PLS167A,PLS167AA

DRAWING NUMBER 0410D 0401F

October 22, 1993

273

853-031511164

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(14 x 48 x 6)
FUNCTIONAL DIAGRAM

Product specification
PLS167/A
I'
PRl!JE

p

F

CLK

PIN DESCRIPTION

PINNO. 1

SYMBOL CLK

2-7 17-23
8

11-113 10

9-11 13
14-15

F0-3 P0-1

16

PR/OE

NAME AND FUNCTION
Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this line is necessary to update the contents of both registers.
Logic Inputs: The 13 external inputs to the AND array used to program jump condtions between machine states, as determined by a given logic sequence.
Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when exercised with standard TIL levels. When 10 is held at +10V, device outputs F0-3 and PO - 1 reflect the contents of State Register bits P2 - 7 (see Diagnostic Output Mode diagram). The contents of flip-flops PO - 1 and FO - 3 remain unaltered.
Logic/Diagnostic Outputs: Four device outputs which normally reflect the contents of
Output Register bits Oo-s. when enabled. When 10 is held at +10V, F0-3 =(P2-5).
Logic/Diagnostic Outputs: Two register bits with shared function as least Significant
= State Register bits, or most significant Output Register bits. When 10 is held at +1OV,
PO - 1 (P6 - 7).
Preset or Output Cnii6li Input: A user programmable function:
· Preset: Provides an Asynchronous Preset to logic ·1 ·of all State and Output Register bits. Preset overrides Clock, and when held High, clocking is inhibited and PO - 7 and FO -3 are High. Normal clocking resumes with the first full clock pulse following a High-to-Low clock transition, after Preset goes Low.
· Output Cnii61i: Provides an Output Enable function to all output buffers.

POLARITY Active-High Active-High/Low Active-High/Low
Active-High Active-High
Active-High (H)
Active-Low (L)

October 22, 1993

274

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (14x48x6)
LOGIC DIAGRAM
110 111 112 113

Product specification
PLS167/A

47 · · · · · · 40 39 · · · · · · 32 31 · · · · · · 24 23 · · · · · · 16 15 · · · · · · 8 7 · · · · · · 0

NOTES:
1. All AND gate inputs with a blown link float to a logic "1 ".
2. Alf OR gate inputs with a blown fuse float to logic "O". 3. .·.·.·.·. Programmable connection.

October 22, 1993

275

Philips Semici>nductors Programmable Logic Devices
Programmable logic sequencers (14x48x6)

Product specification
PLS167/A

TRUTH TABLE 1, 2, 3, 4, s, 6

LOGIC FUNCTION

OPTION

Typlcal State Transition:

Vee

PR

m:

lo

H

*

CK

s

x x

R

QPIF

F

x

H

H

I~ I~ i~ I ~R . PRESENT STATE

L

+10V

x

x

x

On (Qp)n

STATE REGISTER

lt · B · C · ···

I'

L

x

x

x

x

On (Cli:)n

H

*

x

x

x

On

Hi-Z

I I I 0 0 t1 Sn+1 NEXTSTATE

+5V

L

+10V

x

x

x

On

(Qp)n

L

x

x

x

x

On

!Oi:ln

L

x

t

L

L

On

(OF)n

L

x

t

L

H

L

L

SETOg:!o=(Oz · 01 ·~ · ll:·B· C ··· llo·D
RESET01:S1 ·D R1=C!J2·01 ·~ · ll:·B· C ···

L

x

t

H

L

H

H

L

x

t

H

H

IND. IND.

t

x x x

x

x

x

H

NOTES: 1. Positive Lcgic:
SIR=To+T1+T2+ ... T47 Tn = C(IO 11 12 ...)(PO P1 ... P7) 2. Either Preset (Active-High) or output 1:iii519 (Active-Low) are available, but not both. The desired function is a user-programmable option.
3. t denotes transition from Low-to-High level.
4. R = S =High is an illegal input condition. 5. · = H orLor+10V. 6. X = Don't Care (s5.5V)

ABSOLUTE MAXIMUM RATINGS1

SYMBOL Vee V1N

PARAMETER Supply voltage Input voltage

RATINGS

MIN

MAX

+7

+5.5

UNIT Voe Voe

VIRGIN STATE The factory shipped virgin device contains all fusible links intact, such that: 1. PR/OE option is set to PR. Thus, all
outputs will be at ·1 ·, as preset by initial power-up procedure. 2. All transition terms are disabled (0). 3. All SIR flip-flop inputs are disabled (0). 4. The device can be clocked via a Test Array pre-programmed with a standard test pattern. NOTE: The Test Array pattern MUST be deleted before incorporating a user program. This is accomplished automatically by any Philips Semiconductors qualified programming equipment.

Vour

Output voltage

+5.5

Voe

l1N

Input currents

-30

+30

mA

lour

Output currents

+100

mA

Tamt>

Operating temperature range

0

+75

·c

Tstg

Storage temperature range

~5

+150

·c

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal rise ambient to junction

150°C 75°C 75°C

October 22, 1993

276

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (14x48x6)

Product specification
PLS1i67/A

DC ELECTRICAL CHARACTERISTICS
0°C S Tarro S +75°C, 4.75V S Vee S 5.25V

LIMITS

SYMBOL

PARAMETER

TEST CONDITION

MIN TYP1 MAX

UNIT

Input voltage2

VrH

High

VrL

Low

Vrc

Clamp3

Output voltage2

VoH

High4

Vol

Lows

Input current

Vcc=MAX Vee= MIN Vee= MIN, lrN =-12mA

]

Vee= MIN loH=-2mA

loL =9.6mA

2.0

v

0.8

v

-0.8

-1.2

v

2.4

v

0.35

0.45

v

l1H

High

lrL

Low

l1L

Low (CK input)

Output current

VrN =5.5V VrN = 0.45V VrN = 0.45V

<1

80

µA

-10 -100

µA

-50

-250

µA

lo(OFFJ

Hi-Z states, 6

las

Short circuit3· 7

Ice

Vee supply current8

Capacitance&

Vee= MAX Vour=5.5V Vour = 0.45V Vour =OV
Vcc=MAX

1

40

µA

-1

--40

µA

-15

-70

mA

120

180

mA

CrN Cour

Input Output

Vee =5.0V VrN = 2.0V Vaur = 2.0V

8

pF

10

pF

NOTES:
1. All typical values are at Vee = 5V, Tarro = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time.
4. Measured with VrL applied to OE and a logic high stored, or with VrH applied to PR. 5. Measured with a programmed logic condition for which the output is at a low logic level, and VrL applied to PR/OE Output sink current is
supplied through a resistor to Vee. 6. Measured with VrH applied to PR/OE. 7. Duration of short circuit should not exceed 1 second. 8. Ice is measured with the PR/OE input grounded, all other inputs at 4.5V and the outputs open.

October 22, 1993

277

Philips Semiconductors Programmable Logic Devices
Prowammable logic sequencers (14 x 48 x 6)

Product specification
PLS167/A

AC ELECTRICAL CHARACTERISTICS
R1 =4700, R2 =1k0, CL= 30pF, 0°C :s;Tamt>:S+75°C, 4.75°CV !>Vee :s5.25V

LIMITS

SYMBOL

PARAMETER

FROM

TO

PLS167

PLS167A

UNIT

MIN TYP1 MAX MIN TYP1 MAX

Pulse width3

lcKH lcKL lcKP lpRH

Clock2 High Clock Low Clock Period Preset pulse

Setuptime3

CK+

CK-

25

15

20

15

ns

CK-

CK+

25

15

20

15

ns

CK+

CK+

50

30

40

30

ns

PR+

PR-

25

15

25

15

ns

t1s1A

Input

Input±

CK+

60

40

ns

t1s1B

Input

Input±

CK+

50

30

ns

t1s1C

Input

Input±

CK+

42

NIA

ns

tis~

Input (through Complement Array)

Input±

CK+

90

70

ns

t1s2B

Input (through Complement Array)

Input

CK+

80

60

ns

t1s2C

Input (through Complement Array)

Input

CK+

72

N/A

ns

tvs

Power-on preset

lpRS

Preset

Vee+

CK-

0

-10

0

-10

ns

PR-

CK-

0

-10

0

-10

ns

Hold time

t1H

Input

CK+

Input±

5

-10

5

-5

ns

Propagation delay

lcKO

Clock

loE

Output enable4

loo

Output disable4

lpR

Preset

lppR

Power-on preset

Frequency of operatlon3

CK+ OEOE+ PR+ Vee+

Output± OutputOutput+ Output+ Output+

15

30

20 30

20 30

18

30

0

10

15

20

ns

20

30

ns

20

30

ns

18

30

ns

0

10

ns

fMAXC

Without Complement Array

13.9

20.0

MHz

fMAXC

With Complement Array

9.8

12.5

MHz

NOTES: 1. All typical values are at Vee = 5V, Tamt> = +25°C. 2. To prevent spurious clocking, clock rise time (10% -90%) s30ns. 3. See "Speed vs. OR Loading" diagrams.
4. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output voltage of Vr = (VoH-0.5V) with S1 open, and Low-to-High impedance tests are made to the Vr = (VoL + 0.5V) level with S1closed.

TEST LOAD CIRCUIT

VOLTAGE WAVEFORMS

~y~
INPUTS
NOTE:
C1 and ~ are to bypass Vee to GND. October 22, 1993

lJE

IO

By

DUT 113

R1 CL

CLK

Bz

GND

=

= OUTPUTS

278

MEASUREMENTS: All circuit delays ae measured at the +1.5V level al Inputs and outputs, unless otherwise specHied.
Input Pulses

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (14x48x6)

Product specification
PLS167/A

TIMING DIAGRAMS

I0-13

I.SY

Fllp-Flop Outputs

+3V
ov
+3Y I.SY
OY
YOll
Yot. +3Y
OY

Asynchronous Preset

~~~~,....,------------------- YOH

1.SY

(Fn)=1

(Fn+1)

'----- YoL

+3Y

CLK--

OY

October 22, 1993

Power-On Preset

+3Y OY
279

TIMING DEFINITIONS

SYMBOL

PARAMETER

lcKH

Width of input clock pulse.

lcKL

Interval between clock pulses.

Minimum guaranteed clock

lcKP

period.

Required delay between

t1s1

beginning of valid input and

positive transition of clock.

Required delay between

beginning of valid input and

positive transition of clock,

t1s2

when using optional

Complement Array (two

passes necessary through the

AND array).

Required delay between Vee

(after power-on) and negative

tvs

transition of clock preceding

first reliable clock pulse.

Required delay between

negative transition of

asynchronous Preset and

lpRS

negative transition of clock

preceding first reliable clock

pulse.

Required delay between

t1H

positive transition of clock and

end of valid input data.

Delay between positive transition of clock ·and when lcKO outputs become valid (with PR/OE low).

Delay between beginning of

loE

Output Enable Low and when

outputs become valid.

Delay between beginning of

Output Enable High and

loo

when outputs are in the

OFF-State.

Delay between input 10

transition to Diagnostic mode

ls RE

and when the outputs reflect

the contents of the State

Register.

Delay between input 10 transition to Logic mode and
lsRD when the outputs reflect the contenis of the Output
Register.

Delay between positive

tpR

transition of Preset and when

outputs become valid at "1 ".

Delay between Vee (after lppR power-on) and when outputs
become preset at "1 ".

!pRH

Width of preset input pulse.

Minimum guaranteed

IMAX

operating frequency.

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (14x48x6)

Product specification
PLS167/A

TIMING DIAGRAMS (Continued)

1.SV
JO CLK INTERNAL-STATE REG.

+3V ov +10V +3V ov +3V ov

OUTPUT

(Fn)

P,F~~+-~~~~.j...~..J'°""-"-c...e;~

ov

Diagnostic Output Mode

SPEED VS. "OR" LOADING
The maximum frequency at which the PLS can be clocked while operating in sequential mode is given by:
(1/fMAX) =tcv =trs + lcKO
This frequency depends on the number of transition terms Tnused. Having all 48 terms connected in the AND array does not appreciably impact performance; but the number of terms connected to each OR line affects !rs. due to capacitive loading. The effect of this loading can be seen in Figure 1, showing the variation of trs 1with the number of terms connected per OR.
The PLS167 AC electrical characteristics contain three limits for the parameters trs1 and 1rs2 (refer to Figure 1). The first, trs1A is guaranteed for a device with 48 terms connected to any OR line. tr818 is guaranteed for a device with 32 terms connected to any OR line. And !rs1c is guranteed for a device with 24 terms conntected to any OR line.
The three otherentries in the AC table, trs2A, B, and C are corresponding 48, 32, and 24 term limits when· using the on-chip Complement Array.
The PLS167A AC electrical characteristics contain two limits for the parameters trs1and trs2 (refer to Figure 2). The first, trs1A is guaranteed for a device with 24 terms connected to any OR line. tr810 isguaranteed for a device with 16 terms connected to any OR line.

20 l--+--f---+--1--1----1 101---+---l---+--1--1---1

0

8 16 24 32 40 48

TERMS CONNECTED/OR

Figure 1. PLS167 ~s1 vs. Terms/OR Connected

101-----t--+---1---1----1

0

8 16 24 32 40

TERMS CONNECTED/OR

Figure 2. PLS167A t1s1 vs. Terms/OR Connected

The two other entries in the AC table, trs2 A and B are corresponding 24 and 16 term limits when using the on-chip Complement Array.

The worst case of trs for a given application can be determined by identifying the OR line with the maximum numberofT0 connections. This can be done by referring to the interconnect pattern in the PLS logic diagram, typically illustrated in Figure 3, or by counting the maximum number of "H" or"L" entries in one of the columns of the device Program Table.

This number plotted on the curve in Figure 1 or Figure 2 will yield the worst case trs and, by implication, the maximum clocking frequency for reliable operation.

Note that for maximum speed all UNUSED transition terms shouldbe disconnectedfrom the OR array.

(4)mgg} TRANSITION TERMS Tn

TERMS/
00

~

"OR"'
AARM

(3)

NOT USED

Figure 3. Typical OR Array Interconnect Pattern

October 22, 1993

280

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(14 x 48 x 6)

Product specification
PLS167/A

LOGIC PROGRAMMING
The PLS167/A devices are fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips Semiconductors' SNAP design software package. ABEL'" CUPLTM and PALASM® 90 design software packages also support the PLS167/A architecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PRESET/OE OPTION - (P/E)

PLS167/A logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors SNAP PLO design software package.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.

PROGRAMMING AND SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information.

OPTION PRESET 1

CODE H

OPTION

CODE

PROGRAMMING: The PS 167/A has a power-up preset feature. This feature insures thatthe device will power-up in a known state with all register elements (State and Output Register) at logic High (H). When programming the device it is important to realize this is the initial state of the device. You must provide a next state jump if you do not wish to use all Highs (H) as the present state.
"AND" ARRAY - (I), (P)

"OR" ARRAY - (N), (F)

"iro' "iro' ''iro' "iro' i1,I

R

i1,I

R

i1,I

R

i1,I

R

I I I ACTION INACTIVE1· 3

CODE 0

I

ACTION SET

I I CODE H

I

ACTION RESET

I I CODE L

I I I ACTION NO CHANGE

CODE
-

a : a : a : a : "COMPLEMENT"ARRAY- (C)

.
I ACTION INACTIVE1,4

Tn
I I CODE 0

I ACTION GENERATE

Tn
I I CODE A

I ACTION PROPAGATE

Tn
I I CODE ·

[

ACTION

I

L l TRANSPARENT

Tn
J CODE -J

NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate Tn will be unconditionally inhibited if both the true and complement of any input (I, P) are left intact. 3. To prevent simultaneous Set and Reset flip-flop commands, this state is not allowed for N and Flink pairs coupled to active gates Tn (see
flip-flop truth tables). 4. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn·

October 22. 1993

281

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(14 x 48 x 6)

Product specification
PLS167/A

PROGRAM TABLE
CUSTOMER NAME_ _ _ _ _ _ _ _ _ _~ PURCHASE ORDER#_ _ _ _ _ _ _ _ _ __ PHILIPS DEVICE #_ _ _ _ _C_F_(~X_X_X_X~)_ __ CUSTOMER SYMBOLIZED PART#_ _ _ _ __ TOTAL NUMBER OF PARTS_ _ _ _ _ _ _ __ PROGRAM TABLE REV_ _ _ _ _ _ _ _ _ _ _ _ _ _ __ ~~~~~~~~~~~~DATE_ _ _ _ _ _ _ _ _ _ _ _ _ _ __

PROGRAM TABLE ENTRIES

AND

I

OR

------------,-----------~

INACTIVE

0

I INACTIVE

0

GENERATE

A

I SET

H

Ns, Fr

PROPAGATE

·

Cn 1 RESET

L

TRANSPARENT' -

I NO CHANGE

-

INACTIVE

0

-~~N'T l,P

· H

CARE

.'.:.

j I I ''----------~-!-!-~------------!!

I.,. Pa

~:ESET ! ~ PIE

AND

OPTION(P/E)

I

OR

PRESENT STATE (Pa)
0 -7- -6 5 4)) 2 1 0

REMARKS

NEXT STATE (Ns)

OUTPUT (Fr)

7 6 5 4 -3- -2-11 0 3 2 1 0

1

2

3

4

I

I

5 6 7 8

I I I I

. I
I

I I I I

I I I

I I I I

9

I

I

10

11

12

13

14

I

I

I

15

I

I

I

I

16

I

I

I

I

I

17

I

I

I

I

I

18

I

I

I

I

19

20

21

22

R

I

~ f---+--+---:'-t-+-+-~,'~f~t-+-~:--J~!--t-+--+---+--+-----'-,-+-l--J~!--~~~~~~~-1--J~t-+--+--+-~:~1--1-+--+---+--l

26

I

I

I

27

I

I

I

28

I

I

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

PIN NO.

17 18 19 ~ 21 " ~ 2 3 4 5 6 7 8

I I
15 14 13 11 10 9

w

..J w

C~D
a:

::;;
z<[

~

NOTES: 1. The device is shipped with all links initially intact. Thus, a background of "O" for all Terms, and an "H" for the PIE option, exists in the table,
shown BLANK instead for clarity. 2. Unused C0 , Im. and P8 bits are normally programmed Don't Care(-). 3. Unused Transition Terms can be left blank for future code modification, or programmed as(-) for maximum speed. 4. Letters in variable fields are used as identifiers by logic type programmers.

October 22, 1993

282

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (14 x 48 x 6)

Product specification
PLS167/A

TEST ARRAY
The PLS may be subjected to AC and DC parametric tests prior to programming via an on-chip test array.
The array consists of test transition terms 48 and 49, factory programmed as shown below.
Testing is accomplished by clocking the PLS and applying the proper input sequence to
lo-13 as shown in the test circuit timing
diagram.

T
E
R c
M

48

A

49

Both terms 48 and 49 must be deleted during user programming to avoid interfering with the desired logic function. This is accomplished automatically by any Signetic's qualified programming equipment.

T

AND

E

R c

M 3 2 1

48

H H H

48

L L LL

October 22, 1993

State Diagram

Vee +sv Vee

In CLOCK

P0-7

P0-1

I0-13

CK

F0-3

PR/OE

GND

=
PLS Under Test

H

Test Array Program
4.75~,-------------------- +5V Vee
ov
vtH CLK

I0-13
F0-3
STATE REGISTER

Vil

3V

ov

··'------------J

r····

HIGH LOW

Test Circuit liming Diagram

H

Test Array Deleted 283

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (14x48x6)
SNAP RESOURCE SUMMARY DESIGNATIONS

Product specification
PLS167/A
I~

October 22, 1993

284

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (12 x 48 x 8)

Product specification
PLS168/A

DESCRIPTION
The PLS 168 and the PLS 168A are bipolar, Programmable Logic State machines of the Mealy type. They contain logic AND/OR gate arrays with user programmable connections which control the inputs of on-chip State and Output Registers. These consist respectively of 1O Qp, and 4 OF edge-triggered, clocked SIR flip-flops, with an Asynchronous Preset Option.
All flip-flops are unconditionally preset to ·1" during power turn-on.
The AND array combines 12 external inputs, 10-11, with 10 internal inputs, P0-9, fed back from the State Register to form up to 48 transition terms (AND terms). In addition, PO-P3 of the internal State Register are brought off-chip to allow extending the Output Register to 8 bits, if so desired.
All transition terms can include True. False, or Don't Care states of the controlling variables, and are merged in the OR array to issue next-state and next-output commands to their respective registers on the Low-to-High transition of the Clock pulse.
Both True and Complement transition terms can be generated by optional use of the internal variable (C) from the Complement Array. Also, if desired, the Preset input can be converted to output-enable function, as an additional user programmable option.
Order codes are listed in the Ordering Information table below.

FEATURES
· PLS168 - IMAX= 13.9MHz - 20MHz clock rate
· PLS168A - IMAX = 20MHz - 25MHz clock rate
· Field-Programmable (Ni-Cr link) · 12 True/Complement buffered inputs · 48 programmable AND gates · 29 programmable OR gates · 10-bit State Register · 4-bit shared State/Output Register · 4-bit Output Register · Transition Complement Array · Programmable Asynchronous
Preset/Output Enable · Positive edge-triggered clock · Power-on preset to logic "1" of all registers · Automatic logic "HOLD" state via SIR
flip-flops · On-chip Test Array · Power: 600mW (typ.) · TTL compatible · 3-State outputs · Single +5V supply

PIN CONFIGURATIONS
NPackage

F2 GND

110 111 PR/OE P3 P2 P1 PO

N · Plastic DIP (3CXlml~wide)
A Package
13 14 15 CLK Vee 16 17

F2 F3 GND PO P1 P2 P3 A · Plastic Leaded Chp Carrier

APPLICATIONS
· Interface protocols · Sequence detectors · Peripheral controllers · Timing generators · Sequential circuits · Security locking systems ·Counters · Shift registers

ORDERING INFORMATION
DESCRIPTION 24-Pin Plastic DIP (300mil-wide) 28-Pin Plastic Leaded Chip Carrier

ORDER CODE PLS168N,PLS168AN PLS168A,PLS168AA

DRAWING NUMBER 0410D 0401F

October22, 1993

285

853--0322 11164

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (12 x 48 x 8)
FUNCTIONAL DIAGRAM

Product specification
PLS168/A
PR/OE

p

F

CLK

PIN DESCRIPTION

PINNO. 1

SYMBOL CLK

2-6 18-23
7

11-111 10

13-16 10-11
17

P0-3 F2-F3 PR/OE

8,9

FO-F1

NAME AND FUNCTION
Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this line is necessary to update the contents of both registers.
Logic Inputs: The 11 external inputs to the AND array used to program jump conditions between machine states, as determined by a given logic sequence.
Logic/Diagnostic Input: A 12th external logic input to the AND array, as above, when exercised with standard TIL levels. When 10 is held at +1OV, device outputs F2 - F3 and PO - P3 reflect the contents of State Register bits P4 -9 (see Diagnostic Output Mode diagram). The contents of flip-flops PO - 1 and FO - 3 remain unaltered.
Logic/Diagnostic Outputs: Four device outputs which normally reflect the contents of State Register bits PO - 3. When 10 is held at+ 1OV these pins reflect (P6 - P9).
Logic/Diagnostic Outputs: Two register bits (F2 - F3) which reflect Output register bits (02-03). When 10 is held at +10V, these pins reflect (P4- PS).
Preset or Output EiUi6Ji Input: A user programmable function:
· Preset: Provides an Asynchronous Preset to logic "1" of all State and Output Register bits. Preset overrides Clock, and when held High, clocking is inhibited and PO - 9 and FO - 3 are High. Normal clocking resumes with the first full clock pulse following a High-to-Low clock transition, after Preset goes Low.
· Output EiUilili: Provides an Output Enable function to all output buffers.
Logic Output: Two device outputs which reflect Output Registers 00 -01. When 10 is held at +10V, FO- F1 =Logic "1".

POLARITY Active-High Active-High/Low Active-High/Low
Active-High Active-High
Active-High (H)
Active-Low (L)

October 22, 1993

286

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (12 x 48 x 8)
LOGIC DIAGRAM

Product specification
PLS168/A

47· · · · · ·40 39· · · · · ·32 31 · · · · · ·24 23· · · · · ·1& 1s· · · · · · a

NOTES:

1. All programmed "AND" gate locations are pulled to logic "1 ".

2. All programmed "OR" gate locations are pulled to logic "O".

t t 3.

Programmable connection.

1 · · · · · ·o

October 22, 1993

287

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (12x48x8}

Product specification
PLS168/A

TRUTH TABLE 1· 2, 3, 4, s, 6

OPTION

Vee

PR

OE

H

.lo

CU<
x

s x

L

+10V

x

x

L

H

. x

x

x

x x

+5V

L

+10V

x

x

L

x

x

x

L

x

i

L

L

x

i

L

L

x

i

H

L

x

i

H

i

x

x

x

x

x

R

Qplf

F

x

H

H

x

On

(Op)n

x

On

(0F)n

x

On

Hi-Z

x

On

(Op)n

x

On

(0F)n

L

On

(OF)n

H

L

L

L

H

H

H

IND.

IND.

x

H

NOTES:
1. Positive Logic:
S/R =To+ T1 + T2 + ... + T47 Tn = C(IO 11 12 ...)(PO P1 ... P9) 2. Either Preset (Active-High) or Output EMDle (Active-Low) are available, but not both.
The desired function is a user-programmable option.
i 3. denotes transition from Low-to-High level.
4. R = S = High is an illegal input condition.
5. · =H or Lor +1OV.
6. X =Don't Care (55.5V)

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee V1N Vour l1N

Supply voltage Input voltage Output voltage Input currents

+7

Voe

+5.5

Voe

+5.5

Voe

-30

+30

mA

lour Tamb Tstg

Output currents Operating temperature range Storage temperature range

+100

mA

0

+75

cc

~5

+150

cc

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

LOGIC FUNCTION

Typical State Transition:

I~ I~\~ I ~R PRESENT STATE

STATE REGISTER

)( · B · C' ··.

I0I0t1 I Sn+1 NEXTSTATE

SET0g:Sg:'°2 · 01 ·UoJ ·ll:OB · C ...
Rg:O
RESET01:S1 :0
R1 =<112 · 01 ·tJo) · X ·B· C ...
HOLD 02: 52 =0
R2=0

VIRGIN STATE
The factory shipped virgin device contains all fusible links intact, such that: 1. PR/OE option is set to PR. Thus, all outputs
will be at "1 ", as preset by initial power-up procedure. 2. All transition terms are disabled (0). 3. All SIR flip-flop inputs are disabled (0). 4. The device can be clocked via a Test Array pre-programmed with a standard test pattern. NOTE: The Test Array pattern MUST be deleted before incorporating a user program. This is accomplished automatically by any Philips Semiconductors qualified programming equipment.

THERMAL RATINGS
TEMPERATURE Maximum junction
Maximum ambient
Allowable thermal rise ambient to junction

150°C 75°C 75°C

October 22, 1993

288

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (12x48x8)

Product specification
PLS168/A

DC ELECTRICAL CHARACTERISTICS
0°c s Tamb s +75°C, 4.75V s Vee s 5.25V

SYMBOL

PARAMETER

Input voltage2

V1H

High

V1L

Low

Vic

Clamp3

Output voltage2

VoH

High4

Vol

Low5

Input current

TEST CONDITION
Vcc=MAX Vee= MIN Vee= MIN, l1N =-12mA
Vee= MIN loH=-2mA IOL=9.6mA

LIMITS MIN TYP1 MAX

2.0

0.8

-0.8

-1.2

UNIT
v v v

2.4

v

0.35

0.45

v

l1H

High

l1L

Low

l1L

Low (CLK input)

Output current

V1N =5.5V V1N = 0.45V V1N = 0.45V

<1

25

µA

-10

-100

µA

-50

-250

µA

lo(OFF)

Hi-Z state6

Vcc=MAX Vour =5.5V Your= 0.45V

1

40

µA

··1

40

µA

las

Short circuit3· 7

Ice

Vee supply current8

Capacitance6

Vour =OV Vcc=MAX

-15

-70

mA

120

180

mA

Vee =5.0V

C1N

Input

V1N = 2.0V

8

pF

Cour

Output

Your= 2.0V

10

pF

NOTES:
1. All typical values are at Vee= 5V, Tarrb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time.
4. Measured with V1L applied to OE and a logic high stored, or with V1H applied to PR. 5. Measured with a programmed logic condition for which the output is at a low logic level, and V1L applied to PR/OE Output sink current is
supplied through a resistor to Vcc6. Measured with V1H applied to PR/OE. 7. Duration of short circuit should not exceed 1 second. 8. Ice is measured with the PR/OE input grounded, all other inputs at 4.5V and the outputs open.

October 22, 1993

289

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (12 x 48 x 8)

Product specification
PLS168/A

AC ELECTRICAL CHARACTERISTICS
R1 = 4700, R2 = 1k.Q, CL= 30pF, 0°c :S Tamb :S +75°C, 4.75°CV :S Vee s 5.25V

LIMITS

SYMBOL

PARAMETER

FROM

TO

PLS168

PLS168A

UNIT

MIN TYP1 MAX MIN TYP1 MAX

i.

Pulse width3

lcKH

Clock2 High

lcKL

Clock Low

lcKP

Clock Period

lpRH

Preset pulse

CK+

CK-

25

15

20

15

ns

CK-

CK+

25

15

20

15

ns

CK+

CK+

50

30

40

30

ns

PR+

PR-

25

15

25

15

ns

Setup time3

t1s1A

Input

Input±

CK+

60

40

ns

t1s1B

Input

Input±

CK+

50

30

ns

t1s1C

Input

Input±

CK+

42

NIA

ns

tis~

Input (through Complement Array)

Input±

CK+

90

70

ns

t1s2B

Input (through Complement Array)

Input

CK+

80

60

ns

t1s2C

Input (through Complement Array)

Input

CK+

72

NIA

ns

tvs

Power-on preset

tPRS

Preset

Vee+

CK-

0

-10

0

-10

ns

PR-

CK-

0

-10

0

-10

ns

Hold time

t1H

Input

CK+

Input±

5

-10

5

-10

ns

Propagation delay

lcKO

Clock

loE

Output enable4

loo

Output disable4

tpR

Preset

tr PR

Power-on preset

Frequency of operation3

CK+ OEOE+ PR+ Vee+

Output± OutputOutput+ Output+ Output+

15

30

20

30

20

30

18

30

0

10

15

20

ns

20

30

ns

20

30

ns

18

30

ns

0

10

ns

fMAXC IMAXC

Without Complement Array With Complement Array

13.9 9.8

20.0 12.5

MHz MHz

NOTES:

1. All typical values are at Vee = 5V, TaTTt> = +25°C. 2. To prevent spurious clocking, clock rise time (10% -90%) :S 30ns. 3. See "Speed vs. OR Loading" diagrams.

4. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output

voltage of Vr = (VoH -0.5V) with S 1open, and Low-to-High impedance tests are made to the Vr = (VoL + 0.5V) level with S 1closed.

TEST LOAD CIRCUIT

VOLTAGE WAVEFORMS

Vee

OE

lo

By

INPUTS <>-'----<., 111 OUT

R1 CL

NOTE:
C1 and C2 are to bypass Vee to GND.

eLK

Bz

GND

=

= OUTPUTS

MEASUREMENTS: All circuit delays are measured at the + 1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses

October 22, 1993

290

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(12 x 48 x 8)

Product specification
PLS168/A

TIMING DIAGRAMS

I0-11

1.5V

Flip-Flop Outputs

Asynchronous Preset

October 22, 1993

Power-On Preset

+3V
ov
+3V 1.5V
ov
VQH VOL +3V
ov
+3V
ov 291

TIMING DEFINITIONS

SYMBOL

PARAMETER

lcKH lcKL
lcKP

Width of input clock pulse.
Interval between clock pulses.
Minimum guaranteed clock period.

Required delay between

t1s1

beginning of valid input and

positive transition of clock.

Required delay between

beginning of valid input and

positive transition of clock,

t1s2

when using optional

Complement Array (two

passes necessary through the

AND array).

Required delay between Vee

(after power-on) and negative

tvs

transition of clock preceding

first reliable clock pulse.

Required delay between

negative transition of

asynchronous Preset and

lpRS

negative transition of clock

preceding first reliable clock

pulse.

Required delay between

t1H

positive transition of clock and

end of valid input data.

lcKO

Delay betw.een positive transition of clock and when outputs become valid (with PR/OE Low).

Delay between beginning of

loE

Output Enable Low and when

outputs become valid.

Delay between beginning of

Output Enable High and

loo

when outputs are in the

OFF-State.

Delay between input 10

transition to Diagnostic mode

lsRE

and when the outputs reflect

the contents of the State

Register.

Delay between input 10

transition to Logic mode and

ts RD

when the outputs reflect the

contents of the Output

Register.

Delay between positive

tpR

transition of Preset and when

outputs become valid at "1".

Delay between Vee (after

lppR

power-on) and when outputs

become preset at "1 ".

!pRH IMAX

Width of preset input pulse.
Minimum guaranteed operating frequency.

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(12 x 48 x 8)

Product specification
PLS168/A

TIMING DIAGRAMS (Continued)

+3V

ov

+1DV

,,

+3V IO
ov

+3V
CLK
ov
-------- VoH

VoL

OUTPUT

(Fn)

~F~~+-~~~~-+-~~.1 ~.&..<'-"-'-"""

ov
Diagnostic Mode

SPEED VS. "OR" LOADING
The maximum frequency at which the PLS can be clocked while operating in sequential mode is given by:
(1/fMAX) =Icy= t1s + lcKO
This frequency depends on the number of transition terms Tn used. Having all 48 terms connected in the AND array does not appreciably impact performance; but the number of terms connected to each OR line affects t18, due to capacitive loading. The effect of this loading can be seen in Figure 1, showing the variation of t181 with the number of terms connected per OR.
The PLS168 AC electrical characteristics contain three limits for the parameters 1181 and t1s2 (refer to Figure 1). The first, t1s1A is guaranteed for a device with 48 terms connected to any OR line. t1Srn is guaranteed for a device with 32 terms connected to any OR line. And t1s1C is guranteed for a device with 24 terms conntected to any OR line.
The three other entries in the AC table, t1s2A, B, and C are corresponding 48, 32, and 24 term limits when using the on-chip Complement Array.
The PLS168A AC electrical characteristics contain two limits for the parameters t181 and t1s2 (refer to Figure 2). The first, t1s1A is guaranteed for a device with 24 terms connected to any OR line. t1818 is guaranteed for a device with 16 terms connected to any OR line.

20f--+~+---t~-+-~t-~ 10f--+~+---t~-+-~t-~

0

8 16 24 32 40 48

TERMS CONNECTED/OR

Figure 1. PLS168 t1s1 vs.
Terms/OR Connected

v it 30
.. 20 F-~-+--l-+-+--1
10t----t~-+~-r-~t--i

0

8 16 ~ ~ ~

TERMS CONNECTED/OR

Figure 2. PLS168A t1s1 vs. Terms/OR Connected

The two other entries in the AC table. t1s2 A and B are corresponding 24 and 16 term limits when using the on-chip Complement Array.
The worst case of t1s for a given application can be determined by identifying the OR line with the maximum numberolTnconnections. This can be done by referring to the interconnect pattern in the PLS logic diagram, typically illustrated in Figure 3, or by counting the maximum number of "H" or "L" entries in one of the columns of the device Program Table.
This number plotted on the curve in Figure 1 or 2 will yield the worst case t1s and, by implication, the maximum clocking frequency for reliable operation.
Note that for maximum speed all UNUSED transition terms shouldbe disconnectedfrom the OR array

(4)6ffig} TRANSITION TERMS Tn

TERMS/ OR (2)

"OR" ARRAY

(3)

NOT USED

Figure 3. Typical OR Array Interconnect Pattern

October 22, 1993

292

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (12x48x8)

Product specification
PLS168/A

LOGIC PROGRAMMING
The PLS168/A devices are fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors' SNAP design software package. ABEL'"· CUPL'· and PALASM® 90 design software packages also support the PLS168/A architecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.

PLS168/A logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors SNAP PLD design software package.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.

PRESET/OE OPTION - J_P/Eil_

p~R/OE

E:1

LWAYS

'::'

ENABLED)

OPTION PRESET1

CODE H

OPTION

CODE L

PROGRAMMING: The PLS168/A has a power-up preset feature. This feature insures that the device will power-up in a known state with all register elements (State and Output Register) at logic High (H). When programming the device it is important to realize this is the initial state of the device. You must provide a next state jump if you do not wish to use all Highs (H) as the present state.

"AND" ARRAY - (I), (P)

PROGRAMMING AND
SOFTWARE SUPPORT Refer to Section 9 (Development Software)
and Section 10 (Third-party/ Programmer/ Software Suppon) of this data handbook for additional information.

L STATE

I CODE ]

l ( INACTIVE1· 2

0 l

"OR" ARRAY - (N), (F)

"'fg[J-'

n,l

R

L l ACTION
I j [ INACTIVE1· 3

CODE 0

"'fg[J-'

n,l

R

I

ACTION SET

I I CODE H

"fg[J-'

ii;l

R

I

ACTION RESET

I I CODE L

"fg[J-'

ii;l

R

I I - I ACTION NO CHANGE

CODE

a : a : a : a : "COMPLEMENT"ARRAY- (C)

t Ij ACTION INACTIVE1· 4

Tn
j CODE 0

I ACTION GENERATE

Tn
I I CODE A

L l ACTION I [ PROPAGATE

Tn
J CODE · J

L I ACTION
j [ TRANSPARENT

Tn
J CODE -J

NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate Tn will be unconditionally inhibited if both the true and complement of any input (I, P) are left intact. 3. To prevent simultaneous Set and Reset flip-flop commands, this state is not allowed for N and Flink pairs coupled to active gates Tn (see
flip-flop truth tables). 4. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn·

October 22, 1993

293

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(12 x 48 x 8)

Product specification
PLS168/A

PROGRAM TABLE

CUSTOMER NAME_ _ _ _ _ _ _ _ _ __ PURCHASE ORDER#_ _ _ _ _ _ _ _ _~

PHILIPS DEVICE #_ _ _ _ _C_F_,..(X'-X_,_X'-'X,_)- - - CUSTOMER SYMBOLIZED PART#_ _ _ _ _ __ TOTAL NUMBER OF PARTS_ _ _ _ _ _ _ __ PROGRAM TABLE_ _ _ _ _ _ _ _ _ _ __

- - - - - REV
0ATE_ _ _ _

-_-_-_-_-_-_-_ -

_ -

-_-_-_-~ -

PROGRAM TABLE ENTRIES

AND

T

OR .

------------1-----------~

INACTIVE

0

I INACTIVE

0

GENERATE

A

PROPAGATE

·

TRANSPARENT' -

I Cn I
I

SET RESET NO CHANGE

H

Ns, Fr

L

-

INACTIVE

o

l,P

· H

-~~N'T CARE ' .'.:_

L-----------~

l'-----~!!~-------!

1,.. Ps 1 ~=ESET

~ !

I PIE

AND

~ ~

I

OR

INPUT(lm)

PRESENT STATE (P8 )

REMARKS

NEXT STATE (Ns)

OUTPUT (Fr)

s TERM Cn 11 1o -9 8.L1- -6 ..i. ([3 2 1 0 9 8 7 6 5 ( [3 2 :i -0 - - - - - - - - - - -. ii i -6

ti3- 2 ; ::ii -3 ;; 1- -o

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35 36

' '

37 38

' '

39

40

41

42

43

44 45 46 47

' ' ' '

PIN NO. 18 19 20 21 22 23 2 3 4 5 6 7

' ' ' ' '
' ' I '
16 15 14 13 11 10 9 8

w ...J w
IsaD: <:zii :;!:

NOTES:
1. The device is shipped with all links initially intact. Thus, a background of "O" for all Terms, and an "H" for the PIE option, exists in the table, shown BU\NK instead for clarity.
2. Unused C0 , Im. and Ps bits are normally programmed Don't Care(-).
3. Unused Transition Terms can be left blank for future code modification, or programmed as(-) for maximum speed. 4. Letters in variable fields are used as identifiers by logic type programmers.

October 22, 1993

294

Philips SemiconduclDrs Programmable Logic Devices
Programmable logic sequencers (12 x 48 x 8)

Product specification
PLS168/A

TEST ARRAY
The PLS may be subjected to AC and DC parametric tests prior ID programming via an on-chip test array.
The array consists of test transition terms 48 and 49, factory programmed as shown below.
Testing is accomplished by clocking the FPLS and applying the proper input sequence to 10-13 as shown in the test circuit timing diagram.

T

E

R M

Cn

48

A

48

AND

Both terms 48 and 49 must be deleted during user programming ID avoid interfering with the desired logic function. This is accomplished automatically by any Signetic's qualified(rogramming equipment.
I

T

E

R M

Cn

48 49

AND

OclDber 22, 1993

State Diagram

Vee .sv Vee

GND

l'0-3 Fr

FPLS Under Test
H

Test Array Program

Vee

CLK 10-11

Rl-3
STATE REGISTER

Test Circuit Timing Diagram

+SV
ov
av ov
HIGH LOW

Test Array Deleted 295

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(12 x 48 x 8)
SNAP RESOURCE SUMMARY DESIGNATIONS

Product specification
PLS168/A

October 22, 1993

296

Phillps Semiconductors Programmable Logic Devices
Programmable logic sequencer
(20 x 45 x 12)

Product specification
PLS179

DESCRIPTION
The PLS 179 is a 3-State output, registered logic element combining AND/OR gate arrays with clocked J-K flip-flops. These J-K flip-flops are dynamically convertible to D-type via a "foldback" inverting buffer and control gate, Fe. It features 8 registered 1/0 outputs (F) in conjunction with 4 bidirectional 110 lines (8). There are 8 dedicated inputs. These yield variable 1/0 gate and register configurations via control gates (D, L) ranging from 20 inputs to 12 outputs.
The AND/OR arrays consist of 32 logic AND gates, 13 control AND gates, and 21 OR gates with fusible link connections for programming 1/0 polarity and direction. All AND gates are linked to 8 inputs (I). bidirectional 1/0 lines (B), internal flip-flop outputs (0), and the Complement Array output (C} The Complement Array consists of a NOR gate optionally linked to all AND gates for generating and propagating complementary AND terms.
On-chip TIC buffers couple either True (I, B, 0) or Complement (T, B, 0, 'C) input polarities to all AND gates, whose outputs can be optionally linked to all OR gates. Any of the 32 AND gates can drive bidirectional 1/0 lines (8), whose output polarity is individually programmable through a set of EX-OR gates for implementing AND-OR or AND-NOR logic functions. Similarly, any of the 32 AND gates can drive the J-K inputs of all flip-flops. Four AND gates have been dedicated for the Asynchronous PreseVReset functions.
All flip-flops are positive edge-triggered and can be used as input, output or 110 (for interfacing with a bidirectional data bus) in conjunction with load control gates (L), steering inputs (I), (B), (Q) and programmable output select lines (E).
The PLS179 is field programmable, enabling the user to quickly generate custom patterns using standard programming equipment.
Order codes are listed below.

FEATURES e IMAX= 18.2MHz
- 25MHz clock rate · Field-Programmable (Ni-Cr link) · 8 dedicated inputs · 13 control gates · 32 AND gates · 21 OR gates · 45 product terms:
- 32 logic terms - 13 control terms · 4 bidirectional 1/0 lines · 8 bidirectional registers · J/K, T, or D-type flip-flops · Asynchronous PreseVReset · Complement Array · Active-High or-Low outputs · Programmable OE control · Positive edge-triggered clock · Power-on reset on flip-flop
<Fn = "1")
·Input loading: -100µA (max.) ·Power dissipation: 750mW (typ.) · TTL compatible · 3-State outputs

ORDERING INFORMATION
DESCRIPTION 24-Pin Plastic Dual In-Line Package (300mil-wide) 28-Pin Plastic Leaded Chip Carrier

ORDER CODE PLS179N PLS179A

PIN CONFIGURATIONS
N Package

BO BT GND

Vee B3 F7 F6 FS F4 F3 F2 FT FO B2 OE

N = Plastic Dual In-Line Package (300mil-wide)
A Package
12 11 IO CLK Vee B3 F7

NIC F& FS F4 F3 F2 NIC

A= Plastic Leaded Chip Carrier

APPLICATIONS
· Random sequential logic · Synchronous up/down counters · Shift registers · Bidirectional data buffers · 1iming function generators · System controllers/synchronizers · Priority encoder/registers

DRAWING NUMBER 0410D 0401F

October 22, 1993

297

853-0862 11164

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(20 x 45 x 12)
LOGIC DIAGRAM
IO 11 12
17

Product specification
PLS179
1,, ---<1-113 tlE

31 · · · · · ·24 23· · · · · ·16 15· · · · · · 8 7 · · · · · · o Fe
NOTES:
1. All OR gate inputs with a blown link float to logic "O". 2. All other gates and control inputs with a blown link float to logic "1". 3. E9 denotes WIRE-OR. 4. ,f10 Programmable connec1ion.

October 22, 1993

298

CK'~CLK

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (20 x 45 x 12)

Product specification
PLS179

FUNCTIONAL DIAGRAM

(LOGIC TERMS)

(CONTROL TERMS) Pe Re PA RA Le LA

D

EA Ee

a

i b

1-

6

<1---i

_.;:::1-i

r-..

0-t---t---t---------t---11 Q-f----+--f---------+-+-

-

+- --t+- --t--f--t----+t -----+t --:<7_N1Q

rV

t:

LQt--t--------+----t- c

I~ (

S

>-~-_..-.~L>...--..,-,.._

'p--'R

v

e

.:b

J oI-+---+---+-+----+-t--+---1~

l . M-+----Or·I

(4)

->----+--+-I

~-""- '--K--<-J---1--+r-CK-t-<~ lC 1,_..__----+--<>--~

'------+---+-~-

I M -=

T 31

T Fc

H
J Q
(4)
1 '-- '1- K <!---CK

CK~CLK

FLIP-FLOP TRUTH TABLE

OE L CK p R J K Q F

H

H/Hi-Z

L x x xxxxL H L x x H L xxH L
L x x L HxxL H

a L L i L L L L

0

L L i LL LHL H

L L i L LHLH

L

a L L i L L H H 0

H H i L L L H L H*

H H i L L H L H L*

x +10V x i

x L H L H**

x i x x H L H L* ·

NOTES:
1. Positive Logic: J-K =To+ T1 + T2 .................. T31 T.l' = ~· (10 · 11·12 ...) · (Oo · 01 ...) · (l:lO· B1 · ...)
2. i denotes transition from Low to High level.
3. X = Don't care 4. · = Forced at Fn pin for loading the J-K
flip-flop in the Input mode. The load
control term, Ln must be enabled (HIGH)
and the p-terms that are connected to the
associated flip-flop must be forced LOW
(disabled) during Preload.
5. At P = R = H, Q = H. The final state of Q
depends on which is released first. 6. · · = Forced at Fn pin to load J-K flip-flop
independent of program code (Diagnostic mode), 3-State B outputs.

nrtnhP.r ?2 1993

299

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (20 x 45 x 12)

Product specification
PLS179

LOGIC FUNCTION

~ 1 ~ ~\o ~R 3

1

1

1

PRESENT STATE

I t STATE REGISTER

o Io Io

I

Sn+·

J( · IJ · C · ... NEXTSTATE

SETOo:Jo= (<l3. "O:?. o,. t!o>-X · IJ· c ... Ko=O
RESET01:J1 =0
K1 =(Qa· "02 · 01 · t!o>" J( · IJ· C·..
HOLD~:JpO
K2 =0
TOGGLE 03: J3= (03 · "0:? · 01 · °Qo)" J(· IJ· C ··· K3= (<l3· "O:? ·o1 · "00)" X· IJ · c ...
NOTE: Similar logic functions are applicable for D and T mode flip-flops.

VIRGIN STATE The factory shipped virgin device contains all fusible links intact, such that: 1. OE is always enabled.
2. Preset and Reset are always disabled.
3. All transition terms are disabled.
4. All flip-flops are in D-mode unless otherwise programmed to J-K only or J-K or D (controlled).
5. All B pins are inputs and all F pins are outputs unless otherwise programmed.

THERMAL RATINGS TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal rise ambient to junction

1so0 c 75°C 75°C

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee V1N Vour l1N

Supply voltage Input voltage Output voltage Input currents

+7

Voe

+5.5

Voe

+5.5

VDc

-30

+30

mA

lour

Output currents

+100

mA

Tamb

Operating temperature range

0

+75

oc

T!!a.

Storage temperature range

-65

+150

oc

NOTES:

1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these

or any other condition above those indicated in the operational and programming specification of the device is not implied.

October 22, 1993

300

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(20 x 45 x 12)

Product specification
PLS179

DC ELECTRICAL CHARACTERISTICS
0°C S Tamb S +75°C, 4.75V S Vee S 5.25V

SYMBOL

PARAMETER

Input voltage2

V1H

High

V1L

Low

Vic

Clamp

Output voltage2

VoH

High

VoL

Low5

Input current

TEST CONDITION
Vee=MAX Vee=Mln Vee= MIN, l1N = -12mA
Vee= MIN, loH = -2mA loL = 10mA

l1H

High

l1L

Low

Output current

Vee= MAX, V1N = 5.5V V1N = 0.45V

lo(OFF)

Hi-Z state4. 7

las

Short circuit3· 5

Ice

Vcc supply current6

Capacitance

Vee =MAX, VouT = 5.5V VouT = 0.45V VouT =OV
Vee= MAX

C1N CouT

Input Output

Vee= 5.0V, V1N = 2.0V VouT=2.0V

NOTES:
1. All typical values are at Vee= 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time.
4. Measured with V1H applied to OE
5. Duration of short circuit should not exceed 1 second.
6. Ice is measured with the OE input grounded, all other inputs at 4.5V and the outputs open. 7. Leakage values are a combination of input and output leakage.

LIMITS MIN TYP1 MAX

2.0

0.8

--0.8

-1.2

2.4

0.35

0.5

UNIT
v v v v v

<1

40

µA

-10

-100

µA

1

80

µA

-140

µA

-15

-70

mA

150

210

mA

8

pf

15

pf

October 22, 1993

301

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(20 x 45 x 12)

Product specification
PLS179

AC ELECTRICAL CHARACTERISTICS

R1 = 470Q, R2 = 1kQ, CL= 30pF, 0°C s Tamb s +75°C, 4.75°CV S Vee s 5.25V

SYMBOL

PARAMETER

FROM

TO

TEST

LIMITS

UNIT

CONDITION

MIN5 TYP1 MAX

Pulse width3

lcKH

Clock2 High

lcKL

Clock Low

lcKP

Clock period

tPRH

Preset/Reset pulse

CK+

CK-

CL= 30pF

20

15

ns

CK-

CK+

CL= 30pF

20

15

ns

CK+

CK+

CL= 30pF

40

30

ns

(I, 8)-

(I, 8)+

CL= 30pF

35

30

ns

Setup time

t1s1

Input

(1,8)±

CK+

CL =30pF

35

30

ns

t1s2

Input (through Fn)

F±

CK+

CL= 30pF

15

10

ns

t1s3

Input (through Complement Array)4

(I, 8)±

CK+

CL= 30pF

55

45

ns

Hold time

t1H1

Input

(1,8)±

CK+

CL= 30pF

0

-5

ns

l1H2

Input (through Fn)

F±

CK+

CL =30pF

15

10

ns

Propagation delay

lcKO

Clock

loE1

Output enable3

too1

Output disable3

!po

Output

CK±

F±

OE-

F-

OE+

F+

(I, 8)±

8±

CL= 30pF CL= 30pF CL= 5pF CL= 30pF

15

20

ns

20

30

ns

20

30

ns

25

35

ns

loE2

Output enable3

!oo2

Output disable3

(I, 8)+

8±

(I, 8)-

8+

CL= 30pF CL= 5pF

20

30

ns

20

30

ns

lpRQ

Preset/Reset

(I, 8) +

F±

CL= 30pF

35

45

ns

lppR

Power-on preset

Vee+

F-

CL= 30pF

0

10

ns

NOTES:

1. All typical values are at Vee= 5V, Tamil= +25°C.
2. To prevent spurious clocking, clock rise time (10% - 90%) s 1Ons.
3. For 3-State output; output enable times are tested with CL= 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output
voltage of Vr = (VoH -0.5V) with S1open, and Low-to-High impedance tests are made to the Vr = (Vol+ 0.5V) level with S1closed. 4. When using the Complement Array lcKP = 75ns (min). 5. Limits are guaranteed with 12 product terms maximum connected to each sum term line.

VOLTAGE WAVEFORMS

TEST LOAD CIRCUIT

MEASUREMENTS: All circuit delays are measured at the+ 1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses

cyc 1

2

INPUTS

NOTE:
C1 and C2 are to bypass Vee to GND.

Vee t::___.>

OE

lo

By

In OUT Bw

R1

R2

CL

Bz
"::'

OUTPUTS "::'

October 22, 1993

302

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (20 x 45 x 12)

Product specification
PLS179

TIMING DIAGRAMS
l,B (INPUTS)
CLK F
(OUTPUTS)
Flip-Flop Outputs

+3V ov +3V 1.SV ov
YOH
Vol +3V
ov

B (OUTPUTS)

Gate Outputs

. . . .------~-------~-~-~-~+sv 4.SV

Vee
F (OUTPUTS)

ov ~~~~~~~~~~~~~~~~~~~~~~~
IPPR

l,B (INPUTS)

,__ _ _ +3V 1.SV

Power-On Reset

TIMING DEFINITIONS

SYMBOL

PARAMETER

lcKH

Width of input clock pulse.

lcKL

Interval between clock pulses.

Minimum guaranteed Clock

lcKP

period.

lpRH

Width of preset input pulse.

Required delay between

t1s1

beginning of valid input and

positive transition of clock.

Required delay between

beginning of valid input forced

t1s2

at flip-flop output pins, and

positive transition of clock.

Required delay between

t1H1

positive transition of clock and

end of valid input data.

Required delay between

positive transition of clock and

t1H2

end ol valid input data forced

at flip-flop output pins.

lcKO

Delay between positive transition of clock and when outputs become valid (with OE Low).

Delay between beginning of

loE1

Output Enable Low and when

outputs become valid.

Delay between beginning of

Output Enable High and

too1

when outputs are in the

OFF-State .

Delay between Vee (after

tppR

power-on) and when flip-flop outputs become preset at "1"

(internal Q outputs at "O").

Propagation delay between

tpo

combinational inputs and

outputs.

Delay between predefined

Output Enable High, and

loE2

when combinational Outputs

become valid.

Delay between predefined

Output Enable Low and when

too2

combinational Outputs are in

the OFF-State.

lpRQ

Delay between positive transition of predefined Preset/Reset input, and when flip-flop outputs become valid.

October 22, 1993

303

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(20 x 45 x 12)

TIMING DIAGRAMS (Continued)
+3V l,B (INPUTS)
ov

+3V CLK
ov

+3V
PRESET/RESET
ov
(I, B INPUTS)

a

(PRESET)

'--_J~i:=_~--'

....._ tpRQ F (OUTPUTS) - - - - - - - - - - - - - '

(PRESET)

VoH

· Preset and Reset functions override Clock. However, F outputs may glitch with the first positive Clock Edge if t1s1 cannot be guaranteed by the user.

Asynchronous Presel/Reset

I, B (LOAD SELECT)

1.SV

+3V
1.SV
ov

+3V
1.5V
ov

1r------
-t-
-------JI

', '--

I

~-+-------..!,.------,. , - - ; - - - - +3V VoH
F

- (INPUTS) -+-------'

ov VOL

+3V CLK
tcKH
Q~~~~~~~==

Flip-Flop Input Mode

October 22, 1993

304

Product specification
PLS179

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (20x45x 12)

Product specification
PLS179

LOGIC PROGRAMMING The PLS179 is fully supported by industry
standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors' SNAP, Data 1/0 Corporation's ABELTM and Logical Devices lnc.'s CUPLTM design software packages.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.

PLS179 logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors SNAP PLD design software package.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE,

COMPLEMENT, INACTIVE, PRESET, etc., are defined below.
PROGRAMMING AND SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 1O(Third-party Programmer/ Software Support) of this data handbook for additional information.

"AND" ARRAY - (1), (8), (Qp)

~¢'" ~,., 1,8,0

- - - ~~Q 1,8,Q

--1,8,Q

~"' 1,8,Q

--1,8,Q

~--' 1,8,Q

--1,8,Q

(T, Fe. l, P, R, D)n

l 1 STATE

]

INACTIVE1, 2

CODE] 0

(T, Fe, l, P, R, D)n

STATE
I 1,8,Q

I I CODE H

(T, Fe. l, P, R, D)n

STATE
I i,8,Q

I I CODE L

(T, Fe, l, P, R, D)n

1 l STATE

CODE

f 1 - 1 DONT CARE

"COMPLEMENT" ARRAY - (C)
c:t: c:t:

(Tn,Fcl

l I J ACTION T l [ INACTIVE1,3,S

CODE 0

(Tn,Fcl

r T J ACTION

CODE

r J GENERATE5 ]

A

c:t:

(Tn,Fcl

[ 1 J ACTION

CODE

l l · J PROPAGATE

c:t:

<Tn,Fcl

r T l ACTION I - J [ TRANSPARENT

CODE

"OR" ARRAY - (F-F CONTROL MODE)

"OR" ARRAY - (Qn = D-Type)

Q

Q

ACTION
J-KORD (CONTROLLED)

CODE A

Notes on following page.

ACTION J-K

CODE
·

T0 STATUS ACTIVE (Set)1

CODE A

Tn STATUS INACTIVE (Reset)

CODE ·

October 22, 1993

305

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(20 x 45 x 12)

"AND" ARRAY - (QN = J-K Type)

Q

Q

Product specification
PLS179

Q

Q

ACTION TOGGLE

CODE 0

"OR" ARRAY - (S or B)

ACTION SET

CODE H

ACTION RESET

CODE L

"EX-OR" ARRAY - (B)

ACTION HOLD

CODE

~IP,R,S L-/

(ORB)

~IP,R,S L-/

(ORB)

TnSTATUS
l ACTIVE2

A J

"OE" ARRAY - (E)
~~

[ l J Tn STATUS

CODE

l l . J INACTIVE

~~

POLARITY LOW1

J j CODE j LJ

POLARITY HIGH

l J CODE
l HJ

~o~ ~~

En

En

En

r 1 J ACTION

CODE

l

IDLE1· 4

]

0 J

l

ACTION CONTROL

l J CODE

J ]

A

l

ACTION ENABLE4

J j CODE ] ·J

ACTION
t DISABLE

NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates. 2. Any gate (T, Fe, L, P, R, D)n will be unconditionally inhibited if any one of the I, B, or Q link pairs are left intact. 3. To prevent oscillations, this state is not allowed for Clink pairs coupled to active gates Tn. Fe. 4. En= 0 and En =·are logically equivalent states, since both cause Fn outputs to be unconditionally enabled. 5. These states are not allowed for control gates (L, P, R, D)n due to their lack of "OR" array links.

En
J j CODE l -J

October 22, 1993

306

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(20 x 45 x 12)

Product specification
PLS179

PROGRAM TABLE

AND

I

OR

I

CONTROL

I NOTES

- - - - - - - - - 1 , - - - - - - - - 1 - - - - - - - - - - - - - - - - - i 1. Thedevk,. ~sh;ppedwnhall l;nks ;ntact. Thus aback·

INACTIVE Io]

J I lJtK J [ACTIVE A P. R, 8(0)

J_ · F/F

I

ground of entries corresponding to stales of virgin links ex·

1,8,Q

HJ ·J I Io 1,8(1).J LINACTIVE

(O·D) 'lJ/KorD AJMODE IDLE

I

;s1s;nthetable,shown8LANKforclarny.

T. S. 0

I L] O(P)

I (contrdledJl

CONTROrj_ A

I 2. Program unused C, I, 8, and Q bits in the AND array as(-).

-J DON'TCARE

I

I

ENABLE I· EA,BI ~;~~~~su=~~~,P,andRbitsintheORarrayas(-)

I

,_IN~AC~T~IV~E~~~o...

I TOGGLE

l i-=GE~N~E~R~AT~E~i-'-'A-1 c I SET

~:A~~~~~:~ I ~

:~~~T

0

I I
I HIGH

l H (O. JIK) I . LOW
=

I IHL (POL)
. ·

DISABLE_l -

I 3. Unused Terms can be left blank.

I a a 4. (P) and (N) are respectively the present and next states

- - - - . . - - - - - - , . - - - - - 1 ..------..l...___0_1_11_;p....,11,...ops....,.a_.

FIF MODE

Ee

EA

POLARITY

T

AND

(OR)

(/)

E R M

c1-:c,.,--,...,...s-.--.~1-·....,...-2.,....1..,...o-t·--.,--2""'e~(l!'-T--o+-1-.-&-r·-...-~~(~P·)~.,....,.2-.-1....,...-to

Q(N)

8(0)

765432103 2 1 0

(.)
;::::

w z

~
u;

>
Ill

0 w

=II:

w~ _,

a~::

Q.
:; 0
(.)
w

~ 0 w
N
::i

10 11 12

Ill

0

13

0
~
z
;0:::: a:
0
Q.
:c(/)

x x x
~ u..

:Il;l >
(/)
:aw::;:
0
~ (/)
:::>

0 w > iii a(w.:): w
!;;:

:zw~:;
::; 0

14 15 16 17 18 19 20

~ (.) (.) 0 (.)

21

22

23

24

25

26

27

w
!;;:

28 29

0

30

31

Fe

I Pe

a>w::

l--"'!IL"Yf-1---l-+-+-+-+-+--+--l--l--l--l--l-+-+-+-~1--1---1-llt--- L 9

:w;
z<(
:aw:::
~
(/)
:::>
(.)

=II:
aw:: 0a::
0
w
(/) <(
:c (a.:):
:::>
Q.

=II:
w
(.)
> w
0
(/) (.)
;:::: z w u~ ;

~a:: ~
u..
0
aw :
:Il:l
:z_::>,
~
0
~

I
=II:
_w ,
Ill
~
::
<(
a::
~
0a::
Q.

D3 02 01 DO
PIN

9 8 7 6 5 4 3 2 23 14 11 10 22 21 20 19 18 17 16 15

October 22, 1993

307

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (20 x 45 x 12)

SNAP RESOURCE SUMMARY DESIGNATIONS

(LOGIC TERMS)

(CONTROL TERMS)

t~~~-+--------+--~P-e +R-e-~PA--RA+--Le+-L-A +-D

;r;~t?:·:)~:

·

b

Product specification
PLS179

B
F
CK~CLK

October 22, 1993

308

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLO (42x105x12)

Product specification
PLC42VA12

DESCRIPTION
The new PLC42VA12 CMOS PLD from Philips Semiconductors exhibits a unique combination of the two architectural concepts that revolutionized the PLD marketplace.
The Philips Semiconductors unique Output Macro Cell (OMC) embodies all the advantages and none of the disadvantages associated with the "V" type Output Macro Cell devices. This new design, combined with added functionality of two programmable arrays, represents a significant advancement in the configurability and efficiency of multi-function PLDs.
The most significant improvement in the Output Macro Cell structure is the implementation of the register bypass function. Any of the 10 J-K/D registers can be individually bypassed, thus creating a combinatorial 1/0 path from the AND array to the output pin. Unlike other "V" type devices, the register in the PLC42VA 12 Macro Cell remains fully functional as a buried register. Both the combinatorial 1/0 and buried register have separate input paths (from the AND array). In most V-type architectures, the register is lost as a resource when the cell is configured as a combinatorial 1/0. This feature provides the capability to operate the buried register independently from the combinatorial 1/0.
The PLC42VA 12 is an EPROM-based CMOS device. Designs can be generated using Philips Semiconductors SNAP PLD design software packages or one of several other commercially available JEDEC standard PLD design software packages.

FEATURES
· High-speed EPROM-based CMOS Multi-Function PLD - Super set of 22V10, 32VX10 and 20RA 10 PAL® ICs
· Two fully programmable arrays eliminate "P-term Depletion" - Up to 64 P-terms per OR function
· Improved Output Macro Cell Structure - Individually programmable as: · Registered Output with feedback · Registered Input · Combinatorial 1/0 with Buried Register · Dedicated 1/0 with feedback · Dedicated Input (combinatorial) - Bypassed Registers are 100% functional with separate input and feedback paths - Individual Output Enable control functions · From pin or AND array
· Reprogrammable - 100% tested for programmability
· Eleven clock sources
· Register Preload and Diagnostic Test Mode Features
· Security fuse
APPLICATIONS
· Mealy or Moore State Machines - Synchronous - Asynchronous
· Multiple, independent State Machines
· 10-bit ripple cascade
· Sequence recognition
· Bus Protocol generation
· Industrial control
· AID Scanning

PIN CONFIGURATIONS
FA and N Packages

BO GND

Vee M9 M8 M7 MS MS M4 M3 M2 M1 MO 19/0E

N = Plastic DIP (300mil-wide) FA= Ceramic DIP with Quartz Window (300mi1-wide)

A Package
10/ 12 11 CLKN!C Vee M9 M8
M7 M6 MS N/C M4 M3 M2
BO B1 GND N/C 19/ MO M1 OE
A"' Plastic Leaded Chip Carrier (450mil-square)

ORDERING INFORMATION
DESCRIPTION
24-Pin Ceramic Dual In-Line with w.indow, Reprogrammable (300mil-wide)
24-Pin Plastic Dual In-Line, One Time Programmable (300mil-wide)
28-Pin Plastic Leaded Chip Carrier, One Time Programmable (450mil-wide)

ORDER CODE PLC42VA12FA PLC42VA12N PLC42VA12A

DRAWING NUMBER 1478A 0410D 0401F

PAL is a registered trademark of Advanced Micro Devices, Inc.

October 22, 1993

309

853-141411164

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD (42 x 105 x 12}
LOGIC DIAGRAM

Product specification
PLC42VA12

NOTE: ,:$ Programmable '~tV Connection

October 22, 1993

310

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLO
(42 x 105 x 12)

LOGIC DIAGRAM (Continued)

CCC

RRRRC CCC

PRPR C C l LDDDD DODD

DD

KKK l

PMMMMK KKK l MMMM K K MMMMMM MMMM

MM

7 65 A

943214 321 B 9900 9 0 901234 5678

09

Product specification
PLC42VA12

October 22, 1993

311

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLO
(42 x 105 x 12)

Product specification
PLC42VA12

FUNCTIONAL DIAGRAM

P63 ··· Po 11-18
~
.---12 .---12
~ ...

Fe

LI.In PM,, RMn CKn DI.In

DBn

..s

--"' xa
..s
~ - "
~t-

X2 X8 X8

xa X2 X2 X2 X2

X2

X2

J'r~
t i j;--R

N r)rol

'~%7'

J CK

~

l X8

KX8Q~ OMC
"-c~

~4:1(X2)
I~

POLAR~l_V

" ~
i l "'p-R

NTROI

I..!:/ ..t:J'
l X2

'n"~l! >- K Q OMC
.....___ c~

t-
n-::- X2
=

POLARlvl!Y

~

..lg../.O. E
'ofCLK
.....
M1~M8
MO,M9
-u

POLAR1iJLS>

r v

B0-81
-u

October 22, 1993

312

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLO (42 x 105 x 12)

Product specification
PLC42VA12

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

PARAMETER

RATINGS

UNIT

Vee

Supply voltage

-0.5 to +7

Vrx;

V1N

Input voltage

-0.5 to Vee +0.5

Vrx;

Vour

Output voltage

-0.5 to Vee +0.5

Vrx;

l1N

Input currents

-10to+10

mA

lour lamb Tstg

Output currents Operating temperature range Storage temperature range

+24

mA

Oto +75

oc

-65to +150

oc

NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS
TEMPERATURE Maximum junction Maximum ambient
Allowable thermal rise ambient to junction

AC TEST CONDITIONS

VOLTAGE WAVEFORMS

c 1so0
75°C
75°C

Vee

INPUTS
NOTE:
C1 and C2 are to bypass Vee to GND.

"OE

'"

Mz

'" OUT
BM

BM

Mz

CK GND

=

Test Load Circuit

Rt CL
= OUTPUTS

MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLO (42x105x12)

Product specification
PLC42VA12

DC ELECTRICAL CHARACTERISTICS
0°C s Tamb S +75°C, 4.75Y S Yee S 5.25Y

SYMBOL Input voltage:?

PARAMETER

TEST CONDITION

MIN

Y1L

Low

V1H

High

Output vollage2

Yee= MIN Yee= MAX

--0.3 2.0

VaL

Low

VoH

High

Input current

l1L

Low

l1H

High

Output current

Vee= MIN; loL = 16mA

Vee= MIN; loH = -.'3.2mA

2.4

Y1N =GND V1N =Vee

lo(OFF}

Hi-Zstate

Your= Vee VouT = GND

las

Short-circuit3.7

Your= GND

lcc1

Vee supply current (Active)4

lour= OmA, f = 15MHz6 , Vee= MAX

lcc2

Vee supply current (Active)5

Capacitance

lour= OmA, f = 15MHz6, Vee= MAX

C1

Input

Vee = 5V; V1N = 2.0V

Ca

1/0

Va= 2.0V

NOTES:

1. All typical values are at Vee = 5V. Tarrti = +25°C.

2. All voltage values are with respect to network ground terminal.

3. Duration of short-circuit should not exceed one second. Test one at a time.

4. Tested with V1L = 0.45Y, V1H = 2.4V.

5. Tested with V1L = OV, V1H =Vee.

6. Refer to Figure 1, t.lcc vs Frequency (worst case). (Referenced from 15MHz)

The Ice increases by 1.5mA per MHz for the frequency range of 16MHz up to 25MHz.

The Ice remains at a worst case for the frequency range of 26MHz up to 37MHz.

The Ice decreases by 1.0mA per MHz for the frequency range of 14MHz down to 1MHz.

The worst case Ice is calculated as follows:

- All dedicated inputs are switching.

- All OMCs are configured as JK flip-flops in the toggle mode...all are toggling. - All 12 outputs are disabled.

- The number of product terms connected does not impact the Ice. 7. Refer to Figure 2 for t.lpo vs output capacitance loading.

LIMITS TYP1

MAX

0.8 Vee +0.3

0.3

0.5

4.3

-1

-10

+1

10

1

10

-1

-10

-130

90

120

70

100

12 15

UNIT
v
y
v v
µA µA
~
mA mA mA
pF pF

+30

+25

+20

+15
l +10
8 <i +5

;ZJ
~

l Z -5 l Z ~ -10
-15

1

10 15 20 25 30 35 40

~MHz)

Figure 1. t.lcc vs Frequency (Worst Case) (Referenced from 15MHz)

-1 I .'1 -2 ILJ
0 20 40 60 80 100 120 140 160 180 200 OUTPUT CAPACITANCE LOADING (pf)
Figure 2. C.tp0 vs Output Capacitance Loading (Typical)

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLO (42x105x12)

Product specification
PLC42VA12

AC ELECTRICAL CHARACTERISTICS
0°C s Tarro s +75°C, 4.75V s Vee S5.25V; R1 =238Q, R2 = 170Q

SYMBOL

PARAMETER

FROM

TO

Set-up Time

l1s1 t1s2 t1s33 t1S43

Input; dedicated clock Input; P-term clock Preload; dedicated clock Preload; P-term clock

t1ss3

Input through complement array; dedicated clock

t1ss3

Input through complement array; P-terrn clock

Propagation Delay

tpo1

Propagation Delay

Propagation Delay with complement

lpo2

array (2 passes)

lcK01 lcK02
tRP1

Clock to Output; Dedicated clock
Clock to output; P-term clock Registered operating period; Dedicated clock (t1s1 + lcK01)

Registered operating period;

tRP2

P-term clock (t1s2 + lcK02)

tRp}

Register preload operating period; Dedicated clock (t1s3 + lcK01)

tRP43

Register preload operating period; P-term clock (t1S4 + lcK02)

tRP53

Registered operating period with complement array; dedicated clock (tis5 + tcK01)

tRP63
loE1 loE2

Registered operating period with complement array; P-term clock (t1ss + lcK02) Output Enable; from /OE pin4
Output Enable; from P-term4

loo1

Output Disable; from /OE pin4

loo2

Output Disable; from P-term4

tPR03

Preset to Output

tppR3

Power-on Reset( Mn= 1)

Hold lime

t1H1

Input (Dedicated clock)

t1H2

Input (P-term clock)

tlH33

Input; from Mn (Dedicated clock)

tlH43

Input; from Mn (P-term clock)

Pulse Width

lcKH1

Clock High; Dedicated clock

!cKL1

Clock Low; Dedicated clock

lcKH2

Clock High; P-term clock

lcKL2

Clock Low; P-term clock

tPRH3

Width of preseVreset input pulse

Notes on page 316.

(I, B, M)+/(l,B, M)+/-
(M)+/(M)+/(I, B, M)+/-
(I, B, M)+/-
(I, B, M)+/(I, B,)+/CK+
(I, B, M)+/(I, B, M)+/-
(I, B, M)+/-
(M)+/-
(M)+/-
(I, B, M)+/-
(I, B, M)+/-
/OE(I, B, M)+/-
/OE+
(I, B, M)+/(I, B, M) +/-
Vee+
CK+ (I, B, M)+/-
CK+ (I, B, M)+/-
CK+ CKCK+ CK(I, B, M)+/-

CK+ (I, B, M)+/-
CK+ (I, B, M)+/-
CK+
(I, B, M)+/-
(I, B, M) +/(I, B,M)+/-
(M)+/(M)+/(M)+/-
(M)+/-
(M)+/-
(M)+/-
(M)+/-
(M)+/-
(M)+/(B, M)+/Outputs dis-
ab led Outputs dis-
ab led (M)+/(M)+/-
(I, B, M)+/(I, B, M)+/-
(M)+/(M)+/-
CKCK+ CKCK+ (I, B, M)+/-

TEST2 CONDITION
(CL(pF))
50 50 50 50 50
50
50 50 50 50 50
50
50
50
50
50
50 50 5
5 50 50
50 50 50 50
50 50 50 50 50

PLC42VA12 MIN TYP1 MAX

23

16

20

13

10

3.5

2

-1.0

50

34

40

30

20

35

36

55

13

17

18

27

29

40

31

47

16.5

27

17

29

47

67

48

67

10

20

12.5

25

10

20

14.5

25

25

35

15

0

-13

5

-7.5

5

-1.5

10

3.5

10

5

10

5

15

7

15

7

30

7

UNIT
ns ns ns ns ns
ns
ns ns ns ns ns
ns
ns
ns
ns
ns
ns ns ns
ns ns ns
ns ns ns ns
ns ns ns ns ns

Or:tnhPr ?? 1QQ"=l

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD (42x105x12)

Product specification
PLC42VA12

AC ELECTRICAL CHARACTERISTICS (Continued) 0°C s Tamb s +75°C, 4.75V s Vee s 5.25V; R1=23Bn, R2 = 170'2

TEST2

PLC42VA12

SYMBOL

PARAMETER

FROM

TO

CONDITION (CL(pF))

MIN

TYP1 MAX

UNIT

Frequency of Operation

fcK1

Dedicated clock frequency

C+

C+

50

50

100

MHz

fcK2

P-tenn clock frequency

C+

C+

50

33

71.4

MHz

IMAX1

Registered operating frequency; Dedicated clock {~s1 + lcK01)

{I, B, M)+/-

{M)+/-

50

25

34.5

MHz

fMAX2

Registered operating frequency; P-tenn clock {t152 + lcK02l

{I, B, M) +/-

{M)+/-

50

21.3 32.3

MHz

Register preload operating

fMAX33 frequency; Dedicated clock

{M)+/-

{M)+/-

50

37

60.6

MHz

{t153 + lcK01)

Register preload operating

fMAX43 frequency; P-tenn clock

{M)+I-

{M)+/-

50

34.5 58.8

MHz

{t1s4 + lcK02)

Registered operating frequency

IMAX53 with complement array;

{I, B, M) +/-

{M)+/-

50

14.9 21.3

MHz

Dedicated clock {t1ss + lcK01 l

Registered operating frequency

fMAX63

with complement array;

{I, B,M)+/-

{M)+/-

50

14.9 20.8

MHz

P-tenn clock {t1ss + lcK02)

NOTES:

1. All typical values are at Vee= 5V, Tamb = +25°C. These limits are not tested/guaranteed.
2. Refer also to AC Test Conditions (Test Load Circuit). 3. These limits are not tested, but are characterized periodically and are guaranteed by design. 4. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = SpF. High-to-High impedance tests are made to an output
= = voltage of Vr {VoH - 0.5V) with S1open, and Low-to-High impedance tests are made to the Vr {Vol + O.SV) level with S1 closed.

BLOCK DIAGRAM

65 X 105 PROGRA MABLE AND ARRAY
I

I

I

I

64 LOGIC TERMS

j

41 CONTROL TERMS

I I I I

····

64X32 PROGRAMMABLE
OR ARRAY

IO/CLK 19.oE

October 22, 1993

316

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLO
(42 x 105 x 12)
OUTPUT MACRO CELL (OMC)

Product specification
PLC42VA12

FROM OR ARRAY ~ TO AND ARRAY

(REGISTER BYPASS)
=

Output Macro Cell Configuration
Philips Semiconductors unique Output Macro Cell design represents a significant advancement in the configurability of multi-function Programmable Logic Devices.
The PLC42VA 12 has 10 programmable Output Macro Cells. Each can be individually programmed in any of 5 basic configurations:
· Dedicated 1/0 (combinatorial) with feedback to AND array
· Dedicated Input
· Combinatorial 1/0 with feedback and Buried Register with feedback (register bypass)
· Registered Input
· Registered Output with feedback
Each of the registered options can be further customized as J-K type or D-type, with either an internally derived clock (from the AND array) or clocked from an external source. With these additional programmable options, it is possible to program each Output Macro Cell in any one of 14 different configurations.

These 14 configurations, combined with the fully programmable OR array, make the PLC42VA12 the most versatile and silicon efficient of all the Output Macro Cell-type PLDs.
The most significant Output Macro Cell (OMC) feature is the implementation of the register bypass function. Any of the 1OJ-K/D registers can be individually bypassed, thus creating a combinatorial 1/0 path from the AND array to the output pin. Unlike other Output Macro Cell-type devices, the register in the OMC is fully functional as a buried register. Furthermore, both the combinatorial 1/0 and the buried register have separate input paths (from the AND array) and separate feedback paths (to the AND array). This feature provides the capability to operate the buried register independently from the combinatorial 1/0.
The PLC42VA 12 is ideally suited for both synchronous and asynchronous logic functions. Eleven clock sources - 1Odriven from the AND array and one from an external

source - make it possible to design synchronous state machine functions, event-driven state machine functions and combinatorial (asynchronous) functions all on the same chip.
Sophisticated control functions support individual OE control and Reset functions from the AND array. OE control is also available from the 19/0E pin. Register Preset and Load functions are controlled from the AND array, in 2 banks of 4 for OMCs M1 MS. Output Macro Cells MO and M9 have individual Preset and Load Control terms.
Output Polarity for the combinatorial 1/0 paths is configurable via 12 programmable EX-OR gates. The output of each register can be configured as inverting (active Low) or non-inverting (active High) via manipulation of the logic equations.
The output of each buried register can also be configured as inverting or non-inverting via the input buffer which feeds back to the AND array.

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD (42x105x12)

OUTPUT MACRO CELL PROGRAMMABLE OPTIONS

I r

-

-

-

-

-

-

-------OUTPUT MACRO CELL

-

-

-

-

-

-

-

, I

I I

REGISTER SELECT

I ~~

CLOCK OPTIONS

I I

I

I I

OMC

II OUTPUT ENABLE

I

c~;uJ':~oN

c;;:.~1J'~i I

I

I

I

I

I P~:~~

I

I

I

IL---------------------JI

ARCHITECTURAL OPTIONS REGISTER SELECT OPTIONS

p

R

FROM OR ARRAY
FROM AND ARRAY

CLOCK OPTIONS
OMC CON FIG. OPTIONS

OUTPUT CONTROL OPTIONS

REGISTER MODE (Dor JK) D-TYPE
Fe CONTROL P-TERM

CODE A

R

FROM OR ARRAY
FROM AND ARRAY
Notes on page 323.

CLOCK OPTIONS
OMC CONFIG. OPTIONS

OUTPUT CONTROL OPTIONS

REGISTER MODE (D or JK) JK-TYPE
Fe CONTROL P-TERM

CODE ·

October 22, 1993

318

Product specification
PLC42VA12

OMC Programmable Options

For purposes of programming, the Output

Macro Cell should be considered to be

partitioned into five separate blocks. As

shown in the drawing titled "Output Macro Cell

Programmable Options", the programmable

I

blocks are: Register Select Options, Polarity

Options, Clock Options, OMC Configuration

Options and Output Enable Control Options.

There is one programmable location associated with each block except the Output Enable Control block which has two programmable fuse locations per OMC.

The following drawings detail the options associated with each programmable block. The associated programming codes are also included. The table titled "Output Macro Cell Configurations" (page 323) lists all the possible combinations of the five programmable options.

Register Select Options Each OMC Register can be configured either
as a dedicated D-type or a J-K flip-flop. The Flip-Flop Control term, Fe, provides the option to control each Register dynamically-switching from D-type to J-K type, based on the Fe control signal.
Register Preset and Reset are controlled from the AND array. Each OMC has an individual Reset Control term (RMn). The Register Preset function is controlled in two banks of 4 for OMCs M1 - M3 and M4 - MS (via the control terms PA and PB). OMCs MO and M9 have individual control terms (PMO and PM9 respectively).

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD (42 x 105 x 12)

Product specification
PLC42VA12

REGISTER SELECT OPTIONS (Continued)

p

R

Fe

FROM OR ARRAY
FROM AND ARRAY

CLOCK OPTIONS
OMC CONRG. OPTIONS

OUTPUT CONTROL OPTIONS

Fc=LOW

Fc:HIGH

POLARITY OPTIONS (for Combinatorial 1/0 Configurations Only1)

p

R

CLOCK OPTIONS
OMC CONFIG. OPTIONS

OUTPUT CONTROL OPTIONS

REGISTER MODE (D or JK) DYNAllCALLY CONTROLLABLE
Fe CONTROL P-TERM

CODE A
LorH

Polarity Options
When an OMC is configured as a Combinatorial 1/0 with Buried Register, the polarity of the combinatorial path can be programmed as Active-High or Active-Low. A configurable EX-OR gate provides polarity control.
If an OMC is configured as a Registered Output, IQ is propagated to the output pin. Note that either Q or IQ can be fedback to the AND array by manipulating the feedback logic equations. (TRUE or COMPLEMENT).

CLOCK OPTIONS
REGISTER SELECT OPTIONS

FROM OR ARRAY
TO AND ARRAY

D(ORJ) CK.<1--+----t CLK
OMC CON FIG. OPTIONS

CLKOPTIONS EXTERNAL CLOCK
(FROMPIN1)
OUTPUT CONTROL OPTIONS

REGISTER SELECT OPTIONS

CK

CLKOPTIONS

P-TERM CLOCK

CODE A
CODE
·

Clock Options
In the unprogrammed state, all Output Macro Cell clock sources are connected to the External Clock pin (lo/CLK pin 1). Each OMC can be individually programmed such that its P-tenn Clock (CK0) is enabled, thus disabling it from the External Clock and providing event-driven clocking capability.
This feature supports multiple state machines, clocked at several different rates, all on one chip, or the ability to collect large amounts of random logic, including 1Oseparately clocked flip-flops.

FROM
OR ARRAY
TO AND ARRAY
Notes on page 323.
October 22, 1993

OMC CONRG. OPTIONS

OUTPUT CONTROL OPTIONS

319

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD (42x105x12)

Product specification
PLC42VA12

OUTPUT MACRO CELL CONFIGURATION OPTIONS

REGISTER SELECT OPTIONS

REGISTER SELECT OPTIONS
FROM OR ARRAY
TO AND ARRAY

CLOCK OPTIONS
OMC CON A G . OPTIONS

FROM OR ARRAY
>- --

TO AND ARRAY

M
FROM OR
ARRAY

rCOMBINATORIAL OPTIONS

CLOCK OPTIONS

OUTPUT

CONTROL

M

OPTIONS

OMC CONAGURATION
REGISTERED OUTPLIT (DorJK)

CODE A

OMC CONAGURATION
COMBINATORIAL OUTPUT WITH BURIED REGISTER
(D orJK)

CODE
·

L

OUTPUT CONTROL OPTIONS

OMCCONAGURATION REGISTERED INPUT
LOAD CONTROL P-TERM

CODE A or · 5
HS

Notes on page 323.

OMC Configuration Options
Each OMC can be configured as a Registered Output with feedback, a Registered Input or a Combinatorial 1/0 with Buried Register. Dedicated Input and dedicated 1/0 configurations are also possible.
When the Combinatorial 1/0 option is selected, (the Register Bypass option), the Buried Register remains 100% functional, with its own inputs from the AND array and a separate feedback path. This unique feature is ideal for designing any type of state machine; synchronous Mealy-types that require both Buried and Output Registers, or asynchronous Mealy-types that require buried registers and combinatorial output functions. Both synchronous and asynchronous Moore-type state machines can also be easily accommodated with the flexible OMC structure.

Note that an OMC can be configured as either a Combinatorial 1/0 (with Buried Register) or a Registered Output with feedback and it can still be used as a Registered Input. By disabling the outputs via any OE control function, the M pin can be used as an input. When the Load Control P-term is asserted HIGH, the register is preloaded from the M pin(s). When the Le P-term is Active-Low and the output is enabled, the OMC will again function as configured (either a combinatorial 110 or a registered output with feedback). This feature is suited for synchronizing input signals prior to commencing a state sequence.

October 22. 1993

320

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLO
(42 x 105 x 12)

Product specification
PLC42VA12

OUTPUT CONTROL OPTIONS

OE

OMC

CONAG.

M

OPTIONS

TO---~. . ANDARRAY ---~;,..i-------~

OE CONTROL FUSE FROM OE PIN

E,,FUSE FROM OE PIN

CODE A

Output Enable Control Options
Similar to the Clock Options, the Output Enable Control for each OMC can be connected either to an external source (19/0E, pin 13) or controlled from the AND array (P-terms DM0). Each Output can also be permanently enabled.
Output Enable control for the two bi-directional 1/0 (B pins 10 and 11) is from the AND array only (P-terms DBO and DB1 respectively).

DM

OMC

CONAG.

M

OPTIONS

OE FUSE FROM P-TERM CONTROL

En FUSE FROM P-TERM CONTROL

CODE A or 0

OMC

CONAG.

M

OPTIONS

ANDARRATOY -- =====~~------__J

OE CONTROL FUSE ALWAYS ENABLED

CODE A

E,,FUSE ALWAYS ENABLED

CODE

COMPLEMENT ARRAY DETAIL

P53 P52 P51 · · · · P1

Po Fe LMn · · · PMn RMn

· · ·

· · ·

co

co

___ _ ~'~~~~v~~~__.) \.:.

~ __..)
...

TOOR ARRAY

TO OMCa AND BIDIRECTIONAL 1/0

Notes on page 323.

Complement Array Detail The complement array is a special sequencer
feature that is often used for detecting illegal states. It is also ideal for generating IF-THEN-ELSE logic statements with a minimum number of product terms.
The concept is deceptively simple. If you subscribe to the theory that the expressions (/A· /B · /C) and (A+B+C) are equivalent, you will begin to see the value of this single term NOR array.
The complement array is a single OR gate with inputs from the AND array. The output of the complement array is inverted and fedback to the AND array (NOR function). The output of the array will be LOW if any one or more of the AND terms connected to it are active (HIGH). If, however, all the connected terms are inactive (LOW), which is a classic unknown state, the output of the complement array will be HIGH.
Consider the product terms A, B and D that represent defined states. They are also connected to the input of the complement array. When the condition (not A and not B and not D) exists, the Complement Array will detect this and propagate an Active-High signal to the AND array. This signal can be connected to product term E, which could be used in tum to preset the state machine to known state. Without the complement array, one would have to generate product terms for all unknown or illegal states. With very complex state machines, such an approach can be prohibitive, both in terms of time and wasted resources.

October 22, 1993

321

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLO (42 x 105 x 12)

Product specification
PLC42VA12

LOGIC PROGRAMMING
The PLC42VA 12 is fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips Semiconductors SNAP design software package. ABEL'" and CUPLTM design software packages also support the PLC42VA12 architecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.

PLC42VA12 logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. Symbols for OMC

configuration have been previously defined in the Architectural Options section.
PROGRAMMING AND SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for
additional information.

LOGIC IMPLEMENTATION

""4 ... ""4 4··· "AND" ARRAY- (I), (B), (Qp)

~ l,B,Q
1,e,a L~O

---
1,8,Q

LB,Q l,B,Q
1,ii,a

___ l,B,Q

(T, Fe, L, P, R, D)n

[

STATE

] CODE]

l j J INACTIVE1

0

(T, Fe. L, P, R, D)n

I

STATE
l,~Q

I I CODE H

(T, Fe. L, P, R, D)n

I STATE 1,e,a

I I CODE l

(T, Fe, L, P, R, D)n

[

STATE

] CODE]

l 1 - 1 DON'TCARE

"COMPLEMENT" ARRAY - (C)
c:t: c:t:

(Tn,Fc)

l 1 ACTION I J [ INACTIVE1, 3

CODE ] 0

(T,,, Fe)

1 l ACTION

CODE

t 1 1 GENERATE

A

c:t:

(T.,,Fc)

[

ACTION

] CODE ]

I . l [ PROPAGATE

c:t:

(Tn. Fcl

I J [

ACTION

r 1 - l TRANSPARENT

CODE

"OR" ARRAY - (J-K Type)

Tn

Tn

Tn

Q

Q

Q

Q

SET

H

"OR" ARRAY
Tn
~IP,......R_, ,(lORB) ~IP,.__R,, ,(lOR B)

T0 STATUS ACTIVE1

I J CODE l AJ

Notes on page 323.

ABEL is a trademark of Data 110 Corp. CUPL is a trademark of Logical Devices, Inc.

r 1 l T0 STATUS

CODE

1 · l [ INACTIVE

October 22, 1993

322

HOLD

Tn

Q

Q

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLO
(42 x 105 x 12)

Product specification
PLC42VA12

LOGIC IMPLEMENTATION (Continued)

OUTPUT MACRO CELL CONFIGURATIONS

OUTPUT MACRO CELL CONFIGURATION

I 1 REGISTER SELECT

PROGRAMMING CODES

OMC CONFIGURATION

POLARITY

FUSE

FUSE

FUSE

l

Combinatorial 1/0 with Burled 0-type register

External clock source P-term clock source

A A

I

· ·

1 l Hor L Hor L

Combinatorial 110 with Buried J-K type register

External clock source P-term clock source

· ·

l

· ·

l

Hor L Hor L

l

Registered Output (0-type) with feedback

External clock source P-term clock source

A A

I

A A

I l N/A NIA

Registered Output (J-K type) with feedback

External clock source P-term clock source

.· I

A A

l l NIA NIA

Registered Input (Clocked Preload) with feedback

External clock source

A

P-term clock source

A

l

A or·5 A or e5

I

Optional5 Optional5

I

CLOCK FUSE
A
·
A
·
A
·
A
·
A
·

OUTPUT ENABLE CONTROL8 CONFIGURATION

OUTPUT CONTROL FUSES

OE CONTROL FUSE

En FUSES

CONTROL SIGNAL

OMC controlled by /OE pin

A

Output Enabled

Output Disabled

OMC controlled by P-term

·

Output Enabled

Output Disabled

A A orO

Low High
High Low

Output always Enabled

A

0

Not Applicable

NOTES: 1. This is the initial (unprogrammed) state of the device.
2. Any gate will be unconditionally inhibited if both the TRUE and COMPLEMENT fuses are left intact. 3. To prevent oscillations, this state is not allowed for Complement Array fuse pairs that are coupled to active product terms. 4. The OMC Configuration fuse must be programmed as Combinatorial 1/0 in order to make use of the Polarity Option. 5. Regardless of the programmed state of the OMC Configuration fuse, an OMC can be used as a Registered Input. Note that the Load Control
P-term must be asserted Active-High. 6. Output must be disabled. 7. Program code definitions:
A = Active (unprogrammed fuse)
0, · = Inactive (programmed fuse) = Don't Care (both TRUE and COMPLEMENT fuses unprogrammed)
H = Active-High connection
L = Active-Low connection
8. OE control for BO and B1 (Pins 10 and 11) is from the AND array only.

October 22, 1993

323

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD (42 x 105 x 12)

Product specification
PLC42VA12

TIMING DIAGRAMS
~ B, M (INPUTS)

P-TERMCK (l,B,M)

M (OUTPUTS)

I, B, M, OE TERM OR

OEPIN

1.sv

--------..J (OUTPUT ENABLE)

Flip-Flop Outputs with P·term Clock

1,B,M (INPUTS)
EXTERNAL CK
M (OUTPUTS)

Fllp·Flop Outputs with External Clock

(INPut:: -..'I)~l1(_.-s_-v_-_-_-_--_-_-_-_-_-_-_-_-_-_-_-_-_--_-_-_-_-_-_-_-_-_-_-_-_-_--_-_-_-_-_-_-_-_-_+_3_ Vov
(COMBl~tw~~ f.~;-f:---~~::

I, B, M, OE TERM

+3V

(OUTPUTOREN'OAEBLP E) I N - - - - - -· _+UV

_ :_.SV

OV

Gated Outputs

TIMING DEFINITIONS

SYMBOL PARAMETER

fcK1 fc1<2
lcKH1

Clock Frequency; External Clock
Clock Frequency; P-term Clock
Width of Input Clock Pulse; External Clock

Width of Input Clock Pulse; lcKH2 P-term Clock

Interval between Clock pulses; lcKL1 External Clock

Interval between Clock Pulses; lcKL2 P-term Clock

lcK01

Delay between the Positive Transition of External Clock and when M Outputs become valid.

lcK02

Delay between the Positive Transition of P-term Clock and when M Outputs become valid.

Delay between beginning of Valid

tAP1

Input and when the M outputs become Valid when using

External Clock.

Delay between beginning of Valid

tAP2

Input and when the M outputs become Valid when using P-term

Clock.

Delay between beginning of Valid Input and when the M outputs tAP3 become Valid when using Preload Inputs (from M pins) and External Clock.

Delay between beginning of Valid Input and when the M outputs tRP4 become valid when using Preload inputs (from M pins) and P-term Clock.

Delay between beginning of Valid Input and when the M outputs tRP5 become Valid when using Com-
plement Array and External clock.

Delay between beginning of Valid

tRP6

Input and when the M outputs become Valid when using Com-

plement Array and P-term Clock.

Minimum guaranteed Operating fMAX1 Frequency; Dedicated Clock

fMAX2

Minimum guaranteed Operating Frequency; P-term Clock

IMAX3

Minimum guaranteed Operating Frequency using Preload; Dedicated Clock (M pin to M pin)

fMAX4

Minimum guaranteed Operating Frequency using Preload; P-term Clock (M pin to M pin)

fMAX5

Minimum guaranteed Operating Frequency using Complement Array; Dedicated Clock

fMAX6

Minimum Operating Frequency using Complement Array; P-term Clock

Required delay between positive

t1H1

transition of External Clock and

end of valid input data.

October 22, 1993

324

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD (42 x 105 x 12)

TIMING DIAGRAMS (Continued)
~ 8-~1,..................................................,.1~----+3v
(LOADSELECT)_.., 1,...,...,...,...,...,...,...,...,...,...,...,...,J'I'--.-. DY

I, B, OE TERM ml OE PIN (OUTPUT ENABLE)

---+3v

' '--
M.............................. ; ,....................1--+-.-.-.+3V
~NPun.....,....................... 1~...............,_,l'--+------ov

P-TERMOR

· +3V

EXTERNAL CK
tcK ~~~~~~~~-'I

~113,4
Q~~~~~~=

Flip-Flop Input Mode (Preload)

l,B,M .......,...,...,...,...,...,...,...,_ _.......,...,...,...,...,...,_ +3V
ONPUTS) ...........................,...,...,__,,,,...,.......,................~ov

P-TERMOR EXTERNAL CK

PRESET/RESET ~. B, MINPUTSJ ...........,...,....- 1
Q

M (OUTPUTS)
·Preset and Reset functions override Clock. However, M outputs may glitch with tho first positive Clock Edge Htis cannot be guaranteed by the user.
Asynchronous Preset/Reset

+SV
Vee ov

M ~,~~~~~-b-_,...,...,...,...,..,.. (OUTPUTS)

VOL

l,B,M

+3V

(INPUTS) _ _,_,__., 1,...,...,...,--+_,...,.J'J'--.-.-.-.-.........- ov

P-TERMOR EXTERNAL CK - .......,...,.,......,...,...,_,

+3V 1.SV
ov

Power-On Reset

Product specification
PLC42VA12

TIMING DEFINITIONS (Continued)

SYMBOL PARAMETER

Required delay between positive t1H2 transition of P-tenn Clock and
end of valid input dala.

Required delay between positive transition of External Clock and t1H3 end of valid input dala when using Preload Inputs (from M pins).

Required delay between positive
transition of P-1enn Clock and l1H4 end of valid input dala when us-
ing Preload Inputs (from M pins).

Required delay between begin1151 ning of valid input and positive
transition of External Clock.

Required delay between begint1s2 ning of valid input and positive
transition of P-1enn Clock input.

Required delay between

t153

beginning of valid Preload input (from M pins) and positive

transition of External Clock.

Required delay between beginning of valid Preload input 1154 (from M pins) and positive transition of P-1erm Clock input.
Required delay between beginning of valid input through 1155 Complement Array and positive transition of External Clock.
Required delay between beginning of valid input through t1se Complement Array and positive transition of P-terrn Clock input.

Delay between beginning of Output Enable signal (Low) from loE1 /OE pin and when Outputs become valid.

Delay between beginning of Output Enable signal (High or loE2 Low) from OE P-tenn and when Outputs become valid.

Delay between beginning of Output Enable signal (HIGH) from loo1 /OE pin and when Outputs become disabled.

Delay between beginning of

to02

Output Enable signal (High or Low) from OE P-tenn and when

Outputs become disabled.

Delay between beginning of valid lpo input and when the Outputs be-
come valid (Combinatorial Path).

lpRH Width of Preset/Resat Pulse.

Delay between beginning of valid Preset/Resat Input and when the lpRO registered Outputs become Preset ("1 ") or Resat ("O").

Delay between Vee (after

lppR

power-up) and when flip-flops become Reset to "O". Note: Signal

at Output (M pin) will be inverted.

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLO (42x105x12)

Product specification
PLC42VA12

LOGIC FUNCTION

PLC42VA12 UNPROGRAMMED

ERASURE CHARACTERISTICS

STATE

(For Quanz Window Packages

1':'1':'17JJ1 ~ -fi·~

A factory shipped unprogramrried device is configured such that all cells are in a

Only) The erasure characteristics of the

STATE REGISTER
I I I o l,o o t1 Sn+

JI:· IJ · C · ··. NEXTSTATE

conductive state. The following are: ACTIVE:

PLC42VA 12 devices are such that erasure begins to occur upon exposure to light with

I"

wavelength shorter than approximately 4000

Angstroms (A). It should be noted that

SET~:Jo=<ll2 ·~·!Jo) ·11:· IJ· C ··.

- OR array logic terms - Output Macro Cells M1 - MB;

sunlight and certain types of fluorescent lamps have wavelengths in the 3000 - 4000A

Ko=D RESET01:J1 =0
K, =(Cl:l ·lJz ·~·!Jo) ·11:· IJ· c ...

· D-type registered outputs (D = 0) - External clock path

range. Data shows that constant exposure to room level fluorescent lighting could erase a typical PLC42VA 12 in approximately three

HOLD02:J2=D

- Inputs: BO, B1, MO, M9

years, while it would take approximately one

K2=0
RESETC1:1:J3= (Cl:!· 02 · 01 · lJo) ·11:· IJ· C ...
Ka=<C1:1·lJ2·a1 ·lJol·ll:·JJ·c ...
NOTE: Similar logic functions are applicable for D mode flip-flops.

INACTIVE: - AND array logic and control terms (except
flip-flop mode control term, Fe) - Bidirectional 1/0 (BO, B1 );
· Inputs are active. Outputs are 3-Stated via the OE P-terms, DO and D1.

week to cause erasure when exposed to direct sunlight. If the PLC42VA12 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the window to prevent unintentional erasure.
The recommended erasure procedure for the

· D-type registers (D = 0).

PLC42VA 12 is exposure to shortwave

- Output Macro Cells MO and M9;

ultraviolet light which has a wavelength of

FLIP-FLOP TRUTH TABLE
Ln
x x x x xxL L x x H L xxH L x x L H xxL H

· Bidirectional 1/0, 3-Stated via the OE P-terms, DMO and DM9. The inputs are active.
- P-term clocks
- Complement Array
- J-K Flip-Flop mode

2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15Wsec/cm2. The erasure time with this dosage is approximately 30 to 35 minutes using an ultraviolet lamp with a 12,000µW/cm2 power rating. The device should be placed within one inch of the lamp

L Lt L Lt L Lt L Lt
H Ht H Ht
+10V x t x t

L L LLQ u
L L LHL H
L L HLH L
L L HHu Q
L L L H L H' L L H L H L'
x x L H L H" x x H L H L..

PROGRAMMING AND
SOFTWARE SUPPORT
Reier to Section 9 (Development Software)
and Section 1o (Third-party Programmer/
Software Support) in this data handbook for
additional information.

tubes during erasure. The maximum integrated dose a CMOS EPLD can be exposed to without damage is 7258Wseclcm2 (1week@12000µW/cm2). Exposure of these CMOS EPLDs to high intensity UV light for longer periods may cause permanent damage.
The maximum number of guaranteed erase/write cycles is 50. Data retentions exceeds 20 years.

NOTES:
1. Positive Logic: J-K =To+ Tt + T2 + ... + Ta1 Tn="C°-(10·11 ·12...)·(00·01 ...)· tBO · B1...)
2. T denotes transition for Low to High level.
3. X = Don't care

4. · = Forced at Mn pin for loading the J-K flip-flop in the Input mode. The load
control term, Ln must be enabled (HIGH) and the p-terms that are connected to the associated flip-flop must be forced LOW (disabled) during Preload.

5. At P = R = H, 0 = H. The final state of 0 depends on which is released first.
6. ·· = Forced at Fn pin to load J/K flip-flop (Diagnostic mode).

October 22, 1993

326

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLO (42x105x12)

Product specification
PLC42VA12

PROGRAM TABLE

OUTPUT ENABLE CONTROL

J(FIXED OR CONTROLLEO_n EB

EA

CONTRg~l:~~~OM PIN

:NEOCONTROL

I

8(1

M I

c D1 1 e 5 4 3 2 1 o 1 o9 , 1 e 5 · 3 2 1 o 9 · 1 e 5 4 a 2 1 o

ON

M(O)

B{O

9· 7 ' 5 · 321 0 9 · 7 6 5 4 321 0 1 0

" "
" " "'"" " " " " " " " " " """'
00
" "" ' "'""'
"'"''
''""''
"''"'''"M
(),-.tnha.r ?? 100':1.

'""''""
CKn = Asynchronous Clock Control Fe = Dynamic Flip-Flop Mode Control DMn = OMC Direction Control Dn = 110 Direction Control LMnand LA.B = OMC Load PMn and PA,B-' Flip-Flop Preset RMn = Flip-Flop Reset
??7

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLO (42 x 105 x 12)

Product specification
PLC42VA12

SNAP RESOURCE SUMMARY DESIGNATIONS

'j63 .. · Po Fe

LMn PMn RMn CKn DMn

OM,,

DBn

11-18

............ .

~;1·~.- - < f - - - + - - - - - + - - + - + - - + - - - + - + - - - + - - + - - - + - - - + - - - - - 1 -

3:: xa

19/UE IOICK

---j'----+--'------1---1--l---l----l--l---+--+--+-----l---!-~-"'J:r---, ~h
.------r~~~-1-----1--1-----+----1---1---1----1---1---1---1--+---+-----+ ~-o--1-~-1---+-~~~-1---+--+~1--~-1----+---+~+---+-~-1--~-+--

amr
~~
-~ -+-----t---3--1 xa
m:iw

M;:-"M8

MO,M9 '-'

October 22, 1993

328

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer (17 x 68 x 8)

Product specification
PLC415-16

DESCRIPTION
The PLC415-16 PLO is a CMOS Programmable Logic Sequencer of the Mealy type. The PLC415-16 is a pin-for-pin compatible, functional superset of the PLS105 and PLUS405 Bipolar Programmable Logic Sequencer devices.
The PLC415 is ideally suited for high density, power sensitive controller functions. The Power Down feature provides true CMOS standby power levels of less than 1OOµA The EPROM-based process technology supports operating frequencies ol 16 to 20MHz. The PLC415-16 has been designed to accept both CMOS and TTL input levels to facilitate logic integration in almost any system environment.
The PLC415 architecture has been tailored for state machine functions. Both arrays are programmable, thus providing lull interconnectability. Any one or all of the 64 AND transition terms can be connected to any (or all) of the 8 buried state and 8 output registers.
Two clock sources enable the design of 2 state machines on one chip. Separate INIT functions and Output Enable functions for each are controllable either from the array or from an external pin. The J-K flip-flops provide the added flexibility of the toggle function which is indeterminate on S-R flip-flops. The programmable Initialization feature supports asynchronous initialization of the state machine to any user defined pattern.
The unique Complement Array feature supports complex ELSE transition statements with a single product term. The PLC415-16 has 2 Complement Arrays which allows the user to design two independent complement functions. This is particularly useful if two state machines have been implemented on one chip.

FEATURES
· Pin-for-Pin compatible, functional superset of PLS105/A and PLUS405 Logic Sequencers
· Zero standby power of less than 1OOµA (worst case) - Power dissipation at IMAX = 80mA (worst case)
· CMOS and TTL compatible · Programmable asynchronous Initialization
and OE functions - Controllable from AND Array or external
source · 17 input variables · 8 output functions · 68 Product Terms
- 64 transition terms - 4 control terms · 8-bit State Register
· 8-bit Output Register · 2 Transition Complement Arrays · Multiple clocks · Diagnostic test modes features for access
to state and output registers · Power-on preset of all registers to "1" · J-K flip-flops
- Automatic Hold slates · Security Fuse · 3-State outputs
APPLICATIONS
· Interface protocols · Sequence detectors · Peripheral controllers · Timing generators ·Arbitration functions · Sequential circuits · Security locking systems ·Counters · Shift Registers

PIN CONFIGURATIONS N, FA Packages

F7
F5 F4 GND

110 111 112 113
114 115 INIT/OE
PDn1& FO Fl F2 F3

NOTE: N · Plastic DIP (600/Til·wide) FA "' Ceramic DIP with Quartz window (600mil-wide)

A Package
15/CLK 16 17 CLK Vee 18 19

114

F7

115

F&

INITIOE

PDnt&

F4 GNDF3 F2

FO

NOTE: A= Plastic Leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION
28-Pin Ceramic DIP with window; Reprogrammable (600mil-wide) 28-Pin Plastic DIP; One-Time Programmable (600mil-wide) 28-Pin Plastic Leaded Chip Carrier; One-Time Programmable (450mil-wide)

OPERATING FREQUENCY
IMAX= 16MHz IMAX= 16MHz IMAX= 16MHz

ORDER CODE
PLC415-16FA PLC415-16N PLC415-16A

DRAWING NUMBER
1478A 0413B 0401F

329

853-1382 11164

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer
(17 x 68 x 8)

Product specification
PLC415-16

PIN DESCRIPTION

PINNO. SYMBOL

1

CLK1

2, 3, 5--9. 26-27 20-22
4

10--14, 17, 16 18-19
113-115
15/CLK2

23

112

24

111

25

110

10-13 15-18

FO-F7

19

INIT/OE

116/PD

NAME AND FUNCTION
Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this line is necessary to update the contents of both registers. Pin 1 only clocks PO~ and FO~ if Pin 4 is also being used as a clock.
Logic Inputs: The 12 external inputs to the AND array used to program jump conditions between machine states, as determined by a given logic sequence. True and complement signals are generated via use of "H" and "L".
Logic lnpul/Clock: A user programmable function:
·Logic Input: A 13th external logic input to the AND array, as above.
·Clock: A 2nd clock for the State Registers P4-7 and Output Registers F4-7, as above. Note that input buffer 15 must be deleted from the AND array (i.e., all fuse locations "Don't Care") when using Pin 4 as a Clock.
Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when exercising standard ITL or CMOS levels. When 112 is held at + 11 V, device outputs FO--F7 reflect the contents of State Register bits PO-P7. The contents of each Output Register remains unaltered.
Logic/Diagnostic Input: A 15th external logic input to the AND array, as above, when exercising standard TTL or CMOS levels. When 111 is held at +11 V, device outputs FO-F7 become direct inputs for State Register bits PO-P7; a Low-to-High transition on the appropriate clock line loads the values on pins FO-F7 into the State Register bits PO--P7. The contents of each Output Register remains unaltered.
Logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when exercising standard TTL or CMOS levels. When 11 Ois held at + 11 V, device outputs FO--F7 become direct inputs for Output Register bits 00--07; a Low-to-High transition on the appropriate clock line loads the values on pins FO-F7 into the Output Register bits 00--07. The contents of each State Register remains unaltered.
Logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight device outputs which normally reflect the contents of Output Register Bits 00--07, when enabled. When 112 is held at+ 11V, FO-F7 = (PO--P7). When 111 is held at+ 11V, FO-F7 become inputs to State Register bits PO--P7. When 110 is held at+ 11V, FO--F7 become inputs to Output Register bits Q0--07.
External Initialization, External /OE, PD or 116: A user programmable function: Only one of the four options below may be selected. Note that both Initialization and /OE options are alternately available via the AND array. (P-terms INA, INB, OEA, and OEB.)
· External Initialization: Provides an asynchronous Preset to logic "1" or Reset to logic
"O" of any or all State and Output Registers, determined individually on a register-by-register basis. !NIT overrides the clock, and when held High, clocking is inhibited. Normal clocking resumes with the first full clock pulse following a High-to-Low clo.ck transition, after the INIT pulse goes Low. See timing diagrams for tNvcK and tvcK· Note that if the External Initialization option is selected, 116 is disabled automatically via the design software and the Power Down and External OE options are not available. Internal OE is available via P-Terms OEA and/or OEB. This option can be selected for one or both banks of registers.
· External Output Enable: Provides an Output Enable/Disable function for Output Registers. Note that if the External OE option is selected, 116 is disabled automatically via the design software and the Power Down and External !NIT options are not available. Internal !NIT is available via P-terms INA and/or INB. This option can be selected for one or both banks of registers.
·Power Down: When invoked, provides a Power Down (zero power) mode. The contents of all Registers is retained, despite the toggling of the Inputs or the clocks. To obtain the lowest possible power level, all Inputs should be static and at CMOS input levels. Note that if the PD options is selected, 116 is disabled automatically via the design software and the External INIT and External OE options are not available. Internal !NIT is available via P-terms INA and/or INB and Internal OE is available via P-terms OEA and/or OEB.
· Logic Input: The 17th external logic input to the AND array as above. Note that when the 116 option is selected, the Power Down, External /OE and External INIT are not available. Internal OE and Internal INIT are available from P-Terms OEAIOEB and INA/INB, respectively.

POLARITY Active-High (H) Active-High/Low
(H/L) Active-High/Low
(H/L) Active-High (H) Active-High/Low
(H/L) Active-High/Low
(H/L)
Active-High/Low (H/l)
Active-High (H)
Active-High (H)
Active-Low (L)
Active-High (H)
Active-High/low (H/l)

October 22, 1993

330

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer (17 x 68 x 8)

Product specification
PLC415-16

TRUTH TABLE 1, 2, 3, 4, 5

OPTION

Vee

INIT

OE

110

111

112

CK

J

K

Op

QF

F

H

x

x

x

x

x

x

H/L

H/L

OF

x

+11V

x

x

i

x

x

Op

L

L

x

+11V

x

x

i

x

x

Op

H

H

x

x

+11V

x

i

x

x

L

OF

L

x

x

+11V

x

i

x

x

H

OF

H

x

x

x

+11V

x

x

x

Op

OF

Op

L

x

x

x

x

x

x

Op

OF

OF

+5V

H

x

x

x

x

x

x

Op

OF

Hi-Z

x

+11V

x

x

i

x

x

Op

L

L

x

+11V

x

x

i

x

x

Op

H

H

x

x

+11V

x

i

x

x

L

OF

L

x

x

+11V

x

i

x

x

H

OF

H

L

x

x

+11V

x

x

x

Op

OF

Op

L

x

x

x

x

x

x

Op

OF

OF

L

x

x

x

i

L

x

x

x

i

L

x

x

x

i

L

x

x

x

i

L

L

Op

OF

OF

L

H

L

L

L

H

L

H

H

H

H

H

a;;

~

~

i

L

L

x

x

x

x

x

x

H

H

NOTES:
1. Positive Logic:
S/R (or J/K) = T0 + T1 + T2 + ... T63
Tn =(Co, C1)(IO, 11, 12, ...) (PO, P1 ... P7)
i 2. denotes transition from Low-to-High level.
3. X = Don't Care (.s5.5V)
4. H/L implies that either a High or a Low can occur, depending upon user-programmed Initialization selection (each State and Output Register
individually programmable).
5. When using the Fn pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-Stated and the indicated levels on the output pins are forced by the user.

VIRGIN STATE
A factory-shipped virgin device contains all fusible links intact, such that: 1. INIT/CJE/PD/116 is set to INIT. In order to
use the INIT function, the user must select either the PRESET or the RESET option for each flip-flop. Note that regardless of the user-programmed initialization, or even if the INIT function is not used, all registers are preset to "1" by the power-up procedure.
2. All transition terms are inactive (0).
3. All J/K flip-flop inputs are disabled (0).
4. The Complement Arrays are inactive.
5. Clock 1 is connected to all State and Output Registers.

LOGIC FUNCTION

I~ ~·pI ~R 3 2 ,: ,

PRESENT STATE

I I I r. I STATE REGISTER

JI" · lJ · C · ···

0 0 0

Sn+1 NEXTSTATE

SET<lo:Jo:(02. o, ·"Oo) ·JI" ·IJ· c ...
Ko=O RESET01:J1 =0
K, =!Oa · 02 · 01 ·"Oo) · ll"·B· C...
HOLO~:J2:0
K2 :0
RESETQa:J3 = (03 · 02 · 01 · "Ool ·JI"· B · C.. . Ka= <Oa · 02 · o, ·"Ool ·JI"· B · c .. .

October 22, 1993

331

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer (17 x 68 x 8)

Product specification
PLC415-16

FUNCTIONAL DIAGRAM
OEB OEA INA INB I 15
>
~
.--.:i~

...
<

15/CK2

__5:

<::

<]>--

~~ -
-

~ r--

7-

-D-J

Q P4-7

-D-K

<l-I-<

Tt

..----

-D-J

Q~

- ~CK1/CK2

4
_L
4

~ 4
-
4

......
h
INTERNAL INIT

__)'.,,
F~
INTERNAL
INIT ......
4
......
4
~

-D- K

<I--

Tt

..----

-D-J

F4-7 <.r-

~ .. F L 4

..----

-D-J

~

CK1

F

:r-r -D-lKP RO i,.

4

~N1i ~~-=- .INT. OE 1 ~

POWER DOWN

p

~

~

-~EXTERNAL INIT/OE

PD~ NIT/OE/116

J

October 22, 1993

332

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer (17 x 68 x 8)
LOGIC DIAGRAM

Product specification
PLC415-16

NOTE: Programmable connection.
October 22, 1993

333

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer (17x68x8)
DETAILS FOR PLC415-16 LOGIC DIAGRAM

Product specification
PLC415-16

FROM INIT PIN 19 OR PTERM INA(~) OR INB (P4-7)

FROMCLK1 ORCLK2

Detail A State Registers PO - P7

F4-F70E

FROM OE PIN 19
OR PTERM OEA (FG-3)
OR OEB (F4-7)

FROM INIT PIN 19 OR PTERM INA (FG-3) OR INB (F4-7)

FROMCLK1 ORCLK2

Detail B Output Registers FD - F7

FO-F30E

TOINIT. LINES

TOANo-::::::::::::::::~~~~~~~~~~~_J ARRAY -
Detail c
Pin 19 Options: OE, Initialization, Power Down and Input 16

FROM AND ARRAY

P4-7AND F4-71NIT

~AND
FG-31NIT

INA

October 22, 1993

Detail D Internal and External Initialization
334

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer (17x68x8)
DETAILS FOR PLC415-16 LOGIC DIAGRAM (Continued)
OEB OEA INB INA P63 P62 o o o P2 Pl PO
co

Product specification
PLC415-16

Cl
co

TOOR ARRAY
Complement Array Detail

The Complement Array is a special sequencer feature that is often used for detecting illegal states. It is also ideal for generating IF-THEN-ELSE logic statements with a minimum number of product terms.
The concept is deceptively simple. If you subscribe to the theory that the expressions (/A · /B ·IC) and (~are equivalent, you will begin to see the value of this single term NOR array.
The Complement Array is a single OR gate with inputs from the AND array. The output of the Complement Array is inverted and fed back to the AND array (NOR). The output of the array will be Low if any one or more of the

AND terms connected to it are active (High). If, however, all the connected terms are inactive (Low), which is a classic unknown state, the output of the Complement Array will be High.
Consider the Product Terms A, B and D that represent defined states. They are also connected to the input of the Complement Array. When the condition (not A and not B and not D) exists, the Complement Array will detect this and propagate an Active-High signal to the AND array. This signal can be connected to Product Term E, which could be used in turn to reset the state machine to a known state. Without the Complement Array, one would have to generate product terms for

all unknown or illegal states. With very complex state machines, such an approach can be prohibitive, both in terms of time and wasted resources.
Note that the PLC416-16 has 2 Complement Arrays which allow the user to design 2 independent Complement functions. This is panicularly useful if 2 independent state machines have been implemented on one device.
Note that use of the Complement Array adds an additional delay path through the device. Please refer to the AC Electrical Characteristics for details.

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

PARAMETER

RATINGS

UNIT

Vee

Supply voltage

+7

Voe

V1N

Input voltage

+5.5

Voe

Vour

Output voltage

+5.5

Voe

l1N

Input currents

-30 to +30

mA

lour lamb Tstg

Output currents Operating temperature range Storage temperature range

+100

mA

Oto +75

oc

-65 to +150

oc

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

October 22, 1993

335

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer
(17 x 68 x 8)

Product specification
PLC415-16

DC ELECTRICAL CHARACTERISTICS 0°C s; Tarrb s; +75°C, 4.75 s; Vee s; 5.25V

SYMBOL

PARAMETER

TEST CONDITION

LIMITS

MIN

TYP1

MAX

UNIT

Input voltage2

V1L

Low

V1H

High

Output voltage2

Vcc=MIN Vee= MAX

-0.3 2.0

0.8

v

Vee+ 0.3

v

VoL

Low

VoH

High

Input current

l1L

Low

l1H

High

Output current

Vcc=MIN loL = 16mA

loH=-3.2mA

2.4

V1N=GND V1N =Vee

0.5

v

v

-10

µA

10

µA

lo(OFF)

Hi-Z state

los Ices a

Short-drcuit 3· 6
Vee sup~ly current with PD asserted

Ice

Vee supply current Active 4, 5

(TTL or CMOS Inputs)

Capacitance

VouT =Vee VouT = GND

VouT =GND

Vee= MAX V1N = Oor Vee

l louT=OmA

all= 1MHz

l Vee= MAX

atf= MAX

10

µA

-10

µA

-130

mA

50

100

µA

55

mA

80

mA

C1

Input

Vee= 5V V1N =2.0V

12

pF

Ca

110

Va= 2.0V

15

pF

NOTES:
1. All typical values are at Vee= 5V. Tarrb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Duration of short-circuit should not exceed one second. Test one at a time. 4. Tested with TTL input levels: V1L = 0.45V, ViH = 2.4V. Measured with all inputs and outputs switching. 5. Refer to Figure 1, Ice vs Frequency (worst case). 6. Refer to Figure 2 for .1tp0 vs output capacitance loading. 7. The outputs are automatically 3-Stated when the device is in the Power Down mode. To achieve the lowest possible current, the inputs and
clocks should be at CMOS static levels.

50 l-+__,f--+--+--+--!-+---+--1
s;;;~ o-+--4-+-4--4--+-I--+-~
~ 30 l-+---1-+---+--+--+-f--+-4
10 l-+---1-+---+--+--+-f--+-4
1 2 4 6 8 10 12 14 16 18 f(MHz)
Figure 1. Ice vs Frequency (Worst Case)

-1£
0 20 40 60 80 100 120 140 160 180 200
OUTPUT CAPACITANCE LOADING (pF)
Figure 2. !itpo vs Output Capacitance Loading (Typical)

October 22, 1993

336

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer (17x68x8)

Product specification
PLC415-16

AC ELECTRICAL CHARACTERISTICS
R1 =2520, R2 =1780 0°C s Taroo s +75°C 4.75 s Vee s 5 25V

SYMBOL

PARAMETER

FROM

Pulse width

lcKH

Clock High

lcKL

Clock Low

trNITH

Initialization Input pulse

Set-uptime

CK+ CKINIT+

t1s1 t1s21 trsPD trsPu tvs1
tveK1

Input Input through Complement array Power Down Setup (from PD pin) Power Up Setup (from PD pin) Power on Preset Setup Clock resume (after INIT) when using INIT pin (pin 19)

(I)+/(I)+/PD+ PDVee+
INIT-

tveK2 1

Clock resume (after INIT) when using P-term INIT (from AND array)

(I)+/-

tNveK1

Clock lockout (before INIT) when using INIT pin (pin 19)

CK-

INveK21

Clock lockout (before INIT) when using P-term INIT (from AND array)

CK-

Propagation delays

lcKO lpoz
tpLJA1

Clock to Output
Power Down to outputs off
Power Up to outputs Active with dedicated Output Enable

CK+ PD+ PD-

tpuA21

Power Up to outputs Active with P-term Output Enable1

PD-

trHPU

Last valid clock to Power Down delay (Hold)

Last Valid Clock

trHPD

First valid clock cycle before Power Beginning of First

Up

Valid Clock Cycle

loE1 3 loE21 loo1 3 loo23 trNIT1
trNIT2

Output Enable: from /OE pin Output Enable; from P-term Output Disable; from /OE pin Output Disable; from P-term INIT to output when using INIT pin INIT to output when using P-term INIT

OE(I)+/OE+ (I)+/INIT+
(I)+/-

tppR1 tRP1

Power-on Preset <Fn = 1)
Registered operating period; (t1s1 + fcK01)

Vee+ (I)+/-

tRP2 1

Registered operating period with Complement Array (t1s2 + lcK01)

Notes on followrng page

(I)+/-

TO
CKCK+ INIT-
CK+ CK+ CK+ First Valid CK+ CKCK-
CK-
INIT-
INIT-
(F) +/Outputs Off Outputs Active
Outputs Active
PD+
PDOutput Enabled Output Enabled Output Disabled Output Disabled
(F) +/(F) +/(F) + (F) +/-
(F) +/-

TEST CONDITION
30pF 30pF 30pF
30pF 30pF 30pF 30pF 30pF 30pF
30pF
30pF
30pF
30pF 5pF 30pF
30pF
30pF
30pF 30pF 30pF 5pF 5pF 30pF 30pF 30pF 30pF
30pF

LIMITS MIN TYP MAX

25

10

25

10

20

38

25

60

40

38

15

38

30

0

10 -5

20

8

10 -3

0

-5

15

22

25

30

20

35

37

55

25

15

0

-25

15

30

25

40

20

30

30

40

22

35

35

45

15

40

60

55

75

UNIT
ns ns ns
ns ns ns ns ns ns
ns
ns
ns
ns ns ns
ns
ns
ns ns ns ns ns ns ns ns ns
ns

October 22, 1993

337

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer (17 x 68 x 8)

Product specification
PLC415-16

AC ELECTRICAL CHARACTERISTICS (Continued)
R1 =252'1, R2 =178'1, 0°c sTambs +75°C, 4.75sVccs5.25V

TEST

LIMITS

SYMBOL

PARAMETER

FROM

TO

CONDITION MIN TYP MAX UNIT

Hold time

t1H

Input Hold

1~

CK+

(F) +/-

30pF

-10

0

ns

Frequency of operation

fcLK1

Clock (toggle) frequency

C+

C+

30pF

20 .50

MHz

fMAX1

Registered operating frequency (t1s1 + lcK01)

(I)+/-

(F)+/-

30pF

16.7 25

MHz

fMAX2

Registered operating frequency with Complement Array (t1s2 + lcK01)1

(I)+/-

(F)+/-

30pF

13.3 18.2

MHz

NOTE: 1. Not 100% tested, but guaranteed by design/characterization. 2. All propagation delays and setup times are measured and specified under worst case conditions. 3. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output voltage of Vr = (VoH -0.5V) with S 1open, and Low-to-High impedance tests are made to the Vr = (VoL + 0.5V) level with S1closed.

TIMING DIAGRAMS
+3V I0-116
ov

CLK1/2

+3V
1.SV
ov

FO-F7
"OE "(from OEA/B or Pin 19)

Yott
VOL +3V
ov
toe Sequential Mode

I0-116

1.SV

CLK112

FO-F7

INIT (FROM INAIB OR PIN 19)

October 22, 1993

1.SV

1.5V

'<:KH

ICKL

+3V
'-----ov

1.sv

rtcKO +3V

1.SV

1.SV

~NITH

Asynchronous Initialization

338

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer (17x68x8)

Product specification
PLC415-16

The PLC416-16 has a unique power down feature that is ideal for power sensitive controller and state machine applications. During idle periods, the PLC415 can be powered down to a near zero power consumption level of less than 100 micro Amps. Externally controlled from Pin 19, the power down sequence first saves the data in

all the State and Output registers. In order to insure that the last valid states are saved, there are certain hold times associated with the first and last valid clock edges and the Power Down input pulse. The Outputs are then automatically 3-Stated and power consumption is reduced to a minimum.

Once in the power down mode, any or all of the inputs, including the clocks, may be toggled without the loss of data. To obtain the lowest possible power level, the inputs should be at static CMOS input levels during the power down period.

TIMING DIAGRAMS (Continued)

xxxxxxxxxxxxx -v ADDRESS

L.ASTVAUD

_ _ / \ ADDRESS · _

L.ASTVAUD CLOCK

CLOCK

PDPIN---------·l-HP__."[~

x )>------ LA~~A~~UD OUTPUT ___________ POWER DOWN

FIRSTVAUD CLOCK

tcKO

1PUA1,2 POWER UP

L.ASTVAUD STATE

Power Down Enable and Disable

Vee

~~~~~r-------------"'t'----- VoH

FO-F7

1.sv

[FnJ = 1

1.s

IFnl + 1

tcKO '----Vol

CLK1/2 ----~·~t-tcK

ov

tvs-----

I0-116

Power-On Preset

October 22. 1993

339

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer (17 x 68 x 8)

Product specification
PLC415-16

TIMING DIAGRAMS (Continued)

1 1 1 - 1 1 1 , - - , , - - - - - - - - - - - - - - - - - - - - - - - - - - +3V

113-116

1.SV

+tOV I
112

+3V CUC

- - - - - - - - - - - - - VoH

FO-F7

Diagnostic Mode-State Register Outputs

+10V 8.0V
+3V 111
ov
IRJH
FO _ F7 ,.,"T.'r7"T.r7"T.'r7"T.r7"7"~1.I-----""""-"' r."'7.,-,"'7',..,..,. +3V
~NPUTS) """'~"""~"""~"""~"""~I'-------;.,---' '"'"""""""~~ ov

+3V CUC

tis--+
~STQ ATE p~~~~~~----v (DIN) oH

REG.

tcKO

- - - - VOL

Diagnostic Mode-State Register Input Jam

+10V
a.av

+3V

110

ov

------'---1 FO- F7 r'7T.'7'T.'7''7'::1'7''7'::1'7'~

IRJH
n"r,..,"'7",..,"'71 +3V

~NPUTS) ...._........,....._...,....._...,...._.......,,,_, '-------,....--Jl"'~"""~"""r:;...i ov

+3V CLK1/2

October 22, 1993

Diagnostic Mode-Output Register Input Jam 340

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer (17x68x8)

Product specification
PLC415-16

TIMING DEFINITIONS

SYMBOL

PARAMETER

fcLK

Minimum guaranteed toggle

frequency of the clock (from

Clock HIGH to Clock HIGH).

fMAXl,2 Minimum guaranteed operating frequency.

lcKH

Width of input clock pulse.

le KL

Interval between clock

pulses.

tAP1

Minimum guaranteed

operating period -when not

using Complement Array.

tAP2

Minimum guaranteed

operating period - when

using Complement Array.

le KO

Delay between positive

transition of Clock and when

Outputs become valid (with

outputs enabled).

t1H

Required delay between

positive transition of Clock

and end of valid Input data.

t1HPD

Required delay between the positive transition of the beginning of the first valid clock cycle to the beginning of Power Down LOW to insure that the last valid states are intact and that the next positive transition of the clock is valid.

t1HPU

Required delay between the positive transition of the last valid clock and the beginning of Power Down HIGH to insure that last valid states are saved.

tlNITH

Width of initialization input pulse.

t1NIT1 tlNIT2

Delay between positive transition of Initialization and when Outputs become valid when using external INIT control (from pin 19).
Delay between positive transition of Initialization and when outputs become valid when using internal INIT control (from P-terms INA and INB).

t1SPD

Required delay between the beginning of Power Down HIGH (from pin 19) and the positive transition of the next clock to insure that the clock edge is not detected as a valid Clock and that the last valid states are saved.

SYMBOL

PARAMETER

t1spu

Required delay between the beginning of Power Down LOW and the positive transition of the first valid dock.

tis1

Required delay between

beginning of valid input and

positive transition of Clock.

tis2

Required delay between

beginning of valid input and

positive transition of Clock,

when using optional

Complement Array (two

passes necessary through

the AND Array).

tNVCK1

Required delay between the negative transition of the clock and the negative transition of the Asynchronous Initialization when using external IN IT control (from pin 19) to guarantee that the clock edge is not detected as a valid negative transition.

tNVCK2

Required delay between the negative transition of the clock and the negative transition of the Asynchronous l'litialization, when using the internal INIT control (from P-terms INA and INB), to guarantee that the clock edge is not detected as a valid negative transition.

to01

Delay between beginning of

Output Enable High and

when Outputs are in the

OFF-State, when using

external OE control (from

pin 19).

too2

Delay between beginning of

Output Enable High and

when outputs are in the

OFF-State when using

internal OE control (from

P-terms OEA and OEB).

loE1

Delay between beginning of

Output Enable Low and when

Outputs become valid when

using external OE control

from pin 19.

toE2

Delay between beginning of

Output Enable Low and when

outputs become valid when

using internal OE control

(from P-terms OEA and

OEB).

tpoz

Delay between beginning of

Power Down HIGH and when

outputs are in OFF-State and

the circuit is ·powered down".

SYMBOL

PARAMETER

lppR

Delay between Vee (after

power-on) and when Outputs

become preset at "1 ".

lpuA1.2 tRH

Delay between beginning of Power Down LOW and when outputs become Active (valid) and the circuit is "powered up". See AC Specifications.
Required delay between positive transition of Clock and end of valid Input data when jamming data into State or Output Registers in diagnostic mode.

tRJH

Required delay between

positive transition of Clock

and end of inputs 111or110

transition to State and Output

Register Input Jam

Diagnostic Modes,

respectively.

tRJS
ls RD
ts RE tveK1

Required delay between when inputs 111or110 transition to State and Output Register Input Jam Diagnostic Modes, respectively, and when the output pins become available as inputs.
Delay between input 112 transition to Logic mode and when the Outputs reflect the contents of the Output Register.
Delay between input 112 transition to Diagnostic Mode and when the Outputs reflect the contents of the State Register.
Required delay between negative transition of Asynchronous Initialization and negative transition of Clock preceding the first valid clock pulse when using external INIT control (pin 19).

tveK2

Required delay between the negative transition of the Asynchronous Initialization and the negative transition of the clock preceding the first valid clock pulse when using internal INIT control (from P-terms INA and INB).

tvs

Required delay between Vee

(after power-on) and negative

transition of Clock preceding

first reliable clock pulse.

October 22, 1993

341

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer
(17 x 68 x 8)

Product specification
PLC415-16

TEST LOAD CIRCUIT
c1 yc2 INPUTS

Vee L___.>

R1

1lE

IO

By

115 OUT

R2

CL

o----<.. CK

GND

= Bz,_.--~ OUTPUTS

=
NOTE:
C1 and C2 are to bypass Vee to GND.

LOGIC PROGRAMMING
The PLC416-16 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL'" and CUPLTM design software packages also support the PLC416-16 architecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and

CUPL also accept, as input, schematic capture format.
PLC416-16 logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only.

INITIALIZATION (PRESET/RESET)11 OPTION - (P/R)

VOLTAGE WAVEFORMS

- w _j L.~ .Jc

2.Sns

2.5ns

:-J\_ ·{L-

2.Sna

2.Sns

MEASUREMENTS: All circuit delays are measured at the + 1.SV level of Inputs and outputs, unless otherwise specified.
Input Pulses

To implement the desired logic functions, each logic variable (I, B, P, S, T, etc.) from the logic equations if assigned a symbol. TRUE, COMPLEMENT, PRESET, RESET, OUTPUT ENABLE, INACTIVE, etc., symbols are defined below.

ACTION

COOE

i i,pINDETERMINATE1·4,9

0

"AND" ARRAY - (I), (P)

l,P i,ji

Tn

l

STATE

I J CODE

J [ INACTIVE1· 2 _l_ 0

Notes are on page 344.

ii,pPRESET9

H

I, P i,p

Tn
STATE l,P

ii,p
I, P i,ji
Tn STATE
1. p

ABEL is a trademark of Data 110 Corp. CUPL is a trademark of Logical Devices, Inc.
October 22, 1993

342

ACTION

CODE

ii,pNO INIT FUNCTION4·9

l. P i,p

Tn
STATE DON'T CARE

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer
(17 x 68 x 8)

Product specification
PLC415-16

LOGIC PROGRAMMING (Continued)

PIN 19 FUNCTION: POWER DOWN, INllTALIZATION, ~.OR INPUT

~~~~~~~~~~~~~~~~~~-~~~~~~---,

Power Down Mode

P·Term Initialization Control

(PD FUSE) POWER DOWN
CONTROL FROM PIN 19
INIT DISABLED FROM PIN 19

(INIT/OE FUSE)
OE DISABLED FROM PIN 19

FROM AND ARRAY INTERNAL INIT

PRESET/RESET TO REGISTERS
INIT DISABLED FROM PIN19

POWER DOWN FUSE PIN 19 AS POWER DOWN
EXTERNAL INIT/OE FUSE EXTERNAL INIT/OE DISABLED

CODE
CODE L

I J INTERNALINIT FUSES

CODE

l j P-TERMINITCONTROL

H7,8

L l J POWER DOWN FUSE
l I J POWER DOWN ENABLED OR DISABLED

CODE H OR L

External Initialization Control

(PD FUSE) POWER DOWN
DISABLED FROMPIN19
INIT CONTROL FROM PIN 19

(INIT/OE FUSE)
OE DISABLED FROM PIN 19

PD FUSE POWER DOWN DISABLED
EXTERNAL INIT/OE FUSE PIN 19 AS EXTERNAL INIT
INTERNAL INIT FUSES P-TERM INIT ACTIVE OR
INACTIVE

CODE L1
CODE L1
CODE HOR L7· 8

P-Term OE Control
FROM AND ARRAY

INTERNAL OE

OUTPUT ENABLE CONTROL
OE DISABLED FROM PIN 19

INTERNAL OE FUSES P-TERM OE CONTROL
POWER DOWN FUSE POWER DOWN ENABLED OR
DISABLED

CODE
CODE HORL

External Output Enable Control

(PD FUSE) POWER DOWN
DISABLED FROMPIN19
INIT DISABLED FROM PIN19

(INIT/OE FUSE)
,---+-- :oc.f~~R~L

PD FUSE POWER DOWN DISABLED
EXTERNAL INIT/OE FUSE PIN 19 AS EXTERNAL OE
INTERNAL INIT FUSES P-TERM OE ACTIVE OR
INACTIVE
Notes are on page 344.

CODE
CODE H
CODE HOR L7· 8

October 22, 1993

343

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer (17 x 68 x 8)

Product specification
PLC415-16

LOGIC PROGRAMMING (Continued) "OR" ARRAY - J-K FUNCTION - (N), (F)

"'fg[j "'fg[j "'fg[j "'fg[j

R;l'

K

R;l'

K

R;l'

K

R;l'

K

I I I ACTION TOGGLE2

CODE 0

I I I ACTION SET

CODE H

"COMPLEMENT" ARRAY - (C)

~:

Tn

I I I ACTION INACTIVE1· 3

CODE 0

~:

Tn

I I I ACTION GENERATE

CODE A

CLOCK OPTION - (CLK1/CLK2)
CLK2

I ACTION RESET

I I CODE l

I I - I ACTION DON'T CARE

CODE

~:

Tn

I I · I ACTION PROPAGATE

CODE

~:

Tn

I I - I ACTION TRANSPARENT

CODE

CLK1

OPTION CLK1 ONLY1

CODE l

CLK1
I OPTION ClK1 and CLK:z5

CODE H

NOTES: 1. This is the initial unprogrammed state of all links.
2. Any gate Tn will be unconditionally inhibited if any one of its I or P link pairs is left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn· 4. These states are not allowed when using PRESET/RESET option. 5. Input buffer Is must be deleted from the AND array (i.e., all fuse locations "Don't Care") when using second clock option. 6. When using Power Down feature, INPUT 16 is automatically disabled via the design software. 7. If the internal (P-tenn) control fuse for INIT and/or OE is programmed as Active High, the associated External Control function will be
permanently disabled, regardless of the state of the External INIT/OE fuse. 8. One internal control fuse exists for each group of 8 registers. PO - 3 and FO - 3 are banked together in one group, as are P4 - 7 and F4 -
7. Control can be split between the INIT/OE pin (Pin 19) and P-tenns INA, INB, OEA and OEB. 9. The PLC416-16 also has a power-up preset feature. This feature insures that the device will power-up in a known state with all register
elements (State and Output Register) at a logic High (H). When programming the device it is important to realize this is the initial state of the device. You must provide a next state jump if you do not wish to use all Highs (H) as the present state. 10. L =cell unprogrammed.
H =cell programmed. 11. Inputs 10, 11and12 (pins 25, 24, & 23) can be used for supervoltage diagnostic mode tests. It is recommended that these inputs ll21 be
connected to product tenns INA, INB, OEA or OEB if you intend to make use of the diagnostic modes due to the fact Iha.I the patterns associated with the internal INIT and OE control product tenns may interfere with the diagnostic mode data loading and reading.

October 22, 1993

344

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer
(17 x 68 x 8)

Product specification
PLC415-16

PROGRAM TABLE

(lm,Pa) INACTIVE l,P i,P DON'T CARE

AND

(Cn)

0

INACTIVE

0

H L

GENERATE PROPAGATE

. A

-

- TRANSPARENT

~ COMP. ~ ARRAY

INTERNA INIT

INB

INA

OR{Ns,Fn)

TOGGLE

0

SET

H

RESET

L

NO CHANGE

-

i''[ INTERNAL Qi<:

OEB

OEA

.';':';':':':';':

EXTEil!i!L INIT/OE

L ~~j ENTERNAL INIT
[ EXTERNAL OE
l INTERNALINIT/OE H ENABLED
[ INTERNAL INITIOE L DISABLED
I I 171L:21:1 PD

NORI
t Cn

INPUT(lm)

AND

PRESENT STATE (Pa)

1"11CO 16115 114113 11~11 110 19 18 17 16 15 14Jl3 12 11 IO P7 P6 PS P~3 P2 Pl PO

OPTIONS

POWER DOWN ENABLED

H

POWER DOWN DISABLED

L

CLOCK 1 ONLY L]
CLOCK 1AND2 H]

INITIAUZA<noN

PRESET

H

RESET

l

NOINIT

-

INDETERMINATE 0

INITIALIZATION

OR

NEXT STATE (Na)

OUTPUT(Fn)

N7 N6 NS N4jN3 N2 N1 NO F7 F6 FS F4Ji'3 F2 Fl FD

4

I

5

6

I

J:

I

I

7

8

i:

11

12

13

I

I

I

14

[lli

16
ill

18

19

w

20

::;;;

21

z<(
f-
.w0..,
0a:
CL

w
~
0

22

z
0
iii

23 24 25 26

5aw:

27 28 ~

I

30

31

32

33

I

I

J:

J:

I

34

35

36

37

38

39

40

41

42

I

I

43

44

45

46

J:

J:

47

48

I

I

I

49

50

51

52

53

.. .. 54 55 56

~
z<( a:
:w:;;;
8en
::::> 0

acf-:t
en
0
zwf'=
<.?
iii

acf-:t
aw :
::;;;
8en

57
59 59 50 61 62 il_
INB OEB

::::> INA

0 DEA

I

I

I

J:

I

I

I

J:

I

I

I

I

J:

I I

I

I

:r

I

::::::

I

I

:r

:r

PINNO. 19 20 21 22 23 24 25 26 27 2 3 4 16 7 8 9

PIN LABELS

l

10 11 12 13_jis 16 17 18
l

NOTES: ~. In the unprogrammed state all cells are conducting. Thus, the program table for an unprogrammed device would contain "O"s tor alt product terms (inactive) and
initialization states (indeterminate). The default or unprogrammed state of all other options is "L".
2. Unused Cn, Im and Ps cells are normally programmed as Don't Care(-). 3. Unused product terms can be left blank (inactive) for future code modification.

October 22, 1993

345

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer {17x68x8)

Product specification
PLC415-16

ERASURE CHARACTERISTICS (For Quartz Window Packages
Only)
The erasure characteristics of the PLC415 Series devices are such that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps has wavelengths in the 3000 - 4000A range. Data shows that constant exposure to room level fluorescent lighting could erase a typical PLC415 in approximately three years, while it would take approximately one week

to cause erasure when exposed to direct sunlight. If the PLC415 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the window to prevent unintentional erasure.
The recommended erasure procedure for the PLC415 is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity x exposure time) for erasure should
be a minimum of 15Wsec/cm2. The erasure time with this dosage is approximately 30 to

35 minutes using an ultraviolet lamp with a 12,000µW/cm2 power rating. The device should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose a CMOS EPLD can be exposed to without damage is 7258Wsec/cm2 (1 week@12000µW/cm2). Exposure of these CMOS EPLDs to high intensity UV light for longer periods may cause permanent damage.
The maximum number of guaranteed erase/write cycles is 50. Data retention exceeds 20 years.

October 22, 1993

346

Philips Semiconductors Programmable Logic Devices
CMOS programmable logic sequencer {17x68x8)
SNAP RESOURCE SUMMARY DESIGNATIONS
OED OEA INA INB

Product specification
PLC415-16

INTERNAL INIT

October 22, 1993

347

Phillps Semiconductors Programmable Logic Devices
Programmable logic sequencers
(16 x 48 x 8)

Product specification
PLS105/A

D.ESCRIPTION

FEATURES

PIN CONFIGURATIONS

The PLS105and the PLS105A are bipolar Programmable Logic State machines of the Mealy type. They contain logic AND-OR gate arrays with user programmable connections which control the inputs of on-chip State and
°" Output Registers. These consist respectively
of 6 Op, and 8 edge-triggered, clocked SIR flip-flops, with an Asynchronous Preset

· PLS105 - IMAX= 13.9MHz - 20MHz clock rate
· PLS105A - IMAX = 20MHz - 25MHz clock rate

NPackage
Vee
I'
110

option. all flip-flops are unconditionally preset · Field-Programmable (Ni-Cr link)

111

to ·1 ·during power tum on.

· 16 input variables

112

The AND array combines 16 external inputs 10 - hs with six internal inputs P0 _ 5, which

· 8 output functions

113

are fed back from the State Registers to form · 48 transition terms

114

up to 48 transition terms (AND terms). All transition terms can include True, False, or

· 6-bit State Register

115 PRICE

Don't Care states of the controlling variables, · 8-bit Output Register

Al

and are merged in the OR array to issue next-state and next-output commands to their

· Transition complement array

F1

respective registers on the Low-to-High

· Positive edge-triggered clocked flip-flops

F2

transition of the Clock pulse. Both True and Complement transition terms can be generated by optional use of the internal input variable (C) from the Complement Array.

· Programmable Asynchronous Preset or Output Enable
· Power-on preset to all "1" of internal

F3 N · Plastic DIP (600mi~wide)

Also, if desired, the Preset input can be

registers

converted to Output Enable function, as an additional user-programmable option.
Order codes are listed below in the Ordering

· Power dissipation: 600mW (typ.) · TTL compatible

Information Table.

· Single +SV supply

A Package

· 3-State outputs

15 16 17 CU< Yee 18 19

APPLICATIONS

· Interface protocols

· Sequence detectors

· Peripheral controllers

· Timing generators

· Sequential circuits

· Elevator controllers

· Secu.rity locking systems

·Counters · Shift registers

A - Plastic Leaded Chip Carrler

ORDERING INFORMATION DESCRIPTION
28-Pin Plastic DIP (600mil-wide) 28-Pin Plastic Leaded Chip Carrier

ORDER CODE PLS105N,PLS105AN PLS105A, PLS105AA

DRAWING NUMBER 0413B 0401F

October 22, 1993

348

853--0310 11164

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (16x48x8)
FUNCTIONAL DIAGRAM

Product specification
PLS105/A

T41----------To

PIN DESCRIPTION

PINNO. 1

SYMBOL CLK

2-8 20-27
9

11-115 10

10-13 15-18
19

F0-7 PR/OE

NAME AND FUNCTION
Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this line is necessary to update the contents of both registers.
Logic Inputs: The 15 external inputs to the AND array used to program jump conditions between machine states, as determined by a given logic sequence.
Logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when exercised with standard TTL levels. When 10 is held at +1OV, device outputs FO - 5 reflect the contents of State Register bits PO - 5. The contents each Output Register remains unaltered.
Logic/Diagnostic Outputs: Eight device outputs which normally reflect the contents of Output Register bits 00- 7, when enabled. When 10 is held at+10V, FO -5 =(PO- 5), and F6, 7 =Logic "1".
Preset or Output Eni6re Input: A user programmable function:
·Preset: Provides an Asynchronous Preset to logic "1" of all State and Output Register bits. Preset overrides Clock, and when held High, clocking is inhibited and FO - 7 are High. Normal clocking resumes with the first lull clock pulse following a High-to-Low clock transition, alter Preset goes Low.
· output Eil861i: Provides an Output Enable function to all output buffers FO - 7 from the Output Register.

POLARITY Active-High Active-High/Low Active-High/Low
Active-High
Active-High (H)
Active-Low (L)

October 22, 1993

349

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(16 x 48 x 8)
LOGIC DIAGRAM

Product specification
PLS105/A
I'

NOTES: 1. All AND gate inputs with a blown link float to a logic "1".
2. All.9R gate inputs with a blown fuse float to logic ·o·.
3. th Programmable connection.

October 22, 1993

350

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (16 x 48 x 8)

Product specification
PLS105/A

TRUTH TABLE 1, 2, 3, 4, 5, 6

OPTION

Vee

PR

OE

H

.lo

CK
x

s x

L

+10V

x

x

L

H

x .

x x

x x

+SV

L

+10V

x

x

L

x

x

x

L

x

i

L

L

x

i

L

L

x

i

H

L

x

i

H

i

x

x

x

x

x

R

Qp/f

F

x

H

H

x

On

(Op)n

x

On

(OF)n

x

On

Hi-Z

x

On

(Op)n

x

On

(OF)n

L

On

(OF)n

H

L

L

L

H

H

H

IND.

IND.

x

H

NOTES: 1. Positive Logic:
SIR= To+ T1 + T2 + ... + T47 Tn = C(IO 11 12 ...)(PO P1 ... PS)
2. Either Preset (Active-High) or Output FriaDle (Active-Low) are available, but not both. The desired function is a user-programmable option. 3. i denotes transition from Low-to-High level.
4. R = S = High is an illegal input condition. S. ·=Hor Lor+10V.
6. X =Don't Care (s_S.SV).

LOGIC FUNCTION

Typical State Transition:

I I io I ~R Q2 01 QO o 1

PRESENT STATE

STATE REGISTER

JC· IJ · C · ···

JO JO t1 J Sn+1 NEXTSTATE

VIRGIN STATE
The factory shipped virgin device contains all fusible links intact, such that: 1. PR/OE option is set to PR. Thus, all
outputs will be at "1 ", as preset by initial power-up procedure.
2. All transition terms are disabled (0).
3. All SIR flip-flop inputs are disabled (0).

THERMAL RATINGS

TEMPERATURE

Maximum junction

c 1so0

Maximum ambient

7S°C

Allowable thermal rise ambient to junction

7S°C

SETOo: So= (O:! · 01 ·~)·JC· IJ· C ··· Ro=O
RESET 01: S1=0 R, = (O:! · 01 ·~)"JC· IJ · C .··
HOLD D2: S:!=O
R2=0

4. The device can be clocked via a Test Array pre-programmed with a standard test pattern. NOTE: The Test Array pattern MUST be deleted before incorporating a user program. This is accomplished automatically by any Philips Semiconductors qualified programming equipment.

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee

Supply voltage

+7

Voe

V1N

Input voltage

+S.S

Voe

Vour

Output voltage

+S.S

Voe

l1N

Input currents

--30

+30

mA

lour Tarro Tstg

Output currents Operating temperature range Storage temperature range

+100

mA

0

+7S

oc

-SS

+1SO

oc

NOTES:

1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

October 22, 1993

3S1

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(16 x 48 x 8)

Product specification
PLS105/A

DC ELECTRICAL CHARACTERISTICS
0°C S Tamil S +75°C, 4.75V S Vee S 5.25V

SYMBOL
Input ~ollage2

PARAMETER

V1H

High

V1L

Low

Vic

Clamp3

Output voltage2

TEST CONDITION
Vcc=MAX Vee= MIN Vee= MIN, l1N =-12mA

LIMITS

MIN

TYP1 MAX

2.0

0.8

--0.8

-1.2

UNIT
v v v

VoH

High4

Vol

Low5

Input current

Vee= MIN loH =-2mA IQL=9.6mA

2.4

v

0.35

0.45

v

l1H

High

l1L

Low

l1L

Low (CK input)

Output current

V1N = 5.5V V1N = 0.45V V1N = 0.45V

<1

25

µA

-10

-100

µA

-50

-250

µA

lo(OFF)

Hi-Z states

las

Short circuit 3·7

Ice

Vee supply current!'

Capacitance&

Vcc=MAX VouT = 5.5V VouT = 0.45V VouT = OV
Vee= MAX

1

40

µA

-1

-40

µA

-15

-70

mA

120

180

mA

C1N CouT

Input Output

Vee =5.0V V1N = 2.0V VouT = 2.0V

8

pF

10

pF

NOTES:
1. All typical values are at Vee = 5V, Tamil = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time.
4. Measured with V1L applied to OE and a logic high stored, or with V1H applied to PR. 5. Measured with a programmed logic condition for which the output is at a low logic level, and V1L applied to PR/OE Output sink current is
supplied through a resistor to Vee. 6. Measured with V1H applied to PR/OE. 7. Duration of short circuit should not exceed 1 second.
8. Ice is measured with the PR/OE input grounded, all other inputs at 4.5V and the outputs open.

October 22, 1993

352

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(16 x 48 x 8)

Product specification
PLS105/A

AC ELECTRICAL CHARACTERISTICS
R1 =4700, R2 = 11<0, CL= 30pF, 0°C s Tamb s +75°C, 4.75V s Vee s 5.25V

LIMITS

SYMBOL

PARAMETER

FROM

TO

PLS105

PLS105A

UNIT

MIN TYP1 MAX MIN TYP1 MAX

Pulse width

lcKH

Clock2 High

lcKL

Clock Low

lcKP

Clock period

lpAH

Preset pulse

CK+

CK-

25

15

20

15

ns

CK-

CK+

25

15

20

15

ns

CK+

CK+

50

30

40

30

ns

PR+

PR-

25

15

25

15

ns

Setup time3

t1s1A

Input

Input±

CK+

60

40

ns

t1s1B

Input

Input±

CK+

50

30

ns

t1s1C

Input

Input±

CK+

42

NIA

ns

tis~

Input (through Complement Array)

Input±

CK+

90

70

ns

t1s2B

Input (through Complement Array)

Input

CK+

80

60

ns

t1s2C

Input (through Complement Array)

Input

CK+

72

NIA

ns

tvs

Power-on preset

tPAS

Preset

Vee+

CK-

0

-10

0

-10

ns

PR-

CK-

0

-10

0

-10

ns

Hold time

t1H

Input

CK+

Input±

5

-10

5

-10

ns

Propagation delay

lcKO

Clock

loE

Output enable4

loo

Output disable4

tpA

Preset

tppR

Power-on preset

Frequency of operation3

CK+ OEOE+ PR+ Vee+

Output± OutputOutput+ Output+ Output+

15

30

20

30

20

30

18

30

0

10

15

20

ns

20

30

ns

20

30

ns

18

30

ns

0

10

ns

IMAXC

Without Complement Array

13.9

20.0

MHz

IMAXC

With Complement Array

9.8

12.5

MHz

NOTES:
1. All typical values are at Vee= 5V, Tamb = +25°C. 2. To prevent spurious clocking, clock rise time (10%-90%) s 30ns. 3. See 'Speed vs. OR Loading" diagrams. 4. For 3-State output; output enable times are tested with CL= 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output voltage of VT= (VoH -0.5V) with S 1open, and Low-to-High impedance tests are made to the VT= (Vol+ 0.5V) level with S 1closed.

TEST LOAD CIRCUIT
c,yc2

L > Vee

R1

OE

IO

By

VOLTAGE WAVEFORMS

CL

INPUTS

115 OUT

NOTE:
C1 and C2 are to bypass Vee to GND.

CK

Bz

GND

-=

-= OUTPUTS

MEASUREMENTS: Alt circuit delays are measured at the+1.5V level of Inputs and outputs, unless otherwise specified.
Input Pulses

October 22, 1993

353

PhiHps Semiconductors Programmable Logic Devices
Programmable logic sequencers (16 x 48 x 8)
TIMING DIAGRAMS

~15

1.5V

Sequential Mode

4.5V
Vee
R>-F7 CU<
I0-115
October 22, 1993

Asynchronous Preset
Power-On Preset 354

Product specification
PLS105/A

TIMING DEFINITIONS

SYMBOL

PARAMETER

fcKH

Width of input clock pulse.

fcKL

Interval between clock pulses.

Minimum guaranteed Clock

1~

fcKP

period.

Required delay between

t1s1

beginning of valid input and

positive transition of clock.

Required delay between

beginning of valid input and

positive transition of Clock,

t1s2

when using optional

Complement Array (two

passes necessary through the

AND array).

Required delay between Vee

(after power-on) and negative

tvs

transition of Clock preceding

first reliable clock pulse.

Required delay between

negative transition of

Asynchronous Preset and

Ip Rs

negative transition of Clock

preceding first reliable clock

pulse.

Required delay between

t1H

positive transition of Clock

and end of valid input data.

Delay between positive

transition of clock and when

fcKO

outputs become valid (with

PR/OE Low).

Delay between beginning of

loE

Output Enable Low and when

outpU1s become valid.

Delay between beginning of

Output Enable High and

loo

when outputs are in the

OFF-State.

Delay between input 10

transition to Diagnostic mode

lsRE

and when the outputs reflect

the contents of the State

Register.

Delay between input 10

transition to Logic mode and

lsRD

when the outputs reflect the

contents of the Output

Register.

Delay between positive

lpR

transition of Preset and when

outputs become valid at "1".

Delay between Vee (after

lppR

power-on) and when outputs

become preset at "1 ".

lpRH

Width of preset input pulse.

Minimum guaranteed

IMAX

operating frequency.

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (16 x 48 x 8)

Product specification
PLS105/A

TIMING DIAGRAMS (Continued)

11-115 IO
CLI<

+3V
ov
+10V +3V
ov
+3V
ov

VoH
ao-as--

FO-F5

ov

Diagnostic Mode

SPEED VS. "OR" LOADING
The maximum frequency at which the PLS can be clocked while operating in sequential mode is given by:
(1/fMAX) =Icy= tis+ lcKO
This frequency depends on the number of transition terms Tn used. Having all 48 terms connected in the AND array does not appreciably impact performance; but the number of terms connected to each OR line affects tis. due to capacitive loading. The effect of this loading can be seen in Figure 1, showing the variation of t1s1 with the number of terms connected per OR.
The PLS105 AC electrical characteristics contain three limits for the parameters t1s1 and t1s2 (refer to Figure 1). The first, t1s1A is guaranteed for a device with 48 terms connected to any OR line. t1srn is guaranteed for a device with 32 terms
connected to any OR line. And t1s1c is
guranteed for a device with 24 terms conntected to any OR line.
The three other entries in the AC table, t1s2 A, B, and C are corresponding 48, 32, and 24 term limits when using the on-chip Complement Array.
The PLS105A AC electrical characteristics contain two limits for the parameters t1s1 and t1s2 (refer to Figure 2). The first, t1s1A is guaranteed for a device with 24 terms connected to any OR line. t1srn is guaranteed for a device with 16 terms connected to any OR line.

20 >--+--+--+--+--t--1
101---+-+---+--+--t----I

0

8 16 24 32 40 48

TERMS CONNECTED/OR

Figure 1. PLS105 t1s1 vs. Terms/OR Connected

10>--+--+---+---+----i

0

8 16 ~ ~ 40

TERMS CONNECTED/OR

Figure 2. PLS105A t1s1 vs. Terms/OR Connected

The two other entries in the AC table, t1s2 A and B are corresponding 24 and 16 term limits when using the on-chip Complement Array.

The worst case of t1s for a given application can be determined by identifying the OR line with the maximum number of Tn connections. This can be done by referring to the interconnect pattern in the PLS logic diagram, typically illustrated in Figure 3, or by counting the maximum number of "H" or
"L" entries in one of the columns of the device Program Table.

This number plotted on the curve in Figure 1 or 2 will yield the worst case tis and, by implication, the maximum clocking frequency for reliable operation.

Note that for maximum speed all UNUSED transition terms should be disconnected from the OR array.
(4)-} TRANSITION TERMS Tn

TERMS/ OR (2) (3)

"OR" ARRAY

NOT USED

Figure 3. Typical OR Array Interconnect Pattern

October 22, 1993

355

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (16 x 48 x 8)

Product specification
PLS105/A

LOGIC PROGRAMMING The PLS105/A devices are fully supported by
industry slandard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors' SNAP, Dala 1/0 Corporation's ABELTM and Logical Devices lnc.'s CUPLTM design software packages.
All packages allow Boolean and slate equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.

PRESET/OE OPTION - (P/E)

p~RIOE

E·1

LWAYS

-,..

ENABLED)

OPTION PRESET1

CODE H

OPTION

CODE L

PLS105/A logic designs can also be generated using the program lable entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors SNAP PLD design software package.

PROGRAMMING: The PLS105/A has a power-up preset feature. This feature insures thatthe device will power-up in a known slate with all register elements (Slate and Output Register) at logic High (H). When
programming the device it is important to realize this is the initial slate of the device. You must
provide a next slate jump if you do not wish to use all Highs (H) as the present slate.

To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.
"AND" ARRAY- (I), (P)

PROGRAMMING/SOFTWARE
SUPPORT
Refer to Section 9 (Development Software) and Section 1O (Third-party Programmer/ Software Support) of this dala handbook for additional information.

l,P

rl,,pp

l,P ~l,p r;p

1,P ~l,p r,p

~p ~l,p r,p

I STATE

Tn

Tn STATE
l,P

Tn
STATE
1,p

Tn STATE DON'T CARE

"OR" ARRAY - (N), (F)

"±go-' "±go-' "±go-' ··±go-'

ii;1

R

ii;1

R

n;l

R

ii;1

R

I I I ACTION INACTIVE1· 3

CODE 0

I

ACTION SET

I I CODE H

a : a : "COMPLEMENT" ARRAY - (C)

I

ACTION RESET

I I CODE L

a:

I I - I ACTION NO CHANGE

CODE

a:

l ACTION INACTive1,4

Tn
I I CODE 0

I ACTION GENERATE

Tn
I I CODE A

I ACTION PROPAGATE

Tn
I I CODE ·

Tn

I I - I ACTION TRANSPARENT

CODE

NOTES: 1. This is the initial unprogrammed slate of all links. 2. Any gate Tnwill be unconditionally inhibited if both the true and complement of any input (I or P) are left intact. 3. To prevent simultaneous Set and Reset flip-flop commands, this state is not allowed for N and Flink pairs coupled to active gates Tn (see
flip-flop truth !ables). 4. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn·

ABEL is a trademark of Data l/O Corp. CUPL is a trademark of Logical Devices, Inc.

October 22. 1993

356

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(16 x 48 x 8)

Product specification
PLS105/A

PROGRAM TABLE
CUSTOMER NAME·----------~ PURCHASE ORDER#~~-~~----~ PHILIPS DEVICE #_ _ _ _ _C_F~(X_X_X_X~)_ _ __ CUSTOMER SYMBOLIZED PART#_ _ _ _ _ __ TOTAL NUMBER OF PARTS PROGRAM TABLE_ _ _ _ ~~ _- _- _-_ -- _- _- _-_REV~----------~~-~-DATE~---------------

PROGRAM TABLE ENTRIES

- - - - - - -AN-D- - - - 1~ - - - - -OR- - - - - - -

INACTIVE

0

I INACTIVE

0

GENERATE

A

PROPAGATE

·

I Cn I

SET RESET

H

Na, Fr

L

TRANSPARENT' -

j

NO CHANGE

-

INACTIVE
-1~,P~N'TCARE

0
~ H

11 ~ I ''----- -- ---~-!-!-~----- -- ---

Im, P·

:ESET

!

PIE

AND

OPTI~~ (P/E)

_l

INPUT(lm)

TERM

Cn

-
15

-
14

l3

1ti11-

io

ii

([7

6

0

1

2

3

4

5

6

7

8

9

10
11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35 36

' '

37

'

38

'

39

40

41

42

43 44 45 46 47
PIN NO.

-L
' ' ' '
u oo 21 ~ ~ ~ ~ v 2 3

5 -tl3
'
' ' '
-L
' ' ' '
4 ss

PRESENT STATE (P0 )
2-1--0 5 4--3 2 1--0
1 e9

w
.am~.:J:<:zw;;
~

REMARKS

NEXT STATE (No)

OUTPUT(Fr)
s -·!T3 2 1 0

10 11 12 13 15 16 17 18

NOTES:
1. The FPLS is shipped with all links initially intact. Thus, a background of "O" for all Terms, and an "H" for the PIE option, exists in the table, shown BLANK instead for clarity.
2. Unused Cn. Im. and P5 bits are normally programmed Don't Care(-).
3. Unused Transition Terms can be left blank for future code modification, or programmed as (-)for maximum speed. 4. Letters in variable fields are used as identifiers by logic type programmers.

October 22, 1993

357

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (16x48x8)

TEST ARRAY
The PLS105/A may be subjected to AC and DC parametric tests prior to programming via an on-chip test array.
The array consists of test transition terms 48 and 49, factory programmed as shown below.
Testing is accomplished by clocking the PLS105/A and applying the proper input sequence to 10 - 115 as shown in the test circuit timing diagram.

(I,,· Fn)ll'n
State Diagram

Product specification
PLS105/A

Vee +5V Vee

10-15 P0-5

F0-7

F,

GND
=
PLS Under Test

H

T E
R c
M

48

A

49

Test Array Program

+5V
Vee
ov

Both terms 48 and 49 must be deleted

V1H

during user programming to avoid interfering

CLK

with the desired logic function. This is

accomplished automatically by any Philips

Semiconductors' qualified programming

equipment.

I0-15

F0-7
STATE REGISTER

av

ov

------

....
'

'

.._

___________

.,,,

HIGH LOW

Test Circuit Timing Diagram

H
T E
R c
M
48 49
Test Array Deleted

358

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (16 x 48 x 8)

SNAP RESOURCE SUMMARY DESIGNATIONS

~ 1 '6

··..·!.1w,l1·(!·1h·o·,15./0~·-5 .-· ·

.·.·.··--------t-----+-

Product specification
PLS105/A

T 4 1 - - - - - - - - - - To

OUTPUT REG.

October 22, 1993

:11'Q

Phillps Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x48x8)

Product specification
PLUS105-45

DESCRIPTION
The PLUS 105-45 is a bipolar programmable state machine of lhe Mealy type. Both lhe AND and lhe OR array are userprogrammable. Ail 48 AND gates are connected to the 16 external dedicated inputs (10-115) and to Iha feedback paths of the 6 buried State Registers (Qp0-Qp5). Because the OR array is programmable, any one or all of the 48 transition terms can be connected to any or all of lhe State and Output Registers.
All state transition terms can include True, False and Don't Care states of the controlling state variables. A Complement Transition Array supports complex IF-THEN-ELSE state transitions with a single product term.
The PLUS105-45 device features edge-triggered, J-K flip-flops, which provide the added flexibility of the toggle function which is indeterminate on S-R flip-flops. Because the J-K function is a superset of the S-R flip-flop function, the PLUS105-45 is backward compatible with all 105-type devices that have S-R flip-flops. Asynchronous Preset/Output Enable functions are available.
The PLUS105-45 is pin-for-pin and software compatible with the Philips Semiconductors PLS105 and PLS105A Logic Sequencers, as well as other commercially available 105-type programmable logic devices.
To facilitate testing of state machine designs, diagnostic mode features for register preset and buried state register observability have been incorporated into the PLUS105-45 device architecture.
Ordering codes are listed in the Ordering Information Table.

FEATURES
· 45MHz operating frequency - 55.6MHz clock rate - No OR term loading restrictions
·Available in 300mil skinny DIP, 600mil-wide Plastic DIP and PLCC packages
· Pin and software compatible with olher commericaily available 105 logic sequencers
· 16 input variables · 8 output functions · 48 transition terms · 6-bit State Register · 8-bit Output Register · Transition complement array · Positive edge-triggered clocked J-K (or
S-R) flip-flops · Security fuse · Programmable Asynchronous Preset or
Output Enable · Power-on preset (to all "1 "s) of internal
registers · Power dissipation: 800mW (typ.) · TTL compatible · Single +SV supply · 3-State outputs
APPLICATIONS
· Interface protocols · Sequence detectors · Peripheral controllers ·liming generators · Sequential circuits · Elevator controllers · Security Locking systems ·Counters · Shift registers

PIN CONFIGURATIONS
N Packages
N .. Plastic DIP (600mil-wide) N3 = Plastic DIP (300mil-wide)
A Package
A "" Plastic Leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION 28-pin Plastic Dual-In-Line, 600mil-wide 28-pin Plastic Dual-In-Line, 300mil-wide 28-pin Plastic Leaded Chip Carrier, 450mil-square

ORDER CODE PLUS105-45N PLUS105-45N3 PLUS105-45A

DRAWING NUMBER 0413B 0864D 0401F

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)
FUNCTIONAL DIAGRAM

Product specification
PLUS105-45

147----------10

PIN DESCRIPTION

PINNO. SYMBOL

1

CLK

2-9. 26, 27 10-19,

20-22

113-115

23

112

24

111

25

110

10-13 15-18

FO- F7

19

PR/OE

NAME AND FUNCTION

POLARITY

Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this line is necessary to update the contents of both state and output registers.

ActiveHigh(H)

Logic Inputs: The 13 external inputs to the AND array used to program jump conditions between machine states, as determined by a given logic sequence. True and complement signals are generated via use of "H" and "L".

Active-High/ Low (H/L)

Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when exercising standard TTL levels. When 112 is held at+ 1OV, device outputs FO - F5 reflect the contents of State Register bits Po - P5. The contents of each Output Register remains unaltered.

Active-High/ Low (H/L)

Logic/Diagnostic Input: A 15th external logic input to the AND array, as above, when exercising standard TTL levels. When 111 is held at+ 10V, device outputs FO - F5 become direct
inputs for State Register bits P0 - P5; a Low-to-High transition on the clock line loads the values on pins FO - F5 into the State Register bits P0 - P5. The contents of each Output Register remains unaltered.

Active-High/ Low (H/L)

Logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when exercising standard TTL levels. When 11 O is held at +1OV, device outputs FO - F7 become direct inputs for Output Register bits 00 - 07; a Low-to-High transition on the clock line loads the values on pins FO - F7 into the Output Register bits 00 - 07. The contents of each State Register remains unaltered.

Active-High/ Low (H/L)

Logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight device outputs which normally reflect the contents of Output Register bits 00 - 07, when enabled. When 112 is held at +1OV, FO - F5 = (P0 - P5). When 111 is held at +10V, FO - F5 become inputs to State Register bits P0 - P5. When 110 is held at +10V, FO- F7 become inputs to Output Register bits 00-07.
Preset or Output Enable Input: A user programmable function:
· Preset: Provides an asynchronous preset to logic "1" of all State and Output Register bits. PR overrides Clock, and when held High, clocking is inhibited and FO - F7 are High. Normal clocking resumes with the first full clock pulse following a High-to-Low clock transition, after the Preset signal goes low. See timing definitions.
· Output Enable: Provides an output enable function to buffers FO - F7 from the Output Registers.

ActiveHigh (H)
ActiveHigh (H)
ActiveLow(L)

October 22, 1993

361

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x48x8)

Product specification
PLUS105-45

TRUTH TABLE 1, 2, 3, 4, 5, 6

OPTION

Vee

PR H

rn:

.110

.111

.112

CK
x

J
x

K

Op

OF

F

x

H

H

OF

L

+10V

x

x

i

x

x

Op

L

L

L

+10V

x

x

i

x

x

Op

H

H

L

x

+10V

x

i

x

x

L

OF

L

L

x

+10V

x

i

x

x

H

OF

H

L

x

x

+10V

x

x

x

Op

OF

Op

L

H

x x

x x

.x x x x x

x

Op

OF

OF

x

Op

OF

Hi-Z

+5V

x

+10V

x

x

i

x

x

Op

L

L

x

+10V

x

x

i

x

x

Op

H

H

x

x

+10V

x

i

x

x

L

OF

L

x

x

+10V

x

i

x

x

H

OF

H

L

x

x

+10V

x

x

x

Op

OF

Op

L

x

x

x

x

x

x

Op

OF

OF

L

x

x

x

i

L

x

x

x

i

L

L

Op

OF

OF

L

H

L

L

L

L

x

x

x

i

H

L

H

H

H

L

x

x

x

i

H

H

op

OF

OF

i

x

x

x

x

x

x

x

x

H

H

NOTES: 1. Positive Logic:

J-K(orSIR)=To+T1 +T2 + ... T41 Tn =(Co) (10, 11, 12, ...)(Po, P1, ...Ps)
2. Either Preset (Active-High) or Output Enable (Active-Low) are available, but not both. The desired function is a user-programmable option.
i 3. denotes transition from Low-to-High level.
4. ·=Hor Lor+ 10V
5. X =Don't Care (S: 5.5V) 6. When using the Fn pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-Stated and the indicated levels
on the output pins are forced by the user.

VIRGIN STATE
A factory-shipped virgin device contains all fusible links intact, such that: 1. PR/OE option is set to PR. Note that even
if the PR function is not used, all registers are preset to "1" by the power-up procedure.
2. All transition terms are disabled (0).
3. All J-K flip-flop inputs are disabled (0).

October 22, 1993

362

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 48 x 8)
LOGIC DIAGRAM
19 110 111 112 113 114 115
N

Product specification
PLUS105-45
(OPTION) r.===:;:f_----f1 PR/OE
p

47 · · · · · · 40 39 · · · · · · 32 31 · · · · · · 24 23 · · · · · · 16 15 · · · · · · 8
NOTES: 1. All AND gate inputs with a blown link float to a logic "1 ". 2. AILOR gate inputs with a blown fuse float to logic "O". 3. .·.·.·.·. Programmable connection.

7 ······ 0

October 22, 1993

363

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)

Product specification
PLUS105-45

COMPLEMENT ARRAY DETAIL

P47 P_46 P45 · · · ·

PO

co
')
y TOOR ARRAY

The complement array is a special sequencer feature that is often used for detecting illegal states. It is also ideal for generating IF-THEN-ELSE logic statements with a minimum number of product terms.
The concept is deceptively simple. If you subscribe to the theory that the expressions (/A· /B · /C) and(~) are equivalent, you will begin to see the value of this single term NOR array.
The complement array is a single OR gate with inputs from the AND array. The output of the complement array is inverted and fedback to the AND array (NOR function). The output of the array will be LOW if any one or more of the AND terms connected to it are active (HIGH). If, however, all the connected terms are inactive (LOW), which is a classic unknown state, the output of the complement array will be HIGH.

Consider the product terms A, B and D that represent defined states. They are also connected to the input of the complement array. When the condition (not A and not B and not D) exists, the Complement Array will detect this and propagate an Active-High signal to the AND array. This signal can be connected to product term E, which could be used in turn to preset the state machine to a known state. Without the complement array, one would have to generate product terms for all unknown or illegal states. With very complex state machines, this approach can be prohibitive, both in terms of time and wasted resources.
Note that use of the Complement Array adds an additional delay path through the device. Refer to the AC Electrical Characteristics for details.

THERMAL RATINGS
TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction

150°C 75°C 75°C

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee

Supply voltage

+7.0

VDc

V1N

Input voltage

+5.5

Voc

VouT

Output voltage

+5.5

VDc

l1N

Input currents

-30

+30

mA

louT

Output currents

+100

mA

Tamb

Operating temperature range

0

+75

oc

Tstg

Storage temperature range

--B5

+150

oc

NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device.This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

LOGIC FUNCTION

PRESENT STATE Ji·H· C · ··· NEXT STATE

SETOo:Jo =(02. a,. Oo). Ji· IJ. c ...
Ko=O

caa · o a RESET 01: J1=0
K1 =

2 · 1 · Oo) ·Ji· JJ · c ...

HOLD 02: J2 =O
K2 =0
RESET Qa:J3 =(<la· 02 · 01 · OQ) ·Ji· IJ· C ..·
K3 = !<la ·02 · a1 ·Ool ·Ji·JJ· c ···

October 22, 1993

364

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x48x8)

Product specification
PLUS105-45

DC ELECTRICAL CHARACTERISTICS
0°C s Tarro s 75°C, 4.75V S Vee S 5.25V

SYMBOL

PARAMETER

TEST CONDITION

Input voltage2

V1H

High

Vee= MAX

V1L

Low

Vic

Clamp3

Output voltage2

Vee= MIN Vee= MIN, 11N =-12mA

Vee= MIN

VoH

High

Vol

Low

Input current

loH =-2mA loL = 9.6mA

l1H

High

l1L

Low

Output current

Vee= MAX
v,N =Vee
V1N = 0.45V

lo(OFF) los

Hi-Z state Short circuit3· 4

Vee= MAX Vour = 2.7V Vour = 0.45V Vour = OV

Ice

Vee supply current5

Capacitance

Vee= MAX

Vee =5.0V

C1N

Input

V1N = 2.0V

Gour

Output

Vour = 2.0V

NOTES: 1. All typical values are at Vee = 5V, Tarm = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Duration of short circuit should not exceed 1 second. 5. Ice is measured with the PR!Ot: input grounded, all other inputs at 4.5V and the outputs open.

LIMITS MIN TYP1 MAX

2.0

0.8

--0.8

-1.2

2.4

0.35

0.45

<1

30

-20

-250

1

40

-1

-40

-15

-70

160

200

8 10

UNIT
v v v
v v
µA µA
µA µA mA mA
pF pF

October 22, 1993

365

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x48x8)

Product specification
PLUS105-45

AC ELECTRICAL CHARACTERISTICS
R, = 470n, R2= 1kn, CL= 30PF, O'C :S Tamb :S +75'C, 4.75V :S Vee :S5.25V

SYMBOL

PARAMETER

Pulse Width

lcKH

Clock High

lcKL

Clock Low

lcKP

Clock Period

lpRH

Preset pulse

Setup Time

t1s1

Input

t1s2

Input (through Complement Array)

!vs

Power-on preset

Ip Rs

Clock resume (after preset)

INveK

Clock lockout (before preset)

Hold Time

l1H

Input

Diagnostic Mode

IRJS

Initialization of diagnostic mode

tRJH

Clock for diagnostic mode

Propagation Delay3

lcKO

Clock

loE

Output enable2

too

Output disable2

lpR

Preset

IPPR

Power-on preset

Frequency of Operation

FROM
CK+ CKCK+ PR+
Input± Input± Vee+ PRCK-

TO
CKCK+ CK+ PR-
CK+ CK+ CKCKPR-

CK+

Input±

110, 111 orl12+ (to 10V)
CK+

Fn as inputs Register input jam

CK+ OEOE+ PR+ Vee+

Output± OutputOutput+ Output+ Output+

LIMITS MIN TYP1 MAX

9

8

9

8

18

16

10

8

13

12

23

20

0

-10

0

-5

10

5

0

--5

50

25

50

25

8

9

8

9

8

9

12

15

0

10

UNIT
ns ns ns ns
ns ns ns ns ns
ns
ns ns
ns ns ns ns ns

fMAX1

Without Complement Array

(ilS1 : leKO)

Input±

Output±

45.5

50.0

MHz

fMAX2 fMAX3

With Complement Array

( t1s2 : teKO)

Input thru Complement
Array±

Internal feedback without Complement Array

~ (ieKL lcKH )

Register Output±

Output± Register Input±

31.3 55.6

35.7 62.5

MHz MHz

fMAX4

Internal feedback with Complement Array ( t1:2)

Register Output thru Complement
Array±

Register Input±

43.5

50.0

MHz

feLK

Clock frequency

CK+

CK+

55.6

62.5

MHz

NOTES:
1. All typical values are at Vee = 5V, Tamb = +25'C. 2. For 3-State output; output enable times are tested with CL= 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output voltage of VT= (VoH -0.5V) with S 1open, and Low-to-High impedance tests are made to the VT= (VoL + 0.5V) level with S 1closed. 3. All propagation delays and setup times are meausred and specified under worst case conditions.

October 22, 1993

366

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)

Product specification
PLUS105-45

TIMING DIAGRAMS

10-115

CLK FO-F7

OE

10-115

1.5V

'<>E
Sequential Mode

+3V
ov
+3V 1.5V
ov
VoH
VoL +3V
ov

CLK FO-F7
PR

1.SV

1.SV

tcKH

ICKL

-----ov

1.SV

1.5V

1.5V

- - - - ._.....__ _ _ _ _ _ _ __ , ' - - - - - - VoL

1.5V tPRH
Asynchronous Preset

J--tcKO 1.SV

Vee

FO-F7

1.svt- CLK

------' 'cK

ov

I0-115

October 22, 1993

Power-On Preset 367

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x48x8)

Product specification
PLUS105-45

TIMING DIAGRAMS (Continued)

$ 8.0V

+10V
+3V

110
ov

FO- F7 .,...,,.,..,..,..,...,..,..,,.,..,..,..,...,..,..I;..------..........,'R,.J,,H..,..,..,..,..,..'7"11 +3V

(INPUTS) .._........._........................._..............., 1_ _ _ _ ___,,.__, ~-.......- ......... OV

+3V
CLK

-07) ( OQOUTPUT
REG.

Diagnostic Mode-Output Register Input Jam

111
IRJH FO-~P"":il'7'7':::...,.7":r'7'7'7':::...,.7":rll.lr-----...._-"I
PNPUTS) "-'"""'"""""""'"""""'-'"""'"""""""'""-U '------....,.--'

CLK

-~s

+10V 8.0V
+3V
ov
+3V
+3V

Diagnostic Mode-State Register Input Jam

I0-111,

+3V

113-115

ov

+10V

+3V
112
ov

+3V
CLK
ov

~~Ii~:~~---

VoH

ao- as - -

Vol

FO-FS

(Fn)

October 22, 1993

ov
Diagnostic Mode-State Register Outputs
368

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 48 x 8)

Product specification
PLUS105-45

TIMING DEFINITIONS

SYMBOL

PARAMETER

l1H

Required delay between

positive transition of Clock and

end of valid Input data.

t1s1

Required delay between

beginning of valid input and

positive transition of Clock.

t1s2

Required delay between

beginning of valid Input and

positive transition of Clock,

when using optional

Complement Array (two

passes necessary through the

AND Array).

lcKH

Width of input clock pulse

lcKL

Interval between clock pulses.

lcKO

Delay between positive

transition of Clock and when

Outputs become valid (with

PR/OE Low).

lcKP

Minimum guaranteed clock

period.

tNveK

Required delay between the negative transition of the clock and the negative transition of the Asynchronous PRESET to guarantee that the clock edge is not detected as a valid negative transition.

TEST LOAD CIRCUITS

SYMBOL

PARAMETER

loo

Delay between beginning of

Output Enable High and when

Outputs are in the OFF-state.

toE

Delay between beginning of

Output Enable Low and when

Outputs become valid.

tppR

Delay between Vee (after

power-on) and when Outputs

become presetat"1".

lpR

Delay between positive

transition of Preset and when

Outputs become valid at "1 ".

tPRH

Width of preset input pulse.

tpRS

Required delay between

negative transition of

Asynchronous Preset and the

first positive transition of

Clock.

!RH

Required delay between

positive transition of clock and

the end of valid input data

(FQ..-F7 as inputs), when

jamming data into the State or

Output registers in the

Diagnostic Mode.

SYMBOL

PARAMETER

IRJH

Required delay between

positive transition of clock and

return of input 110, 111OR112

from Diagnostic Mode (10V).

IRJs

Required delay between

inputs 110, 111 orl12transition

to Diagnostic Mode (10V), and

when the output pins become

available as inputs.

ls RD

Delay between input (112)

transition to Logic mode and

when the Outputs reflect the

contents of the Output

Register.

ls RE

Delay between input 112

transition to Diagnostic Mode

and when the Outputs reflect

the contents of the State

Register.

tvs

Required delay between Vee

(after power-on) and negative

transition of Clock preceding

first reliable clock pulse.

feLK

Minimum guaranteed clock

frequency (register toggle

frequency)

IMAX

Minimum guaranteed

operating frequency.

VOLTAGE WAVEFORMS

C1YC2

L Y Vee

10

Rl

INPUTS
NOTE:
C1 and C2 are to bypass Vee to GND.

OUT

115

F7

CK GND

R1

R2

CL

2.Sns

2.5ns

MEASUREMENTS: All circuit delays are measured at the+ 1.SV level of inputs and outputs, unless otherwise specified.

Input Pulses

LOGIC PROGRAMMING
PLUS 105-45 is fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips Semiconductors' SLICE and SNAP design software packages. ABEL'·, CUPLTM and PALASM® 90 design software packages also support the PLUS 105-45 architecture.

All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PLUS105-45 logicdesigns can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SLICE only. The SLICE design

package is available, free of charge, to qualified users.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.

ABEL is a trademark of Data 1/0 Corp. CUPL is a trademark of logical Devices, Inc. PALASM is a registered trademark of AMO Corp.

October 22, 1993

369

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)
PRESET/OE OPTION - (P/E)

Product specification
PLUS105-45

OPTION PRESET1

CODE H

OPTION

CODE L

PROGRAMMING THE PLUS105-45:
The PLUS105-45 has a power-up preset feature. This feature insures that the device will
power-up in a known state with all register elements (State and Output Register) at logic High (H). When programming the device it is important to realize this is the initial state of the
device. You must provide a next state jump if you do not wish to use all Highs (H) as the
present state.

"AND" ARRAY -(I), (P)

[

STATE

J L CODE

L l J INACTIVE1· 2

0

l,P~~p
·yT I.ii
Tn STATE
].p

Y. l,P~l,p I.ii

r· C~DE STATE
DON'T CARE

1

"OR" ARRAY - (N), (F)

"iW' n,f

K

I ACTION TOGGLE1

I I CODE 0

"iW' n,f

K

I ACTION SET

I I CODE H

"iW' ii;1

K

I

ACTION RESET

I I CODE L

"iW' ii,l

K

I I I ACTION NO CHANGE

CODE
-

a: a: a: a: "COMPLEMENT"ARRAY- (C)

I ACTION INAC11VE113

Tn
I I CODE 0

I ACTION GENERATE

Tn
I I CODE A

I ACTION PROPAGATE

Tn
I I CODE ·

Tn

I J [ ACTION L 1 J TRANSPARENT

CODE
-

NOTES: 1. This is the initial unprogrammed state of all link pairs. 2. Any gate T0 will be unconditionally inhibited if both the true and complement fuses of any input {l,P) are left intact. 3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn·

October 22, 1993

370

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)

Product specification
PLUS105-45

PLUS105 PROGRAM TABLE

CUSTOMER NAME

PURCHASE ORDER#

PHILIPS DEVICE#

CF(XXXX)

CUSTOMER SYMBOLIZED PART#

TOTAL NUMBER OF PARTS

PROGRAM TABLE

REV

DATE

PROGRAM TABLE ENTRIES

- - - - - - -AN-D- - - - 1_I - - - - -OR- - - - - - -

INACTIVE

0

I INACTIVE

0

GENERATE PROPAGATE

. A

- TRANSPARENT'

Cn

I I

...SmE:.T.IQGGl.f_ RESET

' H
L

I

NO CHANGE

-

Ns, Fr

INACTIVE l,P l,P DON'T CARE

0 H L
-

11 i I 1
m· P·

'I----~-=-E-S-E-T-O--P-T-IO--N--~ ----P--IE

-
-

AND

TERM

Cn

-
15

-
14

l3

1~11

io

0

1

2

3

4

5

6

I

7

I

8

I

9

I

10

11

12

13

14

15

I

16

I

17

I

18

I

19

20

21

22

23

24

25

I

26

I

27

I

28

I

29

30

31

32

33

34

35

I

36

I

37

I

38

I

39

40

41

42

43

44

45

I

46

I

47

I

INPUT(lm)
9 aT1 6
I I I I
I I I I
I I I I
I I I I
I I I I

5 -413
I I I I
I I I I
I I I I
I I I I
I I I I

PIN NO.

20 21 22 23 24 25 26 27 2 3 4 5 6

- - PRESENT STATE (P8 )

--
2 1 0

5

--
4 3

2

--
1 0

7 8 9

OPTION(PIE)

J_

OR

- - - - REMARKS
- ----- -

NEXT STATE (Na)

OUTPUT(Fr)

-
5

4

3

-
2

1

-- --
0 7 6

· -4r3

2

--
1 0

I I I I
I I I I

I I I I

I
'
I I

I

-t-1

I

I

I

10 11 12 13 15 16 17 18

w ..J w
aI~l:l <:z:;;
:£

NOTES:
1. The device is shipped with all links initially intact. Thus, a background of "O" for all Terms, and an "H" for the PIE option, exists in the table, shown BLANK instead for clarity.
2. Unused C0 , Im. and Ps bits are normally programmed Don't Care(-).
3. Unused Transition Terms can be left blank for future code modification, or programmed as(-) for maximum speed. 4. Letters in variable fields are used as identifiers by logic type programmers.

October 22, 1993

371

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 48 x 8)
SNAP RESOURCE SUMMARY DESIGNATIONS

Product specification
PLUS105-45

F

T 4 7 - - - - - - - - - - To

OUTPUT REG.

October 22, 1993

372

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x48x8)

Product specification
PLUS105-55

DESCRIPTION
The PLUS 105-55 is a bipolar programmable state machine of the Mealy type. Both the AND and the OR array are userprogrammable. All 48 AND gates are connected to the 16 external dedicated inputs (ID - 115) and to the feedback paths of the 6 buried State Registers (Qp0-0p5). Because the OR array is programmable, any one or all of the 48 transition terms can be connected to any or all of the State and Output Registers.
All state transition terms can include True, False and Don't Care states of the controlling state variables. A Complement Transition Array supports complex IF-THEN-ELSE state transitions with a single product term.
The PLUS105-55 device features edge-triggered, J-K flip-flops, which provide the added flexibility of the toggle function which is indeterminate on S-R flip-flops. Because the J-K function is a superset of the S-R flip-flop function, the PLUS105-55 is backward compatible with all 105-type devices that have S-R flip-flops. Asynchronous Preset/Output Enable functions are available.
The PLUS105-55 is pin-for-pin and software compatible with Philips Semiconductors PLS105 and PLS105A Logic Sequencers, as well as other commercially available 105-type programmable logic devices.
To facilitate testing of state machine designs, diagnostic mode features for register preset and buried state register observability have been incorporated into the PLUS105-55 device architecture.
Ordering codes are listed in the Ordering Information Table.

FEATURES
· 55MHz operating frequency - 71.4MHz clock rate - No OR term loading restrictions
·Available in 300mil skinny DIP, 60Dmil-wide DIP, and PLCC packages
· Pin and software compatible with other commerically available 105 sequencers
· 16 input variables · 8 output functions · 48 transition terms · 6-bit State Register · 8-bit Output Register · Transition complement array · Positive edge-triggered clocked J-K (or
S-R) flip-flops · Security fuse · Programmable Asynchronous Preset or
Output Enable · Power-on preset to (all "1 "s) of internal
registers · Power dissipation: 800mW (typ.) · TTL compatible · Single +5V supply · 3-State outputs
APPLICATIONS
· Interface protocols · Sequence detectors · Peripheral controllers · Timing generators · Sequential circuits · Elevator controllers · Security Locking systems ·Counters · Shift registers

PIN CONFIGURATIONS
N Packages
N: Plastic DIP (600mil-wide) N3 =Plastic DIP (3DOmil-wide)
A Package
F5 F4 GND F3 F2 F1 FD A= Plastic Leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION 28-pin Plastic Dual-In-Line, 60Dmil-wide 28-pin Plastic Dual-In-Line, 300mil-wide 28-pin Plastic Leaded Chip Carrier, 450mil-square

ORDER CODE PLUS105-55N PLUS105-55N3 PLUS105-55A

DRAWING NUMBER 04138 0864D 0401F

October 22, 1993

373

853--1429 11164

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)
FUNCTIONAL DIAGRAM

Product specification
PLUS105-55

T 4 7 - - - - - - - - - - To

PIN DESCRIPTION

PINNO.

SYMBOL

1

CLK

2-9, 26, 27 20-22

10-19, 113-115

23

112

24

111

25

110

10-13 15-18

FO - F7

19

PR/OE

NAME AND FUNCTION
Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this line is necessary to update the contents of both state and output registers.
Logic Inputs: The 13 external inputs to the AND array used to program jump conditions between machine states, as determined by a given logic sequence. True and complement signals are generated via use of "H" and "L".
Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when exercising standard TIL levels. When 112 is held at +1OV, device outputs FO - FS reflect the contents of State Register bits PO - PS. The contents of each Output Register remains unaltered.
Logic/Diagnostic Input: A 15th external logic input to the AND array, as above, when exercising standard TIL levels. When 111 is held at +1OV, device outputs FO - FS become direct inputs for State Register bits PO - PS; a Low-to-High transition on the clock line loads the values on pins FO - FS into the State Register bits PO - PS. The contents of each Output Register remains unaltered.
Logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when exercising standard TIL levels. When 110 is held at +10V, device outputs FO - F7 become direct inputs for Output Register bits 00 - 07; a Low-to-High transition on the clock line loads the values on pins FO - F7 into the Output Register bits 00 - 07. The contents of each State Register remains unaltered.
Logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight device outputs which normally reflect the contents of Output Register bits 00 - 07, when enabled. When 112 is held at+ 10V, FO - FS =(PO - PS). When 111 is held at+10V, FO - FS become inputs to State Register bits PO - PS. When 110 is held at+ 10V, FO - F7 become inputs to Output Register bits 00-07.
Preset or Output Enable Input: A user programmable function:
· Preset: Provides an asynchronous preset to logic "1" of all State and Output Register bits. PR overrides Clock, and when held High, clocking is inhibited and FO - F7 are High. Normal clocking resumes with the first full clock pulse following a High-to-Low clock transition, after the Preset signal goes Low. See timing definitions.
·Output Enable: Provides an output enable function to buffers FO - F7 from the Output Registers.

POLARITY ActiveHigh (H)
Active-High/ Low (H/L)
Active-High/ Low (H/L)
Active-High/ Low (H/L)
Active-High/ Low (H/l)
ActiveHigh (H)
ActiveHigh (H)
ActiveLow(L)

October 22, 1993

374

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)

Product specification
PLUS105-55

TRUTH TABLE1, 2, 3, 4, 5, 6

OPTION

Vee

PR
H

OE

.110

.111

.112

CK
x

J
x

K

Qp

QF

F

x

H

H

OF

L

+10V

x

x

i

x

x

Op

L

L

L

+10V

x

x

i

x

x

Op

H

H

L

x

+10V

x

i

x

x

L

OF

L

L

x

+10V

x

i

x

x

H

OF

H

L

x

x

+10V

x

x

x

Op

OF

Op

L

H

x x x x

x .

x x

x x

x

Op

OF

OF

x

Op

OF

Hi-Z

+5V

x

+10V

x

x

i

x

x

Op

L

L

x

+10V

x

x

i

x

x

Op

H

H

x

x

+10V

x

i

x

x

L

OF

L

x

x

+10V

x

i

x

x

H

OF

H

L

x

x

+10V

x

x

x

Op

OF

Op

L

x

x

x

x

x

x

Op

OF

OF

L

x

x

x

i

L

L

Op

OF

OF

L

x

x

x

i

L

H

L

L

L

L

x

x

x

i

H

L

H

H

H

L

x

x

x

i

H

H

op

~

~

i

x

x

x

x

x

x

x

x

H

H

NOTES: 1. Positive Logic:

J-K(orS/R)=To+T1 +T2 + ... T48 Tn =(Co) (10, 11, 12, ---)(Po, P1, ...P5)
2. Either Preset (Active-High) or Output Enable (Active-Low) are available, but not both. The desired function is a user-programmable option.
i 3. denotes transition from Low-to-High level.
4. *=Hor Lor +10V
5. X = Don't Care (~ 5.5V) 6. When using the Fn pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-Stated and the indicated levels
on the output pins are forced by the user.

VIRGIN STATE
A factory-shipped virgin device contains all fusible links intact, such that: 1. PR/OE option is set to PR. Note that
even if the PR function is not used, all registers are preset to "1" by the power-up procedure.
2. All transition terms are disabled (0).
3. All J-K flip-flop inputs are disabled (0).

October 22, 1993

375

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 48 x 8)
LOGIC DIAGRAM
110 111 112 113 114 115

Product specification
PLUS105-55

NOTES:

1. All AND gate inputs with a blown link float to a logic "1 ".

2. OR gate inputs with a blown fuse float to logic "O".

3.

Programmable connection.

October 22, 1993

376

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x48x8)

Product specification
PLUS105-55

COMPLEMENT ARRAY DETAIL

P47 P46 P45 · · · ·

PO

co
TOOR ARRAY

The complement array is a special sequencer feature that is often used for detecting illegal states. It is also ideal for generating IF-THEN-ELSE logic statements with a minimum number of product terms.
The concept is deceptively simple. If you subscribe to the theory that the expressions (/A· /B ·IC) and(~) are equivalent, you will begin to see the value of this single term NOR array.
The complement array is a single OR gate with inputs from the AND array. The output of the complement array is inverted and fedback to the ANO array (NOR function). The output of the array will be LOW if any one or more of the AND terms connected to it are active (HIGH). If, however, all the connected terms are inactive (LOW). which is a classic unknown state, the output of the complement array will be HIGH.

Consider the product terms A, B and D that represent defined states. They are also connected to the input of the complement array. When the condition (not A and not B and not 0) exists, the Complement Array will detect this and propagate an Active-High signal to the AND array. This signal can be connected to product term E, which could be used in turn to preset the state machine to a known state. Without the complement array, one would have to generate product terms for all unknown or illegal states. With very complex state machines. this approach can be prohibitive, both in terms of time and wasted resources.
Note that use of the Complement Array adds an additional delay path through the device. Refer to the AC Electrical Characteristics for details.

THERMAL RATINGS
TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction

150°C 75°C 75°C

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

PARAMETER

RATINGS

UNIT

MIN

MAX

Vee

Supply voltage

+7.0

Voe

V1N

Input voltage

+5.5

Voe

Vour

Output voltage

+5.5

Voe

l1N

Input currents

-30

+30

mA

lour Tamb Tstg

Output currents Operating temperature range Storage temperature range

+100

mA

0

+75

oc

-65

+150

oc

NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

LOGIC FUNCTION

I I I I ~R 03 02 01 QO 1 0 1 10

PRESENT STATE

STATE REGISTER

JI . B" · C · ···

JO IO IO t1 I Sn+ 1 NEXTSTATE

SETQo:Jo = (ll"2. o,. Ool. JI:. B". c ... Ko :0
RESET 01:J1=0 K1 = (03 · 0"2 · 01 · ll"o) ·JI· B" · C ··.
HOLD 02: J2 =0
K2=0
RESET03:J3 :(03 · 0"2 · 01 · Ool ·JI· B"· C ···
K3= (Dl ·0"2· 01 ·ll"o) ·Jl·B"· C ···

October 22, 1993

377

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x48x8)

Product specification
PLUS105-55

DC ELECTRICAL CHARACTERISTICS
0°C s Tamb s 75°C, 4.75V s Vcc s 5.25V

SYMBOL

PARAMETER

TEST CONDITIONS

Input voltage2

V1H

High

V1L

Low

Vic

Clamp3

Output vollage2

Vcc=MAX Vee= MIN Vee= MIN, l1N =-12mA

VoH

High

VoL

Low

Input current

Vee= MIN loH=-2mA loL =9.6mA

l1H

High

l1L

Low

Output current

Vcc=MAX V1N =Vee V1N = 0.45V

locoFFJ

Hi-Z state

las

Short circuit3· 4

Ice

Vee supply currents

Capacitance

Vee= MAX VouT = 2.7V VouT =0.45V VouT = OV Vee =MAX

Vee =5.0V

C1N

Input

V1N = 2.0V

CouT

Output

VouT = 2.0V

NOTES: 1. All typical values are at Vee= 5V, Tarrti = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Duration of short circuit should not exceed 1 second. 5. Ice is measured with the PR/OE input grounded, all other inputs at 4.5V and the outputs open.

LIMITS

MIN

TYP1 MAX

2.0

0.8

--0.8

-1.2

2.4

0.35

0.45

<1

30

-20

-250

1

40

-1

-40

-15

-70

160

200

8 10

UNIT
v v v
v v
µA µA
µA µA mA mA
pF pF

October 22, 1993

378

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 48 x 8)

Product specification
PLUS105-55

AC ELECTRICAL CHARACTERISTICS R1 =470Q, R2 = 1Kn, CL= 30pF, O"C s Tamb s +75"C, 4.75V s Vee s 5.25V

SYMBOL

PARAMETER

Pulse Width

lcKH

Clock High

lcKL

Clock Low

lcKP

Clock Period

tPRH

Preset pulse

Setup Time

t1s1

Input

t1s2

Input (through Complement Array)

tvs

Power-on preset

tPRS

Clock resume (after preset)

INVCK

Clock lockout (before preset)

Hold Time

l1H

Input

Diagnostic Mode

IRJS

Initialization of diagnostic mode

tRJH

Clock for diagnostic mode

Propagation Delay2

lcKO

Clock

loE

Output enable3

loo

Output disable3

IPR

Preset

lppR

Power-on preset

Frequency of Operation

FROM

TO

CK+ CKCK+ PR+

CKCK+ CK+ PR-

Input± Input± Vee+ PRCK-

CK+ CK+ CKCKPR-

CK+

Input±

110, 111or112 + (to 10V)
CK+

Fn as inputs Register input jam

CK+ OEOE+ PR+ Vee+

Output± OutputOutput+ Output+ Output+

LIMITS MIN TYP1 MAX

7

6.5

7

6.5

14

13

10

6.0

10

9.5

20

16.0

0

0

0

0

12

10.0

0

-5

50

25

50

25

7

6

6

6

6

6

12

15

5

10

UNIT
ns ns ns ns
ns ns ns ns ns
ns
ns ns
ns ns ns ns ns

fMAX1 fMAX2 fMAX3

Without Complement Array

C1s1 :teKO)

Input±

With Complement Array
Internal feedback without Complement Array

Cs2:tCKo) ( leKL : lcKH )

Input thru Complement
Array±
Register Output±

Output± Output± Register Input±

55.6 35.7 71.4

60.6 40.0 76.9

MHz MHz MHz

fMAX4

Internal feedback with Complement Array (i,:2)

Register Output

thru Complement Register Input±

50.0

55.6

Array±

MHz

feLK

Clock period

CK+

CK+

71.4

76.9

MHz

NOTES:
1. All typical values are at Vee = 5V, Tamb = +25"C. 2. All propagation delays and setup times are meausred and specified under worst case conditions. 3. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output voltage of VT= (VoH -0.5V) with S 1open, and Low-to-High impedance tests are made to the VT= (VOL+ 0.5V) level with S1closed.

October 22, 1993

379

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)

Product specification
PLUS105-55

TIMING DIAGRAMS

+3V 10-115
ov

+3V

I,

CUC

1.sv

ov

YOH FO-F7
VOL
+3V OE
ov

Sequential Mode

I0-115

1.5V

CUC FO-F7

PR

+3V

ov

+3V

1.SV

1.5V

ov

tcKH

tcKL

YOH

1.SV

1.5V

1.5V

VOL

IPR

1.SV IPRH

r-tcKO +3V
1.5V ov

Asynchronous Preset

+SY
Vee ov

FO-F7

1.5V

[FnJ = 1

1..5

VoL

CLK
_____t..SJVt- tcK
tvs

+3V t.SV
ov

October 22, 1993

Power-On Preset 380

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)

Product specification
PLUS105-55

TIMING DIAGRAMS (Continued)

+10V
a.ov
+3V

110
ov

.,..,....,...,...._,....,...,...._,....,,......._,....,~

lRJH , _ _ _ _ _ _. . __ _ ,~,..,..,..,..,,.......,..+3V

FO-F7

(INPUTS) IL.L..'-":..L.C...'-":..L.C...'-":..L.L..rT " - - - - - - -.....- " I , ................................ ov

+3V ClK

(

00 -07)
OUTPUT

REG.

Diagnostic Mode-Output Register Input Jam

+10V
a.av
+3V
111
ov
...,...,...,.......,,_...._.....,...,...._,....,...,., , ______.....___ IR,..J.H.,...,.....,..,..'P""T +3V
FO-F5
(INPUTS) L.'°"':..L.L..'°"':..L.L..'°"':..L.L..'°"'J' ' - - - - - - - . . . . . - - " ,............._._........__. OV

+3V ClK

( PSTOA-TPE S) REG.

-·is

Diagnostic Mode-Slate Register Input Jam

I0-111,

+3V

113-115

1.SV

ov

+10V
+3V 112
ov

+3V ClK
ov

~~~~~~~---

VoH

ao-as--

Vol

VoH FO-F5
Vol

October 22, 1993

ov Diagnostic Mode-State Register Outputs
381

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)

Product specification
PLUS105-55

TIMING DEFINITIONS

SYMBOL

PARAMETER

l1H

Required delay between

positive transition of Clock and

end of valid Input data.

l1s1

Required delay between

beginning of valid input and

positive transition of Clock.

t1s2

Required delay between

beginning of valid Input and

positive transition of Clock,

when using optional

Complement Array (two

passes necessary through the

AND Array).

lcKH lcKL lcKO

Width of input clock pulse
Interval between clock pulses.
Delay between positive transition of Clock and when Outputs become valid (with PR/OE Low).

lcKP

Minimum guaranteed clock

period.

INVCK

Required delay between the negative transition of the clock and the negative transition of the Asynchronous PRESET to guarantee that the clock edge is not detected as a valid negative transition.

TEST LOAD CIRCUITS

SYMBOL

PARAMETER

too

Delay between beginning of

Output Enable High and when

Outputs are in the OFF-state.

toe

Delay between beginning of

Output Enable Low and when

Outputs become valid.

lppR

Delay between Vee (after

power-on) and when Outputs

become preset at "1".

lpR

Delay between positive

transition of Preset and when

Outputs become valid at" 1".

IPRH IPRS
IRH

Width of preset input pulse.
Required delay between negative transition of Asynchronous Preset and the first positive transition of Clock.
Required delay between positive transition of clock and the end of valid input data (FO - F7 as inputs), when jamming data into the State or Output registers in the Diagnostic Mode.

SYMBOL

PARAMETER

IRJH

Required delay between

positive transition of clock and

return of input 110, 111 or 112

from Diagnostic Mode (10V).

IRJs

Required delay between

inputs 110, 111or112 transition

to Diagnostic Mode (10V), and

when the output pins become

available as inputs.

ls RD

Delay between input (112)

transition to Logic mode and

when the Outputs reflect the

contents of the Output

Register.

l s RE

Delay between input 112

transition to Diagnostic Mode

and when the Outputs reflect

the contents of the State

Register.

tvs

Required delay between Vee

(after power-on) and negative

transition of Clock preceding

first reliable clock pulse.

fcLK

Minimum guaranteed clock

frequency (register toggle

frequency)

IMAX

Minimum guaranteed

operating frequency.

VOLTAGE WAVEFORMS

Vee

lo

OUT INPUTS

CK
NOTE: C1 and C2 are to bypass Vee to GNO.

LOGIC PROGRAMMING
PLUS105-55 is fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips Semiconductors' SNAP design software package. ABELTM, CUPLTM and PALASM® 90 design software packages also support the PLUS105-55 architecture.

All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PLUS105-55 logic designs can also be generated using the program table entry format, which is detailed on the following

ABEL Is a trademark of Data VO Corp. CUPL is a trademark of Logical Devices, Inc. PALASM is a registered trademark of AMO Corp.

October 22, 1993

382

2.Sns

2.Sns

MEASUREMENTS: All circuit delays are measured at the+1.5V level of Inputs and outputs, unless otherwise specified.

Input Pulses

pages. This program table entry format is
supported by SNAP.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 48 x 8)
PRESET/OE OPTION - (P/E)

Product specification
PLUS105-55

OPTION PRESET1

CODE H

OPTION OE

CODE

PROGRAMMING THE PLUS105-55: The PLUS105-55 has a power-up preset feature. This feature insures that the device will power-up in a known state with all register elements (State and Output Register) at logic High (H). When programming the device it is important to realize this is the initial state of the device. You must provide a next state jump if you do not wish to use all Highs (H) as the present state.

"AND" ARRAY - (I), (P)
l,P~:::
9T
L ±C~DE j 0
~~~~~~~~~~
STATE [ INACTIVE1· 2

l,P~:::
~"
STATE
!,P

l,P~:::
9T0
STATE
1,P

"OR" ARRAY - (N), (F)

l,P~;:;
~n
STATE
DON'T CARE

"'±gfi' "'±gfi' "±gfi' n,I±gfi'

n;l

K

il,l

K

n;l

K

n.i

I

ACTION TOGGLE1

I I CODE 0

I

ACTION SET

I I CODE H

I

ACTION RESET

I I CODE L

I I I ACTION NO CHANGE

CODE
-

"COMPLEMENT" ARRAY - (C)

Gl: Gl: Gl: Gl:

Tn

I ACTION
~ I j INACTIVE" 3

CODE 0

I ACTION GENERATE

Tn
I I CODE A

I [ ACTION
L j PROPAGATE

To
· J CODE J

I [

ACTION

L l TRANSPARENT

Tn
J CODE -J

NOTES: 1. This is the initial unprogrammed state of all link pairs 2. Any gate T0 will be unconditionally inhibited if both the true and complement fuses of any input (l,P) are left intact. 3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates T0 .

October 22, 1993

383

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x48x8)

Product specification
PLUS105-55

PLUS105 PROGRAM TABLE

CUSTOMER NAME~~~~~~~~~~~

PURCHASE ORDER#~~~~~~~~~~

PHILIPS DEVICE #

CF (XXXX)

CUSTOMER SYMBOLIZED PART#~~~~~~

TOTALNUMBEROFPARTS~~~~~~~~

PROGRAM TABLE ~~~~~~~~~~~~~
REV~~~~~~~~~~~~~~~

DATE~~~~~~~~~~~~~~~~

PROGRAM TABLE ENTRIES
------~~----~----~~------i

INACTIVE

, o

GENERATE

A

PROPAGATE

·

TRANSPARENT' -

J
Cn I
I I

INACTIVE
";E~O<;QLE
RESET NO CHANGE

, o ' H
L -

Na, Fr

INACTIVE

o

1,P

, H

-~~N'T CARE ' :

L------------i

l i l_ ____~!!~-----i

1 .. Pa

1 ~=ESET

~ I PIE

AND

OPTION (PIE[

I

OR

TERM

Cn

15

14

13

1iLI1-

1o

0

1

2
__i

4

5

6

I

7

I

8

I

9

I

10

11

12

13

14

15

I

16

I

17

I

18

I

19

20

21

22

23

24

25

I

26

I

27

I

28

I

29

INPUT(lmJ
9 aJ) 6
I I I
2:
I I I
I I I I

30 31

32

33

34

35

I

I

36

I

I

37

I

I

38

I

I

39

40

41

42

43

44

I

45

I

I

46

I

I

47

I

I

PIN NO. 20 21 22 23 24 25 26 27 2 3

5 -tl3
I I I I
I I I I
I I I I
I I I I
I I I I
4 5 6

PRESENT STATE (Pa)
2 -,- 0 5 4- -3 2 1 0
7 8 9

REMARKS

NEXT STATE (Na)

- - - - - - - - - - -5 4 3 2 1 0

OUTPUT(Fr)
s 7 6 -4r3 2 1 0
I I I I
I I I I
I I I I
I I I I
I I I
10 11 12 13 15 16 17 18

w

...I
m

:wo

:a$: z<I:

~

NOTES:
1. The device is shipped with all links initially intact. Thus, a background of "0" for all Terms, and an "H" for the PIE option, exists in the table, shown BLANK instead for clarity.
2. Unused Cn, Im. and Ps bits are normally programmed Don't Care(-). 3. Unused Transition Terms can be left blank for future code modification, or programmed as(-) for maximum speed. 4. Letters in variable fields are used as identifiers by logic type programmers.

October 22, 1993

384

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 48 x 8)
SNAP RESOURCE SUMMARY DESIGNATIONS

Product specification
PLUS105-55

T47---------- r0

OUTPUT REG.

October 22, 1993

385

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 48 x 8)

Preliminary specification
PLUS105-70

DESCRIPTION
The PLUS 105-70 is a bipolar programmable state machine of the Mealy type. Both the AND and the OR array are userprogrammable. All 48 AND gates are connected to the 16 external dedicated inputs (10 - 115) and to the feedback paths of the 6 buried State Registers (Op0-0p5). Because the OR array is programmable, any one or all of the 48 transition terms can be connected to any or all of the State and Output Registers.
All state transition terms can include True, False and Don't Care states of the controlling state variables. A Complement Transition Array supports complex IF-THEN-ELSE state transitions with a single product term.
The PLUS105-70 device features edge-triggered, J-K flip-flops, which provide the added flexibility of the toggle function which is indeterminate on S-R flip-flops. Because the J-K function is a superset of the S-R flip-flop function, the PLUS105-70 is backward compatible with all 105-type devices that have S-R flip-flops. Asynchronous PreseVOutput Enable functions are available.
The PLUS105-70 is pin-for-pin and software compatible with Philips Semiconductors PLS 105 and PLS 105A Logic Sequencers, as well as other commercially available 105-type programmable logic devices.
To facilitate testing of state machine designs, diagnostic mode features for register preset and buried state register observability have been incorporated into the PLUS105-70 device architecture.
Ordering codes are listed in the Ordering Information Table.

FEATURES
· 70MHz operating frequency - 1OOMHz clock rate - No OR term loading restrictions
·Available in 300mil skinny DIP, 600mil-wide DIP, and PLCC packages
· Pin and software compatible with other commerically available 105 sequencers
· 16 input variables · 8 output functions · 48 transition terms · 6-bit State Register · 8-bit Output Register · Transition complement array · Positive edge-triggered clocked J-K (or
S-R) flip-flops · Security fuse · Programmable Asynchronous Preset or
Output Enable · Power-on preset to (all "1 "s) of internal
registers · Power dissipation: 800mW {typ.) · TTL compatible · Single +5V supply · 3-State outputs
APPLICATIONS
· Interface protocols · Sequence detectors · Peripheral controllers · Timing generators · Sequential circuits · Elevator controllers · Security Locking systems ·Counters · Shift registers

PIN CONFIGURATIONS
N Packages
N ... Plastic DIP (600mil-wide) N3 m Plastic DIP (300mil-wide)
A Package
FS F4 GND F3 F2 F1 FO A ... Plastic Leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION 28-pin Plastic Dual-In-Line, 600mil-wide 28-pin Plastic Dual-In-Line, 300mil-wide 28-pin Plastic Leaded Chip Carrier, 450mil-square

ORDER CODE PLUS105-70N PLUS105-70N3 PLUS105-70A

DRAWING NUMBER 0413B 0864D 0401F

November 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x48x8)
FUNCTIONAL DIAGRAM

Preliminary specification
PLUS105-70

T 4 7 - - - - - - - - - - To

PIN DESCRIPTION

PINNO.

SYMBOL

1

CLK

2-9. 26, 27 20-22

10-19, 113-115

23

112

24

111

25

110

10-13 1S-18

FO-F7

19

PR/OE

NAME AND FUNCTION
Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this line is necessary to update the contents of both state and output registers.
Logic Inputs: The 13 external inputs to the AND array used to program jump conditions between machine states, as determined by a given logic sequence. True and complement signals are generated via use of "H" and "L".
Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when exercising standard TTL levels. When 112 is held at + 1OV, device outputs FO - F5 reflect the contents of State Register bits PO - PS. The contents of each Output Register remains unaltered.
Logic/Diagnostic Input: A 15th external logic input to the AND array, as above. when exercising standard TTL levels. When 111 is held at +1OV, device outputs FO - F5 become direct inputs for State Register bits PO - PS; a Low-to-High transition on the clock line loads the values on pins FO - F5 into the State Register bits PO - PS. The contents of each Output Register remains unaltered.
Logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when exercising standard TTL levels. When 110 is held at +10V, device outputs FO- F7 become direct inputs for Output Register bits 00 - 07; a Low-to-High transition on the clock line loads the values on pins FO - F7 into the Output Register bits QO - 07. The contents of each State Register remains unaltered.
Logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight device outputs which normally reflect the contents of Output Register bits 00 - 07, when enabled. When 112 is held at +10V, FO- FS =(PO - PS). When 111 is held at +10V, FO- F5 become inputs to State Register bits PO - PS. When 110 is held at+ 10V, FO - F7 become inputs to Output Register bits00-07.
Preset or Output Enable Input: A user programmable function:
· Preset: Provides an asynchronous preset to logic "1" of all State and Output Register bits. PR overrides Clock, and when held High, clocking is inhibited and FO - F7 are High. Normal clocking resumes with the first full clock pulse following a High-to-Low clock transition, after the Preset signal goes Low. See timing definitions.
· Output Enable: Provides an output enable function to buffers FO - F7 from the Output Registers.

POLARITY ActiveHigh(H)
Active-High/ Low(H/L)
Active-High/ Low(H/L)
Active-High/ Low(H/L)
Active-High/ Low(H/L)
ActiveHigh(H)
ActiveHigh(H)
ActiveLow(L)

November 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 48 x 8)

Preliminary specification
PLUS105-70

TRUTH TABLE1, 2, 3, 4, 5, 6

OPTION

Vee

PR
H

OE

.110

.111

.112

CK
x

J
x

K

Qp

QF

F

x

H

H

OF

L

+10V

x

x

i

x

x

Op

L

L

I'

L

+10V

x

x

t

x

x

Op

H

H

L

x

+10V

x

i

x

x

L

OF

L

L

x

+10V

x

i

x

x

H

OF

H

L

x

x

+10V

x

x

x

Op

OF

Op

L

H

x x

x x

. x

x

x

x x

x

Op

OF

OF

x

Op

OF

Hi-Z

+5V

x

+10V

x

x

i

x

x

Op

L

L

x

+10V

x

x

t

x

x

Op

H

H

x

x

+10V

x

i

x

x

L

OF

L

x

x

+10V

x

i

x

x

H

OF

H

L

x

x

+10V

x

x

x

Op

OF

Op

L

x

x

x

x

x

x

Op

OF

OF

L

x x

x

i

L

L

Op

OF

OF

L

x

x

x

i

L

H

L

L

L

L

x

x

x

i

H

L

H

H

H

L

x

x

x

i

H

H

op

OF

OF

i

x

x

x

x

x

x

x

x

H

H

NOTES: 1. Positive Logic:

J-K (or SIR)= T0 +T1 +T2 + ... T4a Tn =(Co) (10, 11, 12, ... ) (P0, P1, ... P5)
2. Either Preset (Active-High) or Output Enable (Active-Low) are available, but not both. The desired function is a user-programmable option.
i 3. denotes transition from Low-to-High level.
4. *=HorLor+10V
5. X = Don't Care (~ 5.5V)
6. When using the Fn pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-Stated and the indicated levels on the output pins are forced by the user.

VIRGIN STATE
A factory-shipped virgin device contains all fusible links intact, such that: 1. PR/OE option is set to PR. Note that
even if the PR function is not used, all registers are preset to "1" by the power-up procedure.
2. All transition terms are disabled (0).
3. All J-K flip-flop inputs are disabled (0).

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 48 x 8)
LOGIC DIAGRAM
112 113 114 115

Preliminary specification
PLUS105-70

47· ···· ·40 39· ···· ·32 31· ···· ·24 23· ···· ·16
NOTES: 1. All AND gate inputs with a blown link float to a logic "1 ". 2. All OR gate inputs with a blown fuse float to logic "O". 3. ........ Programmable connection.

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)

Preliminary specification
PLUS105-70

COMPLEMENT ARRAY DETAIL
P.47 P46 P.45 · · · ·
co
co ~-~~~vT~~~~)
TOOR ARRAY

The complement array is a special sequencer feature that is often used for detecting illegal states. It is also ideal for generating IF-THEN-ELSE logic statements with a minimum number of product terms.
The concept is deceptively simple. If you subscribe to the theory that the expressions (/A· /B · /C) and(~ are equivalent, you will begin to see the value of this single term NOR array.
The complement array is a single OR gate with inputs from the AND array. The output of the complement array is inverted and fedback to the AND array (NOR function). The output of the array will be LOW if any one or more of the AND terms connected to it are active (HIGH). If, however, all the connected terms are inactive (LOW), which is a classic unknown state, the output of the complement array will be HIGH.

Consider the product terms A, B and D that represent defined states. They are also connected to the input of the complement array. When the condition (not A and not B and not D) exists, the Complement Array will detect this and propagate an Active-High signal to the AND array. This signal can be connected to product term E, which could be used in turn to preset the state machine to a known state. Without the complement array, one would have to generate product terms for all unknown or illegal states. With very complex state machines, this approach can be prohibitive, both in terms of time and wasted resources.
Note that use of the Complement Array adds an additional delay path through the device. Refer to the AC Electrical Characteristics for details.

THERMAL RATINGS
TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction

150°C 75°C 75°C

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

PARAMETER

RATINGS

UNIT

MIN

MAX

Vee

Supply voltage

+7.0

Voe

V1N

Input voltage

+5.5

Voe

VouT

Output voltage

+5.5

Voe

l1N

Input currents

-30

+30

mA

louT Tarnb Tstg

Output currents Operating temperature range Storage temperature range

+100

mA

0

+75

oc

-65

+150

oc

NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

LOGIC FUNCTION

PRESENT STATE JI' ·II" C " " NEXT STATE

SETQo:Jo:(02. a, ·Oo) ·JI'· B· c ... Ko=O

RESETQ1:J1 :0 K1=<Os.02.

a,.

Oo)

·Jl'·B·

c

...

HOLD Q2: J2 = 0 K2 :0
RESET<l3:J3 = (03 · 02 · 01 · Qo) ·JI'· B · C .. .
Ks=<Os ·02 · a 1 ·OtJ) ·Jl'·B· c .. .

November 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)

Preliminary specification
PLUS105-70

DC ELECTRICAL CHARACTERISTICS 0°C s Tamb s 75°C, 4.75V S Vee s 5.25V

SYMBOL

PARAMETER

TEST CONDITIONS

Input voltage2

V1H

High

V1L

Low

Vic

Clamp3

Output voltage2

Vee= MAX Vee= MIN Vee= MIN, l1N =-12mA

VoH

High

VoL

Low

Input current

Vee= MIN loH =-2mA loL =9.6mA

l1H

High

l1L

Low

Output current

Vcc=MAX V1N =Vee V1N = 0.45V

lo( OFF)

Hi-Z state

los

Short circuit3· 4

Ice

Vcc supply current5

Capacitance

Vcc=MAX VouT = 2.7V VouT = 0.45V VouT =av Vcc=MAX

Vee= 5.0V

C1N

lnRut

V1N = 2.0V

CouT

Output

VouT = 2.0V

NOTES:
1. All typical values are at Vee = 5V, Tamb = +25°C.
2. All voltage values are with respect to network ground terminal. 3. Test one at a time.
4. Duration of short circuit should not exceed 1 second. 5. Ice is measured with the PR/OE input grounded, all other inputs at 4.5V and the outputs open.

LIMITS MIN TYP1 MAX

2.0

0.8

--0.8

-1.2

2.4

0.35

0.45

<1

30

-20

-250

1

40

-1

--40

-15

-70

160

200

8 10

UNIT
v v v
v v
µA µA
µA µA mA mA
pF pF

November 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)

Preliminary specification
PLUS105-70

AC ELECTRICAL CHARACTERISTICS
R1 =470Q, R2 = 11<.Q, CL= 30pF, 0°C :s; TambS +75°C, 4.75Vs Vee :S:5.25V

SYMBOL

PARAMETER

Pulse Width

!cKH

Clock High

!cKL

Clock Low

!cKP

Clock Period

lpRH

Preset pulse

Setup Time

l1s1

Input

l1s2

Input (through Complement Array)

!vs

Power-on preset

tPRS INVeK Hold Time

Clock resume (after preset) Clock lockout (before preset)

t1H

Input

Diagnostic Mode

IAJS

Initialization of diagnostic mode

tRJH

Clock for diagnostic mode

Propagation Delay2

!cKO

Clock

loE

Output enable3

loo

Output disable3

Ip A

Preset

!pp A

Power-on preset

Frequency of Operation

FROM

TO

CK+ CKCK+ PR+

CKCK+ CK+ PR-

Input± Input± Vee+ PRCK-

CK+ CK+ CKCKPR-

CK+

Input±

110, 111or112 + (to10V)
CK+

Fn as inputs Register input jam

CK+ OEOE+ PR+ Vee+

Output± OutputOutput+ Output+ Output+

LIMITS

MIN

TYP1

l MAX

UNIT

5

ns

5

ns

10

ns

10

ns

8

ns

15

ns

0

ns

0

ns

10

ns

0

ns

50

ns

50

ns

6

ns

6.5

ns

6.5

ns

12

ns

10

ns

fMAX1 fMAX2 fMAX3

Without Complement Array

C1s1 : leKo)

Input±

With Complement Array

C1s2 : teKo )

Internal feedback

without Complement

Array

(ieKL : !cKH )

Input thru Complement
Array±
Register Output±

Output± Output± Register Input±

71.4 47.6 100.0

MHz MHz MHz

fMAX4

Internal feedback with Complement Array (il:2)

Register Output thru Complement
Array±

Register Input±

66.7

MHz

feLK

Clock period

CK+

CK+

100.0

MHz

NOTES:
1. All typical values are at Vee = 5V, Tarro = +25°C. 2. All propagation delays and setup times are meausred and specified under worst case conditions. 3. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT= (VoH - 0.5V) with S1open, and Low-to-High impedance tests are made to the VT= <VoL + 0.5V) level with S 1closed.

November 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x48x8}

Preliminary specification
PLUS105-70

TIMING DIAGRAMS

I0-115

CLK FO-F7

OE

10-115

1.5V

CLK

FO-F7

1.sv

toe Sequential Mode

+3V
ov
+3V 1.5V
ov
VOH
VOL +3V
ov

+3V
1.5V
'-----ov

----' "-_.,--------J 1.SV

1.5V

~----- VOL

PR

1.SV

Asynchronous Preset ~------------------- +SV
4.SV
Vee

FO-F7

CLK ____.:.·:l

rl+-tcK

ov

-----tvs----+i

November 1993

Power-On Preset 393

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)

Preliminary specification
PLUS105-70

TIMING DIAGRAMS (Continued)

Y= +10V a.ov +3V

110

r-----....._-, ,. ,. ,. ,. ,. , . ,. ., . FO - F7 lr':r"7"'7",..,,...,'7"'lr"7"'7",..,,...,7\.

ov
IRJH +3V

~NPUTS) "'-'-"'~"'-''""""-'-"'~"'-''""'JI "------.--.1 """""'"""'""""'"""'J.I OV

+3V CLK

QO -07)
( OUTPUT REG.

Diagnostic Mode-Output Register Input Jam

+10V

8.0V

+3V

111

.

ov

FO-F5

lf!JH ~'7"'lr"7"'7",..,..,- +3V

(INPUTS) "-'""""""""'"""'......'-"'"""""'-""""'....... U I ' - - - - - - . . - - - '

+3V CLK

(

PO-PS)
STATE

REG.

-·is

Diagnostic Mode-State Register Input Jam

10-111,

+3V

113-115

1.SV

ov

+10V
+3V 112
ov

+3V
CLK
ov

~~i::~~--

VoH

oo-os--

VOL

FO-FS

(Fn>

November 1993

ov
Diagnostic Mode-State Register Outputs
394

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 48 x 8)

Preliminary specification
PLUS105-70

TIMING DEFINITIONS

SYMBOL

PARAMETER

t1H

Required delay between

positive transition of Clock and

end of valid Input data.

t1s1

Required delay between

beginning of valid input and

positive transition of Clock.

t1s2

Required delay between

beginning of valid Input and

positive transition of Clock,

when using optional

Complement Array (two

passes necessary through the

AND Array).

lcKH

Width of input clock pulse

lcKL

Interval between clock pulses.

lcKO Delay between positive transition of Clock and when. Outputs become valid (with PR/OE Low).

lcKP

Minimum guaranteed clock

period.

INvcK

Required delay between the negative transition of the clock and the negative transition of the Asynchronous PRESET to guarantee that the clock edge is not detected as a valid negative transition.

TEST LOAD CIRCUITS

SYMBOL

PARAMETER

loo

Delay between beginning of

Output Enable High and when

Outputs are in the OFF-state.

loE

Delay between beginning of

Output Enable Low and when

Outputs become valid.

tppR

Delay between Vee (alter

power-on) and when Outputs

become preset at "1".

tpR

Delay between positive

transition of Preset and when

Outputs become valid at "1 ".

tPRH

Width of preset input pulse.

tPRS

Required delay between

negative transition of

Asynchronous Preset and the

first positive transition of

Clock.

tRH

Required delay between

positive transition of clock and

the end of valid input data

(FO - F7 as inputs), when

jamming data into the State or

Output registers in the

Diagnostic Mode.

L > Vee

lo

Fo

INPUTS
NOTE:
C1 and~ are to bypass Vee to GNO.

DUT

115

F7

CK

p

GND

'::"

SYMBOL

PARAMETER

tRJH

Required delay between

positive transition of clock and

return of input 110, 111 or 112

from Diagnostic Mode (10V).

IRJs

Required delay between

inputs 110, 111 or 112 transition

to Diagnostic Mode (10V), and

when the output pins become

available as inputs.

ls RD

Delay between input (112)

transition to Logic mode and

when the Outputs reflect the

contents of the Output

Register.

ls RE

Delay between input 112

transition to Diagnostic Mode

and when the Outputs reflect

the contents of the State

Register.

tvs

Required delay between Vee

(alter power-on) and negative

transition of Clock preceding

first reliable clock pulse.

fcLK

Minimum guaranteed clock

frequency (register toggle

frequency)

IMAX

Minimum guaranteed

operating frequency.

VOLTAGE WAVEFORMS

~.OY~

,/c L ~0% .FJ j OY

'R

:_~

2.Sns

2.Sns

MEASUREMENTS:
All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specHied.

Input Pulses

LOGIC PROGRAMMING
PLUS105-70 is fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips Semiconductors' SNAP design software package. ABEL'", CUPLTM and PALASM® 90 design software packages also support the PLUS105-70 architecture.

All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PLUS105-70 logic designs can also be generated using the program table entry format, which is detailed on the following

ABEL Is a trademark of Data l/O Corp. CUPL is a trademark of Logical Devices, Inc.
PALASM is a registered trademark of AMO Corp.

November 1993

395

pages. This program table entry format is supported by SNAP.
To implement the desired logic functions, the state of each logic variable from logic equations (I, B, 0, P, etc,) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 48 x 8)

:Preliminary specification
PLUS105-70

PRESET/OE OPTION · (PIE)

P~· ·

PRmE

.. .

(ALEW:A1YS

'='

ENABLED)

1·

OPTION PRESET1

OPTION OE

PROGRAMMING THE PLUS105-70:

The PLUS105-70 has a power-up preset feature. This feature insures that the device will

power-up in a known state with all register elements (State and Output Register) at logic High

(H). When programming the device it is important to realize this is the initial state of the

i ~p i~p il,p device. You must provide a next state jump if you do not wish to use all Highs (H) as the
present state. "AND" ARRAY - (I), (P)

l,P

.

1,P

1,P

l,ji

~ji

l,ji

~p i~p tii

I STATE

Tn

Tn STATE
l,P

Tn STATE
1,p

I STATE

Tn

"OR" ARRAY · (N), (F)

··±ro· "fW· "±ro· ··±ro· ii;1

K

ii;1

K

ii;1

K

ii;1

K

I ACTION TOGGLE1

I I CODE 0

I ACTION SET

I I CODE H

I ACTION RESET

I I CODE L

I I - I ACTION NO CHANGE

CODE

"COMPLEMENT" ARRAY · (C)

Gl: Gl: Gl: Gl:

I .ACTION INACTIVE1·3

Tn
I I CODE 0

I ACTION GENERATE

Tn
I I CODE A

I ACTION PROPAGATE

Tn
I I CODE '!

Tn

I I - I ACTION TRANSPARENT

CODE

NOTES:
1. This is the initial unprogrammed state of all link pairs 2. Any gate Tnwill be unconditionally inhibited if both the true and complement fuses of any input (l,P) are left intact. 3. To prevent oscillations, this state is not allowed for C link pairs i:oupled to a91ive gates Tn·

November 1993

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Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x48x8)

Preliminary specification
PLUS105-70

PLUS105 PROGRAM TABLE

PROGRAM TABLE ENTRIES

CUSTOMER NAME_ _ _ _ _ _ _ _ _ _~ PURCHASE ORDER#_ _ _ _ _ _ _ _ _ __ PHILIPS DEVICE #_ _ _ _ _C_F_,_(X_X_X_X,_)- - - CUSTOMER SYMBOLIZED PART#_ _ _ _ _ __ TOTAL NUMBER OF PARTS_ _ _ _ _ _ _ __ PROGRAM TABLE_ _ _ _ _ _ _ _ _ _ __
REV ~~~~~~~~~~~~~~~~~~-
DATE~--------------~
AND

-------AN-D----1T -----OR-------

INACTIVE

' 0

I INACTIVE

' 0

GENERATE

A

I C,,

-'f:rOGGLE , H

PROPAGATE

·

I RESET

' L

No, Fr

TRANSPARENT' -

I

NO CHANGE

-

INACTIVE

o

1,P

, H

~N'T CARE ' .'.:.

L------------

l_ _ _ _ _~!!~-----

I I I,,. Po

:ESET

I ! ~ PIE

J_ OPTION~

J_

OR

INPUT(lm)

a::r1 TERM Cn 15 14 13 1fil1- 1o i

6

0

1

2

3

4

5

6 7 8 9

' ' ' '

' ' ' '

10

11

12

13

14

15

16 17 18

' ' '

' ' I

19

20

21

22

23

24

25 26 27 28

' ' ' '

I
' ' '

29

30

31

32

33

34

35 36 37 38

' ' ' '

' ' ' '

39

40

41

42

43

44

45 46

' I

I I

47
PIN NO.

'

'

20 21 22 23 24 25 26 27 2 3

5 -tl.3
' ' ' '
' ' I
I
' ' '
' ' ' '
I
' '
4 5 6

PRESENT STATE (P0 )
2 -{ -0 5 4 3 2 1 0
78 9

- REMARKS

NEXT STATE (No)

OUTPUT(Fr)

-----------5 4 3

2 ;

0 -7- 6 ii -4T3

2

1

-
0

' ' ' '
I
' ' '
' ' ' '
' I
' I
' ' ' '
10 11 12 13 15 16 17 18

w ...J w
saa:l <:z;;
~

NOTES:
1. The device is shipped with all links initially intact. Thus, a background of "O" for all Terms, and an "H" for the PIE option, exists in the table, shown BLANK instead for clarity.
2. Unused Cn, Im, and P8 bits are normally programmed Don't Care{-).
3. Unused Transition Terms can be left blank for future code modification, or programmed as{-) for maximum speed. 4. Letters in variable fields are used as identifiers by logic type programmers.

November 1993

397

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer {16x48x8)
SNAP RESOURCE SUMMARY DESIGNATIONS

Preliminary specification
PLUS105-70

T 4 1 - - - - - - - - - - To

OUTPUT REG.

November 1993

398

Phillps Semiconductors Programmable Logic Devices
Programmable logic sequencers (16 x 64 x 8)

Product specification
PLUS405-37 /-45

DESCRIPTION
The PLUS405 devices are bipolar, programmable state machines of the Mealy type. Both the AND and the OR array are user-programmable. All 64 AND gates are connected to the 16 external dedicated inputs (I0-115) and to the feedback paths of the 8 on-chip State Registers (Qi.o- Op7). Two complement arrays suppon complex IF-THEN-ELSE state transitions with a single product term (input variables CO, C1).
All state transition terms can include True, False and Don't Care states of the controlling state variables. All AND gates are merged into the programmable OR array to issue the next-state and next-output commands to their respective registers. Because the OR array is programmable, any one or all ol the 64 transition terms can be connected to any or all of the State and Output Registers.
All state (QPO - Op7) and output (OFo - OF7) registers are edge-triggered, clocked J-K flip-flops, with Asynchronous Preset and Reset options. The PLUS405 architecture provides the added flexibility of the J-K toggle function which is indeterminate on S-R flip-flops. Each register may be individually programmed such that a specific Preset-Reset pattern is initialized when the initialization pin is raised to a logic level ·1 ·. This feature allows the state machine to be asynchronously initialized to known i·ntemal state and output conditions, prior to proceeding through a sequence of state transitions. Upon power-up, all registers are unconditionally preset to ·1·. If desired, the initialization input pin (INIT) can be convened to an Output Enable (OE) function as an additional user-programmable feature.
Availability of two user-programmable clocks allows the user to design two independently clocked state machine functions consisting of four state and four output bits each.
Order codes are listed in the Ordering Information Table.

FEATURES
· PLUS405-37 - IMAX = 37MHz - 50MHz clock rate
· PLUS405-45 - IMAX = 45MHz - 58.8MHz clock rate
· Functional superset of PLS105/105A · Field-programmable (Ti-W fusible link) · 16 input variables · 8 output functions · 64 transition terms · 8-bit State Register · 8-bit Output Register · 2 transition Complement Arrays · Multiple clocks* · Programmable Asynchronous Initialization
or OUtput Enable · Power-on preset of all registers to ·1 · · 'On-chip" diagnostic test mode features for
access to slate and output registers · 950mW power dissipation (typ.) · TTL compatible · J-K or S-R flip-flop functions · Automatic "Hold" states · 3-State outputs
APPLICATIONS
· Interface protocols · Sequence detectors · Peripheral controllers · Timing generators · Sequential circuits · Elevator contollers · Security locking systems ·Counters · Shift registers

PIN CONFIGURATIONS
NPackage
N - Plastic DIP (BOOmll-wide)
A Package
A - Plastic Leaded Chip carrier

ORDERING INFORMATION
DESCRIPTION
28-Pin Plastic DIP (600mil-wide) 28-Pin Plastic DIP (600mil-wide) 28-Pin Plastic Leaded Chip Carrier 28-Pin Plastic Leaded Chip Carrier

OPERATING FREQUENCY
45MHz (list + lcK01) 37MHz (~s1 + lcKci1) 45MHz (t1s1 + tcK01) 37MHz (t1s1 + tcK01)

ORDER CODE
PLUS405-45N PLUS405--37N PLUS405-45A PLUS405--37A

DRAWING NUMBER
04138 04138 0401F 0401F

·Refer to AC Specrlcatians for clock and operating frequencies when using rnuhiple clocks.

October 22. 1993

399

853-1280 11164

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(16 x 64 x 8)

Product specification
PLUS405-37/-45

PIN DESCRIPTION

PINNO. SYMBOL

1

CLK1

2, 3, 5-9, 26-27 20-22
4

10-14, 17, 16 18-19
113-115
CLK2

23

112

24

111

25

110

10-13 15-18

FO-F7

19

INITiOE

NAME AND FUNCTION
Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this line is neoessary to update the contents of both state and output registers. Pin 1 only clocks P0-3 and F0-3 if Pin 4 is also being used as a clock.

POLARITY Active-High (H)

Logic Inputs: The 12 external inputs to the AND array used to program jump conditions between machine states, as determined by a given logic sequence. True and complement signals are generated via use of "H" and 'L".

Active-High/Low (H/L)

Logic Input/Clock: A user programmable function:

· Logic Input: A 13th external logic input to the AND array, as above.

Active-High/Low (H/L)

·Clock: A 2nd clock for the State Registers P4-7 and Output Registers F4-7, as above.
Note that input buffer 15 must be deleted from the AND array (i.e., all fuse locations 'Don't Care") when using Pin 4 as a Clock.

Active-High (H)

Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when exercising standard TTL or CMOS levels. When 112 is held at+ 10V, device outputs FO-F7 reflect the contents of State Register bits PO-P7. The contents of each Output Register remains unaltered.

Active-High/Low (H/L)

Logic/Diagnostic Input: A 15th external logic input to the AND array, as above, when exercising standard TTL levels. When 111 is held at +1OV, devioe outputs FO-F7 become direct inputs for State Register bits PO-P7; a Low-to-High transition on the appropriate clock line loads the values on pins FO-F7 into the State Register bits PO-P7. The contents of each Output Register remains unaltered.

Active-High/Low (H/L)

Logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when exercising standard TTL levels. When 110 is held at+ 10V, device outputs FO-F7 become direct inputs for Output Register bits 00-07; a Low-to-High transition on the appropriate
clock line loads the values on pins FO-F7 into the Output Register bits 00-07. The contents of each State Register remains unaltered.

Active-High/Low (H/L)

Logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight devioe outputs which
normally reflect the contents of Output Register Bits 00-07, when enabled. When 112 is
held at+ 10V, FO-F7 = (PO-P7). When 111 is held at +10V, FO-F7 become inputs to State
Register bits PO-P7. When 110 is held at +10V, FO-F7 become inputs to Output Register
bitsQ0-07.

Active-High (H)

Initialization or Output Enable Input: A user programmable function:

·Initialization: Provides an asynchronous preset to logic "1" or reset to logic "O" of all State and Output Register bits, determined individually for each register bit through user programming. INIT overrides Clock, and when held High, clocking is inhibited and FO-F7 and PO-P7 are in their initialization state. Normal clocking resumes with the first full clock pulse following a High-to-Low clock transition, alter INIT goes Low. See timing definition for tNVCK and tvcK.

Active-High (H)

· Output Enable: Provides an output enable function to buffers FO-F7 from the Output Registers.

Active-Low (L)

October 22, 1993

400

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(16 x 64 x 8)

Product specification
PLUS405-37/-45

TRUTH TABLE 1, 2, 3, 4, s, s, 7

OPTION

Vee

INIT

OE

H

.110

.111

.112

CK
x

J
x

K

Qp

QF

F

x

H/L

H/L

OF

L

+10V

x

x

i

x

x

Op

L

L

L

+10V

x

x

i

x

x

Op

H

H

L

x

+10V

x

i

x

x

L

OF

L

L

x

+10V

x

i

x

x

H

OF

H

L

x

x

+10V

x

x

x

Op

OF

Op

L

H

x x

x x

x .

x x

x x

x

Op

OF

OF

x

Op

OF

Hi-Z

+5V

x

+10V

x

x

i

x

x

Op

L

L

x

+10V

x

x

i

x

x

Op

H

H

x

x

+10V

x

i

x

x

L

OF

L

x

x

+10V

x

i

x

x

H

OF

H

L

x

x

+10V

x

x

x

Op

OF

Op

L

x

x

x

x

x

x

Op

OF

OF

L

x

x

x

i

L

x

x

x

i

L

L

Op

OF

OF

L

H

L

L

L

L

x

x

x

i

H

L

H

H

H

L

x

x

x

i

H

H op a.= a.=

i

x

x

x

x

x

x

x

x

H

H

NOTES:
1. Positive Logic:
S/R(orJ/K) =To+ T1 + T2+ ... Ts3 Tn =(CO, C1) (10, 11, 12, ...) (PO, P1, ... P7)
2. Either Initialization (Active-High) or Output EM6l9 (Active-Low) are available, but not both. The desired function is a user-programmable option.
3. i denotes transition from Low-to-High level.
4. · =Hor Lor+1OV 5. X = Don't Care {,;5.5V) 6. H/L implies that either a High or a Low can occur, depending upon user-programmed selection (each State and Output Register individually
programmable).
7. When using the Fn pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-Stated and the indicated levels on the output pins are forced by the user.

VIRGIN STATE
A factory-shipped virgin device contains all fusible links intact, such that: 1. INIT/OE is set to INIT. In order to use the
INIT function, the user must select either the PRESET or the RESET option for each flip-flop. Note that regardless of the user-programmed initialization, or even if the INIT function is not used, all registers are preset to "1" by the power-up procedure.
2. All transition terms are inactive (0).
3. All SIR (or J/K) flip-flop inputs are disabled (0).
4. The device can be clocked via a Test Array preprogrammed with a standard test pattern.
5. Clock 2 is inactive.

LOGIC FUNCTION

J: ~R 03 02 01 00
I1 I0 I1 I

PRESENT STATE

STATE REGISTER

JI · B" · C · ...

JO JD ID t1 J Sn+l NEXTSTATE

SETOo:Jo= (~. 01. Ou»){. B". c ... Ko=·
RESET01:J1 :0
Kp(Qa · 02· 01 ·Ou» JI ·B"· C. ··
HOLD 02: J2 =O K2:0
RESET Qa:J3 =(Qa · ~ · 01 · Ool ·JI ·B"· C. ·· Ka= (Da · 02 · 01 · Ool ·JI· B" · C. ··

October 22, 1993

401

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(16 x 64 x 8)

FUNCTIONAL DIAGRAM

PS3

PO

Product specification
PLUS405-37/-45
l/CLK

October 22, 1993

Q (4)
R
Q (4) K
p R

(4)

K

O·l--t---t

P R

(4) K p
402

INIT/OE

Philips Semiconductors Programmable logic Devices
Programmable logic sequencers {16 x 64 x 8)
LOGIC DIAGRAM

Product specification
PLUS405-37/-45

'

'

1 '

~ ______ _l~T~ ~

NOTE: Denotes a programmable fuse location.
October 22, 1993

·' -0E;i.1i:ii ·

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(16 x 64 x 8)

Product specification
PLUS405-37/-45

DETAILS FOR REGISTERS FOR PLUS405
r- - - - - - - - - - - - - - - - - - - - - - - - - - - - · - - - - ....
I

r----------------------------------. TOINITUNE I

STATE REGISTERS

TO AND ARRAY

Q Pa

CLK

Detail A
, ...................................................................................... ...

'

TOINIT LINE

1

OUTPUT REGISTERS

QI-----+--<

p

,.

CLK

I

Detail B
,--------------------------------- ..I.
FROM PIN 1 CLK

,__ -.. ----- ------- - -- -- ---- ----- ____ . Detail C

COMPLEMENT ARRAY DETAIL

P63 P62 · · · P2 P1 PD

Detail D

C1
co

TOOR ARRAY

The Complement Array is a special sequencer feature that is often used for detecting illegal states. It is also ideal for generating IF-THEN-ELSE logic statements with a minimum number of product tenms.
The concept is deceptively simple. If you subscribe to the theory that the expressions (IA · /B · /C) and (A+lr+C} are equivalent, you will begin to see the value of this single term NOR array.
The Complement Array is a single OR gate with inputs from the AND array. The output of the Complement Array is inverted and fed back to the AND array (NOR). The output of the array will be Low if any one or more of the

AND terms connected to it are active (High).
If, however, all the connected terms are inactive (Low). which is a classic unknown state, the output of the Complement Array will be High.
Consider the Product Terms A, B and D that represent defined states. They are also connected to the input of the Complement Array. When the condition (not A and not 8 and not D) exists, the Complement Array will detect this and propagate an Active-High signal to the AND array. This signal can be connected to Product Term E, which could be used in turn to reset the state machine to a known state. Without the Complement Array, one would have to generate product terms for

all unknown or illegal states. With very complex state machines, this approach can be prohibitive, both in terms of time and wasted resources.
Note that the PLUS405 has 2 Complement Arrays which allow the user to design 2 independent Complement functions. This is particularly useful if 2 independent state machines have been implemented on one device.
Note that use of the Complement Array adds an additional delay path through the device. Please refer to the AC Electrical Characteristics for details.

October 22, 1993

404

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (16x64x8)

Product specification
PLUS405-37/-45

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

PARAMETER

RATINGS

UNIT

Vee

Supply voltage

+7

Voe

V1N

Input voltage

+5.5

Voe

Vour

Output voltage

+5.5

Voe

l1N

Input currents

-30to+30

mA

lour Tarrb

Output currents Operating temperature range

+100

mA

Oto +75

oc

Tsstg

Storage temperature range

--65 to +150

oc

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS

TEMPERATURE

Maximum junction

150°C

Maximum ambient

75°C

Allowable thermal rise ambient to junction

75°C

DC ELECTRICAL CHARACTERISTICS
0°C !>Tarrb !> +75°C, 4.75V !>Vee s5.25V

SYMBOL PARAMETER

Input voltage2

VrH

High

VrL

Low

Vrc

Clamp3

Output voltage2

VoH

High

Vol

Low

Input current

l1H

High

l1L

Low

Output current

TEST CONDITIONS

MIN

Vee= MAX

2.0

Vce=MIN

Vee= MIN, l1N = -12mA

Vee= MIN, loH =-2mA

2.4

Vee =MIN, loL = 9.6mA

Vee= MAX, V1N =Vee Vee= MAX, V1N = 0.45V

lo(OFF)

Hi-Z state

Vee= MAX, Vour = 2.7V

Vee= MAX, Vour = 0.45V

las

Short circuit 3·4

Vour=OV

-15

Ice

Vee supply current5

Capacitance

Vee= MAX

C1N

Input

Vee= 5.0V, V1N = 2.0V

Gour

Output

Vee= 5.0V, Vour = 2.0V

NOTES:
1. All typical values are at Vee= 5V. Tarrb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Duration of short-circuit should not exceed one second. 5. Ice is measured with the INIT/OE input grounded, all other inputs at 4.5V and the outputs open.

LIMITS TYP1

MAX

-0.8
'"'

0.8 -1.2

0.35

0.45

<1

30

-20

--250

1

40

-1

-40

-,70

190

225

8 10

UNIT
v v v
v v
µA µA
µA µA
mA
mA
pF pF

October 22, 1993

405

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (16x64x8)

Product specification
PLUS405-37/-45

AC ELECTRICAL CHARACTERISTICS R1 =4700, R2 = 1k!l, CL= 30pF, 0°C s Tamb S+75°C, 4.75V s Vee S5.25V

SYMBOL

PARAMETER

FROM

TO

Pulse width

lcKH1

Clock High; CLK1 (Pin 1)

lcKL1

Clock Low; CLK1 (Pin 1)

lcKP1

CLK1 Period

lcKH2

Clock High; CLK2 (Pin 4)

lcKL2

Clock Low; CLK2 (Pin 4)

lcKP2

CLK2 Period

t1NITH

Initialization pulse

Setup time

·1s1

Input

Input

l1s2

(through Complement Array)

·vs

Power-on preset

Clock resume

tveK

(alter Initialization)

tNVCK

Clock lockout (before Initialization)

Hold time

t1H

Input

Propagation delay

lcK01

Clock1 (Pin 1)

lcK02
loE2 loo2

Clock2 (Pin 4) Output Enable Output Disable

l1NIT

Initialization

lppR

Power-on Preset

Notes on following page

CK+ CKCK+ CK+ CKCK+ INIT-

CKCK+ CK+ CKCK+ CK+ INIT+

Input± Input± Vee+ INIT-
CK-

CK+ CK+ CKCK-
INIT-

CK+

Input±

CK1+ CK2+ OEOE+ INIT+ Vee+

Output± Output± OutputOutput+ Output+ Output+

LIMITS

PLUS405-37

PLUS405·45

MIN TYP1 MAX MIN TYP1 MAX

10

8

10

8

20

16

10

8

10

8

20

16

15

10

8.5

7

8.5

7

17

14

10

8

10

8

20

16

15

8

15

12

25

20

0

-10

0

-5

15

5

12

10

22

18

0

-10

0

-5

15

5

0

-5

0

-5

10

12

12

15

12

15

12

15

15

20

0

10

8

10

10

12

12

15

12

15

15

20

0

10

UNIT
ns ns ns ns ns ns ns
ns ns ns ns
ns
ns
ns ns ns ns ns ns

October 22, 1993

406

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(16 x 64 x 8)

Product specification
PLUS405-37/-45

AC ELECTRICAL CHARACTERISTICS (Continued}
R1 = 470!1, R2 = 1k.Q, Cl= 30pF, 0°C S Tamb s +75°C, 4.75V s Vee s 5.25V

SYMBOL

PARAMETER

FROM

TO

Frequency of operation

CLK1; without Complement Array

fMAX1

1 ( t1s1 + 1cK01)

fMAX2

CLK2; without Complement Array 1
( t1s1 + tcK02)

fMAX3

CLK1; with Complement Array 1
( t1s2 + tcK01 )

fMAX4

CLK2; with Complement Array 1
( t1s2 + tcK02 )

Input±

Output±

Input±

Output±

Input thru Complement
Array±

Output±

Input thru Complement
Array±

Output±

LIMITS

PLUS405-37

PLUS405·45

MIN TYP1 MAX MIN TYP1 MAX

37.0 45.5

45.5 55.6

33.0 41.7

41.7 50.0

27.0 33.3

31.3 38.5

25.0 31.3

29.4 35.7

UNIT
MHz MHz MHz MHz

Internal feedback without

Complement Array (CLK1 or CLK2)

fMAX5

( lcKl~hH)

Register Output±

Register lntput±

50.0 62.5

58.8 72.4

MHz

fMAX6

Internal feedback with Complement Array (CLK1 or CLK2)
(t,:J

Register Outputthru Complement
Array±

Register lntput±

40.0 50.0

45.5 55.6

MHz

Minimum guaranteed clock

feLK

frequency

CK+

CK+

50.0 62.5

58.8 72.4

MHZ

NOTES:
1. All typical values are at Vee= 5V, Tamb = +25°C. 2. For 3-State output; output enable times are tested with Cl= 30pF to the 1.5V level, and S 1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output voltage of VT= (VoH -0.5V) with S 1open, and Low-to-High impedance tests are made to the VT= (Vol+ 0.5V) level with S 1closed. 3. All propagation delays and setup times are measured and specified under worst case conditions.

TEST LOAD CIRCUIT

Vee L___/

R1

10

Rl

cl
INPUTS~-~~ 115 OUT
F7 OUTPUTS

CK

INITIOE

GND

=

NOTE:

C1 and C2 are to bypass Vee to GND.

=

VOLTAGE WAVEFORMS

~.ov~

L ov _j 'R .FJ ~0%

·:_Jt ·fL- 2.Sns

2.Sna

2.Sns

2.Sna

MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.

Input Pulses

October 22, 1993

407

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (16x64x8)

Product specification
PLUS405-37/-45

TIMING DIAGRAMS

+3V I0-115
ov

+3V

I'

CLK

1.5V

ov

FO-F7

VoH VoL +3V

ov
'<>E
Sequential Mode

I0-115

1.5V

CLK FO-F7

1.SV

1.5V
tcKH'~_....,,___tcKL

1.SV

' - - - - - ov

INIT
October 22, 1993

1.SV 'NITH
Asynchronous Initialization

r·CKO 1.sv

+5V
Vee
ov

FO-F7

1.SV

1.5 VoL

+3V

e I y;;;- CLK

1.sv-j-

1.5V

------'l--tcK

ov

~----tvs----..i

10~115 _ _ _ _ _ _ _ _ _ _1_.s

lMAX

+3V ov

'S =::!:='H=.j '---

Power-On Preset

408

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (16 x 64 x 8)

Product specification
PLUS405-37/-45

TIMING DIAGRAMS (Continued)

I0-111,--..,,.-------------------------- +3V

113-115

1.SV

112 CLK
Rl-F7

+3V - - - - - - - - - - - - - VoH

Diagnostic Mode - State Register Outputs
aov +1.0V +3V
111
o.v
IRJH
...,..,..,_,...,..,_...,..,..,_,...,..,.....,.1.------...._-. 17".,...,...,...,,...,...,."7+3V
Rl-F7
(INPUTS) "'-''-.L.L..<...<;...L..L.J.:..L.L..<...<;...L.." I ' - - - - - - . - - - ' ~....."""................. ov
+3V CLK

Diagnostic Mode - Stale Register Input Jam
Y= +10V aov +3V

110
ov

Rl-

F7

,..,..,..,...,..,..,,...,.,..,,...,..,...,...,'"7"\.

IRJH ~-----'--"""'\J n'7',..,'7',..,~

+3V

ONPUTS) ._.'"""._. . ,. ._, _.'""""._. . ,. ._._, ~-----...,..-J .~ . . . . . . . . . . . . . ov

+3V CLK

October 22. 1993

Diagnostic Mode- Output Register Input Jam

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(16 x 64 x 8)

Produ.ct specification
PLUS405-37 /-45

TIMING DEFINITIONS

SYMBOL fcKH1,2 fcKP1,2

PARAMETER
Width of input clock pulse.
Minimum guaranteed clock period.

t1s1

Required delay between

beginning of valid input and

positive transition of Clock.

fcK01, 2

Delay between positive transition of Clock and when Outputs become valid (with INIT/OE Low).

tppR

Delay between Vee (after

power-on) and when Outputs

become preset at "1 ".

t1s2

Required delay between

beginning of valid Input and

positive transition of Clock,

when using optional

Complement Array (two

passes necessary through

the AND Array).

tRJH

Required delay between

positive transition of clock,

and return of input 110, 111 or

112 from Diagnostic Mode

(10V).

fMAX1,2

Minimum guaranteed operating frequency; input to output (CLK1 and CLK2).

fMAX3,4

Minimum guaranteed operating frequency; input through Complement Array, to output (CLK1 and CLK2).

fMAX5

Minimum guaranteed internal operating frequency; with internal feedback from state register to state register.

SYMBOL fMAX6

PARAMETER
Minimum guaranteed internal operating frequency with Complement Array, with internal feedback from state register through Complement Array, to state register.

fcLK

Minimum guaranteed clock

frequency (register toggle

frequency).

fcKL1, 2 Interval between clock pulses.

t1H

Required delay between

positive transition of Clock

and end of valid Input data.

toE

Delay between beginning of

Output Enable Low and when

Outputs become valid.

ts RE

Delay between input 112

transition to Diagnostic Mode

and when the Outputs reflect

the contents of the State

Register.

tRJS

Required delay between

inputs 111, 110or112

transition to Diagnostic Mode

(10V), and when the output

pins become available as

inputs.

tNVCK

Required delay between the negative transition of the clock and the negative transition of the Asynchronous Initialization to guarantee that the clock edge is not detected as a valid negative 'transition.

SYMBOL

PARAMETER

ltNITH

Width of initialization input pulse.

tvs

Required delay between Vee

(after power-on) and

negative transition of Clock

preceding first reliable clock

pulse.

loo

Delay between beginning of

Output Enable High and

when Outputs are in the

OFF-5tate.

t1NIT

Delay between positive

transition of Initialization and

when Outputs become valid.

lsRD

Delay between input 112

transition to Logic mode and

when the Outputs reflect the

contents of the Output

Register.

tRH

Required delay between

positive transition of Clock

and end of valid Input data

when jamming data into State

or Output Registers in

diagnostic mode.

tvcK

Required delay between

negative transition of

Asynchronous Initialization

and negative transition of

Clock preceding first reliable

clock pulse.

410

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (16 x 64 x 8)

Product specification
PLUS405-37/-45

LOGIC PROGRAMMING
The PLUS405-37/-45 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software packages. ABEL'" and CUPLTM design software packages also support the PLUS405-37/-45 architecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PLUS405-37/-45 logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only.
To implement the desired logic functions, each logic variable (I, B, P, S, T, etc.) from the logic equations is assigned a symbol. TRUE, COMPLEMENT, PRESET, RESET, OUTPUT ENABLE, INACTIVE, etc., symbols are defined below.

INITIALIZATION/OE OPTION - (INIT/'OE)
INIT/OE

INIT.uE

INIT

= INIT 0

E=I

(INITIAUZA

E

_

(ALWAYS

DISABLED)

':'

-

ENABLED)

[

I J OPTION

CODE

I [ INITIAUZATION1

H J

OPTION OE

CODE L

PROGRAMMING THE PLUS405: The PLUS405 has a power-up preset feature. This feature insures that the device will
power-up in a known state with all register elements (State and Output Register) at logic High
(H). When programming the device it is important to realize this is the initial state of the
device. You must provide a next state jump if you do not wish to use all Highs (H) as the
present state.

INITIALIZATION OPTION - (INIT)

ACTION

CODE

i l,pINDETERMINATE4

0

"AND" ARRAY - (I), (P)

l,P
r,p

Tn
I STATE

Notes are on next page.

ACTION

CODE

ii,pPRESET

H

l,P
r,p

Tn
STATE l,P

ii,pRESET
l,P
r,p
Tn STATE
1, p

ii,pINDETERMINATE4
l,P
r,p
Tn STATE DON'T CARE

ABEL is a trademark of Data 110 Corp. CUPL is a trademark of Logical Devices, Inc.
October 22, 1993

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (16 x 64 x 8)

Product specification
PLUS405-371~45

"OR" ARRAY - J·K FUNCTION ""(N), (F)

"±g[J- "±g[J- "'±g[J- ··jg{}

I,
I

R;"F

K

R;"F

K

R;"F

K

R;"F

K

I I I ACTION TOGGLE1,6

CODE 0

I ACTION SET

I I cODE H

I

ACTION RESET

I I CODE L

I I - I ACTION NO CHANGE

CODE

"COMPLEMENT" ARRAY - (C)

Gj:

Tn

I I I ACTION INACTIVE1· 3

CODE 0

Gj:

I ACTION GENERATE

Tn
I I CODE A

Gj:

Tn

I I · I ACTION PROPAGATE

CODE

Gj:

Tn

I I - I ACTION TRANSPARENT

CODE

CLOCK OPTION - (CLK1/CLK2)

CLK2

CLK2

PROGRAMMING/SOFTWARE SUPPORT Refer to Section g (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional
information.

CLK1

OPTION CLK1 ONLY1

CODE L

CLK1
I OPTION CLK1 and CLK25

CODE H

NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate T0 will be unconditionally inhibited if any one of its I or Plink pairs is left intact. 3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn· 4. These states are not allowed when using INITIALIZATION option. 5. Input buffer 15 must be deleted from the AND array (i.e., all fuse locations "Don't Care") when using second clock option. 6. A single product term cannot drive more than 8 registers by itself when used in TOGGLE mode.

412

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers
(16 x 64 x 8)

Product specification
PLUS405-37/-45

PLUS405 PROGRAM TABLE

-_:i--I__ I t-_- - - - - - - - -~_Q _ - -- - -- - - - - ~ - - - _ Q_~ - - -

INACTIVE

0

INACTIVE

0

I 'r~Jt.~E OR 10

Q_P_!l_Q~_ - - -

I INIT

I H INITIOE

l,P

TH Im, Ps

~~N'T CARE j_ L

.___ _ _ __l__,__-_.

GENERATE T : en
==~::~NT -

iI SET RESET

_J_ H
J_ L

_l_ NO CHANGE J_ -

Ns, Fr

iI - OE LCLK1 ONLY
J_ CLK1 AND 2

IL -

J j_

L H

j

CLK11 CLK2

~--------~~--_[~~c=LOC=K~1=12~~I---<
AND

~~

INPUT (Im)

PRESENT STATE (Ps)

@ llillJ!· 11311Wll 110 19 1[[11 16 15 14 [ID 12 11 10 P7 P6 PS P4IP3 P2 el: Po

INITIAUZATIONI &

CE

l

J_ _[ J_ ]_ _[

R

NEXT STATE (Ns)

OUTPUT(Fr)

~

~

:f

J:

I

w
t:

J:

J:

0

w

_J

CD

~

~

21 22

<(

a:

<9

a>w:

0a:
Cl.

28

29

31 32 33

35

J_
I
I l
I
1 I
:r

J:
39 40

J xxx

ct ~
u.

b:

()

J_

I

0 w

so
51

I

!:::! 52
_J

I

~
z<(
wa:

'*!:
w
()
> w
0

0
CD
>:::::-?
(/)
aw :

54 55
57 58
61

I

:::::?
~
(/)

(/)
Cl.
::J

:::::?
~
(/)

62
PINNO. ~~~h.1~~~23456789

::::> :I ::::>

() CL ()

PIN

LABELS

I

I
f-+-+-+-+-t-1-+-l-+-+-l-+--t--- -+
>-+-+--+-c:r--+---+-+-i--+---1--+-tI.' - - t---i"---t-+~-+--+--+-~--t-t---<--t-- - -1 -

1

±

I I

I I
I
1 1 1 1 1 1 1 1 01_zj35678

NOTES: 1. The device Is shi~ed with all links initially intact. Thus, a background of "O" for all Terms, and an "H" for the IN/E and H for the clock option. exists in the table, shown BLANK instead
for clarity. 2. Unused Cn rm. and Ps bits are normally programmed Don't Care{-).
3. Unused Transition Terms can be left blank for future code modification, or programmed as(-) for maximum speed.

October 22, 1993

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencers (16 x 64x 8)

SNAP RESOURCE SUMMARY DESIGNATIONS

P63

PO

~15 ~ ,:::,.o..1: ..·.;·'-··- ···- ···-···.··-·-··:·-·,·-··-·+~ ·1-.;=-.:-

Product specification
PLUS405-37/-45
l/CLK
11

(4)
K p R

,,~~$.

4
':' (4)

4
INITl!lE
414

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x64x8)

Product specification
PLUS405-55

DESCRIPTION
The PLUS405-55 device is a bipolar, programmable state machine of the Mealy type. Both the AND and the OR array are user-programmable. All 64 AND gates are connected to the 16 external dedicated inputs (10 -115) and to the feedback paths of the 8 on-chip State Registers (Opo - Op7). Two complement arrays support complex IF-THEN-ELSE state transitions with a single product term (input variables C0, C1).
All state transition terms can include True, False and Don't Care states of the controlling state variables. All AND gates are merged into the programmable OR array to issue the next-state and next-output commands to their respective registers. Because the OR array is programmable, any one or all of the 64 transition terms can be connected to any or all of the State and Output Registers.
All state (Op0 - Op7) and output (QFo - OF1) registers are edge-triggered, clocked J-K flip-flops, with Asynchronous Preset and Reset options. The PLUS405 architecture provides the added flexibility of the J-K toggle function which is indeterminate on S-R flip-flops. Each register may be individually programmed such that a specific Preset-Reset pattern is initialized when the initialization pin is raised to a logic level "1''. This feature allows the state machine to be asynchronously initialized to known internal state and output conditions prior to proceeding through a sequence of state transitions. Upon power-up, all registers are unconditionally preset to '1 ". If desired, the initialization input pin (INIT) can be converted to an Output Enable (OE) function as an additional user-programmable feature.
Availability of two user-programmable clocks allows the user to design two independently clocked state machine functions consisting of four state and four output bits each.
Order codes are listed in the Ordering Information Table below.

FEATURES
· 66. ?MHz minimum guaranteed clock rate · 55MHz minimum guaranteed operating
frequency ( 1/(tis1 + tcK01) · Functional superset of PLS 105/1 OSA · Field-programmable (Ti-W fusible link) · 16 input variables · 8 output functions · 64 transition terms · 8-bit State Register · 8-bit Output Register · 2 transition Complement Arrays · Multiple clocks · Programmable Asynchronous Initialization
or Output Enable · Power-on preset of all registers to "1" · "On-chip" diagnostic test mode features for
access to state and output registers · 950mW power dissipation (typ.) · TTL compatible · J-K or S-R flip-flop functions · Automatic "Hold" states · 3-State outputs
APPLICATIONS
· Interface protocols · Sequence detectors · Peripheral controllers · Timing generators · Sequential circuits · Elevator contollers · Security locking systems ·Counters · Shift registers

PIN CONFIGURATIONS
N Package

N = Plastic DIP (600mil-wide)
A Package
15/CLK 16 17 CLK Vee 18 2

F7

F5

F2 F1 FO

A"' Plastic Leaded Chip Carrier

110
111 112 113 114 115 INIT/OE

ORDERING INFORMATION
DESCRIPTION 28-Pin Plastic Dual In-Line (600mil-wide) 28-Pin Plastic Leaded Chip Carrier

OPERATING FREQUENCY
55MHz (tis + tcKo)
55MHz (tis + tcKo)

ORDER CODE PLUS405-55N PLUS405-55A

DRAWING NUMBER 04138 0401F

October 22, 1993

Philips SemicoricluctOrs Programmable Logic Devices
Programmable logic sequencer
(16 x 64 x 8)

Product sl>eci!ication
PLUS405-55

PIN DESCRIPTION

PINNO. SYMBOL

NAME AND FUNCTION

POLARITY

1

CLK1

Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this Active-High (H)

line is nl!C9ssary to update the contents of both state and output registers. Pin .1 only

clocks P0-3 and F0-3 if Pin .4 is also being used as a clock.

2,3.~. 10-14, 17, 16 logic Inputs: The 12 external inputs to the AND array used to program jump conditions Active-High/Low

i'

26-27

18-19

between machine states, as detennined by a given logic sequence. True and complement

(H/L)

20-22

113-115 signals are generated via use of "H" and "L'.

4

CLK2

Logic Input/Clock: A user programmable function:

·Logic Input: A 13th external logic input to the AND array, as.above.

Active-High/Low (H/L)

· Clock: A 2nd clock for the State Registers P4-7 and Output Registers F4-7, as above.
Note that input buffer 15 must be deleted from the AND array (i.e., all fuse locations "Don't Carej when using Pin 4 as a Clock.

Active-High (H)

23

112

Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when

Active-High/Low

exercising standard TTL or CMOS levels. When 112 is held at+10V, device outputs FO-F7

(H/L)

reflect the contents of State Register bits PO-P7. The contents of each Output Register

remains unaltered.

24

111

Logic/Diagnostic Input: A 15th external logic input to the AND array, as above, when

Active-High/Low

exercising standard TTL levels. When 111 is held at +10V, device outputs FO-F7 become

(H/L)

direct inputs for State Register bits PO-P7; a Low-to-High transition on the appropriate

clock line loads the values on pins FO-F7 into the State Register bits PO-P7. The contents

of each Output Register remains unaltered.

25

110

Logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when

Active-High/Low

exercising standard TTL levels. When 110 is held at +10V, device outputs FO-F7 become

(H/L)

direct inputs for Output Register bits QO-Q7; a Low-to-High transition on the appropriate

clock line loads the values on pins FO-F7 into the Output Register bits 00--07. The

contents of each State Register remains unaltered.

10-13 15-18

FO-F7

Logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight device outputs which
nonnally reflect the contents of Output Register Bits 00--07, when enabled. When 112 is
= held at+10V, FO-F7 (PO-P7). When 111 is heldat+tOV, FO-F7become inputs to State
Register bits PO-P7. When 110 is held at +1OV, FO-F7 become inputs to Output Register bits00--07.

Active-High (H)

19

INIT/OE Initialization or Output Enable Input: A user programmable function:

· Initialization: Provides an asynchronous preset to logic "1" or reset to logic ·o· of all
State and Output Register bits, detennined individually for each register bit through user programming. INIT overrides Clock, and when held High, clocking is inhibited and FO-F7 and PO-P7 are in their initialization state. Nonnal clocking resumes with the first full clock pulse following a High-to-Low clock transition, alter INIT goes Low. See timing definition for
INVCK and lvCK·

Active-High (H)

· Output Enable: Provides an output enable function to buffers FO-F7 from the Output Registers.

Active-Low (L)

n-............ ,,,, 10Qo:t

416

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 64 x 8)

Product specification
PLUS405-55

TRUTH TABLE 1, 2, 3, 4, 5, 6, 7

OPTION

Vee

INIT

OE

H

.110

.111

.112

CK
x

J
x

K

Qp

QF

F

x

H/L

H/L

OF

L

+10V

x

x

i

x

x

Op

L

L

L

+10V

x

x

i

x

x

Op

H

H

L

x

+10V

x

i

x

x

L

OF

L

L

x

+10V

x

i

x

x

H

OF

H

L

x

x

+10V

x

x

x

Op

OF

Op

L

H

x x

x x

x .

x x

x x

x

Op

OF

OF

x

Op

OF

Hi-Z

+SV

x

+10V

x

x

i

x

x

Op

L

L

x

+10V

x

x

i

x

x

Op

H

H

x

x

+10V

x

i

x

x

L

OF

L

x

x

+10V

x

i

x

x

H

OF

H

L

x

x

+10V

x

x

x

Op

OF

Op

L

x

x

x

x

x

x

Op

OF

OF

L

x

x

x

i

L

x

x

x

i

L

x

x

x

i

L

x

x

x

i

L

L

Op

OF

OF

L

H

L

L

L

H

L

H

H

H

H

H

op

aj;;

aj;;

i

x

x

x

x

x

x

x

x

H

H

NOTES:
1. Positive Logic:
S/R(orJ/K)=To+ Ti+ T2+ ... Ts3 Tn =(CO, C1) (10, 11, 12, ...) (PO, P1, ... P7)
2. Either Initialization (Active-High) or Output Ena6re (Active-Low) are available, but not both. The desired function is a user-programmable
option.
3. t denotes transition from Low-to-High level.
4. ·=Hor Lor +10V 5. X = Don't Care (s5.5V)
6. H/L implies that either a High or a Low can occur, depending upon user-programmed selection (each State and Output Register individually programmable).
7. When using the Fn pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-Stated and the indicated levels on the output pins are forced by the user.

VIRGIN STATE
A factory-shipped virgin device contains all fusible links intact, such that: 1. INIT/OE is set to INIT. In order to use the
INIT function, the user must select either the PRESET or the RESET option for each flip-flop. Note that regardless of the user-programmed initialization, or even if the INIT function is not used, all registers are preset to "1" by the power-up procedure.
2. All transition terms are inactive (0).
3. All SIR (or J/K) flip-flop inputs are disabled (0).
4. The device can be clocked via a Test Array preprogrammed with a standard test pattern.
5. Clock 2 is inactive.

LOGIC FUNCTION

I· I I·J: I ~R 03 02 01 00 0

PRESENT STATE

STATE REGISTER

ll" B · C · ...

I I I I 0 0 0 t1 Sn+1 NEXTSTATE

SETOQ:Jo=<02·01 ·lloJ·X·B·C ...
Ko=O
RESET01:J1 =0 Kp(03·02· 01 ·Oo)"X·B· C ...
HOLD ~: J2 =fl
K2=0
RESETO:i:J3=(0:! · ~ · 01 ·Oo) · X ·B· C.. . 1<3=(0:! · 02· 01 ·Qo) "ll"B· c .. .

October 22, 1993

417

Philips Semiconductors Programmable logic Devices
Programmable logic sequencer (16 x 64 x 8)

FUNCTIONAL DIAGRAM

. P63

PO

Product specification
PLUS405-55

Q (4)

4 4

Q

':"

(4)

R 4 4

Q (4)
R 4 4

Q (4) K
p R
4

INIT/OE

418

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 64 x 8)
LOGIC DIAGRAM

Product specification
PLUS405-55

,D!f,!11!-~ · - - · - - ·

I

I

~------_lf!IT.!oi:!

NOTE: ~ Denotes a programmable fuse location.
January 2, 1992

'
·

0 DErAii:o

·

419

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x64x8)

Product specification
PLUS405-55

DETAILS FOR REGISTERS FOR PLUS405

STATE REGISTERS
Q Po

TOINITUNE TO AND ARRAY

K CU<

Detail A ,---------------------------------~
TOINITUNE OUTPUT REGISTERS
01------+---I p
K
CU<

FROMPIN4 {15/CLK)

Detail B

FROM PIN 1 CU<

Detail C COMPLEMENT ARRAY DETAIL

I
----------------------------------' Detail D
P63 P62 · · · P2 P1 PO

C1
co

TOOR ARRAY

The Complement Array is a special sequencer. feature that is often used for detecting illegal states. It is also ideal for generating IF-THEN-ELSE logic statements with a minimum number of product terms.
The concept is deceptively simple. If you subscribe to the theory that the expressions (/A · /B · /C) and (:A+l:f+C) are equivalent, you will begin to see the value of this single term NOR array.
The Complement Array is a single OR gate with inputs from the AND array. The output of the Complement Array is inverted and fed back to the AND array (NOR). The output of the array will be Low if any one or more of the

AND terms connected to it are active (High). If, however, all the connected terms are inactive (Low), which is a classic unknown state, the output of the Complement Array will be High.
Consider the Product Terms A, B and D that represent defined states. They are also connected to the input of the Complement Array. When the condition (not A and not B and not D) exists, the Complement Array will detect this and propagate an Active-High signal to the AND array. This signal can be connected to Product Term E, which could be used in turn to reset the state machine to a known state. Without the Complement Array, one would have to generate product terms for

all unknown or illegal states. With very complex state machines, this approach can be prohibitive, both in terms of time and wasted resources.
Note that the PLUS405 sequencers have 2 Complement Arrays which allow the user to design 2 independent Complement functions. This.is particularly useful if 2 independent state machines have been implemented on one device.
Note that use of the Complement Array adds an additional delay path through the device. Please refer to the AC Electrical Characteristics for details.

October 22, 1993

420

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16 x 64 x 8)

Product specification
PLUS405-55

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

PARAMETER

RATINGS

UNIT

Vee

Supply voltage

+7

Voe

VrN

Input voltage

+5.5

Voe

Vour

Output voltage

+5.5

Voe

lrN

Input currents

-30to+30

mA

lour

Output currents

Tarrti

Operating temperature range

+100

mA

0 to +75

oc

Ta1g

Storage temperature range

-65to +150

oc

NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS

TEMPERATURE

Maximum junction

1so0 c

Maximum ambient

75°C

Allowable thermal rise ambient to junction

75°C

DC ELECTRICAL CHARACTERISTICS 0°c s Tantis +75°C, 4.75V s Vee s 5.25V

SYMBOL PARAMETER

TEST CONDITIONS

MIN

Input voltageZ

VrH

High

Vcc=MAX

2.0

VrL

Low

Vee=MIN

Vrc

Clamp3

Vee= MIN, lrN = -12mA

Output vollageZ

VOH

High

Vee= MIN, loH = -2mA

2.4

VoL

Low

Vee = MIN, loL = 9.6mA

Input current

lrH

High

Vee= MAX, VrN =Vee

lrL

Low

Vee= MAX, VrN = 0.45V

Output current

IO(oFFJ

Hi-Z state

Vee= MAX, VouT = 2.7V

los

Short circuit 3, 4

Vee = MAX, VouT = 0.45V

Vour=OV

-15

Ice

Vee supply currents

Vcc=MAX

Capacitance

CrN

Input

Vee= 5.0V, VrN = 2.0V

Cour

Output

Vee= 5.0V, Vour = 2.0V

NOTES:

1. All typical values are at Vee= 5V. Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Duration of short-circuit should not exceed one second. 5. Ice is measured with the INIT/OE input grounded, all other inputs at 4.5V and the outputs open.

LIMITS TYP1
--0.8
0.35 <1 -20 1 -1 190 8 10

MAX
0.8 -1.2
0.45
30 -250
40 --40 -70 225

UNIT
v v v
v v
pA pA
pA pA mA mA
pF pF

October 22, 1993

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 64 x 8)

Product specification
PLUS405-55

AC ELECTRICAL CHARACTERISTICS R1 = 470Q, R2 = 1kQ, CL= 30pF, 0°C s: Tamb s: +75°C, 4.75V s: Vee s: 5.25V

SYMBOL

PARAMETER

Pulse width

lcKH1 lcKL1

Clock High; CLK1 (Pin 1) Clock Low; CLK1 (Pin 1)

lcKP1 lcKH2

CLK1 Period Clock High; CLK2 (Pin 4)

lcKL2 lcKP2

Clock Low; CLK2 (Pin 4) CLK2 Period

l1NITH

Initialization pulse

Setup time

t1s1

Input

Input

t1s2

(through Complement Array)

!vs tveK INVeK

Power-on preset
Clock resume (after Initialization)
Clock lockout (before Initialization)

Hold time

l1H

Input

Propagation delay

lcK01

Clock 1 (Pin 1)

lcK02
loE2 loo2

Clock2 (Pin 4) Output Enable Output Disable

l1NIT

Initialization

lppR

Power-on Preset

Notes on following page

FROM
CK+ CKCK+ CK+ CKCK+ INIT-
Input± Input± Vee+ INIT-
CK-
CK+
CK1+ CK2+ OEOE+ INIT+ Vee+

TO
CKCK+ CK+ CKCK+ CK+ INIT+
CK+ CK+ CKCK-
INIT-
Input±
Output± Output± OutputOutput+ Output+ Output+

LIMITS

MIN

TYP1 MAX

UNIT

7.5

6

ns

7.5

6

ns

15

12

ns

7.5

6

·ns

7.5

6

ns

15

12

ns

14

12

ns

10

9

ns

18

15

ns

0

-10

ns

0

-5

ns

12

5

ns

0

-5

ns

6.5

8

ns

7.0

8

ns

6.5

8

ns

6.5

8

ns

12

18

ns

0

10

ns

October 22. 1993

422

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x64x8)

Product specification
PLUS405-55

AC ELECTRICAL CHARACTERISTICS (Continued) Rl = 470Q, R2 = 1k.Q, CL= 30pF, 0°C s; Tarrn s; +75°C, 4.75V s; Vee s; 5.25V

SYMBOL

PARAMETER

Frequency of operation

CLK1; (without Complement Array)

fMAX1

1 ( t1s1 + tcK01)

FROM Input±

TO Output±

LIMITS

MIN

TYP1

MAX

UNIT

55.6

64.5

MHz

CLK2; (without Complement Array)

fMAX2

~eK02) ( t1s1 +

Input±

Output±

55.6

62.5

MHz

fMAX3

CLK1; (with Complement Array) 1
( t1s2+ teK01 )

Input through Complement
Array±

Output±

38.5

46.5

MHz

fMAX4

CLK2; (with Complement Array) 1
( t1s2 + teK02)

Input through Complement
Array±

Output±

38.5

45.5

MHz

fMAX5

Internal feedback without Complement Array (CLK1 or CLK2)
~ ( lcKL lcKH )

Register Output±

Register Input±

66.7

83.3

MHz

fMAX6

Internal feedback with Complement Array (CLK 1 or CLK2)
(il:2)

Register Output through Complement Array±

Register Input±

55.6

66.7

MHz

feLK

Minimum guaranteed Clock frequency

CK+

CK+

66.7

83.3

MHz

NOTES:

1. All typical values are at Vee = 5V, Tarrn = +25°C.
2. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S 1is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL= SpF. High-to-High impedance tests are made to an output
s voltage of VT= (VoH - 0.5V) with 1open, and Low-to-High impedance tests are made to the VT= (VoL + 0.5V) level with S1 closed.
3. All propagation delays and setup times are measured and specified under worst case conditions.

TEST LOAD CIRCUIT
INPUTS NOTE:
C1 and C2 are to bypass Vee to GND.

Vee L___.>

Rt

IO

FO

CL 115 OUT
F7 OUTPUTS

CK

INIT/OE

GND

=

=

VOLTAGE WAVEFORMS

~.ov~

L ov __J IR IFJ ~~

2.Sna

2.5ns

~-~\ ·fC

2.Sns

2.Sns

MEASUREMENTS: All circuit delays are measured at the + t .SV level of inputs and outputs, unless otherwise specified.

Input Pulses

October 22, 1993

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer {16x64x8)

Product specification
PLUS405-55

TIMING DIAGRAMS

I0-115

CU< FO-F7

10-115

1.5V

toe
Sequential Mode

+3V
ov
+3V 1.5V
ov
Voo
Vot +3V
ov

CLK FO-F7
INIT

1.5V 1.5V

tcKH

1.5V ICKL

1.SV

-----ov

1.5V

1.5V

_ _ __, - - - - - - - - - - - . - - - - - - - VoL

~NIT

)--tcKO

1.5V

Vee
FO-F7 CLK

Asynchronous Initialization

1.SV

= [FnJ 1

1.5

____ .:.·5:.J-f

1.5V

'f.--tcK
-----tvs----...i

+5V

ov

[FnJ + 1

VoH Vol

+3V
ov

October 22. 1993

Power-On Preset 424

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x64x8)

Product specification
PLUS405-55

TIMING DIAGRAMS (Continued)
I 0 - 1 1 1 , - - . . , , . - - - - - - - - - - - - - - - - - - - - - - - - - - +3V 113-115

112
+3V CLK
- - - - - - - - - - - - - VoH

FO-F7

OE Diagnostic Mode - State Register Outputs

. +10V
aov

+3V

111
ov

r - - - - - - - " \ FO - F7 1'7'7':7";1"7''7"'.:"7'7':7";1"7'7";1~

IRJH ~,..,_,..~'"7'.,..,. +3V

·------r--- (INPUTS) ._.'-'..._.._...L."'-'-'"-'._....C...<J

·~----- OV

+3V CLK

Diagnostic Mode- State Register Input Jam

Y=8.0V

+10V +3V

110
ov

r - - - - - - - - " \ . FO _ F7 1"7''7"'.:"7'7':7";1"7''7"'.:"7"7":7";1~ I

IRJH J;"7"T.7'?"T.,..,. +3V

(INPUTS) ~""'-"'-'-'"-'._...L."'-'-'"-'::.l I '-------.---1 ,._......_~-..- OV

+3V CLK

October 22, 1993

Diagnostic Mode - Output Register Input Jam 42!'i

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x64x8)

Product specification
PLUS405-55

TIMING DEFINITIONS

SYMBOL

PARAMETER

lcKH1, 2 Width of input clock pulse.

lcKP1,2 Minimum guaranteed clock period.

t1s1

Required delay between

beginning of valid input and

positive transition of Clock.

lcK01, 2

Delay between positive transition of Clock and when Outputs become valid (with INITiOE Low).

lppR

Delay between Vee (after power-on) and when Outputs become preset at "1 ".

t1s2

Required delay between

beginning of valid Input and

positive transition of Clock,

when using optional

Complement Array (two

passes necessary through

the AND Array).

tRJH

Required delay between

positive transition of clock,

and return of input 11.0, 111 or

112 from Diagnostic Mode

(10V).

fMAX1,2

Minimum guaranteed operating frequency; input to output (CLK1 and CLK2).

fMAX3,4

Minimum guaranteed operating frequency; input through Complement Array, to output (CLK1 and CLK2).

IMAX5

Minimum guaranteed internal operating frequency; with internal feedback from state register to state register.

SYMBOL

PARAMETER

fMAX6

Minimum guaranteed internal operating frequency with Complement Array, with internal feedback from state register through Complement Array, to state register.

feLK

Minimum guaranteed clock

frequency (register toggle

frequency).

teKL1,2 Interval between clock pulses.

t1H

Required delay between

positive transition of Clock

and end of valid Input data.

toE

Delay between beginning of

Output Enable Low and when

Outputs become valid.

tsRE

Delay between input 112

transition to Diagnostic Mode

and when the Outputs reflect

the contents of the State

Register.

tRJS

Required delay between

inputs 111, 110 or 112

transition to Diagnostic Mode

(10V). and when the output

pins become available as

inputs.

tNveK

Required delay between the negative transition of the clock and the negative transition of the Asynchronous Initialization to guarantee that the clock edge is not detected as a valid negative transition.

SYMBOL

PARAMETER

~NITH

Width of initialization input pulse.

tvs

Required delay between Vee

(after power-on) and negative

transition of Clock preceding

first reliable clock pulse.

loo

Delay between beginning of

Output Enable High and

when Outputs are in the

OFF-state.

t1N1T

Delay between positive

transition of Initialization and

when Outputs become valid.

lsRD

Delay between input 112

transition to Logic mode and

when the Outputs reflect the

contents of the Output

Register.

tRH

Required delay between

positive transition of Clock

and end of valid Input data

when jamming data into State

or Output Registers in

diagnostic mode.

tveK

Required delay between

negative transition of

Asynchronous Initialization

and negative transition of

Clock preceding first reliable

clock pulse.

October 22, 1993

426

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer (16x64x8)

Product specification
PLUS405-55

LOGIC PROGRAMMING
The PLUS405-55 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL'" and CUPLTM design software packages also support the PLUS405-55 architecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PLUS405-55 logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only.
To implement the desired logic functions, each logic variable (I, B, P, S, T, etc.) from the logic equations is assigned a symbol. TRUE, COMPLEMENT, PRESET, RESET, OUTPUT ENABLE, INACTIVE, etc., symbols are defined below.

INITIALIZATION/OE OPTION - (INIT/OE)

L l OPTION
j [ INITIAUZATION1

J CODE
H

OPTION OE

CODE L

PROGRAMMING THE PLUS405: The PLUS405 has a power-up preset feature. This feature insures that the device will power-up
in a known state with all register elements (State and Output Register) at logic High (H). When
programming the device it is important to realize this is the initial state of the device. You must
provide a next state jump if you do not wish to use all Highs (H) as the present state.

INITIALIZATION OPTION - (INIT)

i i,pINDETERMINATE4

0

"AND" ARRAY - (I), (P)

l,P
r,p

Tn

[

STATE

[ INACTIVE1· 2

Notes are on next page.

ii,pPRESET

H

l,P
I.ii

Tn
STATE l,P

ACTION
ii,pRESET
1,P r,p
Tn STATE
1, p

ii,pINDETERMINATE4
l,P
r,p
Tn STATE DON'T CARE

ABEL is a trademark of Data 1/0 Corp. CUPL is a trademark of Logical Devices, Inc.
October 22, 1993

427

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 64 x 8)

Product specification
PLUS405-55

"OR" ARRAY - J·K FUNCTION - (N), (F)

"'±g[f "'±g[f "'±g[f "'±g[f

"f'1'

K

"f'1'

K

1'1'

K

"f'1'

K

I I I ACTION TOGGLE1·6

CODE 0

I

ACTION SET

I I CODE H

"COMPLEMENT" ARRAY - (C)

G;l:

Tn

ACTION

CODE

~ I JJ INACTIVE1· 3 _l_ 0

G;l:

I ACTION GENERATE

Tn
I I CODE A

CLOCK OPTION - (CLK1/CLK2)
CLK2

I

ACTION RESET

I I CODE L

I I - I ACTION NO CHANGE

CODE

G;l:

Tn

I [

ACTION

L l · J PROPAGATE

CODE ]

G;l:

Tn

[ ACTION
L Il J TRANSPARENT

CODE]
-

PROGRAMMING/SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information.

CLK1

CLK1

OPTION CLK1 ONLY1

CODE

OPTION CLK1 and CLK25

CODE H

NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate Tnwill be unconditionally inhibited if any one of its I or P link pairs is left intact. 3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn· 4. These states are not allowed when using INITIALIZATION option. 5. Input buffer 15 must be deleted from the AND array (i.e., all fuse locations "Don't Care") when using second clock option. 6. A single product tenTI cannot drive more than 8 registers by itself when used in TOGGLE mode.

October 22. 1993

428

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 64 x 8)

Product specification
PLUS405-55

PLUS405 PROGRAM TABLE
.--~~~~~~A-ND~~~~~~~~Tr-~~-O~R~~~~~~~~O~P~Tl~O~N~S~~~

I I I I ~- INA-CT- IVE---0-------- INA- CT- IVE---0---1I -~- ~J- L~- E O-R -I-0 ---1I-- INIT-----H-- INIT- /OE-

l I, p

l H Im, Po

GENERATE TA Cn I SET

H

I - OE

jL -

I, P

-L L

i - DON'T CARE

PROPAGATE -1. ·
TRANSPARENT_l -

lI RESET

J_ L

NO CHANGE -

l [ No, Fr

I [ CLK1 ONLY
CLK1 AND 2

JL CLK11
I HJ CLK2

~m:'v

AND INPUT (Im)

CLOCK 112 PRESENT STATE (Po)

INITIAUZATION I!'!!J

l Ll

lll

R

NEXT STATE (No)

OUTPUT (Fr)

__Q_ Ct.JCOI 11
±
+ i

14 113112Jlll]110 10 IJil]L i l l 14]Ji Jilli:[]!J P7 I
1

fi5leill'.!J P2 P PO ~

::t:

I

I

L!ill.m.~
i I
I

_J_
w ~
0

I l

I I I

w
c_oJ ~

::2'

<(
a:

23 24

0

25

I

>aw:

0a:
Cl.

27 28

l

J_

j 37 38

I

:r

~ x

I

~
LL 0

la-: ~

48 49

:r

w0 51

N

52

::J 53

w 'II: 0co

I

> ::2'
z<(

w
0

e>::n2-'

aw :

w
0

aw :

::2' 0
eI-n-
::J

en
Cl.
::J
I

::2'
~
::J

58 59 60

Li PIN NO.

~ ~~~~ ~~234 5678 9

I

0 Cl. 0

PIN

LABELS

I

I

I I

I

I

j_
I

I

I
I 11 111111 01235678

NOTES:
1. The device is shipped with all links initially intact. Thus, a background of "O" for all Terms, and an "H" for the IN/E and H for the clock option, exists in the table, shown BLANK instead for clarity.
2. Unused Cn Im, and Ps bits are normally programmed Don't Care (-). 3. Unused Transition Terms can be left blank for future code modification, or programmed as(-) for maximum speed.

October 22, 1993

429

Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 x 64 x 8)
SNAP RESOURCE SUMMARY DESIGNATIONS

Product specification
PLUS405-55
l/CLK

K p R
4
Q (4) K
p R
(4)

October 22. 1993

=
430

INITIOE

Programmable Logic Devices

Section 6
Low Volt Devices

CONTENTS

P3C 18V8z35/P3C 1BVBZI 3 Volt zero standby power universal PAL devices

433

LVT16V8-7

3 Volt BiCMOS Versatile GAL-type PLD ...... .

447

LVT22V10-7

3 Volt BiCMOS Versatile PAL ............ .

449

LVT20V8-7

3 Volt BiCMOS Versatile GAL-type PLO ...... .

451

Phillps Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices

Product specification
P3C18V8Z35/P3C18V8ZI

DESCRIPTION
The P3C18V8Z is a universal PAL-type device designed to operate specifically in a low voltage environment (3.3V). Per JEDEC, the P3C18V8Z can support a regulated operating supply voltage, 3.0 to 3.6V and an unregulated (battery) operating supply voltage, 2.7 to 3.6V, at 21 and 18 MHz, respectively. The PAL device is available in the commercial temperature range, P3C 18V8Z35, and the industrial temperature range, P3C18V8ZI.
These devices offer virtually zero standby power (20µA typical) as well as very low power consumption during operation (23mA worst case in combinatorial configuration). The P3C 18V8Z automatically powers down when the inputs or the clock are idle for greater than one full clock cycle. The device will automatically power up from a standby mode once any input or the clock is activated. This input transition detection circuitry makes these devices ideal for power sensitive applications - especially those which are battery operated or backed up.
All the P3C 18V8Z devices are available in plastic DIP, PLCC and Plastic Small Outline (SOL) packages. A ceramic DIP with a window for erasure is available for prototyping.
The P3C18V8Z is a two level logic element comprised of 10 inputs, 74 AND gates (logic and control product terms) and 8 Output Macro Cells (OMCs). Each OMC can be configured as a dedicated input, a combinatorial 1/0 or a registered output with internal feedback. Each OMC has individual direction control (from the AND array) and programmable output polarity. The dedicated clock and OE pins can be configured as inputs for strictly combinatorial applications. Two product terms control the asynchronous Reset and the synchronous Preset functions.

Power up Reset and Register Preload functions have also been incorporated into the P3C 18V8Z to facilitate state machine design and testing.
The Output Macro Cell feature of the P3C 18V8Z devices provides the flexibility to emulate all 20 pin common PAL and GAL functions, thus providing reduced documentation, inventory and manufacturing costs. The P3C18V8Z is also pin and fuse map compatible with all the Philips 5 Volt P3C18V8Z devices.
FEATURES
· 20-pin Universal Programmable Array Logic (PAL), operational over low voltage ranges - 3.0 to 3.6V (35ns Tpo/21 MHz IMAX) - 2.7 to3.6V (40ns Tp[)i18 MHz IMAX)
· Virtually zero-standby-power and very low dynamic power - 20µA standby (typ.) - 0.8 mA/MHz (worst case)
· Functional replacement for Series 16 PALs andGALs - Highly flexible Output Macro Cell
· Available in DIP, PLCC and SOL (Small Outline) packages
· High performance EPROM CMOS cell technology - 100% testable prior to programming - Low cost OTP plastic packages - Erasable/reconfigurable (ceramic package)
· Design support provided by most popular third party programmable Logic CAD tools
APPLICATIONS
· Laptop, notebook and palm top computers · Portable communications equipment · Battery power/backed instruments · Industrial automation/control

PIN CONFIGURATIONS
D, N, and FA Packages

N .. Plastic Dual In-Line Package (DIP) (300mil-wide) FA· Ceramic DIP with Quanz Window (300rril-wide) D ... Plastic Small Outline Large Package (300mit-wide)
A Package lo' CLKVcc F7

lg GND lg! Fo F, OE
A · Plastic Leaded Chi Carrier

PIN DESCRIPTIONS

I

Dedicated Input

F Output/Input Macrocell

CLK Clock Input
OE Output Enable

Vee Supply Voltage GND Ground

ORDERING INFORMATION
DESCRIPTION
20-Pin (300mil-wide) Plastic Dual In-Line Package 20-Pin (300mil-wide) Ceramic Dual In-Line Package with quartz window 20-Pin (350mil square) Plastic Leaded Chip Carrier Package 20-Pin (300mil-wide) Plastic Small Outline Large Package 20-Pin (300mil-wide) Plastic Dual In-Line Package 20-Pin (300mil-wide) Ceramic Dual In-Line Package with quartz window 20-Pin (350mil square) Plastic Leaded Chip Carrier Package 20-Pin (300mil-wide) Plastic Small Outline Large Package

TEMPERATURE RANGE
Commercial
Industrial

ORDER CODE

DRAWING NUMBER

P3C18V8Z35N 04088

P3C18V8Z35FA 05848

P3C18V8Z35A 0400E

P3C18V8Z35D 0172D

P3C18V8ZIN

04088

P3C18VBZIFA

05848

P3C18V8ZIA

0400E

P3C18V8ZID

0172D

September 1, 1993

433

853-1716 10f;QQ

Philips Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices
LOGIC DIAGRAM

Product specification
P3C18V8Z35/P3C18V8ZI

NOTES: In the unprogrammed or virgin state:
All cells are in a conductive state. All AND gate locations are pulled to a logic "O" (Low).
Output polarity is inverting.
September 1, 1993

Pins 1 and 11 are configured as Inputs 0 and 9, respectively, via the configuration cell. The clock and OE functions are disabled. All output macro cells (OMC) are oonfigured as bidirectional 110, with the outputs disabled via the direction term.
(j$ Denotes a programmable cell location.
434

Philips Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices

Product specification
P3C18V8Z35/P3C18V8ZI

PAL DEVICE TO P3C18V8Z OUTPUT PIN CONFIGURATION CROSS REFERENCE

PIN NO.

P3C 18V8Z

16L8 16H8
16P8 16P8

16R4 16R6 16R8 16RP4 16RP6 16RP8

16L2 16H2 16P2

14L4 14H4 14P4

12L6 12H6 12P6

1

lofCLK

I

CLK CLK CLK

I

I

I

19

F7

B

B

B

D

I

I

I

18

F6

B

B

D

D

I

I

0

17

F5

B

D

D

D

I

0

0

16

F4

B

D

D

D

0

0

0

15

F3

B

D

D

D

0

0

0

14

F2

B

D

D

D

I

0

0

13

F1

B

B

D

D

I

I

0

12

FO

B

B

B

D

I

I

I

11

I~

I

OE OE OE

I

I

I

10L8 10H8 10P8
I 0 0 0 0 0 0 0 0 I

FUNCTIONAL DIAGRAM

The Philips Semiconductors" state-of-the-art Floating-Gate CMOS EPROM process yields bipolar equivalent performance at less than one-quarter the power consumption. The erasable nature of the EPROM process enables Philips Semiconductors to functionally test the devices prior to shipment

to the customer. Additionally, this allows Philips Semiconductors to extensively stress test. as well as ensure the threshold voltage of each individual EPROM cell. 100% programming yield is subsequently guaranteed.

OUTPUT MACRO CELL (OMC)

r---------
1
I I
I I
I I
2~~ {::+:=-:1--~-"---·--

t FROM AND ARRAY TO ALL OMCs --;-------, ' ' l Vee
a. a:
"'""

I I II AC1 "~'.-~·-t::>o-~~~-T-~~:----+-~~ I AC2n :
I -=-

'
L---------r-~r''''
t ++
TO ALL OMCs

-----~J

NOTE: ~:;:: Denotes a programmable cell location.

THE OUTPUT MACRO CELL (OMC)
The P3C 1BVBZ series devices have 8 individually programmable Output Macro Cells. The 72 AND inputs (or product terms) from the programmable AND array are connected to the 8 OMCs in groups of 9. Eight of the AND terms are dedicated to logic functions; the ninth is for asynchronous direction control, which enables/disables the respective bidirectional 1/0 pin. Two product terms are dedicated for the Synchronous Preset and Asynchronous Reset functions.
Each OMC can be independently programmed via 16 architecture control bits. AC1n and AC2n (one pair per macro cell). Similarly, each OMC has a programmable output polarity control bit (Xn). By configuring the pair of architecture control bits according to the configuration cell table, 4 different
configurations may be implemented. Note that
the configuration cell is automatically programmed based on the OMC configuration.
DESIGN SECURITY
The P3C 1BVBZ series devices have a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved.

September 1, 1993

435

Philips Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices

Product specification
P3C18V8Z35/P3C18V8ZI

CONFIGURATION CELL
A single configuration cell controls the functions of Pins 1 and 11. Refer to Functional Diagram. When the configuration cell is programmed, Pin 1 is a dedicated clock and Pin 11 is dedicated for output enable. When the configuration cell is unprogrammed, Pins 1 and 11 are both dedicated inputs. Note that the output enable

for all registered OMCs is common-from Pin 11 only. Output enable control of the bidirectional 1/0 OMCs is provided from the AND array via the direction product term.
If any one OMC is configured as registered, the configuration cell will be automatically configured (via the design software) to ensure that the clock and output enable functions are

enabled on Pins 1 and 11, respectively. If none of the OMCs are registered, the configuration cell will be programmed such that Pins 1 and 11 are dedicated inputs. The programming codes are as follows:

Pin 1 = CLK, Pin 11 =OE'

L

Pin 1 and Pin 11 =Input

H

FUNCTION Registered mode

CONTROL CELL CONFIGURATIONS

AC11

AC2N

CONFIG. CELL

Programmed

Programmed

Programmed

Bidirectional 1/0 mode

Un programmed

Unprogrammed

Fixed input mode

Un programmed

Programmed

Fixed output mode

Programmed

Unprogrammed

NOTE: 4. This is the virgin state as shipped from the factory.

ARCHITECTURE CONTROL-AC1 and AC2

Unprogrammed Unprogrammed Un programmed

COMMENTS
Dedicated clock from Pin 1. OE' Control for all registerd OMCs from Pin 11 only.
Pins 1 and 11 are dedicated inputs. 3-State control from AND array only.
Pins 1 and 11 are dedicated inputs.
Pins 1 and 11 are dedicated inputs. The feedback path (via FMux) is disabled.

F(D). F (D)

F(B). F (B)

OMC CONFIGURATION
BIDIRECTIONAL 110 (COMBINATORIAL)

CODE B

OMC CONFIGURATION FIXED OUTPUT

CODE 0

~--------- F(I)

F(D),F(ll)

N SP U C L K O
A N OE

OMC CONFIGURATION FIXED INPUT

CODE

CONFIGURATION CELL
PIN 1 ·CLK PIN11=0E

CODE

CONFIGURATION CELL
PIN 1 =INPUT PIN 11 =INPUT

CODE
H1

NOTES: A factory shipped unprogrammed device is configured such that: 1. This configuration cannot be used if any OMCs are configured as registered (Code= D). The configuration cell will be automatically
configured to ensure that the clock and output enable functions are enabled on Pins 1 and 11, respectively, if any one OMC is programmed as registered. · All AND gates are pulled to a logic "O" (Low). · Output polarity is inverting. * Pins 1 and 11 are configured as inputs Oand 9. The clock and OE functions are disabled. · All Output Macro Cells (OMCs) are configured as bidirectional 1/0, with the outputs disabled via the direction term.

September 1, 1993

436

Philips Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices

Product specification
P3C18V8Z35/P3C18V8ZI

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

PARAMETER

RATINGS

UNIT

Vee Vee V1N Vour
!J.Vt.V

Supply voltage Operating supply voltage Input voltage Output voltage
lnpuVclock transition rise or fall2

-0.5 to +6 2.7to3.6 -0.5 to Vee +0.5 -0.5 to Vee +0.5
200

Voe
Voe Voe
Voe
nsN
maximum

i1N

Input currents

-10to+10

mA

lour

Output currents

+24

mA

Tamb Tstg

Operating temperature range Storage temperature range

-40 to +85 (Industrial)

oc

Oto +75 (Commercial)

-65 to +150

oc

NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. 2. All digital circuits can oscillate ortriggerprematurelywhen input rise and fall times are very long. When the input signal to a device is at or near the switching threshold, noise on the line will be amplified and can cause oscillation which, if the frequency is low enough, can cause subsequent stages to switch and give erroneous results. For this reason, external Schmitt-triggers are recommended if rise/fall times are likely to exceed 200ns at Vee= 3.SV.

THERMAL RATINGS TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal rise
ambient to junction

150°C 75°C 75°C

AC TEST CONDITIONS

L > Vee

R1

lo

By

CL
INPUTS o----<.. lg OUT Bw

NOTE: C1 and C2 are to bypass Vee to GND.

Bx GND Bz
-=

-= OUTPUTS
R1=200Q R2 = 390Q

VOLTAGE WAVEFORMS
M--:xl Jt;·,~.

l+- __j OV

5ns

'R IF

5ns

-~L90%

ov-=rns~

_jsns

MEASUREMENTS: Alt circuit delays are measured at the + 1.5V level of
inputs and outputs, unless otherwise specified.

Input Pulses

SWITCHING WAVEFORM

INPUT

OUTPUT Input to Output Disable/Enable

September 1, 1993

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Philips Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices

Product specification
P3C18V8Z35/P3C18V8ZI

DC ELECTRICAL CHARACTERISTICS
2.7VSVccS3.6and3.0V SVccS 3.6ranges
Commercial= 0°C s Tarro s +75°C
Industrial = -40°C s Tarro s +85°C

SYMBOL

PARAMETER

Input voltage

V1L

Low

V1H

High

Output voltage2

Vol

Low

VoH

High

Input current

l1L

Low5

l1H

High

Output current

lo(OFF)

Hi-Z state

los

Short-circuit3

Ice

Vee supply current (Standby)

lccff

Vee supply current (Active)4

Capacitance

C1

Input

Cs

1/0

TEST CONDITION
Vee=MIN Vee= MAX
Vee= MIN, loL = 20µA Vee= MIN, loL = 24mA Vee= 3.0, loH = -3.2mA Vee= 3.0, loH = -20µA Vee= 2.7, loH =-1.6µA
V1N =GND V1N =Vee
VouT= Vee VouT =GND VouT = GND Vee= MAX, V1N = 0 or Vcc6 Vee= MAX
Vee= 5V V1N = 2.0V Vs= 2.0V

LIMITS

MIN

TYP1

MAX

-0.3 2.0

0.8 Vee +0.3

Vee-0.6 Vec-0.3 Vee-0.3

0.100 0.500

UNIT
v v
v v v v

-5

µA

5

µA

10

µA

-10

µA

-130

mA

20

60

µA

0.8

mA/MHz

12

pF

15

pF

100µA

12

18

!(MHz)

24 30

Figure 1. Ice vs Frequency (Worst Case)

NOTES:
1. All typical values are at Vee = 3.3V, Tarro= +25°C. 2. All voltage values are with respect to network ground terminal. 3. Duration of short-drcuit should not exceed one second. Test one at a time. 4. Measured with all outputs swtiehing. 5. 11L for Pin 1 (lofCLK) is± 1OµA with V1N = 0.4V. 6. V1N includes CLK and OE if applicable.

September 1, 1993

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Philips Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices

Product specification
P3C18V8Z35/P3C18V8ZI

AC ELECTRICAL CHARACTERISTICS 3.0V s Vee s 3.6V range; R2 = 390Q Commercial= 0°C s Tarro s +75°C Industrial = -40°C s Tarm s +85°C

SYMBOL Pulse width

PARAMETER

FROM

TO

lcKP

Clock period (Minimum tis + lcKo)

lcKH

Clock width High

lcKL

Clock width Low

IARW

Async reset pulse width

Hold time

CLK+ CLK+ CLK1±,F±

CLK + CLKCLK+ I+, F +

l1H

Input or feedback data hold time

Setup time

CLK +

Input±

tis

Input or feedback data setup time

Propagation delay

I±, F±

CLK+

tpo

Delay from input to active output

I±, F±

F±

Clock High to output valid access

lcKO

nme

CLK +

F±

loE1

Product term enable to outputs off

I±, F±

F±

loo1

Product term disable to outputs off

I±, F±

F±

loo2

Pin 11 output disable High to outputs off

OE-

F±

loE2

Pin 11 output enable to active output

tARD

Async reset delay

!ARR

Async reset recovery time

lsPR

Sync preset recovery time

tppR

Power-up reset

Frequency of operation

OE+ 1±, F± I±, F± 1±, F± Vee+

F±
F+ CLK+ CLK+
F+

IMAX

Maximum frequency

NOTES: 1. Refer also to AC Test Conditions. (Test Load Circuit)

l/(t1s + lcKol

TEST CONDITION1 CL (pF)

P3C18V8Z35 (Commercial)
MIN MAX

50

47

50

20

50

20

35

50

0

50

25

50

35

50

15

50

40

5

35

5

25

50

30

35

25

25

35

50

25

P3C18V8ZI (Industrial)
MIN MAX

UNIT

57

ns

25

ns

25

ns

40

ns

0

ns

30

ns

40

ns

20

ns

45

ns

40

ns

30

ns

35

ns

40

ns

30

ns

30

ns

40

ns

20 MHz

September 1, 1993

439

Philips Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices

Product specification
P3C18V8Z35/P3C1 BVBZI

AC ELECTRICAL CHARACTERISTICS
2.7V,;; Vee,;; 3.6V range; R2= 390'1 Commercial = O"C ,;; Tamb ,;; +75°C
Industrial = -40°C ,;; Tamb,;; +85°C

SYMBOL

PARAMETER

FROM

TO

Pulse width

le KP

Clock period (Minimum tis + lcKo)

lcKH

Clock width High

lcKL

Clock width Low

IARW

Async reset pulse width

Hold time

CLK+ CLK+ CLKI±, F±

CLK+ CLKCLK+ I+, F+

l1H

Input or feedback data hold time

Setup time

CLK+

Input±

tis

Input or feedback data setup time

Propagation delay

1±,F±

CLK+

lpD

Delay from input to active output

1±, F±

F±

le KO

Clock High to output valid access nme

CLK+

F±

loE1

Product term enable to outputs off

I±, F±

F±

loD1

Product term disable to outputs off

1±,F±

F±

loD2

Pin 11 output disable High to outputs off

OE-

F±

loE2

Pin 11 output enable to active output

OE+

F±

!ARD

Async reset delay

I±, F±

F+

IAAR

Async reset recovery time

I±, F±

CLK+

lsPR

Sync preset recovery time

lppR

Power-up reset

Frequency of operation

I±, F± Vee+

CLK+ F+

IMAX

Maximum frequency

NOTES: 1. Refer also to AC Test Conditions. (Test Load Circuit)

l/(t1s + lcKo)

TEST CONDITION1 CL(PF)

P3C18V8Z35 (Commercial)
MIN MAX

50

57

50

25

50

25

40

50

0

50

30

50

40

50

17

50

45

5

40

5

30

50

35

40

30

30

40

50

21

P3C18V8ZI (Industrial)
MIN MAX

UNIT

57

ns

30

ns

30

ns

45

ns

0

ns

35

ns

45

ns

22

ns

50

ns

45

ns

35

ns

40

ns

45

ns

35

ns

35

ns

45

ns

17 MHz

September 1, 1993

440

Philips Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices

Product specification
P3C18V8Z35/P3C18V8ZI

POWER-UP RESET
In order to facilitate state machine design and testing, a power-up reset function has been incorporated in the P3C18V8Z. All internal registers will reset to Active-Low (logical "O") after a specified period of time (tppR)-

Therefore, any OMC that has been configured as a registered output will always produce an Active-High on the associated output pin because of the inverted output buffer. The internal feedback (0) of a

registered OMC will also be set Low. The programmed polarity of OMC will not affect the Active-High output condition during a system power-up condition.

TIMING DIAGRAMS
INPUTS '7T.~.,r--------.r------------------, ~_,..,..,...,_,..,..,...,_,..,..,...,'"7 110, REG. FEEDBACK

CLK

PIN 110E
REGISTERED OUTPUTS
ANYINPUT"'7T.if'"b'7'T.,..,'7'T.,..,'7'T.,..,'7'T.,..,'7'T.,..,'7'T.,..,'7'T.,..,'7'T.,..,"7'T.7"'i.,r---, ,-----. PROGRAMMED FOR
DIRECTION CONTROL -'-"-4'"-"-"-.L..<"-".L..L..<"-".L..L..<"-".L..L..<"-".L..L..<"-".L..L..<"-"-"-.L..<"-".L..L..<"-".L.LI I' - - - - . I ' - - - - -
COMBINATORIAL OUTPUTS&..J.'-'-"-"""'-'-"-""""-"-"-.L..<'-J ' - - - - - - - - - - - - - - - - - - - - - - " Switching Waveforms
+3.3V

Vee

ov

VoH F
(OUTPUTS) Vol

l,B

+3V

(INPUTS)

ov

+3V CLK
ov

NOTE: Diagram presupposes that the outputs (F) are enabled. The reset occurs regardless of the output condition (enabled or disabled).
Power-Up Reset

September 1, 1993

441

Philips Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices

Product specification
P3C18V8Z35/P3C18V8ZI

TIMING DIAGRAMS (Continued)
ASYNCHRONOUS RESET INPUT_ _ _ __,

REGISTERED OUWUT,L__ _~t;_.;...._~:;_--Jo.c:-,-......;~-1

CLOCK
SYNCHRONOUS PRESET INPUT

Asynchronous Reset
t1s --+1+-- t1H'--+1----·sPR
--~~~~~--+~~

CLOCK
l+-----~K'-o----\
REGISTERED------------------.
OUWUT------------------~~----~
Synchronous Preset

September 1, 1993

442

Philips Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices

Product specification
P3C18V8Z35/P3C18V8ZI

REGISTER PRELOAD FUNCTION (DIAGNOSTIC MODE ONLY)
In order to facilitate the testing of state machine/controller designs, a diagnostic mode register preload feature has been incorporated into the P3C 1SVSZ series device. This feature enables the user to load

the registers with predetermined states while a super voltage is applied to Pins 11 and 6 (lg/Or and 15). (See diagram for timing and sequence.)
To read the data out, Pins 11 and 6 must be returned to normal TIL levels. The outputs, F0 _ 7, must be enabled in order to read data

out. The Q outputs of the registers will reflect data in as input via F0 _ 7 during preload. Subsequently, the register Q output via the feedback path will reflect the data in as input via Fo-7·
Refer to the voltage waveform for timing and
voltage references. tpL = 1Oµsec.

REGISTER PRELOAD (DIAGNOSTIC MODE)

lgitt° (PIN 11)

12.0V

5.0V

IPL IPL

15 (PIN 6)

-----r-----"\ I
lo/CLK - - - - - - - - - - - - - - - - -

(PIN

1)

-

-

-

-

-

-

-

-

+

-

-

-

-

-

-

-

-

+

-

-

-

-

+

'

-

-

-~--.r--1--.-.-.-_--_+_

,I
-

-

-

.

.

PAELOAD DATA IN

DATA OUT

September 1, 1993

443

Philips Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices

Product specification
P3C18V8Z35/P3C18V8ZI

LOGIC PROGRAMMING
The P3C 1SVSZ series is fully supported by industry standard (JEDEC compatible) PLO CAD tools, including Philips Semiconductors' SNAP design software package. ABEL'" and CUPLTM 90 design software packages also support the P3C 1SVSZ architecture.
All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.

P3C 1SVSZ logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only.
With Logic programming, the AND/OR/EX-OR gate input connections necessary to implement the desired logic function are coded directiy from logic equations using the Program Table. Similarly,

various OMC configurations are implemented by programming the Architecture Control bits AC 1 and AC2. Note that the configuration cell is automatically programmed based on the OMC configuration.
In this table, the logic state of variables I, P and B associated with each Sum Term S is assigned a symbol which results in the proper fusing pattern of corresponding link pairs, defined as follows:

OUTPUT POLARITY - (0, B)

0,1'

O.B

I J [[ ACTIVE LEVEL

CODE

I INVERTING1

L

I

l.Bi l.B "AND" ARRAY- (I, B) 1.1'

I 1 [ ACTIVE LEVEL

CODE

I I l NON-INVERTING

H

Bil,B Bil,B

I,

I.

1.1'

T,!J

STATE DON'T CARE

p
STATE INACTIVEi

p
STATE I, B

NOTE: 1. A factory shipped unprogrammed devioe is configured such that all cells are in a conductive state.

Bil,B
I, l,!J
p STATE
1.1'

ERASURE CHARACTERISTICS (For Quartz Window Packages Only)
The erasure characteristics of the P3C18VSZ Series devices are such that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lighting could erase a typical P3C18VSZ in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. If the P3C 1SVSZ is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the window to prevent unintentional erasure.

The recommended erasure procedure for the P3C 1SVSZ is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15Wsec/cm2. The erasure time with this dosage is approximately 30 to 35 minutes using an ultraviolet lamp with a 12,000µW/cm2 power rating. The device should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose a CMOS EPLD can be exposed to without damage is 7258Wsec/cm2). Exposure of these CMOS EPLDs to high intensity UV light for longer
periods may cause permanent damage.

The maximum number of guaranteed erase/write cycles is 50. Data retention exceeds 20 years.

ABEL is a trademark of Data 110 Corp. CUPL is a trademark of Logical Devices, Inc.

September 1, 1993

444

Philips Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices

Product specification
P3C18V8Z35/P3C18V8ZI

PROGRAM TABLE

CONAGURATION CELLj_CLK/llE CONTROY.J:::
A~Jlg~~~l--!-+-+-1--+--+-+-l

~ 1--~~~~~~~~A~N=D~~~~~~,-t
R i-,...8.."'.J1.-,,...-1.J-=r-6..7TC...5."'~c.,.,.-3..7r-2.7r~Jl,-t...1.-=..-L.6..7r...5.~J..,_,Fi_"=)-r-2.-=-r~Jl,-t

ORJAXEl)L

19 20

September 1, 1993

xxx
u~ .
(.)

'It
Ia-:

> ~

aw :

::56:
7

~ en

Cl UJ

Ia-:

'It

N
:J

~

:U::J;
z<( w:a:::; ~ en
::::>
(.)

aw : aC:l
0
wen :<:c( a(.:)
::::>
CL

'It
w
(.)
> w
Cl
en
CL
~
::c
CL

0co
:e>2naw :
:2
~ en
::::>
(.)

u. 0
cwao:
:2
:z:::>
--'
j:'5 ~

l19LI8l 1i l 16L151-1.U 131

AND ARRAY

INACTIVE 0

1,FI,~

H

IF I fil_ L

"DON'T CARE -

OMCARCH.
-=ED RXEDINPUT RXED OUTPUT BIDIRECTIONAL JIO

CONTROL

OUTPUT POLARITY

IL D NON-INVERTING I [INVERTING

IlHt

I

CONRG. CELL'

0
I B LPIN1:CLK;PINn:oqL I LPIN1 PIN11:1NPUT lH

OR ARRAllRXEQL

DATA CANNOT BE ENTERED

INTO THE OR ARRAY RELD DUE TO THE AXED NATURE OF THE DEVICE ARCHITEC.

TURE.

ILDIRECTION CONTROJj_ DJ

I J ACTIVE OUTPUT

A

ILNOT USED

_k:::'.l

· THE CONAGURATION CELL IS AUTOMATICALLY PROGRAMMED BASED ON THE OMC ARCHITECTURE. ··FOR SP, AR: .._ .. JS NOT ALLOWED.

445

Philips Semiconductors Programmable Logic Devices
3 Volt zero standby power universal PAL devices
SNAP RESOURCE SUMMARY DESIGNATIONS

Product specification
P3C18V8Z35/P3C18V8ZI

FROM AND

ARRAY · TO ALL OMCs

- - '' - - - - - - - - - ,

'

I

I

I

I I I AC1n I I AC2n
i - =&J~----------'-_______JH---f------J

I

I

I

:

I l

L_ - --- - - ----f- -:-:-

NOTE: ~}' Denotes a programmable cetl location.

f H

TOALLOMCs

September 1, 1993

446

Philips Semiconductors Programmable Logic Devices
3 Volt BiCMOS Versatile GAL-type PLO

Preliminary specification
LVT16V8-7

DESCRIPTION
The LVT16VB-7 is a V-type GAL device designed to operate over the 3.0 to 3.6 volt range. This versatile device is fabricated using the BiCMOS process which produces superior performance, low noise and reduced ground bounce. The reduction from 5V to 3.3V also dramatically reduces power to less than 0.5 watts (worst case). This industry standard device is ideal for high performance systems which have been designed to operate with 3.3V ± 0.3V power supplies, as well as systems which are operating with dual supplies (5.0V and 3.3V). The LVT16V8-7 can accept both 3.3 and 5.0V input levels without the need for level translators. Both the inputs and 1/0 have high state reverse current flow protection to insure that the outputs are not damaged if the 3V LVT16V8 is interfaced with 5V devices. The LVT16V8-7 is designed with metastable hardened flip-flops so that the outputs can never display a metastable state due to set up or hold time violations. If set up or hold times are violated, the outputs will not glitch or display a metastable state (however propagation delays may extend). Active bus-hold circuitry is provided to eliminate the need for external resistors to hold unused or floating inputs at valid logic levels.
The LVT16VS's flexible architecture supports a wide variety of high performance applications: counters, shift registers, address decoders, state machines, multiplexers and random logic collection.
The LVT16V8-7 is identical, in function and fuse map, to other industry standard EEPROM and EPROM 16V8 devices. Development and programming support are offered by Philips and other third party vendors.
ORDERING INFORMATION DESCRIPTION
20-Pin Plastic Dual In-Line Package 20-Pin Plastic Leaded Chip Carrier 20-Pin Plastic Small Outline Large Package

FEATURES
Advanced low voltage BiCMOS process technology Ultra high performance over the 3.0 to 3.6 voltage range
- 7.5ns lpo
- 5.0ns Tis - 5.0ns TeKo - 110 MHz FMAX (internal feedback) - 143 MHz clock rate Low power dissipation - 300mW typical 5V compatible inputs and 1/0 Exceptional noise immunity and low ground bounce Live insertion/extraction Bus-hold data inputs eliminate the need for external pull up resistors. Wide package availability; DIP, PLCC, SOL Metastable hardened Flip-Flops · Architectural Flexibility - Emulates all 20 pin PAL devices - Up to 16 inputs and 8 outputs - Independently programmable 1/0
macrocells (4 configurations) - Independently programmable output
polarity - Product term output enable for
combinatorial functions - Register Preload and Power Up reset of
all registers Development and programming support - Third party software and programmers - Philips SNAP development software
ORDER CODE
LVT16V8-7N LVT16V8-7A LVT16V8-70

PIN CONFIGURATIONS
D and N Packages
v,, v..
l/05
v,.
Ii,, 11,,
v,,
l/oo GND
N "' Plastic DIP (300mil-wide) D =Plastic SOL {300mil-wide)
A Package
lios l/05
l/04 l/03 1102
A "' Plastic leaded Chip Carrier

PIN TABLE DESCRIPTIONS

CLK Clock

GND Ground

I

Input

110 Input/Output Macro Cell

NC No connect
OE Output Enable

Vee Supply Voltage

DRAWING NUMBER
0408B 0400E 01720

October 1993

447

Philips Semiconductors Programmable Logic Devices
3Volt BiCMOS Versatile GAL-type PLD
LOGIC DIAGRAM

0

4

8

12

16

20

24

28

· 9
10 11 12 13 14
15

2..

18 17
18 19 20 21 22 23

2

24 25
,.26
Z1

29 30 31
2

32 33 34 35
..36
37
38

~
40 41
...42
43
45 48 47
'2_

48 4& 50 51 52 53 54 66
2

58 57 58 59 00 81 82 63
,;:E_

64 85 66 f5I 68 00 70 71
,;:E_

12

16

20

24

28

October 1993

448

Preliminary specification
LVT16V8-7

CK

~
OLMC~ 19 19
~~ -v
OLMC~ 18 18

3:~
OLMC~ 17 17
~~t:K 16 OLMCµ 16

~~
:LMC~ 15 15

rv= _s.:1-1
OLMC~

14

14

-5:~

OLMC~

13

13

~ OLMC~

12

12

3:1- 1oE 11

Philips Semiconductors Low Voltage Products
3 Volt BiCMOS Versatile PAL

Preliminary specification
LVT22V10-7

DESCRIPTION
The LVT22V10-7 is a V-type PAL device designed to operate over the 3.0 to 3.6 volt range. This versatile device is fabricated using the BiCMOS process which produces superior performance, low noise and reduced ground bounce. The reduction from 5V to 3.3V also dramatically reduces the power consumption to less than 1OOmA (worst case).
This industry stan.dard device is ideal for high performance systems which have been designed to operate with 3.3V ± 0.3V power supplies, as well as systems which are operating with dual supplies (5.0V and 3.3V). The LVT22V10-7 can accept both 3.3 and 5.0V input levels without the need for level translators. Both the inputs and 1/0 have high state reverse current flow protection to insure that the outputs are not damaged if the 3V LVT22V10 is interfaced with 5V devices.
The LVT22V10-7 is designed with metastable hardened flip-flops so that the outputs can never display a metastable state due to set up or hold time violations. If set up or hold times are violated, the outputs will not glitch or display a metastable state however (propagation delays may extend).
The LVT22V10's flexible architecture supports a wide variety of high performance applications: counters, shift registers, address decoders, state machines multiplexers and random logic collection.
The LVT22V10-7 is identical, in function and fuse map, to other industry standard EEPROM and EPROM 22V10 devices. Development and programming support are offered by Philips and other third party vendors.

FEATURES
· Advanced low voltage BiCMOS process technology
Ultra high performance over the 3.0 to 3.6 voltage range
- 7.Sns Tpo - 5.0ns Tis - 6.0ns TeKo - 110 MHz FMAX (internal feedback) - 143 MHz clock rate Low power dissipation
- 300mW typical SV compatible inputs and 1/0
Exceptional noise immunity and low ground bounce
Live insertion/extraction
Metastable hardened Flip-Flops
Wide package availability; DIP, PLCC, SOL
Architectural Flexibility
- Up to 22 inputs and 10 outputs - Variable product term distribution for
greater logic flexibility - Synchronous preset; asynchronous clear - Independently programmable output
polarity and output enable - Register preload and power up reset of
all registers - Register Preload and Power Up reset of
all registers Development and programming support - Third party software and programmers - Philips SNAP development software

PIN CONFIGURATIONS D and N Packages

19 GND

Vee
F9 F8 F7 F6 F5 F4 F3 F2 F1 FD 111

N = Plastic Dual In-line Package (300mil-wide) D "" Plastic Small Outline Large (300mil-wide)
Package
A Package
eLK/ 12 11 ID Vee Vee F9 FS

1 11

19 110 GNDGNDl11

F1

A"" Plastic Leaded Chip Carrier

ORDERING INFORMATION
DESCRIPTION
24-Pin Plastic Dual In-Line Package 28-Pin Leaded Chip Carrier 24-Pin Plastic Small Outline Large Package

ORDER CODE
LVT22V10-7N LVT22V10-7A LVT22V10-7D

PIN LABEL DESCRIPTIONS

11-111

Dedicated Input

NC

Not Connected

FO-F9

Macro Cell lnput'Output

CLK/10

Clock lnput'Dedicated Input

Vee

Supply Voltage

GND

Ground

DRAWING NUMBER
0410D 0401F 01730

July 1993

Philips Semiconductors Low Voltage Products
3 Volt BiCMOS Versatile PAL
LOGIC DIAGRAM

Preliminary specification
LVT22V10-7

GND~

3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43

NOTE' ~:;~:~:~~:; Programmable connection.

July 1993

450

Philips Semiconductors Low Voltage Products
3 Volt BiCMOS Versatile GAL-type PLO

Preliminary specification
LVT20V8-7

DESCRIPTION
The LVT20V8-7 is a V-type GAL device designed to operate over the 3.0 to 3.6 volt range. This versatile device is fabricated using the BiCMOS process which produces superior performance, low noise and reduced ground bounce. The reduction from 5V to 3.3V also dramatically reduces power to less than 0.5 watts (worst case).
This industry standard device is ideal for high perlormance systems which have been designed to operate with 3.3V ± 0.3V power supplies, as well as systems which are operating with dual supplies (5.0V and 3.3V). The LVT20V8-7 can accept both 3.3 and 5.0V input levels without the need for level translators. Both the inputs and 110 have high state reverse current flow protection to insure that the outputs are not damaged if the 3V LVT20V8 is interfaced with 5V devices.
The LVT20V8-7 is designed with metastable hardened flip-flops so the outputs can never display a metastable state due to set up or hold time violations. If set up or hold times are violated, the outputs will not glitch or display a metastable state (however propagation delays may extend).
Active bus-hold circuitry is provided to eliminate the need for external pull up resistors to hold unused or floating inputs at valid logic levels.
The LVT20V8's flexible architecture supports a wide variety of high performance applications: counters, shift registers, address decoders, state machines, multiplexers and random logic collection.
The LVT20V8-7 is identical, in function and fuse map, to other industry standard EEPROM and EPROM 20V8 devices. Development and programming support are offered by Philips and other third party vendors.

FEATURES
Advanced low voltage BiCMOS process technology
Ultra high performance over the 3.0 to 3.6 voltage range
- 7.5ns Tpo - 5.0ns T1s - 6.0ns TcKo - 11 OMHz FMAX (internal feedback) - 143MHz clock rate Low power dissipation
- 300mW typical 5V compatible inputs and l/O
Exceptional noise immunity and low ground bounce
Live insertion/extraction
Metastable hardened Flip-Flops
Wide package availability; DIP, PLCC, SOL
Bus-hold data inputs eliminate the need for external pull up resistors
Architectural Flexibility
- Emulates all 24 pin PAL devices - Up to 20 inputs and 8 outputs - Independently programmable 1/0
macrocells (4 configurations) - Independently programmable output
polarity - Product term output enable for
combinatorial functions - Register Preload and Power Up reset of
all registers Development and programming support - Third party software and programmers - Philips SNAP development software

PIN CONFIGURATIONS
D and N Packages
113 1107 1/06 1/05 1104 1103 1/02 1101 1100 112 GND N = Plastic DIP (300mil-wide) D = Plastic SOL (300 mil-wide)
A Package

19 110 GNDGNDDEI 112 110 111
A= Plastic Leaded Chip Carrier
PIN TABLE DESCRIPTIONS

CLK GND
I 1/0 NC OE Vee

Clock Ground Input lnput'Output Macro Cell No connect Output Enable Supply Voltage

ORDERING INFORMATION DESCRIPTION
24-Pin Plastic Dual In-Line Package 28-Pin Plastic Leaded Chip Carrier 24-Pin Plastic Small Outline Large Package

ORDER CODE LVT20V8-7N LVT20V8-7A LVT20V8-7D

DRAWING NUMBER 0410D 0401F 0173D

July 1993

A~<

Philips Semiconductors Low Voltage Products
3 Volt BiCMOS Versatile GAL-type PLO

Preliminary specification
LVT20V8-7

LOGIC DIAGRAM
1

0
2~
· 8
10 11 12 13 14 16
3 ~
16 17 16 19 20 21 22 23
4 '2J
..24
28
27 28 29 30 31
5--f>I
32 33 34
.36
..37
39
6 ~
40
..41
42 43
45 46 47
.7 ~ 49 5"1 ' 52 53 54 55
B ~
..56
57 56
61 62 63
..9-l~ 65 66 67 68 69 70 71
10 :::iB

4

8

12

16

20

24

28

32

36

11-121

0

4

B

12

16

20

24

28

32

36

452

;--
23 I M
u x

~1-L_ CK

-v

~ OLMC

22

22

:s::h'.v::I=r:

FB~ OLMC 21

21

_s:HrOLMC~

20

20

_s:H PLJ;l,. 19 O 19 L M C µ

~ OLMC~

18

18

~J-p

OLMC~

17

17

3:]---p

OLMC~

16

16

.s:1---fPO=LMC~

15

15

3:J_-. -'---CoE
_s;_r
I M
x u
.___

l<1---i 14 13

Programmable Logic Devices

Section 7
Programmable Macro Logic Devices

CONTENTS

PLHS501/PLHS501 I Programmable macro logic ..

455

PML2552

CMOS high density programmable macro logic

467

PML2852

CMOS high density programmable macro logic

486

J ·

Phillps Semiconductors Programmable Logic Devices
Programmable macro logic PMLTM

Product specification
PLHS501 /PLHS501 I

FEATURES · Programmable Macro Logic device
· Full connectivity
· TTL compatible
· SNAP development system: - Supports third-party schematic entry formats - Macro library - Versatile netlist format for design portability - Logic, timing, and fault simulation
· Delay per internal NANO function = 6.5ns (typ)
· Testable in unprogrammed state
· Security fuse allows protection of proprietary designs
STRUCTURE · NANO gate based architecture
- 72 foldback NANO terms
· 136 input-wide logic terms
· 44 additional logic terms
· 24 dedicated inputs (lo - 123)
· 8 bidirectional I/Os with individual 3-State enable: - 4 Active-High (84 - 87)
- 4 Active-Low (Bo - "Bal
· 16 dedicated outputs: - 4 Active-High outputs Oo, 01 with common 3-State enable
O:?. ~with common 3-State enable
- 4 Active-Low outputs: 0 4, Os with common 3-State enable 0 6, 0 7 with common 3-State enable
- 8 Exclusive-OR outputs:
Xo. X1 with common 3-State enable
X2, X3 with common 3-State enable ~. Xs with common 3-State enable Xs. X1 with common 3-State enable

PIN CONFIGURATION

A Package (52-pln PLCC)
la 17 la 15

Vee

'4

13

12
'·
1 lo

83

B2

B1
7 Bo

X7

Do

Xs

GND

GND

1
01 O:! ~ tl4 tl5 "Ila "ll] lCo X1 X2 ~ X4 X5

DESCRIPTION The PLHS501 is a high-density Bipolar Programmable Macro Logic device. PML incorporates a programmable NANO structure. The NAN D architecture is an efficient method for implementing any logic function. The SNAP software development system provides a user friendly environment for design entry. SNAP eliminates the need for a detailed understanding of the PLHS501 architecture and makes it transparent to the user. PLHS501 is also supported on the Philips Semiconductors SNAP software development systems.
The PLHS501 is ideal for a wide range of microprocessor support functions, including bus interface and control applications.
The PLHS501 is also processed to industrial requirements for operation over an extended temperature range of -40°C to +85°C and supply voltage of 4.5V to 5.5V.

ARCHITECTURE The core of the PLHS501 is a programmable fuse array of 72 NANO gates. The output of each gate folds back upon itself and all other NANO gates. In this manner, full connectivity of all logic functions is achieved in the PLHS501. Any logic function can be created within the core of the device without wasting valuable 1/0 pins. Furthermore, a speed advantage is acquired by implementing multi-level logic within a fast internal core without incurring any delays from the 1/0 buffers.

PML is a trademark of Philips Semiconductors October 22, 1993

Philips Semiconductors Programmable Logic Devices
Programmable macro logic PMLTM

Product specification
PLHS501 /PLHS501 I

ORDERING INFORMATION DESCRIPTION
52-Pin Plastic Leaded Chip Carrier
52-Pin Plastic Leaded Chip Carrier

OPERATING CONDITIONS
Commercial Temperature Range ±5% Power Supply
Industrial Temperature Range ±10% Power Supply

ORDER CODE PLHS501A PLHS501IA

DRAWING NUMBER 0397E 0397E

DESIGN DEVELOPMENT TOOLS
SNAP
The SNAP Software Development System provides the necessary tools for designing with PML. SNAP provides the following: · Schematic entry netlist generation from
third-party schematic design packages such as OrCAD/SDT IllTM and FutureNetTM.
· Macro library for standard TTL functions and user defined functions
· Boolean equation entry
· State equation entry
· Syntax and design entry checking
· Simulator includes logic simulation, fault simulation and timing simulation.

SNAP operates on an IBM® PC/XT, PC/AT, PS/2, or any compatible system with DOS 2.1 or higher. The minimum system configuration for SNAP is 640K bytes of RAM and a hard disk.
SNAP provides primitive PML function libraries for third-party schematic design packages. Custom macro function libraries can be defined in schematic or equation form.
After the completion of a design, the software compiles the design for syntax and completeness. Complete simulation can be carried out using the different simulation tools available.
The programming data is generated in JEDEC format. Using the Device Programmer Interface (DPI) module of SNAP,

the JEDEC fusemap is sent from the host computer to the device programmer.
DESIGN SECURITY
The PLHS501 has a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved.
PROGRAMMING/SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 1O(Third-party Programmer/ Software Support) of this data handbook for
additional information.

Future Net is a trademark of FutureNet Corporation.
OrCAD/SDT is a trademark Of OrCAD, Inc. IBM is a registered trademark of International Business Machines Corporation.

456

Philips Semiconductors Programmable Logic Devices
Programmable macro logic PMLTM
PLHS501 FUNCTIONAL BLOCK DIAGRAM
24 DEDICATED
INPUTS

Product specification
PLHS501 /PLHS501 I

NANO ARRAY

I N T E R
c
0 N N E
c
T
16 DEDICATED OUTPUTS

8 BIDIRECTIONAL
I/OS

October 22, 1993

457

Philips Semiconductors Programmable Logic Devices
Programmable macro logic PMLTM

Product specification
PLHS501 /PLHS501 I

FUNCTIONAL DIAGRAM

71

...

0

lg \':).
!
1:!3 ~

~
~
-~
<I-

!

~···QQQ~l3l3l3 x4 x4

~ "·:~-fci

,

x4

~B

'

' )}x4

' :I
' ]) x4

x

'

'

x2

'

v x2 0

'

'

x2

'

x2

~ _____ ~E_!~IL_ A_ _____ 1

October 22. 1993

458

Philips Semiconductors Programmable Logic Devices
Programmable macro logic PMLTM

Product specification
PLHS501 /PLHS5011

DETAIL A
-----------------------------~

'---------+--El B&
t.....-----------4t--------j1a e7
~------§1 Xo ~-------------129 X1
'----------El X2
~-------------J31 X3
~-------1§1 ~
~--------------j33 X5
' - - - - - - - - - - 1 § 1 X& ~--------------t36 X7
-----------Gao
--------------18 01 -----------§] 02
~----------§)03 -----------~ 04 ---------------i~Os
-----------§] ll&
~---------------------------------J

October 22, 1993

459

Philips Semiconductors Programmable Logic Devices
Programmable macro logic PMLTM

ABSOLUTE MAXIMUM RATINGS1

RATINGS

SYMBOL

PARAMETER

MIN

MAX

UNIT

Vee V1N Vour l1N

Supply voltage Input voltage Output voltage Input currents

+7

Voe

+5.5

Voe

+5.5

Voe

-30

+30

mA

lour

Output currents

+100

mA

Tairb

Operating temperature range

0

+75

·c

Tstg

Storage temperature range

-65

+150

·c

NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS

TEMPERATURE

Maximum junction

150°C

Maximum ambient

75°C

Allowable thermal rise ambient to junction

75°C

VIRGIN STATE
A factory shipped virgin device contains all fusible links open, such that: 1. All product terms are enabled.
2. All bidirectional (B) pins are outputs.
3. All outputs are enabled.
4. All outputs are Active-High except
Bo - "B3 (fusible 1/0) and 0 4 - 0 7 which
are Active-Low.

Product specification
PLHS501/PLHS5011

Octaber 22. 1993

460

Philips Semiconductors Programmable Logic Devices
Programmable macro logic PMLTM

Product specification
PLHS501 /PLHS501 I

DC ELECTRICAL CHARACTERISTICS
Commercial= 0°C $Tarro$ +75°C, 4.75V $Vee$ 5.25V
Industrial = -40°C STarm S +85°C, 4.SV S Vee S 5.SV

SYMBOL Input voltage:?

PARAMETER

TEST CONDITION

LIMITS

MIN

TYP1

MAX

V1L

Low

V1H

High

Vic

Clamp2· 3

Output voltage

Vcc=MIN Vee= MAX Vee= MIN, l1N =-12mA

0.8

2.0

--0.8

-1.2

Vol

Low2· 4

VoH

High2· 5

Input current

Vee =MIN loL = 10mA loH =-2mA

0.45 2.4

l1L

Low

l1H

High

Output current

Vee= MAX V1N = 0.45V V1N = 5.SV

-100 40

lo(OFF)

Hi-Z state9

los

Short circuit3· 5, s

Ice

Vee supply current"

Capacitance

Vee= MAX VouT = 5.SV VouT = 0.45V VouT=OV
Vcc=MAX

80

-140

-15

-70

225

295

C1N

Input

Cs

110

Vee =5V

V1N = 2.0V

8

VouT = 2.0V

15

NOTES: 1. All typical values are at Vee = 5V, Tarro= +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time.
4. For Pins 15 - 19, 21 - 27 and 37 -40, Vol is measured with Pins 5 and 41 = 8,75V, Pin 43 = OV and Pins 42 and 44 = 4.SV. For Pins 28 - 33 and 35 -36, Vol is measured under same conditions EXCEPT Pin 44 = OV.
5. VoH is measured with Pins 5 and 41=8.75V, Pins 42 and 43 = 4.5V and Pin 44 = OV. 6. Duration of short circuit should not exceed 1 second. 7. Ice is measured with all dedicated inputs at OV and bidirectional and output pins open. 8. Measured at VT= Vol + 0.5V. 9. Leakage values are a combination of input and output leakage.

UNIT
v v v
v v
µA µA
µA mA mA
pF pF

TEST LOAD CIRCUITS
INPUTS NOTE: C1 and C2 are to bypass Vee to GNO.

Vee l::_.>

R1

lo

By

CL OUT

Bz Bx GND Ox
"::"

OUTPUTS
"::"

VOLTAGE WAVEFORMS

L. .Jc -~
.. _j

2.5na

2.5ns

:Jt-£

2.Sna

2.Sns

MEASUREMENTS: All circuit delays are measured at the+ l .5V level

of inputs and outputs, unless otheiwise specified.

Input Pulses

October 22, 1993

461

Philips Semiconductors Programmable Logic Devices
Programmable macro logic PMLTM

Product specification
PLHS501 /PLHS501 I

SNAP RESOURCE SUMMARY DESIGNATIONS

71
'o~~I-

...

0

123

~

_,_']

~

'..j...'

~
.sJ-i

l

~···QAJ~~ x4 x4

~ ~~~

x4 j-o
.,,. x4 !..[]

"J}x4 _l
_J)x4

XQ,x.,~.x.,
l~i
X1, Xa. X5, X7

..N. x2
~ Oo.02 f@lj@ o,.ea

x2 x2
v

04, os ti.Mi9M
Os.07

October 22. 1993

462

Philips Semiconductors Programmable Logic Devices
Programmable macro logic PMLTM

Product specification
PLHS501 /PLHS501 I

MACRO CELL SPECIFICATIONS1 (SNAP Resource Summary Designations in Parantheses)
Commercial:Tarro = 0°C to +75°C, 4.75V s Vee s 5.25V, Cl= 30pF, R2 = 1000'1, R1 = 470'1 Industrial: Tarro= -40°C to +85°C, 4.5V s Vee s 5.5V, Cl= 30pF, R2 = 1000'1, R1= 470'1
Input Buffer (OIN501 [Non-Inverting], NIN501 [Inverting])

·~~

SYMBOL ,1,fHl ,1,ti_H

MIN 0.05 --0.02

LIMITS TYP 0.1 --0.05

MAX 0.15 --0.08

UNIT ns/p-term ns/p-term

PARAMETER

SYMBOL

To

(Output)

From (Input)

MIN

!pHl tPlH

x x

I

4.5

I

5

tPHl

y

tPlH

y

I

2.5

I

4

Input Pins: 1 - 7, 9 - 14, 41 -45, 48 -52. Bidirectional Pins: 15 - 18, 37 -40. Maximum internal fan-out: 16 p-terms on Xor Y.

LIMITS
TYP
5.5 6 3 4

MAX
6.5 7.5
3.5 4.5

UNIT
ns ns ns ns

NANO Output Buffer with 3-State Control (TOU501)

NOTES With O p-terms load With 0 p-terms load

Tri-ctrl

In

Out

PARAMETER

SYMBOL

To

(Output)

From (Input)

tPHl

Out

In

tPlH

Out

In

loE2

Out

Tri-Ctrl

loD2

Out

Tri-Ctrl

Output Pins: 24 - 27.

LIMITS

MIN

TYP

8.5

14.0

8.5

14.0

8.5

15

8.5

12.5

Internal Foldback NANO (FBNANO)

Input

D

Output

MAX
17.5 16
18.5 17.0

SYMBOL LltPHl ,1,tplH

MIN 0.05 --0.0

LIMITS TYP 0.1 --0.05

MAX 0.15 --0.1

UNIT ns/p-term ns/p-term

UNIT
ns ns ns ns

'

PARAMETER

LIMITS

SYMBOL

To

(Output)

From (Input)

MIN

TYP

MAX

tPHl trlH

Out

Any

4.0

4.5

6.8

5.5

6.5

8

Maximum internal loading of 16 terms. Notes are on following page.

UNIT
ns ns

NOTES With 0 p-terms load

October 22, 1993

463

Philips Semiconductors Programmable Logic Devices
Programmable macro logic PMLTM

Product specification
PLHS501/PLHS5011

MACRO CELL SPECIFICATIONS1 (Continued) (SNAP Resource Summary Designations in Parantheses) Commercial:Tarr1> = 0°c to +75°C, 4.75V s; Vee s 5.25V, CL= 30pF, R2 = 1ooon, R1 = 470n Industrial: Tami>= --40°C to +85°C, 4.5V s Vee s 5.5V, CL= 30pF, R2 = 1ooon, R1 = 470n
AND Output Buffer with 3-State Control (NOU501)

OUt

PARAMETER

SYMBOL

To

(Output)

From (Input)

MIN

LIMITS TYP

lpHL

Output

In

8.0

11

lpLH

Output

In

8.0

11

loE2

Out

Tri-Ctrl

8.5

15

too2

Out

Tri-Ctrl

8.5

12.5

Bidirectional and Output Pins: 19, 21, 22, 23, 15 -18.

NANO Output Buffer (OUT501)

ln~OUt

MAX
13 13
18.5 17.0

PARAMETER

SYMBOL

To

(Output)

From (Input)

lpHL

Out

In

tPLH

Out

In

Bidirectional Pins: 37 - 40.

LIMITS

MIN

TYP

8.5

14

8.5

14

Ex--OR Output Buffer (EX0501)

MAX
17.5 16.0

UNIT ns ns ns ns
UNIT ns ns

PARAMETER

LIMITS

SYMBOL

To

(Output)

From (Input)

MIN

TYP

MAX

UNIT

lpHL

Out

AorB

8.5

lpLH

Out

Aor B

8.5

loE2

Out

Tri-Ctrl

8.5

too2

Out

Tri-Ctrl

8.5

14

17.5

ns

14

16.0

ns

15

18.5

ns

12.5

17.0

ns

Ex-OR Output Pins: 28 - 33.
NOTES: 1. Limits are guaranteed with internal feedback buffers simultaneously switching cumulative maximum of eight outputs. 2. For 3-State output; output enable times are tested with CL= 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output voltage of Vr = (VoH -0.5V) with S1open, and Low-to-High impedance tests are made to the Vr = (VoL + 0.5V) level with S 1 closed.

October 22, 1993

464

Philips Semiconductors Programmable Logic Devices
Programmable macro logic PMLTM

Product specification
PLHS501 /PLHS501 I

PLHS501 GATE AND SPEED ESTIMATE TABLE

FUNCTION

INTERNAL NANO EQUVALENT

TYPICAL tpo

Gates

NANDs ANDs NORs ORs

1

6.5ns

1

6.5ns

1

6.5ns

1

6.5ns

Decoders

3-to-8 4-to-16 5-to-32

8

11ns

16

11ns

32

11ns

Encoders

8-to-3 16-to-4 32-to-5

15

11ns

32

11ns

41

11ns

Multiplexers

4-to-1 8-to-1 16-to-1 27-to-1

5

11ns

9

11ns

17

11ns

28

11ns

Flip-Flops

D-type Flip-Flop

6

T-type Flip-Flop

6

J-K-type Flip-Flop

10

Adders

8-bit Barrel Shifters

45

15.5ns

8-bit

72

11ns

latches

D-latch

3

fuAx
30MHz 30MHz 30MHz

COMMENTS
For 1 to 32 input variables For 1 to 32 input variables For 1 to 32 input variables For 1 to 32 input variables
Inverted inputs available Inverted inputs available Inverted inputs available (24 chip outputs only)
Inverted inputs, 2 logic levels Inverted inputs, 2 logic levels Inverted inputs, 2 logic levels, factored solution.
Inverted inputs available
Can address only 27 external inputs - more if internal
With asynchronous S-R With asynchronous S-R With asynchronous S-R
Full carry-lookahead (four levels of logic)
2 levels of logic
2 levels of logic with one shared gate

October 22, 1993

465

Philips Semiconductors Programmable Logic Devices
Programmable macro logic PMLTM

Product specification
PLHS501 /PLHS501 I

APPLICATIONS

r-------- MASTER -----,r----- SLAVE --,
MODULE SPECIRC

PLHS501

CLOCK ORIGINATION

NUBUS

ARBITRATION

Simplified NuBusTM Diagram (10MHz Operating Frequency)

-ADL
-COSETUP -M/-10 -S1 -SO -A2 -A1 -AO
-CMD---------'
~7c;ZB~============:::>!
DOO
CHRESET

TRANSCEIVER,__ _ _ BUFEN

CONTROL

DIR

t===> r--t--1 1-----+--I

~E 2

DATA OUTPUT

Block Diagram of Basic POS Implementation in PLHS501

NuBus is a trademark of Texas Instruments, Inc.

October 22, 1993

466

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

FEATURES · Full connectivity · Erasable version and one time
programmable version available ·Scan test · Power down mode · Power on reset · 100% testable · SNAP development system
- Supports third-party schematic entry formats
- TTL Macro library - Versatile netlist format for design
portability · Power dissipation (TTL) = 630mW · Power dissipation (CMOS)= 525mW · Power dissipation (Power-Down mode)=
52mW · Security fuse for copy protection · Reprogrammable
PROPAGATION DELAYS · Delay per internal NANO gate
= 15ns (typ) · 50MHz flip-flop toggle rate
APPLICATIONS · Low-end gate array replacement · Instrumentation · Bus arbitration functions · Wide multiplexers and decoders · Multiple independent state machines · General purpose logic integration and
microprocessor support logic · PAL<II and glue logic replacement

DESCRIPTION The Philips Semiconductors PML family of PLDs provides 'instant gate array" capabilities for general purpose logic integration applications. The PML2552 is Iha first high density CMOS-PML product. Fabricated with lhe Philips Semiconductors high-performance EPROM process, it is an ideal way to reduce NRE costs, inventory problems and quality concerns. The PML2552 incorporates Iha PML folded NANO array architecture which provides 100% connectivity to eliminate routing restrictions. What distinguishes the PML2552 from the 'classic" PLO architectures is its flexibility and the potent flip-flop building blocks. The device utilizes a folded NANO architecture, which enables the designer to implement multiple levels of logic on a single chip. The PML2552

eliminates lhe NRE costs, risks, and hard to use design tools associated with semicustom and full custom approaches. It allows the system designer to manage reliable functionality, in less time and space plus a faster time to market. The PML2552 is ideal in todays instrumentation, industrial control, EISA, NuBusTM, bus interface and dense state machine applications in conjunction with the state-of-the-art CMOS processors. It is capable of replacing large amounts of TTL, SSI and MSI logic and literally allows lhe designer to build a system on the chip.
The SNAP development software gives easy access to the density and flexibility of the PML2552 through a variety of design entry formats, including schematic, logic equations, and state equations in any combination.

PIN CONFIGURATION

l/CKD3
l/CKD2 l/CKDI l/CKB/CKC
PD 1/087

l/012 V013 V014 V015 CKE2 VCC2 BO Bl 82
B4 GND2 85 86 87 VDAO I/DAI

ORDERING INFORMATION DESCRIPTION
68-pin Plastic Leaded Chip Carrier 68-pin 'J" Leaded Ceramic Cerquad Package 68-pin Plastic Leaded Chip Carrier 68-pin 'J" Leaded Ceramic Cerquad Package
PAL is a registered trademark of Advanced Micro Devices, Inc. NuBus is a trademark of Texas Instruments, Inc.

tpD(MAX) 35ns 35ns sons 50ns

ORDER CODE PML2552-35A PML2552-35KA PML2552-50A PML2552-50KA

DRAWING NUMBER 0398E 1473A 0398E 1473A

October 22, 1993

467

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

FUNCTIONAL BLOCK DIAGRAM

16

INPUT
· D FLIP-FLOPS
13 DEDICATED

I

INPUTS

A

p

R

~

0 G R A M

M

A

FOLDED NAND ARRAY

B L E

B

I

N

T

E R
c

0 N

N

E

10

c

JK FLIP-FLOPS

T

WITH COMMON

CLK

c

1&0UTPUT DFLIP-FLOPS
E
24 Bl-DIRECTIONAL
110.

10 JK FLIP-FLOPS
WITH DISTINCT
CLKS D
Figure 1.

October 22, 1993

468

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

LOGIC DIAGRAM

-7

!I"

8

A

IL.

r(8)Qr I/DA -8,

CKA

~ -1,

I/DB

8

f g 1/08-1/015

(SCANOUl)

1 ~

tt=t:::=::t==:t=:::=:::::=::t==:t==t:=t:JtL=t=t=:jt=::t:Jcd-:--~--,-<

8

l/OD-V07 (SCANOUl)

1y 3
20 10

8 "~DBFB~ 7) 16 E

(8) D

(8)

OD

~ "::'

Q "::'

BFB(8-15 _ _ _ _ _..,

TL-1-------~~KE1
(SCAN CLOCK)
CKE2

1 00~1
/

October 22, 1993

469

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

STRUCTURE
· 112 possible foldback NAND gates: - 96 internal NAND - 16 from the 1/0 macros
· 114 additional logic terms
· 53 possible inputs (with programmable polarity) - 29 dedicated inputs - 24 bidirectional I/Os
· 24 bidirectional pins
· 52 flip-flops
· 24 possible outputs with individual Output Enable control (8 with programmable polarity)
· Multiple independent clocks
· 20 Buried JK-type flip-flops with foldback (JKFFs): - 1OJKFFs with one shared preset signal and one shared clocked signal originating from the clock array. - 1OJKFFs with 10 independent clock signals originating from the clock array and 1Oindependent clear signals
· 258 inputs per NAND gate
· Bypassable Input D-type flip-flop (DFFs)/Combinatorial Inputs: - 16 DFFs/combinatorial inputs - DFFs clocked in two groups of eight - DFFs not bypassed in unprogrammed state - Independent bypass fuse on each DFF
· lnputs/bypassable D-type flip-flop outputs/foldback NAND gates: - 16 output DFFs/combinatorial inputs/outputs with individual Output Enable control - DFFs clocked in two groups of eight - DFFs not bypassed in unprogrammed state - Independent bypass fuse on each DFF - The DFF can be used as an internal DFF or an internal foldback NANO gate.
· Combinatorial inputs: - 9 dedicated inputs to the NAND array - 3 inputs optional to NAND array and/or clock array - 1 input optional to NAND array and/or clock array, and/or clock of Input D Flip-Flops (Group B)

· Separate clock array:
- Separate clock array for JKFFs clock inputs
- 4 inputs to clock array originated from NAND array
- 4 inputs (with programmable polarity) directly from input pins
- 10 inputs from Q outputs of JKFFs with clear
· Dedicated clocks:
- One dedicated clock for input DFFs (Group A)
- Two dedicated clocks for output DFFs
· Scan test feature: - Scan chain is implemented through the 20 buried JKFFs and 16 output DFFs - Pins SCI, SCM, and CKE1 are used to operate the scan test
· Power down mode
- Dedicated pin (PD) freezes the circuit when brought to logic "1 ".The circuit remains in the same state prior to the logic "O" to logic "1" transition of the "PD" pin.
- When in the power down mode, the SCI pin acts as the 3-State pin for the 24 outputs.
· Power on reset:
- All flip-flops (16 input DFFs, 20 buried JKFFs, and 16 output DFFs) are resetto logic "O" after Vee power on.
ARCHITECTURE
The core of the PML2552 is a programmable NANO array of 96 NAND gates and 20 buried JKFFs. The output of each NAN D gate folds back upon itself and all other NANO gates
and flip-flops. The 'Q' and '0' output of each
flip-flop also folds back in the same manner. Thus, total connectivity of all logic functions is achieved in the PML2552. Any logic function can be created within the core without wasting valuable 1/0 pins. Furthermore, a speed advantage is acquired by implementing multi-level logic within a fast internal core without incurring any delays from the 1/0 buffers. Figure 1 shows the functional block diagram of the PML2552.
Macro Cells
There are 16 bypassable DFFs on the input to the NAND array. These flip-flops are split in two banks of 8 (Bank A and Bank B). Each bank of flip-flops has a common clock. In the

unprogrammed state of the device the flipflops are active. In order to bypass any DFF, its respective bypass fuse (BFAx) must be programmed.
The 16 1/0 pins (100 - 1015) and their respective D flip-flop macros can be used in any one of the following configurations: 1. As combinatorial input(s).
Each of the 16 3-State outputs can be individually disabled by the associated NAND term and the pin is used as an inverting or non-inverting input. 2. As registered DFF outputs. These DFFs are split into two banks of 8, and each bank is clocked separately. The bypass fuse BFBx (see PML2552 Logic Diagram) is used to bypass any one of these DFFs. The flip-flops are all active in an unprogrammed device. 3. As combinatorial outputs. By programming the bypass (BFBx) fuse of any one of the DFFs, the flip-flop(s) is bypassed. The 1/0 pin can then be used as a combinatorial output. 4. As Internal foldback DFFs or foldback NAND gates. When the 1/0 pin is used as an input, the output macro can be used as an internal DFF or a foldback NAND term. If the bypass fuse is programmed, the macro will act as a foldback NAND term. Otherwise it will act as an internal DFF.
The 8 bidirectional pins (BO-B7) can be used as either combinatorial inputs or outputs with programmable polarity. The Exclusive-OR polarity gates are non-inverting in the unprogrammed state.
The NAND signal labeled 'OIT' (Output Disable) shown on the PML2552 logic diagram is used for the Power Down mode operation. This signal disables the outputs when the device enters the Power Down mode and SCI is high.
Clock Array
The 20 buried JKFFs can be clocked through the 'Clock Array'. The Clock Array consists of 11 NAND terms. Ten of these terms are connected to the clock inputs of the Bank A flip-flops that can be clocked individually. One NAND gate is connected to Bank B flip-flops that have a common clock. There are 18 inputs to the clock array. Four come directly from the input pins (with programmable polarity), 4 inputs are from 4 NAND gates connected directly to the folded NAND array. 1O inputs are from the Q outputs of the JKFFs with clear.

October 22, 1993

470

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

SCAN TEST FEATURE
With the rise in the ratio of devices on a chip to the number of 1/0 pins, Design For Testability is becoming an essential factor in logic design methodology. The PML2552 incorporates a variable length scan test feature which permits access to the internal flip-flop nodes without requiring a separate external 1/0 pin for each node accessed. Figure 2 (Scan Mode Operation) shows how a scan chain is implemented through the 20 buried JKFFs and 16 output DFFs. Two dedicated pins, SCI (Scan In) and SCM (Scan Mode), are used to operate the scan test. The SCM pin is used to put the circuit in scan mode. When this pin is brought to a logic "1 ", the circuit enters the scan mode.

In this mode it is possible to shift an arbitrary test pattern into the flip-flops. The SCI pin is used to input the pattern. The inverted outputs of flip-flops DO- 015 are observable on pins 1/00 -1/015.
The following are features and characteristics of the device when in Scan Mode: 1. CKE1 is the common scan-clock for all
the flip-flops when in scan mode. CKE1 overrides all clock resources of normal operational mode.
2. The Preset (PR) and Clear (CL) functions of the flip-flops are disabled.
3. Scan overrides the bypass fuse of the flip-flops. This means that all the

bypassable DFFs remain intact during scan operation even though they may have been bypassed during normal operation.
4. To observe the SCAN data, the output buffers must be enabled by the Output Enable (tri-ctrl) terms.
5. The outputs of the flip-flops are complemented on pins 1/00 -1/015.
6. All external inputs to flip-flops in the scan chain are disabled when the device enters the scan mode.
7. Blowing the security fuse does not disable the Scan Test feature.

SCAN MODE OPERATION

SCOUT

11015

1/00 11014

1101 11013

1102 11012

1103 11011

1104 11010

1105 1/09

1106 1108

1107

(COMMON CLOCK (CKE1) FOR ALL FLIP-FLOPS WHEN IN SCAN MODE)

Figure2.

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

SCAN TEST STRATEGY
The scan test pattern is design dependent and the user must make considerations for Design For Testability (DFT) during the initial stages of the design. A typical test sequence is to pre-load (i.e., enter a state); revert to normal operation (i.e., activate the next state transition); go back to scan mode to check the result. Note that the scan test feature available in the PML2552 is a variable length scan chain. The DATA entered at SCI (JKCL9) can be accessed anywhere between 21 clock cycles (at 1/00) to 36 clock cycles (at 1/015). For the strategy discussed here, DATA is read out after 36 clocks at 1/015 {i.e., D 15). The following operation sequence suggests a possible scan test method.
A conservative test policy demands proof that the test facility is working. Thus, to prove Scan Chain holds and maintains correct data:
a. Fill chain with several patterns (for example, all ones and all zeros).
b. Retrieve same patterns.

5. To read result of the state transition, re-enter scan and apply the scan clock (CKE1 ). The result of the state transition in JKCL9 will be available at SCOUT (J/015) after 36 clocks. The results can be stored in a user defined test memory buffer in inverted logic representation.

6. As the results are being read and stored, new 'Test Data' can be entered via SCI.
7. Repeat for all test patterns of interest.
8. Figure 3 (FLOW_CHART) depicts a flow chart version of the test sequence.

TEST INTEGRITY OF SCAN CHAIN. ASSUME 36-BIT SCAN CHAIN,
IF LESS, SET COUNT= LENGTH-1.
SETSCM= 1 SET COUNT= 35
TEST DATA READY AT 'SCI" INPUT
APPLY SCAN CLOCK

The user is responsible for managing an external test memory buffer for applied vectors and results, as part of the test equipment.
1. Parallel readout of 1100 - 1/015 is possible, but assume only 1/015 is used for this strategy.
2. The first DATA entered at SCI {or JKCL9) will be the content of D15 after 36 clocks. This DATA will be inverted at the output pin 1/015 (i.e., SCOUT). The last DATA entering the scan chain will be the content of JKCL9. Thus, the scan chain resembles a first-in-first-out shift register with inverted outputs (1100 - J/015).
3. 'Test Data' is read in at the SCI input and read out of the SCOUT output pin (1/015). To enter 'Test Data':
a. Put device in Scan Mode by applying the scan control signals {SCM=1).
b. Clock device with scan clock (CKE1).
c. Apply consecutive serial test vectors.
d. Read back results as new 'Test Data' {States) are applied. The first 36 outputs read at SCOUT {J/015) are random {'old') data {e.g., remnant of Step 1).
e. Apply 36 'Test Data' until the chain is full.
4. To apply 'Test Data' (States), exit Scan Mode and apply on system clock together with any other possible test vectors.

READ OUT RESULT AND STORE IN TEST MEMORY'
COUNT= COUNT -1
SELECT NEXT TEST DATA AND APPLY TO SCI
SETSCM=O (NORMAL OPERATING MODE)
APPLY SYSTEM CLOCK AND ANY EXTERNAL TEST VECTORS
RESULT READY FOR OUTPUT ON NEXT 36 CLOCK CYCLES AS NEW TEST VECTOR IS LOADED
NoTE:
1. The first 36 outputs are random ('OLD') dala.
Figure 3. FLOW_CHART

October 22, 1993

'17?

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

A Simple Example
Assume the last three cells of the scan chain (JKCL9, JKCLS, JKCL7 in Figure 4 contain a 3-bit up counter. Our test vector will be a single clock applied to the counter. Suppose we wish to first check the State 5(i.e., 101) to State 6 (i.e., 110) transition, then the State 3 (i.e., 011) to State 4 (i.e., 100) transition. Assume the scan chain has been pre-verified and we may begin. Enter scan mode (set SCM=1)I apply 36 bits
in sequence so that the value 101 (i.e., State
5) resides in the last three cells. Exit scan mode (set SCM=O) and apply a single clock to the counter. Now the value 110(i.e., State 6) resides in the last three cells. Re-enter scan mode (set SCM=1) and read back 36 bits from position 1/015.. Note that the outputs are complemented and are also read back in the reverse order. Therefore the value for STATE 6 read at 1/015 will be 100 which is the complement of STATE 6 (110) read in the reverse order. As this is being read back, apply a new state, serially equal to the value 011 (i.e., State 3). This state should be loaded on the last three clock cycles during which STATE 6 is being read back at 1/015. After STATE 3has been loaded (and STATE 6 read back), exit scan mode and apply a single clock which will invoke the STATE 3(i.e., 011) to STATE 4 (i.e., 100) transition. Re-enter scan mode and read back 36 bits at 1/015. The last three bits should contain HO which is the complement of State 4 read in the reverse order. Figure 4 (SCAN_EXAMPLE) shows a flow diagram of this example. Note that the States will always be complemented and read back in the reverse at 1/015. Other sequences may be applied in the same manner. A possible alternative to this example is to read back the output states at 1/00 (DO) instead of 1/015 (JKCL9). This will allow the outputs to be read back after 21 clock cycles rather than the 36 used in the above example.
October 22, 1993

SCI JKCL9

JKCL8

JKCL7

STATES

JKCL.6

EXIT SCAN MODE (SCM = 0)
AND APPLY COUNTER CLOCK

···

ENTER SCAN MODE
(SCM =1)

SCI JKCL9

JKCLB

JKCL7

STATE6

···
JKCL.6

APPLY 33 SCAN CLOCKS

···

015

014

013

D12

STA TE 6 IN REVERSE ORDER OUTPUTS COMPLEMENTED

STATE 3 (011) WILL BE LOADED ON NEXT 3 CLOCKS

SCI JKCL9

JKCLB

JKCL7

STATE3

···
JKCL6

EXIT SCAN MODE (SCM = 0) AND APPLY COUNTER CLOCK

ENTER SCAN MODE (SCM: 1)

SCI JKCL9

JKCL8

JKCL7

STATE4

· ··
JKCL.6

APPLY 33 SCAN CLOCKS

11014= 1

l/013=0

l/012=X

···

D15

D14

D13

D12

STATE 4 IN REVERSE ORDER OUTPUTS COMPLEMENTED

Figure 4. SCAN_EXAMPLE

473

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

POWER DOWN
The PML2552 offers the user controlled capability of putting the device to "sleep"
where power dissipation is reduced to very
low levels. When brought lo a logic "1 ", the PD pin freezes the circuit while reducing the power. All data is retained. This not only includes that of the registers, but also the state of each foldback gate. For those cases where it is desirable to 3-State the outputs, that can be accomplished by raising the SCI pin to a logic "1".
There is one point that should be noted while the circuit is in its power-down mode. The switching of any external clock pin will cause a disruption of the data. All clocks must be frozen before the circuit goes into powerdown and stay that way until it powered back up. Clocks that are internally generated and feed the clock array are automatically stopped by the power-down circuitry. Any other input can toggle without any loss of data.
NOTE: 1. During power down, external clocks (CKA,
CKBICKC, CKE1, CKE2) should not change. 2. SCM must be "O" as in normal operation mode. 3. External clock recovery time (low-to-high) is 60ns (high-speed) and 70ns (standard) after the device is powered up. 4. Power Down Timing Diagrams on pages 17 and 18 are for combinatorial operation only.

DEVELOPMENT TOOLS
The PM2552 is supported by the Philips Semiconductors SNAP software development package and a multitude of hardware and software development tools. These include industry standard PLD programmers and CAD software.
SNAP
Features · Schematic entry using DASHTM 4.0 or
above or OrCADTM SDT Ill
· State Equation Entry
· Boolean Equation Entry
· Allows design entry in any combination of above formats
·Simulator - Logic and fault simulation - nming model generation for device timing simulation - Synthetic logic analyzer format
· Macro library for standard TTL and user defined functions
· Device independent netlist generation
· JEDEC fuse map generated from netlist
SNAP (Synthesis, Netlist, Analysis and Program) is a versatile development tool that speeds the design and testing of PML. SNAP

combines a user-friendly environment and powerful modules that make designing with PML simple. The SNAP environment gives the user the freedom to design independent of the device architecture.
The flexibility in the variations of design entry methodologies allows design entry in the most appropriate terms. SNAP merges the inputs, regardless of the type, into a highlevel netlist for simulation or compilation into a JEDEC fuse map. The JEDEC fuse map can then be transferred from the host computer to the device programer.
SNAP's simulator uses a synthetic logic analyzer format to display and set the nodes of the design. The SNAP simulator provides complete timing information, setup and hold-time checking, plus toggle and fault grading analysis.
SNAP operates on an IBM® PCIXT, PC/AT, PS/2, or any compatible system with DOS 2.1 or higher. A minimum of 640K bytes of RAM is required together with a hard disk.
DESIGN SECURITY
The PML2552 has a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary design implemented in the device cannot be copied or retrieved.

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

PARAMETER

RATINGS

UNIT

Vee

Supply voltage

+7

Voe

V1N

Input voltage

+5.5

Voe

VouT

Output voltage

+5.5

Voe

l1N

Input currents

-30 to +30

mA

lour

Output currents

+100

mA

lamb

Operating temperature range

0 to +75

oc

Tst9

Storage temperature range

-65 to +150

oc

NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those
indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS
TEMPERATURE Maximum junction
Maximum ambient Allowable thermal rise ambient to junction

c 1so0
75°C 75°C

DASH is a trademark of Data 110 Corporation. OrCAD is a trademark of OrCAD, Inc. IBM is a registered trademark of International Buslness Machines Corporation.
October 22, 1993

474

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

DC ELECTRICAL CHARACTERISTICS
0°C -< Tamb s +75°C, 4.75V s Vee<- 5.25V

SYMBOL

PARAMETER

TEST CONDITIONS

Input voltage

V1L

Low

V1H

High

Vee= MIN Vee=MAX

Output voltage

Vol

Low

Vee= MIN, loL = 5mA

VoH

High

Vee= MIN, loH = -2mA

Input current

l1L

Low

l1H

High

V1N=GND V1N =Vee

Output current

lo(OFF)

Hi-Z state

VouT =Vee VouT = GND

loH

Output High

loL

Output Low

Vee= MIN, Your= 2.4V Vee= MIN, VouT = 0.45V

los

Short-circuits

Your= GND

Ice

Vee supply current

Vee= MAX, No load CMOS input2

f= 1MHz

TTLinput3

lss

Standby Vee supply current

Vee= MAX, No load

CMOS input

PD= V1H

TTL input

Capacitance

C1N

Input

Cs

1/0

Vee = 5V, Tamb = +25°C, V1N = 2.0V Vee= 5V, Tamb = +25°C, V10 = 2.0V

NOTES: 1. All typical values are at Vee = 5V, Tamb = +25°C. 2. CMOS inputs: V1L = GND, V1H =Vee. 3. TTL inputs: V1L = 0.45V, V1H = 2.4V. 4. All voltage values are with respect to network ground terminal. 5. Duration of short-circuit should not exceed one second. Test one at a time. 6. t.lce vs. Frequency = 4mA/MHz max.

TEST LOAD CIRCUITS

Vee

c1 yc2

IA

By

INPUTS

ie OUT
Bw Bz
Bx GND Ox

NOTES: C1 and C2 are to bypass Vee to GND.

=

Test Load R1 = 750Q, R2 = 442.Q, CL= ~F (CL"' 5pF for Output Disable)

0°C .s. Tamb.S. +75"C, 4.75V s. Vcc.s.5.25V

R1

R2

CL

OUTPUTS
=

MIN -0.3 2.0
2.4

LIMITS TYP1

MAX

UNIT

0.8

v

Vee+ 0.3

v

0.45

v

v

-10

µA

10

µA

10

µA

-10

µA

-2

mA

5

mA

-100

mA

60

1006

mA

65

1206

mA

1.0

10

mA

1.5

10

mA

8

pF

16

pF

VOLTAGE WAVEFORMS
+3.0V----~ 90"k
w J_Ij1..JI.c~
~ -J.~ 1~5nsL OV
MEASUREMENTS: All circuit delays are measured at the+ 1.SV level of
inputs and outputs, unless otherwise specified. Input Pulses

October 22, 1993

475

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

MACRO CELL AC SPECIFICATIONS
Min: 0°C, 5.25V; Typ: 25°C, 5.0V; Max: 75°C, 4.75V (SNAP Resource Summary Designations in Parentheses)
Input Buffer (DIN552, NIN552, BDIN55, BNIN552 CDIN552, CNIN552, CKDIN552, CKNIN552, IDFF552*)
I~

PARAMETER

LIMITS

SYMBOL

To

From

PML2552-35

PML2552-50

(Output)

(Input)

MIN TYP MAX MIN TYP MAX

lpHL

x

lpLH

x

I

5

7

10

7

10 15

I

5

7

10

7

10 15

lpHL

y

tPLH

y

I

5

7

10

7

10 15

I

5

7

10

7

10 15

· When D flip-flop is bypassed. Input Pins: 8-14, 16, 17, 20, 22-24. Bidirectional Pins: 1-3, 5-7, 46-48, 50-54, 57-64, 67, 68. Bypassed D flip-flop at pins 26, 28-31, 3~5. 37, 39-45.

Internal NANO of Main Array (FBNAND, NANO)

x D

y

SYMBOL
lpHL lpLH

PARAMETER

To

From

(Output)
y y

(Input)
x x

LIMITS

LIMITS

PML2552-35

PML2552-50

MIN TYP MAX MIN TYP MAX

10 15 20 12 18 25 10 15 20 12 18 25

UNIT ns ns ns ns
UNIT ns ns

SYMBOL
lpHL tPLH

Internal NANO of Clock Array (NANO)

x D

y

PARAMETER

To

From

(Output)
y y

(Input)
x x

LIMITS

LIMITS

PML2552·35

PML2552·50

MIN TYP MAX MIN TYP MAX

5

7

10

7

10 15

5

7

10

7

10 15

UNIT
ns ns

October 22, 1993

476

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

MACRO CELL AC SPECIFICATIONS (Continued)
Min: 0°C, 5.25V; Typ: 25°C, 5.0V; Max: 75°C, 4.75V (SNAP Resource Summary Designations in Parentheses)

3-State Output with Programmable Polarity (TOUT552 + EXOR552}

--~F?D=tL ~

In

Out

D

Connection

BFCx

7

l71

6

l7

5

/'

4
l 3
15
~ 2
<I

1L
171
l7

1

J7

IA 0
-1

-2 0 20 40 60 80 100120140160180200
OUTPUT CAPACITANCE LOADING (pF)

L\.tpD vs Output Capacitance Loading (Typical}

PARAMETER

SYMBOL

To

From

(Output}

(Input}

lpHL

Out

lpLH

Out

loE4

Out

loD4

Out

Bidirectional Pins: 46-48, 50-54.

In In
Tri-Ctrl Tri-Ctrl

LIMITS

PML2552-35

PML2552·50

MIN TYP MAX MIN TYP MAX

12 18 25 17 25 35 12 18 25 17 25 35

5

7

10

7

10 15

5

7

10

7

10 15

UNIT
ns ns ns ns

1/0 Output Buffer with 3-State Control, OFF Bypassed (TOUT552 + NANO}

Tri-Ctrl
L-'
In

K
Bypassed

7

l71

6 5

x 17

4
.~ 3
15
<i 2

IA
171
f71

1

17

0 ,...,

Out

-1

-2 0 20 40 60 80 100 120140160180200
OUTPUT CAPACITANCE LOADING (pF)

L\.tpo vs Output Capacitance Loading (Typical}

PARAMETER

SYMBOL

To

From

(Output}

(Input}

tPHL

Out

In

lpLH

Out

In

loE4

Out

loD4

Out

1/0 Pins: 1-3, 5-7, 57-64, 67, 68.

Tri-Ctrl Tri-Ctrl

Notes on page 481.

LIMITS

PML2552-35

PML2552-50

MIN TYP MAX MIN TYP MAX

12 18 25 17 25 35 12 18 25 17 25 35

5

7

10

7

10 15

5

7

10

7

10 15

UNIT
ns ns ns ns

October 22, 1993

477

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

MACRO CELL AC SPECIFICATIONS (Continued) (SNAP Resource Summary Designations in Parentheses) D FLIP-FLOP
Output OFF Used Internally (ODFF552)

ID

D

CKE~ Q

-~~

SYMBOL
fcKE twcKE High twcKE Low tsEruplD IHoLD/D
SYMBOL
tPLH tPHL

PARAMETER
Flip-flop toggle rate Clock HIGH Clock LOW ID setup time to CKE ID hold time to CKE

PARAMETER

From

To

(Input)

(Output)

CKEi

Q

CKEi

Q

LIMITS

PML2552·35

PML2552·50

MIN TYP MAX MIN TYP MAX

50

35

10

14

10

14

15

20

4

6

UNIT
MHz ns ns ns ns

LIMITS

PML2552·35

PML2552·50

MIN TYP MAX MIN TYP MAX

10 15 20 14 20 25 10 15 20 14 20 25

UNIT
ns ns

October 22, 1993

478

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

MACRO CELL AC SPECIFICATIONS (Continued) (SNAP Resource summary Designations in Parentheses) D FLIP-FLOP (Continued)
Input and Output (IDFF552 & ODFF552)

INPUTS

OUTPUTS

CK

D

a

0

L x ao ao

i

H

H

L

i

L

L

H

NOTE:
a. Oo. Oo represent previous stable condition of 0.

lfDA, ltDB CKA, CKB, CKC

Qt---------
11.__ _ _ _ __

=
Tri-C1rl - - - - - - ,

/D Q

SYMBOL
fcKA, CKB, CKC tw CKA, CKB, CKC High tw CKA, CKB. CKC Low lsETUP I/DA, I/DB tHOLD I/DA, I/DB fcKE twcKE High twcKE Low lsETUP ID !HOLD ID

LIMITS

PML2552-35

PML2552-50

MIN TYP MAX MIN TYP MAX

50

35

10

14

10

14

5

7

5

7

50

35

10

14

10

14

15

20

4

6

=
UNIT
MHz ns ns ns ns
MHz ns ns ns ns

z v 171

i 3
0
::- 2
<l

IL1
x v~

-1 L

-2 0 20 40 60 80 100120140160180200
OUTPUT CAPACITANCE LOADING (pF)

Atpo vs Output Capacitance
Loading (Typical)

SYMBOL
IPLH IPHL IPLH tPHL

PARAMETER

From
(Input)
CKA, CKB/CKC i CKA, CKB/CKC i

To (Output)
a.a a.a

CKEi

Out

CKE t

Out

LIMITS

PML2552-35

PML2552-50

MIN TYP MAX MIN TYP MAX

5

7

10

7

10 15

5

7

10

7

10 15

12

18

25

17

25

35

12

18

25

17

25

35

UNIT
ns
ns ns ns

October 22, 1993

479

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

MACRO CELL AC SPECIFICATIONS (Continued) (SNAP Resource Summary Designations in Parentheses) JK FLIP-FLOPS

(JKPR552)

INPUTS

PR

CK

J

K

L

x

x

x

H

i

L

L

H

i

H

L

H

i

L

H

H

i

H

H

H

L

x

x

OUTPUTS

Q

ll

H

L

ao ao

H

L

L

H

TOGGLE
l Oo Oo

(JKCL.552)

INPUTS

er CK

J

K

L

x

x

x

H

i

L

L

H

i

H

L

H

t

L

H

H

t

H

H

H

L

x

x

OUTPUTS

Q

a

L

H

ao Oo

H

L

L

H

TOGGLE
ao l ao

/J

Q

CK1

/K

SYMBOL
fcK1 fcK2 twcK 1 High twcK1 Low twcK2 High twcK2 Low tsETUP /J, /K tHow/J, /K twPR Low twCL Low

PARAMETER
CK1 toggle frequency CK2 toggle frequency CK1 clock HIGH CK1 clock LOW CK2 clock HIGH CK2 clock LOW /J, /K setup time to CK1, CK2 /J, /K hold time to CK1, CK2 Preset Low period Clear Low period

/J

Q

CK2

IK

LIMITS

PML2552·35

PML2552·50

MIN TYP MAX MIN TYP MAX

50

35

50

35

10

14

10

14

10

14

10

14

27

35

0

0

10

14

10

14

UNIT
MHz MHz
ns ns ns ns ns ns ns ns

SYMBOL
tPLH tPHL lpLH tPHL tPLH IPHL

From (Input)
CK1,2 CK1,2
PR PR
CL CL

PARAMETER
To
(Output)
a.a a.a a.a a.a a.a a.a

LIMITS

PML2552-35

PML2552·50

MIN TYP MAX MIN TYP MAX

2

3.5

5

3

5

7

2

3.5

5

3

5

7

12

18

25

17

24

30

12

18

25

17

24

30

12 18 25 17 24 30 12 18 25 17 24 30

UNIT
ns ns ns ns ns ns

October 22, 1993

480

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

AC ELECTRICAL CHARACTERISTICS
0°c s Tamb s +75°C, 4.75V s Vee s 5.25V, Vpp =Vee.
R1 = 7500, R2 = 4420, CL= 5pF for Output Disable) (See Test Load Circuit Diagram)

LIMITS

SYMBOL

PARAMETER

PML2552-35

PML2552-50

UNIT

MIN

MAX

MIN

MAX

Scan mode operation1

tseMs lseMH

Scan Mode (SCM) Setup time Scan Mode (SCM) Hold time

15

15

ns

25

30

ns

tis

Data Input (SCI) Setup time

5

5

ns

t1H

Data Input (SCI) Hold time

5

5

ns

fcKO fcKH

Clock to Output (110) delay Clock High

30

40

ns

10

15

ns

fcKL

Clock Low

Power down, power up2

10

15

ns

tl

Input (I, bypassed I/DA, I/DB, 1/0, B) setup time before power down

40

50

ns

t2

Input hold time

30

35

ns

t3

Power Up recovery time

60

70

ns

ti

Output hold time

0

0

ns

t5

Input setup time before Power Up

20

25

ns

!oE

SCI to Output Enable time3

40

50

ns

!oD

SCI to Output Disable time3

40

50

ns

Is

Power Down setup time

10

15

ns

t1

Power Up to Output valid

70

80

ns

Power-on reset

tPPR1

Power-on reset output register (Q = 0) to output (110) delay

10

15

ns

tPPR2

Power-on reset input register (Q = 0), buried JK Flip-Flop (Q = 0) to output (B, bypassed 1/0) delay

40

50

ns

NOTES:
1. SCM recovery time is 50ns after SCM operation. 50ns after SCM operation, normal operations can be resumed.
2. Timings are measured without foldbacks.
3. Transition is measured at steady state High level (-500mV) or steady state Low level (+500mV) on the output from 1.5V level on the input
with specified test load (R 1 = 7500, R2 = 4420, CL= 5pF). This parameter is sampled and not 100% tested. 4. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S 1is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output voltage of Vr = (VoH - 0.5V) with S 1 open, and Low-to-High impedance tests are made to the Vr = (Vol+ 0.5V) level with S 1 closed.

October 22, 1993

481

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

TIMING DIAGRAMS

~-{~

1.SV +3V
ov

·scM

,....---+---t-sc-M-H .. +3V

i'

SCI

1.SV

ov
_ ~H __,_ _ ~ _....,.,___

+3V CKE1
ov

1/0

1.SV

1.sv

Yot.

Sean Mode Operation

------+ZV

I, BYPASSED I/DA, I/DB, 1/0, B

1.SV

1.SV

1.SV

·2 Is ·a=1.____ :v ··t :t- ~

-1- . I

-SY_______ \

1.SV

I

PD

_-,,---t~ I

~ ·PD1

ov

B,l!O -__·.s.*.r.,~.,-'-6~r).~-_t,o.-HD,-,~.-,1I-GM"-"PHE-D-~t:(~c-..______~ ~ VVoOHL

______,f SCI

1.SV

\ 1.SV

+3V

ov

Power Down, Power Up Input (old) Ready Before Power Up

October 22, 1993

482

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

TIMING DIAGRAMS (Continued)

·~--~·=t~~~~

+3Y ov

I f PD

uv

-~ I

B, llO

I 1.5

SCI

f'6r~ 1.5V

+3V

\ 1.svl

~-,....-~.-~-

ov

VoH

1.sv

VOL

+3V

ov

Power Down, Power Up Input (new) Ready After Power Up

I, BYPASSED I/DA, I/DB, llO, B PD

~--- +3Y

1.5Y

1.5

OV

'PD
+3Y

OV

October 22, 1993

8,1/0 Voi.
+3Y
SCI ov
PowerDown,PowerUp Input (new) Ready Before Power Up

__. ~~4. I~ 5-Y--------------- +SY Vee ~ 1 -'P-Pn1-- J-------ov

110 ~

,......- 1 . - s v - - - - - - - - - - - VoH

-

'PPR2~

Vol

a,110 ~r-1.-sv----------

VoL
Power·On Reset

483

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

SNAP RESOURCE SUMMARY DESIGNATIONS

@~q~ f~~®M 8 "'-1-----,
00
~·

BO-B7

~·~~··· l/DA>--"r'--1 D Q f--'11-----l----11----+-----+--+---+--+--+--+---+---li----lf-

CKAl)--',

.L

---J> (S) :
BFAx O

1-_--1;_-_-_-i+---_-_--1;_-_-_-++---_-_-_-:_-_-_--1:_-_-_-++---_-_-i-+---_-_+,_-_-_++----_-;_-_-_4;_-_-_-iJ.·.-.-.-._~--1-_._r-_)-

-: -+---+--+---+----+--+--+----1'---+--+--+---;~mi~Mi?

·mB-~-.87r~,B~FDA<x~~i_I~--l:::·r-.;:_:~_J+---+--+-------11----+----l---+-+--l-----lr----l----ll-

· ---11----+----l--+-----+--+---+--+--+--+---+--~····mNiiW
--+--+---+--+----+--+--+--1----+-+--+--iji.l\~~
·;~- __,l----+----1--+-----+--+---+--+--+--+---+--
llCKBIC:K:C ::~::~~~:~~=~=~~!·j·-lji_---ll----+-----+---+---+--+---+---+--+---+---1--

1108-11015 1100-1107

l/CKQ>--t-+-"3-"-;.<----"l ll1---t----11-------+--+---t--+---+---+--l---t----+-

10

c_fit&@J_

~~111-. -.--.·.·.--.--.--.·.·.·-.·.·.·-.·.·---+-_,>---

1 2

ar1.~·---+--+--

CKE2

8 y

fftiAi',lif)

./

Oo~

/

October 22, 1993

484

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2552

ERASURE CHARACTERISTICS (For Quartz Window Packages Only)
The erasure characteristics of the PML2552 device is such that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000 - 4000A range. Data shows that constant exposure to room level fluorescent lighting could erase a typical PML2552 in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. If the PML2552 is to be exposed to

these types of lighting conditions for extended periods of time, opaque labels should be placed over the window to prevent unintentional erasure.
The recommended erasure procedure for the PML2552 is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15Wsec/cm2. The erasure time with this dosage is approximately 30 to 35 minutes using an ultraviolet lamp with a 12,000µW/cm2 power rating. The device should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose a CMOS EPLD can be

exposed to without damage is 7258Wsec/cm2 (1week@12,000µW/cm2). Exposure of these CMOS EPLDs to high intensity UV light
for longer periods may cause permanent
damage.
The maximum number of guaranteed erase/write cycles is 50. Data retention exceeds 20 years.
PROGRAMMING/SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 1O (Third-party Programmer/ Software Support) of this data handbook for additional information.

October 22, 1993

485

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

FEATURES
· Wide gates for efficient product term use
· Multiple 1/0 pins for 16--32 bit buses or up to 32-bit data flow
· Multiple 1/0 pins for multiple-port data handling
· Multiple clocks for independent state machines and storage banks
· 100% connectible, no place and route restrictions
· Erasable and one time programmable versions available
·Scan test
· Low CMOS power dissipation =
525mWmax. · Power down mode (52mW max.)
· Power on reset
· Security fuse for copy protection
· Supported by advanced SNAP and SLICE development systems

· Multiport memory control and arbitration (cache, DRAM, VRAM, etc.)
· Intelligent instrumentation (data acquisition, testers, medical equipment, etc.)
· Industrial control (process control, motor control, engine control, etc.)
·Communication network control (LAN, Ethernet, T1, TDMA, etc.)
· General purpose logic integration · Laptops, pocket computers, and handheld
instruments · Low-end gate array replacement for quick
prototyping
SNAP DEVELOPMENT SYSTEM
· Supports third-party schematic entry formats
· Versatile EDIF-compatible netlist format for design portability
· TTL macro library for automatic mapping · Logic, timing, and fault simulation

PERFORMANCE
· 35ns max. pin-to-pin for 32-bit decoders
· 40ns max. internal, 55ns max. pin-to-pin for 16-bit multiplexers

· Automatic test vector generator
· Espresso logic minimizer · Boolean equation extractor from JEDEC
fusemap

· 33MHz max. throughput for 16-bit latches

· 18-50MHz max. for 10-bitcounters · 31 MHz max. for 10-bit shift registers · 15ns (typ.) delay for internal NANDs · 50MHz max. flip-flop toggle rate
APPLICATIONS
· Bus interface and control (microchannel, VME, NuBus, etc.)
· Microcomputer peripheral interface and control (printers, SCSI, hard disk drives, etc.)

DESCRIPTION
The Philips Semiconductors family of Programmable Macro Logic is optimized for handling wide buses, wide datapaths, and multiple-port applications with the highest throughputs among high density PLDs and FPGAs. The PML2852 now expands Philips Semiconductors CMOS PML product offering into the 32-bit arena. Fabricated with a high-performance EPROM process, the PML2852 is ideal in today's bus interface control, microprocessor peripheral control, memory interface, communications, instrumentation, and industrial control. It is capable of replacing large amounts of TTL

ORDERING INFORMATION

DESCRIPTION

tpo (MAX)

84-pin Plastic Leaded Chip Carrier

35ns

84-pin ·J" Leaded Ceramic Cerquad Package

35ns

84-pin Plastic Leaded Chip Carrier

sons

84-pin "J" Leaded Ceramic Cerquad Package

50ns

SSI and MSI logic, and literally integrates a complete custom microcontroller.
The PML2852 incorporates the folded NAND array architecture, which provides 100% connectivity to eliminate the routing restrictions associated with other high density PLD/FPGA architectures. The array of wide-input NAND gates enables the designer to implement any wide-gate logic function, from decoders to multiplexers, with no more than two gate-level delays. It also allows implementation of multiple levels of logic within the chip, without wasting 1/0 pins. Its flexible and potent flip-flop building blocks provide for high throughput data storage, high speed state machines, and fast counters.
The PML2852 also incorporates two unique features: scan test and power down. With user-controlled scan test, the PML2852 significantly reduces system functional test time by providing access to all of its internal registers. In the user-controlled power down mode, the PML2852 power dissipation is reduced to a mere 52mW, making it ideal for laptop or pocket computers and handheld instruments.
Thanks to its high density and its flexible architecture, the PML2852 provides instant gate array capabilities for all general purpose logic integration. As such, the PML2852 eliminates the NAE costs, risks, inventory problems, and hard to use design tools associated with semicustom and full custom approaches. It allows the designer to quickly bring concepts to silicon for faster learning cycles and a much shorter time to market. Functional prototypes are available within minutes.
The SNAP development software is designed to fully exploit the flexibility and density of the PML2852. It accepts a variety of design entry formats, including schematic, logic equations, and state equations in any combination for maximum flexibility. Its powerful features, but ease of use, allows literally push-button operation.
Together, the PML2852 and SNAP constitute the designer's personal desktop silicon foundry.

ORDER CODE PML2852-35A PML2852-35KA PML2852-50A PML2852-50KA

DRAWING NUMBER 0399F 1551 0399F 1551

NuBus is a trademark of Texas Instruments, Inc. October 22. 1993

486

853-158611164

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

PIN CONFIGURATION
A and KA Packages

FUNCTIONAL BLOCK DIAGRAM

16

INPUT

DFUP.fl.OPS

____&

13 DEDICATED

.._ A

INPUTS ...

32 33

54 S3

Pin Function 1 '[,05 2 1/04 3 1/03 VCC1 1/02 6 1/01 7 1/00 03 02 10 01 11 00 12 18 13 17
14 16 15 15 16 14 17 13 18 12 19 VSS1 20 21 10 22 SCM 23 SCI 24 llCKD3 25 VCC2 26 l/CKD2 27 llCKD1 28 l/CKBICKC

Pin Function 2\l PD
3p llDB7
31 I/DBS 32 I/DBS
33 vccs
34 l/DB4 35 t/083 36 l/DB2 37 l/DB1 38 l/DBO 3B l/DA7 40 VSS2 41 I/DAG 42 llDA5 43 llDA4 44 CKA 45 llDA3 46 VCC3 47 llDA2 48 l/DA1 49 I/DAO 50 015 51 014 52 013 53 012 54 011 55 010 56 09

Pin Function 57 08 58 B7 59 BG 60 BS 61 VSS3 62 B4 63 B3 64 B2 65 B1 66 BO 67 VCC4 68 CKE2 69 11015 70 1/014 71 07 72 06 73 05 74 04 75 11013 76 1/012 77 1/011 78 l/010 79 1109 80 l/08 81 CKE1 82 VSS4 83 1/07 64 1106

p

R

~

0 G R A M

M

A

FOLDED

B

NANO

L

ARRAY

E

B

I

N

T

E

R
c

0

N

N

10

E

JK FLIP-FLOPS

c

WITH

T

COMMON

CLK
c

10 JK FLIP-FLOPS
WITH DISTINCT
CLKS D
Figure 1.

Product specification
PML2852
160UTPUT DFLIP·FLOPS
E
24 Bl·DIRECTIONA
I/Os F
16 DEDICATED OUTPUTS G

October 22, 1993

487

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

LOGIC DIAGRAM

llDAO-llDA7 8

A
~

4 ::EE 1

(8)
BFA(0-7~

fG l/~B7JL
L......> ) l1

1

BFA(8-15F

l/CKB/CKC
!0-18
l/CKDIl/CKD3

-l,- :> ~
~ 2 ~ 32

1 3 8 8

L

[Jllta BJ1 10 10 10

....__

K J
CL(IO)

~ 1
J p

20
" :-7 ..L 20

27
1000

3 ;i;:
--1 i
4

~r=G>

4 OD

i4

41 ~ OD

1
4

?.!l
OD

.---1-----0~

~ Oii

r--E>~ r--000~
~C(0-3)
rE>~
rG:> OD 4,

....FC(4-7)

14
'"V
4
'"V
1.....4
v 4
+ -;?

G 00-03
,.2...!.:.:.g..7> .~ ......1 ..>
012--015 F
3

~
<' -

~.

1108-l/015 (SCAN OUT)

<' 8

1~ ~07

ri>-8 (SCAN OUT)

ri 8

;~c&~~ 8

OD

D

8

1 1

D BFB(0-7) -

(8)

(8)

OD

i\.J ....

....

BFB(S-15

~

(SCA..N...~...K..)

8

8

1 00~1

October 22, 1993

488

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

STRUCTURE
· 112 possible foldback NAND gates: - 96 internal NAND - 16 from the 110 macros
· 114 additional logic terms
· 53 possible inputs (with programmable polarity) - 29 dedicated inputs - 24 bidirectional I/Os
· 24 bidirectional pins
· 16 dedicated output pins
· 52 flip-flops
· 40 possible outputs with Output Enable control (8 with programmable polarity)
· Multiple independent clocks
· 20 Buried JK-type flip-flops with foldback (JKFFs): - 10 JKFFs with one shared preset signal and one shared clocked signal originating from the clock array. - 10 JKFFs with 10 independent clock signals originating from the clock array and 1Oindependent clear signals
· 258 inputs per NAND gate
· Bypassable Input D-type flip-flop (DFFs)/Combinatorial Inputs: - 16 DFFslcombinatorial inputs - DFFs clocked in two groups of eight - DFFs not bypassed in unprogrammed state - Independent bypass fuse on each DFF
· lnputs/bypassable D-type flip-flop outputslfoldback NAND gates: - 16 output DFFs/combinatorial inputs/outputs with individual Output Enable control - DFFs clocked in two groups of eight - DFFs not bypassed in unprogrammed state - Independent bypass fuse on each DFF - The DFF can be used as an internal DFF or an internal foldback NAND gate.
· Combinatorial inputs: - 9 dedicated inputs to the NAND array - 3 inputs optional to NAND array and/or clock array - 1 input optional to NAND array and/or clock array, and/or clock of Input D Flip-Flops (Group B)

· Separate clock array:
- Separate clock array for JKFFs clock inputs
- 4 inputs to clock array originated from NAND array
- 4 inputs (with programmable polarity) directly from input pins
- 10 inputs from Q outputs of JKFFs with clear
· Dedicated clocks:
- One dedicated clock for input DFFs (Group A)
- Two dedicated clocks for output DFFs (Group E)
· Scan test feature:
- Scan chain is implemented through the 20 buried JKFFs and 16 output DFFs
- Pins SCI, SCM, and CKE1 are used to operate the scan test
· Power down mode
- Dedicated pin (PD) freezes the circuit when brought to logic "1 ". The circuit remains in the same state prior to the
logic ·o· to logic "1" transition of the "PD"
pin. - When in the power down mode, the SCI
pin acts as the 3-State pin for the 40 outputs.
· Power on reset: - All flip-flops (16 input DFFs, 20 buried JKFFs, and 16 output DFFs) are reset to logic "O" after Vee power on.
ARCHITECTURE
The core of the PML2852 is a programmable NAND array of 96 NAND gates and 20 buried JKFFs. The output of each NANO gate folds back upon itself and all other NANO gates
and flip-flops. The 'O' and '0' output of each
flip-flop also folds back in the same manner. Thus, total connectivity of all logic functions is achieved in the PML2852. Any logic function can be created within the core without wasting valuable 110 pins. Furthermore, a speed advantage is acquired by implementing multi-level logic within a fast internal core without incurring any delays from the 110 buffers. Figure 1 shows the functional block diagram of the PML2852.
Macro Cells
There are 16 bypassable DFFs on the input to the NANO array. These flip-flops are split in two banks of 8 (Bank A and Bank B). Each

bank of flip-flops has a common clock. In the unprcgrammed state of the device the flip-
flops are active. In order to bypass any DFF,
its respective bypass fuse (BFAx) must be programmed.

The 16 1/0 pins (100 - 1015) and their respective D flip-flop macros can be used in any one of the following configurations: 1. As combinatorial input(s):
Each of the 16 3-State outputs can be individually disabled by the associated NAN D term and the pin is used as an inverting or non-inverting input. 2. As registered DFF outputs: These DFFs are split into two banks of 8, and each bank is clocked separately. The bypass fuse BFBx (see PML2552 Logic Diagram) is used to bypass any one of these DFFs. The flip-flops are all active in an unprogrammed device. 3. As combinatorial outputs: By programming the bypass (BFBx) fuse of any one of the DFFs, the flip-flop(s) is bypassed. The 110 pin can then be used as a combinatorial output. 4. As Internal foldback DFFs or foldback NANO gates: When the 110 pin is used as an input, the output macro can be used as a buried OFF or a foldback NAND term. If the bypass fuse is programmed, the macro will act as a foldback NAND term. Otherwise it will act as a buried DFF.

The 8 bidirectional pins (BO-B7) can be used

as either combinatorial inputs or outputs with

programmable polarity. The Exclusive-OR

polarity gates are non-inverting in the

unprogrammed state.

·ou· The NAND signal labeled

(Output

Disable) shown on the PML2852 logic

diagram is used for the Power Down mode

operation. This signal disables the outputs

when the device enters the Power Down

mode and SCI is high.

Clock Array
The 20 buried JKFFs are clocked through the 'Clock Array'. The Clock Array consists of 11 NANO terms. Ten of these terms are connected to the clock inputs of the Bank A flip-flops that can be clocked individually. One NAND gate is connected to Bank B flip-flops that have a common clock. There are 18 inputs to the clock array. Four come directly from the input pins (with programmable polarity), 4 inputs are from 4 NANO gates connected directly to the folded NANO array. 10 inputs are from the Q outputs of the JKFFs with clear.

489

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

SCAN TEST FEATURE With the rise in the ratio of devices on a chip to the number of 1/0 pins, Design For Testability is becoming an essential factor in logic design methodology. The PML2852 incorporates a variable length scan test feature which permits access to the internal flip-flop nodes without requiring a separate external 1/0 pin for each node accessed. Figure 2 (Scan Mode Operation) shows how a scan chain is implemented through the 20 buried JKFFs and 16 output DFFs. Two dedicated pins, SCI (Scan In) and SCM (Scan Mode), are used to operate the scan test. The SCM pin is used to put the circuit in scan mode. When this pin is brought to a logic "1 ", the circuit enters the scan mode.

In this mode it is possible to shift an arbitrary test pattern into the flip-flops. The SCI pin is used to input the pattern. The inverted outputs of flip-flops DO - D15 are observable on pins 1/00 - 1/015.
The following are features and characteristics of the device when in Scan Mode: 1. CKE1 is the common scan-clock for all
the flip-flops when in scan mode. CKE1 overrides all clock resources of normal operational mode.
2. The Preset (PR) and Clear (CL) functions of the flip-flops are disabled.
3. Scan overrides the bypass fuse of the flip-flops. This means that all the

bypassable DFFs remain intact during scan operation even though they may have been bypassed during normal operation.
4. To observe the SCAN data, the output buffers must be enabled by the Output Enable (bi-ctrl) terms.
5. The outputs of the ffip-flops are complemented on pins l/00 - 1/015.
6. All external inputs to flip-flops in the scan chain are disabled when the device enters the scan mode.
7. Blowing the security fuse does not disable the Scan Test feature.

SCAN MODE OPERATION

SCOUT

11015

1100 11014

1101 11013

1102 11012

1103 11011

l/04 11010

1105 V09

l/06 1108

l/07

SCI

(COMMON CLOCK (CKE1) FOR ALL FLIP-FLOPS WHEN IN SCAN MODE)

Figure2.

October 22, 1993

490

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

SCAN TEST STRATEGY
The scan test pattern is design dependent and the user must make considerations for Design For Testability (OFT) during the initial stages of the design. A typical test sequence is to pre-load (i.e., enter a state); revert to normal operation (i.e., activate the next state transition); go back to scan mode to check the result. Note that the scan test fearure available in the PML2852 is a variable length scan chain. The DATA entered at SCI (JKCL9) can be accessed anywhere between 21 clock cycles (at 1100) to 36 clock cycles (at 1/015). For the strategy discussed here, DATA is read out after 36 clocks at 11015 (i.e., 015). The following operation sequence suggests a possible scan test method.
A conservative test policy demands proof that the test facility is working. Thus, to prove Scan Chain holds and maintains correct data:
a. Fill chain with several patterns (for example, all ones and all zeros).
b. Retrieve same patterns.

5. To read result of the state transition, re-enter scan and apply the scan clock (CKE1 ). The result of the state transition in JKCL9 will be available at SCOUT (1/015) after 36 clocks. The results can be stored in a user defined test memory buffer in inverted logic representation.

6. As the results are being read and stored, new 'Test Data' can be entered via SCI.
7. Repeat for all test patterns of interest.
8. Figure 3 (FLOW_CHART) depicts a flow chart version of the test sequence.

TEST INTEGRITY OF SCAN CHAIN. ASSUME 36-BIT SCAN CHAIN,
IF LESS, SET COUNT= LENGTH-1.
SET SCM: 1 SET COUNT= 35
TEST DATA READY AT 'SCI' INPUT
APPLY SCAN CLOCK

The user is responsible for managing an external test memory buffer for applied vectors and results, as part of the test equipment.
1. Parallel readout of 1100 - 1/015 is possible, but assume only 11015 is used for this strategy.
2. The first DATA entered at SCI (or JKCL9) will be the content of 015 after 36 clocks. This DATA will be inverted at the output pin 1/015 (i.e., SCOUT). The last DATA entering the scan chain will be the content of JKCL9. Thus, the scan chain resembles a first-in-first-out shift register with inverted outputs (1/00 - l/015).
3. 'Test Data' is read in at the SCI input and read out of the SCOUT output pin (1/015). To enter 'Test Data':
a. Put device in Scan Mode by applying the scan control signals (SCM= 1).
b. Clock device with scan clock (CKE1).
c. Apply consecutive serial test vectors.
d. Read back results as new 'Test Data' (States) are applied. The first 36 outputs read at SCOUT (l/015) are random ('old') data (e.g., remnant of Step 1).
e. Apply 36 'Test Data' until the chain is full.
4. To apply 'Test Data' (States), exit Scan Mode and apply on system clock together with any other possible test vectors.

READ OUT RESULT AND STORE IN TEST MEMORY1
COUNT= COUNT-1
SELECT NEXT TEST DATA AND APPLY TO SCI
SETSCM:O (NORMAL OPERATING MODE)
APPLY SYSTEM CLOCK AND ANY EXTERNAL TEST VECTORS
RESULT READY FOR OUTPUT ON NEXT 36 CLOCK CYCLES AS NEW TEST VECTOR IS LOADED
NOTE: 1. The first 36 outputs are random ('OLD') data.
Flgure3. FLOW_CHART

October 22, 1993

491

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

A Simple Example
Assume the last three cells of the scan chain (JKCL9, JKCLS, JKCL7 in Figure 4 contain a 3-bit up counter. Our test vector will be a single clock applied to the counter. Suppose we wish to first check the State 5 (i.e., 101) to State 6 (i.e., 110) transition, then the State 3 (i.e., 011) to State 4 (i.e., 100) transition. Assume the scan chain has been pre-verified and we may begin.
Enter scan mode (set SCM=1)1apply36 bits in sequence so that the value 101 (i.e., State 5) resides in the last three cells. Exit scan mode (set SCM=O) and apply a single clock to the counter. Now the value 110(i.e., State 6) resides in the last three cells. Re-enter scan mode (set SCM=1) and read back 36 bits from position 1/015. Note that the outputs are complemented and are also read back in the reverse order. Therefore the value for STATE 6 read at 1/015 will be 100 which is the complement of STATE 6(110) read in the reverse order.
As this is being read back, apply a new state, serially equal to the value 011 (i.e., State 3). This state should be loaded on the last three clock cycles during which STATE 6 is being read back at 1/015. After STATE 3 has been loaded (and STATE 6 read back), exit scan mode and apply a single clock which will invoke the STATE 3(i.e., 011) to STATE 4 (i.e., 100) transition. Re-enter scan mode and read back 36 bits at 1/015. The last three bits should contain 110which is the complement of State 4 read in the reverse order. 4 (SCAN_EXAMPLE) shows a flow diagram of this example. Note that the States will always be complemented and read back in the reverse at 1/015. Other sequences may be applied in the same manner.
A possible alternative to this example is to read back the output states at 1/00 (DO) instead of 1/015 (JKCL9). This will allow the outputs to be read back after 21 clock cycles rather than the 36 used in the above example.

SCI JKCL9

JKCL9

JKCL7

STATES

···
JKCL6

EXIT SCAN MODE (SCM = 0) AND APPLY COUNTER CLOCK

SCI JKCL9

JKCL9

JKCL7

STATE6

···
JKCL6

APPLY 33 SCAN CLOCKS

1/014:0

1/013:0

li012=X

···

D15

D14

D13

D12

STATE 6 IN REVERSE ORDER OUTPUTS COMPLEMENTED

STATE 3 (011) WILL BE LOADED ON NEXT 3 CLOCKS

SCI JKCL9

JKCL8

JKCL7

STATE3

JKCL6

EXIT SCAN MODE (SCM =0)
AND APPLY COUNTER CLOCK

···

SCI JKCL9

JKCL9

JKCL7

STATE4

· ··
JKCL6

APPLY 33 SCAN CLOCKS

October 22, 1993

···

015

D14

013

D12

STATE 4 IN REVERSE ORDER OUTPUTS COMPLEMENTED

Figure 4. SCAN_EXAMPLE

492

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

POWER DOWN
The PML2852 offers the user controlled capability of putting the device to "sleep" where power dissipation is reduced to very low levels. When brought to a logic "1 ", the PD pin freezes the circuit while reducing the power. All data is retained. This not only includes that of the registers, but also the state of each foldback gate. For those cases where it is desirable to 3-State the outputs, that can be accomplished by raising the SCI pin to a logic "1".
There is one point that should be noted while the circuit is in its power-down mode. The switching of any external clock pin will cause a disruption of the data. All clocks must be frozen before the circuit goes into powerdown and stay that way until it powered back up. Clocks that are internally generated and feed the clock array are automatically stopped by the power-down circuitry. Any other input can toggle without any loss of data.
NOTE: 1. During power down, external clocks (CKA,
CKB/CKC, CKE1, CKE2) should not change. 2. SCM must be "O" as in normal operation mode. 3. External clock recovery time (low-to-high) is 60ns (high-speed) and 70ns (standard) after the device is powered up. 4. Power Down Timing Diagrams on pages 502 and 503 are for combinatorial operation only.

DEVELOPMENT TOOLS
The PM2852 is supported by the Philips Semiconductors SNAP software development package and a multitude of hardware and software development tools. These include industry standard PLD programmers and CAD software.
SNAP
Features · Schematic entry using DASHTM 4.0 or
above or OrCADTM SDT 111
· State Equation Entry
· Boolean Equation Entry
· Allows design entry in any combination of above formats
·Simulator - Logic and fault simulation - Timing model generation for device timing simulation - Synthetic logic analyzer format
· Macro library for standard TTL and user defined functions
· Device independent netlist generation
· JEDEC fuse map generated from netlist
SNAP (Synthesis, Netlist, Analysis and Program) is a versatile development tool that speeds the design and testing of PML. SNAP

combines a user-friendly environment and powerful modules that make designing with PML simple. The SNAP environment gives the user the freedom to design independent of the device architecture.
The flexibility in the variations of design entry methodologies allows design entry in the most appropriate terms. SNAP merges the inputs, regardless of the type, into a highlevel nemst for simulation or compilation into a JEDEC fuse map. The JEDEC fuse map can then be transferred from the host computer to the device programer.
SNAP's simulator uses a synthetic logic analyzer format to display and set the nodes of the design. The SNAP simulator provides complete timing information, setup and hold-time checking, plus toggle and fault grading analysis.
SNAP operates on an IBM® PC/XT, PC/AT, PS/2, or any compatible system with DOS 2.1 or higher. A minimum of 640K bytes of RAM is required together with a hard disk.
DESIGN SECURITY
The PML2852 has a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary design implemented in the device cannot be copied or retrieved.

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

PARAMETER

RATINGS

UNIT

Vee

Supply voltage

+7

Voe

V1N

Input voltage

+5.5

Voe

VouT

Output voltage

+5.5

Voe

l1N

Input currents

-30 to +30

mA

louT

Output currents

+100

mA

Tamb

Operating temperature range

0 to +75

oc

Tstg

Storage temperature range

--65to+150

oc

NOTE. 1. Stresses above those listed may cause malfunction or permanent damage to the device. This
1s a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

THERMAL RATINGS
TEMPERATURE Maximum junction
Maximum ambient
Allowable thermal rise ambient to junction

150°C 75°C 75°C

DASH is a trademark of Data 1/0 Corporation. OrCAD is a trademark of OrCAD, Inc. IBM is a registered trademark of International Business Machines Corporation.
n...tnhi::>r ?? 1QQ~

493

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

DC ELECTRICAL CHARACTERISTICS
0°C,;; Tamb,;; +75°C, 4.75V,;; Vee s 5.25V

SYMBOL

PARAMETER

TEST CONDITIONS

Input voltage

V1L

Low

V1H

High

Vcc=MIN Vee= MAX

Output voltage

Vol

Low

Vee= MIN, loL = 5mA

VoH

High

Vee= MIN, loH = -2mA

Input current

l1L

Low

l1H

High

Output current

V1N= GND V1N =Vee

lo(OFF)

Hi-Z state

Vour =Vee Your= GND

loH

Output High

loL

Output Low

Vee= MIN, Your= 2.4V Vee= MIN, Vour = 0.45V

las

Short-circuit5

Vour= GND

Ice

Vee supply current

lss

Standby Vee supply current

Capacitance

Vee= MAX, No load f=1MHz
Vee= MAX, No load PD= V1H

CMOSinput2 TTLinput3 CMOS input TTL input

C1N

Input

Cs

110

Vee= 5V, Tamb = +25°C, V1N = 2.0V Vee= 5V, Tamb = +25°C, V10 = 2.0V

NOTES: 1. All typical values are al Vee= 5V, Tamb = +25°C.
2. CMOS inputs: V1L = GND, V1H =Vee. 3. TTL inputs: V1L = 0.45V, V1H = 2.4V. 4. All voltage values are with respect to network ground terminal.
5. Duration of short-circuit should not exceed one second. Test one at a time. 6. ~Ice vs. Frequency = 4mAIMHz max.

TEST LOAD CIRCUITS

yc2 c1

Vee L__.>

R1

IA

By

CL

·e OUT
Bw

Bz OUTPUTS

Bx GND Ox

-=

NOTES:
C1 and C2 are to bypass Vee to GNO.

-=

Test Load R1 = 750n, R2"" 442ll, Cl .. 3~F (CL= 5pF for Output Disable)

O"C .s. Tamb ~ +75°C, 4.75V s. Vee~ 5.25V

MIN --0.3 2.0
2.4

LIMITS TYP1

MAX

UNIT

0.8

v

Vee +0.3

v

0.45

v

v

-10

µA

10

µA

10

µA

-10

µA

-2

mA

5

mA

-100

mA

60

1006

mA

65

1206

mA

1.0

10

mA

1.5

10

mA

8

pF

16

pF

VOLTAGE WAVEFORMS

MEASUREMENTS: AU circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses

October 22, 1993

494

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

MACRO CELL AC SPECIFICATIONS Min: 0°C, 5.25V; Typ: 25°C, 5.0V; Max: 75°C, 4.75V (SNAP Resource Summary Designations in Parentheses)
Input Buffer (OIN552, NIN552, BDIN552, BNIN552 COIN552, CNIN552, CKDIN552, CKNIN552, IOFF552*)
·~

PARAMETER

LIMITS

SYMBOL

To

From

PML2852-35

PML2852-SO

(Output)

(Input)

MIN TYP MAX MIN TYP MAX

lpHL

x

lpLH

x

I

5

7

10 7

10 15

I

5

7

10 7

10 15

lpHL

y

lpLH

y

I

5

7

10 7

10 15

I

5

7

10 7

10 15

· When input D flip-flop is bypassed. Input Pins: 12-18, 20, 21, 24, 26-28. 1/0 and Bidirectional Pins: 1-3, 5-7, 58-60, 62-66, 69, 70, 75-80, 83, 84. Bypassed OFF at Pins: 30-32, 34-39, 41-43, 45, 47-49.

Internal NANO of Main Array (FBNANO, NANO)

D x

y

SYMBOL
lpHL lpLH

PARAMETER

To

From

(Output)
y y

(Input)
x x

LIMITS

LIMITS

PML2852-35

PML2852·50

MIN TYP MAX MIN TYP MAX

10 15 20 12 18 25 10 15 20 12 18 25

UNIT ns ns ns ns
UNIT ns ns

SYMBOL
lpHL lpLH

Internal NANO of Clock Array (NANO)

D x

y

PARAMETER

To

From

(Output)
y y

(Input)
x x

LIMITS

PML2852·35

MIN TYP MAX

5

7

10

5

7

10

LIMITS

PML2852-50

MIN TYP MAX

7

10 15

7

10 15

UNIT
ns ns

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

MACRO CELL AC SPECIFICATIONS (Continued)
Min: 0°C, 5.25V; Typ: 25°C, 5.0V; Max: 75°C, 4.75V (SNAP Resource Summary Designations in Parentheses)

3-State Output with Programmable Polarity
(TOUT552 + EXOR552 + NANO)

v v

.L.
IL1
~
v V1

0

OU1

-1 lL

D

-2 o 20 40 60 ao 100 120 1401601ao 200

OUTPUT CAPACITANCE LOADING (pf)

=

~!po vs Output Capacitance

Loading (Typical)

PARAMETER

SYMBOL

To

From

(Output)

(Input)

!pHL

Out

In

!pLH

Out

In

toE4

Out

Tri-Ctrl

too4

Out

Tri-Ctrl

Bidirectional Pins: 58--60, 62--66.

LIMITS

PML2852-35

PML2852·50

MIN TYP MAX MIN TYP MAX

12 18 25 17 25 35 12 18 25 17 25 35

5

7

10

7

10 15

5

7

10

7

10 15

UNIT
ns ns ns ns

1/0 Output Buffer with 3-State Control, OFF Bypassed (TOUT552 + NANO)
In

v k":

I

.~ 3
15
<i 2

v lZIL1

]7

-1 lL
-2 0 20 40 60 80 100120140160180200 OUTPUT CAPACITANCE LOADING (pf)
~!po vs Output Capacitance Loading (Typical)

PARAMETER

SYMBOL

To

From

(Output)

(Input)

!pHL

Out

In

tPLH

Out

In

toE4 too4

Out

Tri-Ctrl

Out

Tri-Ctrl

110 Pins: 1-3, 5-7, 69, 70, 75--80, 83, 84.

Notes on page 501.

LIMITS

PML2852-35

PML2852-50

MIN TYP MAX MIN TYP MAX

12 18 25 17 25 35 12 18 25 17 25 35

5

7

10

7

10 15

5

7

10

7

10 15

UNIT
ns ns ns ns

October 22, 1993

496

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

MACRO CELL AC SPECIFICATIONS (Continued)
Min: 0°C, 5.25V; Typ: 25°C, 5.0V; Max: 75°C, 4.75V (SNAP Resource Summary Designations in Parentheses)

Active-Low 3-State Output (TOUTB52 + NANO)

~

~

Out
D

7 6

v 17

5
4
l 3
15 ~ 2 <l
1

f ILl
v v IZ

_0, IL

-2 0 20 40 60 80 100120140160180200
OUTPUT CAPACITANCE LOADING (pf)

.1.tpo vs Output Capacitance Loading (Typical)

PARAMETER

SYMBOL

To

From

(Output)

(Input)

tpHL

Out

In

tPLH

Out

In

Output Pins: 8-11, 50-57, 71-74.

LIMITS

PML2852-35

PML2852-50

MIN TVP MAX MIN TVP MAX

12 18 25 17 25 35 12 18 25 17 25 35

UNIT
ns ns

497

Philips Semiconductors Programmable logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

MACRO CELL AC SPECIFICATIONS (Continued) (SNAP Resource Summary Designations in Parentheses) D FLIP-FLOP Min: 0°C, 5.25V; Typ: 25°C, 5.0V; Max: 75°C, 4.75V
Output OFF Used Internally (ODFF552)

ID

h.

D

CKE~ Q

·~x

SYMBOL
fcKE twcKE High twcKE low
tsETUP ID
tHoLo/D

PARAMETER
Flip-flop toggle rate Clock HIGH Clock LOW
ID setup time to CKE ID hold time to CKE

SYMBOL
IPLH tPHL

PARAMETER

From

To

(Input)

(Output)

CKEi

Q

CKE i

Q

LIMITS

PML2852-35

PML2852-50

MIN TYP MAX MIN TYP MAX

50

35

10

14

10

14

15

20

4

6

UNIT
MHz ns ns ns ns

LIMITS

PML2852-35

PML2852-50

MIN TYP MAX MIN TYP MAX

10 15 20 14 20 25 10 15 20 14 20 25

UNIT
ns ns

October 22, 1993

498

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

MACRO CELL AC SPECIFICATIONS (Continued) (SNAP Resource summary Designations in Parentheses) D FLIP-FLOP (Continued)
Min: 0°C, 5.25V; Typ: 25°C, 5.0V; Max: 75°C, 4.75V
Input and Output (IDFF552 & ODFF552)

INPUTS

OUTPUTS

CK

D

Q

O"

L

x

Oo

Oo

1'

H

H

L

1'

L

L

H

NOTE: Oo. Oo represent previous stable condition of Q, 0.

I/DA, I/DB CKA, CKB, CKC

Qt-------01--------
=
Trl-C1rl -----~

ID
Q

=

SYMBOL
fcKA, CKB, CKC tw CKA, CKB, CKC High tw CKA, CKB. CKC Low lsETUP I/DA, I/DB tHOLD I/DA, I/DB fcKE twcKE High twcKE Low lsETUP ID tHow/D

LIMITS

PML2852-35

PML2852-50

MIN TYP MAX MIN TYP MAX

50

35

10

14

10

14

5

7

5

7

50

35

10

14

10

14

15

20

4

6

UNIT
MHz ns ns ns ns
MHz ns ns ns ns

v v
f IL'.l
v v12'
-1 .L1
-2 0 20 40 60 80 100120140160180200 OUTPUT CAPACITANCE LOADING (pFJ
L'l.tpD vs Output Capacitance Loading (Typical)

SYMBOL
IPLH IPHL IPLH tPHL

PARAMETER

From

To

(Input)

(Output)

CKA, CKB/CKC 1' CKA, CKB/CKC 1'

0,0 0,0

CKEi

Out

CKE1'

Out

LIMITS

PML2852-35

PML2852-50

MIN TYP MAX MIN TYP MAX

5

7

10

7

10 15

5

7

10

7

10 15

12

18

25

17

25

35

12

18

25

17 25

35

UNIT
ns ns ns ns

OctobP.r 2? HI~~

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

MACRO CELL AC SPECIFICATIONS (Continued) (SNAP Resource Summary Designations in Parentheses) JK FLIP-FLOPS
Min: 0°C, 5.25V; Typ: 25°C, 5.0V; Max: 75°C, 4.75V

(JKPR552)

INPUTS

PR

CK

J

K

L

x

x

x

H

t

L

L

H

t

H

L

H

t

L

H

H

t

H

H

H

L

x

x

OUTPUTS

Q

0

H

L

Oo ao

H

L

L

H

TOGGLE
ao I ao

(JKCL552)

INPUTS

er CK

J

K

L

x

x

x

H

t

L

L

H

t

H

L

H

t

L

H

H

t

H

H

H

L

x

x

OUTPUTS

Q

a

L

H

Oo Oo

H

L

L

H

TOGGLE
0o I ao

IJ

Q

CK1

/K

SYMBOL
fcK1 fc1<2 twcK1 High twcK1 Low twcK2 High twcK2 Low lsETUP /J, /K tHOLD /J,/K tw PR Low twCLLow

PARAMETER
CK1 toggle frequency CK2 toggle frequency CK1 clock HIGH CK1 clock LOW CK2 clock HIGH CK2 clock LOW /J, /K setup time to CK1, CK2 /J, /K hold time to CK1, CK2 Preset Low period Clear Low period

/J

Q

CK2

IK

LIMITS

PML2852·35

PML2852·50

MIN TYP MAX MIN TYP MAX

50

35

50

35

10

14

10

14

10

14

10

14

27

35

0

0

10

14

10

14

UNIT
MHz MHz
ns ns ns ns ns ns ns ns

SYMBOL
tpLH lpHL lpLH lpHL IPLH tPHL

From (Input)
CK1,2 CK1,2
PR PR
CL CL

PARAMETER
To
(Output)
a.a a,o a.a a.a a.a a.o

LIMITS

PML2852·35

PML2852-50

MIN TYP MAX MIN TYP MAX

2 3.5 5

3

5

7

2

3.5

5

3

5

7

12 18 25 17 24 30 12 18 25 17 24 30

12 18 25 17 24 30 12 18 25 17 24 30

UNIT
ns ns ns ns ns ns

October 22, 1993

500

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

AC ELECTRICAL CHARACTERISTICS
0°C s Tarr1i s +75°C, 4.75V s Vee s 5.25V, Vpp =Vee.
R1 = 750Q, R2 = 442Q, CL= 5pF for Output Disable) (See Test Load Circuit Diagram)

LIMITS

SYMBOL

PARAMETER

PML2852·35

PML2852·50

UNIT

MIN

MAX

MIN

MAX

Scan mode operation1

lsCMS lseMH tis

Scan Mode (SCM) Setup time Scan Mode (SCM) Hold time Data Input (SCI) Setup time

15

15

ns

25

30

ns

5

5

ns

t1H

Data Input (SCI) Hold time

5

5

ns

lcKO

Clock to Output (1/0) delay

30

40

ns

lcKH

Clock High

lcKL

Clock Low

Power down, power up2

10

15

ns

10

15

ns

tl

Input (I, bypassed I/DA, I/DB, 1/0, 8) setup time before power down

40

50

ns

t2

Input hold time

30

35

ns

t3

Power Up recovery time

60

70

ns

l;

Output hold time

0

0

ns

ts

Input setup time before Power Up

loE

SCI to Output Enable time3

too

SCI to Output Disable time3

ts

Power Down setup time

t1

Power Up to Output valid

20

25

ns

40

50

ns

40

50

ns

10

15

ns

70

80

ns

Power-on reset

tPPRl

Power-on reset output register (Q = 0) to output (1/0) delay

10

15

ns

tPPR2

Power-on reset input register (Q = 0), buried JK Flip-Flop (Q = 0) to output (8, bypassed 1/0) delay

40

50

ns

NOTES:
1. SCM recovery time is 50ns after SCM operation. 50ns after SCM operation, normal operations can be resumed. 2. 1imings are measured without foldbacks.
3. Transition is measured at steady state High level (-500mV) or steady state Low level (+500mV) on the output from 1.5V level on the input with specified test load (R1 = 750Q, R2 = 442Q, CL= 5pF). This parameter is sampled and not 100% tested.
4. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL= 5pF. High-to-High impedance tests are made to an output voltage of Vr = (VoH -0.SV) with S 1 open, and Low-to-High impedance tests are made to the Vr = (VoL + O.SV) level with S 1 closed.

Or.:tnh,::i.r ?? 1oa".l

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic
TIMING DIAGRAMS

Product specification
PML2852

SCI
ov
+3V CKE1
ov

110

1.SV

1.SV

'-------vOL

Scan Mode Operation

-----+3V

I, BYPASSED I/DA, I/DB, 110, B

1.SV

1.SV

1.SV

f~t1t·2

~:t-13=1-:v

I 1.-sv_______ \ 1.sv I

PD

___,,~ I

~ IPD1

ov

~ ~ r,. to _·~- IM~~ B,110 -__1_.s_,\)E~~,----~~1------+-K.._____~~ vvooLH

...

7'C:__

______,f I.SY

\ 1.SV

+3V

ov

Power Down, Power Up Input (old) Ready Before Power Up

October 22. 1993

502

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

TIMING DIAGRAMS (Continued)
·~--~· =t:~~,.~-.5-V-----:

PD

fI uv

~ I

----..

B,110

" \ 1.5vl

~--.-~.-~-

OY

, _ _ _ _ VoH

1.SY
'----vol

+3V SCI
OY
Power Down, Power Up Input (new) Ready After Power Up

I, BYPASSED I/DA, I/DB, llO, B
PD
9,10

- - - - - +3Y

1.SV

1.5

ov

·PD +3V

ov

October 22. 1993

+3V SCI
OY
Power Down, Power Up Input (new) Ready Before Power Up

__.. 1./'.________________ +SY

~~4.SY

Vee

~I -,PP-R1_ -J _ _ _ _ _ _ ov

1/0 ~

, . . . , . . , . - 1 . - 5 Y - - - - - - - - - - - YoH

B,10 Vol 'PPR2~ ~.-1-.5-V---------- VoH

Power-On Reset

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic
SNAP RESOURCE SUMMARY DESIGNATIONS

Product specification
PML2852

1 3 8 8

October 22, 1993

504

Philips Semiconductors Programmable Logic Devices
CMOS high density programmable macro logic

Product specification
PML2852

ERASURE CHARACTERISTICS (For Quartz Window Packages
Only)
The erasure characteristics of the PML2852 device is such that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000 - 4000A range. Data shows that constant exposure to room level fluorescent lighting could erase a typical PML2852 in approximately three years, while it would take approximately one week to

cause erasure when exposed to direct sunlight. If the PML2852 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the window to prevent unintentional erasure.
The recommended erasure procedure for the PML2852 is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15Wsec/cm2· The erasure time with this dosage is approximately 30 to

35 minutes using an ultraviolet lamp with a 12,000µW/cm2 power rating. The device should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose a CMOS EPLD can be exposed to without damage is 7258Wsec/cm2 (1week@12,000µW/cm2). Exposure of these CMOS EPLDs to high intensity UV light for longer periods may cause permanent damage.
The maximum number of guaranteed erase/write cycles is 50. Data retention exceeds 20 years.

PROGRAMMING
Refer to the following charts for qualified manufacturers of programmers and software tools:

PROGRAMMER MANUFACTURER
DATA 110 CORPORATION 10525 WILLOWS ROAD, N.E. P.O. BOX 97046 REDMOND, WASHINGTON 98073-9746
(800)247-5700

PROGRAMMER MODEL UNISITE 40/48 Ver. 3.5 PINSITE Ver. 3.5

STREBOR DATA COMMUNICATIONS 1008 N. NOB HILL AMERICAN FORK, UT 84003

PLP-S1A Programmer MP68CC adapter

BASIC COMPUTER SYSTEMS AG WOLFGANG-PAULI-GASSE A-1140 WIEN-AUHOF, AUSTRIA

UP2000 Rev. 2.28

SMS - W. STEUDEL IM MORGENTAL 13 D-8994 HERGATZ, GERMANY

SPRINT PLUS/EXPERT Rev. TBD

SYSTEM GENERAL 244 SOUTH PARK VICTORIA DRIVE MILPITAS, CALIFORNIA 95035

TURPR0-1 Rev. 1.42

FAMILY/PINOUT CODES 15918C· (with adaptor) 15918D

Needs a 40-pin DIP to 84-pin PLCC adaptor that is available from Emulation Technology. Part Number: AS-84-40--01P-6YAM

EMULATION TECHNOLOGY, INC.

2368B Walsh Avenue, Building D

Santa Clara, California 95051

Telephone No. (408) 982--0660

Fax. No.

(408) 982--0664

SOFTWARE MANUFACTURER
PHILIPS SEMICONDUCTORS 811 EAST ARQUES AVENUE P.O. BOX 3409 SUNNYVALE, CALIFORNIA 94088-3409
(408)991-2000

DEVELOPMENT SYSTEM SNAP SOFTWARE

I,

Programmable Logic Devices

Section 8
Military Selection Guide

CONTENTS Military selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

Philips Semiconductors Programmable Logic Devices
Military selection guide

Part Number

Device Description

PLC18V8Z/BRA

GAL

PLC 18V8Z/B2A

GAL

PLC22V10-15/BLA

GAL

PLC22V10-20/BLA##

GAL

PLC22V10-25/BLA##

GAL

PLC22V10-30/BLA##

GAL

PL8167/BLA

PL8

PL8168/BLA

PL8

PL8173

PLA

828100/BXA

PLA

828100/BYA

PLA

828101/BXA

PLA

828101/BYA

PLA

828101/B3A

PLA

828105/BXA

PL8

828105/BYA

PLS

828105/B3A

PL8

828153A/BRA

PLA

828153A/B2A

PLA

Available in QPL part IV specifications ## Available as an 8MD part number only

Package Description 20DIP3 20LLCC 24DIP3 24DIP3 24DIP3 24DIP3 24DIP3 24DIP30 24DIP3 28DIP6 28FLAT 28DIP6 28FLAT 28LLCC 28DIP6 28FLAT 28LLCC 20DIP3 20LLCC

Standard MIL-Drawing PLANNED PLANNED 5962-8984105MLA 5962-8984102MLA 5962-8984104MLA 5962-8984101 MLA
5962-9201201 MLA 5962-8850402MLA M38510/50202XA·
M38510/50201XA·
5962-8670901XA 5962-8670901 YA 5962-86709013A 5962-8768201 RA 5962-87682012A

I'

Programmable Logic Devices

Section 9
Development Software

CONTENTS

SNAP 1.9

Synthesis Nellis! Analysis Program

513

I,

Philips Semiconductors Programmable Logic Development Software
Synthesis Netlist Analysis Program

SNAP 1.9

FEATURES
· Schematic entry available using Data 1/0 DASH'" OrCAD SOT IVTM
· State equation entry
· Boolean equation entry
· Truth table entry
· Netlist entry
· Edit 2.xx entry
· Graphical simulation waveform entry
· Capability to design in one or any combination of formats
· Device independent, nellist based design platform
· Boolean equation extractor
· Fuse table editor
· Philips LESIM 5-State gate array simulator: - Logic and fault simulation - Model extraction and timing simulation - Synthetic logic analyzer format - Stimuli entry in waveform format - Simulate multiple-PLO design
· Freezing of selected Critical paths
· Capability to create user defined macros or to use ITL elements
· Automatic test vector generation tor combinatorial circuits
· JEDEC tusemap compiler and device programmer interface

GENERAL DESCRIPTION
SNAP PLO development software. Simple-to-use tools for demanding designs.
Get ready for greater design productivity. SNAP, the complete logic synthesis, simulation and layout package for Philips Semiconductors full line of PLDs, saves one commodity in preciously short supply: design time. Fully equipped with every tool you need to turn out PLO designs quickly, SNAP eliminates the "learning curve" that can keep you from being immediately productive. Regardless of whether you're a PLO novice or seasoned pro, SNAP allows you to produce optimized designs within a matter of hours.
For rapid design you need flexibility and SNAP provides lots of it. Enter your design in the most convenient way possible - using any combination of schematics, truth tables, Boolean equations, state equations or nellists. SNAP merges the inputs and generates a dense, high-speed design that can be simulated in SNAP's powerful simulator and then downloaded to a PLO programmer.
With SNAP, you produce your design in a nellist-based, device-independent environment. No need to commit to a particular part from the start of the design process: With SNAP, you can change the target PLO at will. If you find that your design needs a larger device or can fit into a smaller,

less expensive one, simply select a new part and resimulate. SNAP allows you to take advantage of the most appropriate PLO for the job without wasting time.
SNAP'S UNRIVALED SIMULATION FACILITY
Simulation is a key part of the SNAP design process. SNAP Incorporates Philips S·State ASIC simulator, a simulator so unsurpassed in its accuracy and diagnostic ability that it is a standard tool used by the company's own chip designers. You can examine any of your design's internal nodes and apply SNAP's virtual logic analyzer to display the precise timing at that node. Then change the stimulus and put the design through its paces with SNAP's built-in waveform editor. Compile into a specific PLO and resimulate. When you finally program a PLO, chances are that it will run perfectly the first time.
Since testability represents an ever-important measure of the success of a PLO design, SNAP includes a powerful fault simulator that simplifies the task of analyzing fault coverage. The tool rapidly generates a report detailing undetected and potentially undetectable faults, coverage efficiency, and other useful data. With it, you get the most thorough fault coverage possible in a limited test period.

SNAP Design Flow
INPUT

SIMULATE
DASH is a trademark of Data 1/0 Corp. OrCAD STD IV is a trademark of OrCAO, Inc.
January 26, 1993

COMPILE OUTPUT

Philips Semiconductors Programmable Logic Development Software
Synthesis Netlist Analysis Program

SNAP 1.9

Would you like to know how many potential faults your test vectors can detect? Just look at the output of the SNAP FAULT SIMULATOR...

FAULT LIST·

TOTAL NUMBER OF SIGNALS

NUMBER OF NAMED SIGNALS

6

NUMBER OF CIRCUIT FAULTS

12

NUMBER OF INSERTED FAULTS

10

NUMBER OF COLLAPSED FAULTS

2

FAIJI.T QETECTTON·

NUMBER OF HARD DETECTED FAULTS

12

NUMBER OF POTENTIALLY DETECTED FAULTS

NUMBER OF UNDETECTED FAULTS

Flj[JI.T COVERAGE· HARD DETECTION FAULT COVERAGE POTENTIAL DETECTION FAULT COVERAGE TOTAL DETECTION FAULT COVERAGE

100.0%
o.o
100.0%

HABQ DETECTION FAIJI.T coyBRAGE YEBS!JS PATTERN# ·

PATTERN# %

0

20

40

60

80

100

------------------+----------+---------+---------+---------+---------+

1 58.3

*****************************

2 75.0

**************************************

83.3

******************************************

4 100.0

**************************************************

5 100.0 **************************************************

------------------+---------+---------+---------+---------+---------+

Designers who need to consolidate the designs of existing logic devices will diaw considerable benefit from SNAP's unique Boolean equation extractor. It take the design data from existing PLDs and converts it to the actual, corresponding Boolean equations, which can then be used as an ~ input to SNAP. It eliminates the need to find and re-enter design data, often a time-consuming process.
And for added convenience, SNAP features the powerful logic optimizer, Espresso Minimizer. Espresso automatically removes all unnecessary gates from your design, assuring that it will be the fastest and densest possible. Espresso allows you to pack more in - or fit it into a smaller PLO. The result can be substantial cost and power savings.

FULL SUPPORT NOW - AND
INTO THE FUTURE SNAP supports Philips broad line of PLDs, which includes high-speed PAL®-type devices, programmable logic arrays, programmable logic sequencers, and sophisticated programmable macro logic. It is fully compatible with SLICE, Philips entry-level design package. And as Philips introduces new PLDs in the future, SNAP will support those too, in a timely manner. You

can standardize on SNAP for your future development, with confidence.
Menu-driven and supported by clear, concise documentation, SNAP is a pleasure to use. But if problems do arise, Philips network of field applications engineers stand ready to help. Specially trained and backed by a comps of factory experts, Philips FAEs are stationed in all major cities in the
U.S. and overseas. Wherever you are, chances are that support is nearby.

PAL is a registered trademark of AMO/MM!, Inc.

January 26, 1993

514

Philips Semiconductors Programmable Logic Development Software
Synthesis Netlist Analysis Program

SNAP 1.9

SNAP Boolean Equation Extractor

FROM THIS:

LOOOO 1111111111111101110111101111111111111111 0000000000000000000000000000000000000000 0000000000000000000000000000000000000000 0000000000000000000000000000000000000000 0000000000000000000000000000000000000000 0000000000000000000000000000000000000000 0000000000000000000000000000000000000000 0000000000000000000000000000000000000000 1111111111111011111111111111111111011111

TO THIS:

@LOGIC EQUATION

S.D

=/(ASN*RWN*/DREQNl+S*/DREQNl);

AUTOMATICALLY

IMMEDIATELY

EFFORTLESSLY

PRODUCT SUPPORT
SLICE supports the Philips line of PLDs, which ranges from high-speed PAL devices to complex Programmable Macro Logic circuits. It will also support new Philips PLDs as they are introduced. The devices currently supported are:

Programmable Logic Arrays:

PLUS153

PLS100

PLUS173

Programmable Macro Logic:

PLHS501

PML2852

PML2552

Programmable Logic

Sequencers:

PLS155

PLC42VA12

PLS157

PLC415

PLS159

PLS105

PLS167

PLUS105

PLS168

PLUS405

PLS179

Programmable Array Logic

PLUS20L8

PLUS16L8

PLUS20R8

PLUS16R8

PLUS20R6

PLUS16R6

PLUS20R4

PLUS16R4

10H20EV8

PLQ22V10

10020EV8

PLC18V8Z

PHD48N22

PL22V10

PHD16N8

TRY IT - YOU'LL LIKE IT
Pop the enclosed SNAP demo disk into your computer and see how easy PLO design can be. The demo, like SNAP itself, runs on almost any IBM® PC or compatible having DOS 3.0 or higher, 640K RAM and a hard disk.

IBM is a registered trademark ol lntematlonal Business Machine& Corp.

January 26, 1993

515

Philips Semicond:ldors Programmable Logic Development Software
Synthesis Netlist Analysis Program

SNAP 1.9

-~ ... 0

123

2

~
~
<t---i
<J-i

!

~~rTM I
~-··QC:Q~~- ll4

..ifDll'o

~ .... ·4 I.-[] "4

]_ll4
]!_
Jl··

Xo. Xz,X.,Xa
@·W
X1, ~.Xi;,X7

·2 Og,

x2

~.

-u:. ~n Os i!Wli~J

v

0,

r.=========SNAP Resources Summary ========~

Cell name used/total

%

DIN501 18 I 32 56%

NIN501

7 I 32 21%

FBNAND 72 I 72 100%

NAND 34 I 44 77%

OUT501

2 I 4 50%

NOU501

4 I 8 50%

EX0501

8 I 8 100%

TOU501

4 I 4 100%

Please hit any key to continue ...

PLHS501 Resources

January 26, 1993

516

Philips Semiconductors Programmable Logic Development Software
Synthesis Netlist Analysis Program

SNAP 1.9

SNAP OVERVIEW
Philips SNAP (Synthesis Netlist Analysis and Program) is a software program used in implementing logic designs with Philips Programmable Logic Devices. The software runs on any IBM PS/2, AT, XT, or compatible computer. SNAP accepts the logic design specified in the form of schematics, EDlf' nedists, Boolean logic equations, and/or state equations; combines the different forms and different parts of the design into a single nedist; promJ)ts the user to select a target PLO; and generates the JEDEC fuse map used for programming the target PLO device.
Schematics can be created with either OrCAD SOT Ill, OrCAD SOT IV or DASH three schematic capture packages offered as options to SNAP. Logic and state equations can be created using any ASCII text editor. After you specify the design, SNAP converts the schematic, logic equations, and state equations into a single netlist. You can then use SNAP to perform the following functions:
· Create, display, and edit the stimulus waveforms for simulation
· Simulate the logic functions and timing
· Display and print the simulation results
· Determine the fault coverage for a given set of inputs
· Generate the test vectors
· Generate the fuse map for the target PLO device
· Generate a nedist of the PLO implementation for simulation
· Download the fuse map and test vectors to the PLO programmer

Specification of the logic design is independent of the type of PLO device. You can specify the design first and choose the PLO device later, after simulating and debugging the logic design. If the chosen device is unable to accommodate the design, it is a simple matter to sek!ct another device and generate the fuse map for that device. Alter this has been done, SNAP can generate a nedist and a set of logic equations directly from the final fuse map, allowing analysis and simulation of the final design as implemented in the target device. Also, a design using several PLO devices can be accurately simulated with the use of real delays.

Supported PLD Devices
The PLO devices supported by SNAP 1.8 are listed below, showing the part number, architecture (Inputs x Terms x Outputs), and number of pins for each device type.

Programmable Macro Logic (PML) Devices
PLHS501 104 x 116 x 24 52 pins PML2552 185 x 226 x 24 68 pins PML2852 185 x 226 x 40 84 pins

Programmable Logic Sequencer (PLS)

Devices

PLS155

16 x 45 x 12

PLS157

16 x 45 x 12

PLS159

16 x 45 x 12

PLS167

14 x 48 x

PLS168

16 x 45 x 12

PLS179 12 x 48 x

PLC42VA12 42 x 105 x 12

PLC415

17 x 68 x

20 pins 20 pins 20 pins 24 pins 20 pins 24 pins 24 pins 28 pins

PLS105

16 x 48 x

28 pins

PLUS105 PLUS405

22 x 48 x 24 x 64 x

28 pins 28 pins

Programmable Logic Array (PLA) Devices PLSlOO 16 x 48 x 8 28 pins PLUS153 18 x 42 x 10 20 pins PLUSl 73 22 x 42 x 10 24 pins

PAL Devices PLUS16L8 16 x 64 x PLUS16R8 16 x 64 x PLUS16R6 16 x 64 x PLUS16R4 16 x 64 x PHD16N8 16 x 16 x PLC18V8Z 18 x 74 x 8 PLUS20L8 20 x 64 x PLUS20R8 20 x 64 x PLUS20R6 20 x 64 x 8 PLUS20R4 20 x 64 x 8 10X20EV8 20 x 90 x PHD48N22 48 x 73 x 22 PL22Vl0 22 x 132 x 10 PLQ22Vl0 22 x 132 x 10

20 pins 20 pins 20 pins 20 pins 20 pins 20 pins 24 pins 24 pins 24 pins 24 pins 24 pins 68 pins 24 pins 24 pins

Before you can begin using SNAP, you must first install the software and learn the function keys and top-level menu. As part of the setup procedure, you specify the text editor and schematic capture software you are using with SNAP so that SNAP can invoke these programs as needed.

January 26, 1993

517

Philips Semiconductors Programmable Logic Development Software
Synthesis Netlist Analysis Program

SNAP 1.9

Overview of SNAP Process

OrCAD SOT IV are provided with the OrCAD Any of these schematic capture systems may

The OrCAD SOT IV and DASH schematic

SOT IV software package. Supplemental

be used for logic design purposes with SNAP.

capture systems are available as options to the SNAP software package.
OrCAD SOT IV is a complete schematic capture package, one of several design tools

information is provided in Appendix A of the User's Manual on configuring OrCAD SOT IV for compatibilty with SNAP.
DASH is Data 1/0 schematic capture

SNAP is an interactive, menu-driven software package. At the top level of the program is a graphical menu that allows selection of the desired SNAP operation. See Figure 5.

I,

offered by OrCad Systems Corporation. OrCAD SOT IV lets you create, edit, save, and print logic schematics. Schematic data files are accepted directly by the SNAP software. Instructions on installing and using

package. Schematic data files are accepted directly by the SNAP software. Instructions on installing and using DASH are provided in Appendix B of the User's Manual, serving as an addendum to the DASH User's Manual.

The boxes show the SNAP program operations that you can select. Operations may be performed at any time and in any order, provided that the input files for that operation are available.

SNAP 1.90 Copyright 1993 PHILIPS SEMICONDUCTORS All rights reserved

ScCapture

Abel2Snap

Equations

Minimizer

MacSel

NetGen

Edi f

NetConv

Project DEMO

16:35:21

Waveforms

TestVector

SimFlt

DPI

SimPrt

Plot

Use cursor keys to select module Use function keys to enter command

l:HELP 2:RUN 3:PROJECT 4:STATUS 5:SETUP 6:SAVE ?:DOS B:EDIT 9:PRINT lO:EXIT Figure 5. Top-Level SNAP Menu

January 26, 1993

518

Philips Semiconductors Programmable Logic Development Software
Synthesis Netlist Analysis Program

SNAP 1.9

1 ScCapture

.ABL Abel2Snap

.EQN .EQM .EQJ .EQQ
,I·.,.'.'°"" I

.EQN .EQM .EQJ .EQQ
Minimizer

.SCH

.EDF

.EQM

~'~

.MAC
B Waveforms .SCL

.MAC

.MAC

'S

.NET .EQQ
' S .MOD

.BIN

15 TestVector

s.VEC

.RES

n

'°'~__P_i_o_t--~

.FLT

.MAC

Bl Oo~H·< I

.USE .JED
"S"~

.MOD .EQJ

.JWV

.PRT

Figure 6. Order of Operations and Data Files

Figure 6 shows the typical order in which the SNAP program operations are executed. The figure also shows the file name extensions for the files produced by (and used by) the individual program operations. The menu options shown in bold boxes are the minimum required to specify a design and generate the fuse map. The remaining menu options may be used as needed for simulation and testing purposes.
In Step 1 (ScCapture), you specify part or all of the logic design with the schematic capture package (OrCAD SOT IV or DASH), using a library of logic elements recognized by SNAP. The design may be drawn hierarchically. In Step 2 (NetGen), SNAP converts the schematic into an intermediate netlist (.MAC file).

In Step 3 (Equations), you specify part or all of the logic design with Boolean logic equations and/or state equations. In Step 4 (Minimizer), an optional step, SNAP changes the form of the equations to minimize the number of gates necessary to implement the design. In Step 5 (NetConv), SNAP converts the logic and state equations into an intermediate netlist (.MAC file).
The complete design may be specified with any combination of schematic capture, logic
equations, and state equations. Different
parts of the design may be specified
separately. Each lower-level part of the design is a "macro" that can be used multiple times at a higher level of the hierarchy.

In Step 6 (Merger), SNAP combines the separate netlists (.MAC files) into a single master netlist (.NET file).
In Step 7 (SimNet), SNAP converts the master netlist into a binary-format file (.BIN file) that is accepted by the simulator.
In Step B (Waveforms), you use a graphical waveform editor to create the input signals for the simulation. SNAP converts the waveforms into the "Simulation Control Language" format (.SCL file).
In Step 9 (SimScl), SNAP simulates the logic operation and timing of the design using the input signals created previously. The resulting output signals are stored in a 'results" file (.RES file).

January 26, 1993

519

Philips Semiconductors Programmable Logic Development Software
Synthesis Netlist Analysis Program

SNAP 1.9

In Step 10 (Plot), SNAP displays the results graphically on the screen. You can analyze the simulation results in detail by adjusting the time range and time scale of the display.
Jn Step 11 (SimPrt), SNAP prints out the simulation results on the printer, monitor screen, or a disk file. You select the type of display (alphanumeric or graphic), the time range, and the time scale for the printout.
In Step 12 (Sim Flt), SNAP simulates the design with circuit faults, and reports the percentage of potential faults that can be detected with the given set of input test signals. Test signals may be specified as waveforms or by an ASCII file. A detailed fault coverage report is generated (.FLT file).
In Step 13 (Compiler), SNAP generates the fuse map for implementing the logic design. You select the PLO device type and then specify the input/output signal name associated with each device pin. SNAP optimizes the design for the selected device, generates the fuse map, and writes out the results in JEDEC format (.JED file). The percentage utilization of the on-chip PLO resources is reported on the screen and stored in a separate file (.USE).
In Step 14 (ModGen), SNAP takes the PLO device structure and fuse map, and generates a new netlist (.MOD file) based on the actual implementation of the logic design in the PLO device. This new netlist can be simulated in the same manner as the original design, allowing verification of the PLO implementation.

In Step 15 (TestVector), the test vectors (input signals and expected output signals) are converted to JED EC format. This information can be downloaded to the device programmer machine along with the fuse map (.VEC file).
In Step 16 (DPI), the Device Programmer Interface, SNAP downloads the fuse map and test vectors to the PLO programmer machine through a serial port. The programmer
machine uses the fuse map to program the
PLO device, and the test vectors to test the device after programming.
The programmed device operates as specified by the schematics, logic equations, and state equations created in Steps 1 and 3.
Many of the steps described above are optional. The minimum steps necessary for a project are either ScCapture and NetGen, or Equations and NetConv, to specify the logic design; Merger to make the netlist; Compiler to generate the fuse map; and DPI to download the fuse map to the device programmer. The other steps allow you to analyze and simulate the design, and to generate the test vectors.
Hardware and Software Requirements
SNAP requires the following computer resources:
· IBM PS/2, AT, XT or compatible computer
· MS-DOS operating system, version 3.0 or higher
· 640 Kbytes RAM

· Hard disk drive: 10 Mbytes (20 Mbytes or more preferred)
· Floppy disk drive
· Monitor: Hercules, EGA, or VGA recommended for schematic capture
· Text editor software
Installation
The SNAP software is provided on a set of floppy diskettes. Two functionally identical sets are provided: a 51/4 inch set and a 3112 inch set.
The files are stored on the diskettes in compressed-data format, so you cannot simply copy the files to the hard disk. Instead, use the installation program provided on the diskettes. Running the installation program is straightforward. The program takes care of creating a SNAP subdirectory (if it doesn't already exist), and automatically "decompresses" the SNAP files and transfers them to the hard disk.If you have an earlier version of SNAP installed on your system, first make a backup of all data files (if any) in your SNAP subdirectory. To ensure that you don't lose any valuable files, make a separate, complete backup of the SNAP subdirectory using the BACKUP command or a backup utility program. Then delete all the files from the SNAP subdirectory.
If you are upgrading from SLICE, you can install SNAP without removing SLICE. Once you are familiar with SNAP, you can delete SLICE from the hard disk.

January 26, 1993

520

Programmable Logic Devices

Section 10
Programmer/Software Support

CONTENTS

Philips Semiconductors PLO programming guide . . . . . . . . . . . . . . . . . . . . . . . . . . . .

522

PAL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

522

PLA Devices ................... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

522

PLS Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

522

PML Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

522

PLO programmer reference guide - Data 1/0 Corporation . . . . . . . . . . . . . . . . . . . .

524

PLO programmer reference guide - Stag Micro Systems, Inc. . . . . . . . . . . . . . . . . .

527

PLO programmer vendors contact guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

528

Approved software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

529

Third-par(y software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

530

ABEL...........................................................

530

CUPL...........................................................

532

PLOesigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

533

PLO software vendors contact guide . . . . . . . . . . . . . . . . .

534

PAL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

520

Phillps Semiconductors Programmable Logic Devices
Philips Semiconductors PLO programming guide

ADVANTEST ADVIN

PIE

BP MICROSYSTEMS

Phillps Semiconductors

R4971

PILOT-U84 UP2000

BP-1200 CP-1128

UNISITE

PRODUCT NAME

Revision

Revision

Revision

Software Revision

Software Revision

Revision

PAL® DEVICES

10H20EV8-4

-

10020EV8-4

-

PHD16N8-5

-

PHD48N22-7

-

PL22V10-10/-12/-15

-

PLC18V8Z-25/-35

-

PLUS16L8-71D ··

C50

PLUS16R4-7/D ··

C50

PLUS16R6-7/D ··

C50

PLUS16R8-7/D ··

C50

PLUS20L8-71D ··

C50

PLUS20R4-7/D ··

C50

PLUS20R6-7/D ··

C50

PLUS20R8-7/D ··

C50

PLADEVICES

-
10.16
-
10.32 10.16 10.16 10.16 10.16 10.16 10.16 10.16 10.16 10.16

2.25 2.25 2.25 2.25 3.00 2.25 2.25 2.25 2.25 2.25 2.25 2.25 2.25 2.25

2.22 2.22 2.22 2.22 2.22 2.22 2.22 2.22 2.22 2.22 2.22 2.22 2.22 2.22

1.78 1.78 1.78
-
1.81 1.78 1.78 1.78 1.78 1.78 1.78 1.78 1.78 1.78

4.2 4.2 2.8 3.4 3.5 *** 2.6"'** 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1

PLS100 PLS101 PLS153/153A PLS173 PLUS153-10/D/B PLUS173-10/D/B

C50

10.35

-

C50

10.35

-

2.22

1.78

2.2

2.22

1.78

2.2

C50

10.35

2.25

2.22

1.78

2.8

C50

10.35

2.25

2.22

1.78

1.7

C50

10.35

2.25

2.22

1.78

3.6

C50

10.35

2.25

2.22

1.78

2.3

PLS DEVICES

PLC415-16 PLC42VA12

-

-

2.25

2.21C

1.78

2.6

-

10.32

2.25

2.21C

1.78

3.5

PLS105/105A

C50

10.35

2.25

2.21C

1.78

1.5

PLS155

C50

10.35

2.25

2.21C

1.78

1.5

PLS157

C50

10.35

2.25

2.21C

1.78

1.5

PLS159A

C50

10.35

2.25

2.21C

1.78

3.0

PLS1671167A

C50

10.35

2.25

2.21C

1.78

1.5

PLS168/168A

C50

10.35

2.25

2.21C

1.78

1.5

PLS179

C50

10.35

2.25

2.21C

1.78

3.3

PLUS105-55/-45

C50

-

2.25

2.21C

1.78

4.2

PLUS405-55/-45/-37

C50

10.35

2.25

2.21C

1.78

4.2

PMLDEVICES

PLHS501/501I

-

PML2552-35/-50

-

PML2852-35/-50

-

-

2.25

-

-

2.25

-

-

3.0

-

-

1.7

-

2.8

-

3.8

· See individual programmer reference guide for more details. New revision listed is required if you wish to program the security fuse on the following products: PLUS20L8/R8/R6/R4 Rev. G or later PLUS16R8/R6/R4 Rev. I or later PLUS16L8 Rev.Kor later
··· Need version 4.0 for SO Package Support
®PAL is a registered trademark of Advanced Micro Devices, Inc.

DATAl/0* MODEL 2900 System Revision
1.5 1.5 1.5
-
1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5
1.5 1.5 1.5 1.5 1.5 1.5
1.5 1.6 1.0 4.3 4.3 1.5 1.5 1.5 1.5 1.6 1.6
1.7 1.7
-

MODEL 3900
System Revision
-
1.0 1.1 1.1 1.0 1.2 1.2 1.2 1.2 1.0 1.0 1.0 1.0
1.0 1.0 1.0 1.0 1.1 1.1
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
1.1 1.1 2.0

November 1993

522

Philips Semiconductors Programmable Logic Devices
Philips Semiconductors PLO programming guide

DATA 1/0* (continued)

MODEL 298

MODEL 60

303A..Q11A Revision

System Revision

PAL® DEVICES

-

-

-

-

V12

V15

-

-

V14

V1S

V09

V15

VOS

V14.2/19

VOS

V14.2119

VOS

V14.2/19

VOS

V14.2/19

VOS

V14.2/19

VOS

V14.2/19

VOS

V14.2/19

VOS

V14.2/19

PLADEVICES

vo5·

V01

vo5·

V01

V02

V12

V02

V12

V07

V15

V07

V15

PLSDEVICES

V10

V17.1

V12

V15

V02

V12

V02

V12

V02

V13

V02

V12

V02

V12

V02

V12

V02

-

V09

-

V07

-

PMLDEVICES

-

-

-

-

-

-

LOGICAL DEVICES

ALLPR040 ALLPR088

Software Revision

Software Revision

1.50C

2.10

1.50C

2.10

1.50C

2.10

-

2.10

-

-

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

1.50C

2.10

-

-

-

-

SMS SPRINT
PLUS
System Revision
3.5 3.5 3.5
-
-
3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5
3.5 3.5 3.5 3.5 3.5 3.5
3.5
-
3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5
-
-
-

STAG*
ZL30A
System Revision

STREBOR
PLP-S1A
Software Revision

SYSTEM GENERAL

SGUP-85A TURPR0-1

System Revision

System Revision

-

-

-

-

30A36

-

-

FD

30801

-

30A31

-

30A31/B07

-

30A31/807

-

30A31/807

-

30A31/807

-

30A31/807

-

30A31/807

-

30A31/807

-

30A31/B07

-

2.4

1.6S

2.4

1.6S

2.4

1.6S

-

1.6S

-

1.6S

2.4

1.6S

2.4

1.6S

2.4

1.6S

2.4

1.6S

2.4

1.6S

2.4

1.68

2.4

1.6S

2.4

1.6S

2.4

1.6S

30A01

-

30A01

-

30A01

-

30A01

-

30A40

-

30A40

-

-

-

-

-

2.4

1.6S

2.4

1.6S

2.4

1.6S

2.4

1.6S

30A34

-

30A34

-

30A01

-

30A01

-

30A01

-

30A25

-

30A01

-

30A01

-

30A27

-

30A37

-

30A31

-

-

1.6S

2.4

-

2.4

1.6S

2.4

1.6S

2.4

1.6S

2.4

1.6S

2.4

1.6S

2.4

1.6S

2.4

1.6S

-

-

2.4

1.6S

30A22

FA

-

FC

-

FD

2.4

1.6S

-

1.6S

-

1.6S

November 1993

523

Phlllpe Semiconductors Programmable Logic Device·
PLD programmer reference g.uide Data 110 Corporation

Data llO Corporation 10524 Willows Road, N.E. Redmond, Washington 98073-9746 Telephone Number: (800) 247-5700
Phlllpe Semiconductors

llODEL29B Adapter Revision

UNISITE

MODEL MODEL

llODEL60 Adapter Revision

Pan Number

Device Code

DIP

PLCC

Site Chip/ 2900 3900 System

40/48 Pin Site

Revision

DIP

PLCC

PHD

PHD16N8 PHD48N22

1B8F 303A-011A;V12 303A-0118;V05 V2c8

V3.4

1.6 1.0

- 096082

-

V3.4**** V3.4··

-

1.1

V15 360A001 360A006

-

-

-

ECL

10H20EV8

- 140138

-

10020EV8

- 140138

-

V2.7

V2.7

1.5

-

-

-

-

V3.0

T8D

1.5

-

-

-

-

PAL®

PLC18VBZ-35/-25 864F

303A-011A;V09 303A~0118;V04 V2.6

V2.8

1.5 1.0

V15 360A001 360A006

PL22V10

A628 303A-011A;V14 303A-0118;V04 V3.5

V3.5

1.5 1.1

V18 360A001 360A006

PLUS16L8

1817 303A-011A;V08 303A-0118;V04 V3.a· V3.s· 1.5 1.2 V14.2 360A001 360A006

PLUS16RSIR6/R4 1824 303A-011A;V08 303A-0118;V04 V3.a· V3.s· 1.5 1.2 V14.2 360A001 360A006

PLUS20L8

1826 303A-011A;V08 303A-0118;V04 V3.9· V3.9· 1.5 1.0 V14.2 360A001 360A006

PLUS20RSIR6/R4 1827 303A-011A;V08 303A-0118;V04 V3.9· V3.9· 1.5 1.0 V14.2 360A001 360A006

PLA PLS100/101 PLS100/101 PLS153/A

9601

303A-001 ;V01 -

-

-

1.0 1.0

-

--

9661

303A-001 ;V05 -

V2.2

V2.2

1.0 1.0

- V01 360A003

9665 303A-011A;V02 303A-0118;V02 v2.s

-

1.0 1.0

V01 360A002 A ONLY

PLS153/A PLS173 PLS173

9665 303A-001 ;V05 303A-0118;V02 V2.8

V2.8

1.0 1.0

V12 360A009 A ONLY

9676 303A-011A;V02 303A-0118;V02 V1.7

-

1.0 1.0

voe 360A002 -

9676 303A-001 ;V06 303A-011B;V02 V1.7

V1.7

1.0 1.0

V12

-

360A009

PLUS153B/D/-10 1865 303A-011A;V07 303A-0118;V03 V3.6

V3.6

1.0 1.1

V15 360A001 360A009

PLUS 1738/D/-10 1876 303A-011A;V07 303A-0118;V03 V2.3

V2.3

1.0 1.1

V15 360A002 360A009

PLS

PLC415-16

86AA 303A-011A;V10 303A-0118;V04 V2.6

V2.7

1.5 1.0 V17.1 360A003 T8D

PLC42VA12 PLS105/A PLS105/A PLS105/A

868A 303A-011A;V12 303A-0118;V05 V3.5

V3.5

1.6 1.0

V15 360A002 TBD

9603 303A-011A;V02 -

V1.5

-

1.0 1.0

V01 360A003 A ONLY

9603

- 303A-001 ;V01

-

-

1.0 1.0

V12

-

-

9663 303A-001 ;V05 303A-0118;V02 V1.5

-

1.0 1.0

-

360A003 -

PLS105/A

9663 303A-011A;V02 303A-0118;V02 V1.5

V1.5

1.0 1.0

V01

-

360A008

PLUS105-45/-55 1863 303A-011A;V09 303A-0118;V04 V3.6

V3.6

2.3 1.0

-

--

PLS155

9667 303A-011A;V02 303A-0118;V02 V1.5

-

1.0 1.0

- V01 360A002

PLS155

9667 303A-001 ;V05 303A-0118;V02 V1.5

V1.5

1.0 1.0

V12

-

360A009

PLS157

9668 303A-001 ;V05 303A-0118;V02 V1.5

-

1.5 1.0

- V13 360A002

PLS157

9668 303A-011A;V02 303A-0118;V02 V1.5

V1.5

1.5 1.0

V13

-

360A009

PLS159A PLS159A PLS167/A PLS167/A

6466 303A-011A;V02 303A-0118;V02 V3.0

V2.8

1.5 1.0

V12 360A002 360A009

- 6466

-

V3.0

-

1.5 1.0

-

-

-

9660 303A-011A;V02 303A-0118;V02 V1.5

V1.5

1.5 1.0

- V05 360A002

9660 -

-

-

-

1.5 1.0

V12

-

360A009

PLS168/A

9674 303A-011A;V02 303A-0118;V02 V1.5

V1.5

1.5 1.0

V05 360A002 -

PLS168/A

9674

- 303A-001 ;V06

-

-

1.5 1.0

V12

-

360A009

PLS179

9677 303A-011A;V02 303A-0118;V02 V3.3

V3.3

1.5 1.0

-

-

-

PLUS405-37/-45/-55 1879 303A-011A;V07 303A-011B;V04 V3.6

V3.6

2.3

1.7

-

-

-

November 1993

524

Philips Semiconductors Programmable Logic Devices
PLO programmer reference guide Data 1/0 Corporation

Phillps Semiconductors

MODEL29B Adapter Revision

UNISITE

MODEL MODEL

MODEL60 Adapter Revision

Part Number

Device
Code

DIP

PLCC

Site

Chip/ 2900 3900 System

40/48 Pin Site

Revision

DIP

PLCC

PML

PLHS501 PLHS502

1002

-

01C05E

-

PML2552-35/..SO 15908C

-

PML2852-35/-50 15918C

-

-

-

V1.7

-

1.1

-

--

-

V2.4*.. V3.2**

-

-

-

-

-

-

V2.8**** V3.1**

-

1.1

-

-

-

-

V3.s-··· V3.5

-

-

-

-

-

NOTES:

1. The software and hardware revisions listed are the first revisions released. All following revisions maintain support.

2. FOR UNISITE USERS: PLCC packages can be programmed on either the Chipsite or Pinsite adaptors.

3. FOR UNISITE USERS ONLY: Family codes listed above (the first two digits) must be preceeded with a "O" for PLCC packages. Pin codes

listed above (the last two digits) must be preceeded with a "7" or "6" for PLCC packages. Also, product name might be preceeded by "-FN".

4. * This version required to program security fuse on newer product.

Older parts can use Version 2.3 or later.

Pinsite adaptor required to program and functionally test these products without a DIP to PLCC adaptor.

Needs a 40-Pin DIP to 68-Pin PLCC adaptor available from Emulation Technology. Part Number: AS-68-40-0IP-6

Pinsite is also available for programming and functional testing without an adaptor.

Needs a 40-Pin DIP to 68-Pin PLCC adaptor that is available from Emulation Technology. Part Number: AS-68-40-04P-6

Pinsite is also available for programming and functional testing without an adaptor.

Needs a 40-Pin DIP to 84-Pin PLCC adaptor available from Emulation Technology Part Number: AS-84-40-0IP-6YAM

EMULATION TECHNOLOGY, INC.

23688 Walsh Avenue, Building D

Santa Clara, California 95051

Telephone No. (408) 982-0660

Fax. No.

(408) 982-0664

5. DEVICE CODE: XX.VY

XX= FAMILY CODE

YY=PIN CODE

®PAL is a registered trademark of Advanced Micro Devices, Inc.

November 1993

525

Phillps Semiconductors Programmable Logic Devices
PLO programmer reference guide Stag Micro Systems, Inc.

STAG MICRO SYSTEMS, INC.
Western Area: 1600 Waytt Drive, Suite 3 Santa Clara, CA 95054 (408) 988-1118
PHILIPS SEMICONDUCTORS PART NUMBER
PHO DEVICES PHD16N8-5
ECLDEVICES 1OH/10020EV8
PAL® DEVICES PL22V10-10/-12/-15 PLC18V8Z PLUS20L8D/-7 PLUS20R8D/-7 PLUS20R6D/-7 PLUS20R4D/-7 PLUS16L8D/-7 PLUS16R8D/-7 PLUS16R6D/-7 PLUS16R4D/-7
PLA DEVICES PLS100/101 PLS153/153A PLUS153B/D/-10 PLS173 PLUS 1738/D/-10
PLS DEVICES PLS105/105A PLUS 105-451-55 PLC415 PLC42VA12 PLS155 PLS157 PLS159A PLS167/167A PLS168/168A PLS179 PLUS405-37/-45/-55
PMLDEVICES PLHS501

DEVICE CODES

FAMILY CODES

PIN CODES

10

167

--

--

12

070

12

205

11

56

11

57

11

58

11

59

11

29

11

30

11

31

11

32

13

00

14

05

11

05

15

96

11

96

13

02

11

02

12

177

12

197

14

06

14

07

13

08

15

91

15

97

15

130

11

138

10

133

MODEL ZL30
(DIP ONLY)
30A36
--
--
30A34 30A31 30A31 30A31 30A31 30A31 30A31 30A31 30A31
30A01 30A01 30A39S 30A01 30A39S
30A01 30A39 30A34 30A45 30A01 30A01 30A25 30A01 30A01 30A27 30A31
NIA

Eastern Area: 3 Northern Blvd., Suite B4 Amherst, NH 03031 (603) 673-4380
MODEL ZL30A

SYSTEM REVISION

PLCC ADAPTER

30A36
--

30A001
--

30B01 30A34 30A31/B07 30A31/B07 30A31/B07 30A31/B07 30A31/B07 30A31/B07 30A31/B07 30A31/B07

TBA 30A001 30A001 30A001 30A001 30A001 30A001 30A001 30A001 30A001

30A01 30A01 30A39S 30A01 30A39S

30A001 30A001 30A001
TBA TBA

30A01 30A37 30A34 30A45 30A01 30A01 30A25 30A01 30A01 30A27 30A31

30A001 30A001 30A001 30A001 30A001 30A001 30A001 30A001 30A001 30A001 30A001

30A22+

30A101

NOTES: The software and hardware revisions listed are the earliest revisions that support these products. Later revisions can also be assumed to support these products. · Requires 30A101 adaptor; includes PLCC support. 1. The second revision listed is required if you wish to program the security fuse on the following products:
PLUS20L8/R8/R6/R4 Rev. G or later PLUS16R8/R6/R4 Rev. I or later PLUS16L8 Rev. Kor later

April 1992

527

Phlllpe Semiconductors Programmable Logic Devices
PLO programmer vendors contact guide

COMPANY Advin Systems American Reliance
Aval Data
B&C Microsystems Basic Computer Systems AG BP Microsystems Datal/O Eden Engineering
Elan Digital Systems Hilo/Tribal
Microsystems Logical Devices
Minato
Red Square Co. SMS
Sprint Plus/Expert
Stag Micro Systems, Inc. Strebor
PML Support Only ByTek
Sunrise Electronics System General
Xeltek
November 1993

LOCATION
1050-L E. Duane Avenue Sunnyvale, CA 94086
9952 Eash Bladwin Place El Monte, CA 91731
Daisan-Maruzen Building 6-16-6 Nishishinjuku Shinjuku-ku, Tokyo Japan 160
750 N. Pastoria Avenue Sunnyvale, CA 94086
Wolfgang-Pauli-Gasse A-1140 Klagenlurt-Auhof,
Austria
1000 North Post Oak Rd. Suite 225 Houston, TX 77055
10525 Willow Road, N.E. Redmond, WA 98073-9746
12505 Loma Rica Drive Grass Valley, CA 95945
538 Valley Way Milpitas, CA 95035
44388 S. Grimmer Blvd. Fremont, CA 94538
692 South Military Trail Deerfield Beach, FL 33442
3628 Madison Avenue, Suites
North Highlands, CA 95660
2098 South Grand Avenue Suite H
Santa Ana, CA 92705
P.O. Box 3159 Redmond, WA 98073-3159
SMS - G. Steudel Im Morgental 13 D--B994 Hergatz, Germany
1600 Wyatt Drive, Suite 3 Santa Clara, CA 95054
1008 North Nob Hill Drive America Fork, UT 84003
543 N.W. 77th Street Boca Raton, FL. 33487
524 South Vermont Glendora, CA 81740
510 South Park Victoria Dr. P.O. Box 361898
Milpitas, CA 95036-1898
757 No Pastoria Avenue Sunnyvale, CA 94086

PERSON TO CONTACT
Wing F. Hui (408) 243-7000
John Goosseff Tel: (800) 654-9838
(818) 575-5110
Toshiko Ishii 03-3344-2001

CERTIFICATION Pending update
75%done Vendor to provide equipment
Vendor to provide equipment

(408) 730-5511
Tel: +43-222-9736360 Fax: +43-222-975915
Bill Cates (800) 225-2102 Fax# (713) 461-7413
(800) 24 7-5700
Dan Mower (916) 272-2770
(800) 541-ELAN (408) 946-8495
Robert Kruger (510) 623-8860
Joleen Rasmussen (800) 331-7766 (305) 428-6868 (FL only)
Tel: (916) 348-6066 Fax: (916)348-0926
Stanley Fiala (714) 751-1373
Bob Young (206) 883-8447
Tel: +49-7522-4460 Fax: +49-7522--B929
Terry Hepner (408) 988-1118
Larry Roberts (801) 756-3605
Buddy Fanner 800-523-1565
Anh Le (818) 914-1926
Tim Morse (408) 263-6667
Young Oh (408) 745-7974 (800) 541-1975

Pending new update
Certified 4/89 UP2000
Certified PLD1100, CP1128
Certified Model 29/60 UNISITE, S1000, 2900, 3900 Vendor to provide equipment
Pending new update
Pending new update
ALLPR040 Certified 7/91
Certified System 1891 & 1910
Vendor to provide equipment Certified
Sprint Plus
Certified ZL30A Certified PLP-S1/S1A Vendor to provide EQ.
Vendor to provide equipment
Certified - SGUP-85/85A TURPR0-1
Pending new update

528

Phlllpa Semiconductors Programmable Logic Devices
Approved software suppon

PHILIPS

ACUGEN

PHILIPS PRODUCT NAME

SLICE

SNAP

ATGEN

Rev

Rev

Rev

PAL® DEVICES

10H20EV8-4

1.0

1.6

10020EV8-4

1.0

1.6

PHD16N8-5

1.0

1.6

PHD48N22-7

1.0

1.6

PL22V10-10/-12/-15

1.05

1.8

PLC18VBZ-25/-35

1.05

1.8

PLUS16L8-7/D

1.0

1.6

PLUS16R4-7/D

1.0

1.6

PLUS16R6-7/D

1.0

1.6

PLUS16R8-7/D

1.0

1.6

PLUS20L8-7/D

1.0

1.6

PLUS20R4-7/D

1.0

1.6

PLUS20R6-7/D

1.0

1.6

PLUS20R8-7/D

1.0

1.6

2.47 2.47 2.47
-
2.47
-
2.47 2.47 2.47 2.47 2.47 2.47 2.47 2.47

PLADEVICES

PLS100 PLS101 PLS153/153A PLS173 PLUS153-10/0/B PLUS173-1 O/D/B

1.05

1.8

1.05

1.8

1.0

1.6

1.0

1.6

1.0

1.6

1.0

1.6

2.47 2.47 2.47 2.47 2.47 2.47

PLS DEVICES

PLC415-16

1.0

1.6

PLC42VA12

1.05

1.8

PLS105/105A

1.0

1.6

PLS155

1.05

1.8

PLS157

1.05

1.8

PLS159A

1.05

1.8

PLS167/167A

1.05

1.8

PLS168/168A

1.05

1.8

PLS179

1.05

1.8

PLUS105-551-45

1.0

1.6

PLUS405-55/-45/-37

1.0

1.6

2.47 2.47 2.47 2.47 2.47 2.47 2.47 2.47 2.47 2.47 2.47

PMLDEVICES

PLHS501/501I PML2552-35/-50 PML2852-35/-50

1.0

1.6

2.47

1.0

1.6

-

1.05

1.8

-

®PAL is a registered trademark of Advanced Micro Devices, Inc. · See individual software guide.

DATAl/O
ABEL·
Rev
3.1 3.1 4.0 4.0 3.1 4.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1
3.1 3.1 3.1 3.1 3.1 3.1
4.0 4.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1
3.1
-

ISDATA LOG/IC
Rev

LOGIC DEV CUPL· Rev

3.4

4.2A

3.4

4.2A

3.3

2.50A

3.6

4.2A

3.4

2.11A

3.4

4.2A

3.3

1.01A

3.3

1.01A

3.3

1.01A

3.3

1.01A

3.3

2.0A

3.3

2.0A

3.3

2.0A

3.3

2.0A

3.3

2.0A

3.3

2.0A

3.3

2.15A

3.3

2.15A

3.3

2.15A

3.3

2.1A

-

4.0A

-

4.2A

3.3

2.0A

3.3

2.0A

3.3

2.0A

3.3

2.0A

3.3

2.0A

3.3

2.1A

3.3

3.0A

3.3

3.0A

3.3

3.0A

-

3.2A

-

-

-

-

MINC PL· Designer Rev
2.1 2.1 2.1
-
3.0 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1
2.1 2.1 2.1 2.1 2.1 2.1
2.1
-
2.1 2.1 2.1 2.1 2.1 2.1 2.1 3.0 2.1
-
-

April 1992

529

Phillps Semiconductors Programmable Logic Devices
Third-party software support

ABEL
Data l/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073--9746 Telephone: (206) 881-S444

PART NUMBER

TYPE

PACKAGE

10020EV8

PAL®

DIP

10020EV8

PAL

PLCC

10H20EV8

PAL

DIP

10H20EV8

PAL

PLCC

PHD16N8

PAL

DIP

PHD16N8

PAL

PLCC

PHD48N22

PAL

PLCC

PL22V10

PAL

DIP

PL22V10

PAL

PLCC

PLC18V8Z

EPLD

DIP

PLC18V8Z

EPLD

PLCC

PLC415

FPLS

DIP

PLC415

FPLS

PLCC

PLC42VA12

FPLS

DIP

PLC42VA12

FPLS

PLCC

PLHS501

PML

PLCC

PLS100

FPLA

DIP

PLS100

FPLA

PLCC

PLS101

FPLA

DIP

PLS101

FPLA

PLCC

PLS105/105A

FPLS

DIP

PLS105/105A

FPLS

PLCC

PLS153/153A

FPLA

DIP

PLS153/153A

FPLA

PLCC

PLS155

FPLS

DIP

PLS155

FPLS

PLCC

PLS157

FPLS

DIP

PLS157

FPLS

PLCC

PLS159A

FPLS

OIP

PLS159A

FPLS

PLCC

PLS1671167A

FPLS

DIP

PLS167/167A

FPLS

PLCC

PLS168/168A

FPLS

DIP

PLS168/168A

FPLS

PLCC

PLS173

FPLA

DIP

PLS173

FPLA

PLCC

PLS179

FPLS

DIP

PLS179

FPLS

PLCC

PLUS105

FPLS

DIP

PLUS105

FPLS

PLCC

PLUS153

FPLA

DIP

PLUS153

FPLA

PLCC

PLUS16L8

PAL

DIP

PLUS16L8

PAL

PLCC

PLUS16R4

PAL

DIP

PLUS16R4

PAL

PLCC

PLUS16R6

PAL

DIP

PLUS16R6

PAL

PLCC

PLUS16R8

PAL

DIP

PLUS16R8

PAL

PLCC

PLUS173

FPLA

DIP

PLUS173

FPLA

PLCC

®PAL 1s a registered trademark of Advanced Micro Devices, Inc.

April 1992

530

#PINS
24 28 24 28 20 20 68 24 28 20 20 28 28 24 28 52 28 28 28 28 28 28 20 20 20 20 20 20 20 20 24 28 24 28 24 28 24 28 28 28 20 20 20 20 20 20 20 20 20 20 24 28

DEVICE FILE
EC20EV8A EC20EV8AC EC20EV8A EC20EV8AC P16N8 P16N8 P48N22 P22V10 P22V10C P18V8Z P18V8Z F415 F415 F42VA12 F42VA12 PML501 F100 F100 F100 F100 F105 F105 F153 F153 F155 F155 F157 F157 F159 F159 F167 F167C F168 F168C F173 F173C F179 F179C F105 F105 F153 F153 P16L8 P16L8 P16R4 P16R4 P16R6 P16R6 P16R8 P16R8 F173 F173C

ABEL REV.
3.1 4.2 3.1 4.2 4.0 4.0 4.0 3.4 3.4 4.1 4.1 4.0 4.0 4.1 4.2 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 4.2 3.1 .4.2 3.1 4.2 3.1 4.2 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 4.2

Philips Semiconductors Programmable Logic Devices
Third-party software support

ABEL- Data 1/0 Corporation (CONTINUED)

PART NUMBER
PLUS20LB PLUS20LB PLUS20R4 PLUS20R4 PLUS20R6 PLUS20R6 PLUS20R8 PLUS20R8 PLUS405 PLUS405

TYPE
PAL PAL PAL PAL PAL PAL PAL PAL FPLS FPLS

PACKAGE
DIP PLCC DIP PLCC DIP PLCC DIP PLCC DIP PLCC

#PINS
24 28 24 28 24 28 24 28 28 28

DEVICE FILE
P20LB P20LBC P20R4 P20R4C P20R6 P20R6C P20R8 P20R8C F405 F405

ABEL REV.
3.1 4.1 3.1 4.1 3.1 4.1 3.1 4.1 3.1 3.1

April 1992

531

Philips Semiconductors Programmable Logic Devices
Third-party software support

CUPL
Logical Devices, Inc. 1201 N.W. 65th Place Ft. laudedale, FL 33309 Telephone: (305) 974-0967

PART NUMBER
10020EV8 10H20EV8 828100 828101 82S105/105A 828153/153A PHD16N8 PHD48N22 PLC18V8Z PLC415 PLC42VA12 PLHS501 PLS100 PLS101 PLS105/105A PLS153/153A PLS155 PLS157 PLS159A PLS167/167A PLS168/168A PLS173 PLS179 PLUS105-451-55 PLUS153B/D/-10 PLUS16L8Dl-7 PLUS16R4Dl-7 PLUS16R6Dl-7 PLUS16R8Dl-7 PLUS 1738/D/-10 PLUS20L8D/-7 PLUS20R4D/-7 PLUS20R6D/-7 PLUS20R8D/-7 PLUS405 PL22V10

DEVICE MNEMONIC
P1020EV8 P1020EV8 F100 F100 F105 F153 P16N8 F48N22 F18V8Z F415 F42VA12 F501 F100 F100 F105 F153 F155 F157 F159 F167 F168 F173 F179 F105 F153 F16L8 P16R4 P16R6 P16R8 P173 P20L8 P20R4 P20R6 P20R8 F405 P22V10

#PINS
24 24 28 28 28 20 20 68 20 28 24 52 28 28 28 20 20 20 20 24 24 24 24 28 20 20 20 20 20 24 24 24 24 24 28 24

#FUSES
3616 3616 1928 1928 3553 1842
512 7008 2689 5751 8994 15780 1928 1928 3553 1842 2108 2108 2108 3361 3553 2178 2452 3553 1842 2048 2048 2048 2048 2178 2560 2560 2560 2560 5410 5828

#OFP-TERMS
80 80 48 48 48 42 16 73 72 68 10 112 48 48 48 42 43 43 43 48 48 42 43 48 42 64 64 64 64 42 64 64 64 64 64 130

CUPLREV.
4.2a 4.2a 2.00a 2.00a 2.00a 2.15a 2.50a 4.2a 4.2a 4.0a 4.2a 3.2a 2.00a 2.0oa 2.00a 2.15a 2.ooa 2.00a 2.00a 2.ooa 2.10a 2.15a 3.0a 3.0a 2.15a 1.01a 1.01a 1.01a 1.01a 2.10a 2.00a 2.00a 2.00a 2.00a 3.0a 2.11a

April 1992

532

Philips Semiconductors Programmable Logic Devices
Third-party software support

PLDeslgner
Mine, Incorporated 6755 Earl Drive Colorado Springs, CO 80918 Telephone: (719) 590-1155
PART NUMBER PLS100 PLS101 PLS153/153A PLUS153 PLS173 PLUS173 10020EV8-4 10H20EV8-4 PLUS16LB PHD16N8-5 PLUS16R4 PLUS16R6 PLUS16R8 PLC18VBZ35 PLUS20LB PLUS20R4 PLUS20R6 PLUS20RB PL22V10 PLS105/105A PLUS105 PLS155 PLS157 PLS159A PLS167/167A PLS168/16BA PLS179 PLUS405 PLC415

TEMPLATE NAME A100 A100 A153 A153 A173 A173 P20EV8 P20EV8 P16LB P16NB P16R4 P16R6 P16R8 P18V8S P20l8 P20R4 P20R6 P20R8 P22V10 S105 S105 S155 S157 S159 S167 S168 S179 S405 S415

TECHNOLOGY TTL TTL TTL TTL TTL TTL ECL ECL TTL TTL TTL TTL TTL CMOS TTL TTL TTL TTL CMOS TTL TTL TTL TTL TTL TTL TTL TTL TTL CMOS

PACKAGES DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC CDIP/PLCC CDIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/CDIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/PLCC DIP/CDIP/PLCC

REVISION 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 3.0 2.1 3.0 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1

Anril 1!lQ?

533

Philips Semiconductors Programmable Logic Devices
PLO software vendors contact guide

PRODUCT

LOCATION

CONTACT NUMBER

·Philips Semiconductors SNAP

811 E. Arques Avenue Sunnyvale, CA 94088

(800) 451-6644 Bulletin board #

ACUGEN Software, Inc.
ATGEN

427-3 Amherst St., Ste. 391 Nashua, NH 03063

(603) 881-8821

Datal/O ABEL

10525 Willow Rd., N.E. Redmond, WA 98073-9746

(800) 247-5700

Logical Devices CUPL

1201 N.W. 65th Place Ft. Lauderdale, FL 33309

(800) EE1-PROM

Daisy/Cadnetix PLO Master

5775 Flatiron Parkway Boulder, CO 80301

(303) 444-8075

MINC PLO Designer

6755 Earl Drive Colorado Springs, CO 80918

Michael 0. Watry (719) 590-1155

Mentor Graphics Corp. PLO Synthesis

8500 S.W. Creekside Place Beaverton, OR 97005

(503) 626-7000

OrCAD Systems ORCAD/PLD

1049 S.W. Baseline St., Suite 500
Hillsboro, OR 97123

(503) 640-9488

ISDATA LOG/ic

ISDATAGmbH Daimlerstr. 51 D-7500 Karlsruhe 21
Germany

Tel: +49-721-751087 Fax: +49-721-752634

Logic Automation

19500 N.W. Gibbs Drive P.O. Box310
Beaverton, OR 87075

(503) 690-6900

The SNAP phone number connects to the SPG bulletin board. Compatible with 1200/2400 baud modems, messages can be left, problem files uploaded, and solution files downloaded.

April 1992

534

Programmable Logic Devices

Section 11
Application Notes

PAL Devices
AN043 AN031 AN044 AN045 AN219

Introduction . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

10H/10020EV8 high-speed (4.4ns) EGL PLO . . . . . . . . . . .

542

PHD4BN22 high speed (7.5ns) 32-bit programmable decoder . . 553

68030 system decoding . . .

559

High speed 8-bit parallel to serial converter . . . . . . . . . .

564

A Metastability Primer . . . . . . . . . . . . . . . . . . . . . . . . . . . .

568

PLA Devices

Introduction .

571

AN046

Quick PLA ...

575

AN014

Latches and flip-flops with PLS153 ......... .

580

AN024

PLS 173 as a 10-bit comparator, 74LS460

583

AN021

9-Bit parity generator/checker with PLS153/153A

584

Sequencer Devices

Introduction

590

AN023

PLS 168/168A Primer

602

AN047

Alarm Controller

615

AN028

High-speed 12-bittracking AID converter using PLS179 ..

622

AN048

Interrupt Handler ............. .

633

AN034

PLUS405-55 -the ideal high speed interface .

637

AN032

Minimize metastability in 50MHz state machines

652

AN050

Implementing Counters in Sequencer Devices .

660

CMOS Sequencers

Introduction

............. .

666

AN0301

CMOS power in PLDs .

673

AN0302

Microcontroller power management

676

AN0303

Motor controller

680

AN0304

OMA controller

685

AN036

12C bus expander

688

AN037

ISDN peripheral control

710

PML Devices AN029 AN049
AN038 AN039 AN040 AN035 AN042 AN041

Introduction: Designing with programmable macro logic .. .

724

Programmable macro logic primer

............ . 737

PLHS501 design examples ..

750

8-Bit Barrel Shifter ...

756

12-Bit Comparator with Dual 1-of-8 Decoders ..

761

8-Bit Carry Look-Ahead Adder ...

764

32- to 5-Bit Priority Encoder .

767

4-Bit Synchronous Counter

770

VME Bus EPROM Interface .............. .

772

Micro Channel Interface ...

779

NuBus Interface .

784

Data Bus Parity

791

16-Bit Comparator ...

795

12c 110 ports

797

i2C bus monitor ..

813

Switching control unit for data communication via RS232

819

Microcontroller acceleration

831

Implementing counters in PML2X52 devices

845

Serial data encoder and decoder ..

853

Philips Semiconductors Programmable Logic Devices
PAL devices

INTRODUCTION
Philips Semiconductors provides state-of-the-art industry standard PAL® devices, both bipolar and CMOS. The range of offers spans the entire gamut of performance options; zero-standby power generic devices specified over the commercial, industrial and military temperature ranges, or the ultimate in high speed, an ECL compatible 20EV8 device. Almost every option in between is also offered.
The PAL architecture consists of a programmable AND array, followed by a fixed OR array as shown in Figure 1. The somewhat rigid architecture lends itself to less complex, narrower logic functions. There are three basic PAL-type device configurations. The XXL8 devices are strictly combinatorial. The XXRX series offers a

range of registered and combinatorial outputs.
The XXV8 series is considered to be generic in nature, in that the output macros are variable (hence the "V") as combinatorial or registered. Most frequent applications include counters and shifters (the RX series), and small decoders and multiplexers (the L8 series).
The 22V10 is a popular PLO architecture. Philips Semiconductors offers both CMOS and BiCMOS versions of this device. The PL22V1 Ois an electrically erasable CMOS implementation. The PLQ22V10 is a low-noise, high-speed BiCMOS version with additional improved circuit characteristics.
In addition to the standard devices just described, Philips Semiconductors also offers devices tailored for specific applications. The PHD48N22 is an expanded high-speed

PAL-type architecture device, with up to 48 inputs, 22 outputs and a 7.5ns propagation delay, it is optimized for very wide decoding applications. Another decoder, the PHD16N8 is optimized for decoding speed by removing the OR array.
If you are designing using ECL, Philips Semiconductors offers the 1OH20EV8/10020EV8. This device provides 8 outputs which may be individually configured for registered or combinatorial operation. It al8o features ultra high-speed operation with a !po of 4.5ns and a IMAX of 108MHz. An application note in this section demonstrates how to implement various circuits in a 20EV8 device.
Industry standard software can be used with Philips Semiconductors PAL-type devices. Full support is also provided via the Philips Semiconductors SNAP Design software.

10

12.

11

2.

12

2

-v

13

2.

14

~

15

2

PROGRAM MABLE

>-

AND ARRA11

FIX
CONNoEr~nTION { AR RAY

Figure 1. PAL Architecture

00
-D-- 01
02
03

®PAL Is a registered trademark of Advanced Miao Devices, Inc. October 1993

537

Philips Semiconductors Programmable Logic Devices
PAL devices

The PLUS16L8D and-7
The PLUS16L8D and-7 PAL-type devices are functionally identical to other commercially available 16L8 PAL ICs. Figure 2 shows an extremely simplified version. Less flexible than a PLA, the PLUS16L8D/-7 provides raw speed and current drive so important for driving SAAM arrays on RISC processors or the control/data lines on rapid bus strucbJres. The PLUS16L8D has a worst-case propagation delay of 10ns. The worst-case !po of the -7 is 7.Sns. 24;mA output drive is guaranteed.

The PLUS16L8D/-7 have seven product

terms per OR function and one per 3-$tate

control. Six of the eight outputs can be

configured as inputs or outputs. The

PLUS16L8D/-7 are available in 20-pin plastic

DIL or 20-pin PLCC packages.

.

PLUS16l8D

Figure 2. PLUS16L8 (D and -7)

October 1993

538

Philips Semiconductors Programmable Logic Devices
PAL devices
The PLUS16R8D and -7
The PLUS 16RSD and -7, like the PLUS16LBD and-7 is identical to other manufacturers' registered PAL devices. The parts have eight inputs, eight outputs, and eight D-flip-flops. Each flip-flop feeds an output pin through a 3-State buffer. The
output of each D-flip-flop, 0, is also fed back
to the AND array. Each output is capable of driving 24mA loL max, with all ouputs simultaneously asserted. The PLUS16RBD has a worst-case propagation delay of 1Ons. The worst-case !po of the -7 is 7.5ns. The PLUS16RBD and -7 are available in 20-pin plastic DIP and 20-pin PLCC.

eLK lo
12 13 14 15 Is 17 GND

PLUS16R80

Vee 07 Os 05
C4
03 02 01 Oo OE

Figure 3. PLUS16R8 (D and -7)

Philips Semiconductors Programmable Logic Devices
PAL devices
The PLUS20L8D and -7
The PLUS20LBD and -7 devices have 14 inputs, two dedicated outputs and six bidirectionals. The tpD are 10ns max and 7.Sns max, respectively. The 24mA of output low current of these devices can drive capacitive address line inputs and pc-board traces through long layouts. This makes the particularly suitable for driving SAAM, video DRAM, and FAST dynamic RAM arrays in 32-bit microprocessor environments.
Identical to other commercially available 20L8 PAL devices, the PLUS20LBD and -7 have 56 functional product terms which are hard-wired to eight OR gates. Each OR gate drives an Active-Low output. The 3-State control of each output is from a dedicated AND product term.
The worst-case propagation delays for the PLUS20L8D and 20L8-7 are 10ns and 7.Sns, respectively.

19 110 GND

PLUS20L8D
Vee
113 07 85 85 84 83 82 81
Clo
112 111

Figure 4. PLUS20L8 (D and -7)

October 1993

540

Philips Semiconductors Programmable Logic Devices
PAL devices

CLK
lo 11 12 13
'4
15 Is 17 19 lg GND

PLUS20R8D
Vee 111 07
Os 05 04 03 02 01 Oo 110 OE

Figure 5. PLUS20R8 (D and -7)

The PLUS20R8D and -7
The PLUS20R8D and -7 are 24-pin versions of the 16R8 PAL device. With propagation delays of 1Ons and 7.5ns max, the parts deliver 24mA of output low current drive. Eight D-flip-flops share a common clock and output enable line. The output of each flip-flop is dedicated to a separate output pin and is also fed back to the AND array.
The PLUS20R8D and -7 are available in 24-pin plastic OIL and 28-pin PLCC.

The PLC18V8Z
The PLC18V8Z is a multi-function, generic PAL-type device. It is pin-compatible with, and can replace 22 different 20-pin registered and combinatorial PAL devices. To accomplish this, the conventional 'single function' output pin has been replaced by a configurable Output Macro Cell. Each Macro Cell contains a D-flip-flop or a combinatorial 1/0 path. Output polarity and 3-State control functions are also individually configurable.

Each OMC is fed by nine AND product terms, which are hard-wired in the classic PAL fashion.
One of the key features of the part is its ability to sink 24 milliamps loL. compatible with other bipolar PAL devices-yet still comply with internal CMOS circuitry. The UV erasable version is available in 20-pin ceramic DI L with a quartz window.

October 1993

541

Philips Semiconductors Programmable Logic Devices
1OH/10020EV8 high-speed (4.4ns) ECL PLO

Application Note
AN043

INTRODUCTION
ECL designers have never had enough chips to complete high performance designs. Period. The TTL and CMOS designers always had full MSI and LSI catalogs to rely on, and the ECL guys only had a handful of chips, to solve the hardest technological problems yet! But, that's all changed with the introduction of the Philips Semiconductors PALTM 20EV8. Here's how.
Philips Semiconductors 1OH/10020EV8 PAL devices are two 24-pin PLDs which can be configured to perform a whole catalog of

parts in just two ICs. Whether you need to do simple decoding, multiplexing, counting, shifting or form complex state machines, these extraordinary parts can do it all. You can think of them as equivalents to these valuable functions, or as an empty canvas to paint your own catalog on. Don't be frustrated by the nonavailable entries in your ECL catalog, go ahead and roll your own!
Designers don't have time to read lengthy application notes, so this one was created to show you exactly how to make the basic

functions you'll probably need. First, there is a single page description of the parts. Then, there is a series of four application briefs showing the exact equations, pinning, internal resource usage and simulation files for the basic mux, decoder, shifter and counter. These design files are created using Philips Semiconductors SNAP and SLICE syntax, which is simple: ·=AND, +=OR and /=INVERT These products are also supported on Data 1/0 ABELTM, which has a similar syntax.

SNAP RESOURCE SUMMARY DESIGNATIONS

PROGRAMMABLE AND ARRAY (90 x40)

PRE SE

F

F

F

Output Logic Macrocell

PAL is a registered trademark of Advanced Micro Devices. ABEL is a trademark of Data 1/0 Corporation.

October 1993

542

Philips Semiconductors Programmable Logic Devices
1OH/10020EV8 high-speed (4.4ns) ECL PLO
10H/10020EV8 LOGIC DIAGRAM

Application Note
AN043

NOTES: 1. .~!I unprogrammed or virgin "AND" gate locations are pulled to logic MO" 2. ::::::=· Programmable conned:ions 3. Pinout for F Package
October 1993

543

ASYNCHRONOUS PRESET

Philips Semiconductors Programmable Logic Devices
1OH/10020EV8 high-speed (4.4ns) ECL PLD

Application Note
AN043

Design Brief #1: Three-To-Eight Decoder Using SNAP/SLICE

@PINLIST

DESIGN FROM DECODE.N2 FOR

AO I;Al I;A2 I; OUTO O;OUTl O;OUT2 O;OUT3 O;OUT4

PIN FILE

DEVICE 1OX20EV8

O;OUTS O;OUT6 O;OUT 7 0;

Oev;i.ce =

OX20EV8

Cell Na.ma Used/Total

%

@GROUPS @TRUTHTABLE

Pinl = AO

CKE VB

oI 1

0%

I

@LOGIC EQUATIONS

OUTO =/

( /A2* /Al* /AO);

Pin2 = Al

DINEV8

3 I 28

10%

OUTl =/ OUT2 =/ OUT3 =/

( /A2* /Al* AO); ( /A2* Al* /AO); ( /A2* Al* AO);

Pin4 = PinS =

OUTO OU T l

NINEV8

3 I 28

10%

AND

16 I 90

17%

OUT4 =/ OUTS =/

( A2* /Al* /AO); ( A2'1< /Al* AO);

Pin? = OUT2

OR

8I 8

100%

OUT6 =/

( A2* Al* /AO);

Pin8 = OUT3

OLMDIR

aI a

100%

OUT7 =/

( A2* Al* AO);

@INPUT VECTORS

Pin9 = A2

OLM INV

0I 8

0%

@OUTPUT VECTORS @STATE VECTORS

Pin17 = OUT4

OLMREG

0I 8

0%

@TRANSITIONS

Pin18 = OUTS

DFFEVB

0I 8

0%

Pin20 = OUT6

OUTEVB

8I 8

100%

Pin21 = OUT7

Design Brief #1:, Three-To-Eight Decoder Using ABEL

module_decode;

decode device 'ec20ev8a';

a0,al,a2

pin 1,2,9;

out0,outl,out2,out3 pin 4,5,7,8;

out4,out5,out6,out7 pin 17,18,20,21

inputs= [a2,al,a0]; H,L = 1,0;

equations

outO ! (inputs=O);

outl

(inputs=l);

out2

(inputs==2);

out3

(inputs==3);

out4

(inputs==4);

outs

(inputs==S);

out6

(inputs==6);

out7

(inputs==7);

test vectors ( [inputs
- [ 0
[ 1
- [ 2
[ 3
- [ 4
- [ s
- [ 6
- [ 7
-- [ 0

[outO [ L [ H [ H [ H [ H [ H [ H [ H [ L

end

,outl ,out2,

' H ,H

L 'H H 'L

'

' '

H H
B

, B
'H , H

' H ,H
H ,H

H 'H

out3
B B H L H H B H H

,out4 ,outs

,H , H

,H

'H

,H , H

,H

'H

,L ,H

,H ,L

,H

'H

,H

,H

,H ,H

,out6 H H H H H H L H H

,out7 ]);

B ];

B ];

' ' '

H
H H
H

];
J;
]; ];

H ];

L ];

H ];

October 1993

544

Philips Semiconductors Programmable Logic Devices
1OH/10020EV8 high-speed (4.4ns) ECL PLO

Design Brief #2: Dual Four-to-One MUX with SNAP/SLICE

@PINLIST

AO I;Al I;BO I;Bl I;CO I;Cl I;DO I;Dl I;SEL I;

OUTO O;OUTl O;OUT2 O;OUT3 O;OUT4 O;OUTS O;OUT6 O;OUT 7 O;

@GROUPS

@TRUTHTABLE

@LOGIC EQUATIONS

OUTO = AO*SEL + Al*/SEL;

~MUX AO-DO ON SEL, Al-Dl ON /SEL"

OUTl = BO*SEL + Bl*/SEL;

OUT2

CO*SEL + Cl*/SEL;

OUT3 = OUT4 = OUTS =

DO*SEL + Dl*/SEL; Al*SEL + AO*/SEL; Bl*SEL + BO*/SEL;

~DATA SWAI? FROM ABOVE METHOD"

OUT6 = OUT7 =

Cl*SEL + CO*/SEL;
Dl*SEL + DO*/SEL;

@INPUT VECTORS

@OUTPUT VECTORS

@STATE VECTORS

@TRANSITIONS

PIN FILE Device Pinl
Pin2 Pin4 PinS Pin? Pin8 Pin9 PinlO Pinll Pinl3 Pinl4 PinlS Pinl6 Pinl7 Pinl8 Pin20 Pin21

= OX20EV8 = AO
= Al
= OUTO = OUTl
= OUT2 = OUT3
= BO = Bl
= co
= Cl = DO
= Dl
= SEL
= OUT4 = OUTS
= OUT6 = OUT?

DESIGN FROM MUX.N2 FOR DEVICE 10X20EV8

Call Name Used/Total

%

CKE VS o I 1

0%

DINEVS 9 I 28

32%

NINEV8 1 I 28

3%

AND 24 I 90

26%

OR 8 I 8

100%

OLMDIR o I 8

0%

OLMINV OLMREG DFFEV8

8I 8
oI 8 oI 8

100% 0% 0%

OUTEV8 8 I 8

100%

Application Note
AN043

October 1993

545

Philips Semiconductors Programmable Logic Devices
1OH/10020EV8 high-speed (4.4ns) ECL PLD

Design Brief #2: Dual Four-to-One MUX Using ABEL

module_mux;

mux device 'ec20ev8a';

sel aO,bO,cO.dO al, bl, cl, dl outO,out1,out2,out3 out4,out5,out6,out7

pin 16; pin 1, 9, 11, 14;
pin 2,10,13,15; pin 4,5,7,8; pin 17,la,20,21;

~mux aO-dO to outO-out3 on sel=l nmux al-dl to out4-out7 on sel==l nmux aO-dO to out4-out7 on sel=O nmux al-dl to out0-out3 on sel==O
outl = [out0 ·. out3]; outh = [out4 ·· out7]; inl [aO,bO,cO,dO]; inh = [al,bl,cl,dl];

equations

when (sel==l) then outl=inl;

when (sel==l) then outh=inb;

when (sel==O) then outl=inh;

when (sel==O) then outh=inl;

test vectors [s;l, inl , inh [1, "ho ·"hf [1, "ha ·"hs [O, "ho ,"hf
[O, "ha ·"hs [1, "h1 ·"ha

------

[outl, outh]); 1"ho "hf]; ["ha "hsJ; c"ho "hf]; ["ha "b.sJ; 1"b.1 "b.aJ;

end

Application Note
AN043

October 1993

546

Philips Semiconductors Programmable Logic Devices
1OH/10020EV8 high-speed (4.4ns) ECL PLD

Design Brief #3: 8-bit Counter Using SNAP

@PINLIST

CLOCK I;RESET I;

OUTO O;OUTl O;OUT2 O;OUT3 O;OUT4 O;OUTS O;OUT6 O;OUT 7 O;

@GROUPS

@TRUTHTABLE

@LOGIC EQUATIONS

OUTO.D =

/OUTO;

OUTl.D =

/OUTO*OUTl

+ OUTO*/OUTl;

OUT2.D

/OUT2*0UTl*OUTO

+ OUT2*(/0UT1 + /OUTO);

OUT3.D

/OUT3*0UT2*0UTl*OUTO

+ OUT3*(/0UT2 + /OUTl + /OUTO);

OUT4.D

/OUT4*0UT3*0UT2*0UTl*OUTO

+ OUT4*(/0UT3 + /OUT2 + /OUTl + /OUTO);

OUTS.D

/OUTS*OUT4*0UT3*0UT2*0UTl*OUTO

+ OUT5*(/0UT4 + /OUT3 + /OUT2 + /OUTl + /OUTO);

OUT6.D

/OUT6*0UTS*OUT4*0UT3*0UT2*0UTl*OUTO

+ OUT6*(/0UT5 + /OUT4 + /OUT3 + /OUT2 + /OUTl + /OUTO);

OUT7.D =

/OUT7*0UT6*0UTS*OUT4*0UT3*0UT2*0UTl*OUTO

+ OUT7*(/0UT6 +/OUTS+ /OUT4 + /OUT3 + /OUT2 + /OUTl + /OUTO);

OUTO.CLK = CLOCK;OUTl.CLK = CLOCK;OUT2.CLK = CLOCK;OUT3.CLK = CLOCK;

OUT4.CLK = CLOCK;OUTS.CLK = CLOCK;OUT6.CLK = CLOCK;OUT7.CLK =CLOCK;

OUTO.RST = RESET;OUTl.RST = RESET;OUT2.RST = RESET;OUT3.RST =RESET;

OUT4.RST = RESET;OUTS.RST = RESET;OUT6.RST = RESET;OUT7.RST =RESET;

@INPUT VECTORS

@OUTPUT VECTORS

@STATE VECTORS

@TRANSITIONS

PIN FILE
Device = OX20EV8 Pinl = RESET Pin3 = CLOCK Pin4 = OUTO Pin5 = OUTS Pin7 = OUT7 Pin8 = OUT3
Pinl7 = OUT4 PinlB = OUTl Pin20 = OUT6 Pin21 = OUT2

DESIGN FROM COUNTER.N2 FOR DEVICE 10X20EV8

Cell Name Used/Total

%

CKE VB

1I 1

100%

DINE VB

B I 28

28%

NINE VB

9 I 28

32%

AND 45 I 90

50%

OR

BI B

100%

OLMDIR

0I B

0%

OLM INV

0I B

0%

OLMREG

BI B

100%

DFFEVB

BI B

100%

OU TE VB

BI B

100%

Application Note
AN043

OctnhAr 1QQ3

"47

Philips Semiconductors Programmable Logic Devices
10H/10020EV8 high-speed (4.4ns) ECL PLD

Application Note
AN043

Design Brief #3: 8-blt Cl)!Jl;lter Using SNAP (continued)

output of Waveform Version 1.80

Date: 01/20/92

T1-: 17:26:48

Input File Name Rule File Name : Output File Name

COUNTER.SCL Sol Rule
COUNTER.SCL

P RESET, CLOCK, PCO S 0 (40) RESET S 0 (7,14, ETC) SU time = S220
F

OUTO, OUTl, CLOCK

OUT2,

OUT3,

OUT4,

OUTS,

OUT6,

OUT7

File: counter.res (Model)

Delay = Ona

= Marker Ona

Sec/Div = 20ns

RESET L

CLOCK L

OUTO 0 OUTl 0

....____.r

OUT2 0

OUT3 0

OUT4 0

OUTS 0

OUT6 0 OUT7 0

20

60

100

140

PHILIPS C> 1992

WFA 1.80

MODE = 1

180

220

Fl HELP, FlO : EXIT

October 1993

548

Philips Semiconductors Programmable Lngic Devices
1OH/10020EV8 high-speed (4.4ns) ECL PLD

Design Brief #3: 8-bit Counter Using ABEL

module_count;

countb device 'ec20ev8a' ;

clock, reset out0,out1,out2,out3 out4,out5,out6,out7

pin 3,1; pin 4,18,21,8; pin 17,5,20,7;

count H,L,C

[out7 .. outOl;
[l, 0, .c.;

equations
count ;= count + l; count.ar = !reset;

test_vectors

[clock ,reset]_...

L L
c ,L

l1-

c ,H 1 -

c , H 1-

c ,H 1 -

c ,H c ,H

1l-

c ,H c 'H c ,H

ll-
l-

c ,H 1-

c ,H 1 -

c ,H 1 -

c ,H 1 -

c ,L 1-

count);
o·
O;
1; 2; 3;
4·
5; 6; 7; 8; 9; 10 11 12
O;

end

Application Note
AN043

October 1993

Philips Semiconductors Programmable logic Devices
1OH/10020EV8 high-speed (4.4ns) ECL PLD

Design Brief #4: Octal Shifter Using SNAP

@PDILIST

CLOCK I;DATDI I;RESBT I;

OUTO O;OUTl O;OUT2 O;OUT3 O;OUT4 O;OUTS O;OUT6 O;OUT 7 O;

@GROUPS

@rRUTBTABLE

@LOGJ:C EQUATJ:ONS

OUTO.D =

DATDI;

OUTl.D =

OUTO;

OUT2.D =

OUTl;

OUT3.D =

OUT2;

OUT4.D =

OUT3;

OUTS.D =

OUT4;

OUT6.D =

OUTS;

OUT7.D =

OUT6;

= -OUTO.CLK

CLOCK;OUTl.CLK = CLOCK;OUT2.CLK = CLOCK;OUT3.CLK = CLOCK;

= OUT4.CLK

CLOCK;OUTS.CLK = CLOCK;OUT6.CLK = CLOCK;OUT7.CLK =CLOCK;

= OUTO.RST = RESBT;OUTl.RST = RESET;OUT2.RST = RESET;OUT3.RST =RESET;

OUT4.RST

RESBT;OUTS.RST = RESET;OUT6.RST = RESBT;OUT7.RST =RESET;

@J:NPUT VECTORS

@OUTPUT VECTORS

@STATE VECTORS

@TRANSJ:TJ:ONS

PIN FILE
Device = OX20EV8
Pinl = RESET Pin2 = DAT IN Pin3 = CLOCK Pin4 = OUTO Pin5 = OUTl Pin7 = OUT2 Pin8 = OUT3 Pinl7 = OUT4 Pinl8 = OUTS Pin20 = OUT6 Pin21 = OUT7

DESIGN FROM SHIFTER.N2 FOR DEVICE 10X20EV8

Cell Name Used/Total

%

CKEV8 1 I 1

100%

DINEV8 1 I 28

3%

NINEV8 8 I 28

28%

AND 17 I 90

18%

OR 8 I 8

100%

OLMDIR 0 I 8

0%

OLM INV 0 I 8

0%

OLMREG 8 I 8

100%

DFFEV8 8 I 8

100%

OUTEV8 8 I 8

100%

Application Note
AN043

October 1993

550

Philips Semiconductors Programmable Logic Devices
1OH/10020EV8 high-speed (4.4ns) EGL PLO

Application Note
AN043

Design Brief #4: Octal Shifter using SNAP (continued)

Output of Waveform Version 1.80

Date: 01/20/92

Time: 17:1S:42

Input File Name Rule File Name : Output File Name

SHIFTER. SCL Scl Rule
SHIFTER. SCL

P RESET, DATIN, CLOCK, OUTO, PCO
s 0 (80) RESET s 0 (40, 220, 1640) DATIN s 0 (100, 200,ETC) CLOCK s 1 (S880) vcc s 0 (S880) GND
SU time = S880
F

OUTl,

OUT2,

OUT3,

OUT4,

OUTS,

# OUT6,

OUT7

File: shifter.res (Model)

Delay Ons

Marker Ons

Sec/Div = 100ns

RESET L

DAT IN L CLOCK L

OUTO

u

OUTl u

OUT2 u

OUT3 u

OUT4 u

OUTS u OUT6 u

100

300

soo

700

PHILIPS © 1992

WFA 1.80

MODE

900

1100

Fl HELP, FlO EXIT

October 1993

Philips Semiconductors Programmable Logic Devices
1OH/10020EV8 high-speed (4.4ns) ECL PLO

Application Note
AN043

Design Brief #4: Octal Shifter Using ABEL
module_shift;
shifter device 'ec20ev8a';
clock,reset,datain pin 3,1,2; out0,outl,out2,out3 pin 4,5,7,8; out4,out5,out6,out7 pin 17,18,20,21; output= [out7 .. out0]; H,L,C = [1,0, .C.;

output istype 'buffer';

equations outO.d datain; outl.d = outO; out2.d = outl; out3.d = out2; out4 .d = out3; outs .d = out4; out6 .d out5;
out7.d = out6;
[output] .ar = !reset;

test_vectors

[clock,reset,datain

0

0

0

c

0

1

c

1

1

c

1

0

c

1

1

c

1

0

c

1

1

c

1

0

c

1

1

c

1

0

c

0

1

c

1

1

c

1

1

c

1

1

c

1

1

c

1

1

c

1

1

c

1

1

c

1

1

c

0

1

end

------------------------------------

[outO
[ L [ L [ H [ L [ H [ L [ H [ L [ H [ L

,outl
L L L H L H L H L H

,out2
L L L L H L H L H L

,out3,out4,out5

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

H

L

H

L

H

L

H

L

H

L

H

L

L

L

L

L

L

H

L

L

L

L

L

H

H

L

L

L

L

H

H

H

L

L

L

H

H

H

H

L

L

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

L

L

L

,out6 L L L L L L L L H L

,out? )); L l; L l; L ]; L ]; L ]; L ]; L ]; L ];
L ); H ];

L

L ];

L

L ];

L

L ];

L

L ];

L

L );

L

L ];

L

L ];

H

L ];

H

H ];

L

L ];

nrtnhcr 1 aa~

fifi?

Philips Semiconductors Programmable Logic Devices
PHD48N22 high speed (7.5ns) 32-bit programmable decoder

Application Note
AN031

INTRODUCTION
Performance specifications for PLDs usually include simple parameters like tpo and IMAX· These values oversimplify PLO performance. Specifying the reaction time for an output pin to an input signal (tpo) is important, but tp 0 doesn't tell the whole story. Similarly, the
flip-flop IMAX shows only the maximum upper
limit toggle rate. Neither number tells whether the PLO can even solve the problem at hand. To get that answer, the designer has to go beyond these simple parameters and investigate the design's exact needs.
THE DECODE PROBLEM
A recent computer architecture book (Hennesy and Patterson) shows several guidelines for fast processor design. These principles are commonly associated with RISC processors.
The primary guideline is simple: make the common case fast. For microprocessors, this means make the basic machine cycle as fast as possible. Since the basic cycle is repeated continuously, it defines nearly 100% of what the processor is doing.
Trimming time off the basic instruction cycle results in the single highest payoff. This is simple, right? Take the instruction cycle to zero wait states and the problem is solved. The problem more often yields to a quicker, universal solution - money! Put the fastest possible high speed memory into the processor - memory loop and the design is done. Naturally, there are always competitors who try to make the same design for less cost. All designers must find trade-offs giving maximum speed for minimum cost.
Getting a zero wait state solution for the lowest cost is the goal. Naturally, the cheapest solution is also the slowest one. For this problem, the designer must use the slowest memory devices that meet the zero wait state goal. We'll focus simply on that goal. It gets more interesting if some transactions can be done with one or two wait states while others require zero.
SOLVING THE PROBLEM
What must be done? When the processor emits its address and control signals, the memory space should not respond until specific modules have been explicitly selected. This is the basic problem of fast address decode.
Address decode has several dimensions: speed, resolution and current drive. Speed is

obvious: it is the simple lpo of the part-with the output reacting in the low direction to drive a RAM chip enable. Secondary issues include switching edge rates, reflections and contention. Current drive is the next important dimension because most small systems need at least 24mA (lad to drive an array of chip enables, and pc board traces. The resolution dimension is the most interesting for the following reasons.
Today's high performance microprocessors have 32 address bits, along with several status and control bits. Careful decode may require as many as 36 or more distinct inputs to select bytes from the four gigabyte address space. In the past, it was acceptable to waste whole memory sections if chip decodes couldn't pack memory tightly. 1/0 regions were mapped into the memory space, leaving address gaps. Alternately, 1/0 device addresses would have repeated response regions in memory. Both solutions are less than desirable.
This arrangement contradicts today's prevailing design philosophy. Tight, contiguous memory regions are now desirable, while maintaining design freedom. Most software developers also resent giving up any memory space due to poor hardware design.
How fast does address decode have to be? Today, 33MHz and 50MHz processors are being shipped. This sets memory cycles at 33 and 20 nanoseconds, respectively. To get zero wait states Fast cache (at 20ns or less) is needed. Fast cache cost rises dramatically with 5ns speed increments. Suppose a 25ns cache were used on a 33ns cycle time. This leaves Bns to decode and drive signal capacitance. For this analysis, we'll assume no line ringing or other electrical phenomenon. A decode propagation delay time below 7ns is needed.
To solve this decoding problem, a new PLO the PHD48N22 - has been developed with a minimal tpo and an adequate current drive. The PHD48N22 1/0 structure (Figure 1) is its main strength. As the name implies, the PH D48N22 combines the potential for 48 inputs with 22 outputs. Combining high-speed configurable NANO gates with a PAL® architecture, the PH D48N22 is dual optimized. It easily handles high speed SRAMs, EPROMs, DRAMs and 1/0.
By decoding 32 bits of address lines and several control lines, the PHD48N22 distinguishes reads from writes and 1/0 from memory to a byte level of resolution. This meets the needs of any system today. If the

22 outputs are not enough, another PHD48N22 can be added, to complete the system deccde. Let's describe the part, showing some of its less obvious capabilities.
A LOOK INSIDE THE PHD48N22
Figure 1 is a logic diagram of the PHD48N22. It reveals three distinct logic regions, all connected to the main programming array. First, there are 18 AND gates, then there are three seven-input PAL sites and one 12-input PAL site. The speed of the paths which follow an input pin to an AND gate, inverter and output pin is shown in Figure 2 as solid dots. The speed path passing through the PAL sites is shown as hollow dots.
The number of outputs driven versus tpo is also shown in Figure 2. The address decode function often needs only one output selected at any point in time, so it makes sense to show the speed with only one output driven. One output driven is the fastest configuration and is also a common case. Pyramided solutions that stack gates in series are unacceptable for very fast decode.
Note that the PHD48N22 outputs are 3-State controlled with logic gates programmable from the array. These 3-State, controlled outputs permit PHD48N22 outputs to be wire-ANDed together.
Wire-AN Ding permits two important benefits. First, the logic function through the programmable AND gates becomes the NANO-AND when two outputs are joined. This connection is logically equivalent to the AND-OR-INVERT. The AND-OR-INVERT is exactly the logic function made by the PAL 16L8. Second, wire-AN Ding the gates can double the output drive to 48mA if the outputs are enabled by the same control logic. This approach avoids feeding an output back into the array just to drive another output, or serial buffering. Serial buffering increases time delay. Alternately, drive current can be split from different output pins instead of wire-AN Ding them. Current splitting also increases time delay, but much less so than serial buffering.
For designers that are reluctant to use the wire-AND, some logic flexibility can occur at the four PAL sites. The usual sum-of-products can be made at these sites, and the speed is acceptable for memory decode. The PAL sites are somewhat slower than the high speed AND paths, and are ideal for controlling the processor wait line for 110.
The PAL site outputs can also be 3-State controlled so the logic function can expand if

®PAL is a registered trademark of AMO.

February 1990

553

~ovicorl· nrtnhor 1 oa~

Philips Semiconductors Programmable Logic Devices
PHD48N22 high speed (7.5ns} 32-bit programmable decoder

Applieation Note
AN031

needed. Any mix of the PAL sites and the high speed AND gates may be had at the output pins, but the designer should be aware that the final output function is limited to the wire AND. This means that any low driving output signal dominates at the pin, if its 3-State enable is asserted.
A very simple policy for the use of the AND terms is to put the same logic function on the 3-State ccntrolling term as is applied to the AND gates' logic inputs {Figure 3). Exotic enabling conditions can be made by using the seven input PAL sites to make and gate enable signals -wrapping around the part through the 1/0 pins.
The gate resolution is variable up to 48 inputs. Typically, designers will use 32 or fewer. Even with this, designers can resolve a single byte location out of a four gigabyte address space. Memory mapped 1/0 will no longer fragment an otherwise clean address space. It is possible to drop 1/0 registers {UAR/Ts, disks, etc.) right into the middle of a large memory space giving up no addresses except those needed for 1/0 select.
BACK TO THE SYSTEM. ..
A ccmmon practice today is to make memory and 1/0 devices shadow each other in the same address space. This is a cinch with the PHD48N22.
The best address partitioning with the PHD48N22 is to simply use the fast AND
paths to handle memory, and the PAL sites to handle 1/0 deccde needs. The PAL sites can
be used to control the wait line on the processor for slower deccdes, handle

interrupt input lines, OMA requests, or whatever.
OTHER APPROACHES It makes sense to consider the other
solutions. Let's start with the way most designers have been solving the problem over the last few years. The most obvious way is fast PALs. Until recently, these parts offered the finest address resolution with as many as 21 inputs. This is the case with the 22V10, ccnfigured as an address decoder.
The number of 22V1 O1/0 pins leaves much to be desired, as well as the best case speed of 7.5ns. The output current drive is also low - between 12mA and 16mA depending on the manufacturer. Similarly, Sns PAL devices of other varieties have the current drive and speed, but not enough inputs and outputs.
Considering other parts optimized for fast decode, the TIBPAD-6 is such a simple programmable NANO circuit. This part is pinned compatible to the PAL16L8, and has the requisite current drive, but not enough input pins. The Philips Semiconductors PHD16N8 is pin compatible and faster with a tpo of Sns. The PHD16N8 is the little sister of the PHD48N22. A logic diagram is shown in Figure 8.
The Xilinx LCA 4000 offers four quick decoders at 10ns and up to 60 inputs. The speed is 10ns and the output current is only 12mA. If the output current must be increased with an extra buffer, the horserace is lost. Paralleling output pins uses up pins very quickly.

The Intel 85C508 offers a fast {7.5ns) registered comparator, but it again only provides 12mA of output current. None of these solutions offer a fully integrated system decoder in a single chip.
MORE TRICKS
The PHD48N22 can build up other functions than simple, fast address decoders. For instance, Figure 4 shows a 48N22 exploiting its input width working with a deep counter. When a decode value occurs on the ccunter outputs, the NANO gate generates a pulse to either reset or load the ccunter with a new value.
Any value - from 1 to 16 bits {shown here)can expand to 48 bits.
Fancy latches can be built, or custom arbiters based on the configuration shown in Figure 5 for multiple OMA ccntenders vying for selection.
Other logic structures not needing the signal width are possible to build with a 48N22, if any pins and functions remains after its primary use is accomplished. Figure 6 shows a simple sum of logical products and Figure 7 shows a multiplexer. Both require output signals fold back into the array and neither needs an external pull-up resistor.
In conclusion, the most common way to use the 48N22 is in its intended configuration, as a very wide input high speed address decoder. Literally, any high performance microprocessor can be used with the PHD48N22 resulting in a fast, clean design.

February 1990

554

Philips Semiconductors Programmable Logic Devices
PHD48N22 high speed (7.5ns) 32-bit programmable decoder
INPUTS(0-95)

Application Note
AN031

-<:>-----D~-__,.,, 09 08
-r>-----D~-__,... 02
t::E~=~----l~ 01
-<:>----t>~---<>HOO
-<:>----o~..-.....2187

110 111 112 113 114
116
118 119 120

124
NOTES: 1. All unprogrammed or virgin "AND" gate locations are pulled to logic "O" 2.::.::::::: Programmable connections
Figure 1. PHD48N22-7 Logic Diagram

February 1990

555

Philips Semiconductors Programmable Logic Devices
PHD48N22 high speed (7.5ns) 32-bit programmable decoder

Application Note
AN031

10

T

r 1T

~ 7
~ 6
.w.J
c 5 z 0~ 4
<.:>
~ 3
0g:: 2

··

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

NOTE: o "" OR Outputs · "" 8/0 Outputs

TEST CONDITIONS:

Tam1:1 = 75°C; Vee= 4.75V;CL"' 50pF; A1 = 200n.; R2 = 390n;

Figure 2. Worst Case Propagation Delay vs. Number of Outputs Switching

A

B

+SV

c
D

OUT

7\B-CU·EF

AB+ CD+ EF

E

which is the AND-OR-INVERT

F

l I
Inputs NANDs

l
Wire AND at the pins

Figure 3. Wire ANDing

February 1990

556

Philips Semiconductors Programmable Logic Devices
PHD48N22 high speed (7.Sns) 32-bit programmable decoder

Application Note
AN031

48N22

Counter toad or Reset

Input

Internal feedback can observe these points at output pins

Figure 4. High Speed Count Decode

Figure 6. Two-level Sum of Products

SELECT1 SELECT2

OMA SELECT
SELO SEL1

OUT

Figure 5. Wide Input Latches

February 1990

557

Figure 7. Four-Input MUX

Philips Semiconductors Programmable Logic Devices
PHD48N22 high speed (7.Sns) 32-bit programmable decoder

Application Note
AN031

12

16

20

24

28

J1lfillllfillfill:l[lx:12ffi1v~1t±B£1>Giblflll~'ild1fil1>1d1il'HJ11>l1>±11llsl1ulrc[}~L-~;><r--t---i 19

~

~ v

1 ~114&~~11!111L.T1Itt'BiuuiLli)1uu10!22$]J:Hmm1nu12t>l1<[tL>ilUrrEJe~;io--.-~ 16

~

~

.. , w r1.11 imr:zTti ~::>o-~----1 15

~~>-++++-++++-+H-l---1f-H-f----H

3::

NOTES: 1. All unprogrammed or virgin "AND" gate locations are pulled to logic "O" 2. ) / { ( / Programmable connections
Figure 8. PHD16N8-5 Logic Diagram

February 1990

558

Philips Semiconductors Programmable Logic Devices
68030 system decoding

Application Note
AN044

68030 ADDRESS DECODING
Philips Semiconductors PHD48N22 decoder is not only very high speed but also has a very wide input structure. This combination allows high-performance systems to be constructed in a minimal space without sacrificing decoding resolution. The following example demonstrates the use of the PHD48N22 as well as the PHD16N8 in a 33MHz 68030 system.
This example uses one each 48N22 and 16N8 PHO decoders to interface together a 33MHz 68030 processor, 33MHz 68882 Floating-Point Coprocessor, 12BK bytes of 35ns static RAM, 64K bytes of 200ns EPROM and a SCN2692 Dual port UART. Additional logic required amounts to only one 16-pin and one 24-pin device.

The schematic is shown in Figure with SNAP listings of the PHO devices in Figures and . As can be seen from the schematic, the PHD48N22 handles all of the RAM, PROM and DUART decoding. Notice the number of 68030 address lines input into the 48N22: A31 through AB and A1 and AO. Depending upon the application, the 4BN22 can decode down to the byte level in 6.5ns. The PHD16N8 decodes an early chip-select signal for the 33MHz 68882 FPCP in less than the required 5ns.
Accesses to the RAM produce an immediate acknowledge (DSACK) from the 4BN22 to the 68030, allowing it to run full speed in asynchronous mode. Since the EPROM and DUART operate at a much slower speed than

the 68030, two additional devices, a 74F191 counter and a 74F646 transceiver/register were used in this example. If either the EPROM or DUART are accessed, the counter will count CPU clock cycles and delay the 48N22's assertion of DSACK signal. The 'F646 is used to quickly 3-State signals from the EPROM and DUART. Also, in conjunction with the counter and 4BN22, a read of a DUART register first causes information to be read into a register of the 'F646, which is then read by the 68030 while the DUART's output is disabled. This was done since a DUART specification (tRwo) requires 200ns between reads or writes. Therefore, accesses to the DUART are controlled by the counter, 48N22, and 'F646. Software restrictions are not required.

October 1993

!i5Q

~
[
lll
32 -'- 32

68030-33

P~8

68882-33

_,_A15-AD

'--- 031-00 A31-A20 !--'
A19-A13 i-..:1-4,

031-00
!------- cs

_,_32

l

A12-A5 !--'
. - - IBERR A4-A1

f--/ Ao
FC2-FCO

.,,

~ IAVEC AS IPO OS
nIPP12 RIW
OSACKo

...;cc

en
0"'

1g,

':I'

CD

3g;,

,-, ICllN
tE8lACK1
~
~ k

0

""-r--'
3

I-- SIZE A4-A1
'--1 AO AS
os
RIW
OSACKo OSACK1
CLK

00-07

OB-015

016-023

024-031

A16-A2

32Kx8 RAM

32Kx8 RAM

32Kx8 RAM

32Kx8 RAM

WE OE CE
~ L_ IWLMB '\'!'_Ut,!!!_ IWUU /OE

WE OE CE
j_ 1-

WE OE CE
t 1-

WE OE CE
t -!

A31-AB A1,AO ' -
«J..K

I

_K_OewC_

-.JAf;_

±
PHD48N22

/BEN
lf:!llll
TC 03
ICTEN /CLKN

l J JE~ ~PL TCF191 03020100

A15-AO

27C512

EPROM

CE

OE

07-00

Jf. 031-024

~
-AO

~rF(A.)6(4B!)

1--
DO I--

RIW DIR

~~I

/BEN /OE
SAB<~B
1 SB CPBA '"'

2692 DUART

RON

. - - INTRN

1-~I

Port2

WRN CEN

IAVE<1.]

J

.,.

/CEN

IWRN

IBERR

"tJ

O'> CX>

~
al

0

gi

c.:> 0
(/)
'< ~
CD

2.
8a.
c
&;;;

3

a"tJ

c.
CD

"ii'l
3

(')

3

0
9:

~
CD

c:o:l

b
<Q.

0

0 CD
.~.·

z)>

-6'
12.

~·

0 .i:.. .i:..

c;·
" z

*

Philips Semiconductors Programmable Logic Devices
68030 system decoding

@PINLIST "Signal names preceding with a 'n' means active low signals"

AO

I;

Al

I;

nAS

I;

Q3

I;

TC

I;

CLK

I;

AB

I;

A9

I;

AlO

I;

All

I·

Al2

I;

Al3

I;

Al.4

I;

AlS

I;

Al6

I;

Al?

I;

A18

I;

Al9

I;

A20

I;

A21

I;

A22

I;

A23

I;

A24

I;

A25

I;

A26

I;

A27

I;

A28

I;

A29

I;

A30

I;

A31

I·

FCO

I;

FCl

I;

FC2

I;

SIZO

I;

SIZl

I;

RW

I;

nOE

B;

nCPU

B;

nSAB

B;

nASN

B;

nWUUB

B;

nCEN

B;

nBEN

O;

nRDN

O;

nWRN

O;

nDSACKOa

o;

nDSACKOb

o·

nDSACKOc

o·

nDSACKl

o·

nBERR

O;

nAVEC

o;

nCLKN

O;

nCTEN

o;

nWUMB

B·

nWLMB

B;

nWLLB

B;

@LOGIC EQUATIONS

PROMADR RAMADDR UARTADR UORPROM ASD

"RAM, PROM, and UART address definitions"

/A31*/A30*/A29*/A28*/A27*/A26*/A25*/A24*/A23*/A22*/A21*/A20*

/Al9*/Al8*/A17*/Al6;

/A31*/A30*/A29*/A28*/A27*/A26*/A25*/A24*/A23*/A22*/A21*/A20*

/A19*/Al8*/A17;

/A31*/A30*/A29*/A28*/A27*/A26*/A25*/A24*/A23*/A22*/A21*/A20*

/A19*/Al8*/Al7*A16*/A15*/Al4*/Al3*/Al2*/All*/A10*/A9*/A8;

/A31*/A30*/A29*/A28*/A27*/A26*/A25*/A24*/A23*/A22*/A21*/A20*

/Al9*/A18*/A17;
nAS * nASN;

"eliminate hazard ANDing nAS with nCPU"

Figure 2. PH048N22-7 SNAP Listing (1 of 2)

October 1993

561

Application Note
AN044

Philips Semiconductors Programmable Logic Devices
68030 system decoding

nOE.oe = l; nCPU.oe l;
nSAB.oe = 1;
nASN.oe = l;
nWUUB.oe = l;
nCEN.oe = l; nCTEN .oe l; nWUMB.oe l;
nWLMB.oe 1·
nWLLB.oe l·

"enables for DSACKO and DSACKl"

nDSACKOa.oe (PROMADR*nCPU*ASD*Q3); "acknowledge PROM 8 bits"

nDSACKOb.oe (UARTADR*nCPU*ASD*TC); "acknowlodge USART 8 bits"

nDSACKOc.oe (RAMADDR*nCPU*ASD);

"acknowledge RAM 32 bits"

nDSACKl.oe

(RAMADDR*nCPU*ASD);

"acknowledge RAM 32 bits"

nASN = /nAS; "delay nAS"

nDSACKOa nDSACKOb nDSACKOc nDSACKl

/(PROMADR*nCPU*ASD*Q3); /(UARTADR*nCPU*ASD*TC); /(RAMADDR*nCPU*ASD); /(RAMADDR*nCPU*ASD);

"acknowledge PROM 8 bits" "acknowlodge USART 8 bits" "acknowledge RAM 32 bits" "acknowledge RAM 32 bits"

nCPU
nAVEC

"CPU address space decoding"
I (FCO*FCl*FC2); I (FCO*FC1*FC2*A19*Al8*Al7*Al6); "interrupt ack forces autovector"

"RAM output enable"

nOE

/(RAMADDR*nCPU*RW);

"enable all RAM outputs upon read"

nWLLB

"RAM write strobes"

/(RAMADDR*/RW*Al*AO*nCPU*ASD

''directly addressed, any size"

+RAMADDR*/RW*AO*SIZl*SIZO*nCPU*ASD "old alignment, 3 byte size"

+RAMADDR*/RW*/SIZl*/SIZO*nCPU*ASD "any RAM address, long word size"

+RAMADDR*/RW*Al*SIZl*nCPU*ASD);

"word aligned, word or 3 byte size"

nWLMB

/(RAMADDR*/RW*Al*/AO*nCPU*ASD

"directly addressed, any size"

+RAMADDR*/RW*/Al*/SIZl*/SIZO*nCPU*ASD"word aligned, long word size"

+RAMADDR*/RW*/Al*SIZl*SIZO*nCPU*ASD "word aligned, 3 byte size"

+RAMADDR*/RW*/Al*AO*SIZO*nCPU*ASD); "word aligned, word or long word"

nWUMB

/(RAMADDR*/RW*/Al*AO*nCPU*ASD +RAMADDR*/RW*/Al*/SIZO*nCPU*ASD +RAMADDR*/RW*/Al*SIZl*nCPU*ASD);

"directly addressed, any size" "word aliqned,byte or 3 byte size" "word aligned, word or long word"

nWUUB /(RAMADDR*/RW*/Al*/AO*nCPU*ASD); "directly addressed, any size"

"DUART and PROM address decoding" nCEN /(UARTADR*nCPU*ASD);

nRDN /(UARTADR*nCPU*ASD*/Q3*RW);

nWRN /(UARTADR*nCPU*ASD*/Q3*/RW);

nBEN /(UORPROM*nCPU*ASD);

"enable F646 for USART or PROM"

nSAB /(PROMADR*nCPU*ASD*RW);

"F 64. 6 transparent for PROM, registered for USART"

nCTEN /(UARTADR*nCPU*ASD*/TC +PROMADR*nCPU*ASD*/Q3);

"hold count upon TC for UART or" "Q3 for PROM access"

nCLKN /(CLK*nAS);

"clock for F191"

nBERR I (nCEN*nWUUB*nWUMB*nWLMB*nWLLB*nOE*nCPU*nSAB*ASD) ; "nBERR if no access"

Figure 2. PHD48N22-7 SNAP Listing (2 of 2)

Application Note
AN044

October 1993

562

Philips Semiconductors Programmable Logic Devices
68030 system decoding

@PINLIST

FC2

I;

FCl

I;

FCO

I;

Al9

I;

Al8

I;

Al7

I;

Al6

I;

Al5

I;

Al4

I;

Al3

I;

nCS

o;

@GROUPS @TRUTHTABLE @LOGIC EQUATIONS

nCS.OE = l;

CPU COPROCESSOR CP_ID

FC2 * FCl * FCO; /Al9 * /Al8 * Al7 * /Al6; /Al5 * /Al4 * Al3;

ncs =/(CPU* COPROCESSOR* CP_ID);

"cpu space" "coprocessor corrmunications" "cp-id one"

Figure 3. PHD16N8·5 SNAP Listing

Application Note
AN044

Phillps Semiconductors Programmable Logic Devices
High speed 8-bit parallel to serial converter

Application Note
AN045

INTRODUCTION A common function in many systems is to convert parallel data into a serial data stream. A microcontroller may be programmed to shift a byte in a register out to a port, but this is a relatively slow procedure. A simple pre-loadable shift register could perform the basic conversion. However, for the function to be complete, additional circuitry to perform handshaking or control of the process is required. The entire function can be made to fit into a low cost Programmable Logic Device (PLO), including control circuitry tailored to meet specific application requirements.
DESCRIPTION Figure 1 shows the desired waveforms for a typical implementation. First, a reset signal initializes the system and this circuit. Next, the parallel data to be serialized is applied to the device, possibly from a parallel port of a microcontroller, and a write strobe (WRS) signal pulsed. The PLO then raises a flag (BUSY) and puts the data, one bit at a time, on an output (SDAT) under control of a clock signal (CLK). Another output, (SCLK) is an inverted copy of the transmitting clock, ANDed with a control signal, so it only is active when data is actually being sent. It can be used by the receiving device to clock in the serial data.
How does one get a PLO to perform such a

function? Preferably this design should fit into a simple, low cost device such as a 22V10 type PLO. A 22V10 has ten outputs which may be individually configured to be registered or combinatorial. It is possible to make a two input multiplexer circuit in front of eight of the D-type flip-flops. It could then be configured to shift data or load parallel data upon a control signal and clock. However, to provide the output control signal BUSY and gate SCLK, a 3-bit counter will be required to indicate when the last bit of data is shifted out. That would bring the total registers in the design up to eleven, one more than a 22V1 O provides. Additionally, the write strobe (WRS) is a short duration asynchronous signal, so more circuitry is still required to synchronize it with the transmitting clock (CLK).
Another method of serializing data is to use a multiplexer (8 to1 for this example) and a counter. The counter controls which bit is to be output from the multiplexer. A count of zero connects input IDO to the output, a count of one connects 101, and so on. This will work only if the parallel input data is held stable throughout the serialization process. For this example, the data is applied from one port of a microcontroller and held stable until after the BUSY signal transitions from high-to-low, so a multiplexer will work for this case. An 8-to-1 multiplexer will use only one output, while the three-bit counter will use

three outputs of a 22V10, which leaves us with six outputs for other functions. Let's use this technique to implement this example. Additional outputs are required for signals BUSY, SCLK, and some currenHy unspecified control signals.
A counter may be constructed very easily using a SNAP syntax equation of: "COUNT.D=COUNT#1 H;". The"#" (pound) symbol means addition, the ".D" signifies an input to a D-type of flip-flop, and the "1 H" is 1 hexadecimal. So the equation is simply COUNT equals COUNT plus 1. The actual equation in Figure 3 contains another term, but more on that later. In addition to the D inputs of the flip-flops, it is necessary to describe the flip-flops clock and reset connections. Those are listed in lines 57and 58 of Figure 3.
A multiplexer is also very easy to describe using SNAP syntax Boolean equations. For an 8-to-1 multiplexer with output SDAT and inputs 107-100 it is:
SDAT = 100 ·(COUNT==OH) + 101 *(COUNT==1H) + 102 *(COUNT==2H) + 103 ·(COUNT==3H) + 104 ·(COUNT==4H) + 105 *(COUNT==5H) + 106 · (COUNT==6H) + 107 ·(COUNT==7H);

CLK RESET
WAS ID7.. IDO
SCLK SDAT BUSY

DO

D1

D2

D3

D4

D5

D6

D7

ID7·· IDO [

..1'
-v

wRS

c LK

.....

RES ET

~ SCLK ~ SDAT
BUSY

Figure 1. Desired Input and Output Waveforms

Philips Semiconductors Programmable Logic Devices
High speed 8-bit parallel to serial converter

Application Note
AN045

So far, we have a counter and multiplexer to serialize the data. The process of serialization begins with an asynchronous pulse on the write strobe input (WRS). It is therefore necessary to construct a latch to capture the pulse and then use two registers to synchronize the signal to the input clock. Figure 2 shows the desired operation of two intermediate signals Zand Z1. An extremely simple latch can be made with the equation: ·z = /WRS + Z". Once set with WRS low, it could never be reset. An additional signal named GATE, will be used as an extra term in the latch to reset it. From the waveforms of Figure 2, a table of the three signals may be constructed.

WRS GATE

z

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

WRS,GATE

00

01

zo

1

Z+
1 1 1 1 0 1 0 0

11

10

0

0

0

Z+ is the ·next state" or what value output Z should be, given the current inputs and the current state of Z. From the table, a Karnough map may be constructed (shown above) and the equation "Z=IWRS+Z'/GATE;" derived.

We have signal Z, which latches the input strobe, but we need to synchronize it to the input clock. That can be done with flip-flop Z1 and the following flip-flop, GATE, described later. For Z1, the equation is simply: "Z1 .D=Z;" Z1 is clocked by the rising edge of CLK. Z1 's output will go high upon the rising edge of CLK and Z high. It will go low upon a rising edge of CLK and Z low.
According to the original waveforms of Figure 1, a signal named BUSY is required to occur after the falling edge of CLK following a detected strobe (WRS). The internal D-type
flip-flops of a 22V1 o can only be clocked on
the rising edge of the clock, so one of the 22V10's internal flip-flops cannot be used. However a Boolean equation may be used to describe this signal. The times and conditions when this signal is to be high will be noted from Figure 2 and a Boolean expression generated. From Figure 2, at time T2, BUSY should go high. Therefore, one term of the equation for BUSY will be: ·z·z1 '/CLK". When both Z and Z1 are high and CLK is low, then BUSY will go high. This product term will keep BUSY high until time T3.
At time T3, BUSY should remain high and adding a product term of "BUSY'Z1" can keep it high until time TS. This product term actually becomes active long before time T3 arrives, so there will be no glitching of the output. Adding yet another product term of "BUSY'GATE" will keep BUSY high from just after time T3, through time TS, until time T19. Finally, one last product term of "BUSY'CLK", keeps it high until the falling edge of the

clock. The combined equation for BUSY is shown in Figure 3 lines 38 through 41.
The last signal to be described is GATE. It is used to control the gating of the inverted clock output SCLK, and also control the already described signals BUSY and Z. GATE can use one of the flip-flops inside the 22V10, as it should only switch after the rising edge of the input clock. It goes high after the first rising edge of CLK after BUSY goes high. Therefore, one of inputs to the GATE flip-flop has to be BUSY. GATE should go low after COUNT reaches seven, so the equation can be "GATE.D =BUSY' /(COUNT==7H);" The input to the GATE flip-flop will be high when BUSY goes high and COUNT is not equal to 7.
Signal GATE was also added to each of the terms in the multiplexer equation and it was added as a term in the counter equation. It was added to the multiplexer so SDATwould be low unless actual data was being sent . It was added to the counter so the counter would only count when GATE was high. This design used nine of the ten possible 22V10 outputs. The input RESET was added to many of the equations to force a proper initialization of the signals. From here it is just a matter of typing the equations into SNAP, running a simulation, and generating a JEDEC file for downloading to a device programmer. Figure 4 shows the SNAP simulation results and Figure S shows the associated simulation control language (SCL) file.

October 1993

Figure 2. Waveform Timlng Relationships SSS

Philips Semiconductors Programmable Logic Devices
High speed 8-bit parallel to serial converter

Application Note
AN045

1 I

3 2

!"-------------------------------------------------"
I" High Speed 8-bit Parallel to Serial Converter "

4 5

!"------~------------------------------------------" I

6 l@PINLIST

7 ICLK

I;

I

__\

/

I

8 IID[O .. 7] 9 IRESET

I; I; "active low"

I CLK llCLK/IO

I VCCl24]

10 IWRS

I;

RESET 21Il

I/09123]

11 I

12 IBUSY

O;

13 ISCLK

O;

14 ISDAT

O;

15 IC[0 .. 2]

o·

16 IGATE

O·

17 IZ

O;

18 IZl

O;

19 I

20 !@GROUPS

21 ICOUNT=[C2,Cl,CO];

22 I

23 I@TRUTHTABLE

IDO 31I2 IDl 41I3 ID2 51!4 ID3 61I5 ID4 71I6 IDS 81I7 ID6 [ 91I8 ID7 [101I9 WRS [111 IlO
[121GND
I I

I/08122] Zl
I/07121] z
I/06120] SDAT I/05119] SCLK I/04118] GATE I/03117] C2 I/02116] Cl
I/01115] co
I/00114] BUSY
Illll3]
I I

24 l@LOGIC EQUATIONS

25 I 26 I

"write strobe latch"

27 I

28 IZ /WRS*reset+Z*/GATE*reset;

29 I

30 I "first flip-flop to sychronize WRS to CLK"

31 I

32 IZl.D

Z;

33 IZl .CLK = CLK;

34 IZl.RST = reset;

35 I

36 I "busy flag"

37 I

38 IBUSY = Z*Zl*/CLK*reset

39 I

+ BUSY*Zl*reset

40 I

+ BUSY*GATE*reset

41 I

+ BUSY*CLK*reset;

42 I

43 I "gate for control and 2nd synchronizing.flip-flop"

44 I

45 IGATE.D = BUSY*/(COUNT==7H);

46 IGATE.CLK CLK;

47 IGATE.RST = reset;

48 I

49 I

50 I

"output clock"

51 I

52 ISCLK = /CLK*GATE;

53 I

54 I

"3-bit up counter"

55 I

56 ICOUNT.D = GATE==l * COUNT#lH; "count only when GATE is high"

57 ICOUNT.CLK = CLK;

58 ICOUNT.RST = reset;

59 I

60 I "Multiplexer Equations"

61 I

62 ISDAT IDO* (COUNT==OH) *GATE*reset "if GATE is low then output a low"

63 I

+ IDl*(COUNT==lH)*GATE*reset

64 I

+ ID2*(COUNT==2H)*GATE*reset

65 I

+ ID3*(COUNT==3H)*GATE*reset

66 I

+ ID4*(COUNT==4H)*GATE*reset

67 I

+ IDS*(COUNT==SH)*GATE*reset

68 I

+ ID6*(COUNT==6H)*GATE*reset

69 I

+ ID7*(COUNT==7H)*GATE*reset;

10 I

71 I@INPUT VECTORS

72 !@OUTPUT VECTORS

73 I@STATE VECTORS

NOTE: Line numbers are for reference only, they

74 I@TRANSITIONS

are NOT part of the design file.

75 I

Figure 3. SNAP Listing and Pin File

October 1993

566

Philips Semiconductors Programmable Logic Devices
High speed 8-bit parallel to serial converter

Application Note
AN045

File: SHIFT.RES <Model> CLK L RESET L
WRS H
BUSY u GATE u SCLK u SDAT u
C[2 .. OJ u
z u
Zl u

DELAY Ons

Marker Ons

Sec/Div 200ns

J:=1J2-J3_=:1J4-f5-=:Jf6-J7 J o -

200

600

1000

Philips Semiconductors <C> 1993 MODE = 1

1400

1800

2200

Fl : HELP, FlO : EXIT

Figure 4. SNAP Simulation Waveforms

***************************************************

*

OUtput of Waveform Version 1.90

*

* Date: 04/21/93

Time: 16:14:48 *

***************************************************

** Input File Name * Rule File Name * Output File Name

SHIFT.SCL Scl Rule SHIFT.SCL

*
* * *

*

*

***************************************************

P IDO, IDl, ID2, ID3, ID4, IDS, ID6, ID?, CLK, RESET, WRS, BUSY,

# GATE, SCLK, SDAT, C[2 .. OJ, Z, Zl

PCO

s 0 (S890) IDO s 1 (S890) IDl

s 0 (S890) ID2

s 0 (S890) ID3

s l (S890) ID4

s 0 (S890) IDS

s l (9200) ID6

s 0 (14290) ID?

s 0 (100, 200, ETC) CLK

s 0 (80, S600, 6000) RESET

s 1 (180, 240, 4000, 4200) WRS
SU time = 14290

F

Figure 5. SNAP Simulation SCL File

October 1993

567

Phillps Semiconductors Programmable Logic Devices
A Metastability Primer

Product specification
AN219

INTRODUCTION
When using a latch or flip-flop in normal circumstances (i.e., when the devices set-up and hold times are not being violated) the outputs will respond to a latch enable or clock pulse within some specified time. These are the propagation delays found in the data sheets. If, however, the set-up and hold times are violated so that the data input is not a clear one or zero, there is a finite chance that the flip-flop will not immediately latch a high or low but get caught half way in between. This is the metastable state and it is manifested in a bi-stable device by the outputs glitching, going into an undefined state somewhere between a high and low, oscillating, or by the output transition being delayed for an indeterminable time.
Once the flip-flop has entered the metastable state, the probability that it will still be metastable some time later has been shown to be an exponentially decreasing function. Because of this property, a designer can simply wait for some added time after the specified propagation delay before sampling the flip-flop output so that he can be assured that the likelihood of metastable failure is remote enough to be tolerable. On the other hand one consequence of this is that there is some probability (albeit vanishingly small) that the device will remain in a metastable state forever. The designer needs to know the characteristics of metastability so that he can determine how long he must wait to achieve his design goals.

800
700
600
500 NUMBER
OF FAILURES 400
300
200
100

EXPONENTIAL DECAY - - -
_.} _____OF_F_A_ILU_R_ES_____ _

I

I

f

I

I

ens

9ns

PROPAGATION DELAY

10ns

Figure 1.

1,000,000 ~~~~-~-~-~-~-~

100,000 10,000

--.---,-- '

'

SEMl·LOG GRAPH - -

OF FAILURES

--I---I ---I ---I ---I ---I -

'

' '

NUMBER OF
FAILURES

1,000 - - ,_ - -· - - ..! - - !. - - ·- - -· - 100

10

--I---I ---I ---I ---I ---I -

·

I

I

I

I

I

0.1 ~~-----+--~-~-~

Bns

9ns

10ns

PROPAGATION DELAY
Figure 2.

THE CHARACTERISTICS OF METASTABILITY
In order to define the metastability characteristics of a device three things must be known: first, what is the likelihood that the device will enter a metastable state? This propensity is defined by the parameter T0. Second, once the device is in a metastable state how long would it be expected to remain in that state? This parameter is tau (t) and is simply the exponential time constant of the decay rate of the metastability. It is sometimes called the metastability time constant. The final parameter is the measured propagation delay of the device. Commonly, the typical propagation delays found in the data book are used for this and it is designated h in the equations (although most designers are familiar with this value as

Tpd). Now lets see how tau and T0 are determined by measurements.
A TEST METHOD
Suppose we wanted to measure the metastability characteristics of a fictitious edge-triggered D-type flip-flop and we had a test system that would count each time the flip-flop is found in a metastable state at some time after a clocking edge. The first thing we would like to know about the flip-flop would be the h or typical propagation delay. We could measure the delay or look it up in the data book (of course. measuring the actual delay would allow more precise results). This fictitious flip-flop has an h of 7ns. In this test we decide to use a clock frequency of 1OMHz. This frequency is primarily a function of the test systems ability to assimilate the information. The data will

run at 5MHz asynchronously to the clock and with a varying period. This frequency was chosen because at two transitions per cycle the data signal produces 10 million points each second where it is possible for the flip-flop to go into a metastable state, an average of one point for each clock pulse. An important point about the characteristic of the data signal in relation to the clock is that the data transitions must have an equal probability of occurring anywhere within the clock period or the results could be skewed. In other words, we need to have a uniform distribution of random data transitions (high and low) relative to the clocking edge.
The first measurement we take is to determine the number of times the device is still in a metastable state Bns after the clock edge. With this device there are 792 failures after 1 billion clock cycles. Changing the time to 9ns we measure 65 failures after another 1

October 1993

568

Philips Semiconductors Programmable Logic Devices
A Metastability Primer

Product specification
AN219

billion cycles. Because metastability resolves as an exponentially decaying function the two points define the exponential curve and they can be plotted as shown in Figure 1. An equivalent plot can be made using a semilog scale as in Figure 2. The slope of the line drawn through the two points represents tau. With these two points the tau can be determined by equation (1 ):
(1)

where N1 and N2 are the number of failures at times t1 and t2, respectively.
Working through the numbers gives us a tau of 0.40ns. Tau of this order is representative of the FAST line of flip-flops.
Earlier we stated that T0 is an indicator of the likelihood that the device will enter a metastable state. Now we will attempt to explain it. At 9ns after the clock we observed 65 failures in 1 billion clock cycles. Since the data transits on average once per clock cycle and the period of this clock is 1OOns, from equation (2) we can say that there appears to be an aperture about 0.0065 picoseconds wide at the input of the device that allows metastability to occur for 9 or more nanoseconds. Another way of explaining the same thing would be to suppose that if 1 billion data transitions were uniformly and randomly distributed over a clock period of 1OOns: you would expect 65 of these transitions to cause the outputs to go into a metastable state and remain there for at least 9ns.
(2)

Where Neg is the number of clocking events at 9ns (in this instance, 1 billion), Pc is the period of the clock, and N9 is the number of failures recorded at 9ns.
By the same reasoning the window at Bns appears to be 0.0792 picoseconds wide. It seems to have grown because there are, of course, more failures after Bns than after9ns. This aperture has been normalized by researchers to indicate the effective size of the aperture at the clock edge, or time zero. Unfortunately the normalization process tends to obscure the interpretation of T0 . T0 can be calculated using equation (3). Figure 3 is an extension of Figure 2 and shows the relationship of T0 , h, and tau.

To= Tse (r8~·)

(3)

38T.o4~8 -

1E7 -"'".,.-- ... - - ... --.,--""'--EXTENDED

... ,

I

SEMI-LOG GRAPH I

1E6

_ _ ,..30,~---1---t---1---

1E5
1E4
A~lj~JVrfE 1E3
PICOSECONDS 100
~~
(10,000)

- - T - - 'f - ... - 't - - "f - - ., - - "1 - - , - - -1 - - -1 - -

t

I "'.t

I

I

I

I

- - + - - .. - - ........- .. - - -I - - ... - - ... - - -1 - - -1 - -

I

I

I

..,1

I

I

t

I

I

-

-

.I. -

-

.I -

-

.I -

-

.J'-., - -l ·'

-

-1 -

-

-I -

-

- 1- -

- 1- -

-

- - .. - - ... - - ... - - ... - - ---.,, - -· - - -1 - - - · - - - 1- - -

""I

I

I

I

-_ ~: ~ ~ ~ -_ -_ ~ -_ -_: -_ -_ :-_ -_ ~~'_..-~-:~_ h~-- -_ -~-- -_ -

(NUMBER
FAIL~~ES)

11o&i\

0.Q1 (100)

0.001 '----~-~-~-~-~---'----'--~--'--'"'-'

Ons

5ns

7ns

9ns

NUMBER OF TIME CONSTANTS

Figure3.

or equivalently,

In this case To is 38.4µs and this value is again typical of the FAST line of products.
Figure 3 is an extension of Figure 2 and gives a graphic indication of T0 . The number of failures plots on the same scale as the aperture size but the number of failures is dependent on the number of clock cycles used in the test (we always used 1 billion in this paper) and the ratio of data transitions to clock pulses (1 :1 in this paper). On the other hand, the aperture size is independent of these things.

MTBF
Having determined the T0 and tau of the flip-flop, calculating the mean time between failures (MTBF) is simple. Suppose a designer wants to use the flip-flop for synchronizing asynchronous data that is arriving at 10MHz, he has a clock frequency of 25MHz, and has decided that he would like to sample the output of the flip-flop 15ns after the clock edge. He simply plugs his numbers into equation (4) .

(f)

MTBF = e - - -

(4)

To Jc f;

In this formula fc is the frequency of the clock, f; is the average input event frequency, and t' is the time after the clock pulse that the output is sampled (of course t' > h). In this situation the f; will be twice the data frequency because input events consist of

both low and high data transitions. For the numbers above the MTBF is one million seconds or about one failure every 11.6 days. If the designer would have tried to sample the data after only 1Ons the MTBF would have been 3.8 seconds.

Metastability literature can be very confusing because several companies use different nomenclature and often the fundamental parameters are obscured by scale factors, so it is important that the user understand MTBF. Lets try a thought experiment to determine the correct MTBF formula. We know the size of the aperture at Bns so we need to know how often that window will occur. This is supplied by the clock period. This gives a ratio of window size to clock period and gives us the likelihood of a transition within the clock period causing a metastable state that lasts beyond the Bns point. Now we need to know the number of input events per clock period to determine the MTBF at Bns. This is supplied by the average input event period and produces the equation below where Pc and P; are the periods of the clock and input events, respectively.

I

MTBF = r, ...1.. ..L
8 Pc Pj

r,8

'c
J4

',·
Ji

(5)

This gives the MTBF for Bns, but how can the formula be developed to handle other times? It has been stated in this paper that the rate of decay of metastable events is an exponential function with a time constant of tau. Using this information gives the equation below where t' is the time after the clock pulse that the output is sampled.

October 1993

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Philips Semiconductors Programmable Logic Devices
A Metastability Primer

Product specification
AN219

.('·-:~)
MTBF = - - -

e(f)

(6)

Tg Jc f;

Tg e (';') Jc/;

,(f)

Tofcf;
A point should be made here about MTBF. This is the mean time between failures and as such does not indicate the average time between failures. In fact, in this situation, the MTBF is the time before which there is a 63.2% probability that a failure would have occurred. Suppose a device has an MTBF of one million seconds like the example above; because the MTBF is an exponential function there is a 9.5% probability that a failure will occur in the first 1.16 days of operation. This might cause the user to feel that the device is failing more than expected. The user would find that 50% of his failures would occur within 8 days. Figure 4 gives a visual interpretation of this idea: time constant one represents one million seconds in this case.

Comparing the T0 of any two devices does not show which device is superior. However, one can expect that the device with the lower tau is superior in all but the most peculiar circumstances.
SUMMARY
This paper is intended to introduce the reader to the terms he will be dealing with regarding metastability and it is hoped that this introduction will help him to digest the more in-depth papers that he will be reading. Philips Semiconductors uses the parameters described by Thomas Chaney of Washington University in St. Louis, Missouri because they are fundamental and the better metastability papers generally use these parameters. For further reading on the subject, the article "Metastable behavior in digital systems", by Lindsay Kleeman and Antonio Cantoni published in IEEE Design & Test of Computers in December of 1987, is recommended.

RECENT DEVELOPMENTS
The quest for better metastability characteristics in flip-flops has recently resulted in the development of flip-flops with taus significantly less than 0.40ns. Perhaps the most notable of these is the Philips Semiconductors 74F50XXX series with typical taus of 135ps. The specifications of these new products can cause confusion among the uninitiated because the typical To on these devices is 9.8 million seconds or about 113 days. This is an example of how the normalization process obscures the interpretation of T0 . In the newest products the taus have decreased faster than the normal propagation delays primarily due to speed limitations of the outputs.
Using the example above and calculating T7 from equation (3) we see that the window at h is 0.965ps. Now lets assume that we have a device with the same size window (0.965ps) at h and an h of 7ns. The difference between this device and the previous example is that this device has a tau of 150ps. Clearly, if the device has the same h and the same size of window at h but a smaller tau, the device is better. But lets calculate the To.
To = T1 e(1;s)
T0 = 178 million seconds!

PROBABILITY

OF

50%

FAILURE

---r-------1-------

----1-------.J ______ _

'

. '

- - - - - f- - - - - - - I - - - - - - -

1

2

NUMBER OF TIME CONSTANTS

Figure4.

October 1993

570

Philips Semiconductors Programmable Logic Products
PLA Devices

INTRODUCTION
Philips Semiconductors PLAs are particularly useful in the design of wide address decoders and random logic replacement. The primary advantage Philips Semiconductors brings to these applications with their PLA devices is product term sharing, which is made possible via the two programmable arrays graphically shown in Figure 1. The familiar PAL® architecture supports a programmable AND array, followed by a fixed OR array. Better than 90% of the PAL devices that are available today are limited to 8 input wide OR gates. When pursuing a solution to a complex address decoding scheme, this restriction is prohibitive. The Philips Semiconductors PLA devices support 100% connection of all product terms to one or more OR gates. Once a term is created, it can be shared with any or all of the output functions. No duplication of resources is incurred. The popular PLXX153 family support 32-input wide OR gates which are ideal for memory or 1/0 decoders. The addition of programmable output polarity also enhances design efficiency and logic minimization.
The two programmable array concept dominates the Philips PLD product line. With the exception of the PAL-type devices which have been geared for ultimate performance, all Philips PLDs have been architected with efficient and flexible PLA structures. With the largest breadth programmable product line in the industry, Philips believes the designer can truly fill his requirements from the several product lines PLA, PAL and PLS. Two combinatorial logic PLA device descriptions follow. For information on PLA devices with registers please refer to the sequencer section of this manual.

PHILIPS SEMICONDUCTORS PLUS153
Figure 2 depicts the Philips PLUS153. This bipolar PLA is pin and functionally equivalent to the Philips PLS 153, however is available with a maximum propagation delay time of 10ns from input to output.
The PLUS153 has eight dedicated inputs and 10 bidirectional pins. The bidirectional pins may be adapted to suite the user's specific needs. 20-pin DIP or PLCC packages are available.
The output structure of the PLUS 153 includes programmable polarity control on each output. Either active HIGH (non-inverting) or active LOW (inverting) outputs are configurable via the EX-OR gate associated with each 1/0. Individual 3-State control of the 1/0 is also supported with the ten direction control AND terms (D1-D9).
Other benefits to the PLUS 153 include full pin compatibility with most 20-pin combinational PAL parts. The natural product term sharing capabilities of the PLA architecture yield complete freedom of configuration should the engineer implement a particularly creative decode configuration.

PHILIPS SEMICONDUCTORS PLUS173
Figure 3 depicts the Philips Semiconductors PLUS173. This bipolar PLA is functionally equivalent to the Philips PLS173. The 24-pin PLUS173 has four more inputs pins than the PLUS153. The user may adapt the bidirectional pins to suit particular decoding needs, but the propagation delay time is still no more than 10ns from stabilized input to stable output for a PLUS 173-10 device.
By having more inputs than the 153 part, the 173 can either resolve more input lines or generate more outputs functions for the same number of inputs. Distinct 3-State control over each output may be useful for controlling chip enables where contention (i.e., multiple access) may exist.
For speed and input width, the PLUS173 is probably the best single PLS available today for both memory and 1/0 decoding. Combining the 1Ons TPD with the distinguishable range of 12 to 21 inputs, the designer can easily decode say 16 input addresses as well as read/write qualifiers or encoded status signals. Output polarity control (Active-High or Active-Low) is achieved by programming the Exclusive-OR gate associated with each output.
The flexibility achieved with a PLA structure can be quickly appreciated by the designer who has experienced the frustration of the dedicated "OR" structures in PAL ICs. Currently, the only time penalty for the freedom granted by a PLA is a few nanoseconds!

® PAL is a registered trademark of Advanced Micro Devices 1<71

Philips Semiconductors Programmable Logic Products
PLA Devices

lo

"2

·~

D

2
·~
2

!2
·~

15

12

:m{ PROGRA 0 AR RAY

0 denotes programmable connection

Figure 1. PLA Architecture

..,

PROGRAM MABLE

>-

AND ARRAy

J
Oo
o,

572

Philips Semiconductors Programmable Logic Products
PLA Devices
31 · · · · · ·24 23· · · · · ·1615· · · · · · 8 7 · · · · · · OXo
Figure 2. PLUS153

Philips Semiconductors Programmable Logic Products
PLA Devices
14 15 17 19 111
XO·:'· 31 · ···· ·24 23· ···· ·16 15· · · · · · 8 7 · · · · · · 0
Fi ure 3. PLUS173 574

Philips Semiconductors Programmable Logic Products
Quick PLA

AN046

INTRODUCTION
The PLUS153-10 is available in a 20-pin DIP or 20-pin PLCC package. The PLUS173-10 is available in a 24-pin DIP or 28-pin PLCC package. Both parts have !po no greater than 10ns.
Both parts provide 32 wide input product terms, whose outputs may be tied to the inputs of the sum terms (OR gates) below. There are no restrictions on this interconnect - any or all product terms may feed any or all sum terms. Thus each OR term can accept from 1 to 32 inputs without leaving the chip for a signal "wrap around". All ten outputs are bi-directional, so they may be traded off as inputs are used. Finally, each output may be polarity configured (exclusive-OR fused) and each is independently 3-Stateable from a separate product term (each) which is identical to the rest.
Although slightly slower (from pin to pin) than 7.Sns 20L8 structures, the following example demonstrates a simple case of how a 1Ons PLA can be faster than a 7.Sns PAL.
Example 1: Glue Collection
This first example is an illustration of compressing glue logic. Figure 1 shows a piece of logic which performs one of two operations on two 8-bit numbers. These may come from different registers in a system, or be from two halves of a 16-bit bus. The goal is to perform the input operations (compare the bytes in one mode or multiplex one bit out in the other) in 1Ons. Using MSI parts, this could have been done except there is no 16 to 1 MUX available in the 74F device series. There is a 74150 device available, but it has a propagation delay of 17ns. So this will not work. Figure 1 shows the solution using the 7.Sns PAL devices. Unfortunately, because architecture provides only seven product terms per sum term ( 16L8-7) multiple signal passes are required. This results in a solution needing over 20ns. It might be conjectured that a 15ns 22V10 could make it with 16 product terms on some outputs, but doing the MUX would only provide the output at "point 1" in 15ns. Additional time is needed to make the final out signal. A 1Ons 22V10 could not make spec, with an additional 74F32 adding 4ns. Figure 3 shows the preferred solution - a single PLUS173 generating the final function in 10ns. Figures 4 and 5 show the pinout and SNAP equations for this solution.

Example 2: Cache Update Inhibit
Key to modern microsystem design has been simple, fast RISC processors with quick cache and single cycle high performance operation. Unfortunately even using the new cache control chips, exception handling results in clumsy designs. This may be one of the reasons simple, direct-mapped caches have also become popular. Exception handling is often resolving transactions which occur with data items that are non-cacheable. This occurs in a number of ways - first, EPROMs, 1/0 devices and special state registers are not cacheable items, so they will never be put into a cache memory. What happens when a non-cacheable item is referenced? The cache controller will miss and begin to update the cache. The transaction must be terminated before it overlays an 1/0 device onto the least recently used cache address.
The way to deal with the transaction overlay problem is straightforward - recognize all non-cacheable transactions and intercept them before the controller cleans house. How big of a problem is this? Figure 6 shows what might be an average engineering workstation. Each device (disk controller, LAN controller, keyboard, printer, etc.) usually has several internal registers each occupying a unique address. With two disks, a LAN, modem and printer, a system could instantly exceed 16 distinct 1/0 registers. It is best to assume a large number. Enter the PLA the PLUS173-forsuchasystem. Each product term can be scattered all over memory if needed and decodes summed into a single output signal generating a composite inhibit. This process takes less than 1Ons for up to 32 devices. Using a 20L8-7 requires trading off resolution (number al address bits resolved) and feeding through the chip multiple times, expanding to 13 devices in two passes (at 15ns for a 7.Sns device). Using a PLA keeps the RISC design very clean and fast.
Example 3: Interfacing Mixed Memory Types
Other sections of a microprocessor system can use the summation cl a large number of decoded terms. For instance, the interrupt request, OMA request and the cycle extension WAIT line are contenders for a large number of decoded and summed inputs. Some are asserted low and some high so polarity control is vital. Some require

a 3-State or open collector resistive pull-up, so the PLA enable fits well. These are situations where attention signals come into the processor.
It is not always necessary for the CPU to operate at full speed. Operating the CPU at a slower speed brings about a more economical and compact system. This is due to higher costs associated with fast memory and greater board area for wide memory configurations.
Some software routines where slower performance may be acceptable include power up initialization, diagnostic routines, or some exception routines. When speed is critical, an 8-bit bus is the most economical and compact because of readily available byte wide PROMs and RAMs. The 68030 is easily interfaced to 8-, 16- or 32-bit ports because it dynamically interprets the port size during each bus cycle. Figure 7 shows an example of interfacing both a slow 200ns 8-bit EPROM and a fast 35ns 32-bit RAM to a 68030. A PLUS173-10 was chosen for its high speed and large number of inputs and outputs. The EPROM occupies memory space 0-32K while the RAM occupies addresses 64-128K. Note that because not all of the upper memory address bits were decoded, the memory arrays will also appear at other addresses.
PROBLEM: 16-bit Data Compare I MUX Mode 1: Compare two 8-bit fields Mode 2: Select 1 of 16 bits Must be fast!
SOLUTION 1:
8-BIT COMPARE
74F521
MODE
16-BIT TOONE
MUX 74150
Figure 1.

575

Philips Semiconductors Programmable Logic Products
Quick PLA

SOLUTION 2: MAKE IT OUT OF PALs A(0·.7] ---,>'--'.......,>----< B[O..7] __,,,,_'--i>--<1>----I
16L8-7.5
SELECT - -4-+--+-----1

) 2 WASTED 1/0 PINS

SOLUTION 3: MAKE IT OUT OF A PLUS173D

A[0.. 7] B[0 .. 7] S[0 .. 3] MODE

PLUS173-10

OUT

tpo- 10ns 1 PACKAGE
COMPARE FUNCTION: 16 PRODUCT TERMS
MUX FUNCTION: 16 PRODUCT TERMS
INVERTERS: INCLUDED
QBS.: INCLUDED
GATE EEEIC!ENCV: 1 PLA 32 GATES USED NO GATES WASTED
BEllUl.I:
THE BEST SOLUTION: ONE PACKAGE
Figure3.

Figure 2.

N Package

A1

S3

S2

A3

S1

so

A5

MODE

87

86

BO

85

81

B4

82

OUT

83

Figure 4. Comparator/MUX Pin Program

3) 7.5PALs 1) 20L8-7.5 2) 16L8-7.5

COMPARE FUNCTION:
IPD = 7.5 (1st PASS-#t)
· 7.5 (2nd PASS-#1)
= 7.5 (3rd PASS - #3)
.. 22.Sns

MUX FUNCTION:

IPD · ·

7.5(1stPASS-#2or3) 7.5 (2nd PASS - #2 or 3) 7.5 (3rd PASS - #3)

.. 22.Sns

GATE EFEIC!FNCV: 30 PALs 40 GATES USED 152 GATES WASTED
RESULT: NOT FAST ENOUGH; SLOWER THAN 74F SOLUTION

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Philips Semiconductors Programmable Logic Products
Quick PLA

@PINLIST a[0 .. 7] i; b[0..7] i; s[0..3) i; MODE i;
OUT o·

@GROUPS sel = s[0..3);

@TRUTHTABLE @LOGIC EQUATIONS

comp

ao· bO/mode + laO · bO /mode + a1 · b1 /mode + /a1 · b1 /mode + a2 · b2 /mode + /a2 · b2 /mode + a3 · b3 /mode + /a3 · b3 /mode
a4 · b4 /mode + /a4 · b4 /mode + as · b5 /mode + /aS · bS /mode + as · b6 /mode + /aS · bS /mode + a?* b? /mode + la?· b? /mode;

mux mode

ao · (sel ==Oh)· mode + a1*(sel==1h)* + a2 · (sel == 2h) · mode + a3 · (sel == 3h) ·mode + a4 · (sel == 4h) ·mode + as · (sel == Sh) · mode + as· (sel ==Sh)· mode + a?· (sel == ?h) ·mode
bO · (sel == Bh) ·mode + b1 · (sel == 9h) ·mode + b2 · (sel ==Ah)· mode + b3 · (sel == Bh) ·mode + b4 · (sel ==Ch)· mode + bS · (sel == Oh)· mode + bS · (sel == Eh)· mode + b? · (sel == Fh) · mode;

out= mux +comp;

@INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANSITIONS

Figure 5. SNAP Equation Listing Seotember 1993

32-BIT MICROPROCESSOR

TO MAIN MEMORY CACHE/CONTROLLER

TAG COMPARE

CACHE RAM

ADDRESS 1

UPDATE INHIBIT TO UO DEVICES

ADDRESS2 ADDRESS3

UPDATE INHIBIT

ADDRESSn
Figure 6. Cache Update Inhibit Using a PLA

S77

Philips Semiconductors Programmable Logic Products
Quick PLA

AO-A14

27C256
32KXB t-~~~~~~~~~
EPAOM

MC6BOOO
CLK 00--031

20MHz CLOCK GENERATION
CLK

AO-A31 AS

AS A31 A30 A19 A18 A17 A16 A1 AO

DLYIN

STEAM DSACKO

SIZO SIZ1 AW
PLUS173-10

ACK1

74F244

32 A2-A15

D

Q

TWO 16Kx4 SRAMs

E

"::"

D

Q

TWO 16Kx4 SRAMs
w

"::"

D

Q

TWO 16Kx4 SRAMs

w "E

"::"

D

Q

lWO 16Kx4 SRA Ms

w

"::"

EPAOM SEL

Figure 7. Example Interfacing Mixed Memory Types

September 1993

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Philips Semiconductors Programmable Logic Products
Quick PLA

DECODER FOR INTERFACING SRAMa AND EPROMs TO AN MC68000. THIS DESIGN IS FOR A PLUS173 DEVICE

@PINLIST

diyin i;

nas i;

a{31 ..30)

a{19 .. 16) i;

a[1..0) i;

sizO i;

siz1 i;

rw

i;

nrmcs o;

dstrt o;

nuucs o;

numcs o; nlmcs o;

nllcs o;

napes o;

nack[1 ..0] 0

@LOGIC EQUATIONS
"EPROM enable" napes= I ( /a31 · ta30 · ta19 · 1a18·1a17· 1a16·1 nas;

"start shift register during EPROM access" dstrt =/( /a31 · ta30·ta19·1a18·1a11· 1a16·1 nas;

"DSACKO after 4 clock cycles for EPROM access" nackO = I (dlyin);

"immediate STERM upon RAM access" nack1 =I ( /a31 · /a30 · /a19 · /a18 · /a17 · /a16);

"Byte select signals for RAM writes"

nuucs /(/ao·ta1 ·

1rw·a1s·1a17·119·1a19·1a3o·ta31);

nuucs I ( aO · /a1 · + I a1 · /sizO · + I a1 · /siz1 ·

/rw · a16 · ta17 · 11a · /a19 · ta30 · ta31 /rw · a16 · ta17 · /18 · /a19 · ta30 · ta31 /rw · a16 · /a17 · 11a · /a19 · ta30 · ta31);

nlmcs

I ( /aO · /a1 · + I a1 · /sizO · /siz1 · + I a1 · sizO · /siz1 · + /a1 ·ao·tsiz0·

/rw · a16 · 1a11·118 · ta19 · ta30 · ta31 /rw · a16 · ta17 · 118 · ta19 · ta30 · ta31 /rw · a16 · /a17. /18 · ta19 · ta30 · ta31
1rw·a1s·1a11·119·1a19·1a3o·ta31);

nllcs

I ( aO · a1 ·

+ aO · sizO · siz1 ·

+ I sizO · /siz1 ·

+ I a1 ·

siz1 ·

/rw · a16 · ta17 · 118 · /a19 · ta30 · ta31 /rw · a16 · ta17 · 119 · ta19 · ta30 · ta31 /rw · a16 · ta17 · 118 · ta19 · ta30 · ta31
/rw · a16 · ta17 · 11a · /a19 · ta30 · ta31);

nrmcs I (

/rw · a16 · ta17 · /18 · ta19 · /a30 · ta31);

NPac:kage

Figure 8. Equations for PLUS173 Shown In Figure 7

NRMCS DST RT NUUCS NUMCS NLMCS NLLCS NEPCS NACK1 NACKO RW SIZ1

Seotember 1993

579

Phillps Semiconductors Programmable Logic Devices
Latches and flip-flops with PLS153

Application Note
AN014

DESCRIPTION Using the simple AND, OR and INVERT logic functions of the PLS153, memory functions such as latches and edge-triggered flip-flops may be implemented with a relatively small part of the chip and without external wiring. In this application note, we will discuss the implementation of two R-S latches, a D-latch, an edge-triggered R-S flip-flop, an edge-triggered D flip-flop, and an edge-triggered JK flip-flop.
SIMPLE R-S LATCH A simple R-S latch may be formed by cross-coupling two NANO functions together as shown in Figure 1.
NA2
Figure 1. RS Latch

N02
Figure 3. RS Latch

@pinlist

r i;

s
q
qn

itb·i·;

@logic equations
qn = (/q'/s); q = (/r'/qn); qn-oe=1; q-oe = 1;

Figure 4. RS Latch SNAP Equations

.
·

This circuit may be expanded to have multiple D-latches using the same latch enable (LE).
a. Pinout
D 0---<1>-'-lr---
LE v-.,-,--,.___,,
Q

@pinlist

r i;

s
q

i·
b;

qn b·

@logic equations qn =/(q*s); q = /(r'qn); qn-oe=1; q-oe= 1;
Figure 2. RS Latch SNAP Equations

ANOTHER SIMPLE R-S LATCH Another way to implement a simple latch is shown in Figure 3, in which two NOR functions are cross-coupled to form a latch.
The SNAP equations are shown in Figure 4.
Since each AND-term of the PLS153 can accommodate up to 18 inputs (true or inverting inputs of eight from 10 to 17 and ten
from Bo to 89), and each OR circuit can be
connected to up to thirty-two AND-terms, we can add additional features such as those shown in Figure 5.
The programming of this design is left to the reader as an exercise.

Q
ti
. .
·· ··
87
Figure 5. Expanded RS Latch
D-LATCH A simple D-latch can be constructed with a PLS153 as shown in Figure 6. This circuit may be easily programmed into the PLS153 as shown in Figure 7. Note that according to the K Map of Table [1 ], there is a static hazard using only two gates, so the D · Q term is recommended.

AN2
b. D-L.atch Schematic Figure6.
@pinlist d i· le i· q o·
@logic equations q = ((d' le)
+ (d. q) + (d ·/le));
F.!s!Jre 7. D- Latch SNAP ~atlons

Philips Semiconductors Programmable Logic Devices
Latches and flip-flops with PLS153

Table 1.

d,Le

0

00

0

D-Latch K Map

01

11

10

Application Note
AN014
81

R·S FLIP-FLOP

Two R-S latches may be combined to form a

master-save flip-flop that is b'iggered at the

CU<

rising-edge of the clock (or the falling-edge of

the clock, if the designer so desires). Figure 9

shows a combination of two sets of

cross-coupled NOR gates concatenated to

form the flip-flop. The implementation of this

circuit using SNAP equations is shown in

Figures.

CLK A
s

Agure 9. R-S Edge Triggered Latch

ON

BO

a

81

a. Pinout

@pinlist

elk i;

r i·

s bO

ib· ;

b; b1 b·
q

qn b;

@logic equations
qn :/ (q + (b1 · elk) );
q :/((elk· bO)
+qn); b1 :/ bO
+ (s "/elk); bO: I ((r ·/elk)
+b1):

b0-oe:1; b1·Oe:1; q-oe:1; qn-oe:1;
Figure 8. SNAP Equations

CLK
AST INY

Figure 10. D-type Alp-Flop

CLK D
AST SET
TEMP

@pinlist
~k ::
rst i· set i; q o; tempo;
@logic equations temp: ( (d" /clk" /rst)
+ (d · temp· I rst) + (temp ·I rst ·elk) +(set);
Q : ((temp · elk · I rst) + (temp · q ·I rst) + (q ·I rst · I elk) + (set);

Figure 11. SNAP Equations and Pinout

D FLIP-FLOP
An edge-b'iggered master-slave D flip-flop may be constructed with two D-latches in the manner shown in Figure 10.

A PLS153 may be programmed as shown in Figure 11 to implement ihe D flip-flop.

September 1993

581

Philips Semiconductors Programmable Logic Devices
Latches and flip-flops with PLS153

Application Note
AN014

AN4

U9 K
INV

U7
OR6 AN3

U6
a
OR4
AN3

CLK INV
RST INV
SET

Figure 12. JK-type Flip-Flop

@pinlist

elk

CLK

j

0

k

rst i·

RST

set i;

q o;

SET

tempo;

@logic equations
temp = ( O·I elk· I rst · /q)

+ (/elk · I k ·q · I rst)

+ O· I rst · temp · /q)

+ (temp · /rst · elk)

TEMP

+ (set);

q =( (temp · elk ·I rst)

+ (temp·q· trst)

+ (I rst · q ·I elk)

+ (set);

Figure 13. SNAP Equations and Plnout

JK FLIP-FLOP An edge-triggered J K flip-flop schematic is shown in Figure 12. SNAP equations and pinout are shown in Figure 13.

September 1993

582

Philips Sernlco"_ductors Programmable Logic Devices
PLS173 as a 10-bit comparator, 74LS460

Appllcatlon Note
AN024

DESCRIPTION
The PLS173 is a 24-pin PLA device which has 10 bidirectional outputs and 12 dedicated inputs. The output of the device is the sum of products of the inputs. The polarity of each output may be individually programmed as Active-High or Active-Low. A 10-bit comparator similar to the 74LS460 compares two 10-bit data inputs to establish if EQUIVALENCE or NOT EQUIVALENCE exists. The output has True and Complement comparison status outputs. The logic diagram of the comparator is shown in Figure 1.

The truth table is as shown in Table 1 where vectors a and b are 10-bit inputs to A9 to AO and 89 to BO. If the input to A9-AO is bit-to-bit equivalent to the input to 89-80, the two input vectors are considered EQUIVALENT, and output EQ goes High and NE goes Low. If the two input vectors are not bit-to-bit equivalent, then EQ goes Low and NE goes High. The circuit is implemented with SNAP as shown in Figure 3.

Table 1. Function Table

Ag-Ao a b a b

Bg-Bo EQ NE

a

H

L

b

H

L

b

L

H

a

L

H

Vee

RESOURCES
This design used 20 product terms in the PLS173. As shown in Figure 4, expanded equations, each output needs 20 product terms. Since the product terms are the same, each output shares the 20 product terms with an output polarity fuse determining the proper output level.

D Package

B9

A9

BB AB NE EQ

87

A7

84

86

A6

GND

85

Figure 2. Pin Configuration
This circuit compares to two 10-bit inputs. If they are bit-to-bit equivalent, output EQ goes high and NE goes low. If they are not bit-to-bit equivalent, output EQ will be low while NE will be high.

84 GND

Bg Ag Ba As NE EQ 87 A1 85 As 85 TOP VIEW

Figure 1. Logical Equivalent Circuit of 10·Bit Comparator

@PINLIST

A[0..9] i;

B[0.. 9]

EQ

o;

NE

o·

@GROUPS

one

a[0 .. 9];

two

b[0 .. 9];

@TRUTHTABLE @LOGIC EQUATIONS

EQ = one == two; NE= one !=two;
@INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANSITIONS

These equations are written for Philips Semiconductors SNAP software.
Figure 3. Boolean Equations of 10-Bit Comparator

@LOGIC EQUATIONS

eq

/((/b9.a9)

+ (b9.a9)

+ (b8'/a8)

+ (/b8'a8)

+ (/ b7' a?)

+ ( b7' /a?)

+ (b6'/a6)

+ (/b6'a6)

(b5·/a5)

+ (b5'/a5)

+ (/b5'a5)

+ (/b4 · a4)

+ (b4'a4)

+ (I b3' a3)

+ (b3'/a3)

+ (/b2'a2)

+ (b2'/a2)

+ (/b1 ·a1)

+ (b1 '/a1)

+ (bO'/aO)

+ (I bO · aO) );

ne

((/b9'a9)

+ (b9'a9)

+ (b8'/a8)

+ (/b8'a8)

+ (I b7' a?)

+ (b7'/a7)

+ (b6'/a6)

+ (/b6'a6)

(b5'/a5)

+ (b5'/a5)

+ (lb5'a5)

+ (/b4'a4)

+ (b4'a4)

+ (/b3'a3)

+ (b3'/a3)

+ (/b2'a2)

+ (b2'/a2)

+ (/b1'a1)

+ ( b1 'I a1 )

+ ( bO '/ aO)

+ (I bO ' aO ) );

Figure 4. Expanded Equations

Philips Semiconductors Programmable Logic Devices
9-Bit parity generator/checker with PLS1S3/153A·.

Applicatlon Note
AN021

INTRODUCTION
This application note presents the design of a parity generator using Philips Semiconductors PLO, PLS153 or PLS153A, which enables the designers to customize their circuits in the form of ·sum- of-products". The PLA architecture and the 10 bi-directional I/O's make it possible to implement the 9-bit parity generator/checker in one chip without any exlemal wiring between pins.
The parity of an 8-bit word is generated by counting the number of "1 's" in the word. If the number is odd, the word has odd parity. If the number is even, the word has even parity. Thus, a parity generator designed for even · parity, for example, will generate a "O" if the parity is even, or a "1" if parity is odd. Conversely, an odd parity generator will generate a "O" if the parity of the word is odd, or a "1" if the parity is even. This bit is then concatinated to the word making it 9-bits long. When the word is used elsewhere, its parity may be checked for correctness.
FEATURES
· Generates even and odd parities (SUME and SUMO)
· SUME = ·1 ·for even parity, "O" for odd parity
· SU MO = "1" for odd parity, "O" for even parity
· Generate parity 'or check for parity errors
· Cascaded to expand word length

io--i 11--1 12--1
13--+I 14--+I IS - - + I

~
,_____
SU2 ~

SUMo SUMe

1s--I 11--1 1a--i

~

lo 11 12 SU1

0 0 0

0

0 0 1

1

0 11

0

0 10

1

10 1

0

10 0

1

1 1 0

0

1 1 1

1

I:! 14 Is SU2

0 0 0

0

0 11

0

0 0 1

1

0 10

1

10 1

0

1 10

0

1 0 0

1

1 11

1

Is 17 le SU3

.0 0 0

0

0 11

0

10 1

0

1 10

0

0 0 1

1

0 10

1

1 0 0

1

1 11

1

SU1 SU2 SU3 SUMO SLIME

0

0

0

0

1

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

0

DESCRIPTION
The most straightforward way of implementing the parity generator/checker is to take the 9-input truth table (8 inputs for the 8-bit word, and 1. input for cascading the previous stage) and put it in a 256 x 4 PROM. Since there are ~combinations and half of them is odd, the other half is even, the circuit will take 256 terms.
An alternative is to divide the 9-bits into 3 groups of 3-bits as shown in Figure 1. If the sum of the 3-bits is odd, then the intermediate output SU1, or SU2, or SU3 equals 1. Otherwise it equals 0. The · intermediale results are grouped together and SUMO becomes "1" if the sum is odd, otherwise SUMO equals "O".
The circuit is implemented using SNAP as shown in Figure 3. SU 1 is an intermediate output for inputs 10, 11 and 12· In the same manner, SU2 and SU3 are intermediate outputs for 13, 14, Is and Is, 17, 18·

Figure 1. Block Diagram of 9·Bit Parity Generator/Checker

RESOURCES
The design uses up 20 product terms and 5 control terms leaving 12 product terms and 4 bi-directional I/O's to implement other logic designs.

D Poclcage

INO

IN1

SLIME

IN2

SUMO

IN3

IN4

INS

IN6

SU3

IN7

SU2

INS

SU1

Figure 2. Pin Configuration

SAo!RmbAr 199~

!iR4

Philips Semiconductors Programmable Logic Devices
9-Bit parity generator/checker with PLS153/153A

Application Note
AN021

@PINLIST

ln[0 .. 8)

sul1 .. 3) o;

sumo

o;

sume

o;

@TRUTHTABLE

This circuit Is a 9-bit parity generator/checker commonly used for erra detection In high speed data transmission/retrieval. The odd parity output (SUMO) is high when the sum of the data bits is odd. Otherwise it is tow.
The even parity output (SUME) is high when the sum of the data bits Is even. Otherwise it is low.
SU3, SU2 and SU1 are intermediate terms. This design was done using the Truth Table Entry method of Philips Semiconduc.1ors SNAP software.

l1N2, IN1, INO SU1)

0.

1·

1;

O; 1·

O· 0.

1·

[INS, IN4,

IN3 : SU2) 0. 1; 1· O· 1· O· 0. 1;

[INS, IN7, INS

SU3) 0. 1· 1· 0. 1; 0; 0. 1·

[SU3, SU2, SU1 : SUMO, SUME)

1;

1 ·

o·

0; 1· 0.

1·

1·

0;

Figure 3. SNAP Truth Table Entry

@logic equations

su 1

((in2 · in 1 · inO)

+ (in2 · in1 · inO)

+ (/in2 · in 1 · /inO)

+ (/in2 · /in 1 · inO);

su2

( (in5 · in4 · in3)

+ (in5 · in4 · in3)

+ (/in5 · in4 · /in3)

+ (/in5 · /in4 · in3);

su3

((ins· in?· in6)

+ (ins· in?· in6)

+ (/ins · in 7 · /in6)

+ (/ins · fin 7 · in6);

sumo

( (su3 · su2 · su1) + (su3 · /su2 · /su1) + (/su3 · su2 · /su1) + (/su3 · /su2 · su1 );

sume

( (su3 · su2 · su1) + (su3 · /su2 · /su1) + (/su3 · su2 · /su1) + (/su3 · /su2 · su1 );

Figure 4. Expanded Equations

September 1993

585

Philips Semiconductors Programmable Logic Devices
Schmitt trigger using PLS153

Application Note
AN018

Issued June 1988; revised October 1990; revised September 1993

INTRODUCTION
One of the many features of the PLS153 is the availability of individually controlled 3-State 110 pins. Taking advantage of this feature, a Schmitt trigger may be constructed using one input pin, two bidirectional 1/0 pins and additional components of three resistors. The two threshold voltages, as well as the hysterisis, are determined by the values of the three resistors and the parameters of the PLS153 device, which are 1) input threshold voltage, VrH, 2) High output voltage, VoH. and 3) Low output voltage, Vol- The circuit may be simplified if Schmitt function is needed only on Low going High or High going Low, and if the hysterisis and threshold voltages are not important.

starts at zero volt, the output voltage is
therefore at Vol which causes 0:1 to pull Ra
towards ground. As the input voltage increases, only a traction of the voltage is impressed upon the input buffer due to the dividing network R1 and Ra. As soon as the input voltage reaches a point where V1=VTH (VTH=1.38V typical), the output switches to VoH which, in turn, turns off 0 2 and turns on 01. V1 will jump to a value greater than VTH and 01 then pulls the input pin, through R2, towards VoH. which in turn locks the output to a High state even if the input voltage fluctuates, as long as it does not ftucb.late outside of the designed hysterisis. When the input voltage goes from a High to a Low, the Schmitt function repeats itself except that 0 1 and 0 2 reverse their roles.

DESCRIPTION
A simplified block diagram of a non-inverting Schmitt trigger is shown in 1 where R1, R2, and R1· Ra, form two pairs of voltage dividers one of which get into action at input voltage direction of High going Low and the other
Low going High. Assuming that input voltage

The triggering voltages, VH (Low going High) and Vl (High going Low) are:
VH=VrH [(R1+Ra)IRa]-Vol (R1/Ra):
Vl=VTH [(R1+R2)/R2]-VoH (R1/R2);
where, at room temperature, Vee = 5.0V, loH/lol<1 mA. Vm is the threshold voltage of

the device, typically 1.38V; Vol is the output Low voltage of the device, typically 0.36V at
1 IOL I <1 mA; VoH is the output High voltage of the device, typically 3.BV at I loH I <1mA.
The implementation of 1 using PLS1531153A is as shown in Figures 2a and 2b. A scope photo of the operation of the circuit is shown in Figure 6.
An inverting Schmitt triggered buffer may be constructed using the same principle. A simple block diagram of such inverter is shown in Figure 3a. The circuit is implemented as shown in Figures 3b and c.
If the voltage levels (VL and VH) and the hysterisis are not critical, one 110 pin may be used to pull the input pin High and Low. Therefore one 110 pin and a resistor may be saved. The drawback is that the range of VH and Vl is quite limited. The circuit is as shown in Figure 4.
If Schmitt function is needed only in one direction, one of the resistor/output circuit may be eliminated. The circuit is as shown in Figure 5.

+Vee

INPUT

t;

0

OUTPUT

>

Figure 1. Simplified Block Diagram of a Schmitt Trigger

~ontomhor 1 QQ':l

Philips Semiconductors Programmable Logic Devices
Schmitt trigger using PLS153

INPUT

PLS 153/153A TO OTHER AND TERMS

Application Note
AN018

a. Using PLS153/153A

NOTE: Schmitt trigger output may be obtained from both 10 and 8(1)0 to drive the AND-ARRAY.

SNAP LISTING FOR A SCHMITI TRIGGER FUNCTION. EXTERNAL RESISTORS ARE REQUIRED AS SHOWN ABOVE.

@pinlist

input i;

output b

81

o;

82

o;

@logic equations output output.oe =

input; 1

81.oe 81

/output;
o·

82.oe 82

output 1;

b. SNAP Equations Figure 2. Schmitt Trigger

September 1993

587

Philips Semiconductors Programmable Logic Devices
Schmitt trigger using PLS153
+Vee

INPUT

!::;

OUTPUT

> 0

=
a. Simplified Block Diagram

Application Note
AN018

September 1993

b. Using PLS153

SNAP LISTING SHOWING INVERTING SCHMID TRIGGER FUNCTION.

@pinlist

b input i·
output

B1

o;

B2

o;

@logic equations

output

I input;

output.oe =

1

B1 .oe B1

output; O;

B2.oe B2

output 1;

c. SNAP Equations

Figure 3. Inverting Schmitt Trigger

588

Philips Semiconductors Programmable Logic Devices
Schmitt trigger using PLS 153

Application Note
AN018

4K

INPUT

v

16K

OUTPUT

SNAP LISTING SHOWING SCHMITT TRIGGER USING ONE VO PIN TO PULL INPUT HIGH OR LOW.

@pin list

input i;

output b

B1

o;

81 L--<J-1------~
VL · 0.78V, VH · 1.6V

@logic equations output output.oe =

a.

B1

B1.oe

b. Figure 4. Schmitt Trigger Using One 1/0 Pin

input; 1
output; 1·

INPUT

OUTPUT

SNAP LISTING FOR SCHMITT TRIGGER FUNCTION IN THE HIGH TO LOW DIRECTION ONLY.

@pin list

input i;

output b

B1

o;

@logic equations

output

input;

output.oe =

1

a. High Going Low Direction

B.oe B1
c.

output; 1;

R1 INPUT
-'VI/lo

E 2 >---R -------OUTPUT 3

SNAP LISTING FOR SCHMITT TRIGGER FUNCTION IN THE LOW TO HIGH DIRECTION ONLY.

@pinlist

b input i·
output

B1

o·

81

@logic equations

output

input;

output.oe =

1

b. Low Going High Direction

B1.oe B1

/output; 1;

d. Figure 5. Schmitt Trigger

Output

NOTE: R1·3.9k<l, R2 · 10.Sk..k<l, R3 · 2.0k<l, Vee = 5.0V, Ambient temperature ,,. 25ac

Input
0.5ms/div
Figure 6. A Non-Inverting Schmitt Triggered Buffer

Phillps Semiconductors Programmable Logic Devices
Sequencer devices

INTRODUCTION
Ten years ago, in their search for a straightforward solution to complex sequential problems, Philips Semiconductors originated Programmable Logic Sequencers. Philips Semiconductors Programmable Sequencers represent a product line which combines the versatility of two programmable arrays (PLA concept) with flip-flops, to achieve powerful state machine architectures.
Each arrangement or "architecture" offers a variation of the basic concept which combines two programmable logic arrays with some flip-flops, in an undedicated fashion.
The PLA product terms are oo.t specifically
dedicated to any particular flip-flop. All, none, or any mix in between may be connected to any flip-flop the designer chooses. The PLA structure therefore supports 100% product term-sharing as well as very wide OR functions preceding the flip-flops.
Philips Semiconductors line of Programmable Logic Sequencers has been further customized to accommodate specific types of state machine designs. Some have both registered and combinatorial outputs, specifically for synchronous and asynchronous Moore-type state machines. Others have state or buried registers, as well as output registers. These devices (PLUS105, PLC42VA12 and PLUS405) are ideal for synchronous Mealy-type applications.

J-K and S-R register functions are another benefit. The logic functions provided by these types of registers far exceed the capability of a D-type register. The functionality of the J-K allows the designer to optimize the logic used in generating state transitions. Ninety percent of PAL devices have D-type registers. All the sequencers are equipped with three state options for bussing operations, JK or SR flip-flops and some form of register Preset/Reset functions.
Finally, all PLS devices have a Transition Complement Array. This asynchronous feedback path, from the OR array to the AND array, generates "complement" transition functions using a single term. Virtually hidden in between the AND array and the OR array is the Complement Array. This single NOR gate is not necessarily "an array," however the inputs and outputs of this complement gate span the entire AND array. The input(s) to the Complement Array can be any of the product terms from the AND array. The output of the Complement Array will be the 'complement' of the product term input. If several product terms are connected to the Complement Array, their respective complements can also be generated. The output of the Complement Array is fed back to the AND array, whereby it can be logically gated through another AND gate and finally propagated to the OR array. The significance being that the complement state of several

product terms can be generated using one additional AND product term. For example, if an efficient method of sensing that no inputs were asserted was needed, the designer could connect the output of appropriate AND gates to the complement NOR gate. The output of the NOR gate could then be used to condition and then set or reset a flip-flop accordingly. As well, he could detect a particular state variable combination and force a transition to a new state, independent of the inputs. Or he could combine input signals and state (AND) terms to generate a new composite term. In any of these applications, the Complement Array greatly reduces the number of state transition terms required.
In order to present the material in the most concise fashion, a brief state equation tutorial is presented first. The PLUS105 description immediately follows. In this capsule description, the level of detail is expanded, so read it first for basic understanding. Each additional presentation will be done with regard to the fundamentals described for the PLUS105. Figure 3 shows the detailed drawing of the PLUS105 in full detail. Figure 4 shows a compressed rendition of the same diagram so that the reader can understand the diagram notation. The compressed shorthand version will be used for the rest of the sequencers.

Figure 1. Up-Down Counter State Diagram

While While While When

[STATE OJ

IF

[UJ

IF

[/DJ

[STATE lJ

IF

[UJ

IF

[/DJ

[STATE 2J

IF

[UJ

IF

[/DJ

[STATE 3J

IF

[UJ

IF

[/DJ

THEN THEN
THEN THEN
THEN THEN
THEN THEN

[STATE lJ [STATE 3J
[STATE 2J [STATE OJ
[STATE 3J [STATE lJ
[STATE OJ [STATE 2J

Figure 2. STATE EQUATIONS to Implement Up-Down Counter for JK or SR Type Flip-Flop Based Sequencer

()Mnhor 1 QQ'=l

Philips Semiconductors Programmable Logic Devices
Sequencer devices

State Equation Tutorial
STATE equation entry is a convenient way to describe elementary sequential machines in a manner which is directly related to a state diagram of the machine. The basic commands are few, but can be combined in a powerful fashion. Figure 1 shows a 4 state up-down counter for a machine with an U(up)/D(down) input line. Figure 2 shows the state equation syntax to implement Figure 1.

The basic meaning can be summarized in the following way. Simply, "While in state X" if
z·. input "Y" occurs, "transverse to state This
is a Moore machine model. Mealy may be accommodated by addition of the "With" operation which designates an output variable being associated as shown below:

A.) While

with IF then

[CURRENT STATE] [OUTPUT VARIABLE) [INPUT VARIABLE] [NEXT STATE]

or

B.) While

IF then with

[CURRENT STATE] [INPUT VARIABLE) [NEXT STATE] [OUTPUT VARIABLE]

If a latched output variable is desired, the addition of a prime notion (/) to the right of the output variable is required.

The designer must assign the binary values of choice to specific states for a state equation function to be implemented. The Philips Semiconductors SNAP manual details state equation solutions with more examples, but the advantage of state equations is that the designer can be less involved with the internal structure of the sequencer than required by other methods.

The PLUS105
This part (Figure 3) has sixteen logic inputs and eight outputs. It also has eight S-R flip-flops tied direcHy to those output pins through 3-State buffers (common control from pin 19). The user may select pin 19 to be an Output Enable signal or an asynchronous preset (PR) signal which is common to all flip-flops. Embedded into the device are 48 AND gates. All flip-flops are S-R type with an
OR gate on both S and R. The designer may choose any number of product terms and
connect them with any OR gate. The product
terms can also be shared across any OR
gate, as needed. Six of the 14 flip-flops are termed "buried registers" as their outputs are fed back to the AND array, regenerating both the Q and IQ state variables. There is no direct connection to an output. Both the input signals and the state variables Q and /Q are
fed to the AND array through buffers which
provided the TRUE (or noninverted) and Complement (inverted) renditions of the variable. This is critical for the efficient use of the AND array. The designer has all state and
input variables necessary to generate any
state transition signal to set and/or reset commands to the flip-flops. Because of this AND/OR arrangement, combined with complete freedom of configuration, all sequential design optimization methods are applicable.
There are many other feature capabilities
suitable for creative usage. For example, it is common practice to use the 48 product terms with the 6-bit buried register, treating the output 8-bit register as an intermediate, loadable data register only. This provides a very good bus "pipeline" for the internal 6-bit machine. However, other logic options can be accomplished by combining internal state information (present state) with current input information, generating a next state which is different from the current internal state.

Philips Semiconductors Programmable Logic Devices
Sequencer devices
Figure 3. PLUS105

Philips Semiconductors Programmable Logic Devices
Sequencer devices =
T 4 1 - - - - - - - - - - To Figure 4. Compressed Drawing of PLUS105
October 1993

Philips Semiconductors Programmable Logic Devices
Sequencer devices

The PLS155, 157, and 159A constitute a three part family of 20-pin sequencers that are well suited for high speed handshakers, counters, shift registers, pattern detectors and sequence generators. Additional applications include testability enhancement, demonstrated in the application examples of signature analysis and pseudo random number generation. The three devices are very similar in architecture. All have a fotal of 12 possible outputs. The difference is the ratio of combinational 1/0 to registered outputs available.
ThePLS155
The PLS 155 is a sequencer providing four J-K flip-flops with a PLA having 32 logic product terms and 13 control product terms. Eight combinational 1/0 are available in

addition to the four registered outputs. All of the state variables and combinational variables are presented to the output pins by way of 3-State inverting buffers. The combinational and state variable outputs are fully connected (fed back) back to the AND array in both the True and Complemented form of the variable. The product includes a special feature that allows the user to configure the flip-flops as either J-K or D flip-flops on an individual basis. A Register Preload feature is supported via two product tenms (La, Lb) which penmit "back loading" of data into the flip-flops, direcUy from the output pins. The part can now be easily forced into any known state by enabling La, Lb, applying data at the outputs (previously "3-Stated"), and applying a clock pulse. Register Preset

and Reset functions are controlled in 2 banks of 2 registers each. Note that control product terms are from the OR array.
The outputs of all variables are 3-State controlled by a unique partition. Pin 11 provides an Output Enable input (OE) which can be asserted with the EA and EB control product tenms. EA controls the flip-flops FO and F1, and EB controls F2 and F3. Each combinational output tenm has a distinct 3-State control tenm (DO - 07) originating from the AND array of the PLA. Each combinational output variable can be programmed as inverting (active LOW) or non-inverting (active HIGH) by way of the output polarity EX-OR gate associated with each 1/0 pin.

(LOGIC TERMS) b

(CONTROL TERMS)

L

D

B

I

I

I

1---~~~~~~~~I

To Fcl

4Copiea

I

L----------------------J

Figure 5. PLS155 Architecture

nrtnhar 1 QQ".:l

o;QA

Philips Semiconductors Programmable Logic Devices
Sequencer devices

The PLS157
This sequencer features all the attributes of the aforementioned PLS155, however, two flip-flops have been added, at the expense of two of the combinational outputs. Pins 13 and 18 on the PLS157 are flip-flop driven, where the same pins on the PLS155 are combinatorial, driven from the PLA Again, all variables (input, output, or state variables) fully connect over the PLA portion with both True and complemented versions supplied.

The number of product terms, the Complement array, Output Enable, 3-State configurations, Register Preload, etc., track the PLS155 part. As with the PLS155, distinct clock input on pin 1 is provided for synchronous operation. Register Preset and Reset are available in 2 banks. Pin F4 and F5 are controlled from the AND array (Product Terms Ps and R8). The remaining 4 registers, F0 - F3, are controlled by the sum terms (from the OR array) PA and RA.

Designs requiring more than 16 states but less than or equal to 64 states are solid candidates for realization with the PLS157. It can be configured as a Moore machine for counter and shifter designs from the flip-flop outputs, or as high speed pulse generators or sequence detectors with the combinational outputs. Mixed solutions are also possible.

(LOGIC TERMS)

(CONTROL TERMS)

PR L

L

D

E

...,_-+-~~+---f~~~~~~~~-1-~+-----+~~1--~-l-b

b

i.<::>-t-~---11---!--~~~~~~~---+~-l----l~--l~~~6

B F (n)
F (n)
Figure 6. PLS157 Architecture

Philips Semiconductors Programmable Logic Devices
Sequencer devices

The PLS159A
By extending the PLS157 arrangement even further, the PLS159A can be derived. Again, maintaining identical input, product terms, Complement array and similar S-State partitioning, the PLS159A also resides in a 20-pin package. The expansion to dual 4-bit banks of flip-flops, at the expense of 2

combinational outputs, enhances the number of available internal states while maintaining product term and pin compatibility. Note that all registers are controlled from the AND array in 2 groups of four.
The PLS159A is an ~!!fill. It readily enters the environment of the 8-bit data operand as well as the bus oriented system.

For enhanced performance, the flip-flop outputs are inverted. To provide positive outputs for shifters and counters, the input variables and state feedback variables can be selectively inverted through an input receiver or the feedback path through the AND gate
array.

(LOGIC TERMS)

(CONTROL TERMS)

E

B

F

I

I

I

t-~~~~~~~~1

To Fcl

a Copies

I

L----------------------~

Figure 7. PLS159A Architecture

Philips Semiconductors Programmable Logic Devices
Sequencer devices

There are three basic members in the 24-pin package family: The PLS167A, the PLS168A, and the PLS179. The PLC42VA12 is discussed elsewhere.
The PLS167A
The PLS167A has 14 logic inputs and six registered outputs (S-R flip-flops). Six additional buried flip-flops reside beside the 48 product term AND array. This device can

support state machine designs of up to 256 states-as two outputs feed back into the AND array, making a total of eight buried registers. There is complete feedback connectivity of the inputs and the state flip-flop outputs to the PLA AND gates. Organizationally it has much more in common with the PLS105A than the aforementioned 20-pin parts. The

asynchronous Preset and the Output Enable are identical to the PLS1OSA.
By having the output latched state variable capability, it provides an automatic buffer for bus based systems. The current state may be presented, fully stable and synchronized to a bus-while the internal buried machine is transitioning to the next state based on current input conditions.

STATE REG.

PR/OE

To
Figure 8. PLS167A

Philips Semiconductors Programmable Logic Devices
Sequencer devices

The PLS168A
This sequencer is a down-scaled version of the PLS1 OSA. Having identical product terms, Complement array, asynchronous PRESET/Output Enable options, and 3-State controls, its primary difference is having 12 inputs compared to the PLS105A's 16 inputs. However, the PLS168A can become a state

machine of up to 1024 states due to internal feed back of its six state registers, plus the feedback of four of the eight output registers. The PLS168A is packaged in a 300mil-wide 24-pin DIP or 28-pin PLCC.
This is also an octal part, providing an 8-bit register to a bus based system. State

registers, interrupt vector synchronizers, counters, shifters, or just about any basic state machine can be generated and 3-State interfaced to a computer bus with a PLS168A. Outputs provided by the positive asserted sense make state transitioning and loading of state variables straightforward.

STATE REG.

PR/OE p

CK To
Figure 9. PLS168A

Philips Semiconductors Programmable Logic Devices
Sequencer devices

The PLS179
The PLS179 is architecturally similar to the PLS 159A. The 3-State enable, number of product terms, flip-flop mode controls, register preload, etc., are all identical to the PLS 159A. The four additional inputs are the dominant differentiating feature for this part as compared to the PLS159A. As with the

PLS159A, the PLS179 Preset and Reset functions are controlled from the AND array in 2 groups of 4 registers each.
The PLS179 is also an Q!;!a! part. Providing the state contents directly to the pin through 3-State buffers allows counters and other sequence generators direct access to an asserted low octal bus. Some design

creativity will generate positive assertion through the pin inverters, for positive driven busses. Additional input pins expand the capability of the part beyond the PLS159A. Input combinations may be presented in a wider format, more fully decoded to the sequencer for faster reaction and less external circuitry than the PLS159A requires.

PO - P31 FC

B .)-L)l>-;-.l]'-~'1'--'1'--'1'---'--'l-----rl4
I I I L'=====::!'(.Jr--~~~~~I
---------------~ 8 Copies
CUC 0 - - - l l > - - - - - - - - - - - _ _ _ J
Figure 10. PLS179 Architecture

nrtnhor 1 QQ'=l

Philips Semiconductors Programmable Logic Devices
Sequencer devices

The PLUS405 The PLUS405 is a functional superset of the PLUS105. It is also much faster. The performance of the PLUS405 has been dramatically improved relative to the PLS105A. Available in two speed versions, the operating frequencies (1111s + lcKo) range from 37 to 45MHz (minimum guaranteed frequency). The clock frequencies, or toggle rate of the flip-flops, are 50MHz and 58.SMHz, respectively. The PLUS405 has 16 more product terms and two more buried state registers than the PLUS105. Equipped with two independent clocks, it is partitionable into two distinct state machines with independent clocks. And, it contains two

independent Complement arrays, allowing full benefits over both machines.
The PLUS405 can be partitioned as one large state machine (16FFs) with 64 available p-terms using one clock and 16 inputs or alternately two state machines (8FFs each) with independent clocks, sharing 64 p-terms with 15 inputs in any combination the user desires. The Complement arrays can be used to generate the "else" transition over each state machine or alternately used as NOR gates. They can be coupled into a latch if needed.
The Asynchronous Preset option of the PLS105/167/168 architectures has been

replaced with a Programmable Initialization feature. Instead of a Preset to all logic "1 "s, the user can customize the Preset/Reset pattern of each individual register. When the INIT pin (Pin 19) is raised to a logic '1 ", all registers are preset/or reset. The clocks are inhibited (locked out) until the INIT signal is taken Low. Note that Pin 19 also controls the OE function. Either Initialization or OE is available, but not both.
A CMOS extension to the PLUS405 is Philips Semiconductors PLC415, which is pin compatible and a functional superset of the PLUS405 architecture.

Philips Semiconductors Programmable Logic Devices
Sequencer devices

PO

P63

CK

07

PLUS405
Circuitry with dashed line is replicated four times. (16 JK flip-flops)

I
I

I

I I 4COPIES

I

I

I

I

F7

I

FO

Figure 11. PLUS405

The Future Is Here Now.
Recent architectural extensions are currently available from Philips Semiconductors. These include the PLC415 and PLC42VA12. These

new "Super Sequencers" are available now for high-end new designs. Please check the data sheet section of this handbook for more

information. See also the CMOS Sequencers section for more design examples using the PLC415 and the PLC42VA 12.

October 1993

fin1

Phillps Semiconductors Programmable Logic Devices
PLS168/168A Primer

Application Note
AN023

INTRODUCTION The PLS168/168A is a bipolar Programmable
Logic Sequencer as shown in Figure 1, which consists of 12 inputs, a 48 product term PLA and 14 R/S flip-flops. Out of the 14 flip-flops, six are buried State Registers (P4-P9), four Output Registers (Fo-F3), and four Dual-purpose Registers (Po-P3), which may be used as Output or State Registers. All flip-flops are positive edge-triggered. They are preset to "1" at power-up, or may be asynchronously set to "1" by an optional PR/OE pin, which may be programmed either as a preset pin or as an Output Enable pin. Additional features includes the Complement Array and diagnostics features.
ARCHITECTURE
As shown in Figure 2, the device is organized as a decoding AND-OR network which drives a set of registers some of which, in tum, feedbacks to the AND/OR decoder while the rest serve as outputs. Outputs Po to P3 may be programmed to feedback to the AND/OR decoder as State Registers and, at the same time, used as outputs. The user now can design a 10-bit state machine without external wiring. The AND/OR array is the classical PLA structure in which the outputs of all the AND gates can be programmed to drive all the OR gates. The schematic diagram of the AND-OR array is shown in Figure 3. This structure provides the user a very structured design methodology which can be automated by CAD tools, such as Philips Semiconductors SNAP software package. The output of the PLA is in the form of sum-of-products which, togetherwith the RS flip-flops, is the ideal structure for implementation of state machines. (Reier to Appendix A for a brief description of synchronous finite state machines.)
Design Tools
State machines may be implemented easily with the assistance of a PLO design software package. The software, such as Philips SNAP package, allows for various methods of design description entry. State machines

may be described using direct H/l table entry, schematic entry, Boolean equations, or state equations. The preferred method is, of course, state equation entry. The syntax for each software package differs but is generally of the form:
WHILE [present state]
IF [input condition] then [new state] with [output]
IF [input condition] then [new state] with [output]
IF [input condition] then [new state] with (output]
Only one input condition should be active at any one time, otherwise two or more product terms trying to force the machine into different states may be active simultaneously. The result would be a state machine in an unexpected state, which would not be a desirable condition. The manual for your software package should be consulted for specific syntax rules and options.
Direct H/L table entry is not recommended for design entry, however looking at a table for verification of a design and for learning how state equations are implemented in a device is useful. SNAP does not provide access to a table from a menu entry. Instead, run the program 'FUSETABLE' from the DOS prompt. ABEL from Data 1/0, provides a program called IFLDOC to display the JEDEC file in a H/L table format. Designs implemented in sequencer devices using JK or SR type flip-flops are easier to interpret in a H/L table format than those using D-type flip-flops.
The following examples illustrate how state equations are implemented in a PLS168 device. Two of them illustrate the functioning of the Complement Array and how it may be used to reduce the number of product terms used in a simple state machine design. The last example shows how only one Complement Array may be used in a state machine design which uses multiple ELSE statements.

A PLS168 H/L table as shown in the data sheet is shown in Table 1. The table is organized according to input and output of the PLA decoding network. The lefthand side of the table represent the inputs to the AND-array, which includes input from input pins and present state information from the feedback buffers which feedback the contents of the State Register. The righthand side of the table represents the output of the OR-array, which drives the State and Output Registers as the next state and output Each column in the lefthand side of the table represents an input buffer, which may be inverting, non-inverting, disconnected or unprogrammed. Each column in the righthand side of the table represents a pair of outputs to the flip-flops, which may be set, reset, disconnected, or unprogrammed. The programming symbols are H, L, -, and 0. (See Figure 4 for details.) For inputs buffers, "H" means that the non-inverting buffer is connected, "L" means that the inverting buffer is connected,"-" means that both inverting and non-inverting buffers are disconnected, and "O" means that both inverting and non-inverting buffers are connected which causes that particular AND-term to be unconditionally Low. On the output side of the table, "H" means that the particular AND-term is connected to the OR-term on the "S" input of the particular flip-flop, "L" means that the AND-term is connected to the "R" side, "-" means that the AND-term is not connected to the flip-flop at all, and "O" means that the
AND-term is connected to both the ·s· and
"R" sides. More details of the symbols and their meanings are shown in Appendix B. Each row in the table represents an AND-term. There are 48 AND-terms in the device. Therefore, there are 48 rows in the table. An example of implementing a transition from one state to another is shown in Figure 4a. The state diagram can be implemented by the PLS168 as shown in Figure 4b. The state diagram is translated into H/L format as shown in Figure 4c. The first column on the lefthand side of the table is for the Complement Array which will be discussed in detail in the next section.

Philips Semiconductors Programmable Logic Devices
PLS168/168A Primer
Ml 11 12
15 17 18 19

Application Note
AN023

(OPTION)

p

E

N

F

47 · · · · · · 40 39 · · · · · · 32 31 · · · · · · 24 23 · · · · · · 16 15 · · · · · · 8

NOTES:

1. All programmed "AND" gate locations are pulled to logic "1 ".

2. All programmed 'OR" gate locations are pulled to logic "O".

3. )) Programmable connection.

Figure 1

7 ······ 0

October 1993

603

Philips Semiconductors Programmable Logic Devices
PLS168/168A Primer

Application Note
AN023

Table 1. PLS168/168A Programming Table

CUSTOMER NAME·----------~ PURCHASE ORDER#_ _ _ _ _ _ _ _ __

PHILIPS DEVICE #

CF (XXXX)

CUSTOMER SYMBOLIZED PART#_ _ _ _ __

TOTAL NUMBER OF PARTS_ _ _ _ _ _ __
PROGRAM TABLE_ _ _ _ _ _ _ _ _ _~ REV _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

DATE_ _ _ _ _ _ _ _ _ _ _ _ _ _~

-------A-ND----1I -----OR-------

INACTIVE

0

I INACTIVE

0

GENERATE

A

PROPAGATE

·

I Cn I

SET RESET

H

No, Fr

L

TRANSPARENT' -

I

NO CHANGE

-

INACTIVE

0

1,P

, H

-~N'T CARE ' ~

L------------

11 ~ I l_____~!!~-----

Imo p·

:ESET

!

PIE

AND

10 9 8I1 6

INPUT(lm)

PRESENT STATE (Po) (Px)

ua 5

2 1 0 9 8 7 6 5 4I3 2 1 0

REMARKS

OPTION PIE)

T

OR

I

I

I

I

I

I

' ' '

' ' '

I
'

10

11

12

13

14

15 16 17 18

' ' ' '

' ' '
I

'
I
' I

19

I

I

20

21

22

23

24

I

25

I

I

I

26

I

I

I

27

I

I

I

28

I

I

29

30

31

32

33

34

35 36

37

38

39

40

41

42

43

44

45 46

47

PIN NO. 18 19 20 21 22 23 2 3 4 5 6 7

w

--' w

a~ J
a:

:E
<z (

~

16 15 14 13 11 10 9 8

October 1993

604

Philips Semiconductors Programmable Logic Devices
PLS 168/168A Primer

121NPUTS
10 REGISTER FEEDBACK

AND/OR DECODER

OUTPUT REGISTERS
STATE REGISTERS

D

Application Note
AN023

Figure 2. The Architecture of PLS168/168A

October 1993

605

Philips Semiconductors Programmable Logic Devices
PLS168/168A Primer

Application Note
AN023

Vee

Vee

ANrD-G-A-TE- - - - - ,

I

I

"-lI
Ni-Cr FUSE

: I

I

I

I

I

I

I

------}

TOOTHER ANO-GATES

------}

TOOTHER AND-GATES

~;-1} r - - - - + - - - + -

r ----- ----------~!
I
------~=P L------

TO INPUTS OF FLIP-FLOPS

OR-GATE

Figure 3. Schematic Diagram of AND-OR Array

October 1993

606

Philips Semiconductors Programmable Logic Devices
PLS168/168A Primer

Application Note
AN023

a. State Diagram Fo

b. Implementation of State Diagram (a) with PLS168

AND

OPTION P/E} OR

INPUT

PRESENT STATE

T NEXT STATE

OUTPUT

sJ1 TERM Cn 11 10 9

6 5 4_13 2 1 0 9 8 I 7 6 5 4T3 2 1 0 9 8 · 7 6 5 4 I 3 2 1 0 3 2 1 0

00 01

-.- -·- -·- -·.- - H L

--

I

----
I

- H LI - - - - -

I

I

- L H·- - - - H - - -
I

PIN

I

I

NO.

18 19 20 21 1 22 23 2 I

3 '4 I

5

6

7

I

I

N

I

'

A

M

E

0
~ ~

I ' ' '
I

I '
I
' '

I

·1& 15 14 13 11 10 9 8 I I

I ' '
I

g

I

::i

I

0

c. PLS168 Programming Table

Figure 4. Implementing State Machine with PLS168

October 1993

607

Philips Semiconductors Programmable Logic Devices
PLS168/168A Primer

Application Note
AN023

Figure 5. Logic Diagram of Complement Array

To implement the third vector "go to state 03 if input is neither 1001 nor 1101", the Complement Array accepts the outputs of the first two AND-terms as inputs. If the input vector is neither 1001 nor 1101, then both terms will be Low, which causes the output of the Complement Array (/C) to be High. A third AND-term is used to AND state 24 and IC together to set the registers to state 03. The State Diagram is translated into SNAP syntax as shown in Figure Sb, where all vectors are in square brackets and the Complement Array is represented by the ELSE statement. The State diagram Figure Sa can also be expressed in the format of a program table as shown in Figure Sc. The complement array may be used to exit from different present states to different next states. It can be used many times in one state machine design as shown in Figures 7a, b, and c where the state diagram is implemented using the SNAP state equation syntax and a H/L format representation.

Complement Array
An additional feature is the Complement Array, which is often used to provide escape vectors in case the state machines get into undefined states during power-up or a timing violation due to asynchronous inputs. A logic diagram of the Complement Array is shown in Figure 5. The output of the Complement Array is normally Low when one or more AND-terms are High. If all of the AND-terms are Low, then the output of the Complement

Array will be High. In this example, if each AND-term is a decoder for a particular state and input combination, and if the circuit gets into an undefined state, none of the AND-terms will be High. Therefore, the output IC will be High, which will then enable the AND-term S which in turn may be used to reset all registers to Low or High as predefined. The state machine thus escapes from being in an undefined state by using the Complement Array and one AND-term.
Without the Complement Array an alternate way of escaping from being in an undefined state is by defining all possible states which are not being defined. This method may require quite a few AND-terms depending on the design. Another application for the Complement Array is illustrated by the following example. As shown in Figure S, when the machine is in state 23, if input vector equals 1001, it will go to next state 24. If the input is 1101, then go to state 25. But if the input is neither 1001 nor 1101, then go to state 03. It takes only two terms to implement the first two transition vectors.

October 1993

608

Philips Semiconductors Programmable Logic Devices
PLS168/168A Primer
(PS)a

Application Note
AN023

a. State Diagram

WHILE[23] IF (1001] THEN [24] WITH [OUT1] IF (1101] THEN (25] WITH [OUT2] ELSE (03] WITH [OUT9]
b. SNAP State Equation Syntax

AND INPUT

PRESENT STATE

NEXT STATE

OPTION~

L OR

OUTPUT

TERM Cl--~~~~~~~~~~~-l-~~~~:....;_~~~~-'~..:.::;~~;.:_..,,__.'::::;::::;::::::":::i.:_~~....-I

a 11 10 9

I7 6 5 4 I3 2 1 0 9 8 I7 6 5 4 I 3 2 1 0 9 8 I7 6 5 4 I3 2 1 Q 3 2 1 Q

1111 AH L L H·- -

L LLH

01

L H L

I 02 03 COMPLEMENT ARRAY 04

.J..o"1
, PRESENT STATE=23(HEX) ,

L LH

111 : '
,

f7LjT

OUT1,=000l~,....lL'-f--+-+---+-t
· OUT2=0010~

05

,

,

NEXT STATE: 24(HEX)·_,,r/-++-J1-+--+-~,-<-- OUTG=1001 ,_,._,...-r-....--t--t

t---"--+-+--+--+-......+--f--1--"'-+-+--+--+

25(HEX UJ

...L ...L '

PIN NO.

1a 1s 20 21·22 23 2 3 ·4 s a 1

'

'

N

03(HEX) 1

1 16 15 14 13 11 10 9 8
' '

A

M E

'
' (') (\f ...... 01
~ ~ ~ ~.

'

' ' '

a".'"a.' a~ . o a.
00 00

'

c. H/L Format

Figure 6. Application of Complement Array

October 1993

609

Philips Semiconductors Programmable Logic Devices
PLS168/168A Primer

Application Note
AN023

a. State Diagram

WHILE[OO] IF (0000] THEN [01] WITH [OUTO] IF [0001] THEN (02] WITH [OUT1) ELSE [3F] WITH (OUT9)
WHILE(01] IF [0010] THEN [03] WITH [OUT2) IF [0011] THEN (04] WITH [OUT3] ELSE [2F] WITH [OUTS]
WHILE[02) IF [0100] THEN (05] WITH [OUT4] IF [0101) THEN [06] WITH [OUT5J ELSE [2F] WITH [OUT7)
b. SNAP State Equation

TERM c

AND INPUT

PRESENT STATE

OPTION:J!'RI~

OR

1 NEXT STATE

OUTPUT

11 10 9 8 O 7 6 5 4 O 3 2 1 0 9 8 0 7 6 5 4 0 3 2 1 0 9 8 0 7 6 5 4 O 3 2 1 0 3 2 1 0

00 A L L L Lo- - - -o- - - - L LoL L L Lo- - - - L LoL L L Ho- - - - L L L L

. -·-- 01 A L L L Ho- - - _o_ - - - L L1L L L L'- - - - L L'L L H Lo- - - - L L L H

02

- - - -

0

-

-

_o_ 0

-

-

I
L L:L

0
L L Lo0

0
- - H H:H H H Ho- - - - H L L H 0

03

0

0

0

0

' 0

' 0

0

0

0

0

04

A

L

L

H

Lo0

-

-

-

-0
0

-

-

-

L LoL L L Ho- - - -

L LoL

L

H

Ho0

-

-

-

L L H L

. H:- 05 A L L H Ho- - - -o0 - - - - L L·L L L Ho- - - - L LoL H L L,- - - - L L H H

06 - - - -o- - - -o- - - - L L0 L L L

- - - H L0 H H H Ho- - - - L H H L

0

0

07

0

I

0

0

0

0

08

A

L H L Lo- -

-

_o_

-

-

-

' L L:L

0
L H L'o- -

-

-

I
L L:L H L Ho- -

- - LHLL

0

0

0

- 09

A L H L Ho- - - - 0 - - - -

0

0

L LoL L H Lo- - - -

L L1L H H Lo0

- - LHLH

. - 10

-

-

- -0 0

-

-

-

-0
0

-

-

-

L L1L

L H Lo- -

-

-

H LoH

H

H

Ho0

-

-

-

L H H H

0

0

0

11

0

0

0

0

0

0

'

I

'

PIN NO.

0

0

18 19 20 21 ·22 23 2 3 O 4 5 6 7

0

0

I
0 16 15 14 13 11 10 9 8
I

I

I

I

N

I

0

I

A

0

I

0

I

M E

"'~

~ "'~~

o ,I ~o

I I 0

0

0

I 0 0

"' "' ~o
0.. 0.. 0.. 0..
00 00

c. PLS168 Programming Table

Figure 7. Applications of Complement Array

October 1993

610

Philips Semiconductors Programmable Logic Devices
PLS 168/168A Primer

Application Note
AN023

6 8 12 16 20 24 28 32 36 40 44 48

10
90

0kr=-r±-.:-:.-:-.i-.---~-~-..-..-.-'.f-~".T.-.--.i-,_:k-:-"1,.t12'.,J->-.j

80 'T

~

701-+--++-+--+-+-~ldlll!Y-~-+--~

60 ~~~~~j~lltti

%

soi--t--t-~.--t--t--t----t--t--t--i

40

.....,..

30~

20 t-t-+--t-+--t--+--+ · 25°C --1
... 0°C
lO t-t-+--t-+--t--+--+ · 75"C -
_L
6 8 12 16 20 24 28 32 36 40 44 48

NUMBER OF TERMS

NUMBER OF TERMS

a. PLS168 Setup Time vs. P-Term Loading

Figure 8

b. PLS168 Setup Time vs. P-Term Loading

CK'
Figure 9. Difference In Propagation Delay Due to Different P-Term Loading

OUTPUT

I

-~

_ _ \.....__

__,~

I OUTPUT UNDETERfllNED

DUE TO METASTABLE

CONDITION OF FLIP-FLOP

Figure 10. Change of lcKO Due to Metastable Condition of Flip-Flop

October 1993

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Philips Semiconductors Programmable Logic Devices
PLS168/168A Primer

Application Note
AN023

Optional Preset/Output Enable
The PR/OE pin provides the user with the option of either using that pin to control the 3-State output buffers of the Output Registers, or have that pin to asynchronously preset all registers to High. The purpose of the preset function is to provide the system a way to set the PLS168 to a known state, all Highs. The output enable function are sometimes used where the state machine is
connected to a bus which is shared by other
output circuits. It is also used during power-up sequence to keep the PLS168 from sending power glitches to other circuits which it drives. By programming the PR/OE pin to control the 3-State output buffers, the preset function is permanently disabled. By programming the PR/OE pin to control the asynchronous preset of the registers, the output buffers are permanently enabled. While using the preset function to asynchronously preset the register, if a rising edge of the clock occurs while the preset input is High, the registers will remain preset. Normal flip-flop operation will resume only after the preset input is Low and the rising edge of the next clock. Setting the registers to a predefined pattern other than all Highs
may be accomplished by using a dedicated
p-term, which is activated by an input pin which will also inhibit all other p-terms which are being used. The inhibiting of other p-terms eliminates the problem of undetermined state of an RS flip-flop caused by having Highs on both R and S inputs.

Diagnostic Features
In debugging a state machine, sometimes it is necessary to know what is the content of the state register. The buried State Register
may be read by applying +1OV on 10, which
will cause the contents of register bits P4 to
Ps. P6 to P9 to be displayed on output pins F2
to F3 and Po and P3 respectively. While the device can handle the +1OV on pin 10, prolonged and continuous use will cause the
chip to heat up since more power is being
dissipated at+ 10V. To facilitate more expedient functional tests, synchronous
preset vectors as described above may be used to set the State Register to different states without having to go through the entire
sequence.
Timing Requirements
Since the PLS168 is intended to be a synchronous finite state machine, the inputs are expected to be synchronous to the clock and set-up and hold time requirements are expected to be met. In general, the set-up time requirement is measured at its worst case as having the entire AND-array connected to the OR-term being measured and there is only one active AND-term to drive the entire line. The set-up time decreases from there as less p-terms are used. This is due to the capacitance of the unused AND-terms being removed from the line. Figure Ba shows the typical set-up time requirement of a PLS168A device. Figure Sb shows the normalized set-up time as a percentage of the worst case, which is with

48 terms connected. In a typical state machine design, some flip-flops will change states more frequently than others. Those that change more frequently will have more p-term loading on its OR gates than those that change states less frequently. The different loadings on the OR-terms cause different delay on the inputs of the flip-flops
as shown in Figure 9. If an input fails to meet
the set-up time specification, it is possible that the resultant of the input change gets to one set of flip-flops before the rising edge of
the clock while it gets to other flip-flops during
or after the clock's rising edge. The result is that some flip-flops have changed states and some have not, or some get into metastable condition as shown in Figure 10. The state machine is now either out of sequence or is in an undefined state. This problem often occurs with asynchronous inputs which is generated totally independent of the clock on
the system. A common remedy for the problem of asynchronous inputs is to use
latches or flip-flops to catch the input and then synchronously feed it to the state machine. This minimizes the problem with the different propagation delays due to different p-term loading. But there is still a finite probability that the external latches or flip-flops will get into metastable condition,
which may be propagated into the state
machine. Nevertheless, the window for the flip-flops in state machine to get into undefined states or metastable condition is narrowed by a great extent.

October 1993

612

Philips Semiconductors Programmable Logic Devices
PLS 168/168A Primer

Application Note
AN023

APPENDIX A
INTRODUCTION TO STATE MACHINE
A slate machine is a synchronous sequential circuit which interprets inputs and generates outputs in accordance with a predetermined logic sequence. It is analogous to running a computer program with a computer. The slate machine, with its sequence coded in

hardware, can run much faster than a computer running the sequence in software. Therefore, It is often used in coniroller applications where speed is important.
Generally, state machines may be classified as Mealy or Moore machines as shown in Figures 1a and 1b. The fundamental difference of the two types are: the output of a Moore machine is a dependent of only the

slate of the memory elements whereas the output of a Mealy machine is a dependent of both the state of the memory elements and the inputs to the slate machine. The figures also show graphic representations of the logic sequence in the form of slate diagram in which the bubbles represent slate vectors, and the arrows represent transitions from present states to next states.

INPUTS

OUTPUTS
OUTPUT DECODER

STa IS PRESENT STATE OUTa IS OUTPUT VECTOR
INa IS INPUT VECTOR
Slb IS NEXT STATE OUlb IS OUTPUT VECTOR

Appendix A·1. Moore Machine Model

INPUTS

OUTPUTS
OUTPUT DECODER

STa IS PRESENT STATE
INa IS INPUT VECTOR OUTa IS OUTPUT VECTOR
Slb IS NEXT STATE

Appendix A·2. Mealy Machine Model

October 1993

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Philips Semiconductors Programmable Logic Devices
PLS 168/168A Primer

Application Note
AN023

APPENDIX B

LOGIC PROGRAMMING
The PLS can be programmed by means of Logic programming equipment.
With Logic programming, the AND/OR gate input connections necessary to implement the desired logic function are coded directly from the State Diagram using the Program Table on the following page.

PRESET/OE-(P/E)
p~ ~=' ~

~
P:1~E
~

In this table, the logic state or action of

OPTION

CODE

OPTION

CODE

control variables C, I, P, N, and F. associated

PRESET

H

L

i i,p ii,p il,p il,p witheachTransitionTermT0,isassigneda
symbol which results in the proper fusing pattern of corresponding link pairs, defined as follows:
"AND" ARRAY- (I), (P)

PROGRAMMING: The PLS168/A has a power-up preset feature. This feature insures that the device will power-up in a known state with all register elements (State and Output Register) at logic High (H). When programming the device it is important to realize this is the initial state of the device. You must provide a next state jump if you do not wish to use all Highs (H) as the present state.

l,P

1,P

1,P

~p

r,p

r,p

r.p

r.p

Tn

[

STATE

I J CODE

l [ INACTIVE1· 2

O j

Tn
STATE l,P

Tn
STATE
ip

Tn
STATE DON'T CARE

"OR" ARRAY - (N), (F)

"iro' "±ID' "±ID' "±ID' ii;1

R

n,l

R

n,t

R

n;1

R

L l ACTION
I j [ INACTIVE1· 3

CODE 0

I

ACTION SET

I I CODE H

I

ACTION RESET

I I CODE L

I I - I ACTION NO CHANGE

CODE

"COMPLEMENT" ARRAY - (C)

G;l: G;l: G;l: G;l:

Tn

Tn

Tn

Tn

ACTION
f Il JJ INACTIVE1· 4

CODE 0

I I I ACTION GENERATE

CODE A

I I · I ACTION PROPAGATE

CODE

ACTION
LL lJ. - J TRANSPARENT

CODE j

NOTES:
1. This is the initial unprogrammed state of all links. 2. Any gate Tn will be unconditionally inhibited if both the true and complement of any input (I or P) are left intact. 3. To prevent simultaneous Set and Reset flip-flop commands, this state is not allowed for N and F link pairs coupled to active gates Tn(see
flip-flop truth tables). 4. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates T0 ·

October 1993

614

Phillps Semiconductors Programmable Logic Products
Alarm Controller

Application Note
AN047

A Programmable Alarm System PLS168
A basic alarm controller can be considered as a black box with several inputs and several outputs {Figure 1). Some inputs are used for detection and others for control. Detect inputs

are driven from a variety of alarm transducers such as reed switches, smoke detectors, pressure mats, etc. An ARM input switches the system into a state which allows detection of the various alarm conditions and a RESET

input is used to reset the system after an alarm has been triggered and dealt with or on re-entering the protected area. Outputs from the system include a sounder, a beacon and status indicators.

CLOCK

CONTROL{ ARM

INPUTS

RESET

ARE

PREATAK

TIMED 1

DETECT INPUTS

TIMED 2 ALARM 1 ALARM2

ALARM3

ALARM3

ALARM

SOUNDER BEACON

CONTROLLER

J--. I
I
I----'

}

ALARM OUTPUTS

STATUS } INDICATOR

Figure 1. Basic Alarm Controller

~a~~:reset/ -~nder
TOST_NULL

timed Hire
timed 2·nre

..TOST_NULL TOST_4 Figure 2. State Diagram for the Alarm Controller

615

I arm·rese~
sounder TOST_NULL

Philips Semiconductors Programmable Logic Products
Alarm Controller

Application Note
AN047

Detect inputs can be divided into timed, untimed, lire and personal attack inputs. Timed circuits allow entry/exit delay circuits for front and rear doors, to delay operation of the alarm for approximately 16 seconds. Untimed circuits cause the alarm to operate immediately when an alarm condition occurs. These would be used to protect unusual means of entry, such as windows. Both the timed and untimed circuits should operate only if the system is armed.
The personal attack circuit is a special case untimed circuit and should operate only when the system is disarmed. The fire-detect circuit is again a special case untimed circuit and should operate regardless of whether the system is armed ornot.
Outputs from the controller drive an external sounder and beacon. After 128 seconds, the sounder should turn off if the alarm has been triggered by either a timed or general untimed circuit. However, when a fire or personal attack triggers the system, the sounder should not turn off until the system is reset and the alarm condition removed.
State Machine Implementation
This design is best implemented as a state machine. The state diagram is derived from the verbal system description. Please note from Figure 2 the controller can be in one of six possible states. Examine the transitions

from ST_NULL as an example. If a personal attack or fire condition occurs while in this state, a transition to ST_ 1 takes place as indicated by the arrows on the diagram. Also at this time the sounder and beacon are activated, thus giving the alarm. If the fire and personal attack conditions have not occurred and the ARM SWITCH is set, then a transition to ST_Otakes place.
Similarly, other arrows on the state diagram represent transitions between other states when specified input conditions occur. Output parameters are shown to the right of the slash line. Where there are no output parameters specified in a transition term, this indicates that no output changes are desired during this transition. That is, an output will hold its present value until told to change.
PLD Implementation
Having defined the desired system operation it is now time to select the required device to implement the desired system function from the PLO Data Manual. In this case, the device selected is the PLS168. Figure 3 shows the pinning information for the alarm controller. A 10-bit counter within the controller produces the entry/exit and sounder turn-off delays since this makes more efficient use of the PLO facilities than implementing the delays as part of the state machine. This counter uses seven internal

registers with feedback and three without. For those registers without feedback, external wiring feeds their outputs back into the device to complete the 20-bit counter. Pins five to ten are used for this purpose. Output T7 also forms part of the counter.
Three other registers form the state registers and are labeled SRO, SR1 and BEACON. State vectors for these registers have to be chosen with care lo ensure that the beacon output is activated at the correct time. Other inputs and outputs are as already discussed. Note that the PR/OE pin is not used. SNAP defaults its use to a register PRESET function. This pin should be tied to ground in the final circuit.
The EON file of SNAP is separated into sections. First, in the @PINLIST section all of the signal names connected directly to the pins and their function is listed. If a signal name is used later in the file and not listed in the @PINLIST section, that signal is
assumed to represent an internal node. The
@PINLIST and @LOGIC EQUATIONS sections of the EON file are shown in Table 1. The remaining state machine portion of the EON file is shown in Table 2. Register SRO halts and clears the counter while the controller is in certain states. This needs to be considered when defining the state vectors.

616

Philips Semiconductors Programmable Logic Products
Alarm Controller

TABLE 1. SNAP EQUATIONS

"----------------------------------------" ALARM COH'l'ROLLBR
"----------------------------------------"
@PDILIST clock 1; arm 1; reset i; peratak i; t81n 1; t91n 1; tl01n 1; alarm3 1; alarm2 1; alarm.1 i;
timed2 1; timedl 1; fire 1;

tlO

o;

t9

o;

ta

o;

t7o

o;

sounder o;

beacon o;

srl

o;

srO

o;

@GROUPS

@TRUTHTABLB

@LOGIC EQUATIONS

nten-bit counter for delayn

tl.s = /tl*/srO; tl.r = tl*/srO + srO; tl. elk = clock;
t2.s = tl*/t2*/sr0; t2.r = tl* t2*/sr0 + srO; t2.clk = clock;
t3.s = tl* t2*/t3*/sr0; t3.r = tl* t2* t3*/sr0 + srO;
t3.clk = clock;
t4.s = tl* t2* t3*/t4*/sr0;
t4.r = tl* t2* t3* t4*/sr0 + srO;
t4.clk = clock;
ts.a= tl* t2* t3* t4*/t5*/sr0; tS.r = tl* t2* t3* t4* tS*/srO + srO; tS.clk =clock;
t6.s = tl* t2* t3* t4* t5*/t6*/sr0;
= t6.r = tl* t2* t3* t4* tS* t6*/sr0 + srO;
t6.clk clock; t7.s = tl* t2* t3* t4* tS* t6*/t7*/sr0; t7.r = tl* t2* t3* t4* tS* t6* t7*/sr0 + srO; t 7. elk = clock;
t7o=t7;
t8.s = tl* t2* t3* t4* tS* t6* t7*/t81n*/sr0;
= ta.r = tl* t2* t3* t4* tS* t6* t7* t81n*/sr0 + srO;
t8.clk clock;
t9.s = tl* t2* t3* t4* tS* t6* t7* t81n*/t9in*/sr0; t9.r = tl* t2* t3* t4* tS* t6* t7* t81n* t91n*/sr0 + srO; t9.clk = clock; tlO.s= tl* t2* t3* t4* tS* t6* t7* t8in* t91n*/tl01n*/sr0;
tlO.r= tl* t2* t3* t4* tS* t6* t7* t81n* t91n* tl01n*/sr0 + srO;
tlO.clk clock;

srO.clk =clock;

srl.clk = clock;

beacon.elk = clock;

sounder.elk = clock;

(EON file continued in Table 2)

617

Application Note
AN047

Philips Semiconductors Programmable Logic Products
Alarm Controller

Application Note
AN047

State Equation Entry
The state equation entry portion of the EON file uses a state-transition language, parameters of which are taken directly from the state diagram. Information is entered into this file in a free format. The only points to remember are that the square brackets should be used throughout to define the state registers and transitions, semicolons should be used to mark the end of vector definition. State vectors can be defined in the state equation entry file as shown in Table 2. State vectors are simply a means of labeling an arrangement of state registers which can be used later to define state transitions. Because we are using the BEACON output register as a state register also and SRO is being used to

halt and clear the 10-bit counter, particular care must be taken in defining the state vectors in this instance.
From the state diagram, the counter must begin counting during states ST_O, ST_2 and ST 3 and it must be cleared during states ST-1, ST_4 and ST_NULL State ST_NULL represents the power-up state of the PLS168 in which all register outputs are at logic one. Thus the inactive state of the counter is defined as being when SRO is at logic one, therefore, SRO must be at this level during states ST 1 and ST 4 and at logic zero
The during other states. alarm beacon is
considered to be active by an active-low

signal and must be activated during states ST 3 and ST_4. Register SR1 must therefore bediosen to ensure mutual exclusivity between state vectors. ·Input and output vectors can be defined in the same manner in terms of input and output label names. In this case, however, the label names are used direcdy. State transitions can now be de~ved directly from the state diagram. ·Entry/exit and sounder tum-off delay times are represented as a decoding of the 10-bit counter states. Thus to get the desired 16 second entry/exit delay. t7 must be decoded and to achieve the 128 second sounder tum-off delay t1 Oin must be decoded.

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Philips Semiconductors Programmable Logic Products
Alarm Controller

TABLE 2. SNAP EQUATIONS

@INPUT VECTORS
@OUTPUT VECTORS
[sounder] srff s on Ob;
= s_off lb;

@STATE VECTORS

[srO, srl, beacon]srff

st null lllb;

st 0

OOlb;

st l

lOlb;

st 2

Ollb;

st 3

OlOb;

st- 4

lOOb;

@TRANSITIONS

while [st_null] if [arm*/fire*/peratak] if [peratak] if [fire)

then [st_O] then [st_4] then [st_4]

with [s_on] with [s_on]

while [st- OJ if [t7*/fire*(arm+reset)] if [/arm*I reset] if [fire]

then then then

[st- l]
[st_null]
- [st 4]

with with

[s_off] [s_on)

while [st- l] if [timedl*/fire] if [timed2*/fire] if [alarml*/fire] if [alarm2*/fire) if [alarm3*/fire] if [/arm*/reset] if [fire]

then then then then then then then

[st_2] [st_2] [st_3] [st_3]
[st- 3)
[st_null]
[st- 4]

with with with with with

[s_on] [s_on) [s_on] [s_off] [s_on]

while [st_2] if [t7*/fire] if [alarml*/fire] if [alarm2*/fire] if [alarm3*/fire] if [/arm*/reset] if [fire]

then [st_3] with [s_on]

then [st_3] with [s_on]

then [st_3] with [s_on]

- then [st 3] with [s_on]
then [st_null] with [s_off]

then [st- 4]

with [s_on]

while [st_3]

if [tlOin*/fire*(arm+reset)) then [st_4]

if [/arm*/reset]

then [st_null]

if [fire]

then [st_4]

with with with

[s_off] [s_off] [s_on]

while [st_4] if [/arm*/reset]

then [st_null] with [s_off]

619

Application Note
AN047

Philips Semiconductors Programmable Logic Products
Alarm Controller

Application Note
AN047

PLS168

.i...11....,.----1-1 CK

+SV ........,....___ _ __,,....,

I

. . . -~---""'-t'
..._......__ _ ___.""'! 0
------""'! 0
.......----~..... a
...................__ _..i.....i 0
'"""'......____~ ov

PR ....,...___ _____,.....,...,
0 ........,.....__ _ ___...,....,
o .....,.......____.............
0 ........,..___ ___.............
0 1-"-'"-----'-.LW<I:........

Figure 3. Pinning Information for the Alarm Controller

+V HC132

~
330n

PLS168 Clock Beacon 13
Sounder 11 Arm Reset Peratak

Fire

TSin

T9in T10in

1K

..,...

T10 T9

TS

Figure 4. Alarm System based on the PLS168

With the system fully defined, simply assemble the design information using SNAP.
Functioning of the device can be verified with the SNAP simulator, which can also be used to check A.C. timings before downloading the pattern to a device programmer.
Programmability
The PLS168 device could now be used as the controller of an alarm system. As it stands, the device assumes that all the alarm

inputs indicate an alarm condition when in the high state, logic one, and that the alarms are activated when the alarm outputs are active low (i.e., at logic zero).
Should an alarm input transducer be used which indicates an alarm condition as a low state, this can be catered for by altering the EON file. For example, consider a smoke detector which outputs logic zero on detection of an alarm condition and assume that this transducer is driving the "fire" input

of the device. By changing all references to 'fire' in the EON file to '/fire' and all instances of '/fire' to 'fire' then the activation of the alarms will occur when logic zero is applied to this input and not when logic one is applied, as in the original case.
Polarity of the output signals cannot be altered as easily, as the device will always power-up with the outputs at logic one. This should not prove to be a problem since the outputs simply drive output transistors and

620

Philips Semiconductors Programmable Logic Products
Alarm Controller

Application Note
AN047

these can be used to produce the correct polarity signal for the beacon and sounder.
System Implementation
Figure 2 shows a typical alarm system based on this device. The system clock is produced by a relaxation oscillator built from 74HC132 Schmitt Triggers. Values of R1 and C1 shown result in a frequency of approximately 4Hz which will provide the desired entry/exit and sounder turn-off delays. These delays can be

modified either by changing the external oscillator circuit or by decoding a different internal counter state. For example, to increase the entry/exit delay change all references to t7 in the EON file to 18. Both normally-closed and normally--0pen loop implementations are shown. Due to the distances involved in an alarm system, the open-loop configuration may cause problems, being driven by the positive supply. to avoid

this problem, input-detect polarity of the open-loop circuit can be changed by altering the EON file.
Status indication can be provided by connecting LEDs as in Figure 5. When the reset button is pressed, any LED being lit will indicate an alarm condition for that input. This will not reset the alarm system unless the arm switch is off.

Figure 5. !;ltatus LEDs Connected to the alarm controller as shown provide status information

621

Phlllps Semiconductors Programmable Logic Devices
High-speed 12-bit tracking A/D converter using PLS179

Application Note
AN028

INTRODUCTION
The general technique underlying the operation of this AID converter is illustrated by the functional block diagram in Figure 1.
The system consists of a DIA converter, a
comparator circuit, and digital logic circuitry. The digital logic circuitry outputs a digital value which is converted to analog by the DIA converter.
The comparator senses when the output is greater or less than the input and causes the digital circuit to decrement or increment its digital output respectively. The initial conversion is completed in 13 dock cydes. If tracking mode is used, the AID converter then tracks the input voltage as it changes by incrementing or decrementing 1-LSB per clock. The tracking function makes it possible to make an AID conversion in one dock cycle if the input changes less than the value of
1-LSB per clock period. The conversion may
be halted and the digital output, as well as the converted analog output from DAC, will hold their output constant indefinitely. This feature works well as sample-and-hold since its output voltage will not decay over time whereas the output of an analog sample/hold will decay due to charge leakages.
In order to avoid the violation of setup time by the output of the comparator, its output is latched. There is a built-in 2-phase clock in U2 which may be used to drive the logic circuitry and the latch of the comparator (see Philips Semiconductors NE5105 data sheet for details on output latches of voltage comparators).
The analog input voltage may be sampled and held by an analog sample/hold circuit to keep the input to the ADC from changing. The DONE output may be used to control the sample-and-hold if needed.
This paper discusses only the digital circuit which contains the SAR and the Up/Down

Counter. The analog circuits are not within the scope of this paper.
SAR
Two PLS179s are connected together to form a 12-bit shift register and up/down counter. The schematic diagram of the AID converter is shown in Figure 2. U2 contains bits 0 to 4 and U1 contains Bits 5 to 11. Interconnects are made as shown in the diagram. The digital outputto the DAC is in natural binary format (e.g. 0000 0000 0000 equal zero, and 111111111111 isfullscaleor4095).Afterthe nST input becomes 0, at the rising edge of the next clock, the SAR is initialized to half-scale (1000 0000 0000) and the DONE flip-flop is reset to output 0 which causes the open-collector output nDone_OC to become high impedance.
The digital output is converted by the DAC and is compared to the analog input voltage by the comparator. If the digital output is greater than the analog input, the SAR shifts the 1 to next MSB on the right. The content of the SAR becomes (0100 0000 0000). If the digital output is still greater than the input, the SAR shifts right one bit again. The content of the SAR then becomes (0010 0000 0000). The shifting of 1 to the next MSB in equivalent to reducing by half the value of the bit under consideration. If the output is still too large, the SAR reduces it by half again by shifting to the right one more time. The SAR keeps shifting to the right until the digital output is less than the input. When the output is less than the input, the SAR adds one bit to the next MSB while keeping all the higher order bits unchanged. For example, if the current output is 0001 0000 0000 and the output is less than the input, the SAR adds one bit to the right at the next clock. The output becomes 0001 1000 0000. The output

is again compared to the input. If the addition of that one bit is too much, it will be shifted to the right until the output becomes less than the input. When that happens, that SAR will again add one bit to the right. The algorithm of the SAR may be summarized as the following: If the output is greater than the input, shift to the right; otherwise add one bit to the right. This process continues until all 12 bits have been operated on. The last bit (Bit 0) is always changed from 0 to 1, which is used as the condition to set DONE to 1 which, in turn, sets open-collector output, /nDONE_OC, to 0.
UP/DOWN COUNTER
After DONE becomes 1, if /nST and nHOLD are 1 and nTRACK is 0, the SAR turns into a 12-bit up/down counter. If the analog input voltage increases, the counter will increment by 1 at every clock until it matches the input. If the input decreases, the counter will decrement by 1. When nHOLD becomes 0, the counter is inhibited and the output is held indefinitely. The counters consist of 12 toggle flip-flops and 2 p-terms per flip-flop for directional control. The counter will operate only after the approximation cycle is completed and DONE is 1.
Since the nST and nHOLD inputs may be asynchronous with the clock, in order to minimize the possibilities of having a metastable condition from happening, these inputs close-up are latched by flip-flops nSTART of U1 and nHLD of U2 respectively. Once they are latched, subsequent operation begins at the rising-edge of the next clock. The output of the comparator may be latched to prevent setup time violation. (Philips Semiconductors NE5105 is a high-speed comparator with an output latch. External latch may be used with other comparators.)

October 1993

ST._ _ __....
TRJICK---""'
=---""'

1-----DONE

nomcoc 12-BITSAR AND

1-----

UP/DOWN COUNTER

CLOCK 1

1 - - - · CLOCK 2

ANALOG INPUT

~---,.r 12-BIT DATA OUTPUT

12-BITDAC Figure 1. Functional Block Diagram of 12-Bit High-Speed AID Converter
622

Philips Semiconductors Programmable Logic Devices
High-speed 12-bit tracking AID converter using PLS 179

Application Note
AN028

ST - - - - ,

2
'~
t--!

vJ1

4

START [2i

PLS179

~
~ h

18_

17

16

15

6

7

8

9

U1

;_1u0_

+Vee"

R
·v-::::i::::-

10

vI1

ve

21 Jl[D PLS179
:.I

6

20

19

18

17

16

15
1

U2

14 11
5 4
t!---i

23

...... UOlff8lC

DONE MSB

CLOCK2 CLOCK1

\ LATCH ENABLE
~

CLOCK 1

COMPARATOR

MSB

LSB

o
V1N (ANALOG INPUT)

12-BIT DAC

12-BIT >DIGITAL
OUTPUT
LSB

Figure 2. Schematic Diagram of 12-Bit High-Speed A/D Converter

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High~speed 12-bit tracking AID converter using PLS179

Application Note
AN028

CLOCKS
U2 generates an optional 2-phase clock which may be used to control the latch of the comparator. The two clocks are basically 180° out of phase and CLOCK2 has an additional 2Sns propagation delay behind CLOCK1. CLOCK2 is used to drive the clock-inputs of the PLS 179 devices.
The clock frequency is controlled by R and C. Those who want to use the built-in clock should experiment with RC time constants for the best value. It is recommended that the capacitance should be less than 1000pF for best results.
DONE AND nDONE QC
The output DONE is reseito 0 when nST is 0. It remains 0 until the approximation cycle is completed. After the least significant bit becomes 1, the DONE bit becomes 1 at the next clock. It remains 1 until it is reset again by input nST.
The nDONE_OC output is configured to emulate an open-collector output. The output is programmed to have a logic 0. When DONE is O, the 3-State output buffer is set to

Hi-Z condition. As soon as DONE equals 1, the 3-State buffer is enabled and nDONE_OC becomes 0.
In the initial phase of AID conversion, 13 clock cycles are required. It is essential that the input voltage to the comparator remains unchanged while the SAR is converting. It may be necessary to have a sample/hold at the front end. The DONE output may be used to control the analog sampleillold circuit.
INPUT LATCHES
Flip-flop nSTART and 2 p-terms in U1 are configured as a non-inverting D flip-flop. The input, nST, and the output nSTART have the same polarities. Flip-flop nHLD and 2 p-terms in U2 also form a non-inverting D flip-flop. The output nHLD and the input nHOLD have the same polarities.
AMAZE IMPLEMENTATION
The implementation of the logic circuit using ABEL is as shown in the appendices. Two files (ADCS1 .ABL and ADCS2.ABL) are generated for each PLS179s. State machine

and Boolean equation design entries are used for both files.
The SAR circuit is designed as a state machine and the up/down counter, input latches, 2-phase clocks and the open-collector output are implemented by using Boolean equations. BITO to 4 are described in ADCS2 and BITS to 11 are in ADCS1. Toggle flip-flops are implemented by the JK flip-flops (when .J=.K). In order to combine two different design entries into one device, pin attribute assignment 'ISTYPE REG_JK' must be given to keep output registers type consistency (ABEL will default state machine to D-F/F).
Test vectors are also supplied with each design file to simulate SAR and up/down counter functions. Note that U2 will not start functioning until BITS and U 1 becomes 1 and ripples into U2. When nST becomes O,it clears all the state registers and next conversion cycle begins. The files are then compiled and simulated to produce the JEDEC files (ADCS1 .JED and ADCS2.JED) and the simulation files (ADCS 1.SIM and ADCS2.SIM).

r- CLOCK 1 ~

tpo "2Sns

CLOCK2

H

: ~ 1w 1 CLOCK PERIOD

srlLJ: I

,.....+-l~~~~~~~~~~~~~~~~-1-~+--~~~~~~~

I

I

I

I

SUCCESSIVE APPROXIMATION

DATA VALID

BITSG-11

DONE.
I
111¥I
DORCoC

: I
I I I I I '-~~~~~~~-
Figure 3. Timing Diagram of Successive Approximation Cycle

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Philips Semiconductors Programmable Logic Devices
High-speed 12-bit tracking AID converter using PLS179

APPENDIX A: ABEL DESIGN FILE OF U1

MODULE TITLE

ADCSl; 'SAR AND UPDOWN COUNTER FOR THE BIT5 .. BIT11 PHILIPS SEMICONDUCTORS'

DECLARATIONS ADCSl DEVICE 'Fl79';

"Signal names preceding with a 'n' means 'active low'.

"INPUTS

CLOCK,nST,COMPARE,nHLD,nTRACK

PIN 1,2,3,4,5;

BIT4,BIT3,BIT2,BIT1,BITO,DONE

PIN 6,7,8,9,10,11;

"OUTPUTS BIT5,BIT6,BIT7,BIT8,BIT9 BITlO,BITll,nSTART

PIN 15,16,17,18,19 ISTYPE 'REG_JK';

PIN 20,21,22

ISTYPE 'REG_JK';

H,L,CK,X = l, 0, .C., .X.;

"GREATER means digital output is greater than analog input,
"LESS means digital output is less than analog inputs, ...
GREATER = COMPARE&!BIT4&!BIT3&!BIT2&!BITl&!BIT0&nST&!DONE;
LESS = !COMPARE&!BIT4&!BIT3&!BIT2&!BITl&!BITO&nST&!DONE;

SREG = [nSTART,BITll,BITl0,BIT9,BIT8,BIT7,BIT6,BIT5];

BEGIN !NIT HALF SCALE ST2048 STl024 ST512 ST256 STl28 ST64 ST32

[X, X,X,X, X,X,X,X ]; [O, 0, 0, 0, 0,0,0,0 ]; [l, l,0,0, 0,0,0,0 ]; [l, l, 0, 0, 0,0,0,0 ]; [l, X, l, 0, 0,0,0,0 ]; [l, X,X,l, 0,0,0,0 ];
[l, x,x,x, 1,0,0,0 ];
(1, X,X,X, X, l, 0, 0 ]; [l, X,X,X, X,X,l,O ]; [l, X,X,X, X,X,X,l );

AD1024 AD512 AD256 AD128 AD64 AD32 AD16

[X, X,l,X, X,X,X,X ];
[X, X,X,l, x,x,x,x ); [X, x,x,x, l,X,X,X ];
[X, x,x,x, X,l,X,X ); [X, x,x,x, X,X,l,X ]; [X, x,x,x, X,X,X,l ]; [l, X,X,X, x,x,x,x );

SH1024 SH512 SH256 SH128 SH64 SH32 SH16

[X, 0, l,X, X,X,X,X ];
[X, X,0,1, x,x,x,x );
[X, X,X,O, l,X,X,X ];
[X, x,x,x, 0,1,X,X ];
[X, X,X,X, X,O,l,X ];
[X, X,X,X, X,X,0,1 );
[X, x,x,x, X,X,X,O );

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High-speed 12-bit tracking AID converter using PLS 179

APPENDIX A: ABEL DESIGN FILE OF U1 (Continued)
EQUATIONS

SREG.CLK = CLOCK;

"Non-Inverting Input Latch: nSTART nST nSTART.J = !nST; nSTART.K = nST;

"UPDOWN COUNTER"
BITS.J = !nSTART.Q & !nTRACK & DONE & nHLD& COMPARE &
!BITO & !BITl & !BIT2 & !BIT3 & !BIT4 # !nSTART.Q ' !nTRACK ' DONE ' nHLD& !COMPARE ' BITO & BITl & BIT2 & BIT3 & BIT4;

BITS.K

!nSTART.Q & !nTRACK & DONE & nHLD& COMPARE & !BITO & !BITl & !BIT2 & !BIT3 & !BIT4 # !nSTART.Q & !nTRACK & DONE & nHLD& !COMPARE & BITO & BITl & BIT2 & BIT3 & BIT4;

BIT6.J

!nSTART.Q ' !nTRACK & DONE ' nHLD ' COMPARE ' !BITO & !BITl & !BIT2 & !BIT3 & !BIT4 & BITS.Q # !nSTART.Q & !nTRACK & DONE & nHLD & !COMPARE & BITO & BITl & BIT2 & BIT3 & BIT4 & !BITS.Q;

BIT6.K

!nSTART.Q & !nTRACK & DONE & nHLD & COMPARE & !BITO & !BITl & !BIT2 & !BIT3 & !BIT4 & BITS.Q # !nSTART.Q & !nTRACK & DONE & nHLD & !COMPARE & BITO & BITl & BIT2 & BIT3 & BIT4 & !BITS.Q;

BIT7.J

!nSTART .Q ' !nTRACK & DONE ' nHLD & COMPARE & !BITO & !BITl & !BIT2 & !BIT3 & !BIT4 & BITS.Q & BIT6.Q # !nSTART.Q & !nTRACK & DONE & nHLD & !COMPARE & BITO & BITl & BIT2 & BIT3 & BIT4 & !BITS.Q & !BIT6.Q;

BIT7 .K

!nSTART.Q & !nTRACK & DONE & nHLD & COMPARE & !BITO & !BITl & !BIT2 & !BIT3 & !BIT4 & BITS.Q & BIT6.Q # !nSTART.Q & !nTRACK & DONE & nHLD & !COMPARE & BITO & BITl & BIT2 & BIT3 & BIT4 & !BITS.Q & !BIT6.Q;

BITS.J BITS.K

!nSTART.Q & !nTRACK & DONE & nHLD & COMPARE & !BITO & !BITl & !BIT2 & !BIT3 & !BIT4 & BITS.Q & BIT6.Q & BIT7.Q
#
!nSTART.Q & !nTRACK & DONE & nHLD & !COMPARE & BITO & BITl & BIT2 & BIT3 & BIT4 & !BITS.Q & !BIT6.Q & !BIT7.Q;
!nSTART.Q & !nTRACK & DONE & nHLD & COMPARE & !BITO & !BITl & !BIT2 & !BIT3 & !BIT4 & BITS.Q & BIT6.Q & BIT7.Q # !nSTART.Q & !nTRACK & DONE & nHLD & !COMPARE & BITO & BITl & BIT2 & BIT3 & BIT4 & !BITS.Q & !BIT6.Q & !BIT7.Q;

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High-speed 12-bit tracking AID converter using PLS179

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AN028

APPENDIX A: ABEL DESIGN FILE OF U1 (Continued)

BIT9.J =

!nSTART.Q & !nTRACK & DONE & nBLD & COMPARE & !BITO& !BITl& !BIT2& !BIT3& !BIT4& BITS.Q& BIT6.Q& BIT7.Q& BIT8.Q # !nSTAR.T.Q & !nTRACK & DONE & nBLD & !COMPARE & BITO & BITl& BIT2& BIT3& BIT4& !BITS.Q& !BIT6.Q& !BIT7.Q& !BIT8.Q;

BIT9.K =

!nSTART.Q & !nTRACK & DONE & nHLD & COMPARE & !BITO& !BITl& !BIT2& !BIT3& !BIT4& BITS.Q& BIT6.Q& BIT7.Q& BIT8.Q # !nSTART.Q & !nTRACK & DONE & nBLD & !COMPARE & BITO & BITl& BIT2& BIT3& BIT4& !BITS.Q& !BIT6.Q& !BIT7.Q& !BIT8.Q;

BITlO.J = !nSTART.Q & !nTRACK & DONE & nHLD & COMPARE &
!BITO& !BITl& !BIT2& !BIT3& !BIT4& BITS.Q& BIT6.Q& BIT7.Q& BIT8.Q& BIT9.Q
# !nSTART.Q & !nTRACK & DONE & nHLD & !COMPARE & BITO& BITl& BIT2& BIT3& BIT4& !BITS.Q& !BIT6.Q& !BIT7.Q& !BIT8.Q& !BIT9.Q;

BITlO.K = !nSTART.Q & !nTRACK & DONE & nHLD & COMPARE &
!BITO& !BITl& !BIT2& !BIT3& !BIT4& BITS.Q& BIT6.Q& BIT7.Q& BIT8.Q& BIT9.Q # !nSTART.Q & !nTRACK & DONE & nHLD & !COMPARE & BITO& BITl& BIT2& BIT3& BIT4& !BITS.Q& !BIT6.Q& !BIT7.Q& !BIT8.Q& !BIT9.Q;

BITll.J = !nSTART.Q & !nTRACK & DONE & nHLD & COMPARE & !BITO& !BITl& !BIT2& !BIT3& !BIT4& BITS.Q& BIT6.Q& BIT7.Q& BIT8.Q& BIT9.Q& BITlO.Q # !nSTART.Q & !nTRACK & DONE & nHLD & !COMPARE & BITO& BITl& BIT2& BIT3& BIT4& !BITS.Q& !BIT6.Q& !BIT7.Q& !BIT8.Q& !BIT9.Q& !BITlO.Q;
BITll.K = !nSTART.Q & !nTRACK & DONE & nHLD & COMPARE &
!BITO& !BITl& !BIT2& !BIT3& !BIT4& BITS.Q& BIT6.Q& BIT7.Q& BIT8.Q& BIT9.Q& BITlO.Q # !nSTART.Q ' !nTRACK & DONE & nHLD & !COMPARE & BITO& BITl& BIT2& BIT3& BIT4& !BITS.Q& !BIT6.Q& !BIT7.Q& !BITS.Q& !BIT9.Q& !BITlO.Q;

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High-speed 12-bit tracking AID converter using PLS 179
APPENDIX A: ABEL DESIGN FILE OF U1 (Continued)
STATE_DIAGRAM SREG;
STATE BEGIN: if !nST then INIT;
STATE INIT: if nST then HALFSCALE;
STATE ST2048: if GREATER then SH1024 if LESS then AD1024;
STATE ST1024: if GREATER then SH512 if LESS then AD512;
STATE ST512: if GREATER then SH256 if LESS then AD256;
STATE ST256: if GREATER then SH128 if LESS then AD128;
STATE ST128: if GREATER then SH64 if LESS then AD64;
STATE ST64: if GREATER then SH32 if LESS then AD32;
STATE ST32: if GREATER then SH16 if LESS then AD16;

Application Note
AN028

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High-speed 12-bit tracking AID converter using PLS179

Application Note
AN028

APPENDIX A: ABEL DESIGN FILE OF U1 (Continued)
TEST_VECTORS ([nST,nBLD,nTRACK,BIT4,BIT3,BIT2,BITl,BITO,DOllE,CLOCK,COMPAREJ - [nSTART,BITll,BIT10,BIT9,BIT8,BIT7,BIT6,BIT5J)
[1,l,l,0,0,0,0,0,0,0 'OJ -> [l,l,1,1,1,l,l,lJ; "l power-on reset [l,l,l,0,0,0,0,0,0,CK,OJ -> [l,l,l,1,1,1,l,lJ; "2 [l,l,l,0,0,0,0,0,0,CK,OJ -> [l,1,1,1,l,l,l,lJ; "3 [0,l,l,0,0,0,0,0,0,CK,OJ -> [0,0,0,0,0,0,0,0J; "4 nST resets outputs to Os [0, 1, 1, 0, 0, 0, 0, 0, O,CK, OJ -> [0,0,0,0,0,0,0,0J; "5 [0,1,1,0,0,0,0,0,0,CK,OJ -> [0,0,0,0,0,0,0,0]; "6 [1,1,1,0,0,0,0,0,0,CK,OJ -> [1,1,0,0,0,0,0,0J; "7 State machine goes to HALFSACLE [l,l,l,0,0,0,0,0,0,CK,lJ -> [1,0,1,0,0,0,0,0J; "8 and SAR begins [l,l,l,0,0,0,0,0,0,CK,lJ -> [l,0,0,1,0,0,0,0J; "9 [l, 1, 1, 0, 0, 0, 0, 0, O,CK, lJ -> [1,0,0,0,1,0,0,0J; "10
(1, 1, l, 0, 0, 0, 0, 0, O,CK, lJ -> [l,0,0,0,0,1,0,0J; "11 [l,l,1,0,0,0,0,0,0,CK,OJ -> [1,0,0,0,0,l,l,OJ; "12 [l,l,l,O,O,O,O,O,O,CK,0J -> [1,0,0,0,0,l,l,lJ; "13 [ l, 1, 1, 0, 0, 0, 0, 0, 0, CK, lJ -> [l,0,0,0,0,1,1,0J; "14 End of SAR of bit5-ll [l,l,l,l,0,0,0,0,0,CK,lJ -> [l,0,0,0,0,1,1,0J; "15 Outputs keep unchanqe [l, 1, 1, 0, 1, 0, 0, 0, O,CK, lJ -> [l,0,0,0,0,1,1,0J; "16 [1, 1, l, 0, 1, 1, 0, 0, 0, CK, 0J -> [l,0,0,0,0,1,l,OJ; "17 [1, 1, 1, 0, 1, 0, 1, 0, 0, CK, 0J -> [l,0,0,0,0,1,1,0J; "18 [1,1,l,0,l,0,l,l,0,CK,OJ -> [1, 0, 0, 0, 0, 1, 1, OJ; "19 [l, 1, 1, O, 1, 1, 1, 1, l,CK, OJ -> (1,0,0,0,0,l,1,0J; "20 End of SAR of bit0-4
[1,l,0,1,1,1,1,l,l,CK,lJ -> [1,0,0,0,0,1,1,0J; "21 Tracking (up/down counter) started [l,1,0,1,1,1,1,l,1,CK,OJ -> [1,0,0,0,0,1,1,lJ; "22 up [1,1,0,1,1,1,1,l,l,CK,OJ -> [l,0,0,0,1,0,0,0J; "23 up [1,1,0,1,l,l,1,0,l,CK,OJ -> [l,0,0,0,1,0,0,0J; "24 unchange [l,l,0,1,l,1,1,0,1,CK,0J -> [l,O,O,O,l,0,0,0J; "25 unchange [l,l,O,l,l,l,1,0,1,CK,OJ -> [1,0,0,0,1,0,0,0J; "26 unchanqe [1,1,0,1,l,1,l,1,l,CK,OJ -> [1,0,0,0,1,0,0,1]; "27 up [1,l,0,0,0,0,0,0,1,CK,lJ -> [1,0,0,0,1,0,0,0J; "28 down [1,1,0,0,0,0,0,0,l,CK,lJ -> [1,0,0,0,0,l,l,lJ; "29 down [1,1,0,1,1,l,1,1,l,CK,OJ -> [1, 0, 0, 0, l, 0, 0, OJ; "30 up
[1, 1, 0, 1, 1, 1, 1, 1, l,CK, OJ -> [1,0,0,0,1,0,0,lJ; "31 up [1, 1, 0, 1, 1, 1, 1, 1, l,CK, OJ -> [1,0,0,0,1,0,1,0J; "32 up
[1,l,0,l,1,1,1,l,l,CK,OJ -> [1, o, 0, 0, 1, 0, 1, lJ; "33 up
[l,l,0,1,1,l,1,l,l,CK,OJ -> [l,0,0,0,1,1,0,0J; "34 up [1,1,0,1,1,1,1,l,l,CK,OJ -> [1, 0, 0, 0, 1, 1, 0, lJ; "35 up [l,0,0,1,1,l,l,l,l,CK,OJ -> (1,0,0,0,1,l,0,lJ; "36 nHLD goes LOW, hold the output value (1, 0, 0, 0, 0, 0, 0, 0, l,CK, lJ -> [1,0,0,0,l,l,O,lJ; "37 (1, 0, 0, 1, 1, 1, 1, 1,1,CK, OJ -> [l,0,0,0,1,1,0,lJ; "38 [l,0,0,1,1,1,1,l,l,CK,lJ -> [1,0,0,0,1,1,0,lJ; "39 [O, 1, 1, 0, 0, 0, 0, 0, O,CK, OJ -> [0,0,0,0,0,0,0,0); "40 Next conversion cycle begins
[1, 1, l, 0, 0, 0, 0, 0, O,CK, OJ -> [l,1,0,0,0,0,0,0J; "41 HALFSACLE [l, 1, 1, 0, 0, 0, 0, 0, 0,CK, lJ -> [l,0,1,0,0,0,0,0J; "42 SAR begins [l, 1, 1, 0, 0, 0, 0, 0, O,CK, OJ -> [l,0,1,1,0,0,0,0J; "43
END ADCSl

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Philips Semiconductors Programmable Logic Devices
High-speed 12-bit tracking A/D converter using PLS 179

APPENDIX B: ABEL DESIGN FILE OF U2

MODULE ADCS2; TITLE 'SAR AND UPDOWN COUNTER FOR THE BITO .. BIT4
PHILIPS SEMICONDUCTORS'

DECLARATIONS ADCS2 DEVICE 'Fl79';

"INPUTS CLOCK,nSTART,COMPARE,nHOLD,nTRACK BITS,RC,nDONE_OC

PIN 1,2,3,4,5; PIN 6,10,23;

"OUTPUTS CLOCK1,CLOCK2 DONE,BITO,BIT1,BIT2 BIT3,BIT4,nHLD

PIN 11,14; PIN 15,16,17,18 ISTYPE 'REG_JK'; PIN 19,20,21 ISTYPE 'REG_JK';

H,L,CK,X = 1,0, .c., .X.;

GREATER = COMPARE; "IF DIGITAL OUTPUT IS GREATER THAN ANALOG INPUT.

LESS

!COMPARE; "IF DIGITAL OUTPUT IS LESS THAN ANALOG INPUT.

SREG = [BIT4,BIT3,BIT2,BIT1,BITO,DONEJ;

BEGIN INIT ST16 STS ST4 ST2 STl

[X, X,X,X,X, XJ; [O, 0, 0, 0, 0, OJ; [l, 0, 0, 0, 0, OJ; [X, 1,0,0,0, OJ; [X, X, l, 0, 0, OJ; [X, x,x, 1, 0, OJ; [X, X,X,X,l, OJ;

ADS AD4 AD2 ADl IEND
SHS SH4 SH2 SHl SHO

[X, l,X,X,X, XJ; [X, X,l,X,X, XJ; [X, X,X,l,X, XJ; [X, X,X,X,l, XJ; [X, x,x,x,x, lJ;
[O, l,X,X,X, XJ; [X, 0, l,X,X, XJ; [X, X,0,1,X, XJ; [X, X,X,O, l, XJ; [X, x,x,x,o, lJ;

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High-speed 12-bit tracking AID converter using PLS 179

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AN028

APPENDIX 8: ABEL DESIGN FILE OF U2 (Continued)
EQUATIONS SREG.CU: = CLOCK; nHLD.CU: = CLOCK;

"Non-Inverting Input Latch: nHLD nHLD.J = !nHOLD; nHLD.K = nHOLD;

nHOLD"

"UP /DOWN COUNTER" BITO.J = (nSTART & !nTRACK & !DONE.Q & nHLD ); BITO.K = (nSTART & !nTRACK & !DONE.Q & nHLD );
BITl.J = (nSTART & rnTRACK & !DONE.Q & nHLD & !COMPARE & !BITO.Q #nSTART & !nTRACK & !DONE.Q & nHLD & COMPARE & BITO.Q);
BITl.K = (nSTART & !nTRACK & !DONE.Q & nHLD & !COMPARE & !BITO.Q #nSTART & !nTRACK & !DONE.Q & nHLD & COMPARE & BITO.Q);

BIT2.J BIT2.K

(nSTART & !nTRACK 'DONE.Q & nHLD & !COMPARE & !BITO .Q & !BITl.Q #nSTART & !nTRACK & !DONE.Q & nHLD & COMPARE & BITO.Q & BITl.Q); (nSTART & !nTRACK & !DONE.Q & nHLD & !COMPARE & !BITO.Q & !BITl.Q #nSTART & !nTRACK & !DONE.Q & nHLD & COMPARE & BITO.Q & BITl.Q);

BIT3.J BIT3.K BIT4.J BIT4 .K

(nSTART & !nTRACK & !DONE.Q & nHLD & !COMPARE & 'BITO .Q & !BITl.Q & !BIT2.Q #nSTART & !nTRACK & !DONE.Q & nHLD & COMPARE & BITO.Q & BITl.Q & BIT2.Q); (nSTART & !nTRACK & !DONE.Q & nHLD & !COMPARE & !BITO.Q & !BITl.Q & !BIT2.Q #nSTART & !nTRACK & !DONE.Q & nHLD & COMPARE & BITO.Q & BITl.Q & BIT2.Q);

(nSTART& #nSTART& (nSTART& #nSTART&

!nTRACK& !nTRACK& !nTRACK& !nTRACK&

!DONE.Q& nHLD !DONE.Q& nHLD !DONE.Q& nHLD !DONE.Q& nHLD

&!COMPARE &COMPARE &!COMPARE &COMPARE

&!BITO .Q & !BITl.Q &!BIT2.Q & !BIT3.Q &BITO.Q &BITl.Q &BIT2.Q & BIT3.Q); &!BITO .Q &!BITl.Q &!BIT2.Q & !BIT3.Q &BITO.Q &BITl.Q &BIT2.Q & BIT3.Q);

nDONE QC = O; nDONE QC.OE !DONE.Q;

RC = O; RC.OE =RC;

CLOCKl RC; CLOCK2 !CLOCKl;

STATE_DIAGRAM SREG;
STATE BEGIN: if !nSTART then INIT;
STATE INIT: if BITS then ST16
STATE ST16: if GREATER then SH8 if LESS then ADS;
STATE ST8: if GREATER then SH4 if LESS then AD4;
STATE ST4: i f GREATER then SH2 if LESS then AD2;
STATE ST2: if GREATER then SHl if LESS then ADl;
STATE STl: if GREATER then SHO else IEND;

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High-speed 12-bit tracking AID converter using PLS 179

Application Note
AN028

APPENDIX B: ABEL DESIGN FILE OF U2 (Continued)
TEST_VECTORS
([nSTART,nHOLD,nTRACK,BIT5,COMPARE,CLOCK] -> [BIT4,BIT3,BIT2,BITl,BITO,DONE,nHLD]);
[1,1,1,0,0,0 l -> [l,l,l,1,1,1,l]; "1 Power_on reset [1,1,1,0,0,CK] -> [l,l,l,1,1,1,1]; "2 [0,1,1,0,0,CKJ -> [0,0,0,0,0,0,l]; "3 nSTART clears all tbe output registers [1,1,1,0,1,CKJ -> [O, 0, 0, 0, 0, O, l]; "4 [l,1,1,0,l,CKJ -> [O, 0, 0, 0, 0, O, l]; "5 [1,1,1,0,1,CKJ -> [0,0,0,0,0,0,l]; "6 (1, l, l, 1, 1, CK] -> [l,0,0,0,0,0,l]; "7 bit5=1 ripples into U2 to start SAR of bit0-4 [l,1,1,0,l,CK] -> [0,1,0,0,0,0,l]; "8 [l, l, l, O, l,CKJ -> [O, 0, l, 0, 0, 0, l]; "9 [1,1,1,0,0,CK] -> [0,0,1,1,0,0,l]; "10
(1, l, l, 0, 0,CK] -> [0,0,1,1,1,0,1]; "11 (1, l, l, 0, 0,CK] -> [O, O, l, 1, 1, 1, l]; "12 [l, l, l, 0, 0, CK] -> [0,0,1,1,l,l,l]; "13 end of SAR of bit0-4 [1,1,1,0,l,CK] -> [0,0,1,1,1,1,l]; "14 [l, l, l, O, l,CK] -> [0,0,1,1,l,l,l]; "15 [l, l, l, 0, l,CK] -> [0,0,1,1,1,1,1]; "16 [l, 1, 0, 0, 1, CK] -> [0,0,1,1,0,l,l]; "17 Tracking started and counts down (1, l, 0, 0, 1, CK] -> [O, 0, 1, 0, 1, l, l]; "18 down [l, 1, 0, 0, O,CK] -> [0,0,1,1,0,l,l]; "19 up [l, l, 0, 0, 0,CK] -> [0, O, l, l, l, l, l]; "20 up
[l, l, 0, 0, O,CKJ -> [O,l,0,0,0,1,1]; "21 up [l, 1, 0, 0, 1, CK] -> [0,0,1,1,1,1,1]; "22 down [l, l, 0, O, l,CK] -> [O, 0, 1, 1, 0, 1, l]; "23 down [l, 0, 0, 0, 0,CK] -> [O,O,l,l,1,1,0]; "24 nHOLD becomes 0, hold [l, 0, 0, 0, O,CK] -> [0,0,1,1,1,1,0J; "25 [l, 0, O, O, l,CK] -> [0,0,1,1,1,1,0]; "26 [O, 1, 1, 0, 0,CK] -> [0,0,0,0,0,0,1]; "27 Next conversion cycle begins [O, 1, 1, 0, 0, CK] -> (0, 0, 0, 0, 0, 0, l]; "28 [l, l, l, 0, 1, CK] -> [0,0,0,0,0,0,1]; "29 [l, 1, 1, 1, l, CK] -> [l,0,0,0,0,0,l]; "30
[1, l, 1, 1, 1, CK] -> [0,1,0,0,0,0,1]; "31 [l, l, l, 1, l, CK] -> [0,0,1,0,0,0,l]; "32 [1, l, l, 1, 1, CK] -> [0,0,0,1,0,0,1]; "33
END ADCS2
H

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Phillps Semiconductors Products
Interrupt Handler

Product specification
AN048

Interrupt Handler - PLS179
As an example of designing a microprocessor family part, consider Figure 1, which depicts an interrupt handler. In particular, note that interrupt inputs will be latched into an 8-bit register. This in turn will be encoded to a 3-bit vector which may be appropriately enabled and applied to the microbus. Figure 1 shows the eight flip-flops as having J-K and ID inputs which will be generated with a PLS179 by switching the flip-flop control. Appropriate control signals for the various transactions might be as follows: 1. CLOCK - the system synchronous time
base.
2. Interrupt Enable - when asserted high from the microprocessor, allows interrupts to be generated to the microprocessor.
3. Interrupt - a strobe or level defined to indicate a pending interrupt and a valid encoded vector.
4. Interrupt Acknowledge - a response

signal from the microprocessor which may be used to enable the 3-bit vector onto the bus. As well, it may initiate clearing the currently asserted interrupt latch.
5. /INTO-llNT7 - eight possible interrupt request signals which must be asserted low and held there until service for that device has occurred.
6. Reset - this is a system override signal which will clear all flip-flops during initial operation.
Basic Operation Initially, the part should be reset by asserting the RESET pin high, asynchronously. Then, when interrupts are enabled, the ID-inputs to the 8 flip-flops will be synchronously scanning for interrupt inputs (asserted low). This will put a nonzero value into the eight bit register which will generate an interrupt output, combinationally through the Complement array. In parallel, a 3-bit encoded vector will be applied on the VECO, VEC1, VEC2 lines.

Asserted high logic will be assumed for the vector. Presumably, a microprocessor will interrupt this, transfer control to a service routine and clear the interrupt. The clear will be accomplished by disabling interrupts and strobing the vector value back into the PLS179, using the IACK signal. Disabling the interrupts will put the registers into J-K mode. J is tied to zero and K is decoded from the specifically strobed vector. Therefore, synchronous clear of the high priority bit is done. Interrupts are then re-enabled and the process continues.
The PLS179 solution offers room for user alteration. For example, the IACK condition could be redefined as a combination of the ZBO IOREQ and M1 signals, or any specific splitting of internal signals could be easily done. The design could fit into a PLS159A, but there would be less room for variation for specific users exact needs. Figure 3 shows the pinlist for the handler. Figure 4 gives the corresponding design file.

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Philips Semiconductors Products
Interrupt Handler

RESET INTENA (make D FFS] nNTENA (make J-K FFS]
AN10 KLEARll
nNTt KLEAR1

nNTO nNTt nNT2 nNT3 nNT4 nNTS nNT& ANT7

nNT2 KLEAR2

nNT3 KLEAR3

nNT4 KLEAR4

nNTS KL EARS

nNT& KLEAR&

nNT1

D

KLEAR7

LA = LB = JNTENA.nNT

KLEARS KLEAR& KLEAR7

Figure 1. Interrupt Handler

Product specification
AN048

INT VEC2

ANO
INt
ANO nNt IN2 nNO
nNt nN2 IN3 nNO nNt nN2 nN3 IN4
nNO
AN1 nN2 nN3 nN4 INS nNO
nNt nN2 nN3 nN4
nNs IN&

nNO

nNt

nN2 nN3

- 1 - \ c J f i l_ __ J

nN4

nNs nN& IN7

VECO VECt VEC2

Figure 2. Encoder Logic Diagram

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Philips Semiconductors Products
Interrupt Handler

CLK llCLK ENA 21IO RESET llil :IACK 41I2
51I3 61I4 7II5 BII6 !llI7 INTERUPT [lOIBO VECO [lllBl [121GND
I I

__\

/

VCCl24] B3123] VEC2 1'7122] INT7N 1'6121] INT6N 1'5120] INT5N F411!1] INT4N F3118] INTJN 1'2117] INT2N Flll6J INUH 1'0115] INTON B2114] VECl
OE_lll] OTB
I I

Figure 3. Interrupt Handler Pin Ust

Product specification
AN048

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Philips Semiconductors Products
Interrupt Handler

@PINLIST

OTE

I;

IACK

I·

RESET

I;

ENA

I·

CLK

I;

VEC2

B;

INT7N

B;

INT6N

B;

INT SN

B·

INT4N

B;

INT3N

B;

INT2N

B;

INTlN

B;

INT ON

B;

VECl

B;

VECO

B;

INTERUPT

O;

@LOGIC EQUATIONS

"Encoder Equations" CPTl INTO*INTl*INT2*/INT3; CPT2 INTO*INTl*INT2*INT3*INT4*/INTS; CPT3 INTO*INTl*INT2*INT3*INT4*INTS*/INT6; CPT4 INTO*INTl*INT2*INT3*INT4*INTS*INT6*/INT7; VECO (INTO*/INTl+CPTl+CPT2+cPT4); VECl (INTO*INTl*/INT2+cPTl+CPT3+cPT4); VEC2 = (INTO*INTl*INT2*INT3*/INT4+cPT2+cPT3+CPT4); VECO . oe ENA; VECl. oe ENA; VEC2.oe ENA;

C = /(/INTO+/INTl+/INT2+/INT3+/INT4+/INTS+/INT6+/INT7); INTERUPT = C; INTERUPT.oe = ENA;

"Decoder Equations"
KLEARO = /VEC2*/VECl*/VECO*IACK; "DECODE VECTOR 0" KLEARl = /VEC2*/VECl*VECO*IACK; "DECODE VECTOR l" KLEAR2 /VEC2*VECl*/VECO*IACK ; "DECODE VECTOR 2" KLEAR3 /VEC2*VECl*VECO*IACK ; "DECODE VECTOR 3" KLEAR4 VEC2*/VECl*/VECO*IACK; "DECODE VECTOR 4" KLEARS VEC2*/VECl*VECO*IACK "DECODE VECTOR 5" KLEAR6 VEC2*VECl*/VECO*IACK "DECODE VECTOR 6" KLEAR7 VEC2*VECl*VECO*IACK "DECODE VECTOR 7"

"Register equations" INTO.J=inOj; INTO.K=KLEARO+inOk; INTL J=inlj; INTl.K=KLEARl+inlk; INT2 . J=in2 j; INT2.K=KLEAR2+in2k; INT3. J=in3 j; INT3.K=KLEAR3+1n3k;

INT4 .J=1n4j; INT4.K=KLEAR4+1n4k; INTS.J=inSj; INTS.K=KLEARS+inSk; INT6. J=in6j; INT6.K=KLEAR6+in6k; INT7 .J=in7j; INT7.K=KLEAR7+in7k;

"Register RESET equations" INTO.rst=RESET; INTl. rst=RESET; INT2 . rst=RESET; INT3 . rst=RESET;

INT4.rst=RESET; INTS.rst=RESET; INT6.rst=RESET; INT7.rst=RESET;

Figure 4. Interrupt Handler Design File

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Product specification
AN048

Philips Semiconductors Programmable Logic Devices
PLUS405-55 - the ideal high speed interface

Application Note
AN034

INTRODUCTION
Philips Semiconductors PLUS405-55 is ideal for high performance microprocessor interfacing applications. Being a programmable integrated circuit, it adapts to nearly any bus or microprocessor protocol. The PLUS405-55 can make state machines, counters, and shifters running at speeds of 55 megahertz. The architecture of the PLUS405-55 combines a powerful programmable logic array with 16 JK flip-flops to form a programmable part superior to any comparable PAL part.
WHAT IS INTERFACING?
Interfacing is the translation of digital signals from one target device to another (see Figure 1). Each target device has their own unique signal behavior, and may not be directly connected to each other. Correct connection occurs with the use of a flexible interface. For instance, today's chip set integrated circuits connect a microprocessor to its memory and 1/0 devices. The signals presented by the microprocessor are not the specific /GAS and /RAS needed by the memory. Nor are the microprocessor signals the correct chip enables to attach to the UAR/T or graphics controller. Forming the translated signals which are appropriate for the memories. UAR/T's and other controllers is the job of the interface chips. Unfortunately, there are not off-the-shelf interface parts for all applications. That is where programmable parts excel.
With this information, we can ask: what are the qualities of an ideal interface part?
An ideal interface part must have sufficient logic inside to make correctly any logic translation needed. Because almost every interface is between two target devices which use separate clocks, conventional PAL parts are not adequate. This includes the popular 22V10 and most other registered PAL parts. To reconcile that an interface may exist between two target parts using different clocks, the interface must be able to synchronize signals from either or both target devices. So, an ideal interface must be clockable from at least two different clocks.
An ideal interface part must have enough flip-flops inside to capture data or control information from the target parts, and to re-synchronize control signals. This suggests it needs at least 16 flip-flops because the interface might receive 8 from either target device.
To support the use of the 16 flip-flops as handshaking flip-flops, a typical number of

logic AND gates is about 4 gates per flip-flop. This number of gates can be less if the type of flip-flop is a JK rather than a D flip-flop.
An ideal interface must be as fast - if not faster - than the fastest target devices it must interface. This requirement is sometimes misunderstood. Most microprocessor parts have a clock input which is the fastest signal present at the outside world. Very few signals coming from the microprocessor are as fast or faster than the clock because they are usually made from flip-flop circuits inside the microprocessor.
In the past, many designers believed that
interface PAL parts had to be twice as fast as
the system clock. This was because either the system clock was operating at twice the crystal frequency or the PAL part had to compensate for the fact that some events occur on rising clock edges and other events happen on falling clock edges. This misconception should be reexamined. What is needed is an interface part which can respond to both edges of the basic clock rate, as the interface dictates.
Finally, the ideal interface must be electrically compatible with both devices that must communicate. This is almost always either CMOS or TTL and today's technologies usually support a standard TTL interface.
THE PLUS405·55 ... THE IDEAL INTERFACE!
To meet the needs of the ideal interface, Philips Semiconductors designed the PLUS405-{;5 (see Figure 2). The 405 is fast enough to respond to microprocessor clocks in excess of 50MHz, contains 16 JK flip-flops and a programmable logic array to control the flip-flops. It accepts two clock sources and permits the internal flip-flops to be grouped in one of two standard ways. The PLUS405-{;5 handles simple data synchronization or complex bus handshaking between two target devices, within a single part. It is widely supported by Philips Semiconductors SNAP as well as third-party design tools.
Let's look inside the PLUS405 to see how it works. First, there are 15 input pins, each supplying a signal or its complement, to the main AND array of the 405. There is an additional input pin which can optionally bring in a clock. There are 8 output pins which are directly tied to specific flip-flop outputs (labeled FO to F7). This is the fastest flip-flop configuration possible. It should be noted that the clock to Q time delay (tcKa). measured from the 405's pins. is 8 nanoseconds (max).

This means that signals can get into and out of the PLUS405-55 very fast.
The choice of flip-flops was the JK flip-flop. For building counters, JKs require only one gate per bit of additional logic. For building shift registers inside. no gates are required except that all connections use gates, so it uses a small number to connect the shift register.
For making state machines, the number of gates per flip-flop is up to the application. There is no design restriction with programmable AND gates, which can be assigned as needed to any OR gates. This is superior to the ordinary PAL approach or even the 22V10 approach where each OR gate permanently connects to specific AND gates. AND gate outputs are shared as needed and there is no limit on how many OR gates may be driven from a single AND term. JK flip-flops are superior to D flip-flops for all state machine applications, because they do not need as much external logic to control their behavior.
At this point. we see that the PLUS405-55 combines two superior elements. Namely, JK flip-flops for making state machines and a programmable logic array (PLA) for forming logic expressions. However, there are still more features which the PLUS405-{;5 includes. There is a special pin for tri-state control of the 8 output pins or alternately it can initialization the 405. When used to initialize, the pin can applies any value to the asynchronous set or preset of each flip-flop. Initialization is to any state chosen.
The internal flip-flop connection in the 405 is also critical. Flip-flops are first grouped into two catPgories - 8 internal flip-flops and 8 output flip-flops. The internal flip-flops do not directly access the output pins and the output flip-flops do not feedback. To form state machines inside the 405, the internal flip-flops are best used. This doesn't mean that the · output flip-flops can't be used, but rather that their use with feedback requires external connection. This is seldom necessary.
Another important flip-flop grouping is inside the 405. Four output flip-flops (FO-F3) link with their clock inputs to four internal flip-flops. The other four output flip-flops similarly link with four other internal flip-flops. This permits two separate state machines to be built. One state machine uses 4 internal flip-flops and four output flip-flops on one clock and four other internal flip-flops linked to their four output flip-flops on another clock. Alternately, the can all be linked together to a common clock. or by an external inverter, one

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637

Philips Semiconductors Programmable Logic Devices
PLUS405-55- the ideal high speed interface

Application Note
AN034

state machine can operate on the clock while the other one operates on the clock's complement.
Almost hidden from view in Figure 2 are two additional OR gates which do not drive any flip-flops. These two OR gates are inverted and ledback to the input of the AND logic array. The two inverted OR gates (i.e.. NOR gates) are called complement arrays. They are used to save AND gates when state transitions are complicated. Luckily, the design software - SNAP and SLICE automatically use these gates to save the designer from having to use them. The complement arrays also permit automatic homing to known states. if a power transient accidentally puts a state machine into an undefined state.
PERFORMANCE
As mentioned previously, the clock to Q time delay is 8 nanoseconds maximum. That is only one part of the performance equation. The flip-flop speed is:
tsETUP + tcKa

Passing signals through the PLA section of the PLUS405 (the complement array) will add additional time delay as follows:
lsETUP = 10 nsec
lcKo = 8 nsec
toELAY = 8 nsec
Without the complement array, the IMAX is 55.6MHz found as the inverse of 18 nanoseconds. This is because the specification includes a single signal pass through the PLA as part of the flip-flop setup time. Viewed from the outside, this makes sense because there is no way to get a signal to the flip-flop without entering the PLA. With the complement array, IMAX is the inverse of 26 nanoseconds, found by adding the loELAY term to the IMAX expression. This sets IMAX with the complement array at 38.SMHz. An additional pass through the complement array is never needed, so the PLUS405--55 will never be slower than 38MHz. The additional complement array is included in case two distinct state machines are built, where each needs one.
The PLUS405-55 includes a PLA which has 64 AND gates in it. This permits an average

of 4 AND gates per flip-flop, but this many are seldom needed, because the JK flip-flops are so efficient. Because the AND gate outputs are shared as needed, redundant terms are never used. There are additional buffers to do the asynchronous flip-flop control, and each JK flip-flop includes its own OR gates.
DESIGN SUPPORT
Designers need tools which can capture the design, compile it to a fusemap and download commercially available programmers. Philips Semiconductors supports the PLUS405-55 with SNAP design software (Figure 3). This software runs on personal computers and permits designs to be formulated with Boolean logic equations, state equations or schematics. SNAP, the full-featured product, includes advanced simulation capability found only in Field Programmable Gate Array (FPGA) or ASIC design software.
SNAP includes a simulator with back annotation of time delays to accurately model the PLUS405-55 as well as Philips Semiconductors full PLD product line. Additional support for the PLUS405-55 can be found in third-party design tools.

When a flip-flop is put into a circuit with logic driving it. the logic adds delay which slows the circuit down. For a flip-flop with extra logic. that logic delay is included in the performance equation as follows:

IMAX

1

tsETUP + toELAY + lcKO

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Philips Semiconductors Programmable Logic Devices
PLUS405-55 - the ideal high speed interface

Application Note
AN034

AN EXAMPLE OF INTERFACING WITH THE PLUS405-55

TARGET SYSTEM
'

DATA CONTROL
DATA CONTROL

INTERFACE

DATA CONTROL
DATA CONTROL

TARGET SYSTEM
2

CLOCK1

Figura 1. Dlgltal Interfacing

CLOCK2

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Philips Semiconductors Programmable Logic Devices
PLUS405-55 - the ideal high speed interface

Application Note
AN034

~DETAILS

NOTE: Denotes a programmable fuse location.
October 1993

Figure 2. Philips Semiconductors PLUS405-55 640

. __ ...___ ,,
DETAILD

Philips Semiconductors Programmable Logic Devices
PLUS405-55-the ideal high speed interface

Application Note
AN034

SNAP Brv818 Copyright 1990 PHILIPS SEMICONDUCTORS All rights reserved

Waveforms

Abel2Snap

Equations

Minimizer

MacSel

NetWave

NetConv

Project DDF

22:08:22

DPI
Use cursor keys to select module Use function. keys to enter conunand l:HELP 2:RUN 3:PROJECT 4:STATUS 5:SETUP 6:SAVE 7:DOS 8:EDIT 9:PRINT lO:EXIT
Figure 3. SNAP Shell

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641

Philips Semiconductors Programmable Logic Devices
Single chip multiprocessor arbiter

Application Note
AN07

INTRODUCTION

ARBITER STRUCTURE

Priority b processors are lower in priority than

In multiprocessor environments there is

Within a multiprocessor system, two general the "A's" and may only be granted system

considerable savings to be made through

classes of processors can be recognized:

control when no "A" requests are pending. "b"

sharing system resources. If each processor Priority A and Priority b. Priority A processors processors usually perfonn background

must support its own bus structure, 1/0

have the highest request priority and must

tasks. Within the Priority b group, further

devices, and bulk storage medium, system cost could be very high. In the configuration

only compete with other Priority A processors priority ordering exists such that each "b"

for bus control. The arbiter must issue "A"

processor has a fixed priority position.

I·

shown in Figure 1, all processors share a common communication bus, and a number of system resources.
Since every processor must use the common system bus to communicate with its peripherals, a priority structure that resolves simultaneous processor bus requests into a single bus grant must be integrated into the system. In addition to making request-grant transactions, transient bus contention due to grant switching must be removed by inserting precise guard band times between bus grants.
Philips Semiconductors Programmable Logic Sequencer provides a convenient and cost effective means for implementing a

grants in a manner that prevents any high priority "A" processor from locking out another Priority A processor. To enable this, the Priority A rules implemented here use a Last Granted Lowest Priority (LGLP) ring structure. After an "A" processor has completed a bus-related task, its next arbitrated request priority will be lowest in the "A· request group. The previously second highest priority "A" processor will then become highest priority requester. The net effect of the "round robin" exchange is that every Priority A processor will have a tum at being highest priority processor. Priority A processors are typically ones that perfonn real-time operations or vital system tasks.

Plumber1, Pearce2, and Hojberg3 present asynchronous techniques of arbiter implementation. These methods all have hard-wired priority rules and imprecise guard band times during grant switching. As pointed out by Hojberg, a synchronous state machine can be configured as a Mealy-type controller to provide not only precise guard band times and programmable priority rules, but also programmable input/output polarity. The state machine in Figure 2 is made from a control PROM array and an edge-triggered latch. The "A" and "b" requests and the machine's present state are used by the control PROM to determine the next "A" and "b" grants and the next state.

synchronous arbiter to perform these tasks

within a single chip.

CHANNEL A

SYSTEM ARBITER

CHANNELB

90

r1

91

GLOBAL
RAM

MAG STORAGE

MAPPED 1/0
DEVICES

Figure 1. Multiprocessor Structure

SYSTEM CLOCK

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Philips Semiconductors Programmable Logic Devices
Single chip multiprocessor arbiter

Application Note
ANO?

SYSTEM OPERATION
Two machine states can be identified by inspection: a wait state and a grant state. The state machine enters a grant state as a response to a system request on either RN or rN. The machine will remain in this state with a single grant line asserted as long as the request remains asserted. Upon releasing the request line, the machine will pass through a single wait state before considering other pending requests. This provides a single state guard band time. The requests received must meet the set-up requirement of the edge-triggered latch after propagating through the control PROM. If these time considerations do not fit within a given multiprocessor structure, an input latch may be added such that the RN and rN lines are clocked through the latch by the system clock, thereby removing asynchronous set-up time considerations. On the basis of a state machine approach, two techniques of implementation are feasible: 1) using an architecturally advanced single IC controller, the PLS, and, 2) a traditional PROM/LATCH configuration.

NEXT A

Ro

GRANT

Go

R,

A GRANTS G,

!

NEXTb

'

RN

GRANT

GN

ro
"

CONTROL PROM

NEXT

bGRANTS

90 g,

'N

STATE

gN

SYSTEM CLOCK PRESENT STATE
a. A and b service requests (RN, ·Nl plus the present state determine, through the control PROM, the next state and the next grant outputs (GN, gN)·

SYSTEM CLOCK Ro R1 ro
"

b. Requests R0, R,, r0 , and r1 are asserted low in the same clock sample period. The priority rules that determine the order in which the grants are issued and the shaded guard-band areas are programmed into the control PROM. Note that the A and b request lines and the present state input to the PROM must have a set-up time equal or greater than the latch set-up time plus the PROM access time.
Figure 2. Arbiter Constructed from a Mealy-Type State Machine

October 1993

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Philips Semiconductors Programmable Logic Devices
Single chip multiprocessor arbiter

Application Note
AN07

PR/OE
SYSTEM CLOCK
115
lo

------
CONTROL
PROM
24x48x28 CAPROM

--,
I
l'7 Fu

PRESENT STATE

L

----

'..J

a. PLS Single Chip System

TRANSITION TERM

OPTION (PIE)

1

OUTPUT TERM

· m NO.

C

INPUT VARIABLE Om)

';s· i.iTii" 12[1,"T"iii e a 1 & s "4 r:i""i"

1

0

PRESENT STATE (Po)
s · 3·2

NEXT STATE (Na)

OUTPUT FUNCTION (Fn)

s 4 3 zT"j"T'jj" 7'"i.,....s-·r a 2 1 o

0

1

2
::i

1

I

I I

I

I: I I I I I I I I I I I I 1·1 11 I I I I I I I I I I I I I I I I I I I I I I I

b. PLS Standard Program Table

CK

s

t

0

t

0

t

1

t

1

R

Q

0

a

1

0

0

1

1 Undefine~

NOTE: (i) denotes positive - k transition. s - R- 1 Is an Illegal inpu1 condition.
c. Transition Table of Clocked SIR Fllp·Flop

Fi ure3.

PLS ARBITER IMPLEMENTATION A five Priority 'A" and three Priority "b" arbiter
will be constructed such that all grant outputs will be asserted low for grants and all request inputs will be asserted low for system requests.
Brief PLS Description
The PLS block diagram shown in Figure 3(a) consists of a control PLA and 14 clocked SIR Hip-flops. The control PLA is actually an AND-OR logic array that functions as a Content Addressable PROM. The PLA is organized as 48 words of 28 bits with 16 external input lines, and six internal inputs fed back from the State Register. The 28 PLA

outputs drive the S/R inputs of the six-bit State Register and eight-bit Output Register. Note that the state feedback path is made inside the PLS.
IN and present state inputs, Ps, represent 222 possible input codes; 48 of these codes may be mapped in the PLA to provide a 14 bit register control word. As shown in Figure 3(b) each input code may be specified by assigning to the variables either Low "L", High "H", or Don't Care"-" logic states. If any input code falls logically outside the programmed codes, the PLA asserts a Low on all its 28 internal outputs, thereby issuing a ·no change" command to the R/S flip-flops.

This is an important architectural feature because it requires that only state or output transition terms be programmed. Looping terms that change neither state nor output need not be programmed in the PLS, owing to the functional characteristics of SIR flip-flops tabulated in Figure 3(c). An example of this is shown in Figure 4.
The SIR inputs of both state and output registers are specified by using PLA outputs ("AND" functions of request inputs and present state) in the program table of Figure 3(c).

October 1993

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Philips Semiconductors Programmable Logic Devices
Single chip multiprocessor arbiter

Application Note
ANO?

The corresponding next state of each bit will be set to Ofor "L", 1 for "H", and No Change for"-". The PLS's PR/OE line may be assigned either Asynchronous Preset or Output Enable functions, via a user programmable option.
The entire function is integrated into a single 28-pin package designated as PLUS105.

State Algorithm
Figure 5(a) displays the circular state form and all possible state transitions of the LGLP priority structure. Hex states 3F, 3E, 3D, 3C, and 38 are arbiter wait states W0-4. In these states, processor "A" and "b" requests are monitored. Figure 5(b) illustrates a typical grant to processor A1 in hex state 07. As long as A1 asserts its request line low, the next state will be 0716 and the next output will remain with G1 asserted low and all the other grant outputs asserted high. Since no change in state or grant output results from this transition, no PLA resources are required.
As soon as processor A1 returns its request line, R1, to 1, a state transition is made to 3D, and an output transition is made to set all grant outputs to 1. Since processor A1 was the last to be granted system resources, it will now have the lowest A level request priority (LGLP). In wait state W2, the highest priority processor will be A2, second A3, third A4, and fourth A0. To maintain the LGLP rule, grant transitions must follow the state rule GN-> W(N+ll· and wait states, WM, must set their "A" priorities so that processor AM is highest priority. Priority decreases as one proceeds clockwise around the state ring to the lowest priority processor, A(m-1)·
When no "A" requests are pending; "b" requests may be granted. To avoid upsetting the LGLP priority rule, a "b" grant must leave and return to the same wait state. Since the "b" priority structure is the same regardless of the wait state, only a single set of "b" transition terms are required.

NOTE: TNfFN =Inputs/outputs. The PLS requires that only two out of the three transition terms be programmed.
Figure 4. PLS State and Output Transitions

For example, a grant transition to g2 (Hex 20-25) can be issued only if there are no "A", "b0", or "bi" requests pending. Given the binary wait state code 111 XXX, where "X's" represent Don't Cares, a request code of
o1111111 will transfer the arbiter to the grant
state g2 from any of the wait states, W0-4.
It is important to realize that in making this transition, the lower 3-State bits will not be changed-they provide the wait state return address. When r2 returns high, 1XXXXXXX, a transition back to the previously exited wait state is made by forcing a "1" in the three most significant state bits and leaving the lower 3-State bits unchanged.
All output and state bits are initially preset to "1" through the use of the optional preset function. Grant output lines are only forced low when transitions are made to grant states and are returned to "1" when jumping back to a wait state.
The complete arbiter circuit diagram is shown in Figure 6a. The SNAP equations are shown in Figure 7.

PROM/LATCH IMPLEMENTATION
The same five "A" processor and three "b" processor arbiter can be implemented with discrete PROM's and Latches using the same state diagrams for the PLS, except that now looping transition terms must be programmed. Coding of all state and output transitions requires programming of two memory fields: the "A" request PROM's (2KX6) and the "b" request PROM (64 x 3). The complete circuit diagram is shown in Figure 6(b).
The "A" request PROM's determine the next machine state (Na-5) at all times, except when there are no "A" requests pending and there is a "b" request, or if the machine is presently in a "b" grant state. In these cases, the "b" request PROM controls the machine's next state.
The grant control lines are decoded from the next state lines and latched in two quad output latches. This PROM/LATCH organization is shown in Figure 6a.

October 1993

645

Philips Semiconductors Programmable Logic Devices
Single chip multiprocessor arbiter

Table 1. Design Alternatives for the Priority Arbiter

PARAMETER

SEQUENCER

PROM/LATCH

Parts count PCB space

1 IC .84in2

·191C's 7.92in2

Power

.65W

2.85W

Voltage

+5V

+5V

SUMMARY
As can be seen from the circuit diagrams, the PLS can offer significant advantages over discrete MSI arrays in the design of state· machines. The tradeoff in both design alternatives for the Priority Arbiter is shown in Table 1. Clearly, the PLS approach uses fewer parts, with savings in PC board space and power requirementS.
REFERENCES
1. W.W. Plumber: "Asynchronous Arbiters·; IEEE Transactions on Computers, January 1972, pp. 37-42.

2. R.C. Pearce, J.A. Field, and W.D. Little: "Asynchronous Arbiter Module"; IEEE Transactions on Computers, September 1975, pp. 931-933.
3. K. Soe Hojberg: "An Asynchronous Arbiter Resolves Resource Allocation Conflicts on a Random Priority Basis"; Computer Design, August 1977, pp. 120-123.
4. K. Soe Hojberg: "One-Step Programmable Arbiter for Multiprocessors"; Computer Design, April 1978, pp. 154-158.

Application Note
AN07

October 1993

646

Philips Semiconductors Programmable logic Devices
Single chip multiprocessor arbiter

Application Nole
AN07

TyplCAL IBAtMIDQN DBM
12 r1 l'O Rt "3 A:! Rt Ila
..

txxxxxxx
W0-4

\,1_1"...'.1).~.D./

I rz /Ro
11111111

b. Figure 5. Arbiter Stale Transition Diagram

October 1993

647

Philips Semiconductors Programmable Logic Devices
Single chip multiprocessor arbiter

PRESET SYSTEM CLOCK

J
17 p "7

I&

f&

Is

Fs

14 PLUS105 F4 '3 PLS F3

12

F2

11

F1

lo CK Fo

a.

A1
A& 256x4
As A4 "b" A3 R~~~T
A2
A,
Ao
CE

Application Note
ANO?
NOTE: ALL RANDOM LOGIC MUST BE SCHOTTKY +SP

A1 CE

041----------+-+-+-+------+-----'""---!-~

'~~--1 A& "A" 0:!1----------+-_.__+------+-----'""---!-~

1~~--1 A REQUEST ~>---------+---+------~--~~__,___,

S PROMs O

A1

1

·~~-~As 2Kx4

As
,~~---IA4
A3
·~~-~ A2

04
03~+------------------+----
~ 01 ~+------------------+-~

A1
l~'-'L----:..Ao-"----'

October 1993

SYSTEM C L O C K - - - - - - - - - - - '
b. Figure 6. Arbiter Circuit Diagram Summary
648

Philips Semiconductors Programmable Logic Devices
Single chip multiprocessor arbiter

Application Note
ANO?

"---------------------------------------------" Single Chip Multiprocessor Arbiter AN?
"---------------------------------------------"
@PINLIST

CLOCK I; RB2 I; RBl I; RBO I; RA4 I; RA3 I; RA2 I; RAl I; RAO I;

PRESET I; OB2 O; OBl O; OBO O; OA4 O; OA3 O; OA2 O; OAl O; CAO O;

@GROUl.>S
@TRUTHTABLE @LOGIC EQUATIONS
OBO.CLK = CLOCK; OBl.CLK = CLOCK; OB2.CLK = CLOCK; OAO.CLK = CLOCK; OAl.CLK = CLOCK; OA2.CLK = CLOCK; OA3.CLK = CLOCK; OA4.CLK = CLOCK; FFO.CLK = CLOCK; FFl.CLK = CLOCK; FF2.CLK = CLOCK; FF3.CLK = CLOCK; FF4.CLK = CLOCK; FFS.CLK = CLOCK;

"Flip-Flops are SET when PRESET is HIGH"

OBO.SET OBl.SET OB2.SET CAO.SET OAl.SET OA2.SET OA3.SET OA4.SET FFO.SET FFl.SET FF2.SET FF3.SET FF4.SET FFS.SET

/PRESET; /PRESET; /PRESET; /PRESET; /PRESET; /PRESET; /PRESET; /PRESET; /PRESET; /PRESET; /PRESET; /PRESET; /PRESET; /PRESET;

@INPUT VECTORS

I I CLOCK l(CLK RB2 21!1 RBl 3(I6 RBO 4(IS RA4 SII4 RA3 6II3 RA2 7(I2 RAl 8 (Il RAO ( 9(IO OB2 (10 (F7 OBl [ll(F6 OBO [12 (FS OA4 [13 (F4 (14(GND
I I

\- - -I

I I VCCl28] I8127J I9 I26J IlOl25] Illl24] !12123] !13122] !14121] IlS 120] PR/OE_ll9] PRESET FO (18] CAO Fl 117] OAl F2(16] OA2 F3115] OA3
I I

a. SNAP Equations Figure 7.

October 1993

Philips Semicon<ilctors Programmable Logic Devices
Single chip multiprocessor arbiter
· PIH LABBLS Ii BOOLIUlll BllPRBSSIOKS USBD IJl' !IUIRSI!IOKS · &OU!PU'l VECTORS [082, OBl, OBO, OA4, OA3, OA2, OAl, OAO]srffs QAO .. l'Eh QA1 · FDb QA2 - l'Bh QA3 - 1'7b QA4 - Bl'b ~ .. Dl'b QBl - Jll'b QB2 = 7l'b ; llOGRAll'I - l'l'b @HAD VBCTORS [ 1'1'5, 1'1'4, 1'1'3, 1'1'2, 1'1'1, l'l'O ]srffs WO · 031!'b
1'1 ,. 03Bb
= W2 · 03Dh ;
W3 03Ch ; W4 · 03Bh ; W04 .. 111---b GAO· 06h GA1 - 07h QA2 · OBb QA3 · Ol'h GA4 · 16h ,
GBO = 101---b
GBl · 110---b GB2 - 100---b
b. SNAP Equatlona (Continued)
Figure 7 (Continued)

Application Note
AN07

650

Philips Semiconductors Programmable Logic Devices
Single chip multiprocessor arbiter

@TRANSITIONS

WHILE [WO] CASE [/RAO] : : [GAO] WITH [QAO] [/RAl *RAO] :: [GAl] WITH [QAl] [/RA2 * RA1 * RAO] : : [GA2] WITH [QA2] [/RA3 * RA2 * RAl * RAO] : : [GA3] WITH [QA3] [/RA4 * RA3 * RA2 * RAl * RAO] : : [GA4] WITH END CASE

[QA4]

WHILE [Wl] CASE [/RAl] : : [GAl] WITH [QAl] [/RA2 * RAl] : : [GA2] WITH [QA2] [/RA3 * RA2 * RAl] : : [GA3] WITH [QA3] [/RA4 * RA3 * RA2 * RAl] : : [GA4] WITH [QA4] [/RAO* RA4 * RA3 * RA2 * RAl] :: [GAO] WITH ENDCASE

[QAO]

WHILE [W2] CASE [/RA2] : : [GA2] WITH [QA2] [/RA3 * RA2] : : [GA3] WITH [QA3] [/RA4 * RA3 * RA2] : : [GA4] WITH [QA4] [/RAO * RA4 * RA3 * RA2] : : [GAO] WITH [QAO] [/RAl * RAO * RA4 * RA3 * RA2] : : [GAl] WITH END CASE

[QAl]

WHILE [W3] CASE [/RA3] : : [GA3] WITH [QA3] [/RA4 * RA3] : : [GA4] WITH [QA4] [/RAO * RA4 * RA3] : : [GAO] WITH [QAO] [/RAl * RAO * RA4 * RA3] : : [GAl] WITH [QAl] [/RA2 * RAl * RAO * RA4 * RA3] : : [GA2] WITH END CASE

[QA2]

WHILE [W4]
CASE
[/RA4] :: [GA4] WITH [QA4]
[/RAO * RA4] : : [GAO] WITH [QAO] [/RAl * RAO * RA4] : : [GAl] WITH [QAl]
[/RA2 * RA1 * RAO * RA4] : : [GA2] WITH [QA2]
[/RA3 * RA2 * RA1 * RAl * RA4] : : [GA3] WITH END CASE

[QA3]

WHILE [W04]
CASE
[/RBO * RA4 * RA3 * RA2 * RAl *RAO] :: [GBO] WITH (QBO) * [/RBl * RBO * RA4 RA3 * RA2 * RAl *RAO] :: [GBl] WITH [QBl] [/RA2 * RBl * RBO * RA4 * * RA3 * RA2 * RA1 * RAO] : : [GA2] WITH [QB2]
ENDCASE

WHILE [GAO] IF (RAO] THEN
WHILE [GAl] IF (RAl] THEN
WHILE [GA2] IF (RA2] THEN
WHILE [GA3] IF (RA3] THEN
WHILE [GA4] IF (RA4] THEN
WHILE [GBO] IF (RBO] THEN
WHILE [GBl] IF (RBl] THEN
WHILE [GB2] IF (RB2] THEN

[Wl] WITH [NOGRANT] [W2] WITH [NOGRANT] [W3] WITH [NOGRANT] [W4] WITH [NOGRANT] [WO] WITH [NOGRANT] [GBl] WITH [NOGRANT] [GB2] WITH [NOGRANT] [GBO] WITH [NOGRANT]

b. SNAP Equations (Continued) Figure 7 (Continued)

October 1993

Application Note
ANO?

Philips Semiconductors Programmable Logic Devices
Minimize metastability in 50MHz state machines

Application Note
AN032

Engineers are excited to discover the PLUS405-55, a PLD state machine IC rated for a maximum operating frequency of 55MHz. It has a flexible architecture offering 65 product terms, and a programmable OR array driving 16 J-K flip-flops, 8 of which are buried {see Figure 1). This design allows the 64 product terms to realize 64 state transitions in a general state machine implementations. {State machines based on a counter will be implemented much more efficiently.) In order to estimate if a particular state machine will fit in the PLUS405, one need only count the state transitions and assure that there are fewer than 651 There are the remaining issues of number of states, inputs and outputs. The PLUS405 has 8 buried registers, allowing representation of 256 unique states. A dual complement array is available for the "ELSE" condition of state equations, and along with dual clocking capabilities allows two independent state machines to be synthesized on one IC.
Ease of design is further enhanced by SNAP, the PC-based PLD development tool. SNAP supports Boolean and State Equation entry of the design, simulation, and downloading of the programming information to a programmer. SNAP allows an abstract approach to design with PLDs, as the target device is not specified by the engineer until he is done fully integrating and simulating his efforts. After device selection, SNAP can back-annotate the design files with target silicon characteristics, allowing simulation of the actual device.

The engineer sets out to solve all his high speed state machine design problems armed with this new silicon and software, only to discover all this performance has its price. Studying the data sheet on the PLUS405-55 shows the following performance:

fMAX1 Input Setup time Input Hold time

55.6MHz minimum 10ns minimum Ons minimum

The cycle time at 55MHz is roughly 18.2 nsec. The window during which data must be stable to guarantee no metastability is 10 nsec long. The difference between the setup and hold time, and the cycle time, is the allowed time interval for changes to occur. this example leaves 8.2ns for any changes.

From a system standpoint, this means the design engineer must be extremely careful in implementing his system, or he will violate the setup and hold specifications of the PLUS405-55. This can lead to metastable conditions in the state machine with several negative effects: 1. Jumps to undefined states. {May hang up
system!)

2. Lengthened clock to Q times {slows down!).

3. Jumps to states out of proper sequence.

All of the above problems will yield a system
that is unreliable, unpredictable and expensive in terms of servicing elusive bugs in the field.

The preceding analysis said nothing regarding asynchronicity. It is feasible to design the above system in a fully synchronous manner and have acceptable results. What about the system where known asynchronous inputs will be used in the state machine? Examples of common asynchronous signals are refresh request in DRAM controller applications and interrupts in a real-time control system. One approach
to managing asynchronous inputs is to
precede the state machine with a D-type flip-flop. This can serve as a synchronizing stage ... or can it??? A simple analysis will explore the feasibility of using a simple synchronizing flip-flop.
A common Dual-D flip-flop frequently selected for this application in TTL high-performance systems is the FAST 74F74. The asynchronous data is fed into the D input of the flip-flop, and the Q output is fed into the logic input of the PLUS405 state machine. A common clock is used for both parts {see Figure 2). Based on current published data sheets, the 74F74 has a clock-to-0 time of 9.2ns maximum. The worst case setup time on the PLUS405-55 is 10ns. The minimum cycle time of the combined system is (9.2 + 10) ns, yielding a maximum clock frequency of 52MHz. Let's assume for this example a desired system clock is SOM Hz.

Philips Semiconductors Programmable Logic Devices
Minimize metastability in 50MHz state machines
15

Application Note
AN032

SORJ Q (4)
RORK
p R
SORJ Q (4)
RORK
p R
SORJ (4)
RORK
4

October 1993

4
Figure 1. PLUS405-Q5 Functional Diagram

INIT/OE

Philips Semiconductors Programmable Logic Devices
Minimize metastability in SOMHz state machines

Application Note
AN032

74F74
Q

1--------------------------------------,

I

P

Po

I

I

··························

I

I

I

I

llCLK

I

I

I

I

I

I

I I

I I

I

DATA

(4)

CLOCK > - - - - - - <

SORJ Q (4)
SORJ (4)

I

INITIO!

I

~~~~~---------------------------------

Figure 2. 74F74 Driving PLUS405-55

Philips Semiconductors Programmable Logic Devices
Minimize metastability in 50MHz state machines

Application Note
AN032

The important issue to examine in the timing diagram is the time that elapses between the end of the 74F74 clock-to-a interval and the beginning of the PLUS405's setup time {see Figure 3). This is 20ns minus 10ns minus 9.2ns, which equals .Bns! At 50MHz, this combination is just able to work reliably on a worst case basis, assuming no instances of metastability. If metastable operation is encountered, the 800 picosecond window is the only time left in the clock cycle to resolve the situation. The next issue to examine is the mean time between failures (MTBF) for this system. From the work of Mr. Chaney, an equation which models metastable behavior is:

EQUATION 1. MTBF = exp("'/") I (TO · f ·a)

{Explanation of above symbols}

MTBF is mean time between failures, in seconds.

"r
or

is the elapsed time before sampling the process
the time allotted for metastability to resolve.

is the "Metastability Time Constant".

TD

in seconds, the zero intercept of

aperture time versus propagation

delay. TO indicates the propensity

of a device to enter the metastable

state.

is the clock speed, in Hertz.

a

is the transition rate of data being

sampled (i.e.. edges per second)

in Hertz.

Assume for this discussion that the asynchronous input data is roughly 2MHz, meaning the edges that can cause metastability occur at a 4MHz rate. The system clock is assumed to be 50MHz, and the elapsed time before sampling is 1Ons. (The sample time is calculated from the difference between the cycle time (1/50MHz = 20ns) and the setup time of the PLUS405-55 (10ns). The other parameters can be determined from measurements of an 'F74, or can be found in Mr. Chaney's paper. " was found to be .4ns and TO .2 milliseconds. Armed with a calculator and Equation #1, the MTBF for this particular scenario is calculated:

MTBF = exp{10/.4) I {.2e--3* 50e6 · 4e6) =
1.8 seconds

Clearly, this level of failure in any system is unacceptable. A better solution for this class of problem must be found!
Philips Semiconductors has recently introduced a new family of parts designed with metastability performance in mind. The first four members of this family are the 74F5074, 74F50109, 74F50728 and 74F50729. These are excellent general purpose flip-flops, but special attention has been paid to short setup and hold times, and fast clock-to-a times. The output stage has also been designed with a balanced drive characteristic, leading to tight matching between rise and fall propagation delays, and matching of skews between other outputs. this makes them useful in clock driver applications also. Let's repeat the former calculation using the measured" and TO values for the 74F5074 used as a synchronizer {see Figure 4) ahead of the PLUS405-55.
"= .135ns
TO = 9.8 E 6 seconds
MTBF =exp{10/.135) I (9.8e6 · 50e6 · 4e6) =
75.46 e9 seconds
NOTE: For the reader's reference, a century is 3.154 e9 seconds.

Q 74F74

I PLUS405-55 INPUT REQUIREMENTS

10ns - - - - 1 1... DATA MUST BE STABLEI (SETUP TIME)
Figure 3. Timing Diagram of 74F74 and PLUS405-S5

October 1993

Philips Semiconductors Programmable Logic Devices
Minimize metastability in 50MHz state machines

Application Note
AN032

74F5074
Q DATA
CLOCK > - - - - - t

r--------------------------------------~

I

P ··························Po

I I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

SORJ Q

I I

(4)

I

I

I I I I I I I I I I I I I I I I I I I I I I I I I I
I
I
I
I
I I
I
I I I I I I

SORJ Q (4)
RORK
SORJ (4)

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

INIT/CE

I

I

I~P- LU- S40-5-- 55 --------------------------------- J

nrtnhor 1QQ~

Figure 4. 74F5074 Driving PLUS40~5 656

Philips Semiconductors Programmable Logic Devices
Minimize metastability in 50MHz state machines

Application Note
AN032

Dn - - - - - - - - - - 1 D CP

Q t--------1 D
CP

Q .------
o. 0 ·>-----

Ron -------------------------~
Figure 5. Internal Diagram of 74F50728 (1/2)

A system that was unreliable is now found to be quite acceptable by using the 74F5074. The major drawback to the synchronizing flip-flop solution is the added delay on the asynchronous signal before it enters the state machine. In the case of the 74F5074, this will amount to one clock cycle delay. For designs that demand the maximum in freedom from metastability, Philips Semiconductors has developed a product with cascaded D flip-flops for synchronizing applications. The 74F50728 (see Figure 5) will therefore introduce a two clock cycle delay into the system. It is pin compatible with the 74F5074 and 74F74 to allow retrofits on existing systems.
Calculation for the MTBF of a system using the 74F50728 is similar to the technique used earlier. In this case though, at least one entire clock cycle is used to resolve any metastability.

EQUATION 2. MTBF = exp(trh) I (TO· f ·a)

{Explanation of above symbols)

All symbols are the same as EQUATION 1 with the exception of tr.

tr

is the elapsed time before sampling

the process or the time allotted for

metastability to resolve. In the case

of 74F50728, one entire clock

cycle.

The flip-flops embedded in the 'F50728 are essentially the same as the flip-flops used for the 'F5074, therefore the same "Metastability Time Constant" t, and TO, can be used in the calculation.

MTBF = exp(20/.135)/ (9.8e6 · 50e6 · 4e6) = 1.12 e43 seconds!

Now that the designer is comfortable with handling metastability, it is feasible to begin

approaching the design of the system by stating a goal for MTBF and adjusting the state machine's clock to meet the desired failure level.
Let's assume out system is to have an MTBF of 5 years from metastability induced anomalies. The calculations would proceed as follows, assuming the same 2MHz data rate from our previous example:
MTBF = 5 years· (31.54 e6 seconds/year)= 157.7 e6 seconds
Setting up the equation to find the roots yields:
EQUATION 3. T(setup)/t - 1/(f * t) + 1n(TO·a*MTBF.f) = 0
(T(setup) is the setup time on the PLUS405)

October 1993

Philips Semiconductors Programmable Logic Devices
Minimize metastability in SOMHz state machines

Equation 3 is not solved using algebra, but simple numerical methods will allow easy solution, especially since we have a good initial guess for the value off. (50 to 55MHzl) An HP 32S calculator was used to find the root of this equation by the following program:

COMMENTS

PRGM

start program entry

GTO ..

go to top of memory

801

L8URTN {L8LJ 8 label program as 8

802

INPUT

A

a, Data rate, Edges/Sec.

803

INPUT

F

Clock frequency, Hertz

804

INPUT

J

~.seconds

805

INPUT

M

MT8F, seconds

80S

INPUT

T

807

INPUT

u

TO, seconds T(setup), seconds

808

RCL

A

begin calculation of 1n argument

809

RCLx

T

810

RCLx

M

811

RCLx

F

812

LN

813

RCL

F

814

RCLx

J

815

1/x

81S

+/-

change sign

817

+

add

818

RCL

u

819

RCL+

divide

820

+

821

L8URTN {RTN}

end, return from routine

To execute this program we must use the SOLVE capability on the calculator.

SOLVE {FN} 8 50 ES SOLVE {SOLVE} F A? R/S J? R/S M? R/S T? R/S U? R/S

FN= STO SOLVE 4.0 ES 135 E-12 157.7 ES 9.8 ES 10. E-9

Prompt for label of function
F load initial guess SOMHz prompt for unknown variable frequency in this case! set edge rate run
set~
setMT8F
set TO
setup time

S58

Application Note
AN032

Philips Semiconductors Programmable Logic Devices
Minimize metastability in SOMHz state machines

Application Note
AN032

At this point the calculator will set off to find the root based on the initial guess and the desired conditions entered. The system clock speed determined from this technique is 52.16MHz.
Designers who are forced to deal with an uncertain system for the first time are uncomfortable with the idea that is is possible for the system to fail. Lower speed systems have been traditionally designed using worst case data sheet numbers to guarantee that

the system will always work. As system clock speeds cross over SOMHz, meeting the setup and hold times becomes very difficult for ITL-based designs. The allowed time to resolve metastability gets shorter and the data stream edges become much more frequent, increasing the incidence of metastability. Faster systems demand that a design methodology based on statistics be used and the burden is now on the Engineer to manage likelihood of failure to acceptable

levels. Persons defining high performance systems will need to specify goals for MTBF due to metastability. Usage of parts that have been characterized for metastability behavior will become mandatory in future systems. New parts, such as the 74F5074 and 74F50728 from Philips Semiconductors, which have published metastable traits and are pin compatible with other industry standard ICs, can make solving these problems as easy as plugging in a new part!

Dike, Charles, ·AN219, A Metastability Primer", Philips Semiconductors
Chaney, Thomas J., "Measured Flip-Flop Respcnses to Marginal Triggering"[IEEE Transactions on Computing, Vol. C-32, No. 12, December 1983, pp. 1207-1209] Wakerly, John, "Designers Guide to Synchronizers and Metastability, Part 1 and 2" September 1987, VLSI Design

October 1993

Philips Semiconductors Programmable Logic Products
Implementing Counters in Sequencer Devices

Application Note
AN050

INTRODUCTION
Some state machine applications require a state machine to wait for a number of clock pulses to occur before some decision point is reached. One common example of this is a state machine that needs to analyze only certain bits in a serial data stream. The state machine may have to wait for a number of serial data bits to transpire before pulsing a load signal or proceeding into states to actually check individual data bits for specific preamble or header information.
SEQUENCER ARCHITECTURE
State machine implementations using JK flip-flop based sequencer devices are generally very efficiently implemented because product terms (AND gates) are required only to force a transition from one state to the next. Product terms are not required to hold the sequencer in a state, as they are for D-type based devices. A JK based state machine can wait forever in one state for a specific parallel combination of input signals to happen, using only one product term to pertorm the comparison and force a jump to a new state. In addition, Philips sequencers have a PLA architecture meaning that both the AND array and the OR array have programmable connections. A single product term may be connected to the inputs of multiple state and/or output registers. This feature allows for efficient device resource utilization since any product term may be connected to any buried or output register. The product terms are not fixed in their usage to a specific register or output.
DESIGN METHODS
PLO software packages, such as Philips SNAP, provide for different methods of design entry. The easiest and usually best format for state machines is, of course, a state equation entry method. Figure 1 shows an example using state equations. For JK based sequencers, SNAP essentially translates

each 'IF' statement into a product term in the device. An OR function in the input condition field of the 'IF' statement will cause an additional product term to be used.
A series of unconditional transitions to a new
state may be found in some state machine designs where it is required to wait a certain number of clock cycles before, pertorming a function. The example in Figure 1 shows a simple state machine that runs continuously through sixteen states and outputs a pulse on output 'OUT1' while in state 'F'. This state machine is not waiting for any inputs, other than the clock to occur. It is simply a counter.
COUNTER IMPLEMENTATION
For typical state machine implementations with conditional transitions between states, state equations produce efficient state machines. However for implementing counters, state equations may not produce the most efficient implementation. JK flip-flops have a feature whereby if both J and Kare active, after a clock, the output will toggle or change state. This feature may be used to implement counters very efficientiy. Combining the toggle feature of the flip-flops with a PLA devices ability to connect a single product term to multiple OR array inputs, produces an implementation where only one product term is needed for each bit in the counter. A four bit counter may be constructed using only four product terms!
The function described in Figure 1 is duplicated in Figure 2, except the Figure 2 design uses a counter described with Boolean equations. Only six product terms were used compared to the sixteen used for the design in Figure 1. Four product terms were used for the counter and two to control output pin OUT1. So, when a portion of a state machine design is required to unconditionally transition from one state to the next, consider implementing a counter using Boolean equations and merging it into the state machine. The example in Figure 2 only used Boolean equations, no state equations. So, another

example is shown in Figure 3. This example, using SNAP, illustrates the proper syntax for connecting the outputs of a counter to the inputs of a state machine. This example was complied for a PLUS405 device. The state machine will wait in each state until the counter reaches a specified value. It then transitions to the next state.
Complicating the design a bit more, Figure 4 shows another SNAP example. This is a listing of a design that, in addition to using the counter outputs as inputs to the state machines, connects two outputs of the state machine back to the counter. The outputs of the state machine (actually two of the state bits) can enable or disable counting, or reset the counter. In this example the state vectors were specially assigned such that state register S1 must be LOW for the counter to count. When state register S2 is HIGH, the counter will be reset. Instead of using state registers bits, additional outputs could have been defined and connected to the counter.
Figure 5 shows a counter that counts from O to 12 and then resets. This example may be easily modified to produce a counter that counts to any value.
SUMMARY
The toggle feature of JK flip-flops together with a product term sharing capability, found in most Philips sequencer devices, may be used to build counters using only one product term per counter bit. If a state machine design contains many unconditional transitions, it is possible to reduce the number of product terms required to implement the design by separating the design into a counter and state machine. The counter portion should be described using Boolean equations, when state equations are preferred for the state machines. The counter outputs may be used as inputs to the state machine and some state machines outputs or state bits may be used to enable or reset the counter.

660

Philips Semiconductors Programmable Logic Products
Implementing Counters in Sequencer Devices

@PINLIST elk i; init i;
outl o;

@GROUPS @TRUTHTABLE @LOGIC EQUATIONS

s[3 .. 0].rst = /init; "Use INIT function pin (19) to reset counter" outl.rst = /init; "and to reset output pin."

@INPUT VECTORS
@OUTPUT VECTORS [outl] jkffr
oO = Ob; ol = lb;

@STATE VECTORS
[s3,s2,sl,sO]jkffr
stO OOOOb;
stl OOOlb;
st2 OOlOb;
st3 OOllb; st4 OlOOb;
stS OlOlb; st6 = OllOb;
st7 Olllb;
st8 = lOOOb; st9 = lOOlb;
sta = lOlOb;
stb = lOllb;
stc = llOOb;
std= llOlb; ste = lllOb; stf = llllb;

@TRANSITIONS

while [stO]
if [] then [stl] while [stl]
if [] then [st2] while [st2]
if [] then [st3] while [st3]
if [] then [st4] while [st4]
if [] then [stS] while [st5]
if (] then [st6] while [st6]
if [] then [st7] while [st7]
if [] then [st SJ while [st8]
if (] then [st9] while [st9]
if [] then [sta] while [sta]
if [J then [stb] while [stb]
if [] then [stc] while [stc]
if [] then [std] while [std]
if [] then [ste] while [ste]
if [] then [stf] with [ol] while [stf]
i f (] then [stO] with [oO]

Figure 1. SNAP State Equations

661

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Philips Semiconductors Programmable Logic Products
Implementing Counters in Sequencer Devices
@l'INLIST elk i; init i; outl o; @GROUPS @TRUTH TABLE @LOGIC EQUATIONS "Simple four bit binary counter that" "uses toggle feature of JK flip-flops." "Because of p-term sharing, only 4 p-terms" "are needed to implement this counter." cO.j l; cO.k l; cl.j = cO; cl.k = cO; c2.j cO * cl;
c2.k = cO * c1; c3.j = cO * cl * c2; c3.k cO * cl * c2;
= c[3 ·· 0].rst /init; "Use INIT function pin (19) to reset counter"
outl.rst = /init; " and to reset output pin" "In this example the counter is free-running." "OUtl will be high when the count is llllB and" #will be forced low when the counter transiations" "from 1111 to 0000 binary or reset by pin 19."
= outl.j = c3*c2*cl*/c0;
outl.k c3*c2*cl* cO; @INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANSITIONS
Figure 2. Counter Boolean Equatlona

Application Note
ANOSO

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Philips Semiconductors Programmable Logic Products
Implementing Counters in Sequencer Devices

@J?INLIST elk i; init i; outl o;
out2 o;

@GROUJ?S @TRUTHTABLE @LOGIC EQUATIONS

"Simple four bit binary counter''

cO.j cO.k cl.j cl.k c2.j c2.k c3.j c3.k

l; l; co;
cO; co * cl; co * cl; co * cl * c2; co * cl * c2;

c[3 .. 0].rst s[l. .O) .rst out [2 .. 1) · rst

/init "Use INIT function pin (19) to reset counter" /init " and state registers" /init " and output pins"

@INl?UT VECTORS @OUTl?UT VECTORS [outl,out2]jkffr
oO 0-b; ol 1-b; o2 -Ob; o3 -lb;

@STATE VECTORS
[sl,sO)jkffr
stO OOb;
stl Olb;
st2 = lOb;
st3 = llb;

@TRANSITIONS

"In this example the counter outputs are used" as inputs to the state machine"

while [stO]

if [c3*c2*cl*/c0) then [stl) with [ol] "move to state 1 when counter goes"

"from E hex to F hex"

while [stl)

if [) then [st2) with [oO)

"upon next clock go to state 2 and"

"reset output"

while [st2)
= if [/c3*c2*cl*/c0] then [st3] with [o3] "wait here until count 6 hex"

"then go to state 3 and set out2"

while [st3]

if [) then [stO] with [o2]

"goto state 0 and reset out2"

Figure 3. Counter Connected to State Machine

Application Note
ANOSO

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Philips Semiconductors Programmable Logic Products
Implementing Counters in Sequencer Devices

@PINLIST elk i; inl i; init i;

outl. o; out2 o;

@GROUPS @TRUTHTABLE @LOGIC EQUATIONS

"Four bit binary counter" ''controlled by state machine state register bits"

cO.j cO.k cl.j cl.k c2.j c2.k c3.j c3.k

/sl*/s2;

"Counter will be forced to 0000 upon''

/sl;

"clock and state bit s2 high."

/sl * co * /s2;

"Counter won't count unless state"

/sl * cO;

"reqister sl. is low. (won't count"

/sl. * co * cl. * /s2;

"in state stl)"

/sl * co * cl.;

/sl. * co * cl. * c2 * /s2;

/sl. * co * cl. * c2;

c[3 .. O] .rst s[2 .. O] .rst out[2 .. l] .rst

/init; "Use !NIT function pin (19) to reset counter"
I init; " and state registersu
/init; " and output pins"

@INPUT VECTORS @OUTPUT VECTORS [outl,out2]jkffr
oO 0-b;
ol 1-b;
o2 = -Ob;
o3 = -l.b;

@STATE VECTORS [s2,sl,sO]jkffr stO OOOb; stl. -lOb; st2 = -Olb; st3 = lllb;

"Note the special state assignments to" "simplify one state bit connections to" "the counter."

@TRANSITIONS

"In this example the counter outputs are used" "as inputs to the state machine and some of the" "state register bits S2 and Sl control the operation" "of the counter."

while [stO)

if [/c3*c2*/cl.*c0] then [stl.) with [ol] "move to state 1 when counter goes"

while [stl)

"from 5 hex to 6 hex"

if [inl] then [st2) with [oO]

"when input 'inl = high' go to state 2 but"

"hold counter at 6 while waiting for inl"

while [st2)

if [c3*/c2*/cl*/c0] tben [st3) with [o3] "wait here until count = 8 hex"

"then·go to state 3 and set out2"

while [st3]

if [) then [stO] with [o2)

"goto state 0 and reset out2"

''and counter"

Figure 4. Counter Enable and Reset Functions Controlled

Application Note
ANOSO

664

Philips Semiconductors Programmable Logic Products
Implementing Counters in Sequencer Devices

@PINLIST elk i; ignd i; init i;
outl o;

@GROUPS @TRUTHTABLE @LOGIC EQUATIONS

"Four bit binary counter'' ''modified to count from" "0 to 11 and then reset.·

cO.j cO.k cl.j cl.k c2.j c2.k c3.j c3.k

nor;
nor;
nor * co; nor * co; nor * cO * cl; (nor * cO * cl) + count12;
nor* cO *cl* c2;
(nor * cO * cl * c2) + count12;

count12 = c3*c2*/c1*/c0; nor= /(countl2+ignd);

"When count=ll, then output NOR is LOW, disabling the product terms" "that cause the counter to count. Another product term (countl2)"
"connects to the registers of the counter that are HIGH K-inputs," "forcing it to all zeros upon the next clock. These connections may" "be modified to alter the upper count limit."

c[3 .. 0].rst = /init; "Use INIT function pin (19) to reset counter" outl.rst = /init; " and to reset output pin"

"In this example the counter is free-running." "Outl will be high when the count is llOOB and" ''will be forced low when the counter transistions" "from 1100 to 0000 binary or reset by pin 19."

outl.j = c3*/c2*cl*c0; outl.k = c3*c2*/cl*/c0;

"For SNAP 1. 90 to implement this design in a minimum number of product terms, two passes through the merger are necessary. First, generate a netlist normally - running NETCONV and MERGER. Then, highlight equations in the MERGER box to extract the equations from the netlist. Run the extracted equations through the minimizer (EQNGEN) . Run through NETCONV (Minimized) and MERGER again to produce a minimized netlist. The design may then be compiled for the device."
@INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANSITIONS

Figure 5. Modulo-n Counter

Application Note
AN050

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Philips Semiconductors Programmable Logic Devices
CMOS sequencers

INTRODUCTION
Philips Semiconductors invented the programmable logic sequencer with the 82S105 back in 1979. Since that time, ·lo.additional parts were introduced, with a wide following of users who got programmable · state machines into their designs. But, many potential users are still confused about what a sequencer is. Let us clarify that by simply stating that a sequencer is a programmable logic device capable of making user configurable state machines in a single chip. The first sequencers were configured with a programmable logic array (PLA) connected to a group of flip-flops. For state machine designs, the choice of either S-R or J-K flip-flops was appropriate because of logic efficiency. D flip-flops may be used, just as well, but are less efficient. Also, the restriction of using a PLA may not be mandatory. Many have used fixed-OR structures driving D flip-flops, and found the resulting solutions satisfactory. Hence, the broad definition of a sequencer is simply a programmable logic device with flip-flops. The inclusion of additional features beyond these basics can make all the difference in the world, and will be shown to be quite useful. Among the critical additional features are: A complement array, buried versus exposed flip-flops, independent flip-flop clocking and independent asynchronous set and reset

capabilities. As well, something as simple as permitting some flip-flops to be clocked on rising clock edges and others on falling edges can have far-reaching performance implications.
This booklet will look at three parts that are sequencers, but which also have the additional property of being made from CMOS, so they have some low power capabilities that similar bipolar devices do not have. These devices are the PLC1 SVSZ, the PLC415 and the PLC42VA12. Each of these devices will be presented with a detailed application described that is appropriate to that device. After an initial description of the parts is given, a brief discussion of power-saving techniques is given. Then the example applications are detailed with complete design files which can be run on Philips Semiconductors design software.
The PLC18V8Z
Figure 1 shows the PLC 1SVSZ logic diagram. As can be seen, there is a large programmable region that can interconnect input lines and feed back logic values to a region where they may be associated with the inputs to AND gates at small fixed-OR sites. This is termed Programmable Array Logic (PAL®). The outputs of the fixed-OR sites then drive into macrocells (the little

boxes in Figure 1). The macrocell is detailed in Figure 2, where it is seen that the macrocell consists of one D flip-flop, three multiplexors, an exclusive-OR gate (for polarity control), configuration programmable sites and feedback paths. The output points of the macrocells have access to the chip's output pins. By configuring the macrocell multiplexors, ~ is possible for a signal coming into the macrocell to be routed (by MUX) to the output pins (from the combinational logic area) to take the flip-flop output to the pins, to feed back the flip-Hop to the main logic array, or accept the "F" pin as in input. Because a large number of applications are "byte" oriented, eight macrocells fits in a data oriented system. The number of applications that require no more than 8 product terms per OR gate cluster, is also very large, and includes counters, shifters, pattern recognizers and handshakers. It should also be noted that a special output is dedicated on the macrocell to permit 3-State control of the output pins, from the programmable array.
Designers familiar with generic array logic . (GAL'") will appreciate that the PLC18V8Z IS intentionally pinned to be directly compatible with the 20-pin 16V8 device. This means that the PLC 1SVBZ can replace the long list of fixed-OR devices that includes the popular 16L8, 16R8, 16R6, 16R4, etc.

9PAL is a registered trademark of Advanced Micro Devices, lnc. GAL is a trademark of Lattice Corp.

October 1993

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Philips Semiconductors Programmable Logic Devices
CMOS sequencers

Denotes a programmable cell location. October 1993

Figure 1. PLC1 BVBZ

Philips Semiconductors Programmable Logic Devices
CMOS sequencers

r---------
1 I I I I I I

FROM AND ARRAY · TO ALL OMCe
~------,
.....
"'

' '

I

I :

L---------+-+-1-

NOTE:

yt

t.:~ Denotes a programmable cell location.

TOALLOMCe

_____ .:..J

Figure 2. PLC18V8Z Macrocell

October 1993

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Philips Semiconductors Programmable Logic Devices
CMOS sequencers

The PLC415
The PLC415 is shown in Figure 3, in a shorthand form. The actual part incorporates groups of J-K flip-flops with a programmable logic array. The flip-flops are logically grouped by virtue of association to specific output pins and association with particular clock inputs. The PLC415 illustrates both exposed flip-flops (Q outputs directly tied to the output pins) and buried flip-flops (Q outputs fed directly back to the programmable interconnect region). Sometimes, the outputs of the buried flip-flops are referred to as the state variable register because they capture next-state information to generate the transition signals for driving other flip-flop inputs. It should be noted that the PLC415 associates one group of four buried flip-flops, to a specific group of 4 exposed flip-flops by virtue of common clock inputs. Hence, this group can be thought of as a single, synchronous programmable state machine. The 64 product terms are available to be freely interconnected to any of the flip-flop OR gate inputs. There are no connection restrictions, and complete freedom of sharing. The second state machine can also use any of the AND gates as needed.
One of the powerful features of the PLC415, which is not available on registered fixed-OR

devices, is multiple clock source availability. This, coupled with independent 3-State controls, permits some unique inherent output multiplexing capabilities.
Another feature that has been seldom understood, is the "complement term." Basically, the complement term is a NOR gate located in the PLC415 PLA, to penmit efficient next-state transitioning. If flip-flop transitions are accomplished with Boolean products (asserted to logical "1" at their outputs), the state machine will transition accordingly. Usually, this is thought of by saying "If the machine is in state X, and an input of Z occurs, then assume the next state of W." What happens if input value Z doesn't occur? Usually, the machine will then stay in state X. But what if it is desired to move to another state if there are no asserted input conditions present? The logic designer is confronted with generating a function that provides the correct, positive asserted transition terms. This consumes lots of product terms, and the designer quickly depletes AND gates. However, by logically combining a product term that decodes the present state, with the missing input combination, a logical product will be generated permitting a next-state transition to occur when the input condition is absent. This product can be sent to the NOR term

(i.e., complement term), which generates a logical "1" when all of its inputs are at a logical "O". This NOR output can force a
transition from state X to state Y. This is
commonly referred to as generating a logical "else" condition. Hence, using the complement term, a state transition may be described as "if state X and input Z, then state W, else state Y." A particularly slick feature of this attribute is that by combining the current state with the queried input into a product tenm, other product terms can be . included in the complement NOR gate, which decode different states and input conditions. The state transition payoff is that only one complement term is really ever needed per state machine, to get the "else transitions" from all possible states. Because the PLC415 can build two independent machines, it includes two complement terms. The Philips Semiconductors design software SNAP automatically use the complement term to perform "else state transitions." Because the complement term requires a signal to pass through the programming array twice before hitting a flip-flop input, there is a small speed penalty to use it. However, there is a major payoff in terms of AND gate usage. This_ feature has literally become a signature item in most Philips Semiconductors sequencers.

October 1993

669

Philips Semiconductors Programmable Logic Devices
CMOS sequencers
OEB OEA INA INB
re">V=t=t=t=t==========~=!=J<O-----r---ll~K2
<:

October 1993

-f0-r--- ~
~ -t--+--D--t COPIE: P4-?

--t--r--D--i K

~

~

....--

-t--+--D--t J

Q~

~CK1/CK2

__,~~

- + - - - - H . > - - , - L f - : : - - t - - t_ - - D _-
~ '4

-I

v '4

D ;r....--
-+--+--D--1 J <l'-'.':H.t::L.f->-<......,1-

F

_1'

-

+

-

-

+

-

-

D

-

-

,. 1 J

.

-

-~H'-+----l

CK1

'f _· 4 COPIES

~ : J INTIENRITNAL

- + - t - - t - D - KP
~>--,f-4,_--------'

Rar-tf
~ ~i1

I 4
~Nti

F

-+---Hv ~

-= ~ -= ~

'f J
~

l~--+~~-PO-W-ER"DO-W-N --_Q,~/\

r INTERNAL INIT

~-~·{-t.
'--'--i.

.,:.- EXTERNAL INITIOE

J

Figure 3. PLC415

670

Philips Semiconductors Programmable Logic Devices
CMOS sequencers

The PLC42VA12
The PLC42VA 12 was recently (December 1989) heralded as one of the top programmable logic devices of the year by Electronic Design magazine. Its architecture solves more standard design problems for a 24-pin device than any other comparable device. The PLC42VA 12 is so flexible that designers are permitted nearly unrestricted design freedom. Incorporating 10 J-K Hip-flops with a large PLA, the designer is able to clock each flip-flop from a distinct source. Each flip-flop has asynchronous set and clear, and flip-flop outputs either pass to an output pin, back into the programming array, neither, or both. Using an output pin

does not force the associated flip-flop function to be Jost, and outputs are 3-State controlled in small groups, from either dedicated pins, or from the PLA. The PLC42VA12 also has two combinational outputs. As can be seen in Figure 4, the combinational output points are driven from polarity controlling Exclusive-OR gates. It should be noted that the PLC42VA 12 has been designed for compatibility with the popular 22V1 Odevice. Designers that have enjoyed the 22V10, but needed greater flexibility, will appreciate additional freedom in designing with the PLC42VA 12.
Functional independence is a key feature of the PLC42VA 12. By having separate clocks

for each flip-flop, the designer may treat each Hip-flop as a separate element. Most PLDs assign a single clock to large groups of Hip-flops, which forces the designer to restrict the applications to standard synchronous state machines. The PLC42VA12 permits a designer to build up to 10 (granted, simple) state machines in a single chip. But basically, design freedom is maximized in a PLC42VA 12. Additionally, the asynchronous reset and set inputs are carefully partitioned among the flip-flops to minimize restrictive design practices. As usual, the complement term is available for efficient utilization of the "IF-THEN-ELSE" syntax.

October 1993

671

Philips Semiconductors Programmable Logic Devices
CMOS sequencers

P63 · · · Po Fe
11-la
~
~'2_
.---12
~ ...

Ln Pn Rn CK,,

Lt.In Pt.In RM,, CKn DM,,

DMn

DBn
~

.l.g./.O. E

~ XS

lofCK

<

.....

~t--

<I-

X2 X2 XS XS

X2 X2 X2 X2 XS

X2

X2

rl

.L!!/ __t,'
l -+-----+--+-< XS

l - + - - - - - 1 - - - - - - - - - - - 1 x 2
POLARV.l.S>>----------lv;I">o~~-+---luU-81
Figure 4. PLC42VA12

October 1993

672

Philips Semiconductors Programmable Logic Devices
CMOS power in PLDs

Application Note
AN0301

CMOS POWER IN PLDs
When one first thinks of CMOS, zero power is one concept that comes to mind. A CMOS device should consume not power in a DC state, and when switching the power should be proportional to the frequency. This idea seems to make the thought of a zero power CMOS PLO a natural one. Yet, when one examines the CMOS PLO marketplace, only a fraction of the devices claim the mantle of zero power. An understanding of the basic concepts can be vital.
With the exception of two architectures all CMOS PLDs are constructed using an' electrically erasable (EE PROM) or ultraviolet erasable (EPROM) cell similar to that shown in Figure 1. It should be pointed out that a true CMOS E2 or EPROM memory cell does not exist. The core of almost all CMOS PLDs is an array of NMOS transistors. By wrapping the NMOS core with CMOS 1/0 cells, the illusion of a CMOS PLO is created (Figure 2). The only fallacy behind this is that NMOS devices consume power in a DC state. The array of NMOS devices are continually fed power to maintain optimum speed. This means that even in a DC state, where the device is not switching, the power level is in the 10's of mA. The main advantage here is that since only the array consumes power, the Ice of the device will be much less than similar bipolar PLDs. If we could "eliminate" the power to the array, the power drops to levels expected from CMOS devices.
There are two classical electronic techniques used to eliminate the Ice to the die core, and Philips Semiconductors uses both of them depending on the part. Both techniques have inherent disadvantages, but lower Ice dramatically. The first method is through the use of a special pin. When correctly asserted, a series blocking transistor(s) that supplies power to the core is turned off. This requires an external signal to control when Ice is to be blocked and the core becomes "asleep" or inoperable.

To wake up the part, the power down condition must be released. Placing the part into and out of power down mode takes time and this impedes performance. Figure 3 illustrates the power saving approach of a dedicated control pin with the specific transaction for the PLC415. Note that PD (Power Down) must be asserted (i.e., logic "1 ") and released (logic "O") with a specific timing relationship to the dock. II the timing is maintained, the device will power down and power back up in the same state. Should the
timing be altered, the internal state may be
lost.
From a simple viewpoint, the other method, which is used in Philips Semiconductors 1BVBZ, is more convenient. This technique, called "Input Transition Detection" (ITO), has been adapted from MOS memory design. A diagram of the key circuitry is shown in Figure 4. If any input makes either a high-to-low or low-to-high transition, the ITD senses it and sends a pulse to the array supply module. The supply in turn provides power to the array for a period of time long enough that the contents of the array can be latched. This data is now available as inputs into the 1/0 buffers for further processing. Once the data has been latched, there is no need for the array to consume power. The width of the power pulse is designed so it only need fulfill this function. This period of time, approximately 20ns for the 18VBZ, is much shorter than the cycle time of the device (35ns for the 1BVBZ). This means that the array only consumes power for 57% of each cycle. Obviously when longer cycles are used, the percentage is reduced. The rest of the circuitry obeys CMOS rules. The IDT feature gives a device more typical of a traditional CMOS technology. When all inputs are at static CMOS levels, power to the array is turned off so the device consumes a current of less than 100µA. Unlike some zero power PLDs, there is no surge in current

once the device becomes active. When switching, the current of the 18VBZ rises at a linear rate which is typically 1mA per MHz.
The key to the technique is the Input Transition Detection circuit. Shown in Figure 5 is a simplified ITD implementation.
When any of the inputs makes a transition,
the output of the Ex-OR gate, as well as the OR gate, goes high for a period determined by the delay circuit. This "power signal" is what feeds the array supply circuit which eventually powers the array. The width of the delay varies across temperature to compensate for faster speeds at cold temperatures and slower speeds at hot temperatures.
Waveforms for the ITD circuit are shown in Figure 6. When input A makes a low-to-high transition, the power signal goes high for a period of IAP after a delay of top. From these waveforms, it is easy to see one of the disadvantages of this method. When several inputs are applied to the device in a sys tom environment, there will be a finite amount of skew between the inputs. Since all inputs are tied to the ITD circuitry, pulses will be generated for each input. An example of this is shown in Figure 7. The power signal is initially triggered by input A. Input B, which is skewed from input A by the time lsKEW generates its own power pulse, which is ORed to the pulse generated by input A. This makes the power pulse last longer in a system environment, which means the device will consume more power than originally anticipated.
A disadvantage of the ITD circuit is a speed penalty. Two factors in the design reduce the speed. Since the array is not continuously powered, some delay is incurred by the ITD circuit to provide array power. The other speed penalty is paid in the data latches. These latches are necessary to store the array contents.

October 1993

Ip

N--CHANNEL

=

=

Figure 1. CMOS Programming - The EPLD

673

Philips Semiconductors Programmable Logic Devices
CMOS power in PLDs

Application Note
AN0301

NMOS

·

PROO RA Ml.ING

ARRAY (CORE)

·

CMOS llOPINS

Figure 2. CMOS PLO Layout

CMOS 110 PINS

ADDRESS-_V_'-/-L\ AA-DSDRTES-SVA~ _u_D_,VVVVVVVVVVVVV
LASTVAUD CLOCK

FIRSTVAUD CLOCK

tCKO

IPUA1,2
POWER UP
Figure 3. Power Down Enable and Disable
Vee
INPUT TRANSITION DETECTOR

LASTVAUD STATE

CMOS
110 CELLS

D

NMOS

A

PROGRAMl.ING

T

ARRAY

A

(CORE) L

A

T
c

H

E
s

October 1993

Figure 4. CMOS PLO with ITD 674

Philips Semiconductors Programmable Logic Devices
CMOS power in PLDs

Application Note
AN0301

INPUTO INPUTN

Figure 5. ITD Circuit

POWER SIGNAL

INPUT A
INPUTB ----!------------------
POWERSIGNAL - - - - - - 'DP _ _,___ _ IAp----..i
Figure 6. ITD Wavefonns

INPUT A
INPUTB ----!------.

----t-----' POWERSIGNAL
top

IAP+toP

Figure 7. ITD with Skewed Inputs

October 1993

675

Philips Semiconductors Programmable Logic Devices
Microcontroller power management

Application Note
AN0302

PLC18V8Z APPLICATIONS
The 80C51 microcontroller and its CMOS derivatives have two power reducing modes, Idle and Power Down. The Power Down mode reduces the device's current to less
than SOµA by only keeping the on-chip RAM
and SFRs data intact. In order to resume operation while in the Power Down mode, it is necessary to apply a reset to the microcontroller.
The PLC18V8Z is in a low power mode whenever its inputs are not switching, drawing less than 1OOµA. An input transition causes the PLC18V8Z to power up its
internal array for a short time, latch a valid
output and then return to low power mode. Because of this transparent power reduction feature and its programmability, the PLC 18V8Z is an excellent device to use in low power applications with an 80C51 microcontroller.
Two examples of using the PLC18V8Z with a SC87C751 microcontroller are presented. Both applications use the PLC18V8Z to detect events while the SC87C751 is in a Power Down mode and then reset (wake up) the microcontroller. The first example, shown in Figure 1, uses the PLC 18VBZ as an 8-bit

priority encoder. SNAP pin layout and listing
of the circuitry fused inside the PLC18VBZ is shown in Figure 2.
Whenever one of the inputs 17 - 10 goes LOW, a binary representation of its position is
output on pins A3 - Ao. If more than one input
is Active-LOW, then the input with the highest priority is represented on the output, where 17 has the highest priority. Another output, EO, is not connected to the microcontroller but is used to control the RST output of the PLC18V8Z. E0 is Active-LOW anytime all inputs are high. Actually, the PLC 1BVBZ could easily be reprogrammed to output the inverse of this signal which could be tied to the interrupt line of the microcontroller to generate an interrupt anytime one or more inputs were low.
Pin 16 of the PLC18VBZ, labeled RST, is the output of a 3-State buffer whose input is always high. The buffer's control line is tied internally to a product term which is enabled
ro by and an input from the microcontroller
labeled RSTEN. The RST buffer may be in
only two states, either driving a high (resetting the SC87C751) or 3-State (allowing C3 to discharge), enabling normal operation of the microcontroller. Before entering the

Power Down mode, the microcontroller
should force RSTrn low. Then, any low on 17
- 10 will cause EO and also RST high, resetting the microcontroller. When the microcontroller is reset, it will force its ports to input mode and since P1 and P3 have internal
pull-up resistors, RSTrn will go high forcing
RST into the 3-State mode allowing C3 to discharge.
The second example, shown in Figure 3, with SNAP pin layout and listing in Figure 4, uses the PLC 1BVBZ to monitor three microcontroller input lines (INc - INA) and
reset the microcontroller upon any change.
Three internal registers inside the PLC18VBZ are used to hold the states or levels of the input lines prior to entering Power Down mode. Before entering Power Down mode, the microcontroller should clock into the PLC18V8Z the states of INc- INA with the LOAD signal. Comparator logic fused into the PLC 1BVBZ compares the output of the registers to the three input lines. The RST output of the PLC 1BVBZ operates in a similar manner to the first example to reset the
microcontroller whenever RSTrn is low and
the output of the comparator is false.

U1

PLC18V8Z

Vee

SC87C751

P3.4

AO

P3.3

Al

P3.2

A2

P3.1

P3.0

P0.2

P0.1/SDA

PO.O/SCL

RST

X2

X1
vss

Vee

U2
-=
Figure 1.

October 1993

676

Philips Semiconductors Programmable Logic Devices
Microcontroller power management

Application Note
AN0302

************************************************************

*

PLClBVBZ 20-Pin DIP Package Pin Layout

*

*Date: 10/03/93

Time: 15:27:18 *

************************************************************

I

\ _ _/

I

I

I

llIO/CLK

VCCl20]

IO 21Il

F7119]

Il 31I2

F6118)

I2 41I3

F5I17J

I3 51I4

F4116] RST

I4 61I5

F3115) EO

IS 71I6

F2114) A2

I6 BII7

Fl 113) Al

I7 [ 91IB

FOl12) AO

[lOIGND

I9/0E_l 11J RSTEN

I

I

I

I

@PINLIST IO i;Il i;I2 i;I3 i; I4 i;IS i;I6 i;I7 i; RSTEN i; AO o;Al o;A2 o; EO o;RST o;

@GROUPS @TRUTHTABLE @LOGIC EQUATIONS

AO

/Il*I2*I3*I4*IS*I6*I7

+

/I3*I4*IS*I6*I7

+

/IS*I6*I7

+

/I7;

Al

/I2*I3*I4*I5*I6*I7

+

/I3*I4*IS*I6*I7

+

/I6*I7

+

/I7

A2

/I4*I5*I6*I7

+

/IS*I6*I7

+

/I6*I7

+

/I7

EO

/(IO*Il*I2*I3*I4*IS*I6*I7);

RST

1;

RST.OE = /RSTEN*EO;

@INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANSITIONS

October 1993

Figure2. 677

Philips Semiconductors Programmable Logic ~vices.
Microcontroller power management

Application Note
AN0302

GND

le

F1

'7 8

F2

la

F3

Is

F4

'4

F5

Ii;

17 Vee

cc

LOAD
-=

SC87C75

P3.4

P3.3

P3.2

P3.1

P3.0

P0.2

P1.6ANT1

P0.1/SDA

PO.OISCL

RST

X2

X1

P1.1

vss

U1

Flgure3.

October 1993

678

Philips Semiconductors Programmable Logic Devices
Microcontroller power management

Application Note
AN0302

************************************************************

PLC18V8Z 20-Pin DIP Package Pin Layout

* Date: 10/03/93

Time: 15:27:00 *

************************************************************

I

I LOAD 11 IO/CLK

INA INB INC RS TEN

21n 3 II2 4 II3 SII4

61IS 71I6 B II7

[ 91I8 [lOIGND

I

I

\ - - -I

I I VCCl20] F7I19] RST F6118] OUTC FSl17] OUTB F4 ll6] OUTA F3115] COMP F2114] NDC Fl 113) NDB FO 112] NDA
I9/0E_l 11J OEN
I I

October 1993

@PINLIST

LOAD i;INA i;INB i; INC i;RSTEN i;OEN i;

OUTA o;OUTB o;OUTC o; COMP o;NDA o;NDB o; NDC o;RST o;

@GROUPS @TRUTHTABLE @LOGIC EQUATIONS

da.d = ina;
= da.clk load;
nda = /da;
tion" nda.oe /oen;

"flip-flop equation" "invert buffer to pin equa-

db.d

inb;

db.elk load;
ndb = /db;

ndb.oe /oen;

dc.d = inc;
= de.elk load; = ndc /de;
ndc.oe = /oen;

out a outb outc comp

da*ina + /da*/ina; db*inb + /db*/inb; dc*inc + /dc*/inc;
outa * outb * outc;

"comparator"

rst = 1;
control"
= rst.oe /rsten * /comp;
is low and no compare"

"3-state reset "enable when rsten

@INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANSITIONS

Figure4. 679

Phlllpe Semiconductor· Programmable Logic Devlcea
Motor controller

Application Note
AN0303

PLC415 APPLICATIONS This example places 2 independent stepper
motor controllers in one PLC415. Each indvidually clocked controller includes a direction input as well as full and half step control. Individual set inputs force the internal state and output registers to state #1. Pin 19

is fused as a power-down input and may be used to reduce current consumption while the motors are stationary.
Suppose a stepper motor needs the sequence of data shown in Table 1 Clockwise rotation is performed by applying outputs associated with steps 1 through 8, while

counter-clockwise rotation is achieved by applying outputs correspondng to 8 through 1. Each state or step in this table is actually one half step to the motor. A full step skips one state.
SNAP listings for this example are shown in Figures 3 and 4.

Table 1. Half Step sequence

STATE

W1D

W1C

W1B

W1A

STEP1

0

1

0

1

STEP2

0

0

0

1

STEP3

1

0

0

1

STEP4

1

0

0

0

STEPS

1

0

1

0

STEPS

0

0

1

0

STEP7

0

1

1

0

STEPS

0

1

0

0

CLK1 FHSTP1
DIR1 SET1

1/2 PLC415

W1A W1B W1C W1D

POWER BUFFER

v
MOTOR

Figure 1. Stepper Control Circuit

October 1993

680

Philips Semiconductors Programmable Logic Devices
Motor controller

Application Note
AN0303

NOTES:
0 1, Di! are IN4001 0 1 is a 2N2222 0 2 is a 2N3055
03 is a BY127

Vee
R, 4700
a,
NPN

+20V

L,
INDUCTOR PHASE A

D2 DIODE

Figure 2. Stepper Control Power Buffer 1 OF4

************************************************************

*

PLC415 28-Pin PLCC Package Pin Layout

*

* Date: 10/03/93

Time: 15:28:48 *

************************************************************

CDS C S

LIEL E

KR T K T

2111 2

+-+-+-+-+-+-+-+

I I I I 1212121

141312111817161 +----------------------+

DIR2

I I
I
I I I I 5II4

I I I CVI I

567LC89

I

KC

c

L

K

I I
I
I
I I I IlO 125]

FHSTPl 61I3

Ill 124)

FHSTP2 71I2

Il2123]

81Il

Il3122)

[ 91IO

Il4121)

W2A [101F7

Il5120]

W2B [111F6

IN/O/P/I119)

I

I

I

G

I

I F F NF F F F

I

I 5 4 D3 2 1 0

I

+----------------------+

111111111111111

121314151617181 +-+-+-+-+-+-+-+

WW WWWW

22 1111 CD ABCD

Figure 3. SNAP Listing: Pin Diagram

October 1993

681

Philips Semiconductors Programmable Logic Devices
Motor controller

@PDILIST clkl i; olk2 i; fhstpl i; dirl i; setl i;
set2 i; dir2 i; fhstp2 i;

WlD o; WlC o; W1B o; W1A o; W2A o; W2B o;
W2C o; W2D o;

@GROUPS

@TRUTBTABLE

@LOGIC EQUA!IONS
= wla.clk clkl; "clock & set/rst for"

= wla.aet · aetl; "output flip-flops"
wlb.clk clkl;

wlb.rat a aatl;

wlc.olk · clkl;

= wlc.sat = satl;
wld.clk olkl;

wld.rst · aetl;

= pla.clk olkl; "clock & set/rat for"

pla.set · aetl; "internal flip-flops"

= plb.clk · clkl;
plb.rst setl;

= plc.olk = plc.set = pld.clk

olkl;
setl; clkl;

= pld.rst setl;

= w2a.olk · olk2;
w2a.set set2;

w2b.olk · clk2;
= w2b.rat set2; = w2c.clk clk2; = w2c.set set2;

w2d.olk · clk2;

w2d.rat · set2;

= p2a.clk = p2a.set = p2b.clk

clk2; aet2; olk2;

= p2b.rat · set2;
p2c.clk clk2;

p2c.set aet2;

p2d.olk · clk2;

p2d.rst · set2;

"output flip-flops" ·internal flip-flops"

@INPUT VECTORS @OUTPUT VECTORS [wld,wlc,wlb,wla] stepl OlOlb;
step2 OOOlb; step3 lOOlb; step4 lOOOb; step5 1010b;
step6 OOlOb; step7 OllOb; steps OlOOb;

October 1993

Figure 4. SNAP Usdng: .EON Fiie (1 of 3) 682

Application Note
AN0303

Philips Semiconductors Programmable Logic Devices
Motor controller

[w2d,w2c,w2b,w2a) stepla= OlOlb; step2a= OOOlb; step3a= lOOlb; step4a= lOOOb; stepSa= 1010b; step6a= OOlOb; step7a= OllOb; stepBa= OlOOb;

@STATE VECTORS

[pld,plc,plb,pla]

stpl OlOlb;

"state machine # l"

stp2 OOOlb;

stp3 lOOlb;

stp4 lOOOb;

stp5 1010b;

stp6 OOlOb;

stp7 OllOb;

stpB OlOOb;

[p2d,p2c,p2b,p2a)

stpla= OlOlb;

"state machine # 2"

stp2a= OOOlb;

stp3a= lOOlb;

stp4a= lOOOb;

stpSa= 1010b;

stp6a= OOlOb;

stp7a= OllOb;

stpBa= OlOOb;

@TRANSITIONS

"motor controller #1" while [stpl) if [ fhstpl* dirl] then [stp3] if [/fhstpl* dirl) then [stp2) if [ fhstpl*/dirl] then [stp7) if [/fhstpl*/dirl] then [stpB]

with with with with

[step3] [step2] [step?] [steps]

while [stp2) if [ fhstpl* dirl] if [/fhstpl* dirl) if [ fhstpl*/dirl) if [/fhstpl*/dirl]

then then then then

[stp4) [stp3] [stpB) [stpl)

with with with with

[step4] [step3) [stepB) [stepl)

while [stp3) if [ fhstpl* dirl) if [/fhstpl* di.rl) if [ fhstpl*/dirl) if [/fhstpl*/dirl)

then then then then

[stp5] [stp4] [stpl) [stp2)

with with with with

[stepSJ [step4] [stepl) [step2)

while [stp4) if [ fhstpl* dirl) if [/fhstpl* dirl) if [ fhstpl*/dirl] if [/fhstpl*/dirl]

then then then then

[stp6) [stp5] [stp2] [stp3]

with with with with

[step6] [stepS] [step2] [step3]

while [stpS) if [ fhstpl* dirl] if [/fhstpl* dirl] if ( fhstpl*/dirl] if [/fhstpl*/dirl]

then then then then

[stp7] [stp6] [stp3] [stp4)

with with with with

[step?) [step6) [step3) [step4)

while [stp6) if [ fhstpl* dirl] if [/fhstpl* dirl) if [ fhstpl*/dirl) if [/fhstpl*/dirl]

then then then then

[stpB] [stp7] [stp4] [stp5]

with with with with

[stepB] [step?] [step4) [steps]

"full step forward" "half step forward'' "full step backward" "half step backward"

October 1993

Figure 4. SNAP Listing: .EQN File (2 of 3) 683

Application Note
AN0303

Philips Semiconductors Programmable Logic Devices
Motor controller

while [stp7] if [ fhstpl* dirl] then [stpl] with [stepl] if [/fhstpl* dirl] then [stp8] with [step8] if [ fhstpl*/dirl] then [stpS] with [stepS] if [/fhstpl*/dirl] then [stp6] with [step6]
while [stpB] if [ fhstpl* dirl] then [stp2] with [step2] if [/fhstpl* dirl] then [stpl] with [stepl] if [ fhstpl*/dirl] then [stp6] with [step6] if [/fhstpl*/dirl] then [stp7] with [step7]
"motor controller #2" while [stpla] if [ fhstp2* dir2] then [stp3a] with [step3a] if [/fhstp2* dir2] then [stp2a] with [step2a] if [ fhstp2*/dir2] then [stp7a] with [step7a] if [/fhstp2*/dir2] then [stpBa] with [stepBa]
while [stp2a] if [ fhstp2* dir2] then [stp4a] with [step4a] if [/fhstp2* dir2] then [stp3a] with [step3a] if [ fhstp2*/dir2] then [stpBa] with [stepBa] if [/fhstp2*/dir2] then [stpla] with [stepla]
while [stp3a] if [ fhstp2* dir2] then [stpSa] with [stepSa] if [/fhstp2* dir2] then [stp4a] with [step4a] if [ fhstp2*/dir2] then [stpla] with [stepla] if [/fhstp2*/dir2] then [stp2a] with [step2a]
while [stp4a] if [ fhstp2* dir2] then [stp6a] with [step6a] if [/fhstp2* dir2] then [stpSa] with [stepSa] if [ fhstp2*/dir2] then [stp2a] with [step2a] if [/fhstp2*/dir2] then [stp3a] with [step3a]
while [stpSa] if [ fhstp2* dir2] then [stp7a] with [step7a] if [/fhstp2* dir2] then [stp6a] with [step6a] if [ fhstp2*/dir2] then [stp3a] with [step3a] if [/fhstp2*/dir2] then [stp4a] with [step4a]
while [stp6a] if [ fhstp2* dir2] then [stpBa] with [stepBa] if [/fhstp2* dir2] then [stp7a] with [step7a] if [ fhstp2*/dir2] then [stp4a] with [step4a] if [/fhstp2*/dir2] then [stpSa] with [stepSa]
while [stp7a] if [ fhstp2* dir2] then [stpla] with [stepla] if [/fhstp2* dir2] then [stp8a] with [stepBa] if [ fhstp2*/dir2] then [stpSa] with [stepSa] if [/fhstp2*/dir2] then [stp6a] with [step6a]
while [stp8a] if [ fhstp2* dir2] then [stp2a] with [step2a] if [/fhstp2* dir2] then [stpla] with [stepla] if [ fhstp2*/dir2] then [stp6a] with [step6a] if [/fhstp2*/dir2] then [stp7a] with [step7a]

"full step forward" "half step forward"
"full step backward" "half step backward"

Figure 4. SNAP Listing: .EQN File (3 of 3)

Application Note
AN0303

October 1993

684

Philips Semiconductors Programmable Logic Devices
OMA controller

Application Note
AN0304

PLC42VA12 OMA APPLICATIONS
The PLC42VA12 contains 10 flip-flops that may flexibly be configured to build counters, shifters or any customized state machine required. With today's 32-bit microprocessors, there is a need for user-

designed, system-specific OMA controllers that can generate addresses or count nibbles, bytes, half-words or words. Applications for these controllers include 1/0 concentration and cache subsystem updating. Typically, these devices can be preset or cleared and

count (up) by 1, 2, or 4 depending on the chosen circumstances. A solution for the problem is presented in this section to illustrate solving the problem with Philips Semiconductors SNAP design software. The SNAP files are presented in Figure 1.

@PINLIST CLK I ;MODEO I ;MODEl I;RST I;LOAD I;CO O;TOE I; OUTA O;OUTB O;OUTC O;OUTD B;OUTE B;OUTF B;OUTG G;OUTH B;OUTI B;OUTJ B;

@Logic Equations

model 0

modeO 0 1

function count by 1 count by 2 count by 4
illegal

QUOTA.J QUOTA.K QOUTB.J QOUTB.K

l*/load*/modeO*/model

"load disables P-terms"

+ modeO*/load

"force 0 for count by 2"

+ model*/load

+ XOUTA; ''or count by 4"

l*/load*/modeO*/model + YOUTA; "XOUTA,YOUTA are outputs of"

"tristate inputs "

outa*/load*/modeO*/model + l*/model*modeO*/load

+ rnodel*/modeO*/load + XOUTB; "force 0 count by four"

outa*/load*/modeO*/model

+ model*/modeO*/load + YOUTB;

DOUTC = outa*outb/load*/modeO*/model
+ outb*/model*modeO*/load; QOUTC.J DOUTC + XOUTC; QOUTC.K DOUTC + YOUTC;

DOUTD = outa*outb*outc*/load*/modeO*model + outb*outc*/model*modeO*/load + outc*model*/modeO*/load;
QOUTD.J DOUTD + XOUTD; QOUTD.K DOUTD + YOUTD;

''count by 1" "count by 2" "count by 4"

DOUTE =
QOUTE.J QOUTE.K

outa*outb*outc*outd*/load*/modeO*/model
+ outb*outc*outd*/model*modeO*/load + outc*outd*model*/modeO*/load; DOUTE + XOUTE; DOUTE + YOUTE;

DOUTF = outa*outb*outc*outd*oute*/load*/modeO*model
+ outb*outc*outd*oute*/model*modeO*/load + outc*outd*oute*model*/modeO*/load; QOUTF.J DOUTF + XOUTF; QOUTF.K DOUTF + YOUTF;

DOUTG =
QOUTG.J QOUTG.K

outa*outb*outc*outd*oute*outf*/load*/modeO*/model
+ outb*outc*outd*oute*outf*/model*modeO*/load + outc*outd*oute*outf*model*/modeO*/load;
DOUTG + XOUTG; DOUTG + YOUTG;

DOUTH = outa*outb*outc*outd*oute*outf*outg*/load*/modeO*/model + outb*outc*outd*oute*outf*outg*/model*modeO*/load; + outc*outd*oute*outf*outg*model*/rnodeO*/load;
QOUTH.J DOUTH + XOUTH; QOUTH.K DOUTH + YOUTH;

Figure1. SNAP Files (1 of3)

Philips Semiconductors Programmable Logic Devices
OMA controller
DOUTI outa*outb*outc*outd*oute*outf*outg*outh*/load*/modeO*/model + outb*outc*outd*oute*outf*outg*outh*/model*modeO*/load + outc*outd*oute*outf*outg*outh*model*/modeO*/load;
QOUTI.J DOUTI + XOUTI; QOUTI.K DOUTI + YOUTI;
DOUTJ = outa*outb*outc*outd*oute*outf*outg*outh*outi*/load*/modeO*/model + outb*outc*outd*oute*outf*outg*outh*outi*/model*modeO*/load
+ outc*coutd*oute*outf*outg*outh*outi*model*/modeO*/load; QOUTJ.J ~ DOUTJ + XOUTJ; QOUTJ.K ~ DOUTJ + YOUTJ;
CO = outa*outb*outc*outd*oute*outf*outg*outh*outi*outj*/load*/modeO*/model + outb*outc*outd*oute*outf*outg*outh*outi*outj*/model*modeO*/load + outc*outd*oute*outf*outg*outh*outi*outj*model*/modeO*/load;
" Reset for all flip-flops " QOUTA.RST RST; QOUTB.RST RST; QOUTC.RST RST; QOUTD.RST RST; QOUTE.RST RST; QOUTF.RST RST; QOUTG.RST RST; QOUTH.RST RST; QOUTI.RST RST; QOUTJ.RST RST;
" Flip-flops are followed by tristate outputs which drive the pin OUTA /QOUTA; OUTB /QOUTB; OUTC /QOUTC; OUTD /QOUTD; OUTE /QOUTE; OUTF I QOUTF; OUTG /QOUTG; OUTH /QOUTH; OUTI /QOUTI; OUTJ /QOUTJ; OUT A.OE TOE; OUTB.OE TOE; OUTC.OE TOE; OUTD .OE TOE; OUTE.OE TOE; OUTF.OE TOE; OUTG.OE TOE; OUTH. OE TOE; OUT I.OE TOE; OUTJ .OE TOE;
Figure 1. SNAP Files (2 of 3)

Application Note
AN0304

October 1993

686

Philips Semiconductors Programmable Logic Devices
DMA controller

"Pins are fed back to flip-flops using tristate inputs (FF load)"

XOUTA /OUTA;

"feed.back to J is inverted"

YOUTA OUTA;

"feed-back to K IS NOT inverted"

XOUTB /OUTB;

YOU TB OUTB;

XOUTC /OUTC;

YOU TC OUTC;

XOUTD /OUTD;

YOUTD OUTD;

XO UTE /OUTE;

YO UTE OUTE;

XOUTF /OUTF;

YOUTF OUTF;

XOUTG /OUTG;

YOUTG OUTG;

XOUTH /OUTH;

YOUTH OUTH;

XOUTI /OUTI;

YOUTI OUTI;

XOUTJ /OUTJ;

YOUTJ OUTJ;

XOUTA.LD LOAD;

XOUTB.LD LOAD;

XOUTC.LD LOAD;

XOUTD.LD LOAD;

XOUTE.LD LOAD;

XOUTF.LD LOAD;

XOUTG.LD LOAD;

XOUTH.LD LOAD;

XOUTI.LD LOAD;

XOUTJ.LD LOAD;

YOUTA.LD LOAD;

YOUTB.LD LOAD;

YOUTC.LD LOAD;

YOUTD.LD LOAD;

YOUTE.LD LOAD;

YOUTF.LD LOAD;

YOUTG.LD LOAD;

YOUTH.LO LOAD;

YOUTI.LD LOAD;

YOUTJ.LD LOAD;

Figure 1. SNAP Flies (3 of 3)

Application Note
AN0304

Philips Semiconductors Programmable Logic Devices
12C bus expander

Application Note
AN036

INTRODUCTION

GENERAL DESCRIPTION OF THE · 3'State buffers used as open collector

This application note describes two PLO

DESIGNS

outputs. The 3-State control-input of an 1/0

designs made wilh lhe PLC42VA12. Bolh

The two designs described in this report are

Output buffer is used as logic input. The

designs are conlroller functions for an

both controller functions for an 12C-Bus n-bit

input of that buffer is connected to the

12C-bus n-bit 1/0 expander. The first design is 1/0-expander. The designs were made on a

ground.

I

a controller function for a n-bit 12C-bus Input customer request to have a solution for his

Expansion {12C-bus Slave Transmitter

problem to address via the 12C-Bus more

The intention was, to put both the Slave

function) and the second one for a n-bit

than 200 bits of inputs and outputs. With the Transmitter and the Slave Receiver controller

12C-bus Output Expansion (12C-bus Slave

existing 12C-Bus devices the maximum

in one device. Unfortunately, the resources of

Receiver function).

number of input and/or output bits is 16 x 8 = lhe PLC42VA 12 are not sufficient to

The 12C-bus is a 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SOA) and a serial clock line (SCL). The designs provide remote input or output expansion for our Philips micro controller families via the two-line serial bidirectional 12C-Bus. The 12C-Bus slave

128 (8 x PCF8574 + 8 x PCF8574A). The designs work fully according to the 12C-Bus specification at 100kHz.
When an 12C-Bus master device {e.g. a micro controller) has to read data from or write data to the remote 1/0-expander devices PCF8574 and PCF8574A, it first sends the 12C-Bus

implement both designs in one device. As a combination of a Slave Transmitter and a Slave Receiver with a high number of inputs and outputs is seldom requested, this should not be a problem.
The first PLC42VA 12 design is an 12C-bus Slave Transmitter controller. With one or

address of the designs is equal to the
address of the PCF8574 {remote 8-bit 1/0 expander). The 12C-Bus has been specified

slave address of the device and then reads or writes only one byte. The two controller functions, the Slave-Receiver and the Slave

multiple 74HC165 devices, it forms an 12c-bus n-bit Input Expander. At one side the controller fully controls the 12c-Bus Slave

for 1OOkHz, but the PLC42VA 12 designs can Transmitter, don t have this problem. For

Transmitter function, and at the other side it

go up to 1MHz. This makes the designs

these designs, the master sends lhe slave

generates the control signals for the

suitable as test vehicle for lhe new fast

address only once, and then reads or writes

74HC165. The 74HC165 devices can be

12C-Bus standard of 400 kHz.
The PLC42VA 12 is the most powerful! PLO device in a OIL-package of Philips Semiconductors. The designs use almost all

one or multiple data-bytes. The master device, decides the number of bytes. The slave addresses used for the designs are
identical to the slave addresses of the

cascaded to increase the number of inputs. Chapter. 12C-Bus Slave Transmitter Function gives a detailed description of the design.
The second design is an 12C-bus Slave

resources and most of the features of the

PCF8574 and PCF8574A devices.

Receiver controller. With one or multiple

PLC42VA 12 e.g. combination of synchronous The 12C-bus has been specified for a 100 kHz 74HC595 devices it forms an 12C-bus n-bit

and asynchronous logic, 3-State outputs

clock (SCL). With the internal maximum

Output Expander. At one side the controller

used as open collector outputs and a

system clock of 8 MHz, the two PLC42VA12 fully controls the 12c-Bus Slave Receiver

combination of output flip-flops and state

designs can go upto an 12C-bus clock of

function, and at the other side it generates

flip-flops.

1MHz. This makes the design suitable as test lhe control signals for the 74HC595. The

The design has been verified on a bread-board. This board contains the two PLC42VA 12 controller designs, four 74HC165 devices, four 74HC595 devices and

vehicle for the new fast 12c-bus standard of
400 kbits/s. The speed is the only additional specification point of this new 12C-bus specification that can be met. The other new

74HC595 devices can be cascaded to increase the number of outputs. The section entitled 12C-Bus Slave Receiver Function describes in detail the design.

all the circuitry necessary to read 32

specification points as Schmitt-trigger inputs For design verification purposes, a

DIP-switches and to control 32 LED's.

and slope control of the falling edges of the

bread-board has been made. This board

This application note gives first a general description of lhe designs. Then it describes the characteristics of the 12c-Bus and some basic functions (tricks) used in bolh designs.

SDA and SCL signals can not be met.
The PLC42VA12 has been chosen, because of its special hardware features. These features are not available in other PLO

contains all the devices to build a Slave Transmitter with 32 inputs and a Slave Receiver with 32 outputs. The main devices of the board are:

You will find a detailed description of the

devices available in a 24-pin OIL package

·A PLC42VA 12 with the Slave Transmitter

designs and the 12C-Bus protocols of the

e.g. the PL22V10. Some of the used features

controller function,

controller functions in the sections entitled, 12C-Bus Slave Transmitter Function and

are: · Combination of synchronous and

· 4 PC?4HC 165 devices,

12C-Bus Slave Receiver Function. The

asynchronous logic.

· 4 octal DIP-switches,

appendix, gives all the used design files in the SNAP syntax. SNAP is the Philips Semiconductors PLO design software

· Combination of 0-type flip-flops with JK-type flip-flops.

·A PLC42VA 12 containing the Slave Receiver controller function,

package. You will find the equation entry files EON, the simulation control files SCL and the pinning files PIN. The last sheet gives the

· Flip-flops used as state registers. The M-pins used as inputs and/or outputs.

· 4 PC72HC595 devices, · 32 LED's.

schematic diagram of the bread-board.

October 1993

6RR

Philips Semiconductors Programmable Logic Devices
12c bus expander

Application Note
AN036

CHARACTERISTICS OF THE
12c.eus
The 12C-bus is a 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Bit Transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock

pulse as changes in the data line at this time will be interpreted as control signals (Figure 1, Bit Transfer). The maximum clock frequency is 100 kHz.
Stan and Stop Conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). Figure 2, Definition of Start and Stop Conditions, gives the timing diagram.

System Configuration
A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are slaves. Figure 3, System Configuration, gives a block diagram of the system configuration.

I SDA
SCL

x

:; \: /

I

I

Data Une

Change

Stobie:

of Data

Dato Valid

Allowed

Figure 1. Bit Transfer

\ \

- N : _ J '- - - - \ _ J :._

SDA

. I
I

I I

I I

. I
I

SDA

SCL

-~

/"""""\ ;:,

SCL

: s : L_/

'-·----'· p

Start Condition

Stop Condition

Figure 2. Definition of Start and Stop Conditions

SDA~~~~~~-.~~~~~~~-.~~~~~~~--~~~~~~~-+~~~~~~~--~~
SCL~~-.~~~-i-~~~-+~~~-+~~~-+~~~-+-~~~-+~~~-+~~~-e-~~~-+-~~

SLAVE RECEIVER

SLAVE TRANSMITTER

Figure 3. System Configuration

October 1993

Philips Semiconductors Programmable Logic Devices
12c bus expander

Application Note
AN036

Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the

acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Setup and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition (see Figure 4, Acknowledgement on the J2C-bus).
Formats
Data transfers follow the format shown in Figure 5 Data formats of the J2C-bus. After

the START condition, the master sends the slave address. This address is 7 bits long, the eighth bit is a data direction bit (R/WN). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ). A master always terminates a data transfer by a STOP condition. However, if a master still wishes to communicate on the bus, it can generate an other START condition and address an other slave without first generating a STOP condition. Various combinations of read and write formats are then possible within such a transfer.

etart condition

clock pulse for acknowledgement

SCLFROll MASTER

DATA OUTPUT BY RECBVER

Figure 4. Acknowledgement on the J2C-Bus

Philips Semiconductors Programmable Logic Devices
12c bus expander

Application Note
AN036

Possible data transfer formats are: a. Master transmitter to slave receiver. Direction is not changed.

I s

SLAVE ADDRESS

R/WN

A

DATA1

"O"(Write)

A

DATAn

-tranofened (n bytes + ocllnowledge)

b. Master reads slave immediately after first byte.

I A

p

A =acknowledge
S:llart
p =otop

s

SLAVE ADDRESS

R/WN

DATA1

I A

DATAn

I A

p

"1'(reod)

data transferTed (n bylff + ·ckn-edge)

At the moment of the first acknowledge, the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. This acknowledge is still generated by the slave.
The STOP condition is generated by the master.

S SLAVE ADDRESS R/WN A

DATA

A

S SLAVE ADDRESS R/WN A

DATA

p

read or write

L _J (nbytea +eek.)

read or write

direction of transfer may change ·· - point
During a change of direction within a transfer, the START condition and the slave address are both repeated, but the R/W bit reversed. Start, stop, slave addresses and R/W bits are generated by the master.

Figure 5. Data formats of the 12C-Bus

COMMON BASIC FUNCTIONS
This section gives a number of common basic functions used in the designs. The report gives for each function the basic diagram, the SNAP description and the timing diagram if applicable. The following basic circuits are described:
·Oscillator
· SCL Edge detection
· Start/Stop detection
Oscillator
The design has two clock options, the internal oscillator and an external clock. For both options, the clock input CLK is used. A HIGH CLKEN input selects the internal oscillator

and a LOW input the external clock. Without capacitor, we get the maximum frequency of the internal clock of 8 MHz. This frequency can be lowered by using a small capacitor C. Figure 6 Oscillator shows the diagram and the EON file description of the oscillator.
SCL Edge Detection
The frequency of the system clock is much higher than the 12C-bus clock (SCL). This means, that most of the time the state machine is waiting for the edges of the SCL clock. This section describes the circuit that detects the HIGH and the LOW going edge of the SCL clock. The state machines synchronizes on the output pulses SCLH and SCLL. The detection network uses only two flip flops and two AND gates. Figure 7 SCL

Timing Diagram SCL Edge Detection. gives the timing diagram of the edge detector and Figure 8 SCL Edge Detection. the diagram and the description of the EON file.
Stan/Stop Detection
A HIGH-to-LOW transition of the data line, while the clock is HIGH has been defined as the start condition (S) of the 12C-bus. A LOW-to-HIGH transition of the data line while the clock is HIGH has been defined as the stop condition (P). The easiest way to detect this start and stop condition is using asynchronoos logic. The PLC42VA 12 is very suited for this kind of solutions. Figure 2, Definition of Start and Stop Conditions, gives the timing diagram of these conditions.

October 1993

Philips Semiconductors Programmable Logic Devices
12c bus expander

Application Note
AN036

vcc
15k
RC
-- r" -.. c
- -·- - GND
CLK SCL

CLKEN CLK

@PINLIST

RC

B·

CLK

B;

Cl.KEN

I;

@LOGIC EQUATIONS

CLK.OW

=CI.KEN

RC.OE

=CLK*CLKEN;

RC

=GND;

CLK

=RC;

GND
Figure 6. Oscillator

SCL

D SCLFF1

AST CLK RESET

Figure 7. SCL Timing Diagram SCL Edge Detection

SCLH

@PINLIST

SCL

I;

CLK

B;

RESET

I;

@LOGIC EQUATIONS

SCLFFl.D

=SCL;

AST

SCLFFl.RST

=RESET;

SCLL

SCLFF2.D

=SCLFFl;

SCLFF2.RST

=RESET;

SCLH

=SCLFFl*/SCLFF2;

SCLL

=/SCLFFl*SCLFF2;

Figure 8. SCL Edge Detection

Philips Semiconductors Programmable Logic Devices
12C bus expander

Applicatio!1 Note
AN036

SCL

D

STARTFF

START FF

SDA

RST

D
STOPFF

STOPFF

RST
RESET 19-'----..____...J

@PDILIST

SCL

r

SDA

B

RESET

r

@LOGIC EQOATIOllS

STARTFF.CLK =/SDA;

STARTFF.D

=SCL;

STARTFF.RST =RESET;

STOPFF.CLIC

=SDA;

STOPFF.D

=SCL;

STOPFF.RES

=RESET;

Figure 9. Start/Stop Detection

12C-BUS SLAVE TRANSMITTER FUNCTION
The Slave Transmitter design provides remote input expansion for our Philips microcontroller families via the two-line serial bidirectional 12C-Bus. The 12c-Bus slave address is equal to the address of the PCF8574 (remote 8-bit 1/0 expander). The design will only acknowledge the read-mode.
The design handles the full slave read mode of the 12C-Bus and will generate the control signals for the 74HC165, an 8-bit parallel-in I serial-out shiftregister. This device is used to read the parallel input data and convert this into serial data. This data is written to the 12C-Bus. The total number of 74HC165 devices is almost unlimited.
With the three address selection inputs, the slave transmitter can be combined with multiple PCF8574 devices.
The design has a build-in clock oscillator. The section entitled Oscillator describes this circuit. If an external clock is required, the internal oscillator can be inhibited with the CLKEN-input.
Figure 17, Slave Transmitter EON File Figure 18, Slave TransmitterSCL File 'and Figure 19, Slave Transmitter PIN File.'give the design files. The sections SDA Control Slave Transmitter, 12c-Bus protocol Slave Transmitter and Interface with 74HC165 give a detailed description of parts of the design.
SDA Control Slave Transmitter
The SDA data line of the 12c-bus is a bidirectional line with a passive pull-up. This asks for a bidirectional open collector 110 line. As the PLC42VA 12 has only 3-State I/Os, we need one of the advantages of the PLC42VA 12 to get an open collector output.

IN a PLC42VA12 each OE-input can be used as a logic input. With a LOW level (ground) at the input, the output has a LOW level when OE is true and is floating when OE is false. These are the characteristics of an open collector output.
Only one AND-gate controls the OE input of a bidirectional 1/0. The design asks for multi-level logic. Figure 1OSDA Control Slave
Transmitter shows how this input can be
controlled by multi-level logic. The inputs ACKNOW, DATIN and SDAIN are auxiliary outputs of the PLC42VA 12, used as inputs of the SDA control.
12c-eus protocol Slave Transmitter
The section entitled Formats describes the general data formats of the 12c-Bus protocol. Figure 11 12C-Bus Protocol Slave Transmitter gives the protocol for this design. After a start condition, the master sends the slave address of the device. This 7 bits address consists of a fixed part and a programmable part. The first four bits are fixed (0100) and the three least significant bits are programmable. Three hardware address pins determine the final slave address. Up to 8 devices (or PCF8574) may be addressed by the master. After the slave address and a HIGH R/WN bit, the slave generates an acknowledge. At the next LOW SCL, the slave may start sending the first data byte. This byte will be acknowledged by the master. Also the next bytes will be acknowledged by the master. As after the acknowledge pulse the slave controls the SDA-line, the master can not generate a stop condition. The only way for a master to terminate a transmission, is not to acknowledge the last byte n. Then, the slave

transmitter will release the SDA-line and the master can generate a stop condition.
Interface with 74HC165
The 74HC/HCT165 is an 8-bit parallel load or serial-in shift register with complementary serial outputs (07 and 07N) available from the last stage. When the parallel load (PLN) input is LOW, parallel data from the DO to 07 inputs are loaded into the register asynchronously. When PLN is HIGH, data enters the register serially at the OS input and shifts one place to the right with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the 07 output to the OS input of the succeeding stage.
The CLOUT output of the PLC42VA 12 controls the clock of the 74HC 165 and the PLOADN output controls the PLN input. The 07 output of the 74HC165 is the data input DATIN of the PLC42VA12.
With this setup, the most significant bit of the data is the first bit that will be sent from the slave to the master. Figure 11 12C-Bus Protocol Slave Transmitter gives the timing diagram of this interface.
When the slave address and the read bit have been detected, the controller generates the parallel load pulse PLOADN. After sending the firs bit (most significant bit of the transmission) ii generates the first shift pulse CLOCKOUT. At the end of the first byte, the master generates an acknowledge. The second byte starts with a shift pulse CLOCKOUT. Al each next LOW SCL level, this pulse is repeated. If at the end of the byte the master sends an acknowledge, then the next byte will be sent. A not acknowledge stops the procedure.

October 1993

Philips Semiconductors Programmable Logic Devices
12c bus expander

Application Note
AN036

·SDA GND

ACKHOW

@PINLIS'l'

SDA

B;

ACKHOW

I;

DATIN

I;

SDAEN

O;

SDJIOE

O;

@LOGIC EQUA'l'IONS

SDA

=GND;

SDA.OE

=SDJIOE;

SDJIOE

=JICIQIOW+

(/DA'l'IN*SDAEN)

Figure 10. SDA Control Slave Transmitter

Adcheeframm·lar

DatafromolaV9

I I ;, : I I : : : s o: o: A2: A1: AO;, A

DA~A1 : : :

LStartconditlon

·1·~ LAdmowledgefromola·

O...fromllove

AI : : : ~jlA": : : I I1 p I

L Actmowledgefrommu"" .

~

Nat act<MW!edge from maater end of 1rarwm1Hion.

Stop-on

Figure 11. 12c-bua Protocol Slave Transmitter

Figure 12. Interface with 74HC165

694

Philips Semiconductors Programmable Logic Devices
12c bus expander

Application Note
AN036

12c-eus SLAVE RECEIVER FUNCTION
The slave receiver design provides remote output expansion for our Philips micro controller families via the two-line serial bidirectional 12C-bus. The 12C-bus slave address is equal to the address of the PCF8574 (remote 8-bit 110 expander). The design will only acknowledge the write-mode.
The design handles the full slave write mode of the 12C-Bus and will generate the control signals for the 74HC595, an 8-bit serial-in I parallel-out shiftregister. This device is used to write the serial from the 12C-bus input to, and convert this into parallel data. The total number of 74HC595 devices is almost unlimited.
With the three address selection inputs, the
slave receiver can be combined with multiple
PCF8574 devices.
The design has a build-in clock oscillator. The section entitled Oscillator describes this circuit. If an external clock is required, the internal clock can be inhibited with the

CLKEN-input. Figure 20, Slave Receiver EON File, Figure 21, Slave Receiver SCL File, and Figure 22, Slave Receiver PIN File give the design files. The sections SDA Control Slave Receiver, Set-Reset Flip-Flop, 12c-Bus protocol Slave Receiver and Interface with 74HC595 give a detailed description of parts of the design.
SDA Control Slave Receiver
In the Slave Receiver protocol of the 12C-Bus, mainly the master controls the SDA-line. The Slave Receiver uses the SDA-line only for generating an acknowledge pulse. This is done after receiving its slave address with a write condition and all the following data bytes. Figure 13, SDA Control Slave Receiver gives the diagram and the description of the EON-file.
Set-Reset Flip-Flop
The PLC42VA 12 has 10 internal flip-flops. As the design needs an additional 0-latch, this one has to be built out of gates. Figure 14, Set-Reset Flip-Flop Slave Receiver, gives the diagram and the equation file description of

this function. In this example the signal ST07 is defined as an input, but in the final design this is a auxiliary output of the device.
12c-eus protocol Slave Receiver
The section entiUed Formats describes the general format of the 12C-Bus protocol. Flgure 14, Set-Reset Flip-Flop Slave Receiver, gives the protocol tor this design. After a start condition, the master sends the slave address of the device. This 7 bits address consists of a fixed part and a programmable part. The first tour bits are fixed (0100) and the three least significant bits are programmable. Three hardware address pins determine the final slave address. Up to 8 devices (or PCF8574) may be addressed by the master. After the slave address and a LOW R/WN bit, the slave generates an acknowledge. At the next LOW SOL, the master starts sending the first data byte. This byte will be acknowledged by the slave. Also the next bytes will be acknowledged by the slave. The master terminates a transmission, by sending a stop condition or a restart condition.

ACKNOW

@.PINLIST

SDA

B;

AClQIOW

I;

@LOGIC EQUATIONS

SDA

=GHD;

SDA. OE

=ACK!IOW

SDA ST07

Figure 13. SDA Control Slave Receiver

DATA7

@PIHLIST

SDA

B

ST07

I

DATA?

0

@LOGIC EQUATIONS DATA?= ((ST07*SDA)+
(DATA7*/ST07))

Figure 14. Set-Reset Flip-Flop Slave Receiver

October 1993

695

Philips Semiconducto~ Programmable Logic Devices
12c bus expander

Application Note
AN036

Interface with 74HC595
The 74HC/HCT595 is an 8-stage serial shift register with a storage register and 3-State outputs. The shift register and storage register have separate clockS.
Data is shifted on the positive-going transitions of the SHCP input. The data in each register transfers to the storage register on a positiw going transition of the STCP input. The shift register has a serial input (OS) and a serial standard output (07 ) for cascading. All 8 shift registers have an asynchronous reset (active LOW). The storage register has 8 perallel 3-State bus driver outputs. Data in the storage registers at the output whenever the output enable input (OEN) is LOW.
Four outputs of the PLC42VA12 control the inputs of the 74HC595. The RESOUT output the MRN input, CLKSTO the .STCP input, CLKSHFT the Sl:ICP and the DATOUT the OS input.
The 12c.eus sends first the most significant bit of the transmission. Figure 1612C-Bus

Interface with 74HC595 gives the timing diagram of this interface.
To set all outputs of the 74HC595 to a defined level, after power-on, the controller generates first a reset pulse at the RESOUT output and then a clock pulse CLKSTO for the storage register.
After a the slave address and the write bit (LOW) have been detected, during the next HIGH period of the SCL line there are three options. At the SDA line there can be the most significant bit of new data, the master generates a restart condition or the master generates a stop condition. This is also the case alter each acknowledge.
This implies, that this first data bit must be stored. At the next LOW period of the SCL line we know whether we had data or restart/stop condition. If it was data, then we have to put this data at the DATOUT output and generate a clock pulse at the CLKSHFT output. At the next 7 HIGH periods of the

SCL-line, data is valid and the controller generates a clock at the CLKSHFT output.At the end of the transmission, the master generates a stop condition or a restart. Then the stored data will be.transferred to the storage register by a clock pulse at the CU<STO output.
BREAD·BOARD 12c-eus 110
EXPANDER
For design verification purposes, a bread-board has been designed. The board contains all the devices to build an 12C-Bus Slave Transmitter with 32 inputs and an 12C-Bus Slave Receiver with 32 outputs. The inputs can be set HIGH or LOW by 4 octal DIP-switches. The outputs are examined by 32 LED's: Figure 23, Schematic Diagram Bread-Board, gives the complete diagram of the bread-board.
The board has been designed for design verification only.

Adcheslrom-

Detafrommutar

Data from muter

;a: s I : : o A2: Al: M: OI AI : : : D+A1 : : : I AI : : : +TAn: : : I AI PI L__ .lL___ L___ J I
~ Not acknowledge from slave
Stop condillon end of tronamloalon
Figure 15. 12C-bus Protocol Slave Receiver

Figure 16. Interface with 74HC595 696

Philips Semiconductors Programmable Logic Devices
12C bus expander

***************************************************

*

*

*

Equation Entry File

*

*

* Project

IIC

*

* Function

I IC-bus Slave Transmitter

*

*

*

* File Name

IICTRANS.EQN

*

* Design file IICTRANS.SCL

*

* Pin File

IICTRANS .PIN

*

*

*

* Date

March 1993

*

* Designer

Aloys Schatorj

*

* Company

Philips Semiconductors

*

* Department PCALE

*

* Place

Eindboven

*

* Country

The Netherlands

*

*

*

***************************************************

@PINLIST

CLK

B;

RC

B;

CLKEN

I;

SCL

I;

SDA

B;

RESET

I;

ADDO

I;

ADDl

I;

ADD2

I;

DATIN

I;

CLOCKOUT O;

PLOADN O;

SDAOE

O;

SDAEN

O;

ACKNOW O;

STATEST O;

"System clock" "RC input internal clock" "Clock selection input" "IIC-BUS clock" "IIC-BUS data" "System reset" "Address selection line" "Address selection line" "Address selection line" "Data from input shift-register" "Clock to input shift-register" "Parallel load to input shift-register" "Enable line SDA I/0" "Enable condition SDA caused by data" "Acknowledge data" "Reset start and stop FF"

@GROUPS

@TRUTHTABLE

@LOGIC EQUATIONS

CLK.OE

CLKEN

RC.OE

CLK*CLKEN;

RC

GND

CLK

RC

STARTFF.CLK /SDA

STARTFF.D

SCL

STARTFF.RST STATEST

SCLFFl.D

SCL

SCLFFl.RST

RESET

SCLFF2.D

SCLFFl

SCLFF2.RST

RESET

SCLH

SCLFF1*/SCLFF2

SCLL

/SCLFFl*SCLFF2

QO.RST

RESET

Ql.RST

RESET

Q2.RST

RESET

Q3.RST

RESET

Q4.RST

RESET

QS.RST

RESET

SDA

GND

SDA.OE

SDAOE

PLOADN

/PLOAD

SDAOE

ACKNOW + (/DATIN*SDAEN)

OctohAr 1Oct~

Figure 17. Equation Entry File Slave Transmitter (1 of 3)

Application Note
AN036

Philips Semiconductors Programmable Logic Devices
12C bus expander

Application Note
AN036

@INPUT VECTORS

@OUTPUT VECTORS

[ACKNOW,

ACK

l

CLKOUT

SDAENA

PLOUT

CLOCKOUT, l

PLOAD, l

SDAEN) B
l B l B l B

@STATE VECTORS

[QS, Q4, Q3, Q2, Ql, QO] JKFFR

INITL

00 H;

!NIT

3F H;

WAIT

3E H;

WAITl

30 H;

ADDBIT6

Ol H;

ADDBITS

02 H;

ADDBIT4

03 H;

ADDBIT3

04 H·

ADDBIT2

05 H;

ADDBITl

06 H·

ADDBITO

07 H·

RWBIT

08 H·

READ MOD

09 H;

ACKBITR

OA H;

READ7L

OB H;

READ7C

lO H;

READ?

ll H;

READ6C

12 H;

READ6

13 H·

READ SC

14 H;

READS

15 H;

READ4C

16 H·

READ4

17 H;

READ3C

18 H;

READ3

19 H;

READ2C

lA H;

READ2

lB H;

READlC

lC H;

READl

lD H·

READOC

lE H;

READO

lF H;

ACKPLS

20 H·

ACKPLSW

21 H·

@TRANSITIONS

WHILE [INITL)

IF []

THEN [!NIT)

WHILE [INIT)

IF [)

THEN [WAIT)

WHILE [WAIT]

WITH

IF [STARTFFJ THEN [WAITl]

WHILE [WAITl]

WITH

IF [)

THEN [ADDBIT6]

WHILE [ADDBIT6]

IF [SCLH*SDA) THEN [WAIT)

IF [SCLH*/SDA) THEN [ADDBITS]

WHILE [ADDBITS]

IF [SCLH*/SDA) THEN [WAIT]

IF [SCLH*SDA) THEN [ADDBIT4]

WHILE [ADDBIT4]

IF [SCLH*SDA] THEN [WAIT]

IF [SCLH*/SDA) THEN [ADDBIT3)

WHILE [ADDBIT3)

IF [SCLH*SDA) THEN [WAIT]

IF [SCLH*/SDA] THEN [ADDBIT2)

WHILE [ADDBIT2]

IF

[SCLH*/((SDA*ADD2)+(/SDA*/ADD2))] THEN

IF

[SCLH*((SDA*ADD2)+(/SDA*/ADD2))) THEN

[STATEST) [STATEST]
[WAIT] [ADDBITl]

Figure 17. Equation Entry File Slave Transmitter (2 of 3)

Philips Semiconductors Programmable Logic Devices
12c bus expander

Application Note
AN036

WHILE
WHILE
WHILE
WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE
WHILE

[ADDBITl]

IF

[SCLH*I ( (SDA*ADDl) + (/SDA*/ADDl) ) l THEN

IF

[SCLH*((SDA*ADDl)+(/SDA*/ADDl))] THEN

[ADDBITO]

IF

[SCLH*/ ( (SDA*ADDO)+(/SDA*/ADDO))] THEN

IF

[SCLH*((SDA*ADDO)+(/SDA*/ADDO))] THEN

[RWBIT]

IF

[SCLH*SDA] THEN [READMOD]

IF

[SCLH*/SDA] THEN (WAIT]

[READMOD]

IF

[SCLL]

THEN [ACKBITR]

[ACKBITR]

WITH

IF

[SCLL]

THEN [READ7L]

[READ7L]

WITH

IF

[]

THEN [READ7]

[READ7C]

WITH

IF

[]

THEN [READ7]

[READ7]

WITH

IF

[SCLL]

THEN [READ6C]

[READ6C]

WITH

IF

[]

THEN [READ6]

[READ6]

WITH

IF

[SCLL]

THEN [READSC]

[READSC]

WITH

IF

[]

THEN [READS]

[READS]

WITH

IF

[SCLL]

THEN [READ4C]

[READ4C]

WITH

IF

[]

THEN [READ4]

[READ4]

WITH

IF

[SCLL]

THEN [READ3C]

[READ3C]

WITH

IF

[]

THEN [READ3]

[READ3]

WITH

IF

(SCLL]

THEN [READ2C]

[READ2C]

WITH

IF

[]

THEN [READ2]

[READ2]

WITH

IF

[SCLL]

THEN [READlC]

[READlC]

WITH

IF

[]

THEN [READl]

[READl]

WITH

IF

[SCLLJ

THEN [READOC]

[READOC]

WITH

IF

[]

THEN [READO]

[READO]

WITH

IF

[SCLL]

THEN [ACKl?LS]

[ACKl?LS]

IF

[SCLH*/SDA] THEN [ACKl?LSW]

IF

[SCLH*SDA] THEN [WAIT]

[ACKPLSW]

IF

[SCLL]

THEN [READ7C]

[WAIT] [ADDBITO] [WAIT] [RWBIT]
[ACK] [!?LOUT] [CLKOUT] [SDAENA] [CLKOUT] [SDAENA] [CLKOUT] [SDAENA] [CLKOUT] [SDAENA] [CLKOUT] [SDAENA] [CLKOUT] [SDAENA] [CLKOUT] [SDAENAJ [CLKOUT] [SDAENA]

Figure 17. Equation entry file slave transmitter (3 of 3)

October 1993

Philips Semiconductors Programmable Logic Devices
12c bus expander

Application Note
AN036

***************************************************

*

*

*

Simulation Control Language File

*

*

*

*Project

IIC

*

* Function

!IC-bus Slave Transmitter

*

*

*

* File Name

IICTRANS.SCL

*

* Design fil.e IICTRANS.EQN

*

* Pin File

IICTRANS.PIN

*

*

*

* Date

March 1993

*

* Designer

Al.oys Schatorj

*

* Company

Phil.ips Semiconductors

*

* Departiqent

PCALE

*

* Place

Eindhoven

*

* Country

T,he Netherlands

*

*

***************************************************

*
P CL!t, RESET, SCL, SDA, DATIN, SDAEN, CLOCKOUT, PLOADN, ACKNOW,

# STARTFF, STATEST, QO, Ql., Q2, Q3, Q4,

# RC, CI.KEN, ADDO, ADDl., ADD2, VCC
* SCLH, SCLL,

PCO
*** Initialisation ***

BUSI SDA

BUSICLK

BUSO RC

S 0 (50, 1.00, ETC)CLK

S 0 (75)RBSET

S 0 (500, 1.000, ETC)SCL

ST 1. (DATIN)

ST 1. (VCC)

ST 1 (SDA)

ST 0 (CI.KEN)

ST 001. (ADD2, ADDl., ADDO)

SU TIME = 1.225

*** Generate start condition ***
ST 1. (SDA) SU TIME = *+500
ST 0 (SDA)
SU TIME = *+500

*** receive device address with read (01.00001.1.) . *** ST 0 (SDA)
SU TIME = *+l.000
ST 1. (SDA)
SU TIME = *+l.000
ST 0 (SDA)
SU TIME = *+4000
ST 1. (SDA)
SU TIME = *+2000
*** Generate acknowledqe from slave ***
BUSO SDA SU TIME = *+l.000

*** Transmit 8 bits data word l.1.1.1.1.1.1.l. *** ST 1. (DATIN) SU TIME = *+8000
*** Generate acknowledqe from master ***
BUSI SDA
= ST 0 (SDA)
SU TIME *+l.000

Figure 18··SCL File Slave Transmitter (1 of 2)

Philips Semiconductors Programmable Logic Devices
12c bus expander

Application Note
AN036

*** Transmit 8 bits data word 11001100 *** BOSO SDA
= ST 1 (DATIN)
SO TDIB *+2000
= ST 0 (DATIN)
SO TDIB *+2000
= ST 1 (DATIN)
SO TDIB *+2000
= ST 0 (DATill)
SO TDIB *+2000
*** Generate no acknowledge from master (end of transmition) ***
BOSI SDA
= ST 1 (SDA)
SO TDIB *+1000
= *** Wait for new start condition *** SO TIME *+3000
*** Generate new start condition ***
= ST 1 (SDA)
SO TDIB *+500
= ST 0 (SDA)
SO TDIB *+500
*** receive device address with write (01000010) · *** ST 0 (SDA) SO TIME = *+1000
= ST 1 (SDA)
SO TIME *+1000
= ST 0 (SDA)
SO TDIB *+4000 ST 1 (SDA)
= SO TIME *+1000 = ST 0 (SDA)
SO TIME *+1000
*** Wait for new start condition ***
SO TIME = *+3000
*** Generate new start condition *** ST 1 (SDA)
so TIME = *+500
ST 0 (SDA)
so TDIB = *+500
***Receive wrong device address (0110000). *** ST 0 (SDA) S11 TIME = *+1000 ST 1 (SDA) SO TIME = *+2000
= ST 0 (SDA)
SO TDIB *+6000
*** Test internal clock ***
BOSO CLIC, RC ST 1 (CLIC)
= ST 1 (CI.KEN)
SO TDIB *+ 1000
F
Figure 18..SCL File Slave Transmiller (2 of 2)

October 1993

Philips Semiconductors Programmable Logic Devices
12c bus expander

***************************************************

*

*

*

Pinning File

*

*

*

* Project

IIC

*

* Function

IIC-bus Slave Transmitter

*

*

*

* File Name

IICTRANS.EQN

*

* Design file IICTRANS.SCL

*

* Pin File

IICTRANS .PJJI

*

*

*

*Date

March 1993

*

* Designer

Aloys Schatorje

*

* Company
* Department

Philips Semiconductors PCJILE

*
*

* Place

Eindhoven

*

*Country

The Netherlands

*

*

*

*********************************.******************

Device Pin2
Pin3 Pin4 Pins
Pin8 Pin9 PinlO Pinll Pinl4 PinlS Pinl8
Pinl9 Pin20 Pin21
Pin22 Pin23

=C42VA12
=RESET =ADDO =ADDl =ADD2 =CLI<EN =SCL =SDA =CLOCKOUT
=CLK =RC =DATJJI =ACKNOW =SDAOE =SDAEN =STATEST =PLOADN

Figure 19··PIN Fiie Slave Transmitter

Application Note
AN036

Philips Semiconductors Programmable Logic Devices
12c bus expander

October 1993

***************************************************

*

*

*

Equation Entry Fila

*

*

*

* Project

IIC

*

* Function

IIC-bus Slave Reaei.ver

** File Name * Design fila * Pin File

IICRECEI.EQH IICRECEI.SCL IICRECEI .PIH

* * * *

** Date * Designer * Company

March 1993 Aloys Schatorj Philips Semiconductors

* * *

* Department

PCALE

*

* Place

Eindhoven

*

* Country

The Netherlands

*

*

*

***************************************************

@PIHLIST

CLK

B;

RC

B;

CI.KEH

I;

SCL

I;

SDA

B;

RESET

I;

ADDO

I;

ADDl

I;

ADD2

I;

CLitSllFT 0;

CLitSTO O;

DATOUT O;

DATA7

O;

ST07

O;

OUT7

O;

RESOUT O;

ACKllOW O;

STATEST O;

"System clock" "RC input internal clock" "Clock selection input" "IIC-BUS clock" "IIC-BUS data" "System reset" "Address selection linew "Address selection linen "Ad.dress selection line" "Clock to output shift-register"
"Parallel load into output register" "Data to output shift register" "Output data RSFF bit7" "Stora pulse DATA7 FF" "Enable DATA7 FF data" "Reset output shift register" "Acknowledge data" "Reset start and stop FF"

@GROUPS

@TROTHTABLE

@LOGIC EQUATIONS

CLK.OE

CI.KEH

RC.OE

CLit*CLKEH;

RC

GHD

CLK

RC

STARTFF.CLK /SDA

STARTFF.D

SCL

STARTFF.RST STATEST

STOPFF.CLK

SDA

STOPFF.D

SCL

STOPFF.RST

STATEST

SCLFFl.D

SCL

SCLFFl.RST

RESET

SCLFF2.D

SCLFFl

SCLFF2.RST

RESET

SCLH

SCLFF1*/SCLFF2

SCLL

/SCLFFl*SCLFF2

DATA7

((ST07*SDA)+DATA7*/ST07)

QO.RST

RESET

Ql.RST

RESET

Q2.RST

RESET

Q3.RST

RESET

Q4.RST

RESET

QS.RST

RESET

SDA SDA.OE DATO OT RES OUT

GHD ACKllOW (SDA*/OUT7) + (DATA7*0UT7) /RESOUTH ;

Figure 20. Equation Entry File Slave R-lver (1 of 3)

70::1

Application Note
AN036

Philips Semiconductors Programmable Logic Devices
12c bus expander

Application Note
AN036

@DIPU! VECTORS

IOU!PU! VECTORS

- =[CLKSBFT, CLICS!O, RBSOtrnl, STA!EST, S!07, 00!7]

CLKSBIFT 1

B;

CLKS!OR =

1

1

B;

JIBSO

1

1

B;

HATS!

1

B;

S!AS!07

1

1

B;

OUDI!7

1 B;

OUTCLK7

1

1 B;

@STATE VECTORS

[Q5, Q4, Q3, Q2, Ql, QO] .:nai'FR

IJII!L

= 00 B;

IllI!

31!' B;

IllITl

3E B;

IJIIT2

= 3D B;

WAIT

= 3C B;

WAITl ADDBIT6 ADDBIT5
ADDBIH

- 3B B;
= 01 B; 02 B;
03 B;

ADDBI!3 = 04 B;

ADDBIT2

05 B;

ADDBITl

06 B;

ADDBITO RWBI!
WRIDMOD

-= 07 B;
= 08 B; 09 B;

ACKBI!!R

OA B;

- TESTS!A = OB B;

TESn!Al

OC B;

TESTS!A2 = OD B;

OUTB7

= OE B;

CLKB7
WRID6 WRID6C

- 01!' B; 10 B; 11 B;

WRID5 WRID5C

"

12 B; 13 B;

WRID4

= 14 B;

WRID4C = 15 B;

WRID3

= 16 B;

WRID3C

17 B;

WRID2

= 18 B;

WRID2C

19 B;

WRIDl

= 1A B;

WRIDlC WRIDO WRIDOC

-= 1B B; lC B; lD B;

I TRANSITIONS

WHILE [IllITL]

IF

[]

WHILE [IllIT]

II!'

[]

WHILE [INIU]

IF

[]

WHILE [IllIT2]

II!'

[]

WHILE [WAI!]

IF [STARTl!'l!']

WHILE [WAIU]

IF []

WHILE [ADDBIT6]

II!' [SCLB*SDA]

IF [SCLB*/SDA]

WHILE [ADDBIT5]

II!' [SCLB*/SDA]

II!' [SCLH*SDA]

!BEN
THEN
THEN
THEN THEN
THEN THEN THEN
THEN THEN

[IllIT]
[INIU] [IJII!2]
[WAIT] [11AIU]
[ADDBIT6] [WAIT] [ADDBI!5]
[WAIT] [ADDBI!4]

WITH [RBSO] WI!B [CLICSTOR] WITH [S!ATST] WITH [STATS!]

Figure 20. Equation Entry Fiie Slave Receiver (2 of 3) 704

Philips Semiconductors Programmable Logic Devices
12c bus expander

liHILE
liHILE
liHILE
liHILE
liHILE
liHILE
liHILE WHILE WHILE liHILE liHILE
WHILE liHILE liHILE liHILE liHILE liHILE liHILE liHILE liHILE liHILE liHILE liHILE WHILE liHILE WHILE WHILE

[ADDBIT4]

IF

[SCLH*SDA] THEN [WAIT]

IF

[SCLH*/SDA] THEN [ADDBIT3]

[ADDBIT3]

IF

[SCLH*SDA] THEN [WAIT]

IF

[SCLH* /SDA] THEN [ADDBIT2]

[ADDBIT2]

IF

[SCLH*/((SDA*ADD2)+(/SDA*/ADD2))] THEN

IF

[SCLH*((SDA*ADD2)+(/SDA*/ADD2))] THEN

[ADDBITl]

IF

[SCLH*/((SDA*ADDl)+(/SDA*/ADDl))] THEN

IF

[SCLH*((SDA*ADDl)+(/SDA*/ADDl))] THEN

[ADDBITO]

IF

[SCLH*/((SDA*ADDO)+(/SDA*/ADDO))] THEN

IF

[SCLH*((SDA*ADDO)+(/SDA*/ADDO))] THEN

[RWBIT]

IF

[SCLH* /SDA] THEN [WRIDMOD]

IF

[SCLH*SDA] THEN [WAIT]

[WRIDMOD]

IF

[SCLL]

THEN [ACKBITTR]

[ACKBITTR]

WITH

IF

[SCLL]

THEN [TESTSTA]

[TESTSTA]

WITH

IF

[SCLH]

THEN [TESTSTAl]

[TESTSTAl]

WITH

IF

[]

THEN [TESTSTA2]

[TESTSTA2]

WITH

IF

[STARTFF]

THEN [INIT2]

IF

[STOPFF]

THEN [INIT2]

IF

[SCLL]

THEN [OUTB7]

[OUTB7]

WITH

IF

[]

THEN [CLKB7]

[CLKB7]

WITH

IF

[ l

THEN [WRID6]

[WRID6]

IF

[SCLH]

THEN [WRID6C]

[WRID6C]

WITH

IF

[]

THEN [WRIDS]

[WRIDS]

IF

[SCLH]

THEN [WRIDSC]

[WRIDSC]

WITH

IF

[ l

THEN [WRID4]

[WRID4]

IF

[SCLH]

THEN [WRID4C]

[WRID4C]

WITH

IF

[]

THEN [WRID3]

[WRID3]

IF

[SCLH]

THEN [WRID3C]

[WRID3C]

WITH

IF

[ l

THEN [WRID2]

[WRID2]

IF

[SCLH]

THEN [WRID2C]

[WRID2C]

WITH

IF

[]

THEN [WRIDl]

[WRIDl]

IF

[SCLH]

THEN [WRIDlCJ

[WRIDlC]

WITH

IF

[]

THEN [WRIDO]

[WRIDO]

IF

[SCLH]

THEN [WRIDOC]

[WRIDOC]

IF

[ l

THEN [WRIDMOD]

WITH

[WAIT] [ADDBITl] [WAIT] [ADDBITO] [WAIT] [RWBIT]
[ACKNOW] [STATST] [STAST07] [STATST]
[OUTBIT7] [OUTCLK7]
[CLKSHIFT]
[CLKSHIFT]
[CLKSHIFT]
[CLKSHIFT]
[CLKSHIFT]
[CLKSHIFT]
[CLKSHIFT]

Application Note
AN036

October 1993

Figure 20. Equation Entry File Slave Receiver (3 of 3) 705

Philips Semiconductors Programmable Logic Devices
12C bus expander

Application Note
AN036

***************************************************

*

*

*

Simulation Control Language File

*

*

*

* Project

IIC

*

*Function

IIC-bus Slave Receiver

*

*

* File Name

IICRECEI.SCL

*

* Design file IICRECEI .EQN

*

* Pin File

IICRECEI.PIN

*

*

*

*Date

March 1993

*

* Designer

Aloys Schatorj

*

* Company

Philips Semiconductors

*

* Department * Place * Country

PCALE
Eindhoven The Netherlands

* *
*

*

*

***************************************************

P CL!t, RESET, SCL, SDA, DATOUT, CLKSHFT, CLKSTO, RESOUT, ACKNOW,

# STATEST, DATA7, OUT7, ST07, STARTFF, STOPFF, QO, Ql, Q2, Q3, Q4, Q5,

# RC, CLKEN, ADDO, ADDl, ADD2, VCC
* SCLH, SCLL,

PCO
*** Initialisation ***
BUSI SDA

BUSI CLK

BUSO RC

S 0 (50, 100, ETC)CLK

S 0 (75)RESET

S 0 (500, 1000, ETC)SCL

ST 1 (VCC)

ST 1 (SDA)

ST 0 (CLKEN)

ST 001 (ADD2, ADDl, ADDO)

SU TIME = 1225

*** Generate start condition *** ST 1 (SDA)
SU TIME = *+500
ST 0 (SDA)
SU TIME = *+500

*** receive device address with write (01000010) *** ST 0 (SDA) SU TIME = *+1000
ST 1 (SDA)
SU TIME = *+1000
ST 0 (SDA)
SU TIME = *+4000
ST 1 (SDA)
SU TIME = *+1000
ST 0 (SDA)
SU TIME = *+1000
Generate acknowledge from slave ***
BUSO SDA
SU TIME = *+1000

*** Receive 8 bits data word 11111111 *** BUSI SDA ST 1 (SDA) SU TIME = *+8000
*** Generate acknowledge from slave ***
BUSO SDA
SU TIME = *+1000

t'\.-.t,..hor 1QQ~

Figure 21 ··SCL file slave receiver (1 of 3) 706

Philips Semiconductors Programmable Logic Devices
12c bus expander

October 1993

*** Receive 8 bits data word 11001100 ***
BUSI SDA ST 1 (SDA)
SU TIME = *+2000
ST 0 (SDA)
= SU TIME *+2000
ST 1 (SDA)
= SU TIME *+2000
ST 0 (SDA) SU TIME = *+2000
*** Generate acknowledge from slave ***
BUSO SDA
= SU TIME *+1000 *** Receive 8 bits data word 01110001 ***
BUSI SDA ST 0 (SDA)
SU TIME = *+1000
ST 1 (SDA) SU TIME = *+3000 ST 0 (SDA) SU TIME = *+3000 ST 1 (SDA) SU TIME = *+1000
*** Generate acknowledge from slave ***
BUSO SDA
SU TIME = *+1000
*** Generate new start condition ***
BUSI SDA ST 1 (SDA)
= SU TIME *+500
ST 0 (SDA) SU TIME = *+500
*** receive device address with read (01000011) *** ST 0 (SDA)
= SU TIME *+1000
ST 1 (SDA)
= SU TIME *+1000
ST 0 (SDA)
= SU TIME *+4000
ST 1 (SDA)
= SU TIME *+2000
= *** Wait for new start condition *** SU TIME *+3000
*** Generate new start condition ***
ST 1 (SDA) SU TIME = *+500 ST 0 (SDA) SU TIME = *+500
*** receive device address with write (01000010) *** ST 0 (SDA)
= SU TIME *+1000
ST 1 (SDA)
= SU TIME *+1000
ST 0 (SDA)
= SU TIME *+4000
ST 1 (SDA)
= SU TIME *+1000
ST 0 (SDA)
= SU TIME *+1000
*** Generate acknowledge from slave ***
BUSO SDA
SU TIME = *+1000
Figure 21.·SCL File Slave Receiver (2 of 3)
707

Application Note
AN036

Philips Semiconductors Programmable Logic Devices
12c bus expander

nrtnhor 1 QQ~

*** Generate stop condition ***
ST 0 (SDA) SU TIME = *+500 ST 1 (SDA) SU TIME = *+500 *** Wait for new start condition *** SU TIME = *+3000 *** Generate new start condition *** ST 1 (SDA) SU TIME = *+500 ST 0 (SDA) SU TIME = *+500 *** receive wrong device address (0110000). *** ST 0 (SDA)
SU TIME = *+1000
ST 1 (SDA) SU TIME = *+2000 ST 0 (SDA) SU TIME = *+6000
*** Test internal clock ***
BUSO CLK, RC ST 1 (CLK) ST l (CI.KEN) SU TIME = *+ 1000 F
Figure 21.·SCL File Slave Receiver (3 of 3)

***************************************************

*

*

*

Pinning File

*

*

*

* Project

IIC

* Function

IIC-bus Slave Receiver

*

*

*

* File Name

IICRECEI.SCL

*

* Desiqn file IICRECEI .EQN

*

* Pin File

IICRECEI.PIN

*

*

*

* Date

March 1993

*

* Designer

Aloys Schatorje

*

* Company

Philips Semiconductors

*

* Department PCALE

*

* Place

Eindhoven

*

* Country

The Netherlands

*

*

*

***************************************************

Device Pin2 Pin3 Pin4 Pins Pin8 Pin9 PinlO Pinll Pinl4 Pin15 Pinl6 Pinl7 Pinl8 Pinl9 Pin20 Pin21 Pin22 Pin23

=C42VA12 =RESET =ADDO =ADDl =ADD2 =CI.KEN =SCL =SDA =CLKSHFT =CLK =RC =DATOUT =CLKSTO =RESOUT =ACKNOW =OUT7 =DATA7 =STATEST =ST07
Figure 22. .PIN File Slave Receiver

708

Application Note
AN036

~

C"

~

".",,

llC4lus S!ave--Transmltter

vcc

$4 I 1-1 1-1-1 ·1-1-1 ·1 SWDIP-<I VCC

U6

IOICLK

I~

l~·r-t~-"'=~4;-1 ~

I

a c

15

1!12f1 !':!

~

I I

16
~
81

~

aa
~974Hg~65

aa
~ 974Hg~65

I

I

aa

I I

~ 974Hg1ss

I I

~

---- ---

-- ... _..

I

()
aID

--------------------------------------------~

~m r

a2 .

I I

1 10/CLK 11

I

12

I """''--*<WU~~ i!

I

i~

I

11

101

I

::0

I

01

I

~-~.-~.~-.-.~~.·-

A

DO

031

390

VCC

390

~~~~~~c~~------------------------------------------~~~~------J

,,

N .:gr:. (") "'(/)

"' cC" ;3;·

(/) (!)

0
:ac::i.

x
"O Po>
a:::l.
(..!.),

()
,,ff
Ol
cao
iil 3

3

Ill

S!

"b '

'2.

0

0
s"'.
2

"'

i: z)>

-6'
12.

0

(,.)
a>

:::i
z

0

!D

Philips Semiconductors Programmable Logic Devices
ISDN peripheral control

Application Note
AN037

INTRODUCTION
There are currently numerous integrated circuits available for data communication. They are mostly of a high complexity and their functionality covers nearly all requirements for the development of new telecommunication equipment. However, in many cases, the highly specialized communication ICs do not cover the intended product function exactly, and a few, sometimes simple functions remain to be
realized separately. Those extra parts of the
electronics design can often be satisfied by the use of programmable logic circuits,a fact, that shall be demonstrated by this application note.
In order to complete the prototype of a new system board for data transmission, a small controller unit needed to be designed. The functions of this controller is to monitor an incoming serial stream of data bits, indicating certain commands at fixed positions within this bitstream, and to control an output data line in response to these commands.
SPECIFICATION OF THE CONTROLLER FUNCTION
The first function in this controller is that of monitoring an incoming stream of data bits. A general overview of the construction and timing relations of the serial bitstream and associated input control signals is shown in

Figure 1. The understanding of this structure is most important for the specification of the controller design. The serial stream of data bits (via SDI - Serial Data In) is synchronous to the clock signal DCL and one data bit has the length of two clock cycles. The bit stream itself is subdivided into single data words of 32 Bits, whereas the beginning and the length of each data word is indicated by the frame signal FSC.
Given this structure, the first task of the controller is to synchronize itself on the data frame and to isolate the data bits number 27...30. These are the so called command indication bits (C/1- Command Indication in Figure 1) serving for the link and network control between the communicating stations.
The internal function of the desired controller is to evaluate the C/1-Bits and to send the appropriate response on the output data stream. The complete sequence of commands during a transmission session is shown in Figure 2, illustrating the order of incoming commands and corresponding output bit pattern. Accordingly to this graphical specification the controller has to detect the two commands PU (Power Up) and DR (Deactivate Request), and on the output side, it has to drive the line SDO (Serial Data Out) in dependence on these commands.
Basically SDO has a constant level 'Low' after the activation of a communication

session. But if the input command PU is recognized, the controller shall send a respond command ARN (Active Request None Loop) within the following data frames and at the same bit position as the incoming C/1-Bits. The command ARN on the line SDO is to send till the command DR is detected at the input side. The command DR marks the end of a communication session and one Frame after its detection the line SDO is to switch to the deactive signal level ('High') as it is shown in Figure 2.
Beside the elementary fuctionality, some additional constraints need to be observed. First, it should be considered, that the complete design needs to have an asynchronous part. During the period of no communication, no frame and no clock signal is attached at the inputs and the initial change of the line Start demands an immediate acknowledgment before the clock becomes externally activated. So, the
synchronous mode of operation is to extend
with an asynchronous design part. The second constraint was the demand that the incoming data are to read with the HL-edge of the second clock cycle (see Figure 1), while a signal change of the output line is to initiate synchronous with the LH-edge of the system clock. This requirement assures the correct recognition of the incoming data also for long distance transmissions with slow rising signal edges, but therefore the design needs to work with two active clock edges.

START

EXTERNAL ACTIVATION OF A TRANSMISSION SESSKlN
/

FSC

DCL

SDI SDO

CONFIRMATION ACTIVATION

Figure 1. General Structure of the Data Frame and Basic Timing Relations

710

Philips Semiconductors Programmable Logic Devices
ISDN peripheral control
C> ·····'·*·-·b
C> C> C>
········-·- :-
" C> z
-$!

Application Note
AN037

!
I
~...
1"'

1 l
l

j
l
I

i
J
i

~ ii
·l~="

~

I g ...

..J
0 0

.0 ,
u.

i.5,

.00,

I C>

i!

~

J..j! .0, u.

.i5,

.00,

i
! C> ~

j

., J!
I!

0 u.

.C, i

.g,

';;

!J

I
!!:.
. I
II

'5

! 0 f2

C.,i

';;

!J

g.,

October 1993

Figure 2. Command Sequence for a Complete Transmission Session

Philips Semiconductors Programmable Logic Devices
ISDN peripheral control

Application Note
AN037

FUNCTIONAL DESIGN DESCRIPTION
Figure 3 shows a possible approach for the realization of the specified controller function. This block structure contains a cyclic 6-Bit-Counter clocked with DCL and synchronized on the frame signal FSC. Refering to the counter value it is possible to determine the position of Command-Bits within input bitstream and so the decoder block 'Cl_Decod' can derive the appropriate control signals for Read- and Write-Cycles of Data. The signal Cl controls the second essential module, the shift register, via its Enable-Input. The 4-Bit Shift-Register has to read the four Command Bits from the serial bitstream and the following Decoder 'Com_Decod' has just to indicate the two relevant commands, 'PU' and 'DR'. Finally, the real controller is contained within the block 'Control'. There a finite state machine evaluates the 'PU' and 'DR' signals after a new command was read and in correspondence to the actual section of a transmission session the appropriate bit pattern for the output will be generated.

Using this global design description, all

constraints can be satisfied easily while

realizing the complete controller function.

First, the shift-register and the

Controller-module can be clocked with the

inverted and noninverted DCL-pulse and so

different clock edges are taken for the Read-

and Write- Cycle of Data Bits. Furthermore

the asynchronous initialization of the

'

controller is accomplished by the

Reset-Inputs of the internal Flip-Flop's and

the combinatorial output decoder. Finally the

clear structure of the design guarantees the

complete testability of its circuit implementation.
While a functional specification of each block in this initial design description can easily be created, the final design implementation leads to serious problems. Due to its structure the design requires a sequencer component with one or more combinatorial outputs, and the presence of sequential blocks with two different clocks needs a circuit that fit this condition too. Additionally, the complete design requires a minimum of thirteen internal Flip-Flop's. If these three constraints are taken together an appropriate component can hardly be found. Simple PLDs cannot contain so much multilevel logic. Complex PLDs turned out to be too expensive for this application. So, a different design approach was indicated for this design. The schematic-like block structure was given up for a more abstract, but also compact design description.
DESIGN IMPLEMENTATION
Since the original design couldn't be directly implemented in a simple PLD, a complete revision of its structure had to be carried out. The resulting description file is to see in Figure 4, now given as an abstract HDL-file. The essential advantage of this design description consists of the facts that abstract descriptions are favorable for all kinds of automatic optimization, and that they can easily be adapted to several hardware architectures.
Several changes were made within the design description. First, the counter and the control u·nit are now merged into one state

machine. In doing so, an initial concept was given up. Instead of counting through the whole data frame, the sequencer waits just for the rising and the falling clock edges of the frame signal. So only the second part of a data frame needs to be evaluated and the state machine counts only the steps up to the beginning of the C/1-Bits. Furthermore, some FF's of the shift register are now used twice. While reading the C/1-Bits from the incoming bitstream they have their original function, but during the rest of time they serve as flags. So one FF stores the information about a detected DR-command, while another FF helps to evaluate a frame signal edge timing. Here the feature of two different clock pulses is taken in order to achieve a save mode of operation. All in all the design function is now given in a much more compact description and the abstract description style allows its easy mapping onto different device architectures. So finally a PLC42VA 12 was found to be a suitable circuit for the design's realization.
In spite of its general fitting, a successful implementation of the design requires design optimization. An optimal state assignment for the included state machine description as well as a final boolean minimization are absolutely necessary for the design compilation and Figure 5 shows the optimized version, which can now be compiled directly. Figure 7 gives a corresponding Pinning for the PLC42VA12 and Figure 6 shows a simulation output resulted from the implemented circuit model. This part of the simulation represents the beginning of a communication session from the initialisation via the Start-signal up to the first acknowledgement (ARN) on output SDO.

COUNT6BIT

Fsc..__ _ __..

FSC

BIT5

BIT4

CLK(C) BIT3

BIT2

BIT1

RST(R) BITO

IN5

IN4

Cl

IN3

IN2

IN1

CIEND

INO

CIEND CISTART

.,.__-+-!_ _.. SHENABLE

SDI DCL

.,.__+-! _

_..

DATA IN CLK(C)

DAT3(0) DAT2(Q) DAT1(0)

IN4

PU

IN3

IN2

DR

PU DR

RST(R)

DATO(Q)

IN1

SD01(M)

CLOCK(C)
START ~-+-----------------~--IL RESET(R)

Figure 3. Block Structure of the Controller Design

OUT DECOD DAT1

SERDATA

SDO

DAT2

71?

Philips Semiconductors Programmable Logic Devices
ISDN peripheral control

Application Note
AN037

@PINLIST

Start I

FSC

I

DCL

I

SDI

I

SDO

0

@LOGIC EQUATIONS

" Shift-Enable Signal defines the Time Slots to read the Conunand Bits

ShEnable

Q4 * Q3 * Q2 * /Ql * /QO
+ Q4 * /Q3 * Q2 * /Ql * QO + Q4 * /Q3 * Q2 * Ql * /QO + Q4 * /Q3 * /Q2 * Ql * QO

" DR and PU mark the corresponding Comm.ands decoded from the Shift Register "

DR

/DataBit3 * /DataBit2 * /DataBitl * /DataBitO

PU

/DataBit3 * DataBit2 * DataBitl * DataBitO

" Shift Register - SHIFT operation only when Enable, else HOLD
DataBitO.CLK = I DCL ;
= DataBitO.RST = I Start ;
DataBitO.J ShEnable * SDI DataBitO.K = ShEnable * / SDI
+ Q4 * /Q3 * /Q2 * /Ql * QO

DataBitl.CLK = / DCL ; DataBitl.RST = / Start
DataBitl.J ShEnable * DataBitO DataBitl.K ShEnable * / DataBitO
+ Q4 * /Q3 * /Q2 * /Ql * QO

" DataBit2 serves also for the Detection of a new Frame Phase

DataBit2.CLK = I DCL ;

DataBit2.RST = / Start

DataBit2.J

ShEnable * DataBitl

+ /Q4 * /Q3 * /Q2 * /Ql * /QO * FSC DataBit2.K ShEnable * / DataBitl

+ /Q4 * /Q3 * /Q2 * /Ql * QO * /FSC + Q4 * /Q3 * /Q2 * /Ql * QO ;

" OataBit3 serves also as Flag for a detected DR-Command

DataBit3.CLK = / DCL ; DataBit3.RST = / Start
DataBit3.J ShEnable * DataBit2 + Q4 * /Q3 * /Q2 * /Ql * QO * DR ;
DataBit3.K = ShEnable * I DataBit2 + Q4 * /Q3 * /Q2 * /Ql * QO * /DR ;

" The Flag PU stores the switches at the first occurence of the Command PU

PU Flaq.CLK PU-Flaq.RST
PU-Flaq.J PU:}'laq.K

DCL ;
/ Start ;
Q4 * /Q3 * /Q2 * Ql * QO * PU
0 ·

Q4 .CLK Q4.RST

DCL ; I Start

Q3.CLK Q3.RST

DCL ; I Start

Q2.CLK Q2.RST

DCL I Start

Ql.CLK Ql.RST

DCL ; I Start

QO.CLK QO.RST

DCL ; I Start

Figure 4. Complete HOL-Description for the Controller (1 of 3)

October 1993

71'>

Philips Semiconductors Programmable Logic Devices
ISDN peripheral control

" Finally the OUtput Signal

SDO Start
+ Q4 * Q3 * Q2 * /Ql * PU Flag + Q4 * /Q3 * /Q2 * /Ql * fQO ;

@INPUT VECTORS

[ DataBit3, DataBit2

FSC Flag NFSC Flag DR Flag NDR_Flag

-1 B;
-0 B; 1- B· 0- B;

@OUTPUT VECTORS

@STATE VECTORS

[ Q4, Q3, Q2, Ql, QO ) JKFFR

" state assignment with One Bit Changes for a Minimum of Logic

Wait on FSC

Wait- on-NFSC

" Stepl-

Step2

Step3

Step4

Steps

Step6

Step?

steps

Step9

SteplO

Stepll

Stepl2

Stepl3

Stepl4

SteplS

Step16

Stepl7

SteplS

Stepl9

Step20

DatBitl 0

DatBitl-1

Dat Dat

Bit Bit

22-

0 l

DatBit3-0

DatBi DatBi DatBi

ttt434--

l 0 l

End_Cycle

End

00000 B; 00001 B;
= 00011 B; to much "
00010 B; 00110 B; 00111 B; 00101 B; 00100 B; 01100 B; 01101 B; 01111 B; 01110 B; 01010 B; 01011 B; 01001 B; 01000 B; 11000 B; 11001 B; 11011 B; 11010 B; 11110 B; 11111 B; 11101 B; 11100 B; 10100 B; 10101 B; 10111 B· 10110 B; 10010 B; 10011 B; 10001 B; 10000 B;

@TRANSITIONS

WHILE [ Wait on FSC J
IF CFSC_Flag

THEN [ Wait on NFSC " else remain in this state "

WHILE [ Wait on NFSC ) IF [-NFSC_Flag ) THEN Step2 )

" WHILE [ Stepl ) IF [) THEN [ Step2 ) "

WHILE

Step2 IF [) THEN

Step3

WHILE Step3 J
IF [) THEN Step4

WHILE

Step4 IF [) THEN

steps

Figure 4. Complete HDL-Description for the Controller (2 of 3)

714

Application Note
AN037

Philips Semiconductors Programmable Logic Devices
ISDN peripheral control

WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE
WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE WHILE

Steps l
IF [] THEN Step6
Step6 l
IF [] THEN Step?
Step? IF [] THEN Steps
Steps l
IF [] THEN Step9
Step9 IF [] THEN SteplO
SteplO ] IF [] THEN Stepll
Stepll ] IF [] THEN Step12
Step12 ] IF [] THEN Stepl3
Step13 ] IF [] THEN Stepl4
Stepl4 ] IF [] THEN SteplS
Stepl5 ] IF [] THEN Stepl6
Stepl6 ] IF [] THEN Stepl7
Stepl7 ] IF [] THEN SteplS
SteplS ] IF [] THEN Stepl9
Stepl9 ] IF [] THEN Step20
Step20 ] IF [ DR_Flag ] THEN [ End ] IF [ NDR_Flag ] THEN [ DatBitl_O
DatBitl_O ] IF [] THEN [ DatBitl_l
DatBitl_l ] IF [] THEN [ DatBit2 0
DatBit2_0 ] IF [] THEN [ DatBit2 1
DatBit2_1 ] IF [] THEN [ DatBit3 0
DatBit3_0 ] IF [] THEN [ DatBit3 1
DatBit3_l ] IF [] THEN [ DatBit4 0
DatBit4 0 ] IF [] THEN [ DatBit4_l
DatBit4 l ] IF [] THEN [ End_Cycle
End_Cycle ] IF [] THEN [ Wait_on_FSC
End ] IF [] THEN End ]

October 1993

Figure 4. Complete HDL-Description for the Controller (3 of 3) 715

Application Note
AN037

Philips Semiconductors Programmable Logic Devices
ISDN peripheral control

@l'INLIST

Start I

FSC

I

DCL

I

SDI

I

SDO

0

@LOGIC EQUATIONS

" Shift-Enable Signal defines the Time Slots to read the Command Bits

ShEnable

Q4 * Q3 * Q2 * /Ql * /QO + Q4 * /Q3 * Q2 * /Ql * QO + Q4 * /Q3 * Q2 * Ql * /QO + Q4 * /Q3 * /Q2 * Ql * QO

" DR and l'U mark the correspondinq Commands decoded from the Shift Reqister "

DR

/DataBit3 * /DataBit2 * /DataBitl * /DataBitO

l'U

/DataBit3 * DataBit2 * DataBitl * DataBitO

" Shift Reqister - SHIFT operation only when Enable, else HOLD

DataBitO.CLK = I DCL ; DataBitO.RST = I Start
= DataBitO.J = ShEnable * SDI
DataBitO.K ShEnable * / SDI + Q4 * /Q3 * /Q2 * /Ql * QO
DataBitl.CLK = I DCL ; DataBitl .RST = I Start DataBitl.J Q4 * /Q3 * Q2 * /Ql * QO * DataBitO
+ Q4 * /Q3 * Q2 * Ql * /QO * DataBitO + Q4 * /Q3 * /Q2 * Ql * QO * DataBitO DataBitl.K Q4 * /Q3 * Q2 * /Ql * QO * /DataBitO + Q4 * /Q3 * Q2 * Ql * /QO * /DataBitO + Q4 * /Q3 * /Q2 * Ql * QO * /DataBitO + Q4 * /Q3 * /Q2 * /Ql * QO ;

" DataBit2 serves also for the Detection of a new Frame Phase

DataBit2.CLK = / DCL ; DataBit2.RST = / Start
DataBit2.J Q4 * /Q3 * Q2 * Ql * /QO * DataBitl + Q4 * /Q3 * /Q2 * Ql * QO * DataBitl + /Q4 * /Q3 * /Q2 * /Ql * /QO * FSC ;
DataBit2.K Q4 * /Q3 * Q2 * Ql * /QO * /DataBitl + Q4 * /Q3 * /Q2 * Ql * QO * /DataBitl
+ /Q4 * /Q3 * /Q2 * /Ql * QO * /FSC
+ Q4 * /Q3 * /Q2 * /Ql * QO ;

" DataBit3 serves also as Flaq for a detected DR-Command

DataBit3.CLK = / DCL ;
DataBit3.RST = I Start
DataBit3.J = Q4 * /Q3 * /Q2 * Ql * QO * DataBit2 + Q4 * /Q3 * /Q2 * /Ql * QO * DR ;
DataBit3.K = Q4 * /Q3 * /Q2 * Ql * QO * / DataBit2 + Q4 * /Q3 * /Q2 * /Ql * QO * /DR ;

" The Flag PU stores the switches at the first occurence of the Command PU

l'U Flaq.CLK l'U-Flag.RST l'U-Flag.J
l'U:::Flag.K

DCL ;
I Start ;
Q4 * /Q3 * /Q2 * Ql * QO * l'U
0 ;

Q4.CLK Q4.RST Q4.J Q4.K

DCL ; I Start ;
/Q4 * Q3 * /Q2 * /Ql * /QO ; Q4 * /Q3 * /Q2 * /Ql * QO ;

October 1993

Figure 5. HDL-Descriptlon for the Flnal Design Implementation (1 of 2) 716

Application Note
AN037

Philips Semiconductors Programmable Logic Devices
ISDN peripheral control

Q3.CL!C Q3.RST Q3.J Q3.K

= OCL ;
= I Start
= /Q4 * /Q3 * Q2 * /Ql * /QO ; = Q4 * Q3 * Q2 * Ql ~ QO * Databit3
+ Q4 * Q3 * Q2 * /Ql * /QO ;

Q2.CL!C Q2.RST Q2.J
Q2.K

DCL
= I Start ; /Q4 * /Q3 * /Q2 * Ql * /QO
+ Q4 * Q3 * /Q2 * Ql * /QO /Q4 * Q3 * Q2 * Ql * /QO
+ Q4 * Q3 * Q2 * Ql * QO * DataBit3 + Q4 * /Q3 * Q2 * Ql * /QO

Ql.CL!C Ql.RST Ql.J
Ql.K

= DCL ; = I Start ;
/Q4 * /Q3 * /Q2 * /Ql * QO * /Databit2 + /Q4 * Q3 * Q2 * /Ql * QO + Q4 * Q3 * /Q2 * /Ql * QO + Q4 * /Q3 * Q2 * /Ql * QO
/Q4 * /Q3 * Q2 * Ql * QO + /Q4 * Q3 * /Q2 * Ql * QO + Q4 * Q3 * Q2 * Ql * QO + /Q4 * /Q3 * /Q2 * Ql * QO + Q4 * /Q3 * /Q2 * Ql * QO ;

QO.CL!C QO .RST QO.J
QO.K

= OCL ; = I Start ;
= /Q4 * /Q3 * /Q2 * /Ql * /QO * DataBit2 + /Q4 * /Q3 * Q2 * Ql * /QO + /Q4 * Q3 * Q2 * /Ql * /QO + /Q4 * Q3 * /Q2 * Ql * /QO + Q4 * Q3 * /Q2 * /Ql * /QO + Q4 * Q3 * Q2 * Ql * /QO + Q4 * /Q3 * Q2 * /Ql * /QO + Q4 * /Q3 * /Q2 * Ql * /QO
/Q4 * /Q3 * /Q2 * /Ql * QO * /DataBit2 + /Q4 * /Q3 * Q2 * /Ql * QO + /Q4 * Q3 * Q2 * Ql * QO + /Q4 * Q3 * /Q2 * /Ql * QO + Q4 * Q3 * /Q2 * Ql * QO + Q4 * Q3 * Q2 * Ql * QO * DataBit3 + Q4 * Q3 * Q2 * /Ql * QO + Q4 * /Q3 * Q2 * Ql * QO + Q4 * /Q3 * /Q2 * /Ql * QO

" Finally the Output Signal

SDO

Start

+ Q4 * Q3 * Q2 * /Ql * PU Flag

+ Q4 * /Q3 * /Q2 * /Ql * f QO ;

Figure 5. HDL-Description for the Final Design Implementation (2 of 2)

Application Note
AN037

October 1993

717

Philips Semiconductors Programmable Logic Devices
ISDN peripheral control
FSC DCL
DATABIT2

Application Note
AN037

Figure 6. Simulator Output of the Modeled Circuit Implementation

Device
l?inl l?in2 l?in3 l?in4 l?in14

= C42VA12
= DCL = START = FSC = SDI = SDO

Figure 7. Pinlist for the Controller Implementation

October 1993

718

Philips Semiconductors Programmable Logic Devices
ISDN peripheral control

***************************************************

Output of Updsirn Version 1.85

* Date: 02/04/93

Time: 13:56:28 *

***************************************************

** Input File Name
* Output File Name

APPNOTE3.net APPNOTE3.SCL

* *

*

*

***************************************************

P START, FSC, DCL, SDI, PU_Flag, DataBit3, DataBit2, DataBitl, DataBitO, # SDO
PCO
*
S 1 500 ) START
S 0 1000, 33000, 65000, 97000, 129000, 161000, 192000, 224000 ) FSC S 1 500, 1000, etc) DCL
S 0 55000, 61000, 117000, 119000, 121000, 123000 ) SDI SU time = 300000

F

Figure 8. SCL

SUMMARY
The example of the developed controller has shown that even relative complex designs can be realized with quite small PLDs. Especially if sequential control functions or irregular logic is to be implemented. Hardware programmable logic ICs are often the most suitable solution and sometimes the use of PLDs can simplify the development of new boards and systems significantly.

In addition, the example also illustrates the great effect, which can be achieved by certain design styles and by an appropriate optimization of designs. An initial design description has an essential influence on the final network and its implementation and so it affects the requirements for a component as well as the whole projects costs. By optimization a designer can reduce the amount of gates for a certain design too, leading to a much more efficient use of the given components.

Application Note
AN037

October 1993

719

Philips Semiconductors Programmable Logic Devices
PLO programmable retriggerable one-shot

Application Note
AN011

FEATURES
· Programmable pulse-width/delay
· Maximum 256 clock cycles
· Asynchronous TRIGGER input
· Active-High and Active-Low outputs
· Asynchronous RESET
· 20-pin package
THEORY OF OPERATION
The one-shot consists of a PLC42VA12 and an external clock which may be part of the system in which this one-shot is to work. As shown in Figures 1 and 3 the PLO is configured to have a latch and an eight-bit binary up counter which is presettable by input data to any number less than 256. Since the input data is inverted before it is loaded into the registers, counting from the

complements of the input to FF will give the correct number of counts as counting from the input down to 00.
Pulse-width/delay inputs may be the outputs of another device or switches. When /RESET goes Low, flip-flops are set to all 1's (terms PB, PA, and PMO). At the rising edge of the next clock, data is latched into the registers (terms LB, LA, and LMO). When /TRIG goes Low, it is latched into the input latch formed by term # 0, 1, 2 and 13. The output 01 of the latch goes High and 02 goes Low which enables the 8-bit counting cycle. The 01 and /01 will maintain their output levels until the end of the counting cycle at which time the counter reaches the count FF, resets the latch by term# 13, and sets 02 High. At the rising edge of the next clock, terms LA, LB, and LMO cause data to be loaded again into the registers, and the device is ready for another /TRIG input. The output waveforms are illustrated in Figure 2.

If the /TRIG pulse-width is longer than the desired pulse-width of the one-shot, the device will react as mentioned above, and at the end of the count cycle new data will be loaded, another count cycle begins while the outputs remain set by the /TRIG input without changing throughout the change-over of one count cycle to another. 01 a, on the other hand, will go Low for one clock period at the change-over. As long as the /TRIG is Low, 01a will continue to pulse Low for one clock period at the change-over of one count cycle to another. The output 02 will pulse High for one clock cycle at the change-over. Figure 2 illustrates output wave-forms for both cases. The output wave-forms are as illustrated in Figure 2.
The one-shot is implemented by programming the PLC42VA12 as shown by the SNAP listing in Figures 3 and 4.

".>c-----01

COUNT

FO

00

F1

01

F2

02

F3

03

INPUT

02

F4

Q4

F5

05

06

F7

07

CK P LOAD

=

SYSTEM CLK > - - - - - - - - _ J
RESET ) - - - - - - - - - -

Figure 1. Programmable Retriggerable One-Shot

November 1986

720

Revised: October 1993

Philips Semiconductors Programmable Logic Devices
PLD programmable retriggerable one-shot

Application Note
AN011

CLTOCRK JIGL--......I,uLil,
,___ _ _ COUNT CYCLE _ _ _. ,
s
01, 018 _ _ ___.
01-----.
02---------------~r---i~-----
TRIG-----.

01.-----'

s

,
j

01 _ _ ___,

0 1 - - -.......

I

I

02~~~~~n~~~-n_

Programmable One-Shot

TRIG 01·
02

Figure 2. Timing Diagram of Programmable Retriggerable One-Shot

November 1986

721

Philips Semiconductors Programmable Logic Devices
PLO programmable retriggerable one-shot

Application Note
AN011

************************************************************

*

PLC42VA12 24-Pin DIP Package Pin Layout

*

* Date: 08/10/93

Time: 13:02:11 *

_ _ ******************~*****************************************

I

\

/

I

I

I

I·

CLK llIO/CLK

VCCj24]

RESET 21Il

M9 l23] 02

TRIG 31I2

MS 122] 1101

41I3

M7121] IllF7

51I4

M6120] IllF6

61I5

MS 119] INFS

71I6

M4j18] IllF4

81I7

M3117] INF3

( 9jI8

M2116] IllF2

01 (lOIBO

Mll15] INFl

OlA [lllBl

M0114] INFO

[12jGND

l9/0E_l13]

I

I

Figure 3. Pin Layout

"-------------------------------------"
" Proqrammable Retriqqerable One-Shot "
"-------------------------------------"
" This desiqn is for a PLC42VA12 device. A similar type of function may be proqrammed into any of the PLS155/7/9A type devices. These devices contain a flip-flop preload function which may be controlled by input pins and TTL voltage levels or by feedback into the array from the flip-flops outputs.
This one-shot loads the data at the IllFO-INF7 input pins into the counter at the end of the clock cycle (02 =HIGH). If TRIG input is LOW lonqer than the count cycle, output OlA will qo LOW for one clock period and will qo HIGH aqain for another count cycle. Outputs 1101 and 01 stay LOW and HIGH respectively until TRIG qoes HIGH and the count cycle is completed without interruption.

@pinlist

elk

i;

reset

i;

triq

i;

inf[7 .. O] i;

ol

o;

o2

o;

nol

b;

ola

b"

@loqic equati.ohs
"-----------------------------"
" equations for latch circuit '" "----------------~------------"

01

(nol+/trig);

ola

/(nol+/triq);

Ola.oe 1;

nol

/((f7*f6*f5*f4*f3*f2*fl*f0)

+ Ola);

nol.oe 1;

"---------------------------"

" count comparison equation "
"---------------------------"

o2

(f7*f6*f5*f4*f3*f2*fl*f0);

Flg_ure 4. SNAP Listill!ll1 of 2}_

November 1986

722

Philips Semiconductors Programmable Logic Devices
PLD programmable retriggerable one-shot

"-------------------------------------·
" equations to load counter from pins "
#-------------------------------------"

"use register preload feature"

temp[lS ·· O] .ld templ4 templ5 templ2 templ3 templO templl
temps temp9 temp6 temp7 temp4 temps temp2 temp3 tempo templ

(f7*f6*f5*f4*f3*f2*fl*f0); inf7; /inf7; inf6; /inf6; inf5; /infS;
inf4; /inf4; inf3; /inf3; inf2; /inf2; infl; /infl; infO; /info;

· counter equations"
"------------------"
"The counter is constructed using the toqqle feature of .:JK flip-flops. Both J and K are connected to the same product term so only eiqht product erms are required to implement this counter. Tile ·+tempXX:' input does not require a product term in the 42VA12 or PLS155/7/9A type devices due to the wire-or reqister preloadinq feature. This feature is controlled internally in the device by the LA and LB product terms. SNAP automatically uses these control terms to implement the preload.

fO.j fO.k fl.j fl.k f2.j f2.k f3.j f3.k f4.j f4.k fS.j fS.k f6.j f6.k f7.j f7.k

((nol*reset) +templ);
( (nol*reaet) +tempO);
((nol*fO*reset) +temp3);
((nol*fO*reset) +temp2);
((nol*fl*fO*reset) +temp5);
((nol*fl*fO*reset) +temp4);
((nol*f2*fl*f0*reset) +temp7);
((nol*f2*fl*fO*reset) +temp6);
((nol*f3*f2*fl*f0*reset) +temp9);
((nol*f3*f2*fl*f0*reset) +temp8);
((nol*f4*f3*f2*fl*f0*reset) +temll);
((nol*f4*f3*f2*fl*fO*reset) +temlO);
((nol*f5*f4*f3*f2*fl*f0*reset) +teml3);
((nol*f5*f4*f3*f2*fl*f0*reset) +teml2);
((nol*f6*f5*f4*f3*f2*fl*f0*reset) +teml5);
((nol*f6*f5*f4*f3*f2*fl*fO*reset) +teml4);

f[7 ·. 0].clk elk; f[7 ·. 0].set =reset;

Figure 4. SNAP Listing (2 of 2)

November 1986

723

Application Nole
AN011

Phillps Semiconductors Programmable logic Devices
Designing with programmable macro logic

INTRODUCTION TO PROGRAMMABLE MACRO LOGIC DESIGN CONCEPTS
Programmable Macro Logic (PML), an extension of the Programmable Logic Array (PLA) concept combines a programming or fuse array with an array of wide input NANO gates wherein each gate folds back upon itself and all other such NANO gates. This is called a foldback NANO structure and its basic elements have been outiined previously (Cavlan1, Wong2, Gheissari and Safari3).
The choice of an internal NANO logic cell is appropriate because the cell is functionally complete, requiring but a single cell type to generate any Boolean function. A cell within the PLHS501 may be configured to accommodate from one to 32 inputs from the outside world, and up to 72 inputs from within the chip. Because the user can select either direct or inverted input variables, and either a direct or complemented output, the NANO function can generate, with a single pass through the programming array, the basic four logic functions of AND, OR, NANO, NOR. all these basic functions, can be extremely wide, of course (see Figure 1). This convenient structure allows efficient exploitation of all widely used minimization techniques (Karnaugh Maps, Quine-McClusky, Boolean Algebra, etc.).
The obvious extensions to additional combinational functions for decoding, multiplexing and general Boolean functions is straightforward. Adding feedback to the system expands the range of realizable functions to include sequential as well as combinational functions. Figure 2 illustrates the basic arrangement of the PLHS501.

Because of the large number of inputs each NANO gate has available, logic functions that require several levels of conventional 4 or 8 input gates may be able to be reduced to 1 or 2 levels. However, it is important to realize that unlike AND-OR PLO architectures, more than 2 levels of logic may be implemented in the PLHS501 without wasting output or input pins. Up to 72 levels of logic may be implemented due to each of the 72 foldback NANO gates.
So far, the concept of a ·macro" is still not evident. Two ways for the generation of a macro exist-namely, hard and soft. Borrowing from the concept in computer programming wherein a section of code (called a macro) is repeated every time its use is required, we can establish subfunctions which can be repeated each time required. The user defined or soft macro can be one which will generate a function by fused interconnect. When a fixed design function is provided, ii is a hard macro. This may be an optimized structure like a flip-flop or an adder, or some other function which is generated on the foundation, by the manufacturer. Soft macros are seldom optimized or precisely consistent, but hard macros are both optimized and unalterable.
When a user function for a particular use is isolated, defined and repetition of the function is required, special software constructs are provided which will allow it to be defined at a higher performance and functional density, and an array of choices which contain optimized functions or hard macros will be offered in successor chips. In particular, the PML2552 and PML2852 include an array of flip-flops for state machine design.

Optimizing combinational functions in PML consists largely in making choices and trade-offs. For single output logic functions, the choice is obvious from the truth table. If a particular function's truth table has fewer entries that are logical zeroes than logical ones, product of sums should be chosen and the appropriate OR-AND structure generated. Otherwise, the usual sum of products should be chosen, minimizing as usual, before dropping into the two level AND-OR structure (using the NANO-NANO realization). Combining the availability of inversion at the input and output of the chip, the NANO-NANO structure can perform either the OR-AND or the AND-OR rendition of a function with equal logic levels. The designer needs only to choose the optimal rendition to suit his needs (see Table 1). Truth tables with 50% ones can use either version at the designers whim unless other uses arise.
PERFORMANCE
The PLHS501 (Figure 2) is a high speed, oxide isolated, vertically fused PML device containing 72 internal NANO functions which are combined with 24 dedicated outputs. A large collection of applications, both combinational and sequential, may be configured using this part which looks roughly like a small, user definable gate array. For the sake of clarity, worst case passing a signal from an input, making one pass through the NANO array (output terms) and exiting an output takes around 25 nanoseconds with each incremental pass through the NANO foldback array taking about 8 nanoseconds.

ltp--t>-A+B+... +Z

B:

(OR)

z.

A~ JtB:"::"Z
: IJ-' .,. (NANO)

IZ~ z

lt~A+B+ ... +Z

B:

(NOR)

z.

A~AB ··· z

B:

(AND)

z.

INPUT SECTION

NANO ARRAY

OUTPUT SECTION

Figure 1. PML Basic Functions

November 1993

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Philips Semiconductors Programmable Logic Devices
Designing with programmable macro logic

Table 1. Example Demonstration
F1 (A, B, C);: JJJC + Jl"BC + ABC + ABC + ABC

A

B

c

f1

C'AB DO 01

11

10

0

0

0

0

0

0

1

1

I I 0

0

1

1

0

0 1

0

0

0

0

0

0

0

The optimal choice would be to generate

0

the zero entries

1

0

If we group on the one entries we shall get: AB +BC+ BC

IA~A BA

IB~B ~

~B
IC--~ C
L__J INPUTS NANO ARRAY

OUTPUT

If we group on the~ entries we get Instead: F1 = (B + C) (JI"+ B + C) IA~ A

L__J INPUTS NANO ARRAY

OUTPUT

.. ,_,.,....... a........ 1na<::1

725

Philips Semiconductors Programmable Logic Devices
Designing with programmable macro logic

INPUT71

0

BUFFERS

j_ ·· ~

'°Di I
1230! ~ ..........

t 72 HAND TERMS

J_ J_
J_
I OUT~UT TERMS

INPUTBUF FERS
Kr
~

:

..VVQ .~·

~~~~~~ x4 x4

~~~ x4
x4 x4 '1__

1'..
I~

y

'--------:=_

x4

Jl··>

......

J)xI ")-

Figure 2. PLHS501 Logic Diagram

~f~ E--0 ~ fE--0
.___ ~
OUTPUT BUFFERS

November 1993

726

Philips Semiconductors Programmable Logic Devices
Designing with programmable macro logic

The data sheet first lists some maximum propagation delays from an input, through a NANO output term and out through various output gates. Secondly, it lists maximum propagation delays from an input, through a NANO foldback term, through a NANO output term and out through the different output gates.

It is intriguing that subtracting one from the other yields a NANO foldback gate delay of 5 to 6ns when the worst case gate delay of an internal foldback gate is listed as Bns. This is due to the fact that a gate has less of a delay when its output is falling (IPHLl than when its output is rising (lpLH)· When passing a signal through two NANO gates one gate will have

less of a delay than the other, and since the individual rise and fall delays are not specified, this causes the apparent discrepancy between the two delays.
Figure 3, Figure 4, Figure 5 and Figure 6 show graphically the timing paths listed in the PLHS501 data sheet.

PLHS501 TIMING

tpo

INPUT71 BUFFERS
1oo 1-D
1230-H......__

0
I ···

I I

T

I 72 NANO

'---1--+--1-1----1--'-'i';l-l.--1--'

oTuERlMuTS

'" - =- =- =- =- =-~-=- =-~-=- =-:-=- =- =-:-=- =-:-=- =- =-:~:i. . ; IN,; P, ,;U. ;.T, ,;BUF ERS

TERMS ---+--1--1-<---+-->--1,if--+-+--+--+-+---+--+-+--+--+--+---lllH~<'.:i....I-,

-+-+---+-+----1--1---+-+--+--1--_._.,,f--+-+--+-+--+---+-+--+--+---l--+---111<-0-1=~

x4 x4
T

NOTE: PD = 22ns maximum.
nput Buffer+ 1 NANO gate+ Output Buffer (0, /0,8).

~Do.Cl:! -c..J ·2 -0 o,.ea
*1 ....................;i,. tpo x2 U4,U

'-----------------------J--1~ U5,U.,

Figure 3. !po -22ns Maximum

L.-OUTPUT BUFFERS

November 1993

727

Philips Semiconductors Programmable Logic Devices
Designing with programmable macro logic

PLHS501 TIMING (Continued)

tpo

INPUT71

0

BUFFERS

I ···

·oQ 1-D

: 12301 rD
L.-

1 72
NANO TERMS

~
!

_L J_
-1
ouluT TERMS

INPUTBUFFERS
·~
B:

6&2···vvL I~~~~~~ ·4 x4

~~~

I"~

tI~
1¥x4

-r-u

l - ·~

b=

<$mm

)) :xr4.>

......

J)x4/

NOTE: tpo .. 30ns maximum. Input Buffer+ 2 NANO gates + XOR gate + Output Buffer

Figure 4. tp0 -30ns Maximum

i rr--oo
i rx-2 x2
~ OUTPUT BUFFERS

November 1993

728

Philips Semiconductors Programmable Logic Devices
Designing with programmable macro logic

PLHS501 TIMING (Continued)

INPUT71 BUFFERS
1ooj !.;<>
:
12301.H__:>_

l ...
I 12
NANO TERMS

...... ,;.....;.;..............;.............;:.......;.;..;... .
J. I
OUTlUT TERMS

'""'

INPUT BUFFERS
_,.,_ l<h _,.,_
I<

. _cl

~···QQQ ~~~~~~ x4 x4
J

_§ ~~~ x4 X4

,,

1I4:-~·· ~

.____,~ r 4 { ]

L--'~

'"~

))·~

L..I

I

JJ·->

NOTE, PD = 25ns maximum. nput Buffer+ 1 NANO gate+ XOR gate+ Output Buffer

Figure 5. lpo -25ns Maximum

~~ ~ ~ ~
~
L.-OUTPUT BUFFERS

729

Philips Semiconductors Programmable Logic Devices
Designing with programmable macro logic

PLHS501 TIMING (Continued)

INPUT71 BUFFERS
. 1ooj~ :
1zaO._~_

l .·.
T72
NAND TERMS

'PD 0

J_ J_
.1 .1
ouL
TERMS

INPUT BUFFERS
l<J-

~lpo

~

!

:t~~···LJlJy ~L:J~ L12JL12JLxzJ ·· ..

....,

~~l:;J x4 x4

x4
r(

I~ ~Jlo-B3

S> '--

~84-B7

x4

'---::::J..

Jlx4)-

....., Xo."2.X..lfa

:I
JJ-9

-LJ X1, Xa. lf5, X7

NOTE: tpo - ens maximum.

Figure 6. tpo -8na Maximum

~~Oo.<>2
v ~01.0a
~IE-a o..,0a ~lJr;."G, ~
BUFFERS

November 1993

730

Philips Semiconductors Programmable Logic Devices
Designing with programmable macro logic

NANO GATE FLIP-FLOPS Various types of flip-flops and latches may be constructed using the NANO gate building blocks of the PLHS501. A typical 7474 type of edge-triggered D flip-flop requires 6 NANO gates as shown in Figure 7.
No additional gates are required to implement asynchronous set and reset functions to the flip-flop. The equations necessary for SNAP to implement the D flip-flop are shown in Figure 8. However, please note that the equations of Figure 8 define a D ffip-ftop configured as a divide by 2 (i.e.. ON is connected to the data input) whereas Figure 7 shows a general case. Also note that flip-flops with some additional features may be constructed without using more than the six NAN D gates. This is possible because of the large number of inputs associated with each NANO gate. For instance, a flip-flop may be required to have a clock gated by one or more signals. Using the PLHS501, it may

be implemented by adding additional input signal names to NANO gate equations of gates #2 and #3 of Figure 7. If the data input is to the AND of several signals, extra inputs to NANO gate #4 may be used. Or if additional set or reset lines are required, they may be added simply by using more of the inputs of each NANO gate connected to the main set or reset.
Figure 10 shows two simulations of the same flip-flop. The first one is at a little less than maximum frequency, for clarity in following the waveforms, and the second is at the maximum toggling frequency. For these simulations each NANO gate h~s a maximum lpHL or trLH of 8ns (which is the gate delay of a NANO gate in the PLHS501 's foldback array). First of all, it can be seen from these simulations that for proper simulation or testing of such a device a set or reset input is mandatory. Both 0 and ON outputs are unknown not matter what the inputs do, until

they are put into a known state by either a set or reset input. Secondly, various timing parameters such as propagation delay, as well as setup and hold times may be determined.
Therefore, performance of the flip-flop depends a great deal on which gates in the PLHS501 are used, either NANO gates in the foldback array or output NANO gates, connected to bidirectional pins. As a test of the simulation, a D flip-flop connected as a divide by 2 was constructed using only the foldback NANO terms (see Figure 8). An output NANO terms was used to invert the ON output and drive an output buffer. The only inputs were the clock and a reset. The data input to the flop was driven internally by the ON output. According to the simulation, it was possible to drive the clock at a frequency of 25MHz and this small circuit also functioned at that frequency.

Figure 7. Edge-Triggered D Flip-Flop

November 1993

731

Philips Semiconductors Programmable Logic Devices
Designing with programmable macro logic

************************************************************

*

PLHS501 52-Pin PLCC Package Pin Layout

* Date: 10/13/93

Time: 16:42:21 *

************************************************************

RC

S L

T K

+-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I 1515151414141

171615141312111211101918171
+----------------------------------+

I IIIIIIIIIIIII

I

I 1111111198765

I

I 7654321O

I

I 8 IVCC

I vcc 146)

[ 91 !18

I4145)

[10 I !19

I3144]

[111 I20

I2143)

[121I21

I1142]

[131I22

!0141]

[14 I I23

/B3 I40] OUT

[151B4

/B2 I 39)

[161B5

/Bl 138)

[17 IB6

/BOl37]

[181B7

X7136]

[19100

X6135)

[20 IGND

GNDl34)

I

I

I

I I I I

I

I 0 0 0 0 0 0 0 xxxxxx

I

+I ----1--2--3--4--5---6--7--0--1--2--3--4--5-----+I

121212121212121212131313131

111213141516171819101112131

+-+-+-+-+-+-+-+-+-+-+-+-+-+

@PINLIST elk i; rst i;
out o; @GROUPS @TRUTHTABLE @LOGIC EQUATIONS

flop.elk flop.d flop. rst out

elk; /flop;
rst; flop;

@INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANSITIONS

Figure 8. SNAP Ustlng

November 1993

732

Philips Semiconductors Programmable Logic Devices
Designing with programmable macro logic
PLHS501 776666666666555555555544444444443333333333222222222211111111110000000000 109876543210987654321098765432109876543210987654321098765432109876543210 IIIIIIIIIIIIIIIIIIIIIIIIBBBBBBBB 22221111111111000000000000000000 32109876543210987654321076543210 -------------------------------- Col for /B 0
······················ ········· ············· ········ ················· A ··
HH------------------------------ Col for P 0
···································································· A ···
-H------------------------------ Col for P 1
··································································· A ··· A
H------------------------------- Col for P 2
·································································· A ·.. A.
-------------------------------- Col for P 3
··································································· A ··· A
H------------------------------- Col for P 4
·····································.·····.····················..··· AA.
-------------------------------- Col for P 5
··············.···.··················.····..·····················..·· A.A
Figure 9. Partial PLHS501 Fusemap Showing Test Flip-Flop Fusing

20.0

40.0

60.0

80.0

100.0

120.0

140.0

160.0

180.0

t_

_t

+

+

+

+

+

+

+

+

s

1:..

s

1:..

+

+

s

+

1:..

+

s

RESETN CLOCK DATA

+

+

+

+

+

+

+

DR

t--'

+

+

+

+ L +J

+

+

SN

t--'

+

+

+

+

+

+

+ _ r - - RN

t-'

+

+

+

+

+ J

+

+

L DN

+

+

+

J +

+

+l

Q

+

+

+

+1

+

S+

ON

20.0

40.0

60.0

eo.o

100.0

120.0

140.0

160.0

Figure 10. Waveforms of Test Flip-Flop

November 1993

733

Philips Semiconductors Programmable Logic Devices
Designing with programmable macro logic

FUNCTIONAL FIT
In the late 1960's and early 1970's designers used SSI, MSI and small amounts of early LSI to generate logic solutions. Frustrated by the lack of wide input gates to accommodate a lot of product terms for two level solutions, they turned toward the budding ROM and PROM products. These devices relied on literally realizing a function by generating its truth table in silicon. The logic function had to have each logical one and zero realized distinctly as an entry for a particular combination of input variables, usually supplied on the address lines of the memory. Observing that many such truth tables were dense in ones or zeroes and sparse in the remainder, a cadre of initial manufacturers emerged with focus on supplying a programmable product with a few AND gates and OR gates which were versatile enough to compete against the ROM/PROM parts. The gimmick supplied these PLA manufacturers was to illustrate the functional equivalency of the PLA to the PROM by comparing the number of product terms (to be shortened to "p-terms"} the PLA supplied and comparing this to the width and depth of available PROMs. P-terms became the "currency" of the PLA world and a designer only had to assess the equivalent number of Boolean product terms required by his function to determine whether a particular PLA was a suitable candidate for his design.
Almost in parallel, gate arrays became available. These provided an array of identical, fixed input gates (usually two input NANDs or NORs}. These were generated in a regular fashion on substrate which has a fixed input/output pin arrangement. Also recognizing that all logic functions could be built from the appropriate two input gate, when interconnected correctly, manufacturers offered these devices to customers who required increased density.

The designer's responsibility was to generate what would ultimately be a metal interconnect pattern of his design. Special tools were
required to allow an untrained system
designer to do this successfully. Flop-flops, decoders, registers, adders, etc., could all be generated from the low level gate building blocks.
The currency of gate arrays became known as gate equivalent functions. That is with limited number of available gates on a substrate, the user needed to know precisely how many gates were used up, on a function by function basis, to generate each piece of his design. A D flip-flop requires about six gates, a D latch four, a 3 to B decoder takes about 14 gates and so forth. This allowed estimation regarding whether the function could conceivable be fit onto a particular substrate or not. Manufacturers had to offer multiple foundations to that a designer could be assured that his design would result in a working JC.
The classic method of estimating whether a logic function would fit into a PLA was to determine the number of 1/0 pads required and the number of product terms required to generate the logical function, then select the PLA. For a gate array, the required measure included the 1/0 pad arrangement but substituted the number of available gates to generate the logical function (usually by table lookup}. In an attempt to reconcile the two measures, Hartman4 has evolved a formula for his product line. A calculation using this method and developing an appropriate "exchange rate: is shown in Table 2 for the PLHS501 and PLHS502. An alternate method of generating an estimate is to consider the gate equivalent of generating, say for the PLHS501, a gate equivalent of the part in an optimistic functional configuration (72 occurrences of a 32 input NANO gate}.

Figure 11 shows how this will result in over 2000 equivalent gates. Conversely, by stacking the NANO gates into D flip-flops, its least efficient function, the PLHS501 will have a gate equivalent of only about 100 gates.
The most rational method of assessing fit is to isolate functions and identify the correct configuration in terms of gates, to allow direct tally of the gates used, to generate the proposed configuration. Table 3 may assist in doing this analysis. Note that all basic gates require precisely one gate to generate the function. Also note the occurrence of functions in the table which could never be generated as standard ICs previously. The procedure is to tally the design against a total budget of 72 multiple input NANO gates.
Table 3 is illustrative only, and should by no means be taken as complete. It may be simply expanded by designing the proposed function with disregard to the usual restrictions on the number of inputs to a gate, realize the function as one, two, three, or more levels of interconnected logic and count the number of gate occurrences required. Special software has been provided to allow pyramided logic structures to be generated under the designer's control. These structures may, however, be no deeper than 72 levels for the PLHS501. Functions should be generated in accord with the guidelines mentioned before, for selecting an optimal 2 level logical solution.
It is an interesting observation that manufacturers of gate arrays and standard cell products which offer embedded PROMs, ROMs or RAMs have not successfully described these embedded functions in terms of equivalent gates, but rather resort to other means (such as divulging their relative area with respect to the area of a basic gate). There is, as yet, no standard in this arena.

November 1993

734

Philips Semiconductors Programmable Logic Devices
Designing with programmable macro logic

Table 2. Equlvalency Ratio
Hartman's method is based on a CMOS gate array equivalency wherein 4 transistors constitute a 2 input NANO or NOR gate, equal to one gate. Thus, his "exchange rate" is as follows:
E.R. = 4 x # inputs +9 x # FFs +7 x # 3-State outputs +(15 to 30) x #OR outputs from the AND/OR array.
For the PLHS501: (using CMOS numbers which~ be inappropriate)
E.R. = 4 x32 +9x0 +7x24 +(15 to 30) x 50% of 72 feedbacks= 836 to 1376 gates
Being for two bipolar ICs, in this case, the method may be inappropriate, but may be taken as an estimating procedure.

A B
c
D ABCDEFGH
E F
G H
ABCDEFGfUJRLMNOP

K

L

M

UKLMNOP

N

0 p

NOTE: Double this and add one for a 32 lnput NANO.
Figure 11. 16 Input NANO Formed from 2 Input Gates

Ml'\u.omhnr iQQ'2

735

Philips Semiconductors Programmable Logic Devices
Designing with programmable macro logic

Table 3. PLHS501 Gate Count Equivalents

FUNCTION

INTERNAL NANO EQUVAL·
ENT

COMMENTS

Gates

NANDs ANDs NO Rs ORs

1

For 1 to 32 input variables

1

For 1 to 32 input variables

1

For 1 to 32 input variables

1

For 1 to 32 input variables

Decoders

3-to-8 4-to-16 5-to-32

8

Inverted inputs available

16

Inverted inputs available

32

Inverted inputs available (24 chip outputs

only)

Encoders

8-to-3 16-to-4 32-to-5

15

Inverted inputs, 2 logic levels

32

Inverted inputs, 2 logic levels

41

Inverted inputs, 2 logic levels,

factored solution.

Multiplexers

4-to-1 8-to-1 16-to-1 27-to-1

5

Inverted inputs available

9

17

28

Can address only 27 external inputs -

more if internal

Flip-Flops

D-type Flip-Flop

6

T-type Flip-Flop

6

J-K-type

10

Flip-Flop

With asynchronous S-R With asynchronous S-R With asynchronous S-R

Adders

8-bit Barrel Shifters

45

Full carry-lookahead (four levels of logic)

8-bit Latches

72

2 levels of logic

0-latch

3

2 levels of logic with one shared gate

November 1993

736

Philips Semiconductors Programmable Logic Devices
Programmable macro logic primer

Application Note
AN029

SUMMARY
The evolution of Programmable Logic Devices (PLD's) has led to the birth of a new generation of programmable devices designated as PML (Programmable Macro Logic). The immense versatility of these devices brings them closer as plausible alternatives to semicustom design approaches in low-to-medium ranges of applications. The following paper gives a description of all three PML devices, the PLHS501, PML2552, and the PML2852. In addition, some basic design tips and techniques for PML devices are presented.

For example, if an 1/0 pin is used as an input, the output macros are all wasted. Obviously, such an architecture cannot provide the user with an increase in the levels of logic integration. The PML device takes advantage of the fundamental architecture shown in Figure 2 to overcome these deficiencies and waste of on-cllip resources. As shown in Figure 2, PML incorporates the NAND-NAND gate equivalence to break the AND-OR bottleneck.

The core of the PML is the programmable

NAND-NAND network which connects the

input and output macros to each other. Thus

the inputs, outputs, and function macros are

all connected by a single array.

·

The first device is the PLHS501. The seemingly simple structure of this device can implement every logic function furnished by the current PAUPLA devices. Although the PLHS501 is principally a combinational logic device, its unique architecture makes it an ideal tool for applications involving asynchronous state machines (See Reference 2).

THE EMERGENCE OF THE THIRD GENERATION PLO ARCHITECTURE
PML was introduced at WESCON '86 by Philips Semiconductors Corporation. The unique architecture of PML breaks away into a new era of programmable logic devices. The purpose of the PML architecture is to overcome the two level AND-OR bottleneck and provide the user with a higher level of logic integration. Current PLD's rely on two levels of logic transformation to implement combinational logic in Sum-Of-Products (SOP) form. In addition, various PLD's make use ol higher level macros such as flip-flops to form sequential logic functions. These macros connect the AND-OR chain to dedicated 1/0 pins.
Figure 1 show the basic architecture ol one of the most recent PAL® devices. It is clear that this architecture is inefficient in making full use of the available on-cllip resources. This is due to the fact that an unused 1/0 macro will be wasted and remains futile.

AND-OR CHAIN AND OUTPUT MACRO

Figure 1. One of the Latest Registered PALs

®PAL Is a registered trademark of Advanced Micro Devices, Inc. .l11nc 1QAR

7?.7

Philips Semiconductors Programmable Logic Devices
Programmable macro logic primer
Nx MNANO ARRAY
0

Application Note
AN029
0

Figure 2. PML Fundamental Architecture

June 1988

738

Philips Semiconductors Programmable Logic Devices
Programmable macro logic primer

Application Note
AN029

THE PLHS501
The PLHS501 architecture in Figure 3 exhibits an exquisite logic tool. The device provides a combination of 72 NANO terms, 24 dedicated inputs (10-123), eight bidirectional I/O's (B0-87), eight exclusive-OR outputs (XO-X7), and eight dedicated outputs (00--07).
Since the output of each NAND term feeds back to the inputs of the NAND array,

intricate logic functions can be implemented without wasting valuable 1/0 pins. For example, in order to implement an internal 'RS' latch in a combinational PAUPLD, at least two inputs and two outputs are required. The same internal latch can be configured by the PLHS501 without using any 110 pins.
The shorthand notation of Figure 3 hides something with which many designers have

been impressed in the PLHS501, the wide input NANO gates. Figure 4 shows just how wide the internal NANOs are, from a logical viewpoint. Each NANO can accommodate up to 32 external inputs and 72 internal inputs. Hence the part is ideal for wide decoding of 32-bit address and data busses. With 72 copies of the wide NANO, the PLHS501 is often compared against low-end gate arrays.

24 DEDICATED
INPUTS

NANO ARRAY

I N T E R
c
0 N N E
c
T 16
DEDICATED OUTPUTS
<=> 81-DIRE2C4TIONA I/Os

Figure 3. PLHS501 Functional Block Diagram

1., ....... <1noo

73g

Philips Semiconductors Programmable Logic Devices
Programmable macro logic primer

Application Note
AN029
LATCHES
Figure 5 illustrates how 'RS" and 'D' latches are implemented in the PLHS501.

Figure 4. An Internal NANO Logic Equivalent

INPUTO-- S ~ Q ---c::J OUTPUT ¢

--D=i- INPurD-- R

Q ---c::J OUTPUT

a. RS Latch

lf--+---
Q
0 _ _ __.-l-1-+-
[E-~jj:tt=

0-0ouTPUT¢

b. 0 Latch Figure 5. R/S and 0 Latch Implementation with PML

June 1988

740

Philips Semiconductors Programmable Logic Devices
Programmable macro logic primer

Application Note
AN029

Flip-Flop Merging
Figure 6a shows the positive edge triggered D flip-flop structure. By putting a two-level AND/OR structure in front of the data input, the D flip-flop can be steered from state to state.
Figure Sb shows such an input structure realized from a two-level NAND gate section.
Figure 6c shows this "AND-OR" structure rolled inside of the flip-flop. The gating was merged with the flip-flop inwards to make a faster, composite function. Whereas this may appear as a trick to the uninitiated, this degree of flexibility allowed gate array designers to merge a multitude of logic into a

fixed foundation. For highest efficiency, similar thinking allows the designer to break up decoders and multiplexers into their building blocks and generate only the pieces needed.
PLHS501 DESIGN EXAMPLE
The following example intends to manifest the capabilities of the PLHS501. Figure 7 shows a system formed with TTL logic. The system requirements make it imperative only to use discrete asynchronous latches. Thus, none of the 7 latches in the system can be directly replaced by registers. The system is

partitioned into two PLS173s and one PLS153. The specified PLD's are labeled with the same labels as those on the system schematic (Figure 7). Figure B shows the overall system implemented with PLDs. The logic condensation capabilities of PML makes it feasible to replace the whole system by a single PLHS501 (Figure 9). The PLHS501 in this design will still have ample space for any future additions.
The above example demonstrates only part of the PLHS501 capabilities. The introduction of PML devices and their immense logic power will pave the way for a new generation of efficient and elegant systems.

Figure 6a. Positive Edge Triggered D-Flip-Flop with Reset and Set

A B
c
D
Figure Sb. As in (A), with Input AND-OR Function

CLOCK RESETn

Figure Sc. As Above, with Integral AND-OR Input Function Figure 6. Flip-Flop Merging

!:
~
i
,3, f :;;:!
N
!
i ~ ~
.8
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1N2C,.._.j._..j... I

.,, ~

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3 3

"'51
i

~

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<D .8

3 ~

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i
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.C.D,

If )>
z
2 co f

Philips Semiconductors Programmable Logic Devices
Programmable macro logic primer

Application Note
AN029

IN1A IN1B IN1D IN1E IN1G IN1H IN11 IN1J INIL
IN2B IN2e
IN3e

IN1AL I IN1B[ I OT3G [ I IN1D[ I IN1E[ I OT3AIN1F[ I IN1G[ I IN1H[ I IN11[ I
IN1J CI
OT3EIN1K [ I GND[ I

µvcc op OUTll opounH-

op OUT1G--t-

;::. op OTIF

a: ~

o p OT1EIN3B

~

o p OUT1D op one

opop OT1BIN3A OUT1A

1poT2elN1M

1p1N1L

... OUTll
OUT10 OUT1A

IN1A [ I

pvce

IN2B[ I

ep

EI IN2eL I
IN1G

ep op OT2GIN3E---+-

IN11 L I L---1N1J[ I

N opommm

Ia-: ~

opoT2e1N1M

IN1B L I ~ opouT2e

§ OUT1G [ I

opouT20

"" OUT1H QI

op OUT2e

c: one [5 1
OT3AIN1F I

opour2e
op=

GNDq I

1poT3=:J

d OT1BIN3A I
d OT1EIN3B I

l:J Vee
ep

IN3ea1
a 0T2AN3D q I
r-- OT2GIN3E I
OT1FC 1

.,
Ia-: ~ i;i

ep op=
opopoT3G OUT3F

IN1L[ I .;.;.;. op OT2EIN1K-

"" IN1H LI

opouT3D

ornrnrrF Co

obouT3e

GND L

1p1N1G-

Figure 8. System in Figure 7 Implemented with PLDs

OT2GIN3E OUT2A
OT3G OUT3F OUT3D OUT3e
OT3AIN1F

Philips Semiconductors Programmable Logic Devices
Programmable macro logic primer

!!! ! !! !! ! ! !!

Vee

Vee

Application Note
AN029

-OUT1A

-our10

OT3AlN1F-

-

OUT11

-OUT2A

OT3G-

-OT2GIN3E

GND

GND

--.T'"T,.....,..,.....,.....,.,,_..,~...,..,...;.,..::,.,..::,.,..;::,,...:;...::,r-

0., .Q, Iu!.
8 8 i5
! ! !

Figure 9. System In Figure 7 Implemented with PLHS501

June 1988

744

Philips Semiconductors Programmable Logic Devices
Programmable macro logic primer

Application Note
AN029

THEPML2552
The PML2552 is the first CMOS PML part. Using an EPROM process, the PML2552 is a dense, fast multilevel PLO capable of making multiple independent state machines in a single part. The PML2552 has been optimized for handling data within the part and is ideal for making bus controllers and other microprocessor peripherals. Useful PML2552 applications areas include OMA controllers, DRAM controllers, Video memory controllers, FAX machines, hand held instruments, laser printers, digital and telecommunications.
The PML2552 combines 96 foldback NANO gates with 52 flip-flops in a 68 pin package. See the block diagram in Figure 10.
Foldback NANO gates are the easiest to use programmable elements. Because any function can be built from NANO gates, they have no inherent logic limitation. Foldback gates permit free connection of any gates in
the foldback region. This allows designers to
make any number of logic levels necessary to solve problems. Usually, the design software flattens the logic to exploit the wide inputs of these gates, but the designer easily maintains full control.
The choice of flip-flops has been done judiciously optimizing two 8 bit data paths within the part. Two groups of D flip-flops are

assigned to input pins, and two groups of D flip-flops are associated with output pins. The latter group may also be buried. Additionally, two groups of 1OJK flip-flops are buried for building efficient counters, shifters and other state machines. JK flip-flops require very little additional gating circuitry to make state machines.
Figure 11 shows a more detailed diagram of the PML2552, with the internal cell names broken out according to the conventions used with Philips Semiconductors SNAP software. An important point should be made with Figure 11 regarding internal timing specifications. Each cell shown in Figure 11 has been specified as if it were a gate array type cell. These specifications include the cell time delay (min,typ,max) and how the time delay increases with incremental loading. The details of the time delays are shown in the data sheet. The exact same values are automatically included in the simulation model which SNAP makes after a design compiles into the PML2552.
THE PML2852
Figure 10 shows a block diagram of the PML2852. The PML2852 is similar to the PML2552 except it has an additional 16 outputs. The 3-State control structure for pins
1100 -1/015 was changed from independent

control to two 8-bit groups in the PML2852.
All chip resources connect through the central array. It is possible to form logic functions of up to 96 levels by passing input signals repetitively through the 96 foldback NANO gates. Folded architectures permit free internal connection of buried gates and flip-flops. It is also possible to form logic functions from input to output in a single NANO level. Two groups of 10 buried JK flip-flops are within the programming array, along with two groups of 8 D flip-flops. Additional input flip-flops are available at the device pins. Several clocking options are available for the different flip-flop groups. The PML2852 has 84 pins. The PML2852 and PML2552 both are available in reprogrammable and one time programmable packages.
Typical propagation delays for the internal NANO gates are 15 nanoseconds. Flip-flop toggle rates are at 50 MHz, with some JK based counters operating at that rate.
The basic architectural rationale is to use the
input D flip-flops to capture data. Then, the
buried D flip-flops pipeline data and the JK flip-flops form counters, timers and control flip-flops. Of course, the JKs may act as shift registers as can the buried D flip-flops. Using D flip-flops for counter design is discouraged, but allowed. A wide class of data oriented applications fit this architecture well.

June 1988

745

Philips Semiconductors Programmable Logic Devices
Programmable macro logic primer

Application Note
AN029

16 INPUT DFUP.fLOPS
& 13 DEDICATED
INPUTS A
~
FOLDED NANO ARRAY
B
10 JK FLIP-FLOPS
WITH COMMON
CLK
c
10 JK FLIP-FLOPS
WITH DISTINCT
CLKS D

p

R 0

G

R

A

M

M

A B

16 OUTPUT D FLIP-FLOPS

L

E E

I

N

T

E

R
c
0 N

N

E
c

T

¢=>

24 Bl-DIRECTIONAL
I/Os

PML2852 only

June 1988

Figure 10. PML2552/PML2852 Functional Block Diagram 746

Philips Semiconductors Programmable Logic Devices
Programmable macro logic primer

Application Note
AN029

& ~
Oo :~-

:::@m'

B~x

B0-87

CllKDAA,~~~-8-,.~!..-c..-~-p1 D (9)JQlt--t_-·-~-~t_l,-·-:f--+:~-_-:-_Jt--+----+-+------+----t------+ll------t--4---t--1----++--+---+-l-l----t---l--1--+4------l-'t---
BFAx ~ -t-~+----,l---+-~~~-+----l~--+-~+--+--+~-+--j;111~~~·~8~~~

(~--t-~-t--+-~+-~~-+--+~-+--+--+~+--+---1~-+----

· . '~ "- 20 ·w·~·:··~·E·~Jo2 Q

T'--t-----<::: ·

- ~ -

Q--- ----~

··t··~@t

- ,rr---Q[]

./

OD~

Figure 11. SNAP PML2552 Resource Summary Designations

June 1988

747

Philips Semiconductors Programmable Logic Devices
Programmable macro logic primer

Application Note
AN029

TESTABILITY
Deep nesting of the buried flip-flops makes testability an important issue. Both controllability and observability of the flip-flops would be jeopardized if they were not scan chain configurable. By asserting the Scan Mode pin, the buried flip-flops form a large, multiplexed shift register (Figure 12). The shifter is controllable and observable. Parallel output of the most significant 16 bits of the shifter goes to the outside world. Alternatively, multiple PML2852s or PML2552s can cascade if correctly connected.

POWER DISSIPATION
All EE and EPROM based PLDs contain an NMOS core. An external CMOS image occurs because the 1/0 pads are CMOS. To improve on the power consumption, two techniques have evolved. One technique, input transition detection, automatically reduces power consumption by sensing input pin activity. The other technique uses a special power down pin. The power down pin blocks current flow into the chip core, reducing power consumption. The PML2552 and PML2852 use a power down pin. Power down presents the problem of maintaining the internal device state during power transition. Internal node conditions automatically latch when power down occurs, and restore upon power up. Full power consumption is 525 mW at maximum speed. In low power mode, this drops to one tenth that value.

DESIGN SOFTWARE
To support PML, a gate array style software package, called SNAP, is available from Philips. SNAP contains resources for equation and schematic capture (incorporating OrCADTM SOT and FutureNetTM DASH). SNAP includes a proprietary simulator and logic compilers for the entire Philips Semiconductors PLO family. The compilers use netlist synthesis and netlist optimization methods, and ultimately compile to JEDEC fusemap formats. A logic netlist model, including all internal node delays, is derived automatically from the JEDEC format. The derived model permits accurate device simulation.

SCOUT

1100

1101

1102

1103

V04

1105

1/06

1107

11015

1/014

11013

11012

11011

11010

1/09

1108

June 1988

(COMMON CLOCK (CKE1) FOR ALL FLIP-FLOPS WHEN IN SCAN
MODE)
Figure 12. SCAN Mode Operation Flip-Flop Chain
748

Philips Semiconductors Programmable Logic Devices
Programmable macro logic primer

Application Note
AN029

Targeting a PML2552/2852 Design
Key to a successful design is recognizing an appropriate mapping of internal resources to a specific design. The designer should think of JK flip-flops for counters and state machines, maximizing efficiency. As well, the input D flip-flops should be aimed at handling byte wide data applied to the input pins. The buried D flip-flops can be thought of as a natural landing place for output data, internally buffered data, shift registers, or simple state machines. Care should be taken to assign external clocks to the appropriate pins of the PML2552 or PML2852, because specific pins are dedicated as clock inputs to the internal flip-flops. SNAP may sometimes be used with automatic pinning mode, but this is often less than optimal.
By careful use of key flip-flop properties, a design can be easily forced to land in specific internal flip-flops. Remember, the PML2552/2852 has input D flip-flops, output D flip-flops, JK flip-flops with independent resets and JK flip-flops with independent sets. As an example, if a JK flip-flop equation is written, and its asynchronous set input is to a logical 1, then SNAP assumes that the JK

flip-flop is to be one which has an asynchronous set and assigns it accordingly. On the other hand, if the asynchronous reset is referred to, SNAP will map this to a JK flip-flop with an asynchronous reset input. It's usually that simple. If the designer uses a flip-flop which is not an available PML resource, SNAP will build it out of NANO gates in the foldback array. This is usually found during the compile phase when the resource summary exceeds the available foldback gates and the expected flip-flops go unused.
The most straightforward design method is simple incremental compiling. Incremental compiling is the logical approach to use with PML. Incremental compiling is simply taking a small piece of a design, capturing it (either equations or schematic} and compiling it into the part. During the compilation process, a small table is displayed showing the current usage of internal PML 2552 resources. Figure 13 shows such a small resource table. At this point, when the resources are examined, each cell should be accounted for. If not, there is either something wrong or the designer has misunderstood the part or the

mapping process. When the resource is correcdy mapped, it shows up in the table with the right tally. If not, the netlist may need examination.
By going incrementally, designs will progress systematically with only small surprises along the way. Usually, the surprises are that the design took fewer resources than expected. This is because the PML architecture is almost fully connectible, and SNAP optimizer is focused on flattening the design (for speed} to maximize wide internal gate usage.
As a suggestion, one very appropriate design method is to layout the data paths first, compile the design, then when everything fits appropriately, design in the control sections.
REFERENCES
1. Cavlan, Napoleone 1985. "Third Generation PLO Architecture Breaks AND-OR Bottleneck'', WESCON 1985 Conference Proceedings.
2. Wong, David K. "Third Generation PLD Architecture and its Applications", Electro 1986 Conference Proceedings.

Design from PML2552B.N2 - Created on Fri Jun 22, 1990

Device PML2552

Cell name used/total

========================================

CKDIN552

I 4 0%

CKNIN552

I 4 0%

FBNAND

59 I 96 61%

NAND

96 I 104 92%

DIN552

11 I 25 44%

NIN552

11 I 25 44%

CDIN552

3 I

75%

CNIN552

1 I

25%

CK552

1 I 4 25%

IDFF552

8 I 16 50%

BDIN552

0 I 24

0%

JKCL552

10 I 10 100%

JKPR552

10 I 10 100%

EXOR552

8 I 8 100%

TOUT552

20 I 24 83%

ODFF552

12 I 16 83%

3:19PM

Figure 13. PML2552 Resources Summary

1......... 1noo

749

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

DESIGN EXAMPLES
Most designers tend to view a PLO as a mechanism for collecting logical glue within a system. That is, those pieces which tie together the larger LSI microprocessors, controllers, RAMs, ROMs, UARTs, etc. However, there is a tendency of viewing a gate array as an entire system on a chip. PML based products will fit well in either casting as will be demonstrated by a series of small but straightforward examples. For starters, we shall examine how the fusing process embeds function, progress to glue-like decoding operations and finally demonstrate some coprocessor like functions as well as homemade "standard products".

The method of associating gates within the NANO foldback structure is depicted in Figure 1 wherein a simple three to eight decoder is fused into the array. The corresponding inputs are on the left and outputs at the top. This figure shows inputs and their inverse formed in the array resulting in a solution that requires 6 inverting NAN Os that would probably be best generated at the input receivers. Hence, this diagram could be trimmed by six gates, down to eight to achieve the function. Figure 2 shows two consecutive 0 flip-flop fusing images. Note that asynchronous sets and resets may be

achieved for free, in this version. In both Figures 1 and 2 the gates are numbered in a one-to-one arrangement. As well, the accompanying equations are in the format used by Philips SNAP design software. For clarity, consider the gate labeled 2A in Figure 1. Schematically, this is shown as a 3 input NANO. However, in the fused depiction, it combines from three intermediate output points with the dot intersect designation. Hence, all gates are drawn as single input NANOs whose inputs span the complete NANO gate foldback structure.

1 OF 8 DECODER/DEMULITPLEXER

EN
A B
c
@IDGIC BQUATIOlf AN ~ /A; BN = /B; CN = IC; ANN = /AN; BNN = /BN; CNN = /CN; E - /EN;
YO = / (AN * BN * CN * E); Yl = I ANN "' BN * CN * E): Y2 - / AN * BNN * CN * E); Y3 = / ANN * BNN * CN · E); * Y4 = / AN BN * CNN * E) ; YS = / ANN * BN * CNN * E); Y6 = / AN * BNN * CNN * E); * Y7 = / ANN i. BNN " CNN E) ;

BNN

ANN CNN

CN BN

~

AN

76543210E

A B
c

}~ ~i(

12

13

14

7

R ~

~

EN

~ l

'-

Figure 1. Decoder Implementation In NANO Foldback Structure

October 1993

750

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

@LOQIC SQUA!'IOX
DAl - / IDNl * SNl): SNl - / IDA * CLOCK! I RNl - / (SNl "' CLOCK! * DNl); DNl - / (DATAl * RNl I ; Ql - I (SNl * QNl); QNl .. I (RNl "' Ql);
DA2 = / (DN2 * SN2): SN2 - / (DA2 * CLOCK2)
* * RN2 - / (SN2 CLOCK2 DN2);
DN2 = / ~DATA2 * RN2): 02 - I (SN2 * ONl); QN2 - I (RN2 * Q2);

/CLOCK2 /CLOCKt
DATA2
DATAt

Q2 ~N2 01 ONt
:R=<:
~ &A 68 4A 48 SA 58 3A 38 tA tB 2A
~

Figure 2. Two Flip-Flops Implemented In the NANO Foldback Strucutre

One straightforward example of using a PLHS501 is shown in Figure 3. Here, the device is configured to accept the 23 upper address lines generated by a 68000 microprocessor. By selecting the direct and complemented variables, at least 16 distinct address selections can be made using only the dedicated outputs. The designer can combine additional VME bus strobes, or other control signals to qualify the decode or, define 8 additional outputs for expanded selection.

As well, the designer could transform the bidirectionals to inputs and decode over a 32 bit space, selecting combinations off of a 32 bit wide address bus. Because this simple level of design requires only NANO output terms plus 4 NANO gates in the foldback array (for inversion of signals connected to 03.00), there may be as many as 68 remaining gates to accomplish additional handshaking or logical operations on the input variables.

Figure 3. 68000 Microprocessor Address Decode

7"1

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

A"1"
A2 A3 A4 A5
A6 A7

110
111 101 100 011 010
001 000

~
~

vv

yY y

y

V'

-f1fB_
/LE 87 OUT7

n(B_
86 OUTS

(B_
f1
85 OUTS

v ~ vv y
~ ~

f1 fl

B4 OUT4

83 OUT3

v Vv iY

n (B_ ~ ~
f1 f1

B2 OUT2

81 OUT1

BO OUTO

Figure 4. 8-Bit Barrel Shifter Implemented with the PLHS501

An eight bit barrel shifter exploits most of the PLHS501 as depicted in Figure 4. This implementation utilizes all 72 internal foldback NAN Os in a relatively brute force configuration as well as 8 output NANDs to generate transparent latched and shifted results. The shift position here is generated by the shift 0, shift 1 and shift 2 inputs which are distinguished and selected from the input cells. Variations on this idea of data manipulation could include direct passing

data, mirror imaged data (bit reversal) or byte swapping to name a few.
Part of an eight bit, look-ahead parallel adder is shown in Figure 5. Gates necessary to form the level-0 generate and propagate, as well as the XOR output gates generating the resulting sum are not shown. The reader should be aware that this solution exploits four lay13rs of pyramided gates and only utilizes a total of about 58 gates. Additional comparison or Boolean operations could still

be generated with remaining NANO functions to achieve additional arithmetic operations. This application should make the reader aware of a new class of applications achievable with third generation PLDs - user definable 1/0 coprocessors. The approach of increasing microprocessor performance by designing dedicated task coprocessors is now within the grasp of user definable single chip solutions.

October 1993

752

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

P8
G7 P8 P7 G6 P8 P7
~
IG&----~

P6 GS G11 PS P&1
Id
cPoS
/G6
P7 G&
P7 P6
G~Sl
P6 PS
P7 P& PS
~

:~C1
/G11~

C&

;~~

P2

:;:,

C2

/G2

P&

GS

P3

P2 P1

C3

Iii

P2 G1

/G3------'

P4
G3 P4 P3 P2 P4 P3 P2 G1
/G4------'
~Dr--1P11
P1

Figure 5. Partial NANO Gate Equivalence of the 8-Bit Look-Ahead Adder

An example of one of the least efficient structures realizable on the PLHS501 is shown in Figure 6. Here. a cascade of 12 Hip-flops are formed into a toggle chain that used all available NANO gates in the main logic array. In the PLHS501 simple crosscoupled latches or transparent D latches are preferred over edge triggered flip-flops simply because they conserve NANO gates. Applications for structures like this include timing generators, rate multiplication, etc. Rearranging Figure 6 as a 12-bit shifter, picking off states at the output terms could result in a general purpose sequence recognizer capable of recognizing binary string sequences. These strings could be up to 13 bits long (in a Mealy configuration) and 24 distinct sequences could be sensed and detected.
Figure 7 shows a 32 to 5-bit priority encoder. This sort of device could generate encoded vector interrupts tor 32 contending devices. Of particular interest is the fact that ordinary encoders are not this wide. The designer is, of course, not constrained to generating combinational functions in even powers of two. Thus, the PLHS501 can easily perform customized functions like a 5 to 27 decoder or a 14 to 4 encoder or, even an 18 to 7 multiplexor. For the sake of optimization, the designer is encouraged to implement precisely the function he needs, no more and no lessl
The design examples given are illustrative of some typical operations used in ordinary systems. In each case, the example could be thought of as simply an "off the shelr standard solution to an every day problem (i.e., a de facto standard product).

October 1993

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application-Note
AN049
08

012

011

.010

09

09

07

Figure 6. 12-Blt Ripple Counter

October 1993

INPUT NAND OUTPUT BUFFERS ARRAY TERMS
Figure 7. Encoder
754

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

DEVELOPMENT SUPPORT
SNAP
Because the architecture encourages deep functional nesting, a new support tool has been developed. Synthesis, Nellis!, Analysis and Program (SNAP) software defines a gate array type development environment. SNAP permits several forms of design capture (schematic, Boolean equations, state equations, etc.), a gate array simulator with back annotation, waveform display and a complete fault analyzer and final fusemap compilation and model extraction. SNAP comes with a library of cells, and designs may be captured independently of the ultimate device that will implement the design. This permits the designer to migrate his design among a family of PML devices just as gate array designs can be moved to larger foundations when they do not route on smaller ones. Figure 8 shows the SNAP user interface "Shell" which dictates one sequence of operations to complete a design. Other sequences may be used.

The top portion of the shell depicts the paths available for design entry. Any design may be implemented in any one or a blend of all methods. For instance, a shift register might best be described schematically but a decoder by logic equations. These may be united with a multiplexor described by a text netlist as well. Ultimately, each form of input will be transformed to a function netlist and passed either to the simulation section or to the compiler section. Waveform entry is for simulation stimuli.
The simulator portion of SNAP is a 5-State gate array simulator with full timing information, setup and hold time checking, toggle and fault grade analysis and the ability to display in a wide range of formats, any set of nodes within the design. This permits a designer to zoom in with a synthetic logic state analyzer and view the behavior of any point in the design. Simulations can occur with unit delays, estimations or exact delays. The sequence of operations depicted in Figure 8 is entirely arbitrary, as many other paths exist.

It should be noted that the output of the 'merger" block represents the composite design, but as yet is not associated to a PML device. This occurs in the compiler portion wherein association to the device occurs and a fusemap is compiled. This is analogous to placement and routing in a gate array environment. Because of the interconnectibility of PML, this is not difficult. Once compiled, the exact assignment of pins, gates and flip-flops is known, so timing parameters may be associated and a new simulation model generated with exact detailed timing embedded. The design may be simulated very accurately at this point, and if correct, a part should be programmed.
To facilitate future migration to workstations, SNAP has been written largely in C. The internal design representation is EDIF (Electronic Design Interchange Format) compatible which permits straightforward porting to many commercially viable environments. SNAP currently utilizes OrCAD for schematic entry with eminent availability of FutureNetTM DASH.

MacSel

ScCapture Net Gen

Abel2Snap Edif

Equations NetConv

Minimizer

Merger

Waveforms

Test Vector SirnPrt

SirnFlt

DPI

Plot

Use cursor keys to select module Use function keys to enter command
Figure 8. SNAP Shell Design

FutureNet and DASH are trademarks of DATA 110

October 1993

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Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

PLHS501 EXAMPLES USING SNAP
· 8-bit barrel shifter
· 12-bit comparator with dual 1 of 8 decoders
· 8-bit carry look-ahead adder
· 32 to 5 priority encoder
· 4-bit synchronous counter
· VME EPROM interface
· Microchannel interface
· NuBus interface
· Data bus parity generator
· 16-bit comparator
Following are example applications for the PLHS501 using SNAP. They should not be viewed as showing all possible capabilities of the device. They have been designed to demonstrate some of the PLHS501 features, syntax of SNAP, and to give the reader some ideas for possible circuit implementations.
Note that these examples were written using SNAP Rev. 1.90. Although Philips will try to keep succeeding versions of SNAP compatible, it may be necessary to change some syntax rules. Therefore, please refer to your SNAP manual for any notes on differences, if using a revision later than Rev. 1.90.
8·BIT BARREL SHIFTER
This 8-bit shifter will shift to the right, data applied to A? - A9 with the result appearing on OUT? - OUTO. Data may be shifted by 1 to 7 places by indicating the desired binary count on pins SHIFT2 -SHIFTO. Data applied to the OUTO position for a shift of 1. For a shift of 0, A? will appear on OUT?.
Also included is a transparent latch for the output bits. The input 'COMPLMTO' will invert all output bits simultaneously and input /OE will 3-State all outputs.
This design was done by using OrCAD's SOT with SNAP. The top level drawing is shown in Figure 11. The PLHS501 has various output structures. For the best fit, it was necessary to alter the portion of the schematic connecting to pins 15 - 18 compared to pins 37--40. This is shown in Figures 12 and 13.

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*

PLHS501 52-Pin PLCC Package Pin Layout

*

* Date: 10/15/93

Time: 17:32:41 *

************************************************************

c

0
S S S M

H H HP P

IIIL I FFFM N

AAT T T TL 5

102100E2 +-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I 1515151414141

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I IIIIIIIIIIIII I 1 1111111 987 65 I 7 65 43210
I 81VCC

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A2 [ 91!18
A3 110 II19 A4 (111!20

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AS [121I21

!1142]

A6 [13 II22

IO 141]

A7 (141!23 L4 [151B4

/B3140] LO /B2139] Ll

LS [161BS

/Bll38] L2

L6 [171B6 L7 [181B7
(19100

/BOl37] L3 X7136] OUT? X6135] OUT6

(20 IGND

GNDl34]

I

I

I

I I I I

I

I 0 0 0 0 0 0 0 xxxxxx

I

I 12345 67012345

I

+----------------------------------+

121212121212121212131313131

111213141516171819101112131 +-+-+-+-+-+-+-+-+-+-+-+-+-+

0 0 0 0 0 0 uuuuuu

T T T T T T

012345

Figure 9. Barrel Shifter Pin List

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Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

MJr>-1>-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
At r>-o--~~~....+-~~~.-+-~~~-+-~~~>-~~--.-+~~~....+-~~~....+-~~~-+-~~~
A2r>-l>-~~~++-~~~H-~~......+-+-~~..-+->-~~H-+~~~++~~~H-~~~-+-~~ Mr>-1>-~~-.-+++~~..-+-1-+-~~-++-+-~~++->-~-MH-+~~~++~~~+-+-~~-1--+-~~ Mr>-0--~~-+-+++-~~++-1-+-~--.-+-++-+-~....+-++->-~-HH-+~~--+++~~>--+-+-~......+-+--+-~ ASn-0--~-.-+-+-+++-~-.-+-++-1-+-~H-+-++-+-~++-++->-~-HH-+~-.-+--+++~.-+->--+-+-~-++-+--+-~ A&r>-l>-~-++-++++-~++-++-1-+---;H-+-++-+-~++++-,__.-+--HH-+~-++--+++~+-H>--H--..-I-+++-_,__,
A70-l>--rl+t++++-+++H-l-hr-IH-t+t+r+-++++h-H-~H-t-r+++-+++.+-H-t--l-hH-t+t-t--h
110..-+++++++rl--H-H-tH-trl--H++++-h+--+-H-H-t-h+--l-H+++h+-++H-H-tTl---H-H++-t.+-+++++t-n 1111-+++++-h#l--H-H-tH.-1++--H+++h+t+--+-H-H-th-H-!--l-H++-hll+-++H-Hrltt--H-H-+-hrt!+-+++++-h 1011-+-t++hfH+l--++H-th-H-!++--H-t+-hll+l+--+-H-Hrl+IH---l-H-+-h-++H+-++H-h-H-!tt--H-H-h-llfttl--++++-TI tOOl-+-l+-hl\fH+l--++f-trlH-H-1++--H-+-hfH++l+--+-H-h-H-!+IH---1-H-h-ll-++H+-++++rH-fHtt--H-Hrittjfttt--+++nll Ottl-+-+-h-++HfH+l--+-l-h-H-!H-H-1++--H-MlfH++l+--+-++rH-fH+IH---1-Hrittj-++lf+-++Ml-H-fHtt--H-h+Hl-Hfttl--++h
0101-+-h-!lfH+fH+l--++rH-fHH-H-1++--Hrlt!jfH++l+--+-Mf-H-H-1+1H---l-h+HH1-++H+-++rl++l-H-fHtt--Hh-H-!HH1fttl--+~
0011-trlt!jfH+fH+l---h#H-H-IH-H-1++--h+Hl-HfH++l+--j,.l++!-H-H-l+IH---lh-H-!Hl-H-++H+--h#l++l-H-H-ltt--h++IH-Hl-Hfttl--h
OOOh+Hl-HfH+fH+!-.fH+H-H-IH-H-1++-h-H-!Hl-HfH++l+--.-H-l++l-H-H-l+IH--..l+IH-Hl-H-++H+-.fH+l++l-H-H-ltt-h-H-!+IH-Hl-Hfttl-~
SHIFTO~ SHIFTt ~ SHIFT2~

OUT2

OUTt

Figure 10. 8-Bit Barrel Shifter Schematic

OUTO

October 1993

757

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Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

U10 6
NA5 U9
NA5 1 U6 2 3 4 5
NA5 1 U7 2 3 4 5
NA5 U6
NA5 U5
NA5 1 U4 2 3 4 6
NA5 U3 6
NA5

U1 10
NA9 U2
NA2

Figure 12. Portion of Shifter to Connect lo NANO Output Pins

Application Note
AN049

October 1993

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Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

U10 6
NA5 U9

NA5

1 UB 2 3 4 5
NA5

1 U7

2

3

03

4 5

NA5

us

NA5
us

NA5 U4

U1 10
NA9

NA5 NA2
U3

NA5

Figure 13. Portion of Shifter to Connect to AND Output Pins

Application Note
AN049
I'

October 1993

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Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

************************************************************

*

PLHSSOl 52-Pin PLCC Package Pin Layout

*

* Date: 10/15/93

Time: 17:44:04 *

************************************************************

AA

AAAllAABBBBBB

4321 01 0 98765 4

+-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I JSJSJSJ4J4J4J

)7)6)5)4)3)2)1)2)1)0)9)8)7)

+----------------------------------+

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J

I 1 1 1 1 1 1 1 1 9 e7 6 s

I

I

7 6s4321o

I

I

I

SJVCC

VCCJ46]

AS [ 91I18

I4)45] B3

A6 [10JI19

I3J44] B2

A7 [11JI20

I2J43] Bll

AS [121I21

Il)42] BlO

A9 [13JI22

I0141] Bl

BO [141I23

/B3140] CMPOOT

[151B4

/B2)39] DA2

EHCOMI? [16JBS

/BlJ38] DAl

DCDREH [17JB6

/BOJ37] DAO

RW [181B7

X7)36] R7

WO [19)00

X6J35] R6

[20IGHD

GHDl34]

I

I

I

I I I I

I

I oooooooxxxxxx

I

I 1 2 3 4 s 6 7 o1 2 3 4 s

I

+----------------------------------+

121212121212121212131313131

11121314151617)8)9)0)112131

+-+-+-+-+-+-+-+-+-+-+-+-+-+

WWWWWWWRRRRRR

12345 67012345

Figure 14. 12-Blt Comparator Pin List

12-BIT COMPARATOR WITH DUAL 1-0F-8 DECODERS Two functions that are very often associated with controlling 1/0 parts are address comparison and address decoding. In this example, both functions are programmed into a PLHS501 using 52 out of the 72 foldback NANO terms.
The comparator compares 12 bits on inputs A11 -AO to inputs B11 - BO when the input 'ENCMP' is High. Output 'CMPOUT' will become Active-Low when all 12 bits of the A input match the B. Selection between the two decoders is done with input 'R/W". Only one output may be active (Low) at a time. Although currently separate functions, the decoder enable may be derived internally from 'CMPOUT' freeing 2 bidirectional pins which together with available loldback NANO terms, may be used to incorporate a third function.

A11-AO 811-BO

COMPARE

CM POUT

ENCOMP

DA2

W7-WO

DA1

DUAL

DAO

10F8

DECODERS

RW

R7-RO

DCDREN
Figure 15. 12-Bit Comparator with Dual 1 - 8 Decoders Block Diagram

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Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

"FILENAME: CMP12BIT.EQN"

12-bit address comparator and dual 1 of 8 decoders"

@PINLIST

BO

I;

Bl

I;

B2

I;

B3

I;

B4

I;

BS

I;

B6

I;

B7

I;

BS

I;

B9

I;

BlO

I;

Bll

I;

AO

I;

Al

I;

A2

I;

A3

I;

A4

I;

AS

I;

A6

I;

A7

I;

AS

I;

A9

I;

AlO

I;

All

I;

DAO

I;

DAl

I;

DA2

I·

RW

I;

DCDREN I;

ENCOMI? I;

WO

O·

Wl

O;

W2

O;

W3

O;

W4

O;

WS

O;

W6

O·

W7

O;

RO

O;

Rl

O;

R2

O;

R3

O;

R4

O;

RS

O;

R6

O;

R7

O;

CMPOUT O;

@LOGIC EQUATION

"COMMON PRODUCT TERM" adO=/da2*/dal*/daO*dcdren; adl=/da2*/dal* daO*dcdren; ad2=/da2* dal*/daO*dcdren; ad3=/da2* dal* daO*dcdren; ad4= da2*/dal*/daO*dcdren; adS= da2*/dal* daO*dcdren; ad6= da2* dal*/daO*dcdren; ad7= da2* dal* daO*dcdren;

October 1993

Figure 16. 12-Bit Comparator Boolean Equations (1 of 2) 762

Application Note
AN049

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples
"12-Bit Address Comparator"
axbO aO*/bO + /aO*bO; axbl al*/bl + /al*bl; axb2 a2*/b2 + /a2*b2; axb3 a3*/b3 + /a3*b3; axb4 a4*/b4 + /a4*b4; axb5 a5*/b5 + /a5*b5; axb6 a6*/b6 + /a6*b6; axb? a?*/b? + /a?*b?; axb8 a8*/b8 + /a8*b8; axb9 a9*/b9 + /a9*b9; axblO = alO*/blO + /alO*blO;
axbll = all*/bll + /all*bll; cmpout = /(/axb0*/axbl*/axb2*/axb3*/axh4*/axb5*/axb6*/axb7*/axb8*/axb9*
/axblO*/axhll*encornp);
liDual 1 of 8 decoders
da2-da0 are address inputs dcdren is an enable input rw selects which group of 8 outputs r7-r0 or w7-w0
will have the decoded active low output"
w? /(ad?*/rw); w6 /(ad6*/rw); w5 /(adS*/rw); w4 /(ad4*/rw); w3 /(ad3*/rw); w2 /(ad2*/rw); wl /(adl*/rw); wo /(adO*/rw);
r1 /(ad?* rw); r6 /(ad6* rw); rs /(ad5* rw); r4 /(ad4* rw); r3 I (ad3* rw); r2 I (ad2* rw); rl /(adl* rw); rO /(adO* rw);
Figure 16. 12·Bit Comparator Boolean Equations (2 of 2)

Application Note
AN049

October 1993

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Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

8-BIT CARRY LOOK-AHEAD ADDER
This function may be used as part of an ALU design or simply to off-load a microprocessor. Figure 18 is a block diagram showing the individual components needed for each bit.
A carry input (CO) is provided along with a carry output (CS). The result of an addition between the inputs A7 - AO and 87 - BO occurs on outputs SUM7-SUMO.

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*

PLHSSOl 52-Pin PLCC Package Pin Layout

*

* Date: 10/15/93

Time: 17:50:08 *

************************************************************

AAAAAAA

6543210

+-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I 1515151414141

171615141312111211101918171

+----------------------------------+

I

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1111111198 765

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I VCCl46]

A7 I 9II1B BO (10 I I19

14145]
13144] co

Bl (111120

12143] B7

B2 (12I121

Ill42] B6

B3 (131122

IO 141] BS

B4 (141 I23

/B3140]

[151B4

/B2 I 39]

[161BS

/Bl 138]

[17IB6

/BO 137]

[18 IB7

X7136] SUM7

CB (19100

X6135] SUM6

(20 IGND

GNDl34]

I

I

I

I I I I

I

I 0 0 0 00 0 0 xxxxxx

I

I

123 45 67012 3 45

I

+----------------------------------+

121212121212121212131313131

111213141516171819101112131

+-+-+-+-+-+-+-+-+-+-+-+-+-+ s s s s s s u u u u u u

MMMMMM

012345

Figure 17. 8-Bit Adder Pin List
wwww A A A ~:: :~g~~g mEL-OFUNCTIONS

G4 P4

G3 P3 GROUP I

G2 P2

G1 Pl

! ! ! ! ! ! ! ~ LEVEL·1

I I 02·

AUXILIARY

FUNCTIONS

NOTES:
G1'· G4 + P4 ·G3+P4 ·p3 ·a2 + P4 ·p3 ·p2 ·a1; Pr .p4 ·p3· P2 ·Pl ~·-~.~·w.~·~·~.~·~·~·a~ P2'. PS· P7'PS · P5

C1 -G1 + P1 ·co;
C2.G2+ p2· G1 + P2' P1 ·CO;
~=OO+~·m.~·~·a1+~·~·p1·~;
C4 = Gl' + P1 .. CO; C5-G5+ P5 ·a1·+PS. P1' ·co;
C6=G6+ P6. GS+ P6. PS* Gl' +PG ·p5. P1' ·co;
C7-G7 + p7· GS+ P7. PS 'G5+ P7. PS' P5. G1' +P7. PS. P5. P1' ·co;
CB= G2' + P2'. G1'+ P2'. P1' ·co;

Figure 18. 8-Bit Carry Look-Ahead Adder Block Diagram and Equations

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Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

NFILENAME: ADDRSBIT.EQN 8 Bit Carry Look-Ahead Addern

@PINLIST

AO

I;

Al

I;

A2

I·

A3

I;

A4

I;

AS

I;

A6

I;

A7

I;

BO

I;

Bl

I;

B2

I;

B3

I;

B4

I;

BS

I;

B6

I;

B7

I;

CO

I·

cs

O;

SUMO

O;

SUMl

O;

SUM2 O;
SUM3 o·

SUM4

O;

SUMS O;

SUM6

O;

SUM?

o·

@LOGIC EQUATION

"level-0 functions"

gnl = I (aO*bO); pl = I (/aO*/bO); 91 = /gnl;
= gn2 /(al*bl);
p2 = I (/al*/bl); 92 = /gn2;
gn3 = I (a2*b2); p3 = /(/a2*/b2);
= 93 /gn3; = gn4 /(a3*b3);
p4 = I (/a3*/b3);
= 94 /gn4;
gnS = /(a4*b4);
pS = /(/a4*/b4); 95 = /gnS;
gn6 = I (aS*bS);
p6 = I (/aS*/bS); 96 = /gn6;
gn7 = I (a6*b6); p7 = I (/a6*/b6);
= 97 /gn7; = gnB /(a7*b7);
pS = /(/a7*/b7);
98 = /gnS;

"level-1 functions"
= 91_1 94 + p4*93 + p4*p3*92 + p4*p3*p2*9l; = 92_1 98 + p8*97 + p8*p7*96 + p8*p7*p6*9S;

October 1993

Figure 19. 8-Bit Adder Boolean Equations (1 of 2) 765

Application Note
AN049

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

·carry information·

= cl gl + pl*cO; = c2 g2 + p2*gl + p2*pl*c0; = c3 g3 + p3*g2 + p3*p2*gl = c4 gl 1 + p4*p3*p2*pl*c0;

+ p3*p2*pl*c0;

= c5 s g5- + pS*gl_l + p5*p4*p3*p2*pl*o0;
c6 g6 + p6*g5 + p6*p5*g1_1 + p6*p5*p4*p3*p2*pl*c0;

= c7 · g7 + p7*g6 + p7*p6*g5 + p7*p6*p5*g1_1 + p7*p6*p5*p4*p3*p2*pl*c0;

08 g2_1 + p8*p7*p6*p5*g1_1

+ p8*p7*p6*p5*p4*p3*p2*pl*c0;

"addition function·"

sumo ~ co + (pl * gnl) suml = cl + (p2 * gn2)
sum2 = c2 + (p3 * gn3)
= sum3 = c3 + (p4 * gn4)
sum4 c4 + (p5 * gn5) sum5 = c5 + (p6 * gn6)
= sum6 c6 + (p7 * gn7) = sum7 c7 + (p8 * gn8)

Figure 19. 8-Blt Adder Boolean Equations (2 of 2)

October 1993

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Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

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AN049

************************************************************

*

PLHSSOl 52-Pin PLCC Package Pin Layout

*

*Date: 10/15/93

Time: 17:58:06 *

************************************************************

IIIIII I IIII

111113I 3I 2222

543211002 9876

+-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I 1515151414141

171615141312111211101918171 +----------------------------------+

I IIIIIIIIIIIII

I

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I

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SIVCC

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Il6 [ 9II18

I4145] I25

Il7 [10 II19

I3 I 44] I24

IlS [111 I20

I2143] I23

I19 [121I21

Ill42] I22

I1 [131 I22 I20 [141I23

IOl41] I21
/B3 I 40J no

I3 [151B4

/B2139] I9

I4 [161B5

/Bll38] IS

IS [17 IB6

/B0137] I7

I6 [181B7

X7l36]

AO [19100

X6135]

[20 IGND

GNDl34]

I

I

I

I I I I

I

I

0 0 0 0 0 0 0 x x x x x x

I

I

12345 67012345

I

+----------------------------------+

121212121212121212131313131

111213141516171819101112131 +-+-+-+-+-+-+-+-+-+-+-+-+-+

AAAA

EG

l 234

0 s

Figure 20. Encoder Pin List

32- to 5-BIT PRIORITY ENCODER
This relatively simple example demonstrates the capability of the PLHS501 to be programmed with functions that are not available in 'standard' device libraries. The equations may look difficult at first glance. However, there is a pattern to the encoding. Referring to Figure 21, Lab4-Lab1 are terms that are common to several outputs (A4n - AOn). Separating them from the main equations allows a total reduction in the numbers of gates used.

131-10

32to 5 PRIORITY ENCODER

A4-AO

Figure 21. 32 to 5 Priority Encoder Block Diagram

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Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

October 1993

"FILENAME: ENCODER.EQN 32 TO 5 PRIORITY ENCODER"

@PINLIST

IO

I;

Il

I;

I2

I;

I3

I;

I4

I;

IS

I·

I6

I;

I7

I;

IS

I;

I9

I·

IlO

I;

Ill

I;

!12

I;

!13

I;

!14

I;

IlS

I;

!16

I;

!17

I;

!18

I;

!19

I·

I20

I;

I21

I;

I22

I;

I23

I;

I24

I;

I25

I;

!26

I;

I27

I;

I28

I;

I29

I;

I30

I;

I31

I·

AO

o;

Al

O;

A2

O;

A3

o·

A4

o·

GS

O;

EO

O;

@LOGIC EQUATION

"COMMON PRODUCT TERM" cptl i26*i27*i2B*i29*i30*i31 cpt2 i20*i2l*i22*i23*i24*i25 cpt3 il4*il5*il6*il7*il8*il9 cpt4 i8*i9*il0*ill*il2*il3;

AO=/ ( /i31 +/i29*i30*i31 +/i27*i28*i29*i30*i31 +/i25*cptl +/i23*i24*i25*cptl +/i2l*i22*i23*i24*i25*cptl +/il9*cpt2*cptl +/il7*il8*il9*cpt2*cptl +/il5*il6*il7*il8*i9*cpt2*cptl +/il3*cpt3*cpt2*cptl +/ill*il2*il3*cpt3*cpt2*cptl +/i9 *i10*ill*il2*il3*cpt3*cpt2*cptl +/i7 *cpt4*cpt3*cpt2 +/iS *i6*i7*cpt4*cpt3*cpt2*cptl +/i3 *i4*i5*i6*i7*cpt4*cpt3*cpt2*cptl +/il *i2*i3*i4*iS*i6*i7*cpt4*cpt3*cpt2*cptl);

Al=/( /i31 +/i30*i31 +/i27*i28*i29*i30*i31 +/i26*i27*i28*i29*i30*i31

Figure 22. Encoder Boolean Equations (1 of 2)

768

Application Note
AN049

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

October 1993

+/123*124*12S*cptl +/122*123*124*12S*cptl +/i19*cpt2*cptl +/118*119*cpt2*cptl +/115*116*117*118*119*cpt2*cptl +/114*115*116*117*118*119*cpt2*cptl +/111*112*113*cpt3*cpt2*cptl +/110*1ll*il2*113*cpt3*cpt2*cptl +/17 *cpt4*cpt3*cpt2*cptl +/16 *17*cpt4*cpt3*cpt2*cptl +/13 *14*15*16*17*cpt4*cpt3*cpt2*cptl +/12 *13*14*15*16*17*cpt4*cpt3*cpt2*cptl);
1.2.=/ ( /131 +/130*131 +/129*130*131 +/128*129*130*131 +/123*124*12S*cptl +/122*123*124*12S*cptl +/121*122*123*124*12S*cptl +/120*12l*i22*123*124*12S*cptl +/115*116*117*il8*119*cpt2*cptl +/114*115*116*117*118*119*cpt2*cptl +/113*cpt3*cpt2*cptl +/112*113*cpt3*cpt2*cptl +/17 *cpt4*cpt3*cpt2*cptl +/16 *17*cpt4*cpt3*cpt2*cptl +/15 *16*17*cpt4*cpt3*cpt2*cptl +/14 *15*16*17*cpt4*cpt3*cpt2*cptl);
:A3=/( /131 +/130*131 +/129*130*131 +/128*129*130*131 +/127*128*129*130*131 +/126*127*128*129*130*131 +/i25*cptl +/124*12S*cptl +/115*116*117*118*119*cpt2*cptl +/il4*115*116*117*118*119*cpt2*cptl +/113*cpt3*cpt2*cptl +/112*113*cpt3*cpt2*cptl +/111*112*113*cpt3*cpt2*cptl +/110*111*112*113*cpt3*cpt2*cptl +/19 *110*111*112*113*cpt3*cpt2*cptl +/18 *19*110*ill*112*113*cpt3*cpt2*cptl);
A4=/( /131 +/130*131 +/129*130*131 +/128*129*130*131 +/127*128*129*130*131 +/126*127*128*129*130*131 +/i2S*cptl +/i24*i2S*cptl +/123*124*12S*cptl +/122*123*124*12S*cptl +/121*122*123*124*i2S*cptl +/120*12l*i22*123*124*12S*cptl +/i19*cpt2*cptl +/118*119*cpt2*cptl +/117*118*119*cpt2*cptl +/116*117*118*119*cpt2*cptl);
eo /(10*11*12*13*14*15*16*17 *18*19*110*111*112*113*114*115 *116*117*118*119*120*121*122*123 *124*12S*cptl);
qs /eo;
Figure 22. Encoder Boolean Equatlona (2 of 2)
769

Application Note
AN049

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

4-BIT SYNCHRONOUS COUNTER
This counter produces a binary count on outputs Count3 - CountO. Note the required reset (RST) input to initialize all of the flip-flops. The inputs for each ftip-flop were first determined by drawing the desired output waveforms. Next, Kamaugh maps were used to reduce the number of terms and determine the logic equations for the input to each flip-flop. This technique could be used to construct a counter whose outputs produce some count other than binary.
The simulation only consists of a reset, followed by a number of clocks to count from 0 through 15 and back to O.

************************************************************

*

PLHS50l 52-Pin PLCC Package Pin Layout

*

* Date: 10/18/93

Time: 09:51:23 *

************************************************************

RC

SL

TX

+-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I 1515151414141

171615141312111211101918171 +----------------------------------+

I IIIIIIIIIIIII

I

I l l l l l l l l 987 65

I

I 765432l o

I

I 81VCC

I VCCl46]

[ 91Il8

I4145]

[101Il9

I3144]

[ll1I20

I2143]

[12II21

Il 142]

[131I22 [141I23

I0141] /B3140]

COUll'TO [15IB4

/B2139]

COUll'U [161B5

/Bll38]

COUll'T2 [17IB6

/BOl37]

COUll'T3 [181B7

X7136]

TC [19100

X6135]

[20IGND

GNDl34]

I

I

I I

I I I I
oooooooxxxxxx

I I

I l 2345670l 2345

I

+----------------------------------+

121212121212121212131313131

111213141516171819101112131 +-+-+-+-+-+-+-+-+-+-+-+-+-+

Figure 23. 4·Blt Counter Pin Ust

October 1g93

no

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

n4 bit synchronous eounter·

(!PIHLIST

CL1t

I;

RST

I;

COUR'l'O O;

COURU O;

COURT2 O;

COURT3 O;

TC

O;

@LOGIC BQUATIOll

·IJIPUTS !!'OR BllCR !!'LIP-FLOP·

DATAl · ((CQl*CQJIO) + (CQJll*CQO));
= DATA2 = ((CQO*CQl*CQJl2) + (CQJIO*CQ2) + (CQJ1l*CQ2));
DATA3 ((CQJ12*CQ3)+(CQHO*CQ3)+(CQO*CQl*CQ2*CQJl3)+(CQJll*CQ3));

"4 D-T1PB FLIP FLOPS COHHBCTBD AS A SYHCllROHOUS COURTER"

= CSNO
= ClUIO
= CQO

/(CLlt*RST*(/(CSHO*(/(CQHO*RST*ClUIO))))); /(CSNO*CLK*(/(CQNO*RST*ClUIO)));
/(CSHO*CQJIO);

CQNO = /(ClUIO*CQO*RST);

= CSNl /(CLlt*RST*(/(CSHl*(/(DATAl*RST*ClUll))))); = ClUll /(CSNl*CLK*(/(DATAl*RST*ClUll)));
CQl m /(CSHl*CQJll); CQNl · /(ClUll*CQl*RST);

= CSN2 /(CLK*RST*(/(CSN2*(/(DATA2*RST*ClUl2)))));
ClUl2 · /(CSN2*CLlt*(/(DATA2*RST*ClUl2))); CQ2 · /(CSN2*CQN2); CQJl2 I (ClUl2*CQ2*RST) ;

= CSN3 = ClUl3 = CQ3 = CQJ13

/(CLK*RST*(/(CSH3*(/(DATA3*RST*ClUl3))))); /(CSN3*CLK*(/(DATA3*RST*C1U13))); /(CSN3*CQJl3); /(ClUl3*CQ3*RST);

"Connection to output pins"

countO=aqO; countl=aql; count2=cq2;
count3=aq3;

"TBRMDIAL COURT PIN"

TC=(CQO*CQl*CQ2*CQ3);

Figure 24. 4·Blt Counter Boolean Equations

Application Note
AN049

October 1993

771

Philips Semiconductors Programmable logic Devices
PLHS501 design examples

Application Note
AN049

VME Bus EPROM Interface The idea for this VMEbus EPROM board came from WIRELESS WORLD CIRCUIT IDEAS, January, 1988. The implementation Was done by a PhHips' FAE, John McNally.
The board contains two banks of EPROMs. Each bank consists of either two 27128s or two 27256s; each of which can be enabled by comparing the address location lo the board. Decading three other address bits selects which of the banks is accessed. A 4-bit shift register combined with four jumpers provide wait states.
The circuit drawing was entered onto a PC using FutureNet DASH, a schematic capture

package (Figures 25, 26, and 27). It was then converted to logic equations using SNAP (Figures 29 and 30) and then assembled into aPLHS501.
This application, which originally needed eight ICs, used forty-four of the available seventy-two NANO Foldback Terms and forth of the available fifty-two pins. As the PLHS501 contains no registers, an edge-triggered D-type flip-flop was designed using NANO gates and this is used as a soft macro in order to Implement the shift register function (Figure 27).

As suggested in the original article, the circuit could be expanded to access up to eight ROM banks (Figure 288). This was achieved by editing the logic equation file and adding extra equations (Figure 32). Modifying the drawing, although fairly easy to do, was not considered necessary as the object was to design with PML and not TTL. The expanded circuit would require another three TTL IC packages, brining the total to eleven if done using TTL devices. The number of foldback terms increased to fifty-five, with the number of pins rising to fifty. Figure 28 shows the pinout of both versions.

740 1 .... 2

ENADO

~ /A5 1

I - - - - < - - -V'e=e

~

l-'19...__f--~>-:::=--------_.>--------''MASE~~L

.J!!L....L

,_,18~_.___._GND

_!!L..!.._

1L

GND

1 7432
2J )3

S18 5

16

S22

G2

A19 &

15

A23

~

14

~

13

~

12

~

11

~

S22 A22 821
A21 1 ~2
"""

1 2

J743~2~3-'--+--1!..'!"743-2

-

2] )3

G4

G5

A1& 1 .--z!!!!-I - - -

IR-W

~
._!.._
~
Y+
f - ~ - - - + ' ' - 1

15 ROllll

b..H_.JL....!!RO~M1,,,__-l--l+---'1~74-..3;_, 3 /ROM1LO

13 NC

2

=-..=:=:=

:: :::;

G6

10 NC NC

1 7432 2 "'=3--'-"IR:::OM1=11

GB

1 7432
2J .:>3 /ROM1LO
G7
1 7432 2 ) )->"3_1R=OM"'1"'11
a;

ENDATLO ENDATll

/DSO /DS1 R-WN

/DTACK

2 7402
WAIT 31 ./ 1 G10

(SOURCE: WIRELESS WORLD, JAN. 19811, CIRCUIT IDEAS)

CKBMZ

Figure 25. VME- EPROM Interface

October 1993

772

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

PN CK
0

7404 EL 1
G1
GNO
CLBMZ

SET OFFS

12

Q

QN
GS G4

1 7400

ON

G6

Figure 26. Edge-Triggered D Flip-Flop (OFFS)

OFFS

OFFS

OFFS

Figure 27. 4-Bit Shifter (7495)

October 1993

773

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

October1993

A.

2 ROM BANKS AS ORIGINAL CIRCUIT.

REPLACES 8 PACKAGES - USES 48 FOLDBACK TERMS

St7

/AS

!ill

At&

St9

A17

S20

At8
A1I

.~ ..m

A20

S23

vcc

l716 5 4 3 2 t 52 5t 50 49JaJ1

8

48

vcc

A2t

9

__.§_ WAIT

.AZ:!

10

44

N/C

A23

11

43 CKBMZ

/DSO

t2

i!!i1 ii

PLHS50t

42

N/C

4t

N/C

R-WN t4

Qjj_:

t5

40 /R-W 39 DTAK

Qt

t6

gg_

t7

38 /DTACK 37 /MASEL

Q3

t8

38

N/C

/ROMOLO t9

35

N/C

GND

20 VMEEXP

34

GND

/ROMOll /ROMtLO /ROMtll N/C N/C NIC

J21}22 23 24 25 26 27 28 29 30 3t l32133

N/C N/C NIC E@/ITll ENDATLO ENADD NIC

8.

EXPANDED TO 8 ROM BANKS

REPLACES tt PACKAGES - USES 55 FOLDBACK TERMS

St7

IA5

Sta

Alf..

St9

At7

S20

At8

S2t

At9

S22

A20

S23

vcc

8

A2t

9

A22

to

A23

tt

/DSO

t2

/DSt

t3

R-WN t4

REG

t5

ENADD t6

ENDATLO t7

ENDATll t8

IROMOLO t9

GND

20

i716 5 4 3 2 t 52 5t 50 49148147

46

vcc

45

W2

44

Wt

43 CKBMZ

42

N/C

PLHS50t

4t

N/C

40

/R-W

39 ::DJAK

38 /DTACK

37 /MAS EL

36 /ROM7HI

35 IROM7LO

FULLEXP

34

GND

IROMOll IROMtLO IROMtll IROM2LO /ROM2HI IROM3LO

J2}2 23 24 25 28 27 28 28 30 31132133

/ROM6HI /ROM&LO /RQM§HI /ROMSLO /ROM4HI IROM4LO /ROM3HI

Figure 28. VMEEXP and FULLEXP 774

Application Note
AN049

Phiflps Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

*********P*L**B*S*5*0*1**5*2*-*P*i*n**PL*C*C***P*a*c*k*a*g*e**P*i*n**L*a*y*o*u*t***************

* Date: 10/24/93

Time: 17:24:59 *

************************************************************

AAAAA SSSSSSS

2 1 1 1 1 A1 1 1 2 2 2 2

0 987 65 78 901 23

+-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I 1515151414141

171615141312111211101918171

+----------------------------------+

I IIIIIIIIIIIII

I

I 1111111198765

I

I

7 65 4321o

I

I 81VCC

I
VCCl46]

A21 [ 91Il8

:1:4145] WAIT

A22 [101Il9

I3 I 44]

A23 [111I20

I2143] CXBMZ

DSO [12 II21

Ill42]

DSl [131I22

IOl41]

RD [141I23

/83140] RW

QO [15184

/82139] DTACK

Ql [16185

/81138] NDTACK

Q2 [17186

/80137] MASEL

Q3 [18187

X7136]

ROMOLO [19100

X6135]

[20 IGND

GNDl34]

I

I

I

I I I I

I

I oooooooxxxxxx I

I 1234567012345

I

+----------------------------------+

121212121212121212131313131

111213141516171819101112131

+-+-+-+-+-+-+-+-+-+-+-+-+-+

RRR

EEE

000

NNN

HMM

ADD

0 1 1

DA A

HL H

DT T

I 0I

L H

0 I

Figure 29. VMEEXP PLHSS01 Plnllsl

October 1993

775

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

8PINLIST

WAIT

I;

CllBllZ

I;

DS[l ·· OJ I;

1Ulll

I;

AS

I;

A[16 .·23] I;

S[17 ·· 23] I;

Q[O ·· 3] O;

ROMO LO

O;

ROMOBI O;

ROIQLO

O;

ROlllBI

O;

BRADD

O;

BHDATLO O;

BllDATBI O;

RW

O;

HDTACX O;

DTACX

O;

llllSBL

O;

@LOGIC BQUATIOHS

R03 · (/(MASBL*S03*CDMZ*D03));
= S03 (/(CKBMZ*(/(S03*D03*MASBL)))); = D03 (/(Q2*R03)); = R02 (/(MASBL*S02*Cla!MZ*D02));
S02 · (/(CKBMZ*(/(S02*D02*MASBL)))); D02 · (/ (Ql*R02));
= ROl (/(MASBL*SOl*Cla!MZ*DOl)); = SOl (/(CKBMZ*(/(SOl*DOl*MASBL)))); = DOl · (/ (QO*ROl) ) ;
ROO (/(MASBL*SOO*CDllZ*DOO)); SOO · (/ (Cla!MZ* (/ (SOO*DOO*MUBL))));
DOO = (/ (O*ROO)) ;

= ROMOLO = (/DSO+ (/ (/.ll6*MASBL))) ;
ROMOBI (/DS1+(/(/.ll6*MlUIBL))); ROMl.LO = (/DSO+ (/ ( A16*MASBL)) ) ; ROMlBJ: = (/DSl+ (/ ( A16*1111SBL)));
= QO (/((/(ROO*QO))*SOO*(MASBL))); = Ql (/((/(ROl*Ql))*SOl*(MASBL))); = Q2 (/((/(R02*Q2))*S02*(MASBL))); = Q3 (/((/(R03*Q3))*S03*(MASBL)));

KASEL · / (/ (/ (/ ((A17*S17+/A17*/S17)

* (A18*S18+/A18*/S18)

*(A19*S19+/A19*/S19)

*(A20*S20+/A20*/S20)

*(A21*S21+/A21*/S21)

*(A22*S22+/A22*/S22)

*(A23*S23+/A23*/S23)

*(AS)))));

HDUC:K = / ((/ (MllSBL+WAIT)) *RWll);

DTACX D /HDTACX;

RW

= / (RWll) ;

BllADD = AS;

= ( BHDATLO = ((RW+MASEL)+/DSO);
EHDATHI (RW+MASEL) +/DSl);

Figure 30. VllEEXP PLHS501 .BEE File

Application Nole
AN049

October 1993

776

Phinps Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

************************************************************

*

PLHS501 52-Pin PLCC Pacltaqe Pin Layout

*

* Date: 10/24/93

Time: 16:42:18 *

************************************************************

AAAAA S S S S S S S

2 1 1 1 1 A1 1 1 2 2 2 2

0 987 65 78 90123

+-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I 1515151414141

171615141312111211101918171
+----------------------------------+

I IIIIIIIIIIIII

I

I 111111 1198765

I

I

7 654321o

I

I

I

81vt:C

vt:Cl46]

A21 [ 91I18

I4145] WO

A22 [101I19

I3144] Wl

A23 [111I20

I2143] CKBMZ

DSO [12II21

Ill42]

DSl [131I22

IOl41]

RllN [141I23

/B3l40) RW

REG [151B4

/B2139] DTACK

DADD [16 IB5

/Bl 138) HDTAC!t

ENDATLO [171B6

/BDl37] M1'SEL

BJIDATllI [181B7

X7136] ROM7HI

ROMOLO [19100

X6135] ROM7LO

[201GHD

GNDl34]

I

I

I

I I I I

I

I oooooooxxxxxx I

I 1 2 3 4 5 6 7 o1 2 3 4 5

I

+----------------------------------+

121212121212121212131313131

111213141516171819101112131
+-+-+-+-+-+-+-+-+-+-+-+-+-+

RRRRRRRRRRRRR

0000000000000

MMMMMMMMMMMMM

01122334455 66

HLHLHLBLHLBLB

I 0 I 0 I 0 I OI 0 I 0 I

Figure 31. FULLEXP Plnllat

October 1993

777

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

@PINLIST

CK8MZ

I;

DS[l ·· OJ I;

R.Wll

I·

AS

I;

A[l6 ·· 23J I;

S[l7 .. 23J I;

W[l ·· OJ I;

ENDATLO O;

ROMO LO

O;

ENDATHI O;

ROMO HI

o·

RW

O;

ROMlLO

O;

NDTACK O;

ROMlHI

O;

DTACK

O;

ENADD

O;

MASEL

O;

@GROUPS
ADDR = A[l8 ·. 16J;

@LOGIC EQUATIONS

= R03 (/(MllSEL*S03*CKBMZ*D03)); = S03 (/(CKBMZ*(/(S03*D03*MASEL))));

003 = (/(Q2*R03));
= R02 (/(MllSEL*S02*CKBMZ*D02)); = S02 (/(CKBMZ*(/(S02*D02*MASEL))));

D02 · (/(Ql*R02));
= ROl (/(MllSEL*SOl*CKBMZ*DOl)); = SOl (/(CKBMZ*(/(SOl*DOl*MASEL))));

DOl = (/(QO*ROl));

ROO = (/(MASEL*SOO*CKBMZ*DOO));
= SOO (/(CKBMZ*(/(SOO*DOO*MASEL)))); = DOO (/(O*ROO));

= ROMOLO (/DSO+(/((addr == Oh)*MASEL))) = ROMOHI (/DSl+(/((addr == Oh)*MASEL)))

ROMlLO = (/DSO+ (/ ( (addr = lh) *MASEL)))

ROMlHI = (/DSl+ (/ ( (addr = lh) *MASEL)))

= == ROM2LO (/DSO+(/((addr = == ROM2HI (/DSl+ (/ ( (addr

2h)*MASEL))) 2h) *MASEL) ) )

ROM3LO = (/DSO+ (/ ( (addr == 3h) *MASEL)))
== ROM3HI · (/DSl+(/((addr 3h)*MASEL))) = == ROM4LO (/DSO+(/((addr 4h)*MASEL))) = == ROM4HI (/DSl+(/((addr 4h)*MASEL)))

= ROMSLO = (/DSO+(/((addr = Sh)*MllSEL))) ROMSHI (/DSl+(/((addr == Sh)*MASEL)))

ROM6LO = (/DSO+ (/ ((addr = 6h) *MASEL)))

= ROM6HI
ROM7LO

=

(/DSl+(/((addr (/DSO+(/((addr

== ==

6h)*MASEL))) 7h)*MASEL)))

ROM7HI = (/DSl+(/((addr == 7h)*MASEL)))

QO = (/((/(ROO*QO))*SOO*(MASEL)));
= Ql = (/((/(ROl*Ql))*SOl*(MASEL)));
Q2 (/((/(R02*Q2))*S02*(MASEL))); Q3 = (/((/(R03*Q3))*S03*(MASEL)));
= MASEL /(/(/(/((Al7*Sl7+/Al7*/Sl7) *(Al8*Sl8+/A18*/Sl8) *(A19*Sl9+/A19*/Sl9) *(A20*S20+/A20*/S20) *(A2l*S21+/A21*/S21) *(A22*S22+/A22*/S22) *(A23*S23+/A23*/S23) *(AS)))));

NDTACK /((/(MASEL+/((/qO*wO*/wl)+(ql*wO*/wl)+(/q2*/wO*wl)

+(/q3*wO*wl))))*RWll);

DTACK = /NDTACK;

RW

= /(RWN);

ENADD = AS;

ENDATLO = ((RW+MASEL)+/DSO);

ENDATHI = ( (RW+MASEL) +/DSl) ;

Figure 32. FULLEXP PLHS501 .BEE File

October 1993

na

Application Note
AN049

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

MICRO CHANNEL INTERFACE
IBM's new Micro Channel Architecture (MCA) bus implements new features not found on the XT/AT bus. One new requirement for adapter designers is that of Programmable Option Select (POS) circuitry. It allows system software to configure each adapter card upon power on, thereby eliminating option select switches or jumpers on the main logic board and on adapter cards.
Each adapter card slot has its own unique -CDSETUP signal routed to it. This allows the CPU to interrogate each card individually upon power up. By activating a card's -CDSETUP line along with appropriate address and control lines two unique 8 bit ID numbers are first read from the adapter. Based upon the ID number, the system then writes into the card's option latches configuration information that has been stored in the system's CMOS RAM. The CPU also activates POS latch address 102h bit 0, which is designated as a card enable bit
If a new card is added to the system, an auto-configuration utility will be invoked. Each adapter card has associated with it a standardized Adapter Description File with filename of @XXXX.ADF, where XXXX is the hex ID number of the card. The configuration utility prompts the user according to the text

provided in the .ADF file and updates the card's latches and the system's CMOS RAM.
IBM reserves 8 addresses for byte-wide POS latches, however, depending on the card's function, not all addresses need to be used. In addition, of those addresses that are used, only the bits used need to be latched. The first two addresses which are reserved for reading the ID bytes, and bit 0 of the third address, which is defined as a card enable bit, are mandatory. Some of the remaining bits of the third address are suggested by IBM to be used as inputs to an 1/0 or memory address comparator to provide for alternate card addresses. Many adapter cards will not use more than these three POS locations.
The following example describes an implementation of POS circuitry realized in a PLHS501. It uses only 56 of the possible 72 internal foldback NANO gates and only a portion of the device pins, allowing additional circuitry to ba added. Figure 33 shows a block diagram of the circuit, and Figures 35 and 36 are the SNAP files. Pins labeled 000-007 must be connected externally to pins DINO-DIN7. They also must be connected through a 74F245 transceiver to the Micro Channel. External transceiver direction and enable control is provided for by

circuitry within the PLHS501. The external transceiver may also be used by other devices on the adapter card.
In this application, edge-triggered registers are not required and therefore should not be used, as transparent latches use fewer NANO gates to implement. Figure 34 shows the various latch circuits described by the SNAP equations. POS byte 2 was made using four of the /B device pins and four of the B pins. Notice however, from Figure 34(B) that the bits on the /B pins used the complement of the input pin, thereby implementing a non-inverting latch. Also, all 8 bits of this byte were brought to output pins. If some of the bits are not used by external circuitry, then the specific bit latch may not be needed or may be constructed entirely from foldback NANO gates freeing additional pins.
An external F521 may be added to provide for 1/0 address decoding. As the MCA bus requires all 16 bits of the 110 address to be decoded, 8 bits may be assigned to the F521 and 8 bits to the 501. Bit fields decoded in the 501 may be done so in conjunction with bits from POS byte 2 to provide for alternate 110 addressing. Additionally, some of the available 501 outputs may be used as device enables for other devices on the card.

-ADL
-CDSETUP
-11/-10 -S1 -SO -A2 -At -Ml
-CMD--------'
°f7.,....;;·,,________.._.
llOO
CHRESET

RANSCEIVER1----- BUFEN ..,_co--,,NTR..-OL__,,__ _ _ DIR
~-1---1 1------1----l 1 - - - - " ~E 2
DATA OUTPUT

October1g93

Figure 33. Block Diagram of Basic POS Implementation in PLHS501 779

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

D4I SETUP

(SETUP) ADL

IL4

PNTERNAL NODE)

(A) Control Signal Input Latch (1 of 7) DOI

(B) Data Latch of Blta 4 - 7
LO

(C) Data Latch of Bits 0 -3 Figure 34. Latches Used In MCA Interface

October 1993

780

Pht"lps Semiconcb:tcn Programmable Logic Devices
PLHS501 design examples

****D**a*t*e*: **P1*L0*B/2*S*45*/09*1*3*5*2*-*P*i*n**PL*C**C**P*a*al*<*a*g*e**P*i*n**L*a*y*o*Tu*ti*ll*e*:**1*5*:*4*2*:*3*3****
************************************************************

s

B

DDD

S S TC

HAR I I I

S S 1J H A A A I D S II II II

1 0P D2 1 00 LT7 65

+-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I 1515151414141

171615141312111211101918171

+----------------------------------+

I IIIIIIIIIIIII

I

I 1111 1111 987 65

I

I 7654321o

I

I

I

8 l'VCC

'VCC 146]

I 91118

14145] Dill4

(101119

I3144] Dill3

(111120

I2143] Dill2

(121121

11142] Dill1

[131122

IDl41] DillD

(141123

/B314D] L3

L4 (15184

/B2139] L2

LS [16185

/B1138] Ll

L6 (17186

/BDl37] LD

L7 (18187

X7136] D07

(19100 120 IGIR>

X6135] 006
mro 1341

I

I

I

I I I I

I

I oooooooxxxxxx I

I 1 2 3 4 5 6 7 o1 2 3 45

I

+------~-------------------------+

121212121212121212131313131

111213141516171819101112131

+-+-+-+-+-+-+-+-+-+-+-+-+-+

8

I

D D D D D D

1J

0

r w

0 0 0 0 0 0
o1 2 3 4 5

B

8

II

Figure 35. PUfS501 llCPOSREG Plnllsl

Application Note
AN049

October 1993

781

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Basic Programmable Option Select circuitry for a Micro Channel Adaptor card

@PIMLIU

a[2 .. OJ i;

cmd

i;

setup

i;

ss[l ·. OJ i;

din[7 .. OJ i;

adl

i;

mio

i;

rat

i;

1(7 .. OJ o;

do[7 ·. OJ o;

bufen o;

iowb

o;

@LOGIC EQUATIONS

readO
= readl = read2

(nsetupl*/sall*as0l*nmiol*/cmd*na21*/all*/a01)
(nsetupl*/ssll*ss0l*nmiol*/cmd*na21*/all* aOl) (nsetupl*/ssll*aa0l*nmiol*/cmd*na21* all*/aOl)

b7hi = O;
b6hi l;
b5hi = l;
b4hi l; b3hi = l; b2hi l; blhi l;
bOhi O;

" Define high ID byte " (POS byte #1) 7E hex

b7lo · l;
b6lo = l;

b5lo b4lo b3lo

·==

l; l; l;

b2lo = l;

bllo = l;

bOlo = l;

" Defina low ID byte "
(POS byte #0) FF hex

" 7-Bit Input Latch for Control Signals "

nsetupl /setup*/adl + nsetupl*adl;

nmiol

/mio */adl + nmiol *adl;

ssll

asl */adl + ssll *adl;

ssOl = ·sso */adl + ssOl *adl;

na21 all

= /a2 */adl + na21 *adl;
al */adl + all *adl;

aOl

= aO */adl + aOl *adl;

" Option Select Octal Data Latch (POS byte #2) " " 10 is to be used as a card enable aignal"
nan= /(nsetupl*/ss0l*ssll*nmiol*/cmd*na2l*all*/a01); "write to latch"
= 17 /(/din7 * /nen) * /(/17 * nen) * (/rat);
16 = /(/din6 * /nen) * /(/16 * nen) * (/rat); 15 = /(/din5 * /nen) * /(/15 * nen) * (/rat); 14 /(/din4 * /nen) * /(/14 * nen) * (/rat); 13 · /(/( din3 * /nen */rat) * /(13 * nen */rat)); 12 /(/( din2 * /nen */rat) * /(12 * nen */rat)); 11 /(/( dinl * /nen */rat) * /(11 * nen ·*/rat)); 10 = /(/( dinO * /nen */rat) * /(10 * nen */rat));

Figure 36. PLHS501 MCPOSREG .EQN File (1 of 2)

October 1993

782

Application Note
AN049

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples
" Octal 3 to 1 lalltiplexer " " !Ilia maltiplexer selects bet-an reading
POS[O], POS[l) or POS[2) onto tba data bus"
ido7 - (b7hi*readl + b7lo*read0 + 17*read2); ido6 .. (b6hi*read1 + b6lo*raad0 + 16*raad2); ido5 · (b5hi*raad1 + b5lo*raad0 + 15*read2); ido4 .. (b4hi*raad1 + b4lo*raad0 + 14*raad2); idol. (b3hi*raad1 + b3lo*read0 + 13*raad2); ido2 - (b2hi*raad1 + b2lo*raad0 + 12*read2); idol .. (blhi*readl + bllo*raadO + ll*raad.2); idoO · (bOhi*raadl + bOlo*raadO + lO*read.2) ;
·3-State output control for do7-do0"
= do[7 ·· 0] · ido[7 ·· O];
do[7 ·· 0].oa (nsetupl*/sall*sa0l*nm.iol*/cmd*na2l*out·n); outen =/(all*aOl);
·External F245 transceiver control"
= iowb /(na.21 * naetupl * nm.iol * aall * /aaOl);
niow = /(na21 * naetupl * nmiol * asll * /aaOl);
bufen · cmd. * niow;
Figura 36. PLHS501 MCPOSREG .EQN Fiie (2 of 2)

Application Note
AN049

October 1993

783

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

NuBuslNTERFACE
In Apple Computer's book* "Designing Carcls and Drivers for Macintosh II and Macintosh SE~ an application was described for interfacing an 8-bit 1/0 controller to the NuBus. The controller used was a SCSI controller of the type used on the main Macintosh logic board. Seven devices (three of which were PAL architecture) were used as control circuitry interfacing the SCSI controller and two RAM chips to the bus.
This example of using the PLHS501 shows a method of interfacing the same SCSI controller and RAM chips to the NuBus using only three parts. The adapter card schematic is shown in Figure 38, the SNAP pin listing is in Figure 42, and the SNAP .EON listing is in Figure 43. Although the SNAP listing may

seem confusing at first glance, the circuitry fused into the PLHS501 can be broken down into small blocks of latches, flip-flops, and schematically in Figures 40 and 41. Circuit timing is shown in Figure 39.
Referring to Figure 40 and Figure 41, the circuitry starts a transaction by first detecting a valid address in either the slot or super slot range. The detection is accomplished by two wide-input NAND gates, and controlled by the /CLK signal. Following each NAND gate is an S-R latch to hold the signal until near the end of the cycle. The two S-R latch signals are combined into one signal named STO such that if either NAND gate output was low, then some delay time after the rising edge of /CLK, STO will go low. The next rising edge of /CLK will cause signal ST1 to go low. This

sets signal DE2 low, which is an input to an external flip-flop to cause ST2 to go low at the next rising /CLK edge terminating the cycle. An external flip-flop was necessary to achieve a high-speed /CLK to /IOR and /ACK transition. Also, an external Fl25 buffer was added to meed the soon to be approved IEEE P1196 specification requirement of 60mA loL for signal /NMRO and 24mA loL for signals /TMO/TM1 and /ACK. Figure 41 (8) shows an easily implemented latch which controls interrupts generated by the SCSI controller passing onto the bus. Upon /RESET the latch is put into a known state. Under software control, by writing to a decoded address, the latch may be set or reset, thereby gating or blocking the interrupt signals.

r-------- MASTER -----,r----- SLAVE --,

I

MOOULE

SPECIAC

PLHS501

CLOCK ORIGINATION

NU BUS Figure 37. Simplified NuBusTM Diagram

ARBITRATION

·Designing Cards and Drivers for Macintosh II and Macintosh SE, Addison-Wesley Publishing Company, Inc. 1987.

October 1993

784

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

~~~-IROMCS

' - - - - - - - /DACK '-------/SCSI

1 -i* r:-

~
I ~-----:i~'""' A12

07 19

34
3S 07

~----:2"1"1 A11
P.=== :~ l ~-----;;, 24;-t A10

D6 18 :

38 D6 37 D5

= =t}-- ~-----=;H25 I
I

~----;3;.,

A7

g:, =i-!--- ·~----· ~ :~ ~----5:-<....AAS&

D3 15

38 :

8Kx8 RAM

DO

·1""1~---.......---~: 1'"'

D2

Yee

IIDBD P ~ B7~

:: 14

IDB&r.--- 12

/DBS

10

~IDB2~

8 :

C:lR

2

~----6.-.M

//AA001145>r f-8·-::-----i54H'AF&""B7B1&-2o190;...---1'~1-1'-------;-897r~l

A3
AZ A1

!¥.-- WE
OE

~

AOW AOR

i ; - CS1

IRAMCS

/A013
::g:~-

::& A5 85 18
~ :;1c!:;;!--~J

10 AO

CS2 t=-- PU

&2&4

/C--S-",* /EDP

IDACK----ji /DACK

J /IOWAO~

/CS ~OROW

'

"

i J - - ISEL ii}---- 44

r s - - /BSY
IACK

¢----

:38

/AlN

40

/RST lij"-- 50

/A010
/AD9 !--<
/AD8~

,: A2 11 AA01

821-::i:i--_J B801 13
t-=--~ I

- - f ADCLK----t CAB CBA~GNO

t=- PU

SAB SBAtfi-GNO

'-"'"- GAB GBA

PU

~

l
I

~~-------~2.2;1,~_H.

A12 AU

I _ _ _ __,24=-t A10

i ----~25~::

D7 D6

t,c1;_;9;- :,,-.~- --- --''

J
1

g:05 1 "~,----..,1,..s_ _ _ _.,

22 ORO-ij DRO IRO--= IRO
(~~ ~ AAO 2A1

ANO /CNO IMSG
/REO

W ~ -
~

4& 42

F---~

/RESET ~ /RESETS

GNO

111

::~rI~e-><-----;4~5'AA7&"'i7B1&·r"1·°9~---4~:I:-::-:- ::- :;-:36H--t

A7
A&As
A4

8Kx8 02
RAorM 0001 PROM

"~1:~3~-~------.-./·1-J
'

GNO

/AOsl-< /AD4 /A03 /AD21-<
//AA010918~

& A5 7 A4 8 A3 9 A2 lO A1 11 AO

85 18 84 17 83 16
BB80121-'111=354 --~:I:/1

7 A3

8 AZ

1:

A.1 AO

WE OE CS1 CS2

t~ ~ ~ =A-O - A/PRR OUOWMCS

6264127&4

-t::ij IF ADCLK---ii CAB CBA~GND

PU.

SAB SBA

GNO

~Jj,~f,A t=-PU

October 1993

Figure 38. Adapter Card Schematic 785

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples
/CU< /START
ACLK

Application Note
AN049
1, '

,.00
·· ADO
D3 AD3
°"
D7 START
/ACK CU< /RESET
no°o"
START - - - - - 1 /ACK-----1
- - - - - 1 CU<-----1
/RESET
October 1993

Figure 39. Timing Diagram
/SLT
Figure 40. Decoding and Latch Circuitry 786

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

/RESET

/STD

/SLOT

/CLK

/SLT
~---r4-m

/RESET

/SlO

/SUPER

/CLK

/SUP

/RESET

Tll

TMIL

AD/CLK ISLT

/CLK_LJ

(A) Four Internal Flip-Flops Constructed from NANO Gates.

INTEN

AND-OR FUNCTIONS
·---------------~I

DRG -1C---;---L..-

NMRQ

/RESET

IRQ ---~,....._..___,
~---------------4

(B) Interrupt Enable Control Latch Interns! Flip-Flops and Latches

Figure 41. Internal Flip-Flops and Latches

October 1993

787

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

************************************************************

*

PLHS501 52-Pin PI.CC Package Pin Layout

*

*Date: 10/24/93

Time: 13:03:39 *

************************************************************

N

I

R

N

E

S

NNS NNTN

IIETAAC

D D T MC R L D D D D D D

1 01 1KTK7 65 43 2
+-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I 1515151414141

171615141312111211101918171
+----------------------------------+

I

lll l l l lllll ll

I

I 11111 111 g8765

I

I

7 65 43 2 1 o

I

I

I

81VCC

VCCl46]

NlD2 [ 91!18

!4145] Dl

NlD3 [10 I!19

13144] DO

DRQ [111120

12143] A19

IRQ [121121

Ill 42] A18

llRESET2 [131122

IOl41J A9

ST2 [141123

/B3140]

STO [15 IB4

/B2139]

[161B5

/Bll38]

[171B6

/B0137]

[181B7

X7136]

(19100

X6135)

(20 IGND

GNDl34]

I

I

I

I I I I

I

I oooooooxxxxxx I

I 1 2 3 4 5 6 7 o1 2 3 4 5

I

+----------------------------------+

121212121212121212131313131

fll213141516171819IOl112131
+-+-+-+-+-+-+-+-+-+-+-+-+-+

ANN NDNNNNN

CR R NE R S DI I

L 0 A M2 E C A0 0 KMM R SSCRW

CC Q EIKR

S S

T

B

Figure 42. SNAP Pin List

October 1993

788

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

"SCSI-NuBus Interface"

@PINLIST

nid[O ·· 3] i;

d[7 .. OJ i;

a9

i;

a [19 .· 18] i·

nresetl i;

nreset2 i;

ntml

i;

naclt

i;

nstart i;

nclk

i·

drq

i;

irq

i·

st2

i;

nromcs o; nramcs o; nnmrq o; nresetb o; nscsi o;

ndaclt o;

niorr o;

niow

o;

stO

b;

aclk

o;

de2

o;

@LOGIC EQUATION

cmpOa cmpla cmp2a cmp3a cmpOb cmplb
cmp2b cmp3b

"Address Decode"
(dO*/nidO+/dO*nidO); (dl*/nidl+/dl*nidl); (d2*/nid2+/d2*nid2); (d3*/nid3+/d3*nid3); (d4*/nid0+/d4*nid0); (dS*/nidl+/dS*nidl); (d6*/nid2+/d6*nid2); (d7*/nid3+/d7*nid3);

nsl /(d7*d6*d5*d4*cmp0a*cmpla*cmp2a*cmp3a*/nstart*naclt*/nclk); nsp = /(cmp0b*cmplb*cmp2b*cmp3b*/nstart*nack*/nclk);

nslt nsup

"latch slot signal" /(nresetl*st2*/(nsl*nslt));
"latch super siqnalw /(nresetl*st2*/(nsp*nsup));

"Let nslt or nsup throuqh only
until after the rising edge of nclk"
istO = /(/(nslt*nsup*nclk) * /(stO*/nclk) * /(nslt*nsup*stO) * nresetl);
stO = istO;
stO.oe = l;

nslot.d = stO;
nslot.clk nclk; nslot.set nreset2; nslot.rst nalt;

"Slot signal D-type Flip Flop"

nsuper.d = stO; nsuper.clk nclk;
nsuper.set nreset2; nsuper.rst nsup;

"Super signal D-type Flip Flop"

st1.d = stO; stl.clk nclk;
stl.set = nreset2;

"State 1 D-type Flip Flop"

"output to external flop" de2 = /(/stl * st2);

adclk a elk

"address latch clock"
/nclk*stO*stl; /nclk*stO*stl;

tmll.d = ntml; tmll.set nreset2; tmll.clk adclk; tmll.rst nslt;

"latch tml signal for r/w info"

October 1993

Figure 43. SNAP .EQN Listing (1 of 2) 789

Application Note
AN049

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

tmll -> 1 read, 0 write

"atraiqht decode atuff'"

niorr · /(/at0*tm11

* nreaetl);

niow = /(/tmll*/atO nacai · /(/nalot*/al9*/al8*/a9

* nreaetl);
* nresetl);

nd.aclc: = /(/nalot*/al9*/al8* a9

* nreaet2);

nromca· /(/nalot* al9* al8 nramca= /(/nauper

* nreaet2);
* nraaat2);

nraaetb= nreset2;

"interrupt control latch" aetad = /(/tmll*/atO*/nalot* al9*/al8* a9); ratad = /(/tmll*/atO*/nalot* al9*/al8*/a9); inten = /(aetad*(/(inten*ratad*nreaet2))); nnmrq = /(inten*drq+inten*irq);

Figure 43. SNAP .EON Usllng (1 of 2)

Application Note
AN049

October 1993

790

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

Application Note
AN049

Data Bus Parity
The PLHS501 can span 32 bits of input data. It has four output Ex-OR gates, and the ability to generate literally any function of the inputs. It would seem that there must be some "best" way to generate and detect parity. Recall that the PLHS501 can generate both deep logic functions (lots of levels) and wide logic functions (lots of inputs). The best solution would require the fewest gates and the fewest number of logic levels. Let's review the basics, first. Table 1(A) shows the parity function for two variables and Table 1(B) shows it for three variables. The Ex-OR function generates even parity.
It is noticeable that there are precisely 50% logical 1 entries in the truth tables. This yields the famous checkerboard Karnaugh Maps. With a checkerboard K-map, no simplification of Ex-OR functions is possible by Boolean simplification. The two variable Ex-OR has two ones (implying 3 gates to generate), the

3 variable has four ones (implying 5 gates to generate). In general, 2n-1+1 product terms could generate Ex-OR functions in two levels of NANO gates (assuming complementary input variables exist). You must have an unlimited number of gate inputs for this to hold.
The PLHS501 could do this for 7 input variables in two levels (;!6+1=65), but cannot
support 8 (27+1=129). Hence, it is appropriate to seek a cascaded solution, hopefully taking advantage of the available output Ex-OR functions. Let's solve a 16 input Ex-OR function, by subpartitioning. First, consider Figure 44(A) where two literals are Exclusive-ORed to generate an intermediate Ex-OR function. This requires available complementary inputs and generates even parity in two levels. Figure 44(8) also does this (by factoring), requiring 3 gate levels, but does not require complementary inputs.

Assuming inputs must get into the PLHS501 through the pin receivers, it is best to generate as wide of an initial Ex-OR as possible, so a structure like Figure 44(A) expanded is appropriate. Figure 44 shows a 2-level 4 input Ex-OR function which may be viewed as a building block. This structure may be repeated four times, across four sets of four input bits generating partial intermediate parity values which may then be treated through two boxes similar to Figure 44(8). These outputs are finally combined through an output Ex-OR at a PLHS501 output pin. Figure 46 shows the complete solution which requires 44 NANDs plus one Ex-OR.
Figures 4 7 and 48 show the pin layout and SNAP equations for a parity generator. This example uses a cascade with a different partitioning than just previously discussed.

Table 1. Even Parity Functions

A B

0

0

0

1

0

AffiB 0 1 1 0

Table 1(A).

A B c

0

0

0

0

0

1

0 1 0

0 1 1

0

0

0

1

1 0

1 1

AffiB 0 1 1 0
0 0

Table 1(8).

- . . J --~~-- 2 LEVELS
w
wev y

3 LEVELS
w y

wev

Figure 44(A).

Figure 44. Complementary Input Levels

Figure 44(8).

October 1993

791

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

A~: B~: c~: D~:
I~

JI"
ucB
!
~
D A
!
D JI"
c B
D A
B c
D JI"
uBc
A
ucB
Al!l8"'ClllD

4~NPUT EX-OR SYMBOL

Figure 45. Four Variable Ex-ORs

11

A

12 13 14

cB FIG. 30
D

w

15 16 17

A

B
c

AG.30

r

AG.29(8)

18

D

19

A

110 111 112

B
c

AG.30

D

w

113 114 115

A

B
c

AG.30

r

AG. 29(8)

Total gates - 44 + l Ex-OR.

116

D

Gate Delay .. 5-NAND levels+ 1 Ex·OR.

Figure 46. 16 Input Even Parity Generation

October 1993

792

Application Note
AN049
Al!lBl!lCl!lD

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

*********P*L**H*S*5*0*1**5*2*-*P*i*n*P*L*C*C***P*a*c*k*a*g*e**P*i*n**L*a*y*o*u*t***************

* Date: 10/24/93

Time: 14:32:27 *

************************************************************

F E DCBAYXVUT S R

+-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I 1515151414141

171615141312111211101918171

+----------------------------------+

I

l l l l l l l l l l l l l

I

I l l l l l l 1 l 987 65

I

I 7 65 432l o

I

I 81VCC

I VCCl46)

G [ 91118

14145) Q

H [101119

13144) P

l [111120

12143) 0

J [121121

11142) N

K [131122

10141) M

L [141123

/B3140) OEN

[15IB4

/B2139]

[16IB5

/Bll38]

[171B6

/BOl37]

[181B7

X7136)

[19100

X6135)

[20IGND

GNDl34]

I

I

I

I I I I

I

I oooooooxxxxxx I

I 12 3 45 67 ol 2 3 45

I

+----------------------------------+

121212121212121212131313131

111213141516171819101112131 +-+-+-+-+-+-+-+-+-+-+-+-+-+

0 0 EE

DDVV

DD EE

N N

c 0 c

Figure 47. PARITET PLHS501 Pinlist

Application Note
AN049

October 1993

793

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

"FILENAME:PARITET.EQN

24 BIT PARITY CIRCUIT" @PINLIST

A

I;

B

I;

C

I·

D

I;

E

I;

F

I;

G

I;

H

I;

I

I;

J

I;

K

I;

L

I;

M

I;

N

I;

0

I;

p

I·

Q

I;

R

I;

S

I·

T

I;

U

I;

V

I;

X

I;

y

I;

OEN

I;

ODD

O;

EVEN O·

ODD OC O;

EVEN_OC O;

@LOGIC EQUATION

"FIRST LEVEL: 'EVEN' FROM GROUPS OF THREE INPUTS" JO=/A*/B*/C + /A*B*C + A*/B*C + A*B*/C; Jl=/D*/E*/F + /D*E*F + D*/E*F + D*E*/F;
J2=/G*/H*/I + /G*H*I + G*/H*I + G*H*/I; J3=/J*/K*/L + /J*K*L + J*/K*L + J*K*/L;
J4=/M*/N*/O + /M*N*O + M*/N*O + M*H*/O; JS=/P*/Q*/R + /P*Q*R + P*/Q*R + P*Q*/R; J6=/S*/T*/U + /S*T*U + S*/T*U + S*T*/U;
J7=/V*/X*/Y + /V*X*Y + V*/X*Y + V*X*/Y;

"SECOND LEVEL: 'EVEN' FROM FOUR GROUPS AT A TIME" J8=/JO*/Jl*/J2*/J3 + /JO*/Jl*J2*J3 + JO*Jl*/J2*/J3 + /JO*Jl*J2*/J3
+ JO*/Jl*/J2*J3 + /JO*Jl*/J2*J3 + JO*/Jl*J2*/J3 + JO*Jl*J2*J3;
J9=/J4*/JS*/J6*/J7 + /J4*/JS*J6*J7 + J4*JS*/J6*/J7 + /J4*JS*J6*/J7 + J4*/JS*/J6*J7 + /J4*JS*/J6*J7 + J4*/JS*J6*/J7 + J4*JS*J6*J7;

TO=/(J8*J9); Tl=/ (/J8*/J9); T2=/(J8*/J9); T3=/ (/J8*J9);

ODDI=/(T2*T3); EVENI=/(TO*Tl); ODD=ODDI; EVEN=EVENI; ODD.OE = /OEN; EVEN.OE = /OEN; ODD OCI = O; EVEN OCI = O; ODD Oc=ODD OCI; EVEN OC=EvEN OCI; ODD Cc.OE = T2*T3*/0EN; EVEN_OC.OE = TO*Tl*/OEN;

October 1993

Figure 48. PARITET PLHS501 .BEE Fiie 794

Application Note
AN049

Philips Semiconductors Programmable Logic Devices
PLHS501 design examples

16-Blt Comparator
This example "compare", implements, a 16-bit comparator over 32 input bits. The design generates outputs for conditions representing the classic "EQUAL", "AGTB" (A>B) and BGTA (B>A). The long, triangularized equation for T42 suggests a clever editing approach to accurately enter a relatively long design equation into SNAP.

************************************************************

*

PIJ!S501 52-Pin PLCC Package Pin Layout

*

* Date: 10/24/93

Time: 14:54:43 *

************************************************************

AAAAAAABBBBBB

E DCBA 9 8 A 9 8 7 6 5

+-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I 1515151414141

171615141312111211101918171

+----------------------------------+

I IIIIIIIIIIIII

I

I 1111111198765

I

I

76543210

I

I 8IVCC

I VCCI 46]

AF [ 91I18

I4145] B4

BB [101Il9

B 144] B3

BC [111 I20

I2143] B2

BD [121I21

I1142] Bl

BE [131I22

IO 141] BO

BF [141 I23

/B3140] A7

AO [15IB4

/B2139] A6

Al [161B5

/Bll38] AS

A2 [171B6

/BOl37] A4

A3 [181B7

X7136]

[19100

X6135]

[20 IGND

GNDl34J

I

I

I

I I I I

I

I 0000000xxxxxx

I

I 1234567012345

I

+----------------------------------+

121212121212121212131313131

111213141516171819101112131

+-+-+-+-+-+-+-+-+-+-+-+-+-+

EAB

Q GG

UT T

ABA

L

Figure 49. PLHS501 Pinllst for 16-Blt Comparator

Application Note
AN049

October 1993

795

Philips Semiconductors Programmable Lo_gic Devices
PLHS501 design examples

"FILENAME:PARITET.EQN 16 BIT COMPARATOR WITH THREE OUTPUTS: EQUAL, AGTB (A>B) , AND BGTA (B>A) "

@PINLIST

A[9 .· OJ I;

AA

I;

AB

I;

AC

I;

AD I; AE I; AF I;

B[9 .. OJ I;

BA

I;

BB

I·

BC

I;

BD I BE I BF I

EQUAL O; AGTB O; BGTA O;

@LOGIC EQUATION Tl=/ (AF*/BF);
T3=/(AE*/BE); TS=/ (AD*/BD); T7=/ (AC*/BC);
T9=/ (AB*/BB); Tll=/ (AA*/BA); Tl3=/(A9*/B9); Tl5=/(A8*/B8);
Tl7=/(A7*/B7); Tl9=/ (A6*/B6);
T21=/(AS*/BS); T23=/(A4*/B4); T25=/ (A3*/B3);
T27=/(A2*/B2); T29=/(Al*/B2); T31=/(AO*/BO);

T2=/ (/AF*BF) ;
T4=/ (/AE*BE) ; T6=/ (/AD*BD) ; TS=/ (/AC*BC) ; TlO=/ (/AB*BB) ;
Tl2=/ (/AA*BA) ; Tl4=/ (/A9*B9) ;
Tl6=/ (/A8*B8) ; TlB=/ (/A7*B7); T20=/ (/A6*B6) ;
T22=/ (/AS*BS); T24=/ (/A4*B4); T26=/ (/A3*B3); T28=/ (/A2*B2) ;
T30=/ (/Al*Bl); T32=/ (/AO*BO);

T4l=Tl*T2*T3*T4*TS*T6*T7*T8*T9*TlO*Tll*Tl2*Tl3*Tl4*TlS*Tl6*Tl7*

Tl8*Tl9*T20*T2l*T22*T23*T24*T25*T26*T27*T28*T29*T30*T3l*T32;

T42=

/Tl+

/'r3*T2+

/TS*T4*T2+

/'r7*T6*T4*T2+

/T9*T8*T6*T4*T2+

/Tll*Tl0*T8*T6*T4*T2+

/Tl3*Tl2*Tl0*T8*T6*T4*T2+

/Tl5*Tl4*Tl2*Tl0*T8*T6*T4*T2+

/Tl7*Tl6*Tl4*Tl2*Tl0*T8*T6*T4*T2+

/Tl9*Tl8*Tl6*Tl4*Tl2*Tl0*T8*T6*T4*T2+

/T2l*T20*Tl8*Tl6*Tl4*Tl2*Tl0*T8*T6*T4*T2+

/T23*T22*T20*Tl8*Tl6*Tl4*Tl2*Tl0*T8*T6*T4*T2+

/T25*T24*T22*T20*Tl8*Tl6*Tl4*Tl2*Tl0*T8*T6*T4*T2+

/T27*T26*T24*T22*T20*Tl8*Tl6*Tl4*Tl2*Tl0*T8*T6*T4*T2+

/T29*T28*T26*T24*T22*T20*Tl8*Tl6*Tl4*Tl2*Tl0*T8*T6*T4*T2+

/T3l*T30*T28 *T26*T24*T22*T20*Tl8*Tl6*Tl4*Tl2*Tl0*T8*T6*T4*T2;

EQUAL=T41; AGTB=T42;
BGTA=/ (T4l+T42) ;

Figure 50. Compare PLHS501 .BEE Fiie

Application Note
AN049

October 1993

796

Phillps Semiconductors Programmable Logic Devices
12c 110 ports

Application Note
AN038

INTRODUCTION
This application note describes how to implement expansion 1/0 ports for a microcontroller via the 12C bus using a Philips Semiconductors PML2552 programmable logic device. This design provides 24 dedicated inputs and 16 outputs using only a single PML2552. Sixteen of the inputs may be configured on the bit level to be registered or direct inputs. The remaining eight are fixed as direct inputs.
12ceus
The 12C bus is a popular two-wire serial bus developed by Philips Semiconductors for communication between one or more microcontrollers and peripheral devices within a system. Although not as fast as parallel buses, itis designed to reduce packaging and board layout costs by requiring less wiring and fewer device pins to interconnect res or modules. Another feature is that additional circuitry may be easily plugged onto the two wires for testing or expansion purposes.
A complete specification for the 12c bus may be found in Philips' Microcontroller Data Handbook. A brief overview of the bus follows.
CHARACTERISTICS OF THE 12c BUS
The 12e bus provides 2-way, 2-line communication between different res or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (Figure 2).
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). Figure 3 shows start and stop conditions.
A device generating a message is a "transmitter", a device receiving a message is the "receiver". The device that controls the message is the "master" and the devices that are controlled by the master are "slaves".

Figure 4 shows a block diagram of a system configuration.
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of the eight bits is followed by one acknowledge bit. The master supplies the clock pulse for the acknowledge bit. An acknowledge is a LOW level on the SDA line during the acknowledge clock. Therefore the transmitter must leave the bus HIGH so the receiver may pull the SDA line LOW to acknowledge.
A slave receiver which is addressed must generate an acknowledge alter the reception of each byte (Figure 5) A master receiver must generate an acknowledge alter the reception of each byte provided the master wants to continue receiving bytes. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the slave transmitter must leave the data line HIGH to enable to master to generate a stop condition ).
Data transfers follow the formats shown in Figure 6. After the START condition, the master sends the slave address. This address is 7 bits long, the eighth bit is a data direction bit (R/W). A 'zero' indicates a transmission (WRITE) and a 'one" indicates a request for data (READ). A master always terminates a data transfer by a STOP condition. However, if a master still wishes to communicate on the bus, it can generate another START condition and address another slave without first generating a STOP condition. Various combinations of read and write formats are possible within such a transfer.
Each port in this design is assigned a unique address, so only 8 bits are available to or from each address. However, a master may read or write a port multiple times during the same message. During a read of a port (slave), if the master acknowledges the data, then the same port will put data on the bus again. When the master not-acknowledges the data, then the slave will release the bus so the master may generate a stop or another start condition. During a write, the master may simply continue to write data after the address. All data will go into and be acknowledged by the addressed slave output port.

PML2552 OVERVIEW
A functional block diagram of the Philips PML2552 is shown is Figure 1. The PML2552 is a CMOS device built on an EPROM process. This device contains 16 bypassable input D flip-flops, 16 bypassable output D flip-flops, 20 internal JK flip-flops, and 96 foldback NANO gates in a 68 pin package. The core of the PML2552 is a programmable array of 96 NANO gates and 20 buried JK flip-flops. The output of each NANO gate folds back upon itself and all other NANO
a gates and flip-flops. The and IQ output of
each ftip-ftop folds back in a similar manner. All inputs (true and complement) also connect to each of the NAN D gate and flip-flop inputs. Thus, total connectivity of all logic functions is achieved.
A NANO operation is functionally complete meaning that using only NANO gates, AND, OR and INVERT operations may be realized. Any logic function may therefore be constructed from the NANO gates in the folded NANO array, from simple combinatorial logic to additional edge-triggered registers. Because the NANO gates have very wide inputs (258 possible input connections), some functions which require many logic levels using simple 2 or 4 input gates, may be 'flattened' or implemented in fewer delay inducing logic levels.
12c 1/0 PORT DESIGN
Shown in Figure 7 is a block diagram of the 12C 1/0 port design for the PML2552. It is set up as an 12e slave device to provide three 8 bit input ports and two 8 bit output registers. Addresses are programmed into the device and may be altered by changing 3 lines in the equations file. Two of the 8 bit input ports may be configured to be registered or direct inputs. These inputs are mapped to the 16 input D flip-flops of the PML2552 which may be individually bypassed. The third 8 bit port uses 8 direct input pins. The dual 8 bit output registers are mapped to the 16 output D flip-flops. An external connection is necessary to clock the output D flip-flops.
An 8-bit shift register was constructed from 8 internal JK flip-flops. Addresses and data appearing on the 12C bus are clocked into this register. A state machine looks at this register for a valid address, and if appropriate, clocks the data following the address into the output registers.

797

Philips Semiconductors Programmable Logic Devices
12c 110 ports

Application No1e
AN038

In addition to the shift register the sta1e machine also looks at a three bit coun1er output to determine when a specific bit or data bytes are available. Using a counter to mark time ins1ead of adding states to the
sta1e machine can save device resources for
other functions. A counter may be constucted very elficiendy using JK flip-flops and this one uses a unique design which uses only three NANO gates in the PML2552 flip-flop clock array, none in the foldback NANO array! The state machine is built using 7 of the PML2552's internal JK flip-flops. The state machine has an output, DSBLCNT, which holds the counter at zero for one clock cycle during the acknowledge bit time. DSBLCNT is also gated with a couple other signals to generate an acknowledge on the bus.
Two signals are involved in reseting or initializing the state machine and coun1er. They are called START and BUSY. Their relative timing is shown in Figure 8. The derivation of these signals is described later, but for now note that the counter and state machine are reset whenever START is HIGH or BUSY is low. START and BUSY are generated from a circuit which detects the 12c bus start and stop conditions. If an address is placed on the 12C bus that does not match one programmed into the device, the state machine will go into a state which can only be exited by the START or BUSY signals resetting the state machine. Also, if a bus master issues a repeated start condition, START will go HIGH initializing the state machine to begin looking for an address match.
lns1ead of loading the input register data into a shift register, a 24 to 1 multiplexer, along with the counter, select the proper input bit to send out onto the 12C bus. An additional flip-flop (U11) inside of the interface logic synchronizes the data to the 12c clock, SCL. The multiplexer inputs are offset in relation to the counter value. It was necessary to offset the bits relative to the counter due to the one bit delay introduced by U11 and DSBLCNT holding the counter at zero for one bit time.
U11's output connects to another flop-flop called U10. U10 holds the data (port data or acknowledge bit) to be sent to the master device for one data bit time. The 12c data must change only when the SCL clock is LOW. The falling edge of SCL may be up to

300ns long. For this reason, U10 is docked by a delayed falling edge of SCL. The delay is created by a bidirectional output pin (DLYOUT) and an external RC network. Pin DLYOUT is configured to operate like an open-collector output. The input to DLYOUT's output buffer is connected to ground. The SCL input is internally connected to the three state output enable control line of this output buffer. DLYOUT should be externally connected to a 1OK pull-up resistor and a 33pF capacitor connected to ground. An input buffer is internally connected to DLYOUT and clocks U10. U10's output controls the 3-Sta1e control line of output SDA. Output SDA behaves like an open-collector as the input to the 3-State output buffer is connected to ground.
Demcting valid 12C start and stop conditions was done without using internal flip-flops. Instead, an asychronous state machine was designed to output a pulse during start conditions and hold a line (busy) high until a stop condition. The start pulse initializes (resets) the state machine and counter.
START/STOP DETECTION DETAILS The waveforms produced by the detection circuitry are shown in Figure 8. The first step to achive these waveforms is to draw waveforms of the desired circuit operation showing all possible input transitions. First. let's start with the START signal waveforms. These timing waveforms are shown in Figure9a.
Next, a primitive flow table should be constructed. A primitive flow table has only a single stable state on each row. It is shown in Figure 9b. From the primitive flow table, a reduced flow table can be constructed by merging rows. Two rows may be merged, if, when comparing each column entry, they are the same or at least one is a Don't Care. Merging of rows may be described by a merger diagram. For this case one is shown in Figure 9c. So, from the primitive diagram, rows with stable states 0, 1 and 2 are combined. Also, rows with stable states 6 and 3 are combined.
The merged flow table (Figure 9d) has two rows so only one state variable (Yo) is

required. The output matrix table is shown in Figure 9e. It was generated by simply assigning the output value associated with each stable state. Unstable entries were assigned the output value associated with the corresponding stable state.
A table showing the next state value for Yo is shown in Figure 9f. It was generated by noting which states should remain stable and what value Y must be to either enter or remain in that state.
Generation of the BUSY signal required two state variables as shown in Figure 10. Tables were constructed in a manner similar to the process described above. However when transitioning from unstable state 1 to stable state 1 (see reduced flow table, stable state 1 is circled) an intermediate state was added. This was done to avoid switching the two transistion variables, y1 & yo, from 00 to 11 simultaneously. Adding the intermediate state makes the variables change from 00 to 10 to 11 . Additionally, an extra state was added to transistion from unstable state 3 to stable state3.
Waveforms for bus transations along with some internal signals are shown in Figures 11 and 12. The SNAP listing is shown in Figure 14.
CONCLUSION
PLDs may be used in embedded systems for more than simple decoding and glue logic collection functions. This design combined several low level functions (counter, shift register, state machine, random logic) to produce a useful microcontroller peripheral using one programmable logic device. This design may be easily altered to provide for specific system requirements. It has alre&dY been altered to make a simple 12C bus activity monitor which is the subject of another application note (AN039)1
A breadboard of this circuit was constructed for functional testing purposes. A listing for the design is shown in Figure 14. Additional circuit details are written as comments in the listing. A copy may be downloaded from the Philips PLO and Microcontroller Bulletin Board. The phone number is (800) 451-6644 or (408) 991-2406. Use a modem set to 8 bits, no parity and one stop bit

October 1993

798

Philips Semiconductors Programmable Logic Devices
c12 110 ports

Application Note
AN038

16 INPUT DFLIP-FLOPS
& 13 DEDICATED
INPUTS A
~
FOLDED NANO ARRAY
B
10 JK FLIP-FLOPS
WITH COMMON
CLK
c
10 JK FLIP-FLOPS
WITH DISTINCT
CLKS D

p

R

0

G

R

A

M

M A B

160UTPUT D FLIP-FLOPS

L

E E

I

N

T

E

R
c

0

N

N

E

c
T

<=>

24 Bl-DIRECTIONAL
I/Os

F

October 1993

Figure 1. PML2552 Functional Block Diagram 799

Philips Semiconductors Programmable Logic Devices
12c 110 ports

Application Note
AN038

I SDA
SCL

x

:; \: /

I

I

I

Data Une Stable:

Change
of Data

Data Valid

Allowed

Figure 2. Bit Transfer

\ \

- ' ~, - - - - \ _' J -

SDA

I

I

I

l

SDA

I

1

I

I

'

'

SCL

SCL

p

Start Condition

Stop Condition

Figure 3. Definition of Start and Stop Conditions

SDA~~~~~~~-+~~~~~~~~--~~~~~~~~...-~~~~~~~~--~~~~~~~~...-~~SCL~~~.,._~~~-+~~~--<>--~~~-1-~~~-<11--~~~-l-~~~--<>-~~~-1-~~~-<11--~~~-1-~~-

SLAVE RECEIVER

SLAVE TRANSMITIER

Figure 4. System Configuration Using 12C·Bus
start condition
SCLFROM MASTER

clock pulse for acknowledgement
'

s
DATA OUTPUT BY RECBVER
October 1993

Figure 5. Acknowledgement on the 12c.eus 800

__\ ___,(

Philips Semic:onwctors Programmable Logic Devices
t2C 110 ports

Application Note
AN038

Possible data transfer formats are: a. Master transmitter to slave receiver. Direction is not changed.

acknowledge from elave

s

SLAVE ADDRESS

R/W 'O'(wrlte)

b. Master reads slave immediately after first byte.

A

OATA1 FROM MASTER

A

DATAn FROM MASTER

datatrlinsfened (n byleo + ockn.-dge)

A

p

A =acknowledge
s :alart
P =atop

s

SLAVE ADDRESS

R/W '1'(reod)

acknowledge from master

not acknowledge from master to end transmission

A

OATA1

A

DATAn

A

p

FROM SLAVE

FROM SLAVE

data transfened (n bytes + acknowledge)

o. Combined format.

acknowledge from alave

acknowledge from slave

S SLAVE ADDRESS R/W read or write

DATA

A S

L _J (nbyleo +ack.)

SLAVE ADDRESS R/W read or write

DATA

A

p

L _J (nbyteo +ack.)

direction of transfer may change at this point.

During a change of direction within a transfer, the START condition and the slave address are both repeated, but the R/W bit reversed. Start, stop, slave addresses and R/W bits are generated by the master.
Figure 6. Data formats of the 12C-Bus

R01

Philips Semiconductors Programmable Logic Devices
12c 110 ports

Application Note
AN038

REG
INPUT PORTS
REG

MUX

SHIFT REG

REG
OUTPUT PORTS
REG

12cBus
SDA
SCL

INTERFACE LOGIC

CONTROL STATE
MACHINE AND
COUNTER

Figure 7. 110 Ports Block Diagram

START CONDITION

r--.,

I

I

----t-i...I,. !I

SDA

STOP CONDITION
r--.,

I

I

I

I

--~-\__j/f--

1

I

I

SCL lI __jI\ ____;--\__/[I }-I --

START _____.n....___ _ __

BUSY
October 1993

Figure 8. Start and Busy Signal Timing 802

Philips Semiconductors Programmable Logic Devices
12c 110 ports

Application Note
AN038

D

1 1

c

0 00

z

0 0 0 0 0 0 0 0 0 0 0 0 0

3 6 0

0 23

3

0 2 0

36 0

9a. Waveforms with Assigned State Values

DC

z 0 0 0 1 1 1 1 0 0 - 3 (1) 0

-

© 6

1

0

© 0

3

-

®2 -

1

0

© 0

3 -

9b. Primitive Flow Table

DC
00 0 1 1 1 10
a 0 ©© 1
b ® © 3 (1)
9d. Reduced Flow Table

DC

Yo

00 0 1 1 1 10

0 0

0

0 z

0

0

0

0

START=U · C ·Yo
9e. Output Matrix

9c. Merger Diagram

01 11

0

0

z

0

Yo='C+Uyo 91. Transition Matrix

Figure 9. START Equation Generation 803

Philips Semiconductors Programmable Logic Devices
12c 110 ports

Application Note
AN038

D

1 0

c

0 00

z

lo o o o o o o o o o o

36 4 57546463636457 6 6463

0

3

0 2 02 3

DC

z 0 0 0 1 1 1 1 0

© -

6

1

© 4

3 -

©6 -

5

4 PrimItIve
- Flowtable

© -

7

G 6

5

0 0 -

3

® 2' -

1

© 0

3 -

DC

0 0 0 1 11 10

© © a 4

1

b© 6 0 ©

c®© 3 0

Reduced Flow Table

01 11 1 0

0

0

Output Matrix

11

0

0

1 0

0 1 11 10

00

0

0

01

0

1-+......i-+---

1 1

Yo

DC

Y1Yo

00 01

00 0

0

01 0

0

1 1

1 0

Y1 = Y1Yo + Y1a + YoDa + Y1U

Transition Matrix

October 1993

Figure 10. BUSY Signal Generation 804

Address

Drive

Bus

H

Data

Drive Bus
H

SDA

c!;..ca..!..
f ~ l:.c.
Ii
ID
~
l

SCL START

~~~~~~~~~~~~~~~~~,~~

STATE STATE STATE

1

2

3

S ATE STATE

2

3

BUSY DSBLCNT

OWN

DTR

WP

"'()

0

"'O 0

;::i.

(/)

a"'D

"~ '

3 ~
ii)

b
IQ.
()
0
.:(!s).
8

)z >
0

{
~

(,)

::>

CX> z

~

Philips Semiconductors Programmable Logic Devices
12c 110 ports

..
:I .D
...!.
~ .!!
Ul
October 1993

0 S.,~oS.,~

., 0

UJ
~(D

....

<D

LO
....

"'
N

., 0

UJ
~~

., 0

UJ
~~

....

UJ
.~, ~

<D

LO
....

"'
N

0
,_.
z
::> 0
"

...
CJ

Ia-:
i!

Ul

Ul

> :U:>l m

Igz-
m
~

Figure 12. Transmit Data Timing 806

Application Note
AN038

PhiNps Semiconductors Programmable Logic Devices
12c 110 ports

Application Note
AN038

R B
s pp p

p p p p p

~
p p p p p

1Bl l l l l l l l l 2 2 2 2
7T0l 2 345 ' 7 c0 l 23 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I I I 16161616161616161

ltl81716151413121118171615141312111

+------------------------------------------+

I I I I I I VI I I I I GCI I I I

I

I 7 a I I I c I I I I I Nx I I I I I

I

ooocoooooDBoooo I

I

ol 2 l 3 4 s 6 7 l l a9 l l

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I

o l

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I I6 [101I6

I I/012160] P24

IS [ll!IS

I/013159] P25

I4 [121I4

I/014158] P26

I3 [13113 I2 [14112
[151GND4

I/015157] P27 C1CB2156] VCC2155] llP2CJ

I1 [161Il IO [171IO
F [l81SCM [19ISC1 '=' [201I/CXD3
[211VCC4 SCL [2211/CXD2
[2311/CXDl CK3 [241 l/CXB/CXC

=~ =-l B0154]
Bll53] B2152] B3151] OWH

B4150] DLYIO

GND214t] B5148] START B6147] BUSY

I

B7 I46] SDA

J:

[251PD P37 [261I/DB7

I

I/DA0145] P40 I/DA1144] P41
I

I

I I 11 1I 1 1 11I 11

I

I VI I I I GI I I IvI I I I I I

I C DDDDNDDDC DC DDDDD

I

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+------------------------------------------+

12121213131313131313131313141414141

17181910111213141516171819101112131
+-+p-+p-+p-+p-+-+p-+p-+p-+c-+p-+-+p-+p-+p-+p-+p-+ 3333 333x4 44444

65 43 21047 65432

Figure 13. Pin Layout with External Connections

~hor1Q<v.l

807

Philips Semiconductors Programmable Logic Devices
12c 110 ports

Application Note
AN038

I2C I/0 Porta
This design ia for a PML2552 device. It configures the PML2552 to operate as several I2C slave remote I/O ports. It provides for 16 parallel output lines and 24 inputs. Specifically, the I/0 ports are arranged as two 8-bit output ports, two 8-bit input ports (which may be modified on the bit level to be registered or direct inputs), and one 8-bit direct input port. The two 8-bit output ports will power-up to a HIGH level on the device pins.
SNAP 1.90 or later must be used to compile this file.

@PINLIST

"input pins"

acl

i;

reset

i;

p4[7 .. OJ i;

p3[7 ·. OJ i;

ck3

i;

ck4

i;

wplc

i;

wp2c

i;

i[7 .· OJ i;

"I2C clock" "reset input is active LOW" "port 4" "port 3" "clock for port 3" "clock for port 4" "connect pin to wpl pin" "connect pin to wp2 pin" "port 5"

"output pins"

ada

b;

at art

b;

busy

b;

own

o;

wpl

o;

wp2

o;

dlyio

b;

p2[0 ·· 7J o;

pl[O ·· 7J o;

"I2C data"
"pulse during start condition" "bus busy - high from start to atop" "address compare" "connect pin to wplc pin" "connect pin to wp2c pin" "connect pin to lOK pullup and 33pf cap to gnd" "port 2" "port l"

@GROUPS

adr

ar[6 .. OJ;

ex

c[2 .. OJ;

ct

c[2 .. OJ;

ports i[7 ·. OJ;

port4 p4[7 .. OJ;

port3 p3 [7 .· OJ;

port2 p2[7 .. OJ;

portl pl[7 .. OJ;

"direct inputs" "reqistered or direct inputs" "registered or direct inputs" "outputs" "outputs"

@TRUTHTABLE @LOGIC EQUATIONS

"-----------------"
" Input registers "
"-----------------"

d[l5 .· 8J.id port4;

d[l5 ·· 8J.clk ck4;

d[7 .. 0J.id

port3;

d[7 .. 0].clk ck3;

The breadboard doesn't use input registers

so the above section is commented out and

the following section used.

October 1993

Figure 14. (1 of 5) 808

Philips Semiconductors Programmable Logic Devices
12c 110 ports

Application Note
AN038

" Input pins "

d[lS .. SJ d[7 .. OJ
di[7 .. OJ

port4; port3;
ports;

" output registers "
" ------------------ "
= port2.od sr[7 .. 0J; = port2.clk wp2c; portl.od = sr[7 .. 0J; = portl.clk wple;

" Shift register equations "

u2.elk sol;

u3.elk sol;

u4.elk sol;

uS.elk sol;

u6.elk sol;

u7 .elk sol;

u8.clk sol;

u9.elk u2.set u3.set u4.set us.set u6.set

sol;
I (start + /busy); /(start + /busy); I (start + /busy); I (start + /busy); I (start + /busy);

u7.set us.set u9.rst

/(start + /busy); I (start + /busy); I (start + /busy);

u2.j

sda;

u2.k /sda;

u3.j

u2;

u3.k /u2;

u4.j

u3;

u4.k /u3;

uS.j

u4;

uS.k /u4;

u6.j

uS;

u6.k /uS;

u7.j

u6;

u7.k /u6;

uS.j

u7;

uS.k /u7;

u9.j

u8;

u9.k /us;

sr[O .. 7J = u[2 .. 9J;
,,-----------------'"
,",_C__o_u_n_t_e_r__s_e_c_t_io_n__,",

e2.j l; e2.k l; el.j l; el.k l; eO.j l; eO.k l;

October 1993

"S bit shift register for input" "of I2C address and data" "the state machine reads this register'' "for address comparison and clocks" "data from this register into'' "appropriate output register" "this register is clocked by the I2C" "bus clock" "reset or set signals defined so SNAP" "will use specific internal JK flip-flops"
"3-bit binary counter" "outputs connected to state machine" "and to multiplexer "
Figure 14. (2 of 5) 809

Philips Semiconductors Programmable Logic Devices
c12 110 ports

Application Note
AN038

cO .. rst cl.rst c2.rst

I (/busy + start); I (/busy + start); /(/busy + start);

CO.elk cl.elk c2.clk

I (/dsblcnt */sol); I (/dsblcnt * /scl * cO);
I (/dsblcnt * /sol * co * cl);

"counter uses NANO gates" "in clock NAND array, not" "from the foldback array"

"-----------------------"
" Multiplexer equations ''
"-----------------------"
uuuOUT = (D6*0Wlll*/OWll2*CT==OH*/dsblcnt)
+ (D5*0Wlll*/OWll2*CT==lH*/dsblcnt) + (D4*0Wlll*/OW112*CT==2H*/dsblcnt) + (D3*0Wlll*/OWN2*CT==3H*/dsblcnt) + (D2*0WN1*/0WN2*CT==4H*/dsblcnt) + (Dl*OWN1*/0WN2*CT==SH*/dsblcnt) + (DO*OWll1*/0WN2*CT==6H*/dsblcnt) + (D7*0WN1*/0WN2* dsblcnt)
+ (Dl4*0WN2*/0WNl*CT==OH*/dsblcnt) + (Dl3*0WN2*/0WNl*CT==lH*/dsblcnt) + (Dl2*0WN2*/0WNl*CT==2H*/dsblcnt) + (Dll*OWN2*/0WNl*CT==3H*/dsblcnt) + (DlO*OWN2*/0WNl*CT==4H*/dsblcnt) + (D9 *OWN2*/0WNl*CT==5H*/dsblcnt) + (08 *OWN2*/0WNl*CT==6H*/dsblcnt) + (Dl5*0WN2*/0WN1* dsblcnt)

"convert parallel input data" "to serial format"
"port 3"
"port 4"

+ (di6*0WNl*OWN2*CT==OH*/dsblcnt) + (di5*0WNl*OWN2*CT==lH*/dsblcnt) + (di4*0WNl*OWN2*CT==2H*/dsblcnt) + (di3*0WNl*OWN2*CT==3H*/dsblcnt) + (di2*0WNl*OWN2*CT==4H*/dsblcnt) + (dil*OWNl*OWN2*CT==5H*/dsblcnt)
+ (diO*OWNl*OWN2*CT==6H*/dsblcnt) + (di7*0WNl*OWN2* dsblcnt);

"port 5"

,,------------------------------------''
" Detect I2C start & stop conditions "
"------------------------------------"

uuuy uuustart start start .oe

/sol + uuuy*/sda; /uuuy*/sda*scl; uuustart;
l;

uuuyO

uuuyl*/sda + uuuyl*/scl + /sda*/scl + /uuuyl*uuuyO*sda + uuuyO*/scl + /reset;

"start condition pulse"
"bus busy signal is HIGH" "from start to stop" "conditions"

uuuyl

uuuyl*uuuyO + uuuyl*/scl + /uuuyO*sda*/scl + uuuyl*/sda + /reset;

uuubusy busy busy.oe

/uuuyl*uuuyO + /uuuyl*/sda; uuubusy;
l;

October 1993

Figure 14. (3 of 5) 810

Philips Semiconductors Programmable Logic Devices
12c 110 ports

Application Note
AN038

"n _O__u_t_p_u_t__c_o_n_t_r_o_l_ n

ada sda.oe

O· ulO;

"I2C data"

ulOin
ulO.j ulO.k ulO.clk ulO.rst

/dtw * dsblcnt * own

nsend ACK on bus"

=+ dtw * /dsblcnt * own * /ull; "send data on bus" ulOin;

/ulOin;

"ulO holds data stable on bus"

dlyio;

/(start + /busy);

ull.j ull.k ull.clk ull.rst

uuuout; /uuuout;
· scl; /(start+ /busy);

"ull synchronizes input data to I2C clock"

dlyio

O;

dlyio.oe scl;

"pin dlyio should ba connected to a lOK" "pull-up and a 33pf cap to ground"

"-----------------------"
" State machine portion "
"-----------------------"

·port address declarations" "these addresses may be changed to" "any valid I2C addressn

adrpl
adrp2 adrpS

adr==OlllOOOb; adr=OlllOlOb; adr==OlllOllb;

"this address is for portl (write) & port3 (read)" "this address is for port2 (write) & port4 (read)" "this address is to read pins IO to I7"

state2i state4i state6i

S2*/Sl*SO; /S2* Sl*SO; /S2*/Sl*SO;

"duplication of soma state ma.chine· "states to be used in following" "boolean equation"

dsblcnt state2i+state4i+state6i; "dsblcnt HIGH when in state 2,4 or 6"

s2.set al.set so.set ownl.rst own2.rst dtw.rst dtr.rst s2.clk al.elk so.elk ownl.clk own2.clk dtw.clk dtr.clk

/(start + /busy); I (start + /busy); I (start + /busy); I (start + /busy); /(start + /busy);
/(start + /busy); I (start + /busy);
·~l;
scl;
scl; scl;
acl;
acl; scl;

#reset state machine upon start· ·condition and whenever bus is " "not busy (stop detected).

"ownl & own2 denote address match"

"write to I2C bus (read port)"

"read I2C bus

(write port)"

"clock state machine from I2C clock"

cntr7 cx==7h; cntr6 cx==6h;
= wp dtr * dsblcnt * ulO;
wp2 wp * own2; wpl wp * ownl; own ownl + own2;

"state machine reads counter to" "wait for specific bits"
"wp2 and wpl clock data from shift register" "into proper output port. external connection" "from wpl to wplc and wp2 to wp2c is required"

October 1993

Figure 14. (4 of 5) 811

Philips Semiconductors Programmable Logic Devices
12c 110 ports

Application Note
AN038

f!DIPO'l VECTORS @OUTPUT VECTORS [dtw,ownl,own2] .nG'FR low = OOOb; [dtr] JKFFR dtrl Ob; dtrh = lb;

@STATE VECTORS [s2,sl,s0] JKFFS
stateO lllb; statel llOb; state2 lOlb; state3 lOOb;
state4 Ollb; states OlOb;
state6 OOlb; state7 OOOb;

"bus start or stop condition required to leave state7"

@TRANSITIONS

while [stateOJ if [cntr6] then [statel]

"start detected, " "wait for address"

while [statel]
if [a<llpl* sda] then [state4] with [ownl] if [a<llp2* sda] then [state4] with [own2] if [a<llpS* sda] then [state4] with [ownl, own2] if [adrpl*/sda] then [state2] with [ownl]
if [adrp2*/sda] then [state2] with [own2] if [/a<llpl*/a<llp2*/adrpS] then [state7] if [a<llpS*/sda] then [state7]

"compare address & r/w bit"
"addressed port 3 to read" "addressed port 4 to read" "addressed port 5 to read" "addressed port l to write" "ad.dressed port 2 to write" "no address compare"
"ignore port 5 for write"

while [state2] if [] then [state3]

wwrite port"

while [state3] if [cntr7] then [state2] with [dtrh]

"wait for 7 bits"

while [state4] if [] then [states] with· [dtw]

"read port"

while [states] if [cntr7] then [state6]

"wait for 7 bits"

While [state6]

if [/sda] then [stateS]

"master acknowledged so send byte again"

if [ sda] then [state7] with [low] "master not-acknowedged so release bus"

Figure 14. (5 of 5)

October 1993

812

Phillps Semiconductors Programmable Logic Devices
12c bus monitor

Application Note
AN039

INTRODUCTION
The PML2552 device may be used to build a simple real time non-intrusive 12C bus monitor. This monitor displays all addresses and data sent on the bus as well as acknowledge and read/write bit conditions. It also outputs START and BUSY signals which may be used for synchronizing additional test equipment to the bus. The outputs of this monitor may be connected to a microcontroller for additional data formatting capabilities.
A block diagram of this design is shown in Figure 1. This design is a modification of an 12C 1/0 port application using the PML2552. The input registers and multiplexor functions were removed from the 12C 1/0 port and the control state machine was modified to latch all addresses and data bytes acknowledged on the bus. Additionally, since the monitor does not drive the 12C bus, the circuitry in the 110 port application that generated acknowledge bits during a read was also removed. Two signals, START and BUSY are generated by an asynchronous state machine. For detailed information on the derivation of these signals, the reader should refer to the PML2552 12C 1/0 port application note (AN038).
SHIFT REGISTER
Referring to Figure 1 and Figure 3, an 8-bit shift register was constructed from 8 internal JK flip-flops. Addresses and data appearing on the 12C bus are clocked into this register. A state machine looks at this register, and clocks the byte into the appropriate output register for address or data display. The byte will only be clocked into an output register if an acknowledge of the address or data occurred.
In addition to the shift register the state machine also looks at a three bit counter output to determine when a specific bit or data bytes are available. Using a counter to mark time instead of adding states to the

state machine can save device resources for other functions. A counter may be constructed very efficiently using JK flip-flops and this one uses a unique design which uses only three NANO gates in the PML2552 flip-flop clock array, none in the foldback NANO array! The state machine is built using 7 of the PML2552's internal JK flip-flops. The state machine has an output, DSBLCNT, which holds the counter at zero for one clock cycle during the acknowledge bit time. DSBLCNT is also gated with a couple other signals to generate the clock pulse that updates the output registers.
Two signals are involved in resetting or initializing the state machine and counter. They are called START and BUSY. These signals are generated from a circuit which detects the 12C bus start and stop conditions. Refer to Figure 2 to see the relative timing of these signals. If a bus master issues a repeated start condition, START will go HIGH initializing the state machine to begin looking for an address match.
STATE MACHINE DETAILS
After the BUSY line goes HIGH, the state machine will be in state 0. It simply waits in this state until the counter counts to six. The shift register should now contain the address sent on the bus.
Upon the next 12C clock, the state machine to transitions to state 1. When the next 12C clock occurs, the RW bit status will be transferred to a register and an output pin. In addition, the RW bit will also be shifted into the shift register to be displayed along with the address when the shift register is clocked into the address display output port. The state machine will transition to state 2.
Being in state 2 causes a signal DSBLCNT to go HIGH. This signal disables the counter for one count but also enables WP 1 to clock the address and data into the display port upon the falling edge of the 12c clock.

After the address is found and latched into the output port, the state machine will transition to state 3. While in state 3 the state
machine waits for the counter to count to
seven, indicating that a byte of data is in the shift register. The state machine now transitions back to state 2 but sets a control bit named DATA. Once set, this bit can only be reset by another bus START condition or by a bus STOP condition. When the acknowledge clock pulse occurs, the byte in the shift register will be transferred to the data display output port.
The state machine continues in a like manner transitioning between state 2 and state 3, latching data into the data display output port. When a bus STOP condition occurs, the state machine and counter circuitry will be reset, and will be held in the reset state until a bus START condition occurs.
CONCLUSION
This design combined several low level functions (counter, shift register, state machine, random logic) to produce a useful function using one programmable logic
device. Although a microcontroller may be programmed to read addresses and data on the 12C bus, as the speed of the 12c bus is
increased to 400 Kbits/sec the microcontroller will have difficulty doing anything else. Moving some high speed functions to hardware makes sense, allowing the microcontroller time to analyze and format
the data . This design may be easily altered
to provide for specific system requirements.
A breadboard of this circuit was constructed for functional testing purposes. A listing for the design is shown in Figure 3. Additional circuit details are written as comments in the
listing. A copy may be downloaded from the
Philips PLO and Microcontroller Bulletin Board. The phone number is (800) 451-6644 or (408) 991-2406. Use a modem set to 8 bits, no parity and one stop bit.

October 1993

813

Philips Semiconductors Programmable Logic Devices
12c bus monitor

Application Note
AN039

SHIFT REG

REG

ADDRESS DISPLAY

OUTPUT PORTS

REG

DATA DISPLAY

12C BUS
SDA
SCL

INTERFACE LOGIC

CONTROL STATE
MACHINE AND
COUNTER

Figure 1. Monitor Block Diagram
START CONDITION

STOP CONDITION

SDA

SCL
START ____.n..______ _ __

BUSY
October 1993

Figure 2. Start and Busy Signal Timing 814

Philips Semiconductors Programmable Logic Devices
12c bus monitor

Application Note
AN039

October 1993

I 2C Bus Monitor
This design is for a PML2552 device. It configures the PML2552 to work as a simple real time non-intrusive I2C bus monitor. 1ihen connected to the I2C bus, one 8-bit output port displays addresses sent on the bua while another 8-bit port displays data. Additional output pins display address acknowledge, data acknowledge, rw mode, bus start condition, and bus busy status.
SNAP 1.90 or later must be used to compile this file.

@PINLIST

"inputs"

sol

i; "I2C clock"

sda

i; "I2C data"

reset

i; "reset input active LOW"

wplc

i; "connect this pin to wpl pin "

wp2c

i; "connect this pin to wp2 pin

"outputs"

start

b;

busy

b;

a a ck

o;

dack

o;

rwo

o;

wpl

o;

wp2

o;

p2 [O .. 7] o;

pl[O .. 7] o;

"start pulse" "bus busy"
"address acknowledge" "data acknowledge" ,,read/write"
"connect this pin to wplc pin" "connect this pin to wp2c pin'' "data display port" "address display port"

@GROUPS

adr

sr(6 .. O];

ex

c(2 .. O];

ct

c(2 .. O];

port2 = p2 (7 .. OJ; "data display port"

portl = pl(7 .. 0]; "address display port"

@TRUTHTABLE @LOGIC EQUATIONS
"------------------"
" output registers "

port2.od port2.clk portl.od portl.clk

sr(7 .. O]; wp2c; sr[7 .. 0]; wplc;

"--------------------------"
" Shift register equations "
"--------------------------"

u2.clk scl; u3.clk scl; u4.clk scl; uS.clk = scl; u6.clk scl; u7 .elk scl; us .elk scl; u9.clk scl;
u2.set I (start + /busy); u3.set I (start + /busy); u4 .. set I (start + /busy); us.set /(start + /busy); u6.set /(start + /busy); u7.set /(start + /busy); us.set I (start + /busy); u9.rst /(start + /busy);

"8 bit shift register for input" "of I2C addresses and data"
"the state machine will clock address" "or data bits from this register into" "the appropriate output register after" "eight bits have been clocked in"
"this register is clocked by the I2C" "bus clock''
"reset or set signals are defined so SNAP" "will use specific internal JK flip-flop"

Figure 3. (1 of 3) 815

Philips Semiconductors Programmable Logic Devices
12c bus monitor

Application Note
AN039

u2.j = sda; u2.k /sda; u3.j u2; u3.k /u2; u4.j u3; u4.k /u3; u5.j u4; u5.k /u4; u6.j us; u6.k /u5; u7.j u6; u7.k /u6; u8.j u7; u8.k /u7; u9.j us; u9.k /u8;
sr[0 .. 7] = u[2 .. 9];
"-----------------"
" Counter section "

c2.j 1; c2.k 1; cl.j l; cl.k l; cO.j 1; cO.k l;

"3-bit binary counter" "outputs are connected to state machine"

cO.rst cl.rst c2.rst

/(/busy+ start); /(/busy+ start); /(/busy+ start);

cO.clk /(/dsblcnt */sol); cl.elk /(/dsblcnt */sol* cO); c2.clk = /(/dsblcnt */sol* cO *cl);

"------------------------------------"
" Detect IIC start & stop conditions "
"------------------------------------"

uuuy

= /sol + uuuy*/sda;

uuustart /uuuy*/sda*scl;

start

uuustart;

start.oe l;

"counter uses NANO gates in"' "clock NANO array, not in" "foldback array"
"start condition pulse"

uuuyO
uuuyl
uuubusy busy busy.oe

uuuyl*/sda + uuuyl*/scl

"bus busy signal is HIGH"

+ /sda*/scl + /uuuyl*uuuyO*sda

"from start to stop conditions"

+ uuuyO*/scl + /reset;

= uuuyl*uuuyO + uuuyl*/scl

+ /uuuyO*sda*/scl + uuuyl*/sda + /reset;

= /uuuyl*uuuyO + /uuuyl*/sda;
= uuubusy;
= 1;

"-----------------------"
" State machine portion "
"-----------------------"

state2i S2*/Sl*SO;

"duplication of state definition to be used" "in following- equation"

dsblcnt = state2i;

"dsblcnt HIGH when in state2"

s2.set al.set so.set data.rat rw.rst acka.rst ackd.rst

I (start + /busy); /(start + /busy); I (start + /busy); I (start + /busy); reset reset
reset

"reset state machine upon start" "condition and whenever bus is" "not busy (stop detected)."
"rw displays read or write bus operation" ''acknowledge address" "acknowledge data"

Figure 3. (2 of 3)

October 1993

816

Philips Semiconductors Programmable Logic Devices
12c bus monitor

Application Note
AN039

s2.elk sl.elk SO.elk data.elk rw.elk acka.clk ackd.elk

scl; scl; scl; scl; scl; scl; scl;

cntr7 = cx=7h; cntr6 = cx==6h;

"clock state machine from I2C bus clock"
"state maachine reads counter to wait" "for specific bits"

wp2 dsblcnt * /sel * data;
wpl = dsblcnt * /sel * /data;

11write data to port2" "write address and rw bit to portl"

rwo = rw; aack=acka; dack=ackd;

"pins mirror values of internal flops"

@INPUT VECTORS @OUTPUT VECTORS [rw,data,aeka,aekd]JKFFR
low = OOOOb;

@STATE VECTORS [s2, sl, sO] JKFFS stateO lllb; statel llOb; state2 lOlb; state3 lOOb;

@TRANSITIONS while [stateO]
if [entr6] then [statel]

"start detected" "wait for address"

while [statel] if [sda] then [state2] with [rw] if [/sda] then [state2) with [/rw]

"check polarity of rw bit" ''addressed port to read" "addressed port to write"

while [state2] if [ sda*/data) if [/sda*/data] if [ sda* data) if [/sda* data]

then then then then

[state3] [state3] [state3] [state3]

with with with with

[ aeka) [/aeka] [ aekd] [/aekd]

"display port data" "display address ack"
"or data acknowledge"

while [state3] if [entr7) then [state2] with [data]

"wait for 7 bits"

Figure 3. (3 of 3)

October 1993

817

Philips Semiconductors Programmable Logic Devices
12c bus monitor

Application Note
AN039

R

E
sppp ppppp ppppp

E111 11111 12222

T0 1 2 3 4 5 67 C0 1 2 3 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+

I I I I I I I I I 16161616161616161

19181716151413121118171615141312111

+------------------------------------------+

I I I I I I V I I I I I GC I I I I

I 78 I I Ic I I I I IHK I I I I

I

oooCooo0 0 DE 0 0 oo

I

o1 2 13 4 s 61 1 1 8 91 1

I

o 1

I [101I6

I/012160] P24

[lllIS

I/013159] P25

[121I4

I/014158] P26

[131I3

I/015157] P27

[14 II2 [151GHD4

CKE2156] VCC2155] WP2CJ

[161 I l [171IO

B0154] RWO Bll53] WP2

[181SCM

B2152] WPl-

[19ISCI [20 II/CKD3

B3151] AACK B4150] DACK

[211VCC4 SCL [221 I/CKD2

GHD2149] B5148] START

[231 I/CKDl

B6 I47] BUSY

[241 I/CKB/CKC

B7146] SDA

[251PD [261I/DB7

I/DA0145] I/DAl 144]

I

I

I

IIII III I IIIII

I

I VI I I IGI I I Iv I I I I I I

I CDDDDHDDDCDCDDDDD

I

I CBBBBDBBBKACAAAAA

I

I 5 65 4 33 21 0A73 65 43 2

I

+------------------------------------------+

12121213131313131313131313141414141

17181910111213141516171819101112131 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+

Figure 4. Bus Monitor Pin Layout and External Connections

October 1993

818

Phillps Semiconductors Programmable Logic Devices
Switching control unit for data communication via RS232

Application Note
AN040

INTRODUCTION
In many laboratories and institutions one can still find many PCs or similar computer equipment which are not connected via a network. There is often a need for occasional communication and data exchange in these cases and this application note describes a inexpensive solution, allowing intercommunications of up to eight stations.
The specific goal of this design was to connect six PCs and two PLO-Programmers in such a way that any two of them could communicate. Each of these devices has a serial interface (RS 232), which may be connected to another device in a null modem

configuration by connecting theTrD (Transmit Data) and RcD (Receive Date) lines of the two selected stations. With the addition of readily available software for the PCs that handshakes using a XON/XOFF protocol, the design realizes a digital switching network.
The main part of the developed design represents a MUX-DEMUX-circuit realizing the primary switching network. One Multiplexer for each direction switches the TrD line of an activated station to an internal crosspoint and a Demultiplexer connects it to the RcD wire of the corresponding station. The choice of the stations to be connected is set up by the user via mechanical switches,

so that an additional priority encoder has to guarantee the activation of only two stations at a time. In order to display the actual status of the switching network, two decoders are added which can drive 7-Segment-Displays directly and indicate the actual connection.
Figure 1 shows the basic interconnection to be realized by the switching network and the structure of the complete design is shown in Figure 2. Beside the Line Buffers (OS 232) the complete design was to be implemented using just one programmable logic component. A Philips Semiconductor's PLHS501 proved to be an excellent choice for this design.

Connector-Station 1

Tr Ox RcDx
GND

·
·

· · · ·

Connector-Station 2

GND

· ·

· · · ·

Nullmode, XON/XOFF protocol Figure 1. Interconnection via RS232 for a Simple XON/XOFF Protocol

October 1993

819

~
<T
!!l <O
""''

Select active stations

c!;ca!

Sel1

!"

s 12

Ei'

Sel3

~

s 14

!!.

I/)

Sel5

2

Sel6

!l

CX>
I\)

p~

Se/7

0 a

;;.

'"I/)

!. ;;
:::;:·r ca
z

!1
.:~:.e.

TrD 0..7

Unk:Control

MUX
TOO TD1 TD2 TD3

OUT

17PD 1

DEMUX

ADO

RD1

INPUT

RD2

RD3

SSSSSSSS RD4
EEEEEEEE RDS
LLLLLLLL RD6 01234S67 R07

Decoder for Dloploy 1

D e - for Dieploy 2

I DISP2B DISP2C DISP2D DISP2E
IS ISP2G

I I

I I

OR_ Array

RD1 0

RD1-1

RD1-2

ADO

RD1=3

RD1 4

RD1

I "-'i> ~g~=~

RD1_7

TD7 SS SSSSSS

TOO EEEEEEEE

TDS TD4

LLLLLLLL 01 234S67

TD3

OUT

TD2

TD1

TOO

MUX

17PR 1

ssssssss RD7

EEEEEEEE RDS LLLLLLLL RDS 01234567 RD4

INPUT

RD3

RD2

1" 6
1§_
14
!!:
12
1

RD1 _1Q_

ADO

DEMUX

RD2_7 RD2_6
RD2_S R~4 RD:t,3 RD2_2 RD2_1 RD2_0

RD4 RDS
RD7-i

Rc07

RcD 0..7

"C

en "~.".

(;=:":=:):;:
::T
5· co

~ 3
§'
~
0

-(")
0
:..:.l,
Q..

~ a"C
<Q
iil 3

c: ~

-::l
;:::;:
0...,

<T
iD
b
~-

a. ea.
ll>

~
1il
"'

(")

0
3

3
c:

::l

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eear.

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5<5·

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I\) (,) I\)

)z >
0
~
0

"'aa>e2"r·. " z

a0 r

Philips Semiconductors Programmable Logic Devices
Switching control unit for data communication via RS232

Application Note
AN040

BASIC OPERATION
Link Control and Priority Encoder
The first module of the design is the link control unit. As inputs it has eight selection signals indicating the choice of two stations which are to be connected. This primary selection will be converted to internal control signals for the switching network by the link control. As outputs there are 2x8 signals ( 8 for each direction of data flow) controlling the multiplexer and demultiplexer directly.
In addition to the basic function, the link control has to ensure that just two stations are connected with each other, even if more are activated by the switches. In order to fulfill this constraint there has been implemented an implicit priority encoder satisfying the following rules:
· if just two stations are chosen by the switches (the normal case) then an interconnect of these stations will be established;
· if only one switch is set active, the transmission signal of this station is directed to the Receive line of the same station (self test);
· if no switch is activated no interconnection is set up at all;
· if more then two switches were set to the 'Active' level just the two stations with the highest and lowest number ( Station 0, Station 7 - highest priority) are interconnected with each other.

Realizing such privileges the appropriate function of the switching network is guaranteed in a way, that never more then two stations are linked together.
Multiplexer
Two multiplexers are the first part of the internal switching network. Directly controlled by the output of the link control module the
multiplexers have the task to switch the
transmission line of a selected station to an internal crosspoint. Since both directions of data flow are to be supported, two multiplexers exist which link the TrD lines to the crosspoints PD and PR respectively.
Demultiplexer
The second part of the digital switching network is formed by two demultiplexers. While the multiplexers have to link the active transmitter to central crosspoints, the demultiplexers connect these internal nodes with the RcD line of the corresponding counter station. The links to be established are as well controlled by the link control module and in the result each set of multiplexer/demultiplexers realizes an interconnection between any TrD and RcD signal lines. Since two of these sets are contained, both directions of data flow can be satisfied and a logical OR-operation of both demultiplexer outputs completes the switching network.
Status Display
A display was added to the basic function to show the actual interconnection. Since the original task was to connect eight stations

with each other two numerical displays were
used to display just the number of the two active ones. In order to accomplish this
function two identical decoders were created. The decoders read directly the eight control signals from the link control module and in correspondence to the active line they drive the displays with numbers 1 to 8. For the case that no station is selected, the displays will blank.
THE PML-ARCHITECTURE
Circuits with a PML-structure represent an
architecture that can replace all typical PLDs.
In contrast to PAL and PLA circuits which use AND and OR gates, PML is composed of just one programmable logic array using only NAND gates. The outputs of each gate folds back upon itself and all other NAND gates. Inputs, outputs and bi-directional pins are available in the same way as they are in other PLDs.
The general PML-architecture is shown in
Figure 3. It is possible to realize any logical
function block with this architecture. An example of implementing a D-type Latch is shown in Figure 4. Efficient design implementations require a certain design style and software that includes an appropriate simulator, optimizer and compiler. Such tools are contained in the PLO-Development Software SNAP, which can be used to implement designs within a short period of time for PML as well as for other programmable logic devices.

n....tnhar1QQ<::l

821

Philips Semiconductors Programmable Logic Devices
Switching control unit for data communication via RS232

Application Note
AN040

1/0 0
Figure 3. The Basic Architecture of PML·Circults
D
EN

F D
EN
October 1993

Figure 4. Realization of a D-Latch by a PML-Architecture 822

Philips Semiconductors Programmable Logic Devices
Switching control unit for data communication via RS232

Application Note
AN040

A DESIGN TOOL FOR PML·CIRCUITS (SNAP)
Design implementation for PML as well as of other programmable logic ICs is supported by the Software tool SNAP. This program package, offered by Philips Semiconductors, guides the user through the complete design process beginning with the design description up to the automatic generation of final programming data and a corresponding test vector file. For the initial description of designs several entry tools are available. First there is the opportunity to create a network description via a schematic editor (e.g. OrCAD SOT). Alternatively SNAP defines a specific HDL (Hardware Description language) and by using this method, a design description may be given in terms of Boolean equations, truth tables or FSM (Finite State Machines) syntax.
Whichever entry method is used becomes converted into an internal network description in a following step. The internal network format is similar to the EDIF-format and it corresponds with the data formats used by Philips Design Station for ASIC development. So it is also possible with SNAP to import designs given as EDIF-network descriptions and moreover the internal format keeps open the choice of a PLO or a Gate Array design implementation. Finally SNAP contains a minimzer module can optimize the Boolean function thereby increasing the quality of the design implementation, sometimes significantly.
After a description has been created, the point of interest is to verify the correct operation of the design. For this purpose SNAP has included an easy to use digital simulator. The simulator, LESIM3, is contained in SNAP as well as in the Philips Design Station which has been used for ASIC-development for many years.
Basically LESIM3 supports the simulation of abstract network descriptions as well as of concrete circuit models. The simulator either assumes a constant, propagation delay value for a given, bare network or it can consider the real timing relations if the model for a

certain IC is available. The stimuli for a design simulation can be generated by an interactive, graphical wave form entry or a textual stimuli description. The graphical entry is very easy to handle and leads quickly to appropriate stimuli for smaller designs. The other choice, the textual notation of stimuli, bases on an own simulation control language (SCL) of LESIM3 and it allows the compact description of sophisticated sequences for extensive design verification. This opportunity serves more the needs of experienced designers and in correlation with fault simulator, test pattern generator, model generator and other options it makes possible all kinds of functional simulation and test.
The goal of design development software is the generation of ICs realizing an application specific function. Since the initial design description in SNAP is device independent, one task is to select a specific component. Even the choice of a PLO is made easy by SNAP, since all available devices are listed directly on the screen together with their most relevant data. After the designer has decided which PLO to use, there is only left the task of specifying pinning of the device. An initial pin assignment is suggested by SNAP automatically, which can be revised in an interactive process direcUy on the graphical presentation of the device.
If all assignments are done, the ultimate design step is the compiler run. Automatically the compiler tries to map the given network on the selected PLO-architecture and in case of success a programmer file is generated (the format of programmer file follows JEDEC No.3A standard). This file can be downloaded onto a device programmer directly from the SNAP-shell, so that the IC-implementation can be completed immediately by programming the physical device. If on the other hand the compiler fails in its run the appeared problems will be listed in a status file and in this way the designer gets hints how to modify the design for a successful compilation. Especially in these cases SNAP has an essential advantage, since the SNAP-shell with its clear structure (Figure 5)

allows additional design iterations quickly and furthermore automated.
DEVELOPMENT OF THE SWITCHING CONTROL UNIT WITH SNAP
Design Description
The general functionality of the intended switching network has been outlined already in section two. There, the complete design has been subdivided into basic modules, of which the logical function can easily be described by boolean equations. Therefore it makes sense to use the 'Equations' entry of SNAP for design description and activating this module from the SNAP-shell an editor makes it possible to fill in a script of an empty HDL-file. Using the Equation-entry any design definition has to follow the specific HDL-syntax of SNAP and Figure 6 shows this description for the complete design.
Referring to the listing (Figure 6) the basic structure of HDL-files can be demonstrated. The first section '@PINLIST' serves for the definition of primary inputs, outputs and bi-directional pins of a design. Just the names of the ports and the port types are fixed here. After declaring the 1/0-part the section '@LOGIC EQUATIONS' contains the definition of the designs functionality. In this part the output is to specify in terms of boolean equations, in which inputs, intermediate signals and logical operators can be used. The basic operators are AND ('..),OR('+'), NOT('/') and EXOR(':+:'), but more abstract operations are available too.
Within a HDL-file additional sections can be used for describing truth tables and finite state machines, but since they are not necessary for the switching network they are not explained here. Finally it should be mentioned that any project file in SNAP gets a specific file name extension upon completion of each development stage, so that the created Equation-file is marked with '.EON' and the project file is named as NullMod.Eqn.

October 1993

A?~

Philips Semiconductors Programmable Logic Devices
Switching control unit for data communication via RS232

Application Note
AN040

MacSel

Sc Capture NetGen

Abel2Snap Edif

Equations NetConv

Minimizer

Project DECODERO

Merger

15:48:01

Waveforms

SimNet

TestVector SimPrt

SimScl Plot

SimFlt

DPI

Use cursor keys to select module Use function keys to enter command
Figure 5. Snap Shell

R?4

Philips Semiconductors Programmable Logic Devices
Switching control unit for data communication via RS232

Application Note
AN040

@PINLIST

SelO

I;

Sell

I;

Sel2

I;

Sel3

I;

Sel4

I;

SelS

I;

Sel6

I;

Sel7

I;

TrDO

I;

TrDl

I;

TrD2

I;

TrD3

I;

TrD4

I;

TrDS

I;

TrD6

I;

TrD7

I;

RcDO

O;

RcDl

O;

RcD2

O;

RcD3

o·

RcD4

O;

RcDS

O;

RcD6

O;

RcD7

O;

DisplA

O·

DisplB

O;

DisplC

O;

DisplD

O;

DisplE

O;

DisplF

O;

DisplG

O;

Disp2A

O;

Disp2B

O;

Disp2C

O;

Disp2D

O;

Disp2E

O;

Disp2F

O;

Disp2G

O;

@LOGIC EQUATIONS

SsO Ssl Ss2 Ss3 Ss4 SsS Ss6 Ss7
PD =
Se7 Se6 SeS Se4 Se3 Se2 Sel Seo
PR=

SelO ;
/SelO * Sell; /SelO * /Sell * Sel2; /SelO * /Sell * /Sel2 * Sel3; /SelO * /Sell * /Sel2 * /Sel3 * Sel4; /SelO * /Sell * /Sel2 * /Sel3 * /Sel4 * SelS; /SelO * /Sell * /Sel2 * /Sel3 * /Sel4 * /SelS * Sel6; /SelO * /Sell * /Sel2 * /Sel3 * /Sel4 * /SelS * /Sel6 * Sel7;
TrDO * SsO + TrDl * Ssl + TrD2 * Ss2 + TrD3 * Ss3 + TrD4 * Ss4 + TrDS * SsS + TrD6 * Ss6 + TrD7 * Ss7
Sel7
/Sel7 * Sel6 ; /Sel7 * /Sel6 * SelS ; /Sel7 * /Sel6 * /SelS * Sel4 ; /Se17 * /Sel6 * /SelS * /Sel4 * Sel3 ; /Sel7 * /Sel6 * /SelS * /Sel4 * /Sel3 * Sel2 /Sel7 * /Se16 * /SelS * /Sel4 * /Sel3 * /Sel2 * Sell /Sel7 * /Se16 * /SelS * /Se14 * /Sel3 * /Sel2 * /Sell * SelO;
TrD7 * Se7 + TrD6 * Se6 + TrDS * SeS + TrD4 * Se4 + TrD3 * Se3 + TrD2 * Se2 + TrDl * Sel + TrDO * Seo;

Figure 6. The Complete Design Description for the Switching Network Circuit (1 of 2)

Philips Semiconductors Programmable Logic Devices
Switching control unit for data communication via RS232

Application Note
AN040

RcD7 = PD * Se7 + PR * Ss7 RcD6 = PD * Se6 + PR * Ss6 RcD5 = PD * SeS + PR * Ss5 RcD4 = PD * Se4 + PR * Ss4 RcD3 = PD * Se3 + PR * Ss3 RcD2 = PD * Se2 + PR * Ss2
RcDl = PD * Sel + PR * Ssl RcDO = PD * Seo + PR * SsO

DisplG /( Se2 + Se3 + Se4 + SeS + Se6 ); DisplD = /( SeO + Se2 + Se3+ Se5 + Se6 );
DisplE = /( SeO + Se2+ Se6 );
DisplF = /( SeO + Se4 + SeS + Se6 );
DisplA = /( SeO+ Se2 + Se3+ SeS + Se6 + Se7 );
DisplB = /( SeO + Sel + Se2 + Se3 + Se4+ Se7 );
DisplC /(Seo+ Sel + Se3 + Se4 + SeS + Se6 + Se7 );

Disp2G /( Ss2 + Ss3 + Ss4 + SsS + Ss6 );

Disp2D /( SsO + Ss2 + Ss3 + SsS + Ss6 );

Disp2E /( SsO + Ss2 + Ss6 );

Disp2F /( SsO+ Ss4 + SsS + Ss6 );

Disp2A = /( SsO + Ss2 + Ss3+ SsS + Ss6 + Ss7 );

= /( Disp2B

SsO + Ssl + Ss2 + Ss3 + Ss4 + Ss7 );

Disp2C = /( SsO + Ssl + Ss3 + Ss4 + SsS + Ss6 + Ss7);

Figure 6. The Complete Design Description for the Switching Network Circuit (2 of 2)

October 1993

R?I':

Philips Semiconductors Programmable Logic Devices
Switching control unit for data communication via RS232

Application Note
AN040

Generation of an Internal Netllst
As already mentioned, each design description within SNAP becomes converted into an internal netlist format first. In general this step is carried out automatically just by activating the corresponding program module and for the actual design this means to start the 'Net Converter' and the 'Merger' in succession. The network converter translates

the given HDL-file into an EDIF like netlist description, while the merger has no essential meaning for this design. It is rather important for larger, hierarchical designs, where this module has to merge several function blocks into one, flat netlist.
Regardless of design complexity, the merger has to be executed for each design and the

out coming netlist file with the name NullMod.Net (project name with extension '.NET') forms the bases for the following simulation and for the compiler. That's why a part of the resulting netlist is shown in Figure 7 for demonstration of this important, internal file format.

******************************************************

* Output of Merger

Version 1. 60

*Date: 10/ 1/1993

Time: 14:26:44 *

******************************************************

* Input File Name:

NULLMOD.MAC *

***N**e*t*l*i*s*t*F**i*le**N**am**e**: *************N*U*L*L*M**O*D*.N*E*T***********

NETSTART

SSl AN2 I(N48 l,Sell) O(SSl)

B48 1 INV I(SelO) O(N48 1)

SS2-AN3 I(N49 l,Sel2,N4B 1) O(SS2)
B49 1 INV I(Sell) O(N49 l)

- .- SS3-AN4 I(N49 l,NSO l,Sel3,N48 1) O(SS3)

BSO 1 INV I(Sel2) O(NSO 1)

-

#

#

Disp2B N06 I(Sel0,SS1,SS2,SS3,SS4,SS7) O(Disp2B)

Disp2C N07 I(Sel0,SS1,SS3,SS4,SS5,SS6,SS7) O(Disp2C)

*
NE TEND

NETIN Sel0,Sell,Sel2,Sel3,Sel4,Sel5,Sel6,Sel7,TrD0,TrD1,TrD2, #TrD3,TrD4,TrDS,TrD6, TrD7 NETOUT RcDO,RcD1,RcD2,RcD3,RcD4,RcDS,RcD6,RcD7, #DisplC,DisplB,DisplA,DisplF,DisplE,DisplD,DisplG, #Disp1C,Disp2B,Disp2A,Disp2F,Disp2E,Disp2D,Disp2G
*

Figure 7. The Netllst File NullMod.Net

Philips Semiconductors Programmable Logic Devices
Switching control unit for data communication via RS232

Application Nole
AN040

Design Slmulatlon
The simulation of a design is an important , step in the development of each circuit . Beside the bare functil>nal simulation, the actual device timing relations, the testability, and last but not least an appropriate test patlem needs to be generaled. All these functions can be realized by SNAP, even if only the basic procedure is demonstrated here.
Working with SNAP the first step is lo convert the nedisl into a more compact format easier

to read for the simulator. This win be
accomplished by starting lhe program module 'SIMNET' and as a result a binary file wilh the name NullMod.Bin becomes created. Additionally a stimuli file NullMod.Scl will automatically be generaled too. These automatically generated stimuli are quite arbitrary and so ii is advi&able to modify them by the module 'WAVEFORMS' or by the available lex! editor. Are the binary design file and 1he stimuli file present the real simulator 'SIMSCL' can be run and the simulation results are stored in a project file ending with

'.RES' (NuHMod.Res for the switching network). These results can either be visualized graphically on the screen by 'PLOT' or printed out by the program module 'SIMPRT'.
A complete simulation takes a good deal of work for any design and it can become quile
Part exlensive. Thars why only a small of the
stimuli file for the switching network shall be shown here for demonstration (Figure 8) and Figure 9 shows the corresponcing section of the graphical simulator output

**************************************************************

* output of Updairn

Version 1. 00

*

* Date: lO~ol/93

Time: 14:27:02

*

****rn**p*u*t*F**i*le**N**a*m*e*: ****************N*U*L*L*M**O*D*.N*E*T*******************

* OUtput File Name:

NULLMOD. SCL *

***************~**********************************************

P SelO, Sell, Sel2, Sel3, Sel4, SeO, Sel, Se2, Se3 PCO S 0 (500) SelO S 0 (1000) Sell S 0 (1700) Sel2 S 0 (2500) Sel3 S 0 (2800) Sel4 S 0 (3100) Sel5 S 0 (3500) Sel6 S 0 (4000) Sel7
= SU time 5000

Figure 8. A Section of the Simulator Stimull for the Verification of the Design

File: NULLMOD.RES

DELAY= Ons

Marker m 700na

= Sea/Div lOOns

Sel 0 B Sel 1 L Sel 2 L Sel 3 L
[,
Sel 4 L

_f I

Se 0 B Se 1 B

L

_J

1

Se 2 L Se 3 L

A

500

1000

1500

Figure 9. Graphical Pl'ftentallon of Simulator Output

2000

October 1993

828

Philips Semiconductors Programmable Logic Devices
Switching control unit for data communication via RS232

Application Note
AN040

The Compiler
The final aim of the design process is to generate a data file in order to customize programmable logic devices with the functionality of the developed design. The programming data format generated by SNAP follows the international standard JED EC No. 3A, which is widely accepted and used in industry and research.
The compiler block of SNAP has the task to map a given, verified netlist onto a certain device architecture and to convert the result into a JED EC file readable by a device programmer. In order to do so a specific device should be chosen and a pin out selected. For this design, a PLHS501 is chosen within the program module 'DEVSELECT' and the Pinning needs to be entered with 'PINSELECT' in correspondence to that of Figure 10. After running these two programs, the compiler can be started which fits the design into the chosen device. In case of problems during the compilation an error file (with extension '.ERR') will be generated reporting errors, warnings and information about necessary modifications to the initial

design. But for the design of the switching network the compiler finishes its work with success resulting in a JEDEC file named NullMod.Jed. This file can now directly be used to program a PLHS501 or it can be modeled for a final timing simulation.
PROGRAMMING OF THE PLHS501
Among other alternatives the UP2000 device programmer represents an interesting, efficient tool for the development of programmable logic especially in laboratories and smaller enterprises. Manufactured for use in PC environments it consists of an expansion board for PCs (8-Bit Slot), an adapter box, several adapters for mounting various package layouts, and corresponding programmer software. This device programmer and associated software supports all of the programmable logic devices that are contained within the SNAP library, so that the UP2000 is the ideal companion for the SNAP development

system. The programmer software is mostly self explanatory and with some skill it can directly be included into the SNAP shell. Using the JEDEC file from SNAP and a UP2000 to program a PLHS501 revealed no problems at all. The programming of the design of the switching network into the PLHS501 was finished within one minute.
SUMMARY
The design of a digital switching network as described here was implemented within just one Philips PLHS501. Adding some buffer/drivers and the necessary switches and display elements completed the design to a working application. It was tested within a laboratory of 8 PCs, which were interconnected by the switching network via their standard serial interfaces. By changing the switches, any of the computers could be interconnected and using communication link programs such as Laplink or Norton Commander, a simple data transfer method was realized.

October 199~

Philips Semiconductors Programmable Logic Devices
Switching control unit for data communication via RS232

Application Note
AN040

Octoh.,r 1993

U1 T10UT R11N
T20UT R21N
C1+ C1C2+ C205232
U2 14 T10UT 13 R11N
T20UT R21N
C1+ C1C2+ C205232
U3 14 T10UT 13 R11N
T20UT R21N
C1+ C14 C2+ C2DS232
U4 14 T10UT 13 R11N
T20UT R21N
C1+ C1C2+ C2DS232

T11N R10UT
T21N R20UT
V+ V-

PLHS501
TrOO RcDO Tr01 RcD1

Dlsp1A Dlsp1B Oisp1C Dlsp1D
Di'!> 1E
Dlsp1F Dlsp 1G

Yee
8 0

Vee

T11N R10UT
T21N R20UT
V+
v-

TrD2 RcD2
Tr03 Rc03

= YCC

T11N R10UT
T21N R20UT
V+
v-

Tr04 Rc04
Tr05 Rc05

T11N R10UT
T21N R20UT
V+
v-

Yee
Tr06 Rc06 Tr07 RcD7
T
Yee

Disp2A Dlsp2B Dlsp2C
Dlsp2E Dlsp2F

8

YCC

vcc
SWDIP-8
1234 5678
SeiD Sel 1 Sel2 Sei3 Sel4 Sel5 Sel6 Sel 7

Figure 10. Schematic of the Complete Switching Network 830

Phillps Semiconductors Programmable Logic Devices
Microcontroller acceleration

Application Note
AN035

INTRODUCTION
This paper presents the design of an accelerator that increases microcontroller performance without resorting to multiple expensive high speed memory chips or a high-cost superscalar controller_ The design of a data acquisition unit, similar to a logic analyzer, is presented as an example. The task of the analyzer is to capture and respond
to data, sampled at a rate faster than the
microcontroller can operate.
Data capture is a hardware-intensive function
- it is difficult using software to synchronize
controller operations with external data and balance memory requirements. On the other hand, formatting captured data and outputting it for display is best done in software. The accelerator exploits these characteristics by using a programmable logic device with the microcontroller. This partitions data acquisition and display into fast hardware-intensive and slower, software-intensive functions.
What Is Microcontroller Acceleration?
Microcontroller acceleration is anything that makes a microcontroller appear to operate faster. Accelerators are special purpose hardware units that perform a time critical task that a microcontroller cannot. In the microprocessor world, accelerators have been hardware arithmetic units, simulation engines or graphics engines. The accelerator works with the microcontroller, either intercepting the time critical activity automatically (coprocessor), or acting when requested by the microcontroller.

To illustrate, an arithmetic coprocessor automatically intercepts multiply and divide instructions, which slow down an integer based microprocessor. The coprocessor does the arithmetic operations with special purpose state machines and floating point hardware. A simulation engine performs high speed logic evaluations and operates directly on a circuit model contained in memory. Graphics engines operate directly with the display memory, performing the basic housekeeping and bit transformations with special purpose hardware. Each acceleration device permits the host processor to execute other code while the accelerator operates at high speed doing its special purpose activity.
SYSTEMATIC APPROACH TO ACCELERATION
Can we systematically design hardware accelerators? The answer to that question is - probably. The standard approach is part science and part art, much like system partitioning. In fact, accelerator definition tracks functional partitioning in many ways.
The microcontroller system must be designed by first identifying microcontroller activities and those that must be done externally. The same approach is used for microprocessors as for microcontrollers, and will be shown by example.
Matching a microcontroller or microprocessor to a target task involves several steps. 1. Identify tasks that must operate at full
speed and tasks that can operate slower.

2. Identify operations that are most efficient when handled by microprocessor data paths and those that must be outside, handled by high speed logic.
3. Maximize tasks that can be done by software and minimize tasks that must be done by application specific hardware.
4. Identify which tasks must operate with custom hardware because of their asynchronous nature.
Much of the task partitioning is intuitive, but
some may be quantitatively derived. For
instance, the cycle time of the microprocessor is a constraint. Any activity that occurs in less time than the cycle time of the processor must by handled by hardware that can respond quickly enough. Any activity that is not critical is a candidate for being handled by the microprocessor.
The key to success in acceleration is correctly identifying the tasks that must be done at speed and those that can wait. This is the first partition.
The next step is to identifying slow and fast datapath operands. For instance, initializing a
counter or a comparator may be done slowly,
but the counting and comparing operations must occur at full speed. Isolating these kinds of operations is another partition.
Additional steps may or may not be needed.
However, synchronizing signals that are asynchronous is very difficult for controllers to do unless the signals are extremely slow and the degree of synchronization is loose.

Phifips Semiconwc:tors Programmable Logic Devices
Microcontroller acceleration

Applkiation Note
AN035

AN EXAMPLE Lers look at an example taken from the instrumentation wolld. Most digital engineers are famUiar with logic analyzers, because they use them for digital system debug. The idea is to make an .actd~ unit for a, perSonal computer, using the PC;s 11bilities to manage and display data. However, the PC cannot do high speed data capturing or triggering (stopping the data capture), unless ridiculously low speeds are the goal. For a 40 MHz data capture rate, these tasks must be done by a second processor, passing data frames to the PC. This unit, shown in Figure 1, could even be inexpensively designed into a system that might benefit

from remote aecess diagnostics..Clearly. it can operate stand,.alone. as well. .
To handle the 40 MHz data rate, samples must occur every 25 nanoseconds, and be stored in consecUtive RAM locations. The RAM will hold a sampled time iinage of probe voltages captured by the analyzer. Just
passing the data into the RAM is no problem,
but an address counter must manage the RAM. We'll assume a 20 nanosecond SRAM, giving some time margin.
There are RISC processors today, that could pass data through them and update counters near this rate. However, that is not all that must be done. This is the tough part - each

data item must be examined if a pretriggering feature is-implemented.
Pre-triggering permits the analyzer tci recognize a data item, and when recognized, strip capture. This important feature permits designers to isolate bugs, and find what caused them. An important added feature, is time delayed stopping.
Time delayed stopping permits more data capture after the trigger event, allowing assessment of the results of a bug. Time delayed stopping must be done at lull hardWare rates to be effective. It gets complicated.

oa::a::aJOODDDDCJ
CilJ[][JDDDDOCIJ[J[l
DDDDDODDDDDDDDU DDDDDDOa:a:a::::J

LOGIC
ANALYZER
Figure 1. PC Based Logic Analyzer

SYSTEM

· ·

UNDER TEST

A~?

Philips Semiconductors Programmable Logic Devices
Microcontroller acceleration

Application Note
AN035

Now, let's oudine the tasks to be done. 1. The logic analyzer must be enabled by
the PC.
2. Each sample must be captured, and examined.
3. In parallel, a RAM address must be calculated.
4. The data must be stored at the address.
5. If the data matches a trigger value, a time delay procedure must be started.
6. Samples must continue to be captured and addresses calculated.
7. When the time delay value is reached, sample capture is to cease.
8. The PC must be informed that sample capture has ceased.
9. At this point, the PC assumes control and reads back the RAM for display.
Everything is possible for a fast RISC to perform up to step four, when a trigger event occurs. At this point, the complexity increases

to the point that at least four tasks occur simultaneously. Examining the sample, storing it, updating the address and the delay must occur in one 25 nanosecond period, to keep up with arriving samples. This suggests hardware speeds are required, and sets the speed of the events to occur. Since each task can be done within the same 25 nanosecond period, the next sample can arrive and be handled. Even if the RISC could keep up with the tasks, it would be a prohibitive solution (at least one thousand dollars) for processor and memory. Twenty nanosecond SRAMs aren't cheap, and fast 32-bit RISCs need several of them.
Even by restricting the analyzer to an 8 bit one, doesn't help much. RISC processors of this speed are inherently 32 bits wide. This motivates us to find an alternative solution. We'd like to make a unit for less than 100 dollars and fifty is preferable.
First, let's partition the problem into two pieces, on-line tasks and off-line tasks. On-line tasks are those that occur during data capture, and must meet the 25 nanosecond

time constraint. Off-line tasks are those that occur when the heat is off, and have no particular time constraints beyond ·user friendly" speeds.
Enabling the analyzer, reading back the RAM contents and dealing with the PC are off-line tasks. Sample capture, store and triggering activities are on-line tasks. The design must do the on-line tasks in pure hardware and the off-line tasks in micro-<:ontroller software. Figure 2 shows the microcontroller and data capture unit along with an SAAM.
By isolating the high speed operations into application specific hardware, forming an accelerator, a large class of inexpensive microcontrollers can meet the needs of the off-line tasks. First, because the needs of this example are only for 8 bit data, we'll use an 8 bit microcontroller. A microcontroller with enough 1/0 ports and the ability to do the off-line tasks in a single chip will be the most desirable. Off-line tasks include managing the sample RAM, communicating with the PC and enabling or disabling !he accelerator.

CLOCK

M

DATA

I
c

R

0
c

0

FPGA

N

T R

SAAM

0

L

L

E

R

READ/WRITE
CONTROL

DATA

Figure 2. Logic Analyzer Block Diagram

October 1993

833

Philips Semiconductors Programmable Logic Devices
Microcontroller acceleration

External lnterrupta

128
RAM

Application Note
AN035

Timer 1 Timer 0

Counter Inputs

~

P1

P3

Address/Data

Figure 3. The 80C51

TXD RXD

MICROCONTROLLER SELECTION
The design requires serial access to the PC, and at least four ports for handling the accelerator. These requirements are met by a single 8051 type microcontroller. Because 8051 s are inexpensive and readily available, let's pick one that has an additional feature speed - ensuring an enjoyable user interface for off-line activities. The 33 Mhz version of the 8051, offered by Philips Semiconductors meets the basic needs.
An interesting aspect of the 8051 family, is that there are so many derivative parts. The design presented here, can be adapted in many ways to meet other needs. For instance, I picked the 33 MHz version, preserving user frustration. I could have picked the 80CL41 Ofor low power, the 87C751 to minimize the size, or the 87C451 if

I needed more 1/0 ports. Other family members have fewer ports (in smaller packages) and built in AID converters. For our needs, we'll simply pick the fastest microcontroller, the 80C51. Figure 3 shows the architecture of the 80C51. If the unit was to be portable for a notebook or palmtop PC, the chosen 8051 would probably be different.
ACCELERATOR HARDWARE SELECTION
The accelerator (data capture unit) is another issue. First, it must be able to do the tasks described as on-line, and it must do them in 25 nanoseconds. This should not be confused with a pin to pin propagation time of 25 nanoseconds, but simply at a rate tracking 25 nanosecond samples. As long as the RAM addresses and the captured data arrive at the SAAM together - at a rate equal to 40 MHz -

the analyzer tracks the samples. It is important to update the counter at the sample rate, as well as time delay a pretriggered sample at the same rate. This is easily done with an FPGA type part or a complex PLD.
For this task, I picked a Philips Semiconductors PML 2852 (Figure 4). The PML 2852 includes 8 bit registers which operate as input data synchronizers and uses JK flip flops for internal counters. The PML 2852 has 52 JK and D type flip flops, with over a hundred very wide Nand gates inside. The data rate of 40 MHz is well below the PML 2852 system clock rate. Interconnect routing is not a problem because of the fully connectible foldback architecture. In all, the PML 2852 provides enough flip flop and gate resources in an 84 pin package, to form the needed comparators, counters, multiplexers and timers to complete the accelerator.

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Philips Semiconductors Programmable Logic Devices
Microcontroller acceleration

Application Note
AN035

1 3 8 8

8
·t¢i·~

October 1993

Figure 4. PML2852 Detail with SNAP Resource Summary Designations 835

~

CT

i:i.111:-i:

!!l

P E7

AIN AOUT

CD

P 6

BIN BOUT·

&l

fl

CIN COUT

~ ~

DIN OOUT"' EIN EOUT

fl
~ ~

FIN FOUT GIN
HIN GOUT

::fllOilli AD

HOUT.,

LOAD

PROBEDATAREGISTER

·-·-··
l~~? l~~? l~8?
IlN~O~OJ l~~d IlN~F~?l l~~?
~SEL

OOUTA OOUTB OOUTC DOUTD OOUTE.J OOUTF OOUTG OOUTH.J
-

6
5 ~4
OATOU13
~2 ~UIO1J

!!
"; c ' .!"0,".'
Ill
i"i'
Ii """''' ;;·
>
.!"!!'.
'<
~
c
~

[l;QMj>IN7

RI I<'<'
AIN AOUT

@MPIN6

BIN

~ ~ING 4 IN DIN

[Qi: MPfil

EIN

BOUT
GOUT .,
DOUT

~ Mi'lli2:

FIN EOUT

ICClMp N1

GIN FOUT

~HIN GOUT

a - ~~

COMPARAND REGISTER

XC CVRS

< ATABUS? < AT~ /< AIABL~ << AA"fATi3D~S4 _;><llAiil6:US2: < ~ < ilAJAiliJSO
ma

~ DB7
j+ D86 ~ DBS j+ DB4
DB3
DB2 DB1
I. DBO
ENA

NDB7 .J

ND86 · ND85 -

NDB4 ·

ND83 ·

ND82 · NDB1

ND80

Dg:IN~7g

~ ~

DIN4 ~

81~~

DIN1 DINO

DIR· 1 08~7 XFRS TO DATABUS DIR= 0 DATABUS XFRS TO D~7

~~C=ci ~~~~= ?~~~~~'686~g~~~T~7 COMP aA1O

~~/1~2

_ COMPARE

--f--<r--<UC~O!iiM~PA~R~E]J

tdl BUFF

r

AIN AOUT"i
H-1--1-++-I--- BIN BOUT o1

.._,__._,_._,___ __. GIN GOUT 91-·

"

a8~4
ag fi
*i~
ig
~

H-+-1----l· ~:~
.._,__ ___.GFIINN ~HIN

OOUT - 1 EOUT.J FOUT 1>1-----' GOUT

I~ ~ ENABI E ~ =KIN

_,,c,.o.,N.,.TR,,o.,L_ _ _ __

ENABLE LOCKIN

COMPARE 4 - - NWRITE

r t LOAD HOUT -I

I '
TNi71lii

COMPARE ENABLE
J REGISTER

[QN [fill
~

CNTSTROBE COUNTENA ,.i

LEAR

COUNT ....,
1 I

1

COUfillL

NWRITE

1 1 11 1

D7

H

D6

G

D5

F

D4

E

D3

D-

D2

C

D1

8

DO

A

j. COUNT ~ CLK LOAD~
' I

ADDRESS7
ADDRESS6 ADDRESS5
ADDRESS4 ADDRESS3 ADDRESS2] ADDRESS1 ADDRESSO]

"tJ

s:::

2: ~

(/)

(...'.).."

(/) in

0
(")

3
i;i"

0
:::J
........+.

"a' . ~

0

(il

(i) ......
!l>
(") (")

a"ti
"ii'l
3 3
Ill

~

2:
in

C...D... !l>

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<Q. 0

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0

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::>

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z

0

!D

Philips Semiconductors Programmable Logic Devices
Microcontroller acceleration

FROM MICROCONTROLLER CONTROL POAT BIT

TIED TO PROBELOAD
FROM COMPARATOR
U1 FROM MICAOCONTROLLER INV CONTROL PORT BIT
U4 !NV FROM MICROCONTROLLER

U16
NA2 U15
NA2 U2
NA2 UG
NA3

Application Note
AN035

UUU19
NA2 To Counts Clock Input NA2 U] To Memory Write ENA

INV

U12

L

AN2

Timeoul Staned

r TimerClock

AN2

AN2

Figure Sb Control Block Schematic

October 1993

837

Philips Semiconductors Programmable Logic Devices
Microcontroller acceleration

Application Note
AN035

SOME DESIGN DETAILS Let's look at some of the more critical internal functions (Figure Sa) to understand the accelerator operation. The pretrigger structure is fonned with an eight bit register holding a compare pattern, a series of Exclusive-Nor functions and a second register holding bit enables. The bit enables pennit "don't care" triggering. The Exclusive-nor gates are made from foldback Nand gates. The entire unit is designed to fonnat 8 bit samples into 256 byte data frames, but the design may be expanded by cascading additional PML 2852s and SRAMs. Cascading can be done using

leftover pins, and the fact that the counters and comparators are made in a expandable fashion.
Three of the 8051 ports are used to drive data values into the PML part, with the fourth port makes strobes for the various registers. One of the 8051 ports is designated as bidirectional and is used to read and write data values, compare operands, and counters. The pretrigger in this example is set at a fixed value of 16 time units, but this value can be changed.
The design shown in Figure Sa, was done using Philips Semiconductors PLO design

software, SNAP. SNAP (Figure 6) permits a gate array flow for the entire PLO family at Philips Semiconductors, including the PML family. SNAP supports schematic and equation entry, device independent design, optimization. fitting and back annotated logical simulation. All of the blocks in Figure Sa were written using Boolean equations, except for the control block. The control block was described using a schematic shown in Figure 5b. The SNAP equation listings for the other blocks are shown in Figures 9a, b, c, d, and e, with the final PML2852 pin layout in Figure 1O.

MacSel

ScCapture

Abel12Snap

Equations

NetGen

Edif

NetConv

Minimizer

Project LOGIC

Merger

13:08:21

Waveforms

Compiler

TestVector SimPrt

SimFlt

ModGen

DPI

Plot

Use cursor keys to select module Use function keys to enter command
Figure 6. SNAP Flow Chart

October 1993

838

Philips Semiconductors Programmable Logic Devices
Microcontroller acceleration

Application Note
AN035

ANALYZER OPERATIONS
The order of operations is shown in Figure 7. Initial values are loaded into the counter, the compare and enable registers. When a control strobe is sent from the 8051 to the PML 2852, automatic data capture begins. Data capture continues, loading consecutive values into the SAAM, at that point.
When a data value matches the qualified trigger pattern, a time delay counter is enabled and 16 more samples are taken. At

the end of the delay, the SAAM write circuitry is disabled. The 8051 software scans the internal control register and senses the data capture complete condition. The 8051 begins SAAM readback at that point. If a trigger pattern is never encountered, data sampling continues and will load one 256 bit frame after another on top of old values. As mentioned before, the depth of the SAAM can be easily expanded to capture these frames using more parts, if needed.

Readback occurs when the 8051 resets the SAAM address and reads 256 consecutive values from it. The 8051 updates the counter, reads the SAAM and inputs the data. The data is passed on an RS-232 cable to the PC, where a separate display routine takes the data and forms a familiar waveform pattern. Remember that readback is an oflline activity. The data capture hardware is stopped, and the RAM dumping occurs at a leisurely rate.

SETUP

READBACK

LOAD COMPARE REGISTER

OFF-LINE 8051 CODE SETS UP ANALVZER

INCREMENT ADDRESS NO

OFF-LINE
8051 TRANSFERS ANALYZER BACKTOP.C.

READBACK

ON-LINE 8051 SCANS WHILE
ANALVZER FREE RUNS

DONE

Figure 7. Simplified Analyzer Operation Flow

October 1993

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Philips Semiconductors Programmable Logic Devices
Microcontroller acceleration

Application Note
AN035

RESULT DISPLAY
When the data is retrieved by the PC, it can be formatted and displayed in classic logic analyzer style. Separate channels are simply the separate SRAM data lines. Display is simply a matter of finding the frame starting point, and making transition display segments on the screen.
As an example of this type of display, see Figure B. Figure B is actually, a display of data taken from the simulation section of Philips Semiconductors SNAP design software, running on a PC. The simulation software in SNAP mimics the display format of a logic analyzer. By formatting the information taken from the logic analyzer and renaming the file for SNAP's needs, a usable result is obtained. The SNAP simulation display includes features like waveform expansion, cursor movement, overlap and reorder of waveforms, etc.

CONCLUSIONS
At the outset of this paper, a procedure for making accelerators was outlined. By example, a small logic analyzer design was shown, to speed up an inexpensive microcontroller, with a low cost FPGA.
But why is this class of designs so important? First, the logic analyzer shows which activities must be made in hardware and which can be in software. Second, the design is typical of a larger class of designs parallel data operation designs. Included in this category are other instrumentation applications and many computer control applications. For instance, if the logic analyzer had the triggering hardware removed and only passed the data through it to the SRAM, it becomes a generalized data acquisition unit. If the data acquisition unit was supplemented with a single B bit AID

converter, and its analog input was taken as a probe, it becomes a digital oscilloscope. If the data acquisition unit passes data to the SRAM, and adds a word counter, the unit becomes a DMA controller: Other examples exist. Each simply takes a high speed task, offloads the microcontroller and makes the overall operation much faster.
There are other design categories where accelerators can be beneficial. Most notable is the class of serial data operation designs. These designs can also be made with inexpensive microcontrollers and low cost FPGAs. Their primary abilities include capturing and sensing serial data patterns and taking action, as well. The world of high speed data communications uses these types of machines, accelerating lower level data operations. However, that is the topic of another paper!

CLOCK H RESET H DATAl H DATA2 L
DATA3 L _ s - i
DATA4 H DATA5 L DATA6 H DATA7 H DATA8 L

100

300

500

700

900

Figure 8. PC Waveform Displays

llOO

October 1993

840

Philips Semiconductors Programmable Logic Devices
Microcontroller acceleration
@PINLIST AIN I;BIN I;CIN I;DIN I;EIN I;FIN I;GIN I;HIN I;LOAD I; AOUT O;BOUT O;COUT O;DOUT O;EOUT O;FOUT O;GOUT O;HOUT O; @LOGIC EQUATIONS AOUT.D AIN; BOUT.D BIN; COUT.D CIN; DOUT.D DIN; EOUT.D EIN; FOUT.D FIN; GOUT.D GIN; HOUT.D HIN; AOUT.CLK LOAD; BOUT.CLK LOAD; COUT. CLK LOAD; DOUT.CLK LOAD; EOUT.CLK LOAD; FOUT.CLK LOAD; GOUT. CLK LOAD; HOUT.CLK LOAD; @INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANSITIONS
Figure 9a. BUFF Block Equations
@PINLIST INAO I;INAl I;INBO I;INBl I;INCO I;INCl I;INDO I;INDl I INEO I;INEl I;INFO I;INFl I;INGO I;INGl I;INHO I;INHl I SEL I; DOUTA O;DOUTB O;DOUTC O;DOUTD O;DOUTE O;DOUTF O;DOUTG 0 DOUTH O; @LOGIC EQUATIONS DOUTA = /SEL*INAO + SEL*INAl; DOUTB /SEL*INBO + SEL*INBl; DOUTC /SEL*INCO + SEL*INCl; DOUTD /SEL*INDO + SEL*INDl; DOUTE /SEL*INEO + SEL*INEl; DOUTF /SEL*INFO + SEL*INFl; DOUTG /SEL*INGO + SEL*INGl; DOUTH /SEL*INHO + SEL*INHl; @INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANSITIONS
Figure 9b. MUX Block Equations

Application Note
AN035

October 1993

841

Philips Semiconductors Programmable Logic Devices
Microcontroller acceleration

@PINLIST DBO B;DBl B;DB2 B;DB3 B;DB4 B;DBS B;DB6 B;DB7 B; NDBO O;NDBl O;NDB2 O;NDB3 O;NDB4 O;NDBS O;NDB6 O;NDB7 O; DINO I;DINl I;DIN2 I;DIN3 I;DIN4 I;DINS I;DIN6 I;DIN7 I; ENA I; @LOGIC EQUATIONS DBO DJ:NO; DBl DINl; DB2 DIN2; DB3 DIN3; DB4 DIN4; DBS DINS; DB6 DIN6;
DB7 = DIN7;
DBO.OE = ENA; DBl.OE = ENA; DB2.0E =ENA; DB3.0E =ENA; DB4.0E =ENA; DBS.OE= ENA; DB6. OE = ENA; DB7.0E =ENA; NDBO DBO; NDBl DBl; NDB2 DB2; NDB3 DB3; NDB4 DB4; NDBS DBS; NDB6 = DB6; NDB7 = DB7; @INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANSITIONS
Figure 9c. XCVRS Block Equations

@PINLIST

COUNT I; LOAD I; DO I;Dl J:;D2 I;D3 I;D4 J:;DS J:;D6 I;D7 I; CLK I;

A O;B O; C O; D O; E O; F O; G O; H O;

@LOGIC EQUATJ:ONS

H.J = COUNT*A*B*C*D*E*F*G + LOAD*D7;

H.K = COUNT*A*B*C*D*E*F*G + LOAD*/D7;

G.J = COUNT*A*B*C*D*E*F G.K = COUNT*A*B*C*D*E*F F.J = COUNT*A*B*C*D*E F.K = COUNT*A*B*C*D*E E.J = COUNT*A*B*C*D

+ LOAD*D6; + LOAD*/D6; + LOAD*DS; + LOAD*/DS; + LOAD*D4;

E.K = COUNT*A*B*C*D

+ LOAD*/D4;

D.J = COUNT*A*B*C D.K = COUNT*A*B*C

+ LOAD*D3; + LOAD*/D3;

C.J = COUNT*A*B
C.K = COUNT*A*B
B.J = COUNT*A

+ LOAD*D2; + LOAD*/D2; + LOAD*Dl;

B.K = COUNT*A A.J = COUNT A.K = COUNT

+ LOAD*/Dl; + LOAD*DO; + LOAD*/DO;

H.CLK = CLK;G.CLK CLK;F.CLK = CLK;E.CLK = CLK;

D.CLK = CLK;C.CLK CLK;B.CLK = CLK;A.CLK = CLK;

A.SET = l;B.SET=l;C.SET=l;D.SET=l;E.SET=l;F.SET=l;G.SET=l;H.SET=l;

@INPUT VECTORS

@OUTPUT VECTORS

@STATE VECTORS

@TRANSITIONS

Figure 9d. COUNTS Block Equations

October 1993

842

Application Note
AN035

Philips Semiconductors Programmable Logic Devices
Microcontroller acceleration
@PINLIST AO I:BO I;Al I;Bl I;A2 I;B2 I;A3 I;B3 I; A4 I;B4 I;AS I;BS I;A6 I;B6 I;A7 I;B7 I; ENAO I;ENAl I;ENA2 I;ENA3 I; ENA4 I;ENAS I;ENA6 I;ENA7 I; COMPARE O; @LOGIC EQUATIONS EQO /(AO:+:BO)+ENAO; EQl /(Al:+:Bl)+ENAl; EQ2 /(A2:+:B2)+ENA2; EQ3 /(A3:+:B3)+ENA3; EQ4 /(A4:+:B4)+ENA4; EQS /(AS:+:BS)+ENAS; EQ6 /(A6:+:B6)+ENA6; EQ7 /(A7:+:B7)+ENA7;
= COMPARE EQO*EQ1*EQ2*EQ3*EQ4*EQS*EQ6*EQ7;
@INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANDITIONS
Figure 9e. COMP Block Equations

Application Note
AN035

October 1993

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Philips Semiconductors Programmable Logic Devices
Microcontroller acceleration

Application Note
AN035

DDDD

AAAAAA

AAAA

BDDDDDD

TTTT

HRRRRRR

0000
u u u u

LBBBBBB
o s s s s s·s

T T T T

AS S S S S S

0 1 2 3

D7 6 5 4 3 2

+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+

11111 I I I I I I I I 181818181817171717171

1110191817161514131211141312111019181716151 +-----------------------------------------+

IO O O O I I I V I I I I I V C I I I I I II

10 1 2 3 I I I c I I I I I s KI I I I I II

I

O 0 0 c o 0 0 0 0 S B o o 0 0 0 OI

I

0 1 2 1 3 4 5 6 7 4 1 8 9 1 1 1 11

l

0 1 2 31

I

I

[121I8

04174] DATOUT4

[131I7

05173] DATOUT5

[141I6

06172] DATOUT6

CLEAR [151I5

07171] DATOUT7

LOAD [161 I4

I/014170] ADRBSSl

BHABLB [171I3

I/015169] ADRBSSO

DIR [18 II2

CKB2 I 68] ADDRBSSLOAD

[19IVSS1

VCC4167]

CLOCKIH [201Il

BOl66J DATBUSO

SBL [211IO

Bll65] DATBUSl

[221SCM

B2164] DATBUS2

[23ISCI

B3163] DATBUS3

CHTSTROBB [241I/CKD3

B4162] DATBUS4

[2SIVCC2

VSS3161]

[261I/CKD2

BSl60] DATBUSS

[271I/CKD1

B6159] DATBUS6

PROBLOAD [281I/CKB/CKC

B7158] DATBUS7

[291PD

08157] COMPARE

PROBB7 [301I/DB7

09156] 'llWRITB

PROBB6 [311I/DB6

010155] COUHTOUT

PROBES [321I/DBS

011154]

I

I

I IIIIII III I III

I

IV I I I I I I v I I I I v I I I

I

IC D D D D D D S D D D C D C D D D O 0 0 01

IC B B BBB A S A A AK AC A A A 1 1 1 11

15 4 3 2 1 0 7 2 6 S 4 A 3 3 2 1 0 S 4 3 21

+-----------------------------------------+

131313131313131414141414141414141·151515151

1314151617181910111213141516171819101112131 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
p p p p p c ccccc ccc

RRRRRO 00000 000

OOOOOM MMMMM MMM

BBBBBP P P P P P P P P

BBBBBI I I I LI I I I

43210H HHHOH NHN

7 654A3 210

D

Agure 10. Data Capture Unit Pin Layout

October 1993

844

Phillps Semiconductors Programmable Logic Devices
Implementing counters in PML2X52 devices

Application Note
AN042

INTRODUCTION
The PML2552 and PML2852 devices contain internal clocked JK-type flip-flops that may be used to implement counters, shift registers, or synchronous state machines. JK-type flip-flops can generally be used to implement state machines and counters very efficiently. For state machines, JK flip-flop based machines require product terms (AND gates) only to transition between states. Product terms are not required to hold the state registers in specified states as they would be for D-type flip-flop implementations.
For implementing counters, JK-type flip-flops can be easily configured as T-type or toggle flip-flops by connecting the J and K inputs together. Only one product term per counter bit is required to construct a counter in this manner.
The PML2552 and PML2852 each contain two groups of ten clocked JK-type flip-flops. One group features independent clocks and independent reset inputs. The other group of ten features a common clock and a common preset input. These are indicated as JKCL552 and JKPR552 respectively in Figure 1. It is the purpose of this application note to demonstrate how, using Philips Semiconductors SNAP software, counters may be implemented most efficiently in the JKCL552 group of flip-flops. Counters of up to ten bits may be implemented using only one of the 96 foldback (FBNAND) NANO gates. This is accomplished by using the independent clocking feature of the JKCL552 flip-flops.
TYPICAL COUNTER IMPLEMENTATION
The most common way of connecting JK-type flip-flops as a counter is shown in the listing of Figure 2. This arrangement connects all clock inputs to a common clock. The least significant counter bit flip-flop has its J and K inputs tied HIGH. This flip-flop will change state after every clock pulse. The next bit flip-flop has its J and K inputs tied to the output of the least significant bit flip-flop output. If its J and K inputs are tied to the Q output of the previous flip-flop, it will toggle after a clock when the LSB is HIGH, producing an up counter. If its J and K inputs

are tied to the QN output, then it will toggle when the LSB is LOW, producing a down counter. The remaining flip-flops in the counter have their J and K inputs tied to the outputs of all previous counter bits. In all Philips Semiconductors PLO devices that contain JK flip-flops, the same product term that connects to the J input may also be connected to the K input. For PML this is also true except it is a NANO gate connecting to the integral NANO gate inputs on the JK flip-flops.
This type of counter will use one foldback NANO gate (FBNAND) for each bit in the counter. It may be implemented in the JKPR552 or the JKCL552 groupings of flip-flops. Which group the counter is implemented in can be controlled in SNAP by defining an equation for the RST or SET inputs of the flip-flops. If a SET equation is defined, SNAP will try to use the JKPRFF devices. If a RST equation is supplied, SNAP will try to use the JKCLFF devices. If neither SET or RST equations are defined or both are defined, SNAP may try to make JK flip-flops totally from the FBNAND gates.
DEVICE SPECIFIC COUNTER
Although using only one FBNAND gate per counter bit is fairly efficient, a ten bit counter would require ten FBNAND gates. A design technique is available that can implement up to a ten bit counter in the JKCL552 group of flip-flops using only one FBNAND gate for the whole counter. Figure 3 contains a schematic representation of a 3-bit version . Figure 4 shows the associated SNAP simulation waveforms. As can be seen in Figure 3, all of the flip-flops JK inputs are tied HIGH. This is were the one FBNAND gate is used. All of its inputs are disconnected so that its output is LOW. The FBNANDs output is then connected to the integral NANO gates on the JK flip-flops inputs.
This counter uses a NANO gate to clock each bit in the counter. As the JKCL552 flip-flops are clocked independently by a special array of NANO gates, this design fits perfectly into the PML2552 or PML2852 devices.
Figure 5 shows SNAP equations for a 10-bit version. Figure 6 shows a SNAP resource

summary for this 10-bit implementation to verily that only one FBNAND gate was used. Figure 7 shows the clock NANO array portion of a PML2552 fusetable, demonstrating again how nicely the counter may be implemented in a PML2552 or PML2852. A fusetable representation of any PLO device is available in SNAP by running FUSTABLE.EXE from the DOS command prompt.
SPECIFIC REQUIREMENTS
This counter design may be altered to provide for a count of any length. Figure 8 shows a modification to the 3-bit counter to produce a modulo-5 counter. This counter is reset to count011. ltthen counts up to 111 in a binary fashion and then transitions to 011 producing 5 unique states.
Figure 9 contains the SNAP listing of another modification. This 12-bit counter was part of a design that already was using all ten of the JKPR552 flip-flops and two of the JKCL552 resources. For this case 8 of the JKCL552 flip-flops were configured as described above, the remaining four bits used D-type flip-flops realized using only FBNAND gates. An additional design technique was implemented with these D-type flip-flops.
Normally when making a counter using D-type flip-flops, the flip-flops are preceded by some AND-OR logic. In this case, since the flip-flops are constructed using only FBNAND gates, it was possible to merge the AND-OR logic structure directly into the construction of the flip-flop. For additional information on flip-flop merging, please refer to application note AN049.
CONCLUSION
Counters of up to 10-bits may be implemented in PML2552 and PML2852 devices using only one FBNAND gate and the JKCL552 group of flip-flops. The design presented may be altered to provide a count of any value. If more than 10-bits are required, it is possible to add flip-flops from the JKPR552 group, the ODFF group, or construct flip-flops from FBNAND gates.

October 1993

845

Philips Semiconductors Programmable Logic Devices
Implementing counters in PML2X52 devices

Application Note
AN042

~ AL;J a' 8 BFCx

8

BO- 7

ClK/DAA:,>_-~-8'77'~CL-~-iB1>FDA(x9)UQ tt'-----+l~+l-r----+-+--t-------+-+l-f------+-<t----------------+1-r-+----+----t--1--f+--1------+++-----+++------t++---------++lf------+----ljl---~---;-ll~ff1----~C~-8--~

l/DBl>--7'rL-.-JQl-~~-l······f-······-······_)-+---+---+------lf----t---l--+-+--l----lf----l---ll-

1
-l----1--l----1-----+---+---+--+---t--+--+--:::ji)ii',15Si1:
--1---1---1---t-----+---+---+--+--+--+---+-- aMNm
--~'.::.::~:::~'.::.::~::::::::~'.::.::~:::~'.::.::~::~::-=:,~::~'.::.:=i~~i.~
l/CKB/C>KC-+---;..<---=-i~r1-l····--1---t-----+--+---+--+--t--+---+---+:--~-~ +--

1/08-1/015 1/00-1/07

llCK1J>-t-....:3_._,,___=.i iiB·1---+--t------+--+---+--+--1---+--+--+--+-

~:.~.m 10 10 1 8=&1'58 52

K

J

D BFB

D

,;;;

CK1 (10) PR
u a JK1iRss~

(8)

(8)

""

ro = a =

-----~

l

CKE1

CKE2

~j!~i------+----lf----

:N:)KllJN552::------+----lf----

~

1r1~·- - - 1 - - -

.·...........·..·..·..

./

O - - ..D rr--~ <fil

Figure 1. PML2552 Logic Diagram

October 1993

846

Philips Semiconductors Programmable Logic Devices
Implementing counters in PML2X52 devices

"8-bit up counter"
" ----------------"
"constructed as a down counter with inverted outputs"

@PINLIST

clr i; elk i;

q[7 .. O]

o;

@GROUPS

@TRUTHTABLE

@LOGIC EQUATIONS

qi[7 .. 0].clk = elk;

"common clock"

qi[7 .. 0].set = /clr;

"conanon clear"

qO=/qiO q3=/qi3 q6=/qi6

ql=/qil; q4=/qi4; q7=/qi7;

q2=/qi2; "invert outputs to" qS=/qiS; "make an up counter"

qiO. j = l; qiO.k = l; qil. j = /qiO; qil.k /qiO; qi2.j /qiO*/qil; qi2.k /qiO*/qil; qi3.j /qi0*/qil*/qi2; qi3.k /qi0*/qil*/qi2; qi4.j /qi0*/qil*/qi2*/qi3; qi4.k /qi0*/qil*/qi2*/qi3; qiS.j /q10*/qil*/qi2*/qi3*/qi4; q15.k /qi0*/qil*/q12*/qi3*/qi4; qi6.j /qi0*/qil*/qi2*/qi3*/q14*/qi5; qi6.k /q10*/qil*/q12*/qi3*/qi4*/qi5; q17.j /qi0*/qil*/qi2*/qi3*/qi4*/qi5*/qi6; q17.k /q10*/qil*/qi2*/qi3*/qi4*/q15*/qi6;

@INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANSITIONS

Figure 2. Typical B·Bit Binary Counter

Application Note
AN042

October 1993

847

Philips Semiconductors Programmable Logic Devices
Implementing counters in PML2X52 devices

Application Note
AN042

U7

vcc
U1 JKFFR

03 02 01

00 0

0 0

1

01 0

01 1

1 0

0

1 0

1

11 0

1 1

1

U4 JKFFR
CP
K R 4
Figure 3. 3-Blt Binary Counter (modulo-8)

File: CTBPML.RES DELAY= Ons (Netlist)

CLOCK L

RESET L

01 u

02 u

03 u

*#CHECK u

u
L

Marker = Ons

Sec/Div = 200ns

200

600

1000

Philips S8Dli.conductors (C) 1993 MODE = 1

1400

1800

2200

Fl : HELP, FlO : EXIT

Figure 4. SNAP Simulation Waveforms of 3-Bit Binary Counter

October 1993

848

Philips Semiconductors Programmable Logic Devices
Implementing counters in PML2X52 devices

Application Note
AN042

"Ten bit counter using only HAND gates in clock array of JK flip-flops with reset in PML2552 or PML2852"

@PINLIST

clr

i;

elk

i;

q[9 .. OJ o;

@GROUPS

@TRUTHTABLE

@LOGIC EQUATIONS

qiO.clk elk;

"JKCL552 flip-flops have"

qil.clk /(qiO*/clk);

"an independent clock

qi2.clk /(qiO*qil*/clk);

"HAND array

qi3.clk /(qiO*qil*qi2*/clk);

qi4.clk /(qi0*qil*qi2*qi3*/clk);

"clock on rising edge of elk"

qi5.clk /(qiO*qil*qi2*qi3*qi4*/clk);

qi6.clk /(qi0*qil*qi2*qi3*qi4*qi5*/clk);

qi7.clk /(qiO*qil*qi2*qi3*qi4*qi5*qi6*/clk);

qi8.clk /(q10*qil*q12*qi3*q14*qi5*qi6*qi7*/clk);

qi9.clk /(qiO*qil*qi2*qi3*qi4*qi5*qi6*q17*qi8*/clk);

qiO.rst qi3.rst qi6.rst qi9.rst

/clr; qil.rst /clr; qi4.rst /clr; qi7.rst /clr;

/clr; qi2.rst /clr; qi5.rst /clr; qi8 .rst

/clr; /clr; /clr;

"define reset so SNAP" "will use .JXCL552 devices"

qO=qiO; ql=qil; q2=qi2; q3=q13; q4=qi4; q5=q15; q6=qi6; q7=qi7; q8=qi8; q9=qi9;

qi[9 .. O] .j l; qi[9 ·. 0].k = l;

"tie J and K inputs HIGH"

Figure 5. SNAP Equations for a 10-Blt Counter

Design from CT256PML.N2 - for device PML2552

Cell name used/total

%

========================================

CKDIN552

0I 4

0%

CKNIN552

1 I 4 25%

FBNAND

1 I 96

1%

HAND 51 I 104 49%

DIN552

1 I 25

4%

NIN552

0 I 25

0%

CDIN552

0I 4

0%

CNIN552

0I 4

0%

CK552

0I 4

0%

IDFF552

0 I 16

0%

BDIN552

0 I 24

0%

BNIN552

0 I 24

0%

JKCL552 10 I 10 100%

JKPR552

0 I 10

0%

EXOR552

8 I 8 100%

TOUT552

10 I 24

41%

ODFF552

2 I 16 12%

Figure 6. SNAP Resource Summary

October 1993

849

Philips Semiconductors Programmable Logic Devices
Implementing counters in PML2X52 devices

Application Note
AN042

>> Print out of fusemap starting from col l to col 18 <<

IIIIMMMMJJJJJJJJJJ

I I I /AAAAKKllKKKIOO< CCCCIIIICCCCCCCCCC

KKKKNNllNLLLLLLLLLL

B ( ( ( 0123456789

/l23CCCC
C)) ) KKKK=QQQ,,.,,-,QQ=-QQ""'QQQ=

__ (( (( 1111111111

22220123111 I I I I I I I

4320)))) 11111 11111

111111111111111111

1111 11111111111111

vvvvvvvvvvvvvvv

VKPR CK->

.·.........·..

JKCLO-CK-> ---L ....· AAAAAAAAA

JKCLl-CK-> ---L ...... AAAAAAAA

JKCL2-CK-> ---L ....... AAAAAAA

JKCL3-CK-> ---L ........ AAAAAA

JKCL4-CK-> ---L ......... AAAAA

JKCLS-CK-> ---L .......... AAAA

JKCL6-CK-> ---L ........... AAA JKCL7-CK-> ---L ............ AA

JKCL8-CK-> ---L ............. A

JKCL9-CK-> ---L ............. .

Figure 7. Portion of PML2552 Fuse Table Showing Clock Array Connections

October 1993

850

Philips Semiconductors Programmable Logic Devices
Implementing counters in PML2X52 devices

Application Note
AN042

vcc

u1
JKFFR

J

Q

CP

K R ON

oa 02 Ql

0 1

1

1 0

0

1 0

1

1 1

0

1 1

1

U4 JKFFR
Q
CP
4
U8 4
NA3
Figure Ba. Modulo·S Counter

File: CTSPML.RES DELAY = Ons (Netlist)

Marker = Ons

us
JKFFR Q
CP K R ON
Sec/Div = 200ns

03 u *#CHECK U

I
u
L.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~-11

200

600

1000

= Philips Semiconductors (C) 1993 MODE l

1400

1800

2200

Fl : HELP, FlO : EXIT

Figure 8b. SNAP Simulation Waveforms of Modulo·S Counter

October 1993

851

Philips Semiconductors Programmable Logic Devices
Implementing counters in PML2X52 devices

Application Note
AN042

" This example is a 12-bit binary up counter. J:t is constructed using 8 JKCLS52 flip-flops and 4 D-type flip-flops constructed from FBHAND gates.

@PJ:HLJ:ST

clr

i;

olkn

i;

q[ll ·· O] o;

@GROtJPS

@TRUTHTABLE

@LOGJ:C EQUATIONS

= qiO.clk
qil.clk

/clkn; /(qiO*clkn);

"clock on falling edge of clkn"

= qi2.clk · /(qiO*qil*clkn);
qi3.clk /(qiO*qil*qi2*clkn);

qi4.clk /(qiO*qil*qi2*qi3*clkn);

qi5.clk /(qiO*qil*qi2*qi3*qi4*clkn);

qi6.clk /(qiO*qil*qi2*qi3*qi4*qi5*clkn);

qi7.clk /(qiO*qil*qi2*qi3*qi4*qi5*qi6*clkn);

qiO.rst
qi3.rat qi6.rst qi9.rst

= /clr; qil.rat = /clr; qi2.rst = /clr;
/clr; qi4.rat = /clr; qi5.rst /clr;
/clr; qi7.rst = /clr; qiB.rst = /clr; /clr; qilO.rst m /clr; qill.rst /clr;

"define reset.inputs"

qO=qiO; ql=qil; q2=qi2; q3=qi3; q4=qi4; q5=qi5; q6=qi6; q7=qi7;

q8=qi8; q9=qi9; qlO=qilO; qll=qill;

qi (7 ·· O] . j = l; qi[7 .. 0].k = l;

"all J and K inputs are tied HJ:GH"

"Four bit D-type flop counter clocked from output of qi7"

qi8 =/(qi8n*f8sn);
qi8n =/(qi8*f8rn*/clr);
f8sn =/(f8snn*/qi7*/clr); f8snn=/(f8sn*f8rnn);
f8rn =/(f8rnn*f8sn*/qi7); f8rnn=/(f8rn*qi8n*/clr);

"LSB" "qiB.d /qiB;"

qi9 =/(qi9n*f9sn);

"LMSB"

qi9n =/(qi9*f9rn*/clr);

f9an =/(f9snn*/qi7*/clr);

f9snn=/(f9sn*f9rnna*f9rnnb);

f9rn =/(f9rnna*f9rnnb*f9sn*/qi7); "merge llN!l/OR into flop"

f9rnna=/(f9rn*/clr*qi8n*qi9);

"qi9.d = /qi8*qi9+qi8*/qi9;"

f9rnnb=/(f9rn*/clr*qi8*qi9n);

qilO =/(qilOn*flOsn);

"UMSB"

qilOn =/(qilO*flOrn*/clr);

flOsn =/(fl0snn*/qi7*/clr);

flOsnn=/(flOsn*flOrnna*flOrnnb*flOrnnc);

flOrn =/(fl0rnna*fl0rnnb*fl0rnnc*fl0sn*/qi7); "merge llN!l/OR into flop"

flOrnna=/(flOrn*/clr*qiBn*qilO); "qilO.d=/qi8*qilO+/qi9*qilO+qi8*qi9*/qil0;"

fl0rnnb=/(fl0rn*/clr*qi9n*qil0);

fl0rnnc=/(fl0rn*/clr*qi8*qi9*qil0n);

qill =/(qilln*fllan);

"MSB"

qilln =/(qill*fllrn*/clr);

fllsn =/(fllsnn*/qi7*/clr);

fllsnn=/(fllsn*fllrnna*fllrnnb*fllrnnc*fllrnnd);

fllrn =/(fllrnna*fllrnnb*fllrnnc*fllrnnd*fllsn*/qi7);

"merge AND/OR into flop"

"qill.d=/qiB*qill+/qi9*qill+/qlO*qill+qi8*qi9*qilO*/qill;"

fllrnna=/(fllrn*/clr*qi8n*qill);

·

fllrnnb=/(fllrn*/clr*qi9n*qill);

fllrnnc=/(fllrn*/clr*qilOn*qill);

fllrnnd=/(fllrn*/clr*qi8*qi9*qilO*qilln);

@INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANSJ:TJ:ONS

Figure 9. 12-Bll Counter

October 1993

852

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

Authors: Uwe Kruger and Jurgen Meixner

INTRODUCTION
Serial digital data encoding and decoding protocols are often used to increase the
reliability of data transmission and storage. Transmitting digital data permits reliable error detection and correction techniques to be applied. Some encoding formats allow the transmitting clock to be extracted from the data stream and reproduced at the receiver. Long sequences of binary Os or 1s may be transparently limited using formats such as HDBn or Manchester.
Encoded serial signals are used, for instance, on the SO-bus in ISDN user interfaces (inverse AMI) and in PCM systems (HDB3 encoding).
This application note describes circuits that can encoder and decode eight of the most frequently used formats. A programmable logic device, the Philips PML2552, was used to implement the encoder. Another PML2552 was used to implement the decoder function. Three inputs on both devices permit selection of the desired encoding or decoding method.

The decoder will flag transmitting errors based upon the specific coding rules of each format. This design is part of a testing device tor cables and encoded serial data signals.
Serial Encoding Formats
This is a short explanation of the eight implemented codes:
AMI-Code: (alternate mark inversion) A binary 1 is transmitted alternating as a high mark (+1, positive voltage level) and as a low mark (-1, negative voltage level), a binary 0 appears as space (0 Volt).
HDBn-Code: (high density bipolar n) after n spaces will be included a code violation, i.e. the following "O" is transmitted as high mark or low mark depending on previous "1": Was it sent as a high mark, the violation will be also a high mark. So a binary 0 is

turned into a "wrong" mark that can be recognized and corrected by the receiver. A binary 1 after these n spaces will be sent as the alternating mark.
IAMl-Code: (inverse AMI) same as AMI code, but binary 0 and 1 are swapped.
RZ-Code: (return-to-zero), a binary 1 is transmitted as high mark returning to space after the half step time.
NRZ-Code: (non-return-to-zero), it's the same as the input of the coder, here will be amplified the signal amplitude only.
Manchester - Code: binary 1 is transmitted as transition between high mark and low mark, binary 0 switches from low mark to high mark. This code is free of any direct voltage, but requires the double bandwidth.

October 19\)3

853

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

binary sequence
clock
+1 AMI
-1 +1 HDB1 -1 +1 HDB2 -1 +1 HDB3 -1 +1 IAMI -1 +1 RZ 0 +1 NRZ 0 +1 MANCHESTER -1
Figure 1. Timing Diagrams of Implemented Serial Encoding Methods

October 1993

854

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

ENCODER
Realizing the Encoder Using a PML2552
Description of Encoder Facilities The encoder is designed as a Moore-type finite state machine. This structure of state machine ensures the output signals transition synchronously with the clock. Using a clock generated from a quartz oscillator, the data link can be provided on only one line. however, in this case the receiver must have extra circuitry such as a phase locked loop to extract the clock from the incoming data stream. The receiver must also be able to

synchronize itself to the transmitter when the transmitter sends a special data pattern.
Three additional pins are implemented in this design: Single and double bit clock (CP und CP2) and a signal for synchronization (/SYNC) of external devices. These pins are used in the testing device to trigger an oscilloscope and a pattern generator.
To make a bipolar signal, the outputs Y[2, 1] of the encoder must be connected with a subtractor realized with an OP-AMP. A schematic of the complete encoder circuit is shown in Figure 15. The following table shows dependencies between the encoder output and the output of the subtracter:

Lowmark Space Highmark

Y[2,1]

10

()()

01

To run the encoder, pin CP4 should be connected to an oscillator running at quadruple the bit clock. After resetting by a LOW pulse on RESET, the encoder generates the synchronizing signal (SYNC). Outputs Y[2, 1] are valid upon the falling edges of the clock (CP) after the /SYNC pulse. Refer to Figure 6 for timing information.
Code will be chosen by a binary combination on pins S[2..O]:

Code

AMI

HDB1

HDB2

HDB3

IAMI

RZ

NAZ

Manch.

S[2..0)

000

001

010

011

100

101

110

111

/Sync

S2 S1 SO

r---------------- -----

----,

1

I

I

I

I

I

synchronizer

I

I

Y2

I

/Reset[]- - I'- - - - - - .;_ - - - - - - - - - - - - - - - - - - - - - -
I

Coder

Y1

I

L -

I

I

clock

divider

4Cp

L----------------

Cp 2Cp

X

Figure 2. General Structure of Coder Unit

October 1993

855

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

Structure of Encoder State Machine The finite state machine implementing the encoder has a total of nineteen states. Due to the complexity of a complete state diagram, and the size of this page, only a partial state diagram is shown in Figure 3. The state diagram of Figure 3 shows the encoding technique for the Alternate Mark Inversion

(AMI) format. Operation of the complete state machine may be analyzed by studying the @TRANSITIONS section in the CODER.EON-file shown in Figure 5.
Structure of Synchronizer State Machine The synchronizer was also realized as a Moore machine. A state diagram is shown in

Figure 4. RESET initializes the state machine to State 0. After four clock pulses, the machine will be in State 4 and output SYNC is forced LOW. SYNC stays LOW for one more clock pulse, while in State 5, and returns HIGH when in State 6. The state machine will stay in State 6 until another RESET occurs.

0

Figure 3. State Diagram of AMI Encoding Technique

October 1993

Figure 4. State Diagram of Synchronizer 856

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

Usllng of Descriptive Fiia CODER.EQN

@PIHLIST

so

i; al

i; s2

i;

x

i;

cp4

i;

reset i;

yl

o; y2

o;

sync o;

cp2

o; cp

o;

@GROUPS @TRUTBTABLB @LOGIC BQUATIOllS sy_r ·/(/reset * cp4 * ztl);
= = ztl.clk cp4; ztl.j /ztl; ztl.k ztl; ztl.rst = = = zt2.clk ztl; zt2.j /zt2; zt2.k zt2; zt2.rat

/((ztl+zt2)*/reaat); /((ztl+zt2)*/reaet);

cp2 = ztl; cp = zt2;
= zsl.clk = cp4; zs2.clk = cp4; zs3.clk cp4;
zsl.rat sy_r; za2.rst = sy_r; zs3.rst = sy_r;
= = = zz4.clk ztl; zz3.clk = ztl; zz2.clk ztl; zzl.clk = ztl; zzO.clk ztl;
zz4.rst = sy_r; zz3.rat = sy_r; zz2.rat · ay_r; zzl.rst · sy_r; zzO.rat = sy_r;

@DIPUT VECTORS [s2, al, aO] ami 000 B; hdbl iami · 100 B; rz

001 B; hdb2 101 B; nrz

010 B; hdb3 110 B; man

011 B; 111 B;

= = [x]
xO 0 B; xl 1 B;

@OU!lPUT VECTORS
= [y2, yl]
higbm 01 B; null

= 00 B; lowm lOB;

= [sync]
sy 0 B; nay = 1 B;

@STATE VECTORS [zz4, zz3, zz2, zzl, zzO] jkffr zO 00000 B; zl = 00001 B; z2 z4 00100 B; zS 00101 B; z6 zB = 01000 B; z9 01001 B; zlO zl2 = 01100 B; zl3 01101 B; zl4 zl6 · 10000 B; zl7 10001 B; zlB

00010 B; z3 00011 B; 00110 B; z7 00111 B;
= 01010 B; zll 01011 B;
01110 B; zlS 01111 B; 10010 B;

[zs3, zs2, zal] jkffr
syO = 000 B; syl = 001 B; sy2 sy4 = 100 B; sys = 101 B; sy6

010 B; sy3 = 011 B; 110 B;

@TRANSITIONS while[zO] with[null)
if[) then[zl] while[zl] with[null]
if[) then[z2] while[z2] with[null]
if[(iami*xl)+((ami+hdbl+hdb2+hdb3)*x0)] if[man*xO] if [ (man+nrz) *xl] if[(iami*xO)+((ami+rz+hdbl+hdb2+hdb3)*xl)) if [ (nrz+rz) *xO] while[z3] with[highm]
if[((man+iami)*x0)+((ami+hdbl+hdb2+hdb3)*xl)] if[man*xl] if[nrz] if[((ami+hdbl+hdb2+hdb3)*x0)+(iami*xl)) while[z4] with[lowm] if[ami+hdbl+hdb2+hdb3+iami] if[man*xO]

then[zS] then[z4] then[z3] than[zl2] then[zl3]
then[z4) than[zll] than[zl2) than[zl3)
than[zll) than[zl2)

Figura 5. Description Fiia CODER.EQN (1 of 2)

October 1993

857

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

while[z5] with[null] if[ami+hdbl+hdb2+hdb3+iami]
while[z6] with[null] if[(hdb2+hdb3)*x0] if[hdbl*xO] if[(ami*xO)+(iami*xl)J if[((ami+hdbl+hdb2+hdb3)*xl)+(iami*x0)]
while[z7] with[null] if[]
while[z8] with[null] if[hdb3*x0] if[hdb2*x0] if[ (hdb2+hdb3) *xl]
wh1le[z9] with[null] if[]
while[zlO] with[null] if[hdb3*x0] if[hdb3*xl]
while[zll] with[lowm] if[((ami+hdbl+hdb2+hdb3)*xO)+(iami*xl)] if[man*xO] if[man*xl] if[((ami+hdbl+hdb2+hdb3)*xl)+(iami*x0)]
wh1le[zl2] with[highm] if[man*xO] if[rz+(nrz*xO)]
if[ami+hdbl+hdb2+hdb3+iami+((nrz+man)*xl)J while[zl3] with[null]
if[rz*xO] if[rz*xl] if[ami+hdbl+hdb2+hdb3+iami+nrz] while[zl4] with[null]
if[((ami+hdbl+hdb2+hdb3)*xl)+(iami*x0)] if[nrz*xl] if[hdbl*xO] if [ (hdb2+hdb3) *xO] while[zl5] with[null] if[] while[zl6] with[null] if(hdb2*x0] if[(hdb2+hdb3)*xl] if[hdb3*x0] while[zl7] with[null] if[] while[zl8] with[null] if [hdb3*x0] if[hdb3*xl]
while(syO] with [nay] if[] then[ayl] while(syl] with [nay] if[] then[ay2] while [sy2] with[nay] if[] then[ay3] while [ay3] with [nay] if [] then[ay4] while[sy4] with[ay] if[] then[ayS] while[ayS] with[ay] if[] then[sy6] while [sy6] with[nay] if[] then[ay6]

then[z6]
then[z7] then[z4] then[z5] then[zl2]
then[zB]
then[z9] then[z4] then[zl2]
then[zlO]
then[z4] then(zl2]
then[z5] then[z4] then[z3] then[zl2]
then[z4] then[zl3] then[z3]
then[zl3] then[zl2] then[zl4]
then[z4] then[z3] then[zl2] then[zlSJ
then[zl6]
then[zl2] then[z4] then[zl7]
then[zl8]
then[zl2] then[z4]

Figure 5. Description Fiie CODER.EQN (2 of 2)

October 1993

858

Philips Semiconductors Programmable logic Devices
Serial data encoder and decoder

Timing simulation
llmlng Diagram of Synchronizer

x

2

Y1

3

Y2

4

CP4

5

CP2

6

CP

7

RESET

8

SYNC

Figure 6. Timing Diagram of Generating the /SYNC Signal

Application Note
AN041

October 1993

859

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

Ustlngs of Stlmull Flies for Timing Slmulatlon Using LESIM

*******~*******************************~***********

*

Output of Waveform Version 1.90

*

* Date: 07/19/93

Time: 09:56:50 *

***************************************************

** Input File Name * Rule File Name * Output File Name

AMJ:.SCL Scl Rule AMJ:.SCL

* * * *

*

*

**·*************************************************

P S[2 ·· 0], X, Clt2, Yl, Y2, ZZ[4 .· 0], RESET

PCO

s 0 (200000) so

S 0 (200000) Sl

S 0 (200000) S2
s 0 (20500, 24500, 28500, 36500, 52500, 64500, 104500, 112500, 116500,
# 120500, 124500, 128500) x

S 0 (1000, 2000, ETC) CK2

S 1 (100, 200) RESET

SU time = 200000

F

Figure 7. Stimulus File AMl.SCL, Control Word On Inputs 5(2··0]= 0008

***************************************************

Output of Waveform Version 1.90

* Date: 07/19/93

Time: 09:56:50 *

***************************************************

** Input File Name * Rule File Name * Output File Name

HDBl.SCL Scl Rule HDBl.SCL

* * * *

*

*

***************************************************

P S[2 .. 0], X, CK2, Yl, Y2, ZZ[4 .. 0], RESET

PCO

s 1 (200000) so

S 0 (200000) Sl

S 0 (200000) S2
s 0 (20500, 24500, 28500, 36500, 52500, 64500, 104500, 112500, 116500,

# 120500, 124500, 128500) x

S 0 (1000, 2000, ETC) CK2

S 1 (100, 200) RESET

SU time = 200000

F

Figure 8. Stimulus File HDB1 .SCL, Control Word On Inputs 5(2··0]= 001 B

October 1993

860

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

*

output of Waveform Version 1.90

*

* Date: 07/19/93

Ti.ma: 09:56:50 *

***************************************************

** Input File Name * Rule File Name
* output File Name

BDB2.SCL Scl Rule BDB2.SCL

* * * *

*

*

***************************************************

P S[2 ·· 0], X, CK2, Yl, Y2, ZZ[4 ·. 0], RESET

PCO
s 0 (200000) so

S 1 (200000) Sl

S 0 (200000) S2

s 0 (20500, 24500, 28500, 36500, 52500, 64500, 104500, 112500, 116500,
# 120500, 124500, 128500) x

S 0 (1000, 2000, ETC) CK2

S 1 (100, 200) RESET
so ti.ma = 200000

F

Figure 9. Stimulus File HDB2.SCL, Control Word On Inputs S[2··0] =010 B

*******O**U*t*p*u*t**o*f**W*a*v*e*f*o*rm***V*e*r*s*io**n**l.*9*0****************

* Date: 07/19/93

Time: 09:56:50 *

***************************************************

** Input File Name * Rule File Name

BDB3.SCL Scl Rule

.**.

* OUtput File Name BDB3.SCL

*

*

*

***************************************************

P S[2 ·· 0], X, CK2, Yl, Y2, ZZ[4 ·. 0], RESET

PCO
s 1 (200000) so

S l (200000) Sl

S 0 (200000) S2

s 0 (20500, 24500, 28500, 36500, 52500, 64500, 104500, 112500, 116500,
# 120500, 124500, 128500) x

S 0 (1000, 2000, ETC) CK2

= S l (100, 200) RESET
so time 200000

F

Figure 10. Stimulus File HDB3.SCL, Control Word On Inputs S[2··0] =011 B

October 1993

861

Philips Semiconductors Programmable Logic Devices .
Serial data encoder and decoder

Application Note
AN041

*

output of Waveform Version 1. 90

*

* Date: 07/19/93

Time: 09:56:50 *

***************************************************

** Input File Nama * Rule File Name
* output File Name

INV AMI.SCL
Sol-Rule
IHV_AMI. SCL

* * * *

*

*

***************************************************

P S[2 ·· 0]. X, CK2, Yl, Y2, ZZ[4 .· 0], RESET

PCO

s 0 (200000) so

S 0 (200000) Sl

S 1 (200000) S2
s 0 (20500, 24500, 28500, 36500, 52500, 64500, 104500, 112500, 116500, # 120500, 124500, 128500) x

S 0 (1000, 2000, ETC) CK2

= S 1 (100, 200) RESET
SU time 200000

F

Figure 11. Stimulus Fiie INV AMl.SCL, Control Word On Inputs 5[2.·0] =100 B

***************************************************

*

OUtput of Waveform Version 1.90

*

* Date: 07/19/93

Time: 09:56:50 *

**************************************,*************

** Input File Name * Rule File Nama * OUtput File Name

RZ.SCL Sol Rule RZ.SCL

* * * *

*****************************************************

P S[2 ·. 0], X, CK2, Yl, Y2, ZZ[4 .. 0], RESET

PCO

s 1 (200000) so

S 0 (200000) Sl

S 1 (200000) S2
s 0 (20500, 24500, 28500, 36500, 52500, 64500, 104500, 112500, 116500, # 120500, 124500, 128500) x

S 0 (1000, 2000, ETC) CK2

S 1 (100, 200) RESET

SU time = 200000

F

Figure 12. Stimulus File RZ.SCL, Control Word On Inputs 5[2..0] =101 B

October 1993

862

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

*

output of Waveform Version 1.90

*

* Date: 07/19/93

Time: 09:56:50 *

***************************************************

** Input File Name * Rule File Name * output File Name

HRZ.SCL Scl Rule HRZ.SCL

* * * *

*

*

***************************************************

P S[2 .. 0], X, CK2, Yl, Y2, ZZ[4 ·. 0], RESET

PCO

s 0 (200000) so

S l (200000) Sl

S 1 (200000) S2

s 0 (20500, 24500, 28500, 36500, 52500, 64500, 104500, 112500, 116500,

# 120500, 124500, 128500) x

S 0 (1000, 2000, ETC) CK2

S 1 (100, 200) RESET
SU time = 200000

F

= F!!!_ure 13. Stimulus File NRZ.SCL, Control Word On l~ts ~--~ 110 B

***************************************************

*

OUtput of Waveform Version 1.90

*

* Date: 07/19/93

Time: 09:56:50 *

***************************************************

** Input File Name
* Rule File Name

MAHCHEST.SCL Scl Rule

* *

* OUtput File Name MAHCHEST.SCL

*

*****************************************************

P S[2 .. 0], X, CK2, Yl, Y2, ZZ[4 .· 0], RESET

PCO

s l (200000) so

S 1 (200000) Sl

S l (200000) S2
s 0 (20500, 24500, 28500, 36500, 52500, 64500, 104500, 112500, 116500,
· 120500, 124500, 128500) x

S 0 (1000, 2000, ETC) CK2

S 1 (100, 200) RESET

SU time = 200000

F

Figure 14. Stimulus File MANCHEST.SCL, Control Word On Inputs S[2··0] = 111 B

October 1993

863

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder
Wiring of the Encoder

Application Note
AN041

Figure 15. Wiring of Encoder Unit

DECODER
Realizing the Decoder Using a PML2552
Description of Decoder The decoding unit is also realized as a Moore machine. The capability to recognize transmission errors can also be implemented as a state machine. So, actually, the decoding and error detection functions are combined and written as one state machine.

The SNAP state equations for lhe decoder and error detection functions are shown in Figure 18.
Pin 2CP of the decoder must be connected to a double bit clock. Reselling the decoder brings it in lhe initial state. It is necessary to convert lhe incoming bipolar sequence into two digital signals to be applied to the two decoder inputs. This splitter is made in the testing device by two voltage comparators as

shown in Figure 18. Synchronized by a LOW pulse on the SYNC input, lhe decoder converts the serially encoded sequence into binary information on output Y.

Lowmark Space Hlghmark

Y[2,1)

10

00

01

Code will be chosen by a binary combination on pins S[2..OJ:

Code

AMI

HDB1

HDB2

HDB3

IAMI

RZ

NRZ

Manch.

S[2 ·· 0)

000

001

010

011

100

101

110

111

r------------,

I

I

S2 +--+--I

I I

S1

I

so

I
1-1---10v

I

X2

Decoder

I

X1

:I -1---D Error

2Cp

I

/Sync

I I

/Reset

I

LI ------------JI

Figure 16. General Structure of Decoder

October 1993

864

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

If an error should occur, the decoder will set output ERROR to a HIGH. Output Y will remain LOW until a reset and synchronization cycle begins. Using this facility, a layer II of the OSI stack can be controlled by the decoder unit and the decoder can get its RESET and SYNC inputs from layer II.

Structure of Decoders State Machine The state diagram shown in Figure 17 shows only the AMI portion of the decoder. For detailed information on the operation of the decoder for other formats, refer to the @TRANSISTIONS section of the SNAP state equation listing shown in Figure 18.

Application Note
AN041

0

0

Figure 17. State Diagram of AMI Decoder

October 1993

865

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Listing of Description File DECODER.EQN

@PINLIST

so

i; sl

i; s2

i;

xl

i· x2

i;

ck2

i;

reset i;

sync i;

y

o;

f

o;

@GROUPS

@TRUTHTABLE

@LOGIC EQUATIONS

zz5.clk zz2.clk

ck2; ck2;

zz4.clk zzl.clk

= =

ck2; ck2;

zz3.clk zzO.clk

= =

ck2; ck2;

zzS.rst = reset; zz4.set reset; zz3.rst reset;

zz2.rst = reset; zzl.rst =reset; zzO.rst = reset;

@INPUT VECTORS [s2, sl, sO] ami = 000 B; hdbl
iami = 100 B; rz

001 B; hdb2 101 B; nrz

010 B; hdb3 110 B; man

011 B; 111 B;

[x2, xl]
highm = 11 B; lowm = 00 B; spc = 10 B;

[sync]
sy = 1 B; nsy = 0 B;

@OUTPUT VECTORS [y, f]
= = high 10 B; low = 00 B; err 01 B;

@STATE VECTORS
[zzS, zz4, zz3, zz2, zzl, zzO] jkffsr zO 010000 B; zl 000010 B; z2 100000 B z3 z4 000100 B; z5 000101 B; z6 001011 B z7 z8 010010 B; z9 010001 B; zlO 000001 B zll z12 001000 B; z13 101000 B; z14 100101 B zl5 zl6 100011 B· zl7 100010 B; zl8 000000 B zl9 z20 100001 B· z2l 000110 B; z22 000111 B

000011 B
001001 B 110000 B 100100 B 101001 B

@TRANSITIONS
while[zO] with[low] if [sy]
if[nsy*((lowm*(ami+hdbl+hdb2+hdb3))+(highm*(rz+nrz+man)))] if[nsy*((spc*(hdbl+hdb2+hdb3))+(highm*iami)+(lowrn*man))] if[nsy*(spc*(ami+rz+nrz))] if[nsy*(hiqhm*(ami+hdbl+hdb2+hdb3))] if[nsy*lowm*iami] if[nsy*((lowm*(rz+nrz))+(spc*man))] while[zl] with[low]
if[spc*(ami+rz+nrz)] if[(lowm*ami)+(hiqhm*(rz+nrz+man))] if [lowm*man] if [hiqhm*ami] if[(lowm*(rz+nrz))+(spc*man)] while[z2] with[hiqh]
if[ami+hdbl+hdb2+hdb3+iami] while[z3] with[hiqh]
if[lowrn*(ami+hdbl+hdb2+hdb3)] if[(spc*(ami+hdbl+hdb2+hdb3))+(iami*lowm)] if[hiqhm*(ami+hdbl+hdb2+hdb3+iami)] if [spc*iami] while[z4] with[low] if[hdbl+hdb2+hdb3+iami] if[ami]

October 1993

Figure 18. Description File DECODER.EQN (1 of 2) 866

Application Note
AN041
then[zO] then[zlO] then[z12] then[zl] then[z2] then[z4] then[zl8] then[zl] then[zlO] then[zl2] then[z2] then[zl8] then[z3] then[zlO] then[z4] then[z18] then[z2] then[zS] then[zl]

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

while[z5] with[low] if[spc*(hdb2+hdb3)] if[(lowm*(hdbl+hdb2+hdb3))+(spc*iami)] if [hiqhm*iami] if [hiqhm*hdbl] if[(hiqhm*(hdb2+hdb3))+(1owm*iami)+(spc*hdbl)]
while[z6] with[low] if [hdb2+hdb3 J
while[z7] with[low] if [hiqhm*hdb2] if[lowm*(hdb2+hdb3)] if[(hiqhm*hdb3)+(spc*hdb2)] if[spc*hdb3]
while[z8] with[low] if [hdb3]
while[z9] with[low] if[spc*hdb3] if [hiqhm*hdb3] if [lowm*hdb3]
while[zlO] with[hiqh] if[man*(spc+hiqhm)] if[iami+ami+hdbl+hdb2+hdb3+rz+nrz+(man*lowm)J
while[zll] with[hiqh]
if[hiqhm*(ami+hdbl+hdb2+hdb3)] if[(hiqhm*(rz+nrz+man))+(spc*iami)] if[(spc*(ami+hdbl+hdb2+hdb3))+(hiqhm*iami)+(lowm*man)] if[spc*(rz+nrz)] if[(lowm*(iami+ami+hdbl+hdb2+hdb3+rz+nrz))+(spc*man)] while[z12] with[low] if[man*(spc+lowm)] if[(hiqhm*man)+ami] if[iami+hdbl+hdb2+hdb3] while[z13] with[low]
if[lowm*hdbl] if[spc*iami] if[hiqhm*(hdbl+hdb2+hdb3)] if[(hiqhm*iami)+(lowm*(hdb2+hdb3))+(hdbl*spc)] if [lowm*iami] if[spc*(hdb2+hdb3)] while[z14] with[low] if[hdb2+hdb3] while[zlS] with[low] if[spc*hdb3] if[hiqhm*(hdb2+hdb3)] if[(lowm*hdb3)+(spc*hdb2)] if[lowm*hdb2] while[z16] with[low] if[hdb3] while[z17] with[low] if[spc*hdb3] if [hiqhm*hdb3] if[lowm*hdb3] while[z18] with[err] if[] while[z19] with[low] if[hdbl+hdb2+hdb3] while[z20] with[low] if[lowm*(hdbl+hdb2+hdb3)] if[hiqhm*(hdbl+hdb2+hdb3)] if[spc*(hdbl+hdb2+hdb3)] while[z21] with[low] if [hdbl+hdb2+hdb3] while[z22] with[low]
if[lowm*(hdbl+hdb2+hdb3)] if[hiqhm*(hdbl+hdb2+hdb3)] if[spc*(hdbl+hdb2+hdb3)]

October 1993

Figure 18. Description File DECODER.EON (2 of 2) 867

then[z6] then[zlO] then[z12] then[z21] then[zl.8]
then[z7]
then[z2l.] then[zlOJ then[zl.8] then[z8]
then[z9]
then[zl.8] then[z21] then[zl.O]
then[zl.8] then[zl.l.]
then[z2] then[zl.O] then[zl.2] then[zl] then[zl.8]
then[zl.8] then[zl] then[zl3]
then[zl.9] then[z2] then[z2] then[zl8] then[z4] then[z14]
then[zl.5]
then[z16] then[z2] then[z18] then[zl.9]
then[zl7]
then[zl.8] then[z2] then[zl9]
then[zl.8]
then[z20]
then[zl.8] then[z2] then[zl.2]
then[z22]
then[zl.O] then[zl.8] then[z4]

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder
Timing simulation
Timing Diagram of Synchronizing Cycle

2

X2

3

CLK2

5

SYNC

6

RESET

Figure 19. Timing Diagram of Synchronizing Cycle

Application Note
AN041

October 1993

868

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

Listings of Stimulus Flies for Timing Simulation Using LESIM

***************************************************

*

Output of Waveform Version 1.90

*

* Date: 06/08/93

Time: 19:25:46 *

***************************************************

** Input File Name * Rule File Name * Output File Name

AMI.SCL Scl Rule AMJ:.SCL

* * * *

*****************************************************

P S[2 .· 0], Xl, X2, CK2, Y, ZZ[4 .· 0J, SYNC, RESET, F

PCO

s 0 (16500, 20500, 28500, 32500, 52500, 56500, 100500, 104500,

# 112500, 116500) Xl

s 1 (24500, 28500, 48500, 52500, 56500, 60500, 104500, 108500,

# 120500, 124500) X2

S 0 (300, 400) SYNC

S 1 (100, 200) RESET

S 0 (1000, 2000, ETC) CK2

S 0 (200000) S2

S 0 (200000) Sl
s 0 (200000) so SU time = 200000

F

= Figure 20. Stimulus File AMl.SCL, Control Word On Inputs S[2··0) 000 B

***************************************************

*

output of Waveform Version 1.90

*

* Date: 06/08/93

Time: 19:25:46 *

***************************************************

** Input File Name * Rule File Name * output File Name

HDBl.SCL Scl Rule HDBl.SCL

* * * *

*

*

***************************************************

P S[2 .. 0J, Xl, X2, CK2, Y, ZZ[4 .. 0], SYNC, RESET, F

PCO

s 0 (16500, 20500, 28500, 32500, 36500, 40500, 44500, 48500, 52500, 56500,

# 100500, 104500, 112500, 116500) Xl

s 1 (4500, 8500, 12500, 16500, 24500, 28500, 48500, 52500, 56500, 60500,

# 64500, 68500, 72500, 76500, 80500, 84500, 88500, 92500, 96500, 100500,

# 104500, 108500, 120500, 124500) X2

S 0 (300, 400) SYNC

S 1 (100, 200) RESET

S 0 (1000, 2000, ETC) CK2

S 0 (200000) S2

S 0 (200000) Sl
s 1 (200000) so SU time = 200000

F

= Figure 21. Stimulus File HDB1.SCL, Control Word On Inputs S[2··0) 001 B

October 1993

869

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

*

OUtput of Waveform Version 1.90

*

* Date: 06/08/93

Time: 19:25:46 *

***************************************************

** Input File Name * Rule File Name

HDB2.SCL Sol Rule

* *

* Output File Name HDB2.SCL

*

*

***************************************************

P S[2 .. 0], Xl, X2, CK2, Y, ZZ[4 .. 0], SYNC, RESET, F

PCO

s 0 (16500, 20500, 28500, 32500, 40500, 44500, 52500, 56500,

# 100500, 104500, 112500, 116500) Xl
s 1 (8500, 12500, 24500, 28500, 48500, 52500, 56500, 60500, 68500, # 72500, 80500, 84500, 92500, 96500, 104500, 108500, 120500, 124500) X2

S 0 (300, 400) SYNC

S 1 (100, 200) RESET

S 0 (1000, 2000, ETC) CK2

S 0 (200000) S2

S l (200000) Sl
s 0 (200000) so

SU time = 200000

F

= Figure 22. Stimulus File HDB2.SCL, Control Word On Inputs S[2..0] 010 B

***************************************************

*

output of Waveform Version 1.90

*

* Date: 06/08/93

Time: 19:25:46 *

***************************************************

* * Input File Name * Rule File Name

HDB3.SCL Sol Rule

* * *

* Output File Name HDB3.SCL

***************************************************
P S[2 .. 0], Xl, X2, CK2, Y, ZZ[4 .. O], SYNC, RESET, F
PCO
s 0 (16500, 20500, 28500, 32500, 44500, 48500, 52500,
# 100500, 104500, 112500, 116500) Xl
s 1 (12500, 16500, 24500, 28500, 48500, 52500, 56500,
# 76500, 88500, 92500, 104500, 108500, 120500, 124500)
S 0 (300, 400) SYNC s 1 (100, 200) RESET
s 0 (1000, 2000, ETC) CK2 s 0 (200000) S2
s 1 (200000) Sl
s 1 (200000) so
SU time = 200000
F

56500,
60500, X2

72500,

= Figure 23. Stimulus File HOB3.SCL, Control Word On Inputs S[2..0] 011 B

October 1993

870

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

*

OUtput of Waveform Version 1.90

*

* Date: 06/08/93

Time: 19:25:46 *

***************************************************

** Input File Name * Rule File Name * OUtput File Name

INV AMI.SCL Sol-Rule
INV_AMI. SCL

* * * *

*****************************************************

P S[2 ·. 0], Xl, X2, CK2, Y, ZZ[4 .. 0], SYNC, RESET, F

PCO
s 0 (500, 4500, 8500, 12500, 20500, 24500, 36500, 40500, 44500,

# 48500, 64500, 68500, 72500, 76500, 80500, 84500, 88500, 92500,

# 96500, 100500, 116500, 120500) Xl
s 1 (4500, 8500, 12500, 16500, 32500, 36500, 40500, 44500,

# 60500, 64500, 68500, 72500, 76500, 80500, 84500, 88500, 92500,

# 96500, 108500, 112500, 124500, 128500) X2

S 0 (300, 400) SYNC

S l (100, 200) RESET

S 0 (1000, 2000, ETC) CK2

S 1 (200000) S2

S 0 (200000) Sl
s 0 (200000) so

SU time = 200000

F

= Figure 24. Stimulus File INV_AMl.SCL, Control Word On Inputs S(2.·0) 100 B

***************************************************

*

output of Waveform Version 1.90

*

* Date: 07/19/93

Time: 16:01:57 *

***************************************************

** Input File Name * Rule File Name * OUtput File Name

RZ.SCL Scl Rule RZ.SCL

* * * *

*

*

***************************************************

P S[2 .. OJ. Xl, X2, CK2, Y, ZZ[4 .. 0], SYNC, RESET, F

PCO
s l (200000) S2 s 0 (200000) Sl s l (200000) so s 0 (16500, 18500, 24500, 26500, 28500, 30500, 48500, 50500, 52500,

# 54500, 56500, 58500, 100500, 102500, 104500, 106500, 112500, 114500,

# 120500, 122500) Xl

S 1 (200010) X2

S 0 (1000, 2000, ETC) CK2

S 0 (300, 400) SYNC

S 1 (100, 200) RESET

SU time = 200000

F

= Figure 25. Stimulus File RZ.SCL, Control Word On Inputs S[2··0) 101 B

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

*

output of Waveform Version 1.90

*

* Date: 07/19/93

Time: 16:01:57 *

***************************************************

* Input File Name

NRZ.SCL

* Rule File Name : Scl Rule

* OUtput File Name : NRZ.SCL

***************************************************

P S[2 .. 0], Xl, X2, CK2, Y, ZZ[4 .. 0], SYNC, RESET, F

PCO

S 1 (200000) S2

S 1 (200000) Sl
s 0 (200000) so s 0 (16500, 20500, 26500, 32500, 48500, 60500, 100500, 108500,

# 112500, 116500, 120500, 124500) Xl

S 1 (200010) X2

S 0 (1000, 2000, ETC) CK2

S 0 (300, 400) SYNC

S 1 (100, 200) RESET
SU time = 200000

F

= Figure 26. Stimulus File NRZ.SCL, Control Word On Inputs 5[2..0) 110 B

***************************************************

*

Output of Waveform Version 1.90

*

* Date: 07/19/93

Time: 16:01:57 *

****************************~**********************

* Input File Name

MANCl!EST.SCL

* Rule File Name : Scl Rule

* output File Name : MANCl!EST.SCL

* * *

***************************************************

P S[2 .. 0], Xl, X2, CK2, Y, ZZ[4 .. OJ, SYNC, RESET, F

PCO

S 1 (200000) S2

S 1 (200000) Sl

s 1 (200000) so

s 0 (2500, 4500, 6500, 8500, 10500, 12500, 14500, 18500, 22500,

# 26500, 28500, 30500, 34500, 36500, 38500, 40500, 42500, 44500,

# 46500, 50500, 52500, 54500, 56500, 58500, 62500, 64500, 66500,

# 68500, 70500, 72500, 74500, 76500, 78500, 80500, 82500, 84500,

# 86500, 88500, 90500, 92500, 94500, 96500, 98500, 102500, 104500,

# 106500, 110500, 114500, 118500, 122500, 126500, 128500) Xl

s 0 (2500, 4500, 6500, 8500, 10500, 12500, 14500, 18500, 22500,

# 26500, 28500, 30500, 34500, 36500, 38500, 40500, 42500, 44500,

# 46500, 50500, 52500, 54500, 56500, 58500, 62500, 64500, 66500,

# 68500, 70500, 72500, 74500, 76500, 78500, 80500, 82500, 84500,

# 86500, 88500, 90500, 92500, 94500, 96500, 98500, 102500, 104500,

# 106500, 110500, 114500, 118500, 122500, 126500, 128500) X2

S 0 (1000, 2000, ETC) CK2

S 0 (300, 400) SYNC

S 1 (100, 200) RESET
SU time = 200000

F

= Figure 27. Stimulus File MANCHEST.SCL, Control Word On Inputs S[2..0) 111 B

October 1993

872

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder
Wiring of the Decoder Unit

Application Note
AN041

PLD1 PML2552
SROESET
'---"'~S1 '---~~s2
SYNC '--+--"'-iX1
~-+--=-tX2
CK2

Y F Ir~~L--cC::Y=:::J

> GND

PIN 1 OF EACH LT1011 MUST BE CONNECTED WITH GND
Figure 28. Wiring of Decoder Unit

October 1993

873

Philips Semiconductors Programmable Logic Devices
Serial data encoder and decoder

Application Note
AN041

WIRING OF THE ENCODER AND DECODER UNITS FOR TESTING

~
S1 LI2...___.>
[INPUT
4CP [ /RESET
~ c
~

DECODER PMl..2552

~so 51 S2
f"" INPUT

2CP .. CP ..
OUTPUT . .
/SYNC =o

4CP !RESET
+Vee -Vee GND
CODER.SCH

DECODER PML2552

so S1 s2
2CP

INPUT /SYNC

·-y-.

y

ERROR~~

~/RESET
+Vee -Vee GND
DECODER.SCH

Figure 29. Wiring of the Encoder and Decoder Units for Testing

October 1993

874

Programmable Logic Devices

Section 12
Package Outlines

0400E 0401F 0397E 0398E 0399F 05848
05868
05898
1473A 1551 04080 0410D 04130 0864D 01720
0173D

20-Pin (350 mils wide) Plastic Leaded Chip Carrier (A) Package . . . . . . . . . . . 877
28-Pin (300 mils wide) Plastic Leaded Chip Carrier (A) Package . . . . . . . . . . . 878
52-Pin Plastic Leaded Chip Carrier (A) Package . . . . . . . . . . . . . . . . . . . . . . . . 879
68-Pin Plastic Leaded Chip Carrier (A) Package . . . . . . . . . . . . . . . . . . . . . . . . 880
84-Pin Plastic Leaded Chip Carrier (A) Package . . . . . . . . . . . . . . . . . . . . . . . . 881
20-Pin (300 mils wide) Ceramic Dual In-line (F) Package (with window (FA) Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
24-Pin (300 mils wide) Ceramic Dual In-line (Fl Package (with Window (FA) Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . . 883
28-Pin (600 mils wide) Ceramic Dual In-line (F) Package (with Window (FA) Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
68-Pin CerOuad J-Bend (K) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
84-Pin CerOuad J-Bend (K) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
20-Pin (300 mils wide) Plastic Dual In-Line (N) Package . . . . . . . . . . . . . . . . . . 887
24-Pin (300 mils wide) Plastic Dual In-Line (N) Package . . . . . . . . . . . . . . . . . . 888
28-Pin (600 mils wide) Plastic Dual In-Line (N) Package . . . . . . . . . . . . . . . . . . 889
28-Pin (300 mils wide) Plastic Dual In-Line (N) Package . . . . . . . . . . . . . . . . . . 890
20-Pin (300 mils wide) Plastic SOL (Small Outline Large) Dual In-Line (D) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
24-Pin (300 mils wide) Plastic SOL (Small Outline Large) Dual In-Line (D) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892

December 1993

~

§

I ~
.i.8.

m

11

§

o.395(10.031_1"__{$"lo.001co.181®I A@I F--O ®I 0.385 (9.78)

9 z"II

0.010 (0.25) MAX. R 3 PLACES
0.358 (9.04) 0.350 (8.89)

~

B@IC>-E®

NOTES

3

1. l?ackage dimensions conform to JEDEC Specification M0-047-AA

if

for Plastic Leaded Chip Carrier 20 leads, 0.050 inch (1.27mm) lead spacing, square. (Issue A, 10/31/84.)
2. Controlling dimensions: inches. Metric dimensions in mm are shown

i

0.048(1.22) X®45"
0.042 (1.07)

'"''-

I 0.050 (1.27)

4SIDES

~ - · - - - ·

1 -- 1-

- -1 I·

0.358 (9.04) o.350(8.89)

CD
:::I

®

0.025 (0.64) MIN.

0.032 (0.81)

®

0.028 (0.88)

00..005482 (c11..4027)) X45·---lI J.l-:..__-H-,{·---t-T-:-:-:-::-

-H-

0.045(1.14) R

in parentheses.

"II

3. Dimensioning and tolerancing per ANSI Y14.5M-1982.

I"'

& Datum plane "-H-" located at the top of mold parting line and coincident

J>
fl)

with top of lead, where lead exits plastic body.
& Location to datum "-A-' and '-B-" to be determined at plane "-H-". These

-I
0

datums do not include mold flash. Mold flash protrusion shall not exceed 0.01 o· (0.25mm) on any side.
& Datum "0-E" and "F-G" are determined where these center leads exilfrom the body at plane "-H-".
7. Pin numbers continue counterclockwise to Pin 20 (top view). 8. Signetics order code for product packaged in a PLCC is the suffix

Im"' cmcJ>
0::c

& "A" after the product number. Applicable to packages with pedestal only.

=a
0

L!. O.Ol5 (0.3B) ~0.020 (0.5) MIN.~
Ln 0.005 (0.13) CLEARANCE W/O

PEDESTAL

PEDESTAL

::J::>nn i::ini

C·T.1 CLEARANCE - - - L 1 SEATING PLANE 4 0.198(5 03/ 8 IJ"lo.010(0.25J©IA®le®I& 0.194(4.93) ill

o.330 (8.38)

IJ"I 0.015 co.38) ®I 1>-E ® I

~ ~
0
,"J.>,

0.290(7.37)

m

0.025 (0.64)

20PLACES

I "'C nD> ;II;"

..=-0r
-6-
~

cDc>
CD
c 0
s·:::::!:.

~r :ac:J. ~ Ol
-0
.&
iii

CD 3

(I)

3

!"Z' :

CD

b

"c';·

0
.~.·

.. I~"''-
::> <:
~
IB
11 ~

0.495 (12.57) ·I l-$-10.007 (0.181®1 A®I F-G ®I 0.485 (12.32)

0
g""'
"Tl
,,cI\p)

z

0.010 (0.25) MAX. R 3 PLACES

0.007(0.1~l®I B®I D-E®

w
8

0.456 (11.58) 0.450 (11.43)

0.495 (12.57) 0.485 (12.32)

NOTES

3

1. Package dimensions conform to JED EC Specification M0-047-AB

~

for Plastic Leaded Chip Carrier 28 leads, 0.050 inch (1.27mm) lead spacing, square. (Issue A, 10/31/84.)
2. Controlling dimensions: inches. Metric dimensions in mm are shown in parentheses.

~.
,,a.
.!.

Q)
al

0.048 (1.22) ®
~)X45°

[

I-ill
&

I 0.050 (1.27)

4SIDES

~14~1------.---.~-1A-®~s~IF--G~®~l+i·~

0.456 (11.58) 0.450 (11.43)

®
0.032 (0.81)
0.026 (0.66)
f-

0.025 (0.64) MIN.

-H~004 (0.10)1 SEATING PLANE

0.180 (4.57) 0.165(4.19)
Jl l 00..00~113-((00..53;3,:.c-:s-1;4;1i0;.0r0,7c(0;.:18;):@:1:Dc-~Ec®=r·cF---G~-®--I

I _,,__ _,_ 0.430 (10.92)

0.045 (1.14)

0.390 (9.96)"(Jfl 0.015 (0.38)@1 F-G®

3. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Lt Datum plane "-H-" located at the top of mold parting line and coincident

re>n

with top of lead, where lead exits plastic body.
& Location to datum "-A-" and "-B-" to be determined at plane "-H-". These
datums do not include mold flash. Mold flash protrusion shall not
exceed 0.010" (0.25mm) on any side.
,&. Datum "D-E" and "F-G" are determined where these center leads

-I
0 >rm
0

exit from the body at plane "-H-". 7. Pin numbers continue counterclockwise to Pin 28 (top view). 8. Signetics order code for product packaged in a PLCC is the suffix

m c
0:c

& "A" after the product number. Applicable to packages with pedestal only.

A

t Location of Pin #1 mark is optional. Mark on chamfered side is preferred.

LbJ!.:l. 0O·0.D0155 ((O0.·3183))

0.020 (0.5) MIN. ~
CLEARANCE W/O

ci_~~~1"6E PEDESTAL

~

· 1 SEATING PLANE

LI· .J I A'""'®~IB~®~I&,. 0.224 (5.69/ 8 1r.§c-l,..,.o..,,..01"'0.,..,(o"".25"'°i<=r:9I Ll2l 0.218 (5.54) ill

0.430 (10.92)

=ii
~
:ti
;:;t;i
:ti
~ ~
0
" ~

o.390 (9.91)·$Jo.015 (0.38l®I D-E ®I

m

0.025 (0.64) R

28 PLACES

,,

I m"CJ

-~o·
tn

(')
cm;cII;'
CD

(J)
"3e'r
0
:a:>.
<:

0

,, c0:

B iii

s·::::!:. .8 iil

CD 3

tn

3
"~'

b
IQ
O"

0
"2< ' ·

tn

c....
~ c:

c0wo

i ~
l8
"" ~
§ 0.010 (0.25) MAX. R
3 PLACES

o.795(20.19)

,1

0.785 (19.94)

~
I --1rffi&I

l~lo.001(0.19i@JA®Jf'.-O©J 0.001 (o.108l®l s®J D-E ®

m--.I
U1 I'))
z"C

0.756 (19.20) 0. 750 (19.05)

~

__..!
~
&

0.795 (20.19) 0.785 (19.94)

JL ®
0.048 (1.22)

-!~£

0.042 (1.07) X45 ·

I 0.050 (1.27) J4 SIDES

0.756 (19.20) --->--~-~ '--------~ 0.750 (19.05)
"~ '

®

0.045(1.14) 0.025 (0.64) R

0.180 (4.57)

0.165(4.19)

l.I'---------------1'-'--'-~~~-

...{

I _ 0.021 (0.53)
0.013(0.33)

-10$10.007

(0.18)1Qil

0-E

®·

F--0

®I

0.730(18.54)~
0.690 (17.53)

NOTES
1. Package dimensions conform to JEDEC Specification M0-047-AD for Plastic Leaded Chip Carrier 52 leads, 0.050 inch (1.27mm) lead spacing, square. (Issue A, 10/31/84).
2. Controlling dimensions: inches. Metric dimensions in mm are shown in parentheses.
3. Dimensioning andtolerancing per ANSI Y14.5M-1982.
& Datum plane "-H-" located at the top of mold parting line and coincident
with top of lead, where lead exits plastic body.
& Location to datum "-A-" and "-B-" to be determined at plane "-H-". These datums do not include mold flash. Mold flash protrusion shall not exceed 0.010" (0.25mm) on any side.
.&l. Datum "D-E" and "F-G" are determined where these center leads exit from the body at plane ·-H-·.
7. Pin numbers continue counterclockwise to Pin 52 (top view).
8. Signetics order code for product packaged in a PLCC is the suffix "A" after the product number.
Lfti. Applicable to packages with pedestal only.

~ 0.730 (18.54) 0.690 (17.53)

b. 0.015 (0.38) t0.020 (0.5) MIN.~
l n 0.005 (0.13) CLEARANCE W/O PEDESTAL

--..

I SEATING PLANE

&

& 0 o.364(9.25) l"$io,01o(0.25J©IA@ls@I 0.358 (9.09)

0.015(0.38)@ D-E@

"r C J>
(/)
-I
0
r m
mccJ>
(')
:c '6
0
m::J::>uu
::u
~ ~
0
"J>
G')
m

68 PLACES

"O

I ""C I» (')

2: ~
"en'
(\)

~
cIc»
CD
=c0

3
8'
:ac;n>:;. ;;;
a"O
<O

:J iil

CD 3

"' 3
."2,':

b
'n9.
0
(\)
~·

"'

~

~
~

I
tii 0.010 (0.25) MAX. R 3PLACES

- - - - 0.995(25.27) 0.985 (25.02)
~

·I l-$-I0.007(0.18l®JA®[F--O®J 0.001 (o.1sJ©T!©Io:E®

.---

I
m
'z"Cl

0.958 (24.33) 0.950 (24.13)

0.995(25.27)

"Cl

0.985 (25.02)
~--'-~~I -0.8,00-(2-0.3-2)

NOTES
1. Package dimensions conform to JEDEC Specification M0-047-AE for Plastic Leaded Chip Carrier 68 leads, 0.050 inch lead spacing,

~

square. (Issue A, 10131/84).

2. Controlling dimensions: inches. Mebic dimensions in mm are shown

~

in parentheses.

.

3. Dimensioning and tolerancing per ANSI Y14.5M-1982.
£ Datum plane ·-H-" located at the top of mold parting line and coincident

~ m c

~ J~L 0.048(1.22)
i-t::£.:J& 0.042(1.07) X45"

rr-, 0.05D (1.27) 4 SIDES

0.958 (24.33)

~

0.950 (24.13)

-

with top of lead, where lead exits plastic body.
& Location to datum '-A-" and ·-e-· to be determined at plane "-H-". These
datums do not include mold flash. Mold flash protrusion shall not

2;;

exceed 0.010" (0.25mm) on any side.
Lil. Datum "0-E" and "F-G" are determined where these center leads exit from the body at plane "-H-". 7. Pin numbers continue counterclockwise to Pin 68 (top view).

i
~

8. Signetics order code for product packaged in a PLCC is the suffix "A" after the product number.

~

£ Ai>Plicable to packages with pedestal only. & Location of Pin #1 mark is optional. Mark on chamfered side is
preferred.

L/J!.n. .

0.015 (0.38) 0.005 (0.13)

~C0L.E0A20RA(0N.5C) EMIWNI.O~

i
~
m

..-.,~---=~'"'-""'-=~~-:"'l::'!!i-~~~;:'"'~'"' cFC8ii~E PEDESTAL

Ce-wu~a4Alj,,&--iH-~i ''a'=ui=>aoJ6i}'liM 0.604(15.34) /J.. l!I o.598(15.19) ID

· r 1 ' SPELAATNINEG /J..
0.010(0.25)Q;) A® B® LJn.

0.930(23.62) 0.890 (22.81)

0.015(0.38) D-E®

68PLACES

"ti D>

~
~

~ f ()

J CD
c 0
{ :5::!·:.

CD
i tn

i
c
.I.·

; o.cug~o~5)

11

3 PLACES

§

1.158 (29.41) 1.150 (29.21)

1.195 (30.35) 1.185 (30.10)

J__j

~ 1---EB& I 0.048(1.22)@ 11
-I 0.042(1.07) x45·

~4SIDES

·

11..115580((2299..2411))

·I I -·-;-- ... , ..,

0.045 (1.14) 0.025 (0.64) R
84 PLACES

0.180 (4.57) 0.165(4.19)
0.120 (3.05) 0.090 (2.29)

~
"11

~
z'ti

'rt-i

~

0 NOTES
1. Package dimensions conform to JEDEC Specification M0-047-AF

for Plastic Leaded Chip Carrier 84 leads, 0.050 inch lead spacing, square. (Issue A, 10/31/84).
2. Controlling dimensions: inches. Metric dimensions in mm are shown in parentheses.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982.

f;; cmc>

~ Datum plane "-H-" located at the top of mold parting line and coincident with top of lead, where lead exits plastic body.
& Location to datum "-A-" and "-B-" to be determined at plane ·-H-". These datums do not include mold flash. Mold flash protrusion shall not exceed 0.010" (0.25mm) on any side.
& Datum "D-E" and "F-G" are determined where these center leads

0:c
=a ~
lJ lJ

exit from the body at plane "-H-". 7. Pin numbers continue counterclockwise to Pin 84 (top view).

~

~ 8. Signetics order code for product packaged in a PLCC is the suffix "A" after the product number.

~ Applicable to packages with pedestal only.

AQ. Location of Pin #1 mark is optional. Mark on chamfered side is preferred.

/). 0.015 (0.38)

0.020(0.5)MIN.
t ~ CLEARANCE W/O

ill 0·005 (0·13)

~
~
G')
m

PEDESTAL

ci~~~T:~E

L SEATING

PLANE

r----o-1~(1iaBi-;--i--- ,...__.. / &

1---"' ~ill '

l4flo.010(0.25i©IACIDl0®I

1.130(28.70) --10§10.015(0.38)@1 D-E® ~
1.090 (27.69)

"C D>
() ~

~
~·
~

~ ~

(D
c 0
:=:;::!·:.

!ai
iii
,-gc
iil

(D
rn

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NOTES: 1. Controlling dimension: Inches. Millimeters are
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NOTES: 1. Controlling dimension: Inches. Millimeters are
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NOTES: 1. Controlling dimension: Inches. Millimeters are
shown in parentheses. 2. Dimension and tolerancing per ANSI Y14. SM-1982. 3. "T", 'D", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on the seal line, and lid to base mismatch. 4. These dimensions measured with the leads constrained to be perpendicular to plane T 5. Pin n~mbers start with Pin #1 and continue counterclockwise to Pin #28 when viewed from the top. @ 6. Denotes window location for EPROM products.

0.175 (4.45) 0.145 (3.68)
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0.015 (0.38) 0.010(025)

0.620 (15.75)
0.590 (14.99) (NOTE4)

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0.51 {0.02)X45°

to ANSI Y14.5-1982.

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~ Dimensions do not include glass protrusion.
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ca.,.

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1.057 (26.85) 1.045 (26.54)

2. Package dimensions conform to JEDEC Specification MS-001-AE for standard Dual In-Line (DIP) package 0.300 inch row spacing (plastic) 20 leads (Issue B, 7/85).
3. Dimension and tolerancing per ANSI Y14, 5M-1982.
4. "T", "D", and "E" are reference datums on the molded body and do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm) on any side.
5. These dimensions measured with the leads constrained to be perpendicular to plane T.
6. Pin numbers start with Pin #1 and continue counterclockwise to Pin #20 when viewed from the top.

SEATING PLANE
Jl 0.02210.s61-Ef[TJE]n-®~1025)®] O.Q17 (0.43)

0.138 (3.51) 0.120 (3.05)

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O.D15 (0.38) O.Q10 (0.25)

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4. "T", ·o·, and ·e· are reference datums on the molded body and do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm) on any side.
5. These dimensions measured with the leads constrained to be perpendicular to plane T.
6. Pin numbers start with Pin #1 and continue counterclockwise to Pin #24.when viewed from the top.

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0.560 (14.22) (plastic) 28 leads (Issue B, 7/84).

]'"': Dimension and tolerancing per ANSI Y14, SM - 1982. "T", "D", and "E" are reference datums on the molded body and

9.i .~.........9.......v.......v.......v.....,v""'F"l"'"fv'""""v,-;o.v....v~v...v."""'.v............

do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm) on any side.

0. 100 (2.54) SSC

5. These dimensions measured with the leads constrained to be perpendicular to plane T.

1 460 (37 OBJ
r - 1 - - - - - - - 1.415(35.94)

6. Pin numbers start with Pin #1 and continue counterclockwise to Pin #28 when viewed from the top.

o.022(0.56J--J'il-I TIE lo@lo.010(0.251@1 0.017 (0.43)

® 0.620(15.75)~
, _ Q.600 (15.24)

(NOTES)

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0.010 (0.25)--JL

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1. Controlling dimension: Inches. Metric are shown in parentheses.
2. Dimension and tolerancing per ANSI Y14, SM - 1982.

'SJ?

Si?

0.280 (7.11) ©
0.255 (6.48)
v v v v v v v v v v v y·l_l

3
.

"T", "D", and "E" are reference datums on the molded body and do not include mold flash or

protrusions which shall not exceed 0.010 inch

(0.25mm) on any side.

4. These dimensions measured with the leads

constrained to be perpendicular to plane "T".

0.100 (2.54) BSC
1.425 (35.63) @
f---1--~~~~~~~~~- -~~-
1.415 (35.38)

0.055(1.40)@

~

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[±]__

@ 0.021 (0.53) -1~%~1T-.-1=-ET:oI :-c®~lo:-::.0::;10;-;(o;;:.2;;;;5);A@ill 0.015 (0.38)

5. Pin numbers start with Pin #1 and continue

counterclockwise to Pin#28 when viewed

·

from the top.

& Lead tip taper is required after trimming.

@

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0.150 (3.81)-,

0.300 (7.62)

tMAX ©
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(NOTE4)

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0.300 (7.62)

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NOTES 1. Package dimensions conform to JEDEC Specification MS-013-AC

10.26 (0.404)

for standard Small Outline (SO) package, 20 leads, 7.50mm (0.300")

l-$-1 E @lo.25 (0.010)@1

body width (Issue A, June 1985).

2. Controlling dimensions are mm. Inch dimensions in parentheses.

3. Dimensioning and tolerancing per ANSI Y14.SM-1982.

·o· 4. "D" and "E" are reference datums on the molded body and do not include mold flash/protrusions. Mold flash/protrusions at shall not
exceed 0.1 Smm (0.006") per side. Inter-lead flash/protrusions at "E" shall not exceed 0.25mm (0.01 O") per side.

~

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~1.27 (0.050) SSC
1123..6000((00..459162) )®_ _ _ _ _ __-J

5. The lead width above the seating plane shall not exceed a maximum value of 0.61mm (0.024").
6. Pin numbers start with Pin #1 and continue counterclockwise to Pin #20 when viewed from top.
7. Signetics ordering code for a product packaged in a plastic Small Outline (SO) package is the suffix D after the product number.

I
-

0.75 (0.030) 0.50 (0.020) x 45·

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IOJo.10(0.004)1

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2.65 (0.104) 2.351093)

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1.07 (0.042) 0.86 (0.034)

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NOTES 1. Package dimensions conform to JEDEC Specification
MS-013-AD for standard Small OuUine (SO) package, 24 leads, 7.50mm (0.3001 body width (Issue A. June 1985). 2 Controlling dimensions are mm. Inch dimensions in · parentheses.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982.
4. ·o· and "E" are reference datums on the molded body and do

Jz !
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not include mold flash/protrusions. Mold flash/protrusions
at ·o· shall not exceed 0.15mm (0.006">ger side. Inter-lead
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~

per side.

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5. The lead width abow lhe seating plane shall not exceed a maximum value of 0.61mm (0.024;.
6. Pin numbers start with Pin #1 and continue counterc:lockwise to Pin #24 when viewed from top.
7. Signetics ordering code for a product packaged in a plastic Small OuUine (SO) package is the suffix D after the

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15.20 ~.598)

product number.

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Programmable Logic Devices

Section 13
North American Regional Sales Organization Sales Offices

North American Sales Offices, Representatives and Distributors . . . . . . . . . . . . · . . . . . . 895

Philips Semiconductors
North American Sales Offices, Representatives and Distributors

PHILIPS SEMICONDUCTORS 811 East Arques Avenue P.O. Box 3409 Sunnyvale, CA 94088-3409
ALABAMA Huntsville
Philips Semiconductors Phone: (205) 464-0111
Elcom, Inc. Phone: (205) 830-4001
ARIZONA Scottsdale
Thom Luke Sales, Inc. Phone: (602) 451-5400
CALIFORNIA Calabasas
Philips Semiconductors Phone: (818) 880-6304
Irvine Philips Semiconductors Phone: (714) 833-8980 (714) 752-2780
Orangevale Webster Associates Phone: (916) 989-0843
San Diego Philips Semiconductors Phone: (619) 560-0242
San Jose B.A.E. Sales, Inc. Phone: (408) 452-8133
Sunnyvale Philips Semiconductors Phone: (408) 991-3737
COLORADO EnWewood
hilips Semiconductors Phone: (303) 792-9011
Thom Luke Sales, Inc. Phone: (303) 649-9717
CONNECTICUT Wallingford
JEBCO Phone: (203) 265-1318
FLORIDA Oviedo
Conley and Assoc., Inc. Phone: (407) 365-3283
GEORGIA Atlanta
Philips Semiconductors Phone: (404) 594-1392
Norcross Elcom, Inc. Phone: (404) 447-8200
ILLINOIS Hoffman Estates
Micro-Tex, Inc. Phone: (708) 765-3000

Itasca Philips Semiconductors Phone: (708) 250-0050
IN DIANA lndlana~lis
Moh ield Marketing, Inc. Phone: (317) 546-6969
Kokomo Philips Semiconductors Phone: (317) 459-5355
MARYLAND Columbia
Third Wave Solutions, Inc. Phone: (410) 290-5990
MASSACHUSETTS Chelmsford
JEBCO Phone: (508) 256-5800
Westford Philips Semiconductors Phone: (508) 692-6211
MICHIGAN Monroe
S-J Associates Phone: (313) 242-0450
Novi Philips Semiconductors Phone: (313) 347-1700
MINNESOTA Bloomi'Wton
High echnology Sales Phone: (612) 844-9933
MISSOURI Bridgeton
Centech, Inc. Phone: (314) 291-4230
Raytown Centech, Inc. Phone: (816) 358-8100
NEW JERSEY Toms River
Philips Semiconductors Phone: (908) 505-1200
NEW YORK Ithaca
Bob Dean, Inc. Phone: (607) 257-1111
Rockville Centre S-J Associates Phone: (516) 536-4242
Wa~~ingers Falls ilips Semiconductors
Phone: (914) 297-4074
Bob Dean, Inc. Phone: (914) 297-6406
NORTH CAROLINA Greensboro
ADI, Inc. Phone: (919) 273-8887
Matthews ADI, Inc. Phone: (704) 847-4323

Smith field ADI, Inc. Phone: (919) 934-8136
OHIO Aurora
S-J Associates, Inc. Phone: (216) 562-2050
Columbus S-J Associates, Inc. Phone: (614) 885-6700
Kettering S-J Associates, Inc. Phone: (513) 298-7322
Parma S-J Associates, Inc. Phone: (216) 888-7004
Toledo S-J Associates, Inc. Phone: (313) 242-0450
West Carrollton S-J Associates, Inc. Phone: (513) 438-1700
OREGON Beaverton
Philips Semiconductors Phone: (503) 627-0110
Western Technical Sales Phone: (503) 644-8860
PENNSYLVANIA Erie
S-J Associates, Inc. Phone: (216) 888-7004
Hatboro Delta Technical Sales, Inc. Phone: (215)957-0600
Pittsburgh S-J Associates, Inc. Phone: (216) 888-7004
Plymouth Meeting Philips Semiconductors Phone: (215) 825-4404
TENNESSEE Greeneville
Philips Semiconductors Phone: (615) 639-0251
TEXAS Austin
Philips Semiconductors Phone: (512) 339-9945
Austin Synergistic Sales, Inc. Phone: (512)346-2122
Houston Synergistic Sales, Inc. Phone: (713) 937-1990
Richardson Philips Semiconductors Phone: (214) 644-1610
Richardson Shnergistic Sales, Inc. P one: (214) 644-3500

UTAH Salt Lake City
Electrodyne Phone: (801) 264-8050
WASHINGTON Bellevue
Western Technical Sales Phone: (206) 641-3900 Spokane Western Technical Sales Phone: (509) 922-7600
WISCONSIN Waukesha
Micro-Tex, Inc. Phone: (414) 542-5352
CANADA PHILIPS SEMICONDUCTORS CANADA, LTD.
Ca~ary, Alberta ech-Trek, ltd. Phone: (403) 241-1719
Kaneta, Ontario Philips Semiconductors Phone: (613) 599-8720
Tech-Trek, ltd. Phone: (613) 599-8787
Mississauga, Ontario Tech-Trek, ltd. Phone: (416) 238-0366
Richmond, B.C. Tech-Trek, ltd. Phone: (604) 276-8735
Ville St. Laurent, Quebec Tech-Trek, ltd. Phone: (514) 337-7540
MEXICO Anzures Section
Philips Components Phone: 52-5-533-3858
El Paso, TX Philips Components Phone: (915) 775-4020
PUERTO RICO Santurce
Mectron Grou~ Phone: (809) 23-6165
DISTRIBUTORS
Contact one of our local distributors: Alrnac/Arrow Electronics Anthem Electronics Arrow/Schweber Electronics Future Electronics Gerber Electronics Hamilton Hallmark Marshall Industries Wyle Laboratories, EMG Zeus Electronics
10126'93

Phillps Semiconductors
Data handbook system

Appendix A

DATA HANDBOOK SYSTEM Philips Semiconductors data handbooks contain all pertinent data available at the time of publication and each is revised and reissued regularly.

Loose data sheets are sent to subscribers to keep them up-to-date on additions or alterations made during the lifetime of a data handbook.

Catalogs are available for selected product ranges (some catalogs are also on floppy discs).

Our data handbook titles are listed here.

Integrated Circuits

Book Title

IC01

Semiconductors for Radio and Audio Systems

IC02

Semiconductors for Television and Video Systems

IC03

Semiconductors for Telecom Systems

IC04

CMOS HE4000B Logic Family

ICOS

Advanced Low-power Schottky (ALS) Logic Series

IC06

High-speed CMOS Logic Family

IC08

1OOK ECL Logic Families

IC10

Memories

IC11

General-purpose/Linear ICs

IC12

Display Drivers and Microcontroller Peripherals (planned)

IC13

Programmable Logic Devices (PLO)

IC14

8048-based 8-bit Microcontrollers

IC15

FAST TIL Logic Series

IC16

ICs for Clocks and Watches

IC18

Semiconductors for In-car Electronics and General Industrial Applications (planned)

IC17

RF/Wireless Communications

IC19

Semiconductors for Datacom: LANs, UARTs, Multi-protocol Controllers and Fibre Optics

IC20

80C51-based 8-bit Microcontrollers

IC21 IC22

68000-based 16-bit Microcontrollers (planned) ICs for Multi-media Systems (planned)

IC23

QUBiC Advanced BiCMOS Bus Interface Logic ABT, MULTIBYTETM

IC24

Low Voltage CMOS & BiCMOS Logic

Discrete Semiconductors

Book Title

SC01 Diodes

SC02 Power Diodes

SC03 Thyristors and Triacs

SC04
scos

Small-signal Transistors
Low-frequency Power Transistors and Hybrid IC Power Modules

SC06

High-voltage and Switching NPN Power Transistors

SC07 Small-signal Field-effect Transistors

SC08a RF Power Bipolar Transistors

SC08b RF Power MOS Transistors

SC09 RF Power Modules

SC10 Surface Mounted Semiconductors

SC13 SC14

Power MOS Transistors including TOPFETs and IGBTs
RF Wideband Transistors, Video Transistors and Modules

SC15 Microwave Transistors

SC16 SC17

Wideband Hybrid IC Modules Semiconductor Sensors

Professional Components PC01 High-power Klystrons and Accessories PC06 Circulators and Isolators

MORE INFORMATION FROM PHILIPS SEMICONDUCTORS? For more information about Philips Semiconductors data handbooks, catalogs and subscriptions contact your nearest Philips Semiconductors national organization, select from the address list on the back cover of this handbook. Product specialists are at your service and inquiries are answered promptly.

October 1993

896

Philips Semiconductors
Data handbook system

Appendix A

OVERVIEW OF PHILIPS COMPONENTS DATA HANDBOOKS Our sister product division, Philips Components, also has a comprehensive data handbook system to support their products. Their data handbook titles are listed here.

Dlsplay Components Book Title

DC01
DC02 DC03 DCOS

Colour Display Components Colour TV Picture Tubes and Assemblies Colour Monitor Tube Assemblies
Monochrome Monitor Tubes and Deflection Units
Television Tuners, Coaxial Aerial Input Assemblies
Flyback Transformers, Mains Transformers and General-purpose FXC Assemblies

Magnetic Products

MA01 Soft Ferrites

MA03

Piezoelectric Ceramics Specialty Ferrites

MA04 Dry-reed Switches

Passive Components PA01 Electrolytic Capacitors PA02 Varistors, Thermistors and Sensors PA03 Potentiometers and Switches PA04 Variable Capacitors PAOS Film Capacitors

PA06 Ceramic Capacitors

PA07 PA08 PA1O PA 11

Quartz Crystals for Special and Industrial Applications
Fixed Resistors
Quartz Crystals for Automotive and Standard Applications
Quartz Oscillaors

Professlonal Components PC04 Photo Multipliers

PCOS PC07
PC08

Plumbicon Camera Tubes and Accessories
Vidicon and Newvicon Camera Tubes and Deflection Units
Image Intensifiers

PC12 Electron Multipliers

MORE INFORMATION FROM PHILIPS COMPONENTS? For more information contact your nearest Philips Components national organizaiton shown in the following list.
Argentina: BUENOS AIRES, Tel. (541)5414261, Fax. (541)786 9367. AustraHa: NORTH RYDE, Tel. (02)805 4455, Fax. (02)805 4466. Austria: WIEN, Tel (01)601011820, Fax. (01)60101 1210. Belgium: BRUXELLES, Tel. (02)741 8211, Fax. (02)735 8667. Brazil: SAO PAULO, Tel. (011 )829 1166, Fax. (011 )8291849. Canada: SCARBOROUGH, Tel. (416)292 5161, Fax. (416)754 6248. Chile: SANTIAGO, Tel. (02)m 816, Fax. (02)5602 735 3594. China (Peoples Republic oij: SHANGHAI, Tel. (021 )3264140, Fax. (021 )3202160. Columbia: BOGOTA, Tel. (01)2497624, Fax. (01)261 0139. Denmark: COPENHAGEN, Tel. (032)883 333, Fax. (031 )571 949. Finland: ESPOO, Tel. (9)0-50261, Fax. (9)0-520971. France: SURESNES, Tel. (01)40996161, Fax. (01)40996431. Germany: HAMBURG, Tel. (040)3296-0, Fax. (040)3296 216. Greece: TAVROS, Tel. (01)489 4339/(01)489 4911, Fax. (01)481 5180. Hong Kong: KWAI CHUNG, Tel. (852) 724 5121, Fax. (852)480 6960. India: BOMBAY, Tel. (022)4938 541, Fax. (022)4938 722. Indonesia: JAKARTA, Tel. (021 )5201122, Fax. (021 )5205 189. Ireland: DUBLIN, Tel. (01)640203, Fax. (01)640210. Italy: MILANO, Tel. (02)6752.1, Fax. (02)6752 3300. Japan: TOKIO, Tel. (03)3740 5143, Fax. (03)3740 5035. Korea (Republicoij: SEOUL, Tel. (02)709-1412, Fax. (02)709-1415. Malaysia: KUALA LUMPUR, Tel. (03)757 5511, Fax. (03)757 4880. Mexico: CHI HUA HUA, Tel. (016)18-67-01/(016)18-67-02, Fax. (016)778 0551. Netherlands: EINDHOVEN, Tel. (040)7 83749, Fax. (040)7 88399. New Zealand: AUKLAND, Tel. (09)849-4160, Fax. (09)849-7811. Norway: OSLO, Tel. (22)748000,Fax. (22)748341. Pakistan: KARACHI, Tel. (021 )577 032, Fax. (021 )569 1832. Phlllpplnes: MANILA, Tel. (02)810-0161, Fax. (02)817-3474. Ponugal: LISBOA, Tel. (01)388 3121, Fax. (01)388 3208. Singapore: SINGAPORE, Tel. (65)350 2000, Fax. (65)3551758. South Africa: JOHANNESBURG, Tel. (011 )470-5434, Fax. (011 )470-5494. Spain: BARCELONA, Tel. (93)301 6312, Fax. (93)301 4243. Sweden: STOCKHOLM, Tel. (08)632 2000, Fax. (08)632 2745. Switzerland: ZORICH, Tel. (01 )488 2211, Fax. (01 )481 7730. Taiwan: TAIPEI, Tel. (2)509 7666, Fax. (2)500 5912. ThaOand: BANGKOK, Tel (2)399-3280 to 9, (2)398-2083, Fax. (2)398-2080. Turkey: ISTANBUL, Tel. (01 )279 2770, Fax. (01)2693094. United Kingdom: LONDON, Tel. (071)580 6633, Fax. (071)636 0394. United States: RIVIERA BEACH, Tel. (800)447-37621(407)881-3200, Fax. (407)881-3300. Uruguay: MONTEVIDEO, Tel. (02)704 044, Fax. (02)920 601. For all other countries apply to: Philips Components. Marketing Communications, Building BAE, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands Telex 35000 phtcnl, Fax. +31-40-724547.

October 1993

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Philips Semiconductors - a worldwide company

Argentina: IEROD, Av. Juramento 1992-14.b (1428) BUENOS AIRES, Tel. (541) 786 7633, Fax. (541) 786 9367
Australia: 34 Waterloo Road,NORTH RYDE, NSW 2113, Tel. (02) 805-4455, Fax. (02) 805 4466
Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01) 60101·1236, Fax. (01) 60101-1211
Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Nethertands, Tel. (31)40 783 749, Fax. (31)40 788 399
Brazil: Rua do Rocia 220 - 5th Floor, Suite 51 CEP: 04552·903 SAO PAULO-SP, Brazil P.O. Box 7383-(01064·970), Tel. (011) 829·1166, Fax (011) 829·1849
Canada: INTEGRATED CIRCUITS: Tel. (800) 234·7381, Fax. (708) 296·8556 DISCRETE SEMICONDUCTORS: 601 Milner Ave., SCARBOROUGH, ONTARIO, M1B 1M8 Tel. (0416) 292-5161ext.2336, Fax. (0416) 292-44n
Chile: Av. Santa Maria 0760, SANTIAGO,
Tel. (02) m 816, Fax. (02) 1n 6730
Colombia: Carrera 21 No. 56· 17, BOGOTA, D.E .. P.O. Box 77621, Tel. (571)217 4609, Fax (01) 217 4549
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032) 88 2636, Fax. (031) 571949
Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0 50261, Fax. (9)0 520971
France: 4 rue du Port·aux·Vins, BP317 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax, (01)4099 6427
Genmany: P.O. Box 10 63 23, 20095 HAMBURG, Tel. (040) 3296·0, Fax. (040) 3296 213
Greece: No. 15, 25th March Street, GR 1n78 TAVROS, Tel. (01) 4894 339/4894 911, fax. (01) 4814 240
Hong Kong: 15/F Philips Ind. Bldg., 24·28 Kung Yip St., KWAI CHUNG, Tel. (0)42 45 121, Fax. (0) 4806 960
India: PEICO ELECTRONICS & ELECTRICALS Ltd., Components Dept., Shivsagar Estate, Block 'P!, Dr. Annie Besant Rd., Worli, BOMBAY-400 018, Tel. (022) 49 38 541, Fax. (022) 4938 722
Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 34, P.O. Box 4252, JAKARTA 12950 Tel. (021) 5201122, Fax (021) 5205189
Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01) 640000, Fax. (01) 640 200
haly: Viale F. Testi, 327, 20162-MILANO, Tel. (02) 6752.1, Fax. (02) 6752 3350
Japan: Philips Bldg. 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. (03) 3740 5101, Fax. (03) 37400 570
Korea (Republic of): Philips House,260-199 ltaewon-dong, Yongsan-ku, SEOUL, Tel. (02) 794 5011, Fax. (02) 798 8022
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03) 757 5511, Fax. (03) 757 4880
Mexico: Philips Components, '5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9·5(800) 234·7381, Fax. (708) 296-8556
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Tel. (040) 78 37 49, Fax. (040)78 83 99
New Zealand: 2 Wagener Place, C.P.0. Box 1041, AUCKLAND, Tel. (09) 849·4180, Fax. (09) 849·7811

Norway: Box 1, Manglerud 0612, OSLO, Tel. (22) 74 8000, Fax (22)74 8341
Pakistan: Philips Markaz, M.A. Jinnah Rd., KARACHl-3, Tel. (021) 577 039, Fax. (021) 569 1832
Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc., 106 Valero St. Salcedo Village, P.O. Box 911, MAKATI, Metro MANILA, Tel. (02) 810 0161, Fax. (02) 817 3474
Portugal: Av. Eng. Duarte Pacheco 6, 1009 LISBOA Codex, Tel. (01)683121, Fax. (01)658013
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65) 350 2000, Fax. (65) 251 6500
South Africa: 195·215 Main Road, Martindale, P.O. Box 7430, JOHANNESBURG 2000, Tel. (011) 470·5433, Fax. (011) 470·5494
Spain: Balmes 22, 08007 BARCELONA, Tel. (03) 301 6312, Fax. (03) 301 42 43
Sweden: Kottbygatan 7, Akalla. S·164 85 STOCKHOLM, Tel. {0)8·632 2000, Fax. (0)8-632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZORICH, Tel. (01) 488 2211 , Fax. (01) 481 7730
Taiwan: 69, Min Sheng East Road, Sec. 3, P.O. Box 22978, TAIPEI 10446, Tel. (2) 509 7666, Fax. (2)500 5899
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd. 60/14 MOO 11, Bangna- Trad Road Km. 3 Prakanong, BANGKOK 10260 Tel. (2)399·3280 to 9, (2)398-2083, Fax. (2)398-2080
Turkey: Talatpasa Cad. No. 5, 80640 LEVENT/ISTANBUL, Tel. (0212) 279 2770, Fax. (0212) 269 3094
United Kingdom: Philips Semiconductors Limited, P.O. Box 65, Philips House, Torrington Place, LONDON WC1 E 7HD, Tel. (071) 436 4144, Fax. (071) 323 0342
United States: INTEGRATED CIRCUITS: 811 East Arques Avenue, SUNNYVALE, CA 94088·3409, Tel. (800) 234-7381, Fax. (708) 296-8556 DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd., P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404, Tel. (800) 447-3762.and (407)881·3200, Fax. (407) 881·3300
Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02) 70 4044, Fax (02) 92 0601

For alt other countries apply to: Philips Semiconductors, Marketing Communications, Building BAF·1, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax +31·40·724825

SCD26

©Philips Electronics N.V. 1993

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent - or industrial or intellectual property rights.

Printed in the USA

2093B/24M/CR211293 904pp

Document order number: Document order number USA:

9398 652 47011 98·7001-230·02

PHILIPS