Index of /components/zilog/z8
ntrollers
Embedded Control used in a variety of
User's Manual
ZS® Microcontrollers
User·s Manual
02195 UM95Z80010
Overview
Zilog·s Focus on Application-Specific Products Helps You Maintain Your Technological Edge
The ZS® Microcontroller User's Manual consists of the following:
· ZS® Architecture Technical Description
· Zilog Software User's Guides - asm ZS® Cross Assembler - Zilog Universal Object File Utilities
· Zilog General Information - General Terms and Conditions - Zilog Sales Offices, Representatives, and Distributors - Zilog Literature Guide
Application notes and other information on Zilog specialty software and documentation is available through the Zllog Bulletin Board Service (ZBBSJ, which can be reached by calling 408-370·8024 (up to 28.8 baud supported, B-N·1 connections, and ANSI/BBS terminal emulation setup recommended}.
© 1994, 1995 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com/zilog
UM95Z800103
Z8' MICROCONTROLI.ERS
USER's MANUAL
ZILOG ZS® MICROCONTROLLERS USER1S MANUAL
TABLE OF CONTENTS
za· I.
MICROCONTROLLER TECHNICAL DESCRIPTION
CHAPTER TITLE AND SUBSECTIONS
PAGE
zae CHAPTER 1: DISCRETE
PRODUCT OVERVIEW
1.1 ZS MCU Family Overview ........................................................................................................ 1-1
CHAPTER 2: ADDRESS SPACE
2.1 Introduction .............................................................................................................................2-1 2.2 ZS® Standard Register File ......................................................................................................2-1 2.3 ZS® Expanded Register File ....................................................................................................2-5 2.4 ZS® Control and Peripheral Registers .................................................................................... 2-8 2.5 Program Memory ...................................................................................................................2-10 2.6 Z8® External Memory ............................................................................................................2-11 2.7 ZS® Stacks .............................................................................................................................2-12
CHAPTER 3: CLOCK
3.1 Clock .......................................................................................................................................3-1 3.2 Clock Control ...........................................................................................................................3-1 3.3 Oscillator Control .....................................................................................................................3-2 3.4 Oscillator Operation ................................................................................................................3-3 3.5 LC Oscillator ............................................................................................................................3-7 3.6 RC Oscillator ...........................................................................................................................3-8
CHAPTER 4: RESET-WATCH-DOG TIMER
4.1 Reset .......................................................................................................................................4-1 4.2 /Reset Pin, Internal POR Operation ........................................................................................ 4-1 4.3 Watch-Dog Timer (WOT) .........................................................................................................4-7 4.4 Power-On-Reset (POR) ...........................................................................................................4-8
CHAPTER 5: 1/0 PORTS 5.1 Introduction .............................................................................................................................5-1 5.2 Port O.......................................................................................................................................5-2 5.3 Port 1 .......................................................................................................................................5-5 5.4 Port 2 .......................................................................................................................................5-9 5.5 Port3 .....................................................................................................................................5-13 5.6 Port Handshake ....................................................................................................................5-19 5.7 1/0 Port Reset Conditions ......................................................................................................5-23
CHAPTER TITLE AND SUBSECTIONS
zae MICROCONTROLLERS USER'S MANUAi. PAGE
CHAPTER 5: 1/0 PORTS (CONTINUED) 5.8 Analog Comparators .............................................................................................................5-25 5.9 Open-Drain Configuration .....................................................................................................5-29 5.10 Low EMI Emission ...............................................................................................................5-29 5. 11 Input Protection ...................................................................................................................5-30 5.12. CMOS Z8® AUTO lATCHES .....................................................................................................5-31
CHAPTER 6: CouNTERJ'TIMERS 6.1 Introduction .............................................................................................................................6-1 6.2 Prescalers and Counter{Timers ...............................................................................................6-2 6.3 Counter!Timer Operation .........................................................................................................6-3 6.4 Tour Modes ..............................................................................................................................6-5 6.5 T1N Modes ................................................................................................................................6-7 6.6 Cascading Counter!Timers ...................................................................................................6-11 6. 7 Reset Conditions ...................................................................................................................6-12
CHAPTER 7: INTERRUPTS 7.1 Introduction .............................................................................................................................7-1 7.2 Interrupt Sources .....................................................................................................................7-2 7.3 Interrupt Request (IRQ) Register Logic and Timing ............................................................... 7-4 7.4 Interrupt Initialization ...............................................................................................................7-5 7.5 IRQ Software Interrupt Generation ......................................................................................... 7-9 7.6 Vectored Processing ...............................................................................................................7-9 7. 7 Polled Processing .................................................................................................................7-12 7.8 Reset Conditions ...................................................................................................................7-12
CHAPTER 8: POWER-DOWN MODES 8.1 Introduction .............................................................................................................................8-1 8.2 Halt Mode Operation ...............................................................................................................8-1 8.3 STOP Mode Operation ............................................................................................................8-2 8.4 STOP-Mode Recovery Register (SMR) .................................................................................. 8-3
CHAPTER 9: SERIAL VO
9.1 UART Introduction ...................................................................................................................9-1 9.2 UART Bit-Rate Generation ......................................................................................................9-2 9.3 UART Receiver Operation .......................................................................................................9-4 9.4 Transmitter Operation ..............................................................................................................9-6 9.5 UART Reset Conditions ...........................................................................................................9-8 9.6 Serial Peripheral Interface (SPI) ..............................................................................................9-9 9. 7 SPI Operation ........................................................................................................................9-1 O 9.8 SPI Compare .........................................................................................................................9-10 9.9 SPI Clock ...............................................................................................................................9-10 9.10 Receive Character Available and Overrun ......................................................................... 9-12
ii
'Z8' MICROCONTROWRS
USER'S MANUAi.
CHAPTER TITLE AND SUBSECTIONS
PAGE
CHAPTER 10: EXTERNAL INTERFACE 10.1 Introduction ......................................................................................................................... 10-1 10.2 Pin Descriptions .................................................................................................................. 10-2 10.3 External Addressing Configuration .................................................................................... 10-3 10.4 External Stacks .................................................................................................................... 10-4 10.5 Data Memory ....................................................................................................................... 10-4 10.6 Bus Operation ..................................................................................................................... 10-5 10.7 Extended Bus Timing .......................................................................................................... 10-7 10.S Instruction Timing ................................................................................................................ 10-9 10.9 ZS® RESET CONDITIONS .......................................................................................................... 10-11
CHAPTER 11: ADDRESSING MODES 11.1 Introduction ......................................................................................................................... 11-1 11.2 ZS® REGISTER ADDRESSING (R) ................................................................................................. 11-2 11.3 ZS® INDIRECT REGISTER ADDRESSING (IR) .................................................................................. 11-3 1.4 Z8® INDEXED ADDRESSING (X) ..................................................................................................... 11-5 11.5 ZS® DIRECT ADDRESSING (DA) .................................................................................................. 11-6 11.6 ZS® RELATIVE ADDRESSING (RA) ................................................................................................ 11-7 11.7 ZS® IMMEDIATE DATA ADDRESSING (IM) ...................................................................................... 11-8
CHAPTER 12: INSTRUCTION SET 12.1 ZS® FUNCTIONAL SUMMARY ....................................................................................................... 12-1 12.2 Processor Flags .................................................................................................................. 12-2 12.3 Condition Codes ................................................................................................................. 12-4 12.4 Notation and Binary Encoding ............................................................................................ 12-5 12.5 ZS Instruction Summary ...................................................................................................... 12-7 12.6 Instruction Descriptions and Formats .............................................................................. 12-10
CHAPTER 13: Z1LOG EMULAToRs/SoFTWARE 13.1 ZILOG ZS® EMULATOR PRODUCTS ................................................................................................ 13-1 13.2 ZS CCPTM Emulator 'Quick Start" ......................................................................................... 13-2 13.3 ZS CCPTM Emulator Package Contents .. ..... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. ........ .. .. ... .. .. .. .. .. .. ..... ... 13-3 13.4 ZS6CCPOOZEM Emulator .................................................................................................... 13-4 13.5 ZS6CCPOOZAC Emulator Kit ............................................................................................... 13-5 13.6 ZS6C1200ZEM Emulator ..................................................................................................... 13-6 13.7 ZS6C5000ZEM Emulator ..................................................................................................... 13-7 13.8 Software ..............................................................................................................................13-8 13.9 Accessing Register Memory ............................................................................................... 13-8 13.10 Accessing Program and External Data Memory ............................................................ 13-12 13.11 BIT Manipulations ............................................................................................................ 13-13 13.11.1 Test Under Mask (TM) .................................................................................................. 13-14 13.11.2 Test Complement Under Mask .................................................................................... 13-14 13.12 Stack Operations ............................................................................................................. 13-15 13.13 Interrupts ......................................................................................................................... 13-16
iii
CHAPTER TITLE AND SUBSECTIONS
m' MICROCONTROLWIS USER'S MANUAL PAGE
13.14 Timer/Counter Functions ................................................................................................. 13-20 13.15 1/0 Functions ................................................................................................................... 13-29 13. 16 Arithmetic Routines ......................................................................................................... 13-37 13.17 Conclusion ...................................................................................................................... 13-42
CHAPTER 14: THIRD-PARTY SuPPoRT TooLS 14.1 Third-Party Support-Emulators/Programmers .................................................................. 14-1 14.2 Third-Party Support-Assemblers/C Compilers ................................................................. 14-1
iv
zr II. ZILOG
SOFTWARE
zae ASM
CROSS ASSEMBLER USER'S GUIDE
'ZS' MlcRocoNTROUERS
USEA'S MANUAL
CHAPTER TITLE AND SUBSECTIONS
PAGE
CHAPTER 1: OVERVIEW 1.1 Introduction ............................................................................................................................. 1-1 1.2 Assembler Overview ...............................................................................................................1-2 1.3 Relocation and Linking ............................................................................................................1-3
CHAPTER 2: ASSEMBLY LANGUAGE SYNTAX 2.1 Introduction .............................................................................................................................2-1 2.2 Symbolic Notation ...................................................................................................................2-1 2.3 Operations and Operands ......................................................................................................2-6 2.4 Comments ............................................................................................................................... 2-6 2.5 Arithmetic Expressions ............................................................................................................2-7 2.6 Expressions and Operators .....................................................................................................2-7 2.7 Constants ..............................................................................................................................2-10 2.8 Location Counter ...................................................................................................................2-11
CHAPTER 3: PSEUDO-OPS 3.1 Introduction .............................................................................................................................3-1 3.2 Relocation Pseudo-Ops ..........................................................................................................3-1 3.3 Label Definition Pseudo-Ops ..................................................................................................3-3 3.4 Module and Section Pseudo-Ops .......................................................................................... 3-6 3.5 General Data Definition Operation ......................................................................................... 3-8 3.6 Conditional Assembly Pseudo-Ops ..................................................................................... 3-12 3.7 Assembler Control Pseudo-Ops ............................................................................................3-13
CHAPTER 4: MACROS 4.1 General Description ................................................................................................................4-1 4.2 MACRO or String MACRO ......................................................................................................4-2 4.3 PROC or Procedure MACRO ..................................................................................................4-3 4.4 Special MACRO Pseudo-Ops .................................................................................................4-4 4.5 Special MACRO Operators .....................................................................................................4-6
CHAPTER 5: PROGRAM INVOCATION 5.1 Assembler Command Lines and Options .............................................................................. 5-1 5.2 Listing Format .........................................................................................................................5-2 5.3 Program Termination ...............................................................................................................5-2
APPENDICES
Appendix A. Pseudo-Op Summary ............................................................................................. A-1 Appendix 8. Special Symbols ..................................................................................................... B-1 Appendix C. ASCII Character Set ............................................................................................... C-1 Appendix D. Error Messages and Explanations ......................................................................... D-1 Appendix E. Program Example ................................................................................................... E-1
v
't'2H.!16
ZILOG UNIVERSAL OBJECT FILE UTILITIES USER'S GUIDE
ZS' MICROCONTROLLERS
USER'S MANUAL
CHAPTER TITLE AND SUBSECTIONS
PAGE
CHAPTER 1: INTRODUCTION
1.1 Overview ................................................................................................................................. 1-1 1.2 Utilities Description ................................................................................................................. 1-2 1.3 Utility Invocation ...................................................................................................................... 1-6
CHAPTER 2: MCONV 2.1 Introduction .............................................................................................................................2-1 2.2 Command Syntax and Options ...............................................................................................2-1
CHAPTER 3: MDUMP 3.1 Introduction .............................................................................................................................3-1 3.2 Command Syntax and Options ...............................................................................................3-1 3.3 Display Formats and Examples ..............................................................................................3-2
CHAPTER 4: MLIB 4.1 Introduction .............................................................................................................................4-1 4.2 Command Syntax and Options ...............................................................................................4-1 4.3 Examples .................................................................................................................................4-2
CHAPTER 5: MLINK 5.1 Introduction .............................................................................................................................5-1 5.2 Command Line Syntax and Options ...................................................................................... 5-4 5.3 Constraints ............................................................................................................................5-13 5.4 Using MUNK: Some Examples .............................................................................................5-14
CHAPTER 6: MLIST 6.1 Introduction .............................................................................................................................6-1 6.2 Command Syntax and Options ...............................................................................................6-1 6.3 USAGE, OUTPUT FORMAT AND EXAMPLES ......................................................................................... 6-1
CHAPTER 7: MLIST 7.1 Introduction .............................................................................................................................7-1 7.2 Command Syntax and Options ...............................................................................................7-1 7.3 Operation ................................................................................................................................7-2 7.4 Using MLOAD: Some Examples ............................................................................................ 7-3
CHAPTER 8: MLORDER 8.1 Introduction ....................................................................................................,........................ 8-1 8.2 Command Syntax and Options ...............................................................................................8-1
CHAPTER 9: MMM 9.1 Introduction .............................................................................................................................9-1 9.2 Command Syntax and Options ...............................................................................................9-1 9.3 Output Format and Examples .................................................................................................9-1
vi
CHAPTER TITLE AND SUBSECTIONS
ZP MICROCOHIROLLERS USER's l.fANUAL PAGE
CHAPTER 10: PROTOCOL
10.1 Introduction ......................................................................................................................... 10-1 10.2 Command Syntax and Options ........................................................................................... 10-1 10.3 Using PROTOCOL: Some Examples .................................................................................. 10-2
CHAPTER 11: OTHER PROGRAMS
11 .1 MAR .................................................................................................................................... 11-1 11.2 M2A ..................................................................................................................................... 11-1 11.3 MUIMAGE ........................................................................................................................... 11-2
APPENDICES
Appendix A. MUFOM File Format ............................................................................................... A-1 Appendix B. Tektronix Hex Format .............................................................................................. B-1 Appendix C. Intel Hex Format ..................................................................................................... C-1 Appendix D. Error Messages ...................................................................................................... D-1
Glossary ....................................................................................................................................... G-1
Ill. ADDITIONAL INFORMATION
GENERAL TERMS AND CoNDmoNs ...................................................................................................... T-1 ZILOG SALES OFFICES, REPRESENTATIVES, AND DISTRIBUTORS ............................................................... Z-1 ZILOG LITERATURE GUIDE .................................................................................................................. L-1
vii
II ZS® Mlcrocontroller
Technical Description
ft'2i1 In.,
USER'S MANUAL
1.1 ZS MCU FAMILY OVERVIEW
The Zilog Z89 microcontroller product line continues to expand with new product introductions. Zilog MCU products are targeted for cost-sensitive, high-volume applications including consumer, automotive, security, and HVAC. It includes ROM-based products geared for high-volume production (where software is stable) and one-time programmable (OTP) equivalents for prototyping as well as volume production where time to market or code flexibility is critical (Table 1-1). A variety of packaging options are available including plastic DIP, SOIC, PLCC, and QFP.
CHAPTER 1
DISCRETE Z8® PRODUCT OVERVIEW
II
A generalized ZB MCU block diagram is shown in Figure 1-1. The same on-chip peripherals are used across the MCU product line with the primary differences being the amount of ROM/RAM, number of 1/0 lines present, and packaging/temperature ranges available. This allows code written for one MCU device to be easily ported to another family member.
1.1.1 Key Product Line Features
· General-Purpose Register (GPR) Fiie Architecture: Every RAM register acts like an accumulator, speeding instruction execution and maximizing coding efficiency. Working register groups allow fast context switching.
· Flexible 1/0: 1/0 byte, nibble, and/or bit programmable as inputs or outputs. Outputs are software programmable as open-drain or push-pull on a port basis. Inputs are Schmitt-triggered with auto latches to hold unused inputs at a known voltage state.
· Analog Inputs: Three input pins are software programmable as digital or analog inputs. When in the analog mode, two comparator inputs are provided with a common reference input. These inputs are ideal for a variety of common functions, including threshold level detection, analog-to-digital conversion, and short circuit detection. Each analog input provides a unique maskable interrupt input.
· Tlmer/Counter(T/C): The T/C consists of a programmable 6-bit prescaler and 8-bit downcounter, with maskable interrupt upon end-of-count. Software controls TIC load/start/stop, countdown read (at any time on the fly), and maskable end-of-count interrupt. Special functions available include T1N (external counter input, external gate input, or external trigger input) and Tour (external access to timer output or the internal system clock.) These special functions allow accurate hardware input pulse measurement and output waveform generation.
· Interrupts: There are six vectored interrupt sources with software-programmable enable and priority for each of the six sources.
· Watch-Dog Timer (WOT): An internal WOT circuit is included as a fail-safe mechanism so that if software strays outside the bounds of normal operation, the WOT will timeout and reset the MCU. To maximize circuit robustness and reliability, the defaultWOT clock source is an internal RC circuit (isolated from the device clock source).
· Auto Reset/Low-Voltage Protection: All family devices have internal Power-On Reset. ROM devices add low-voltage protection. Low-voltage protection ensures the MCU is in a known state at all times (in active RUN mode or RESET) without external hardware (or a device reset pin).
· Low·EMI Operation: Mode is programmable via software or as a maskoption. This new option provides for reduced radiated emission via clock and output drive circuit changes.
· Low-Power: CMOS with two standby modes: STOP and HALT.
· Full ZS Instruction Set: Forty-eight basic instructions, supported by six addressing modes with the ability to operate on bits, nibbles, bytes, and words.
1-1
<tl21LCE
ZS' MICROCONTAOLLERS
Output Input
Vee GND
i i
Counter/ Timers (2)
Interrupt Control
Analog Comparators
(2)
ALU
FLAG
Register Pointer Register File 256X8·Bit
XTAL /AS IDS RINI /RESET
Machine Timing and Instruction Control RESET WDT,POR
Prg. Memory 4096x8-Bit
Program Counter
Port3
Porto
Port 1
1/0 (Bit Programmable)
Address or 1/0 (Nibble Programmable)
Address/Data or 1/0 (Byte Programmable)
Figure 1·1. zae MCU Block Diagram
1-2
·21Ul6
'1J' MICROCONIROUSIS
1.1.2 Product Development Support
The Z8~ MCU product line is fully supported with a range of cross assemblers, C compilers, ICEBOX emulators, single and gang OTP/EPROM programmers, and software simula tors.
The Z86CCPOOZEM low-cost Z8 CCPTM real-time emulator/programmer kit was designed specifically to support all the products outlined in Table 1-1.
PRODUCT
Z86C03 Z86C03 Z86C04 Z86E04 Z86C06 Z86E06 Z86COS Z86EOS ZS6C30 Z86E30 Z86C31 Z86E31 Z86C40 Z86E40
Table 1·1. Zilog General-Purpose Microcontroller Product Family
ROM/ l/O RAM 512/60 14 512/60 14 11</124 14 11</124 14 1K/124 14 11</124 14 21</124 14 21</124 14 41</236 24 41</236 24 21</124 24 21</124 24 41</236 32 41</236 32
T/C AN INT WOT POR Vbo RC SPEED
IN
(MHz)
2
6
F
y
y
y
8
2
6
F
y
N
y
8
2
2
6
F
y
y
N
8
2
2
6
F
y
N
N
8
2
2
6
p
y
y
y
12
2
2
6
p
y
N
y
12
2
2
6
F
y
y
N
12
2
2
6
F
y
N
N
12
2
2
6
p
y
y
y
12
2
2
6
p
y
N
y
12
2
2
6
p
y
y
y
8
2
2
6
p
y
N
y
8
2
2
6
p
y
y
y
12
2
2
6
p
y
N
y
12
PIN COUNT 18 18 18 18 18 18 1S 18 28 28 28 28 40/44 40/44
II
Note: Z86Cxx signify ROM devices; Z86Exx signify EPROM devices; F =fixed; P = programmable.
The Z86CCPOOZEM kit comes with: · ZS CCP Emulator/Programmer Module · 1S-pin Target Connection Cable
A Z8 CCP Emulator Accessory Kit (Z8CCPOOZAC) is also available and provides an RS-232 cable and power cable along with the 28- and 40- pin ZIF sockets and 28 and 40 pin target connector cables required to emulate/program 28/40 pin devices.
· WINDOWS-based GUI Host Software
· DOS-based ZASM LINKER/LOADER
· Documentation: ZBMOBJ Linker/Loader User's Guide, ZS Cross Assembler User's Guide, Z8 Emulator GUI User's Guide, Discrete ZS MCU Product Specifications Databook, and Z8 MCU Technical Manual.
1-3
~2iUD.,
USER'S MANUAL
2.1 INTRODUCTION
Four address spaces are available for the zse
microcontroller:
· The ZS Standard Register File contains addresses for
peripheral, control, all general-purpose, and all 1/0
port registers. This is the default register file specification.
· The ZS Expanded Register File (ERF) contains
CHAPTER 2
ADDRESS SPACE
El
addresses for control and data registers for additional peripherals/features.
· ZS External Program Memory contains addresses for all memory locations having executable code and/or data.
· ZS External Data Memory contains addresses for all memory locations that hold data only, whether internal or external.
2.2 ZS STANDARD REGISTER FILE
The ZS Standard Register File totals up to 256 consecutive bytes (Registers). The register file consists of 4 1/0 ports (OOH-03H). 236 General-Purpose Registers (04H-EFH), and 16 control registers (FOH-FFH). Table 2-1 shows the layout of the register file, including register names, locations, and identifiers.
Table 2·1. ZS Standard Register File
Hex Address
FF FE FD FC FB FA F9 FB
F7 F6 F5 F4
F3 F2 Fl FO
EF
Register Description
Stack Pointer Low Byte Stack Pointer High Byte Register Pointer Program Control Flags Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Port 0-1 Mode Register
Port 3Mode Register
Port 2 Mode Register TO Prescaler Timer/Counter O
T1 Prescaler Timer/Counter 1 Timer Mode Serial 1/0
Register Identifier
SPL SPH RP FLAGS IMR IRQ IPR POlM
P3M P2M PREO TO
PREl T1 TMR SIO
R239
General-Purpose Registers (GPR)
04
R4
03
Port3
P3
02
Port2
P2
01
Port 1
Pl
00
Port O
PO
Note: Refer to the product specification to determine which registers are available for use on any specific device.
2-1
2.2 ZS STANDARD REGISTER FILE (Continued)
'Z!' MICROCONTROLl.ERS
Registers can be accessed as either 8-bit or 16-bit registers using Direct, Indirect, or Indexed Addressing. All 236 general-purpose registers can be referenced or modified by any instruction that accesses an 8-bit register, without the need for special instructions. Registers accessed as 16 bits are treated as even-odd register pairs (there are 118 valid pairs). In this case, the data's Most Significant Byte (MSB) is stored in the even numbered register, while the Least Significant Byte (LSB) goes into the next higher odd numbered register (Figure 2-1).
MSB
LSB
Rn
Rn+1
= n Even Address
Figure 2·1. 16·Blt Register Addressing
By using a logical instruction and a mask, individual bits within registers can be accessed for bit set, bit clear, bit complement, or bit test operations. For example, the instruction AND R1 S, MASK performs a bit clear operation. Figure 2-2 shows this example.
2.2.1 General-Purpose Registers
General-Purpose Registers (GPR) are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the Vee voltage-specified operating range. It will not keep its last state from a VLv reset if Vcc drops below 1.8v.
Note: Registers in Bank EO-EF may only be accessed through the working register and indirectaddressing modes. Direct access cannot be used because the 4-bit working register address mode already uses the format [E I dst]. where dst represents the working register number from OH to FH.
2.2.2 RAM Protect
The upper portion of the register file address space SOFH to EFH (excluding the control registers) may be protected from reading and writing. The RAM Protect bit option is mask-programmable and is selected by the customer when the ROM code is submitted. After the mask option is selected, the user activates this feature from the internal ROM code to turn off/on the RAM Protect by loading either a 0 or 1 into the IMR register, bit D6. A 1 in D6 enables RAM Protect. Only devices that use registers 80H to EFH offer this feature.
2.2.3 Working Register Groups
ANDR15, DFH
;Clear Bit 5 of Working Register 15
I I I I I I I I I 0 1 0 1 0 0 0 0 R15
Figure 2·2. Accessing Individual Bits (Example)
When instructions are executed, registers are read when defined as sources and written when defined as destinations. All General-Purpose Registers function as accumulators, address pointers, index registers, stack areas, or scratch pad memory.
ZS® instructions can access S-bit registers and register pairs (16-bit words) using either 4-bit or 8-bit address fields. 8-bitaddress fields refer to the actual address of the register. For example, Register SSH is accessed by calling upon its 8-bit binary equivalent, 01011000 (SSH).
With 4-bit addressing, the register file is logically divided into 16 Working Register Groups of 16 registers each, as shown in Table 2-2. These 16 registers are known as Working Registers. A Register Pointer (one of the control registers, FDH) contains the base address of the active Working Register Group. The high nibble of the Register Pointer determines the current Working Register Group.
When accessing one of the Working Registers, the 4-bit address of the Working Register is combined within the upper four bits (high nibble) of the Register Pointer, thus forming the 8-bit actual address. Figure 2-3 illustrates this operation. Since working registers are typically specified by short format instructions, there are fewer bytes of code needed, which reduces execution time. In addition, when processing interrupts or changing tasks, the Register Pointer speeds context switching. A special Set Register Pointer (SRP) instruction sets the contents of the Register Pointer.
2-2
Table 2·2. Working Register Groups
Register Pointer (FDH)
High Nibble
1111(B) 1110(B) 1101(B) 1100(B) 1011 (B)
Working Register Group
(HEX)
F E
D
c
B
Actual Registers
(HEX)
FO-FF EO-EF DO-OF CO-CF BO-BF
1010(B) 1001(B) 1000(B) 0111(B) 0110(B)
A
AO-AF
9
90-9F
8
80-BF
7
70-7F
6
60-6F
0101(B) 0100(8) 0011 (8) 0010(8) 0001(8) 0000(8)
5
50-SF
4
40-4F
3
30-3F
2
20-2F
1
10-1F
0
00-0F
ZS' MICROCONTROLLERS
II
I I I I I I I I I O 1 1 1 0 0 0 0 Register Pointer (FDH), Standard Register File I I I I I I I I I 0 1 1 0 1 1 1 0 INC R6 (Instruction, Short Format)
0 1
0 1
O Actual Register Address (76H)
Figure 2·3. Working Register Addressing Examples
2-3
1.8' MICROCONTROLLERS
I I I ~~ster r7 r6 rs r4 r3 r2 r1 rO
Pointer)
The upper nibble of the register file address provided by the register pointer specHies
:---~ :: Ithe active working-register group. Working Register Group F
·
EF I
:---
I
.
·
80
I
:' --- 7F
·
70
·
6F
...__
60 SF
50
4F The lower nibble
40
of the register
3F 30
Specified Working Register Group
-+- file address provided by the instruction points
2F
20 IF
10 OF
Working Register Group 1 Working Register Group 0
1to the specified register. R15toRO R15to R4
00 ~------VO-P-or-ts--------
R3toRO
Figure 2-4. Register Pointer
Note: The full register file is shown. Please refer to the selected device product specification for actual file size.
2.2.4 Error Conditions
Registers in the ZS® Standard Register File must be correctly used because certain conditions produce inconsistent results and should be avoided.
· Registers F3H and F5H-F9H are write-only registers. If an attempt is made to read these registers, FFH is returned. Reading any write-only register will return FFH.
· When register FDH (Register Pointer) is read, the least significant four bits (lower nibble) will indicate the current Expanded Register File Bank. (Example: 0000 indicates the Standard Register File, while 1010 indicates Expanded Register File Bank A.)
· Writing to bits that are defined as timer output, serial output, or handshake output will have no effect.
· The ZS instruction DJNZ uses any general-purpose working register as a counter.
· Logical instructions such as OR and AND require that the current contents of the operand be read. They therefore will not function properly on write-only registers.
· The WDTMR register must be written within the first 64 internal system clocks (SCLK) of operation after a reset.
· When Ports 0 and 1 are defined as address outputs, registers OOH and 01H will return 1s in each address bit location when read.
2-4
2.3 ZS EXPANDED REGISTER FILE
ZS' MICROCONTROLLERS
The standard register file of the ZB® has been expanded to form 16 Expanded Register File (ERF) Banks (Figure 2-5). Each ERF Bank consists of up to 256 registers (the same amount as in the Standard Register File) that can then be
divided into 16 Working Register Groups. This expansion allows for access to additional feature/peripheral control and data registers.
EXPANDED REGISTER FILE BANK(F)
REGISTER POINTER
11 1·I ·I ·I ·I ·I ·I ·I
Working Regis~ ~anded Register
Gro!!i.Pointer
Gr°-!m_Pointer
(F)OF
WDTMR
_!BOE (F)OO ..JEl..OC
..J!:l.08
(F)OA
(F)09
_nos
""""''""""""""'
--SMA
---.......
Z8 Register File
FF FO
(F)07
..fil.06
_ill05
..fil.04
(F)03 (F)02 (F)01
-----."."."..".".".
(F)OO
POON
jj(~-~ BANK(C)
-;<:10F
-
'---t;I
OF 00
(C)OC
..J:V
(C) OD
__!9_0C
.J9.0B
(C)M
(C)09
(2L_06
]9_07
N~=_Jf:)04 {C)o.l _Jf:)02
Rusrwd Resarvad ........
------""""'""
"S"C"O"N'""
_Jf:)01
RXBUF
(C)OO
SCOMP
EXRllNDED REGISTER FILE BANK(O)
JiOF GPR
(Ql_OE
GPR
~D
GPR
..J!!LOC
GPR
(Ql_OB
GPR
_AOA
GPR
_A09
GPR
1£1_06
GPR
~7
GPR
..Jm..06
GPR
~·
_A04
GPR GPR
(0)03
P3
J!!)_02
P2
~· (0)00
P1 Po
Figure 2-5. Expanded Register File Architecture
Note: The fully implemented register file is shown. Please refer to the specific product specification for actual register file architecture implemented.
2-5
Currently, three out of the possible sixteen Z8<1t ERF Banks have been implemented. ERF BankO, also known as the ZB Standard Register File, has all 256 bytes defined (Figure 21). Only Working Register Group 0 (register addresses OOH to OFH) have been defined for ERF Bank C and ERF Bank F (Table 2-4). All other working register groups in ERF Banks C and F, as well as the remaining thirteen ERF Banks, are not implemented. All are reserved for future use.
When an ERF Bank is selected, register addresses OOH to OFH access those sixteen ERF Bank registers - in effect replacing the first sixteen locations of the ZB Standard Register File.
For example, if ERF Bank C is selected, the Z8 Standard Registers OOH through OFH are no longer accessible. Registers OOH through OFH are now the 16 registers from ERF Bank C. Working Register Group 0. No other ZB Standard Registers are effected since only Working Register Group 0 is implemented in ERF Bank C.
Access to the ERF is accomplished through the Register Pointer (FDH). The lower nibble of the Register Pointer determines the ERF Bank while the upper nibble determines the Working Register Group within the register file (Figure 2-6).
ZS' MICROCONTROLLERS
Table2-3. ERF Bank Address
Register Pointer (FDH)
Low Nibble Hex
OOOO(B)
0
0001(B)
1
0010(B)
2
OOll(B)
3
0100(B)
4
0101(B)
5
0110(B)
6
0111(B)
7
1000(B)
8
1001{B)
9
1010(B)
A
1011(B)
B
11 OO(B)
c
Register File
za@ Standard Register File ·
Expanded Register File Bank 1 Expanded Register File Bank 2 Expanded Register File Bank 3 Expanded Register File Bank 4
Expanded Register File Bank 5 Expanded Register File Bank 6 Expanded Register File Bank 7 Expanded Register File Bank 8
Expanded Register File Bank 9
Expanded Register File Bank A Expanded Register File Bank B Expanded Register File Bank C
1101(B) 1110(B) 1111(B)
D Expanded Register File Bank D E Expanded Register File Bank E F Expanded Register File Bank F
Note: The ZS Standard Register File is equivalent to Expanded Register File Bank 0.
0 1 1 1
10 10
Working Register Group
Expanded Register
Bank
Selects ERF Bank A(H), Working Register Group 7(H)
Figure 2-6. Register Pointer (FDH) Example
The value of the lower nibble in the Register Pointer (FDH) corresponds to the ERF Bank identification. Table 2.3 shows the lower nibble value and the register file assigned to it.
2-6
The upper nibble of the register pointer selects which group of 16 bytes in the Register File, out of the full 256, will be accessed as working registers.
For example:
(See Figure 2-4)
R253 RP = OOH
If: R253 RP = OFH
;ERF Bank 0, Working Reg. Group 0. RO = Port 0 = OOH R1 = Port 1 = 01 H R2 = Port 2 = 02H R3 = Port 3 = 03H R11 =GPROBH R15 = GPR OFH
;ERF Bank F, Working Reg. Group 0. RO = PCON = OOH R1 = Reserved = 01 H R2 = Reserved = 02H R11 = SMR = OBH R15 = WDTMR = OFH
If: R253 RP= FFH
;ERF Bank F, Working Reg. Group F. OOH= PCON RO = SIO 01 H= Reserved R1 = TMR 02H= Reserved
R2 = T1 OBH= SMR
R15 = SPL OFH = WDTMR
Note that since enabling an ERF Bank (C or F) only changes register addresses OOH to OFH, the working register pointer can be used to access either the selected ERF Bank (Bank C or F, Working Register Group 0) or the ZB Standard Register File (ERF Bank 0, Working Register Groups 1 through F).
Note: When an ERF Bank other than Banko is enabled, the first 16 bytes of the Z8 Standard Register File {1/0 ports 0 to 3, Groups 4 to F) are no longer accessible (the selected ERF Bank, Registers OOH to OFH are accessed instead}. It is important to reinitialize the Register Pointer to enable ERF Bank 0 when these registers are required for use.
The SPI register is mapped into ERF Bank C. Access is easily done using the following example:
LD RP,#OCH
LD R2,#xx LD R1, #xx LD RP,#OOH
;Select ERF Bank C working ;register group 0 for access. ;access SCON ;access RXBUF ;Select ERF Bank 0 so 1/0 ports ;are again accessible.
Table 2-4. Z8 Expanded Register File Bank Layout
Expanded
Register File
Bank
ERF
F(H)
PCON, SMR, WOT., (OOH, OBH, OFH), Working Register Group 0 only implemented.
E(H)
Not Implemented (Reserved)
D(H)
Not Implemented (Reserved)
C(H)
SPI Registers: SCOMP, RXBUF,
SCON (OOH, 01H, 02H), Working Register Group 0
only implemented.
B(H)
Not Implemented (Reserved)
A(H)
Not Implemented (Reserved)
9(H)
Not Implemented (Reserved)
B(H)
Not Implemented (Reserved)
7(H)
Not Implemented (Reserved)
6(H)
Not Implemented (Reserved)
5(H)
Not Implemented (Reserved)
4(H)
Not Implemented (Reserved)
3(H)
Not Implemented (Reserved)
2(H)
Not Implemented (Reserved)
1(H)
Not Implemented
(Reserved)
O(H)
ZB Ports 0, 1, 2, 3, and General-Purpose Registers 04H to EFH, and control registers
FOH toFFH.
II
Please refer to the specific product specification to determine the above registers are implemented.
2-7
2.4 Z8 CONTROL AND PERIPHERAL REGISTERS
2.4.1 Standard Z8 Registers
The standard Z88 control registers govern the operation of the CPU. Any instruction which references the register file can access these control registers. Available control registers are:
· Interrupt Priority Register (IPR) · Interrupt Mask Register (IMR) · Interrupt Request Register (IRQ) · Program Control Flags (FLAGS) · Register Pointer (RP) · Stack Pointer High-Byte (SPH) · Stack Pointer Low-Byte (SPL)
za The uses a 16-bit Program Counter (PC) to determine
the sequence of current program instructions. The PC is not an addressable register.
Peripheral registers are used to transfer data, configure the operating mode, and control the operation of the on-chip peripherals. Any instruction that references the register file can access the peripheral registers. The peripheral registers are:
Serial 1/0 (SIO)
· Timer Mode (TMR) · Timer/Counter 0 (TO) · TO Prescaler (PREO) · Timer/Counter 1 (T1) · T1 Prescaler (PRE1) · Port 0-1 Mode (P01 M) · Port 2 Mode (P2M) ·· Port 3 Mode (P3M)
In addition, the four port registers (PO-P3) are considered to be peripheral registers.
'a- MICROCONTROLWIS
2.4.2 Expanded Z8 Registers
The expanded ZB control registers govern the operation of additional features or peripherals. Any instruction which references the register file can access these registers.
The ERF contains the control registers for WOT, Port Control, Serial Peripheral Interface (SPI), and the SMR functions. Figure 2-4 shows the layout of the Register Banks in the ERF. Register Bank C in the ERF consists of the registers for the SPI. Table 2-5 shows the registers within ERF Bank C, Working Register Group 0.
Table 2·5. Expanded Register Fiie Register Bank C, WRGroupO
Register
Register Function
Working Register
F
Reserved
R15
E
Reserved
R14
D
Reserved
R13
c
Reserved
R12
8
Reserved
R11
A
Reserved
R10
9
Reserved
R9
8
Reserved
RB
7
Reserved
R7
6
Reserved
R6
5
Reserved
R5
4
Reserved
R4
3
Reserved
R3
2
SPI Control (SCON) R2
1
SPI Tx/Rx Data (RxBuf) R1
0
SPI Compare ($COMP) RO
2-8
·21LC16
Working Register Group 0 in ERF Bank 0 consists of the registers for ZS General-Purpose Registers and ports. Table 2-6 shows the registers within this group.
7JI MICROCONlROl.t.ERS
Working Register Group 0 in ERF Bank F consists of the control registers for STOP mode, WOT, and port control. Table 2-7 shows the registers within this group.
Table 2-6. Expanded Register File Bank o,
WRGroupO
Register
F E D
c
Register Function
General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register
Working Register
R15 R14 R13 R12
B
General-Purpose Register
R11
A
General-Purpose Register
R10
9
General-Purpose Register
R9
s
General-Purpose Register
RS
7
General-Purpose Register
R7
6
General-Purpose Register
R6
5
General-Purpose Register
RS
4
General-Purpose Register
R4
3
Port3
R3
2
Port2
R2
1
Port 1
R1
0
Porto
RO
Table 2·7. Expanded Register Fiie Bank F, WRGroupO
Register
F E D
c
Register Function
WDTMR Reserved Reserved Reserved
I I Working
Register
R15 R14 R13 R12
B
SMR
R11
A
Reserved
R10
9
Reserved
R9
8
Reserved
RB
7
Reserved
R7
6
Reserved
R6
5
Reserved
R5
4
Reserved
R4
3
Reserved
R3
2
Reserved
R2
1
Reserved
R1
0
PCON
RO
The functions and applications of the control and peripheral registers are described in subsequent sections of this manual.
2-9
7J' MICROCONTROLilRS
2.5 PROGRAM MEMORY
The first 12 bytes of Program Memory are reserved for the interrupt vectors (Figure 2-7). These locations contain six 16-bit vectors that correspond to the six available interrupts. Address 12 up to the maximum ROM address consists of on-chip mask-programmable ROM. See the product data sheet for the exact program, data, register memory size, and address range available. At addresses outside the internal ROM, the ZBQll executes external program memory fetches through Port 0 and Port 1 in Address/Data mode for devices with Port 0 and Port 1 featured. Otherwise, the program counter will continue to execute NOPs up to address FFFFH, roll over to OOOOH, and continue to fetch executable code (Figure 2-7).
The internal program memory is one-time programmable (OTP) or mask programmable dependent on the specific device. A ROM protect feature prevents "dumping" of the ROM contents by Inhibiting execution of the LDC,
LDC/, LDE, and LDEI Instructions to Program Memory
In all modes. ROM look-up tables cannot be used with this feature.
The ROM Protect option is mask-programmable, to be selected by the customer when the ROM code is submitted. For the OTP ROM, the ROM Protect option is an OTP programming option.
65 535 409 6 4095
External ROM and RAM
"'- ------- -- Locationof
First Byte of
Instruction Executed
............
After RESET 12
On-Chip ROM
-
11
IRQ5
10
IRQ5
9
IRQ4
8
IRQ4
7 Interrupt
Vector 6 (Lower Byte)
5 ~
Interrupt ...J--1 ~ Vector 3 (Upper Byte)
2
IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1
1
IRQO
0
IRQO
Figure 2-7. Z8 Program Memory Map
2-10
2.6 ZS EXTERNAL MEMORY
'lJ' MICROCONTROLLERS
2.6.1 External Data Memory {/DM)
The ZS411, in some cases, has the capability to access external program memory with the 16-bit Program Counter. To access external program memory the ZS offers multiplexed address/data lines (AD7-ADO) on Port 1 and address lines (A 15-AS) on Port 0. This feature only applies to devices that offer Port 0 and Port 1.The maximum external address is FFFF. This memory interface is supported by the control lines /AS (Address Strobe}, JDS (Data Strobe), and RN/ (ReadNo/rite). The origin of the external program memory starts after the last address of the internal ROM. Figure 2-S shows an example of external program memory for the ZS.
The ZS, in some cases, can address up to 60 Kbytes of external data memory beginning at location 4096. External Data Memory may be included with, or separated from, the external Program Memory space. /OM, an optional 1/0 function that can be programmed to appear on pin P34, is
used to distinguish between data and program memory space. The state of the /OM signal is controlled by the type of instruction being executed. An LDC opcode references Program (/OM inactive) Memory, and an LOE instruction references Data (/OM active Low) Memory. The user must configure Port 3 Mode Register (P3M) bits 03 and 04 for this mode.
II
65535
External Memory
4096 4095
Not Addressable
0
Figure 2·8. External Memory Map
Note: For additional information on using external memory, see Chapter 10 of this manual. For exact memory addressing options available, see the device product specification.
2-11
(tl2JIJ:E
2.7 Z8 STACKS
zs· Stack operations can occur in either the Standard
Register File or external data memory. Under software control, Port 0-1 Mode register (FSH) selects the stack location. Only the General-Purpose Registers can be used for the stack when the internal stack is selected.
The register pair FEH and FFH form the 16-bit Stack Pointer (SP), that is used for all stack operations. The stack address is stored with the MSB in FEH and LSB in FFH (Figure 2-9).
I I- . . . . FFH LOWER....
Low
IFEH - UPPER Byte
Stack Pointer High
Figure 2-9. Stack Pointer
'II MICROCONTROWRS
The stack address is decremented prior to a PUSH operation and incremented after a POP operation. The stack address always points to the data stored on the top of the
zs· stack. The stack is a return stack for CALL instructions
and interrupts, as well as a data stack.
During a CALL instruction, the contents of the PC are saved on the stack. The PC is restored during a RETURN instruction. Interrupts cause the contents of the PC and Flag registers to be saved on the stack. The IRET instruction restores them (Figure 2-10).
When the ZS is configured for an internal stack (using the ZS Standard Register File), register FFH serves as the Stack Pointer. The value in FEH is ignored. FEH can be used as a general-purpose register in this case only.
An overflow or underflow can occur when the stack address is incremented or decremented during normal stack operations. The programmer must prevent this occurrence or unpredictable operation will result.
. .
PCL
Top of Stack -
PCL PCH
- Top of Stack
PCH FLAGS
Stack Contents After a Call Instruction
Stack Contents After an
Interrupt Cycle
Figure 2-10. Stack Operations
2-12
.2iUd:i
USER'S MANUAL
3.1 CLOCK
The ZS® derives its timing from on-board clock circuitry connected to pins XTAL1 and XTAL2. The clock circuitry consists of an oscillator, a divide-by-two shaping circuit, and a clock buffer. Figure 3-1 illustrates the clock circuitry. The oscillator's input is XTAL1 and its output is XTAL2. The clock can be driven by a crystal, a ceramic resonator, LC clock, RC, or an external clock source.
3.1.1 Frequency Control
CHAPTER3
CLOCK
El
low EMI option. When low EMI is selected, the device output drive and oscillator drive is reduced to approximately 25 percent of the standard drive and the divide-bytwo flip flop is bypassed such that the XTAL clock frequency is equal to the internal system clock frequency. In this mode, the maximum frequency of the XTAL clock is 4 MHz. Please refer to specific product specification for availability of options and output drive characteristics.
In some cases, the ZS has an EPROM/OTP option or a
Mask ROM option bit to bypass the divide-by-two flip flop
XTAL1
in Figure 3-1 . This feature is used in conjunction with the
XTAL2
osc
+2
Internal Clock
Buffer
Figure 3-1. ZS Clock Circuit
3.2 CLOCK CONTROL
In some cases, the ZS offers software control of the internal system clock via programming register bits. The bits are located in the Stop-Mode Recovery Register in Expanded Register File Bank F, Register OBH. This register selects
the clock divide value and determines the mode of StopMode Recovery (Figure 3-2). Please refer to the specific product specification for availability of this feature/register.
SMR (F)OB
I lml~lool~lool~l~lool
SCLKITCLK Divide by 16 0 OFF"" 1 ON
External Clock Divide Mode by 2 0 ~ SCLKITCLK = XTAL/2" 1 = SCLKITCLK = XTAL
· Default setting after RESET. ·· Default setting after RESET and STOP-Mode Recovery.
Figure 3·2. Stop-Mode Recovery Register (Write-Only Except 07, Which is Read-Only)
3-1
~211.£16
Z8" MICROCONTROLLERS
3.2.1 SCLK/TCLK Divide-By-16 Select (DO)
3.3 Oscillator Control
This bit of the SMR controls a divide-by-16 prescalar of SCLK!TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic).
3.2.2 External Clock Divide-By-Two (01)
This bit can eliminate the oscillator divide-by-two circuitry. When this bit is 0, SCLK (System Clock) and TCLK (Timer Clock) are equal to the external clock frequency divided by two. The SCLK{TCLK is equal to the external clock frequency when this bit is set (01 = 1). Using this bit, together with 07 of PCON, further helps lower EMI (07 (PCON) = 0, 01 (SMR) = 1). The default setting is O. Maximum fre-
= quencyis4MHzwith 01 1(Figure3-3}.
In some cases, the ZB® offers software control of the oscillator to select low EMI drive or standard drive. The selection is done by programming bit 07 of the Port Configuration (PCON) register (Figure 3-4). The PCON register is located in Expanded Register File Bank F, Register OOH.
A 1 in bit 07 configures the oscillator with standard drive, while a 0 configures the oscillator with Low EMI drive. This only affects the drive capability of the oscillator and does not affect the relationship of the XTAL clock frequency to the internal system clock (SCLK).
PCON (FH) OOH
Low EMI Oscillator 0 LowEMI 1 Standard
Figure 3·4. Port configuration register (PCON (Write-Only)
00(~
Ext er nal a ock Figure 3·3. External Clock Circuit
3-2
3.4 OSCILLATOR OPERATION
The Z89 uses a Pierce oscillator with an internal feedback R1 is a resistive component placed from output to input of (Figure 3-5). The advantages of this circuit are low cost, the amplifier. The purpose of this feedback is to bias the
large output signal, low-power level in the crystal, stability amplifier in its linear region and to provide the start-up
with respect to Vcc and temperature, and low impedances transition.
(not disturbed by stray effects).
I Capacitor C2 combined with the amplifier output resis-
One draw back is the need for high gain in the amplifier to tance provides a small phase shift. Itwill also provide some
compensate for feedback path losses. The oscillator am- attenuation of overtones.
plifies its own noise at start-up until it settles at the fre-
quency that satisfies the gain/phase requirements Ax B =
= = JV 1, where A V 1is the gain of the amplifier and B V/V0
is the gain of the feedback element. The total phase shift
around the loop is forced to zero (360 degrees). Since V1N must be in phase with itself, the amplifier/inverter provides
180 degree phase shift and the feedback element is forced
Capacitor C1 combined with the crystal resistance provides additional phase shift.
c1 and c2 can affect the start-up time if they increase
dramatically in size. As C1 and C2 increase, the start-up time increases until the oscillator reaches a point where it
to provide the other 180 degrees of phase shift.
does not start up any more.
It is recommended for fast and reliable oscillator start-up (over the manufacturing process range) that the load capacitors be sized as low as possible without resulting in overtone operation.
r------------.
I
Z8
I
:
: Vss
I
I
I
R1
Vo
I I
Figure 3-5. Pierce Oscillator with Internal Feedback Circuit
3-3
ZS' MJCROCONTROLLERS
3.4.1 Layout
Traces connecting crystal, caps, and the Z8411 oscillator pins should be as short and wide as possible. This reduces parasitic inductance and resistance. The components (caps, crystal, resistors) should be placed as close as possible to the oscillator pins of the ZB.
The traces from the oscillator pins of the IC and the ground side of the lead caps should be guarded from all other traces (clock, Vee· address/data lines, system ground) to reduce cross talk and noise injection. This is usually accomplished by keeping other traces and system ground trace planes away from the oscillator circuit and by placing a ZB device V55 ground ring around the traces/components. The ground side of the oscillator lead caps should be connected to a single trace to the ZB V58 (GND) pin. It should not be shared with any other system ground trace or components except at the Z8 device V58 pin. This is to prevent differential system ground noise injection into the oscillator (Figure 3-6).
3.4.2 Indications of an Unreliable Design
There are two major indicators that are used in working designs to determine their reliability over full lot and temperature variations. They are:
Start-up Time. If start-up time is excessive, or varies widely from unit to unit, there is probably a gain problem. C/C2 needs to be reduced; the amplifier gain is not adequate at frequency, or crystal Rs is too large.
Output Level. The signal at the amplifier output should swing from ground to Vcc· This indicates there is adequate gain in the amplifier. As the oscillator starts up, the signal amplitude grows until clipping occurs, at which point the loop gain is effectively reduced to unity and constant oscillation is achieved. A signal of less than 2.5 volts peakto-peak is an indication that low gain may be a problem. Either C1 or C2 should be made smaller or a low-resistance crystal should be used.
3.4.3 Circuit Board Design Rules
The following circuit board design rules are suggested:
· To prevent induced noise the crystal and load capacitors should be physically located as close to the Z8411 as possible.
· Signal lines should not run parallel to the clock oscillator inputs. In particular, the crystal input circuitry and the internal system clock output should be separated as much as possible.
· Vcc power lines should be separated from the clock oscillator input circuitry.
· Resistivity between XTAL1 or XTAL2 and the other pins should be greater than 10 Mohms.
3-4
XTAL 1 C1
Z8
XTAL2 C2
Clock Generator Circuit
SignalsA B
" (Parallel Traces
Must Be Avoided)
I
Signal C;--""'"T-.--t-
Board Design Example (1bp View)
D
Z8 ...-11·---~.&....<'"i 3
-=- " - (Connection to System Ground
Must Be Avoided) Figure 3-6. Circuit Board Design Rules
II
3-5
3.4.4 Crystals and Resonators
Crystals and ceramic resonators (Figure 3-7) should have the following characteristics to ensure proper oscillator operation:
Crystal Cut Mode CrystalCapacitance Load Capacitance
Resistance
AT (crystal only) Parallel, Fundamental Mode <7pF 10pF <CL< 220 pF, 15typical 100ohms max
zae MICROCONTROLLERS
In most cases, the R0 is 0 Ohms and RF is infinite. It is
determined and specified by the crystal/ceramic resona-
tor manufacturer. The R0 can be increased to decrease the
amount of drive from the oscillator output to the crystal. It can also be used as an adjustment to avoid clipping of the
oscillator signal to reduce noise. The RF can be used to
improve the start-up of the crystal/ceramic resonator. The Z8 oscillator already has an internal shunt resistor in parallel to the crystal/ceramic resonator.
Depending on operation frequency, the oscillator may
require the addition of capacitors c1 and c2 (shown in
Figures 3-7). The capacitance values are dependent on the
manufacturer's crystal specifications.
-!>o-1 XTAL1
ZB
ZB Vss
XTAL1
XTAL2
XTAL2 Figure 3-9. External Clock
D
C1
Figure 3-7. Crystal/Ceramic Resonator Oscillator
C1 C2
Figure 3·8. LC Clock
3-6
Z8' MICROCONTROLLERS
It is recommended in Figures 3-7, 3-8, and 3-9 to connect the load capacitor ground trace directly to the Vss (GND)
pin of the za@. This ensures that no system noise is injected
into the ZB clock. This trace should not be shared with any other components except at the Vss pin of the ZS.
In some cases. the ZB XTAL1 pin also functions as one of
the EPROM high-voltage mode programming pins or as a
special factory test pin. In this case, applying 2 V above
vttf~soenmtohedeXsT. ASLin1cpeitnhiwsilpl icnaaucsceetphtes
device to enter one of high voltages to enter
these respective modes, the standard input protection
diode to Vcc is not on XTAL1. It is recommended that in
applications where the ZB is exposed to much system
noise, a diode from XTAL1 to V00 be used to prevent accidental enabling of these modes. This diode will not
affect the crystal/ceramic resonator operation .
3.5 LC OSCILLATOR.
The ZB oscillator can use a LC network to generate a XTAL clock (Figure 3-8).
The frequency stays stable over Vcc and temperature. The oscillation frequency is determined by the equation:
1 Frequency= 2n(LCT)1/2
where Lis the total inductance including parasitics and CT is the total series capacitance including the parasitics.
Simple series capacitance is calculated using the following equation:
Please note that a parallel resonant crystal or resonator data sheet will specify a load capacitor value that is the series combination of C1 and C2, including all parasitics (PCB and holder).
....L= 2
cT c1
C, =2CT
Sample calculation of capacitance C1 and C2 for 5.83 MHz frequency and inductance value of 27 uH:
5.83 (10''6) =
CT= 27.6 pf Thus C1 = 55.2 pf and C2 = 55.2 pf.
3-7
3.6 RC OSCILLATOR
In some cases, the Z89 has a RC oscillator option. Please refer to the specific product specification for availability. The RC oscillator requires a resistor across XTAL1 and XTAL2. An additional load capacitor is required from the XTAL 1 input to V88 pin (Figure 3-9).
ZS' MICROCONTROLLERS
XTAL1 ZS XTAL2
Figure 3-9. RC Clock
3-8
·2iua.,
USER'S MANUAL
4.1 RESET
This section describes the Z89 reset conditions, reset timing, and register initialization procedures. Reset is generated by Power-On Reset (POR), Reset Pin, WatchDog Timer (WOT), and Stop-Mode Recovery.
A system reset overrides all other operating conditions and puts the ZB into a known state. To initialize the chip's internal logic, the /RESET input must be held Low for at least 4 internal system clock periods. The control register and ports are reset to their default conditions after a POR, a reset from the /Reset pin, or Watch-Dog Timer timeout while in RUN mode and HALT mode. The control registers
CHAPTER4
RESET-WATCH-DOG TIMER
II
and ports are not reset to their default conditions after Stop- Mode Recovery and WOT timeout while in STOP mode.
While /RESET is Low, /AS is output at the internal clock rate, /DS is forced Low, and R//W remains High. The program counter is loaded with OOOCH. 1/0 ports and control registers are configured to their default reset state.
Resetting the ZB does not effect the contents of the general-purpose registers.
4.2 /Reset Pin, Internal POR Operation
In some cases, the ZB hardware /RESET pin initializes the control and peripheral registers, as shown in Tables 4-1, 4-2, 4-3, and 4-4. Specific reset values are shown by 1 or O, while bits whose states are unknown are indicated by the letter U. The Tables 4-1, 4-2, 4-3, and 4-4 show the reset conditions for the generic ZB.
Note: The register file reset state is device dependent. Please refer to the selected device product specifications for register availability and reset state.
4-1
ft'2iLCl6
. . MICROCONTROLLERS
Table 4-1. Sample Control and Peripheral Register Reset Values (ERF Bank 0)
Register Register (HEX) Name
Bits 76543210
Comments
FO Serial 1/0
uuuuuuuu
F1
Timer Mode
F2 Counter{Timer1
F3 T1 Prescaler
F4 Counter/TimerO
F5 TO Prescaler
00000000
uuuuuuuu uuuuuuoo uuuuuuuu uuuuuuuo
Counter/Timers Stopped Single-Pass Count Mode, External Clock Source Single-Pass Count Mode
F6 Port 2 Mode
1 1 All Inputs
F7
Port3 Mode
00000000
Port 2 Open-Drain, P33-P30 Input, P37-P34 Output
F8
Port 0-1 Mode
F9
Interrupt Priority
0 00
0 1
uuuuuuuu
Internal Stack, Normal Memory Timing
FA Interrupt Request
FB Interrupt Mask
00000000
ouuuuuuu
All Interrupts Cleared Interrupts Disabled
FC Flags
U U U U U U UU
FD Register Pointer
0 0 0 0 0 0 00
FE Stack Pointer (High) U U U U U U U U
FF Stack Pointer (Low) U U U U U U U U
Program execution starts 5 to 1Oclock cycles after /RESET has returned High. The initial instruction fetch is from location COOCH. Figure 4-1 shows reset timing.
First Machine Cycle
Clock SCLK /RESET
/AS IDS R//W
4-2
Figure 4-1. Reset Timing
I
1 4 - - First Instruction Fetch
I I
'lJ' MICROCONTROUERS
After a reset, the first routine executed should be one that initializes the control registers to the required system configuration.
The /RESET pin is the input of a Schmitt-triggered circuit. Resetting the zs~will initialize port and control registers to their default states. To form the internal reset line, the output of the trigger is synchronized with the internal clock. The clock must therefore be running for /RESET to function. It requires 4 internal system clocks after reset is detected for the ZS to reset the internal circuitry. An internal pull-up, combined with an external capacitor of 1 uf, provides enough time to properly reset the ZS (Figure 4-2). In some cases, the ZS has an internal POR timer circuit that holds the ZS in reset mode for a duration (TPOR) before releasing the device out of reset. On these ZS devices, the internally generated reset drives the reset pin low for the POR time. Any devices driving the reset line must be open-drained in order to avoid damage from possible conflict during reset conditions. This reset time allows the on-board clock oscillator to stabilize.
To avoid asynchronous and noisy reset problems, the ZS is equipped with a reset filter of four external clocks (4TpC). If the external reset signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the reset is detected, an internal AST signal is latched and held for an internal
/Reset
I 1µF 10V
+SV 100kn
II
Figure 4-2. Example of External Power-On Reset CircuH
register count of 1Sexternal clocks, or for the duration of the external reset, whichever is longer. During the reset cycle, IDS is held active low while /AS cycles at a rate of the internal system clock. Program execution begins at location OOOCH, 5-10 TpC cycles after /RESET is released. For the internal Power-On Reset, the reset output time is specified as TPOR' Please refer to specific product specifications for actual values.
Register Register (HEX) Name
00 Port 0
01 Port 1
02 Port2
03 Port 3
04-EF
GeneralPurpose Registers 04-EF
Table 4-2. Sample Expanded Register File Banko Reset Values
Bits 7 6543210
Comments
u uuuuuuu u uuuuuuu u uuuuuuu
1 1 1 u u uu u uuuuuuu
Input mode, output set to push-pull Input mode, output set to push-pull Input mode, output set to push-pull Standard Digital input and output Standard Digital input and output
4-3
1.8' MICROCONTROLLERS
Table 4-3. Sample Expanded Register File Bank C Reset Values
Register Register (HEX) Name
Bits 7 6 5 4 3 2 10
Comments
00 SPI Compare (SCOMP)
01 Receive Buffer (RxBUF)
02 SPI Control (SCON)
0 0 0 0 0 0 00
u uuuuuuu uuuuoooo
Table 4-4. Sample Expanded Register Fiie Bank F Reset Values
Register Register (HEX) Name
Bits 7 6 5 4 3 2 10
Comments
00 Port Configuration (PCON)
1 1 1 10
Comparator outputs disabled on Port 3 Port 0 and 1 output is push-pull Port 0, 1, 2, 3, and oscillator with standard output drive
OB STOP-Mode Recovery 00100000 Clock divide by 16 off
(SMR)
XTAL divide by 2
POR and I OR External Reset
Stop delay on
Stop recovery level is low, STOP flag is POR
OF Watch-Dog Timer Mode (WDTMR)
UUU01101
512 TPC for WDT time out. WDT runs during STOP and HALT mode, on-board RC drives WDT
4-4
1J' MICROCONTROl.LERS
W(DWTOSTeMleRc)l -----J..-----l.-r---"iimi!~~W~O'TE'"D(l.P\S!EjLE!C"TI
CKSSouerleocet _ _ _ _ _...,_ _
(WOTMR)
XTAL -----..i...--11
oRCsc.
~RTpC CK CLR
256 512 1024 4096 TpC TpC TpC TpC WOT/POR Counter Chain
VOO 2.6V REF.
2.6V Operating + )lt>llage Del.
lntemal RESET
WOT _ _ _ _ _ ___. Stop Delay _ _ _ _ _ _ _ _ _ _ _... Select (SMR)
Figure 4·3. Example of Z8 Reset with /RESET Pin, WDT, SMR, and POR
4-5
tt'ZH.m
4Clock Filter* t-----tClear
.-----tCLK
18 Clock RESET Generator*
RESET
WOT Select (WDTMR)
CLKSource Select
(WOTMR)
XTAL
Internal RC
osc.
Vee ~\bHa2VgOpeeraDUeln.g
> - V 2VREF
From Stop Mode
Recovery Source
12 ns Glitch Filter
WOT >--------'
StopOelay Select (SMR)
WOT TAP SELECT
SmsPOR 5ms 15ms 25ms 100ms
CLK
WOT/POR Counter Chain
CLR
Figure 4-4. Example of Z8 Reset with WDT, SMR, and POR
'1J' lllCROCONTllOLLERS
Internal RESET
4-6
11' MICROCONTROUERS
4.3 Watch-Dog Timer (WOT)
The WOT is a retriggerable one-shot timer that resets the Z84t if it reaches its terminal count. When operating in the RUN or HALT modes, a WOT reset is functionally equivalent to a hardware /POR reset. The WOT is initially enabled by executing the WOT instruction and refreshed on subsequent executions of the WOT instruction. The WOT cannot be disabled after it has been initially enabled. Permanently enabled WDTs are always enabled and the WOT instruction is used to refresh it. The WOT circuit is driven by an onboard RC oscillator or external oscillator from the XTAL1 pin. The POR clock source is selected with bit 4 of the Watch-Dog Timer Mode register (WDTMR). In some cases, a ZS that offers the WOT but does not have a WDTMR register, has a fixed WOT timeout and uses the on board RC oscillator as the only clock source. Please refer to specific product specifications for selectability of timeout, WOT during HALT and STOP modes, source of WOT clock, and availability of the permanently-on WOT option.
Note: Execution of the WOT Instruction affects the Z (zero), S (sign), and V (overflow) flags.
WOTMR (F)OF
I 1~1001~1~1001~1~1001
~
~00 -
01· 10 11
- = m .5 . ,., 512TpC
15'
1024 TpC
25
2048 TpC
100
8192 TpC
WOT During HALT 0 OFF 1 ON*
...__ _ _ _ WOT During STOP
0 OFF 1 ON* . . . _ _ _ _ _ _ XTAL1nNT RC Select for WOT
0 On-Board RC · 1 XTAL
' - - - - - - - - - Reserved (Must be 0)
· Default setting after RESET t Must be 01 for Z88C03
Figure 4·5. Example of ZS Watch-Dog Timer Mode Register (Write-Only)
Note: The WDTMR register is accessible only during the first 64 processor cycles from the execution of the first instruction after Power-On Reset, Watch-Dog Reset or a Stop-Mode Recovery. After this point, the register cannot be modified by any means, intentional or otherwise. The WDTMR is a write-only register.
The WDTMR is located in Expanded Register File Bank F, register OFH. The control bits are described as follows:
WOT Time Select (01, DO). Bits 0 and 1 control a tap circuit that determines the time-out period. Table 4-5 shows the different values that can be obtained. The default value of 01 and DO are 0 and 1, respectively.
II
Table 4-5. Time-Out Period of the WOT
Time-Out of 01 DO
Typical Time-Out of Internal RC OSC
XTALClock
0
0
0
1
1
0
1
1
5ms min 15 ms min 25msmin 100msmin
256TpC 512TpC 1024TpC 4096TpC
Notes: TpC = XTAL clock cycle
= The default on reset is, DO 1 and 01 = 0.
The values given are for Vee= 5.0V. See the device product specification for exact WDTMR time-out select options available.
WOT During HALT (02). This bit determines whether or not the WOT is active during HALT mode. A 1 indicates active during HALT. The default is 1. A WDTtime out during HALT mode will reset control register ports to their default reset conditions .
WOT During STOP (03). This bit determines whether or not the WOT is active during STOP mode. Since XTAL clock is stopped during STOP Mode, unless as specified below, the on-board RC must be selected as the clock source to the POR counter. A 1 indicates active during STOP. The default is 1. If bits 03 and 04 are both set to 1, the WOT only, is driven by the external clock during STOP mode. This feature makes it possible to wake up from STOP mode from an internal source. Please refer to specific product specifications for conditions of control and port registers when the ZB comes out of STOP mode. A WOT time out during STOP mode will not reset all control registers. The reset conditions of the ports from STOP mode due to WOT time out is the same as if recovered using any of the other STOP mode sources.
4-7
Z8' MICROCONlROLLERS
Clock Source for WOT (04). This bit determines which oscillator source is used to clock the internal POR and WOT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WOT clock source is driven from the external pin, XTAL1. The default configuration of
this bit is o, which selects the internal RC oscillator.
Vcc Voltage Comparator. An on-board voltage comparator checks that Vcc is at the required level to insure correct operation of the device. Reset is globally driven if Vcc is below the specified voltage. This feature is available in select ROM Z89 devices. See the device product specification for feature availability and operating range.
Bits 5, 6 and 7. These bits are reserved.
4.4 POWER-ON·RESET (POR)
A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer (TPOR) function. The POR time allows Vcc and the oscillator circuit to stabilize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
1. Power fail to Power OK status (cold start). 2. STOP-Mode Recovery (if bit 5 of SMR=1). 3. WOT timeout.
The POR time is specified as TPOR' On ZS devices that feature a Stop-Mode Recovery register (SMR), bit5 selects whether the POR timer is used after Stop-Mode Recovery or by-passed. If bit 05 = 1then the POR timer is used. If bit 5 = 0 then the POR timer is by-passed. In this case, the Stop-Mode Recovery source must be held in the recovery state for 5 TPC or 5 crystal clocks to pass the reset signal internally. This option is used when the clock is provided with an RC/LC clock. See the device product specification for timing details.
POR (cold start) will always reset the ZS control and port registers to their default condition. If a ZS has a SMR register, the warm start bit will be reset to a 0 to indicate POR.
INTOSC
XTALOSC
POR (Cold Start)
P27 (Stop Mode)
DelayUne TPORms
18CLK Reset Filter
Chip Reset
Figure 4-6. Example of Z8 with Simple SMR and POR
4-8
USER'S MANUAL
5.1 INTRODUCTION
The ZS8 has up to 32 lines dedicated to input and output.
These lines are grouped into four S-bit ports known as Port
0, Port 1, Port 2, and Port 3. Port 0 is nibble programmable as input, output, or address. Port 1 is byte configurable as input, output, or address/data. Port 2 is bit programmable as either inputs or outputs, with or without handshake and
CHAPTER 5
1/0 PORTS
II
SPI. Port 3 can be programmed to provide timing, serial and parallel input/output, or comparator input/output.
All ports have push-pull CMOS outputs. In addition, the push-pull outputs of Port 2 can be turned off for open-drain operation.
5.1.1 Mode Registers
5.1.2 Input and Output Register$
Each port has an associated Mode Register that determines the port's functions and allows dynamic change in port functions during program execution. Port and Mode Registers are mapped into the Standard Register File as shown in Figure 5-1.
Register
Port 0-1 Mode Port3 Mode Port2 Mode
HEX Identifier
FSH P01M F7H P3M F6H P2M
Port3
Port2 Port 1 Porto
03H P3 02H P2 01H P1 OOH PO
Figure 5-1. UO Ports and Mode Registers
Each bit of Ports 0, 1, and 2, have an input register, an output register, associated buffer, and control logic. Since there are separate input and output registers associated with each port, writing to bits defined as inputs stores the data in the output register. This data cannot be read as long as the bits are defined as inputs. However, if the bits are reconfigured as outputs, the data stored in the output register is reflected on the output pins and can then be read. This mechanism allows the user to initialize the outputs prior to driving their loads (Figure 5-2).
Since port inputs are asynchronous to the ZS internal clock, a READ operation could occur during an input transition. In this case, the logic level might be uncertain (somewhere between a logic 1 and 0). To eliminate this meta-stable condition, the ZS latches the input data two clock periods prior to the execution of the current instruction. The input register uses these two clock periods to stabilize to a legitimate logic level before the instruction reads the data.
Note: The following sections describe the generic function of the
Z8 ports. Any additional features of the ports such as SPI, err.
and Stop-Mode Recovery are covered in their own section.
Because of their close association, Port and Mode Registers are treated like any other general-purpose register. There are no special instructions for port manipulation. Any instruction which addresses a register can address the ports. Data can be directly accessed in the Port Register, with no extra moves.
5-1
D' MICROCONTROll.ERS
5.2 Porto
This section deals with only the 1/0 operation of Port 0. The in this manual. Figure 5-2 shows a block diagram of Port port's external memory interface operation is covered later 0. This diagram also applies to Ports 1 and 2.
A. _8_
"
A
...
_8
Input Register
A.
"
lni:>ut Stiffer
~ ;...
.-'.)
Portl/O Lines
Read....,.... Port
8
Write Port
i----,
1--+- Internal
Ec8
TI ming
Handshake Selected
Handshake
~
Logic
4
_a_
.A Output Register
~
_ ...
__)
OB ,.uert
J_ 1-----i tDAV/ADY
1--- ~RDYi/DAV
~
Internal Bus
O~ut En le
---I
Figure S-2. Ports 0, 1, 2 Generic Block Diagram
5-2
1J' MICROCONTROLLERS
5.2.1 General 1/0 Mode
Port 0 can be an 8-bit, bidirectional, CMOS or TTL compatible 1/0 port. These eight 1/0 lines can be configured under software control as a nibble 1/0 port (P03-POO input/output
and P07-P04 input/output), or as an address port for
interfacing external memory. The input buffers can be Schmitt-triggered, level shifted, or a single-trip point buffer and can be nibble programmed. Either nibble output can be
globally programmed as push-pull or open-drain. Low EMI output buffers in some cases can be globally programmed by the software, as an OTP program option, or as a ROM
za· mask option. In some, the has Auto Latches hardwired
to the inputs. Please refer to specific product specifications for exact input/output buffer type features that are available (Figures 5-3a and 5-3b).
II
Porto
Z8
(VOorA15-A8)
Handshake Controls /D/IWO and RDYO (P32 and P35)
0 n-Drain OEN
PAD
Out
1.5 -
2.3V Hysteresis
r ----------- -,
:
: Auto latch
I
I
LI __R_~_50_0_kn_______ _JI
Figure 5-38. Port OConfiguration with Open-Drain Capablllty, Auto Latch, and Schmitt·Trigger
5-3
ZB' MICROCONTROUERS
OEN PAD
OUT TTL Level Shifter
IN Figure 5-3b. Port 0 Configuration with TTL Level Shifter
5-4
5.2.2 Read/Write Operations
In the nibble 1/0 Mode, Port 0 is accessed as generalpurpose register PO (OOH) with ERF Bank set to 0. The port is written by specifying PO as an instruction's destination register. Writing to the port causes data to be stored in the port's output register.
The port is read by specifying PO as the source register of
an instruction. When an output nibble is read, data on the external pins is returned. Under normal loading conditions this is equivalent to reading the output register. However, for Port 0 outputs defined as open-drain, the data returned is the value forced on the output by the external system.
This may not be the same as the data in the output register.
Reading a nibble defined as input also returns data on the external pins. However, input bits under handshake control return data latched into the input register via the input strobe.
The Port 0-1 Mode resister bits D,00 and Dp6 are used to configure Port 0 nibbles. The lower nibble (P00-P03) can be defined as inputs by setting bits D1 to 0 and D0 to 1, or as outputs by setting both D1 and D0 to 0. Likewise, the upper nibble (PO4-P07) can be defined as inputs by setting bits D7
too(0FiagnudreD56-t4o).1, or as outputs by setting both D8 and D7 to
5.2.3 Handshake Operation
When used as an 1/0 port, Port 0 can be placed under
handshake control by programming the Port3 Mode register bit D2 to 1. In this configuration, handshake control lines are DAV0 (P32) and ADY0 (P35) when Port Dis an input port, or ROY0 (P32) and DAV0 (P35) when Port 0 is an output port. (See Figure 5-5.)
5.3Port1
Thissectiondealsonlywiththe l/Ooperation. The port's external memory interface operation is discussed later in this manual. Figure 5-2 shows a block diagram of Port 1.
5.3.1 General UO Mode
Port 1 can be an 8-bit, bidirectional, CMOS or TTL compatible port with multiplexed Address (A7-AO) and Data (0700) ports. These eight 1/0 lines can be byte programmed as inputs or outputs or can be configured under software control as an Address/Data port for interfacing to external memory. The input buffers can be Schmitt-triggered, levelshifted, or a single-point buffer. In some cases, the output buffers can be globally programmed as either push-pull or open-drain. Low-EMI output buffers can be globally programmed by software, as an OTP program option, or as a
za· ROM Mask Option. In some cases, the can have auto
latches hardwired to the inputs. Please refer to specific product specifications for exact input/output buffer-type features available (Figures 5-6aand 5-6b).
II
Register F8H Port 0-1 Mode Register (P01M)
(Write-Only)
llD1losl
l01lool
---c_ P9a...- PO MODE
P94..- PQ,. MODE
0UTPUl3= 00
OUTPUT= 00
INPUT= 01
INPUT=01
A9-A11 =1X
A12-A15=1X
Figure 5-4. Port O110 Operation
Handshake direction is determined by the configuration
(input or output) assigned to the Port 0 upper nibble, P04POr The lower nibble must have the same 1/0 configuration
as the upper nibble to be under handshake control. Figure
5-3a illustrates the Port 0 upper and lower nibbles and the
associated handshake lines of Port 3.
Register F7H Port 3 Mode Register (P3M)
(Write-Only)
_J 0 P32 =INPUT
1~P~3~5
~~~YO
= RDYQ AVO
Figure 5-5. Port oHandshake Operation
5-5
'II' MICROCONTROLLERS
ZS
...
Port 1 (1/0 or AD7 -ADO)
Handshake Controls /DAV1 and RDY1 (P33 and P34)
Open-Drain OEN
PAD
Out
1.5..... 2.3V Hysteresis In
r ----------- I
:
: Auto Latch
I
I
IL __R_~_50_0_kn_______ .JI
Figure 5-68. Port 1 Configuration with Open-Drain Capablllty, Auto Latch, and Schmitt-Trigger
5-6
ZS' MICROCONTROLLERS
za
...
Port 1 (VO or AD7 -ADO)
Handshake Controls /DAV1 and RDY1 (P33 and P34)
El
OEN------1
OUT _ ~--------,.._ _ ___, TTL Level Shifter
PAD
Figure 5-&b. Port 1 Configuration with TTL Level Shifter
5-7
ZS' MICROCOHTROUEAS
5.3.2 Read/Write Operations
5.3.3 Handshake Operations
In byte input or byte output mode, the port is accessed as General-Purpose Register P1 (01 H). The port is written by specifying P1 as an instruction's destination register. Writing to the port causes data to be stored in the port's output register.
The port is read by specifying P1 as the source register of an instruction. When an output is read, data on the external pins is returneq. Under normal loading conditions, this is equivalent to reading the output register. However, if Port 1outputs are defined as open-drain, the data returned is the value forced on the output by the external system. This may not be the same as the data in the output register. When Port 1 is defined as an input, reading also returns data on the external pins. However, inputs under handshake control return data latched into the input register via the input strobe.
Using the Port 0-1 Mode Register, Port 1 is configured as an output port by setting bits D4 and 03 to 0, or as an input portbysetti1gD4toOandD3to1 (Figure5-8).
When used as an 1/0 port, Port 1 can be placed under handshake control by programming the Port 3 Mode register bits D4 and 03 both to 1. In this configuration, handshake control lines are DAV1 (P33) and RDY1 (P34) when Port 1 is an input port, or RDY1 (P33) and DAV1 (P34) when Port 1 is an output port. See Figures 5-6 and 5-8.
Handshake direction is determined by the configuration (input and output) assigned to Port 1. For example, if Port 1 is an output port then handshake is defined as output.
R247P3M Port 3 Mode Register
(F7, Write-Only)
I I 104103 I I I I
---c... 00 P33 = Input 01 P33 = Input 10 P33 · lllmlt 11 P33 = DAV1/RDY1
P34 =Output
= P34 = OM
P34 OM _ P34 = RDY1/DAV1
Figure 5-8. Handshake Operation
A248P01M Port ().1 Mode Register
(F8, Write-Only)
P1o - P1s MODE
= 00 = Bytf'Output
01 Byte Input 10=ADo-AD7 1L=...l:llg'1Jmpadenca ADO· AD7,
AS", OS, RIW, A8 ·A11, A12 ·A15
Figure 5-7. Port 1 VO Operation
5-8
ZS' MICROCONTROLJ.£RS
5.4 PORT2
5.4.1 General Port 1/0
Port 2 is a general-purpose port. Figure 5-2 shows a block Port 2 can be an 8-bit, bidirectional, CMOS- or TIL-
diagram of Port 2. Each of its lines can be independently compatible 1/0 port. These eight 1/0 lines can be config-
programmed as input or output via the Port 2 Mode Register ured under software control to be an input or output,
(F6H) as seen in Figure 5-9. A bit set to a 1 in P2M
configures the corresponding bit in Port2 as an input, while
a bit set to o configures an output line.
independently. Input buffers can be Schmitt-triggered, level-shifted, or a single trip point buffer and may contain Auto Latches. Bits programmed as outputs may be glo-
I
bally programmed as either push-pull or open-drain. Low-
Register F6H
Port2 Mode Register (P2M) (Write-01 ly)
EMI output buffers can be globally programmed by the software, an OTP program option, or as a ROM mask option. In addition, when the SPI is featured and enabled,
P20 functions as data-in (DI), and P27 functions as data-
out (DO). Please refer to specific product specifications
for exact input/output buffer type features available. See
Port2 Mode
0= Output 1 =Input
Figures 5-10a through 5-10c.
Figure 5-9. Port 2 1/0 Mode Configuration
5-9
'1J'I lllCROCONTROLLEAS
Open-Drain-------~
-----1 P21-P26 OE
P21-P26
PAD
P21-P26 O U T - - - - - - - - - - f
1 . 5 - 2.3 Hysteresis @ V00 = 5.0V
P21-P26 IN ---c;;."=--------------' r ----------- -,
:
: Auto Latch
I
I
IL __R_~_50_0_K_Q ______ JI
Figure S-10a. Port 2 Configuration with Open-Drain C&pability, Auto Latch, and Schmitt·Trigger
Open Drain - - - - - - - -..
OEN -"'""""""""""-t ;fJ---;::===I
PAD
OUT - - - - - - - - - - - -....- - - - _ _ , TTL Level Shilier
~ -----~ 1---------------------------...-
Figure S-10b. Port 2 Configuration with TTL Level Shifter
5-10
Open-Drain P200E SPI EN
U' MICROCONTROLLERS
P20 PAD
P201N or
-
-
-
-
-
-
<.r::rt----------------e--'
SPI DI
r ----------- I
I I
I I
Auto Latch
I
I
LI __R_~__SO_OK_O______ JI
Open-Drain
P270UT
Standard
SPI SPIDO -----~~
t P270E
Standard
SPI Active _ _ _ _ _S_P_l-a
SCON
_
0 SPI DO Enable 1 P270UT *SPI must be enabled with DO.
P27 PAD
r ----------- I
l
l Auto Latch
I
I
IL __R_~_5_00_KQ_______ JI
Figure 5·10c. Port 2 Configuration with Open-Drain Capability, Auto Latch, Schmitt-Trigger and SPI
5-11
ZS' MICROCONTROLLERS
5.4.2 Read/Write Operations
Port 2 is accessed as General-Purpose Register P2 (02H). Port 2 is written by specifying P2 as an instruction's destination register. Writing to Port 2 causes data to be stored in the output register of Port 2, and reflected externally on any bit configured as an output. Regardless of the bit inpuVoutput configuration, Port 2 is always written and read as a byte-wide port.
Port 2 is read by specifying P2 as the source register of an instruction. When an output bit is read, data on the external
pin is returned. Under normal loading conditions, this is equivalent to reading the output register. However, if a bit of Port 2 is defined as an open-drain output, the data returned is the value forced on the output pin by the external system. This may not be the same as the data In the output register. Reading input bits of Port 2 also returns data on the external pins. However, inputs under handshake control return data latched into the input register via the input strobe.
5.4.3 Handshake Operation
Port 2 can be placed under handshake control by programming bit 6 in the Port 3 Mode Register (Figure 5-11 ). In this configuration, Port 3 lines P31 and P36 are used as the handshake control lines /DAV2 and RDY2 for input handshake, or RDY2 and /DAV2 for output handshake.
Handshake direction is determined by the configuration (input or output) assigned to bit 7 of Port 2. Only those bits with the same configuration as P27 will be under handshake control. Figure 5-12 illustrates bit lines of Port 2 and the associated handshake lines of Port 3.
Register F7H Port 3 Mode Register
(Write-Only)
T
Port 2 Handshaking
o
1
P31 P31
==/IDnpAuVt2IT/RJrDii>Y2
P36 P36
==ORDutYp2u/t/D(TA.oVu2r>
Figure 5-11. Port 2 Handshake Configuration
P2o Port2 (1/0)
} Handshake Controls /DAV2 and RDY2 (P31 and P36)
Figure 5-12. Port 2 Handshaking
5-12
5.5 PORT3
5.5.1 General Port VO
Port 3 differs structurally from Port O, 1, and 2. Port 3 lines The inputs can be Schmitt-triggered, level-shifted, or single-
zae are fixed as four inputs (P33-P30) and four outputs (P37- trip point buffered. In some cases, the may have auto
I P34) Port 3 does not have an input and output register for latches hardwired on certain Port 3 inputs and Low-EMI
each bit. Instead, all the input lines have one input register, capabilities on the outputs. Please refer to specific product and all the output lines have an output register. Port 3 can specifications for exact input/output buffer type features. be a CMOS- or TTL- compatible 1/0 port. Under software Please refer to the section on counter/timers, Stop-Mode control, the lines can be configured as special control lines Recovery, serial 1/0, comparators, and interrupts for more for handshake, comparator inputs, SPI control, external information on the relationships of Port 3 to that feature. memory status, or 1/0 lines for the on-board serial and timer facilities. Figure 5-13 is a generic block diagram of Port 3.
Read
Port
Input
Input
Register .....,--._ Buffer
Port Input
Lines
P3o-P3s
Read
Port
Output
Data Return Buffer
Write
Port
Output Buffer
Port Output
Lines
P34-P3-,
Internal Bus
From Timer, Handshake Logic
or Serial 110
Figure 5-13. Port 3 Block Diagram
5-13
zae MICROCONTROLLERS
P31 (AN1)
......t - - - - P 3 0 .....t - - - - P 3 1 .....i - - - - P 3 2 .....t - - - - P 3 3
t----11~ P34
t----tl~P35
t----11~ P36
t----tl~P37
Port 3 (110 or Control)
I-I -------------------------,II IIL------------------R-~-50-0-K-'-2--II
A247= P3M
1 =Analog 0 =Digital
P30 Data Latch IRQ3
IRQ2, TIN· P31 Data Latch
P32 (AN2) P33 (REF)
From Stop-·~M:od:;:e:--------0....._ _ _ _ __
,Recovery Source
0
IRQ1, P33 Data Latch
Figure 5-14a. Port 3 Configuration with Comparator, Auto Latch, and Schmitt-Trigger
5-14
P340UT---d
I V P31~ ~.
REF (P33)
zse MICROCONTROLLERS
P34 PAD
El
P370UT---a P32--r=t>--
REF (P33)
PCON
DO
0 P34, P37 Standard Output 1 P34, P37 Comparator Output
Figure 5·14b. Port 3 Configuration with Comparator
P37 PAD
5-15
ZB' MICROCOHTROlilRS
Figure 5·14c. Port 3 Configuration with SPI and Comparator Outputs Using P34 and P35 5-16
Out
PAD
·
--c<J....___,._r~-------------::;----=r·-19 1TLLevalShift·
-'"
PCl't 3 Output Cllnl ~ration
PAD
_
I ........ !
-P-or-t-3-In-p-ut-C-o-rll-g1-r-11-U-o-n---------~
Figure 5-14d. Port 3 Configuration wHh TTL Level Shifter and Auto Latch
5-17
zae MICROCONTROLL.ERS
5.5.2 Read/Write Operations
5.5.3 Special Functions
Port 3 is accessed as a General-Purpose Register P3 (03H). Port 3 is written by specifying P3 as an instruction's destination register. However, Port 3 outputs cannot be written to if they are used for special functions. When writing to Port 3, data is stored in the output register.
Port 3 is read by specifying P3 as the source register of an instruction. When reading from Port 3, the data returned is both the data on the input pins and in the output register.
Special functions for Port 3 are defined by programming the Port 3 Mode Register. By writing Os in bit 6 through bit 1, lines P37-P30 are configured as input/output pairs (Figure 5-15). Table 5-1 shows available functions for Port 3. The special functions indicated in the figure are discussed in detail in their corresponding sections in this manual.
Port 3 input lines P33-P30 always function as interrupt requests regardless of the configuration specified in the Port 3 Mode Register.
O Port 2 Open-Drain 1 Port 2 Push-Pull
0 P31, P32 Digital Mode 1 P31, P32 Analog Mode
0 P32 = Input
P35 = Output
1 P32 = /DAV/RDY2 P35 = RDY//DAVO
00 P33 = Input
P34 = Output
01 P33 = Input
P34 =/OM
10 P33 =Input
P34 =/OM
11 P33 = /DAV1 /RDY1 P34 = RDY1 //DAV1
0 P31 = Input
P36 = Output
1 P32 = /DAV2/RDY2 P36 = ROY2//DAV2
0 P30 = Input
P37 = Output
1 P30 = Serial In P37 = Serial Out
OParityON 1 Parity OFF
Figure 5·15. Port 3 Mode Register Configuration
5-18
.2il..Cl6
Table 5·1. Port 3 Line Functions
Function
Line
Signal
Inputs
P30
Input
P31
Input
P32
Input
P33
Input
Outputs
P34
Output
P35
Output
P36
Output
P37
Output
Port 0 Handshake Input
P32
/DAVO/RDYO
Port 1 Handshake Input
P33
/DAV1/RDY1
Port 2 Handshake Input
P31
/DAV2/RDY2
Port 0 Handshake Output P35 Port 1 Handshake Output P34 Port 2 Handshake Output P36
Analog Comparator Input P31 P32 P33
RDYO//DAVO RDY1//DAV1 RDY2//DAV2
AN1 AN2 REF
Analog Comparator Output P34 P35 P37
Interrupt Requests
P30
P31
P32
P33
AN1-0UT AN2-0UT AN2-0UT
IRQ3 IRQ2 IRQO IRQ1
Serial Input
P20
DI
Serial Output
P27
DO
SPI Slave Select SPI Clock
P35
SS
P34
SK
Counter/Timer
P31
T,N
P36
TOUT
External Memory Status
P34
/OM
ZS' MICROCOHTROLLERS
5.6 PORT HANDSHAKE
When Ports 0, 1, and 2 are configured for handshake operation, a pair of lines from Port 3 are used for handshake controls. The handshake controls are interlocked to properly time asynchronous data transfers between the
za@ and a peripheral. One control line (/DAV) functions as
a strobe from the sender to indicate to the receiver that data is available. The second control line (ROY) acknowledges receipt of the sender's data, and indicates when the receiver is ready to accept another data transfer.
·
In the input mode, data is latched into the Port's input register by the first /DAV signal, and is protected from being overwritten if additional pulses occur on the /DAV line. This overwrite protection is maintained until the port data is read. In the output mode, data written to the port is not protected and can be overwritten by the ZB during the handshake sequence. To avoid losing data, the software must not overwrite the port until the corresponding interrupt request indicates that the external device has latched the data.
The software can always read Port 3 output and input handshake lines, but cannot write to the output handshake line.
The following is the recommended setup sequence when configuring a Port for handshake operation for the first time after a reset:
· Load P01 M or P2M to configure the port for input/ output.
· Load P3 to set the Output Handshake bit to a logic 1.
· Load P3M to select the Handshake Mode for the port.
Once a data transfer begins, the configuration of the handshake lines should not be changed until the handshake is completed.
Figures 5-16 and 5-17 show detailed operation for the handshake sequence.
5-19
zse MICROCONTROLLERS
/DAV (Input To ZB)
ROY (Output From ZB)
Data On Port (Input To ZB)
2
3
Valid Data
4
5
State 1. State 2.
State 3. State 4. State 5.
Port 3 Ready output is High, indicating that the ZB is ready to accept data.
The 1/0 device puts data on the port and then activates the /DAV input. This causes the data to be latched into the port input register and generates an interrupt request.
The ZB forces the Ready (ROY) output Low, signaling to the 1/0 device that the data has been latched.
The 1/0 device returns the /DAV line High in response to the ROY going Low.
The zs® software must respond to the interrupt request and read the contents
of the port in order for the handshake sequence to be completed. The ROY line goes High if and only if the port has not been read and /DAV is High. This returns the interface to its initial state.
Figure 5-16. ZS Input Handshake
5-20
ft' 2JUJ6
ZS- MICROCONTROLl.ERS
ROY (Output From Z8)
/DAV (Output From Z8)
Data On Port (Output From Z8)
2
3
4
5
II
Valid Data
State 1. State 2. State 3.
State 4. State 5.
ROY input is High indicating that the 1/0 device is ready to accept data.
The za® writes to the port register to initiate a data transfer. Writing the port
outputs new data and forces /DAV Low if and only if ROY is High.
The 1/0 device forces ROY Low after latching the data ROY Low causes an interrupt request to be generated. The ZS can write new data in response to ROY going Low; however, the data is not output until State 5.
The /DAV output from the ZS is driven High in response to ROY going Low.
The /DAV goes High, the 1/0 device is free to raise ROY High thus returning the interface to its initial state.
Figure 5·17. ZS Output Handshake
5-21
'ZS" MICROCONTROWRS
In applications requiring a strobed signal instead of the
za· interlocked handshake, the can satisfy this require-
ment as follows:
· In the Strobed Input mode, data can be latched in the Port input register using the /DAV input. The data transfer rate must allow enough time for the software to read the Port before strobing in the next character. The ROY output is ignored.
· In the Strobed Output Mode, the ROY input should be tied to the /DAV output.
Figures 5-18 and 5-19 illustrate the strobed handshake con.nections.
P2o-P27
.A
"'Y'
ZS P3e P31
/DAV~
RDvJ
1/0 Device
Figure 5-18. Output Strobed Handshake on Port 2
A_
P2o·P21 'I ZS .._/DAV P31 ~
1/0 Device
Figure 5·19. Input Strobed Handshake on Port 2
5-22
ZS- MICROCONTROLLERS
5.7 1/0 PORT RESET CONDITIONS
5.7.1 Full Reset
After a hardware reset, Watch-Dog Timer (WDT) reset, or a Power-On Reset (POR), Port Mode Registers P01M, P2M, and P3M are set as shown in Figures 5-20 through 5-22. Port 2 is configured for input operation on all bits and is set for open-drain (Figure 5-22). If push-pull outputs are desired for Port 2 outputs, remember to configure them using P3M. Please note that a WDT time-out from Stop-Mode Recovery does not do a full reset. Certain registers that are not reset after Stop-Mode Recovery will not be reset.
Register F8H Port 0·1 Mode Register (P01 M) (Write-Only)
For the condition of the Ports after Stop-Mode Recovery, please refer to specific device product specifications. In some cases, the ZBllD has the P01 M, P2M, and P3M control register set back to the default condition after reset while others do not.
All special 1/0 functions of Port 3 are inactive, with P33-P30 set as inputs and P37-P34 set as outputs (Figure 5-22).
Note: Because the types and amounts of 1/0 vary greatly among the ZS family devices, the user is advised to review the selected device's product specifications for the register default state after reset.
POO - P03 Mode 00 =Output 01 =Input 1X = A8 · A11
Stack Selection O =External 1 =Internal P10 · P17 Mode 00 = Byte Output 01 =Byte Input 10 =AdO ·Ad7 11 = High Impedance ADO· AD7, AB · A15, /AS, /OS, /RIW
External Memory Timing Normal=O Extended= 1
P04 · P07 Mode Output= 00 Input= 01 A12-A15= 1x
Figure 5-20. Port 0/1 Reset
5-23
Register F6H Port 2 Mode Register (P2M) (Write-Only)
Port 2 Mode
o =Output
1 =Input
Figure 5-21. Port 2 Reset
ZS' MICROCONTROLLERS
Register F7H Port 3 Mode Register (P3M)
(Write-Only)
o= Port 2 Open-Drain
1 = Port 2 Push-Pull
0 = P31, P32 Digital Mode 1 = P31, P32Analog Mode
0 = P32 = Input P35 = Output
1 = P32 =/DAV
00 P33 = Input P34 = Output 01 P33 = Input P34 =/OM 10 P33 =Input P34 =/OM 11 P33 = /DAV1/RDY1 P34 = RDY1//DAV1
O P31 = Input
P36 =Output
1 P31 = /DAV2/RDY2 P36 = RDY2//DAV2
o P30 = Input
P37 = Output
1 P30 =Serial In P37 = Serial Out
O Parity Off 1 Parity On
Figure 5-22. Port 3 Mode Reset
5-24
ZS' MICROCOKTROLLERS
5.8 ANALOG COMPARATORS
za@ Select devices include two independent on-chip ana-
log comparators. See the device product specification for feature availability and use. Port 3, Pins P31 and P32 each have a comparator front end. The comparator reference voltage, pin P33, is common to both comparators. In Analog Mode, the P31 and P32 are the positive inputs to the comparators and P33 is the reference voltage supplied to both comparators. In Digital Mode, pin P33 can be used as a P33 register input or IRQ1 source. P34, P35, or P37 may output the comparator outputs by software-programming the PCON Register bit DO to 1.
5.8.1 Comparator Description
Two on-board comparators can process analog signals on P31 and P32 with reference to the voltage on P33. The analog function is enabled by programming the Port 3 Mode Register (P3M bit 1). For interrupt functions during analog mode, P31 and P32 can be programmable as rising, falling, or both edge triggered interrupts (IRQ register bits 6 and bit 7).
II
Note: P33 cannot generate an external interrupt while in this mode. P33 can only generate interrupts in the Digital Mode.
Note: Port 3 inputs must be in digital mode if Port 3 Is a StopMode Recovery source. The analog comparator is disabled in STOP mode.
P31 can be used as T1N in Analog or Digital Modes, but it must be referenced to P33, when in Analog Mode.
RegisterF?H Port 3 Mode Register (P3M) (Write-Oily)
I I I I I I I I01
T
0 = Digital Mode P31, P32, P33
1 =Analog Mode P31, P32, P33
Figure 5-23. Port 3 Input Analog Selection
ERFBank F Register OOH Port Configuration Register (PCON) (Write-Only)
'"""C_ O P34, P35, or P37 Standard Outputs
1 P34, P35, or P37 Comparator Outputs
Figure 5-24. Port 3 Comparator Output Selection
5-25
'lJ' MICROCOHTROLLERS
P30 P31
P32
P33
Porta
P34
(1/0 or Control)
P35 P36 P37
Ii-------------------------,I Auto Latch
II~------------------R-·-S-O-O-K-n-J1I
R247=P3M
-----.DIG.~
1 ..Analog 0= Digital
P30Data Latch IRQ3
P31 (AN1)
-~-----· IRQ2, TIN· P31 Data Latch
P32(AN2)
P33(REF)
From Stop-·~M:ode:--------....;,..,__ _ _ _ _ IRQ1, P33 Data Laich
Recovery SOUR:&
·
;
Figure 5-25. Port Configuration of Comparator Inputs on P31, P32, and P33
5-26
P34 our----.~
r-v P31~ -+
REF(P33)
P 3 7 0 U T - - -...
P32~
REF(P33)
PCON
....__ _ _ _ _ _ _ _D0....
0 P34, P37 Standard Output 1 P34, P37 Comparator Output
Figure 5-26. Port 3 Configuration
5.8.2 Comparator Programming
Example of enabling analog comparator mode.
LO P3M, #XX.XX XX1XB
Note:X= don't care. Example of enabling analog comparator output.
LORP, #%0FH
;Sets register pointer to ;working register group 0 ;and Expanded Register ;File bank.
LO RO, #XX.XX XXX1 B ;Enables comparator ;outputs using PCOM ;Register programming.
D' MICROCONTROLL!RS
P34
II PAD
P37 PAD
5-27
Z8' MICROCONTROLLERS
5.8.3 COMPARATOR OPERATION
5.8.6. RUN Mode
After enabling the Analog Comparator mode, P33 becomes a common reference input for both comparators. The P33 (Ref) is hard wired to the reference inputs to both comparators and cannot be separated. P31 and P32 are always connected to the positive inputs to the comparators. P31 is the positive input to comparator AN1 while P32 is the positive input to comparator AN2. The outputs to comparators AN 1 and AN2 are AN 1-out and AN2-out, respectively.
The comparator output reflects the relationship between the positive input to the reference input.
P33 is not available as an interrupt input during Analog Mode. P31 and P32 are valid interrupt inputs in conjunction with P33 (Ref) when in the Analog Mode.
P31 can still be used as T1N when the analog mode is selected. If comparator outputs are desired to be outputted on the Port 3 outputs, please refer to specific products specification for priority of muxing when other special features are sharing those same Port 3 pins.
5.8.7. HALT Mode
Example: If the voltage on AN1 is higher than the voltage on RefthenAN1-outwill beatahigh state. lfvoltageonAN2 is lower than the voltage on Ref then AN2-out will be at a Low state. In this example, when the Port 3 register is read,
Bits 01 = 1 and 02 = 0. If the comparator outputs are
enabled to come out on P34 and P37, then P34 = 1 and P37 = 0. Please note that the previous data stored in P34 and P37 is not disturbed. Once the comparator outputs are deselected the stored values in the P34 and P37 register bits will be reflected on these pins again.
5.8.4 Interrupts
In the example from Section 5.8.3, P32 (AN2) will generate an interrupt based on the result of the comparison being low and the Interrupt Request Register (IRQ FAH) having bits D7=0and 06=0. If IRQD7=1 and D6=0thenbothP31 and P32 would generate interrupts.
The analog comparators are functional during HALT Mode if the Analog Mode has been enabled. P31 and P32, in conjunction with P33 (Ref) will be able to generate interrupts. Only P33 cannot generate an interrupt since the P33 input goes directly to the Ref input of the comparators and is disconnected from the interrupt sensing circuits.
5.8.8. STOP Mode
The analog comparators are disabled during STOP Mode so it does not use any current at that time. If P31, P32, or P33 are used as a source for Stop-Mode Recovery, the Port 3 Digital Mode must be selected by setting bit 01 =0 in the Port 3 Mode Register. Otherwise in STOP Mode, the P31, P32, and P33 cannot be sensed. If the Analog Mode was selected when entering STOP Mode, it will still be enabled after a valid SMR triggered reset.
5.8.5. Comparator Definitions
5.8.5.1. VICR
The usable voltage range for both positive inputs and the reference input is called the common mode voltage range
(V1cR). The comparator is not guaranteed to work if the inputs are outside of the V1cR range.
5.8.5.2. VOFFSET
The absolute value of the voltage between the positive input and the reference input required to make the comparator output voltage switch is the input offset voltage (Voffset). If AN1 is 3.000V and Ref is 3.001V when the comparator output switches states then the Voffset = 1mV.
5.8.5.3. llO
For CMOS voltage comparator inputs, the input offset current (110) is the leakage current of the CMOS input gate.
5-28
.,, MICROCONTROUERS
5.9 OPEN-DRAIN CONFIGURATION
All Z8s can configure Port 2 to provide open-drain outputs by programming the Port 3 Mode Register (P3M) bit DO=O.
Register F7H Port 3 Mode Register (Write Only)
lo1losloslo4loalo2lo1lool
--c._ Port 2 Configuration
= 0 Pull-Ups Open-Drain
1 = Pull-Ups Active
Figure 5·27. Port 2 Configuration
Other Z8s that have a Port Configuration Register (PCON) that can configure Port 0 and Port 1 to provide open-drain outputs. The PCON Register is located in Expanded Register File (ERF) Bank F, Register OOH. See Figure 5-28.
dently. Other Z8s may offer a ROM Mask or OTP programming option to configure the ZS Ports and oscillator globally to a Low-EMI mode (where the XTAL frequency is set equal to the internal system clock frequency.
I I Use of the Low EMI feature results in:
· The output pre-drivers slew rate reduced to 10 ns (typical).
· Low EMI output drivers have resistance of 200 Ohms (typical).
· Low EMI Oscillator. · All output drivers are approximately 25 percent of the
standard drive. · Internal SCLK/TCLK = XTAL operation limited to a
maximum of 4 MHz - 250 ns cycle time, when Low EMI Oscillator is selected and system clock (SCLK=XTAL, SMR Reg. Bit 01=1).
PCON (FH) OOH
jmj~j~j~joojooj~jooj
~L
ComparatorOUlpUIPort3 0 P34. PS7 Standard Output' 1 P34. PS7Co-Ootput
0 Port 1 Open Drain
1 Port 1 .....h-pull - · 0 Port 0 Open Drain 1 Port 0 Puall-pu!IActlve·
0 Port 0 Low EMI
1 Port 0 Slanda.r ....__ _ _ _ 0 Port1 LI>wEMI
1 Port 1 Standard" .____ _ _ _ _ 0 Port2 LowEMI
1 Port2Standanr
' - - - - - - - - 0 Port3 LowEMI 1 Port3Slandanr
· Default SettlngAlter Re8111
Low EMI Oodll0 LawEMI 1 Standanl'
For Z8s having the PCON register feature, the following bits control the Low EMI options:
· Low EMI Port O(03). Port Ocan be configured as a Low EMI Port by resetting this bit (D3=0) or configured as a Standard Port by setting this bit (D3=1). The default value is 1.
· Low EMI Port 1 (04). Port 1 can be configured as a Low EMI Port by resetting this bit (D4=0) or configured as a Standard Port by setting this bit (D4=1). The default value is 1.
· Low EMI Port 2 (05). Port 2 can be configured as a Low EMI Port by resetting this bit (D5=0) or configured as a Standard Port by setting this bit (D5=1). The default value is 1.
Figure 5-28. Port Configuration Register (PCON) (Write-Only)
Port1 Open-Drain(D1).Port1 canbeconfiguredasopen-drainby resettingthisbit(D1 =O)oroonliguredaspush-pullactivebysettinglhis bit(D1=1).Thedefaultvalueis1.
Port 0 Open Drain (02). Port 0 can be configured as opendrain by resetting this bit(D2=0) or configured as push-pull active by setting this bit (D2= 1). The default value is 1.
5.10 LOW EMI EMISSION
Some Z8s can be programmed to operate in a Low EMI Emission Mode using the Port configuration register (PCON). The PCON register allows the oscillator and all I/ O ports to be programmed in the Low-EM I Mode indepen-
· Low EMI Port 3 (06). Port 3 can be configured as a Low EMI Port by resetting this bit (D6=0) or configured as a Standard Port by setting this bit (D6=1). The default value is 1.
· Low EMI OSC (07). This bit of the PCON Register controls the Low EMI oscillator. A 1 in this location configures the oscillator with standard drive, while a O configures the oscillator with low noise drive. The LowEMI mode will reduce the drive of the oscillator (OSC). The default value is 1. XTAU2 mode is not effected by this bit.
Note: The maximum external clock frequency is 4 MHz when running in the Low EMI oscillator mode.
Please refer to the selected device product specification for availability of the Low EMI feature and programming options.
5-29
U' MICROCOHTROUERS
5.11 INPUT PROTECTION
All CMOS ROM Z8s have 1/0 pins with diode input protection. There is adiode from the 1/0 pad to Vcc and to Vss· See Figure 5-29A.
On CMOS OTP EPROM Z8's, the Port 3 inputs P31, P32, P33 and the XTAL 1 pin have only the input protection diode from pad to Vss· See Figure 5-298.
PAD
PAD
Figure 5-29a. Diode Input Protection
Figure 5-29b. OTP Diode Input Protection
The high-side input protection diodes were removed on these pins to allow the application of +12.5V during the various OTP programming modes.
For better noise immunity in applications that are exposed to system EMI, a clamping diode to V00 from these pins may be required to prevent entering the OTP programming mode or to prevent high voltage from damaging these pins.
5-30
5.12. CMOS ZS AUTO LATCHES
1/0 port bits that are configurable as inputs are protected against open circuit conditions using Auto Latches. An Auto Latch is a circuit which, in the event of an open circuit condition, latches the input at a valid CMOS level. This
inhibits the tendency of the input transistors to self-bias in the forward active region, thus drawing excessive supply current. A simplified schematic of the CMOS Z8 l/O circuit is shown in Figure 5-30.
Open-Drain
II
OE
Data Out
vDD
Data In
Figure 5-30. Simplified CMOS Z8 VO Circuit
The operation of the Auto Latch circuit is straight-forward. Assume the input pad is latched at +5V (logic 1). The inverter G1 inverts the bit, turning the P-channel FET ON and the N-channel FET OFF. The output of the circuit is effectively shorted to V00, returning +5V to the input. If the pad is then disconnected from the +5V source, the Auto Latch will hold the input at the previous state. If the device is powered up with the input floating, the state of the Auto Latch will be at either supply, but which state is unpredictable.
There are four operating conditions which will activate the Auto Latches. The first, which occurs when the input pin is physically disconnected from any source, is the most obvious. The second occurs when the input is connected to the output of a device with tri-state capability.
The Auto Latch will also activate when the input voltage at the pin is not within 200 microV or so of either supply rail. In this case, the circuit will draw current, which is not significant compared to the Ice operating current of the device, but will increase lcc2 STOP Mode current of the device dramatically.
The fourth condition occurs when the 1/0 bit is configured
as an output. Referring to the output section of Figure 5-30, there are two ways of tri-stating the port pin. The first is by configuring the port as an input, which disables the /OE signal turning both transistors off. The second can be achieved in output mode by writing a "1" to the output port, then activating the open drain mode. Both transistors are again off, and the port bit is in a high impedance state. The Auto Latches then pull the input section toward V00.
5-31
Auto Latch Model:
The Auto Latch's equivalent circuit is shown in Figure 5-31. When the input is high, the circuit consists of a resistance Rp from V00 (the P-channel transistor in its ON state) and a much greater resistance Rh to GND. Current lao flows from V00 to the output. When the input is low, the circuit may be modeled as a resistance Rp from GND (the Nchannel transistor in the ON state) and a much greater
resistance Rh to V00· Current lao now flows from the input to ground. The Auto Latch is characterized with respectto
lao, so the equivalent resistance Rp is calculated accord-
ing to RP= (V00-V1N)/lao. The worst case equivalent resistance Rp (min) may be calculated at the worst case input
voltage, Vi= Vih(min).
Voo
y
Rp Data In Logic 1
VDo
y
Data In LogicO
Figure 5-31. Auto Latch Equivalent Circuit
5-32
'1J' MICROCONTROLLERS
Design Considerations:
For circuits in which the Auto Latch is active, consideration should be given to the loading constraints of the Auto Latches. For example, with weak values of V,N' close to Vih (min) or Vil (max), pullup or pull-down resistances must be calculated using Ref = R/Rp. For best case STOP mode operation, the inputs should be within 200 mV of the supply rails.
In output mode, if a port bit is forced into a tri-state condition, the Auto Latches will force the pad to VDD" If there is an external pulldown resistor on the pin, the voltage at the pin may not switch to GND due to the Auto Latch. As shown in Figure 5-32, the equivalent resistance of the Auto Latch and the external pulldown form a voltage divider, and if the
external resistor is large, the voltage developed across it will exceed Vil(max). For worst case:
Vil(max > VDD [Rext/(Rext+Rp)] Rext(max) = ((Vil(max)NDD)Rp]/[1-(Vil(max)NDD)]
For VDD = 5.0V and lao = 5 uA we have Vih(max) =0.BV: Rext(max) = (0.16/1M)/(1-0.16) = 190 K ohms.
II
Rp increases rapidly with VDD' so increased VDD will relax the requirement on Rext.
In summary, the CMOS ZS Auto Latch inhibits excessive current drain in ZB devices by latching an open input to eitherVDD or GND. The effect of the Auto Latch on the 1/0 characteristics of the device may be modeled by a current lao and a resistor Rp, whose value is VDJlao.
y
~ D-
rV1H(mlo.)
5:' REXT
....
Figure 5-32. Effect of Pulldown Resistors on Auto Latches
5-33
USER'S MANUAL
6.1 INTRODUCTION
The Z89 provides up to two 8-bit counter/timers, TO and T1, each driven by its own 6-bit prescaler, PREO and PRE1 {Figure 6-1 ). Both counter/timers are independent of the processor instruction sequence, that relieves software from time-critical operations such as interval timing or event counting. Some MCUs offer clock scaling using the SMR register. See the device product specification for clock available options. The following description is typical.
CHAPTER 6
COUNTER/TIMERS
II
Each counter/timer operates in either Single-Pass or Continuous mode. Atthe end-of-count, counting either stops or the initial value is reloaded and counting continues. Under software control, new values are loaded immediately or when the end-of-count is reached. Software also controls the counting mode, how a counter/timer is started or stopped, and its use of 1/0 lines. Both the counter and prescaler registers can be altered while the counter/timer is running.
Internal Data Bus
Write
Read
PREO lnttlal \tilue
Register
TO Initial \tilue
Register
TO Current \tilue
Register
Internal Clock External Clock
Clock Logic
lntemal Clock Gated Clock Triggered Clock
TIN P31
6-Btt Down Counter
8-blt Down Counter
IRQ4
TOUT P36
6·Blt Dcwn Counter
8-Btt Down Counter
IRQ5
PRE1 Initial \tilue
Register
Tt Initial Velue
Register
T1 Current \tilue
Register
Write
Read
lntemal Data Bus
Figure 6-1. Counter/rimer Block Diagram
6-1
11' MlCROCONTROLLERS
Counter/timers 0 and 1 are driven by a timer clock generated by dividing the internal clock by four. The divide-byfour stage, the 6-bit prescaler, and the 8-bit counter/timer form a synchronous 16-bit divide chain. Counter/timer 1 can also be driven by a external input (T1N) using P31. Port 3 line P36 can serve as a timer output (Tour> through which TO, T1 , or the internal clock can be output. The timer output will toggle at the end-of-count.
The counter/timer, prescaler, and associated mode registers are mapped into the register file as shown in Figure
6-2. This allows the software to treat the counter/timers as
general-purpose registers, and eliminates the need for special instructions.
PresRca2l4e5rPoRREeOgister
(%F5; W~te ·Only)
1~1~1~1~1~1~1~1~1
L
C0 o=uInnt MSolndaele Pass 0 1 = 1 Modulo-n
Reserved (Must be O)
Prescaler Modulo (Range: 1·64 Decimal 01-00 HEX)
Figure 6-3. Prescaler ORegister
6.2 PRESCALERS AND COUNTER/TIMERS
The prescalers, PREO (FSH) and PRE1 (F3H), each consist of an 8-bit register and a 6-bit down-counter as shown in Figure 6-1. The prescaler registers are write-only registers. Reading the prescalers returns the value FFH. Figures 6-3 and 6-4 show the prescaler registers.
The six most significant bits (D2-D7) of PREO or PRE1 hold the prescalers count modulo, avalue from 1to 64 decimal. The prescaler registers also contain control bits that specify TO and T1 counting modes. These bits also indicate whether the clock source for T1 is internal or external. These control bits will be discussed in detail throughout this chapter.
The counter/timer registers, TO (F4H) and T1 (F2H), each consist of an 8-bit down-counter, a write-only register that holds the initial count value, and a read-only register that holds the current count value (Figure 6-1 ). The initial value can range from 1 to 256 decimal (01 H,02H, .. ,OOH). Figure 6-5 illustrates the counter/timer registers.
DEC
HEX ldenllflers
247
Port3Mode
F7
245
To Prescaler
FS
244 Timer/CountelO
F4
243
T1 Prescaler
F3
242 nmer/Counter1
F2
241
Timer Mode
F1
Register FSH Port 0·1 Mode Register (P01 M)
(Write-Only)
l ---C:. ID1fDel I
ID1IDol
PO · PO MODE
P91L· PQa MODE OUTPUT= 00
oi'.flrPUT= 00 INPUT= 01
AsINPUT= 01 -A11 = 1X
A12·A15=1X
Figure 6-4. Prescaler 1 Register
R242T1 Countermmer 1 Register (%F2; Read/Write Only)
R244TO Countermmer O Register
(%F4; Read/Write Only)
1~1~1~1~1~1~1~1~1
c
Initial value when written
(Range 1·256 decimal, 01-00 HEX)
current value when read
Figure 6·5. Counter I Timer 0 and 1 Registers
Figure 6-2. Counter/Timer Register Map 6-2
6.3 COUNTER/TIMER OPERATION
Under software control, counter/timers are started and stopped via the Timer Mode Register (TMA,F1 H) bits D0-D3 (Figure 6-6). Each counter/timer is associated with a Load bit and an Enable Count bit.
6.3.1 Load and Enable Count Bits
Setting the Load bit (D0 for TO and D2 for T1) transfers the initial value in the prescaler and the counter/timer registers into their respective down-counters. The next internal clock resets bits D0 and 0 2 to 0, readying the Load bit for the next load operation. New values may be loaded into the downcounters at any time. If the counter/timer is running, it continues to do so and starts the count over with the new value. Therefore, the Load bit actually functions as a software re-trigger.
The counter timers remain at rest as long as the Enable Count bits are 0. To enable counting, the Enable Count bit (D1 for TO and D3 forT1)mustbesetto1. Counting actually
starts when the Enable Count bit is written by an instruc-
tion. The first decrement occurs four internal clock periods after the Enable Count bit has been set. If T1 is configured
to use an external clock, the first decrement begins on the next clock period. The Load and Enable Count bits can be set at the same time. For example, using the instruction:
II
ORTMR,#03H
sets both DO and D1 of the TMR. This loads the initial values of PREO and TO into their respective counters and starts the count after the M2T2 machine state after the operand is fetched (Figure 6-7).
R241 TMR Timer Mode Realstar (% F1; Read/Write)
= O No Function = 1 LoedT0
= o Disabler0 Count
1 = Enable T0 Count
= o · No Function
1 LoedT1
= 0
1
=
DEnisaabblleeTT11CCoouunntt
Figure 6-6. Timer Mode Register
R243PRE1 Prescaler 1 Register (%F3; Write-Only)
PresRca2l4e6rPoRREeOgister
(%F5; Write-Only)
Count Mode
= O T1 Single Pass = 1 T1 Moclulo-n
Figure 6-7. Starting The Count
I~ I~ I~ I~ I
I T '"[__ lnl~lnlnl~lnlnl~lmlnl~lml First Decrement Occurs Four Clock Periods Later ' - - - - - - - - - TMR Is Written, Countermmer is loaded ...__ _ _ _ _ _ _ _ _ _ _ _ _ _ _ #03H is Fetched
Figure 8-8. Counting Modes
6-3
ZS' MicRocoNrRou.eRS
6.3.2 Prescaler Operations
During counting, the programmed clock source drives the 6-bit Prescaler Counter. The counter is counted down from the value specified by bits of the corresponding Prescaler Register, PREO (bit 7 to bit 2) or PRE1 (bit 7 to bit 2). (Figures 6-3, 6-4). When the Prescaler Counter reaches its end-of-count, the initial value is reloaded and counting continues. The prescaler never actually reaches 0. For example, if the prescaler is set to divide-by-three, the
count sequence is:
The time interval (i) until end-of-count, is given by the equation:
i=tXpXv
in which:
t = four divided by the internal clock frequency.
3-2-1-3-2-1-3-2-1-3 ...
Each time the prescaler reaches its end of count a carry is generated, that allows the Counter/Timer to decrement by one on the next timer clock input. When the Counter/Timer and the prescaler both reach the end-of-count, an interrupt request is generated (IRQ4 for TO, IRQS for T1 ). Depending on the counting mode selected, the Coun,ter/Timer will either come to rest with its value at OOH (Single-Pass Mode) or the initial value will be automatically reloaded and counting will continue (Continuous Mode). The counting modes are controlled by bit 0 of PREO and bit 0 of PRE1. (Figure 6-8). A 0, written to this bit configures the counter for Single-pass counting mode, while a 1 written to this bit configures the counter for Continuous mode.
The internal clock frequency defaults to the external clock source (XTAL, ceramic resonator, and others) divided by 2. Some Z81111 microcontrollers allow this divisor to be changed via the Stop-Mode Recovery register. See the product data sheet for available clock divisor options.
Note that tis equal to eight divided-by-XTAL frequency of the external clock source for T1 (external clock mode only).
p =the prescaler value (1 - 63) for T0 and T1·
The minimum prescaler count of 1 is achieved by loading 000001 xx. The maximum prescaler count of 63 is achieved by loading 111111xx.
The Counter/Timer can be stopped at any time by setting the Enable Count bit to 0, and restarted by setting it back to 1. The Counter/Timer will continue its count value at the time it was stopped. The current value in the Counter/Timer can be read at any time without affecting the counting operation.
Note: The prescaler registers are write-only and cannot be read.
v=theCou1termmervalue(1-256}
Minimum duration is achieved by loading 01 H(1prescaler output count). maximum duration is achieved by loading OOH (256 prescaler outputs counts).
It should be apparent the prescaler and counter/timer are true divide-by-n counters.
New initial values can be written to the prescaler or the Counter/Timer registers at any time. These values will be transferred to their respective down counters on the next load operation. If the Counter/Timer mode is Continuous, the next load occurs on the timer clock following an endof-count. New initial values should be written before the desired load operation, since the prescalers always effectively operate in Continuous count mode.
6-4
ft'21LCE
6.4 Tour Modes
The Timer Mode Register TMR (F1 H ) (Figure 6-9), is used in conjunction with the Port 3 Mode Register P3M (F7H) (Figure 6-10) to configure P36 for Tour operation for TO and
"lB' MICROCONTROLLERS
T1 . In order for ToLJT to function, P36 must be defined as an output line by setting P3M bit 5 to 0. Output is controlled by one of the counter/timers (TO or T1 ) or the internal clock.
Register F1 H Timer Mode Register (TMR) (Read/Write)
T
T1031
lool o -c__ = No Function
1 =Load TO
....___ _ _ _ _ O=Disable T1 Count
1 = Enable T1 Count
TouIModes
g~: ffi~ttOff
10=T1 Out 11 = Internal Clock Out
II
Figure 6-9. Timer Mode Register {TOUT Operation)
Register F7H
Port 3 Mode Register (P3M)
(Write-Only)
I I Ios I I
T
= = o P31 = Input ffit.1). P36 = Output CT.our)
1 P31 /DAV2/RDY2 P36 RDY2//0AV2
Figure 6-10. Port 3 Mode Register {Tour Operation)
6-5
'1' MICROCOHIROLIBIS
The counter/timer to be output is selected byTMR bit 7 and bit 6. TO is selected to drive the T0 UT line by setting bit) 7 to 0 and bit 6 to 1. Likewise, T1 is selected by setting bit 7 and bit 6 to 1 and 0, respectively. The counter/timer T0UT mode is turned off by setting TMR bit and bit 6 both to 0, freeing P36 to be a data output line.
Tour is initialized to a logic 1whenever the TMR Load bit (bit 0 for TO or bit 1 for T1) is set to 1. The T configuration timer load, and Timer Enable Count bits°for the counter/ timer driving the ToUT pin can be set at the same time. For example, using the instruction:
OR TMR,#43H
· Configures TO to drive the TOUT pin (P36).
· Sets the P36 Tout pin to a logic 1 level.
At end-of-count, the interrupt request line (IRQ4 or IRQ5), clocks a toggle flip-flop. The output of this flip-flop drives the TOUT line, P36. In all cases, when the selected counter/ timer reaches its end-of-count, TOUT toggles to its opposite state (Figure 6-11). If, for example, the counter/timer is in Continuous Counting Mode, Tout will have a 50 percent duty cycle output. This duty cycle can easily be controlled by varying the initial values after each end-of-count.
The internal clock can be selected as output instead of TO or T1 by setting TMR bit 7 and bit 6 both to 1. The internal clock ()<TAL frequency/2) is then directly output on P36 (Figure 6-12).
While programmed as TOUT' P36 cannot be modified by a
zs· write to port register P3. However, the software can
examine the P36 current output by reading the port register.
· Loads the initial PREO and TO levels into their respective counters and starts the counter after the M2T2 machine state after the operand is fetched.
(TO End-of-CoIRuQnt4) - - -
+2
IRQS __JTMR
(T1 End-of-Count)
07 06=10
Figure ls-11. TO and T1 Output Through Tour
Internal Clock
osc
+2
I
I
I
=OJ
Figure 6-12. Internal Clock Output Through TouT
6-6
zse MICROCOKTROLLERS
6.5 TIN MODES
The Timer Mode Register TMR (F?H} (Figure 6-13) is used in conjunction with the Prescaler Register PRE1 (F?H) (Figure 6-14) to configure P31 as T,w T,N is used in conjunction with T1 in one of four modes:
· External Clock Input
· Gated Internal Clock
· Triggered Internal Clock
· Retriggerable Internal Clock
Note: The T,N mode is restricted for use with timer 1 only. To enable the T,N mode selected (via TMR bits 4- 5), bit 1 of PRE1 must be set to 1.
The counter/timer clock source must be configured for external by setting the PRE1 Register bit 2 to 0. The Timer Mode Register bit5 and bit 4 can then be used to select the desired T,N operation.
For T1 to start counting as a result of a T,N input, the Enable Count bit (bit 3 in TMR) must be set to 1. When using T,N as an external clock or a gate input, the initial values must be loaded into the down counters by setting the Load bit (bit 2 in TMR) to a 1 before counting begins. In the descriptions of T,N that follow, it is assumed the programmer has performed these operations. Initial values are automatically loaded in Trigger and Retrigger modes so software loading is unnecessary.
II
Register F1 H Timer Mode Register (TMR)
(Read/Write)
= TIN Modes
Oo External Clock Input 01 = Gate Input 10 =Trigger Input (Non-Retriggerable) 11 =Trigger Input (Retriggerable)
Figure 6-13. Timer Mode Register (T,N Operation)
Register FSH Prescaler 1 Register (PRE1} (Write-Only}
l~lool~l~lmlool~lool
T
Clock Source
O = T1 Internal
1 = T1 External
Figure 6-14. Prescaler 1 Register (T,N Operation)
6-7
ZS' MICROCONTROUERS
It is suggested that P31 be configured as an input line by
setting P3M Register bit5 to 0, although T1Nis still functional if P31 is configured as a handshake input .
Each High-to-Low transition on T1N generates an interrupt request IRQ2, regardless of the selected T1N mode or the enabled/disabled state of T1. IRQ2 must therefore be masked or enabled according to the needs of the application.
6.5.1 External Clock Input Mode
The T1N External Clock Input Mode (TMR bit 5 and bit4 both set to 0) supports counting of external events, where an
event is considered to be a High-to-Low transition on T1N (Figure 6-15).
Note: See the product data sheet for the minimum allowed T,N external clock input period (TP T,N}.
TMR
:-1__ I.05-04=00
c~6~k _I Ps_1 .,..-o-"""11.--0-..,I 1 . _P_R_E_1---T-1-~ 1~
JlJL
lotemal
i
i
~ IRQ2
Clock
Figure 6-15. External Clock Input Mode
6-8
ZS- MICROCONTROLLERS
6.5.2 Gated Internal Clock Mode
The T1NGated Internal Clock Mode (TMR bit 5 and bit 4 set to 0 and 1 respectively) measures the duration of an
external event. In this mode, the T1 prescaler is driven by the internal timer clock, gate by a High level on T1N (Figure 6-16). T1 counts while T1N is High and stops counting while
T1N is Low. Interrupt request IRQ2 is generated on the Highto-Low transition of T1N signalling the end of the gate input. Interrupt request IRQ5 is generated if T1 reaches its end-
of-count.
osc
+2
1---e-----..- Internal Clock
II
+4
PRE1
T1
IRQ5
TIN
Gate
D
D .__..-------------------IRQ2
Figure 6-16. Gated Clock Input Mode
6-9
't'2iUl6
ZS' MICROCONTROLLERS
6.5.3 Triggered Input Mode
The T1N Triggered Input Mode (TMR bits 5 and 4 are set to
1 and 0 respectively) causes T1 to start counting as the
result of an external event (Figure 6-17). T1 is then loaded
and clocked by the internal timer clock following the first
High-to-Low transition on the T1N input. Subsequent T1N transitions do not affect T1. In the Single-Pass Mode, the
Enable bit is reset whenever T1 reaches its end-of-count. Further T1N transitions will have no effect on T1 until software sets the Enable Count bit again. In Continuous mode, once T1 is triggered counting continues until software resets the Enable Count bit. Interrupt request IRQ5 is generated when T1 reaches its end-of-count.
osc
+2
TIN Trigger
P31
Sl.
D
D
Internal Clock
Edge Trigger
1.
+4
TMR 0 5-04 = 11
PRE1
T1
Figure 6·17. Triggered Clock Mode
IRQ5 IRQ2
6-10
ZIJ' MICROCONTROUERS
6.5.4 Retriggerable Input Mode
The T,N Retriggerable Input Mode (TMR bits 5 and 4 are set to 1) causes T1 to load and start counting on every occurrence of a High-to-Low transition on T,N (Figure 6-17). Interrupt request IRQS will be generated if the programmed time interval (determined by T1 prescaler and counter/timer register initial values) has elapsed since the last High-to-Low transition on T,N. In Single-Pass Mode, the end-of-count resets the Enable Count bit. Subsequent
T,N transitions will not cause T1 to load and start counting until software sets the Enable Count bit again. In Continuous Mode, counting continues once T1 is triggered until software resets the Enable Count bit. When enabled, each High-to-Low T,N transition causes T1 to reload and restart counting. Interrupt request IRQS is generated on every end-of-count.
El
6.6 CASCADING COUNTER/TIMERS
For some applications, it may be necessary to measure a time interval greater than a single counter/timer can measure. In this case, T,N and Tour can be used to cascade TO and T1 as a single unit (Figure 6-18). TO should be configured to operate in Continuous mode and to drive Tour· T,N should be configured as an external clock input to T1 and wired back to Tour On every other TO end-of-count, Tour undergoesaHigh-to-LowtransitionthatcausesT1 tocount.
T1 can operate in either Single-Pass or Continuous mode.
When the T1 end-of-count is reached, interrupt request IRQS is generated. Interrupt requests IRQ2 (T,N High-toLow transitions) and IRQ4 {TO end-of-count) are also generated but are most likely of no importance in this configuration and should be disabled.
PREO
TO
IRQ4
Figure 6-18. Cascaded Counter I Timers
PRE1
T1
IRQS
IRQ2
6-11
6.7 RESET CONDITIONS
ZS' MICROCONTROLL.ERS
After a hardware reset, the counter/timers are disabled and the contents of the counter/timer and prescaler registers are undefined. However, the counting modes are configured for Single-Pass and the T1 clock source is set for
external. T1N is set for External Clock mode, and the Tour mode is off. Figures 6-19 through 6-22 show the binary reset values of the Prescaler, Counter{fimer, and Timer Mode registers.
R242T1 Countermmer 1 Register (%F2; Read/Write Only)
CounterRm2m4e4rToORegister
(%F4; Read/Write Only)
lulululululululul
L
Initial value when written (Range 1-256 decimal, 01·00 HEX) current value when read
Figure 6-19. Counter /Timer Reset
R243 PRE1 Prescaler 1 Register (%F3; Write-Only)
--1 L Iu Iu Iu lu Iu Iu Io I oI
Count Mode
0 1
==TT11
Single Pass Modulo·n
= Clock Source
1 0
=
T1 T 1
Internal External
(TIN)
Prescaler Modulo (Range: 1·64 Decimal 01-00HEX)
Figure 6-20. Prescaler 1 Register Reset
6-12
R245 PREO Prescaler O Register
(o/oF5; Write Only)
I ujujujulujujujo I
I L !n Count Mode 0 = Single Pass 0 1 = 1 Modulo-n Reserved (Must be O)
Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
Figure 6·21. Prescaler 0 Reset
zse MICROCONTROLLERS
II
olololololo lolo I -,--- - , - -r~"'[__ o = No Function
1=LoadT0
o = Disable T Count
1 = Enable Tgcount
O = No Function 1=LoadT1
' - - - - - - O = DisableT1 Count 1 = Enable T1 Count
.___ _ _ _ _ _ _ TIN Modes:
External Clock Input = 00 Gate Input = 01 Trigger Input = 1o (Non-retriggerrable) Trigger Input = 11 (Retriggerable)
' - - - - - - - - - - - - TouTModes: TouTOFF=OO T0 0UT=01 T1 OUT=10 Internal Clock OUT= 11
Figure 6-22. Timer ModeRBegister Reset
6-13
USER'S MANUAL
7.1 INTRODUCTION
The Z~ microcontroller allows six different interrupt levels from a variety of sources; up to four external inputs, the on-
chip Counter/Timer(s), software, and serial 1/0 peripher-
als. These interrupts can be masked and their priorities set by using the Interrupt Mask and the Interrupt Priority Registers. All six interrupts can be globally disabled by resetting the master Interrupt Enable, bit 7 in the Interrupt Mask Register, with a Disable Interrupt (DI) instruction. Interrupts are globally enabled by setting bit 7 with an Enable Interrupt (El) instruction.
CHAPTER 7
INTERRUPTS
II
There are three interrupt control registers: the Interrupt Request Register (IRQ), the Interrupt Mask register (IMR), and the Interrupt Priority Register (IPR). Figure 7-1 shows addresses and identifiers for the interrupt control registers. Figure 7-2 is a block diagram showing the Interrupt Mask and Interrupt Priority logic.
The ZS MCU family supports both vectored and polled interrupt handling. Details on vectored and polled interrupts canbefoundlaterinthischapter.
Register
HEX Identifier
lnter~Mask lnterr~ R~uest Intern~~ Prio~
FBH FAH F9H
IMR IRQ IPR
Figure 7-1. Interrupt Control Registers
6
Interrupt Request
Vector Select Figure 7-2. Interrupt Block Diagram
Note: See the selected ZS MCU's product specification for the exact interrupt sources supported.
7-1
ZS' MICROCONTROLLERS
7.2 Interrupt Sources
Table 7-1 presents the interrupt types, sources, and vectors available in the Z8® family of processors.
Name IRQO IRQ1 IRQ2
IR03
IR04 IRQ5
Table 7-1. Interrupt Types, Sources, and Vectors *
Sources
Vector Location
Comments
DAV0, IRQ0, Comparator DAV1, IRQ1 DAV2, IRQ2, TIN, Comparator IRQ3
Serial In
0, 1
External (P32), Edge Triggered; Internal
2,3
External (P33), Edge Triggered; Internal
4,5
External (P31), Edge Triggered: Internal
6,7
External (P30) or (P32), Edge Triggered;
Internal
6,7
Internal
To Serial Out
8,9
Internal
8,9
Internal
T,
10, 11
Internal
7.2.1 External Interrupt Sources
External sources involve interrupt request lines IRQO-IRQ3. IRQO, IRQ1, and IRQ2 can be generated by a transition on the corresponding Port3 pin (P32, P33, and P31 correspond to IRQO, IRQ1, and IRQ2, respectively}. Figure 7-3 is a block diagram for interrupt sources IRQO, IR01, and IRQ2.
n= 2.3,1
Muliple lnputt--.----1 S
Q
and Sgnal Conclinonhg
arclity
R
D
Q
D
Q
IRO m='Pi,1;1
QntCerbnaclk) - - - - - - - '
Figure 7-3. Interrupt Sources IRQO-IRQ2 Block Diagram
Note: The interrupt sources and trigger conditions are device dependent. See the device product specification to determine available sources (internal and external), triggering edge options, and exact programming details.
7-2
ZS' MICROCONTROLLERS
When the Port 3 pin (P31, P32, or P33) transitions, the first flip-flop is set. The next two flip-flops synchronize the request to the internal clock and delay it by two internal clock periods. The output of the last flip-flop (IRQO, IRQ1, or IRQ2) goes to the corresponding Interrupt Request Register.
IRQ3 can be generated from an external source only if Serial In is not enabled. Otherwise, its source is internal. The external request is generated by a negative edge signal on P30 as shown in Figure 7-4. Again, the external
request is synchronized and delayed before reaching IRQ3. Some Z819 products replace P30 with P32 as the external source for IRQ3. In this case, IRQ3 interrupt generation follows the logic as illustrated in Figure 7-3.
Note: Although interrupts are edge triggered, minimum interrupt request Low and High times must be observed for proper
operation. See the device product specification for exact timing requirements on external interrupt requests (Twll, T)H).
II
P3Me
D
Q
D
(IR03 Serial In)
J1.[1_
Clock--------' IROs External Source
Serial Receiver
IRQ3 Internal Source
IROs
Figure 7-4. Interrupt Source IRQ3 Block Diagram
7.2.2 Internal Interrupt Sources
Internal sources involve interrupt requests IRQO, IRQ1, IRQ3, IRQ4, and IRQ5. Internal sources are ORed with the external sources, so either an internal or external source can trigger the interrupt. Internal interrupt sources and trigger conditions are device dependent. See the device product specification to determine available sources, triggering edge options, and exact programming details.
For more details on the internal interrupt sources, refer to the chapters describing the Counter/fimer, 1/0 ports, and Serial 1/0.
7-3
~zn.m
ZS' MICROCONTROLLERS
7.3 INTERRUPT REQUEST (IRQ) REGISTER LOGIC AND TIMING
Figure 7-5 shows the logic diagram for the Interrupt Request (IRQ) Register. The leading edge of the request will set the first flip-flop, that will remain set until interrupt requests are sampled.
At sample time the request is transferred to the second flipflop in Figure 7-5, that drives the interrupt mask and priority logic. When an interrupt cycle occurs, this flip-flop will be reset only for the highest priority level that is enabled.
Requests are sampled internally during the last clock cycle before an opcode fetch (Figure 7-6). External requests are sampled two internal clocks earlier, due to the synchronizing flip-flops shown in Figures 7-3 and 7-4.
The user has direct access to the second flip-flop by reading and writing the IRQ Register. IRQ is read by specifying it as the source register of an instruction and written by specifying it as the destination register.
IR00-IRQ5 R
s
Q
Sample
Clock
R
From Priority
Logic
Figure 7·5. IRQ Register Logic
To Mask
and Priority Logic
I I I I Mn
M1
M2
lnlnlnlnlnlnlnlnlnl
T
Interrupt Requests Sampled Internally
External Interrupt Requests Sampled
Figure 7-6. Interrupt Request Timing
7-4
ZS' MICROCONTROLLERS
7.4 INTERRUPT INITIALIZATION
After reset, all interrupts are disabled and must be initialized before vectored or polled interrupt processing can begin. The Interrupt Priority Register (IPR), Interrupt Mask Register (IMR), and Interrupt Request Register (IRQ) must be initialized, in that order, to start the interrupt process. However, IPR need not be initialized for polled processing.
7.4.1 Interrupt Priority Register (IPR) Initialization
IPR (Figure 7-7) is a write-only register that sets priorities for the six levels of vectored interrupts in order to resolve simultaneous interrupt requests. (There are 48 sequence possibilities for interrupts.) The six interrupt levels IRQOIRQ5 are divided into three groups of two interrupt requests each. One group contains IRQ3 and IRQ5. The second group contains IRQO and IRQ2, while the third group contains IRQ1 and IRQ4.
II
Priorities can be set both within and between groups as shown in Tables 7-2 and 7-3. Bits 1, 2, and 5 define the priority of the individual members within the three groups. Bits 0, 3, and 4 are encoded to define six priority orders between the three groups. Bits 6 and 7 are reserved.
Interrupt Group Priority Bits Priority 000 Reserved 001 C >A>B 010 A>B>C 011 A>C>B 100 B>C>A 101 C>B>A 110 B>A>C 111 Reserved
Group C (IRQ1 and IRQ4 Priority)
0 =IRQ1 > IRQ4 1 =IRQ4 > IRQ1
Group B (IRQO and IRQ2 Priority)
= 0 IRQ2 > IRQO
1 = IRQO > IRQ2
Group A (IRQ3 and IRQ5 Priority)
0 =IRQ5 > IRQ3
1 = IRQ3 > IRQ5
Reserved (Must be 0)
Figure 7-7. Interrupt Priority Register
7-5
't'2iUl6
Group
c
B
A
Table 7-2. Interrupt Priority
Priority Bit Value Highest Lowest
Bit 1
0
1
IRQ1 IRQ4
IRQ4 IRQ1
Bit 2
0
1
IRQ2 IRQO
IRQO IRQ2
Bit 5
0
1
IRQ5 IRQ3
IRQ3 IRQ5
U' MICROCONTROLLERS
Table 7-3. Interrupt Group Priority
Bit Pattern Bit4 Bit3 BitO
Group Priority
High
Medium Low
0 0 0
Not Used
0
0
1
c
A
B
0 1 0
A
B c
0
1
1
A
c
B
10 0
B
c
A
1
0
1
c
B
A
1 1 0
B
A
c
1
1
1
Not Used
7.4.2 Interrupt Mask Register (IMR) Initialization
MR individually or globally enables or disables the six interrupt requests (Figure 7-8). When bit Oto bit 5 are set to 1, the corresponding interrupt requests are enabled. Bit 7 is the master enable and must be set before any of the individual interrupt requests can be recognized. Resetting bit 7 globally disables all the interrupt requests. Bit 7 is set and reset by the El and DI instructions. It is automatically reset during an interrupt service routine and set following the execution of an Interrupt Return (IRET) instruction.
Note: Bit 7 must be reset by the DI instruction before the contents of the Interrupt Mask Register or the Interrupt Priority Register are changed except:
· Immediately after a hardware reset.
· Immediately after executing an interrupt service routine and before IMR bit 7 has been set by any instruction.
0 =Disables IRQO 1 =Enables IRQO O=Disables IRQ1 1 = Enables IRQ1 o = Dlsables IRQ2 1 = Enables IRQ2 O=Disables IR03 1 = Enables IRQ3
o=Disables IRQ4
1 = Enables IRQ4 O= Disables IRQ5 1 = Enables IRQ5 O= Disable RAM Protect 1 = Enable RAM Protect ~---------- o =Disables Interrupts 1 = Enables Interrupts
Figure 7-8. Interrupt Mask Register
Note: The RAM Protect option is selected at ROM mask submission time or at EPROM program time. If not selected or not an available option, this bit is reserved and must be 0.
7-6
ZS' MICROCONTROLLERS
7.4.3 Interrupt Request (IRQ) Register lnltlalization
IRQ (Figure 7-9) is a read/Write register that stores the interrupt requests for both vectored and polled interrupts. When an interrupt is made on any of the six levels, the corresponding bit position in the register is setto 1. Bit 0 to bit 5 are assigned to interrupt requests IRQO to IRQ5, respectively.
Note: Setting the Global Interrupt Enable bit in the Interrupt Mask Register (IMR, bit 7) will not enable the IRQ. Execution of the El instructionisrequired(Rgure7-1 O).
For polled processing, IRQ must still be initialized by an El instruction.
Whenever Power-On Reset (POR) is executed, the IRQ resister is reset to OOH and disabled. Before the IRQ register will accept requests, it must be enabled by executing an ENABLE INTERRUPTS (El) instruction.
To properly initialize the IRQ register, the following code is provided:
CLR IMR El DI
Register FAH Interrupt Request Register (IRQ) (Read/Write)
o = IRQO Reset 1 = IRQO Set
o = IRQ1 Reset
1 = IRQ1 Set
= 0 = IRQ2 Reset
1 IRQ2 Set
o = IRQ3 Reset
1 = IRQ3 Set
o = IRQ4 Reset
1 = IRQ4 Set o = IRQ5 Reset 1 = IRQ5 Set
Reseived /Int Edge Select
Figure 7·9. Interrupt Request Register
7-7
zae MICROCONTROLLERS
IMR is cleared before the IRQ enabling sequence to insure no unexpected interrupts occur when El is executed. This code sequence should be executed prior to programming the application required values for IPR and IMR.
Note: IRQ bits 6 and 7 are device dependent. When reserved, the bits are not used and will return a Owhen read. When used as the Interrupt Edge select bits, the configuration options are as show in Table 7-4.
Table 7-4. IRQ Register Configuration
IRQ 07 06
Interrupt Edge P31 P32
0
0
0
1
1
0
1
1
F
F
F
R
R F
R/F R/F
The proper sequence for programming the interrupt edge select bits is (assumes IPR and IMR have been previously initialized):
DI
;Inhibit all interrupts
till input edges are
configured.
OR IRQ,#XX OOOOOOB ;Configure interrupt
edges as needed -
do not disturb
IRQ0-5.
El
;Re-enable inter-
rupts.
Note: F = Falling Edge R = Rising Edge
El Instruction
Interrupt Request Register (IRQ, FAH)
Power-On Reset (POR)
Figure 7·10. IRQ Reset Functional Logic Diagram
7-8
~2H.1l6
zse MICROCONTROLLERS
7.5 IRQ SOFTWARE INTERRUPT GENERATION
IRQ can be used to generate software interrupts by specifying IRQ as the destination of any instruction referencing the ZS® Standard Register File. These Software Interrupts (SWI) are controlled in the same manner as hardware generated requests (in other words, the IPR and the IMR control the priority and enabling of each SWI level).
where the immediate data, NUMBER, has a 1 in the bit position corresponding to the level of the SWI desired. For example, if an SWI is desired on IRQ5, NUMBER would have a 1 in bit 5:
OR IRQ, #001000008
To generate aSWI, the desired request bit inthe IRQ is set as follows:
OR IRQ, #NUMBER
With this instruction, if the interrupt system is globally enabled, IRQ5 is enabled, and there are no higher priority pending requests, control is transferred to the service routine pointed to by the IRQ5 vector.
7.6 VECTORED PROCESSING
Each ZS interrupt level has its own vector. When an interrupt occurs, control passes to the service routine pointed to by the interrupt's vector location in program memory. The sequence of events for vectored interrupts is as follows:
· PUSH PC Low Byte on Stack · PUSH PC High Byte on Stack · PUSH FLAGS on Stack · Fetch High Byte of Vector · Fetch Low Byte of Vector · Branch to Service Routine specified by Vector
Figures 7-11 and 7-12 show the vectored interrupt operation.
SP and STACK before an Interrupt
SP
Top of Stack
SP and STACK after an Interrupt
f SP
h
PC LOW Byte
PC HIGH Byte
I...+
FLAGS
Figure 7-11. Effects of an Interrupt on the STACK 7-9
Program Memory
XXFFH
Interrupt Se rvice
Ro utine
ZS' MICROCONlllOLl!RS
OOOCH
Vector Selected By Priority Logic
1--
lnterrui;>t Vector Table
OOOOH
Figure 7·12. Interrupt Vectoring
7-10
7.6.1 Vectored Interrupt Cycle Timing
The interrupt acknowledge cycle time is 24 internal clock
!I
cycles and is shown in Figure 7-13. In addition, two internal clock cycles are required for the synchronizing flip-flops. The maximum interrupt recognition time is equal to the
j
number of clock cycles required for the longest executing
instruction present in the user program (assumes worst case condition of interrupt sampling, Figure 7-6, just prior to the interrupt occurrence). To calculate the worst case
l
interrupt latency (maximum time required from interrupt
generation to fetch of the first instruction of the interrupt
ij
service routine), sum these components:
Worst Case Interrupt Latency ... 24 TpC (interrupt acknowl-
t
edge time) + # TPC of longest instruction present in the
user's application program+ 2TPC (internal synchroniza-
if
tion time).
t
~
J
t
~
J
t
1
J
t
l l
l
'ZS' MICROCONTAOLLEAS
Figure 7-13. ZS Interrupt Acknowledge Timing
7-11
~z11.m
Z8' MICROCONIROIURS
7.6.2 Nesting of Vectored Interrupts
Nesting of vectored interrupts allows higher priority requests to interrupt a lower priority request. To initiate vectored interrupt nesting, do the following during the interrupt service routine:
· Push the old IMR on the stack. · Load IMR with a new mask to disable lower priority
interrupts. · Execute El instruction.
· Proceed with interrupt processing. · After processing is complete, execute DI instruction. · Restore the IMR to its original value by returning the
previous mask from the stack. · Execute IRET.
Depending on the application, some simplification of the above procedure may be possible.
7.7 POLLED PROCESSING
Polled interrupt processing is supported by masking off the IRQ levels to be polled. This is accomplished by clearing the corresponding bits in the IMR.
To initiate polled processing, checkthe bits of interest in the IRQ using the Test Under Mask (TM) instruction. If the bit is set, call or branch to the service routine. The service routine services the request, resets its Request Bit in the IRQ, and branches or returns back to the main program. An example of a polling routine is as follows:
TM JR CALL
IRQ, #MASKA Z,NEXT SERVICE
;Test for request ;If no request go to NEXT ;If request is there, then ;service it
NEXT:
SERVICE:
;Process Request
AND IRQ, #MASKS RET
;Clear Request Bit ;Return to next
In this example, if IRQ2 is being polled, MASKA will be 000001008 and MASKB will be 111110116.
7.8 RESET CONDITIONS
Upon reset, all bits in IPR are undefined.
In IMR, bit 7 is 0 and bits 0-6 are undefined. The IRQ register is reset and held in that state until an enable interrupt (El) instruction is executed.
7-12
~2iUD.,
USER'S MANUAL
CHAPTER 8
POWER-DOWN MODES
8.1 INTRODUCTION
In addition to the standard RUN mode, the Z841 supports two Power-Down modes to minimize device current consumption. The two modes supported are HALT and STOP.
8.2 HALT MODE OPERATION
The HALT mode suspends instruction execution and turns off the internal CPU clock. The on-chip oscillator circuit remains active so the internal clock continues to run and is applied to the Counter/Timer(s) and interrupt logic.
To enter the HALT mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in midinstruction. To do this, the application program must execute a NOP instruction (opcode = FFH) immediately before the HALT instruction (opcode 7FH), that is,
FF NOP ;clear the instruction pipeline 7F HALT ;enter HALT mode
The HALT mode is exited by interrupts, either externally or internally generated. Upon completion of the interrupt service routine, the user program continues from the instruction after HALT.
The HALT mode may also be exited via a POR/RESET activation or a Watch-Dog Timer (WOT) timeout. (See the product data sheet for WOT availability). In this case, program execution will restart at the reset restart address COOCH.
To further reduce power consumption in the HALT mode, some ZS family devices allow dynamic internal clock scaling. Clock scaling may be accomplished on the fly by reprogramming bitOand/or bit1 of the STOP-Mode Recovery register (SMR). See Figure 8-1.
Note: Internal clock scaling directly effects Counter/Timer operation-adjustment of the prescaler and downcounter values may be required. To determine the actual HALT mode current (lcc1) value for the various optional modes available, see the selected Z841 device's product specification.
8·1
. . MICROCONTROLLERS
8.3 STOP MODE OPERATION
The STOP mode provides the lowest possible device standby current. This instruction turns off the on-chip oscillator and internal system clock.
To enter the STOP mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in midinstruction. To do this, the application program must execute a NOP instruction (opcode=FFH) immediately before the STOP instruction (opcode=6FH), that is,
FF NOP ;clear the instruction pipeline 6F STOP ;enter STOP mode
The STOP mode is exited by any one of the following resets: Power-On Reset activation, WOT time out (if available), or a STOP-Mode Recovery source. Upon reset generation, the processor will always restart the application program at address OOOCH.
za PORJRESET activation is present on all devices and is
implemented as a reset pin and/or an on-chip power on reset circuit.
Some ZS devices allow for the on-chip WOT to run in the STOP mode. If so activated, the WOTtimeout will generate a reset some fixed time period after entering the STOP mode.
Note: STOP-Mode Recovery by the WDTwlll increase the STOP mode standby current (I=). This is due to the WOT clock and divider circuitry that is now enabled and running to support this recovery mode. See the product data sheet for actual lcc2 values.
In the simple case, a low level applied to input pin P27 will trigger a SMR. To use this mode, pin P27 {1/0 Port 2, bit 7) must be configured as an input before the STOP mode is entered. The low level on P27 must meet a minimum pulse width TWSM · (See the product data sheet) to trigger the device reset mode). Some Z8 devices provide multiple SMR input sources. The desired SMR source is selected via the SMR Register.
Note: Use of specialized SMR modes (P2. 7 input or SMR register based) or the WOTtimeout (only when in the STOP mode) provide a unique reset operation. Some control registers are initialized differently for a SMR/WOT triggered POR than a standard resE!t operation. See the product specification (register file map) for exact details.
To determine the actual STOP mode current (lcc2) value for the optional SMR modes available, see the selected ZS device's product data sheet.
Note: The STOP mode current (I=) will be minimized when:
· Vcc is at the low end of the devices operating range.
· WOT is off in the STOP mode.
· Output current sourcing is minimized.
· All inputs (digital and analog) are at the low or high rail voltages.
All Z8 devices provide some form of dedicated STOP-Mode Recovery (SMR) circuitry. Two SMR methods are implemented - a single fixed input pin or a flexible, programmable set of inputs. The selected Z8 device product specification should be reviewed to determine the SMR options available for use.
Note: For devices that support SPI, the slave mode compare feature also serves as a SMR source.
S-2
1J" MICROCOHTROLLEllS
8.4 STOP-Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of STOP-Mode Recovery (Figure 8-1 ). All bits are Write-Only, except bit 7, that is Read-Only. Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset by a power-on cycle. Bit 6 controls whether a low level or a high level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits 2, 3, and 4, of the SMR register, specify the source of the STOP-Mode Recovery signal. Bits 0 and 1 control internal clock divider circuitry. The SMR is located in Bank F of the Expanded Register File at address OBH.
II
SMR (FH) OB
SCLK/TCLK Dlvlde-by-16 0 OFF'* 1 ON
External Clock Divide by 2 0 SCLKITCLK =XTAIJ2* 1 SCLKITCLK =XTAL
STOP-Mode Recovery Source 000 POR Only and/or External Reset· 001 P30 010 P31 011 P32
100 P33 101 P27
110 P2 NOR 0-3 111 P2 NOR 0-7
Stop Delay 0 OFF 1 ON'
Stop Recovery Level
o Low*
1 High
Stop Flag (Read only)
0 POR*
* Default setting after RESET.
1 Stop Recovery
· · Default setting after RESET and STOP-Mode Recovery.
Figure 8-1. STOP·Mode Recovery Register (Write-Only Except Bit 07, Which Is Read-Only)
Note: The SMR register is available in select ZS MCU products. Refer to the device product specification to determine SMR options available.
8-3
SCLK/TCLK Dlvlde-by-16 Select (DO). This bit of the SMR controls a divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic).
External Clock Divide-by-Two (D1). This bit can eliminate the oscillator divide-by-two circuitry. When this bit is 0, the System Clock (SCLK) and Timer Clock (TCLK) are equal to the external clock frequency divided by two. The SCLK/TCLK is equal to the external clock frequency when this bit is set (01=1). Using this bit together with 07 of PCON helps further lower EMI (07 (PCON) =0, 01 (SMR) =1). The default setting is zero.
STOP-Mode Recovery Source (D2, 03, and D4). These three bits of the SMR specify the wake-up source of the STOPreccvery and(Table8-1andFigure8-2).
STOP-Mode Recovery Delay Select (05). This bit, if High, enables the TPOR /RESET delay after Stop-Mode Recovery. The default configuration of this bit is 1. If the "fast" wake up is selected, the Stop-Mode Recovery source is kept active for at least 5 TpC.
STOP-Mode Recovery Edge Select (D6). A 1 in this bit position indicates that a high level on any one of the
recovery sources wakes the zae from STOP mode. A O
indicates low-level recovery. The default is 0 on POR (Figure 8-2).
Cold or Warm Start (D7). This bit is set by the device upon entering STOP mode. AO in this bit (cold) indicates that the device reset by POR/WDT RESET. A 1 in this bit (warm) indicates that the device awakens by a SMR source.
Table 8-1. STOP-Mode Recovery Source
SMR:432
Operation
04 03 02 Description of Action
0 0 0 POR and/or external reset recovery 0 0 1 P30 transition 0 1 0 P31 transition (not in Analog Mode) 0 1 1 P32 transition (not in Analog Mode)
0 0 P33 transition (not in Analog Mode) 0 1 P27 transition 1 0 Logical NOR of P20 through P23 1 1 Logical NOR of P20 through P27
8-4
SMR D4 03 02 SMR 04 03 02
10 0
10 1
SMR D4 03 02 11 0
'1' MICROCONlllOLLERS
SMR D4 03 02 11 1
ToPOR
~Sto~p M~od~e R~ec~ov~ery~Ed-ge-11--~~~~~~~~~~~~~~~~~~--it--~~~ ~~-1~
Select (SMR)
To P33 Data
Latch and IRQ1
. . . . . . . . -P-33~F-ro_m_P~a-ds~~~~--i--~~~~~~~~~~~~~~~~~~~~~-IMUx
~~~~~
II
DlgltaVAnalog Mode
Select (P3M)
Figure 8-2. STOP·Mode Recovery Source
Note: If P31, P32, or P33 are to be used for a SMR source, the digital mode of operation must be selected prior to entering the STOP Mode.
8-5
ft'2iUD.,
USER'S MANUAL
9.1 UART INTRODUCTION
Select zae microcontrollers contain an on-board full-du-
plex Universal Asynchronous Receiver{rransmitter {UART) for data communications. The UART consists of a Serial 1/0 Register (SIO) located at address FOH, and its associated control logic (Figure 9-1). The SIO is actually
CHAPTER 9
SERIAL 1/0
two registers, the receiver buffer and the transmitter buffer, which are used in conjunction with Counter/Timer TO and Port 31/0 lines P30 (input) and P37 (output). Counter/Timer TO provides the clock input for control of the data rates.
P3o
Serial l/OClock (From TO)
lntamal Data Bus
Read FOH
Bit~ 1 - - - - - - - - IRC4
Serial In Start
WrlteFOH
CPha:t
Char Datacl Shift CIOck
Transmitter Shift Register
Shift CIOck
+ 16
Mark
~p~
Partly
Gan
L....J-----------------+1RQ3
+6
Stop
Figure 9-1. UART Block Diagram
9-1
Configuration of the UART is controlled by the Port 3 Mode
zs· Register (P3M) located at address F7H. The always
transmits eight bits between the start and stop bits (eight Data Bits or seven Data Bits and one Parity Bit). Odd parity generation and detection is supported.
The SIO Register and its associated Mode Control Registers are mapped into the Standard ZS Register File as shown in Table 9-1 . The organization allows the software to access the UART as general-purpose registers, eliminating the need for special instructions.
ZS8 MfcROCONlROWRS
Table 9-1. UART Register Map
Register Name
Identifier
Hex Address
Port3 Mode
P3M
F7
TO Prescaler
PREO
F5
Timer/CounterO
TO
F4
Timer Mode
TMR
F1
UART
SIO
FO
9.2 UART BIT-RATE GENERATION
When Port 3 Mode Register bit 6 is set to 1, the UART is enabled and TO automatically becomes the bit rate generator (Figure 9-2). The end-of-count signal of TO no longer
generates Interrupt Request IRQ4. Instead, the signal is used as the input to the divide-by-16 counters (one each for the receiver and the transmitter) that clock the data stream.
Register F7H (Write·Only)
l~l~l~l~loolool~lool
T
= O P30 Input and P37 Output
= 1 P30 Serial In and P37 Serial Out
Figure 9-2. Port 3 Mode Register {P3M) and Bit-Rate Generation
The divide chain that generates the bit rate is shown in Figure 9-3. The bit rate is given by the following equation:
Bit Rate= XTAL Frequency/(2 x 4 x p x t x 16)
where p and t are the initial values in PrescalerO and Counter{TimerO, respectively. The final divide-by-16 is required since TO runs at 16 times the bit rate in order to synchronize on the incoming data.
fXTAL
+2
+4
p
PREO
TO
Figure 9-3. Bit Rate Divide Chain
+ 16
Bit Rate Clock
To configure the ZS for a specific bit rate, appropriate values as determined by the above equation must be loaded into registers PREO
(F5H) and TO (F4H). PREO also controls the counting mode for TO and should therefore be set to the Continuous Mode (DO= 1).
9-2
4\21Ul6
.,, lllCRocoNlRouER
For example, given an input clock frequency ()<TAL) of 11.9808 MHz and a selected bit rate of 1200 bits per second, the equation is satisfied by p = 39 and t = 2. Counter/Timer TO should be set to 02H. With TO in Continuous Mode, the value of PREO becomes 9DH (Figure 9-4).
Table 9-2 lists several commonly used bit rates and the values of XTAL, p, and t required to derive them. This list is presented for convenience and is not intended to be exhaustive.
Bit Rate
1!ml !HD 48D 2«D 1aD 6D 3'.D
1BJ 110
7,3728 p t
3 1 3 2 3 4 3 8 3 16 3 32 3 &i 3 1a3 3 175
7,9872 p t
13 1 13 2 13 4 13 8 13 16 13 32 3 1Ell
Table 9-2. Bit Rates
9,8304 p t
11,0592 p t
4 1 4 2 4 4 4 8 4 16 4 32 4 &i 4 1a3 4 175
9 1 9 2 9 4 9 8 9 16 9 32 9 &i 5 157
11,6738 p t
11,9808
p
t
19 1 19 2 19 4 19 8 19 16
19 32 4 'JJ1'
~
1
~
2
~
4
~
8
~ 16
17 BJ
II 12,2880
p t
5 1 5 2 5 4 5 8 5 16 5 32 5 &i 5 1a3 8 1CB
Register F5H (Write-Only)
1~1~1~1~1001~1~1001
L _ Count Mode = O TO Single Pass =1 TO Moduo-n
(Range: 1-64 decimal, 01 H·OOH) (Range: 1-64)
Figure 9-4. Prescaler 0 Register (PREO) Blt·Rate Generation
9-3
The bit rate generator is started by setting the Timer Mode Register (TMR) (F1 H) bit 1 and bit 0 both to 1 (Figure 9-5). This transfers the contents of the Prescaler 0 Register and
'ii' MICROCONTROLLERS
Counter{TimerO Register to their corresponding down counters. In addition, counting is enabled so that UART operations begin.
Register F1 H (Read/Write)
O= No Function 1 =Load TO O= Disable TO Count 1 = Enable TO Count
Figure 9-5. Timer Mode Register (TMR) Bit Rate Generation
9.3 UART RECEIVER OPERATION
The receiver consists of a receiver buffer ($10 Register [FOH]), a serial-in, parallel-out shift register, parity checking, and data synchronizing logic. The receiver block diagram is shown as part of Figure 9-1.
9.3.1 Receiver Shift Register
After a hardware resetorafteracharacterhasbeen received, the ReceiverShift Register is initialized to all 1sand theshiftclock is stopped. Serial data, input through Port 3 bit 0, is synchronized to the internal clock by two D-type flip-flops before being input to the Shift Register and the start bit detection circuitry.
The start bit detection circuitry monitors the incoming data stream, looking for a start bit (a High-to-Low input transition). When a start bit is detected, the shift clock logic is enabled. The TO input is divided-by-16 and, when the count equals eight, the divider outputs a shift clock. This clock shifts the start bit into the Receiver Shift Register at the center of the bit time. Before the shift actually occurs, the input is rechecked to ensure that the start bit is valid. If the detected start bit is false, the receiver is reset and the process of looking for a start bit is repeated. If the start bit is valid, the data is shifted into the Shift Register every sixteen counts until a full character is assembled (Figure 9-6).
(R) RCVR
Data
Shift Clock RCVR IRQ3
9-4
Start Bit Transition Detected Eight TO Counts Later Shifting Starts
Figure !Mi. Receiver Timing
Stop Bit One or More
r· ·· ,
Shift Register Contents Transferred to Receiver Buffer
and IRQ3 Is Generated
ZS' MICROCONTROu.ERS
After a full character has been assembled in the receiver's buffer, SIO Register (FOH), Interrupt Request IRQ3 is generated. The shift clock is stopped and the Shift Register reset to all 1s. The start bit detection circuitry begins monitoring the data input for the next start bit. This cycle allows the receiver to synchronize on the center of the bit time for each incoming character.
9.3.2 Overwrites
Although the receiver is single buffered, it is not protected from being overwritten, so the software must read the SIO Register (FOH) within one character time after the interrupt
za request (IRQ3). The does not have a flag to indicate this
overrun condition. If polling is used, the IRQ3 bit in the Interrupt Request Register must be reset by software.
9.3.3 Framing Errors
Framing error detection is not supported by the receiver hardware, but by responding to the interrupt request within one character bittime, the software can test for a stop bit on P30. Port3 bits are always readable, which facilitates break detection. For example, if a null character is received, testing P30 results in a 0 being read.
9.3.4 Parity
II
The dataformat supported by the receiver must have a start bit, eight data bits, and at least one stop bit. If parity is on, bit 7 of the data received will be replaced by a Parity Error Flag. A parity error sets bit 7 to 1, otherwise, bit D7 is set to 0. Figure 9-7 shows these data formats.
Received Data (No Parity)
Received Data (With Parity)
Start Bit Eight Data Bits One Stop Bit
Figure 9-7. Receiver Data Formats
Start Bit Seven Data Bits Parity Error Flag One Stop Bit
9-5
·21Ul6
zs· The hardware supports odd parity only, that is enabled
by setting the Port 3 Mode Register bit 7 to 1 (Figure 9-8).
'ZS' MICROCONTROLLERS
If even parity is required, the Parity Mode should be disabled (P3M bit 7 set to 0), and software must calculate the received data's parity.
Register F7H (Write-Only)
0= Parity Off 1 =Parity On
Figura 9-8. Port 3 Mode Register (P3M) Parity
9.4 TRANSMITTER OPERATION
9.4.1 Overwrites
The transmitter consists of a transmitter buffer (SIO Register [FOH]), a parity generator, and associated control
logic. The transmitter block diagram is shown as part of
Figure 9-1.
The user is not protected from overwriting the transmitter, so it is up to the software to respond to IRQ4 appropriately. If polling is used, the IRQ4 bit in the Interrupt Request Register must be reset.
After a hardware reset or after a character has been transmitted, the transmitter is forced to a marking state (output always High) until a character is loaded into the transmitter buffer, SIO Register (FOH). The transmitter is loaded by specifying the SIO Register as the destination register of any instruction.
TO's output drives a divide-by-16 counter that in turn generates a shift clock every 16 counts. This counter is reset when the transmitter buffer is written by an instruction. This reset synchronizes the shift clock to the software. The transmitter then outputs one bit per shift clock, through Port 3 bit 7, until a start bit, the character written to the buffer, and two stop bits have been transmitted. After the second stop bit has been transmitted, the output is again forced to a marking state. Interrupt request IRQ4 is generated at this time to notify the processor that the transmitter is ready to accept another character.
9.4.2 Parity
The data format supported by the transmitter has a start bit, eight data bits, and at least two stop bits. If parity is on, bit 7 of the data transmitted will be replaced by an odd parity bit. Figure 9-9 shows the transmitter data formats.
Parity is enabled by setting Port 3 Mode Register bit 7 to 1. If even parity is required, the parity mode should be disabled (P3M bit 7 reset to 0), and software must modify the data to include even parity.
Since the transmitter can be overwritten, the user is able to generate a break signal. This is done by writing null characters to the transmitter buffer (SIO Register [FOH]) at a rate that does not allow the stop bits to be output. Each time the SIO Register is loaded, the divide-by-16 counter is resynchronized and a new start bit is output followed by data.
9-6
'zat MICROCONTROLLERS
Transmitted Data (No Parity)
T I "'[__ 1~1~1~1~1~1~1~1~1~1~1&1 Start Bit '-·- - - - - - - - Eight Data Bits Two Stop Bits
Transmitted Data (With Parity)
1T "'[__ 1~1~1p1~1~1~1~1~1~1~1&1 StartBlt
L - - - - - - - - Seven Data Bits
L - - - - - - - - - - - - - Odd Parity L - - - - - - - - - - - - - - - Two Stop Bit
Figure 9-9. Transmitter Data Formats
9·7
'Z8' MICROCONTROLLERS
9.5 UART RESET CONDITIONS
After a hardware reset, the SIO Register contents are undefined, and Serial Mode and parity are disabled. Figures 9-10 and 9-11 show the binary reset values of the SIO Register and its associated mode register P3M.
Serial Data (D0 = LSB) Figure 9-10. SIO Register Reset
L
O Port 2 pull-ups open-drain 1 Port 2 pull-ups active
0 P32 = Input
P35 = Output
1 P32 = /DAVO/RrNO P35 = RrNO//DAVO
...___ _ _ _ _ _ 00 P33 =Input
P34=0utput
~J P33 = Input
P34=/DM
= 11 P33 /DAV1/RrN1 P34 = RrN1//DAV1
. . . . _ _ _ _ _ _ _ _ _ _ 0 P31 = Input CT1N) P36 =Output (Tour>
1 P31 = /DAV2/RrN2 P36 = RD'f2//DAV2
...___ _ _ _ _ _ _ _ _ _ 0 P30 =Input
1 P30 =Serial In
P37= Output P37 = Serial Out
' - - - - - - - - - - - - - - O Parity Off 1 ParityOn
Figure 9-11. P3M Register Reset
9-8
'ZB' MICROCONTROLl.ERS
9.6 Serial Peripheral Interface (SPI)
Select Z8® microcontrollers incorporate a serial peripheral interface (SPI) for communication with other microcontrollers and peripherals. The SPI includes features such as Stop-Mode Recovery, Master/Slave selection, and Compare mode. Table 9-3 contains the pin configuration for the SPI feature when it is enabled. The SPI consists of four registers: SPI Control Register (SCON), SPI Compare Register (SCOMP), SPI Receive/Buffer Register (RxBUF), and SPI Shift Register. SCON is located in bank (C) of the Expanded Register File at address 02.
Table 9-3. SPI Pin Configuration
Name
Function
Pin Location
DI
Data-In
P20
DO
Data-Out
P27
SS
Slave Select
P35
SK
SPI Clock
P34
The SPI Control Register (SCON) (Figure 9-12), is a read/ write register that controls Master/Slave selection, interrupts, clock source and phase selection, and error flag. Bit O enables/disables the SPI with the default being SPI disabled. A 1 in this location will enable the SPI, and a 0 will disable the SPI. Bits 1 and 2 of the SCON register in Master Mode select the clock rate. The user may choose whether internal clock is divide-by-2, 4, 8, or 16. In Slave Mode, Bit 1 of this register flags the user if an overrun of the RxBUF Register has occurred. The RxCharOverrun flag is only reset by writing a 0 to this bit. In slave mode, bit 2 of the Control Register disables the data-out 1/0 function. If a 1 is written to this bit, the data-out pin is released to its original port configuration. If a 0 is written to this bit, the SPI shifts out one bit for each bit received. Bit 3 of the SCON Register enables the compare feature of the SPI, with the default being disabled. When the compare feature is enabled, a comparison of the value in the SCOMP Register is made with the value in the RxBUF Register. Bit 4 signals that a receive character is available in the RxBUF Register.
SCON (C)02
lwl~l~l~lmlool~lool
L
(S) Used with Bit D7 equal to 0 (M) Used with Bit D7 equal to 1 * Default Setting After Reset.
SPI Enable O Disable· 1 Enable
RxCharOverrun (S)
o Resat
1 overrun
CLK Divide (M) 00 TCLK/2 01 TCLK/4 10 TCUK/8 11 TCLK/16
DO SPI Port Enable (S) O SPI DO Port Enabled 1 DO Port to 1/0
cg"E,8~~1;nable
1 Disable·
RxCharAvail o Reset 1 Char. Avail.
Clock Phase 0 Trans/Fall 1 Trans/Rise
CLKSource 0 TCLK 1 Timer OOutput
Master Slave 0 Slave 1 Master
Figure 9-12. SPI Control Register (SCON)
If the associated IRQ3 is enabled, an interrupt is generated. Bit 5 controls the clock phase of the SPI. A 1 in bit 5 allows for receiving data on the clock's falling edge and transmitting data on the clock's rising edge. A O allows receiving data on the clock's rising edge and transmitting on the clock's falling edge. The SPI clock source is defined in bit 6. A 1 uses TimerO output for the SPI clock, and a O uses TCLK for clocking the SPI. Finally, bit 7 determines whethertheSPI is used as a MasteroraSlave.A 1 puts the SPI into Master mode and a 0 puts the SPI into Slave mode.
9-9
Z8' MICROCONTROLLERS
9.7 SPI Operation
9.8 SPI Compare
The SPI is used in one of two modes: either as system slave, or as system master. Several of the possible system configurations are shown in Figure 9-13. In the slave mode, data transfer starts when the slave select (SS) pin goes active. Data is transferred into the slave's SPI Shift Register through the DI pin, which has the same address as the RxBUF Register. After a byte of data has been received by the SPI Shift Register, a Receive Character Available (RCA/IRQ3) flag and interrupt is generated. The next byte of data will be received at this time. The RxBUF Register must be cleared, or a Receive Character Overrun (RxCharOverrun) flag will be set in the SCON Register, and the data in the RxBUF Register will be overwritten. When the communication between the master and slave is complete, the SS goes inactive.
When the SPI Compare Enable bit, D3 of the SCON Register is set to 1, the SPI Compare feature is enabled. The compare feature is only valid for slave mode. A compare transaction begins when the (SS) line goes active. Data is received as if it were a normal transaction, but there is no data transmitted to avoid bus contention with other slave devices. When the compare byte is received, IRQ3 is not generated. Instead, the data is compared with the contents of the SCOMP Register. If the data does not match, DO remains inactive and the slave ignores all data until the (SS) signal is reset. If the data received matches the data in the SCOMP register, then a SMR signal is generated. DO is activated if it is not tri-stated by D2 in the SCON Register, and data is received the same as any other SPI slave transaction.
Unless disconnected, for every bit that is transferred into the slave through the DI pin, a bit is transferred out through the DO pin on the opposite clock edge. During slave operation, the SPI clock pin (SK) is an input. In master mode, the CPU must first activate a SS through one of its 1/0 ports. Next, data is transferred through the master's DO pin one bit per master clock cycle. Loading data into the shift register initiates the transfer. In master mode, the master's clock will drive the slave's clock. At the conclusion of a transfer, a Receive Character Available (RCA/ IRQ3) flag and interrupt is generated. Before data is transferred via the DO pin, the SPI Enable bit in the SCON Register must be enabled.
When the SPI is activated as a slave, it operates in all system modes: STOP, HALT, and RUN. Slaves' not comparing remain in their current mode, whereas slaves' comparing wake from a STOP or HALT mode by means of an SMR.
9.9 SPI Clock
The SPI clock maybe driven by three sources: TimerO, a division of the internal system clock, or the external master when in slave mode. Bit D6 of the SCON Register controls what source drives the SPI clock. A 0 in bit D6 of the SCON Register determines the division of the internal system clock if this is used as the SPI clock source. Divide by 2, 4, 8, or 16 is chosen as the scaler.
9-10
't'2H.C6
Standard Serial Setup
Standard Parallel Setup
ZS' MICROCONTROLLERS
II
Setup For Compare
(1)
(2)
(255)
Up to 256 slaves per SS fine
Three Wire Compare Setup
(256)
Multiple slaves may have the same address.
Figure 9-13. SPI System Configuration
9-11
<tlZH.!16
7JI MICROCONTROLLERS
9.10 Receive Character Available and Overrun
When a complete data stream is received, an interrupt is generated and the RxCharAvail bit in the SCON Register is set. Bit 4 in the SCON Register is for enabling or disabling the RxCharAvail interrupt. The RxCharAvail bit is available for interrupt polling purposes and is reset when the RxBUF Register is read. RxCharAvail is generated in both master and slave modes. While in slave mode, if the RxBUF is not
read before the next data stream is received and loaded into the RxBUF Register, Receive Character Overrun (RxCharOverrun) occurs. Since there is no need for clock control in slave mode, bit D1 in the SPI Control Register is used to log any RxCharOverrun (Figure 9-14 and Figure 9-15).
No
Parameter
Min
Units
1
DI to SK Setup
10
ns
2
SK to DO Valid
15
ns
3
SS to SK Setup
.5 Tsk
ns
4
SS to DO Valid
15
ns
5
SK to DI Hold Time
10
ns
Tsk SK
3 SS
00
©
DI
Figure 9-14. SPI Timing
9-12
SMR
Bit Counter /Interrupt Control
IRQ3
SPI Compare Register (SCOMP) SPI Shift Register
SPI Receive Buffer (RxBUF) SPI Control
Figure 9-15. SPI Logic
ZS' MICROCONTROLLERS
SK
DO
DI
SS
Ill
SPI Clock
TCLK SCLK+n
9-13
Open-Drain P200E SPIEN
D' MlcRoCONTROLLEllS
P20 PAD
P201N
or
SPIDI
- ----------- ,
I
I
Auto latch
R1'11500K'1
I I
Open-Drain - - - - - - - - - - - . P27 OUT _ _ _Sta_nda_rd_,, ~----.,.......
SPI DO _ _ ___:S:;,.Pl;.....;-
11\D
P27 OE
Standard
SPIActlve _ _ ___.S.P..I~
I I SCON
'-·_ _ _ _ _ _..__ _._ o1 SPP2I7D0OUETnable
·SP1 must be enabled with DO.
I I t ------------, Auto Latch
LII _
_R:_l:IG_5_00_K'_1
_
_
_
__
_
I
J I
Figure 9-16. SPI Data In/Out Configuration
9-14
ZS' MICROCONTROLLERS
SKIN
SPI EN - - - - - - 1
SPI MSTR - - - - 1 ~--,__,
P340UT---<I
P31~t
SPI EN - - - - - - , SK OUT - - - - - t MUX
REF
ss-------------<
SPIEN
SPIMSTR
P350UT----
P32~
REF PCON 0 P34, P35 Standard Output
.__ _ _ _ _ __._D_.o 1 P34, P35 Comparator Output
Figure 9-17. SPI Clock/ SPI Slave Select Output Configuration
P34 PAD
P35 PAD
II
9-15
USER'S MANUAL
10.1 INTRODUCTION
The ZS"' can be a microcontroller with 20 pins for external memory interfacing. The external memory interface on the ZS is generally for either RAM or ROM. This is only available
for devices featuring Port 0, Port 1, R/N/, /DM, /AS, and
/DS. Please refer to specific product specifications for availability of these features.
CHAPTER 10
EXTERNAL INTERFACE
El
The ZS has a multiplexed external memory interface. In the multiplexed mode, eight pins from Port 1 form an Address/ Data Bus (AD7-ADO), eight pins from Port 0 form a High Address Bus (A15-AS). Three additional pins provide the Address Strobe, Data Strobe, and the Read/Write Signal. Figure 10-1 shows the external interface pins of the ZS.
IA
(Port 1)AD7-ADO
"'
(Porto) AD15-AD8
Z8
/AS IDS R//W /DM
~A -.'"
._A
External ProgramfDala
....
Memory up to 64 KbY18S
Each
....
Figure 1l>-1. Z8 External Interface Pins
10-1
7J1 MICRoCONTBOLLERS
10.2 PIN DESCRIPTIONS
The following sections briefly describe the pins associated with the Z88 external memory interface.
10.2.1 /AS Address Strobe (output, active Low). Address Strobe is pulsed Low once at the beginning of each machine cycle. The rising edge of /AS indicates the address, Read/Write (R/JW), and Data Memory (/DM) signals are valid for program or data memory transfers. In some cases, the ZB address strobe is pulsed low regardless of accessing external or internal memory. Please refer to specific product specifications for /AS operation.
10.2.2 IDS DataStrobe(output, active Low). Data Strobe provides the timing for data movement to or from the Address/Data bus for each external memory transfer. During a Write Cycle, data out is valid at the leading edge of the /DS. During a Read Cycle, data in must be valid prior to the trailing edge of the /DS.
10.2.3 R//W Read/Write(output). Read/Write determines the direction of data transfer for memory transactions. R/JW is Low when writing to program or data memory, and High for all other transactions.
10.2.4 /DM Data Memory (output). Data Memory provides a signal to separate External Program Memory from External Data Memory. It is a programmable function on pin P34. Data memory is active low for External Data Memory accesses and high for External Program Memory accesses.
10.2.5 P07 · P01 High Address Lines A15 -AB (Outputs can be CMOS- or TTL-compatible. Please refer to product specifications for actual type). A15-A8 provide the High Address lines for the memory interface. Port 0 - 1 mode register must have bits D7 = 1 and D1 = 1to configure Porto as A15-A8 (Figure 10-2).
10.2.6 P17 · P10 Address/Data Lines AD? - ADO (inputs/ outputs, TTL-compatible). AD7-ADO is a multiplexed Address/Data memory interface. The lower eight Address lines (A7-AO) are multiplexed with Data lines (D7-DO). Port 0- 1 mode register must have bits D4 = 1 and D3 = 0 to configure Port 1 as AD? - ADO (Figure 10-2).
10.2.7 /RESET Reset(input, active Low). /RESET initializes the ZS. When /RESET is deactivated, program execution begins from program location OOOCH. If held Low, /RESET acts as a register file protect during power-down and power-up sequences. To avoid asynchronous and noisy reset problems, the ZB is equipped with a reset filter of four external clocks (4TPC). If the external /RESET signal is less than 4TPC in duration, no reset will occur. On the fifth clock after the /RESET is detected, an internal reset signal is latched and held for an internal register count of 18 or more external clocks, or for the duration of the external /RESET, whichever is longer. Please refer to specific product specifications for length of reset delay time.
10.2.8 XTAL1, XTAL2. Crysta/1, Crysta/2(0scillator input and output). These pins connect a parallelresonant crystal, ceramic resonator, LC, RC network, or external single-phase clock to the on-chip oscillator input. Please refer to the device product specifications for information on availability of RC oscillator features.
10-2
ZS- MICROCONTROLLERS
10.3 EXTERNAL ADDRESSING CONFIGURATION
The minimum bus configuration uses Port 1 as a multiplexed address I data port (AD7 -ADO), allowing access to 256 bytes of external memory. In this configuration, the eight low order bits (AO- A7) are multiplexed with the data
(07- DO).
Port 0 can be programmed to provide either four additional address lines (A11- A8), which increases the addressable memory to 4K bytes, or eight additional address lines (A15 -A8), which increases the addressable external memory up
to 64K bytes. It is required to add a NOP after configuring Port 0 I Port 1 for external addressing before jumping to external memory execution.
El
P07 - POp Mode 00 Output 01 Input
1X A11 -As
P17-P10 00 Byte Output 01 Byte Input 10 AD7 -AD0 11 High-Impedance
A15-A8 AD7-ADO /AS/OS
R//W
P07 - P04 Mode 00 Output 01 Input 1X A15 ·A12
Figure 10-2. External Address Configuration
10-3
D' MICROCONTBOLLERS
10.4 EXTERNAL STACKS
The ZS-architecture supports stack operations in eitherthe ZS Standard Register File or External Data Memory. A stack's location is determined by bit 2 in the Port 0-1 Mode Register (FSH). If bit 2 is set to 0, the stack is in External Data Memory. (Figure 10-3).
The instruction used to change the stack selection bit should not be immediately followed by the instructions RET
or IRET, because this will cause indeterminate program flow. After a /RESET, the internal stack is selected.
Please note that if Port 0 is configured as A15 - AS and the stack is selected as internal, any stack operation will cause the contents in register FEH to be displayed on Port 0.
Register FBH (P01 M) Port 0-1 Mode Reglsler (Write-Only)
Jo1losloslo4I osl 021011 ool
T
Zo8 =SEtaxctkerSneallection
1 = lnlemal
Figure 1e». Z8 Stack Selection
10.5 DATA MEMORY
The two ZS external memory spaces, data and program, are addressed as two separate spaces of up to 64 Kbytes each. External Program Memory and External Data Memory are logically selected by the Data Memory select output (/DM). /DM is made available on Port 3, bit 4 (P34) by setting bit 4 and bit 3 in the Port 3 Mode Register (F7H) to 10 or 01 (Figure 10-4). /DM is active Low during the
execution of the LDE, LDEI instructions, and High for the execution of program instructions. /DM is also active Low during the execution of CALL, POP, PUSH, RET and IRET instructions if the stack resides in External Data Memory. After a /RESET, /DM is not selected.
8egisler F7H (P3M)
Port 3 Mode Register (Write-Only)
l~lool~l~lool~lrnlool
---,=....________ Bl1s
00 01 10 11
Configuration
P33= Input P34= Oulput P33=1nput P34=!DM P33= Input P34=!DM P33= JDAV1 /RDV1 P34=RDY1//0AV1
Figure 1G-4. Port 3 Data Memory Operation
10-4
10.6 BUS OPERATION
Typical data transfers between the"ZJ1' and EXternal Memory are illustrated in Figures 10-5 and 10-6. Machine cycles can vary from six to 12 clock periods depending on the operation being performed. The notations used to de-
T1
scribe the basic timing periods of the ZS are machine cycles (Mn), timing states (Tn), and clock periods. All timing references are made with respect to the output signals /AS and JDS. The clock is shown for clarity only and does not have a specific timing relationship with other signals.
Machi: 3 Cycle ---T----1111~,
El
Clock A15-A8 AD7-ADO
x
A8-A15
x
x ) A7-AO
(01-001NH
/AS
\__/
\__
IDS
\
I
R//W
I
\:
/OM
x
x
1~
Read Cycle
·I
Figure 10-S. External Instruction Fetch or Memory Read Cycle
·Port inputs are strobed during T2, which is two internal system clocks before the execution cycle of the current instruction.
10-S
ftl21Ul6
Clock A15·A8 AD7·ADO
/AS IDS R//W /OM
r T1
Machine Cycle T2
U' MICROCONTROLLERS
~,
T3
x x A7·AO
A15·A8
x
D7·DOOUT
x::: x:::
\_/
\_
\
I
\
r
x
x:::
I,.
Write Cycle
~1
Figure 10-6. External Memory Write Cycle
10.6.1 Address Strobe (/AS)
All transactions start with /AS driven Low and then raised High bythezae. The rising edge of /AS indicatesthatR//W, /OM (if used), and the address outputs are valid. The address outputs (AD7·ADO), remain valid only during MnT1
and typically need to be latched using /AS. Address outputs
(A15-AB) remain stable throughout the machine cycle, regardless of the addressing mode.
10.6.2 Data Strobe (IDS)
The ZB uses IDS to time the actual data transfer. For Write operations (R//W = Low), a Low on /OS indicates that valid data is on the AD7-ADO lines. For Read operations (R/W = High), the bus is placed in a high-impedance state before driving /OS Low, so the addressed device can put its data on the bus. The ZB samples this data prior to raising /DS High.
10·6
'ZS" MICROCONTROLLERS
10.7 EXTENDED BUS TIMING
Some products can accommodate slow memory access time by automatically inserting an additional software controlled state time (Tx). This stretches the /DS timing by
two clock periods. Figures 10-7 and 10-8 illustrate extended external memory Read and Write cycles.
,~
T1
Machine Cycle - - - - - - - - - · . . ,..1
T2
TX
T3
II
Clock
x::: A15-A8 ==><----------A-15-·A_s__________
AD7-ADO /AS
A7-AO
\__/
\_
IDS
R//W
I
=::x /OM
Read Cycle
\:
x:::
Figure 10-7. Extended External Instruction Fetch or Memory Read Cycle ·Port inputs are strobed during T2, which is two internal system clocks before the execution cycle of the current instruction.
10-7
ft'ZH.m
i- T1
Machine Cycle
T2
TX
'11' MICROCONTROLLERS
.,
T3
Clock
A15-A8 :::::><
AD7-ADO :::::><
A7-AO
x
/AS
\__/
A15-A8 07-DOOUT
x:: x::
\__
IDS
RINI
\
/OM:::::><
\
Write Cycle
I
r
x::
Figure 1o-a. Extended External Memory Write Cycle
Timing is extended by setting bit 05 in the Port 0-1 Mode Register (FBH) to 1(Figure10-9). After a/RESET, this bit is set
too.
ReglsterF8H (P01M) Port 0-1 Mode Register (Write-Only)
l l l l l02l l 1 01 06 05 04 03 01 00 I
T
External MemoryTlming o =Normal 1 =Extended
Figure 10-9. Extended Bus Timing
10-8
·211.m
'lJ' llK:RoCONTROLLERS
10.8 INSTRUCTION TIMING
The High throughput of the Z8111 is due , in part, to the use of an instruction pipeline, in which the instruction fetch and execution cycles are overlapped. During the execution of , the current instruction, the opcode of the next instruction is fetched. Instruction pipelining is illustrated in Figure 10-10.
Figures 10-11 and 10-12 show typical instruction cycle timing for instructions fetched from memory. For those instructions that require execution time longer than that of the overlapped fetch, or reference program or data memory as part of their execution, the pipe must be flushed.
Note: Figures 10-11 and 10-12 assume the XTAL./2 clock mode is selected.
II
Izi ecn:
!5
I
)!!
~
:§ ~
.E
Q)
~
cd:i Q.
.CcE:l
F
~
~
c:
n 0
:J
1E
.E
I .,....;.
)!!
~
,0...
!!!
1:J ~
Q)
£ 0
Q)
~
c:
~
0
~
Q)
Q)
£ !!! .2 .Qc) .:C:J.:)
0 .Q 0
E J!l
CJ)
~
(\j
E J!l
.!;;;
~
.!!! .s::.
:0c
~==
Cc: l
"§
"'C
"'C
e.Qc)
1i5 c
Q) .Q ~u Ill :J
.ae .~!; ts·c-: -c:
IL S!!!
« 0
i ~
~ 8 <
fl
~
~
10-9
"'::i; ~
:~c
;::
!ll ~
~ :c
i ~
~
:c
;::
1J' MICROCONTROLLERS
· Port inputs are strobed during T2, which is two internal system clocks before the execution cycle of the current instruction.
T
!~-w
ff
-!:1::5;
ll!
~i 'cii' 0 ts
~
.5
t
ID
..!.c.
!-
~
"caCsl
~ ~
·ecCll
j::
~ (;
c
i e
';;
!
!!
~
.5
,..0.....:
l I!! :II ~
10-10
10.9 ZS RESET CONDITIONS
After a hardware reset, extended timing is setto accommodate slow memory access during the configuration routine, /DM is inactive, the stack resides in the register file. Port 0, 1, and 2 are reset to input mode. Port 2 is set to Open-Drain Mode.
'ZJ' MICROCONTROLl.ERS
El
10-11
4'2iU:a.,
USER'S MANUAL
11.1 INTRODUCTION
11.1.1 ZS Addressing Modes
The Z89 microcontroller provides six addressing modes:
Register (R)
· Indirect Register (IA) · lndexed(X) · Direct(D) · Relative (RA) ·· Immediate (IM)
With the exception of immediate data and condition codes, all operands are expressed as register file, Program Memory, or Data Memory addresses. Registers are accessed using 8-bit addresses in the range of OOH-FFH. The Program Memory or Data Memory is accessed using 16-bit addresses (register pairs) in the range of OOOOHFFFFH.
CHAPTER 11
ADDRESSING MODES
II
Working Registers are accessed using 4-bit addresses in the range of 0-15 (OH-FH). The address of the register being accessed is formed by the combination of the upper four bits in the Register Pointer (R253) and the 4-bit working register address supplied by the instruction.
Registers can be used in pairs to designate 16-bit values or memory addresses. A Register Pair must be specified as an even-numbered address in the range of 0, 2, ...., 14 for Working Registers, or 4, 6, ....238 for actual registers.
In the following definitions of ZB Addressing Modes, the use of 'register' can also imply register pair, working register, or working register pair, depending on the context.
Note: See the product data sheet for exact program, data, and register memory types and address ranges available.
11-1
ft'21Ul6
11.2 Z8 REGISTER ADDRESSING (R)
'lJ' MICROCON1ROUERS
In 8-bit Register Addressing mode, the operand value is equivalent to the contents of the specified register or register pair.
In the Register Addressing (Figure 11·1 ), the destination and/or source address specified corresponds to the actual register in the register file.
Program Memory
Register File
..... 8·Bit Register
File Address
...... One Operand Instruction (Example)
dst OpCode
~
Points to One Register
in the
Re~ister
ile
Operand
Figure 11-1. 8-Blt Register Addressing
In 4-bit Register Addressing (Figure 11-2), the destination and/or source addresses point to the Working Register within the current Working Register Group. This 4-bit
address is combined with the upper four bits of the Register Pointer to form the actual 8-bit address of the affected register.
Register File
RP
~~
Program Memory
4-Bit Working Registers
~
Two Operand Instruction ~ (Example)
ldst
src
OpCode
1
Points to the Working Registers
Operand Operand
Points to Origin of Working Register Group
14-
Figure 11-2. 4-Blt Register Addressing 11-2
ue MICROCONTROLLERS
11.3 ZS INDIRECT REGISTER ADDRESSING (IR)
In the Indirect Register Addressing Mode, the contents of the specified register are equivalent to the address of the operand (Figures 11-3 and 11-4).
When accessing program memory or External Data Memory, register pairs or Working Register pairs are used to hold the 16-bit addresses.
Depending upon the instruction selected, the specified register contents points to a Register, Program Memory, or an External Data Memory location.
II
Program Memory
Register File
8-Bit Register File Address
- One Operand Instruction - (Example)
dst OpCode
Points to one
Re~isterin
Register File
Address of Operand Used By Instruction
Address/, .....,
Points to Register of Operand
Value Used In Instruction
......i
Execution
Operand i..-
Figure 11-3. Indirect Register Addressing to Register Fiie
11-3
11.3 ZS INDIRECT REGISTER ADDRESSING (IR) (Continued)
Register File
RP .,....__
Program Memory
-- 4-Bit Working
Register Address
Instruction Example References Either Program Memory or
Data Memory
Jdst
SIC
OpCode
Points to
Working Register Pair(Even Address)
Register PairLSB
Register PairMSB
points to Origin ~ of Working
Register Group
-
~I-
!-
or DPat~a aemmory
16-Bit Address
.....
Points to Program or Data
Memory
Value Used In Instruction
Operand
Figure 11-4. Indirect Register Addressing to Program or Data Memory
11-4
D" MICllOCONTIIOLLERS
11.4 ZS INDEXED ADDRESSING (X)
The Indexed Addressing Mode is used only by the Load (LO) instruction. An indexed address consists of a register address offset by the contents of a designated Working Register (the Index). This offset is added to the register
address to obtain the address of the operand. Figure 115 illustrates this addressing convention.
Register Fila
II
RP .....
Program Memory
Two Operand Instruction
~
Address
ldssrct/
x
OpCode
..... Points to a Working R~ster ~
Offset
.... Points to Origin of Working Register Group
Operand
-
~ValueUsed In In struction
Figure 11-5. Indexed Register Addressing
11-5
11.5 ZS DIRECT ADDRESSING (DA)
The Direct Addressing mode, as shown in Figure 11-6, specifies the address of the next instruction to be executed. Only the Conditional Jump (JP) and Call (CALL) instructions use this addressing mode.
Program Memory
i-
ZS' MICROCONTROLLERS
Program Memory Address Used
·-
Lower Addr. Byte Upper Addr. Byte
OpCode
I-
-
Figure 11·6. Direct Addressing
11-6
Zt' MICROCONTROLLERS
11.6 ZS RELATIVE ADDRESSING (RA)
In the Relative Addressing mode, illustrated in Figure 11-7, the instruction specifies a two's-complement signed displacement in the range of -128 to +127. This is added to the contents of the PC to obtain the address of the next
instruction to be executed. The PC (prior to the add) consists of the address of the instruction following the Jump Relative (JR) or Decrement and Jump if Non-Zero (DJNZ) instruction. JR and DJNZ are the only instructions which use this addressing mode.
Program Memory
II
Program Memory Address Used
NextOpCode
- JR orDJNZ
Displacement OpCode
Current
PCVU.~
Figure 11-7. Relative Addressing
11-7
7.8' MICROCONTROLLERS
11.7 ZS IMMEDIATE DATA ADDRESSING (IM}
Immediate data is considered an "addressing mode" for the purposes of this discussion. It is the only addressing mode that does not indicate a register or memory address
as the source operand. The operand value used by the instruction is the value supplied in the operand field itself. Because an immediate operand is part of the instruction, it is always located in the Program Memory address space (Figure 11-8).
Program Memory
OpCode Immediate Data
The Operand value is in the instruction
Figure 11·8. Immediate Data Addressing
11-8
4'2.iUJl:>
USER'S MANUAL
12.1 ZS FUNCTIONAL SUMMARY
za· instructions can be divided functionally into the follow-
ing eight groups:
Load
· Bit Manipulation · Arithmetic · Block Transfer · Logical · Rotate and Shift · Program Control ·· CPU Control
The following summary shows the instructions belonging to each group and the number of operands required for each. The source operand is 'src,' the destination operand is 'dst,'and a condition code is 'cc.'
Table 12·1. Load Instructions
Mnemonic Operands
Instruction
QR LD
ux;
l.ll: RY FU:H
ct:t
dst,src dst,src dst,src
ct:t
SC
Clear LLa:l L.a:dCcnstant l...cedExlernal R:p F\.Bi
Table 12-2. Arithmetic Instructions
Mnemonic Operands
Instruction
ADC ADD CP DA DEC DECW INC INCW SBC SUB
dst, src dst, src dst, src dst dst dst dst dst dst, src dst, src
Add with Carry Add Compare Decimal Adjust Decrement Decrement Word Increment Increment Word Subtract with Carry Subtract
CHAPTER 12
INSTRUCTION SET
Table 12-3. Logical Instructions
Mnemonic Operands Instruction
~
dst,src
~
a:M
ct:t
OJ1p:m:rt
CR
dst,src
Utjcala=l
)Ui
dst,src
LogicalExclusivea=l
Table 12-4. Program Control Instructions
Mnemonic Operands Instruction
~
Q.NZ
IRET ..P ..R RET
ct:t
dst,src
cc,dst cc,dst
callPrtx:edure DeaerrentardJ.rnp f\tn.Zero lnterruptRetum
J.ni:>
JumpRelalive Aelun
Table 12·5. Bit Manipulation Instructions
Mnemonic Operands Instruction
lOv1
dst,src
TeslCar4:Jierren
UnderMask
lM
dst,src
TestUnderMask
~
dst,src
BitClear
CR
dst,src
Bit Set
)Ui
dst,src
BitCarpErra1
Table 12-6. Block Transfer Instructions
Mnemonic Operands Instruction
LOO
dst,src
L.a:dQ:nstait
.AJ..doh:rernent
LIE
dst,src
l...cedExlernal
.AJ..dolncrement
II
12-1
12.1 Z8 FUNCTIONAL SUMMARY (Continued)
'1J' MICROCONTROUERS
Table 12·7. Rotate and Shift Instructions
Mnemonic Operands Instruction
RL RLC RR ARC SRA SWAP
dst
Rotate Left
dst
Rotate Left Through Carry
dst
Rotate Right
dst
Rotate Right Through Carry
dst
Shift Right Arithmetic
dst
Swap Nibbles
Table 12-8. CPU Control Instructions
Mnemonic Operands Instruction
CCF DI El HALT NOP ACF SCF SAP STOP WDH WOT
Complement Carry Flag
Disable Interrupts
Enable Interrupts
Halt
No Operation
Reset Carry Flag
Set Carry Flag
src
Set Register Pointer
Stop
WDT Enable During HALT
WDT Enable or Refresh
12.2 PROCESSOR FLAGS
The Flag Register (FCH} informs the user of the current status of the ZS. The flags and their bit positions in the Flag Register are shown in Figure 12-1.
The ZS Flag Register contains six bits of status information which are set or cleared by CPU operations. Four of the bits (C, V, Zand S) can be tested for use with conditional Jump instructions. Two flags (Hand D) cannot be tested and are used for BCD arithmetic. The two remaining bits in the Flag Register (F1 and F2) are available to the user, but they
must be set or cleared by instructions and are not usable with conditional Jumps.
As with bits in the other control registers, the Flag Register bits can be set or reset by instructions; however, only those instructions that do not affectthe flags as an outcome of the execution should be used (Load Immediate).
Note: The Watch-Dog Timer (WDT) instruction effects the Flags accordingly: Z=1, S=O, V=O.
Register FCH (Flags) Flag Register (Read/Write)
I011 oel osl 041 oal 021 01IooI
..,.....,.....,.....,.....,...~~""[
User Flag (F1) User Flag (F2) Half Carry Flag (H) Decimal Adjust Flag (D) Overflow Flag (V) Sign Flag (S) Zero Flag (Z) Carry Flag (C)
Figure 12·1. Z8 Flag Register
12-2
'1.ae MICROCOHTliOLLERS
12.2.1 Carry Flag (C)
12.2.4 Overflow Flag (V)
The Carry Flag is set to 1 whenever the result of an arithmetic operation generates a 'carry out of' or a 'borrow into' the high order bit 7. Otherwise, the Carry Flag is cleared to 0.
Following Rotate and Shift instructions, the Carry Flag contains the last value shifted out of the specified register.
An instruction can set, reset, or complement the Carry Flag.
IRET changes the value of the Carry Flag when the Flag Register saved in the Stack is restored.
12.2.2 Zero Flag (Z)
For arithmetic and logical operations, the Zero Flag is set to 1 if the result is zero. Otherwise, the Zero Flag is cleared
too.
If the result of testing bits in a register is OOH, the Zero Flag is set to 1. Otherwise the Zero Flag is cleared to 0.
If the result of a Rotate or Shift operation is OOH, the Zero Flag is set to 1. Otherwise, the Zero Flag is cleared to 0.
IRET changes the value of the Zero Flag when the Flag Register saved in the Stack is restored. The WOT Instruction sets the Zero Flag to a 1.
12.2.3 Sign Flag (S)
The Sign Flag stores the value of the most significant bit of a result following an arithmetic, logical, Rotate, or Shift operation.
When performing arithmetic operations on signed numbers, binary two's-complement notation is used to represent and process information. A positive number is identified by a 0 in the most significant bit position (bit 7); therefore, the Sign Flag is also 0.
For signed arithmetic, Rotate, and Shift operations, the Overflow Flag is set to 1 when the result is greater than the maximum possible number (>127) or less than the minimum possible number (<-128) that can be represented in two's-complement form. The Overflow Flag is set to 0 if no overflow occurs.
Following logical operations the Overflow Flag is set to 0.
II
IRET changes the value of the Overflow Flag when the Flag Register saved in the Stack is restored.
12.2.5 Decimal Adjust Flag (D)
The Decimal Adjust Flag is used for BCD arithmetic. Since the algorithm for correcting BCD operations is different for addition and subtraction, this flag specifies what type of instruction was last executed so that the subsequent Decimal Adjust (DA) operation can function properly. Normally, the Decimal Adjust Flag cannot be used as a test condition.
After a subtraction, the Decimal Adjust Flag is set to 1. Following an addition it is cleared to 0.
IRET changes the value of the Decimal Adjust Flag when the Flag Register saved in the Stack is restored.
12.2.6 Half Carry Flag (H)
The Half Carry Flag is set to 1 whenever an addition generates a "carry out of" bit 3 (Overflow) or a subtraction generates a "borrow into" bit 3. The Half Carry Flag is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (BCD) result. As in the case of the Decimal Adjust Flag, the user does not normally access this flag.
IRET changes the value of the Half Carry Flag when the Flag Register saved in the Stack is restored.
A negative number is identified by a 1 in the most significant bit position (bit 7); therefore, the Sign Flag is also 1.
IRET changes the value of the Sign Flag when the Flag Register saved in the Stack is restored.
12-3
'11' MICROCDNTROLLERS
12.3 CONDITION CODES
The C, Z, S, and V Flags control the operation of the 'Conditional' Jump instructions. Sixteen frequently useful functions of the flag settings are encoded in a 4-bit field called the condition code (cc), which forms bits 4-7 of the conditional instructions.
Table 12·9. Z8 Flag Definitions
Flag
Description
C
Carry Flag
Z
Zero Flag
S
Sign Flag
V
Overflow Flag
D
Decimal Adjust Flag
H
Half Carry Flag
Condition codes and flag settings are summarized inTables 12-9, 12-10, and 12-11. Notationfortheflagsand how they are affected are as follows:
Table 12·10. Flag Settings Definitions
Symbol
Definition
0
Cleared to 0
1
Setto 1
Set or cleared according to operation
Unaffected
x
Undefined
Binary
0000 1000 0111 1111 0110
1110 1101 0101 0100 1100
0110 1110 1001 0001 1010
0010 1111 0111 1011 0011
Mnemonic
F (blank)
c
NC
z
NZ PL Ml
ov
NOV
EQ NE GE LT GT
LE UGE ULT UGT ULE
Table 12·11. Condition Codes
Definition
Always False Always True Carry No Carry Zero
Non-Zero Plus Minus Overflow No Overflow
Equal Not Equal Greater Than or Equal Less Than Greater Than
Less Than or Equal Unsigned Greater Than or Equal Unsigned Less Than Unsigned Greater Than Unsigned Less Than or Equal
Flag Settings
C=1 C=O Z=1
Z=O S=O S=1 V=1 V=O
Z=1 Z=O (S XORV) = 0 (S XOR V) = 1 (Z OR (S XOR V)) = 0
(Z OR (S XOR V)) = 1 C=O C=1 (C = 0 AND Z = O) = 1 (C OR Z) = 1
12-4
.2il.CJ6
D' MICROCONlROLLERS
12.4 NOTATION AND BINARY ENCODING
In the detailed instruction descriptions that make up the rest of this chapter, operands and status flags are represented by a notational shorthand. Operands, condition
codes, address modes, and their notations are as follows (Table 12-12):
Notation cc R
RR
Ir IA
Irr IRA
x
DA RA IM
Table 12-12. Notational Shorthand
Address Mode
Operand
Range·
Condition Code
Working Register
Rn
Register
Reg
or
Working Register
Rn
Register Pair
Reg
or
Working Register Pair
RRp
Indirect Working Register
@Rn
Indirect Register or Indirect Working Register
@Reg @Rn
Indirect Working Register Pair @RRp
Indirect Register Pair
@Reg
or Working Register Pair Indexed
@RRp Reg (Rn)
Direct Address Relative Address
Add rs Addrs
Immediate
#Data
See condition codes n=0-15 Reg. represents a number in the range of OOH to FFH
n=0-15 Reg. represents an even number in the range of OOH to FEH
p = 0, 2, 4, 6, 8, 10, 12, or 14 n=0-15 Reg. represents a number in the range of OOH to FFH
n = 0-15 p = 0, 2, 4, 6, 8, 10, 12, or 14 Reg. represents an even number in the range OOH to FFH
p = 0, 2, 4, 6, 8, 10, 12, or 14 Reg. represents a number in the range of OOH to FFH andn=0-15 Addrs. represents a number in the range of OOH to FFH Addrs. represents a number in the range of +127 to -128 which is an offset relative to the address of the next instruction Data is a number between OOH to FFH
·See the device product specification to determine the exact register file range available. The register file size varies by device type.
12-5
12.4 NOTATION AND BINARY ENCODING (Continued)
'119 MICROCONTROLLERS
Additional symbols used are:
12.4.1 Assembly Language Syntax
Table 12·13. Additional Symbols
Symbol Definition
dst src
@
SP PC FLAGS RP IMR # % H B OPC
Destination Operand Source Operand Indirect Address Prefix Stack Pointer Program Counter Flag Register (FCH) Register Pointer (FDH) Interrupt Mask Register (FBH) Immediate Operand Prefix Hexadecimal Number Prefix Hexadecimal Number Suffix Binary Number Suffix Opcode
Assignment of a value is indicated by the symbol"+-·. For example,
For proper instruction execution, ZS assembly language syntax requires 'dst, src' be specified, in that order. The following instruction descriptions show the format of the object code produced by the assembler. This binary format should be followed by users who prefer manual program coding or who intend to implement their own assembler.
Example: If the contents of registers 43H and 08H are added and the result is stored in 43H, the assembly syntax and resulting object code is:
ASM: ADD 43H, OBH (ADD dst, src)
OBJ: 04
OB
43
(OPC src, dst)
In general, whenever an instruction format requires an B-bit register address, that address can specify any register location in the range 0- 255 or aWorking Register RO- R15. If, in the above example, register OBH is a Working Register, the assembly syntax and resulting object code would be:
dst +- dst + src
indicates the source data is added to the destination data and the result is stored in the destination location. The notation 'addr(n)' is used to refer to bit 'n' of a given location. For example,
ASM: ADD OBJ: 04
43H, RB
EB
43
(ADD dst, src) (OPC src, dst)
Note: See the device product specification todeterminethe exact register file range available. The register file size varies by device type.
dst(7)
refers to bit 7 of the destination operand.
12-6
ft'21Ul6
12.5 ZS INSTRUCTION SUMMARY
U' MICROCONTROLLERS
Instruction
Address Opcode Flags
and Operation Mode Byte (Hex) Affected
dst src
c z s v DH
ADC dst, src t
dSlf-dSt + src +C
1( 1 * * * * 0 *
ADD dst, src t
O[ 1
dstf-dst + src
AND dst, src t
5[ 1
dSlf-dSt AND src
CALL dst
DA
06
SPf-SP - 2 and IRR 04
PCf-dSt or
@SPf-PC
CCF
E F
Cf-NOT c
* ***0* - **0
- - - - --
*-- - --
CLRdst dS!f-0
R
BO
IR
81
COMdst
R
60
dslf-NOT dst IR
61
- **0
CP dst, src
t
dst - src
A[ l * * * *
DA dst
R
40
dslf-DA dst
IR
41
* * * x
DEC dst
R
00
dSlf-dSI - 1
IR
01
- ***--
DECW dst
RR
80
dSlf-dSI - 1
IR
81
- ***--
DI IMR(7)f-0
8F - - - - - -
DJNZ r, dst rf-r - 1
RA
rA
- --- --
r =0 - F
if r ":# 0, then
PCf-PC +dst
Range: +127,
-128
El IMR(7)f-1
9F
- - - - --
HALT
INC dst dSlf-dSI + 1
R IR
7F
rE
r =0 - F
20 21
- ***--
Instruction and Operation
INCW dst dSlf-dSI + 1
Address Mode dst src
RR IR
Opcode Byte(Hex)
AO A1
Flags Affected
c z s V DH
- ***--
IRET FLAGSf-@SP; SPf-SP + 1 PCf-@SP; SPf-SP + 2, and IMR(7)f-1
JP cc, dst
DA
if cc is true,
then PCf-dst IRR
JR cc, dst
RA
if cc Is true, then
PCf-PC +dst
Range: +127 to-128
LD dst, src dstf-src
Im r R R r
r x x r
r Ir
Ir r R R R IR R IM IR IM IR R
LDC dst, src dstf-src
r Irr Irr r
LOCI dst, src dstf-src and rf-r + 1 or rrf-rr +1
Ir Irr Irr r
LOE dst, src dstf-src
r Irr Irr r
LDEI dst, src dst f-Src and r f- r+1 or rr f-rr+1
r Irr Irr r
NOP
OR dst, src
t
dSlf-dSt OR src
BF
co
c =0 - F
30 cB
c =0 - F
re r8 r9
r =0 - F
C7 07 E3 F3 E4 E5 E6 E 7 F5 C2 02 C3 03
82 92 C2 02
FF
4[ 1
******
- - -- -- - - - -- - -- --
- - - --- - - - -- - - - ----- -- ---
- **0
II
12-7
~211.JJG
12.5 INSTRUCTION SUMMARY (Continued)
'ZP MICROCONTROLLERS
Instruction and Operation
Address Opcode Flags
Mode Byte (Hex) Affected
dst src
C Z S V DH
POP dst
R
50
dst+-@SP and I R
51
SP+-SP + 1
PUSH src
R
70
SP+-SP - 1 and I R
71
@SP+-src
RCF C+-0
RET PC+-@SP;
SP+-SP + 2
CF
0-----
AF
RL dst
R
90
IR
91
****""
RLC dst
R
10
IR
11
****""
RR dst RRC dst
R
EO
IR
E 1
R co IR c 1
****""
****--
SBC dst, src t
3( I
dst+-dst - src - C
SCF
OF
C+-1
SRA dst
R
DO
~ IR
01
SRP dst RP+-src
STOP
Im
31
6F
* * * 0
Instruction and Operation
SUB dst, src dsl+-dst - src
SWAP dst
§ 5 !1
o!
Address Opcode Flags
Mode Byte (Hex) Affected
dstsrc
CZSVDH
t
2[ I
R
FO
IR
F1
x * * x
TCM dst, src t (NOT dst)
AND src
TM dst, src
t
dst AND src
WDH
WOT
XOR dst, src t
dSl+-dSI
XOR src
6[ I
7( I - * * 0
4F
- xxx
SF
- xxx
B[ I - * * 0
t These instructions have an Identical set of addressing modes, which are encoded for brevity. The first Opcode nibble is found in the Instruction set table above. The second nibble is expressed symbolically by a'[ ]'in this table,andltsvaluelsfoundinthefollowingtabletotheleftoftheappllcable addressing mode pair.
For example, the Opcode of an ADC instruction using the addressing modes r (destination) and Ir (source) is 13.
Address Mode
dst
src
Ir
R
R
R
IR
R
IM
IR
IM
Lower Opcode Nibble
[2]
[3] [4] [5] [6] [7]
12-8
ZS' MICROCONTROLLERS
12.5.1 OPCODE MAP
Lower Nibble (Hex)
0
2
3
4
5
6
7
8
9
A
B
c
D
E
F
0
2 3 4 5 6
ie.
.!! 7
:z8
Iaaii.. 8
;:, 9 A B
c
D E F
6.5
6.5
6.5
6.5 10.5 10.5 10.5 10.5 6.5
6.5
DEC DEC ADD ADD ADD ADD ADD ADD LD LD
R1
IR1 r1, r2 r1, lr2 R2, R1 IR2, R1 R1, IM IR1,IM r1,R2 r2, R1
6.5
6.5
6.5
6.5 10.5 10.5 10.5 10.5
RLC RLC ADC ADC ADC ADC ADC ADC
R1
IR1 r1, r2 r1, lr2 R2, R1 IR2,R1 R1,IM IR1,IM
6.5
6.5
6.5
6.5 10.5 10.5 10.5 10.5
INC INC SUB SUB SUB SUB SUB SUB
R1
IR1 r1, r2 r1, lr2 R2, R1 IR2, R1 R1,IM IR1,IM
8.0 6.1
6.5
6.5 10.5 10.5 10.5 10.5
JP SRP SBC SBC SBC SBC SBC SBC
IRR1 IM
r1, r2 r1, lr2 R2, R1 IR2, R1 R1,IM IR1,IM
8.5
8.5
6.5
6.5 10.5 10.5 10.5 10.5
DA DA OR OR OR OR OR OR
R1
IR1 r1, r2 r1, lr2 R2, R1 IR2,R1 R1,IM IR1,IM
10.5 10.5 6.5
6.5 10.5 10.5 10.5 10.5
POP POP AND AND AND AND AND AND
R1
6.5
COM
IR1
6.5
COM
r1, r2
6.5
TCM
r1, lr2 R2, R1 IR2, R1 R1, IM IR1,IM
6.5 10.5 10.5 10.5 10.5
TCM TCM TCM TCM TCM
R1
IR1
10/12.1 12/14.1
PUSH PUSH
R2
IR2
10.5 10.5
DECW DECW
RR1 IR1
6.5
6.5
RL RL
R1
IR1
10.5 10.5
INCW INCW
r1, r2
6.5
TM
r1, r2
12.0
LOE
r1 lrr2
12.0
LOE
r2 lrr1 6.5
CP
r1, lr2 R2, R1
6.5 10.5
TM TM
r1, lr2 R2, R1
18.0
LDEI
lr1 lrr2
18.0
LDEI
lr2 lrr1 6.5 10.5
CP CP
IR2, R1 10.5 TM
IR2, R1
R1, IM
10.5
TM
R1, IM
10.5 10.5
CP CP
IR1, IM 10.5 TM
IR1, IM
10.5
CP
RR1
6.5
CLR
R1
6.5
ARC
IR1
6.5
CLR
IR1
6.5
RRC
r1 r2
6.5
XOR
r1, r2
12.0
LDC
r1, lr2
6.5
XOR
r1, lr2
18.0
LOCI
R2, R1
10.5
XOR
R2, Al
IR2,R1
10.5
XOR
IR2, R1
R1 IM
10.5
XOR
Rl, IM
IR1 IM
10.5
XOR
IR1,IM
10.5
LD
R1
IR1 r1, lrr2 lr1, lrr2
6.5
6.5
12.0 18.0 20.0
SRA SRA LDC LOCI CALL'
r1,x R2
20.0 10.5
CALL LO
R1
IR1 lrr1, r2 lrr1 lr2 IRR1
DA r2,x,R1
6.5
6.5
RR RR
6.5 10.5 10.5 10.5 10.5
LO LD LO LD LD
R1
8.5
SWAP
_fil_
IR1
8.5
SWAP
_Jfil
y
r1, IR2 R2,R1 IR2, R1 R1,IM IR1, IM
6.5
LO
lr1 r2
10.5
LD
R2 IR1
y
' l
2
3
Bytes per instruction
Lower
Opcode
. Execu!Jon
1Nibble
Pipeline
~~~~~-
Nibble~
12/10.5 12/10.0 6.5 12.10.0
DJNZ JR LD JP
r1,RA cc, RA r1, IM cc, DA
' *l
y
2
3
Legend:
R = 8-bit Address
r = 4-bit Address
R1 or r1 = Ost Address
R2 or r2 = Src Address
Sequence: Opcode, First Operand, Second Operand
Note: Blanks are reserved.
6.5
INC r1 I - - -
I---
1---i
'6.0 WDH
t-;;:o
WOT I---
6.0
STOP
t-y:o
HALT
t---s.;-
DI
ts:1 El
~
RET I---
16.0
IRET
t-e.s RCF
i-s:s SCF
t-e.s CCF
~
t NOP
v--'
El
First Operand
Second Operand
'2-byte instruction appears as a 3-byte instruction
12-9
12.6 INSTRUCTION DESCRIPTIONS AND FORMATS
ZS' MICROCONTROLLERS
ADC ADD WITH CARRY
ADC Add with Carry
ADCdst,src
Instruction Format:
OPC Address Mode
Cycles (Hex) dst
src
OPC I ldstlsrcl
OPC 11 src OPC 11 dst
11 dst 11 src
6
12
6
13
10 14 10 15
10 16 10 17
r Ir
R
R
R
IR
R
IM
IR
IM
Operation: Flags: Note:
dst<-dst + src + C
The source operand, along with the setting of the Carry (C) Flag, is added to the destination operand. Two's complement addition is performed. The sum is stored in the destination operand. The contents of the source operand are not affected. In multiple precision arithmetic, this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands.
C: Set if there is a carry from the most significant bit of the result; cleared otherwise. Z: Set if the result is zero; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if an arithmetic overflow occurs, that is, if both operands are of the same sign and
the result is of the opposite sign; cleared otherwise. D: Alwayscleared. H: Set if there is a carry from the most significant bit of the low order four bits of the result;
cleared otherwise.
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is specified by adding 111OB (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example:
If Working Register R3 contains 16H, the C Flag is set to 1, and Working Register R11 contains 20H, the statement:
ADCR3,R11 OpCode: 12 38
leaves the value 37H in Working Register R3. The C, Z, S, V, D, and H Flags are all cleared.
12-10
ADC ADD WITH CARRY
zr MICROCONTROLLERS
Example: Example:
If Working Register R16 contains 16H, the C Flag is not set, Working Register R10 contains 20H, and Register 20H contains 11 H. the statement:
ADC R16, @R10 Opcode: 13 FA
leaves the value 27H in Working Register R16. The C, Z, S, V, D, and H Flags are all cleared.
If Register 34H contains 2EH, the C Flag is set, and Register 12H contains 1BH, the statement:
ADC34H, 12H OpCode: 14 12 34
leaves the value 4AH in Register 34H. The H Flag is set, and the C, Z, S, V, and D Flags are cleared.
El
Example:
If Register 4BH contains 82H, the C Flag is set, Working Register R3 contains 10H. and Register 10H contains 01 H, the statement:
ADC4BH,@R3 OpCode: 15 E3 48
leaves the value 84H in Register 4BH. The S Flag is set. and the C, Z, V. D. and H Flags are cleared.
Example:
If Register 6CH contains 2AH. and the C Flag is not set, the statement:
ADC 6CH, #03H OpCode: 16 6C 03
leaves the value 2DH in Register 6CH. The C, Z, S, V, D, and H Flags are all cleared.
Example:
If Register D4H contains SFH, Register SFH contains 4CH, and the C Flag is set, the statement:
ADC @D4H,#02H OpCode: 17 D4 02
leaves the value 4FH in Register SFH. The C, Z, S, V, D,.and H Flags are all cleared.
12-11
ftl21Ul6
ADD Add
ADDdst,src
Instruction Format:
I OPC ldstlsrcl
I I OPC 11 src
dst
II OPC 11 dst
src
OPC Address Mode
Cycles (Hex) dst
src
6
02
6
03
10 04 10 05
10 06 10 07
r Ir
A
A
R
IA
A
IM
IA
IM
'II' MICROCONTROLLERS
ADD ADD
Operation: Flags: Note:
dst <- dst + src
The source operand is added to the destination operand. Two's complement addition is performed. The sum is stored in the destination operand. The contents of the source operand are not affected.
C: Set if there is a carry from the most significant bit of the result; cleared otherwise. Z: Set if the result is zero; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if an arithmetic overflow occurs, that is, if both operands are of the same sign and
the result is of the opposite sign; cleared otherwise. D: Alwayscleared. H: Set if there is a carry from the most significant bit of the low order four bits of the result;
cleared otherwise.
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is specified by adding 111 OB (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example: Example:
If Working Register R3contains 16H and Working Register R11 contains 20H, the statement:
ADD RS, R11 OpCode: 02 38
leaves the value 36H in Working Register R3. The C, Z, S, V, D, and H Flags are all cleared.
If Working Register R16 contains 16H, Working Register R10 contains 20H, and Register 20H contains 11 H, the statement:
ADD R16, OR10 OpCode: 03 FA leaves the value 27H in Working Register R16. The C, Z, S, V, D, and H Flags are all cleared.
12-12
ft' ZiUJ6
ADD ADD
'1J' MlcROCONTROWRS
Example: Example:
If Register 34H contains 2EH and Register 12H contains 1BH, the statement:
ADD34H, 12H OpCode: 04 12 34
leaves the value 49H in Register 34H. The H Flag is set, and the C, Z, S, V, and D Flags are cleared.
If Register 4BH contains 82H, Working Register R3 contains 10H, and Register 10H contains 01H, the statement:
ADD3EH, OR3 OpCode: 05 E3 4B
leaves the value 83H in Register4BH. The S Flag is set, and the C, Z, V, D, and H Flags are cleared.
II
Example:
If Register 6CH contains 2AH, the statement:
ADD &CH, #03H OpCode: 06 &C 03
leaves the value 2DH in Register 6CH. The C, Z, S, V, D, and H Flags are all cleared.
Example:
If Register D4H contains 5FH and Register 5FH contains 4CH, the statement:
ADD OD4H, #02H OpCode: 07 D4 02
leaves the value 4EH in Register 5FH. The C, Z, S, V, D, and H Flags are all cleared.
12-13
AND Logical AND
ANDdst,src
Instruction Format:
I OPC lds1lsrcl
OPC 11 src OPC 11 dst
11 dst 11 src
'lJ9 MICROCONTllOWRS
AND LOGICAL AND
OPC Address Mode
Cycles (Hex) dst
src
6
52
6
53
10 54 10 55
10 56 10 57
r Ir
R
R
R
IR
R
IM
IA
IM
Operation: Flags: Note:
dst <- dst AND src
The source operand is logically ANDed with the destination operand. The AND operation results in a 1 being stored whenever the corresponding bits in the two operands are both 1, otherwise a 0 is stored. The result is stored in the destination operand. The contents of the source bit are not affected.
C: Unaffected Z: Set if the result is zero; cleared otherwise S: Set if the result of bit 7 is set; cleared otherwise V: Always reset to 0 D: Unaffected H: Unaffected
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is specified by adding 111 OB (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example: Example:
If Working Register R1 contains 34H (001110006) and Working Register R14 contains 4DH (10001101), the statement:
AND R1, R14 OpCode: 52 1E
leaves the value 04H (00001000) in Working Register R1. The Z, V, and S Flags are cleared.
If Working Register R4 contains F9H (11111001 B), Working Register R13 contains 7BH, and Register 7BH contains 6AH (011010106), the statement:
ANDR4, OR13 OpCode: 53 4D
leaves the value 68H (01101 OOOB) in Working Register R4. The Z, V, and S Flags are cleared.
12-14
AND LOGICAL AND
1' MlcRocoNTROLLERS
Example:
If Register 3AH contains the value F5H (111101010) and Register 42H contains the value OAH (00001010), the statement:
AND3AH,42H OpCode: 54 42 3A
leaves the value OOH (OOOOOOOOB) in Register 3AH. The Z Flag is set, and the V and S Flags are cleared.
El
Example:
If Working Register R5 contains FOH ( 111100008), Register 45H contains 3AH, and Register 3AH contains 7FH (011111118), the statement:
AND RS, 045H OpCode: 55 45 ES
leaves the value ?OH (011100008) in Working Register R5. The Z, V, and S Flags are cleared.
Example:
If Register 7AH contains the value F7H (111101118), the statement:
AND 7AH, #FOH OpCode: 56 7A FO
leaves the value FOH (111100008) in Register 7AH. The SFlag is set, and the Zand V Flags are cleared.
Example:
If Working Register R3 contains the value 3EH and Register 3EH contains the value ECH (111011008), the statement:
AND OR3, #05H OpCode: 57 E3 05
z. leaves the value 04H (000001008) in Register 3EH. The V, and S Flags are cleared.
12-15
CALL Call Procedure
CALLdat
Instruction Format:
'lJ' MICROCONlllOLLERS
CALL CALL PROCEDURE
OPC Address Mode
Cycles (Hex)
dst
Operation: Flags:
OPC 11
dst
II OPC
dst
SP <-SP-2 @SP<- PC PC<-dst
20 06
DA
20 04
IRA
The Stack pointer is decremented by two, the current contents of the Program Counter (PC) (address of the first instruction following the CALL instruction) are pushed onto the top of the Stack, and the specified destination address is then loaded into the PC. The PC now points to the first instruction of the procedure.
At the end of the procedure a RET (return) instruction can be used to return to the original program flow. RET will pop the top of the Stack and replace the original value into the PC.
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
Note:
Address mode IRA can be used to specify a 4-bitWorking Register Pair. In this format, the
destination Working Register Pair operand is specified by adding 11108 (EH) to the high nibble of the operand. For example, if Working Register Pair RR12 (CH) is the destination
operand, then ECH will be used as the destination operand in the OpCode.
Example:
If the contents of the PC are 1A47H and the contents of the SP (Registers FEH and FFH) are 3002H, the statement:
CALL3521H OpCode: D6 35 21
causes the SP to be decremented to 3000H, 1A4AH (the address following the CALL instruction) to be stored in external data memory 3000 and 3001 H, and the PC to be loaded with 3521 H. The PC now points to the address of the first statement in the procedure to be executed.
12-16
CALL CALL PROCEDURE
7J8 MICROCONTROLIERS
Example:
If the contents of the PC are 1A47H, the contents of the SP (Register FFH) are 72H, the contents of Register A4H are 34H, and the contents of Register Pair 34H are 3521H, the statement:
CALLOA4H OpCode: D4 A4
causes the SP to be decremented to ?OH, 1A4AH (the address following the CALL instruction) to be stored in R70H and 71 H, and the PC to be loaded with 3521 H. The PC now points to the address of the first statement in the procedure to be executed.
12-17
CCF Complement carry Flag CCF Instruction Format:
OPC
OPC Cycles (Hex)
6 EF
'1J' MICROCOHTROLLERS
CCF COMPLEMENT CARRY FLAG
Operation: Flags: Example:
C<-NOTC
TheCFlag iscomplemented. lfC= 1, then itischangedtoC=O:or, ifC=O, then it is changed toC= 1.
C: Complemented Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
If the C Flag contains a 0, the statement:
CCF OpCode: EF
will change the C Flag from C = 0 to C = 1.
12-18
CLR CLEAR
'lJ' lllclloCoNTROWRS
CLR CLEAR
CLRdst
Instruction Format:
OPC Address Mode
Cycles (Hex)
dst
I I OPC
dst
6 BO
R
6
81
IR
Operation: Flags:
Note:
dst<-0
The destination operand is cleared to OOH.
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 11108 (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example:
If Working Register R6 contains AFH, the statement:
CLRR6
OpCode: BO E6
will leave the value OOH in Working Register R6.
If Register ASH contains the value 23H, and Register 23H contains the value FCH, the statement:
CLR OASH OpCode: B1 A5 will leave the value OOH in Register 23H.
12-19
COM Complement
COMdst
Instruction Format:
II OPC
dst
OPC Address Mode
Cycles (Hex)
dst
6
60
A
6
61
IA
COM COMPLEMENT
Operation:
Flags:
Note:
dst <-NOT dst
The contents of the destination operand are complemented (one's complement). All 1 bits are changed to 0, and all 0 bits are changed to 1.
C: Unaffected Z: Set if the result is zero; cleared otherwise. S: Set if result bit 7 is set; cleared otherwise. V: Always reset to 0. D: Unaffected H: Unaffected
Address modes R or JR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 11108 (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example: Example:
If Register 08H contains 24H (001001008), the statement:
COM08H OpCode: 60 08
leaves the value D8H (11011011) in Register 08H. The S Flag is set, and the Zand V Flags are cleared.
If Register 08H contains 24H, and Register 24H contains FFH (11111111 B), the statement:
COM@08H OpCode: 61 08
leaves the value OOH (000000008) in Register 24H. The Z Flag is set, and the V and S Flags are cleared.
12-20
CP COMPARE
CP Compare CP dst, src
Instruction Format:
OPC lldstlsrcl
OPC 11 src OPC 11 dst
11 dst 11 src
OPC Address Mode
Cycles (Hex) dst
src
6
A2.
6
A3
10
A4
10
AS
10
AS
10
A7
r Ir
R
R
R
IR
R
IM
IR
IM
Z8' MICROCONTROUERS
II
Operation: Note:
dst-src
The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected.
C: Cleared if there is a carry from the most significant bit of the result. Set otherwise indicating a borrow.
Z: Set if the result is zero; cleared otherwise. S: Set if result bit 7 is set (negative); cleared otherwise. V: Set if arithmetic overflow occurs; cleared otherwise. D: Unaffected H: Unaffected
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the
source or destination Working Register operand is specified by adding 111OB (EH) to the high
nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example: Example:
If Working Register R3 contains 16H and Working Register R11 contains 20H, the statement: CP R3, R11 OpCode: A2. 38
sets the C and S Flags, and the Z and V Flags are cleared.
If Working Register R15 contains 16H, Working Register R10 contains 20H, and Register 20H contains 11 H, the statement:
CPR16, OR10 OpCode: A3 FA
clears the C, Z, S, and V Flags.
12-21
Example: Example: Example: Example:
U" MICROCONlHOLLERS
CP COMPARE
If Register 34H contains 2EH and Register 12H contains 1BH, the statement: CP34H,12H OpCode: A4 12 34
clears the C, Z, S, and V Flags.
If Register 4BH contains 82H, Working Register R3 contains 1OH, and Register 1OH contains 01 H, the statement:
CP4BH,@R3 OpCode: AS E3 48 sets the S Flag, and clears the C, Z, and V Flags.
If Register 6CH contains 2AH, the statement: CP6CH,#2AH OpCode: A6 6C 2A
sets the Z Flag, and the C, S, and V Flags are all cleared.
If Register D4H contains FCH, and Register SFH contains FCH, the statement: CP@D4H, 7FH OpCode: A7 D4 FF
sets the V Flag, and the C, Z, and S Flags are all cleared.
12-22
't'2iUl6
DA DECIMAL ADJUST
DA Decimal Adjust
DAdst
Instruction Format:
OPC Address Mode
Cycles (Hex)
dst
zr MICROCOHTROLLERS
11 OPC
dst
8
40
R
8
41
IR
Operation:
dst<-DAdst
The destination operand is adjusted to form two 4-bit BCD digits following a binary addition or subtraction operation on BCD encoded bytes. For addition (ADD and ADC) or subtraction (SUB and SBC), the following table indicates the operation performed.
Instruction
ADD ADC
SUB SBC
Carry Before
DA
0 0 0 0 0 0 1 1 1
0 0 1 1
Bits 7-4 Value (HEX)
0-9 0-8 0-9 A-F 9-F A-F 0-2 0-2 0-3
0-9 0-8 7-F 6-F
HFlag Before
DA
0 0 1 0 0 1 0 0 1
0 1 0 1
Bits 3-0 Value (HEX)
0-9 A-F 0-3 0-9 A-F 0-3 0-9 A-F 0-3
0-9 6-F 0-9 6-F
Number Added To
Byte
00 06 06 60 66 66 60 66 66
00 FA
AO
9A
Carry After DA
0 0 0 1 1 1 1 1 1
0 0 1 1
Flags:
If the destination operand is not the result of a valid addition or subtraction of BCD digits, the operation is undefined.
C: Set if there is a carry from the most significant bit; cleared otherwise (see table above). Z: Set if the result is zero; cleared otherwise. S: Set if result bit 7 is set (negative); cleared otherwise. V: Undefined D: Unaffected H: Unaffected
12-23
Note:
DA DECIMAL ADJUST
Address modes R or IA can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 11108 (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example:
If addition is performed using the BCD value 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic.
= 0001 0101 15H
+ Q0.1Q w..11 = 2Zl::l 0011 1100 = 3CH
If the result of the addition is stored in Register 5FH, the statement: DA5FH OpCode: 40 5F
adjusts this result so the correct BCD representation is obtained.
0011 1100 = 3CH JJlXlQ Q.110 = Q6l::l
0100 0010 = 42H
Register 5F now contains the value 42H. The C, Z, and S Flags are cleared, and V is undefined.
Example:
If addition is performed using the BCD value 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic.
= 0001 0101 15H
+ Q0.1Q w..11 = 2Zl::l
0011 1100 = 3CH
If Register 45F contains the value 5FH, and the result of the addition is stored in Register 5FH, the statement:
DA045H OpCode: 40 45
adjusts this result so the correct BCD representation is obtained.
0011 1100 = 3CH .OQQQ Q.110 = Q6l::l 0100 0010 = 42H
Register 5F now contains the value 42H. The C, Z, and S Flags are cleared, and V is undefined.
12-24
DEC DECREMENT
DEC Decrement DEC dst Instruction Format:
OPC Address Mode
Cycles (Hex)
clst
Z8" MICROCONTROLLERS
Ill
11 OPC
dst
6
00
R
6
01
IR
Operation: Flags:
Note:
dst<-dst-1
The contents of the destination operand are decremented by one.
C: Unaffected Z: Set if the result is zero; cleared otherwise S: Set if the result of bit 7 is set (negative); cleared otherwise V: Set if arithmetic overflow occurs; cleared otherwise D: Unaffected H: Unaffected
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 11108 (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example: Example:
If Working Register R10 contains 2A%, the statement: DECR10 OpCode: 00 EA
leaves the value 29H in Working Register R10. The Z, V, and S Flags are cleared.
If Register 83H contains CBH, and Register CBH contains 01H, the statement: DEC@B3H OpCode: 01 B3
leaves the value OOH in Register CBH. The Z Flag is set, and the V and S Flags are cleared.
12-25
DECW Decrement Word
DECWdst
Instruction Format:
D' MICROCONTROLLERS
DECW DECREMENT WORD
OPC Address Mode
Cycles (Hex)
dst
11 OPC
dst
10 80
RR
10 81
IR
Operation: Flags: Note:
dst<-dst-1
The contents of the destination {which must be an even address) operand are decremented by one. The destination operand can be a Register Pair or a Working Register Pair.
C: Unaffected Z: Set if the result is zero; cleared otherwise S: Set if the result of bit 7 is set {negative); cleared otherwise V: Set if arithmetic overflow occurs; cleared otherwise D: Unaffected H: Unaffected
Address modes RR or IA can be used to specify a 4-bitWorking Register Pair. In this format, the destination Working Register Pair operand is specified by adding 111 OB {EH) to the high nibble of the operand. For example, if Working Register Pair R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example: Example:
If Register Pair 30H and 31H contain the value OAF2H, the statement:
DECW30H OpCoda: 80 30
leaves the value OAF1H in Register Pair 30H and 31H. The Z, V, and S Flags are cleared.
If Working Register RO contains 30H and Register Pairs 30H and 31H contain the value FAF3H, the statement:
DECWORO OpCode: 81 EO
leaves the value FAF2H in Register Pair 30H and 31 H. The S Flag is set, and the Z and V Flags are cleared.
12-26
DI DISABLE INTERRUPTS
DI Disable Interrupts
DI
Instruction Format:
OPC Cycles (Hex)
mt MICROCONTROLl.ERS
II
OPC
6 SF
Operation: Flags: Example:
IMR (7) <-0
Bit 7 of Control Register FBH (the Interrupt Mask Register) is reset to 0. All interrupts are disabled, although they remain "potentially" enabled. (For instance, the Global Interrupt Enable is cleared, but not the individual interrupt level enables.)
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
If Control Register FBH contains BAH (10001010) (interrupts IRQ1 and IRQ3 are enabled), the statement:
DI OpCode: BF
sets Control Register FBH to OAH (000010108) and disables these interrupts.
12-27
<t'2il.CE
DJNZ
Decrement and Jump if Non-zero
DJNZr, dst Instruction Format:
zr MICROCONTROLLERS DJNZ
DECREMENTANDJUMPIFNONZERO
Cycles
OPC Address Mode
(Hex)
dst
12 if jump taken
rA
RA
= 10 if jump nottaken (r O to F)
Operation: Flags: Note:
r<-r-1; If r <> 0, PC <-PC + dst
The specified Working Register being used as a counter is decremented. If the contents of the specified Working Register are not zero after decrementing, then the relative address is added to the Program Counter (PC) and control passes to the statement whose address is
now in the PC. The range of the relative address is +127 to -128. The original value of the
PC is the address of the instruction byte following the DJNZ statement. When the specified Working Register counter reaches zero, control falls through to the statement following the DJNZ instruction.
C: Unaffected Z: Unaffected S: Unaffected
V: Unaffected
D: Unaffected H: Unaffected
The Working Register being used as a counter must be one of the Registers from 04H to EFH. Use of one of the 1/0 ports, control or peripheral registers will have undefined results.
Example:
DJNZ is typically used to control a "loop" of instructions. In this example, 12 bytes are moved from one buffer area in the register file to another. The steps involved are:
· Load 12 into the counter (Working Register R6).
· Set up the loop to perform the moves.
· End the loop with DJNZ.
The assembly listing required for this routine is as follows:
LOOP:
LO R6, 12 LD R9, @R6 LD @R6, R9 DJNZ R6, LOOP
;Load Counter :Move one byte to ;new location ;Decrement and Loop until
;counter= 0
12-28
El
ENABLE INTERRUPTS
El Enable Interrupts
El
Instruction Format:
OPC Cycles (Hex)
OPC
6
9F
Operation: Flags: Example:
IMR (7) <-0
Bit 7 of Control Register FBH (the Interrupt Mask Register) is set to 1. This allows potentially enabled interrupts to become enabled.
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
If Control Register FBH contains OAH (00001010) (interrupts IRQ1 and IRQ3 are selected), the statement:
El OpCode: 9F
sets Control Register FBH to BAH (100010106) and enables IRQ1 and IRQ3.
II
12-29
HALT
Halt
HALT
Instruction Format:
OPC Cycles (Hex)
6 7F
'lJ' MICROCONTROLLERS
HALT HALT
Operation: Flags:
Note: Example:
The HALT instruction turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and the external interrupts IAQ1, IAQ2, and IAQ3 remain active. The devices are recovered by interrupts, either externally or internally generated.
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
In order to enter HALT mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. The user must execute a NOP immediately before the execution of the HALT instruction.
Assuming the ZS is in normal operation, the statements:
NOP
HALT
OpCodea: FF 7F
place the ZS into HALT mode.
12-30
INC INCREMENT
INC Increment
INCdst
Instruction Format:
Idst lapel
11 OPC
dst
OPC Address Mode
Cycles (Hex)
dst
6
rE
6
20
R
6
21
IR
Operation: Flags:
Note:
dst<-dst+ 1
The contents of the destination operand are incremented by one.
C: Unaffected Z: Set if the result is zero; cleared otherwise. S: Set if the result of bit 7 is set (negative); cleared otherwise. V: Set if arithmetic overflow occurs; cleared otherwise. D: Unaffected H: Unaffected
Address modes A or IA can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 111 OB (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
II
Example: Example: Example:
If Working Register R10 contains 2AH, the statement: INCR10 OpCode: AE
leaves the value 2BH in Working Register R10. The Z, V, and S Flags are cleared.
If Register B3H contains CBH, the statement: INC83H OpCode: 20 83
leaves the value CCH in Register CBH. The SFlag is set, and the Zand V Flags are cleared.
If Register 83H contains CBH and Register BCH contains FFH, the statement: INCOB3H OpCode: 21 83
leaves the value OOH in Register CBH. The Z Flag is set, and the V and S Flags are cleared.
12-31
INCW Increment Word
INCWdst
Instruction Format:
I I OPC
dst
OPC Address Mode
Cycles (Hex)
dst
10 AO
RR
10
A1
JR
D' MICROCONTROUERS
INCW INCREMENT WORD
Operation: Flags: Note:
dst<-dst-1
The contents of the destination (which must be an even address) operand is decremented by one. The destination operand can be a Register Pair or a Working Register Pair.
C: Unaffected Z: Set if the result is zero; cleared otherwise. S: Set if the result of bit 7 is set (negative); cleared otherwise. V: Set if arithmetic overflow occurs; cleared otherwise. D: Unaffected H: Unaffected
Address modes RR or IR can be used to specify a 4-bit Working Register Pair. In this format, the destination Working Register Pair operand is specified by adding 111 OB (EH) to the high nibble of the operand. For example, if Working Register Pair R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example: Example:
If Register Pairs 30H and 31 H contain the value OAF2H, the statement:
INCW30H OpCode: AO 30
leaves the value OAF3H in Register Pair 30H and 31H. The Z, V, and S Flags are cleared.
If Working Register RO contains 30H, and Register Pairs 30H and 31H contain the value FAF3H, the statement:
INCW@RO OpCode: A1 EO
leaves the value FAF4H in Register Pair 30H and 31H. The S Flag is set, and the Zand V Flags are cleared.
12·32
IRET INTERRUPT RETURN
IRET Interrupt RETURN
IRET
Instruction Format:
OPC
Cycles (Hex)
OPC
16 BF
'lJI MICROCONTROUERS
II
Operation: Flags: Example:
FLAGS<- @SP SP <-SP+ 1 PC<- @SP SP <-SP+ 2 IMR(7) <-1
This instruction is issued attheend of an interruptservice routine. It restores the Flag Register (Control Register FCH) and the PC. It also re-enables any interrupts that are potentially enabled.
C: Restored to original setting before the interrupt occurred. Z: Restored to original setting before the interrupt occurred. S: Restored to original setting before the interrupt occurred. V: Restored to original setting before the interrupt occurred. D: Restored to original setting before the interrupt occurred. H: Restored to original setting before the interrupt occurred.
If Stack Pointer Low Register FFH currently contains the value 45H, Register 45H contains the value OOH, Register 46H contains 6FH, and Register 47 Contains E4H, the statement:
IRET OpCode: BF
restores the FLAG Register FCH with the value OOH, restores the PC with the value 6FE4H, re-enables the interrupts, and sets the Stack Pointer Low to 48H. The next instruction to be executed will be at location 6FE4H.
12-33
JP JUMP
JPcc,dst
Instruction Format:
I cc loPcl I dst
11 OPC
dst
'II' MICROCONTROLLERS
JP JUMP
Cycles
OPC Address Mode
(Hex)
dst
12 ifjumptaken ccD
DA
10 if not taken cc=Oto F
8
30
IRA
Operation: Flags: Note:
If cc (condition code) is true, then PC <-dst
A conditional jump transfers Program Control to the destination address if the condition specified by cc (condition code) is true. Otherwise, the instruction following the JP instruction is executed. See Section 12.3 for a list of condition codes.
The unconditional jump simply replaces the contents of the Program Counter with the contents of the register pair specified by the destination operand. Program Control then passes to the instruction addressed by the PC.
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
Address mode IRR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 11108 (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example: Example: 12-34
If the Carry Flag is set, the statement:
JPC, 1520H OpCode: 7D 15 20
replaces the contents of the Program Counter with 1520H and transfers program control to that location. If the Carry Flag had not been set, control would have fallen through to the statement following the JP instruction.
If Working Register Pair RR2 contains the value 3F45H, the statement:
JP ORR2 OpCode: 30 E2
replaces the contents of the PC with the value 3F45H and transfers program control to that location.
JR JUMP RELATIVE
JR Jump Relative
JR cc, dst
Instruction Format:
Cycles
OPC Address Mode
(Hex)
dst
Operation: Flags: Example: Example:
10 If jump taken
ccB
RA
12 if jump not taken cc = 0 to F
If cc is true, PC <-PC + dst
Ifthe condition specified bythe "cc' is true, the relative address is added to the PC and control passes to the instruction located at the address specified by the PC (See Section 12.3 for a
list of condition codes). Otherwise, the instruction following the JR instruction is executed. The range of the relative address is +127 to -128, and the original value of the PC is taken to be the address of the first instruction byte following the JR instruction.
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
If the result of the last arithmetic operation executed is negative, the next four statements (which occupy a total of seven bytes) are skipped with the statement:
JRMl,#9 OpCode: SB 09
If the result was not negative, execution would have continued with the instruction following the JR instruction.
A short form of a jump -45 is:
JR#-45 OpCode: 88 D3
The condition code is "blank' in this case, and is assumed to be "always true.·
II
12-35
LO LOAD
LO Load
LDdst, src
Instruction Format:
dst loPcl
src lope
OPC
src
dst
I I dst src
OPC
src
dst
OPC
dst
src
OPC Address Mode Cycles (Hex) dst src
6
rC
IM
6
r8
R
6
r9
R*
r=Oto F
6
E3
r
Ir
6
F3
Ir
10 E4 10 ES
R
R
R
IR
10 ES 10 E7
R IM IR IM
OPC
src
dst
OPC
Idst x
src
OPC
Isrc x
dst
10 F5
IR
R
10 C7
x
10 07
x
In this instance, only a fu 8-bit register can be used.
Operation: dst <- src
The contents of the source operand are loaded into the destination operand. The contents of the source operand are not affected.
Flags: Note:
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is specified by adding 111 OB (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
12-36
ft' 2JUJ6
LO LOAD
'1J' MICROCONTROLLERS
Example: Example: Example: Example:
The statement:
LD R15, #34H OpCode: FC 34
loads the value 34H into Working Register R15.
If Register 34H contains the value FCH, the statement:
LDR14,34H OpCode: F8 34
loads the value FCH into Working Register R15. The contents of Register 34H are not affected.
If Working Register R14 contains the value 45H, the statement:
LD 34H, R14 OpCode: E9 34
loads the value 45H into Register 34H. The contents of Working Register R14 are not affected.
If Working Register R12 contains the value 34H, and Register 34H contains the value FFH, the statement:
LD R13, @R12 OpCode: E3 DC
loads the value FFH into Working Register R13. The contents of Working Register R12 and Register R34 are not affected.
II
Example: Example:
If Working Register R13 contains the value 45H, and Working Register R12 contains the value OOH the statement:
LD@R13, R12 OpCode: F3 DC
loads the value OOH into Register 45H. The contents of Working Register R12 and Working Register R13 are not affected.
If Register 45H contains the value CFH, the statement:
LD34H,45H OpCode: E4 45 34
loads the value CFH into Register 34H. The contents of Register 45H are not affected.
12-37
Example: Example: Example: Example: Example: Example:
7J' MICROCONTROLllRS
LD LOAD
If Register 45H contains the value CFH and Register CFH contains the value FFH, the statement:
LD34H, 045H OpCode: ES 45 34
loads the value FFH into Register 34H. The contents of Register 45H and Register CFH are not affected.
The statement:
LD 34H,#A4H OpCode: E& 34 A4
loads the value A4H into Register 34H.
If Working Register R14 contains the value 7FH, the statement:
LD OR14, #FCH OpCode: E7 EE FC
loads the value FCH into Register 7FH. The contents of Working Register R14 are not affected.
If Register 34H contains the value CFH and Register 45H contains the value FFH, the statement:
LD 034H,45H OpCode: FS 45 34
loads the value FFH into Register CFH. The contents of Register 34H and Register 45H are not affected.
= IfWorking Register RO contains the value OBH and Register 2CH (24H + OBH 2CH) contains
the value 4FH, the statement:
LD R10, 24H(RO) OpCode: C7 AO 24
loads Working Register R10 with the value 4FH. The contents of Working Register RO and Register 2CH are not affected.
If Working Register RO contains the value OBH and Working Register R10 contains 83H the statement:
LD FOH(RO), R10 OpCode: 07 AO FO
loads the value 83H into Register FBH (FOH + OBH = FBH). Since this is the Interrupt Mask Register, the LOAD statement has the effect of enabling IRQO and IRQ1. The contents of Working Registers RO and R10 are unaffected by the load.
12-38
LDC LOAD CONSTANT
LDC Load Constant LDCdst, src Instruction Format:
OPC lldmlsrcl OPC lldmlsrcl
Cycles (OHPeCx)
Adsdrcress
Mode dst
12 C2
Irr
12 02
Irr
'11' MICROCONTROUERS
II
Operation: Flags: Example: Example:
dst<-src
This instruction is used to load a byte constantfrom program memory into a Working Register, or vice versa. The address ofthe program memory location is specified by aWorking Register Pair. The contents of the source operand are not affected.
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
If Working Register Pair R6 and R7 contain the value 30A2H and program memory location 30A2H contains the value 22H, the statement:
LDCR2,@RR6 OpCode: C2 26
loads the value 22H into Working Register R2. The value of program memory location 30A2H is unchanged by the load.
If Working Register R2 contains the value 22H, and Working Register Pair R6 and R7 contains the value 10A2H, the statement:
LDC@RR6,R2 OpCode: 02 26
loads the value 22H into program memory location 10A2H. The value of Working Register R2 is unchanged by the load.
Note: This instruction format is valid only for MCUs which can address external program memory.
12-39
LOCI Load Constant Auto-Increment LOCI dst, src Instruction Format:
I OPC ldstlsrcl I OPC ldstlsrcl
1H' MICROCONlROUERS
LOCI LOAD CONSTANT AUTO-INCREMENT
OPC Cycles (Hex)
Address Mode src dst
18 C3
Ir
Irr
18 03
Irr
Ir
Operation:
Flags: Example:
dst<-src r <-r + 1 rr <-rr+ 1
This instruction is used for block transfers of data between program memory and the Register File. The address of the program memory location is specified by a Working Register Pair, and the address of the Register File location is specified by Working Register. The contents of the source location are loaded into the destination location. Both addresses in the Working Registers are then incremented automatically. The contents of the source operand are not affected.
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
If Working Register Pair R6-R7 contains 30A2H, program memory location 30A2H and 30A3H contain 22H and BCH respectively, and Working Register R2 contains 20H, the statement:
LOCI OR2, ORR& OpCode: C3 26
loads the value 22H into Register 20H. Working Register Pair RR6 is incremented to 30A3H and Working Register R2 is incremented to 21 H. A second
LOCI OR2, ORR& OpCode: C3 26
loads the value BCH into Register 21 H. Working Register Pair RR6 is incremented to 30A4H and Working Register R2 is incremented to 22H.
Note: This instruction format is valid only for MCUs which can address external program memory.
1240
LOCI LOAD CONSTANT AUTO-INCREMENT
'1JI MICROCONTROu.ERS
Example:
If Working Register R2 contains 20H, Register 20H contains 22H, Register 21H contains BCH, and Working Register Pair R6-R7 contains 30A2H, the statement:
LDCI ORR&, @R2 OpCode: D3 26
loads the value 22H into program memory location 30A2H. Working Register R2 is incremented to 21 H and Working Register Pair R6-R7 is incremented to 30A3H. A second
LDCI ORR&, @R2 OpCode: D3 26
loads the value BCH into program memory location 30A3H. Working Register R2 is incremented to 22H and Working Register Pair R6-R7 is incremented to 30A4H.
II
12-41
LDE Load External Data LDEdst,src Instruction Format:
OPC lldstlsrcl OPC llsrclctstl
D' MICROCONTROLLERS
LOE LOAD EXTERNAL DATA
OPC Address Mode
Cycles (Hex)
SIC dst
12 82
Irr
12 92
Irr
Operation: Flags: Example: Example:
dst<-src
This instruction is used to load a byte from external data memory into a Working Register or vice versa. The address of the external data memory location is specified by a Working Register Pair. The contents of the source operand are not affected.
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
If Working Register Pair R6 and R7 contain the value 40A2H and external data memory location 40A2H contains the value 22H, the statement:
LDER2, ORR& OpCode: 82 26
loads the value 22H into Working Register R2. The value of external data memory location 40A2H is unchanged by the load.
If Working Register Pair R6 and R7 contain the value 404AH and Working Register R2 contains the value 22H, the statement:
LDE ORR6,R2 OpCode: 92 26
loads the value 22H into external data memory location 404AH
Note: This instruction format is valid only for MCUs which can address external data memory.
12-42
LDEI LOAD EXTERNAL DATA AUTO-INCREMENT
LDEI Load External Data Auto-increment
LDEI dst, src
Instruction Format:
OPC Address Mode
Cycles (Hex)
src dst
OPC lldstlsrcl OPC llsrcldstl
18 83 18 93
Ir
Irr
Irr
Ir
D' MICROCONTROLLERS
Operation: Flags: Example:
dst<-src r<-r + 1 rr<-rr+ 1
This instruction is used for block transfers of data between external data memory and the Register File. The address of the external data memory location is specified by a Working Register Pair, and the address of the Register File location is specified by a Working Register. The contents of the source location are loaded into the destination location. Both addresses in the Working Registers are then incremented automatically. The contents of the source are not affected.
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
If Working Register Pair R6 and R7 contains 404AH, external data memory location 404AH and 404BH contain ABH and C3H respectively, and Working Register R2 contains 22H, the statement:
LDEI OR2, ORR& OpCode: 83 26
loads the value ABH into Register 22H. Working Register Pair RR6 is incremented to 404BH and Working Register R2 is incremented to 23H. A second
LOCI OR2, ORR& OpCode: 83 26
loads the value C3H into Register 23H. Working Register Pair RR6 is incremented to 404CH and Working Register R2 is incremented to 24H.
12-43
'1J' MICROCONTROU!RS
LDEI LOAD EXTERNAL DATA AUTO-INCREMENT
Example:
If Working Register R2 contains 22H, Register 22H contains ABH, Register 23H contains C3H, and Working Register Pair R6 and R7 contains 404AH, the statement:
LDEI ORR&, OR2 OpCode: 93 26
loads the value ABH into external data memory location 404AH. Working Register R2 is incremented to 23H and Working Register Pair RR6 is incremented to 404BH. A second
LOCI ORR&, OR2 OpCode: 93 26
loads the value C3H into external data memory location 404BH. Working Register R2 is incremented to 24H and Working Register Pair RR6 is incremented to 404CH.
Note: This instruction format is valid only for MCUs which can address external data memory.
12-44
NOP NO OPERATION
NOP No Operation NOP Instruction Format:
OPC
OPC Cycles (Hex)
6 FF
'llJ' MICRocoNTRoLLERS
Operation: Flags:
No action is performed by this instruction. It is typically used for timing delays or clearing the pipeline.
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
12-45
OR LoglcalOR
ORdst,src
Instruction Format:
OPC llclstlslCI
11 OPC
SIC
OPC 11 dst
11 dst 11 SIC
OPC Address Mode
Cycles (Hex)
dst SIC
6
42
r
6
43
Ir
10
44
R
R
10
45
R
IR
10
46
R
IM
10
47
IR
IM
OR LOGICAL OR
Operation: Flags: Note:
dst <- dst OR src
The source operand is logically ORed with the destination operand and the result is stored in the destination operand. The contents of the source operand are not affected. The OR operation results in a one bit being stored whenever either of the corresponding bits in the two operands is a one. Otherwise, a zero bit is stored.
C: Unaffected Z: Set if the result is zero; cleared otherwise S: Set if the result of bit 7 is set; cleared otherwise V: Always reset to 0 D: Unaffected H: Unaffected
Address modes R or IA can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is specified by adding 111 OB (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example: Example: 12-46
If Working Register R1 contains 34H (001110008) and Working Register R14 contains 4DH (10001101), the statement:
OR R1, R14 OpCode: 42 1E
leaves the value BDH (10111101 B) in Working Register R1. The SFlag is set, and the Zand V Flags are cleared.
If Working Register R4 contains F9H (111110018), Working Register R13 contains 7BH, and Register 78 contains 6AH (011010108), the statement:
ORR4, OR13 OpCode: 43 4D
leaves the value FBH ( 111110118) in Working Register R4. The S Flag is set, and the Z and V Flags are cleared.
OR LOGICAL OR
Example: Example: Example: Example:
If Register 3AH contains the value F5H (11110101 B) and Register 42H contains the value OAH (00001010), the statement:
OR3AH,42H OpCode: 44 42 3A
leaves the value FFH (111111118) in Register 3AH. The S Flag is set, and the Zand V Flags are cleared.
If Working Register R5 contains 70H (011100008), Register 45H contains 3AH, and Register 3AH contains 7FH (01111111 B). the statement:
OR RS, 045H OpCode: 45 45 ES
leaves the value 7FH (01111111 B) in Working Register RS. The Z, V, and S Flags are cleared.
If Register 7AH contains the value F3H (11110111 B), the statement:
OR7AH,#FOH OpCode: 46 7A FO
leaves the value F3H (111101118) in Register7AH. The S Flag is set, and the Zand VFlags are cleared.
If Working Register R3 contains the value 3EH and Register 3EH contains the value OCH (000011 DOB), the statement:
OR OR3,#05H OpCode: S7 E3 05
leaves the value OOH (00001101 B) in Register 3EH. The Z, V, and S Flags are cleared.
12-47
'lJ' MICROCONTROUERS
POP POP
POP Pop
POPdst
Instruction Format:
OPC Address Mode
Cycles (Hex)
dst
OPC 11 dst
10 50
R
10 51
IR
Operation: Flags: Note:
dst <-@SP SP <-SP+ 1
The contents of the location specified by the SP (Stack Pointer) are loaded into the destination operand. The SP is then incremented automatically.
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 11108 (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example: Example:
If the SP (Control Registers FEH and FFH) contains the value ?OH and Register 70H contains 44H, the statement:
POP34H OpCode: 50 34
loads the value 44H into Register 34H. After the POP operation, the SP contains 71 H. The contents of Register 70 are not affected.
If the SP (Control Registers FEH and FFH) contains the value 1OOOH, external data memory location 1000H contains 55H, and Working Register R6 contains 22H, the statement:
POPOR6 OpCode: 51 E6
loads the value 55H into Register 22H. After the POP.operation, the SP contains 1001 H. The contents of Working Register R6 are not affected.
12-48
't'211..C16
PUSH PUSH
PUSH Push
PUSH src
Instruction Format:
Cydes
OPC Address Mode
(Hex)
dst
Operation: Flags: Note:
11 OPC
src
SP<- SP-1 @SP <-src
10 lntemal Stack
70
R
12 Elclernal Stack
12 lntemal Stack 71
IR
14 External Stack
The contents of the SP (stack pointer) are decremented by one, then the contents of the source operand are loaded into the location addressed by the decremented SP, thus adding a new element to the stack.
C: Unaffected Z: Unaffected S: Unaffected
V: Unaffected D: Unaffected
H:
Unaffected
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 111 OB (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example: Example:
If the SP contains 1001 H, the statement:
PUSHFCH OpCode: 70 FC
stores the contents of Register FCH (the Flag Register) in location 1000H. After the PUSH operation, the SP contains 1000H.
If the SP contains 61H and Working Register R4 contains FCH, the statement:
PUSH OR4 OpCode: 71 E4
stores the contents of Register FCH (the Flag Register) in location 60H. After the PUSH operation, the SP contains 60H.
12-49
RCF Reset Carry Flag RCF Instruction Format:
OPC
OPC Cycles (Hex)
6 CF
Operation: Flags:
Example:
C<-0
The C Flag is reset to 0, regardless of its previous value.
C: Reset to O Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
If the C Flag is currently set, the statement:
RCF Opcode: CF
resets the Carry Flag to 0.
Z8' MICROCON11IOLLERS
RCF RESET CARRY FLAG
12-50
RET RETURN
ZS' Mlc:ROCONTROLLERS
RET Return RET Instruction Format:
OPC
OPC Cycles (Hex)
14 AF
Operation: Flags: Note: Example:
PC<- @SP SP <-SP+ 2
This instruction is normally used to return from a procedure entered by a CALL instruction. The contents of the location addressed by the SP are popped into the PC. The next statement executed is the one addressed by the new contents of the PC. The stack pointer is also incremented by two.
C: Unaffected
Z: Unaffected
S: Unaffected V: Unaffected D: Unaffected H: Unaffected
Each PUSH instruction executed within the subroutine should be countered with a POP
instruction in order to guarantee the SP is at the correct location when the RET instruction
is executed. Otherwise the wrong address will be loaded into the PC and the program will not operate as desired.
If SP contains 2000H, external data memory location 2000H contains 18H, and location 2001 H contains B5H, the statement:
RET OpCode: AF
leaves the value 2002H in the SP, and the PC contains 1885H, the address of the next instruction to be executed.
II
12-51
RL Rotate Left
RLdst
Instruction Format:
11 OPC
dst
OPC Address Mode
Cycles (Hex)
dst
6
90
R
6
91
IA
'l!' MICROCONTROLLERS
RL ROTATE LEFT
Operation:
C<-dst(7) dst(O) <-dst(7) dst(1) <-dst(O) dst(2) <-dst(1) dst(3) <-dst(2) dst(4) <-dst(3) dst{5) <-dst(4) dst(6) <-dst(5) dst(7) <- dst(6)
The contents of the destination operand are rotated left by one bit position. The initial value
of bit 7 is moved to the bit Oposition and also into the Carry Flag.
Flags: Note:
C: Set if the bit rotated from the most significant bit position was 1 ( i.e., bit 7 was 1). Z: Set if the result is zero; cleared otherwise. S: Set if the result in bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred (if the sign of the destination operand changed
during rotation); cleared otherwise. D: Unaffected H: Unaffected
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 11108 (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
12-52
4'21Ul6
RL ROTATE LEFT
'lJ' MICROCONTROWRS
Example: Example:
If the contents of Register C6H are SSH (100010008), the statement:
RLC6H OpCode: 80 C6
leaves the value 11 H (00010001 B) in Register CSH. The C and V Flags are set, and the S and Z Flags are cleared.
If the contents of Register C6H are SSH, and the contents of Register SSH are 44H (010001008), the statement:
RL@C6H OpCode: 81 C6
leaves the value SSH in Register SSH (100010008). The Sand V Flags are set, and the C and Z Flags are cleared.
[I
12-53
RLC Rotate Left Through Carry RLCdst Instruction Format:
OPC 11 dst
'lJ' MICROCONTROLLERS
RLC ROTATE LEFT THROUGH CARRY
OPC Address Mode
Cycles (Hex)
dst
6
10
R
6
11
IR
Operation:
C<-dst(7) dst(O)<-C dst(1) <-dst(O) dst(2) <-dst(1) dst(3) <- dst(2) dst(4) <-dst(3) dst(5) <-dst(4) dst(6) <- dst(5) dst(7) <-dst(6)
The contents of the destination operand along with the C Flag are rotated left by one bit position. The initial value of bit 7 replaces the C Flag and the initial value of the C Flag replaces bitO.
Flags: Note:
C: Set if the bit rotated from the most significant bit position was 1 ( i.e., bit 7 was 1). Z: Set if the result is zero; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred (if the sign of the destination operand changed
during rotation); cleared otherwise. D: Unaffected H: Unaffected
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 11108 (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
12-54
RLC ROTATE LEFT THROUGH CARRY
'16' MlCRocoNTRoLl.ERS
Example: Example:
If the C Flag is reset and Register C6 contains BF (10001111 B), the statement:
RLCC& OpCode: 10 C&
leaves Register C6 with the value 1EH (0001111 OB). The C and V Flags are set, and S and Z Flags are cleared.
If the C Flag is reset. Working Register R4 contains C6H, and Register C6 contains BF (100011118), the statement:
RLC OR4 OpCode: 11 E4
leaves Register C6 with the value 1EH (000111108). The C and V Flags are set, and S and Z Flags are cleared.
12-55
RR Rotate Right
RRdst
Instruction Format:
11 OPC
dst
OPC Address Mode
Cycles (Hex)
d&t
6 EO
R
6
E1
IR
RR ROTATE RIGHT
Operation:
C <-dst(O) dst(O) <- dst(1) dst(1) <-dst(2) dst(2) <- dst(3) dst(3) <-dst(4) dst(4) <-dst(5) dst(5) <- dst(6) dst(6) <- dst(7) dst(7) <- dst(O)
The contents of the destination operand are rotated to the right by one bit position. The initial value of bit 0 is moved to bit 7 and also into the C Flag.
LI P-0 011oeloslD4losI02101 Ioo
Flags: Note:
C: Set if the bit rotated from the least significant bit position was 1 ( i.e., bit 0 was 1). Z: Set if the result is zero; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred (if the sign of the destination operand changed
during rotation); cleared otherwise. D: Unaffected H: Unaffected
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 111 OB (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then
ECH will be used as the destination operand in the OpCode.
12-56
RR ROTATE RIGHT
D' MICROCONTROLLERS
Example: Example:
If the contents of Working Register R6 are 31 H (00110001 B), the statement:
RRR6 OpCode: EO E6
leaves the value 98H (10011000) in Working Register R6. The C, V, and S Flags are set, and the Z Flag is cleared.
If the contents of Register C6 are 31H and the contents of Register 31H are ?EH (0111111 OB), the statement:
RROC6 OpCode: E1 C6
leaves the value 4FH (00111111) in Register 31H. The C, Z, V, and S Flags are cleared.
12-57
RRC Rotate Right Through Can'Y
RRCdst
Instruction Format:
II OPC
dst
RRC ROTATE RIGHT THROUGH CARRY
OPC Address Mode
Cycles (Hex)
dst
6 co
R
6
C1
IR
Operation:
C<-dst(O) dst(O) <- dst(1) dst(1) <-dst(2) dst(2) <- dst(3) dst(3) <-dst(4) dst(4) <-dst(5) dst(5) <- dst(S) dst(S) <- dst(7) dst(7)<-C
The contents of the destination operand with the C Flag are rotated right by one bit position. The initial value of bit 0 replaces the C Flag and the initial value of the C Flag replaces bit 7.
L::jo1loelo5lo4loslo2lo1loo~
Flags: Note:
C: Set if the bit rotated from the least significant bit position was 1 ( i.e., bit 0 was 1). Z: Set if the result is zero; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred (if the sign of the destination operand changed
during rotation); cleared otherwise. D: Unaffected H: Unaffected
Address modes A or IA can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 11108 (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
12-58
ARC ROTATE RIGHT THROUGH CARRY
'lH' MICROCONTROLLERS
Example: Example:
If the contents of Register C6H are DOH (11011101 B) and the C Flag is reset, the statement:
RRCC6H OpCode: CO C6
leavesthevalue6EH(01101110B) in registerC6H. TheC andVFlagsare set, and the Zand S Flags are cleared.
If the contents of Register 2C are EDH, the contents of Register EDH is OOH (000000008), and the C Flag is reset, the statement:
RRC 02CH OpCode: C1 2C
leaves the value 01H (000000018) in Register EDH. The C, Z, S, and V Flags are reset.
El
12-59
SBC Subtract With Carry
SBCdst,src
Instruction Format:
I OPC ldstlsrcl
II OPC
11 src
dst
OPC 11 dst 11 src
'lJ'I MICllOCONTROLLERS
SBC SUBTRACT WITH CARRY
OPC Address Mode
Cycles (Hex) dst
src
6
32
6
33
10 34
10
35
10
36
10
37
r Ir
R
R
R IR
R IM IR IM
Operation: Flags: Note:
dst<-dst-src-C
The source operand, along with the setting of the C Flag, is subtracted from the destination operand and the result is stored in the destination operand. The contents of the source operand are not affected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry (borrow) from the subtraction of low order operands to be subtracted from the subtraction of high order operands.
C: Cleared if there is a carry from the most significant bit of the result; set otherwise, indicating a "borrow."
Z: Set if the result is O; cleared otherwise. V: Set if arithmetic overflow occurred (if the operands were of opposite sign and the sign
of the result is the same as the sign of the source); reset otherwise. S: Set if the result is negative; cleared otherwise. H: Cleared if there is a carry from the most significant bit of the low order four bits of the
result; set otherwise indicating a "borrow.· D: Always set to 1.
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is specified by adding 111 OB (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example:
If Working Register R3 contains 16H, the C Flag is set to 1, and Working Register R11 contains 20H, the statement:
SBC R3, R11 OpCode: 32 3B
leaves the value F5H in Working Register R3. The C, S, and D Flags are set, and the Z, V, and H Flags are all cleared.
12-60
SBC SUBTRACT WITH CARRY
Example: Example: Example: Example: Example:
If Working Register R15 contains 16H, the C Flag is not set, Working Register R10 contains 20H, and Register 20H contains 11 H, the statement:
SBC R16, OR10 OpCoda: 33 FA
leaves the value 05H in Working Register R15. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
If Register 34H contains 2EH, the C Flag is set, and Register 12H contains 18H, the statement:
SBC34H, 12H OpCoda: 34 12 34
leaves the value 13H in Register 34H. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
If Register 4BH contains 82H, the C Flag is set, Working Register R3 contains 10H, and Register 1OH contains 01 H, the statement:
SBC4BH, ORS OpCoda: 35 E3 4B
leaves the value BOH in Register 4BH. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
If Register 6CH contains 2AH, and the C Flag is not set, the statement:
SBC &CH, #03H OpCode: 36 &C 03
leaves the value 27H in Register 6CH. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
If Register D4H contains 5FH, Register 5FH contains 4CH, and the C Flag is set, the statement:
SBC OD4H, #02H OpCoda: 37 D4 02
leaves the value 4AH in Register 5FH. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
II
12-61
SCF
Set Carry Flag
SRC
Instruction Format:
OPC
OPC Cycles (Hex)
6 OF
Operation: Flags;
C <- 1
The C Flag is set to 1, regardless of its previous value.
C: Set to 1 Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
If the C Flag is currently reset, the statement:
SCF
OpCode: DF
sets the Carry Flag to 1.
SCF SET CARRY FLAG
12-62
SRA SHIFT RIGHT ARITHMETIC
SRA Shift Right Arithmetic SRAdst Instruction Format:
OPC Address Mode
Cycles (Hex)
dst
7J8 MICROCONIROUERS
II
11 OPC
dst
6
DO
R
6
01
IR
Operation:
C<-dst(O) dst(O) <-dst(1) dst(1) <-dst(2) dst(2) <-dst(3) dst(3) <-dst(4) dst(4) <-dst(5) dst(5) <-dst(6) dst(6) <- dst(7) dst(7) <-dst(7)
An arithmetic shift right by one bit position is performed on the destination operand. Bit 0 replaces the C Flag. Bit 7 (the Sign bit) is unchanged and its value is shifted into bit 6.
Flags: Note:
C: Set if the bit rotated from the least significant bit position was 1 ( i.e., bit 0 was 1). Z: Set if the result is zero; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always reset to 0. D: Unaffected H: Unaffected
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, destination Working Register operand is specified by adding 111OB (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
12-63
't'Zil.CE
'II' MICROCONTROLLERS
SRA SHIFT RIGHT ARITHMETIC
Example:
If the contents of Working Register R6 are 31 H (00110001 B), the statement:
SRAR6 OpCode: DO E6
leaves the value 98H (00011000) in Working Register R6. The C Flag is set, and the Z, V, and S Flags are cleared.
Example:
lfRegisterC6 contains the value DFH, and Register DFH contains the value 68H (101110006), the statement:
SRA OC6 OpCode: 01 C6
leaves the value OCH (110111006) in Register DFH. The C, Z, and V Flags are reset, and the S Flag is set.
12-64
'tl211..D6
SRP SET REGISTER POINTER
SRP Set Register Pointer
SRPsrc
Instruction Format:
OPC Address Mode
Cycles (Hex)
dst
m- MICROCONTROLLERS
II
OPC 11 src
6
31
IM
Operation:
RP <-src
The specified value is loaded into the Register Pointer (RP) (Control Register FDH). Bits 7-4 determine the Working Register Group within the ZS Standard Register File. These Working Registers are selected when bits 3-0 are set to OOOOB. When bits 3-0 are defined, the Expanded Working Register Bank is specified. The contents of bits 7-4 are disregarded when bits 3-0 are defined other than OOOOB.
Register Pointer (FDH)
Contents (Bin) 11110000 11100000 1101 0000 11000000 1011 0000 10100000 1001 0000 1000 0000 0111 0000 01100000 0101 0000 01000000 0011 0000 0010 0000 0001 0000 00000000
Working Register Group
(Hex) F E D
c
B A 9 8 7 6 5 4 3
2
0
Actual Registers
(Hex) FO-FF EO-EF DO-OF CO-CF BO-BF AO-AF 90-9F 80-BF 70-7F 60-6F 50-5F 40-4F 30-3F 20-2F 10-1F 00-0F
12-65
Register Pointer (FDH)
Contents (Hex) xxxx 1111 xxxx 1110 xxxx 1101 xxxx 1100 xxxx 1011 xxxx 1010 xxxx 1001 xxxx 1000 xxxx 0111 xxxx0110 xxxx 0101 xxxx 0100 xxxx0011 xxxx 0010 xxxx0001
Working Register Group
(Hex)
F E D
c
B A 9 8 7 6 5 4 3 2
D' MICRocoN!ROLLERS
SRP SET REGISTER POINTER
Working Registers
(Dec) RO-R15 RO-R15 RO-R15 RO-R15 RO-R15 RO-R15 RO-R15 RO-R15 RO-R15 RO-R15 RO-R15 RO-R15 RO-R15 RO-R15 RO-R15
Example:
C: Unaffected
Z: Unaffected S: Unaffected
V: Unaffected D: Unaffected
H: Unaffected
When an Expanded Register Bank is defined as the current Working Register, access to the ZS Standard Register File is possible through direct addressing.
The statement:
SRPFOH OpCode: 70 FO
sets the Register Pointer to access Working Register Group F in the ZS Standard Register File. All references to Working Registers now affect this group of 16 registers. Registers FOH to FFH can be accessed as Working Registers RO to R15
12-66
SRP SET REGISTER POINTER
U' MICROCONTROLISIS
Example: Example:
The statement:
SRPOFH OpCode: 70 OF
sets the Register Pointer to access Expanded Register Bank F as the current Working Registers. All references to Working Registers now affect this group of 16 registers. These registers are now accessed as Working Registers RO to R15.
Assume the RP currently addresses the Control and Peripheral Working Register Group and the program has just entered an interrupt service routine. The statement:
SRP70H OpCode: 31 70
retains the contents of the Control and Peripheral Registers by setting the RP to 70H (011100008). Any reference to Working Registers in the interrupt routine will point to registers 70H to 7FH.
II
12-67
STOP Stop STOP Instruction Format:
OPC
OPC
Cycles (Hex)
6 6F
STOP STOP
Operation: Flags:
Note: Example:
This instruction turns off the internal system clock (SCLK) and external crystal ()ITAL) oscillation, and reduces the standby current. The STOP mode is terminated by a RESET which causes the processor to restart the application program at address OOOCH.
C: Unaffected Z: Unaffected S: Unaffected V: Unaffected D: Unaffected H: Unaffected
In order to enter STOP mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. The user must execute a NOP immediately before the execution of the STOP instruction.
The statements:
NOP STOP Opcodes: FF 6F
place the ZS into STOP mode.
12-68
SUB SUBTRACT
SUB Subtract
SUB dst,src
Instruction Format:
I OPC
ldstlsrcl
Operation:
OPC 11 src
OPC 11 dst
dst <-dst- src
11 dst 11 src
OPC Address Mode
Cycles (Hex) dst
src
6
22
6
23
10 24 10 25
10 26 10 27
r Ir
R
R
R
IR
R
IM
IR
IM
The source operand is subtracted from the destination operand and the result is stored in the destination operand. The contents of the source operand are not affected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.
Flags:
C: Cleared if there is a carry from the most significant bit of the result; set otherwise, indicating a "borrow.'
Z: Set if the result is O; cleared otherwise. V: Set if arithmetic overflow occurred (if the operands were of opposite sign and the sign
of the result is the same as the sign of the source); reset otherwise. S: Set if the result is negative; cleared otherwise. H: Cleared if there is a carry from the most significant bit of the low order four bits of the
result; set otherwise indicating a "borrow.' D: Always set to 1.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is specified by adding 111 OB (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example:
If Working Register R3 contains 16H, and Working Register R11 contains 20H, the statement:
SUB R3, R11 OpCode: 22 3B
leaves the value F6H in Working Register R3. The C, S, and D Flags are set, and the Z, V, and H Flags are cleared.
II
12-69
Example: Example: Example: Example: Example:
'lJI MICROCONTROWRS
SUB SUBTRACT
If Working Register R15 contains 16H, Working Register R10 contains 20H, and Register 20H contains 11 H, the statement:
SUB R16, @R10 OpCode: 23 FA
leaves the value 05H in Working Register R15. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
If Register 34H contains 2EH. and Register 12H contains 1BH, the statement:
SUB34H, 12H OpCode: 24 12 34
leaves the value 13H in Register 34H. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
If Register 4BH contains 82H, Working Register R3 contains 1OH, and Register 1OH contains 01 H, the statement:
SUB4BH,@R3 OpCode: 25 E3 4B
leaves the value 81 H in Register 4BH. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
If Register 6CH contains 2AH, the statement:
SUB 6CH, #03H OpCode: 26 6C 03
leaves the value 27H in Register 6CH. The D Flag is set, and the C, Z. S, V, and H Flags are cleared.
If Register D4H contains 5FH. Register 5FH contains 4CH, the statement:
SUB OD4H, #02H OpCode: 17 D4 02
leaves the value 4AH in Register 5FH. The D Flag is set, and the C, Z. S, V, and H Flags are cleared.
12-70
SWAP SWAP NIBBLES
SWAP Swap Nibbles
SWAPdst
Instruction Format:
OPC Address Mode
Cycles (Hex)
dst
11 OPC
dst
6
FO
R
6
F1
IR
Operation: Flags:
Note:
dst(7-4) <-> dst(3-0)
The contents of the lower four bits and upper four bits of the destination operand are swapped.
C: Unaffected Z: Set if the result is zero; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Undefined D: Unaffected H: Unaffected
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, destination Working Register operand is specified by adding 11106 (EH) to the high nibble
of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example: Example:
If Register 6CH contains 63H (101100116), the statement:
SWAPB3H OpCode: FO B3
will leave the value 38H (001110116) in Register 6CH. The Zand S Flags are cleared.
If Working Register R5 contains 6CH and Register BCH contains 63H (101100116), the statement:
SWAP@R5H OpCode: F1 E5
will leave the value 38H (001110116) in Register 6CH. The Zand S Flags are cleared.
II
12-71
TCM Test Complement Under Mask
TCM dst, src
Instruction Format:
I OPC
lds1lsrcl
OPC 11 src OPC 11 dst
11 dst 11 src
'lJ' MICROCONTROLLERS
TCM TEST COMPLEMENT UNDER MASK
OPC Address Mode
Cycles (Hex)
dst
src
6
62
6
63
10
64
10 65
10 66 10 67
r Ir
R
R
R
IR
R
IM
IR
IM
Operation: Flags:
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logical 1 value. The bits to be tested are specified by setting a 1 bit in the corresponding bit position in the source operand (the mask). The TCM instruction complements the destination operand, and then ANDs itwith the source mask(operand). The Zero (Z) Flag can then be checked to determine the result. If the Z Flag is set, then the tested bits were 1. When the TCM operation is complete, the destination and source operands still contain their original values.
C: Unaffected Z: Set if the result is zero; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always reset to 0. D: Unaffected H: Unaffected
Note:
Address modes R or IA can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is specified by adding 111OB (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example:
If Working Register R3 contains 45H (01000101 B) and Working Register R7 contains the value 01 H (00000001 B) (bit 0 is being tested if it is 1), the statement:
TCMR3,R7 OpCode: 62 37
will set the Z Flag indicating bit 0 in the destination operand is 1. The V and S Flags are cleared.
12-72
TCM TEST COMPLEMENT UNDER MASK
ZS" MICROCONTROlLERS
Example: Example: Example:
If Working Register R14 contains the value F3H (111100118), Working Register RS contains C8H, and Register C8H contains 88H (100010008) (bit 7 and bit 4 are being tested if they are 1), the statement:
TCM R14,@R5 OpCode: 63 ES
will reset the Z Flag, because bit 4 in the destination operand is not a 1. The V and S Flags are also cleared.
If Register D4H contains the value 04H (0000010008), and Working Register RO contains the value BOH (100000008) (bit 7 is being tested if it is 1), the statement:
TCM D4H, RO OpCode: 64 EO 04
will reset the Z Flag, because bit 7 in the destination operand is not a 1. The S Flag will be set, and the V Flag will be cleared.
If Register DFH contains the value FFH (111111118), Register 07H contains the value 1FH, and Register 1FH contains the value 8DH (101111018) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are being tested if they are 1), the statement:
TCM DFH, @07H OpCode: 65 07 DF
will setthe Z Flag indicating the tested bits in the destination operand are 1. The Sand VFlags are cleared.
II
Example: Example:
If Working Register R13 contains the value F1H (111100018), the statement:
TCM R13, #02H OpCode: 66 ED, 02
tests bit 1 of the destination operand for 1. The Z Flag will be set indicating bit 1 in the destination operand was 1. The S and V Flags are cleared.
If Register SDH contains AOH, and Register AOH contains OFH (000011118), the statement:
TCM 5D,#10H OpCode: 67 SD 10
tests bit 4 of the Register AOH for 1. The Z Flag will be reset indicating bit 1 in the destination operand was not 1. The S and V Flags are cleared.
12-73
TM Test Under Mask
D' MICROCONTROLLERS
TM TEST UNDER MASK
TMdst,src
Instruction Format:
I OPC ldstlslCI
II II OPC
SIC
dst
II OPC
dst 11 SIC
dst OPC Address Mode
Cycles (Hex)
SIC
6 72 6 73
10 74 10 75
10 76 10 77
r Ir
R
R
R
IR
R
IM
IR
IM
Operation: dstANDsrc
This instruction tests selected bits in the destination operand for logical a Ovalue. The bits to be tested are specified by setting a 1 bit in the corresponding bit position in the source operand (the mask). The TCM instruction ANDs the destination operand with the source operand (the mask). The Zero (Z) Flag can then be checked to determine the result. If the Z Flag is set, then the tested bits were 0. When the TCM operation is complete, the destination and source operands still contain their original values.
Flags:
C: Unaffected Z: Set if the result is zero; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always reset to 0. D: Unaffected H: Unaffected
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is specified by adding 111 OB (EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example:
If Working Register R3 contains 45H (01000101 B) and Working Register R7 contains the value 01 H (0000001 OB) (bit 1 is being tested if it is 0), the statement:
TMR3,R7 OpCode: 72 37
will set the Z Flag indicating bit 1 in the destination operand is 0. The V and S Flags are cleared.
12-74
TM TEST UNDER MASK
'1' MICROCONlllOLLERS
Example: Example: Example: Example: Example:
If Working Register R14 contains the value F3H ( 11110011 B), Working Register A5 contains CBH, and Register CBH contains 88H (10001 OOOB) (bit 7 and bit 4 are being tested if they are 0), the statement:
TM R14,@R5 OpCode: 73 ES
will reset the Z Flag, because bit 4 in the destination operand is not a 0. The S Flag will be set, and the V Flag is cleared.
If Register D4H contains the value 08H (00001 OOOB), and Working Register AO contains the value 04H (00001000B) (bit 3 is being tested if it is 0), the statement:
TM D4H,RO OpCode: 74 EO D4
will set the Z Flag, because bit 3 in the destination operand is a 0. The Sand V Flags will be cleared.
If Register DFH contains the value OOH (OOOOOOOOB), Register 07H contains the value 1FH, and Register 1FH contains the value BDH (10111101 B) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit Oare being tested if they are 0), the statement:
TM DFH,@07H OpCode: 75 07 DF
will set the Z Flag indicating the tested bits in the destination operand are 0. The S is set, and the V Flag is cleared.
If Working Register R13 contains the value F1H (111100016), the statement:
TM R13,#02H OpCode: 76 ED, 02
tests bit 1 of the destination operand for O. The Z Flag will be set indicating bit 1 in the destination operand was 0. The S and V Flags are cleared.
If Register 5DH contains AOH, and Register AOH contains OFH (00001111 B), the statement:
TM 5D,#10H OpCode: 77 SD 10
tests bit 4 of the Register AOH for O. The Z Flag will be set indicating bit 1 in the destination operand was 0. The S and V Flags are cleared.
12-75
1J' MICROCONTROLLBIS
WDH WATCH-DOG TIMER ENABLE DURING HALT MODE
WDH Watch-Dog Timer Enable During HALT Mode
WDH Instruction Format:
OPC
Cycles (Hex)
OPC
6 4F
Operation:
When this instruction is executed it will enable the WDT (Watch-Dog Timer) during HALT mode. If this instruction is not executed the WDT will stop when entering HALT mode. This instruction does not clear the counter, it just makes it possible to have the WDT function running during HALT mode. A WDH instruction executed without executing WDT (5FH) has no effect.
C: Unaffected Z: Undefined S: Undefined V: Undefined D: Unaffected H: Unaffected
Note:
The WDH instruction should not be used following any instruction in which the condition of the flags is important.
Example:
If the WDT is enabled, the statement:
WDH OpCode: 4F
will enable the WDT in HALT mode.
Nal9;ThisinstructionfcrmatisvafldonlyfortheZBOC04,C07,Ql3andZB6E04iBJ7/EOO.
12-76
WOT
WATCH-DOG TIMER
WOT Watch-Dog Timer WOT Instruction Format:
OPC
OPC Cycles (Hex)
6 SF
zr MICROCONTROLLERS
Operation: Flags:
Note: Example: Example:
The WOT (Watch-Dog Timer) is a retriggerable one shot timer that will reset the Z8 if it reaches its terminal count. The WOT is initially enabled by executing the WOT instruction. Each subsequent execution of the WOT instruction refreshes the timer and prevents the WOT from timing out.
C: Unaffected Z: Undefined S: Undefined V: Undefined D: Unaffected H: Unaffected
The WOT instruction should not be used following any instruction in which the condition of the flags is important.
If the WOT is enabled, the statement:
WOT Opcode: SF
refreshes the Watch-Dog Timer.
The first execution of the statement:
WOT OpCode: SF
enables the Watch-Dog Timer.
12-77
XOR Logical Exclusive OR
XOR dst,src
Instruction Format:
OPC lldstlsrcl
I I OPC 11 src
dst
II II OPC
dst
src
ZS" MICROCONTROLLERS
XOR LOGICAL EXCLUSIVE OR
OPC Address Mode
Cycles {Hex)
dst
src
6
B2
6
B3
10 B4 10 B5
10 BS 10 B7
r Ir
R
R
R
IR
R
IM
IA
IM
Operation: Flags: Note:
dst <- dst XOR src
The source operand is logically EXCLUSIVE ORed with the destination operand. The XOR operation results in a 1 being stored in the destination operand whenever the corresponding bits in the two operands are different, otherwise a 0 is stored. The contents of the source operand are not affected.
C: Unaffected Z: Set if the result is zero; cleared otherwise. S: Set if the result of bit 7 is set; cleared otherwise. V: Always reset to 0 D: Unaffected H: Unaffected
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination Working Register operand is specified by adding 1110B(EH) to the high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the OpCode.
Example:
If Working Register R1 contains 34H (001110008) and Working Register R14 contains 4DH (10001101B), the statement:
XOR R1, R14 OpCode: 82 1E
leaves the value BDH (101111018) in Working Register R1. The Z, and V Flags are cleared, and the S Flag is set.
12-78
XOR LOGICAL EXCLUSIVE OR
Example: Example: Example: Example: Example:
If Working Register R4 contains F9H (111110018), Working Register R13 contains 78H, and Register 78 contains 6AH (0110101 OB), the statement:
XORR4, OR13 OpCode: B3 40
leaves the value 93H (100100118) in Working RegisterR4. The S Flag is set, and theZ, and V Flags are cleared.
If Register 3AH contains the value FSH (111101018) and Register 42H contains the value OAH (000010108), the statement:
XOR3AH,42H OpCode: 84 42 3A
leaves the value FFH (111111118) in Register 3AH. The S Flag is set, and the C and V Flags are cleared.
If Working Register RS contains FOH (111100008), Register 45H contains3AH. and Register 3A contains 7F (011111118), the statement:
XORR5, 045H OpCode: BS 45 ES
leaves the value BFH (100011118) in Working Register RS. The S Flag is set, and the C and V Flags are cleared.
If Register 7AH contains the value F7H (111101118), the statement:
XOR 7AH, #FOH OpCode: 86 7A FO
leaves the value 07H (000001118) in Register ?AH. The Z, V and S Flags are cleared.
If Working Register R3 contains the value 3EH and Register 3EH contains the value 6CH (011011008), the statement:
XOR OR3, #OSH OpCode: 87 E3 05
leaves the value 69H (011010018) in Register 3EH. The Z, V, and S Flags are cleared.
El
12-79
4'2.HJ a,
USER'S MANUAL
ZS' MICROCOHTROWRS
CHAPTER 13
ZILOG EMULATORS/SOFTWARE
13.1 ZILOG Z8 EMULATOR PRODUCTS
Zilog provides a family of full-featured real-time in-circuit emulators to support Z88 product development. In-circuit emulation links your design to a PC to determine how the microcontroller is functioning in your design. This greatly simplifies system debug, reducing development time and OTP device consumption. All emulators include OTP programming, a user configurable WINDOWS interface, a
Zilog za· cross assembler and complete za· documenta-
tion. Product specifications for the following in-circuit emulator kits are also provided:
· Z86CCPOOZEM I Z86CCPOOZAC
· Z86C1200ZEM
· Z86C5000ZEM
13-1
13.2 ZS9CCPTM EMULATOR
7J' MICROCONTROUERS
QUICK START
(D Check Support Package Contents (See Other Side1
@ Load Software 1. Select the "Run' command from the 'File' menu, located under Microsoft Windows "Program Manager". a. Insert the disk labeled "Zilog ZASM Cross Assembler/Zilog M08J Object File Util." in drive A (or drive 8, if appropriate.) b. Type 'a:\setup" and press ENTER. (Type 'b:\setup' if drive B is used.) c. Follow on-screen instructions. d. Remove diskette and store in a safe place when done.
ml For more information on assembling source code, refer to ZS CCP Emulator
. , User's Gulde (Appendix C) and the Zee Mlcrocontrollers Technical Manual.
2. Select the "Run" command from the 'File" menu, located under Microsoft Windows "Program Manager". a. Insert disk labeled "ZS GUI S/W" in drive A (or drive 8, if appropriate.) b. Type "a:\setup" and press ENTER. (Type "b:\setup" if drive 8 is used.) c. Follow on-screen instructions. d. Remove diskette and store in a safe place when done.
@ Make Connections Power Supply, PC, and Your Design
ml Refer to zee CCP'"'
. , Emulator User's Manual
ml Observe Electrlcal Safeguards
. , (See ZB CCP Emulator User's Manual)
Connect to Power Supply
@ Run Zilog ICEBOX GUI Software 1. Double click the ZS-ICE icon. 2. Select the microcontroller and ROM size to be emulated in the Configuration Dialog Box. 3. Use the 'File' menu to download sample files to ZS Code Memory. 4. Refer to ZS CCP Emulator User's Manual,
"Chapter 3: ZS Emulator Sample Session'.
COM1-4 10o-Parcent Compatible PC
13-2
'tl2H.m
13.3 za·CCPTM EMULATOR
PACKAGE CONTENTS
SUPPORT PRODUCTS PACKAGE CONTENTS
The Zilog ZS® CCP"' Emulator Support Products Package contains the following items:
Hardware
ZS® CCP"' Emulator Board 1S-Pin DIP-to-DIP Target Cable ZS6EOS 1S-Pin DIP OTP Device
Software
ZS® GUI S/W Diskette Zilog ZASM Cross Assembler/MOBJ Object File Util. Diskette Production Languages Corporation (PLC) Compass/ZSTM Diskette (Evaluation Version)
Description of za· GUI Diskette Include Files
zScfg.o zSice.exe icehelp.hlp meter.di I read me setup.inf setup.axe zSem_c12.o zSem_c27.o zSem_c50.o zSem_c62.o zSem_c65.o zSem_c67.o zSem_c93.o zSem_l7x.o zSem_ccp.o
Configuration Executable Help Installation library Text file Installation information Windows install program On board software for ZS6C12 Icebox On board software for ZS6C27 Icebox On board software for ZS6C50 Emulator On board software for ZS6C62 Emulator On board software for ZS9C65 Emulator On board software for ZS9C67 Emulator On board software for ZS6C93 Emulator On board software for ZS6L7X Emulator On board software for ZS6CCP Emulator
Publications
Zilog ZS CCP Emulator User's Manual ZS Microcontrollers Technical Manual Discrete ZS Microcontrollers Databook Registration Card
Optional Accessory Kit
An optional accessory kit (PIN ZS6CCPOOZAC) available from Zilog contains the following items: 2S-Pin ZIF Socket 40-Pin ZIF Socket Power Cable 2S-Pin DIP-to-DIP Target Cable 40-Pin DIP-to-DIP Target Cable
ZS' MICROCONTROLLERS
II
13-3
13. 4 Z86CCPQOZEM EMULATOR
PRODUCT SPECIFICATION
DEVICES SUPPORTED: Z86C03, Z86C04/E04, Z86C06, Z86C08/E08, Z86C09/19, Z86E03/E06; WITH ZS® CCPTM EMULATOR ACC. KIT {Z86CCPZAC): Z86C30/E30, Z86C31/ E31,Z86C40/E40,Z86730,Z86C32
DESCRIPTION
KIT CONTENTS
The Z86CCPOOZEM is a member of Zilog's family of incircuit emulators. The ZS CCP emulator provides emulation and OTP programming support for Zilog's Consumer Controller Processor (CCP"') microcontroller. The Emulator provides all the essential MCU timing and 1/0 circuitry which simplifies user emulation of the prototype hardware/ software product.
The data entering, program debugging, and OTP programming are performed by the monitor ROM and the Host Package which communicates through RS-232C serial interface with a fixed 19200 baud rate. The user program can be downloaded directly from the host computer via an RS-232C connector. The user code may then be executed using various debugging commands in the monitor. The Emulator can be connected to a serial port (COM 1, COM 2, COM3, COM4) of the host computer (3S6 or 4S6, IBM compatible PC) and uses Graphical User Interface (GUI) software.
zse CCP"' Emulator
CMOS Z86C9320VSC RS-232C Interface Reset Switch 20 MHz CMOS ZS6C5020FSE ICE Chip SK x 8 STATIC RAM (for Code Memory) 1S-Pin DIP ZIF Programming Socket 1S-Pin Target Connector Cable Holes Available for 2S/40-Pin ZIF Sockets Sockets Available for 1S/2S/40-Pin Target Cables
Software (IBM PC Platform)
ZASM Cross-Assembler and MOBJ Object File Util. ZS9 GUI Emulator Software Production Languages Corporation COMPASS/ZS
(Evaluation Version)
System Requirements
SPECIFICATIONS
Emulatlon Specification
Maximum Emulation Speed: S MHz Minimum Emulation Speed: 1 MHz
Power Requirements
+SV Vdc @ 0.5 A
Dimensions
Width: 7.0 in. (17.7 cm) Length: 9.0 in. (22.9 cm) Height: 0.9 in. (2.3 cm)
Serlal Interface
3S6 or 486, IBM Compatible PC VGA Video Adapter (Color Monitor Recommended) 20 MHz, Minimum 4 Mbytes RAM Microsoft Windows 3.0 or 3.1 Hard Disk Drive (1 Mbyte Free Space) High Density (HD) Floppy Disk Drive (3.5-lnch) RS-232 COM Port
Documentation
Registration Card Product Information ZB9 CCP"' Emulator User's Manual Discrete ZS Databook ZS9 Microcontroller User's Manual
ORDERING INFORMATION
RS-232C @ 19200 baud
Part No: ZS6CCPOOZEM
13-4
13.5 Z86CCPOOZAC EMULATOR KIT
PRODUCT SPECIFICATION
'lJ' MICROCONTllOLWIS
DESCRIPTION
KIT CONTENTS
The Z86CCPOOZAC is the accessory kit for the Z86CCPOOZEM. The kit contains all accessories to fully populate and operate all functions of the Z86CCPOOZEM.
Z8 CCP Emulator Accessory Kit
28-Pin ZIF Socket 28-Pin Target Connector Cable 40-Pin ZIF Socket 40-Pin Target Connector Cable RS-232 Cable Power Cable
ORDERING INFORMATION
Part No: Z86CCPOOZAC
II
13-5
13.6 Z86C1200ZEM EMULATOR
PRODUCT SPECIFICATION
'ZS' MICROCONTROLLERS
DEVICES SUPPORTED: Z86117n17, Z86C04/E04, Z86C07/E07, Z86C08/E08, Z86C11,Z86C20,Z86C21/E21,Z86E22,Z86E23,Z88C80,Z86C61/E61, Z86C63/E63,Z86C65,Z86C91
DESCRIPTION
KIT CONTENTS
The Z86C1200ZEM ZS® Emulator is a member of Zilog's ICEBOX"' product family of in-circuit emulators. The Z86C1200ZEM provides emulation and OTP programming support for Zilog's ZS microcontrollers. The Emulator provides all the essential MCU timing and 1/0 circuitry which simplifies user emulation of the prototype hardware/ software product. The data entering, program debugging, and OTP programming are performed by the monitor ROM and the Host Package which communicates through a RS232C serial interface with a fixed 19200 baud rate. The user program can be downloaded directly from the host computer through the RS-232C connector. The user code may then be executed using various debugging commands in the monitor. The Emulator can be connected to a serial port (COM 1, COM 2, COM3, COM4) of the host computer (386 or 486, IBM compatible PC) and uses Graphical User Interface (GUI) software.
SPECIFICATIONS
Emulatlon Specification
Minimum Emulation Speed: 1 MHz Maximum Emulation Speed: 16 MHz
Power Requirements
+5 Vdc@0.5 A
Dimensions
Width: 6.25 in. (15.8 cm) Length: 9.5 in. (24.1 cm) Height: 2.5 in. (6.35 cm)
Serlal Interface
RS-232C @ 19200 baud
Z86C12 Emulator
ZS- Emulation Base Board
CMOS Z86C9120PSC BK X 8 EPROM (Programmed with Debug Monitor)
32K X 8 STATIC RAM 3 64K X 4 STATIC RAM RS-232C Interface Reset Switch Z86C12 Emulation Daughter Board 16 MHz CMOS Z86C1216GSE ICE Chip 18/40-Pin ZIF OTP Sockets 40/60/80-Pin Target Connectors
Cables/Pods
18-Pin DIP Emulation Cable 28-Pin DIP Emulation Cable 40-Pin DIP Emulation Cable Power Cable with Banana Plugs Power Cable with 1A Slow-Blow Fuse DB 25 RS-232C Cable
Software (IBP·PC Platform)
ZASM Cross-Assembler and MOBJ Object File Util. ZS® GUI Emulator Software
Documentation
Emulator User's Manual ZS® Cross-Assembler User's Guide Universal Object File Utilities (MOBJ) User's Guide Registration Card Product Information
ORDERING INFORMATION
Part No: Z86C1200ZEM
13-6
(tl2Jl.£16
.,, MICROCONTROUERS
13.7 Z86C5000ZEM EMULATOR
PRODUCT SPECIFICATION
DEVICES SUPPORTED: Z86C03, Z86C06, Z86C09/19, Z86C30/E30, Z86C31/E31, Z86C40/E40,Z86C89,Z86C90,Z86l06,Z86L29,Z86E03/E06,Z86C32,Z86730
DESCRIPTION
KIT CONTENTS
The Z86C5000ZEM (C50) Emulator is a member of Zilog's ICEBOXTM product family of in-circuit emulators. The CSO Emulator provides emulation and OTP programming support for Zilog's CCPN (Consumer Controller Processor) microcontrollers. The C50 Emulator provides all the es-
sential MCU timing and 1/0 circuitry which simplifies user
emulation of the prototype hardware/software product. The Emulator can be connected to a serial port (COM 1, COM 2, COM3, COM4) of the host computer {386 or 486, IBM compatible PC) and uses Graphical User Interface (GUI) software.
SPECIFICATIONS
Emulation Specification
Miinimum Emulation Speed: 1 MHz Maximum Emulation Speed: 20 MHz
Z86C50 Emulator
Z89 Emulation Base Board CMOS Z86C9120PSC SK x S EPROM (Programmed with Debug Mtr.) 32K x S Static RAM 3 64K x4 Static RAMs RS-232C Interface Reset Switch
Z86C50 Emulation Daughter Board 20 MHz CMOS Z86C5020GSE ICE Chip 2K x S Static RAM 1S/28/40-Pin ZIF OTP Sockets 6 HP-16500A Logic Analysis System Interface Connectors 40/60/80-Pin Target Connectors
Cables
Power Requirements
+5V Vdc@ 1.0 A
Dimensions
Width: 6.25 in. (15.8 cm) Length: 9.5 in. (24.1 cm) Height: 2.5 in. (6.35 cm)
Serlal Interface
RS-232C @19200 baud
System Requirements
386 or 486, IBM Compatible PC VGA Video Adapter (Color Monitor Recommended) 20 MHz, Minimum 4 Mbytes RAM Microsoft Windows 3.0 or 3.1 Hard Disk Drive (1 Mbyte Free Space) High Density (HD) Floppy Disk Drive (3.5-lnch) RS-232 COM Port
40-Pin DIP Emulation Cable 2S-Pin DIP Emulation Cable 18-Pin DIP Emulation Cable Power Cable with Banana Plugs DB25 RS-232C Cable
Software (IBM PC Platform)
ZASM Cross-Assembler and MOBJ Object File Util.
zge GUI Emulator Software
Documentation
ICEBOXN User's Manual ZS Cross-Assembler User's Guide Windows Host Interface User's Guide (GUI) Universal Object File Utilities (MOBJ) User's Guide Registration Card
ORDERING INFORMATION
Part No ZS6C5000ZEM
13-7
13.8 SOFTWARE
13.8.1 INTRODUCTION
This section describes some of the important features of
za·, the with software examples that illustrate its power
and ease of use. It is divided into sections by topic; the userneed not read each section sequentially, but may skip around to the sections of current interest.
For feature availability and implementation details on a particular ZB device, see the product specification.
13.9 ACCESSING REGISTER MEMORY
The ZB register space consists of 1/0 ports, control and status registers, and general-purpose registers. The general-purpose registers are RAM areas typically used for accumulators, pointers, and stack area. This section describes these registers and how they are used. Bit manipulation and stack operations effecting the register space are discussed in other sections of this manual.
13.9.1 Registers and Register Pairs
The ZB supports 8-bit registers and 16-bit register pairs. A register pair consists of a an even-numbered register concatenated with the next higher numbered register (00 and 01, 02 and 03, ... FFH). A register pair must be addressed by reference to the even-numbered register.
· F1 H and F2H are not a valid register pairs.
· FOH and F1H are valid register pairs, addressed by reference to FOH.
Register pairs may be incremented (INCW) and decremented (DECW) and are useful as pointers for accessing program and external data memory.
Any instruction which can reference or modify an 8-bit register can do so to any of the registers in the ZS, regardless of the inherent nature of that register. Thus, I/ O ports, control, status, and general-purpose registers may all be accessed and manipulated without the need for special-purpose instructions. Similarly, instructions which reference or modify a 16-bit register pair can do so to any of the valid register pairs.
The only exceptions to this rule are as follows:
· The DJNZ (decrement and jump if non-zero) instruction may successfully operate on the general-purpose working registers only.
· All write-only control registers may be modified only by such instructions as LOAD, POP, and CLEAR. Instructions such as OR and AND require that the . current contents of the operand be readable and therefore will not function properly on the write-only registers.
13.9.2 Register Pointer
Within the register addressing modes provided by the Z89 , a register may be specified by its full 8-bit address (OOHFFH) or by a short 4-bit address. In the latter case, the register is viewed as one of the 16 working registers within a working register group. Such a group must be aligned on a 16-byte boundary and is addressed by Register Pointer RP (FDH). As an example, assume the Register Pointer contains 70, thus pointing to the working register group from 70H to 7FH. The LD instruction may be used to initialize register 76H to an immediate value in one of two ways
LD 76,#01H !8-bit register address is given by instruction (3 byte instruction)!
or
LD R6,#01 H
!4-bit working register address is given by instruction; 4-bit work ing register group address is given by Register Pointer (2 byte instruction)!
13-8
The address calculation for the latter case is illustrated in Figure 13.1. Notice that 4-bit working-register addressing offers code compactness and fast execution compared to its 8-bit counterpart.
za To modify the contents of the Register Pointer, the
provides the instruction
SRP #value
Execution of this instruction will load the upper four bits of the Register Pointer; the lower four bits are always set to
zero. Although a load instruction such as
LO RP, #value
could be used to perform the same function, SRP provides execution speed (six vs. ten cycles) and code space (two vs. three bytes) advantages over the LO instruction. The instruction
SRP #?OH
II
is used to set the Register Pointer for the previous example.
Register Pointer
0
Instruction (LO R6, #1)
Register Address
0
0 0 0 0
0
0
0
0
0 0
0 0 0 0
0 0 0
Figure 13-1. Address Calculation Using The Register Pointer
13.9.3 Context Switching
A typical function performed during an interrupt service routine is context switching. Context switching refers to the saving and subsequent restoring of the program counter, status, and registers of the interrupted task.
za· During an interrupt machine cycle, the automatically
saves the Program Counter and status flags on the stack. It is the responsibility of the interrupt service routine to preserve the register space. The recommended means to this end is to allocate a specific portion of the register file for use by the service routine. The service routine thus preserves the register space of the interrupted task by avoiding modification of registers not allocated as its own. The most efficient scheme with which to implement this function in the ZS is to allocate a working register group (or portion thereof) to the interrupt service routine. In this way, the preservation of the interrupted task's registers is solely a matter of saving the Register Pointer on entry to the service routine, setting the Register Pointer to its own working register group, and restoring the Register Pointer prior to exiting the service routine. For example, assume such a register allocation scheme has been implemented in which the interrupt service routine for IRQO may access only working register
Group 4 (registers 40H-4FH). The service routine for IRQO should be headed by the code sequence:
PUSH RP SRP #40H
!preserve Register Pointer of in terruptedtask! !addressworking register group 41
Before exiting, the service routine should execute the instruction
POP RP
to restore the Register Pointer to its entry value.
It should be noted thatthe technique described above need not be restricted to interrupt service routines. Such a technique might prove efficient for use by a subroutine requiring intermediate registers to produce its outputs. In this way, the calling task can assume that its environment is intact upon return from the subroutine.
13-9
13.9.4 Addressing Mode
zs· The provides three addressing modes for accessing
the register space: Direct Register, Indirect Register, and Indexed.
13.9.5 Direct Register Addressing
This addressing mode is used when the target register address is known at assembly time. Both long (S-bit) register addressing and short (4-bit) working register addressing are supported in this mode. Most instructions supporting this mode provide access to single S-bit registers. For example:
LD FEH,#HI STACK
!load register FEH (SPH) with the upper Sbits of the label STACKI
AND OOH,MASK_REG
register whose S-bit register address or 4-bit working register address is given by the instruction. This mode is used when the target register address is not known at assembly time and must be calculated during program execution. For example, assume registers 60H-7FH contain a buffer for output to the serial line via repetitive calls to procedure SERIAL_OUT. SERIAL_OUT expects working register Oto hold the output character. The following instructions illustrate the use of the indirect addressing mode to accomplish this task:
LD R1,#20H
!working register 1 is the byte counter output 20H bytes!
LD R2,#60H
ouLagain:
!working register 2 is the buffer pointer register!
!AND register 0 with register named MASK_REG!
OR 01H,RS
LD RO,@R2
!load into working registerOthe byte pointed to by working register 21
!OR register 1 with working register S!
INC R2 !increment pointer!
Increment word (INCW) and decrement word (DECW) are the only two ZS instructions which access 16-bit operands. These instructions are illustrated below for the direct register addressing mode:
INCW ARO
!increment working register pair RO, A R1=R1+1 RO= RO + carry!
DECW 7EH
!decrement working register pair 7EH, 7FH 7FH=7FH-1 7EH = 7EH - carry!
Note that the instruction
INCW RAS
CALL SERIAL_OUT
!outputthe byte!
DJNZ R1 ,ouLagain
!loop till done!
Indirect addressing may also be used for accessing a 16bit register pair via the INCW and DECW instructions. For example:
INCW @RO
!increment the register pair whose ad dress is contained in working register O!
DECW @7FH
!decrement the register pair whose address is contained in register 7FH!
will be flagged as an error by the assembler (RAS not evennumbered).
13.9.6 Indirect Register Addressing
In this addressing mode, the operand is pointed to by the
The contents of registers RO and 7FH should be even numbers for proper access; when referencing a register pair, the least significant address bit is forced to the appropriate value by the ZS. However, the register used to point to the register pair need not be an even-numbered register.
13-10
ft'2iUJ6
zat MICROCOHTROLLERS
Since the indirect addressing mode permits calculation of a target address prior to the desired register access, this mode may be used to simulate other, more complex addressing modes. For example, the instruction
SUB 4,BASE(R5)
requires the indexed addressing mode which is not directly supported bytheZ88subtractinstruction. This instruction can be sirulatedasfolb.vs
LO R6,#BASE
!working register 6 has the base address!
ADD R6,R5
!calculate the target address!
SUB 04H,@R6
!now use indirect addressing to perform the actual subtract!
Any available register or working register may be used in place of R6 in the above example.
13.9.7 Indexed Addressing
The indexed addressing mode is supported by the load instruction (LO) for the transference of bytes between a working register and another register. The effective address of the latter register is given by the instruction which is offset by the contents of a designated working (index) register. This addressing mode provides efficient memory usage when addressing consecutive bytes in a block of
register memory, such as a table or a buffer. The working
register used as the index in the effective address calculation can serve the additional role of counter to control a loop's duration.
For example, assume an ASCII character buffer exists in register memory starting at address BUF for LENGTH bytes. In order to determine the logical length of the character string, the buffer should be scanned backward until the first non-occurrence of a blank character. The following code sequence may be used to accomplish this task:
LO RO,#LENGTH
!length of buffer! !starting at buffer end, look for 1st nonblank!
loop: LO CP JR
R1,BUF-1(RO) R1,#'' ne,found
!found non-blank!
DJNZ RO.loop
all_blanks:
!look at next! !length=O!
El
found
5 instructions 12 bytes 6 cycles overhead 42 cycles per character tested
At labels "all_blanks" and "found," RO contains the length of the character string. These labels may refer to the same location, but they are shown separately for an application where special processing is required for a string of zero length. To perform this task without indexed addressing would require a code sequence such as:
LO R1 ,#BUF+LENGTH-1 LO RO,#LENGTH
!starting at buffer end, look for 1st non-blank!
loop1:
CP @R1,#'' JR ne,found1
!found non-blank!
DEC R1
!dee pointer!
DJNZ RO,loop1
!are we done?!
all_blanks1: !length=O!
found1:
6 instructions 13 bytes 12 cycles overhead 38 cycles per character tested
The latter method requires one more byte of program memorythanthefonner,butisfasterbyfourexecutioncyclesper character tested.
13-11
7.8' MICROCOHTROLLERS
As an alternative example, assume a buffer exists as described above, but it is desired to scan this bufferforward for the first occurrence of an ASCII carriage return. The following illustrates the code to do this:
data memory, more complex addressing modes may be simulated. For example, the instruction
LDC R3,BASE(R2)
LD
next: LD CP JR
RO,# - LENGTH
!starting at buffer start, look for 1st car riage return(= OOH)!
r1,BUF + LENGTH(RO) R1,#0DH eq,cr
requires the indexed addressing mode, where BASE is the base address of a table in program memory and R2 contains the offset from table start to the desired table entry. The following code sequence simulates this instruction with the use of two additional registers (RO and R1 in this example):
LD RO,#HI BASE LD R1,#LO BASE
!found it!
!ARO has table start address!
INC RO !update counter/index!
JR nz,next !try again!
er: ADD RO,#LENGTH !RO has length to CR!
ADD R1,R2 ADC R0,#0
!ARO has table entry address!
LDC R3,@RRO
!R3 has the table entry!
13.10.1 Configuring the ZS for 1/0 Applications as Opposed to Memory Intensive Applications
7 instructions 16bytes 6 cycles overhead 48 cycles per character tested
13.10 Accessing Program and External Data Memory
In a single instruction, the Z8111 can transfer a byte between register memory and either program or external data memory. Load Constant (LDC) and Load Constant and Increment (LOCI) reference program memory; Load External (LOE) and Load External and Increment (LDEI) reference external data memory. These instructions require that a working register pair contain the address of the byte in either Program or External Data Memory to be accessed by the instruction (indirect working register pair addressing mode). The register byte operand is specified by using the direct working register addressing mode in LDC and LOE or the indirect working register addressing mode in LOCI and LDE1. In addition to performing the designated byte transfer, LOCI and LDEI automatically increment both the indirect registers specified by the instruction. These instructions are therefore efficient for performing block moves between register and either program or external data memory. Since the indirect addressing mode is used to specify the operand address within program or external
The ZB offers a high degree of flexibility in memory and 1/0 intensive applications. For devices with thirty-two port bits provided, 16, 12, eight, or zero may be configured as address bits to external memory. This allows for addressing of up to 64K bytes of external memory, which can be expanded to 128K bytes if the Data Memory Select output (OM) is used to distinguish between program and data memory accesses. The following instructions illustrate the code sequence required to configure the ZB with 12 external addressing lines and to enable the Data Memory Select output:
LD P01M,# 00010010B
!bit 3-4 enable ADO-AD?; bit 0-1 enable AB-A 11 !
LD P3M,# 00010010B !bit 3-4 enable OM!
The two bytes following the mode selection of Port O and Port 1 should not reference external memory due to pipelining of instructions within the ZB. Note that the load instruction to P3M satisfies this requirement (providing that it resides within the internal program memory).
13-12
Z8" MICROCONTROLLERS
13.10.2 LDC and LOE
13.10.4 LDEI
To illustrate the use of the Load Constant (LDC) and Load External (LDE) instructions, assume there exists a hardware configuration with external memory and Data Memory Select enabled.
13.10.3 Accessing Program and External Data Memory
LOCI instruction provides an economical means of initializing consecutive registers from an initialization table in program memory. The following code excerpt illustrates this technique of initializing control registers F2H through FFH from a 14-byte array (INIT_tab) in program memory:
SRP #OOH
LD R6,#HI !NIT_tab LD R7,#LO INIT_tab LD R8,#F2H
!1st reg to be initialized!
LD R9,#0EH
loop:
!length of register block!
The LDEI instruction is useful for moving blocks of data between external and register memory since auto-increment is performed on both indirect registers designated by the instruction. The following code excerpt illustrates a register buffer being saved at address 40H through 60H into external memory at address SAVE:
LD R10,#HI SAVE
El
!external memory!
LD R11,#LO SAVE
!address!
LD R8,#40H
LD loop:
!starting register!
R9,#21H
sponding mask bit is a logic 1.
!number of registers to save in external data memory!
LDEI @RR1 O,@R8
LOCI @R8,@RR6
!initaregister!
!load a register from the inittable!
DJNZ R9,loop
DJNZ R9,loop
!until done!
!continue till done!
7 instructions 14 bytes 30 cycles overhead 30 cycles per register initialized
6 instructions 12 bytes 24 cycles overhead 30 cycles per register saved
13.11 BIT MANIPULATIONS
Support of the test and modification of an individual bit or group of bits is required by most software applications suited to the ZS microcomputer. Initializing and modifying
za the control registers, polling interrupt requests, manipu-
lating port bits for control of or communication with attached devices, and manipulation of software flags for internal control purposes are all examples of the heavy use of bit manipulation functions. These examples illustrate the need for such functions in all areas of the ZB register space.
These functions are supported in the ZB primarily by six instructions:
· Test Under Mask (TM) · Test Complement Under Mask (TCM) · AND · OR · XOR · Complement (COM)
13-13
ZS' MICROCONTROLLERS
These instructions may access any ZS® register, regardless of its inherent type (control, 1/0, or general-purpose), with the exception of the write-only control registers. Table 13-1 summarizes the function performed on the destination byte by each of the above instructions. All of these instructions, with the exception of COM, require a mask operand. The 'selected' bits referenced in Table 13-1 are those bits in the destination operand for which the corre-
Table 13-1 Bit Manipulation Instruction Usage
Opcode TM TCM AND
OR XOR COM
Use
To test selected bits for logic 0 To test selected bits for logic 1 To reset all but selected bits to logicO To set selected bits to logic 1 To complement selected bits To complement all bits
The instructions AND, OR, XOR, and COM have functions common to today's microcontrollers and therefore are not described in depth here. However, examples of the use of these instructions are laced throughout the remainder of this chapter, thus giving an integrated view of their uses in common functions. Since they are unique to the ZS, the functionsofTest under Mask and Test Complement under Mask, are discussed in more detail next.
13.11.1 Test Under Mask (TM)
The Test under Mask instruction is used to test selected bits for logic 0. The logical operation performed is
destination AND source.
Neither source nor destination operand is modified; the FLAGS control register is the only register affected by this instruction. The zero flag (Z) is set if all selected bits are logic O; it is reset otherwise. Thus, if the selected destination bits are either all logic 1 or a combination of 1sand Os, the zero flag would be cleared by this instruction. The sign flag (S) is either set or reset to reflect the result of the AND operation; the overflow flag (V) is always reset. All other flags are unaffected. Table 13-2 illustrates the flag settings which result from the TM instruction on a variety of source and destination operand combinations. Note that a given TM instruction will never result in both the Z and S flags being set.
13.11.2 Test Complement Under Mask
The Test Complement under Mask instruction is used to test selected bits for logic 1. The logical operation perforrnedis
(NOT destination)ANDsource.
Table 13-2 Effects of the TM Instruction
Destination (bilary)
10001100 01111100 10001100 11111100 00011000 01000000
Source (bilary)
01110000 01110000 11110000 11110000 10100001 10100001
Flags
zsv
1 0 0 0 0 0 0 10 0 10 1 0 0 1 0 0
As in Test under Mask, the FLAGS control register is the ?nly re9ister affected by this operation. The zero flag (Z) 1s set 1f all selected destination bits are 1; it is reset otherwise. The sign flag (S) is set or reset to reflect the result of the AND operation; the overflow flag (V) is always reset. Table 13-3 illustrates the flag settings which result from the TCM instruction on a variety of source and destination operand combinations. As with the TM instruc-
z tion, a given TCM instruction will never result in both the
and S flags being set.
Table 13-3 Effects of the TCM Instruction
Destination (binary)
10001100 01111100 10001100 11111100 00011000 01000000
Source (binary)
01110000 01110000 11110000 11110000 10100001 10100001
Flags
z s v
0 0 0
1 0 0 0 0 0 1 0 0 0 10 0 10
13-14
'1' MICROCOHTROLWIS
13.12 Stack Operations
13.12.2 CALL
The ZS® stack resides within an area of data memory (internal or external). The current address in the stack is contained in the stack pointer, which decrements as bytes are pushed onto the stack, and increments as bytes are popped from it. The stack pointer occupies two control register bytes (FEH and FFH) in the ZS register space and may be manipulated like any other register. The stack is useful for subroutine calls, interrupt service routines, and parameter passing and saving. Figure 13-2 illustrates the downward growth of a stack as bytes are pushed onto it.
13.12.1 Internal as Opposed to External Stack
A subroutine call causes the current Program Counter (the address of the byte following the CALL instruction) to be pushed onto the stack. The Program Counter is loaded with the address specified by the CALL instruction. This address may be a direct address or an indirect register pair reference. For example:
LABEL 1
CALL 4F98H
ll
!direct addressing: PC is loaded with the hex value 4F98; address LABEL 1+3 is pushed onto the stack!
The location of the stack in data memory may be selected to be either internal register memory or external data
memory. Bit 2 of control register P01 M(FBH) controls this
selection. Register pair SPH (FEH), SPL (FFH) serves as the stack pointer for an external stack. Register SPL is the stack pointer for an internal stack.
In the latter configuration, SPH is available for use as a general purpose register. The following illustrates a code sequence that initializes external stack operations:
LD P01 M,#OOH
!bit 2: select external stack!
LABEL 2 LABEL3
CALL @RR4
!indirect addressing: PC is loaded with the contents of working register pair R4, RS; address LABEL 2+2 is pushed onto the stack!
CALL @7EH
!indirect addressing PC is loaded with the contents of register pair 7EH, 7FH; address LABEL 3+2 is pushed onto the stack!
LD SPH,#HI
;STACK
LD SPL,#LO
;STACK
xSP-
x -1
x- 2 x- 3
x- 4
Initial State
S P - R1
R1
- PC Low
SP
PC High
Following Push R1
Following Call
Figure 13-2. Growth Of A Stack
13·15
13.12.3 RET
The return (RET) instruction causes the top two bytes to be popped from the stack and loaded into the Program Counter. Typically, this is the last instruction of a subroutine and thus restores the PC to the address following the CALL to that subroutine.
13.12.4 Interrupt Machine Cycle
During an interrupt machine cycle, the PC followed by the status flags is pushed onto the stack. A more detailed discussion of interrupt processing is provided in sections that follow.
13.12.5 IRET
The interrupt return (IRET) instruction causes the top byte to be popped from the stack and loaded into the status flag register, FLAGS (FCH); the next two bytes are then popped and loaded into the Program Counter. In this way, status is restored and program execution continues where it had left off when the interrupt was recognized.
ZS' MICROCONTROLLERS
13.12.6 PUSH and POP
The PUSH and POP instructions allow the transfer of bytes between the stack and register memory, thus providing program access to the stack for saving and restoring needed values and passing parameters to subroutines.
Execution of a PUSH instruction causes the stack pointer to be decremented by 1, the operand byte is then loaded into the location pointed to by the decremented stack pointer. Execution of a POP instruction causes the byte addressed by the stack pointer to be loaded into the operand byte; the stack pointer is then incremented by 1. In both cases, the operand byte is designated by either a direct register address or an indirect register reference. For example:
PUSH R1 POP 05H PUSH @R4
PUSH @11 H
!indirect address: push working register 1 onto the stack! !direct address: pop the top stack byte into register 5! !indirect address: pop the top stack byte into the byte pointed to by working register 4! !indirect address: push onto the stack the byte pointed to by register 17!
13.13 Interrupts
The ZS® recognizes six different interrupts from internal and external sources, including internal timer/counters, serial 1/0, and Port 3 lines. Interrupts may be individually or globally enabled/disabled using the Interrupt Mask Register IMR (FBH) and may be prioritized for simultaneous interrupt resolution using the Interrupt Priority Register IPR (F9H). When enabled, interrupt request processing automatically vectors to the designated service routine. When disabled, an interrupt request may be polled to determine when processing is needed.
13.13.1 Interrupt Initialization
corresponding IRQ bit cannot be set. The El instruction is specially decoded by the ZS to enable the IRQ; simply setting bit 7 of IMR is therefore not sufficient to enable interrupt processing following RESET. However, subsequent to this initial El instruction, interrupts may be globally enabled either by the instruction:
El
!enableinterrupts!
or by a register manipulation instruction such as
OR IMR,#SOH
Before the ZS can recognize interrupts following RESET, some initialization tasks must be performed. The initialization routine should configure the ZS interrupt requests to be enabled/disabled, as required by the target application and assigned a priority (via IPR) for simultaneous enabledinterrupt resolution. An interrupt request is enabled if the corresponding bit in the IMR is set (=1) and interrupts are globally enabled (bit 7 of IMR = 1). An interrupt request is disabled if the corresponding bit in the IMR is reset (=0) or interrupts are globally disabled (bit 7 of IMR =0).
A RESET of the ZS causes the contents of the Interrupt Request Register IRQ (FAH) to be held to zero until the execution of an El instruction. Interrupts that occur while the ZS is in this initial state will not be recognized since the
To globally disable interrupts, execute the instruction
DI
!disable interrupts!
This will cause bit 7 of IMR to be reset.
Interrupts must be globally disabled prior to any modification of the IMR, IPR or enabled bits of the IRQ (those corresponding to enabled interrupt requests), unless it can be guaranteed that an enabled interrupt will not occur during the processing of such instructions. Since interrupts represent the occurrence of events asynchronous to program execution, it is highly unlikely that such a guarantee can be made reliably.
13-16
1' MICRocoNTROLLERS
13.13.2 Vectored Interrupt Processing
Enabled interrupt requests are processed in an automatic vectored mode in which the interrupt service routine address is retrieved from within the first 12 bytes of Program Memory. When an enabled interrupt request is recognized by the ZS, the Program Counter is pushed onto the stack (low order 8 bits first, then high-order 8 bits) followed by the FLAGS register (FCH). The corresponding interrupt request bit is reset in IRQ, interrupts are globally disabled (bit 7 of IMR is reset), and an indirect jump is taken on the word in location 2x, 2x + 1 (x =interrupt request number,O~s;5). For example, if the bytes at addresses 0004H and 0005H contain 05H and 78H respectively, the interrupt machine cycle for IRQ2 will cause program execution to continue at address 0578H.
When interrupts are sampled, more than one interrupt may be pending. The Interrupt Priority Register (IPR) controls the selection of the pending interrupt with highest priority. While this interrupt is being serviced, a higher-priority
interrupt may occur. Such interrupts may be allowed service within the current interrupt service routine (nested) or may be held until the current service routine is complete (non-nested).
To allow nested interrupt processing, interrupts must be selectively enabled upon entry to an interrupt service routine. Typically, only higher-priority interrupts would be allowed to nest within the current interrupt service. To do this an interrupt routine must "know" which interrupts have a higher priority than the current interrupt request. Selection of such nesting priorities is usually a reflection of the priorities established in the Interrupt Priority Register (IPR). Given this data, the first instructions executed in the service routine should be to save the current Interrupt Mask Register, mask off all interrupts of lower and equal priority, and globally enable interrupts (El). For example, assume that service of interrupt requests 4 and 5 are nested within the service of interrupt request 3. The following illustrates the code required to enable IRQ4 and IRQ5:
II
CONSTANT
GLOBAL IRQ3_service
INT_MASK_3 PROCEDURE
PUSH IMR
AND IMR,#INT_MASK_3
El !. .. !
DI POP IMR IRET END IRQ3_service
001100008 ENTRY !service routine for IRQ3!
!interruptswere globally disabled during the interruptmachine cycle -no DI is needed prior to modification of IMR! !disable all but IRQ4 & 5!
!service interrupt! !interrupts are globally enabled now- must disable them prior to modification of IMR!
!restore entry IMR!
Note: IRQ4 and IRQ5 are enabled by the above sequence after IRQ3_service only if their respective IMR bits = 1 on entry to
IR03_servlce.
13-17
Note (Continued): The service routine for an interrupt whose processing is to be completed without interruption should not allow interrupts to be nested within it. Therefore, it need not modify the IMR, since interrupts are disabled automatically during the interrupt machine cycle.
The service routine for an enabled interrupt is typically concluded with an IRET instruction, which restores the FLAGS register and Program Counter from the top of the stack and globally enables interrupts. To return from an interrupt service routine without re-enabling interrupts, the following code sequence could be used:
!R.AGS=@SP!
AET
IPC=@SP!
This accomplishes all the functions of IRET, except that IMR is not affected.
13-18
7J' MICROCONTROLWS
13.13.3 Polled Interrupt Processing
Disabled interrupt requests may be processed in a polled mode, in which the corresponding bits of the Interrupt Request Register (IRQ) are examined by the software. When an interrupt request bit is found to be a logic 1, the interrupt should be processed by the appropriate service routine. During such processing, the interrupt request bit in the IRQ must be cleared by the software in order for subsequent interrupts on that line to be distinguished from
the current one. If more than one interrupt request is to be processed in a polled mode, polling should occur in the order of established priorities. For example, assume that IRQO, IRQ1, and IRQ4 are to be polled and that established priorities are, from high to low, IRQ4, IRQO, IRQ1. An instruction sequence like the following should be used to poll and service the interrupts:
!...!
!poll interrupt inputs here!
TCM
JR
CALL
IRQ, #000100006 NZ,TESTO IRQ4_service
!IRQ4 need service?! !no! !yes!
TESTO TCM
IRQ, #000000016
JR
NZ,TEST1
CALL
IRQO_service
!IRQO need service?! !no!
TEST1 DONE!...!
TCM
JR
CALL
IRQ, #000000106 NZ.DONE IRQ1_service
!IRQ1 need service?! !no!
IRQ4_service
PROCEDURE
ENTRY
!... ! AND !...! RET
IRQ, #111011116
!clear IRQ4!
END IRQ4_service
IRQO_service
PROCEDURE
ENTRY
!...! AND
!...!
RET
IRQ, #1111111 OB
!clear IRQO!
END IRQO_service
IRQ1_service
!. .. ! AND !. .. ! RET
PROCEDURE
ENTRY
IRQ, #111111016
!clear IRQ1 !
END IRQ1_service !. .. !
13-19
'11' MrCROCOHTROu.ERS
13.14 Timer/Counter Functions
The ZS41 provides two S-bit timer/counters, TO and T1, that are adaptable to a variety of application needs and thus allow the software (and external hardware) to be relieved of the bulk of such tasks. Included in the set of such uses are:
· Internal Delay Timer
· Maintenance of a Time-Of-Day Clock
· Watch-Dog Timer
· External Event Counting
· Variable Pulse Train Output
· Duration Measurement of External Event
characterizes the relation between the prescaler (p), counter (v), and clock input period (t); is given by
1/(XTAUS)
(assumes internal clock set for XTAL divide by 2 mode)
where XTAL is the ZS input clock frequency; p is in the range 1-64; vis in the range 1-256. When programming the prescaler and counter registers, the maximum load value is truncated to six and eight bits, respectively, and is therefore programmed as zero. For an input clock frequencyof S MHz, the prescaler and counter register values may be programmed to time an interval in the range
1usx 1x1sis1usx64x256 1us sis 16.3S4 ms
· Automatic Delay Following External Event Detection
Each timer/counter is driven by its own 6-bit prescaler, which is in turn driven by the internal ZS clock divided by four. For T1, the internal clock may be gated or triggered by an external event or may be replaced by an external clock input. Each timer/counter may operate in either singlepass or continuous mode where, at end-of-count, either counting stops or the counter reloads and continues counting. The counter and prescaler registers may be altered individually while the timer/counter is running; the software controls whether the new values are loaded immediately or when end-of-count (EOC) is reached.
Although the timer/counter prescaler registers (PAEO and PRE1) are write-only, there is a technique by which the timer/counters may simulate a readable prescaler. This capability is a requirement for high resolution measurement of an event's duration. The basic approach requires that one timer/counter be initialized with the desired counter and prescaler values. The second timer/counter is initialized with a counter equal to the prescaler of the first timer/ counter and a prescaler of 1. The second timer/counter must be programmed for continuous mode. With both timer/counters driven by the internal clock and started and stopped simultaneously, they will run synchronous to one another; thus, the value read from the second counter will always be equivalent to the prescaler of the first.
13.14.1 Time/Count Interval Calculation
To determine the time interval (i) until EOC, the equation
i=txpxv
To determine the count (c) until EOC for T1 with external clock input, the equation
c=pxv
characterizes the relation between the T1 prescaler (p) and the T1 counter (v). The divide-by-Son the inputfrequency is bypassed in this mode. The count range is
1x1ScS64x256 1ScS16,3S4
13.14.2 T001 Modes
Port 3, bit 6 (P36) may be configured as an output (Tour> which is dynamically controlled by one of the following
· Internal Clock
When driven byT0 orT1, T0ur is reset to a logic 1 when the corresponding load bit is set in timer control register TMR (F1 H) and toggles on EOC from the corresponding counter.
When TouT is driven by the internal clock, that clock is directly output on P36.
While programmed as TouT· P36 is disabled from being modified by a write to port register 03H; however, its current output may be examined by the ZS software by a read to port register 03H.
13-20
ZS' MICROCONlROLLERS
13.14.3 T1N Modes
Port3, bit 1(P31)maybe configured asan input(T1N)which is used in conjunction with T1 in one of four modes.
· External Clock Input
· Gate Input for Internal Clock
· Nonretriggerable Input for Internal Clock
· Retriggerable Input for Internal Clock
For the latter two modes, it should be noted that the existence of a synchronizing circuit within the ZB" causes a delay of two to three internal clock periods following an external trigger before clocking of the counter actually begins.
Each High-to-Low transition on T1N will generate interrupt request IRQ2, regardless of the selected T1N mode or the enabled/disabled state of T1. IRQ2 must therefore be masked or enabled according to the needs of the application.
The 'external clock input' T1Nmode supports the counting of external events, where an event is seen as a High-to-Low transition on T1N. Interrupt request IRQ5 is generated on the nth occurrence (single-pass mode) or on every nth occurrence (continuous mode) of that event.
The "gate input for internal clock" T1Nmode provides for duration measurement of an external event. In this mode, the T1 pre scaler is driven by the ZB internal clock, gated by a High level on T1N. In other words, T1 will count while T1N is High and stop counting while T1N is Low. Interrupt request IRQ2 is generated on the High-to-Low transition on T1N. Interrupt request IRQ5 is generated on T1 EOC. This mode may be used when the width of a High-going pulse needs to be measured. In this mode, IRQ2 is typically the interrupt request of most importance, since it signals the end of the pulse being measured. If IRQ5 is generated prior to IRQ2 in this mode, the pulse width on T1Nis too large for T1 to measure in a single pass.
The "nonretriggerable input" T1Nmode provides for auto matic delay timing following an external event. In this
mode, T1 is loaded and clocked by the ZB internal clock following the first High-to-Low transition on T1Nafter T1 is enabled. T1Ntransitions that occur after this point do not affect T1· In single-pass mode, the enable bit is reset on EOC; further T1N transitions will not cause T1 to load and begin counting until the software sets the enable bit again. In continuous mode, EOC does not modify the enable bit,
but the counter is reloaded and counting continues immediately; IRQ5 is generated every EOC until software resets the enable bit. This T1N mode may be used, for example, to time the line feed delay following end of line detection on a printer or to delay data sampling for some length of time following a sample strobe.
11
The "retriggerable input" T1Nmode will load and clock T1 with the ZB internal clock on every occurrence of a Highto-Low transition on T1N. T1 will time-out and generate interrupt request IRQ5 when the programmed time interval (determined by T1 prescaler and load register values) has elapsed since the last High-to-Low transition on T1w In single-pass mode, the enable bit is reset on EOC; further T1N transitions will not cause T1 to load and begin counting until the software sets the enable bit again. In continuous mode, EOC does not modify the enable bit, butthe counter is reloaded and counting continues immediately; IRQ5 is generated at every EOC until the software resets the enable bit. This T1Nmode may provide such functions as watch-dog timer (in other words, interrupt if conveyor belt stopped or clock pulse missed), or keyboard time-out (in other words., interrupt if no input in x ms).
13-21
13.14.4 Examples
Several possible uses of the timer/counters are given in the following four examples.
13.14.5 Time-Of-Day Clock
The following module illustrates the use of T1 for maintenance of a time-of-day clock, which is kept in binary format in terms of hours, minutes, seconds, and hundredths of a
ZS' MICROCONTROLLERS
second. It is desired thatthe clock be updated once every hundredth of a second; therefore,T1 1 is programmed in continuous mode to interrupt 100 times a second. Although T1 is used for this example, TO is equally suited for the task.
The procedure for initializing the timer (TOD_INIT), the interrupt service routine (TOD) which updates the clock, and the interrupt vector forT1 end-of-count (IRQ_5) are illustrated below ()<TAL = 7.3728 MHz, XTALJ2 mode is assumed):
ZBASM2.0 LOC OBJ CODE
P 0000 OOOF'
POOOC P 0000 E6 F3 93
P 0003 E6 F2 00 P 0006 46 F1 OC P 0009 BF P OOOA 46 FB 20 P OOOD 9F P OOOEAF P OOOF
P OOOF
P OOOF 70 FD
P0011 3110 P 0013 FE P 0014 A6 EF 64 P 0017 EB 13 P 0019 BO EF P 001B EE P 001C A6 EE 3C P 001F EB OB P 0021 BO EE
STMT SOURCE STATEMENT
1 TIMER1
MODULE
2 CONSTANT
3
HOUR=
R12
4
MINUTE
R13
5
SECOND
R14
6
HUND=
R15
7
$SECTION PROGRAM
B GLOBAL
9 !IRQ5 interrupt vector!
10
$ABS 10
11
IRQ_5 ARRAY [1 WORD]
[TOD]
12
13
$REL
14 TOD_INIT
PROCEDURE
15 ENTRY
16
LD PRE1,#10010011 B
17
!bit 2-7 prescaler = 36;
18
bit 1 internal clock;
19
bit 0 continuous mode!
20
LO T1 ,#OOH
!(256) time-out =
21
1/100 second!
22
OR TMR,#OCH
!load, enable T1 !
23
DI
24
OR IMR,#20H
!enable T1 interrupt!
25
El
26
RET
27 END TOD_INIT
28
29 TOD PROCEDURE
30 ENTRY
31
PUSH RP
32
!Working register file 1OH to 1FH contains
33
the time of day clock!
34
SAP #10H
35
INC HUND
!1 more .01 sec!
36
CP HUND,#64H
!full second yet?!
37
JR NE,TOD_EXIT
!jump if no!
38
CLR HUND
39
INC SECOND
!1more second!
40
CP SECOND,#3CH
!full minute yet?!
41
JR NE,TOD_EXIT
!jump if no!
42
CLR SECOND
13-22
't'ZJLCE
P 0023 DE
43
P 0024 A6 ED 3C
44
P 0027 EB 03
45
P 0029 BO ED
46
P 002B CE
47
48
P 002C 50 FD
49
P 002E BF
50
P 002F
51
52
0 ERRORS ASSEMBLY COMPLETE
TOD_INIT 7 instructions 15 bytes 16 us
INC CP JR CLR INC TOD_EXIT:
MINUTE MINUTE,#3CH NE,TOD_EXIT MINUTE HOUR
POP RP IRET END TOD END TIMER1
!1 more minute! !full hour yet?! !jump if no!
!restore entry RPI
TOD 17 instructions 32bytes 19.5 us (average) including interrupt response time
II
13-23
13.14.6 Variable Frequency, Variable Pulse Width Output
The following module illustrates one possible use of Tour Assume it is necessary to generate a pulse train with a 10 percent duty cycle, where the output is repetitively high for 1.6 ms and then low for 14.4 ms. To do this, ToUT is controlled by end-of-count from T1, although TO could alternately be chosen. This examples makes use of the ZS feature that allows a timer's counter register to be modified without disturbing the count in progress. In continuous mode, the new value is loaded when T1 reaches EOC. T1 is first loaded and enabled with values to generate the short interval. The counter register is then immediately modified with the value to generate the long interval; this value is loaded into the counter automatically on T1 EOC. The prescaler selected value must be the same for both
1B' MICROCONIROLLERS
long and short intervals. Note that the initial loading of the T1 counter register is followed by setting the T1 load bit of timer control register TMR (F1 H); this action causes T0UT to be reset to a logic 1output. Each subsequent modification of the T1 counter register does not affect the current ToUT level, since the T1 load bit is NOT altered by the software. The new value is loaded on EOC and TOUT will toggle at that time. The T1 interrupt service routine should simply modify the T1 counter register with the new value, alternating between the long and short interval values.
In the example which follows, bit 0 of register 04H is used as a software flag to indicate which value was loaded last. This module illustrates the procedure for T1frOUT initialization (PULSE_INIT), the T1 interrupt service routine (PULSE), and the interrupt vector forT1 1 EOC (IRQ_5). XTAL = 8 MHz, XTAU2 mode is assumed.
ZBASM 2.0 LOC OBJ CODE
p 00000017' POOOC P 000 E6 F3 03
P 0003 E6 F7 00 P 0006 E6 F2 19 P 0009 BF P OOOA 46 FB 20 P OOOD E6 F1 BC
P 0010 E6 F2 E1 P 0013 BO 04 P 0015 9F P 0016 AF
STMT SOURCE STATEMENT
1 TIMER2
MODULE
2
$SECTION PROGRAM
3 GLOBAL
4
5
ABS 10
6 IRQ_5 ARRAY[1 WORD]
7
B
$REL
9 PULSE_INIT PROCEDURE
10 ENTRY
11
LD PRE1 ,#00000011 B
12
13
14
15
LD P3M,#OOH
16
LD T1,#19H
17
DI
1B
OR IMR,#00100000B
19
LD TMR,#100011008
20
21
22
23
!IRQ5 interrupt vector!
[PULSE]
!bit 2-7 prescaler= 64; bit 1 internal clock; bit 0 continuous mode! !bit 5: P36 =output (Tour)! !for short interval!
!enable T1 interrupt!
!bit 6-7 Tout controlled byT1; bit 3 enable T1 ; bit 2 load T1 !
24 !Set long interval counter, to be loaded on T1 EOC!
25
LD T1,#0E1H
26 !Clear alternating flag for PULSE!
27
CLR 04H
28
29
El
30
RET
!= o 25 next;
= 1 225 next!
13-24
p 0017
p 0017
P 0017 E6 F2 E1 P 001A B6 04 01 P001D 6B 03 P 001F E6 F2 19
P 0022 BF P0023
31
END PULSE_INIT
32
33
34
PULSE PROCEDURE
35
ENTRY
36
LD T1,#0E1H
37
XOR 04H,#01H
38
JR Z,PULSE_EXIT
39
LD T1,#19H
40 PULSE_EXIT
41
IRET
42 END PULSE
43 END TIMER2
!new load value! !which value next?! !should be225! !should be 25!
0 ERRORS ASSEMBLY COMPLETE
PULSE_INIT 10 instructions 23 bytes 23 us
PULSE 5 instructions 12 bytes 25 us (average) including interrupt response time
'118 MICROCOHTROLLERS
II
13-25
13.14.7 Cascaded Timer/Counters
For some applications it may be necessary to measure a greater lime interval than a single timer/counter can measure (16.384 ms). In this case, T1N and Tovr may be used to cascade TO and T1 to function as a single unit. ToUT· programmed to toggle on TO end-of-count, should be wired back to T1N, which is selected as the external clock input for T1 . With TO programmed for continuous mode, T0UT (and therefore T,N) goes through a High-to-Low transition (causing T1 to count) on every other TO EOC. Interrupt request IRQ5 is generated when the programmed time interval has elapsed. Interrupt requests IRQ2 (generated on every T1N High-to-Low transition) and IRQ4 (generated on TO EOC) are of no importance in this application and are therefore disabled.
To determine the time interval (i) until EOC, the equation
i = t x pO x vO x (2 x p1 x v1 - 1)
characterizes the relation between the TO prescaler (pO) and counter (vO), the T1 prescaler (p1) and counter (v1), and the clock input period (t). Assuming XTAL= 8 MHz, the measurable time interval range is:
1 us x 1x1 x (2 x 1 - 1) :S: i :S:
1 us x 64 x 256x (2 x 64 x 256- 1)
1 us :S: i :S: 536.854528 s
Figure 13-3 illustrates the interconnection between TO and T1 . The following module illustrates the procedure required to initialize the timers for a 1.998 second delay interval
XTAL
8-BltTO Counter ToUT(P3sJ
- - - - - To Interrupt Logic (IRQ4)
.___ _ _ _ To Interrupt Logic (IRQ5)
Figure 13-3. Cascaded Timer/Counters
13-26
ZS- MICROCONTROLLERS
ZBASM 2.0
LOC OBJ CODE
p 0000 P 0000 E6 F3 28
P 0003 E6 F7 00 P 0006 E6 F2 64 P 0009 E6 F5 29
STMT 1 2 3 4 5 6 7 8 9
10 11
SOURCE STATEMENT
TIMER3
MODULE
GLOBAL
TIMER_16
PROCEDURE
ENTRY
LO
PRE1,#001010008
LO
P3M,#OOH
LO
T1 ,#64H
LO
PRE0,#001010018
P OOOC E6 F4 64 P OOOF BF P 0010 56 FB 2B P 0013 46 FB 20 P 0016 9F P 0017 E6 F1 4F
P 001A AF P001B
13
14
LO
T0,#64H
15
DI
16
AND
IMR,#00101011 B
17
18
OR
IMR,#001000008
19
El
20
LO
TMR,#010011118
21
22
23
24
25
26
27
28
29
RET
30
END TIMER_16
31
END TIMER3
0 ERRORS ASSEMBLY COMPLETE
11 instructions 27 bytes 26.6 us
!bit 2-7 prescaler =1O;
bit 1 external clock; bit 0 single-pass mode! !bit 5 let P36 be Tout! !T1 counter register! 12
!bit 2-7 prescaler =1O;
bit Ocontinuous mode! !TO counter register!
!disable IRQ2 (Tin); and IRQ4 (TO)! !enable IRQ5 (T1 )!
!bit6-7T=oontrolled by TO; bit4-5T,Nmodeisext. clock input; bit 3 enable T1; bit 2 load T1; bit 1 enable TO; bit 0 enable TO!
El
13-27
'lJ' MICROCONlROUERS
13.14.8 Clock Monitor
T1 and T1N may be used to monitor a clock line (in a diskette drive, for example) and generate an interrupt request when a clock pulse is missed. To accomplish this, the
clock line to be monitored is wired to P31 (T1N). T1Nshould be programmed as a retriggerable inputto T1, such that each falling edge on T1Nwill cause T1 to reload and continue counting. If T1 is programmed to time-out after an interval of one-and-a-half times the clock period being monitored, T1 will time-out and generate interrupt request IRQ5 only if a clock pulse is missed.
The following module illustrates the procedure for initializing T1 and T1N(MONITOR__INIT) to monitor a clock with a period of 2us. XTAL = 8 MHz is assumed. Note that this example selects single-pass rather than continuous mode for T1. This is to prevent a continuous stream of IRQ5 interrupt requests in the eventthatthe monitored clock fails completely. Rather, the interrupt service routine (CLK_ERR) is left with the choice of whether or not to re-enable the monitoring. Also shown is the T1 interrupt vector (IRQ_5).
Z8ASM2.0 LOC OBJ CODE
p 0000 0015'
POOOC P 0000 E6 F3 04
P0003E6F700 15 P0006E6F203 16 P 0009 BF POOOA56F83B 19 POOOD46FB20 :D P00109F P 0011 E6 F1 38
P 0014 AF p 0015
p 0015
STMT SOURCE STATEMENT
1 TIMER4
MODULE
2
$SECTION PROGRAM
3 GLOBAL
4
5
$ABS 10
6
IRQ_5 ARRAY[1 WORD]
7
8
$REL
9
MONITOR_INITPROCEDURE
10 ENTRY
11
LO PRE1 ,#00000100B
12
13
14
LD
P3v1,m-l
LD T1,m-l
17
18
DI
PNJ 111.41,#00111011B
CR
1~#001CXXXXB
21
8
22
23
LO TMR,#001110008
a:i
25
26
27
RET
28 END MONITOR_INIT
29
30
31 CLK__ERR PROCEDURE
32 ENTRY
33
!. .. !
34
35 !if clock monitoring should continue ... !
!IRQ5 interrupt vector! [CLK__ERR]
!bit 2-7 prescaler =1;
bit 1 external clock;
bit osingle-pass model
!bit51etP36beTOlJT"! !T1 loadregister, =1.5*2usec! ldisablelRQ2(T;N)! !enablelRQ5(T1)!
!bit4-5~NmodeiS
retrig. input; bit 3 enable T1 !
!handle the missed clock!
13-28
P 0015 46 F1 08
36
OR TMR, #000010006
37
P 0018 BF
38
IRET
p 0019
39 END CLK_ERR
40 END TIMER4
0 ERRORS
ASSEMBLY COMPLETE
MONITOR_INIT
CLK_ERR
9 instructions
2+ instructions
21 bytes
4+ bytes
21 .5 us
18.5 us+ including interrupt response time
!bit 3: enable T1 !
13.15 1/0 FUNCTIONS
The Z81111 provides up to 32 1/0 lines mapped into registers 0-3 of the internal register file. Each nibble of Port 0 is individually programmable as input, output, or address/ data lines (A15-A12, A11-A8). Port 1 is programmable as a byte entity to provide input, output, or address/data lines
o (AD7-ADO). The operating modes for the bits of Ports
and 1 are seiected by control register P01 M (F8H). Selec-
tion of 1/0 lines as address/data lines supports access to
external program and Data Memory. Each bit of Port 2 is
individually programmable as an input or an output bit.
Port 2 bits programmed as outputs may also be programmed (via bit 0 of P3M) to all have active pull-ups or all be open-drain (active pull-ups inhibited). In Port 3, four bits (P30-P33) are fixed as inputs, and four bits (P34-P37) are fixed as outputs, but their functions are programmable. Special functions provided by Port3 bits are listed in Table 13-4.
Note: 1/0 feature options are device dependent. Consult the selected ZS device product specification for exact 1/0 features available.
Table 13-4. Generic ZS MCU Port 3 Special Functions
FUNCTION BIT SIGNAL
P31
P32
P32
Handshake P34
P35
P36
P30
Interrupt
P31
Request
P32
P33
Counter/
P31
Timer
P36
Data Memory
Select
P34
Status Out
P30
Serial 1/0
P37
DAV2/RDY2 DAVO/RDYO DAV1/RDY1
- - RDY1/DAV1
RDYO/DAVO RDY2/DAV2 IRQ3 IRQ2 IRQO IRQ1 TIN TOUT
OM
Serial In Serial Out
13-29
ZS' MICROCONTROLLERS
13.15.1 Asynchronous Receiver/Transmitter Operation
In some cases, full-duplex, serial asynchronous receiver/ Although the ZB directly supports either odd parity or no
transmitter operation is provided using P37 (output) and parity for serial 1/0 operation, even parity may also be
P30 (input) in conjunction with control register SIO (FOH), provided with additional software support. To receive and
SIO is actually two registers: a receiver buffer and a transmit with even parity, the ZB should be configured for
transmitter buffer. Counter{TimerTO provides the clock for serial 1/0 with odd parity disabled. The ZB software must
control of the bit rate.
calculate parity and modify the eighth bit prior to the load
of a character into SIO and then modify a parity error flag
The ZBll always receives and transmits eight bits between following the load of a character from SIO. All other
start and stop bits. However, if parity is enabled, the eighth processing required for serial 1/0 (in other words, buffer
bit (07) is replaced by the odd-parity bit when transmitted management, error handling, and other processing) is the
and a parity-error flag(= 1 if error) when received. Table same as that for odd parity operations.
13-5 illustrates the state of the parity bit/parity error flag
during serial 1/0 with parity enabled.
Table 13-5. Serial 1/0 With Odd Parity
Character Loaded Into SIO
11000011 11000011
01111000 01111000
Transmitted To Serial Line
01000011 01000011
11111000 11111000
Received From Serlal Line
01000011 01000111 11111000 01111000
Transferred Character To SIO
01000011
11000111
01111000 11111000
Note· no error error no error error
· Left most bit is D7 To configure the ZB for Serial 1/0, it is necessary to:
· Enable P30 and P37 for serial 1/0 and select parity,
· Set up TO for the desired bit rate,
· Configure IRQ3 and IRQ4 for polled or automatic interrupt mode,
· Load and enable TO.
To enable P30 and P37 for serial 1/0, bit 6 of P3M (F7H) is set. To enable odd parity, bit 7 of P3M is set; to disable it, the bit is reset. For example, the instruction:
LD P3M,#40H
will enable serial 1/0, but disable parity. The instruction:
LD P3M,#OCOH
will enable serial 1/0, and enable odd parity.
In the following discussions, bit rate refers to all transmitted bits, including start, stop, and parity (if enabled}. The serial bit rate is given by the equation:
input clock frequency bit rate = (2x4xTO prescaler x TO counter x 16)
The final divide-by-16 is incurred for serial communications, since in this mode TO runs at 16 times the bit rate in
za order to synchronize the data stream. To configure the
for a specific bit rate, appropriate values must first be selected for TO prescaler and TO counter by the above equation; these values are then programed into registers TO (F4H) and PREO (F5H) respectively. Note that PREO also controls the continuous vs. single-pass mode for TO; continuous mode should be selected for serial 1/0. For example, given an input clock frequency of 7.3728 MHz and aselected bit rate of9600 bits per second, the equation is satisfied by TO counter = 2 and prescaler = 3. The following code sequence will configure the TO counter and TO prescaler registers:
LD T0,#02H
!TO counter= 2!
LD PRE0,#00001101 B
!bit2-7prescaler=3; bitO
continuous mode!
Interrupt request3 (IRQ3) is generated whenever a character is transferred into the receive buffer; interrupt request 4 (IRQ4) is generated whenever a character is transferred out of the transmit buffer. Before accepting such interrupt requests, the Interrupt Mask, Request, and Priority Registers (IMR, IRQ, and IPR) must be programmed to configure the mode of interrupt response. The section on Interrupt Processing provides a discussion of interrupt configurations.
13-30
To load and enable TO, set bits 0 and 1 of the timer mode register (TMR) via an instruction such as
OR TMR,#03H
This will cause the TO prescaler and counter registers (PREO and TO) to be transferred to the TO prescaler and counter. In addition, TO is enabled to count, and serial 1/0 operations will commence.
Characters to be output to the serial line should be written to serial 1/0 register SIO (FOH). IRQ4 will be generated when all bits have been transferred out.
Characters input from the serial line may be read from SIO. IRQ3 will be generated when a full character has been transferred into SIO.
The following module illustrates the receipt of a character and its immediate echo back to the serial line. It is assumed thatthe Z8· has been configured for serial 1/0 as described above, with IRQ3 (receive) enabled to interrupt, and IRQ4 (transmit) configured to be polled. The received character is stored in a circular buffer in register memory from address 42H to 5FH. Register 41 H contains the address of the next available buffer position and should have been initialized by some earlier routine to 42H.
Z8ASM 2.0 LOC OBJ CODE
P0006 000' POOOO
P 0000 E4 FO FO P 0003 F5 FO 41 p 0006 20 41 P 0008 A6 41 60 POOOB EB03 P OOOD E6 41 42 P 0010 66 FA 10 P 0013 EB FB P 0015 56 FA EF
STMT SOURCE STATEMENT
1 SERIALIO MODULE
2 CONSTANT
3
next_addr
41H
4
start =
42H
5
length=
1EH
6 $SECTION PROGRAM
7 GLOBAL
8
!IRQ3vector!
9
$ABS 6
10 IRQ_3 ARRAY [1 WORD]= [GET_CHARACTER]
11
12
$REL 0
13 GET_CHARACTER PROCEDURE ENTRY
14
15
!Serial 1/0 receive interrupt service!
16
!Echo received character and wait for
17
echo completion!
18
Id
SIO,SIO
!echo!
19
20
!Save it in circular buffer!
21
Id
@next_addr,SIO !save in buffer!
22
inc next_addr
!Point to next position!
23
cp next_addr,#start+length
24
!Wrap-around yet?!
25
jr
ne,echo_wait !No.!
26
Id
next_addr,#start!Yes. Point to start!
27
!Now, waitfor echo complete!
28 echo_wait
29
tern IRQ,#10H
!Transmitted yet?!
30
jr
nz,echo_wait !Not yet!
31
32
and IRQ,#OEFH !Clear IRQ4!
13-31
. . MICROCONTROUERS
P 0018 BF p 0019
33
IRET
34
END GET_CHARACTER
35
END SERIAL_IO
!Return from interrupt!
0 ERRORS ASSEMBLY COMPLETE
10 instructions 25 bytes 35.5 us + 5.5 us for each additional pass through the echo_wait loop, including interrupt response time
13.15.2 Automatic Bit-Rate Detection
In a typical system, where serial communication is required (in other words, a system with a terminal), the desired bit rate is either user-selectable via a switch bank or nonvariable and "hard-coded" in the software. As an alternate method of bit-rate detection, it is possible to automatically determine the bit rate of serial data received by measuring the length of a start bit. The advantage of this method is that it places no requirements on the hardware design for this function and provides a convenient (automatic) operator interface.
In the technique described here, the serial channel of the
za· is initialized to expect a bit rate of 19,200 bits per
second. The number of bits (n) received through Port pin P30 for each bit transmitted is expressed by:
n = 19,200/b
where b = transmission bit rate. For example, if the
transmission bit rate were 1200 bits per second, each incoming bit would appear to the receiving serial line as 19,200/1200 or 16 bits.
The following example is capable of distinguishing between the bit rates shown in Table 13-6 and assumes an input clock frequency of 7.3728 MHz, a TO prescaler of 3, XTAU2 mode, and serial 1/0 enabled with parity disabled. This example requires that a character with its low order bit = 1(such as a carriage return) be sentto the serial channel. The start bit of this character can be measured by counting the number of zero bits collected before the low order 1 bit. The number of zero bits actually collected into data bits by the serial channel is less than n (as given in the above equation), due to the detection of start and stop bits. Figure 13-4 illustrates the collection (at 19,200 bits per second) of a zero bit transmitted to the Z8 at 1,200 bits per second. Notice that only 13 of the 16 zero bits received are collected as data bits.
13-32
ftl211.Jl6
Bit Rate
19200 9600 4800 2400 1200 600 300
150
D' MlcRocoNTRoLLERS
Table 13-6. Inputs to the Automatic Bit Rate Detection Algorithm
Number of Bits Received Per Bit Transmitted
1 2 4 8 16 32 64 128
Number of Bits Collected as Data Bits
dee binary
0 00000000
1 00000001 3 00000011 7 00000111
13 00001101
25 00011001
49 00110001 97 01100001
T0 Counter dee binary
00000001 2 00000010 4 00000100
8 00001000 16 00010000 32 00100000
64 01000000 128 10000000
I... · - - - ·I 1 Bit Time at 1,200 Bits Par Second - - -...
ST= Start Bit Sp = Stop Bit On = Data Bit n Each Interval Shown = 1 Bit Time At 19,200 Bits Par Second
Figure 13-4. Collection of a Start Bit Transmitted at 19.2 KBps
13-33
ft'21Ul6
'1' MICROCONTROLLERS
Once the number of zero bits in the start bit has been collected and counted, it remains to translate this count into the appropriate TO counter value and program that value into TO (F4H). The patterns shown in the two binary columns of Table 13-6 are utilized in the algorithm for this translation.
an interrupt request after the appropriate amount of time has elapsed. Since a character is composed of eight bits plus a minimum of one stop bit following the start bit, the length of time to delay may be expressed as:
(9 x n)/b
As a final step, if incoming data is to commence immediately, it is advisable to wait until the remainder of the current 'elongated' character has been received, thus 'flushing' the serial line. This can be accomplished either via a software loop; or by programming T1 to generate
where n and bare as defined above. The following module illustrates a sample program for automatic bit rate detection.
ZBASM2.0
LOC OBJCODE
POOOO
P OOOOBF P 0001 56 FB 77 P 0004 56 FA F7 P 0007 E6 F7 40
P OOOA E6 F4 01
p OOOD E6 F5 OD
P 0010 BO EO P 0012 E6 F1 03
P001576FA08 P00186B FB P 001A 18 FO P 001C 56 FA F7 P 001F 1E P00201A05 P 0022 06 EO 08 P 0025 88 EE
P 0027 EO E1 P00297B03 P 002BOE P002C BB F9
STMT SOURCE STATEMENT
1
BIT_RATE MODULE
2
EXTERNAL
3
DELAY PROCEDURE
4
GLOBAL
5
main PROCEDURE
6
ENTRY
7
di
!Disable interrupts!
8
and IMR,#77H
!IRQ3 polled mode!
9
and IRQ,#OF7H !Clear IRQ3!
10
Id
P3M,#40H
!Enable serial 1/0!
11
Id
T0,#01H
12
Id
PRE0,#(3 SHL 2)+ 1 !bit rate= 19,200;
13
continuous count mode!
14
cir
RO
!lnit. zero byte counter!
15
Id
TMR#03H
!Load and enable TO!
16
17
!Collect input bytes by counting the number of null
18 characters received. Stop when non-zero byte received!
19 collect:
20
tm
IRQ,#OBH
!Characterreceived?!
21
jr
Z,collect
!Notyet!
22
Id
R1 ,SIO !Getthe character!
23
and IRQ,#OF7H !Clear interrupt request!
24
inc R1
!Compare too ... !
25
djnz R1 ,bitloop
!...(IN 3 bytes of code)!
26
add RO,#OBH
!UpdatecountofObits!
27
jr
collect
28 bitloop:
!Add in zero bits from low
29
end of 1st non-zero byte!
30
RR R1
31
jr
c,counLdone
32
inc RO
33
jr
bitloop
34
35
!RO has number of zero bits collected!
36
!Translate AO to the appropriate TO counter valueI
37 counLdone
!RO has count of zero bits!
13-34
't'2il.Cl6
ZB8 MICROCONTROLLERS
P 002E 1C 07 P 0030 2C 80 P 0032 90 EO
P 0034 90 EO P0036 7B 04 P 0038 EO E2 P 003A 1A F8
P 003C 29 F4
P 003E 06 0000*
P 0041 56 FA F7
p 0044
38
39
40
41
42 loop:
43
44
45
46
47
done
48
49
50
51
52
53
54
END
55
END
Id
R1,#07H
Id
R2,#80H
RL RO
RL RO
jr
c,done
RR R2
djnz r1 ,loop
Id
TO,R2
call DELAY
and IRQ,#OF7H
main bit_rate
!R2 will have TO counter value!
!Load value for detected bit rate! !Delay long enough to clear serial line of bit stream!
!Clear receive interrupt request!
II
0 ERRORS ASSEMBLY COMPLETE
30 instructions 68 bytes Execution time is variable based on transmission bit rate.
13.15.3 Port Handshake
Each of Ports 0, 1 and 2 may be programmed to function under input or output handshake control. Table 13-7 defines the port bits used for handshaking and the mode bit settings required to select handshaking. To input data under handshake control, the Z8e should read the input port when the DAV input goes Low (signifying that data is available from the attached device). To output data under handshake control, the Z8 should write the output port when the ROY input goes Low (signifying that the previously output data has been accepted by the attached device). Interrupt requests IRQO, IRQ1, and IRQ2 are generated by the falling edge of the handshake signal input to the Z8 for Port 0, Port 1, and Port 2 respectively. Port handshake operations may therefore be processed under interrupt control.
Consider a system that requires communication of eight parallel bits of data under handshake control from the Z8 to a peripheral device and that Port 2 is selected as the output port. The following assembly code illustrates the proper sequence for initializing Port 2 for output handshake.
CLR P2M !Port2moderegistera11Port2bits are outputs!
LD P3M,#20H
!Port 3 mode register enable Port 2 handshake!
LD 02H,DATA
!output first data byte; DAV2 will be cleared by the Z8 to indicate data available to the peripheral device!
Note that following the initialization of the output sequence, the software outputs the first data byte without regard to the state of the RDY2 input; theZ8will automatically hold DAV2 High until the RDY2 input is High. The peripheral device should force the Z8 RDY2 input line Low after it has latched the data in response to a Low on DAV2....I!J.e Low on RDY2 will cause the Z8 to automatically force DAV2 High until the next byte is output. Subsequent bytes should be output in response to interrupt request IRQ2 (caused by the Highto-Low transition on RDY2) in either a polled or an enabled interrupt mode.
OR 03H,#40H
!set DAV2 data not available!
13-35
'1J' MICROCONTROLLERS
Input handshake lines
Table 13·7. Port Handshake Selection
Porto
P32 =DAV P35 =ROY
Port 1
P33 =DAV P34 =ROY
Port2
P31 =DAV P36 =ROY
Output handshake lines
P32= ROY P35 =DAV
P33= ROY P34= DAV
P31 =ROY P36= DAV
To select input handshake
set bit 6 & reset bit 7 of P01 M (program high nibble as input)
set bit 3 & reset bit 4 of P01 M (program byte as input)
set bit 7 of P2M (program high bit as input)
To select output handshake To enable handshake
set bits 6, 7 of P01 M (program high nibble as output)
set bit 5 of Port 3 (P35); set bit 2 of P3M
set bit 3, 4 of P01M (program byte as output)
set bit 4 of Port 3 (P34): set bits 3, 4 of P3M
set bit 7 of P2M (program high bit as output)
set bit 6 of Port 3 (P36); set bit 5 of P3M
13-36
11 MICROCONTROLLERS
13.16 ARITHMETIC ROUTINES
This section gives examples of the arithmetic and rotate instructions for use in multiplication, division, conversion, and BCD arithmetic algorithms.
13.16.1 Binary to Hex ASCII
The following module illustrates the use of the ADD and SWAP arithmetic instructions in the conversion of a 16-bit binary number to its hexadecimal ASCII representation.
The 16-bit number is viewed as a string of four nibbles and is processed one nibble at a time from left to right, beginning with the high-order nibble of the lower memory address. 30H is added to each nibble if it is in the range Oto 9; otherwise 37H is added. In this way, OOH is converted to30H, 1Hto31H, ... OAHto41H, ... OFHto46H. Figure 135 illustrates the conversion of ARO (contents= F2BEH) to its hex ASCII equivalent; the destination buffer is pointed to by RR4.
II
Bit Register
D1
4 3
Do D7 4 3
Do
F
2 II B
E
RO
R1
D1 4 3
Do D7 4 3
Do D1 4 3
Do 07
4 3
Do
RR4-
4
I 6
I 3
2 II 4
I 2
I 4
5
Figure 13-5. Conversion of (RRO) To Hex ASCII
Z8ASM 2.99 INTERNAL RELEASE
LOC OBJ CODE STMT SOURCE STATEMENT
1
ARITH MODULE
2
GLOBAL
p 0000
3
BINASC
PROCEDURE
4
!**************************************************
5
Purpose=
To convert a 16-bit binary
6
number to Hex ASCII
7
8
Input=
RAO = 16-bit binary number.
9
RR4 = pointer to destination
10
buffer in external memory.
11
12 Output=
Resulting ASCII string (4 bytes)
13
in destination buffer.
14
RR4 incremented by 4 .
15
RO, R2, R6 destroyed.
16 **************************************************!
17
ENTRY
18
POOOO 6C 04
19
Id
R6,#04H
!nibble count!
P0002FOEO
20
again: SWAP RO
!look at next nibble!
P 0004 28 EO
21
Id
R2,RO
P 0006 56 E2 OF
22
and R2,#0FH
!isolate 4 bits!
23
!convert to ASCII R2 + #30H if RO in range O
to 9
24
else R2 + #37H (in range OA to OF)!
13-37
P 0009 06 E2 30 P OOOC A6 E2 3A POOOF7B03 P 0011 06 E2 07 p 0014 92 24 P0016AOE4
P 0018 A6 E6 03
P 0018 EB 02
P 0010 08 E1
P 001F 6A E1 P 0021 AF p 0022
0 ERRORS ASSEMBLY COMPLETE 16 instructions 34 bytes 120.5 us (average)
26
ADD R2,#30H
27
cp R2,#3AH
28
jr
ult.skip
29
ADD RS,#07H
30 skip: Ide @RR4,R2
31
incw RR4
32
33
cp R6,#03H
34
jr
ne,same_byte
35
Id
RO,R1
36 same_byte:
37
djnz R6,again
38
ret
39 END BINASC
40 END ARITH
ZS' MICROCONTROLLERS
!save ASCII in buffer! !point to next buffer position! !time for second byte?!
!no.! !2nd byte!
13.16.2 BCD Addition
The following module illustrates the use of the add with carry (ADC) and decimal adjust (DA) instructions for the addition of two unsigned BCD strings of equal length.
Within a BCD string, each nibble represents a decimal
digit (0-9). Two such digits are packed per byte with the most
significant digit in bits 7-4. Bytes within a BCD string are arranged in memory with the most significant digits stored in the lowest memory location. Figure 13-6 illustrates the representation of 5970 in a 6-digit BCD string, starting in register 33H.
Bit Register
D7
4 3
Do D1
4 3
Do D1
4 3
Do
0
I I 0
5
I I 9
7
0
%33
%34
%35
Figure 13-6. Unsigned BCD Representation
13-38
zr MICROCONTROLLERS
Z8ASM 2.0 LOC OBJ CODE
p 0000
p 0000 02 12 p 0002 02 02 P 0004 CF P 0005 00 E1 P 0007 00 EO P 0009 E3 31 p 0008 13 30 P OOOD 40 E3 P OOOF F3 03 P 0011 2A F2 P0013AF p 0014
STMT 1
2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21
22
23 24 25 26 27 28 29 30 31 32
33
34 35
36
37 38 39 40 41 42 43
SOURCE STATEMENT
ARITH MODULE
CONSTANT
BCD_SRC = R1
BCD_DST = RO
BCD_LEN = R2
GLOBAL
BCADDPROCEDURE
! **************************************************
Purpose=
To add two paced BCD strings of
equal length.
dst <- dst + src
Input=
RO= pointer to dst BCD string. R1 = pointer to src BCD string. R2 = byte count in BCD string
(digit count= (R2)*2 ).
Output=
BCD string pointed to by RO is
the sum.
Carry FLAG= 1 if overflow.
RO , R1 as on entry.
R2= 0
************************************************** !
ENTRY
add add ref add_again: dee
BCD_SRC,BCD_LEN BCD_DST,BCD_LEN
BCD_SRC
dee BCD_DST
Id ADC DA Id djnz
R3,@BCD_SRC R3,@BCD_DST R3 @BCD_DST,R3 BCD_LEN,add_again
ret
!start at least. .. ! !significant digits! !carry=O!
!point to next two srcdigits! !point to next two dstdigits! !getsrcdigits! !add dst digits! !decimal adjust! !move to dst! !loop for next digits! !all done!
END BCADD END ARITH
Ill
0 ERRORS ASSEMBLY COMPLETE 11 instructions 20bytes Execution time is a function of the number of bytes (n) in input BCD string: 20 us + 12.5(n-1) us
13-39
7J' MICROCONTROUERS
13.16.3 Multiply
The following module illustrates an efficient algorithm for the multiplication of two unsigned 8-bit values, resulting in a 16-bit product. The algorithm repetitively shifts the multiplicand right (using RRC), with the low-order bit being shifted out (into the carry flag). If a one is shifted out, the multiplier is added to the high-order byte of the partial
product. As the high-order bits of the multiplicand are vacated by the shift, the resulting partial-product bits are rotated in. Thus, the multiplicand and the low byte of the product occupy the same byte, which saves register space, code, and execution time.
Z8ASM 2.99 INTERNAL RELEASE
LOC OBJ CODE STMT SOURCE STATEMENT
1
ARITH MODULE
2
CONSTANT
3
MULTIPLIER = R1
4
PRODUCT_LO = R3
5
PRODUCT_HI = R2
6
COUNT= RO
7
GLOBAL
p 0000
8
MULT PROCEDURE
9!**************************************************
10 Purpose=
To perform an 8-bit by 8-bit unsigned
11
binary multiplication.
12
13 Input=
R1 = multiplier
14
R3 =multiplicand
15
16 Output=
RR2 = product
17
RO destroyed
18 ************************************************** !
19 ENTRY
POOOO OC 09
20
Id
COUNT,#09H
!8 BITS+ 1!
P 0002 BO E2
21
cir
PRODUCT_HI
!INIT HIGH RESULT BYTE!
P 0004 CF
22
RCF
!CARRY=O!
P0005 CO E2
23
LOOP: RRC PRODUCT_HI
P 0007 CO E3
24
RRC PRODUCT_LO
P 0009 FB 02
25
jr
NC.NEXT
p OOOB 02 21
26
ADD PRODUCT_HI.MULTIPLIER
POOODOA F6
27 NEXT: djnz COUNT.LOOP
P OOOFAF
28
ret
p 0010
29 END MULT
30
END ARITH
0 ERRORS ASS EMBLY COMPLETE 9 instructions 16 bytes 92.5 us (average)
13-40
ft'21u:&
'11 MJCROCONTROLLERS
13.16.4 Divide
The following module illustrates an efficient algorithm for the division of a 16-bit unsigned value by an 8-bit unsigned value, resulting in an 8-bit unsigned quotient. The algorithm repetitively shifts the dividend left (via RLC). If the high-order bit shifted out is a one or if the resulting highorder dividend byte is greater than or equal to the divisor,
the divisor is subtracted from the high byte of the dividend. As the low-order bits of the dividend are vacated by the shift left, the resulting partial-quotient bits are rotated in. Thus, the quotient and the low byte of the dividend occupy the same byte, which saves register space, code, and execution time.
Z8ASM2.0 LOC OBJ CODE
POOOO
POOOO OC 08 P0002A212 P 0004 BB 02 P0006 OF P 0007 AF P000810 E3 POOOA 10 E2 POOOC 7B 04 POOOEA212 P0010 BB 03 P0012 22 21 P 0014 OF P0015 OA F1
STMT SOURCE STATEMENT
1 ARITH MODULE
2 CONSTANT
3
COUNT= RO
4
DIVISOR= R1
5
DIVIDEND_HI = R2
6
DIVIDEND_LO = R3
7 GLOBAL
8 DIVIDE PROCEDURE
9 !**************************************************
10
Purpose=
To perform a 16-bit by 8-bit unsigned
11
binary division.
12
13 Input=
R1=8-bit divisor
14
RR2 = 16-bit dividend
15
16 Output=
R3 = 8-bit quotient
17
R2 = 8-bit remainder
18
Carry flag = 1 if overflow
19
= 0 if no overflow
20 **************************************************!
21
ENTRY
22
Id
COUNT,#08H
!LOOP COUNTER!
23
24
!CHECK IF RESULT WILL FIT IN 8 BITS!
25
cp DIVISOR,DIVIDEND_HI
26
jr
UGT,LOOP
!CARRY= 0 (FOR RLC)!
27
!WON'T FIT. OVERFLOW!
28
SCF
!CARRY = 1!
29
ret
30
31
LOOP !RESULT WILL FIT. GO AHEAD WITH DIVISION!
32
RLC DIVIDEND_LO
!DIVIDEND * 21
33
RLC DIVIDEND_HI
34
jr
c,subt
35
cp
DIVISOR,DIVIDEND_HI
36
jr
UGT,next
!CARRY= O!
37 subt: SUB DIVIDEND_Hl,DIVISOR
38
SCF
!TO BE SHIFTED INTO RESULT!
39 next: djnz COUNT.LOOP
!no flags affected!
40
41
!ALL DONE!
El
13-41
P 001710 E3
42
43
P 0019AF
44
P001A
45
46
0 ERRORS ASSEMBLY COMPLETE 15 instructions 26bytes 124.5 us (average)
RLC
ret END DIVIDE END ARITH
DIVIDEND_LO !CARRY= Ono overflow!
13.17 Conclusion
za· This section has focused on ways in which the micro-
computer can easily yet effectively solve various application problems. In particular, the many sample routines illustrated here should aid the user in applying the ZS to
za greater advantage. The major features of the have
been described so that the user can continue to expand
and explore the repertoire of uses for the ZS.
13-42
USER'S MANUAL
CHAPTER 14
THIRD-PARTY SUPPORT TOOLS
II
In addition to Zilog tool offerings, an extensive list of third party suppliers offer a variety of software (XASM, C Compilers, Simulators/Debuggers), hardware emulator, and OTP programmer (single and gang) products.
14.1 Third-Party Support-Emulators/ Programmers
14.2 Third-Party Support-Assemblers/C Compilers
Data 1/0 (OTP Programmer)
(800) 332-8246 2500AD Software
(719) 395-8683
EmulationTechnologies (OTP Socket Adapters)
iSystems
Logical Devices, Inc. (OTP Programmer)
Needham Electronics (OTP Programmer)
(408) 982-0660 Avocer Systems
(49)8131-25085 (800) 331-7766
ByteCraft Micro Computer Control Production Languages Corp.
(916) 924-8037 Pseudo Corp.
(800) 448-8500 {519) 888-6911 (609) 466-1751 (817) 599-8363 (503) 683-9173
Orion Instruments
(408) 747-0440
Signum Systems
{805) 371-4608
Systems General (OTP Programmer)
(408) 263-6667
14-1
Z8® Microcontroller Technical Description
nl Zilog ZS® Software
ZHo General I ormation
USER'S GUIDE
DI
asm ZS®
CROSS ASSEMBLER
Related Publications IEEE Proposal P695 Microprocessor Universal Format for Object
Modules. IEEE Micro August 1983 Vol. 3 & 4 pp. 48-66 SuperB Technical Manual, document number 03-8257-0X Universal Object Files Utilities User's Guide, document
number 03-8236-0X ZB Microcomputer Technical Manual, document number 03-3047-0X
Trademark Acknowledgements asmSB, cas, PLZ/ASM, Super8, System 8000, and ZB are trademarks of Zilog Inc.
UNIX is a trademark of AT&T Bell Laboratories VAX is a trademark of Digital Equipment Corporation
ID
Zilog does not support the software mentioned in this publication. use at own risk.
© 1985 by Zilog, Inc. All rights reserved. No part of this publica· lion may be reproduced, stored in a retrieval system, or transmit· ted, in any form or by any means, electronic. mechanical.
photocopying, recording. or otherwise, without the prior written permission of Zilog. The information contained herein is subject to change without notice. Zilog assumes no responsibliijy for the use of any circuitry other than circuitry embOdied in a Zilog product. No other circuit patent licenses are implied. All sPE!cifications (parameters) are subject to change without no· tice. The applicable Zilog test documentation will specify which parameters are tested.
1' MICROCONlllOLLERS USER's MANUAL
ASM ZS4DCROSS ASSEMBLER USER'S GUIDE TABLE OF CONTENTS
CHAPTER TITLE AND SUBSECTIONS
PAGE
CHAPTER 1: OVERVIEW
1.1 Introduction ............................................................................................................................. 1-1 1.2 Assembler Overview ............................................................................................................... 1-2 1.3 Relocation and Linking ............................................................................................................ 1-3
CHAPTER 2: ASSEMBLY LANGUAGE SYNTAX
2.1 Introduction .............................................................................................................................2-1 2.2 Symbolic Notation ...................................................................................................................2-1 2.3 Operations and Operands ......................................................................................................2-6 2.4 Comments ...............................................................................................................................2-6 2.5 Arithmetic Expressions ............................................................................................................2-7 2.6 Expressions and Operators .....................................................................................................2-7 2.7 Constants ..............................................................................................................................2-10 2.8 Location Counter ...................................................................................................................2-11
CHAPTER 3: PSEUDO-OPS
3.1 Introduction .............................................................................................................................3-1 3.2 Relocation Pseudo-Ops ..........................................................................................................3-1 3.3 Label Definition Pseudo-Ops ..................................................................................................3-3 3.4 Module and Section Pseudo-Ops .......................................................................................... 3-6 3.5 General Data Definition Operation ......................................................................................... 3-8 3.6 Conditional Assembly Pseudo-Ops ..................................................................................... 3-12 3.7 Assembler Control Pseudo-Ops ............................................................................................3-13
CHAPTER 4: MACROS
4.1 General Description ................................................................................................................4-1 4.2 MACRO or String MACRO ......................................................................................................4-2 4.3 PROC or Procedure MACRO ..................................................................................................4-3 4.4 Special MACRO Pseudo-Ops .................................................................................................4-4 4.5 Special MACRO Operators .....................................................................................................4-6
CHAPTER 5: PROGRAM INVOCATION 5.1 Assembler Command Lines and Options .............................................................................. 5-1 5.2 Listing Format .........................................................................................................................5-2 5.3 Program Termination ...............................................................................................................5-2
APPENDICES
Appendix A. Pseudo-Op Summary ............................................................................................. A-1 Appendix B. Special Symbols ..................................................................................................... B-1 Appendix C. ASCII Character Set ............................................................'................................... C-1 Appendix D. Error Messages and Explanations ......................................................................... D-1 Appendix E. Program Example ................................................................................................... E-1
U' MICAOCONTROUERS USEA's MANUAL
ii
Overview
1.1 INTRODUCTION
CHAPTER 1 OVERVIEW
Zilog's Super8/Z8 Cross-Assembler (asm58) takes a source file containing assembly language statements and translates it into a corresponding object file. It can produce a listing conta.ining the source code, object code, and comments. The assembler supports macros and conditional assembly. It is written in C and runs on the UNIX operating system. Figure 1-1 illustrates the development path of a typical program.
EDITOR
(
LISTING )
SINGLE OBJECT MODULE
ASSEMBLY SOURCE FILE
umS8 ASSEMBLER
ABSOWTEOR RELOCATABLE OBJECT MODULE
1
ABSOWTEOR RELOCATABLE OBJECT MODULE
N
MULTIPLE
OBJECT MODULES
mlink LINKER
ABSOWTEOR
RELOCATABLE OBJECT MODULE
DI
mload OOWNLOADER
DOWNLOADABLE OBJECT MODULE
Figure 1-1. asa58 Program Development Cycle
1-1
Overview 1.1 INTROOUCTION
(Continued)
1.2 ASSDELER OVERVIEW
1.2.1 Assembler
Enhancements
1.2.2 Modules
The assembler can produce relocatable and absolute object code. Object files can contain a mixture of absolute and relocatable code. Object files then can be linked with other object files and loaded into memory.
For a description of the architecture of the Supers family of microcomputers, refer to the Supers Technical Manual. for a description of the architecture of the ZS family, refer to the ZS Microcomputer Technical Manual.
The asmSB Cross-Assembler is a macro assembler, written ip C, that runs on the UNIX operating system for the DEC VAX and VMS, IBM-PC, and Zilog System 8000. The assembler produces output in a universal object code format (refer to the Universal Object Files Utilities User's Guide).
Providing more than compatibility with existing hardware and software, the asmSS assembler includes new features not available in earlier assemblers. Integer arithmetic on numbers up to SO bits long is supported, as is arbitrary integer arithmetic on external and relocatable symbols. Additional expression operators are defined, and syntax rules for expressions and operand delimiters have fewer restrictions.
The asmSB assembler increases support for constants by providing floating-point constants in addition to those numbers supported in the C language. However, floating-point arithmetic in assembly-time expressions is not supported.
A program consists of one or more separately coded and assembled modules. Modules are referred to as either source modules or object modules.
A source module is made up of assembly language statements. These statements are then translated by the asmSB assembler into an object module that can either be separately executed by the SuperB (or ZB) microprocessor, or linked with other object modules to form a complete program. The user can also control the operation of the . assembler by including assembler directives, or "pseudo-ops," in the source code. Briefly, pseudo-ops resemble opcodes in form, but not function (see Chapter 3).
Depending on the assembler directives used, addresses within an object module or program can be absolute (addresses in the source program correspond exactly to
1-2
1.3 RELOCATION AND
LINCDC
Overview
logical memory addresses) or relocatable (addresses can be assigned relative to a logical base address at a later time). Object modules should be made relocatable whenever possible. This facilitates the ability to link with other object modules and also provides the ability to load object programs anywhere in memory. Relocatable addressing also allows the creation of libraries of common! y used procedures (including math or input/output routines) that can be linked selectively into several programs as desired.
Relocation refers to the ability to bind a program module and its data to a particular memory area after. the assembly process. The output of the assembler is an object module that contains enough information to allow the linker to assign that module to a memory area. Since many modules can be loaded together to form a complete program, a need for inter-module communication arises. f'or example, one module can contain a call to a routine that was assembled as part of another module and is located in some arbitrary part of memory. Therefore, the assembler must provide information in the object module that allows the linker to link int.er-module references.
There are several major advantages to using the relocating assembler as compared to an absolute assembler:
1) Assignment of modules to memory areas can be handled by the linker rather than requiring the programmer to assign fixed absolute locations vi a the "ORG" pseudo-op; thus, modules can be relocated without requiring reassembly.
2) If errors are found in one module, only that one module needs to be reassembled and relinked with the other modules, thus increasing software productivity.
3) Programs can be structured into independent modules, coded separately and assembled, even though other modules may not yet exist.
4) Libraries of commonly used modules can be built and then linked with programs without requiring reassembly of the library module.
5) Communications between overlay segments can be achieved through methods similar to normal (non-overlay) inter-module references.
Unless otherwise specified, the output of the assembler is in relocatable form. During program execution, the instruction will be located at the memory location
1-3
DI
Overview 1.3 RELOCATION AND
LINKING (Continued)
1.3.1 Inter-Module References
1.3.2 Sections
specified by the 1inker (assigned origin plus the relative offset). Thus, a relocatable module has its first instruction located at. the memory location that is the assigned origin of the module as determined by the linker.
To achieve relocation, addresses are altered at linkage time for both inst.ructions that reference memory locations and data values that serve as pointers to memory locations. This process is transparent to the programmer.
The asmSB assembler supports two pseudo-ops (or pseudo operation codes), GLOBAL and EXTERNAL, so that instructions can refer to "names" (either data values or entry points) in other assembled modules. GLOBAL means that the listed names are defined in this module and are ava.ilable for use by other modules. EXTERNAL means that the names are used in this module, but are defined in another module where they are declared to be global. The syntax requires one or more names to follow either pseudo-op.
The GLOBAL name can be either absolute or relocatable. A portion of the object module contains a list of both the GLOBALs that are defined in the module, and the EXTERNALS that the module references. One function of the linker is to mat.ch all the EXTE.RNALs with the appropriate GLOBALs so that every instruction will reference the correct address during program execution.
A more thorough discussion of pseudo-ops is given in Chapter 3.
Programs can be divided into sections that are mapped into various areas of memory when linked or loaded for execution. A single module can contain several sections, each allocated to a different area in program or data memory. Likewise, portions of a section can be spread through several different modules and automatically combined into a single area by the linker.
Sections provide the programmer with complete control over the memory mapping of a program without requiring absolute addressing. A module can contain some relocatable sections and some absolute sect.ions, but a single section is either entirely absolute or entirely relqcatable. Section 3.4.2 describes section definition in more detail.
Assembly Language Syntax
OIAPTER Z ASSDISLY LANGUAGE SYNTAX
2.1 INTRODUCTION
The basic component of an asmSB program is the assembly language statement. An assembly language statement can be up to 128 characters in length and is terminated by an end-of-line character. A statement can include four fields:
· Statement labels · An opcode · Operands · Comments
A typical asm58 statement might look like:
LABEL1: LO R2,RS ;comment
where LABEL1 is the statement label (signified by the colon), LO is the opcode, R2 is the destination operand, RS is the source operand, and a comment is indicated by a semicolon. for compatibility with Zilog 's ZBOOO assembler, comments can begin with //, although this assembles slower.
All fields are optional; label and comment fields can start in any column; the opcode and operands cannot start in column 1. The statement can have zero or more operands, depending on the opcode selected. The following sections describe convent ions that must be observed in writing a program statement.
2.2 SYteOLIC NOTATION
Symbolic identifiers can include opcodes, pseudo-ops, special symbols, and labels. Legal identifiers can be up to 127 characters in length, and consist of one or more alphabetic characters, digits, or the characters: comma (,), dollar sign ($), question mark (?), period (.), at sign (3), or single quote mark ('). Upper and lower case letters are considered unique, and all characters are significant.
The only restriction on symbols is that they cannot start with a digit or single quote mark ( '). Since some older programs can rely on having only the first eight characters of a symbol being significant, a global variable called $'SYMLEN is provided to limit the number of significant characters in a symbol. Appendix B describes global variables in more detail.
2-1
Assembly Language Syntax
2.2.1 Labels
Any statement that is referenced by another statement must be labeled, and any statement can contain one or more labels. A label is a symbolic identifier that can represent:
· An address (up to 16 bits) · An 1/0 port · A floating-point number · Other quantities with up to 80 bits of significance.
When a label is being defined, it can start in any column when immediately followed by a colon (:). If a colon is not used, the label must start in column 1. More than one label can be defined on the same line, for example:
LABEL1: LABEL2: ··· LABELn: statement
A GLOBAL label can be declared by placing two colons after the label on the line where it is defined (e.g., LABEL 1::). An EXTERNAL label can be declared by two pound signs that immediately follow (e.g., LABEL2/UI). A t.ilde ("') as the first character of a label makes it local to a block, as defined by the .BEGIN and .END pseudo-ops.
A label definition preceded by a colon (:LABEL1) specifies that the data type of the label will be the same as the type generated by the rest of the statement. These labels can be checked across module boundaries.
Labels for registers are given special treatment. Indexing is the only val id operation. Table 2-1 lists the ZB System and Control register names. Table 2-2 lists the Super8 system register names and Table 2-3 lists the Super8 Mode and Control register names.
The names of opcodes can be used freely as labels in the same assembly language statements. The assembler can recognize when a string is being used as an opcode rather than as a label.
2-2
Assembly Language Syntax
Decimal Address
255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 127-4
3 2 1 0
Table 2-1. ZS System and Control Registers
Hexadecimal Address
Register name
FF FE
FD FC FB FA F9 F8
F7
F6 F5 F4
F3
F2 F1
FO
7F-04 03 02 01 00
Stack Pointer (bits 7-0) Stack Pointer (bits 15-8)
Register Pointer Program Control Flags
Interrupt Mask Register
Interrupt Request Register Interrupt Priority Register
Ports 0-1 Mode Port 3 Mode Port 2 Mode
TO Prescaler Timer/Counter T1 Prescaler Timer/Counter Timer Mode Serial 1/0
General-purpose registers Port 3 Port 2
Port 1 Port O
Identifier
SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P2M PREO
TO
PRE1 T1 TMR SIO
P3 P2 P1 PO
Ill
Decimal Address
222 221 220 219 218 217 216 215 214 213 212 211 210 209 208
Table 2-Z. Super8 System Registers
Hexadec.illal Address
Register name
DE
System mode
DD
Interrupt Mask Register
or:
Interrupt Request Register
DB
Instruction Pointer (Bits 7-0)
DA
Instruction Pointer (Bits 15-8)
D9
Stack Pointer (Bits 7-0)
DB
Stack Pointer (Bits 15-8)
07
Register Pointer 1
06
Register Pointer 0
05
Program Control flags
D4
Port 4
03
Port 3
02
Port 2
01
Port 1
DO
Port 0
Identifier
SYM IMR IRQ IPL IPH SPL SPH RP1 RPO Flags P4 P3 P2 P1 PO
Assembly Language Syntax
Deci·al Address
255
254
253 252 251
250
249
248
247 246 245 244 241
240
Z39 237 236 235 229
228
227
226
225
224
Table Z-3. SuperB Mode and Control Registers
Hexadecimal Bank
Address
Number Register Name
FF
0
Interrupt Priority
1
Wake-up Mask
FE
0
External Memory Timing
1
Wake-Up Match
FD
0
Port 2/38 Interrupt Pending
FC
0
Port Z/3A Interrupt Pending
PS
0
Port Z/30 Mode
1
UART Mode B
FA
0
Port 2/3C Mode
1
UART Mode A
F9
0
Port 2/38 Mode
1
UART Baud Generator (bits 7-0)
F8
0
Port 2/3A Mode
1
UART Baud Generator (bits 15-8)
F7
0
Port 4 Open Drain
F6
0
P·ort 4 Direction
F5
0
Handshake 1 Control
F4
0
Handshake 0 Control
F1
0
Port Mode
1
OMA Count (bi ts 7-0)
FO
0
Port D Mode
1
OMA Count (bits 15-8)
EF
0
UART Data
ED
0
UART Interrupt Enable
EC
0
UART Receive Control
EB
0
UART Transmit Control
E5
0
CTR 1 Capture (bits 7-0)
1
CTR 1 Time Constant (bits 7-0)
E4
0
CTR 1 Capture (bits 15-8)
1
CTR 1 Time Constant (bits 15-8)
E3
0
CTR 0 Capture (bits 7-0)
1
CTR 0 Time Constant (bits 7-0)
E2
0
CTR 0 Capture (bits 15-8)
1
CTR 0 Time Constant (bits 15-8)
E1
0
CTR 1 Control
1
CTR 1 Mode
EO
0
CTR 0 Cont rol
1
CTR 0 Mode
Identifier
IPR WUMSK EMT WUMCH P2BIP P2AIP
P2DM LIMB P2CM UMA PZBM UBGL P2AM UBGH P40D P4D H1C HOC PM DCL POM OCH UIO UIE URC UTC C1CL C1TCL C1CH C1TCH COCL COT CL COCH COT CH C1CT C1M COCT COM
?-4
Assembly Language Syntax
Z.Z.2 Condition Codes
Condition codes are recognized only as operands of instructions that take them. for example, the statement
JR Z, Label
causes Z to be treat.ed as the condition code for zero.
The condition codes and flag settings they represent are listed in Table 2-4.
Binary
0000 1000 0111 1111 0110 1110 1101 0101 0100 1100 0110 1110 1001 0001 1010 0010 1111 0111 1011 0011
Table Z-4. ZS and Supers Condition Codes
ttr-Jnic Meaning
Flags Set
F
Always False
T
Always True
c
Carry
C=1
NC
No Carry
C=O
z
Zero
Z=1
NZ
Not Zero
Z:O
PL
Plus
5:0
MI
Minus
5:1
ov
Overflow
V=1
NOV
No Overflow
V:O
EQ
Equal
Z=1
NE
Not Equal
Z=O
GE
Greater than or equal
(5 XOR V) = 0
LT
Less than
GT
Greater than
(5 XOR V) = 1 (Z OR (5 XOR V) ) = 0
LE
Less than or equal
( Z OR (5 XOR V)) = 1
UGE
Unsigned greater than or equal C=O
ULT
Unsigned less than
C=1
UGT
Unsigned greater than
(C = 0 AND Z = 0) =
ULE
Unsigned less than or equal
(CORZ)=1
2-S
Assembly language Syntax
2.3 OPERATIONS ANO OPERANDS
An operation is a mnemonic that represents an instruction.
The assembler also supports a restricted mode that
handles only za instructions.
An operation in a program statement can be followed by one or more operands, which are general expressions separated by spaces or commas. Macro parameter lists are the only exceptions since they require parameters to be separated by commas only. Commas do not have the same effect as spaces because two commas in a row denote an omitted operand. A carriage return always serves as a st atement de1imi t er. No more than one statement can be on single line, and a single statement cannot span more than one line.
An operand in a program statement can be:
· Data to be processed (immediate data)
· The designation of a location from which data is to be taken (source address)
· The designation of a location where data is to be placed (destination address)
· The address of a program location to which program control is to be passed
· A condition code, used to direct program flow
Although there are a number of val id combinations of operands, there is one basic convention to remember: the destination operand always precedes the source operand(s). Refer to the specific instructions in the appropriate (Super8 or ZS) Technical Manual for valid operand combinations, and for information about addressing modes.
2.4 CIH4ENTS
A comment is any string of characters following a semicolon (;)or two slashes (//) in a statement line. Comments have no functional effect on the assembly of a program--they are used only for documentation.
Comments can start in any column of a line, and a statement can consist of only a comment. Comments terminate at the end of the line.
2-6
2.5 ARITt14ETIC EXPRESSIONS
2.6 EXPRESSIONS
AN> OPERATORS
Assembly language Syntax
The asmS8 assembler has a rich set of operators and
expressions to handle arithmetic operations. This section first deals with specific formats for arithmetic statements, then follows with a discussion of constants and special symbols.
Arithmetic expressions can be as long as 80 bits, and are examined from left to right. Precedence (order of evaluation) is as follows:
· Operators and operands are accunulated. As soon as an operator is found that has a precedence level greater than or equal to' the last operator encountered, all lower-precedence operations up to the new operator are performed.
· first prefix operations are performed, from right to left (inside out}, then postfix and infix operations are performed from left to right.
· Operands (labels and subexpressions in parentheses) are considered to be of precedence level O.
The operators and their precedence {order of evaluation) are given in Table 2-5. The character "-" after the precedence means that the operation is not present in the ZS assembler. The last column gives the PLZ/ASM equivalent, if there is one.
DI
2-7
Assembly Language Syntax
Table 2-5. Operations and Precedence
Operator
function
Precedence PLZ/ASM
operand
label
0
constant
0
...constant
( )
Grouping
0
prefix
~
Register indirect
Declare local symbol
postfix
ffil
Declare external
label
( ... )
~
prefix
"HB
High byte
2-
"LB
Low byte
2-
"HW
High word
2-
"LW
Low word
2-
+
Unary plus
2
+
Unary minus
2
AC
1 's complement
2
LNOT
"B
Binary-coded decimal 2
A BYTE
Byte (8 bit)
2-
/\WORD
Word (16 bit)
2-
/\LONG
Long (32 bit )
2-
/\QUAD
Quad (64 bit)
2-
/\QUINT
Quint (80 bit)
2-
/\ ADDR
Address (16 bit)
2-
/\REV
Byte reverse
2-
"FWD
Forward reference
Z-
/\EXT
External reference
2-
**
*
I /\MOD
A (
A>
infix
Exponentiation
Multiplication Division Modulo Shift right Shift left
3-
4
*
4
I
4-
MOD
4
SHL
4
SHR
2-8
Assembly Language Syntax
Table 2-5. Operations and Precedeuce (Continued)
Operator
runtlion
Precedence PLZ/ASM
+
ACAT
Addition
5
+
Subtraction
5
String concatenation 5-
,"S or A&
.....
Bitwise AND Bitwise OR
6
LAND
7
LOR
AX
Bitwise exclusive OR 7
LXOR
=
> < >= <=
AUGT "ULT
<>
"SEQ
"SNE
Equal
B-
Greater than
B-
less than
8-
Greater than or equal B-
less than or equal
8-
Unsigned >
8-
Unsigned <
8-
Not equal
8-
Strings equal
8-
Strings not equal
8-
prefi'x
Not-zero
9-
infix
&&
Logical AND
9-
II
Logical OR
10-
prefix
I
Immediate operand
11
postfix
adr[ ··· ]
Indexing
adr( ··· )
Indexing
11
11-
11
a()
Arithmetic is NOT DEFINED on floating-point values.
The result of a test is zero if false, and all ones if true. For purposes of conditional assembly and logical operations, non-zero is considered to be TRUE.
Parentheses can be used for grouping as well as to alter the predecedence of evaluation.
Indexing (parentheses or square brackets) can be applied to st rings to extract a particular character, or to addresses or offsets to denote indexed addressing.
2-9
l!I
Assembly Language Syntax
The type operators (like ./\BYTE) can be used to tell
the assembler that a forward or external reference will fit in a given size.
The Af'WD and "EXT operations return 1 if the value of
their operand they otherwise
is return
fao.rward-referenced
or
external;
There are no restrictions on the relocation modes of integer operands, since the linker can support arbitrary integer arithmetic on relocatable and
external symbols. However, operations on strings cannot be passed to the linker.
Some expression operators consist of multiple characters. There are three main forms, as shown in Table 2-6.
Form
?? "? "'x id
Ex·ple
<= "<
"FS
Table 2-6. Expression Operators
Description
Two punctuation characters """ plus single punctuation character """ plus any number of letters An identifier
No identifiers are used as expression operators in the assembler as supplied. However, the user can define them to achieve compatibility with PLZ/ASM and other assemblers.
2.7 CONSTANTS
A constant value is one that doesn't change throughout the program, Constants can be expressed as numbers
(integer and floating-point), character sequences, or as symbolic names representing a constant value.
Constants supported by the assembler include integers, floating-point numbers, characters, and character strings.
Integers start with a digit (leading zero is sufficient) and can contain a base indicator:
B D, E or e H or X 0 or Q
Binary Decimal Hexadecimal Octal
2-10
Assembly Language Syntax
This is an extension that was made to allow C-style constants. Base indicators and hexadecimal digits can be in any mixture of upper and lower case. The default value is decimal.
In addition, the PLZ base-tag convention is supported:
!'.I !'G(B) !'.1(2)
Hexadecimal Octal Binary
Floating-point nuntiers start with a digit. and contain a decimal point. They can optionally contain the letter E or e followed by an optional sign and an exponent.
Floating-point numbers are always in base 10.
Characters and character strings are enclosed in single
or double quotes. If an escape character is defined, C-type escape sequences are permitted. The escape character is the value of the special symbol $'STRESC. The characters permitted after the escape character and
their meanings are noted in Table 2-7.
Permitted Characters
q n r f t b
II
\ %dd ddd
Table 2-7. Escape Characters
Meaning
The string's quote character Newline (line feed) Carri age return Form feed Tab Backspace Single quote Double quote Backslash (2 hex digits)--arbitrary character (1-3 octal digits)--arbitrary character
Cll
2.8 LOCATION llJUNTER
The number base of the digits form of escape is given by $'SBASE (default 8).
The symbols ($) or (.) refer to the current value of the location counter (corresponding to the address where the first byte generated by the statement is loaded). Either one of these symbols can be used as an operand in any arithmetic expression (but their use does not imply the use of PC-relative addressing). The arithmetic expression is computed at assembly or link time.
2-11
Assembly Language Pseudo-Ops
3.1 INTRODUCTION
J. Z .RELOCATION PSEtllO-DPS
DIAPTER J
PSElllO-<FS
The asmSB assembler permits the use of pseudo-ops (pseudo operation codes}. These pseudo-ops do not cause the assembler to generate object code, but rather specify actions to be taken by the assembler. Pseudoops use the same line format as standard instructions (label, opcode, operands, comments). Pseudo-ops can
begin in any column except column 1. The pseudo-ops permitted by the asmSB assembler are grouped by function and are described in the following sections. Table 3-1 lists the pseudo-op abbreviations and their meanings.
Table }-1. Pseudo-Op Description Abbreviations
Abbreviations
Meaning
n
Numeric expression
s
String
sn
String or numeric expression
d
Decimal digit
p
Actual parameter (see note 1)
f
Formal parameter (see note Z)
1
Optional label, more than one
Permitted
11
Required label, one only
?
Optional
Notes for Table }-1:
1. An actual parameter is a string enclosed by macro quotes (normally {··· ) } or any sequence of characters delimited by a conna, space (if $'BSEP is set}, end-of-line, or semicolon. (Refer to $'MACBEG and $'MACENO in section 4.Z.Z}.
2. A formal parameter is either a label or an actual parameter that does not start with a character that can denote a label.
The following pseudo-ops are used to specify the relocation of code within memory.
3-1
Assembly Language Pseudo-Ops
3.2.1 Origin
General Form:
l .ORG n
Description:
The .ORG pseudo-op sets the location counter to the value of the expression n. In specifying where the object code is located, the location counter serves the same function for the assembler as the Program Counter does for the CPU.
The location counter is set to the value of the expres-
sion, so that the next machine instruction or data item will be located at the specified address. The expression must not contain any forward references, but can
be relocatable. The location counter is initially set to zero, so if no .ORG statement precedes the first
instruction or data byte in a section, that byte will be assembled at location zero (relative to .the start of the section). Any label that is present will be assigned the same value as the expression. A module can contain any number of .ORG statements.
The mode of the expression in an .ORG pseudo-op cannot
be external and depends on the relocatability of the section. If a section is absolute, the .ORG pseudo-op serves to assign an absolute address to both the loca-
tion counter and the label. In addition, any .ORG statement wi 11 also set the starting address of an absolute sect.ion when it immed.iately follows the
.SECTION statement.
In a relocatable section, the expression will be treated as any offset relative to the origin of the module. Thus the label on an .ORG statement in a relocatable module will have a relocatable mode. for example, the effect of the statement
Label Opcode Operand
LAB: .ORG
100
within a relocatable section would be to set the loca-
tion counter to the beginning of the section plus 100, assign the label LAB the value 100, and make that label relocatable. A simply relocatable expression in
an .ORG can be used to change to another section.
Relocatable sections do not generally contain .ORG statements, since the pseudo-op is useful only to reserve space within the module (in a manner similar to the .DErS pseudo-op).
3-2
Assembly Language Pseudo-Ops
Example:
START1: .ORG %10 ;Start section 1 at the hex ;address 10
J.2.2 Phase
General Form:
.PHASE n
Description:
The .PHASE pseudo-op assembles the code that follows to execute starting at address n. Labels will be defined as if an origin pseudo-op ( .ORG) had been issued, but . the address into that code is not affected. This pseudo-op is provided for pieces of code.that are going to be moved (for example, from ROM to RAM) before they are executed.
Example:
.PHASE 500
J.2.J Dephase
General rom: .DEPHASE Description: The .DEPHASE pseudo-op terminates the effect of a preceding .PHASE pseudo-op. Exaaple: .DEPHASE
J.J LABEL DEFINITION PSEl.DJ-OPS
Labels on instruct ions are automatically assigned the current value of the location counter. The pseudo-ops .EQU and .SET can be used to assign arbitrary values to symbols. To facilitate inter-module conmunication, certain symbols can be declared to be either .GLOBAL or .EXTERNAL to a particular module. .EQU and .SET require that the expression have no forward references (it can contain previously declared external symbols).
III
3-3
Assembly Language Pseudo-Ops
l.3.1 E"'9ate
General For11:
11 .EQU n
11 = n
Description:
The .EQU pseudo-op assigns the value of the expression n to the symbol in the label field 11. The label cannot be redefined in . this source program. The expression can include a register or other addl'essing mode.
Using symbolic names for constant values in place of numbers enhances the l'eadability of a program and tends to make the code self-documenting. For instance, the symbol 81.f'LEN is a more descriptive name for a value than just the number 72. Furthermore, if a value that is used throughout a program needs to be changed, the .EQU statement can simply be modified l'ather than finding all occurrences of the numbel' 72.
Example:
TWO .EQU 2 ;the symbol TWO now has ;a value of 2
l.l.2 Set Re-definable General For·:
Label 11 .SET n
Description:
This pseudo-op assigns the value of the expression n to the symbol in the label field 11. The label assignment can be changed using a subsequent .SET pseudo-op. The .SET pseudo-op is identical to the .EQU pseudo-op except that the assigned label can appear in multiple .SET pseudo-ops in the same program.
In general, use the .EQU for symbol definition since the assembler will generate error messages for multiply-defined symbols. This can indicate spelling errors or some Qther oversight by the user. .SET should be reserved for special cases where the same symbol is re-used (e.g., in conjunction with the assembly of macros) ·
·EQU and .SET require that the expl'ession have no forward references (it can have external symbols provided they have been declared previously).
3-4
Assembly Language Pseudo-Ops
Example:
COND1 .SET COND1 .SET
150 COND1 + 100
;set initial value to 150 ;increment value by 100
J.3.3 Define
General rorm:
Arbitrary Synbol
11 .DEr 1
Description:
This pseudo-op defines the label 11 as an exact synonym for the operand symbol 1. Neither the label nor the operand needs to be an identifier; they may be punctuation characters such as + · If the label is non-alphabetic, it must be preceded by a colon.
Exa111ple:
AND .DEF "&
STORE .DEF LD
: I .DEF "I
J.3.4 Global
General r orm:
.GLOBAL 111, ··· lln
Description:
These pseudo-ops specify that each of their operands are symbols that are defined in the current module and that the name and value of each operand is made available t.o other modules that contain an .EXTERN declaration for any symbol. There can be one or more names separated by commas (or no names at all) · ·GLOBAL pseudo-ops can occur anywhere within the source text ·
DI
J.3.5 External
·GLOBAL ENTRYA, EXITA, ENTRYB, EXITS
General rorm:
.EXTERN 111, ··· lln
Description:
This pseudo-op specifies that each of the operands are symbols that are defined in some other module, but are referenced in the current module. The syntax is the same as · GLOBl\L.
3-5
Assembly Language Pseudo-Ops
J.J.5 External
(Continued)
.EXTERN pseudo-ops can occur anywhere within the source text. The .EXTERN pseudo-op assigns each name an external mode, which allows the name to be used in arbitrary expressions elsewhere in the module, subject to the rules for external expressions. If an .EXTERN and a .GLOBAL definition for the same label appear in the same module, the .GLOBAL pseudo-op will take precedence.
An external symbol can .be assigned a value using either a .SET or .EQU pseudo-op. An. assigned value wil 1 be the default value of a symbol if it is not resolved when the object module is linked.
Example:
.EXTERN ENTRYA, EXITA, ENTRYB, EXITS
J.4 tlDJl..E AND SECTION
PSEll>O-OPS
The following pseudo-ops are used to name the object module, and to define speci fie areas of source code that can be relocated separately.
J.4.1 Module
Definition
General Form:
.MODULE p p?
Description:
This pseudo-op defines the name of the module. If given, the second parameter becomes the target name in the object module. Otherwise, the target name will be "Z8" or "ZS8". The target name is a universal object file format field name for use by other programs such as a loader (see the Universal Object File Utilities User's Guide).
There can be only one .MODULE statement in a module. If no .MODULE statement. is given, the module takes the name of the source file with its extensi9n (.s) deleted.
Ex1111ple:
.MODULE Main ;Define main module
J.4.2 Section
Definition
General fot'll:
l .SECTION 11, ··· ln 1 .PSEC 11, ··· ln
3-6
Assembly Language Pseudo-Ops
Description:
These pseudo-ops start a section. The first parameter is the name of the section, and can be null when terminated by a comma. Any other parameters are the universal object file attributes of the section (see the Universal Object Files Utilities User's Guide). When given, a statement label is defined as a pseudo-op that will direct assembly output to that section. Assembly can also be directed to the section by giving another .SECTION command with the same section name.
The following section changing operations are predefined:
Name
.DATA .CODE .BSS .ABS .CSEC
Meaning
Data section Code section BSS section Absolute section Common section
All of these direct· assembly to a section with the same name and appropriate attributes. The default section is a nameless and relocatable section; to return to the
default section, use a .SECTION command with no parameters.
The following operations enclose blocks of local symbols:
Nme
.BEGIN
{
.END }
Meaning
Begin local symbol block Begin local syll'bol block End local symbol block End local syll'bol block
Local symbols are defined wit~ a tilde character '!-...." at the beginning. .BEGIN and { are synonymous, as are
.END and I· Furthermore, blocks can be nested.
Example:
.BEGIN
L1:
.REG IN
L1:
.END .END
3-7
ID
Assembly Language Pseudo-Ops
3.4.2 Section
Definition (Continued )
Note that a .END without a matching .BEGIN will mar.-k the end of the source program (see section 3.7.1).
3.5 GENERAL DATA DEF"INITION OPERATION
Pseudo-ops are provided to define message, text, character string, and data size.
3.5.1 Data Definition General for11:
l .IX) sn1, ··· ,snn or
1 .IX) repeat-count(data)
Description:
This pseudo-op assembles a list of data items. Any
number of expressions or strings can be listed in a .DD
statement. Each item listed is stored in its natural length: expressions involving addresses or forward references are stored in 16-bit words, expressions with values less than 256 are stored in one 8-bit byte, and strings are stored "as is."
Strings that are not used as numbers (no arithmetic operators are applied to them) are not affected by special symbols $'STRLEN and $'STRORD. Operators like .BYTE can be used· to force an expression to an appropriate length.
Ex·ple:
DATA: .IX) ZED+100 .IX) "This is a string"
3.5.2 Sized Data Definition
General f oN:
I .BYTE n1, ··· ,nn l .WORD n1, .·· ,nn l .LONG n1, ··· , nn l .QUAD n1, ··· , nn I .QUINT n1, ··· ,nn l .EXTEND n1, ··· , nn
Description:
These pseudo-ops define data of a specified size. Any number of expressions can be listed provided each fits within the specified data size. These pseudo-ops take each operand and generate object code of the size specified, locating the most significant byte at t.he
3-8
l.5.3 Define ASCII String
l.5.4 .Define ASCII String with Length
3.5.5 Define ASCII String with Flagged Last Character
Assembly Language Pseudo-Ops
current value of the location counter, and the next most significant byte at the next higher location.
The mode of the expression can be either absolute,
relocatable, or external. If present, a label will be assigned the address of the first data item. String arguments are alw.ays subject to the processing specified by $'SnLEN and $ 1SnORD (i.e., converted to numbers).
Exa11ple:
WORDS: .· WORD 512,ABLE
General f or11:
1 .ASCII sn1, ··· ,snn
Description:
This pseudo-op defines message strings or byte data. A parameter can be either an expression or a string. Any
number of parameters can be 1isted. An expression must fit into a single byte area; strings are stored completely.
Exa11ples:
label Opcode
Operand
MSG: .ASCII
'HELLO THERE', x+1
General form:
.ASCIL s1, ··· ,sn
Description:
This pseudo-op defines strings, with each string preceded by a byte containing its length. Parameters can also be expressions, each of which is also stored with a byte ·containing its length.
Exa11ple:
TXT: .·ASCIL 'OPEN I, 'CLOSE I
General for11:
l .ASCIC s1, ··· ,sn
This pseudo-op defines character strings. The high-order bit of the last character of each string is set to one (1); the high-order bi ts of all other characters in the string are set to zero (0).
3-9
ID
Assembly Language Pseudo-Ops
l.l.5
Define ASCII String with
Flagged Last Character (Continued)
Example: CHARS: .ASCIC 'ABCD','EfGH'
l.5.6 Define Null-
General Fol'll:
Terminated ASCII
Strings
1 .ASCIZ s1, ··· ,sn
·Description:
This pseudo-op defines character strings with an additional zero (null) byte at the end of each string.
Example:
label: ASCIZ '51',52
l.5.7 Reserve Space
General Fol'll:
1 .BLKB n 1 .BLKW n
l .BLKL n 1 .BLKQ n l .BLKX n
Reserve a block of bytes Reserve a block of words Reserve a block of longwords Reserve a blo~k of quadwords Reserve a block of extended words
Description:
These pseudo-ops reserve space in differing word
lengths. The operand n specifies the number of words to be reserved for data storage starting at the current
value of the location counter. Except for .BLKB, these pseudo-ops are aligned on word boundaries. When present, a label will be assigned the address of the
first byte reserved.
The expression can evaluate to any quantity; however,
the mode must be absolute and not have forward references. Any symbol appearing in the expression must have been defined before the assembler encounters
the expression.
Example:
label: .BLKW 5
J.5.8 General ·Reserve General Fol'll: Block l .BLOCK n, n?
}-10
j.5.9 Alignment
j.5.10 Even or Odd Aligraent
Assembly Language Pseudo-Ops
Description:
This pseudo-op reserves n bytes of space in memory. One operand (n) specifies the number of bytes to be reserved for data storage starting at the current value of the location counter. When provided, the second operand is the alignment boundary for the block. Any label will be assigned the address of the first reserved byte.
The expression can evaluate to any quantity, but the mode must be absolute and not have forward references. Any symbol appearing jn the expression must be defined before the assembler encounters the expression.
This pseudo-op reserves storage by incrementing the location counter by the value of the first expression. Since no object code is generated into the storage area, the contents of storage during initial program execution are unpredictable.
Example:
STORE: .BLOCK 512
General Form:
.ALIGN n?
Description:
This pseudo-op aligns the next item on a multiple of n bytes. If the next statement is a .SECTION pseudo-op, the start of the section is aligned. If the parameter n is omitted, a word alignment default value of 2 is assumed,
Exaaple:
FORMAT: .ALIGN 4
DI
General Form:
.EVEN
.ooo
Description:
These pseudo-ops align the next item on an even or odd boundary.
3-11
Assembly Language Pseudo-Ops
3.6· CDNDITIOllAL
ASSEtllLY PSEll>O-OPS
Conditional assembly permits the programmer to inhibit or enable the assembly of defined portions of the source code depending on the presence of a predetermined condition.
General Fora:
· Start Conditional Block .Ir n
· Separate True and False Conditional Blocks .ELSE
· End Conditional Block .END IF
Description:
.IF defines the start of the conditional code block and tests for the true (non-zero) or false (zero) state of the expression n. .ELSE separates the code that is assembled if the expression is true from the code that is assembled if the condition is false (.ELSE is optional). .ENDIF defines the end of the conditional code block. Conditional blocks can be nested up to 80 deep.
The mode of the expression can be either relocatable or absolute. Forward or external expressions generate a warning, and are always considered to be true.
Notice that the definition of symbols within a conditional assembly block can be inhibited, and thus references to these symbols elsewhere in the module can cause undefined symbol errors. In particular, the .label on an .ELSE pseudo-op is part of the true block, and will not be defined if the assembly is inhibited on that portion of the program.
Conditional assembly is particularly useful when a program needs to contain similar code sequences for slightly different applications. Rather than generating a multitude of p{ograms to handle these situations, the ·application-dependent sections of code can be enclosed by the conditional pseudo-ops within a single program. Thus, the user generates different object modules from subsequent assemblies of the same source by changing the values of several symbols used to control the conditional assembly.
Another common use of conditional assembly is in conjunction with macros to control generation of code dependent on the value of parameters (see Chapter 4).
Assembly language Pseudo-Ops
Example: IF FLAG
.ELSE
.END IF
;assembled if FLAG non-zero ;assembled if FLAG equals zero
J. 7 ASSEMBLER CONTROL
PSEtllO-OPS
Pseudo-ops are provided to: control the format of printed listings, control the information presented on the listings, control the printing of errors or warning messages, and to establish the compatibility mode ·of the assembler.
J. 7.1 End Program
General for11:
1 .END n?
Description:
This pseudo-op specifies the end of source code. Any expression is taken as the starting address of the program. The .END pseudo-op signifies the end of the source program, and thus any subsequent text w.ill be ignored and will not appear in a listing.
Any label will be assigned the current value of the location counter. Operands are ignored. If a source program does not contain an .END pseudo-op, then the end-of-file mark in the assembler command line will signify the end of the program.
Examples:
EXIT: .END ;end of module
.END START
m
J.7.2 Include
General foni:
.INCLUDE p
Description:
This pseudo-op includes the source file identified by the parameter (p) into the source stream immediately following this statement. The usual use of this statement is to include items such as files of macro definitions, lists of .EXTERNAL declarations, lists of
3-13
Assembly Language Pseudo-Ops
3.7.2 Include (Continued)
.EQU statements, or commonly used subroutines into the source stream. However, this pseudo-op can be used anywhere in a program. The file name given must follow the normal convention for specifying source file names ·
· INCLUDE pseudo-ops can be used in files specified in a preceding .INCLUDE pseudo-op. These pseudo-ops can be nested to a depth of four deep. If the · INCLUDE pseudo-op appears within a macro definition, the file wi 11 be included every time the macro is expanded · · INCLUDE pseudo-ops can be used in conditionals.
Ex·ple:
· INCLUDE FILE 1
3.7.J Page Title
General Forni: X
.TITLE p1, ··· pn
Description:
This pseudo-op causes the string specified in parameters to be printed at the top of each page of the listing.
Ex·ple:
.TITLE Program for Interest Calculation
J.7~4 Page Subtitle
General Fora:
.SUBTTL p1, ··· pn
Description:
This pseudo-op prints str.ings specified in parameters on the second line of following pages in the listing. The subtitle on the first page of the listing will be the name of the source file. An outer layer of quotes will be ignored.
Example:
.SUBTTL Created by P. Jones
3-14
Assembly Language Pseudo-Ops
3.7.5 Listing Control
General for11: · Control Listing
.LIST p · Control Warning Listing
.WLIST p · Control Conditional Listing
.CLIST p
· Control Macro Listing .MUST p
· Control Macro Object Listing .XLIST p
Description: These pseudo-ops cause an output listing file to be generated according to the pseudo-op(s) used and the parameter given. The parameters given for each of the listing control pseudo-ops can be any one of the following symbols:
ID
Value ON OFF
PUSH
POP
Meaning
Include in listing file.
Do not include in listing file.
Save current value of pseudo-op control status in appropriate variable.
Restore saved value of pseudo-op control status from appropriate variable.
The variables $'LIST, $'WLIST, $'CLIST, $'MLIST, and $'XLIST are used as 80-bit pushdown stacks to store and recover the current state of the parameter given in their respective list control pseudo-op. The parameter state value is stored in the low-order bits of the variable.
Pseudo-op .LIST with p=ON enables a listing file of the source to be generated. When P:OFF, .LIST prevents a listing file from being generated.
3-15
Assembly Language Pseudo-Ops
l.7.5 Listing Control (Continued)
Pseudo-op .WLIST with p:ON enables warning messages to be included in the listing file. When p=OfF, .WLIST
prevents warning messages from being included in the listing file.
Pseudo-op .CLIST with p:ON enables those portions of the source file that are conditionally skipped to be included in the listing file. When p=OFF, .CLIST prevents those "conditionally skipped" portions of the source file from being included in the listinq file.
Pseudo-op .MLIST with p=ON enables the expansion of macros to be included in the list.ing file. When p=Off, .MUST prevents macl'o expansions from being included in the listing file ·
. Pseudo-op .XLIST with p=ON enables the listing of binary object code to be included in the listing file. When p=OFF, .XLIST prevents these extra binary object lines from being included in the listing file.
The default value fol' all listing control listings is p:ON.
Exaaple:
.LIST ON
l.7.6 List Error
Message
l.7.7 List Warning Message
General Form:
.ERROR s
Description:
This pseudo-op causes the message given in stl'ing (s) to be generated and sent to the terminal and the listing.
Exaaple:
.ERROR 'SYNTAX ERROR'
General Foni:
.WARN s
Description:
This pseudo-op causes the warning message given in string (s) to be generated and sent to t.he st.andard output ·
·WARN 'POSSIBLE PROBLEM HERE' 3-16
Assembly Language Pseudo-Ops
3.7.8 Start New Page
General Fon
.PAGE n
Description:
This pseudo-op causes the listing to be paginated. The page size is set at the value given in n. If n is zero, the assembler will not paginate the listing. Page size is given in number of lines per page.
The default action is not to paginate the listing, since system utilities can be used for that purpose· ·PAGE with no operand simply starts a new page in the listing, and is equivalent to a line containing a form feed.
Exmple:
.PAGE 66 ;set page size to 66 lines
3.7.9 Search Library
General Fon: 1 .LIBRARY p 11, ··· ln? Description:
DI
This pseudo-op puts a directive into the object file
that instructs the linker to search a given library file (the first parameter) for the definitions of
external symbols. If labels are given in the parameter(s), the library is searched only for those external labels.
Example:
.LIBRARY clib.a Subr1, Subr2, SubrJ
.LIBRARY xyzlib
J.7.10 Object file
c~
General Forti
.OCOMMENT n? s
Description:
This pseudo-op enters the text given in string (s) into the object file listing as a comment. Any value given for n is used as the "comment level" value. Comments below a link-time settable level will appear in load maps.
Example:
.OCOMMENT J,'tables start here'
3-17
Macros
4.1 GENERAL DESCRIPTION
DfAPTER 4
MACROS
Macros provide a means for users to define their own opcodes or to redefine existing opcodes. A macro is a portion of a program invoked by its name. It begins and ends with pseudo-ops, and can contain any assembler constructs, including pseudo-ops and macros. Two types of macros can be used in asmSB programs: MACROs and PROCs.
MACROs are the familiar string substitution macros used in other assemblers. Parameter strings provided in the macro's invocation are substituted in the body of the macro. MACRO parameters must be separated by commas, and can contain blanks.
PROCs are call-by-value, procedure-type macros. The parameters provided in the invocation statement are expressions, and their values are substituted into the body of the macro. As with ordinary opcodes, PROC parameters can contain blanks either before or after operators. Likewise, commas between expressions are optional.
In general, a macro definition consists of the block of code beginning with a "start" pseudo-op and ending with an "end" pseudo-op. The statement containing the start pseudo-op requires a label. It serves as the name of the macro, and is used to invoke it. Each statement between the start and end statements is stored in the assembler's symbol table as the definition of the macro. These statements can include macro invocations and definitions. In addition, recursion is allowed.
The statements of the macro body are not assembled at definition time. As a result, they do not define labels, generate code, or cause errors until the macro is invoked. Macros must be defined before they are invoked.
A macro is invoked by using its name as an opcode at any point after the definition. Every macro definition has an implicit parameter named #$YM. This can be referenced by the user in the macro body, but should not explicitly appear in the .MACRO statement.
ID
4-1
Macros
4.1 GENERAL II:SCRIPTIDN (Continued)
At expansion time, each occurrence of 11$YM in the
definition is replaced by a string representing a 4digit hexadecimal constant. This string is constant
over a given macro expansion. However, it increases by one for each macro invocation to avoid multiple definition errors. This provides unique labels for different expansions of the same parameter.
4.2 MAcRo DR STRING MACRO
MACRO is the string substitution macro.
4.2.1 MACRO Definition_ The general form of a MACRO definition is:
11 .MACRO f1, ··· ,fn ;start MACRO pseudo-op.
(statements that form body of MACRO)
.ENDM
;end MACRO pseudo-op.
The required label serves as the name of the MACRO, to
be used on invocation. A formal parameter (f1, ··· ,fn) can be either a label or a string of any characters except blanks, commas, or semicolons. furthermore,
parameters must start with a character that cannot start a label. formal parameters that are labels are recognized in the macro body anywhere a label would be recognized (i.e., labels or opcodes). Parameters that are not labels are recognized anywhere (e.g., within labels, strings, or comments).
Parameters are scanned left .to right for a match, so the user is cautioned not to use parameter names that are prefix substrings of later parameter names. formal parameters are not entered in the symbol table.
MACROs can contain any statements including MACRO definitions and invocations, other assembler directives, and conditional assembly. The pseudo-ops .MACRO and .ENDM specify the beginning and end of a MACRO, respectively.
4.2.2 MACRO Special Symbols
The following special symbols are defined for use with MACROs.
They can be reassigned using .SET pseudo-ops, and can be used as operands anywhere a label could be used.
$'MACEVAL
'%'
Used to replace an expression, used as a macro parameter, with its value.
4-2
Macros
$'MACQUOTE
'!'
Used to include the followjng character in a macro parameter, despite any special meaning it may have.
$'MACBEG
·I'
$'MACEND
')·
Beginning and ending macro parameter delimiters. If different, they must be properly nested, or they could cause an escape with $'MACQUOTE.
4.2.3
MACRO Invocation and Expansion
A MACRO is invoked when its name is used as the opcode. The rest of the line is made up of "actual
parameters"--strings of characters separated by commas, possibly enclosed jn quotes (normally { ··· )) · Quoted parameters can include commas as well.
The actual parameters on the invoking line replace the corresponding formal parameters from the defining line
wherever they occur in the body of the macro. If
legal, a formal parameter is replaced wherever it occurs as an identifier. If a formal parameter is not a legal identifier, it is matched as a string and is replaced wherever it occurs. The statement is assembled after these substitutions, and the resultant
code placed in the program in place of the invoking statement.
[II
4.2.4 MACRO Example
Assuming that the label UPDATE has already been defined, the .MACRO invocation
START UPDATE 46,99,current
substitutes the actual parameter strings 46, 99, and "current" for the first, second, and third formal parameters within the body of the MACRO named UPDATE.
4.3 PROC OR PROCEDURE MACRO
The procedure (or .PROC) macro is a call-by-value macro. The major difference between a .MACRO and a .PROC is that the parameters of the procedure-type macro are expressions that are evaluated before the .PROC is expanded.
4.3.1 PROC Definition
The general form of a PRDC definition is:
11 .PROC 11, ··· ,ln ;start PROC pseudo-op
(statements that form body of PROC)
.ENDP
;end PRDC pseudo-op
4-3
Macros
4.3.1 PROC Definition (Continued)
The required label is the name of the .PROC and is used
to invoke it. The pseudo-ops .PROC and .ENDP specify the beginning and end of a PROC-type macro. The formal parameters are labels that are recognized only when
they are used in expressions or as statement labels. PROCs can contain any statements including macro definitions and invocations, assembler commands, and conditional assembly.
4.3.Z PROC Invocation and Expansion
When a PROC is invoked, the expression parameters are evaluated and substituted into the body of the PROC as values. Then the PROC is assembled normally and its code is inserted into the program in place of the invocation statement.
4.3.3 PRDC Exa11ple
For example, assume the following PROC definition:
ESTIMATE .PROC total,average
(body of PROC)
.ENDP
Using this invocation:
ESTIMATE sum+12,sum+12/num
would substitute the value of sum+12 for the formal parameter "total", and the value of sum+12/num for "average" in the ESTIMATE PROC. These values would then be used by the assembler in assembling the PROC in the program stream.
4.4 SPECIAL MACRO PSElllO-OPS
Several special pseudo-ops are provided for use within MACROs. These pseudo-ops can stop macro expansions, define labels for each macro ir:ivocation, or provide looping capabilities.
4.4.1 Exit Macro
General For·:
.EXITM n?
Description:
This pseudo-op stops the expansion of a macro. It can be used in all forms of a macro (MACRO or PROC) to force an early termination of the MACRO's expansion. The exit can be made on a conditional basis.
4-4
4.4. 2 Define Local Symbols
4.4.3 Repeat
Macros
General Form:
.LOCAL 11, ··· ,ln
Description:
This pseudo-op defines local symbols within a macro. Each symbol given in the list with this pseudo-op is replaced in the expansion of the MACRO by the symbol " ·· XXXX" where XXXX represents a hexadecimal number unique for each local symbol in each invocation of the macro. When used, the · LOCAL pseudo-op must immediately follow the defining MACRO or PROC statement.
Example:
POWER: ·MACRO x .LOCAL two,three ;two and three will be assigned ;a unique symbol for each ;invocation of the macro.
General form: .REPT n
III
.ENDM
Description:
The block of statements between .REPT and .ENDM is repeated n times. The value of n must be absolute and not include forward references.
Ex&11ple:
.REPT 4
.ENDM
4.4.4 Repeat On Para.eter List
General Form: · IRP f, s
.ENDM
4-5
Macros
4.4.4 Repeat On Par~er List (Continued)
Description:
The quotes are stripped from the string, and the block of statements between .IRP and .ENDM is repeated, with each parameter in the string s replacing the formal parameter f in the expansion of the contained statement.
Exanple:
.IRP X, "4,8" ;first 4, then 8, is substituted for ;each occurrence of X from here to the ;end of the macro ·
· ENDM
4.4.5 Repeat On
General Form:
Character String
· IRPC f ,s
4.5 SPECIAL MACRO OPERATORS
4.5.1 ·s· Operator
.ENDM
Description:
The block of statements between · IRPC and .ENDM is repeated, with each character in s replacing the formal parameter f in the contained statements.
Exmple:
.IRPC X, "1234567"
;the characters 1 ;through 7 are substituted ;for the seven iterations of this ;macro.
ENDM
The following sections discuss operators and symbols that are useful mainly within macro definitions· or invocations. These symbols are %, ! , { ) , "DEF, and "NUL. Note that the single-character operators can be redefined by changing the value of the corresponding special symbols.
The symbol % in front of a label in a macro parameter causes the numeric value of the expression to be
converted to a decimal ASCII string and incorporated into the parameter. The symbol % will be recognized
within a symbol to construct new symbols. The label's value must be absolute, and may not contain a forward reference.
4-6
4.5.2 '!' Operator
4.5.3 1··· 1
4.5.4 l\[)[F 1 4.5.5 AMJL
Macros
The special symbol $MACEVAL can be used to change the character used for this function from its initial default of "%".
The character ! in front of a character in a macro parameter makes that character part of the parameter, even if the character is normally treated specially (e.g., , comma, etc.). The special symbol $MACQUOTE can be used to change the character used for this function from its initial default of "!".
A macro parameter enclosed in braces will have an outer layer of braces eliminated. The beginning and ending braces are the value of $'HACBEG and $'HACENO, respectively, but can be changed.
Beginning and ending braces must be properly nested. If the beginning and ending characters are the same, they cannot be nested. However, the character itself may be entered by either doubling it (e.g., "") or preceding it with'!'.
/\DEf followed by a symbol expands to a non-zero value if the symbol has been defined (previous to the current line) or 0 if the symbol has not been defined.
/\ NUL expands to a non-zero value if it is the last token on a 1.ine (not counting a comment), or 0 otherwise. The rest of the line is ignored,
4-7
Program Invocation
DIAPTER 5
PROGRAM INVOCATION
S.1 ASSEMBLER ClllWI> LINES AM> OPTIONS
The asm58 assembler accepts various connand line options for assembly, creates a listing, and creates an object file in a universal file format suitable for use by such utilities as a loader (see the Universal Object File Utilities User's Guide).
The assembler is invoked as follows:
asmSB [option ··· ] file
Valid assembler options are listed in Table 5-1.
Option
-d -en -1 -o objfile -ob -oc -on
-os
-ow
-p -r -s symfile
-u -w -x
Table 5-1 · ASBelllbler Options
Meaning
Reserved Stop after n errors Produce listing for files in file.1 Specify object file name other than a.out Produce object in binary form Produce object in character form Produce object with file and line number in
comment level 1 Produce object with source lines in comment
level 2 Produce object with user-generated warnings
in comment level 2 Produce listing on standard output Restrict to ZS instruction set Get assembler's symbol table initialization
from symfile Treat undefined symbols as externals Don't list warnings Produce cross-reference on file.x
DI
If the -1 option is given and the source filename ends in ".s", the listing is produced in filename.!. If the -s flag is not used, the assembler will obtain its symbols from a file on /z/bin/asm* whose name was used to invoke the assembler. Normally, this is /z/bin/lib/asm/asmSB**. The symbol file is an ordinary ASCII source file, and can contain any constructs that do not generate object code. This is used to create custom versions of the assembler.
* for VAX/UNIX it is /usr/local/bin/asm ** for VAX/UNIX it is :/usr/local/bin/asm/asmSB
5-1
Program Invocation
5.2 LISTill: FORMAT
5.J PROGRAM TERMINATION
The assembler produces a listing of the source program, along with generated object cod~. The various fields in the listing format are the heading, the location counter (LOC), the object code (OBJ CODE), the statement number (LINE#), and the source statement (SOURCE). They contain the following:
· The heading is on the first page of the listing and contains the date, time, year, file name, and page number, as well as the column headings LOC, OBJ CODE, LINE#, and SOURCE.
· LOC contains the value of the location counter for statements.
· OBJ CODE contains the qenerated object code. If a statement does not generate object code, this field is blank. Relocatable values are represented as Rsss+nnnnnnnn where ssss is the section number and nnnnnnnn is the offset within the section. Externals are noted by the "letter x, with a capital X representing the first byte. An asterisk (*) notes other link-time expressions that are not simply relocatable.
· LINE# contains the sequence number of each line of the source, starting at 1.
· SOURCE contains the source code including labels, opcodes, operands, and comments.
Appendix E shows a sample listing.
The assembler returns an error code of 0 if the program has no errors. Otherwise, the assembler returns an error code of 1 and error messages wi 11 appear in· the listing. These error messages will also be sent to the terminal with the relevant. file and line numbers. If possible, an object file will be created even if errors are present. Appendix D lists the et'ror messages and their explanations.
5-2
Appendix A
APPEN>IX A PSEtllO-OP SlllMRY
The following abbreviations apply to the pseudo-op summary:
n s sn d p f l 11
? [ ··· ]
Numeric expression
String String or numeric expression
Decimal digit Actual parameter Formal parameter Label (optional, more than one allowed)
Label (required, only one allowed) Hay be repeated Optional Not exactly equivalent (either form acceptable)
Label Pseudo-Op
Operand
Relocation Operations
l
.ORG
n
.PHASE
n
.OEPHASE
Section Operations
.MODULE
l
.SECTION
p p? 1 ···
Label Definition Operations
ll
.EQU
n
11
.SET
n
.GLOBAL
11
.EXTERNAL
11
Data·Definition Operations
l
.00
1
· BYTE
l
.WORD
l
.LONG
1
.QUAD
1
.QUINT
I
.EXTEND
1
.ASCII
l
· ASCIL
sn ··· n n
n n n n
sn ···
s ...
Meaning
Origin Phase Oephase
Module name Define a section
Equate Define a label Global symbols External symbols
Define dat.a Define byte data Define word data Define longword data Define quadword data Define 5-byte (extended) data Define extended data Define ASCII string Define ASCII string with length
III
A-1
Appendix .0.
Label Pseudo-Op
Operand
Meaning
Data Definition Operations - (Continued)
l
.ASCIC
s
l
.ASCIZ
s
Define ASCII string with flagged last character
Define null-terminated ASCII string
Reserve Space Operations
l
.BLOCK
n n?
1
.BLKB
n
1
.BLKW
n
l
.BLKL
n
1
.BLKQ
n
1
.BLKX
n
Reserve a block with optional
alignment Reserve a block of bytes
Reserve a block of words Reserve a block of longwords Reserve a block of quadwords Reserve a block of extended data
Conditional Assembly
.IF
n
.ELSE
n
.END IF
n
Start conditional block False branch of conditional End conditional block
Assembler Control Operations
.END
n?
.INCLUDE
p
· TITLE
p
.SUBTTL
p
.LIST
p
.WllST
p
.MLIST
p
· XLIST
p
.ERROR
s
.WARN
s
.PAGE
n?
.LIBRARY
p l?
.OCOMMENT
n? s
End program Include a source file
Listing t.i tle
Subtitle Control listing
Control conditional listing Control macro listing Control macro object listing List an error message List a warning message Start a new page library search Object comment
Macro Operations
11
.MACRO
.ENDM
f .·.
Define macro End MACRO definition
11
.PROC
· ENOP
l ···
Define a procedure End PROC definition
.EXITM
n?
.LOCAL
1
.REPT
n
.!RP
f s
.IRPC
f s
.ENOM
End macro expansion
Define macro labels Repeat. Repeat on parameter list
Repeat on character string End repeated block
A-2
Appendix B
APPENDIX B SPECIAL SYtBll...S
The following special symbols are defined. They can be reassigned using .SET pseudo-ops, and can be used as operands anywhere a label could be used. If needed, additional special symbols will be defined later.
Symbol
$'LIST $'WLIST $'CLIST $'MUST $'XLIST
Initial Value
1 1 1 1 1
Meaning
Controls the whole listing Controls the warning listing Controls listing of false conditional Controls macro expansion listing Controls listing of object code that does
not fit on original source line
These special symbols are used for control of the listing. If the low-order bit is 1, the corresponding item is listed. If the low-order bit is O, the item is not listed.
$'LIST controls the listing as a whole, $'WLIST controls the listing of warning messages, $'CLIST the listing of false conditionals, $'MLIST the listing of macro expansions, and $1-XLIST the listing of object code that does not fit on the original source line.
Default Yalue
$'SYMLEN
127
The maximum number of significant characters in a symbol.
$'UCASE
0
Treat all letters as uppercase.
$'STRESC
1\ 1
The string-escape character. The meaning of the
following character is given in the table in section 3.3.2 (constants).
B-1
Appendil< B
$'51LEN
10
$'510RD
'M'
$'52LEN
10
$'520RD
'H'
The length byte first,
and 'L'
=bylteea-sotrdesrign(if'Mic'an=t
most byte
significant first) of
strings surrounded by single and double quotes
respectively. In the byte-order parameters, only
the least-significant bit is actually looked at. Thus,
0 and 1 can be used instead of 'L' and 'H',
respectively.
$'SxLEN and $'SxORD are provided because previous ZBOOO assemblers have evaluated byte order differently
when using strings as numbers.
$'BASE
10
$'ZBASE
10
$'SBASE
8
The input default number base for numbers that start with non-zero digits, numbers that start with zero, and string escape sequences respectively. Setting $'ZBASE to 8 gives the C convention for octal numbers. Terms like $'BASE must be in the range 2 to 16.
$'ADRLEN
2
The length in bytes of an address. $'ADRLEN is 2.
The value for
$'ADRORD
'M'
The byte-order of an address. $'ADRORD is normally
left as 'M'; this can be changed if the assembler is being used to produce non-ZB0,000 code.
$'ADRTYPE
0
This indicates the current addressing type: 0 =
linear, 1 = segmented, 2 = compact (nonsegmented).
$'ALIGN
1
The alignment boundary for inst ructions and data with
length >= 1 byte.
B-2
Appendix B
$'EPUID
0
The current EPU Identifier. Unused.
$'ZB
0 (1 if -r option)
When set to 1, the SuperB instruction set is accepted. When cleared to 0 (explicitly or with an option), the ZB instruction set is accepted.
$'0PCOPT
0
If the value is not zero and an opcode is missing on a line containing expressions, the opcode .ll> (arbitrarylength data) will be assumed.
B-J
Appendix C
APPDl>IX C ASCII CHARACTER SET
Graphic
"
I $ '<I &
I
*
+
Numeric Deci·l Hex
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
A
11
8
12
c
13
D
14
E
15
F
16
10
17
11
18
12
19
1J
20
14
21
15
22
16
23
17
24
18
25
19
26
1A
27
18
28
1C
29
10
30
1E
31
1F
32
20
33
21
34
22
35
23
36
24
37
25
38
26
39
27
40
28
41
29
42
2A
43
28
44
2C
C-1
C~s
Null Start of heading St art of text End of text End of transmission Enquiry Acknowledge Bell Backspace Horizontal tabulation Line feed Vertical tabulation form feed Carriage return Shift out Shift in Data link escape Device control 1 Device control 2 Device control 3 Device control 4 Negative acknowledge Synchronous idle End of block Cancel End of medium
Substitute Escape
file separator Group separator Record separator Unit separ.ator Space Exclamation point Quotation mark Number sign Dollar sign Percent sign
Ampersand Apostrophe Opening parenthesis Closing parenthesis Asterisk Plus Conrna
Appendix C
ASCII Character Set (Continued)
Graphic
I
0
1 2 J 4 5 6 7 8 9
;
< = >
· ?
A
B
c
D
[
F G
H
I
J K
L M N 0
p
Q R
s u T v w
x
y
z
[
' ]
A
'
Numeric Deci-1 Hex
45
20
46
2E
47
2F
48
JO
49
J1
50
J2
51
JJ
52
34
53
35
54
36
55
37
56
38
57
39
58
JA
59
JB
60
JC
61
JD
62
J[
63
JF
64
4{)
65
41
66
42
67
43
68
44
69
45
70
46
71
47
72
48
73
49
74
4A
75
48
76
4C
77
40
78
4E
79
4F
80
50
81
51
82
52
BJ
·53
84
54
85
55
86
56
87
57
88
58
89
59
90
5A
91
58
92
5C
93
50
94
5E
95
5F
96
60
C-2
C~s
Hyphen (minus) Period (decimal point)
Slant Zero One
Two Three Four Five Six Seven Eight
Nine Colon Semicolon Less than Equals Greater than Question mark Commercial at Uppercase A Uppercase B Uppercase C Uppercase D Uppercase E Uppercase F Uppercase G Uppercase H Uppercase I Uppercase J Uppercase K Uppercase L Uppercase M Uppercase N Uppercase 0 Uppercase P Uppercase Q Uppercase R Uppercase S Uppercase T Uppercase U Uppercase V Uppercase W Uppercase X
Uppercase Y Uppercase Z Opening bracket Reverse slant
Closing bracket Circumflex Underscore Grave accent
ASCII Character
Set
(Continued)
Appendix C
Graphic
a b c d e f g h i
j k
1
m
n
0
p
q
r s t u
v
w x
y
z
l
I )
Nu-ric Decimal Hex
97
61
98
62
99
63
100
64
101
65
102
66
103
67
104
68
105
69
106
6A
107
6B
108
6C
109
60
110
6E
111
6F
112
70
113
71
114
72
115
73
116
74
117
75
118
76
119
77
120
78
121
79
122
7A
123
78
124
7C
125
70
126
7E
127
7F
Coiments
Lowercase a Lowercase b Lowercase c Lowercase d Lowercase e Lowercase f Lowercase g Lowercase h Lowercase i Lowercase j Lowercase k Lowercase 1 Lowercase m Lowercase n Lowercase o Lowercase p Lowercase q Lowercase r Lowercase s Lowercase t Lowercase u Lowercase v Lowercase w Lowercase x Lowercase y Lowercase z Opening (left) brace Vertical line Closing (right) brace Tilde Delete
DI
C-3
Appendix D
APPEtl>IX D
ERROR tESSAGES AM> EXPLANATIONS
EM>Ir (end conditional) expected
.Ir was seen but not followed by a matching .ENDIF.
ENDM (end 11aero definition) expected
End of file was reached while still inside a macro definition.
can't set read-only symbol
An attempt was made to set a special symbol such as $'PASS, that cannot be redefined.
extended instruction set not allo.ed
An attempt was made to use a Super8 instruction or addressing mode not available on the ZB CPU while the -r option or $' ZS flag is in effect.
extra parameters (ignored)
A pseudo-op was passed more parameters than it requires. The extra parameters will be ignored.
III
extra right parenthesis (ignored)
A right parenthesis was seen without a matching left parenthesis. It is ignored.
forward reference not allowed here
An expression in an IF, COND, EQU, or SET contains a forward reference (a label that has not been defined earlier in the program).
label required
A pseudo-op such as EQU or SET, which require a label, does not have one.
line too long (truncated)
The source file or a macro expansion contains a line longer than 512 characters.
link-ti.e expression not allowed here
An expression that cannot be evaluated by the assembler has been used in a context where the assembler needs to know its value.
D-1
Appendix D
llissinQ par.ater A pseudo-op has been given fewer parameters than it requires.
llissinQ right parenthesis (assu·ed) The end of an expression was encountered without finding a right parenthesis to match a left parenthesis already seen. The assembler will evaluate the expression as if the missing parenthesis had been at the end of the expression.
Multiple definition A symbol has been used as a label, defined by an EQU, or defined as a macro more than once.
no i..,ut file The assembler cannot open the specified input file.
operand expected (0 8SSU!Ed) A binary expression operator (such as +) was not followed by an operand. A zero operand is assumed.
operation not defined on register An expression operator (such as *) has been applied to a register value for which it is not valid. The only expression operators that can be applied to registers are indexing and indirection.
parser stack overflow The assembler received an expression too complex for it to handle.
phase error-passes out of sync. Something happened differently on passes 1 and 2 of the assembler. This can occur if an opcode or pseudo-op is used and later redefined as a macro.
storage allocation failed The assembler ran out of storage as a result of a combination of symbol table, macro definitions, and macro invocations.
syntax error A source statement contains a syntactic error, usually in an expression, which cannot be otherwise classified.
D-2
Appendix D
undef'ined addressing mode expression
An expression represents an addressing mode not available on the Supers and ZB CPU, such as (HL + A).
undefined char~ter
A character appears in the input that the assembler does not understand.
undefined synbol
A symbol has been used that is never defined. The value 0 will normally be used.
value out of range
An expression does not fit in the specified size of field (for example, an address in a .BYTE statement).
wrong operand type for this operation
An opcode has been given an operand with an addressing mode that does not apply to it.
ID
D-3
asmS8 version 1.0
LOC
OBJ
00000000 123S
00000002 1335
00000004 1440e3
00000007 14e520
OOOOOOOa 144020
OOOOOOOd 1540e3
00000010 1Se520
00000013 1S4U20
00000016 16e340
00000019 162040
OOOOOOlc 172040
OOOOOOlf 17e340
00000022 023S 00000024 033S 00000026 0440e3 00000029 04e520 0000002c 044020 0000002f 0540e3 00000032 OSeS20 0000003S OS4020 00000038 06 e340 0000003b 062040 0000003e 072040 00000041 07e340
00000044 523S 00000046 5335 00000048 S440e3 0000004b 54e520 0000004e 544020 00000051 SS40e3 OOOOOOS4 SSe520 OOOOOOS7 S54020 OOOOOOSa S6e340 OOOOOOSd S62040 00000060 s 72040 00000063 57e340
00000066 d4e2 00000068 d420 0000006a d60040
0000006d ef
0000006e b0e3 00000070 b020 00000072 ble3 00000074 bl20
00000076 60e3 00000078 6020
t.z8inst
LINEii -·-- SOURCE
l
adc
2
adc
3
adc
4
adc
s
adc
6
adc
7
adc
8
adc
9
adc
10
adc
11
adc
12
adc
13
14
add
lS
add
16
add
17
add
18
add
19
add
20
a4d
21
add
22
add
23
add
24
add
2S
add
26
27
and
28
and
29
and
30
and
31
and
32
and
33
and
34
and
3S
and
36
and
37
and
38
and
39
40
call
41
call
42
call
43
44
ccf
4S
46
clr
47
clr
48
clr
49
clr
so
Sl
com
S2
com
r3,rS r3,@rS r3,64 32,rS 32,64 r3,@64 32 ,@rs 32 ,@64 r3 ,#64 32 ,#64 @32 'f/64 @r3 ,1164
r3,rS r3 ,@rs r3,64 32,rS 32,64 r3,@64 32 ,@rs 32,@64 r3, 1164 32'1/64 @32,#64 @r3, #64
r3,r5 r3,@rs r3,64 32 ,rs 32,64 r3 ,@64 32 ,@r5 32,@64 r3,#64 32 'f/64 @32,#64 @r3, #64
@rr2 @32 64
r3 32 @r3 @32
r3 32
E-1
Appendil( E
Appendix E
0000007a 6le3 0000007c 6120
0000007e a235 00000080 a3JS 00000082 a440e3 00000085 a4e520 00000088 a44020 0000008b a540e3 0000008e a5e520 00000091 a54020 00000094 a6e340 00000097 a72040 0000009a a7 e340
0000009d 40e3 0000009f 4020 OOOOOOal 4le3 000000a3 4120
OOOOOOaS 00e3 000000a7 0020 000000a9 Ole3 OOOOOOab 0120
OOOOOOad 80e2 OOOOOOaf 8020 000000 bl 81 e3 000000b3 8120
000000b5 8f
0000001>6 3afc
000000b8 9f
000000b9 3e OOOOOOba 2020 OOOOOObc 2le3 OOOOOObe 2120
OOOOOOcO a0e2 000000c2 a020 000000c4 ale3 000000c6 al20
000000c8 bf
000000c9 8d0400 OOOOOOcc ed0400 OOOOOOcf 30e2 OOOOOOdl 3020
000000d3 8bfe 000000d5 ebf e
53
COii.
@r3
54
CODI
@32
55
56
cp
r3,r5
.57
cp
r3,@r5
58
cp
r3,64
59
cp
32,r5
60
cp
32,64
61
cp
r3 ,@64
62
cp
32 ,@rs
63
cp
32,@64
64
cp
r3,H64
65
cp
@32,#64
66
cp
@r3,#64
67
68
da
r3
69
da
32
70
da
@r3
71
da
@32
72
73
dee
r3
74
dee
'32
75
dee
@r3
76
dee
@32
77
78
decw rr2
79
decw 32
80
decw @r3
81
decw @32
82
83
di
84
85
djnz r3,$
86
87
ei
88
89
inc
r3
90
inc
32
91
inc
@r3
92
inc
@32
93
94
incw rr2
95
incw 32
96
lncw @r3
97
incw @32
98
99
iret
100
101
jp
1024
102
jp
nz,1024
103
jp
@rr2
104
jp
@32
105
106
jr
$
107
jr
nz,$
E-2
OOOOOOd7 3c40
000000d9 38 e5 OOOOOOdb 3840 OOOOOOdd 5920
OOOOOOdf e335 OOOOOOel f335
000000e3 e44020
000000e6 e335 000000e8 eS40e3 OOOOOOeb e5e520 OOOOOOee eS4020
oooooon 3c40
000000£3 e62040 000000£6 e7 e340 000000£9 d62040
OOOOOOfc £335 OOOOOOfe f S40e3 00000101 f5e520 00000104 £54020
00000107 e73540 OOOOOlOa d7S340
OOOOOlOd c234 0000010£ d252
00000111 c334 000001.13 d3S2
00000115 8234 00000117 9252
00000119 93S2 0000011 b 8334
OOOOOlld ff
OOOOOlle 423S 00000120 433S 00000122 4440e3 0000012S 44e520 00000128 444020 0000012b 4540e3 0000012e 45e520 00000131 454020 00000134 46e340 00000137 462040 0000013a 472040
108
109
ld
r3,#64
110
111
I4
r3,r5
112
ld
r3,64
113
Id
32,rS
114
llS
Id
r3 ,@rs
116
ld
@r3,r5
117
118
Id
32,64
119
120
Id
r3,@r5
121
Id
r3,@64
122
Id
.32,@rs
123
Id
32,@64
124
12S
Id
r3,#64
126
Id
32,#64
127
Id
@r3,1164
128
Id
@32,#64
129
130
Id
@r3,r5
131
Id
@r3, 64
132
Id
@32 'rs
133
Id
@32,64
134
13S
Id
r3 ,64(r5)
136
Id
64(r3) ,rs
137
138
Ide
r3,@rr4
139
Ide
@rr2, rS
140
141
Idci @r3 ,@rr4
142
Idci @rr2 ,@rs
143
144
Ide
r3,@rr4
14S
Ide
@t"r2, rS
146
147
ldei @u2,@rS
148
ldei @r3,@rr4
149
lSO
nop
lSl
1S2
or
r3,rS
153
or
r3 ,@rs
154
or
r3,64
155
or
32,r5
156
or
32,64
157
or
r3,@64
158
or
32,@r5
159
or
32,@64
160
or
r3,IJ64
161
or
32,1164
162
or
@32,#64
E-3
Appendix [
Appendix E
0000013d 47e340
00000140 50e3 00000142 5020 00000144 5le3 00000146 5120
00000148 70e3 0000014a 7020 0000014e 7le3 0000014e 7120
00000150 cf
00000151 af
00000152 90e3 00000154 9020 00000156 9le3 00000158 9120
0000015a 10e3 0000015c 1020 0000015e lle3 00000160 1120
00000162 e0e3 00000164 e020 00000166 ele3 00000168 el20
0000016a c0e3 0000016e e020 0000016e cle3 00000170 cl20
00000172 3235 00000174 3335 00000176 3440e3 00000179 34e520 0000017e 344020 0000017£ 3540e3 00000182 35e520 00000185 354020 00000188 36e340 0000018h 362040 0000018e 372040 00000191 37e340
00000194 df
00000195 d0e3 00000197 d020 00000199 dle3 0000019h dl20
163
or
@r3,#64
164
165
pop
r3
166
pop
32
167
pop
@r3
168
pop
@32
169
170
push r3
171
push 32
172
push @r3
173
push @32
174
175
ref
176
177
ret
178
179
rl
r3
180
rl
32
181
rl
@r3
182
rl
@32
183
184
rlc
r3
185
rlc
32
186
rle
@r3
187
rle
@32
188
189
rr
r3
190
rr
32
191
rr
@r3
192
rr
@32
193
194
rre
r3
195
rrc
32
196
rrc
@r3
197
rre
@32
198
199
she
r3,r5
200
she
r3,@r5
201
she
r3,64
202
she
32,rS
203
she
32,64
204
she
r3,@64
205
she
32,@r5
206
she
32,@64
207
she
r3,#64
208
she
32,#64
209
she
@32,#64
210
she
@r3 ,#64
211
212
sef
213
214
sra
r3
215
sra
32
216
sra
@r3
217
sra
@32
E-4
0000019d 3170
0000019£ 2235 OOOOOlal 2335 00000la3 2440e3 00000la6 24e520 00000la9 244020 OOOOOlac 2S40e3 OOOOOlaf 2Se520 000001 b2 254020 000001 b5 26e340 900001 b8 262040 OOOOOlbb 272040 OOOOOlbe 27e340
OOOOOlcl f0e3 00000lc3 f020 OOOOOlcS fle3 OOOOOlc7 fl20
00000lc9 6235 OOOOOlcb 6335 OOOOOlcd 6440e3 OOOOOldO 64e520 00000ld3 644020 00000ld6 6S40e3 00000ld9 6Se520 OOOOOldc 6S4020 OOOOOldf 66e340 00000le2 662040 OOOOOleS 672040 00000le8 67e340
OOOOOleb 7235 OOOOOled 733S
OOOOOlef 7440e3 00000lf2 74e520 000001£5 744020 000001£8 7S40e3 OOOOOlfb· 7Se520 OOOOOlfe 7S4020 00000201 76e340 00000204 762040 000002Q7 772040 0000020a 77e340
0000020d b235 0000020f b335 00000211 b440e3 00000214 b4c520 00000217 b44020 000002la bS40e3 000002ld b5eS20
218
219
srp il70h
220
221
sub
r3,rS
222
sub
r3 ,@rs
223
sub r3,64
224
sub 32,rS
22S
sub 32,64
226
sub
rJ,@64
227
sub 32 ,@rs
228
sub 32,@64
229
sub
r3,#64
230
sub 32,#64
231
sub @32,#64
232
sub @r3,#64
233
234
swap r3
23S
swap 32
236
swap @r3
237
swap @32
238
239
tcm r3,r5
240
tcm r3 ,@rs
241
tcm r3,64
242
tcm 32,rS
243
tcm 32,64
244
tcm
r3 ,@64
24S
tcm 32 ,@rs
246
tcm 32,@64
247
tcm r3,#64
248
tcm 32,#64
249
tcm @32,#64
250
tcm @r3 ,#64
251
2S2
tm
r3,r5
253
tm
r3 ,@rs
2S4
2SS
tm
r3,64
2S6
tm
32,rS
2S7
tm
32,64
258
tm
rJ,@64
2S9
tm
32,@rs
260
tm
32,@64
261
tm
r3,#64
262
tm
32,#64
263
tm
@32,#64
264
tm
@r3 ,#64
26S
266
xor
r3,r5
267
xor
r3,@rS
268
xor r3,64
269
xor J2,r5
270
xor 32,64
271
xor
r3,@64
272
xor 32 ,@rs
E-5
Appendix E
Appendix E
00000220 b54020 00000223 b6c340 00000226 b62040 00000229 b72040 0000022c b7e340
0000022£ 38ff 00000231 38fe 00000233 38fd 00000235 38fc 00000237 38fb 00000239 38fa 0000023b 38£9 0000023d 38£8 0000023£ 38f7 00000241 38£6 00000243 38£5 00000245 38£4 00000247 38£3 00000249 38£2 0000024 b 38£1 0000024d 38£0 0000024£ 3803 00000251 3802 00000253 3801 00000255 3800
00000257 38ff 00000259 38fe 0000025b 38fd 0000025d 38fc 0000025£ 38fb 00000261 38fa 00000263 38£9 00000265 38£8 00000267 38£7 00000269 38£6 0000026b 38£5 0000026d 38£4 0000026£ 38£3 00000271 38£2 00000273 38£1 00000275 38£0 00000277 3803 00000279 3802 0000027b 3801 0000027d 3800
·273
xor
32,@64
274
xor
r3,1164
275
xor
32,1164
276
xor
@32,1164
277
xor
@r3, 1164
278
279
280 ;defined register names
281
282
ld
r3,spl
283
ld
r3,sph
284
ld
r3,rp
285
ld
r3,flags
236
ld
r3,imr
287
ld
r3 ,irq
288
ld
r3,ipr
289
ld
r3,p01m
290
ld
r3,p3m
291
ld
r3 ,p2m
292
ld
r3,pre0·
293
ld
r3, tO
294
ld
r3,prel
295
ld
r3, tl
296
ld
r3,tmr
i97
ld
r3 ,sio
298
ld
r3,p3
299
ld
r3,p2
300
ld
r3,pl
301
ld
r3,p0
302
303
304 ;defined register names
305
306
ld
r3,SPL
307
ld
r3 ,SPH
308
ld
r3,RP
309
ld
r3,FLAGS
310
ld
r3,IMR
311
ld
r3,IRQ
312
ld
r3,IPR
313
ld
r3,P01H
314
ld
r3,P3M
315
ld
r3_,P2M
316
ld
r3,PRE0
317
ld
r3,TO
318
ld
r3,PRE1
319
ld
r3,Tl
320
ld
r3,TMR
321
ld
r3,SIO
322
ld
r3,P3
323
ld
r3,P2
324
ld
r3,Pl
325
ld
r3,PO
326
327 ;test for condition codes
E-6
0000027£ Od0080
00000282 6d0080 00000285 ed0080 00000288 6d0080 0000028b ed0080
0000028e 7d0080 00000291 f d0080
00000294 ad0080 00000297 ld0080 0000029a 9d0080 0000029d 2d0080
000002a0 dd0080 000002a3 5d0080
000002a6 cd0080 000002a9 4d0080
000002ac bd0080 000002af 7d0080 000002b2 fd0080 000002b5 3d0080
328
329
jp
f,128
330
331
jp
z,128
332
jp
nz,128
333
jp
eq,128
334
jp
ne,128
335
336
jp
c,128
337
jp
nc,128
338
339
jp
gt,128
340
jp
lt,128
341
jp
ge,128
342
jp
le ,128
343
344
jp
pl,128
345
jp
mi,128
346
347
jp
nov,128
348
jp
ov,128
349
350
jp
ugt ,128
351
jp
ult,128
352
jp
uge,128
353
jp
ule,128
354
Appendix E
E-7
AppendilC E
asmS8 version 1.0
LOC
OBJ
00000000 123S 00000002 133S 00000004 1440c3 00000007 14cS20 OOOOOOOa 144020 OOOOOOOd 1S40c3 00000010 1Sc520 00000013 1S4020 00000016 16c340 00000019 162040
OOOOOOlc 0235 OOOOOOle 0335 00000020 0440c3 00000023 04c520 00000026 044020 00000029 OS40c3 0000002c 05c520 0000002f 054020 00000032 06c340 00000035 062040
00000038 S235 0000003a 5335 0000003c 5440c3 0000003£ 54c520 00000042 544020 OOOOOQ4S SS40c3 00000048 5Sc520 0000004 b SS4020 0000004e 56c340 00000051 562040
00000054 673ec5 OOOOOOS7 673e40 OOOOOOSa 675fc3 OOOOOOSd 675f20
00000060 173ec5 00000063 173e40
00000066 573e
00000068 773e
0000006a 773f
0000006c 073ec5 0000006£ 073e40
t.s8inst
LINE# --- SOURCE ---
1 ;reference test source for Super8 instructin set.
2
3
4
adc r3,r5
5
adc r3 ,@rs
6
adc r3,64
7
adc 32,rS
8
adc 32,64
9
adc r3,@64
10
adc 32 ,@rs
11
adc 32,@64
12
adc r3,#64
13
adc 32,#64
14
15
add r3,rS
16
add r3,@r5
17
add r3,64
18
add 32,rS
19
add 32,64
20
add r3 ,@64
21
add 32,@rS
22
add 32,@64
23
add r3,#64
24
add 32,#64
25
26
and r3,r5
27
and r3 ,@rs
28
and r3,64
29
and 32,rS
30
and 32,64
31
and r3,@64
32
and .32 ,@rs
33
and 32,@64
34
and r3,#64
35
and 32,#64
36
37
band r3,r5,#7
38
band r3,64,#7
39
band r3,#7 ,rs
40
band 32,#7,r5
41
42
bcp r3,r5,#7
43
bcp r3,64,117
44
4S
bite r3,#7
46
47
bi tr r3,fl7
48
49
bits r3,#7
50
Sl
bor r3,rS,#7
52
bor r3,64,#7
E-B
00000072 075f c3 00000075 075£20
00000078 375efd 0000007b 375£fd
0000007e 273ec5 00000081 273e40 00000084 275fc3 00000087 275£20
0000008a d420 0000008c f 4e2 ·0000008e £420 00000090 f 60040
00000093 ef
00000094 b0e3 00000096 b020 00000098 bl c3 0000009a bl20
0000009e 60c3 0000009e 6020 OOOOOOaO 6lc3 000000a2 6120
000000a4 a235 000000a6 a335 000000a8 a440c3 OOOOOOab a4e520 OOOOOOae a44020 OOOOOObl a540c3 000000b4 a5c520 000000b7 a54020 OOOOOOba a6 c340
OOOOOObd d253fd
OOOOOOeO c253fd
000000c3 40e3 OOOOOOc5 4020 000000c7 4lc3 000000c9 4120
OOOOOOcb 00e3 OOOOOOcd 0020 OOOOOOcf Olc3 OOOOOOdl 0120
000000d3 80c2 OOOOOOdS 8020 000000d7 81 c3
53
bor r3,#7 ,r5
54
bor 32,#7 ,r5
55
56
btjrf $,r5,it7
57
btjrt $. r5, 117
58
59
bxor r3,r5,#7
60
bxor r3,64,#7
61
bxor r3,#7,r5
62
bxor 32,#7 ,r5
63
64
call #32
65
call @rr2
66
call @32
67
call 64
68
69
ccf
70
71
clr r3
72
clr 32
73
clr @r3
74
clr @32
75
76
com r3
77
com 32
78
com @r3
79
com @32
80
81
cp
r3 ,r5
82
cp
r3,@r5
83
cp
r3,64
84
cp
32,r5
85
cp
32,64
86
cp
r3 ,@64
87
cp
32,@r5
88
cp
32 ,@64
89
cp
r3,#64
90
91
cpijne r3,@r5,$
92
93
cpije r3,@r5,$
94
95
da
r3
96
da
32
97
da
@r3
98
da
@32
99
100
dee r3
101
dee 32
102
dee @r3
103
dee @32
104
105
decw rr2
106
decw 32
107
dccw @r3
E-9
Appendi>< E
Appendix E
000000d9 8120
OOOOOOdb Sf
OOOOOOdc 94c5c2 OOOOOOdf 9440c2 000000e2 94c520 000000e5 944020 000000e8 95c5c2 OOOOOOeb 9S40c2 OOOOOOee 95c520 OOOOOOfl 954020 000000£4 9640c2 000000f7 964020
OOOOOOfa 3afe
OOOOOOfc 9f
OOOOOOfd lf
OOOOOOfe 2f
000000ff 3e 00000100 2020 00000102 21 c3 00000104 2120
00000106 a0c2 00000108 · a020 OOOOOlOa al c3 OOOOOlOc a120
OOOOOlOe bf
0000010£ 8d0400 00000112 ed0400 OOOOOllS 30c2 00000117 3020
00000119 Sbfe OOOOOllb ebfe
OOOOOlld 3c40
000001 lf 38c5 00000121 3840 00000123 S920
0000012S c735 00000127 d73S
00000129 e44020
0000012c c735
108
de cw @32
109
110
di
111
112
div rr2,rS
113
div rr2,64
H4
div 32,rS
us
div 32,64
116
div rr2 ,@rs
117
div rr2 ,@64
118
div 32 ,@rs
119
div 32,@64
120
div rr2,fl64
121
div 32,#64
122
123
djnz r3,$
124
125
ei
126
127
enter
128
129
exit
130
131
inc r3
132
inc 32
133
inc @r3
134
inc @32
13S
136
incw rr2
137
incw 32
138
incw @r3
139
incw @32
140
141
iret
142
143
jp
1024
144
jp nz,1024
145
jp
@rr2
146
jp @32
147
148
jr $
149
jr
nz,$
lSO
151
ld
r3,#64
152
1S3
ld
r3,rS
1S4
ld
r3,64
lSS
ld 32,r5
156
1S7
ld
r3,@rS
158
ld @r3,rS
1S9
160
ld 32,64
161
162
ld
r3 ,@r5
E-10
0000012e e540c3 00000131 e5c520 00000134 e54020
00000137 3c40 00000139 e62040 0000013c d6c340 0000013f d62040
00000142 d735 00000144 f540c3 00000147 f5c520 0000014a £54020
0000014d 873540 00000150 975340
00000153 473ec5 00000156 473e40 00000159 475fc3 0000015c 475f20
0000015f a7340004 00000163 e73440 00000166 b7520004 0000016a f75240 0000016d b7500020 00000171 a7500040 00000175 c334 00000177 d352
00000179 e234 0000017b e334 0000017d £252 0000017£ £352
00000181 a7350004 00000185 e73540 00000188 b7530004 0000018c f75340 0000018£ b7510020 00000193 a75i0040 00000197 c335 00000199 d353
0000019b e235 0000019d e335 0000019£ £253 OOOOOlal f353
0000Qla3 c4c4c2 00000la6 c440c2 00000la9 c4c420 OOOOOlac c44020
163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 .188 189 190 191 192 193 194 195 196 197 198 199 200 201' 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217
ld
r3,@64
ld· .32 ,@r5
ld
32,@64
ld
r3,#64
ld
32,#6-4
ld
@r3,#64
ld @32,#64
ld @r3,r5
ld
@r3 ,64
ld
@32,r5
ld @32,64
ld
r3,64(r5}
ld 64(r3),r5
ldb r3,r5,ll7 ldb r3,64,#7 ldb r3,#7 ,r5 ldb 32,#7,r5
ldc r3, 1024(rr4} ldc r3,64(rr4} ldc 1024(rr2},r5
ldc 64(rr2) ,r5 ldc 32,rS ldc r5,64 ldc r3,@rr4 ldc @rr2,r5
ldcd r3,@rr4 ldci r3,@rr4 ldcpd @rr2,r5 ldcpi @rr2,r5
lde r3, 1024(rr4) lde r3,64(rr4) lde 1024(rr2),r5 lde 64( rr2), r5 lde 32,r5 lde r5,64 lde r3,@rr4 lde @rr2,r5
lded r3 ,@rr4 ldei r3,@rr4 ldepd @rr2,r5 ldepi @rr2., r5
ldw rr2,rr4 ldw rr2,64 ldw 32 ,rr4 ldw 32,64
E-11
Appendix E
III
Appendix E
OOOOOlaf c5c4c2 00000lb2 c540c2 000001 b5 c5c420 00000lb8 c54020
OOOOOlbb c6c20400 OOOOOlbf c6200400
00000lc3 84c5c2 OOOOOlc6 8440c2 00000lc9 84c520 OOOOOlcc 844020 OOOOOlcf '85cSc2 00000ld2 8540c2 00000ld5 85c520 00000ld8 8S4020 OOOOOldb 8640c2 OOOOOlde 864020
OOOOOlel Of
00000le2 ff
00000le3 423S OOOOOleS 4335 00000le7 4440c3 OOOOOlea 44c520 OOOOOled 444020 000001£0 4540c3 000001£3 45cS20 000001£6 454020 000001£9 46c340 OOOOOlf c 462040
000001££ 50c3 00000201 5020 00000203 5lc3 0000020S 5120
00000207 92cSc3 0000020a 9240c3 0000020d 92c520 00000210 924020
00000213 93cSc3 00000216 9340c3 00000219 93c520 000002lc 934020
0000021£ 70c3 00000221 7020 00000223 7lc3 00000225 7120
00000227 82c3cS
218
ldw rr2,@r4
219
ldw rr2 ,@64
220
ldw 32 ,@r4
221
ldw 32,@64
222
223
ldw rr2, 111024
224
ldw 32,#1024
225
226
mult rr2, r5
227
mult rr2,64
228
mult 32,r5
229
mult 32,64
230
mult rr2 ,@rs
231
mult rr2,@64
232
mult 32,@rS
233
mult 32,@64
234
mult rr2,#64
235
mult 32,#64
236
237
next
238
239
nop
240
241
<>r
r3,r5
242
or
r3 ,@rs
243
or
r3,64
244
or
32,r5
245
or
32,64
246
or
r3,@64
247
or
32,@rS
248
or
32,@64
249
or
r3, 1!64
250
or
32, 1164
251
252
pop r3
253
pop 32
254
pop @r3
2S5
pop @32
256
257
popud r3 ,@rs
2S8
popud r3,@64
259
popud 32,@rS
260
popud 32,@64
261
262
popui r3 ,@r5
263
popui r.3,@64
264
popui 32,@rS
265
popui 32,@64
266
267
push r3
268
push 32
269
push @r3
270
push @32
271
272
pushud @r3 ,rs
F-12
0000022a 82c340 0000022d 8220c5 00000230 822040
00000233 83c3c5 00000236 83c340 00000239 8320c5 0000023c 832040
0000023f cf
00000240 d5a5
00000242 af
00000243 90c3 00000245 9020 00000247 9lc3 00000249 9120
0000024b 10c3 0000024d 1020 0000024f llc3 00000251 1120
00000253 e0c3 00000255 e020 00000257 elc3 00000259 el20
0000025b c0c3 0000025d c020 0000025f clc3 00000261 cl20
00000263 4f
00000264 5f
00000265 3235 00000267 3335 00000269 3440c3 0000026c 34e520 0000026f 344020 00000272 3540c3 00000275 35e520 00000278 354020 0000027b 36e340 0000027e 362040
00000281 df
00000282 d0c3 00000284 d020 00000286 dl c3
273
pushud @r3,64
274
pushud @32, r5
275
pushud @32,64
276
277
pushui @r3, rS
278
pushui @r3, 64
279
pushui @32,rS
280
pushui @32,64
281
282
ref
283
284
rdr /10a5h
285
286
ret
287
288
rl
r3
289
rl
32
290
rl
@r3
291
rl
@32
292
293
rlc r3
294
rlc 32
295
rlc @r3
296
rlc @32
297
298
rr
r3
299
rr
32
300
rr
@r3
301
rr
@32
302
303
rrc r3
304
rrc 32
305
rrc @r3
306
rrc @32
307
308
sbO
309
310
sbl
311
312
sbc r3, rS
313
sbe r3 ,@rs
314
sbe r3,64
315
sbe 32,r5
316
sbc 32,64
317
she r3,@64
318
sbe 32,@rs
319
she 32,@64
320
she r3 ,f/64
321
sbe 32 ,1164
322
323
sef
324
325
sra r3
326
sra 32
327
sra @r3
E-13
Appendix E
DI
Appendix E
00000288 dl20
0000028a 3180 0000028c 3181 0000028e 3182
00000290 2235 00000292 2335 00000294 2440c3 00000297 24c520 0000029a 244020 0000029d 2540c3 000002a0 2Sc520 000002a3 254020 000002a6 26c340 000002a9 262040
000002ac f0c3 000002ae f020 000002b0 flc3 000002b2 fl20
000002b4 6235 000002b6 6335 000002b8 6440c3 000002bb 64c520 000002be 644020 000002cl 6540c3 000002c4 65c520 000002c7 654020 000002ca 66c340 000002cd 662040
000002d0 7235 000002d2 7335
000002d4 7440c3 000002d7 74c520 000002da 744020 000002dd 7540c3 000002e0 75c520 000002e3 754020 000002e6 76c340 000002e9 762040
000002ec b235 000002ee b335 000002f0 b440c3 000002f3 b4c520 000002 f6 b44020 000002 f9 b540c3 000002 fc b5c520 000002ff b54020 00000302 b6c340 00000305 b62040
328
sra @32
329
330
srp 1!128
331
srpl i/128
332
srpO #128
333
334
sub r3,r5
335
sub r3,@r5
336
sub r3,64
337
sub 32,rS
338
sub 32,64
339
sub r3 ,@64
340
sub 32,@rS
341
sub 32,@64
342
sub r3 ,1164
343
sub 32'1164
344
345
swap r3
346
swap 32
347
swap @r3
348
swap @32
349
350
tcm r3,r5
351
tcm r3 ,@rs
352
tcm r3,64
353
tcm 32,rS
354
tcm 32,64
355
tcm r3,@64
356
tcm 32,@rS
357
tcm 32,@64
358
tcm r3, 1164
359
tcm 32,#64
360
361
tm
r3,r5
362
tm
r3 ,@rs
363
364
tm
r3,64
365
tm 32,r5
366
tm 32,64
367
tm
r3,@64
368
tm 32 ,@rs
369
tm
32,@64
370
tm
r3,#64
371
tm
32,#64
372
373
xor r3,r5
374
xor r'3,@r5
375
xor r3,64
376
xor 32,rS
377
xor 32,64
378
xor r3,@64
379
xor 32 ,@rs
380
xor 32,@64
181
xor r3,1164
382
xor 32,#64
£-14
00000308 3f
00000309 38de 0000030b 38dd 0000030d 38dc 0000030f c4dac2 00000312 38db 00000314 38da 00000316 c4d8c2 00000319 38d9 0000031 b 38d8 000003ld 38d7 000003 lf 38d6 00000321 38d5 00000323 38d4 00000325 38d3 00000327 38d2 00000329 38dl 0000032b 38d0
0000032d 38ff 0000032f 38fe 00000331 38fd 00000333 38fc 00000335 38fb 00000337 38fa 00000339 38£9 0000033b 38f8 0000033d 38£7 0000033£ 38£6 00000341 38f5 00000343 38£4 00000345 38£1 00000347 38dl 00000349 38£0 0000034b 38ed 0000034d 38ec 0000034£ 38eb 00000351 38ea 00000353 38e9 00000355 38e8 00000357 38e7 00000359 38e6 0000035b c4e4c2 0000035e 38e5 00000360 38e4 00000362 c4e2c2 00000365 38e3 00000367 38e4 00000369 38el
383
384
wfi
385
386 ;defined register names
387
388
ld
r3,sym
389
ld
r3 ,imr
390
ld
r3,irr
391
ldw
rr2,ip
392
ld
r3,ipl
393
ld
r3 ,iph
394
ldw
rr2 ,sp
395
ld
r3, spl
396
ld
r3,sph
397
ld
r3 ,rpl
398
ld
r3, rpO
399
ld
r3 ,flags
400
ld
r3,p4
401
ld
r3 ,p3
402
ld
r3,p2
403
ld
r3, pl
404
ld
r3,p0
405
406 Bank 0 Special Registers
407
408
ld
r3,ipr
409
ld
r3,emt
410
ld
r3,p2bip
411
ld
r3, p2aip
412
ld
r3,p2dm
413
ld
r3, p2cm
414
ld
r3 ,p2bm
415
ld
r3 ,p2am
416
ld
r3,p4od
417
ld
r3,p4d
418
ld
r3,hlc
419
ld
r3 ,hOc
420
ld
r3,pm
421
ld
r3,pl
422
ld
r3,p0m
423
ld
r3 ,uie
424
ld
r3,urc
425
ld
r3, utc
426
ld
r3 ,sio
427
ld
r3, sie
428
ld
r3,srcb
429
ld
r3 ,srca
430
ld
r3,stc
431
ldw
rr2 ,cl c
432
ld
r3 ,cl cl
433
ld
r3 ,cl ch
434
ldw
rr2 ,cOc
435
ld
r3 ,cOcl
436
ld
r3,clch
437
ld
r3 ,cl ct
E-15
Appendix E
Appendix E
0000036b 38e0
0000036d 38ff 0000036£ 38fe 00000371 38fb 00000373 38fa 00000375 c4f8c2 00000378 38f9 0000037a 38f8 0000037c c4f0c2 0000037 f 38fl 00000381 38f0 00000383 c4eec2 00000386 38ef 00000388 38ee 0000038a 38ed 00000 38 c 38ec 0000038e 38eb 00000390 38ea 00000392 c4e8c2 00000395 38e9 00000397 38e8 00000399 c4e4c2 0000039c 38e5 0000039e 38e4 000003a0 c4e2c2 000003a3 38e3 000003a5 38e2 000003a7 38el 000003a9 38e0
000003ab 38de 000003ad 38dd 000003af 38dc 000003bl c4dac2 000003 b4 38db 000003b6 38da 000003b8 c4d8c2 000003bb 38d9 000003bd 38d8 000003bf 38d7 000003cl 38d6 000003c3 38d5 000003c5 38d4 000003c7 38d3 000003c9 38d2 000003cb 38dl 000003cd 38d0
000003cf 38ff
438
ld
r3 ,cOct
439
440 Bank 1 Special Registers
441
442
ld
r3,wumsk
443
ld
r3,wumch
444
ld
r3,umb
445
ld
r3,uma
446
ldw
rr2,ubg
447
ld
r3,ubgl
448
ld
r3,ubgh
449
ldw
rr2,dc
450
ld
r3,dcl
451
ld
r3,dch
452
ldw
rr2,syn
453
ld
r3 ,synh
454
ld
r3,synl
455
ld
r3 ,smd
456
ld
t:3 , SlllC
457
ld
r3,smb
458
ld
r3,sma
459
ldw
rr2,sbg
460
ld
r3,sbgl
461
ld
r3,sbgh
462
ldw rr2,cltc
4,63
ld
r3 ,cl tel
464
ld
r3,cltch
465
ldw
rr2,c0tc
466
ld
r3,c0tcl
467
ld
r3,c0tch
468
ld
r3,clm
469
ld
r3,c0m
470
471 ;upper case test
472
ld
r3,SYM
473
ld
r3 ,IMR
474
ld
r3,IRR
475
ldw
rr2, IP
476
ld
r3,IPL
477
ld
r3,IPH
478
ldw rr2,SP
479
ld
r3 ,SPL
480
ld
r3,SPH
481
ld
r3,RP1
482
ld
r3,RPO
483
ld
r3,FLAGS
484
ld
r3,P4
485
ld
r3,P3
486
ld
r3,P2
487
ld
r3,Pl
488
ld
r3,PO
489
490 Bank 0 Special Registers
491
492
ld
t"3,IPR
E-16
000003dl 38fe 000003d3 38fd 000003d5 38fc 000003d7 38fb 000003d9 38fa 000003db 38f9 000003dd 38f8 000003df 38f7 000003el 38f6 000003e3 38f5 000003e5 38f4 000003e7 38f1 000003e9 38dl 000003eb 38f0 000003ed 38ed 000003ef 38ec 000003fl 38eb 000003f3 38ea 000003f5 38e9 000003£7 38e8 000003£9 38e7 000003fb 38e6 000003fd c4e4c2 00000400 38e5 00000402 38e4 00000404 c4e2 c2 00000407 38e3 00000409 38e2 0000040b 38el 0000040d 38e0
0000040f 38ff 00000411 38fe 00000413 38fb 00000415 38fa 00000417 c4f8c2 000004la 38f9 000004lc 38f8 000004le .c4f0c2 00000421 38fl 00000423 38f0 00000425 c4eec2 00000428 38ef 0000042a 38ee 0000042c 38ed 0000042e 38ec 00000430 38eb 00000432 38ea 00000434 c4e8c2 00000437 38e9 00000439 38e8 0000043b c4e4c2 0000043e 38e5
493
ld
r3,EMT
494
ld
r3,P2BIP
495
ld
r3,P2AIP
496
ld
r3,P2DM
497
ld
r3,P2CM
498
ld
r3,P2BM
499
ld
r3,P2AM
500
ld
r3,P40D
501
ld
r3,P4D
502
ld
r3,HlC
503
ld
r3,HOC
504
ld
r3,PM
505
ld
r3,Pl
506
ld
r3,POM
507
ld
r3,UIE
508
ld
r3,URC
509
ld
r3,UTC
510
ld
r3,SIO
511
ld
r3,SIE
512
ld
r3,SRCB
513
ld
r3,SRCA
514
ld
r3,STC
515
ldw
rr2,ClC
516
ld
r3,ClCL
517
ld
r3 ,ClCH
518
ldw rr2,COC
519
ld
r3,COCL
520
ld
r3,COCH
521
ld
r3,ClCT
522
ld
r3,COCT
523
524 Bank 1 Special Registers
525
526
ld
r3,WUMSK
527
ld
r3,WUMCH
528
ld
r3,UMB
529
ld
r3,UMA
530
ldw rr2,UBG
531
ld
r3,UBGL
532
ld
r3,UBGH
533
ldw rr2,DC
534
ld
r3,DCL
535
ld
r3,DCH
536
ldw
rr2,SYN
537
ld
r3,SYNH
.538
ld
r3,SYNL
539
ld
r3,SMD
540
ld
r3,SMC
541
ld
r3,SMB
542
ld
r3,SMA
543
ldw
rr2,SBG
544
ld
r3,SBGL
545
ld
r3,SBGH
546
ldw rr2,ClTC
547
ld
r3 ,ClTCL
E-17
Appendix E
Appendix E
00000440 38e4 00000442 c4e2c2 00000445 38e3 00000447 38e2 00000449 38el 0000044b 38e0
0000044d Od0080
00000450 6d0080 00000453 ed0080 00000456 6d0080 00000459 ed0080
0000045c 7d0080 0000045f fd0080
00000462 ad0080 00000465 ld0080 00000468 9d0080 0000046 b 2d0080
0000046e dd0080 00000471 5d0080
00000474 cd0080 000004 77 4d0080
0000047a bd0080 0000047d 7d0080 00000480 fd0080 00000483 3d0080
548
ld
r3,ClTCH
549
ldw
rr2,COTC
550
ld
r3,COTCL
551
ld
r3,COTCH
552
ld
r3,ClM
553
ld
r3,COM
554
555 ; test for condition codes
556
557
jp
f ,128
558
559
jp
z,128
560
jp
nz,128
561
jp
eq,128
562
jp
ne,128
563
564
jp
c,128
565
jp
nc,128
566
567
jp
gt,128
568
jp
lt,128
569
jp
ge,128
570
jp
le,128
571
572
jp
pl,128
573
jp
mi,128
574
575
jp
nov,128
576
jp
ov,128
577
578
jp
ugt,128
579
jp
ult,128
580
jp
uge, 128
581
jp
ule,128
582
E-18
~2.iLCE
USER'S GUIDE
DI
ZILOG
UNIVERSAL OBJECT FILE UTILITIES
Rel·t·d Docu·enta
Kernighan, Brian w. ana Ritchie, Dennis M. !bi k ft¥~CAmm~US
L~ogw1g1. Engle~ood Cliffs, NJ: ?rentic·-H~ll1 1978.
IEEE Standard 695-1985. "The Microprocessor Universal Format for Object Modules."
Trade··rk Ackno·ledge·enta
UNIX is a trademark of AT&T Sell Laboratories; Zilog is licensed by AT&T Technologie3, Inc.
Copyright 1985, 1986 by Zilog1 Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electron~c, mechanical, photocopying, recording, or otherwise, without the prior ~ritten permission of Zilog. The information contained herein is subject to change without notice. Zilog assumes no responsibility for the use of any circuitry other than circuitry embodied in a Zilog product. No other circuit patent licenses are implied. All specifications (parameters) are subject to change without notice. The applicable Zilog test documentation will specify ~hich parameters are tasted.
Zilog does not support the software mentioned in this pubfication, use at own risk.
Zilo~ Object File Utilities
ZILOG UNIVERSAL OBJECT FILE UTILITIES USER'S GUIDE TABLE OF CONTENTS
ZS' MICROCONTROLLERS
USER'S MANUAL
CHAPTER TITLE AND SUBSECTIONS
PAGE
CHAPTER 1: INTRODUCTION 1.1 Overview ................................................................................................................................. 1-1 1.2 Utilities Description ................................................................................................................. 1-2 1.3 Utility Invocation ...................................................................................................................... 1-6
CHAPTER 2: MCONV 2.1 Introduction .............................................................................................................................2-1 2.2 Command Syntax and Options ...............................................................................................2-1
CHAPTER 3: MDUMP 3.1 Introduction .............................................................................................................................3-1 3.2 Command Syntax and Options ...............................................................................................3-1 3.3 Display Formats and Examples ..............................................................................................3-2
CHAPTER 4: MLIB 4.1 Introduction .............................................................................................................................4-1 4.2 Command Syntax and Options ...............................................................................................4-1 4.3 Examples .................................................................................................................................4-2
ID
CHAPTER 5: MLINK 5.1 Introduction .............................................................................................................................5-1 5.2 Command Line Syntax and Options ...................................................................................... 5-4 5.3 Constraints ............................................................................................................................5-13 5.4 Using MUNK: Some Examples .............................................................................................5-14
CHAPTER 6: MLIST 6.1 Introduction .............................................................................................................................6-1 6.2 Command Syntax and Options ...............................................................................................6-1 6.3 USAGE, OUTPUT FORMAT AND ExAMPLES ......................................................................................... 6-1
CHAPTER 7: MLIST 7.1 Introduction ........................·..................................................................................................... 7-1 7.2 Command Syntax and Options ...............................................................................................7-1 7.3 Operation ................................................................................................................................ 7-2 7.4 Using MLOAD: Some Examples ............................................................................................ 7-3
CHAPTER 8: MLORDER 8.1 Introduction .............................................................................................................................8-1 8.2 Command Syntax and Options ...............................................................................................8-1
't'2H..cE
CHAPTER TITLE AND SUBSECTIONS
"lJ' MICROCONTROLLERS
USER'S MANUAL
PAGE
CHAPTER 9: MMM 9.1 Introduction .............................................................................................................................9-1 9.2 Command Syntax and Options ...............................................................................................9-1 9.3 Output Format and Examples .................................................................................................9-1
CHAPTER 10: PROTOCOL 10.1 Introduction ......................................................................................................................... 10-1 10.2 Command Syntax and Options ........................................................................................... 10-1 10.3 Using PROTOCOL: Some Examples .................................................................................. 10-2
CHAPTER 11: OTHER PROGRAMS 11.1 MAR .................................................................................................................................... 11-1 11.2M2A ..................................................................................................................................... 11-1 11.3 MU IMAGE ........................................................................................................................... 11-2
APPENDICES
Appendix A. MUFOM File Format ............................................................................................... A-1 Appendix 8. Tektronix Hex Format .............................................................................................. 8-1 Appendix C. Intel Hex Format ..................................................................................................... C-1 Appendix D. Error Messages ...................................................................................................... D-1
Glossary ....................................................................................................................................... G-1
ii
Chapter 1 INTRODUCTION
1.1. OVERVIEW
1.1.1. Product Overvi··
Th& Univarsal Objact File Utilities are part of Zilog's ~UFCM-output cross-software family. The utilities allow the programmer to combine, display, and load ~·chine-language object modules. Tha utilities are universai because they can process object modules produced by any of Zilog's MUFOM-outout cross-asse~blers.
MUFCM is an acronym tor Microprocessor Universal Format for Object ~odules. MUFOM was developed by the IE!E as a format for representing machine-language object modules for any microprocessor. By using the MUFOM object format, Zilog supports all its assemblers (and compilers) using only one set of programs, the Universal Object Fil· Utilities.
This manual provides the following information:
0
A brief description of the program's features.
0
A complete definition of the command line syntax.
0
A complete definition of th· utilities· functions.
0
Tutorials for the more complex portions of the utili-
ties.
0
A complete definition of th· input file format.
0
A complete definition of the output file for:11at.
Section 1.2 briefly gescribes the utilities and their uses,
and Section 1.3 describes how to invoka the utilities and
/
the general co~mand line syntax.
C~apters 2 through 10 discuss each utility in turn. within e~ch cha~ter com~and syntax, fe~tura descriptions, and examoles are provided. Chapter 11 describes thrae special· purpos· programs which are ~lso supplie~ with the utilities.
Appendix A provioes · discussion of ar.d specifications for
1-1
Zilo; Object File utilities
INTRODUCTION
Chapter 1
the MUFOM objact file format. Appendices 8 and C discuss the Tektronix Hex for~at and Intel Hex format, respectively. Appendix ~ lists the error mess·ges.
Appendix E is the glossary. You do not need to understend the HUFC~ object-file format to use these utilities. There are1 however, a number of terms used when discussing MUFO~ products that you should understand. These terms ·re defined in Appendix ;. It is sug;ested that you familiarize yourself with these terms before continuing with the rest of this User·s Guide.
1.2. UTILITIES DESCRIPTION
This section presents a brief description of each utility
and its usage. Figure 1-1 sho·s how the utilities fit into
the software development process.
1.2.1. ·conv
m·2ai is en object for··t converter. It converts object
modules from HUFOM ASCII format to MUFOM binary format and vice versa.
mgwm; is the object code dumoer. It displays information
about an object module, its sections, and its load data in human-re·dable form.
1.2.3. mllb
mliR is the object-code library maintenance utility. It
allo·s object files to be combined into libraries ~hich can be automatically searched by mliD~·
~lie~ is a relocating linker. It accepts an arbitrary nu·ber of input files (limited only by available memory),
resolves external references between files1 co~bines file sections, and locates sections at absolute addresses. mliD~
also generates relocatable output modules which can be re-
linked later.
Zilo~ Object Fil· Utilities
1-2
l~TRODUCTION
Chapter 1
INTROOUCTIO~
1.2.s. ·list
mli11 is the objact code lister. It reconstructs an
assembler-like listing from an object ~odule, using special comments which are optionally inserted in the object module by the assembler.
1.2.6. ·load
m191d is a download for~at converter that translates MUFOM-
format object modules into a form suitable for transmission (downloading) to development modules, emulators, or ?ROM progra,mers. The outout formats suoported are Tektronix Hex, Intel Hex, and a si,plified form of ~UFOH. ml2i~ is
intended to be used with ;ce1e,g1 or · similar communication
program.
Ix mlorder examines a set of object files to d·t·r~ine the optimum ordering for them in a library file, ~hich can then
be constructed using mliR·
1.2.a. ·n·
m~m is the object module s1mbol lister. It displays information about the symbols within an object module.
1.2.9. protocol
;cgSg,gl is a communication utility for transmitting files
(typically load modules generatad by mload) from a development host system to a target syste~ (downloading) or vice versa (uploading). It supports a variety of handshakes to provide reliable transmission.
Three other programs are supplied with the Object File Utilities; they are intended for rather specialized purposes and ·ill not b· needed by most users.
miC is an older v·rsio~ of mli~, producing an IC£bi~i file ~hich is compatible with the previous release of mlit~·
1-3
Zilog Cbject File Utilities
INTROOUCTION
Chapter 1
I lllTRO OUC TION
1.2.10.2. .2.
mli converts MUFOM files to l·iWl form, the ~bject fila for-
mat used on Zilog·s S8000 microcomputers. This is provided for users of Zilog·s EMS-8000 emulators, ·hich use that format for downlo·ding.
1.2.10.3. ·ui··l··c mwiml~l·G is a MUFOM loader provided in IQWC'I form for user customization.
Zilo~ Object File Utilities
1-4
INTRODUCTION
Chaptei- 1
INTRO:JUCT ION
m
Figure 1-1. The Universal Object Fil· Utilities in tha Soft··re Development Process
1-5
Zilog Object File Utilities
INHO::IUCTION
Chapter 1
INTROiJUCTICN
1.3. UTILITY INVOCATION
This section describes the invocation of the ocject file utiliti·s. The syr.tectic notatians used in this section and throughout the r·st of the manual are described below.
1.3.1. Syntactic Notation.
CitnJ Square brackets indicate that the item is optional.
itern1 I item2
A vertical bar inoicates that either of th· two items can be provided.
... item Three periods indicate that there can be one or more occurrences of the preceding item.
ite111 · An asterisk indicates that there can be zero or more occurr·nces of the preceding item.
N
N stands for a oecimal number.
rt
~ stands for a hexadeci111al number.
Each utility is a separate program, invoked by usin~ its name as a com111and. Tha com~an~ name is foll~med by zero or more "arguments" separated by spaces; command ar;umants may be filena~es1 numbers, or so-called "options".
Command line syntax follows the U~IX· convention in which a ·-· sign followed by a one-character option identifier (with no intervening spaces> is parsed as an option <e.g., -o). 0Ptions can appear in any ord·r· Case is not significant in aption identifiers; they may b· uppercase or lowercase letters.
Some options may be followed by a n~mber or filename. A soace is QRliiDll between the option letter and the number ar filename, and ctgMiCI~ follo~ing i t .
· UNIX is a trade~ark of AT ~ T Bell laboratories; Zilog is licencea by AT&T Technologies, Inc.
Zilo~ Cbject File Utilities
1-6
INTROOUCT!CN
Chapter 1
INTRODUCTION
C~tion characters may be concatenated <e.g., two options,
such as -a ~nd -b, can be ~ritten as -ab), provided the
c-a first option
in this example) does not expect to be fol-
lowed by a number or f4lename.
For example, the command
illustrates most of these principles: Th~ -1 and -o options
are each follow·d by a filename (foo.o for ·1, foo for ·o.
The two single-character options -r and ·z are combined as -rz.
1-7
Zilo; Object File Utilities
Chapter Z
~CONY
2.1. INTRODUCTION The m'2DX utility is a filter that converts an object modula
from one format to another. MUFOM object files can be in either ASCII character or binary form. Object modules in binary form save space, while character form allows easy examination and reading by the user, and is ~ore useful for downloading over serial links.
2.2. COMMAND SYNTAX AND OPTIONS The m'2DX conversion utility is invoked by the following
command:
mconv [optionsj Cf ileJ
If no input file is specified, standard input is converted.
The command-line options are:
-b Convert the source to binary form.
-c Conve~t the source to character form; this is the default option.
-1 Retain local symbols in the output. If this option is not supplied, only global and external symbols will be listed.
-k N Retain ~UFOM comments up to level N in the output.
-o file Direct output to the given file rather than to standard output.
2-1
Zilo~ Object File Utilities
Chapter 3
~DUMP
3.1. INTRODUCTION
The ~d~mg utility is used to display MUFOM object coda in a user-friendly format. It accepts MUFOM obj~ct modules es input and can output four items of information: the object mooule header, the sec~ion tabla, the link ~ap, and the load data.
3.2. COMMAND SYNTAX ANO OPTIONS The command syntax tor this utility is as follows:
~dump (optionsJ (f ileJ If no file is specified, then the standard input will be dumped.
The command-line options are:
-h Display the header information. -1 Display the load data. -m Display the link map. -s Display th· section table.
If n~ne of -h, -1, -m, or -s is given, all information is
displ~yed.
-o file Direct output to the given file instead of standard output.
-k N ~rint the ~uFOM comments within the object mo~ula wit~ a level less than or eQual to N. S·~ Appendix A for a discussion of MuFCM comments.
3-1
Zilo; Object Fila Utilities
MOU MP
Chapter 3
Mu UMP
3.3. DISPLAY FORMATS AND EXAMPLES
This section describes the form~ts of the four items of
information in mgwmQ'I output. They may ba individually
selected for display by command-line options; by default all four items are output.
3.3.1. The Header
The first part of m~wm;'1 output is ~ haader containing general information about the module. The header information includes:
o
Module name
o
Tar;et processor
o
Character/ainary format
o
Address length ana byte order
o
Creation date and time
o
Absolute/Relocatable
o
Entry point
o
Program size Cin hex and decimal)
A typical module header is shown below:
Module: test; target ZSOK; character form.
Address length 4 bytes; MS8 first.
Created 1986/04/02 09:39:38.
= Entry point 00000001.
Total size =
e58 (3672); absolute.
3.3.2. Th· Section Table
Following the header, mdump lists a table of all the sections in the object module, as shown in the two examples below. Note that some fields may be blank if no values have been set for them. In particular, the LOCATION f iald is blank for relocatable sections.
Zilog Object Fila Utilities
3-2
MOU MP
Chapter 3
SECN LOCATION --SIZE-- --ALIGN- --PAGE-- f\AME:ATTS
D
00000d4c; 00000002
1
OOOOOG14 OG000002
sec1 _name:
2
COOOOCOa 00000002
sec2:XP
3
00000002 00000004
sec3:
4
OOOCOOCc COOOOOOc
cod·:X
5
00000006 00000002
data:
6
00000010 00000002
bss:!3C~
7 00001000 00000014 00000002
abs:A
8
OOOOOC02 00000002
com111: M
SECN LOCATION --SIZE-- --ALIGN- --PAGE-- NAME:ATTS
0 00000000 00000166 00000002 00010000 dlfoo:ANSW
1 00005000 0000092·
libcode:ANSX
2 00005000 00000060 00000002 00010000 code;ANSX
3 00005060 OOOOOOfO 00000002 00000000 Ccommon:ABNS!il
The SECN column displays the section number. Each section has a number associated with it that differentiates it from the other sections in the object module. The LOCATION column displays starting address Clower boundary) of the section. If the section is relocatable then the LOCATION column's entry will be blank. The SIZE column shows the size in hexadecimal of th· section. The ALIGN and PAGE columns show the alignment boundary and page size of the section, if defined.
The NAME:ATTS column shows th· name and attributes of the section, separated by a colon. See Section 5.2.2.4 in the chapter on mliD~ for a discussion of section attributes and their meanings.
3.3.3. The Link Nap
Object modules that are output by the linker, mliD~, contain information about the files and sections that were linked together to form them. This information is called the Lirk M~p, and is identical to that displayed by the -v option of
mho'1 ·
If no link map is present, mg~mR dis~lays the message
No link map information.
3-3
Zilo~ Object File Utilities
"40UMP
Ch&pte,. 3
An example of a link map is shown below:
LINK MAP: Input Sections
FILE test.o
c,.eated 1986/03/24 09:4C:3t
0
1 L=OOOOOOOo S=00000d4a t·st.o,:ANSW
1
s L=00000o7e S=OC000014 test.o,sec1_name:A~SW
2
4 L=00000a74 S=OOOOOOOa test.o,see2:APSX
3
6 L=00000d94 S=00000002 test.o,sec3:ANSW
4
3 LzOOOOOd6& S=OOOOOOOc test.o,code:ANSX
5
0 L=OOOOOOOO ssOOG00006 test.o,oata:ANSW
6
a L=000010bc: szoooooo10 test.o,bss:ABCNW
7
7 L=00001000 S=J0000014 test.o,abs:ANSh
8
8 L=00001014 S=OOOOOC02 test.o,comm:AMNW
FILE txxx.o
c,.eated 1985/10/31 14:53:08
0
2 L=00000d5C S=00000010 txxx.o,:ANSw
1
8 L=00001014 5=00000004 txxx.o,comm:AMNW
Note that the link map includes the name and c,.eation date of each fil· that was linked; if the file ceme f,.om a lib,.ary, the libr~,.Y name follo·s the f ilaname in parentheses.
The line fo,. each input file is followed by a line fo,. each section that the f il· contains; the first tmo columns are the input and output section numbers, respectively.
For relocatable sections, "L=" is replaced by "R=", and tha associat·d location is the offset of the input section within the (possibly larger) output section.
3.3.4. Th· Load Data
The Load Data is the data and code that will actually be load1d into the target ~achine·s memory.
The data is displayed in the format shown below:
Section number address: --------object code-------address: --------object code--------
ete.
!ASCII equivalent! IASCII equivalent!
The load data is broken up into lines fo,. display, each of which can show up to sixteen bytes of data. The display lines ar· aligned on modulo-16 byte boundaries with the address being the address of the first byte actually displayed. If the section is relocatable thin the address is relative to th· be;inning of the section. If the section is absolute, then the address is the actual position in
Zilog Object File Utilities
3-4
H OU"!P
Chapter 3
MOU HP
me·11ory.
Exc:111ple:
JOOOOOOO C0000010 OCCC002C 00000030
OOJ::l0040
JCO:l005J
Sil 83
OS
22
so
Se
S4 08
as1o
7e 4a
a 1 lib
6d eO
a 1
Ob
5 c Oc
Sd 00
c4
oc
s.
St
Oe C2
50
so
16 3c
20 eC Oa dO Se Oe SC 3c Oc ·4 Se Ce SC 34 33 22
·· Sa
20
08 d8
50 b1
4c:
oc
219 e3
ea 02
a9 Se
dO OS
Se 50
08 4a
50 Sc
16 f1
20
Oc:
02
bc1o
20
co
a9 f5 9e 06 ab 1S Sc: f9 Oc 02 OJ 00 5· 08 so 04
.I"
I
,O. T
PJ
'11
\
" I
P< A
I " OJ
A p
I
" ?J\
I
\
3.3.5. Disjoint Section·
It is important to note that the MUFOM for'11at allows the object code for a section to be broken UP into physicelly disjoint pieces. If pieces of sections are distributed ranaomly throughout the object module, mdu~p will not Ct able to display each section contiguously. Instead, mdump will display the pieces of the sections as it receives them fro111 the input file. The example below shows the load datE< of a module with two sections, eacn split into two pieces.
Section 0
00000000 61 62 63 f4
Section 1
OO:>OOOuO 30 32 33 34 !S
Section 0
00000004
65 66 67 68
Section 1
J:>OOOOOS
36 37 38 39
la1>cd 10234S
ef gh 5789
Sections can also contain gaps (c~usao by assembler state-
ments that reserve space without initi~lizing it>. Short ~aps pre reDresented by "······" within a sin;le line; lon; gaps by "····" in the address field, zs sho~n below:
........ 00000000 01 C2 C3 ··········· 04 OS 06
00000068
os o~
DI
3.3.6. Displaying Relocation Information
kithin ~UFOM reloeat~ble object cod~, raf erences to unresolved external sy~bols and to locc:tions in relocatable sections are represented as expressions. The for~ats usea
3-5
Zilo; Cbject Fil· Utilities
MOU MP
Chapter 3
for displaying expressions ·r· showr below:
Rnn+offset Xnn+offset
**********
relocatable address external referance other expressions
The expressions are padded with periods to occupy the appropriate amount of space (three columns per byte). If ther~ is insufficient space for the whole expression, it is abbreviated to its first letter and paddeo with periods. The follo·ing example illustrates all three for~ats.
00000000 R1+1234 ···· X0+1234 ···· *··········
If necessary, more detail about an expression can be
obt2ined by running mlill, which can expand expressions com-
pletely.
7iloo Ob;·ct ~ila Utilities
3-6
Chapter 4 MLIB
4.1. INTRODUCTION
The mli~ utility is used for creating and maintaining libraries of object modules for use with mliD~· lib~aries are stored in a for~ that permits efficient searching and linking of the modules they contain.
4.2. COMMAND SYNTAX AND OPTIONS
The ~li~ conversion utility is invoked by the followir.g command:
mlib key lfile CnameJ ···
~I~ is one character from the set udrtQxf" optionally fol-
lowed by "v". lfilt is the library file; the Dimts are the
constituent files in the library.
Note that a "keyu is not an "option"; it has no leading "-" character. The meanings of the key characters are:
d Delete the named files from th· library file.
r
Replace the named files in the library file.
Q
Cuickly append the na~ed files to the end of the
library file, without checking whether they are ~lready
in the library.
t
Print a table of contents of the library file. If no
names are given, all files in the library are tabled.
x Extract the named files from the library. If no names are given, all files· in th· library are extracted. The library file itself is not altered. The extracted files are put into the current working directory.
v
Verbose. Gives more inf or~ation -about what mlib is
doing. With J this includes ~ list~n~ of the symbols
in each module as well as th9 names of the mo~ul9s.
f
The f~rst and only "name" in the co~mand line is the
name of a file which contains the list of filenames.
4-1
Zilog Object File Utilities
~LIB
Chapter 4
MLIB
4.3. EXAMPLES
To combine several files (say, "file1.0"1 "fileZ.o" and "file3.o"> into a library, us· the command:
mlib q too.lib file1.o file2.o file3.o
If one of the files is modified, it can be replaced with the command:
mlib r foo.lib fileZ.o
To ~dd another file to the library, use mlib q foo.l1b file4.o
To find out what is in the library, use ~lib t foo.lib
To break the library into separate files, use the command
mlib x too.lib Note that the library file is unaffected by this operation. A single file can be extracted with the command
mlib x too.lib file2.o
If a filename containin~ a list of files, say "bar", has
been prepared (for example as the output of tliCQIC), we can
use it to create a library with the eo~mand
mlib qf bar.lib bar
Zilog Object File Utilities
4-2
Chapter 5 MLINK
S.1. INTRODUCTION
The ~liD~ utility is used to assign absolute addresses to relocatable sections in MUFOM input modules, and to combine (link) t~o or more separate object modules into one moGule. Linking allows programs to be developed as groups of smaller, easier-to-manage modules that can then be combined to form a single object module. All of a program's modules can be merged at one time or they can be combined into submodules (sometimes called ore-links) which can themselves be combined in a subse~uent mliD~ run.
5.1.1. Modules And Sections
In order to understand the linkin; process, it is useful to understand the way in which MUFOM files are constructed. {The following discussion is a shortened version of that found in Sections A.2 and A.3 of the Appendix on MUFOM. See the Appendix for more detail.> MUFOM object files are aivided into Ji,1lQDi each of which is destined to be loaded into a separate area of memory. Each section has a Qi~I' a Jiit, 111Ci~W111, and (if not relocatable> a lQ,11120· Each section also has a li,liQD DY~QIC which is used to refer to it internally. In Zilog's implementation these section numbers correspond to the order of the sections in the section table. CSee Section A.2 in th· Appendix on ~UFOM for a discussion of the various section attributes and their meanings.>
It is important to note that the name of a section may be null Cin which case the section is referred to as "unnamed"), and that the names of sections Diid DQl bi woigYi· Thus, a file may contain several sections named "code". Th· advanta~e of this is that the linker can relocate such sections separately; thus on a Z8001 not all "code" sections have to b· in the same segment.
Sections can be referenced in the linker by either their na~e, their attributes, or the name of the file from which they ceme.
MUFOM object files as implemented at Zilog are divided into three regions: a li·l~QD ll~lt giving all information about th· file 1 s sections except their actual contents, ~ i~~~21
li~li which defines the N, r, and X variables which
S-1
Zilog Object File Utilities
ML INK
Chapter 5
MLIN~
represent local, internel, and external sy~bols respectively, and finally the 121~ ~ili' the ~O and LR commands which define the actual contents of the sections. These regions are delimited by special MUFOM comment commands; separating them in this way makes the linker and other utilities run faster.
As impl···nted at Zilog, the N, 1, and X variables of any object file are allocated contiguously starting fro~ NO, IO, and XO. The variable indexes do Q9l' however, necessarily correspond to the order of the variables in the symbol table. It is only guaranteed that there will be no gaps in the numbering.
MUFOM permits comments CCO commands) in object files; Zilog's assemblers use level C comments for error messages, level 1 comments for compiler-supplied debugging information, level 2 comments for assembler source lines, and level 3 for asse·bler line numbers and formatting infor~ation. This permits debuggers and other utilities (such as ~li1l> to reconstruct the source from the object file.
The co~ments that introduce the section table, symbol table, and section contents have levels 100Chex), 1011 and 102 respectively.
5.1.2. The Link Process
The command arguments are parsed from left to right. argument is essentially a command to the linker.
Each
Th· linker ~aintains two lists of sections: the Inout List
and the Output List. The -1 fil···· command-line argument
;ets sections from input fil·s and puts them into the Input List. As each file is input, its section table is processed
to construct entries on th· Input List, and its symbol table
is processed to resolve external references.
The -· command-line !rgument selects sections from the Input List and puts them into the Output List at the Current Location. As each section is select·d it is assigned a starting loe~tion, ano the Current Location is incremented by the length of the section*.
;--T~i~;;--;~;--;~t~;ii;--. little ·ore complicated; assignment of location is deferred until either a -n or -o option is encountered. This is done to allow the -u option to "unselect" sactions. Also, if an absolute section is encountered, the Current Location for the next section mill be the location of the absolute section Plus its size.
Zilog Object File Utilities
5-2
ML INK
Chapter 5
ML INK
The -o file commend-line argument appends the sections in the Output List to · file. The output list is then cleared. hhen the code or data contained ~n a section is output to a file, the values of external or relocatable references end link-time expressions are substituted.
All other arguments operate on the Output List or the Symbol Table.
After the command line is parsed, the linker mak·s two passes over the input files. In the first pass, the symbol and section information in each input file is read and pro· cessed, end en Output List is constructed for each output file. kith each ·o argument, locations are assigned to relocatable sections.
At the end of the first pass, any remaining sections are put on the Output List of the last file mentioned, locations are assign·d to com·on symbols, and still-undefined externals are identified.
In the second pass th· output files are written. For each output file, symbols and program data are copied from the input files. Link-time expressions (including relocation> and external references are replaced by their values during the copying process.
S-3
Zilo~ Object Fil· Utilities
MLINK
Chapter- 5
MLINK
5.2. COMMAND LINE SYNTAX AND OPTIONS
Th· command-line options for- mlia~ ar-e given beloL in Table S-1. More complete discussions of each option ar-e given ~n the followin~ sections.
The command line is processed from left to r-i~hti each option with its sub-arguments is essentially a co~nand to the linker. Unlike most of the other utilities, the or-der
of the command-line ar-guments is significant in mliDk·
Option
Description
Input and Output Fila Cptions
-1 CifileJ·
specify input files
-o [ofileJ Cisectionl* specify output file
Section Options
-s [isectionJ·
-n CosectionJ -address -t address -r -m N -u CisectionJ·
select input sections name and combine sections set location for next section set top loc. for- previous sect. relocatable sections follow mark loc./return to mar-k unselect sections
Output Fila Options
-b -c -k N
binary format output character format output keep comments in output
Symbol Options
-1 -d -x Csym_opJ*
-·-~ Csy111_opl* CvalueJ
Other Options
discard local sy~bols define C com~on symbols process external symbols process ~lobal sy~bols specify entry point
-p
-v l:Nj
-111
-z -f file
proceed even if errors
set v~r-bosity leval suppress 111a~nings Z8000 segments command file input
Zilo~ Objact File Utilities
5-4
MLIN(
Chapter 5
~LINK
S.2.1. Input and Output file Options
The Input and Output options specify the input and output files for the link operation. If no output files are specified, output goes by default to "m.out". Note that more than one output file can be specified.
If no input files are specified, ~lie~ will generate an output file containing no load data. This ca~ be useful if the symbol options are used to define symbols. Also, the section options can be used to create e~pty sections with specified names, attributes, and locations.
S.2.1.1. File Option Syntax
file_opt
::= -1 [ifile)*
-o [ofileJ (isectionJ·
ifil· ofile
::= object_filename I archive_filenam· ::= object_filename
S.2.1.2. File Option Descriptions
-i [ifile)· Input the specified files, putting their sections into the Input List. As each file is processed, its sections are placed into the Input List in numerical order.
A -i is assumed at the be;inning of the command, so the following are equivalent:
ml ink - i file1.o mlink file1.o
If · library file is specified, it is searched for modules containing global symbols that match undefined externals currently in the Symbol Table. If any such m~dules are found, they are added to the Input List.
If searching a library causes any new externals to be adaed to the symbol table, it is searched agsin.
-o (ofileJ [isectionJ· Appends the Output List to the ;iven file. !f no file is given, the sections in the Output List sre thro~n away (but space is still allocated for them). Note that more than one output file can be specifiedi this
5-5
Zilo~ Object File Utilities
ML INK
Chapter 5
MLIN~
feature can be used for loading into different segments or PROMs1 or for constructing overlays.
If section specifiers ara given, only those specified sections Cin addition to th· sections in the file's Output List) ar· included in the output file's section table. Filenames in the section specifiers refer to
QWiRWi files. This feature is used to ensure that
overlays do not reference sections in mutually exclusive overlays.
5.2.1.3. luto··tic Section Co·bining
So~e section attributes specify that sections are to be co~ bined automatic~lly in various ways. CS·· Section A.2.Z for the discussion of Overlap attributes and their effects.> Such sections are combined when they are first encountered in -1 (input) file lists, and only the sections in the current Input List are looked at to find sections to combine with. Thus, if a ·i option comes after some sections have been selected with a -· option, the sections that nave
already been selected ·ill QQi be co~binad with, even if
their names and attributes match those of some new sections. This provides a way to override the automatic sectioncombining ~·chanism.
5.2.2. Section Options
The section options allow you to specify explicitly how the sections input object modules are selected and positioned in the output modules. Sections in the input modules are kept in an internal structure called the Input List until selected by a -· (select) option. They are then moved to the Output List. Sections on the Output List are moved into an output file ·hen a -o (output) option is encountered.
Zilog Object Fil· Utilities
s-~
"llINK
Chapter 5
"!LINK
s.2.2.1. Section Option Syntax
see_opt
::= -s (isectionJ·
-n (oseetionJ -address
--,.t. address
-111 N
-u (isectionJ *
address isection osec:tion
::= digit (hexdioitJ·
::= (filaname1J(sec_nameJ[:att_matchJ
::= (sec_name](:attributesJ
att_match ::= att_Ql"OUp ::=
sec_name : :=
attributes ::=
(att_termJ [+att_termJ·
(letter I -letter] ··· symbol I +
letter*
S.2.2.z. Section Option De·eriptions
-s (iseetionl · Select sections from the Input List and put them into t~· Output List. They will be located starting at the Current Location, which is initially zero. Sections matching the first "isaction" in the select list will be put into the output list first; sections that match th· same "isection" will stay in tha same order that they had in tha Input List. The section selectors are described in more detail below.
If no sections are specified the entire Input List is selected, except for Postpone sections (sections with the "P" attribute.> If Postpone sections are selected in other cases, they are placed after all the other sections in the same selection.
-n (osection] Combines all tha sections currently in the Output List and gives them the given name (~nd attributes, if specified). If no section or ":attributes" is specified, the combined section is unnamed. If no attributes era specified, the new section has the default attributes C:WSN). No attributes are inherited from any of tha constituent sections.
-address Sets the Currant Location to the givan address.
DI
S-7
Zilo; Object Fila Utilities
ML INK
Chapter S
ML INK
-t eddress Adjusts the base address of the last section in the Output List Ci.a., the last section selected before the -t option> so that its top comes as close as possible to the given ~ddr·ss without violating its ali~nment constraint.
-r Any sections selected after the -r argument will be relocatable (until the next -address or -t argument).
If this is the first time the given ~ark number is
encountered, set that mark to the Current Location. Other·ise, set the Current Location to the value of the given mark. This argument is used for alioning overlays.
-u (section]* "Unselect" the given sections, moving them from the output list back into the input list. This can be used, for example, to select ·all but" a given section,
or to construct a "Postpone" section which will be out-
put later.
s.z.z.J. Section Selectors
A section selector as used in the -· option has three components: a filename, a section name, and an attribute-match specifier. Any of these may be omitted1 in ·hich case all sections matching the other components are selected (the limiting case is -· with no section selectors, which selects
tll sections in the Input List).
Th· format of a section selector is
Note that QQ IQl,ll ICI Qttm~11Jg between the fielas. Note also that the filename must not contain a comma (this is permitted only in UNlX1 and is rare in any case>.
File Name The f il· name component of a section selector refers to the input file from which the section came. It is terminated by a comma.
Section Name The section na~· component of a section refers to the
name of the section as given in a MUFOM ·st· command in
Zilog Object File Utilities
5-8
'llLINK
Ctu·pter S
MLINK
the input module from which it came. Sections can be un-named; such sections can be selected explicitly by
using ·+· as the section name component of a section
selector.
Attribute Match The attribut·-match component of a section refers to th· attributes ms 9iven in a MUFOM 'ST' command in the input module from ~hich it came. Secause sections have more than one ~ttribute, the attribute-match component can be rather complicated.
The attrib~te-match component of a section selector starts with a colon, and consists of zero or
more "terms" separated by ·+· signs. A section
matches th· attribute-match if it matches IDX 20!
of the fields. Thus, ·+· has the meaning of "log-
ical OR".
A term in an attribute-match consists of one or more letters Cease is not significant), each optionally preceded by a ·-· sign. If s letter is non-ne;ated in a term, the corresponding attribute
mMll QI QClllDl in a section in order for it to
match. If a letter is negated in a term, the
corresponding attribute mMll DQl QI QCl~IDl in a
section in order for it to match. Thus, letters <attributes) in a term are connected by "logical ANO", and ·-· has the meaning of "logical NOT".
Note that the attributes matched by a term may be a IM~lll of the att~ibutes which a section actually has.
See Section A.2 in th· Appendix on MUFO~ for a discussion of
th· various section attribut·s and their meanings.
At the end of the link, any sections still in the Input List are selected, and the Output List i5 appended to th· output list of the last file mentionea in a -o argument <as if the
·o argument had been moved to the end of the command). If
no -o argument is given, the default filename is m·lDk·
The sections are selected in the seQuence: co~e CX attribute), read-only data (R attribute), other non-SSS data, C
common and SSS Ca attribute). The default beh~vior is thus
eQuivalent to
5-9
Zilog Object File Utilities
Chapter 5
mlink -o m.lnk <actual arguments> -s :X :R :-a -d -s :B
5.2.3. Output Fil· Options
The following argu~ents apply to the next output. file, or to
the last output file if they fol lo· the last ·o \rgument.
5.2.3.1. Output file Option Syntax
ofile_opt
::= -b -e
-k N
5.2.3.2. Output file Option Descriptions
The folloming options apply to the output file specified by the next ·o argument, or if they follow the last ·o argument, to the last output file specified.
-b Put out the next output file in binary form.
-c
Put out the next output file in character form.
-k In the next output file, keep comments up to and including level N. To retain source information for
use with mliil' use ·k3.
5.2.4. Syabol Options
The symbol options operate on the symbol table which is ~en erated in the linking process. They allow new symbols to be defined, or sets of symbols to be excluded from the output symbol table.
5.2.4.1. Syabol Option Syntax
Zilo~ Object File Utilities
5-10
MlINK
Ch11pter 5
sy11_opt
symbol value sym_op
: : = -l -d -x l:sy~_opJ*
-·-g [sy11_opJ· CvalueJ
::= letter(letterldigitj*
: : = (symbol I address]
: : = sy111bol + sy11bol = + symbol (value) + sy11bol length
5.2.4.2. Sy·bol Option Descriptions
-1 Do not put local sy~bols in the next output file.
-d Cef ine a section for any common symbols encountered up to this point, and select it into the Output List. Co1111on sy11bols are used by the C compiler and other compilers to hold un-initialized data. The com11on section defined has the na11e "Ccom11on" and the attributes "BNSW.".
-x [sy11_opJ·
-g Csy11_opJ· Process external or global symbols. ·ith no sym_op·s given, the aefault operation is to strip the symbols
from 111 output files. "Stripped" symbols are not
actually removed from the internal sy~bol table, but are marked so that they will not be output. The operations are:
sy!llbol Strip a particular sy~bol.
+ symbol Add a particular symbol. Externals are added as undefined1 globals as zero.
= + symbol CvalueJ Add a symbol with the given value. If the valua is 011ittedl the Current Location is used. In the -x argument, a Weak External is constructed. A Weak External is an external sy~bol which receives the given value as a oefault if no corresponaing
Zilog Object File Utilities
ML INK
Chapter 5
MLINK
global symbol is defined in the link.
+ sy111bol length
Add a C·type Common symbol with the ;iven length.
Used in the -x argument only.
CvalueJ
-· Set the entry Point to the given velue (symbol or
address>. If no value is given, the default is th·
... Current Location. If no
argu!lant is given, the
default is th· entry point of the first input file that
has one. If no input file has an entry point, it is up
to the loader or operating system to def in· one.
5.2.5. Other Options
The follo·ing arguments are non·positionel, and apply to the entire link operation.
other.opt
-·::= ·p ·v [numberJ
-z
-f fih
5.2.5.2. Other Option Descriptions
-vCnJ "Verbose": print information on Standard Error about what th· linker is doing. The optional number selects
different levels of information:
1
(default> Output a link ~·P on Standard Error at
th· end of pas~ 1.
2 Output the name of each input and output file as it is opened.
3 Output information about each section as it is defined or selected.
4
Output more information about input file format
errors.
-o Proceed in spite of errors.
Zilo; Object File Utilities
s-12
ML INK
Chapter 5
ML INK
-w Suppress warr.in; ··ssages.
-z Perform ZS001-type segmented address arithmetic. With this option in effect, the next address after 100FFFF hex is 2000000; in other words bits 16-23 are not part of the address.
-f file Take arguments fro~ a file. Newlines in the file are treated as spaces. The file is effectively inserted into the command line in place of th· -f ar~ument. The file can contain comments starting with a semicolon
en;·) character and termin·t·d by end of line.
5.3. CONSTRAINTS
All of mliak·1 tables are dynamically allocated, so that the
number of symbols, sections, and files that can be handled depends mainly on th· a~ount of memory available. In addition, Zilog·s implementation of MUFOM imposes the following limits:
Symbol and Section Names: 127 characters. Sections: 6SS36. Local Symbols: 65536. Global and External Symbols: 65536 total.
5-13
Zilog Object File Utilities
l4LINK.
Chapter 5
ML INK
5.4. USING ·link: SOME EXAMPLES
This section describes the usage of the mliD~ utility through several examples.
5.4.1. The S··Pl· Input Files
For the purposes of most of the following axamples1 we will use two input files called "file1.o" and "file2.o" with a structure similar to that produced by th· C compiler. ;ach has three sections, called "code", "date", and "bss". ("bss" stands for "Block Started by ~ymbol"1 and is used for uni"itialized data that is cleared to zero when the progra~ is started.>
In addition, we will assume that "file1.o" contains a section called "rom" containing read-only data, that "file2.o" has an additional section called "stack" for the program's stack1 and that both files contain some ~Qmm~D sy~bols. (Common sy~bols are external symbols which are allocated in a BSS section if no corresponding global symbol is defined. They ar· used by C for uninitialized variables.)
The sections of the sanple input files are shown below in
tabular form (prepared by mgwm;), and graphically in Figure
s-1.
file1:
SECN LOCATION --SIU-- --ALIGN- --PAGE-- NAME:ATTS
0
00000242 00000002
code:X
1
00000231 00000002
rom:R
2
00000232 00000002
data:
3
COOOC20C 00000002
bss:SCW
file2:
SECN LOCATION --SIZE-- --ALIGN- --PAGE-- NA:'1E:ATTS
0
G0000242 00000002
code:X
1
00000234 00000002
di!lta:
2
00000200 00000002
bss:SCW
3
00002000 00000002
stack:SP
Zilo; Object File Utilities
S-14
MLlNK
Chapter 5
MLINK
file1 .o:
·-----f-il-e-1-.-0-1-c-o-d-e-:-X------·I +----f-i-le--1-.-o-,r-o--m-:-R-------+I +----f-i-l-e-1-.0--1-d-a-t-a-:-W------+I +-----------------------+
file1.01bss:wac
*-----------------------·
·-f-i-le-2--.-o-:----------------·
I
file2.o,code:X
+I ----f-i-l-a-2-.-o-,-d-a-t-a-:-w------+I
+----f-i-le-2-.-0-1-b-s-s-:-W--B-C-----+I
+I ----f-i-l-e-i.-o-,-s-t-a-c-k-:-W--B--P--+I
*-----------------------·
Figure 5-1. Example Input Files
5.4.2. Default Seetion Ordering
The simplest thing to do with our two sample files is to let the linker select sections in their default ordering, and locate them consecutively starting at zero. The linker·s defaults are designed to "do the ri~ht thing" for C compiler output running in an environment like UNIX·. Thus1 code (sections marked 11!,Yll~lt uith the "X" attribute) is placed startir~ at address zero1 follo··d by read-only deta ("R" attribute), read-·rite initialized date (flh" attrioute), SSS ("W" and "B" attr1outes)1 and stack (flW", "8"1 "P" attributes). The command for doirg this is
mlink -i file1.o fila2.o -o ex1
where ex1 is the name of the file which will receive the
linker·s output. ~ote that the -1 option flag is not reQuired, since it comes at th· beginning of the command1 ana that 1f the -o link·d.out option is omitted the output file will be called "m.lnk".
The resultin~ file·s structure is shown below and in Fi~ure
s-2.
Note th~t tha t~o SSS sections have been combined automatically, because thet have the "C" attribute. Sections with this att~ibute rre automatically combined if thair namas and
5-15
Zilog Object File Utilities
MLINK
Chaptel" 5
MLINK
other attl"ibutes are the same. Also note that the section
"Ccoemon" has been created to hold the ;ammaa symbols, and
that the linker has filled in the default se:tion attributes
"W" C"~ritabl·"), "N" <"no·", the inverse of "P"> and "S"
("separate", the inverse of "C"> wherever appropriate. Since the linker has given each section a location, they
have also acquired the "A" <"absolute") attribute as well.
mlink -i file1.o file2.o -o ex1 ·v
mlir.k v. 2.1 ·- Zilog MUFOM linking utility
MAP: I Seen CSecn Location Size
IFile,Na111e:Atts
Output file ex1:
0 0 L·OOOOOOOO S=-00000242 file1.o,code:ANSX
0 1 L=00000242 S·00000242 filez.o,:ode:ANSX
1 2 L·00000484 S·00000231 file1.01ro11:ANRS
2 3 L=000006b6 S=COOOC232 file1.o,d·ta:AhSW
1
4 s
1.=00000S.8 L=00000b1c
5=00000234 S=00000032
file2.01data:ANSW ,ccom11on:A8NSW
6 L·00000b4e S=O::J000400 ,bss:ABCNW
3 7 L=00000f 4e S=00002000 fil·2.orstack:A&PSW
Input files: 0 1 2 3 0
1
2 3
0 1.=00000000 5=00000242 file1.01code:ANSX 2 L=00u00484 S=C0000231 f ile1. o,rom: ANR S 3 L·00u006b6 S=C0000232 file1.o,data:A~SW 6 L=COOOObh S=000002CO file1.01bss:ABC~W 1 L=00000242 S=00000242 filez.o,code:ANSX
4 L·COOOOS.8 S=00000234 file2.01d·ta:ANSW
6 L=OOCOOd4· S·000002CO ~il·2.o,bss:ABCNW 7 L=00000f4e S=C0002000 file2.o,sta=k:ASPS~
Zilog Object File ~tilities
5-16
MLINK
Chiipter 5
NI.INK
file ex1:
·I-----f-il-e-1-.-0-1-c-o-d-e-:-X------· +I ----f-i-le--2-.0--1-c-o-d-e--:X------+ +----f-i-l-e-1-.-o-,-ro--m--:R-------+I +----f-i-l-e-1-.-0-1-d-a--ta-:-w------+I +-----------------------+ +--C-c-o-1-1m--on-:-W-B------------+ +--b-s-s-:-W-IS-C---------------+
file1.01bss:lii8C file2.01bss:wac
+-----------------------+
·-----------------------·
Figure 5-2. Default Selection Ordering
The -v command-line option of mliD~ ·as used to generate th· link ··P above; not· that its format is slightly different from the information displayed by IQWIR· More information ·bout ·h·t mlia~ is doing can be displayed with the ·v3 option, as shown below:
l1I
5-17
Zilog Object Fil· Utilities
ML INK
Ch11pter 5
MLINK
mlink -i file1.o file2.o -o ex1 -v3
11lirk v. 2.1 -- Zilog MUFOM linking utility Input file 'file1.o" 0 - R=OOQOOOOO S=00000242 fih1.01code:NSX 1 - R=OOOOOOOO S=00000231 f ile1. 01ro111:NRS 2 - R=COOCOOOO S·00000232 file1.01clata:NSW
3 - R=OOOCOOOO S=00000200 file1.01bss:BCNW In1>ut file "filez.o·
0 - R=OOOOOOOO $=00000242 file2.01code:NSX 1 - R=OOOOOOOO S·00000234 file2. 01dat..:NSW 2 - R·C0000200 S=C0000200 file2.01bss:8CNW 3 - R=COOOOCOO S·OOOOZOOO file2.01stack:6PSW Select :X 0 · R·COCOOOOO S=00000242 fih1. 01cocie:NSX 0 - R·OOOOOOOO 5=00000242 file2.01coae:NSX Select :R 1 - R·OOOOOOOO S=CC000231 f ih1. 01ro11: NRS Select :·B 2 · R=OOCOOOOC $=00000232 file1.01data:NSW 1 - R·OOOOOOOO S=OOC00234 file2.01data:NSW Select
- R·OOOOOOOO S·C0000400 1bss:8CNW 3 - R=OOOOOOOO S=CC002000 file2.01stack:8PSW
IOP: ISecn OSecn Location Size
IFile1Name:"tts
Output file ex1:
0 0 L=OOOOOOOO S·00000242 file1.01code:ANSX
0 1 L:z00000242 S=00000242 file2.01code:ANSX
1 2 L:z00000484 S=00000231 file1·01rom:ANRS
2 1
3 4
.L..=. c0o0o00o0o6sb.s6
S=00000232 S=00000234
file1.01data:ANSW file2.01datg:ANSW
S L=00000b1c S=C0000032 , Cco:a11 on: A8NSW
6 L=00000b4e S=0000040C 1bss :A8CNW
3 7 L=COOOOf h S·00002000 file2.01stack:ABPSW
Input files:
0
0 L·OOOOCOOO S=00000242 file1.~1code:ANSX
1 2 L=000004S4 5=00000231 file1.01ro11:ANRS
2 3 L·000006b6 S·00000232 file1.01data:ANSW
3 6 L..Oil000b4e S·00000200 file1.01bss:ABCNW
0 1 L·00000242 S=COC00242 fileZ.01code:ANSX
1 4 L=OOOCOS.8 S·00000234 file2.01data:ANSW
2 6 L=OOOOOdh S=00000200 file2.01bss:ABCNW
3 7 L·C0000f4e s.. 00002ooc file2.01stack:ABPSW
Output file ·ex1 ·
Input file ·tile1.o"
-- Input file "file2.o·
Zilov Object File Utilities
5-18
MLINK
Chapter 5
MLINK
5.4.3. Selecting Sections by N···
Sometimes it is necessary to put the s·ctions of th· output 1ile in some order other th·n 1lin~'s default ordering. (This is usually done in order to specify th· addr·sses of the sections, as ·· will s·· in later examples, but is also useful for constructing large tables fro~ data in several different modules.> Sections can be selected according to their name, their attributes, or their file of origin, or any combination of these.
The first exa~ple in this series will select sections by name, sine· th· command line for doing this is somewhat simpler. For example, su~pose you want the data sections to
come first, followed by ROM, and then code1 sss, and steck
in their usual order. The command for this and the resulting map are sho·n below.
mlink -i file1.o file2.o -s data rom -o ex2 -v
~link v. 2.1 -- Zilog MUFOM linking utility
~AP: I5ecn OSecn Location Size
IFile1Name:Atts
Output file ex2:
2 0 L=OOOOOOOO S=OC000232 file1.01data:ANSW
1 1 L=C0000232 S=00000234 file2.01data:ANSW
1
2 L=00000466 5=00000231 file1.01rom:A~RS
0 3 L=00000698 5=00000242 file1.01code:ANSX
0 4 L=OCCCOSda S=00000242 file2.01code:ANSX
S L=00000b1c S=00000032 ,ccoramon:AoNSW
6 L=00000b4e S=00000400 1bss:ABCNW
3 7 L=00000f4e S=00002000 file2.o,stack:ABPSW
Input files: 0 1 2 3 0 1 2 3
3 L=00000698 S=CC000242 file1.01coda:ANSX
2 L=Ci0000466 S=C0000231 file1.o,rom:ANRS 0 L·OOOOOOOO S=OOQ00232 file1.01data:ANSW 6 L=Ci000Cb4e S=OC000200 fila1.01bss:ABCNW 4 L=0000;)8cta 5=00000242 file2.01coda:ANSX 1 L=COCOC232 S=C0000234 fila2.01data:ANSW 6 L=COC0Cid4e S=COC002CO file2.01bss:ABCNw
7 L:00000f4e S=00002000 file2.o,stack:ABPSW
S-19
Ziloi Object Fila Utilities
ML INK
ML INK
file ex2:
·I-----f-il-e-1-.-0-1-d-a-t-·-:W -------· +I ----f-i-l-e-2-.-0-1-d-·-t-a-:-W------+ +-----------------------+
+I ----f-i-l-e-1-.0--1-c-o-d-e--:X------+I
+-----f1-l-e-2-.~0-1-c-o-d-e-:-X------+I
+--C-c-o-m-m--o-n-:k-B------------+I
+--b-s-s-:-w-a-c---------------+I
file1.o,bss:k6C
I
file2.o,bss:wac
I
·-----f-i-le-2--.o-,-s-t-·-c-k-:-W--8-P--+I
·-----------------------·
Fi;ure S-3. Selecting Sections by Name
5.4.4. Selecting Section· by Fil·
Selecting sections according to their file of origin is equ·lly simple. The syntax for a filename selector is the filen·m· followed by a comma, as in the following example ·here ·e select all th· sections in "fila1.o" followed by all th· sections in "file2.o".
Zilo; Object ~ile Utilities
s-'c
Chapt·r S
MLINK
mlink -i file1.o file2.o -s file1.01 fileZ.01 -o ex3 -v
mlink v. 2.1 -- Zilow MUFOM linking utility
~AP: ISecn CSecn Location Size
IFile1Name: At ts
Output fih ex3:
0 0 L=OOOOOOOO S=00000242 file1.01coae:ANSX 1 1 L=COOC024Z S=CC000231 file1.01rom:ANRS 2 2 L=C0000474 S=COCOC232 file1.01data:AhSw 0 3 L=000006a6 S=00000242 file2.01coae:ANSX 1 4 L=OOCOOS.S S=COCI00234 file2.01d·ta:ANSW
3 s L=OCOCOb1e S=CC002CCO file2.01stack:ABPSw
6 L=00002b1c S=00000032 ,ccomillon:ASNSw 7 L=OOC02b4e 5=00000400 1 b ss: ABC NW
Input files:
0 1 2
3
0 1 2 3
a L=OOOOOOOO S=00000242 file1.01cod·:ANSX
1 L=C0000242 S=COOOOZ31 file1.01rom:ANRS 2 L=OOOC0474 S=00000232 file1.01datc:ANSW 7 L=00002b4e 5=00000200 file1.01bss:ABCNW
3 L=OCC006a6 S=CC000242 file2.01Code:AhSX 4 L=OOOOOS.8 S=00000234 file2.01data:ANSW
7 L=C0002d4e S=COOC0200 file2.01bss:ASCNW
5 L=00000b1c S=00002COO file2.01st·ck:A6PSW
file ex3:
·I-----f-il-e-1-.-0-1-c-o-d-e-:-X------· ·I-----f-i-le-1-.-0-1-r-o-m--:-R------+I +I --·--f-i-l-e-1-.-0-1-d-a-t-·-:-W------+I +I ----f-i-l-e-2-.0--1-c-o-d-e--:X------+ +----f-i-l-e-2-.-o-,-d-a-t-a-:-w------+I +I ----f-i-le--2-.0--1-s-ta--:k-:-W--B--P--+I +--C-c-o-m-'ll-o-n-:W-C--S -----------+ +--b-s-s-:W--S-C---------------+
fila1.01bss:wac f11e2.01bss:wac
·-----------------------·
Figure 5-4. Selecting Sections by File
Note, however, that the co~bined BSS section r.nd the Ccommon section still come at the end of this link. This is because
s-21
Zilo~ Cbject File Utilities
MLINK
Chapter 5
ML INK
the SSS sections are combined automatically and the Ccommon section is generated automatically; automatically-generated sections do not have a file of origin. Also, note that the "st~ck" section is selected along with the rest of file2.o's sections, ~hich may not be desirable.
You can make sure that the stack is postponed until the end of the link in one of two ways: not selecting it by combining filename and attribute selection, or MD-select it with the ·u argu~ent. Commands using these two techniques are sho!l.'n belo111:
mlink -i file1.o file2.o -s file1.01 file2.o,:-P -o ex3 mlink -i file1.o fila2.o -s file1.01 file2.o, -u stack -o ex3
5.4.5. Separate ·i Argu·ents
In order to circumvent these effects, if desired, you can
select the sections from "file1.o" ~liQCI ~QM ·ic;wi
"file2.o". Note that in this case you can use ·s with no
arguments to select everything in the input list except "postpone" sections. The second -· selects all of file2.o's sections except "stack", which has tha "P" C"post~one") attribute. Also note the use of -d to define a separate Ccommon section for file1's common sy~bols.
111link -i fih1.o -s -d -i file2.o -s -o ex4 -v
MAP: ISecn OSecn Location Size
IFile1Name:Atts
Output
file 0 1 2 3
0 1 2
3
ex4: 0 L=OOOCOOOO 1 L=COCOC242 2 L=C0000474
3 L.=000006a6
4 L=C.00008a6
s L=OOOOOSba
6 L=OOOOOafc 7 L=00000d30 Ii L=OOOOOf 30
9 L.=00000f44
5=00000242 S=COOOC231 5=00000232 S=00000200
S=C0000014 5=00000242 s=OOOOOB4 S=OOOOC200 S=COOOOJ14 S=00002000
file1.01code:ANSX file1.o,rom:ANRS file1.01pata:ANSW
file1.01bss:ABCNW
1Ccommon:ABNSW file2.01code:ANSX file2.01aata:ANSW
file2.01bss:ASC~W
1Ccom111on;ABNSW
file2.01staek:ABPS~
Input files: 0 1 2 3
0 1 2 3
0 L=OuOOJOOO S=00000242 file1.01COGe:AhSX 1 L=00000242 S=COOOOB1 file1.01rom:ANRS 2 L=OOOOJ474 5=00000232 file1.01data:ANSW
3 L=000006a6 S=C0000200 file1.01bss:ABCNW 5 L=00(;003ba S=CC000242 file2.01e~d·:ANSX 6 1.:QQQOul'fC S=00000234 file2.01data:ANSW 7 L.=C0000d30 5=00000200 file2.o,bss:A8C~W 9 L=CCC00f44 S=C0002COO file2.01stack:ASPSk
Zilo· Object File Utilities
5-22
ML INK
Chapter 5
file ex4:
·-----------------------· file1.01code:X
+----f-i-le-1--.0--1-r-o-m--:R-------+I +----f-i-le--1-.0--1-d-a-t-a-:-W------+I +----f-i-le-1--.0--1-b-s-s-:-w-6-C-----+ +I --C-c-o-m-m--on-:-W--S-----------+I +I ----f-i-le--2-.0--1-c-o-d-e--:X------+I ·I-----f-i-le-2--.0-1--d-a-t-a-:-w-----+I +I --C-c-o-m-m--on-:-W--S-----------+I +I ----f-i-le-2-.-0-1-b-s-s-:-W--B--C----+ +I ----f-i-le-2--.0--1-s-ta-c--k-:W ---S-P--+I ·-----------------------·
Fi3ure 5-5. Separate -i Arguments
5.4.6. Selecting Sections by Attribute
It is freQuently more convenient to select sections by their attributes than by their names or files of origin. In other cases it may be a1·1111c~, as when preparing ~ generalpurpose command procedure in ~hich the na~es of the input files might not be kn~wn. CFor example, the linker's default selection is done by attribute.>
Section attributes can be combined for selection in several different ways. You may want to select all sections that
have a given set of attributes, all sections ·that do D9l
have a parti~ular attribute, or ~11 sections that have
1ilb1c of two or more attributes or combinat~~ns of attri-
butes. Loosely speaking, "not" is represented by preceding an attribute by a "-" sign, and "either" <logical "or") is
represented by separating two groups of attributes by a "+"
sign. The attributes themselves are represented by uppercase or lowercase letters (See Section A.2 for specific information about the attributes and their meanings). Attributes in a selection are preceded by a colon C":"), which also separates th·· from the section name1 if any.
For example, you might want to put writable but non-SSS data first, followed by r·ad-only data, then code, then SSS anc stack. The command to do this is shown below. ~ote that
s-23
Zilo; Object Fila Utilities
MLINI<.
Chapter S
MLINK
the 3SS and stack are select·d E-t the end by default, and so need not be mentioned exQlicitly. Note that if you did not care what order the "rom" ~nd "code" sections came in, you
could have replaced ":R :X" with either ":R+X" or ":-w".
mlink -i file1.o file2.o -s :w-s :R :X -o exS -v
"tA p: ISecn CSecn Loc~tion Size
IFile1Name:Atts
Outp"'t file exS:
2 0 L=OOOOOOJC 5=00000232 file1.01data:ANSW
1 1 L=C0000232 5=00000234 file2.01data:ANSW
1
2 L.=CCC00466 5=00000231 file1 .01rom:A~RS
0 3 L=COOC0698 S=00000242 file1.01code:ANSX
0 4 L=OOCOCSda 5=00000242 file2.01code:ANSX
S L=00000b1c S=OC000032 1Cco111mon:A6NSW
6 1.=00000b4e S=00000400 1bss:A8CNW
3 7 L=00000f4e S=00002000 file2.01stack:ABPSW
Input files: 0 1 2
3
0 1 2 3
3 L=00000698 S=C0000242 file1.01code:ANSX 2 L=OOC00466 S=COOOG231 file1.,01rom:ANRS 0 L=OOOJOOOO S=00000232 file1.01data:ANSW 6 L=COC00b4e S=COOOC200 file1.01bss:ASC~W
4 L=000008da S=00000242 file2 .. oicode:AN5X
1 L=COC00232 S=00000234 file2.o,aata:ANSW 6 l=CCOOOdite S=COOOC200 fil1Z .. 01bss:ABCNW 7 L=00000f4e 5=00002000 1ila2.o,stack:ABP5w
fila ex5:
·-----f-il-e-1-.-0-1-d-a-t-a-:-w------· +----f-i-l-e-2-.-o-,d--a-ta-:-:-W------+ +I ----f-i-l-e-1-.--o-,-r-o-~-:-R------+I +I ----f-i-l-e-1-.-o-,-c-o-d-e-:-X------+I
+-----------------------+ I fileZ.o,code:X
+I --C-c-o-m-m-o-n-:-~-B------------+I +I --b-s-s:-W--B-C---------------+I +I ----f-i-l-e-2-.-o-,-s-ta-c-k--:w--B--P--+ ·-----------------------·
Figure 5-6. Selecting Sections by Attribute
Zilog Cbject File Utilities
S-24
MLINK
MLINK
5.4.7. Loceting Sections ·t Specific Addr·····
A common problem that occurs in cross-software oavelopment
is when the target system has both PRCM and RAM, and it is
-·ddr··· necessary to out th· program in PROM and the data in RA~.
The
option specifies the bas· address of the naxt
section to be selected, so it is used in conjunction with
selection to control the addresses of sections.
Another thing most users want to do is to locate the stack as high in memory as possible; this can be done with the -t address option to specify the l9Q address of th· l l l l section to be selected. Tha ·x·mpla below shows both of these section-locating tachniQuas. (~ota that wa are grouping
some "~ritabl·" data with "read-only" data and code in what is prasum·bly th· PROM area; this is a common techniQue in languages like C ·hich allow no distinction between writable and read-only data. In such cases, tables and so on that
need to b· in PRO~ are grouped into a single file1 such as fil·1.o in this example.)
<In the example balow1 the command follows the UNIX* conven-
tion in ·hich a backslash (\) character is used to continua a long command on another line.>
mlink ·i file1.o fileZ.o -o -s :X :R file1.o,data \
-4000 -s :W-P ·d -s :P -t CFFFF -o ex6 -v
!4AP: ISecn OSacn Location Size
IFile1 Name: At ts
Output file ax6:
0 0 L=COOCOOOO S=C0000242 fila1.01coda:ANSX I) 1 L·00000242 S=OOOOOZ42 fila2.01code:ANSX 1 2 L=COC00484 S=00000231 file1.01rom:ANRS 2 3 L=000006b6 S·COOOC232 file1.01data:ANSW
4 L·C0004000 S=00000400 1bss:A8CNW
1 5 L=COC04400 S=0000Ci234 file2.01data:ANSW
6 L=CCOC4634 S=COOOOC32 ,ccornmon:A8NS· 3 7 L=OOOOdf fe S=00002000 fila2.01stack:A8PSW
Input files:
0
1 2
3 0 1 2 3
0 L=OCCCOCOO S=00000242 fila1.01coda:ANSX
2 L=OOC00484 S=OJ000231 fila1.01rom:ANRS
3 L=COC006b6 S=OOCi0023Z file1.01data:ANSW
4 L=CCCC4000 S=CCC00200 file1.01bss:ABCNW
1 s
L=00000242 L=C0004400
S=C0000~42
S=00000234
fila2.01code:ANSX fila2.01data:ANSW
4 L=000042JO S=00000200 fila2.01bss:ABCNW
7 L=COCHldffa S=CC0020Ci0 file2.01stack:A8PSW
5-25
Zilog Cbject Fil· Utilities
MLINK
Chapter S
~LINK
fil· ex6:
0000 ·-----f-il-e-1-.-0-1-c-o-d-e-:-X------· +-----------------------+ +----f-i-l-e-1-.-o-,r-o--m-:-R-------+ +----f-i-l-e-1-.-o-,-d-a-t-a-:-w------+ +-----------------------+
4000 +--b-s-s·:W--8-C---------------+ +----f-i-l-e-2-.-0-1-d-a--ta-:-w------+I +--C-c-o-m-m--on-:-W--S-----------+I +-----------------------+
DFFE +-----------------------+
Ff FF ·--··-·-----------------·
Figure 5-7. Locating Sections at Specific Addresses
S.4.1. M··ing and Co·bining Sections
It is usually not necessary to combine or rename sections in order to affect their location or order, but naming and combining can be useful if the output of the linker is a relocatable file which is going to be used as input to a subsequent link. For axa~pla1 you may want to construct a library module containing tha code and data from several sub-modules. In this case it may ba desirable to have only a single combined coae section, a single date section, and so on. An example of this is sho~n below. Note the use of
-r to keep the resulting output file relocatable. ~ota that
we are specifyinv ·ttributes as wall as section naNes1 and that neither th· n~~·s nor the attributes of the combined sections have to be the same as those of the inpyt sactions.
Zilog Object File Utilities
S-26
ML INK
Chzpter 5
ML INK
~link -i file1.o file2.o -r -s code -n code:X \ -s data -n data:· -s rom -n rom:R -o ex7 -v
MAP: ISecn OSecn Location Size
Output file ex7: 0 R·OOOOOOOO S=00000484 ,code:N5X
1 R=OOCOOOOO S=00000466 1data:NSW 2 R=OOOOOOOO 5=00000231 1rom:NRS
3 R=COOOQOJO S=00000032 1Ccommon:BNSW 4 R=OOOOOOJO 5=C0000400 1bss:BCNk 3 S R=OOOOOOOO S=OC002000 file2.01stack:BPSW
Input files:
c
1 2 3
0 1
2
3
0 R=OOCOOOOO 5=00000242 file1.o,cooe:N5X 2 R=OOCCOOOO S=00000231 file1.01rom:NRS 1 R=OOOOOOOO S=00000232 file1.01data:NSW 4 R=OOOOOOOO S=OOOOC200 file1.01bss:BCNW 0 R=000002~2 5=00000242 file2.01coce:NSX 1 R=C0000232 5=CC000~34 file2.01data:NSW 4 R=COOOQ200 S=COOC0200 file2.01bss:BCNW
5 R=OOOOOOOO S=00002000 file2.01stack:BPSW
file ex7:
·---c-o-d-e-:X----------------·I
file1.01code:X
I
file2.01code:X
I
+--r-o-m-:-R-----------------+I
I file1.01rom:R
I
+I --d-a-t-a-:-w----------------+I
I file1.01d£ta:w
I
I file2.01data:w
I
+I --C-c-o-m-m-o-n-:-W-B------------+
+I --b-s-s-:W--S--t--------------+
I file1.01bss:WBC
I file2.01bss:WBC
+----f-i-le-2--.0--1-s-ta-c--k-:W ---S-P--+
·-----------------------*
Fi;ure S-8. Naming and Co~binin; Sections
5-27
Zilog Object File Utilities
Chapter 5
~LINK
5.4.9. Overlays
In small systems it is sometimes necessary to break programs up into pieces that "overlay" or loao on top of ona another. A clever loading pro~ram that understands about section~ could select the sections belongi~g to overlays out of an ~bject file containing the whole orogram, but more often it is necessary to put overlays in a separate file. This can be done in a single linking step by specifying multiple output files.
A related problem is ··king sure that the sections that are supposed to overlay one another start at the sa~· address. This can be done easily if ·· want to specify the address exactly, but more often the overlaid sections are located relative to other sections, whose size we don·t care to keep track of. The ·· (mark) option is useful here.
The techniques used for making overlays are shown below. We assu~· that the code and data in file2.o are need~d only part of the time, and can overlay file1.o's data section, which ·· therefore locate li1tC the Ccom~on and 8SS sections. we locate the stack at the high end of memory using the ·t option. It doesn't matter which overlay file the stack goes ·ith because, being · BSS section, no data is actually loaded into it.
Zilog Object Fil· Utilities
S-28
MLINi<
Chapte,. 5
ML INK
mlink -i file1.o file2.o -s file1.o,code :R -s :S-P -d \ -m1 -s fila1.01data -o exS \ -m1 -s :X :~-a :P -t Offff -o ex8a -v
MAP: !Seen OSecn Location Size
I File1Name :At ts
Output file exa: 0 0 L=CiOCOOOOO S=C0000242 file1.01code:ANSX
1 1 L=OOC00242 S=OCC00231 file1.o,rom:ANRS
2 L=00000474 S=COOOJ400 ,bss:A6CNW 3 L=CCC00874 S=CCCCOC32 ,ccommon:ASNSW
2 4 L=CCC008a6 S=COC00232 file1.o,data:ANSW
Output file ex8a: 0 S L=CCCC08a6 S=00000242 file2.o,code:AhSX 1 6 L=OOCOCu8 S=OOC00234 file2.o,aata:AhSW 3 7 L=OOOOdffe 5=00002000 file2.o,stack:ASPSW
Input filas:
0 1 2 3 0 1 2 3
0 L=OCCCOOCO S=C0000242 file1.o,code:ANSX 1 L=JOOOJ242 S=C0000231 file1.o,rom:ANRS
4 L=C00008a6 S=C0000£32 file1.o,data:ANSW 2 L=CCC00474 S=OC000200 file1.o,bss:A8CNw S L=OOC008a6 S=OJQ00242 file2.01code:ANSX 6 L=COCOOaeB S=OCOOC234 file2.o,data:ANSW 2 L=00000674 S=00000200 f ile2.o,bss:ABCNW
7 L=OOOOdffe S=OC002000 file2.o,stack:ABPSW
DI
5-29
Zilog Object File Utiliti·s
ML INK
Chapter 5
MLihK
file ex8:
0000 *I ----f-i-l-e-1-.0--1-c-o-d-e-:-X------* +-----------------------+
I
+I --b-s-s-:-w-a-c---------------+I +--C-c-o-m-m-o-n-:-W-~------------+I 08A6 +-----------------------+
·-----------------------·
file ax8a:
08A6
·I -----fi-l-e-2-.-o-,c--o-d-e-:-X------·
+I ----f-i-le-Z--.-0-1-d-a-t-a-:-W------+
+-----------------------+
DFFE +---~-------------------+
FFFF ·-----------------------·
Figure 5-9. Overlays
5.4.10. Di·c·rding Section·
It is somati~es useful to produce an object file containing only some of the sections of the input files. This is an alternative way of producing overlays; it is used more often if one input file contains an operating system and another an application that runs under it. The application will need to know th· addresses of routines in the operating system, but can assume that the oQerating system will already be in memory.
Sections are discardeo by giving a -o option with no filen·me. This is shown in the example below, in ~hich all the sections in file1.o are aiscarded.
Zilog Object File Utilities
5-30
Chapter 5
MlihK
~link -i file1.o -s -d -o -i file2.o -s -o ex9 -v
MAP: ISecn CSecn Location Size
Oisc~rded:
0 1 2 3
0 L=COOOOOOO S=C0000242 file1.01cooe:ANSX 1 L=00000242 S=OOOOC231 file1.01ro~:AhRS 2 L=00000474 S=00000232 file1.01dat~:ANSW
3 L=GCOC06a6 5=00000200 file1.01bss:ASCNW 4 L=000008a6 S=00000014 ,ccom~on:ABNSh
Output file ex9:
0 5 L=CCCOCSba S=C0000242 file2.01code:ANSX
1 6 L=OOOOOofc S=Oi:l000234 file2.01data:ANSW
2 7 L=OOOC0d30 S=C00002CO file2.01bss:ABCNW
8 L=OOOCOf30 S=OOCC0014 ,cco1i;11on: ABNSW
3
Y L=00000f44 S=OOOOZOO·J file2.01st~ck:ABPSW
Input files:
0 1 2 3 0 1 2
3
0 L=COOCOOOO 5=COC00242 file1.01code:ANSX
1 L=OJ000242 5=00000231 file1.01ro111:ANRS 2 L=00000474 5=00000232 file1.01data:ANSW 3 L=OOC006a6 5=00000200 file1.01bss:ASCNW S L=000008ba 5=00000242 file2.01code:ANSX 6 L=OOCOOafc S=CCOOC234 file2.01oata:AhSW
7 L=Ci0000d30 S=OC000200 file2.01bss:ABCNW 9 L=OOJ00f44 S=C0002000 file2.01stack:ABPSw
file ex9:
·I-----f-il-e-2-.-o-,-c-o-d-e-:-X------· +I ----f-i-le--2-.0--1-d-a-t-a-:-W------+I +----f-i-le-Z--.0-1--b-s-s:-W--B--C----+I +I --C-c-o-~-m-o-n-:-W-S------------+I ·-----f-i-le-2-.-0-1-s-t-a-c-k-:-W--a-P--+ ·-----------------------·
Figure S-10. Discarding Sections
5-31
Zilog Object File Utilities
Chapter 6 MLIST
6.1. INTRODUCTION
The mliil utility uses spacial commer.ts that the asse~bler
can optionally insert into an object fila Cwith the -oson gssembler option) to construct an asse~bler-l1ke listing file from a MUFOM object m~dule.
6.2. COMMAND SYNTAX AND OPTIONS
The command syntax for this utility is as follows:
mlist C-o f ileJ C-s -1 I -xJ [fileJ
The file and options may appear in any order. If no file is given, standard input is used.
The command-line options are:
-o file output file name C!f not specified, output is to standard output.>
-s short format <····s instead of expressions)
-1 lon; format (single long line for overflow of object code)
-x exclude object code that doesn·t fit on the source line.
6.3. USA&E1 OUTPUT FORMAT AND EXAMPLES
The input file sho~la be generated by runr.ing the assembler with the ·o· -on options, to get source coda and line nu~bers into the object file. Most object-file utilities can be made to preserve comments with the -k option; the
comments use~ by mliil are in levels 2 ana 3, so the -kl
option should be used. In particular, keeping comments
through !liDk means that an assembler-like listing. can be
;enerated from a fully linked and relocated load ~ocula.
A full explanation of th· ~UFOM variables used in the expressions displayeo in the object-code column of the
6-1
Zilo~ Object File Utilities
'4LIST
Chapter 6
.. l..IST
listing ca" be found i" Appendix A. The more com·on express ions are:
Xnnn Rnnn·off set
external relocatable in section nnn
Aoart fro~ ·ddition1 represented by an infix "+"
operations in expressions are listed as
sign,
even for operations such as "*" for multiplication. The
er.tire expression is enclosed in an additional set ~f parentheses.
The following examples show e short assembly-lan;~a;e program with its assembler listing, and ml11i-;enerated lis~ ings in the various available formats.
asm80k -oson -oc foo.s -o foo.o -p
asm80k version 2.1a
Mon Apr 28 09:41:34 19S6
foo
LOC
OBJ
LINefi
SOURCE ---
1
.extern xxx
0000~000 6121803cW·······
2
ld
r1, rr2Cfoo1JCr3J
OCu0-0008 1402********
3 foo1: ldl
rrz, #xxx + foo1
OOOOOOOe
4
0000100e R000+000000081**
5
.blkb 1000h
.dd
foo1, xxx * 1001 foo1 Ac
ooou1013 **************
6
mlist foo.o
mlist v. 2.1 -- Zilog MUFOM listing utility
cccoooco
00000000 6121803c <RO+S> 00000008 1402CXO+RO+S)
COOOCOOe
0000100. CRO+S>C· Cx0,64)) 00001010 (iINS(O,RC+e,3,
OOC01C16 ·t»
1
2 3 foo1:
4
s
.extern xx:x
ld
r1, rr2Cfoo1JCr3J
ldl
rr2, #xxx + foo1
.blkb
.Cid
100Gh
foo11 xxx * 100, foo1 Ac
Zilow Object Fil· Utilities
~-2
MLIST
Chapter 6
MLIST
:nlist foo.o -s
mlist v. 2.1 -- Zilog MUFOM listing utility
00000000 OOOCOCOO 61218C3e********
00000008 1402******** OCiOOOCOe
OCOC10Ce **************** 00001016 ********
1 2 3 foo1:
4 s
.extern xxx
ld
r11 rr2Cfoo1JCr3)
ldl
rr2, #xxx + foo1
.blkb 1000h
.dd
foo1, xxx · 100, foo1 A
111list foo.o -x
mlist v. 2.1 -- Zilog MUFOM listing utility
00000000 00000000 6121803cCR0+8) 00000008 1402CXO+RO+a>
0000000. 0000100a (R0+8)(*(X01C4))
1
2
3 foo1: 4
s
.extern xxx
ld
r11 rr2Cfoo1J(r3J
ldl
rr21 #xxx + foo1
.blkb 1000h
.dd
foo1, xxx * 1001 foo1 A
111list foo.o -1
mlist v. 2.1 -- Zilog MUFOM listing utility
;)0000000
00000000 6121S03e<R0+8) 00000008 1402 CXO+RO+S> OOOOCOOe 0000100· CR0+8) (· (XQ,64)) 00001016 C;INSC01RC+a,3,4f))
1
2 3 foo1:
4
s
.extern xxx
ld
r11 rr2Cfoo1J(r3)
ldl
rr,, #xxx + foo1
.blkb 1000h
.dd
foo11 xxx * 100, foo1 #
IDI
6-3
Zilo~ Object File Utilities
Ch~pter 7
~LCA~
7.1. INTRODUCTION
The il~~g ut1lity is a format conversion progran ~hich translates MUFC~ files into one of three for~ats suitable
for movin~ an object module from a host system to a target
systeffl. The three output form~ts are Taktronix ·nd Intel Hex formats, and a simplified version of MUFOM. ml2~' is usually
used in conjunction with QC212,21' which sends the resultin~
outout to a target systam using the Tektronix or other handshaking protocol.
!n eddition to simply converting formats, ~l2i~ has several options which are useful in burring ?RO~s and in download-
i~g.
7.2. COMMAND SYNTAX AND OPTIONS
The command syntax for this utility is as follows:
mload (options) CfileJ
If no filaname is given, the standard input will be converted.
The command-line options are:
-o file Output file name (if not specified, output is to dard output).
stan-
-a MUFOM absolute do~nload subset (default)
-i This option specifies the output to be in Intal Hax format, as aefined in Appendix C.
-t This option sp·cifies the output to be in Tektronix Hex
a. format, as define~ in Appendix
CTne following are useful for burning PRC~s.>
-N Output every Nth byte. Divide input addresses by ~ to ~et output addresses.
7-1
Zilo9 Object File Utilities
!illOAO
Chai:iter- 7
MLOAil
@H Start at (input> address H.
=H Output H bytes.
(The following options are useful for do·nloading, and especially for- mappin; code into a specific s~g~ent.)
+H Add offset of H to every QW1QWl address.
-p (PROM) Subtract 111ti fro~ every iDQWl address (before the division specified by ·N o~tion>. This starts out-
put addresses at zero for burning a PROM.
-z Map Z9001-type sagNented addressss into 24-bit linear
addresses. The 7-bit segment n~1ber in bits 24-30 of
the input address is placed in bits 16-22 of the output
address.
Thus, th· Z800C address 12001234
C<<12h>>1234h in ass·mbler notation) is ~apped into the
output address 121234.
<The follo11ing apply only to MUFOM or Intel download for:11ats.>
-o Output global symbols.
-1 Output local symbols.
-k Keep comments of level N or lower (MUFO'I only).
(default: N = 255)
-s Cutput se·ction infor:nation (MUFCM only).
7.3. OPERATION
The input to mlilQ is a single MUFOM format object module. If the input object module is relocatable C i·i·' there are
symbols fo~ address references for which no values have been associated), than mlal~ will produce an er-ror messa;e but will proceed with the translation, relocatin~ every section starting at zero.
7.3.2. ·loed Addr··· Trenslation
The parameters that affect mla19's address translation are:
S th· specifieo starting address (&S option).
Lilog Object File utilities
7-2
MLOAO
Ch·pter 7
MLOAD
L The number of bytes to be output C=L option).
T
=the specified offset (+T option). The -p option sets T
-s.
N the number of separata PROMS being burned C-N option>.
Given an input address A, this will be translated to an out-
put address AIN - T. Cnly data with Pddresses between S and S + N*L will be loaded.
It should b· noted that all symbolic information is lost when MUFOM is translated into Intel or Tektronix Hex. In addition, MUFOM sections have no counterpart in Intel or Tektronix formr.t, i.e., all sections in the MUFOM file will become one contiguous set of records when translated.
Intel Hex format limits addresses to 16 bits without extended addressing, and 20 bits with extended addressing. Tektronix Hex format limits addresses to 16 bits. Thus, large programs may have to be downloaded in several pieces.
7.4. USING ·loed: SOME EXAMPLES
The f ollo·ing exa~ples show how ml21Q works. The first few examples &~sume the following inp~t module called "tload.o":
7-3
Zilog Cbject File Utilities
!14L0Ai>
Chapter 7
111BZ80K, 05 tload. A0031041'4. OT19860505094SS4. C001C0115--- Section Table ST001A103&bs. SAC0,02. assoc,0111. ASL00100. STC11A1X104code. SAC1,02. ASS0112F0020C6,2F0020CO,-. ASL0112F0020CO. C00101114--- Sy~bol Table ASG12F00200C. NN01,03foo. ASNC110101. NI0010Sstart. ASI0012F002000. C001J2,18--- Program Sections ---. SBOO. LR0001020304CS06070809CAOBOCODOECF. ASPQ0,0101. LR0102030405C6C708090AOBOCOOCEOF10. S801. LR5EC8AF002000.
JlllE.
The following three exomples show the use of ~lQi~ to produce absolute MUFOM output in a form suitable for do~nload
in;.
Zilog Object Fila Wtiliti9S
MLOAO
cIHtPhr" 7
Command:
mload tload.o -o load.o
Output: loaa.o (absolute MUFOM)
MB28Ql(,QS tload. ADC81C4,M. ASPO:J100. LR000102G30405060708090ACBOCCOCECF. ASP0010101. LR0102030405060708090A08CCOOOEOF10. ASP0012F002000. LRSE08AF002CCC. ASG12F002000. ME.
mload tload.o -o load.o -·
Output: load.o CMUFOM with sections)
·'482!0K,05tload. AOC81C4,M. C0010011S--- Section Table ---. ST001A,C311bs. SAOil102. Assoo,0111. ASL00100. STC11A,A,Q4code. SA01102. ASS01106. ASL01,2F002000. C00101,14--- Symbol Table ---. C001C2118--- Pr"ogr"em Sections ---.
uoo.
ASP00100. LR00010203040506070!09QAC&OCCOO!OF. ASP0010101. LR0102030405060708090A090CODCEOF1C. 5801. ASP0012F00200Q. LR SEOSAF0020Ci0. ASG12F002000. ME.
7-5
Zilog Object File Utilities
MLOAO
MLOAiJ
Chapter 7
MLOAD
Co11mand:
mload tload.o -o load.o -slg
Output: load.o (MUFCM ·ith sections and symbols)
MBZ80K10Stload. ADQ6,Q4,M. C001Q0,1S--- S·etion Table ST001A103abs. SA00102. ASS0010111. ASL00100. ST011A1A104code. SA01,02. ASS01106. ASL0112F002000. coo101,14--- Sy11bol Table NN01103foo. ASN0110101. NI0010Sstart. ASI0012FC020<JC. C00102112--- Program Sections ---. SBOO. ASP00100. LR0001020304050607C8090ACBOCODOEOF. ASP0010101. LR0102030405060708090AOBOCODOEOF10. SB01. ASP0012F002000. LRSE08AF002000. ASG12F002000.
"1c.
7.4.2. Tranelating from MUFOM to Intel H·x
Suppose that you ~ant to transl·te an object module that is formatted in MUFOM into Intel Hex records. The following example sho·s ho· this would be performed:
Zilog Cbject File Utilities
7-6
MLOAO
Chapter 7
ML CAO
Command:
mload -i tload.o -o load.o
Output: loaa.o (Intel riex)
mload v. 2.1 -- Zilog MUFOM load formatting
:100000C0000102C3040506C7CS090AOBOCODOE~F78 :10010100010203040506~708090A080COO~EOF1066
:062000005EOSAF002000AS :0020000300 :00000001FF
utility
The ·i option specifies that the input be translated into Intel hex records. link.o is th· input file. ·o load.o specifies that output goes into the file called load.o.
Note that the addresses in the output have bean truncated to 16 bits.
7.4.3. Tranalatin; fro· NUFOM to Tektronix Hex
The method shown for translating object ~odules from MUFOM format to Intel Hex in the previous section is the sa~e
= method used for translating Tektronix format. Instead of
the -1 option (output Intel), the -t option is used to indicate that the output will be Tektronix for~at.
The following example shows tr.e translation of a file to Tektronix Hex with output on Standard Output.
Command:
mload -t tload.o
Output (Standard Output)
mload v. 2.1 -- Zilog MUFOM load formatting utility /00001001000102C3040S06C708090ACBOCOOOECF7S /0101100301020304050607C8090AOBOCOJOEOF1079 /20000608SEOSAF00200036 /20000002
Note that the addresses in the output have been truncatea to 16 bits.
7-7
ZilOi Obj·et Fila Utilitias
~LOAJ
Chapter 7
MLOAO
Downloading a pro;ram or se~ment thereof to a PROM program~·r is straightfor&ard. First, generate · file of the proper format, i.e., Intel or Tektronix Hex. Second, attach the programmer to your terminal's auxiliary port. Third, 'Ii (~~IX·) or 1¥21 COOS) th· file while capturin; the data on the programmer. Last, burn the PROM. This methoe has been used successfully with Data I/C Programmers and ADM 31 terminals.
A second ~ethod can be used if tha PKOM programmer is attached to a second serial port. In this case, the output of ml21~ can be sent to this port insteBd of to a file. If the PROM progra~m·r requires a handshake, QC212,2l can be used <see Section 10.3.3 in the chapter on QC212,Ql·>
7.4.S. Progr···ing Multiple PROM1
Whan a program is too big to fit into a single PROM, it is necessary to perform several loads. The following example shows how to do this.
Suppose you have a file, "file1" which is to be translated into two Tektronix-format files "prom1" and "prom2" with
starting addresses OCOO and 1000 Chex) respectively. You
can do this with the t~o commands
mload -p file1 -o prom1 mload -p file1 -o prom2 i1COO
The 11000 option in the second com~and specifies that output starts with ad~ress 1000 (hex). The -p option specifies that the physical addresses in the output files start ·ith
~ooo.
7.4.6. Pro1r···in1 PROM· for · 16-bit Processor
When developing software for 16-bit processors such as the ZSOCQ, it is ne~essary to progra~ odd and ·~en locations into separate PROMs. The following example shows ho~ to do this:
Given a file "file1" which you want to separate into two Intel-format files, "promO" and "pro~1" respectively, you use the two eom~anas:
mload -2 -p file1 -o promo mload -2 -p fil·1 -o prom1 t1
Zilo~ Object File Utilities
7-8
MLOAO
Chapter 7
MLOAiJ
The -2 option sQecifies that two PROMs are being programmed, so that only every other byte is to be loaded. The -p o~tion scecifies that addresses in the PROM output file
start with O. The 11 option in the second command specifies
that output to file "prom1" starts with adoress 1 in the input file.
Note that for 32-bit processors, -4 can be us·d to produce four PRCll4s.
7.4.7. Tr·n·l·ting Logic·l to Phyaicel Addr·····
When developing soft~are for systems that incorporate m·~ory ~apping, i~ is sometimes necessary to load software ~t a different address (physical address) from the address at which it is intended to run Clogic·l addrvss>. The following example shows how to perform this translation using the
+9.Uu1 option:
Given a file "file1" containing a program linked starting at logical lo~ation Q, you want to load the program into physical segment 1 on a Z8001. The Z8001 CP~ places the start of segment 1 at 0100C000Chex); the target system's memory places it at 010J00(hex). Use the command:
mload file1 -z +01JOOOOJ
The output of this command is another MUFOM file on standard
output. The ·z option specifies that 32-bit Z8001 logical
address·s are mapped into 24-bit physical adoresses by "squeezing out" the secono byte. The +01000000 option specifies that 01000000 is added to logical load addresses
in the input file <;1:tslc1 the translation implied by ttle ·z
option.
Note that only the addresses at ·hich data are to be lg1g1g
are mapped. Addresses in the program, and the values of symbols, ~re unchanged.
7-9
Zilog Object File Utilities
Chapter 8 MLOROER
8.1. INTRODUCTION
The ml2cg1c utility takes a list of MUFOM modules and com-
putes the optimum order for putting these modules into a library. noptimum order" is the order that allows all reQuired modules to be found in a single pass throu~h the liorary; thus, all ~odules in the library that reference a symbol appear in front of the module that defines it.
It is not always possible to find such an optimu~ orderi ~l2C2it will inform you if this is the case, with the message:
cycle in data:
followed by a list of the modules that contain a circular series of references.
The output file generated by !l2t£tt is in a form that can be used by ~1~2 to generate a library.
8.2. COMMAND SYNTAX AND OPTIONS
The ml2cg1c conversion utility is invoked by the following
command:
mlorder C-rJ (fileJ ···
The command-line options are:
-r If the -r option is given, the standard output is a
list of pairs of object file names, ~eaning that the first file of the pair refers to external identifiers defined in the secono. The output ~ay be processed by 1i2t1 to find an ordering suitable for one-pass ~ccess by mlAD~·
Alternatively, the proper ord·rin~ may be generated directly by mlgc2i~ by not giving the -r option. In this casa the o~tput is ~ 1ila suitable for diract input to ml~g witr. the f option.
B-1
Zilo~ Object File Utilities
9.1. INTRODUCTION
mom The
utility prints the symbol table name list for a
given file in any of several formats.
9.2. COMMAND SlNTAX AND OPTIONS
The command syntax for this utility is as follows: mnm CoptionsJ Cfil·~
If no file is given, standard input is used.
The com~and-line options are:
-1 Include local symbols in the listing.
-n List symbols in n~~erical order.
-u List symbols unsorted, that is, in the order they appear in the object file.
-m List symbols with link map information.
-s Swapped format, with name first on the line.
-s N Swapped format with name first snd truncated to N char-
acters.
-o file Direct output to the given
o~tput.
file
instead of
standard
9.3. OUTPUT FORMAT AND EXAMPLES
ma~ displays the sy~bols defined in the given file in any of several formats. Options are provided to display
9-1
Zilog Object File Utilities
MNM
Chapter 9
'4NM
o
only global and external sy11bols (th· default> or local
sy11bols as well.
o sy·bols in alphabetical order, in nu·erical order by address, or in their order of definition.
o with or ·ithout link map information.
0
in a short for· suitable for use with symbolic
debuggers, e11ulators1 or other utilities.
9.3.1. Default N··· Liat For··t
The default format of the symbol na11· list is shown in the example below. The list has · line entry for each symbol. The first column shoms the value of the symbol. This is a hexadecimal number for absolute symbols, or an expression
involving an R-variabl· (relocatable section origin) or x-
variabl· (external symbol). More complex expressions are listed as "<expression.>".
The second column contains "X" for external symbols, "I" for
global (internal) symbols, and "Nu for local symbols.
The third column contains the name of the symbol.
;wnm -1 foo.o
mnm v. 2.1 -- Zilog itlJFOM namelist utility
00001002+XOOOO
N expr1
<ooEoxoporoeoscs+ioxono.>co
N expr2 X ext1
OOOOOOOO+X0001
X ext2
00000004+ROOOO
I glb1
00001002
I glb2
000001234S6789abcdef I glb3
OOOOOOOS+ROOOO
N loc1
OOOOOOOa+ROOOO
N loc2
Note that the above example was prepared with the "-1"
option to list local symbols.
9.3.2. N··· Liet ·1th.Map lnfor·ation
The ·· option can be used to list sy·bols ·ith information derived from the section table, and from the link map in
modules output by mliCk· The fourth column contains the
file of or1g1n for the symbol, with · library na~· in parentheses if the symbol came from a library. The fifth
Zilog Object File Utilities
9-2
MN'4
Chapter 9
column contains the name of the section in which tha symbol resides, and its attributes. This column contains "?:" if the section cannot be determined. (The sp~c:e between columns has b·an decreased a little in the example below to make it fit ~ithin th· margins in this manual.)
11nm -m foo.o
"· mnm 2.1
00005714 00005256 00005086 00005786 00005Sb2 00005000 00005200 OOOOOOCa
00,JOSl!fa
00005026 00000000 00000002 00000004 000067ab 00004567 00005026 00001234 00001234 00005678
Zilog MUFOM namelist utility
I __ align
doprtz.oCfoo.lib), libc:ode: ANS>
I I
__ Cloprtz __ iob
doprtz.oCfoo.lib), libc:ode: Al'li S> strlen.oCfoo.lib), libc:ode:At.S>
I __ pr tint
doprtz.o(foo.lib), libc:ode: ANS>
I __ xputc
doprtz.o(foo.lib), libc:ode:ANS>
I _atoi
atoi.o(foo.lib), libcode:ANSX
I _printf
printz.o(foo.lib), libc:ode: ANS>
I _pute
foo.01 allfoo:ANSW
I _strlen
strlen.o(foo.lib), libcode:ANS>
I _strnc:ml)
strnc:mp.o(foo.lib), libc:ode:AN!
I foo1
foo.o, allfoo:ANSW
I foo2
foo.o, allfoo:ANSW
I foo3
foo.o, allfoo:ANSW
I gru
strlen.oCfoo.lib), ? :
I zoo
strlen.oCfoo.lib), ? :
I zorc:h
strlen.oCfoo.lib), libc:ode:ANS>
I zork
strlen.0Cfoo.lib)1 ?:
I zorn
strlen.o(foo.lib), ?:
I zot
strlen.oCfoo.lib), libcode:ANS>
ID
9.3 .. 3. Swapped N··· List Fof'··t
In order to interface to some symbolic: debuggers, it is possible to get a nswapped" listing with the nama first on the line. It is also possible to truncate the name f i1ld to a ~iven number of characters. This is done with the ·s or -· N option, as in the example below.
mnm -s8 foo.o
11n111 v. 2.1 -- Zilog MUFCM namelist utility
ext1 x oooooooo+xoooo
ext2
x OOOOOOOO+x0001
glb1
I OOC00004+ROOOO
glb2 I 00001002
glb3 I OOOOC123456789abcdef
9-3
Zilog Object File Utilities
Chapter 10 PROTOCOL
10.1. INTRODUCTION
The QC9S9&9l utility is the upload/download communication
handshake program. It supports a variety of different file-transfer protocols commonly used on PROM pr~grammers and development systems. It is normally used in conjunction
with 1la1d to download modules into a target system.
10.2. COMMAND SYNTAX AND OPTIONS
The command syntax for this utility is as follows:
protocol CoptionsJ Cf ileJ
A maxilll'Um of one file may be specif iedi if no file is spe~i
fied the standard input is used for downloading, standard output for uploading. Order of command line arguments is not significant.
The command-line options are:
-d device download device name. (If no -d option is ;iven or no device is specified, the terminal is used.)
·u CdeviceJ upload device name. (If no device is specif ied1 th· ter~inal is used.)
·f file
take command arguments from the specified file. Argu-
ments in th· f il· may be separatea by whitespace or
newlines; comments start with a semicolon and end with
-·
newline. suppress error messages.
-s string setup string sent to upload/download device. Multiple -· options are permitted; the strings are concaten£ted.
1 c-1
Zilog Object Fil· Utilities
PRCTOCCL
Chapter 10
PROTOCCL
-p protocol specifies protocol. (uafault Tektronix.>
The protocol is matched with a list of protocol names. Case is ignored, and abbreviation is allowed. Presently, the only protocol defined is "Tektronix".
Protocol may also be ~ list of ite~s of the form "variable;value". Values are numeric; hex if they start
with "O", decimal otherwise. Variables are one of the
following:
ack acknowledgement character.
nak negative ackno~ledgement character.
abort abort character.
linedelay delay (in milliseconds) after sending each line.
chprdelay delay (in milliseconds) after sending each character.
prompt prompt character.
retry number of times to retry an incorrectly-received record.
timeout timeout in seconds.
10.3. USING protocol: SOME EXAMPLES
10.3.1. Do·nloadlng to a Z8 or 18000 D·v·lOP··nt Module
To download an object module to a target syste~ such as a Zilo~ Z8 or ZSCOO development module, the following procedure is used:
(1) In Unix, create an alias with the command alias LOAD 'protocol -t·
In othe~ operating syste~s, create a command file with
Zilo; Object File Utilities
10-2
PROTOCOL
Ch·pter- 10
PROTOCOL
the same effect. Note that the filename argument to the LOAD comman~ is appended after the "-t" option. If you want to specify MUFOM object modules rather than Tektr-onix hex, your ali·s or command file will need to
run them through ml;ag first; this can be done with
alias LCAO ·mload -t * I protocol -t·
(On operating systems other than Unix, this will take two commands, with mliiQ creating · temporary inter1aediate file.)
(2) While running in the development module·s monitor, axe· cute the command:
t.OAO <filename>
The development module sends the host the co~mand: LOAD <filename>
which the host inter-prets as protocol -t filename
which performs the Tektronix handshake protocol with the development module.
10.3.2. Uplo·dlng fro· a 18 or Z8000 Dovolopmont Modulo
The procedure to uploac from the Z8 or Z800C development module is slightly more complicated than t~e procedure used to download. T~e user must kno~ the starting and ending addr-esses of the image to be uploaded before proceding. ~iven that, the following procedure must be followed:
<1> Alias "SEND" to "protocol -u -t·.
<2> ~hil· running in the development module·s monitor, exe-
cute the command:
SEND <filename> <start-add~> <end-addr>
The development module sends the host the com~and: LOAD <filename>
which the host interprets as protocol -u ·t file"ame
10-3
Zilog Cbject Fila Utilities
PROTOCOL
Chapter 10
PROTOCOL
This invokes QC919,9l, ·hich pe~forms the Tektronix
handshake protocol with the aevelopment module. The resulting file is in Tektronix Hex format, suitable for downloading again.
NOTE that "protocol -t -u filename" is incorrect: this
causes ataia,al to interpret the given filename as the dev-
ice to upload from, with odd results.
Soma PROM programmers do not require a download protdcol; they simply have a file copied directly to them, as
described in the chapter on mlali· Others (e.g., the
DATA/IO model 21) require more elaborate tr·atment as described below.
It is most convenient, if · device requires a complex download protocol, to make a command file. For downloading to a OATA/IO model 29 attached to device "/dev/tty4", this file (call it "dataio"> should contain:
-d /dev/tty4
-s \~\C86A\rI\r
-p prompt·03E
In order to do·nload a file, for example ~foo", use the command
protocol -f dataio foo
For uploading from the DATA/Io, the corresponding command file should contain:
-s \C\CS6A\r2000;\r1CM\r0\r -u /dev/tty4 -p prompt=03E
Naturally, other PROM programmers ano emulato~s ·ill have different protocols; you will need to consult your manual for details, and uill probably have to experiment as ··11.
Zilog Object File Utilities
Ch·pter 11 OTHER PROGR~MS
The following pro;rams are supplied with the Object Fil· Utilities for specializad purposes:
·m2a·r
~uima;e.c
They are described below.
11.1. MAR
The mit utility is an older version of ~li;. It produces a
so-called "archive" file which is compatible with older versions of mlic~, as well as the library files of the Berkeley version of the UNIX· operating system. Archive files have the advantage of being able to contair. any kind of file (not just MUFOM object files), and the disadva~tage of not allowing the linker to access them randomly.
The command line of llC is identical to that of mli2 Csee
Chapter 4).
m
11.2. M2A The ~ii utility converts MUFOM object files to a form called 1·2Y1' which is the format used i~ Zilog's SSOOC microcom-
puters. This for·at is primarily useful for downloading into Zilog's EMS-8000 emulator for the Z8000 microprocessor.
11.2.1. Co·mand Syntax And Options
The J'i conversion utility is invoked by the following command:
m2a ( -i I -o J ( -s seg J inputf ile outputf ile
The command-line options are:
-i Put instructions and data in separate address spaces.
-o Convert an overlay file.
11-1
Zilo; Object File Utilities
OT~ER PROGRAMS
Chapter 11
OTHER PROGRAMS
-s H is the seg~ent number (i~ hexadecimal> in which the stack is to reside.
lhe input file must be absolute, i·I· the output of mlin~ or mlQIQ· Many features of MUFOM cannot be converted to l·9Wl' these include arbitrary expressions involving relocatable or external symbols, and sections other than code, data, and BSS.
11.3. MUIMAGE.C
The mwim1g1., program is the C-language source for a pro-
gram. It converts a MUFOM character form object file on Standard Input to en absolute binary image file on its Standard Output, while producing a hexadecimal listing on Standard Error (the terminal). This program is not very useful by itself, but is supplied in source form so that you can construct a customized loader for mhatever target system you
are using. 1wim1a1 is designed to work on the output of
mlal~, and understands only absolute modules in character form.
11.3.1. Co···nd S~ntax
lhe 'wim1g1 conversion program is invoked by the following
co~mand:
muimage CinputfileJ > outputfile
If no input file is specified, Standard Input is used.
Zilog Object File Utilities
11-2
Appendix A MUFOM FILE FORMAT
A.1. THE MUFOM STANDARD
The MUFOM format, as implemented by the Zilog crosssoftware products, follows th· format specified in the IEEE
standard 1~~~ 62~-121~, "The Microprocessor Universal Format for Object ~odules." The standard specifies only the '~ICi':
iiC t2cm for object files; the biD~C~ t2cm of MUFOM files
follows the suggested format in Appendix 6 of the standard.
Section A.2 discusses the concepts of modules and sections,
and the various section attributes and their meanings. Sec-
tion A.3 discusses the way MUFOM handles sy~bols, and the
use of MUFOM variables~ Section A.4 discusses tha local
usage of IEEE Standard 695 by the Zilog cross-soft~are,
including
i~plementation restrictions.
Section A.S
discusses local extensions to the standard that have been
added to implement efficient library search. Section A.6
contains an example of a MUFOM object module and an explana-
tion of its constituent commands.
A.2. MODULES AND SECTIONS
MUFOM object modules C~bject files> are divided into 11':
tiaDI each of ·hich is destined to be loaded into a separate
area of memory. Each section has a Dim·' a illl' 111ti: QW11i' and Cif not relocatable) a la;11iRQ· Each section also has a 1t;liiD DWIQIC which is used to refer to it internally. In Zilo;'s implementation these section nu~b·rs correspond to the order of the sections in the section tabla. Section numbers are limited to 16 bits. The name and attributes of a section are specified in a MUFOM "ST"
(Section Type) command; the size and location are MUFOM s-
and L-variables respectiv·l~.
It is important to note that the name of a section may be null Cin ·hich case the section is referred to as "unnamed"), and that the names of sections DllG DQl bi WDl9MI· Thus, a file may contain severel sections named "coda". The advantage of this is that the linker can relocate such sections separately. Therefore, on a Z8001 all "code" sections do not have to be in the same segment.
Sections may also have an 1li~am1a1 and QIQI Jill· The location Clower bound) o~ a section is restricted to be a multiple of its align~ent, and the section may not cross a bo~ndary ·hich is a multiple of its page size. The page
A-1
Zilog Object Fila Utilities
"UFO" FILE FORMAT
Appendix A
MuFOM FIL! FORMAT
size is used to implement addr~ss-space and segment-size limits. The ·lignment and page size of a section are spec~ fiea by the MUFOM "SA" (Section Alignment) co~m·nd.
The follo·ing is a description of the various section attri-
butes and their meanings. This includes the way they affect the link process, ano their eventual use in a target system. each ~ttribute is represented by a letter <lowercase or uppercase>.
A.2.1. Ace··· Attributes.
The access attributes specify ho· sections are used (accessed) in the target system. They are used during the link process to select groups of sections that are to be located together.
W <Writeabl9> This is th· default access attribute.
R <Read-only) This attribute is used for data that is intended to go into ROM.
8 (8SS> This attribute is used for data that is initialized to zero when a program is started. (8SS st·nds for "Block Started by Symbol".>
X <executable) This attribute is used for cod· sections.
Z <Zero page) This attribute is used for sections that are ·ccessed via a processor-dependent short addressing Mode, such as the ZS on-chip regist·rs.
A (Absolute> Sections with this attribute have been located .,t an absolute ·ddress.
Th· overlap attributes specify how sections with the same name and sam· access attributes are to b· handled. Sections can be unnamedi all unnamed sections are treated as if they have the same na~e. The overlap attributes are mutually
exclusive and · section may have only QDI of them.
Zilog Object File Utilities
A-2
MUFOM FILE FORMAT
Appendix A
HUFCM FILE FORMAT
S (Separate) All sections with this attribute will be kept separate ·h·n located in the output file. This is th· default overlap attribute.
C <Concatenate) Concatenate (combine into a single contiguous chunk) all sections with the sa~· name and attributes. This ·ttribute performs the equivalent of th· linker's -n com~and line option.
E (Equal Length) Overlap all sections with the same name and attributes; the size of the resulting section is the size of its components. Produce an error mess·ge if they rave different sizes.
H (Maximum Length) Overlap all sections with the same name and attributes; the size of the resulting section is the size of its largest component.
U (Unique Names> Only one section with the same name and attributes is permitted.
A.2.3. Allocetion Attributes.
The two allocation attributes determina the order in ~hich sections are selected.
~ (Now> Selected sections with the "n" attribute will be merged before all sections with the "p" attribute. This is th· default allocation attribute.
P (Postpone) Selected sections with the "p" attribute will be merged after all sections with the "n" attribute. When sections are selected via mliok's -· command-line argument, any "postpone" sections selected are placed after any "now" sections selected by the same sub-argument. Th~s,
-s code data
selects first the s·ctions mith name "code" and attributes that include Nn", then sections with n·~· "coda" and attribute "p", than sections with na~· "data" ana attribute "n", and finally sections with n2ma "datz" and attribute "p".
Zilo; Cbject File Utilities
MUFOM FILE FORMAT
Appendix A
MUFOM FILE FORMAT
A.3. SYMBOLS AND VARIABLES
MUFOM modules associate nu~erical values with constructs called ~ICiigl911 ~hich are represented as a letter in the set ~-z followed by a hexadecimal nu~ber1 the iD~i!· In Zilog·s reP.resentation1 variable indices are restricted to 16 bits. (Avoiding the letters A-F as variable identifiers means that variables can always be distinguished from hexadecimal numbers.>
Values are assigned to variables with the MUFOM n45n (Assign) co~mand.
Some of the variables in a ~UFOM module are associated with sections, and their index is the same as the corresponding section number. These variables, and their meanings, are:
S Size of the corresponaing section.
L Location of the corresponding section. The Lvariable is present only for absolute sections.
R "Relocation base" for t~e section. In absolute sections this is initialized to the section's location; in relocatable sections it represents the address at which the section will eventually be locgted.
P "Program Counter" for the section. In the load data of the ~odule1 the ?-variable represents the next location at which code will De loaded. Space can be reserved within a section by ~ssigning to the P-variable.
Other variables in a MUFO~ module are associated with symbols. The value assigned to the variable is the value of the corresponding asse~bly-language symbol.
The symbol variables are:
~
N-variab1es are associated with 12·!1 symbols
(names). It is possible to h~v· more th~n one N-
variable in a module with the sa~· name; this
occurs when two modules containing locPl symbols
with the same name are linked together.
Zilo~ Cbject File Utilities
A-4
~UFCH FILE FORMAT
Appendix A
~UFOM FILE FORMAT
I
I-variables are associated with ~lQbll (Internal)
sy~bols. These are symbols defined within a moaule that can be referred to in other ~oaules
that are linked witn it.
X X-variables are associated with l~iiCQJl refer-
x- ences to ;lobal sy~bols in otner ~odules.
variables are never assignee values.
As implement·~ gt Zilog, the N, 1, and X variables of eny object module are allocated conti~uously starting from NO, 10, ano XO. The variable inciiees do DQ!1 however, necessarily correspond to the order of the variebles in the symbol table. !t is only guaranteea that there will be no gaps in tha numbering.
A.3.3. Other V·riabl··
Finally, there are two other kinds of variables in MUFOM modules:
G
There is at most one u-variable in a ~UFCM ~odule;
its value is the 1Dit¥ gg~ol or starting address
of the program.
w k-variables are Qworkino registers". we is used
as temporary storage for range-checking. Tha
other w-variables are used by the assembler to
hold the v~lues of fQCWICQ tl11CID·IJ' that is1 symbols that are used before they are aefinad.
A.4. LOCAL USAGE
A.4.1. Co···nts
There are two $Pecial local us~ges for comments. Comment levels C-3 are used for specific kinds of debugging and link m~o information. CoMment levels 100Chax>-102 are used for separating the object file into regions containing different kincis of information.
A.4.1.1. Infor·atlon Co···nts
Information comments contain error messa;es,_ source code, and link ~ap information. They allow symbolic debuggers and
other programs {including m~wm;1 mo~, and mlii1> to display
~ore infor~ation than would otherwise ba present in the object file.
m
A-5
Zilog Object File Utilities
MUFCM FILE FORMAT
Appendix A
MUFO~ FILE FCR~AT
0
Comment level 0 is used for error ~··s~ges.
1
Comment level 1 cont~ins comments of the followin;
for~s:
:FILE Innnn hnnnn Or.r.nnnnnnnnnn filename(library) Input file information. I, ~, and 0 precede the I-variable origin, N-variable ori;in, and creati~n date respectively.
:SECT isecn osecn L=nnnnnnnn S=nnnn~nnn ifile,secname:atts Link map information on input sections.
filename: line-number Compiler filename and line number from .FILE and .LINE assembler statements.
2 Comment level 2 contains assembler source lines.
3 Comment level 3 contains assembler listing format information, in comments of the form:
filename: linenumber Assembler source file and line number.
:PAGE
marks a new listing page.
A.4.1.2. Ob~ect Fil· legions
Three special comments divide the object file into regions, as shown in Figure A-1. The region before the first such comment is the file header, containing the MS, AO, and OT
com~ands.
1CO A comment of level 100Chex) introduces the section table, containing ST, SA, ASL, and ASS commands and the input file and link map comments.
101 A comment of lev·l 101Chex) introduces the symbol
table, containing Nl1 NX, NN, ASI, ASh, ASG, wx,
AT, LI1 Li, RI, and TY commands.
102 A co~ment of l·v·l 1C2Chex) introducas the load
data re;ion, conteining ASw, sa, ASP, LO, LR1 IR,
and RE commands and comments containing error mes-
sages, assembler source, and so on.
Splitting object files i~to these ragions ~akes the lir.ker and other utilit~es more efficient by marking parts of the file that do not neeo to De processed.
Zilo; Object Fil~ Utilities
A-6
MUFOM FILE FORMAT
Appenaix A
MUFC~ ~ILE FOR~AT
Section Table
Symbol Table
Program Section
Module End
Figure A-1. Cbject Module Regions
A.4.2. Expreeeions
The MUFOM standard permits the use of expressions of great generality in many places in the object files. ·hat the linker and other utilities ·ill 1;;1;l is1 in general, more restricted; and ·h·t th· assembler, linker, and other utili-
ties mill 1mi1 is more restricted still.
In this section, codes are used to indicate the kinds of
expressions that are acceptable.
Except when only
hexnumbers are permitted, ill functions are allowed. The
codes are:
Hnn
any hexnumber of at most nn bits.
R
R-variables.
·
w-variebles.
x
x-variables.
As a rule, other vari~bles are not used in ex~ressions; all utilities expana them into eqyivalent expressions involving
A-7
Zilo; Object File Utilities
~UFCM FILE FORMAT
Appendix A
MUFOM F!LE FCRMAT
R, w, and X variables. WOO is used purely as a temoorary
for limit checking; other ~ variables are useo by the assem-
blers for forward references.
Indices Addresses Numbers SA
co
AS(R,P) ASW LR IR RE WX
All variable indices and section numbers are H16·s. All addresses are limited to 32 bits {H32 RWX). Nu~bers up to 80 bits CH80) are permitted in assignments and LR commands. Section Alignment: H32, Page Size: H32.
H32. H80 RX. H32 R. H80 RWX. HSO RwX. Relocation 8ase: H8C Rwx, Nu~ber Of Sits: H8. H32. ~80 RwX.
A.4.3. Co···nd Order
There are some local restrictions on the orderin; of MUFOM commands. Observing these restrictions makes it possible to avoid retaining information that will not be needed later.
A.4.3.1. Section Information
All the information for a single section is grouped together, with the ST command first, followea by the SA, ASL and ASS commands in any order. The ASS command must be present, and the section size must be a hexnumber.
Zilog Object File Utilities
A-8
MUFOM FILE FOR~AT
Aopandix A
MUFOM FILE FOR~AT
A.4.3.2. Variable Information
All the information for a single va~iable is groupeo together, with the ~v command first.
An NI, or N~ command is always followed immediat·ly by the corresponding AT command (if any) anQ ASI or ASN command.
An NX command is always followed immediately by the correspondin~ AT and kX commanas, if any.
w-variables must be assigned to before th·y are referenced.
R-variables are assi;ned implicitly. No existing utilities ~enerate ASR commands.
A.5. LIBRARY EXTENSIONS
The following commands have been added for maintaining libraries. A library file consists of a li2titX b!l~lt' the modules in the library, and a libtltX m1;. The li~CICX biiQlt consists of an LS command, an optional OT command,
and an LE command. The li~t·tX m1; is at the end of· the
file, and consists of a series of LM commands followed by an LE command. The library extension commands are always in character form. Modules contained in a library may either be in character form or binary form.
. LS map_position "," lib_name " "
Library Se;in: the first commana in a library.
The hexnumber m1;_;91ili9D is the position in the
file of the libr5ry map, which consists of LM commands f ollomed by an LE command.
The LB command may be followed by a OT eom~and with the date the library was createci or last modified. This is followed by an LE1 the MUFCM modules contained in the library, and the library map.
. LE " "
Library fna: marks the end of the library header and th· library map.
. LM
position
"X" (", "
" , " size "," m_name
x_name)·) " "
(","
I_name)·
(","
ZiloQ Object File Utilities
MUFOH FILE FORMAT
Jppendix A
Library Module: indicates the position in the library of · module, its size in bytes, its name1 the n·~·s of the symbols <I-variables) it defines1 and the names of the external symbols CXvariables> it references.
A.6. EXAM,LE: Zilog MUFOM Modul·
Figure A·2 shows an actual character-form MUFOM module produced by a Zilog MUFO~ Cross-asse~bler. Line nu~bers hav· been ·dded in parentneses along the right ~argin for reference purposes.
Zilog Object File Utilities
A-10
MUFC~ FILE FORMAT
Appendix A
MUFO~ FIL! FCR~AT
~5Z80Q,Q6link.o.
0119350522102255.
A~Q81021L.
C00100117---- S·ction Tebla ST001X1A104code. ASLOo,oo. ASSCC131. s1c1,w,A,04d·t·. ASLC1131. ASS01,oc.
s102,s,w,c,A,06CO~MON.
ASL0213D. ASS02110. C00101116---- Symbol Table ----. NNC11Cabc_store. £SNC1r31. NN0210SbcShl. As111c2,2s. NI00103div. ASI00100. NI01109dvd_store. ASICl1133. NNQ3,Q4div1 · ASNC3109. NNC4104div2. ASN0411B. NI02109mpy_stor·· ASI0213D. ATI02100100110102.
AS~100.
C00102,1A---- Progr·· Sections ----.
saoo.
AS?co,co. LREBCS44402100003E1087CB13CB12C81SC814CD280CDA1BCO E0421C3DC20900C1EB223300223DOOC9ESB7E042223100!1C9. SB01. ASP01131. LROOOOOOOOOOCOOOOOOOOOOOOO. 5802. AS!)0213D.
"'e.CCFF120BSS (uninitialized d·ta> s·ction.
Fi9ure A-2. ~UFCM Module
(1)
(2)
(3)
(4)
CS>
(6)
(7)
CS)
(9)
C1 O> ( 11) <12) ( 13)
(14)
<15) (16) <17> <18) (19) (20) <21) (22> (23) (24) (25) <26) (27) <28)
(29)
(30)
(31)
<32) (33>
(34)
(35)
(36)
(37) (38) (39) (40) C41> (42)
III
Lines <1> - C3) define the module he·der. The module header is standard ·cross all Zilog MUFOM object modules.
MB - Module 3egin o oe·ines the start of a MUFCM object module. o Defines the target orocassor type (optional). o Defines the object ~odule·s name (optional).
A-11
Zilo; Object Fil· Utilities
~UFO~ FILE FORMAT
Appendix A
MUFOM FILE FORMAT
OT - ~ate o Defines the object module's creation time and date.
AD o
o
o
Address D·scriptor Defines the number of bits per Minimum Addressable Unit (MAU). Defines the mexirn~m siz· of the target processor's address space in MAUs (optional>. Defines the order of the address's MAUs within tre object code.
Lin~ (4) - MUFOM comment commands are used in the Zilo; MUFOM imPl·~·ntation to delimit the different parts of the object module. Lin· (4) aelimits the start of the Section Table. Comments are prefixed by the MUFOM CO command.
Lines (5) - C13) are the section t~ble. ~ach section within
an object module will have a set of description commr.nds in this table. MUFOM commands that are used in the section table region of the mo~ule are
ST - Section.Type. for a given section, defines
o Section type attributes (optional) o Section name (optional>
SA - Section Ali~nment. For a given section, defines o Section alignment (given in MAUs) (optional) o Maximu~ section size (optional)
AS o
Assignment ·ssigns values to section variables S - section siz~ L - location of section·s lower boundary
(optional)
Line (14> - The start of the symbol t~ble.
Lines <15) - (30) - The symbol table contains declarations for all of the global, external, and local symbols within the object ~odule. Assign~ent of absolute values or expressions to symbols, definition of symbol type, and definition of symbol attributes ~re kept here. The ~odule's entry point, if any, is also specified here. ~UFOM commands used in the symbol table region of the object file are
NI - Name Internal (Global) Symbol o Declares an external symbol, a table entry number, a name length count, and gives its name.
NX - Name External Symbol o Declares an external symbol1 a table entry number, a n!me length count, and gives its name.
NN - Name Local Symbol o Declares a local symbol, a table entry number, a
Zilog Object File Utilities
A-12
MUFOM FILE FORMAT
Appendix A
MUFOM FILe FORMAT
name length count, and gives its name.
AT o
o o
o
Symbol Attribute. Cef ines for a given sy~bol Type table entry
Lexical level (optional) Size (used for common symbols) (optional)
Alignment <used for processors where variables must be aligned on specific addresses> (optional)
AS - Assignment. o Assigns a value or expression to a sy~bol.
TY - Type. Defines a tYP· table entry.
WX - Weak External.
o Defines a given symbol as a weak external·. o Provides a default value or expression to be
assigned if the symbol is not resolved.
Line C31> The MUFOM comment used to delimit the start of the program portion of the object module.
Lines C32) - C41> The code, or load data, portion of the object module is kept in this region. The heading "Program Sections" refers to the MuFCM sections which are the logical divisions of the program. MUFOM commands used within this region to aef ine the code are
SB - Section Begin o Declares that the following code belongs to the
specified section.
LO - Load. o Contains object code.
LR - Load Relocate. o Contains code ana relocation expressions.
IR - Initialize Relocation Base o Assigns a value to e relocation letter.
RE - Replicate. o Repeat the immediately follo·ing LR expression a
specified number of times.
AS - Assignment o Assigns a value or an expression to a section's ? (load pointer> variable.
-*---A--··-a-k---e-x-t-e-r-n-a-l---·-i-l-l--be resolved with a global
definition if one is present; otherwise it receives the default value specified in the ~X command.
A-13
Zilo; Object File Utilities
MUFOM FILE FORMAT
Appenaix A
~UFOM FILc FORMAT
Line (42> The end of a MUFOM object '-odul9 is delimitec by the ME Com:nand.
Zilo; Object File Utilities
A-14
Appendix 8
HEX TEKTRO~IX
FOR~AT
8.1. RECORD FORMAT
field name: field size:
Record Format
SR
RL
CS1 ****DATA**** CS2 ~NO
1
2
2
0-255
2 1
Figure 8-1. Tektronix Hex Record Format
SR--Start Record Field (frame 0) The ASCII slash character (/) is used to signal the start of a record.
AODR--Load Address Field <frames 1 to 4) The starting loc·tion in me,ory to/from which data will
be lo·ded/s&ved.
RL--Record Length Fiela (frames S and 6)
Tha number of data bytes in the record is represented by two ASCII hexadecimal digits.
CS1--First Checksum Field (frames 7 and 8) This checksum is the 8-bit sum of the six hexadecimal digits that make up the load aadress and record length.
OATA--Oata Field (fr·mes 9 to 9 + (RL * 2) -1)
Each pair of frames in the data field represents a data byte, where each frame contains the ASCII representation of a 4-bit value.
C
S
2-
-Second
(RL *
Checksum 2)) + 1)
Field
(frames (9 +(PL* 2)) and (9 .+
This checksum is the sum of the 4-bit hexadecimal
values of the digits in the data fiela, ~odulo 236.
s-1
Zilog Object File Utilit~es
TcKTRONIX HEX FORMAT
Appendix 8
TEKTRONIX HEX FORMAT
ENO--End of Recora Field (frame (9 + (RL * 2)) + 2>
The ASCII code for a carriage return is used to signal
the end of a record.
1.2. END-OF-FILE RECORD FORMAT
The end-of-file record has a record length of o, the address
field containing the entry point address, and no data or second checksum.
Example B-1: /4F000013<CR>
1.3. AIORT RECORD FORMAT
The do·nload operation can be aborted by the host system sending an abort record, consisting of two slashes followed by en error message and carriage return.
Exa~ple B-2: //PROGRAM ABORTED <CR>
8.4. NINOSHAKINQ FOR DOWNLOAD/UPLOAD
mload and msend us· th· Tektronix handshakini protocol, by default, for each format. Since there is no handshaking used in conjunction ·ith th· Intel Hex format, the -h option must be used to turn it off whenever the -1 option is specified. The handshaking protocol consists of three signals:
o "O" No error o "7" Bad recordi retransmit o "9"
Abort
These signals are sent by th· target to the host when downloaaing and vie· versa when uploading.
It is recommended that handshaking always be used to prevent erroneous ~ata transmission.
Zilow Cbjact File Utilities
Appendix C INTEL HEX FORMAT
C.1. RECORD FORMAT
Record Format
field name: field size:
SR RL AOOR RT ****DATA**** CS
1 2
4
2
0-255
2
Figure C-1. Intel ~ex Record Form~t
SR--Start Record Field (frame Q)
The ASCII character colon C:> is used to si;n~l the
start of a record.
RL--Record Length Field (frames 1 and 2) The number of d·ta bytes in the record is representeG by two ASCII hexadecimal digits.
AODR--Load Address Field (frames 3 to 6) Four ASCII hexadecimal digits representing zeros or the address to/from which data will be loaded/saved.
RT--Reeord Type Field (fra~es 7 and 8) The ASCII hexadeci~al digits in this field specify one of the record types sho~n in Table C-1:
Table C-1. Intel Hex Record Types
Record Type
Description
00
D~ta Record
01
end-of-File Record
02
Extended Address Record
03
Start Adoress R~cord Centry point)
The address specified by the Extanded Address Record is left-shifted four bits (representing the four most significant bits in a 20-bit ~ddress), and added to all subsequent
C-1
lilo~ Object File Utilities
IlllTEL HEX FORMAT
Aopenciix C
INTEL HEX FORMAT
type 00 (Oat· Record) addresses.
OATA--Oata Field Each.pair of frames in the data field represents a data
byte, where each fra·· contains the ASCII reoresenta-
tion of a 4-bit velue.
CS--ChecksuM Field
This field contains the ASCII representation of the two·s complement of the sum of the data bytes Ceach
pair of data field frames converted to one binary byte), modulo 2S6.
Zilo~ Object File Utilities
c-z
A~pen~ix J ERROR ~fSSAGES
D.1. INTRODUCTION
each utility describes errors with ;learly stated error ~es sages. There are three types of errors that can occur: process errors, input format errors, and internal errors.
The action taken due to an error depends on the severity of the error and the utility being executed. Most errors do not interrupt object ~odule processin;.
0.1.1. Proc··· Errors
Process errors occur cue to either incorrect command U$age, or otherwise-correct co~mand usage on inappropriate data
(for example, attempting to load a relocatable file>.
Process errors can occur
o
~hile attempting to interpret the co~mand line used to
invoke the utility.
o During the processing of object modules.
o.z. COMMON ERRORS
The following errors are common to most or all of the utilities:
0.2.1. Co···nd Line Errors
-<letter> argument filena~· missing -<letter> argument number missing garbage after nu~eric arg~ment: -<letter>
unrecognized command-line argu~ent -<letter> -<letter> argument inconsistent with previous arguments extra output file~ame ignored
0-1
Zilo; Cbject File utilities
ERROR MESSAG~S
0.2.2. Other Errors
Appenoix 0
ERROR MESSAGES
OPEN error on file <file can't handle libraries division by zero no free storage left value out of ran~e
na~a>
An OPE~ error ~eans either that a specifieo input file does not exist or is protectac agE-inst reading, or that a specified output file is protected against wr~tin~.
"No tree storage left" means that there are too many sy~ bo ls, sections, or filas in the input.
The "division bi zero" and "value out of ran99" errors represent errors in assembly-language code ~hich could not
be detected by the assembler because they involved relocatable or external symbols.
D.3. COMMAND-SPECIFIC ERRORS
0.3.1. Mlib Errors
The errors unique to ~lib are
unknown option '<latter>' Can not read '<filename>' Must have exactly one of 'd,q,r,t,x· No archive file specified Only one option allowed in 'd,q,r,t,x' archive file '<filename>' not found missing argument for 'f' options ~ultiple '<letter>' options 3uildLM - '<filaname>' ~ot archive for~at SuildLM - Out of ~emory 3uildLM - no m~tchin9 LE Creat~lib - Can not create '<filename>· Out of memory WritaAll - Can not cre~te ·<filename>' WriteAll - Can not open '<fil~na~~>· can't handle libraries q_mlib - Cut of memory x_mlib - Can not c~eate '<filename>'
Zilog Object File Utilities
0-2
ERROR M:SSAGES
ERROR M:SSAGES
D.3.2. ·link Errors
The errors uniQua to mlio~ or·
- without attribute 1n s·l·ct string <arg>
-m not implemented in relocat~ble link
- t ar~ument adoress missing
-<sy~bol> =value with no symbol
-<symbol> langtr with no symbol
-t cannot relocat· absolute section
-t with no sections selected
+symbol: symbol missing
=valu·: value missing
E section at~ributa: sections must have same size
U section attribute: sections must be unique
attempting to merge
absolute section
<section descriptor>
with reloc. section <section descriptor>
entry point <symbol> undefined
file <filename> has different address order
illegal character in select string <arg>
multiply-defined global symbol <symbol>
nested -f files not allowed
output file <filename> is also an input file
symbol <symbol> not absolute
undefined external <symbol>
The only utility that generates warnings, as opposed to
errors, is mliD~·
~arnings represent ~nusual conditions
th~t may, nevertheless, be what you intended to produce.
The -· option to mlio~ suppresses these warning messages.
address space overflow at <address>
attemptin; to load into ass section at <address>
no section information for section <number> no section information in input file <filenBme> null select: <arg> null unselect: <arg> section overlap
<section descriptor> <section descriptor> symbol <symbol> redefined by -g argument
The "section overlap" error, in particular, can occur when making files with separate add~ess spaces for instruction and data. The "no section information" errors occur when linking files ~enerated as output from ~l~l~ ~ithout t~e -· option.
0-3
Zilog Cbject Fil~ Utiliti~s
ERROR MESSAGES
Appendix 0
ERROR MESSAGES
D.3.4. ·list Errors
There ara no errors actually uni~ue to mlil1' but errors
included as level-C commants by the ~·sembler are ~ncluded in the listing.
D.3.S. mlo·d Errors Tha errors unique to JlQJg are
section <name> is relocetable
D.3.6. ·lord·r Error·
The errors unique to mlgcg1c are
<symbol> multiply defined in <filename> and <filename> cannot open <filename> cycle in data: extern overflow module overflow out of memory symbol space overflow text speca overflow
D.3.7. protocol Errors
too many files write record error
writ· first ·o· error
cannot open <filename>
conflict -d & -u options
duplicate -<letter> options invalid -r option - <string> invalid -t option - <string>
no file specified unknown handshaking code <number> fro~ Re~ote unrecognized option <string>
D.4. INPUT FILE FORMAT ERRORS
Input Fil· Format Errors are primarily associated with the p·rsing and execution of ~UFOM commands Cas opposed to utility program command lines) within · ~UFOM object file. These errors are displayed in one of two for~ats:
Zilog Object Fil· Utilities
D-4
ERROR ~ESSAGES
Appendix 0
E~ROR MESSAGES
input file format error: HCE at line 9 of foo.o
or
input fil· format error: HCE at line 9 of foo.o MCE: missing command-er.d period byte Oxa of the MUFOH com~and:
NNC11xxx1?04foo1.
The second, more descriptive format is obtainable via tr· v4 option in mliD~· If the input file is in binary form, tre line number is replaced by an offset in characters from the b·Qinning of the file.
It is generally impossible to get format errors unless a MUFCM file has bean Qarbled, or ;ener&tad incorrectly. This usually is caused by a bug in one of the utilities, and should be called to the attention of your Zilog representative.
~-5
Zilog Object File Utilities
ERRCR ~ESSAGES
Appendix 0
ERROR MESSAGES
Table o-1. Input Fil· Format Errors.
ZHO: 2 hex digits reQuired AOR: address > 32 bits ARG: not enough ar~uments for function ASG: multiple assi~nments to G-variables C·ntry points) ASI: variable index of ASI does not match previous NI ASL: ASL eommano before or without ST ASS: ASS command before or without ST ASX: assignment to X-variable is illegal CMO: command expectea/undefined com~and EOF: unexpected ena-of-fil· in <filenam·> EXP: expr·ssions not permitted in download EXU: expression stack underflow IAF: invalid archive format IAH: invalid archive head·r ILF: invalid library format LIS: library command inside module ~AU: can·t handle MAU length other than 8 bits MCE: missing command-enc period MCP: missing comma or period MCS: missing com~·nd start MEX: ~issing expression MHB: M! commana missing ~RO: missing relocation offset HRP: missing ·)' MSA: SA com~ana mith no expressions MST: no ST for section <number> N16: number > 16 bits N32: number > 32 bits N80: number > 80 bits ~AN: not a number NNR: not a number or R-variable STL: strin~ > 127 characters long TYU: unexpected TY-component TYV: N-variabl· or T-number expected UAT: AT command do·· not apply to previous variP.ble
UEX: unknown/invalid item in expression UFN: unknown operator/function ULO: invalid load item USA: SA command before or without ST UXP: unexpected refer~nce to P-variabl· VAR: undefined variable
x:x: too many expressions
XN8: MB command not at beginning of fil· XRP: unexpected .,.
D.S. INTERNAL ERRORS
Internal errors ~enerally indicate a bu; in one of the utilities; they r·present conditions that should not occur, and
Zilog Object File Utilities
0-6
i:RRCR MESSAG!:S
A;:>penaix 0
E~ROR MESSAGES
should be called to the attention of your Zilog representative.
READ error on file <filename> <upload/domnload> read error write error core dumpe<i
The "core dumped" error is a host oper~ting syste~ error which usually means that something drastic is ~ro~g with the program, but it can also occur if a program runs out of free storage and fails to detect the fact.
III
D-7
Zilo~ Object Fila Utilitias
GLOSSARY
absolute code: Cod· ~hose position within memory has been defined end whose address referenc·s have been assigned values relative to the code's position.
absolute loader: A Qrocess ~hich can load one or more sections of absolute code only at the locations specified by the sections.
checksum: A semi-random function of a file's cor.tents. If a file is copied and the checksum of the copy is different from that of the origin£l, there has been an ·~ror in copying.
code: A program or segment thereof ~hich has been encoded in a language useabl· by a processor. Often used loosely as a synonym for "load data". See Object Code, Source Coda.
co··and: Control information for a linker or loader. It is to be distinguished from Load Data.
external r·ferenc·: The usage, within ~ module, of a sy~bol which is defined outside that module. An i~ported global definition.
file: A MUFOM object file is a structure defined by th· host operatin; system containing one or more MUFOM object modules. Files containing more than one module are considered to be libraries.
global definition: The definition within a Nodule, of a symbol which may be used outside that mooule.
identifier: A string of characters ~hich uniQualy represents a defined entity s~ch as a symbol, option or command.
lib~ary: A set of two or more object modules.
linker: A program that combines object modules into a sin;le object module satisfying links between the object ~odules.
load data: Oata (including machine instructions) to be loaded into a processor's memory.
load pointer: A pointer for a section which is dynamically ~sintained by the loader. It indicates where the next it·~ of the code is to be loaded. It is initialized to a starting load address.
G-1
Zilog Object File Utilities
GLOSSARY
GLOSSARY
~LOSSARY
local symbol: A symbol which is accessible only within a sin;le module.
machine code: Code that is directly understandable by a processor 1 s hardware. Since digital processors are binary in nature, machine code consists of binery numbers. Sae Object Code.
module: A pro;ram or portion thereof, usually in the form of a separate file. See Object Mociule, Source Module.
object code: Code (Load Data) contained in an Object Module.
object format: The language in which Object Modules are specified.
object ·odule: A MUFOM object module is a set of sections of absolute or relocat~ble machine coda, to;athar with ancillary commands. Sea Modul~, Source Module.
prelink: A link session that precedes one or more other link sessions over the same object code.
program: An algorithm and associated data. A series of operations to be Performed over some given data.
process: A program executed by a processor.
relocatable code: Code that consists of machine code and relocation commands. Relocation commands allow address references within the machine code to be reevaluated if the machine code is repositionad in memory. Relocatable code is to be distinguished from absolute code.
section: A part of a program with ~ncillary information
(commands) which becomes a segment when loaded.
segment: A conti~uous region in memory with arbitrary boun· oaries which may contain machine coda.
source code: A pro~ram in some human-readable program~ing
language. Source code is translated into Object Code by a
compiler or assembler.
source module: A Module containing Source Code.
symbol: A label or name that represents a numeric value.
symbol resolution: The process of replacing an external reference with its globally defined value.
Zilo9 Cbject File Utilities
G-2
Zilog General PPPI
Information I.I.II
·2i1J a., General Terms and Conditions of Sala
ORDERING PRODUCTS
Orders placed for Zilog components should include the component part number as shown in the example below. The part number consists of a T prefix, followed by a five-digit part number, two-digit numerical speed designator, alpha package designator, alpha operating temperature range designator, and an environmental flow designator (e.g., Z8032008VSC or Z0840006VEC).
ORDERING CODES
PACKAGE
IC PACKAGE CODES
A= VQFP (Very Small QFP) C = Ceramic Side Brazed D= Cerdip E = Ceramic Window F = Plastic Quad Flat Pack G = Ceramic PGA (Pin Grid Array) H = SSOP (Slim Small Outline Package) I = PCB Chip Carrier K = Cerdip Window L = Ceramic LCC (Leadless Chip Carrier) p = Plastic DIP S = SOIC (Small Outline Integrated Circuit) V = Plastic Leaded Chip Carrier
SUPPORT TOOL PACKAGE CODES
T = Emulation Module Z = Support Tools
ENVIRONMENTAL
PREFERRED C = Plastic Standard E = Hermetic Standard
LONGER LEAD TIME A = Hermetic Stressed B = 883 Class B Military D = Plastic Stressed
TEMPERATURE
PREFERRED Standard: S = 0°C to +70°C
LONGER LEAD TIME Extended: E = -40°C to +100°C (-40°C to +105°C for Consumer Products) Military: M =-55°C to +125°C
EXAMPLE
Z84C001 OPEC is a CMOS 8400, 10 MHz, Plastic, -40°C to +100°C, Plastic Standard Flow.
:=:: Z 84COO 10 P E C XXXX 111 Temperature Package Speed ' - - - - - - - - - - Product Number
' - - - - - - - - - - - Zilog Prefix
T-1
General Terms and Conditions of Sale
1. Terms: Net 30 days
2. Order/Shipment Minimums:
A. Commercial Standard Product
$500 per order $250 per line item and/or shipment release 100 piece minimum quantity/line item per release in multiples of tube, tray, or reel count
B. Custom ROM Products
10,000 unit order minimum for 18-, 28-, or 40-pin devices One-half of the units to be scheduled within ninety (90) days $3,000 mask charge for each new ROM
C. Non-Standard Product
Windowed Products } Systems Development Boards Emulators Software
100 piece minimum waived $250 line item minimum still applies
D. Tape and Reel
44-lead PLCC 500 units per reel minimum 68-lead PLCC 250 units per reel minimum
E. Trays
44-lead QFP =96 pieces per tray. 80-lead QFP =50 pieces per tray. 100-lead QFP =50 pieces per tray.
= 48-lead VQFP 60 pieces per tray.
100-lead VQFP = 90 pieces per tray.
F. Technical Publications $100 per order or shipment release
T-2
·atJ a., General Terms and Conditions of Sale
3. Cancellation, Reschedule, and Failure to Release
If buyer cancels shipment of any purchase order or a portion of any purchase order or reschedules without prior agreement by Zilog, any purchase order or a portion of any purchase order, the following charges may, at Zilog's option, be assessed and invoiced by Zilog:
Product Type Commercial
*Notice Received Prior to Acknowledgment Shipping Date
0 - 30 Days
Military
O - 90 Days
ROM*
0 - 90 Days
Remote Control End Products
0 - 90 Days
Note: · Notice shall be calculated from the customer request date.
Cancellation Reschedule Charges
No cancellations allowed. 100 per cent Invoice charges apply.
No cancellations allowed. 100 per cent Invoice charges apply.
No cancellations allowed. 100 per cent Invoice charges apply.
No cancellations allowed. 100 per cent Invoice charges apply.
ROM Code Variations
Because ROM Coded Products are custom products made specifically for Buyer, Buyer agrees thatZilog may ship a quantity of such ROM Coded Products which is five percent (5%) more or less than the quantity ordered and that such variation will be accepted as delivery in full and paid for by Buyer.
Zilog price quotations and acknowledgments are dependent upon quality and schedule. If the Buyer does not release the full quantity quoted and acknowledged within the time frame stated on the quotation, Seller reserves the right to either invoice the full quantity quoted and acknowledged within the time frame stated on the quotation or to invoice for a higher price in accord with Seller's price schedule for the lower quantity actually released by
Buyer.
4. Product Availability
Product availability is a function of a constantly changing market and manufacturing conditions, therefore Zilog cannot guarantee availability. Please contact your local Zilog sales office or sales representative for current product availability information.
Information for products not listed in this selection guide can be obtained from your local Zilog sales office, or sales representative. The point of delivery will be determined by the Zilog sales order acknowledgment.
5. Cost Adders
Special processing of both commercial and military products to the customer's specifications (non-Zilog standard) is available in the following circumstances on most Zilog products: top mark, packing instructions, shipping
instructions, one lot date code per shipment, stepping qualification, and certificate of conformance (C of C). Read Only Memory (ROM) mask charges are required for ROM coded products. For information regarding charges and
possible delays which special processing may have on delivery dates, contact your local Zilog sales office or sales representative. All prices quoted apply to orders placed worldwide, excluding VAT, tax, freight, duties, and exchange rate variations.
T-3
·2HJ0, General Terms and Conditions of Sale
Special Services and Prices
Military Grade Components - The following cost adders should be used if standard military specifications are not adequate for a given requirement:
Condition
... ~ ~
Generic Data
1. Group "A" - sample Electrical Test, per generic part type
$100.00
2. Group "B" - Assembly Construction Test, per generic part type
3. Group ·c· -12 week results on JAN product/Die Life Test -
52 week results on non-JAN product
$100.00 $100.00
4. Group "D" - 26 week results on JAN product/Package Life Test 52 week results on non-JAN product
$100.00
5. Generic Data Pack - Includes Groups A, B, C, D data
$300.00
Customer Specific Data
1. Group "A" - done on customer parts
2. Group "B" - done on customer parts
3. Group ·c· - done on customer parts (per device type).
Delivery increased eight weeks.
4. Group ·o· -done on customer production lot, excludes
destructive test part cost of 50 parts at customer's price. Delivery increased three weeks.
$100.00 $600.00 $1200.00
$2500.00
Additional Requirements
1. Particle Noise Detection (PINO) testing Minimum charge per line item, per part, per order. Lot acceptance will conform to 883 Rev. C method 2020.5 allowing up to 25% lot defective maximum, pass on 1% PDA.
2. X-ray screening per Mil Std 883C or 5.00 per unit
3. Lead finish other than solder dipped
4. Special top marking requirements or 2.50 per unit
$250.00 minimum or 25.00 per unit
$500.00 minimum
Contact Factory $250.00 minimum
T-4
General Terms and Conditions of Sale
Special Services and Prices
The final character in the DESC drawing number ("X") refers to the type of lead finish the parts must have. An "X'' indicates that any lead finish (Solder= "A," Tin Plate= "B," Gold Plate= "C'1 is acceptable. It is the standard policy of Zilog to only offer the "A" lead finish which is solder dipped (ex. 5962-8551802QA).
Notes: In general, if special processing is required and is not listed above, it Is not available. However, call your local Zilog sales office to discuss requirements as necessary.
Condition
Initial customer qualification of products in place of Zilog qualification report.
Customer pays for qualification sample
Customer Change Notification 1. Notification to customer of product tooling revision 2. Notification to customer of process change
0.1 o per unit 0.1 o per unit
3. Customer approval of process tooling revision
0.30 per unit
4. Customer approval of process change
0.20 per unit
Special customer top mark & special customer logo (case by case basis for some requests) Special customer burn-in in place of Zilog standard Special customer final test Final test data recording Test data recording before and after burn-in Special shipping containers Special shipping container marking in place of Zllog standard Special safety stock in place of Zilog standard Special shipping routine to point-of-title transfer in place of Zilog standard Date code requirement in place of Zilog standard Certificate of Origin with shipment Certificate of Conformance
0.1 o per unit
0.50 per unit 0.50 per unit 1.00 per unit 2.00 per unit Cost plus 15% 0.05 per unit 0.20 per unit 0.10 per unit 0.05 per unit 20.00 per shipper 5.00 per shipper
T-5
General Terms and Conditions of Sale
Special Services and Prices
Condition
Tape and Reel (where available) 44-lead PLCC 500 units per reel minimum 68-lead PLCC 250 units per reel minimum
Special tube stoppers - rubber plugs
Special 100% full functional final test at hot temperature before bum-in
~
0.1 Oper unit 0.20 per unit 0.05 per unit
0.05 per unit
Special die orientation - die bonded upside down and rotated 90 degrees from JEDEC standards
Special back mark instruction
0.1 Oper unit 0.10 per unit
Special shipping box - parts to be shipped in a box lined with conductive material or static shielding bags
"Dry Pack" of PLCCs in place of normal
0.05 per unit 0.30 per unit
Special tube orientation indicator mark Parts requiring retest
Programming Z8/0TP Failure Analysis
0.05 per unit
10.00 per military unit, 0.30 per commercial unit
500.00 minimum per order
200.00-600.00 for military, depending on test requirements
100.00-400.00 for commercial, depending on test requirements
Single date code per shipment/line item
500.00 minimum or 5.00 per unit
T-6
'P2iUd:- General Terms and Conditions of Sale
Shipping Requirements for Plastic Packaging
Trays:
A 100 VQFP: 90/tray 450/bag 48 VQFP: 60/tray 600/bag 64 VQFP: 160/tray 800/bag
F 100 QFP: 66/tray 660/bag 132 QFP: 36/tray 360/bag 144 QFP: 24/tray 240/bag 80 QFP: 66/tray 660/bag 44 QFP: 96/tray 960/bag
H
20 SSOP: 66/tray
20 PCB Chip Carrier (C3) (not shipping yet): 40/rail 28 PCB Chip Carrier (C3) (not shipping yet): 40/rail 44 PCB Chip Carrier (C3) (Not shipping yet): 30/rail
p
18 Plastic DIP: 20 units/rail
20 Plastic DIP: 20 units/rail
28 Plastic DIP: 15 units/rail
40 Plastic DIP: 10 units/rail
48 Plastic DIP: 10 units/rail
52 Plastic DIP: 10 units/rail
64 Plastic DIP: 10 units/rail
s
18 SOIC 40 units/rail 1000/bag
20 SOIC: 38 units/rail 950/bag
28 SOIC: 27 units/rail 1080/bag
v
44 PLCC: 25 units/rail 500/bag
68 PLCC: 20 units/rail 400/bag
84 PLCC: 15 units/rail 225/bag
Tape and Reel:
s
18 SOIC: 2,000/reel
20 SOIC: 2,000/reel
v
44 PLCC:
500/reel
68 PLCC: 250/reel
84 PLCC: 250/reel
Dll
T-7
ZILOG DOMESTIC SALES OFFICES AND TECHNICAL CENTERS
INTERNATIONAL SALES OFFICES
CALIFORNIA Agoura .......................................................... 818-707-2160 Campbell ........................................................ 408-370-8120 Irvine .............................................................. 714-453-9701 San Diego ...................................................... 619-658-0391
COLORADO Boulder ........................................................... 303-494-2905
FLORIDA Clearwater ...................................................... 813-725-8400
GEORGIA Duluth ............................................................. 404-931-4022
ILLINOIS Schaumburg ................................................... 708-517-8080
MINNESOTA Minneapolis .................................................... 612-944-0737
NEW HAMPSHIRE Nashua ........................................................... 603-888-8590
OHIO Independence ................................................ 216-447-1480
OREGON Portland .......................................................... 503-274-6250
PENNSYLVANIA Horsham ......................................................... 215-784-0805
CANADA Toronto ........................................................... 905-850-2377
CHINA Shenzhen ................................................... 86-755-2220869
86-755-2220873 Shanghai ..................................................... 86-21-415-0691
86-21-415-8158 Rm. 5204
GERMANY Munich ........................................................... 49-8967-2045 SOmmerda .................................................... 49-3634-23906
JAPAN Tokyo ........................................................... 81-3-5272-0230
HONGKONG Kowloon ...................................................... 85-2-2723-8979
KOREA Seoul ............................................................. 82-2-577-3272
SINGAPORE Singapore .......................................................... 65-2357155
TAIWAN Taipei .......................................................... 886-2-741-3125
UNITED KINGDOM Maidenhead .................................................. 44-628-392-00
TEXAS Austin ............................................................. 512-343-8976 Dallas ............................................................. 214-987-9987
© 1995 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subjectto change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, lnc. makes no warranty, express, statutory, implied or by descriplion, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Ziiog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
Zilog, Inc. 21 O East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 91()..338-7621 FAX 408 370·8058 Internet: http://www.zilog.com/zilog
llJI
Z·1
SALES REPRESENTATIVES AND DISTRIBUTORS
U.S., CANADIAN & PUERTO RICAN REPRESENTATIVES
ALABAMA
KANSAS
Huntsville Alabama Bits, Inc .................................... (205) 534-4020
Olathe Advanced Technical Sales ..................... (913) 782-8702
ARIZONA
MARYLAND
Scottsdale Thom Luke Sales, Inc .............................. (602) 451-5400
Pasadena Electronic Engineering & Sales ............... (410) 255-9686
CALIFORNIA
Irvine Infinity Sales ............................................ (714) 833-0300
Santa Clara Phase II Technical Sales ......................... {408) 980-0414
San Diego Addem .................................................... (619) 729-9216
MASSACHUSETTS North Reeding Advanced Technical Sales ..................... (508) 664-0888
MICHIGAN Novi Rathsburg Associates, Inc...................... (810) 615-4000
COLORADO
MINNESOTA
Englewood Thorson Rocky Mountain ........................ (303) 773-6300
Mlnneepolls Professional Sales for Industry ................ (612) 944-8545
CONNECTICUT
MISSOURI
Wallingford Advanced Technical Sales ..................... (508) 664-0888
Bridgeton Advanced Technical Sales ..................... (314) 291-5003
FLORIDA Altamonte Springs Semtronic Associates, Inc...................... (407) 831-8233 Cleerweter Semtronic Associates, Inc...................... (813) 461-4675 Fort Lauderdale Semtronic Associates, Inc...................... (305) 731-2484
GEORGIA Norcross BITS ........................................................ (404) 564-5599
ILLINOIS Hoffman Estates Victory Sales, Inc.................................... (708) 490-0300
IOWA Cedar Rapids Advanced Technical Sales ..................... (319) 393-8280
NORTH CAROLINA Huntsville BITS ........................................................ (205) 881-2900 Raleigh BITS ........................................................ (919) 676-1880
NEW JERSEY Cherry Hiii Tritek ....................................................... (609) 667-0200
NEW MEXICO Albuquerque Quatra & Associates ............................... (505) 296-6781
NEW YORK Fairport L-Mar Associates, Inc............................. {716) 425-9100
OHIO Independence Rathsburg Associates, Inc...................... (216) 447-8825
Z-2
SALES REPRESENTATIVES AND DISTRIBUTORS
OKLAHOMA
Tulsa Nova Marketing, Inc................................ (918) 660-5105
WASHINGTON
Kirkland Phase II Technical Sales ......................... (206) 821-8313
OREGON
Portland Phase II Technical Sales ......................... (503) 643-6455
WISCONSIN
Broolcffeld Victory Sales, Inc.................................... (414) 789-5770
TEXAS Austin Nova Marketing, Inc................................ (512) 343-2321 Dallas Nova Marketing, Inc................................ (214) 265-4630 Houston Nova Marketing, Inc................................ (713) 240-6082
UTAH Salt Lake City Thorson Rocky Mountain ........................ (801) 264-9665
CANADA British Columbia J-Squared Technologies, Inc.................. (604) 473-4666 Ontario J-Squared Technologies, Inc.................. (905) 672-2030 Ottawa J-Squared Technologies, Inc.................. (613) 592-9540 Quebec J-Squared Technologies, Inc .................. (514) 694-8330
PUERTO RICO RloP/edms Semtronic Associates, Inc...................... (809) 766-0700
Dll
Z-3
SALES REPRESENTATIVES AND DISTRIBUTORS
U.S. AND CANADIAN DISTRIBUTORS
NATIONWIDE Newark Electronics ................................ 1-800-367-3573 Zeus Electronics .................................... 1-800-524-4735
ALABAMA Birmingham Newark Electronics ................................. (205) 979-7003 Huntsville Anthem Electronics ................................. {205} 890-0302 Arrow Electronic~ .................................... 205 837-6955 Newark Electronics ................................. 205 837-9091 Mobile Newark Electronics ................................. (205) 471-6500
ARKANSAS Little Rock Newark Electronics ................................. (501) 225-8130
ARIZONA Phoenix Anthem Electronics ................................. {602} 966-6600 Arrow Electronic~ .................................... 602 431-0030 Newark Electronics ...... ............. ..... ......... 602 864-9905 Tempe Anthem Electronics ................................. (602) 966-6600 Arrow Electronic~ .................................... (602) 431-0030 Newark Electronics ................................. (602) 966-6340
CALIFORNIA Arcadia Newark Electronics ................................. (818) 445-1420 Calabasas Arrow Electronics .................................... (818) 880-9686 Chatsworth Anthem Electronics ................................. (818) 775-1333 Chula Vista Newark Electronics ................................. (619) 691-0141 Fremont Arrow Electronics .................................... (510) 490-9477 Garden Grove Newark Electronics ................................. (714) 893-4909 Hayward Arrow Electronics .................................... (510) 487-8416 lrvlne Anthem Electronics ................................. {714} 768-4444 Arrow Electronics .................................... 714 587-0404 Zeus Electronics ..................................... 714 581-4622
Palo Alto Newark Electronics ................................. (415) 812-6300 Riverside Newark Electronics ................................. (909) 784-1101 Sacramento Anthem Electron!cs ................................. (916) 624-9744 Newark Electronics ................................. (916) 565-1760 San Diego Anthem Electronics ................................. {619} 453-9005 Arrow Electronic~ .................................... 619 565-4800 Newark Electronics ................................. 619 453-8211 San Jose Anthem Electronics ................................. {408} 453-1200 Arrow Electronics .................................... 408 441-9700 Zeus Electronics ..................................... 408 629-4789 Santa Clara Newark Electronics ................................. (408) 988-7300 Santa Fe Springs Newark Electronics ................................. (310) 929-9722 Ventura Newark Electronics ................................. (805) 644-2265 West Hills Newark Electronics ................................. (818) 888-3718
COLORADO Denver Newark Electronics ................................. (303) 373-4540 Englewood Anthem Electronics ................................. (303) 790-4500 Arrow Electronics .................................... (303) 799-0258
CONNECTICUT
Bloomfield Newark Electronics ................................. (203) 243-1731 Norwalk Zeus Electronics ..................................... (203) 852-5411 Wallingford Arrow Electronics .................................... (203) 265-7741 Waterbury Anthem Electronics ................................. (203) ?75-1575
Z-4
SALES REPRESENTATIVES AND DISTRIBUTORS
FLORIDA Altamonte Springs Anthem Electronics ................................. (407) 831-0007 Clearwater Anthem Electronics ................................. (813) 538-4157 (800) 359-3522 Fort Lauderdale Anthem Electronics ................................. (305) 484-0990 Deerfield Beach Arrow Electronics .................................... (305) 429-8200 Jacksonville Newark Electronics ................................. (904) 399-5041 Orlando Newark Electronics ................................. (407) 896-8350 Plantation Newark Electronics ................................. (305) 424-4400 Tampa Newark Electronics ................................. (813) 287-1578 Lake Mary Arrow Electronics .................................... (407) 333-9300 Zeus Electronics ..................................... (407) 333-3055
GEORGIA
Duluth Anthem Electronics ................................. ~404~ 931-3900
Arrow Electronics .................................... ~~~~ ~~~~~5
Norcross Newark Electronics ................................. (404) 448-1300
IDAHO
Boise Newark Electronics ................................. (208) 342-4311
ILLINOIS Addison Newark Electronics ................................. (708) 495-7740 Arlington Heights Newark Electronics ................................. (708) 956-9270 Itasca Arrow Electronics .................................... (708) 250-0500 Zeus Electronics ..................................... (708) 595-9730 Rockford Newark Electronics ................................. (815) 229-0225 Schaumberg Anthem Electron)cs ................................. (708) 884-0200 Newark Electronics ................................. (708) 310-8980 Springfield Newark Electronics ................................. (217) 787-9972 Willowbrook Newark Electronics ................................. (708) 789-4780 (708) 654-8250
INDIANA Ft. Wayne Newark Electronics ................................. (219) 484-0766 lndianopo/ls Arrow Electronic!J .................................... ~317~ 299-2071 Newark Electronics .. .................... .. .. .. ..... 317 259-0085 317 884-0047
IOWA Bettendorf Newark Electronics ................................. (319) 359-3711 Cedar Rapids Arrow Electronics .................................... (319) 395-7230 Newark Electronics ................................. (319) 393-3800 West Des Moines Newark Electronics ................................. (515) 222-0700
KANSAS Lenexa Anthem Electronics ................................. (913) 599-1528 Arrow Electronics .................................... (913) 541-9542 Overland Park Newark Electronics ................................. (913) 677-0727
KENTUCKY Louisville Newark Electronics ................................. (502) 423-0280
LOUISIANA Metarle Newark Electronics ................................. (504) 838-9771
MARYLAND Columbia Anthem Electronics ................................. (410) 995-6640 Arrow Electronics .................................... (410) 596-7800 Hanover Newark Electronics ................................. (410) 712-6922
MASSACHUSETTS North Reading Advanced Technical Sales ..................... (508) 664-0888 Marlborough Newark Electronics ................................. (508) 229-2200 Methuen Newark Electronics ................................. (508) 683-0913 Wiimington Anthem Electronics ................................. ~508~ 657-5170 Arrow Electronics .. ........ ........ .......... .. ...... 508 658-0900 Zeus Electronics ..................................... 508 658-4776 Woburn Newark Electronics ................................. (617) 935-8350
Z-5
SALES REPRESENTATIVES AND DISTRIBUTORS
U.S. AND CANADIAN DISTRIBUTORS
MICHIGAN Grand Rapids Newark Electronics ................................. (616) 954-6700 Livonia Anthem Electronics ................................. p13~ 347-4090
~~~~~ ~g~:~~~g Arrow Electronics ....................................
Oak Park Newark Electronics ................................. (810) 967-0600
(810) 968-2950 Plymouth Arrow Electronics .................................... (313) 462-2290 Saginaw Newark Electronics ................................. (517) 799-0480
MINNESOTA Eden Prairie Anthem Electronics ................................. (612) 946-4826 Arrow Electronics .................................... (612) 941-5280 Minneapolis Newark Electronics ................................. (612) 331-6350 St. Paul Newark Electronics ................................. (612) 631-2683
MISSISSIPPI Ridgeland Newark Electronics ................................. (601) 956-3834
MISSOURI Maryland Heights Newark Electronics ................................. (314) 298-2505 St. Louis Arrow Electronics .................................... (314) 567-6888
MONTANA Helena Newark Electronics ................................. (406) 443-6192
NEBRASKA Omaha Newark Electronics ................................. (402) 592-2423
NEVADA Las Vegas Newark Electronics ................................. (702) 597-0330 Reno Newark Electronics ................................. (702) 322-6090 Sparks Arrow Electronics .................................... (702) 331-5000
NEW HAMPSHIRE Nashua Newark Electronics ................................. (603) 888-5790
NEW JERSEY East Brunswick Newark Electronics ................................. (908) 937-6600 Mar/ton Arrow Electronics .................................... (609) 596-8000 Plnebrook Anthem Electronics ................................. (201) 227-7960 Arrow Electronics .................................... (201) 227-7880 Union Newark Electronics ................................. (908) 851-2290
Z-6
SALES REPRESENTATIVES AND DISTRIBUTORS
NEW MEXICO
Albuquerque Newark Electronics ................................. (505) 828-1878
NEW YORK
Bohemia Newark Electronics ................................. (516) 567-4200 Brookhallflll Arrow Electronics .................................... (516) 924-9400 Cheektowaga Newark Electronics ................................. (716) 862-9700 Commack Anthem Electronics ................................. (516) 864-6600 Hauppauge Arrow Electronics .................................... (516) 231-1000 Latham Newark Electronics ................................. (518) 783-0983 Liverpool Newark Electronics ................................. (315) 457-4873 Long Island Anthem Electronics ................................. (516) 864-6600 Me/ville Arrow Electronics .................................... (516) 391-1300 Rochester Arrow Electronics .................................... (716) 427-0300 Pittsford Newark Electronics ................................. (716) 381-4244 Port Chester Zeus Electronics ..................................... (914) 937-7400 WapplnllflTS Falls Newark Electronics ................................. (914) 298-2810
NORTH CAROLINA
Charlotte Newark Electronics ................................. (704) 535-5650 GtNnsboro Newark Electronics ................................. (910) 294-2142 Raleigh Anthem Electronics ................................. !9191782-3550
Arrow Electronic!3 .................................... ~~ ~~~~~
Newark Electronics ................................. 919 781-7677
OHIO Centerville Arrow Electronics .................................... (513) 435-5563 Cincinnati Newark Electronics ................................. (513) 772-8181 Cleveland Newark Electronics ................................. (216) 391-9330 Columbus Newark Electronics ................................. (614) 326-0352 Dayton Newark Electronics ................................. (513) 294-8980 Solon Arrow Electronics .................................... (216) 248-3990 Toledo Newark Electronics ................................. (419) 866-0404 Youngstown Newark Electronics ................................. (216) 793-6134
OKLAHOMA Oklahoma City Newark Electronics ................................. (405) 843-3301 Tulsa Arrow Electronic!3 .................................... (918) 252-7537 Newark Electronics ................................. (918) 252-5070
OREGON Beaverton Al.J.AAC/Arrow Electronics ....................... (503) 629-8090 Anthem Electronics ................................. (503) 643-1114 Portland Newark Electronics ................................. (503) 297-1984
PENNSYLVANIA Allentown Newark Electronics ................................. (610) 434-7171 Fort Wahington Newark Electronics ................................. (215) 654-1434 Horsham Anthem Electronics ................................. (215) 443-5150 Pittsburgh Arrow Electronic!3 .................................... (412) 856-9490 Newark Electronics ................................. (412) 788-4790
Z-7
SALES REPRESENTATIVES AND DISTRIBUTORS
U.S. AND CANADIAN DISTRIBUTORS
SOUTH CAROLINA
Greenville Newark Electronics ................................. (803) 288-9610
TENNESSEE
Brentwood Newark Electronics ................................. (615) 371-1341
Knoxville Newark Electronics ................................. (615) 588-6493
Memphis
ANrerowwarkElEelcetcrotrnoinc!icl s····.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·..·.·.·
(901) (901)
367-0540 396-7970
TEXAS
Austin Anthem Electronics ................................. {512~ 388-0049 Arrow Electronics .................................... 512 835-4180 Newark Electronics ......... ........................ 512 338-0287
carrollton Arrow Electronics .................................... (214) 380-9049 Zeus Electronics ..................................... (214) 380-4330
Corpus Christi Newark Electronics ................................. (512) 857-5621
Dallas Newark Electronics ................................. (214) 458-2528
El Paso Newark Electronics ................................. (915) 772-6367
Houston
ANrerwowarkElEelcetcrotrnoinc!icl s····.·.·.·.·.·.·.·.·.·.·.·.·.·..·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·
(713) (713)
647-6868 894-9334
Richardson Anthem Electronics ................................. (214} 238-7100
San Antonio Newark Electronics ................................. (210) 734-7960
UTAH
Salt Lake City
Anthem Electronics ................................. ~801 ~ 973-8555
ANrerowwarkElEelcetcrotrnoinc!icl s····.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·..·.·.·.·.·
801 801
973-6913 261-5660
VIRGINIA
Herndon Newark Electronics ................................. (703) 707-9010
Richmond Newark Electronics ................................. (804) 282-5671
Roanoke Newark Electronics ................................. (703) 772-6821
WASHINGTON
Bellevue ALMAC/Arrow Electronics ....................... (206) 643-9992 Newark Electronics ................................. (206) 641-9800 Bothell Anthem Electronics ................................. (206) 483-1700 Spokane ALMAC/Arrow Electronics ....................... (509) 924-9500 Newark Electronics ................................. (509) 327-1935
WEST VIRGINIA Charleston Newark Electronics ................................. (304) 345-3086
WISCONSIN
Brookfield Arrow Electronics .................................... (414) 792-0150 Green Bay Newark Electronics ................................. (414) 494-1400 Madison Newark Electronics ................................. (608) 221-4738 Mllwaulcae Newark Electronics ................................. (414) 453-9100
CANADA
Alberta Future Electron!cs ................................... (403) 250-5550 Future Electronics ................................... (403) 438-2858 British Columbia Arrow Electroni~s .................................... (604) 421-2333 Future Electronics ................................... (604) 294-1166 Manitoba Future Electronics ................................... (204) 944-1446 Montreal Arrow Electronics .................................... (514l 421-7411 Future Electronics ................................... (514 694-7710 Ontario Arrow Electronics .................................... 613 226-6903 Arrow Electronics .................................... 905 670-7769 Future Electronics ................................... 905 612-9200 Future Electronics ................................... 613 820-8313 Newark Electronics ............. ... ......... ........ 519 685-4280 Newark Electronics ......................... ........ 905 670-2888 Toronto Arrow Electronics .................................... (416) 670-2010 Quebec Arrow Electronics .................................... {418~ 871-7500 Future Electroniqs ................................... 418 877-6666 Newark Electronics ........................... ...... 514 738-4488
Z-8
SALES REPRESENTATIVES AND DISTRIBUTORS
CENTRAL AND SOUTH AMERICA
MEXICO Semiconductores Profesionales ............................................. 525-524-6123
ARGENTINA Buenos Aires YEL SRL ............................................. 011-541-440-1532
BRAZIL
Sao Paulo Nishicom ......................................... 011-55-11-535-1755 Graftec ....................................................... 011-572-2727 DSD Microtechnology Distributors ............ 305-563-8665
ASIA-PACIFIC
AUSTRALIA
KOREA
R&D Electronics ....................................... 61-3-558-0444 ENC-Korea ................................................. 822-523-2220
GEC Electronics Division ........................ 61-2-638-1888 MEMEC, Ltd .............................................. 822-518-8181
CHINA Beijing China Electronics Appliance Corp....... 86-755-335-4214 TLG Electronics, Ltd ................................ 85-2-388-7613
HONGKONG Electrocon Products, Ltd......................... 85-2-481-6022 Components Agent, Ltd ........................... 85-2-487-8826 Maxisum, Ltd ............................................ 85-2-410-2780 MEMEC, Ltd ............................................. 85-2-410-2777
MALAYSIA Kuala Lumper ...........,. ............................... 60-3-703-8498 Penang L.T. Electronics Ltd ..................... 60-4-656-2895
NEW ZEALAND GEC Electronics Division ......................... 64-9-526-0107
· PHILIPPINES Alexan Commercial .................................. 63-2-241-9493 Cinergi Tech & Devices (Phils), Inc......... 63-2-817-9519
INDIA
Bangalore Maxvale .................................................. 91-80-556-6761 Zenith Technologies Pvt. Ltd................. 91-80-558-6782
Bombay Zenith Technologies Pvt. Ltd................. 91-22-494-7457 Maxvale .................................................. 91-22-830-0959
New Delhi Maxvale (S) Pte. Ltd ............................... 91-11-622-5122
SINGAPORE Cinergi Technology & Devices Pte. Ltd...... 65-778-9331 Eltee Electronics Ltd................................... 65-283-0888 MEMEC, Ltd................................................ 65-222-4962
TAIWAN (ROC) Acer Sertek, Inc..................................... 886-2-501-0055 Asec lnt'I. Corporation ........................... 886-2-786-6677 MEMEC, Ltd........................................... 886-2-760-2028 Promate Electronics Co. Ltd.................. 886-2-659-0303
INDONESIA Jakarta
Cinergi Asiamaju ..................................... 62-21-7982762
THAILAND Eltee Electronics Ltd................................ 66-2-933-7565
JAPAN
Tokyo Teksel Co., Ltd ....................................... 81-3-5467-9000 lnternix Incorporated .............................. 81-3-3369-1105 Kanematsu Elec. Components Corp...... 81-3-3779-7811
Osaka Teksel Co., Ltd .......................................... 81-6368-9000
Z-9
SALES REPRESENTATIVES AND DISTRIBUTORS
EUROPE
AUSTRIA Vienna EBV Elektronik GMBH .......................... 43-222-8941-774 Avnet/Electronic 2000 ........................... 0043-1-9112847
BELGIUM Antwerp D & D Electronics PVBA ............................ 32-3-8277934 Zaventem EBV Elektronik ............................................. 322-7209936
DENMARK Brondby Ditz Schweitzer AS ...................................... 4542-453044 Lynge Rep Delco .................................................. 45-35-821200
ENGLAND Berkshire Future Electronics ................................... 44-753-521193 Gothic Crellon ......................................... 44-734-787848 Macro Marketing ..................................... 44-628-604383 Kent Arrow Electronics ...................................... 44-732-74039 Lancashire Complementary Technologies Ltd .......... 44-942-274731
FINLAND Espoo Yleiselektroniikka ...................................... 358-0-452-621
FRANCE Cedex A2M ........................................................ 331-395-49-113 CCI Electronique ....................................... 331-46744700 Champs sur Mame EBV Elektronik ......................................... 331-646-88600 Massy Reptronic SA ............................................. 331-60139300
GERMANY
Berlin EBV Elektronik GMBH ................................. 030-3421041 Avnet/Electronic 2000 ................................. 030-2110761 Burgwedel EBV Elektronik GMBH ................................. 05139-80870
Camberg
Thesys A/E ................................................. 49-6434-5041
Castrop
Future GMBH .............................................. 02305-42051 Dortmund Future GMBH .............................................. 02305-42051 Duesseldorf Avnet/Electronic 2000 ............................... 0211-9200385 Thesys/AE ................................................... 0211-536020 Erfurt Thesys ....................................................... 0361-4278100
Erkrath Avnet/Electronic 2000 ............................... 211-92003-85
Frankfurt EBV Elektronik GMBH ................................... 069-785037 Avnet/Electronic 2000 ................................. 069-9738041 Future GMBH .............................................. 06121-54020 Thesys/AE ..................................................... 06434-5041 Gerllngen Avnet/Electronic 2000 ................................. 7156-356190 Hamburg Avnet/Electronic 2000 ............................... 040-64557021 Leonberg EBV Elektronik GMBH ................................. 07152-30090 Muenchen Avnet/Electronic 2000 ................................. 089-4511004 EBV Elektronik GMBH ................................... 089-456100 Future GMBH ................................................ 089-957270 Thesys A/E .................................................. 89-99355866
Nuemberg Avnet/Electronic 2000 ............................... 0911-9951610 Neuss EBV Elektronik GMBH ................................. 02131-96770
Qulckbom
Future GMBH ................................................ 4106-71022
Rauxel
Future GMBH .............................................. 02305-42051
Stuttgart Avnet/Electronic 2000 ............................... 07156-356190 Future GMBH .............................................. 0711-830380 Thesys/AE ................................................. 0711-9889100 Weinbach EBV Elektronik GMBH ................................... 036-426486
Z-10
SALES REPRESENTATIVES AND DISTRIBUTORS
ISRAEL RDT ........................................................... 972-35483137
ITALY Milano Avnet EMG S.R.L. ............................... 0039-295-343600 EBV Elektronik ..................................... 0039-2-66017111 Silver Star ..................................................... 02-66-125-1 Firenze EBV Elektronik ....................................... 0039-55-350792 Roma EBV Elektronik ....................................... 0039-6-2253367 Modena EBV Elektronik ....................................... 0039-59-344752 Napoli EBV Elektronik ..................................... 0039-81-2395540 Torino EBV Elektronik ..................................... 0039-11-2161531
NETHERLANDS EBV Elektronik ........................................... 313-465-2353
NORWAY Bexab Norge ............................................... 47-63833800
POLAND Warsaw Gamma Ltd ............................................. 004822-330853
RUSSIA Woronesh Thesys/lntechna ........................................... 0732553697 Vyborg Gamma Ltd ................................................. 81278-31509 St. Petersburg Gamma Ltd ................................................. 812-5311402
SPAIN Barcelona Amitron-Arrow S.A. ................................ 0034-3-4907494 Madrid Amitron-Arrow S.A. ................................ 0034-1-3043040
SWEDEN Bexab Sweden AB ................................... 46-8-63088-00 Rep Delco Sweden AB ............................ 46-8-63086-00
SWITZERLAND Dietikon EBV Elektronik GMBH ........................... 0041-1-7401090 Lausanne EBV ElektronikAG ............................... 0041-21-3112804 Regensdorf Eurodis AG ............................................. 0041-1-8433111
UKRAINE Kiev Thesys/Mikropribor ..................................... 44-434-9533
PORTUGAL Amadora Amitron-Arrow....................................... 0035-1-4714806
IDI
Z-11
LITERATURE GUIDE
ze· MICROCONTROLLERS · CONSUMER FAMILY OF PRODUCTS
Databooks By Market Niche
Part No Unit Cost
ZS- Microcontrollers Databook
Product Spsclfications Z86B07 CMOS Z8 8-Bit MCU for Battery Charging and Monitoring Z86C05/C07 CMOS Z8 8-Bit Microcontroller ZB6E07 CMOS ZB B-Bit OTP Microcontroller ZB6C11 CMOS ZB Microcontroller ZB6C12 CMOS ZB In-Circuit Microcontroller Emulator Z86C21 BK ROM Z8 CMOS Microcontroller ZB6E21 CMOS Z8 BK OTP Microcontroller ZB6C61/62/96 CMOS ZB Microcontrollers ZB6E61/6316K/32K EPROM CMOS ZB Microcontrollers ZB6C63/64 32K ROM Z8 CMOS Microcontrollers ZB6C91 CMOS ZB ROMless Microcontroller ZB6C93 CMOS Z8 Multiply/Divide Microcontroller ZB61171717 Z8 B-Bit CMOS OTP/ROM Microcontrollers
DC-8305-03
$5.00
Appl/cation Notes On-Chip Oscillator Design Designing aLow-Cost Thermal Printer
Support Product Specifications Z0860000ZCO Evaluation Board ZB6C1200ZEM Emulator ZB6E0700ZDP Adaptor Kit ZB6E2100ZDF Adaptor Kit ZB6E2100ZDP Adaptor Kit ZB6E2100ZDV Adaptor Kit Z86E2101ZDP Adaptor Kit ZB6E2101ZDV Adaptor Kit ZB6C6100TSC Emulator ZB6C6200ZEM Emulator ZB6C9300ZEM Emulator ZB SSeries Emulators, Base Units and Pods
Additional Information Zilog's Superintegration'" Products Guide General Terms and Conditions of Sale Zilog's Sales Offices, Representatives and Distributors Literature Guide & Third Party Support Vendors
L-1
·2H Id:>
LITERATURE GUIDE
ZS9 MICROCONTROLLERS - CONSUMER FAMILY OF PRODUCTS Databooks By Market Niche Infrared Remote OR) Controllers Databook
P10ductSp1clflt:aUons Z86L03/L06 Low Voltage CMOS Consumer Controller Processor Z86L29 6K Infrared (IR) Remote (ZIRCj Controller Z86L70/L71/L72/L75/L76 Zilog IR (ZIRC") CCP"' Controller Family Z86L73/74/77 24/32K ROM Infrared Remote Controller (ZIRCj Z86E72/E73/E74/77 Zilog IR (ZIRCj CCP"' Controller Family Z86C72/76 Zilog Infrared Remote Controller Family (ZIRC'") Z86L7816K, 20-Pin Zilog Infrared Remote Controller (ZIRC'")
AppllcaUon Nots Beyond the 3Volt Limit X-10 Compatible Infrared Remote Control
Support Product Spsclllcatlons Z86C50000ZEM Emulator Z86L7100ZDB Emulator Board Z86L7100ZEM ICEBOX'" In-Circuit Emulator Board
Additional Information Zilog's Superintegration'" Products Guide Literature Ordering Guide Zilog's Sales Offices, Representatives and Distributors
Part No DC-8301-()4
Unit Cost $5.00
L-2
LITERATURE. GUIDE
za· MICROCONTROLLERS - CONSUMER FAMILY OF PRODUCTS
Databooks By Market Niche
Part No
Unit Cost
Discrete ZS- Microcontrollers
Product Specifications Z86C03/C06 CMOS ZS® S-Bit Consumer Controller Processors Z86E03/E06 CMOS Z8® 8-Bit OTP Consumer Controller Processors ZS6C04/C08 CMOS Z8® S-Bit Low Cost 1K/2K ROM Microcontrollers Z86E04/E08 CMOS Z8® 8-Bit OTP Microcontrollers Z86C07 CMOS ZS® S-Bit Microcontroller Z86E07 CMOS Z8® S-Bit OTP Microcontroller Z86C30/C31 CMOS ZS® S-Bit Consumer Controller Processors Z86E30/E31 CMOS ZS® 8-Bit OTP Consumer Controller Processors Z86C40 CMOS ZS® 4K ROM Consumer Controller Processor Z86E40 CMOS Z8® S-Bit OTP Consumer Controller Processor
DC 8318-02
$5.00
ZIP Microcontrollers Application Notes Timekeeping with the ZB®
Using The Zilog ZS6C06 SPI Bus
DTMF Tone Generation Using the ZS® CCP'" Serial Communications Using the Z8® CCP'" Software UART The Versatile ZS6COS: Three Key Features of this Z8® MCU
The Z86C08 Controls aScrolling LED Message Display Interfacing LCDs to the ZS® Microcontroller
Support Product Specifications and Third-Party Vendors ZS6C0800ZCO Evaluation Board ZS6C0800ZDP Adaptor Kit ZS6C1200ZEM Emulator ZS6E0600ZDP Adaptor Kit ZS6E0700ZDP Adaptor Kit Z86E3000ZDP Adaptor Kit Z86E4000ZDF Adaptor Kit ZS6E4000ZDP Adaptor Kit Z86E4000ZDV Adaptor Kit Z86E4001 ZDF Adaptor Kit Z86E4001 ZDV Adaptor Kit Z86CCPOOZEM Emualtor Z86CCPOOZAC Emulator Kit Z8®S Series Emulators, Base Units and Pods Third-Party Support Vendors
Additional Information Zilog's Superintegration'" Products Guide Literature Guide and Ordering Information Zilog's Sales Offices, Representatives and Distributors
L-3
LITERATURE GUIDE
zs· MICROCONTROLLERS - CONSUMER FAMILY OF PRODUCTS
Databooks By Market Niche
Digital Television Controllers
Product Specifications Z89300 Series Digital Television Controller Z86C27/97 CMOS Z8®Digital Signal Processor Z86C47/E47 CMOS ZS® Digital Signal Processor Z86127 Low Cost Digital Television Controller Z86128/228 Line 21-Closed-CiiJJtion Controller (L21 C"') Z86227 40-Pin Low Cost (4LDTC"') Digital Television Controller
SupportProductSpsclf/catlons Z86C2700ZCO Application Kit Z86C2700ZDB Emulation Board Z86C2702ZEM In-Circuit Emulator
Additional Information Zilog's Superintegration"' Products Guide Literature Guide and Ordering Information Zilog's Sales Offices, Representatives and Distributors
Part No DC-8308-01
Unit Cost $5.00
Telephone Answering Device Databook
DC-8300-03
ProductSpsclflcatlons Z89165/166 (ROMless) Low-Cost DTAD Controller (Preliminary)
Z89167/169 Z89168 (ROMless) Enhanced Dual Processor Tapeless TAM Controller (Preliminary) Development Guides
Z89165 Software Developer's Manual
Z89167/169 Software Developer's Manual Technical Notes
Z89165/167/169 Design Guidelines
Z89167/169 Codec Interfacing Preliminary
Controlling the Out -5V and Codec Clock Signals for Low-Power Halt Mode
Z89165/166 Input ND and Electronic Hybrid
Z89C67/C69/167/169 Low-Power Halt Mode Sequence Samsung KT8554 Codec
Watch-Dog Timer For TAD Applications
Zilog LPC Words Listing
Support Product Specifications
Z89C5900ZEM Emulation Module
Z89C6500ZDB Emulation Board
Z89C6501ZEM ICEBOX"' In-Circuit Emulator
Z89C6700ZDB Emulator Board
Z89C6700ZEM ICEBOX'" Emulator Board
Additional Information
Zilog's Superintegration'" Products Guide
Literature Ordering Guide
Zilog's Sales Offices, Representatives and Distributors
$ 5.00
L-4
LITERATURE GUIDE
zs· MICROCONTROLLERS - PERIPHERALS MULTIMEDIA FAMILY OF PRODUCTS
Databooks By Market Niche
Part No
Digital Signal Processors Databook
Product Specification Z89321/371/39116-Bit Digital Signal Processor
Application Notes Using the Z89321/371/391 CODEC Interface Z89321/371/391 Interprocessor Communication
Support Product Specification Z89371 OOZEM ICEBOX"' In-Circuit Emulator -371
Additional Information General Terms and Conditions of Sale Zilog's Sales Offices, Representatives and Distributors Literature Guide and Ordering Information
DB95DSP0105
Unit Cost
$ 5.00
Keyboard/Mouse/Pointing Devices Databook
ProductSpeciflcatlons Z8602/14 NMOS Z8® 8-Bit Keyboard Controller Z8615 NMOS Z8® 8-Bit Keyboard Controller Z86C15 CMOS ZB® 8-Bit MCU Keyboard Controller Z86E23 ZB® 8-Bit Keyboard Controller with BK OTP Z86C04/C08 CMOS Z8® 8-Bit Microcontroller Z86E08 CMOS ZB® 8-Bit Microcontroller Z88C17 CMOS ZB® 8-Bit Microcontroller Z86C117/717 Z8® 8-Bit Microcontroller Z86217 ZS® 8-Bit Microcontroller
Application Notes Z8602 Keyboard Z86C17 In-Mouse Applications
Support Product Spsc/flcatlons and Third Party Support Z0860200ZCO Evaluation Board Z0860200ZDP Adaptor Kit Z86C0800ZCO Evaluation Board Z86C0800ZDP Adaptor Kit Z86C1200ZEM Emulator Z86E2300ZDP Adaptor Kit Z86E2301ZDP Adaptor Kit Z86E2300ZDV Adaptor Kit Z86E2301ZDV Adaptor Kit
Additional Information Zilog's Superintegration'" Products Guide Literature Guide and Ordering Information Zilog's Sales Offices, Representatives and Distributors
DC-8304-01
$ 5.00
L-5
LITERATURE GUIDE
za· MICROCONTROLLERS · PERIPHERALS MEMORY FAMILY OF PRODUCTS
Databooks By Market Niche
Part No
Mass Storage Solutions
Product Specifications Z86C21 SK ROM ZS CMOS Microcontroller Z86E21 CMOS ZS SK OTP Microcontroller Z86C91 CMOS ZS ROMless Microcontroller Z86C93 CMOS ZS Multiply/Divide Microcontroller Z86C95 ZB Digital Signal Processor Z8601SData l'ath Controller Z89COO 16-Bit Digital Signal Processor
Appl/cation Nots Understanding 015 Two's Complement Fractional Multiplication (ZS9COO DSP)
Support Product Specifications Z8060000ZCO Development Kit Z86C1200ZEM In-Circuit Emulator Z86E2100ZDF Adaptor Kit Z86E2100ZDP Adaptor Kit Z86E21 OOZDV Adaptor Kit Z86E2101ZDF Conversion Kit Z86E2101ZDV Conversion Kit Z86C9300ZEM ICEBOX"' Emulator Z86C9500ZCO Evaluation Board ZB® SSeries Emulators, Base Units and Pods Z89COOOOZAS Z89COO Assembler, Linker and Librarian Z89COOOOZCC ZS9COO CCross Compiler Z89COOOOZEM In-Circuit Emulator-COO Z89COOOOZSD Z89COO Simulator/Debugger ZPCMCIAOZDP PCMCIA Extender Card
Additional Information Zilog's Superintegration"' Products Guide Zilog's Literature Guide Zilog's Sales Offices, Representatives and Distributors
DC·8303-o1
Unit Cost $5.00
L-6
LITERATURE GUIDE
Z8 Technical Manuals and Users Guides
za· Microcontrollers User's Manual
Z86018 Preliminary User's Manual Digital TV Controller User's Manual Z89COO 16-Bit Digital Signal Processor User's Manual/DSP Software Manual Z86C9516-Bit Digital Signal Processor User Manual Z86017 PCM CIA Adaptor Chip User's Manual and Databook PLC Z89COO Cross Development Tools Brochure
zee Appllcatlon Notes
The Z8 MCU Dual Analog Comparator
Z8 Applications for 1/0 Port Expansions
Z86E21 ZS Low Cost Thermal Printer Zilog Family On-Chip Oscillator Design Using the Zilog Z86C06 SPI Bus Interfacing LCDs to the ZS X-1OCompatible Infrared (IA) Remote Control Z86C17 In-Mouse Applications Z86C40/E40 MCU Applications Evaluation Board Z86C08/C17 Controls AScrolling LED Message Display Z86C95 Hard Disk Controller Flash EPROM Interface Three ZS- Applications Notes: Timekeeping with Z8; DTMF Tone Generation;
Serial Communication Using the CCP Software UART
Part No.
UM95Z800103 DC-8296-00 DC-8284-01 DC-8294-02 DC-8595-02 DC-8298-03 DC-5538-01
Unit Cost
5.00 N/C 5.00 5.00 5.00 5.00 N/C
Part No
DC-251&-01 DC-2539-01 DC-2541-01 DC-249&-01 DC-2584-01 DC-2592-01 DC-2591-01 DC-3001-01 DC-2604-01 DC-2605--01 DC-2639-01 DC-2645-01
Unit Cost
N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
L·7
LITERATURE GUIDE
Z809/Z80009 DATACOMMUNICATIONS FAMILY OF PRODUCTS
Databooks By Market Niche
High·Speed Serial Communication Controllers Product Specifications Z16C30 CMOS Universal Serial Controller (USC'") (Preliminary) Z16C32 Integrated Universal Serial Controller (IUSC'") (Preliminary) Application Notes Using the Z16C30 Universal Serial Controller with MIL-STD-1553B Design aSerial Board to Handle Multiple Protocols Datacommunications IUSC'"/MUSC'" Time Slot Assigner Support Products and Third Party Vendor Support Z16C3001ZCO Evaluation Board Product Specification Z16C3200ZCO Evaluation Board Product Specification Z8018600ZCO Evaluation Board Product Specification ZEPMDC00001 EPM'" Electronic Programmer's Manual Product Specification Third Party Vendors Additional Information Zilog's Superintegration'" Products Guide General Terms and Conditions of Sale Sales Offices, Representatives and Distributors Literature Guide
Part No DC-8314-01
Unit Cost 5.00
Serial Communication Controllers
DC-8316-01
5.00
Product Specifications
Z8030/Z8530 Z-Bus· SCC Serial Communication Controller
Z80C30/Z85C30 CMOS Z-Bus® SCC Serial Communication Controller
Z80230 Z-Bus· ESCC'" Enhanced Serial Communication Controller (Preliminary)
Z85230 ESCC"' Enhanced Serial Communication Controller
Z85233 EMSCC'" Enhanced Mono Serial Communication Controller
Z85C80 SCSCI'" Serial Communications and Small Computer Interface
Z16C35/Z85C35 CMOS ISCC"' Integrated Serial Communications Controller
Application Notes
Interfacing Z8500 Peripherals to the 68000
SCC in Binary Synchronous Communications
Zilog SCC Z8030/Z8530 Questions and Answers
Integrating Serial Data and SCSI Peripheral Control on One Chip
Zilog ISCC'" Controller Questions and Answers
Boost Your System Performance Using the Zilog ESCCTM
Zilog ESCC'" Controller Questions and Answers
The Zilog Datacom Family with the 80186 CPU
On-Chip Oscillator Design
Support Products
Z8S1 BOOOZCO Evaluation Board Product Specification
Z8523000ZCO Evaluation Board Product Specification
Z8018600ZCO Evaluation Board Product Specification
ZEPMDC00002 Electronic Programmer's Manual Software
Additional Information
Zilog's Superintegration'" Products Guide
Sales Offices, Representatives and Distributors
Literature Guide
L-8
4'2.iU Q,.
LITERATURE GUIDE
Z808/Z8000· DATACOMMUNICATIONS FAMILY OF PRODUCTS
Data books
Z80 Family Databook Discrete ZBr Family Z8400/COO NMOS/CMOS ZBO® CPU Product Specification Z8410/C10 NMOS/CMOS Z80 OMA Product Specification Z8420/C20 NMOS/CMOS Z80 PIO Product Specification Z8430/C30 NMOS/CMOS Z80 CTC Product Specification Z8440/C40 NMOS/CMOS Z80 SIO Product Specification Embedded Controllers Z84C01 Z80 CPU with CGC Product Specification Z8470 ZBO DART Product Specification Z84C90 CMOS Z80 KIO'" Product Specification Z84013/015 Z84C13/C15 IPC/EIPC Product Specification Application Notes and Technical Articles ZBO® Family Interrupt Structure Using the Z80® SIO with SDLC Using the Z80® SIO in Asynchronous Communications Binary Synchronous Communication Using the Z80® SIO Serial Communication with the Z80A DART Interfacing Z80®CPUs to the Z8500 Peripheral Family Timing in an Interrupt-Based System with the Z80® CTC AZ80-Based System Using the OMA with the SIO Using the Z84C11/C13/C15 in Place of the Z84011/013/015 On-Chip Oscillator Design AFast Z80® Embedded Controller ZBO® Questions and Answers Additional Information Zilog's Superintegration'" Products Guide Literature Guide Third Party Support Vendors Zilog's Sales Offices, Representatives and Distributors
Part No DC·8321·00
Unit Cost 5.00
L-9
LITERATURE GUIDE
Z808/Z80009 DATACOMMUNICATIONS FAMILY OF PRODUCTS
Data books
Z180- Microprocessors and Peripherals Databook ProductSpec/Hcalions Z80180/Z8S180/Z8L180 Z180'" Microprocessor Z80181 Z181'" Smart Access Controller (SAC'") Z80182/Z8L182 Zilog Intelligent Peripheral Controller (ZIP'") Application Notes and Technical Articles Z180'" Questions and Answers Z180'"/SCC Serial Communication Controller Interface at 10 MHz Interfacing Memory and 1/0 to the 20 MHz ZBS180 System Break Detection on the Z80180 and Z181'" Local Talk Link Access Protocol Using the Z80181 Z182 Programming the MIMIC Autoecho ECHOZ182 Sample Code High Performance PC Communication Port Using the Z182 Improving Memory Access Timing in Z182 Applications Support Products Z8S18000ZCO Evaluation Board Z8018100ZCO Evaluation Board Z8018101ZCO Evaluation Board Z8018101ZA6 Driver Software Z8018100ZDP Adaptor Kit Z8018200ZCO Evaluation Board ZEPMIP00001 EPM'" Electronic Programmer's Manual ZEPMIP00002 EPM Electronic Programmer's Manual Z809 and Z80180 Hardware and Software Support Additional Information Zilog's Superintegration'" Products Guide Literature Guide Zilog's Sales Offices, Representatives and Distributors
Part No Unit Cost DC-8322·01 5.00
L-10
~2iUO:i
LITERATURE GUIDE
ZSO-JZSOOO- DATACOMMUNICATIONS FAMILY OF PRODUCTS
Databooks and User's Manuals
ZSOOO Family of Products ZBOOO Family Databook Zilog's Z8000 Family Architecture Z8001/Z8002 Z8000 CPU Product Specification Z8016 Z8000 Z-DTC Product Specification Z8036 ZBOOO Z-CIO Product Specification Z8536 CIO Counter/Timer and Parallel 1/0 Unit Product Specification Z8038/Z8538 FIO FIFO lnpuVOutput Interface Unit Product Specification Z8060/Z8560 FIFO Buffer Unit Z8581 Clock Generator and Controller Product Specification UsBr's Manuals
ZBOOO CPU Central Processing Unit User's Manual Z801 OMemory Management Unit (MMU) User's Manual Z8036 Z-CI0/28536 CIO Counter/Timer and Parallel lnpuVOutput User's Manual Z8038 Z8000 Z-FIO FIFO lnpuVOutput Interface User's Manual ZBOOO Application Notes and Military Products Application Notss Using SCC with Z8000 in SDLC Protocol SCC in Binary Synchronous Communication Zilog's Military Products Overview Additional Information Zilog's Superintegration'" Products Guide Literature Guide Zilog's Sales Offices, Representatives and Distributors
Part No
DC-8319·00
Unit Cost
5.00
ZSO Family Microprocessor Family User's Manual
UsBr's Manuals ZBO Central Processing Unit (CPU) ZBO Counter Timer Channels (CTC) ZBO Direct Memory Access (OMA) ZBO Parallel lnpuVOutput (PIO) ZBO Serial lnpuVOutput (SIO)
Additional Informal/an
Zilog's Superintegration'" Products Guide
Zilog's Sales Offices, Representatives and Distributors
Literature Guide
DC-8309-01
5.00
L-11
LITERATURE GUIDE
Databooks and User's Manuals
Z80180 Z180 MPU Microprocessor Unit Technical Manual Z280 MPU Microprocessor Unit Technical Manual Z380'" Product Specification Z380'" User's Manual Z2000 Spread-Spectrum Transceiver Advance Information Product Specification ZNW2000 PC WAN Adapter Board Development Kit User's Manual
SCC Serial Communication Controller User's Manual High-Speed SCC, Z16C30/Z16C32 User's Manual
MILITARY COMPONENTS FAMILY
Military Product Specifications
Z8681 ROMless Microcomputer Z8001/8002 Military Z8000 CPU Central Processing Unit Z8581 Military CGC Clock Generator and Controller Z8030 Military Z8000 Z-SCC Serial Communications Controller Z8530 Military SCC Serial Communications Controller Z8036 Military Z8000 Z-CIO Counter/Timer Controller and Parallel 1/0 Z8038/8538 Military FIO FIFO lnpuVOutput Interface Unit Z8536 Military CIO Counter/Timer Controller and Parallel 1/0 Z8400 Military Z80 CPU Central Processing Unit Z8420 Military PIO Parallel lnpuVOutput Controller Z8430 Military CTC Counter/Timer Circuit Z8440/1/2/4 Z80 SIO Serial lnpuVOutput Controller Z80C30/85C30 Military CMOS SCC Serial Communications Controller Z84COO CMOS Z80 CPU Central Processing Unit Z84C20 CMOS Z80 PIO Parallel lnpuVOutput Z84C30 CMOS Z80 CTC Counter/Timer Circuit Z84C40/1/2/4 CMOS Z80 SIO Serial lnpuVOutput Z16C30 CMOS USC Universal Serial Controller (Preliminary) Z80180Z180 MPU Microprocessor Unit Z84C90 CMOS KIO Serial/Parallel/Counter Timer (Preliminary) Z85230 ESCC Enhanced Serial Communication Controller
Part No
DC-8276-04 DC-8224-03 DC-6003-03 PS953800104 DC-6021-00 UM95Z800101
Unit Cost
5.00 5.00 N/C 5.00 N/C N/C
DC-8293-02
5.00
DC-8350-00
5.00
Part No Unit Cost
DC-2392-02 N/C
DC-2342-03 N/C
DC-2346-01
N/C
DC-2388-02 N/C
DC-2397-02 N/C
DC-2389-01
N/C
DC-2463-02 N/C
DC-2396-01
N/C
DC-2351-02 N/C
DC-2384-02 N/C
DC-2385-01
N/C
DC-2386-02 N/C
DC-2478-02 N/C
DC-2441-02 N/C
DC-2384-02 N/C
DC-2481-01
N/C
DC-2482-01
N/C
DC-2531-01
N/C
DC-2538-01
N/C
DC-2502-00 N/C
DC-2595-00 N/C
L-12
LITERATURE GUIDE
GENERAL LITERATURE
Catalogs, Handbooks, Product Flyers and Users Guides
Superintegration Master Selection Guide 1994-1995 Superintegration Products Guide Quality and Reliability Report ZIA"' 3.3-5.5V Matched Chip Set for AT Hard Disk Drives Datasheet ZIA ZIAOOZCO Disk Drive Development Kit Datasheet Zilog Hard Disk Controllers - Z86C93/C95 Datasheet Zilog Infrared (IR) Controllers - ZIRC'" Datasheet Zilog V. Fast Modem Controller Solutions Zilog Digital Signal Processing - ZS9320 Datasheet Zi log Keyboard Controllers Datasheet Z380'" - Next Generation Z80®/Z180'" Datasheet Fault Tolerant ZS® Microcontroller Datasheet 32K ROM ZS® Microcontrollers Datasheet Zilog Datacommunications Brochure ZS9300 DTC Controller Family Brochure Zilog Digital Signal Processing Brochure Zilog ASSPs - Partnering With You Product Brochure Zilog Wireless Products Datasheet Zilog ZS604 Cost Efficient Datasheet Zilog Chip Carrier Device Packaging Datasheet Zi log Database of IR Codes Datasheet Zilog PCMCIA Adapter Chip ZS6017 Datasheet Zilog TelevisionNideo Controllers Datasheet Zilog TAD Controllers - Z89C65/C67/C69 Datasheet Zilog ZS7000 Z-Phone Datasheet Zilog 1993 Annual Report Zilog 1994 Annual Report
Part No
DC-5634-01 DC-5676-00 DC-S329-01 DC-5556-01 DC-5593-01 DC-5560-01 DC-555S-01 DC-5525-02 DC-5547-01 DC-5600-01 DC-55S0-02 DC-5603-01 DC-5601-01 DC-5519-00 DC-560S-01 DC-5536-02 DC-5553-01 DC-5630-00 DC-5662-00 DC-5672-00 DC-5631-00 DC-55S5-01 DC-5567-01 DC-5561-02 DC-5632-00 DC-1993-AR DC-1994-AR
Unit Cost
N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
DIC
N/C N/C
DII
L-13
Acrobat 11.0.23 Paper Capture Plug-in