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Remote Update Intel FPGA IP User Guide

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Updated for Intel Quartus Prime Design Suite: 18.0. Describes the Remote Update Intel FPGA IP core for device reconfiguration using dedicated remote system upgrade circuitry.

IP cores, Remote Update IP core, remote update, Avalon Memory-Mapped, remote system upgrade circuitry, Intel Arria 10, Intel Cyclone 10, Arria II, Arria V, Cyclone V, Stratix IV, Stratix V

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Remote Update Intel� FPGA IP User Guide
Updated for Intel� Quartus� Prime Design Suite: 18.0

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UG-31005 | 2021.07.13 Latest document on the web: PDF | HTML

Contents
Contents
1. Remote Update Intel� FPGA IP User Guide..................................................................... 3 1.1. Avalon�-MM in Remote Update Intel FPGA IP Core..................................................... 4 1.2. Intel Arria 10 and Intel Cyclone� 10 GX Devices........................................................ 5 1.2.1. Remote System Configuration Mode............................................................. 5 1.2.2. Remote System Configuration Components................................................... 8 1.2.3. Parameter Settings.................................................................................... 9 1.2.4. Ports........................................................................................................9 1.2.5. Parameters............................................................................................. 11 1.2.6. Avalon-MM Interface................................................................................ 12 1.2.7. Enabling Remote System Upgrade Circuitry................................................. 14 1.2.8. Generating Initial RSU Image.................................................................... 15 1.3. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices...................................... 16 1.3.1. Remote System Configuration Mode........................................................... 16 1.3.2. Remote System Configuration Components................................................. 16 1.3.3. Parameter Settings.................................................................................. 17 1.3.4. Ports...................................................................................................... 18 1.3.5. Parameters............................................................................................. 21 1.3.6. Avalon-MM Interface ............................................................................... 22 1.3.7. Enabling Remote System Upgrade Circuitry................................................. 24 1.4. Cyclone IV and Intel Cyclone 10 LP Devices.............................................................25 1.4.1. Remote System Configuration Mode........................................................... 25 1.4.2. Remote System Configuration Components................................................. 25 1.4.3. Parameter Settings.................................................................................. 27 1.4.4. Ports...................................................................................................... 27 1.4.5. Parameters............................................................................................. 30 1.4.6. Remote Update Operation......................................................................... 31 1.4.7. Avalon-MM Interface ............................................................................... 33 1.4.8. Enabling Remote System Upgrade Circuitry................................................. 37 1.5. Flash Memory Programming Files........................................................................... 37 1.6. Design Examples................................................................................................. 38 1.6.1. Intel Arria 10 Remote Update Design Example............................................. 38 1.6.2. Cyclone V Remote Update Design Example.................................................. 39 1.7. Remote Update Intel FPGA IP User Guide Archives................................................... 40 1.8. Document Revision History for the Remote Update Intel FPGA IP User Guide................41

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1. Remote Update Intel� FPGA IP User Guide

Figure 1.

The Remote Update Intel� FPGA IP core implements a device reconfiguration using dedicated remote system upgrade circuitry available in supported devices. Remote system upgrade helps you deliver feature enhancements and bug fixes without recalling your product, reduces time-to-market, and extends product life. The Remote Update Intel FPGA IP core commands the configuration circuitry to start a reconfiguration cycle.
The dedicated circuitry performs error detection during and after the configuration process. When the dedicated circuitry detects errors, the circuitry facilitates system recovery by reverting back to a safe, default factory configuration image and then provides error status information.
The following figures shows a functional diagram for a typical remote system upgrade process.
Typical Remote System Upgrade Process

Control Module

receive data from network

Flash

Remote System and update the new image into Controller

New Application Image Configuration Data

Upgrade (RSU)

the flash

Development Location sent through network

Control

Flash

Module

Control Module

trigger reconfiguration

to new image using RSU IP core

RSU

IP Core

Note:

Reconfiguration to new application image
Intel recommends that you use the following Remote Update Intel FPGA IP core input clock (fMAX) values: � 10 MHz--for Arria� II and Stratix� IV devices � 20 MHz--for other supported devices

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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Figure 2.

High-Level Block Diagram of Remote System Upgrade

Passive Serial and Fast Passive Parallel Configuration Scheme

Active Serial Configuration Scheme

Active Parallel Configuration Scheme

FPGA Nios II Processor or User Logic

FPGA
(Cyclone IV E devices only) Nios II Processor or User Logic

Flash Memory
MAX II, MAX V or MAX 10

EPCS, EPCQ or EPCQ-L

Supported Parallel Flash

Note:

The remote system upgrade feature support for each configuration scheme varies between device family. For more information about the configuration scheme and the remote system upgrade feature, please refer to the configuration chapter of the respective device family handbook.
Related Information
� Remote Update Intel FPGA IP Core Knowledge Base
� Configuration Support Center
� Introduction to Intel FPGA IP Cores Provides general information about all Intel FPGA IP cores, including parameterizing, generating, upgrading, and simulating IP cores.
� Creating Version-Independent IP and Qsys Simulation Scripts Create simulation scripts that do not require manual updates for software or IP version upgrades.
� Project Management Best Practices Guidelines for efficient management and portability of your project and IP files.
� Remote Update Intel FPGA IP User Guide Archives on page 40 Provides a list of user guides for previous versions of the Remote Update Intel FPGA IP core.

1.1. Avalon�-MM in Remote Update Intel FPGA IP Core

The Avalon�-MM interface is supported in the Remote Update Intel FPGA IP core. You can only use the IP core either with or without Avalon-MM interface. You can instantiate the Avalon-MM Interface by turning on the Add support for Avalon Interface option in Remote Update Intel FPGA IP parameter editor.

Note:

The Avalon-MM support for Remote Update Intel FPGA IP core is available in Intel Quartus� Prime software version 15.0 and onwards.

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Figure 3.

Remote Update Intel FPGA IP Core Implementation with and without AvalonMM Interface
Figure shows the Avalon Remote update support architecture which consists of 2 components; Remote Intel FPGA IP core and Avalon remote update controller. If Avalon interface is enabled, the conduit interfaces of Remote Update Intel FPGA IP core will connect to conduit interface of the controller.

Avalon Remote Update Controller

Remote Update Intel FPGA IP Core

Remote Update Intel FPGA IP core without Avalon-MM Interface

Avalon Remote Update Controller

Remote Update Intel FPGA IP Core

Remote Update Intel FPGA IP core with Avalon-MM Interface
1.2. Intel Arria 10 and Intel Cyclone� 10 GX Devices
1.2.1. Remote System Configuration Mode
Remote configuration supports "Direct to application" (DTA) and "Application to Application" update. Remote configuration only supports a 4-byte address scheme so there is no support for devices with densities smaller than 128 Mbit.

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Figure 4.

Transitions Between Factory and Application Configurations in Remote Update Mode

Trigger reconfiguration & Start Address = 0 or externaly pulse nCONFIG

After POR or nCONFIG Assertion

Trigger reconfiguration & Start Address = 0 or externaly pulse nCONFIG

Note: Note: Note:

Factory Configuration

Read Start Address from Flash

Error Count <= 3 Application Configuration

Load Factory POF

Error Count > 3

Load Application Number POF

Reconfiguration & Start Address = 32
Enter Factory User Mode
Reconfiguration & Start Address > 0 and not 32

Watchdog Timeout

No Error

Enter Application

User Mode

Reconfiguration & Start Address = 32

Reconfiguration & Start Address > 0
and not 32

The CRC check on the application image is done taking only image data into consideration. Dummy bytes in programming files are not taken into account during CRC checks.
When you use low-voltage quad-serial configuration (EPCQ-L) devices, the remote update mode allows a configuration space to start at any flash sector boundary. This capability allows a maximum of 512 pages in the EPCQ-L256 device and 1024 pages in the EPCQ-L512 device, in which the minimum size of each page is 512 kilobits (Kb). Additionally, the remote update mode features an optional user watchdog timer that can detect functional errors in an application configuration.

When error occurs, the AS controller will load the same application configuration image for three times before reverting to factory configuration image. By that time, the total time taken exceeds 100ms and violates the PCIe boot-up time when using CvP configuration mode. If your design is sensitive to the PCIe boot-up requirement, Intel recommends that you do not use the direct-to-application feature.

Intel recommends that you set a fixed start address and never update the start address during user mode. You should only overwrite an existing application configuration image when you have a new application image. This is to avoid the factory configuration image to be erased unintentionally every time you update the start address.

The fallback to the factory image does not work when the last 576 bytes of the application image bitstream are corrupted. Intel recommends that you examine the last 576 bytes of the application image before triggering the application image configuration.

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1.2.1.1. Remote System Upgrade State Machine
After power-up and exit POR, the remote system upgrade registers are reset to 0 and the factory or application configuration image is loaded based on the start address stored at 0x00 to 0x1F in the configuration device or QSPI flash. The Remote Update Intel FPGA IP core enables you to perform the following remote update functions once the factory or an application image is loaded successfully:
� Switch from factory image to application image
� In DTA mode, switch from initial application image to others application image
The configuration mode (AnF) bit is by default set to 0 in the DTA mode, the AnF bit cannot be used to indicate the type (such as factory or application image) of image loaded into the FPGA. In the DTA mode, the watchdog timer is disabled by default. You cannot enable the watchdog timer in the initial or first application image loaded upon powering up the device. You can enable the watchdog timer feature when you perform remote update from the initial application image to other application image.
1.2.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
Follow these steps to switch from factory to application image or from initial application image to other application image:
1. Write the AnF bit to 1 via RU_RECONFIG register.
2. Write the start address of the application image to be loaded via the RU_PAGE_SELECT register.
3. Enable the watchdog timer settings:
a. Write the timeout value to RU_WATCHDOG_TIMEOUT register.
b. Enable watchdog timeout via RU_WATCHDOG_ENABLE register.
4. Writes RU_RECONFIG to "1" to trigger reconfiguration to application image. After successful reconfiguration, the system stays in the application configuration. If error occurs during reconfiguration, the RSU state machine falls back to the factory image.
5. Optional step. Read the configuration status via the RU_RECONFIG_TRIGGER_CONDITIONS register.
6. Write a falling edge signal to reset the watchdog timer.
7. Repeat steps 1 to 6 to perform remote update to other application image.
Note: It is optional to instantiate the Remote Update Intel FPGA IP core in the application image if you do not need to update the application image in user mode. Without this IP core instantiated in the application image, the device is still able to revert back to factory image if there is an error in loading the application image.

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1.2.2. Remote System Configuration Components

Table 1.

Remote System Configuration Components in Intel Arria 10 and Intel Cyclone� 10 GX Devices

Components Page mode feature

Details The dedicated 32-bit start address register PGM[31..0] holds the start address.

Factory configuration
Application configuration Watchdog timer
Remote update subblock Remote configuration registers

Factory configuration can be set as the default configuration setup depending on the address pointer set. The factory configuration loads into the device upon power-up. If a system encounters an error while loading application configuration data or if the device reconfigures due to nCONFIG assertion, the device loads the factory configuration. The remote system configuration register determines the reason for factory configuration. Based on this information, the factory configuration determines which application configuration to load.
Application configuration can be the default configuration setup depending on the address pointer set. The application configuration loads into the device upon power-up. The application configuration is the configuration data from a remote source and the data is stored in different locations or pages of the memory storage device, excluding the factory page.
A watchdog timer is a circuit that determines the functionality of another mechanism. The watchdog timer functions like a time delay relay that remains in the reset state while an application runs properly. Intel Arria 10 and Intel Cyclone� 10 GX devices are equipped with a built-in watchdog timer for remote system configuration to prevent a faulty application configuration from indefinitely stalling the device. The timer is a 29-bit counter, but you use only the upper 12 bits (left-most or most-significant bits) to set the value for the watchdog timer. The timer begins counting after the device goes into user mode. To ensure the application configuration is valid, you must continuously reset the watchdog reset_timer within a specific duration during user mode operation. If the application configuration does not reset the user watchdog timer before time expires, the dedicated circuitry reconfigures the device with the factory configuration and resets the user watchdog timer.
The remote update sub-block manages the remote configuration feature. A remote configuration state machine controls this sub-block. This sub-block generates the control signals required to control the various configuration registers.
The remote configuration registers keep track of page addresses and the cause of configuration errors. You can control both the update and shift registers. The status and control registers are controlled by internal logic, but are read via the shift register. The control register is 38-bits wide. For details about configuration registers, refer to the Configuration, Design Security, and Remote System Upgrades chapter in the Intel Arria 10 Core Fabric and General Purpose I/Os Handbook or the Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook.

Related Information
� Intel Arria 10 Core Fabric and General Purpose I/Os Handbook Provides more information about configuration registers of the Intel Arria 10 devices.
� Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook Provides more information about configuration registers of the Intel Cyclone 10 GX devices.

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1.2.3. Parameter Settings

Table 2.

Remote Update Intel FPGA IP Core Parameters for Intel Arria 10 and Intel Cyclone 10 GX Devices

GUI Name
Which operation mode will you be using?

Values REMOTE

Description
Specifies the configuration mode of the Remote Update Intel FPGA IP core.

Which configuration device will you be using?

EPCQ-L device

Choose the configuration device you are using.

Add support for

Enable this if you need to write configuration

writing configuration

parameters.

parameters

Add support for Avalon Interface

Enable this if you are using Avalon interface.

Enable reconfig POF checking

Not available as this option is handled by the FPGA AS

controller instead of the Remote Update Intel FPGA IP

core. The same application image is loaded for three

times before reverting to factory application image, to

ensure no unexpected system failure occurred.

1.2.4. Ports

Table 3.

Remote Update Intel FPGA IP Core Ports for Intel Arria 10 and Intel Cyclone 10 GX Devices

Name read_param
write_param
param[]

Port Input
Input
Input

Required?

Description

Read signal for the parameter specified in param[] input port and

fed to data_out[] output port.

Signal indicating the parameter specified on the param[] port
should be read. The number of bits set on data_out[] depends on the parameter type. The signal is sampled at the rising clock edge. Assert the signal for only one clock cycle to prevent the parameter from being read again in a subsequent clock cycle.

The busy signal is activated as soon as read_param is read as active. While the parameter is being read, the busy signal remains asserted, and data_out[] has invalid data. When the busy signal is deactivated and data_out[] has a valid data, another parameter can be read.

Write signal for parameter specified in param[] and with value

specified in data_in[].

Signal indicating parameter specified with param[] should be written into remote update block with the value specified in data_in[]. The number of bits read from data_in[] depends on the parameter type.

The signal is sampled at the rising clock edge. The signal should be asserted for only one clock cycle to prevent the parameter from being rewritten on a subsequent clock cycle. The busy signal is activated as soon as write_param is read as being active. While the parameter is being written, the busy signal remains asserted, and input to data_ in[] is ignored. When the busy signal is deactivated, another parameter can be written. This signal is only valid in factory configuration mode because parameters cannot be written in Application configuration mode.

Bus that specifies which parameter need to be read or updated.

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Name data_in[]
reconfig reset_timer
clock reset busy
data_out[]

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Port Input
Input Input
Input Input Output
Output

Required?

Description

A 3-bit bus that selects the parameter to be read or updated. If left unconnected, the default value for this port is 000.

Data input for writing parameter data into the remote update block.

Input bus for parameter data.

For some parameters, not all bits are used. In this case, the lowerorder bits are used (for example, status values use bits [4:0]).

If left unconnected, this bus defaults to 0. The port is ignored if the current configuration is the Application configuration.

A 32-bit bus width (4-bytes addressing configuration device, for example EPCQ-L256) in the Intel Quartus Prime software version 14.0 or later.

Yes

Signal indicating that reconfiguration of the part should begin using

the current parameter settings. A value of 1 indicates

reconfiguration should begin. This signal is ignored if the busy signal

is asserted to ensure all parameters are completely written before

reconfiguration begins.

Reset signal for watchdog timer.

Signal indicating the internal watchdog timer should be reset. Unlike other inputs, this signal is not affected by the busy signal and can

reset the timer even when the busy signal is asserted.

A falling edge of this signal triggers a reset of the user watchdog timer.

For the timing specification of this parameter, refer to the specific device handbook.

Yes

Clock input to the remote update block.

Clock input to control the machine and to drive the remote update block during the update of parameters.

This port must be connected to a valid clock.

Yes

This is an active high signal. Asserting this signal high will reset the

IP core.

Asynchronous reset input to the IP core to initialize the machine to a valid state. The machine must be reset before first use, otherwise the state is not guaranteed to be valid.

Busy signal that indicates when remote update block is reading or

writing data.

While this signal is asserted, the machine ignores most of its inputs and cannot be altered until the machine deasserts this signal. Therefore, changes are made only when the machine is not busy.

This signal goes high when read_param or write_ param is asserted, and remains high until the read or write operation completes.

Data output when reading parameters.

This bus holds read parameter data from the remote update block. The param[] value specifies the parameter to read. When the read_param signal is asserted, the parameter value is loaded and driven on this bus. Data is valid when the busy signal is deasserted.

If left unconnected, the default value for the port is 0.

continued...

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Name ctl_nupdt

Port Input

Required?

Description

The width of this bus is device-dependent. For the Intel Quartus Prime software version 14.0 and later, the bus width is 32-bit--using 4-byte addressing configuration device, for example EPCQL-256.

Yes

This port allows you to select which register to be read whenever

read_param operation is running.

� A logic high selects the Control Register--register containing the current remote update settings such as watchdog timer settings, configuration mode (AnF), and page address.

� A logic low selects the Update Register--register containing similar data as held in the Control Register, but the values are updated via write_param operation for use in next reconfiguration.

1.2.5. Parameters

Table 4.

Parameter Type and Corresponding Parameter Bit Width Mapping for Intel Arria 10 and Intel Cyclone 10 GX Devices

Bit

Parameter

Width

Comments

000

Reconfiguration trigger conditions (Read Only)

� Bit 4--wdtimer_source: User watchdog timer timeout.

� Bit 3--nconfig_source: External configuration reset

(nCONFIG) assertion.

� Bit 2--runconfig_source: Configuration reset triggered

from logic array.

� Bit 1--nstatus_source: nSTATUS asserted by an external

device as the result of an error.

� Bit 0--crcerror_source: CRC error during application configuration.

The POR value for all bits are 0.

001

Illegal Value

010 Watchdog Timeout Value

Width of 12 when writing.

The 12 bits for writing are the upper 12 bits (left-most or mostsignificant bits) of the 29-bit Watchdog Timeout Value.

When writing parameter data, data_in[11..0] corresponds to the upper 12 bits of the 29-bit Watchdog Timeout Value. For example, to set the Watchdog Timeout Value to 1, write the 12 bits of data_in[11..0] as 12'b000000000001.

Width of 29 when reading.

011 Watchdog Enable

100 Page Select

For the Intel Quartus Prime software version 14.0 and later:

� Width of 32 when reading and writing the start address.

� For active serial devices using 32-bit addressing, such as EPCQL-256, PGM[31..2] corresponds to the upper 30 bits of

the 32-bits start address. PGM[1..0] is read as 2'b0.

101 Configuration Mode (AnF)

This parameter is set to 1 in application page and is set to 0 in

factory page. In remote update mode, this parameter can be

read and written.

Before loading the application page in remote update mode, Intel recommends that you set this parameter to 1. The content of the control register cannot be read properly if you fail to do so.

110

Illegal Value

111

Illegal Value

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1.2.6. Avalon-MM Interface

1.2.6.1. Control Status Register Signals

Table 5.

Remote Update Intel FPGA IP Core Avalon-MM Control Status Register Signals for Intel Arria 10 and Intel Cyclone 10 GX Devices

Name

Width

Direction

Description

clk

Input

Clock input.

reset

Input

Reset input.

avl_csr_address

Input

Address bus.

avl_csr_read

Input

Perform a read transaction.

avl_csr_write

Input

Perform a write transaction.

avl_csr_readdata

Output

Read data from IP.

avl_csr_readdata_valid 1

Output

Indicate when read data is valid.

avl_csr_writedata

Input

Write data to IP.

avl_csr_waitrequest

Output

Waitrequest signal high indicates the core is busy.

1.2.6.1.1. Control Status Register Write Operation
To execute the write operation for the control status register, perform the following steps: 1. Asserts the avl_csr_write high. 2. Write a correct address of the register in the avl_csr_address bus. Refer to the
Register Map for register information. 3. Write data into the avl_csr_writedata bus.

Related Information Register Map on page 14

1.2.6.1.2. Control Status Register Read Operation
To execute the read operation for the control status register, perform the following steps: 1. Asserts avl_csr_read high. 2. Write a correct address of the register in the avl_csr_address bus. Refer to the
Register Map for register information. 3. Wait for the avl_csr_readdata_valid signal to go high. 4. Retrieve read data from avl_csr_readdata.

1.2.6.1.3. Operations Example Waveforms

Note:

Intel recommends that you verify the Remote Update Intel FPGA IP core for Intel Arria 10 and Intel Cyclone 10 GX devices in hardware because the simulation model is not supported for Remote Update Intel FPGA IP core for Intel Arria 10 and Intel Cyclone 10 GX devices.

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Figure 5. Waveform for Write Operation

Figure 6. Waveform for Read Operation

Figure 7.

Waveform for RU_CTL_NUPDT Operation
The RU_CTL_NUPDT will hold the value until a new value is inserted.

Figure 8.

Waveform for Reset Timer and Reconfiguration Operation
The RU_RECONFIG will hold the value until the reconfiguration process is done.

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1.2.6.2. Register Map

Table 6.

Remote Update Intel FPGA IP Core Avalon-MM Register Map for Intel Arria 10 and Intel Cyclone 10 GX Devices
� The IP core can read or write each field separately as each command has different parameter value.
� The default value for the registers is 0.

Address Offset
0x0

RU_WATCHDOG_TIMEOUT

0x1

Width 5
12

R/W

Description

Read Read/Write

Read configuration trigger conditions. � Bit 4--wdtimer_source: User
watchdog timer timeout � Bit 3--nconfig_source: External
configuration reset (nCONFIG) assertion. � Bit 2--runconfig_source:
Configuration reset triggered from logic array � Bit 1--nstatus_source: nSTATUS asserted by an external device as the result of an error � Bit 0--crcerror_source: CRC error during application configuration.
Read or write watchdog timeout value.

RU_WATCHDOG_ENABLE

0x2

RU_PAGE_SELECT

0x3

RU_CONFIGURATION_MODE

0x4

RU_RESET_TIMER

0x5

RU_RECONFIG

0x6

RU_CTL_NUPDT

0x7

1 24 or 32
1 1 1
1

Read/Write Read/Write Read/Write
Write Write
Write

Enable or disable watchdog timeout. � 0: Disable � 1: Enable
Read or write start address of the configuration image.
Write configuration mode set to 1 in application page and 0 in factory page.
Write a value of 1 to this register to trigger reset timer of the remote update. The IP will automatically trigger a reset pulse to the reset timer pin of the remote update.
Write a value of 1 to this register to trigger reconfiguration from a new image. The IP will set 1 to the reconfig pin of the remote update and hold this value until the process done.
Allow capturing of data from either Control/ Update register by controlling ctl_nupdt. � 0: Capture value from Update Register � 1: Capture data from Control Register

1.2.7. Enabling Remote System Upgrade Circuitry
To enable the remote system upgrade feature, select Active Serial or Configuration Device from the Configuration scheme list in the Configuration page of the Device and Pin Options dialog box in the Intel Quartus Prime software.
Intel-provided Remote Update Intel FPGA IP core provides a memory-like interface to the remote system upgrade circuitry and handles the shift register read and write protocol in the Intel Arria 10 and Intel Cyclone 10 GX device logic.

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When using the Remote Update Intel FPGA IP core and the Direct to Application (DTA) mode in the Intel Arria 10 devices, you must enable the Auto-restart configuration after error option from the General page of the Device and Pin Option dialog box to enable the factory fall back mechanism.
1.2.8. Generating Initial RSU Image
To convert .sof files to one .jic/.rpd files and to generate the initial RSU image, follow these steps: 1. On the File menu, click Convert Programming File and select the details as
shown below: � Programming File type: JTAG Indirect Configuration File (.jic). � Configuration Device: <Select the Configuration Device used in your board>. � Mode: Select either Active Serial/Active Serial x4. � File_name: Set the file name and your desired location. � Optional:
-- Check the Create Memory File to generate the .map file -- Check the Create config data RPD to generate the .rpd file � Flash loader: Click Add Device, select Arria 10 and choose the Device name used in your design � SOF DATA PAGE_0: click Add File and assign Factory image (.sof) to Page_0. � Click Add Sof Page to add SOF Data Page_1. You can add more SOF Data Page according to the number of application images in this initial RSU image. � SOF DATA PAGE_1: click Add File and select the application image file (.sof). � Setting Boot Page Selection for enabling the device to boot either from factory image or application image -- To select the boot page, click the Option/Boot Info button in Convert
Programming File. -- In the Options window, select the page available from the Boot from
page drop down menu. -- By default, the page number will be set at Page_0. -- To allow the FPGA to boot directly from application image (DTA), change
the page number to Page_1 and so on. � Click Generate. � Click OK when the dialog box of .jic file successfully generated appears.

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1.3. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices

1.3.1. Remote System Configuration Mode

Remote Configuration Mode

Figure 9. Remote Configuration Mode

Configuration Error

Power Up
Configuration Error

Factory Configuration
(page 0)

Set Control Register and Reconfigure

Application 1 Configuration

Reload a Different Application Reload a Different Application

Set Control Register and Reconfigure

Application n Configuration

Configuration Error

When using with serial configuration (EPCS) or quad-serial configuration (EPCQ) devices, the remote update mode allows a configuration space to start at any flash sector boundary, allowing a maximum of 128 pages in the EPCS64 device and 32 pages in the EPCS16 device, in which the minimum size of each page is 512 Kb. Additionally, the remote update mode features a user watchdog timer that can detect functional errors in an application configuration.

1.3.2. Remote System Configuration Components

Table 7.

Remote System Configuration Components in Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices

Components Page mode feature

Details The dedicated 24-bit start address register PGM[23..0] holds the start address.

Factory configuration
Application configuration Watchdog timer

Factory configuration is the default configuration setup. In remote configuration mode, the factory configuration loads into the device upon powerup. If a system encounters an error while loading application configuration data or if the device reconfigures due to nCONFIG assertion, the device loads the factory configuration. The remote system configuration register determines the reason for factory configuration. Based on this information, the factory configuration determines which application configuration to load.
The application configuration is the configuration data from a remote source and the data is stored in different locations or pages of the memory storage device, excluding the factory default page.
A watchdog timer is a circuit that determines the functionality of another mechanism. The watchdog timer functions like a time delay relay that remains in the reset state while an application runs properly.
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Components
Remote update sub-block Remote configuration registers

Details
Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V devices are equipped with a built-in watchdog timer for remote system configuration to prevent a faulty application configuration from indefinitely stalling the device. The timer is a 29-bit counter, but you use only the upper 12 bits (left-most or mostsignificant bits) to set the value for the watchdog timer. The timer begins counting after the device goes into user mode. If the application configuration does not reset the user watchdog timer before time expires, the dedicated circuitry reconfigures the device with the factory configuration and resets the user watchdog timer. To ensure the application configuration is valid, you must continuously reset the watchdog reset_timer within a specific duration during user mode operation.
The remote update sub-block manages the remote configuration feature. A remote configuration state machine controls this sub-block. This sub-block generates the control signals required to control the various configuration registers.
The remote configuration registers keep track of page addresses and the cause of configuration errors. You can control both the update and shift registers. The status and control registers are controlled by internal logic, but are read via the shift register. The control register is 38-bit wide. For details about configuration registers, refer to the Configuration, Design Security, and Remote System Upgrades chapter in the respective device handbook.

Related Information
� Arria V Device Handbook Volume 1: Device Interfaces and Integration Provides more information about configuration registers of the Arria V devices.
� Cyclone V Device Handbook Volume 1: Device Interfaces and Integration Provides more information about configuration registers of the Cyclone V devices.
� Stratix V Device Handbook Volume 1: Device Interfaces and Integration Provides more information about configuration registers of the Stratix V devices.

1.3.3. Parameter Settings

Table 8.

Remote Update Intel FPGA IP Core Parameters for Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices

GUI Name

Values

Description

Which operation mode will you be using?

REMOTE

Specifies the configuration mode.

Which configuration �

device will you be

�

using?

EPCS device EPCQ device

Choose the configuration device you are using. continued...

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GUI Name
Add support for writing configuration parameters
Add support for Avalon Interface(1)
Enable reconfig POF checking

Values --
-- --

Description
Enable this if you need to write configuration parameters.
Enable this if you are using Avalon interface.
Allows you to enable .pof checking, which allows the remote update block to verify the existence of an application configuration image before the image is loaded. When you turn on this parameter, the Remote Update Intel FPGA IP core checks the .pof and sends the reconfig signal. This option is disabled by default.

The POF checking feature detects and verifies the existence of an application configuration image before the image is loaded. Loading an invalid application configuration image may lead to unexpected behavior of the FPGA including system failure. Examples of invalid application configuration images are:
� A partially programmed application image
� A blank application image
� An application image assigned with a wrong start address
When enabled, POF checking feature only checks the header section of the application image by calculating the section's CRC.
� If the header section is invalid, the Remote Update Intel FPGA IP does not trigger reconfiguration and asserts pof_error signal.
� If the header section is valid, but the corruption appears in a different part of the image, the IP triggers application image reconfiguration. The reconfiguration fails due to a CRC mismatch and the nSTATUS signal asserts. The IP then loads the factory image.

1.3.4. Ports

Table 9.

Remote Update Intel FPGA IP Core Ports for Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices

Name

Port

Required?

Description

read_param

Input

Read signal for the parameter specified in param[] input

port and fed to data_out[] output port.

Signal indicating the parameter specified on the param[] port should be read. The number of bits set on data_out[] depends on the parameter type. The signal is sampled at the rising clock edge. Assert the signal for only one clock cycle to prevent the parameter from being read again in a subsequent clock cycle.

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(1) Parameter not available in Stratix II devices.
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Name write_param
param[] data_in[]
reconfig reset_timer

Port Input
Input Input
Input Input

Required? No
No No
Yes No

Description
The busy signal is activated as soon as read_param is read as active. While the parameter is being read, the busy signal remains asserted, and data_out[] has invalid data. When the busy signal is deactivated, data_out[] is valid, another parameter can be read.
Write signal for parameter specified in param[] and with value specified in data_in[].
Signal indicating parameter specified with param[] should be written into remote update block with the value specified in data_in[]. The number of bits read from data_in[] depends on the parameter type.
The signal is sampled at the rising clock edge. The signal should be asserted for only one clock cycle to prevent the parameter from being rewritten on a subsequent clock cycle. The busy signal is activated as soon as write_param is read as being active. While the parameter is being written, the busy signal remains asserted, and input to data_in[] is ignored. When the busy signal is deactivated, another parameter can be written. This signal is only valid in factory configuration mode because parameters cannot be written in application configuration mode.
Bus that specifies which parameter need to be read or updated. A 3-bit bus that selects the parameter to be read or updated. If left unconnected, the default value for this port is 000. For more information, refer to Parameters on page 21.
Data input for writing parameter data into the remote update block. Input bus for parameter data. For some parameters, not all bits are used. In this case, the lower-order bits are used (for example, status values use bits [4:0]).
If left unconnected, this bus defaults to 0. The port is ignored if the current configuration is the Application configuration. A 24-bit bus width in the Intel Quartus Prime software version 13.0 or earlier. For the Intel Quartus Prime software version 13.1 and later, the bus widths are as follow: � 24-bit bus width--using 3-byte addressing
configuration device, for example EPCS128. � 32-bit bus width--using 4-byte addressing
configuration device, for example EPCQ256.
Signal indicating that reconfiguration of the part should begin using the current parameter settings. A value of 1 indicates reconfiguration should begin. This signal is ignored while the busy signal is asserted to ensure all parameters are completely written before reconfiguration begins.
Reset signal for watchdog timer. Signal indicating the internal watchdog timer should be reset. Unlike other inputs, this signal is not affected by the busy signal and can reset the timer even when the busy signal is asserted. A falling edge of this signal triggers a reset of the user watchdog timer. For the timing specification of this parameter, refer to the specific device handbook.
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Name clock reset busy data_out[]
asmi_busy asmi_data_valid asmi_dataout

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Port Input Input Output Output
Input Input Input

Required? Yes Yes No No
No No No

Description
Clock input to the remote update block. Clock input to control the machine and to drive the remote update block during the update of parameters. This port must be connected to a valid clock.
This is an active high signal. Asserting this signal high will reset the IP core. Asynchronous reset input to the IP core to initialize the machine to a valid state. The machine must be reset before first use, otherwise the state is not guaranteed to be valid.
Busy signal that indicates when remote update block is reading or writing data. While this signal is asserted, the machine ignores most of its inputs and cannot be altered until the machine deasserts this signal. Therefore, changes are made only when the machine is not busy. This signal goes high when read_param or write_param is asserted, and remains high until the read or write operation completes.
Data output when reading parameters. This bus holds read parameter data from the remote update block. The param[] value specifies the parameter to read. When the read_param signal is asserted, the parameter value is loaded and driven on this bus. Data is valid when the busy signal is deasserted. If left unconnected, the default value for the port is 0. The width of this bus is device-dependent: For the Intel Quartus Prime software version 13.0 or earlier, the bus widths is 24 bits. For the Intel Quartus Prime software version 13.1 and later are as follow: � 24-bit bus width--using 3-byte addressing
configuration device, for example EPCS128. � 32-bit bus width--using 4-byte addressing
configuration device, for example EPCQ256.
Input from the altasmi_parallel component.
Available when the check_app_pof parameter is set to true. A logic high on this pin indicates that the ASMI Parallel Intel FPGA IP core is busy processing the operation. The Remote Update Intel FPGA IP core waits for this pin to go low before initiating another operation. Wire this pin to the asmi_busy output port of the ASMI Parallel Intel FPGA IP core.
Input from the altasmi_parallel component.
Available when the check_app_pof parameter is set to true. A logic high on this pin indicates valid data in the asmi_dataout[7..0] output port of the ASMI Parallel Intel FPGA IP core. Wire this pin to the asmi_data_valid output port of the ASMI Parallel Intel FPGA IP core.
Input from the altasmi_parallel component.
Available when the check_app_pof parameter is set to true.
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Name pof_error
asmi_addr asmi_read asmi_rden

Port Output
Output Output Output

Required? No
No No No

Description
The Remote Update Intel FPGA IP core presents the address information on this pin before initiating the read operation on the ASMI Parallel Intel FPGA IP core.
Detects an invalid application configuration image. Available when the check_app_pof parameter is set to TRUE. A logic high on this pin indicates that the Remote Update Intel FPGA IP core detects an invalid application configuration image. If asserted high, you must take corrective action by reloading a new application configuration image or specifying a different address location in the EPCS or EPCQ that contains a valid application configuration image. Wire this pin based on your system requirement.
Address signal to the altasmi_parallel component.
Available when the check_app_pof parameter is set to TRUE. The Remote Update Intel FPGA IP core presents the address information on this pin before initiating the read operation on the ASMI Parallel Intel FPGA IP core.
Read signal to the altasmi_parallel component.
Available when the check_app_pof parameter is set to TRUE. A logic high on this pin initiates the read operation on the ASMI Parallel Intel FPGA IP core. Wire this pin to the asmi_read input port of the ASMI Parallel Intel FPGA IP core.
Read enable signal to the altasmi_parallel component. Available when the check_app_pof parameter is set to TRUE. This pin enables the read operation on the ASMI Parallel Intel FPGA IP core. Wire this pin to the asmi_rden input port of the ASMI Parallel Intel FPGA IP core.

1.3.5. Parameters

Table 10.

Parameter Type and Corresponding Parameter Bit Width Mapping for Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices

Bit

Parameter

000

Reconfiguration trigger conditions (Read Only)

001 010 Watchdog Timeout Value

Width 5 12

Comments
� Bit 4--wdtimer_source: User watchdog timer timeout. � Bit 3--nconfig_source: External configuration reset
(nCONFIG) assertion. � Bit 2--runconfig_source: Configuration reset triggered
from logic array. � Bit 1--nstatus_source: nSTATUS asserted by an external
device as the result of an error. � Bit 0--crcerror_source: CRC error during application
configuration. The POR value for all bits are 0.
Illegal Value
Width of 12 when writing. The 12 bits for writing are the upper 12 bits (left-most or mostsignificant bits) of the 29-bit Watchdog Timeout Value.
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Bit

Parameter

011 Watchdog Enable 100 Page Select

101 Configuration Mode (AnF)
110 111

Width 29 1
24 or 32
1

Comments
When writing parameter data, data_in[11..0] corresponds to the upper 12 bits of the 29-bit Watchdog Timeout Value. For example, to set the Watchdog Timeout Value to 1, write the 12 bits of data_in[11..0] as 12'b000000000001.
Width of 29 when reading.
--
For the Intel Quartus Prime software version 13.1 and later: � Width of 24 or 32 when reading and writing the start address. � For active serial devices using 24-bit addressing, such as
EPCS128 or EPCQ128, PGM[23..2] corresponds to the upper 22 bits of the 24-bits start address. PGM[1..0] is read as 2'b0. � For active serial devices using 32-bit addressing, such as EPCQ256, PGM[31..2] corresponds to the upper 30 bits of the 32-bits start address. PGM[1..0] is read as 2'b0. For the Intel Quartus Prime software version 13.0 and earlier: � Width of 24 when reading and writing the start address. � For Arria II and Stratix IV devices, PGM[23..0] form the 24bit start address. � For Arria V, Cyclone V, and Stratix V devices, if you use active serial devices using 24-bit addressing, such as EPCS128 or EPCQ128, PGM[23..0] corresponds to the 24 bits of the start address. If you use active serial devices using 32-bit addressing, such as EPCQ256, PGM[23..0] corresponds to the 24 MSB of the start address, thus the 32 bits start address is PGM[23..0],8'b0.
This parameter is set to 1 in application page and is set to 0 in factory page. In remote update mode, this parameter can be read and written. Before loading the application page in remote update mode, Intel recommends that you set this parameter to 1. The content of the control register cannot be read properly if you fail to do so.
Illegal Value
Illegal Value

1.3.6. Avalon-MM Interface
The Avalon-MM interface in Remote Update Intel FPGA IP core is not supported in Stratix II devices.

1.3.6.1. Control Status Register Signals

Table 11.

Remote Update Intel FPGA IP Core Avalon-MM Control Status Register Signals for Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices

Name clk

Width 1

Direction Input

Clock input.

Description

reset

Input

Reset input.

avl_csr_address

Input

Address bus.

avl_csr_read

Input

Perform a read transaction.

avl_csr_write

Input

Perform a write transaction.

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Name

Width

avl_csr_readdata

avl_csr_readdata_valid 1

avl_csr_writedata

avl_csr_waitrequest

Direction Output Output Input Output

Description Read data from IP. Indicate when read data is valid. Write data to IP. Waitrequest signal high indicates the core is busy.

1.3.6.1.1. Control Status Register Write Operation
To execute the write operation for control the status register, perform the following steps: 1. Asserts the avl_csr_write high. 2. Write a correct address of the register in the avl_csr_address bus. Refer to the
Register Map for register information. 3. Write data into the avl_csr_writedata bus.
Related Information Register Map on page 23
1.3.6.1.2. Control Status Register Read Operation
To execute the read operation for the control status register, perform the following steps: 1. Asserts avl_csr_read high. 2. Write a correct address of the register in the avl_csr_address bus. Refer to the
Register Map for register information. 3. Wait for the avl_csr_readdata_valid signal to go high. 4. Retrieve read data from avl_csr_readdata.

1.3.6.2. Register Map

Table 12.

Remote Update Intel FPGA IP Core Avalon-MM Register Map for Arria V, Cyclone V, Stratix IV, and Stratix V Devices
� The IP core can read or write each field separately as each command has different parameter value.
� The default value for the registers is 0.

Address Offset
0x0

Width 5

R/W Read

Description Read configuration trigger conditions.
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Address Offset

RU_WATCHDOG_TIMEOUT

0x1

RU_WATCHDOG_ENABLE

0x2

RU_PAGE_SELECT

0x3

RU_CONFIGURATION_MODE

0x4

RU_RESET_TIMER

0x5

RU_RECONFIG

0x6

Width
12 1 24 or 32 1 1 1

R/W

Description

Read/Write Read/Write
Read/Write Read/Write
Write
Write

� Bit 4--wdtimer_source: Users watchdog timer timeout
� Bit 3--nconfig_source: External configuration reset (nCONFIG) assertion.
� Bit 2--runconfig_source: Configuration reset triggered from logic array
� Bit 1--nstatus_source: nSTATUS asserted by an external device as the result of an error
� Bit 0--crcerror_source: CRC error during application configuration.
Read or write watchdog timeout value.
Enable or disable watchdog timeout. � 0: Disable � 1: Enable
Read or write start address of configuration image.
Write configuration mode set to 1 in application page and 0 in factory page.
Write a value of 1 to this register to trigger reset timer of the remote update. The IP will automatically trigger a reset pulse to reset timer pin of the remote update.
Write a value of 1 to this register to trigger reconfiguration from a new image. The IP will set 1 to reconfig pin of the remote update and hold this value until the process done.

1.3.7. Enabling Remote System Upgrade Circuitry
To enable the remote system upgrade feature, follow these steps:
1. Select Active Serial x1/x4 or Configuration Device from the Configuration scheme list in the Configuration page of the Device and Pin Options dialog box in the Intel Quartus Prime software.
2. Select Remote from the Configuration mode list in the Configuration page of the Device and Pin Options dialog box in the Intel Quartus Prime software.
Enabling this feature automatically turns on the Auto-restart configuration after error option.
Remote Update Intel FPGA IP core provides a memory-like interface to the remote system upgrade circuitry and handles the shift register read and write protocol in the device logic.

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1.4. Cyclone IV and Intel Cyclone 10 LP Devices

1.4.1. Remote System Configuration Mode

Remote Configuration Mode

Figure 10. Remote Configuration Mode

Configuration Error

Power Up
Configuration Error

Factory Configuration
(page 0)

Set Control Register and Reconfigure

Application 1 Configuration

Reload a Different Application Reload a Different Application

Set Control Register and Reconfigure

Application n Configuration

Configuration Error

Only Cyclone IV E devices support both the active parallel (AP) and active serial (AS) configuration scheme for remote system upgrade. Intel Cyclone 10 LP and other Cyclone IV devices support only the AS configuration scheme for remote system upgrade.
When using with EPCS or EPCQ devices, the remote update mode allows a configuration space to start at any flash sector boundary, allowing a maximum of 128 pages in the EPCS64 device and 32 pages in the EPCS16 device, in which the minimum size of each page is 512 Kb. Additionally, the remote update mode features a user watchdog timer that can detect functional errors in an application configuration.

1.4.2. Remote System Configuration Components

Table 13.

Remote System Configuration Components in Cyclone IV and Intel Cyclone 10 LP Devices

Components

Details

Page mode feature

Cyclone IV and Intel Cyclone 10 LP devices use a 24-bit boot start address for AS configuration in which you set the most significant 22 bits. Similar setting applies for AP configuration in Cyclone IV E devices. In addition, Cyclone IV and Intel Cyclone 10 LP devices do not support pgmout ports.

Factory configuration

Factory configuration is the default configuration setup.
In remote configuration mode, the factory configuration loads into Cyclone IV and Intel Cyclone 10 LP devices upon power-up.
If a system encounters an error while loading application configuration data or if the device reconfigures due to nCONFIG assertion, the device loads the factory configuration. The remote system configuration register determines the reason for factory configuration. Based on this information, the factory configuration determines which application configuration to load.
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Components
Application configuration Watchdog timer
Remote update sub-block Remote configuration registers

Details
Upon power-up in remote update in the AP configuration scheme, Cyclone IV E devices load the default factory configuration located at the following address:
boot_address[23:0] = 24'h010000 = 24'b1 0000 0000 0000 0000. You can change the default factory configuration address to any address using the APFC_BOOT_ADDR JTAG instruction. The factory image is stored in non-volatile memory and is never updated or modified using remote access. This corresponds to the default start address location 0x010000 (or the updated address if the default address is changed) in the supported parallel flash memory. Note that 0x010000 is the 16-bit word address for the AP flash memory. However, the Intel Quartus Prime software implements 8-bit byte addressing. Therefore, the correct Intel Quartus Prime software setting for this address is 0x020000.
The application configuration is the configuration data from a remote source and the data is stored in different locations or pages of the memory storage device, excluding the factory default page.
A watchdog timer is a circuit that determines the functionality of another mechanism. The watchdog timer functions like a time delay relay that remains in the reset state while an application runs properly. The devices are equipped with a built-in watchdog timer for remote system configuration to prevent a faulty application configuration from indefinitely stalling the device. The timer is a 29-bit counter, but you use only the upper 12 bits (left-most or mostsignificant bits) to set the value for the watchdog timer. The timer begins counting after the device goes into user mode. If the application configuration does not reset the user watchdog timer before time expires, the dedicated circuitry reconfigures the device with the factory configuration and resets the user watchdog timer. To ensure the application configuration is valid, you must continuously reset the watchdog reset_timer within a specific duration during user mode operation.
The remote update sub-block manages the remote configuration feature. A remote configuration state machine controls this sub-block. This sub-block generates the control signals required to control the various configuration registers.
The remote configuration registers keep track of page addresses and the cause of configuration errors. You can control both the update and shift registers. The status and control registers are controlled by internal logic, but are read via the shift register. The remote system upgrade status register has additional capabilities. Three sets of registers store the status for the current application configuration and the two previous application configurations. For details about configuration registers, refer to the Configuration, Design Security, and Remote System Upgrades chapter in the respective device handbook.

Related Information
� Cyclone IV Device Handbook, Volume 1 Provides more information about configuration registers of the Cyclone IV devices.
� Intel Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook Provides more information about configuration registers of the Intel Cyclone I0 LP devices.

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1.4.3. Parameter Settings

Table 14.

Remote Update Intel FPGA IP Core Parameters for Cyclone IV and Intel Cyclone 10 LP Devices

GUI Name
Which operation mode will you be using?

Legal Value in GUI REMOTE

Description
Specifies the configuration mode of the Remote Update Intel FPGA IP core.

Which configuration �

device will you be

�

using?

EPCS device EPCQ device

Choose the configuration device that you are using.

Add support for

Enable this if you need to write configuration

writing configuration

parameters.

parameters

Enable reconfig POF checking

Allows you to enable .pof checking, which allows the

remote update block to verify the existence of an

application configuration image before the image is

loaded. When you turn on this parameter, the Remote

Update Intel FPGA IP core checks the .pof and sends the

reconfig signal. This option is disabled by default.

1.4.4. Ports

Table 15.

Remote Update Intel FPGA IP Core Ports for Cyclone IV and Intel Cyclone 10 LP Devices

Name read_param
write_param

Port Input
Input

Required? No
No

Description
Read signal for the parameter specified in param[] input port and fed to data_out[] output port.
Signal indicating the parameter specified on the param[] port should be read. The number of bits set on data_out[] depends on the parameter type. The signal is sampled at the rising clock edge. Assert the signal for only one clock cycle to prevent the parameter from being read again in a subsequent clock cycle.
The busy signal is activated as soon as read_param is read as active. While the parameter is being read, the busy signal remains asserted, and data_out[] has invalid data. When the busy signal is deactivated, data_out[] becomes valid and another parameter can be read.
Write signal for parameter specified in param[] and with value specified in data_in[].
Signal indicating parameter specified with param[] should be written into remote update block with the value specified in data_in[]. The number of bits read from data_in[] depends on the parameter type.
The signal is sampled at the rising clock edge. The signal should be asserted for only one clock cycle to prevent the parameter from being rewritten on a subsequent clock cycle. The busy signal is activated as soon as write_param is read as being active. While the parameter is being written, the busy signal remains asserted, and input to data_in[] is ignored. When the busy signal is deactivated, another parameter can be written. This signal is only valid in factory configuration mode because parameters cannot be written in application configuration mode.
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Name param[] data_in[]
reconfig reset_timer read_source
clock

Port Input Input
Input Input Input
Input

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Required? No No
Yes No Yes
Yes

Description
Bus that specifies which parameter need to be read or updated. A 3-bit bus that selects the parameter to be read or updated. If left unconnected, the default value for this port is 000. For more information, refer to Parameters on page 30.
Data input for writing parameter data into the remote update block. Input bus for parameter data. For some parameters, not all bits are used. In this case, the lower-order bits are used (for example, status values use bits [4:0]).
If left unconnected, this bus defaults to 0. The port is ignored if the current configuration is the application configuration. For the Intel Quartus Prime software version 13.0 or earlier, the bus width is 22-bit. For the Intel Quartus Prime software version 13.1 and later, the bus widths are as follow: � 24-bit bus width--using 3-byte addressing
configuration device, for example EPCS128. � 32-bit bus width--using 4-byte addressing
configuration device, for example EPCQ256.
Signal indicating that reconfiguration of the part should begin using the current parameter settings. A value of 1 indicates reconfiguration should begin. This signal is ignored while busy is asserted to ensure all parameters are completely written before reconfiguration begins.
Reset signal for the watchdog timer. Signal indicating the internal watchdog timer should be reset. Unlike other inputs, this signal is not affected by the busy signal and can reset the timer even when the busy signal is asserted. A falling edge of this signal triggers a reset of the user watchdog timer. For the timing specification of this parameter, refer to the specific device handbook.
Specifies whether a parameter value is read from the current or a previous state. This 2-bit port specifies the state from which a parameter value is read. This signal is valid only when the read_param signal is valid.
Mapping read_source[1..0] to Selected Source is defined as follow: � 00 - Current State Content in Status Register � 01 - Previous State Register 1 Content in Status
Register � 10 - Previous State Register 2 Content in Status
Register � 11 - Value in Input Register For details, refer to the Configuration, Design Security, and Remote System Upgrades chapter in the respective device handbook.
Clock input to the remote update block. Clock input to control the machine and to drive the remote update block during the update of parameters. This port must be connected to a valid clock.
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Name reset busy data_out[]
asmi_busy asmi_data_valid asmi_dataout pof_error

Port Input Output Output
Input Input Input Output

Required? Yes No No
No No No No

Description
This is an active high signal. Asserting this signal high will reset the IP core. Asynchronous reset input to the IP core to initialize the machine to a valid state. The machine must be reset before first use, otherwise the state is not guaranteed to be valid.
Busy signal that indicates when remote update block is reading or writing data. While this signal is asserted, the machine ignores most of its inputs and cannot be altered until the machine deasserts this signal. Therefore, changes are made only when the machine is not busy. This signal goes high when read_param or write_param is asserted, and remains high until the read or write operation completes.
Data output when reading parameters. This bus holds read parameter data from the remote update block. The param[] value specifies the parameter to read. When the read_param signal is asserted, the parameter value is loaded and driven on this bus. Data is valid when the busy signal is deasserted. If left unconnected, the default value for the port is 000. The width of this bus is device-dependent: For the Intel Quartus Prime software version 13.0 or earlier, the bus width is 29-bit. For the Intel Quartus Prime software version 13.1 and later, the bus widths are as follow: � 29-bit bus width--using 3-byte addressing
configuration device, for example EPCS128. � 32-bit bus width--using 4-byte addressing
configuration device, for example EPCQ256.
Input from the altasmi_parallel component.
Available when the check_app_pof parameter is set to true. A logic high on this pin indicates that the ASMI Parallel Intel FPGA IP core is busy processing the operation. The Remote Update Intel FPGA IP core waits for this pin to go low before initiating another operation. Wire this pin to the asmi_busy output port of the ASMI Parallel Intel FPGA IP core.
Input from the altasmi_parallel component.
Available when the check_app_pof parameter is set to true. A logic high on this pin indicates valid data in the asmi_dataout[7..0] output port of the ASMI Parallel Intel FPGA IP core. Wire this pin to the asmi_data_valid output port of the ASMI Parallel Intel FPGA IP core.
Input from the altasmi_parallel component.
Available when the check_app_pof parameter is set to true. The Remote Update Intel FPGA IP core presents the address information on this pin before initiating the read operation on the ASMI Parallel Intel FPGA IP core.
Detects an invalid application configuration image.
continued...

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Name
asmi_addr asmi_read asmi_rden

Port
Output Output Output

Required?
No No No

Description
Available when the check_app_pof parameter is set to TRUE. A logic high on this pin indicates that the Remote Update Intel FPGA IP core detects an invalid application configuration image. If asserted high, you must take corrective action by reloading a new application configuration image or specifying a different address location in the EPCS or EPCQ that contains a valid application configuration image. Wire this pin based on your system requirement.
Address signal to the altasmi_parallel component.
Available when the check_app_pof parameter is set to TRUE. The Remote Update Intel FPGA IP core presents the address information on this pin before initiating the read operation on the ASMI Parallel Intel FPGA IP core. Wire this pin to the asmi_addr input port of the ASMI Parallel Intel FPGA IP core.
Read signal to the altasmi_parallel component.
Available when the check_app_pof parameter is set to TRUE. A logic high on this pin initiates the read operation on the ASMI Parallel Intel FPGA IP core. Wire this pin to the asmi_read input port of the ASMI Parallel Intel FPGA IP core.
Read enable signal to the altasmi_parallel component. Available when the check_app_pof parameter is set to TRUE. This pin enables the read operation on the ASMI Parallel Intel FPGA IP core. Wire this pin to the asmi_rden input port of the ASMI Parallel Intel FPGA IP core.

1.4.5. Parameters

Table 16.

Parameter Type and Corresponding Parameter Bit Width Mapping for Cyclone IV and Intel Cyclone 10 LP Devices

Bit

Parameter

000 Master State Machine Current State Mode (Read Only)

001 Force early CONF_DONE (cd_early) check
010 Watchdog Timeout Value

Width 2
1 12

Comments
00--Factory mode. 01--Application mode. 11--Application mode with the master state machine user watchdog timer enabled.
--
Width of 12 when writing. The 12 bits for writing are the upper 12 bits (left-most or mostsignificant bits) of the 29-bit Watchdog Timeout Value. When writing parameter data, data_in[11..0] corresponds to the upper 12 bits of the 29-bit Watchdog Timeout Value. For example, to set the Watchdog Timeout Value to 1, write the 12 bits of data_in[11..0] as 12'b000000000001.

011 Watchdog Enable

Width of 29 when reading.

continued...

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Bit

Parameter

100 Boot Address

101
110 Force the internal oscillator as startup state machine clock (osc_int) option bit
111 Reconfiguration trigger conditions (Read Only)

Width --
1

Comments
For the Intel Quartus Prime software version 13.1 and later: � Width of 29 or 32 when reading the boot address. � Width of 24 or 32 when writing the boot address. � For active serial devices using the 24-bit addressing, such as
EPCS128 or EPCQ128, boot_address[23..2] corresponds to the upper 22 bits of the 24-bits boot address. boot_address[1..0] is read as 2'b0. � For active serial devices using the 32-bit addressing, such as EPCQ256, boot_address[31..2] corresponds to the upper 30 bits of the 32-bits boot address. boot_address[1..0] is read as 2'b0. For the Intel Quartus Prime software version 13.0 or earlier: � Width of 24 when reading the boot address. � Width of 22 when writing the boot address. � Writes the boot address to the upper 22 bits of the 24-bits boot address.
Illegal Value
--

Bit 4 (nconfig_source)--external configuration reset

(nconfig) assertion.

Bit 3 (crcerror_source)--CRC error during application configuration.

Bit 2 (nstatus_source)--nstatus asserted by an external device as the result of an error.

Bit 1 (wdtimer_source)--User watchdog timer timeout.

Bit 0 (runconfig_source)--Configuration reset triggered from logic array.

1.4.6. Remote Update Operation

The operation defined in the Remote Update Operation column should only be performed in the corresponding master state machine (MSM) mode.

Table 17. Cyclone IV and Intel Cyclone 10 LP Devices Remote Update Operation

Note:

read_source specifies whether a parameter value is read from the current or a previous state. For more information, refer to Table 18 on page 33.

read_ write_ read_source param param param

Remote Update Operation

data_out width (bits)

MSM Mode

[00]

[000] Master State Machine Current State Mode (Read Only)

Factory or

Application

� 00--Factory mode

� 01--Application mode

� 11--Application mode with master state machine user watchdog timer enabled

[00]

[100] Read factory boot address

Factory

[01]

[100]

Read Past Status 1 boot address.
For more information, refer to Figure 11 on page 33.

Factory

continued...

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read_ write_ read_source param param param

Remote Update Operation

data_out MSM Mode width (bits)

[01]

[111]

Read Past Status 1 reconfiguration trigger condition source.
For more information, refer to Figure 11 on page 33.

Factory

[10]

[100]

Read Past Status 2 boot address.
For more information, refer to Figure 11 on page 33.

Factory

[10]

[111]

Read Past Status 2 reconfiguration trigger condition source
For more information, refer to Figure 11 on page 33.

Factory

[01]

[010] Read current application mode watchdog value

Application

[01]

[011] Read current application mode watchdog enable

Application

[10]

[100] Read current application mode boot address

Application

[00]

[001] Write the early confdone check bit. All parameters can be written in factory mode only.

Factory

[00]

[010] Write the watchdog time-out value. All parameters can be written in factory mode only.

Factory

[00]

[011] Write the watchdog enable bit. All parameters can be written in factory mode only.

Factory

[00]

[100] Write application boot address. All parameters can be written in factory mode only.

Factory

[00]

[110]

Write to force the internal oscillator as startup state machine clock. All parameters can be written in factory mode only.

Factory

[11]

[001] Read the early confdone check bits

Factory

[11]

[010] Read watchdog time-out value

Factory

[11]

[011] Read watchdog enable bit

Factory

[11]

[100] Read boot address

Factory

[11]

[110] Read to check whether the internal oscillator is set as startup state machine clock

Factory

read_source
The following table lists the details for read_source. read_source specifies whether a parameter value is read from the current or a previous state. When you trigger the read operation, all contents in the status register or input register latched to the data_out node in the Remote Update Intel FPGA IP core.

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Table 18. read_source

read_source

Description

Current state contents in status register

Previous state register 1 contents in status register

Previous state register 2 contents in status register

Current contents is in input register

State Register

The previous state register 1 reflects the current application configuration and the previous state register 2 reflects the previous application configuration.

Figure 11.

State Register

Back to factory (State register 1 reflects to current application which is application 1)

Configured the Application 1 from Factory
Factory Configuration

Application 1 Configuration

Switched to Application 2

Application 2 Configuration

Back to factory (State register 1 reflects to current application which is application 2, while the state register 2 is reflects to previous application which is application 1)
1.4.7. Avalon-MM Interface

1.4.7.1. Control Status Register Signals

Table 19.

Remote Update Intel FPGA IP Core Avalon-MM Control Status Register Signals for Cyclone IV and Intel Cyclone 10 LP Devices

Name clk

Width 1

Direction Input

Clock input.

Description

reset

Input

Reset input.

continued...

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Name

Width

avl_csr_address

avl_csr_read

avl_csr_write

avl_csr_readdata

avl_csr_readdata_valid 1

avl_csr_writedata

avl_csr_waitrequest

Direction Input Input Input Output Output Input Output

Description Address bus. Perform a read transaction. Perform a write transaction. Read data from IP. Indicate when read data is valid. Write data to IP. Waitrequest signal high indicates the core is busy.

1.4.7.1.1. Control Status Register Write Operation
To execute the write operation for the control status register, perform the following steps: 1. Asserts the avl_csr_write high. 2. Write a correct address of the register in the avl_csr_address bus. Refer to the
Register Map for register information. 3. Write data into the avl_csr_writedata bus.
Related Information Register Map on page 35
1.4.7.1.2. Control Status Register Read Operation
To execute the read operation for the control status register, perform the following steps: 1. Asserts avl_csr_read signal high. 2. Write a correct address of the register in the avl_csr_address bus. Refer to the
Register Map for register information. 3. Wait for the avl_csr_readdata_valid signal to go high. 4. Retrieve read data from avl_csr_readdata.

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1.4.7.2. Register Map

Table 20.

Remote Update Intel FPGA IP Core Avalon-MM Register Map for Cyclone IV and Intel Cyclone 10 LP Devices
� The last two bits of an address represents the read_source signals.
� You have to write the correct address offset to carry read_source value as shown in the Read Source Mapping table.
� The IP core combines the address bus of control status register interface to the read_source parameter.
� The default value for the registers is 0. � The address offsets are in word.

Address Offset
0x0

RU_FORCE_EARLY_CONF_DO

0x4

Width 2
1

R/W

Description

Read Read/Write

Read current state of the state machine 00: Factory mode 01: Application mode 11: Application mode with the master state machine user watchdog timer enabled.
Force early CONF_DONE

RU_WATCHDOG_TIMEOUT RU_WATCHDOG_ENABLE
RU_BOOT_ADDRESS
RU_FORCE_INTERNAL_OSC

0x8 0xC 0x10 0x14

29 or 12 1
24, 29 or 32 1

Read/Write Read/Write Read/Write Read/Write

Read or write watchdog timeout value. � 12 bit wide when writing � 29 bit wide when reading
Enable or disable watchdog timeout. � 0: Disable � 1: Enable
� 29 or 32 bit wide (EPCQ 32 bit addressing) when reading boot address.
� 24 or 32 bit wide when writing the boot address.
Force the internal oscillator as startup state machine clock (osc_int) option bit

RU_RECONFIG_TRIGGER_CO

0x18

Read

Read configuration trigger conditions.

NDITIONS

continued...

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Address Offset

Width

0x1C

0x1D

R/W
Write Write

Description
� Bit 4--nconfig_source: External configuration reset (nCONFIG) assertion.
� Bit 3--crcerror_source: CRC error during application configuration.
� Bit 2--nstatus_source: nSTATUS asserted by an external device as the result of an error
� Bit 1--wdtimer_source: Users watchdog timer timeout
� Bit 0--runconfig_source: Configuration reset triggered from logic array
Write a value of 1 to this register to trigger reset timer of the remote update. The IP core will automatically trigger a reset pulse to reset timer pin of the remote update.
Write to this address with value of 1 to trigger reconfiguration from a new image. The IP core will set 1 to reconfig pin of the remote update and hold this value until the process done.

1.4.7.3. Read Source Mapping

Table 21.

Read Source Mapping
� Table shows the address offset with their read source value. � These combinations are used to describe all supported operations in the Control Status Register Signals.

Name RU_MASTER_SM_CURRENT_STATE_MODE RU_FORCE_EARLY_CONF_DONE RU_WATCHDOG_TIMEOUT RU_WATCHDOG_ENABLE RU_BOOT_ADDRESS RU_FORCE_INTERNAL_OSC

Address offset
0x0 0x1 0x2 0x3
0x4 0x5 0x6 0x7
0x8 0x9 0xA 0xB
0xC 0xD 0xE 0xF
0x10 0x11 0x12 0x13
0x14 0x15

Read source value
00 01 10 11
00 01 10 11
00 01 10 11
00 01 10 11
00 01 10 11
00 01 continued...

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Name
RU_RECONFIG_TRIGGER_CONDITIONS
RU_RESET_TIMER RU_RECONFIG

Address offset
0x16 0x17
0x18 0x19 0x1A 0x1B
0x1C
0x1D

Read source value
10 11
00 01 10 11
N/A
N/A

1.4.8. Enabling Remote System Upgrade Circuitry
To enable remote update in the compiler settings of the project, perform the following steps: 1. On the Assignments menu, click Device. 2. In the Settings dialog box, Click Device and Pin Options. 3. In the Device and Pin Options dialog box , click the Configuration tab. 4. From the Configuration Mode list, select Remote. 5. Click OK. 6. In the Settings dialog box, click OK.

1.5. Flash Memory Programming Files

You can program the flash memory, EPCS, EPCQ, and EPCQ-L using the JTAG interface or Active Serial interface. Depending on the interface, you need to generate either a JTAG indirect configuration (.jic) file or a raw programming data (.rpd) file.

Table 22. Flash Memory Programming Files Based on Programming Interface

Programming Interface JTAG Interface Active Serial Interface

Flash Memory Programming File Used .jic
.rpd

Description
The .jic file instantiates the Serial Flash Loader IP core in the design to form a bridge between the flash and the JTAG Interface.
Programming data is transferred directly between the flash and download cable.

To update the application image only, you can do either one of the following: � Recompile the .jic file and choose new application image only in the convert
programming file tool. � Generate the .rpd file and program the EPCQ-L with ASMI IP or external
controller.
Related Information � Using the Intel FPGA Serial Flash Loader with the Intel Quartus Prime Software � ASMI Parallel Intel FPGA IP Core User Guide

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1.6. Design Examples
1.6.1. Intel Arria 10 Remote Update Design Example
This Intel Arria 10 design example uses the Avalon-MM interface. Intel uses the following hardware and software to create the design example: � Intel Quartus Prime Version : 15.0 � Intel Arria 10 Development Kit with 10AX115S3F45I2SGE2 FPGA Device
Follow these steps to perform the design example tasks: 1. Unzip the contents of the design example to your working directory on your PC. 2. Convert the three .sof files into one .jic by using Convert Programming File.
On the File Menu, click Convert Programming Files and select the details as shown below: � Programming File type: JTAG Indirect Configuration File (.jic). � Select Configuration Device: EPCQL1024. � Mode: Active Serial. � Set the file name you your desired location. � Flash loader: click add device and choose 10AX115S2E2. � SOFT DATA PAGE_0: click Add File and select the factory image with start
address set to <auto>. � SOFT DATA PAGE_1: click Add File and select the application image file with
start address 0x2000000. Compression is enabled for this application image file. � SOFT DATA PAGE_2: click Add File and select the application image file with start address 0x4000000. Compression is enabled for this application image file. � Click Generate. � Click OK when the dialog box of .jic file successfully generated appears. 3. Please follow the steps below to run the simple design: a. After programming the .jic file, power cycle the board, all LED is lighted up. It indicates you are currently at factory image. b. Go to system console and direct to the directory where your FI_SysConsole_try.tcl is located. Type source FI_SysConsole_try.tcl. Only one LED is lighted up which indicates successfully go to application image 1. After the watchdog timeout, all LED will light up and go back to factory image. Note: To go to application image 2 directly form the factory image, comment out
the write boot address to App1 and uncomment the write boot address App2 in the FI_SysConsole_try.tcl file. 4. Setting Boot Page Selection for design with more than one SOF page: a. To select the boot page, click the Option/Boot Info button in Convert Programming File.

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b. In the Active Serial Boot Info window, select the page available from the Boot from page drop down menu. By default, the page number will be set at page_0.
c. For application to application image, change the page number to page_1 or page_2.
Related Information Intel Arria 10 Remote System Update with Avalon-MM Interface Design Example
1.6.2. Cyclone V Remote Update Design Example
Intel uses the following hardware and software to create the design example: � Intel Quartus Prime Version : 13.0 � Cyclone V Development Kit with 5CEFA7F31C7ES FPGA Device
Follow these steps to perform the design example tasks: 1. Unzip the contents of the design example to your working directory on your PC. 2. In the Intel Quartus Prime software, click Open Project in the File menu. 3. Compile the application image:
a. Browse to the folder in which you unzipped the files and open the Application_Image.qpf.
b. Click Yes in the message box "Do you want to overwrite the database for C:/ your working directory/Application_Image.qpf created by Quartus II 64-Bit Version 13.0.a Build 232 Service Pack 1 SJ Full version?"
c. On the Processing menu, choose Start Compilation. d. Click OK when the full compilation successful dialog box appears. The
Application_Image.sof will be generated in c:\your working directory\output_files. e. Click close project in the file menu. 4. Compile the factory image: a. Browse to the folder in which you unzipped the files and open the SVRSU.qpf. b. Click Yes in the message box "Do you want to overwrite the database for C:/ your working directory/Application_Image.qpf created by Quartus II 64-Bit Version 13.0.a Build 232 Service Pack 1 SJ Full version?" c. Choose Start Compilation on the Processing menu. d. Click OK when the full compilation successful dialog box appears. The Factory_Image.sof will be generated in c:\your working directory \output_files. 5. On the File Menu, click Convert Programming Files and select the details as shown below: � Programming File type: JTAG Indirect Configuration File (.jic) � Select Configuration Device: EPCQ 128 � Mode: Active Serial x4 � File name: c:/your working directory/output_file.jic

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� Flash loader: click add device and choose 5CEFA7ES � SOFT DATA PAGE_0: click Add File and select the factory image file
(SVRSU.sof) � SOFT DATA PAGE_1: click Add File and select the Application image file
(Application_Image.sof) � Click Generate. � Click OK when the dialog box of .jic file successfully generated appears. 6. On the Tool Menu, click Programmer and follow these steps: a. Make sure the board is power up and the Intel FPGA Download Cable is
connected between computer and the board. This design example uses the Intel FPGA Download Cable and JTAG mode. b. Click Auto Detect. c. Right-click on the 5CEFA7ES and select change file. d. Browse to the output_file.jic that was generated in previous steps. e. Turn on the Program/Configure checkbox and click Start. f. Configuration successful indicates the FPGA is configured successfully.
Related Information � Cyclone V Remote System Update Design Example � AN 603: Active Serial Remote System Upgrade Reference Design
Provides more information about Arria II GX, Stratix III and Stratix IV devices reference design.

1.7. Remote Update Intel FPGA IP User Guide Archives

IP versions are the same as the Intel Quartus Prime Design Suite software versions up to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
If an IP core version is not listed, the user guide for the previous IP core version applies.

IP Core Version

User Guide

16.0

Altera Remote Update IP Core User Guide

15.1

Altera Remote Update IP Core User Guide

15.0

Altera Remote Update IP Core User Guide

14.0

Altera Remote Update IP Core User Guide

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1.8. Document Revision History for the Remote Update Intel FPGA IP User Guide

Document Version 2021.07.13 2020.02.11 2019.12.24 2019.10.22 2019.04.26
2019.01.09 2018.11.26

Intel Quartus Prime Version
18.0 18.0 18.0 18.0 18.0
18.0 18.0

Changes
� Added new note describing the fallback to the factory image in the Remote System Configuration Mode topic.
� Updated the POF checking feature description in the Parameter Settings topic.
Updated the Enabling Remote System Upgrade Circuitry topic.
� Updated the Intel Arria 10 and Intel Cyclone 10 Devices section: -- Added new topic: Generating Initial RSU Image -- Updated the description of the Remote System Configuration Mode topic.
� Added new topics: -- Remote System Upgrade State Machine -- Switching from Factory to Application Image or from Initial Application Image to Other Application Image
� Added support information for Intel Cyclone 10 GX and LP devices. � Updated label for active parallel configuration scheme to "Cyclone IV E
devices only" in Figure: High-Level Block Diagram of Remote System Upgrade. � Updated details for page mode feature and factory configuration components in Table: Remote System Configuration Components in Cyclone IV and Intel Cyclone 10 LP Devices so that AP configuration only applies to Cyclone IV E devices. � Updated Watchdog Timer details by adding "left-most or mostsignificant bits" to enhance clarity of "upper 12 bits" in Table: Remote System Configuration Components in Intel Arria 10 and Intel Cyclone 10 GX Devices, Table: Remote System Configuration Components in Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices, and Table: Remote System Configuration Components in Cyclone IV and Intel Cyclone 10 LP Devices. � Added width of 29 and comments to Watchdog Timeout Value in Table: Parameter Type and Corresponding Parameter Bit Width Mapping for Intel Arria 10 and Intel Cyclone 10 GX Devices and Table: Parameter Type and Corresponding Parameter Bit Width Mapping for Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices. � Updated Watchdog Timeout Value comments by adding "left-most or most-significant bits" to enhance clarity of "upper 12 bits" and statements on bit mapping between data_in and the 12-bit watchdog timeout value in Table: Parameter Type and Corresponding Parameter Bit Width Mapping for Cyclone IV and Intel Cyclone 10 LP Devices.
� Updated the table description in Table: Remote Update Intel FPGA IP Core Avalon-MM Register Map for Cyclone IV Devices.
� Renamed the document as Remote Update Intel FPGA IP User Guide. � Updated Figure: Typical Remote System Upgrade Process. � Updated the note under Figure: Typical Remote System Upgrade
Process. � Added a note to Operations Example Waveforms. � Updated Table: Remote Update Intel FPGA IP Core Parameters for Intel
Arria 10 Devices to update the description for Enable reconfig POF checking. � Rebranded as Intel.

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Table 23. Document Revision History

Date April 2017

Version 2017.04.10

October 2016 June 2016 May 2016

2016.10.31 2016.06.01 2016.05.02

December 2015 November 2015
June 2015

2015.12.14 2015.11.17
2015.06.15

April 2015 January 2015 December 2014

2015.04.07 2015.01.23 2014.12.15

Changes
� Updated Transitions Between Factory and Application Configurations in Remote Update Mode figure.
� Removed redundant statement in Avalon-MM in Altera Remote Update IP Core.
� Updated note in Remote Update Operation table.
� Updated Parameters table for Arria 10 devices and Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices.
� Added Add support for Avalon Interface parameter in Parameter Settings tables.
� Updated Convert Programming File settings in Arria 10 Remote Update Design Example.
� Removed references to Local update mode features.
� Added recommended FMAX for Altera Remote Update IP core. � Added missing title for Cyclone IV Devices Remote Update
Operation table. � Added note on possible PCIe timing violation when using direct-
to-application. � Added note on recommending user to set a fixed configuration
image start address. � Added Enabling Remote System Upgrade subsection.
Updated RU_RECONFIG_TRIGGER_CONDITIONS description for Cyclone V Avalon-MM interface register.
� Updated Page description in Convert Programming Files setting from SOFT DATA PAGE_0 to SOFT DATA PAGE_1.
� Added high level configuration scheme block diagram for remote system upgrade.
� Added Flash Memory Programming Files. � Added design example for Arria 10 devices.
� Added Avalon-MM interface support for Quartus II Software version 15.0.
� Added table for Avalon-MM interface Control Status Registers and register map definitions.
� Added steps for read and write operation for Avalon-MM interface.
� Added example waveforms for read, write, reset timer, ctl_nupdt, and reconfiguration operation for Arria 10 devices.
� Updated the Device Support section to include information on device families that will be phased out from Quartus II software version 15.0.
Added design example link.
Updated Arria 10 remote system configuration mode flow diagram.
� Updated POF checking feature description and invalid configuration image examples.
� Added Arria 10 device support with descriptions, ports and parameters.
� Replaced outdated design examples with a current application design example.
continued...

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Date June 2014 May 2014 August 2013 July 2013
July 2013

Version 2014.06.30 2014.05.13 2013.08.16 2013.07.12
2013.07.12

Changes
� Replaced MegaWizard Plug-In Manager information with IP Catalog.
� Added standard information about upgrading IP cores. � Added standard installation and licensing information. � Removed outdated device support level information. IP core
device support is now available in IP Catalog and parameter editor. � Added a note to recommend users to use 20�MHz fMAX for all devices.
� Updated the Device Support section to include information on device families that will be phased out from Quartus II software version 13.1 and Quartus II software version 14.0.
� Rearranged content for remote system configuration modes, remote system configuration components, parameter settings, ports, param for each group of devices. Refer to Device Support section for more information.
Added Cyclone IV devices support for Active Serial Remote Configuration Mode in Parameters, Output Ports, and Active Serial Remote Configuration Mode.
� Updated Watchdog Timer to include the watchdog reset_time requirement to ensure the validity of the application configuration. Listed the supported devices for the watchdog timer feature.
� Updated Device Support section. � Added Active Serial Remote Configuration Mode to clarify that
the active serial configuration mode is a subset of the remote configuration mode. Also clarified that this mode is only available for EPCS devices. � Added a link to the Configuration Handbook in the Remote System Configuration Modes. � Updated Remote Configuration Mode to add that Cyclone IV E devices support AP configuration scheme and included a link to the Configuration and Remote System Upgrades in Cyclone IV Devices chapter. � Updated Remote System Configuration Components to clarify that the local configuration mode does not support the user watchdog timer feature. � Included a cross-reference to the Input Port in Page Mode Feature. � Updated Parameters to update values and supported devices of the GUI parameter settings. � Updated Factory Configuration to clarify that the default factory configuration address does not apply for Cyclone V devices.
� Added Cyclone III and Cyclone IV Devices Remote Update Operation.
� Updated Input Ports to include Arria V and Cyclone V support for data_in[] port.
� Added Param[] as a standalone section. � Updated Parameter Type and Corresponding Parameter Bit
Width Mapping to include Arria V and Cyclone V support for Reconfiguration trigger conditions parameter. Also updated Page Select parameter to include information for Arria V, Cyclone V, and Stratix V devices. � Updated Parameter Type and Corresponding Parameter Bit Width Mapping to update the Configuration Mode (AnF) information. � Updated Input Ports to add a link to the Configuration, Design Security, and Remote Upgrades in the Cyclone III Device Family chapter.
continued...

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Date
February 2012 August 2010
April 2009
May 2007 March 2007 December 2006 September 2006 March 2005

Version
3.0 2.5
2.4
2.3 2.2 2.1 2.0 1.0

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Changes
� Updated Input Ports to clarify that a falling edge of the reset_timer signal triggers a reset of the user watchdog timer.
� Updated Output Ports to add Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V device support for 24-bit bus for data_out[] port.
� Added Knowledge Base section. � Added Simulation to clarify that simulation capability are for
Arria GX, Stratix, and Stratix II devices only.
Add Cyclone IV support for param[] parameter.
Updated for Quartus II software v10.0, including: � Updated the Device Family Support section. � Add Parameters table to Specifications chapter. � Added new parameters and ports to Specifications chapter. � Added new prototypes and declarations sections to
Specifications chapter. � Updated design example figures and steps.
Updated for Quartus II software v9.0, including: � Updated the section. � Added the Maximum Clock Frequency (fMAX) for the supported
devices. � Updated ports and parameter tables.
Updated for Quartus II software v7.1, including: � Updated to include support for Arria GX devices. � Updated to include Cyclone III device information. � Added Referenced Documents section.
Updated Chapter 1 to include Cyclone III support.
Updated Chapter 1 to include Stratix III support.
General update for Quartus II software version 6.0, including screenshots; added ModelSim�-Altera simulation tool section to Chapter 3.
Initial release.

Remote Update Intel� FPGA IP User Guide 44

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