Actiontec Electronics RGM840 RGMII 802.11ac WLAN module User Manual UserMan

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Date Submitted	2014-07-22 00:00:00
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Document Title	UserMan
Document Creator	Microsoft® Word 2010
Document Author:	lchong

Actiontec 11ac RGMII Module User’s Guide
Part Number: RGM840
Revision 1.3
Date: 10/21/2013
Subject to change
1. Introduction
This document provides the hardware specification for RGM840 module. This module supports
802.11ac standard with 5GHz 4x4 MIMO, 4 spatial streams, transmit beamforming and etc. This
11ac RGMII module uses local memory and flash to fully offload the host processor on the main
board so only minimal software is required on the host for management purpose.
2. Block diagram
The block diagram of the module is shown in figure 1. As indicated in the diagram, this module
uses a proprietary RGMII over mPCIe interface and provides 4 U.FL antenna connectors for
cable antenna.
U.FL
U.FL
FEM
FFE
FEM
FFE
QT
6 KB
Flash
FEM
FFE
FEM
FFE
8B
SPI
QT 8
BC
DDR
WPS
I put
WPS
I put
UART
UART
RGMI
RGMI
RGMII over
PCIe
RGMII over
I/F
PCIe
LEDs/
GPIOs/
HRST
LEDs/
GPIOs/
HRST
Figure 1. Block Diagram of the RGM840 module
3. General feature list
Feature list
Target dimensions [mm]
Signaling connection
Antenna connection
PCB
Chipset
RF FEM
Band support
Freq support
BW
Spatial Streams
Configuration and System
management
WPS
Wi-Fi LED
WPS LED
Radio ON/OFF Control
Factory reset
Hard reset
UART
DDR3 Memory
SPI flash
Calibration data storage
Power Source
Interoperability
MIMO features
Security
Descriptions
80mm(L) x 60mm(W)
RGMII connection over mPCIe connector
4 antenna connections via U.FL connectors .
6 Layers
QV840 (QT3840BC and QT2518B)
Microsemi LX5586H or Triquint TQP8080 (subject to change)
5GHz
5180-5825MHz
20MHz/40MHz/80MHz Mixed mode
Up to 4SS
In-band or Web GUI
WPS input pin
Wi-Fi LED signal pin
WPS LED signal pin
Radio enable/disable pin
Factory reset to default input via mPCIe connector
Hardware reset input via mPCIe connector
via mPCIe connector
16bit – 128MB, 400MHz
64KB ( firmware downloaded via RGMII interface ) or 16MB
SPI flash
via mPCIe connector, 3.3V-2.5A and optional 5V for FEM
Operates with 802.11a/n/ac clients/STA and AP
MU-MIMO, Tx Beamforming and LDPC
WPA,WPA2
4. RF Specification
Items
Total max conductive output
power
TX EVM at antenna port (Subject
to change for manufacturing)
Target Specification
24dBm with 3.3V
RX min. sensitivity (Subject to
change for manufacturing)
20MHz MCS0 -93dBm
20MHz MCS7 -75dBm
40MHz MCS0 -90dBm
40MHz MSC7 -72dBm
+17dBm @3% EVM, HT40, MCS7
+15dBm @1.8% EVM , MCS9 (subject to change)
80MHz MCS0 -87dBm
80MHz MCS7 -66dBm
80MHz MCS9 -60dBm
+/- 1.5 dB max
Output power accuracy
5. Pin assignment
Pins
11
13
Definitions
5V
5V
GND
EXTRST
GND
GMDIO_B
GRXD_I_3
Pin Type
5V DC Input
5V DC Input
Ground
Reset Output
Ground
Bidirectional
Input
Pins
10
12
14
15
17
19
21
23
25
27
29
31
GRXD_I_1
GRXCLK_I
GND
GTXCLK_O
GND
GTXEN_O
GTXD_O_3
GTXD_O_2
GND
Input
Input
Ground
Output
Ground
Output
Output
Output
Ground
16
18
20
22
24
26
28
30
32
33
25M_GPHY
Output
34
35
37
GND
1_AGPIO_B_8
Ground
36
Output (UART TX) 38
39
WLAN_LED
(AGPIO_B_1)
WPS
(AGPIO_B_4)
WPS_LED1
(AGPIO_B_3)
GND
3.3V
3.3V
3.3V
Output, 3.3V,
PWM
Input (0: Active)
Output, 3.3V,
PWM
Ground
3.3V DC Input
3.3V DC Input
3.3V DC Input
41
43
45
47
49
51
Definitions
5V
5V
GND
AGPIO_B_10
AGPIO_B_11
GMDC_O
WLAN_DISABLE
(AGPIO_B_12)
GRXD_I_2
GRXD_I_0
RXDV_I
GND
GTXCLK_I
GND
GTXD_O_1
GTXD_O_0
RTD (Reset to
Default)
(AGPIO_B_5)
AGPIO_B_16
Pin Type
5V DC Input
5V DC Input
Ground
Bidirectional
Bidirectional
Output
Input (0 : Disable)
Output
Output, PWM
40
AGPIO_B_6
WPS_LED2
(AGPIO_B_13)
1_AGPIO_B_0
42
GND
Ground
44
HRST
Input (0 : Active)
46
48
50
52
GND
3.3V
3.3V
3.3V
Ground
3.3V DC Input
3.3V DC Input
3.3V DC Input
Input
Input
Input
Ground
Input
Ground
Output
Output
Input
Bidirectional, PWM
Input (UART RX)
6. Module power requirement
Power supply: 3.3V DC input
Max output power per chain = 18dBm (LX5586H or TQP8080)
Voltage rails
3.3V only
RMS Current rating (Max)
2.5A
7. Hardware reset (HRST) requirement
Since the HRST signal is connected to the hard reset of QT3840BC and is also used to start the linux boot
via RGMII interface, therefore it should be connected to the GPIO pin of the network processor so that it
can be controlled by software. Once the HRST signal is deasserted, the module will start to request tftp
server running on the host processor to fetch the bootloader and firmware image. The HRST should be
keep low for no less than 30ms after the 3.3V supply reaches the nominal voltage.
3.3V
3.3V IN
HRST
30ms
8. Power Management Unit (PMU)
The power management unit is a new feature integrated into the QT3840 chip and it consists of 3
switching regulators and 3 LDOs. The 3 buck converters are designed specifically to generate 1.1V for
QT3840 core voltage, 1.2V for QT2518B, 1.5V for DDR3. The LDOs provide clean output voltages for
oscillator, RF synthesizer and AFE block. In the latest revision of QTM840 RGMII module design, 1.1V for
QT3840 core voltage is fed by external DC-DC switching regulator instead of PMU in the purpose of
reducing the heat dissipation inside the QT3840 package.
FEM
3.3V IN
QT3840BC
PMU
DC-DC SW
1.2V RFIC4
1.5V DDR3
1.1V Core
9. Mechanical drawing
60mm
80mm
10.
Compliance Certifications
1. FCC EMI Certification – pending
2. FCC DFS Certification – pending
3. WiFi Certification - pending
11.
RGMII interface connection example
RGMII signals from the host processor
Signals
Pin descriptions
GTXD3
RGMII Transmit data bit 3
GTXD2
RGMII Transmit data bit 2
GTXD1
RGMII Transmit data bit 1
GTXD0
RGMII Transmit data bit 0
GTXEN
RGMII Transmit enable
GTXCLK RGMII 125MHz TXCLK
GRXCLK RGMII receive clock
GRXDV
GRXD3
GRXD2
GRXD1
GRXD0
12.
1K Pull down resistor
RGMII receive data valid
RGMII Receive data bit 3
RGMII Receive data bit 2
RGMII Receive data bit 1
RGMII Recevie data bit 0
1k Pull down resistor
Pin Type
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Output
Output
RGMII signals from RGMII module pin assignments
Pin
Signals
Pin Type
13
16
15
18
20
17
21
24
25
27
29
28
30
33
GRXD_I_3
GRXD_I_2
GRXD_I_1
GRXD_I_0
RXDV_I
GRXCLK_I
GTXCLK_O
GTXCLK_I
GTXEN_O
GTXD_O_3
GTXD_O_2
GTXD_O_1
GTXD_O_0
25M_GPHY
Input
Input
Input
Input
Input
Input
Output
Input
Output
Output
Output
Output
Output
Output
MDIO/MDC
QT3840BC has a MDIO master controller so it can be used to manage any MDIO slave device on the host
board. The two signals are provided on pin 11 and pin 12 of the mPCIe connector. If there is no need for
QT3840BC to be the MDIO master, then pull down both MDC and MDIO signal to ground with 1K ohm
resistor.
13.
25M_GPHY
25M_GPHY is a free running 25MHz clock generated by QT3840BC.
14.
Booting from 64KB SPI flash
The 64K Byte SPI flash is a cost reduction version of booting from flash mode. The small size of
SPI flash is required to store only the mini-uboot with tftp client feature, calibration data and a
small file system. The external host processor will be required to use its flash memory to store
the uboot and linux image for this module. Besides, it will be allowed to control the boot up
sequence of the target by controlling the hardware reset to the module via pin 44 ~HRST. When
the hardware reset is released, the mini uboot will decompress itself into the internal SRAM of
QT3840BC and then start the tftp client to download the full uboot code and linux image from
external processor via xMII bus to the DDR3 memory of the target. Both target and external
host will need IP addresses for the tftp procotol to work. After the linux kernel is boot up, the
system looks the same as booting from the big flash mode.
Note: The RF calibration of the QTM840 chipset is required for on each target board and it is
executed internally but requires the external calibration software to control DUT and the
Litepoint equipment via telnet session. For any system with external host processor, ethernet
bridge between external ethernet port to wifi ethernet port is needed to bridge the RF
calibration control packets to the QT3840BC.
PC: 1.1.1.1
Ethernet
Host:1.1.1.0
RGMII
QT3840BC:
1.1.1.2
15.
WPS description
The WPS pairing input pin is assigned to pin 41 on the connector and it is active low input. The WPS
input pin can be connected to on board push button or host processor. The current timing requirement
to trigger WPS function is in low state for no less than 6s but the timing can be adjusted.
16.
LED description
There are 3 LEDs provided by the modules and it is active high output signal with pulse width
modulation feature.
1. WLAN_LED (AGPIO_B_1) – Wifi 5GHz LED
Turn on when wifi connection is available
Turn off when wifi connection is not available
Blinking when negotiation or traffic is on line
2. WPS_LED1(AGPIO_B_3) and WPS_LED2 (Red – AGPIO_B_13)
Green on when WPS pairing is active
Blinking 2Hz Green when WPS negotiation is in progress
Solid Red when WPS registration failed
Both off when WPS functionality is disabled
17.
Spare GPIO description
There are 3 spare GPIO reserved for future use. They are AGPIO_B_10, AGPIO_B_11, and
AGPIO_B_16. Those spare GPIOs can be connected to host processor for general use. The
default state of all GPIOs is in input state.
AGPIO_B_10 and AGPIO_B_11 are pulled up on the module.
AGPIO_B_16 are floating on the module and please pulled down if not needed on the main
board.
18.
Console port (UART)
The console port of the module is provided on the module and also through pin 37 (1_AGPIO_B_8) and
pin 40 (1_AGPIO_B_0) of the mPCIe interface. Host processor can communicate to the module through
the console port.
1_AGPIO_B_8 – UART TX signal
1_AGPIO_B_0 – UART RX signal (1K pull up resistor is required at pin 40 of mPCIe connector on the host
processor board)
19.
EMI and Antenna isolation requirement
This module is a 5GHz only radio and requires 25dB isolation from 2.4GHz antenna when dual band dual
concurrent mode is supported in the final product. Otherwise, the throughput performance will be
degraded due to harmonics of 2.4GHz leaking into the 5GHz radio band.
The SoC motherboard typically consists of many subsystems such as DDR2, DDR3, A/VDSL, VOIP, USB
and other high speed interfaces. Each subsystem will operate on different clock frequencies and its
harmonics could fall into the 5GHz band. Please make sure the EMI radiated from different clocks on the
board can be contained or mitigated by either HW or SW solution.

---

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