Compaq 21264 Users Manual

2015-02-03

• Table of Contents
  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • A
  • B
  • C
  • D
  • E
• Figures
• Tables
• Preface
• Introduction
  • 1.1 The Architecture
    • 1.1.1 Addressing
    • 1.1.2 Integer Data Types
    • 1.1.3 Floating-Point Data Types
  • 1.2 21264/EV67 Microprocessor Features
• Internal Architecture
  • 2.1 21264/EV67 Microarchitecture
    • 2.1.1 Instruction Fetch, Issue, and Retire Unit
      • 2.1.1.1 Virtual Program Counter Logic
      • 2.1.1.2 Branch Predictor
      • 2.1.1.3 Instruction-Stream Translation Buffer
      • 2.1.1.4 Instruction Fetch Logic
      • 2.1.1.5 Register Rename Maps
      • 2.1.1.6 Integer Issue Queue
      • 2.1.1.7 Floating-Point Issue Queue
      • 2.1.1.8 Exception and Interrupt Logic
      • 2.1.1.9 Retire Logic
    • 2.1.2 Integer Execution Unit
    • 2.1.3 Floating-Point Execution Unit
    • 2.1.4 External Cache and System Interface Unit
      • 2.1.4.1 Victim Address File and Victim Data File
      • 2.1.4.2 I/O Write Buffer
      • 2.1.4.3 Probe Queue
      • 2.1.4.4 Duplicate Dcache Tag Array
    • 2.1.5 Onchip Caches
      • 2.1.5.1 Instruction Cache
      • 2.1.5.2 Data Cache
    • 2.1.6 Memory Reference Unit
      • 2.1.6.1 Load Queue
      • 2.1.6.2 Store Queue
      • 2.1.6.3 Miss Address File
      • 2.1.6.4 Dstream Translation Buffer
    • 2.1.7 SROM Interface
  • 2.2 Pipeline Organization
    • 2.2.1 Pipeline Aborts
  • 2.3 Instruction Issue Rules
    • 2.3.1 Instruction Group Definitions
    • 2.3.2 Ebox Slotting
    • 2.3.3 Instruction Latencies
  • 2.4 Instruction Retire Rules
    • 2.4.1 Floating-Point Divide/Square Root Early Retire
  • 2.5 Retire of Operate Instructions into R31/F31
  • 2.6 Load Instructions to R31 and F31
    • 2.6.1 Normal Prefetch: LDBU, LDF, LDG, LDL, LDT, LDWU, HW_LDL Instructions
    • 2.6.2 Prefetch with Modify Intent: LDS Instruction
    • 2.6.3 Prefetch, Evict Next: LDQ and HW_LDQ Instructions
    • 2.6.4 Prefetch with the LDx_L / STx_C Instruction Sequence
  • 2.7 Special Cases of Alpha Instruction Execution
    • 2.7.1 Load Hit Speculation
    • 2.7.2 Floating-Point Store Instructions
    • 2.7.3 CMOV Instruction
  • 2.8 Memory and I/O Address Space Instructions
    • 2.8.1 Memory Address Space Load Instructions
    • 2.8.2 I/O Address Space Load Instructions
    • 2.8.3 Memory Address Space Store Instructions
    • 2.8.4 I/O Address Space Store Instructions
  • 2.9 MAF Memory Address Space Merging Rules
  • 2.10 Instruction Ordering
  • 2.11 Replay Traps
    • 2.11.1 Mbox Order Traps
      • 2.11.1.1 Load-Load Order Trap
      • 2.11.1.2 Store-Load Order Trap
    • 2.11.2 Other Mbox Replay Traps
  • 2.12 I/O Write Buffer and the WMB Instruction
    • 2.12.1 Memory Barrier (MB/WMB/TB Fill Flow)
      • 2.12.1.1 MB Instruction Processing
      • 2.12.1.2 WMB Instruction Processing
      • 2.12.1.3 TB Fill Flow
  • 2.13 Performance Measurement Support—Performance Counters
  • 2.14 Floating-Point Control Register
  • 2.15 AMASK and IMPLVER Instruction Values
    • 2.15.1 AMASK
    • 2.15.2 IMPLVER
  • 2.16 Design Examples
• Hardware Interface
  • 3.1 21264/EV67 Microprocessor Logic Symbol
  • 3.2 21264/EV67 Signal Names and Functions
  • 3.3  Pin Assignments
  • 3.4  Mechanical Specifications
  • 3.5  21264/EV67 Packaging
• Cache and External Interfaces
  • 4.1 Introduction to the External Interfaces
    • 4.1.1 System Interface
      • 4.1.1.1 Commands and Addresses
    • 4.1.2 Second-Level Cache (Bcache) Interface
  • 4.2 Physical Address Considerations
  • 4.3 Bcache Structure
    • 4.3.1 Bcache Interface Signals
    • 4.3.2 System Duplicate Tag Stores
  • 4.4 Victim Data Buffer
  • 4.5 Cache Coherency
    • 4.5.1 Cache Coherency Basics
    • 4.5.2 Cache Block States
    • 4.5.3 Cache Block State Transitions
    • 4.5.4 Using SysDc Commands
    • 4.5.5 Dcache States and Duplicate Tags
  • 4.6 Lock Mechanism
    • 4.6.1 In-Order Processing of LDx_L/STx_C Instructions
    • 4.6.2 Internal Eviction of LDx_L Blocks
    • 4.6.3 Liveness and Fairness
    • 4.6.4 Managing Speculative Store Issues with Multiprocessor Systems
  • 4.7 System Port
    • 4.7.1 System Port Pins
    • 4.7.2 Programming the System Interface Clocks
    • 4.7.3 21264/EV67-to-System Commands
      • 4.7.3.1 Bank Interleave on Cache Block Boundary Mode
      • 4.7.3.2 Page Hit Mode
    • 4.7.4 21264/EV67-to-System Commands Descriptions
    • 4.7.5 ProbeResponse Commands (Command[4:0] = 00001)
    • 4.7.6 SysAck and 21264/EV67-to-System Commands Flow Control
    • 4.7.7 System-to-21264/EV67 Commands
      • 4.7.7.1 Probe Commands (Four Cycles)
      • 4.7.7.2 Data Transfer Commands (Two Cycles)
    • 4.7.8 Data Movement In and Out of the 21264/EV67
      • 4.7.8.1 21264/EV67 Clock Basics
      • 4.7.8.2 Fast Data Mode
      • 4.7.8.3 Fast Data Disable Mode
      • 4.7.8.4 SysDataInValid_L and SysDataOutValid_L
      • 4.7.8.5 SysFillValid_L
      • 4.7.8.6 Data Wrapping
    • 4.7.9 Nonexistent Memory Processing
    • 4.7.10 Ordering of System Port Transactions
      • 4.7.10.1 21264/EV67 Commands and System Probes
      • 4.7.10.2 System Probes and SysDc Commands
  • 4.8 Bcache Port
    • 4.8.1 Bcache Port Pins
    • 4.8.2 Bcache Clocking
      • 4.8.2.1 Setting the Period of the Cache Clock
    • 4.8.3 Bcache Transactions
      • 4.8.3.1 Bcache Data Read and Tag Read Transactions
      • 4.8.3.2 Bcache Data Write Transactions
      • 4.8.3.3 Bubbles on the Bcache Data Bus
    • 4.8.4 Pin Descriptions
      • 4.8.4.1 BcAdd_H[23:4]
      • 4.8.4.2 Bcache Control Pins
      • 4.8.4.3 BcDataInClk_H and BcTagInClk_H
    • 4.8.5 Bcache Banking
    • 4.8.6 Disabling the Bcache for Debugging
  • 4.9 Interrupts
• Internal Processor Registers
  • 5.1 Ebox IPRs
    • 5.1.1 Cycle Counter Register – CC
    • 5.1.2 Cycle Counter Control Register – CC_CTL
    • 5.1.3 Virtual Address Register – VA
    • 5.1.4 Virtual Address Control Register – VA_CTL
    • 5.1.5 Virtual Address Format Register – VA_FORM
  • 5.2 Ibox IPRs
    • 5.2.1 ITB Tag Array Write Register – ITB_TAG
    • 5.2.2 ITB PTE Array Write Register – ITB_PTE
    • 5.2.3 ITB Invalidate All Process (ASM=0) Register – ITB_IAP
    • 5.2.4 ITB Invalidate All Register – ITB_IA
    • 5.2.5 ITB Invalidate Single Register – ITB_IS
    • 5.2.6 ProfileMe PC Register – PMPC
    • 5.2.7 Exception Address Register – EXC_ADDR
    • 5.2.8 Instruction Virtual Address Format Register — IVA_FORM
    • 5.2.9 Interrupt Enable and Current Processor Mode Register – IER_CM
    • 5.2.10 Software Interrupt Request Register – SIRR
    • 5.2.11 Interrupt Summary Register – ISUM
    • 5.2.12 Hardware Interrupt Clear Register – HW_INT_CLR
    • 5.2.13 Exception Summary Register – EXC_SUM
    • 5.2.14 PAL Base Register – PAL_BASE
    • 5.2.15 Ibox Control Register – I_CTL
    • 5.2.16 Ibox Status Register – I_STAT
    • 5.2.17 Icache Flush Register – IC_FLUSH
    • 5.2.18 Icache Flush ASM Register – IC_FLUSH_ASM
    • 5.2.19 Clear Virtual-to-Physical Map Register – CLR_MAP
    • 5.2.20 Sleep Mode Register – SLEEP
    • 5.2.21 Process Context Register – PCTX
    • 5.2.22 Performance Counter Control Register – PCTR_CTL
  • 5.3 Mbox IPRs
    • 5.3.1 DTB Tag Array Write Registers 0 and 1 – DTB_TAG0, DTB_TAG1
    • 5.3.2 DTB PTE Array Write Registers 0 and 1 – DTB_PTE0, DTB_PTE1
    • 5.3.3 DTB Alternate Processor Mode Register – DTB_ALTMODE
    • 5.3.4 Dstream TB Invalidate All Process (ASM=0) Register – DTB_IAP
    • 5.3.5 Dstream TB Invalidate All Register – DTB_IA
    • 5.3.6 Dstream TB Invalidate Single Registers 0 and 1 – DTB_IS0,1
    • 5.3.7 Dstream TB Address Space Number Registers 0 and 1 – DTB_ASN0,1
    • 5.3.8 Memory Management Status Register – MM_STAT
    • 5.3.9 Mbox Control Register – M_CTL
    • 5.3.10 Dcache Control Register – DC_CTL
    • 5.3.11 Dcache Status Register – DC_STAT
  • 5.4 Cbox CSRs and IPRs
    • 5.4.1 Cbox Data Register – C_DATA
    • 5.4.2 Cbox Shift Register – C_SHFT
    • 5.4.3 Cbox WRITE_ONCE Chain Description
    • 5.4.4 Cbox WRITE_MANY Chain Description
    • 5.4.5 Cbox Read Register (IPR) Description
• Privileged Architecture Library Code
  • 6.1 PALcode Description
  • 6.2 PALmode Environment
  • 6.3 Required PALcode Function Codes
  • 6.4 Opcodes Reserved for PALcode
    • 6.4.1 HW_LD Instruction
    • 6.4.2 HW_ST Instruction
    • 6.4.3 HW_RET Instruction
    • 6.4.4 HW_MFPR and HW_MTPR Instructions
  • 6.5 Internal Processor Register Access Mechanisms
    • 6.5.1 IPR Scoreboard Bits
    • 6.5.2 Hardware Structure of Explicitly Written IPRs
    • 6.5.3 Hardware Structure of Implicitly Written IPRs
    • 6.5.4 IPR Access Ordering
    • 6.5.5 Correct Ordering of Explicit Writers Followed by Implicit Readers
    • 6.5.6 Correct Ordering of Explicit Readers Followed by Implicit Writers
  • 6.6 PALshadow Registers
  • 6.7 PALcode Emulation of the FPCR
    • 6.7.1 Status Flags
    • 6.7.2 MF_FPCR
    • 6.7.3 MT_FPCR
  • 6.8 PALcode Entry Points
    • 6.8.1 CALL_PAL Entry Points
    • 6.8.2 PALcode Exception Entry Points
  • 6.9 Translation Buffer (TB) Fill Flows
    • 6.9.1 DTB Fill
    • 6.9.2 ITB Fill
  • 6.10 Performance Counter Support
    • 6.10.1 General Precautions
    • 6.10.2 Aggregate Mode Programming Guidelines
      • 6.10.2.1 Aggregate Mode Precautions
      • 6.10.2.2 Operation
      • 6.10.2.3 Aggregate Counting Mode Description
        • 6.10.2.3.1 Cycle counting
        • 6.10.2.3.2 Retired instructions cycles
        • 6.10.2.3.3 Bcache miss or long latency probes cycles
        • 6.10.2.3.4 Mbox replay traps cycles
      • 6.10.2.4 Counter Modes for Aggregate Mode
    • 6.10.3 ProfileMe Mode Programming Guidelines
      • 6.10.3.1 ProfileMe Mode Precautions
      • 6.10.3.2 Operation
      • 6.10.3.3 ProfileMe Counting Mode Description
        • 6.10.3.3.1 Cycle counting
        • 6.10.3.3.2 Inum retire delay cycles
        • 6.10.3.3.3 Retired instructions cycles
        • 6.10.3.3.4 Bcache miss or long latency probes cycles
        • 6.10.3.3.5 Mbox replay traps cycles
      • 6.10.3.4 Counter Modes for ProfileMe Mode
• Initialization and Configuration
  • 7.1 Power-Up Reset Flow and the Reset_L and DCOK_H Pins
    • 7.1.1 Power Sequencing and Reset State for Signal Pins
    • 7.1.2 Clock Forwarding and System Clock Ratio Configuration
    • 7.1.3 PLL Ramp Up
    • 7.1.4 BiST and SROM Load and the TestStat_H Pin
    • 7.1.5 Clock Forward Reset and System Interface Initialization
  • 7.2 Fault Reset Flow
  • 7.3 Energy Star Certification and Sleep Mode Flow
  • 7.4 Warm Reset Flow
  • 7.5 Array Initialization
  • 7.6 Initialization Mode Processing
  • 7.7 External Interface Initialization
  • 7.8 Internal Processor Register Power-Up Reset State
  • 7.9 IEEE 1149.1 Test Port Reset
  • 7.10 Reset State Machine
  • 7.11 Phase-Lock Loop (PLL) Functional Description
    • 7.11.1  Differential Reference Clocks
    • 7.11.2  PLL Output Clocks
      • 7.11.2.1  GCLK
      • 7.11.2.2  Differential 21264/EV67 Clocks
      • 7.11.2.3  Nominal Operating Frequency
      • 7.11.2.4  Power-Up/Reset Clocking
• Error Detection and Error Handling
  • 8.1 Data Error Correction Code
  • 8.2 Icache Data or Tag Parity Error
  • 8.3 Dcache Tag Parity Error
  • 8.4 Dcache Data Single-Bit Correctable ECC Error
    • 8.4.1 Load Instruction
    • 8.4.2 Store Instruction (Quadword or Smaller)
    • 8.4.3 Dcache Victim Extracts
  • 8.5 Dcache Store Second Error
  • 8.6 Dcache Duplicate Tag Parity Error
  • 8.7 Bcache Tag Parity Error
  • 8.8 Bcache Data Single-Bit Correctable ECC Error
    • 8.8.1 Icache Fill from Bcache
    • 8.8.2 Dcache Fill from Bcache
    • 8.8.3 Bcache Victim Read
      • 8.8.3.1 Bcache Victim Read During a Dcache/Bcache Miss
      • 8.8.3.2 Bcache Victim Read During an ECB Instruction
  • 8.9 Memory/System Port Single-Bit Data Correctable ECC Error
    • 8.9.1 Icache Fill from Memory
    • 8.9.2 Dcache Fill from Memory
  • 8.10 Bcache Data Single-Bit Correctable ECC Error on a Probe
  • 8.11 Double-Bit Fill Errors
  • 8.12 Error Case Summary
• Electrical Data
  • 9.1 Electrical Characteristics
  • 9.2 DC Characteristics
  • 9.3 Power Supply Sequencing and Avoiding Potential Failure Mechanisms
  • 9.4 AC Characteristics
• Thermal Management
  • 10.1 Operating Temperature
  • 10.2 Heat Sink Specifications
  • 10.3 Thermal Design Considerations
• Testability and Diagnostics
  • 11.1 Test Pins
  • 11.2 SROM/Serial Diagnostic Terminal Port
    • 11.2.1 SROM Load Operation
    • 11.2.2 Serial Terminal Port
  • 11.3 IEEE 1149.1 Port
  • 11.4 TestStat_H Pin
  • 11.5 Power-Up Self-Test and Initialization
    • 11.5.1 Built-in Self-Test
    • 11.5.2 SROM Initialization
      • 11.5.2.1 Serial Instruction Cache Load Operation
  • 11.6 Notes on IEEE 1149.1 Operation and Compliance
• Alpha Instruction Set
  • A.1 Alpha Instruction Summary
  • A.2 Reserved Opcodes
    • A.2.1 Opcodes Reserved for Compaq
    • A.2.2 Opcodes Reserved for PALcode
  • A.3 IEEE Floating-Point Instructions
  • A.4 VAX Floating-Point Instructions
  • A.5 Independent Floating-Point Instructions
  • A.6 Opcode Summary
  • A.7 Required PALcode Function Codes
  • A.8 IEEE Floating-Point Conformance
• 21264/EV67 Boundary-Scan Register
  • B.1 Boundary-Scan Register
    • B.1.1 BSDL Description of the Alpha 21264/EV67 Boundary-Scan Register
• Serial Icache Load Predecode Values
• PALcode Restrictions and Guidelines
  • D.1 Restriction 1 : Reset Sequence Required by Retire Logic and Mapper
  • D.2 Restriction 2 : No Multiple Writers to IPRs in Same Scoreboard Group
  • D.3 Restriction 4 : No Writers and Readers to IPRs in Same Scoreboard Group
  • D.4 Guideline 6 : Avoid Consecutive Read-Modify-Write-Read- Modify-Write
  • D.5 Restriction 7 : Replay Trap, Interrupt Code Sequence, and STF/ ITOF
  • D.6 Restriction 9 : PALmode Istream Address Ranges
  • D.7 Restriction 10: Duplicate IPR Mode Bits
  • D.8 Restriction 11: Ibox IPR Update Synchronization
  • D.9 Restriction 12: MFPR of Implicitly-Written IPRs EXC_ADDR, IVA_FORM, and EXC_SUM
  • D.10 Restriction 13 : DTB Fill Flow Collision
  • D.11 Restriction 14 : HW_RET
  • D.12 Guideline 16 : JSR-BAD VA
  • D.13 Restriction 17: MTPR to DTB_TAG0/DTB_PTE0/DTB_TAG1/ DTB_PTE1
  • D.14 Restriction 18: No FP Operates, FP Conditional Branches, FTOI, or STF in Same Fetch Block a...
  • D.15 Restriction 19: HW_RET/STALL After Updating the FPCR by way of MT_FPCR in PALmode
  • D.16 Guideline 20 : I_CTL[SBE] Stream Buffer Enable
  • D.17 Restriction 21: HW_RET/STALL After HW_MTPR ASN0/ASN1
  • D.18 Restriction 22: HW_RET/STALL After HW_MTPR IS0/IS1
  • D.19 Restriction 23: HW_ST/P/CONDITIONAL Does Not Clear the Lock Flag
  • D.20 Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, CLEAR_MAP
  • D.21 Restriction 25: HW_MTPR ITB_IA After Reset
  • D.22 Guideline 26: Conditional Branches in PALcode
  • D.23 Restriction 27: Reset of ‘Force-Fail Lock Flag’ State in PALcode
  • D.24 Restriction 28: Enforce Ordering Between IPRs Implicitly Written by Loads and Subsequent Loads
  • D.25 Guideline 29 : JSR, JMP, RET, and JSR_COR in PALcode
  • D.26 Restriction 30 : HW_MTPR and HW_MFPR to the Cbox CSR
  • D.27 Restriction 31 : I_CTL[VA_48] Update
  • D.28 Restriction 32 : PCTR_CTL Update
  • D.29 Restriction 33 : HW_LD Physical/Lock Use
  • D.30 Restriction 34 : Writing Multiple ITB Entries in the Same PALcode Flow
  • D.31 Guideline 35 : HW_INT_CLR Update
  • D.32 Restriction 36 : Updating I_CTL[SDE]
  • D.33 Restriction 37 : Updating VA_CTL[VA_48]
  • D.34 Restriction 38 : Updating PCTR_CTL
  • D.35 Guideline 39: Writing Multiple DTB Entries in the Same PAL Flow
  • D.36 Restriction 40: Scrubbing a Single-Bit Error
  • D.37 Restriction 41: MTPR ITB_TAG, MTPR ITB_PTE Must Be in the Same Fetch Block
  • D.38 Restriction 42: Updating VA_CTL, CC_CTL, or CC IPRs
  • D.39 Restriction 43: No Trappable Instructions Along with HW_MTPR
  • D.40 Restriction 44: Not Applicable to the 21264/EV67
  • D.41 Restriction 45: No HW_JMP or JMP Instructions in PALcode
  • D.42 Restriction 46: Avoiding Live locks in Speculative Load CRD Handlers
  • D.43 Restriction 47: Cache Eviction for Single-Bit Cache Errors
  • D.44 Restriction 48: MB Bracketing of Dcache Writes to Force Bad Data ECC and Force Bad Tag Parity
• 21264/EV67-to-Bcache Pin Interconnections
  • E.1 Forwarding Clock Pin Groupings
  • E.2 Late-Write Non-Bursting SSRAMs
  • E.3 Dual-Data Rate SSRAMs
• Glossary
• Index
  • Numerics
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