AD5696/AD5694 (Rev. A) AD5696 5694
2015-07-24
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Quad, 16-/12-Bit nanoDAC+ with I2C Interface AD5696/AD5694 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD High relative accuracy (INL): ±2 LSB maximum at 16 bits Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum VREF AD5696/AD5694 VLOGIC INPUT REGISTER DAC REGISTER STRING DAC A SCL VOUTA BUFFER INTERFACE LOGIC SDA A1 A0 INPUT REGISTER DAC REGISTER STRING DAC B VOUTB BUFFER INPUT REGISTER DAC REGISTER STRING DAC C VOUTC BUFFER INPUT REGISTER DAC REGISTER STRING DAC D VOUTD BUFFER LDAC RESET POWER-ON RESET GAIN = ×1/×2 RSTSEL GAIN POWERDOWN LOGIC Figure 1. APPLICATIONS Digital gain and offset adjustment Programmable attenuators Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION Table 1. Quad nanoDAC+ Devices The AD5696 and AD5694, members of the nanoDAC+™ family, are low power, quad, 16-/12-bit buffered voltage output DACs. The devices include a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and 1.5 mV offset error performance. The devices are available in a 3 mm × 3 mm LFCSP package and in a TSSOP package. Interface SPI The AD5696/AD5694 incorporate a power-on reset circuit and a RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. The parts contain a per-channel power-down feature that reduces the current consumption of the device in power-down mode to 4 µA at 3 V. The AD5696/AD5694 use a versatile 2-wire serial interface that operates at clock rates up to 400 kHz and include a VLOGIC pin intended for 1.8 V/3 V/5 V logic. Rev. A I2 C Reference Internal External Internal External 16-Bit AD5686R AD5686 AD5696R AD5696 14-Bit AD5685R AD5695R 12-Bit AD5684R AD5684 AD5694R AD5694 PRODUCT HIGHLIGHTS 1. 2. 3. High Relative Accuracy (INL). AD5696 (16-bit): ±2 LSB maximum AD5694 (12-bit): ±1 LSB maximum Excellent DC Performance. Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum Two Package Options. 3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOP Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 10799-001 Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User-selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility 400 kHz I2C-compatible serial interface 4 I2C addresses available Low glitch: 0.5 nV-sec Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating Low power: 1.8 mW at 3 V 2.7 V to 5.5 V power supply −40°C to +105°C temperature range GND AD5696/AD5694 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 17 Applications ....................................................................................... 1 Write and Update Commands .................................................. 18 Functional Block Diagram .............................................................. 1 I2C Slave Address ........................................................................ 18 General Description ......................................................................... 1 Serial Operation ......................................................................... 18 Product Highlights ........................................................................... 1 Write Operation.......................................................................... 18 Revision History ............................................................................... 2 Read Operation........................................................................... 19 Specifications..................................................................................... 3 Multiple DAC Readback Sequence .......................................... 19 AC Characteristics ........................................................................ 5 Power-Down Operation ............................................................ 20 Timing Characteristics ................................................................ 6 Load DAC (Hardware LDAC Pin) ........................................... 20 Absolute Maximum Ratings ............................................................ 7 LDAC Mask Register ................................................................. 21 Thermal Resistance ...................................................................... 7 Hardware Reset Pin (RESET) ................................................... 21 ESD Caution .................................................................................. 7 Reset Select Pin (RSTSEL) ........................................................ 21 Pin Configurations and Function Descriptions ........................... 8 Applications Information .............................................................. 22 Typical Performance Characteristics ............................................. 9 Microprocessor Interfacing ....................................................... 22 Terminology .................................................................................... 14 AD5696/AD5694 to ADSP-BF531 Interface .......................... 22 Theory of Operation ...................................................................... 16 Layout Guidelines....................................................................... 22 Digital-to-Analog Converter .................................................... 16 Galvanically Isolated Interface ................................................. 22 Transfer Function ....................................................................... 16 Outline Dimensions ....................................................................... 23 DAC Architecture ....................................................................... 16 Ordering Guide .......................................................................... 24 REVISION HISTORY 6/13—Rev. 0 to Rev. A Changes to Pin GAIN and Pin RSTSEL Descriptions; Table 7....... 8 7/12—Revision 0: Initial Version Rev. A | Page 2 of 24 Data Sheet AD5696/AD5694 SPECIFICATIONS VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE 2 AD5696 Resolution Relative Accuracy Min A Grade Typ 16 Min B Grade Typ Max Unit ±1 ±1 ±2 ±3 ±1 Bits LSB LSB LSB ±1 ±1 Bits LSB LSB 16 ±2 ±2 ±8 ±8 ±1 ±0.12 ±2 ±1 ±0.12 4 ±4 ±0.2 ±0.2 ±0.25 ±0.25 0.4 +0.1 +0.01 ±0.02 ±0.01 Differential Nonlinearity AD5694 Resolution Relative Accuracy Differential Nonlinearity Max 12 12 Zero-Code Error Offset Error Full-Scale Error Gain Error Total Unadjusted Error 0.4 +0.1 +0.01 ±0.02 ±0.01 Offset Error Drift3 Gain Temperature Coefficient3 DC Power Supply Rejection Ratio3 DC Crosstalk3 ±1 ±1 ±1 ±1 mV mV % of FSR % of FSR % of FSR % of FSR µV/°C ppm 0.15 0.15 mV/V ±2 ±2 µV ±3 ±2 ±3 ±2 µV/mA µV OUTPUT CHARACTERISTICS 3 Output Voltage Range 0 0 Capacitive Load Stability Resistive Load 4 Load Regulation VREF 2 × VREF 2 10 1 REFERENCE INPUT Reference Current Reference Input Impedance 0 0 2 10 Short-Circuit Current 5 Load Impedance at Rails 6 Power-Up Time Reference Input Range VREF 2 × VREF 1.5 ±1.5 ±0.1 ±0.1 ±0.1 ±0.2 1 V V nF nF kΩ 80 80 µV/mA 80 80 µV/mA 40 25 2.5 40 25 2.5 mA Ω µs 90 180 90 180 µA µA V V kΩ kΩ 1 1 VDD VDD/2 1 1 16 32 VDD VDD/2 16 32 Rev. A | Page 3 of 24 Test Conditions/Comments 1 Gain = 2 Gain = 1 Guaranteed monotonic by design Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register Gain = 2 Gain = 1 Of FSR/°C DAC code = midscale; VDD = 5 V ± 10% Due to single channel, fullscale output change Due to load current change Due to power-down (per channel) Gain = 1 Gain = 2 (see Figure 20) RL = ∞ RL = 1 kΩ DAC code = midscale 5 V ± 10%; −30 mA ≤ IOUT ≤ +30 mA 3 V ± 10%; −20 mA ≤ IOUT ≤ +20 mA See Figure 20 Coming out of power-down mode; VDD = 5 V VREF = VDD = 5.5 V, gain = 1 VREF = VDD = 5.5 V, gain = 2 Gain = 1 Gain = 2 Gain = 2 Gain = 1 AD5696/AD5694 Parameter LOGIC INPUTS3 Input Current Input Low Voltage, VINL Input High Voltage, VINH Pin Capacitance LOGIC OUTPUTS (SDA)3 Output Low Voltage, VOL Output High Voltage, VOH Floating State Output Capacitance POWER REQUIREMENTS VLOGIC ILOGIC VDD Data Sheet Min A Grade Typ Max Min B Grade Typ ±2 0.3 × VLOGIC 0.7 × VLOGIC Max Unit Test Conditions/Comments 1 ±2 0.3 × VLOGIC µA V V pF Per pin 0.4 V V pF ISINK = 3 mA ISOURCE = 3 mA 5.5 3 5.5 5.5 V µA V V 0.7 4 6 mA µA µA 0.7 × VLOGIC 2 2 0.4 VLOGIC − 0.4 VLOGIC − 0.4 4 1.8 4 5.5 3 5.5 5.5 2.7 VREF + 1.5 1.8 2.7 VREF + 1.5 IDD Normal Mode 7 All Power-Down Modes 8 0.59 1 0.7 4 6 0.59 1 Gain = 1 Gain = 2 VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V −40°C to +85°C −40°C to +105°C Temperature range is −40°C to +105°C. DC specifications are tested with the outputs unloaded, unless otherwise noted. Upper dead band (10 mV) exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5696) or 12 to 4080 (AD5694). 3 Guaranteed by design and characterization; not production tested. 4 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to 30 mA up to a junction temperature of 110°C. 5 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded during current limit. Operation above the specified maximum junction temperature may impair device reliability. 6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 20). 7 Interface inactive. All DACs active. DAC outputs unloaded. 8 All DACs powered down. 1 2 Rev. A | Page 4 of 24 Data Sheet AD5696/AD5694 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1, 2 Output Voltage Settling Time AD5696 AD5694 Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Multiplying Bandwidth Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Total Harmonic Distortion 4 Output Noise Spectral Density Output Noise Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Signal-to-Noise-and-Distortion Ratio (SINAD) Min Typ Max Unit 5 5 0.8 0.5 0.13 500 0.1 0.2 0.3 −80 100 6 90 83 80 8 7 µs µs V/µs nV-sec nV-sec kHz nV-sec nV-sec nV-sec dB nV/√Hz µV p-p dB dB dB Guaranteed by design and characterization; not production tested. See the Terminology section. 3 Temperature range is −40°C to +105°C; typical at 25°C. 4 Digitally generated sine wave at 1 kHz. 1 2 Rev. A | Page 5 of 24 Test Conditions/Comments 3 ¼ to ¾ scale settling to ±2 LSB 1 LSB change around major carry transition At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz DAC code = midscale, 10 kHz, gain = 2 0.1 Hz to 10 Hz At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz AD5696/AD5694 Data Sheet TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter1, 2 t1 t2 t3 t4 t5 t63 t7 t8 t9 t104 t114, 5 t12 t13 tSP6 CB 5 Min 2.5 0.6 1.3 0.6 100 0 0.6 0.6 1.3 0 20 + 0.1CB 20 400 0 Max 0.9 300 300 50 400 Unit μs μs μs μs ns μs μs μs μs ns ns ns ns ns pF Description SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD,STA, start/repeated start hold time tSU,DAT, data setup time tHD,DAT, data hold time tSU,STA, repeated start setup time tSU,STO, stop condition setup time tBUF, bus free time between a stop condition and a start condition tR, rise time of SCL and SDA when receiving tF, fall time of SCL and SDA when transmitting/receiving LDAC pulse width SCL rising edge to LDAC rising edge Pulse width of suppressed spike Capacitive load for each bus line 1 See Figure 2. Guaranteed by design and characterization; not production tested. A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the SCL falling edge. 4 tR and tF are measured from 0.3 × VDD to 0.7 × VDD. 5 CB is the total capacitance of one bus line in pF. 6 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns. 2 3 Timing Diagram START CONDITION REPEATED START CONDITION STOP CONDITION SDA t9 t10 t11 t4 t3 SCL t4 t2 t6 t5 t7 t1 t8 t12 t13 LDAC1 t12 LDAC2 10799-002 NOTES 1ASYNCHRONOUS 2SYNCHRONOUS LDAC UPDATE MODE. LDAC UPDATE MODE. Figure 2. 2-Wire Serial Interface Timing Diagram Rev. A | Page 6 of 24 Data Sheet AD5696/AD5694 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 5. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. This value was measured using a JEDEC standard 4-layer board with zero airflow. For the LFCSP package, the exposed pad must be tied to GND. Parameter VDD to GND VLOGIC to GND VOUT to GND VREF to GND Digital Input Voltage to GND1 SDA and SCL to GND Operating Temperature Range Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb Free (J-STD-020) ESD Human Body Model (HBM) Field-Induced Charged Device Model (FICDM) 1 Rating −0.3 V to +7 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VLOGIC + 0.3 V −0.3 V to +7 V −40°C to +105°C −65°C to +150°C 125°C 260°C Table 6. Thermal Resistance Package Type 16-Lead LFCSP 16-Lead TSSOP ESD CAUTION 3.5 kV 1.5 kV Excluding SDA and SCL. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 7 of 24 θJA 70 112.6 Unit °C/W °C/W AD5696/AD5694 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUTA 1 12 A1 GAIN 8 LDAC 7 SDA 6 VOUTD 5 RESET 14 A1 13 SCL 12 A0 VOUTC 6 11 VLOGIC VOUTD 7 10 GAIN SDA 8 9 LDAC VDD 5 9 VLOGIC VOUTC 4 RSTSEL 15 GND 4 10 A0 VDD 3 16 VOUTA 3 11 SCL GND 2 VREF 1 VOUTB 2 AD5696/ AD5694 TOP VIEW (Not to Scale) 10799-007 13 RESET 14 RSTSEL 16 VOUTB 15 VREF AD5696/AD5694 NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. 10799-006 TOP VIEW (Not to Scale) Figure 3. Pin Configuration, 16-Lead LFCSP Figure 4. Pin Configuration, 16-Lead TSSOP Table 7. Pin Function Descriptions LFCSP 1 2 3 Pin No. TSSOP 3 4 5 Mnemonic VOUTA GND VDD 4 5 6 6 7 8 VOUTC VOUTD SDA 7 9 LDAC 8 10 GAIN 9 10 11 11 12 13 VLOGIC A0 SCL 12 13 14 15 A1 RESET 14 16 RSTSEL 15 16 17 1 2 N/A VREF VOUTB EPAD Description Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Power Supply Input. The parts can be operated from 2.7 V to 5.5 V. The supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. LDAC can be operated in two modes, asynchronous update mode and synchronous update mode. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data; all DAC outputs are simultaneously updated. This pin can also be tied permanently low. Gain Select Pin. When this pin is tied to GND, all four DAC outputs have a span of 0 V to VREF. When this pin is tied to VLOGIC, all four DAC outputs have a span of 0 V to 2 × VREF. Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V. Address Input. Sets the first LSB of the 7-bit slave address. Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 24-bit input shift register. Address Input. Sets the second LSB of the 7-bit slave address. Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is activated (low), the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. When RESET is low, all LDAC pulses are ignored. Power-On Reset Pin. When this pin is tied to GND, all four DACs are powered up to zero scale. When this pin is tied to VLOGIC, all four DACs are powered up to midscale. Reference Input Voltage. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Exposed Pad. The exposed pad must be tied to GND. Rev. A | Page 8 of 24 Data Sheet AD5696/AD5694 1.0 8 0.8 6 0.6 4 0.4 2 0.2 0 –2 0 –0.2 –4 –0.4 –6 –0.6 VDD = 5V TA = 25°C REFERENCE = 2.5V –0.8 30000 40000 50000 60000 CODE –1.0 0 625 8 6 6 4 4 ERROR (LSB) 8 2 0 –2 2 3750 4096 DNL –6 –6 –8 3125 3750 4096 INL –2 –4 CODE VDD = 5V TA = 25°C REFERENCE = 2.5V –10 –40 10 60 110 TEMPERATURE (°C) Figure 6. AD5694 INL Figure 9. INL Error and DNL Error vs. Temperature 10 0.8 8 0.6 6 0.4 4 ERROR (LSB) 1.0 0.2 0 –0.2 2 INL 0 DNL –2 –4 –0.4 VDD = 5V TA = 25°C REFERENCE = 2.5V –0.8 –1.0 0 10000 20000 30000 40000 CODE 50000 60000 –8 VDD = 5V TA = 25°C –10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VREF (V) Figure 7. AD5696 DNL Figure 10. INL Error and DNL Error vs. VREF Rev. A | Page 9 of 24 4.5 5.0 10799-125 –6 –0.6 10799-121 DNL (LSB) 3125 0 –4 10799-120 INL (LSB) 10 2500 2500 Figure 8. AD5694 DNL 10 1875 1875 CODE Figure 5. AD5696 INL V = 5V –8 DD TA = 25°C REFERENCE = 2.5V –10 0 625 1250 1250 10799-124 V = 5V –8 DD TA = 25°C REFERENCE = 2.5V –10 0 10000 20000 10799-123 DNL (LSB) 10 10799-118 INL (LSB) TYPICAL PERFORMANCE CHARACTERISTICS Data Sheet 10 0.10 8 0.08 6 0.06 4 0.04 ERROR (% of FSR) 2 INL 0 DNL –2 –4 –6 0.02 GAIN ERROR 0 FULL-SCALE ERROR –0.02 –0.04 –0.06 4.2 4.7 VDD = 5V –0.08 T = 25°C A REFERENCE = 2.5V –0.10 2.7 3.2 3.7 10799-126 VDD = 5V –8 TA = 25°C REFERENCE = 2.5V –10 3.2 3.7 2.7 5.2 SUPPLY VOLTAGE (V) 4.2 4.7 10799-129 ERROR (LSB) AD5696/AD5694 5.2 SUPPLY VOLTAGE (V) Figure 11. INL Error and DNL Error vs. Supply Voltage Figure 14. Gain Error and Full-Scale Error vs. Supply Voltage 1.5 0.10 0.08 1.0 0.04 0.5 FULL-SCALE ERROR 0.02 0 ERROR (mV) GAIN ERROR –0.02 OFFSET ERROR –1.0 40 60 80 100 120 TEMPERATURE (°C) 4.2 4.7 5.2 0.10 TOTAL UNADJUSTED ERROR (% of FSR) 1.2 1.0 0.8 0.6 ZERO-CODE ERROR 0.2 20 40 60 80 100 120 TEMPERATURE (°C) 10799-128 OFFSET ERROR 0 3.7 Figure 15. Zero-Code Error and Offset Error vs. Supply Voltage VDD = 5V 1.4 T = 25°C A REFERENCE = 2.5V –20 3.2 SUPPLY VOLTAGE (V) Figure 12. Gain Error and Full-Scale Error vs. Temperature 0.4 VDD = 5V TA = 25°C REFERENCE = 2.5V –1.5 2.7 10799-127 VDD = 5V –0.08 T = 25°C A REFERENCE = 2.5V –0.10 –40 –20 0 20 10799-130 –0.06 ERROR (mV) 0 –0.5 –0.04 0 –40 ZERO-CODE ERROR Figure 13. Zero-Code Error and Offset Error vs. Temperature VDD = 5V 0.09 TA = 25°C REFERENCE = 2.5V 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 16. TUE vs. Temperature Rev. A | Page 10 of 24 100 120 10799-131 ERROR (% of FSR) 0.06 AD5696/AD5694 0.10 1.0 0.08 0.8 0.06 0.6 0.04 0.4 0.02 0.2 ΔVOUT (V) SINKING, 2.7V 0 –0.02 SINKING, 5V 0 –0.2 –0.04 –0.4 –0.06 –0.6 SOURCING, 5V SOURCING, 2.7V VDD = 5V –0.08 T = 25°C A REFERENCE = 2.5V –0.10 3.2 3.7 2.7 4.2 4.7 5.2 –1.0 SUPPLY VOLTAGE (V) 0 10 15 20 25 30 LOAD CURRENT (mA) Figure 17. TUE vs. Supply Voltage, Gain = 1 Figure 20. Headroom/Footroom vs. Load Current 7 0 VDD = 5V 6 TA = 25°C REFERENCE = 2.5V GAIN = 2 5 –0.01 –0.02 –0.03 0xFFFF 4 0xC000 VOUT (V) –0.04 –0.05 –0.06 3 0x8000 2 0x4000 1 –0.07 0x0000 0 –0.08 30000 40000 50000 60000 65535 –2 –0.06 CODE –0.02 0 0.02 0.04 0.06 LOAD CURRENT (A) Figure 18. TUE vs. Code, AD5696 25 –0.04 10799-138 –1 10799-133 VDD = 5V –0.09 T = 25°C A REFERENCE = 2.5V –0.10 0 10000 20000 Figure 21. Source and Sink Capability at 5 V 5 VDD = 5V TA = 25°C REFERENCE = 2.5V VDD = 3V TA = 25°C 4 REFERENCE = 2.5V GAIN = 1 20 0xFFFF 3 0xC000 VOUT (V) 15 10 2 0x8000 1 0x4000 0 0x0000 5 0 540 560 580 600 IDD (mA) 620 640 –2 –0.06 –0.04 –0.02 0 0.02 0.04 LOAD CURRENT (A) Figure 22. Source and Sink Capability at 3 V Figure 19. IDD Histogram at 5 V Rev. A | Page 11 of 24 0.06 10799-139 –1 10799-135 HITS TOTAL UNADJUSTED ERROR (% of FSR) 5 10799-200 –0.8 10799-132 TOTAL UNADJUSTED ERROR (% of FSR) Data Sheet AD5696/AD5694 Data Sheet 3 1.4 VOUTA VOUTB VOUTC VOUTD 1.2 2 VOUT (V) CURRENT (mA) 1.0 GAIN = 2 0.8 FULL-SCALE 0.6 GAIN = 1 1 0.4 10 60 110 TEMPERATURE (°C) 0 –5 0 5 10 TIME (µs) Figure 23. Supply Current vs. Temperature Figure 26. Exiting Power-Down to Midscale 4.0 3.5 VDD = 5V TA = 25°C REFERENCE = 2.5V 10799-143 0 –40 10799-140 0.2 2.5008 VOUTA VOUTB VOUTC VOUTD 3.0 2.5003 VOUT (V) VOUT (V) 2.5 2.0 2.4998 1.5 CHANNEL B TA = 25°C VDD = 5.25V REFERENCE = 2.5V CODE = 0x7FFF TO 0x8000 ENERGY = 0.227206nV-sec 2.4993 40 80 160 320 TIME (µs) 2.4988 10799-141 VDD = 5V 0.5 TA = 25°C REFERENCE = 2.5V ¼ TO ¾ SCALE 0 10 20 0 8 10 12 Figure 27. Digital-to-Analog Glitch Impulse 6 0.06 VOUTA VOUTB VOUTC VOUTD VDD 0.003 VOUTB VOUTC VOUTD 5 0.03 3 0.02 2 0.01 1 0 0 VDD (V) 4 VOUT AC-COUPLED (V) 0.002 0.04 0.001 0 TA = 25°C REFERENCE = 2.5V –0.01 –5 –10 0 5 10 TIME (µs) –1 15 Figure 25. Power-On Reset to 0 V –0.002 0 5 10 15 TIME (µs) Figure 28. Analog Crosstalk, VOUTA Rev. A | Page 12 of 24 20 25 10799-145 –0.001 10799-142 VOUT (V) 6 4 TIME (µs) Figure 24. Settling Time 0.05 2 10799-144 1.0 Data Sheet AD5696/AD5694 4.0 T 0nF 0.1nF 0.22nF 4.7nF 10nF 3.9 3.8 VDD = 5V TA = 25°C REFERENCE = 2.5V VOUT (V) 3.7 1 3.6 3.5 3.4 3.3 3.2 VDD = 5V TA = 25°C REFERENCE = 2.5V 802mV BANDWIDTH (dB) –80 –100 –120 –140 FREQUENCY (Hz) 1.620 1.625 1.630 –20 –30 –40 –50 –160 10799-149 THD (dBV) –60 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 1.615 –10 –40 0 1.610 0 –20 –180 1.605 Figure 31. Settling Time vs. Capacitive Load VDD = 5V TA = 25°C REFERENCE = 2.5V 0 1.600 TIME (ms) Figure 29. 0.1 Hz to 10 Hz Output Noise Plot 20 1.595 10799-150 A CH1 VDD = 5V TA = 25°C REFERENCE = 2.5V, ±0.1V p-p –60 10k 100k 1M FREQUENCY (Hz) Figure 32. Multiplying Bandwidth Figure 30. Total Harmonic Distortion at 1 kHz Rev. A | Page 13 of 24 10M 10799-151 M1.0s 3.0 1.590 10799-146 CH1 10µV 3.1 AD5696/AD5694 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Figure 5 and Figure 6 show typical INL vs. code plots. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. The AD5696/AD5694 are guaranteed monotonic by design. Figure 7 and Figure 8 show typical DNL vs. code plots. Zero-Code Error Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5696/AD5694 because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. Figure 13 shows a plot of zero-code error vs. temperature. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD − 1 LSB. Full-scale error is expressed as a percentage of the full-scale range (% of FSR). Figure 12 shows a plot of full-scale error vs. temperature. Gain Error Gain error is a measurement of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed in % of FSR. Gain Temperature Coefficient Gain temperature coefficient is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/°C. Offset Error Offset error is a measurement of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. It can be negative or positive. Offset Error Drift Offset error drift is a measurement of the change in offset error with changes in temperature. It is expressed in µV/°C. DC Power Supply Rejection Ratio (PSRR) DC PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for midscale output of the DAC. It is measured in mV/V. VREF is held at 2.5 V, and VDD is varied by ±10%. Output Voltage Settling Time The output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 27). Digital Feedthrough Digital feedthrough is a measurement of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Noise Spectral Density (NSD) Noise spectral density is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/√Hz) and is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in μV. DC crosstalk due to load current change is a measurement of the impact that a change in load current on one DAC has on another DAC kept at midscale. It is expressed in μV/mA. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is expressed in nV-sec. Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC in response to a change in the output of another DAC. To measure analog crosstalk, load one of the input registers with a full-scale code change (all 0s to all 1s and vice versa), and then execute a software LDAC and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-sec. Rev. A | Page 14 of 24 Data Sheet AD5696/AD5694 DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC in response to a digital code change and subsequent analog output change of another DAC. It is measured by loading one channel with a full-scale code change (all 0s to all 1s and vice versa) using the write to and update commands while monitoring the output of another channel that is at midscale. The energy of the glitch is expressed in nV-sec. Total Harmonic Distortion (THD) THD is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC; THD is a measurement of the harmonics present on the DAC output. It is measured in dB. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Rev. A | Page 15 of 24 AD5696/AD5694 Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER The AD5696/AD5694 are quad, 16-/12-bit, serial input, voltage output DACs that operate from supply voltages of 2.7 V to 5.5 V. Data is written to the AD5696/AD5694 in a 24-bit word format via a 2-wire serial interface. The AD5696/AD5694 incorporate a power-on reset circuit to ensure that the DAC output powers up to a known output state. The devices also have a software powerdown mode that reduces the current consumption to 4 µA. The resistor string structure is shown in Figure 34. Each resistor in the string has a value R. The code loaded to the DAC register determines the node on the string from which the voltage is tapped off and fed into the output amplifier. The voltage is tapped off by closing one of the switches that connect the string to the amplifier. Because the AD5696/AD5694 are a string of resistors, they are guaranteed monotonic. VREF TRANSFER FUNCTION R Because the input coding to the DAC is straight binary, the ideal output voltage is given by R D VOUT = VREF × Gain N 2 R DAC ARCHITECTURE The DAC architecture consists of a string DAC followed by an output amplifier. Figure 33 shows a block diagram of the DAC architecture. DAC REGISTER R Figure 34. Resistor String Structure Output Amplifiers The output buffer amplifier can generate rail-to-rail voltages on its output for an output range of 0 V to VDD. The actual range depends on the value of VREF, the GAIN pin, the offset error, and the gain error. The GAIN pin selects the gain of the output. VREF • REF (+) • RESISTOR STRING REF (–) GND VOUTX GAIN (GAIN = 1 OR 2) Figure 33. Single DAC Channel Architecture Block Diagram 10799-052 INPUT REGISTER R 10799-053 where: VREF is the value of the external reference. Gain is the gain of the output amplifier and is set to 1 by default. The gain can be set to 1 or 2 using the gain select pin. When the GAIN pin is tied to GND, all four DAC outputs have a span of 0 V to VREF. When this pin is tied to VDD, all four DAC outputs have a span of 0 V to 2 × VREF. D is the decimal equivalent of the binary code that is loaded to the DAC register as follows: 0 to 4095 for the 12-bit AD5694, and 0 to 65,535 for the 16-bit AD5696. N is the DAC resolution (12 bits or 16 bits). TO OUTPUT AMPLIFIER When this pin is tied to GND, all four outputs have a gain of 1, and the output range is from 0 V to VREF. When this pin is tied to VDD, all four outputs have a gain of 2, and the output range is from 0 V to 2 × VREF. The output amplifiers are capable of driving a load of 1 kΩ in parallel with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale settling time of 5 µs. Rev. A | Page 16 of 24 Data Sheet AD5696/AD5694 SERIAL INTERFACE Table 8. Command Definitions The AD5696/AD5694 have a 2-wire, I2C-compatible serial interface (see the I2C-Bus Specification, Version 2.1, January 2000, available from Philips Semiconductor). See Figure 2 for a timing diagram of a typical write sequence. The AD5696/AD5694 can be connected to an I2C bus as slave devices, under the control of a master device. The AD5696/AD5694 support standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10-bit addressing or general call addressing. C3 0 0 Input Shift Register The input shift register of the AD5696/AD5694 is 24 bits wide. Data is loaded into the device, MSB first, as a 24-bit word under the control of the serial clock input, SCL. The first eight MSBs make up the command byte (see Figure 35 and Figure 36). 0 1 0 0 0 0 0 0 1 0 1 1 1 1 X1 1 0 0 1 1 X1 1 0 1 0 1 X1 1 The first four bits of the command byte are the command bits (C3, C2, C1, and C0), which control the mode of operation of the device (see Table 8). The last four bits of the command byte are the address bits (DAC D, DAC C, DAC B, and DAC A), which select the DAC that is operated on by the command (see Table 9). X = don’t care. Table 9. Address Bits and Selected DACs DAC D 0 0 0 0 0 0 0 1 1 … 1 The 8-bit command byte is followed by two data bytes, which contain the data-word. For the AD5696, the data-word comprises the 16-bit input code (see Figure 35); for the AD5694, the dataword comprises the 12-bit input code followed by four don’t care bits (see Figure 36). The data bits are transferred to the input shift register on the 24 falling edges of SCL. Commands can be executed on one DAC channel, any two or three DAC channels, or on all four DAC channels, depending on the address bits selected (see Table 9). 1 C2 C1 C0 COMMAND DAC D DAC C DAC B DAC A D15 D14 D13 DAC ADDRESS COMMAND BYTE D12 D11 DAC A 1 0 1 0 1 0 1 0 1 … 1 Selected DAC Channels1 DAC A DAC B DAC A and DAC B DAC C DAC A and DAC C DAC B and DAC C DAC A, DAC B, and DAC C DAC D DAC A and DAC D … All DACs Any combination of DAC channels can be selected using the address bits. DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 C3 Address Bits DAC C DAC B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 … … 1 1 D10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DAC DATA DAC DATA DATA HIGH BYTE DATA LOW BYTE 10799-302 • 0 Command No operation Write to Input Register n (dependent on LDAC) Update DAC Register n with contents of Input Register n Write to and update DAC Channel n Power down/power up DAC Hardware LDAC mask register Software reset (power-on reset) Reserved Reserved Figure 35. Input Shift Register Contents, AD5696 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 C3 C2 C1 COMMAND C0 DAC D DAC C DAC B DAC A D11 DAC ADDRESS COMMAND BYTE D10 D9 D8 D7 D6 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D5 D4 D3 D2 D1 D0 X X X X DAC DATA DAC DATA DATA HIGH BYTE DATA LOW BYTE Figure 36. Input Shift Register Contents, AD5694 Rev. A | Page 17 of 24 10799-300 • Command Bits C2 C1 C0 0 0 0 0 0 1 AD5696/AD5694 Data Sheet WRITE AND UPDATE COMMANDS SERIAL OPERATION For more information about the LDAC function, see the Load DAC (Hardware LDAC Pin) section. The 2-wire I2C serial bus protocol operates as follows: 1. Write to Input Register n (Dependent on LDAC) Command 0001 allows the user to write to each DAC’s dedicated input register individually. When LDAC is low, the input register is transparent (if not controlled by the LDAC mask register). 2. Update DAC Register n with Contents of Input Register n Command 0010 loads the DAC registers/outputs with the contents of the input registers selected by the address bits (see Table 9) and updates the DAC outputs directly. 3. Write to and Update DAC Channel n (Independent of LDAC) Command 0011 allows the user to write to the DAC registers and update the DAC outputs directly, independent of the state of the LDAC pin. 4. I2C SLAVE ADDRESS The AD5696/AD5694 have a 7-bit I2C slave address. The five MSBs are 00011, and the two LSBs (A1 and A0) are set by the state of the A1 and A0 address pins. The ability to make hardwired changes to A1 and A0 allows the user to incorporate up to four AD5696/AD5694 devices on one bus (see Table 10). WRITE OPERATION When writing to the AD5696/AD5694, the user must begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The AD5696/AD5694 require two bytes of data for the DAC and a command byte that controls various DAC functions. Three bytes of data must, therefore, be written to the DAC with the command byte followed by the most significant data byte and the least significant data byte, as shown in Figure 37. All these data bytes are acknowledged by the AD5696/AD5694. A stop condition follows. Table 10. Device Address Selection A1 Pin Connection GND GND VLOGIC VLOGIC A0 Pin Connection GND VLOGIC GND VLOGIC A1 Bit 0 0 1 1 A0 Bit 0 1 0 1 1 The master initiates a data transfer by establishing a start condition when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address. The slave device with the transmitted address responds by pulling SDA low during the 9th clock pulse (this is called the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its input shift register. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). Transitions on the SDA line must occur during the low period of SCL; SDA must remain stable during the high period of SCL. After all data bits are read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the 9th clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse and then high again during the 10th clock pulse to establish a stop condition. 9 1 9 SCL 0 SDA 0 0 1 1 A1 R/W A0 DB23 DB22 DB21 DB20 DB19 DB18 DB17 ACK BY AD5696/AD5694 START BY MASTER DB16 ACK BY AD5696/AD5694 FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 1 9 SCL (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 FRAME 3 MOST SIGNIFICANT DATA BYTE DB9 DB8 DB7 DB6 ACK BY AD5696/AD5694 Figure 37. I2C Write Operation Rev. A | Page 18 of 24 DB5 DB4 DB3 DB2 FRAME 4 LEAST SIGNIFICANT DATA BYTE DB1 DB0 ACK BY STOP BY AD5696/AD5694 MASTER 10799-303 SDA (CONTINUED) Data Sheet AD5696/AD5694 READ OPERATION MULTIPLE DAC READBACK SEQUENCE When reading data back from the AD5696/AD5694, the user must begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte must be followed by the command byte, which determines both the read command that is to follow and the pointer address to read from; the command byte is also acknowledged by the DAC. The user configures the channel to read back the contents of one or more DAC registers and sets the readback command to active using the command byte. When reading data back from multiple AD5696/AD5694 DACs, the user begins with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte must be followed by the command byte, which is also acknowledged by the DAC. The user selects the first channel to read back using the command byte. Following this, the master establishes a repeated start condition, and the address is resent with R/W = 1. This byte is acknowledged by the DAC, indicating that it is prepared to transmit data. The first two bytes of data are then read from DAC Input Register n (selected using the command byte), most significant byte first, as shown in Figure 38. The next two bytes read back are the contents of DAC Input Register n + 1, and the next bytes read back are the contents of DAC Input Register n + 2. Data is read from the DAC input registers in this auto-incremented fashion until a NACK followed by a stop condition follows. If the contents of DAC Input Register D are read out, the next two bytes of data that are read are the contents of DAC Input Register A. Following this, the master establishes a repeated start condition, and the address is resent with R/W = 1. This byte is acknowledged by the DAC, indicating that it is prepared to transmit data. Two bytes of data are then read from the DAC, as shown in Figure 38. A NACK condition from the master, followed by a stop condition, completes the read sequence. If more than one DAC is selected, Channel A is read back by default. 1 9 1 9 SCL 0 SDA 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 ACK BY AD5696/AD5694 START BY MASTER ACK BY AD5696/AD5694 FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 1 9 SCL 0 SDA 0 0 REPEATED START BY MASTER 1 1 A1 A0 R/W DB15 DB14 DB13 DB12 DB11 DB10 ACK BY AD5696/AD5694 FRAME 3 SLAVE ADDRESS 1 9 DB9 DB8 ACK BY MASTER FRAME 4 MOST SIGNIFICANT DATA BYTE n 1 9 SCL (CONTINUED) DB7 DB6 DB5 DB4 DB3 DB2 FRAME 5 LEAST SIGNIFICANT DATA BYTE n DB1 DB0 DB15 DB14 DB13 DB12 ACK BY MASTER Figure 38. I2C Read Operation Rev. A | Page 19 of 24 DB11 DB10 FRAME 6 MOST SIGNIFICANT DATA BYTE n + 1 DB9 DB8 NACK BY MASTER STOP BY MASTER 10799-304 SDA (CONTINUED) AD5696/AD5694 Data Sheet POWER-DOWN OPERATION Table 11. Modes of Operation PDx1 0 PDx0 0 0 1 1 1 0 1 POWER-DOWN CIRCUITRY VOUTX RESISTOR NETWORK Figure 39. Output Stage During Power-Down The bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when power-down mode is activated. However, the contents of the DAC registers are unaffected in power-down mode, and the DAC registers can be updated while the device is in power-down mode. The time required to exit power-down is typically 2.5 µs for VDD = 5 V. Any or all DACs (DAC A to DAC D) can be powered down to the selected mode by setting the corresponding bits in the input shift register. See Table 12 for the contents of the input shift register during the power-down/power-up operation. When both Bit PDx1 and Bit PDx0 (where x is the DAC selected) in the input shift register are set to 0, the parts work normally with their normal power consumption of 0.59 mA at 5 V. When Bit PDx1, Bit PDx0, or both Bit PDx1 and Bit PDx0 are set to 1, the part is in power-down mode. In power-down mode, the supply current falls to 4 μA at 5 V. LOAD DAC (HARDWARE LDAC PIN) The AD5696/AD5694 DACs have double buffered interfaces consisting of two banks of registers: input registers and DAC registers. The user can write to any combination of the input registers (see Table 9). Updates to the DAC registers are controlled by the LDAC pin. OUTPUT AMPLIFIER In power-down mode, the output stage is internally switched from the output of the amplifier to a resistor network of known values. In this way, the output impedance of the part is known when the part is in power-down mode. Table 11 lists the three power-down options. The output is connected internally to GND through either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited (three-state). The output stage is illustrated in Figure 39. VREF 12-/16-BIT DAC LDAC DAC REGISTER VOUTX INPUT REGISTER SCL SDA INPUT SHIFT REGISTER 10799-059 Operating Mode Normal Operation Power-Down Modes 1 kΩ to GND 100 kΩ to GND Three-State AMPLIFIER DAC 10799-058 Command 0100 is designated for the power-down function. The AD5696/AD5694 provide three separate power-down modes (see Table 11). These power-down modes are software programmable by setting Bit DB7 to Bit DB0 in the input shift register (see Table 12). Two bits are associated with each DAC channel. Table 11 shows how the state of these two bits corresponds to the mode of operation of the device. Figure 40. Simplified Diagram of Input Loading Circuitry for a Single DAC Table 12. 24-Bit Input Shift Register Contents for Power-Down/Power-Up Operation 1 DB23 (MSB) DB22 DB21 DB20 0 1 0 0 Command bits (C3 to C0) 1 DB19 to DB16 X Address bits (don’t care) DB15 to DB8 X Don’t care DB7 DB6 PDD1 PDD0 Power-down select, DAC D X = don’t care. Rev. A | Page 20 of 24 DB5 DB4 PDC1 PDC0 Power-down select, DAC C DB3 DB2 PDB1 PDB0 Power-down select, DAC B DB0 DB1 (LSB) PDA1 PDA0 Power-down select, DAC A Data Sheet AD5696/AD5694 Table 13. LDAC Overwrite Definition Instantaneous DAC Updating (LDAC Held Low) Load LDAC Register For instantaneous updating of the DACs, LDAC is held low while data is clocked into the input register using Command 0001. Both the addressed input register and the DAC register are updated on the 24th clock, and the output begins to change (see Table 14). LDAC Bit (DB3 to DB0) 0 1 Deferred DAC Updating (LDAC Pulsed Low) For deferred updating of the DACs, LDAC is held high while data is clocked into the input register using Command 0001. All DAC outputs are asynchronously updated by pulling LDAC low after the 24th clock. The update occurs on the falling edge of LDAC. 1 LDAC Pin LDAC Operation 1 or 0 X1 Determined by the LDAC pin. DAC channels are updated. (DAC channels see LDAC pin as 1.) X = don’t care. HARDWARE RESET PIN (RESET) RESET is an active low reset that allows the outputs to be cleared to either zero scale or midscale. The clear code value is user selectable via the reset select pin (RSTSEL). It is necessary to keep RESET low for a minimum of 30 ns to complete the operation. LDAC MASK REGISTER Command 0101 is reserved for the software LDAC function. When this command is executed, the address bits are ignored. When writing to the DAC using Command 0101, the 4-bit LDAC mask register (DB3 to DB0) is loaded. Bit DB3 of the LDAC mask register corresponds to DAC D; Bit DB2 corresponds to DAC C; Bit DB1 corresponds to DAC B; and Bit DB0 corresponds to DAC A. When the RESET signal is returned high, the output remains at the cleared value until a new value is programmed. The outputs cannot be updated with a new value while the RESET pin is low. There is also a software executable reset function that resets the DAC to the power-on reset code. Command 0110 is designated for this software reset function (see Table 8). Any events on LDAC or RESET during power-on reset are ignored. The default value of these bits is 0; that is, the LDAC pin works normally. Setting any of these bits to 1 forces the selected DAC channel to ignore transitions on the LDAC pin, regardless of the state of the hardware LDAC pin. This flexibility is useful in applications where the user wishes to select which channels respond to the LDAC pin. RESET SELECT PIN (RSTSEL) The AD5696/AD5694 contain a power-on reset circuit that controls the output voltage during power-up. When the RSTSEL pin is tied to GND, the outputs power up to zero scale (note that this is outside the linear region of the DAC). When the RSTSEL pin is tied to VDD, the outputs power up to midscale. The outputs remain powered up at the level set by the RSTSEL pin until a valid write sequence is made to the DAC. The LDAC mask register allows the user extra flexibility and control over the hardware LDAC pin (see Table 13). Setting the LDAC bit (DB3 to DB0) to 0 for a DAC channel allows the hard-ware LDAC pin to control the updating of that channel. Table 14. Write Commands and LDAC Pin Truth Table 1 Command 0001 Description Write to Input Register n (dependent on LDAC) 0010 Update DAC Register n with contents of Input Register n 0011 Write to and update DAC Channel n Hardware LDAC Pin State VLOGIC GND 2 VLOGIC Input Register Contents Data update Data update No change GND No change VLOGIC GND Data update Data update DAC Register Contents No change (no update) Data update Updated with input register contents Updated with input register contents Data update Data update A high to low transition on the hardware LDAC pin always updates the contents of the DAC register with the contents of the input register on channels that are not masked (blocked) by the LDAC mask register. 2 When the LDAC pin is permanently tied low, the LDAC mask bits are ignored. 1 Rev. A | Page 21 of 24 AD5696/AD5694 Data Sheet APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5696/AD5694 is via a serial bus that uses a standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 2-wire interface consisting of a clock signal and a data signal. AD5696/AD5694 TO ADSP-BF531 INTERFACE For enhanced thermal, electrical, and board level performance, solder the exposed pad on the bottom of the LFCSP package to the corresponding thermal land paddle on the PCB. Design thermal vias into the PCB land paddle area to further improve heat dissipation. The GND plane on the device can be increased (as shown in Figure 42) to provide a natural heat sinking effect. AD5696/ AD5694 The I2C interface of the AD5696/AD5694 is designed for easy connection to industry-standard DSPs and microcontrollers. Figure 41 shows the AD5696/AD5694 connected to the Analog Devices, Inc., Blackfin® processor. The Blackfin processor has an integrated I2C port that can be connected directly to the I2C pins of the AD5696/AD5694. GND PLANE 10799-166 AD5696/ AD5694 BOARD ADSP-BF531 LDAC RESET GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. Figure 41. AD5696/AD5694 to ADSP-BF531 Interface LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The PCB on which the AD5696/AD5694 are mounted should be designed so that the AD5696/AD5694 lie on the analog plane. The AD5696/AD5694 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply, located as close to the package as possible, ideally right up against the device. The 10 µF capacitor is the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types; these capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. In systems where many devices are on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. The Analog Devices iCoupler® products provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5696/AD5694 makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 43 shows a 4-channel isolated interface to the AD5696/ AD5694 using the ADuM1400. For more information, visit http://www.analog.com/icouplers. CONTROLLER SERIAL CLOCK IN SERIAL DATA OUT ADuM1400 VOA VIA ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE VIB VOB VIC RESET OUT LOAD DAC OUT The AD5696/AD5694 LFCSP models have an exposed pad beneath the device. Connect this pad to the GND supply for the part. For optimum performance, use special considerations to design the motherboard and to mount the package. Rev. A | Page 22 of 24 VOC VOD VID Figure 43. Isolated Interface TO SCL TO SDA TO RESET TO LDAC 10799-167 PF9 PF8 Figure 42. Paddle Connection to Board SCL SDA 10799-164 GPIO1 GPIO2 Data Sheet AD5696/AD5694 OUTLINE DIMENSIONS 3.10 3.00 SQ 2.90 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.75 1.60 SQ 1.45 9 TOP VIEW 0.80 0.75 0.70 4 5 8 0.50 0.40 0.30 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW 08-16-2010-E PIN 1 INDICATOR 0.30 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 44. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 45. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. A | Page 23 of 24 0.75 0.60 0.45 AD5696/AD5694 Data Sheet ORDERING GUIDE Model 1 AD5696ACPZ-RL7 AD5696BCPZ-RL7 AD5696ARUZ AD5696ARUZ-RL7 AD5696BRUZ AD5696BRUZ-RL7 AD5694BCPZ-RL7 AD5694ARUZ AD5694ARUZ-RL7 AD5694BRUZ AD5694BRUZ-RL7 EVAL-AD5696RSDZ EVAL-AD5694RSDZ 1 Resolution 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 12 Bits 12 Bits 12 Bits 12 Bits 12 Bits Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Accuracy (INL) ±8 LSB ±2 LSB ±8 LSB ±8 LSB ±2 LSB ±2 LSB ±1 LSB ±2 LSB ±2 LSB ±1 LSB ±1 LSB Package Description 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead LFCSP_WQ 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP AD5696 TSSOP Evaluation Board AD5694 TSSOP Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10799-0-6/13(A) Rev. A | Page 24 of 24 Package Option CP-16-22 CP-16-22 RU-16 RU-16 RU-16 RU-16 CP-16-22 RU-16 RU-16 RU-16 RU-16 Branding DJ8 DJ9 DJQ
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No ADI Prelim : Data Sheet ADI Pub Year : 2012–2013 ADI Pubcode : D10799-0-6/13(A) ADI Rev : A ADI Template : 3.5 ADI Title : AD5696/AD5694 Author : Analog Devices, Inc. Category : Datasheet Create Date : 2013:06:25 15:17:05-04:00 Keywords : "D/A conversion, D/A converter(s), data converter(s), DAC, , DAC circuit, nanoDAC, nanoDAC+" Modify Date : 2013:06:25 17:11:24-04:00 Source Modified : D:20130625191642 Tagged PDF : Yes XMP Toolkit : Adobe XMP Core 5.2-c001 63.139439, 2010/09/27-13:37:26 Metadata Date : 2013:06:25 17:11:24-04:00 Creator Tool : Acrobat PDFMaker 10.1 for Word Document ID : uuid:76a04a12-d290-494a-b538-286193c0b3d9 Instance ID : uuid:8ee418bb-d90c-48c6-b2ba-47bdf6f048f8 Format : application/pdf Title : AD5696/AD5694 (Rev. A) Description : Quad, 16-/12-Bit nanoDAC+ with I2C Interface Creator : Analog Devices, Inc. Subject : D/A conversion, D/A converter(s), data converter(s), DAC, , DAC circuit, nanoDAC, nanoDAC+ Producer : Adobe PDF Library 10.0 ADI0020 Rev : A ADI0020 Title : AD5696/AD5694 ADI0020 Prelim : Data Sheet ADI0020 Pubcode : D10799-0-6/13(A) ADI0020 Pub 0020 Year : 2012–2013 ADI0020 Template : 3.5 Headline : Quad, 16-/12-Bit nanoDAC+ with I2C Interface Page Layout : SinglePage Page Mode : UseOutlines Page Count : 24EXIF Metadata provided by EXIF.tools