AD5696/AD5694 (Rev. A) AD5696 5694

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Quad, 16-/12-Bit nanoDAC+

with I

2

C Interface

Data Sheet

AD5696/AD5694

Rev. A Document Feedback

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Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.

Technical Support www.analog.com

FEATURES

High relative accuracy (INL): ±2 LSB maximum at 16 bits

Tiny package: 3 mm × 3 mm, 16-lead LFCSP

Total unadjusted error (TUE): ±0.1% of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.1% of FSR maximum

High drive capability: 20 mA, 0.5 V from supply rails

User-selectable gain of 1 or 2 (GAIN pin)

Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility

400 kHz I2C-compatible serial interface

4 I2C addresses available

Low glitch: 0.5 nV-sec

Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating

Low power: 1.8 mW at 3 V

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

APPLICATIONS

Digital gain and offset adjustment

Programmable attenuators

Process control (PLC I/O cards)

Industrial automation

Data acquisition systems

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD5696 and AD5694, members of the nanoDAC+™ family,

are low power, quad, 16-/12-bit buffered voltage output DACs.

The devices include a gain select pin giving a full-scale output

of 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from

a single 2.7 V to 5.5 V supply, are guaranteed monotonic by

design, and exhibit less than 0.1% FSR gain error and 1.5 mV

offset error performance. The devices are available in a 3 mm ×

3 mm LFCSP package and in a TSSOP package.

The AD5696/AD5694 incorporate a power-on reset circuit and a

RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power

up to zero scale or midscale and remain at that level until a valid

write takes place. The parts contain a per-channel power-down

feature that reduces the current consumption of the device in

power-down mode to 4 µA at 3 V.

The AD5696/AD5694 use a versatile 2-wire serial interface that

operates at clock rates up to 400 kHz and include a VLOGIC pin

intended for 1.8 V/3 V/5 V logic.

Table 1. Quad nanoDAC+ Devices

Interface Reference 16-Bit 14-Bit 12-Bit

SPI Internal AD5686R AD5685R AD5684R

External AD5686 AD5684

I2C Internal AD5696R AD5695R AD5694R

External AD5696 AD5694

PRODUCT HIGHLIGHTS

1. High Relative Accuracy (INL).

AD5696 (16-bit): ±2 LSB maximum

AD5694 (12-bit): ±1 LSB maximum

2. Excellent DC Performance.

Total unadjusted error: ±0.1% of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.1% of FSR maximum

3. Two Package Options.

3 mm × 3 mm, 16-lead LFCSP

16-lead TSSOP

SCL

V

LOGIC

SDA

A1

A0

INPUT

REGISTER DAC

REGISTER STRING

DAC A

BUFFER

V

OUT

A

INPUT

REGISTER DAC

REGISTER STRING

DAC B

BUFFER

V

OUT

B

INPUT

REGISTER DAC

REGISTER STRING

DAC C

BUFFER

V

OUT

C

INPUT

REGISTER DAC

REGISTER STRING

DAC D

BUFFER

V

OUT

D

V

REF

GNDV

DD

POWER-

DOWN

LOGIC

POWER-ON

RESET GAIN =

×1/×2

INTERFACE LOGIC

RSTSEL GAIN

LDAC RESET

AD5696/AD5694

10799-001

AD5696/AD5694 Data Sheet

Rev. A | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Characteristics ........................................................................ 5

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 16

Digital-to-Analog Converter .................................................... 16

Transfer Function ....................................................................... 16

DAC Architecture ....................................................................... 16

Serial Interface ............................................................................ 17

Write and Update Commands .................................................. 18

I2C Slave Address ........................................................................ 18

Serial Operation ......................................................................... 18

Write Operation.......................................................................... 18

Read Operation........................................................................... 19

Multiple DAC Readback Sequence .......................................... 19

Power-Down Operation ............................................................ 20

Load DAC (Hardware LDAC Pin) ........................................... 20

LDAC Mask Register ................................................................. 21

Hardware Reset Pin (RESET) ................................................... 21

Reset Select Pin (RSTSEL) ........................................................ 21

Applications Information .............................................................. 22

Microprocessor Interfacing ....................................................... 22

AD5696/AD5694 to ADSP-BF531 Interface .......................... 22

Layout Guidelines....................................................................... 22

Galvanically Isolated Interface ................................................. 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 24

REVISION HISTORY

6/13—Rev. 0 to Rev. A

Changes to Pin GAIN and Pin RSTSEL Descriptions; Table 7 ....... 8

7/12—Revision 0: Initial Version

Data Sheet AD5696/AD5694

Rev. A | Page 3 of 24

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.

Table 2.

A Grade

B Grade

Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments1

STATIC PERFORMANCE2

AD5696

Resolution 16 16 Bits

Relative Accuracy ±2 ±8 ±1 ±2 LSB Gain = 2

±2 ±8 ±1 ±3 LSB Gain = 1

Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by

design

AD5694

Resolution 12 12 Bits

Relative Accuracy ±0.12 ±2 ±0.12 ±1 LSB

Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by

design

Zero-Code Error 0.4 4 0.4 1.5 mV All 0s loaded to DAC register

Offset Error +0.1 ±4 +0.1 ±1.5 mV

Full-Scale Error +0.01 ±0.2 +0.01 ±0.1 % of FSR All 1s loaded to DAC register

Gain Error ±0.02 ±0.2 ±0.02 ±0.1 % of FSR

Total Unadjusted Error

±0.01

±0.25

±0.01

±0.1

% of FSR

Gain = 2

±0.25 ±0.2 % of FSR Gain = 1

Offset Error Drift3 ±1 ±1 µV/°C

Gain Temperature

Coefficient3

±1 ±1 ppm Of FSR/°C

DC Power Supply Rejection

Ratio3

0.15 0.15 mV/V DAC code = midscale; VDD =

5 V ± 10%

DC Crosstalk3 ±2 ±2 µV Due to single channel, full-

scale output change

±3

±3

µV/mA

Due to load current change

±2 ±2 µV Due to power-down (per

channel)

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VREF 0 VREF V Gain = 1

0 2 × VREF 0 2 × VREF V Gain = 2 (see Figure 20)

Capacitive Load Stability 2 2 nF RL = ∞

10 10 nF RL = 1 kΩ

Resistive Load4 1 1 kΩ

Load Regulation DAC code = midscale

80 80 µV/mA 5 V ± 10%; −30 mA ≤ IOUT ≤

+30 mA

80 80 µV/mA 3 V ± 10%; −20 mA ≤ IOUT ≤

+20 mA

Short-Circuit Current

5

40

40

mA

Load Impedance at Rails6 25 25 Ω See Figure 20

Power-Up Time 2.5 2.5 µs Coming out of power-down

mode; VDD = 5 V

REFERENCE INPUT

Reference Current 90 90 µA VREF = VDD = 5.5 V, gain = 1

180 180 µA VREF = VDD = 5.5 V, gain = 2

Reference Input Range 1 VDD 1 VDD V Gain = 1

1 VDD/2 1 VDD/2 V Gain = 2

Reference Input Impedance

16

16

kΩ

Gain = 2

32 32 kΩ Gain = 1

AD5696/AD5694 Data Sheet

Rev. A | Page 4 of 24

A Grade B Grade

Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments1

LOGIC INPUTS3

Input Current ±2 ±2 µA Per pin

Input Low Voltage, VINL 0.3 × VLOGIC 0.3 × VLOGIC V

Input High Voltage, VINH 0.7 × VLOGIC 0.7 × VLOGIC V

Pin Capacitance 2 2 pF

LOGIC OUTPUTS (SDA)3

Output Low Voltage, VOL 0.4 0.4 V ISINK = 3 mA

Output High Voltage, VOH VLOGIC − 0.4 VLOGIC − 0.4 V ISOURCE = 3 mA

Floating State Output

Capacitance

4 4 pF

POWER REQUIREMENTS

VLOGIC 1.8 5.5 1.8 5.5 V

ILOGIC 3 3 µA

VDD 2.7 5.5 2.7 5.5 V Gain = 1

VREF + 1.5 5.5 VREF + 1.5 5.5 V Gain = 2

IDD VIH = VDD, VIL = GND, VDD =

2.7 V to 5.5 V

Normal Mode7 0.59 0.7 0.59 0.7 mA

All Power-Down Modes8 1 4 1 4 µA −40°C to +85°C

6 6 µA −40°C to +105°C

1 Temperature range is −40°C to +105°C.

2 DC specifications are tested with the outputs unloaded, unless otherwise noted. Upper dead band (10 mV) exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD

with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5696) or 12 to 4080 (AD5694).

3 Guaranteed by design and characterization; not production tested.

4 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to 30 mA

up to a junction temperature of 110°C.

5 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded

during current limit. Operation above the specified maximum junction temperature may impair device reliability.

6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices.

For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 20).

7 Interface inactive. All DACs active. DAC outputs unloaded.

8 All DACs powered down.

Data Sheet AD5696/AD5694

Rev. A | Page 5 of 24

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter1, 2 Min Typ Max Unit Test Conditions/Comments3

Output Voltage Settling Time ¼ to ¾ scale settling to ±2 LSB

AD5696 5 8 µs

AD5694 5 7 µs

Slew Rate 0.8 V/µs

Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry transition

Digital Feedthrough 0.13 nV-sec

Multiplying Bandwidth 500 kHz

Digital Crosstalk 0.1 nV-sec

Analog Crosstalk 0.2 nV-sec

DAC-to-DAC Crosstalk 0.3 nV-sec

Total Harmonic Distortion4 −80 dB At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz

Output Noise Spectral Density 100 nV/√Hz DAC code = midscale, 10 kHz, gain = 2

Output Noise 6 µV p-p 0.1 Hz to 10 Hz

Signal-to-Noise Ratio (SNR) 90 dB At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz

Spurious-Free Dynamic Range (SFDR) 83 dB At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz

Signal-to-Noise-and-Distortion Ratio

(SINAD)

80 dB At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz

1 Guaranteed by design and characterization; not production tested.

2 See the Terminology section.

3 Temperature range is −40°C to +105°C; typical at 25°C.

4 Digitally generated sine wave at 1 kHz.

AD5696/AD5694 Data Sheet

Rev. A | Page 6 of 24

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 4.

Parameter1, 2 Min Max Unit Description

t1 2.5 μs SCL cycle time

t2 0.6 μs tHIGH, SCL high time

t3 1.3 μs tLOW, SCL low time

t4 0.6 μs tHD,STA, start/repeated start hold time

t5 100 ns tSU,DAT, data setup time

t63 0 0.9 μs tHD,DAT, data hold time

t7 0.6 μs tSU,STA, repeated start setup time

t8 0.6 μs tSU,STO, stop condition setup time

t9 1.3 μs tBUF, bus free time between a stop condition and a start condition

t104 0 300 ns tR, rise time of SCL and SDA when receiving

t114, 5 20 + 0.1CB 300 ns tF, fall time of SCL and SDA when transmitting/receiving

t12 20 ns

LDAC pulse width

t13 400 ns

SCL rising edge to LDAC rising edge

tSP6 0 50 ns Pulse width of suppressed spike

CB5 400 pF Capacitive load for each bus line

1 See Figure 2.

2 Guaranteed by design and characterization; not production tested.

3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the SCL

falling edge.

4 tR and tF are measured from 0.3 × VDD to 0.7 × VDD.

5 CB is the total capacitance of one bus line in pF.

6 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.

Timing Diagram

Figure 2. 2-Wire Serial Interface Timing Diagram

SCL

SDA

t

1

t

3

LDAC

1

LDAC

2

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

NOTES

1

ASYNCHRONOUS LDAC UPDATE MODE.

2

SYNCHRONOUS LDAC UPDATE MODE.

t

4

t

6

t

5

t

7

t

8

t

2

t

13

t

4

t

11

t

10

t

12

t

12

t

9

10799-002

Data Sheet AD5696/AD5694

Rev. A | Page 7 of 24

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V

VLOGIC to GND −0.3 V to +7 V

VOUT to GND −0.3 V to VDD + 0.3 V

VREF to GND −0.3 V to VDD + 0.3 V

Digital Input Voltage to GND1 −0.3 V to VLOGIC + 0.3 V

SDA and SCL to GND −0.3 V to +7 V

Operating Temperature Range

−40°C to +105°C

Storage Temperature Range −65°C to +150°C

Junction Temperature 125°C

Reflow Soldering Peak Temperature,

Pb Free (J-STD-020)

260°C

ESD

Human Body Model (HBM) 3.5 kV

Field-Induced Charged Device

Model (FICDM)

1.5 kV

1 Excluding SDA and SCL.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages. This

value was measured using a JEDEC standard 4-layer board with

zero airflow. For the LFCSP package, the exposed pad must be

tied to GND.

Table 6. Thermal Resistance

Package Type θJA Unit

16-Lead LFCSP 70 °C/W

16-Lead TSSOP 112.6 °C/W

ESD CAUTION

AD5696/AD5694 Data Sheet

Rev. A | Page 8 of 24

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration, 16-Lead LFCSP

Figure 4. Pin Configuration, 16-Lead TSSOP

Table 7. Pin Function Descriptions

Pin No.

Mnemonic Description

LFCSP TSSOP

1 3 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

2 4 GND Ground Reference Point for All Circuitry on the Part.

3 5 VDD Power Supply Input. The parts can be operated from 2.7 V to 5.5 V. The supply should be decoupled

with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

4 6 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

5 7 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

6 8 SDA Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the

24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the

supply with an external pull-up resistor.

7 9 LDAC LDAC can be operated in two modes, asynchronous update mode and synchronous update mode.

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new

data; all DAC outputs are simultaneously updated. This pin can also be tied permanently low.

8 10 GAIN Gain Select Pin. When this pin is tied to GND, all four DAC outputs have a span of 0 V to VREF.

When this pin is tied to VLOGIC, all four DAC outputs have a span of 0 V to 2 × VREF.

9 11 VLOGIC Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.

10 12 A0 Address Input. Sets the first LSB of the 7-bit slave address.

11 13 SCL Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the

24-bit input shift register.

12 14 A1 Address Input. Sets the second LSB of the 7-bit slave address.

13 15 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is activated

(low)

, the input register and the DAC register are updated with zero scale or midscale, depending

on the state of the RSTSEL pin. When RESET is low, all LDAC pulses are ignored.

14 16 RSTSEL Power-On Reset Pin. When this pin is tied to GND, all four DACs are powered up to zero scale.

When this pin is tied to VLOGIC, all four DACs are powered up to midscale.

15 1 VREF Reference Input Voltage.

16 2 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND.

12

11

10

1

3

4

A1

SCL

A0

9V

LOGIC

V

OUT

A

V

DD

2

GND

V

OUT

C

6

SDA

5

V

OUT

D

7

LDAC

8

GAIN

16 V

OUT

B

15 V

REF

14 RSTSEL

13 RESET

AD5696/AD5694

NOTES

1. THE EXPOSED PAD MUST BE TIED TO GND.

TOP VIEW

(Not to Scale)

10799-006

1

2

3

4

5

6

7

8

V

OUT

B

V

OUT

A

GND

V

OUT

D

V

OUT

C

V

DD

V

REF

SDA

16

15

14

13

12

11

10

9

RESET

A1

SCL

GAIN

LDAC

V

LOGIC

A0

RSTSEL

TOP VIEW

(Not to Scale)

AD5696/

AD5694

10799-007

Data Sheet AD5696/AD5694

Rev. A | Page 9 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. AD5696 INL

Figure 6. AD5694 INL

Figure 7. AD5696 DNL

Figure 8. AD5694 DNL

Figure 9. INL Error and DNL Error vs. Temperature

Figure 10. INL Error and DNL Error vs. VREF

10

–10

–8

–6

–4

–2

0

2

4

8

6

010000 20000 30000 40000 50000 60000

INL (LSB)

CODE

VDD = 5V

TA = 25°C

REFERENCE = 2.5V

10799-118

10

–10

–8

–6

–4

–2

0

2

4

8

6

0625 1250 1875 2500 3125 3750 4096

INL (LSB)

CODE

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V

10799-120

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.8

0.6

010000 20000 30000 40000 50000 60000

DNL (LSB)

CODE

VDD = 5V

TA = 25°C

REFERENCE = 2.5V

10799-121

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.8

0.6

0625 1250 1875 2500 3125 3750 4096

DNL (LSB)

CODE

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V

10799-123

10

–10

–8

–6

–4

–2

0

2

4

6

8

–40 1106010

ERROR (LSB)

TEMPERATURE (°C)

INL

DNL

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V

10799-124

10

–10

–8

–6

–4

–2

0

2

4

6

8

05.04.54.03.53.02.52.01.51.00.5

ERROR (LSB)

VREF (V)

INL

DNL

VDD = 5V

TA = 25°C

10799-125

AD5696/AD5694 Data Sheet

Rev. A | Page 10 of 24

Figure 11. INL Error and DNL Error vs. Supply Voltage

Figure 12. Gain Error and Full-Scale Error vs. Temperature

Figure 13. Zero-Code Error and Offset Error vs. Temperature

Figure 14. Gain Error and Full-Scale Error vs. Supply Voltage

Figure 15. Zero-Code Error and Offset Error vs. Supply Voltage

Figure 16. TUE vs. Temperature

10

–10

–8

–6

–4

–2

0

2

4

6

8

2.7 5.2

4.74.23.73.2

ERROR (LSB)

SUPPLY VOLTAGE (V)

INL

DNL

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V

10799-126

0.10

–0.10

–0.08

–0.06

–0.04

–0.02

0

0.02

0.04

0.06

0.08

–40 –20 020 40 60 80 100 120

ERROR (% of FSR)

TEMPERATURE (°C)

GAIN ERROR

FULL-SCALE ERROR

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V

10799-127

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–40 –20 020 40 60 80 100 120

ERROR (mV)

TEMPERATURE (°C)

OFFSET ERROR

ZERO-CODE ERROR

VDD = 5V

TA = 25°C

REFERENCE = 2.5V

10799-128

0.10

–0.10

–0.08

–0.06

–0.04

–0.02

0

0.02

0.04

0.06

0.08

2.7 5.24.74.23.73.2

ERROR (% of FSR)

SUPPLY VOLTAGE (V)

GAIN ERROR

FULL-SCALE ERROR

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V

10799-129

1.5

–1.5

–1.0

–0.5

0

0.5

1.0

2.7 5.24.74.23.73.2

ERROR (mV)

SUPPLY VOLTAGE (V)

ZERO-CODE ERROR

OFFSET ERROR

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V

10799-130

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

–40 –20 020 40 60 80 100 120

TOTAL UNADJUSTED ERROR (% of FSR)

TEMPERATURE (°C)

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V

10799-131

Data Sheet AD5696/AD5694

Rev. A | Page 11 of 24

Figure 17. TUE vs. Supply Voltage, Gain = 1

Figure 18. TUE vs. Code, AD5696

Figure 19. IDD Histogram at 5 V

Figure 20. Headroom/Footroom vs. Load Current

Figure 21. Source and Sink Capability at 5 V

Figure 22. Source and Sink Capability at 3 V

0.10

0.08

0.06

0.04

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

2.7 5.2

4.74.2

3.7

3.2

TOTAL UNADJUSTED ERROR (% of FSR)

SUPPLY VOLTAGE (V)

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V

10799-132

0

–0.01

–0.02

–0.03

–0.04

–0.05

–0.06

–0.07

–0.08

–0.09

–0.10 010000 20000 30000 40000 50000 60000 65535

TOTAL UNADJUSTED ERROR (% of FSR)

CODE

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V

10799-133

25

20

15

10

5

0540 560 580 600 620 640

HITS

IDD (mA)

VDD = 5V

TA = 25°C

REFERENCE = 2.5V

10799-135

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

0 5 10 15 20 25 30

ΔVOUT (V)

LOAD CURRENT (mA)

SOURCING, 2.7V

SOURCING, 5V

SINKING, 2.7V

SINKING, 5V

10799-200

7

–2

–1

0

1

2

3

4

5

6

–0.06 –0.04 –0.02 0

0.02 0.04 0.06

V

OUT

(V)

LOAD CURRENT (A)

0xFFFF

0x4000

0x8000

0xC000

0x0000

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V

GAIN = 2

10799-138

5

–2

–1

0

1

2

3

4

–0.06 –0.04 –0.02 00.02 0.04 0.06

V

OUT

(V)

LOAD CURRENT (A)

0xFFFF

0x4000

0x8000

0xC000

0x0000

V

DD

= 3V

T

A

= 25°C

REFERENCE = 2.5V

GAIN = 1

10799-139

AD5696/AD5694 Data Sheet

Rev. A | Page 12 of 24

Figure 23. Supply Current vs. Temperature

Figure 24. Settling Time

Figure 25. Power-On Reset to 0 V

Figure 26. Exiting Power-Down to Midscale

Figure 27. Digital-to-Analog Glitch Impulse

Figure 28. Analog Crosstalk, VOUTA

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

–40 110

6010

CURRENT (mA)

TEMPERATURE (°C)

FULL-SCALE

10799-140

0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

10 32016040 8020

VOUT (V)

TIME (µs)

VOUTA

VOUTB

VOUTC

VOUTD

VDD = 5V

TA = 25°C

REFERENCE = 2.5V

¼ TO ¾ SCALE

10799-141

–0.01

0

0.06

0.01

0.02

0.03

0.04

0.05

–1

0

6

1

2

3

4

5

–10 15100 5–5

VOUT (V)

VDD (V)

TIME (µs)

VOUTD

VDD

VOUTA

VOUTB

VOUTC

TA = 25°C

REFERENCE = 2.5V

10799-142

0

1

3

2

–5 100 5

V

OUT

(V)

TIME (µs)

V

OUT

D

V

OUT

A

V

OUT

B

V

OUT

C

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V

GAIN = 1

GAIN = 2

10799-143

2.4988

2.5008

2.5003

2.4998

2.4993

012810462

VOUT (V)

TIME (µs)

CHANNEL B

TA = 25°C

VDD = 5.25V

REFERENCE = 2.5V

CODE = 0x7FFF TO 0x8000

ENERGY = 0.227206nV-sec

10799-144

–0.002

–0.001

0

0.001

0.002

0.003

0252010 155

V

OUT

AC-COUPLED (V)

TIME (µs)

V

OUT

B

V

OUT

C

V

OUT

D

10799-145

Data Sheet AD5696/AD5694

Rev. A | Page 13 of 24

Figure 29. 0.1 Hz to 10 Hz Output Noise Plot

Figure 30. Total Harmonic Distortion at 1 kHz

Figure 31. Settling Time vs. Capacitive Load

Figure 32. Multiplying Bandwidth

CH1 10µV M1.0s A CH1 802mV

1

T

VDD = 5V

TA = 25°C

REFERENCE = 2.5V

10799-146

–180

–160

–140

–120

–100

–80

–60

–40

–20

0

20

020000160008000 1200040002000 1800010000 140006000

THD (dBV)

FREQUENCY (Hz)

VDD = 5V

TA = 25°C

REFERENCE = 2.5V

10799-149

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.0

1.590 1.6301.6201.600 1.610 1.6251.605 1.6151.595

V

OUT

(V)

TIME (ms)

0nF

0.1nF

10nF

0.22nF

4.7nF

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V

10799-150

–60

–50

–40

–30

–20

–10

0

10k 10M1M100k

BANDWIDTH (dB)

FREQUENCY (Hz)

V

DD

= 5V

T

A

= 25°C

REFERENCE = 2.5V, ±0.1V p-p

10799-151

AD5696/AD5694 Data Sheet

Rev. A | Page 14 of 24

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

Relative accuracy or integral nonlinearity is a measurement of

the maximum deviation, in LSBs, from a straight line passing

through the endpoints of the DAC transfer function. Figure 5

and Figure 6 show typical INL vs. code plots.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent codes.

A specified differential nonlinearity of ±1 LSB maximum ensures

monotonicity. The AD5696/AD5694 are guaranteed monotonic

by design. Figure 7 and Figure 8 show typical DNL vs. code plots.

Zero-Code Error

Zero-code error is a measurement of the output error when

zero code (0x0000) is loaded to the DAC register. Ideally, the

output should be 0 V. The zero-code error is always positive in

the AD5696/AD5694 because the output of the DAC cannot go

below 0 V due to a combination of the offset errors in the DAC

and the output amplifier. Zero-code error is expressed in mV.

Figure 13 shows a plot of zero-code error vs. temperature.

Full-Scale Error

Full-scale error is a measurement of the output error when full-

scale code (0xFFFF) is loaded to the DAC register. Ideally, the

output should be VDD − 1 LSB. Full-scale error is expressed as a

percentage of the full-scale range (% of FSR). Figure 12 shows a

plot of full-scale error vs. temperature.

Gain Error

Gain error is a measurement of the span error of the DAC. It is

the deviation in slope of the DAC transfer characteristic from

the ideal expressed in % of FSR.

Gain Temperature Coefficient

Gain temperature coefficient is a measurement of the change in

gain error with changes in temperature. It is expressed in ppm

of FSR/°C.

Offset Error

Offset error is a measurement of the difference between VOUT

(actual) and VOUT (ideal) expressed in mV in the linear region

of the transfer function. It can be negative or positive.

Offset Error Drift

Offset error drift is a measurement of the change in offset error

with changes in temperature. It is expressed in µV/°C.

DC Power Supply Rejection Ratio (PSRR)

DC PSRR indicates how the output of the DAC is affected by

changes in the supply voltage. PSRR is the ratio of the change in

VOUT to a change in VDD for midscale output of the DAC. It is mea-

sured in mV/V. VREF is held at 2.5 V, and VDD is varied by ±10%.

Output Voltage Settling Time

The output voltage settling time is the amount of time it takes

for the output of a DAC to settle to a specified level for a ¼ to ¾

full-scale input change.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV-sec

and is measured when the digital input code is changed by 1 LSB

at the major carry transition (0x7FFF to 0x8000) (see Figure 27).

Digital Feedthrough

Digital feedthrough is a measurement of the impulse injected into

the analog output of the DAC from the digital inputs of the DAC,

but is measured when the DAC output is not updated. It is

specified in nV-sec and measured with a full-scale code change

on the data bus, that is, from all 0s to all 1s and vice versa.

Noise Spectral Density (NSD)

Noise spectral density is a measurement of the internally gener-

ated random noise. Random noise is characterized as a spectral

density (nV/√Hz) and is measured by loading the DAC to mid-

scale and measuring noise at the output. It is measured in nV/√Hz.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC

in response to a change in the output of another DAC. It is

measured with a full-scale output change on one DAC (or soft

power-down and power-up) while monitoring another DAC

kept at midscale. It is expressed in μV.

DC crosstalk due to load current change is a measurement

of the impact that a change in load current on one DAC has

on another DAC kept at midscale. It is expressed in μV/mA.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output of

one DAC at midscale in response to a full-scale code change (all

0s to all 1s and vice versa) in the input register of another DAC.

It is expressed in nV-sec.

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output

of one DAC in response to a change in the output of another DAC.

To measure analog crosstalk, load one of the input registers with

a full-scale code change (all 0s to all 1s and vice versa), and then

execute a software LDAC and monitor the output of the DAC

whose digital code was not changed. The area of the glitch is

expressed in nV-sec.

Data Sheet AD5696/AD5694

Rev. A | Page 15 of 24

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the

output of one DAC in response to a digital code change and

subsequent analog output change of another DAC. It is measured

by loading one channel with a full-scale code change (all 0s to

all 1s and vice versa) using the write to and update commands

while monitoring the output of another channel that is at mid-

scale. The energy of the glitch is expressed in nV-sec.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The

multiplying bandwidth is a measure of this. A sine wave on the

reference (with full-scale code loaded to the DAC) appears on

the output. The multiplying bandwidth is the frequency at

which the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion (THD)

THD is the difference between an ideal sine wave and its

attenuated version using the DAC. The sine wave is used as the

reference for the DAC; THD is a measurement of the harmonics

present on the DAC output. It is measured in dB.

AD5696/AD5694 Data Sheet

Rev. A | Page 16 of 24

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

The AD5696/AD5694 are quad, 16-/12-bit, serial input, voltage

output DACs that operate from supply voltages of 2.7 V to 5.5 V.

Data is written to the AD5696/AD5694 in a 24-bit word format

via a 2-wire serial interface. The AD5696/AD5694 incorporate a

power-on reset circuit to ensure that the DAC output powers up

to a known output state. The devices also have a software power-

down mode that reduces the current consumption to 4 µA.

TRANSFER FUNCTION

Because the input coding to the DAC is straight binary, the ideal

output voltage is given by













×= N

REF

OUT

D

GainVV 2

where:

VREF is the value of the external reference.

Gain is the gain of the output amplifier and is set to 1 by default.

The gain can be set to 1 or 2 using the gain select pin. When the

GAIN pin is tied to GND, all four DAC outputs have a span of

0 V to VREF. When this pin is tied to VDD, all four DAC outputs

have a span of 0 V to 2 × VREF.

D is the decimal equivalent of the binary code that is loaded to

the DAC register as follows: 0 to 4095 for the 12-bit AD5694,

and 0 to 65,535 for the 16-bit AD5696.

N is the DAC resolution (12 bits or 16 bits).

DAC ARCHITECTURE

The DAC architecture consists of a string DAC followed by an

output amplifier. Figure 33 shows a block diagram of the DAC

architecture.

Figure 33. Single DAC Channel Architecture Block Diagram

The resistor string structure is shown in Figure 34. Each resistor

in the string has a value R. The code loaded to the DAC register

determines the node on the string from which the voltage is

tapped off and fed into the output amplifier. The voltage is tapped

off by closing one of the switches that connect the string to the

amplifier. Because the AD5696/AD5694 are a string of resistors,

they are guaranteed monotonic.

Figure 34. Resistor String Structure

Output Amplifiers

The output buffer amplifier can generate rail-to-rail voltages on

its output for an output range of 0 V to VDD. The actual range

depends on the value of VREF, the GAIN pin, the offset error,

and the gain error. The GAIN pin selects the gain of the output.

• When this pin is tied to GND, all four outputs have a gain

of 1, and the output range is from 0 V to VREF.

• When this pin is tied to VDD, all four outputs have a gain

of 2, and the output range is from 0 V to 2 × VREF.

The output amplifiers are capable of driving a load of 1 kΩ in

parallel with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼

to ¾ scale settling time of 5 µs.

INPUT

REGISTER DAC

REGISTER RESISTOR

STRING

REF (+)

V

REF

GND

REF (–)

V

OUT

X

GAIN

(GAIN = 1 OR 2)

10799-052

R

R

R

R

RTO OUTPUT

AMPLIFIER

V

REF

10799-053

Data Sheet AD5696/AD5694

Rev. A | Page 17 of 24

SERIAL INTERFACE

The AD5696/AD5694 have a 2-wire, I2C-compatible serial

interface (see the I2C-Bus Specification, Version 2.1, January

2000, available from Philips Semiconductor). See Figure 2 for a

timing diagram of a typical write sequence. The AD5696/AD5694

can be connected to an I2C bus as slave devices, under the control

of a master device. The AD5696/AD5694 support standard

(100 kHz) and fast (400 kHz) data transfer modes. Support is

not provided for 10-bit addressing or general call addressing.

Input Shift Register

The input shift register of the AD5696/AD5694 is 24 bits wide.

Data is loaded into the device, MSB first, as a 24-bit word under

the control of the serial clock input, SCL. The first eight MSBs

make up the command byte (see Figure 35 and Figure 36).

• The first four bits of the command byte are the command

bits (C3, C2, C1, and C0), which control the mode of oper-

ation of the device (see Table 8).

• The last four bits of the command byte are the address bits

(DAC D, DAC C, DAC B, and DAC A), which select the

DAC that is operated on by the command (see Table 9).

The 8-bit command byte is followed by two data bytes, which

contain the data-word. For the AD5696, the data-word comprises

the 16-bit input code (see Figure 35); for the AD5694, the data-

word comprises the 12-bit input code followed by four don’t care

bits (see Figure 36). The data bits are transferred to the input

shift register on the 24 falling edges of SCL.

Commands can be executed on one DAC channel, any two or

three DAC channels, or on all four DAC channels, depending

on the address bits selected (see Table 9).

Table 8. Command Definitions

Command Bits

C3 C2 C1 C0 Command

0 0 0 0 No operation

0 0 0 1 Write to Input Register n (dependent

on LDAC)

0 0 1 0 Update DAC Register n with contents

of Input Register n

0 0 1 1 Write to and update DAC Channel n

0 1 0 0 Power down/power up DAC

0 1 0 1 Hardware LDAC mask register

0 1 1 0 Software reset (power-on reset)

0

1

1

1

Reserved

1 X1 X1 X1 Reserved

1 X = don’t care.

Table 9. Address Bits and Selected DACs

Address Bits

Selected DAC Channels1 DAC D DAC C DAC B DAC A

0 0 0 1 DAC A

0 0 1 0 DAC B

0 0 1 1 DAC A and DAC B

0

1

0

0

DAC C

0 1 0 1 DAC A and DAC C

0 1 1 0 DAC B and DAC C

0 1 1 1 DAC A, DAC B, and DAC C

1 0 0 0 DAC D

1 0 0 1 DAC A and DAC D

… … … … …

1 1 1 1 All DACs

1 Any combination of DAC channels can be selected using the address bits.

Figure 35. Input Shift Register Contents, AD5696

Figure 36. Input Shift Register Contents, AD5694

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3 C2 C1 C0 DAC D DAC C DAC B DAC A D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

COMMAND DAC ADDRESS DAC DATA DAC DATA

COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE

10799-302

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3 C2 C1 C0 DAC D DAC C DAC B DAC A D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

COMMAND DAC ADDRESS DAC DATA DAC DATA

COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE

10799-300

AD5696/AD5694 Data Sheet

Rev. A | Page 18 of 24

WRITE AND UPDATE COMMANDS

For more information about the LDAC function, see the Load

DAC (Hardware LDAC Pin) section.

Write to Input Register n (Dependent on LDAC)

Command 0001 allows the user to write to each DAC’s

dedicated input register individually. When LDAC is low, the

input register is transparent (if not controlled by the LDAC

mask register).

Update DAC Register n with Contents of Input Register n

Command 0010 loads the DAC registers/outputs with the

contents of the input registers selected by the address bits

(see Table 9) and updates the DAC outputs directly.

Write to and Update DAC Channel n (Independent of LDAC)

Command 0011 allows the user to write to the DAC registers

and update the DAC outputs directly, independent of the state

of the LDAC pin.

I2C SLAVE ADDRESS

The AD5696/AD5694 have a 7-bit I2C slave address. The five

MSBs are 00011, and the two LSBs (A1 and A0) are set by the

state of the A1 and A0 address pins. The ability to make hard-

wired changes to A1 and A0 allows the user to incorporate up

to four AD5696/AD5694 devices on one bus (see Table 10).

Table 10. Device Address Selection

A1 Pin Connection A0 Pin Connection A1 Bit A0 Bit

GND GND 0 0

GND VLOGIC 0 1

VLOGIC GND 1 0

VLOGIC VLOGIC 1 1

SERIAL OPERATION

The 2-wire I2C serial bus protocol operates as follows:

1. The master initiates a data transfer by establishing a start

condition when a high-to-low transition on the SDA line

occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit slave address.

2. The slave device with the transmitted address responds by

pulling SDA low during the 9th clock pulse (this is called

the acknowledge bit). At this stage, all other devices on the

bus remain idle while the selected device waits for data to

be written to, or read from, its input shift register.

3. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit).

Transitions on the SDA line must occur during the low period

of SCL; SDA must remain stable during the high period of SCL.

4. After all data bits are read or written, a stop condition is

established. In write mode, the master pulls the SDA line high

during the 10th clock pulse to establish a stop condition. In

read mode, the master issues a no acknowledge for the 9th

clock pulse (that is, the SDA line remains high). The master

then brings the SDA line low before the 10th clock pulse and

then high again during the 10th clock pulse to establish a

stop condition.

WRITE OPERATION

When writing to the AD5696/AD5694, the user must begin with

a start command followed by an address byte (R/W = 0), after

which the DAC acknowledges that it is prepared to receive data

by pulling SDA low. The AD5696/AD5694 require two bytes of

data for the DAC and a command byte that controls various DAC

functions. Three bytes of data must, therefore, be written to the

DAC with the command byte followed by the most significant

data byte and the least significant data byte, as shown in Figure 37.

All these data bytes are acknowledged by the AD5696/AD5694.

A stop condition follows.

Figure 37. I2C Write Operation

FRAME 2

COMMAND BYTE

FRAME 1

SLAVE ADDRESS

1 9 91

SCL

START BY

MASTER ACK BY

AD5696/AD5694 ACK BY

AD5696/AD5694

SDA R/W DB23A0A11000 1 DB22 DB21 DB20 DB19 DB18 DB17 DB16

1 9 91

ACK BY

AD5696/AD5694 ACK BY

AD5696/AD5694

FRAME 4

LEAST SIGNIFICANT

DATA BYTE

FRAME 3

MOST SIGNIFICANT

DATA BYTE

STOP BY

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

10799-303

Data Sheet AD5696/AD5694

Rev. A | Page 19 of 24

READ OPERATION

When reading data back from the AD5696/AD5694, the user

must begin with a start command followed by an address byte

(R/W = 0), after which the DAC acknowledges that it is prepared

to receive data by pulling SDA low. The address byte must be

followed by the command byte, which determines both the read

command that is to follow and the pointer address to read from;

the command byte is also acknowledged by the DAC. The user

configures the channel to read back the contents of one or more

DAC registers and sets the readback command to active using

the command byte.

Following this, the master establishes a repeated start condition,

and the address is resent with R/W = 1. This byte is acknowledged

by the DAC, indicating that it is prepared to transmit data. Two

bytes of data are then read from the DAC, as shown in Figure 38.

A NACK condition from the master, followed by a stop condition,

completes the read sequence. If more than one DAC is selected,

Channel A is read back by default.

MULTIPLE DAC READBACK SEQUENCE

When reading data back from multiple AD5696/AD5694 DACs,

the user begins with an address byte (R/W = 0), after which the

DAC acknowledges that it is prepared to receive data by pulling

SDA low. The address byte must be followed by the command

byte, which is also acknowledged by the DAC. The user selects

the first channel to read back using the command byte.

Following this, the master establishes a repeated start condition,

and the address is resent with R/W = 1. This byte is acknowledged

by the DAC, indicating that it is prepared to transmit data. The

first two bytes of data are then read from DAC Input Register n

(selected using the command byte), most significant byte first, as

shown in Figure 38. The next two bytes read back are the contents

of DAC Input Register n + 1, and the next bytes read back are

the contents of DAC Input Register n + 2. Data is read from the

DAC input registers in this auto-incremented fashion until a

NACK followed by a stop condition follows. If the contents of

DAC Input Register D are read out, the next two bytes of data

that are read are the contents of DAC Input Register A.

Figure 38. I2C Read Operation

FRAME 2

COMMAND BYTE

FRAME 1

SLAVE ADDRESS

1

1000 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16

9 91

START BY

MASTER ACK BY

AD5696/AD5694 ACK BY

AD5696/AD5694

SCL

SCL

SDA

1 9 91

1 9 91

ACK BY

AD5696/AD5694

REPEATED START BY

MASTER ACK BY

MASTER

FRAME 4

MOST SIGNIFICANT

DATA BYTE n

FRAME 3

SLAVE ADDRESS

ACK BY

MASTER NACK BY

MASTER STOP BY

MASTER

FRAME 6

MOST SIGNIFICANT

DATA BYTE n + 1

FRAME 5

LEAST SIGNIFICANT

DATA BYTE n

1000 1 A1 A0 R/W DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

SDA

SCL

(CONTINUED)

SDA

(CONTINUED) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

10799-304

AD5696/AD5694 Data Sheet

Rev. A | Page 20 of 24

POWER-DOWN OPERATION

Command 0100 is designated for the power-down function. The

AD5696/AD5694 provide three separate power-down modes

(see Table 11). These power-down modes are software program-

mable by setting Bit DB7 to Bit DB0 in the input shift register

(see Table 12). Two bits are associated with each DAC channel.

Table 11 shows how the state of these two bits corresponds to

the mode of operation of the device.

Table 11. Modes of Operation

Operating Mode PDx1 PDx0

Normal Operation 0 0

Power-Down Modes

1 kΩ to GND 0 1

100 kΩ to GND 1 0

Three-State 1 1

Any or all DACs (DAC A to DAC D) can be powered down

to the selected mode by setting the corresponding bits in the

input shift register. See Table 12 for the contents of the input

shift register during the power-down/power-up operation.

When both Bit PDx1 and Bit PDx0 (where x is the DAC selected)

in the input shift register are set to 0, the parts work normally

with their normal power consumption of 0.59 mA at 5 V. When

Bit PDx1, Bit PDx0, or both Bit PDx1 and Bit PDx0 are set to 1,

the part is in power-down mode. In power-down mode, the

supply current falls to 4 μA at 5 V.

In power-down mode, the output stage is internally switched

from the output of the amplifier to a resistor network of known

values. In this way, the output impedance of the part is known

when the part is in power-down mode.

Table 11 lists the three power-down options. The output is

connected internally to GND through either a 1 kΩ or a 100 kΩ

resistor, or it is left open-circuited (three-state). The output stage

is illustrated in Figure 39.

Figure 39. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other

associated linear circuitry are shut down when power-down

mode is activated. However, the contents of the DAC registers

are unaffected in power-down mode, and the DAC registers can

be updated while the device is in power-down mode. The time

required to exit power-down is typically 2.5 µs for VDD = 5 V.

LOAD DAC (HARDWARE LDAC PIN)

The AD5696/AD5694 DACs have double buffered interfaces

consisting of two banks of registers: input registers and DAC

registers. The user can write to any combination of the input

registers (see Table 9). Updates to the DAC registers are con-

trolled by the LDAC pin.

Figure 40. Simplified Diagram of Input Loading Circuitry for a Single DAC

Table 12. 24-Bit Input Shift Register Contents for Power-Down/Power-Up Operation1

DB23

(MSB) DB22 DB21 DB20 DB19 to DB16

DB15

to DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

(LSB)

0 1 0 0 X X PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0

Command bits (C3 to C0) Address bits

(don’t care)

Don’t

care

Power-down

select, DAC D

Power-down

select, DAC C

Power-down

select, DAC B

Power-down

select, DAC A

1 X = don’t care.

RESISTOR

NETWORK

V

OUT

X

DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

10799-058

SDA

SCL

VOUTX

DAC

REGISTER

INPUT SHIFT

REGISTER

OUTPUT

AMPLIFIER

LDAC

VREF

INPUT

REGISTER

12-/16-BIT

DAC

10799-059

Data Sheet AD5696/AD5694

Rev. A | Page 21 of 24

Instantaneous DAC Updating (LDAC Held Low)

For instantaneous updating of the DACs, LDAC is held low while

data is clocked into the input register using Command 0001. Both

the addressed input register and the DAC register are updated on

the 24th clock, and the output begins to change (see Table 14).

Deferred DAC Updating (LDAC Pulsed Low)

For deferred updating of the DACs, LDAC is held high while data

is clocked into the input register using Command 0001. All DAC

outputs are asynchronously updated by pulling LDAC low after the

24th clock. The update occurs on the falling edge of LDAC.

LDAC MASK REGISTER

Command 0101 is reserved for the software LDAC function.

When this command is executed, the address bits are ignored.

When writing to the DAC using Command 0101, the 4-bit LDAC

mask register (DB3 to DB0) is loaded. Bit DB3 of the LDAC mask

register corresponds to DAC D; Bit DB2 corresponds to DAC C;

Bit DB1 corresponds to DAC B; and Bit DB0 corresponds to

DAC A.

The default value of these bits is 0; that is, the LDAC pin works

normally. Setting any of these bits to 1 forces the selected DAC

channel to ignore transitions on the LDAC pin, regardless of the

state of the hardware LDAC pin. This flexibility is useful in appli-

cations where the user wishes to select which channels respond

to the LDAC pin.

The LDAC mask register allows the user extra flexibility and

control over the hardware LDAC pin (see Table 13). Setting

the LDAC bit (DB3 to DB0) to 0 for a DAC channel allows the

hard-ware LDAC pin to control the updating of that channel.

Table 13. LDAC Overwrite Definition

Load LDAC Register

LDAC Bit

(DB3 to DB0) LDAC Pin LDAC Operation

0 1 or 0 Determined by the LDAC pin.

1 X1 DAC channels are updated. (DAC

channels see LDAC pin as 1.)

1 X = don’t care.

HARDWARE RESET PIN (RESET)

RESET is an active low reset that allows the outputs to be cleared

to either zero scale or midscale. The clear code value is user select-

able via the reset select pin (RSTSEL). It is necessary to

keep RESET low for a minimum of 30 ns to complete the

operation.

When the RESET signal is returned high, the output remains at

the cleared value until a new value is programmed. The outputs

cannot be updated with a new value while the RESET pin is low.

There is also a software executable reset function that resets the

DAC to the power-on reset code. Command 0110 is designated

for this software reset function (see Table 8). Any events

on LDAC or RESET during power-on reset are ignored.

RESET SELECT PIN (RSTSEL)

The AD5696/AD5694 contain a power-on reset circuit that

controls the output voltage during power-up. When the RSTSEL

pin is tied to GND, the outputs power up to zero scale (note

that this is outside the linear region of the DAC). When the

RSTSEL pin is tied to VDD, the outputs power up to midscale.

The outputs remain powered up at the level set by the RSTSEL

pin until a valid write sequence is made to the DAC.

Table 14. Write Commands and LDAC Pin Truth Table1

Command Description

Hardware LDAC

Pin State

Input Register

Contents DAC Register Contents

0001 Write to Input Register n (dependent on LDAC) VLOGIC Data update No change (no update)

GND2 Data update Data update

0010 Update DAC Register n with contents of Input

Register n

VLOGIC No change Updated with input register

contents

GND No change Updated with input register

contents

0011 Write to and update DAC Channel n VLOGIC Data update Data update

GND Data update Data update

1 A high to low transition on the hardware LDAC pin always updates the contents of the DAC register with the contents of the input register on channels that are not

masked (blocked) by the LDAC mask register.

2 When the LDAC pin is permanently tied low, the LDAC mask bits are ignored.

AD5696/AD5694 Data Sheet

Rev. A | Page 22 of 24

APPLICATIONS INFORMATION

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5696/AD5694 is via a

serial bus that uses a standard protocol that is compatible with

DSP processors and microcontrollers. The communications

channel requires a 2-wire interface consisting of a clock signal

and a data signal.

AD5696/AD5694 TO ADSP-BF531 INTERFACE

The I2C interface of the AD5696/AD5694 is designed for easy

connection to industry-standard DSPs and microcontrollers.

Figure 41 shows the AD5696/AD5694 connected to the Analog

Devices, Inc., Blackfin® processor. The Blackfin processor has

an integrated I2C port that can be connected directly to the I2C

pins of the AD5696/AD5694.

Figure 41. AD5696/AD5694 to ADSP-BF531 Interface

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure the

rated performance. The PCB on which the AD5696/AD5694

are mounted should be designed so that the AD5696/AD5694

lie on the analog plane.

The AD5696/AD5694 should have ample supply bypassing of

10 µF in parallel with 0.1 µF on each supply, located as close to

the package as possible, ideally right up against the device. The

10 µF capacitor is the tantalum bead type. The 0.1 µF capacitor

should have low effective series resistance (ESR) and low effective

series inductance (ESI), such as the common ceramic types; these

capacitors provide a low impedance path to ground at high

frequencies to handle transient currents due to internal logic

switching.

In systems where many devices are on one board, it is often

useful to provide some heat sinking capability to allow the

power to dissipate easily.

The AD5696/AD5694 LFCSP models have an exposed pad

beneath the device. Connect this pad to the GND supply for

the part. For optimum performance, use special considerations

to design the motherboard and to mount the package.

For enhanced thermal, electrical, and board level performance,

solder the exposed pad on the bottom of the LFCSP package to

the corresponding thermal land paddle on the PCB. Design

thermal vias into the PCB land paddle area to further improve

heat dissipation.

The GND plane on the device can be increased (as shown in

Figure 42) to provide a natural heat sinking effect.

Figure 42. Paddle Connection to Board

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to provide

an isolation barrier between the controller and the unit being

controlled to protect and isolate the controlling circuitry from

any hazardous common-mode voltages that may occur.

The Analog Devices iCoupler® products provide voltage iso-

lation in excess of 2.5 kV. The serial loading structure of the

AD5696/AD5694 makes the part ideal for isolated interfaces

because the number of interface lines is kept to a minimum.

Figure 43 shows a 4-channel isolated interface to the AD5696/

AD5694 using the ADuM1400. For more information, visit

http://www.analog.com/icouplers.

Figure 43. Isolated Interface

ADSP-BF531

SCLGPIO1

SDAGPIO2

LDACPF9

RESETPF8

AD5696/

AD5694

10799-164

AD5696/

AD5694

GND

PLANE

BOARD

10799-166

ENCODE

SERIAL

CLOCK IN

CONTROLLER

ADuM1400

SERIAL

DATA OUT

RESET OUT

LOAD DAC

OUT

DECODE TO

SCL

TO

SDA

TO

RESET

TO

LDAC

V

IA

V

OA

ENCODE DECODE

V

IB

V

OB

ENCODE DECODE

VIC VOC

ENCODE DECODE

VID VOD

10799-167

Data Sheet AD5696/AD5694

Rev. A | Page 23 of 24

OUTLINE DIMENSIONS

Figure 44. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

3 mm × 3 mm Body, Very Very Thin Quad

(CP-16-22)

Dimensions shown in millimeters

Figure 45. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

3.10

3.00 SQ

2.90

0.30

0.23

0.18

1.75

1.60 SQ

1.45

08-16-2010-E

1

0.50

BSC

BOTTOM VIEWTOP VIEW

16

5

8

9

12

13

4

EXPOSED

PAD

PIN 1

INDICATOR

0.50

0.40

0.30

SEATING

PLANE

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

COPLANARITY

0.08

PIN 1

INDICATOR

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

0.80

0.75

0.70

COMPLIANT

TO

JEDEC STANDARDS MO-220-WEED-6.

16 9

81

PIN 1

SEATING

PLANE

8°

0°

4.50

4.40

4.30

6.40

BSC

5.10

5.00

4.90

0.65

BSC

0.15

0.05

1.20

MAX 0.20

0.09 0.75

0.60

0.45

0.30

0.19

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

AD5696/AD5694 Data Sheet

Rev. A | Page 24 of 24

ORDERING GUIDE

Model1 Resolution Temperature Range

Accuracy

(INL) Package Description

Package

Option Branding

AD5696ACPZ-RL7 16 Bits −40°C to +105°C ±8 LSB 16-Lead LFCSP_WQ CP-16-22 DJ8

AD5696BCPZ-RL7 16 Bits −40°C to +105°C ±2 LSB 16-Lead LFCSP_WQ CP-16-22 DJ9

AD5696ARUZ 16 Bits −40°C to +105°C ±8 LSB 16-Lead TSSOP RU-16

AD5696ARUZ-RL7 16 Bits −40°C to +105°C ±8 LSB 16-Lead TSSOP RU-16

AD5696BRUZ 16 Bits −40°C to +105°C ±2 LSB 16-Lead TSSOP RU-16

AD5696BRUZ-RL7 16 Bits −40°C to +105°C ±2 LSB 16-Lead TSSOP RU-16

AD5694BCPZ-RL7 12 Bits −40°C to +105°C ±1 LSB 16-Lead LFCSP_WQ CP-16-22 DJQ

AD5694ARUZ 12 Bits −40°C to +105°C ±2 LSB 16-Lead TSSOP RU-16

AD5694ARUZ-RL7 12 Bits −40°C to +105°C ±2 LSB 16-Lead TSSOP RU-16

AD5694BRUZ 12 Bits −40°C to +105°C ±1 LSB 16-Lead TSSOP RU-16

AD5694BRUZ-RL7 12 Bits −40°C to +105°C ±1 LSB 16-Lead TSSOP RU-16

EVAL-AD5696RSDZ AD5696 TSSOP Evaluation Board

EVAL-AD5694RSDZ AD5694 TSSOP Evaluation Board

1 Z = RoHS Compliant Part.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D10799-0-6/13(A)