Cypress Semiconductor 3033 This product is a Bluetooth wireless EZ-BT WICED Module User Manual CYBT 013033 01 EZ BT Module
Cypress Semiconductor This product is a Bluetooth wireless EZ-BT WICED Module CYBT 013033 01 EZ BT Module
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![Document Number: 002-18414 Rev. ** Page 8 of 33PRELIMINARY CYBT-013033-01Module ConnectionsTable 3 details the solder pad connection definitions and available functions for each connection pad. Table 3 lists the solder pads on the CYBT-013033-01, the silicon device pin, and denotes what functions are available for each solder pad. Table 3 also lists the primary/intended function for each solder pad for the application this module was specifically designed for.Connections and Optional External ComponentsPower Connections (VDDIN)The CYBT-013033-01 contains one power supply connection,VDDIN.VDDIN accepts a supply range of 3.00 V to 3.60 V. Table 10provides this specification. The maximum power supply ripple forthis power connection is 100 mV, as shown in Table 10. External Reset (XRES)The CYBT-013033-01 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This action can also be driven by an external reset signal, which can be used to externally control the device, forcing it into a power-on reset state. The XRES signal is an active-low signal, which is an input to the CYBT-013033-01 module. UART ConnectionsFor full UART functionality, all UART signals must be connected to the Host device. If full UART functionality is not being used, and only UART RXD and TXD are desired or capable, then the following connection considerations should be followed for UART RTS and CTS: ■UART RTS: Can be left floating, pulled low, or pulled high. RTS is not critical for initial firmware uploading at power on. ■UART CTS: Must by pulled low to bypass flow control and to ensure that continuous data transfers are made from the host to the module. External Component RecommendationPower Supply CircuitryIt is not required to place any power supply decoupling or noisereduction circuitry on the host PCB. If desired, an external ferritebead between the supply and the module connection can beincluded, but is not necessary. If used, the ferrite bead should bepositioned as close as possible to the module pin connection. If used, the recommended ferrite bead value is 330, 100 MHz.(Murata BLM21PG331SN1D).Apple MFi Authentication Coprocessor InterfaceIf solder pads 2 and 3 are used as the interface to the Apple MFiauthentication coprocessor, 10 K pull-up resistors should beplaced between the MFi coprocessor and the Cypress module.Table 3. Solder Pad Connection Definitions Pad Number SiliconDevice Pin UART BSC (I2C) PWM GPIO_WAKE GPIO Primary Function1 A6 External Reset Hardware Connection Input External Reset (Active Low)2A8 ✓(SCL) ✓(PWM3) ✓(P3, P29, or P35) Apple SCL Interface3C7 ✓(SDA) ✓(PWM3) ✓(P12) Apple SDA Interface4F8 ✓(BT_GPIO_0)[3] ✓(P36 or P38) Device Wake Event Input5F7✓(PUART: RXD or TXD) ✓(BT_GPIO_1)[4] ✓(P25 or P32) UART_TX DebugHost Wake Event OutputNC/GPIO6F5 ✓(UART_RXD) UART RXD7G4 ✓(UART_CTS) UART CTS8F4 ✓(UART_TXD) UART TXD9F3 ✓(UART_RTS) UART RTS10 VDDIN Power Supply Input (3.00 to 3.60V) Power Supply Input11 GND GND Ground Connection12 GND GND Ground Connection13 GND GND Ground ConnectionNotes3. BT_GPIO_0/BT_DEV_WAKE is a signal from the host to the CYBT-013033-01 that the host requires attention. 4. BT_GPIO_1/BT_HOST_WAKE is a signal from the CYBT-013033-01 module to the host indicating that the Bluetooth device requires attention.](https://usermanual.wiki/Cypress-Semiconductor/3033/User-Guide-3836153-Page-8.png)
![Document Number: 002-18414 Rev. ** Page 19 of 33PRELIMINARY CYBT-013033-01RF SpecificationsTable 15. Receiver RF Specifications[5, 6]Parameter Conditions Minimum Typical[7] Maximum UnitGeneralFrequency range – 2402 – 2480 MHzRX sensitivity[8] GFSK, 0.1% BER, 1 Mbps – –93.5 – dBmp/4-DQPSK, 0.01% BER, 2 Mbps – –95.5 – dBm8-DPSK, 0.01% BER, 3 Mbps – –89.5 – dBmMaximum input GFSK, 1 Mbps – – –20 dBmMaximum input p/4-DQPSK, 8-DPSK, 2/3 Mbps – – –20 dBmInterference Performance■GFSK Modulation[9]C/I cochannel GFSK, 0.1% BER – 9.5 11 dBC/I 1 MHz adjacent channel GFSK, 0.1% BER – –5 0 dBC/I 2 MHz adjacent channel GFSK, 0.1% BER – –40 –30.0 dBC/I > 3 MHz adjacent channel GFSK, 0.1% BER – –49 –40.0 dBC/I image channel GFSK, 0.1% BER – –27 –9.0 dBC/I 1 MHz adjacent to image channel GFSK, 0.1% BER – –37 –20.0 dB■QPSK Modulation[10]C/I cochannel p/4-DQPSK, 0.1% BER – 11 13 dBC/I 1 MHz adjacent channel p/4-DQPSK, 0.1% BER – –8 0 dBC/I 2 MHz adjacent channel p/4-DQPSK, 0.1% BER – –40 –30.0 dBC/I > 3 MHz adjacent channel 8-DPSK, 0.1% BER – –50 –40.0 dBC/I image channel p/4-DQPSK, 0.1% BER – –27 –7.0 dBC/I 1 MHz adjacent to image channel p/4-DQPSK, 0.1% BER – –40 –20.0 dB■8PSK Modulation[11]C/I cochannel 8-DPSK, 0.1% BER – 17 21 dBC/I 1 MHz adjacent channel 8-DPSK, 0.1% BER – –5 5 dBC/I 2 MHz adjacent channel 8-DPSK, 0.1% BER – –40 –25.0 dBC/I > 3 MHz adjacent channel 8-DPSK, 0.1% BER – –47 –33.0 dBC/I Image channel 8-DPSK, 0.1% BER – –20 0 dBC/I 1 MHz adjacent to image channel 8-DPSK, 0.1% BER – –35 –13.0 dBNotes5. All specifications are single ended. Unused inputs are left open.6. All specifications, except typical, are for industrial temperatures.7. Typical operating conditions are 3.3V VBAT and 25°C ambient temperature.8. The receiver sensitivity is measured at BER of 0.1% on the device interface.9. Typical GFSK CI numbers at –7 MHz, –5 MHz, and –3 MHz are –45 dB, –42 dB, and –41 dB, respectively.10. Typical QPSK CI numbers at –7 MHz, –5 MHz, and –3 MHz are –46 dB, –43 dB, and –42 dB, respectively.11. Typical 8PSK CI numbers at –7 MHz, –5 MHz, and –3 MHz are –50 dB, –45 dB, and –45 dB, respectively.12. Meets this specification using front-end band pass filter.13. Numbers are referred to the pin output with an external BPF filter.14. f0 = -64 dBm Bluetooth-modulated signal, f1 = –39 dBm sine wave, f2 = –39 dBm Bluetooth-modulated signal, f0 = 2f1 – f2, and |f2 – f1| = n * 1 MHz, where “n” is 3, 4, or 5. For the typical case, n = 4.15. Includes baseband radiated emissions.](https://usermanual.wiki/Cypress-Semiconductor/3033/User-Guide-3836153-Page-19.png)
![Document Number: 002-18414 Rev. ** Page 20 of 33PRELIMINARY CYBT-013033-01Out-of-Band Blocking Performance (CW)[12]30 MHz–2000 MHz 0.1% BER – –10.0 – dBm2000–2399 MHz 0.1% BER – –27 – dBm2498–3000 MHz 0.1% BER – –27 – dBm3000 MHz–12.75 GHz 0.1% BER – –10.0 – dBmOut-of-Band Blocking Performance, Modulated Interferer776–764 MHz CDMA – –10[13] –dBm824–849 MHz CDMA – –10[13] –dBm1850–1910 MHz CDMA – –23[13] –dBm824–849 MHz EDGE/GSM – –10[13] –dBm880–915 MHz EDGE/GSM – –10[13] –dBm1710–1785 MHz EDGE/GSM – –23[13] –dBm1850–1910 MHz EDGE/GSM – –23[13] –dBm1850–1910 MHz WCDMA – –23[13] –dBm1920–1980 MHz WCDMA – –23[13] –dBmIntermodulation Performance[14]BT, Df = 4 MHz – –39.0 – – dBmSpurious Emissions[15]30 MHz to 1 GHz – – – –62 dBm1–12.75 GHz – – – –47 dBm65–108 MHz FM RX – –147 – dBm/Hz746–764 MHz CDMA – –147 – dBm/Hz851–894 MHz CDMA – –147 – dBm/Hz925–960 MHz EDGE/GSM – –147 – dBm/Hz1805–1880 MHz EDGE/GSM – –147 – dBm/Hz1930–1990 MHz PCS – –147 – dBm/Hz2110–2170 MHz WCDMA – –147 – dBm/HzTable 15. Receiver RF Specifications[5, 6] (continued)Parameter Conditions Minimum Typical[7] Maximum UnitNotes5. All specifications are single ended. Unused inputs are left open.6. All specifications, except typical, are for industrial temperatures.7. Typical operating conditions are 3.3V VBAT and 25°C ambient temperature.8. The receiver sensitivity is measured at BER of 0.1% on the device interface.9. Typical GFSK CI numbers at –7 MHz, –5 MHz, and –3 MHz are –45 dB, –42 dB, and –41 dB, respectively.10. Typical QPSK CI numbers at –7 MHz, –5 MHz, and –3 MHz are –46 dB, –43 dB, and –42 dB, respectively.11. Typical 8PSK CI numbers at –7 MHz, –5 MHz, and –3 MHz are –50 dB, –45 dB, and –45 dB, respectively.12. Meets this specification using front-end band pass filter.13. Numbers are referred to the pin output with an external BPF filter.14. f0 = -64 dBm Bluetooth-modulated signal, f1 = –39 dBm sine wave, f2 = –39 dBm Bluetooth-modulated signal, f0 = 2f1 – f2, and |f2 – f1| = n * 1 MHz, where “n” is 3, 4, or 5. For the typical case, n = 4.15. Includes baseband radiated emissions.](https://usermanual.wiki/Cypress-Semiconductor/3033/User-Guide-3836153-Page-20.png)
![Document Number: 002-18414 Rev. ** Page 21 of 33PRELIMINARY CYBT-013033-01Notes16. All specifications are for industrial temperatures.17. All specifications are single-ended. Unused input are left open.18. +12 dBm output for GFSK measured with PA VDD = 2.5V.19. +9 dBm output for EDR measured with PA VDD = 2.5V.20. Maximum value is the value required for Bluetooth qualification.21. Meets this spec using a front-end bandpass filter.Table 16. Transmitter RF Specifications[16,17]Parameter Conditions Minimum Typical Maximum UnitGeneralFrequency range – 2402 – 2480 MHzClass1: GFSK TX power[18] ––12–dBmClass1: EDR TX power[19] – –9–dBmClass 2: GFSK TX power – – 2 – dBmPower control step – 2 4 8 dBModulation Accuracyp/4-DQPSK Frequency Stability – –10 – 10 kHzp/4-DQPSK RMS DEVM – – – 20 %p/4-QPSK Peak DEVM – – – 35 %p/4-DQPSK 99% DEVM – – – 30 %8-DPSK frequency stability – –10 – 10 kHz8-DPSK RMS DEVM – – – 13 %8-DPSK Peak DEVM – – – 25 %8-DPSK 99% DEVM – – – 20 %In-Band Spurious Emissions1.0 MHz < |M – N| < 1.5 MHz – – – –26 dBc1.5 MHz < |M – N| < 2.5 MHz – – – –20 dBm|M – N| > 2.5 MHz – – – –40 dBmOut-of-Band Spurious Emissions30 MHz to 1 GHz – – – –36.0[20] dBm1–12.75 GHz – – – –30.0[20,21] dBm1.8–1.9 GHz – – – –47.0 dBm5.15–5.3 GHz – – – –47.0 dBmGPS Band Noise Emission (without a front-end band pass filter)1572.92 MHz to 1577.92 MHz – – –150 –127 dBm/HzOut-of-Band Noise Emissions (without a front-end band pass filter)65–108 MHz FM RX – –145 – dBm/Hz746–764 MHz CDMA – –145 – dBm/Hz869–960 MHz CDMA – –145 – dBm/Hz925–960 MHz EDGE/GSM – –145 – dBm/Hz1805–1880 MHz EDGE/GSM – –145 – dBm/Hz1930–1990 MHz PCS – –145 – dBm/Hz2110–2170 MHz WCDMA – –140 – dBm/Hz](https://usermanual.wiki/Cypress-Semiconductor/3033/User-Guide-3836153-Page-21.png)
![Document Number: 002-18414 Rev. ** Page 22 of 33PRELIMINARY CYBT-013033-01Timing and AC CharacteristicsIn this section, use the numbers listed in the reference column to interpret the timing diagrams.System Startup TimingThe global reset signal in the CYBT-013033-01 is a logical OR (actually a wired AND, since the signals are active low) of the XRES input and the internal POR signals. The last signal to be released determines the time at which the chip is released from reset. The POR is typically asserted for 2.4 ms after the POR threshold is crossed.Figure 10 illustrates the startup timing for the CYBT-013033-01.Figure 10. System Startup TimingUART TimingTable 17. BLE RF SpecificationsParameter Conditions Minimum Typical Maximum UnitFrequency Range NA 2402 – 2480 MHzRX Sense[22] GFSK, 0.1% BER, 1 Mbps – –96.5 – dBmTX Power[23] NA – 9 – dBmMod Char: Delta F1 average NA 225 255 275 kHzMod Char: Delta F2 max[24] NA 99.9 – – %Mod Char: Ratio NA 0.8 0.95 – %Notes22. Dirty TX is Off.23. The BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc. The output is capped at 12 dBm out. The BLE TX power at the antenna port cannot exceed the 10 dBm EIRP specification limit.24. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.Table 18. UART Timing SpecificationsRef No. Characteristics Minimum Typical Maximum Unit1 Delay time UART_CTS_N low to UART TXD valid. – – 1.50 Bit periods2 Setup time UART_CTS_N high before midpoint of stop bit. – – 0.67 Bit periods3 Delay time Midpoint of stop bit to UART_RTS_N high. – – 1.33 Bit periods](https://usermanual.wiki/Cypress-Semiconductor/3033/User-Guide-3836153-Page-22.png)
![Document Number: 002-18414 Rev. ** Page 23 of 33PRELIMINARY CYBT-013033-01Figure 11. UART TimingBSC Interface TimingThe timing intervals displayed in Figure 12 can be referenced in Table 19.Figure 12. BSC Interface Timing DiagramTable 19. BSC Interface Timing SpecificationsReference Characteristics Minimum Maximum Unit1 Clock frequency –1004008001000kHz2 START condition setup time 650 – ns3 START condition hold time 280 – ns4 Clock low time 650 – ns5 Clock high time 280 – ns6 Data input hold time[25] 0–ns7 Data input setup time 100 – ns8 STOP condition setup time 280 – ns9 Output valid from clock – 400 ns10 Bus free time[26] 650 – nsNotes25. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions26. Time that the cbus must be free before a new transaction can start.](https://usermanual.wiki/Cypress-Semiconductor/3033/User-Guide-3836153-Page-23.png)
![Document Number: 002-18414 Rev. ** Page 24 of 33PRELIMINARY CYBT-013033-01Environmental SpecificationsEnvironmental ComplianceThis Cypress BLE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) directive. The Cypressmodule and components used to produce this module are RoHS compliant.RF CertificationThe CYBT-013033-01 module is certified under the following RF certification standards:■FCC: WAP3033■CE■IC: 7922A-3033■MIC: TBDSafety CertificationThe CYBT-013033-01 module complies with the following safety regulations:■Underwriters Laboratories, Inc. (UL): Filing E331901■CSA■TUVEnvironmental ConditionsTable describes the operating and storage conditions for the Cypress BLE module.ESD and EMI ProtectionExposed components require special attention to ESD and electromagnetic interference (EMI).A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosurenear the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.Table 20. Environmental Conditions for CYBT-013033-01Description Minimum Specification Maximum SpecificationOperating temperature 30 °C 85 °COperating humidity (relative, non-condensation) 5% 85%Thermal ramp rate – 3 °C/minuteStorage temperature –30 °C 85 °CStorage temperature and humidity – 85 °C at 85%ESD: Module integrated into system Components[27] –15 kV Air2.0 kV ContactNote27. This does not apply to the RF pins (ANT).](https://usermanual.wiki/Cypress-Semiconductor/3033/User-Guide-3836153-Page-24.png)
