Cypress Semiconductor 4110 Bluetooth Module User Manual II

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Document ID	3001122
Application ID	iwhrc5YCg0Q+qBHWgSEuBA==
Document Description	User Manual II
Short Term Confidential	No
Permanent Confidential	No
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Document Type	User Manual
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Filesize	128.09kB (1601119 bits)
Date Submitted	2016-05-23 00:00:00
Date Available	2016-05-23 00:00:00
Creation Date	2015-04-01 18:33:04
Producing Software	Acrobat Distiller 9.5.5 (Windows)
Document Lastmod	2016-05-16 20:39:55
Document Title	CYBLE-022001-00 Bluetooth®Low Energy (BLE) Module
Document Creator	FrameMaker 7.0
Document Author:	Cypress Semiconductor

CYBLE-224116-01
PRELIMINARY
TM
PSoC® XT/XR BT 4.2 Module
EZ-BLE
General Description
The Cypress CYBLE-224116-01 is a fully certified and qualified
module supporting Bluetooth Low Energy (BLE) wireless
communication. The CYBLE-224116-01 is a turnkey solution
that includes onboard power amplifier (PA), low noise amplifier
(LNA), crystal oscillators, chip antenna, passive components,
and the Cypress PSoC® 4 BLE. Refer to the PSoC® 4 BLE
datasheet for additional details on the capabilities of the PSoC®
4 BLE device used on this module.
Low power mode support
p Deep Sleep: 1.3 µA with watch crystal oscillator (WCO) on
p Hibernate: 150 nA with SRAM retention
p Stop: 60 nA with XRES wakeup
Integrated PA/LNA
Supports output power up to +9.5 dBm and RXS of -95 dBm
The EZ-BLETM PSoC® XT/XR BT 4.2 module provides extended
industrial temperature operation (XT) as well as extended
communication range (XR). The EZ-BLETM XT/XR BT 4.2
module is a scalable and reconfigurable platform architecture,
combining programmable and reconfigurable analog and digital
blocks with flexible automatic routing. The CYBLE-224116-01
also includes digital programmable logic, high-performance
analog-to-digital conversion (ADC), opamps with comparator
mode, and standard communication and timing peripherals.
Programmable Analog
The CYBLE-224116-01 includes a royalty-free BLE stack
compatible with Bluetooth 4.2 and provides up to 25 GPIOs in a
small 9.5 × 15.4 × 1.80 mm footprint.
Module Description
Module size: 9.5 mm × 15.4 mm × 1.80 mm (with shield)
Extended Range: Up to 400 meters line-of-sight
Extended industrial temperature range: –40 °C to +105 °C
Up to 25 GPIOs
256-KB flash memory, 32-KB SRAM memory
Bluetooth 4.2 qualified single-mode module
Certified to FCC, CE, MIC, KC, and IC regulations
32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit
multiply, operating at up to 48 MHz
Watchdog timer with dedicated internal low-speed oscillator
Two-pin SWD for programming
Power Consumption
Four opamps with reconfigurable high-drive external and
high-bandwidth internal drive, comparator modes, and ADC
input buffering capability; can operate in Deep-Sleep mode
12-bit, 1-Msps SAR ADC with differential and single-ended
modes; channel sequencer with signal averaging
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
One low-power comparator that operate in Deep-Sleep mode
Programmable Digital
Four programmable logic blocks called universal digital blocks,
(UDBs), each with eight macrocells and datapath
Cypress-provided peripheral Component library, user-defined
state machines, and Verilog input
Capacitive Sensing
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
SNR (> 5:1) and liquid tolerance
Cypress-supplied software component makes
capacitive-sensing design easy
Automatic hardware-tuning algorithm (SmartSense™)
Segment LCD Drive
LCD drive supported on all GPIOs (common or segment)
Operates in Deep-Sleep mode with four bits per pin memory
Serial Communication
Two independent runtime reconfigurable serial communication
blocks (SCBs) with I2C, SPI, or UART functionality
TX output power: –18 dbm to +9.5 dbm
Timing and Pulse-Width Modulation
RX Receive Sensitivity: –95 dbm
Received signal strength indicator (RSSI) with 1-dB resolution
Four 16-bit timer, counter, pulse-width modulator (TCPWM)
blocks
1 Second connection interval with PA/LNA active: 26.3 µA
Center-aligned, Edge, and Pseudo-random modes
TX current consumption:
p BLE silicon: 15.6 mA (radio only, 0 dbm)
p SE2438T: 20 mA (PA/LNA only, +9.5 dBm)
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
RX current consumption of 16.4 mA (radio only)
p BLE silicon: 16.4 mA (radio only)
p SE2438T: 5.5 mA (PA/LNA only)
Up to 25 Programmable GPIOs
Any GPIO pin can be CapSense, LCD, analog, or digital
Two overvoltage-tolerant (OVT) pins; drive modes, strengths,
and slew rates are programmable
Cypress Semiconductor Corporation
198 Champion Court
Document Number: 002-12524 PRELIMINARY
San Jose, CA 95134-1709
408-943-2600
Revised May 16, 2016
PRELIMINARY
CYBLE-224116-01
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to
quickly and effectively integrate the module into your design.
Overview: EZ-BLE Module Portfolio, Module Roadmap
EZ-BLE PSoC Product Overview
PSoC 4 BLE Silicon Datasheet
Application notes: Cypress offers a number of BLE application
notes covering a broad range of topics, from basic to advanced
level. Recommended application notes for getting started with
EZ-BLE modules are:
p AN96841 - Getting Started with EZ-BLE Module
®
p AN94020 - Getting Started with PSoC 4 BLE
®
p AN97060 - PSoC 4 BLE and PRoC™ BLE - Over-The-Air
(OTA) Device Firmware Upgrade (DFU) Guide
p AN91162 - Creating a BLE Custom Profile
p AN91184 - PSoC 4 BLE - Designing BLE Applications
p AN92584 - Designing for Low Power and Estimating Battery
Life for BLE Applications
®
®
p AN85951 - PSoC 4 CapSense Design Guide
®
p AN95089 - PSoC 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques
AN91445 - Antenna Design and RF Layout Guidelines
Technical Reference Manual (TRM):
®
p PSoC 4 BLE Technical Reference Manual
p PSOC(R) 4 BLE Registers Technical Reference Manual
(TRM)
Development Kits:
p CYBLE-224116-EVAL, CYBLE-224116-01 Evaluation Board
®
p CY8CKIT-042-BLE, Bluetooth Low Energy (BLE) Pioneer
Kit
®
p CY8CKIT-002, PSoC MiniProg3 Program and Debug Kit
Test and Debug Tools:
®
p CYSmart, Bluetooth LE Test and Debug Tool (Windows)
®
p CYSmart Mobile, Bluetooth LE Test and Debug Tool
(Android/iOS Mobile App)
PSoC® Creator™ Integrated Design Environment (IDE)
PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and
debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, PRoC BLE and EZ-BLE module systems with no code size limitations. PSoC
peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified,
production-ready PSoC Components™.
PSoC Components are analog and digital “virtual chips,” represented by an icon that users can drag-and-drop into a design and
configure to suit a broad array of application requirements.
Blutooth Low Energy Component
The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you
quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.2 compliant BLE protocol stack and
provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS)
hardware via the stack.
Technical Support
Frequently Asked Questions (FAQs): Learn more about our BLE ECO System.
Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums.
Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,
you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.
Document Number: 002-12524 PRELIMINARY
Page 2 of 42
PRELIMINARY
CYBLE-224116-01
Contents
Overview............................................................................ 4
Module Description...................................................... 4
Pad Connection Interface ................................................ 6
Recommended Host PCB Layout ................................... 8
Power Supply Connections and Recommended External
Components.................................................................... 12
Connection Options................................................... 12
External Component Recommendation .................... 12
Critical Components List ........................................... 15
Antenna Design......................................................... 15
Electrical Specification .................................................. 16
GPIO ......................................................................... 18
XRES......................................................................... 19
Analog Peripherals .................................................... 19
Digital Peripherals ..................................................... 23
Serial Communication ............................................... 25
Memory ..................................................................... 26
System Resources .................................................... 26
Environmental Specifications ....................................... 32
Environmental Compliance ....................................... 32
RF Certification.......................................................... 32
Environmental Conditions ......................................... 32
ESD and EMI Protection ........................................... 32
Document Number: 002-12524 PRELIMINARY
Regulatory Information ..................................................
FCC ...........................................................................
Industry Canada (IC) Certification .............................
European R&TTE Declaration of Conformity ............
MIC Japan .................................................................
KC Korea...................................................................
Packaging........................................................................
Ordering Information......................................................
Part Numbering Convention ......................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
33
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Page 3 of 42
CYBLE-224116-01
PRELIMINARY
Overview
Module Description
The CYBLE-224116-01 is an integrated wireless module designed to be soldered to the main host board.
Module Dimensions and Drawing
Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE
module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should
be completed with the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).
Table 1. Module Design Dimensions
Dimension Item
Specification
Length (X)
9.50 ± 0.15 mm
Width (Y)
15.40 ± 0.15 mm
Length (X)
7.00 mm
Width (Y)
5.00 mm
PCB thickness
Height (H)
0.50 ± 0.10 mm
Shield height
Height (H)
1.10 ± 0.10 mm
Maximum component height
Height (H)
1.30 mm typical (chip antenna)
Total module thickness (bottom of module to highest component)
Height (H)
1.80 mm typical
Module dimensions
Antenna location dimensions
See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-224116-01.
Document Number: 002-12524 PRELIMINARY
Page 4 of 42
PRELIMINARY
CYBLE-224116-01
Figure 1. Module Mechanical Drawing
Top View (View from Top)
Side View
Bottom View (Seen from Bottom)
Note
1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on
recommended host PCB layout, see Figure 3, Figure 4, Figure 5, and Figure 6 and Table 3.
Document Number: 002-12524 PRELIMINARY
Page 5 of 42
CYBLE-224116-01
PRELIMINARY
Pad Connection Interface
As shown in the bottom view of Figure 1 on page 5, the CYBLE-224116-01 connects to the host board via solder pads on the back of
the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-224116-01 module.
Table 2. Solder Pad Connection Description
Name
SP
Connections Connection Type
32
Solder Pads
Pad Length Dimension
Pad Width Dimension
Pad Pitch
0.71 mm
0.41 mm
0.76 mm
Figure 2. Solder Pad Dimensions (Seen from Bottom)
Document Number: 002-12524 PRELIMINARY
Page 6 of 42
PRELIMINARY
CYBLE-224116-01
To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress BLE module is in a corner of the host board with the antenna located on the edge of the host
board. This placement minimizes the additional recommended keep-out area shown in item 2. Please refer to AN96841 for module
placement best practices.
2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional
keep-out area, where no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The
recommended dimensions of the host PCB keep-out area are shown in Figure 3 (dimensions are in mm).
Figure 3. Recommended Host PCB Keep-Out Area Around the CYBLE-224116-01 Trace Antenna
Host PCB Keep-Out Area Around Trace Antenna
Document Number: 002-12524 PRELIMINARY
Page 7 of 42
PRELIMINARY
CYBLE-224116-01
Recommended Host PCB Layout
Figure 4, Figure 5, Figure 6, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the
CYBLE-224116-01. Dimensions are in millimeters unless otherwise noted. The minimum recommended host PCB pad length is 0.91
mm (0.455 mm from center of the pad to either side) is recommended as shown in Figure 6. The host PCB layout pattern can be
completed using either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern.
Figure 4. Host Layout Pattern for CYBLE-224116-01
Document Number: 002-12524 PRELIMINARY
Figure 5. Module Pad Location from Origin
Page 8 of 42
PRELIMINARY
CYBLE-224116-01
Table 3 provides the center location for each solder pad on the CYBLE-224116-01. All dimensions reference the to the center of the
solder pad. Refer to Figure 6 for the location of each module solder pad.
Table 3. Module Solder Pad Location
Solder Pad
(Center of Pad)
Location (X,Y) from
Orign (mm)
Dimension from
Orign (mils)
(0.26, 3.37)
(10.24, 132.68)
(0.26, 4.13)
(10.24, 162.68)
(0.26, 4.89)
(10.24, 192.68)
(0.26, 5.66)
(10.24, 222.68)
(0.26, 6.42)
(10.24, 252.68)
(0.26, 7.18)
(10.24, 282.68)
(0.26, 7.94)
(10.24, 312.68)
(0.26, 8.70)
(10.24, 342.68)
(0.56, 15.14)
(22.05, 596.06)
10
(1.32,15.14)
(51.97, 596.06)
11
(2.08, 15.14)
(81.89, 596.06)
12
(2.84,15.14)
(111.81, 596.06)
13
(3.61, 15.14)
(142.13, 596.06)
14
(4.37, 15.14)
(172.13, 596.06)
15
(5.13, 15.14)
(202.13, 596.06)
16
(5.89, 15.14)
(231.89, 596.06)
17
(6.65,15.14)
(261.81, 596.06)
18
(7.42, 15.14)
(292.13, 596.06)
19
(8.18, 15.14)
(322.05, 596.06)
20
(8.94, 15.14)
(351.97, 596.06)
21
(9.24, 14.04)
(363.78, 552.76)
22
(9.24, 13.28)
(363.78, 522.83)
23
(9.24, 12.51)
(363.78,492.52)
24
(9.24, 11.75)
(363.78, 462.60)
25
(9.24,10.99)
(363.78, 432.68)
26
(9.24,10.23)
(363.78, 402.76)
27
(9.24, 9.47)
(363.78, 372.83)
28
(9.24, 8.70)
(363.78, 342.52)
29
(9.24, 7.94)
(363.78, 312.60)
30
(9.24, 7.18)
(363.78, 282.68)
31
(9.24, 6.42)
(363.78, 252.76)
32
(9.24,5.66)
(363.78, 222.83)
Document Number: 002-12524 PRELIMINARY
Figure 6. Solder Pad Reference Location
Page 9 of 42
CYBLE-224116-01
PRELIMINARY
Table 4 and Table 5 detail the solder pad connection definitions and available functions for each connection pad. Table 4 lists the
solder pads on CYBLE-224116-01, the BLE device port-pin, and denotes whether the digital function shown is available for each
solder pad. Table 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for
a single option shown with a 3.
Table 4. Digital Peripheral Capabilities
Pad
Number
Device
Port Pin
GND[3]
Ground Connection
XRES
External Reset Hardware Connection Input
P1.5
P1.1
P1.0
P0.1
P0.4
P0.5
P0.7
UART
SPI
I2 C
TCPWM[2]
CapSense
3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM2_N)
3(SCB1_SS1)
3(TCPWM0_N)
3(TCPWM0_P)
3(SCB1_TX) 3(SCB1_MISO) 3(SCB1_SCL) 3(TCPWM0_N)
3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM1_P)
3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM1_N)
3(SCB0_CTS) 3(SCB0_SCLK)
3(TCPWM2_N)
WCO ECO
Out OUT
LCD
SWD
GPIO
(SWDCLK)
10
P1.3
11
VDDR
12
P0.6
3(SCB1_SS3)
3(TCPWM1_N)
Radio Power Supply (2.0V to 3.6V)
3(SCB0_RTS) 3(SCB0_SS0)
3(TCPWM2_P)
(SWDIO)
13
P1.2
14
VDD
15
P1.4
16
P2.1
17
VDDA
18
P2.2
19
P2.6
20
P3.0
21
P2.3
22
VREF
23
P3.4
24
P3.5
25
P3.7
26
P3.1
27
P3.6
28
P2.5
29
P5.0
30
P5.1
31
P2.4
32
GND[3]
3(SCB1_SS2)
3(TCPWM1_P)
Digital Power Supply Input (1.71 to 5.5V)
3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM2_P)
3(SCB0_SS2)
Analog Power Supply Input (1.71 to 5.5V)
3(SCB0_SS3)
3(SCB0_RX)
3(SCB0_SDA) 3(TCPWM0_P)
Reference Voltage Input
3(SCB1_RX)
3(SCB1_TX)
3(SCB1_CTS)
3(SCB0_TX)
3(SCB1_RTS)
3(SCB1_SDA) 3(TCPWM2_P)
3(SCB1_SCL) 3(TCPWM2_N)
3(TCPWM3_N)
3(SCB0_SCL) 3(TCPWM0_N)
3(TCPWM3_P)
3(SCB1_RX) 3(SCB1_SS0) 3(SCB1_SDA) 3(TCPWM3_P)
3(SCB1_TX) 3(SCB1_SCLK) 3(SCB1_SCL) 3(TCPWM3_N)
Ground Connection
Notes
2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions.
3. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system.
Document Number: 002-12524 PRELIMINARY
Page 10 of 42
CYBLE-224116-01
PRELIMINARY
Table 5. Analog Peripheral Capabilities
Pad Number
Device Port Pin
GND[3]
Ground Connection
XRES
External Reset Hardware Connection Input
P1.5
P1.1
P1.0
P0.1
P0.4
P0.5
P0.7
10
P1.3
11
VDDR
12
P0.6
13
P1.2
14
VDD
15
P1.4
16
P2.1
17
VDDA
18
P2.2
19
P2.6
20
P3.0
21
P2.3
22
VREF
23
P3.4
24
P3.5
25
P3.7
26
P3.1
27
P3.6
28
P2.5
29
P5.0
30
P5.1
31
P2.4
32
GND
Document Number: 002-12524 PRELIMINARY
SARMUX
OPAMP
LPCOMP
3(CTBm1_OA1_INP)
3(CTBm1_OA0_INN)
3(CTBm1_OA0_INP)
3(COMP0_INN)
3(COMP1_INP)
3(COMP1_INN)
3(CTBm1_OA1_OUT)
Radio Power Supply (2.0V to 3.6V)
3(CTBm1_OA0_OUT)
Digital Power Supply Input (1.71 to 5.5V)
3(CTBm1_OA1_INN)
3(CTBm1_OA0_INN)
Analog Power Supply Input (1.71 to 5.5V)
3(CTBm1_OA0_OUT)
3(CTBm1_OA0_INP)
3(CTBm1_OA1_OUT)
Reference Voltage Input (Optional)
3(CTBm0_OA1_INP)
3(CTBm0_OA1_INN)
Ground Connection
Page 11 of 42
CYBLE-224116-01
PRELIMINARY
Power Supply Connections and Recommended External Components
Power Connections
External Component Recommendation
The CYBLE-224116-01 contains three power supply connections, VDD, VDDA, and VDDR. The VDD and VDDA connections
supply power for the digital and analog device operation respectively. VDDR supplies power for the device radio and PA/LNA.
In either connection scenario, it is recommended to place an
external ferrite bead between the supply and the module
connection. The ferrite bead should be positioned as close as
possible to the module pin connection.
VDD and VDDA accept a supply range of 1.71 V to 5.5 V. VDDR
accepts a supply range of 2.0 V to 3.6 V. These specifications
can be found in Table 12. The maximum power supply ripple for
both power connections on the module is 100 mV, as shown in
Table 10.
Figure 7 details the recommended host schematic options for a
single supply scenario. The use of one or three ferrite beads will
depend on the specific application and configuration of the
CYBLE-224116-01.
The power supply ramp rate of VDD and VDDA must be equal
to or greater than that of VDDR when the radio is used.
Connection Options
Two connection options are available for any application:
1. Single supply: Connect VDD, VDDA, and VDDR to the same
supply.
2. Independent supply: Power VDD, VDDA, and VDDR
separately.
Figure 8 details the recommended host schematic for an
independent supply scenario.
The recommended ferrite bead value is 330 Ω, 100 MHz. (Murata
BLM21PG331SN1D).
Figure 7. Recommended Host Schematic Options for a Single Supply Option
Single Ferrite Bead Option
Document Number: 002-12524 PRELIMINARY
Three Ferrite Bead Option
Page 12 of 42
PRELIMINARY
CYBLE-224116-01
Figure 8. Recommended Host Schematic for an Independent Supply Option
Document Number: 002-12524 PRELIMINARY
Page 13 of 42
PRELIMINARY
CYBLE-224116-01
The CYBLE-224116-01 schematic is shown in Figure 9.
Figure 9. CYBLE-224116-01 Schematic Diagram
Document Number: 002-12524 PRELIMINARY
Page 14 of 42
CYBLE-224116-01
PRELIMINARY
Critical Components List
Table 6 details the critical components used in the CYBLE-224116-01 module.
Table 6. Critical Component List
Component
Reference Designator
Silicon
U1
Description
76-pin WLCSP Programmable System-on-Chip (PSoC) with BLE
Crystal
Y1
24.000 MHz, 10PF
Crystal
Y2
32.768 kHz, 12.5PF
Antenna Design
Table 7 details the antenna used on the CYBLE-224116-01 module. The Cypress module performance improves many of these
characteristics. For more information, see Table 11.
Table 7. Chip Antenna Specifications
Item
Description
Chip Antenna Manufacturer
Johanson Technology Inc.
Chip Antenna Part Number
2450AT18B100
Frequency Range
2400 – 2500 MHz
Peak Gain
0.5 dBi typical
Average Gain
-0.5 dBi typical
Return Loss
9.5 dB minimum
Power Amplifier (PA) and Low Noise Amplifier (LNA)
Table 8 details the PA/LNA that is used on the CYBLE-224116-01 module. For more information, see Table 11.
Table 8. Power Amplifier/Low Noise Amplifier Detailss
Item
Description
PA/LNA Manufacturer
Skyworks Inc.
PA/LNA Part Number
SE2438T
Power Supply Range
2.0V ~ 3.6V
Table 9 details the power consumption of the integrated PA/LNA used on the CYBLE-224116-01 module. Table 9 only details the
current consumption of the SE2438T PA/LNA. VCC = VCC1 = VCC2 = 3 V, TA = +25 „°C, measured on the SE2438T evaluation
board, unless otherwise noted.
Table 9. Power Amplifier/Low Noise Amplifier Current Consumption Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Total supply current ICC_Tx14
Tx mode POUT = +14 dBm
–
33
–
mA
Total supply current ICC_Tx12
Total supply current ICC_Tx10
Tx mode POUT = +12 dBm
–
25
–
mA
Tx mode POUT = +10 dBm
–
20
–
mA
Quiescent current
No RF
–
–
mA
Total supply current ICC_RXHG
Rx Low Noise Amplifier (LNA) High Gain mode
–
5.5
–
mA
Total supply current ICC_RXLG
Total supply current ICC_RXBypass
Rx LNA Low Gain mode
–
2.7
–
mA
Rx Bypass mode
–
–
10
µA
Sleep supply current ICC_OFF
No RF
–
0.05
1.0
µA
ICQ_Tx
Document Number: 002-12524 PRELIMINARY
Page 15 of 42
CYBLE-224116-01
PRELIMINARY
Electrical Specification
Table 10 details the absolute maximum electrical characteristics for the Cypress BLE module.
Table 10. CYBLE-224116-01 Absolute Maximum Ratings
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VDDD_ABS
VDD or VDDA supply relative to VSS (VSSD = VSSA)
–0.5
–
Absolute maximum
VDDR_ABS
VDDR supply relative to VSS (VSSD = VSSA)
-0.3
–
3.6
Restricted by SE2438T
VCCD_ABS
Direct digital core voltage input relative to VSSD
–0.5
–
1.95
Absolute maximum
VDDD_RIPPLE
Maximum power supply ripple for VDD, VDDA and
VDDR input voltage
–
–
100
mV
3.0V supply
Ripple frequency of 100 kHz
to 750 kHz
VGPIO_ABS
GPIO voltage
–0.5
–
VDD +0.5
Absolute maximum
IGPIO_ABS
Maximum current per GPIO
–25
–
25
mA
Absolute maximum
IGPIO_injection
GPIO injection current: Maximum for VIH > VDD
and minimum for VIL < VSS
–0.5
–
0.5
mA
Absolute maximum current
injected per pin
LU
Pin current for latch up
–200
200
mA
–
Max
Units
Details/Conditions
Configurable via register
dBm
settings. PA active.
Table 11 details the RF characteristics for the Cypress BLE module.
Table 11. CYBLE-224116-01 RF Performance Characteristics
Parameter
Description
Min
Typ
RFO1
RF output power on ANT
PA active
–8.5
9.5
RFO2
RF output power on ANT
PA bypassed
-18
dBm
RXS1
RF receive sensitivity on ANT
LNA active
–
–95
–
dBm Measured value
RXS2
RF receive sensitivity on ANT
LNA bypassed
–
–87
–
dBm Measured value
FR
Module frequency range
2400
–
2480
MHz
–
GP
Peak gain
–
0.5
–
dBi
–
GAvg
Average gain
–
–0.5
–
dBi
–
RL
Return loss
–
–10
–
dB
–
Configurable via register
settings. PA in bypass mode.
Table 12 through Table 52 list the module level electrical characteristics for the CYBLE-224116-01. All specifications are valid for –40
°C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.
Table 12. CYBLE-224116-01 DC Specifications
Min
Typ
Max
Units
Details/Conditions
VDD1
Parameter
Power supply input voltage (VDD = VDDA )
Description
1.71
–
5.5
–
VDD2
Power supply input voltage unregulated (VDD =
VDDA)
1.71
1.8
1.89
Internally unregulated
supply
VDD3
Power supply input voltage (VDD = VDDA = VDDR)
2.0
–
3.6
Restricted by SE2438T
VDDR1
Radio supply voltage (radio on)
2.0
–
3.6
Restricted by SE2438T
VDDR2
Radio supply voltage (radio off)
2.0
–
3.6
–
Active Mode, VDD = 1.71 V to 5.5 V
IDD3
Execute from flash; CPU at 3 MHz
–
1.7
–
mA
T = 25 °C,
VDD = 3.3 V
IDD4
Execute from flash; CPU at 3 MHz
–
–
–
mA
T = –40 °C to 85 °C
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CYBLE-224116-01
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Table 12. CYBLE-224116-01 DC Specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
IDD5
Execute from flash; CPU at 6 MHz
–
2.5
–
mA
T = 25 °C,
VDD = 3.3 V
IDD6
Execute from flash; CPU at 6 MHz
–
–
–
mA
T = –40 °C to 85 °C
IDD7
Execute from flash; CPU at 12 MHz
–
–
mA
T = 25 °C,
VDD = 3.3 V
IDD8
Execute from flash; CPU at 12 MHz
–
–
–
mA
T = –40 °C to 85 °C
IDD9
Execute from flash; CPU at 24 MHz
–
7.1
–
mA
T = 25 °C,
VDD = 3.3 V
IDD10
Execute from flash; CPU at 24 MHz
–
–
–
mA
T = –40 °C to 85 °C
IDD11
Execute from flash; CPU at 48 MHz
–
13.4
–
mA
T = 25 °C,
VDD = 3.3 V
IDD12
Execute from flash; CPU at 48 MHz
–
–
–
mA
T = –40 °C to 85 °C
–
–
–
mA
T = 25 °C, VDD = 3.3 V,
SYSCLK = 3 MHz
–
–
–
mA
T = 25 °C, VDD = 3.3 V,
SYSCLK = 3 MHz
Sleep Mode, VDD = 1.71 to 5.5 V
IDD13
IMO on
Sleep Mode, VDD and VDDR = 1.9 to 5.5 V
IDD14
ECO on
Deep-Sleep Mode, VDD = 1.71 to 3.6 V
IDD15
WDT with WCO on
–
1.3
–
µA
T = 25 °C,
VDD = 3.3 V
IDD16
WDT with WCO on
–
–
–
µA
T = –40 °C to 85 °C
IDD17
WDT with WCO on
–
–
–
µA
T = 25 °C,
VDD = 5 V
IDD18
WDT with WCO on
–
–
–
µA
T = –40 °C to 85 °C
Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)
IDD19
WDT with WCO on
–
–
–
µA
T = 25 °C
IDD20
WDT with WCO on
–
–
–
µA
T = –40 °C to 85 °C
Hibernate Mode, VDD = 1.71 to 3.6 V
IDD27
GPIO and reset active
–
150
–
nA
T = 25 °C,
VDD = 3.3 V
IDD28
GPIO and reset active
–
–
–
nA
T = –40 °C to 85 °C
Hibernate Mode, VDD = 3.6 to 5.5 V
IDD29
GPIO and reset active
–
–
–
nA
T = 25 °C,
VDD = 5 V
IDD30
GPIO and reset active
–
–
–
nA
T = –40 °C to 85 °C
Stop Mode, VDD = 1.71 to 3.6 V
IDD33
Stop-mode current (VDD)
–
20
–
nA
T = 25 °C,
VDD = 3.3 V
IDD34
Stop-mode current (VDDR)
–
40
–-
nA
T = 25 °C,
VDDR = 3.3 V
IDD35
Stop-mode current (VDD)
–
–
–
nA
T = –40 °C to 85 °C
IDD36
Stop-mode current (VDDR)
–
–
–
nA
T = –40 °C to 85 °C,
VDDR = 1.9 V to 3.6 V
–
–
–
nA
T = 25 °C,
VDD = 5 V
Stop Mode, VDD = 3.6 to 5.5 V
IDD37
Stop-mode current (VDD)
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CYBLE-224116-01
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Table 12. CYBLE-224116-01 DC Specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
IDD38
Stop-mode current (VDDR)
–
–
–
nA
T = 25 °C,
VDDR = 5 V
IDD39
Stop-mode current (VDD)
–
–
–
nA
T = –40 °C to 85 °C
IDD40
Stop-mode current (VDDR)
–
–
–
nA
T = –40 °C to 85 °C
Table 13. AC Specifications
Parameter
Description
Min
Typ
Max
Units
DC
–
48
MHz
Wakeup from Sleep mode
–
–
µs
Guaranteed by characterization
TDEEPSLEEP
Wakeup from Deep-Sleep mode
–
–
25
µs
24-MHz IMO. Guaranteed by
characterization
THIBERNATE
Wakeup from Hibernate mode
–
–
800
µs
Guaranteed by characterization
TSTOP
Wakeup from Stop mode
–
–
ms
XRES wakeup
Min
Typ
Max
Units
FCPU
CPU frequency
TSLEEP
Details/Conditions
1.71 V ≤ VDD ≤ 5.5 V
GPIO
Table 14. GPIO DC Specifications
Parameter
VIH[4]
Description
Input voltage HIGH threshold
0.7 × VDD
–
–
LVTTL input, VDD < 2.7 V
0.7 × VDD
–
–
LVTTL input, VDD ≥ 2.7 V
2.0
–
–
–
–
0.3 × VDD
Input voltage LOW threshold
VIL
VOH
VOL
Details/Conditions
CMOS input
–
–
CMOS input
LVTTL input, VDD < 2.7 V
–
–
0.3× VDD
–
LVTTL input, VDD ≥ 2.7 V
–
–
0.8
–
Output voltage HIGH level
VDD –0.6
–
–
IOH = 4 mA at 3.3-V VDD
Output voltage HIGH level
VDD –0.5
–
–
IOH = 1 mA at 1.8-V VDD
Output voltage LOW level
–
–
0.6
IOL = 8 mA at 3.3-V VDD
Output voltage LOW level
–
–
0.6
IOL = 4 mA at 1.8-V VDD
IOL = 3 mA at 3.3-V VDD
–
–
0.4
RPULLUP
Output voltage LOW level
Pull-up resistor
3.5
5.6
8.5
kΩ
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
IIL
Input leakage current (absolute value)
–
–
nA
IIL_CTBM
Input leakage on CTBm input pins
–
–
nA
–
CIN
Input capacitance
–
–
pF
–
–
–
25 °C, VDD = 3.3 V
VHYSTTL
Input hysteresis LVTTL
25
40
–
mV
VHYSCMOS
Input hysteresis CMOS
0.05 × VDD
–
–
–
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
–
ITOT_GPIO
Maximum total source or sink chip
current
–
–
200
mA
–
VDD > 2.7 V
Note
4. VIH must not exceed VDD + 0.2 V.
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CYBLE-224116-01
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Table 15. GPIO AC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
TRISEF
Rise time in Fast-Strong mode
–
12
ns
3.3-V VDDD, CLOAD = 25 pF
TFALLF
Fall time in Fast-Strong mode
–
12
ns
3.3-V VDDD, CLOAD = 25 pF
TRISES
Rise time in Slow-Strong mode
10
–
60
ns
3.3-V VDDD, CLOAD = 25 pF
TFALLS
Fall time in Slow-Strong mode
10
–
60
ns
3.3-V VDDD, CLOAD = 25 pF
FGPIOUT1
GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V
Fast-Strong mode
–
–
33
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT2
GPIO Fout; 1.7 V≤ VDD ≤ 3.3 V
Fast-Strong mode
–
–
16.7
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT3
GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V
Slow-Strong mode
–
–
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT4
GPIO Fout; 1.7 V ≤ VDD ≤ 3.3 V
Slow-Strong mode
–
–
3.5
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOIN
GPIO input operating frequency
1.71 V ≤ VDD ≤ 5.5 V
–
–
48
MHz
90/10% VIO
XRES
Table 16. XRES DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VIH
Input voltage HIGH threshold
0.7 × VDDD
–
–
CMOS input
VIL
Input voltage LOW threshold
–
–
0.3 × VDDD
CMOS input
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
–
CIN
Input capacitance
–
–
pF
–
VHYSXRES
Input voltage hysteresis
–
100
–
mV
–
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
µs
–
Table 17. XRES AC Specifications
Parameter
TRESETWIDTH
Description
Reset pulse width
Analog Peripherals
Opamp
Table 18. Opamp Specifications
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
IDD (Opamp Block Current. VDD = 1.8 V. No Load)
IDD_HI
Power = high
–
1000
1300
µA
IDD_MED
Power = medium
–
500
–
µA
IDD_LOW
Power = low
–
250
350
µA
GBW (Load = 20 pF, 0.1 mA. VDDA = 2.7 V)
GBW_HI
Power = high
–
–
MHz
GBW_MED
Power = medium
–
–
MHz
GBW_LO
Power = low
–
–
MHz
IOUT_MAX (VDDA ≥ 2.7 V, 500 mV from Rail)
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PRELIMINARY
Table 18. Opamp Specifications (continued)
Parameter
Description
Min
Typ
Max
Units
IOUT_MAX_HI
Power = high
10
–
–
mA
IOUT_MAX_MID
Power = medium
10
–
–
mA
IOUT_MAX_LO
Power = low
–
–
mA
Details/
Conditions
IOUT (VDDA = 1.71 V, 500 mV from Rail)
IOUT_MAX_HI
Power = high
–
–
mA
IOUT_MAX_MID
Power = medium
–
–
mA
IOUT_MAX_LO
Power = low
–
–
mA
VIN
Charge pump on, VDDA ≥ 2.7 V
–0.05
–
VDDA – 0.2
VCM
Charge pump on, VDDA ≥ 2.7 V
–0.05
–
VDDA – 0.2
0.5
–
VDDA – 0.5
VOUT (VDDA ≥ 2.7 V)
VOUT_1
Power = high, ILOAD=10 mA
VOUT_2
Power = high, ILOAD=1 mA
0.2
–
VDDA – 0.2
VOUT_3
Power = medium, ILOAD=1 mA
0.2
–
VDDA – 0.2
VOUT_4
Power = low, ILOAD=0.1 mA
0.2
–
VDDA – 0.2
VOS_TR
Offset voltage, trimmed
±0.5
mV
High mode
VOS_TR
Offset voltage, trimmed
–
±1
–
mV
Medium mode
VOS_TR
Offset voltage, trimmed
–
±2
–
mV
Low mode
VOS_DR_TR
Offset voltage drift, trimmed
–10
±3
10
µV/C
High mode
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
µV/C
Medium mode
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
µV/C
Low mode
CMRR
DC
65
70
–
dB
VDDD = 3.6 V,
High-power mode
PSRR
At 1 kHz, 100-mV ripple
70
85
–
dB
VDDD = 3.6 V
VN1
Input referred, 1 Hz–1 GHz, power = high
–
94
–
µVrms
VN2
Input referred, 1 kHz, power = high
–
72
–
nV/rtHz
VN3
Input referred, 10 kHz, power = high
–
28
–
nV/rtHz
VN4
Input referred, 100 kHz, power = high
–
15
–
nV/rtHz
CLOAD
Stable up to maximum load. Performance
specs at 50 pF
–
–
125
pF
Slew_rate
Cload = 50 pF, Power = High,
VDDA ≥ 2.7 V
–
–
V/µsec
T_op_wake
From disable to enable, no external RC
dominating
–
300
–
µsec
Noise
Comp_mode (Comparator Mode; 50-mV Drive, TRISE = TFALL (Approx.)
TPD1
Response time; power = high
–
150
–
nsec
TPD2
Response time; power = medium
–
400
–
nsec
TPD3
Response time; power = low
–
2000
–
nsec
Vhyst_op
Hysteresis
–
10
–
mV
–
kHz
Deep-Sleep Mode (Deep-Sleep mode operation is only guaranteed for VDDA > 2.5 V)
GBW_DS
Gain bandwidth product
–
50
IDD_DS
Current
–
15
–
µA
Vos_DS
Offset voltage
–
–
mV
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Table 18. Opamp Specifications (continued)
Parameter
Description
Min
Typ
Max
Units
–
20
–
µV/°C
Vos_dr_DS
Offset voltage drift
Vout_DS
Output voltage
0.2
–
VDD–0.2
Vcm_DS
Common mode voltage
0.2
–
VDD–1.8
Min
Typ
Max
Units
Details/
Conditions
Table 19. Comparator DC Specifications
Parameter
Description
VOFFSET1
Input offset voltage, Factory trim
–
–
±10
mV
VOFFSET2
Input offset voltage, Custom trim
–
–
±6
mV
VOFFSET3
Input offset voltage, ultra-low-power mode
–
±12
–
mV
VHYST
Hysteresis when enabled
–
10
35
mV
Details/
Conditions
VICM1
Input common mode voltage in normal mode
–
VDDD –0.1
VICM2
Input common mode voltage in low-power
mode
–
VDDD
VICM3
Input common mode voltage in ultra
low-power mode
–
VDDD
–1.15
CMRR
Common mode rejection ratio
50
–
–
dB
VDDD ≥ 2.7 V
CMRR
Common mode rejection ratio
42
–
–
dB
VDDD ≤ 2.7 V
ICMP1
Block current, normal mode
–
–
400
µA
ICMP2
Block current, low-power mode
–
–
100
µA
ICMP3
Block current in ultra-low-power mode
–
–
µA
ZCMP
DC input impedance of comparator
35
–
–
MΩ
Min
Typ
Max
Units
Modes 1 and 2
Table 20. Comparator AC Specifications
Parameter
Description
Details/
Conditions
TRESP1
Response time, normal mode, 50-mV
overdrive
–
38
–
ns
50-mV overdrive
TRESP2
Response time, low-power mode, 50-mV
overdrive
–
70
–
ns
50-mV overdrive
TRESP3
Response time, ultra-low-power mode,
50-mV overdrive
–
2.3
–
µs
200-mV overdrive
Min
–5
Typ
±1
Max
Units
°C
Details/Conditions
–40 to +85 °C
Details/Conditions
Temperature Sensor
Table 21. Temperature Sensor Specifications
Parameter
TSENSACC
Description
Temperature-sensor accuracy
SAR ADC
Table 22. SAR ADC DC Specifications
Parameter
A_RES
Description
Resolution
Document Number: 002-12524 PRELIMINARY
Min
Typ
Max
Units
–
–
12
bits
Page 21 of 42
CYBLE-224116-01
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Table 22. SAR ADC DC Specifications
A_CHNIS_S
Number of channels - single-ended
–
–
8 full-speed
A-CHNKS_D
Number of channels - differential
–
–
Diff inputs use
neighboring I/O
A-MONO
Monotonicity
–
–
–
A_GAINERR
Gain error
–
–
±0.1
With external
reference
A_OFFSET
Input offset voltage
–
–
mV
Measured with 1-V
VREF
A_ISAR
Current consumption
–
–
mA
A_VINS
Input voltage range - single-ended
VSS
–
VDDA
A_VIND
Input voltage range - differential
VSS
–
VDDA
Yes
A_INRES
Input resistance
–
–
2.2
kΩ
A_INCAP
Input capacitance
–
–
10
pF
VREFSAR
Trimmed internal reference to SAR
–1
–
Min
Typ
Max
Units
Percentage of Vbg
(1.024 V)
Table 23. SAR ADC AC Specifications
Parameter
Description
A_PSRR
Power-supply rejection ratio
70
–
–
dB
A_CMRR
Common-mode rejection ratio
66
–
–
dB
Details/
Conditions
Measured at 1-V
reference
A_SAMP
Sample rate
–
–
Msps
Fsarintref
SAR operating speed without external ref.
bypass
–
–
100
Ksps
A_SNR
Signal-to-noise ratio (SNR)
65
–
–
dB
A_BW
Input bandwidth without aliasing
–
–
A_SAMP/2
kHz
A_INL
Integral nonlinearity. VDD = 1.71 V to 5.5 V,
1 Msps
–1.7
–
LSB
VREF = 1 V to VDD
A_INL
Integral nonlinearity. VDDD = 1.71 V to 3.6 V,
1 Msps
–1.5
–
1.7
LSB
VREF = 1.71 V to VDD
A_INL
Integral nonlinearity. VDD = 1.71 V to 5.5 V,
500 Ksps
–1.5
–
1.7
LSB
VREF = 1 V to VDD
A_dnl
Differential nonlinearity. VDD = 1.71 V to
5.5 V, 1 Msps
–1
–
2.2
LSB
VREF = 1 V to VDD
A_DNL
Differential nonlinearity. VDD = 1.71 V to
3.6 V, 1 Msps
–1
–
LSB
VREF = 1.71 V to VDD
A_DNL
Differential nonlinearity. VDD = 1.71 V to
5.5 V, 500 Ksps
–1
–
2.2
LSB
VREF = 1 V to VDD
A_THD
Total harmonic distortion
–
–
–65
dB
Description
Min
Typ
Max
Units
VCSD
Voltage range of operation
1.71
–
5.5
IDAC1
DNL for 8-bit resolution
–1
–
LSB
12-bit resolution
FIN = 10 kHz
FIN = 10 kHz
CSD
CSD Block Specifications
Parameter
Document Number: 002-12524 PRELIMINARY
Details/
Conditions
Page 22 of 42
CYBLE-224116-01
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CSD Block Specifications (continued)
Parameter
Description
Min
Typ
Max
Units
IDAC1
INL for 8-bit resolution
–3
–
LSB
IDAC2
DNL for 7-bit resolution
–1
–
LSB
IDAC2
INL for 7-bit resolution
–3
–
LSB
SNR
Ratio of counts of finger to noise
–
–
Ratio
IDAC1_CRT1
Output current of IDAC1 (8 bits) in High
range
–
612
–
µA
IDAC1_CRT2
Output current of IDAC1 (8 bits) in Low
range
–
306
–
µA
IDAC2_CRT1
Output current of IDAC2 (7 bits) in High
range
–
305
–
µA
IDAC2_CRT2
Output current of IDAC2 (7 bits) in Low
range
–
153
–
µA
Details/
Conditions
Capacitance range of
9 pF to 35 pF, 0.1-pF
sensitivity. Radio is not
operating during the
scan
Digital Peripherals
Timer
Table 24. Timer DC Specifications
Parameter
ITIM1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
42
Units
µA
Details/Conditions
16-bit timer
ITIM2
Block current consumption at 12 MHz
–
–
130
µA
16-bit timer
ITIM3
Block current consumption at 48 MHz
–
–
535
µA
16-bit timer
Min
FCLK
Typ
–
Max
48
Units
MHz
Table 25. Timer AC Specifications
Parameter
TTIMFREQ
Description
Operating frequency
Details/Conditions
TCAPWINT
Capture pulse width (internal)
2 × TCLK
–
–
ns
TCAPWEXT
Capture pulse width (external)
2 × TCLK
–
–
ns
TTIMRES
Timer resolution
TCLK
–
–
ns
TTENWIDINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
TTENWIDEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
TTIMRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
TTIMRESEXT
Reset pulse width (external)
2 × TCLK
–
–
ns
16-bit counter
16-bit counter
Counter
Table 26. Counter DC Specifications
Parameter
ICTR1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
42
ICTR2
Block current consumption at 12 MHz
–
–
130
Units
µA
µA
ICTR3
Block current consumption at 48 MHz
–
–
535
µA
Document Number: 002-12524 PRELIMINARY
Details/Conditions
16-bit counter
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Table 27. Counter AC Specifications
Parameter
TCTRFREQ
Description
Operating frequency
Min
FCLK
Typ
–
Max
48
Units
MHz
TCTRPWINT
Capture pulse width (internal)
2 × TCLK
–
–
ns
TCTRPWEXT
Capture pulse width (external)
2 × TCLK
–
–
ns
TCTRES
Counter Resolution
TCLK
–
–
ns
TCENWIDINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
TCENWIDEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
TCTRRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
TCTRRESWEXT
Reset pulse width (external)
2 × TCLK
–
–
ns
Details/Conditions
Pulse Width Modulation (PWM)
Table 28. PWM DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
IPWM1
Block current consumption at 3 MHz
–
–
42
µA
16-bit PWM
IPWM2
Block current consumption at 12 MHz
–
–
130
µA
16-bit PWM
IPWM3
Block current consumption at 48 MHz
–
–
535
µA
16-bit PWM
Min
Typ
Max
Units
Table 29. PWM AC Specifications
Parameter
Description
TPWMFREQ
Operating frequency
FCLK
–
48
MHz
TPWMPWINT
Pulse width (internal)
2 × TCLK
–
–
ns
TPWMEXT
Pulse width (external)
2 × TCLK
–
–
ns
TPWMKILLINT
Kill pulse width (internal)
2 × TCLK
–
–
ns
TPWMKILLEXT
Kill pulse width (external)
2 × TCLK
–
–
ns
TPWMEINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
TPWMENEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
TPWMRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
TPWMRESWEXT
Reset pulse width (external)
2 × TCLK
–
–
ns
Details/Conditions
LCD Direct Drive
Table 30. LCD Direct Drive DC Specifications
Spec ID
SID228
Parameter
ILCDLOW
Description
Operating current in low-power mode
SID229
CLCDCAP
LCD capacitance per segment/common
driver
Long-term segment offset
SID230
LCDOFFSET
SID231
ILCDOP1
SID232
ILCDOP2
LCD system operating current
VBIAS = 5 V
LCD system operating current
VBIAS = 3.3 V
Min
–
Typ
17.5
Max
–
Units Details/Conditions
µA 16 × 4 small segment
display at 50 Hz
pF
–
500
5000
–
20
–
mV
–
–
mA
–
–
mA
Min
10
Typ
50
Max
150
Units
Hz
32 × 4 segments.
50 Hz at 25 °C
32 × 4 segments
50 Hz at 25 °C
Table 31. LCD Direct Drive AC Specifications
Spec ID
SID233
Parameter
FLCD
Description
LCD frame rate
Document Number: 002-12524 PRELIMINARY
Details/Conditions
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Serial Communication
Table 32. Fixed I2C DC Specifications
Parameter
Description
II2C1
Block current consumption at 100 kHz
II2C2
Block current consumption at 400 kHz
II2C3
Block current consumption at 1 Mbps
I C enabled in Deep-Sleep mode
II2C4
Min
Typ
Max
Units
Details/Conditions
–
–
50
µA
–
–
–
155
µA
–
–
–
390
µA
–
–
–
1.4
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
400
kHz
Table 33. Fixed I2C AC Specifications
Parameter
FI2C1
Description
Bit rate
Table 34. Fixed UART DC Specifications
Min
Typ
Max
Units
Details/Conditions
IUART1
Parameter
Block current consumption at 100 kbps
Description
–
–
55
µA
–
IUART2
Block current consumption at 1000 kbps
–
–
312
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
Mbps
–
Table 35. Fixed UART AC Specifications
Parameter
FUART
Description
Bit rate
Table 36. Fixed SPI DC Specifications
Min
Typ
Max
Units
Details/Conditions
ISPI1
Parameter
Block current consumption at 1 Mbps
Description
–
–
360
µA
–
ISPI2
Block current consumption at 4 Mbps
–
–
560
µA
–
ISPI3
Block current consumption at 8 Mbps
–
–
600
µA
–
Table 37. Fixed SPI AC Specifications
Parameter
FSPI
Description
Min
Typ
Max
Units
Details/Conditions
SPI operating frequency (master; 6x over sampling)
–
–
MHz
–
Table 38. Fixed SPI Master Mode AC Specifications
Min
Typ
Max
Units
Details/Conditions
TDMO
Parameter
MOSI valid after SCLK driving edge
Description
–
–
18
ns
–
TDSI
MISO valid before SCLK capturing edge
Full clock, late MISO sampling used
20
–
–
ns
Full clock, late MISO sampling
THMO
Previous MOSI data hold time
–
–
ns
Referred to Slave capturing edge
Table 39. Fixed SPI Slave Mode AC Specifications
Parameter
Description
Min
Typ
Max
Units
TDMI
MOSI valid before SCLK capturing edge
40
–
–
ns
TDSO
MISO valid after SCLK driving edge
–
–
42 + 3 × TCPU
ns
TDSO_ext
MISO Valid after SCLK driving edge in
external clock mode. VDD < 3.0 V
–
–
50
ns
THSO
Previous MISO data hold time
TSSELSCK
SSEL valid to first SCK valid edge
Document Number: 002-12524 PRELIMINARY
–
–
ns
100
–
–
ns
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Memory
Table 40. Flash DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
1.71
–
5.5
–
Number of Wait states at 32–48 MHz
–
–
CPU execution from flash
Number of Wait states at 16–32 MHz
–
–
CPU execution from flash
Number of Wait states for 0–16 MHz
–
–
CPU execution from flash
Min
Typ
Max
VPE
Erase and program voltage
TWS48
TWS32
TWS16
Table 41. Flash AC Specifications
Parameter
Description
Units
Details/Conditions
TROWWRITE[5]
TROWERASE[5]
Row (block) write time (erase and program)
–
–
20
ms
Row erase time
–
–
13
ms
–
TROWPROGRAM[5]
TBULKERASE[5]
TDEVPROG[5]
Row program time after erase
–
–
ms
–
Bulk erase time (256 KB)
–
–
35
ms
–
–
–
25
seconds
–
FEND
Flash endurance
100 K
–
–
cycles
–
FRET
Flash retention. TA ≤ 55 °C, 100 K P/E cycles
20
–
–
years
–
FRET2
Flash retention. TA ≤ 85 °C, 10 K P/E cycles
10
–
–
years
–
Min
Typ
Max
Units
Details/Conditions
Total device program time
Row (block) = 256 bytes
System Resources
Power-on-Reset (POR)
Table 42. POR DC Specifications
Parameter
Description
VRISEIPOR
Rising trip voltage
0.80
–
1.45
–
VFALLIPOR
Falling trip voltage
0.75
–
1.40
–
VIPORHYST
Hysteresis
15
–
200
mV
–
Min
Typ
Max
Units
Details/Conditions
–
–
µs
–
Table 43. POR AC Specifications
Parameter
TPPOR_TR
Description
Precision power-on reset (PPOR) response
time in Active and Sleep modes
Table 44. Brown-Out Detect
Description
Min
Typ
Max
Units
Details/Conditions
VFALLPPOR
Parameter
BOD trip voltage in Active and Sleep modes
1.64
–
–
–
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.4
–
–
–
Table 45. Hibernate Reset
Parameter
VHBRTRIP
Description
BOD trip voltage in Hibernate
Min
Typ
Max
Units
Details/Conditions
1.1
–
–
–
Note
5. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have
completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make
certain that these are not inadvertently activated.
Document Number: 002-12524 PRELIMINARY
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Voltage Monitors (LVD)
Table 46. Voltage Monitor DC Specifications
Parameter
VLVI1
Description
LVI_A/D_SEL[3:0] = 0000b
Min
1.71
Typ
1.75
Max
1.79
Units
Details/Conditions
–
VLVI2
LVI_A/D_SEL[3:0] = 0001b
1.76
1.80
1.85
–
VLVI3
LVI_A/D_SEL[3:0] = 0010b
1.85
1.90
1.95
–
VLVI4
LVI_A/D_SEL[3:0] = 0011b
1.95
2.00
2.05
–
VLVI5
LVI_A/D_SEL[3:0] = 0100b
2.05
2.10
2.15
–
VLVI6
LVI_A/D_SEL[3:0] = 0101b
2.15
2.20
2.26
–
VLVI7
LVI_A/D_SEL[3:0] = 0110b
2.24
2.30
2.36
–
VLVI8
LVI_A/D_SEL[3:0] = 0111b
2.34
2.40
2.46
–
VLVI9
LVI_A/D_SEL[3:0] = 1000b
2.44
2.50
2.56
–
VLVI10
LVI_A/D_SEL[3:0] = 1001b
2.54
2.60
2.67
–
VLVI11
LVI_A/D_SEL[3:0] = 1010b
2.63
2.70
2.77
–
VLVI12
LVI_A/D_SEL[3:0] = 1011b
2.73
2.80
2.87
–
VLVI13
LVI_A/D_SEL[3:0] = 1100b
2.83
2.90
2.97
–
VLVI14
LVI_A/D_SEL[3:0] = 1101b
2.93
3.00
3.08
–
VLVI15
LVI_A/D_SEL[3:0] = 1110b
3.12
3.20
3.28
–
VLVI16
LVI_A/D_SEL[3:0] = 1111b
4.39
4.50
4.61
–
LVI_IDD
Block current
–
–
100
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
µs
–
Min
Typ
Max
Units
Details/Conditions
–
–
14
MHz
SWDCLK ≤ 1/3 CPU clock frequency
Table 47. Voltage Monitor AC Specifications
Parameter
TMONTRIP
Description
Voltage monitor trip time
SWD Interface
Table 48. SWD Interface Specifications
Parameter
Description
F_SWDCLK1
3.3 V ≤ VDD ≤ 5.5 V
F_SWDCLK2
1.71 V ≤ VDD ≤ 3.3 V
–
–
MHz
SWDCLK ≤ 1/3 CPU clock frequency
T_SWDI_SETUP T = 1/f SWDCLK
0.25 × T
–
–
ns
–
T_SWDI_HOLD
0.25 × T
–
–
ns
–
T_SWDO_VALID T = 1/f SWDCLK
T = 1/f SWDCLK
–
–
0.5 × T
ns
–
T_SWDO_HOLD
–
–
ns
–
T = 1/f SWDCLK
Document Number: 002-12524 PRELIMINARY
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Internal Main Oscillator
Table 49. IMO DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
IIMO1
IMO operating current at 48 MHz
–
–
1000
µA
–
IIMO2
IMO operating current at 24 MHz
–
–
325
µA
–
IIMO3
IMO operating current at 12 MHz
–
–
225
µA
–
IIMO4
IMO operating current at 6 MHz
–
–
180
µA
–
IIMO5
IMO operating current at 3 MHz
–
–
150
µA
–
Table 50. IMO AC Specifications
Min
Typ
Max
Units
FIMOTOL3
Parameter
Frequency variation from 3 to 48 MHz
Description
–
–
±2
Details/Conditions
FIMOTOL3
IMO startup time
–
12
–
µs
–
Min
Typ
Max
Units
Details/Conditions
–
0.3
1.05
µA
–
With API-called calibration
Internal Low-Speed Oscillator
Table 51. ILO DC Specifications
Parameter
IILO2
Description
ILO operating current at 32 kHz
Table 52. ILO AC Specifications
Min
Typ
Max
Units
Details/Conditions
TSTARTILO1
Parameter
ILO startup time
Description
–
–
ms
–
FILOTRIM1
32-kHz trimmed frequency
15
32
50
kHz
–
Table 53. ECO Trim Value Specification
Parameter
ECOTRIM
Description
24-MHz trim value
(firmware configuration)
Value
Details/Conditions
0x00003FFA
Optimum trim value that needs to be loaded to register
CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG
Table 54. UDB AC Specifications
Parameter
Description
Min
Typ
Max
Units
FMAX-TIMER
Max frequency of 16-bit timer in a UDB
pair
–
–
48
MHz
FMAX-ADDER
Max frequency of 16-bit adder in a UDB
pair
–
–
48
MHz
FMAX_CRC
Max frequency of 16-bit CRC/PRS in a
UDB pair
–
–
48
MHz
–
–
48
MHz
Details/Conditions
Data Path performance
PLD Performance in UDB
FMAX_PLD
Max frequency of 2-pass PLD function
in a UDB pair
Clock to Output Performance
TCLK_OUT_UDB1
Prop. delay for clock in to data out at
25 °C, Typical
–
15
–
ns
TCLK_OUT_UDB2
Prop. delay for clock in to data out,
Worst case
–
25
–
ns
Document Number: 002-12524 PRELIMINARY
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CYBLE-224116-01
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Table 55. BLE Subsystem
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
RF Receiver Specification
RXS, DIRTY
RX sensitivity with dirty transmitter
–
–95
–
dBm
With LNA active
RXS, LOWGAIN
RX sensitivity in low-gain mode with idle
transmitter
–
–87
–
dBm
LNA in bypass mode
RXS, HIGHGAIN
RX sensitivity in high-gain mode with idle
transmitter
–
–95
–
dBm
With LNA active
PRXMAX
Maximum input power
–10
–1
–
dBm
CI1
Cochannel interference,
Wanted signal at –67 dBm and Interferer
at FRX
–
21
dB
RF-PHY Specification
(RCV-LE/CA/06/C)
RF-PHY Specification
(RCV-LE/CA/03/C)
CI2
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±1 MHz
–
TBD
–
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI3
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±2 MHz
–
TBD
–
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI4
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at ≥FRX ±3 MHz
–
TBD
–
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI5
Adjacent channel interference
Wanted Signal at –67 dBm and Interferer
at Image frequency (FIMAGE)
–
TBD
–
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI3
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at Image frequency (FIMAGE ± 1 MHz)
–
TBD
–
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
OBB1
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 30–2000 MHz
–
TBD
–
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
OBB2
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 2003–2399 MHz
–
TBD
–
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
OBB3
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 2484–2997 MHz
–
TBD
–
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
OBB4
Out-of-band blocking,
Wanted signal a –67 dBm and Interferer
at F = 3000–12750 MHz
–
TBD
–
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
IMD
Intermodulation performance
Wanted signal at –64 dBm and 1-Mbps
BLE, third, fourth, and fifth offset channel
–
TBD
–
dBm
RF-PHY Specification
(RCV-LE/CA/05/C)
RXSE1
Receiver spurious emission
30 MHz to 1.0 GHz
–
TBD
–
dBm
100-kHz measurement
bandwidth
ETSI EN300 328 V1.8.1
RXSE2
Receiver spurious emission
1.0 GHz to 12.75 GHz
–
TBD
–
dBm
1-MHz measurement
bandwidth
ETSI EN300 328 V1.8.1
Document Number: 002-12524 PRELIMINARY
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Table 55. BLE Subsystem (continued)
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
RF Transmitter Specifications
TXP, ACC
RF power accuracy
–
±1
–
dB
TXP, RANGE
RF power control range
–
30
–
dB
TXP, 0dBm
Output power, 0-dB Gain setting (PA7)
–
–
-6
dBm
TXP, MAX
–
9.5
–
dBm
–
–18
–
dBm
185
–
–
kHz
225
250
275
kHz
EO
Output power, maximum power setting
(PA10)
Output power, minimum power setting
(PA1)
Average frequency deviation for
10101010 pattern
Average frequency deviation for
11110000 pattern
Eye opening = ΔF2AVG/ΔF1AVG
TBD
–
–
FTX, ACC
Frequency accuracy
–150
–
150
kHz
FTX, MAXDR
Maximum frequency drift
–50
–
50
kHz
FTX, INITDR
Initial frequency drift
–20
–
20
kHz
FTX, DR
Maximum drift rate
–20
–
20
In-band spurious emission at 2-MHz
offset
IBSE2
In-band spurious emission at ≥3-MHz
offset
TXSE1
Transmitter spurious emissions
(average), <1.0 GHz
TXSE2
Transmitter spurious emissions
(average), >1.0 GHz
RF Current Specifications
–
–
TBD
kHz/
50 µs
dBm
–
–
TBD
dBm
–
–
TBD
dBm
RF-PHY Specification
(TRM-LE/CA/05/C)
RF-PHY Specification
(TRM-LE/CA/05/C)
RF-PHY Specification
(TRM-LE/CA/05/C)
RF-PHY Specification
(TRM-LE/CA/06/C)
RF-PHY Specification
(TRM-LE/CA/06/C)
RF-PHY Specification
(TRM-LE/CA/06/C)
RF-PHY Specification
(TRM-LE/CA/06/C)
RF-PHY Specification
(TRM-LE/CA/03/C)
RF-PHY Specification
(TRM-LE/CA/03/C)
FCC-15.247
–
–
TBD
dBm
FCC-15.247
IRX
Receive current in normal mode
–
18.7
–
mA
Radio only
IRX_RF
Radio receive current in normal mode
–
16.4
–
mA
Radio only
IRX, HIGHGAIN
Receive current in high-gain mode
–
21.5
–
mA
Radio only
ITX, 3dBm
TX current at 3-dBm setting (PA10)
–
20
–
mA
Radio only
ITX, 0dBm
TX current at 0-dBm setting (PA7)
–
16.5
–
mA
Radio only
ITX_RF, 0dBm
Radio TX current at 0 dBm setting (PA7)
–
15.6
–
mA
Radio only
ITX_RF, 0dBm
–
14.2
–
mA
ITX,-3dBm
Radio TX current at 0 dBm excluding
Balun loss
TX current at –3-dBm setting (PA4)
–
15.5
–
mA
Guaranteed by design
simulation
Radio only
ITX,-6dBm
TX current at –6-dBm setting (PA3)
–
14.5
–
mA
Radio only
ITX,-12dBm
TX current at –12-dBm setting (PA2)
–
13.2
–
mA
Radio only
ITX,-18dBm
TX current at –18-dBm setting (PA1)
–
12.5
–
mA
Radio only
TXP, MIN
F2AVG
F1AVG
IBSE1
Document Number: 002-12524 PRELIMINARY
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CYBLE-224116-01
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Table 55. BLE Subsystem (continued)
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
TXP: +9.5 dBm; ±20-ppm
master and slave clock
accuracy.
For empty PDU exchange
PA/LNA active
TXP: +9.5 dBm; ±20-ppm
master and slave clock
accuracy.
For empty PDU exchange
PA/LNA active
Iavg_1sec, 0dBm
Average current at 1-second BLE
connection interval
–
26.3
–
µA
Iavg_4sec, 0dBm
Average current at 4-second BLE
connection interval
–
TBD
–
µA
2400
–
2482
MHz
General RF Specifications
FREQ
RF operating frequency
CHBW
Channel spacing
–
–
MHz
DR
On-air data rate
–
1000
–
kbps
IDLE2TX
BLE.IDLE to BLE. TX transition time
–
120
140
µs
IDLE2RX
BLE.IDLE to BLE. RX transition time
–
75
120
µs
RSSI, ACC
RSSI accuracy
–
±5
–
dB
RSSI, RES
RSSI resolution
–
–
dB
RSSI, PER
RSSI sample period
–
–
µs
RSSI Specifications
Document Number: 002-12524 PRELIMINARY
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CYBLE-224116-01
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Environmental Specifications
Environmental Compliance
This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF)
directives. The Cypress module and components used to produce this module are RoHS and HF compliant.
RF Certification
The CYBLE-224116-01 module is certified under the following RF certification standards:
FCC ID: WAP4110
CE
IC: 7922A-4110
MIC
KC
Environmental Conditions
Table 56 describes the operating and storage conditions for the Cypress BLE module.
Table 56. Environmental Conditions for CYBLE-224116-01
Description
Operating temperature
Operating humidity (relative, non-condensation)
Thermal ramp rate
Minimum Specification
Maximum Specification
-40 °C
105 °C
5%
85%
–
3 °C/minute
–40 °C
105 °C
Storage temperature and humidity
–
105 ° C at 85%
ESD: Module integrated into system
Components[6]
–
15 kV Air
2.2 kV Contact
Storage temperature
ESD and EMI Protection
Exposed components require special attention to ESD and electromagnetic interference (EMI).
A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure
near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground.
Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.
Note
6. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.
Document Number: 002-12524 PRELIMINARY
Page 32 of 42
PRELIMINARY
CYBLE-224116-01
Regulatory Information
FCC
FCC NOTICE:
The device CYBLE-224116-01 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter
approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device
may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause
undesired operation.
CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by
Cypress Semiconductor may void the user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.
If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment
off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help
LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible
label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well
as the FCC Notice above. The FCC identifier is FCC ID: WAP4110.
In any case the end product must be labeled exterior with "Contains FCC ID: WAP4110"
ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antennas listed in Table 7 on page 15. When integrated in the OEMs
product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna
not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for
emissions.
RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved
antenna in the previous.
The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas
in Table 7 on page 15, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal
instructions about the integrated radio module is not allowed.
The radiated output power of CYBLE-224116-01 is far below the FCC radio frequency exposure limits. Nevertheless, use
CYBLE-224116-01 in such a manner that minimizes the potential for human contact during normal operation.
End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with
transmitter operating conditions for satisfying RF exposure compliance.
Document Number: 002-12524 PRELIMINARY
Page 33 of 42
PRELIMINARY
CYBLE-224116-01
Industry Canada (IC) Certification
CYBLE-224116-01 is licensed to meet the regulatory requirements of Industry Canada (IC),
License: IC: 7922A-4110
Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure
compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from
www.ic.gc.ca.
This device has been designed to operate with the antennas listed in Table 7 on page 15, having a maximum gain of 0.5 dBi. Antennas
not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna
impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna
or transmitter.
IC NOTICE:
The device CYBLE-224116-01 complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter
approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful
interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.
IC RADIATION EXPOSURE STATEMENT FOR CANADA
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1)
this device may not cause interference, and (2) this device must accept any interference, including interference that may cause
undesired operation of the device.
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter
tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label
on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC
Notice above. The IC identifier is 7922A-4110. In any case, the end product must be labeled in its exterior with "Contains IC:
7922A-4110".
European R&TTE Declaration of Conformity
Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-224116-01 complies with the essential requirements and
other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the
Directive 1999/5/EC, the end-customer equipment should be labeled as follows:
All versions of the CYBLE-224116-01 in the specified reference design can be used in the following countries: Austria, Belgium,
Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.
Document Number: 002-12524 PRELIMINARY
Page 34 of 42
PRELIMINARY
CYBLE-224116-01
MIC Japan
CYBLE-224116-01 is certified as a module with type certification number TBD. End products that integrate CYBLE-224116-01 do not
need additional MIC Japan certification for the end product.
End product can display the certification label of the embedded module.
KC Korea
CYBLE-224116-01 is certified for use in Korea with certificate number TBD.
Document Number: 002-12524 PRELIMINARY
Page 35 of 42
CYBLE-224116-01
PRELIMINARY
Packaging
Table 57. Solder Reflow Peak Temperature
Module Part Number
Package
CYBLE-224116-01
32-pad SMT
Maximum Peak Temperature Maximum Time at PeakTemperature
260 °C
30 seconds
No. of Cycles
Table 58. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Module Part Number
Package
MSL
CYBLE-224116-01
32-pad SMT
MSL 3
Document Number: 002-12524 PRELIMINARY
Page 36 of 42
CYBLE-224116-01
PRELIMINARY
Ordering Information
The CYBLE-224116-01 part number and features are listed in the following table.
I2S (using UDB)
GPIO
Package
3 3
PWMs (using UDBs)
SCB Blocks
TCPWM Blocks
LP Comparators
Opamp (CTBm)
12-bit SAR ADC
UDB
32
Direct LCD Drive
Low Noise Amplifier (LNA)
256
CapSense
Power Amplier (PA)
48
SRAM (KB)
CYBLE-224116-01
Flash (KB)
MPN
Max CPU Speed (MHz)
Features
1 Msps
25
32-SMT
Part Numbering Convention
The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.
For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales
representative. To locate the nearest Cypress office, visit our website.
U.S. Cypress Headquarters Address
U.S. Cypress Headquarter Contact Info
Cypress website address
Document Number: 002-12524 PRELIMINARY
198 Champion Court, San Jose, CA 95134
(408) 943-2600
http://www.cypress.com
Page 37 of 42
CYBLE-224116-01
PRELIMINARY
Acronyms
Table 59. Acronyms Used in this Document
Acronym
Description
ABUS
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
Table 59. Acronyms Used in this Document (continued)
Acronym
Description
EMIF
external memory interface
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
ETM
embedded trace macrocell
ALU
arithmetic logic unit
FCC
Federal Communications Commission
AMUXBUS
analog multiplexer bus
FET
field-effect transistor
API
application programming interface
FIR
finite impulse response, see also IIR
APSR
application program status register
FPB
flash patch and breakpoint
®
advanced RISC machine, a CPU architecture
FS
full-speed
ATM
automatic thump mode
GPIO
BLE
Bluetooth Low Energy
general-purpose input/output, applies to a PSoC
pin
Bluetooth
SIG
Bluetooth Special Interest Group
HCI
host controller interface
HVI
high-voltage interrupt, see also LVI, LVD
BW
bandwidth
IC
integrated circuit
CAN
Controller Area Network, a communications
protocol
IDAC
current DAC, see also DAC, VDAC
CE
European Conformity
IDE
integrated development environment
CSA
Canadian Standards Association
ARM
2C,
or IIC
Inter-Integrated Circuit, a communications
protocol
CMRR
common-mode rejection ratio
IC
Industry Canada
CPU
central processing unit
IIR
infinite impulse response, see also FIR
CRC
cyclic redundancy check, an error-checking
protocol
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
I/O
input/output, see also GPIO, DIO, SIO, USBIO
IPOR
initial power-on reset
interrupt program status register
DAC
digital-to-analog converter, see also IDAC, VDAC
DFB
digital filter block
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
DMIPS
Dhrystone million instructions per second
IPSR
DMA
direct memory access, see also TD
IRQ
interrupt request
DNL
differential nonlinearity, see also INL
ITM
instrumentation trace macrocell
DNU
do not use
KC
Korea Certification
DR
port write data registers
LCD
liquid crystal display
DSI
digital system interconnect
LIN
Local Interconnect Network, a communications
protocol.
LNA
low noise amplifier
LR
link register
LUT
lookup table
DWT
data watchpoint and trace
ECC
error correcting code
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
EMI
electromagnetic interference
Document Number: 002-12524 PRELIMINARY
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
Page 38 of 42
CYBLE-224116-01
PRELIMINARY
Table 59. Acronyms Used in this Document (continued)
Acronym
Description
Table 59. Acronyms Used in this Document (continued)
Acronym
Description
LVTTL
low-voltage transistor-transistor logic
SC/CT
switched capacitor/continuous time
MAC
multiply-accumulate
SCL
I2C serial clock
MCU
microcontroller unit
SDA
I2C serial data
MIC
Ministry of Internal Affairs and Communications
(Japan)
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SMT
surface-mount technology; a method for
producing electronic circuitry in which the components are placed directly onto the surface of
PCBs
MISO
master-in slave-out
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
SOC
start of conversion
Opamp
operational amplifier
SOF
start of frame
PA
power amplifier
SPI
PAL
programmable array logic, see also PLD
Serial Peripheral Interface, a communications
protocol
PC
program counter
SR
slew rate
PCB
printed circuit board
SRAM
static random access memory
PGA
programmable gain amplifier
SRES
software reset
PHUB
peripheral hub
PHY
physical layer
PICU
port interrupt control unit
PLA
programmable logic array
PLD
programmable logic device, see also PAL
PLL
phase-locked loop
PMDD
package material declaration data sheet
POR
power-on reset
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
®
PSoC
Programmable System-on-Chip™
PSRR
power supply rejection ratio
STN
super twisted nematic
SWD
serial wire debug, a test protocol
SWV
single-wire viewer
TD
transaction descriptor, see also DMA
THD
total harmonic distortion
TIA
transimpedance amplifier
TN
twisted nematic
TRM
technical reference manual
TTL
transistor-transistor logic
TUV
Germany: Technischer Überwachungs-Verein
(Technical Inspection Association)
TX
transmit
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
PWM
pulse-width modulator
UDB
universal digital block
QDID
qualification design ID
USB
Universal Serial Bus
RAM
random-access memory
USBIO
RISC
reduced-instruction-set computing
USB input/output, PSoC pins used to connect to
a USB port
RMS
root-mean-square
VDAC
voltage DAC, see also DAC, IDAC
RTC
real-time clock
WDT
watchdog timer
RTL
register transfer language
WOL
write once latch, see also NVL
RTR
remote transmission request
RX
receive
SAR
successive approximation register
Document Number: 002-12524 PRELIMINARY
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Page 39 of 42
PRELIMINARY
CYBLE-224116-01
Document Conventions
Units of Measure
Table 60. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
dBm
decibel-milliwatts
fF
femtofarads
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
kΩ
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
MΩ
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
Ω
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
second
sps
samples per second
sqrtHz
square root of hertz
volt
Document Number: 002-12524 PRELIMINARY
Page 40 of 42
PRELIMINARY
CYBLE-224116-01
Document History Page
Document Title: CYBLE-224116-01 EZ-BLETM PSoC® XT/XR Module
Document Number: 002-12524
Revision
ECN
Orig. of
Change
PRELIMINARY
PRELIMINARY
DSO
Submission
Date
Description of Change
05/16/2016 Preliminary datasheet for CYBLE-224116-01 module.
Document Number: 002-12524 PRELIMINARY
Page 41 of 42
PRELIMINARY
CYBLE-224116-01
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/touch
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 002-12524 PRELIMINARY
Revised May 16, 2016
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 42 of 42

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Description                     : CYBLE-022001-00 Bluetooth?Low Energy (BLE) Module
Title                           : CYBLE-022001-00 Bluetooth®Low Energy (BLE) Module
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