Cypress Semiconductor 4110 Bluetooth Module User Manual CYBLE 224110 00 EZ BLE TM PSoC XT XR Module
Cypress Semiconductor Bluetooth Module CYBLE 224110 00 EZ BLE TM PSoC XT XR Module
Contents
- 1. User Manual
- 2. User Manual II
User Manual
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| Mirror Download [FCC.gov] | |
| Document ID | 3001048 |
| Application ID | iwhrc5YCg0Q+qBHWgSEuBA== |
| Document Description | User Manual |
| Short Term Confidential | No |
| Permanent Confidential | No |
| Supercede | No |
| Document Type | User Manual |
| Display Format | Adobe Acrobat PDF - pdf |
| Filesize | 127.82kB (1597779 bits) |
| Date Submitted | 2016-05-23 00:00:00 |
| Date Available | 2016-05-23 00:00:00 |
| Creation Date | 2016-05-16 20:29:43 |
| Producing Software | Acrobat Distiller 9.5.5 (Windows) |
| Document Lastmod | 2016-05-16 20:33:11 |
| Document Title | CYBLE-224110-00, EZ-BLE(TM) PSoC® XT/XR Module |
| Document Creator | FrameMaker 7.0 |
| Document Author: | Cypress Semiconductor |
PRELIMINARY
CYBLE-224110-00
EZ-BLE™ PSoC® XT/XR Module
General Description
The Cypress CYBLE-224110-00 is a fully certified and qualified
module supporting Bluetooth Low Energy (BLE) wireless
communication. The CYBLE-224110-00 is a turnkey solution
that includes onboard power amplifier (PA), low noise amplifier
(LNA), crystal oscillators, chip antenna, passive components,
and the Cypress PSoC® 4 BLE. Refer to the PSoC 4 BLE
datasheet for additional details on the capabilities of the PSoC 4
BLE device used on this module.
Low power mode support
p Deep Sleep: 1.3 µA with watch crystal oscillator (WCO) on
p Hibernate: 150 nA with SRAM retention
p Stop: 60 nA with XRES wakeup
Integrated PA/LNA
Supports output power up to +9.5 dBm and RXS of -95 dBm
The EZ-BLE PSoC® XT/XR module provides extended
industrial temperature operation (XT) and extended
communication range (XR). The EZ-BLE XT/XR module is a
scalable and reconfigurable platform architecture, combining
programmable and reconfigurable analog and digital blocks with
flexible automatic routing. The CYBLE-224110-00 also includes
digital programmable logic, high-performance analog-to-digital
conversion (ADC), opamps with comparator mode, and standard
communication and timing peripherals.
Programmable Analog
The CYBLE-224110-00 includes a royalty-free BLE stack
compatible with Bluetooth 4.1 and provides up to 25 GPIOs in a
small 9.5 × 15.4 × 1.80 mm footprint.
Module Description
Module size: 9.5 mm × 15.4 mm × 1.80 mm (with shield)
Extended Range: Up to 400 meters line-of-sight
Extended industrial temperature range: –40 °C to +105 °C
Up to 25 GPIOs
256-KB flash memory, 32-KB SRAM memory
Bluetooth 4.1 qualified single-mode module
Certified to FCC, CE, MIC, KC, and IC regulations
32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit
multiply, operating at up to 48 MHz
Watchdog timer with dedicated internal low-speed oscillator
Two-pin SWD for programming
Four opamps with reconfigurable high-drive external and
high-bandwidth internal drive, comparator modes, and ADC
input buffering capability; can operate in Deep-Sleep mode
12-bit, 1-Msps SAR ADC with differential and single-ended
modes; channel sequencer with signal averaging
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
One low-power comparator that operate in Deep-Sleep mode
Programmable Digital
Four programmable logic blocks called universal digital blocks,
(UDBs), each with eight macrocells and datapath
Cypress-provided peripheral Component library, user-defined
state machines, and Verilog input
Capacitive Sensing
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
SNR (> 5:1) and liquid tolerance
Cypress-supplied software component makes
capacitive-sensing design easy
Automatic hardware-tuning algorithm (SmartSense™)
Segment LCD Drive
LCD drive supported on all GPIOs (common or segment)
Operates in Deep-Sleep mode with four bits per pin memory
Serial Communication
Power Consumption
Two independent runtime reconfigurable serial communication
blocks (SCBs) with I2C, SPI, or UART functionality
TX output power: –18 dbm to +9.5 dbm
Timing and Pulse-Width Modulation
RX Receive Sensitivity: –95 dbm
Received signal strength indicator (RSSI) with 1-dB resolution
Four 16-bit timer, counter, pulse-width modulator (TCPWM)
blocks
1 Second connection interval with PA/LNA active: 26.3 µA
Center-aligned, Edge, and Pseudo-random modes
TX current consumption:
p BLE silicon: 15.6 mA (radio only, 0 dbm)
p SE2438T: 20 mA (PA/LNA only, +9.5 dBm)
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Up to 25 Programmable GPIOs
RX current consumption of 16.4 mA (radio only)
p BLE silicon: 16.4 mA (radio only)
p SE2438T: 5.5 mA (PA/LNA only)
Cypress Semiconductor Corporation
Document Number: 002-11264 Rev. *A
•
Any GPIO pin can be CapSense, LCD, analog, or digital
Two overvoltage-tolerant (OVT) pins; drive modes, strengths,
and slew rates are programmable
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 16, 2016
PRELIMINARY
CYBLE-224110-00
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to
quickly and effectively integrate the module into your design.
Overview: EZ-BLE Module Portfolio, Module Roadmap
EZ-BLE PSoC Product Overview
PSoC 4 BLE Silicon Datasheet
Application notes: Cypress offers a number of BLE application
notes covering a broad range of topics, from basic to advanced
level. Recommended application notes for getting started with
EZ-BLE modules are:
p AN96841 - Getting Started with EZ-BLE Module
®
p AN94020 - Getting Started with PSoC 4 BLE
®
p AN97060 - PSoC 4 BLE and PRoC™ BLE - Over-The-Air
(OTA) Device Firmware Upgrade (DFU) Guide
p AN91162 - Creating a BLE Custom Profile
p AN91184 - PSoC 4 BLE - Designing BLE Applications
p AN92584 - Designing for Low Power and Estimating Battery
Life for BLE Applications
®
®
p AN85951 - PSoC 4 CapSense Design Guide
®
p AN95089 - PSoC 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques
AN91445 - Antenna Design and RF Layout Guidelines
Technical Reference Manual (TRM):
®
p PSoC 4 BLE Technical Reference Manual
p PSOC(R) 4 BLE Registers Technical Reference Manual
(TRM)
Development Kits:
p CYBLE-224110-EVAL, CYBLE-224110-00 Evaluation Board
®
p CY8CKIT-042-BLE, Bluetooth Low Energy (BLE) Pioneer
Kit
®
p CY8CKIT-002, PSoC MiniProg3 Program and Debug Kit
Test and Debug Tools:
®
p CYSmart, Bluetooth LE Test and Debug Tool (Windows)
®
p CYSmart Mobile, Bluetooth LE Test and Debug Tool
(Android/iOS Mobile App)
PSoC® Creator™ Integrated Design Environment (IDE)
PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and
debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, PRoC BLE and EZ-BLE module systems with no code size limitations. PSoC
peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified,
production-ready PSoC Components™.
PSoC Components are analog and digital “virtual chips,” represented by an icon that users can drag-and-drop into a design and
configure to suit a broad array of application requirements.
Blutooth Low Energy Component
The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you
quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.1 compliant BLE protocol stack and
provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS)
hardware via the stack.
Technical Support
Frequently Asked Questions (FAQs): Learn more about our BLE ECO System.
Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums.
Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,
you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.
Document Number: 002-11264 Rev. *A
Page 2 of 43
PRELIMINARY
CYBLE-224110-00
Contents
Overview ............................................................................ 4
Module Description ...................................................... 4
Pad Connection Interface ................................................ 6
Recommended Host PCB Layout ................................... 8
Power Supply Connections and Recommended
External Components .................................................... 12
Connection Options ................................................... 12
External Component Recommendation .................... 12
Critical Components List ........................................... 15
Antenna Design ......................................................... 15
Electrical Specifications ................................................ 16
GPIO ......................................................................... 18
XRES ......................................................................... 19
Analog Peripherals .................................................... 20
Digital Peripherals ..................................................... 24
Serial Communication ............................................... 26
Memory ..................................................................... 27
System Resources .................................................... 27
Environmental Specifications ....................................... 33
Environmental Compliance ....................................... 33
RF Certification .......................................................... 33
Document Number: 002-11264 Rev. *A
Environmental Conditions ......................................... 33
ESD and EMI Protection ........................................... 33
Regulatory Information .................................................. 34
FCC ........................................................................... 34
Industry Canada (IC) Certification ............................. 35
European R&TTE Declaration of Conformity ............ 35
MIC Japan ................................................................. 36
KC Korea ................................................................... 36
Packaging ........................................................................ 37
Ordering Information ...................................................... 38
Part Numbering Convention ...................................... 38
Acronyms ........................................................................ 39
Document Conventions ................................................. 41
Units of Measure ....................................................... 41
Document History Page ................................................. 42
Sales, Solutions, and Legal Information ...................... 43
Worldwide Sales and Design Support ....................... 43
Products .................................................................... 43
PSoC® Solutions ...................................................... 43
Cypress Developer Community ................................. 43
Technical Support ..................................................... 43
Page 3 of 43
CYBLE-224110-00
PRELIMINARY
Overview
Module Description
The CYBLE-224110-00 is an integrated wireless module designed to be soldered to the main host board.
Module Dimensions and Drawing
Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE
module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should
be completed with the physical dimensions provided in the mechanical drawings (see Figure 1). All dimensions are in millimeters (mm).
Table 1. Module Design Dimensions
Dimension Item
Specification
Length (X)
9.50 ± 0.15 mm
Width (Y)
15.40 ± 0.15 mm
Length (X)
7.00 mm
Width (Y)
5.00 mm
PCB thickness
Height (H)
0.50 ± 0.10 mm
Shield height
Height (H)
1.10 ± 0.10 mm
Maximum component height
Height (H)
1.30 mm typical (chip antenna)
Total module thickness (bottom of module to highest component)
Height (H)
1.80 mm typical
Module dimensions
Antenna location dimensions
See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-224110-00.
Document Number: 002-11264 Rev. *A
Page 4 of 43
PRELIMINARY
CYBLE-224110-00
Figure 1. Module Mechanical Drawing
Top View
Side View
Bottom View
Note
1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on
recommended host PCB layout, see Figure 3 on page 7, Figure 4 and Figure 5 on page 8, Figure 6 and Table 3 on page 9.
Document Number: 002-11264 Rev. *A
Page 5 of 43
CYBLE-224110-00
PRELIMINARY
Pad Connection Interface
As shown in the bottom view of Figure 1, the CYBLE-224110-00 connects to the host board via solder pads on the back of the module.
Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-224110-00 module.
Table 2. Solder Pad Connection Description
Name
SP
Connection Connection Type
32
Solder Pads
Pad Length Dimension
Pad Width Dimension
Pad Pitch
0.71 mm
0.41 mm
0.76 mm
Figure 2. Solder Pad Dimensions (Bottom View)
Document Number: 002-11264 Rev. *A
Page 6 of 43
PRELIMINARY
CYBLE-224110-00
To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress BLE module is in a corner of the host board with the antenna located on the edge of the host
board. This placement minimizes the additional recommended keep-out area shown in item 2. Please refer to AN96841 for module
placement best practices.
2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional
keep-out area, where no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The
recommended dimensions of the host PCB keep-out area are shown in Figure 3 (dimensions are in mm).
Figure 3. Recommended Host PCB Keep-Out Area around CYBLE-224110-00 Trace Antenna
Host PCB Keep-Out Area around Trace Antenna
Document Number: 002-11264 Rev. *A
Page 7 of 43
PRELIMINARY
CYBLE-224110-00
Recommended Host PCB Layout
Figure 4 through Figure 6 and Table 3 provide details that can be used for the recommended host PCB layout pattern for the
CYBLE-224110-00. Dimensions are in millimeters unless otherwise noted. The minimum recommended host PCB pad length is 0.91
mm (0.455 mm from center of the pad to either side) is recommended as shown in Figure 6. The host PCB layout pattern can be
completed using either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern.
Figure 4. Host Layout Pattern for CYBLE-224110-00
Document Number: 002-11264 Rev. *A
Figure 5. Module Pad Location from Origin
Page 8 of 43
PRELIMINARY
CYBLE-224110-00
Table 3 provides the center location for each solder pad on the CYBLE-224110-00. All dimensions reference the to the center of the
solder pad. Figure 6 provides the location of each module solder pad.
Table 3. Module Solder Pad Location
Solder Pad
(Center of Pad)
Location (X,Y) from
Orign (mm)
Dimension from
Orign (mils)
(0.26, 3.37)
(10.24, 132.68)
(0.26, 4.13)
(10.24, 162.68)
(0.26, 4.89)
(10.24, 192.68)
(0.26, 5.66)
(10.24, 222.68)
(0.26, 6.42)
(10.24, 252.68)
(0.26, 7.18)
(10.24, 282.68)
(0.26, 7.94)
(10.24, 312.68)
(0.26, 8.70)
(10.24, 342.68)
(0.56, 15.14)
(22.05, 596.06)
10
(1.32,15.14)
(51.97, 596.06)
11
(2.08, 15.14)
(81.89, 596.06)
12
(2.84,15.14)
(111.81, 596.06)
13
(3.61, 15.14)
(142.13, 596.06)
14
(4.37, 15.14)
(172.13, 596.06)
15
(5.13, 15.14)
(202.13, 596.06)
16
(5.89, 15.14)
(231.89, 596.06)
17
(6.65,15.14)
(261.81, 596.06)
18
(7.42, 15.14)
(292.13, 596.06)
19
(8.18, 15.14)
(322.05, 596.06)
20
(8.94, 15.14)
(351.97, 596.06)
21
(9.24, 14.04)
(363.78, 552.76)
22
(9.24, 13.28)
(363.78, 522.83)
23
(9.24, 12.51)
(363.78,492.52)
24
(9.24, 11.75)
(363.78, 462.60)
25
(9.24,10.99)
(363.78, 432.68)
26
(9.24,10.23)
(363.78, 402.76)
27
(9.24, 9.47)
(363.78, 372.83)
28
(9.24, 8.70)
(363.78, 342.52)
29
(9.24, 7.94)
(363.78, 312.60)
30
(9.24, 7.18)
(363.78, 282.68)
31
(9.24, 6.42)
(363.78, 252.76)
32
(9.24,5.66)
(363.78, 222.83)
Document Number: 002-11264 Rev. *A
Figure 6. Solder Pad Reference Location
Page 9 of 43
CYBLE-224110-00
PRELIMINARY
Table 4 and Table 5 detail the solder pad connection definitions and available functions for each connection pad. Table 5 lists the
solder pads on CYBLE-224110-00, the BLE device port-pin, and denotes whether the digital function shown is available for each
solder pad. Table 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for
a single option shown with a 3.
Table 4. Digital Peripheral Capabilities
Pad
Number
Device
Port Pin
GND[3]
Ground Connection
XRES
External Reset Hardware Connection Input
P1.5
P1.1
P1.0
P0.1
P0.4
P0.5
P0.7
10
P1.3
11
VDDR
12
P0.6
3(SCB0_RTS) 3(SCB0_SS0)
3(TCPWM2_P)
13
P1.2
3(SCB1_SS2)
3(TCPWM1_P)
14
VDD
15
P1.4
16
P2.1
17
VDDA
18
P2.2
19
P2.6
20
P3.0
21
P2.3
22
VREF
23
P3.4
24
P3.5
25
P3.7
26
P3.1
27
P3.6
28
P2.5
29
P5.0
30
P5.1
31
P2.4
32
GND[3]
UART
SPI
I2 C
TCPWM[2]
Cap
Sense
WCO ECO
Out OUT
LCD
3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM2_N)
3(SCB1_SS1)
3(TCPWM0_N)
3(TCPWM0_P)
3(SCB1_TX) 3(SCB1_MISO) 3(SCB1_SCL) 3(TCPWM0_N)
3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM1_P)
3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM1_N)
3(SCB0_CTS) 3(SCB0_SCLK)
3(TCPWM2_N)
3(SCB1_SS3)
3(TCPWM1_N)
SWD
GPIO
(SWDCLK)
Radio Power Supply (2.0V to 3.6V)
(SWDIO)
Digital Power Supply Input (1.71 to 5.5V)
3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM2_P)
3(SCB0_SS2)
Analog Power Supply Input (1.71 to 5.5V)
3(SCB0_SS3)
3(SCB0_RX)
3(SCB0_SDA) 3(TCPWM0_P)
Reference Voltage Input
3(SCB1_RX)
3(SCB1_TX)
3(SCB1_CTS)
3(SCB0_TX)
3(SCB1_RTS)
3(SCB1_SDA) 3(TCPWM2_P)
3(SCB1_SCL) 3(TCPWM2_N)
3(TCPWM3_N)
3(SCB0_SCL) 3(TCPWM0_N)
3(TCPWM3_P)
3(SCB1_RX) 3(SCB1_SS0) 3(SCB1_SDA) 3(TCPWM3_P)
3(SCB1_TX) 3(SCB1_SCLK) 3(SCB1_SCL) 3(TCPWM3_N)
Document Number: 002-11264 Rev. *A
Ground Connection
Page 10 of 43
CYBLE-224110-00
PRELIMINARY
Table 5. Analog Peripheral Capabilities
Pad Number
Device Port Pin
SARMUX
[3]
GND
XRES
P1.5
P1.1
P1.0
P0.1
P0.4
P0.5
P0.7
10
P1.3
11
VDDR
12
P0.6
13
P1.2
14
VDD
15
P1.4
16
P2.1
17
VDDA
18
P2.2
19
P2.6
20
P3.0
21
P2.3
22
VREF
23
P3.4
24
P3.5
25
P3.7
26
P3.1
27
P3.6
28
P2.5
29
P5.0
30
P5.1
31
P2.4
32
GND
OPAMP
LPCOMP
Ground Connection
External Reset Hardware Connection Input
−
−
−
−
−
−
−
−
3(CTBm1_OA1_INP)
3(CTBm1_OA0_INN)
3(CTBm1_OA0_INP)
−
−
−
−
3(CTBm1_OA1_OUT)
−
−
−
3(COMP0_INN)
3(COMP1_INP)
3(COMP1_INN)
−
−
Radio Power Supply (2.0V to 3.6V)
−
−
−
3(CTBm1_OA0_OUT)
−
−
Digital Power Supply Input (1.71 to 5.5V)
−
−
3(CTBm1_OA1_INN)
3(CTBm1_OA0_INN)
−
−
Analog Power Supply Input (1.71 to 5.5V)
−
−
−
3(CTBm1_OA0_OUT)
3(CTBm1_OA0_INP)
−
3(CTBm1_OA1_OUT)
−
−
−
−
Reference Voltage Input (Optional)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3(CTBm0_OA1_INP)
−
−
3(CTBm0_OA1_INN)
−
−
−
−
Ground Connection
Notes
2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions.
3. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system.
Document Number: 002-11264 Rev. *A
Page 11 of 43
CYBLE-224110-00
PRELIMINARY
Power Supply Connections and Recommended External Components
Power Connections
Connection Options
The CYBLE-224110-00 contains three power supply
connections, VDD, VDDA, and VDDR. The VDD and VDDA
connections supply power for the digital and analog device
operation respectively. VDDR supplies power for the device
radio and PA/LNA.
Two connection options are available for any application:
1. Single supply: Connect VDD, VDDA, and VDDR to the same
supply.
2. Independent supply: Power VDD, VDDA, and VDDR
separately.
VDD and VDDA accept a supply range of 1.71V to 5.5V. VDDR
accepts a supply range of 2.0V to 3.6 V. These specifications can
be found in Table 12. The maximum power supply ripple for both
power connections on the module is 100 mV, as shown in
Table 10.
The power supply ramp rate of VDD and VDDA must be equal
to or greater than that of VDDR when the radio is used.
External Component Recommendation
In either connection scenario, it is recommended to place an
external ferrite bead between the supply and the module
connection. The ferrite bead should be positioned as close as
possible to the module pin connection.
Figure 7 details the recommended host schematic options for a
single supply scenario. The use of one or three ferrite beads will
depend on the specific application and configuration of the
CYBLE-224110-00.
Figure 8 details the recommended host schematic for an
independent supply scenario.
The recommended ferrite bead value is 330 Ω, 100 MHz (Murata
BLM21PG331SN1D).
Figure 7. Recommended Host Schematic Options for Single Supply Option
Single Ferrite Bead Option
Document Number: 002-11264 Rev. *A
Three Ferrite Bead Option
Page 12 of 43
PRELIMINARY
CYBLE-224110-00
Figure 8. Recommended Host Schematic for Independent Supply Option
Document Number: 002-11264 Rev. *A
Page 13 of 43
PRELIMINARY
CYBLE-224110-00
The CYBLE-224110-00 schematic is shown in Figure 9.
Figure 9. CYBLE-224110-00 Schematic Diagram
Document Number: 002-11264 Rev. *A
Page 14 of 43
CYBLE-224110-00
PRELIMINARY
Critical Components List
Table 6 provides the critical components used in the CYBLE-224110-00 module.
Table 6. Critical Component List
Component
Reference Designator
Description
Silicon
U1
76-pin WLCSP Programmable System-on-Chip (PSoC) with BLE
Crystal
Y1
24.000 MHz, 10PF
Crystal
Y2
32.768 kHz, 12.5PF
Antenna Design
Table 7 details the antenna used on the CYBLE-224110-00 module. The Cypress module performance improves many of these
characteristics. For more information, see Table 11.
Table 7. Chip Antenna Specifications
Item
Description
Chip Antenna Manufacturer
Johanson Technology Inc.
Chip Antenna Part Number
2450AT18B100
Frequency Range
2400 – 2500 MHz
Peak Gain
0.5 dBi typical
Average Gain
–0.5 dBi typical
Return Loss
9.5 dB minimum
Power Amplifier (PA) and Low Noise Amplifier (LNA)
Table 8 details the PA/LNA that is used on the CYBLE-224110-00 module. For more information, see Table 11.
Table 8. Power Amplifier/Low Noise Amplifier Details
Item
Description
PA/LNA Manufacturer
Skyworks Inc.
PA/LNA Part Number
SE2438T
Power Supply Range
2.0V ~ 3.6V
Table 9 details the power consumption of the integrated PA/LNA used on the CYBLE-224110-00 module. Table only details the current
consumption of the SE2438T PA/LNA. VCC = VCC1 = VCC2 = 3 V, TA = +25°C, measured on the SE2438T evaluation board, unless
otherwise noted.
Table 9. Power Amplifier/Low Noise Amplifier Current Consumption Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Total supply current ICC_Tx14
Tx mode POUT = +14 dBm
–
33
–
mA
Total supply current ICC_Tx12
Total supply current ICC_Tx10
Tx mode POUT = +12 dBm
–
25
–
mA
Tx mode POUT = +10 dBm
–
20
–
mA
No RF
–
–
mA
Total supply current ICC_RXHG
Rx Low Noise Amplifier (LNA) High Gain mode
–
5.5
–
mA
Total supply current ICC_RXLG
Total supply current ICC_RXBypass
Rx LNA Low Gain mode
–
2.7
–
mA
Rx Bypass mode
–
–
10
µA
Sleep supply current ICC_OFF
No RF
–
0.05
1.0
µA
Quiescent current
ICQ_Tx
Document Number: 002-11264 Rev. *A
Page 15 of 43
CYBLE-224110-00
PRELIMINARY
Electrical Specifications
Table 10 provides the absolute maximum electrical characteristics for the Cypress BLE module.
Table 10. CYBLE-224110-00 Absolute Maximum Ratings
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
VDDD_ABS
VDD or VDDA supply relative to VSS (VSSD = VSSA)
–0.5
–
Absolute maximum
VDDR_ABS
VDDR supply relative to VSS (VSSD = VSSA)
-0.3
–
3.6
Restricted by SE2438T
VCCD_ABS
Direct digital core voltage input relative to VSSD
–0.5
–
1.95
Absolute maximum
VDDD_RIPPLE
Maximum power supply ripple for VDD, VDDA and
VDDR input voltage
–
–
100
mV
3.0V supply
Ripple frequency of 100 kHz
to 750 kHz
VGPIO_ABS
GPIO voltage
–0.5
–
VDD +0.5
Absolute maximum
IGPIO_ABS
Maximum current per GPIO
–25
–
25
mA
Absolute maximum
IGPIO_injection
GPIO injection current: Maximum for VIH > VDD
and minimum for VIL < VSS
–0.5
–
0.5
mA
Absolute maximum current
injected per pin
LU
Pin current for latch up
–200
–
200
mA
–
Min
Typ
Max
Unit
Details/Conditions
Table 11 provides the RF characteristics for the Cypress BLE module.
Table 11. CYBLE-224110-00 RF Performance Characteristics
Parameter
Description
RFO1
RF output power on ANT
PA active
–8.5
9.5
dBm
Configurable through register
settings. PA active.
RFO2
RF output power on ANT
PA bypassed
-18
dBm
Configurable through register
settings. PA in bypass mode.
RXS1
RF receive sensitivity on ANT
LNA active
–
–95
–
dBm Measured value
RXS2
RF receive sensitivity on ANT
LNA bypassed
–
–87
–
dBm Measured value
FR
Module frequency range
2400
–
2480
MHz
–
GP
Peak gain
–
0.5
–
dBi
–
GAvg
Average gain
–
–0.5
–
dBi
–
RL
Return loss
–
–10
–
dB
–
Table 12 through Table 53 list the module level electrical characteristics for the CYBLE-224110-00. All specifications are valid for
–40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71V to 5.5V, except where noted.
Table 12. CYBLE-224110-00 DC Specifications
Parameter
Description
Min
Typ
Max
Unit
1.71
–
5.5
Details/Conditions
VDD1
Power supply input voltage (VDD = VDDA )
VDD2
Power supply input voltage unregulated (VDD =
VDDA)
1.71
1.8
1.89
Internally unregulated
supply
–
VDD3
Power supply input voltage (VDD = VDDA = VDDR)
2.0
–
3.6
Restricted by SE2438T
VDDR1
Radio supply voltage (radio on)
2.0
–
3.6
Restricted by SE2438T
VDDR2
Radio supply voltage (radio off)
2.0
–
3.6
–
1.7
–
mA
–
Active Mode, VDD = 1.71V to 5.5V
IDD3
Execute from flash; CPU at 3 MHz
Document Number: 002-11264 Rev. *A
T = 25 °C,
VDD = 3.3V
Page 16 of 43
CYBLE-224110-00
PRELIMINARY
Table 12. CYBLE-224110-00 DC Specifications (continued)
Min
Typ
Max
Unit
IDD4
Parameter
Execute from flash; CPU at 3 MHz
Description
–
–
–
mA
T = –40 °C to 85 °C
Details/Conditions
IDD5
Execute from flash; CPU at 6 MHz
–
2.5
–
mA
T = 25 °C,
VDD = 3.3V
IDD6
Execute from flash; CPU at 6 MHz
–
–
–
mA
T = –40 °C to 85 °C
IDD7
Execute from flash; CPU at 12 MHz
–
–
mA
T = 25 °C,
VDD = 3.3V
IDD8
Execute from flash; CPU at 12 MHz
–
–
–
mA
T = –40 °C to 85 °C
IDD9
Execute from flash; CPU at 24 MHz
–
7.1
–
mA
T = 25 °C,
VDD = 3.3V
IDD10
Execute from flash; CPU at 24 MHz
–
–
–
mA
T = –40 °C to 85 °C
IDD11
Execute from flash; CPU at 48 MHz
–
13.4
–
mA
T = 25 °C,
VDD = 3.3V
IDD12
Execute from flash; CPU at 48 MHz
–
–
–
mA
T = –40 °C to 85 °C
–
–
–
mA
T = 25 °C, VDD = 3.3V,
SYSCLK = 3 MHz
–
–
–
mA
T = 25 °C, VDD = 3.3V,
SYSCLK = 3 MHz
Sleep Mode, VDD = 1.71 to 5.5V
IDD13
IMO on
Sleep Mode, VDD and VDDR = 1.9 to 5.5V
IDD14
ECO on
Deep-Sleep Mode, VDD = 1.71 to 3.6V
IDD15
WDT with WCO on
–
1.3
–
µA
T = 25 °C,
VDD = 3.3V
IDD16
WDT with WCO on
–
–
–
µA
T = –40 °C to 85 °C
IDD17
WDT with WCO on
–
–
–
µA
T = 25 °C,
VDD = 5V
IDD18
WDT with WCO on
–
–
–
µA
T = –40 °C to 85 °C
Deep-Sleep Mode, VDD = 1.71 to 1.89V (Regulator Bypassed)
IDD19
WDT with WCO on
–
–
–
µA
T = 25 °C
IDD20
WDT with WCO on
–
–
–
µA
T = –40 °C to 85 °C
Hibernate Mode, VDD = 1.71 to 3.6V
IDD27
GPIO and reset active
–
150
–
nA
T = 25 °C,
VDD = 3.3V
IDD28
GPIO and reset active
–
–
–
nA
T = –40 °C to 85 °C
Hibernate Mode, VDD = 3.6 to 5.5V
IDD29
GPIO and reset active
–
–
–
nA
T = 25 °C,
VDD = 5V
IDD30
GPIO and reset active
–
–
–
nA
T = –40 °C to 85 °C
Stop Mode, VDD = 1.71 to 3.6V
IDD33
Stop-mode current (VDD)
–
20
–
nA
T = 25 °C,
VDD = 3.3V
IDD34
Stop-mode current (VDDR)
–
40
–-
nA
T = 25 °C,
VDDR = 3.3V
IDD35
Stop-mode current (VDD)
–
–
–
nA
T = –40 °C to 85 °C
Document Number: 002-11264 Rev. *A
Page 17 of 43
CYBLE-224110-00
PRELIMINARY
Table 12. CYBLE-224110-00 DC Specifications (continued)
Parameter
IDD36
Description
Min
Stop-mode current (VDDR)
Typ
Max
Unit
Details/Conditions
–
–
–
nA
T = –40 °C to 85 °C,
VDDR = 1.9V to 3.6V
Stop Mode, VDD = 3.6 to 5.5V
IDD37
Stop-mode current (VDD)
–
–
–
nA
T = 25 °C,
VDD = 5V
IDD38
Stop-mode current (VDDR)
–
–
–
nA
T = 25 °C,
VDDR = 5V
IDD39
Stop-mode current (VDD)
–
–
–
nA
T = –40 °C to 85 °C
IDD40
Stop-mode current (VDDR)
–
–
–
nA
T = –40 °C to 85 °C
Table 13. AC Specifications
Parameter
Description
Min
Typ
Max
Unit
DC
–
48
MHz
Wakeup from Sleep mode
–
–
µs
Guaranteed by characterization
TDEEPSLEEP
Wakeup from Deep-Sleep mode
–
–
25
µs
24-MHz IMO. Guaranteed by
characterization
THIBERNATE
Wakeup from Hibernate mode
–
–
800
µs
Guaranteed by characterization
TSTOP
Wakeup from Stop mode
–
–
ms
XRES wakeup
Min
Typ
Max
Unit
FCPU
CPU frequency
TSLEEP
Details/Conditions
1.71V ≤ VDD ≤ 5.5V
GPIO
Table 14. GPIO DC Specifications
Parameter
VIH[4]
Description
Input voltage HIGH threshold
0.7 × VDD
–
–
LVTTL input, VDD < 2.7V
0.7 × VDD
–
–
–
LVTTL input, VDD ≥ 2.7V
2.0
–
–
–
–
–
0.3 × VDD
Input voltage LOW threshold
VIL
VOH
VOL
Details/Conditions
CMOS input
CMOS input
LVTTL input, VDD < 2.7V
–
–
0.3 × VDD
–
LVTTL input, VDD ≥ 2.7V
–
–
0.8
–
Output voltage HIGH level
VDD –0.6
–
–
IOH = 4 mA at 3.3-V VDD
Output voltage HIGH level
VDD –0.5
–
–
IOH = 1 mA at 1.8-V VDD
Output voltage LOW level
–
–
0.6
IOL = 8 mA at 3.3-V VDD
Output voltage LOW level
–
–
0.6
IOL = 4 mA at 1.8-V VDD
Output voltage LOW level
–
–
0.4
IOL = 3 mA at 3.3-V VDD
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
–
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
IIL
Input leakage current (absolute value)
–
–
nA
IIL_CTBM
Input leakage on CTBm input pins
–
–
nA
–
CIN
Input capacitance
–
–
pF
–
VHYSTTL
Input hysteresis LVTTL
25
40
–
mV
–
25 °C, VDD = 3.3 V
VDD > 2.7 V
Note
4. VIH must not exceed VDD + 0.2V.
Document Number: 002-11264 Rev. *A
Page 18 of 43
CYBLE-224110-00
PRELIMINARY
Table 14. GPIO DC Specifications (continued)
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
0.05 × VDD
–
–
–
Current through protection diode to
VDD/VSS
–
–
100
µA
–
Maximum total source or sink chip
current
–
–
200
mA
–
VHYSCMOS
Input hysteresis CMOS
IDIODE
ITOT_GPIO
Table 15. GPIO AC Specifications
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
TRISEF
Rise time in Fast-Strong mode
–
12
ns
3.3-V VDDD, CLOAD = 25 pF
TFALLF
Fall time in Fast-Strong mode
–
12
ns
3.3-V VDDD, CLOAD = 25 pF
TRISES
Rise time in Slow-Strong mode
10
–
60
ns
3.3-V VDDD, CLOAD = 25 pF
TFALLS
Fall time in Slow-Strong mode
10
–
60
ns
3.3-V VDDD, CLOAD = 25 pF
FGPIOUT1
GPIO Fout; 3.3V ≤ VDD ≤ 5.5V
Fast-Strong mode
–
–
33
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT2
GPIO Fout; 1.7V≤ VDD ≤ 3.3V
Fast-Strong mode
–
–
16.7
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT3
GPIO Fout; 3.3V ≤ VDD ≤ 5.5V
Slow-Strong mode
–
–
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT4
GPIO Fout; 1.7V ≤ VDD ≤ 3.3V
Slow-Strong mode
–
–
3.5
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOIN
GPIO input operating frequency
1.71V ≤ VDD ≤ 5.5V
–
–
48
MHz
90/10% VIO
XRES
Table 16. XRES DC Specifications
Parameter
Description
VIH
Input voltage HIGH threshold
VIL
Input voltage LOW threshold
RPULLUP
Pull-up resistor
CIN
Min
Typ
Max
Unit
Details/Conditions
0.7 × VDDD
–
–
CMOS input
CMOS input
–
–
0.3 × VDDD
3.5
5.6
8.5
kΩ
–
Input capacitance
–
–
pF
–
VHYSXRES
Input voltage hysteresis
–
100
–
mV
–
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
–
Min
Typ
Max
Unit
Details/Conditions
–
–
µs
–
Table 17. XRES AC Specifications
Parameter
TRESETWIDTH
Description
Reset pulse width
Document Number: 002-11264 Rev. *A
Page 19 of 43
CYBLE-224110-00
PRELIMINARY
Analog Peripherals
Opamp
Table 18. Opamp Specifications
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
IDD (Opamp Block Current. VDD = 1.8V. No Load)
IDD_HI
Power = high
–
1000
1300
µA
–
IDD_MED
Power = medium
–
500
–
µA
–
IDD_LOW
Power = low
–
250
350
µA
–
GBW (Load = 20 pF, 0.1 mA. VDDA = 2.7V)
GBW_HI
Power = high
–
–
MHz
–
GBW_MED
Power = medium
–
–
MHz
–
GBW_LO
Power = low
–
–
MHz
–
IOUT_MAX (VDDA ≥ 2.7V, 500 mV from Rail)
IOUT_MAX_HI
Power = high
10
–
–
mA
–
IOUT_MAX_MID
Power = medium
10
–
–
mA
–
IOUT_MAX_LO
Power = low
–
–
mA
–
IOUT (VDDA = 1.71V, 500 mV from Rail)
IOUT_MAX_HI
Power = high
–
–
mA
–
IOUT_MAX_MID
Power = medium
–
–
mA
–
IOUT_MAX_LO
Power = low
–
–
mA
–
VIN
Charge pump on, VDDA ≥ 2.7V
–0.05
–
VDDA – 0.2
–
VCM
Charge pump on, VDDA ≥ 2.7V
–0.05
–
VDDA – 0.2
–
VOUT (VDDA ≥ 2.7V)
VOUT_1
Power = high, ILOAD = 10 mA
0.5
–
VDDA – 0.5
–
VOUT_2
Power = high, ILOAD = 1 mA
0.2
–
VDDA – 0.2
–
VOUT_3
Power = medium, ILOAD = 1 mA
0.2
–
VDDA – 0.2
–
VOUT_4
Power = low, ILOAD = 0.1 mA
0.2
–
VDDA – 0.2
–
VOS_TR
Offset voltage, trimmed
±0.5
mV
High mode
VOS_TR
Offset voltage, trimmed
–
±1
–
mV
Medium mode
VOS_TR
Offset voltage, trimmed
–
±2
–
mV
Low mode
VOS_DR_TR
Offset voltage drift, trimmed
–10
±3
10
µV/C
High mode
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
µV/C
Medium mode
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
µV/C
Low mode
CMRR
DC
65
70
–
dB
VDDD = 3.6V,
High-power mode
PSRR
At 1 kHz, 100-mV ripple
70
85
–
dB
VDDD = 3.6V
VN1
Input referred, 1 Hz–1 GHz, power = high
–
94
–
µVrms
–
VN2
Input referred, 1 kHz, power = high
–
72
–
nV/rtHz
–
VN3
Input referred, 10 kHz, power = high
–
28
–
nV/rtHz
–
VN4
Input referred, 100 kHz, power = high
–
15
–
nV/rtHz
–
Noise
Document Number: 002-11264 Rev. *A
Page 20 of 43
CYBLE-224110-00
PRELIMINARY
Table 18. Opamp Specifications (continued)
Parameter
Min
Typ
Max
Unit
Details/Conditions
CLOAD
Stable up to maximum load. Performance
specs at 50 pF
Description
–
–
125
pF
–
Slew_rate
Cload = 50 pF, Power = High,
VDDA ≥ 2.7V
–
–
V/µsec
–
T_op_wake
From disable to enable, no external RC
dominating
–
300
–
µsec
–
150
–
nsec
–
Comp_mode (Comparator Mode; 50-mV Drive, TRISE = TFALL (Approx.)
TPD1
Response time; power = high
–
TPD2
Response time; power = medium
–
400
–
nsec
–
TPD3
Response time; power = low
–
2000
–
nsec
–
Vhyst_op
Hysteresis
–
10
–
mV
–
Deep-Sleep Mode (Deep-Sleep mode operation is only guaranteed for VDDA > 2.5V)
GBW_DS
Gain bandwidth product
–
50
–
kHz
–
IDD_DS
Current
–
15
–
µA
–
Vos_DS
Offset voltage
–
–
mV
–
Vos_dr_DS
Offset voltage drift
–
20
–
µV/°C
–
Vout_DS
Output voltage
0.2
–
VDD–0.2
–
Vcm_DS
Common mode voltage
0.2
–
VDD–1.8
–
Min
Typ
Max
Unit
Details/Conditions
Table 19. Comparator DC Specifications
Parameter
Description
VOFFSET1
Input offset voltage, Factory trim
–
–
±10
mV
–
VOFFSET2
Input offset voltage, Custom trim
–
–
±6
mV
–
VOFFSET3
Input offset voltage, ultra-low-power mode
–
±12
–
mV
–
VHYST
Hysteresis when enabled
–
10
35
mV
–
VICM1
Input common mode voltage in normal mode
–
VDDD–0.1
VICM2
Input common mode voltage in low-power
mode
–
VDDD
–
VICM3
Input common mode voltage in ultra
low-power mode
–
VDDD–1.15
–
CMRR
Common mode rejection ratio
50
–
–
dB
VDDD ≥ 2.7V
CMRR
Common mode rejection ratio
42
–
–
dB
VDDD ≤ 2.7V
ICMP1
Block current, normal mode
–
–
400
µA
ICMP2
Block current, low-power mode
–
–
100
µA
–
ICMP3
Block current in ultra-low-power mode
–
–
µA
–
ZCMP
DC input impedance of comparator
35
–
–
MΩ
–
Document Number: 002-11264 Rev. *A
Modes 1 and 2
–
Page 21 of 43
CYBLE-224110-00
PRELIMINARY
Table 20. Comparator AC Specifications
Parameter
Min
Typ
Max
Unit
TRESP1
Response time, normal mode, 50-mV
overdrive
Description
Details/Conditions
–
38
–
ns
50-mV overdrive
TRESP2
Response time, low-power mode, 50-mV
overdrive
–
70
–
ns
50-mV overdrive
TRESP3
Response time, ultra-low-power mode,
50-mV overdrive
–
2.3
–
µs
200-mV overdrive
Min
Typ
Max
Unit
–5
±1
°C
Temperature Sensor
Table 21. Temperature Sensor Specifications
Parameter
TSENSACC
Description
Temperature-sensor accuracy
Details/Conditions
–40 to +85 °C
SAR ADC
Table 22. SAR ADC DC Specifications
Min
Typ
Max
Unit
Details/Conditions
A_RES
Parameter
Resolution
Description
–
–
12
bits
–
A_CHNIS_S
Number of channels - single-ended
–
–
–
8 full-speed
A-CHNKS_D
Number of channels - differential
–
–
–
Diff inputs use
neighboring I/O
A-MONO
Monotonicity
–
–
–
–
Yes
A_GAINERR
Gain error
–
–
±0.1
With external reference
A_OFFSET
Input offset voltage
–
–
mV
A_ISAR
Current consumption
–
–
mA
–
A_VINS
Input voltage range - single-ended
VSS
–
VDDA
–
A_VIND
Input voltage range - differential
VSS
–
VDDA
–
A_INRES
Input resistance
–
–
2.2
kΩ
–
A_INCAP
Input capacitance
–
–
10
pF
–
VREFSAR
Trimmed internal reference to SAR
–1
–
Min
Typ
Max
Unit
Measured with 1-V
VREF
Percentage of Vbg
(1.024 V)
Table 23. SAR ADC AC Specifications
Parameter
Description
Details/Conditions
Measured at 1-V
reference
A_PSRR
Power-supply rejection ratio
70
–
–
dB
A_CMRR
Common-mode rejection ratio
66
–
–
dB
–
A_SAMP
Sample rate
–
–
Msps
–
Fsarintref
SAR operating speed without external ref.
bypass
–
–
100
Ksps
A_SNR
Signal-to-noise ratio (SNR)
65
–
–
dB
FIN = 10 kHz
A_BW
Input bandwidth without aliasing
–
–
A_SAMP/2
kHz
–
A_INL
Integral nonlinearity. VDD = 1.71V to 5.5V, 1
Msps
–1.7
–
LSB
Document Number: 002-11264 Rev. *A
12-bit resolution
VREF = 1V to VDD
Page 22 of 43
CYBLE-224110-00
PRELIMINARY
Table 23. SAR ADC AC Specifications (continued)
Parameter
Description
Min
Typ
Max
Unit
A_INL
Integral nonlinearity. VDDD = 1.71V to 3.6V,
1 Msps
Details/Conditions
–1.5
–
1.7
LSB
VREF = 1.71V to VDD
A_INL
Integral nonlinearity. VDD = 1.71V to 5.5V,
500 Ksps
–1.5
–
1.7
LSB
VREF = 1V to VDD
A_dnl
Differential nonlinearity. VDD = 1.71V to 5.5V,
1 Msps
–1
–
2.2
LSB
VREF = 1V to VDD
A_DNL
Differential nonlinearity. VDD = 1.71V to 3.6V,
1 Msps
–1
–
LSB
VREF = 1.71V to VDD
A_DNL
Differential nonlinearity. VDD = 1.71V to 5.5V,
500 Ksps
–1
–
2.2
LSB
VREF = 1V to VDD
A_THD
Total harmonic distortion
–
–
–65
dB
Description
Min
Typ
Max
Unit
Details/Conditions
VCSD
Voltage range of operation
1.71
–
5.5
–
IDAC1
DNL for 8-bit resolution
–1
–
LSB
–
IDAC1
INL for 8-bit resolution
–3
–
LSB
–
IDAC2
DNL for 7-bit resolution
–1
–
LSB
–
IDAC2
INL for 7-bit resolution
–3
–
LSB
FIN = 10 kHz
CSD
Table 24. CSD Block Specifications
Parameter
SNR
Ratio of counts of finger to noise
–
–
Ratio
Capacitance range of
9 pF to 35 pF, 0.1-pF
sensitivity. Radio is not
operating during the
scan
IDAC1_CRT1
Output current of IDAC1 (8 bits) in High
range
–
612
–
µA
–
IDAC1_CRT2
Output current of IDAC1 (8 bits) in Low
range
–
306
–
µA
–
IDAC2_CRT1
Output current of IDAC2 (7 bits) in High
range
–
305
–
µA
–
IDAC2_CRT2
Output current of IDAC2 (7 bits) in Low
range
–
153
–
µA
–
Document Number: 002-11264 Rev. *A
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PRELIMINARY
Digital Peripherals
Timer
Table 25. Timer DC Specifications
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
ITIM1
Block current consumption at 3 MHz
–
–
42
µA
16-bit timer
ITIM2
Block current consumption at 12 MHz
–
–
130
µA
16-bit timer
ITIM3
Block current consumption at 48 MHz
–
–
535
µA
16-bit timer
Table 26. Timer AC Specifications
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
FCLK
–
48
MHz
–
Capture pulse width (internal)
2 × TCLK
–
–
ns
–
TCAPWEXT
Capture pulse width (external)
2 × TCLK
–
–
ns
–
TTIMRES
Timer resolution
TCLK
–
–
ns
–
TTENWIDINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
–
TTENWIDEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
–
TTIMRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
–
TTIMRESEXT
Reset pulse width (external)
2 × TCLK
–
–
ns
–
Min
Typ
Max
Unit
Details/Conditions
TTIMFREQ
Operating frequency
TCAPWINT
Counter
Table 27. Counter DC Specifications
Parameter
Description
ICTR1
Block current consumption at 3 MHz
–
–
42
µA
16-bit counter
ICTR2
Block current consumption at 12 MHz
–
–
130
µA
16-bit counter
ICTR3
Block current consumption at 48 MHz
–
–
535
µA
16-bit counter
Table 28. Counter AC Specifications
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
FCLK
–
48
MHz
–
Capture pulse width (internal)
2 × TCLK
–
–
ns
–
TCTRPWEXT
Capture pulse width (external)
2 × TCLK
–
–
ns
–
TCTRES
Counter Resolution
TCLK
–
–
ns
–
TCENWIDINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
–
TCENWIDEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
–
TCTRRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
–
TCTRRESWEXT
Reset pulse width (external)
2 × TCLK
–
–
ns
–
Details/Conditions
TCTRFREQ
Operating frequency
TCTRPWINT
Pulse Width Modulation (PWM)
Table 29. PWM DC Specifications
Parameter
Description
Min
Typ
Max
Unit
IPWM1
Block current consumption at 3 MHz
–
–
42
µA
16-bit PWM
IPWM2
Block current consumption at 12 MHz
–
–
130
µA
16-bit PWM
IPWM3
Block current consumption at 48 MHz
–
–
535
µA
16-bit PWM
Document Number: 002-11264 Rev. *A
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PRELIMINARY
Table 30. PWM AC Specifications
Min
Typ
Max
Unit
Details/Conditions
TPWMFREQ
Parameter
Operating frequency
Description
FCLK
–
48
MHz
–
TPWMPWINT
Pulse width (internal)
2 × TCLK
–
–
ns
–
TPWMEXT
Pulse width (external)
2 × TCLK
–
–
ns
–
TPWMKILLINT
Kill pulse width (internal)
2 × TCLK
–
–
ns
–
TPWMKILLEXT
Kill pulse width (external)
2 × TCLK
–
–
ns
–
TPWMEINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
–
TPWMENEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
–
TPWMRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
–
TPWMRESWEXT
Reset pulse width (external)
2 × TCLK
–
–
ns
–
LCD Direct Drive
Table 31. LCD Direct Drive DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SID228
ILCDLOW
Operating current in low-power mode
–
17.5
–
µA
16 × 4 small segment
display at 50 Hz
SID229
CLCDCAP
LCD capacitance per segment/common
driver
–
500
5000
pF
–
SID230
LCDOFFSET
Long-term segment offset
–
20
–
mV
–
SID231
ILCDOP1
LCD system operating current
VBIAS = 5V
–
–
mA
32 × 4 segments.
50 Hz at 25 °C
SID232
ILCDOP2
LCD system operating current
VBIAS = 3.3V
–
–
mA
32 × 4 segments
50 Hz at 25 °C
Min
Typ
Max
Unit
Details/Conditions
10
50
150
Hz
–
Table 32. LCD Direct Drive AC Specifications
Spec ID
SID233
Parameter
FLCD
Description
LCD frame rate
Document Number: 002-11264 Rev. *A
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PRELIMINARY
Serial Communication
Table 33. Fixed I2C DC Specifications
Parameter
Description
II2C1
Block current consumption at 100 kHz
II2C2
Block current consumption at 400 kHz
II2C3
Block current consumption at 1 Mbps
II2C4
I C enabled in Deep-Sleep mode
Min
Typ
Max
Unit
Details/Conditions
–
–
50
µA
–
–
–
155
µA
–
–
–
390
µA
–
–
–
1.4
µA
–
Min
Typ
Max
Unit
Details/Conditions
–
–
400
kHz
Table 34. Fixed I2C AC Specifications
Parameter
FI2C1
Description
Bit rate
Table 35. Fixed UART DC Specifications
Min
Typ
Max
Unit
Details/Conditions
IUART1
Parameter
Block current consumption at 100 kbps
Description
–
–
55
µA
–
IUART2
Block current consumption at 1000 kbps
–
–
312
µA
–
Min
Typ
Max
Unit
Details/Conditions
–
–
Mbps
–
Min
Typ
Max
Unit
Details/Conditions
Table 36. Fixed UART AC Specifications
Parameter
FUART
Description
Bit rate
Table 37. Fixed SPI DC Specifications
Parameter
Description
ISPI1
Block current consumption at 1 Mbps
–
–
360
µA
–
ISPI2
Block current consumption at 4 Mbps
–
–
560
µA
–
ISPI3
Block current consumption at 8 Mbps
–
–
600
µA
–
Description
Min
Typ
Max
Unit
Details/Conditions
SPI operating frequency (master; 6x over sampling)
–
–
MHz
–
Min
Typ
Max
Unit
Details/Conditions
–
Table 38. Fixed SPI AC Specifications
Parameter
FSPI
Table 39. Fixed SPI Master Mode AC Specifications
Parameter
Description
TDMO
MOSI valid after SCLK driving edge
–
–
18
ns
TDSI
MISO valid before SCLK capturing edge
Full clock, late MISO sampling used
20
–
–
ns
Full clock, late MISO sampling
THMO
Previous MOSI data hold time
–
–
ns
Referred to Slave capturing edge
Table 40. Fixed SPI Slave Mode AC Specifications
Min
Typ
Max
Unit
TDMI
Parameter
MOSI valid before SCLK capturing edge
Description
40
–
–
ns
TDSO
MISO valid after SCLK driving edge
–
–
42 + 3 × TCPU
ns
TDSO_ext
MISO Valid after SCLK driving edge in
external clock mode. VDD < 3.0V
–
–
50
ns
THSO
Previous MISO data hold time
–
–
ns
Document Number: 002-11264 Rev. *A
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Table 40. Fixed SPI Slave Mode AC Specifications (continued)
Parameter
TSSELSCK
Description
SSEL valid to first SCK valid edge
Min
Typ
Max
Unit
100
–
–
ns
Memory
Table 41. Flash DC Specifications
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
1.71
–
5.5
–
VPE
Erase and program voltage
TWS48
Number of Wait states at 32–48 MHz
–
–
–
CPU execution from flash
TWS32
Number of Wait states at 16–32 MHz
–
–
–
CPU execution from flash
TWS16
Number of Wait states for 0–16 MHz
–
–
–
CPU execution from flash
Min
Typ
Max
Unit
Table 42. Flash AC Specifications
Parameter
Description
Details/Conditions
TROWWRITE[5]
TROWERASE[5]
Row (block) write time (erase and program)
–
–
20
ms
Row erase time
–
–
13
ms
TROWPROGRAM[5]
TBULKERASE[5]
TDEVPROG[5]
Row program time after erase
–
–
ms
–
Bulk erase time (256 KB)
–
–
35
ms
–
Total device program time
–
–
25
seconds
–
FEND
Flash endurance
100 K
–
–
cycles
–
FRET
Flash retention. TA ≤ 55 °C, 100 K P/E cycles
20
–
–
years
–
FRET2
Flash retention. TA ≤ 85 °C, 10 K P/E cycles
10
–
–
years
–
Min
Typ
Max
Unit
Details/Conditions
Row (block) = 256 bytes
–
System Resources
Power-on-Reset (POR)
Table 43. POR DC Specifications
Parameter
Description
VRISEIPOR
Rising trip voltage
0.80
–
1.45
–
VFALLIPOR
Falling trip voltage
0.75
–
1.40
–
VIPORHYST
Hysteresis
15
–
200
mV
–
Min
Typ
Max
Unit
Details/Conditions
–
–
µs
–
Description
Min
Typ
Max
Unit
Details/Conditions
VFALLPPOR
BOD trip voltage in Active and Sleep modes
1.64
–
–
–
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.4
–
–
–
Table 44. POR AC Specifications
Parameter
TPPOR_TR
Description
Precision power-on reset (PPOR) response
time in Active and Sleep modes
Table 45. Brown-Out Detect
Parameter
Note
5. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have
completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make
certain that these are not inadvertently activated.
Document Number: 002-11264 Rev. *A
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Table 46. Hibernate Reset
Parameter
VHBRTRIP
Description
BOD trip voltage in Hibernate
Min
Typ
Max
Unit
Details/Conditions
1.1
–
–
–
Min
Typ
Max
Unit
Details/Conditions
Voltage Monitors (LVD)
Table 47. Voltage Monitor DC Specifications
Parameter
Description
VLVI1
LVI_A/D_SEL[3:0] = 0000b
1.71
1.75
1.79
–
VLVI2
LVI_A/D_SEL[3:0] = 0001b
1.76
1.80
1.85
–
VLVI3
LVI_A/D_SEL[3:0] = 0010b
1.85
1.90
1.95
–
VLVI4
LVI_A/D_SEL[3:0] = 0011b
1.95
2.00
2.05
–
VLVI5
LVI_A/D_SEL[3:0] = 0100b
2.05
2.10
2.15
–
VLVI6
LVI_A/D_SEL[3:0] = 0101b
2.15
2.20
2.26
–
VLVI7
LVI_A/D_SEL[3:0] = 0110b
2.24
2.30
2.36
–
VLVI8
LVI_A/D_SEL[3:0] = 0111b
2.34
2.40
2.46
–
VLVI9
LVI_A/D_SEL[3:0] = 1000b
2.44
2.50
2.56
–
VLVI10
LVI_A/D_SEL[3:0] = 1001b
2.54
2.60
2.67
–
VLVI11
LVI_A/D_SEL[3:0] = 1010b
2.63
2.70
2.77
–
VLVI12
LVI_A/D_SEL[3:0] = 1011b
2.73
2.80
2.87
–
VLVI13
LVI_A/D_SEL[3:0] = 1100b
2.83
2.90
2.97
–
VLVI14
LVI_A/D_SEL[3:0] = 1101b
2.93
3.00
3.08
–
VLVI15
LVI_A/D_SEL[3:0] = 1110b
3.12
3.20
3.28
–
VLVI16
LVI_A/D_SEL[3:0] = 1111b
4.39
4.50
4.61
–
LVI_IDD
Block current
–
–
100
µA
–
Min
Typ
Max
Unit
Details/Conditions
–
–
µs
–
Table 48. Voltage Monitor AC Specifications
Parameter
TMONTRIP
Description
Voltage monitor trip time
SWD Interface
Table 49. SWD Interface Specifications
Min
Typ
Max
Unit
Details/Conditions
F_SWDCLK1
Parameter
3.3V ≤ VDD ≤ 5.5V
Description
–
–
14
MHz
SWDCLK ≤ 1/3 CPU clock frequency
F_SWDCLK2
1.71V ≤ VDD ≤ 3.3V
–
–
MHz
SWDCLK ≤ 1/3 CPU clock frequency
T_SWDI_SETUP T = 1/f SWDCLK
0.25 × T
–
–
ns
–
T_SWDI_HOLD
0.25 × T
–
–
ns
–
T_SWDO_VALID T = 1/f SWDCLK
T = 1/f SWDCLK
–
–
0.5 × T
ns
–
T_SWDO_HOLD
–
–
ns
–
T = 1/f SWDCLK
Document Number: 002-11264 Rev. *A
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Internal Main Oscillator
Table 50. IMO DC Specifications
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
IIMO1
IMO operating current at 48 MHz
–
–
1000
µA
–
IIMO2
IMO operating current at 24 MHz
–
–
325
µA
–
IIMO3
IMO operating current at 12 MHz
–
–
225
µA
–
IIMO4
IMO operating current at 6 MHz
–
–
180
µA
–
IIMO5
IMO operating current at 3 MHz
–
–
150
µA
–
Min
Typ
Max
Unit
Details/Conditions
Table 51. IMO AC Specifications
Parameter
Description
FIMOTOL3
Frequency variation from 3 to 48 MHz
–
–
±2
With API-called calibration
FIMOTOL3
IMO startup time
–
12
–
µs
–
Min
Typ
Max
Unit
Details/Conditions
–
0.3
1.05
µA
–
Min
Typ
Max
Unit
Details/Conditions
Internal Low-Speed Oscillator
Table 52. ILO DC Specifications
Parameter
Description
ILO operating current at 32 kHz
IILO2
Table 53. ILO AC Specifications
Parameter
Description
TSTARTILO1
ILO startup time
–
–
ms
–
FILOTRIM1
32-kHz trimmed frequency
15
32
50
kHz
–
Table 54. ECO Trim Value Specification
Parameter
ECOTRIM
Description
24-MHz trim value
(firmware configuration)
Value
Details/Conditions
0x00003FFA
Optimum trim value that needs to be loaded to register
CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG
Table 55. UDB AC Specifications
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
FMAX-TIMER
Max frequency of 16-bit timer in a UDB
pair
–
–
48
MHz
–
FMAX-ADDER
Max frequency of 16-bit adder in a UDB
pair
–
–
48
MHz
–
FMAX_CRC
Max frequency of 16-bit CRC/PRS in a
UDB pair
–
–
48
MHz
–
–
–
48
MHz
–
–
15
–
ns
–
Data Path Performance
PLD Performance in UDB
FMAX_PLD
Max frequency of 2-pass PLD function
in a UDB pair
Clock to Output Performance
TCLK_OUT_UDB1
Prop. delay for clock in to data out at
25 °C, Typical
Document Number: 002-11264 Rev. *A
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Table 55. UDB AC Specifications (continued)
Parameter
TCLK_OUT_UDB2
Description
Prop. delay for clock in to data out,
Worst case
Min
Typ
Max
Unit
Details/Conditions
–
25
–
ns
–
Min
Typ
Max
Unit
Table 56. BLE Subsystem
Parameter
Description
Details/Conditions
RF Receiver Specification
RXS, DIRTY
RX sensitivity with dirty transmitter
–
–95
–
dBm
With LNA active
RXS, LOWGAIN
RX sensitivity in low-gain mode with idle
transmitter
–
–87
–
dBm
LNA in bypass mode
RXS, HIGHGAIN
RX sensitivity in high-gain mode with idle
transmitter
–
–95
–
dBm
With LNA active
PRXMAX
Maximum input power
–10
–1
–
dBm
RF-PHY Specification
(RCV-LE/CA/06/C)
CI1
Cochannel interference,
Wanted signal at –67 dBm and Interferer
at FRX
–
21
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI2
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±1 MHz
–
TBD
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI3
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±2 MHz
–
TBD
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI4
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at ≥FRX ±3 MHz
–
TBD
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI5
Adjacent channel interference
Wanted Signal at –67 dBm and Interferer
at Image frequency (FIMAGE)
–
TBD
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI3
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at Image frequency (FIMAGE ± 1 MHz)
–
TBD
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
OBB1
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 30–2000 MHz
–
TBD
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
OBB2
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 2003–2399 MHz
–
TBD
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
OBB3
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 2484–2997 MHz
–
TBD
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
OBB4
Out-of-band blocking,
Wanted signal a –67 dBm and Interferer
at F = 3000–12750 MHz
–
TBD
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
IMD
Intermodulation performance
Wanted signal at –64 dBm and 1-Mbps
BLE, third, fourth, and fifth offset channel
–
TBD
dBm
RF-PHY Specification
(RCV-LE/CA/05/C)
Document Number: 002-11264 Rev. *A
–
–
–
–
–
–
–
–
–
–
Page 30 of 43
CYBLE-224110-00
PRELIMINARY
Table 56. BLE Subsystem (continued)
Parameter
Description
Min
Typ
RXSE1
Receiver spurious emission
30 MHz to 1.0 GHz
–
TBD
RXSE2
Receiver spurious emission
1.0 GHz to 12.75 GHz
–
TBD
Max
–
–
Unit
Details/Conditions
dBm
100-kHz measurement
bandwidth
ETSI EN300 328 V1.8.1
dBm
1-MHz measurement
bandwidth
ETSI EN300 328 V1.8.1
RF Transmitter Specifications
TXP, ACC
RF power accuracy
–
±1
–
dB
–
TXP, RANGE
RF power control range
–
30
–
dB
–
TXP, 0dBm
Output power, 0-dB Gain setting (PA7)
–
–
-6
dBm
–
TXP, MAX
Output power, maximum power setting
(PA10)
–
9.5
–
dBm
TXP, MIN
Output power, minimum power setting
(PA1)
–
–18
–
dBm
F2AVG
Average frequency deviation for
10101010 pattern
185
–
–
kHz
RF-PHY Specification
(TRM-LE/CA/05/C)
F1AVG
Average frequency deviation for
11110000 pattern
225
250
275
kHz
RF-PHY Specification
(TRM-LE/CA/05/C)
EO
Eye opening = ΔF2AVG/ΔF1AVG
TBD
–
–
FTX, ACC
Frequency accuracy
–150
–
150
kHz
RF-PHY Specification
(TRM-LE/CA/06/C)
FTX, MAXDR
Maximum frequency drift
–50
–
50
kHz
RF-PHY Specification
(TRM-LE/CA/06/C)
FTX, INITDR
Initial frequency drift
–20
–
20
kHz
RF-PHY Specification
(TRM-LE/CA/06/C)
FTX, DR
Maximum drift rate
–20
–
20
kHz/
50 µs
RF-PHY Specification
(TRM-LE/CA/06/C)
IBSE1
In-band spurious emission at 2-MHz
offset
–
–
TBD
dBm
RF-PHY Specification
(TRM-LE/CA/03/C)
IBSE2
In-band spurious emission at ≥3-MHz
offset
–
–
TBD
dBm
RF-PHY Specification
(TRM-LE/CA/03/C)
TXSE1
Transmitter spurious emissions
(average), <1.0 GHz
–
–
TBD
dBm
FCC-15.247
TXSE2
Transmitter spurious emissions
(average), >1.0 GHz
–
–
TBD
dBm
FCC-15.247
–
–
RF-PHY Specification
(TRM-LE/CA/05/C)
RF Current Specifications
IRX
Receive current in normal mode
–
18.7
–
mA
Radio only
IRX_RF
Radio receive current in normal mode
–
16.4
–
mA
Radio only
IRX, HIGHGAIN
Receive current in high-gain mode
–
21.5
–
mA
Radio only
ITX, 3dBm
TX current at 3-dBm setting (PA10)
–
20
–
mA
Radio only
ITX, 0dBm
TX current at 0-dBm setting (PA7)
–
16.5
–
mA
Radio only
ITX_RF, 0dBm
Radio TX current at 0 dBm setting (PA7)
–
15.6
–
mA
Radio only
Document Number: 002-11264 Rev. *A
Page 31 of 43
CYBLE-224110-00
PRELIMINARY
Table 56. BLE Subsystem (continued)
Parameter
Description
Min
Typ
Unit
Details/Conditions
–
mA
Guaranteed by design
simulation
15.5
–
mA
Radio only
–
14.5
–
mA
Radio only
TX current at –12-dBm setting (PA2)
–
13.2
–
mA
Radio only
ITX,-18dBm
TX current at –18-dBm setting (PA1)
–
12.5
–
mA
Radio only
Iavg_1sec, 0dBm
Average current at 1-second BLE
connection interval
µA
TXP: +9.5 dBm; ±20-ppm
master and slave clock
accuracy.
For empty PDU exchange
PA/LNA active
ITX_RF, 0dBm
Radio TX current at 0 dBm excluding
Balun loss
–
14.2
ITX,-3dBm
TX current at –3-dBm setting (PA4)
–
ITX,-6dBm
TX current at –6-dBm setting (PA3)
ITX,-12dBm
Iavg_4sec, 0dBm
Average current at 4-second BLE
connection interval
–
26.3
Max
–
–
TBD
–
µA
TXP: +9.5 dBm; ±20-ppm
master and slave clock
accuracy.
For empty PDU exchange
PA/LNA active
2400
–
2482
MHz
–
General RF Specifications
FREQ
RF operating frequency
CHBW
Channel spacing
–
–
MHz
–
DR
On-air data rate
–
1000
–
kbps
–
IDLE2TX
BLE.IDLE to BLE. TX transition time
–
120
140
µs
–
IDLE2RX
BLE.IDLE to BLE. RX transition time
–
75
120
µs
–
RSSI, ACC
RSSI accuracy
–
±5
–
dB
–
RSSI, RES
RSSI resolution
–
–
dB
–
RSSI, PER
RSSI sample period
–
–
µs
–
RSSI Specifications
Document Number: 002-11264 Rev. *A
Page 32 of 43
CYBLE-224110-00
PRELIMINARY
Environmental Specifications
Environmental Compliance
This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF)
directives. The Cypress module and components used to produce this module are RoHS and HF compliant.
RF Certification
The CYBLE-224110-00 module is certified under the following RF certification standards:
FCC ID: WAP4110
CE
IC: 7922A-4110
MIC
KC
Environmental Conditions
Table 57 describes the operating and storage conditions for the Cypress BLE module.
Table 57. Environmental Conditions for CYBLE-224110-00
Description
Operating temperature
Operating humidity (relative, non-condensation)
Minimum Specification
Maximum Specification
–40 °C
105 °C
5%
85%
–
3 °C/minute
–40 °C
105 °C
Storage temperature and humidity
–
105 ° C at 85%
ESD: Module integrated into system Components[6]
–
15 kV Air
2.2 kV Contact
Thermal ramp rate
Storage temperature
ESD and EMI Protection
Exposed components require special attention to ESD and electromagnetic interference (EMI).
A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure
near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground.
Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.
Note
6. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.
Document Number: 002-11264 Rev. *A
Page 33 of 43
PRELIMINARY
CYBLE-224110-00
Regulatory Information
FCC
FCC NOTICE:
The device CYBLE-224110-00 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter
approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device
may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause
undesired operation.
CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by
Cypress Semiconductor may void the user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.
If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment
off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help
LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible
label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well
as the FCC Notice above. The FCC identifier is FCC ID: WAP4110.
In any case the end product must be labeled exterior with "Contains FCC ID: WAP4110"
ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antennas listed in Table 7 on page 15. When integrated in the OEMs
product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna
not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for
emissions.
RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved
antenna in the previous.
The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas
in Table 7 on page 15, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal
instructions about the integrated radio module is not allowed.
The radiated output power of CYBLE-224110-00 is far below the FCC radio frequency exposure limits. Nevertheless, use
CYBLE-224110-00 in such a manner that minimizes the potential for human contact during normal operation.
End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with
transmitter operating conditions for satisfying RF exposure compliance.
Document Number: 002-11264 Rev. *A
Page 34 of 43
PRELIMINARY
CYBLE-224110-00
Industry Canada (IC) Certification
CYBLE-224110-00 is licensed to meet the regulatory requirements of Industry Canada (IC),
License: IC: 7922A-4110
Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure
compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from
www.ic.gc.ca.
This device has been designed to operate with the antennas listed in Table 7 on page 15, having a maximum gain of 0.5 dBi. Antennas
not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna
impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna
or transmitter.
IC NOTICE:
The device CYBLE-224110-00 complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter
approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful
interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.
IC RADIATION EXPOSURE STATEMENT FOR CANADA
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1)
this device may not cause interference, and (2) this device must accept any interference, including interference that may cause
undesired operation of the device.
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter
tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label
on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC
Notice above. The IC identifier is 7922A-4110. In any case, the end product must be labeled in its exterior with "Contains IC:
7922A-4110".
European R&TTE Declaration of Conformity
Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-224110-00 complies with the essential requirements and
other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the
Directive 1999/5/EC, the end-customer equipment should be labeled as follows:
All versions of the CYBLE-224110-00 in the specified reference design can be used in the following countries: Austria, Belgium,
Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.
Document Number: 002-11264 Rev. *A
Page 35 of 43
PRELIMINARY
CYBLE-224110-00
MIC Japan
CYBLE-224110-00 is certified as a module with type certification number TBD. End products that integrate CYBLE-224110-00 do not
need additional MIC Japan certification for the end product.
End product can display the certification label of the embedded module.
KC Korea
CYBLE-224110-00 is certified for use in Korea with certificate number TBD.
Document Number: 002-11264 Rev. *A
Page 36 of 43
CYBLE-224110-00
PRELIMINARY
Packaging
Table 58. Solder Reflow Peak Temperature
Module Part Number
Package
CYBLE-224110-00
32-pad SMT
Maximum Peak Temperature Maximum Time at PeakTemperature
260 °C
30 seconds
No. of Cycles
Table 59. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Module Part Number
Package
MSL
CYBLE-224110-00
32-pad SMT
MSL 3
Document Number: 002-11264 Rev. *A
Page 37 of 43
CYBLE-224110-00
PRELIMINARY
Ordering Information
Table 60 lists the CYBLE-224110-00 part number and features.
Table 60. Ordering Information
I2S (using UDB)
GPIO
Package
3 3
PWMs (using UDBs)
SCB Blocks
TCPWM Blocks
LP Comparators
Opamp (CTBm)
12-bit SAR ADC
UDB
32
Direct LCD Drive
Low Noise Amplifier (LNA)
256
CapSense
Power Amplier (PA)
48
SRAM (KB)
CYBLE-224110-00
Flash (KB)
MPN
Max CPU Speed (MHz)
Features
1 Msps
25
32-SMT
Part Numbering Convention
The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.
For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales
representative. To locate the nearest Cypress office, visit our website.
U.S. Cypress Headquarters Address
U.S. Cypress Headquarter Contact Info
Cypress website address
Document Number: 002-11264 Rev. *A
198 Champion Court, San Jose, CA 95134
(408) 943-2600
http://www.cypress.com
Page 38 of 43
CYBLE-224110-00
PRELIMINARY
Acronyms
Table 61. Acronyms Used in this Document
Acronym
Description
ABUS
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus, an ARM data
transfer bus
ALU
arithmetic logic unit
Table 61. Acronyms Used in this Document (continued)
Acronym
Description
EMIF
external memory interface
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
ETM
embedded trace macrocell
FCC
Federal Communications Commission
AMUXBUS analog multiplexer bus
FET
field-effect transistor
API
application programming interface
FIR
finite impulse response, see also IIR
APSR
application program status register
FPB
flash patch and breakpoint
ARM®
advanced RISC machine, a CPU architecture
FS
full-speed
ATM
automatic thump mode
BLE
Bluetooth Low Energy
GPIO
general-purpose input/output, applies to a PSoC
pin
Bluetooth
SIG
Bluetooth Special Interest Group
HCI
host controller interface
HVI
high-voltage interrupt, see also LVI, LVD
BW
bandwidth
IC
integrated circuit
CAN
Controller Area Network, a communications
protocol
IDAC
current DAC, see also DAC, VDAC
CE
European Conformity
IDE
integrated development environment
CSA
Canadian Standards Association
CMRR
common-mode rejection ratio
CPU
central processing unit
CRC
cyclic redundancy check, an error-checking
protocol
DAC
digital-to-analog converter, see also IDAC, VDAC
INL
integral nonlinearity, see also DNL
DFB
digital filter block
I/O
input/output, see also GPIO, DIO, SIO, USBIO
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
IPOR
initial power-on reset
IPSR
interrupt program status register
DMIPS
Dhrystone million instructions per second
IRQ
interrupt request
DMA
direct memory access, see also TD
ITM
instrumentation trace macrocell
DNL
differential nonlinearity, see also INL
KC
Korea Certification
DNU
do not use
LCD
liquid crystal display
DR
port write data registers
DSI
digital system interconnect
LIN
Local Interconnect Network, a communications
protocol.
DWT
data watchpoint and trace
LNA
low noise amplifier
ECC
error correcting code
LR
link register
ECO
external crystal oscillator
LUT
lookup table
EEPROM
electrically erasable programmable read-only
memory
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
EMI
electromagnetic interference
LVTTL
low-voltage transistor-transistor logic
Document Number: 002-11264 Rev. *A
2C,
or IIC Inter-Integrated Circuit, a communications protocol
IC
Industry Canada
IIR
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
Page 39 of 43
CYBLE-224110-00
PRELIMINARY
Table 61. Acronyms Used in this Document (continued)
Acronym
Description
Table 61. Acronyms Used in this Document (continued)
Acronym
Description
MAC
multiply-accumulate
SCL
I2C serial clock
MCU
microcontroller unit
SDA
I2C serial data
MIC
Ministry of Internal Affairs and Communications
(Japan)
S/H
sample and hold
MISO
master-in slave-out
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
Opamp
operational amplifier
PA
power amplifier
PAL
PC
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced features.
See GPIO.
SMT
surface-mount technology; a method for producing
electronic circuitry in which the components are
placed directly onto the surface of PCBs
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
programmable array logic, see also PLD
SR
slew rate
program counter
SRAM
static random access memory
PCB
printed circuit board
SRES
software reset
PGA
programmable gain amplifier
STN
super twisted nematic
PHUB
peripheral hub
SWD
serial wire debug, a test protocol
PHY
physical layer
SWV
single-wire viewer
PICU
port interrupt control unit
TD
transaction descriptor, see also DMA
PLA
programmable logic array
THD
total harmonic distortion
PLD
programmable logic device, see also PAL
TIA
transimpedance amplifier
PLL
phase-locked loop
TN
twisted nematic
PMDD
package material declaration data sheet
TRM
technical reference manual
POR
power-on reset
TTL
transistor-transistor logic
PRES
precise power-on reset
PRS
pseudo random sequence
TUV
Germany: Technischer Überwachungs-Verein
(Technical Inspection Association)
PS
port read data register
TX
transmit
PSoC®
Programmable System-on-Chip™
UART
PSRR
power supply rejection ratio
Universal Asynchronous Transmitter Receiver, a
communications protocol
PWM
pulse-width modulator
UDB
universal digital block
QDID
qualification design ID
USB
Universal Serial Bus
RAM
random-access memory
USBIO
USB input/output, PSoC pins used to connect to a
USB port
RISC
reduced-instruction-set computing
VDAC
voltage DAC, see also DAC, IDAC
RMS
root-mean-square
WDT
watchdog timer
RTC
real-time clock
WOL
write once latch, see also NVL
RTL
register transfer language
WRES
watchdog timer reset
RTR
remote transmission request
XRES
external reset I/O pin
RX
receive
XTAL
crystal
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
Document Number: 002-11264 Rev. *A
Page 40 of 43
PRELIMINARY
CYBLE-224110-00
Document Conventions
Units of Measure
Table 62. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
dBm
decibel-milliwatts
fF
femtofarads
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
kΩ
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
MΩ
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
Ω
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
second
sps
samples per second
sqrtHz
square root of hertz
volt
Document Number: 002-11264 Rev. *A
Page 41 of 43
PRELIMINARY
CYBLE-224110-00
Document History Page
Document Title: CYBLE-224110-00, EZ-BLE™ PSoC® XT/XR Module
Document Number: 002-11264
Orig. of
Change
Submission
Date
Revision
ECN
**
5144379
DSO
02/19/2016 Preliminary datasheet for CYBLE-224110-00 module.
*A
Preliminary
DSO
05/16/2016 Update datasheet to add FCC and IC certification numbers.
Document Number: 002-11264 Rev. *A
Description of Change
Page 42 of 43
PRELIMINARY
CYBLE-224110-00
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/support
cypress.com/touch
USB Controllers
Wireless/RF
cypress.com/psoc
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including
any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.
Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual
property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby
grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-11264 Rev. *A
Revised May 16, 2016
Page 43 of 43
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