Cypress Cy7C68014A Users Manual CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ USB FX2LP(TM) Microcontroller High Speed Peripheral Controller
CY7C68015A to the manual f8c27236-c4f7-439f-912c-6630ea7e969c
2015-02-05
: Cypress Cypress-Cy7C68014A-Users-Manual-532549 cypress-cy7c68014a-users-manual-532549 cypress pdf
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Page Count: 62
- 1. Features (CY7C68013A/14A/15A/16A)
- 2. Applications
- 3. Functional Overview
- 3.1 USB Signaling Speed
- 3.2 8051 Microprocessor
- 3.3 I2C Bus
- 3.4 Buses
- 3.5 USB Boot Methods
- 3.6 ReNumeration™
- 3.7 Bus-powered Applications
- 3.8 Interrupt System
- 3.9 Reset and Wakeup
- 3.10 Program/Data RAM
- 3.11 Register Addresses
- 3.12 Endpoint RAM
- 3.13 External FIFO Interface
- 3.14 GPIF
- 3.15 ECC Generation[7]
- 3.16 USB Uploads and Downloads
- 3.17 Autopointer Access
- 3.18 I2C Controller
- 3.19 Compatible with Previous Generation EZ-USB FX2
- 3.20 CY7C68013A/14A and CY7C68015A/16A Differences
- 4. Pin Assignments
- 5. Register Summary
- 6. Absolute Maximum Ratings
- 7. Operating Conditions
- 8. Thermal Characteristics
- 9. DC Characteristics
- 10. AC Electrical Characteristics
- 10.1 USB Transceiver
- 10.2 Program Memory Read
- 10.3 Data Memory Read
- 10.4 Data Memory Write
- 10.5 PORTC Strobe Feature Timings
- 10.6 GPIF Synchronous Signals
- 10.7 Slave FIFO Synchronous Read
- 10.8 Slave FIFO Asynchronous Read
- 10.9 Slave FIFO Synchronous Write
- 10.10 Slave FIFO Asynchronous Write
- 10.11 Slave FIFO Synchronous Packet End Strobe
- 10.12 Slave FIFO Asynchronous Packet End Strobe
- 10.13 Slave FIFO Output Enable
- 10.14 Slave FIFO Address to Flags/Data
- 10.15 Slave FIFO Synchronous Address
- 10.16 Slave FIFO Asynchronous Address
- 10.17 Sequence Diagram
- 11. Ordering Information
- 12. Package Diagrams
- 13. PCB Layout Recommendations
- 14. Quad Flat Package No Leads (QFN) Package Design Notes
- Logic Block Diagram
- Logic Block Diagram