Datron World Communications G25RMV110 VHF Mobile Radio User Manual G25AMK005a

Datron World Communications Inc VHF Mobile Radio G25AMK005a

Technical Manual

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G25AMK005
G25AMK005
GUARDIAN 110W MOBILE RADIO
TECHNICAL MANUAL
Datron World Communications Inc.
Manual Part No. G25AMK005
Release Date: May 2002
Revision: A
3030 Enterprise Court
Vista, CA 92083, USA
Phone: (760)597-1500 Fax: (760)597-1510
E-mail: sales@dtwc.com
www.dtwc.com
 2000 Datron World Communications Inc. All Rights Reserved.
GuardianTM Technical Manual for use with the Guardian 110W mobile radio.
This manual, as well as the software described in it, are furnished under license and may only be
used in accordance with the terms of such license. This manual is furnished for informational
use only, is subject to change without notice, and should not be construed as a commitment by
Datron World Communications Inc. Datron assumes no responsibility or liability for any errors
or inaccuracies that may appear in this manual.
Except as permitted by such license, no part of this publication may be reproduced, stored in a
retrieval system, or transmitted, in any form or by any means—electronic, mechanical,
recording, or otherwise—without the prior written permission of Datron World Communications
Inc.
GuardianTM is a trademark of Datron World Communications Inc.
Written and designed at Datron World Communications Inc., 3030 Enterprise Court, Vista,
California 92083 USA.
For defense agencies: Restricted Rights Legend. Use, reproduction, or disclosure is subject to
restrictions set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer
Software clause at 252.227-7013.
For civilian agencies: Restricted Rights Legend. Use, reproduction, or disclosure is subject to
restrictions set forth in subparagraphs (a) through (d) of the commercial Computer Software
Restricted Rights clause at 52.227-19 and the limitations set forth in Datron’s standard
commercial agreement for this software. Unpublished rights reserved under the copyright laws
of the United States.
The warranty is void if an unauthorized dealer opens or attempt maintenance on the radio.
Manual part number: G25AMK005. Specifications are subject to change without notice or
obligation.
This device made under license of one or more of the following US Patents: 5,164,986;
5,146,497; 5,185,795; 4,636,791; 4,590,473; 5,185,796; 5,148,482; 5,271,017; 5377229;
4,833,701; 4,972,460.
The IMBETM voice coding technology embodied in this product is protected by intellectual
property rights including patent rights, copyrights, and trade secrets of Digital Voice Systems,
Inc. The voice coding technology can only be used as part of the North American land mobile
radio communications system for the APCO Project 25. The user of this technology is explicitly
prohibited from attempting to decompile, reverse engineer, or disassemble the Object Code, or in
any other way convert the Object Code into human-readable form.
Made in the USA
GUARDIAN
VHF
110W
MOBILE
NOTICE TO USER
WARNING! Maintain a distance of at least 3 feet (1 meter) between the antenna
and people.
To satisfy RF exposure compliance, you, as a qualified user of this radio device
must control the exposure conditions of bystanders to ensure the minimum
distance is maintained between the antenna and nearby persons. The operation
of this transmitter must satisfy the requirements of the Occupational/Controlled
Exposure Environment for work-related use. Transmit only when people are at
least the minimum distance from the properly installed, externally mounted
antenna.
This radio is designed for initial setup by authorized technicians using a
computer and the GuardianTM programming software. Programming can enable
or disable many of the radio’s features from user access per user agency
security policy and legal restrictions. All, some, or none of the features and
functions described in this manual may be available to the user. To successfully
operate the radio, it is important to understand how the radio is programmed
prior to issuance by the user agency. Consult authorized agency personnel for
features and functions made available or restricted to the user. FCC licensees
are prohibited by federal law from enabling the radio to directly enter transmit
frequencies using the radio's controls.
NOTICE TO INSTALLATION TECHNICIANS
Use only a manufacturer- or dealer-supplied antenna.
Antenna minimum safe distance: 3 feet (1 meter).
The Federal Communications Commission (FCC) has adopted a safety
standard for human exposure to Radio Frequency (RF) energy that is below
the Occupational Safety and Health Act (OSHA) limits.
Antenna mounting: The antenna supplied by the manufacturer or radio
dealer must be mounted at a location so that during radio transmission
people cannot come closer than the minimum safe distance to the antenna,
i.e., 3 feet (1 meter).
To comply with current FCC RF exposure limits, the antenna must be
installed at or exceeding the minimum safe distance, and in accordance
with the requirements of the antenna manufacturer or supplier.
Base station installation: The antenna should be fixed-mounted on an
outdoor permanent structure. Address RF exposure compliance at the time
of installation.
Antenna substitution: Do not substitute any antenna for the one supplied or
recommended by the manufacturer or radio dealer. You may be exposing
people to harmful RF radiation. Contact your radio dealer or manufacturer
for further instructions.
ii
GUARDIAN
VHF
110W
MOBILE
CONTENTS
CHAPTER 1:
1.1
1.2
1.3
GENERAL INFORMATION ................................................................................................. 1-1
SCOPE ......................................................................................................................................................... 1-1
GENERAL DESCRIPTION .............................................................................................................................. 1-1
PERFORMANCE SPECIFICATIONS ................................................................................................................. 1-1
CHAPTER 2:
HARDWARE THEORY OF OPERATION.......................................................................... 2-1
2.1
INTRODUCTION ........................................................................................................................................... 2-1
2.2
SYSTEM SPECIFICATIONS ............................................................................................................................ 2-1
2.3
SYSTEM BLOCK DIAGRAM .......................................................................................................................... 2-2
2.4
RECM CONTROL HARDWARE THEORY OF OPERATION .............................................................................. 2-4
2.4.1
Control Logic ..................................................................................................................................... 2-4
2.4.2
DSP .................................................................................................................................................... 2-7
2.4.3
Flash ROM......................................................................................................................................... 2-7
2.4.4
RAM .................................................................................................................................................. 2-7
2.4.5
TCXO................................................................................................................................................. 2-7
2.4.6
FPGA ................................................................................................................................................. 2-8
2.4.7
IF ADC............................................................................................................................................... 2-8
2.4.8
Clock Generation ............................................................................................................................... 2-8
2.4.9
Logic Audio CODEC......................................................................................................................... 2-8
2.4.10 Accessory Connector Interface and Filtering ..................................................................................... 2-8
2.4.11 Transceiver Interface and Filtering .................................................................................................... 2-8
2.4.12 Keypad Interface ................................................................................................................................ 2-8
2.4.13 Audio Interface................................................................................................................................... 2-8
2.4.14 Test Interface...................................................................................................................................... 2-9
2.4.15 LED.................................................................................................................................................... 2-9
2.4.16 RECM Power Consumption............................................................................................................... 2-9
2.5
RECM TRANSCEIVER SECTION .................................................................................................................. 2-9
2.5.1
Interface Section................................................................................................................................. 2-9
2.5.2
Receiver Section............................................................................................................................... 2-10
2.5.3
Digital/Analog Control..................................................................................................................... 2-13
2.5.4
Keypad Microcontroller ................................................................................................................... 2-14
2.6
AUDIO AMPLIFIER BOARD ........................................................................................................................ 2-14
2.6.1
Description ....................................................................................................................................... 2-14
2.6.2
Power Conditioning ......................................................................................................................... 2-14
2.6.3
Communication with Transceiver .................................................................................................... 2-15
2.6.4
Audio Amplifiers ............................................................................................................................. 2-15
2.6.5
Power Levels Detector, Converter, and RF/DC Combiner .............................................................. 2-15
2.6.6
PA ON/OFF Control (Bypass Mode)............................................................................................... 2-16
2.6.7
RF Power Indication ........................................................................................................................ 2-16
2.6.8
Audio Board Block Diagram............................................................................................................ 2-16
2.7
DISPLAY BOARD ....................................................................................................................................... 2-17
Figure 2-4: Guardian Keypad Board............................................................................................................... 2-17
2.7.1
Control Logic Interface .................................................................................................................... 2-18
2.7.2
Keypad ............................................................................................................................................. 2-18
2.7.3
Switch Interface ............................................................................................................................... 2-18
2.8
FRONT PANEL INTERFACE BOARD ............................................................................................................ 2-18
CHAPTER 3:
SOFTWARE THEORY OF OPERATION ........................................................................... 3-1
3.1
FUNCTIONAL SYSTEM OPERATION .............................................................................................................. 3-1
3.1.1
General ............................................................................................................................................... 3-1
3.1.2
Guardian Block Diagram ................................................................................................................... 3-1
3.1.3
Architecture........................................................................................................................................ 3-2
3.1.4
Board Identification ........................................................................................................................... 3-2
GUARDIAN
VHF
110W
MOBILE
iii
Self-Test on Power-Up....................................................................................................................... 3-2
3.1.5
3.1.6
Flash Software Upgrades ................................................................................................................... 3-2
3.1.7
Voice Coder/Decoder (VOCODER) .................................................................................................. 3-2
3.2
RADIO CONTROL SOFTWARE ...................................................................................................................... 3-2
3.2.1
Audio Control .................................................................................................................................... 3-2
3.2.2
DSP Control Software........................................................................................................................ 3-2
3.2.3
Transceiver Board .............................................................................................................................. 3-3
3.2.4
DC Power Control.............................................................................................................................. 3-5
3.2.5
Monitoring ......................................................................................................................................... 3-5
3.2.6
Radio Control Drivers ........................................................................................................................ 3-5
3.3
DIGITAL SIGNAL PROCESSING..................................................................................................................... 3-6
3.3.1
DSP Transmit Chain .......................................................................................................................... 3-6
3.3.2
DSP Receive Chain ............................................................................................................................ 3-8
3.3.3
DSP Software ................................................................................................................................... 3-11
3.4
KEYPAD MPU SOFTWARE ........................................................................................................................ 3-11
3.4.1
Overview.......................................................................................................................................... 3-11
3.4.2
General ............................................................................................................................................. 3-11
3.4.3
Keypad Scanning ............................................................................................................................. 3-11
3.4.4
Push-to-Talk (PTT) Input................................................................................................................. 3-11
3.4.5
Switch Input ..................................................................................................................................... 3-11
3.4.6
LED Output...................................................................................................................................... 3-11
3.4.7
Backlight Control ............................................................................................................................. 3-11
3.4.8
Serial Interface ................................................................................................................................. 3-11
3.5
DATA INTERFACE...................................................................................................................................... 3-12
3.5.1
CAI Data Interface ........................................................................................................................... 3-12
3.5.2
Synchronous Serial Data Interface ................................................................................................... 3-12
3.5.3
CAI Data Link Layer ....................................................................................................................... 3-12
3.5.4
Transmit Physical Link Layer .......................................................................................................... 3-13
3.5.5
Receive Physical Link Layer............................................................................................................ 3-14
3.5.6
DES Encryption ............................................................................................................................... 3-14
3.5.7
Host Interface ................................................................................................................................... 3-15
3.5.8
Flash Interface.................................................................................................................................. 3-15
3.5.9
Paging............................................................................................................................................... 3-15
3.5.10 Hardware Control............................................................................................................................. 3-16
3.6
CONTROLLER SOFTWARE.......................................................................................................................... 3-16
3.6.1
Overview.......................................................................................................................................... 3-16
3.6.2
Environment..................................................................................................................................... 3-16
3.6.3
Radio Store....................................................................................................................................... 3-18
3.6.4
Program/Fill/Control Interface ......................................................................................................... 3-19
3.7
USER INTERFACE ...................................................................................................................................... 3-20
3.7.1
Display ............................................................................................................................................. 3-20
3.7.2
Optional DTMF Microphone ........................................................................................................... 3-20
CHAPTER 4:
INSTALLATION, ADJUSTMENT, AND OPERATION .................................................... 4-1
4.1
RADIO CONFIGURATION ............................................................................................................................. 4-1
4.1.1
Channels............................................................................................................................................. 4-1
4.1.2
Zones.................................................................................................................................................. 4-1
4.1.3
Banks.................................................................................................................................................. 4-1
4.2
INSTALLATION AND ADJUSTMENT .............................................................................................................. 4-1
4.2.1
Hardware............................................................................................................................................ 4-1
4.2.2
Software ............................................................................................................................................. 4-1
4.3
OPERATING PROCEDURES ........................................................................................................................... 4-1
4.3.1
Connect the Power Source ................................................................................................................. 4-1
4.3.2
Connect the Antenna .......................................................................................................................... 4-1
4.3.3
Optional External Speaker ................................................................................................................. 4-1
4.3.4
Radio Programming ........................................................................................................................... 4-1
iv
GUARDIAN
VHF
110W
MOBILE
Radio Power Up ................................................................................................................................. 4-2
Choose a Channel............................................................................................................................... 4-2
Transmit a Voice Message ................................................................................................................. 4-2
Receive a Voice Message................................................................................................................... 4-2
Programming and Bypass Mode ........................................................................................................ 4-2
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
CHAPTER 5:
RADIO SET AND ACCESSORIES ....................................................................................... 5-1
5.1
SYSTEM DESCRIPTION ................................................................................................................................ 5-1
5.1.1
Mobile Radio...................................................................................................................................... 5-1
5.1.2
Antenna .............................................................................................................................................. 5-1
5.1.3
Guardian PC Programmer .................................................................................................................. 5-1
5.1.4
Cloning Cable..................................................................................................................................... 5-2
5.2
CONTROLS, INDICATORS, AND CONNECTORS ............................................................................................. 5-2
5.2.1
Controls.............................................................................................................................................. 5-2
5.2.2
Indicators............................................................................................................................................ 5-3
5.2.3
Connectors ......................................................................................................................................... 5-4
5.3
TRANSCEIVER CHARACTERISTICS ............................................................................................................... 5-4
5.3.1
Transmitter Characteristics ................................................................................................................ 5-4
5.3.2
Receiver Characteristics..................................................................................................................... 5-5
5.4
COMMUNICATION SECURITY ...................................................................................................................... 5-5
5.4.1
Algorithms ......................................................................................................................................... 5-5
5.4.2
Keyfill ................................................................................................................................................ 5-5
5.4.3
Zeroize ............................................................................................................................................... 5-6
CHAPTER 6:
6.1
6.2
6.3
SERVICING THE RADIO...................................................................................................... 6-1
GENERAL .................................................................................................................................................... 6-1
SELF-TEST AT POWER UP ........................................................................................................................... 6-1
CAUTION ..................................................................................................................................................... 6-1
CHAPTER 7:
TROUBLESHOOTING........................................................................................................... 7-1
7.1
INTRODUCTION ........................................................................................................................................... 7-1
7.2
RADIO FUNCTIONAL TESTS ......................................................................................................................... 7-1
7.2.1
Power-On Test ................................................................................................................................... 7-1
7.2.2
Buttons and Switches Test ................................................................................................................. 7-1
7.2.3
Transmit Test ..................................................................................................................................... 7-1
7.2.4
Receive Test....................................................................................................................................... 7-1
7.2.5
Audio Test.......................................................................................................................................... 7-1
CHAPTER 8:
DEFINITIONS ......................................................................................................................... 8-1
CHAPTER 9:
SIGNAL TONES ...................................................................................................................... 9-1
CHAPTER 10:
INTERFACE ...............................................................ERROR! BOOKMARK NOT DEFINED.
10.1
ACCESSORY CONNECTOR PINS AND FUNCTIONS ....................................................................................... 10-1
CHAPTER 11:
SCHEMATICS....................................................................................................................... 11-1
FIGURES
Figure 2-1:
Figure 2-2:
Figure 2-3:
Figure 2-4:
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 3-4:
Guardian Interconnect Diagram .............................................................................................................2-3
Guardian Control Logic .........................................................................................................................2-4
RECM Power Supply .............................................................................................................................2-5
Guardian Keypad Board....................................................................................................................... 2-17
Guardian Block Diagram........................................................................................................................3-1
Transmit DSP Chain...............................................................................................................................3-7
Receive DSP Chain ................................................................................................................................3-8
Controller Software .............................................................................................................................. 3-16
GUARDIAN
VHF
110W
MOBILE
CHAPTER 1: GENERAL INFORMATION
1.1 Scope
This manual provides technical information for the Guardian 110 Watt mobile radio system.. This chapter gives a
general description and provides a system block diagram. Chapters 2 and 3 provided detailed theory of operation for
hardware and software portions of the radio. Chapter 4 provides general operation of the radio. Chapter 5 is the
physical description of the radio components and the available accessories. Chapters 6 and 7 describe servicing,
testing, and troubleshooting the radio system. The remaining chapters provide additional technical information and
schematics.
1.2 General Description
The Guardian 110W mobile radio system is compliant with the APCO project 25 FDMA common air interface, and
is also compatible with conventional wideband FM systems and newer narrowband FM systems. It provides fully
digital encrypted communication suitable for use by modern public safety and commercial users. The radio system is
built from a remote power amplifier and a control head. The 110W RF power amplifier mounts in a remote location
such as a vehicle trunk, while the control unit is mounted in the cabin. The two are connected by a single coaxial
cable. The cable carries both the RF signal and control signals (PTT, and power level setting).
1.3 Performance Specifications
Model Designation
Guardian VHF Mobile Radio
General
Model G25RMV110
Frequency Range
136.000 to 174.000 MHz
Banks, Zones, Channels, Shadow
4 banks, 16 zones, 256 channels, 7 shadow
Voice Digital Mode Voice Coding
IMBE™ 4.4 kb
Frame Re-sync Interval
180 msec
Error Correction Method
RS, golay, hamming
Input Voltage
13.6 Vdc, negative chassis ground
Current Drain @ 13.8V: Standby
0.5A
Receive @ Rated Audio
3.0A
Transmit @ Rated Power
28.0A
Mounting
Dashboard mounted, including bracket
Dimensions
2.75” x 7.1” x 5.5” (H x W x D)
Weight
Control Head
Remote Unit
2.5 lb
12 lb
Case
Metal and plastic
Temperature Range
-30° to +60°C
Channel Spacing
12.5 and 25 kHz, selectable in 2.5 or
3.125 kHz steps
FCC Type Acceptance Number
Pending
Industry Canada
Pending
GUARDIAN
VHF
110W
MOBILE
1-1
Model Designation
Guardian VHF Mobile Radio
Receiver (Measurements per TIA/EIA 603 Standards)
Sensitivity Digital Mode: 5% BER
-116 dBm or greater
Analog Mode: 12 dB SINAD
Spurious
-70 dB
Intermodulation
-70 dB
Audio Output Power
10W, 4Ω external, 5W, 8Ω internal speaker
Audio Distortion (at 1000 Hz)
3%
Frequency Stability (-30° to 60°C)
± 1 ppm
Maximum Frequency Separation
Full-band split
Transmitter (Measurements per TIA/EIA 603 Standards)
RF Power Output
25W to 110W, adjustable
Spurious and Harmonic Emissions
-70 dB
FM Hum and Noise (wideband)
-46 dB @ 25 kHz/-40 dB @ 12.5 kHz
FCC Modulation Designators
16K0F3E, 11K0F3E, 20K0F1E
Audio Distortion (at 1000 Hz)
2%
Audio Response (1000 Hz Ref.)
± 3 dB, 300 to 3000 (EIA/TIA 603)
Frequency Stability (-30°C to 60°C)
± 2.5 ppm
Maximum Frequency Separation
Full bandwidth
Environment Specifications (MIL-SPEC)
Environment
1-2
810C
810D
810E
Method
Procedure
Method
Procedure
Method
Procedure
Low Pressure
500.1
500.2
500.3
II
High Temp.
501.1
I, II
501.2
I, II
501.3
I, II
Low Temp.
502.1
502.2
502.3
Temp. Shock
503.1
503.2
503.3
Solar Radiation
505.1
505.2
505.3
Humidity
507.1
II
507.2
II (5)
507.3
II (5)
Salt Fog
509.1
509.2
509.3
Dust and Sand
510.1
510.2
510.3
I, II
Vibration
514.2
VII(W)
514.3
I (1)
514.4
I (1)
Shock
516.2
I, II, V
516.3
516.4
GUARDIAN
VHF
110W
MOBILE
CHAPTER 2: HARDWARE THEORY OF OPERATION
2.1 Introduction
The Control Module contains the Receiver Exciter Control Module (RECM), Audio amplifier
board, Interface board, and display and keypad assemblies. The RECM is a shielded assembly
containing the transceiver and all control and signal processing hardware and firmware, except
the RF and audio power amplifiers. The trunk-mounted RF power amplifier contains a single PC
assembly.
Schematics for all the boards are located in the back of the manual.
2.2 System Specifications
Table 2-1: Guardian G25RMV110 Technical Specifications
Specification
Description
General
Frequency Range
136.000 to 174.0000 MHz
Banks, Zones, Channels, Shadow
4 banks, 16 zones, 256 channels, 7 shadow
Voice Digital
Mode Voice Coding
IMBE 4.4 kb
Frame Re-sync Interval
180 msec
Error Correction Method
RS, golay, hamming
Mounting
Under dashboard using bracket
Dimensions
2.94”x7.13”x7.06” (H x W x D)
Weight
5 lbs. Approximately
Case
Metal and plastic
Temperature Range
-30° to +60°C
Channel Spacing
12.5 and 25 kHz, selectable in 2.5 or 3.125 kHz steps
FCC Type Acceptance Number
Pending
Industry Canada
Pending
Receiver (Measurements per TIA/EIA 603 Standards)
Sensitivity
Digital Mode: 5% BER
-116 dBm maximum
Analog Mode: 12 dB SINAD
Spurious
-70 dB
Intermodulation
-70 dB
Audio Output Power
5W internal, 10W external speaker
Audio Distortion (at 1000 Hz)
5%
Frequency Stability (-30° to +60°C)
±2.5 ppm
Maximum Frequency Separation
Full-band split
Transmitter (Measurements per TIA/EIA 603 Standards)
Duty Cycle
3%, 3 min continuous
RF Power Output
25W, 50W, 110W; also bypass mode
Spurious and Harmonic Emissions
-70 dB
FM Hum and Noise (wide/narrowband)
-48/-47 dB typical
FCC Modulation Designators
11K0F3E, 16K0F3E, 22K0F3E, 14K6F1E
Audio Distortion (at 1000 Hz)
5%
Audio Response (1000 Hz Ref.)
±3 dB 300 to 3000 (EIA/TIA 603)
Frequency Stability (-30° to +60°C)
±2.5 ppm
GUARDIAN
VHF
110W
MOBILE
2-1
Specification
Maximum Frequency Separation
DES Encryption
Encryption Keys
Code Key Generator
SBCF Analog DES Encryption
Description
Full bandwidth
16
External
Standard feature
Environmental Specifications MIL-STD-810F
Test
Low Pressure (Altitude)
High Temperature
Low Temperature
Temperature Shock
Solar Radiation (Sunshine)
Humidity
Salt Fog
Sand and Dust
Vibration
Shock
Standard Accessories
5W Internal Speaker
Palm Microphone
Mounting Bracket
14 ft Power Cable
Method/Procedure
500.4/II
501.4/I, II
502.4/I
503.4/I
505.4/I
507.4/I
509.4/I
510.4/I, II
514.5/I
516.5/I
Optional Accessories
10W External Speaker
DTMF Microphone
Key Variable Loader
25 ft Power Cable
2.3 System Block Diagram
2-2
GUARDIAN
VHF
110W
MOBILE
Ignition and Emergency Switch
System Control and
Programming
Speaker out
Fused DC Power
DB25
DB9
RECM
PA
control
DTMF
control
Front panel interface
(LCD,Keypad and switches)
MIC
connector
Control Head
Coax
Control
Cable
Fused DC Cable
DC
connector
Power ON/OFF and R/T
switches
Control
In/Out
AMP
Power
spliter
AMP
Filter&
combiner
Antenna Connection
output power
control monitor
power sensor
Mounted Power Amplifier
Figure 2-1: Interconnect Block Diagram
GUARDIAN
VHF
110W
MOBILE
2-3
2.4 RECM Control Hardware Theory of Operation
2.4.1
Control Logic
The control logic interfaces to the keypad logic, transceiver, internal audio, and Motherboard. The control logic
implements the main radio control function and all the baseband signal processing.
TCVR Module
DB25 Accessory Connector
Keypad Board and Front Panel Interface
Grey areas connect
through the 80-pin
connector on the
Motherboard.
Power Supply
Figure 2-2: Guardian Control Logic
2.4.1.1
Power Supply Unit
This block of circuitry takes the 7.8V regulated voltage together with a number of control signals to generate a
number of power supply outputs.
2-4
GUARDIAN
VHF
110W
MOBILE
2.4.1.2
On/Off Switching
The main continuous supply 10V control is passed through a front panel on/off switch to generate 10V SW from the
main radio supply. In normal operation the on/off switching is controlled by the radio on/off rotary switch by the
control /RADON. Once switched on the main controller can hold the radio on by setting PWRHOLD. In addition
to the radio rotary on/off switch, the on/off switching can be controlled by the external line /RADOFF via the
accessory connector. This line overrides the /RADON line and can be used to force the radio off regardless of the
rotary switch setting. However, the H8 controller uses the PWRHOLD and PWROFF lines to implement a clean
controlled switch off.
Figure 2-3: RECM Power Supply
2.4.1.3
Transmit Power Switching
A single FET switch controlled by CTX is used to provide a switched 10VTX high-current supply (1.5A) for the
transmitter.
2.4.1.4
4.5V Switch Mode Power Supply
This circuit uses a switch mode power supply device to generate a 4.5V supply at 450 mA maximum for the radio
logic. The switch mode device is synchronous and uses an externally provided power supply clock at 384 kHz. The
power supply circuit includes input and output filters to limit the conduction of the fundamental switching
components and their harmonics in the VHF band, both onwards into the logic and back into the power supply.
GUARDIAN
VHF
110W
MOBILE
2-5
2.4.1.5
3.3V Linear Logic Supply
The output from the 4.5V switch mode power supply is passed through 3.3V linear power supplies to remove any
remaining power supply switching noise on the main logic supply. One 3.3V supply is used for control logic, the
other 3.3V, 50 mA supply is used for control logic analog circuitry.
2.4.1.6
Reset Generator
This circuit uses a MPU supervisory device (MAX825) to generate a reset pulse of at least 140 ms whenever the
3.3V logic supply drops below 3.08V. The circuit also generates a reset signal when the watchdog input is asserted
by H8 or DSP.
2.4.1.7
5V Linear Logic Supply
This circuit generates a 5V logic supply at 50 mA maximum for use on the control logic.
2.4.1.8
Audio Supplies
Two linear regulators providing clean filtered supplies for the audio at 5V are provided. The audio power amplifiers
use the 5V, 800 mA audio supply. The audio supply is used for the low-current microphone amplifier. A linear 5V
bias supply to the internal microphone is also provided.
2.4.1.9
H8 Microcontroller
H8 is the main controller for the radio and is a HD6433044 ROM-less microcontroller. H8 is configured with an
expanded bus connected to the Flash, RAM, and DSP. The H8 integral bus arbitration logic allows H8 and DSP to
both have access to the Flash and RAM. H8 is clocked by the external TCXO.
H8 is powered from the 3.3V logic supply, and reset by the hardware /RES line. A watchdog output to the hardwarereset circuitry is provided. H8 generates chip select outputs to allow the Flash, RAM, FPGA, and DSP host port to
be separately addressed.
One serial port of H8 is used to implement a bidirectional synchronous serial interface to the keypad board. This
interface is used to communicate with the keypad MPU and directly load the LCD controller. The clock on this
interface runs at 100 kHz. An associated interrupt input to H8 is used to initiate transfers from the keypad to H8.
This serial interface is also used to load the output expander in the FPGA, and also to configure the FPGA.
One serial port of H8 is used to implement a bidirectional asynchronous serial interface to an external PC used for
programming, filling, and controlling the radio. This interface uses programmable standard baud rates (default 9600
baud) and standard data formats. There are no handshaking parallel lines associated with this interface. Two parallel
I/O lines on H8 are used to generate an I2C interface to allow the EEPROM on the transceiver to be accessed. Four
parallel output lines on H8 are used to generate a synchronous serial output bus with clock and data and separate
strobe lines for the DAC, control shift register, and synthesizer on the transceiver.
One H8 DAC output is used to generate simple audio tones of varying volume for use as audio alerts. The second
H8 DAC output is available for VCTCXOP control. The six-channel ADC is used to measure: the raw supply
voltage, WRU radio input, reference crystal temperature, PA temperature, PA current, and RSSI. Two I/O lines are
used to implement software UART, used for debug outputs in the development environment.
2.4.1.10
H8 Input Requirements
The total requirements for parallel input signals to H8, which need to be polled on a regular basis are:
OOL: Out-of-lock (OOL) signal from the transceiver synthesizer
EXT PTT: External PTT
PWROFF: On/off switch position
CONFDONE: Configuration status of FPGA
2.4.1.11
H8 Output Requirements
The total requirements for parallel output signals from H8, which need to be controlled are as below. A serial load
output latch in the FPGA expands the output capabilities of H8.
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LCDA0: LCD controller A0 command/ data select
LCDCS: LCD chip select
SCL: I2C and synthesizer clock
DACSDA: Transceiver serial data, synthesizer, DAC, S-R
SYNTHENA: Synthesizer framing pulse
DACENA: DAC framing pulse
SRENA: S-R framing pulse
/DINT: Interrupt to DSP from H8
/RESO: Watchdog output from H8
2.4.1.12
H8 Input/Output Requirements
The total requirements for parallel input/output signals on H8, which need to be read and controlled are:
BATBUS: Not used in the mobile configurations
SDA: I2C data
2.4.1.13
H8 Input Interrupt Requirements
The total requirements for parallel input interrupt signals on H8 are:
LBOUT: Not used in the mobile configuration
DSPINT DSP: Interrupt
2.4.2
DSP
The DSP56309 (or DSP56302) processor implements all baseband signal-processing functions in the radio. It
interfaces with the transceiver through one ESSI port, to the user for voice through the second ESSI port. The DSP
function is controlled by H8 through the DSP host port. The DSP has direct access to the main Flash memory
through the bus arbitration logic in H8, this allows it to download program images. The initial power-on code
download is through the host port. The hardware-reset line resets the DSP. The TCXO clock output line clocks the
DSP at 12.288 MHz. The DSP ESSI 1 port is used to provide a synchronous interface to the IF ADC and the
transceiver 12-bit DAC. In receive modes that interface is capable of writing to the DAC at 48 ksps while still
reading the ADC at 96 ksps. The DSP ESSI “0” port is used to provide a full-duplex synchronous interface to the
audio CODEC using 8 kHz sampling rate and 13 bit samples. The data transfer is at 2.048 MHz using a DSP
sourced clock and framing pulse.
2.4.3
Flash ROM
A 512k x16 Flash ROM is used as the main program store for the H8 controller and DSP. The Flash ROM uses a
protected boot sector that is factory programmed via the DSP JTAG port. Normal reprogramming is implemented
by running H8 from the boot sector and using 3V, programming the bulk of the device. The Flash is used to provide
a parameter storage area for nonvolatile data storage of frequencies and keys, etc. This storage area is capable of in
excess of 100k write cycles.
2.4.4
RAM
A 128k x 8 static RAM is used for temporary storage of data by the H8 controller. This RAM is powered by a
continuous supply that maintains its contents as long as a power source is present. Additionally the RAM has a
backup capacitor to retain its contents over power interruptions.
2.4.5
TCXO
This oscillator serves as the reference for all logic and power supply clocks within the control logic and keypad. It
provides the data rate clocks for radio operation, and is the source of the ADC/DAC/CODEC conversion clocks. The
TCXO is at 12.288 MHz, with a temperature tolerance of +2.5 ppm. Additional calibration is performed to provide
a typical temperature tolerance of ± 1.0 ppm, a trimmer to set the initial frequency is provided. A Schmitt trigger
buffer squares up the TCXO sine wave output before being output to H8 and DSP.
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2.4.6
FPGA
The control logic uses an Altera 8282 FPGA device to provide a flexible serial data routing function, I/O expansion
for H8 and DSP, clock generation, data multiplexing, and to absorb discrete logic functions.
The synchronous serial bus routing function involves routing the synchronous serial port of H8 either to the keypad
and LCD, or to the I/O expansion in the FPGA. High-order address pins from H8 control this routing and a FPGA
dummy write with dedicated FPGA chip select from H8. The FPGA includes a serial load parallel output shift
register that is used for parallel output expansion for H8.
The discrete logic functions of the FPGA, includes logic to control an inverter for one of the LCD control outputs.
The data multiplexing function involves rerouting serial pins between the accessory connector and the DSP SCI port
to allow data transmission and keyfill operations.
2.4.6.1
FPGA Configuration
The FPGA is configured at start-up from the main Flash memory using a serial load from H8. During configuration
outputs are tri-stated and pulled to a safe level by committing resistors to prevent audio and RF bursts at power up.
2.4.7
IF ADC
The IF sampling ADC is a 12-bit ADC capable of sub-sampling a 455 kHz, IF signal at 96 kHz sampling rate. It is
connected by a serial interface to the DSP ESSI port 1. The serial data interface is clocked at 1536 kHz.
2.4.8
Clock Generation
The clock generation logic is used to generate clocks for the synchronous power supplies, the ADC serial interface,
and the keypad microcontroller. The clock generator logic is implemented in the FPGA.
2.4.9
Logic Audio CODEC
The audio CODEC is an integrated ADC/DAC and audio filter device capable of full-duplex operation on voice
bandwidth signals at 8 ksps. The samples have a resolution of 13-bits linear. The CODEC is connected to the DSP
ESSI port “0” with serial data transfer rate of 2.048 MHz. The CODEC is continuously powered from the 3V logic
and 3V audio supplies. DSP parallel control lines are used to mute the input and output sections as required.
2.4.10 Accessory Connector Interface and Filtering
All outputs are filtered to limit their bandwidth to the minimum and current limited to protect them from output
short circuits to ground or up to 16V. All inputs are filtered and protected from continuous application of ground or
+16V. There is no protection against negative applied voltages. Inputs and outputs are protected from static
discharge of at least 10 kV air discharge. All inputs and outputs incorporate RF bypass filter capacitors adjacent to
the connector, except for ground.
2.4.11 Transceiver Interface and Filtering
Most of the signals crossing the interface are filtered to limit their bandwidth to the minimum consistent with correct
operation. Outputs from the control are filtered with series resistors on the RECM and grounded capacitors on the
transceiver adjacent to the connector. Outputs from the transceiver to the control use the reverse configuration.
2.4.12 Keypad Interface
Some filtering is provided on this interface, but all outputs are protected from short circuits by series resistors.
Where possible, inputs are also protected from damage by series resistors.
2.4.13 Audio Interface
The audio interface is implemented with four-way wire connectors directly via the 80-pin interface through the
Motherboard to the integral speaker and microphone.
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2.4.14 Test Interface
The test interface provides the following functions:
Joint test action group (JTAG) connector access for board test and Flash boot sector programming
Board reset and control access
Board power supply and on-off switching access
H8 serial debug port access
2.4.15 LED
The control logic incorporates a 3-color LED used for status information. It is controlled by the FPGA to show red,
green, or off. It is optically coupled to the top face of the radio by a light pipe. The hardware is configured so
during hardware reset, before the keypad MPU software is running, the LEDs are off.
2.4.16 RECM Power Consumption
The control logic operates at input voltage 7.7V. The average current consumption of the control logic is:
Standby mode: 60 mA
Receive mode @ 500 mW: 330 mA
Transmit mode @ 2W: 1,000 mA
Transmit mode @ 5W: 1,500 mA
2.5 RECM Transceiver
RF shields covers the board.
2.5.1
Interface
J2 is the transceiver antenna connector. RF signals are transmitted and received through this surface mount RF
connector. Transmitted and received RF signals are routed from this connector through a short RF cable to the
RX/TX relay on the Motherboard.
2.5.1.1
Transmit Chain
The pre-driver amplifier (Q7, etc.) amplifies the TXLO signal from the synthesizer section. The Q7 output power is
typically 13 dBm measured at C77/R44/R49 node.
R44, R49, and R52 are part of a 3 dB pie attenuator network. The gain control is made up of CR5, CR6, and
associated components. This circuit yields more than 50 dB of useful attenuation range. The circuit is part of a
DAC controlled closed loop system, in conjunction with the detector/power control circuit (U12, U13, and
associated components), which controls the transmitter output power level. The power amplifier (PA) is a
Mitsubishi M68776, 7.2V, 6W gained controlled power amplifier.
The harmonic filter (C209, L30, C81, C82, L31, C83, and C84) attenuates harmonics created by the power
amplifier. The harmonic filter insertion loss is 0.4 dB typically at 174 MHz. The output of the harmonic filter
connects to the 20 dB coupler (U12). This coupler is part of a DAC-controlled closed loop system designed to set
the transmitter output power level. The insertion loss through the coupler (U12-1 to U12-3) is 0.2 dB typically.
2.5.1.2
Power Amplifier Control
Transmit output power level is controlled by the detector/power control circuit and the gain control amplifier input
via VCONTROL. This closed loop system is designed to keep the transmitter output power constant over variations
in temperature, transmitter supply voltage (7.5VT), and RF power levels into the transmit chain. The detector/power
control circuit is made up of the 20 dB coupler (U12), an RF rectifier circuit (CR11, CR12, etc.), and an integrator
(U13). The DAC line labeled PWRSET at the non-inverting input of U13 sets the transmitter to the desired power
level. U12-2 samples the transmit signal. The sampled RF signal is rectified by the temperature stable circuitry of
CR11, CR12, etc, and is routed to the inverting input of the integrator at U13-4. The output of the integrator at U131, labeled VCONTROL, controls the gain of the power amplifier. Any change in transmitter output power level is
automatically corrected by the loop.
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2.5.1.3
PIN Diode Switch
The antenna PIN diode switch is made up of CR7, CR8, CR9, CR10, and other associated components. This switch
is a four-port design. The four ports are antenna 1 (TOP RF), antenna 2 (SIDE RF), receive, and transmit. Receive
and transmit ports can be switched to only one of the two antenna ports. Transmit signals are routed from the
transmit/receive PIN diode switch (to be discussed in the following paragraph) to the antenna port. The receive
signal is routed from the selected antenna port to the transmit/receive PIN diode switch. The antenna PIN diode
switch and receiver circuits share current in the receive mode of operation via the signal labeled RXSINK at Q11,
pin 3. The insertion loss through the antenna pin switch is 0.2 dB typically.
The transmit/receive PIN diode switch is made up of C6, L60, L38, L40, L39, D9, D7, D10, C97, C98, C104, C105,
C106, C107, and other associated components. C127, C114, L42, and C115 are the 1/4 wave simulator circuit. The
1/4 wave simulator is critical to the design of the switch. In the transmit mode of operation CR13 and CR14 are
forward biased. C116 resonates with the internal series inductance of CR14 at 155 MHz and the receive port (RX
INPUT) is RF shorted to ground. With the receive port RF shorted to ground; the parallel combination of C127,
C114, and L42 forms a tank circuit resonating at 155 MHz. Consequently, the receive port appears as an open
circuit to the transmit signal and is routed to the antenna PIN diode switch. In the receive mode of operation, CR13
and CR14 are biased off so C114/L42/C115 appears as a low-pass filter (LPF) to signals at the antenna port of the
switch. The insertion loss through the transmit/receive PIN diode switch is 0.4 dB in the transmit mode and 0.2 dB
in the receive mode typically.
Q10 to Q19 and associated components are switching transistors used to control the antenna and transmit/ receive
PIN diode switches. The current flowing through the entire PIN diode circuit is approximately 45 mA in the
transmit mode of operation. In the receive mode of operation the transmit/receive PIN diode switch is disabled, and
nominal 85 mA flows through the antenna PIN diode switch.
2.5.2
Receiver
The VHF signal enters into the RX INPUT via the PIN diode switch (discussed previously). D1 and D2 are
Schottky protection diodes to protect the front-end circuitry from RF overloads that could occur if the PIN diode
switch failed to work properly or if a transmitter is very close to a receiver. Typical insertion loss is 0.1 dB for the
protection diodes. L25/C61 form a band-stop filter (BSF) at the first IF frequency of 45 MHz. Typical insertion
loss for the BSF is 15 dB at 45 MHz but less than 0.1 dB in the VHF band.
L14, L6, CR3, CR4, L7, CR27, CR28, L8, and L15 make up the very high frequency (VHF) preselector band-pass
filter (BPF). The BPF is inductively coupled for improved high-side attenuation. This filter provides attenuation to
spurious signals such as the first image and the half-IF. The BPF is varactor diode tuned by DAC line RXVTF.
Typical insertion loss (138 to 174 MHz) is 1 dB for the VHF BPF.
The RF amplifier (Q1, T1, etc.) utilizes loss-less feedback to deliver reasonable gain, low-noise figure, and a high
third order intercept point simultaneously. Typical gain (136 to 174 MHz) is 11.5 dB for the RF amplifier.
C14, L1, C9, C15, L2, C10, C16, L3, C11, C17, and L9 form a VHF LPF. This filter provides additional RX
spurious attenuation as well as image noise attenuation. L4, C12, L16, C25, L5, and C13 form a BSF at the first IF
frequency of 45 MHz. The insertion loss is 1.0 to 2.0 dB (136 to 174 MHz) typically for the cascade. The IF BSF
insertion loss is typically 40 dB at 45 MHz, but less than 0.3 dB in the VHF band.
U1 is a double-balanced mixer (DBM). U1 converts the desired RF signal down to the first IF of 45 MHz. Highside local oscillator (LO) injection is used. Therefore, the LO is 45 MHz higher than the receiver tuned frequency.
The LO drive level is +10 dBm nominal at U1, pin 1. The conversion loss of the mixer (RF to IF) is 5.5 dB
typically.
The LO signal is generated in the synthesizer section (to be discussed later). The LO signal is designated RXLO on
the schematic diagram. The LO signal is routed to a LPF consisting of C31, L21, C87, C30, L20, C75, and C28.
L19 and C28 are also used to impedance match the LO port of the mixer. The insertion loss of the VHF LO LPF is
0.3 dB typically at 174 MHz.
R4, L17, C6, L10, R5, and C23 make up the diplexer network. This network properly terminates the DBM both in
and out of band. The diplexer also provides some additional half-IF spurious rejection. The diplexer insertion loss
is 0.8 dB typically at 45 MHz.
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There are two 45 MHz IF amplifier circuits. The first (Q2, T2, etc.) utilizes loss-less feedback to deliver reasonable
gain, low-noise figure, and a high third order intercept point simultaneously. Typical gain is 10.5 dB for the first IF
amplifier.
There are two crystal BPFs and a second 45 MHz IF amplifier. The BPFs provide attenuation for the adjacent and
alternate channels, and also for the second image response. FL1 is a four-pole crystal filter with a 20 kHz
bandwidth centered at 45 MHz. FL4 is a two-pole crystal filter with a 30 kHz bandwidth centered at 45 MHz. The
second 45 MHz IF amplifier provides high gain to prevent further degradation of receive sensitivity. C57, L12,
C18, C19, and L13 are impedance matching elements for the input of FL1. The output of FL1 is impedance
matched to the second 45-MHz IF amplifier (Q36, etc.) by C285, L64, and C242.
The output of the second 45-MHz IF amplifier is impedance matched to FL4 by C287, L61, C286, C237, L60, and
C235. The entire cascade provides 21 dB of gain and has a 3 dB bandwidth of 20 kHz typically. Typical insertion
loss is 1.5 dB for each crystal BPF.
The IF IC (U28) contains the second mixer and an IF amplifier chain. The 45 MHz IF signal enters U28 at pin 6
from the crystal BPF (FL4). FL4 is impedance matched to the IF IC input by C294, L62, and C288. The incoming
45 MHz IF signal is mixed with the second LO (to be discussed later). The second mixer IF output is at U28, pin 8
and the second IF frequency is 455 kHz.
The signal from U28-8 is routed to FL3. FL3 is a ceramic BPF operating at 455 kHz. The insertion loss of the
ceramic BPF is 6 dB typically in a 1500-ohm system.
The 455 kHz IF signal enters U28-10, is amplified by a cascade of IF amplifiers, and exits at U28-14. The signal
from U28-14 then enters a second ceramic BPF, FL2. FL2 is the final ceramic BPF with a typical insertion loss of 8
dB in a 1000-ohm system. The 455 kHz IF signal enters its final stage of amplification at U29-3. U29 is configured
as a non-inverting operational amplifier and is capable of driving a 50-ohm load. The amplifier is set for a voltage
gain of 2.5. With the receiver set to full gain the signal level at J4 (455 kHz IF OUT MONITOR) is -20 dBm "3 dB
into 50 ohm with a -119 dBm unmodulated 136 MHz signal injected at J2 (TOP RF) or J3 (SIDE RF). The second
LO consists of CR26, R33, Y1, L24, C59, C226, C227, and Q35. The oscillator is a Colpitts type with the crystal
operating in the series mode. CR24 is a varactor diode used to set the oscillator on frequency using the DAC output
labeled 2nd LO. The second LO operating frequency is 44.545 MHz (low-side injection). L65 and C223 impedance
match the output of Q35 to the LPF (C289, C293, L63, and C284). The signal is attenuated by R282, R283, and
R284 and sent on to the second mixer. The signal level at U28-4 is -16 dBm nominal.
U4 is a voltage regulator used to power the receiver circuits. The dc voltage appearing at U4, pin 1, labeled
RXSINK on the schematic diagram, is routed from the antenna PIN diode switch. As previously discussed, the PIN
diode switch and the receiver circuits share current to reduce receive power consumption. The control line +3.3V
RXEN is used to enable the regulator while the transceiver is in the receive mode of operation. The regulator is
disabled during the transmit mode of operation.
2.5.2.1
Synthesizer and Reference Oscillator
U19 is a fractional-N synthesizer IC programmed for a specific frequency by loading appropriate serial data into the
IC. It controls the receive VCO when the transceiver is in the receive mode of operation, and the transmit VCO
when in the transmit mode. The programming lines are labeled 3VSCL, 3VSDA and 3VSYNTHENA on the
schematic diagram. These are all CMOS logic level inputs. R118 (RF) and R123 (RN) are the fractional
compensation and phase detector current setting resistors, respectively. These resistors are critical to the operation
of the synthesizer system and must be checked when troubleshooting around U19. The phase detector output pins
(U19-13 and U19-14) are fed to the passive loop filter (R140, C177, C172, R134, and C173) and on to the VCO
control varactor diodes (CR17/CR19) for frequency control. The buffered, filtered output from the VCO is fed into
U19-5 (RF IN) to close the phase-locked-loop. The level is typically -10 dBm into U19-5. The reference oscillator
is made up of CR22, Y2, Q28, C197, and C198 and associated components. The reference oscillator operates at
12.8 MHz. The reference oscillator operating frequency is adjusted by varying the dc voltage at the DAC controlled
line that is labeled REFOSCMOD. This line is also used to modulate the reference oscillator during the
transceiver’s transmit mode of operation. The 12.8 MHz signal is fed into the synthesizer chip at U19-8 (REF IN)
using a coupling capacitor, C194. The AC signal level at U19-8 is 1V p-p typically.
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U22 is the reference oscillator temperature sensor used to monitor the temperature near Y2. Its output is labeled
XTALTEMP on the schematic diagram. This line is normally monitored by the microprocessor so the reference
oscillator can be adjusted for drift due to changes in temperature.
2.5.2.2
Receive/Transmit VCOs and Buffer Amplifiers
The receive VCO operates from 181 to 219 MHz since high side LO injection is used and the first IF is
45 MHz. The transmit VCO operates from 136 to 174 MHz. Each VCO is a Colpitts type design utilizing a low
noise, bipolar transistor as the active device. The receive VCO uses Q24 and the transmit VCO uses Q21, each in
the common collector configuration. The Colpitts capacitors are C169/C180 (receive VCO), and C137/C142
(transmit VCO). These capacitors enable Q24 to oscillate in the 181 to 219 MHz frequency range and Q21 to
oscillate in the 136 to 174 MHz frequency range. L53 is the resonating inductor for the receive VCO and L45/L46
are the resonating inductors for the transmit VCO. CR20/CR21, and CR16/CR18 are the coarse tuning varactor
diodes for the receive and transmit VCO respectively. These diodes are used to coarse tune the VCO such that the
LPF, phase detector output voltage (from U19) at TP10 equals 1.65 Vdc. The receive and transmit VCOs share the
coarse tuning DAC controlled line labeled CTUNE. Coarse tune dc voltage swings from nominal 1.8 to 22 Vdc.
CR19 (receive VCO) and CR17 (transmit VCO) are the fine-tuning varactor diodes controlled by U19 as was
explained previously. CR15 is the modulation varactor diode for the transmit VCO. The output from the receive
VCO is coupled off Q24-E using C174. The output from the transmit VCO is coupled off Q21-E using C139. The
signal is measured at the C174/R146 node (receive) and the C139/R107 node (transmit), and measures -15 dBm
typically.
Q26 and Q22, and associated components, form the first VCO receive and transmit buffer amplifiers respectively.
These amplifiers buffer the VCO output from changing-output voltage standing wave ratios (VSWR) that could pull
the VCO off frequency. The output from each measures -5 dBm typically. The buffer is measured at the
C170/R141 node (receive) and the C138/R131 node (transmit). Q25 is the second buffer amplifier. This amplifier is
common to both the receive and the transmit VCOs. R131, R141, and R142 are the combining elements used to
make this possible. This buffer outputs a signal large enough, after subsequent attenuation and filtering, to properly
drive the RF IN pin of the synthesizer (U19-5). The output from this buffer is measured at the C167/C53/L52/C175
node and measures 0 dBm typically.
The output from the Q25 buffer is filtered by C175, C53, L52, and C176. This LPF prevents the synthesizer IC
(U19) from locking on to harmonics of the desired frequency. The insertion loss of the LPF is 0.4 dB typically.
The signal is then split by R138, R139, and R144, and sent on to the appropriate receive or transmit final buffer
amplifier. The signal measured at R139/C150/ C186 node is -6 dBm, and the signal measured at R144/R143/C168
node is -6 dBm.
Q23 (receive) and Q27 (transmit) is the final buffer amplifier. Q23 amplifies the signal up to the level needed to
properly drive the LO port of the DBM (discussed previously). Q27 amplifies the signal up to the level needed to
properly drive the PA pre-driver (previously discussed). The signal measured at RXLO is +7 dBm typically. The
signal measured at TXLO is +7 dBm typically.
U17, Q20, etc. form the voltage regulator for the receive and transmit VCO/buffer amplifiers. R67, C124, and Q20
form a super filter, which attenuates voltage regulator noise that may otherwise degrade the synthesizer phase noise
performance.
U20, U21, Q29, Q30, CR23, CR24, CR35, C199, C202, C203, etc. create a voltage multiplier. The circuit is
configured as a voltage quadrupler. Circuit losses and output loading lowers the voltage down from 24 Vdc to about
22 Vdc. The driver circuit (U21) switches at about 192 kHz. This frequency was selected so harmonics would not
land at or near the second IF frequency of 455 kHz. The 22 Vdc supply is used to power the DAC supporting quad
op-amp U18.
The shift register (U24) is used to control transceiver modes of operation and functions. The line labeled STD/SIDE
selects the desired antenna port of the transceiver. The line labeled TX/RX selects either the transmit or receive
mode of operation. +3.3V RXEN turns the receiver on and off (previously discussed). Q34/Q32 and Q33/Q31
enable and disable the receive and transmit VCOs and buffers respectively (discussed previously). U16 is the
voltage regulator that supplies all 5V digital circuitry on the transceiver.
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2.5.3
Digital/Analog Control
Digital/analog control is shown on page 1 of the RECM schematic. The transceiver is fitted with an EEPROM
(U15). The IC is used to store calibration and curve fit data, which is needed when the transceiver is configured
with the Guardian radio. Each transceiver has its calibration and curve fit data stored within the EEPROM. The
calibration and curve fit data is written to the EEPROM at the successful conclusion of level 2 testing. Two quad 8bit serial DACs, a quad 12-bit serial DAC, and supporting operational-amplifiers (U2, U6, U13, U18, and U30)
control much of the transceiver, as has been discussed previously. U32 is a 2.5 Vdc reference used by the Quad 12bit DAC and the variable IF attenuator (discussed previously).
U18D and associated components amplifies the dc signal supplied by U31-3.
As was discussed previously, REFOSCMOD is the dc signal, which varies the operating frequency of the reference
oscillator. Normally under DSP and microprocessor control, this line is used to FM modulate the reference
oscillator, which in turn FM modulates the RF carrier in transmit mode. This line is used to temperature compensate
the reference oscillator as well.
The DAC controlled line TXVCOMOD at U31-4 is transmit data normally controlled by DSP and a microprocessor.
This signal is routed to U18C and associated components. U18C and associated components form an active
LPF/attenuator to shape the transmit data before modulating the RF carrier in the transmit mode. The cutoff
frequency of the LPF occurs at 20 kHz. The 1 kHz peak-to-peak signal level at the active LPF output (U18-8) is
one-fourth TXVCOMOD at 2.5 Vdc.
The synthesizer reference oscillator and the transmit VCO are simultaneously modulated to balance the FM
modulation. We refer to this technique as two-point modulation. The DAC values required to balance the
modulation are dependent on RF frequency.
The dc signal at U31-17 is routed to U30 and associated components. This op-amp is configured for a voltage gain
of 2. The dc signal VATT controls the variable IF attenuator (discussed previously) in the receiver chain. Under
DSP and microprocessor control, the attenuator is normally set for a desired amount of attenuation by this DAC
controlled signal.
Q37, Q38, Q39, Q40, Q41, and associated components are used to enable and disable the 14 dB step attenuator in
the receiver chain (discussed previously). Normally under DSP and microprocessor control, the attenuator is set to
the desired state of operation via U31-13. A logic level “1” at this pin enables the attenuator. Conversely, a logic
level “0” at this pin disables the attenuator (bypass mode).
U18B and associated components amplifies the dc signal supplied by U33-2. As discussed previously, CTUNE is
the dc signal which coarse tunes the receive and transmit VCOs. Under microprocessor control, the appropriate
VCO is normally coarse tuned to a desired frequency based on curve fit data stored in the EEPROM (U15). Curve
fit data is obtained and stored in the EEPROM during coarse tune calibration procedures performed at level 2
testing.
The DAC controlled DC signal 2nd LO sets the 2nd LO (discussed previously) on frequency at 44.545 MHz.
Normally under microprocessor control, the 2nd LO is set on frequency based on a DAC value stored in the
EEPROM (U15). The correct DAC value is obtained and stored in the EEPROM during the 2nd LO calibration
procedure at level “2” testing.
The DAC controlled dc signal RXVTF appropriately sets the varactor tuned BPF (discussed previously) based on
the receiver tuned frequency. Normally under microprocessor control, the varactor tuned BPF is set based on curve
fit data stored in the EEPROM (U15). The curve fit is based on statistical data obtained during the testing of
hundreds of units.
The DAC controlled dc signal PWRSET sets the power amplifier (discussed previously) to a desired power level.
Normally under microprocessor control, the power amplifier is set to the desired level based on curve fit data stored
in the EEPROM (U15). The curve fit data is obtained and stored in the EEPROM during transmit power calibration
procedures at level 2 testing. The power calibration procedure obtains curve fit data for five power level settings
(0.1W, 0.5W, 1.0W, 2.0W, and 5.W) over the entire transmitter operating frequency range (136 to 174 MHz).
The DAC controlled dc signals PA1 and PA2 set the gate bias for each power transistor (Q6 and Q9 respectively) in
the power amplifier circuit (discussed previously). These two signals are routed to op-amps U2 and U6, which are
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configured for a voltage gain of 2. The outputs at U2-1 and U6-1, labeled PABIAS1 and PABIAS2 respectively, are
then routed to the gates of the power transistors. The correct DAC values for the bias current are stored in the
EEPROM (U15). The correct DAC value is obtained and stored in the EEPROM during the power amplifier bias
calibration procedure at level 2 testing. Each gate is biased such that 100 mA of current flows through each power
transistor with PWRSET set to a DAC value of zero in the transmit mode. Level 2 software monitors the U10
output line labeled IMONITOR when calibrating PA bias.
2.5.4
Keypad Microcontroller
The keypad board is controlled by an Atmel AVR4414 microcontroller. This is a Flash programmable device. The
microcontroller implements these functions:
Keypad scanning
PTT switch input
Auxiliary keys input
Volume switch input
Channel switch input
Emergency switch input
Synchronous bidirectional serial interface to main controller at 100 kHz
Keypad and LCD backlight control
A clock derived from the main reference clock, clocks the keypad microcontroller at 1.5 MHz. The keypad
microcontroller is powered by the 3.3V supply as the LCD driver device.
2.6 Audio Amplifier Board
2.6.1
Description
The Audio amplifier board contains the internal and external audio and control circuitry. It also houses the DB25
accessory connector, the DB9 power connector, and the RF control connector that protrudes through the rear panel.
The board is located in the Control Module. The board contains the following functions:
RFI and transient protection and system on/off switch
Voltage regulator and 7.8V on/off switch
Communication with transceiver
Audio power amplifiers
Power levels detector and converter and the RF and DC combiner
PA on off control
RFI and transient protection
2.6.2
Power Conditioning
Power for the Guardian 110W control head enters this board on J5 the DB9 connector. Dual low RDS(on) P-channel
FET Q10 serves as reverse polarity protection and on-off switching. Transistor Q7 pulls down the gates of Q10
when the ON/OFF signal is high, allowing Q10 to conduct. With ON/OFF control low, Q10 is cut off, and will not
pass forward or reverse polarity. An over-voltage condition is detected by D2 and Q6, which cause Q7 to cut off and
turn off power.
Back-to-back transorbers D1 and D4 are used to eliminate voltage spikes before the on/off switch. The input power
is routed to the clamp circuit via an LC filter. The filter eliminates unwanted signals from being conducted to the
vehicle power line.
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2.6.2.1
Voltage Regulator and 7.8V On/Off Switch
Linear regulator U5 provides +7.8V to the RF power control circuitry and to the other two PC assemblies in the
control head. The regulator is powered via Q10 body diode at all time. When the unit is turned off all the circuits
are disconnected from power except the transceiver in the control head. The transceiver in this case is in the off
state. The power consumption in this case is less than 2 mA powering the boat backup memory circuits.
2.6.3
Communication with Transceiver
Twenty pin IDC headers J2 and J3 carry control and status signals from the transceiver and front panel via the
Control PCA.
2.6.4
Audio Amplifiers
The board contains two identical audio amplifiers. Each audio amplifier has 20 dB gain and is capable of delivering
more than 10W to a 4-ohm load in a bridge-tied-load configuration. They are fed from the transceiver audio output.
A front panel switch selects either or both amplifiers; an unselected amplifier is placed in a mute condition by the
appropriate disable signal. When there is no received signal, both amplifiers are placed in a low-current standby
mode by squelch comparator.
2.6.5
Power Levels Detector, Converter, and RF/DC Combiner
ON /OFF, PTT and RF output power control signals to the 110W power amplifier are generated on this board.
These are present as DC signals on the center conductor of the coaxial cable connecting the control head to the
remote RF PA. A low-pass filter prevents RF from reaching the control circuitry. The voltage levels are as follows:
DC Control Voltage Range
PA State
0 to 0.4V
DC on/off switch – OFF
>0.7V
DC on/off switch – ON
0.7 to 1.2V
PA is in bypass – RECEIVE mode
2.1V
Power output set 25W
3.6V
Power output set 50W
6.5V
Power output set to 110W
The transceiver power levels are detected via the connection to TP21. The voltages are as follows:
TP 21 Control Voltage
Boat Power Output
2.85
5W
1.87
2W
1.28
1W
The control circuits converts an input above 2.2V (5W setting) to a control signal to 6.5V, which results in 110W
generated in the remote RF power module. Accordingly it converts the 2W and 1W control levels to the indicated
PA control. Input control of less than 1V is converted to 2.6V. The PA puts out 25W also for the 0.5W input power
setting but will fail to do so at the 0.1W setting. In this case power output is not specified, and the red LED will not
light.
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2.6.6
PA ON/OFF Control (Bypass Mode)
It is possible to operate the system not utilizing the PA (PA in by pass mode.) This is done by turning on control
head on with the PTT depressed. An orange TX light indicates to the user that he is operating in by pass mode. In
this mode, output power is about 1dB lower that the nominal levels delivered from the transceiver, as indicated in
the table above. In normal mode, Q16 conducts at start-up, causing Q14 to conduct, which keeps Q15 off. When
using this mode, Q16 conducts in the reverse direction, Q14 remains off and Q15 conducts, which prevents bias
voltage from being sent to the RF power amplifier.
2.6.7
RF Power Indication
Operational amplifier U3A forces the output control voltage at Q8-E to be equal to that at U3-3. After high power
transmit is detected at the PA output. The RF PA test circuit forces additional current back into this line. The opamp loop holds the voltage at the input level, so the additional current is forced out Q8-C and through R44. This
forces Q9 to conduct and sink additional current from the LED_TX. The LED_TX turns off the green light. When
the unit is in bypass (low power) mode the Tx lamplights orange because the red and the green LED’s are on.
2.6.8
Audio Board Block Diagram
Audio Block diagram
voltage
ragulator
D input voltage
RFI filter&
transient
protection
7.8volts
audio out p
7.8volts
switched
internal
audio amplifier
audio out n
audio in
audio out p
on off switch
external
audio amplifier
audio out n
power level input
25
7.8volts
switched
power level
voltage
converter
RF&DC
combiner
j4
PA on off
control
RF &control out/in
RF IN
Switch PTT
J2 - IDC 20 pin
J3 - IDC 20 pin
Figure 2-4: Audio Board Block Diagram
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2.7 Display Board
The Display board consists of a seven-switch keypad and an LCD module with integrated LED blue backlight. The
board is heatstaked onto the plastic front panel, forming a permanent assembly. Electrical connections are made to
the Interface board via a 20-pin connector (J13).
The radio display module is a full graphics 80x32 pixels LCD, requiring a temperature compensated differential
driving voltage of about 12V and a 1/6 bias, 1/32 duty cycle driving scheme. The LCD driver device (Seiko Epson
SED 1530) drives the display. This LCD driver has an internal display RAM that copes with all the display
refreshing autonomously. Display data transfers from the main controller are only required when the display is
changed, selective display RAM updates are also available to minimize serial traffic. The LCD driver display RAM
is accessed through a one way synchronous serial interface and connected in parallel with the AVR serial port. The
LCD CS input is used to differentiate between serial data for the LCD driver and the keypad board hardware reset
line resets the display drive. The hardware is configured such that during hardware reset, before serial LCD data is
presented, the LCD is blank. The radio keypad consists of 16 keys, which contact onto switch contacts on the rear of
the keypad board.
Keypad
Figure 2-5: Keypad Board
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2.7.1
Control Logic Interface
The signals on this interface need not be filtered, but are protected from short circuits to ground. All logic signals
are at 0 to 3V Complimentary Metal-Oxide Semiconductor (CMOS) levels at the interface. The interface carries the
following functions:
•
•
•
•
•
•
•
•
•
•
•
•
•
10V Control
Ground
/RADON
Switched 10V Supply
Reset
AVR Clock
Serial Data Clock
Serial Data Input
Serial Data Output
Key Interrupt
LCD Chip Select
LCD A0 (data\command select)
Keypad Chip Select
2.7.2
Keypad
2.7.3
Switch Interface
Interface to switches is provided to the RECM via 80-pin connector to the Interface board.
2.8 Interface Board
This board is located in the Control Head Assembly in the vehicle cab. The transceiver (RECM) is mounted to this
board and interfaces through 80-pin connector J1. The front panel display PCA mounts to this assembly and
interfaces through 20-pin connector J4. The microphone interface is J5, an 8-pin modular connector.
Communication with the audio amplifier board and the remote RF Power Amplifier is through two 20-pin
connectors J2 and J3. The DC power for this board, the transceiver and front panel functions enters via J3. The 3.3V
powering the display and logic is generated by a linear regulator U1 powered from the 7.8V via an on/off switch
q12. All front panel switches and LED lamps are mounted to this board. Connection to the internal 5W speaker is
via J6.
ON/OFF control: Transistors Q11-14 are connected to the outputs of the binary volume switch SW3. The
transceiver uses these signals to detect the off position of the volume switch. At the off position all lines are open. If
any of the lines is switched and ignition power is high Q17 is on providing low (0V) to one of the transistor witch
will result in a positive ON/OFF voltage. This signal witch is routed also to the audio board to control power
function there and in the remote RF Power Amplifier.
SW4: Used to change channels. The transceiver uses the binary outputs to detect the position of the channel switch.
Toggle Switches: Program switch SW1 for a variety of functions. Switch SW2 is used to select between internal
and external audio speakers.
Front panel buttons: Keypad depressions on the front panel are detected by the scanning outputs from the
transceiver. Keypad depressions on the optional DTMF microphone are detected by the DTMF decoder on this
board and are processed as ordinary scan-in signals by the transceiver.
DTMF keypad processing: The optional DTMF can be used to program the radio. Keypad depressions generate a
DTMF tone in the audio output. This signal is routed to DTMF detector U6, and digital outputs are sent to1-of-16
de-multiplexer U2. The outputs from U2 are used to control analog switches U3-5. In this way the transceiver scanout lines can be connected to the appropriate scan-in lines to simulate a physical switch closure.
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PTT processing: In normal operation, a PTT switch closure causes Q2 to conduct, which in turn causes Q7 to
conduct. This signal is distributed to the rest of the radio as the PTT signal. When a DTMF button is depressed, the
transceiver automatically transmits this tone.
PTT lockout: To prevent transmission of DTMF tone during programming, a latch circuit is provided to lockout
PTT. When the ENTER button is pressed the PTT signals is disabled by a latches circuit. When the ESCAPE button
is pressed the lockout latch is reset. It is recommended to utilize the PTT condition lockout during programming the
PTT (light will stay off). This is done by pressing ENTER key and after that hold the PTT key depressed until
programming is done. To re-key the radio release PTT and key the radio once the radio is out of the programming
mode use the ESC key quit programming.
J6, 2-pin
speaker
connection
J4, 20-pin display
connection
J5, RJ11, 8-pin MIC
and KLV connection
J2, IDC, 20-pin audio
connection
J3, IDC, 20-pin audio
connection
DTMF to keypad
interface
J1, 80-pin boat connection
LED
drivers/control
Programming PTT
disable
Volume selector
and on/off control
Channel, speaker
out, ABC switch
selectors
On/off controlled
3.3V regulator
Figure 2-5: Interface Board
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CHAPTER 3: SOFTWARE THEORY OF OPERATION
3.1 Functional System Operation
3.1.1
General
All control and channel software is resident in the RECM.
3.1.2
Guardian Block Diagram
DB25 Accessory Connector
Switches
Keypad
LCD
Keypad MPU
Control/Fill/Code
H8 Controller
Control
External Power
Keyfill
Transceiver
User Data
DSP
IF Output
Audio
Modulation
Receiver/Exciter/Control
Module (RECM)
PSU
Power
Battery
Data
Power Supply
Figure 3-1: Software Theory of Operation Block Diagram
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3.1.3
Architecture
A single digital signal processor (DSP) handles all signal-processing functions. An H8 microcontroller is used to
control the user interface and implement other radio control functions. All references to signal names relate to the
Receiver/Exciter/Control Module (RECM). Functionality partitioning is shown in Figure 1-1.
3.1.4
Board Identification
The control logic stores an electronic serial number and modification status within nonvolatile storage on the board.
3.1.5
Self-Test on Power-Up
The software automatically executes a self-test when the radio is switched on. This test is capable of detecting and
identifying faults that prevent the radio from properly operating.
3.1.6
Flash Software Upgrades
The radio software is updated if required using a PC and the Guardian G25AXG004 PC Programming/Cloning
cable.
3.1.7
Voice Coder/Decoder (VOCODER)
The VOCODER uses an improved multi-band excitation (IMBE) voice-coding algorithm as specified in the
telecommunications industry association and electronic industries alliance (TIA/EIA)-102.BABA. The IMBE
VOCODER compresses a high-bit-rate waveform into a low-bit-rate data stream suitable for transmission over the
channel. The VOCODER operates at a net bit rate of 4.4 kbps for voice information and a gross bit rate of 7.2 kbps
after error control coding.
3.2 Radio Control Software
This software controls the transceiver and baseband signal processing functions.
3.2.1
Audio Control
H8 controls the analog audio signal processing. Audio for transmission comes via an external microphone attached
to the front panel. It is wired into the microphone amplifier, which is permanently powered.
Audio output is required when a voice message is received or a tone is generated by the user interface. To allow
audio output, H8 sets either SPKRON or EXTSPKRON to the internal speaker or the accessory connector. If an
external audio accessory is detected by who are you (WRU) <0.5 Vdc, the audio is routed to the accessory
connector. Otherwise audio is routed to the internal speaker. The 16-position volume control knob is decoded and
sent to the DSP through the controller software to control the output audio volume.
3.2.2
DSP Control Software
The DSP implements most of the baseband signal processing in the radio. Its function is controlled through its host
port by the H8 controller. The DSP operates in a number of basic modes controlled by H8 through the host port.
They are as follows:
Mode
Idle
Searching
Searching paused
Active receive
Transmit
Keyfill
Management
3-2
Description
Current shutdown mode released through the host port
Actively looking for a signal on the IF input signal
Search algorithm paused for an economize cycle or frequency change
Actively receiving a message, initiated by detecting a signal or H8 command
Actively transmitting voice or data
Keyfill operations and key
Management tasks
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The DSP pages-in different program images from the Flash for different modes of operation. Typically one image is
used for receive and standby modes, but a new image is needed for transmit and key management operations. The
DSP can interrupt the H8 controller, and then pass data over the host port back to H8. Interrupts from the DSP
include the following events:
•
•
•
•
Signal detected with type data
Signal lost
DSP BIT errors
Paging request
In all active modes the H8 software must be able to write a number of parameters to the DSP and also read back a
number of parameters from the DSP. This is implemented through the host port. The parameters used include:
Mode
Search
Analog setting
Digital setting
Project 25 setting
CVSD setting
Receive
Analog setting
Digital setting
Project 25 setting
CVSD setting
Project 25 setting
Transmit
Analog setting
CVSD setting
Project 25 setting
3.2.3
Description
Reference oscillator temperature used by DSP to correct frequency offsets. AGC
reset control is used at start of search period
BW, squelch tones, squelch code, and squelch level
Data rate, key, and algorithm
NAC and TGID
Continuously variable slope delta (CVSD). Data rate
Reference oscillator temperature used by DSP to correct frequency offsets. Audio
volume
Squelch controls, de-emphasis, and companding
Data rate and key algorithm
NAC, TGID, BER, and test mode
Data rate and key
Read by H8: SS bits, low-rate data (for future use), and sender ID
Reference oscillator temperature used by DSP to correct frequency offsets. Audio
volume, sidetone on/off
Squelch controls and de-emphasis
Data rate and key
NAC, TGID, key and low-rate data (for future use)
Transceiver Board
The Transceiver board is controlled through a synchronous serial bus from H8 to the transceiver allowing H8 to
control the synthesizer, two 4-channel 8-bit digital to analog converters (DAC), and a control shift register in the
transceiver board. Some of the DAC channels are set according to data in the transceiver’s electronically erasable
read-only memory (EEPROM) calibration tables.
3.2.3.1
Mode Control
The transceiver shift register and the CTX output of the field-programmable gate array (FPGA) control the modes of
operation (transmit, receive, or standby). The outputs are controlled as below:
Mode
Spare (SR bit 1)
3.3VRXSynth (SR bit 2)
3.3VTXSynth (SR bit 3)
3.3VRXEnable (SR bit 4)
Spare (SR bit 5)
Spare (SR bit 6)
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Spare
Set in active receive mode, RXVCO enable
Set in active transmit mode, TXVCO enable
Set in active receive mode, receiver enable
Spare
Spare
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3-3
Mode
TX/RX (SR bit 7)
STD/SIDE (SR bit 8)
CTX (FPGA output)
3.2.3.2
Description
Set in active transmit mode, front end TX/RX control
Set to use radio antenna, reset to use accessory connector RF port
Set in active transmit mode to enable the RF power amplifier
Frequency Control
The frequency of operation in both transmit and receive is controlled by the H8 setting in the synthesizer through the
serial bus. To set the desired frequency, the appropriate TX or RX synthesizer enable S-R bit must be set, the serial
data loaded into the synthesizer chip, and the DAC2 output A synthesizer coarse tune set to the appropriate value for
the frequency according to the EEPROM calibration table. Synthesizer lock is monitored by the out-of-lock (OOL)
input. Once the synthesizer lock is achieved, the transmitter or receiver is enabled with the appropriate control bits
3.3VRX enable, CTX, and TX/RX. Economizing the synthesizer function is implemented by controlling the
3.3VTXS/RXS bits and by controlling the EM main divider enable bit in the synthesizer control word. If the
frequency is unchanged, the synthesizer serial data need not be reloaded when coming out of economize.
3.2.3.3
12-Bit DAC
DACLDA, DACADCCLK, and DACDOUT control the 12-bit DAC for IFAGC, TXVCOMOD, REFOSCMOD,
and VATT.
3.2.3.4
Reference Oscillator Temperature Compensation
The H8 software constantly monitors the reference oscillator crystal temperature using the XTALMON line. The
temperature data is used to lookup the compensation factor in the transceiver’s EEPROM calibration table. This
compensation factor is written into the DSP, added as a dc offset reference oscillator modulation signal, and used as
a dc offset in receive mode.
3.2.3.5
Receiver Control
Setting 3.3VRXE enables the linear receiver chain. The DSP implements software AGC system to control the gain
of the linear receiver chain. The H8 controller monitors the actual received signal level by reading RSSI. At all
times during receive the RXVTF DAC2 output C must be set to the value in the EEPROM calibration table
corresponding to the receive frequency used. This makes the receiver’s front-end tunable filter centered on the
desired frequency. At all times in receive modes the second LO DAC2 line output B must be controlled using data
from the EEPROM calibration table and indexed with oscillator temperature data XTALMON. The temperature
compensates the second LO in the receiver chain.
3.2.3.6
Transmitter Control
The radio uses a complex H8 software-based algorithm to dynamically control the transmit power of the radio. The
inputs to the power control algorithm are: requested power level (0.1W, 0.5W, 1W, 2W, or 5W), PA calibration
data in the EEPROM, supply voltage BATMON (used for monitoring), transmit frequency, PA current, (used for
monitoring), and PA temperature (used for monitoring).
The power control algorithm takes these inputs and uses them to control the following outputs to provide a steady
RF power output with a clean rise and fall at switch on/off.
Output
PWRSET (DAC1 output A)
PABIAS1 (DAC1 output B)
PABIAS2 (DAC1 output C)
3.2.3.7
Description
Sets the power level in the power amplifier ALC loop
Adjusts the bias in the final driver stage
Adjusts the bias in the final driver stage
TX/RX Switching
The procedure needed to quickly switch the transceiver from receive to transmit and back again is to shut down the
current mode, lock the synthesizer in the new mode on the new frequency, and enable the transmitter or receiver, as
required.
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3.2.3.8
Receiver Scanning
In some scanning modes it is necessary for the radio to scan a number of channels looking for traffic, as controlled
by the H8 software. The basic requirement is to change the synthesizer frequency, RXVTF, synthesizer tune DAC,
and to resume searching on the new frequency. The DSP may have to be informed of new traffic settings on which
to search, for each new frequency. Scanning is interrupted when the DSP detects a signal of interest.
3.2.4
DC Power Control
The H8 controller software controls the power supply switching in the radio. The control software algorithm uses
the following inputs:
Input
/PWROFF
WRU
/LBOUT
BATBUS
BATMON
Description
Indicates the current position of the radio on/off switch and the accessory connector off line
Indicates if the radio is fitted into a harness providing external power
Indicates the supply voltage is at the minimum required for correct operation
Not used in the mobile configuration
Indicates the voltage on the main radio supply from external power source
These inputs are used to control the following FPGA outputs:
Output
PWRHOLD
BATOFF
Description
Set during normal operation, the radio stays on regardless of the on/off switch. When
PWROFF indicates that a switch off is required, software shut down is executed followed
by a release of this output
Not used in the mobile configuration
Additionally the /LBOUT interrupt is used to execute a fast shutdown of the software when the supply voltage drops
below that needed for normal operation, or when the power source is removed without switching the radio off.
3.2.4.1
Power Supply Frequency Control
The power supply software controls the switch mode power supply frequency output according to the RF frequency
used. The frequency is checked and changed if necessary at every synthesizer frequency change.
3.2.5
Monitoring
The H8 software monitors the following signals:
Signal
Out-of-lock
EPTT/RTS
RSSI
WRU
DC voltage
PA temp
REF temp
PA current
3.2.6
Description
In all active modes, every 100 ms
In all modes, every 20 ms
In receive modes, every 100 ms
In all modes, every second
In all modes, every 5 seconds
In transmit modes, every second
In all modes, every 5 seconds
In transmit modes, every second
Radio Control Drivers
A number of low-level software drivers are used by H8, which interface to the transceiver hardware.
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3.2.6.1
Audio and Power Supply Unit (PSU) Driver
A serial interface driver controls the output bits of a serial-to-parallel output shift register in the FPGA. Clock and
data source for this shift register is the same serial port used for the user interface serial bus, but data is directed to
the shift register using high-order H8 address lines.
3.2.6.2
Transceiver Serial Bus Driver
A serial interface driver controls the transceiver shift register, DAC, and synthesizer. It uses a common clock and
data line, and three separate strobe lines for each device.
3.2.6.3
DSP Host Driver
The H8 software includes a DSP host driver for controlling the DSP mode of operation, and initial start-up code
download.
3.2.6.4
IIC Bus Driver
The H8 software includes a driver that allows the controller software to read and write to the transceiver EEPROM
using IIC protocols. The two lines are general-purpose I/O lines controlled on a bit-by-bit basis by the software.
3.3 Digital Signal Processing
The DSP software implements all baseband signals processing in the radio. It processes signals between the user
audio and data interface, and the transceiver modulation and intermediate frequency (IF) interfaces. The signal
processing provides compatible analog FM modes, common air interface (CAI) compatible modes, and 12 kbps
secure CVSD modes.
3.3.1
DSP Transmit Chain
Signal processing while the radio is transmitting depends on the radio's operational mode. The possible modes are
clear analog voice FM, CVSD DES voice, Project 25 clear digital voice, and Project 25 DES digital voice. The
Transmit DSP Chain block diagram is shown in Figure 3-2. The major signal processing functions of the DSP
transmit chain are described in the following paragraphs.
3.3.1.1
Audio Coder/Decoder (CODEC)
The Guardian uses a Texas Instruments® TLV320-AC36 audio CODEC. Data is transferred to and from the
CODEC using the DSP enhanced synchronous serial interface (ESSI) 0 port. The data word is 16 bits long. The
first thirteen bits are the two’s compliment audio sample, and the last 3 are the volume control word in the receive
direction (DIN), and zero padded in the transmit direction (DOUT). The DSP currently sets volume control bits for
no attenuation. Scaling the signal prior to sending it to the CODEC controls the volume. The sample rate from the
CODEC is 8 ksps.
3.3.1.2
Audio Processing Board
The Audio Processing board receives audio input from the audio CODEC, applies filtering and automatic gain
control (AGC), and transmits it to the mode-specific formatting module. The audio filter has a passband from
300 Hz to 3 kHz. This board also transmits DTMF tones to the audio CODEC. DTMF over-dial is supported to
allow redirection through the phone network via a base station. Data is transferred to and from the CODEC under
interrupt service routine (ISR) control.
3.3.1.3
Project 25 Voice Module
The Project 25 Voice module performs framing and conversion tasks. The framing function uses its own task table
to build a CAI time-division multiple access (TDMA) frame. This includes compression of the voice signal using
the IMBE VOCODER, forward error correction, and encryption. The physical layer task converts a 4.8 ksps dibit
data stream into a 48 ksps real sampled waveform, which is then fed to the Modulation module. The physical layer
scales each dibit symbol so that the proper frequency deviation is attained. It applies raised cosine filtering for
control of inter-symbol interference.
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Project 25 Voice
Module
VOICE
Audio
Processing
Module
Audio
CODEC
DTMF
Tones
CVSD DES
Module
Analog FM
Module
Transceiver
Modulation
Module
Figure 3-2: Transmit DSP Chain
3.3.1.4
CVSD DES Module
Audio data from the Audio Processing module is sent to the audio circular buffer. The sample rate is increased from
8 ksps to 12 ksps. The CVSD encodes the data and sends it to the transmit CVSD audio circular buffer. The data is
DES-encrypted and differentially encoded before sent to the physical interface buffer. The CVSD physical layer
converts the CVSD encoded, DES encrypted 12 ksps data stream into a 48 ksps waveform suitable for processing by
the Modulation module. The module contains a finite impulse response (FIR) raised cosine filter that acts as an
interpolation filter. Transmitting an end of message (EOM) indicator, consisting of 160 ms of alternating ones and
zeros, signals the end of a transmission. This allows the receiving radio to squelch the audio output before the radio
stops transmitting.
3.3.1.5
Analog FM Module
Audio data entering the Analog FM module is sent through a linear-phase, FIR, audio-shaping filter. Interpolation
from 8 ksps to 48 ksps is accomplished using a linear-phase, FIR filter. A single-quadrant sine look-up table (LUT),
using fractional addressing and quadrant folding, generates continuous tone controlled squelch system (CTCSS)
tones. If the DCS audio turn-off code is transmitted, the tone is fixed at 134.4 Hz and the codes transmitted at a rate
of 134.4 bps, derived using the CTCSS tone generator. The DCS data stream passes through a raised cosine filter
before added to the speech. The 8 ksps audio stream, with CTCSS/DCS controls, is interpolated to 48 ksps before
sent to the Modulation module.
3.3.1.6
Modulation Module
The Modulation module prepares the signal for transmission. The signal is split into a reference oscillator signal and
a voltage controlled oscillator (VCO) signal. This allows independent scale and offset values for each signal. A
modulation-balance variable scales the reference oscillator voltage, so that the maximum frequency deviation is
constant for all RF channels. A transmit modulation variable does the same for the VCO signal.
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3.3.1.7
Transceiver Interface
The transceiver DAC has four output ports, two of which modulate the carrier. One of the two channels maintains
carrier frequency accuracy. On transmit channel changes, the controller provides the DSP with two fractional values
used to scale the two signals output from the DAC. The controller provides the DSP with an additional integer value
at one second intervals, and is added to one of the DAC output signals to control carrier frequency accuracy. The
modulation interface receives modulation data samples at 48 ksps, independent of the transmit mode. When the
radio is operating as a transmitter, the transceiver interface controls the operation of the DAC via ESSI 1 on the
DSP. Data is written to the DAC at 96 ksps.
3.3.2
DSP Receive Chain
The radio receive chain hardware consists of an RF transceiver board, analog to digital converter (ADC), a
Motorola® DSP 56302 or DSP 56309, and an audio CODEC. The Receive DSP Chain block diagram is shown in
Figure 1-3. The major signal receive functions of the DSP receive chain are described in the following paragraphs.
Project 25
Voice Module
Transceiver
FM
Demodulator
Signal
Detectors
CVSD DES
Module
Analog FM
Module
Audio
CODEC
Audio
Processing
Module
Figure 3-3: Receive DSP Chain
3.3.2.1
Transceiver
The RF transceiver board performs mixing and filtering of the received signal to produce a 455 kHz, 25 kHz
bandwidth (BW), IF signal. The output signal from the transceiver is digitized by the ADC and fed to the DSP. The
bulk of signal processing is performed by the DSP. An ISR that implements the transceiver/ADC/DAC interface is
called at a rate of 96 kHz in receive modes. The ISR reads ADC output data, stores the values in a circular buffer,
and controls data transmission to the DAC.
3.3.2.2
FM Demodulator
The FM demodulator converts the FM output of the transceiver to a real-valued, baseband signal. FM demodulation
is implemented by a discriminator task. Sub-sampling the 455 kHz IF at 96 kHz folds down the signal to 25 kHz. A
mixing function mixes the sampled IF data in the input buffer before filtering. For 12.5 kHz channels, a second
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filter is applied to the IQ data stream. Calculating the angular difference between consecutive IQ pairs demodulates
the received signal.
3.3.2.2.1 Analog to Digital Converter
Because the signal BW is much less than the 455 kHz carrier frequency, the ADC sub-samples the 455 kHz IF
producing a frequency translation as part of the sampling process. The ADC sampling rate is 96 ksps.
3.3.2.2.2 25 kHz Frequency Translation
The 25 kHz frequency translation converts the signal image into a baseband signal, centered at 0 Hz. The DSP
implements the digital equivalent of a mixer to perform frequency translation.
3.3.2.2.3 IF Filtering
The complex baseband signal is sent through two linear phase FIR filters. The first IF filter is used as a decimate by
two, polyphase, FIR filters and applied to the 96 ksps, complex, baseband output of the 25 kHz mixer. This filter
removes some of the out-of-band noise produced by the nonlinear analog components of the transceiver. CVSD
DES and analog wide modes have a 25 kHz BW and the first IF filter is the only filtering performed for these
modes. Project 25 and analog narrow modes have a 12.5 kHz BW. The second IF filter provides the filtering
required for these modes and is applied to the 48 ksps output of the first IF filter.
3.3.2.3
Signal Detectors
The radio uses three signal detectors to detect the presence or absence of a modulated signal in the tuned channel.
These signal detectors search for Project 25, analog FM (including noise, CTCSS, and DCS), and CVSD DES
signals.
3.3.2.3.1 Project 25 Detector
The Project 25 frame detector detects a Project 25 signal by searching for the frame synchronization (FS) signal and
network identifier (NID) embedded in the preamble of every Project 25 data unit. The detector uses this information
to perform bit recovery and packet identification. It processes and buffers the binary data for use by the Project 25
Voice Module. Once a target signal is detected, the radio disables squelch using an enable transmit function, so the
user can monitor the signal. If the detected signal is lost, squelch is enabled by the shutdown active receive
function.
3.3.2.3.2 Analog FM Detector
The analog FM detector uses a function to decimate the incoming data stream by six, to run the noise detector,
CTCSS single-tone detector, CTCSS multi-tone detector, and the DCS multi-code detector. A noise squelch detect
function detects the appearance of a carrier by searching for a drop in power in a frequency band just above the
audio band. In the analog noise detector, the input data is scaled and high-pass filtered, then rectified and scaled
again. Then the data is low-pass filtered. The output of the low-pass filter is used to determine whether or not a
signal is present.
The detector has two states, searching and locked. If the detector state is searching and the detected power drops
below the lower squelch threshold, the detector state transitions to locked. Conversely, if the detector state is locked
and the detected power rises above the upper squelch threshold, the detector state transitions to searching. Upper
and lower threshold values are BW dependent and can be adjusted at run time.
The multiple-value DCS detector searches for a 134.4 bps bit stream in the sub-audible frequency band used for
DCS codes. If found, the code is extracted and appropriate state variables updated. Code extraction is performed in
two steps: input data is converted to a binary bit stream, and then data extraction and code comparisons are
performed.
The conversion of the input data to a binary bit stream starts with the 8 ksps input data sent through a decimate by
six, FIR filter to produce a 1.33 ksps, real valued data stream. This filter removes any signal energy outside of the
sub-audible frequency band. The data is then split into two paths. The lower path estimates the dc content of the
signal with a narrow low-pass infinite impulse response (IIR) filter. Subtracting the lower path signal from the
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upper path signal removes the dc component from the upper path signal. Following this, the resulting signal passes
through a single-bit quantizer and the output buffered for use by the code removal step. Data extraction and DCS
code comparisons are then accomplished.
3.3.2.3.3 CVSD DES Detection
Detection of CVSD DES waveform is performed by a secure detection function. This function also recovers the
12 kbps bit stream from the 48 ksps input signal. The detector looks for a 12 kbps data stream to determine if a
CVSD signal is received.
3.3.2.4
Project 25 Voice Module
The physical layer task extracts FS, NID, SS symbols, and data. All other dibits are passed to the receive framing
task. The module performs recovery and symbol extraction based on frame synchronization using a correlation
detector. Symbol extraction and error-correction decoding follow carrier frequency offset compensation.
VOCODER data and Project 25 framing data is removed and secure mode decryption performed. The VOCODER
converts the compressed voice data stream to a 8 ksps audio data stream that is sent to the Modulation module.
3.3.2.5
Analog FM Module
The analog FM module performs two tasks. The detection task uses an FIR filter to down-sample the FM
demodulated bit stream from 48 ksps to 8 ksps. It then uses four detectors (noise, single-tone CTCSS, multi-tone
CTCSS, and multi-code DCS) to determine signal squelch. The post-detection audio-shaping task applies deemphasis on/off filtering to a received clear analog signal.
3.3.2.6
CVSD DES Module
The CVSD DES module consists of a 12 kbps clock detection/recovery task, a 12 kbps symbol resolver, a
differential decoder, a DES decoder, a 12 kbps CVSD decoder, and a 12 ksps to 8 ksps sample rate converter. The
input to the clock detection algorithm is a 48 ksps data stream, representing the sampled FM demodulated carrier.
To allow for variation in carrier frequency, the dc component of the demodulated carrier is removed before zerocrossing detection. From a zero-crossing phase profile, a decision can be made whether a 12 ksps data stream is
present on the demodulated carrier, or a 12 kHz clock recovered for usage within the 12 kbps symbol resolver.
Differential encoding of the binary FSK modulation ensures compatibility between manufacturers, so that either a
positive or negative frequency shift can be used to represent a 1 symbol. In the CVSD receive chain, differential
decoding precedes one-bit cipher feedback DES decoding. To conserve memory and aid processing efficiency, all
symbols (encoded and decoded) are packed in memory. The 12 kbps CVSD decoder is modeled after FED-STD1023.
The decoder consists of a modulation level analyzer (MLA), a syllabic filter, a pulse modulator, a principal
integrator and a comparator. The output of the CVSD decoder is at 12 kbps and must be changed to 8 ksps for
output by the CODEC.
3.3.2.7
Audio Processing Module
An audio receive task function and an audio filter is used to output Project 25, clear analog, or secure analog speech
samples to the CODEC. When in active receive modes, the ISR is enabled and the task outputs data to the CODEC
circular buffer as data is written to it’s audio input circular buffer.
3.3.2.8
Audio CODEC
The audio CODEC and the DSP interface uses the DSP ESSI 0 port. The serial clock to the CODEC operates at
2.048 MHz, and is derived from the DSP internal clock. ESSI 0 is configured to operate using a frame rate divider
of 16 and a word length of 16 bits, transmitting packets of encoded audio to the CODEC at 8 kHz. The CODEC is
used in a linear decode mode, where 13 bits are used to represent the full audio range. The post-processed DSP
signal is fed to the audio CODEC, which converts the signal to an analog waveform, applies gain, and routes it to
the appropriate output device.
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3.3.3
DSP Software
The program data for the DSP is stored in 64K Flash program blocks. The data is stored as unpacked bytes. The
blocks used for the DSP software are dedicated so that selective upgrades of this code only are possible.
3.4 Keypad MPU Software
3.4.1
Overview
The keypad microprocessor unit (MPU) provides an indirect interface via the Motherboard to the DTMF keypad and
front panel switches. It communicates with the main controller via a synchronous bi-directional serial link.
3.4.2
General
The software is designed so that processor activity and current consumption is minimized. The only continuous
operation required is keypad scanning and switch reading. An external clock at 1.5 MHz clocks the keypad. The
hardware reset is supplied from the main controller.
3.4.3
Keypad Scanning
The keypad scanning software continuously scans the keypad at a rate of a row every 10 ms. A debounce period of
40 ms is used on key presses and key releases. The software deals with simultaneous key presses and key rollovers,
making only single key presses valid. Debounced and validated key presses are passed to the serial data output
buffer.
3.4.4
Push-to-Talk (PTT) Input
Inputs from the momentary input switches, and the PTT and auxiliary keys, are read every 10 ms and are debounced
for 40 ms. The validation software filters out simultaneous presses of the auxiliary keys and the key rollover
between them. Simultaneous presses of the PTT switch and one auxiliary key are allowed. Debounced and
validated auxiliary key presses and PTT press and releases are passed to the serial data output buffer.
3.4.5
Switch Input
Inputs from the rotary switches and toggle switch are read at least every 40 ms. Changes in state are debounced for
100 ms. Debounced new switch positions are passed to the serial output buffer.
3.4.6
LED Output
The outputs to the LED are controlled under instruction from the serial port. It is possible to set both outputs off, set
the red LED on, set the green LED on, set both LEDs on (orange), and to flash either or both on a 50% duty cycle at
a controlled rate of approximately 1 Hz.
3.4.7
Backlight Control
The two LCD backlight controls for setting bright and dim operations are controlled under instruction from the serial
port. The keypad uses a fixed level backlight operation. A timeout facility switches off the backlight after
30 seconds if not requested by the main controller.
3.4.8
Serial Interface
The keypad controller implements a synchronous bi-directional serial interface using its serial port allowing it to
interface to the main controller. The main controller always sources the serial data clock. To allow autonomous
transfers from the keypad controller, a separate keypad interrupt line is provided with the interface. The interrupt
line is used to request 8 clocks from the main controller to transfer data from the keypad. The LCD chip select (CS)
input line is used to distinguish between serial data for the keypad controller and LCD driver. The serial interface
supports the following transfers:
•
Keypad to controller including:
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•
•
•
•
•
•
Keypad power up okay
Keypad error 1-n
Key press 1-16
Key release 1-16
PTT press
PTT release
Volume switch 1-16
Channel switch 1-16
Toggle switch 1-3
Auxiliary key press 1-3
Emergency key press
Controller to keypad
Request current switch status
Reset and execute BIT test
Backlight off/bright/dim
LED off/red/green/yellow/flash/flash rate
Key press request and interrupt acknowledge
LCD data transfers are in blocks of 80 bytes maximum, allowing a pause on the serial interface at least every 100 ms
for the keypad MPU to assert the interrupt and transfer key press or switch change data. During the LCD data
transfers, the key data are buffered into the keypad MPU.
3.5 Data Interface
The DSP incorporates a user data interface through its SCI port.
3.5.1
CAI Data Interface
The DSP supports an asynchronous data interface for CAI modes using its SCI port. This interface conforms to the
CAI data peripheral interface. It uses standard V24, and RS232 baud rates up to 9600 baud. The software also
controls the associated flow control signal data of the terminal ready (DTR) input to the DSP, and the clear to send
(CTS) output from the DSP. The request to send (RTS) input to the radio for this interface is processed by H8.
3.5.2
Synchronous Serial Data Interface
The DSP supports a 12 kbps synchronous serial port using its SCI port. The interface is half duplex, uses a DSP
generated clock, and includes minimum data buffering within the DSP and RTS/CTS flow control on the transmit
function.
3.5.2.1
Receiver Synchronous Serial Data Buffering
In receive synchronous serial data modes the DSP software uses a variable length first-in first-out (FIFO) buffer to
cope with differences in clock rates between the transmitter and receiver.
3.5.3
CAI Data Link Layer
This software provides the link between the raw voice and data bit streams, in addition to the data formats required
to implement a 9.6 kbps CAI compatible interface.
3.5.3.1
CAI Transmit Voice Mode
The DSP software takes the 144 bit voice code words (encrypted or not) and a number of link control fields set by
the host H8 or from the DES system, and formats CAI-compatible logic link data units.
3.5.3.2
CAI Transmit Voice Test Modes
The DSP software is capable of transmitting the CAI voice silence test pattern, the CAI 1 kHz test pattern and a
9 x 144-bit (1296) PRBS test pattern used for error rate tests. The H8 controller controls these test modes.
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3.5.3.3
CAI Receive Voice Mode
The DSP takes the 9.6 kbps CAI-compatible data stream and framing, and splits out the voice data for passing to the
VOCODER. The DSP decodes the link control words so that the host H8 can read the link control fields, and the
encryption synchronization information is available to the encryption process. CAI receive processing is initiated by
the frame synchronization correlator trigger. When this is asserted the next 64 bits of network identifier (NID) data
are decoded and checked. If the NAC code matches the one selected for the channel, voice or data processing
proceeds, otherwise the physical layer is forced into search mode.
3.5.3.4
CAI Receive Voice Test Mode
The DSP software is capable of testing the 9 voice code words received in a CAI frame against a known 9 x 144
PRBS segment. The total number of errors in that frame is then output to the H8 controller. The H8 controller
controls this test mode.
3.5.3.5
CAI Transmit Data Mode
The DSP selects the user data (encrypted or clear) and a number of link control fields set by the host H8 or from the
DES system, and formats logic link data units compatible with the CAI at 9600 bps.
3.5.3.6
CAI Receive Data Mode
The DSP selects the 9.6 kbps CAI-compatible data stream and framing, and splits out and decodes the data for
passing to the user data port. The DSP decodes the link control words so that the host H8 can read the link control
fields, and the encryption synchronization information is available to the encryption process.
3.5.4
Transmit Physical Link Layer
This software uses common modulator interface software and a number of mode-dependent, physical link layer
software modules.
3.5.4.1
Transmit Modulation Interface
The software provides a common interface to the dual modulation, DAC in the transceiver through its SSI serial port
1 for all transmit modes. In transmit modes, the SSI uses an externally sourced clock at 3072 kHz. This interface
takes frequency deviation samples at 48 kHz, and writes each value scaled by a fixed number set by the host to both
the reference oscillator DAC and the VCO DAC. Additionally a host-controlled dc offset is added to the reference
oscillator DAC value.
3.5.4.2
Transmit CAI Physical Link Layer
This software takes the 9.6 kbps CAI-compatible data stream and converts it to 48k samples of frequency deviation
data. To achieve this the software implements the dibit for symbol mapping, Nyquist, and shaping filters as
described in the CAI.
3.5.4.3
Transmit Analog FM Physical Link Layer
This software takes the 8 ksps filtered audio and converts it to 48 ksps of frequency deviation data compatible with
TIA/EIA-603 in 12.5 kHz and 25 kHz modes. The signal processing uses additional high-pass filtering to reduce the
energy in the DCS tone band, audio band pre-emphasis if required, DCS tone addition, and deviation limiting and
smoothing. The software is capable of operation in 12.5 kHz, and 25 kHz channel spacing with appropriate
deviation scaling. It is capable of appending a phase reversed tone burst of 180 ms as defined in EIA-603,
generating DCS and audio turn-off codes, and companding the voice signal in 12.5 kHz mode.
3.5.4.4
Transmit CVSD Physical Link Layer
The transmit CVSD physical link layer converts the 12/16 kbps CVSD data stream and converts it to 48 ksps of
frequency deviation data. The software implements a pre-modulation filter with raised cosine time response and
100% eye height.
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3.5.5
Receive Physical Link Layer
This software uses common FM demodulation software, and mode-dependent receiver physical layer software
modules.
3.5.5.1
Receive ADC and DAC Interface
In receive modes SSI port 1 is used in a duplex manner to allow the ADC to be read continuously at 96 kHz and the
DAC written up to 48 ksps for AGC and reference oscillator adjustment. In receive modes, the SSI port is clocked
at 1536 kHz from an external clock source, using a 16-bit cycle. At every cycle a value is read out of the ADC. At
every other cycle a value may be written to one of the DAC channels to control the AGC and reference oscillator.
3.5.5.2
FM Demodulator
This software provides a common interface to the 96 ksps IF signal at SSI port 1 and produces 48 ksps of frequency
deviation data for use in all modes. The SSI port uses an external clock at 1536 kHz. The software implements an
FM demodulator function using a quadrature mix with a 24 kHz (Fs/4) local oscillator, dual I and Q channel filters,
and a frequency estimator. The channel filtering function is programmable-dependent on the channel spacing used.
The channel filtering provides the adjacent channel filtering in addition to that provided by the hardware to achieve
the radio adjacent channel rejection performance.
3.5.5.3
Receive CAI Physical Link Layer
This software takes the 48 ksps of frequency deviation data and outputs a 9.6 kbps data stream. The software
implements an integrate and dump filter and data slicer as described in the CAI. The integrate and dump filter is
controlled by a clock recovery function that selects one of ten possible phases for output to the slicer. The slicer
incorporates an averager with a time constant of at least 100 bits, to correct for dc offsets in the received signal.
In parallel with the above, a FIR correlator searching for the CAI fixed framing sequence of 24 symbols operates on
the filtered 48 ksps of frequency deviation data. The correlator operates at 10 samples per symbol. The correlator
phase with the highest correlation peak selects the clock phase for use in the integrate and dump filter and slicer.
This correlator operates continuously when searching for CAI traffic and occasionally when tracking an CAI signal
when subsequent frame syncs are expected. The correlator trigger is used to provide a framing signal for the
subsequent CAI link layer processing.
3.5.5.4
Receive Analog FM Physical Link Layer
This software takes the 48 ksps frequency deviation data and outputs 8 ksps of audio to the receive audio processing.
Software signal processing implements a high-pass filter to remove CTCSS tones and de-emphasis if required. The
gain of the signal path is adjusted to cope with the different deviations used on different channel bandwidths. The
signal processing signal path is controlled by squelch signals. The software includes audio expanding to reverse the
transmit companding.
3.5.5.5
Receive CVSD Physical Link Layer
This software takes the 48 ksps frequency deviation data and outputs 12/16 kbps serial data. The software uses a
data filter, a slicer, and a clock recovery function.
3.5.6
DES Encryption
The DSP software implements DES encryption of traffic in the CAI and CVSD modes.
3.5.6.1
DES Kernel
The DSP software implements the DES encryption kernel as described in FIPS 46-2, encrypting 64 data bits using a
56-bit key. It uses output feedback operation or a single bit cipher feedback operation.
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3.5.6.2
CAI Encryption
The DSP software uses DES kernel software to implement the CAI encryption of voice traffic as described in
TIA/EIA/IS-102.AAAA. The key manager supplies the encryption key. In transmit, the message indicator (MI)
vector is passed to data link processing for encoding and transmission. In receive, the data link layer decodes the MI
vector, and fly wheeled if decoding fails for up to n frames.
3.5.6.3
DES Data Link Layer
This software encrypts and decrypts the 12 kb of CVSD data using the DES kernel. During transmit, framing
synchronization data and the MI vector are inserted into the data stream. In receive, the software searches for and
extracts the framing and MI data. Bit definitions and formats are defined in the DES protocol.
3.5.6.4
Key Interface
This software provides an interface for inputting DES encryption keys from the DSP SCI port using synchronous
data transfers with an external clock, and for conforming to the Motorola KVL data transfer mechanism and the CAI
DES keyfill protocol.
3.5.6.5
Key Bank
The radio maintains a bank of up to 16 encryption keys stored in Flash memory. Associated with each key are a key
ID, key data, and an 8-character alphanumeric tag. Each encrypted channel is assigned one of the 16 keys for both
secure transmit and secure receive modes. Channel key assignment is accomplished by selecting the corresponding
key tag. Upon entering the secure transmit or secure receive mode, H8 transfers the appropriate encryption key to
the DSP through the SCI port.
3.5.7
Host Interface
The DSP is controlled through its host interface by H8. It initially boots up through this interface. The host
interface is used for DSP mode control, encryption key transfer, link control data transfer, low-rate data transfer,
frequency variable data transfer, CTCSS mode control, and initial software download.
3.5.8
Flash Interface
The DSP has direct access to the main radio Flash memory through the H8 bus arbitration logic. This interface is
used for software downloads using byte-wide direct memory access (DMA) transfers under host control for mode
changes. The DSP software does not write to Flash memory.
3.5.9
Paging
The DSP software is designed so that normal operation does not involve off-chip bus accesses. This means the code
size must be limited to 24K words and the data memory to 10K words. A number of program images that
correspond to different modes are allowed, with paging of images out of Flash by the DMA at mode changes. The
minimum subdivision of images corresponds to the following modes, and a continuously resident core host interface
function.
•
•
•
•
•
•
Initialization/POST
Receive 12.5 kHz
Receive 25 kHz
Transmit 12.5 kHz
Transmit 25 kHz
Keyfill
The paging DMA mechanism is controlled by the host H8 and allows the transfer of a program image within 50 ms.
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3.5.10 Hardware Control
The DSP software controls the DSP clock rate through the phased locked loop (PLL) output divider. The DSP clock
rate is dynamically matched to the mode of operation, in coarse steps for example, between searching and tracking
receive modes. The DSP software uses low-current wait modes in pauses between processing to minimize current
consumption. The host is also able to request a very low-current idle mode in the DSP. The host releases this mode.
3.6 Controller Software
3.6.1
Overview
The controller software has overall control of the radio; including user interface operations, and the DSP and
transceiver. Figure 1-4 is the controller software block diagram.
Alarms
Switches
and Keys
Environment
Software
Main
Controller/
Scheduler
LCD
MMI Drivers (AVR)
Software Update
Driver
MMI Software
Radio Store
Key
Fill Data
Fill/Program/
Control
Software
Radio
State
FPGA
Configure
Driver
Debug
Serial
Driver
PC
Serial
Port
Driver
Radio Control Software
Audio
PSU
Frequency Power/Mode DSP
Control Control
Control
Audio/PSU
Driver
Transceiver
Driver
DSP
Host
Battery
EEPROM
BIT
Monitor
BATBUS IIC Bus
Driver
Driver
Figure 3-4: Controller Software
3.6.2
3.6.2.1
Environment
General
The H8 controller system is designed for minimum external bus activity and minimum current consumption. These
features are provided by the maximum use of low-current standby modes in H8, and an interrupt-driven architecture,
with a minimum of input polling. In radio standby and receive modes the only H8 tasks are the control of the
transceiver frequency and DSP mode as the radio scans and economizes. The most H8-intensive activities are
associated with user interactions, and operations on the fill/program/control port.
3.6.2.2
Scheduler
H8 operates with a simple scheduler that launches tasks after interrupt events. A time base interrupt of 10 ms is
used to keep track of time and poll inputs at regular intervals.
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3.6.2.2.1 Interrupt Sources
The following interrupt sources are used in H8.
Interrupt Source
User interface
DSP
Low dc voltage
Timer
PC serial port
UI serial port
Debug serial port
Alarm generator
Description
External interrupt from the keypad
External interrupt from the DSP, signal detected, etc.
External NMI from power supply indicates power supply fail
Internal time base tick interrupt every 10 ms
Internal interrupt from PC interrupt serial port
Internal interrupt from user interface serial port, key press, and LCD data
Internal interrupt from DMA/timer
Internal interrupt from DMA/timer
3.6.2.2.2 Polled Inputs
The H8 software polls the following inputs at regular intervals.
Input
EXTPTT/RTS
OOL
PWROFF
SENSE
Description
External PTT and data RTS
Synthesizer out of lock
On/off switch position
External keyfill device detect
The following analog inputs are measured as appropriate to the radio mode of operation.
Input
RSSI
WRU
BATT
PA TEMP
XTAL TEMP
PA CURRENT
Description
Receiver signal strength
External device detect
Main radio 10V supply monitor
Transmitter temperature
Reference crystal temperature
Transmitter current
3.6.2.2.3 Watchdog
A regular watchdog service task is scheduled to prevent the H8 watchdog controller from overrunning, and a
hardware reset from occurring. The target watchdog timeout is 100/200 ms.
3.6.2.3
Start-Up Software
3.6.2.3.1 Boot Block Start-Up Software
The minimum simplest start-up software is provided in the boot block of the Flash. This software holds the keypad,
DSP, user interface, and FPGA in reset, and then establishes whether a valid H8 program image exists in the
program blocks of the Flash. If no valid program exists, a simple alarm sounds. The boot block software includes a
minimum basic BIT facility to check the code itself, and the internal and external random access memory (RAM).
The boot block code includes the software to allow programming of the program blocks through the PC serial port.
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3.6.2.3.2 Full Start-Up Software
If a valid H8 program image exists, the full start-up code executes. This involves initializing RAM, DSP, keypad,
user interface, FPGA, transceiver, etc., executing the start-up BIT, and transferring control to the main scheduler.
3.6.2.3.3 FPGA Configure Software
At start-up H8 configures the FPGA using data from the main Flash memory and transferring it via a synchronous
serial bus to the FPGA.
3.6.2.4
Shut Down Software
At normal shut down when the front panel on/off switch is off, the H8 software executes a clean shut down to the
transceiver, DSP, and user interface (UI), saves any usage data to the Flash, and releases the main power supply. In
cases where the power is removed, the low-power interrupt executes a minimum fast shut down, saving RAM data
as required, with no Flash update.
3.6.2.5
Debug Driver Software
The H8 controller includes software to implement an asynchronous serial port on two input/output (I/O) pins of H8.
Facilities provided include the ability to monitor particular radio variables, and to control specific variables. This
port allows PC serial access to the board during board-level factory testing, through the test connector.
3.6.3
Radio Store
All functional areas of the controller software, including the user interface, access the radio data store, fill control,
and radio software.
3.6.3.1
Physical Data Storage
The radio data is physically stored in 4 devices, all devices are accessible by the controller software.
3.6.3.1.1 H8 Internal RAM
The H8 controller has 2K x 8 of internal RAM. This data is not retained when the radio is switched off or the power
is removed. It is used for short-term storage of frequently accessed variables, stack workspace, etc. to minimize bus
activity when the H8 controller is running. The internal RAM is used as program space from which to execute
during some Flash update operations.
3.6.3.1.2 External RAM
H8 is provided with an external 128k x 8 bit RAM that is backed up for at least 30 seconds when the radio power is
removed, and at all times when a external power is applied with the radio switched off. This device is used as a
variable data expansion area, and stores specific user-entered data that must be retained over power interruptions
(unlock password, etc.).
3.6.3.1.3 Flash ROM
H8 has a 512k x 16-bit Flash read-only memory (ROM) used primarily for program storage. Data in the Flash is
retained permanently. Different areas of the Flash have different characteristics. The boot sector is a 16k block
used for the reprogramming software and the radio serial number. The data in this sector is programmed or blockerased only in the factory.
The Flash has 15-64k and 6-8k program blocks that can be block-erased and programmed by the boot block code
during normal reprogramming operations, without special equipment and without opening the radio. These blocks
are used for H8 and DSP operating software, radio fill data, and FPGA programming data. The Flash has two small
8k parameter blocks used for changing data that must be stored indefinitely, such as user specific settings and usage
data.
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3.6.3.1.4 Transceiver EEPROM
The radio transceiver has an 8k x 8 serial EEPROM for storing transceiver calibration data. This data is set during
production testing for the specific transceiver. The data in this device is essentially constant and is never written to
by the main controller. At switch on, contents of the EEPROM are copied into the external RAM; EEPROM is not
accessed during normal operation.
3.6.3.2
Data Types
The controller software uses a number of different data types.
3.6.3.2.1 Volatile Variables
Variable data used by the H8 controller that is not retained when the radio is switched off, is stored in the H8
internal RAM and the external RAM.
3.6.3.2.2 Short Term Stored Variables
Variable data retained while the radio is switched off or the power is interrupted, is stored in the external RAM.
3.6.3.2.3 Permanent Stored Variables
Variable data retained indefinitely is stored in the parameter blocks of the Flash. Every time this data changes, a
parameter block must be erased, and the new data written into the now blank parameter block.
3.6.3.2.4 Radio Fill Data
The frequencies, modes, and power levels are associated with different channels programmed into the radio. This
data is programmed into the radio through the fill port.
3.6.4
Program/Fill/Control Interface
The controller provides a serial port for PC access to allow the following functions:
Function
Programming
Filling
Control
3.6.4.1
Description
To update radio software
For modifying the radio data store of modes and frequencies, etc.
For controlling the radio operating mode
Radio Programming
The controller software allows reprogramming of the Flash memory program blocks, on a block-by-block basis.
During these operations, the controller executes from the boot sector of the Flash and no radio or user interface
operations are possible. After a programming operation, cycle the power on the radio. Programming operations are
initiated on receipt of a specific serial message on the PC serial port.
3.6.4.2
Radio Fill
The controller provides the facilities to modify the system, group, bank, and radio global data through the PC serial
port. This interface provides the following facilities:
Facility
Radio erase
Selective erase
Radio fill
Radio read
GUARDIAN
Description
Delete all fill data in the radio
Delete (mark as deleted) specific systems, groups, and banks (for
future use)
Add specific systems, groups, banks, and global data to the radio store
Export the fill data contents of the radio store to the PC
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All transfers and operations on the fill port are cyclic redundancy checked (CRC) and acknowledged.
3.6.4.2.1 Cloning
The radio can export channel data to other radios. Data export is initiated by a user interface operation at the
exporting radio. The exporting radio emulates a PC programmer during the data transfer. Cloning of keyfill data
is not allowed.
3.6.4.2.2 Radio Keyfill
The DSP software manages the radio keyfill protocols.
3.6.4.3
Radio Control Port
It is possible for an external PC to control the functioning of the radio. This provides the following facilities:
•
•
•
•
Radio status read to export the radio serial number, revision status, history, usage, etc.
Set external control mode
Set radio transmit frequency, power level, and mode
Set radio receive frequency and mode
The transceiver mode control also allows transmission of 1 kHz test tones in analog modes, and BER test patterns in
digital modes. The receiver mode control allows the continuous (every 0.5 second) output of the bit error count per
frame in digital modes.
3.6.4.4
PC Serial Port Driver
The controller software controls the H8 serial port to implement the asynchronous data formats and baud rates
(9,600, 19,200, and 38,400) for the PC serial port. The serial port driver software also controls the 232OFF signal to
maintain the RS232 in its low-current standby state, except when data is driven out and while RTS is asserted.
3.7 User Interface
The radio interface is described in the following paragraphs.
3.7.1
Display
The radio has an 80 x 32 dot matrix LCD display. Some of the features of the display are:
Feature
Phone
Scan
Encryption
Power level
Priority scan
Receive only channel
Talkaround
Repeater mode
Emergency message
3.7.2
Description
Indicated by an icon in the top, right of the display (for future use)
Indicated by SCAN****, SRCH****, or ZONE**** flashing in the top row of the display
Indicated by a key icon
Indicated by HI/LO/2W in the bottom row of the display
Indicated by SCANP1 (P2), SRCHP1 (P2), or ZONEP1 (P2) flashing in the top row of the
display
Indicated by an RX in the bottom, left corner of the display
Indicated by a TA in the bottom, left corner of the display
Indicated by a receiver icon in the bottom, left corner of the display
EMG displays in the bottom, left corner when the radio is transmitting an emergency
message
Optional DTMF Microphone
The radio is programmed using DTMF microphone. For detailed instructions on programming the radio a DTMF
microphone, see the Guardian operator manual (G25AMK004).
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CHAPTER 4: INSTALLATION, ADJUSTMENT, AND OPERATION
4.1 Radio Configuration
4.1.1
Channels
A channel consists of a receive and transmit frequency pair. The radio has a total of 256 selectable channels. Each
channel can be programmed for different receive and transmit frequencies, squelch, modulation, encryption, and
power. Each channel can have one of possible 16 keys assigned on a channel-by-channel basis. An 8-character
alphanumeric label identifies each channel or by its channel number if no text label. Up to 7 shadow channels can
be added to each channel. They enable the radio to be used in several squelch/encryption modes on each physical
channel.
4.1.2
Zones
A zone is a group of channels. Each zone can be assigned up to 16 channels. The radio can store up to 16 zones, or
groups of channels. The zones can be assigned names of up to 8 alphanumeric characters and assigned to banks
during programming. Three zones can be selected by the toggle switch, 16 zones by the front panel keyboard.
Channels are mapped to the channel select switch positions using the Guardian PC programmer. When a zone is
active (selected), channels within the zone are selected using the 16-position channel select switch on the front panel
of the radio.
4.1.3
Banks
A bank is a group of zones. Zones are assigned to banks during programming. The radio can store up to 4 banks of
16 zones each. Banks are assigned names of up to 8 characters.
4.2 Installation and Adjustment
4.2.1
Hardware
Install using the Datron approved bracket.
4.2.2
Software
The manufacturer offers software updates when required. Software updates can be performed via an external port.
No radio disassembly is required.
4.3 Operating Procedures
4.3.1
Connect the Power Source
Use only the Datron approved power cable set, negative ground only.
4.3.2
Connect the Antenna
The antenna connects to the radio through a UHF antenna connector. For best VSWR, make sure to match the
antenna before operation.
4.3.3
Optional External Speaker
Use the accessory connector on the rear panel of the radio to connect the external speaker.
4.3.4
Radio Programming
Prior to the first time of operation, the radio must be programmed using the Guardian programming kit. For
information about programming a radio using the PC programmer, refer to the Guardian programming manual. For
PTT lockout during a programming sequence, refer to the Interface board description in Chapter 2.
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4.3.5
Radio Power Up
Turn on the radio using the on/off/volume knob. The radio performs a self-test and sounds a short medium-pitched
tone to indicate PASS. Use the switch to set the volume to a comfortable level. Select the desired channel using the
channel select switch. The process takes 3 to 5 seconds before the radio is ready for operation.
4.3.6
Choose a Channel
The default display shows the current zone and channel. Use the channel select switch to select a different channel
in the zone. To change zones, program one of the side keys, program the three-position toggle switch to zone select,
or program through the display using the select menu.
4.3.7
Transmit a Voice Message
Press the PTT switch on the palm microphone, hold the radio 2 to 6 inches from your mouth, and speak in a clear
voice.
4.3.8
Receive a Voice Message
To receive a voice message, release the PTT. Use the PC programmer or the radio program menu to set or adjust the
squelch level, CTCSS tones, DCS variables, NACs, and/or talk-group identifiers (TGIDs) as required.
4.3.9
Programming and Bypass Mode
For description of these features, refer to the Interface board section in Chapter 2.
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CHAPTER 5: RADIO SET AND ACCESSORIES
5.1 System Description
The Guardian consists of the following components:
•
•
•
•
Receiver/Exciter/Control Module (RECM)
Front Panel Interface
Motherboard
Heatsink Assembly
For available accessories, contact a Datron Guardian representative.
5.1.1
Mobile Radio
The Guardian is a vehicular-mounted transceiver capable of providing secure and non-secure communications over
the 136 to 174 MHz RF range. The radio includes an LCD, emergency push button, speaker, microphone, multifunction accessory connector, three programmable function keys, 16-position channel select rotary knob,
on/off/volume rotary knob, 3-position programmable toggle switch, antenna connector, dc power connector, and two
LED status indicators. The Guardian features adjustable power output ranging from 25W to 110W. Operational
modes include:
•
•
•
•
Clear analog voice FM, 12.5 and 25 kHz
DES CVSD modulation voice, 25 kHz, 12 kbps
Project 25 clear digital voice, 12.5 kHz
DTMF overdial
5.1.2
Antenna
The antenna is a SO239 (UHF) jack mounted to the rear panel.
5.1.3
Guardian PC Programmer
Note: For some programming features, refer to the Interface board section in Chapter 2.
The Guardian programming kit is compatible with Windows 95/98/NT, capable of loading or modifying
programming information into the radio from a PC. It includes software, a detailed operator manual, and an RS232
compatible programming/cloning cable. The cable connects the PC serial port to the accessory connector on the rear
panel of the radio. See the Guardian programming manual for a complete description of PC programming. The PC
programmer is capable of programming the following settings:
BANK
Bank tag
Special channels: Priority channels 1 and 2, emergency channel, and home channel
Zones/available zones
ZONE
CHANNEL
Zone tag
Scan list
Channels/available channels
Channel tag
Channel type
Bandwidth
Receive only option
Options: Scan list, talkaround, and locked
Encryption: Enable, and key
Transmit Power: High and low RF power levels
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Receive and Transmit Parameters: Operating frequencies, P25 NAC (digital),
talkgroup (digital), squelch mode/value (analog), and shadow channels
GLOBAL
KEY
User (configuration name)
User ID P25
Keys and Switches: Auxiliary switch (1-3) function, toggle switch function, and
emergency button function
Programming Access: Programming enable, and programming password
Scan: Revert mode, scan delay, scan reply, and monitor time
Transmit: Transmit inhibit/override, and transmit time-out
Emergency: Alert mode, duration timer, and repeat timer
Key tag
Key ID
Key data
5.1.4
Cloning Cable
The Guardian G25AXG004 programming/cloning cable is used to transfer programming information (excluding
crypto keys and global parameters) from one radio to another radio. The cable connects to the radio accessory
connector on both the sending (source) and receiving (target) radios. Each cable end is labeled accordingly (source
and target) for ease of use.
5.2 Controls, Indicators, and Connectors
Consult the Guardian operator manual for detailed operating instructions.
5.2.1
Controls
The radio controls consist of a 16-position channel rotary knob, an on/off/volume rotary knob, a 3-position toggle
switch, 3 programmable function keys, an emergency push button, a PTT switch, and a 16-button keypad.
5.2.1.1
On/Off/Volume Rotary Knob
The on/off/volume knob located on the front panel of the radio is a 16-position rotary switch. The first position is
off, the second position is on with the speaker off (mute), and the remaining positions are used for increasing
volume levels.
5.2.1.2
16-Channel Rotary Knob
The channel select knob, located on the front panel of the radio, is used to rapidly switch between the programmable
16 channels.
5.2.1.3
3-Position Toggle Switch
The 3-position toggle switch located on the front panel of the radio is programmed using the PC programmer for
zone select, transmit encryption enabled/disabled, scan on/priority/off, high/low power, talkaround on/off, monitor
(squelch adjust) on/off, and disabled.
5.2.1.4
External Speaker Switch
The external speaker provides 10W of clear communications audio from the radio. Comes with data and speaker
cable. Set the speaker switch to I for internal speaker operation, E for external, or B for both speakers
simultaneously.
5.2.1.5
PTT Switch
The PTT switch is located on the microphone.
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5.2.1.6
Programmable Keys
Three programmable keys are located on the front panel of the radio. These keys are programmed using the PC
programmer for the following functions:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Backlight dim/bright/off (for future use)
Encryption on/off
Scan list add/delete
Keypad disable (for future use)
Monitor on/off
Scan on/priority/off
Signal strength meter on/off
Talkaround
On/off
Home channel
Audible tones on/off (for future use)
Next zone (future use)
Open microphone (for future use)
Previous channel (for future use)
Disabled
5.2.1.7
Optional Emergency Button
Program the emergency button for emergency operation or for zeroize operation. If programmed for emergency
operation, pressing the button activates the emergency calling. The emergency condition remains active until
cleared by turning off the radio. When the emergency mode is activated, an emergency message is broadcast over
the emergency channel. There are two programmable modes: audio (full alert and silent), and display (alert and
silent). In full-alert mode, EMERGENCY flashes on the display and an audio tone is sounded. In silent mode, there
is no audio tone and no LED indication. If the emergency button is programmed for zeroize operation, all
encryption keys contained in the radio are erased.
5.2.1.8
Optional DTMF Microphone
The optional DTMF microphone includes a 12-button keypad with positive feedback on the front panel. The keypad
provides adjustable backlighting for nighttime viewing.
5.2.2
5.2.2.1
Indicators
LCD
The radio contains a full graphics 80 x 32 pixel LCD that uses characters and graphics to provide the operator with
radio operating information. The display provides backlighting for nighttime operation.
5.2.2.2
LED
The 3-color LED provides the operating status of the radio. The LED is viewable from front panel of the radio and
provides radio status as follows:
LED
Red
Green
Flashing green
Orange
GUARDIAN
Indication
Transmitting
Receiving/busy channel indicator
Receiving encrypted transmission
Emergency/low dc power voltage
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5-3
5.2.2.3
Audible Tones
The radio has several audible tones that are activated by states of operation or by radio faults. These tones are
described in Chapter 9.
5.2.3
Connectors
5.2.3.1
Accessory Connector
The accessory connector is a DB25 connector located on the rear panel of the radio. This connector is used for
multiple functions, including PC programming, keyfill, cloning, external speaker, and audio accessory attachment.
The pin names and functions are defined in Chapter 10.
5.2.3.2
Antenna Connector
The antenna connector is a SO239 jack.
5.2.3.3
DC Power Connector
The dc power connector is a 9-pin D connector in the rear panel of the radio.
5.3 Transceiver Characteristics
The radio frequency range is 136 to 174 MHz with channel spacing of 12.5 or 25 kHz, tunable in 5 kHz steps.
5.3.1
Transmitter Characteristics
5.3.1.1
Transmitter Output
The transmitter output consists of a single channel FM carrier using either conventional 12.5 or 25 kHz FM
modulation, or 12.5 kHz compatible 4-level FM (C4FM). The signal source is analog or digitized voice signals.
5.3.1.2
Transmit Squelch
Transmit squelch parameters are required to enable selective squelch communications options. These parameters
are described below.
5.3.1.2.1 Analog Transmit Squelch
There are 3 types of analog transmit squelch:
Type
None
CTCSS
DCS
Description
No squelch is included with the analog transmit signal
Sub-audible CTCSS squelch tones are included with the analog transmit signal
DCS variables are superimposed on the analog transmit signal
5.3.1.2.2 Digital Transmit Squelch
There are 4 types of digital transmit squelch:
Type
None
Network Access
Code (NAC)
TGID
5-4
Description
No squelch is included with the digital transmit signal
A digital NAC is transmitted with the Project 25 digital transmit signal. The
primary purpose of this code is to allow the user access to a repeater network
A digital TGID is transmitted with the Project 25 digital transmit signal. The
primary purpose of this selective digital calling identification is to group users into
functional teams
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Type
Individual Call
Description
TGID is automatically set to 0000 (hex) and the user ID of the targeted radio is
activated within the Project 25 digital transmit signal
5.3.2
Receiver Characteristics
5.3.2.1
Receiver Performance
The receiver is capable of demodulating a single-channel FM carrier using either conventional 12.5 kHz FM, 25 kHz
FM, C4FM, or compatible quadrature phase shift keying (CQPSK) modulation. The receiver demodulates analog or
digital voice and data signals. The radio circuitry receives clear messages while operating in secure mode, and
secure messages while in the clear mode, if encryption is enabled.
5.3.2.2
Receive Squelch
5.3.2.2.1 Analog Receive Squelch
There are 3 types of analog receive squelch:
Type
Carrier (noise)
CTCSS
DCS
Description
Squelch is opened on any intelligible analog signal
Squelch is opened on any analog signal having the correct CTCSS tone
Squelch is opened on any analog signal having the correct DCS variable
5.3.2.2.2 Digital Receive Squelch
There are 4 types of digital receive squelch:
Type
Monitor
Normal
Selective
Individual call
Description
Squelch is opened on any intelligible digital signal. The NAC and talkgroup ID do not
have to match
Squelch is opened on any digital signal having the correct NAC
Squelch is opened on any digital signal having the correct NAC and TGID
Squelch is opened on a digital signal having a TGID of 0000 (hex) and a user ID matching
that of the receiving radio
5.4 Communication Security
The radio is capable of secure communication by means of type-3, software-based encryption, and is fully
compatible with any radio using Project 25 DES encryption. When the radio is operating in the secure mode, the
transmission of all tone squelch signals is disabled.
5.4.1
Algorithms
The radio is capable of single-bit cipher feedback (SBCF) DES (compatible with other manufacturers) 25 kHz
channels.
5.4.2
Keyfill
Keyfill is accomplished through the radio accessory connector using the PC programmer. The PC programming
cable is used to load the keys. The radio can store up to 16 encryption keys. The radio retains encryption keys until
they are rewritten or zeroized.
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5.4.3
Zeroize
The radio can be programmed using an optional, external emergency key to zeroize all encryption keys. Using the
programming menu, the radio can also zeroize all encryption keys, or selectively zeroize individual encryption keys.
The emergency key is programmed using the PC programmer.
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CHAPTER 6: SERVICING THE RADIO
6.1 General
There are no user serviceable parts in the Guardian radio. Return it for servicing to the manufacturer after
requesting an RMA number. Attempts to service the Guardian radio by non-authorized personnel voids the
warranty.
6.2 Self-Test at Power Up
At radio switch-on, the H8 controller executes a number of tests to confirm correct operation. Any errors are
reported to the user through displayed error messages and logged in the Flash. The tests implemented include:
•
•
•
•
•
•
•
•
Flash checksum CRC
RAM read and write
FPGA configuration
DSP host interface
Keypad interface to AVR
DC bus interface
Transceiver EEPROM interface
Synthesizer lock tests top and bottom frequencies, lock time, etc.
6.3 Caution
Repair of some parts of this unit require special tools and soldering techniques not normally available in a field
service environment. DWC highly recommends the module subassemblies be returned to the factory for service.
Damage can easily occur from repair attempts by non-trained personnel.
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CHAPTER 7: TROUBLESHOOTING
7.1 Introduction
This chapter is included to help qualified service personnel troubleshoot and repair the Guardian radio. If questions
or problems arise, contact Datron Technical Support Services Group, Datron World Communications Inc., 3030
Enterprise Court, Vista, CA 92083, or phone (760) 597-3755, or email to: guardianservice@dtwc.com. For
additional troubleshooting information, refer to the following sections of this manual:
•
•
•
•
Chapter 2: Hardware Theory of Operation
Chapter 3: Software Theory of Operation
Chapter 4: Installation, Adjustment and Operation
Chapter 11: Schematics
This chapter contains basic functional tests. Once the problem is corrected, restart the tests.
7.2 Radio Functional Tests
The tests in this chapter require the radio to be tested as programmed. It is best to program all 3 auxiliary buttons to
Hi/Lo power, the emergency button to emergency, and the toggle switch to zone select. Program the radio with
eighteen channels, 3 zones, and 1 bank. Put 16 channels in zone 1, 1 channel in zone 2, and 1 channel in zone 3. For
all of the channels, use assigned transmit and receive frequencies, turn transmit squelch off, and set receive squelch
to carrier, level 8. When more than one remove and receive tasks are shown in a block, they are listed in order from
most to least probable for fixing the problem. It is recommended that the remove and repair tasks are tried one at a
time, and the radio re-tested until the problem is fixed.
The tests outlined below provide an overall check of the radio to ensure it is working properly.
7.2.1
Power-On Test
This test ensures that the radio turns on, the latest software version number briefly appears, a beep is heard, and an
operational screen appears on the LCD.
7.2.2
Buttons and Switches Test
This test ensures that the PTT, auxiliary buttons, toggle switch, emergency key, keypad, on/off/volume switch, and
channel switch work.
7.2.3
Transmit Test
This test ensures the radio has the required transmit power, frequency accuracy, and deviation.
7.2.4
Receive Test
This test ensures the radio LED works, a 1 kHz tone is heard, and that SINAD is within specified limits.
7.2.5
Audio Test
This test ensures that the radio’s internal speaker and microphone are working. If the radio fails this test, please
contact Datron for radio servicing.
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7-2
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CHAPTER 8: DEFINITIONS
Alert Mode: Display and audio properties are used when the emergency key is pressed. In normal mode, the display
flashes EMERGENCY and an audio tone is heard. In silent mode, the display is blank and no audio tone is heard.
Analog-to-Digital Converter (ADC): An electronic device for converting data from analog to digital form for use
in electronic equipment.
Backlight: The light behind the keypad and LCD enables the keys and LCD to be visible in dark conditions.
Backlight Delay: The time the backlight remains on after the last keypad activity.
Bandwidth (BW): A small range of frequencies around a transmit or receive frequency in which a message can be
received or transmitted.
Bank: A group of zones. There are up to 4 banks per radio. Up to 16 zones can be distributed through these
4 banks.
Channel: A memory location with defined receive, transmit, squelch, modulation, and power settings. There are
256 channels per radio.
Channel Locked: An indicator informing that channel settings cannot be programmed using the LCD and keypad.
The settings can only be changed using the PC programmer.
Channel Scan: Scans all channels on the scan list in a given 16-channel zone. The scan starts on the home channel,
checks each channel in the scan plan, returns to the home channel, and then scans each channel in the scan plan.
Common Air Interface (CAI): The CAI standard allows interoperability within any Project 25 system provided
they are all in the same frequency band.
Continuous Tone-Controlled Squelch System (CTCSS) Tone: A sub-audible tone superimposed on an analog
signal to reduce interference from traffic and background noise.
Digital Coded Squelch (DCS): A digital variable superimposed on a digital signal to reduce interference from
traffic and background noise.
Digital Signal Processor (DSP): Handles all signal-processing functions.
Digital to Analog Converter (DAC): A device that takes a digital value and outputs a voltage that is proportional to
the input value.
Dual-Tone Multiple-Frequency (DTMF): A signaling scheme used by the telephone system in which two-voice
band tones are generated for each keypad key press.
Global Search: Scans all frequencies programmed into the radio, regardless of scan list designation.
Initial Synchronization: The length of time required for the radio to perform encryption synchronization.
Microprocessor Unit (MPU): A computer’s entire CPU is contained on one (or a small number of) integrated
circuit.
Monitor Receive Squelch: The radio receives any intelligible analog transmission.
Monitor Timer: The amount of time the radio stays on a channel picked up during the scan and before the radio
reverts back to scan mode.
Network Access Code (NAC): Selective squelch for digital mode. The primary purpose is to allow the user access
to a repeater network. In radio-to-radio communications, these codes are used to eliminate interference from other
traffic and background noise.
Normal Receive Squelch: The radio receives any transmission having the correct NAC.
Priority 1 Scan: Priority 1 channel is sampled during scanning, receive of an active channel, or standby. Activity
on the priority1 channel overrides all other modes except emergency.
GUARDIAN
VHF
110W
MOBILE
8-1
Priority 2 Scan: Priority-2 channel is sampled in a similar fashion to the priority-1 channel. Activity on the
priority-2 channel overrides all other modes except emergency and priority 1.
Receive Only Channel: A feature that does not allow outgoing transmissions on the channel. It is used for channels
in which transmission is prohibited (i.e., weather channels). If PTT is pressed on a receive-only channel, RX ONLY
appears on the display.
Receiver/Exciter/Control Module (RECM): Transceiver module containing all radio functions except RF/audio
amplifiers and display/keypad circuitry.
Repeater Delay: A delay timer used to prevent a radio from receiving its own transmission from a tactical repeater.
Scan Delay: The amount of time the scanner dwells on an active receive channel after the carrier is dropped. This
prevents another message from being received before a response can be made.
Scan Reply: If a PTT press interrupts the scan delay timer, this is the amount of time allowed to ensure a reply to a
received message.
Scan List: A group of channels in a zone that are designated as active scan list channels. Channels are added or
deleted from the scan list using the PC programmer or the radio keypad.
Scan Revert Channel: The transmit channel that the radio reverts to when PTT is pressed during or following a
scanned message.
Search Mode: The radio scans for and opens on carrier only regardless of CTCSS, DCS, or the digital ID.
Selective Receive Squelch: The radio receives any transmission having the correct NAC and TGID.
Shadow Channel: The radio of primary channels, each of which can have up to 7 shadow channels. A shadow
channel has the same transmit and receive frequencies, options, and transmit power levels as its primary channel.
Individual shadow channels can be configured for different channel types (analog or digital), BW (12.5 or
25 kHz for analog channels), squelch modes, P25 NACs (digital channel only), and encryption key (only one primary
or shadow channel can have CVSD DES enabled). When properly configured, shadow channels can be created to
allow a user to hear all transmissions on a receive/transmit frequency regardless of channel type, BW, squelch mode,
or encryption. Shadow channels are created and their settings edited using the PC programmer.
Talk Group Identifier (TGID): Selective squelch for the digital mode, used to group users into functional teams.
Transmit Inhibit and Override: A feature that stops users from talking over other radio conversations. There are
three options: CARRIER prevents transmission if any activity is detected on the channel, TONE prevents
transmission on an active channel with a squelch code other than your own, and NAC prevents transmission on an
active channel with the same NAC. There is a quick-key override feature available that allows a user to override the
transmit inhibit state by quick-keying the radio (i.e., 2 PTT presses within a short time frame).
Transmit Timeout: Prevents inadvertent or prolonged transmit operations.
User Interface: The same as a man-machine interface.
Zone: A group of channels. There is a maximum of 16 zones per radio and each zone can contain up to 16 channels.
Three zones can be selected using the toggle switch or 16 zones selected by the radio keypad.
Zone Scan List: A group of zones in a bank designated as active scan list zones. Zones are added or deleted from
the scan list using the PC programmer or the radio’s keypad.
8-2
GUARDIAN
VHF
MOBILE
CHAPTER 9: SIGNAL TONES
Tone
Brief low-pitched
Signal
Key press error
Failed power on self-test (POST)
Transmit time-out warning
Empty channel warning
Steady low-pitched
Transmit time-out timed out
Transmit inhibit
Invalid mode
Radio locked
Brief medium-pitched
Repeated medium-pitched
Brief high-pitched
Repeated high-pitched
GUARDIAN
VHF
Key press
Radio passed POST
Clear voice received
Emergency call state
Key error
Low dc supply voltage
Individual call
110W
MOBILE
Cause
Invalid key pressed
Radio fails POST
Time-out about to interrupt PTT
No RX/TX frequencies programmed for the
channel
Transmit time is exceeded and PTT still pressed
PTT switch is pressed and there is activity on the
transmit channel
No programmed data on the selected channel
Radio locks after 3 consecutive wrong password
attempts
Valid key press is accepted by the radio
Radio passed POST
Radio is receiving a clear signal
Emergency button is pressed
Encryption is selected but no key is present
DC supply voltage falls below a preset value
An individual call is received
9-1
9-2
GUARDIAN
VHF
MOBILE
CHAPTER 10:
10.1
CONNECTOR PINOUTS
Accessory Connector Pins and Functions
Pin
Signal Name
RS232_RXD
RS232_RTS
SERIAL_CLOCK
RS232_CTS
PC_232RXD
SQUELCH_INF
GND
EXTERNAL_SPEAKER_N
EXTERNAL_PTT/KID
10
11
7.7V
EXTERNAL_MIC/WE
12
13
GND
INTERNAL_SPEAKER_P
14
15
16
PTT_SWITCH
RS232_DTR
PC_232TXD
17
RS232_TXD
18
19
20
21
22
WRU_MONITOR
EXT_10W_SPEAKER_N
EXT_10W_SPEAKER_P
EXTERNAL_MIC_BIAS/KEY
EXTERNAL_SPEAKER_P/KLD
23
24
EMERGENCY_SWITCH
IGN_SW
25
INTERNAL_SPEAKER_N
GUARDIAN
VHF
110W
Description
Receive data line output (DCE), RS232 level
(>+3V=ZERO, <-3V=ONE)
Data port control input (DCE), RS232 level (>+3V=ON, <-3V=OFF)
Synchronous clock output to PC terminal (DCE), RS232 level
(>+3V=ZERO, <-3V=ONE)
Data port control output (DCE), RS232 level (>+3V=ON, <-3V=OFF)
Programming receive data line output (DCE), RS232 level
(>+3V=ZERO, <-3V=ONE)
Squelch, low on valid receive signal, 7.8V squelched
Ground
Balanced audio output from RECM, 500 mW into 8 ohms
PTT input asserted by voltage closure to ground or pseudo-random key
insert data, LVTTL level input
Test point for internal regulated voltage supply
Microphone input or key transfer indicator input, asserted by voltage
0.8 Vdc
Ground
Balanced audio input from external device; can override RECM audio
output signal
PTT input asserted by voltage closure to ground
Data port control input (DCE), RS232 level (>+3V=ON, <-3V=OFF)
Programming transmit data line input (DCE), RS232 level
(>+3V=ZERO, <-3V=ONE)
Transmit data line input (DCE), RS232 level
(>+3V=ZERO, <-3V=ONE)
Voltage input identifies external device
Balanced audio output for external 10W 4-ohm speaker
Balanced audio output for external 10W 4-ohm speaker
Microphone bias or bi-directional key data, LVTTL levels
Balanced audio output from RECM, 500 mW into 8 ohms or LVTTL
low-output level when keyloader is connected
Active low control to transmit emergency signal
Power switch override input. Ground forces off, open enables switch
Balanced audio input from external device; can override RECM audio
output signal
MOBILE
10-1
10.2
Power Connector Pins and Functions
Pin
Signal Name
BATTERY
Description
Battery power
GROUND
Ground
IGN_SW
Ignition switch
EXTERNAL_10W_SPEAKER_N External speaker
EXTERNAL+10W_SPEAKER_P
External speaker
BATTERY
Battery power
GROUND
Ground
GROUND
Ground
EMERGENCY_SWITCH
Emergency switch
10.3
Microphone Jack Connector Pins and Functions
Pin
Signal Name
EXTERNAL_MIC_BIAS/KEY
Description
Keyload line
GROUND
Ground
INTERNAL_MIC
Microphone audio
EXTERNAL_MIC/WE
Keyload line
PTT_SWITCH
Push-to-talk line
BIAS(+)
Microphone power
EXTERNAL_SPEAKER_P/KLD
Keyload line
EXTERNAL_PTT/K1D
Keyload line
10-2
GUARDIAN
VHF
MOBILE
CHAPTER 11:
GUARDIAN
VHF
110W
MOBILE
SCHEMATICS
11-1
J9
10
REV
ECN
02-0128
DESCRIPTION
DATE
BB
RELEASE
APPR
02-19-02
E1
V3.3_LCD
LCD_RESET_N
LCD_DATA_MODE
+7.7V
C1
.01
C2
LCD_TX
LCD_CLOCK
LCD_CS_N
.01
E2
LCD_BACKLIGHT
080010002
C3
.01
PART OF LCD MODULE 320803
KEYPAD_SCAN_OUT_1
KEYPAD_SCAN_OUT_2
KEYPAD_SCAN_OUT_3
KEYPAD_SCAN_IN_1
P13
10
11
12
13
14
15
16
17
18
19
20
S1
S2
S3
MENU KEY 1
MENU KEY 2
KEYPAD_SCAN_IN_2
V3.3_LCD
LCD_RESET_N
LCD_DATA_MODE
LCD_TX
LCD_CLOCK
LCD_BACKLIGHT
LCD_CS_N
AUXILLARY_SWITCH_1
AUXILLARY_SWITCH_2
AUXILLARY_SWITCH_3
+7.7V
KEYPAD_SCAN_OUT_1
KEYPAD_SCAN_OUT_2
KEYPAD_SCAN_OUT_3
KEYPAD_SCAN_IN_1
KEYPAD_SCAN_IN_2
MENU KEY 3
S4
ENTER
S5
AUXILLARY_SWITCH_1
AUXILLARY_SWITCH_2
AUXILLARY_SWITCH_3
MENU KEY 1
S6
MENU KEY 1
S7
MENU KEY 1
620171
3030 Enterprise Ct.
Vista, CA 92083
(760)597-3777
Title:
Schematic
SCHEMATIC, KEYPAD/DISPLAY
Size:
Drawn:
ABE SABET
Date:
04-12-01
Appr:
Date:
File: 994466A.Sch
Drawing Number:
Rev:
994466
Date: 14-May-2002 Time: 11:06:32 Sheet
1 of 1
REV
EXTERNAL AUDIO AMPLIFIER
10K
47uF,20V 47uF,20V
1nF
R13
10k
+IN2
OUT2
Vref
BS2
R16
10k
R3
--IN1
+IN1
C6
1uF/25V
13
C5
1uF/25V
10k
R33
10k
BS1
OUT1
R4
0ohm
INT_5W_SPEAKER_P
TDA1516BQ
12
R15
EXTERNAL_10W_SPEAKER_N
0ohm
RR
+IN2
OUT2
Vref
BS2
GND2
10k
RR
C4
1uF/25V
R14
EXTERNAL_10W_SPEAKER_P
0ohm
R5
0ohm
INT_5W_SPEAKER_N
R2
M/SS
Vp
M/SS
GND1
R1
200k
J2
TDA1516BQ
13
C1
1uF/25V
C22
47uF,20V 47uF,20V
U2
BS1
OUT1
R8
7.8Vsw
3.3V
+IN1
C3
1uF/25V
12
R21
10k
--IN1
GND2
R6
10k
R9
10k
C21
0.1uF
C8
10k
C2
1uF/25V
APPR
SWBAT
C15
R18
10k
U1
10k
10
11
12
13
14
15
16
17
18
19
20
R17
C20
10
11
C7
1nF
R7
INTERNAL_SPEAKER_P
INTERNAL_SPEAKER_N
613507
C19
0.1uF
10K
DATE
10
R10
C14
Vp
RS232_RXD
PC_232RXD
RS232_RTS
SERIAL_CLOCK
RS232_CTS
RS232_DTR
IGN_SW
EMERGENCY_SWITCH
PC_232TXD
RS232_TXD
WRU_MONITOR
EXTERNAL_MIC_BIAS/KEY
EXTERNAL_SPEAKER_P/KLD
EXTERNAL_MIC/WE
EXTERNAL_PTT/KID
EXTERNAL_SPEAKER_N
VBAT_TP
GND1
10
11
12
13
14
15
16
17
18
19
20
10k
R11
10k
R19
10k
AUDIO_INTERNAL_DISABLE
11
J1
DESCRIPTION
INTERNAL AUDIO AMPLIFIER
SWBAT
R12
AUDIO_EXT_DISABLE
ECN
U6A
PTT_SWITCH
SQUELCH_INDICATOR
INTERNAL_SPEAKER_N
INTERNAL_SPEAKER_P
AUDIO_EXT_DISABLE
AUDIO_INTERNAL_DISABLE
INT_5W_SPEAKER_P
INT_5W_SPEAKER_N
LED_TX
PA_PTT
TP21
LM2903
U6B
BIAS
LM2903
7.8V
R20
100k
ON/OFF
613507
R31
7.8Vsw
0OHM
R40
10k
R66
R28
R29
DNP
10k
100
C38
Q1
2N7002
FB1
7.8Vsw
3.3V
VBAT
SWBAT
R67
7.8V
7.8Vsw
VBAT
SWBAT
C26 C27 C28 C29 C30 C31 C32 C35 C36 C38 C39 C40
100pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF
FB4
RS232_RXD
FB24
PTT_SWITCH
FB5
FB6
FB7
FB8
FB9
FB10
FB11
FB12
FB13
RS232_RTS
RS232_DTR
SERIAL_CLOCK
PC_232TXD
RS232_CTS
RS232_TXD
PC_232RXD
WRU_MONITOR
SQ_INF
FB14
FB15
FB16
FB17
FB18
FB19
FB20
FB21
C43
C44
C45
C46
C47
C48
C49
C50
Q9
MMBT2222
R23
1k
R25
6.2K
R26
10k
R24
1k
R37
0ohm
R27
300
7.8Vsw
R43
0ohm
Q16
MMBT2222
EXTERNAL_10W_SPEAKER_N
R44
100K
7.8Vsw
C24
1uF/25V
EXTERNAL_SPEAKER_N
EXTERNAL_MIC_BIAS/KEY
EXTERNAL_PTT/KID
EXTERNAL_SPEAKER_P/KLD
EXTERNAL_10W_SPEAKER_P
R30
10k
U4A
TP21
R65
100k
PTT_SWITCH
LM2903
7.8Vsw
R39
1.27k-1%
R57
PA_PTT
INTERNAL_SPEAKER_N
INTERNAL_SPEAKER_P
C54
1nF
R38
2.67K-1%
Q5
2N7002
7.8Vsw
EMERGENCY_SWITCH
EXTERNAL_MIC/WE
IGN_SW
FB22
FB23
C42
0OHM
Q14
2N7002
C52
100pF
1nF
0OHM
Q15
2N7002
Q13
2N7002
OSMT
LED_TX
R42
R64
100k
D3
4148
C41
J4
R45
14
15
16
17
18
19
20
21
22
10
23
11
24
12
25
13
610458
C12
7.8Vsw
7.8V
R63
100k
J6
E2
PAD
LM2904
0OHM 51.1K-1%
3.3V
PANEL MNT
C10
1nF
Q8
10K/10K
R41
C9
1nF
R46
100k
U3A
R22
10k
J3
2.7uH
R48
10k
DNP
E1
PAD
L1
FB2
U4B
R53
10k
0OHM
C51
LM2903
R54
1.82K-1%
100pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF 100pF
R55
560
7.8Vsw
U3B
SWBAT
BIAS
VBAT
R60
R68
R69
270
10k
VBAT_TP
U5
LM350T
PF1
10uH
C25
.01uF
7,8
D1
1N6278
5,6
J5
D4
1N6278
FB3
R35
10k
EMERGENCY_SWITCH
C34
100pF
+Vin
Vout
7.8Vsw
ADJ
C53
10uF
C55
1uF/25V
C16
0.1uF
R50
2.67K
C82
1uF/25V
C56
1uF/25V
R62
10K
C57
C11
10uF
FB25
IGN_SW
C13
1nF
R56
1.05K,1%
C58
1nF
DNP
Q10
IRF7328
ON/OFF
Q3
MMBT2907
Q2
MMBT2222
R47
100K
Q11
2N7002
R51
12.7K
R49
1.05K,1%
Q7
2N7002
ON/OFF
R34
10k
SWBAT
SWBAT
PCB:738534
BOM:125-50220
SWBAT
EXTERNAL_10W_SPEAKER_N
EXTERNAL_10W_SPEAKER_P
C33
100pF
C37
100pF
C17
0.1uF
VCC
GND
U3C
LM2904
C18
0.1uF
3030 Enterprise Ct.
Vista, CA 92083
(760)597-3777
U4C
LM2903
C23
0.1uF
U6C
LM2903
Title:
Schematic
AUDIO AMP BD, GUARDIAN 100W MOBILE
610457
R36
10k
550044
LM2904
Q12
IRLML6302
L2
R52
10k
10k
R32
10k
7.8V
Size:
FD3 FD2 FD1
Drawn:
Date:
Appr:
Date:
File: 994478A.Sch
Drawing Number:
Rev:
994478
Date: 14-May-2002 Time: 10:55:16 Sheet
1 of 1
REV
C27
.01uF
DESCRIPTION
DATE
APPR
C38
1nF
C62
C63
47uF,20V 47uF,20V
Q6
DTA114EKA
ECN
C15
1uF/25V
VCC
U3C
LM2904
GND
C33
Q5
2N7002
DNP
R40
DNP
68k
1k
R8
0.01ohm-1%
LM2904M
15K
U5A
R16
4.99K
R73
15K
DNP
R78
DNP
R9
R13
100K
51.1K
Q1
TPC8106-H
Q17
TPC8106-H
Q2
TPC8106-H
Q18
TPC8106-H
R15
10k
U7A
LM2904
RF_IN
C54
18pF
C95
2.2pF
L3
RF_OUT
C66
.001uF
U9
701363
C55
6.8pF
C70
10pF
C72
DNP
74nH
L7
C43
10pF
C73
DNP
C71
12pF
68nH
C81
DNP
C57
DNP
100k
5.62K 1%
MMBD4148
100pF
MMBD4148
C3
1nF
M68702H
C67
.001uF
R61
D5
R20
Vref
D6
R28
0ohm
R79
R12
10k
R11
Vdet
DNP
Q21
2N7002
R59
20.5K
C37
Vin-
10k
R2
100k
Q9
IRF4905
C16
1uF/25V
DNP
C14
0.1uF
U3A
LM2904
R77
U5B
C1
100pF
U1
DNP
LM2904M
R70
C26
.01uF
C11
D2
MMBD4148
Vtemp
OUT
R10
4.99K
DNP
Vin+
V+
GND
C10
C94
2.2pF
C17
1uF/25V
R34
7 1k
DC2
R32
DC1
R3
GND
C28
.01uF
U3B
LM2904
R48
Vdet
100k
Q11
2N7002
SWBAT1
C100
10uF
L1
115uH
SWBAT2
D9
1N6278
E3
CHASSIS
GND
C41
1nF
C64
C65
47uF,20V 47uF,20V
C31
.01uF
Q8
DTA114EKA
D10
1N6278
E2
C20
Q3
Q19
TPC8106-H TPC8106-H
VCC
1uF/25V
U4C
LM2904
GND
C34
R30
0ohm
DNP
R22
10k
R81
R80
DNP
1nF
DC2
M68702H
RF_IN
C58
18pF
C76
2.2pF
L2
RF_OUT
C68
.001uF
U10
701363
C19
0.1uF
R18
Vdet
20.5k
D7
C42
6.8pF
C56
10pF
C60
DNP
74nH
L4
C59
10pF
C61
DNP
C74
12pF
68nH
C77
DNP
C78
DNP
R19
10k
C4
100pF
MMBD4148
Vref
DNP
R54
30.1K
U8A
LM2904
D3
C44
DNP
R49
DNP
MMBD4148
68K
R45
100k
D1
R25
Vdet
R52
10K
VR1
10K/11T
C105
1nF
R26
1k
MMBD4148
C103
6.8pF
R47
100
C106
DNP
R14
330
C80
150pF
C82
150pF
C84
4.7pf
C83
DNP
R75
C79
8.25k
R46
2.7K
R71
1uF/25V
100-1/2W
D8
R44
MMBD4148
100
R64
150
R65
150
E7
R17
R23
R24
150-1/2W 150-1/2W 150-1/2W
K1
TX2SA-5V-X
E6
R92
R29
R35
R38
150-1/2W 150-1/2W 150-1/2W
T1
CURRENTXFMR
R67
150
R60
150
R72
100-1/2W
J2
610551
10
ANTENNA
0ohm
SWBAT1
SWBAT1
U6A
R31
1k
C45
DNP
R41
1k
LM2904
FB2
FB
LM35
C23
1uF/25V
D15
6.8V
U12
3 R36
R6
100k
U6B
LM2904
SWBAT2
1k
LM35
TEMP SENSOR
C32
C8
.01uF 100pF
Vtemp
D11
MMBD4148
R87
SWBAT1
12
6.8V
C50
1nF
R83
DNP
R50
10ohm
R66
0ohm
1K
FB5
FB
SWBAT2
R88
R58
1.8K
20.5K
D13
6.8V
C36
100pF
U7B
R21
7.5K
R37
20.5K
LM2904
R51
10ohm
Q12
2N7002
C49
1nF
R62
100k
GND
C7
1uF/25V
VCC
GND
C24
1uF/25V
VCC
GND
U7C
LM2904
C25
1uF/25V
VCC
GND
U8C
LM2904
C35
1uF/25V
Q13
MMBT2222
U6C
LM2904
SWBAT2
VCC
GND
VCC
U5C
LM2904
U11C
LM2904
Q4
MMBT2222
U8B
LM2904
C5
1uF/25V
FB3
FB
R69
10k
1nF
E5
E4
12
K2
TX2SA-5V-X
C52
1nF
D14
R27
10k
6.8V
C51
1nF
Vref
SWBAT2
RADIO
R86
5.62k
SWBAT1
J1
080002001
C53
10
C9
100pF
R85
6.19k
SWBAT1
C46
1nF
R84
SWBAT2
D12
402k
Q22
2N7002
C21
1uF/25V
R82
R74
15K
U11A
C29
.01uF
C40
Q10
IRF4905
1k
COAX BYPASS-WHEN INSTALLED
15K
LM2904M
R56
4.99K
7R39
C69
.001uF
100k
10k
C75
2.2pF
C22
1uF/25V
C13
DNP
MMBD4148
R5
R4
100k
LM2904M
U11B
C12 6
DNP
Vtemp
U4A
LM2904
R57
R76
1k
C30
.01uF
DNP
C2
100pF
OUT
R43
4.99K
68K
D4
Vin-
Vin+
V+
GND
U2
DNP
R55
0.01ohm-1%
R33
R7
10k
R89
U4B
LM2904
DNP
R42
R1
10k
DC1
Q7
2N7002
Q20
TPC8106-H
GND
Q16
TPC8106-H
BATT-
C18
1uF/25V
BATT+
C98
0.1uF
C39
1nF
E1
FB4
FB
L12
2.7uH
Q15
MMBT2907
C99
0.1uF
R63
100k
C47
1nF
C48
1nF
BOM:125-50110
PCB:738536
Q14
MMBT2222
3030 Enterprise Ct.
Vista, CA 92083
(760)597-3777
C6
R68
10k
1uF/25V
Title:
R53
10k
Schematic
GUARDIAN MOBILE, 110WPA
Size:
FD3 FD2 FD1
FDU FDU FDU
Drawn:
Date:
Appr:
Date:
File: 994483A.sch
Drawing Number:
Rev:
994483
Date: 14-May-2002 Time: 10:56:49 Sheet
1 of 1
REV
ECN
DESCRIPTION
DATE
APPR
J2
10
11
12
13
14
15
16
17
18
19
20
RS232_RXD
PC_232RXD
RS232_RTS
SERIAL_CLOCK
RS232_CTS
RS232_DTR
IGN_SW
EMERGENCY_SWITCH
PC_232TXD
RS232_TXD
WRU_MONITOR
EXTERNAL_MIC_BIAS/KEY
EXTERNAL_SPEAKER_P/KLD
EXTERNAL_MIC/WE
EXTERNAL_PTT/KID
EXTERNAL_SPEAKER_N
3.3V
E3
PAD
3.3V
C20
1uF/16V
R17
KEYPAD_SCAN_IN_1
R18
47K
Q1
DTA144EK
VBAT
Q15
2N7002
1M
Q8
2N7002
10k
J6
VOLUME_SWITCH_1
10K
3.3V
3.3V
C38
DNP
Q11
DTA114EKA
Q6
2N7002
3.3V
613507
SPEAKER
INT_5W_SPEAKER_P
7.8V
10k
R8
(ESCAPE)
VBAT
1k
R19
10k
R16
10k
3.3V
R3
ON/OFF
ON/OFF
7.8Vsw
R30
DNP
Q12
DTA114EKA
R31
DNP
R32
DNP
610217
INT_5W_SPEAKER_N
VOLUME_SWITCH_2
KEYPAD_SCAN_IN_2
J3
10
11
12
13
14
15
16
17
18
19
20
(ENTER)
PTT_SWITCH
SQUELCH_INDICATOR
INTERNAL_SPEAKER_N
INTERNAL_SPEAKER_P
AUDIO_EXT_DISABLE
AUDIO_INTERNAL_DISABLE
INT_5W_SPEAKER_P
INT_5W_SPEAKER_N
LED_TX
PA_PTT
TP21
7.8Vsw
47K
Q3
DTA144EK
R12
100k
Q7
2N7002
INTERNAL_PTT
FB
47K
Q14
DTA114EKA
Q5
2N7002
PTT_SWITCH
Q18
2N7002
47K
ON/OFF
Q2
DTA144EK
R20
10k
10K
C31
D3
7.8Vsw
R10
100K
R33
RED
100
PA_PTT
R11
100K
GRN
035500004
Q16
2N7002
Q10
DTA144EK
47K
7.8V
LED_GREEN_N
R59 DNP
LED_TX
R22
1M
R58 0OHM
LED_RED_N_SYS
R60 0OHM
1uF/16V
R61
10k
E2
PAD
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C14 C15 C16 C17 C18 C19
100p 100p 100p 100p 100p 100p
C13
DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP
J1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Q19
DTA144EK
10K
VOLUME_SWITCH_4
3.3V
613507
VOLUME_SWITCH_1
R9
10K
SW3
ON/OFF
KEYPAD_BACKLIGHT_N
KEYPAD_SCAN_OUT_1
KEYPAD_SCAN_OUT_2
KEYPAD_SCAN_OUT_3
KEYPAD_SCAN_IN_1
KEYPAD_SCAN_IN_2
KEYPAD_SCAN_IN_3
KEYPAD_SCAN_IN_4
KEYPAD_SCAN_IN_5
KEYPAD_SCAN_IN_6
LCD_BACKLIGHT_N
FB1
FB2
FB3
FB4
FB5
FB6
VOLUME_SWITCH_2
R36
R62
10K
R38
100
100
R35
R37
100
100
U1
C21
0.1uF
Q20
2N7002
INTERNAL_PTT
AUXILLARY_SWITCH_3
AUXILLARY_SWITCH_2
AUXILLARY_SWITCH_1
FB
VOLUME
VOLUME_SWITCH_4
3.3DTMF
7.8V
3.3V
FB
R23
IGN_SW
1M
R55
1M
249
R54
150
CHANNEL_SWITCH_1
SW4
CHANNEL_SWITCH_2
CHANNEL_SWITCH_1
CHANNEL_SWITCH_2
CHANNEL_SWITCH_3
CHANNEL_SWITCH_4
CHANNEL_SWITCH_3
EMERGENCY_SWITCH
CHANNEL_SWITCH_4
R39
100
510038
D2
4148
Q17
2N7002
R44
100k
C40
47uF,20V
VOLUME_SWITCH_1
VOLUME_SWITCH_2
VOLUME_SWITCH_3
VOLUME_SWITCH_4
TOGGLE_SWITCH_1
TOGGLE_SWITCH_2
FB8
FB
FB11
C22
0.1uF
R52
INTERNAL_MIC
510038
FB
LM317
IN
NC
OUT2OUT7
OUT3OUT6
ADJ
NC
R53
270
ON/OFF
VOLUME_SWITCH_3
FB10
7.8Vsw
Q21
IRLML6302
7.8V
INTERNAL_PTT
FB12
+3.3V_LCD
FB
LCD_CS_N
LCD_RESET_N
LCD_DATA_MODE
INTERNAL_SPEAKER_P
INTERNAL_SPEAKER_N
1k
1k
FB9
LCD_CLOCK
LCD_TX
R1
R2
E8
PAD
CHANNEL
3V3_LOGIC
3.3DTMF
E6
PAD
LED_RED_N_SYS
LED_GREEN_N
C25
0.1uF
U3
74HC4016
VCC
E5
PAD
DNP
0ohm
14
R24
R25
E7
PAD
1Y
EXTERNAL_MIC_BIAS/KEY
1Z
13
EXTERNAL_MIC/WE
12
2Y
2E
2Z
3E
3Y
4E
3Z
4Y
VEE
10k
1E
4Z
FB
L5
FB
L6
J5
FB
L7
FB
L8
FB
L11
DNP
C46
C47
C48
C49
C50
C51
C45
C52
100p
100p
100p
100p
100p
100p
100p
100p
PC_232RXD
R46
EXTERNAL_MIC_BIAS/KEY
C39
DNP
3.3DTMF
R43
BIAS(+)
PC_232TXD
D7
DNP
R47
C27
0.1uF
PTT_SWITCH
EXTERNAL_PTT/KID
D6
DNP
DNP
EXTERNAL_MIC/WE
EXTERNAL_SPEAKER_P/KLD
17
270k
INTERNAL_MIC
D4
12V
560
BIAS
TOGGLE_SWITCH_1
KEYPAD_SCAN_IN_4
1K
TOGGLE
C43
DNP
11
10
0ohm
VREF
VDD
Y4
Y5
Q1
GS
Q2
PD
Q3
ESt
Q4
StD
OSC1
St/GT
OSC2
11
12
13
21
14
22
3.3DTMF
C32
Y1
3.579545 MHZ
Y7
A2
Y8
A3
Y9
Y10
R29
0ohm
23
/LE
/E
Y11
Y12
Y13
12
R50
DNP
Y6
A1
1uF/16V
E10
PAD
CM88L70
A0
GND
Y14
R51
ESt
Y15
47.5k
VCC
U4
74HC4016
1Y
1Z
K2
10
13
K3
K4
K5
12
K6
1E
2Y
2E
2Z
3E
3Y
4E
3Z
4Y
K7
VEE
Y3
11
K1
0ohm
18
K8
4Z
C33
1uF/16V
R5
1K
I TOGGLE
KEYPAD_SCAN_OUT_3
7.8Vsw
11
10
KEYPAD_SCAN_IN_5
R57
330
C41
DNP
R56
330
R34
330
K*
19
3.3DTMF
RED
14
K#
13
16
SW2
AUDIO_INTERNAL_DISABLE
20
K0
C30
0.1uF
15
13
R15
100k
0ohm
AUDIO_EXT_DISABLE
KEYPAD_SCAN_OUT_2
17
K9
12
1E
D5
U5
74HC4016
1Y
1Z
47K
Q4
DTA144EK
R26
KEYPAD_SCAN_OUT_1
16
Y2
14
15
FB
L3
FB
L4
220K
IN-
Y1
VCC
621112
100k
IN+
FB
L2
ESt
L10
DNP
L1
R48
Y0
Vcc
C24
0.1uF
2Y
2E
2Z
3E
3Y
4E
3Z
4Y
VEE
.01uF
KEYPAD_SCAN_OUT_1
KEYPAD_SCAN_OUT_2
KEYPAD_SCAN_OUT_3
KEYPAD_SCAN_IN_1
KEYPAD_SCAN_IN_2
R14
24
C23
0.1uF
TOE
7.8Vsw
R13
100k
C53
INH
AUDIO
R45
DNP
VSS
FB
C29
0.1uF
U6
FB13
0ohm
R6
DNP
18
R49
220K
C54
.01uF
10
0ohm
LCD_CS_N
AUXILLARY_SWITCH_1
AUXILLARY_SWITCH_2
AUXILLARY_SWITCH_3
E9
PAD
R7
R4
4Z
KEYPAD_SCAN_IN_6
Q9
2N7002
AUDIO_EXT_DISABLE
C44
DNP
BOM: 125-50210
PCB: 738535
11
10
3030 Enterprise Ct.
Vista, CA 92083
(760)597-3777
C28
0.1uF
C26
0.1uF
14
U2
74HC4514
3.3DTMF
+3.3V_LCD
R40
SW1
R27
3.3DTMF
LCD_RESET_N
LCD_DATA_MODE
LCD_TX
LCD_CLOCK
TOGGLE_SWITCH_2
R28
7.8V
10
11
12
13
14
15
16
17
18
19
20
C42
DNP
3.3DTMF
J4
KEYPAD_SCAN_IN_3
R21
WRU_MONITOR
EXTERNAL_PTT/KID
EXTERNAL_SPEAKER_P/KLD
EXTERNAL_SPEAKER_N
SQUELCH_INDICATOR
RADIO_OFF_SC_N
SERIAL_CLOCK
RS232_RXD
RS232_TXD
RS232_DTR
RS232_CTS
RS232_RTS
PC_232RXD
PC_232TXD
610354
610669
VOLUME_SWITCH_3
FB7
7.8V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Q13
DTA114EKA
PAD
BIAS
E1
PAD
10K
E4
Title:
Schematic
GUARDIAN 100W MOBILE, CONTROL BD
Size:
FD3 FD2 FD1
Drawn:
Date:
Appr:
Date:
File: 994484A.sch
Drawing Number:
Rev:
994484
Date: 14-May-2002 Time: 10:57:49 Sheet
1 of 1
1
REVISIONS
ZONE
REV
01
DESCRIPTION
02
4.5VSW
D36
BAR43S
FL6
BEAD
D37
BAR43S
3V3LOGIC
CONTROL SIDE
D39
BAR43S
R376
6,8 7.5VT
B.MAAT
6 RADONSW
7.5VT
10/10/01
3V3LOGIC
D38
CMDSH2-3
3V3LOGIC
BOARD SPIN 2 UPDATED
3V3LOGIC
XCVR SIDE
3V3LOGIC
APPROVED
R374
100K
1%
Q49
BSS123
BATTSW
100 1%
BATTBUS 2
8 7.5VA
R385
RSSIMON 2,3
8 BATTSENSE
10 RSSI
NOTES: UNLESS OTHERWISE SPECIFIED.
1.
INTERPRET DRAWING PER MIL-STD-100.
2.
ALL RESISTANCE VALUES ARE IN OHMS,
3.
CAPACITANCE VALUES ARE IN MICROFARADS,
4.
LAST REF DES USED:
B1,C550,D69,FL6,J5,L80,P2,Q71,R580,RT1,
T2,TP24,U77,Y1
5.
REF DES NOT USED:
C20,C24,C32,C33,C35-C37,C39-C42,C44-C52,
C54,C55,C58,C60,C62-C73,C76,C79,C80,C85,
C89-C91,C93,C99,C119,C122,C147,C153,C189,C194,C197,
C198,C204,C205,C207,C208,C210-C213,C217-C221,
C232,C234,C238,C239,C243,C250-C255,C258-C266,
C272-C274,C277,C278,C280-C283,C291,C296-C300,
C313-C317,C320-C327,C329,C330,C333,C391,C394-C398,
C402-C404,C530,C533,C548,D5,D6,D22,D29-D34,D51,
J1,J4,L23,L26,L27,L29,L32-L34,L36,L54,L57-L59,L67,P1,
Q3-Q6,Q8,Q9,Q20,Q28-Q30,Q37-Q45,Q56,R13-R30,R32,
R34-R43,R45,R46,R50,R53,R54,R56,R58-R63,R88,
R90,R93,R108,R158,R161,R163-R168,R170,R174,
R176,R184,R188-R190,R192,R194,R195,R197-R202,
R205,R207,R209-R211,R216,R221,R223,R226,R228,
R231-R235,R239,R242-R249,R260,R261,R265,
R267-R271,R274,R275,R277,R278,R285,R286,R289,
R301-R305,R307-R314,R317,R318,R379,R383,R397,
R399,R402-R405,R407,R425,R438,R441-R443,R508,
R509,R519,R520,R532,TP4,TP15,TP16,TP22,TP23,U2,
U5-U10,U18,U22,U23,U25,U26,U30,U34,U38-U41,
U61,U66,U67,U72
DATE
PREPRODUCTION RELEASE
100 1%
R381
12 PATEMP
PATMON 2
100 1%
11 SYNTHLOCK
BL_KP_N 7
R387
SYNTHOOL 2
R326
10K 1%
KOUT1 7
1K
R328
1%
8 BATTCTRL
8 TXCTRL
11 20VCLK
9 EEPWP
KOUT2 7
1K
1%
R330
KOUT3 7
1K
R332
R389
/BATTOFF 5
100 1%
R391
CTX 5
100 1%
1%
R393
KIN1 7
1K
1%
MULTCLOCK 5
R334
100 1%
2,9,11 PROGCLK
2,9,11 PROGDATA
2,11 SYNTHENA
2,11 SRENA
2,9 8DACENA
KIN2 7
R336
1K
1%
KIN3 7
1K
1%
R338
KIN4 7
R340
1K
PROGCLK 2,9,11
PROGDATA 2,9,11
1%
KIN5 7
1K
SYNTHENA 2,11
R342
1%
1K
KIN6 7
6,8 4.5VSW
BL_LCD_N 7
3,10 IFOUT
SRENA 2,11
1%
8DACENA 2,9
IFOUT 3,10
MCLK 5,7
12DACENA 3,9
R406
BATTSW
3V3LOGIC
3,9 12DACENA
9 12DACCLK
3,9 12DACDATA
MTXD 5,7
3V3LOGIC
R353
/LCD_CS 5
1K
1%
C392
0.01 uF
10%
1%
LCDA0 5
C349
0.01 uF
10%
P2
80 POS
61619-80
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
51
51
52
52
53
53
54
54
55
55
56
56
57
57
58
58
59
59
60
60
61
61
62
62
63
63
64
64
65
65
66
66
67
67
68
68
69
69
70
70
71
71
72
72
73
73
74
74
75
75
76
76
77
77
78
78
79
79
80
80
1K
R357
R349
100
1%
C350
100 pF
5%
C345
100 pF
5%
1K
C346
100 pF
5%
12DACDATA 3,9
R355
/XRST 2,3,7
C343
0.01 uF
10%
DACADCCLK 3,5
47.5 1%
1%
C353
100 pF
5%
C351
100 pF
5%
C406
100 pF
5%
C393
0.01 uF
10%
2,3,4,5,6,7,8,9,10,11,12 GND_SIGNAL
C352
100 pF
5%
C408
0.01 uF
10%
R395
2.21K
1%
C407
0.01 uF
10%
C399
0.01 uF
10%
C400
0.01 uF
10%
C409
0.01 uF
10%
C405
100 pF
5%
C401
100 pF
5%
C347
100 pF
5%
SPKR+ 4
SPKR- 4
INTMIC 4
R324
PTTSW 7
1K
R325
1%
AUX3 7
1K
1%
R327
AUX2 7
1K
R329
1%
AUX1 7
1K
1%
R331
VOL1 7
1K
R333
1%
VOL2 7
1K
1%
R335
VOL3 7
1K
R337
1%
3V3LOGIC
VOL4 7
1K
1%
R339
TOG1 7
1K
R341
1%
TOG2 7
1K
1%
R364 R365 R366
10K
10K
10K
1%
1%
1%
R343
CHN1 7
1K
R344
1%
R367 R368
10K
10K
1%
1%
R369
10K
1%
7.5VT
R370
1K
1%
3V3LOGIC
CHN2 7
1K
1%
1K
R346
1K
EXTPWR
R345
1%
CHN3 7
R371
CHN4 7
10K 1%
1%
R347
J5
20 POS
SECSW 7
R348
1K
1%
EMERGSW 7
1K
R373
LEDREDN 5
LEDGREENN 5
BL_KNOB_N 7
EXTMICB/KEY 5
EXTMIC/WE 5
R350
WRUMON 2
10K 1%
EXTPTT/KID 5
EXTSPKR+/KLD 4,5
EXTSPKR- 4
R351
1%
R375
/RESET_JTAG 2,3,7
R377
R378
/STBY 2,3,5
R380
10
1%
DRXD 2
1K 1%
R382
R384
1K 1%
DTXD 2
TCK 3,5
10
1%
R386
T DI 3
R388
10
1%
TDO 5
10
1%
R390
TMSDSP 3,5
R392
10
1%
/TRST 3
R352
/RADOFF_SC 6
R354
10K 1%
100 1%
R356
R358
100 1%
10
R396
R359
100 1%
R361
R362
100 1%
2.21K 1%
JTAG/DEBUG
INTERFACE
232TXD_SC 5
100 1%
10
1%
R398
TMSFPGA 5
10
232CTS_SC 5
232RTS_SC 5
1%
R401
100K
1%
R400
56.2
1%
232DTR_SC 5
C390
100 pF
5%
PCRXD_SC 5
100 1%
R394
/W R 2,3,5
232RXD_SC 5
R360
1%
/DE 3
232CLK_SC 5
100 1%
2.21K 1%
/WP 2
1K 1%
SQL_SC 5
10K 1%
10
100 1%
10
11
12
13
14
15
16
17
18
19
20
1%
/RADON 6,7
R372
R363
PCTXD_SC 5
FL5
100 1%
EXTPWR_SC 6
C348
0.01 uF
10%
C344
0.01 uF
10%
C362
0.01 uF
10%
C372
100 pF
5%
C354
100 pF
5%
C373
0.01 uF
10%
C355
100 pF
5%
C374
47 pF
5%
C356
47 pF
5%
C375
100 pF
5%
C357
0.01 uF
10%
C376
100 pF
5%
C358
100 pF
5%
C377
100 pF
5%
C359
100 pF
5%
C378
100 pF
5%
C360
100 pF
5%
C379
100 pF
5%
C361
100 pF
5%
C363
0.01 uF
10%
C380
0.01 uF
10%
C364
0.01 uF
10%
C381
0.01 uF
10%
C365
0.01 uF
10%
C382
0.01 uF
10%
C366
0.01 uF
10%
C383
0.01 uF
10%
C384
0.01 uF
10%
C367
0.01 uF
10%
C368
0.01 uF
10%
C385
0.01 uF
10%
C369
47 pF
5%
C386
47 pF
5%
C387
0.01 uF
10%
C370
0.01 uF
10%
C388
0.01 uF
10%
BEAD
C371
0.01 uF
10%
THALES COMMUNICATIONS, INC.
This information represents intellectual property which
shall not be disclosed or released, except to comply with
contractural requirements. This information is provided
on a limited basis and does not include any rights to
manufacture, or have manufactured, any equipment
depicted therein.
EXTPWR
C389
0.01 uF
10%
C342
0.01 uF
10%
ELEC ENG.
FRACTIONS
MECH ENG.
+/QA
TREATMENT
4101421
REV STATUS
DSGNR
PART
SHEETS
DATRON
NEXT ASSY
USED ON
DRAWN
07/20/00
SCHEMATIC DIAGRAM,
CCA CONTROL/TRANSCEIVER
SIZE
SIMILAR TO
DASH
ADDITIONAL APPROVALS
DATE
FINISH
TECH DIR
OF SHEETS
TITLE
APPROVALS
CHECKED
07160101.DSN
REVISION
+/-
E. HOOKER
MFG/TEST ENG
FILENAME
THALES COMMUNICATIONS, INC.
ROCKVILLE, MARYLAND
ANGLES
DO NOT SCALE DRAWING
SOFTWARE VERSION
Orcad Capture 7.00
DECIMALS
.XX +/.XXX +/-
CONTRACT NO.
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN INCHES
TOLERANCES ARE:
DATE
NO.
APPLICATION
CAGE CODE
DWG NO
D 23386
SHEET
NONE
02
4200716
SCALE
REV
Thursday, November 15, 2001
OF
12
1
3V3LOGIC
R505
10
1%
3V3LOGIC
RSTVCC
1,3,4,5,6,7,8,9,10,11,12 GND_SIGNAL
C482
0.1 uF
10%
R506
10K
1%
U60
MAX825TEUK
/RESO
VCC
RESET
MR
RESET
/RES 5
Q66
2N7002
3 DSPWD
3V3LOGIC
GND
R514
150K
1%
R507
10
1%
3V3LOGIC
3V3LOGIC
C LKDVRVCC
O.P
C490
100 pF
5%
C495
NU
R516
182K
1%
R518
NU
TCXOCTRL
DV RINCLK
C487
0.01 uF
10%
GND
VCONT
XTALCLK
R515
82.5
1%
4 DVROUTCLK
DSPCLK 3
R568
82.5
1%
NC
FPGACLK 5
MPUCLK
C485
0.01 uF
10%
C486
1000 pF
5%
VCC
GND
XTALVCC 4
R513
221K
1%
VCC
U68
12.288 MHz
R567
82.5
1%
U71
NC7SZ14
365647
SOT23/5P
R510
10
1%
C483
0.01 uF
10%
L76
1.2 uH
5%
3V3LOGIC
Q65
BSS84TA
R512
10K
1%
C484
0.1 uF
10%
R511
150K
1%
Q67
2N7002
3 VPPCTRL
R517
150K
1%
3V3LOGIC
H8VCC
L75
BEAD
C491
0.1 uF
10%
C492
0.1 uF
10%
C493
0.1 uF
10%
C494
0.1 uF
10%
FLASHVPP
3V3LOGIC
3V3LOGIC
C489
+ 2.2 uF
10%
10V
L77
BEAD
FLASHVCC
R563
10K
1%
3V3LOGIC
H8VCC
5 KEYLOAD
17
16
15
14
13
12
91
90
89
88
87
85
84
83
82
81
80
79
78
R521
11 SRENA
R524
100K
1%
C498
0.01 uF
10%
100 1%
77
76
35
68
VREF
AVCC
VCC
VCC
VCC
36
37
38
39
40
41
42
43
45
46
47
48
49
50
51
52
27
28
29
30
31
32
33
34
3 /DSPO_CS
R564
10K
1%
/XRST 1,3,7
/BREQ 3
R580
10K
1%
/RAM_CS 3
/ RD 3
R572
10K
1%
/WR 1,3,5
/BACK 3
3V3LOGIC
R525
100K
1%
G5
B5
A2
A1
B2
232RTS_H8 5
TCXOCTRL
R530
100
1%
100 1%
9 8DACENA
ALM 4
C502
0.01 uF
10%
R531
100K
1%
R323
10K
1%
WRUMON 1
LBI 6
/MINT 7
C503
0.01 uF
10%
/HINT 3
/FPGA_CS 5
3V3LOGIC
TXDO 5
R533
4.75K
1%
R534
100
1%
DATOUT_H8 5
R535
100
1%
RXDO 5
9,11 PROGDATA
L78
BEAD
RAMVCC
PATMON 1
R528
3V3CONT
R321
10K
1%
BATTMON
C501
0.01 uF
10%
R529
100
1%
VCCQ
VCCQ
VCC
VCC
H8VCC
11 SYNTHENA
R527
100K
1%
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
ALARM INPUT?
R526
100
1%
F2
E2
G3
E4
G4
F5
E6
H6
E1
E3
F3
F4
E5
G5
F6
G6
3V3LOGIC
R522
100K
1%
R523
10K
1%
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D6
E1
5 CONFDONE
U70
NC7SZ126
365773
SC70-5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
RSSIMON 1,3
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
A3
A4
A5
B3
B4
C3
C4
D4
H2
H3
H4
H5
G3
G4
F3
F4
E4
WE#
CE#
OE#
LB#
UB#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
VCC
VCC
1 DRXD
3V3LOGIC
C538
0.1 uF
10%
AB16
AB17
AB18
AB19
53
54
55
56
58
59
60
69
70
71
72
3V3LOGIC
G1
A1
B1
C1
D1
D2
A2
C2
D7
D8
A7
B7
C7
C8
B8
A8
G8
B2
A3
B3
GND
GND
1 BATTBUS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
18
19
20
21
23
24
25
26
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
RC28F160C3BA90
365764
U64
IS62LV12816LL-70BI
365766
NC
NC
NC
NC
NC
NC
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
C500
0.1 uF
10%
+ C499
2.2 uF
10%
10V
A6
D3
E3
G2
H1
H6
B6
C5
C6
D5
E5
F5
F6
G6
B1
C1
C2
D2
E2
F2
F1
G1
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
D1
E6
1 DTXD
/FLASH_CS 3
WE#
RP#
WP#
CE#
OE#
C496
2.2 uF
10%
10V
A6
G7
G2
H5
3 /DINT
1 SYNTHOOL
1 /WP
3,6 /LBOUT
MD2
MD1
MD0
EXTAL
XTAL
STBY
RES
VPP* /RESO
NMI
3 PORT A
PORT B
U63
HD6433044SS00XI
365582
AVSS
VSS
VSS
VSS
VSS
VSS
VSS
/RESO
C4
B4
C3
F1
H2
86
11
22
44
57
65
92
/RES
75
74
73
66
67
61
62
63
10
64
93
94
95
96
97
98
99
100
PORT 9
2 PORT 8
4 PORT 7
1,3,5 /STBY
U69
NC7SZ126
365773
SC70-5
MPUCLK
C488
12 pF
5%
/RES
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
C537
0.1 uF
10%
VPP
A4
H3
H7
A5
H4
U62
GND
GND
VSSQ
VSSQ
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
R579
10K
1%
C497
0.1 uF
10%
DATIN_H8 5
C504
100 pF
5%
SOCLK 5
/EXTPTT 5,6
AB20
C505
0.01 uF
10%
6 /PWROFF
C506
0.01 uF
10%
AB[0..20] 3,5
DB[0..15] 3
3V3LOGIC
R536
4.75K
1%
R537
100
1%
9,11 PROGCLK
C507
100 pF
5%
Control MPU
Thales Communications, Inc.
Rockville, Maryland
Size CAGE Code
Dwg No.
Drawn E. HOOKER
Scale None Thursday, November 15, 2001
23386
R ev
4200716
Sheet 2
02
o f 12
1
1,2,4,5,6,7,8,9,10,11,12 GND_SIGNAL
1,2,7 /XRST
1,2,7 /RESET_JTAG
3V3LOGIC
L79
BEAD
R538
33.2K
1%
DECOUPLING CAPS MUST BE CLOSE TO DSP VCC PINS
DSPVCC
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
2 DB[0..15]
2 /RAM_CS
2 /FLASH_CS
AB18
AB19
L4
L5
L6
L7
L8
L9
L10
L11
GND
GND
GND
GND
GND
GND
GND
GND
N6
P6
A1
A14
B14
P1
P14
NC
NC
NC
NC
NC
E2
K1
VCCS
VCCS
VCCH
M4
N12
P9
VCCC
VCCC
EXTAL
CLOCK
XTAL
CLKOUT
PLL
PCAP
PINIT/NMI
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
D0
D1
D2
D3
D4
D5
D6
D7
D8
PORT A
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
AAO
AA1
AA2
AA3
RD
WR
TA
BR
BG
BB
CAS
BCLK
BCLK
MODAIRQA
MODBIRQB
MODCIRQC
MODDIRQD
RESET
H0
H1
H2
H3
H4
H5
H6
H7
PORT B
HA0
HA1
HA2
HCS/HCS
HRW
HDS/HDS
HREQ/HREQ
HACK/HACK
SC00
SC01
SC02
PORT C
SCK0
SRD0
STD0
SC10
SC11
SC12
PORT D
SCK1
SRD1
STD1
RXD
PORT E
TXD
SCLK
TI00
TIMER
TI01
TI02
TCK
TDI
TDO
TMS
TRST
DE
C4
A5
C5
B5
N5
M5
P4
N4
P3
N3
P2
N1
N2
M3
M1
M2
L1
J2
J3
K2
J1
F3
D2
C1
H3
E3
E1
F2
A2
B2
G1
B1
C2
F1
G3
G2
L3
L2
K3
C3
B3
A4
A3
B4
D3
/DINT 2
/IRQD 5
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
2 / RD
/DSPO_CS 2
/ RD 2
/W R 1,2,5
/HINT 2
VPPCTRL 2
/CODECMICMUTE 4
/CODECEARMUTE 4
232RTS/EORS_DSP 5
1.536 MHz
DACADCCLK 1,5
232TXD_DSP 5
232RXD_DSP 5
232CLK_DSP 5
DSPWD 2
232CTS/DIGSQ_DSP 5
232DTR/SYNC_DSP 5
TCK 1,5
TDI 1
TDODSP 5
TMSDSP 1,5
/TRST 1
/DE 1
R541
100
1%
CODECFSK 4
GND
GND
GND
GND
GND
GND
GND
GND
K4
K5
K6
K7
K8
K9
K10
K11
C524
100 pF
5%
R542
47.5
1%
2.048 MHz
CODECCLK 4
C525
100 pF
5%
D4
D5
D6
D7
D8
D9
D10
D11
E4
E5
E6
E7
E8
E9
E10
E11
F4
F5
F6
F7
F8
F9
F10
F11
G4
G5
G6
G7
G8
G9
G10
G11
H4
H5
H6
H7
H8
H9
H10
H11
J4
J5
J6
J7
J8
J9
J10
J11
1,2,5 /W R
R540
10K
1%
AB0
AB1
AB2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2,5 AB[0..20]
C521
0.01 uF
10%
GNDP
GNDP1
M8
P8
M9
P5
D1
N14
M13
M14
L13
L14
K13
K14
J13
J12
J14
H13
H14
G14
G12
F13
F14
E13
E12
E14
D12
D13
C13
C14
B13
C12
A13
B12
A12
B11
A11
C10
B10
A10
B9
A9
B8
C8
A8
B7
B6
C6
A6
N13
P12
P7
N7
M12
M11
P10
N11
P13
P11
N8
N10
M10
2 DSPCLK
2,6 /LBOUT
U65
XC56309GC100A
365770
C520
0.1 uF
10%
A7
C9
C11
D14
C523
.033 uF
10
C519
0.01 uF
10%
VCCD
VCCD
VCCD
VCCD
C541
12 pF
5%
R539
10K
1%
C518
0.1 uF
10%
H12
K12
L12
C522
+ 2.2 uF
10%
10V
C517
0.01 uF
10%
C516
0.1 uF
10%
VCCA
VCCA
VCCA
C515
0.01 uF
10%
C514
0.1 uF
10%
F12
H1
M7
C513
0.01 uF
10%
VCCQH
VCCQH
VCCQH
C512
0.1 uF
10%
C7
G13
H2
N9
C511
0.01 uF
10%
VCCQL
VCCQL
VCCQL
VCCQL
C510
0.1 uF
10%
M6
C509
0.01 uF
10%
VCCP
C508
0.1 uF
10%
2 /BREQ
R544
100
1%
2 /BACK
R543
10K
1%
CODECDOUT 4
1,2,5 /STBY
R545
100
1%
CODECDIN 4
C526
100 pF
5%
3V3ANALOG
R548
100
1%
R547
10
1%
ADCD IN
C527
100 pF
5%
AD CVCC
ADCD IN
14
16
1,5 DACADCCLK
C543
0.047 uF
10%
DOUT
SSTRB
COM
SHDN
VREF
CS
12
13
3V3ANALOG
U73
NU
SOT23/3P
R570
NU
15
R549
100K
1%
R551
100
1%
12DACENA 9
C531
100 pF
5%
AD CREFVCC
C532
NU
C528
+ 4.7 uF
10%
10V
REFADJ
DIN
SCLK
R553
100
1%
E4
PAD2
R552
10K
1%
C534
0.01 uF
10%
R550
NU
AD CDOUT
AGND
DGND
1,2 RSSIMON
CH0
CH1
CH2
CH3
C529
0.1 uF
10%
AD CDOUT
10
11
Vdd
R569
NU
R546
100
1%
U74
MAX1246
365695
QSOP16/025/210
3V3LOGIC
3V3LOGIC
TEST PAD
R555
100K
1%
R556
100
1%
4 55IFCOUT
12DACDATA 9
R554
10K
1%
C535
100 pF
5%
10 IFOUT
Control DSP
Thales Communications, Inc.
Rockville, Maryland
Size CAGE Code
Dwg No.
Drawn E. HOOKER
Scale None Thursday, November 15, 2001
23386
R ev
4200716
Sheet 3
02
o f 12
1
1,2,3,5,6,7,8,9,10,11,12 GND_SIGNAL
3V3ANALOG
C463
3900 pF
5%
3V3ANALOG
R483
10
1%
U57
LMC7101A
365438
R490
15K
1%
R491
221K
1%
41
40
42
11
45
46
44
17
43
36
C469
0.047 uF
10%
C472
1.0 uF
20%
C471
2.2 uF
10V
D67
BAR43C
U56
TLV320
MICGS
MICIN
DCLKR
MICBIAS
CLK
MICMUTE
DOUT
EARB
FSX
EARGS
FSR
EARA
DIN
EARMUTE
LINSEL
PDN
TSX/DCLKX
VMID
AGND
C470
0.1 uF
10%
5 EXTMIC
R488
100K
1%
C466
+ 15 uF
10%
10V
DVCC
C465
0.1 uF
10%
CODECCLK 3
14
19
21
20
16
15
26
22
CODECDOUT 3
CODECFSK 3
CODECDIN 3
DGND
1 INTMIC
CO DECVCC
3V3LOGIC
27
R489
562
1%
C467
0.1 uF
10%
R485
10
1%
L74
BEAD
C464
0.1 uF
10%
AVCC
C468
1.0 uF
20%
R487
4.75K
1%
AC ODVCC
R484
100
1%
5VMICBIAS
34
R486
5.62K
1%
C549
470 pF
10%
R492
150K
1%
3 /CODECMICMUTE
3 /CODECEARMUTE
R494
150K
1%
C473
470 pF
10%
R497
150K
1%
Q63
2N7002
-IN
+IN
C474
0.1 uF
10%
V01
SPKR+ 1
SPKR- 1
BYPASS
U58
LM4872
R499
10K
1%
SDOWN
+ C477
1 uF
10%
V02
R560
475
1%
C476
0.1 uF
10%
GND
5 SPKRON
C475
0.033 uF
10%
R559
33.2K
1%
D68
BAR43C
R498
100K
1%
5VAUDIO
5VAUDIO
R495
100K
1%
R496
15K
1%
VDD
R493
150K
1%
C478
470 pF
10%
5VLOGIC
R501
15K
1%
U59
LM4872
-IN
+IN
C479
0.1 uF
10%
V01
EXTSPKR+/KLD 1,5
EXTSPKR- 1
BYPASS
R504
150K
1%
+ C481
1 uF
10%
SDOWN
GND
5 EXTSPKRON
C480
0.033 uF
10%
R561
33.2K
1%
Q64
2N7002
D69
BAR43S
R503
100K
1%
R502
150K
1%
5VAUDIO
VDD
5VAUDIO
R500
100K
1%
2 ALM
V02
R562
475
1%
Control Audio
Thales Communications, Inc.
Rockville, Maryland
Size CAGE Code
Dwg No.
Drawn E. HOOKER
Scale None Thursday, November 15, 2001
23386
R ev
4200716
Sheet 4
02
o f 12
1
1,2,3,4,6,7,8,9,10,11,12 GND_SIGNAL
FPGAVCC
R565
10K
1%
R447
1K
1%
R448
10K
1%
R446
10
1%
L73
BEAD
R449
1K
1%
C448
0.1 uF
10%
R450
1K
1%
C451
0.1 uF
10%
C450
0.1 uF
10%
C449
0.1 uF
10%
C452
0.1 uF
10%
C453
0.1 uF
10%
3V3LOGIC
C447
+ 2.2 uF
10%
10V
D52
CMPSH-3A
2 /RES
1,2,3 /STBY
U53
EPF6016AFI100-3
365765
H2
G5
K5
D6
A6
C9
C2
K9
E10
C7
A7
A9
C8
D10
C10
E1
E2
F9
F10
B5
B6
A1
A2
A3
A4
A5
A8
A10
B1
B2
B3
B4
B7
B8
B9
B10
C1
C3
C4
C5
C6
D1
D3
D5
D8
D9
D2
K10
G2
G3
2 SOCLK
2 TXDO
2 CONFDONE
2 FPGACLK
AB20
AB16
AB17
AB18
AB19
2,3 AB[0..20]
1 /LCD_CS
3 232TXD_DSP
1,2,3 /WR
2 /FPGA_CS
1,7 MCLK
1,7 MTXD
KVLSEL
/232SHDN
1 CTX
1 SQL_SC
6 PWRHOLD
7 /KPD_CS
4 EXTSPKRON
1 /BATTOFF
1 LCDA0
/WE
PSU_CLK
LEDRED
LEDGREEN
R466
NU
3 TDODSP
R468
10
1%
C542
12 pF
5%
MSEL
nSTATUS
nCONFIG
DCLK
DATA
CONFIG_DONE
nCE
nCEO
INIT_DONE
nWS
nRS
nCS
CS
RDYnBUSY
CLKUSR
IN
IN
IN
IN
DEV_CLRn
DEV_OE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
TDO
TMS
TCK
VCC
VCC
VCC
VCC
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
GND
GND
D7
E4
E5
F6
F7
G4
E3
E8
E9
F1
F2
F3
F8
G1
G6
G8
G9
G10
H1
H3
H4
H5
H6
H7
H8
H9
H10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K6
K7
K8
D4
E6
E7
F4
F5
G7
232TXDIN
232RTS IN
K EYOUT
SPKRON 4
232CLK_DSP 3
KEYID
232DTR/SYNC_DSP 3
/IRQD 3
KEYIN
232RXDOUT
DAC_ADC_CLK
RXDO 2
MULTCLOCK 1
232CLKOUT
AVR_CLK
2 32DTRIN
232CTS/DIGSQ_DSP 3
232RTS/EORS_DSP 3
232RXD_DSP 3
MRXD 7
232RTS_H8 2
232CTSOUT
3V3LOGIC
R465
10K
1%
R467
100K
1%
R452
47.5
1%
DAC_ADC_CLK
R451
100K
1%
C454
100 pF
5%
R469
NU
DACADCCLK 1,3
1 TDO
1 TMSFPGA
LEDREDN 1
R471
10
1%
LEDGREENN 1
R453
56.2
1%
1,3 TMSDSP
1,3 TCK
LEDRED
PSU_CLK
LEDGREEN
R455
150K
1%
AVR_CLK
C458
0.1 uF
10%
3V3LOGIC
232CTSOUT
R462
10K
1%
R463
10K
1%
11
12
14
15
16
R464
10K
1%
232CLKOUT
C1+
C1C2+
C2-
20
21
232RXDOUT
2 DATOUT_H8
D54
2 32DTRIN
232TXDIN
232RTS IN
D57
CMDSH2-3
D56 CMDSH2-3
2 DATIN_H8
CMDSH2-3
R1O
R2O
R3O
R4O
R5O
EN
V+
V-
13
17
T10
T20
T30
T40
R1I
R2I
R3I
R4I
R5I
SHDN
28
232CLK_SC 1
232RXD_SC 1
PCRXD_SC 1
27
23
18
25
232DTR_SC 1
232RTS_SC 1
PCTXD_SC 1
/232SHDN
CMDSH2-3
C460
0.1 uF
10%
CMDSH2-3
5VLOGIC
232TXD_SC 1
10
D55
26
22
19
24
AVRCLK 7
232CTS_SC 1
T1I
T2I
T3I
T4I
D53
R458
100
1%
U54
MAX213EEAI
VCC
R461
10K
1%
GND
R460
100K
1%
R456
150K
1%
C456
100 pF
5%
R459
22.1K
1%
C457
0.1 uF
10%
C459
0.1 uF
10%
Q60
2N7002
232VCC
C455
+ 15 uF
10%
10V
R457
10
1%
C461
100 pF
5%
Q59
2N7002
6 PSUCLK
R454
56.2
1%
5VLOGIC
R472
1K
1%
R470
10K
1%
5VLOGIC
R473
100K
1%
KVLSEL
3V3LOGIC
R474
100
1%
Q61
2N7002
R475
10K
1%
C462
0.1 uF
10%
R479
100K
1%
ADDC
ADDB
ADDA
INH
16
NCA
NOA
5VLOGIC
5VLOGIC
5VLOGIC
11
10
NCB
NOB
COMA
/WE
12
13
EXTMIC 4
D59
KEYID
D60
CMDSH2-3
/EXTPTT 2,6
D61
CMDSH2-3
KEYLOAD 2
CMDSH2-3
5VLOGIC
3V3LOGIC
D64
BAR43S
R480
4.75K
1%
D63
BAR43S
D62
BAR43S
R478
10K
1%
R477
100K
1%
GND
1,4 EXTSPKR+/KLD
NCC
NOC
COMB
V-
15
1 EXTPTT/KID
R476
10K
1%
3V3LOGIC
D58
CMDSH2-3
1 EXTMIC/WE
V+
U55
MAX4053
14
COMC
3V3LOGIC
3V3LOGIC
R481
10K
1%
D65
CMDSH2-3
1 EXTMICB/KEY
KEYIN
5VLOGIC
Q62
2N7002
K EYOUT
D66
BAR43S
R482
150K
1%
Control FPGA
Thales Communications, Inc.
Rockville, Maryland
Size CAGE Code
Dwg No.
Drawn E. HOOKER
Scale None Thursday, November 15, 2001
23386
R ev
4200716
Sheet 5
02
o f 12
1
LBI 2
3V3ANALOG
7.5VT
R421
100
1%
U44
LP2980A-3.3
P60
1,8 7.5VT
C414
0.1 uF
10%
VIN
VOUT
GND
EN
NC
C416
0.1 uF
10%
C415
+ 4.7 uF
10%
10V
1,2,3,4,5,7,8,9,10,11,12 GND_SIGNAL
3V3LOGIC
R424
2.00
1%
7.5VT
U46
MIC5205
P61
4.5VSW
R422
47.5
1%
8 4.5VSW
P56
C417
0.1 uF
10%
VIN
VOUT
P57
GND
EN
NC
R423
10
1%
D46
CMDSH2-3
U45
LP2980A-3.6
C423
0.1 uF
10%
C418
+ 4.7 uF
10%
10V
C420
0.1 uF
10%
3V3CONT
VIN
VOUT
C422
0.1 uF
10%
GND
EN
BYP
C419
+ 100 uF
20%
6V
C421
+ 4.7 uF
10%
10V
C424
0.01 uF
10%
R426
562K
1%
BATTSW
R427
150K
1%
L70
10 uH
5%
C426
0.1 uF
10%
C425
+ 1.0 uF
20%
35V
RT1
miniSMD050-2
U47A
Si4953DY
C428
0.1 uF
10%
R428
562K
1%
20
18
10
17
16
15
13
11
R430
150K
1%
U49B
Si4953DY
Q55
MMBT3906
LTC1434IGN
365421
C427
+ 4.7 uF
10%
10V
D50
BZX84C8V2
33606
19
R440
10
1%
NC
R433
8.25K
1%
R435
182K
1%
5VLOGIC
U50
LP2980A-5.0
P62
C438
0.1 uF
10%
3V3CONT
VIN
VOUT
EN
NC
R437
5.11K
1%
C433
680 pF
5%
R573
150K
1%
1 RADONSW
3V3LOGIC
C440
0.1 uF
10%
C439
+ 4.7 uF
10%
10V
C436
0.01 uF
10%
C437
47 pF
5%
C435
6800 pF
10%
R439
150K
1%
VIN
VOUT
C442
0.1 uF
10%
GND
R578
150K
1%
C441
+ 15 uF
10%
10V
C443
+ 4.7 uF
10%
10V
TAB-GND
Q71
2N7002
1,7 /RADON
Q70
2N7002
R577
150K
1%
R434
100K
1%
U51
LT1118
R576
150K
1%
C432
100 pF
5%
5VAUDIO
U49A
Si4953DY
C431
+ 4.7 uF
10%
10V
Q68
2N7002
Q69
2N7002
R431
274K
1%
C430
+ 100 uF
20%
6V
BATTSW
7.5VT
Q57
2N7002
C429
0.1 uF
10%
D49
ZHCS1000
1 /RADOFF_SC
L72
1.2 uH
P59
/LBOUT 2,3
R575
150K
1%
12
14
C434
0.1 uF
10%
GND
R436
10K
1%
7.5VT
R574
150K
1%
PWRVIN
BSW
SVIN
SSW
LBI
VOSENSE
PLLIN
NC
PLL LPF
NC
COSC
POR
ITH
NC
VPROG
NC
RUN/SS
LBO
PGND
R432
10K
1%
L71
33 uH
20%
R429
10K
1%
1 EXTPWR_SC
P64
4.5VSW
U48
SGND
P58
U47B
Si4953DY
D48
CMSH2-40
D47
ZHCS1000
2 /PWROFF
Q58
2N7002
R445
475
1%
5 PWRHOLD
R444
150K
1%
5VMICBIAS
U52
LP2980A-5.0
P63
C444
0.1 uF
10%
VIN
VOUT
GND
EN
NC
C446
0.1 uF
10%
C445
+ 4.7 uF
10%
10V
2,5 /EXTPTT
5 PSUCLK
Control Power
Thales Communications, Inc.
Rockville, Maryland
Size CAGE Code
Dwg No.
Drawn E. HOOKER
Scale None Thursday, November 15, 2001
23386
R ev
4200716
Sheet 6
02
o f 12
1
3V3LOGIC
3V3LED
Q50
BSS84TA
BL_LCD_N 1
R409
1K
1%
BL_KP_N 1
BL_KNOB_N 1
R408
47.5K
1%
C410
0.01 uF
10%
R413
100K
1%
R414
100
1%
R415
100K
1%
/BK_DIM
Q54
2N7002
Q53
MMBT3904
C412
0.01 uF
10%
R416
100K
1%
R417
100
1%
Q52
MMBT3904
C411
0.01 uF
10%
R412
1.5K
1%
/BK_ON
R411
1K
1%
R410
1K
1%
Q51
MMBT3904
R418
100
1%
MRXD 5
/MINT 2
KOUT3 1
KOUT2 1
KOUT1 1
1,2,3,4,5,6,8,9,10,11,12 GND_SIGNAL
3V3LOGIC
L69
BEAD
ATMELVCC
ATFVCC
R419
10
1%
C413
0.1 uF
10%
1 TOG2
1 TOG1
1 SECSW
1 EMERGSW
1 AUX3
1 AUX2
1 AUX1
1 PTTSW
3V3LOGIC
R420
47.5K
1%
34
PA3
35
PA2
36
PA1
PA0
VCC
37
38
39
NC
40
PB0
41
PB1
42
PB2
OC1B
PD3
PC7
PD4
PC6
33
32
31
30
29
Added GND to ICP.
28
27
26
25
24
PC4
23
22
PC3
21
12
PC5
PC2
PD5
20
11
PD2
PC1
1 KIN4
ALE
19
1 KIN3
PD1
PC0
10
NC
PD6
1 KIN2
ICP
AT90S8515
NC
18
1 KIN1
PD0
NC
PA7
17
RESET
GND
PA6
16
PB7
XTAL1
PA5
15
PB6
XTAL2
1,2,3 /XRST
PA4
14
1,5 MCLK
PB5
PD7
13
1,5 MTXD
PB3
PB4
44
U43
AT90S8515-4AC
43
5 /KPD_CS
D40
CMDSH2-3
1 KIN5
D41
CMDSH2-3
D42
CMDSH2-3
D44
CMPSH-3A
D43
CMPSH-3A
1,6 /RADON
1 KIN6
5 AVRCLK
D45
CMDSH2-3
1 CHN1
1 CHN2
1 CHN3
1 CHN4
1 VOL1
1 VOL2
1 VOL3
1 VOL4
Control Keypad
Thales Communications, Inc.
Rockville, Maryland
Size CAGE Code
Dwg No.
Drawn E. HOOKER
Scale None Thursday, November 15, 2001
23386
R ev
4200716
Sheet 7
02
o f 12
1
U36-2
Si4925DY
32675
U36-1
Si4925DY
32675
E1
PAD1
BATTERY+
C311
0.1 uF
10%
C312
+ 15 uF
20V
20%
R298
150K
1%
TXCTRL
7.5VT_XCVR 12
R299
150K
1%
Q48
2N7002LT1
SS-32550
R306
7.5VA_XCVR 11
Q47
2N7002LT1
SS-32550
BATTCTRL
R297
150K
1%
E3
PAD1
BATTSENSE
P55
BATTERY-
P54
E2
PAD1
C318
0.1 uF
10%
C319
0.1 uF
10%
R300
150K
1%
GND_SIGNAL 1,2,3,4,5,6,7,9,10,11,12
20VCLK 1,11
1,6 7.5VT
1 7.5VA
1,2,3,4,5,6,7,9,10,11,12 GND_SIGNAL
EEP WP 1,9
1 BATTSENSE
1,12 PATEMP
PROGCLK 2,9,11
1,10 RSSI
1,11 SYNTHLOCK
PROGDATA 2,9,11
1 BATTCTRL
1 TXCTRL
1,11 20VCLK
SYNTHENA 2,11
1,9 EEPWP
SRENA 2,11
2,9,11 PROGCLK
2,9,11 PROGDATA
2,11 SYNTHENA
2,11 SRENA
8DACENA 2,9
2,9 8DACENA
L66
1.2 uH
5%
6 4.5VSW
4.5VSW_XCVR 11,12
C304
.22 uF
10
C305
.22 uF
10
3,9 12DACENA
12DACENA 3,9
1,9 12DACCLK
3,9 12DACDATA
12DACCLK 1,9
12DACDATA 3,9
1,12 PATEMP
1,10 RSSI
TOPRF 12
1,11 SYNTHLOCK
J2
OSMT
60165
SIDERF 12
J3
OSMT
60165
Transceiver Interface
Thales Communications, Inc.
Rockville, Maryland
Size CAGE Code
Dwg No.
Drawn E. HOOKER
Scale None Thursday, November 15, 2001
23386
R ev
4200716
Sheet 8
02
o f 12
1
7.5VA_XCVR
8,11 7.5VA_XCVR
+3.3VRX
10,11 +3.3VRX
+5VDIG
TXVCOMOD 11
11 +5VDIG
R169
274K
1%
R186
47.5K
1%
1,2,3,4,5,6,7,8,10,11,12 GND_SIGNAL
+5VDIG
20V
12 BIT DAC
R255
100K
1%
+2.5VREF
VDD
OUTA
OUTB
FBA
OP
R252
100K
1%
+IP
FBB
REFOSCMOD 11
U75
V-
R254
100K
1%
TP24
-IP
LM7301
365661
20
C267
0.1 uF
10%
MAX525B
365588
AD1582C
365795
SOT23/3P
C544
.033 uF
TP
U31
U32
+5VDIG
R172
90.9K
1%
V+
C257
0.1 uF
10%
R253
100K
1%
2.5 VDC
C268
+ 2.2 uF
10V
10%
SS-25131
C270
0.1 uF
10%
REFAB
OUTC
C269
0.1 uF
10%
FBC
15
R258
100K
1%
R259
100K
1%
R257
100K
1%
REFCD
TP17
TP
C271
0.1 uF
10%
OUTD
14
13
3 12DACDATA
R256
100K
1%
16
+5VDIG
17
CL*
FBD
IFAGC 10
R262
100K
1%
19
PDL*
R263
100K
1%
UPO
DIN
CS*
DOUT
3 12DACENA
DGND
10
18
SCLK
AGND
12
11
1 12DACCLK
R175
130K
1%
20V
11
14
R287
1M
1%
C279
1000 pF
5%
13
PROGCLK
R290
100
1%
12
2,11 PROGCLK
VCC
4OE*
1A
1Y
2Y
3Y
2A
4Y
3A
1OE*
4A
GND
2OE*
3OE*
10
R264
100K
1%
11
+5VDIG
R266
100K
1%
10
TP
TP19
2ND_LO_TUNE 10
REF
OUTB
74HCT125
365078-125
2 8DACENA
OUTA
R196
10K
1%
DIN
LDAC
TP20
OUTC
16
CS*
SCLK
OUTD
TP
U35
CTUNE 11
C206
1.0 uF
20%
35V
R193
10K
1%
RXVTF 10
15
CLR*
PDE
DOUT
TP21
UPO
R273
100
1%
VDD
TP18
R272
100K
1%
R180
100K
1%
MAX534B
365590
13
LM7301
365661
TP
U76
+2.5VREF
U33
C276
0.1 uF
10%
C303
0.1 uF
10%
R182
100K
1%
R181
NU
C275
0.1 uF
10%
+5VDIG
+IP
V-
+5VDIG
OP
TP
R179
23.7K
1%
D25
SS-35620
BAR43S
-IP
V+
8 BIT DAC
C545
.033 uF
R177
43.2K
1%
12
14
DGND
PWRSET 12
AGND
PROGDATA
R291
100
1%
2,11 PROGDATA
EEPROM
3V3LOGIC
U15
PROGCLK
24C64
365440
1 EEP WP
VCC
C117
0.1 uF
10%
WP
SDA
GND
PROGDATA
A0
A1
A2
SCL
R86
100K
1%
Transceiver DACs
Thales Communications, Inc.
Rockville, Maryland
Size CAGE Code
Dwg No.
Drawn E. HOOKER
Scale None Thursday, November 15, 2001
23386
R ev
4200716
Sheet 9
02
o f 12
1
RF AMPLIFIER
+3.3VRX
1st IF AMPLIFIER
C1
0.1 uF
10%
+3.3VRX
R1
10
1%
L7
0.39 uH
2%
C4
1000 pF
5%
L8
7T-AW
3400439-5
R1
D27
SMV1204-136
D4
SMV1204-136
R187
100K
1%
R9
100K
1%
L15
5T-AW
3400439-3
L11
1.2 uH
5%
P1
D28
SMV1204-136
R12
51.1
1%
C5
1000 pF
5%
R3
C9
2.7 pF
0.1pF
R4
11T
R3
2.67K
1%
L3
56 nH
2%
L2
47 nH
2%
L4
100 nH
2%
L9
56 nH
2%
C11
5.6 pF
0.1pF
C12
120 pF
5%
R5
C16
22 pF
2%
C15
22 pF
2%
C14
18 pF
2%
L22
150 nH
2%
Q1
MMBR941
32098 P2
C10
9.1 pF
0.1pF
L5
100 nH
2%
C13
120 pF
5%
R6
C17
22 pF
2%
C6
39 pF
5%
RF
IF
C7
0.01 uF
10%
R8
R9
L10
330 nH
5%
R7
GND
L16
1.8 uH
2%
GND
R5
51.1
1%
R4
51.1
1%
GND
R8
332
1%
C21
NU
C22
0.1 uF
10%
C302
0.1 uF
10%
C25
6.2 pF
0.25pF
R7
3.01K
1%
C28
27 pF
5%
9 RXVTF
C30
18 pF
2%
C214
0.1 uF
10%
C56
10 pF
0.25pF
C31
10 pF
0.25pF
C23
150 pF
5%
L17
82 nH
2%
L19
15 nH
2%
T2
45MHz
1600463-1
1T
C3
0.1 uF
10%
P6
U1
EMRS-1A
84586
D3
SMV1204-136
29050
C8
1.0 pF
0.1pF
L14
5T-AW
3400439-3
R2
NC
D2
MMBD701
SS-36034
NC
D1
MMBD701
SS-36034
12 RX_INPUT
T1
136-174MHz
1600462-1
4T
1T
L1
56 nH
2%
L6
7T-AW
3400439-5
TP1
TP
C61
120 pF
5%
136-174 MHZ
R2
10
1%
MIXER
LO
2 POLE BANDPASS FILTER
LOWPASS FILTER & IF NOTCH
C2
0.1 uF
10%
P3
L25
100 nH
2%
C26
0.01 uF
10%
4T
R10
R11
11T
R6
2.67K
1%
Q2
MMBR901
32099
L18
6.8 uH
5%
P5
R10
3.01K
1%
C27
0.1 uF
10%
P4
L20
33 nH
2%
L21
39 nH
2%
C29
NU
C75
5.6 pF
0.25pF
R11
332
1%
C87
1.8 pF
0.25pF
11 RXLO
181-219MHz
1,2,3,4,5,6,7,8,9,11,12 GND_SIGNAL
9 IFAGC
+3.3VRX
TP
L63
150 nH
10%
+3.3VRX
C224
0.1 uF
10%
R283
150
1%
R208
NU
R212
18.2K
1%
D26
SMV1236-011
29037
TP2
C223
18 pF
2%
Q35
MMBR901
32099
C284
91 pF
5%
C289
91 pF
5%
C226
56 pF
5%
R284
68.1
1%
R276
51.1
1%
R250
1.5K
1%
+3.3VRX
12
RSSI
LOIP
IFOP
R251
51.1
1%
RFLO
IF AMPLIFIER
17
14
R224
1K
1%
FL2
455 kHz
37107
C337
0.1 uF
10%
C231
0.1 uF
10%
C228
0.01 uF
10%
R217
12.1K
1%
C240
0.1 uF
10%
V+
U29
OPA343
365701
R571
49.9
1%
R222
49.9
1%
IFOUT 3
10
IFLO
DMIP
R227
1.21K
1%
15
R281
20K
1%
R225
681
1%
C547
NU
C236
NU
R229
2.21K
1%
P12
C290
0.1 uF
10%
C247
3.3 pF
0.25pF
C246
0.1 uF
10%
FL3
455 kHz
37121
C338
0.1 uF
10%
C34
0.1 uF
10%
U4
LP2980A-3.3
365460
R238
1.5K
1%
R237
174
1%
TP3
+3.3VRX
2nd
R236
1.3K
1%
R219
12.1K
1%
18
11
IFHI
MXOP
VMID
COM2
GREF
C244
0.1 uF
10%
C249
0.1 uF
10%
C248
0.1 uF
10%
PLACE NEAR U28-9
(VMID)
U27
LMC7101A
V365438
VP10
R230
332
1%
L62
0.82 uH
2%
RFHI
C245
0.1 uF
10%
L60
1.5 uH
2%
C235
NU
R220
3.01K
1%
L61
390 nH
10%
C294
NU
L64
1.0 uH
2%
C285
2.2 pF
.25pF
C19
2-10 pF
SS-28058
C18
8.2 pF
0.1pF
P8
C286
3.3 pF
0.25pF
13
R241
475
1%
Q36
MMBR901
32099
QOUT
R13
AD607ARS
365513
IOUT
C288
15 pF
2%
FL4
45 MHz 2-POLE
1600479-1
R12
R240
475
1%
L13
470 nH
10%
C237
8.2 pF
.1pF
C242
39 pF
5%
FL1
45 MHz 4-POLE
1600471-1
C287
120 pF
5%
COM1
R218
2.67K
1%
C57
1.8 pF
0.25pF
L12
680 nH
10%
R279
100
1%
U28
FDIN
20
16
19
C230
0.1 uF
10%
C536
0.1 uF
10%
C229
+ 4.7 uF
10%
10V
C233
0.1 uF
10%
VPS1
VPS2
PRUP
FLTR
R215
10
1%
RSSI 1
+3.3VRX
C256
0.1 uF
10%
R280
20K
1%
R214
1K
1%
V+
R213
1.3K
1%
2 dB PAD
R316
10
1%
+3.3VRX
C227
56 pF
5%
P9
C241
0.01 uF
10%
C225
0.1 uF
10%
PLACE C230 NEAR PIN 16, C536 NEAR PIN 20
R282
68.1
1%
C215
0.1 uF
10%
R204
NU
L65
680 nH
10%
R206
10K
1%
C59
100 pF
5%
L24
1.2 uH
10%
IF IC
P7
Y1
44.545 MHz
1600407-1
9 2ND_LO_TUNE
C293
12 pF
2%
C222
0.1 uF
10%
TP
2nd LO
R33
1.82K
1%
R31
200K
1%
R203
100
1%
VIN
VOUT
ON/OFF
NC
GND
+3.3VRX 11
C292
4.7 uF
10V
10%
P11
PLACE NEAR FL3-3
C550
0.1 uF
10%
12 RXSINK
Transceiver Receiver
11 +3.3VRXEN
Thales Communications, Inc.
Rockville, Maryland
Size CAGE Code
Dwg No.
Drawn E. HOOKER
Scale None Thursday, November 15, 2001
23386
R ev
4200716
02
Sheet 10 o f 12
1
MIC5205
1%
365499
+5VDIG
+3.5V
VIN
VOUT
ON/OFF
NC
GND
C120
4.7 uF
10%
10V
SS-25122-475-10
VIN
C121
1.0 uF
20%
35V
ON/OFF
C123
+ 4.7 uF
10%
10V
SS-25122-475-10
R89
110K
1%
GND
P13
BYP
+3.3VRX
P14
VOUT
C295
0.01 uF
10%
TP8
R87
10
1%
+3.3VA
TP
TP
4.5VSW_XCVR
TP7
LP2980A-5.0
365413
C118
1.0 uF
20%
35V
25122-105-35-A
U17
U16
7.5VA_XCVR
C124
+ 4.7 uF
10%
10V
R91
200K
1%
10 +3.3VRX
+5VDIG
4.5VSW_XCVR
C125
2.2 uF
10%
10V
20V
TX VCO
R140
22.1K
1%
RFIN
R143
51.1
1%
PHI
13
C177
0.068 uF
5%
+3.3VDIG
PHA
RFIN*
11
C172
6800 pF
10%
22562-682
D19
SMV1493-011
29054
C173
2200 pF
10%
D20
SMV1207-001
D21
SMV1207-001
29036
C183
1000 pF
5%
L53
3400439-1
P16
P27
R128
47.5
1%
C164
1000 pF
5%
P25
C169
27 pF
5%
C174
4.7 pF
.25pF
R145
4.75K
1%
R137
4.32K
1%
R146
10
1%
C180
18 pF
2%
R150
5.62K
1%
L55
1.5 uH
10%
R133
2.21K
1%
R131
16.2
1%
C170
15 pF
5%
R15
R141
16.2
1%
R142
16.2
1%
R16
R18
C167
15 pF
5%
R17
Q25
MMBR901
R147
3.01K
1%
P24
C181
1000 pF
5%
L49
68 nH
5%
R132
182
1%
C171
1000 pF
5%
Q26
MMBR901
R149
332
1%
L50
68 nH
5%
R136
182
1%
C53
10 pF
2%
C163
1000 pF
5%
Q24
MMBR901
C159
1000 pF
5%
R135
R152
511
1%
C175
15 pF
2%
P26
C179
1000 pF
5%
L52
27 nH
5%
R138
16.2
1%
RX BUFFER
AMPLIFIER
TP11
R139
16.2
1%
R19
R144
16.2
1%
C176
15 pF
2%
R111
10
1%
R148
267
1%
REFIN
10
12
R117
1.1K
1%
C150
1000 pF
5%
R120
1.3K
1%
RXLO 10
P30
C154
1000 pF
5%
R20
C149
12 pF
2%
Q23
MMBR901
C187
1000 pF
5%
L48
56 nH
5%
R115
475
1%
C145
1000 pF
5%
P31
VCCP
VSS
AUXIN
VSSA
C141
0.1 uF
10%
+3.3VRX
C184
1000 pF
5%
R157
100
1%
C158
0.1 uF
10%
P23
C166
9.1 pF
.1pF
C165
10 pF
2%
P28
C157
0.1 uF
10%
+3.3VA
TP
L51
1.5 uH
10%
TXLO 12
C188
1000 pF
5%
P15
TP10
R134
47.5K
1%
NC
RA
R153
22.1
1%
C152
2.2 uF
10V
10%
C185
15 pF
5%
14
C162
+ 4.7 uF
10V
10%
R124
47.5
1%
R130
2.21K
1%
R156
1.1K
1%
BUFFER
AMPLIFIER
L56
68 nH
5%
Q27
MMBR901
PHP
R112
511
1%
R125
47.5
1%
+3.3VA
R155
825
1%
C186
1000 pF
5%
C168
1000 pF
5%
C161
0.022 uF
10%
R154
475
1%
C160
1000 pF
5%
P17
15
R14
C144
1000 pF
5%
VDDA
R127
22.1
1%
R129
1M
1%
STROBE
RX VCO
2 SYNTHENA
R110
5.62K
1%
C182
1000 pF
5%
P29
P21
C155
0.1 uF
10%
R126
100
1%
C156
0.1 uF
10%
16
C138
22 pF
2%
+3.3VRXS
RN
C151
0.1 uF
10%
L43
82 nH
5%
Q22
MMBR901
R121
NU
R107
10
1%
R151
22.1
1%
P22
R123
35.7K
1%
DATA
C139
4.7 pF
.25pF
R109
332
1%
17
+3.3VRXS
2,9 PROGDATA
RF
R118
681
1%
R119
100
1%
18
C134
1000 pF
5%
R103
182
1%
R104
4.32K
1%
L47
1.5 uH
10% C148
1000 pF
5%
LOCK
R116
10K
1%
VDD
TEST
CLK
R114
1M
1%
C143
+ 4.7 uF
10V
10%
C146
0.022 uF
10%
P18
TP
2,9 PROGCLK
20
19
C142
22 pF
2%
SA7025DK
365423
D18
BBY40
SS-29029
C137
22 pF
2%
R105
4.75K
1%
L46
100 nH
2%
L45
100 nH
2%
R106
22.1
1%
C140
1000 pF
5%
Q21
MMBR901
32099
D16
BBY40
D17
SMV1213-001
29044
U19
+3.3VDIG
SYNTHESIZER
R113
100
1%
KEEP VERY SHORT
SYNTHLOCK 1
C136
6.8 pF
.1pF
C135
8.2 pF
.1pF
R102
1K
1%
R100
47.5
1%
1,2,3,4,5,6,7,8,9,10,12 GND_SIGNAL
L44
1.5 uH
10%
R101
2.21K
1%
C130
1.0 pF
.1pF
C178
0.1 uF
10%
+3.3VTXS
R99
47.5
1% C133
1000 pF
5%
P20
D15
BBY31
SS-29031
R185
47.5K
1%
LM7301
365661
U77
+IP
C132
220 pF
5%
R98
23.7K
1%
C131
3300 pF
5%
TX BUFFER
AMPLIFIER
+3.3VTXS
C129
0.1 uF
10%
9 TXVCOMOD
OP
C128
0.1 uF
10%
R94
182K
1%
-IP
R96
4.32K
1%
TP9
R95
15K
1%
V-
8 7.5VA_XCVR
C126
0.015 uF
10%
R97
3.92K
1%
R92
7.5K
1%
TP
C546
.033 uF
V+
7.5VA_XCVR
+3.3VTXS
12 +3.3VDIG
+3.3VDIG
+5VDIG 9
+3.3VTXS
8,12 4.5VSW_XCVR
R122
121
1%
+5VDIG
R320
22.1
9 CTUNE
9 REFOSCMOD
C339
0.1 uF
P33
REF OSC
VOLTAGE
MULTIPLIER
U42
4 12.8 MHz
37132
Vc
TP
C539
NU
C341
100 pF
D23
BAR43S
SS-35620
GND
QC
11
QD
SRCLK
QE
QF
QG
6.00VDC
R171
100K
1%
R173
100K
1%
C193
+ 1.0 uF
20%
35V
Q31
Si2301DS
32631
QH
RCLK
QH'
SRCLR
Q32
Si2301DS
10
R288
1M
1%
GND
R183
1M
1%
Q33
BSS123
SS-32564
Q34
BSS123
13
C301
1000 pF
5%
12
2 SRENA
TP12
TP
+3.3VRXS
R178
1M
1%
VIN
VOUT
P35
ON/OFF
GND
BYP
R295
86.6K
1%
P34
C310
470 pF
10%
R294
100
1%
7.5VA_XCVR
C190
+ 2.2 uF
20%
16V
R160
10
1%
C191
0.01 uF
10%
U21
MIC4416BM4
365621
P36
C192
0.1 uF
10%
VS
CTL
GND
D35
BAR43S
C202
.033 uF
10%
C199
.033 uF
10%
C203
.033 uF
10%
C308
.033 uF
10%
R162
1K
1%
C309
.033 uF
10%
C201
+ 1.0 uF
20%
35V
C196
1.0 uF
20%
35V
Q46
MMBT3904
SS-32089-3904
C307
.033 uF
10%
Note: Use single
point ground here
R296
332K
1%
R159
121
1%
TP13
TP
R293
100
1%
MIC5205
365499
+3.3VTXS
C195
1000 pF
5%
QB
U20
+3.3VA
16
SER
VCC
14
74HC595
365459-595
15
QA
D24
BAR43S
U24
R292
100
1%
R566
NU
C200
0.1 uF
10%
P32
+3.3VDIG
TP14
20V
OUT
C340
0.01 uF
Vcc
R322
10K
1%
1 20VCLK
+3.3VRXEN 10
TX/RX 12
STD/SIDE 12
Transceiver Synthesizer
Thales Communications, Inc.
Rockville, Maryland
Size CAGE Code
Dwg No.
Drawn E. HOOKER
Scale None Thursday, November 15, 2001
23386
R ev
4200716
02
Sheet 11 o f 12
1
SENSOR LOCATED CLOSE
TO POWER MODULE
7.5VT_XCVR
8 7.5VT_XCVR
+5VTX
4.5VSW_XCVR
C216
0.1 uF
10%
U11
8,11 4.5VSW_XCVR
LM50B
365437
R191
100
1%
+V
+3.3VDIG
GND
11 +3.3VDIG
OUT
PATEMP 1
C540
1000 pF
5%
1,2,3,4,5,6,7,8,9,10,11 GND_SIGNAL
PRE-DRIVER
POWER MODULE
7.5VT_XCVR
TXSINK
B1
50@100
45270
P39
C331
0.018 uF
10%
RF IN
C81
2.7 pF
.25pF
R24
MMBR941
32098
P38
R44
475
1%
R52
475
1%
R57
150
1%
C88
0.01 uF
10%
C209
6.8 pF
.25pF
C112
1000 pF
5%
20 dB Coupler
1600458-1
C83
10 pF
2%
R25
C127
1.5 pF
.1pF
C84
6.8 pF
.25pF
C82
22 pF
2%
R26
D13
C113
1000 pF
5%
L42
6T-AW
3400439-11
MA4P7001F
36047
RX_INPUT 10
C114
10 pF
2%
C115
10 pF
2%
D14
MA4P7001F
36047
RF OUT
U12
R21
R319
L31
5T#24-AW
3400439-10
R55
1.3K
1%
R49
10
1%
L30
6T#24-AW
3400439-9
L41
1.2 uH
2%
P44
VGG
C92
0.01 uF
10%
L68
0.22 uH
10%
P40
P41
C334
0.1 uF
10%
C335
0.018 uF
10%
C95
3300 pF
5%
R558
562
1%
R69
1K
1%
HSMS-2800
SS-35616
NC 2
P51
R70
1K
1%
R71
20K
1%
P52
HSMS-2800
SS-35616
C101
1000 pF
5%
C102
1000 pF
5%
R74
100K
1%
VCONTROL
U13
LMC7101A
365438
NC
D12
DETECTOR / POWER
CONTROL
C336
0.01 uF
10%
P50
C100
1000 pF
5%
R85
47.5
1%
1/10W
R84
43.2
1%
R64
7.5VT_XCVR
D11
R68
100K
1%
R83
43.2
1%
R65
NU
C96
1000 pF
5%
+5VTX
R67
51.1
1%
R66
51.1
1%
VCONTROL
R557
562
1%
R315
562
1%
C116
1000 pF
5%
VDD
C78
1000 pF
5%
R22
R23
L37
100 nH
2%
R27
M68776-E01
84604
Q7
11 TXLO
R51
51.1
1%
P43
L35
180 nH
5%
2 dB attenuator
C77
10 pF
2%
(FROM SYNTH)
C86
15 pF
5%
R78
47.5
1%
R77
43.2
1%
U37
R47
562
1%
L28
120 nH
10%
R48
2K
1%
C111
1000 pF
5%
C328
3.3 uF
10%
16V
C332
0.018 uF
10%
R76
43.2
1%
C74
0.01 uF
10%
TX/RX PIN
SWITCH
P42
7.5VT_XCVR
R75
2.21K
1%
9 PWRSET
C110
0.01 uF
10%
P53
TOPRF 8
C94
1000 pF
5%
ANTENNA PIN
SWITCH
R28
D8
C103
390 pF
5%
L40
1.2 uH
2%
P47
C106
1000 pF
5%
L39
1.2 uH
2%
MA4P7001F
R73
1.82K
1%
P46
P45
C105
1000 pF
5%
SIDERF 8
D10
MA4P7001F
R72
1.82K
1%
R29
7.5VT_XCVR
P49
P48
C107
1000 pF
5%
C104
390 pF
5%
U14
C109
0.1 uF
10%
TP5
LP2980A-5.0
365413
TP
C98
1000 pF
5%
D9
L38
1.2 uH
2%
L80
NU
5%
R30
MA4P7001F
36047
+5VTX
D7
MA4P7001F
C97
1000 pF
5%
VIN
VOUT
ON/OFF
GND
C108
4.7 uF
10%
10V
SS-25122-475-10
TP6
TP
LP2980A-3.3
365460
VIN
VOUT
ON/OFF
Q19
BSS123
GND
C43
4.7 uF
10%
10V
SS-25122-475-10
+3.3VDIG
C38
0.1 uF
10%
TXSINK
U3
Q15
BSS123
SS-32564
Q18
BSS123
C306
0.1 uF
4.5VSW_XCVR
11 STD/SIDE
Q10
Si2301DS
32631
R80
100K
1%
Q11
Si2301DS
32631
Q14
BSS123
Q17
BSS123
Q16
BSS123
Q12
Si2301DS
32631
Q13
Si2301DS
32631
R82
100K
R81
100K
R79
100K
1%
4.5VSW_XCVR
RXSINK 10
11 TX/RX
Transceiver Transmitter
Thales Communications, Inc.
Rockville, Maryland
Size CAGE Code
Dwg No.
Drawn E. HOOKER
Scale None Thursday, November 15, 2001
23386
R ev
4200716
02
Sheet 12 o f 12

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.4
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Create Date                     : 2002:05:13 23:07:22Z
Modify Date                     : 2002:05:14 11:11:43-07:00
Page Count                      : 85
Creation Date                   : 2002:05:13 23:07:22Z
Mod Date                        : 2002:05:14 11:11:43-07:00
Producer                        : Acrobat Distiller 5.0.5 (Windows)
Author                          : cdunlap
Metadata Date                   : 2002:05:14 11:11:43-07:00
Creator                         : cdunlap
Title                           : Microsoft Word - G25AMK005a.doc
Has XFA                         : No

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Datron World Communications G25RMV110 VHF Mobile Radio User Manual G25AMK005a

Datron World Communications Inc VHF Mobile Radio G25AMK005a

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Technical Manual

FCC ID Filing: B3TG25RMV110

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