Digi 50M1558 Wi-EM a/b/g User Manual Part 2 Revised 072709 Rev 2

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Document ID	1223554
Application ID	SQPZ15MfNwWaWR99li6qRA==
Document Description	Users Manual Part 2 Revised 072709 Rev 2
Short Term Confidential	No
Permanent Confidential	No
Supercede	No
Document Type	User Manual
Display Format	Adobe Acrobat PDF - pdf
Filesize	206.31kB (2578913 bits)
Date Submitted	2010-01-07 00:00:00
Date Available	2010-01-07 00:00:00
Creation Date	2009-04-01 15:03:12
Producing Software	KONICA MINOLTA bizhub C253
Document Lastmod	2009-07-24 15:29:32
Document Title	Users Manual Part 2 Revised 072709 Rev 2
Document Creator	KMBT_C253

About the Development
Board
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CHAPTERZ
Overview
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This chapter provides information on the development board, a hardware platform from
which you can determine how to integrate the embedded module into your design For
additional information. see the schematic and mechanical drawings.
Basic Description
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The following gTaphic is a layout of the development board,
....... 17
Basic Description
Basic Description
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7 GPIO ports
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" "“ connector
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LEDs c ‘_ . . m 1——
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‘5'5 SM Jumper
Main m block
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Fuwer jack
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Ports
About the Development Board
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The developmeni board provides the following ports:
Serial Port 1 (P1) and Serial Port 2 (P2)
Ethemei Port (P12)
GPlO Port (P3)
Serial Port 1 (P1) and Serial Port 2 (P2)
Serial port 1 and port 2 are DB-9 male connectors labeled Pi and P2. Use the following
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figure and table for pin orientation and pin assignment information
Serial Port Pin Orientation
Pinfi Pin9
Serial Pin Assignment
Port Signal Signal Signal Signal Signal Signal Signal Signal Signal
Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9
1 DUB RXI) TXD DTR GND DSR RTS CTS NM
Connceled
Nni Nni No! No! Not Not
2 Command RXD TXD Connected GND Connected Cunnccled Connecled Connecied
19
Connectors and Blocks
GPIO Port (P3)
The GPIO pen is a lO-pin male right-angle connector (labeled P3). See the following
figure and table for pin orientation and pin assignments.
GPIO Port Pin Orientation
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Pin1 Pin10 5
GPIO Port Pin Assignments
Pin Signal Name
I GND
2 GPIO-9
3 GPIO-8
4 GP10-7
5 GPIO—6
6 GPIO-5
7 GPIO-4
8 GPIO-3
9 GPIO-2
10 GPIO-I
Connectors and Blocks
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The development board provides the following connectors and blocks:
- JTAG Debugger Connector (P4)
l SP1 Connector (P11) and SP1 Jumper Block
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enigma
About the Development Board
JTAG Debugger Connector Pin Assignments
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
1 2 3 4 5 6 7 8 9 10 ll 12 13 14
Signal VCCQ GND [TRST GND TDI GND TMS GND TCK GND TDO /5RST VC(H GND
SP1 Connector (P11)
This connector is used for a Serial Peripheral Interface (SP1) connection. When enabled,
signals are disconnected from serial port 1 and GPIO connectors See the following figure
and table for pin orientation and pin assignments.
2]
Connectors and Blocks
SPI Connector Pin Orientation
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Pin2 a w Pin1
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SP1 Pin Assignments
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
1 2 3 4 5 6 7 8 9 10
Signal SPI-EN GND SPl-CLK GND SPI—TX GND SPI-RX GND cum!“ with“,
SP1 Jumper Block
The SP1 jumper block determines whether the SP] connector is connected or not. lfSPI is
off (the default), serial and GPIO signals are muted to switch banks 1 through 4, (See
"Serial/GPIO Switch Bank 3 (SW3) and Switch Bank 4 (SW4)“ on page 26 and "GPIO
Switch Bank 1 (SWl) and 2 (SW2)" on page 27.) If SP1 is on, SP1 signals are routed to the
SP1 connector (P11).
The following figures demonstrate how to set the SP1 jumper block
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About the Development Board
SPI Jumper Settings
SPI OFF SPI ON
Panama
Pia-n P1! ants
Putnam
Pisaaa
Logic Signal Analyzer Header (P6)
This 20-pin male vertical header (labeled P6) connects a digital signal analyzer (for
example, a logic analyzer) to the development board, It is used with the development kit
only. See the following figure and table for pin orientation and pin assignments.
Logic Analyzer Header Pin Orientation
Pinl—>l 1—Pin2
--
n-
.-
Pin19—>-
<—Pin 20
Logic Analyzer Header Pin
Assignments
Pin Signal
1 - 8 Not connected
”mm 23
Connectors and Blocks
Logic Analyzer Header Pin
Assignments
Pin Signal
9 /RST
10 Nm conncmcd
ll DTR/GPIO-S
12 TX l)-2/G F [0-8
13 CTS/GPIO-Z
14 RXDvZ/GPIO~9
15 DSR/GPIO»3
lb TXD-l/GI’IO-G
l7 RTS/GPlO-A/SPLCLK
18 RXD-l/GPIO-7
19 DCD/GPlO-l/SPI_EN
20 GND
Main Connector (P8)
This 12-pin connector is used to interface with the embedded modular See the following
figure for pin orientation.
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About the Development Board
Main Connector Pin Orientation
up view
Power Jack (P17)
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The Power Jack is a barrel connector that accepts 9 to 30 VDC +/~ 5%, The jack is labeled
P17. The following table shows the polarity of the power jack.
Power Jack Polarity
Contact Polarity
Center +9 to +30 VDC
Outer Ground
The following figure schematically represents the polarity of the power jack
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Switches
Power Jack Polarity Schematic.
Ground +9ro+30 VDC
Switches
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The development board provides the following switches:
- Reset Switch (sw5)
I Serial/GPIO Switch Bank 3 (SW3) and Switch Bank 4 (SW4)
l GPIO Switch Bank 1 (SW!) and 2 (SWZ)
Reset Switch (SWS)
This push button switch is labeled SWS. Pressing it sets the module's /RST line low.
holding the module in a hard reset until the switch is released.
Note: This is a ”hard" reset using the /RST pin on the main connector, not a "so "
reset. The reset button on the embedded module performs a "sofi" reset (see
also "Main Connector (P8)" on page 24).
Serial/GPIO Switch Bank 3 (sws) and Switch Bank 4 (SW4)
Each switch bank holds five slide switches that enable either serial or GPlO signaling
between the development board and the module. When set for GPIO signaling, SW3 works
in conjunction with SW], and SW4 works with SWZ. See "GPIO Switch Bank 1 (SWI)
and 2 (SW2)" on page 27 for more information. See the following table for SW3 and SW4
switch definitions.
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About the Development Board
Note: These switches control where the development board routes 3 signal. They do not
reconfigure the Wi-EM 9210 processor. Sofiware should be configured to track
with switch settings. See "GPIO" on page 33 for more information.
GPIO Switch Banks 3 and 4 Settings
Switch Switch Left Right
Bank Number Position Position
1 DCD GPIOVI
2 CTS GPIO-Z
SW3 3 DSR GHQ-3
4 RTS GPIO-4
5 DTR GPIO-S
6 TXD-l GPIO-6
7 RXD-l GPIOJ
SW4 8 TXD-Z GPIO-8
9 RXD-2 GPIOv9
10 Not connected Nut connected
GPIO Switch Bank 1 (SW1)and 2 (SW2)
GPIO Switch Bank 1 and Switch Bank 2, labeled SW] and SWZ, are two sets of five slide
switches that set GPIO inputs to logic levels of high (switch to left) or low (switch to
right).
If the GPIO port is configured as an output, then the switch should always be to the left. If
there is an external device connected to P1 the switch should always be set to the lefi.
Each GPIO port can be used independently.
Notes:
I These switches do n_ot determine whether the GPIO is an input or output, That
is determined by the module sofiware,
- If GPIO is set to an output by sofiware, switches must be set to the lefl (high).
I These switches are used in conjunction with SW3 and SW4.
Hunt. 27
Devclnpmenl Board LEDs
Development Board LEDs
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The development board contains 21 LEDs labeled CR] through CR2 1. The following table
lists and describes the LEDs.
LED Descriptions
Beard Description Color or State Indication
La beI
Flickering Serial ncliviry
CRl TXD-2
Green lnaclive
Flickering Serial activity
CRZ RXD~2
Green Inactive
Yellow Active
CR} 018 Green lnamlve
Off Noi connecled or signal
not being driven
Yellow Active
CR 4 DTR Green lmlcnvc
on Not cl‘innecied or signal
nor being driven
Flickering Serial activity
CRS TXD~I
Green Inactive
Flickering Serial acilvily
CRG RXD-l
Green Inactive
Yellow Active
CR7 RTS Green Inactive
Off Nut connected or Signal
not being driven
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About Ihe Development Board
LED Descriptions
Board Description Color or State Indication
Label
Yellow Active
CRR DCD (ween lnacllve
Not connemed or signal
Off . .
not being driven
Yellow Active
CR9 DSR Green Inactlve
Not connected or signal
0“ not being driven
Gl’IO»l through GPIO-9. On Logic high
CRIO—IS (CRIOZGPIO-1.CR1IZGPIOQJB‘C
All can be used for input or output.) Off LOgiC 10W
On Power on
CRZO 33V Indiuatur
Off Power off
Ethernet power presem
On from external powered
Ethemel connector
CRZI EPWR. Powered Elhemel Enabled (Ethernet hub or switch)
Off No powered Ethernet
voltage
Test Points
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The development board provides 25 test points that can be identified by board label or test
point number. The board labels are adjacent to each test point on the board. The test point
numbers are in the development board schematic drawings. The following table lists the
test point number, board label, and a brief description of each test point.
”mull 29
Test Points
30
Test Paint Descriptions
Te.st Board Description
Point Label
TPZ TXD I'XD-Z
TP3 RXD RXD-Z
TP4 CTS CTS
TPS DTR DTR
TP6 TXD TXD-l
TP7 RXD RXD-l
TP8 RTS RTS
TP9 DCD DCD
TP 1 0 DSR DSR
TPH 10-1 GPIO-I
TP12 IO~2 GPIO-Z
TP13 10-3 GHQ-3
T'i’l4 10-4 GHQ-4
TP 15 10-5 GPIO-S
TPI7 3.3V 3.3v Supply
mo RESET Reset (active low)
TP2] ii+ Ethemel Power +
TP22 E- Ethemel Puwer -
TP23 V-IN 9-30 VDC lnpui
TP24 GND Ground
TP25 GND Ground
TP26 [0—8 GNU-8
TP27 [0-7 (iPIO-7
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About the Development Board
Test Point Descriptions
Test
Board
Point Label Description
TPZS 10-6 GPIO—fi
TPZ9 10-9 GPIO—9
Test Points
32 "an" Digi L'nnncc! Wi-hM 9210 Hardware Rcl'crcncc

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Creator Tool                    : KMBT_C253
Modify Date                     : 2009:07:24 15:29:32-05:00
Metadata Date                   : 2009:07:24 15:29:32-05:00
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