Digi 50M1558 Wi-EM a/b/g User Manual Part 3 Revised 072709 Rev 2

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Document ID	1223555
Application ID	SQPZ15MfNwWaWR99li6qRA==
Document Description	Users Manual Part 3 Revised 072709 Rev 2
Short Term Confidential	No
Permanent Confidential	No
Supercede	No
Document Type	User Manual
Display Format	Adobe Acrobat PDF - pdf
Filesize	153.35kB (1916904 bits)
Date Submitted	2010-01-07 00:00:00
Date Available	2010-01-07 00:00:00
Creation Date	2009-04-01 15:03:12
Producing Software	KONICA MINOLTA bizhub C253
Document Lastmod	2009-07-24 15:36:04
Document Title	Users Manual Part 3 Revised 072709 Rev 2
Document Creator	KMBT_C253

Programming
Considerations
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CHAPTER3
This chapter addresses the embedded modules programming considerations.
Note: This chapter applies only to development kit customers.
GPIO
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General Information
The WifEM 92l0 processor supports 16 general purpose I/O (GPIO) lines, some of which
are reserved for specific functions and some of which can be customized. These GPIO lines
fall into three categories:
I Those labeled “Reserved" in the following table are reserved for a specific use
and must n_ot be reprogrammed, or the unit may not operate correctly. Often,
these lines are not connected to extemal interfaces
1 Those labeled “Allocated” in the following table are exposed to an external
interface and allocated to a specific use by the software, but they can be
customized safely with code modifications.
I Those labeled “Available" are exposed to an external interface, not controlled
directly by the sofiware, and can be customized,
nu...- 33
GPXO
GPIO Registers
Six registers govern the 16 GPIO pins. There are four configuration registers Each has
eight bits dedicated to the configuration of each GPIO.
Register D31124 D23:Dl D15:08 D07:0I)
A0902000.config0 GPIOIIS] GPIO[|4] GPIOIIS] GPIOUZ]
A0902004.c0nfigl GPIOHl] gnome] GPIO[9] GPIO[8]
A0902008.configz 0mm Gmom (mom (mom
A090200C.conflg3 GPIO[3] GPIO[2] GPlO[1] optow]
Each GPIO configuration section is set up the same way. The following tflble shows the
settings using hits D07z00; the same settings apply to the corresponding bits in D31124,
D23rD16, and D15:08.
GPIO pin configuration registers
GPIO Configuration
Setings using bits D07:00
D07:06 Reserved N/A
Use these bits to select the function you want to use. For
a detailed description of each function sue the NS 9210
HRM in the Ptnoul chapter under "General pulposc 1/0
(GPIO)" and the "GPlO pin use" table in this manual
1:05:03 thc 000 Function to
001 Function #1
010 Funcliun fiZRESFT_DONE . default for 01mm]
011 Function #3LiPIO - default. except for GPIOUZ]
100 Function tt4
34 intuit DijJi ("ottncct \\ i»! M (22m Hnttltturc Rclctuvcc
Programming Considerslions
GPIO Configuration
Setings using bits D07:00
Controls the pin direction when he FUNC field is
configured for GPIO model, function 133,
o lnpul
D02 DIR lOulpul
All GPIO pins resel lo the inpul smle.
Note: The pin direction is controlled by the selected
function in modes {to dimugh $12.
Conlmls rne inversion funclion omie GPIO pin.
0 Disables ilie inversion function
1 Enables the inversion [unclion
This on applies to all funcrlonnl modes
D0! INV
Controls the GPIO pin pullup resinoroperaiion,
0 Enables the pullup
D00 PUDls I Disables the pullup
Note: The pullup cannot be disabled on GPIO[9],
GPIOUZ]
riurreo 35
GPIO
GPIO [15:0] Control Register
There is one GPIO control Register that governs all 16 GPIO pinsr When a GPIO pin is
configured as a GPIO output, the corresponding bit in the GPIO Control Register is driven
out the GPIO pin, In all configurations, the CPU has read/Write access to these registers.
Register bits D3 1 116 are unused GPIO pins. These pins are being used as memory data bits
15:00. It is safest to read all 32 bits, modify the bit(s) corresponding to the GPlO(s) of
interest, and then write back the full 32 bits, In this way the behavior of the other GPIO
lines will be preserved,
Register D31:24 D23:D16 D15:08 D07:00
A090 206C GPIO [31:24] GPIO [23:16] GPIO [15:21] GPIO [7:0]
not used] not used
GPIO [15:0] Status Register
36
There is one GPIO Status Register. This register contains the status information for each of
the 16 GPIO pinsi Bits D31:16 are used as memory data therefore their status will not be
meaningful In all configurations, the Value on the GPIO input pin is brought to the status
register and the CPU has read—only access to this register.
Register D31124 D231D16 D15:08 D07:00
A090 207C GPIO [31:24] GPIO [23.16] GPIO [15.8] GPIO [7:0]
not used] not used
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GPIO pin use table
Programming Considernrions
G PI 0 P i [1 Us e
Register External A
~ Descrl tian
Name Bit Category Interface p
Used forlhe serial TXD or SPLTX. but
I‘XSD/ P, 4 [h could be reassigned asaGPIO,iimcroul70r
SPLTX/ GPIOI7] Allocated m‘z‘in $2“; in 8.
GP]O»6 liused with me developmenl board. this pin
maps [0 GPJO-s,
Usedc fonhe serial D'I'R but could he
mR/GPIO- Pin 6 ml lhc reassngned as a GPIO. or iimer in 7.
5 WOW “1M“ main header lrused Wllh Ihe development heard, this pill
maps xo GPIOes.
Since ihcse two processor pins map to the
same header pin, one must be configured in
an inpul lo avoid contenlionr
UART- (mom is confiured for RTS and
RTS, GPIOI4] for GPIO inpur.
SPLCLK/ GPIO[5]or A” ‘ d l>in 5 on me SP]: GPIO[5] for GPIO input and (mom
GPlo—4(See GPIOMJ ”C“ 5 main header for SPLCLK,
description) Other: GPIOIS 1 supporis mo; and iimeroul
6.
GPIO|4J suppons IRQZ and urner in 0.
If used with the development board, header
pin 5 maps to GPIOJ,
RXD/ Used for the serial RXD or SPIvRX, bul
could be rcassi ncd as a (‘PIO or PICOJ.
SPLRX/ GPIO[3] Allocnicd Pm} °“ ”w , g ’ , ,
nunn header Ifused will die developmenr hoard. Ihis pm
GPIO-7
maps lo (mo-7.
Used for me serial DSR. but could be
DSR/GPIO- Pin 9 on me reassigned as a GPIO or PICO-Z,
3 GP10[2] A'l‘m'm main header lfused wim me development heard, this pin
maps to GPIO-S.
37
GPIO
38
GPIO Pin Use
Register External . ,
Name Bit Category Interface Description
Used for the serial CTS, but could he
CTS/GPIO» Pin 7 011 the reassigned as a GPIOt IRQO or PlCO-l, If
2 GPIOl ‘1 “hm“ main hcadcr used with the development hoard this pin
maps to GPIO-Z,
DCDN Used for the serial DCD or SPIiEN, out
' could he tenssu ed as a (‘PIO or PICO-O.
SPIiEN/ GP]O[0] Allocated P'“.8 °“ m g" ’ . ,
mam header Ifused wtlh the development board. lhls pin
GPIO-l
mops lo GPIO~1.
Used for the seriniz 7x11 hut could he
TXDZ/ Pin 12 on the reassigncd as a GPIOor timer ln 9.
GPIO»8 GHQ“ 51 A""°"‘°d main header lfused with the development board. this pin
maps to GPIO-S.
Comma to Network link status.
Network the Green On - unit is associated with an access point
link Green GPIOI 14] Reserved LED above Blinking slowly , unit is in ad hoe mode
LED “15 “10W Blinking quickly ~ unit is scanning for a
LED network
Connected to
/lN IT (moi l 3] Available the butlun on Should be configured as a GPlO input.
the module
A Used as the NET+OS green LED. hut can he
. Connected to
Serial Port m reassigned as ageneral purpose LED. lt must
netivity GPK) [12] Allocated £5315 remain a GPIO output for the LED to operate
LED/MFGO (he red LED lcsgcctly. The LED ts itt when the signal 15
Used for the serinlz RXD. but could he
RXDZ/ Pin 1 t on the tedutgned as a GPIO or lkoz.
GPIO-9 Gm“ ” ”Mm“ main ltettder If used with the development board, this pin
maps to Gl’lO—9.
lRQ] GPIO[ 10] Reserved N/A N/A
vulntv-LlJlgl(liliflLL‘ \\; Viv](7110“nlllWalCRL‘lkL’MAIDC
Programming Considerations
GPlO Pin Use
Register External . ,
Name Bil Category Interface Description
MFGI GPIOW] Reserved N/A N/A
. , Connected“) Used for diagnostics and power on
Red m) (imam Allocated (he Red LED Mimic"
Note: The Wi-EM c)210 signals NCO-[0:3] provided by the programmable FlMs
(DRPIC) are only applicable when running NET+OS.
About Embedded Module LEDs
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Embedded Module LED Description
LED Description
Green _ , i . . i . .
This LED IS Wired to the network hardware and provides an indicanun oflink slams
(above yellow LED)
Green This LED is software programmable and is wired to processor GPlO registerbit
(me one above "15 red LED) GPIO[12] and wired to be lit when low. Us: for serial port actiwty.
This LED is wired to the network hardware and provides an indication of network
Yellow activity
This LED is sufiware programmable, wired to processor GPIO rcgisterbil (mom,
Red and wired to be lit when low. LED ON indicates pcwer on and |s l“ addllmn used for
diagnostics,
rurrr.r 39
Embedded Module Reset
Embedded Module Reset
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Hard Reset
The embedded modules support a hardware reset on pin 10 of the 12-pin header. The unit
will be forced into a hard reset if this pin is pulled low. When used with the development
board, this pin is wired to reset button SWS, which means it acts as a hard reset button.
The JTAG version ofthe Wi-EM 9210 EM module has a 3—pinjumper (JP 1) to allow two
modes of operation.
shorted 1-2: The CPU and other registers are reset, The PLL, GPlOs, and memory are not.
Debugger connection is maintained. This is the same as SRST# from the debugger.
shorted 2-3: The entire module is reset. Debugger connection will need to be re—
established.
Soft Reset
NET+OS provides an internal facility to enact a soft reset, but it is the responsibility of a
specific implementation to choose a reasonable trigger to invoke it. One choice is to use a
GPlO pin as a signal to trigger a soft reset. The embedded modules have one GPIO pin
GPIO[13] which is not normally assigred to any other task named "AMT." It is an ideal
candidate for use as a signal for sofl reset. The signal is wired to the push button on the
module (next to the LEDs), and is pulled high unless the button is pushed.
The "naresetapp" sample application demonstrates a simple mechanism for monitoring a
GPlO pin and then initiating a soft reset when the pin achieves a particular value.
Memory
(hr:r:n:.r.rthtLnLl‘rtzLKtuktlzlLIEK‘I'KL:lFLKL‘LF.EI4LI:LLLPI‘EEml.“
Flash
The Wi-EM 9210 module has 4 MB of flash memory, which is controlled by chip select 2
(default 1 sticsl) located at OXSOOOOOOO.
40 mu“; Higi (nitncet \\l mu ofi‘u [laminate regiments
Programming Considerations
SDRAM
The Wi—EM 9210 module has 16 MB of SDRAM memory. controlled by chip select 1
(default : dyicso), located at OXOOOOOOOO.
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Mcmory
42
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muncct \’\’i»1iM 9210 llardwalc Rcl'ucnrc

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