Digi 50M1782 ConnectCore Wi-i.MX53 User Manual 90001270 C 2

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ConnectCore TM for i.MX53 TM
Hardware Reference
90001270_C
5/29/2012
Š2012 Digi International Inc.
All rights reserved.
Digi, Digi International, the Digi logo, a Digi International Company, Digi JumpStart Kit, ConnectCore, and XBee
are trademarks or registered trademarks of Digi International, Inc. in the United States and other countries
worldwide. All other trademarks are the property of their respective owners.
All other trademarks mentioned in this document are the property of their respective owners.
Information in this document is subject to change without notice and does not represent a commitment on the
part of Digi International.
Digi provides this document “as is,” without warranty of any kind, either expressed or implied, including, but
not limited to, the implied warranties of fitness or merchantability for a particular purpose. Digi may make
improvements and/or changes in this manual or in the product(s) and/or the program(s) described in this manual
at any time.
This product could include technical inaccuracies or typographical errors. Changes are periodically made to the
information herein; these changes may be incorporated in new editions of the publication.
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Contents
Chapter 1: About the Module ........................................................ 12
Features and Functionality
Module Variant
Block Diagram
CPU
Module
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External Interface Module (EIM)
NAND Flash Memory
DDR2 SDRAM Memory
Overview
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DA9053 Power Management
+3.3V
+2.775V
+1.8V
+3.15V
Supply Outputs
Battery input (VLIO)
Charger input (VCHRG)
Coin Cell input (VCC_COINCELL)
Supply Inputs
Module Power Supplies
Memory
J2 Pinout
J1 Pinout
Pinout Definitions
Pinout Legend
Power
Module Pinout
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System Boot
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Audio Subsystem
Video Subsystem
Multiplexed GPIO
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GPIO Multiplexing Table
Interfaces
1-Wire
Accelerometer
ADC and Touch Screen
CAN
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Clock Amplifier (CAMP)
Configurable SPI (CSPI)
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Known Issue with the RTC
SATA
ConnectCore for i.MX53 PWM
DA9053 PWM
RTC
Memory Cards (MMCI/eMMC/SD/SDIO)
LVDS Display Bridge (LDB)
PWM
Image Processing Unit (IPU)
Keypad
Graphics Processing Unit 3D (GPU3D)
Graphics Processing Unit 2D (GPU2D)
General Purpose Input/Output (GPIO)
External Interface Module (EIM)
I2 C
Enhanced Configurable SPI (ECSPI)
Ethernet 2
Digital Audio MUX (AUDMUX)
Ethernet 1
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SPDIF
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Synchronous Serial Interface (SSI)
Television Encoder (TVE)
UART
USB Host and USB OTG
Video Processing Unit (VPU)
Watchdog Timer
WLAN
WLAN
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Antenna Specification: RP-SMA
Attributes
Cable Specification: U.FL/W.FL to RP-SMA
Attributes
Dimensions
SAR Requirements
Labelling Requirements
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Chapter 2: About the Development Board ........................................ 70
What’s on the Development Board?
The Development Board
Switches and Push-buttons
Power Switch, S2
Reset Button, S12
UART 2 Switch, S6
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Boot Mode Switch, S9
Boot Device Switch, S8
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Legend for Multi-Position Switches
UART 1 Switch, S7
User Buttons, S3 and S5
Power Button, S13
Ident Button, S10
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Jumpers
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Battery Enable, J13
+3.3V Source, P29
WLAN Disable, J17
WLAN, LE12
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Analog Video Connector, X32
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Analog Video Interface (VGA)
UART 2 Status LEDs
UART 1 Status LEDs
XBee Assoc., LE50
Serial Status LEDs
User LEDs, LE49 and LE51
Power LEDs LE4, LE6, LE7 and LE8
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DIGIO2/XBEE_ON_SLEEP#, R280/R289
DIGIO1/XBEE_SLEEP_RQ, R278/R288
DIGIO0/XBEE_RESET#, R277/R287
UART1_RTS/SD3_CLK, R281/R282
UART1_CTS/SD3_CMD, R283/R284
CSI1_VSYNC#/DISP1_VSYNC, R255/R293
CSI1_HSYNC#/DISP1_HSYNC, R256/R292
CSI1_RESET#/KEY_COL7, R201/R202
CSI0_RESET#/KEY_ROW7, R203/R204
Configuration Resistors
CAN2 Termination resistor, J9
CAN1 Termination resistor, J7
LEDs
Coincell Enable, J3
Autoboot, J6
Touch Selection, J20
JTAG Mod, J4
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Audio Interface
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Line-out Connector Pinout, J18
Line-in Connector Pinout, J12
Microphone Connector Pinou, J15
Camera Interfaces
X15 Pinout
X16 Pinout
CAN Interface
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Parallel LCD Interface
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Module Connectors, J1 and J2
MicroSD™ Connector, X14
MicroSD™ Card Interface
LVDS LCD Interface
Standard JTAG ARM Connector, X13
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I2C Header, P22
JTAG Interface
HDMI Connector, J19
Ethernet 2, Connector J17
Ethernet 2 Interface
Ethernet 1, RJ-45 Connector X7
I2C Interface
Ethernet 1 Interface
Digital I/O Connector, X45
Digital IO Interface
Charger Power Connector
CAN 2, X21
HDMI Interface
CAN 1, X31
Coin Cell Battery
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Peripheral Application Header
Peripheral Application Header, P21
Power-Over-Ethernet (PoE) - IEEE802.3af
The PoE Module
PoE Connector (power in), P19
PoE Connector (power out), P20
PWM Interface
Power Header, P23
SATA Interface
SATA Connector, P2
SD Card Interface
SD/MMC Connector, X18
SPI Interface
SPI Header, P24
UART Interface
UART 1 (Console), X27
UART 2 (MEI), X30
UART 3 (TTL Interface), X19
USB Host Interface
USB OTG Connector, J11
User Interface
WLAN Interface
Digi XBee Interface
Antenna Connectors (WLAN)
USB Host Connectors, J8 and J10
USB OTG Interface
Digi XBee Module Connectors, X28 and X29
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Appendix A: Module Specifications ............................................... 141
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Mechanical Specifications
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Fasteners and Appropriate Torque
Environmental Specifications
Network Interface
Antenna specifications: 802.11 a/b/g antenna
Attributes
Dimensions
Attributes
Dimensions
Ethernet 1
Ethernet 2
WLAN
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General Purpose I/O (GPIOxx) DC Electrical Parameters
Low Voltage I/O (LVIO) DC Electrical Parameters
Ultra High Voltage I/O (UHVIOxx) DC Electrical Parameters
LVDS I/O DC Electrical Parameters
WLAN DC Electrical Parameters
I/O DC Parameters
On-Module Power Supplies
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Current measurement in Minimum configuration
Current measurement in Typical configuration
Current measurement in Maximum configuration
Supply Current
Supply Voltages
Electrical Characteristics
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Standard
Frequency Band
Data Rates
Media Access Control
Wireless Medium
DFS Client
Modulation DSSS
Frequency Bands
Available Transmit Power Settings ( Typical +- ( 2 dBm )@25°C)
Receive Sensitivity
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Antenna Specifications: 802.11b/g antenna
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VDDCORE DC Electrical Parameters
PMIC_IO1 DC Electrical Parameters
PMIC_IO2 DC Electrical Parameters
PMIC_ADC Subsystem (ADIN) DC Electrical Parameters
PMIC_TOUCH DC Electrical Parameters
Ethernet (ETH) DC Electrical Parameters
Analog RGB (RGB) DC Electrical Parameters
Digital USB (DIG_USB) DC Electrical Parameters
Analog USB (AN_USB) DC Electrical Parameters
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Appendix B: Module Dimensions ................................................... 157
Top View
Bottom View
Side View
Connectors
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Appendix C: Certifications .......................................................... 161
FCC Part 15 Class B
Radio Equipment - FCC Warning Statement
Radio Equipment - Canadian Warning Statements
161
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Appendix D: Change Log ............................................................ 163
Revision A
Revision B
Revision C
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Using this Guide
This guide provides information about the Digi ConnectCore for i.MX53 embedded
core module family.
Conventions used in this guide
This table describes the typographic conventions used in this guide:
This convention
Is used for
Digi Information
Document Updates
Please always check the product specific section on the Digi support website at
www.digiembedded.com/support for the most current revision of this document.
Contact Information
For more information about your Digi products, or for customer service and
technical support, contact Digi International.
To contact Digi International by
Use
Additional Resources
Please also refer to the most recent Freescale i.MX53 Application Processor
Reference Manual (IMX53RM) and related documentation for additional information.
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About the Module
he network-enabled ConnectCore for i.MX53 is a highly integrated and future-proof
System-on-Module (SOM) solution based on the new FreescaleÂŽ i.MX535/i.MX536 application
processor with a high-performance ARMÂŽ Cortex-A8ÂŽ core, powerful multimedia options,
and a complete set of peripherals.
The module combines the fast integration, reliability and design flexibility of an off-theshelf SOM with complete out-of-the-box software development support for platforms such
as MicrosoftÂŽ WindowsÂŽ Embedded CE 7.0, DigiÂŽ Embedded Linux ÂŽ, TimesysÂŽ LinuxLinkÂŽ,
and AndroidTM.
With industry-leading performance and key features like a dual-display interface and a
hardware encryption engine, the module is the ideal choice for a broad range of target
markets including medical, digital signage, security/access control, retail, industrial/
building automation, transportation and more.
Complete and cost-efficient Digi JumpStart Kits TM for Microsoft Windows Embedded
Compact 7.0, Linux and Android allow immediate and professional embedded product
development with dramatically reduced design risk and time-to-market.
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Features and Functionality
The ConnectCore for i.MX53 module is based on the i.MX53 processor from Freescale. This
processor offers a high number of interfaces. Most of these interfaces are multiplexed and
are not available simultaneously. The module has the following features:
„High-end,
low-power 32-bit System-on-Module
„Freescale
i.MX535/i.MX536 processor
– Cortex-A8 at 1GHz/800 MHz
– 32Kbyte L1 instruction and 32Kbyte L1 data cache
– 256Kbyte L2 cache
– NEON coprocessor
– Vector Floating Point (VFP) unit
„SLC
„Up
and MLC NAND flash support on module
to 2GB 32-bit/200 MHz DDR2-800 memory
„Dialog
DA9053 Power Manager IC
– Programmable battery charger
– 4 buck converters and 10 LDO’s to supply processor and peripherals
– RTC counter with Coin Cell input
– White LED driver boost for three LED strings
– ADC and touch screen interface
„Debug
interfaces
– Standard JTAG controller IEEE 1149.1
– ETM/ETB
„SAHARA
Security co-processor that includes
– Encryption (AES, DES and 3DES)
– Hashing algorithms (MD5, SHA-1, SHA-224 and SHA-256)
– Cipher algorithm (ARC4)
– Hardware random number generator
„RTC
„Timer
„Two
watchdog timers
„Up
to 5 UART ports, up to 4Mbps each
„Up
to 3 SPIs, (two of them up to 54Mbps each)
„Up
to 3 I2Cs (up to 400Kbps)
„SATA
„2
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controller
controller area network (FLEXCAN), 1Mbps each
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„8/16-bit
„4
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external memory interface
memory card interfaces (3 for the wireless version of the module)
– SD/SDIO - 1 and 4-bits (up to 200Mbps)
– MMC - 1, 4 and 8-bits (up to 416Mbps)
„USB
– Up tp 3x USB 2.0 high-speed USB Host ports
– 1 USB Host with integrated high-speed PHY
– 1 high-speed USB 2.0 on-the-go USB port with integrated PHY
„2
parallel camera ports
„Display
– 5 interfaces available. Total rate of all interfaces is up to 180Mpixels/sec, 24 bits per
pixel. Up to 2 interfaces may be active at once.
– 2x parallel 24-bit display ports up to 165Mpixels/sec (UXGA@60Hz)
– 2x LVDS serial ports. 1 port up to 165Mpixels/sec or 2 ports (WXGA@60Hz) each
– 1 TV-out/VGA port up to 150Mpixels/sec (1080p at 60Hz)
„4-wire
„SPDIF
resistive touch screen with pen pressure measurement
output
I2S/AC97/SSI, up to 1.4Mbps each connected to Audio Multiplexer providing 4
external ports
„3
„1-wire
interface
„Keypad
„Up
port
to 4 independent PWM interfaces
„GPIO
„Up
with interrupt capabilities
to 3x 10-bit ADC channels
„On-module
three axis accelerometer (optional)
„On-module
10/100 Ethernet controller (optional)
„Second
on-module 10/100Mbit Ethernet interface (optional)
„2.4GHz
& 5GHz IEEE 802.11a/b/g/n wireless LAN interface (optional)
– Future 802.11abgn + Bluetooth 4.0 option
„Complete
Microsoft Windows Embedded Compact 7, Linux and Android platform
support with BSP source code
Module Variant
The ConnectCore for i.MX53 module is available with various population options such as
network interfaces (Ethernet, WLAN), memory (flash, RAM), processor (speed grade/
operating temperature) and others.
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Block Diagram
The following figures show the block diagram of the Freescale i.MX535 CPU and the block
diagram of the ConnectCore for i.MX53 module.
CPU
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Module
ConnectCore i.MX53
180-pin
i Connector
CPU i.MX53
Security
Module
ConEgurA?@A
Memory
System Control
Timers
DDR2 Memory
EMI
NONPQR;ASTQULVWX
Memory
ARM Core
L=Art DMA
IPU
InterfAMes
InterfAces
ZYT>[\>YQ]HY
C 3892
DA9053
PMIC
Power Mgmt
EYTernet
Controller
Buck SwitcTes
dVON
b ADC
10-bit
VPe RegulAYor
ToucT I/F
Boost SwitcT>S
RTC
CPU I/F
Ext>[\A;
Power Supply
Accelerometer
180-pin Connector
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Module Pinout
The module has two 180-pin connectors, J1 and J2. The following tables describe each pin,
its properties, and its use on the module and development board. The DC parameters for
each I/O type are defined in the "I/O DC Parameters" section of Appendix A - Module
Specifications.
The ‘Use on module’ column shows the connection of the signals on the module. The format
of this column is component: pad_name, where ‘component’ indicates the connected
component on the module, and ‘pad_name’ indicates the corresponding component signal
(per datasheet).
Pinout Legend
Low level active signal
NC
Pin not connected on module
Pinout Definitions
GPIO - General Purpose IO
UHVIO - Ultra High Voltage IO
HSGPIO - High Speed GPIO
LVIO - Low Voltage IO (meaning 1.8V)
I/O Type descriptions can be read as follows:
„18
- 1.8V logic level switching (for example, GPIO18)
„27
- 2.775V logic level switching (for example, GPIO27)
„31
- 3.15V logic level switching (for example, UHVIO31)
„33
- 3.3V logic level switching (for example, UHVIO33)
J1 Pinout
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Power
Module Power Supplies
The following figure shows the power supply scheme of the ConnectCore for i.MX53 module.
Supply Inputs
The ConnectCore for i.MX53 module has the following supply inputs:
„Battery
input (VLIO)
„Charger
input (VCHRG)
„Coin
Cell input (VCC_COINCELL)
Batte ry inpu t (V LIO)
The VLIO supply is used to generate all the voltage supplies needed by the ConnectCore for
i.MX53. The minimum voltage of VLIO (allowing the module to power up) is +3.4V. The
maximum voltage of VLIO is +4.8V.
This input is the recommended when only one of the two main power inputs (VLIO, VCHRG) is
used. The benefit of using this as the Main input is that power restrictions are relaxed and a
higher overall current may be drawn through this input. If this is used as the Main power
input, the other input VCHRG can be left disconnected. If this is the only power input used,
the supply must be rated to maintain the voltage on this input during times of peak demand
by the module.
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Ch arger in put (V CH RG )
The battery charger supply is used to charge rechargeable batteries, as well as to power up
the module when the battery is discharged or not connected. The minimum voltage of the
battery charger is +3.4V. The maximum voltage of the battery charger is +5.5V.
Whether this input is used depends on the Host Circuit. If a Lithium Ion secondary cell is
connected to VLIO this input is necessary, but the minimum voltage to allow the Lithium Ion
cell to charge means that the effective minimum input voltage rises to +4.5V. Note that the
i.MX53 module will still work when VCHRG is lower, but the battery will not charge. When
there is a Lithium Ion cell connected to VLIO and power is also applied to VCHRG, the current
needed by the i.MX53 module and anything that the module powers can be shared between
the two inputs. This allows a measurement of the average current to be taken and after
allowing a margin for variation and also for the charging of the battery, this figure can be
used as the amount needed at the VCHRG input. In this circumstance the peaks drawn by the
module are taken from the battery, thus allowing for a smaller power supply to power
VCHRG.
If there is no Lithium Ion secondary cell on VLIO, it is still allowed to use the VCHRG power
input as the Main input, in which case the VLIO input can be left disconnected. The benefit of
using this input as the Main input is that it has a wider input voltage range than VLIO. There
are some limitations on the amount of current that can be drawn (especially during powerup), this may mean that Carrier boards for the module that use this power input alone may
need to have software controlled power features to prevent the load exceeding the current
capabilities. If this is the only power input used, the supply must be rated to maintain the
voltage on this input during times of peak demand by the module.
Co i n C e l l i n p u t ( V C C_ CO I N CE L L )
A connection for a coin cell or supercap is provided at VCC_COINCELL. This power pin can
provide power to the RTC even without a connected main battery. If higher voltage is present
on the main battery or charger inputs, the main battery/charger will be used as a power
source instead.
There are three types of components that can be connected to this pin: Lithium coin cells
(Primary cell: non-rechargeable), Lithium coin cells (Secondary cell: rechargeable), and
Supercaps. When a Primary Lithium coin cell is connected, the charger must be turned off
and this pin is used strictly as an input. It is hazardous to attempt to charge Primary Lithium
cells as they may vent or explode. Secondary Lithium coin cells are only made available
directly to manufacturers of equipment that could use them, in that case they are normally
required to design their product to prevent the user gaining access to this part since there is
a danger to the user if by replacing it, they fit a primary type (the only sort that they are
likely to be able to source) into the charging circuit. When a Secondary Lithium coin cell is
used, both the charging current and the termination voltage are programmable. When a
Supercap is used, both the charge current and termination voltage should be set to the
maximum values.
The advantage of using a Primary Lithium coin cell is that the energy density usually allows
years of service since the self discharge rate is low. The advantage of using a Secondary
Lithium coin cell is that the self discharge rate is usually sufficient to allow a few months of
support for the RTC before it will need recharging. The advantage of the Supercap is that it is
intrinsically safe and can out-last the Primary Lithium coin cell option, however the self
discharge rate is high meaning that a 1F capacitor at 25° C is likely to support the RTC for
approximately 5 to 10 days.
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A programmable constant charge current charger with a programmable top-off charging
voltage is provided for charging of Secondary Lithium-Manganese coin cell batteries and
super capacitors. Charging current is programmable from 100uA to 6mA. Termination voltage
is programmable from +1.1 to +3.1V.
The minimum voltage of the coin cell supply is +2V. The maximum voltage of the coin cell
supply is +3.6V.
Supply Outputs
The ConnectCore for i.MX53 module provides the following supply outputs:
„+3.3V
„+2.775V
„+1.8V
„+3.15V
+3 . 3V
The ConnectCore for i.MX53 module has a DC/DC converter to generate a +3.3V supply. This
supply is used on the module to power the WLAN interface, the Ethernet PHY and the
Ethernet Controller.
This power regulator can be enabled/disabled by software to save power when the module is
in the low power modes. The maximum current provided by this regulator is 1A.
The current available to supply off-module components is 400mA for the wireless variants of
the ConnectCore for i.MX53, and 800mA for the wired-only variant of the ConnectCore for
i.MX53. If the module is powered from the charger, the maximum charger current limit
(1800mA) may limit the current available to supply off-module components.
+2 . 77 5 V
This supply is generated by LDO4 of the DA9053 PMIC. This supply is used on the module to
power the CPU peripherals, the Ethernet PHY, the accelerometer and the CPU image
processing unit. The maximum current provided by this supply is 150mA.
The current available to supply off-module components is 80mA.
+1 . 8V
This supply is generated by LDO8 of the DA9053 PMIC. This supply is used on the module to
power the External Interface Module (EIM), the JTAG interface, the touch screen controller
and the Ethernet controller. The maximum current provided by this supply is 200mA.
The current available to supply off-module components is 100mA.
+3 . 15 V
This supply is generated by LDO6 of the DA9053 PMIC. This supply is used in the module to
power the NAND flash interface, the SD interfaces and the PATA controller. The maximum
current provided by this supply is 150mA.
The current available to supply off-module components is 100mA.
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DA9053 Power Management
The ConnectCore for i.MX53 module integrates a Dialog DA9053 Power Management chip. This
chip provides reference and supply voltages for the ConnectCore for i.MX53 processor as well
as for the peripheral devices.
The DA9053 provides four buck switchers and ten low dropout regulators. The start-up of
DA9053 supplies is performed with a configurable sequencer. The DA9053 also provides a
battery charger that supports current/voltage charging at currents up to 1.25A. Other
interfaces as touch screen, general purpose 10bit ADC and PWM are also included on the
DA9053.
The following figure shows a block diagram of the DA9053.
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Memory
Overview
The i.MX53 processor has an External Memory Controller (EXTMC) that services all the
external memory access requests. The EXTMC provides the arbitration interface and different
external memory controllers in order to support several memory devices:
„M4IF
– Multi Master Multi Memory Interface
„ESDRAMC
„NFC
„EIM
– Enhanced DDR memory controller
– NAND flash memory controller
– SRAM/PSRAM/NOR/NOR flash memory controller
DDR2 SDRAM Memory
The ConnectCore for i.MX53 module provides up to 2GB of DDR2-800 SDRAM memory. On the
module in the development kits four 16-bit, 128Mbit, DDR2-800 chips, configured as two
banks of 32-bits of 128Mbits DDR2-800 memory are used.
NAND Flash Memory
The ConnectCore for i.MX53 module provides 8GB of NAND flash memory. On the module in
the development kits a 512MByte, 2Kbyte page, NAND flash chip is used. This NAND flash
device is connected to NAND flash Chip Select 0.
The NAND flash controller signals are available on the module connectors.
External Interface Module (EIM)
The External Interface Module (EIM) is used on the ConnectCore for i.MX53 module to control
the Ethernet Controller. This device is connected to EIM Chip Select 1.
The EIM signals are available on the module connectors.
System Boot
The ConnectCore for i.MX53 boot process begins at Power On Reset when the hardware reset
logic forces the ARM core to begin execution starting from the on-chip boot ROM. Boot ROM
code uses the state of the internal register BOOT_MODE[1:0] as well as the state of various
eFUSEs and/or GPIO settings to determine the boot flow behavior of the module.
The ConnectCore for i.MX53 supports the following boot modes:
„Internal
boot
– The module boots from the internal ROM
– Program Image loaded from the chosen boot device
– Boot flow controlled by GPIO and eFUSE (GPIO overrides eFUSE settings)
– Supports a secure boot using HAB
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„Boot
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from fuses
– Same as internal boot but GPIO boot override pins are ignored
„Serial
Downloader
– Supports UART and USB
The ConnectCore for i.MX53 supports the following boot devices:
„NOR
flash with External Interface Module (EIM), located on CS0, 16-bits bus width
„One
NAND flash with EIM, located on CS0, 16-bits bus width
„NAND
flash
„SD/MMC
„Parallel
ATA (PATA)/Serial ATA (SATA) HDD
ROM devices (SPI and I2C EEPROM)
„Serial
Audio Subsystem
The audio subsystem provided by the ConnectCore for i.MX53 consists of the SSI, SPDIF and
the AUDMUX blocs. In addition, the IOMUXC must be configured for appropriate signal
directions.
Video Subsystem
The ConnectCore for i.MX53 has a video subsystem that includes the following modules:
„Video
Processing Unit (VPU): a multi-standard video/image codec
„Two
Graphics Processing Units (GPUs): one for accelerating 3D graphics (OpenGL/ES),
and one for accelerating vector graphics (OpenVG and 2D graphics BitBLT)
„Image
Processing Unit (IPU): providing connectivity to cameras and displays, related
processing, synchronization and control
„Display
interface bridge: providing optional translation from the digital display
interface supported by the IPU to other interfaces:
– TV encoder (TVE) bride: composite, S-video, component and VGA interfaces
– LVDS bridge: up to two LVDS interfaces
The following figure on the next page shows the block diagram of the Video Subsystem:
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Multiplexed GPIO
GPIO Multiplexing Table
The ConnectCore for i.MX53 has seven GPIO banks. Each bank provides up to 32 bidirectional
general purpose input and output signals.
The GPIO pins are multiplexed with other functions on the module. The IOMUX controller
allows the configuration of the pin functions (ALT Mode) and other options (pull-up, keeper,
etc).
The table below shows the default configuration of the GPIO pins, the name of the Pad and
the default use on the ConnectCore for i.MX53 module. For a detailed description of all the
muxing options for each pin, please refer to the Freescale i.MX53 Reference Manual
(IMX53RM).
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Interfaces
1-Wire
The ConnectCore for i.MX53 provides a 1-Wire interface to communicate with 1-Wire devices
such as EEPROMs, secure memory and sensors. The required protocol for accessing the
generic 1-Wire device is defined by Maxim.
The 1-Wire interfaces offer the following capabilities:
„Performs
the 1-Wire bus protocol to communicate with an external 1-Wire device.
„Provides
a clock divider to generate a 1-Wire bus reference clock.
„Supports
byte transfers with optional interrupts for more efficient programming.
„Provides
a search ROM accelerator mode to speed the search ROM protocol.
Accelerometer
The module provides a three axis digital output accelerometer. This device is connected to
the CPU through the I2C bus.
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The accelerometer offers the following:
„User
assigned registers for offset calibration
„Programmable
„Level
detection for motion recognition (shock, vibration, freefall)
„Pulse
detection for single or double pulse recognition
„Selectable
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threshold interrupt output
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sensitivity (Âą2g, Âą4g, Âą8g) for 8-bit mode
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ADC and Touch Screen
The module provides an Analogue to Digital Converter (ADC) and Touch Screen Interface. The
ADC/Touch interface is part of the integrated DA9053 PMIC.
The ADC has a 10 bit resolution and a track and hold circuitry combined with an analog input
multiplexer. The analog multiplexer allows conversion of up to 10 different inputs.
The track and hold circuit ensures stable input voltages at the input of the ADC during the
conversion.
The following table shows the ADC channel assignments:
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CAN
The ConnectCore for i.MX53 provides two FlexCAN controllers implementing the CAN protocol
according to the CAN 2.0B protocol specification. The CAN block includes two embedded
memories, one for storing Message Buffers and another one for storing Rx Individual Mask
Registers.
The FlexCAN controllers include these distinctive features:
„Full
Implementation of the CAN protocol specification
– Standard data and remote frames
– Extended data and remote frames
– Zero to eight bytes data length
– Programmable bit rate up to 1 Mb/sec
– Content-related addressing
„Deterministic
„Flexible
behavior and increased reliability of FlexCAN
Message Buffers of zero to eight bytes data length
„Each
Message Buffer configurable as Rx or Tx, all supporting standard and extended
messages
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„Individual
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Rx Mask Registers per Message Buffer
„Includes
1056 bytes (64 Mbytes) of RAM used for Message Buffer storage
„Includes
256 bytes (64 Mbytes) of RAM used for individual Rx Mask Registers
„Full
featured Rx FIFO with storage capacity for 6 frames and internal pointer handling
„Powerful
Rx FIFO ID filtering, capable of matching incoming IDs against either 8
extended, 16 standard or 32 partial (8 bits) IDs, with individual masking capability
„Selectable
backwards compatibility with previous CAN version
„Programmable
clock source to the CAN Protocol Interface, either bus clock or crystal
oscillator
„Unused
message buffer and Rx Mask Register space can be used as general purpose
RAM space
„Listen
only mode capability
„Programmable
loop-back mode supporting self-test operation
„Programmable
transmission priority scheme: lowest ID, lowest buffer number or
highest priority
„Time
Stamp based on 16-bit free-running timer
„Global
network time, synchronized by a specific message
„Maskable
interrupts
„Independent
„Short
„Low
of the transmission medium (an external transceiver is assumed)
latency time due to an arbitration scheme for high-priority messages
power modes, with programmable wake up on bus activity
„Configurable
Glitch filter width to filter the noise on CAN bus when waking up
Clock Amplifier (CAMP)
The ConnectCore for i.MX53 provides two inputs connected to a clock amplifier. The clock
amplifier converts a square wave/sinusoidal input of frequency range 8-40 MHz, into a +1.8V
rail to rail square wave.
The input to the CAMP is internally AC coupled. No external coupling is required.
The outputs of the CAMP are connected to the Clock Control Module (CCM) of the
ConnectCore for i.MX53.
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Configurable SPI (CSPI)
The ConnectCore for i.MX53 module provides one Configurable SPI (CSPI) interface that can
be configured in either master or slave mode. The CSPI contains an 8 x 32 receive buffer
(RXFIFO) and an 8 x 32 transmit buffer (TXFIFO).
Key features of the CSPI include:
„Full-duplex
synchronous serial interface
„Master/Slave
„Four
Chip Select (SS) signals to support multiple peripherals
„Transfer
„32-bit
„Direct
continuation function allows unlimited length data transfers
wide by 8-entry FIFO for both transmit and receive data
„Polarity
„Max
configurable
and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable
Memory Access (DMA) support
operation frequency up to one quarter of the reference clock frequency
Digital Audio MUX (AUDMUX)
The Digital Audio Multiplexer (AUDMUX) provides a programmable interconnect device for
voice, audio, and synchronous data routing between host serial interfaces, such as SSI, and
peripheral serial interfaces-that is, audio and voice codecs.
The AUDMUX includes two types of interfaces. Host ports connect to the processor serial
interfaces, and peripheral ports connect to off-chip audio devices. A desired connectivity is
achieved by configuring the appropriate host and peripheral ports.
The AUDMUX provides flexible, programmable routing of the on-chip serial interfaces to and
from off-chip audio devices. The AUDMUX routes audio data but does not decode or process
audio data itself.
Enhanced Configurable SPI (ECSPI)
The ConnectCore for i.MX53 module provides two Enhanced Configurable SPI (ECSPI)
interfaces that can be configured in either master or slave mode. The ECSPI contains a 
64 x 32 receive buffer (RXFIFO) and a 64 x 32 transmit buffer (TXFIFO).
Key features of the ECSPI include:
„Full-duplex
synchronous serial interface
„Master/Slave
„Four
Chip Select (SS) signals to support multiple peripherals
„Transfer
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continuation function allows unlimited length data transfers
„32-bit
wide by 64-entry FIFO for both transmit and receive data
„32-bit
wide by 16-entry FIFO for HT message data
„Polarity
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configurable
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and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable
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„Direct
„Max
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Memory Access (DMA) support
operation frequency up to the reference clock frequency
Ethernet 1
The ConnectCore for i.MX53 provides a Fast Ethernet Controller (FEC) designed to support
both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. A low-power 10/100 Ethernet PHY
(SMSC LAN8710A) is integrated on the module.
The module does not provide a transformer and Ethernet connector.
The PHY address on the MII bus is 0x7 (0b00111).
The module also provides two status signals for activity and link LEDs.
Ethernet 2
The ConnectCore for i.MX53 module can provide an optional high-performance 10/100Mbit
Ethernet controller (SMSC LAN9221) with integrated MAC and PHY as a second Ethernet port.
Key features of the second Ethernet controller:
„Embedded
„Support
16 Kbyte FIFO for packet buffers
burst-mode read for highest performance applications
„Configurable
„Compatible
„Integrate
„10Mbps
„Full
interrupt pin with programmable hold-off timer
with IEEE 802.3, 802.3u standards
Fast Ethernet MAC/PHY transceiver in one chip
and 100Mbps data rate
and half duplex operations
„10/100Mbps
„Twisted
„EEE
Auto-negotiation operation
pair crossover detection and auto-correction (HP Auto-MDIX)
802.3x flow control for full-duplex operation
„Wake-on-LAN
„LED
capabilities:
pins for various network activity indications
The Ethernet controller is connected to EIM_CS1#. Its programmable polarity interrupt
output is connected to the signal GPIO4_2.
The module does not have a transformer and Ethernet connector.
The module provides two status signals for activity and link LEDs.
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External Interface Module (EIM)
The ConnectCore for i.MX53 module provides access to the External Interface Module (EIM) of
the i.MX53 processor. The EIM allows interfacing devices external to the ConnectCore for
i.MX53, including generation of chip selects, clock and control for external peripherals and
memory. It provides asynchronous access to devices with SRAM-like interface and
synchronous access to devices with NOR-flash-like or PSRAM-like interface.
Key features of the External Interface Module:
„Support
for multiplexed address/data bus operations x16 and x32
„Programmable
„Up
to 6 Chip select with selectable Write Protection for each Chip Select
„Read
and write control lines
„26-bit
„2x
data port size of each Chip select (x8, x16 and x32)
address bus
byte enable signals
„Asynchronous
„Support
accesses with programmable setup and hold times for control signals
for Asynchronous page mode accesses (x16 and x32 port size)
„Independent
synchronous Memory Burst Mode support for Nor-flash and PSRAM
memories (x16 and x32 port size)
„Support
for Big Endian and Little Endian operation modes per access
General Purpose Input/Output (GPIO)
The GPIO peripheral provides dedicated general-purpose pins that can be configured as
either inputs or outputs. When configured as an output, it is possible to write to an internal
register to control the state driven on the output pin. When configured as an input, it is
possible to detect the state of the input by reading the state of an internal register.
In addition, the GPIO peripheral can produce CORE interrupts.
Each GPIO input has a dedicated edge-detect circuit which can be configured through
software to detect rising edges, falling edges, logic low-levels or logic high-levels on the
input signals. The outputs of the edge detect circuits are optionally masked by setting the
corresponding bit in the interrupt mask register.
The GPIO includes the following features:
„General
purpose input/output logic capabilities:
– Drives specific data to output using the data register (GPIO_DR)
– Controls the direction of the signal using the GPIO direction register (GPIO_GDR)
– Enables the core to sample the status of the corresponding inputs by reading the pad
sample register (GPIO_PSR).
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„GPIO
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interrupt capabilities:
– Supports up to 32 interrupts
– Identifies interrupt edges
– Generates three active-high interrupts to the ConnectCore for i.MX53 interrupt
controller
Graphics Processing Unit 2D (GPU2D)
The 2D graphics processing unit is an embedded 2D and vector graphics accelerator. The
GPU2D is divided into two segments. The first accelerates 2D bitmap graphics operations.
The second one accelerates vector graphics rendering with anti-aliasing polygon rasterizer.
Key features of the GPU2D:
„Frame
buffer size support up to 2048x2048
„Linear
and block-based (4x4 pixels) frame buffer modes
„Fast
buffer clears
„Support
for OpenVG render to Image
Main features of the 2D bitmap graphics unit:
„BitBlt
(surface-to-surface copy)
„Block
fill
„Internal
32-bit color precision
„Supports
three source bitmaps for separate mask/pattern/alpha bitmap support plus
reading destination for ROP, blend and color key operations
„Supports
masking source coordinates for wrapping patterns
„Supports
inverting mask and alpha values from source
„Supports
destination rotation by 0/90/180/270 degrees
„Supports
programmable blending with optional alpha un-premultiply
„Supports
color keying by source and destination colors, with optional ignoring of alpha
channel
„Supports
„Dithering
one scissor rectangle for destination coordinates
(ordered)
„Color
component masking
„sRGB
reads and writes
„BitBlt
with scaling, bilinear filtering with texture lookups, programmable filter
kernels possible with the programmable Pixel processor
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Key features of the vector graphics unit:
„Rasterization
of convex and concave polygons with anti-aliasing
„Efficient
native polygon rendering (no tessellation to triangles)
„Non-zero
and odd-even fill rules
„Primitives
supported:
– Polygons
– OpenVG path primitives
– Curve types supported: cubic and quadratic Bézier
– Strokes with thickness, joints and end caps, unlimited stroke thickness
– Supports paths with a maximum of 256 crossings along a horizontal or a vertical line
„Input
coordinates:
– Absolute and relative coordinate input in floating point
– Fixed-point and floating-point coordinate input - 0.8, 0.16, 16.16 formats
„Geometry:
– User to surface transform for vertices and stroke shape
– Hardware curve tessellation
– Adjustable accuracy for curve and round cap splitting
– OpenVG/SVG join types: Miter (with miter limit), round, bevel
– OpenVG/SVG cap types: Butt, round, square
„Pixel
processing:
– Programmable gradient and texturing processor
– Linear and radial gradients (with focal point)
– Perspective texture mapping with filtering
– Two textures supported
– sRGB and pre-multiply support for textures
– 16-sample anti-aliasing
– Per-pixel alpha-masking
– Maximum texture size: 1024x1024 pixels
„Vector
graphics rendering system ARM platform load:
– Display list generation during path creation - commands and vertices are stored to an
internal format/buffer, no format conversion is performed
– Filling or stroking a path only requires a few register writes to start the operation in
hardware
– Display lists are transferred to the vector graphics rasterizer using DMA without ARM
platform interaction
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Graphics Processing Unit 3D (GPU3D)
The 3D Graphics Processing Unit (GPU3D) is an embedded engine capable of DirectX9 Shader
Model 3.0+ program execution. The unit is focused on accelerating user level graphics APIs.
Main features of the GPU3D:
„Built
to accelerate OpenGL ES 2.0
„Uses
shading architecture to share resources between vertex and pixel shaders
„Advanced
packet based command processor for efficient host-GPU transfers
„Integrated
„Customer
Power Management
configurable on-chip memory used to accelerate 3D rendering
I2C
The ConnectCore for i.MX53 module provides up to three I2C interfaces. The I2C interfaces
operate up to 400Kbps, depending on pad loading and timing characteristics. The I2C system
is a true multiple master bus including arbitration and collision detection that prevents data
corruption if multiple devices attempt to control the bus simultaneously.
The I2C port 3 interface is used on the module to communicate to the accelerometer and to
the DA9053 PMIC. Two 2K2 pull-up resistors connected to +2.775V are provided on the
module. This bus is available at the module connector J2.
The I2C interfaces provide the following capabilities:
„Compatibility
with I2C bus standard
„Multiple-master
operation
„Software
programmable for one of 64 different serial clock frequencies
„Software
selectable acknowledge bit
„Interrupt-driven,
„Arbitration-lost
„Calling
„Start
and stop signal generation detection
START signal generation
„Acknowledge
„Bus-busy
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interrupt with automatic mode switching from master to slave
address identification interrupt
„Repeated
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byte-by-byte data transfer
bit generation/detection
detection
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Image Processing Unit (IPU)
The Image Processing Unit (IPU) provides comprehensive support for the flow of data from an
image sensor and/or display device:
„Connect
relevant devices - cameras, displays, graphics accelerators, TV encoders and
decoders
image processing and manipulation: sensor image signal processing, display 
processing, image conversions, etc.
„Related
„Synchronization
and control capabilities (for example, to avoid tearing artifacts)
The following figure shows the simplified block diagram of the IPU:
Image Processing Unit (IPU)
CSI
CSI
CameraQSensorQI/F
CameraQSensorQI/F
SMFC
VDI
VideoQDekInterlacer
DI
DI
Display I/F
Display I/F
IC
Image Converter
IDMAC
Image DMAQ
Controller
DP
Display processor
DMFC
DC
Display Control
CM
ControlQModule
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IRT
Image Rotator
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The image processing unit has the following blocks:
„2x
Camera Sensor Interface - CSI
– Controls a camera port; provides interface to an image sensor or a related device.
„2x
Display Interface - DI
– Provides interface to displays, display controllers and related devices.
„Display
Controller - DC
– Controls the display ports
„Display
Processor - DP
– Performs the processing required for data sent to display
„Image
Converter - IC
– Performs resizing, color conversion/correction, combining with graphics, and
horizontal inversion
„Video
De Interlacer - VDI
– Performs video de interlacing (interlaced -> progressive)
„Image
Rotator - IRT
– Performs rotation (90 or 180 degrees) and inversion (vertical/horizontal)
„Image
DMA Controller - IDMAC
– Controls the memory port; transfers data to/from system memory
„Sensor
Multi FIFO Controller - SMFC
– Controls FIFOs for output from the CSIs to system memory
„Display
Multi FIFO Controller - DMFC
– Controls FIFOs for IDMAC channels related to the display system
„Control
Module - CM
– Provides control and synchronization
For more in-depth information regarding the blocks of the IPU please refer to the 
Freescale i.MX53 Applications Processor Reference Manual (IMX53RM).
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Keypad
The ConnectCore for i.MX53 module provides a keypad port that can be used as a keypad
matrix interface or as general purpose input/output.
The Keypad port interface to a keypad matrix with 2-point contact or 3-point contact keys.
The Keypad port is designed to simplify the software task of scanning a keypad matrix. With
appropriate software support, the Keypad port is capable of detecting, debouncing, and
decoding one or multiple keys pressed simultaneously on the keypad.
The Keypad Port includes these features:
„Supports
„Port
up to an 8 x 8 external keypad matrix
pins can be used as general purpose I/O
„Open
drain design
„Glitch
suppression circuit design
„Multiple-key
„Long
detection
key-press detection
„Standby
key-press detection
„Synchronizer
„Supports
chain clear
a 2-point and 3-point contact key matrix
LVDS Display Bridge (LDB)
The LVDS Display Bridge (LDB) is used to connect the Image Processing Unit (IPU) to an
external LVDS display interface.
The LDB provides following ports:
„Two
parallel display port inputs
„Two
LVDS channel outputs – each channel consisting of 4 data pairs, and 1 clock pair
„Control
„Clocks
signals – to configure LDB parameters and operations
from SoC DPLLs
The RGB input data interface contains RGB data (18 or 24 bits), pixel clock and control
signals (HSYNC, VSYNC and DE). The rates supported are:
„For
single-channel output: Up to 170 MHz pixel clock (for example, UXGA -1600x1200
@ 60 Hz + 35% blanking)
dual-channel output: Up to 85 MHz per interface (for example, WXGA -1366x768 
@ 60 Hz + 35% blanking)
„For
The two LVDS ports may be used as follows:
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„One
single-channel output
„One
dual channel output: single input, split to two output channels
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„Two
identical outputs: single input sent to both output channels
„Two
independent outputs: two inputs sent, each to a different output channel
Memory Cards (MMCI/eMMC/SD/SDIO)
The ConnectCore for i.MX53 module provides up to four Enhanced Secured Digital Host
Controllers (ESDHC) to interface between the i.MX53 CPU and MMC/eMMC/SD/SDIO devices.
The ESDHC acts as a bridge, passing host bus transactions to the cards by sending commands
and performing data accesses to/from the cards. It handles the MMC/eMMC/SD/SDIO
protocols at the transmission levels.
The types of cards supported by the ESDHC are described briefly as follows:
„MultiMediaCard
(MMC)
This is a universal low-cost data storage and communication media that is designed to
cover a wide area of applications including mobile video and gaming, WLAN or other
wireless networks. Old MMC cards are based on 7-pin serial bus with a single data pin,
while the newer high-speed MMC communication is based on an advanced 11-pin serial
bus designed to operate at lower voltage.
„Embedded
Multimedia Card (eMMC)
The eMMC describes an architecture consisting of an embedded storage solution with
MMC interface, flash memory and controller, all in a small ball grid array (BGA) package.
„Secure
Digital (SD) card
This is an evolution of earlier MMC technology. It is specifically designed to meet the
security, capacity, performance, and environment requirements inherent in newly
emerging audio and video consumer electronic devices. The physical form factor, pin
assignment and data transfer protocol are forward compatible with MMC, with some
additions. Under the SD protocol, an SD card can be categorized as memory card, I/O
card, or combo card (having both memory and I/O functions).
The main features of the ESDHC are the following:
„Designed
to work with MMC, MMC plus, MMC RS, SD memory, miniSD memory, SDIO,
and SD Combo. Compatible with the following specifications:
– MMC System Specification versions 4.2/4.3/4.4
– SD Host Controller Standard Specification version 2.0
– SD Memory Card Specification version 2.0 and supports High-Capacity SD Memory 
Cards
– SDIO Card Specification version 2.0
„Supports
1, 4, or 8 bit MMC modes and 1bit or 4 bit SD and SDIO modes
– Card bus clock frequency up to 52 MHz
– Up to 832 Mbps of data transfer for MMC cards in 8-bit Dual Data Rate mode
– Up to 416 Mbps of data transfer for MMC cards in 8-bit Single Data Rate mode
– Up to 200 Mbps of data transfer for SD/SDIO cards in 4-bit mode
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„Supports
Single Block, Multi Block read and write
„Supports
block sizes of 1 ~ 4096 bytes
„Supports
the write protection switch for write operations
„Supports
both synchronous and asynchronous abort
„Supports
pause during the data transfer at block gap
„Supports
SDIO read wait and suspend resume operations
„Supports
auto CMD12 for multi-block transfer
„Host
can initiate non-data transfer command while data transfer is in progress
„Allows
cards to interrupt the host in 1-bit and 4-bit SDIO modes
„Embodies
a fully configurable 128x32-bit FIFO for read/write data
„Supports
internal and external DMA capabilities
„Supports
advanced DMA to perform linked memory access
PWM
The ConnectCore for i.MX53 module provides four PWM interfaces. Two of these PWM
interfaces are available on the i.MX53 CPU and the other two PWM interfaces are provided
by the DA9053 PMIC.
C o n n e c t C o r e fo r i . M X5 3 PW M
The two PWM interfaces of the i.MX53 have a 16-bit counter, and are optimized to generate
sound from stored sample audio images and they can also generate tones.
Main features of these PWM interfaces:
„16-bit
„4
up-counter with clock source selection
× 16 FIFO to minimize interrupt overhead
„12-bit
prescaler for division of clock
„Sound
and melody generation
„Active
high or active low configured output
„Can
be programmed to be active in low power and debug modes
„Interrupts
at compare and rollover
D A 90 5 3 P W M
The DA9053 PMIC has two GPIO signals including PWM control. The generated PWM signals
have a frequency of 21 kHz. The duty cycle can be controlled with 95 steps (using a 2MHz
clock for each step).
The PWM signals can be configured to use an internal 100Kohm pull-up to +3.3V, or an
external pull-up.
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ȹȹ
RTC
The ConnectCore for i.MX53 provides a Real Time Clock and a Secure Real Time clock.
The real time clock function is provided including time and day counters as well as an alarm
function. The RTC utilizes a 32.768 KHz crystal oscillator for the time base and is powered by
the coin cell backup supply when main supply has dropped below operational range. The
accuracy of the 32.768 KHz crystal used for the Real-Time Clock is Âą20ppm.
„RTC
accuracy Âą20ppm
„6-bit
year counter. Year 0 corresponds to 2000.
„Alarm
registers containing min, hrs, day, month, and year.
The secure real time clock helps to comply with issues arising out of different applications
requiring secure and certifiable time, for example Digital Rights Management (DRM)
schemes.
Main features of the secure RTC interface are the following:
„Secure
47-bit time counter
„Non-secure
„Use-mode
47-bit time counter
protection. The SRTC cannot be configured by non-secured SW.
„Re-programming
protection. The SRTC cannot be altered or disabled after SRTC
locked.
„Clock
source protection
„Programmable
secure and non-secure alarms with interrupt
Known Iss ue wi th the R TC
Symptom:
Loss of Time and Date from the RTC registers.
Occurrence:
When the VCHRG power supply is used, the VLIO power supply is disconnected, a coin-cell is
connected to VBBAT and the temperature is below +40 Celsius. At the time when VCHRG is
disconnected, the PMIC should cause the power to switch over from VCHRG (charger power
input) to VBBAT (the coin-cell power input). However, there is a fault which results in the
registers being reset. At +20 Celsius and below, this happens every time the power 
change-over takes place. At temperatures between +20 and +40 Celsius the fault may occur.
For temperatures over +40 Celsius the switch-over works satisfactorily.
ĂŤ
ĂŹ
Ă­
ĂŽ
There may be some variation in the temperature trip points.
ĂŻ
Possible Workarounds:
1. Use the VLIO and VBBAT inputs only, leave VCHRG disconnected.
2. Use VLIO, VBBAT and VCHRG.
3. Use an RTC on the board that hosts this module.
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ȹȹ
SATA
The integrated Serial Advanced Technology Attachment (SATA) Controller is compatible with
the Advanced Host Controller Interface (AHCI) specification. The SATA Controller along with
integrated physical link hardware (SATA PHY) provides one SATA port for the attachment of
external SATA compliant storage devices.
The ConnectCore for i.MX53 module provides connection to the SATA port on system module
connectors (J1 and J2).
The SATA port provides the following features:
„Compliant
with Serial ATA Specification 2.6, and AHCI Revision 1.3 specifications
(except FIS-based switching) at 1.5 Gb/s port speed
„Rx
Data Buffer for recovered clock systems
„Data
alignment circuitry
„OOB
signaling detection and generation
„Asynchronous
„Digitally
„8b/10b
Signal Recovery, including retry polling
supports device hot-plugging
encoding/decoding
„Supports
power management features including automatic partial to slumber
transition
„Supports
BIST loopback data checking on a per FIS basis
„Supports
one SATA device (Port 0)
„AMBA
AHB interface (one master and one slave)
„Internal
DMA engine for reading command lists and transferring data
„Supports
hardware-assisted native command queuing for up to 32 entries
„Supports
port multiplier with command-based switching
„Activity
LED support
„Supports
disabling Rx and Tx data clocks during power down modes
„Supports
eSATA (when external analog logic also supports eSATA)
SPDIF
The ConnectCore for i.MX53 provides a Sony/Philips Digital Interface Transmitter (SPDIF Tx)
audio module enabling the processor to transmit stereo digital audio. The SPDIF transceiver
allows handling of both SPDIF channel status (CS) and User (U), data including a frequency
measurement for the precise measurement of an incoming sampling frequency.
As the SPDIF internal data width is 24-bit, the eight most-significant bits of all registers
return zeros.
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ȹȹ
The SPDIF is composed of two parts: SPDIF Receiver and SPDIF Transmitter. The SPDIF
receiver extracts the audio data from each SPDIF frame and places the data in the SPDIF Rx
left and right FIFOs. The Channel Status and User Bits are also extracted from each frame
and placed in the corresponding registers. The SPDIF receiver also provides a bypass option
for direct transfer of the SPDIF input signal to the SPDIF transmitter.
For the SPDIF transmitter, the audio data is provided by the processor. The Channel Status
bits are also provided via the corresponding registers. The SPDIF transmitter generates a
SPDIF output bitstream in the biphase mark format (IEC60958), which consists of audio data,
channel status and user bits.
In the SPDIF transmitter, the IEC60958 biphase bit stream is generated on both edges of the
SPDIF Transmit clock. The SPDIF Transmit clock is generated by the SPDIF internal clock
generate block and the sources are from outside of the SPDIF block. For the SPDIF receiver, it
can recover the SPDIF Rx clock. Both the Rx clock and Tx clock are be sent to the ASRC.
Synchronous Serial Interface (SSI)
The ConnectCore for i.MX53 module provides up to three synchronous serial interfaces (SSI).
The SSI is a full-duplex serial port that allows communication with external audio devices
using a variety of serial protocols (SSI normal, SSI network, I2S and AC-97), bit depths and
clock/frame sync options.
SSI is typically used to transfer samples in a periodic manner. The SSI consists of independent
transmitter and receiver sections with independent clock generation and frame
synchronization.
Main features of the SSI interface:
„Independent
(asynchronous) or shared (synchronous) transmit and receive sections
operating in Master or Slave mode
„Normal
mode operation using frame sync
„Network
mode operation allowing multiple devices to share the port with as many as
32 time slots
„Two
sets of four 15 x 32 bits Transmit and Receive FIFOs
„Programmable
data interface mode such like I2S, LSB, MSB aligned
„Programmable
word length 8, 10, 12, 16, 18, 20, 22 or 24 bits
„Program
options for frame sync and clock generation
„Programmable
„AC97
I2S modes (Master, Slave or Normal)
support
„Completely
separate clock and frame sync selections for the receive and transmit
sections
„External
„SSI
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network clock input for use in I2S Master mode
power-down
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ȹȹ
Television Encoder (TVE)
The Television Encoder (TVE) provides a direct connection between the ConnectCore for
i.MX53 and a TV set via analog interface. The TV Encoder supports Standard Definition (SD)
and High Definition (HD) television standards.
The TVE can operate in two modes:
„Encoding
the video data according to the selected TV standard
„Generating
RGB analog signals according to the VGA specification
Key features of the TVE in TV encoding mode:
„SD
mode features
– Supported TV standards: NTSC, 480i, 576i and PAL B,D,G,H, I/M/N
– Supported output formats: CVBS, S-Video (Y/C), YPrPb and RGB
– Wide-Screen Signaling (WSS) support
– MacrovisionTM 7.1 copy protection
– Output oversampling up to x16 for elimination of external analog filters
„HD
mode features
– Supported TV standards: 720p@60Hz, 720p@50Hz, 720p@30Hz, 720p@25Hz,
1080i@60Hz, 1080i@50Hz, 1035i@60Hz, 1080p@30Hz, 1080p@50Hz, 1080p@60Hz
– Supported output formats: YPrPb and RGB
– Output oversampling up to x4 for elimination of external analog filters
„Common
SD/HD mode features
– Flexible timing and gain control mechanism allowing non-standard parameters
– Programmable Chroma digital filters
– Programmable adaptive Luma digital filters
– Programmable YCrCb to RGB color matrix
– Output resolution - 10 bits
UART
The ConnectCore for i.MX53 module provides up to five UART ports. UART 1 is a full-modem
UART port with all handshake signals available. The other UART ports are 4-wire UART ports
with data lines RXD/TXD and the handshake lines RTS#/CTS#.
The UART ports supports NRZ encoding and IrDA-compatible infrared slow data rate (SIR)
format.
Main features of these UART ports:
„High-speed
„Serial
„7
Čą
Čą
Čą
TIA/EIA-232-F compatible, up to 4.0 Mbit/s
IR interface low-speed, IrDA-compatible (up to 115.2 Kbit/s)
or 8 data bits
Čą
ȹȹȹȹȹ

Čą
Čą
„1
Čą
Čą
ȹȹ
or 2 stop bits
„Programmable
parity (even, odd, and no parity)
„Hardware
flow control support for request to send (RTS#) and clear to send (CTS#)
signals (signal direction according to DCE mode).
„Maskable
„Two
Interrupts
DMA Requests (TxFIFO FMA Request and RxFIFO DMA Request)
„Escape
„Voting
character sequence detection
logic for improved noise immunity (16x oversampling)
„DCE/DTE
„Auto
capability
baud rate detection (up to 115.2 Kbps)
„Programmable
„Two
baud rate (up to 4Mbps)
independent 32-byte FIFOs for receive and transmit
„Receiver,
transmitter and UART internal clocks enable/disable for power saving
USB Host and USB OTG
The ConnectCore for i.MX53 provides three USB 2.0 high speed Host controllers and one USB
2.0 On-The-Go (OTG) high speed controller. These interfaces conform to the USB 2.0
specification, the OTG supplement.
Each controller can support ULPI, Serial, UTMI, IC-USB or HSIC interfaces according to its
feature. All four controllers are single-port. For the OTG, there is only one port. It is used as
both a downstream and upstream port. For the Host-only core, there is also one port which is
used as a downstream port.
Key USB features:
„High-speed/full-speed/low-speed
host only (Host1)
–
HS/FS/LS UTMI compliant interface
–
HS USB PHY included
„High-speed/full-speed/low-speed
host only (Host2)
– HS/FS/LS ULPI compliant interface
– Software configurable for full speed/low speed interface for Serial transceiver
– Full Speed Inter-Chip USB compliant interface (IC-USB)
„High-speed/full-speed/low-speed
host only (Host3)
– HS/FS/LS ULPI compliant interface
– Software configurable for full speed/low speed interface for Serial transceiver
„High-speed/full-speed/low-speed
OTG
– HS/FS/LS UTMI compliant interface
– HS USB PHY included
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ȹȹȹȹȹ

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– High Speed, Full Speed and Low Speed operation in Host mode (with UTMI transceiver)
– High Speed, and Full Speed operation in Peripheral mode (with UTMI transceiver)
– Hardware support for OTG signaling, session request protocol, and host negotiation
protocol
– Up to 8 bidirectional endpoints
„Low-power
mode with local and remote wake-up capability
„Serial
PHY interfaces configurable for bidirectional/unidirectional and differential/
single ended
„Embedded
Čą
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DMA controller
ȹȹȹȹȹ

Čą
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ȹȹ
Video Processing Unit (VPU)
The video processing unit is a multi-standard video processing codec capable of handling
multiple streams simultaneously through time multiplexing. This VPU covers many standards
and high definition video decoders and decoders as a multi-standard video codec engine, as
well as several important video processes such as rotation, mirroring and deringing.
The VPU has its own DMA driven AXI masters that allow it to retrieve data directly from
system memory (DDR and iRAM).
The following table lists the VPU’s encoding/decoding capabilities:
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Watchdog Timer
The Watchdog Timer (WDOG-1) protects against system failures by providing a method of
recovering from unexpected events or programming errors. Once the watchdog is activated,
it must be serviced by software on a periodic basis. If servicing does not take place, the
watchdog asserts the internal system reset signal after the corresponding timeout occurs.
The Watchdog Timer features are as follows:
„A
time-out counter with time-out periods from 0.5 to 128 seconds
„Time
resolution of 0.5 seconds
„Configurable
time-out counter that can be programmed to run or stop during low
power and debug modes
„Programmable
Čą
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Čą
interrupt generation prior to time-out
ȹȹȹȹȹ

Čą
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ȹȹ
„Programmable
time duration between interrupt and timeout events, from 0 to 128
seconds in steps of 0.5 seconds
„Power
down counter with fixed time-out period of 16 seconds
WLAN
WLAN
In addition to the on-module Ethernet interface, the ConnectCore for i.MX53 module can also
provide an optional dual-diversity 802.11a/b/g/n WLAN interface with data rates up to 54
Mbps 802.11a/b/g mode and up to 65 Mbps in 802.11n mode.
Two U.FL antenna connectors are provided on the module.
Primary
Secondary
On the ConnectCore for i.MX53 module variant, attach the antennas with the U.FL-RP-SMA
female cable to the primary connector and secondary connector on the module.
ĂŤ
When disconnecting U.FL connectors, the use of a U.FL plug extraction tool (Hirose P/
N U.FL-LP-N-2 or U.FL-LP(V)-N-2) is strongly recommended to avoid damage to the U.FL
connectors on the module.
ĂŹ
Ă­
ĂŽ
ĂŻ
To mate U.FL connectors, the mating axes of both connectors must be aligned. The "click"
will confirm mated connection. Do not attempt insertion at an extreme angle.
Čą
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ȹȹȹȹȹ

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ȹȹ
Cable Specification: U.FL/W.FL to RP-SMA
Attributes
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ĂŤ
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ĂŽ
Dimensions are provided for reference purposes only. The actual antenna might vary.
ĂŻ
1 = U.FL
2 = RP-SMA
ĂŤ
Čą
Čą
Čą
This module obtained its complete certification by using the cable described here. End
users in North America should use a cable that matches these specifications to maintain the
module’s certification.
ĂŹ
Ă­
ĂŽ
ĂŻ
Čą
ȹȹȹȹȹ

Čą
Čą
Čą
Čą
ȹȹ
Antenna Specification: RP-SMA
Attributes
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This module obtained its complete certification by using the antenna described here.
End users in North America should use an antenna that matches these specifications to
maintain the module's certification. Antennas of the same type but operating with a lower
gain may be used.
ĂŹ
Ă­
ĂŽ
ĂŻ
SAR Requirements
This module and its associated antennas should be installed at a distance of at least 20cm
from personnel.
Labelling Requirements
Products in which this module is fitted must be labelled with the following text
"contains FCC ID: MCQ-50M1699".
Čą
Čą
Čą
Čą
ȹȹȹȹȹ
About the Development Board
Ăś
he development board supports the ConnectCore for i.MX53 module. This chapter
describes the interfaces of the development board and explains how to configure the board
for your requirements.
The development board has two 180-pin connectors that mate with the module connectors.
What’s on the Development Board?
„Flexible
9-30VDC charger power supply with power-on switch
„Screw-flange
„3V
Battery header with enable jumper
coin cell battery
„+3.3V
selection jumper. The +3.3V supply can be selected from the module or from
the development board.
„Connectors
„1
x UART RS232 with status LEDs and SUB-D 9-pin connector
„1
x UART MEI (RS232/RS4xx) with status LEDs and SUB-D 9-pin connector
„1
x UART with TTL levels
„1
x CAN bus with termination resistor selection and SUB-D 9-pin connector
„1
x CAN bus with termination resistor selection and pin header
„1
x USB OTG connector
„4
x USB Host connectors
„1
x SD/MMC card holder
„1
x MicroSD card holder
„1
x SATA connector
and I2C headers
„SPI
„PWM
header
„Audio
„VGA
Čą
Čą
Čą
for Digi 802.3af PoE Application board (sold separately)
Čą
interface with Line-out, Line-In and Mic-In jacks
interface
ȹȹȹȹȹ

Čą
Čą
Čą
„HDMI
„2
Ethernet connector
I/O header
socket with Association LED and Ident Button (XBee module sold separately)
„1-Wire
interface with 2-pin header
„1-Wire
EEPROM
„1-Wire
iButton retainer
„Peripheral
„Keypad
„JTAG
Čą
Čą
for a Digi 100M_ETHADPT (sold separately)
x RP-SMA WLAN antenna connectors
„XBee
ȹȹ
Screen selection circuit
„Digital
LCD connector with Touch Screen interface
„Connector
x Camera connectors
„RJ-45
Čą
LCD connector with Touch Screen interface
„Touch
„2
Čą
interface
„Parallel
„LVDS
application header
header
interface
„2
x User LEDs (green)
„2
x User Push-buttons
„Boot
mode switch
„Boot
device switch
„1
x Power Push-button
„1
x Reset Push-button
Čą
ȹȹȹ

Čą
Čą
Čą
Čą
ȹȹ
The Development Board
R2
C176
C175
C174
C154
Čą
Čą
R84
R222
C150
U28
U29
L4
C70
C71
C24
C66
C62
R268
TP45
L9
C106
R270
TP61
TP46
TP43
TP42
TP114
R103
TP113
R110
TP63
R111
TP69
TP60
TP118
TP64
TP117
ETHERNET 1
R93
R30
+ C109
C13
C10
C11
L18
TP25
R46
R203
R204
TP29
TP26
POS 2
R205
TP30
TP31
TP28
TP33
OPEN
OPEN
DESCRIPTION
INT. BOOT
BOOT - uSD
OPEN
CLOSE
RESERVED
CLOSE
BOOT - SD
CLOSE
CLOSE
CLOSE
BOOT - SATA
CLOSE
OPEN
BOOT - FUSES
SER DOWNLOAD
CAN2
R140
C178
U34
J27
CLOSE
R83
OPEN
POS 1
TP27
TP92
TP58
TP36
TP35
TP91
TP57
TP62
TP82
TP87
TP89
TP88
TP90
TP68
TP86
TP37
TP38
DESCRIPTION
BOOT - FLASH
CLOSE
OPEN
OPEN
U32
C116
POS 2
OPEN
S9
X31
R87
R44
S8
POS 1
TP51
TP52
TP49
R255
TP47
R265
TP48
R25
U30
C54
L5
L20
H9
R47
R293
R264
R263
R262
R261
R260
R259
R258
R257
R256
R292
R49
CAMERA 1
C120
C119
BOOT CONF
J9
JP5
ETHERNET 2 J7
C123
C124
JP4
CAN1
CAN1 TERMINATION
S8
ON
ON
12
12
S9
JP12
U8
J17
U33
C118
R104
R100
ON=
WLAN DISABLE
U13
C121
C122
P15
R32
LE12
P13
PERIPHERAL CONNECTOR
WLAN SECONDARY
R209
C117
P21
R45
X15
C171
C18
R211
X18
X16
C132
U44
C170
R162
C168
J8
L6
C179
R246
R5
R61
R90
R63
R62
C12
L19
R206
CAN2 TERMINATION
IDENT
LBL1
R13
L22
C17
R151
R152
C99
C98
R141
R121
R66
R65
R92
R79
R247
S5
L8
+ C111
C115
C114
R27
R17
R218
R207
R35
X21
R96
USER
L7
C89
R154
R153
S3
L10
L21
C112
C64
R201
R202
R253
R197
C110
C113
C65
C125
C5
C100
U4
L24
L25
R37
U41
J11
J10
L26
R29
C102
R16
C2
C1
R215
R214
R173
U56
C194
C126
R208
CAMERA 2
R213
LE49
LE51
Čą
C61
R112
R113
R116
R119
R99
TP115
R274
TP66
TP65
TP23
TP70
R282
R281
R284
R283
TP71
R128
Y1
C192
J1
X29
MICRO SD
X14
R57
C84
J20
C161
C155
C159
C162
TP74
TP72
TP73
TP75
TP76
R229
U38
R135
C9 R122
C196
C197
JP3
ON=AUTOBOOT
R195
C55
R8
S10
LED 2
BUTTON 1
R183
R36
U42
C94
XBEE MODULE
R101
C69
R271
C107
C131
RESET
U54
C72
ASSOC
R59
R102
R192
U53
R78
R6
R76
R64
R91
C158
R188
C169
R28
C43
R216
R10
DIGI
INTERNATIONAL
R174
L3
R69
R60
C172
R31
C45
R33
C48
R172
L12
UART3 (TTL)
R199
C128 C129
R176
LINE OUT
R181
R189
LINE IN
C189
U52
TP41 TP39
LE50
LED 1
C15
C19
R127
C130
MICRO
U27
U7
R12
S12
Čą
U39
J24
POWER
R52
C127
J15
R136
U51
C187
C190
U55
U23
C186
R120
U47
C167
S13
X7
USB OTG
USB HOST
C108
R187
J6
C49
C195
U25
R196
U19
U36
R131
R51
J12
U1
U5
V10
C52
C22
L16
R85
R38
U43
R171
C188
C191
C193
O2
R193
U37
R132
O1
V11
C38
C57
C28
C27
C50
U18
U26
U20
U48
C8
U3
R198
U12
R117
R118
U16
U22
C56
CONNECTCORE i.MX53 MODULE
C134
U40
DISABLED
C59
C68
ACTIVE
C95
C67
TERMINATION
C4
C58
R254
U35
R217
R220
U31
DISABLED
4-WIRE
U14
ACTIVE
2-WIRE
C101
AUTO PWR DWN
RS485 MODE
C53
1-WIRE
Y3
R42
C86
R20
U10
R269
R273
R266
X28
C149
C14
R105
SATA
C63
U49
L27
RS422/485
R221
RS232
R191
C46
C147
C3
R39
TP137
TP44
R279
R288
R278
R287
R277
OFF/OPEN
MODE
R190
C41
AUDIO
J18
C40
TP81 TP80 TP78 TP79 TP24
R276
R133
LE48
C148
R54
R285
JP1
ON/CLOSE
R134
R75
LE62
1234
U17
C26
TP85 TP84 TP83
TP67 TP116
KEYPAD
R291
LE47
J5
C16
C83
H3
ON
X19
C20
C145
R34
POS DESCRIPTION
RXD
LE63
C33
U11
C42
C34
J2
R286
R53
C88
R108
P2
X20
R272
DIGITAL I/O
R82
R129
R125
R124
TXD
C39
JP10
U6
C93
R107
RN2
S6
U24
X30
J3
R275
H1
R74
LE61
U9
X30
C36
C32
C96
LE44
R73
LE60
R23
S7
R72
LE59
LE43
LE46
R77
C97
C87
R88
X45
ON=ENABLE
COIN CELL
LE45
R43
L29
C21
JTAG
R280
R290
R56
R71
U21
C37
C31
C51
PWM
P19
POE MODULE
POE MODULE
R89
U50
R142
X13
C82
12
UART2 STATUS
R41
I2C
P20
C81
R138
P14
TOUCH SELECTION
P23
C85
L17
R289
ON
SPI
D1
Q2
R143
R97
TXD
RXD
P22
R106
LE40
LE58
R3
R86
LE42
X27
R1
BATT
R4
R123
R55
LE41
LE57
R114
C30
X27
C29 C35
R109
TP77
C133
R137
R126
UART1 STATUS
UART1 (CONSOLE)
C60
L1
R58
P24
R231
C79
U2
R7
R139
D5
D6
C135
R9
R70
R40
J13
J23
C90
C80
C163
C151
R67
R24
C166
J4
JP2
+3.3V_MOD
U61
L11
R48
R21
C78
R18
JP6
C23
R68
L23
C165
ON=SJC-ONLY
JP20
P12
TP20
TP93
R158
C25
R159
R50
ON=
ENABLE EXT BATT
+3.3V_JS
UART2 (MEI)
C44
R130
EXT BATT
P29
U15
C47
C105
C157 R177
TP22
TP21
R179
R178
U45
U57
R81
R80
R185
R186
VGA
C6
C7
R26
C164
R15
U58
U46
R22
WLAN PRIMARY
P1
PARALLEL LCD
R182 C153
R14
R19
V2
R180 C152
R11
L30
C156
SD/MMC
C104
P4
TP19
C160
L28
C103
LVDS
LCD
R184
R175
R227
R228
R194
R98
X32
X24
9V-30VDC
R230
V6
V5
MAIN POWER
LE6
OFF
LE7
ON
R95
LE4
LE8
R94
S2
J19
R232 C177
S2
C91
+5V
+3.3V
HDMI
VCHRG VBATT
POWER
BUTTON 2
ȹȹȹ
á
ø
Ăš
Ăš
Ăş
Ăť
Ăź
á
ø
Ă˝
Čą
Ăž
Ăş
ø
Čą
Ă˝
Čą
Ăż
Ă˝
Ă˝
Čą
Ăş
Ăž
Ăş
Ăş
Ă˝
Ăş
Ăš
Ăť
ȹȹ
Ăş
Switches and Push-buttons
Power Switch, S2
R84
R222
C150
U28
U29
J20
C161
C155
C151
C164
C70
C71
C24
C66
C62
R268
TP45
L9
C106
R270
TP61
TP46
TP43
TP42
TP114
R103
TP113
R110
TP63
R111
TP69
TP118
TP64
TP117
TP60
R99
TP23
TP70
TP71
TP72
TP115
R274
TP65
TP66
C61
R112
R113
R116
R119
L4
R88
TP74
R93
R30
C115
R29
C10
C11
R46
R140
C178
U34
DESCRIPTION
INT. BOOT
OPEN
OPEN
BOOT - uSD
OPEN
CLOSE
BOOT - SD
CLOSE
OPEN
BOOT - FUSES
CLOSE
CLOSE
BOOT - SATA
CLOSE
CLOSE
SER DOWNLOAD
X31
R87
CAN2
R83
RESERVED
C179
C119
BOOT CONF
J9
ETHERNET 2 J7
C123
JP4
CAN1
CAN1 TERMINATION
ON
ON
S9
JP12
12
C117
C118
R104
U13
12
R100
ON=
WLAN DISABLE
J17
U33
C121
C122
P15
R32
C171
S8
U8
P21
U44
JP5
C124
C170
R246
R5
R61
R90
R49
CAMERA 1
C120
R211
X18
X15
SD/MMC
IDENT
C18
R45
CAN2 TERMINATION
X16
C132
LE12
P13
PERIPHERAL CONNECTOR
WLAN SECONDARY
R209
C17
R151
R152
L18
J27
C131
User
Button 1,
S3
L8
R17
C112
S9
R203
R204
TP29
POS 2
R205
TP25
TP30
TP31
TP28
TP33
POS 1
TP26
DESCRIPTION
BOOT - FLASH
TP27
TP92
TP58
TP36
TP35
TP91
TP57
TP82
TP87
TP89
TP88
TP68
TP86
TP90
TP37
TP38
TP49
TP52
POS 2
OPEN
CLOSE
OPEN
OPEN
C116
TP62
R293
OPEN
LBL1
R13
C13
C114
R27
C113
C65
C64
R206
CLOSE
U32
R141
R121
R66
R65
R92
R79
R247
S5
S8
POS 1
C89
R154
USER
R255
TP47
R265
TP48
R25
C54
R44
U30
CAMERA 2
R63
R62
LE49
X14
L5
L20
H9
X21
R96
R135
LE51
R153
C84
S3
C99
C98
MICRO SD
R57
R59
J8
L6
R47
S10
ASSOC
C12
L19
XBEE MODULE
LED 2
L7
L22
L21
R218
R207
J1
X29
L10
+ C109
C102
C5
C100
C110
R35
R208
L24
L25
R37
U41
C125
C126
U4
J11
J10
+ C111
C68
U40
R269
R273
R266
Y1
R201
R202
R253
R197
C194
R16
C2
C55
R8
C1
R215
R214
R173
R193 R196
C94
U55
C192
R198
R190
R229
R128
R183
C187
C190
R36
U42
R271
C107
R213
C19
C9 R122
C196
C197
JP3
ON=AUTOBOOT
R195
ETHERNET 1
L26
R38
U43
C69
U56
C72
LE50
LED 1
R101 R102
Reset
Button,
S12
U54
R78
R6
R76
R64
R91
R216
R10
C158
R188
R172
Power
Button, S13
R192
U53
R264
R263
R262
R261
R260
R259
R258
R257
R256
R292
L12
R162
C168
R28
C43
L3
R174
C169
R33
C48
U27
BUTTON 1
RESET
C189
U52
TP41 TP39
U47
U7
R12
S12
U23
R136
U51
R191
R134
U19
U37
U38
C38
R131
C195
U25
C186
R120
DIGI
INTERNATIONAL
R69
R60
C172
R51
C130
MICRO
R52
C127 C15
J15
U39
R127
POWER
U1
U5
V10
C188
C191
C193
O2
U36
U12
C57
O1
C52
X28
C167
S13
X7
USB OTG
USB HOST
C108
R187
J6
C134
R171
V11
U18
U26
C28
C27
C50
C22
L16
C8
C49
C59
U3
R132
C53
R42
J12
C58
R254
C46
J24
Y3
TP73
TP75
R217
R220
CONNECTCORE i.MX53 MODULE
C67
DISABLED
U35
DISABLED
4-WIRE
ACTIVE
C95
U31
ACTIVE
2-WIRE
TERMINATION
C4
U14
AUTO PWR DWN
RS485 MODE
1-WIRE
C14
R85
U10
C101
U20
U48
R31
C45
LINE IN
R39
C86
R20
C63
U49
L27
RS422/485
S6
R117
R118
OFF/OPEN
RS232
1234
C41
U22
C56
ON/CLOSE
R221
MODE
R133
LE48
U16
UART3 (TTL)
R199
C128 C129
R176
LINE OUT
R181
R189
C3
R285
JP1
R23
LE47
C147
C149
TP44
R279
R288
R278
R287
R277
R74
ON
AUDIO
J18
C40
TP137
R276
R105
SATA
H3
POS DESCRIPTION
RXD
C148
R54
TP81 TP80 TP78 TP79 TP24
KEYPAD
R34
J5
C16
C88
C145
C83
R291
X19
C20
TP67 TP116
R82
R129
R125
R124
R73
TXD
R75
LE62
C26
TP85 TP84 TP83
R286
R53
C87
R108
P2
X20
R272
DIGITAL I/O
J2
R275
H1
U17
JP10
U6
C93
R107
RN2
LE63
U11
U24
X30
C96
LE44
C39
C42
C34
C33
C36
J3
R280
R290
R56
S7
R72
LE59
LE60
LE61
U9
X30
R77
R89
X45
LE43
LE46
C32
P19
POE MODULE
POE MODULE
JTAG
ON=ENABLE
COIN CELL
LE45
R43
L29
C21
X13
C82
C97
C85
R231
Q2
R138
12
R71
U21
C37
C31
C51
PWM
R106
R289
ON
I2C
P20
TP76
RXD
SPI
L17
C81
R137
R142
U50
R143
R97
TXD
UART2 STATUS
R41
R3
P14
TOUCH SELECTION
P23
P22
P24
D1
LE42
X27
R1
R86
LE40
LE58
R109
BATT
R4
R123
R55
LE41
LE57
R114
C30
X27
C35
R58
R48
R2
C176
C175
C174
C154
L1
C133
C90
C80
C79
C135
R126
UART1 STATUS
C29
C60
R139
D6
D5
U2
R7
UART1 (CONSOLE)
R158
C25
R21
R67
C78
R24
R9
R70
R40
J13
J23
C163
J4
JP2
+3.3V_MOD
WLAN PRIMARY
P1
P12
U61
L11
C166
ON=SJC-ONLY
JP20
R18
TP93
C165
C23
R68
L23
JP6
UART2 (MEI)
R159
R50
ON=
ENABLE EXT BATT
C105
C159
U45
U57
C44
+3.3V_JS
R130
EXT BATT
C162
R26
U58
P29
U15
C47
U46
R22
V2
L30
C156
R177
C157
TP22
TP21
R179
TP20
R178
UART 2
Switch, S6
R81
R80
R185
R186
VGA
C6
C7
PARALLEL LCD
R182 C153
R19
R15
R282
R281
R284
R283
C104
R14
TP77
X24
R11
R180 C152
X32
P4
TP19
C160
L28
C103
LVDS
LCD
R184
R175
R227
R98
TP51
V5
MAIN POWER
J19
LE6
R228
V6
LE7
R194
R230
OFF
R95
LE4
ON
9V-30VDC
LE8
R94
R232 C177
S2
S2
C91
+5V
+3.3V
HDMI
VCHRG VBATT
POWER
UART 1
Switch, S7
BUTTON 2
User
Button 2,
S5
Ident
Button,
S10
Boot Device
Switch, S8
Boot Mode
Switch, S9
Power Switch, S2
The development board has an ON/OFF switch, S2. The power switch S2 can switch both 
9V-30VDC input power supply and 12VDC coming out of the optional PoE module 
(Digi P/N DG-ACC-POE). However, if a power plug is present on the DC power jack, PoE is
disabled.
Čą
Čą
Čą
Ăš
Ăź
Ăş
Ă˝
Ăš
Ăź
ø
Ăš
Ăż
Ăż
Čą
Ăż
Ăš
Ăť
ȹȹȹ
á
ø
Ăš
Ăš
Ăş
Ăť
Ăź
á
ø
Ă˝
Čą
Ăž
Ăş
ø
Čą
Ă˝
Čą
Ăż
Ă˝
Ă˝
Ăş
Čą
Ăş
Ăž
Ăş
Ă˝
Ăş
Ăš
Ăť
Ăş
ȹȹ
Reset Button, S12
The reset push-button S12, resets the module and the peripherals on the development board.
A push-button allows manual reset by connecting POR# or optionally RSTIN# to ground.
Power Button, S13
The power button S12 generates a power event for the i.MX53 and the DA9053 PMIC.
When the module is in Off mode, a Power event will power on the module.
When the module is in On mode, a long press (>2sec) of the power button will turn off the
module.
When the module is in On mode, a short press of the power button will put the module in
suspend mode (low power).
When the module is in Suspend mode, a short press of the power button will resume the
module.
User Buttons, S3 and S5
Use the user push-buttons to interact with the applications running on the ConnectCore for
i.MX53 module. Use these module signals to implement the push-buttons:
Ident Button, S10
The Ident push-button S10 is associated to the commissioning input of the Digi XBee modules.
This input provides a variety of simple functions to aid in deploying devices in a network. For
a deeply description of this functionality please refer to the Digi XBee modules
documentation.
Legend for Multi-Position Switches
Switches S6, S7, S8 and S9 are multi-pin switches. In the description tables for these
switches, the position is designated as S[switch number].[pin number]. For example, position
1 on switch S6 is specified as S6.1.
Čą
Čą
Čą
Ăš
Ăź
Ăş
Ă˝
Ăš
Ăź
ø
Ăš
Ăż
Ăż
Čą
Ăż
Ăš
Ăť
ȹȹȹ
á
ø
Ăš
Ăš
Ăş
Ăť
Ăź
á
ø
Ă˝
Čą
Ăž
Ăş
ø
Čą
Ă˝
Čą
Ăż
Ă˝
Ă˝
Čą
Ăş
Ăž
Ăş
Ăş
Ă˝
Ăş
Ăš
Ăť
ȹȹ
Ăş
UART 1 Switch, S7
Use S7 to configure the line interface for serial port 1 (console):
UART 2 Switch, S6
Use S6 to configure the line interface for serial port 2 MEI:
Čą
Čą
Čą
Ăš
Ăź
Ăş
Ă˝
Ăš
Ăź
ø
Ăš
Ăż
Ăż
Čą
Ăż
Ăš
Ăť
ȹȹȹ
á
ø
Ăš
Ăš
Ăş
Ăť
Ăź
á
ø
Ă˝
Čą
Ăž
Ăş
ø
Čą
Ă˝
Čą
Ăż
Ă˝
Ă˝
Čą
Ăş
Ăş
Ăž
Ăş
Ă˝
Ăş
Ăš
Ăť
Ăş
ȹȹ
Boot Device Switch, S8
Use S8 to configure the source of the boot code when S9 is configured in internal boot mode.
Boot Mode Switch, S9
Use S9 to configure the module boot mode:
Čą
Čą
Čą
Ăš
Ăź
Ăş
Ă˝
Ăż
Ăš
Ăź
ø
Ăš
Ăż
Čą
Ăż
Ăš
Ăť
ȹȹȹ
á
ø
Ăš
Ăš
Ăş
Ăť
Ăź
á
ø
Ă˝
Čą
Ăž
Ăş
ø
Čą
Ă˝
Čą
Ăż
Ă˝
Ă˝
Čą
Ăş
Ăž
Ăş
Ăş
Ă˝
Ăş
Ăš
Ăť
ȹȹ
Ăş
Jumpers
Touch
Selection,
J20
+3.3V Source, P29
JTAG Mod, J4
C176
C175
C174
C154
R84
R222
C150
U28
U29
J20
C161
C155
C151
C164
C91
C70
C71
C24
C66
C62
R268
TP45
L9
C106
R270
TP61
TP46
TP43
TP42
TP114
R103
TP113
R110
TP63
R111
TP69
TP118
TP64
TP60
R99
TP117
TP66
R274
TP115
TP23
TP70
R282
R281
R284
R283
ETHERNET 1
C61
R112
R113
R116
R119
L4
R88
TP74
TP71
TP72
TP75
R93
R30
C115
R29
R17
C112
C13
R46
R203
R204
TP29
R205
TP25
TP30
TP28
TP33
TP31
TP26
RESERVED
CLOSE
BOOT - SD
CLOSE
OPEN
BOOT - FUSES
CLOSE
CLOSE
BOOT - SATA
CLOSE
CLOSE
SER DOWNLOAD
R83
DESCRIPTION
INT. BOOT
CLOSE
X31
R87
OPEN
OPEN
CAN2
R140
J27
OPEN
BOOT - uSD
TP51
POS 2
S9
DESCRIPTION
BOOT - FLASH
C179
R78
R6
R76
R64
R91
C120
C119
BOOT CONF
J9
ETHERNET 2 J7
C123
C124
JP4
CAN1
CAN1 TERMINATION
S8
ON
ON
S9
JP12
U8
C118
R104
U13
12
R100
ON=
WLAN DISABLE
J17
U33
12
C117
P21
U44
JP5
C121
C122
P15
R32
C171
C132
C18
R49
CAMERA 1
R45
X15
R211
X18
X16
C170
R246
R5
R61
R90
R63
R62
TP27
TP92
TP58
TP36
TP35
TP91
TP57
TP82
TP87
TP89
TP88
TP90
TP68
TP86
TP37
TP38
TP49
TP62
R293
R255
TP47
R265
TP52
R25
TP48
R44
C54
POS 1
C178
U34
LE12
P13
PERIPHERAL CONNECTOR
WLAN SECONDARY
C17
R151
R152
Autoboot, J6
C116
POS 2
OPEN
CLOSE
OPEN
OPEN
CAN2 TERMINATION
IDENT
LBL1
R13
L18
R209
S5
S8
POS 1
OPEN
U32
R141
R121
R66
R65
R92
R79
R247
USER
BUTTON 1
C99
C98
U30
C89
R154
R153
S3
X14
R57
R59
L8
C11
R206
R47
CAMERA 2
MICRO SD
LE49
LE51
LED 2
L5
L20
H9
X21
R96
R135
LED 1
L6
S10
ASSOC
J8
L19
C10
R218
R207
J1
X29
C12
L21
R35
R208
L7
L22
R27
C110
C113
U41
R271
L10
C114
C67
U4
C64
C5
C100
U31
C65
C126
C125
Y1
L24
L25
R37
U14
R16
C2
C55
R8
C1
R215
R214
R173
R193 R196
C94
U55
C192
R198
R134
R36
U42
R197
C194
U35
C102
C69
R201
R202
R253
R183
C187
C190
R38
U43
J11
J10
L26
+ C111
C68
C101
C134
U40
R269
R273
R266
C59
U56
R191
R190
R128
U54
C107
R213
C19
C9 R122
C196
C197
R102
C95
XBEE MODULE
R101
R172
R192
U53
C72
C131
RESET
C4
C58
R254
U3
TP41 TP39
LE50
C84
JP3
ON=AUTOBOOT
R195
C15
S12
C189
U52
R264
R263
R262
R261
R260
R259
R258
R257
R256
R292
L12
R162
C168
R28
C43
R216
R10
DIGI
INTERNATIONAL
L3
C158
R188
C169
R31
C45
R33
C48
U27
U7
R12
R52
C127
J15
U39
R127
POWER
U23
R136
U51
R229
U38
C38
C57
C28
C27
R174
R69
R60
C172
R51
MICRO
S13
C195
U25
C186
R120
U47
C167
C130
C49
X7
USB OTG
USB HOST
C108
J24
J6
U1
U5
R131
C188
C191
C193
O2
V10
C52
U18
U26
U20
O1
V11
X28
R187
Y3
L16
R85
U10
R171
U36
U12
U37
U19
R117
U22
C50
C22
C8
TP73
TP76
R217
R220
CONNECTCORE i.MX53 MODULE
R132
R42
J12
U49
L27
DISABLED
R221
DISABLED
4-WIRE
ACTIVE
C53
U48
C14
C86
R20
C63
C46
C41
U16
UART3 (TTL)
R199
C128 C129
R176
LINE OUT
R189
LINE IN
R39
R285
JP1
R23
ACTIVE
2-WIRE
TERMINATION
1-WIRE
C149
R105
SATA
+ C109
R124
R82
R129
R125
AUTO PWR DWN
RS485 MODE
S6
C147
R181
C40
C3
TP137
TP44
R133
LE48
C56
RS422/485
1234
LE47
C148
R54
TP81 TP80 TP78 TP79 TP24
R276
R279
R288
R278
R287
R277
R74
R75
LE62
OFF/OPEN
RS232
MODE
LE63
C33
C26
ON/CLOSE
AUDIO
J18
TP67 TP116
KEYPAD
H3
ON
J5
C16
C88
C145
R34
X19
C20
C87
R108
C83
R291
POS DESCRIPTION
RXD
R118
U11
C42
C34
TP85 TP84 TP83
R286
R53
C93
R107
RN2
TXD
U17
JP10
U6
P2
X20
R272
DIGITAL I/O
J2
R275
H1
C39
U24
X30
C96
LE44
R73
LE60
LE61
U9
X30
C36
C32
J3
R280
R290
R56
S7
R72
LE59
LE43
LE46
R77
L29
C21
ON=ENABLE
COIN CELL
LE45
R43
R158
X45
12
R71
U21
C37
C31
C51
P19
POE MODULE
POE MODULE
JTAG
C97
C85
R231
X13
C82
R89
U50
R138
R289
ON
PWM
R106
P20
TP77
RXD
I2C
SPI
L17
C81
R137
R142
Q2
R143
R97
TXD
UART2 STATUS
R41
R3
R86
LE42
X27
J4
R1
P14
TOUCH SELECTION
P23
P22
P24
D1
LE40
LE58
R109
BATT
R4
R123
R55
LE41
LE57
R114
C30
X27
C35
R58
P12
U61
R184
R2
R48
R67
R126
L1
C133
C90
C80
C79
C135
U2
R7
C29
C60
R139
D6
D5
UART1 STATUS
UART1 (CONSOLE)
UART2 (MEI)
C25
R21
C78
R9
R70
R40
J13
J23
Coincell
Enable,
J3
R159
R50
ON=
ENABLE EXT BATT
R24
JP6
C163
JP2
+3.3V_MOD
WLAN PRIMARY
P1
PARALLEL LCD
L11
C166
ON=SJC-ONLY
JP20
R18
TP93
C165
C23
R68
L23
R130
EXT BATT
U57
C44
+3.3V_JS
C105
C159
U45
U58
P29
U15
C47
C162
R26
V2
L30
C156
C157 R177
TP22
TP21
R179
TP20
R178
U46
R22
R81
R80
R185
R186
VGA
C6
C7
R182 C153
R19
R15
R180 C152
R14
SD/MMC
C104
R11
P4
TP19
C160
L28
C103
LVDS
LCD
R232 C177
R175
R227
R98
X32
X24
9V-30VDC
LE6
R228
V6
MAIN POWER
V5
Battery
Enable,
J13
R194
R230
OFF
R95
J19
HDMI
+5V
LE7
ON
LE4
LE8
R94
TP65
+3.3V
VCHRG VBATT
S2
S2
POWER
BUTTON 2
CAN2
WLAN
Termination,Disable,
J9
J17
CAN1
Termination,
J7
Battery Enable, J13
When J13 is set, the development board can be powered by an external battery connected to
J23.
+3.3V Source, P29
When set on positions 1-2, the +3.3V supply of the development board is generated in a
voltage regulator provided on the development board.
Čą
Čą
Čą
Ăš
Ăź
Ăş
Ă˝
Ăš
Ăź
ø
Ăš
Ăż
Ăż
Čą
Ăż
Ăš
Ăť
ȹȹȹ
Čą
Čą
Čą
Čą
ȹȹ
When set on positions 2-3, the +3.3V supply of the development board is generated on the
module.
WLAN Disable, J17
When J17 is set, the WLAN interface is disabled.
Touch Selection, J20
When J20 is set, an external SPI touch screen controller is configured for the Parallel LCD
interface, and the internal analog touch screen controller (on module) is configured for the
LVDS interface.
When J20 is removed, an external SPI touch screen controller is configured for the LVDS
interface, and the internal analog touch screen controller (on module) is configured for the
parallel LCD interface.
Coincell Enable, J3
When J3 is set, +3V from the lithium coin cell battery is supplied to the RTC, even if the
board is switched off.
JTAG Mod, J4
When J4 is set, the Standard JTAG interface is the only debug capability enabled for the
ConnectCore for i.MX53.
When J4 is removed, the Trace port is also enabled for debugging.
Autoboot, J6
When J6 is set, the module boots as soon as the power supplies are present.
When J6 is removed, a power on event is needed to turn on the module.
CAN1 Termination resistor, J7
When J7 is set, a 120 Ohm termination resistor is connected to the CAN 1 lines.
CAN2 Termination resistor, J9
When J9 is set, a 120 Ohm termination resistor is connected to the CAN 2 lines.
Čą
Čą
€
Čą
‚

Čą
‚
ƒ
„
ȹȹȹ
†
Čą
Čą
Čą
Čą
ȹȹ
Configuration Resistors
UART1_RTS
SD3_CLK
Čą
€

Čą
R102
ƒ
„
Čą
R84
R222
C150
U29
J20
U28
R184
C161
C155
C159
C151
C164
C70
C71
C24
C66
C62
R268
L9
C106
TP45
TP46
TP43
TP42
R270
TP61
R103
TP113
R110
TP63
R111
TP69
TP118
TP64
TP117
TP60
R99
TP114
R274
TP115
TP23
TP70
TP71
R282
R281
R284
R283
TP66
C61
R112
R113
R116
R119
L4
R88
TP74
TP72
TP73
TP75
R93
R30
R29
C113
R17
C11
C13
OPEN
OPEN
CLOSE
R46
R203
R204
TP29
POS 2
R205
TP25
TP30
TP28
TP31
TP26
TP27
TP92
POS 1
OPEN
R140
C178
KEY_ROW7
CSI0_RESET#
U34
J27
DESCRIPTION
INT. BOOT
CLOSE
OPEN
BOOT - uSD
BOOT - SD
CLOSE
OPEN
BOOT - FUSES
CLOSE
CLOSE
BOOT - SATA
CLOSE
CLOSE
SER DOWNLOAD
CAN2
R83
RESERVED
X31
R49
CAMERA 1
C120
C119
BOOT CONF
J9
JP5
ETHERNET 2 J7
C123
C124
JP4
CAN1
CAN1 TERMINATION
ON
ON
S9
JP12
U8
J17
U33
12
C118
R104
U13
12
R100
ON=
WLAN DISABLE
C121
C122
P15
R32
C171
S8
P21
U44
R45
X15
C170
C18
R211
X18
X16
C132
SD/MMC
R246
R5
R61
R90
R63
R62
L18
LE12
P13
PERIPHERAL CONNECTOR
WLAN SECONDARY
R209
C17
R151
R152
C10
C65
C64
R218
R207
TP91
TP35
TP33
TP82
TP87
TP57
TP36
TP88
TP58
TP68
TP86
DESCRIPTION
BOOT - FLASH
S9
CLOSE
C117
LBL1
L5
L20
R206
CAN2 TERMINATION
IDENT
R13
J8
L6
R87
OPEN
C116
POS 2
OPEN
TP90
POS 1
OPEN
U32
TP37
TP38
TP49
TP52
S8
TP62
TP89
R293
R255
TP48
TP47
R265
R44
U30
C54
R25
C99
C98
R141
R121
R66
R65
R92
R79
R247
S5
C12
L19
C179
R96
USER
L7
L22
R47
C89
R154
R153
C84
S3
X14
R57
DIGIO0
XBEE_RESET#
L21
H9
X21
MICRO SD
LE49
LE51
LED 2
R59
L10
CAMERA 2
R213
LED 1
L24
C114
R27
C110
R35
S10
ASSOC
L8
+ C111
C115
U40
C102
R16
C5
C100
R201
R202
R253
J1
X29
J11
J10
L25
R37
U41
C125
C2
C1
R215
R214
R173
R193 R196
R198
R128
R229
C126
U4
R208
R264
R263
R262
R261
R260
R259
R258
R257
R256
R292
R162
C168
L12
R135
C9 R122
C19
BUTTON 1
‚
R197
C194
XBEE MODULE
R101
R172
C55
R8
Y1
C131
RESET
‚
C94
U55
C192
R271
C107
LE50
U27
C196
C197
R195
ON=AUTOBOOT
JP3
C15
Čą
R183
C187
C190
U56
C72
BUTTON 2
CSI1_HSYNC
DISP1_HSYNC
U54
TP41 TP39
U47
U7
R12
S12
R192
U53
R78
R6
R76
R64
R91
R216
R10
U39
R127
POWER
R52
C127
J15
R28
C43
L3
C158
R188
C169
R33
C48
MICRO
S13
C189
U52
R120
DIGI
INTERNATIONAL
R174
R69
R60
C172
R51
C49
U23
R136
U51
R190
U19
U37
C38
U38
C57
R131
C195
U25
C186
R36
U42
C108
C167
J6
U1
U5
V10
C188
C191
C193
O2
U36
U12
C27
C28
C56
O1
C52
X28
J24
C130
J12
C69
R171
V11
U18
U26
U20
C50
C22
L16
C8
ETHERNET 1
L26
R38
U43
R254
U3
R132
C53
R42
C134
C46
R117
U22
R187
Y3
X7
USB OTG
USB HOST
C112
LE63
CONNECTCORE i.MX53 MODULE
C59
U35
DISABLED
C95
U31
ACTIVE
C4
C58
U14
TERMINATION
R217
R220
C68
R269
R273
R266
S6
1-WIRE
C14
R85
U10
C67
DISABLED
4-WIRE
C41
U48
R31
C45
LINE IN
R39
C86
R20
C63
U49
L27
ACTIVE
2-WIRE
R133
LE48
U16
UART3 (TTL)
R199
C128 C129
R176
LINE OUT
R181
R189
C3
R105
SATA
C101
AUTO PWR DWN
RS485 MODE
R221
R134
R75
LE62
TP76
JP1
R23
1234
C147
C40
TP44
+ C109
R124
R82
R129
R125
RS422/485
LE47
C148
R54
TP137
TP81 TP80 TP78 TP79 TP24
KEYPAD
R276
R279
R288
R278
R287
R277
R74
RS232
AUDIO
C149
TP67 TP116
R291
OFF/OPEN
MODE
J5
C16
C88
C145
C83
H3
ON/CLOSE
ON
X19
J18
R53
C87
R108
R34
POS DESCRIPTION
RXD
U17
C26
TP85 TP84 TP83
R286
C20
C93
R107
RN2
TXD
R118
U11
U24
X30
JP10
U6
P2
X20
R272
DIGITAL I/O
J2
R275
H1
C39
C42
C34
C33
C36
C96
LE44
R73
LE60
LE61
U9
X30
R77
J3
R285
R56
S7
R72
LE59
LE43
LE46
C32
R89
X45
ON=ENABLE
COIN CELL
LE45
R43
C97
C85
P19
POE MODULE
POE MODULE
JTAG
12
R71
U21
C37
C31
C51
DIGIO1
XBEE_SLEEP_RQ
L29
C21
X13
C82
R280
R290
ON
PWM
R106
P20
R289
RXD
I2C
R231
Q2
R138
P14
TOUCH SELECTION
P23
P22
SPI
L17
C81
U50
R143
R97
TXD
UART2 STATUS
R41
R3
R86
LE42
X27
J4
R1
P24
D1
LE40
LE58
R109
BATT
R4
R123
R55
LE41
LE57
R114
C30
X27
R142
L1
C133
UART1 STATUS
C29 C35
R139
R126
R137
U2
R7
UART1 (CONSOLE)
C60
R58
R48
R2
C176
C175
C174
C154
C90
C80
C79
C135
D5
D6
J13
J23
R158
C25
R21
R67
C78
R24
R9
R70
R40
C163
JP2
+3.3V_MOD
P12
U61
L11
C166
ON=SJC-ONLY
JP20
R18
TP93
C165
C23
R68
L23
JP6
UART2 (MEI)
R159
R50
ON=
ENABLE EXT BATT
C105
U57
C44
+3.3V_JS
R130
EXT BATT
C162
U45
U58
P29
U15
C47
C157 R177
TP22
TP21
R179
TP20
R178
R26
V2
WLAN PRIMARY
P1
PARALLEL LCD
R182 C153
R22
R81
R80
R185
R186
VGA
C6
C7
U46
R19
R15
R191
C104
R14
TP77
X24
R11
L30
C156
R180 C152
X32
P4
TP19
C160
L28
C103
LVDS
LCD
R232 C177
R175
R227
R98
TP51
V5
MAIN POWER
LE6
R228
V6
R95
J19
HDMI
+5V
LE7
R194
R230
OFF
LE4
ON
9V-30VDC
LE8
R94
TP65
+3.3V
VCHRG VBATT
S2
S2
POWER
UART1_CTS
SD3_CMD
C91
DIGIO2
XBEE_ON_SLEEP#
CSI1_VSYNC
DISP1_VSYNC
KEY_COL7
CSI1_RESET#
ȹȹȹ
‡
Čą
Čą
Čą
Čą
ȹȹ
CSI0_RESET#/KEY_ROW7, R203/R204
The development board provides two 0Ÿ resistors, R203 and R204 to select the interface
where the KEY_ROW7/GPIO5_27 signal is connected. These two resistors should not be
populated at the same time.
The following table shows the configuration of these two resistors:
‰
Š
‰
ˆ
‹
CSI1_RESET#/KEY_COL7, R201/R202
The development board provides two 0Ÿ resistors, R201 and R202 to select the interface
where the KEY_COL7/GPIO5_26 signal is connected. These two resistors should not be
populated at the same time.
The following table shows the configuration of these two resistors:
‰
Š
‰
ˆ
Œ

Œ
CSI1_HSYNC#/DISP1_HSYNC, R256/R292
The development board provides two 0Ÿ resistors, R256 and R292 to select the interface
where the EIM_DA11/CSI1_HSYNC signal is connected. These two resistors should not be
populated at the same time.
The following table shows the configuration of these two resistors:
‰
Š
‰
ˆ
Œ
Ž
Œ
Œ
Œ
Čą
Čą
€
Čą
‚

Čą
‚
ƒ
„
Œ

Ž
Œ
Ž
Œ
ȹȹȹ
†
Čą
Čą
Čą
Čą
ȹȹ
CSI1_VSYNC#/DISP1_VSYNC, R255/R293
The development board provides two 0Ÿ resistors, R255 and R293 to select the interface
where the EIM_DA12/CSI1_VSYNC signal is connected. These two resistors should not be
populated at the same time.
The following table shows the configuration of these two resistors:
‰
Š
‰
ˆ
Œ

Œ
Œ
Œ
Œ


Œ

Œ
UART1_CTS/SD3_CMD, R283/R284
The development board provides two 0Ÿ resistors, R283 and R284 to select the interface
where the SD3_CMD/UART1_CTS signal is connected. These two resistors should not be
populated at the same time.
The following table shows the configuration of these two resistors:
‰
Š
‰
ˆ
Œ
Œ
Œ
Œ
UART1_RTS/SD3_CLK, R281/R282
The development board provides two 0Ÿ resistors, R281 and R282 to select the interface
where the SD3_CLK/UART1_RTS signal is connected. These two resistors should not be
populated at the same time.
The following table shows the configuration of these two resistors:
‰
Š
‰
ˆ
Œ
Œ

Œ
Čą
Čą
€
Čą
‚

Čą
‚
ƒ
„
ȹȹȹ
†
Čą
Čą
Čą
Čą
ȹȹ
DIGIO0/XBEE_RESET#, R277/R287
The development board provides two 0Ÿ resistors, R277 and R287 to select the interface
where the GPIO6_15 signal is connected.
The following table shows the configuration of these two resistors:
‰
Š
‰
ˆ
Œ
Œ
DIGIO1/XBEE_SLEEP_RQ, R278/R288
The development board provides two 0Ÿ resistors, R278 and R288 to select the interface
where the GPIO7_6 signal is connected.
The following table shows the configuration of these two resistors:
‰
Š
‰
ˆ
Œ
Œ

DIGIO2/XBEE_ON_SLEEP#, R280/R289
The development board provides two 0Ÿ resistors, R280 and R289 to select the interface
where the GPIO6_16 signal is connected.
The following table shows the configuration of these two resistors:
‰
Š
‰
ˆ
Œ
Œ
Čą
Čą
€
Čą
‚

Čą
‚
ƒ
„
ȹȹȹ
†
Čą
Čą
Čą
Čą
ȹȹ
LEDs
+3.3V,
LE7
+5V,
LE6
C176
C175
C174
C154
R84
R222
C150
J20
R184
C164
L4
C70
C71
C24
C66
C62
R268
L9
C106
TP45
ETHERNET 1
R270
TP61
TP43
TP42
TP114
R103
TP113
R110
TP63
R111
TP69
TP60
TP118
TP64
TP117
X7
C61
R112
R113
R116
R119
R99
R274
TP115
TP23
TP70
TP71
R282
R281
R284
R283
TP66
TP46
R93
R30
C115
R29
L8
C13
R46
R203
R204
TP29
TP26
POS 2
R205
TP25
TP30
TP31
OPEN
DESCRIPTION
INT. BOOT
OPEN
CLOSE
RESERVED
CLOSE
BOOT - SD
CLOSE
CLOSE
CLOSE
BOOT - SATA
CLOSE
OPEN
BOOT - FUSES
SER DOWNLOAD
R83
R140
J27
CLOSE
CAN2
C178
U34
X31
R87
TP33
TP28
TP27
TP92
TP36
TP35
TP91
TP57
TP82
TP87
TP89
TP88
TP58
TP68
TP86
TP37
TP38
TP90
TP52
TP49
R255
TP48
R25
TP47
R265
R44
C54
POS 1
S9
OPEN
BOOT - uSD
C179
C120
C119
BOOT CONF
J9
ETHERNET 2 J7
C123
C124
JP4
CAN1
CAN1 TERMINATION
ON
ON
S9
JP12
U8
12
C117
C118
R104
U13
12
R100
ON=
WLAN DISABLE
J17
U33
C121
C122
P15
R32
C171
S8
P21
U44
JP5
C170
R246
R5
R61
R90
C18
R49
CAMERA 1
C132
R211
R141
R121
R66
R65
R92
R79
R247
X18
IDENT
X15
R45
CAN2 TERMINATION
X16
LBL1
R13
L18
LE12
P13
PERIPHERAL CONNECTOR
WLAN SECONDARY
R209
C17
R151
R152
BUTTON 1
TP62
R293
R264
R263
R262
R261
R260
R259
R258
R257
R256
R292
C116
POS 2
OPEN
DESCRIPTION
BOOT - FLASH
C89
R154
S5
C10
C11
R206
CLOSE
OPEN
OPEN
CAMERA 2
R63
R62
LE49
LE51
R153
USER
S8
POS 1
OPEN
U32
MICRO SD
X14
R57
C84
S3
C99
C98
S10
LED 2
R59
L5
L20
H9
X21
R96
R135
LED 1
L6
R47
U30
C107
ASSOC
J8
L19
XBEE MODULE
R213
C19
C12
R17
C112
R218
R207
J1
X29
L7
L22
L21
R35
R208
L10
C114
R27
C110
C113
C65
U31
U41
C64
C5
C100
U4
+ C111
C68
C67
U35
C102
C126
C125
Y1
R201
R202
R253
R198
R197
C194
R16
C2
C55
R8
C1
R215
R214
R173
R193 R196
C94
U55
C192
L24
L25
R37
U42
U56
R191
R190
R128
R183
C187
C190
R36
J10
L26
R38
U43
C69
J11
USB OTG
USB HOST
+ C109
C134
U40
C59
R271
C131
RESET
U29
C151
R88
TP74
TP72
TP73
TP75
TP76
R285
R280
R290
R289
U54
C72
LE50
C9 R122
C196
C197
R195
JP3
ON=AUTOBOOT
R102
R192
U53
TP41 TP39
R101
R172
C189
U52
R78
R6
R76
R64
R91
R216
R10
C158
R188
C15
S12
U23
R136
U51
R229
U38
L12
R162
C168
R28
C43
L3
R174
R33
C48
MICRO
U27
U7
R12
R52
C127
J15
U39
R127
POWER
C195
U25
C186
R120
DIGI
INTERNATIONAL
R69
R60
C172
C169
R31
C45
LINE IN
R51
C167
S13
R85
C108
X28
J24
C130
C49
U1
U5
R131
C188
C191
C193
O2
V10
C52
C38
C57
C28
C27
C56
O1
V11
U18
U26
U20
C50
U47
J6
C95
R171
U36
U12
U37
U19
R117
R118
U16
U22
R187
Y3
C58
R254
U3
R132
C53
C22
L16
C8
C4
R217
R220
CONNECTCORE i.MX53 MODULE
C46
C41
R42
J12
C86
R20
U10
U14
DISABLED
R133
LE48
U48
C14
U49
C101
DISABLED
4-WIRE
ACTIVE
R134
R75
LE62
C26
UART3 (TTL)
R199
C128 C129
R176
LINE OUT
R189
C3
R39
R105
SATA
C63
R269
R273
R266
ACTIVE
2-WIRE
TERMINATION
1-WIRE
C149
TP44
L27
AUTO PWR DWN
RS485 MODE
R221
S6
C147
R181
C40
R276
R279
R288
R278
R287
R277
1234
LE47
C148
R54
L29
C21
JP1
RS422/485
AUDIO
J18
TP137
TP81 TP80 TP78 TP79 TP24
R82
R129
R125
R124
RS232
LE63
C42
U11
TP85 TP84 TP83
TP67 TP116
KEYPAD
R291
OFF/OPEN
MODE
J5
C16
C83
H3
ON/CLOSE
ON
X19
C20
C88
C145
P2
X20
R272
DIGITAL I/O
J2
R286
R53
C87
R108
R34
POS DESCRIPTION
RXD
U17
JP10
U6
C93
R107
RN2
TXD
R74
LE61
U9
C34
J3
R275
H1
C39
U24
X30
C96
LE44
R73
LE60
R23
S7
R72
LE59
LE43
C33
X30
C36
C32
R158
X45
12
LE46
R77
C97
C85
P19
POE MODULE
POE MODULE
JTAG
X13
C82
R89
U50
R138
ON=ENABLE
COIN CELL
LE45
R43
PWM
R106
P20
TP77
ON
I2C
SPI
L17
C81
R137
R142
Q2
R143
RXD
R71
U21
C37
C31
C51
R3
R231
R97
TXD
UART2 STATUS
R41
J4
R1
R86
LE42
LE58
R109
P14
TOUCH SELECTION
P23
P22
P24
D1
LE40
R56
R58
BATT
R4
R123
R55
LE41
LE57
R114
C30
X27
C35
X27
UART2 (MEI)
R2
R48
R67
R126
L1
C133
C90
C80
C79
C135
U2
R7
C29
C60
R139
D6
D5
UART1 STATUS
UART1 (CONSOLE)
UART 2
Status
LEDs
C25
R21
C78
R9
R70
R40
J13
J23
UART 1
Status
LEDs
R159
R50
ON=
ENABLE EXT BATT
R24
JP6
C163
JP2
+3.3V_MOD
WLAN PRIMARY
P1
P12
U61
L11
C166
ON=SJC-ONLY
JP20
R18
TP93
C165
C23
R68
L23
R130
EXT BATT
U57
C44
+3.3V_JS
C105
C161
C155
U45
U58
P29
U15
C47
C159
R26
V2
L30
C156
C157 R177
TP22
TP21
R179
TP20
R178
R182 C153
R22
R81
R80
R185
R186
VGA
C6
C7
U46
R19
R15
R180 C152
R14
TP51
C104
R11
PARALLEL LCD
U28
C103
P4
TP19
C160
L28
X32
X24
R232 C177
R175
R227
R98
LVDS
LCD
SD/MMC
V5
MAIN POWER
LE6
R228
R194
V6
R95
9V-30VDC
R230
OFF
J19
HDMI
+5V
LE7
ON
LE4
LE8
R94
TP65
+3.3V
VCHRG VBATT
S2
S2
POWER
C91
Charger,
LE8
C162
Battery,
LE4
BUTTON 2
USER LED1,
LE51
USER LED2,
LE49
Assoc.,
LED50
WLAN, LE12
WLAN, LE12
Green LED indicating WLAN operational status.
Čą
Čą
€
Čą
‚

Čą
‚
ƒ
„
ȹȹȹ
†
Čą
Čą
Čą
Čą
ȹȹ
Power LEDs LE4, LE6, LE7 and LE8
The power LEDs show the status of their power supplies. All power LEDs are red.
„LE4
ON indicates that battery power is present or that the DA9053 PMIC is charging
the battery. The intensity of the LED will change depending on the battery voltage
and depending on the charging voltage.
„LE6
ON indicates that +5VDC power for the development board is present
„LE7
ON indicates that +3.3VDC power for the development board is present
„LE8
ON indicates that charger power is present
User LEDs, LE49 and LE51
The user LEDs are controlled through applications running on the ConnectCore for i.MX53
module. You may use these module signals to implement the LEDs:
’
“
”
•
–
—
˜
–
™
š
›
œ


ž
•
Ÿ
ÂĄ
¢
ÂŁ
¤
ÂŚ
§
¨
Š
ÂŞ
ÂŤ
¨
ÂŹ
­
ÂŤ
¨
ÂŽ
­
ÂŻ
°
Âą
²
ÂŽ
ÂŞ
Âł
´
ÂŚ
§
¨
Š
ÂŞ
ÂŤ
¨
ÂŹ
Âł
ÂŤ
¨
Âľ
Âś
ÂŻ
°
Âą
²
¡
ÂŞ
­
Âł
š
ÂĽ
Serial Status LEDs
The development board has two sets of serial port LEDs - four for serial port 1 and four for
serial port 2. The LEDs are connected to the TTL side of the RS232 or RS4xx transceivers.
„Green
Čą
Čą
€
Čą
„Red
means corresponding signal low
„The
intensity and color of the LED will change when the voltage is switching
‚

means corresponding signal high
Čą
‚
ƒ
„
ȹȹȹ
†
‘
Čą
Čą
Čą
Čą
ȹȹ
UART 1 Status LEDs
š
¸
š
Š
Âş
¨
Âź
š
½
š
•
ž
š
Âż
œ
•
ž

“
ž
•
ž

“
ž
•
Âť
ÂŹ
ÂŻ
Š
¨
¨
À
ÂŤ
¨
Âľ
­
ÂŤ
¨
Âľ
´
Á
Â
ÂŹ
ÂŤ
¨
ÂŽ
¡
ÂŤ
¨
Âľ
Âł
Š
ÂŤ
¨
ÂŽ
Ã
ÂŤ
¨
Âľ
Ä
Š
Á
§
Å
ÂŤ
¨
ÂŽ
Âś
ÂŤ
¨
Âľ
Âľ
Æ
Á
§
Å
Â
ÂŹ
UART 2 Status LEDs
š
¸
š
Š
Âş
¨
Âź
š
½
š
•
ž
š
Âż
œ
•
Âť
ÂŹ
ÂŻ
Š
¨
¨
À
ÂŤ
¨
Ç
´
ÂŤ
¨
Âľ
ÂŽ
Á
Â
ÂŹ
ÂŤ
¨
Ç
­
ÂŤ
¨
Âľ
Ç
Š
ÂŤ
¨
Ç
Âł
ÂŤ
¨
Âľ
¡
Š
Á
§
Å
ÂŤ
¨
Ç
Ä
ÂŤ
¨
Âľ
Ã
Æ
Á
§
Å
Â
ÂŹ
XBee Assoc., LE50
This LED is connected to the Associate output of the Digi XBee module. This LED provides
information of the device's network status and diagnostics information. For a more in-depth
description of this LED please refer to the Digi XBee module documentation available on the
Digi website.
Čą
Čą
€
Čą
‚

Čą
‚
ƒ
„
ȹȹȹ
†
Čą
Čą
Čą
Čą
ȹȹ
Analog Video Interface (VGA)
VGA Connector, X32
R84
R222
C150
U28
U29
C151
C91
L4
C70
C71
C24
C66
C62
R268
L9
C106
TP45
ETHERNET 1
R270
TP61
TP46
TP43
TP42
TP69
X7
R93
R30
C115
R29
C13
L5
C10
C11
L18
TP25
R46
R203
R204
TP29
POS 2
R205
TP30
TP28
OPEN
DESCRIPTION
INT. BOOT
BOOT - uSD
OPEN
CLOSE
RESERVED
CLOSE
CLOSE
OPEN
BOOT - SD
CLOSE
CLOSE
CLOSE
BOOT - SATA
CLOSE
OPEN
BOOT - FUSES
SER DOWNLOAD
R83
R140
J27
CLOSE
CAN2
C178
U34
X31
R87
TP33
TP31
TP26
TP27
TP92
POS 1
S9
OPEN
X15
C119
BOOT CONF
J9
ETHERNET 2 J7
C123
JP4
CAN1
CAN1 TERMINATION
ON
ON
S9
JP12
U8
J17
U33
12
R104
U13
12
R100
C121
C122
P15
R32
LE12
P13
PERIPHERAL CONNECTOR
R209
WLAN SECONDARY
C17
C118
ON=
WLAN DISABLE
C171
S8
P21
U44
JP5
C124
C170
R78
R6
R76
R64
R91
C18
R49
CAMERA 1
C120
R211
X18
X16
C132
R45
CAN2 TERMINATION
R246
R5
R61
R90
R63
R62
L8
C113
R17
C112
R218
R207
TP58
TP36
TP35
TP91
TP57
TP82
TP87
TP89
TP88
TP90
TP68
TP86
TP37
TP38
TP49
TP52
POS 2
OPEN
C117
LBL1
R13
L6
L20
R206
DESCRIPTION
BOOT - FLASH
OPEN
C116
TP62
R293
R255
TP48
R25
TP47
R265
R44
C54
S8
POS 1
OPEN
U32
R141
R121
R66
R65
R92
R79
R247
S5
J8
C179
IDENT
C131
R151
R152
C99
C98
U30
C89
R154
USER
C12
L19
R47
CAMERA 2
R213
LE49
LE51
R153
S3
L22
L21
H9
X21
MICRO SD
X14
L7
C114
R27
C110
S10
ASSOC
L10
L25
R35
R208
L24
+ C109
C65
R201
R202
R253
C64
C5
C100
U4
J10
L26
R37
U41
C125
C126
J11
USB OTG
USB HOST
+ C111
C68
U40
C102
R16
C2
C1
R215
R214
R173
U56
R197
C194
J1
X29
R96
R135
C9 R122
C196
R102
C61
R112
R113
R116
R119
R99
TP114
R103
TP113
R110
TP63
R111
TP60
TP118
TP64
TP117
TP23
TP70
TP115
R274
TP66
R193 R196
C55
R8
Y1
XBEE MODULE
R57
BUTTON 1
RESET
J20
C161
C155
C159
C162
R88
TP71
TP72
R128
C94
U55
C192
U54
U53
R183
R264
R263
R262
R261
R260
R259
R258
R257
R256
R292
C168
L12
R162
R28
C107
R101
R172
U52
C190
R36
R271
C72
LED 2
C84
JP3
R195
ON=AUTOBOOT
C19
R59
C15
R52
C127
R192
TP41 TP39
LE50
LED 1
R12
S12
U23
C189
C187
R120
C43
R216
R10
C158
R188
C197
U27
U7
R127
POWER
C69
U42
R198
U36
U38
C38
R131
C195
U25
R136
U51
V10
C52
C188
U1
U5
C186
DIGI
INTERNATIONAL
L3
R174
R69
R60
C172
C169
R33
C48
MICRO
S13
C191
C193
O2
V11
R191
O1
R190
U19
U37
U12
C57
C28
C27
C50
U47
C167
J6
C49
J15
U39
J24
C130
R51
L16
C8
R85
R38
U43
R171
R42
J12
C86
R20
C108
R187
Y3
C134
U3
R132
C22
C14
TP73
TP75
TP76
CONNECTCORE i.MX53 MODULE
C59
C67
DISABLED
C95
U35
ACTIVE
C4
C58
R254
U31
TERMINATION
R217
R220
U14
X28
U48
R31
C45
LINE IN
R39
R105
SATA
C101
DISABLED
4-WIRE
R269
R273
R266
RS422/485
ACTIVE
2-WIRE
R117
R118
U16
C56
C26
UART3 (TTL)
R199
C128 C129
R176
LINE OUT
R189
C3
C145
U10
L27
RS232
AUTO PWR DWN
RS485 MODE
U18
U26
U20
1-WIRE
C149
C88
R108
C63
U49
R279
R288
R278
R287
R277
MODE
C53
C147
R181
C40
R285
JP1
R229
C33
U11
C42
C34
OFF/OPEN
R221
LE63
U22
C148
R54
TP44
C46
C41
AUDIO
J18
TP137
R276
R133
LE48
U17
ON/CLOSE
R134
R75
LE62
1234
LE47
J5
C16
TP81 TP80 TP78 TP79 TP24
KEYPAD
R291
ON
X19
C20
R107
C83
H3
POS DESCRIPTION
RXD
R286
R53
C93
C87
R34
S6
U24
X30
TP85 TP84 TP83
TP67 TP116
R82
R129
R125
R124
TXD
C39
JP10
U6
P2
X20
R272
DIGITAL I/O
J2
R275
H1
R74
LE61
U9
X30
C36
C32
P19
POE MODULE
RN2
LE46
R77
C96
LE44
R73
LE60
R23
S7
R72
LE59
LE43
J3
R280
R290
R56
12
TP74
ON=ENABLE
COIN CELL
LE45
R43
R89
X45
R289
ON
R71
U21
C37
C31
C51
L29
C21
R231
C81
U50
P20
POE MODULE
JTAG
X13
C82
C97
C85
L17
R138
TP77
RXD
UART2 STATUS
R41
R3
PWM
R106
LE42
X27
R1
R86
LE40
LE58
R109
I2C
SPI
D1
Q2
R143
R142
R137
R139
TXD
R4
R123
R55
LE41
LE57
R114
C30
X27
C29 C35
R58
BATT
R97
UART1 STATUS
J4
P14
TOUCH SELECTION
P23
P22
P24
R184
R2
C176
C175
C174
C154
C79
C135
R126
L1
C133
C90
C80
C163
R48
R21
R67
C78
D6
D5
U2
R7
UART1 (CONSOLE)
R158
C25
R159
R50
ON=
ENABLE EXT BATT
R40
J13
J23
C60
U61
L11
C166
JP2
+3.3V_MOD
R24
R9
R70
C165
ON=SJC-ONLY
JP20
R18
P12
TP20
TP93
C23
R68
L23
JP6
UART2 (MEI)
C44
+3.3V_JS
R130
EXT BATT
P29
U15
C47
C105
C157 R177
TP22
TP21
R179
R178
U45
U57
VGA
C6
C7
R26
C164
R15
U58
U46
R22
WLAN PRIMARY
P1
PARALLEL LCD
R182 C153
R14
R19
V2
R180 C152
R11
L30
C156
R81
R80
R185
R186
R282
R281
R284
R283
C104
R232 C177
R175
R227
X32
X24
9V-30VDC
C103
P4
TP19
C160
L28
TP51
V5
MAIN POWER
R98
LVDS
LCD
SD/MMC
R95
LE6
R228
V6
R194
R230
OFF
J19
HDMI
+5V
LE7
ON
LE4
LE8
R94
TP65
+3.3V
VCHRG VBATT
S2
S2
POWER
BUTTON 2
Analog Video Connector, X32
connector. The Analog Video interface is connected to the television encoder interface (TVE)
and to the display 2 synchronization interface (DISP1) of the i.MX53 CPU.
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Čą
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Čą
‚

Čą
‚
ƒ
„
ȹȹȹ
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È
Čą
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Ð
É
Ê
Ë
Ë
Ì
Í
Î
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Ê
Ï
Ì
Ê
Ï
Ñ
Ò
Ó
Ô
Õ
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Ö
Ï
×
Ù
Ú
Ï
Ø
Čą
Ì
Ø
Ð
Ì
Ì
Ï
Ì
Ë
Û
Í
Ì
ȹȹ
The VGA interface shares share the functionality in the development board with the
bootstrap interface and with the camera 2 interface. To avoid conflict between the camera
2/VGA signals and the bootstrap interface, a delay circuit is provided in the board to disable
the camera 2 and the VGA interfaces while the bootstrap configuration is being reading by
the i.MX53 CPU. Once the bootstrap configuration has been read the camera 2 and the VGA
interfaces are enabled. To avoid conflicts between the camera 2 and the VGA interface 0Ÿ
resistors are used to select the interface to be used. Please refer to the "Configuration
Resistors" section on page 79 for detailed information.
The table below shows the pinout of the Analog Video connector.
“
Ü
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Ý
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Ý
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Čą
Ë
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’
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”
•
–
—
­
ç
ÂŻ
è
ÂŞ
Š
Âł
ç
ÂŻ
è
ÂŞ
ÂŻ
Ä
ç
ÂŻ
è
ÂŞ
ĂŠ
Âľ
ĂŞ
ÂŽ
ÂŻ
Ç
Š
¡
ÂŻ
Ã
ĂŠ
Âś
ĂŞ
À
¨
ÂŹ
Š
¨
ÂŤ
¨
ÂŚ
À
¨
ÂŹ
¨
ÂŹ
Š
ÂŞ
¨
ÂŤ
ÂŚ
¨
À
¨
ÂŞ
¨
Á
ÂŞ
Š
ÂŚ
Š
Š
¨
¨
Á
Á
ÂŚ
À
ÂŚ
Š
Š
À
À
´
ÂŻ
­
­
ĂŞ
­
Âł
ĂŞ
­
Ä
ÂŹ
Âą
§
°
­
ÂŞ
ĂŤ
§
ĂŹ
À
Æ
Å
­
Âľ
ÂŹ
Âą
§
°
­
ÂŞ
ç
§
ĂŹ
À
Æ
Å
­
ÂŽ
ĂŞ
Ë
Î
Ê
Ë
Čą
Ë
Í
â
Ø
Ñ
Ø
ĂŁ
ä
À
Š
­
â
Ñ
“
ÂŹ
ȹȹȹ
ĂĽ
Ò
ĂŚ
Čą
Čą
Ð
É
Ê
Ë
Ë
Ì
Í
Î
É
Ê
Ï
Ì
Ê
Ï
Ñ
Ò
Ó
Ô
Õ
Čą
Ö
Ï
×
Ù
Ú
Ï
Ø
Čą
Ì
Ø
ȹȹ
Ð
Ì
Ì
Ï
Ì
Ë
Í
Ì
Û
Audio Interface
R84
R222
C150
U29
J20
U28
C164
C91
L4
C70
C71
C24
C66
C62
R268
TP45
L9
C106
R270
TP61
TP46
TP43
TP42
TP114
R103
TP113
R110
TP63
R111
TP69
TP60
TP118
TP64
C61
R112
R113
R116
R119
R99
TP117
TP23
TP70
TP71
TP115
R274
TP66
R93
R30
C115
R29
L8
R17
C112
C13
L6
L5
L20
C11
C10
C64
J8
L19
L18
TP25
R46
R203
R204
S9
OPEN
DESCRIPTION
INT. BOOT
OPEN
CLOSE
CLOSE OPEN
BOOT - uSD
OPEN
CLOSE
RESERVED
BOOT - SD
CLOSE
CLOSE CLOSE
BOOT - SATA
CLOSE CLOSE
BOOT - FUSES
CAN2
R140
X31
SER DOWNLOAD
R83
OPEN
J27
R87
TP29
R205
TP30
TP28
TP33
TP31
TP26
TP27
TP92
POS 2
C178
U34
C179
R246
R5
R61
R90
J9
U44
JP5
ETHERNET 2 J7
C123
C124
JP4
CAN1
CAN1 TERMINATION
S8
ON
ON
S9
JP12
U8
J17
U33
12
C117
R104
C118
U13
12
R100
ON=
WLAN DISABLE
C121
C122
P15
R32
C171
C18
BOOT CONF
C119
C170
R141
R121
R66
R65
R92
R79
R247
X18
R49
CAMERA 1
C120
R211
R96
IDENT
X15
R45
CAN2 TERMINATION
X16
C132
LE12
P13
PERIPHERAL CONNECTOR
P21
WLAN SECONDARY
R209
C17
R101
C12
L21
R218
R207
TP36
TP35
TP91
TP57
TP82
TP87
TP89
TP88
TP58
POS 1
X21
LBL1
R13
L22
R206
OPEN
C131
R151
R152
TP68
TP86
TP90
POS 2
OPEN
C89
S5
L7
C114
R27
C113
C65
C125
C5
C100
C110
H9
DESCRIPTION
BOOT - FLASH
OPEN
U32
C116
TP37
TP38
TP49
TP52
S8
POS 1
TP62
R293
R255
TP48
TP47
R265
R44
C54
R25
C99
C98
U30
CAMERA 2
R213
LE49
USER
L10
R47
MICRO SD
X14
L24
L25
R37
U41
R201
R202
R253
R198
U4
+ C111
C68
U40
C67
U35
C102
R16
C2
C1
R215
R214
R173
R196
R193
C126
J11
J10
L26
R35
S10
R63
R62
R122
R135
LE51
R102
R154
R153
S3
BUTTON 1
RESET
R184
C161
C155
C159
C151
R88
R89
TP74
TP72
TP75
R285
TP73
R190
C55
R8
Y1
XBEE MODULE
R57
C84
R195
ETHERNET 1
R264
R263
R262
R261
R260
R259
R258
R257
R256
R292
R162
C168
J1
X29
C107
C9
C196
C197
ON=AUTOBOOT
JP3
R172
R36
R208
C72
LED 2
R59
C15
S12
C94
U56
R197
C194
TP41 TP39
ASSOC
LED 1
R12
Microphone
Connector,
J15
C69
C192
U54
R183
C187
C190
SD/MMC
R216
C19
R127
POWER
X7
USB OTG
USB HOST
R38
U43
R271
R78
R6
R76
R64
R91
C158
R188
C169
R28
C43
L3
R10
C172
MICRO
S13
R192
U53
R128
R229
U38
C38
R131
LE50
U27
U7
C167
R52
C127
J15
U39
DIGI
INTERNATIONAL
R174
R69
R60
R33
C48
C49
C134
U42
U55
U23
C189
U52
U51
V10
C195
U25
R136
R120
U47
J6
R85
C108
J24
C130
R51
L16
C8
U1
U5
C186
C52
C188
C191
C193
O2
V11
R191
U19
U37
O1
R42
J12
C59
R171
U36
U12
C57
C28
C27
C50
X28
R187
Y3
C95
U3
R132
C22
C14
R280
R290
CONNECTCORE i.MX53 MODULE
C4
C58
R254
U31
DISABLED
ACTIVE
R217
R220
U14
TERMINATION
RS422/485
C101
RS232
R269
R273
R266
DISABLED
4-WIRE
U18
U26
U20
U48
R31
C45
LINE IN
R39
C86
R20
U10
L27
AUTO PWR DWN ACTIVE
2-WIRE
RS485 MODE
R221
MODE
L12
UART3 (TTL)
R199
C128 C129
R176
LINE OUT
R181
R189
C3
R105
SATA
C63
U49
R279
R288
R278
R287
R277
R117
U16
U22
C56
OFF/OPEN
C53
1-WIRE
C149
TP44
C46
C41
C147
C40
R276
R133
LE48
C148
R54
C145
+ C109
R124
LE63
C26
ON/CLOSE
R134
R75
LE62
1234
AUDIO
Line-In
Connector,
J12
J18
TP137
TP81 TP80 TP78 TP79 TP24
KEYPAD
R291
LE47
J5
C16
C88
R108
C83
H3
ON
X19
C20
C93
R34
POS DESCRIPTION
RXD
R118
C42
U11
TP85 TP84 TP83
TP67 TP116
R82
R129
R125
R73
TXD
U17
JP10
U6
C87
R107
RN2
R286
R53
C96
P2
X20
R272
DIGITAL I/O
J2
R275
H1
R74
LE61
U9
C34
J3
R289
JP1
R23
R72
LE59
S7
C39
U24
X30
C97
LE44
S6
C33
X30
C36
C32
L29
C21
X45
12
LE46
R77
P19
POE MODULE
POE MODULE
JTAG
ON=ENABLE
COIN CELL
LE45
R43
PWM
R231
Q2
P20
X13
LE43
LE60
C51
I2C
C85
L17
C82
TP77
ON
UART2 STATUS
R41
R3
TP76
RXD
R71
U21
C37
C31
X27
R1
P14
TOUCH SELECTION
P23
P22
SPI
D1
R138
LE42
LE58
R109
P24
R106
LE40
R56
R58
R86
C81
R137
R142
U50
R143
TXD
R4
R123
R55
LE41
LE57
R114
C30
X27
C29 C35
J4
BATT
R97
UART1 STATUS
C163
R48
R2
C176
C175
C174
C154
L1
C133
C90
C80
C79
C135
R126
R139
D6
D5
U2
R7
UART1 (CONSOLE)
R158
C25
R21
R67
C78
R40
J13
J23
C60
U61
L11
C166
JP2
+3.3V_MOD
R24
R9
R70
C165
ON=SJC-ONLY
JP20
R18
P12
TP20
TP93
C23
R68
L23
JP6
Line-Out
Connector,
J18
R159
R50
ON=
ENABLE EXT BATT
C105
UART2 (MEI)
C44
+3.3V_JS
R130
EXT BATT
P29
U15
C47
WLAN PRIMARY
P1
C157 R177
TP22
TP21
R179
R178
U45
U57
VGA
C6
C7
R26
U46
R15
U58
R182 C153
R22
P4
PARALLEL LCD
C152
R14
R19
V2
R180
R11
L30
C156
R81
R80
R185
R186
R282
R281
R284
R283
C104
R232 C177
R175
R227
X32
X24
9V-30VDC
C103
LVDS
LCD
TP19
C160
L28
TP51
V5
MAIN POWER
R98
C162
R95
LE6
R228
V6
R194
R230
OFF
J19
HDMI
+5V
LE7
ON
LE4
LE8
R94
TP65
+3.3V
VCHRG VBATT
S2
S2
POWER
BUTTON 2
The development board provides an audio interface with line in, line out, and microphone in.
The Freescale SGTL5000 audio CODEC on the development board is controlled through I2C
port 3 of the ConnectCore for i.MX53 module. Digital audio data is sent/receive between the
audio CODEC and the module through the I2S interface (AUD5 channel of the i.MX53
AUDMUX).
ÂĄ
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è
Ü
Čą
Ý
Þ
ß
Ý
Čą
Ă 
Čą
Ë
Î
Ì
Ï

š
Ă´
Ë
½
Ăľ
Î
Ê
Ăś
Âź
á
–
ž
Æ
²
Ë
â
Ñ
ĂĄ
Ñ
š
ÂĄ
ÂŹ
Čą
Ë
¨
Æ
Í
â
Ø
Ñ
Ø
ĂŁ
ä
ø
§
ÂŻ
Á
ÂŤ
ÂŽ
´
´
´
Ăš
Ă­
´
ĂŽ
Ăş
ĂŻ
­
ÂĽ
ÂĽ
½
š
¤
¤
Ă°
Ăą
ò
“

¤
Ăł
è
ȹȹȹ
ĂĽ
Ò
ĂĽ
Čą
Čą
Ð
É
Ê
Ë
Ë
Ì
Í
Î
É
Ê
Ï
Ì
Ê
Ï
Ñ
Ò
Ó
Ô
Õ
Čą
Ö
Ï
×
Ø
Ù
Ú
Ï
Čą
Ì
Ø
ȹȹ
Ð
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Ì
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Û
Three stereo audio jacks are provided on the development board:
„J18
connector for LINE-OUT
„J12
connector for LINE-IN
„J15
connector for microphone
Line-out Connector Pinout, J18
Ăź
Ă˝
Ăž
Ăż
Ă˝
Ăž
Line-in Connector Pinout, J12
Ăź
Ă˝
Ăž
Ăż
Ă˝
Ăž
Microphone Connector Pinou, J15
Ăź
Ă˝
Ăž
Ăż
Čą
Ý
Þ
ß
Ý
Čą
Ă 
Čą
Ë
Î
Ì
Ï
Ë
Î
Ê
Ë
â
Ñ
ĂĄ
Ñ
Čą
Ë
Í
â
Ø
Ñ
Ø
ĂŁ
ä
Ăž
Ü
Ă˝
ȹȹȹ
ĂĽ
Ò
Ăť
Čą
Čą
Ð
É
Ê
Ë
Ë
Ì
Í
Î
É
Ê
Ï
Ì
Ê
Ï
Ñ
Ò
Ó
Ô
Õ
Čą
Ö
Ï
×
Ù
Ú
Ï
Ø
Čą
Ì
Ø
ȹȹ
Ð
Ì
Ì
Ï
Ì
Ë
Í
Ì
Û
Camera Interfaces
C176
C175
C174
C154
R84
R222
C150
U28
U29
C164
L4
C70
C71
C24
C66
C62
R268
ETHERNET 1
L9
C106
TP45
TP46
TP43
TP42
X7
R270
TP61
R103
TP113
R110
TP63
R111
TP69
TP60
TP118
TP64
TP117
R85
R93
R30
C115
R29
L8
C113
R17
C112
C11
C13
C10
C65
R46
R203
R204
TP29
TP26
R205
TP25
TP30
TP31
DESCRIPTION
INT. BOOT
CLOSE
RESERVED
CLOSE
BOOT - SD
CLOSE
CLOSE
CLOSE
BOOT - SATA
CLOSE
BOOT - FUSES
SER DOWNLOAD
R83
OPEN
CLOSE
CAN2
R140
J27
X31
C179
R246
R5
R61
R90
R49
CAMERA 1
C120
C119
BOOT CONF
J9
JP5
ETHERNET 2 J7
C123
C124
JP4
CAN1
CAN1 TERMINATION
S8
ON
ON
S9
JP12
U8
C118
R104
U13
12
R100
ON=
WLAN DISABLE
J17
U33
12
C117
P21
R45
X15
R211
C18
C121
C122
P15
R32
C171
X16
C132
SD/MMC
X18
U44
C170
CAMERA 2
IDENT
R63
R62
POS 2
C178
U34
LE12
P13
PERIPHERAL CONNECTOR
WLAN SECONDARY
R209
C17
R151
R152
R101
TP27
OPEN
OPEN
C131
BUTTON 1
TP28
TP91
TP92
TP36
TP35
TP33
TP57
TP82
TP87
TP88
TP58
TP68
TP86
TP37
TP38
TP49
TP90
POS 1
S9
OPEN
BOOT - uSD
CAN2 TERMINATION
LBL1
R13
L18
R87
R44
C54
TP62
TP89
R293
TP52
TP47
R265
TP48
R25
R255
C116
POS 2
OPEN
DESCRIPTION
BOOT - FLASH
C89
S5
L5
L20
R206
CLOSE
OPEN
OPEN
R141
R121
R66
R65
R92
R79
R247
USER
S8
POS 1
OPEN
U32
X21
R96
R135
LE51
LE49
R154
R153
S3
C99
C98
U30
MICRO SD
R57
J8
L6
R47
S10
X14
C12
L19
R264
R263
R262
R261
R260
R259
R258
R257
R256
R292
R162
C168
L12
J1
X29
L7
L22
L21
R218
R208
L10
C114
R27
C110
H9
R271
L24
L25
R35
R207
R197
U31
C64
U4
U14
U41
C125
C126
+ C111
C68
C67
U35
C102
R198
C5
U56
C194
R16
C2
C1
R215
R214
R173
R196
C55
R8
Y1
J10
L26
R37
U42
C94
C192
R201
R202
R253
R183
R36
J11
USB OTG
USB HOST
R38
U43
C69
C100
U54
R193
U53
C187
C190
U40
C134
C101
C59
XBEE MODULE
LED 2
C84
R102
C61
R112
R113
R116
R119
R99
TP114
TP115
R274
TP66
TP65
TP23
TP70
R282
R281
R284
R283
U52
C107
ASSOC
R59
RESET
J20
C161
C155
C159
C151
R88
TP74
TP71
TP72
TP75
TP73
U51
R229
U38
R192
C72
R213
C19
C9 R122
C196
C197
JP3
ON=AUTOBOOT
R195
C189
R78
R6
R76
R64
R91
R216
R10
C158
R188
R172
C95
U3
TP41 TP39
LE50
LED 1
C15
S12
C4
C58
R254
U55
U23
R136
R128
U36
R28
C43
L3
R174
DIGI
INTERNATIONAL
R69
R60
C172
C169
R31
C45
LINE IN
R33
C48
MICRO
U27
U7
R12
R52
C127
J15
U39
R127
POWER
C86
R20
C108
C167
S13
C195
U25
C186
R120
U47
J6
C49
U1
U5
R131
C188
C191
C193
O2
V10
C52
C38
C57
O1
V11
X28
J24
C130
R51
J12
R105
SATA
U10
R171
R190
U19
U37
U12
C50
U18
U26
U20
C28
C27
C56
R217
R220
CONNECTCORE i.MX53 MODULE
R132
C53
R117
R118
U16
U22
R187
Y3
U49
C46
C22
L16
C8
C145
C63
R269
R273
R266
DISABLED
R42
TP44
L27
DISABLED
4-WIRE
ACTIVE
R221
ACTIVE
2-WIRE
TERMINATION
C41
U48
C14
R285
JP1
R23
AUTO PWR DWN
RS485 MODE
R134
R75
LE62
C26
UART3 (TTL)
R199
C128 C129
R176
LINE OUT
R181
R189
C3
R39
L29
C21
R231
S6
1-WIRE
C149
R108
+ C109
R124
1234
C147
C40
R276
R133
LE48
C148
R54
TP137
TP81 TP80 TP78 TP79 TP24
R82
R129
R125
RS422/485
AUDIO
J18
TP67 TP116
KEYPAD
R279
R288
R278
R287
R277
R74
RS232
J5
C16
C88
C83
R291
OFF/OPEN
MODE
LE47
U17
JP10
U6
P2
X20
H3
ON/CLOSE
ON
X19
C20
C87
R107
R34
POS DESCRIPTION
RXD
LE63
C33
U11
C42
C34
TP85 TP84 TP83
R286
R53
C96
C93
R106
RN2
TXD
C39
U24
X30
P19
POE MODULE
R272
DIGITAL I/O
J2
R275
H1
R73
LE60
LE61
U9
X30
C36
C32
C97
LE44
LE46
R77
J3
R280
R290
R56
S7
R72
LE59
LE43
LE45
R43
R89
U50
ON=ENABLE
COIN CELL
12
R71
U21
C37
C31
C51
PWM
C85
X45
R289
ON
I2C
POE MODULE
JTAG
X13
C82
TP76
RXD
SPI
L17
R138
P14
TOUCH SELECTION
P23
P22
P20
C81
R137
R142
Q2
R143
R97
TXD
UART2 STATUS
R41
R3
R86
LE40
LE58
J4
R1
D1
LE42
X27
R109
BATT
R4
R123
R55
LE41
LE57
R114
C30
X27
R58
P24
R184
R2
R48
R67
UART1 STATUS
C90
C80
C79
C135
R126
L1
C133
C29 C35
C60
R139
D6
D5
U2
R7
UART1 (CONSOLE)
R158
C25
R21
C78
R9
R70
R40
J13
J23
UART2 (MEI)
R159
R50
ON=
ENABLE EXT BATT
R24
JP6
C163
JP2
+3.3V_MOD
P12
U61
L11
C166
ON=SJC-ONLY
JP20
R18
TP93
C165
C23
R68
L23
R130
EXT BATT
C105
U57
C44
+3.3V_JS
C162
U45
U58
P29
U15
C47
WLAN PRIMARY
P1
C157 R177
TP22
TP21
R179
TP20
R178
R26
V2
L30
C156
PARALLEL LCD
R182 C153
R22
R81
R80
R185
R186
VGA
C6
C7
U46
R19
R15
R191
C104
R14
TP77
X24
R11
R180 C152
X32
P4
TP19
C160
L28
C103
LVDS
LCD
R232 C177
R175
R227
R98
TP51
V5
MAIN POWER
J19
LE6
R228
V6
LE7
R194
R230
OFF
R95
LE4
ON
9V-30VDC
LE8
R94
C91
+5V
HDMI
+3.3V
VCHRG VBATT
S2
S2
POWER
BUTTON 2
Camera 2
Connector, X16
Camera 1
Connector, X15
The development board provides two camera interfaces connected to the camera sensor
interfaces (CSI) of the i.MX53 CPU. The I2C bus 3 of the ConnectCore for i.MX53 module is
used to configure and control connected cameras.
Two 2x10 pin headers, X15 and X16, are provided on the development board for optional Digi
camera application kits or customer specific camera hardware.
Ü
Čą
Ý
Þ
ß
Ý
Čą
Ă 
Čą
Ë
Î
Ì
Ï
„X15
connector for camera 1
„X16
connector for camera 2
Ë
Î
Ê
Ë
â
Ñ
ĂĄ
Ñ
Čą
Ë
Í
â
Ø
Ñ
Ø
ĂŁ
ä
ȹȹȹ
Ăť
Ò
Þ

Čą
Čą
Čą
Čą
ȹȹ
The camera 2 signals share the functionality in the development board with the bootstrap
interface and with the VGA interface. To avoid conflict between the camera 2/VGA signals
and the bootstrap interface, a delay circuit is provided in the board to disable the camera 2
and the VGA interfaces while the bootstrap configuration is being reading by the i.MX53 CPU.
Once the bootstrap configuration has been read the camera 2 and the VGA interfaces are
enabled. To avoid conflicts between the camera 2 and the VGA interface 0Ù resistors are
used to select the interface to be used. Please refer to the "Configuration Resistors" section
on page 79 for detailed information.
The following table shows the I2C device addresses of the Digi camera application kits:
Ăž
Ă˝
X15 Pinout
Ăź
Ă˝
Ăž
Ăż
Čą
Čą
Čą
Ăž
Ă˝
Ăż
Ăž
Ă˝
Ăź
Čą
Ăž
Ă˝
ȹȹȹ

Čą
Čą
Čą
Čą
ȹȹ
X16 Pinout
Ăź
Ă˝
Ăž
Ăż
Čą
Čą
Čą
Ă˝
Ăž
Ăż
Ăž
Ă˝
Ăź
Čą
Ăž
Ă˝
ȹȹȹ

Čą
Čą
Čą
Čą
ȹȹ
CAN Interface
C176
C175
C174
C154
Q2
R84
R222
C150
U29
L4
C70
C71
C24
C66
C62
R268
L9
C106
R270
TP45
TP46
TP43
TP42
TP114
R103
TP113
R110
TP63
R111
TP69
TP118
TP64
TP60
R99
TP117
C61
R112
R113
R116
R119
TP66
R274
TP115
TP23
TP70
R282
R281
R284
R283
TP71
ETHERNET 1
R93
R30
R102
C115
R29
C13
C10
C11
R46
R205
RESERVED
CLOSE
BOOT - SD
CLOSE
OPEN
BOOT - FUSES
CLOSE
CLOSE
BOOT - SATA
CLOSE
CLOSE
SER DOWNLOAD
CAN2
R83
DESCRIPTION
INT. BOOT
CLOSE
R140
CAN 1,
X31
X31
R87
POS 2
R203
R204
TP29
TP26
OPEN
OPEN
CAMERA 1
C120
C119
BOOT CONF
J9
JP5
ETHERNET 2 J7
C123
C124
JP4
CAN1
CAN1 TERMINATION
ON
ON
S9
JP12
U8
J17
U33
12
C117
C118
R104
U13
12
R100
ON=
WLAN DISABLE
C121
C122
P15
R32
C171
S8
P21
R45
X15
R211
C18
U44
C170
X16
C132
R78
R6
R76
R64
R91
R141
R121
R66
R65
R92
R79
R247
R246
R5
R61
R90
X18
R49
LE12
P13
PERIPHERAL CONNECTOR
WLAN SECONDARY
R209
C17
R151
R152
BUTTON 1
L8
R17
C112
C64
R218
TP25
TP30
TP31
OPEN
BOOT - uSD
C179
R96
R63
R62
TP27
POS 1
C178
U34
J27
DESCRIPTION
BOOT - FLASH
OPEN
CAMERA 2
LBL1
R13
TP28
TP91
TP92
TP58
TP36
TP35
TP33
TP57
TP82
TP87
TP89
TP88
TP90
TP68
TP86
POS 2
OPEN
S9
CLOSE
OPEN
OPEN
U32
C116
TP37
TP38
TP49
POS 1
TP51
TP52
S8
TP62
R293
R255
TP48
TP47
R265
R44
U30
C54
R25
C99
C98
C89
R154
S5
USER
L18
R47
X21
IDENT
R213
LE49
LE51
R153
C84
S3
L5
L20
H9
R206
CAN2 TERMINATION
MICRO SD
X14
R57
J8
L6
S10
LED 2
C12
L19
J1
X29
L22
L21
R35
R208
L7
C114
R27
C110
C113
C65
C125
U41
R271
L10
+ C109
C67
U35
C102
R197
+ C111
C68
U40
R269
R273
R266
C1
R215
R214
R173
C2
R16
C5
U4
R207
R229
U56
C194
C126
R201
R202
R253
R183
C187
C55
R8
Y1
L24
L25
R37
U42
C94
U55
C192
C100
U54
R128
U53
R36
J11
J10
L26
R38
U43
C69
C131
RESET
J20
U28
C151
TP74
TP72
TP61
C134
XBEE MODULE
R135
C9 R122
C196
C197
JP3
ON=AUTOBOOT
R195
U52
C107
R101
R172
U51
R264
R263
R262
R261
R260
R259
R258
R257
R256
R292
L12
R162
C168
R28
C43
R216
R10
C158
R188
C169
R33
C48
MICRO
R192
C72
ASSOC
R59
C15
R52
C127
C19
LED 1
R12
S12
C189
C190
R193 R196
U19
U36
DIGI
INTERNATIONAL
R174
L3
R69
R60
C172
R189
R31
C45
LINE IN
R51
R127
POWER
U23
R136
TP41 TP39
LE50
U27
U7
C167
S13
C195
U25
C186
R198
U37
C57
C38
C27
C28
R131
C188
U1
U5
R120
U47
R187
C130
C49
J15
U39
J24
J6
X7
USB OTG
USB HOST
C108
1-WIRE
Y3
C59
R171
C191
C193
O2
V10
C52
U18
U26
U20
O1
V11
U38
U22
C50
C22
L16
C58
R254
U3
R132
C53
R191
C46
R190
C41
U48
C8
TP73
TP75
TP76
R217
R220
CONNECTCORE i.MX53 MODULE
U31
DISABLED
C95
U14
DISABLED
4-WIRE
ACTIVE
R42
J12
R85
U10
C101
ACTIVE
2-WIRE
TERMINATION
X28
C149
C14
C86
R20
C63
U49
L27
AUTO PWR DWN
RS485 MODE
C4
R221
U12
U16
UART3 (TTL)
R199
C128 C129
R176
LINE OUT
C40
C3
R285
JP1
R23
RS422/485
S6
R117
R118
OFF/OPEN
RS232
R133
LE48
C56
ON/CLOSE
R134
R75
LE62
MODE
1234
C147
R181
R54
TP44
R279
R288
R278
R287
R277
R74
LE47
C148
R39
TP137
R276
R105
SATA
R291
ON
AUDIO
J18
TP81 TP80 TP78 TP79 TP24
KEYPAD
H3
POS DESCRIPTION
RXD
J5
C16
C83
R34
X19
C20
TP67 TP116
R82
R129
R125
R124
TXD
U17
C26
TP85 TP84 TP83
R286
R53
C145
RN2
LE63
U11
C42
C34
U24
X30
C88
R108
P2
X20
R272
DIGITAL I/O
J2
R275
H1
C39
JP10
U6
C87
R107
LE44
R73
LE60
LE61
U9
C36
C33
X30
R77
J3
R280
R290
R56
S7
R72
LE59
LE43
LE46
C32
C96
C93
R88
X45
ON=ENABLE
COIN CELL
LE45
R43
C97
C85
P19
POE MODULE
POE MODULE
JTAG
12
R71
U21
C37
C31
C51
C91
C21
X13
C82
R89
R138
R289
ON
PWM
R106
TP77
RXD
I2C
P20
C81
U50
R143
R137
R142
R86
SPI
R231
R97
TXD
UART2 STATUS
R41
R3
L17
LE42
X27
J4
R1
P14
TOUCH SELECTION
P23
P22
P24
D1
LE40
LE58
R109
BATT
R4
R123
R55
LE41
LE57
R114
C30
X27
C35
R58
P12
U61
R184
R2
R48
R67
R126
L1
C133
C90
C80
C79
C135
U2
R7
C29
C60
R139
D6
D5
UART1 STATUS
UART1 (CONSOLE)
R158
C25
R21
C78
R9
R70
R40
J13
J23
UART2 (MEI)
R159
R50
ON=
ENABLE EXT BATT
R24
JP6
C163
JP2
+3.3V_MOD
WLAN PRIMARY
P1
PARALLEL LCD
L11
C166
ON=SJC-ONLY
JP20
R18
TP93
C165
C23
R68
L23
R130
EXT BATT
U57
C44
+3.3V_JS
C105
C161
C155
U45
U58
P29
U15
C47
C159
R26
V2
L30
C156
C157 R177
TP22
TP21
R179
TP20
R178
C164
R22
R81
R80
R185
R186
VGA
C6
C7
L29
R19
R15
U46
R14
SD/MMC
C104
R11
R182 C153
X32
C162
C160
L28
C103
P4
TP19
R180 C152
R227
R98
LVDS
LCD
R232 C177
R175
LE6
R228
R194
V6
V5
MAIN POWER
X24
9V-30VDC
R230
OFF
J19
HDMI
+5V
LE7
ON
R95
LE4
LE8
R94
TP65
+3.3V
VCHRG VBATT
S2
S2
POWER
BUTTON 2
CAN 2, X21
Čą
Čą
Čą
Čą
ȹȹȹ

Čą
Čą
Čą
Čą
ȹȹ
CAN 1, X31
The CAN 1 connector X31, is a DB-9 male connector. One 120 ohm termination resistor can be
connected to the output lines of the CAN 1 bus. The termination resistor can be connected or
disconnected using the jumper J7. Refer to the “Jumpers” section on page 77 for more
information.
CAN 1 pins are allocated as shown:
CAN 2, X21
The CAN 2 connector X21, is a 2x5 pin header. One 120 ohm termination resistor can be
connected to the output lines of the CAN 2 bus. The termination resistor can be connected or
disconnected using the jumper J9. Refer to the “Jumpers” section on page 77 for more
information.
CAN 2 pins are allocated as shown:
Čą
Čą
Čą
Čą
ȹȹȹ

Čą
Čą
Čą
Čą
ȹȹ
Charger Power Connector
Charger Power
Connector, X24
C176
C175
C174
C154
R84
R222
C150
C70
C71
C24
R268
C66
C62
U29
ETHERNET 1
L9
C61
C106
R270
TP61
TP43
TP42
TP114
R103
TP113
R110
TP63
R111
TP69
TP60
TP118
TP64
X7
R93
R30
C115
R29
C13
C10
C11
R46
S9
OPEN
OPEN
DESCRIPTION
INT. BOOT
BOOT - uSD
OPEN
CLOSE
RESERVED
CLOSE
BOOT - SD
CLOSE
OPEN
BOOT - FUSES
CLOSE
CLOSE
BOOT - SATA
CLOSE
CLOSE
SER DOWNLOAD
R83
R140
J27
DESCRIPTION
BOOT - FLASH
CAN2
C178
U34
X31
R87
POS 2
R203
R204
TP29
TP26
TP27
POS 1
R205
TP25
TP30
TP31
TP28
TP91
TP92
TP36
TP35
TP33
TP57
TP82
TP87
TP89
TP88
TP58
TP68
TP86
TP90
TP37
TP38
TP49
TP62
R293
TP52
TP48
TP47
R265
R44
C54
R25
R255
C116
POS 2
OPEN
CLOSE
OPEN
OPEN
C120
C119
BOOT CONF
J9
ETHERNET 2 J7
C123
C124
JP4
CAN1
CAN1 TERMINATION
S8
ON
ON
S9
JP12
U8
R104
U13
12
R100
C121
C122
P15
R32
LE12
P13
PERIPHERAL CONNECTOR
R209
WLAN SECONDARY
C17
C118
ON=
WLAN DISABLE
J17
U33
12
C117
P21
U44
JP5
C171
C132
C18
R49
CAMERA 1
R45
X15
C170
X18
X16
R211
R141
R121
R66
R65
R92
R79
R247
R246
R5
R61
R90
R63
R62
L18
C179
IDENT
LBL1
R13
C131
R151
R152
S8
POS 1
OPEN
U32
C89
S5
L8
R17
C112
R206
CAN2 TERMINATION
R96
USER
BUTTON 1
C99
C98
U30
CAMERA 2
R213
LE51
LE49
R154
R153
C84
S3
X14
L5
L20
H9
X21
MICRO SD
R57
J8
L6
R47
S10
ASSOC
C12
L19
C107
LED 2
L7
L22
L21
R218
R207
J1
X29
L10
C114
R27
C110
R35
R208
L24
L25
C113
C65
U41
C64
C5
C100
+ C111
C68
U40
C67
U35
C102
C126
U4
R201
R202
R253
R197
C194
R16
Y1
C125
C2
C55
R8
C1
R215
R214
R173
R193 R196
C94
U55
C192
J10
L26
R37
U42
R198
R191
R190
R183
C187
C190
R36
J11
USB OTG
USB HOST
R38
U43
C69
XBEE MODULE
R135
C9 R122
C19
R59
R102
J20
U28
L4
R112
R113
R116
R119
R99
TP23
TP70
TP115
R274
TP117
TP45
TP74
TP71
TP72
TP75
TP73
TP76
R282
R281
R284
R283
TP66
TP46
C134
U56
C72
LE50
LED 1
RESET
R184
C161
C155
C159
C162
C151
R88
C59
R271
R78
R6
R76
R64
R91
R216
C196
C197
ON=AUTOBOOT
R195
U54
R264
R263
R262
R261
R260
R259
R258
R257
R256
R292
L12
R162
C168
R28
C43
C158
R188
JP3
R192
U53
TP41 TP39
R101
R172
C189
U52
R120
DIGI
INTERNATIONAL
L3
R10
C172
C169
R33
C48
MICRO
U27
U7
C15
S12
U23
R136
U51
R128
R131
C195
U25
C186
R229
U38
C38
C57
C28
R174
R60
R31
C45
LINE IN
R51
U39
R12
R52
C127
J15
R85
C108
R127
POWER
U1
U5
V10
C52
C188
C191
C193
O2
U36
U12
U37
U19
R117
C27
C56
O1
V11
U18
U26
U20
C50
X28
C167
S13
C95
R171
R134
R75
LE62
U16
U22
J24
C130
C49
C58
R254
U3
R132
C53
U47
J6
C4
R217
R220
CONNECTCORE i.MX53 MODULE
C46
C41
R187
Y3
C86
R20
U10
U31
DISABLED
C22
L16
C8
U49
U14
DISABLED
4-WIRE
ACTIVE
R42
J12
R105
C63
R269
R273
R266
ACTIVE
2-WIRE
TERMINATION
R133
LE48
U48
C14
TP44
L27
AUTO PWR DWN
RS485 MODE
LE63
C26
UART3 (TTL)
R199
R69
C128 C129
R176
LINE OUT
R181
R189
R39
C145
SATA
C101
S6
R221
1234
1-WIRE
C149
R285
JP1
R23
RS422/485
C147
C40
C3
R108
+ C109
R124
RS232
LE47
C148
R54
R276
R279
R288
R278
R287
R277
R74
OFF/OPEN
MODE
AUDIO
J18
TP137
TP81 TP80 TP78 TP79 TP24
KEYPAD
H3
ON/CLOSE
ON
J5
C16
C88
R34
X19
C20
C87
R107
C83
R291
POS DESCRIPTION
RXD
R118
C42
U11
TP85 TP84 TP83
TP67 TP116
R82
R129
R125
TXD
U17
JP10
U6
C93
R106
RN2
R286
R53
C96
P2
X20
R272
DIGITAL I/O
J2
R275
H1
C39
U24
X30
C97
LE44
R73
LE60
LE61
U9
C34
C33
X30
C36
C32
J3
R280
R290
R56
S7
R72
LE59
LE43
LE46
R77
R89
X45
ON=ENABLE
COIN CELL
LE45
R43
P19
POE MODULE
POE MODULE
JTAG
12
R71
U21
C37
C31
C51
C91
C21
X13
C82
R289
ON
PWM
C85
L17
R138
TP77
RXD
I2C
SPI
P20
C81
U50
Q2
R143
R142
R137
R139
R97
TXD
UART2 STATUS
R41
R3
R86
LE42
X27
J4
R1
D1
LE40
LE58
R109
BATT
R4
R123
R55
LE41
LE57
R114
C30
X27
R58
P14
TOUCH SELECTION
P23
P22
P24
R231
UART1 STATUS
C90
C80
C79
C135
R126
L1
C133
C29 C35
C60
C163
R48
R21
R67
C78
D6
D5
U2
R7
UART1 (CONSOLE)
R158
C25
R159
R50
ON=
ENABLE EXT BATT
J13
J23
R2
U61
L11
C166
JP2
+3.3V_MOD
R24
R9
R70
R40
C165
ON=SJC-ONLY
JP20
R18
P12
TP20
TP93
C23
R68
L23
JP6
UART2 (MEI)
C44
+3.3V_JS
R130
EXT BATT
U15
C47
C105
C157 R177
TP22
TP21
R179
R178
U45
U57
VGA
C6
C7
R26
C164
R15
U58
L29
R22
WLAN PRIMARY
P1
PARALLEL LCD
R182 C153
R14
R19
P29
U46
R11
V2
TP51
C104
L30
C156
R81
R80
R185
R186
R180 C152
X32
X24
P4
TP19
C160
L28
C103
LVDS
LCD
R232 C177
R175
R227
R98
SD/MMC
V5
MAIN POWER
LE6
R228
V6
R95
J19
HDMI
+5V
LE7
R194
R230
OFF
LE4
ON
9V-30VDC
LE8
R94
TP65
+3.3V
VCHRG VBATT
S2
S2
POWER
BUTTON 2
The charger power connector (X24) is a barrel connector for the development board’s 
9-30VDC power supply. The figure below shows the polarity.
Čą
Čą
Čą
Čą
ȹȹȹ
u
Čą
Čą
€

Čą
‚
ƒ
†
„
Čą
„
ȹȹ
‡
Coin Cell Battery
Coin Cell Battery
Holder, H1
C176
C175
C174
C154
R84
R222
C150
J20
U29
L4
C70
C71
C24
C66
C62
R268
L9
C106
TP45
ETHERNET 1
R270
TP61
TP46
TP43
TP42
TP114
R103
TP113
R110
TP63
R111
TP60
TP118
TP64
TP117
X7
C61
R112
R113
R116
R119
R99
R274
TP115
TP23
TP70
TP71
R282
R281
R284
R283
TP66
TP69
R93
R30
R29
L8
+ C109
C11
C13
C10
R218
TP25
POS 2
R203
R204
R46
R205
TP31
TP30
TP29
DESCRIPTION
INT. BOOT
CLOSE
RESERVED
CLOSE
BOOT - SD
CLOSE
CLOSE
CLOSE
BOOT - SATA
CLOSE
BOOT - FUSES
SER DOWNLOAD
X31
R87
OPEN
R83
R140
J27
CLOSE
CAN2
C178
U34
C18
X15
R49
CAMERA 1
C120
C119
BOOT CONF
J9
JP5
ETHERNET 2 J7
C123
C124
JP4
CAN1
CAN1 TERMINATION
S8
ON
ON
S9
JP12
U8
C117
R104
C121
C122
P15
R32
LE12
P13
PERIPHERAL CONNECTOR
WLAN SECONDARY
C17
C118
U13
12
R100
ON=
WLAN DISABLE
J17
U33
12
P21
R45
X16
C132
U44
C171
X18
R211
R141
R121
R66
R65
R92
R79
R247
R246
R5
R61
R90
R63
R62
TP26
OPEN
OPEN
C170
CAMERA 2
LBL1
R13
TP28
TP33
OPEN
BOOT - uSD
TP51
POS 1
TP27
TP92
TP58
TP36
TP35
TP91
TP57
TP82
TP87
TP89
TP88
TP68
TP86
TP90
TP37
TP38
TP49
TP62
R293
R255
TP47
R265
TP52
R25
TP48
R44
C54
DESCRIPTION
BOOT - FLASH
OPEN
C116
POS 2
OPEN
CLOSE
OPEN
OPEN
U32
C89
S5
C131
R151
R152
POS 1
S9
C179
R96
USER
BUTTON 1
U30
S8
R209
R102
R154
R153
C84
S3
C99
C98
CAN2 TERMINATION
IDENT
R213
LE49
LE51
R57
L18
R47
X21
MICRO SD
X14
L5
R206
S10
LED 2
J8
L6
J1
X29
R264
R263
R262
R261
R260
R259
R258
R257
R256
R292
C168
L12
R162
R28
C12
L19
L20
H9
R208
L7
L22
R27
R17
R35
R271
L10
L21
C112
R197
C110
C113
U41
C64
C5
C100
U4
+ C111
C115
C68
C67
C65
C126
C125
C1
C2
U56
C194
R16
R215
R214
R173
C55
R8
Y1
L24
L25
R37
U42
C94
U55
C192
R207
R183
C187
R36
R201
R202
R253
R128
U54
C190
U35
C102
C69
J10
L26
R38
U43
J11
USB OTG
USB HOST
C114
C134
U40
C59
XBEE MODULE
ASSOC
R59
RESET
R184
U28
C151
R88
TP74
TP72
TP73
TP75
TP76
R285
U53
R229
U38
U52
C107
R135
C9 R122
C197
JP3
ON=AUTOBOOT
R195
C189
U51
C72
R101
R172
C186
R192
R78
R6
R76
R64
R91
R216
R10
C158
R188
R33
C48
C196
C19
R12
S12
U23
R136
TP41 TP39
LE50
LED 1
C15
POWER
C195
U25
R193 R196
U19
U36
R131
C43
L3
R174
R60
C172
C169
R31
C45
DIGI
INTERNATIONAL
R69
C128 C129
R176
LINE OUT
R181
R189
LINE IN
R51
MICRO
U27
U7
R127
R52
C127
J15
U39
J24
C167
S13
U1
U5
R120
U47
J6
C49
R85
C108
R187
C130
J12
C95
R171
C188
C191
C193
O2
V10
C52
C38
C57
C28
C27
O1
V11
U18
U26
U20
C50
R198
U37
R117
R118
U16
U22
1-WIRE
Y3
C4
C58
R254
U3
R132
C53
R191
C46
R190
C41
U12
LE48
C56
R217
R220
CONNECTCORE i.MX53 MODULE
U31
S6
DISABLED
C22
L16
C86
R20
U10
U14
DISABLED
4-WIRE
ACTIVE
R133
U48
C8
U49
C101
ACTIVE
2-WIRE
TERMINATION
R42
R105
SATA
C63
R269
R273
R266
AUTO PWR DWN
RS485 MODE
X28
C149
C14
TP44
L27
R221
1234
C147
C3
R39
TP137
R276
R279
R288
R278
R287
R277
RS422/485
R134
R75
LE62
C26
UART3 (TTL)
R199
J18
R280
R290
JP1
R23
RS232
AUDIO
C40
TP81 TP80 TP78 TP79 TP24
R82
R129
R125
R124
R73
LE60
R74
OFF/OPEN
MODE
LE63
C33
U11
C42
C34
TP85 TP84 TP83
TP67 TP116
KEYPAD
R291
ON/CLOSE
ON
LE47
C148
R54
C88
C145
C83
H3
POS DESCRIPTION
RXD
J5
C16
C87
R108
R34
X19
C20
C93
R107
RN2
TXD
U17
JP10
U6
P2
X20
R272
DIGITAL I/O
J2
R275
H1
R289
R56
R72
LE59
S7
J3
R286
R53
C96
LE44
C39
U24
X30
C91
C21
X45
LE43
LE61
U9
X30
C36
C32
C97
C85
P19
POE MODULE
POE MODULE
JTAG
X13
C82
R89
U50
R138
12
LE46
R77
PWM
R106
ON=ENABLE
COIN CELL
LE45
R43
I2C
SPI
P20
TP77
ON
R71
U21
C37
C31
C51
C163
L17
C81
R137
R142
Q2
R143
RXD
UART2 STATUS
R41
R3
P14
TOUCH SELECTION
P23
P22
P24
D1
LE42
X27
R1
R86
LE40
LE58
R109
P12
U61
R231
TXD
R4
R123
R55
LE41
LE57
R114
C30
X27
C35
R58
R48
R67
R2
BATT
R97
UART1 STATUS
C90
C80
C79
C135
R126
L1
C133
C29
C60
R139
D6
D5
U2
R7
UART1 (CONSOLE)
R158
C25
R21
C78
R9
R70
R40
J13
J23
UART2 (MEI)
R159
R50
ON=
ENABLE EXT BATT
R24
JP6
C166
JP2
+3.3V_MOD
WLAN PRIMARY
P1
PARALLEL LCD
L11
J4
ON=SJC-ONLY
JP20
R18
TP93
C165
C23
R68
L23
R130
EXT BATT
U57
C44
+3.3V_JS
C105
C161
C155
U45
U58
P29
U15
C47
C159
R26
V2
L30
C156
C157 R177
TP22
TP21
R179
TP20
R178
C164
R22
R81
R80
R185
R186
VGA
C6
C7
L29
R19
R15
U46
R14
SD/MMC
C104
R11
R182 C153
X32
C162
C160
L28
C103
P4
TP19
R180 C152
R227
R98
LVDS
LCD
R232 C177
R175
LE6
R228
R194
V6
V5
MAIN POWER
X24
9V-30VDC
R230
OFF
J19
HDMI
+5V
LE7
ON
R95
LE4
LE8
R94
TP65
+3.3V
VCHRG VBATT
S2
S2
POWER
BUTTON 2
The development board provides a coin cell battery to back up the module’s integrated RTC
while main power is disconnected. Jumper J3 connects/disconnects the coin cell power
source.
ˆ
Čą
‰
Š
‹
‰
Čą
Œ
Čą
Ž

„
Čą
Ž
„


ȹȹȹ
‘
’
u
Čą
Čą
€

Čą
‚
ƒ
†
„
Čą
„
ȹȹ
‡
Digital IO Interface
Digital I/O
Connector, X45
C176
C175
C174
C154
Čą
‰
Š
‹
‰
Čą
Čą
Ž

Čą
Ž


R84
R222
C150
U28
U29
C164
C91
L4
C70
C71
C24
C66
C62
R268
ETHERNET 1
L9
C106
TP45
X7
R270
TP61
TP43
TP42
TP114
R103
TP113
R110
TP63
R111
TP69
TP60
TP118
TP64
TP117
R85
C61
R112
R113
R116
R119
R99
R274
TP115
TP23
TP70
TP71
R282
R281
R284
R283
TP66
TP46
TP74
TP72
TP75
TP73
TP76
R93
R30
C115
R29
C13
C114
C113
R17
C11
C10
R218
TP25
R46
R203
R204
TP29
TP26
R205
TP30
TP31
OPEN
DESCRIPTION
INT. BOOT
BOOT - uSD
OPEN
CLOSE
RESERVED
CLOSE
CLOSE
OPEN
BOOT - SD
CLOSE
CLOSE
CLOSE
BOOT - SATA
CLOSE
R83
BOOT - FUSES
SER DOWNLOAD
X31
R87
OPEN
CAN2
R140
J27
CLOSE
R49
CAMERA 1
C120
C119
BOOT CONF
J9
JP5
ETHERNET 2 J7
C123
C124
JP4
CAN1
CAN1 TERMINATION
S8
ON
ON
S9
JP12
U8
R104
U13
12
R100
C121
C122
P15
R32
LE12
P13
PERIPHERAL CONNECTOR
WLAN SECONDARY
R209
C118
ON=
WLAN DISABLE
J17
U33
12
P21
U44
R45
X15
C171
C18
C170
X18
X16
C132
R211
R141
R121
R66
R65
R92
R79
R247
R246
R5
R61
R90
R63
R62
POS 2
S9
OPEN
C117
LBL1
R13
TP28
TP33
POS 1
TP27
TP92
TP58
TP36
TP35
TP91
TP57
TP82
TP87
TP89
TP88
TP68
TP86
TP90
TP37
TP38
TP49
TP52
POS 2
OPEN
DESCRIPTION
BOOT - FLASH
OPEN
C116
TP62
R293
R255
TP48
R25
TP47
R265
R44
C54
S8
POS 1
OPEN
U32
C178
U34
C17
R151
R152
C99
C98
U30
C89
R154
S5
L18
R47
CAN2 TERMINATION
IDENT
R213
LE49
LE51
R153
USER
L5
R206
C179
R96
R135
C9 R122
C196
S3
J8
L6
X21
MICRO SD
X14
C12
L19
J1
X29
L7
L22
L20
H9
R208
L10
L21
R35
R271
L8
+ C111
C68
C67
R27
C110
C112
R197
U31
C65
U4
C64
C5
C100
U41
C125
C126
L24
L25
R37
U14
R16
C2
C1
R215
R214
R173
R193 R196
C55
R8
Y1
U56
C194
R36
U42
C94
U55
C192
R207
R183
C187
C190
U35
C102
C69
J10
L26
R38
U43
J11
USB OTG
USB HOST
+ C109
C134
U40
C59
R201
R202
R253
R229
R128
U54
CAMERA 2
ASSOC
R57
C84
J20
C161
C155
C151
R88
C95
S10
LED 2
BUTTON 1
„
C4
C58
XBEE MODULE
C131
U53
C107
R101
„
U52
R78
R6
R76
R64
R91
R216
R10
C197
JP3
R195
ON=AUTOBOOT
C19
R59
RESET
U51
C72
LE50
LED 1
R102
R192
R264
R263
R262
R261
R260
R259
R258
R257
R256
R292
C168
R162
R28
C43
L3
C158
R188
C169
R33
C48
U27
R12
R172
Œ
C189
TP41 TP39
U47
U7
C15
POWER
S12
ˆ
DIGI
INTERNATIONAL
R174
R69
R60
C172
R51
MICRO
S13
R52
C127
J15
U39
R127
C130
C49
C86
R20
C108
C167
J6
U23
R136
R120
C22
L16
C8
R105
U10
R254
U3
R198
U19
U38
C38
R131
C195
U25
C186
R191
U37
U36
V10
C52
U1
U5
R42
J12
U49
R171
C188
C191
C193
O2
R190
U12
C57
C28
C27
O1
V11
U18
U26
U20
C50
X28
R187
Y3
R285
R217
R220
CONNECTCORE i.MX53 MODULE
R132
C53
R134
C46
J24
C14
C145
SATA
C101
DISABLED
S6
C41
U48
R31
C45
LINE IN
R39
R108
C63
R269
R273
R266
DISABLED
4-WIRE
ACTIVE
L12
UART3 (TTL)
R199
C128 C129
R176
LINE OUT
R189
C3
TP44
L27
ACTIVE
2-WIRE
TERMINATION
R221
AUTO PWR DWN
RS485 MODE
1-WIRE
C149
R280
R290
JP1
R23
RS422/485
1234
R117
R118
U16
U22
C56
OFF/OPEN
RS232
MODE
C147
R181
C40
TP137
R276
R133
LE48
C148
R54
TP81 TP80 TP78 TP79 TP24
KEYPAD
R279
R288
R278
R287
R277
R74
R75
LE62
C26
ON/CLOSE
AUDIO
J18
C88
C83
R291
ON
LE47
U17
JP10
U6
P2
X20
H3
POS DESCRIPTION
RXD
LE63
C33
U11
C42
C34
TP85 TP84 TP83
TP67 TP116
R82
R129
R125
R124
R73
LE60
TXD
J5
C16
C87
R107
R34
X19
C20
C96
C93
R106
RN2
R286
R53
P19
POE MODULE
R272
DIGITAL I/O
J2
R275
H1
C39
U24
X30
J3
R289
R56
S7
R72
LE59
LE43
LE61
U9
X30
C36
C32
C97
LE44
LE46
R77
L29
C21
ON=ENABLE
COIN CELL
LE45
R43
R89
U50
X45
12
R71
U21
C37
C31
C51
PWM
C85
POE MODULE
JTAG
X13
C82
TP77
ON
I2C
P20
C81
R137
R142
Q2
R143
RXD
SPI
L17
R138
P14
TOUCH SELECTION
P23
P22
R231
R97
TXD
UART2 STATUS
R41
R3
R86
LE40
LE58
J4
R1
P24
D1
LE42
X27
R109
BATT
R4
R123
R55
LE41
LE57
R114
C30
X27
C35
R58
P12
U61
R184
R2
R48
R67
UART1 STATUS
C90
C80
C79
C135
R126
L1
C133
C29
C60
R139
D6
D5
U2
R7
UART1 (CONSOLE)
R158
C25
R21
C78
R9
R70
R40
J13
J23
UART2 (MEI)
R159
R50
ON=
ENABLE EXT BATT
R24
JP6
C163
JP2
+3.3V_MOD
WLAN PRIMARY
P1
PARALLEL LCD
L11
C166
ON=SJC-ONLY
JP20
R18
TP93
C165
C23
R68
L23
R130
EXT BATT
U57
C44
+3.3V_JS
C105
C159
U45
U58
P29
U15
C47
C162
R26
V2
L30
C156
C157 R177
TP22
TP21
R179
TP20
R178
R182 C153
R22
R81
R80
R185
R186
VGA
C6
C7
U46
R19
R15
R180 C152
R14
TP51
C104
R11
P4
TP19
C160
L28
C103
X32
X24
R232 C177
R175
R227
R98
LVDS
LCD
SD/MMC
V5
MAIN POWER
LE6
R228
R194
V6
R95
9V-30VDC
R230
OFF
J19
HDMI
+5V
LE7
ON
LE4
LE8
R94
TP65
+3.3V
VCHRG VBATT
S2
S2
POWER
BUTTON 2
ȹȹȹ
‘
“
u
Čą
Čą
€

Čą
‚
ƒ
†
„
„
Čą
‡
ȹȹ
Digital I/O Connector, X45
The development board provides a 2x5 position pin header, X45, to access four on-chip digital
GPIOs of the i.MX53 CPU.
š
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œ
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ÂŞ
›
ÂŤ
¸
ÂŹ
š
Âľ
ÂŹ
š
Âł
Ÿ
ÂĄ
š
¢
ÂŁ
¤
­
ÂŹ
ÂŽ
ÂŻ
­
°
ÂŹ
ÂŽ
Âą
²
ÂŞ
­
ÂŹ
ÂŽ
ÂŞ
­
°
ÂŹ
ÂŽ
Âť
­
ÂŹ
ÂŽ
¸
­
°
ÂŹ
ÂŽ
Âą
²
ÂŞ
­
ÂŹ
ÂŽ
Âľ
­
°
ÂŹ
ÂŽ
Âą
²
ÂŞ
Âł
ÂĽ
ÂŚ
Ÿ
ž
´
Âľ
Âś
ÂŞ
Âł
´
Âľ
Âś
ÂŞ
Âą
´
Âľ
Âś
ÂŞ
Âł
¡
Âź
´
Âľ
Âś
ÂŞ
Âł
¡
§
¨
§
Š
§
¡
²
Âą
Âł
¡
Âş
ÂŤ
Âą
œ
Âş
ÂŤ
Âź
ž
ÂŹ
š
Âş
Âť
ÂŤ
ÂŹ
½
­
š
ÂŤ
­
š
ÂŤ
ÂŻ
¡
ž
­
š
ÂŤ
­
š
ÂŤ
ÂŻ
¡
On the development board, GPIO6_15, GPIO6_16 and GPIO7_6 are connected to the XBee
interface. When using these signals as digital I/O, the XBee interface should not be used.
•
ˆ
Čą
‰
Š
‹
‰
Čą
Œ
Čą
Ž

The digital I/O interface is not-protected against ESD, over-voltage or inverse polarity.
Care must be taken when using these signals.
–
—
„
˜
™
Čą
Ž
„


ȹȹȹ
‘
”
u
Čą
Čą
€

Čą
‚
ƒ
†
„
Čą
„
ȹȹ
‡
Ethernet 1 Interface
C176
C175
C174
C154
Q2
U29
J20
U28
C151
C164
L4
C70
C71
C24
C66
C62
R268
L9
C106
R270
TP61
TP45
TP43
TP42
TP114
R103
TP113
R110
TP63
R111
TP69
TP60
TP118
TP64
TP117
C61
R112
R113
R116
R119
R99
R274
TP115
TP23
TP70
TP71
R282
R281
R284
R283
TP66
TP46
TP74
R93
R30
C115
R29
L8
R17
C112
C11
C13
L18
R46
R203
R204
TP29
POS 2
R205
TP25
TP30
TP31
TP26
POS 1
TP27
TP92
OPEN
OPEN
DESCRIPTION
INT. BOOT
BOOT - uSD
OPEN
CLOSE
RESERVED
BOOT - SD
CLOSE
BOOT - SATA
CLOSE CLOSE
OPEN
R140
J27
BOOT - FUSES
X31
SER DOWNLOAD
CAN2
C178
U34
C179
CAMERA 1
C120
C119
BOOT CONF
J9
ETHERNET 2 J7
C123
C124
JP4
CAN1
CAN1 TERMINATION
S8
ON
ON
S9
JP12
U8
R104
U13
12
R100
C121
C122
P15
R32
LE12
P13
PERIPHERAL CONNECTOR
WLAN SECONDARY
C17
C118
ON=
WLAN DISABLE
J17
U33
12
C117
P21
U44
JP5
C171
C132
C18
R49
R45
X15
C170
R141
R121
R66
R65
R92
R79
R247
R246
R5
R61
R90
X18
X16
R211
R96
R63
R62
TP28
TP91
TP33
TP82
TP57
TP36
TP88
TP58
DESCRIPTION
BOOT - FLASH
R83
CLOSE CLOSE
TP68
TP35
CLOSE
OPEN
TP86
POS 2
OPEN
S9
CAN2 TERMINATION
IDENT
R213
LE49
R101
C10
R207
R218
R206
R87
C116
TP87
TP89
OPEN
TP90
POS 1
OPEN
U32
TP37
TP38
TP49
TP52
S8
TP62
R293
R255
TP47
R265
TP48
R25
C54
R44
U30
CAMERA 2
LBL1
R13
L5
L20
H9
X21
MICRO SD
C131
R151
R152
C99
C98
C89
S5
J8
L6
R209
R102
USER
C12
L19
R47
S10
X14
L22
R264
R263
R262
R261
R260
R259
R258
R257
R256
R292
R162
C168
J1
X29
L7
L21
R35
R208
L10
C114
R27
C110
C113
C65
U31
U41
C64
U4
+ C111
C68
U40
C67
U35
C102
R16
C5
C100
C192
R197
C194
C126
C125
C2
C1
R215
R214
R173
C55
R8
Y1
L24
L25
R37
U42
C94
R201
R202
R253
R229
R128
R183
R36
J11
J10
L26
R38
U43
C69
XBEE MODULE
R135
C9 R122
LE51
R153
S3
BUTTON 1
RESET
R184
C161
C155
C159
C162
R84
R222
C150
C134
U56
CLOSE
R57
C84
R195
ON=AUTOBOOT
JP3
R172
C59
R271
C107
LED 2
R59
C15
R52
C127
U54
C72
ASSOC
R154
C197
R33
C48
C196
C19
LED 1
R12
S12
R192
U53
TP41 TP39
LE50
U27
U7
R127
POWER
C189
U52
R78
R6
R76
R64
R91
C158
R188
C169
R28
C43
R216
R10
C172
DIGI
INTERNATIONAL
L3
R174
R60
R51
MICRO
S13
R136
U51
C187
C190
U55
U23
C186
R120
U47
C167
C130
C49
J15
U39
J24
J6
ETHERNET 1
USB OTG
USB HOST
C108
X28
R187
Y3
C195
U25
R196
U19
U36
U38
C38
R131
C188
U1
U5
V10
C52
C22
L16
C8
C95
R171
C191
C193
O2
V11
R193
U37
O1
R42
J12
C4
C58
R254
U3
R198
U12
C57
C28
C27
C50
U18
U26
U20
1-WIRE
C14
TP72
CONNECTCORE i.MX53 MODULE
R132
C53
U48
R31
C45
LINE IN
R39
TP73
TP75
TP76
R217
R220
U14
DISABLED
ACTIVE
R269
R273
R266
TERMINATION
RS422/485
L27
L12
UART3 (TTL)
R199
R69
C128 C129
R176
LINE OUT
R181
R189
C3
X7
U10
C101
DISABLED
4-WIRE
RS232
R221
AUTO PWR DWN ACTIVE
2-WIRE
RS485 MODE
R191
C46
C147
C149
R85
C63
U49
R279
R288
R278
R287
R277
MODE
R190
C41
AUDIO
J18
C40
R285
JP1
R117
U16
U22
C56
OFF/OPEN
R133
LE48
C148
R54
TP137
TP44
C86
R20
+ C109
R124
LE63
ON/CLOSE
R134
R75
LE62
1234
J5
C16
TP81 TP80 TP78 TP79 TP24
R276
R105
SATA
R291
LE47
U17
C26
TP85 TP84 TP83
TP67 TP116
KEYPAD
H3
ON
X19
C20
Ethernet 1
RJ-45,
X7
C83
R34
POS DESCRIPTION
RXD
R118
C42
U11
J2
R286
R53
C145
P2
X20
R272
DIGITAL I/O
R82
R129
R125
TXD
R74
LE61
U9
C34
J3
R275
H1
C39
U24
X30
C88
R108
RN2
S6
C33
X30
C36
C32
JP10
U6
C87
R107
LE44
R73
LE60
R23
S7
R72
LE59
LE43
LE46
R77
C96
C93
R88
X45
ON=ENABLE
COIN CELL
LE45
R43
C97
C85
P19
POE MODULE
POE MODULE
JTAG
R280
R290
R56
R71
U21
C37
C31
C51
L29
C21
X13
C82
R89
R138
12
UART2 STATUS
R41
PWM
R106
R289
ON
I2C
P20
TP77
RXD
SPI
L17
LE42
X27
R3
R86
LE40
LE58
J4
R1
D1
C81
R137
R142
U50
R143
TXD
R4
R123
R55
LE41
LE57
R114
C30
X27
C29 C35
R109
BATT
R97
UART1 STATUS
R58
P14
TOUCH SELECTION
P23
P22
P24
R231
R126
L1
C133
C90
C80
C79
C135
U2
R7
UART1 (CONSOLE)
C60
R139
D6
D5
C163
R48
R67
R2
U61
L11
C166
JP2
+3.3V_MOD
R24
R9
R70
R40
J13
J23
R158
C25
R21
C78
R18
C165
ON=SJC-ONLY
JP20
R68
L23
JP6
UART2 (MEI)
R159
R50
ON=
ENABLE EXT BATT
C105
TP93
C23
P12
TP20
U57
C44
+3.3V_JS
R130
EXT BATT
U15
C47
WLAN PRIMARY
P1
C157 R177
TP22
TP21
R179
R178
U45
U58
VGA
R26
V2
P29
L30
C156
R81
R80
R185
R186
U46
R22
C6
C7
R182 C153
R19
R15
R180 C152
R14
TP51
C104
R11
PARALLEL LCD
C91
C103
P4
TP19
C160
L28
X32
X24
R232 C177
R175
R227
R98
LVDS
LCD
SD/MMC
V5
MAIN POWER
LE6
R228
V6
R95
J19
HDMI
+5V
LE7
R194
R230
OFF
LE4
ON
9V-30VDC
LE8
R94
TP65
+3.3V
VCHRG VBATT
S2
S2
POWER
BUTTON 2
The development board provides one 8-wire RJ-45 jack with integrated 1:1 transformers and
link/activity LEDs for the Ethernet 1 interface. This interface is attached to the Fast Ethernet
controller (FEC) of the i.MX53. The ConnectCore for Wi-i.MX53 module provides a 10/100
Ethernet PHY chip for this interface.
The Ethernet 1 RJ-45 connector also supports 802.3af (PoE) operation (optional Digi PoE
application kit required).
ˆ
Čą
‰
Š
‹
‰
Čą
Œ
Čą
Ž

„
Čą
Ž
„


ȹȹȹ
‘
‘
Âż
À
Á
Á
Â
Ã
Ä
Âż
À
Å
Čą
Æ
Â
À
Čą
Å
Ç
È
É
Ê
Ë
Čą
Ì
Å
Í
Ï
Ð
Å
Î
Čą
Â
Î
Æ
Â
Â
Å
Â
Á
Ã
ȹȹ
Â
Ñ
Ethernet 1, RJ-45 Connector X7
The table below shows the pinout of the Ethernet 1 RJ-45 connector.
š
›
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
›
ž
œ
Ÿ
Û
Ü
ĂĽ
Þ
ß
ÂĽ
Ÿ
â
Ă 
ĂĄ
§
œ
ç
â
ĂŁ

ä
Ÿ
œ
Û
Ü
ĂĽ
è
Ý
Þ
ĂŚ
ß
ÂĽ
Ÿ
â
â
ĂŠ
§
ĂŞ
ĂŻ
Ă°
ÂŤ
¸
ĂŻ
Ă°
ÂŤ
Âľ
Âź
°
´
°
Ă˝
Ăľ
Ă´
Ăľ
Ăś
Ăą
¡
Âł
°
´
°
Ă˝
Ăľ
Ă´
Ăľ
Ăś
Ăą
¡
Âą
Âť
°
š
Ăą
ò
Ăł
Ă´
Ăľ
Ăś
Ăą
¡
½
°
š
Ăą
ò
Ăł
Ă´
Ăľ
Ăś
Ăą
¡
ÂŤ
Ă°
›
â
ĂŁ
è
ÂŞ
Ă°
´
Ý
ĂŚ

ä
Ÿ
œ
§
ĂŹ
Ă­
ĂŽ
›
ä
ÂŚ
›
ÂĽ
œ
ĂŤ
š
Ăą
ò
Ăł
Ă´
Ăľ
Ăś
Ăą
¡
á
ø
Ăš
Ăş
ĂŻ
Ăť
Ăł
Ăź
Ă˝
Ăž
Ăľ
Ă´
Ăż
Ăł
Ă´
Ăł
š
Ăą
ò
Ăł
Ă´
Ăľ
Ăś
Ăą
¡
á
ø
Ăš
Ăş
ĂŻ
Ăť
Ăł
Ăź
Ă˝
Ăž
Ăľ
Ă´
Ăż
Ăł
Ă´
Ăł
´
°
ÂŤ
Ă˝
°
Ăľ
Ă˝
Ă´
Ăľ
Ăľ
Ă´
Ăś
Ăľ
Ăą
Ăś
¡
Ăą
á
¡
ø
á
Ăš
ø
Ăş
Ăš
Ăą
á
ø
Ăš
Ăş
á
ø
Ăš
Ăş
Ăş
ø
Ăš
Ăş
á
ø
Ăš
Ăş
Ăą
Ăľ
Ăś
Ăą
Ăż
Ăł
Ă´
Ăł
´
°
Ăą
Ăť
Ăť
Ăž
Ă˝
Ăľ
Ă´
´
°
Ăą
Ăť
Ăť
Ăž
Ă˝
Ăľ
Ă´
´
Ăż
Ăł
Ăą
á
´
Ăą
Ăľ
Ăś
Ăą
Ă´
Ăł
°
Ăą
Ăť
Ăť
Ăž
Ă˝
Ăľ
Ă´
°
Ăą
Ăť
Ăť
Ăž
Ă˝
Ăľ
Ă´
The table below shows the description of the Ethernet 1 LEDs.
¨
ĂĄ
§
ĂŤ
ĂŹ
Ă­
ĂŽ
›
ä
ÂŚ
Ăą
š
Ăą
Ă´
Ăť
Ăł
Ò
Čą
Ó
Ô
Õ
Ó
Čą
Ö
Čą
Ø
Ç
×
Ç
Á
Ä
Â
Å
Ăť
Á
Ăą
Ä
Î
Ăą
À
Ç
ÂĽ
œ
Ăź
š
Á
Čą
Ø
Î
Ù
Ú
Á
Ã
È
Ăą
Ă´
ÂŽ
ÂŽ
Ăź
ÂŽ
Ă´
Ăł
­
›
ĂŤ
Ă˝
Ăľ
Ăľ
Ă´
Ă˝
ò
Ăľ
Ăź
Ăź
Ăą
Ă´
Ăą
Ăź
Ăż
Ăą
Ăľ
Ăż
Ăł
Ăť
Ă´
Ăą
Ă˝
Ă´
Ăź
Ăť
Ăł
Ăą
Ă´
Ăľ
Ăť
Ă´
Ăť
Ăł
Ăľ
Ăľ
Ăľ
Ăź
Ăź
Ăť
Ăś
Ăľ
Ăź
Ăź
Ăż
Ăľ
Ăł
Ăź
Ăą
Ă´
Ă´
Ăą
Ă˝
Ăł
Ăź
Ăť
Ăł
Ă´
Ăľ
Ăź
Ăľ
Ăś
Ăą
Ăź
Ăť
Ăą
Ăą
Ă˝
Ă´
Ăą
Ăź
Ăť
Ăľ
Ăź
Ă´
ȹȹȹ
Õ
Ô
Ô

---

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File Type                       : PDF
File Type Extension             : pdf
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Page Count                      : 100
Producer                        : GPL Ghostscript 8.15
Create Date                     : 2012:05:30 09:54:53
Modify Date                     : 2012:05:30 09:54:53
Title                           : 90001270_C (2).PDF
Creator                         : Adobe Acrobat 10.1.1
Author                          : rwhite

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