EZ USB_TRM 001 13670 USB Technical Reference Manual
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- EZ-USB® Technical Reference Manual
- Contents Overview
- Contents
- 1. Introducing EZ-USB®
- Introduction
- 1.1 An Introduction to USB
- 1.2 The USB Specification
- 1.3 Host is Master
- 1.4 USB Direction
- 1.5 Tokens and PIDs
- 1.6 USB Frames
- 1.7 USB Transfer Types
- 1.8 Enumeration
- 1.9 The Serial Interface Engine
- 1.10 ReNumeration™
- 1.11 EZ-USB Architecture
- 1.12 EZ-USB Feature Summary
- 1.13 EZ-USB Integrated Microprocessor
- 1.14 EZ-USB Block Diagram
- 1.15 Packages
- 1.16 Package Diagrams
- 1.17 EZ-USB Endpoint Buffers
- 1.18 External FIFO Interface
- 1.19 EZ-USB Product Family
- 1.20 Document History
- 2. Endpoint Zero
- 3. Enumeration and ReNumeration™
- 4. Interrupts
- 4.1 Introduction
- 4.2 SFRs
- 4.3 Interrupt Processing
- 4.4 USB-Specific Interrupts
- 4.4.1 Resume Interrupt
- 4.4.2 USB Interrupts
- 4.4.2.1 SUTOK, SUDAV Interrupts
- 4.4.2.2 SOF Interrupt
- 4.4.2.3 Suspend Interrupt
- 4.4.2.4 USB RESET Interrupt
- 4.4.2.5 HISPEED Interrupt (FX2LP only)
- 4.4.2.6 EP0ACK Interrupt
- 4.4.2.7 Endpoint Interrupts
- 4.4.2.8 In-Bulk-NAK (IBN) Interrupt
- 4.4.2.9 EPxPING Interrupt (FX2LP only)
- 4.4.2.10 ERRLIMIT Interrupt
- 4.4.2.11 EPxISOERR Interrupt
- 4.5 USB-Interrupt Autovectors
- 4.6 I²C Bus Interrupt
- 4.7 FIFO/GPIF Interrupt (INT4)
- 4.8 FIFO/GPIF Interrupt Autovectors
- 5. Memory
- 6. Power Management
- 7. Resets
- 8. Access to Endpoint Buffers
- 8.1 Introduction
- 8.2 EZ-USB Large and Small Endpoints
- 8.3 High Speed and Full Speed Differences
- 8.4 How the CPU Configures the Endpoints
- 8.5 CPU Access to EZ-USB Endpoint Data
- 8.6 CPU Control of EZ-USB Endpoints
- 8.7 The Setup Data Pointer
- 8.8 Autopointers
- 9. Slave FIFOs
- 9.1 Introduction
- 9.2 Hardware
- 9.2.1 Slave FIFO Pins
- 9.2.2 FIFO Data Bus
- 9.2.3 Interface Clock
- 9.2.4 FIFO Flag Pins (FLAGA, FLAGB, FLAGC, FLAGD)
- 9.2.5 Control Pins (SLOE, SLRD, SLWR, PKTEND, FIFOADR[1:0])
- 9.2.6 Slave FIFO Chip Select
- 9.2.7 Implementing Synchronous Slave FIFO Writes
- 9.2.8 Implementing Synchronous Slave FIFO Reads
- 9.2.9 Implementing Asynchronous Slave FIFO Writes
- 9.2.10 Implementing Asynchronous Slave FIFO Reads
- 9.3 Firmware
- 9.3.1 Firmware FIFO Access
- 9.3.2 EPx Memories
- 9.3.3 Slave FIFO Programmable Level Flag
- 9.3.4 Auto-In / Auto-Out Modes
- 9.3.5 CPU Access to OUT Packets, AUTOOUT = 1
- 9.3.6 CPU Access to OUT Packets, AUTOOUT = 0
- 9.3.7 CPU Access to IN Packets, AUTOIN = 1
- 9.3.8 Access to IN Packets, AUTOIN=0
- 9.3.9 Auto In/Auto Out Initialization
- 9.3.10 Auto Mode: Synchronous FIFO IN Data Transfers
- 9.3.11 Auto Mode Example: Asynchronous FIFO IN Data Transfers
- 9.3.12 Skipping Out Packets while in AUTOOUT Mode
- 9.3.13 Aborting Packets in FIFO while in AUTOIN Mode
- 9.4 Switching Between Manual Out and Auto Out
- 10. General Programmable Interface
- 10.1 Introduction
- 10.2 Hardware
- 10.2.1 The External GPIF Interface
- 10.2.2 Default GPIF Pins Configuration
- 10.2.3 Six Control OUT Signals
- 10.2.4 Six Ready IN Signals
- 10.2.5 Nine GPIF Address OUT Signals
- 10.2.6 Three GSTATE OUT Signals
- 10.2.7 8/16-Bit Data Path, WORDWIDE = 1 (default) and WORDWIDE = 0
- 10.2.8 Byte Order for 16 Bit GPIF Transactions
- 10.2.9 Interface Clock (IFCLK)
- 10.2.10 Connecting GPIF Signal Pins to Hardware
- 10.2.11 Example GPIF Hardware Interconnect
- 10.3 Programming the GPIF Waveforms
- 10.4 Firmware
- 10.4.1 Single Read Transactions
- 10.4.2 Single Write Transactions
- 10.4.3 FIFO Read and FIFO Write (Burst) Transactions
- 10.4.4 GPIF Flag Selection
- 10.4.5 GPIF Flag Stop
- 10.4.6 Firmware Access to IN Packets, (AUTOIN=1)
- 10.4.7 Firmware Access to IN Packets, (AUTOIN = 0)
- 10.4.8 Firmware Access to OUT packets, (AUTOOUT=1)
- 10.4.9 Firmware Access to OUT Packets, (AUTOOUT = 0)
- 10.5 UDMA Interface
- 10.6 ECC Generation
- 11. CPU Introduction
- 11.1 Introduction
- 11.2 8051 Enhancements
- 11.3 Performance Overview
- 11.4 Software Compatibility
- 11.5 803x/805x Feature Comparison
- 11.6 EZ-USB/DS80C320 Differences
- 11.7 EZ-USB Register Interface
- 11.8 EZ-USB Internal RAM
- 11.9 I/O Ports
- 11.10 Interrupts
- 11.11 Power Control
- 11.12 Special Function Registers
- 11.13 External Address/Data Buses
- 11.14 Reset
- 12. Instruction Set
- 13. Input/Output
- 14. Timers/Counters and Serial Interface
- 15. Registers
- 15.1 Introduction
- 15.2 Special Function Registers
- 15.3 About SFRs
- 15.4 GPIF Waveform Memories
- 15.4.1 WAVEDATA
- 15.5 General Configuration Registers
- 15.5.1 CPUCS
- 15.5.2 IFCONFIG
- 15.5.3 PINFLAGSxx
- 15.5.4 FIFORESET
- 15.5.5 BREAKPT
- 15.5.6 BPADDRx
- 15.5.7 UART230
- 15.5.8 FIFOINPOLAR
- 15.5.9 REVID
- 15.5.10 REVCTL
- 15.5.11 GPIFHOLDAMOUNT
- 15.6 Endpoint Configuration
- 15.6.1 EP1OUTCFG
- 15.6.2 EP1INCFG
- 15.6.3 EPxCFG
- 15.6.4 EPxFIFOCFG
- 15.6.5 EP2AUTOINLENH
- 15.6.6 EP6AUTOINLENH
- 15.6.7 EP4AUTOINLENH
- 15.6.8 EP8AUTOINLENH
- 15.6.9 EPxAUTOINLENL
- 15.6.10 EPxFIFOPFH
- 15.6.11 EPxFIFOPFL
- 15.6.12 EP2ISOINPKTS
- 15.6.13 EP4ISOINPKTS
- 15.6.14 EP6ISOINPKTS
- 15.6.15 EP8ISOINPKTS
- 15.6.16 INPKTEND
- 15.6.17 OUTPKTEND
- 15.7 Interrupts
- 15.7.1 EPxFIFOIE
- 15.7.2 EPxFIFOIRQ
- 15.7.3 IBNIE
- 15.7.4 IBNIRQ
- 15.7.5 NAKIE
- 15.7.6 NAKIRQ
- 15.7.7 USBIE
- 15.7.8 USBIRQ
- 15.7.9 EPIE
- 15.7.10 EPIRQ
- 15.7.11 GPIFIE
- 15.7.12 GPIFIRQ
- 15.7.13 USBERRIE
- 15.7.14 USBERRIE
- 15.7.15 ERRCNTLIM
- 15.7.16 CLRERRCNT
- 15.7.17 INT2IVEC
- 15.7.18 INT4IVEC
- 15.7.19 INTSETUP
- 15.8 Input/Output Registers
- 15.8.1 PORTACFG
- 15.8.2 PORTCCFG
- 15.8.3 PORTECFG
- 15.8.4 I2CS
- 15.8.5 I2CDAT
- 15.8.6 I2CTL
- 15.8.7 XAUTODATx
- 15.9 ECC Control and Data Registers
- 15.9.4 ECCCFG
- 15.9.5 ECCRESET
- 15.9.6 ECC1B0
- 15.9.7 ECC1B1
- 15.9.8 ECC1B2
- 15.9.9 ECC2B0
- 15.9.10 ECC2B1
- 15.9.11 ECC2B2
- 15.10 UDMA CRC Registers
- 15.10.1 UDMACRCx
- 15.10.2 UDMACRCQUALIFIER
- 15.11 USB Control
- 15.11.1 USBCS
- 15.11.2 SUSPEND
- 15.11.3 WAKEUPCS
- 15.11.4 TOGCTL
- 15.11.5 USBFRAMEH
- 15.11.6 USBFRAMEL
- 15.11.7 MICROFRAME
- 15.11.8 FNADDR
- 15.12 Endpoints
- 15.12.1 EP0BCH
- 15.12.2 EP0BCL
- 15.12.3 EP1OUTBC
- 15.12.4 EP1INBC
- 15.12.5 EP2BCH
- 15.12.6 EP6BCH
- 15.12.7 EP4BCH
- 15.12.8 EP8BCH
- 15.12.9 EPxBCL
- 15.12.10 EP0CS
- 15.12.11 EP1OUTCS
- 15.12.12 EP1INCS
- 15.12.13 EP2CS
- 15.12.14 EP4CS
- 15.12.15 EP6CS
- 15.12.16 EP8CS
- 15.12.17 EP2FIFOFLGS
- 15.12.18 EP4FIFOFLGS
- 15.12.19 EP6FIFOFLGS
- 15.12.20 EP8FIFOFLGS
- 15.12.21 EP2FIFOBCH
- 15.12.22 EP6FIFOBCH
- 15.12.23 EP4FIFOBCH
- 15.12.24 EP8FIFOBCH
- 15.12.25 EPxFIFOBCL
- 15.12.26 SUDPTRx
- 15.12.27 SUDPTRCTL
- 15.12.28 SETUPDAT
- 15.13 General Programmable Interface
- 15.13.1 GPIFWFSELECT
- 15.13.2 GPIFIDLECS
- 15.13.3 GPIFIDLECTL
- 15.13.4 GPIFCTLCFG
- 15.13.5 GPIFADRH
- 15.13.6 GPIFADRL
- 15.13.7 FLOWSTATE
- 15.13.8 FLOWLOGIC
- 15.13.9 FLOWEQxCTL
- 15.13.10 FLOWSTB
- 15.13.11 FLOWHOLDOFF
- 15.13.12 FLOWSTBEDGE
- 15.13.13 FLOWSTBHPERIOD
- 15.13.14 GPIFHOLDAMOUNT
- 15.13.15 GPIFTCBx
- 15.13.16 EPxGPIFFLGSEL
- 15.13.17 EPxGPIFPFSTOP
- 15.13.18 EPxGPIFTRIG
- 15.13.19 XGPIFSGLDATH
- 15.13.20 XGPIFSGLDATL
- 15.13.21 XGPIFSGLDATLNOX
- 15.13.22 GPIFREADYCFG
- 15.13.23 GPIFREADYSTAT
- 15.13.24 GPIFABORT
- 15.14 Endpoint Buffers
- 15.14.1 EP0BUF
- 15.14.2 EP1OUTBUF
- 15.14.3 EP1INBUF
- 15.14.4 EP2FIFOBUF
- 15.14.5 EP4FIFOBUF
- 15.14.6 EP6FIFOBUF
- 15.14.7 EP8FIFOBUF
- 15.15 Synchronization Delay
- Appendix A. Descriptors for Full- Speed Mode
- Appendix B. Descriptors for High- Speed Mode
- Appendix C. Device Register Summary
- Index