EZ USB_TRM 001 13670 USB Technical Reference Manual

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EZ-USB® Technical Reference Manual
Document # 001-13670 Rev. *F
May 10, 2017
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
http://www.cypress.com
2 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
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and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or refer-
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tive owners.
This manual is the EZ-USB® Technical Reference Manual, for EZ-USB FX2LP™, and EZ-USB FX1™. It provides information
for the following chips.
CY7C68013A
CY7C68014A
CY7C68015A
CY7C68016A
CY7C64713
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 3
Contents Overview
1. Introducing EZ-USB® 13
2. Endpoint Zero 37
3. Enumeration and ReNumeration™ 51
4. Interrupts 59
5. Memory 71
6. Power Management 77
7. Resets 83
8. Access to Endpoint Buffers 87
9. Slave FIFOs 99
10. General Programmable Interface 121
11. CPU Introduction 169
12. Instruction Set 175
13. Input/Output 181
14. Timers/Counters and Serial Interface 193
15. Registers 211
Appendix A. Descriptors for Full-Speed Mode 367
Appendix B. Descriptors for High-Speed Mode 375
Appendix C. Device Register Summary 383
Index 395
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Contents
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 5
Contents
1. Introducing EZ-USB® 13
1.1 An Introduction to USB...................................................................................................................13
1.2 The USB Specification....................................................................................................................14
1.3 Host is Master.................................................................................................................................14
1.4 USB Direction.................................................................................................................................14
1.5 Tokens and PIDs............................................................................................................................14
1.5.1 Receiving Data from the Host ..........................................................................................15
1.5.2 Sending Data to the Host .................................................................................................15
1.6 USB Frames...................................................................................................................................15
1.7 USB Transfer Types.......................................................................................................................15
1.7.1 Bulk Transfers ..................................................................................................................16
1.7.2 Interrupt Transfers............................................................................................................16
1.7.3 Isochronous Transfers......................................................................................................16
1.7.4 Control Transfers..............................................................................................................16
1.8 Enumeration ...................................................................................................................................16
1.8.1 Full Speed/High Speed Detection ....................................................................................17
1.9 The Serial Interface Engine............................................................................................................17
1.10 ReNumeration™.............................................................................................................................18
1.11 EZ-USB Architecture ......................................................................................................................18
1.12 EZ-USB Feature Summary.............................................................................................................20
1.13 EZ-USB Integrated Microprocessor................................................................................................20
1.14 EZ-USB Block Diagram ..................................................................................................................21
1.15 Packages........................................................................................................................................22
1.15.1 56-Pin Packages ..............................................................................................................22
1.15.2 CY7C68013A/14A and CY7C68015A/16A Differences ...................................................22
1.15.3 100-Pin Package..............................................................................................................22
1.15.4 128-Pin Package..............................................................................................................23
1.15.5 Signals Available in the Five Packages............................................................................23
1.16 Package Diagrams .........................................................................................................................25
1.17 EZ-USB Endpoint Buffers...............................................................................................................30
1.18 External FIFO Interface ..................................................................................................................31
1.19 EZ-USB Product Family .................................................................................................................34
1.20 Document History...........................................................................................................................35
2. Endpoint Zero 37
2.1 Introduction.....................................................................................................................................37
2.2 Control Endpoint EP0.....................................................................................................................37
2.3 USB Requests................................................................................................................................39
2.3.1 Get Status.........................................................................................................................40
2.3.2 Set Feature.......................................................................................................................42
2.3.3 Clear Feature ...................................................................................................................43
2.3.4 Get Descriptor ..................................................................................................................43
2.3.4.1 Get Descriptor-Device....................................................................................44
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Contents
2.3.4.2 Get Descriptor-Device Qualifier .....................................................................45
2.3.4.3 Get Descriptor-Configuration .........................................................................45
2.3.4.4 Get Descriptor-String .....................................................................................46
2.3.4.5 Get Descriptor-Other Speed Configuration ...................................................46
2.3.5 Set Descriptor ..................................................................................................................46
2.3.5.1 Set Configuration ..........................................................................................47
2.3.6 Get Configuration.............................................................................................................47
2.3.7 Set Interface.....................................................................................................................47
2.3.8 Get Interface ....................................................................................................................48
2.3.9 Set Address .....................................................................................................................48
2.3.10 Sync Frame......................................................................................................................49
2.3.11 Firmware Load .................................................................................................................49
3. Enumeration and ReNumeration™ 51
3.1 Introduction ....................................................................................................................................51
3.2 EZ-USB Startup Modes..................................................................................................................51
3.3 The Default USB Device ................................................................................................................52
3.4 EEPROM Boot-load Data Formats.................................................................................................52
3.4.1 No EEPROM or Invalid EEPROM....................................................................................52
3.4.2 Serial EEPROM Present, First Byte is 0xC0 ...................................................................53
3.4.3 Serial EEPROM Present, First Byte is 0xC2....................................................................53
3.4.3.1 General Purpose Use of the I2CBus..............................................................54
3.5 EEPROM Configuration Byte .........................................................................................................55
3.6 The RENUM Bit..............................................................................................................................56
3.7 EZ-USB Response to Device Requests (RENUM = 0) ..................................................................56
3.8 EZ-USB Vendor Request for Firmware Load.................................................................................56
3.9 How the Firmware ReNumerates...................................................................................................57
3.10 Multiple ReNumerations™ .............................................................................................................58
4. Interrupts 59
4.1 Introduction ....................................................................................................................................59
4.2 SFRs ..............................................................................................................................................59
4.2.1 803x/805x Compatibility...................................................................................................61
4.3 Interrupt Processing .......................................................................................................................62
4.3.1 Interrupt Masking .............................................................................................................62
4.3.1.1 Interrupt Priorities...........................................................................................62
4.3.2 Interrupt Sampling............................................................................................................62
4.3.3 Interrupt Latency ..............................................................................................................63
4.4 USB-Specific Interrupts..................................................................................................................63
4.4.1 Resume Interrupt .............................................................................................................63
4.4.2 USB Interrupts .................................................................................................................63
4.4.2.1 SUTOK, SUDAV Interrupts............................................................................66
4.4.2.2 SOF Interrupt .................................................................................................66
4.4.2.3 Suspend Interrupt ..........................................................................................66
4.4.2.4 USB RESET Interrupt ....................................................................................66
4.4.2.5 HISPEED Interrupt (FX2LP only)...................................................................66
4.4.2.6 EP0ACK Interrupt ..........................................................................................66
4.4.2.7 Endpoint Interrupts ........................................................................................66
4.4.2.8 In-Bulk-NAK (IBN) Interrupt ...........................................................................66
4.4.2.9 EPxPING Interrupt (FX2LP only) ...................................................................66
4.4.2.10 ERRLIMIT Interrupt........................................................................................67
4.4.2.11 EPxISOERR Interrupt ....................................................................................67
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4.5 USB-Interrupt Autovectors..............................................................................................................67
4.5.1 USB Autovector Coding ...................................................................................................68
4.6 I²C Bus Interrupt .............................................................................................................................68
4.7 FIFO/GPIF Interrupt (INT4) ............................................................................................................69
4.8 FIFO/GPIF Interrupt Autovectors....................................................................................................69
4.8.1 FIFO/GPIF Autovector Coding .........................................................................................70
5. Memory 71
5.1 Introduction.....................................................................................................................................71
5.2 Internal Data RAM..........................................................................................................................71
5.2.1 The Lower 128 .................................................................................................................72
5.2.2 The Upper 128 .................................................................................................................72
5.2.3 Special Function Register Space......................................................................................72
5.3 External Program Memory and External Data Memory..................................................................72
5.3.1 56- and 100-Pin EZ-USB Chips .......................................................................................73
5.3.2 128-Pin EZ-USB Chip ......................................................................................................73
5.4 EZ-USB Memory Maps...................................................................................................................74
5.5 ‘Von-Neumannizing’ Off-Chip Program and Data Memory.............................................................76
5.6 On-Chip Data Memory at 0xE000-0xFFFF.....................................................................................76
6. Power Management 77
6.1 Introduction.....................................................................................................................................77
6.2 USB Suspend.................................................................................................................................79
6.2.1 Suspend Register.............................................................................................................79
6.3 Wakeup/Resume............................................................................................................................80
6.3.1 Wakeup Interrupt..............................................................................................................81
6.4 USB Resume (Remote Wakeup) ...................................................................................................81
6.4.1 WU2 Pin ...........................................................................................................................81
7. Resets 83
7.1 Introduction.....................................................................................................................................83
7.2 Hard Reset .....................................................................................................................................83
7.3 Releasing the CPU Reset...............................................................................................................84
7.3.1 RAM Download ................................................................................................................84
7.3.2 EEPROM Load.................................................................................................................84
7.3.3 External ROM...................................................................................................................84
7.4 CPU Reset Effects..........................................................................................................................84
7.5 USB Bus Reset...............................................................................................................................85
7.6 EZ-USB Disconnect........................................................................................................................85
7.7 Reset Summary .............................................................................................................................85
8. Access to Endpoint Buffers 87
8.1 Introduction.....................................................................................................................................87
8.2 EZ-USB Large and Small Endpoints ..............................................................................................87
8.3 High Speed and Full Speed Differences ........................................................................................87
8.4 How the CPU Configures the Endpoints ........................................................................................88
8.5 CPU Access to EZ-USB Endpoint Data .........................................................................................89
8.6 CPU Control of EZ-USB Endpoints ................................................................................................89
8.6.1 Registers That Control EP0, EP1IN, and EP1OUT..........................................................90
8.6.1.1 EP0CS ...........................................................................................................90
8.6.1.2 EP0BCH and EP0BCL...................................................................................90
8.6.1.3 USBIE, USBIRQ.............................................................................................91
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8.6.1.4 EP01STAT.....................................................................................................91
8.6.1.5 EP1OUTCS ...................................................................................................91
8.6.1.6 EP1OUTBC ...................................................................................................91
8.6.1.7 EP1INCS .......................................................................................................91
8.6.1.8 EP1INBC .......................................................................................................92
8.6.2 Registers That Control EP2, EP4, EP6, EP8...................................................................92
8.6.2.1 EP2468STAT.................................................................................................92
8.6.2.2 EP2ISOINPKTS, EP4ISOINPKTS, EP6ISOINPKTS, EP8ISOINPKTS.........92
8.6.2.3 EP2CS, EP4CS, EP6CS, EP8CS..................................................................92
8.6.2.4 EP2BCH:L, EP4BCH:L, EP6BCH:L, EP8BCH:L ...........................................93
8.6.3 Registers That Control All Endpoints ..............................................................................93
8.6.3.1 IBNIE, IBNIRQ, NAKIE, NAKIRQ...................................................................93
8.6.3.2 EPIE, EPIRQ .................................................................................................94
8.6.3.3 USBERRIE, USBERRIRQ, ERRCNTLIM, CLRERRCNT..............................94
8.6.3.4 TOGCTL ........................................................................................................95
8.7 The Setup Data Pointer..................................................................................................................95
8.7.1 Transfer Length................................................................................................................96
8.7.2 Accessible Memory Spaces .............................................................................................96
8.8 Autopointers ...................................................................................................................................96
9. Slave FIFOs 99
9.1 Introduction ....................................................................................................................................99
9.2 Hardware........................................................................................................................................99
9.2.1 Slave FIFO Pins.............................................................................................................100
9.2.2 FIFO Data Bus ...............................................................................................................101
9.2.3 Interface Clock ...............................................................................................................102
9.2.4 FIFO Flag Pins (FLAGA, FLAGB, FLAGC, FLAGD)......................................................103
9.2.5 Control Pins (SLOE, SLRD, SLWR, PKTEND, FIFOADR[1:0]) .....................................103
9.2.6 Slave FIFO Chip Select .................................................................................................104
9.2.7 Implementing Synchronous Slave FIFO Writes .............................................................105
9.2.8 Implementing Synchronous Slave FIFO Reads.............................................................107
9.2.9 Implementing Asynchronous Slave FIFO Writes ...........................................................108
9.2.10 Implementing Asynchronous Slave FIFO Reads ...........................................................109
9.3 Firmware ......................................................................................................................................110
9.3.1 Firmware FIFO Access .................................................................................................. 110
9.3.2 EPx Memories................................................................................................................ 111
9.3.3 Slave FIFO Programmable Level Flag........................................................................... 111
9.3.4 Auto-In / Auto-Out Modes .............................................................................................. 111
9.3.5 CPU Access to OUT Packets, AUTOOUT = 1............................................................... 112
9.3.6 CPU Access to OUT Packets, AUTOOUT = 0............................................................... 113
9.3.7 CPU Access to IN Packets, AUTOIN = 1....................................................................... 115
9.3.8 Access to IN Packets, AUTOIN=0 ................................................................................. 116
9.3.9 Auto In/Auto Out Initialization......................................................................................... 117
9.3.10 Auto Mode: Synchronous FIFO IN Data Transfers ........................................................ 118
9.3.11 Auto Mode Example: Asynchronous FIFO IN Data Transfers ....................................... 119
9.3.12 Skipping Out Packets while in AUTOOUT Mode ........................................................... 119
9.3.13 Aborting Packets in FIFO while in AUTOIN Mode .........................................................120
9.4 Switching Between Manual Out and Auto Out .............................................................................120
10. General Programmable Interface 121
10.1 Introduction ..................................................................................................................................121
10.1.1 Typical GPIF Interface ...................................................................................................123
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10.2 Hardware......................................................................................................................................123
10.2.1 The External GPIF Interface...........................................................................................124
10.2.2 Default GPIF Pins Configuration ....................................................................................124
10.2.3 Six Control OUT Signals ................................................................................................124
10.2.3.1 Control Output Modes..................................................................................124
10.2.4 Six Ready IN Signals......................................................................................................124
10.2.5 Nine GPIF Address OUT Signals...................................................................................124
10.2.6 Three GSTATE OUT Signals..........................................................................................124
10.2.7 8/16-Bit Data Path, WORDWIDE = 1 (default) and WORDWIDE = 0 ............................125
10.2.8 Byte Order for 16 Bit GPIF Transactions........................................................................125
10.2.9 Interface Clock (IFCLK)..................................................................................................125
10.2.10 Connecting GPIF Signal Pins to Hardware ....................................................................126
10.2.11 Example GPIF Hardware Interconnect...........................................................................126
10.3 Programming the GPIF Waveforms .............................................................................................127
10.3.1 The GPIF Registers........................................................................................................127
10.3.2 Programming GPIF Waveforms .....................................................................................127
10.3.2.1 The GPIF IDLE State ...................................................................................128
10.3.2.2 Defining States.............................................................................................128
10.3.3 Reexecuting a Task Within a DP State...........................................................................131
10.3.4 State Instructions............................................................................................................134
10.3.4.1 Structure of the Waveform Descriptors........................................................136
10.3.4.2 Terminating a GPIF Transfer .......................................................................136
10.4 Firmware ......................................................................................................................................137
10.4.1 Single Read Transactions ..............................................................................................143
10.4.2 Single Write Transactions...............................................................................................147
10.4.3 FIFO Read and FIFO Write (Burst) Transactions...........................................................150
10.4.3.1 Transaction Counter.....................................................................................150
10.4.3.2 Reading the Transaction-Count Status in a DP State..................................150
10.4.4 GPIF Flag Selection .......................................................................................................150
10.4.5 GPIF Flag Stop...............................................................................................................150
10.4.5.1 Performing a FIFO Read Transaction..........................................................151
10.4.6 Firmware Access to IN Packets, (AUTOIN=1) ...............................................................156
10.4.7 Firmware Access to IN Packets, (AUTOIN = 0) .............................................................157
10.4.7.1 Performing a FIFO-Write Transaction..........................................................159
10.4.8 Firmware Access to OUT packets, (AUTOOUT=1)........................................................164
10.4.9 Firmware Access to OUT Packets, (AUTOOUT = 0) .....................................................165
10.5 UDMA Interface............................................................................................................................167
10.6 ECC Generation ...........................................................................................................................167
11. CPU Introduction 169
11.1 Introduction...................................................................................................................................169
11.2 8051 Enhancements.....................................................................................................................170
11.3 Performance Overview.................................................................................................................170
11.4 Software Compatibility..................................................................................................................171
11.5 803x/805x Feature Comparison ...................................................................................................171
11.6 EZ-USB/DS80C320 Differences...................................................................................................172
11.6.1 Serial Ports.....................................................................................................................172
11.6.2 Timer 2 ...........................................................................................................................172
11.6.3 Timed Access Protection................................................................................................172
11.6.4 Watchdog Timer .............................................................................................................172
11.6.5 Power Fail Detection ......................................................................................................172
11.6.6 Port I/O...........................................................................................................................172
11.6.7 Interrupts ........................................................................................................................172
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11.7 EZ-USB Register Interface...........................................................................................................172
11.8 EZ-USB Internal RAM ..................................................................................................................172
11.9 I/O Ports .......................................................................................................................................173
11.10 Interrupts ......................................................................................................................................173
11.11 Power Control ..............................................................................................................................173
11.12 Special Function Registers ..........................................................................................................174
11.13 External Address/Data Buses ......................................................................................................174
11.14 Reset............................................................................................................................................174
12. Instruction Set 175
12.1 Introduction ..................................................................................................................................175
12.1.1 Instruction Timing...........................................................................................................178
12.1.2 Stretch Memory Cycles ..................................................................................................178
12.1.3 Dual Data Pointers.........................................................................................................179
12.1.4 Special Function Registers ............................................................................................179
13. Input/Output 181
13.1 Introduction ..................................................................................................................................181
13.2 I/O Ports .......................................................................................................................................181
13.3 SFR Registers..............................................................................................................................182
13.4 I/O Port Alternate Functions.........................................................................................................183
13.4.1 Port A Alternate Functions .............................................................................................185
13.4.2 Port B and Port D Alternate Functions...........................................................................186
13.4.3 Port C Alternate Functions.............................................................................................187
13.4.4 Port E Alternate Functions .............................................................................................188
13.5 I2C Bus Controller........................................................................................................................189
13.5.1 Interfacing to I2C Peripherals ........................................................................................189
13.5.1.1 Multiple Bus Masters....................................................................................189
13.5.2 Registers........................................................................................................................190
13.5.2.1 I2CS Register ..............................................................................................190
13.5.2.2 I2CDAT Register..........................................................................................191
13.5.2.3 I2CTL Register.............................................................................................191
13.5.3 Sending Data .................................................................................................................191
13.5.4 Receiving Data...............................................................................................................191
13.6 EEPROM Boot Loader .................................................................................................................192
14. Timers/Counters and Serial Interface 193
14.1 Introduction ..................................................................................................................................193
14.2 Timers/Counters...........................................................................................................................193
14.2.1 803x/805x Compatibility.................................................................................................193
14.2.2 Timers 0 and 1 ...............................................................................................................193
14.2.2.1 Mode 0, 13 Bit Timer/Counter—Timer 0 and Timer 1..................................194
14.2.2.2 Mode 1, 16 Bit Timer/Counter — Timer 0 and Timer 1................................195
14.2.2.3 Mode 2, 8 Bit Counter with Auto-Reload — Timer 0 and Timer 1................196
14.2.2.4 Mode 3, Two 8 Bit Counters — Timer 0 Only ..............................................196
14.2.3 Timer Rate Control.........................................................................................................197
14.2.4 Timer 2...........................................................................................................................197
14.2.4.1 Timer 2 Mode Control ..................................................................................198
14.2.5 Timer 2: The 6 Bit Timer/Counter Mode.........................................................................198
14.2.5.1 Timer 2 The 16 Bit Timer/Counter Mode with Capture ................................198
14.2.6 Timer 2: 16 Bit Timer/Counter Mode with Auto-Reload..................................................199
14.2.7 Timer 2: Baud Rate Generator Mode.............................................................................200
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14.3 Serial Interface .............................................................................................................................201
14.3.1 803x/805x Compatibility .................................................................................................202
14.3.2 High-Speed Baud Rate Generator .................................................................................202
14.3.3 Mode 0 ...........................................................................................................................202
14.3.4 Mode 1 ...........................................................................................................................205
14.3.4.1 Mode 1 Baud Rate .......................................................................................205
14.3.4.2 Mode 1 Transmit ..........................................................................................207
14.3.5 Mode 1 Receive .............................................................................................................207
14.3.6 Mode 2 ...........................................................................................................................208
14.3.6.1 Mode 2 Transmit ..........................................................................................208
14.3.6.2 Mode 2 Receive ...........................................................................................208
14.3.7 Mode 3 ...........................................................................................................................210
15. Registers 211
15.1 Introduction...................................................................................................................................211
15.1.1 Example Register Format...............................................................................................211
15.1.2 Other Conventions .........................................................................................................211
15.2 Special Function Registers...........................................................................................................212
15.3 About SFRs ..................................................................................................................................213
15.4 GPIF Waveform Memories...........................................................................................................219
15.5 General Configuration Registers ..................................................................................................220
15.6 Endpoint Configuration.................................................................................................................233
15.6.11.1 IN Endpoints.................................................................................................248
15.6.11.2 OUT Endpoints.............................................................................................249
15.7 Interrupts ......................................................................................................................................256
15.8 Input/Output Registers..................................................................................................................275
15.9 ECC Control and Data Registers..................................................................................................283
15.9.1 ECC Features.................................................................................................................283
15.9.2 ECC Implementation ......................................................................................................283
15.9.3 ECC Check/Correct........................................................................................................284
15.10 UDMA CRC Registers..................................................................................................................295
15.11 USB Control..................................................................................................................................297
15.12 Endpoints......................................................................................................................................305
15.13 General Programmable Interface .................................................................................................333
15.14 Endpoint Buffers...........................................................................................................................359
15.15 Synchronization Delay..................................................................................................................366
Appendix A. Descriptors for Full-Speed Mode 367
Appendix B. Descriptors for High-Speed Mode 375
Appendix C. Device Register Summary 383
Index 395
12 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Contents
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 13
1. Introducing EZ-USB®
Introduction
The Universal Serial Bus (USB) has gained wide acceptance as the connection method of choice for PC peripherals. Equally
successful in the Windows and Macintosh worlds, USB has delivered on its promises of easy attachment, an end to configu-
ration hassles, and true plug-and-play operation.
The latest generation of the USB specification, ‘USB 2.0’, extends the original specification to include:
■A new ‘high speed’ 480 Mbps signaling rate, a 40× improvement over the USB 1.1 full speed rate of 12 Mbps
■Full backward and forward compatibility with USB 1.1 devices and cables
■A new hub architecture that can provide multiple 12 Mbps downstream ports for USB 1.1 devices
The Cypress Semiconductor EZ-USB® family offers single chip USB 2.0 peripherals with architecture designed to accommo-
date the higher data rates offered by USB 2.0. The EZ-USB FX2LP device (CY7C68013A/14A/15A/16A) supports both full
and high speed modes. The EZ-USB FX1 device (CY7C64713) only supports the full speed mode. The term ‘EZ-USB’ refers
generically to both EZ-USB FX2LP and EZ-USB FX1 devices.
This introductory chapter begins with a brief USB tutorial to put USB and EZ-USB terminology into context. The remainder of
the chapter briefly outlines the EZ-USB architecture.
Note This Technical Reference Manual does not cover the CY7C646xx or AN21xx products. See the respective Technical
Reference Manuals for these products for more information.
1.1 An Introduction to USB
Like a well designed automobile or appliance, a USB peripheral’s outward simplicity hides internal complexity. There is a lot
going on under the hood of a USB device.
■A USB device can be plugged in anytime, even while the PC is turned on
■When the PC detects that a USB device has been plugged in, it automatically interrogates the device to learn its capabili-
ties and requirements. From this information, the PC automatically loads the device’s driver into the operating system.
When the device is unplugged, the operating system automatically logs it off and unloads its driver.
■USB devices do not use DIP switches, jumpers, or configuration programs. There is never an IRQ, DMA, memory, or I/O
conflict with a USB device.
■USB expansion hubs make the bus simultaneously available to dozens of devices
■USB is fast enough for printers, hard disk drives, CD-quality audio, and scanners
■USB supports three speeds:
❐Low speed (1.5 Mbps), suitable for mice, keyboards and joysticks
❐Full speed (12 Mbps), for devices such as modems, speakers and scanners
❐High speed (480 Mbps), for devices such as hard disk drives, CD-ROMs, video cameras, and high resolution scanners
14 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Introducing EZ-USB®
The Cypress Semiconductor EZ-USB family supports the
high bandwidth offered by the USB 2.0 high-speed mode.
The EZ-USB chips provide a highly-integrated solution for a
USB peripheral device. The EZ-USB chips offer the follow-
ing features:
■An integrated, high-performance CPU based on the
industry-standard 8051 processor
■A soft (RAM-based) architecture that allows unlimited
configuration and upgrades
■Full USB throughput. USB devices that use EZ-USB
chips are not limited by number of endpoints, buffer
sizes, or transfer speeds
■Automatic handling of most of the USB protocol, which
simplifies code and accelerates the USB learning curve
1.2 The USB Specification
The Universal Serial Bus Specification Version 2.0 is avail-
able on the Internet from the USB Implementers Forum,
Inc., at http://www.usb.org. Published in April, 2000, the
USB Specification is the work of a founding committee of
seven industry heavyweights: Compaq, Hewlett-Packard,
Lucent, Philips, Intel, Microsoft, and NEC. This impressive
list of developers secures USB’s position as the low- to high
speed PC connection method of the future.
A glance at the USB Specification makes it immediately
apparent that USB is not nearly as simple as the older serial
or parallel ports. The USB Specification uses new terms like
endpoint, isochronous, and enumeration, and finds new
uses for old terms like configuration, interface, and interrupt.
Woven into the USB fabric is a software abstraction model
that deals with things such as pipes. The USB Specification
also contains information about such details as connector
types and wire colors.
1.3 Host is Master
This is a fundamental USB concept. There is exactly one
master in a USB system: the host computer. USB devices
respond to host requests. USB devices cannot send infor-
mation among themselves, as they could if USB were a
peer-to-peer topology.
However, there is one case where a USB device can initiate
signaling without prompting from the host. After being put
into a low-power ‘suspend’ mode by the host, a device can
signal a ‘remote wakeup’. This is the only case in which the
USB device is the initiator; in all other cases, the host makes
device requests and the device responds to them.
There is an excellent reason for this host-centric model. The
USB architects were keenly aware of cost, and the best way
to make low-cost peripherals is to put most of the ‘smarts’
into the host side, the PC. If USB had been defined as peer-
to-peer, every USB device would have required more intelli-
gence, raising cost.
1.4 USB Direction
Because the host is always the bus master, it is easy to
remember USB direction: OUT means from the host to the
device, and IN means from the device to the host. EZ-USB
nomenclature uses this naming convention. For example, an
endpoint that sends data to the host is an IN endpoint. This
can be confusing at first, because the EZ-USB sends data to
the host by loading an IN endpoint buffer. Likewise, the EZ-
USB receives host data from an OUT endpoint buffer.
1.5 Tokens and PIDs
In this manual, you will read statements such as: “When the
host sends an IN token…,” or “The device responds with an
ACK.” What do these terms mean?
A USB transaction consists of data packets identified by
special codes called Packet IDs or PIDs. A PID signifies
what kind of packet is being transmitted. There are four PID
types, shown in Table 1-1.
Figure 1-1 illustrates a USB OUT transfer. Host traffic is
shown in solid shading, while device traffic is shown cross-
hatched. Packet 1 is an OUT token, indicated by the OUT
PID. The OUT token signifies that data from the host is
about to be transmitted over the bus. Packet 2 contains
data, as indicated by the DATA1 PID. Packet 3 is a hand-
shake packet, sent by the device using the ACK (acknowl-
edge) PID to signify to the host that the device received the
data error-free.
Continuing with Figure 1-1, a second transaction begins with
another OUT token 4, followed by more data 5, this time
using the DATA0 PID. Finally, the device again indicates
success by transmitting the ACK PID in a handshake packet
6.
When operating at full speed, every OUT transfer sends the
OUT data, even when the device is busy and cannot accept
the data. When operating at high speed, this slightly waste-
ful use of USB bandwidth is remedied by using the new
‘Ping’ PID. The host first sends a short PING token to an
OUT endpoint, asking if there is room for OUT data in the
peripheral device. Only when the PING is answered by an
ACK does the host send the OUT token and data.
Table 1-1. USB PIDS
PID Type PID Name
Token IN, OUT, SOF, SETUP
Data DATA0, DATA1, DATA2, MDATA
Handshake ACK, NAK, STALL, NYET
Special PRE, ERR, SPLIT, PING
Bold type indicates PIDs introduced with USB 2.0
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 15
Introducing EZ-USB®
Figure 1-1. USB Packets
There are two DATA PIDs (DATA0 and DATA1) in Figure 1-1
because the USB architects took error correction very seri-
ously. As mentioned previously, the ACK handshake is an
indication to the host that the peripheral received data with-
out error (the CRC portion of the packet is used to detect
errors). But what if the handshake packet itself is garbled in
transmission? To detect this, each side (host and device)
maintains a ‘data toggle’ bit, which is toggled between data
packet transfers. The state of this internal toggle bit is com-
pared with the PID that arrives with the data, either DATA0
or DATA1. When sending data, the host or device sends
alternating DATA0-DATA1 PIDs. By comparing the received
Data PID with the state of its own internal toggle bit, the
receiver can detect a corrupted handshake packet.
SETUP tokens are unique to CONTROL transfers. They
preface eight bytes of data from which the peripheral
decodes host Device Requests.
At full speed, SOF (Start of Frame) tokens occur once per
millisecond. At high speed, each frame contains eight SOF
tokens, each denoting a 125-s microframe.
Four handshake PIDs indicate the status of a USB transfer:
■ACK (Acknowledge) means ‘success’; the data was
received error-free.
■NAK (Negative Acknowledge) means ‘busy, try again.’ It
is tempting to assume that NAK means ‘error,’ but it
does not; a USB device indicates an error by not
responding.
■STALL means that something unforeseen went wrong
(probably as a result of miscommunication or lack of
cooperation between the host and device software). A
device sends the STALL handshake to indicate that it
does not understand a device request, that something
went wrong on the peripheral end, or that the host tried
to access a resource that was not there. It is like HALT,
but better, because USB provides a way to recover from
a stall.
■NYET (Not Yet) has the same meaning as ACK — the
data was received error-free — but also indicates that
the endpoint is not yet ready to receive another OUT
transfer. NYET PIDs occur only in high-speed mode.
A PRE (Preamble) PID precedes a low-speed (1.5 Mbps)
USB transmission. The EZ-USB family supports full-speed
(12 Mbps) and high-speed (480 Mbps) USB transfers only.
1.5.1 Receiving Data from the Host
To send data to a USB peripheral, the host issues an OUT
token followed by the data. If the peripheral has space for
the data and accepts it without error, it returns an ACK to the
host. If it is busy, it sends a NAK. If it finds an error, it sends
back nothing. For the latter two cases, the host re-sends the
data at a later time.
1.5.2 Sending Data to the Host
A USB device never spontaneously sends data to the
host. Either EZ-USB firmware or external logic can load
data into an EZ-USB endpoint buffer and ‘arm’ it for transfer
at any time. However, the data is not transmitted to the host
until the host issues an IN request to the EZ-USB endpoint.
If the host never sends the IN token, the data remains in the
EZ-USB endpoint buffer indefinitely.
1.6 USB Frames
The USB host provides a time base to all USB devices by
transmitting a start-of-frame (SOF) packet every millisecond.
SOF packets include an 11 bit number which increments
once per frame; the current frame number [0-2047] may be
read from internal EZ-USB registers at any time.
At high speed (480 Mbps), each one-millisecond frame is
divided into eight 125-s microframes, each of which is pre-
ceded by an SOF packet. The frame number still increments
only once per millisecond, so each of those SOF packets
contains the same frame number. To keep track of the cur-
rent microframe number [0-7], the EZ-USB FX2LP provides
a readable microframe counter.
The EZ-USB can generate an interrupt request whenever it
receives an SOF (once every millisecond at full speed, or
once every 125 s at high speed). This SOF interrupt can be
used, for example, to service isochronous endpoint data.
1.7 USB Transfer Types
USB defines four transfer types. These match the require-
ments of different data types delivered over the bus.
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16 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Introducing EZ-USB®
1.7.1 Bulk Transfers
Figure 1-2. Two Bulk Transfers, IN and OUT
Bulk data is ‘bursty,’ traveling in packets of 8, 16, 32, or 64
bytes at full speed or 512 bytes at high speed. Bulk data has
guaranteed accuracy, due to an automatic retry mechanism
for erroneous data. The host schedules bulk packets when
there is available bus time. Bulk transfers are typically used
for printer, scanner, or modem data. Bulk data has built-in
flow control provided by handshake packets.
1.7.2 Interrupt Transfers
Figure 1-3. An Interrupt Transfer
Interrupt data is like bulk data; it can have packet sizes of 1
through 64 bytes at full speed or up to 1024 bytes at high-
speed. Interrupt endpoints have an associated polling inter-
val that ensures they will be polled (receive an IN token) by
the host on a regular basis.
1.7.3 Isochronous Transfers
Figure 1-4. An Isochronous Transfer
Isochronous data is time-critical and used to stream data like
audio and video. An isochronous packet may contain up to
1023 bytes at full speed, or up to 1024 bytes at high speed.
Time of delivery is the most important requirement for iso-
chronous data. In every USB frame, a certain amount of
USB bandwidth is allocated to isochronous transfers. To
lighten the overhead, isochronous transfers have no hand-
shake (ACK/NAK/STALL/NYET), and no retries; error detec-
tion is limited to a 16 bit CRC.
Isochronous transfers do not use the data-toggle mecha-
nism. Full-speed isochronous data uses only the DATA0
PID; high-speed isochronous data uses DATA0, DATA1,
DATA2 and MDATA.
In full-speed mode, only one isochronous packet can be
transferred per endpoint, per frame. In high-speed mode, up
to three isochronous packets can be transferred per end-
point, per microframe. For more details, refer to the Isochro-
nous Transfers discussion in Chapter 5 of the USB
specification.
1.7.4 Control Transfers
Figure 1-5. A Control Transfer
Control transfers configure and send commands to a device.
Because they are so important, they employ the most exten-
sive USB error checking. The host reserves a portion of
each USB frame for Control transfers.
Control transfers consist of two or three stages. The SETUP
stage contains eight bytes of USB CONTROL data. An
optional DATA stage contains more data, if required. The
STATUS (or handshake) stage allows the device to indicate
successful completion of a CONTROL operation.
1.8 Enumeration
Your computer is ON. You plug in a USB device, and the
Windows™ cursor switches to an hourglass and then back
to a cursor. Magically, your device is connected and its Win-
dows driver is loaded. Anyone who has installed a sound
card into a PC and has had to configure countless jumpers,
drivers, and I/O / Interrupt / DMA settings knows that a USB
connection is miraculous. We’ve all heard about Plug and
Play, but USB delivers the real thing.
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SETUP
Stage
DATA
Stage
(optional)
STATUS
Stage
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 17
Introducing EZ-USB®
How does all this happen automatically? Inside every USB
device is a table of descriptors. This table is the sum total of
the device’s requirements and capabilities. When you plug
into USB, the host goes through a sign on sequence:
1. The host sends a Get Descriptor-Device request to
address zero (all USB devices must respond to address
zero when first attached).
2. The device responds to the request by sending ID data
back to the host to identify itself.
3. The host sends a Set Address request, which assigns a
unique address to the just-attached device so it may be
distinguished from the other devices connected to the
bus.
4. The host sends more Get Descriptor requests, asking for
additional device information. From this, it learns every-
thing else about the device: number of endpoints, power
requirements, required bus bandwidth, what driver to
load, etc.
This sign-on process is called ‘Enumeration’.
1.8.1 Full Speed/High Speed Detection
The USB Specification requires that high-speed (480 Mbits/
sec) devices must also be capable of enumerating at full-
speed (12 Mbps). In fact, all high-speed devices begin the
enumeration process in full-speed mode; devices switch to
high-speed operation only after the host and device have
agreed to operate at high speed. The high-speed negotia-
tion process occurs during USB reset, via the ‘Chirp’ proto-
col described in Chapter 7 of the USB Specification.
When connected to a full-speed host, the EZ-USB FX2LP
enumerates as a full-speed device. When connected to a
high-speed host, the EZ-USB FX2LP automatically switches
to high-speed mode. The EZ-USB FX1 always enumerates
as a full-speed device. Neither the EZ-USB FX2LP or the
EZ-USB FX1 support the low-speed mode (1.5 Mbps).
1.9 The Serial Interface Engine
Figure 1-6. What the SIE Does
Every USB device has a Serial Interface Engine (SIE) which
connects to the USB data lines (D+ and D-) and delivers
data to and from the USB device. Figure 1-6 illustrates the
SIE’s role: it decodes the packet PIDs, performs error
checking on the data using the transmitted CRC bits, and
delivers payload data to the USB device.
Bulk transfers are ‘asynchronous’, meaning that they
include a flow control mechanism using ACK and NAK
handshake PIDs. The SIE indicates busy to the host by
sending a NAK handshake packet. When the USB device
has successfully transferred the data, it commands the SIE
to send an ACK handshake packet, indicating success. If
the SIE encounters an error in the data, it automatically indi-
cates no response instead of supplying a handshake PID.
This instructs the host to retransmit the data at a later time.
Serial
Interface
Engine
(SIE)
D+
D-
USB
Transceiver
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18 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Introducing EZ-USB®
To send data to the host, the SIE accepts bytes and control
signals from the USB device, formats it for USB transfer, and
sends it over D+ and D-. Because USB uses a self-clocking
data format (NRZI), the SIE also inserts bits at appropriate
places in the bit stream to guarantee a certain number of
transitions in the serial data. This is called ‘bit stuffing,’ and
is handled automatically by the EZ-USB’s SIE.
One of the most important features of the EZ-USB family is
that its configuration is soft. Instead of requiring ROM or
other fixed memory, it contains internal program/data RAM
which can be loaded over the USB. This makes modifica-
tions, specification revisions, and updates a snap.
The EZ-USB’s ‘smart’ SIE performs much more than the
basic functions shown in Figure 1-6; it can perform a full
enumeration by itself, which allows the EZ-USB to connect
as a USB device and download code into its RAM while its
CPU is held in reset. This added SIE functionality is also
made available to the EZ-USB programmer, to make devel-
opment easier and save code and processing time.
1.10 ReNumeration™
Because the EZ-USB’s configuration is ‘soft’, one chip can
take on the identities of multiple distinct USB devices.
When first plugged into USB, the EZ-USB enumerates auto-
matically and downloads firmware and USB descriptor
tables over the USB cable. Next, the EZ-USB enumerates
again, this time as a device defined by the downloaded infor-
mation. This patented two-step process, called ReNumera-
tion™, happens instantly when the device is plugged in, with
no hint that the initial download step has occurred.
Alternately, EZ-USB can also load its firmware from an
external EEPROM.
The Enumeration and ReNumeration™ chapter on page 51
describes these processes in detail.
1.11 EZ-USB Architecture
Figure 1-7. EZ-USB 56-Pin Package Simplified Block Diagram
The EZ-USB packs all the intelligence required by a USB
peripheral interface into a compact integrated circuit. As
Figure 1-7 illustrates, an integrated USB transceiver con-
nects to the USB bus pins D+ and D-. A Serial Interface
Engine (SIE) decodes and encodes the serial data and per-
forms error correction, bit stuffing, and the other signaling-
level tasks required by USB. Ultimately, the SIE transfers
parallel data to and from the USB interface.
The EZ-USB FX2LP SIE operates at full-speed (12 Mbps)
and high-speed (480 Mbps) rates. The EZ-USB FX1 SIE
operates at the full-speed (12 Mbps) rate only. To accommo-
date the increased bandwidth of USB 2.0, the EZ-USB end-
point FIFOs and slave FIFOs (which interface to external
logic or processors) are unified to eliminate internal data
transfer times.
The CPU is an enhanced 8051 with fast execution time and
added features. It uses internal RAM for program and data
storage.
The role of the CPU in a typical EZ-USB-based USB periph-
eral is two fold:
■It implements the high-level USB protocol by servicing
host requests over the control endpoint (endpoint zero)
■It is available for general-purpose system use
The high-level USB protocol is not bandwidth-critical, so the
EZ-USB’s CPU is well-suited for handling host requests over
Serial
Interface
Engine
(SIE)
USB
Transceiver
D+
D-
USB
Connector
OUT
data
IN
data
I/O Ports
USB
Interface
Slave
FIFOs
Program &
Data
RAM
EZ-USB GPIF
8/16
CPU
(Enhanced
8051)
CTL RDY
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 19
Introducing EZ-USB®
the control endpoint. However, the data rates offered by
USB are too high for the CPU to process the USB data
directly. For this reason, the CPU is not usually in the high-
bandwidth data path between endpoint FIFOs and the exter-
nal interface. Note Instead, the CPU simply configures the
interface, then ‘gets out of the way’ while the unified EZ-
USB FIFOs move the data directly between the USB and
the external interface.
The FIFOs can be controlled by an external master, which
either supplies a clock and clock-enable signals to operate
synchronously, or strobe signals to operate asynchronously.
Alternately, the FIFOs can be controlled by an internal EZ-
USB timing generator called the General Programmable
Interface (GPIF). The GPIF serves as an ‘internal’ master,
interfacing directly to the FIFOs and generating user-pro-
grammed control signals for the interface to external logic.
Additionally, the GPIF can be made to wait for external
events by sampling external signals on its RDY pins. The
GPIF runs much faster than the FIFO data rate to give good
programmable resolution for the timing signals. It can be
clocked from either the internal EZ-USB clock or an exter-
nally supplied clock.
The EZ-USB’s CPU is rich in features. Up to five I/O ports
are available, as well as two USARTs, three counter/timers,
and an extensive interrupt system. It runs at a clock rate of
up to 48 MHz and uses four clocks per instruction cycle
instead of the twelve required by a standard 8051.
The EZ-USB chip family uses an enhanced SIE/USB inter-
face which simplifies EZ-USB code by implementing much
of the USB protocol. In fact, the EZ-USB can function as a
full USB device even without firmware.
All EZ-USB family chips operate at 3.3V. This simplifies the
design of bus-powered USB devices, since the 5V power
available at the USB connector (which the USB Specifica-
tion allows to be as low as 4.4V) can drive a 3.3V regulator
to deliver clean, isolated power to the EZ-USB chip.
EZ-USB is available in a 128-pin package which brings out
the 8051 address bus, data bus, and control signals to allow
connection of external memory and/or memory-mapped I/O.
Figure 1-8 is a block diagram for this package; The
Memory chapter on page 71, gives full details of the exter-
nal-memory interface.
Figure 1-8. EZ-USB 128-Pin Package Simplified Block Diagram
Serial
Interface
Engine
(SIE)
USB
Transceiver
D+
D-
USB
Connector
OUT
data
IN
data
USB
Interface
Slave
FIFOs
Program &
Data
RAM
EZ-USB GPIF
8/16
CTL RDY
Address Bus
Data Bus
Off-Chip
Memory
I/O Ports
CPU
(Enhanced
8051)
20 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Introducing EZ-USB®
1.12 EZ-USB Feature Summary
The EZ-USB chips include the following features:
■Low power consumption enabling bus-powered designs
■For EZ-USB FX2LP, an on-chip 480 Mbps transceiver.
For EZ-USB FX1, an on-chip 12 Mbps transceiver. Both
devices contain a PLL and SIE—the entire USB physical
layer (PHY).
■Double-, triple- and quad-buffered endpoint FIFOs
accommodate the 480 Mbps USB data rate
■Built in, enhanced 8051 running at up to 48 MHz
❐Fully featured: 256 bytes of register RAM, two
USARTs, three timers, two data pointers
❐Fast: four clocks (83.3 ns at 48 MHz) per instruction
cycle
❐SFR access to control registers (including I/O ports)
that require high speed
❐USB-vectored interrupts for low ISR latency
❐Used for USB housekeeping and control, not to
move high-speed data
■‘Soft’ operation—USB firmware can be downloaded over
USB, eliminating the need for hard coded memory
■Four interface FIFOs that can be internally or externally
clocked. The endpoint and interface FIFOs are unified to
eliminate data transfer time between USB and external
logic.
■General Programmable Interface (GPIF), a microcoded
state machine which serves as a timing master for a
glueless interface to the EZ-USB FIFOs
■ECC Generation based on the SmartMedia™ standard
The EZ-USB family offers single-chip USB 2.0 peripheral
solutions. Unlike designs that use an external PHY, the EZ-
USB integrates everything on one chip, eliminating costly
high pin-count packages and the need to route high speed
signals between chips.
1.13 EZ-USB Integrated
Microprocessor
The EZ-USB’s CPU uses on-chip RAM as program and data
memory. The Memory chapter on page 71, describes the
various internal/external memory options.
The CPU communicates with the SIE using a set of registers
occupying on-chip RAM addresses 0xE500-0xE6FF. These
registers are grouped and described by function in individual
chapters of this reference manual and summarized in regis-
ter order. See chapter “Registers” on page 211.
The CPU has two duties. First, it participates in the protocol
defined in the Universal Serial Bus Specification Version
2.0, Chapter 9, USB Device Framework. Thanks to the EZ-
USB’s ‘smart’ SIE, the firmware associated with the USB
protocol is simplified, leaving code space and bandwidth
available for the CPU’s primary duty—to help implement
your device. On the device side, abundant input/output
resources are available, including I/O ports, USARTs, and
an I2C bus master controller. These resources are
described in the Input/Output chapter on page 181, and the
Timers/Counters and Serial Interface chapter on page 193.
It is important to recognize that the EZ-USB architecture is
such that the CPU sets up and controls data transfers, but it
normally does not participate in high bandwidth transfers. It
is not in the data path; instead, the large data FIFOs that
handle endpoint data connect directly to outside interfaces.
To make the interface versatile, a programmable timing gen-
erator (GPIF, General Programmable Interface) can create
user-programmed waveforms for high bandwidth transfers
between the internal FIFOs and external logic.
The EZ-USB chips add eight interrupt sources to the stan-
dard 8051 interrupt system:
■INT2: USB Interrupt
■INT3: I2C Bus Interrupt
■INT4: FIFO/GPIF Interrupt
■INT4: External Interrupt 4
■INT5: External Interrupt 5
■INT6: External Interrupt 6
■USART1: USART1 Interrupt
■WAKEUP: USB Resume Interrupt
The EZ-USB chips provide 27 individual USB-interrupt
sources which share the INT2 interrupt, and 14 individual
FIFO/GPIF-interrupt sources which share the INT4 interrupt.
To save the code and processing time which normally would
be required to identify an individual interrupt source, the EZ-
USB provides a second level of interrupt vectoring called
Autovectoring. Each INT2 and INT4 interrupt source has its
own autovector, so when an interrupt requires service, the
proper ISR (interrupt service routine) is automatically
invoked. The Interrupts chapter on page 59 describes the
EZ-USB interrupt system.
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 21
Introducing EZ-USB®
1.14 EZ-USB Block Diagram
Figure 1-9. EZ-USB Block Diagram
8051
48 MHz
16 KB
Pgm/Data
RAM
4 KB
Endpoint
RAM
port D
GPIFFIFOS
16
General Programmable Interface
(e.g. ATA, EPP, etc.)
USB regs
0.5K Data
RAM
port B
port A
8
7
14
port E
port C
8
1
16
4
Ext
Clock
D+ D-
Data(8)
Addr(16)
SIO
2
i2c SIO
2
PHY
Interface
24 MHz
crystal
USB
2.0
PHY
PLL
2
22 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Introducing EZ-USB®
1.15 Packages
EZ-USB is available in five packages.
Figure 1-10. 56-Pin QFN, 56-Pin VFBGA, 56-Pin SSOP, 100-Pin, and 128-Pin EZ-USB Packages
1.15.1 56-Pin Packages
Twenty-four general-purpose I/O pins (ports A, B, and D) are
available. Sixteen of these I/O pins can be configured as the
16 bit data interface to the EZ-USB’s internal high-speed 16-
bit FIFOs, which can be used to implement low cost, high-
performance interfaces such as ATAPI, UTOPIA, EPP, etc.
The 56-pin packages have the following:
■Three 8-bit I/O ports: PORTA, PORTB, and PORTD
■I2C™ bus
■An 8- or 16-bit General Programmable Interface (GPIF)
multiplexed onto PORTB and PORTD, with five non-mul-
tiplexed control signals
■Four 8- or 16-bit Slave FIFOs, with five non-multiplexed
control signals and four or five control signals multi-
plexed with PORTA
1.15.2 CY7C68013A/14A and
CY7C68015A/16A Differences
Two additional GPIO signals are available on the
CY7C68015A and CY7C68016A to provide more flexibility
when neither IFCLK or CLKOUT are needed in the 56-pin
package. The CY7C68015A and CY7C68016A is only avail-
able in the 56-pin package options.
1.15.3 100-Pin Package
The 100-pin package adds functionality to the 56-pin pack-
age:
■Two additional 8-bit I/O ports: PORTC and PORTE
■Seven additional GPIF Control (CTL) and Ready (RDY)
signals
■Nine non-multiplexed peripheral signals (two USARTs,
three timer inputs, INT4, and INT5#)
■Eight additional control signals multiplexed onto PORTE
■Nine GPIF address lines, multiplexed onto PORTC
(eight) and PORTE (one)
■RD# and WR# signals which may be used as read and
write strobes for PORTC
128
TQFP
14x20x1.4
mm
56
SSOP
18x8x2.3
mm
100
TQFP
14x20x1.4
mm
56-pin VFBGA
5x5x1
mm
56-pin QFN
8x8x1
mm
Table 1-2. CY7C68013A/14A and CY7C68015A/16A Pin
Differences
CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A
IFCLK PE0
CLKOUT PE1
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 23
Introducing EZ-USB®
1.15.4 128-Pin Package
The 128-pin package adds the 8051 address and data
buses and control signals. The RD#, PSEN#, and WR#
strobes are standard 8051 control strobes, serving as read/
write strobes for external memory attached to the 8051
address and data buses. The EZ-USB encodes the CS# and
OE# signals to automatically exclude external access to
memory spaces which exist on-chip, and optionally to com-
bine off-chip data- and code-memory read accesses. The
128-pin package adds the following:
■16-bit 8051 address bus
■8-bit 8051 data bus
■Address/data bus control signals
1.15.5 Signals Available in the Five
Packages
Three interface modes are available: Ports, GPIF Master,
and Slave FIFO.
Figure 1-11 shows a logical diagram of the signals available
in the five packages. The signals on the left edge of the dia-
gram are common to all interface modes with the noted dif-
ferences between the CY7C68013A and the CY7C68015A,
while the signals on the right are specific to each mode. The
interface mode is software-selectable via an internal mode
register.
In ‘Ports’ mode, all the I/O pins are general-purpose I/O
ports.
‘GPIF master’ mode uses the PORTB and PORTD pins as a
16-bit data interface to the four EZ-USB endpoint FIFOs
EP2, EP4, EP6 and EP8. In this ‘master’ mode, the EZ-USB
FIFOs are controlled by the internal GPIF, a programmable
waveform generator that responds to FIFO status flags,
drives timing signals using its CTL outputs, and waits for
external conditions to be true on its RDY inputs. Note that
only a subset of the GPIF signals (CTL0-2, RDY0-1) are
available in the 56-pin packages, while the full set (CTL0-5,
RDY0-5) is available in the 100- and 128-pin packages.
In the ‘Slave FIFO’ mode, external logic or an external pro-
cessor interfaces directly to the EZ-USB endpoint FIFOs. In
this mode, the GPIF is not active, since external logic has
direct FIFO control. Therefore, the basic FIFO signals (flags,
selectors, strobes) are brought out on EZ-USB pins. The
external master can be asynchronous or synchronous, and
it may supply its own independent clock to the EZ-USB
interface.
The 100-pin package includes all the functionality of the 56-
pin packages, and brings out the two additional I/O ports
PORTC and PORTE as well as all the USART, Timer, Inter-
rupt, and GPIF signals. The RD# and WR# pins function as
PORTC strobes in the 100-pin package, and as expansion
memory strobes in the 128-pin package.
The 128-pin package adds 28 pins to the 100-pin package
to bring out the full 8051 expansion memory bus. This
allows for the connection of external memory for applica-
tions that run at power-on and before connection to USB.
The 128-pin package also provides the foundation for the
Cypress EZ-USB Development Kit boards, in which code is
developed using a debug monitor that runs in external RAM.
24 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Introducing EZ-USB®
Figure 1-11. Signals for the Five EZ-USB Package Types
RDY0
RDY1
CTL0
CTL1
CTL2
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
56
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
T2
T1
T0
100
D7
D6
D5
D4
D3
D2
D1
D0
EA
128
RD#
WR#
CS#
OE#
PSEN#
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
**PE0
**PE1
IFCLK
CLKOUT
DPLUS
DMINUS
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
SLRD
SLWR
FLAGA
FLAGB
FLAGC
INT0#/ PA0
INT1#/ PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
Port GPIF Master Slave FIFO
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
** pinout for CY7C68015A/CY7C68016A only
**PE0 replaces IFCLK
on CY7C68015A/16A
& PE1 replaces CLKOUT
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 25
Introducing EZ-USB®
1.16 Package Diagrams
Figure 1-12. 128-Pin TQFP Pin Assignment
128-pin TQFP
* denotes programmable polarity
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
VCC
D4
D3
D2
D1
D0
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
CS#
WR#
RD#
PSEN#
OE#
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
PD0/FD8
*W AKEUP
VCC
RESET#
CTL5
A3
A2
A1
A0
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
D7
D6
D5
PA3/*W U2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
0
PD 1/F D 9
PD 2/F D 1 0
PD 3/F D 1 1
INT5#
VC C
PE 0/T 0O U T
PE 1/T 1O U T
PE 2/T 2O U T
PE3/RXD0OUT
PE4/RXD1OUT
PE 5/INT 6
PE 6/T 2E X
PE 7/GP IFAD R 8
GND
A4
A5
A6
A7
PD 4/F D 1 2
PD 5/F D 1 3
PD 6/F D 1 4
PD 7/F D 1 5
GND
A8
A9
A1
RDY0/*SLRD
RDY1/*SLW R
RESERVED
CLKOUT
VCC
GND
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGN D
NC
NC
NC
AVCC
DPLUS
DMINUS
AGND
A11
A12
A13
A14
A15
VCC
GND
INT4
T0
T1
T2
*IFCLK
BKPT
EA
SCL
SDA
26 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Introducing EZ-USB®
Figure 1-13. 100-Pin TQFP Pin Assignment
100-pin TQFP
* denotes programmable polarity
GND
VCC
GND
PB7 /F D7
PB6 /F D6
PB5 /F D5
PB4 /F D4
RX D1
TX D1
RX D0
TX D0
GND
VCC
PB3 /F D3
PB2 /F D2
PB1 /F D1
PB0 /F D0
VCC
WR#
RD#
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PD0/FD8
*W AKEUP
VCC
RESET#
CTL5
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*W U2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGN D
NC
NC
NC
AVCC
DPLUS
DMINUS
AGN D
VCC
GND
INT4
T0
T1
T2
*IFCLK
RESERVED
BKPT
SCL
SDA
PD1/FD9
PD2/FD10
PD3/FD11
IN T 5 #
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 27
Introducing EZ-USB®
Figure 1-14. 56-Pin SSOP Pin Assignment
* Programmable polarity
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
*IFCLK
RESERVED
SCL
SDA
VCC
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
*WAKEUP
VCC
RESET#
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
56-pin SSOP
28 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Introducing EZ-USB®
Figure 1-15. 56-Pin QFN Pin Assignment
* Programmable polarity
** CY7C68015A/16A pinout
56-pin QFN
GND
VCC
AGND
DMINUS
RDY1/*SLWR
DPLUS
AVCC
AGND
RDY0/*SLRD
AVCC
XTALIN
XTALOUT
*IFCLK/**PE0
RESERVED
CLKOUT/**PE1
GND
PD7/FD15
PD6/FD14
*WAKEUP
PD5/FD13
PD4/FD12
PD3/FD11
VCC
PD0/FD8
PD2/FD10
PD1/FD9
VCC
GND
VCC
PB0FD0
PB1/FD1
PB2/FD2
VCC
PB3/FD3
PB4/FD4
PB5/FD5
GND
GND
PB6/FD6
PB7/FD7
SDA
SCL
CTL2/*FLAGC
VCC
PA0/INT0#
PA1/INT1#
GND
PA2/*SLOE
PA3/*WU2
PA4/FIFOADR0
RESET#
PA7/*FLAGD/SLCS#
PA5/FIFOADR1
PA6/*PKTEND
CTL1/*FLAGB
CTL0/*FLAGA
31
32
33
34
41
35
36
37
42
40
38
39
30
29
17
18
19
20
27
21
22
23
28
26
24
25
16
15
12
11
10
9
2
8
7
6
1
3
5
4
13
14
54
53
52
51
44
50
49
48
43
45
47
46
55
56
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 29
Introducing EZ-USB®
Figure 1-16. 56-Pin VFBGA Pin Assignment
12345678
A
B
C
D
E
F
G
H
1A 2A 3A 4A 5A 6A 7A 8A
1B 2B 3B 4B 5B 6B 7B 8B
1C 2C 3C 4C 5C 6C 7C 8C
1D 2D 7D 8D
1E 2E 7E 8E
1F 2F 3F 4F 5F 6F 7F 8F
1G 2G 3G 4G 5G 6G 7G 8G
1H 2H 3H 4H 5H 6H 7H 8H
30 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Introducing EZ-USB®
1.17 EZ-USB Endpoint Buffers
The USB Specification defines an endpoint as a source or
sink of data. Since USB is a serial bus, a device endpoint is
actually a FIFO which sequentially empties or fills with USB
data bytes. The host selects a device endpoint by sending a
4-bit address and a direction bit. Therefore, USB can
uniquely address 32 endpoints, IN0 through IN15 and OUT0
through OUT15.
From the EZ-USB’s point of view, an endpoint is a buffer full
of bytes received or held for transmission over the bus. The
EZ-USB reads host data from an OUT endpoint buffer, and
writes data for transmission to the host to an IN endpoint
buffer.
EZ-USB contains three 64-byte endpoint buffers, plus 4 KB
of buffer space that can be configured 12 ways, as indicated
in Figure 1-17. The three 64-byte buffers are common to all
configurations.
The three 64-byte buffers are designated EP0, EP1IN and
EP1OUT. EP0 is the default CONTROL endpoint, a bidirec-
tional endpoint that uses a single 64-byte buffer for both IN
and OUT data. EZ-USB firmware reads or fills the EP0 buf-
fer when the (optional) data stage of a CONTROL transfer is
required.
Note The eight SETUP bytes in a CONTROL transfer do not
appear in the 64-byte EP0 endpoint buffer. Instead, to sim-
plify programming, the EZ-USB automatically stores the
eight SETUP bytes in a separate buffer (SETUPDAT, at
0xE6B8-0xE6BF).
EP1IN and EP1OUT use separate 64 byte buffers. EZ-USB
firmware can configure these endpoints as BULK or INTER-
RUPT. These endpoints, as well as EP0, are accessible only
by EZ-USB firmware. This is in contrast to the large endpoint
buffers EP2, EP4, EP6 and EP8, which are designed to
move high bandwidth data directly on and off chip without
firmware intervention.
Endpoints 2, 4, 6 and 8 are the large, high bandwidth, data
moving endpoints. They can be configured in various ways
to suit bandwidth requirements. The shaded boxes in
Figure 1-17 enclose the buffers to indicate double, triple, or
quad buffering. Double buffering means that one packet of
data can be filling or emptying with USB data while another
packet (from the same endpoint) is being serviced by exter-
nal interface logic. Triple buffering adds a third packet buffer
to the pool, which can be used by either side (USB or inter-
face) as needed. Quad buffering adds a fourth packet buffer.
Multiple buffering can significantly improve USB bandwidth
performance when the data supplying and consuming rates
are similar, but bursty; it smooths out the bursts, reducing or
eliminating the need for one side to wait for the other.
Figure 1-17. EZ-USB Endpoint Buffers
64 64 64 64 64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64 64 64 64 64
64
512
512
1024
1024
1024
1024
1024
1024
1024
512
512
512
512
512
512
512
512
512
512
EP2 EP2 EP2
EP6
EP6
EP8 EP8
EP0 IN & OUT
EP1 IN
EP1 OUT
1024
1024
EP6 1024
512
EP8
512
512
EP6
512
512
512
512
EP2
512
512
EP4
512
512
EP2
512
512
EP4
512
512
EP2
512
512
EP4
512
512
EP2
512
512
512
512
EP2
512
512
512
512
EP2
512
512
1024
EP2
1024
1024
EP2
1024
1024
EP2
1024
512
512
EP6
1024
1024
EP6
512
512
EP8
512
512
EP6
512
512
512
512
EP6
1024
1024
EP6
512
512
EP8
512
512
EP6
512
512
64 64 64 64 64 64 64 64 64 64 64
12345678 9 10 11 12
512
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 31
Introducing EZ-USB®
Endpoints 2, 4, 6 and 8 can be configured using the choices
shown in Table 1-3.
When the EZ-USB operates at full speed (12 Mbps), some
or all of the endpoint buffer bytes shown in Figure 1-17 may
be employed, depending on endpoint type.
Note Regardless of the physical buffer size, each endpoint
buffer accommodates only one full-speed packet.
For example, if EP2 is used as a full-speed BULK endpoint,
the maximum number of bytes (maxPacketSize) it can
accommodate is 64, even though the physical buffer size is
512 or 1024 bytes (it makes sense, therefore, to configure
full-speed BULK endpoints as 512 bytes rather than 1024,
so that fewer unused bytes are wasted). An ISOCHRO-
NOUS full-speed endpoint, on the other hand, could fully
use either a 512- or 1024-byte buffer.
1.18 External FIFO Interface
The large data FIFOs (endpoints 2, 4, 6 and 8) in the
EZ-USB are designed to move high-speed (480 Mbps) USB
data on and off chip without introducing any bandwidth bot-
tlenecks. They accomplish this goal by implementing the fol-
lowing features:
1. Direct interface with outside logic, with the EZ-USB’s
CPU out of the data path.
2. ‘Quantum FIFO’ architecture instantaneously moves
(commits) packets between the USB and the FIFOs.
3. Versatile interfaces: Slave FIFO (external master) or
GPIF (internal master), synchronous or asynchronous
clocking, internal or external clocks, etc.
The firmware sets switches to configure the outside FIFO
interface, and then generally does not participate in moving
the data into and out of the FIFOs.
To understand the ‘Quantum FIFO’, it is necessary to refer
to two data domains, the USB domain and the Interface
domain. Each domain is independent, allowing different
clocks and logic to handle its data.
The USB domain is serviced by the SIE, which receives and
delivers FIFO data packets over the two-wire USB bus. The
USB domain is clocked using a reference derived from the
24 MHz crystal attached to the EZ-USB chip.
The Interface domain loads and unloads the endpoint
FIFOs. An external device such as a DSP or ASIC can sup-
ply its own clock to the FIFO interface, or the EZ-USB’s
internal interface clock (IFCLK) can be supplied to the inter-
face.
The classic solution to the problem of reconciling two differ-
ent and independent clocks is to use a FIFO. The EZ-USB’s
FIFOs have an unusual property: They are Quantum FIFOs,
which means that data is committed to the FIFOs in USB-
size packets, rather than one byte at a time. This is invisible
to the outside interface, since it services the FIFOs just like
any ordinary FIFO (i.e., by checking full and empty flags).
The only minor difference is that when an empty flag goes
from 1 (empty) to 0 (not empty), the number of bytes in the
FIFO jumps to a USB packet size, rather than just one byte.
EZ-USB Quantum FIFOs may be moved between data
domains almost instantaneously. The Quantum nature of the
FIFOs also simplifies error recovery. If endpoint data were
continuously clocked into an interface FIFO, some of the
packet data might have already been clocked out by the
time an error is detected at the end of a USB packet. By
switching FIFO data between the domains in USB-packet-
size blocks, each USB packet can be error-checked (and
retried, if necessary) before it’s committed to the other
domain.
Figure 1-18 on page 32 and Figure 1-19 on page 33 illus-
trate the two methods by which external logic interfaces to
the endpoint FIFOs EP2, EP4, EP6 and EP8.
Table 1-3. Endpoint 2, 4, 6, and 8 Configuration Choices
Characteristic Choices
Direction IN, OUT
Type Bulk, Interrupt, Isochronous
Buffering Double, Triple, Quad
32 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Introducing EZ-USB®
Figure 1-18. EZ-USB FIFOs in Slave FIFO Mode
Figure 1-18 illustrates the outside-world view of the EZ-USB
data FIFOs configured as Slave FIFOs. The outside logic
supplies a clock, responds to the FIFO flags, and clocks
FIFO data in and out using the strobe signals. Optionally, the
outside logic may use the internal EZ-USB Interface Clock
(IFCLK) as its reference clock.
Three FIFO flags are shown in parentheses in Figure 1-18
because they actually are called FLAGA-FLAGD in the pin
diagram (there are four flag pins). Using configuration bits,
various FIFO flags can be assigned to these general-
purpose flag pins. The names shown in parentheses illus-
trate typical uses for these configurable flags. The Program-
mable Level Flag (PRGFLAG) can be set to any value to
indicate degrees of FIFO ‘fullness’. The outside interface
selects one of the four FIFOs using the FIFOADR pins, and
then clocks the 16-bit FIFO data using the SLRD (Slave
Read) and SLWR (Slave Write) signals. PKTEND is used to
dispatch a short (less than max packet size) IN packet to
USB.
Synchronous
Asynchronous
SLRD
SLWR
PKTEND
IFCLK
SLRD
SLWR
PKTEND
FIFO
FD[15:0] Data
(OUTEMPTY)
(INFULL)
(PRGFLAG)
IFCLK
SLRD
SLWR
SLOE
PKTEND
FIFOADR1
FIFOADR0
EP8
EP6
EP4
EP2
select
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 33
Introducing EZ-USB®
Figure 1-19. EZ-USB FIFOs in GPIF Master Mode
External systems that connect to the EZ-USB FIFOs must
provide control circuitry to select FIFOs, check flags, clock
data, etc. The EZ-USB contains a sophisticated control unit
(the General Programmable Interface, or GPIF) which can
replace this external logic. In the GPIF Master FIFO mode,
(Figure 1-19), the GPIF reads the FIFO flags, controls the
FIFO strobes, and presents a user-customizable interface to
the outside world. The GPIF runs at a very high speed (up to
48 MHz clock rate) so that it can develop high-resolution
control waveforms. It can be clocked from one of two inter-
nal sources (30 or 48 MHz) or from an external clock.
Control (CTL) signals are programmable waveform outputs,
and ready (RDY) signals are input pins that can be tested
for conditions that cause the GPIF to pause and resume
operation, implementing ‘wait states’. GPIFADR pins pres-
ent a 9-bit address to the interface that may be incremented
as data is transferred. The 8051 INT signal is a ‘hook’ that
can signal the EZ-USB’s CPU in the middle of a transaction;
GPIF operation resumes once the CPU asserts its own 8051
RDY signal. This ‘hook’ permits great flexibility in the gener-
ation of GPIF waveforms.
FIFO
FD[15:0] Data
EP8
EP6
EP4
EP2
GPIF
FLAGS
CTL
RDY
6
6
GPIFADR
9
30 MHz
48 MHz IFCLK
IFCLK
SLRD
8051 RDY
8051 INT
select
SLWR
SLOE
SLRD
34 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Introducing EZ-USB®
1.19 EZ-USB Product Family
The EZ-USB family is available in various pinouts and operational modes to serve different system requirements and costs.
Table 1-4. EZ-USB FX2LP Part Numbers (Full Speed and High Speed)
Part Number Package RAM ISO
Support I/O Bus Width Data/Address Bus
Ideal for battery powered applications
CY7C68014A-128AXC 128-pin TQFP – Pb-Free 16K Bytes Yes 40 16/8 Bit 8051 Address/Data Bus
CY7C68014A-100AXC 100-pin TQFP – Pb-Free 16K Bytes Yes 40 – No
CY7C68014A-56PVXC 56-pin SSOP – Pb-Free 16K Bytes Yes 24 – No
CY7C68014A-56LFXC 56-pin QFN – Pb-Free 16K Bytes Yes 24 – No
CY7C68016A-56LFXC 56-pin QFN – Pb-Free 16K Bytes Yes 26 – No
Ideal for nonbattery powered applications
CY7C68013A-128AXC 128-pin TQFP – Pb-Free 16K Bytes Yes 40 16/8 Bit 8051 Address/Data Bus
CY7C68013A-128AXI 128-pin TQFP – Pb-Free (Industrial) 16K Bytes Yes 40 16/8 Bit 8051 Address/Data Bus
CY7C68013A-100AXC 100-pin TQFP – Pb-Free 16K Bytes Yes 40 – No
CY7C68013A-100AXI 100-pin TQFP – Pb-Free (Industrial) 16K Bytes Yes 40 – No
CY7C68013A-56PVXC 56-pin SSOP – Pb-Free 16K Bytes Yes 24 – No
CY7C68013A-56PVXI 56-pin SSOP – Pb-Free (Industrial) 16K Bytes Yes 24 – No
CY7C68013A-56LFXC 56-pin QFN – Pb-Free 16K Bytes Yes 24 – No
CY7C68013A-56LFXI 56-pin QFN – Pb-Free (Industrial) 16K Bytes Yes 24 – No
CY7C68015A-56LFXC 56-pin QFN – Pb-Free 16K Bytes Yes 26 – No
CY7C68013A-56BAXC 56 VFBGA – Pb-Free 16K Bytes Yes 24 – No
Table 1-5. EZ-USB FX1 Part Numbers (Full Speed Only)
Part Number Package RAM ISO
Support I/O Bus Width Data/Address Bus
Ideal for nonbattery powered applications
CY7C64713-128AXC 128-pin TQFP – Pb-Free 16K Bytes Yes 40 16/8 Bit 8051 Address/Data Bus
CY7C64713-100AXC 100-pin TQFP – Pb-Free 16K Bytes Yes 40 – No
CY7C64713-56LFXC 56-pin QFN – Pb-Free 16K Bytes Yes 24 – No
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 35
Introducing EZ-USB®
1.20 Document History
This section is a chronicle of the EZ-USB Technical Reference Manual for the EZ-USB FX2LP and EX-USB FX1 devices.
EZ-USB Technical Reference Manual History
Release Date Version Originator Description of Change
01/31/2003 1.4 ARI This manual has gone through several versions and is based on the EZ-USB FX2. The most recent
printing of this manual is Version 1.4.
09/11/2006 2.0 ARI The information in this manual is identical to version 1.4, but a new template was implemented as part
of the new corporate standard.
N/A 2.1 ARI The information in this manual is the same as the previous versions but it has a new Document History
section and it has an index. This version was not released.
03/19/2007 ** ARI This manual is a new document to the Cypress Document Control (Revision **) system; it is the same
as version 2.1. This document has been issued the document number 001-13670
02/21/2008 *A CMCC Delete references to CY7C64714. Remove T0OUT and T1OUT from 56-pin QFN. Add industrial part
numbers to product list. Change FIFORESET procedures to NAK all while resetting FIFO to avoid
potential race condition. Fix general typos and text formatting.
06/15/2009 *B DSG
Updated EP2 and EP6 byte capacity in Section 15.12.4. Corrected the Notes entry for E611 to Default:
BULK IN 64 in Appendix C, Pg 338. Corrected the Appendix A title in the Contents Section. Updated
the USBCS (USB Control and Status) register address 7FD6 to E680 in section 6.4. Modified Fig 10-
37 to remove the additional AUTOIN = 1 from the diagram in Section 10.4.6. Updated Bit 1 description
for INT4 in Section 15.7.12. Corrected AUTOOUT setting in point 5 of section 9.3.2. Corrected bit
descriptions in section 15.12.5 through 15.12.8. Added sections 9.3.12 and 9.3.13. Reformatted to
match current template.
09/08/2010 *C DSG
Changed 4x to 2x in section 9.2.7. Added bit 7 functionality to section 3.5 EEPROM Configuration
Byte. Changed FIFORESET = 0x86 to 0x88 in Figure 9-40. Added Contents Overview. Updated Note
in section 8.4. Added Note in section 15.6.3. Updated Bit 3 AUTOIN Description in section 15.6.4.
Updated Bit 2 BERR Description in Section 13.5.2.1 and 15.8.4.
02/04/2011 *D ODC Fixed Figure 10-18
04/24/2014 *E DBIR Sunset review; no content updates
05/10/2017 *F DBIR Updated logo and copyright; no content updates
36 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Introducing EZ-USB®
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 37
2. Endpoint Zero
2.1 Introduction
Endpoint zero has special significance in a USB system. It is a CONTROL endpoint, and it is required by every USB device.
The USB host uses special SETUP tokens to signal transfers that deal with device control; only CONTROL endpoints accept
these special tokens.
The USB host sends a suite of standard device requests over endpoint zero. These standard requests are fully defined in
Chapter 9 of the USB Specification. This chapter describes how the EZ-USB chip handles endpoint zero requests.
The EZ-USB provides extensive hardware support for handling endpoint-zero operations; this chapter describes those opera-
tions and the EZ-USB resources that simplify the firmware which handles them.
Endpoint zero is the only CONTROL endpoint supported by the EZ-USB. CONTROL endpoints are bidirectional, so the
EZ-USB provides a single 64-byte buffer, EP0BUF, which firmware handles exactly like a bulk endpoint buffer for the data
stages of a CONTROL transfer. A second 8-byte buffer called SETUPDAT, which is unique to endpoint zero, holds data that
arrives in the SETUP stage of a CONTROL transfer. This relieves the EZ-USB firmware of the burden of tracking the three
CONTROL transfer phases (SETUP, DATA, and STATUS). The EZ-USB also generates separate interrupt requests for the
various transfer phases, further simplifying code.
Endpoint zero is always enabled and accessible by the USB host.
2.2 Control Endpoint EP0
Endpoint zero accepts a special SETUP packet, which contains an 8-byte data structure that provides host information about
the CONTROL transaction. CONTROL transfers include a final STATUS phase, constructed from standard PIDs (IN/OUT,
DATA1, and ACK/NAK).
Some CONTROL transactions include all required data in their 8-byte SETUP Data packet. Other CONTROL transactions
require more OUT data than fit into the eight bytes, or require IN data from the device. These transactions use standard bulk-
like transfers to move the data. Note in Figure 2-1 on page 38 that the DATA Stage looks exactly like a bulk transfer. As with
BULK endpoints, the endpoint zero byte count registers must be loaded to ACK each data transfer stage of a CONTROL
transfer.
The STATUS stage consists of an empty data packet with the opposite direction of the data stage, or an IN if there was no
data stage. This empty data packet gives the device a chance to ACK or NAK the entire CONTROL transfer.
The HSNAK bit holds off the completion of a CONTROL transfer until the device has had time to respond to a request. For
example, if the host issues a Set_Interface Request, the EZ-USB firmware performs various housekeeping chores such as
adjusting internal modes and re-initializing endpoints. During this time, the host issues handshake (STATUS stage) packets to
which the EZ-USB automatically responds with NAKs, indicating ‘busy.’ When the firmware completes its housekeeping oper-
ations, it clears the HSNAK bit (by writing ‘1’ to it), which instructs the EZ-USB to ACK the STATUS stage, terminating the
transfer. This handshake prevents the host from attempting to use an interface before it is fully configured.
To perform an endpoint stall for the DATA or STATUS stage of an endpoint zero transfer (the SETUP stage can never stall),
firmware must set both the STALL and HSNAK bits for endpoint zero.
38 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Endpoint Zero
Figure 2-1. A USB Control Transfer (With Data Stage)
Some CONTROL transfers do not have a DATA stage.
Therefore, the code that processes the SETUP data should
check the length field in the SETUP data (in the 8-byte buffer
at SETUPDAT) and arm endpoint zero for the DATA phase
(by loading EP0BCH:L) only if the length field is non-zero.
Two interrupts provide notification that a SETUP packet has
arrived, as shown in Figure 2-2.
Figure 2-2. Two Interrupts Associated with EP0 CONTROL
Transfers
The EZ-USB asserts the SUTOK (Setup Token) interrupt
request when it detects the SETUP token at the beginning of
a CONTROL transfer. This interrupt is normally used for
debug only.
The EZ-USB asserts the SUDAV (Setup Data Available)
interrupt request when the eight bytes of SETUP data have
been received error-free and transferred to the SETUPDAT
buffer. The EZ-USB automatically takes care of any retries if
it finds errors in the SETUP data. These two interrupt
request bits must be cleared by firmware.
Firmware responds to the SUDAV interrupt request by either
directly inspecting the eight bytes at SETUPDAT or by trans-
ferring them to a local buffer for further processing. Servic-
ing the SETUP data should be a high priority, since the USB
Specification stipulates that CONTROL transfers must
always be accepted and never NAK’d. It is possible, there-
fore, that a CONTROL transfer could arrive while the firm-
ware is still servicing a previous one. In this case, the earlier
CONTROL transfer service should be aborted and the new
one serviced. The SUTOK interrupt gives advance warning
that a new CONTROL transfer is about to overwrite the eight
SETUPDAT bytes.
8051 clears HSNAK bit (writes 1 to it)
or sets the STALL bit.
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SETUP Stage
SUTOK Interrupt
EZ-USB sets HSNAK=1
SUDAV Interrupt
DATA Stage
EP0-IN Interrupt EP0-IN Interrupt
STATUS Stage
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SUTOK
Interrupt SUDAV
Interrupt
8 RAM
bytes
SETUPDAT
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 39
Endpoint Zero
Figure 2-3. Registers Associated with EP0 Control Transfers
If the firmware stalls endpoint zero (by setting the STALL
and HSNAK bits to 1), the EZ-USB automatically clears the
stall bit when the next SETUP token arrives.
Like all EZ-USB interrupt requests, the SUTOK and SUDAV
bits can be directly tested and cleared by the firmware
(cleared by writing ‘1’) even if their corresponding interrupts
are disabled. Figure 2-3 shows the EZ-USB registers that
are associated with CONTROL transactions over EP0.
These registers augment those associated with normal bulk
transfers, which are described in the Access to Endpoint
Buffers chapter on page 87.
Two bits in the USBIE (USB Interrupt Enable) register
enable the SETUP Token (SUTOK) and SETUP Data Avail-
able interrupts. The actual interrupt-request bits are in the
USBIRQ (USB Interrupt Requests) register.
The EZ-USB transfers the eight SETUP bytes into eight
bytes of RAM at SETUPDAT. A 16-bit pointer, SUDPTRH:L,
provides hardware assistance for handling CONTROL IN
transfers, in particular the ‘Get Descriptor’ requests
described later in this chapter.
2.3 USB Requests
The Universal Serial Bus Specification Version 2.0, Chapter
9, USB Device Framework defines a set of Standard Device
Requests. When the firmware is in control of endpoint zero
(RENUM=1), the EZ-USB handles only one of these
requests (Set Address) automatically; it relies on the firm-
ware to support all of the others. The firmware acts on
device requests by decoding the eight bytes contained in the
SETUP packet and available at SETUPDAT. Table 2-1
defines these eight bytes.
The Byte column in Table 2-1 shows the byte offset from
SETUPDAT. The Field column shows the different bytes in
the request, where the ‘bm’ prefix means bitmap, ‘b’ means
byte [8 bits, 0-255], and ‘w’ means word [16 bits, 0-65535].
Table 2-2 shows the different values defined for bRequest,
and how the firmware should respond to each request. The
remainder of this chapter describes each of the requests in
Table 2-2 in detail.
Note Table 2-2 applies when RENUM = 1, signifying that
the firmware, rather than the EZ-USB hardware, handles
device requests.
8 Bytes of
SETUP Data
Interrupt Enable:
Initialization
SETUPDAT
Data transfer
Registers Associated with Endpoint Zero
For handling SETUP transactions
7 6 5 4 3 2 1 0
EP0BCL
15 14 13 12 11 10 9 8
EP0BCH
15 14 13 12 11 10 9 8
SUDPTRH
7 6 5 4 3 2 1 0
SUDPTRL
USBIE T D
SUDPTRCTL A
A=SDP Auto
A
USBIRQ
Interrupt Request:
T
Interrupt Control
D
A
T=Setup Token
D=Setup Data
A=EP0 ACK
T=Setup Token
D=Setup Data
A=EP0 ACK
Table 2-1. The Eight Bytes in a USB SETUP Packet
Byte Field Meaning
0 bmRequestType Request Type, Direction, and Recipient.
1bRequest The actual request (see Table 2-2).
2 wValueL 16-bit value, varies according to bRequest.
3 wValueH
4 wIndexL 16-bit field, varies according to bRequest.
5 wIndexH
6 wLengthL Number of bytes to transfer if there is a data
phase.
7 wLengthH
40 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Endpoint Zero
.
In the ReNumerated condition (RENUM = 1), the EZ-USB
passes all USB requests except Set Address to the firmware
via the SUDAV interrupt.
The EZ-USB implements one vendor-specific request: ‘Firm-
ware Load,’ 0xA0 (the bRequest value of 0xA0 is valid only if
byte 0 of the request, bmRequestType, is also ‘x10xxxxx,’
indicating a vendor-specific request.) The 0xA0 firmware
load request may be used even after ReNumeration, but is
only valid while the 8051 is held in reset. If your application
implements vendor-specific USB requests, and you do not
wish to use the Firmware Load feature, be sure to refrain
from using the bRequest value 0xA0 for your custom
requests. The Firmware Load feature is fully described in
the Enumeration and ReNumeration™ chapter on page 51.
To avoid future incompatibilities, vendor requests 0xA0-
0xAF are reserved by Cypress Semiconductor.
2.3.1 Get Status
The USB Specification defines three USB status requests. A
fourth request, to an interface, is declared in the specifica-
tion as ‘reserved’. The four status requests are:
■Remote Wakeup (Device request)
■Self-Powered (Device request)
■Stall (Endpoint request)
■Interface request (reserved)
The EZ-USB automatically asserts the SUDAV interrupt to
tell the firmware to decode the SETUP packet and supply
the appropriate status information.
As Figure 2-4 illustrates, the firmware responds to the
SUDAV interrupt by decoding the eight bytes the EZ-USB
has copied into RAM at SETUPDAT. The firmware answers
a Get Status request (bRequest = 0) by loading two bytes
into the EP0BUF buffer and loading the byte count register
EP0BCH:L with the value 0x0002. The EZ-USB then trans-
mits these two bytes in response to an IN token. Finally, the
firmware clears the HSNAK bit (by writing ‘1’ to it), which
instructs the EZ-USB to ACK the status stage of the transfer.
Table 2-2. How the Firmware Handles USB Device Requests (RENUM =1)
bRequest Name EZ-USB Action Firmware Response
0x00 Get Status SUDAV Interrupt Supply RemWU, SelfPwr or Stall Bits
0x01 Clear Feature SUDAV Interrupt Clear RemWU, SelfPwr or Stall Bits
0x02 (reserved) none Stall EP0
0x03 Set Feature SUDAV Interrupt Set RemWU, SelfPwr or Stall Bits
0x04 (reserved) none Stall EP0
0x05 Set Address Update FNADDR Register none
0x06 Get Descriptor SUDAV Interrupt Supply table data over EP0-IN
0x07 Set Descriptor SUDAV Interrupt Application dependent
0x08 Get Configuration SUDAV Interrupt Send current configuration number
0x09 Set Configuration SUDAV Interrupt Change current configuration
0x0A Get Interface SUDAV Interrupt Supply alternate setting No. from RAM
0x0B Set Interface SUDAV Interrupt Change alternate setting No.
0x0C Sync Frame SUDAV Interrupt Supply a frame number over EP0-IN
Vendor Requests
0xA0 (Firmware Load) Upload / Download on-chip RAM ---
0xA1 to 0xAF SUDAV Interrupt Reserved by Cypress Semiconductor
All except 0xA0 SUDAV Interrupt Application dependent
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 41
Endpoint Zero
Figure 2-4. Data Flow for a Get_Status Request
The following tables show the eight SETUP bytes for Get
Status Requests.
Get Status-Device queries the state of two bits, ‘Remote
Wakeup’ and ‘Self-Powered’. The Remote Wakeup bit indi-
cates whether or not the device is currently enabled to
request remote wakeup (remote wakeup is explained in the
Power Management chapter on page 77). The Self-Pow-
ered bit indicates whether or not the device is self-powered
(as opposed to USB bus-powered).
The firmware returns these two bits by loading two bytes
into EP0BUF, then loading a byte count of 0x0002 into
EP0BCH:L.
Each endpoint has a STALL bit in its EPxCS register. If this
bit is set, any request to the endpoint returns a STALL hand-
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SETUP Stage
SUTOK
Interrupt SUDAV
Interrupt
DATA Stage
STATUS Stage
8 RAM
bytes
SETUPDAT
IN0BUF
64-byte
Buffer
2
IN0BC
A
C
K
H/S Pkt
A
C
K
H/S Pkt
Table 2-3. Get Status-Device (Remote Wakeup and Self-
Powered Bits)
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x80 IN, Device
Load two bytes into
EP0BUF:
Byte 0: bit 0 =
Self-Powered
Byte 0: bit 1 =
Remote Wakeup
Byte 1: zero
1bRequest 0x00 ‘Get Status’
2 wValueL 0x00
3 wValueH 0x00
4 wIndexL 0x00
5 wIndexH 0x00
6 wLengthL 0x02 Two bytes
requested
7 wLengthH 0x00
Table 2-4. Get Status-Endpoint (Stall Bits)
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x82 IN, Endpoint
Load two bytes into
EP0BUF:
Byte 0: bit 0 =
Stall Bit for EP(n)
Byte 1: zero
1bRequest 0x00 ‘Get Status’
2 wValueL 0x00
3 wValueH 0x00
4 wIndexL EP 0x00-0x08:
OUT0-OUT8
0x80-0x88:
IN0-IN8
5 wIndexH 0x00
6 wLengthL 0x02 Two bytes
requested
7 wLengthH 0x00
42 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Endpoint Zero
shake rather than ACK or NAK. The Get Status-Endpoint
request returns the STALL state for the endpoint indicated in
byte 4 of the request. Note that bit 7 of the endpoint number
EP (byte 4) specifies direction (0 = OUT, 1 = IN).
Endpoint zero is a CONTROL endpoint, which by USB defi-
nition is bidirectional. Therefore, it has only one stall bit.
Get Status/Interface is easy: the firmware returns two zero
bytes through EP0BUF and clears the HSNAK bit (by writing
‘1’ to it). The requested bytes are shown as ‘Reserved (reset
to zero)’ in the USB Specification.
2.3.2 Set Feature
Set Feature is used to enable remote wakeup, stall an end-
point, or put the device into a specific test mode. No data
stage is required.
This Set Feature/Device request sets the remote wakeup
bit. This is the same bit reported back to the host as a result
of a Get Status-Device request (Table 2-3 on page 41). The
host uses this bit to enable or disable remote wakeup by the
device.
This Set Feature/Device request sets the TEST_MODE fea-
ture. This request puts the device into a specific test mode,
and power to the device must be cycled in order to exit test
mode. The EZ-USB SIE handles this request automatically,
but the firmware is responsible for acknowledging the hand-
shake phase.
About STALL
The USB STALL handshake indicates that something
unexpected has happened. For instance, if the host
requests an invalid alternate setting or attempts to send
data to a nonexistent endpoint, the device responds with a
STALL handshake over endpoint zero instead of ACK or
NAK.
Stalls are defined for all endpoint types except ISOCHRO-
NOUS, which does not employ handshakes. Every
EZ-USB bulk endpoint has its own stall bit. The firmware
sets the stall condition for an endpoint by setting the
STALL bit in the endpoint’s EPxCS register. The host tells
the firmware to set or clear the stall condition for an end-
point using the Set Feature/Stall and Clear Feature/Stall
requests.
The device might also set the stall condition on its own. In
a routine that handles endpoint zero device requests, for
example, when a request that is not defined or not sup-
ported is decoded, the firmware should stall EP0.
Once the firmware stalls an endpoint, it should not remove
the stall until the host issues a Clear Feature/Stall request.
An exception to this rule is endpoint 0, which reports a
stall condition only for the current transaction and then
automatically clears the stall condition. This prevents end-
point 0, the default CONTROL endpoint, from locking out
device requests.
Table 2-5. Get Status-Interface
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x81 IN, Endpoint
Load two bytes into
EP0BUF:
Byte 0: zero
Byte 1: zero
1bRequest 0x00 ‘Get Status’
2 wValueL 0x00
3 wValueH 0x00
4 wIndexL 0x00
5 wIndexH 0x00
6 wLengthL 0x02 Two bytes
requested
7 wLengthH 0x00
Table 2-6. Set Feature-Device (Set Remote Wakeup Bit)
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x00 OUT, Device
Set the Remote
Wakeup Bit
1bRequest 0x03 ‘Set Feature’
2 wValueL 0x01 Feature Selector:
Remote Wakeup
3 wValueH 0x00
4 wIndexL 0x00
5 wIndexH 0x00
6 wLengthL 0x00
7 wLengthH 0x00
Table 2-7. Set Feature-Device (Set TEST_MODE Feature)
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x00 OUT, Device
ACK handshake
phase
1bRequest 0x03 ‘Set Feature’
2 wValueL 0x02 Feature Selector:
TEST_MODE
3 wValueH 0x00
4 wIndexL 0x00
5 wIndexH 0xnn nn = specific test
mode
6 wLengthL 0x00
7 wLengthH 0x00
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 43
Endpoint Zero
The only Set Feature/Endpoint request presently defined in
the USB Specification is to stall an endpoint. The firmware
should respond to this request by setting the STALL bit in
the EPxCS register for the indicated endpoint EP (byte 4 of
the request). The firmware can either stall an endpoint on its
own or in response to the device request. Endpoint stalls are
cleared by the host Clear Feature/Stall request.
The firmware should respond to the Set Feature/Stall
request by performing the following tasks:
1. Set the STALL bit in the indicated endpoint’s EPxCS reg-
ister.
2. Reset the data toggle for the indicated endpoint.
3. Restore the stalled endpoint to its default condition,
ready to send or accept data after the stall condition is
removed by the host (via a Clear Feature/Stall request).
For EP1 IN, for example, firmware should clear the
BUSY bit in the EP1CS register; for EP1OUT, firmware
should load any value into the EP1 byte-count register.
4. Clear the HSNAK bit in the EP0CS register (by writing 1
to it) to terminate the Set Feature/Stall CONTROL trans-
fer.
Step 3 is also required whenever the host sends a ‘Set Inter-
face’ request.
2.3.3 Clear Feature
Clear Feature is used to disable remote wakeup or to clear a
stalled endpoint.
If the USB device supports remote wakeup (reported in its
descriptor table when the device enumerates), the Clear
Feature/Remote Wakeup request disables the wakeup
capability.
The Clear Feature/Stall removes the stall condition from an
endpoint. The firmware should respond by clearing the
STALL bit in the indicated endpoint’s EPxCS register.
2.3.4 Get Descriptor
During enumeration, the host queries a USB device to learn
its capabilities and requirements using Get Descriptor
requests. Using tables of descriptors, the device sends back
(over EP0-IN) such information as what device driver to
load, how many endpoints it has, its different configurations,
alternate settings it may use, and informative text strings
about the device.
The EZ-USB provides a special Setup Data Pointer to sim-
plify firmware service for Get_Descriptor requests. The firm-
ware loads this 16-bit pointer with the starting address of the
requested descriptor, clears the HSNAK bit (by writing ‘1’ to
it), and the EZ-USB transfers the entire descriptor.
Table 2-8. Set Feature-Endpoint (Stall)
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x02 OUT, Endpoint
Set the STALL bit
for the indicated
endpoint.
1bRequest 0x03 ‘Set Feature’
2wValueL 0x00 Feature Selector:
STALL
3 wValueH 0x00
4 wIndexL EP 0x00-0x08:
OUT0-OUT8
0x80-0x88:
IN0-IN8
5 wIndexH 0x00
6 wLengthL 0x00
7 wLengthH 0x00
Data Toggles
The EZ-USB automatically maintains the endpoint toggle
bits to ensure data integrity for USB transfers. Firmware
should directly manipulate these bits only for a very limited
set of circumstances:
■Set Feature/Stall
■Set Configuration
■Set Interface
Table 2-9. Clear Feature-Device (Clear Remote Wakeup
Bit)
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x00 OUT, Device
Clear the remote
wakeup bit.
1bRequest 0x01 ‘Clear Feature’
2wValueL 0x01 Feature Selector:
Remote Wakeup
3 wValueH 0x00
4 wIndexL 0x00
5 wIndexH 0x00
6 wLengthL 0x00
7 wLengthH 0x00
Table 2-10. Clear Feature-Endpoint (Clear Stall)
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x02 OUT, Endpoint
Clear the STALL bit
for the indicated
endpoint.
1bRequest 0x01 ‘Clear Feature’
2wValueL 0x00 Feature Selector:
STALL
3 wValueH 0x00
4 wIndexL EP 0x00-0x08:
OUT0-OUT8
0x80-0x88:
IN0-IN8
5 wIndexH 0x00
6 wLengthL 0x00
7 wLengthH 0x00
44 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Endpoint Zero
Figure 2-5. Using Setup Data Pointer (SUDPTR) for Get_Descriptor Requests
Figure 2-5 illustrates use of the Setup Data Pointer. This
pointer is implemented as two registers, SUDPTRH and
SUDPTRL. The base address of SUDPTRH:L must be
word-aligned. Most Get Descriptor requests involve transfer-
ring more data than fits into one packet. In the Figure 2-5
example, the descriptor data consists of 91 bytes.
The CONTROL transaction starts in the usual way, with the
EZ-USB automatically transferring the eight bytes from the
SETUP packet into RAM at SETUPDAT, then asserting the
SUDAV interrupt request. The firmware decodes the Get
Descriptor request, and responds by clearing the HSNAK bit
(by writing ‘1’ to it), and then loading the SUDPTRH:L regis-
ters with the address of the requested descriptor. Loading
the SUDPTRL register causes the EZ-USB to automatically
respond to two IN transfers with 64 bytes and 27 bytes of
data using SUDPTRH:L as a base address, and then to
respond to the STATUS stage with an ACK.
The usual endpoint-zero interrupts SUDAV and EP0IN
remain active during this automated transfer, so firmware
normally disables these interrupts because the transfer
requires no firmware intervention.
Three types of descriptors are defined: Device, Configura-
tion, and String.
2.3.4.1 Get Descriptor-Device
As illustrated in Figure 2-5 on page 44, the firmware loads
the two-byte SUDPTRH:L with the starting address of the
Device Descriptor table. The start address needs to be
I
N
A
D
D
R
E
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D
P
C
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5
Token Packet
D
A
T
A
0
8 bytes
Setup
Data
C
R
C
1
6
Data Packet
A
C
K
H/S Pkt
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E
T
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D
R
E
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D
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C
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C
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Token Packet
D
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Payload
Data
C
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6
Data Packet
A
C
K
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Token Packet
D
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Payload
Data
C
R
C
1
6
Data Packet
A
C
K
H/S Pkt
SETUP Stage
SUDAV Interrupt
DATA Stage
EP0IN
Interrupt EP0IN
Interrupt
STATUS Stage
D
A
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A
1
O
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A
D
D
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E
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P
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5
Token Packet
C
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1
6
H/S Pkt
Data Pkt
A
C
K
H/S Pkt
SUDPTRH/L
64 bytes
27 bytes
8 RAM
bytes
SETUPDAT
Table 2-11. Get Descriptor-Device
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x80 IN, Device
Set SUDPTR H:L to
start of Device
Descriptor table in
RAM.
1bRequest 0x06 ‘Get Descriptor’
2 wValueL 0x00
3 wValueH 0x01 Descriptor Type:
Device
4 wIndexL 0x00
5 wIndexH 0x00
6 wLengthL LenL
7 wLengthH LenH
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 45
Endpoint Zero
word-aligned. When SUDPTRL is loaded, the EZ-USB auto-
matically performs the following operations:
1. Reads the requested number of bytes for the transfer
from bytes 6 and 7 of the SETUP packet (LenL and
LenH in Table 2-11).
2. Reads the requested descriptor’s length field to deter-
mine the actual descriptor length.
3. Sends the smaller of (a) the requested number of bytes
or (b) the actual number of bytes in the descriptor, over
EP0BUF using the Setup Data Pointer as a data table
index. This constitutes the second phase of the three-
phase CONTROL transfer. The EZ-USB packetizes the
data into multiple data transfers as necessary.
4. Automatically checks for errors and re-transmits data
packets if necessary.
5. Responds to the third (handshake) phase of the CON-
TROL transfer to terminate the operation.
The Setup Data Pointer can be used for any Get Descriptor
request (for example, Get Descriptor-String).
It can also be used for vendor-specific requests. If bytes six
and seven of those requests contain the number of bytes in
the transfer (see Step 1, above), the Setup Data Pointer
works automatically, as it does for Get Descriptor requests;
if bytes six and seven do not contain the length of the trans-
fer, the length can be loaded explicitly (see the SDPAUTO
paragraphs of section 8.7 The Setup Data Pointer on
page 95).
It is possible for the firmware to do manual CONTROL trans-
fers by directly loading the EP0BUF buffer with the various
packets and keeping track of which SETUP phase is in
effect. This is a good USB training exercise, but not neces-
sary due to the hardware support built into the EZ-USB for
CONTROL transfers.
For DATA stage transfers of fewer than 64 bytes, moving the
data into the EP0BUF buffer and then loading the
EP0BCH:L registers with the byte count would be equivalent
to loading the Setup Data Pointer. However, this would
waste bandwidth because it requires byte transfers into the
EP0BUF Buffer; using the Setup Data Pointer does not.
2.3.4.2 Get Descriptor-Device Qualifier
The Device Qualifier descriptor is used only by devices
capable of high-speed (480 Mbps) operation; it describes
information about the device that would change if the device
were operating at the other speed (for example, if the device
is currently operating at high speed, the device qualifier
returns information about how it would operate at full speed
and vice-versa).
Device Qualifier descriptors are handled just like Device
descriptors; the firmware loads the appropriate descriptor
address (must be word-aligned) into SUDPTRH:L, then the
EZ-USB does the rest.
2.3.4.3 Get Descriptor-Configuration
Table 2-12. Get Descriptor-Device Qualifier
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x80 IN, Device
Set SUDPTR H:L to
start of the appro-
priate Device Quali-
fier Descriptor table
in RAM.
1bRequest 0x06 ‘Get Descriptor’
2 wValueL 0x00
3wValueH 0x06 Descriptor Type:
Device Qualifier
4 wIndexL 0x00
5 wIndexH 0x00
6 wLengthL LenL
7 wLengthH LenH
Table 2-13. Get Descriptor-Configuration
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x80 IN, Device
Set SUDPTR H:L to
start of Configura-
tion Descriptor table
in RAM
1bRequest 0x06 ‘Get Descriptor’
2wValueL CFG Configuration
Number
3wValueH 0x02 Descriptor Type:
Configuration
4 wIndexL 0x00
5 wIndexH 0x00
6 wLengthL LenL
7 wLengthH LenH
46 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Endpoint Zero
2.3.4.4 Get Descriptor-String
Configuration and String descriptors are handled similarly to
Device descriptors. The firmware reads byte 2 of the SETUP
data to determine which configuration or string is being
requested, then loads the corresponding descriptor address
(must be word-aligned) into SUDPTRH:L. The EZ-USB does
the rest.
2.3.4.5 Get Descriptor-Other Speed
Configuration
The Other Speed Configuration descriptor is used only by
devices capable of high-speed (480 Mbps) operation; it
describes the configurations of the device if it were operat-
ing at the other speed (that is, if the device is currently oper-
ating at high speed, the Other Speed Configuration returns
information about full-speed configuration and vice-versa).
Other Speed Configuration descriptors are handled just like
Configuration descriptors; the firmware loads the appropri-
ate descriptor address (must be word-aligned) into SUDP-
TRH:L, then the EZ-USB does the rest.
2.3.5 Set Descriptor
The firmware handles Set Descriptor requests by clearing
the HSNAK bit (by writing ‘1’ to it), then reading descriptor
data directly from the EP0BUF buffer. The EZ-USB keeps
track of the number of byes transferred from the host into
EP0BUF, and compares this number with the length field in
bytes six and seven. When the proper number of bytes has
been transferred, the EZ-USB automatically responds to the
STATUS phase, which is the third and final stage of the
CONTROL transfer.
Table 2-14. Get Descriptor-String
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x80 IN, Device
Set SUDPTR H:L to
start of String
Descriptor table in
RAM.
1bRequest 0x06 ‘Get Descriptor’
2 wValueL STR String Number
3 wValueH 0x03 Descriptor Type:
String
4 wIndexL 0x00 (Language ID L)
5 wIndexH 0x00 (Language ID H)
6 wLengthL LenL
7 wLengthH LenH
Table 2-15. Get Descriptor-Other Speed Configuration
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x80 IN, Device
Set SUDPTR H:L to
start of Other Speed
Configuration
Descriptor table in
RAM.
1bRequest 0x06 ‘Get Descriptor’
2 wValueL CFG Other Speed
Configuration
Number
3 wValueH 0x07 Descriptor Type:
Other Speed
Configuration
4 wIndexL 0x00 (Language ID L)
5 wIndexH 0x00 (Language ID H)
6 wLengthL LenL
7 wLengthH LenH
Table 2-16. Set Descriptor-Device
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x00 OUT, Device
Read device
descriptor data over
EP0BUF.
1bRequest 0x07 ‘Set Descriptor’
2 wValueL 0x00
3 wValueH 0x01 Descriptor Type:
Device
4 wIndexL 0x00
5 wIndexH 0x00
6 wLengthL LenL
7 wLengthH LenH
Table 2-17. Set Descriptor-Configuration
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x00 OUT, Device
Read configuration
descriptor data over
EP0BUF.
1bRequest 0x07 ‘Set Descriptor’
2 wValueL 0x00
3 wValueH 0x02 Descriptor Type:
Configuration
4 wIndexL 0x00
5 wIndexH 0x00
6 wLengthL LenL
7 wLengthH LenH
Table 2-18. Set Descriptor-String
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x00 IN, Device
Read string descrip-
tor data over
EP0BUF.
1bRequest 0x07 ‘Set Descriptor’
2 wValueL 0x00 String Number
3 wValueH 0x03 Descriptor Type:
String
4 wIndexL 0x00 (Language ID L)
5 wIndexH 0x00 (Language ID H)
6 wLengthL LenL
7 wLengthH LenH
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 47
Endpoint Zero
Note The firmware controls the flow of data in the Data
Stage of a Control Transfer. After the firmware processes
each OUT packet, it writes any value into the endpoint’s byte
count register to re-arm the endpoint.
Configurations, Interfaces, and Alternate Settings
A USB device has one or more configurations. Only one
configuration is active at any time.
A configuration has one or more interfaces, all of which are
concurrently active. Multiple interfaces allow different host-
side device drivers to be associated with different portions of
a USB device.
Each interface has one or more alternate settings. Each
alternate setting has a collection of one or more endpoints.
This structure is a software model; the EZ-USB takes no
action when these settings change. However, the firmware
must re-initialize endpointsand reset the dat toggle
when the host changes configurations or interfaces alter-
nate settings.
As far as the firmware is concerned, a ‘configuration’ is sim-
ply a byte variable that indicates the current setting.
The host issues a ‘Set Configuration’ request to select a
configuration, and a ‘Get Configuration’ request to deter-
mine the current configuration.
2.3.5.1 Set Configuration
When the host issues the ‘Set Configuration’ request, the
firmware saves the configuration number (byte 2, CFG, in
Table 2-19), performs any internal operations necessary to
support the configuration, and finally clears the HSNAK bit
(by writing ‘1’ to it) to terminate the ‘Set Configuration’ CON-
TROL transfer.
Note After setting a configuration, the host issues Set Inter-
face commands to set up the various interfaces contained in
the configuration.
2.3.6 Get Configuration
When the host issues the ‘Get Configuration’ request, the
firmware returns the current configuration number. It loads
the configuration number into EP0BUF, loads a byte count
of one into EP0BCH:L, and finally clears the HSHAK bit (by
writing ‘1’ to it) to terminate the ‘Set Configuration’ CON-
TROL transfer.
2.3.7 Set Interface
This confusingly-named USB command actually sets ‘alter-
nate settings’ for a specified interface.
USB devices can have multiple concurrent interfaces. For
example, a device may have an audio system that supports
Device
Config 2
Low Power
Config 1
High Power
Interface 1
audio
Interface 0
CDROM
control
A
lt Setting
0
A
lt Setting
1
A
lt Setting
3
Interface 2
video
Interface 3
data
storage
Concurrent
One at a time
ep ep ep
One at a time
Table 2-19. Set Configuration
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x00 OUT, Device
Read and store
CFG, change con-
figurations in firm-
ware.
1bRequest 0x09 ‘Set
Configuration’
2wValueL CFG Configuration
Number
3 wValueH 0x00
4 wIndexL 0x00
5 wIndexH 0x00
6 wLengthL 0x00
7 wLengthH 0x00
Table 2-20. Get Configuration
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x80 IN, Device
Send CFG over
EP0 after reconfig-
uring.
1bRequest 0x08 ‘Get
Configuration’
2 wValueL 0x00
3 wValueH 0x00
4 wIndexL 0x00
5 wIndexH 0x00
6 wLengthL 1 LenL
7 wLengthH 0 LenH
48 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Endpoint Zero
different sample rates, and a graphic control panel that sup-
ports different languages. Each interface has a collection of
endpoints. Except for endpoint 0, which each interface uses
for device control, endpoints may not be shared between
interfaces.
Interfaces may report alternate settings in their descriptors.
For example, the audio interface may have settings ‘0’, ‘1’,
and ‘2’ for 8-kHz, 22-kHz, and 44-kHz sample rates, respec-
tively. The panel interface may have settings ‘0’ and ‘1’ for
English and Spanish, respectively. The Set/Get Interface
requests select among the various alternate settings in an
interface.
The firmware should respond to a Set Interface request by
performing the following steps:
1. Perform the internal operation requested (such as
adjusting a sampling rate).
2. Reset the data toggles for every endpoint in the inter-
face.
3. Restore the endpoints to their default conditions, ready
to send or accept data. For EP1 IN, for example, firm-
ware should clear the BUSY bit in the EP1CS register;
for EP1OUT, firmware should load any value into the
EP1 byte-count register.
4. Clear the HSNAK bit (by writing ‘1’ to it) to terminate the
Set Interface CONTROL transfer.
2.3.8 Get Interface
When the host issues the Get Interface request, the firm-
ware simply returns the alternate setting for the requested
interface IF and clears the HSNAK bit (by writing ‘1’ to it).
2.3.9 Set Address
When a USB device is first plugged in, it responds to device
address 0 until the host assigns it a unique address using
the Set Address request. The EZ-USB copies this device
address into the FNADDR (Function Address) register, then
subsequently responds only to requests to this address.
This address is in effect until the USB device is unplugged,
the host issues a USB Reset, or the host powers down.
The FNADDR register is read-only. Whenever the EZ-USB
ReNumerates™ (see Enumeration and ReNumeration™, on
page 51), it automatically resets FNADDR to zero, allowing
the device to come back as new.
An EZ-USB program does not need to know the device
address, because the EZ-USB automatically responds only
to the host-assigned FNADDR value. The device address is
readable only for debug/diagnostic purposes.
Table 2-21. Set Interface (Actually, Set Alternate Setting
#AS for Interface #IF)
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x00 OUT, Device
Read and store byte
2 (AS) for Interface
#IF, change setting
for Interface #IF in
firmware.
1bRequest 0x0B ‘Set Interface’
2 wValueL AS Alternate Setting
Number
3 wValueH 0x00
4wIndexL IF Interface Number
5 wIndexH 0x00
6 wLengthL 0x00
7 wLengthH 0x00
Table 2-22. Get Interface (Actually, Get Alternate Setting
#AS for interface #IF)
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x81 IN, Device
Send AS for Inter-
face #IF over EP0.
1bRequest 0x0A ‘Get Interface’
2 wValueL 0x00
3 wValueH 0x00
4 wIndexL IF Interface Number
5 wIndexH 0x00
6 wLengthL 1 LenL
7 wLengthH 0 LenH
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 49
Endpoint Zero
2.3.10 Sync Frame
The ‘Sync Frame’ request is used to establish a marker in
time so the host and USB device can synchronize multi-
frame transfers over isochronous endpoints.
Suppose an isochronous transmission consists of a repeat-
ing sequence of five 300-byte packets transmitted from host
to device over EP8-OUT. Both host and device maintain
sequence counters that count repeatedly from 1 to 5 to keep
track of the packets inside a transmission. To start up in
sync, both host and device need to reset their counts to ‘0’
at the same time (in the same frame).
To get in sync, the host issues the Sync Frame request with
EP=EP8OUT (0x08). The firmware responds by loading
EP0BUF with a two-byte frame count for some future time;
for example, the current frame plus 20. This marks frame
‘current+20’ as the sync frame, during which both sides ini-
tialize their sequence counters to ‘0.’ The current frame
count is always available in the USBFRAMEL and USB-
FRAMEH registers.
Multiple isochronous endpoints can be synchronized in this
manner; the firmware can keep a separate internal
sequence count for each endpoint.
2.3.11 Firmware Load
The USB endpoint-zero protocol provides a mechanism for
mixing vendor-specific requests with standard device
requests. Bits 6:5 of the bmRequestType field are set to 00
for a standard device request and to 10 for a vendor
request.
The EZ-USB responds to two endpoint-zero vendor
requests, RAM Download and RAM Upload. These requests
are active whether RENUM=0 or RENUM=1, but can only
occur while the 8051 is held in reset. RAM Uploads can only
occur on word boundaries (i.e. the start address must be
evenly divisible by two). The same restriction does not apply
to RAM Downloads.
Because bit 7 of the first byte of the SETUP packet specifies
direction, only one bRequest value (0xA0) is required for the
upload and download requests. These RAM load com-
mands are available to any USB device that uses the EZ-
USB chip.
A host loader program must write 0x01 to the CPUCS regis-
ter to put the EZ-USB’s CPU into RESET, load all or part of
the EZ-USB’s internal RAM with code, then reload the
CPUCS register with zero to take the CPU out of RESET.
Table 2-23. Sync Frame
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x82 IN, Endpoint
Send a frame num-
ber over EP0 to
synchronize end-
point #EP
1bRequest 0x0C ‘Sync Frame’
2 wValueL 0x00
3 wValueH 0x00
4 wIndexL EP Endpoint number
5 wIndexH 0x00
6 wLengthL 2 LenL
7 wLengthH 0 LenH
About USB Frames
In full-speed mode (12 Mbps), the USB host issues an
SOF (Start Of Frame) packet once every millisecond.
Every SOF packet contains an 11-bit (mod-2048) frame
number. The firmware services all isochronous transfers
at SOF time, using a single SOF interrupt request and
vector. If the EZ-USB detects a missing or garbled SOF
packet, it can use an internal counter to generate the SOF
interrupt automatically.
In high-speed mode (480 Mbps), each frame is divided
into eight 125-microsecond microframes. Although the
frame counter still increments only once per frame, the
host issues an SOF every microframe. The host and
device always synchronize on the zero-th microframe of
the frame specified in the device’s response to the Sync
Frame request; there is no mechanism for synchronizing
on any other microframe.
Table 2-24. Firmware Download
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0x40 Vendor Request,
OUT
None required.
1bRequest 0xA0 ‘Firmware Load’
2wValueL Addr
L Starting address
3wValueH Addr
H
4 wIndexL 0x00
5 wIndexH 0x00
6 wLengthL LenL Number of bytes
7 wLengthH LenH
Table 2-25. Firmware Upload
Byte Field Value Meaning Firmware
Response
0 bmRequestType 0xC0 Vendor Request,
IN
None Required.
1bRequest 0xA0 ‘Firmware Load’
2wValueL Addr
L Starting address
3wValueH Addr
H
4 wIndexL 0x00
5 wIndexH 0x00
6 wLengthL LenL Number of Bytes
7 wLengthH LenH
50 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Endpoint Zero
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 51
3. Enumeration and
ReNumeration™
3.1 Introduction
The EZ-USB’s configuration is ‘soft’: Code and data are stored in internal RAM, which can be loaded from the host over the
USB interface. EZ-USB-based USB peripherals can operate without ROM, EPROM, or FLASH memory, shortening produc-
tion lead times and making firmware updates extremely simple.
To support this soft configuration, the EZ-USB is capable of enumerating as a USB device without firmware. This
automatically-enumerated USB device (the Default USB Device) contains a set of interfaces and endpoints and can accept
firmware downloaded from the host. However, at a minimum, an I2C™ boot EEPROM is required for production (see 3.2 EZ-
USB Startup Modes for more details).
Note For the FX2LP, two separate Default USB Devices actually exist, one for enumeration as a full-speed (12 Mbps) device,
and the other for enumeration as a high-speed (480 Mbps) device. The FX2LP automatically performs the speed-detect pro-
tocol and chooses the proper Default USB Device. The two sets of Default USB Device descriptors are shown in Appendices
A and B.
Once the Default USB Device enumerates and the host downloads firmware and descriptor tables to the EZ-USB, it then
begins executing the downloaded code, which electrically simulates a physical disconnect/connect from the USB and causes
the EZ-USB to enumerate again as a second device, this time taking on the USB personality defined by the downloaded code
and descriptors. This patented secondary enumeration process is called ‘ReNumeration™’.
An EZ-USB register bit called RENUM controls whether device requests over endpoint zero are handled by firmware or auto-
matically b y the Default USB Device. When RENUM = 0, the Default USB Device handles the requests automatically; when
RENUM = 1, they must be handled by firmware.
3.2 EZ-USB Startup Modes
When the EZ-USB comes out of reset, it can act in various ways to establish itself as a USB device. EZ-USB power-on
behavior depends on several factors:
1. If no off chip memory (either on the I2C bus or on the address/data bus) is connected to the EZ-USB, it enumerates as the
Default USB Device, with descriptors and VID/PID/DID supplied by hardwired internal logic (Table 3-3 on page 52).
RENUM is set to ‘0’, indicating that the Default USB Device automatically handles device requests. This startup mode is
not allowed for production devices, since it uses the Cypress VID, and is detailed here for completeness only.
2. If an EEPROM containing custom VID/PID/DID values is attached to the EZ-USB’s I2C bus, EZ-USB also enumerates as
the Default USB Device as above, but it substitutes the VID/PID/DID values from the EEPROM for its internal values. The
EEPROM must contain the value 0xC0 in its first byte to indicate this mode to EZ-USB, so this mode is called a ‘C0 Load’.
As above, RENUM is automatically set to ‘0’, indicating that the Default USB Device automatically handles device
requests. A 16 byte EEPROM is sufficiently large for a C0 Load. A C0 Load is often used to automate downloading firm-
ware via USB.
3. If an EEPROM containing EZ-USB firmware is attached to the I2C bus, the firmware is automatically loaded from the
EEPROM into the EZ-USB’s on chip RAM, and then the CPU is taken out of reset to execute this boot-loaded code. In this
case, the VID/PID/DID values are encapsulated in the firmware; the RENUM bit is automatically set to ‘1’ to indicate that
the firmware, not the Default USB Device, handles device requests. The EEPROM must contain the value 0xC2 in its first
byte to indicate this mode to EZ-USB, so this mode is called a ‘C2 Load’. Note Although the EZ-USB can perform C2
Loads from EEPROMs as large as 64 KB, code can only be downloaded to the 16K of on chip RAM. Using bootloader
firmware allows download to external RAM.
52 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Enumeration and ReNumeration™
4. If a Flash, EPROM, or other memory is attached to the
EZ-USB’s address/data bus (128-pin package only) and
a properly formatted EEPROM meeting the require-
ments above is not present, and the EA pin is tied high
(indicating that the EZ-USB starts code execution at
0x0000 from off-chip memory), the EZ-USB begins exe-
cuting firmware from the off chip memory. In this case,
the VID/PID/DID values are encapsulated in the firm-
ware; the RENUM bit is automatically set to ‘1’ to indi-
cate that the firmware, not internal EZ-USB logic,
handles device requests.
Case (2) is the most frequently used mode when soft opera-
tion is desired, since the VID/PID values from EEPROM
always bind the device to the appropriate host driver while
allowing EZ-USB firmware to be easily updated. In this case,
the host first holds the CPU in reset, uses the EZ-USB
Default USB Device to download firmware, then the host
takes the CPU out of reset so that it can execute the down-
loaded code. Section 3.8 EZ-USB Vendor Request for Firm-
ware Load on page 56 describes the USB ‘Vendor Request’
that the EZ-USB supports for code download and upload.
Note The Default USB Device is fully characterized in
Appendices A and B, which list the built-in EZ-USB descrip-
tor tables for full-speed and high-speed enumeration,
respectively. Studying these Appendices in conjunction with
Table 3-1 and Table 3-2 is an excellent way to learn the
structure of USB descriptors.
3.3 The Default USB Device
The Default USB Device consists of a single USB configura-
tion containing one interface (interface 0) and alternate set-
tings 0, 1, 2 and 3. The endpoints and MaxPacketSizes
reported for this device are shown in Table 3-1 (full speed)
and Table 3-2 (high speed). Note that alternate setting zero
consumes no interrupt or isochronous bandwidth, as recom-
mended by the USB Specification.
Note Although the physical size of the EP1 endpoint buffer
is 64 bytes, it is reported as a 512 byte buffer for high speed
alternate setting 1. This maintains compatibility with the USB
specification, which allows only 512 byte bulk endpoints. If
you use this default alternate setting, do not send/receive
EP1 packets larger than 64 bytes.
3.4 EEPROM Boot-load Data
Formats
This section describes three EEPROM boot-load scenarios
and the EEPROM data formats that support them. The three
scenarios are:
■No EEPROM, or EEPROM with invalid boot data
■‘C0’ EEPROM (load custom VID / PID / DID only)
■‘C2’ EEPROM (load firmware to on-chip RAM)
3.4.1 No EEPROM or Invalid EEPROM
In the simplest scenario, either no serial EEPROM is pres-
ent on the ICbus or an EEPROM is present, but its first byte
is neither 0xC0 nor 0xC2. In this case, descriptor data is
supplied by hardwired internal EZ-USB tables. The EZ-USB
enumerates as the Default USB Device, with the ID bytes
shown in Table 3-3 or Table 3-4.
Note Pull up resistors are required on the SCL/SDA pins
even if no device is connected. The resistors are required to
allow EZ-USB logic to detect the ‘No EEPROM / Invalid
EEPROM’ condition.
Table 3-1. Default Full Speed Alternate Settings
Alternate
Setting 0 1 2 3
ep0 64 64 64 64
ep1out 064 bulk 64 int 64 int
ep1in 064 bulk 64 int 64 int
ep2 064 bulk out (2x) 64 int out (2x) 64 iso out (2x)
ep4 064 bulk out (2x) 64 bulk out (2x) 64 bulk out (2x)
ep6 064 bulk in (2x) 64 int in (2x) 64 iso in (2x)
ep8 064 bulk in (2x) 64 bulk in (2x) 64 bulk in (2x)
Note: ‘0’ means ‘not implemented’, ‘2x’ means double buffered.
Table 3-2. Default High Speed Alternate Settings
Alternate
Setting 0 1 2 3
ep0 64 64 64 64
ep1out 0512 bulk 64 int 64 int
ep1in 0512 bulk 64 int 64 int
ep2 0512 bulk out (2x) 512 int out (2x) 512 iso out (2x)
ep4 0512 bulk out (2x) 512 bulk out (2x) 512 bulk out (2x)
ep6 0512 bulk in (2x) 512 int in (2x) 512 iso in (2x)
ep8 0512 bulk in (2x) 512 bulk in (2x) 512 bulk in (2x)
Note: ‘0’ means ‘not implemented’, ‘2x’ means double buffered.
Table 3-3. Default ID Values for EZ-USB FX2LP, No
EEPROM / Invalid EEPROM
Vendor ID 0x04B4 (Cypress Semiconductor)
Product ID 0x8613 (EZ-USB FX2LP)
Device Release 0xAnnn (depends on chip revision,
nnn = chip revision, where first silicon = 001)
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Enumeration and ReNumeration™
The USB host queries the EZ-USB Default USB Device dur-
ing enumeration, reads its device descriptor, and uses the
IDs in Table 3-3 or Table 3-4 to determine which software
driver to load into the operating system. This is a major USB
feature — drivers are dynamically matched with devices and
automatically loaded when a device is plugged in.
The ‘No EEPROM / Invalid EEPROM’ scenario is the sim-
plest configuration, and also the most limiting. This configu-
ration must only be used for code development, using
Cypress software tools matched to the ID values in
Table 3-3 or Table 3-4.
Note No USB peripheral based on the EZ-USB FX2LP or
EZ-USB FX1 may use this configuration.
3.4.2 Serial EEPROM Present, First
Byte is 0xC0
If, at power-on reset, the EZ-USB detects an EEPROM con-
nected to its I2C bus with the value 0xC0 at address 0, the
EZ-USB automatically copies the Vendor ID (VID), Product
ID (PID), and Device ID (DID) from the EEPROM (Table 3-5)
into internal storage. The EZ-USB then supplies these
EEPROM bytes to the host as part of its response to the
host’s Get Descriptor-Device request (these six bytes
replace only the VID / PID / DID bytes in the Default USB
Device descriptor). This causes a host driver matched to the
VID / PID / DID values in the EEPROM to be loaded by the
host OS.
After initial enumeration, that host driver holds the CPU in
reset, downloads the firmware and USB descriptor data into
the EZ-USB’s RAM, then releases the CPU reset. The EZ-
USB then ReNumerates™ as a custom device. At that point,
the host may load a new driver, bound to the VID / PID / DID
contained in the firmware.
The eighth EEPROM byte contains configuration bits that
control the following:
■I2C bus speed. Note Default is 100 kHz.
■Disconnect state. Note Default is for EZ-USB to come
out of reset connected to USB.
Note Section EEPROM Configuration Byte, on page 55 con-
tains a full description of the configuration bits.
3.4.3 Serial EEPROM Present, First
Byte is 0xC2
If, at power-on reset, the EZ-USB detects an EEPROM con-
nected to its I2C with the value 0xC2 at address zero, the
EZ-USB loads the EEPROM data into on-chip RAM. It also
sets the RENUM bit to ‘1’, causing device requests to be
handled by the firmware instead of the Default USB Device.
The ‘C2 Load’ EEPROM data format is shown in Table 3-6.
The first byte indicates a ‘C2 Load’, which instructs the EZ-
USB to copy the EEPROM data into on-chip RAM. The EZ-
USB reads the next six bytes (VID / PID / DID) even though
they are not used by most C2 Load applications. The eighth
byte (byte 7) is the configuration byte described in the previ-
ous section.
Table 3-4. Default ID Values for EZ-USB FX1, No EEPROM
/ Invalid EEPROM
Vendor ID 0x04B4 (Cypress Semiconductor)
Product ID 0x6473 (EZ-USB FX1)
Device Release 0xAnnn (depends on chip revision,
nnn = chip revision, where first silicon = 001)
Table 3-5. ‘C0 Load’ Format
EEPROM Address Contents
00xC0
1Vendor ID (VID) L
2Vendor ID (VID) H
3Product ID (PID) L
4Product ID (PID) H
5Device ID (DID) L
6Device ID (DID) H
7Configuration byte
Table 3-6. ‘C2 Load’ Format
EEPROM Address Contents
00xC2
1Vendor ID (VID) L
2Vendor ID (VID) H
3Product ID (PID) L
4Product ID (PID) H
5Device ID (DID) L
6Device ID (DID) H
7Configuration byte
8 Length H
9Length L
10 Start Address H
11 Start Address L
--- Data Block
---
--- Length H
--- Length L
--- Start Address H
--- Start Address L
--- Data Block
---
--- 0x80
--- 0x01
--- 0xE6
--- 0x00
last 00000000
54 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Enumeration and ReNumeration™
Note Bytes 1-6 of a C2 EEPROM can be loaded with VID /
PID / DID bytes if it is desired at some point to run the firm-
ware with RENUM = 0 (i.e., EZ-USB logic handles device
requests), using the EEPROM VID / PID / DID rather than
the development-only VID / PID / DID values shown in
Table 3-3 on page 52 or Table 3-4 on page 53.
One or more data records follow, starting at EEPROM
address 8. Each data record consists of a 10-bit Length field
(0-1023) which indicates the number of bytes in the follow-
ing data block, a 14-bit Start Address (0-0x3FFF) for the
data block, and the data block itself.
The last data record, which must always consist of a single-
byte load of 0x00 to the CPUCS register at 0xE600, is
marked with a ‘1’ in the most-significant bit of the Length
field. Only the least-significant bit (8051RES) of this byte is
writable by the download; that bit is set to zero to bring the
CPU out of reset.
Note Serial EEPROM data can be loaded only into these
three on-chip RAM spaces:
■Program/Data RAM at 0x0000-0x3FFF
■Data RAM at 0xE000-0xE1FF
■The CPUCS register at 0xE600 (only bit 0, 8051RES, is
EEPROM loadable)
3.4.3.1 General Purpose Use of the I2CBus
The EZ-USB’s I2C controller serves two purposes. First, as
described in this chapter, it manages the serial EEPROM
interface that operates automatically at power-on to deter-
mine the enumeration method. Second, once the CPU is up
and running, firmware can access the I2C controller for gen-
eral-purpose use. This makes a wide range of standard I2C
peripherals available to an EZ-USB-based system.
Other I2C devices can be attached to the SCL and SDA
lines as long as there is no address conflict with the serial
EEPROM described in this chapter. The Input/
Output chapter on page 181 describes the general-purpose
nature of the I2C interface.
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Enumeration and ReNumeration™
3.5 EEPROM Configuration Byte
The configuration byte is valid for both EEPROM load formats (C0 and C2) and has the following format:
Figure 3-1. EEPROM Configuration Byte
7The config byte of the .iic file must be changed so that the FX2 will start at full speed. The uVision
project file contains the following iic generation line:
c:\cypress\usb\bin\hex2bix -c 0x80 -i -f 0xC2 -o bulkloop.iic bulkloop.hex
This line sets bit 7 of the config byte with the “-c 0x80”. Setting bit 7 prevents the FX2 from entering
high-speed mode on startup.
6 DISCON (USB Disconnect) A USB hub or host detects attachment of a full speed device by sensing a high level on the D+ wire.
A USB device provides this high level using a 1500-ohm resistor between D+ and 3.3V (the D+ line is
normally low, pulled down by a 15 K resistor in the hub or host). The 1500 resistor is internal to
the EZ-USB.
The EZ-USB accomplishes ReNumeration by selectively driving or floating the 3.3V supply to its
internal 1500 resistor. When the supply is floated, the host no longer ‘sees’ the EZ-USB; it appears
to have been disconnected from the USB. When the supply is then driven, the EZ-USB appears to
have been newly connected to the USB. From the host’s point of view, the EZ-USB can be discon-
nected and reconnected to the USB, without ever physically disconnecting.
The ‘connect state’ of EZ-USB is controlled by a register bit called DISCON (USBCS.3), which
defaults to 0, or ‘connected’. This default may be overridden by setting the DISCON bit in the
EEPROM configuration byte to 1, which allows the EZ-USB to come up ‘disconnected’. The EZ-USB
core sees that this DISCON bit is set, and sets the USBCS.3 bit before the CPU is taken out of reset.
The DISCON bit in the EEPROM configuration byte cannot be used to instruct the EZ-USB to con-
nect to the USB bus. Once the CPU is running, firmware can modify this bit.
0 400KHZ (I2C bus speed) 0 100 kHz
1 400 kHz
If 400KHZ = 0, the I2C bus operates at approximately 100 kHz. If 400KHZ = 1, the I2C bus operates
at approximately 400 kHz. This bit is copied to I2CTL.0, whose default value is ‘0’, or 100 kHz. Once
the CPU is running, firmware can modify this bit.
Configuration
b7 b6 b5 b4 b3 b2 b1 b0
0DISCON 00000400KHZ
Bit Name Description
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Enumeration and ReNumeration™
3.6 The RENUM Bit
An EZ-USB control bit called ‘RENUM’ (ReNumerated)
determines whether USB device requests over endpoint
zero are handled by the Default USB Device or by EZ-USB
firmware. At power-on reset, the RENUM bit (USBCS.1) is
zero, indicating that the Default USB Device automatically
handles USB device requests. Once firmware has been
downloaded to the EZ-USB and the CPU is running, it can
set RENUM = 1 so that subsequent device requests are
handled by the downloaded firmware and descriptor tables.
The Endpoint Zero chapter on page 37 describes how the
firmware handles device requests while RENUM = 1.
If a 128-pin EZ-USB is using off-chip code memory at
0x0000, the EA pin is high, and there is no boot EEPROM to
supply a custom Vendor ID and Product ID, the EZ-USB
automatically sets the RENUM bit to ‘1’ so that device
requests are always handled by the firmware and descriptor
tables in the off-chip memory. The EZ-USB also sets
RENUM = 1 after a ‘C2 load’ if the EA pin is low. In this case,
firmware execution begins in on-chip RAM using the code
loaded from the EEPROM, with the firmware handling all
USB requests.
3.7 EZ-USB Response to Device
Requests (RENUM = 0)
Table 3-7 shows how the Default USB Device responds to
endpoint zero device requests when RENUM=0.
A USB host enumerates by issuing Set Address, Get
Descriptor, and Set Configuration (to ‘1’) requests (the Set
Address and Get Descriptor requests are used only during
enumeration). After enumeration, the Default USB Device
responds to the following device requests from the host:
■Set or clear an endpoint stall (Set/Clear Feature-End-
point)
■Read the stall status for an endpoint (Get_Status-End-
point)
■Set/Read an 8-bit configuration number (Set/Get Config-
uration)
■Set/Read a 2-bit interface alternate setting (Set/Get
Interface)
■Download or upload EZ-USB on-chip RAM
3.8 EZ-USB Vendor Request for
Firmware Load
Prior to ReNumeration, the host downloads data into the EZ-
USB’s internal RAM. The host can access two on-chip EZ-
USB RAM spaces — Program / Data RAM at 0x0000-
0x3FFF and Data RAM at 0xE000-0xE1FF — which it can
download or upload only when the CPU is held in reset.
The host must write to the CPUCS register to put the CPU in
or out of reset. These two RAM spaces may also be boot-
loaded by a ‘C2’ EEPROM connected to the I2C bus.
Note Off-chip RAM (on the 128-pin EZ-USB’s address/data
bus) cannot be uploaded or downloaded by the host using
the ‘Firmware Load’ vendor request.
The USB Specification provides for ‘vendor-specific
requests’ to be sent over endpoint zero. The EZ-USB uses
Another Use for the Default USB Device
The Default USB Device is established at power on to set
up a USB device capable of downloading firmware into
the EZ-USB’s RAM. Another useful feature of the Default
USB Device is that EZ-USB code can be written to sup-
port the already-configured generic USB device. Before
bringing the CPU out of reset, the EZ-USB automatically
enables certain endpoints and reports them to the host via
descriptors. By using the Default USB Device (for exam-
ple, by keeping RENUM = 0), the firmware can, with very
little code, perform meaningful USB transfers that use
these preconfigured endpoints. This accelerates the USB
learning curve.
Table 3-7. How the Default USB Device Handles EP0
Requests When RENUM=0
bRequest Name EZ-USB Response
0x00 Get Status-Device Returns two zero bytes
0x00 Get Status-Endpoint Supplies EP Stall bit for indicated
EP
0x00 Get Status-Interface Returns two zero bytes
0x01 Clear Feature-Device None
0x01 Clear Feature-Endpoint Clears Stall bit for indicated EP
0x02 (reserved) None
0x03 Set Feature Device Sets TEST_MODE feature
0x03 Set Feature Endpoint Sets Stall bit for indicated EP
0x04 (reserved) None
0x05 Set Address Updates FNADDR register
0x06 Get Descriptor Supplies internal table
0x07 Set Descriptor None
0x08 Get Configuration Returns internal value
0x09 Set Configuration Sets internal value
0x0A Get Interface Returns internal value (0-3)
0x0B Set Interface Sets internal value (0-3)
0x0C Sync Frame None
Vendor Requests
0xA0 Firmware Load Upload/Download on-chip RAM
0xA1-0xAF Reserved Reserved by Cypress Semiconduc-
tor
all other None
Table 3-7. How the Default USB Device Handles EP0
Requests When RENUM=0
bRequest Name EZ-USB Response
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Enumeration and ReNumeration™
this feature to transfer data between the host and EZ-USB
RAM. The EZ-USB automatically responds to two ‘Firmware
Load’ requests, as shown in Table 3-8 and Table 3-9.
Note These upload and download requests are always
handled by the EZ-USB, regardless of the state of the
RENUM bit. The upload start address must be word-aligned
(that is, the start address must be evenly divisible by two).
The bRequest value 0xA0 is reserved for this purpose. It
should never be used for another vendor request. Cypress
Semiconductor also reserves bRequest values 0xA1
through 0xAF; devices should not use these bRequest val-
ues.
A host loader program must write 0x01 to the CPUCS regis-
ter to put the CPU into RESET, load all or part of the EZ-
USB RAM with firmware, then reload the CPUCS register
with ‘0’ to take the CPU out of RESET. The CPUCS register
(at 0xE600) is the only EZ-USB register that can be written
using the Firmware Download command.
3.9 How the Firmware ReNumerates
Two control bits in the USBCS (USB Control and Status) register control the ReNumeration process: DISCON and RENUM.
Figure 3-2. USB Control and Status Register
To simulate a USB disconnect, the firmware sets DISCON to ‘1’. To reconnect, the firmware clears DISCON to ‘0’.
Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device
handles device requests over endpoint zero: if RENUM = 0, the Default USB Device handles device requests; if RENUM = 1,
the firmware does.
Table 3-8. Firmware Download
Byte Field Value Meaning EZ-USB
Response
0bmRequest 0x40 Vendor Request, OUT
None
required
1bRequest 0xA0 ‘Firmware Load’
2wValueL AddrL Starting Address
3wValueH AddrH
4wIndexL 0x00
5wIndexH 0x00
6wLenghtL LenL Number of Bytes
7wLengthH LenH
Table 3-9. Firmware Upload
Byte Field Value Meaning EZ-USB
Response
0bmRequest 0xC0 Vendor Request, IN
None required
1bRequest 0xA0 ‘Firmware Load’
2wValueL AddrL Starting Address (must
be word-aligned)
3wValueH AddrH
4wIndexL 0x00
5wIndexH 0x00
6wLengthL LenL Number of Bytes
7wLengthH LenH
USBCS USB Control and Status E680
b7 b6 b5 b4 b3 b2 b1 b0
HSM 0 0 0 DISCON NOSYNSOF RENUM SIGRSUME
R/W R R R R/W R/W R/W R/W
00000100
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Enumeration and ReNumeration™
3.10 Multiple ReNumerations™
EZ-USB firmware can ReNumerate anytime. One use for this capability might be to ‘fine tune’ an isochronous endpoint’s
bandwidth requests by trying various descriptor values and ReNumerating.
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 59
4. Interrupts
4.1 Introduction
The EZ-USB’s interrupt architecture is an enhanced and expanded version of the standard 8051’s. The EZ-USB responds to
the interrupts shown in Table 4-1; interrupt sources that are not present in the standard 8051 are shown in bold type.
The Natural Priority column in Table 4-1 shows the EZ-USB interrupt priorities. The EZ-USB can assign each interrupt to a
high or low priority group; priorities are resolved within the groups using the natural priorities.
4.2 SFRs
The following SFRs are associated with interrupt control:
■IE - SFR 0xA8 (Table 4-2 on page 60)
■IP - SFR 0xB8 (Table 4-3 on page 60)
■EXIF - SFR 0x91 (Table 4-4 on page 60)
■EICON - SFR 0xD8 (Table 4-5 on page 60)
■EIE - SFR 0xE8 (Table 4-6 on page 60)
■EIP - SFR 0xF8 (Table 4-7 on page 61)
The IE and IP SFRs provide interrupt enable and priority control for the standard interrupt unit, as with the standard 8051.
Additionally, these SFRs provide control bits for the Serial Port 1 interrupt.
The EXIF, EICON, EIE and EIP registers provide flags, enable control, and priority control.
Table 4-1. EZ-USB Interrupts
EZ-USB Interrupt Source Interrupt Vector Natural Priority
IE0 INT0# Pin 0x0003 1
TF0 Timer 0 Overflow 0x000B 2
IE1 INT1# Pin 0x0013 3
TF1 Timer 1 Overflow 0x001B 4
RI_0 & TI_0 USART0 Rx & Tx 0x0023 5
TF2 Timer 2 Overflow 0x002B 6
Resume WAKEUP / WU2 Pin or USB Resume 0x0033 0
RI_1 & TI_1 USART1 Rx & Tx 0x003B 7
USBINT USB 0x0043 8
I2CINT I2C Bus 0x004B 9
IE4 GPIF / FIFOs / INT4 Pin 0x0053 10
IE5 INT5# Pin 0x005B 11
IE6 INT6 Pin 0x0063 12
60 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Interrupts
Table 4-2. IE Register — SFR 0xA8
Bit Function
IE.7 EA - Global interrupt enable. Controls masking of all
interrupts except USB wakeup (resume). EA = 0 disables
all interrupts except USB wakeup. When EA = 1, inter-
rupts are enabled or masked by their individual enable
bits.
IE.6 ES1 - Enable Serial Port 1 interrupt. ES1 = 0 disables
Serial Port 1 interrupts (TI_1 and RI_1). ES1 = 1 enables
interrupts generated by the TI_1 or RI_1 flag.
IE.5 ET2 - Enable Timer 2 interrupt. ET2 = 0 disables Timer 2
interrupt (TF2). ET2=1 enables interrupts generated by
the TF2 or EXF2 flag.
IE.4 ES0 - Enable Serial Port 0 interrupt. ES0 = 0 disables
Serial Port 0 interrupts (TI_0 and RI_0). ES0=1 enables
interrupts generated by the TI_0 or RI_0 flag.
IE.3 ET1 - Enable Timer 1 interrupt. ET1 = 0 disables Timer 1
interrupt (TF1). ET1=1 enables interrupts generated by
the TF1 flag.
IE.2 EX1 - Enable external interrupt 1. EX1 = 0 disables exter-
nal interrupt 1 (IE1). EX1=1 enables interrupts generated
by the INT1# pin.
IE.1 ET0 - Enable Timer 0 interrupt. ET0 = 0 disables Timer 0
interrupt (TF0). ET0=1 enables interrupts generated by
the TF0 flag.
IE.0 EX0 - Enable external interrupt 0. EX0 = 0 disables exter-
nal interrupt 0 (IE0). EX0=1 enables interrupts generated
by the INT0# pin.
Table 4-3. IP Register — SFR 0xB8
Bit Function
IP.7 Reserved. Read as ‘1’.
IP.6 PS1 - Serial Port 1 interrupt priority control. PS1 = 0 sets
Serial Port 1 interrupt (TI_1 or RI_1) to low priority. PS1 = 1
sets Serial port 1 interrupt to high priority.
IP.5 PT2 - Timer 2 interrupt priority control. PT2 = 0 sets Timer
2 interrupt (TF2) to low priority. PT2 = 1 sets Timer 2 inter-
rupt to high priority.
IP.4 PS0 - Serial Port 0 interrupt priority control. PS0 = 0 sets
Serial Port 0 interrupt (TI_0 or RI_0) to low priority. PS0 = 1
sets Serial Port 0 interrupt to high priority.
IP.3 PT1 - Timer 1 interrupt priority control. PT1 = 0 sets Timer
1 interrupt (TF1) to low priority. PT1 = 1 sets Timer 1 inter-
rupt to high priority.
IP.2 PX1 - External interrupt 1 priority control. PX1 = 0 sets
external interrupt 1 (IE1) to low priority. PT1 = 1 sets exter-
nal interrupt 1 to high priority.
IP.1 PT0 - Timer 0 interrupt priority control. PT0 = 0 sets Timer
0 interrupt (TF0) to low priority. PT0 = 1 sets Timer 0 inter-
rupt to high priority.
IP.0 PX0 - External interrupt 0 priority control. PX0 = 0 sets
external interrupt 0 (IE0) to low priority. PX0 = 1 sets exter-
nal interrupt 0 to high priority.
Table 4-4. EXIF Register — SFR 0x91
Bit Function
EXIF.7 IE5 - External Interrupt 5 flag. IE5 = 1 indicates a falling
edge was detected at the INT5# pin. IE5 must be cleared
by software. Setting IE5 in software generates an inter-
rupt, if enabled.
EXIF.6 IE4 - GPIF/FIFO/External Interrupt 4 flag. The ‘INT4’ inter-
rupt is internally connected to the FIFO/GPIF interrupt by
default; it can optionally function as External Interrupt 4 on
the 100- and 128-pin EZ-USB. When configured as Exter-
nal Interrupt 4, IE4 indicates that a rising edge was
detected at the INT4 pin. IE4 must be cleared by software.
Setting IE4 in software generates an interrupt, if enabled.
EXIF.5 I2CINT - I2C Bus Interrupt flag. I2CINT = 1 indicates an
I2C Bus interrupt. I2CINT must be cleared by software.
Setting I2CINT in software generates an interrupt, if
enabled.
EXIF.4 USBINT - USB Interrupt flag. USBINT = 1 indicates an
USB interrupt. USBINT must be cleared by software. Set-
ting USBINT in software generates an interrupt, if enabled.
EXIF.3 Reserved. Read as ‘1’.
EXIF.2-0 Reserved. Read as ‘0’.
Table 4-5. EICON Register — SFR 0xD8
Bit Function
EICON.7 SMOD1 - Serial Port 1 baud rate doubler enable. When
SMOD1 = 1, the baud rate for Serial Port 1 is doubled.
EICON.6 Reserved. Read as ‘1’.
EICON.5 ERESI - Enable Resume interrupt. ERESI = 0 disables
the Resume interrupt. ERESI = 1 enables interrupts
generated by the resume event.
EICON.4 RESI - Wakeup interrupt flag. RESI = 1 indicates a false-
to-true transition was detected at the WAKEUP or WU2
pin, or that USB activity has resumed from the sus-
pended state. RESI must be cleared by software before
exiting the interrupt service routine, otherwise the inter-
rupt is immediately be reasserted. Setting RESI = 1 in
software generates a wakeup interrupt, if enabled.
EICON.3 INT6 - External interrupt 6. When INT6 = 1, the INT6 pin
has detected a low to high transition. INT6 must be
cleared by software. Setting this bit in software gener-
ates an IE6 interrupt, if enabled.
EICON.2-0 Reserved. Read as ‘0’.
Table 4-6. EIE Register — SFR 0xE8
Bit Function
EIE.7-5 Reserved. Read as ‘1’.
EIE.4 EX6 - Enable external interrupt 6. EX6 = 0 disables external
interrupt 6 (IE6). EX6 = 1 enables interrupts generated by the
INT6 pin.
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 61
Interrupts
4.2.1 803x/805x Compatibility
The implementation of interrupts is similar to that of the Dallas Semiconductor DS80C320. Table 4-8 summarizes the differ-
ences in interrupt implementation between the Intel 8051, the Dallas Semiconductor DS80C320, and the EZ-USB.
EIE.3 EX5 - Enable external interrupt 5. EX5 = 0 disables external
interrupt 5 (IE5). EX5 = 1 enables interrupts generated by the
INT5# pin.
EIE.2 EX4 - Enable external interrupt 4. EX4 = 0 disables external
interrupt 4 (IE4). EX4 = 1 enables interrupts generated by the
INT4 pin or by the FIFO/GPIF Interrupt.
EIE.1 EI2C - Enable I2C bus interrupt (I2CINT). EI2C = 0 disables
the I2C Bus interrupt. EI2C = 1 enables interrupts generated
by the I2C bus controller.
EIE.0 EUSB - Enable USB interrupt (USBINT). EUSB = 0 disables
USB interrupts. EUSB = 1 enables interrupts generated by the
USB Interface.
Table 4-6. EIE Register — SFR 0xE8
Bit Function
Table 4-7. EIP Register — SFR 0xF8
Bit Function
EIP.7-5 Reserved. Read as ‘1’.
EIP.4 PX6 - External interrupt 6 priority control. PX6 = 0 sets external
interrupt 6 (IE6) to low priority. PX6 = 1 sets external interrupt 6
to high priority.
EIP.3 PX5 - External interrupt 5 priority control. PX5 = 0 sets external
interrupt 5 (IE5) to low priority. PX5=1 sets external interrupt 5
to high priority.
EIP.2 PX4 - External interrupt 4 priority control. PX4 = 0 sets external
interrupt 4
(INT4 / GPIF / FIFO) to low priority. PX4=1 sets external inter-
rupt 4 to high priority.
EIP.1 PI2C - I2CINT priority control. PI2C = 0 sets I2C Bus interrupt
to low priority. PI2C=1 sets I2C Bus interrupt to high priority.
EIP.0 PUSB - USBINT priority control. PUSB = 0 sets USB interrupt to
low priority. PUSB=1 sets USB interrupt to high priority.
Table 4-8. Summary of Interrupt Compatibility
Feature Intel
8051
Dallas
DS80C320
Cypress
EZ-USB
Power Fail Interrupt Not implemented Internally generated Replaced with RESUME Interrupt
External Interrupt 0 Implemented Implemented Implemented
Timer 0 Interrupt Implemented Implemented Implemented
External Interrupt 1 Implemented Implemented Implemented
Timer 1 Interrupt Implemented Implemented Implemented
Serial Port 0 Interrupt Implemented Implemented Implemented
Timer 2 Interrupt Not implemented Implemented Implemented
Serial Port 1 Interrupt Not implemented Implemented Implemented
External Interrupt 2 Not implemented Implemented Replaced with autovectored USB Interrupt
External Interrupt 3 Not implemented Implemented Replaced with I2C Bus Interrupt
External Interrupt 4 Not implemented Implemented Replaced by autovectored FIFO/GPIF Interrupt. Can be configured as
External Interrupt 4 on 100- and 128-pin EZ-USB only.
External Interrupt 5 Not implemented Implemented Implemented
Watchdog Timer Interrupt Not implemented Internally generated Replaced with External Interrupt 6
Real-time Clock Interrupt Not implemented Implemented Not implemented
62 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Interrupts
4.3 Interrupt Processing
When an enabled interrupt occurs, the EZ-USB completes the instruction it is currently executing, then vectors to the address
of the interrupt service routine (ISR) associated with that interrupt (see Table 4-9 on page 62). The EZ-USB executes the ISR
to completion unless another interrupt of higher priority occurs. Each ISR ends with a RETI (return from interrupt) instruction.
After executing the RETI, the EZ-USB continues executing firmware at the instruction following the one which was executing
when the interrupt occurred.
Note The EZ-USB always completes the instruction in progress before servicing an interrupt. If the instruction in progress is
RETI, or a write access to any of the IP, IE, EIP, or EIE SFRs, the EZ-USB completes one additional instruction before servic-
ing the interrupt.
4.3.1 Interrupt Masking
The EA Bit in the IE SFR (IE.7) is a global enable for all
interrupts except the RESUME (USB wakeup) interrupt,
which is always enabled. When EA = 1, each interrupt is
enabled or masked by its individual enable bit. When EA =
0, all interrupts are masked except the USB wakeup inter-
rupt.
Table 4-9 provides a summary of interrupt sources, flags,
enables, and priorities.
4.3.1.1 Interrupt Priorities
There are two stages of interrupt priority: assigned interrupt
level and natural priority. Assigned priority is set by EZ-USB
firmware; natural priority is as shown in Table 4-9, and is
fixed.
Note The assigned interrupt level (highest, high, or low)
takes precedence over natural priority.
The RESUME (USB wakeup) interrupt always has highest
assigned priority and is the only interrupt that can have high-
est assigned priority. All other interrupts can be assigned
either high or low priority.
In addition to an assigned priority level (high or low), each
interrupt also has a natural priority, as listed in Table 4-9.
‘Simultaneous’ interrupts with the same assigned priority
level (for example, both high) are resolved according to their
natural priority. For example, if INT0 and INT1 are both
assigned high priority and both occur simultaneously, INT0
takes precedence due to its higher natural priority.
Once an interrupt is being serviced, only an interrupt of
higher ‘assigned’ priority level can interrupt the service rou-
tine. That is, an ISR for a low-assigned-level interrupt can
only be interrupted by a high-assigned-level interrupt. An
ISR for a high-assigned-level interrupt can only be inter-
rupted by the RESUME interrupt.
4.3.2 Interrupt Sampling
The internal timers and serial ports generate interrupts by
setting the interrupt flag bits shown in Table 4-9. These inter-
rupts are sampled once per instruction cycle (that is, once
every 4 CLKOUT cycles).
Table 4-9. Interrupt Flags, Enables, Priority Control, and Vectors
Interrupt Description Interrupt Request
Flag Interrupt
Enable Assigned Priority
Control Natural
Priority Interrupt
Vector
RESUME Resume interrupt EICON.4 EICON.5 Always Highest 0 (highest) 0x0033
IE0 External interrupt 0 TCON.1 IE.0 IP.0 1 0x0003
TF0 Timer 0 interrupt TCON.5 IE.1 IP.1 2 0x000B
IE1 External interrupt 1 TCON.3 IE.2 IP.2 3 0x0013
TF1 Timer 1 interrupt TCON.7 IE.3 IP.3 4 0x001B
TI_0 or RI_0 Serial port 0 transmit or receive
interrupt SCON0.1 (TI.0)
SCON0.0 (RI_0)
IE.4 IP.4 5 0x0023
TF2 or EXF2 Timer 2 interrupt T2CON.7 (TF2)
T2CON.6 (EXF2)
IE.5 IP.5 6 0x002B
TI_1 or RI_1 Serial port 1 transmit or receive
interrupt SCON1.1 (TI_1)
SCON1.0 (RI_1)
IE.6 IP.6 7 0x003B
USBINT Autovectored USB interrupt EXIF.4 EIE.0 EIP.0 8 0x0043
I2CINT I2C Bus interrupt EXIF.5 EIE.1 EIP.1 9 0x004B
IE4 Autovectored FIFO / GPIF or
External interrupt 4 EXIF.6 EIE.2 EIP.2 10 0x0053
IE5 External interrupt 5 EXIF.7 EIE.3 EIP.3 11 0x005B
IE6 External interrupt 6 EICON.3 EIE.4 EIP.4 12 0x0063
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 63
Interrupts
INT0# and INT1# are both active low and can be pro-
grammed to be either edge-sensitive or level-sensitive,
through the IT0 and IT1 bits in the TCON SFR. When ITx =
0, INTx# is level-sensitive and the EZ-USB sets the IEx flag
when the INTx# pin is sampled low. When ITx = 1, INTx# is
edge-sensitive and the EZ-USB sets the IEx flag when the
INTx# pin is sampled high then low on consecutive samples.
The remaining five interrupts (INT 4-6, USB and I2C Bus
interrupts) are edge-sensitive only. INT6 and INT4 are active
high and INT5# is active low.
To ensure that edge-sensitive interrupts are detected, the
interrupt pins should be held in each state for a minimum of
one instruction cycle (4 CLKOUT cycles). Level-sensitive
interrupts are not latched; their pins must remain asserted
until the interrupt is serviced.
4.3.3 Interrupt Latency
Interrupt response time depends on the current state of the
EZ-USB. The fastest response time is five instruction cycles:
one to detect the interrupt, and four to perform the LCALL to
the ISR.
The maximum latency is 13 instruction cycles. This 13-cycle
latency occurs when the EZ-USB is currently executing a
RETI instruction followed by a MUL or DIV instruction. The
13 instruction cycles in this case are: one to detect the inter-
rupt, three to complete the RETI, five to execute the DIV or
MUL, and four to execute the LCALL to the ISR.
This 13-instruction-cycle latency excludes autovector
latency for the USB and FIFO/GPIF interrupts (see sections
4.5 USB-Interrupt Autovectors on page 67 and 4.8 FIFO/
GPIF Interrupt Autovectors on page 69), and any instruc-
tions required to perform housekeeping, as shown in
Figure 4-2 on page 65. Autovectoring adds a fixed four-
instruction cycle, so the maximum latency for an autovec-
tored USB or FIFO/GPIF interrupt is 13 + 4 = 17 instruction
cycles.
4.4 USB-Specific Interrupts
The EZ-USB provides 28 USB-specific interrupts. One,
‘Resume’, has its own dedicated interrupt; the other 27
share the ‘USB’ interrupt.
4.4.1 Resume Interrupt
After the EZ-USB has entered its idle state, it responds to an
external signal on its WAKEUP/WU2 pins or resumption of
USB bus activity by restarting its oscillator and resuming
firmware execution.
The Power Management chapter on page 77 describes sus-
pend/resume signaling in detail, and presents an example
which uses the Wakeup Interrupt.
4.4.2 USB Interrupts
Table 4-10 shows the 27 USB requests that share the USB
Interrupt. Those marked with an asterisk are not imple-
mented in FX1. Figure 4-1 on page 64 shows the USB Inter-
rupt logic; the bottom IRQ, EP8ISOERR, is expanded in the
diagram to show the logic which is associated with each
USB interrupt request.
Table 4-10. Individual USB Interrupt Sources
Priority
INT2VEC
Value Source Notes
1 00 SUDAV SETUP Data Available
2 04 SOF Start of Frame (or microframe)
3 08 SUTOK Setup Token Received
4 0C SUSPEND USB Suspend request
5 10 USB RESET Bus reset
6 14 HISPEED Entered high-speed operation*
718EP0ACK
EZ-USB ACK’d the CONTROL Hand-
shake
8 1C reserved
9 20 EP0-IN EP0-IN ready to be loaded with data
10 24 EP0-OUT EP0-OUT has USB data
11 28 EP1-IN EP1-IN ready to be loaded with data
12 2C EP1-OUT EP1-OUT has USB data
13 30 EP2 IN: buffer available. OUT: buffer has
data
14 34 EP4 IN: buffer available. OUT: buffer has
data
15 38 EP6 IN: buffer available. OUT: buffer has
data
16 3C EP8 IN: buffer available. OUT: buffer has
data
17 40 IBN IN-Bulk-NAK (any IN endpoint)
18 44 reserved
19 48 EP0PING EP0 OUT was Pinged and it NAK’d*
20 4C EP1PING EP1 OUT was Pinged and it NAK’d*
21 50 EP2PING EP2 OUT was Pinged and it NAK’d*
22 54 EP4PING EP4 OUT was Pinged and it NAK’d*
23 58 EP6PING EP6 OUT was Pinged and it NAK’d*
24 5C EP8PING EP8 OUT was Pinged and it NAK’d*
25 60 ERRLIMIT Bus errors exceeded the programmed
limit
26 64 reserved
27 68 reserved
28 6C reserved
29 70 EP2ISOERR ISO EP2 OUT PID sequence error
30 74 EP4ISOERR ISO EP4 OUT PID sequence error
31 78 EP6ISOERR ISO EP6 OUT PID sequence error
32 7C EP8ISOERR ISO EP8 OUT PID sequence error
64 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Interrupts
Figure 4-1. USB Interrupts
Referring to the logic inside the dotted lines of Figure 4-1,
each USB interrupt source has an interrupt request latch.
IRQ bits are set automatically by the EZ-USB; firmware
clears an IRQ bit by writing a ‘1’ to it. The output of each
latch is ANDed with an Interrupt Enable Bit and then ORed
with all the other USB Interrupt request sources.
The EZ-USB prioritizes the USB interrupts and constructs
an Autovector, which appears in the INT2VEC register. The
interrupt vector values IV[4:0] are shown to the left of the
interrupt sources (shaded boxes in Figure 4-1); zero is the
highest priority, 31 is the lowest. If two USB interrupts occur
simultaneously, the prioritization affects which one is first
indicated in the INT2VEC register.
If Autovectoring is enabled, the INT2VEC byte replaces the
contents of address 0x0045 in the EZ-USB’s program mem-
ory. This causes the EZ-USB to automatically vector to a dif-
ferent address for each USB interrupt source. This
mechanism is explained in detail in section 4.5 USB-Inter-
rupt Autovectors on page 67.
Due to the OR gate in Figure 4-1, assertion of any of the
individual USB interrupt sources sets the EZ-USB’s ‘main’
USB Interrupt request bit (EXIF.4). This main USB interrupt
is enabled by setting EIE.0 to ‘1’.
To clear the main USB interrupt request, firmware clears the
EXIF.4 bit to ‘0’.
After servicing a USB interrupt, EZ-USB firmware clears the
individual USB source’s IRQ bit by setting it to ‘1’. If any
other USB interrupts are pending, the act of clearing the IRQ
bit causes the EZ-USB to generate another pulse for the
highest-priority pending interrupt. If more than one is pend-
ing, each is serviced in the priority order shown in
Figure 4-1, starting with SUDAV (priority 00) as the highest
priority, and ending with EP8ISOERR (priority 31) as the
lowest.
USB Interrupt
SUTOK
SUDAV
SOF
EIE.0
EXIF.4(rd)
EXIF.4(0)
S
R
"USB"
Interrupt
USBERRIE.7
USBERRIRQ.7 (1)
S
R
USBERRIRQ.7 (rd)
EP4ISOERR
EP6ISOERR
EP8ISOERR
0
IV4
IV3
IV2
IV1 IV0 0 0
INT2VEC
00
01
02
29
30
31
Interrupt Request Latch
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 65
Interrupts
Note The main USB interrupt request is cleared by clearing
the EXIF.4 bit to ‘0’; each individual USB interrupt is cleared
by setting its IRQ bit to ‘1’.
Note It is important in any USB Interrupt Service Routine
(ISR) to clear the main USB Interrupt before clearing the
individual USB interrupt request latch. This is because as
soon as the individual USB interrupt is cleared, any pending
USB interrupt immediately tries to generate another main
USB Interrupt. If the main USB IRQ bit has not been previ-
ously cleared, the pending interrupt is lost.
Figure 4-2 illustrates a typical USB ISR.
Figure 4-2. The Order of Clearing Interrupt Requests is Important
The registers associated with the individual USB interrupt sources are described in the Registers chapter on page 211 and
section 8.6 CPU Control of EZ-USB Endpoints on page 89. Each interrupt source has an enable (IE) and a request (IRQ) bit.
Firmware sets the IE bit to ‘1’ to enable the interrupt. The EZ-USB sets an IRQ bit to ‘1’ to request an interrupt, and the firm-
ware clears an IRQ bit by writing a ‘1’ to it.
USB_ISR: push dps
push dpl
push dph
push dpl1
push dph1
push acc
;
mov a,EXIF ; FIRST clear the USB (INT2) interrupt request
clr acc.4
mov EXIF,a ; Note: EXIF reg is not bit-addressable
;
mov dptr,#USBERRIRQ ; now clear the USB interrupt request
mov a,#10000000b ; use EP8ISOERR as example
movx @dptr,a
;
; (service the interrupt here)
;
pop acc
pop dph1
pop dpl1
pop dph
pop dpl
pop dps
;
reti
66 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Interrupts
4.4.2.1 SUTOK, SUDAV Interrupts
Figure 4-3. SUTOK and SUDAV Interrupts
SUTOK and SUDAV are supplied to the EZ-USB by CON-
TROL endpoint zero. The first portion of a USB CONTROL
transfer is the SETUP stage shown in Figure 4-3 (a full
CONTROL transfer is shown in Figure 2-1 on page 38).
When the EZ-USB decodes a SETUP packet, it asserts the
SUTOK (SETUP Token) Interrupt Request. After the EZ-
USB has received the eight bytes error-free and copied
them into the eight internal registers at SETUPDAT, it
asserts the SUDAV Interrupt Request.
Firmware responds to the SUDAV Interrupt by reading the
eight SETUP data bytes in order to decode the USB
request. See chapter “Endpoint Zero” on page 37.
The SUTOK Interrupt is provided to give advance warning
that the eight register bytes at SETUPDAT are about to be
overwritten. It is useful for debug and diagnostic purposes.
4.4.2.2 SOF Interrupt
Figure 4-4. A Start Of Frame (SOF) Packet
A USB Start-of-Frame Interrupt Request is asserted when
the host sends a Start of Frame (SOF) packet. SOFs occur
once per millisecond in full-speed (12 Mbits/sec) mode, and
once every 125 microseconds in high-speed (480 Mbits/sec)
mode.
When the EZ-USB receives an SOF packet, it copies the
eleven-bit frame number (FRNO in Figure 4-4) into the USB-
FRAMEH:L registers and asserts the SOF Interrupt
Request. Isochronous endpoint data may be serviced via
the SOF Interrupt.
4.4.2.3 Suspend Interrupt
If the EZ-USB detects a ‘suspend’ condition from the host, it
asserts the SUSP (Suspend) Interrupt Request. A full
description of Suspend-Resume signaling appears in the
Power Management chapter on page 77.
4.4.2.4 USB RESET Interrupt
The USB host signals a bus reset by driving both D+ and D-
low for at least 10 ms. When the EZ-USB detects the onset
of USB bus reset, it asserts the URES Interrupt Request.
4.4.2.5 HISPEED Interrupt (FX2LP only)
This interrupt is asserted when the host grants high-speed
(480 Mbps) access to the FX2LP.
4.4.2.6 EP0ACK Interrupt
This interrupt is asserted when the EZ-USB has acknowl-
edged the STATUS stage of a CONTROL transfer on end-
point 0.
4.4.2.7 Endpoint Interrupts
These interrupts are asserted when an endpoint requires
service.
For an OUT endpoint, the interrupt request signifies that
OUT data has been sent from the host, validated by the EZ-
USB, and is in the endpoint buffer memory.
For an IN endpoint, the interrupt request signifies that the
data previously loaded by the EZ-USB into the IN endpoint
buffer has been read and validated by the host, making the
IN endpoint buffer ready to accept new data.
4.4.2.8 In-Bulk-NAK (IBN) Interrupt
When the host sends an IN token to any IN endpoint which
does not have data to send, the EZ-USB automatically
NAKs the IN token and asserts this interrupt.
4.4.2.9 EPxPING Interrupt (FX2LP only)
These interrupts are active only during high-speed (480
Mbits/sec) operation.
D
A
T
A
0
8 bytes
Setup
Data
C
R
C
1
6
Data Packet
A
C
K
H/S Pkt
S
E
T
U
P
A
D
D
R
E
N
D
P
C
R
C
5
Token Packet
SETUP Stage
SUTOK
Interrupt SUDAV
Interrupt
S
O
F
F
R
N
O
C
R
C
5
Token Pkt
Table 4-11. Endpoint Interrupts
Interrupt
Name Description
EP0-IN EP0-IN ready to be loaded with data (BUSY bit 1-to-0)
EP0-OUT EP0-OUT has received USB data (BUSY bit 1-to-0)
EP1-IN EP1-IN ready to be loaded with data (BUSY bit 1-to-0)
EP1-OUT EP1-OUT has received USB data (BUSY bit 1-to-0)
EP2 IN: Buffer available (Empty Flag 1-to-0)
OUT: Buffer has received USB data (Empty Flag 0-to-1)
EP4 IN: Buffer available (Empty Flag 1-to-0)
OUT: Buffer has received USB data (Empty Flag 0-to-1)
EP6 IN: Buffer available (Empty Flag 1-to-0)
OUT: Buffer has received USB data (Empty Flag 0-to-1)
EP8 IN: Buffer available (Empty Flag 1-to-0)
OUT: Buffer has received USB data (Empty Flag 0-to-1)
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 67
Interrupts
High-speed USB implements a PING-NAK mechanism for
OUT transfers. When the host wishes to send OUT data to
an endpoint, it first sends a PING token to see if the end-
point is ready (for example, if it has an empty buffer). If a
buffer is not available, the FX2LP returns a NAK handshake.
PING-NAK transactions continue to occur until an OUT buf-
fer is available, at which time the FX2LP answers a PING
with an ACK handshake and the host sends the OUT data to
the endpoint.
The EPxPING interrupt is asserted when the host PINGs an
endpoint and the FX2LP responds with a NAK because no
endpoint buffer memory is available.
4.4.2.10 ERRLIMIT Interrupt
This interrupt is asserted when the USB error-limit counter
has exceeded the preset error limit threshold. See section
8.6.3.3 USBERRIE, USBERRIRQ, ERRCNTLIM,
CLRERRCNT on page 94 for full details.
4.4.2.11 EPxISOERR Interrupt
These interrupts are asserted when an ISO data PID is
missing or arrives out of sequence, or when an ISO packet
is dropped because no buffer space is available (to receive
an OUT packet).
4.5 USB-Interrupt Autovectors
The main USB interrupt is shared by 27 interrupt sources.
To save the code and processing time which normally would
be required to identify the individual USB interrupt source,
the EZ-USB provides a second level of interrupt vectoring,
called ‘Autovectoring.’ When a USB interrupt is asserted,
the EZ-USB pushes the program counter onto its stack then
jumps to address 0x0043, where it expects to find a ‘jump’
instruction to the USB Interrupt service routine.
The EZ-USB jump instruction is encoded as follows:
If Autovectoring is enabled (AV2EN=1 in the INTSETUP reg-
ister), the EZ-USB substitutes its INT2VEC byte (see
Table 4-10 on page 63) for the byte at address 0x0045.
Therefore, if the high byte (‘page’) of a jump-table address is
preloaded at location 0x0044, the automatically-inserted
INT2VEC byte at 0x0045 directs the jump to the correct
address out of the 27 addresses within the page.
As shown in Table 4-13, the jump table contains a series of
jump instructions, one for each individual USB Interrupt
source’s ISR.
Table 4-12. EZ-USB Jump Instruction
Address Op-Code Hex Value
0x0043 LJMP 0x02
0x0044 AddrH 0xHH
0x0045 AddrL 0xLL
Table 4-13. A Typical USB-Interrupt Jump Table
Table Offset Instruction
0x00 LJMP SUDAV_ISR
0x04 LJMP SOF_ISR
0x08 LJMP SUTOK_ISR
0x0C LJMP SUSPEND_ISR
0x10 LJMP USBRESET_ISR
0x14 LJMP HISPEED_ISR
0x18 LJMP EP0ACK_ISR
0x1C LJMP SPARE_ISR
0x20 LJMP EP0IN _ISR
0x24 LJMP EP0OUT_ISR
0x28 LJMP EP1IN _ISR
0x2C LJMP EP1OUT_ISR
0x30 LJMP EP2_ISR
0x34 LJMP EP4_ISR
0x38 LJMP EP6_ISR
0x3C LJMP EP8_ISR
0x40 LJMP IBN_ISR
0x44 LJMP SPARE_ISR
0x48 LJMP EP0PING_ISR
0x4C LJMP EP1PING_ISR
0x50 LJMP EP2PING_ISR
0x54 LJMP EP4PING_ISR
0x58 LJMP EP6PING_ISR
0x5C LJMP EP8PING_ISR
0x60 LJMP ERRLIMIT_ISR
0x64 LJMP SPARE_ISR
0x68 LJMP SPARE_ISR
0x6C LJMP SPARE_ISR
0x70 LJMP EP2ISOERR_ISR
0x74 LJMP EP2ISOERR_ISR
0x78 LJMP EP2ISOERR_ISR
0x7C LJMP EP2ISOERR_ISR
68 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Interrupts
Figure 4-5. The USB Autovector Mechanism in Action
4.5.1 USB Autovector Coding
To employ autovectoring for the USB interrupt:
1. Insert a jump instruction at 0x0043 to a table of jump
instructions to the various USB interrupt service rou-
tines. Make sure the jump table starts on a 0x0100-byte
page boundary.
2. Code the jump table with jump instructions to each indi-
vidual USB interrupt service routine. This table has two
important requirements, arising from the format of the
INT2VEC Byte (zero-based, with the two LSBs set to
‘0’):
a. It must begin on a page boundary (address 0xnn00)
b. The jump instructions must be four bytes apart.
3. The interrupt service routines can be placed anywhere in
memory.
4. Write initialization code to enable the USB interrupt
(INT2) and Autovectoring.
Figure 4-5 illustrates an ISR that services endpoint 2. When
endpoint 2 requires service, the EZ-USB asserts the USB
interrupt request, vectoring to location 0x0043.
The jump instruction at this location, which was originally
coded as ‘LJMP 0400’, becomes ‘LJMP 042C’ because the
EZ-USB automatically inserts 2C, the INT2VEC value for
EP2 (Table 4-13 on page 67).
The EZ-USB jumps to 0x042C, where it executes the jump
instruction to the EP2 ISR, arbitrarily located for this exam-
ple at address 0x0119.
Once the EZ-USB vectors to 0x0043, initiation of the end-
point-specific ISR takes only eight instruction cycles.
4.6 I²C Bus Interrupt
Figure 4-6. I²C Bus Interrupt Enable Bits and Registers
EP2_ISR:
USB_Jmp_Table:
LJMP
04
2C
0x0043
0x0044
0x0045
2C
INT2VEC
Automatically
copied by EZ-USB LJMP EP2_ISR
01
19
0x042C
0x042D
0x042E
0x0400
0x0119
USB Interrupt
Vector
EIE.1
EXIF.5(rd)
EXIF.5(0)
S
R
I2C Bus
Interrupt
I2C Bus
Interrupt Request
DONE S
R
RD or WR
I2DAT register
I2CS
0xE678
I2DAT
0xE679
START STOP LASTRD ID1 ID0 BERR ACK
D7 D6 D5 D4 D3 D2 D1 D0
DONE
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 69
Interrupts
The Input/Output chapter on page 181 describes the inter-
face to the EZ-USB’s I2C Bus controller. The EZ-USB uses
two registers, I2CS (Control and Status) and I2DAT (Data),
to transfer data over the bus.
An I2C Bus Interrupt is asserted whenever one of the follow-
ing occurs:
■The DONE bit (I2CS.0) makes a zero-to-one transition,
signaling that the bus controller is ready for another
command
■The STOP bit (I2CS.6) makes a one-to-zero transition
To enable the ‘Done’ interrupt source, set EIE.1 to ‘1’; to
additionally enable the ‘Stop’ interrupt source, set STOPIE
to ‘1’. If both interrupts are enabled, the interrupt source may
be determined by checking the DONE and STOP bits in the
I2CS register.
To reset the Interrupt Request, write a zero to EXIF.5. Any
firmware read or write to the I2DAT or I2CS register also
automatically clears the Interrupt Request.
Note Firmware must make sure the STOP bit is zero before
writing to I2CS or I2DAT.
4.7 FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual
USB-interrupt sources, the FIFO/GPIF interrupt is shared
among 14 individual FIFO/GPIF sources.
The FIFO/GPIF Interrupt, like the USB Interrupt, can employ
autovectoring. Table 4-14 shows the priority and INT4VEC
values for the 14 FIFO/GPIF interrupt sources.
When FIFO/GPIF interrupt sources are asserted, the EZ-
USB prioritizes them and constructs an Autovector, which
appears in the INT4VEC register; ‘0’ is the highest priority,
‘14’ is the lowest. If two FIFO/GPIF interrupts occur simulta-
neously, the prioritization affects which one is first indicated
in the INT4VEC register. If Autovectoring is enabled, the
INT4VEC byte replaces the contents of address 0x0055 in
the EZ-USB’s program memory. This causes the EZ-USB to
automatically vector to a different address for each FIFO/
GPIF interrupt source. This mechanism is explained in detail
in section 4.8 FIFO/GPIF Interrupt Autovectors.
Note It is important in any FIFO/GPIF Interrupt Service
Routine (ISR) to clear the main INT4 Interrupt before clear-
ing the individual FIFO/GPIF interrupt request latch. This is
because as soon as the individual FIFO/GPIF interrupt is
cleared, any pending individual FIFO/GPIF interrupt immedi-
ately tries to generate another main INT4 Interrupt. If the
main INT4 IRQ bit has not been previously cleared, the
pending interrupt is lost.
The registers associated with the individual FIFO/GPIF
interrupt sources are described in the Registers chapter on
page 211 and in section 8.6 CPU Control of EZ-USB
Endpoints on page 89. Each interrupt source has an enable
(IE) and a request (IRQ) bit. Firmware sets the IE bit to ‘1’ to
enable the interrupt. The EZ-USB sets an IRQ bit to ‘1’ to
request an interrupt, and the firmware clears an IRQ bit by
setting it to ‘1’.
Note The main FIFO/GPIF interrupt request is cleared by
clearing the EXIF.6 bit to ‘0’; each individual FIFO/GPIF
interrupt is cleared by setting its IRQ bit to ‘1’.
4.8 FIFO/GPIF Interrupt
Autovectors
The main FIFO/GPIF interrupt is shared by 14 interrupt
sources. To save the code and processing time which nor-
mally is required to sort out the individual FIFO/GPIF inter-
rupt source, the EZ-USB provides a second level of interrupt
vectoring, called Autovectoring. When a FIFO/GPIF inter-
rupt is asserted, the EZ-USB pushes the program counter
onto its stack then jumps to address 0x0053, where it
expects to find a ‘jump’ instruction to the FIFO/GPIF Inter-
rupt service routine.
The EZ-USB jump instruction is encoded as follows:
If Autovectoring is enabled (AV4EN=1 in the INTSETUP reg-
ister), the EZ-USB substitutes its INT4VEC byte (see
Table 4-14 on page 69) for the byte at address 0x0055.
Table 4-14. Individual FIFO/GPIF Interrupt Sources
Priorit
y
INT4VEC
Value Source Notes
1 80 EP2PF Endpoint 2 Programmable Flag
2 84 EP4PF Endpoint 4 Programmable Flag
3 88 EP6PF Endpoint 6 Programmable Flag
4 8C EP8PF Endpoint 8 Programmable Flag
5 90 EP2EF Endpoint 2 Empty Flag
6 94 EP4EF Endpoint 4 Empty Flag
7 98 EP6EF Endpoint 6 Empty Flag
8 9C EP8EF Endpoint 8 Empty Flag
9 A0 EP2FF Endpoint 2 Full Flag
10 A4 EP4FF Endpoint 4 Full Flag
11 A8 EP6FF Endpoint 6 Full Flag
12 AC EP8FF Endpoint 8 Full Flag
13 B0 GPIFDONE
GPIF Operation Complete
(See General Programmable Interface,
on page 121)
14 B4 GPIFWF
GPIF Waveform
(See General Programmable Interface,
on page 121)
Table 4-15. EZ-USB JUMP Instruction
Address Op-Code Hex Value
0x0053 LJMP 0x02
0x0054 AddrH 0xHH
0x0055 AddrL 0xLL
70 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Interrupts
Therefore, if the high byte (‘page’) of a jump-table address is
preloaded at location 0x0054, the automatically-inserted
INT4VEC byte at 0x0055 directs the jump to the correct
address out of the 14 addresses within the page.
As shown in Table 4-16, the jump table contains a series of
jump instructions, one for each individual FIFO/GPIF Inter-
rupt source’s ISR.
4.8.1 FIFO/GPIF Autovector Coding
To employ autovectoring for the FIFO/GPIF interrupt, per-
form the following steps:
1. Insert a jump instruction at 0x0053 to a table of jump
instructions to the various FIFO/GPIF interrupt service
routines. Make sure the jump table starts at a 0x0100-
byte page boundary plus 0x80.
2. Code the jump table with jump instructions to each indi-
vidual FIFO/GPIF interrupt service routine. This table
has two important requirements, arising from the format
of the INT4VEC byte (0x80-based, with the 2 LSBs set to
0); the two requirements are the following:
a. It must begin on a page boundary + 0x80 (address
0xnn80).
b. The jump instructions must be four bytes apart.
3. Place the interrupt service routines anywhere in memory.
4. Write initialization code to enable the FIFO/GPIF inter-
rupt (INT4) and Autovectoring.
Figure 4-7 illustrates an ISR that services EP4’s Full Flag.
When EP4 goes full, the EZ-USB asserts the FIFO/GPIF
interrupt request, vectoring to location 0x0053.
The jump instruction at this location, which was originally
coded as ‘LJMP 0480’, becomes ‘LJMP 04A4’ because the
EZ-USB automatically inserts A4, the INT4VEC value for
EP4FF (Table 4-13 on page 67).
The EZ-USB jumps to 0x04A4, where it executes the jump
instruction to the EP4FF ISR, arbitrarily located for this
example at address 0x0321.
Once the EZ-USB vectors to 0x0053, initiation of the end-
point-specific ISR takes only eight instruction cycles.
Figure 4-7. The FIFO/GPIF Autovector Mechanism in Action
Table 4-16. A Typical FIFO/GPIF-Interrupt Jump Table
Table Offset Instruction
0x80 LJMP EP2PF_ISR
0x84 LJMP EP4PF_ISR
0x88 LJMP EP6PF_ISR
0x8C LJMP EP8PF_ISR
0x90 LJMP EP2EF_ISR
0x94 LJMP EP4EF_ISR
0x98 LJMP EP6EF_ISR
0x9C LJMP EP8EF_ISR
0xA0 LJMP EP2FF_ISR
0xA4 LJMP EP4FF_ISR
0xA8 LJMP EP6FF_ISR
0xAC LJMP EP8FF_ISR
0xB0 LJMP GPIFDONE_ISR
0xB4 LJMP GPIFWF_ISR
EP4FF_ISR
FIFO_GPIF_Jmp_Table:
LJMP
04
A4
0x0053
0x0054
0x0055
A4
INT4VEC
Automatically
copied by EZ-USB LJMP EP4FF_ISR
01
19
0x04A4
0x04A5
0x04A6
0x0480
0x0321
FIFO/GPIF
Interrupt
Vector
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 71
5. Memory
5.1 Introduction
Memory organization in the EZ-USB is similar, but not identical, to that of the standard 8051. There are three distinct memory
areas: Internal Data Memory, External Data Memory, and External Program Memory. As is explained below, ‘External’ mem-
ory is not necessarily external to the EZ-USB chip.
5.2 Internal Data RAM
As shown in Figure 5-1, the EZ-USB’s Internal Data RAM is divided into three distinct regions: the ‘Lower 128’, the ‘Upper
128’, and ‘SFR Space’. The Lower 128 and Upper 128 are general purpose RAM; the SFR Space contains EZ-USB control
and status registers.
Figure 5-1. Internal Data RAM Organization
0x00
0xFF
0x7F
0x80
Lower 128
Upper 128 SFR Space
0xFF
0x80
Lower 128
0x00 R0-R7 (Bank 0)
0x07
0x08 R0-R7 (Bank 1)
0x0F
0x10 R0-R7 (Bank 2)
R0-R7 (Bank 3)
0x17
0x18
0x1F
0x20
0x2F
0x30
0x7F
00
07
78
7F . . . .
. . . .
Bit-Addressable
RAM
General-
Purpose
Direct or indirect addressing
Indirect addressing only
Direct addressing
only
00
01
10
11
Register
Bank Select
(PSW.4:3)
72 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Memory
5.2.1 The Lower 128
The Lower 128 occupies Internal Data RAM locations 0x00-
0x7F. All of the Lower 128 may be accessed as general-pur-
pose RAM, using either direct or indirect addressing (for
more information on the EZ-USB addressing modes. See
chapter “Instruction Set” on page 175).
Two segments of the Lower 128 may be accessed in other
ways.
■Locations 0x00-0x1F comprise four banks of 8 registers
each, numbered R0 through R7. The current bank is
selected via the ‘register-select’ bits (RS1:RS0) in the
PSW special-function register; code which references
registers R0-R7 accesses them only in the currently-
selected bank.
■Locations 0x20-0x2F are bit addressable. Each of the
128 bits in this segment may be individually addressed,
either by its bit address (0x00 to 0x7F) or by reference to
the byte which contains it (0x20.0 to 0x2F.7).
5.2.2 The Upper 128
The Upper 128 occupies Internal Data RAM locations 0x80-
0xFF; all 128 bytes may be accessed as general-purpose
RAM, but only by using indirect addressing (for more infor-
mation on the EZ-USB addressing modes. See chapter
“Instruction Set” on page 175).
Since the EZ-USB’s stack is internally accessed using indi-
rect addressing, it is a good idea to put the stack in the
Upper 128; this frees the more-efficiently-accessed Lower
128 for general purpose use.
5.2.3 Special Function Register Space
The Special Function Register (SFR) space, like the Upper
128, is accessed at Internal Data RAM locations 0x80-0xFF.
The EZ-USB keeps SFR space separate from the Upper
128 by using different addressing modes to access the two
regions: SFRs may only be accessed using ‘direct’ address-
ing, and the Upper 128 may only be accessed using ‘indi-
rect’ addressing.
The SFR space contains EZ-USB control and status regis-
ters; an overview is in section 11.12 Special Function
Registers on page 174, and a full description of all the SFRs
is in the Registers chapter on page 211.
The sixteen SFRs at locations 0x80, 0x88, …, 0xF0, 0xF8
are bit-addressable. Each of the 128 bits in these registers
may be individually addressed, either by its bit address
(0x80 to 0xFF) or by reference to the byte which contains it
(for example, 0x80.0, 0xC8.7, etc.).
5.3 External Program Memory
and External Data Memory
The standard 8051 employs a Harvard architecture for its
External memory; the program and data memories are phys-
ically separate. The EZ-USB uses a modified version of this
memory model; ‘off-chip’ program and data memories are
separate, but the ‘on-chip’ program and data memories are
unified in a Von Neumann architecture. This allows the EZ-
USB’s on-chip RAM to be loaded from an external source
(USB or EEPROM, see Enumeration and ReNumeration™,
on page 51), then used as program memory.
Standard 8051
The standard 8051 has separate address spaces for pro-
gram and data memory; it can address 64 KB of read-only
program memory at addresses 0x0000-0xFFFF, and
another 64 KB of read/write data memory, also at addresses
0x0000-0xFFFF. The standard 8051 keeps the two memory
spaces separate by using different bus signals to access
them; the read strobe for program memory is PSEN# (Pro-
gram Store Enable), and the read and write strobes for data
memory are RD# and WR#. The 8051 generates PSEN#
strobes for instruction fetches and for the MOVC (move
code memory into the accumulator) instruction; it generates
RD# and WR# strobes for all data-memory accesses. In a
standard 8051 application, an external 64 KB ROM chip
(enabled by the 8051’s PSEN# signal) might be used for
program memory and an external 64 KB RAM chip (enabled
by the 8051’s RD# and WR# signals) might be used for data
memory.
In the standard 8051, all program memory is read only.
EZ-USB
The EZ-USB has 16 KB of on-chip RAM (the ‘main RAM’) at
addresses 0x0000-0x3FFF, and 512 bytes of on-chip RAM
(the ‘Scratch RAM’) at addresses 0xE000-0xE1FF. Although
this RAM is physically located inside the chip, it is addressed
by EZ-USB firmware as ‘External’ memory, just as though it
were in an external RAM chip.
Some systems use only this on-chip RAM, with no off-chip
memory. In those systems, the RD# and PSEN# strobes are
automatically combined for accesses to addresses below
0x4000, so the main RAM is accessible as both data and
program memory. The RD# and PSEN# strobes are not
combined for the Scratch RAM; Scratch RAM is accessible
as data memory only.
Although it is technically accurate to say that the main RAM
data memory is writable while the main RAM program mem-
ory is not, it is a distinction without a difference. The main
RAM is accessible both as program memory and data mem-
ory, so writing to main RAM data memory is equivalent to
writing to main RAM program memory at the same address.
The Scratch RAM is never accessible as program memory.
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 73
Memory
The EZ-USB also reserves 7.5 KB (0xE200-0xFFFF) of the
data-memory address space for control/status registers and
endpoint buffers (see section On-Chip Data Memory at
0xE000-0xFFFF on page 76). Note Only the data-memory
space is reserved; program memory in the 0xE000-0xFFFF
range is not reserved, so the 128-pin EZ-USB can access
off-chip program memory in that range.
5.3.1 56- and 100-Pin EZ-USB Chips
The 56- and 100-pin EZ-USB chips have no facility for add-
ing off-chip program or data memory. Therefore, the main
RAM must serve as both program and data memory. To
accomplish this, the EZ-USB reads the main RAM using the
logical OR of the PSEN# and RD# strobes. It is the respon-
sibility of the system designer to ensure that the program-
and data-memory spaces do not overlap; with most C com-
pilers, this is done by using linker directives that place the
code and data modules into separate areas.
5.3.2 128-Pin EZ-USB Chip
It is possible to add off chip program and data memory to the
128-pin EZ-USB; the organization of that memory depends
on the state of the EA (External Access) pin. Note that the
EA pin is ‘live’, meaning it is always active and not just sam-
pled coming out of a chip reset.
EA = 0
The main RAM is accessible both as program and data
memory, just as in the 56- and 100-pin EZ-USB.
To avoid conflict with the main RAM, the pins which control
access to off-chip memory (the RD#, WR#, CS#, OE#, and
PSEN# pins) are inactive whenever the EZ-USB accesses
addresses 0x0000-0x3FFF. This allows a 64 KB memory
chip (data and/or program) to be added without requiring
additional external logic to inhibit access to the lower 16 KB
of that chip. Note that the PSEN# and RD# signals are avail-
able on separate pins, so the program and data spaces out-
side the EZ-USB are not combined as they are inside the
EZ-USB.
When code in the range 0x0000-0x3FFF is fetched from the
on-chip RAM, the PSEN# pin is not asserted; when code is
fetched from program memory in the range 0x4000-0xFFFF,
the PSEN# pin is asserted.
EA = 1
All program memory is off chip; all on chip RAM, including
the main RAM, is data memory only.
The EZ-USB reads all on-chip RAM using only the RD#
strobe; the combining of RD# and PSEN# is disabled, so the
on-chip RAM becomes data memory only. All program mem-
ory is off-chip; accesses to the lower 16 KB of off-chip pro-
gram memory are not inhibited.
Any code fetch asserts the PSEN# pin.
After a power on reset, the EZ-USB immediately begins exe-
cuting code at address 0x0000 in the off-chip program mem-
ory (as long as there is no EEPROM on the I2C bus with a
valid 0xC0 or 0xC2 signature byte), rather than waiting for
an EEPROM load or USB code download to complete (see
the Resets chapter on page 83 for a full description of the
EZ-USB resets).
74 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Memory
5.4 EZ-USB Memory Maps
Figure 5-2. EZ-USB External Program/Data Memory Map, EA=0
Figure 5-2 illustrates the memory map of the 128-pin EZ-
USB with off-chip program and data memory.
Note The 56- and 100-pin EZ-USB chips cannot access off-
chip memory; the entire memory map for those chips is illus-
trated on the left side of Figure 5-2, in the ‘Inside EZ-USB’
column.
On-chip EZ-USB memory consists of three RAM regions:
■0x0000-0x3FFF (main RAM)
■0xE000-0xE1FF (Scratch RAM)
■0xE200-0xFFFF (Registers/Buffers)
The 16 KB main RAM occupies program memory (PSEN#)
and data memory (RD#/WR#) addresses 0x0000-0x3FFF.
The 512 byte ‘Scratch RAM’ occupies data memory (RD#/
WR#) addresses 0xE000-0xE1FF.
7.5 KB of control/status registers and endpoint buffers
occupy data-memory (RD#/WR#) addresses 0xE200-
0xFFFF.
When off-chip memory is connected to the EZ-USB, it fills in
the gaps not occupied by on-chip EZ-USB RAM. Since the
lower 16 KB of memory is occupied by on-chip program/data
memory and the upper 8 KB is occupied by on-chip data
memory, the off-chip memory cannot be active in these
regions. Nevertheless, it is still safe to populate those
regions with off-chip memory, as the following paragraphs
explain.
The middle column of Figure 5-2 indicates EZ-USB data
memory (activated by the RD# and WR# strobes) and the
right-most column indicates EZ-USB program memory (acti-
vated by PSEN#).
The middle 40 KB of the data memory space may be filled
with off-chip memory, since it does not conflict with the
upper 8 KB of on-chip EZ-USB data memory and the lower
16 KB of on-chip EZ-USB program/data memory. To allow a
64 KB RAM to be connected to the EZ-USB, the EZ-USB
gates its RD# and WR# strobes to exclude the top 8 KB and
bottom 16 KB for off-chip accesses. Therefore, a 64 KB
RAM can be connected to EZ-USB, and the top 8 KB and
bottom 16 KB of it are automatically disabled.
7.5 KB
USB regs and
EP buffers
(RD#,WR#)
0.5 KB RAM
Data
(RD#,WR#)*
16 KB RAM
Program & Data
(PSEN#,
RD#,WR#)*
E000
E200
3FFF
0000
FFFF
40 KB
External
Data
Memory
(RD#,WR#)
48 KB
External
Program
Memory
(PSEN#)
(OK to populate
data memory
here--RD#/WR#
strobes are not
active)
Inside EZ-USB Outside EZ-USB
EA=0
* SUDPTRH:L, USB upload/download, I2C boot access
(OK to populate
data memory
here--RD#/WR#
strobes are not
active)
(OK to populate
program
memory here--
PSEN# strobe is
not active)
data memory program memory
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 75
Memory
Likewise, when a 64 KB program memory (PSEN# strobe) is
attached to the EZ-USB (when EA = 0), the lower 16 KB is
automatically excluded for off-chip code fetches, avoiding
conflict with the on-chip program/data memory inside EZ-
USB. This allows the ‘upper’ 48 KB of program memory
space to be filled with off-chip memory.
The asterisks in Figures Figure 5-2 on page 74 and
Figure 5-3 indicate memory regions that may be accessed
using three special EZ-USB resources:
■Setup Data Pointer (see section 8.7 The Setup Data
Pointer on page 95)
■Upload or download via USB (see section 3.8 EZ-USB
Vendor Request for Firmware Load on page 56)
■Code boot from an I2C EEPROM (see section 13.6
EEPROM Boot Loader on page 192 and section 3.4
EEPROM Boot-load Data Formats on page 52)
Figure 5-3 illustrates the 128-pin EZ-USB memory map
when the EA pin is tied high. Note The only difference from
Figure 5-2 is that the main RAM is data memory only,
instead of combined code/data memory. This allows an off-
chip code memory to contain all of the EZ-USB firmware. In
this configuration, the EZ-USB can begin executing code
from off-chip memory immediately after power-on-reset.
Note EZ-USB code execution begins at address 0x0000,
where the reset vector is located.
Off-chip data memory is partially disabled just as in
Figure 5-2 on page 74, ensuring that off-chip data memory
does not conflict with on-chip data RAM.
Note Be careful to check the access time of external Flash
or other program memory in this mode. The EZ-USB can
stretch its RD# and WR# strobes to compensate for slow
data memories, but it does not have the capability to stretch
its PSEN# signal to allow for slow program memories. An
external program memory chip must meet the program
memory access-time specifications given in the FX2LP and
FX1 data sheets.
Figure 5-3. EZ-USB External Program/Data Memory Map, EA=1
7.5 KB
USB regs and
EP buffers
(RD#,WR#)
0.5 KB RAM
Data
(RD#,WR#)*
16 KB RAM
Data
(RD#,WR#)*
E000
E200
3FFF
0000
FFFF
40 KB
External
Data
Memory
(RD#,WR#)
64 KB
External
Program
Memory
(PSEN#)
Inside EZ-USB Outside EZ-USB
EA=1
(OK to populate
data memory
here--RD#/WR#
strobes are not
active)
(OK to populate
data memory
here--RD#/WR#
strobes are not
active)
* SUDPTRH:L, USB upload/download, I2C boot access
data memory program memory
76 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Memory
5.5 ‘Von-Neumannizing’ Off-
Chip Program and Data
Memory
The 128-pin EZ-USB package provides a 16-bit address
bus, an 8 bit data bus, and memory control signals PSEN#,
RD#, and WR#. These signals are used to expand the EZ-
USB’s external program and/or external data memory.
As described in the previous section, the EZ-USB gates the
RD# and WR# signals to exclude selection of off-chip data
memory in the range occupied by the on-chip memory. The
PSEN# signal is also available on a pin for connection to off-
chip code memory.
In some systems, it may be desirable to combine off-chip
program and data memory, just as the EZ-USB combines its
on-chip program/data main RAM. These systems must logi-
cally OR the PSEN# and RD# strobes to qualify the off-chip
memory’s chip enable and output enable signals. To save
the external logic which would normally be needed, EZ-USB
provides two additional control signals, CS# and OE#. The
equations for these active-low signals are:
CS# = RD# + WR# + PSEN#
OE# = RD# + PSEN#
Because the RD#, WR#, and PSEN# signals are already
qualified by the addresses allocated to off-chip memory, the
added strobes CS# and OE# strobes are active only when
the EZ-USB accesses off-chip memory.
5.6 On-Chip Data Memory at
0xE000-0xFFFF
Figure 5-4. On-Chip Data Memory at 0xE000-0xFFFF
Figure 5-4 shows the memory map for on-chip data RAM at
0xE000-0xFFFF.
512 bytes of Scratch RAM are available at 0xE000-0xE1FF.
This is data RAM only; code cannot be executed from it. The
128 bytes at 0xE400-0xE47F hold the four waveform
descriptors for the GPIF, described in the General Program-
mable Interface chapter on page 121. The area from
0xE500-0xE6FF contains EZ-USB control and status regis-
ters.
Memory blocks 0xE200-0xE3FF, 0xE480-0xE4FF, 0xE700-
0xE73F, and 0xE800-0xEFFF) are reserved; they must not
be used for data storage.
The remaining RAM contains the endpoint buffers. These
buffers are accessible either as addressable data RAM (via
the ‘MOVX’ instruction) or as FIFOs (via the Autopointer,
described in section 8.8 Autopointers on page 96).
Scratch RAM (512)
Reserved (512)
GPIF Waveforms (128)
Reserved (128)
EZ-USB Control and Status
Registers (512)
Reserved (64)
EP0 IN/OUT (64)
EP1OUT (64)
EP1IN (64)
Reserved (2 KB )
EP2-EP8 (4 KB)
Buffers
FFFF
F000
EFFF
E7FF
E800
E7C0
E77F
E7BF
E780
E700
E740
E6FF
E73F
E500
E4FF
E480
E47F
E400
E3FF
E200
E1FF
E000
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 77
6. Power Management
6.1 Introduction
The USB host can ‘suspend’ a device to put it into a power-down mode. When the USB signals a Suspend operation, the EZ-
USB goes through a sequence of steps to allow the firmware first to turn off external power-consuming subsystems, and then
to enter a low-power mode by turning off the EZ-USB’s oscillator. Once suspended, the EZ-USB is awakened either by
resumption of USB bus activity or by assertion of one of its two WAKEUP pins (provided that they are enabled). This chapter
describes the suspend-resume mechanism.
It is important to understand the distinction between ‘suspend’, ‘resume’, ‘idle’, and ‘wakeup’.
■Suspend is a request (indicated by a 3-ms ‘J’ state on the USB bus) from the USB host/hub to the device. This request is
usually sent by the host when it enters a low power ‘suspended’ state. USB devices are required to enter a low power
state in response to this request.
The EZ-USB also provides a register called suspend; writing any value to it allows the EZ-USB to enter the suspended
state even when a Suspend condition does not exist on the bus.
■Resume is a signal initiated by the device or host driving a ‘K’ state on the USB bus, requesting that the host or device be
taken out of its low power ‘suspended’ mode. A USB device can only signal a resume if it has reported (through its Config-
uration Descriptor) that it is ‘remote wakeup capable’, and only if the host has enabled remote wakeup from that device.
■Idle is an EZ-USB low power state. EZ-USB firmware initiates this mode by setting bit zero of the PCON (Power Control)
register. To meet the stringent USB suspend current specification, the EZ-USB’s oscillator must be stopped; after the
PCON.0 bit is set, the oscillator stops if: a) a suspend condition exists on the bus or the Suspend register has been written
to, and b) all three wakeup sources are either disabled or false (WAKEUP, WU2, USB Resume). The EZ-USB exits the
Idle state when it receives a wakeup interrupt.
■Wakeup is the mechanism which restarts the EZ-USB oscillator and asserts an interrupt to force the EZ-USB to exit the
Idle state and resume code execution. The EZ-USB recognizes three wakeup sources: one from the USB itself (when bus
activity resumes) and two from device pins (WAKEUP and WU2).
The EZ-USB enters and exits its Idle state independent of USB activity; in other words, the EZ-USB can enter the Idle state at
any time, even when not connected to USB. The Idle state is ‘hooked into’ the USB Suspend-Resume mechanism using inter-
rupts. A suspend interrupt is automatically generated when the USB goes inactive for 3 ms; EZ-USB firmware may respond to
that interrupt by entering the Idle state to reduce power. If the EZ-USB is in the Idle state, a Wakeup interrupt is generated
when one of the three Wakeup sources is asserted; the EZ-USB responds to that interrupt by exiting the Idle state and resum-
ing code execution.
Once the EZ-USB is awake, its firmware may send a USB Resume request by setting the SIGRSUME bit in the USBCS reg-
ister (at 0xE680). Before sending the Resume request, the device must have: a) reported remote-wakeup capability in its
Configuration Descriptor, and b) been given permission (via a ‘Set Feature-Remote Wakeup’ request from the host) to use
that remote-wakeup capability. To be compliant with the USB Specification, firmware must wait 5 ms after the Wakeup inter-
rupt, set the SIGRSUME bit, wait 10-15 ms, then clear it.
Figure 6-1 illustrates the EZ-USB logic that implements USB suspend and resume. These operations are explained in the
next sections.
78 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Power Management
Figure 6-1. Suspend-Resume Control
USB Resume
WAKEUP pin
OPEN
WUEN
WU2EN
WUPOL
WU2POL
WU2 pin
PLL
Oscillator
divider
8051
CLKOUT
24 MHz
START
PCON.0
STOP
USB
"SUSPEND"
Interrupt
No USB activity
for 3 msec.
"RESUME" INT Signal
Resume
(USBCS.0)
Restart
Delay
Resume
Suspend
Writes any value to
SUSPEND register
(0xE681)
EICON.5
(ERESI)
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 79
Power Management
6.2 USB Suspend
Figure 6-2. USB Suspend Sequence
A USB device recognizes a Suspend request as three milli-
seconds of the bus-idle state. When the EZ-USB detects
this condition, it asserts the USB interrupt (INT2) and the
Suspend interrupt autovector (vector #3).
If the CPU is in reset when a Suspend condition is detected
on the bus, the EZ-USB automatically turns off its oscillators
(and keep the CPU in reset) until an enabled Wakeup
source is asserted.
Note The bus-idle state is not equivalent to the discon-
nected-from-USB state; for full-speed, bus-idle is a ‘J’ state
which means that the voltage on D+ is higher than that on
D-.
EZ-USB firmware responds to the Suspend interrupt by tak-
ing the following actions:
1. Perform any necessary housekeeping such as shutting
off external power-consuming devices.
2. Set bit zero of the PCON register.
These actions put the EZ-USB into a low power ‘suspend’
state, as required by the USB Specification.
6.2.1 Suspend Register
EZ-USB firmware can force the chip into its low-power mode
at any time, even without detecting a 3-ms period of inactiv-
ity on the USB bus. This ‘unconditional suspend’ functional-
ity is useful in applications which require the EZ-USB to
enter its low-power mode even while disconnected from the
USB bus.
To force the EZ-USB unconditionally to enter its low-power
mode, firmware simply writes any value to the Suspend reg-
ister (at 0xE681) before setting the PCON.0 bit.
PLL
Oscillator
divider
8051
CLKOUT
24 MHz
STOP
USB
"SUSPEND"
Interrupt
No USB activity
for 3 msec.
PCON.0
Writes any value to
SUSPEND register
(0xE681)
Signal
Resume
(USBCS.0)
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Power Management
6.3 Wakeup/Resume
Figure 6-3. EZ-USB Wakeup/Resume Sequence
Once in the low-power mode, there are three ways to wake up the EZ-USB:
■USB activity on the EZ-USB’s DPLUS pin
■Assertion of the WAKEUP pin
■Assertion of the WU2 (‘Wakeup 2’) pin
These three Wakeup sources may be individually enabled by setting the DPEN, WUEN, and WU2EN bits in the Wakeup Con-
trol register.
The polarities of the WAKEUP pins are set using the
WUPOL and WU2POL bits; ‘0’ is active low and ‘1’ is active
high.
Three bits in the Wakeup register enable the three Wakeup
sources. DPEN stands for ‘DPLUS Enable’ (DPLUS is one
of the USB data lines; the other is DMINUS).
WUEN (Wakeup Enable) enables the WAKEUP pin, and
WU2EN (Wakeup 2 Enable) enables the WU2 pin.
When the EZ-USB chip detects activity on DPLUS while
DPEN is true, or a false-to-true transition on WAKEUP or
WU2 while WUEN or WU2EN is true, it asserts the Wakeup
interrupt.
The status bits WU and WU2 indicate which of the WAKEUP
pins caused the Wakeup event. Asserting the WAKEUP pin
(according to its programmed polarity) sets the correspond-
ing bit. If the wakeup was caused by resumption of USB
DPLUS activity, neither of these bits is set, leading to the
conclusion that the third source, a USB bus reset, caused
the Wakeup event. EZ-USB firmware clears the WU and
WU2 flags by writing ‘1’ to them.
Note Holding either WAKEUP pin in its active state (as
determined by the programmed polarity) inhibits the EZ-
USB chip from turning off its oscillator in order to enter the
‘suspend’ state.
Note While disconnected from the USB bus, the DPLUS
and DMINUS lines may float. Noise on these lines may indi-
cate activity to the EZ-USB and initiate a Wakeup event. EZ-
USB firmware must set DPEN to ‘0’ if this is not desired.
Some designs also use the WAKEUP# pin as a general pur-
pose input pin. Due to the built-in latch on this pin, it must be
WAKEUPCS Wakeup Control & Status E682
b7 b6 b5 b4 b3 b2 b1 b0
WU2 WU WU2POL WUPOL 0DPEN WU2EN WUEN
R/W R/W R/W R/W RR/W R/W R/W
0 0 0 0 0 1 0 1
PLL
Oscillator
divider
8051
CLKOUT
24 MHz
START
USB Resume
WAKEUP pin
"WAKEUP" INT Signal
Resume
(USBCS.0)
Restart
Delay
OPEN
WUEN
WU2EN
WUPOL
WU2POL
WU2 pin
EICON.5
(ERESI)
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 81
Power Management
cleared before it can show the current state of the pin. For
example, to detect a ‘1’ on the WAKEUP# pin use the follow-
ing code:
WAKEUPCS = bmWU | bmWUPOL | bmWUEN; //
Write one to bmWU to clear it, set
//
active high, enable
WAKEUPCS = bmWU | bmWUPOL | bmWUEN; // This
line is required only if WUPOL
// is
changing.
// A
WUPOL change can trigger a WAKEUP event
if (WAKEUPCS & bmWU)
{
// WAKEUP# is a one
}
else
{
// WAKEUP# is 0
}
Note If the polarity is changed, an additional Wakeup event
may be triggered. Always clear the Wakeup event after
changing the polarity.
6.3.1 Wakeup Interrupt
When a Wakeup event occurs, the EZ-USB restarts its oscil-
lator and, after the PLL stabilizes, it generates an interrupt
request. This applies whether or not the EZ-USB is con-
nected to the USB. The Wakeup interrupt is a dedicated
interrupt, and is not shared by USBINT like most of the other
individual USB interrupts.
The Wakeup interrupt vector is at 0x33, and has the highest
interrupt priority. It is enabled by ERESI (EICON.5), and its
IRQ flag is at EICON.4 (EICON is SFR 0xD8). Note If the
EZ-USB is suspended with ERESI (EICON.5) low, it never
‘wakes up’.
The Wakeup interrupt Service Routine clears the interrupt
request flag RESI (using the ‘bit clear’ instruction, i.e. ‘clr
EICON.4’), and then executes a ‘RETI’ (return from inter-
rupt) instruction. This causes the EZ-USB to continue pro-
gram execution at the instruction following the one that set
PCON.0 to initiate the power-down operation.
About the Wakeup Interrupt
The EZ-USB enters its idle state when it sets PCON.0 to ‘1’.
Although a standard 8051 exits the idle state when any inter-
rupt occurs, the EZ-USB supports only the Wakeup interrupt
to exit the idle state.
Note If PCON.0 is set when no Suspend condition exists
(for example, the USB is not signaling ‘Suspend’, and firm-
ware has not written to the Suspend register), the Wakeup
interrupt fires immediately.
6.4 USB Resume (Remote Wakeup)
Firmware sets the SIGRSUME bit to send a remote-wakeup
request to the host. To be compliant with the USB Specifica-
tion, the firmware must wait 5 milliseconds after the Wakeup
interrupt, set the SIGRSUME bit, wait 10-15 milliseconds,
then clear it.
Note Before setting the SIGRSUME bit to ‘1’, EZ-USB firm-
ware must check that the source of the Wakeup event was
one of the WAKEUP pins. If neither WAKEUP pin was the
source, the Wakeup event was the resumption of USB
DPLUS activity, and in this case, the device must not signal
a remote-wakeup by setting the SIGRSUME bit to ‘1’.
The Default USB Device does not support remote wakeup.
This fact is reported at enumeration time in byte 7 of the
built-in Configuration Descriptor (see Appendices A and B).
6.4.1 WU2 Pin
The WU2 function shares the general-purpose I/O pin PA3.
Unlike other multi-purpose I/O pins that use configuration
registers (PORTACFG, PORTCCFG, and PORTECFG) to
select alternate functions, the PA3 and WU2 functions are
simultaneously active. However, the WU2 function has no
effect unless enabled (by setting the WU2EN bit to ‘1’). If
WU2 is used as a WAKEUP pin, make sure to set PA3 as an
input (OEA.3=0, the default state) to prevent PA3 from also
driving the pin.
The dual nature of the PA3/WU2 pin allows the EZ-USB to
enter the low-power mode, then periodically awaken itself.
This is done by connecting an RC network to the PA3/WU2
pin; if the WU2 pin is set to the default polarity (active-high),
USBCS USB Control and Status E680
b7 b6 b5 b4 b3 b2 b1 b0
HSM - - - DISCON NOSYNSOF RENUM SIGRSUME
82 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Power Management
the resistor is connected to 3.3V and the capacitor is con-
nected to ground.
The firmware then performs these steps:
1. Set W2POL to ‘1’ for active-high polarity on the WU2 pin.
2. Set WU2EN to ‘1’ to enable Wakeup 2.
3. Enable the Wakeup interrupt by setting EICON.5=1.
4. Set PA3 to ‘0’, then set OEA.3 to ‘1’. This enables the
PA3 output and drives the PA3/WU2 pin to ground, dis-
charging the capacitor.
5. Set OEA.3 to ‘0’. This floats the PA3/WU2 pin, allowing
the resistor to begin charging the capacitor.
6. Write any value to the Suspend register, so the EZ-USB
unconditionally stops the oscillator when the firmware
sets PCON.0.
7. Set PCON.0 to ‘1’. This commands the EZ-USB to enter
the Idle state.
After the capacitor charges to a logic high level, the Wakeup
interrupt triggers via the WU2 pin.
1. In the Wakeup interrupt service routine, clear EICON.4
(the Wakeup interrupt request flag), then execute a
‘RETI’ instruction. This resumes program execution at
the instruction following the instruction in step 7.
2. At this point, the firmware can check for any tasks to per-
form; if none are required, it can then re-enter the Idle
state starting at step 4.
By selecting a long time constant for the RC network
attached to the WU2 pin, the EZ-USB chip can operate at
extremely low average power, since the on/off (active/sus-
pend) duty-cycle is very short.
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 83
7. Resets
7.1 Introduction
There are three different reset functions on the EZ-USB. This chapter describes their effects.
■Hard Reset. An active low reset pin (RESET#) is provided in order to reset the EZ-USB to a known state at power-on or
any other application-specific reset event.
■CPU Reset. This is controlled by the EZ-USB’s USB Core logic. The CPU Reset is always asserted (for example, the CPU
is always held in reset) while the EZ-USB’s RESET# pin is asserted.
■USB Bus Reset. This is a condition on the USB bus initiated by the USB host in order to put every device’s USB functions
in a known state.
Figure 7-1. EZ-USB Resets
7.2 Hard Reset
The RESET# pin can be connected to an external R-C network or other external reset source in order to ensure that, when
power is first applied, the EZ-USB is held in reset until the operating parameters (VCC voltage, crystal frequency, PLL fre-
quency, and others) stabilize. The 24 MHz oscillator and PLL stabilize 5 ms after VCC reaches 3.0V. An R-C network can sat-
isfy the power-on reset requirements of the EZ-USB. See Figure 7-1 for a sample connection scheme (for example, R = 27K
ohm, C = 1 µF).
The RESET# pin can also be asserted at any time after the EZ-USB is running. If the EZ-USB’s XTALIN pin is driven by an
external clock source that continues to run while the chip is in reset, RESET# need only be asserted for 200 µs. Otherwise, it
must be asserted for at least 5 ms.
RESET# RES
USB Core
CPU
RES
CPUCS.0
(1 at PWR ON)
Oscillator
XTALIN
XTALOUT
PLL ÷1, ÷2,
or ÷4
24
MHz
CLKOUT
12, 24,
or 48
MHz
48 MHz
USB Bus
Reset
Vcc
DPLUS
DMINUS
84 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Resets
The CLKOUT pin, crystal oscillator, and PLL are active as
soon as power is applied. Once the CPU is out of reset, firm-
ware may clear a control bit (CLKOE, CPUCS.1) to inhibit
the CLKOUT output pin for EMI-sensitive applications that
do not need this signal.
The CLKOUT signal is active while RESET# is low. When
RESET# returns high, the activity on the CLKOUT pin
depends on whether or not the EZ-USB is in the low-power
‘suspend’ state; if it is, CLKOUT stops. Resumption of USB
bus activity or assertion of the WAKEUP or WU2 pin (if
enabled) restarts the CLKOUT signal.
Power-on default values for all EZ-USB register bits are
shown in the Registers chapter on page 211. At power-on
reset:
■Endpoint data buffers and byte counts are uninitialized
■The CPU clock speed is set to 12 MHz, the CPU is held
in reset, and the CLKOUT pin is active
■All port pins are configured as general purpose input
pins
■USB interrupts are disabled and USB interrupt requests
are cleared
■Bulk IN and OUT endpoints are unarmed, and their stall
bits are cleared. The EZ-USB NAKs IN and OUT tokens
while the CPU is reset.
■Endpoint data toggle bits are cleared to ‘0’
■The RENUM bit is cleared to ‘0’. This means that the
Default USB Device, not the firmware, responds to USB
device requests.
■The USB Function Address register is cleared to ‘0’
■The endpoints are configured for the Default USB
Device
■Interrupt autovectoring is turned Off
■Configuration Zero, Alternate Setting Zero is in effect
■The D+ pull up resistor is disconnected from the data line
during a hard reset
7.3 Releasing the CPU Reset
Register bit CPUCS.0 resets the CPU. This bit is set to ‘1’ at
power-on, initially holding the CPU in reset. There are three
ways that the CPUCS.0 bit can be cleared to ‘0’, releasing
the CPU from reset:
■By the host, as the final step of a RAM download
■Automatically, at the end of an EEPROM load (assuming
the EEPROM is correctly programmed)
■Automatically, when external ROM is used (EA=1) and
no ‘C0’ or ‘C2’ EEPROM is present
Note EZ-USB firmware cannot put the CPU into reset by
setting CPUCS.0 to ‘1’; to the firmware, that bit is read only.
7.3.1 RAM Download
Once enumerated, the host can download code into the EZ-
USB RAM using the ‘Firmware Load’ vendor request (End-
point Zero chapter on page 37). The last packet loaded
writes 0x00 to the CPUCS register, which releases the CPU
from reset. Note that only CPUCS.0 can be written in this
way.
7.3.2 EEPROM Load
The Enumeration and ReNumeration™ chapter on page 51
describes the EEPROM boot loads in detail. At power-on,
the EZ-USB checks for the presence of an EEPROM on its
I2C bus. If found, it reads the first EEPROM byte. If it reads
0xC2 as the first byte, the EZ-USB downloads firmware from
the EEPROM into internal RAM. The last operation in a ‘C2’
Load writes 0x00 to the CPUCS register, which releases the
CPU from reset.
After a ‘C2’ Load, the EZ-USB sets the RENUM bit to ‘1’, so
the firmware is responsible for responding to USB device
requests.
7.3.3 External ROM
The 128-pin EZ-USB can use off-chip program memory con-
taining EZ-USB code and USB device descriptors, which
include the VID/DID/PID bytes. Because such a system
does not require an I2C EEPROM to supply the VID/DID/
PID, the EZ-USB automatically releases the CPU from reset
when:
■The EA pin is pulled high (indicating off-chip code mem-
ory), and
■No ‘C0/C2’ EEPROM is detected on the I2C bus
Under these conditions, the EZ-USB also sets the RENUM
bit to ‘1’, so the firmware is responsible for responding to
USB device requests.
7.4 CPU Reset Effects
The USB host may reset the CPU at any time by download-
ing the value 0x01 to the CPUCS register. The host might do
this, for example, in preparation for loading code overlays,
effectively magnifying the size of the internal EZ-USB RAM.
For such applications, it is important to know the state of the
EZ-USB chip during and after a CPU reset. In this section,
this particular reset is called a ‘CPU Reset,’ and should not
be confused with the resets described in section 7.2 Hard
Reset on page 83 This discussion applies only to the condi-
tion in which the EZ-USB chip is powered, and the CPU is
reset by the host setting the CPUCS.0 bit to ‘1’.
The basic USB device configuration remains intact through
a CPU reset. Endpoints keep their configuration, the USB
Function Address remains the same, and the I/O ports retain
their configurations and values. Stalled endpoints remain
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 85
Resets
stalled, data toggles do not change, and the RENUM bit is
unaffected. The only effects of a CPU reset are as follows:
■USB (INT2) interrupts are disabled, but pending interrupt
requests remain pending.
■When the CPU comes out of reset, pending interrupts
are kept pending, but disabled. This gives the firmware
writer the choice of acting on pre-reset USB events, or
ignoring them by clearing the pending interrupts before
enabling INT2.
■The breakpoint condition (BREAKPT.3) is cleared.
■While the CPU is in reset, the EZ-USB enters the Sus-
pend state automatically if a ‘suspend’ condition is
detected on the bus.
7.5 USB Bus Reset
The host signals a USB bus reset by driving an SE0 state
(both D+ and D- data lines low) for a minimum of 10 ms. The
EZ-USB senses this condition, requests the USB Interrupt
(INT2), and supplies the interrupt vector for a USB Reset.
After a USB bus reset, the following occurs:
■Data toggle bits are cleared to ‘0’.
■The device address is reset to ‘0’.
■If the Default USB Device is active, the USB configura-
tion and alternate settings are reset to ‘0’.
■The FX2LP renegotiates with the host for high-speed
(480 Mbps) mode.
Note that the RENUM bit is unchanged after a USB bus
reset. Therefore, if a device has ReNumerated™ and
loaded a new personality, it retains the new personality
through a USB bus reset.
7.6 EZ-USB Disconnect
Although not strictly a ‘reset,’ the disconnect-reconnect
sequence used for ReNumeration™ affects the EZ-USB in
ways similar to the other resets. When the EZ-USB simu-
lates a disconnect-reconnect, the following occurs:
■Endpoint STALL bits are cleared.
■Data toggles are reset to ‘0’.
■The Function Address is reset to ‘0’.
■If the Default USB Device is active, the USB configura-
tion and alternate settings are reset to ‘0’.
7.7 Reset Summary
Table 7-1. Effects of Various Resets on EZ-USB Resources
(“—” means “no change”)
RESET#
Pin CPU
Reset USB Bus
Reset Disconne
ct
CPU Reset Reset n/a — —
IN Endpoints Unarm — — —
OUT Endpoints Unarm — — —
Breakpoint 00 — —
Stall Bits 0— — 0
Interrupt Enables 00 — —
Interrupt Requests 0— — —
CLKOUT Active — — —
CPU Clock Speed 12 MHz — — —
Data Toggles 0— 0 0
Function Address 0— 0 0
Default USB
Device
Configuration
0— 0 0
Default USB
Device
Alternate Setting
0— 0 0
RENUM Bit 0— — —
86 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Resets
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8. Access to Endpoint Buffers
8.1 Introduction
USB data enters and exits the EZ-USB via endpoint buffers. Note External logic usually reads and writes this data by direct
connection to the endpoint FIFOs without any participation by the EZ-USB’s CPU. This is especially necessary for the FX2LP,
which can operate at the high-speed 480 Mbits/sec transfer rate. However, this feature is also available for FX2LP when
attached to a full-speed host and for the full-speed-only FX1.
Note The chapters Slave FIFOs, on page 99 and General Programmable Interface, on page 121 give details about how
external logic directly connects to the large endpoint FIFOs. Direct connection is available only on endpoints 2, 4, 6, and 8.
In the following sections, references to full-speed behavior refer to both FX2LP attached to a full-speed host and to the full-
speed-only FX1.
When an application requires the CPU to process the data as it flows between external logic and the USB — or when there is
no external logic — firmware can access the endpoint buffers either as blocks of RAM or (using a special auto-incrementing
pointer) as a FIFO.
Even when external logic or the built-in General Programmable Interface (GPIF) is handling high-bandwidth data transfers
through the four large endpoint FIFOs without any CPU intervention, the firmware has certain responsibilities:
■Configure the endpoints
■Respond to host requests on CONTROL endpoint zero
■Control and monitor GPIF activity
■Handle all application-specific tasks using its USARTs, counter-timers, interrupts, I/O pins, and so on
8.2 EZ-USB Large and Small Endpoints
EZ-USB endpoint buffers are divided into ‘small’ and ‘large’ groups. EP0 and EP1 are small, 64-byte endpoints which are
accessible only by the CPU; they cannot be connected directly to external logic.
EP2, EP4, EP6 and EP8 are large, configurable endpoints designed to meet the high-bandwidth requirements of USB 2.0.
Although data normally flows through the large endpoint buffers under control of the FIFO interfaces described in Chapters 9
and 10, the CPU can access the large endpoints if necessary.
8.3 High Speed and Full Speed Differences
The data payload size and transfer speed requirements differ between full speed (12 Mbps) and high speed (480 Mbps). The
EZ-USB architecture is optimized for high-speed transfers, but does not limit full-speed transfers:
■Instead of many small endpoint buffers, EZ-USB provides a reduced number of large buffers
■EZ-USB provides double, triple, or quad buffering on its large endpoints (EP2, 4, 6, and 8)
■The CPU need not participate in data transfers. Instead, dedicated EZ-USB logic and unified endpoint/interface FIFOs
move data on and off the chip without any CPU intervention.
In the FX2LP, endpoint buffers appear to have different sizes depending on whether it is operating at full or high speed. This
is due to the difference in maximum data payload sizes allowed by the USB specification for the two modes, as illustrated by
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Table 8-1. FX1 always operates in full-speed mode.
Although the EP2, EP4, EP6, and EP8 buffers are physically
large, they appear as smaller buffers for the non-isochro-
nous types when the EZ-USB is operating at full speed. This
is to account for the smaller maximum data payload sizes.
When operating at high speed, firmware can configure the
large endpoints’ size, type, and buffering depth; when oper-
ating at full speed, type and buffering are configurable but
the buffer size is always fixed at 64 bytes for the non-iso-
chronous types.
8.4 How the CPU Configures the Endpoints
Endpoints are configured using the six registers shown in Table 8-2.
Note The Registers chapter on page 211 gives full bit-level
details for all endpoint configuration registers.
Endpoint 0 does not require a configuration register since it
is fixed as valid, IN/OUT, CONTROL, 64 bytes, single-buff-
ered. EP0 uses a single 64-byte buffer both for IN and OUT
transfers. EP1 uses separate 64 byte buffers for IN and OUT
transfers.
Endpoints EP2 and EP6 are the most flexible endpoints, as
they are configurable for size (512 or 1024 bytes in high-
speed mode, 64 bytes in full-speed mode for the non-iso-
chronous types) and depth of buffering (double, triple, or
quad). Endpoints EP4 and EP8 are fixed at 512 bytes, dou-
ble-buffered in high-speed mode. They are fixed at 64 bytes,
double-buffered in full-speed mode for the non-isochronous
types.
The bits in the EPxCFG registers control the following:
■Valid. Set to ‘1’ (default) to enable the endpoint. A non-
valid endpoint does not respond to host IN or OUT pack-
ets.
■Type. Two bits, TYPE1:0 (bits 5 and 4) set the endpoint
type.
❐00 = invalid
❐01 = ISOCHRONOUS (EP2,4,6,8 only)
❐10 = BULK (default)
❐11 = INTERRUPT
■Direction. 1 = IN, 0 = OUT.
■Buffering. EP2 and EP6 only. Two bits, BUF1:0 control
the depth of buffering.
❐00 = quad
❐01 = invalid
❐10 = double (default)
❐11 = triple
‘Buffering’ refers to the number of RAM blocks available to
the endpoint. With double buffering, for example, USB data
can fill or empty an endpoint buffer at the same time that
another packet from the same endpoint fills or empties from
the external logic. This technique maximizes performance
Table 8-1. Maximum Data Payload Sizes for Full Speed and
High Speed
Transfer Type Max Data Payload Size
Full Speed High Speed
CONTROL (EP0 only) 8,16,32,64 64
BULK 8,16,32,64 512
INTERRUPT 1-64 1-1024
ISOCHRONOUS 1-1023 1-1024
Table 8-2. Endpoint Configuration Registers
Address Name Configurable Parameters
0xE610 EP1OUTCFG valid, type1 (always OUT, 64 bytes, single-buffered)
0xE611 EP1INCFG valid, type1 (always IN, 64 bytes, single-buffered)
0xE612 EP2CFG valid, direction, type, size, buffering
0xE613 EP4CFG valid, direction, type (always 512 bytes, double-buffered in high-speed mode, 64 bytes double-buffered in full-
speed mode for non-iso)
0xE614 EP6CFG valid, direction, type, size, buffering
0xE615 EP8CFG valid, direction, type (always 512 bytes double-buffered in high-speed mode, 64 bytes double-buffered in full-
speed mode for non-iso)
Note 1: For EP1, ‘type’ may be set to Interrupt or Bulk only. Even though these buffers are 64 bytes in size, they are reported as 512 for USB 2.0 compliance.
The user must never transfer packets larger than 64 bytes to EP1.
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Access to Endpoint Buffers
by saving each side, USB and external-logic interface, from
waiting for the other side. Multiple buffering is most effective
when the providing and consuming rates are comparable
but bursty (as is the case with USB and many other inter-
faces, such as disk drives). Assigning more RAM blocks (tri-
ple and quad buffering) provides more ‘smoothing’ of the
bursty data rates. A simple way to determine the appropriate
buffering depth is to start with the minimum, then increase it
until no NAKs appear on the USB side and no wait states
appear on the interface side.
Note The Valid bit is ignored when buffer space is allocated
by the EZ-USB (for example, BUF[1:0] takes precedence
over the Valid bit).
When you are not using all of the endpoints in the endpoint
configuration, disable the unused endpoints by writing a
zero into the “valid” bit of the corresponding EPxCFG
register without disturbing the default state of the other bits
in the register.
For example, if the endpoint configuration 11 (see 1.17 EZ-
USB Endpoint Buffers on page 30), which utilizes only
endpoints 2 and 8, must be used, configure the endpoints as
follows.
EP2CFG = 0xDB;
SYNCDELAY;
EP8CFG = 0x92;
SYNCDELAY;
EP4CFG &= 0x7F;
SYNCDELAY;
EP6CFG &=0x7F;
SYNCDELAY;
8.5 CPU Access to EZ-USB
Endpoint Data
Endpoint data is visible to the CPU at the addresses shown
in Table 8-3. Whenever the application calls for endpoint
buffers smaller than the physical buffer sizes shown in
Table 8-3, the CPU accesses the endpoint data starting from
the lowest address in the buffer. For example, if EP2 has a
reported MaxPacketSize of 512 bytes, the CPU accesses
the data in the lower portion of the EP2 buffer (that is, from
0xF000 to 0xF1FF). Similarly, if the EZ-USB is operating in
full-speed mode (which dictates a maximum bulk packet
size of only 64 bytes), only the lower 64 bytes of the end-
point (for example, 0xF000-0xF03F for EP2) are used for
bulk data.
Note EP0BUF is for the (optional) data stage of a Control
transfer. The eight bytes of data from the Control packet
appear in a separate EZ-USB RAM buffer called SETUP-
DAT, at 0xE6B8-0xE6BF.
The CPU can only access the ‘active’ buffer of a multiple-
buffered endpoint. In other words, firmware must treat a
quad-buffered 512-byte endpoint as being only 512 bytes
wide, even though the quad-buffered endpoint actually
occupies 2048 bytes of RAM. Also, when EP2 and EP6 are
configured such that EP4 and/or EP8 are unavailable, the
firmware must never attempt to access the buffers corre-
sponding to those unavailable endpoints.
For example, if EP2 is configured for triple-buffered 1024-
byte operation, the firmware should access EP2 only at
0xF000-0xF3FF. The firmware should not access the EP4 or
EP6 buffers in this configuration, since they do not exist (the
RAM space which they would normally occupy is used to
implement the EP2 triple-buffering).
8.6 CPU Control of EZ-USB
Endpoints
From the CPU’s point of view, the ‘small’ and ‘large’ end-
points operate slightly differently, due to the multiple-packet
buffering scheme used by the large endpoints.
The CPU uses internal registers to control the flow of end-
point data. Since the small endpoints EP0 and EP1 are pro-
grammed differently than the large endpoints EP2, EP4,
EP6, and EP8, these registers fall into three categories:
■Registers that apply to the small endpoints (EP0, EP1IN,
and EP1OUT)
■Registers that apply to the large endpoints (EP2, EP4,
EP6, and EP8)
■Registers that apply to both sets of endpoints
Table 8-3. Endpoint Buffers in RAM Space
Name Address Size (bytes)
EPOBUF 0xE740-0xE77F 64
EP1OUTBUF 0xE780-0xE7BF 64
EP1INBUF 0xE7C0-0xE7FF 64
EP2FIFOBUF 0xF000-0xF3FF 1024
EP4FIFOBUF 0xF400-0xF7FF 1024
EP6FIFOBUF 0xF800-0xFBFF 1024
EP8FIFOBUF 0xFC00-0xFFFF 1024
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8.6.1 Registers That Control EP0,
EP1IN, and EP1OUT
8.6.1.1 EP0CS
Firmware uses this register to coordinate Control transfers
over endpoint 0. The EP0CS register contains three bits:
HSNAK, Busy and Stall.
HSNAK
HSNAK is automatically set to ‘1’ whenever the SETUP
token of a Control transfer arrives. The EZ-USB logic auto-
matically NAKs the status (handshake) stage of the Control
transfer until the firmware clears the HSNAK bit by writing ‘1’
to it. This mechanism gives the firmware a chance to hold off
subsequent transfers until it completes the actions required
by the Control transfer.
Note Firmware must clear the HSNAK bit after servicing
every Control transfer.
BUSY
The read-only Busy bit is relevant only for the data stage of
a Control transfer. BUSY=1 indicates that the endpoint is
currently being serviced by USB, so firmware should not
access the endpoint data.
‘Busy’ is automatically cleared to ‘0’ whenever the SETUP
token of a Control transfer arrives. The Busy bit is set to ‘1’
under different conditions for IN and OUT transfers.
For EP0 IN transfers, EZ-USB logic will NAK all IN tokens to
EP0 until the firmware has ‘armed’ EP0 for IN transfers by
writing to the EP0BCH:L Byte Count register, which sets
BUSY=1 to indicate that firmware should not access the
data. Once the endpoint data is sent and acknowledged,
Busy is automatically cleared to ‘0’ and the EP0IN interrupt
request bit is asserted. After Busy is automatically cleared to
‘0’, the firmware may refill the EP0IN buffer.
For EP0 OUT transfers, EZ-USB logic will NAK all OUT
tokens to EP0 until the firmware has ‘armed’ EP0 for OUT
transfers by writing any value to the EP0BCL register. Busy
is automatically set to ‘1’ when the firmware writes to
EP0BCL, and Busy is automatically cleared to ‘0’ after the
data has been correctly received and ACK’d. When Busy
transitions to zero, the EZ-USB also generates an EP0OUT
interrupt request.
Note The EZ-USB’s autovectored interrupt system automat-
ically transfers control to the appropriate Interrupt Service
Routine (ISR) for the endpoint requiring service. The
Interrupts chapter on page 59 describes this mechanism.
STALL
Set STALL=1 to instruct the EZ-USB to return the Stall
response to a Control transfer. This is generally done when
the firmware does not recognize an incoming USB request.
According to the USB specification, endpoint zero must
always accept transfers, so Stall is automatically cleared to
‘0’ whenever a SETUP token arrives. If it is desired to stall a
transfer and also clear HSNAK to ‘0’ (by writing a ‘1’ to it),
the firmware should set STALL=1 first, in order to ensure
that the Stall bit is set before the ‘acknowledge’ phase of the
Control transfer can complete.
8.6.1.2 EP0BCH and EP0BCL
These are the byte count registers for bytes sent as the
optional data stage of a Control transfer. Although the EP0
buffer is only 64 bytes wide, the byte count registers are 16
bits wide to allow using the Setup Data Pointer to send USB
IN data records that consist of multiple packets.
To use the Setup Data Pointer in its most-general mode,
firmware clears the SUDPTR AUTO bit and writes the word-
aligned address of a data block into the Setup Data Pointer,
then loads the EP0BCH:L registers with the total number of
bytes to transfer. The EZ-USB automatically transfers the
entire block, partitioning the data into MaxPacketSize pack-
ets as necessary.
Note The Setup Data Pointer is the subject of section 8.7
The Setup Data Pointer on page 95.
For IN transfers without using the Setup Data Pointer, firm-
ware loads data into EP0BUF, then writes the number of
bytes to transfer into EP0BCH and EP0BCL. The packet is
armed for IN transfer when the firmware writes to EP0BCL,
so EP0BCH should always be loaded first. These transfers
are always 64 bytes or less, so EP0BCH must be loaded
with ‘0’ (and EP0BCL must be in the range [0-64]). EP0BCH
holds that zero value until firmware overwrites it.
For EP0 OUT transfers, the byte count registers indicate the
number of bytes received in EP0BUF. Byte counts for EP0
OUT transfers are always 64 or fewer, so EP0BCH is always
zero after an OUT transfer. To re-arm the EP0 buffer for a
future OUT transfer, the firmware simply writes any value to
EP0BCL.
Note The EP0BCH register must be initialized on reset,
since its power-on-reset state is undefined.
Table 8-4. Registers that control EP0 and EP1
Address Name Function
0xE6A0 EP0CS EP0 HSNAK, Busy, Stall
0xE68A
0xE68B
EP0BCH
EP0BCL
EP0 Byte Count (MSB)
EP0 Byte Count (LSB)
0xE65C
0xE65D
USBIE
USBIRQ
EP0 Interrupt Enables
EP0 Interrupt Requests
SFR 0xBA EP01STAT Endpoint 0 and 1 Status
0xE6A1 EP1OUTCS EP1OUT Busy, Stall
0xE68D EP1OUTBC EP1OUT Byte Count
0xE6A2 EP1INCS EP1IN Busy, Stall
0xE68F EP1INBC EP1IN Byte Count
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8.6.1.3 USBIE, USBIRQ
Three interrupts — SUTOK, SUDAV, and EP0ACK — are
used to manage Control transfers over endpoint zero. The
individual enables for these three interrupt sources are in
the USBIE register, and the interrupt-request flags are in the
USBIRQ register.
Each of the three interrupts signals the completion of a dif-
ferent stage of a Control transfer.
■SUTOK. (Setup Token) asserts when EZ-USB receives
the SETUP token.
■SUDAV. (Setup Data Available) asserts when EZ-USB
logic has loaded the eight bytes from the SETUP stage
into the 8-byte buffer at SETUPDAT.
■EP0ACK. (Endpoint Zero Acknowledge) asserts when
the handshake stage has completed.
The SUTOK interrupt is not normally used; it is provided for
debug and diagnostic purposes. Firmware generally ser-
vices the Control transfer by responding to the SUDAV inter-
rupt, since this interrupt fires only after the eight setup bytes
are available for examination in the SETUPDAT buffer.
8.6.1.4 EP01STAT
The Busy bits in EP0CS, EP1OUTCS, and EP1INCS
(described later in this chapter) are replicated in this SFR;
they are provided here in order to allow faster access (via
the MOV instruction rather than MOVX) to those bits.
Three status bits are provided in the EP01STAT register; the
status bits are the following:
■EP1INBSY. 1 = EP1IN is busy
■EP1OUTBSY. 1 = EP1OUT is busy
■EP0BSY. 1 = EP0 is busy
8.6.1.5 EP1OUTCS
This register is used to coordinate Bulk or Interrupt transfers
over EP1OUT. The EP1OUTCS register contains two bits,
Busy and Stall.
BUSY
This bit indicates when the firmware can read data from the
Endpoint 1 OUT buffer. BUSY=1 means that the SIE ‘owns’
the buffer, so firmware should not read (or write) the buffer.
BUSY=0 means that the firmware may read from (or write
to) the buffer. A 1-to-0 Busy transition asserts the EP1OUT
interrupt request, signaling that new EP1OUT data is avail-
able.
‘Busy’ is automatically cleared to ‘0’ after the EZ-USB veri-
fies the OUT data for accuracy and ACKs the transfer. If a
transmission error occurs, the EZ-USB automatically retries
the transfer; error recovery is transparent to the firmware.
Firmware arms the endpoint for OUT transfers by writing
any value to the byte count register EP1OUTBC, which
automatically sets BUSY=1.
At power-on (or whenever a 0-to-1 transition occurs on the
RESET# pin), the Busy bit is set to ‘0’, so the EZ-USB will
NAK all EP1OUT transfers until the firmware arms EP1OUT
by writing any value to EP1OUTBC.
STALL
Firmware sets STALL=1 to instruct the EZ-USB to return the
Stall PID (instead of ACK or NAK) in response to an
EP1OUT transfer. The EZ-USB continues to respond to
EP1OUT transfers with the Stall PID until the firmware
clears this bit.
8.6.1.6 EP1OUTBC
Firmware may read this 7-bit register to determine the num-
ber of bytes (0-64) in EP1OUTBUF.
Firmware writes any value to EP1OUTBC to arm an
EP1OUT transfer.
8.6.1.7 EP1INCS
This register is used to coordinate Bulk or Interrupt transfers
over EP1IN. The EP1INCS register contains two bits: Busy
and Stall.
BUSY
This bit indicates when the firmware can load data into the
Endpoint 1 IN buffer. BUSY=1 means that the SIE ‘owns’ the
buffer, so firmware should not write (or read) the buffer.
BUSY=0 means that the firmware may write data into (or
read from) the buffer. A 1-to-0 Busy transition asserts the
EP1IN interrupt request, signaling that the EP1IN buffer is
free and ready to be loaded with new data.
The firmware schedules an IN transfer by loading up to 64
bytes of data into EP1INBUF, then writing the byte count
register EP1INBC with the number of bytes loaded (0-64).
Writing the byte count register automatically sets BUSY=1,
indicating that the transfer over USB is pending. After the
EZ-USB subsequently receives an IN token, sends the data,
and successfully receives an ACK from the host, Busy is
automatically cleared to ‘0’ to indicate that the buffer is
ready to accept more data. This generates the EP1IN inter-
rupt request, which signals that the buffer is again available.
At power on, or whenever a 0-to-1 transition occurs on the
RESET# pin, the Busy bit is set to ‘0’, meaning that the EZ-
USB will NAK all EP1IN transfers until the firmware arms the
endpoint by writing the number of bytes to transfer into the
EP1INBC register.
STALL
Firmware sets STALL=1 to instruct the EZ-USB to return the
Stall PID (instead of ACK or NAK) in response to an EP1IN
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transfer. The EZ-USB continues to respond to EP1IN trans-
fers with the Stall PID until the firmware clears this bit.
8.6.1.8 EP1INBC
Firmware arms an IN transfer by loading this 7-bit register
with the number of bytes (0-64) it has previously loaded into
EP1INBUF.
8.6.2 Registers That Control EP2, EP4,
EP6, EP8
Note In order to achieve the high transfer rates required by
USB 2.0’s high-speed mode, and to maximize full-speed
transfer rates, the EZ-USB’s CPU should not participate in
transfers to and from the ‘large’ endpoints. Instead, those
endpoints are usually connected directly to external logic
(see chapters Slave FIFOs, on page 99 and General Pro-
grammable Interface, on page 121 for details). Although
especially suited for high-speed (480 Mbits/sec) transfers,
the functionality of these endpoints is identical at full speed,
except for packet size.
Some applications, however, may require the firmware to
have at least some small amount of control over the large
endpoints. For those applications, the EZ-USB provides the
registers shown in Table 8-5.
8.6.2.1 EP2468STAT
The Endpoint Full and Endpoint Empty status bits (described
below, in section Section 8.6.2.3) are replicated here in
order to allow faster access by the firmware.
8.6.2.2 EP2ISOINPKTS, EP4ISOINPKTS,
EP6ISOINPKTS, EP8ISOINPKTS
These registers only apply to ISOCHRONOUS IN endpoints.
Refer to the EPxISOINPKTS register descriptions in the
Registers chapter on page 211 for details.
FX2LP has the capability of sending a zero-length packet
(ZLP) when the host issues an IN token to an isochronous
IN endpoint and the SIE does not have any data available.
These registers do not affect full-speed (12 Mbps) operation;
full-speed isochronous transfers are always fixed at one
packet per frame.
8.6.2.3 EP2CS, EP4CS, EP6CS, EP8CS
Because the four large EZ-USB endpoints offer double, tri-
ple or quad buffering, a single Busy bit is not sufficient to
convey the state of these endpoint buffers. Therefore, these
endpoints have multiple bits (NPAK, FULL, EMPTY) that can
be inspected in order to determine the state of the endpoint
buffers.
Note Multiple-buffered endpoint data must be read or written
only at the buffer addresses given in Table 8-3 on page 89.
The EZ-USB automatically switches the multiple buffers in
and out of the single addressable buffer space.
NPAK[2:0] (EP2, EP6) and NPAK[1:0] (EP4, EP8)
NPAK values have different interpretations for IN and OUT
endpoints:
■OUT Endpoints. NPAK indicates the number of packets
received over USB and ready for the firmware to read.
■IN Endpoints. NPAK indicates the number of IN packets
committed to USB (i.e., loaded and armed for USB
transfer), and thus unavailable to the firmware.
The NPAK fields differ in size to account for the depth of
buffering available to the endpoints. Only double buffering is
available for EP4 and EP8 (two NPAK bits), and up to quad
buffering is available for EP2 and EP6 (three NPAK bits).
FULL
While FULL and EMPTY apply to transfers in both direc-
tions, ‘FULL’ is more useful for IN transfers. It has the same
meaning as ‘Busy’, but applies to multiple-buffered IN end-
points. FULL=1 means that all buffers are committed to
USB, and none are available for firmware access.
For IN transfers, FULL=1 means that all buffers are commit-
ted to USB, so firmware should not load the endpoint buffer
with any more data. When FULL=1, NPAK holds 2, 3, or 4
Table 8-5. Registers that Control EP2,EP4,EP6 and EP8
Address Name Function
SFR 0xAA EP2468STAT EP2, 4, 6, 8 empty/full
0xE648 INPKTEND force end of IN packet
0xE649 OUTPKTEND skip or commit an OUT packet
0xE640 EP2ISOINPKTS ISO IN packets per frame or micro-
frame
0xE6A3 EP2CS npak, full, empty, stall
0xE690 EP2BCH byte count (H)
0xE691 EP2BCL byte count (L)
0xE641 EP4ISOINPKTS ISO IN packets per frame or micro-
frame
0xE6A4 EP4CS npak, full, empty, stall
0xE694 EP4BCH byte count (H)
0xE695 EP4BCL byte count (L)
0xE642 EP6ISOINPKTS ISO IN packets per frame/microframe
0xE6A5 EP6CS npak, full, empty, stall
0xE698 EP6BCH byte count (H)
0xE699 EP6BCL byte count (L)
0xE643 EP8ISOINPKTS ISO IN packets per frame/microframe
0xE6A6 EP8CS npak, full, empty, stall
0xE69C EP8BCH byte count (H)
0xE69D EP8BCL byte count (L)
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Access to Endpoint Buffers
depending on the buffering depth (double, triple or quad).
This indicates that all buffers are in use by the USB transfer
logic. As soon as one buffer becomes available, FULL is
cleared to ‘0’ and NPAK is decremented by one, indicating
that all but one of the buffers are committed to USB (i.e.,
one is available for firmware access). As IN buffers are
transferred over USB, NPAK decrements to indicate the
number still pending, until all are sent and NPAK=0.
EMPTY
While FULL and EMPTY apply to transfers in both direc-
tions, EMPTY is more useful for OUT transfers. EMPTY=1
means that the buffers are empty; all received packets (2, 3,
or 4, depending on the buffering depth) have been serviced.
STALL
Firmware sets STALL=1 to instruct the EZ-USB to return the
Stall PID (instead of ACK or NAK) in response to an IN or
OUT transfer. The EZ-USB continues to respond to IN or
OUT transfers with the Stall PID until the firmware clears this
bit.
8.6.2.4 EP2BCH:L, EP4BCH:L, EP6BCH:L,
EP8BCH:L
Endpoints EP2 and EP6 have 11-bit byte count registers to
account for their maximum buffer sizes of 1024 bytes. End-
points EP4 and EP8 have 10-bit byte count registers to
account for their maximum buffer sizes of 512 bytes.
The byte count registers function similarly to the EP0 and
EP1 byte count registers:
■For an IN transfer, the firmware loads the byte count reg-
isters to arm the endpoint (if EPxBCH must be loaded, it
should be loaded first, since the endpoint is armed when
EPxBCL is loaded).
■For an OUT transfer, the firmware reads the byte count
registers to determine the number of bytes in the buffer,
then writes any value to the low byte count register to re-
arm the endpoint. See the ‘Skip’ section, below, for fur-
ther details.
SKIP
Normally, the CPU interface and outside-logic interface to
the endpoint FIFOs are independent, with separate sets of
control bits for each interface. The AUTOOUT mode and the
SKIP bit implement an ‘overlap’ between these two
domains. A brief introduction to the AUTOOUT mode is
given below; full details appear in the Slave FIFOs chapter
on page 99
When outside logic is connected to the interface FIFOs, the
normal data flow is for the EZ-USB to commit OUT data
packets to the outside interface FIFO as they become avail-
able. This ensures an uninterrupted flow of OUT data from
the host to the outside world, and preserves the high band-
width required by the high-speed mode.
In some cases, it may be desirable to insert a ‘hook’ into this
data flow, so that – rather than the EZ-USB automatically
committing the packets to the outside interface as they are
received over USB – firmware receives an interrupt for every
received OUT packet, then has the option either to commit
the packet to the outside interface (the output FIFO), or to
discard it. The firmware might, for example, inspect a packet
header to make this skip/commit decision.
To enable this ‘hook’, the AUTOOUT bit is cleared to ‘0’. If
AUTOOUT = 0 and an OUT endpoint is re-armed by writing
to its low byte-count register, the actual value written to the
register becomes significant:
■If the SKIP bit (bit 7 of each EPxBCL register) is cleared
to ‘0’, the packet is committed to the output FIFO and
thereby made available to the FIFO’s master (either
external logic or the internal GPIF).
■If the SKIP bit is set to ‘1’, the just-received OUT packet
is not committed to the output FIFO for transfer to the
external logic; instead, the packet is ignored, its buffer is
immediately made available for the next OUT packet,
and the output FIFO (and external logic) never even
‘knows’ that it arrived.
Note The AUTOOUT bit appears in bit 4 of the Endpoint
FIFO Configuration Registers EP2FIFOCFG, EP4FIFOCFG,
EP6FIFOCFG and EP8FIFOCFG.
8.6.3 Registers That Control All
Endpoints
8.6.3.1 IBNIE, IBNIRQ, NAKIE, NAKIRQ
These registers contain the interrupt-enable and interrupt-
request bits for two endpoint conditions: IN-BULK-NAK and
PING.
Table 8-6. Registers That Control All Endpoints
Addres
sName Description
0xE658 IBNIE IN-BULK-NAK individual interrupt enables
0xE659 IBNIRQ IN-BULK-NAK individual interrupt requests
0xE65A NAKIE PING plus combined IBN-interrupt enable
0xE65B NAKIRQ PING plus combined IBN-interrupt request
0xE65C USBIE SUTOK, SUDAV, EP0-ACK, SOF interrupt
enables
0xE65D USBIRQ SUTOK, SUDAV, EP0-ACK, and SOF inter-
rupt requests
0xE65E EPIE Endpoint interrupt enables
0xE65F EPIRQ Endpoint interrupt requests
0xE662 USBERRIE USB error interrupt enables
0xE663 USBERRIE USB error interrupt requests
0xE664 ERRCNTLIM USB error counter and limit
0xE665 CLRERRCNT Clear error count
0xE683 TOGCTL Endpoint data toggles
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IN-BULK-NAK
When the host requests an IN packet from an EZ-USB
BULK endpoint, the endpoint NAKs (returns the NAK PID)
until the endpoint buffer is filled with data and armed for
transfer, at which point the EZ-USB answers the IN request
with data.
Until the endpoint is armed, a flood of IN-NAKs can tie up
bus bandwidth. Therefore, if the IN endpoints are not always
kept full and armed, it may be useful to know when the host
is ‘knocking at the door’, requesting IN data.
The IN-BULK-NAK (IBN) interrupt provides this notification.
The IBN interrupt fires whenever a Bulk endpoint NAKs an
IN request. The IBNIE/IBNIRQ registers contain individual
enable and request bits per endpoint, and the NAKIE/
NAKIRQ registers each contain a single bit, IBN, that is the
OR’d combination of the individual bits in IBNIE/IBNIRQ,
respectively.
Firmware enables an interrupt by setting the enable bit high,
and clears an interrupt request bit by writing a ‘1’ to it.
Note The EZ-USB interrupt system is described in detail in
the Interrupts chapter on page 59
The IBNIE register contains an individual interrupt-enable bit
for each endpoint: EP0, EP1, EP2, EP4, EP6, and EP8.
These bits are valid only if the endpoint is configured as a
Bulk or Interrupt endpoint. The IBNIRQ register similarly
contains individual interrupt request bits for the six end-
points.
The IBN interrupt-service routine should take the following
actions, in this order:
1. Clear the USB (INT2) interrupt request (by writing ‘0’ to
it).
2. Inspect the endpoint bits in IBNIRQ to determine which
IN endpoint just NAK’d.
3. Take the required action (set a flag, arm the endpoint,
etc.), then clear the individual IBN bit in IBNIRQ for the
serviced endpoint (by writing ‘1’ to it).
4. Repeat steps (2) and (3) for any other endpoints that
require IBN service, until all IRQ bits are cleared.
5. Clear the IBN bit in the NAKIRQ register (by writing ‘1’ to
it).
Note Because the IBN bit represents the OR’d combination
of the individual IBN interrupt requests, it does not ‘fire’
again until all individual IBN interrupt requests have been
serviced and cleared.
PING
PING is the ‘flip side’ of IBN; it is used for high-speed (480
Mbps) Bulk OUT transfers. Thus, PING is only applicable to
the FX2LP.
When operating at full speed, every host OUT transfer con-
sists of the OUT PID and the endpoint data, even if the end-
point is NAKing (not ready). While the endpoint is not ready,
the host repeatedly sends all the OUT data; if it is repeatedly
NAK’d, bus bandwidth is wasted.
USB 2.0 introduced a new mechanism, called PING, that
makes better use of bus bandwidth for ‘unready’ Bulk OUT
endpoints.
At high speed, the host can ‘ping’ a Bulk OUT endpoint to
determine if it is ready to accept data, holding off the OUT
data transfer until it can actually be accepted. The host
sends a PING token, and the FX2LP responds with:
■An ACK to indicate that there is space in the OUT end-
point buffer
■A NAK to indicate ‘not ready, try later’.
The PING interrupts indicate that an FX2LP Bulk OUT end-
point returned a NAK in response to a PING.
Note PING only applies at high speed (480 Mbps).
Unlike the IBN bits, which are combined into a single IBN
interrupt for all endpoints, each Bulk OUT endpoint has a
separate PING interrupt (EP0PING, EP1PING, EP2PING,
…, EP8PING). Interrupt-enables for the individual interrupts
are in the NAKIE register; the interrupt-requests are in the
NAKIRQ register.
The interrupt service routine for the PING interrupts should
perform the following steps, in the order shown:
1. Clear the INT2 interrupt request.
2. Take the action for the requesting endpoint.
3. Clear the appropriate EPxPING bit for the endpoint.
8.6.3.2 EPIE, EPIRQ
These registers are used to manage interrupts from the EZ-
USB endpoints. In general, an interrupt request is asserted
whenever the following occurs:
■An IN endpoint buffer becomes available for the CPU to
load.
■An OUT endpoint has new data for the CPU to read.
For the small endpoints (EP0 and EP1IN/OUT), these condi-
tions are synonymous with the endpoint Busy bit making a
1-to-0 transition (busy to not-busy). As with all EZ-USB inter-
rupts, this one is enabled by writing a ‘1’ to its enable bit, and
the interrupt flag is cleared by writing a ‘1’ to it.
Note Do not attempt to clear an IRQ bit by reading the IRQ
register, OR’ing its contents with a bit mask (for example,
00010000), then writing the contents back to the register.
Since a ‘1’ clears an IRQ bit, this clears all the asserted IRQ
bits rather than just the desired one. Instead, simply write a
single ‘1’ (for example, 00010000) to the register.
8.6.3.3 USBERRIE, USBERRIRQ,
ERRCNTLIM, CLRERRCNT
These registers are used to monitor the ‘health’ of the USB
connection between the EZ-USB and the host.
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 95
Access to Endpoint Buffers
USBERRIE
This register contains the interrupt-enable bits for the ‘Iso-
chronous Endpoint Error’ interrupts and the ‘USB Error
Limit’ interrupt.
An ‘Isochronous Endpoint Error’ occurs when the FX2LP
detects a PID sequencing error for a high-bandwidth, high-
speed ISO endpoint.
USBERRIRQ
This register contains the interrupt flags for the ‘Isochronous
Endpoint Error’ interrupts and the ‘USB Error Limit’ interrupt.
ERRCNTLIM
EZ-USB firmware sets the USB error limit to any value from
1 to 15 by writing that value to the lower nibble of this regis-
ter; when that many USB errors (CRC errors, Invalid PIDs,
garbled packets, etc.) have occurred, the ‘USB Error Limit’
interrupt flag is set. At power-on-reset, the error limit
defaults to 4 (0100 binary).
The upper nibble of this register contains the current USB
error count.
CLRERRCNT
Writing any value to this register clears the error count in the
upper nibble of ERRCNTLIM. The lower nibble of
ERRCNTLIM is not affected.
8.6.3.4 TOGCTL
As described in the Introducing EZ-USB® chapter on
page 13 the host and device maintain a data toggle bit,
which is toggled between data packet transfers. There are
certain times when the firmware must reset an endpoint’s
data toggle bit to ‘0’:
■After a configuration changes (for example, after the
host issues a Set Configuration request).
■After an interface’s alternate setting changes (i.e., after
the host issues a Set Interface request).
■After the host sends a ‘Clear Feature - Endpoint Stall’
request to an endpoint.
For the first two, the firmware must clear the data toggle bits
for all endpoints contained in the affected interfaces. For the
third, only one endpoint’s data toggle bit is cleared.
The TOGCTL register contains bits to set or clear an end-
point data toggle bit, as well as to read the current state of a
toggle bit.
At this writing, there is no known reason for firmware to set
an endpoint toggle to ‘1’. Also, since the EZ-USB handles all
data toggle management, normally there is no reason to
know the state of a data toggle. These capabilities are
included in the TOGCTL register for completeness and
debug purposes.
A two-step process is employed to clear an endpoint data
toggle bit to ‘0’. First, writes the TOGCTL register with an
endpoint address (EP3:EP0) plus a direction bit (I/O). Then,
keeping the endpoint and direction bits the same, write a ‘1’
to the ‘R’ (reset) bit. For example, to clear the data toggle for
EP6 configured as an ‘IN’ endpoint, write the following val-
ues sequentially to TOGCTL:
■00010110
■00110110
8.7 The Setup Data Pointer
The USB host sends device requests using Control trans-
fers over endpoint 0. Some requests require the EZ-USB to
return data over EP0. During enumeration, for example, the
host issues Get Descriptor requests that ask for the device’s
capabilities and requirements. The returned data can span
many packets, so it must be partitioned into packet-sized
blocks, then the blocks must be sent at the appropriate
times (for example, when the EP0 buffer becomes ready).
The Setup Data Pointer automates this process of returning
IN data over EP0, simplifying the firmware.
Note For the Setup Data Pointer to work properly, EP0’s
MaxPacketSize must be set to 64, and the address of
SUDPTRH:L must be word-aligned (for example, the LSB of
SUDPTRL must be ‘0’).
TOGCTL Data Toggle Control E683
b7 b6 b5 b4 b3 b2 b1 b0
Q S R I/O EP3 EP2 EP1 EP0
RR/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
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Access to Endpoint Buffers
Table 8-7 lists the registers which configure the Setup Data
Pointer.
To send a block of data, the block’s word-aligned starting
address is loaded into SUDPTRH:L. The block length must
previously have been set; the method for accomplishing this
depends on the state of the SDPAUTO bit:
■SDPAUTO = 0 (Manual Mode): Used for general-pur-
pose block transfers. Firmware writes the block length to
EP0BCH:L.
■SDPAUTO = 1 (Auto Mode): Used for sending Device,
Configuration, String, Device Qualifier, and Other Speed
Configuration descriptors only. The block length is auto-
matically read from the ‘length’ field of the descriptor
itself; no explicit loading of EP0BCH:L is necessary.
Writing to SUDPTRL starts the transfer; the EZ-USB auto-
matically sends the entire block, packetizing as necessary.
For example, to answer a Get Descriptor - Device request,
firmware sets SDPAUTO = 1, then loads the address of the
device descriptor into SUDPTRH:L. The EZ-USB then auto-
matically loads the EP0 data buffer with the required number
of packets and transfers them to the host.
To command the EZ-USB to ACK the status (handshake)
packet, the firmware clears the HSNAK bit (by writing ‘1’ to
it) before starting the Setup Data Pointer transfer.
If the firmware needs to know when the transaction is com-
plete (for example, sent and acknowledged), it can enable
the EP0ACK interrupt before starting the Setup Data Pointer
transfer.
Note When SDPAUTO = 0, writing to EP0BCH:L only sets
the block length; it does not arm the transfer (the transfer is
armed by writing to SUDPTRL). Therefore, before perform-
ing an EP0 transfer which does not use the Setup Data
Pointer (i.e., one which is meant to be armed by writing to
EP0BCL), SDPAUTO must be set to ‘1’.
8.7.1 Transfer Length
When the host makes any EP0IN request, the EZ-USB
respects the following two length fields:
■the requested number of bytes (from the last two bytes
of the SETUP packet received from the host)
■the available number of bytes, supplied either as a
length field in the actual descriptor (SDPAUTO = 1) or in
EP0BCH:L (SDPAUTO = 0)
In accordance with the USB Specification, the EZ-USB
sends the smaller of these two length fields.
8.7.2 Accessible Memory Spaces
The Setup Data Pointer can access data in either of two
RAM spaces:
■On-chip Main RAM (16 KB at 0x0000-0x3FFF)
■On-chip Scratch RAM (512 bytes at 0xE000-0xE1FF)
Note The Setup Data Pointer cannot be used to access off-
chip memory at any address.
8.8 Autopointers
Endpoint data is available to the CPU in RAM buffers (see
Table 8-3 on page 89). In some cases, it is faster for the
firmware to access endpoint data as though it were in a
FIFO register. The EZ-USB provides two special data point-
ers, called ‘Autopointers’, that automatically increment after
each byte transfer. Using the Autopointers, firmware can
access contiguous blocks of on- or off-chip data memory as
a FIFO.
Each Autopointer is controlled by a 16-bit address register
(AUTOPTRnH:L), a data register (XAUTODATn), and a con-
trol bit (APTRnINC). An additional control bit, APTREN,
enables both Autopointers.
A read from (or write to) an Autopointer data register actually
accesses the address pointed to by the corresponding Auto-
pointer address register, which increments on every data-
register access. To read or write a contiguous block of mem-
ory (for example, an endpoint buffer) using an Autopointer,
load the Autopointer’s address register with the starting
address of the block, then repeatedly read or write the Auto-
pointer’s data register.
The AUTOPTRnH:L registers may be written or read at any
time to determine the current Autopointer address.
Most of the Autopointer registers are in SFR Space for quick
access; the data registers are available only in External Data
space.
The Autopointers are configured using three bits in the
AUTOPTRSETUP register: one bit (APTREN) enables both
Table 8-7. Registers Used To Control the Setup Data
Pointer
Address Register Name Function
0xE6B3 SUDPTRH High address
0xE6B4 SUDPTRL Low address
0xE6B5 SUDPTRCTL SDPAUTO bit
Table 8-8. Registers that control the Autopointers
Address Register Name Function
SFR 0xAF AUTOPTRSETUP Increment/freeze, off-chip access enable
SFR 0x9A AUTOPTR1H Address high
SFR 0x9B AUTOPTR1L Address low
0xE67B XAUTODAT1 Data
SFR 0x9D AUTOPTR2H Address high
SFR 0x9E AUTOPTR2L Address low
0xE67C XAUTODAT2 Data
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 97
Access to Endpoint Buffers
autopointers, and two bits (one for each Autopointer, called
APTR1INC and APTR2INC, respectively) control whether or
not the address increments for every Autodata access.
Enabling the Autopointers has one side effect: Any ‘code’
access (an instruction fetch, for instance) from addresses
0xE67B and 0xE67C returns the AUTODATA values, rather
than the code-memory values at these two addresses. This
introduces a two-byte ‘hole’ in the code memory.
Note There is no 2-byte hole in the data memory at
0xE67B:E67C; the hole only appears in the program mem-
ory.
Note The Autopointers must not be used to read or write
registers in the 0xE600 to 0xE6FF range; Autopointer
accesses within that range produce undefined results.
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EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 99
9. Slave FIFOs
9.1 Introduction
Although some EZ-USB-based devices may use the EZ-USB’s CPU to process USB data directly (See chapter “Access to
Endpoint Buffers” on page 87), most use the EZ-USB simply as a conduit between the USB and external data processing
logic (for example, an ASIC or DSP, or the IDE controller on a hard disk drive).
In devices with external data-processing logic, USB data flows between the host and that external logic — usually without any
participation by the EZ-USB’s CPU — through the EZ-USB’s internal ‘endpoint FIFOs’. To the external logic, these endpoint
FIFOs look like most others; they provide the usual timing signals, handshake lines (full, empty, programmable level), read
and write strobes, output enable, and others.
These FIFO signals must, of course, be controlled by a FIFO ‘master’. The EZ-USB’s General Programmable Interface
(GPIF) can act as an ‘internal’ master when the EZ-USB is connected to external logic which does not include a standard
FIFO interface (General Programmable Interface, on page 121 discusses the internal-master GPIF), or the FIFOs can be
controlled by an external master. While its FIFOs are controlled by an external master, the EZ-USB is said to be in ‘Slave
FIFO’ mode.
This chapter provides details on the interface — both hardware and software — between the EZ-USB’s slave FIFOs and an
‘external’ master.
9.2 Hardware
Figure 9-1 illustrates the four slave FIFOs. The figure shows the FIFOs operating in 16 bit mode, although they can also be
configured for 8-bit operation.
Figure 9-1. Slave FIFOs’ Role in the EZ-USB System
EP8
EP6
EP4
EP2
Slave FIFOs
CPU Device Pins
FD[15:0]
IFCLK
30/48MHz
5 - 48MHz
FLAGA
FLAGB
FLAGC
FLAGD / SLCS#
SLOE
SLRD
SLWR
FIFOADR[1:0]
PKTEND
PORT I /O
Slave FIFOs
WORDWIDE = 1
CPU
INPKTEND
EPxFIFOBUF
EPxBCH:L
EPx - EF, FF, PF
where: x =
2, 4, 6, or 8
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Slave FIFOs
Table 9-1 lists the registers associated with the slave FIFO
hardware. The registers are fully described in the
Registers chapter on page 211
9.2.1 Slave FIFO Pins
The EZ-USB comes out of reset with its I/O pins configured
in ‘Ports’ mode, not ‘Slave FIFO’ mode. To configure the
pins for Slave FIFO mode, the IFCFG[1:0] bits in the IFCON-
FIG register must be set to ‘11’ (see Table 13-10, “IFCFG
Selection of Port I/O Pin Functions,” on page 188 for
details). When IFCFG1:0 = 11, the Slave FIFO interface pins
are presented to the external master, as shown in
Figure 9-2.
Figure 9-2. EZ-USB Slave Mode Full Featured Interface
Pins
External logic accesses the FIFOs through an 8- or 16-bit
wide data bus, FD. The data bus is bidirectional, with its out-
put drivers controlled by the SLOE pin.
The FIFOADR[1:0] pins select which of the four FIFOs is
connected to the FD bus and is being controlled by the
external master.
In asynchronous mode (IFCONFIG.3 = 1), SLRD and SLWR
are read and write strobes; in synchronous mode
(IFCONFIG.3 = 0), SLRD and SLWR are enables for the
IFCLK clock pin.
Figure 9-3. Asynchronous vs. Synchronous Timing Models
Table 9-1. Registers Associated with Slave FIFO Hardware
Register Name
IFCONFIG EPxFIFOPFH/L
PINFLAGSAB PORTACFG
PINFLAGSCD INPKTEND
FIFORESET EPxFIFOIE
FIFOPINPOLAR EPxFIFOIRQ
EPxCFG EPxFIFOBCH:L
EPxFIFOCFG EPxFLAGS
EPxAUTOINLENH:L EPxFIFOBUF
EZ - USB
Slave
Mode
EXT.
Master
FLAGA
FLAGB
FLAGC
IFCLK
FLAGD / SLCS#
SLOE
SLRD
SLWR
PKTEND
FD[15:0]
FIFOADR[1:0]
Asynchronous
SLRD
SLWR
Synchronous
SLRD
SLWR
IFCLK
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Slave FIFOs
9.2.2 FIFO Data Bus
The FIFO Data (FD) bus, FD[x:0], can be either 8- or 16-bits
wide. The width is selected via each FIFO’s WORDWIDE
bit, (EPxFIFOCFG.0):
■WORDWIDE = 0: 8-bit mode. FD[7:0] replaces Port B.
See Figure 9-4.
■WORDWIDE = 1: 16-bit mode. FD[15:8] replaces Port D
and FD[7:0] replaces Port B. See Figure 9-5. FD[7:0] is
the LSB of the word, and FD[15:8] is the MSB of the
word.
On a hard reset, the FIFO data bus defaults to 16-bit mode
(WORDWIDE = 1) for all FIFOs.
In either mode, the FIFOADR[1:0] pins select which of the
four FIFOs is internally connected to the FD pins.
Note If all of the FIFOs are configured for 8-bit mode, Port D
remains available for use as general-purpose I/O. If any
FIFO is configured for 16-bit mode, Port D is unavailable for
use as general-purpose I/O regardless of which FIFO is cur-
rently selected via the FIFOADR[1:0] pins.
Note In 16-bit mode, the EZ-USB only transfers even-sized
packets of data across the FD bus. This should be consid-
ered when the EZ-USB interfaces to host software that
sends or receives odd sized packets.
Figure 9-4. 8-bit Mode Slave FIFOs, WORDWIDE = 0
Figure 9-5. 16-bit Mode Slave FIFOs, WORDWIDE = 1
30/48MHz
FLAGA
FIFOADR[1:0]
Slave FIFOsEZ-USB Registers Devi ce P ins
FLAGB
FLAGC
FLAGD/SLCS#
SLOE
SLRD
SLWR
PKTEND
FD[7:0]
EP4FIFOBUF
EP6FIFOBUF
EP8FIFOBUF
EP2FIFOBUF
EP8
EP6
EP4
EP2
IFCLK
5 - 48MHz
30/48MHz
FLAGA
FIFOADR[1:0]
Slave FIFOsEZ-USB Registers Device Pins
FLAGB
FLAGC
FLAGD/SLCS#
SLOE
SLRD
SLWR
PKTEND
FD[15:0]
EP4FIFOBUF
EP6FIFOBUF
EP8FIFOBUF
EP2FIFOBUF
EP8
EP6
EP4
EP2
IFCLK
5- 48MHz
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Slave FIFOs
9.2.3 Interface Clock
The slave FIFO interface can be clocked from either an
internal or an external source. The EZ-USB’s internal clock
source can be configured to run at either 30 or 48 MHz, and
it can optionally be output on the interface clock (IFCLK) pin.
If the EZ-USB is configured to use an external clock source,
the IFCLK pin can be driven at any frequency between 5
MHz and 48 MHz. On a hard reset, the EZ-USB defaults to
the internal source at 48 MHz, normal polarity, with the
IFCLK output disabled. See Figure 9-6.
IFCONFIG.7 selects between internal and external sources:
0 = external, 1 = internal. If an external IFCLK is chosen, it
must be free running at a minimum frequency of 5 MHz. In
addition, in order to provide synchronization for the internal
endpoint FIFO logic, the external IFCLK source must be
present before the firmware sets IFCONFIG.7 = 0.
IFCONFIG.6 selects between the 30- and 48-MHz internal
clock: 0 = 30 MHz, 1 = 48 MHz. This bit has no effect when
IFCONFIG.7 = 0.
IFCONFIG.5 is the output enable for the internal clock
source: 0 = disable, 1 = enable. This bit must not be set to ‘1’
when IFCONFIG.7 = 0.
IFCONFIG.4 inverts the polarity of the interface clock (either
internal or external): 0 = normal, 1 = inverted. IFCLK inver-
sion can make it easier to interface the EZ-USB with certain
external circuitry. When an internal IFCLK is used (IFCON-
FIG.7 = 1), IFCONFIG.4 only affects the IFCLK output polar-
ity if IFCONFIG.5 = 1. Figure 9-7 demonstrates the use of
IFCLK output inversion in order to ensure a long enough
setup time (ts) for reading the EZ-USB’s FIFO flags.
Note When IFCLK is configured as an input, the minimum
external frequency that can be applied to it is 5 MHz. This
clock must be applied prior to initialization of the GPIF; only
interruptions of it lower the overall frequency, causing viola-
tions of the minimum frequency requirement.
Figure 9-6. IFCLK Configuration
Figure 9-7. Satisfying Setup Timing by Inverting the IFCLK Output
0
1
30 MHz
48 MHz 0
1
0
1
1
0
Internal
IFCLK
Signal
IFCFG.7
IFCFG.4
IFCFG.6 IFCFG.4 IFCFG.5
IFCLK
Pin
EZ-USB
Asserts
Flag
t
s
Master
Samples
Flag
Internal IFCLK Signal
Inverted IFCLK Output
FIFO Flag
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Slave FIFOs
9.2.4 FIFO Flag Pins (FLAGA, FLAGB,
FLAGC, FLAGD)
Four pins — FLAGA, FLAGB, FLAGC, and FLAGD (see
Figure 9-7) — report the status of the EZ-USB’s FIFOs; in
addition to the usual ‘FIFO full’ and ‘FIFO empty’ signals,
there is also a signal which indicates that a FIFO has filled to
a user-programmable level. The external master typically
monitors the ‘empty’ flag (EF) of OUT endpoints and the full
(FF) flag of IN endpoints; the programmable level flag (PF)
is equally useful for either type of endpoint (it can, for
instance, give advance warning that an OUT endpoint is
almost empty or that an IN endpoint is almost full).
The FLAGA, FLAGB, and FLAGC pins can operate in either
of two modes: Indexed or Fixed, as selected via the PIN-
FLAGSAB and PINFLAGSCD registers. The FLAGD pin
operates in Fixed mode only. FLAGA-FLAGC pins can be
configured independently; some pins can be in Fixed mode
while others are in Indexed mode. See the PINFLAGSAB
and PINFLAGSCD register descriptions in the
Registers chapter on page 211 for complete details.
Flag pins configured for Indexed mode report the status of
the FIFO currently selected by the FIFOADR[1:0] pins.
When configured for Indexed mode, FLAGA reports the pro-
grammable level status, FLAGB reports the ‘full’ status, and
FLAGC reports the ‘empty’ status.
Flag pins configured for Fixed mode report one of the three
conditions for a specific FIFO, regardless of the state of the
FIFOADR[1:0] pins. The condition and FIFO are user-
selectable. For example, FLAGA could be configured to
report FIFO2’s ‘empty’ status, FLAGB to report FIFO4’s
‘empty’ status, FLAGC to report FIFO4’s ‘programmable
level’ status, and FLAGD to report FIFO6’s ‘full’ status.
The polarity of the ‘empty’ and ‘full’ flag pins defaults to
active-low but may be inverted via the FIFOPINPOLAR reg-
ister.
On a hard reset, the FIFO flags are configured for Indexed
operation.
Figure 9-8. FLAGx Pins
9.2.5 Control Pins (SLOE, SLRD,
SLWR, PKTEND, FIFOADR[1:0])
The Slave FIFO ‘control’ pins are SLOE (Slave Output
Enable), SLRD (Slave Read), SLWR (Slave Write),
PKTEND (Packet End), and FIFOADR[1:0] (FIFO Select).
‘Read’ and ‘Write’ are from the external master’s point of
view; the external master reads from OUT endpoints and
writes to IN endpoints. See Figure 9-9 on page 104.
Slave Output Enable and Slave Read — SLOE and
SLRD:
In synchronous mode (IFCONFIG.3 = 0), the FIFO pointer is
incremented on each rising edge of IFCLK while SLRD is
asserted. In asynchronous mode (IFCONFIG.3 = 1), the
FIFO pointer is incremented on each asserted-to-deas-
serted transition of SLRD.
The SLOE pin enables the FD outputs. In synchronous
mode, when SLOE is asserted, this causes the FD bus to be
driven with the data that the FIFO pointer is currently point-
ing to. The data is pre-fetched and is output only when
SLOE is asserted. In asynchronous mode, the data is not
pre-fetched, and SLRD must be asserted when SLOE is
asserted for the FD bus to be driven with the data that the
FIFO pointer is currently pointing to. SLOE has no other
function besides enabling the FD bus to be in a driven state.
By default, SLOE and SLRD are active-low; their polarities
can be changed via the FIFOPINPOLAR register.
FLAG
A
FIFOADR
[
1:0
]
Slave FIFOs
EZ-USB Registers
Device Pins
FLAGB
FLAGC
SLOE
SLRD
SLWR
PKTEND
FD
[
15:0
]
EP4FIFOBUF
EP6FIFOBUF
EP8FIFOBUF
EP2FIFOBUF
EP8
EP6
EP4
EP2
IFCLK
30/48MHz
5 - 48MHz
FLAGD/SLCS#
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Slave FIFOs
Slave Write — SLWR
In synchronous mode (IFCONFIG.3 = 0), data on the FD bus
is written to the FIFO (and the FIFO pointer is incremented)
on each rising edge of IFCLK while SLWR is asserted. In
asynchronous mode (IFCONFIG.3 = 1), data on the FD bus
is written to the FIFO (and the FIFO pointer is incremented)
on each asserted-to-deasserted transition of SLWR.
By default, SLWR is active-low; its polarity can be changed
via the FIFOPINPOLAR register.
FIFOADR[1:0]:
The FIFOADR[1:0] pins select which of the four FIFOs is
connected to the FD bus (and, if the FIFO flags are operat-
ing in Indexed mode, they select which FIFO’s flags are pre-
sented on the FLAGx pins):
PKTEND
An external master asserts the PKTEND pin to commit an IN
packet to USB regardless of the packet’s length. PKTEND is
usually used when the master wishes to send a ‘short’
packet (for example, a packet smaller than the size specified
in the EPxAUTOINLENH:L registers).
For example: Assume that EP4AUTOINLENH:L is set to the
default of 512 bytes. If AUTOIN = 1, the external master can
stream data to FIFO4 continuously, and (absent any bottle-
necks in the data path) the EZ-USB automatically commits a
packet to USB whenever the FIFO fills with 512 bytes. If the
master wants to send a stream of data whose length is not a
multiple of 512, the last packet is not be automatically com-
mitted to USB because it is smaller than 512 bytes. To com-
mit that last packet, the master can do one of two things: It
can pad the packet with dummy data in order to make it
exactly 512 bytes long, or it can write the short packet to the
FIFO, then pulse the PKTEND pin.
If the FIFO is configured to allow zero-length packets (EPx-
FIFOCFG.2 = 1), pulsing the PKTEND pin when a FIFO buf-
fer is available commits a zero-length packet.
By default, PKTEND is active-low; its polarity can be
changed via the FIFOPINPOLAR register.
Note The PKTEND pin must not be asserted unless a buf-
fer is available, even if only a zero-length packet is being
committed. The ‘full’ flag may be used to determine whether
a buffer is available.
Note In synchronous mode, there is no specific timing
requirement for PKTEND assertion with respect to SLWR
assertion. PKTEND can be asserted anytime. In asynchro-
nous mode, SLWR and PKTEND should not be pulsed at
the same time. PKTEND should be asserted after SLWR
has been deasserted for the minimum deasserted pulse
width. In both modes, FIFOADR[1:0] should be held con-
stant during the PKTEND pin assertion.
Figure 9-9. Slave FIFO Control Pins
9.2.6 Slave FIFO Chip Select
The Slave FIFO Chip Select (SLCS#) pin is an alternate
function of pin PA7; it is enabled via the PORTACFG.6 bit
(see section 13.4.1 Port A Alternate Functions on
page 185).
The SLCS# pin allows external logic to effectively remove
the EZ-USB from the FIFO Data bus, in order to, for exam-
ple, share that bus among multiple slave devices. For appli-
cations that do not need to share the FD bus among multiple
slave devices, the SLCS# pin can be tied to GND to perma-
nently select the EZ-USB slave FIFO interface. This configu-
ration is assumed for the interface and timing examples that
follow.
While the SLCS# pin is pulled high by external logic, the EZ-
USB floats its FD[x:0] pins and ignores the SLOE, SLRD,
SLWR, and PKTEND pins.
Table 9-2. FIFO Selection via FIFOADR[1:0]
FIFOADR[1:0] Selected FIFO
00 EP2
01 EP4
10 EP6
11 EP8
FLAGA
FIFOADR
[
1:0
]
Slave FIFOs
EZ-USB Registers
Device Pins
FLAGB
FLAGC
FLAGD/SLCS#
SLOE
SLRD
SLWR
PKTEND
FD
[
15:0
]
EP4FIFOBUF
EP6FIFOBUF
EP8FIFOBUF
EP2FIFOBUF
EP8
EP6
EP4
EP2
IFCLK
30/48MHz
5 - 48MHz
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 105
Slave FIFOs
9.2.7 Implementing Synchronous Slave
FIFO Writes
Figure 9-10. Interface Pins: Synchronous FIFO Writes
In order to implement synchronous FIFO writes, a typical
sequence of events for the external master is:
IDLE: When a write event occurs, transition to State 1.
STATE 1: Point to IN FIFO, assert FIFOADR[1:0] (setup
time must be met with respect to the rising edge of IFCLK),
transition to State 2.
STATE 2: If FIFO-Full flag is false (FIFO not full), transition
to State 3 else remain in State 2.
STATE 3: Drive data on the bus, assert SLWR (setup and
hold times must be met with respect to the rising edge of
IFCLK), deassert SLWR. Transition to State 4.
STATE 4: If more data to write, transition to State 2 else tran-
sition to IDLE.
Figure 9-11. State Machine: Synchronous FIFO Writes
Figures 9-12 to 9-14 show timing examples of an external
master performing synchronous FIFO writes to EP8. These
examples assume that EP8 is configured as IN, Bulk, 512
bytes buffer size, 2x buffered, WORDWIDE = 1, AUTOIN =
1, EP8AUTOINLENH:L = 512. With AUTOIN = 1, and
EP8AUTOINLENH:L = 512, this causes data packets to be
automatically committed to USB whenever the master fills
the FIFO with 512 bytes (or 256 words since WORDWIDE =
1).
In Figure 9-12, the external master selects EP8 by setting
FIFOADR[1:0] to ‘11’ and once it writes the first data value
over the FD bus, FLAGC - EMPTY exhibits a ‘not-empty’
condition.
Figure 9-12. Timing Example: Synchronous FIFO Writes, Waveform 1
IFCLK
FIFOADR[1:0]
FULL
EMPTY
PKTEND
SLWR
FD[15:0]
FLAGC
FLAGB
5-48MHz
EXT.
Master
EZ-USB
Slave
Mode
State 3
State 2
State 4
Done
Launch
Full
State 1
Master Selects EP8 EP8 Not Empty
N
PKTEND
FD[15:0]
SLWR
FLAGC - EMPTY
FLAGB - FULL
FIFOADR1
FIFOADR0
IFCLK
ZN+1
106 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Slave FIFOs
Figure 9-13. Timing Example: Synchronous FIFO Writes, Waveform 2
In Figure 9-13, once the external master writes the 512th
word into the EP8 FIFO, the second 512-byte packet is auto-
matically committed to USB. The first 512-byte packet was
automatically committed to USB when the external master
wrote the 256th word into the EP8 FIFO.
Figure 9-14 shows the fourth packet in the EP8 FIFO being
manually committed by pulsing PKTEND. There is no spe-
cific timing requirement for PKTEND assertion with respect
to SLWR assertion. Hence, PKTEND is asserted the same
time the 816th word is written into EP8. This causes the
short packet to be committed, which contains 48 words (or
96 bytes). The fourth packet would have been automatically
committed if the external master finished writing the 1024th
word.
Once the fourth packet has been committed, FLAGB - FULL
is asserted, indicating that no more FIFO buffers are avail-
able for the external master to write into. A buffer becomes
available once the host has read an entire packet.
Note FIFOADR[1:0] must be held constant during the
PKTEND assertion.
Figure 9-14. Timing Example: Synchronous FIFO Writes, Waveform 3, PKTEND Pin Illustrated
Core Auto
Commits Pkt
PKTEND
FD[15:0]
SLWR
FLAGC - EMPTY
FLAGB - FULL
FIFOADR1
FIFOADR0
IFCLK
510 511 512
AUTOIN=1
PKTEND
FD[15:0]
SLWR
FLAGC - EMPTY
FLAGB - FULL
FIFOADR1
FIFOADR0
IFCLK
815 816 N
Data Not
Written
Master Manually
Commits Short Pkt
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 107
Slave FIFOs
9.2.8 Implementing Synchronous Slave
FIFO Reads
Figure 9-15. Interface Pins: Synchronous FIFO Reads
In order to implement synchronous FIFO reads, a typical
sequence of events for the external master is:
IDLE. When a read event occurs, transition to State 1.
STATE 1: Point to OUT FIFO, assert FIFOADR[1:0] (setup
time must be met with respect to the rising edge of IFCLK),
transition to State 2.
STATE 2: Assert SLOE. If FIFO-Empty flag is false (FIFO
not empty), transition to State 3 else remain in State 2.
STATE 3: Sample data on the bus, assert SLRD (setup and
hold times must be met with respect to the rising edge of
IFCLK), deassert SLRD. Deassert SLOE, transition to State
4.
Note Since SLOE has no other function than to enable the
FD outputs, it is also correct to tie the SLRD and SLOE sig-
nals together.
STATE 4: If more data to read, transition to State 2 else tran-
sition to IDLE.
Figure 9-16. State Machine: Synchronous FIFO Reads
Figures 9-17 and 9-18 show timing examples of an external
master performing synchronous FIFO reads from EP2.
These examples assume that EP2 is configured as OUT,
Bulk, 512 bytes buffer size, 2x buffered, WORDWIDE = 0,
AUTOOUT = 1.
In Figure 9-17, the external master selects EP2 by setting
FIFOADR[1:0] to 00. It asserts SLOE to turn on the FD out-
put drivers, samples the first byte in the FIFO, and then
pulses SLRD to increment the FIFO pointer.
Figure 9-17. Timing: Synchronous FIFO Reads, Waveform 1
IFCLK
FIFOADR[1:0]
FULL
EMPTY
SLOE
SLRD
FD[15:0]
FLAGC
FLAGB
5-48MHz
EXT.
Master
EZ-USB
Slave
Mode
State 3
State 2
State 4
Done
Launch
Empty
State 1
N+1
NZ
Asserts SLOE then
Reads First Byte
in FIFO Increments to Next
Byte in FIFO
FD[7:0]
SLRD
SLOE
FLAGC - EMPTY
FLAGB - FULL
FIFOADR1
FIFOADR0
IFCLK
Selects EP2
108 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Slave FIFOs
Figure 9-18. Timing Example: Synchronous FIFO Reads, Waveform 2, EMPTY Flag Illustrated
Figure 9-18 shows FLAGC - EMPTY assert after the master
reads the 1024th (last) byte in the FIFO. This assumes that
the host has only sent 1024 bytes to EP2.
9.2.9 Implementing Asynchronous Slave
FIFO Writes
Figure 9-19. Interface Pins: Asynchronous FIFO Writes
In order to implement asynchronous FIFO writes, a typical
sequence of events for the external master is:
IDLE. When a write event occurs, transition to State 1.
STATE 1: Point to IN FIFO, assert FIFOADR[1:0] (setup time
must be met with respect to the asserting edge of SLWR),
transition to State 2.
STATE 2: If FIFO-Full flag is false (FIFO not full), transition
to State 3 else remain in State 2.
STATE 3: Drive data on the bus (setup time must be met
with respect to the deasserting edge of SLWR), write data to
the FIFO and increment the FIFO pointer by asserting then
deasserting SLWR, transition to State 4.
STATE 4: If more data to write, transition to State 2 else tran-
sition to IDLE.
Figure 9-20. State Machine: Asynchronous FIFO Writes
EP2 Empty
Z
1024
1023
Reads 1023 Byte
in FIFO Reads Last Byte
in FIFO
FD[7:0]
SLRD
SLOE
FLAGC - EMPTY
FLAGB - FULL
FIFOADR1
FIFOADR0
IFCLK
FIFOADR[1:0]
FULL
EMPTY
SLWR
PKTEND
FD[15:0]
FLAGC
FLAGB
EZ-USB
Slave
Mode
EXT.
Master
State 3
State 2
State 4
Done
Launch
Full
State 1
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 109
Slave FIFOs
Figure 9-21. Timing: Asynchronous FIFO Writes
Figure 9-21 shows a timing example of asynchronous FIFO
writes to EP8. The external master selects EP8 by setting
FIFOADR[1:0] to 11. Once it writes the first data value over
the FD bus, FLAGC - EMPTY exhibits a ‘not empty’ condi-
tion.
9.2.10 Implementing Asynchronous Slave
FIFO Reads
Figure 9-22. Interface Pins: Asynchronous FIFO Reads
In order to implement asynchronous FIFO reads, a typical
sequence of events for the external master is:
IDLE: When a read event occurs, transition to State 1.
STATE 1: Point to OUT FIFO, assert FIFOADR[1:0] (setup
time must be met with respect to the asserting edge of
SLRD), transition to State 2.
STATE 2: If Empty flag is false (FIFO not empty), transition
to State 3 else remain in State 2.
STATE 3: Assert SLOE, assert SLRD, sample data on the
bus, deassert SLRD (increment FIFO pointer), deassert
SLOE, transition to State 4.
Note Since SLOE has no other function than to enable the
FD outputs, it is also correct to tie the SLRD and SLOE sig-
nals together.
STATE 4: If more data to read, transition to State 2 else tran-
sition to IDLE.
Figure 9-23. State Machine: Asynchronous FIFO Reads.
N+1N
Z
PKTEND
FD[15:0]
SLWR
FLAGC - EMPTY
FLAGB - FULL
FIFOADR1
FIFOADR0
IFCLK
FIFOADR[1:0]
FULL
EMPTY
SLOE
SLRD
FD[15:0]
FLAGC
FLAGB
EZ-USB
Slave
Mode
EXT.
Master
State 3
State 2
State 4
Done
Launch
Empty
State 1
110 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Slave FIFOs
Figure 9-24. Timing: Asynchronous FIFO Reads
Figure 9-24 shows a timing example of asynchronous FIFO
reads from EP2. The external master selects EP2 by setting
FIFOADR[1:0] to 00, and strobes SLOE/SLRD to sample
data on the FD bus.
9.3 Firmware
This section describes the interface between EZ-USB firm-
ware and the FIFOs. More information is available in the
Access to Endpoint Buffers chapter on page 87.
9.3.1 Firmware FIFO Access
EZ-USB firmware can access the slave FIFOs using four
registers in XDATA memory: EP2FIFOBUF, EP4FIFOBUF,
EP6FIFOBUF, and EP8FIFOBUF. These registers can be
read and written directly (using the MOVX instruction), or
they can serve as sources and destinations for the dual
Autopointer mechanism built into the EZ-USB (see section
Autopointers on page 96).
Additionally, there are a number of FIFO control and status
registers: Byte Count registers indicate the number of bytes
in each FIFO; flag bits indicate FIFO fullness, mode bits con-
trol the various FIFO modes, etc.
This chapter focuses on the registers and bits which are
specific to slave-FIFO operation; for a more detailed
description of all the FIFO registers, see the chapters
Access to Endpoint Buffers, on page 87 and Registers, on
page 211
Note Setting the REVCTL bits enables features that are not
required by every application. So although not necessary,
for proper operation as described in this chapter, EZ-USB
firmware must set the DYN_OUT and ENH_PKT bits
(REVCTL.0 and REVCTL.1) to ‘1’.
Figure 9-25. EPxFIFOBUF Registers
N
Z
IFCLK
FIFOADR0
FIFOADR1
FLAGB - FULL
FLAGC - EMPTY
SLOE
SLRD
FD[15:0] Z
Table 9-3. Registers Associated with Slave FIFO Firmware
Register Name
EPxCFG INPKTEND/OUTPKTEND
EPxFIFOCFG EPxFIFOIE
EPxAUTOINLENH/L EPxFIFOIRQ
EPxFIFOPFH:L INT2IVEC
EP2468STAT INT4IVEC
EP24FIFOFLGS INTSETUP
EP68FIFOFLGS IE
EPxCS IP
EPxFIFOFLGS INT2CLR
EPxBCH:L INT4CLR
EPxFIFOBCH:L EIE
EPxFIFOBUF EXIF
REVCTL (bits 0 and 1 must be initialized to ‘1’ for operation as described in
this chapter)
FLAGA
FIFOADR
[
1:0
]
Slave FIFOs
EZ-USB Registers
Device Pins
FLAGB
FLAGC
FLAGD/SLCS#
SLOE
SLRD
SLWR
PKTEND
FD
[
15:0
]
EP4FIFOBUF
EP6FIFOBUF
EP8FIFOBUF
EP2FIFOBUF
EP8
EP6
EP4
EP2
IFCLK
30/48MHz
5 - 48MHz
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 111
Slave FIFOs
9.3.2 EPx Memories
The slave FIFOs connect external logic to the EZ-USB’s four
endpoint memories (EP2, EP4, EP6, and EP8). These end-
point memories have the following programmable features:
1. Type can be either BULK, INTERRUPT, or ISOCHRO-
NOUS.
2. Direction can be either IN or OUT.
3. For EP2 and EP6, size can be either 512 or 1024 bytes.
EP4 and EP8 are fixed at 512 bytes.
4. Buffering can be 2x, 3x, or 4x for EP2 and EP6. EP4 and
EP8 are fixed at 2x.
5. EZ-USB can automatically commit endpoint data to and
from the slave FIFO interface (AUTOIN = 1, AUTOOUT
= 1), or manually commit endpoint data to and from the
slave FIFO interface (AUTOIN = 0, AUTOOUT = 0).
On a hard reset, these endpoint memories are configured as
follows:
1. EP2 - Bulk OUT, 512 bytes/packet, 2x buffered.
2. EP4 - Bulk OUT, 512 bytes/packet, 2x buffered.
3. EP6 - Bulk IN, 512 bytes/packet, 2x buffered.
4. EP8 - Bulk IN, 512 bytes/packet, 2x buffered.
Note In full speed mode, buffer sizes scale down to 64
bytes for the non-isochronous types.
Figure 9-26. EPx Memories
9.3.3 Slave FIFO Programmable Level
Flag
Each FIFO’s Programmable level Flag (PF) asserts when
the FIFO reaches a user-defined fullness threshold.
See the discussion of the EPxFIFOPFH:L registers in the
Registers chapter on page 211 for full details.
9.3.4 Auto-In / Auto-Out Modes
The EZ-USB FIFOs can be configured to commit packets to/
from USB automatically. For IN endpoints, Auto-In Mode
allows the external logic to stream data into a FIFO continu-
ously, with no need for it or the EZ-USB firmware to pack-
etize the data or explicitly signal the EZ-USB to send it to the
host. For OUT endpoints, Auto-Out Mode allows the host to
continuously fill a FIFO, with no need for the external logic
or EZ-USB firmware to handshake each incoming packet,
arm the endpoint buffers, and so on. See Figure 9-27.
Figure 9-27. When AUTOOUT=1, OUT Packets are
Automatically Committed
To configure an IN endpoint FIFO for Auto Mode, set the
AUTOIN bit in the appropriate EPxFIFOCFG register to ‘1’.
To configure an OUT endpoint FIFO for Auto Mode, set the
AUTOOUT bit in the appropriate EPxFIFOCFG register to
‘1’. See Figure 9-28 and Figure 9-29 on page 112.
On a hard reset, all FIFOs default to Manual Mode (i.e.,
AUTOIN = 0 and AUTOOUT = 0).
FLAGA
FIFOADR
[
1:0
]
Slave FIFOs
EZ-USB Registers
Device Pins
FLAGB
FLAGC
FLAGD/SLCS#
SLOE
SLRD
SLWR
PKTEND
FD
[
15:0
]
EP4FIFOBUF
EP6FIFOBUF
EP8FIFOBUF
EP2FIFOBUF
EP8
EP6
EP4
EP2
IFCLK
30/48MHz
5 - 48MHz
AUTOOUT=1
Data Path
CPU
USB
Host Slave Master
112 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Slave FIFOs
Figure 9-28. TD_Init Example: Configuring AUTOOUT = 1
Figure 9-29. TD_Init Example: Configuring AUTOIN = 1
9.3.5 CPU Access to OUT Packets, AUTOOUT = 1
The EZ-USB’s CPU is not in the host-to-master data path when AUTOOUT = 1. To achieve the maximum bandwidth, the host
and master are directly connected, bypassing the CPU. Figure 9-30 shows that, in Auto-Out mode, data from the host is auto-
matically committed to the FIFOs with no firmware intervention.
Figure 9-30. TD_Poll Example: No Code Necessary for OUT Packets When AUTOOUT=1
Note If AUTOOUT = 1, an OUT FIFO buffer is automatically committed, and could contain 0-1024 bytes, depending on the
size of the OUT packet transmitted by the host. The buffer size should be set appropriately (512 or 1024) to accommodate the
USB data payload size.
TD_Init():
… … … … …
REVCTL = 0x03; // REVCTL.0 and REVCTL.1 to set to 1
SYNCDELAY;
EP2CFG = 0xA2; // EP2 is DIR=OUT, TYPE=BULK, SIZE=512, BUF=2x
SYNCDELAY;
FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;
FIFORESET = 0x82;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
OUTPKTEND = 0x82; // Arm both EP2 buffers to “prime the pump”
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
EP2FIFOCFG = 0x10; // EP2 is AUTOOUT=1, AUTOIN=0, ZEROLEN=0, WORDWIDE=0
… … … … …
TD_Init():
… … … … …
REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1
SYNCDELAY;
EP8CFG = 0xE0; // EP8 is DIR=IN, TYPE=BULK
SYNCDELAY;
FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;
FIFORESET = 0x88;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP8FIFOCFG = 0x0C; // EP8 is AUTOOUT=0, AUTOIN=1, ZEROLEN=1, WORDWIDE=0
SYNCDELAY;
EP8AUTOINLENH = 0x02; // Auto-commit 512-byte packets
SYNCDELAY;
EP8AUTOINLENL = 0x00;
… … … … …
TD_Poll():
… … … … …
// no code necessary to xfr data from host to master!
// AUTOOUT=1 auto-commits packets
… … … … …
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 113
Slave FIFOs
9.3.6 CPU Access to OUT Packets, AUTOOUT = 0
In some systems, it may be desirable to allow the EZ-USB’s CPU to participate in the transfer of data between the host and
the slave FIFOs. To configure a FIFO for this ‘Manual-Out’ mode, the AUTOOUT bit in the appropriate EPxFIFOCFG register
must be cleared to ‘0’ (see Figure 9-31).
Figure 9-31. TD_Init Example, Configuring AUTOOUT=0
As Illustrated in Figure 9-32, EZ-USB firmware can do one
of three things when the EZ-USB is in Manual-Out mode
and a packet is received from the host:
1. It can ‘commit’ (pass to the FIFOs) the packet by writing
OUTPKTEND with SKIP=0 (Figure 9-33 on page 113).
2. It can ‘skip’ (discard) the packet by writing OUTPKTEND
with SKIP=1 (Figure 9-34 on page 114).
3. It can ‘edit’ the packet (or source an entire OUT packet)
by writing to the FIFO buffer directly, then write the
length of the packet to EPxBCH:L. The write to EPxBCL
commits the edited packet, so EPxBCL should be written
after writing EPxBCH (Figure 9-35 on page 114).
In all cases, the OUT buffer automatically re-arms so it can
receive the next packet, once the external master has fin-
ished reading all data in the OUT buffer.
See section 8.6.2.4 EP2BCH:L, EP4BCH:L, EP6BCH:L,
EP8BCH:L on page 93 for a detailed description of the SKIP
bit.
Figure 9-32. Skip, Commit, or Source (AUTOOUT=0)
Figure 9-33. TD_Poll Example, AUTOOUT=0, Commit Packet
TD_Init():
… … … … …
REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1
SYNCDELAY;
EP2CFG = 0xA2; // EP2 is DIR=OUT, TYPE=BULK, SIZE=512, BUF=2x
SYNCDELAY;
FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;
FIFORESET = 0x82;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP2FIFOCFG = 0x00; // EP2 is AUTOOUT=0, AUTOIN=0, ZEROLEN=0, WORDWIDE=0
SYNCDELAY;
OUTPKTEND = 0x82; // Arm both EP2 buffers to “prime the pump”
SYNCDELAY;
OUTPKTEND = 0x82;
… … … … …
CPU
USB Slave Master
skip = 0
skip = 1
Data
Host
AUTOOUT = 0
EPxBCH:L
TD_Poll():
… … … … …
if( !( EP2468STAT & 0x01 ) )
{ // EP2EF=0 when FIFO NOT empty, host sent packet
OUTPKTEND = 0x02; // SKIP=0, pass buffer on to master
}
… … … … …
114 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Slave FIFOs
Figure 9-34. sbTD_Poll Example, AUTOOUT=0, Skip Packet
Figure 9-35. TD_Poll Example, AUTOOUT=0, Source
Note If an uncommitted packet is in an OUT endpoint buffer when the EZ-USB is reset, that packet is not automatically com-
mitted to the master. To ensure that no uncommitted packets are in the endpoint buffers after a reset, the EZ-USB firmware’s
‘endpoint initialization’ routine should skip 2, 3, or 4 packets (depending on the buffering depth selected for the FIFO) by writ-
ing OUTPKTEND with SKIP=1. See Figure 9-36.
Figure 9-36. TD_Init Example, OUT Endpoint Initialization
TD_Poll():
… … … … …
if( !( EP2468STAT & 0x01 ) )
{ // EP2EF=0 when FIFO NOT empty, host sent packet
OUTPKTEND = 0x82; // SKIP=1, do NOT pass buffer on to master
}
… … … … …
TD_Poll():
… … … … …
if( EP24FIFOFLGS & 0x02 )
{
SYNCDELAY; //
FIFORESET = 0x80; // nak all OUT pkts. from host
SYNCDELAY; //
FIFORESET = 0x82; // advance all EP2 buffers to cpu domain
SYNCDELAY; //
EP2FIFOBUF[0] = 0xAA; // create newly sourced pkt. data
SYNCDELAY; //
EP2BCH = 0x00;
SYNCDELAY; //
EP2BCL = 0x01; // commit newly sourced pkt. to interface fifo
// beware of "left over" uncommitted buffers
SYNCDELAY; //
OUTPKTEND = 0x82; // skip uncommitted pkt. (second pkt.)
// note: core does not allow pkts. to get out of sequence
SYNCDELAY; //
FIFORESET = 0x00; // release "nak all"
}
… … … … …
TD_Init():
… … … … …
REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1
SYNCDELAY;
EP2CFG = 0xA2; // EP2 is DIR=OUT, TYPE=BULK, SIZE=512, BUF=2x
SYNCDELAY;
EP2FIFOCFG = 0x00; // EP2 is AUTOOUT=0, AUTOIN=0, ZEROLEN=0, WORDWIDE=0
// OUT endpoints do NOT come up armed
SYNCDELAY;
OUTPKTEND = 0x82; // arm first buffer by writing OUTPKTEND w/skip=1
SYNCDELAY;
OUTPKTEND = 0x82; // arm second buffer by writing OUTPKTEND w/skip=1
… … … … …
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 115
Slave FIFOs
9.3.7 CPU Access to IN Packets, AUTOIN = 1
Auto-In mode is similar to Auto-Out mode: When an IN FIFO is configured for Auto-In mode (by setting its AUTOIN bit to ‘1’),
data from the master is automatically packetized and committed to USB without any CPU intervention (see Figure 9-37).
Figure 9-37. TD_Poll Example, AUTOIN = 1
Auto-In mode differs in one important way from Auto-Out
mode: In Auto-Out mode, data (excluding data in short pack-
ets) is always auto-committed in 512- or 1024-byte packets;
in Auto-In mode, the auto-commit packet size may be set to
any non-zero value (with the single restriction, of course,
that the packet size must be less than or equal to the size of
the endpoint buffer). Each FIFO’s Auto-In packet size is
stored in its EPxAUTOINLENH:L register pair.
To source an IN packet, EZ-USB firmware can temporarily
halt the flow of data from the external master (via a signal on
a general-purpose I/O pin, typically), wait for an endpoint
buffer to become available, create a new packet by writing
directly to that buffer, then commit the packet to USB and
release the external master. In this way, the firmware can
insert its own packets in the data stream. See Figure 9-38,
which illustrates data flowing directly between the master
and the host, and Figure 9-39, which shows the firmware
sourcing an IN packet. A firmware example appears in
Figure 9-40 on page 116.
Figure 9-38. Master Writes Directly to Host, AUTOIN = 1
Figure 9-39. Firmware Intervention, AUTOIN = 0 or 1
TD_Poll():
… … … … …
// no code necessary to xfr data from master to host!
// AUTOIN=1 and EP8AUTOINLEN=512 auto commits packets
// in 512 byte chunks.
… … … … …
Data Path
CPU
USB
Host Slave Master
AUTOIN=1
BusyI/O
CPU
USB
Host Slave Master
AUTOIN=0 or
AUTOIN=1
BusyI/O
Data Path
116 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Slave FIFOs
Figure 9-40. TD_Poll Example: Sourcing an IN Packet
9.3.8 Access to IN Packets, AUTOIN=0
In some systems, it may be desirable to allow the EZ-USB’s
CPU to participate in every data-transfer between the exter-
nal master and the host. To configure a FIFO for this ‘Man-
ual-In’ mode, the AUTOIN bit in the appropriate
EPxFIFOCFG register must be cleared to ‘0’.
In Manual-In mode, EZ-USB firmware can commit, skip, or
edit packets sent by the external master, and it may also
source packets directly. To commit a packet, firmware writes
the endpoint number (with SKIP=0) to the INPKTEND regis-
ter. To skip a packet, firmware writes the endpoint number
with SKIP=1 to the INPKTEND register. To edit or source a
packet, firmware writes to the FIFO buffer, then writes the
packet commit length to EPxBCH and EPxBCL (in that
order).
Figure 9-41. TD_Poll, AUTOIN=0, Committing a Packet via INPKTEND
TD_Poll():
… … … … …
if( source_pkt_event )
{ // 100-msec background timer fired
if( holdoff_master( ) )
{ // signaled “busy” to master successful
while( !( EP68FIFOFLGS & 0x20 ) )
{ // EP8EF=0, when buffer not empty
; // wait ‘til host takes entire FIFO data
}
FIFORESET = 0x80; // initiate the “source packet” sequence
SYNCDELAY;
FIFORESET = 0x88;
SYNCDELAY;
FIFORESET = 0x00;
EP8FIFOBUF[ 0 ] = 0x02; // <STX>, packet start of text msg
EP8FIFOBUF[ 1 ] = 0x06; // <ACK>
EP8FIFOBUF[ 2 ] = 0x07; // <HEARTBEAT>
EP8FIFOBUF[ 3 ] = 0x03; // <ETX>, packet end of text msg
SYNCDELAY;
EP8BCH = 0x00;
SYNCDELAY;
EP8BCL = 0x04; // pass newly-sourced buffer on to host
}
else
{
history_record( EP8, BAD_MASTER );
}
}
… … … … …
TD_Poll():
… … … … …
if( master_finished_longxfr( ) )
{ // master currently points to EP8, pins FIFOADR[1:0]=11
if( !( EP68FIFOFLGS & 0x10 ) )
{ // EP8FF=0 when buffer available
INPKTEND = 0x08; // firmware commits EP8 packet
// by writing 8 to INPKTEND
release_master( EP8 );
}
}
… … … … …
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 117
Slave FIFOs
Figure 9-42. TD_Poll, AUTOIN=0, Skipping a Packet via INPKTEND
Figure 9-43. TD_Poll, AUTOIN=0, Editing a Packet via EPxBCH:L
9.3.9 Auto In/Auto Out Initialization
Enabling Auto In transfers between slave FIFO
and endpoint
Typically, a FIFO is configured for Auto-In mode as follows:
1. Configure bits IFCONFIG[7:4] to define the behavior of
the interface clock.
2. Set bits IFCFG1:0=11.
3. Set REVCTL.0 and REVCTL.1 to ‘1’.
4. Configure EPxCFG.
5. Reset the FIFOs.
6. Set bit EPxFIFOCFG.3=1.
7. Set the size through the EPxAUTOINLENH:L registers.
Enabling Auto Out transfers between endpoint
and slave FIFO
Typically, a FIFO is configured for Auto-Out mode as fol-
lows:
1. Configure bits IFCONFIG[7:4] to define the behavior of
the interface clock.
2. Set bits IFCFG1:0=11.
3. Set REVCTL.0 and REVCTL.1 to ‘1’.
4. Configure EPxCFG.
5. Reset the FIFOs.
6. Arm OUT buffers by writing to OUTPKTEND N times
with skip = 1, where N is buffering depth.
7. Set bit EPxFIFOCFG.4=1.
TD_Poll():
… … … … …
if( master_finished_longxfr( ) )
{ // master currently points to EP8, pins FIFOADR[1:0]=11
if( !( EP68FIFOFLGS & 0x10 ) )
{ // EP8FF=0 when buffer available
INPKTEND = 0x88; // firmware skips EP8 packet
// by writing 0x88 to INPKTEND
release_master( EP8 );
}
}
… … … … …
TD_Poll():
… … … … …
if( master_finished_xfr( ) )
{ // modify the data
EP8FIFOBUF[ 0 ] = 0x02; // <STX>, packet start of text msg
EP8FIFOBUF[ 7 ] = 0x03; // <ETX>, packet end of text msg
SYNCDELAY;
EP8BCH = 0x00;
SYNCDELAY;
EP8BCL = 0x08; // pass buffer on to host, packet size is 8
}
… … … … …
118 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Slave FIFOs
9.3.10 Auto Mode: Synchronous FIFO IN Data Transfers
Figure 9-44. Code Example, Synchronous Slave FIFO IN Data Transfer
TD_Init():
IFCONFIG = 0x03; // use IFCLK pin driven by external logic (5MHz to 48MHz)
// use slave FIFO interface pins driven sync by external master
SYNCDELAY;
REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1
SYNCDELAY;
EP8CFG = 0xE0; // sets EP8 valid for IN's
// and defines the endpoint for 512 byte packets, 2x buffered
SYNCDELAY;
FIFORESET = 0x80; // reset all FIFOs
SYNCDELAY;
FIFORESET = 0x82;
SYNCDELAY;
FIFORESET = 0x84;
SYNCDELAY;
FIFORESET = 0x86;
SYNCDELAY;
FIFORESET = 0x88;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY; // this defines the external interface to be the following:
EP8FIFOCFG = 0x0C; // this lets the EZ-USB auto commit IN packets, gives the
// ability to send zero length packets,
// and sets the slave FIFO data interface to 8-bits
PINFLAGSAB = 0x00; // defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0]
SYNCDELAY; // FLAGB as full flag, as pointed to by FIFOADR[1:0]
PINFLAGSCD = 0x00; // FLAGC as empty flag, as pointed to by FIFOADR[1:0]
// won't generally need FLAGD
PORTACFG = 0x00; // used PA7/FLAGD as a port pin, not as a FIFO flag
SYNCDELAY;
FIFOPINPOLAR = 0x00; // set all slave FIFO interface pins as active low
SYNCDELAY;
EP8AUTOINLENH = 0x02; // EZ-USB automatically commits data in 512-byte chunks
SYNCDELAY;
EP8AUTOINLENL = 0x00;
SYNCDELAY;
EP8FIFOPFH = 0x80; // you can define the programmable flag (FLAGA)
SYNCDELAY; // to be active at the level you wish
EP8FIFOPFL = 0x00;
TD_Poll():
// nothing! The EZ-USB is doing all the work of transferring packets
// from the external master sync interface to the endpoint buffer...
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 119
Slave FIFOs
9.3.11 Auto Mode Example: Asynchronous FIFO IN Data Transfers
The initialization code is exactly the same as for the synchronous-transfer example in Auto Mode: Synchronous FIFO IN Data
Transfers on page 118, but with IFCLK configured for internal use at a rate of 48 MHz and the ASYNC bit set to ‘1’.
Figure 9-45 shows the one-line modification that is needed.
Figure 9-45. TD_Init Example, Asynchronous Slave FIFO IN Data Transfers
Code to perform the transfers is, as before, unnecessary; as Figure 9-46 illustrates.
Figure 9-46. TD_Poll Example, Asynchronous Slave FIFO IN Data Transfers
9.3.12 Skipping Out Packets while in
AUTOOUT Mode
If flushing the packets in the buffers is required, It is neces-
sary to switch from auto mode to manual mode and reset
the FIFO. In auto out mode, if the firmware needs to flush
the packets received from host that are not read by the
external master/slave, the firmware can implement this
sequence:
1. Set the NAKALL bit
2. Switch to manual mode
3. Reset the FIFOs
4. Use OUTPKTEND 'n' times to skip uncommitted packets
(FIFO is 'n' buffered)
5. Switch to auto mode
6. Release the NAKALL bit
Note Resetting the FIFO while it is configured as AUTOOUT
does not clear the buffer or set the EMPTY bit in EPxCS.
This is why OUTPKTEND is used 'n' times for 'n' buffered
FIFO.
Figure 9-47. TD_Poll Example, Skipping Out Packets in AUTOOUT Mode
TD_Init( ): // slight modification from our synchronous firmware example
IFCONFIG = 0xCB;
// this defines the external interface as follows:
// use internal IFCLK (48MHz)
// use slave FIFO interface pins asynchronously to external master
TD_Poll( ):
// nothing! The EZ-USB is doing all the work of transferring packets
// from the external master async interface to the endpoint buffer…
TD_Poll ( ) :
… … …
if (FIFO_RESET)
{
//This is an example code segment which resets the EP2 FIFO
//where EP2 has been configured as AUTOOUT
//Note: Settings of other bits of EPxFIFOCFG are ignored here
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY;
EP2FIFOCFG = 0x00; //switching to manual mode
SYNCDELAY;
FIFORESET = 0x02; // Reset FIFO 2
SYNCDELAY;
OUTPKTEND = 0X82; //OUTPKTEND done twice as EP2 is double buffered by default
SYNCDELAY;
OUTPKTEND = 0X82;
SYNCDELAY;
EP2FIFOCFG = 0x10; //switching to auto mode
SYNCDELAY;
FIFORESET = 0x00; //Release NAKALL
SYNCDELAY;
}
… … …
120 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Slave FIFOs
9.3.13 Aborting Packets in FIFO while in
AUTOIN Mode
Resetting the FIFO, after taking it out of the AUTOIN mode,
empties the FIFO and sets the EMPTY bit in EPxCS. Any
packets in the buffers are skipped or invalid. Thus the
sequence is:
1. Set the NAKALL bit
2. Switch to manual mode
3. Reset the FIFOs
4. Switch to auto mode
5. Release the NAKALL bit
Figure 9-48. TD_Poll Example, Aborting Packets in FIFO while in AUTOIN Mode
9.4 Switching Between Manual
Out and Auto Out
Because OUT endpoints are not automatically armed when
the EZ-USB enters Auto-Out mode, the firmware can safely
switch the EZ-USB between Manual-Out and Auto-Out
modes without any need to flush or reset the FIFOs.
Note Switching between Manual-Out mode to Auto-Out
mode is not required for every application. Most applications
remain in either mode for each endpoint.
TD_Poll ( ) :
… … …
if (FIFO_RESET)
{
//This is an example code segment which resets the EP6 FIFO
//where EP6 has been configured as AUTOIN
//Note: Settings of other bits of EPxFIFOCFG are ignored here
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY;
EP6FIFOCFG = 0x00; //switching to manual mode
SYNCDELAY;
FIFORESET = 0x06; // Reset FIFO 6
SYNCDELAY;
EP6FIFOCFG = 0x0C; //switching to auto mode
SYNCDELAY;
FIFORESET = 0x00; //Release NAKALL
SYNCDELAY;
}
… … …
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 121
10. General Programmable Interface
10.1 Introduction
The General Programmable Interface (GPIF) is an internal master to the EZ-USB’s endpoint FIFOs. It replaces the external
‘glue’ logic which might otherwise be required to build an interface between the EZ-USB and the outside world.
At the GPIF’s core is a programmable state machine which generates up to six ‘control’ and nine ‘address’ outputs, and
accepts six external and two internal ‘ready’ inputs. Four user defined Waveform Descriptors control the state machine; gen-
erally (but not necessarily), one is written for FIFO reads, one for FIFO writes, one for single-byte/word reads, and one for sin-
gle-byte/word writes.
Note Read and Write are from the EZ-USB’s point of view. ‘Read’ waveforms transfer data from the outside world to the EZ-
USB; ‘Write’ waveforms transfer data from the EZ-USB to the outside world.
EZ-USB firmware can assign the FIFO read and FIFO write waveforms to any of the four FIFOs, and the GPIF generates the
proper strobes and handshake signals to the outside-world interface as data is transferred into or out of that FIFO.
As with external mastering (see Slave FIFOs, on page 99), the data bus between the FIFOs and the outside world can be
either 8 or 16 bits wide.
The GPIF is not limited to simple handshaking interfaces between the EZ-USB and external ASICs or microprocessors; it is
powerful enough to directly implement such protocols as ATAPI (PIO and UDMA), IEEE 1284 (EPP Parallel Port), Utopia, and
others. An EZ-USB can, for instance, function as a single-chip interface between USB and an IDE hard disk drive or Com-
pactFlash™ memory card.
This chapter provides an overview of GPIF, discusses external connections, and explains the operation of the GPIF engine.
Figure 10-1 on page 122 presents a block diagram illustrating GPIF’s place in the EZ-USB system.
Note GPIF waveforms are created with the Cypress GPIF Designer utility, a Windows®-based application which is distributed
with the Cypress EZ-USB Development Kit. Although this chapter describes the structure of the Waveform Descriptors in
some detail, knowledge of that structure is usually not necessary. The GPIF Designer simply hides the complexity of the
Waveform Descriptors; it does not compromise the programmer’s control over the GPIF in any way.
122 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Figure 10-1. GPIF’s Place in the EZ-USB System
Figure 10-2 on page 123 shows an example of a simple
GPIF transaction. For this transaction, the GPIF generates
an address (GPIFADR[8:0]), drives the FIFO data bus
(FD[15:0]), then waits for an externally-supplied handshake
signal (RDY0) to go low, after which it pulls its CTL0 output
low. When the RDY0 signal returns high, the GPIF brings its
CTL0 output high, then floats the data bus.
EPxEF
FIFOADR[1:0]
Slave FIFOs
8051 Device Pins
EPxFF
EPxPF
SLOE
SLRD
SLWR
INPKTEND
IFCLK
FD[15:0]
EP4FIFOBUF
EP6FIFOBUF
EP8FIFOBUF
EP2FIFOBUF
EP8
EP6
EP4
EP2
GPIF
GPIF
8051
CTL[5:0]
RDY[5:0]
GPIFADR[8:0]
GPIFWF
8051 INTRDY
30/48MHz
CLK
5 - 48MHz
XDATA
Waveform Descriptors
WF3
WF2
WF1
WF0
GPIF DONE
XGPIFSGLDATH/L
GPIFTRIG
XGPIFSGLDATLX
GSTATE[2:0]
WORDWIDE=1
PORT I/O
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 123
General Programmable Interface
Figure 10-2. Example GPIF Waveform
10.1.1 Typical GPIF Interface
The GPIF allows the EZ-USB to connect directly to external
peripherals such as ASICs, DSPs, or other digital logic that
uses an 8 or 16 bit parallel interface.
The GPIF provides external pins that can operate as outputs
(CTL[5:0]), inputs (RDY[5:0]), Data bus (FD[15:0]), and
Address Lines (GPIFADR[8:0]).
A Waveform Descriptor in internal RAM describes the
behavior of each of the GPIF signals. The Waveform
Descriptor is loaded into the GPIF registers by the EZ-USB
firmware during initialization, and it is then used throughout
the execution of the code to perform transactions over the
GPIF interface.
Figure 10-3 shows a block diagram of a typical interface
between the EZ-USB and a peripheral function.
Figure 10-3. EZ-USB Interfacing to a Peripheral
The following sections detail the features available and
steps needed to create an efficient GPIF design. This
includes definition of the external GPIF connections and the
internal register settings, along with EZ-USB firmware
needed to execute data transactions over the interface.
10.2 Hardware
Table 10-1 lists the registers associated with the GPIF hard-
ware; a detailed description of each register may be found in
the Registers chapter on page 211.
GPIFADR[8:0]
FD[15:0]
CTL0
RDY0
S0 S1 S2 S3 S4 S5 S6
ZZ
VALID
AA+1
GPIFADR[8:0]
FD[15:0]
CTL[5:0]
RDY[5:0]
PORT I/O
GSTATE[2:0]
EZ-USB
Master
Mode
Peripheral
IFCLK
Debug
Table 10-1. Registers Associated with GPIF Hardware
Register Name
GPIFIDLECS IFCONFIG
GPIFIDLECTL FIFORESET
GPIFCTLCFG EPxCFG
PORTCCFG EPxFIFOCFG
PORTECFG EPxAUTOINLENH/L
GPIFADRH/L EPxFIFOPFH/L
GPIFTCB3:0
GPIFWFSELECT EPxGPIFTRIG
EPxGPIFFLGSEL GPIFABORT
EPxGPIFPFSTOP XGPIFSGLDATH/LX/LNOX
GPIFREADYCFG GPIFSGLDATH/LX/LNOX
GPIFREADYSTAT GPIFTRIG
Note The ‘x’ in these register names represents 2, 4, 6, or 8; endpoints 0
and 1 are not associated with the GPIF.
124 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
10.2.1 The External GPIF Interface
The GPIF provides many general input and output signals
with which external peripherals may be interfaced ‘glue-
lessly’ to the EZ-USB.
The GPIF interface signals are shown in Table 10-2.
The Control Output pins (CTL[5:0]) are usually used as
strobes (enable lines), read/write lines, and others.
The Ready Input pins (RDY[5:0]) are sampled by the GPIF
and can force a transaction to wait (inserting wait states),
continue, or repeat until they are in a particular state.
The GPIF Data Bus is a collection of the FD[15:0] pins.
■An 8 bit wide GPIF interface uses pins FD[7:0].
■A 16 bit wide GPIF interface uses pins FD[15:0].
The GPIF Address lines (GPIFADR[8:0]) can generate an
incrementing address as data is transferred. If higher order
address lines are needed, other non-GPIF I/O signals (for
example, general-purpose I/O pins) may be used.
The Interface Clock, IFCLK, can be configured to be either
an input (default) or an output interface clock for synchro-
nous interfaces to external logic.
The GSTATE[2:0] pins are outputs that show the current
GPIF State number; they are used for debugging GPIF
waveforms.
The number of GPIF signals available externally varies
depending on the package. See package information in
Introducing EZ-USB® chapter on page 13.
10.2.2 Default GPIF Pins Configuration
The EZ-USB comes out of reset with its I/O pins configured
in Ports mode, not GPIF Master mode. To configure the pins
for GPIF mode, the IFCFG1:0 bits in the IFCONFIG register
must be set to ‘10’ (see Table 13-10, “IFCFG Selection of
Port I/O Pin Functions,” on page 188 for details).
10.2.3 Six Control OUT Signals
The 100 and 128-pin EZ-USB packages bring out all six
Control Output pins, CTL[5:0]. The 56-pin package brings
out three of these signals, CTL[2:0]. CTLx waveform edges
can be programmed to make transitions as often as once
per IFCLK clock (once every 20.8 ns if IFCLK is running at
48 MHz).
By default, these signals are driven high.
10.2.3.1 Control Output Modes
The GPIF Control pins (CTL[5:0]) have several output
modes:
■CTL[3:0] can act as CMOS outputs (optionally tristat-
able) or open drain outputs.
■CTL[5:4] can act as CMOS outputs or open-drain out-
puts.
If CTL[3:0] are configured to be tristatable, CTL[5:4] are
not available.
10.2.4 Six Ready IN Signals
The 100 and 128-pin EZ-USB packages bring out all six
Ready inputs, RDY[5:0]. The 56-pin package brings out two
of these signals, RDY[1:0].
The RDY inputs can be sampled synchronously or asyn-
chronously. When the GPIF samples RDY inputs asynchro-
nously (SAS = 0), the RDY inputs are unavoidably delayed
by a small amount (approximately 24 ns at 48 MHz IFCLK).
In other words, when the GPIF ‘looks’ at a RDY input, it
actually ‘sees’ the state of that input 24 ns ago.
10.2.5 Nine GPIF Address OUT Signals
Nine GPIF address lines, GPIFADR[8:0], are available. If the
GPIF address lines are configured as outputs, writing to the
GPIFADRH:L registers drives these pins immediately. The
GPIF engine can then increment them under control of the
Waveform Descriptors. The GPIF address lines can be tri-
stated by clearing the associated PORTxCFG bits and OEx
bits to ‘0’ (see section 13.4.3 Port C Alternate Functions on
page 187 and section 13.4.4 Port E Alternate Functions on
page 188).
10.2.6 Three GSTATE OUT Signals
Three GPIF State lines, GSTATE[2:0], are available as an
alternate configuration of PORTE[2:0]. These default to gen-
eral-purpose inputs; setting GSTATE (IFCONFIG.2) to ‘1’
selects the alternate configuration and overrides
PORTECFG[2:0] bit settings.
Table 10-2. GPIF Pin Descriptions
PIN IN/OUT Description
CTL[5:0] O / Hi-Z Programmable control outputs
RDY[5:0] I Sampleable ready inputs
FD[15:0] I / O / Hi-Z Bidirectional FIFO data bus
GPIFADR[8:0] O / Hi-Z Address outputs
IFCLK I / O Interface clock
GSTATE[2:0] O / Hi-Z Current GPIF State number (for debug) Table 10-3. CTL[5:0] Output Modes
TRICTL
(GPIFCTLCFG.7) GPIFCTLCFG[6:0] CTL[3:0] CTL[5:4]
00
CMOS,
Not Tri-statable CMOS,
Not Tri-statable
0 1 Open-Drain Open-Drain
1X
CMOS,
Tri-statable Not Available
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 125
General Programmable Interface
The GSTATE[2:0] pins output the current GPIF State num-
ber; this feature is used for debugging GPIF waveforms, and
is useful for correlating intended GPIF waveform behavior
with actual observed GPIF signaling.
10.2.7 8/16-Bit Data Path, WORDWIDE =
1 (default) and WORDWIDE = 0
When the EZ-USB is configured for GPIF Master mode,
PORTB is always configured as FD[7:0].
If any of the WORDWIDE bits (EPxFIFOCFG.0) are set to
‘1’, PORTD is automatically configured as FD[15:8]. If all the
WORDWIDE bits are cleared to ‘0’, PORTD is available for
general-purpose I/O.
10.2.8 Byte Order for 16 Bit GPIF
Transactions
Data is sent over USB in packets of 8-bit bytes, not 16-bit
words. When the FIFO Data bus is 16 bits wide, the first
byte in every pair sent over USB is transferred over FD[7:0]
and the second byte is transferred over FD[15:8].
10.2.9 Interface Clock (IFCLK)
The GPIF interface can be clocked from either an internal or
an external source. The EZ-USB’s internal clock source can
be configured to run at either 30 or 48 MHz, and it can
optionally be output on the IFCLK pin. If the EZ-USB is con-
figured to use an external clock source, the IFCLK pin can
be driven at any frequency between 5 MHz and 48 MHz. On
a hard reset, the EZ-USB defaults to the internal source at
48 MHz, normal polarity, with the IFCLK output disabled.
See Figure 10-4.
IFCONFIG.7 selects between internal and external sources:
0 = external, 1 = internal. If an external IFCLK is chosen, it
must be free running at a minimum frequency of 5 MHz. In
addition, in order to provide synchronization for the internal
endpoint FIFO logic, the external IFCLK source must be
present before the firmware sets IFCONFIG.7 = 0.
IFCONFIG.6 selects between the 30 and 48 MHz internal
clock: 0 = 30 MHz; 1 = 48 MHz. This bit has no effect when
IFCONFIG.7 = 0.
IFCONFIG.5 is the output enable for the internal clock
source: 0 = disable; 1 = enable. This bit has no effect when
IFCONFIG.7 = 0.
IFCONFIG.4 inverts the polarity of the interface clock
(whether it is internal or external): 0 = normal; 1 = inverted.
IFCLK inversion can make it easier to interface the EZ-USB
with certain external circuitry. When an internal IFCLK is
used (IFCONFIG.7 = 1), IFCONFIG.4 only affects the IFCLK
output polarity (if IFCONFIG.5 = 1). When an external IFCLK
is used (IFCONFIG.7 = 0), IFCONFIG.4 only affects the
IFCLK input polarity. Figure 10-5 on page 126, for example,
demonstrates the use of IFCLK output inversion in order to
ensure a long enough setup time (ts) for a control signal to
the peripheral.
Figure 10-4. IFCLK Configuration
Note When IFCLK is configured as an input, the mini-
mum external frequency that can be applied to it is
5 MHz. This clock must be applied prior to initial-
ization of the GPIF and interruptions of it lowers
the overall frequency, causing violations of the
minimum frequency requirement.
0
1
30 MHz
48 MHz 0
1
0
1
1
0
Internal
IFCLK
Signal
IFCFG.7
IFCFG.4
IFCFG.6 IFCFG.4 IFCFG.5
IFCLK
Pin
126 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Figure 10-5. Satisfying Setup Timing by Inverting the IFCLK
Output
10.2.10 Connecting GPIF Signal Pins to
Hardware
The first step in creating the interface between the EZ-
USB’s GPIF and an external peripheral is to define the hard-
ware interconnects.
1. Choose IFCLK settings. Choose either the internal or
external interface clock. If internal, choose either 30 or
48 MHz; if external, ensure that the frequency of the
external clock is in the range 5-48 MHz, and that it is free
running.
2. Determine the proper FIFO Data Bus size. If the data
bus for the interface is 8 bits wide, use the FD[7:0] pins
and set WORDWIDE=0. If the data bus for the interface
is 16 bits wide, use FD[15:0] and set WORDWIDE=1.
3. Assign the CTLx signals to the interface. Make a list
of all interface signals to be driven from the GPIF to the
peripheral, and assign them to the CTL[5:0] inputs. If
there are more output signals than available CTLx out-
puts, non-GPIF I/O signals must be driven manually by
EZ-USB firmware. In this case, the CTLx outputs should
be assigned only to signals that must be driven as part of
a data transaction.
4. Assign the RDYn signals to the interface. Make a list
of all interface signals to be driven from the peripheral to
the GPIF, and assign them to the RDY[5:0] inputs. If
there are more input signals than available RDY inputs,
non-GPIF I/O signals must be sampled manually by EZ-
USB firmware. In this case, the RDYn inputs should be
used only for signals that must be sampled as part of a
data transaction.
5. Determine the proper GPIF Address connections. If
the interface uses an Address Bus, use the GPI-
FADR[8:0] signals for the least significant bits, and other
non-GPIF I/O signals for the most significant bits. If the
address pins are not needed (as when, for instance, the
peripheral is a FIFO) they may be left unconnected.
10.2.11 Example GPIF Hardware
Interconnect
Table 10-4 illustrates the hardware connections that can be
made for a standard interface to a 27C256 EPROM.
The process is the same for larger, more-complicated inter-
faces.
Note Two other GPIF hardware interconnect examples are
also available in the GPIF Designer utility. These examples
illustrate a connection between the GPIF and the asynchro-
nous FIFO as well as a connection between the GPIF and a
DSP from Texas Instrument.
EZ-USB
Asserts
Flag
t
s
Master
Samples
Flag
Internal IFCLK Signal
Inverted IFCLK Output
FIFO Flag
Table 10-4. Example GPIF Hardware Interconnect
Step Result Connection Made
1. Choose IFCLK settings. Internal IFCLK, 48MHz, Async RDY sampling, GPIF. No connection.
2. Determine proper FIFO Data Bus size. 8 bits from the EPROM. FD[7:0] to D[7:0]. Firmware writes WORDWIDE=0.
3. Assign CTLx signals to the interface. CS and OE are inputs to the EPROM. CTL0 to CS.
CTL1 to OE.
4. Assign RDYn signals to the interface. 27C256 EPROM has no output ready/wait signals. No connection.
5. Determine the proper GPIFADR connections. 16 bits of address. GPIFADR[8:0] to A[8:0] and other I/O pins to A[15:9].
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 127
General Programmable Interface
10.3 Programming the GPIF
Waveforms
Each GPIF Waveform Descriptor can define up to seven
States. In each State, the GPIF can be programmed to:
■Drive (high or low) or float the CTL outputs
■Sample or drive the FIFO Data bus
■Increment the value on the GPIF Address bus
■Increment the pointer into the current FIFO
■Trigger a GPIFWF (GPIF Waveform) interrupt
Additionally, each State may either sample any two of the
following:
■The RDYx input pins
■A FIFO flag
■The INTRDY (internal RDY) flag
■The Transaction-Count-Expired flag
then AND, OR, or XOR the two terms and branch on the
result to any State
or:
■Delay a specified number [1-256] of IFCLK cycles
States that sample and branch are called ‘Decision Points’
(DPs); states that do not are called ‘Non-Decision Points’
(NDPs).
Figure 10-6. GPIF State Machine Overview
10.3.1 The GPIF Registers
Two blocks of registers control the GPIF state machine:
■GPIF Configuration Registers — These registers con-
figure the general settings and report the status of the
interface. Refer to the Registers chapter on page 211
and the remainder of this chapter for details.
■Waveform Registers — These registers are loaded
with the Waveform Descriptors that configure the GPIF
state machine; there are a total of 128 bytes located at
addresses 0xE400 to 0xE47F. The GPIF Designer utility
should be used to create Waveform Descriptors.
GPIF transactions cannot be initiated until the Configuration
registers and Waveform registers are loaded by EZ-USB
firmware.
Access to the Waveform registers is only allowed while the
EZ-USB is in GPIF mode (i.e., IFCFG1:0 = 10). The Wave-
form registers may only be written while the GPIF engine is
halted (for example, DONE = 1).
If it is desired to dynamically reconfigure Waveform Descrip-
tors, this may be accomplished by writing just the bytes that
change; it is not necessary to reload the entire set of Wave-
form Descriptors in order to modify only a few bytes.
10.3.2 Programming GPIF Waveforms
The ‘programs’ for GPIF waveforms are the Waveform
Descriptors, which are stored in the Waveform registers by
EZ-USB firmware.
The EZ-USB can hold up to four Waveform Descriptors,
each of which can be used for one of four types of transfers:
Single Write, Single Read, FIFO Write, or FIFO Read. By
default, one Waveform Descriptor is assigned to each trans-
fer type, but it is not necessary to retain that configuration;
all four Waveform Descriptors could, for instance, be config-
ured for FIFO Write usage (see the GPIFWFSELECT regis-
ter in the Registers chapter on page 211).
Each Waveform Descriptor consists of up to seven 32 bit
State Instructions that program key transition points for
GPIF interface signals. There is a one-to-one correspon-
dence between the State Instructions and the GPIF state
machine States. Among other things, each State Instruction
defines the state of the CTLx outputs, the state of FD[15:0],
the use of the RDYn inputs, and the behavior of GPI-
FADR[8:0].
trig
(up to 7 programmable states)
and
GPIF State Machine
INTRDY bit
GPIFWF ISR
Event
Firmware Hooks
State X
State Y
NDP
DP
State 7
State 7
IDLE
IDLE
CPU
Y
where:
1
6
(reserved)
CPU
GPIF
X = Y-1
(A
LFunc
B) {
A
ND,
OR,
XOR}
Done
128 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Transitions from one State to another always happen on a
rising edge of the IFCLK, but the GPIF may remain in one
State for many IFCLK cycles.
10.3.2.1 The GPIF IDLE State
A Waveform consists of up to seven programmable States,
numbered S0 to S6, and one special Idle State: S7. Note A
Waveform terminates when the GPIF program branches to
its Idle State.
To complete a GPIF transaction, the GPIF program must
branch to the IDLE State, regardless of the State that the
GPIF program is currently executing. For example, a GPIF
Waveform might be defined by a program which contains
only two programmed States, S0 and S1. The GPIF program
would branch from S1 (or S0) to S7 when it wished to termi-
nate.
The state of the GPIF signals during the Idle State is deter-
mined by the contents of the GPIFIDLECS and GPI-
FIDLECTL registers.
Once a waveform is triggered, another waveform may not
be started until the first one terminates. Termination of a
waveform is signaled through the DONE bit (GPIFIDLECS.7
or GPIFTRIG.7) or, optionally, through the GPIFDONE inter-
rupt.
■If DONE = 0, the GPIF is busy generating a Waveform.
■If DONE = 1, the GPIF is done (GPIF is in the Idle State)
and ready for firmware to start the next GPIF transaction.
Note With one exception (writing to the GPIFABORT regis-
ter in order to force the current waveform to terminate) it is
illegal to write to any of the GPIF-related registers (including
the Waveform Registers) while the GPIF is busy. Doing so
causes indeterminate behavior likely to result in data corrup-
tion.
GPIF Data Bus During IDLE
During the Idle State, the GPIF Data Bus (FD[15:0]) can be
either driven or tri-stated, depending on the setting of the
IDLEDRV bit (GPIFIDLECS.0):
■If IDLEDRV = 0, the GPIF Data Bus is tri-stated during
the Idle State.
■If IDLEDRV = 1, the GPIF Data Bus is actively driven
during the Idle State, to the value last placed on the bus
by a GPIF Waveform.
CTL Outputs During IDLE
During the IDLE State, the state of CTL[5:0] depends on the
following register bits:
■TRICTL (GPIFCTLCFG.7), as described in section
10.2.3.1 Control Output Modes on page 124.
■GPIFCTLCFG[5:0]
■GPIFIDLECTL[5:0].
The combination of these bits defines CTL5:0 during IDLE
as follows:
■If TRICTL is ‘0’, GPIFIDLECTL[5:0] directly represent
the output states of CTL5:0 during the IDLE State. The
GPIFCTLCFG[5:0] bits determine whether the CTL5:0
outputs are CMOS or open drain: If GPIFCTLCFG.x = 0,
CTLx is CMOS; if GPIFCTLCFG.x = 1, CTLx is open
drain.
■If TRICTL is ‘1’, GPIFIDLECTL[7:4] are the output
enables for the CTL[3:0] signals, and GPIFIDLECTL[3:0]
are the output values for CTL[3:0]. CTL4 and CTL5 are
unavailable in this mode.
Table 10-5 illustrates this relationship.
10.3.2.2 Defining States
Each Waveform is made up of a number of States, each of
which is defined by a 32 bit State Instruction. Each State can
be one of two basic types: a Non-Decision Point (NDP) or a
Decision Point (DP).
For ‘write’ waveforms, the data bus is either driven or tri-
stated during each State. For ‘read’ waveforms, the data bus
is either sampled/stored or not sampled during each State.
Non-Decision Point (NDP) States
For NDP States, the control outputs (CTLx) are defined by
the GPIF instruction to be either ‘1’, ‘0’, or tri-stated during
the entire State. NDP States have a programmable fixed
duration in units of IFCLK cycles.
Figure 10-7 illustrates the basic concept of NDP States. A
write waveform is shown, and for simplicity all the States are
shown with equal spacing. Although there are a total of six
programmable CTL outputs, only one (CTL0) is shown in
Figure 10-7.
Table 10-5. Control Outputs (CTLx) During the IDLE State
TRICTL Control
Output Output State Output Enable
0
CTL0 GPIFIDLECTL.0
N/A
(CTL Outputs are always
enabled when TRICTL = 0)
CTL1 GPIFIDLECTL.1
CTL2 GPIFIDLECTL.2
CTL3 GPIFIDLECTL.3
CTL4 GPIFIDLECTL.4
CTL5 GPIFIDLECTL.5
1
CTL0 GPIFIDLECTL.0 GPIFIDLECTL.4
CTL1 GPIFIDLECTL.1 GPIFIDLECTL.5
CTL2 GPIFIDLECTL.2 GPIFIDLECTL.6
CTL3 GPIFIDLECTL.3 GPIFIDLECTL.7
CTL4 N/A
(CTL4 and CTL5 are not available when TRICTL =
1)
CTL5
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General Programmable Interface
Figure 10-7. Non-Decision P int (NDP) States
The following information refers to Figure 10-7.
In State 0:
■FD[7:0] is programmed to be tri-stated.
■CTL0 is programmed to be driven to a logic ‘1’.
In State 1:
■FD[7:0] is programmed to be driven.
■CTL0 is still programmed to be driven to a logic ‘1’.
In State 2:
■FD[7:0] is programmed to be driven.
■CTL0 is programmed to be driven to a logic ‘0’.
In State 3:
■FD[7:0] is programmed to be driven.
■CTL0 is still programmed to be driven to a logic ‘0’.
In State 4:
■FD[7:0] is programmed to be driven.
■CTL0 is programmed to be driven to a logic ‘1’.
In State 5:
■FD[7:0] is programmed to be tri-stated.
■CTL0 is still programmed to be driven to a logic ‘1’.
In State 6:
■FD[7:0] is programmed to be tri-stated.
■CTL0 is still programmed to be driven to a logic ‘1’.
Since all States in this example are coded as NDPs, the
GPIF automatically branches from the last State (S6) to the
Idle State (S7). This is the State in which the GPIF waits until
the next GPIF waveform is triggered by the firmware.
States 2 and 3 in the example are identical, as are States 5
and 6. In a real application, these would probably be com-
bined (there is no need to duplicate a State in order to
‘stretch’ it, since each NDP State can be assigned a duration
in terms of IFCLK cycles). If fewer than 7 States were
defined for this waveform, the Idle State would not automati-
cally be entered after the last programmed State; that last
programmed State’s State Instruction would have to include
an explicit unconditional branch to the Idle State.
Decision Point States
Any State can be designated as a Decision Point (DP). A DP
allows the GPIF engine to sample two signals — each of the
‘two’ can be the same signal, if desired — perform a bool-
ean operation on the sampled values, then branch to other
States (or loop back on itself, remaining in the current State)
based on the result.
If a State Instruction includes a control task (advance the
FIFO pointer, increment the GPIFADR address, and so on),
that task is always executed once upon entering the State,
regardless of whether the State is a DP or NDP. If the State
is a DP that loops back on itself, however, it can be pro-
grammed to re-execute the control task on every loop.
With a Decision Point, the GPIF can perform simple tasks
(wait until a RDY line is low before continuing to the next
State, for instance). Decision point States can also perform
more-complex tasks by branching to one State if the opera-
tion on the sampled signals results in a logic ‘1’, or to a dif-
ferent State if it results in a logic ‘0’.
In each State Instruction, the two signals to sample can be
selected from any of the following:
■The six external RDY signals (RDY0-RDY5)
■One of the current FIFO’s flags (PF, EF, FF)
■The INTRDY bit in the READY register
■A Transaction Count Expired signal (which replaces
RDY5)
The State Instruction also specifies a logic function (AND,
OR, or XOR) to be applied to the two selected signals. If it is
desired to act on the state of only one signal, the usual pro-
cedure is to select the same signal twice and specify the
logic function as AND.
GPIFADR[8:0]
FD[15:0]
CTL0
S0 S1 S2 S3 S4 S5 S6
ZZ
VALID
A
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General Programmable Interface
The State Instruction also specifies which State to branch to
if the result of the logical expression is ‘0,’ and which State to
branch to if the result of the logical expression is ‘1.’
Below is an example waveform created using one Decision
Point State (State 1); Non-Decision Point States are used for
the rest of the waveform.
In Figure 10-8 and Figure 10-9, there is a single Decision
Point defined as State 1. In this example, the input ready
signal is assumed to be connected to RDY0, and the State
Instruction for S1 is configured to branch to State 2 if RDY0
is a logic ‘0’ or to branch to State 1 (for example, loop indefi-
nitely) if RDY0 is a logic ‘1’.
In Figure 10-8, the GPIF remains in S1 until the RDY0 signal
goes low, then branches to S2. Figure 10-9 illustrates the
GPIF behavior when the RDY0 signal is already low when
S1 is entered: The GPIF branches to S2.
Note Although it appears in Figure 10-9 that the GPIF
branches immediately from State 1 to State 2, this is not
exactly true. Even if RDY0 is already low before the GPIF
enters State 1, the GPIF spends one IFCLK cycle in State 1
to evaluate the decision point. The logic function is applied
on the rising edge of IFCLK entering State 1. If the logic
function holds TRUE at this point, then the branch is effec-
tive on the next rising of IFCLK.
Figure 10-8. One Decision Point: Wait States Inserted Until RDY0 Goes Low
Figure 10-9. One Decision Point: No Wait States Inserted: RDY0 is Already Low at Decision Point I1
GPIFADR[8:0]
FD[15:0]
CTL0
RDY0
S0 S1 S2 S3 S4 S5 S6
ZZ
VALID
A
GPIFADR[8:0]
FD[15:0]
CTL0
RDY0
S0 S1 S2 S3 S4 S5 S6
ZZ
VALID
A
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General Programmable Interface
10.3.3 Reexecuting a Task Within a DP
State
In the simple DP examples shown earlier in this chapter, a
control task (e.g., output a word on FD[15:0] and increment
GPIFADR[8:0]) executes only once at the start of a DP
State, then the GPIF waits, sampling a RDYx input repeat-
edly until that input ‘tells’ the GPIF to branch to the next
State.
The GPIF also has the capability to reexecute the control
task every time the RDYx input is sampled; this feature can
be used to burst a large amount of data without passing
through the Idle State (a waveform example is shown in
Figure 10-10).
To re-execute a task within a decision point state, the reexe-
cute bit for that decision point must be enabled. This is per-
formed by checking the ‘Loop (Re-Execute)’ check-box
within GPIF Designer (an example is shown in
Figure 10-11). Figure 10-13 on page 132 shows an example
of a GPIF waveform that uses a DP state which does not re-
execute its control tasks.
Figure 10-10. Reexecuting a Task within a DP State
Figure 10-11. GPIF Designer Setup for the Waveform of Figure 10-10
D+3
A
DD+1 D+2
A+3A+2A+1
IFCLK
GPIFADR[8:0]
CTL0
RDY0
FD[15:0]
DP NDPNDP
DP, using re-execute control
task feature… to loop on to
itself until terms are met
DP, transitions to
next interval when
terms are met
132 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Figure 10-12. GPIF Designer Output for the Waveform of Figure 10-10
Figure 10-13. A DP State That Does NOT Reexecute the Task
State 01234567
AddrMode Same Val Inc Val Same Val Same Val Same Val Same Val Same Val
DataMode Activate Activate No Data No Data No Data No Data No Data
NextData SameData NextData SameData SameData SameData SameData SameData
Int Trig No Int No Int No Int No Int No Int No Int No Int
IF/Wait Wait 4 IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
Term A RDY0
LFUNC AND
Term B RDY0
Branch1 Then 2
Branch0 Else 1
Re-execute Yes
CTL0 10111111
CTL1 11111111
CTL2 11111111
CTL3 11111111
CTL4 11111111
CTL5 11111111
A
DD+1
A+1
IFCLK
GPIFADR[8:0]
CTL0
RDY0
FD[15:0]
DP NDPNDP
DP, loop on to itself until terms
are met… control tasks execute
on rising edge transition into
DP only…
DP, transitions to
next interval when
terms are met
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 133
General Programmable Interface
Figure 10-14. GPIF Designer Setup for the Waveform of Figure 10-13
Figure 10-15. GPIF Designer Output for the Waveform of Figure 10-13
State 01234567
AddrMode Same Val Inc Val Same Val Same Val Same Val Same Val Same Val
DataMode Activate Activate No Data No Data No Data No Data No Data
NextData SameData NextData SameData SameData SameData SameData SameData
Int Trig No Int No Int No Int No Int No Int No Int No Int
IF/Wait Wait 4 IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
Term A RDY0
LFUNC AND
Term B RDY0
Branch1 Then 2
Branch0 Else 1
Re-execute No
CTL0 10111111
CTL1 11111111
CTL2 11111111
CTL3 11111111
CTL4 11111111
CTL5 11111111
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General Programmable Interface
10.3.4 State Instructions
Each State’s characteristics are defined by a 4-byte State Instruction. The four bytes are named LENGTH / BRANCH,
OPCODE, LOGIC FUNCTION, and OUTPUT.
Note that the State Instructions are interpreted differently for Decision Points (DP = 1) and Non-Decision Points (DP = 0).
Non-Decision Point State Instruction (DP = 0)
Decision Point State Instruction (DP = 1)
LENGTH / BRANCH
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Number of IFCLK cycles to stay in this State (0 = 256 cycles)
OPCODE
76543210
x x SGL GINT INCAD NEXT/ SGLCRC DATA DP = 0
LOGIC FUNCTION
76543210
Not Used
OUTPUT (if TRICTL Bit = 1)
76543210
OE3 OE2 OE1 OE0 CTL3 CTL2 CTL1 CTL0
OUTPUT (if TRICTL Bit = 0)
76543210
x x CTL5 CTL4 CTL3 CTL2 CTL1 CTL0
LENGTH / BRANCH
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Re-Execute x BRANCHON1 BRANCHON0
OPCODE
76543210
x x SGL GINT INCAD NEXT/SGLCRC DATA DP = 1
LOGIC FUNCTION
76543210
LFUNC TERMA TERMB
OUTPUT (if TRICTL Bit = 1)
76543210
OE3 OE2 OE1 OE0 CTL3 CTL2 CTL1 CTL0
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General Programmable Interface
LENGTH / BRANCH Register. This register’s interpretation
depends on the DP bit:
■For DP = 0 (Non-Decision Point), this is a LENGTH field;
it holds the fixed duration of this State in IFCLK cycles. A
value of ‘0’ is interpreted as 256 IFCLK cycles.
■For DP = 1 (Decision Point), this is a BRANCH field; it
specifies the State to which the GPIF branches.
BRANCHON1 Specifies the State to which the GPIF
branches if the logic expression evaluates to ‘1’.
BRANCHON0 Specifies the State to which the GPIF
branches if the logic expression evaluates to ‘0’.
Re-Execute Setting this bit allows the DP to re-exe-
cute its control tasks.
OPCODE Register. This register sets a number of State
characteristics.
SGL Bit. This bit has no effect in a Single Read or Sin-
gle Write waveform. In a FIFO waveform, it specifies
whether a single data transaction should occur (from/to
the SGLDATH:L or UDMACRCH:L registers), even in a
FIFO Write or FIFO Read transaction. See also NEXT/
SGLCRC, below.
1 = Use SGLDATH:L or UDMACRCH:L.
0 = Use the FIFO.
GINT Bit. This bit specifies whether to generate a
GPIFWF interrupt during this State.
1 = Generate GPIFWF interrupt (on INT4) when
this State is reached.
0 = Do not generate interrupt.
INCAD Bit. This bit specifies whether to increment the
GPIF Address lines GPIFADR[8:0].
1 = Increment the GPIFADR[8:0] bus at the begin-
ning of this State.
0 = Do not increment the GPIFADR[8:0] signals.
NEXT/SGLCRC Bit.
If SGL = 0, specifies whether the FIFO should be
advanced at the start of this State.
1 = Move the next data in the OUT FIFO to the
top.
0 = Do not advance the FIFO.
The NEXT bit has no effect when the wave-
form is applied to an IN FIFO.
If SGL = 1, specifies whether data should be trans-
ferred to/from SGLDATH:L or UDMACRCH:L. See
also SGL Bit above.
1 = Use UDMACRCH:L.
0 = Use SGLDATH:L.
DATA Bit. This bit specifies whether the FIFO Data bus
is to be driven, tri-stated, or sampled.
During a write:
1 = Drive the FIFO Data bus with the output
data.
0 = tri-state (do not drive the bus).
During a read:
1 = Sample the FIFO Data bus and store the
data.
0 = Do not sample the data bus.
DP Bit. This bit indicates whether the State is a DP or
NDP.
1 = Decision Point.
0 = Non-Decision Point.
LOGIC FUNCTION Register. This register is used only
in DP State Instructions. It specifies the inputs (TERMA
and TERMB) and the Logic Function (LFUNC) to apply
to those inputs. The result of the logic function deter-
mines the State to which the GPIF branches (see also
LENGTH /BRANCH Register, above).
TERMA and TERMB bits:
= 000: RDY0
= 001: RDY1
= 010: RDY2
= 011: RDY3
= 100: RDY4
= 101: RDY5 (or Transaction-Count Expiration, if GPIF-
READYCFG.5 = 1)
= 110: FIFO flag (PF, EF, or FF), preselected via EPxG-
PIFFLGSEL
= 111: INTRDY (Bit 7 of the GPIFREADYCFG register)
LFUNC bits:
= 00: A AND B
= 01: A OR B
= 10: A XOR B
= 11: A AND B
The TERMA and TERMB inputs are sampled at each ris-
ing edge of IFCLK. The logic function is applied, then the
branch is taken on the next rising edge.
This register is meaningful only for DP Instructions;
when the DP bit of the OPCODE register is cleared to
‘0’, the contents of this register are ignored.
OUTPUT (if TRICTL Bit = 0)
76543210
x x CTL5 CTL4 CTL3 CTL2 CTL1 CTL0
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General Programmable Interface
OUTPUT Register. This register controls the state of the
six Control outputs (CTL5:0) during the entire State
defined by this State Instruction.
OEx Bit. If TRICTL = 1, specifies whether the cor-
responding CTLx output signal is tri-stated.
1 = Drive CTLx
0 = Tri-state CTLx
CTLx Bit. This specifies the state to set each CTLx
signal to during this entire State.
1 = High level
If the CTLx bit in the GPIFCTLCFG regis-
ter is set to ‘1’, the output driver is an open-drain.
If the CTLx bit in the GPIFCTLCFG regis-
ter is set to ‘0’, the output driver is driven to CMOS
levels.
0 = Low level
10.3.4.1 Structure of the Waveform
Descriptors
Up to four different Waveforms can be defined. Each Wave-
form Descriptor comprises up to 7 State Instructions which
are loaded into the Waveform Registers as defined in this
section.
Within each Waveform Descriptor, the State Instructions are
packed as described in Table 10-7. Waveform Descriptor 0
is shown as an example. The other Waveform Descriptors
follow exactly the same structure but at higher XDATA
addresses.
10.3.4.2 Terminating a GPIF Transfer
Once a GPIF transfer is initiated, the ONLY way to terminate
the transfer is to either:
■have it terminate naturally when the byte count expires
or
■have the 8051 terminate and abort the transfer by writing
to the GPIFABORT register.
Once a GPIF transfer is triggered, it does not terminate until
the Transaction Count (TC) has expired. The GPIF engine
checks the state of the TC only when in IDLE state. While
designing a GPIF waveform, you must have the waveform
Table 10-6. Waveform Descriptor Addresses
Waveform Descriptor Base XDATA Address
00xE400
10xE420
20xE440
30xE460
Table 10-7. Waveform Descriptor 0 Structure
XDATA
Address Contents
0xE400 LENGTH / BRANCH [0] (LENGTH / BRANCH field of State 0 of
Waveform Program 0)
0xE401 LENGTH / BRANCH [1] (LENGTH / BRANCH field of State 1 of
Waveform Program 0)
0xE402 LENGTH / BRANCH [2] (LENGTH / BRANCH field of State 2 of
Waveform Program 0)
0xE403 LENGTH / BRANCH [3] (LENGTH / BRANCH field of State 3 of
Waveform Program 0)
0xE404 LENGTH / BRANCH [4] (LENGTH / BRANCH field of State 4 of
Waveform Program 0)
0xE405 LENGTH / BRANCH [5] (LENGTH / BRANCH field of State 5 of
Waveform Program 0)
0xE406 LENGTH / BRANCH [6] (LENGTH / BRANCH field of State 6 of
Waveform Program 0)
0xE407 Reserved
0xE408 OPCODE[0] (OPCODE field of State 0 of Waveform Program
0)
0xE409 OPCODE[1] (OPCODE field of State 1 of Waveform Program
0)
0xE40A OPCODE[2] (OPCODE field of State 2 of Waveform Program
0)
0xE40B OPCODE[3] (OPCODE field of State 3 of Waveform Program
0)
0xE40C OPCODE[4] (OPCODE field of State 4 of Waveform Program
0)
0xE40D OPCODE[5] (OPCODE field of State 5 of Waveform Program
0)
0xE40E OPCODE[6] (OPCODE field of State 6 of Waveform Program
0)
0xE40F Reserved
0xE410 OUTPUT[0] (OUTPUT field of State 0 of Waveform Program 0)
0xE411 OUTPUT[1] (OUTPUT field of State 1 of Waveform Program 0)
0xE412 OUTPUT[2] (OUTPUT field of State 2 of Waveform Program 0)
0xE413 OUTPUT[3] (OUTPUT field of State 3 of Waveform Program 0)
0xE414 OUTPUT[4] (OUTPUT field of State 4 of Waveform Program 0)
0xE415 OUTPUT[5] (OUTPUT field of State 5 of Waveform Program 0)
0xE416 OUTPUT[6] (OUTPUT field of State 6 of Waveform Program 0)
0xE417 Reserved
0xE418 LOGIC FUNCTION[0] (LOGIC FUNCTION field of State 0 of
Waveform Program 0)
0xE419 LOGIC FUNCTION[1] (LOGIC FUNCTION field of State 1 of
Waveform Program 0)
0xE41A LOGIC FUNCTION[2] (LOGIC FUNCTION field of State 2 of
Waveform Program 0)
0xE41B LOGIC FUNCTION[3] (LOGIC FUNCTION field of State 3 of
Waveform Program 0)
0xE41C LOGIC FUNCTION[4] (LOGIC FUNCTION field of State 4 of
Waveform Program 0)
0xE41D LOGIC FUNCTION[5] (LOGIC FUNCTION field of State 5 of
Waveform Program 0)
0xE41E LOGIC FUNCTION[6] (LOGIC FUNCTION field of State 6 of
Waveform Program 0)
0xE41F Reserved
Table 10-7. Waveform Descriptor 0 Structure (continued)
XDATA
Address Contents
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 137
General Programmable Interface
pass through an IDLE state in order for the GPIF to check
the TC and finally terminate when TC has expired.
GPIF does allow you to save time and avoid going through
the IDLE state by using the ‘Transaction Count Expired’
(TCxpire) signal. This TCxpire replaces RDY5, if GPIF-
READYCFG.5 = 1. Section 10.4.3.2 Reading the Transac-
tion-Count Status in a DP State on page 150 provides
further information on this.
10.4 Firmware
The ‘x’ in these register names represents 2, 4, 6, or 8; end-
points 0 and 1 are not associated with the Slave FIFOs.
The GPIF Designer utility, distributed with the Cypress EZ-
USB Development Kit, generates C code which may be
linked with the rest of an application’s source code. Except
for GpifInit(), the GPIF Designer output source file does not
include the following basic GPIF framework and functions.
TD_Init():
… … … … …
GpifInit(); // Configures GPIF from GPIF Designer generated waveform data
// TODO: configure other endpoints, etc. here
// TODO: arm OUT buffers here
// setup INT4 as internal source for GPIF interrupts
// using INT4CLR (SFR), automatically enabled
// INTSETUP |= 0x03; //Enable INT4 Autovectoring
// SYNCDELAY;
// GPIFIE = 0x03; // Enable GPIFDONE and GPIFWF interrupts
// SYNCDELAY;
// EIE |= 0x04; // Enable INT4 ISR, EIE.2(EIEX4)=1
// TODO: configure GPIF interrupts to meet your needs here
Table 10-8. Registers Associated with GPIF Firmware
GPIFTRIG (SFR) EPxCFG
GPIFSGLDATH (SFR) EPxFIFOCFG
GPIFSGLDATLX (SFR) EPxAUTOINLENH/L
GPIFSGLDATLNOX
(SFR) EPxFIFOPFH/L
EPxGPIFTRIG EP2468STAT(SFR)
XGPIFSGLDATH EP24FIFOFLGS(SFR)
XGPIFSGLDATLX EP68FIFOFLGS(SFR)
XGPIFSGLDATLNOX EPxCS
GPIFABORT EPxFIFOFLGS
GPIFIE
GPIFIRQ EPxFIFOIE
GPIFTCB3 EPxFIFOIRQ
GPIFTCB2 INT2IVEC
GPIFTCB1 INT4IVEC
GPIFTCB0 INTSETUP
IE (SFR)
EPxBCH/L IP (SFR)
EPxFIFOBCH/L INT2CLR(SFR)
EPxFIFOBUF INT4CLR(SFR)
INPKTEND/OUTPKTEND EIE (SFR)
EXIF (SFR)
138 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
… … … … …
void GpifInit( void )
{
BYTE i;
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// 8051 doesn't have access to waveform memories 'til
// the part is in GPIF mode.
IFCONFIG = 0xCE;
// IFCLKSRC=1 , FIFOs executes on internal clk source
// xMHz=1 , 48MHz internal clk rate
// IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
// ASYNC=1 , master samples asynchronous
// GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
// IFCFG[1:0]=10, FX2 in GPIF master mode
GPIFABORT = 0xFF; // abort any waveforms pending
GPIFREADYCFG = InitData[ 0 ];
GPIFCTLCFG = InitData[ 1 ];
GPIFIDLECS = InitData[ 2 ];
GPIFIDLECTL = InitData[ 3 ];
GPIFWFSELECT = InitData[ 5 ];
GPIFREADYSTAT = InitData[ 6 ];
// use dual autopointer feature...
AUTOPTRSETUP = 0x07; // inc both pointers,
// ...warning: this introduces program holes
// ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
// source
APTR1H = MSB( &WaveData );
APTR1L = LSB( &WaveData );
// destination
AUTOPTRH2 = 0xE4;
AUTOPTRL2 = 0x00;
// transfer
for ( i = 0x00; i < 128; i++ )
{
EXTAUTODAT2 = EXTAUTODAT1;
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 139
General Programmable Interface
}
// Configure GPIF Address pins, output initial value,
PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
OEC = 0xFF; // and as outputs
PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
OEE |= 0x80; // and as output
// ...OR... tri-state GPIFADR[8:0] pins
// PORTCCFG = 0x00; // [7:0] as port I/O
// OEC = 0x00; // and as inputs
// PORTECFG &= 0x7F; // [8] as port I/O
// OEE &= 0x7F; // and as input
// GPIF address pins update when GPIFADRH/L written
SYNCDELAY; //
GPIFADRH = 0x00; // bits[7:1] always 0
SYNCDELAY; //
GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
// Configure GPIF FlowStates registers for Wave 0 of WaveData
FLOWSTATE = FlowStates[ 0 ];
FLOWLOGIC = FlowStates[ 1 ];
FLOWEQ0CTL = FlowStates[ 2 ];
FLOWEQ1CTL = FlowStates[ 3 ];
FLOWHOLDOFF = FlowStates[ 4 ];
FLOWSTB = FlowStates[ 5 ];
FLOWSTBEDGE = FlowStates[ 6 ];
FLOWSTBHPERIOD = FlowStates[ 7 ];
}
// Set Address GPIFADR[8:0] to PERIPHERAL
void Peripheral_SetAddress( WORD gaddr )
{
SYNCDELAY; //
GPIFADRH = gaddr >> 8;
SYNCDELAY; //
GPIFADRL = ( BYTE )gaddr; // setup GPIF address
}
// Set GPIF Transaction Count
void Peripheral_SetGPIFTC( WORD xfrcnt )
{
SYNCDELAY; //
GPIFTCB1 = xfrcnt >> 8; // setup transaction count
SYNCDELAY; //
GPIFTCB0 = ( BYTE )xfrcnt;
}
#define GPIF_FLGSELPF 0
#define GPIF_FLGSELEF 1
#define GPIF_FLGSELFF 2
// Set EP2GPIF Decision Point FIFO Flag Select (PF, EF, FF)
void SetEP2GPIFFLGSEL( WORD DP_FIFOFlag )
{
EP2GPIFFLGSEL = DP_FIFOFlag;
}
140 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
// Set EP4GPIF Decision Point FIFO Flag Select (PF, EF, FF)
void SetEP4GPIFFLGSEL( WORD DP_FIFOFlag )
{
EP4GPIFFLGSEL = DP_FIFOFlag;
}
// Set EP6GPIF Decision Point FIFO Flag Select (PF, EF, FF)
void SetEP6GPIFFLGSEL( WORD DP_FIFOFlag )
{
EP6GPIFFLGSEL = DP_FIFOFlag;
}
// Set EP8GPIF Decision Point FIFO Flag Select (PF, EF, FF)
void SetEP8GPIFFLGSEL( WORD DP_FIFOFlag )
{
EP8GPIFFLGSEL = DP_FIFOFlag;
}
// Set EP2GPIF Programmable Flag STOP, overrides Transaction Count
void SetEP2GPIFPFSTOP( void )
{
EP2GPIFPFSTOP = 0x01;
}
// Set EP4GPIF Programmable Flag STOP, overrides Transaction Count
void SetEP4GPIFPFSTOP( void )
{
EP4GPIFPFSTOP = 0x01;
}
// Set EP6GPIF Programmable Flag STOP, overrides Transaction Count
void SetEP6GPIFPFSTOP( void )
{
EP6GPIFPFSTOP = 0x01;
}
// Set EP8GPIF Programmable Flag STOP, overrides Transaction Count
void SetEP8GPIFPFSTOP( void )
{
EP8GPIFPFSTOP = 0x01;
}
// write single byte to PERIPHERAL, using GPIF
void Peripheral_SingleByteWrite( BYTE gdata )
{
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
}
XGPIFSGLDATLX = gdata; // trigger GPIF
// ...single byte write transaction
}
// write single word to PERIPHERAL, using GPIF
void Peripheral_SingleWordWrite( WORD gdata )
{
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 141
General Programmable Interface
}
// using registers in XDATA space
XGPIFSGLDATH = gdata >> 8;
XGPIFSGLDATLX = gdata; // trigger GPIF
// ...single word write transaction
}
// read single byte from PERIPHERAL, using GPIF
void Peripheral_SingleByteRead( BYTE xdata *gdata )
{
static BYTE g_data = 0x00;
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
}
// using registers in XDATA space, dummy read
g_data = XGPIFSGLDATLX; // trigger GPIF
// ...single byte read transaction
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
}
// using registers in XDATA space,
*gdata = XGPIFSGLDATLNOX; // ...GPIF reads byte from PERIPHERAL
}
// read single word from PERIPHERAL, using GPIF
void Peripheral_SingleWordRead( WORD xdata *gdata )
{
BYTE g_data = 0x00;
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
}
// using registers in XDATA space, dummy read
g_data = XGPIFSGLDATLX; // trigger GPIF
// ...single word read transaction
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
}
// using registers in XDATA space, GPIF reads word from PERIPHERAL
*gdata = ( ( WORD )XGPIFSGLDATH << 8 ) | ( WORD )XGPIFSGLDATLNOX;
}
#define GPIFTRIGWR 0
#define GPIFTRIGRD 4
#define GPIF_EP2 0
#define GPIF_EP4 1
142 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
#define GPIF_EP6 2
#define GPIF_EP8 3
// write bytes/words to PERIPHERAL, using GPIF and EPxFIFO
// if EPx WORDWIDE=0 then write bytes
// if EPx WORDWIDE=1 then write words
void Peripheral_FIFOWrite( BYTE FIFO_EpNum )
{
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
}
// trigger FIFO write transactions, using SFR
GPIFTRIG = FIFO_EpNum; // R/W=0, EP[1:0]=FIFO_EpNum for EPx writes
}
// read bytes/words from PERIPHERAL, using GPIF and EPxFIFO
// if EPx WORDWIDE=0 then read bytes
// if EPx WORDWIDE=1 then read words
void Peripheral_FIFORead( BYTE FIFO_EpNum )
{
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
{
;
}
// trigger FIFO read transactions, using SFR
GPIFTRIG = GPIFTRIGRD | FIFO_EpNum; // R/W=1, EP[1:0]=FIFO_EpNum for EPx reads
}
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General Programmable Interface
10.4.1 Single Read Transactions
Figure 10-16. Firmware Launches a Single Read Waveform, WORDWIDE=0
* All EPx WORDWIDE bits must be cleared to ‘0’ for 8 bit single transactions. If any of the EPx WORDWIDE bits are set to ‘1’, then single transactions are 16
bits wide.
Figure 10-17. Single Read Transaction Waveform
8051 Device Pins
IFCLK
* FD[7:0]
GPIF
GPIF
8051
CTL[5:0]
RDY[5:0]
GPIFADR[8:0]
GPIFWF
8051 INTRDY
30/48MHz
CLK
5- 48MHz
XDATA
Waveform Descriptors
WF3
WF2
WF1
WF0
GPIF DONE
XGPIFSGLDATH/L
XGPIFSGLDATLX
i2
hi-Z
0x00AB
0x80
IFCLK
GPIFADR[8:0]
CTL0
RDY0
FD[7:0]
NDPNDP NDP NDP NDP NDP
hi-Z
i1 i3 i4
144 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Figure 10-18. GPIF Designer Setup for the Waveform of Figure 10-17
Figure 10-19. GPIF Designer Output for the Waveform of Figure 10-17
To perform a Single Read transaction:
1. Initialize the GPIF Configuration Registers and Wave-
form Descriptors.
2. Check that the GPIF is IDLE by checking if the DONE bit
(GPIFIDLECS.7 or GPIFTRIG.7) is set.
3. Perform a dummy read of the XGPIFSGLDATLX register
to start a single transaction.
4. Wait for the GPIF to indicate that the transaction is com-
plete. When the transaction is complete, the DONE bit
(GPIFIDLECS.7 or GPIFTRIG.7) is set to ‘1’. If enabled,
a GPIFDONE interrupt is also generated.
5. Depending on the bus width and the desire to start
another transaction, the data read by the GPIF can be
retrieved from the XGPIFSGLDATH, XGPIFSGLDATLX,
and/or the XGPIFSGLDATLNOX register (or from the
SFR-space copies of these registers).
In 16 bit mode only, the most significant byte, FD[15:8],
of data is read from the XGPIFSGLDATH register.
In 8 and 16 bit modes, the least significant byte of data is
read by either:
❐reading XGPIFSGLDATLX, which reads the least
significant byte and starts another Single Read trans-
action.
❐reading XGPIFSGLDATLNOX, which reads the least
significant byte but does not start another Single
Read transaction.
The following C program fragments (Figure 10-20 on
page 145 and Figure 10-21 on page 146) illustrate how to
perform a Single Read transaction in 8 bit mode (WORD-
WIDE=0):
State 01234567
AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
DataMode No Data No Data Activate No Data No Data No Data No Data
NextData SameData SameData SameData SameData SameData SameData SameData
Int Trig No Int No Int No Int No Int No Int No Int No Int
IF/Wait Wait 4 Wait 1 Wait 1Wait 2Wait 1Wait 1Wait 1
Term A
LFUNC
Term B
Branch1
Branch0
Re-execute
CTL0 11011111
CTL1 11111111
CTL2 11111111
CTL3 11111111
CTL4 11111111
CTL5 11111111
sample data bus here
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 145
General Programmable Interface
Figure 10-20. Single Read Transaction Functions
#define PERIPHCS 0x00AB
#define AOKAY 0x80
#define BURSTMODE 0x0000
#define TRISTATE 0xFFFF
#define EVER ;;
// prototypes
void GpifInit( void );
// Set Address GPIFADR[8:0] to PERIPHERAL
void Peripheral_SetAddress( WORD gaddr )
{
if( gaddr < 512 )
{ // drive GPIF address bus w/gaddr
GPIFADRH = gaddr >> 8;
SYNCDELAY;
GPIFADRL = ( BYTE )gaddr; // setup GPIF address
}
else
{ // tri-state GPIFADR[8:0] pins
PORTCCFG = 0x00; // [7:0] as port I/O
OEC = 0x00; // and as inputs
PORTECFG &= 0x7F; // [8] as port I/O
OEE &= 0x7F; // and as input
}
}
// read single byte from PERIPHERAL, using GPIF
void Peripheral_SingleByteRead( BYTE xdata *gdata )
{
static BYTE g_data = 0x00;
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
}
// using registers in XDATA space, dummy read
g_data = XGPIFSGLDATLX; // to trigger GPIF single byte read transaction
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
}
// using registers in XDATA space, GPIF read byte from PERIPHERAL here
*gdata = XGPIFSGLDATLNOX;
}
146 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Figure 10-21. Initialization Code for Single Read Transactions
void TD_Init( void )
{
BYTE xdata periph_status;
… … … … …
GpifInit(); // Configures GPIF from GPIF Designer generated waveform data
// TODO: configure other endpoints, etc. here
// TODO: arm OUT buffers here
// setup INT4 as internal source for GPIF interrupts
// using INT4CLR (SFR), automatically enabled
// INTSETUP |= 0x03; //Enable INT4 Autovectoring
// SYNCDELAY;
// GPIFIE = 0x03; // Enable GPIFDONE and GPIFWF interrupts
// SYNCDELAY;
// EIE |= 0x04; // Enable INT4 ISR, EIE.2(EIEX4)=1
// TODO: configure GPIF interrupts to meet your needs here
… … … … …
// get status of peripheral function
Peripheral_SetAddress( PERIPHCS );
Peripheral_SingleByteRead( &periph_status );
if( periph_status == AOKAY )
{ // set it and forget it
Peripheral_SetAddress( BURSTMODE );
}
else
{
Peripheral_SetAddress( TRISTATE );
}
}
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 147
General Programmable Interface
10.4.2 Single Write Transactions
Figure 10-22. Firmware Launches a Single Write Waveform, WORDWIDE=0
* All EPx WORDWIDE bits must be cleared to zero for 8 bit single transactions. If any of the EPx WORDWIDE bits are set to ‘1’, then single transactions are 16
bits wide.
Figure 10-23. Single Write Transaction Waveform
8051 Device Pins
IFCLK
* FD[7:0]
GPIF
GPIF
8051
CTL[5:0]
RDY[5:0]
GPIFADR[8:0]
GPIFWF
8051 INTRDY
30/48MHz
CLK
5- 48MHz
XDATA
Waveform Descriptors
WF3
WF2
WF1
WF0
GPIF DONE
XGPIFSGLDATH/L
XGPIFSGLDATLX
hi-Z
0x00AB
hi-Z 0x01
IFCLK
GPIFADR[8:0]
CTL0
RDY0
FD[7:0]
NDPNDP NDP
– I1 NDP
i3i2i1
NDP
i4
NDP
148 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Figure 10-24. GPIF Designer Setup for the Waveform of Figure 10-23
Figure 10-25. GPIF Designer Output for the Waveform of Figure 10-23
Single Write transactions are simpler than Single Read
transactions because no dummy read operation is required.
To execute a Single Write transaction:
1. Initialize the GPIF Configuration Registers and Wave-
form Descriptors.
2. Check that the GPIF is IDLE by checking if the DONE bit
(GPIFIDLECS.7 or GPIFTRIG.7) is set.
3. If in 16 bit mode (WORDWIDE = 1), write the most signif-
icant byte of the data to the XGPIFSGLDATH register,
then write the least significant byte to the XGPIFSGL-
DATLX register to start a Single Write transaction.
4. In 8 bit mode, simply write the data to the XGPIFSGL-
DATLX register to start a Single Write transaction.
5. Wait for the GPIF to indicate that the transaction is com-
plete. When the transaction is complete, the DONE bit
(GPIFIDLECS.7 or GPIFTRIG.7) is set to ‘1’. If enabled,
a GPIFDONE interrupt is also generated.
The following C program fragments (Figure 10-26 and
Figure 10-27 on page 149) illustrate how to perform a
Single Write transaction in 8 bit mode (WORDWIDE=0):
drive databus here
State 01234567
AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
DataMode No Data No Data Activate No Data No Data No Data No Data
NextData SameData SameData SameData SameData SameData SameData SameData
Int Trig No Int No Int No Int No Int No Int No Int No Int
IF/Wait Wait 4 Wait 1 Wait 1 Wait 1Wait 1Wait 1Wait 1
Term A
LFUNC
Term B
Branch1
Branch0
Re-execute
CTL0 11011111
CTL1 11111111
CTL2 11111111
CTL3 11111111
CTL4 11111111
CTL5 11111111
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 149
General Programmable Interface
Figure 10-26. Single Write Transaction Functions
Figure 10-27. Initialization Code for Single Write Transactions
#define PERIPHCS 0x00AB
#define P_HSMODE 0x01
// prototypes
void GpifInit( void );
// Set Address GPIFADR[8:0] to PERIPHERAL
void Peripheral_SetAddress( WORD gaddr )
{
GPIFADRH = gaddr >> 8;
SYNCDELAY;
GPIFADRL = ( BYTE )gaddr; // setup GPIF address
}
// write single byte to PERIPHERAL, using GPIF
void Peripheral_SingleByteWrite( BYTE gdata )
{
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
}
XGPIFSGLDATLX = gdata; // trigger GPIF single byte write transaction
}
void TD_Init( void )
{
… … … … …
GpifInit(); // Configures GPIF from GPIF Designer generated waveform data
// TODO: configure other endpoints, etc. here
// TODO: arm OUT buffers here
// setup INT4 as internal source for GPIF interrupts
// using INT4CLR (SFR), automatically enabled
// INTSETUP |= 0x03; //Enable INT4 Autovectoring
// SYNCDELAY;
// GPIFIE = 0x03; // Enable GPIFDONE and GPIFWF interrupts
// SYNCDELAY;
// EIE |= 0x04; // Enable INT4 ISR, EIE.2(EIEX4)=1
// TODO: configure GPIF interrupts to meet your needs here
… … … … …
// tell peripheral we are going into high speed xfr mode
Peripheral_SetAddress( PERIPHCS );
Peripheral_SingleByteWrite( P_HSMODE );
}
150 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
10.4.3 FIFO Read and FIFO Write (Burst)
Transactions
FIFO Read and FIFO Write waveforms transfer data to and
from the EZ-USB’s Slave FIFOs (See chapter “Slave FIFOs”
on page 99). The waveform is started by writing to EPxG-
PIFTRIG, where ‘x’ represents the FIFO (2, 4, 6, or 8) to/
from which data should be transferred, or to GPIFTRIG.
A FIFO Read or FIFO Write waveform generally transfers a
long stream of data rather than a single byte or word. Usu-
ally, the waveform is programmed to terminate after a speci-
fied number of transactions or when a FIFO flag asserts (for
example, when an IN FIFO is full or an OUT FIFO is empty).
A ‘transaction’ is a transfer of a single byte (if WORDWIDE =
0) or word (if WORDWIDE = 1) to or from a FIFO. Using the
GPIF Designer’s terminology, a transaction is either an ‘Acti-
vate Data’ for a FIFO Read or a ‘Next FIFO Data’ for a FIFO
Write.
10.4.3.1 Transaction Counter
To use the Transaction Counter for FIFO ‘x’, load
GPIFTCB3:0 with the desired number of transactions (1 to
4,294,967,295). When a FIFO Read or Write waveform is
triggered on that FIFO, the GPIF transfers the specified
number of bytes (or words, if WORDWIDE = 1) automati-
cally.
This mode of operation is called Long Transfer Mode; when
the Transaction Counter is used in this way, the Waveform
Descriptor should branch to the Idle State after each trans-
action.
Each time through the Idle State, the GPIF checks the
Transaction Count; when it expires, the waveform termi-
nates and the DONE bit is set. Otherwise, the GPIF re-exe-
cutes the entire Waveform Descriptor. Note In Long Transfer
Mode, the DONE bit is not set until the Transaction Count
expires.
While the Transaction Count is active, the GPIF checks the
Full Flag (for IN FIFOs) or the Empty Flag (for OUT FIFOs)
on every pass through the Idle State. If the flag is asserted,
the GPIF pauses until the over/underflow threat is removed,
then it automatically resumes. In this way, the GPIF auto-
matically throttles data flow in Long Transfer Mode.
The GPIFTCB3:0 registers are readable and they update as
transactions occur, so the CPU can read the Transaction
Count value at any time.
10.4.3.2 Reading the Transaction-Count
Status in a DP State
To sample the transaction-count status in a DP State, set
GPIFREADYCFG.5 to ‘1’ (which instructs the EZ-USB to
replace the RDY5 input with the transaction-count expiration
flag), then launch a FIFO transaction which uses a transac-
tion count. The EZ-USB sets the transaction-count expira-
tion flag to ‘1’ when the transaction count expires. This
feature allows the Transaction Counter to be used without
passing through the Idle State after each transaction.
10.4.4 GPIF Flag Selection
The GPIF can examine the PF, EF, or FF (of the current
FIFO) during a waveform. One of the three flags is selected
by the FS[1:0] bits in the EPxGPIFFLGSEL register; that
selected flag is called the GPIF Flag.
10.4.5 GPIF Flag Stop
When EPxGPIFPFSTOP.0 is set to ‘1’, FIFO Read and Write
transactions are terminated by the assertion of the GPIF
Flag. When this feature is used, it overrides the Transaction
Counter; the GPIF waveform terminates (sets DONE to ‘1’)
only when the GPIF Flag asserts. If the GPIF Flag is already
asserted at the time the waveform is launched, a GPIF
DONE interrupt is not generated.
No special programming of the Waveform Descriptors is
necessary, and FIFO Waveform Descriptors that transition
through the Idle State on each transaction (for example,
waveforms that do not use the Transaction Counter) are
unaffected. Automatic throttling of the FIFOs in IDLE still
occurs, so there is no danger of the GPIF writing to a full
FIFO or reading from an empty FIFO.
Note Unless the firmware aborts the GPIF transfer by writ-
ing to the GPIFABORT register, only the GPIF Flag asser-
tion terminates the waveform and sets the DONE bit.
A waveform can potentially execute forever if the GPIF Flag
never asserts.
Important The GPIF Flag is only automatically tested by the
EZ-USB core while transitioning through the IDLE State, and
the assertion of the GPIF Flag is not latched. Since the
assertion of the GPIF Flag is not latched, if it is asserted and
deasserted during the waveform (due to the dynamic rela-
tionship between USB host activity and status of the EZ-
USB FIFOs), the EZ-USB core would not see the GPIF Flag
asserted in the IDLE state.
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 151
General Programmable Interface
10.4.5.1 Performing a FIFO Read Transaction
Figure 10-28. Firmware Launches a FIFO Read Waveform
Figure 10-29. Example FIFO Read Transaction
EPxEF
FIFOADR[1:0]
Slave FIFOs
8051 Device Pins
EPxFF
EPxPF
SLOE
SLRD
SLWR
INPKTEND
IFCLK
FD[7:0]
EP4FIFOBUF
EP6FIFOBUF
EP8FIFOBUF
EP2FIFOBUF
EP8
EP6
EP4
EP2
GPIF
GPIF
8051
CTL[5:0]
RDY[5:0]
GPIFADR[8:0]
GPIFWF
8051 INTRDY
30/48MHz
CLK
5 - 48MHz
XDATA
Waveform Descriptors
WF3
WF2
WF1
WF0
GPIF DONE
GPIFTRIG
i2
…
…
0x01 Peripheral data (Pdata)
0x01 0x02 0x03 0xFF
NN+1 N+2 512
TC=N
TC=N+1
TC=N+2
TC=512
0x02
0x03
0xFF
EPxFIFOBUF
…
…
GPIF TC
i2 i2 i2
…
152 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Figure 10-30. FIFO Read Transaction Waveform
The above waveform executes until the Transaction Counter
expires (until it counts to 512, in this example). The Transac-
tion Counter is decremented and sampled on each pass
through the IDLE state. When the Transaction Counter is
used without passing through the IDLE state, the Transac-
tion Counter is decremented on each ‘Activate’ (which sam-
ples the data bus).
Each iteration of the waveform reads a data value from the
FIFO data bus into the FIFO, then decrements and checks
the Transaction Counter. When it expires, the DONE bit is
set to ‘1’ and the GPIFDONE interrupt request is asserted.
Figure 10-31. GPIF Designer Setup for the Waveform of Figure 10-30
hi-Z
0x0000
hi-Z Pdata++
IFCLK
GPIFADR[8:0]
CTL0
RDY0
FD[7:0]
NDPNDP NDP
– I1 NDP
i3i2i1
NDP
i4
NDP
sample databus here
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 153
General Programmable Interface
Figure 10-32. GPIF Designer Output for the Waveform of Figure 10-30
Typically, when performing a FIFO Read, only one ‘Activate’
is needed in the waveform, since each execution of ‘Acti-
vate’ increments the internal FIFO pointer (and EPxBCH:L)
automatically.
To perform a FIFO Read Transaction:
1. Program the EZ-USB to detect completion of the trans-
action. As with all GPIF Transactions, bit 7 of the
GPIFTRIG register (the DONE bit) signals when the
Transaction is complete.
2. In the GPIFTRIG register, set the RW bit to ‘1’ and load
EP[1:0] with the appropriate value for the FIFO which is
to receive the data.
3. Program the EZ-USB to commit (‘pass-on’) the data from
the FIFO to the endpoint. The data can be transferred
from the FIFO to the endpoint by either of the following
methods.
❐AUTOIN=1: CPU is not in the data path; the EZ-USB
automatically commits data from the FIFO Data bus
to the USB.
❐AUTOIN=0: Firmware must manually commit data to
the USB by writing either EPxBCL or INPKTEND
(with SKIP=0).
The following C program fragments (Figure 10-33 on
page 154 through Figure 10-36 on page 156) illustrate how
to perform a FIFO Read transaction in 8 bit mode (WORD-
WIDE = 0) with AUTOIN = 0.
State 01234567
AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
DataMode No Data No Data Activate No Data No Data No Data No Data
NextData SameData SameData SameData SameData SameData SameData SameData
Int Trig No Int No Int No Int No Int No Int No Int No Int
IF/Wait Wait 4 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
Term A
LFUNC
Term B
Branch1
Branch0
Reexecute
CTL0 11011111
CTL1 11111111
CTL2 11111111
CTL3 11111111
CTL4 11111111
CTL5 11111111
154 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Figure 10-33. FIFO Read Transaction Functions
#define GPIFTRIGRD 4
#define GPIF_EP2 0
#define GPIF_EP4 1
#define GPIF_EP6 2
#define GPIF_EP8 3
#define BURSTMODE 0x0000
#define HSPKTSIZE 512
… … … … …
// reads from PERIPHERAL, using GPIF and EPxFIFO
void Peripheral_FIFORead( BYTE FIFO_EpNum )
{
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
{
;
}
// trigger FIFO read transactions, using SFR
GPIFTRIG = GPIFTRIGRD | FIFO_EpNum; // R/W=1, EP[1:0]=FIFO_EpNum
// for EPx reads
}
// Set GPIF Transaction Count
void Peripheral_SetGPIFTC( WORD xfrcnt)
{
GPIFTCB1 = xfrcnt >> 8; // setup transaction count
SYNCDELAY;
GPIFTCB0 = ( BYTE )xfrcnt;
}
… … … … …
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 155
General Programmable Interface
Figure 10-34. Initialization Code for FIFO Read Transactions
Figure 10-35. FIFO Read w/ AUTOIN = 0, Committing Packets via INPKTEND w/SKIP=0
void TD_Init( void )
{
… … … … …
GpifInit(); // Configures GPIF from GPIF Designer generated waveform data
// TODO: configure other endpoints, etc. here
EP8CFG = 0xE0; // EP8 is DIR=IN, TYPE=BULK
SYNCDELAY;
EP8FIFOCFG = 0x04; // EP8 is AUTOOUT=0, AUTOIN=0, ZEROLEN=1, WORDWIDE=0
// TODO: arm OUT buffers here
// setup INT4 as internal source for GPIF interrupts
// using INT4CLR (SFR), automatically enabled
// INTSETUP |= 0x03; //Enable INT4 Autovectoring
// SYNCDELAY;
// GPIFIE = 0x03; // Enable GPIFDONE and GPIFWF interrupts
// SYNCDELAY;
// EIE |= 0x04; // Enable INT4 ISR, EIE.2(EIEX4)=1
// TODO: configure GPIF interrupts to meet your needs here
… … … … …
// tell peripheral we are going into high speed xfr mode
Peripheral_SetAddress( PERIPHCS );
Peripheral_SingleByteWrite( P_HSMODE );
// configure some GPIF registers
Peripheral_SetAddress( BURSTMODE );
Peripheral_SetGPIFTC( HSPKTSIZE );
}
void TD_Poll( void )
{
… … … … …
if( !( EP68FIFOFLGS & 0x10 ) )
{ // EP8FF=0 when buffer available
// host is taking EP8 data fast enough
Peripheral_FIFORead( GPIF_EP8 );
}
if( gpifdone_event_flag )
{ // GPIF currently pointing to EP8, last FIFO accessed
if( !( EP2468STAT & 0x80 ) )
{ // EP8F=0 when buffer available
INPKTEND = 0x08; // Firmware commits pkt by writing 8 to INPKTEND
gpifdone_event_flag = 0;
}
}
… … … … …
}
156 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Figure 10-36. FIFO Read w/ AUTOIN = 0, Committing Packets through EPxBCL
10.4.6 Firmware Access to IN Packets,
(AUTOIN=1)
The only difference between auto (AUTOIN=1) and manual
(AUTOIN=0) modes for IN packets is the packet length fea-
ture (EPxAUTOINLENH/L) in AUTOIN=1.
Figure 10-37. GPIF FIFO Read Transactions, AUTOIN = 1
Figure 10-38. FIFO Read Transaction Code, AUTOIN = 1
void TD_Poll( void )
{
… … … … …
if( !( EP68FIFOFLGS & 0x10 ) )
{ // EP8FF=0 when buffer available
// host is taking EP8 data fast enough
Peripheral_FIFORead( GPIF_EP8 );
}
if( gpifdone_event_flag )
{ // GPIF currently pointing to EP8, last FIFO accessed
if( !( EP2468STAT & 0x80 ) )
{ // EP8F=0 when buffer available
// modify the data
EP8FIFOBUF[ 0 ] = 0x02; // <STX>, packet start of text msg
EP8FIFOBUF[ 7 ] = 0x03; // <ETX>, packet end of text msg
SYNCDELAY;
EP8BCH = 0x00;
SYNCDELAY;
EP8BCL = 0x08; // pass 8-byte packet on to host
}
}
… … … … …
}
Data Path
8051
USB
Host Slave Peripheral
AUTOIN=1, Long Transfer Mode
GPIF
void TD_Init( void )
{
EP8CFG = 0xE0; // EP8 is DIR=IN, TYPE=BULK
SYNCDELAY;
EP8FIFOCFG = 0x0C; // EP8 is AUTOOUT=0, AUTOIN=1, ZEROLEN=1, WORDWIDE=0
SYNCDELAY;
EP8AUTOINLENH = 0x02; // if AUTOIN=1, auto commit 512 byte packets
SYNCDELAY;
EP8AUTOINLENL = 0x00;
}
void TD_Poll( void )
{
// no code necessary to xfr data from master to host!
// AUTOIN=1 and EP8AUTOINLENH:L=512 auto commits IN packets,
// in 512 byte chunks.
}
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 157
General Programmable Interface
Figure 10-39. Firmware Intervention, AUTOIN = 0/1 10.4.7 Firmware Access to IN Packets,
(AUTOIN = 0)
In manual IN mode (AUTOIN=0), the firmware has the fol-
lowing options:
1. It can commit (‘pass-on’) packets sent from the master to
the host when a buffer is available, by writing the INPK-
TEND register with the corresponding EPx number and
SKIP = 0 (see Figure 10-40).
2. It can skip a packet by writing to INPKTEND with
SKIP = 1. See Figure 10-41 on page 157.
3. It can source or edit a packet (for example, write directly
to EPxFIFOBUF) then write the EPxBCL. See
Figure 10-42 on page 158.
Figure 10-40. Committing a Packet by Writing INPKTEND with EPx Number (w/SKIP = 0)
Figure 10-41. Skipping a Packet by Writing to INPKTEND w/SKIP = 1
8051
USB
Host Peripheral
AUTOIN=0 or
AUTOIN=1
Slave GPIF
Data Path
TD_Poll():
… … … … …
if( master_finished_longxfr( ) )
{ // master currently points to EP8, last FIFO accessed
if( !( EP68FIFOFLGS & 0x10 ) )
{ // EP8FF=0 when buffer available
INPKTEND = 0x08; // Firmware commits pkt
// by writing 0x08 to INPKTEND
release_master( EP8 );
}
}
… … … … …
TD_Poll():
… … … … …
if( master_finished_longxfr( ) )
{ // master currently points to EP8, last FIFO accessed
if( !( EP68FIFOFLGS & 0x10 ) )
{ // EP8FF=0 when buffer available
INPKTEND = 0x88; // Firmware commits pkt
// by writing 0x88 to INPKTEND
release_master( EP8 );
}
}
… … … … …
158 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Figure 10-42. Sourcing an IN Packet by Writing to EPxBCH:L
TD_Poll():
… … … … …
if( source_pkt_event )
{ // 100msec background timer fired
if( holdoff_master( ) )
{ // signaled “busy” to master successful
while( !( EP68FIFOFLGS & 0x20 ) )
{ // EP8EF=0, when buffer not empty
; // wait ‘til host takes entire FIFO data
}
// Reset FIFO 8.
FIFORESET = 0x80; // Activate NAK-All to avoid race conditions.
SYNCDELAY;
FIFORESET = 0x88; // Reset FIFO 8.
SYNCDELAY;
FIFORESET = 0x00; // Deactivate NAK-All.
EP8FIFOBUF[ 0 ] = 0x02; // <STX>, packet start of text msg
EP8FIFOBUF[ 1 ] = 0x06; // <ACK>
EP8FIFOBUF[ 2 ] = 0x07; // <HEARTBEAT>
EP8FIFOBUF[ 3 ] = 0x03; // <ETX>, packet end of text msg
SYNCDELAY;
EP8BCH = 0x00;
SYNCDELAY;
EP8BCL = 0x04; // pass src’d buffer on to host
}
else
{
history_record( EP8, BAD_MASTER );
}
}
… … … … …
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 159
General Programmable Interface
10.4.7.1 Performing a FIFO-Write Transaction
Figure 10-43. Firmware Launches a FIFO Write Waveform
Figure 10-44. Example FIFO Write Transaction
EPxEF
FIFOADR[1:0]
Slave FIFOs
8051 Device Pins
EPxFF
EPxPF
SLOE
SLRD
SLWR
INPKTEND
IFCLK
FD[7:0]
EP4FIFOBUF
EP6FIFOBUF
EP8FIFOBUF
EP2FIFOBUF
EP8
EP6
EP4
EP2
GPIF
GPIF
8051
CTL[5:0]
RDY[5:0]
GPIFADR[8:0]
GPIF INTRDY
8051 INTRDY
30/48MHz
CLK
5 - 48MHz
XDATA
Waveform Descriptors
WF3
WF2
WF1
WF0
GPIF DONE
GPIFTRIG
i2
…
…
0x01 Peripheral data (Pdata)
0x01 0x02 0x03 0xFF
NN+1 N+2 512
TC=N
TC=N+1
TC=N+2
TC=512
0x02
0x03
0xFF
EPxFIFOBUF
…
…
GPIF TC
i2 i2 i2
…
160 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Figure 10-45. FIFO Write Transaction Waveform
The above waveform executes until the Transaction Counter
expires (until it counts to 512, in this example). The Transac-
tion Counter is decremented and sampled on each pass
through the Idle State. When the Transaction Counter is
used without passing through the IDLE state, the Transac-
tion Counter is decremented on each ‘Nextdata’ (which
increments the FIFO pointer).
Each iteration of the waveform writes a data value from the
FIFO to the FIFO Data bus, then decrements and checks
the Transaction Counter. When it expires, the DONE bit is
set to ‘1’ and the GPIFDONE interrupt request is asserted.
Figure 10-46. GPIF Designer Setup for the Waveform of Figure 10-45
hi-Z
0x0000
hi-Z Pdata++
IFCLK
GPIFADR[8:0]
CTL0
RDY0
FD[7:0]
NDPNDP NDP
– I1 NDP
i3i2i1
NDP
i4
NDP
drive databus here increment FIFO pointer here
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 161
General Programmable Interface
Figure 10-47. GPIF Designer Output for the Waveform of Figure 10-45
Typically, when performing a FIFO Write, only one ‘Next-
Data’ is needed in the waveform, since each execution of
‘NextData’ increments the FIFO pointer.
To perform a FIFO-Write Transaction:
1. Program the EZ-USB to detect completion of the trans-
action. As with all GPIF Transactions, bit 7 of the
GPIFTRIG register (the DONE bit) signals when the
Transaction is complete.
2. In the GPIFTRIG register, set the RW bit to ‘0’ and load
EP[1:0] with the appropriate value for the FIFO which is
to source the data.
3. Program the EZ-USB to commit (‘pass-on’) the data from
the endpoint to the FIFO. The data can be transferred by
either of the following methods:
❐AUTOOUT=1: CPU is not in the data path; the EZ-
USB automatically commits data from the USB to the
FIFO Data bus.
❐AUTOOUT=0: Firmware must manually commit data
to the FIFO Data bus by writing
EPxBCL.7=0 (firmware can choose to skip the cur-
rent packet by writing EPxBCL.7=1).
The following C program fragments (Figure 10-48 on
page 162 through Figure 10-50 on page 163) illustrate how
to perform a FIFO-Read transaction in 8 bit mode (WORD-
WIDE = 0) with AUTOOUT = 0.
State 01234567
AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
DataMode No Data No Data Activate No Data No Data No Data No Data
NextData SameData SameData SameData SameData SameData SameData NextData
Int Trig No Int No Int No Int No Int No Int No Int No Int
IF/Wait Wait 4 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
Term A
LFUNC
Term B
Branch1
Branch0
Re-execute
CTL0 11011111
CTL1 11111111
CTL2 11111111
CTL3 11111111
CTL4 11111111
CTL5 11111111
162 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Figure 10-48. FIFO Write Transaction Functions
#define GPIFTRIGWR 0
#define GPIF_EP2 0
#define GPIF_EP4 1
#define GPIF_EP6 2
#define GPIF_EP8 3
#define BURSTMODE 0x0000
#define HSPKTSIZE 512
… … … … …
// write bytes to PERIPHERAL, using GPIF and EPxFIFO
void Peripheral_FIFOWrite( BYTE FIFO_EpNum )
{
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
{
;
}
// trigger FIFO write transactions, using SFR
GPIFTRIG = FIFO_EpNum; // R/W=0, EP[1:0]=FIFO_EpNum for EPx writes
}
// Set GPIF Transaction Count
void Peripheral_SetGPIFTC( WORD xfrcnt)
{
GPIFTCB1 = xfrcnt >> 8; // setup transaction count
SYNCDELAY;
GPIFTCB0 = ( BYTE )xfrcnt;
}
… … … … …
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 163
General Programmable Interface
Figure 10-49. Initialization Code for FIFO Write Transactions
Figure 10-50. FIFO Write w/ AUTOOUT = 0, Committing Packets through OUTPKTEND
void TD_Init( void )
{
… … … … …
GpifInit(); // Configures GPIF from GPIF Designer generated waveform data
// TODO: configure other endpoints, etc. here
EP2CFG = 0xA2; // EP2 is DIR=OUT, TYPE=BULK, SIZE=512, BUF=2x
SYNCDELAY;
EP2FIFOCFG = 0x00; // EP2 is AUTOOUT=0, AUTOIN=0, ZEROLEN=0, WORDWIDE=0
SYNCDELAY;
// “all” EP2 buffers automatically arm when AUTOOUT=1
// TODO: arm OUT buffers here
OUTPKTEND = 0x82; // Arm both EP2 buffers to “prime the pump”
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
// setup INT4 as internal source for GPIF interrupts
// using INT4CLR (SFR), automatically enabled
// INTSETUP |= 0x03; //Enable INT4 Autovectoring
// GPIFIE = 0x03; // Enable GPIFDONE and GPIFWF interrupts
// EIE |= 0x04; // Enable INT4 ISR, EIE.2(EIEX4)=1
// TODO: configure GPIF interrupts to meet your needs here
… … … … …
// tell peripheral we are going into high speed xfr mode
Peripheral_SetAddress( PERIPHCS );
Peripheral_SingleByteWrite( P_HSMODE );
// configure some GPIF control registers
Peripheral_SetAddress( BURSTMODE );
}
void TD_Poll( void )
{
… … … … …
if( !( EP2468STAT & 0x01 ) )
{ // EP2EF=0 when FIFO “not” empty, host sent pkt.
OUTPKTEND = 0x02; // SKIP=0, pass buffer on to master
if( gpifdone_event_flag )
{
Peripheral_SetGPIFTC( HSPKTSIZE );
Peripheral_FIFOWrite( GPIF_EP2 );
gpifdone_event_flag = 0;
}
}
… … … … …
}
164 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
10.4.8 Firmware Access to OUT packets,
(AUTOOUT=1)
To achieve the maximum USB 2.0 bandwidth, the host and
master are directly connected when AOUTOOUT=1; the
CPU is bypassed and the OUT FIFO is automatically com-
mitted to the host.
Figure 10-51. CPU Not in Data Path, AUTOOUT=1
Figure 10-52. TD_Init Example: Configuring AUTOOUT = 1
Figure 10-53. FIFO-Write Transaction Code, AUTOOUT = 1
Data Path
8051
USB
Host Peripheral
AUTOOUT=1, Long Transfer Mode
Slave GPIF
TD_Init():
… … … … …
REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1
SYNCDELAY;
EP2CFG = 0xA2; // EP2 is DIR=OUT, TYPE=BULK, SIZE=512, BUF=2x
SYNCDELAY;
FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;
FIFORESET = 0x82;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
OUTPKTEND = 0x82; // Arm both EP2 buffers to “prime the pump”
SYNCDELAY;
OUTPKTEND = 0x82;
SYNCDELAY;
EP2FIFOCFG = 0x10; // EP2 is AUTOOUT=1, AUTOIN=0, ZEROLEN=0, WORDWIDE=0
… … … … …
TD_Poll():
… … … … …
// no code necessary to xfr data from host to master!
// AUTOOUT=1 auto-commits packets
… … … … …
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 165
General Programmable Interface
10.4.9 Firmware Access to OUT Packets, (AUTOOUT = 0)
Figure 10-54. Firmware can Skip or Commit, AUTOOUT = 0
Figure 10-55. Initialization Code for AUTOOUT = 0
In manual OUT mode (AUTOOUT = 0), the firmware has the
following options:
■It can commit (‘pass on’) packets sent from the host to
the master when a buffer is available, by writing the
OUTPKTEND register with the SKIP bit (OUTPK-
TEND.7) cleared to ‘0’ (see Figure 10-56) and the end-
point number in EP[3:0].
■It can skip packets sent from the host to the master by
writing the OUTPKTEND register with the SKIP bit
(OUTPKTEND.7) set to ‘1’ (see Figure 10-57) and the
endpoint number in EP[3:0].
Figure 10-56. Committing an OUT Packet by Writing OUTPKTEND w/SKIP=0
TD_Init():
… … … … …
REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1
SYNCDELAY;
EP2CFG = 0xA2; // EP2 is DIR=OUT, TYPE=BULK, SIZE=512, BUF=2x
SYNCDELAY;
FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;
FIFORESET = 0x82;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP2FIFOCFG = 0x00; // EP2 is AUTOOUT=0, AUTOIN=0, ZEROLEN=0, WORDWIDE=0
SYNCDELAY;
// OUT endpoints do NOT come up armed
OUTPKTEND = 0x82; // arm first buffer by writing OUTPKTEND w/skip=1
SYNCDELAY;
OUTPKTEND = 0x82; // arm second buffer by writing OUTPKTEND w/skip=1
… … … … …
Data
8051
USB
Host Peripheral
AUTOOUT=0
skip=0
skip=1
Slave GPIF
TD_Poll():
… … … … …
if( !( EP24FIFOFLGS & 0x02 ) )
{ // EP2EF=0 when FIFO “not” empty, host sent pkt.
OUTPKTEND = 0x02; // SKIP=0, pass buffer on to master
}
… … … … …
166 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
Figure 10-57. Skipping an OUT Packet by Writing OUTPKTEND w/SKIP=1
■It can edit the packet (or source an entire OUT packet)
by writing to the FIFO buffer directly, then writing the
length of the packet to EPxBCH:L. The write to EPxBCL
commits the edited packet, so EPxBCL should be written
after writing EPxBCH (Figure 10-58).
In all cases, the OUT buffer automatically re-arms so it can
receive the next packet, after the GPIF has transmitted all
data in the OUT buffer.
See section 8.6.2.4 EP2BCH:L, EP4BCH:L, EP6BCH:L,
EP8BCH:L on page 93 for a detailed description of the SKIP
bit.
The master is not notified when a packet has been skipped
by the firmware.
The OUT FIFO is not committed to the host after a hard
reset. This means that it is not available to initially accept
any OUT packets. In its initialization routine, therefore, the
firmware should skip n packets (where n = 2, 3, or 4 depend-
ing on the buffering depth) in order to ensure that the entire
FIFO is committed to the host. See Figure 10-59 on
page 167.
Figure 10-58. Sourcing an OUT Packet (AUTOOUT = 0)
TD_Poll():
… … … … …
if( !( EP24FIFOFLGS & 0x02 ) )
{ // EP2EF=0 when FIFO “not” empty, host sent pkt.
OUTPKTEND = 0x82; // SKIP=1, do NOT pass buffer on to master
}
… … … … …
TD_Poll():
… … … … …
if( EP24FIFOFLGS & 0x02 )
{
SYNCDELAY; //
FIFORESET = 0x80; // nak all OUT pkts. from host
SYNCDELAY; //
FIFORESET = 0x82; // advance all EP2 buffers to cpu domain
SYNCDELAY; //
EP2FIFOBUF[0] = 0xAA; // create newly sourced pkt. data
SYNCDELAY; //
EP2BCH = 0x00;
SYNCDELAY; //
EP2BCL = 0x01; // commit newly sourced pkt. to interface fifo
// beware of “left over” uncommitted buffers
SYNCDELAY; //
OUTPKTEND = 0x82; // skip uncommitted pkt. (second pkt.)
// note: core does not allow pkts. to get out of sequence
SYNCDELAY; //
FIFORESET = 0x00; // release “nak all”
}
… … … … …
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 167
General Programmable Interface
Figure 10-59. Ensuring that the FIFO is Clear after a Hard Reset
10.5 UDMA Interface
The EZ-USB has additional GPIF registers specifically for
implementing a UDMA (Ultra-ATA) interface. For more infor-
mation, refer to the Registers chapter on page 211.
10.6 ECC Generation
The EZ-USB has additional registers specifically for imple-
menting ECC based on the SmartMedia™ standard. For
more information, refer to the Registers chapter on
page 211.
TD_Init():
… … … … …
REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1
SYNCDELAY;
EP2CFG = 0xA2; // EP2 is DIR=OUT, TYPE=BULK, SIZE=512, BUF=2x
SYNCDELAY;
FIFORESET = 0x80; // Reset the FIFO
SYNCDELAY;
FIFORESET = 0x82;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP2FIFOCFG = 0x00; // EP2 is AUTOOUT=0, AUTOIN=0, ZEROLEN=0, WORDWIDE=0
SYNCDELAY;
// OUT endpoints do NOT come up armed
OUTPKTEND = 0x82; // arm first buffer by writing OUTPKTEND w/skip=1
SYNCDELAY;
OUTPKTEND = 0x82; // arm second buffer by writing OUTPKTEND w/skip=1
… … … … …
168 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
General Programmable Interface
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 169
11. CPU Introduction
11.1 Introduction
The EZ-USB’s CPU, an enhanced 8051, is fully described in chapters Instruction Set, on page 175, Input/Output, on
page 181, and Timers/Counters and Serial Interface, on page 193. This chapter introduces the processor, its interface to the
EZ-USB logic, and describes architectural differences from a standard 8051. Figure 11-1 is a block diagram of the EZ-USB’s
8051-based CPU.
Figure 11-1. EZ-USB CPU Features
8-bit CPU
Oscillator
Crystal
Register
RAM
(256 bytes) Serial Port0 Timer0
Serial Port1
Timer1
Timer2
Bus Control Interrupt
Control I/O Ports*
* The EZ-USB family implements I/O ports differently than in the standard 8051
170 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
CPU Introduction
11.2 8051 Enhancements
The EZ-USB uses the standard 8051 instruction set, so it is
supported by industry-standard 8051 compilers and assem-
blers. Instructions execute faster on the EZ-USB than on the
standard 8051.
■Wasted bus cycles are eliminated; an instruction cycle
uses only four clocks, rather than the standard 8051’s 12
clocks
■The EZ-USB’s CPU clock runs at 12 MHz, 24 MHz, or 48
MHz—up to four times the clock speed of the standard
8051
In addition to speed improvements, the EZ-USB includes the
following architectural enhancements to the CPU.
■A second data pointer
■A second USART
■A third, 16 bit timer (TIMER2)
■A high-speed external memory interface with a non-mul-
tiplexed 16 bit address bus
■Eight additional interrupts (INT2-INT6, WAKEUP, T2,
and USART1)
■Variable MOVX timing to accommodate fast and slow
RAM peripherals
■Two Autopointers (auto-incrementing data pointers)
■Vectored USB and FIFO/GPIF interrupts
■Baud rate timer for 115K/230K baud USART operation
■Sleep mode with three wakeup sources
■An I2C™ bus controller that runs at 100 or 400 kHz
■EZ-USB specific SFRs
■Separate buffers for the SETUP and DATA portions of a
USB CONTROL transfer
■A hardware pointer for SETUP data, plus logic to pro-
cess entire CONTROL transfers automatically
■CPU clock-rate selection of 12, 24 or 48 MHz
■Breakpoint facility
■I/O Port C read and write strobes
11.3 Performance Overview
The EZ-USB has been designed to offer increased perfor-
mance by executing instructions in a 4-clock bus cycle, as
opposed to the 12-clock bus cycle in the standard 8051 (see
Figure 11-2 on page 171). This shortened bus timing
improves the instruction execution rate for most instructions
by a factor of three over the standard 8051 architectures.
Some instructions require a different number of instruction
cycles on the EZ-USB than they do on the standard 8051. In
the standard 8051, all instructions except for MUL and DIV
take one or two instruction cycles to complete. In the EZ-
USB, instructions can take between one and five instruction
cycles to complete. However, due to the shortened bus tim-
ing of the EZ-USB, every instruction executes faster than on
a standard 8051, and the average speed improvement over
the entire instruction set is approximately 2.5×. Table 11-1
catalogs the speed improvements.
Table 11-1. EZ-USB Speed Compared to Standard 8051**
Of the 246 EZ-USB opcodes...
150 execute at 3.0× standard speed
51 execute at 1.5× standard speed
43 execute at 2.0× standard speed
2 execute at 2.4× standard speed
Average Improvement: 2.5×
** Comparison is between EZ-USB and standard 8051 running at the same
clock frequency.
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 171
CPU Introduction
Figure 11-2. EZ-USB to Standard 8051 Timing Comparison
11.4 Software Compatibility
The EZ-USB is object code compatible with the industry
standard 8051 microcontroller. That is, object code compiled
with an industry standard 8051 compiler or assembler exe-
cutes on the EZ-USB and is functionally equivalent. How-
ever, because the EZ-USB uses a different instruction timing
than the standard 8051, existing code with timing loops may
require modification.
The EZ-USB instruction timing is identical to that of the Dal-
las Semiconductor DS80C320.
11.5 803x/805x Feature
Comparison
Table 11-2 provides a feature-by-feature comparison
between the EZ-USB and several common 803x/805x
devices.
PSEN
ALE
XTAL1
AD0-AD7
PSEN
PORT2
EZ-USB
Standard
PORT2
Single-Byte, Single-Cycle Instruction Timing
AD0-AD7
4
12
8051
Table 11-2. Comparison Between EZ-USB and Other 803x/805x Devices
Feature Intel Dallas DS80C320 Cypress
EZ-USB
8031 8051 80C32 80C52
Clocks per instruction cycle 12 12 12 12 4 4
Program / Data Memory - 4 kB ROM - 8 kB ROM - 16 kB RAM
Internal RAM 128 bytes 128 bytes 256 bytes 256 bytes 256 bytes 256 bytes
Data Pointers 1111 2 2
Serial Ports 1111 2 2
16-bit Timers 2233 3 3
Interrupt sources (internal and external) 5566 13 13
Stretch data-memory cycles no no no no yes yes
172 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
CPU Introduction
11.6 EZ-USB/DS80C320
Differences
Although the EZ-USB is similar to the DS80C320 in terms of
hardware features and instruction cycle timing, there are
some important differences between the EZ-USB and the
DS80C320.
11.6.1 Serial Ports
The EZ-USB does not implement serial port framing-error
detection and does not implement slave address compari-
son for multiprocessor communications. Therefore, the EZ-
USB also does not implement the following SFRs: SADDR0,
SADDR1, SADEN0, and SADEN1.
11.6.2 Timer 2
The EZ-USB does not implement Timer 2 downcounting
mode or the downcount enable bit (TMOD2, Bit 0). Also, the
EZ-USB does not implement Timer 2 output enable (T2OE)
bit (TMOD2, Bit 1). Therefore, the TMOD2 SFR is also not
implemented in the EZ-USB.
The EZ-USB Timer 2 overflow output is active for one clock
cycle. In the DS80C320, the Timer 2 overflow output is a
square wave with a 50% duty cycle.
Note Although the T2OE bit is not present in the EZ-USB,
Timer 2 output can still be enabled or disabled via the
PORTECFG.2 bit, since the T2OUT pin is multiplexed with
PORTE.2.
PORTECFG.2 = 0 configures the pin as a general-purpose I/
O pin and disabled Timer 2 output.
PORTECFG.2 = 1 configures the pin as the T2OUT pin and
enables Timer 2 output.
11.6.3 Timed Access Protection
The EZ-USB does not implement timed access protection
and, therefore, does not implement the TA SFR.
11.6.4 Watchdog Timer
The EZ-USB does not implement a watchdog timer.
11.6.5 Power Fail Detection
The EZ-USB does not implement a power fail detection cir-
cuit.
11.6.6 Port I/O
The EZ-USB’s port I/O implementation is significantly differ-
ent from that of the DS80C320, mainly because of the alter-
nate functions shared with most of the I/O pins. See Input/
Output, on page 181.
11.6.7 Interrupts
Although the basic interrupt structure of the EZ-USB is simi-
lar to that of the DS80C320, five of the interrupt sources are
different:
For more information, refer to the Timers/Counters and
Serial Interface chapter on page 193.
11.7 EZ-USB Register Interface
The EZ-USB peripheral logic (USB, GPIF, FIFOs, and oth-
ers) is controlled via a set of memory mapped registers and
buffers at addresses 0xE400 through 0xFFFF. These regis-
ters and buffers are grouped as follows:
■GPIF Waveform Descriptor Tables
■General configuration
■Endpoint configuration
■Interrupts
■Input/Output
■USB Control
■Endpoint operation
■GPIF/FIFOs
■Endpoint buffers
These registers and their functions are described throughout
this manual. A full description of every EZ-USB register
appears in the Registers chapter on page 211.
11.8 EZ-USB Internal RAM
Figure 11-3. EZ-USB Internal Data RAM
Table 11-3. Differences between EZ-USB and DS80C320
Interrupts
Interrupt
Priority Dallas DS80C320 Cypress EZ-USB
0 Power Fail RESUME (USB Wakeup)
8 External Interrupt 2 USB
9 External Interrupt 3 I²C Bus
10 External Interrupt 4 GPIF/FIFOs
12 Watchdog Timer External Interrupt 6
Lower 128
Direct Addr
SFR Space
Direct Addr
Upper 128
Indirect Addr
0x00
0x7F
0x80
0xFF
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 173
CPU Introduction
Like the standard 8051, the EZ-USB contains 128 bytes of
Internal Data RAM at addresses 0x00-0x7F and a partially
populated SFR space at addresses 0x80-0xFF. An addi-
tional 128 indirectly-addressed bytes of Internal Data RAM
(sometimes called ‘IDATA’) are also available at addresses
0x80-0xFF.
All other on-chip EZ-USB RAM (program/data memory, end-
point buffer memory, and the EZ-USB control registers) is
addressed as though it were off-chip 8051 memory. EZ-USB
firmware reads or writes these bytes as data using the
MOVX (‘move external’) instruction, even though the EZ-
USB RAM and register set is actually inside the EZ-USB
chip. Off-chip memory attached to the EZ-USB address and
data buses (only offered in the 128-pin packages) can also
be accessed by the MOVX instruction. EZ-USB logic
encodes its memory strobe and select signals (RD#, WR#,
CS#, OE#, and PSEN#) to eliminate the need for external
logic to separate the on-chip and off-chip memory spaces;
see the Memory chapter on page 71.
11.9 I/O Ports
The EZ-USB implements I/O ports differently than a
standard 8051, as described in Input/Output, on page 181.
The EZ-USB has up to five 8 bit wide, bidirectional I/O ports.
Each port is associated with a pair of registers.
■An ‘OEx’ register. It sets the input/output direction of
each of the 8 port pins (0 = input, 1 = output).
■An ‘IOx’ register. Values written to IOx appear on the
pins configured as outputs; values read from IOx indi-
cate the states of the 8 pins, regardless of input/output
configuration.
Most I/O pins have alternate functions which are selected
using configuration registers. When an alternate configura-
tion is selected for an I/O pin, the corresponding OEx bit is
ignored (see section 13.2 I/O Ports on page 181). The
default (power on reset) state of all I/O ports is: alternate
configurations ‘off’, all I/O pins configured as ‘inputs’.
11.10 Interrupts
All standard 8051 interrupts, plus additional interrupts, are
supported by the EZ-USB. Table 11-4 lists the EZ-USB inter-
rupts.
The EZ-USB uses INT2 for 27 different USB interrupts. To
help determine which interrupt is active, the EZ-USB pro-
vides a feature called Autovectoring, which dynamically
changes the address pointed to by the ‘jump’ instruction at
the INT2 vector address. This second level of vectoring
automatically transfers control to the appropriate USB inter-
rupt service routine (ISR). The EZ-USB interrupt system,
including a full description of the Autovector mechanism, is
the subject of the Interrupts chapter on page 59.
11.11 Power Control
The EZ-USB implements a low power mode that allows it to
be used in USB bus powered devices (which are required by
the USB specification to draw no more than 500 A when
suspended) and other low power applications. The mecha-
nism by which the EZ-USB enters and exits this low power
mode is described in detail in the Power
Management chapter on page 77.
Table 11-4. EZ-USB Interrupts
Standard
8051
Interrupts
Additional
EZ-USB
Interrupts Source
INT0 Pin PA0 / INT0#
INT1 Pin PA1 / INT1#
Timer 0 Internal, Timer 0
Timer 1 Internal, Timer 1
Tx0 & Rx0 Internal, USART0
INT2 Internal, USB
INT3 Internal, I²C Bus Controller
INT4 Pin INT4 (100 and 128 pin only) OR Internal,
GPIF/FIFOs
INT5 Pin INT5# (100 and 128 pin only)
INT6 Pin INT6 (100 and 128 pin only)
WAKEUP Pin WAKEUP or Pin RA3/WU2
Tx1 & Rx1 Internal, USART1
Timer 2 Internal, Timer 2
174 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
CPU Introduction
11.12 Special Function Registers
The EZ-USB was designed to keep coding as standard as possible, to allow easy integration of existing 8051 software devel-
opment tools. The EZ-USB Special Function Registers (SFR) are summarized in Table 11-5. Standard 8051 SFRs are shown
in normal type and EZ-USB-added SFRs are shown in bold type. Full details of the SFRs can be found in the
Registers chapter on page 211.
Note All unlabeled SFRs are reserved.
11.13 External Address/Data
Buses
The 128-pin version of the EZ-USB provides external, non-
multiplexed 16-bit address and 8 bit data buses. This differs
from the standard 8051, which multiplexes eight pins among
three sources: I/O port 0, the external data bus, and the low
byte of the external address bus.
A standard 8051 system with external memory requires a
demultiplexing address latch, strobed by the 8051 ALE
(Address Latch Enable) pin. The external latch is not
required by the EZ-USB chip, and no ALE signal is provided.
In addition to eliminating the need for this external latch, the
non-multiplexed EZ-USB bus saves one cycle per memory-
fetch and allows external memory to be connected without
sacrificing I/O pins.
The EZ-USB is the sole master of the bus, providing read
and write signals to the off-chip memory. The address bus is
output-only, and cannot be floated.
11.14 Reset
The various EZ-USB resets and their effects are described
in the Resets chapter on page 83.
Table 11-5. EZ-USB Special Function Registers (SFR)
x8x 9x Ax Bx Cx Dx Ex Fx
0IOA IOB IOC IOD SCON1 PSW ACC B
1SP EXIF INT2CLR IOE SBUF1
2DPL0 MPAGE INT4CLR OEA
3DPH0 OEB
4DPL1 OEC
5DPH1 OED
6DPS OEE
7PCON
8 TCON SCON0 IE IP T2CON EICON EIE EIP
9TMOD SBUF0
ATL0 AUTOPTRH1 EP2468STAT EP01STAT RCAP2L
BTL1 AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H
CTH0 EP68FIFOFLGS TL2
DTH1AUTOPTRH2 GPIFSGLDATH TH2
ECKCON AUTOPTRL2 GPIFSGLDATLX
FAUTOPTRSETUP GPIFSGLDATLNOX
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 175
12. Instruction Set
12.1 Introduction
This chapter provides a technical overview and description of the EZ-USB’s assembly-language instruction set.
All EZ-USB instructions are binary code compatible with the standard 8051. The EZ-USB instructions affect bits, flags, and
other status functions just as the 8051 instructions do. Instruction timing, however, is different both in terms of the number of
clock cycles per instruction cycle and the number of instruction cycles used by each instruction.
Table 12-2 on page 176 lists the EZ-USB instruction set and the number of instruction cycles required to complete each
instruction. Table 12-1 defines the symbols and mnemonics used in Table 12-2.
Table 12-1. Legend for Instruction Set Table
Symbol Function
A Accumulator
Rn Register (R0–R7, in the bank selected by RS1:RS0)
direct Internal RAM location (0x00-0x7F in the ‘Lower 128’, or 0x80-0xFF in ‘SFR’ space)
@Ri Internal RAM location (0x00-0x7F in the ‘Lower 128’, or 0x80-0xFF in the ‘Upper 128’) pointed to by R0 or R1
rel Program-memory offset (-128 to +127 bytes relative to the first byte of the following instruction). Used by conditional jumps and SJMP.
bit Bit address (0x20-x2F in the ‘Lower 128,’ and SFRs 0x80, 0x88, …, 0xF0, 0xF8)
#data 8-bit constant (0-255)
#data16 16-bit constant (0-65535)
addr16 16-bit destination address; used by LCALL and LJMP, which branch anywhere in program memory
addr11 11-bit destination address; used by ACALL and AJMP, which branch only within the current 2K page of program memory (i.e., the upper 5
address bits are copied from the PC)
PC Program Counter; holds the address of the currently-executing instruction. For the purposes of ‘ACALL’, ‘AJMP’, and ‘MOVC A,@A+PC’
instructions, the PC holds the address of the first byte of the instruction following the currently-executing instruction.
176 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Instruction Set
Table 12-2. EZ-USB Instruction Set
Mnemonic Description Bytes Cycles PSW Flags Affected Opcode (Hex)
Arithmetic
ADD A, Rn Add register to A 1 1 CY OV AC 28-2F
ADD A, direct Add direct byte to A 2 2 CY OV AC 25
ADD A, @Ri Add data memory to A 1 1 CY OV AC 26-27
ADD A, #data Add immediate to A 2 2 CY OV AC 24
ADDC A, Rn Add register to A with carry 1 1 CY OV AC 38-3F
ADDC A, direct Add direct byte to A with carry 2 2 CY OV AC 35
ADDC A, @Ri Add data memory to A with carry 1 1 CY OV AC 36-37
ADDC A, #data Add immediate to A with carry 2 2 CY OV AC 34
SUBB A, Rn Subtract register from A with borrow 1 1 CY OV AC 98-9F
SUBB A, direct Subtract direct byte from A with borrow 2 2 CY OV AC 95
SUBB A, @Ri Subtract data memory from A with borrow 1 1 CY OV AC 96-97
SUBB A, #data Subtract immediate from A with borrow 2 2 CY OV AC 94
INC A Increment A 1 1 04
INC Rn Increment register 1 1 08-0F
INC direct Increment direct byte 2 2 05
INC @ Ri Increment data memory 1 1 06-07
DEC A Decrement A 1 1 14
DEC Rn Decrement Register 1 1 18-1F
DEC direct Decrement direct byte 2 2 15
DEC @Ri Decrement data memory 1 1 16-17
INC DPTR Increment data pointer 1 3 A3
MUL AB Multiply A and B (unsigned; product in B:A) 1 5 CY=0 OV A4
DIV AB Divide A by B
(unsigned; quotient in A, remainder in B) 15CY=0 OV 84
DA A Decimal adjust A 1 1 CY D4
Logical
ANL, Rn AND register to A 1 1 58-5F
ANL A, direct AND direct byte to A 2 2 55
ANL A, @Ri AND data memory to A 1 1 56-57
ANL A, #data AND immediate to A 2 2 54
ANL direct, A AND A to direct byte 2 2 52
ANL direct, #data AND immediate data to direct byte 3 3 53
ORL A, Rn OR register to A 1 1 48-4F
ORL A, direct OR direct byte to A 2 2 45
ORL A, @Ri OR data memory to A 1 1 46-47
ORL A, #data OR immediate to A 2 2 44
ORL direct, A OR A to direct byte 2 2 42
ORL direct, #data OR immediate data to direct byte 3 3 43
XRL A, Rn Exclusive-OR register to A 1 1 68-6F
XRL A, direct Exclusive-OR direct byte to A 2 2 65
XRL A, @Ri Exclusive-OR data memory to A 1 1 66-67
XRL A, #data Exclusive-OR immediate to A 2 2 64
XRL direct, A Exclusive-OR A to direct byte 2 2 62
XRL direct, #data Exclusive-OR immediate to direct byte 3 3 63
CLR A Clear A 1 1 E4
CPL A Complement A 1 1 F4
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 177
Instruction Set
SWAP A Swap nibbles of a 1 1 C4
RL A Rotate A left 1 1 23
RLC A Rotate A left through carry 1 1 CY 33
RR A Rotate A right 1 1 03
RRC A Rotate A right through carry 1 1 CY 13
Data Transfer
MOV A, Rn Move register to A 1 1 E8-EF
MOV A, direct Move direct byte to A 2 2 E5
MOV A, @Ri Move data byte at Ri to A 1 1 E6-E7
MOV A, #data Move immediate to A 2 2 74
MOV Rn, A Move A to register 1 1 F8-FF
MOV Rn, direct Move direct byte to register 2 2 A8-AF
MOV Rn, #data Move immediate to register 2 2 78-7F
MOV direct, A Move A to direct byte 2 2 F5
MOV direct, Rn Move register to direct byte 2 2 88-8F
MOV direct, direct Move direct byte to direct byte 3 3 85
MOV direct, @Ri Move data byte at Ri to direct byte 2 2 86-87
MOV direct, #data Move immediate to direct byte 3 3 75
MOV @Ri, A MOV A to data memory at address Ri 1 1 F6-F7
MOV @Ri, direct Move direct byte to data memory at address Ri 2 2 A6-A7
MOV @Ri, #data Move immediate to data memory at address Ri 2 2 76-77
MOV DPTR, #data16 Move 16-bit immediate to data pointer 3 3 90
MOVC A, @A+DPTR Move code byte at address DPTR+A to A 1 3 93
MOVC A, @A+PC Move code byte at address PC+A to A 1 3 83
MOVX A, @Ri Move external data at address Ri to A 1 2-9* E2-E3
MOVX A, @DPTR Move external data at address DPTR to A 1 2-9* E0
MOVX @Ri, A Move A to external data at address Ri 1 2-9* F2-F3
MOVX @DPTR, A Move A to external data at address DPTR 1 2-9* F0
PUSH direct Push direct byte onto stack 2 2 C0
POP direct Pop direct byte from stack 2 2 D0
XCH A, Rn Exchange A and register 1 1 C8-CF
XCH A, direct Exchange A and direct byte 2 2 C5
XCH A, @Ri Exchange A and data memory at address Ri 1 1 C6-C7
XCHD A, @Ri Exchange the low-order nibbles of A and data memory at
address Ri 11 D6-D7
* Number of cycles is user-selectable. See Stretch Memory Cycles on page 178.
Boolean
CLR C Clear carry 1 1 CY=0 C3
CLR bit Clear direct bit 2 2 C2
SETB C Set carry 1 1 CY=1 D3
SETB bit Set direct bit 2 2 D2
CPL C Complement carry 1 1 CY B3
CPL bit Complement direct bit 2 2 B2
ANL C, bit AND direct bit to carry 2 2 CY 82
ANL C, /bit AND inverse of direct bit to carry 2 2 CY B0
ORL C, bit OR direct bit to carry 2 2 CY 72
ORL C, /bit OR inverse of direct bit to carry 2 2 CY A0
Table 12-2. EZ-USB Instruction Set (continued)
Mnemonic Description Bytes Cycles PSW Flags Affected Opcode (Hex)
178 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Instruction Set
12.1.1 Instruction Timing
Instruction cycles in the EZ-USB are four clock cycles in
length, as opposed to the 12 clock cycles per instruction
cycle in the standard 8051. For full details of the instruction-
cycle timing differences between the EZ-USB and the stan-
dard 8051, See “Performance Overview” on page 170..
In the standard 8051, all instructions except for MUL and
DIV take one or two instruction cycles to complete. In the
EZ-USB, instructions can take between one and five instruc-
tion cycles to complete. For calculating the timing of soft-
ware loops, etc., use the ‘Cycles’ column from Table 12-2.
The ‘Bytes’ column indicates the number of bytes occupied
by each instruction.
By default, the EZ-USB’s timer/counters run at 12 clock
cycles per increment so that timer-based events have the
same timing as with the standard 8051. The timers can also
be configured to run at 4 clock cycles per increment to take
advantage of the higher speed of the EZ-USB’s CPU.
12.1.2 Stretch Memory Cycles
The EZ-USB can execute a MOVX instruction in as few as
two instruction cycles. However, it is sometimes desirable to
stretch this value (for example to access slow memory or
slow memory-mapped peripherals such as USARTs or
LCDs). The EZ-USB’s ‘stretch memory cycle’ (Wait States)
feature enables EZ-USB firmware to adjust the speed of
data memory accesses (program memory code fetches are
not affected).
The three LSBs of the Clock Control Register (CKCON, at
SFR location 0x8E) control the stretch value; stretch values
between zero and seven may be used. A stretch value of
zero adds zero instruction cycles, resulting in MOVX instruc-
tions which execute in two instruction cycles. A stretch value
of seven adds seven instruction cycles, resulting in MOVX
instructions which execute in nine instruction cycles. The
stretch value can be changed dynamically under program
control.
At power on reset, the stretch value defaults to one (three
cycle MOVX); for the fastest data memory access, EZ-USB
MOV C, bit Move direct bit to carry 2 2 CY A2
MOV bit, C Move carry to direct bit 2 2 92
Branching
ACALL addr11 Absolute call to subroutine 2 3 11-F1
LCALL addr16 Long call to subroutine 3 4 12
RET Return from subroutine 1 4 22
RETI Return from interrupt 1 4 32
AJMP addr11 Absolute jump unconditional 2 3 01-E1
LJMP addr16 Long jump unconditional 3 4 02
SJMP rel Short jump (relative address) 2 3 80
JC rel Jump if carry = 1 2 3 40
JNC rel Jump if carry = 0 2 3 50
JB bit, rel Jump if direct bit = 1 3 4 20
JNB bit, rel Jump if direct bit = 0 3 4 30
JBC bit, rel Jump if direct bit = 1, then clear the bit 3 4 10
JMP @ A+DPTR Jump indirect to address DPTR+A 1 3 73
JZ rel Jump if accumulator = 0 2 3 60
JNZ rel Jump if accumulator is non-zero 2 3 70
CJNE A, direct, rel Compare A to direct byte; jump if not equal 3 4 CY B5
CJNE A, #d, rel Compare A to immediate; jump if not equal 3 4 CY B4
CJNE Rn, #d, rel Compare register to immediate; jump if not equal 3 4 CY B8-BF
CJNE @ Ri, #d, rel Compare data memory to immediate; jump if not equal 3 4 CY B6-B7
DJNZ Rn, rel Decrement register; jump if not zero 2 3 D8-DF
DJNZ direct, rel Decrement direct byte; jump if not zero 3 4 D5
Miscellaneous
NOP No operation 1 1 00
There is an additional reserved opcode (A5) that performs the same function as NOP. All mnemonics are copyright 1980, Intel Corporation.
Table 12-2. EZ-USB Instruction Set (continued)
Mnemonic Description Bytes Cycles PSW Flags Affected Opcode (Hex)
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 179
Instruction Set
software must explicitly set the stretch value to zero. The
stretch value affects only data memory access (not program
memory).
The stretch value affects the width of the read/write strobe
and all related timing. Using a higher stretch value results in
a wider read/write strobe, which allows the memory or
peripheral more time to respond.
Table 12-3 lists the data memory access speeds for stretch
values zero through seven. MD2-0 are the three LSBs of the
Clock Control Register (CKCON.2-0). The strobe width tim-
ing shown is typical.
CPUCS.4:3 sets the basic clock reference for the EZ-USB.
These bits can be modified by EZ-USB firmware at any time.
At power on reset, CPUCS.4:3 is set to ‘00’ (12 MHz).
12.1.3 Dual Data Pointers
The EZ-USB employs dual data pointers to accelerate data
memory block moves. The standard 8051 data pointer
(DPTR) is a 16 bit pointer used to address external data
RAM or peripherals. The EZ-USB maintains the standard
data pointer as DPTR0 at the standard SFR locations 0x82
(DPL0) and 0x83 (DPH0); it is not necessary to modify exist-
ing code to use DPTR0.
The EZ-USB adds a second data pointer (DPTR1) at SFR
locations 0x84 (DPL1) and 0x85 (DPH1). The SEL bit (bit 0
of the DPTR Select Register, DPS, at SFR 0x86), selects
the active pointer. When SEL = 0, instructions that use the
DPTR will use DPL0:DPH0. When SEL = 1, instructions that
use the DPTR will use DPL1:DPH1. No other bits of the
DPS SFR are used.
All DPTR related instructions use the data pointer selected
by the SEL Bit. Switching between the two data pointers by
toggling the SEL bit relieves EZ-USB firmware from the bur-
den of saving source and destination addresses when doing
a block move; therefore, using dual data pointers provides
significantly increased efficiency when moving large blocks
of data.
The fastest way to toggle the SEL bit between the two data
pointers is via the ‘INC DPS’ instruction, which toggles bit 0
of DPS between ‘0’ and ‘1’.
The SFR locations related to the dual data pointers are:
0x82 DPL0 DPTR0 low byte
0x83 DPH0 DPTR0 high byte
0x84 DPL1 DPTR1 low byte
0x85 DPH1 DPTR1 high byte
0x86 DPS DPTR Select (Bit 0)
12.1.4 Special Function Registers
The four SFRs listed below are related to CPU operation
and program execution. Except for the Stack Pointer (SP),
each of the registers is bit addressable.
0x81 SP Stack Pointer
0xD0 PSW Program Status Word
0xE0 ACC Accumulator Register
0xF0 B B Register
Table 12-4 lists the functions of the PSW bits.
Table 12-3. Data Memory Stretch Values
MD2 MD1 MD0 MOVX
Instruction
Cycles
Read/Write
Strobe Width
(Clocks)
Strobe Width
@ 12 MHz
CPUCS.4:3 = 00
Strobe Width
@ 24 MHz
CPUCS.4:3 = 01
Strobe Width
@ 48 MHz
CPUCS.4:3 = 10
0 0 0 2 2 167 ns 83.3 ns 41.7 ns
0 0 1 3 (default) 4 333 ns 167 ns 83.3 ns
0 1 0 4 8 667 ns 333 ns 167 ns
0 1 1 5 12 1000 ns 500 ns 250 ns
1 0 0 6 16 1333 ns 667 ns 333 ns
1 0 1 7 20 1667 ns 833 ns 417 ns
1 1 0 8 24 2000 ns 1000 ns 500 ns
1 1 1 9 28 2333 ns 1167 ns 583 ns
180 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Instruction Set
Table 12-4. PSW Register - SFR 0xD0
Bit Function
PSW.7 CY - Carry flag. This is the unsigned carry bit. The CY flag is set when an arithmetic operation results in a carry from bit 7 to bit 8, and
cleared otherwise. In other words, it acts as a virtual bit 8. The CY flag is cleared on multiplication and division. See the ‘PSW Flags
Affected’ column in Table 12-2 on page 176.
PSW.6 AC - Auxiliary carry flag. Set to ‘1’ when the last arithmetic operation resulted in a carry into (during addition) or borrow from (during sub-
traction) the high order nibble, otherwise cleared to ‘0’ by all arithmetic operations. See the ‘PSW Flags Affected’ column in Table 12-2 on
page 176.
PSW.5 F0 - User flag 0. Available to EZ-USB firmware for general purpose.
PSW.4 RS1 - Register bank select bit 1.
PSW.3 RS0 - Register bank select bit 0.
RS1:RS0 select a register bank in internal RAM:
RS1 RS0 Bank Selected
0 0 Register bank 0, addresses 0x00-0x07
0 1 Register bank 1, addresses 0x08-0x0F
1 0 Register bank 2, addresses 0x10-0x17
1 1 Register bank 3, addresses 0x18-0x1F
PSW.2 OV - Overflow flag. This is the signed carry bit. The OV flag is set when a positive sum exceeds 0x7F or a negative sum (in two’s comple-
ment notation) exceeds 0x80. After a multiply, OV = 1 if the result of the multiply is greater than 0xFF. After a divide,
OV = 1 if a divide-by-0 occurred. See the ‘PSW Flags Affected’ column in Table 12-2 on page 176.
PSW.1 F1 - User flag 1. Available to EZ-USB firmware for general purpose.
PSW.0 P - Parity flag. Contains the modulo-2 sum of the 8 bits in the accumulator (for example, set to ‘1’ when the accumulator contains an odd
number of ‘1’ bits, set to ‘0’ when the accumulator contains an even number of ‘1’ bits).
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 181
13. Input/Output
13.1 Introduction
The 56-pin EZ-USB provides two input/output systems:
■A set of programmable I/O pins
■A programmable I2C bus controller
The 100- and 128-pin packages additionally provide two programmable USARTs, which are described in the Timers/Counters
and Serial Interface chapter on page 193
The I/O pins may be configured either for general purpose I/O or for alternate functions (GPIF address and data; FIFO data;
USART, timer, and interrupt signals, and others). This chapter describes the usage of the pins in the general purpose config-
uration, and the methods by which the pins may be configured for alternate functions.
This chapter also provides both the programming information for the I2C interface and the operating details of the EEPROM
boot loader. The role of the boot loader is described in the Enumeration and ReNumeration™ chapter on page 51.
13.2 I/O Ports
The EZ-USB’s I/O ports are implemented differently than those of a standard 8051.
The EZ-USB has up to five 8-pin bidirectional I/O ports, labeled A, B, C, D, and E. Individual I/O pins are labeled Px.n, where
x is the port (A, B, C, D, or E) and n is the pin number (0 to 7).
The 100- and 128-pin EZ-USB packages provide all five ports; the 56-pin package provides only ports A, B, and D.
Each port is associated with a pair of registers:
■An OEx register (where x is A, B, C, D, or E), which sets the input/output direction of each of the 8 pins (0 = input, 1 = out-
put). See the OEx register on page 182.
■An IOx register (where x is A, B, C, D, or E). Values written to IOx appear on the pins which are configured as outputs; val-
ues read from IOx indicate the states of the 8 pins, regardless of input/output configuration. See IOx register on page 183.
Most I/O pins have alternate functions which may be selected using configuration registers (see Table 13-1 on page 185
through Table 13-9 on page 188). Each alternate function is unidirectional; the EZ-USB ‘knows’ whether the function is an
input or an output, so when an alternate configuration is selected for an I/O pin, the corresponding OEx bit is ignored (see Fig-
ures Figure 13-2 on page 184 and Figure 13-3 on page 184).
The default (power on reset) state of all I/O ports is:
■Alternate configurations off
■All I/O pins configured as inputs
Figure 13-1 on page 182 shows the basic structure of an EZ-USB I/O pin.
182 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Input/Output
Figure 13-1. EZ-USB I/O Pin
13.3 SFR Registers
OEx Bit
IOx Bit I/O Pin
Read
Write
OEA Port A Output Enable SFR 0xB2
b7 b6 b5 v4 v3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0
OEB Port B Output Enable SFR 0xB3
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0
OEC Port C Output Enable SFR 0xB4
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0
OED Port D Output Enable SFR 0xB5
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0
OEE Port E Output Enable SFR 0xB6
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 183
Input/Output
13.4 I/O Port Alternate Functions
Each I/O pin may be configured for an alternate (for exam-
ple, non-general purpose I/O) function. These alternate
functions are selected through various configuration regis-
ters, as described in the following sections.
The I/O pin logic for alternate function outputs is slightly dif-
ferent than for alternate function inputs, as shown in Figures
13-2 (output) and 13-3 (input).
IOA Port A (Bit-Addressable) SFR 0x80
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
IOB Port B (Bit-Addressable) SFR 0x90
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
IOC Port C (Bit-Addressable) SFR 0xA0
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
IOD Port D (Bit-Addressable) SFR 0xB0
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
IOE Port E SFR 0xB1
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
184 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Input/Output
Figure 13-2. I/O Pin Logic when Alternate Function is an OUTPUT
Figure 13-2 shows an I/O pin whose alternate function is
always an output.
In Figure 13-2a, the I/O pin is configured for general pur-
pose I/O. In this configuration, the alternate function is dis-
connected and the pin functions normally.
In Figure 13-2b, the I/O pin is configured as an alternate-
function output. In this configuration, the IOx/OEx output
buffer is disconnected from the I/O pin, so writes to IOx and
OEx have no effect on the I/O pin. ‘Reads’ from IOx, how-
ever, continue to work normally; the state of the I/O pin (and,
therefore, the state of the alternate function) is always avail-
able.
Figure 13-3 shows an I/O pin whose alternate function is
always an input.
In Figure 13-3a, the I/O pin is configured for general pur-
pose I/O. There is an important difference between alter-
nate-function inputs and the alternate function outputs
shown earlier in Figure 13-2 on page 184: Note Alternate-
function inputs are never disconnected; they are always lis-
tening.
If the alternate function’s interrupt is enabled, signals on the
I/O pin may trigger that interrupt. If the pin is to be used only
for general purpose I/O, the alternate function’s interrupt
must be disabled.
For example, suppose the PE5/INT6 pin is configured for
general purpose I/O. Since the INT6 function is an input, the
pin signal is also routed to the EZ-USB’s internal INT6 logic.
If the INT6 interrupt is enabled, traffic on the PE5 pin trigger
an INT6 interrupt. If this is undesirable, the INT6 interrupt
should be disabled.
Figure 13-3. I/O Pin Logic when Alternate Function is an INPUT
OEx Bit
IOx Bit I/O Pin
Read
Write
Alternate Function
(Output)
OEx Bit
IOx Bit I/O Pin
Read
Write
Alternate Function
(Output)
a) General-Purpose I/O Configuration b) Alternate-Function Configuration
OEx Bit
IOx Bit I/O Pin
Read
Write
Alternate Function
(Input)
OEx Bit
IOx Bit I/O Pin
Read
Write
Alternate Function
(Input)
a) General-Purpose I/O Configuration b) Alternate-Function Configuration
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 185
Input/Output
Of course, this side effect can be useful in certain situations.
In the case of PE5/INT6, for example, PE5 can trigger an
INT6 interrupt even if the I/O pin is configured as an output
(for example, OEE.5 = 1), so the EZ-USB’s firmware can
directly generate external interrupts.
In Figure 13-3b, the I/O pin is configured as an alternate
function input. Just as with alternate function outputs, the
IOx/OEx output buffer is disconnected from the I/O pin, so
writes to IOx and OEx have no effect on the I/O pin. ‘Reads’
from I/Ox, however, continue to work normally; the state of
the I/O pin (and therefore, the input to the alternate function)
is always available.
13.4.1 Port A Alternate Functions
Alternate functions for the Port A pins are selected by bits in
three registers, as shown in Tables 13-1 and 13-2.
Table 13-1. Register Bits that Select Port A Alternate Functions
b7 b6 b5 b4 b3 b2 b1 b0
PORTACFG
(0xE670) FLAGD SLCS[1] 0 0 0 0 INT1 INT0
IFCONFIG
(0xE601) IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0
WAKEUPCS
(0xE682) WU2 WU WU2POL WUPOL 0DPEN WU2EN WUEN
[1] Although the SLCS alternate function is selected by bit 6 of PORTACFG, that function does not appear on pin PA6. Instead, the SLCS function appears
on pin PA7 (see Table 13-2).
Table 13-2. Port A Alternate Function Configuration
Port A Pin Alternate Function Alternate Function is Selected By... Alternate Function is Described in...
PA.0 INT0 PORTACFG.0 = 1 Interrupts chapter on page 59
PA.1 INT1 PORTACFG.1 = 1 Interrupts chapter on page 59
PA.2 SLOE IFCFG1:0 = 11 Slave FIFOs chapter on page 99
PA.3 WU2[1] WU2EN = 1 Power Management chapter on page 77
PA.4 FIFOADR0 IFCFG1:0 = 11 Slave FIFOs chapter on page 99
PA.5 FIFOADR1 IFCFG1:0 = 11 Slave FIFOs chapter on page 99
PA.6 PKTEND IFCFG1:0 = 11 Slave FIFOs chapter on page 99
PA.7 FLAGD[2] PORTACFG.7 = 1 Slave FIFOs chapter on page 99
SLCS[3] PORTACFG.6 = 1 and IFCFG1:0 = 11 Slave FIFOs chapter on page 99
[1] When PA.3 is configured for alternate function WU2, it continues to function as a general purpose input pin as well. See section 6.4.1 WU2 Pin on page 81
for more information.
[2] Although PA.7’s alternate function FLAGD is selected via the PORTACFG register, the state of the FLAGD output is undefined unless IFCFG1:0 = 11.
[3] FLAGD takes priority over SLCS if PORTACFG.6 and PORTACFG.7 are both set to ‘1’.
186 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Input/Output
13.4.2 Port B and Port D Alternate
Functions
When IFCFG1 = 1, all eight Port B pins are configured for an
alternate configuration (FIFO Data 7:0).
If any of the FIFOs are set to 16 bit mode (via the WORD-
WIDE bits in the EPxFIFOCFG registers), all eight Port D
pins are also configured for an alternate configuration (FIFO
Data 15:8). See Tables 13-3, 13-4, and 13-5.
If all WORDWIDE bits are cleared to ‘0’ (for example, if all
four FIFOs are operating in 8 bit mode), the eight Port D pins
may be used as general purpose I/O pins even if
IFCFG1 = 1.
Table 13-3. Register Bits Which Select Port B and Port D Alternate Functions
b7 b6 b5 b4 b3 b2 b1 b0
IFCONFIG
(0xE601) IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0
EP2FIFOCFG
(0xE618) 0INFM2 OEP2 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE
EP4FIFOCFG
(0xE619) 0INFM4 OEP4 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE
EP6FIFOCFG
(0xE61A) 0INFM6 OEP6 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE
EP8FIFOCFG
(0xE61B) 0INFM8 OEP8 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE
Table 13-4. Port B Alternate-Function Configuration
Port B Pin Alternate Function Alternate Function is Selected By... Alternate Function is Described in...
PB.7:0 FD[7:0] IFCFG1 = 1 Slave FIFOs chapter on page 99
Table 13-5. Port D Alternate-Function Configuration
Port D Pin Alternate Function Alternate Function is Selected By... Alternate Function is Described in...
PD.7:0 FD[15:8] IFCFG1 = 1 and any WORDWIDE bit = 1 Slave FIFOs chapter on page 99
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 187
Input/Output
13.4.3 Port C Alternate Functions
Each Port C pin may be individually configured for an alternate function by setting a bit in the PORTCCFG register, as shown
in Tables 13-6 and 13-7.
Table 13-6. Register Bits That Select Port C Alternate Functions
b7 b6 b5 b4 b3 b2 b1 b0
PORTCCFG
(0xE671) GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0
Table 13-7. Port C Alternate Function Configuration
Port C Pin Alternate Function Alternate Function is Selected By... Alternate Function is Described in...
PC.0 GPIFA0[1] PORTCCFG.0 = 1 General Programmable Interface chapter on page 121.
PC.1 GPIFA1[1] PORTCCFG.1 = 1 General Programmable Interface chapter on page 121.
PC.2 GPIFA2[1] PORTCCFG.2 = 1 General Programmable Interface chapter on page 121.
PC.3 GPIFA3[1] PORTCCFG.3 = 1 General Programmable Interface chapter on page 121.
PC.4 GPIFA4[1] PORTCCFG.4 = 1 General Programmable Interface chapter on page 121.
PC.5 GPIFA5[1] PORTCCFG.5 = 1 General Programmable Interface chapter on page 121.
PC.6 GPIFA6[1] PORTCCFG.6 = 1 General Programmable Interface chapter on page 121.
PC.7 GPIFA7[1] PORTCCFG.7 = 1 General Programmable Interface chapter on page 121.
[1] Although the Port C alternate functions GPIFA0:7 are selected via the PORTCCFG register, the states of the GPIFA0:7 outputs are undefined unless
IFCFG1:0 = 10.
188 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Input/Output
13.4.4 Port E Alternate Functions
Each Port E pin may be individually configured for an alter-
nate function by setting a bit in the PORTECFG register.
If the GSTATE bit in the IFCONFIG register is set to ‘1’, the
PE.2:0 pins are automatically configured as GPIF Status
pins GSTATE[2:0], regardless of the PORTECFG.2:0 set-
tings. In other words, GSTATE overrides PORTECFG.2:0.
See Tables 13-8 and 13-9.
Table 13-8. Register Bits That Select Port E Alternate Functions
b7 b6 b5 b4 b3 b2 b1 b0
PORTECFG
(0xE671) GPIFA8 T2EX INT6 RXD1OUT RXD0OUT T2OUT T1OUT T0OUT
IFCONFIG
(0xE601) IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0
Table 13-9. Port E Alternate-Function Configuration
Port E Pin Alternate Function Alternate Function is Selected By... Alternate Function is Described in...
PE.0 T0OUT[1,3] PORTECFG.0 = 1 and GSTATE = 0 Timers/Counters and Serial Interface chapter on page 193
PE.1 T1OUT[1,3] PORTECFG.1 = 1 and GSTATE = 0 Timers/Counters and Serial Interface chapter on page 193
PE.2 T2OUT[1] PORTECFG.2 = 1 and GSTATE = 0 Timers/Counters and Serial Interface chapter on page 193
PE.3 RXD0OUT PORTECFG.3 = 1 Timers/Counters and Serial Interface chapter on page 193
PE.4 RXD1OUT PORTECFG.4 = 1 Timers/Counters and Serial Interface chapter on page 193
PE.5 INT6 PORTECFG.5 = 1 Interrupts chapter on page 59
PE.6 T2EX PORTECFG.6 = 1 Timers/Counters and Serial Interface chapter on page 193
PE.7 GPIFA8[2] PORTECFG.7 = 1 General Programmable Interface chapter on page 121
[1] If GSTATE is set to ‘1’, these settings are overridden and PE.2:0 are all automatically configured as GPIF Status pins (See General Programmable
Interface chapter on page 121).
[2] Although the PE.7 alternate function GPIFA8 is selected via the PORTECFG register, the state of the GPIFA8 output is undefined unless IFCFG1:0 = 10.
[3] Alternate function for PE.1:0 not available for CY7C68015A and CY68016A.
Table 13-10. IFCFG Selection of Port I/O
Pin Functions
IFCFG1:0 = 00
(Ports)
IFCFG1:0 = 10
(GPIF Master)
IFCFG1:0 = 11
(Slave FIFO)
PD7 FD[15] FD[15]
PD6 FD[14] FD[14]
PD5 FD[13] FD[13]
PD4 FD[12] FD[12]
PD3 FD[11] FD[11]
PD2 FD[10] FD[10]
PD1 FD[9] FD[9]
PD0 FD[8] FD[8]
PB7 FD[7] FD[7]
PB6 FD[6] FD[6]
PB5 FD[5] FD[5]
PB4 FD[4] FD[4]
PB3 FD[3] FD[3]
PB2 FD[2] FD[2]
PB1 FD[1] FD[1]
PB0 FD[0] FD[0]
INT0# / PA0 INT0# / PA0 INT0# / PA0
INT1# / PA1 INT1# / PA1 INT1# / PA1
PA2 PA2 SLOE
WU2 / PA3 WU2 / PA3 WU2 / PA3
PA4 PA4 FIFOADR0
PA5 PA5 FIFOADR1
PA6 PA6 PKTEND
PA7 PA7 PA7 / FLAGD / SLCS#
PC7:0 PC7:0 PC7:0
PE7:0 PE7:0 PE7:0
Note Signals shown in bold type do not change with IFCFG; they are
shown for completeness.
Table 13-10. IFCFG Selection of Port I/O
Pin Functions (continued)
IFCFG1:0 = 00
(Ports)
IFCFG1:0 = 10
(GPIF Master)
IFCFG1:0 = 11
(Slave FIFO)
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 189
Input/Output
13.5 I2C Bus Controller
The I2C bus controller uses the SCL (Serial Clock) and SDA
(Serial Data) pins, and performs two functions:
■General purpose interfacing to I2C peripherals
■Boot loading from a serial EEPROM
Note Pull up resistors are required on the SDA and SCL
lines, even if nothing else is connected to the I2C bus.
Each line must be pulled up to Vcc through a 2.2K ohm
resistor.
The bus frequency defaults to approximately 100 kHz for
compatibility, and it can be configured to run at 400 kHz for
devices that support the higher speed.
13.5.1 Interfacing to I2C Peripherals
Figure 13-4 illustrates the waveforms for an I2C transfer.
SCL and SDA are open drain EZ-USB pins which must be
pulled up to Vcc with external resistors. The EZ-USB is a
bus master only, meaning that it generates clock pulses on
SCL. Once the master drives SCL low, external slave
devices can hold SCL low to extend clock-cycle times.
Serial data is permitted to change state only while SCL is
low, and must be valid while SCL is high. Two exceptions to
this rule are the ‘start’ and ‘stop’ conditions. A ‘start’ condi-
tion is defined as a high-to-low transition on SDA while SCL
is high, and a ‘stop’ condition is defined as a low-to-high
transition on SDA while SCL is high. Data is sent MSB first.
During the last bit time (clock #9 in Figure 13-4), the trans-
mitting device floats the SDA line to allow the receiving
device to acknowledge the transfer by pulling SDA low.
13.5.1.1 Multiple Bus Masters
The EZ-USB acts only as a bus master, never as a slave.
Conflicts with a second master can be detected, however,
by checking for BERR=1 (see section 13.5.2.1 I2CS
Register on page 190).
Each peripheral (slave) device on the I2C bus has a unique
address. The first byte of an I2C transaction contains the
address of the desired peripheral. Figure 13-5 shows the
format for this first byte, which is sometimes called a control
byte.
The EZ-USB sends the bit sequence shown in Figure 13-5
to select the peripheral at a particular address, to establish
the transfer direction (using R/W), and to determine if the
peripheral is present by testing for ACK.
The four most significant bits (SA3:0) are the peripheral
chip’s slave address. I2C devices are internally hardwired
to pre-assigned slave addresses by device type.
EEPROMs, for instance, are assigned slave address 1010.
The next three bits (DA2:0) usually reflect the states of the
device’s address pins. A device with three address pins can
be strapped to one of eight distinct addresses, which allows,
for example, up to eight serial EEPROMs to be individually
addressed on one I2C bus.
The eighth bit (R/W) sets the direction for the data transfer
to follow (1 = master read, 0 = master write). Most address
transfers are followed by one or more data transfers, with
the ‘stop’ condition generated after the last data byte is
transferred.
In Figure 13-5, the master clocks the 7 bit slave/device
address out on SDA, then sets the R/W bit high at clock 8,
indicating that a read transfer follows this address byte. At
clock 9, the master releases SDA and treats it as an input;
the peripheral device responds to its address by asserting
ACK. At clock 10, the master begins to clock in data from
the slave on the SDA pin.
Figure 13-4. General I2C Transfer
Figure 13-5. Addressing an I2C Peripheral
SDA
SCL 12345678 9
D7 ACKD6 D5 D4 D3 D2 D1 D0
start stop
SDA
SCL
12345678 9
SA3 ACKSA2 SA1 SA0 DA2 DA1 DA0
start
SDA
D7 D6
10 11
R/W
SCL
190 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Input/Output
13.5.2 Registers
The three registers shown in this section are used to conduct transfers over the I2C bus.
13.5.2.1 I2CS Register
Bit 7: START. When START = 1, the next write to I2DAT
generates a ‘start’ condition followed by the byte of data writ-
ten to I2DAT. The START bit is automatically cleared to 0
after the ACK interval (clock 9 in Figure 13-4 on page 189).
START is a control bit.
Bit 6: STOP. When STOP = 1 after the ACK interval (clock
9 in Figure 13-4 on page 189), a ‘stop’ condition is gener-
ated. STOP may be set by firmware at any time before, dur-
ing, or after the 9-bit data transaction. STOP is automatically
cleared after the ‘stop’ condition is generated. STOP is a
control bit.
An interrupt request is available to signal that the stop condi-
tion is complete; see STOPIE, below.
Bit 5: LASTRD. An I2C master reads data by floating the
SDA line and issuing clock pulses on the SCL line. After
every eight bits, the master drives SDA low for one clock to
indicate ACK. To signal the last byte of a multi-byte transfer,
the master floats SDA at ACK time to instruct the slave to
stop sending. LASTRD is a control bit.
When LASTRD = 1 at ACK time, the EZ-USB floats the SDA
line. The LASTRD bit may be set at any time before or dur-
ing the data transfer; it is automatically cleared after the
ACK interval.
Note Setting LASTRD does not automatically generate a
‘stop’ condition. At the end of a read transfer, the STOP bit
should also be set.
Bits 3 and 4: ID1, ID0. These bits are automatically set by
the boot loader to indicate the Boot EEPROM addressing
mode. They are normally used only for debug purposes; for
full details, see section 13.6 EEPROM Boot Loader on
page 192.
Bit 2: BERR. This bit indicates a bus error. BERR=1 indi-
cates that there was bus contention during the preceding
transfer, which results when an outside device drives the
bus when it should not, or when another bus master wins
arbitration and takes control of the bus. BERR is a status bit.
When a bus error is detected, the EZ-USB immediately can-
cels its current transfer, floats the SCL and SDA lines, and
sets DONE and BERR. BERR remains set until it is updated
at the next ACK interval. The I2C master does not drive SCL
till BERR is reset. If the bus error causes the master to
detect bus contention and slave to be stuck in the middle of
a transfer. Then there is no in-built contention resolution
method to workaround this deadlock. If there is a possibility
of this condition then the design must implement a method
of resetting the slave or clocking the slave till the next ACK.
Note DONE is set with BERR only when bus contention
occurs during a transfer. If BERR is set and the bus is still
busy when firmware attempts to restart a transfer, that trans-
fer request is ignored and the DONE flag is not set. If con-
tention is expected, therefore, EZ-USB firmware should
incorporate a timeout to test for this condition. See Steps 1
and 3 of Section 13.5.3 and Section 13.5.4.
Bit 1: ACK. During the ninth clock of a write transfer, the
slave indicates reception of the byte by driving SDA low to
acknowledge the byte it just received. The EZ-USB floats
SDA during this time, samples the SDA line, and updates
the ACK bit with the complement of the detected value: ACK
= 1 indicates that the slave acknowledged the transfer, and
ACK = 0 indicates the slave did not. ACK is a status bit.
The ACK bit is only meaningful after a write transfer. After a
read transfer, its state should be ignored.
Bit 0: DONE. The EZ-USB sets this bit whenever it com-
pletes a byte transfer. The EZ-USB also generates an inter-
rupt request when it sets the DONE bit. The DONE bit is
automatically cleared when the I2DAT register is read or
written, and the interrupt request bit is automatically cleared
by reading or writing the I2CS or I2DAT registers (or by
clearing EXIF.5 to 0). DONE is a status bit.
For additional information, refer to the I2CS register on page
278.
I2CS I2C Bus Control and Status E678
b7 b6 b5 b4 b3 b2 b1 b0
START STOP LASTRD ID1 ID0 BERR ACK DONE
R/W R/W R/W R R R R R
0 0 0 x x 0 0 0
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 191
Input/Output
13.5.2.2 I2CDAT Register
Writing to I2DAT initiates a write transfer on the I2C bus; the
value written to I2DAT is then transferred. Reading from
I2DAT retrieves the data that was transferred in the previous
read transfer and (with one exception) initiates another read
transfer. To retrieve data from the previous read transfer
without initiating another transfer, I2DAT must be read dur-
ing the generation of the ‘stop’ condition. See Step 13 of
section 13.5.4 Receiving Data on page 191 for details. For
additional information, refer to the I2CDAT register on page
280.
13.5.2.3 I2CTL Register
I2CTL configures the bus. Data is transferred to and from
the bus through the I2DAT register. The I2CS register con-
trols the transfers and reports various status conditions.
Bit 1: STOPIE. Setting this bit to ‘1’ enables the STOP bit
Interrupt Request, which is activated when the STOP bit
makes a 1-to-0 transition (for example, when generation of a
‘stop’ condition is complete). STOPIE is a control bit.
Bit 0: 400KHZ. When this bit is at its default value of ‘0’,
SCL is driven at approximately 100 kHz. Setting this bit to ‘1’
causes the EZ-USB to drive SCL at approximately 400 kHz.
400KHZ is a control bit.
For additional information, refer to the I2CTL register on
page 281.
13.5.3 Sending Data
To send a multiple byte data record, follow these steps:
1. Set START=1. If BERR=1, start timer. The timeout
should be at least as long as the longest expected Start-
to-Stop interval on the bus.
2. Write the 7-bit peripheral address and the direction bit (0
for a write) to I2DAT.
3. Wait for DONE=1 or for timer to expire*. If BERR=1, go
to step 1.
4. If ACK=0, go to step 9.
5. Load I2DAT with a data byte.
6. Wait for DONE=1*. If BERR=1, go to step 1.
7. If ACK=0, go to step 9.
8. Repeat steps 5-7 for each byte until all bytes have been
transferred.
9. Set STOP=1. Wait for STOP = 0 before initiating another
transfer.
13.5.4 Receiving Data
To read a multiple-byte data record, follow these steps:
1. Set START=1. If BERR = 1, start timer. The timeout
should be at least as long as the longest expected Start-
to-Stop interval on the bus.
2. Write the 7-bit peripheral address and the direction bit (1
for a read) to I2DAT.
3. Wait for DONE=1 or for timer to expire*. If BERR=1, go
to step 1.
4. If ACK=0, set STOP=1 and go to step 15.
5. Read I2DAT to initiate the first burst of nine SCL pulses
to clock in the first byte from the slave. Discard the value
that was read from I2DAT.
6. Wait for DONE=1. If BERR=1, go to step 1.
7. Read the just-received byte of data from I2DAT. This
read also initiates the next read transfer.
8. Repeat steps 6 and 7 for each byte until ready to read
the second-to-last byte.
9. Wait for DONE=1. If BERR=1, go to step 1.
I2DAT I2C Bus Data E679
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
I2CTL I2C Bus Mode E67A
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 STOPIE 400KHZ
R RRRRRR/W R/W
00000000
192 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Input/Output
10. Before reading the second-to-last I2DAT byte, set LAS-
TRD=1.
11. Read the second-to-last byte from I2DAT. With LAS-
TRD=1, this initiates the final byte read on the bus.
12. Wait for DONE=1. If BERR=1, go to step 1.
13. Set STOP=1.
14. Read the final byte from I2DAT immediately (the next
instruction) after setting the STOP bit. By reading I2DAT
while the ‘stop’ condition is being generated, the just-
received data byte is retrieved without initiating an extra
read transaction (nine more SCL pulses) on the I2Cbus.
15. Wait for STOP = 0 before initiating another transfer.
13.6 EEPROM Boot Loader
Whenever the EZ-USB is taken out of reset via the reset pin,
its boot loader checks for the presence of an EEPROM on
the I2C bus. If an EEPROM is detected, the loader reads the
first EEPROM byte to determine how to enumerate. The var-
ious enumeration modes are described in the Enumeration
and ReNumeration™ chapter on page 51.
The EZ-USB boot loader supports two I2C EEPROM types:
■EEPROMs with slave address 1010 that use an 8-bit
internal address (for example, 24LC00, 24LC01/B,
24LC02/B).
■EEPROMs with slave address 1010 that use a 16-bit
internal address (for example, 24AA64, 24LC128,
24AA256).
EEPROMs with densities up to 256 bytes require only a sin-
gle address byte; larger EEPROMs require two address
bytes. The EZ-USB must determine which EEPROM type is
connected — one or two address bytes — so that it can
properly read the EEPROM.
The EZ-USB uses the EEPROM device-address pins A2,
A1, and A0 to determine whether to send out one or two
bytes of address. As shown in Table 13-11, single byte
address EEPROMs must be strapped to address 000, while
double byte address EEPROMs must be strapped to
address 001.
[1] This EEPROM does not have device-address pins.
Additional EEPROM devices can be attached to the I2Cbus
for general purpose use, as long as they are strapped for
device addresses other than 000 or 001.
Note Many single byte Address EEPROM’s are special
cases, because the EEPROM responds to all eight device
addresses. If one of these EEPROM’s is used for boot load-
ing, no other EEPROMs may share the bus. Consult your
EEPROM data sheet for details
After determining whether a one or two byte address
EEPROM is attached, the EZ-USB reports its results in the
ID1 and ID0 bits, as shown in Table 13-12.
Note The EZ-USB does not check for bus contention during
the bootloading process; if another I2C master is sharing the
bus, that master must not attempt to initiate any transfers
while the EZ-USB bootloader is running.
Table 13-11. Strap Boot EEPROM Address Lines to These
Values
Bytes Example EEPROM A2 A1 A0
16 24LC00[1] N/A N/A N/A
128 24LC01 0 0 0
256 24LC02 0 0 0
4K 24LC32 0 0 1
8K 24LC64 0 0 1
16K 24LC128 0 0 1
Table 13-12. Results of Power-On_Reset EEPROM Test
ID1 ID0 Meaning
0 0 No EEPROM detected
0 1 One byte address load EEPROM detected
1 0 Two byte address load EEPROM detected
1 1 Not used
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 193
14. Timers/Counters and Serial
Interface
14.1 Introduction
The EZ-USB’s timer/counters and serial interface are very similar to the standard 8051, with some differences and enhance-
ments. This chapter provides technical information on configuring and using the timer/counters and serial interface.
14.2 Timers/Counters
The EZ-USB includes three timer/counters (Timer 0, Timer 1, and Timer 2). Each timer/counter can operate either as a timer
with a clock rate based on the EZ-USB’s internal clock (CLKOUT) or as an event counter clocked by the T0 pin (Timer 0), T1
pin (Timer 1), or the T2 pin (Timer 2). Timers 1 and 2 may be used for baud clock generation for the serial interface (see sec-
tion 14.3 Serial Interface on page 201 for details of the serial interface).
Note The EZ-USB can be configured to operate at 12, 24, or 48 MHz. In timer mode, the timer/counters run at the same
speed as the EZ-USB, and they are not affected by the CLKOE and CLKINV configuration bits (CPUCS.1 and CPUCS.2).
Each timer/counter consists of a 16 bit register that is accessible to software as two SFRs.
■Timer 0 TH0 and TL0
■Timer 1 TH1 and TL1
■Timer 2 TH2 and TL2
14.2.1 803x/805x Compatibility
The implementation of the timers/counters is similar to that of the Dallas Semiconductor DS80C320. Table 14-1 summarizes
the differences in timer/counter implementation between the Intel 8051, the Dallas Semiconductor DS80C320, and the EZ-
USB.
14.2.2 Timers 0 and 1
Timers 0 and 1 operate in four modes, as controlled through the TMOD SFR (Table 14-2 on page 195) and the TCON SFR
(Table 14-3 on page 195). The four modes are:
■13 bit timer/counter (mode 0)
■16 bit timer/counter (mode 1)
■8 bit counter with auto-reload (mode 2)
■Two 8 bit counters (mode 3, Timer 0 only)
Table 14-1. Timer/Counter Implementation Comparison
Feature Intel 8051 Dallas DS80C320 EZ-USB
Number of timers 2 3 3
Timer 0/1 overflow
available as output signals No No Yes; T0OUT, T1OUT
(one CLKOUT pulse)
Timer 2 output enable n/a Yes Yes
Timer 2 down-count enable n/a Yes No
Timer 2 overflow
available as output signal n/a Yes Yes; T2OUT (one CLKOUT pulse)
194 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Timers/Counters and Serial Interface
14.2.2.1 Mode 0, 13 Bit Timer/Counter—
Timer 0 and Timer 1
Mode 0 operation is illustrated in Figure 14-1.
In mode 0, the timer is configured as a 13 bit counter that
uses bits 0-4 of TL0 (or TL1) and all 8 bits of TH0 (or TH1).
The timer enable bit (TR0/TR1) in the TCON SFR starts the
timer. The C/T Bit selects the timer/counter clock source:
either CLKOUT or the T0/T1 pins.
The timer counts transitions from the selected source as
long as the GATE Bit is 0, or the GATE Bit is 1 and the corre-
sponding interrupt pin (INT0 or INT1) is 1.
When the 13 bit count increments from 0x1FFF (all ones),
the counter rolls over to all zeros, the TF0 (or TF1) Bit is set
in the TCON SFR, and the T0OUT (or T1OUT) pin goes
high for one clock cycle.
Ignore the upper 3 bits of TL0 (or TL1) because they are
indeterminate in mode 0.
Figure 14-1. Timer 0/1 - Modes 0 and 1
TL0 (or TL1)
07
4
Divide by
Divide by 4
CLKOUT
T0 (or T1)
TR0 (or TR1)
GATE
INT0 (or
INT1) pin
7
0
TF0 (or
TF1) INT
TH0 (or TH1)
T0M (or T1M)
Mode 0
Mode 1
0
10
1
To Serial Port
(Timer 1 only)
CLK
C/ T
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 195
Timers/Counters and Serial Interface
14.2.2.2 Mode 1, 16 Bit Timer/Counter — Timer 0 and Timer 1
In mode 1, the timer is configured as a 16 bit counter. As illustrated in Figure 14-1 on page 194, all 8 bits of the LSB Register
(TL0 or TL1) are used. The counter rolls over to all zeros when the count increments from 0xFFFF. Otherwise, mode 1 opera-
tion is the same as mode 0.
Table 14-2. TMOD Register — SFR 0x89
Bit Function
TMOD.7 GATE1 - Timer 1 gate control. When GATE1 = 1, Timer 1 will clock only when INT1 = 1 and TR1 (TCON.6) = 1. When
GATE1 = 0, Timer 1 will clock only when TR1 = 1, regardless of the state of INT1.
TMOD.6 C/T1 - Counter/Timer select. When C/T1 = 0, Timer 1 is clocked by CLKOUT/4 or CLKOUT/12, depending on the state of
T1M (CKCON.4). When C/T1 = 1, Timer 1 is clocked by high-to-low transitions on the T1 pin.
TMOD.5 M1 - Timer 1 mode select bit 1.
TMOD.4 M0 - Timer 1 mode select bit 0.
M1 M0 Mode
0 0 Mode 0: 13 bit counter
0 1 Mode 1: 16 bit counter
1 0 Mode 2: 8 bit counter with auto-reload
1 1 Mode 3: Timer 1 stopped
TMOD.3 GATE0 - Timer 0 gate control, When GATE0 = 1, Timer 0 will clock only when INT0 = 1 and TR0 (TCON.4) = 1. When
GATE0 = 0, Timer 0 will clock only when TR0 = 1, regardless of the state of INT0.
TMOD.2 C/T0 - Counter/Timer select. When C/T0 = 0, Timer 0 is clocked by CLKOUT/4 or CLKOUT/12, depending on the state of
T0M (CKCON.3). When C/T0 = 1, Timer 0 is clocked by high-to-low transitions on the T0 pin.
TMOD.1 M1 - Timer 0 mode select bit 1.
TMOD.0 M0 - Timer 0 mode select bit 0.
M1 M0 Mode
0 0 Mode 0: 13 bit counter
0 1 Mode 1: 16 bit counter
1 0 Mode 2: 8 bit counter with auto-reload
1 1 Mode 3: Two 8 bit counters
Table 14-3. TCON Register — SFR 0x88
Bit Function
TCON.7 TF1 - Timer 1 overflow flag. Set to 1 when the Timer 1 count overflows; automatically cleared when the EZ-USB vectors to
the interrupt service routine.
TCON.6 TR1 - Timer 1 run control. 1 = Enable counting on Timer 1.
TCON.5 TF0 - Timer 0 overflow flag. Set to 1 when the Timer 0 count overflows; automatically cleared when the EZ-USB vectors to
the interrupt service routine.
TCON.4 TR0 - Timer 0 run control. 1 = Enable counting on Timer 0.
TCON.3 IE1 - Interrupt 1 edge detect. If external interrupt 1 is configured to be edge-sensitive (IT1 = 1), IE1 is set when a negative
edge is detected on the INT1 pin and is automatically cleared when the EZ-USB vectors to the corresponding interrupt ser-
vice routine. In this case, IE1 can also be cleared by software. If external interrupt 1 is configured to be level-sensitive
(IT1 = 0), IE1 is set when the INT1 pin is 0 and automatically cleared when the INT1 pin is 1. In level-sensitive mode, soft-
ware cannot write to IE1.
TCON.2 IT1 - Interrupt 1 type select. INT1 is detected on falling edge when IT1 = 1; INT1 is detected as a low level when IT1 = 0.
TCON.1 IE0 - Interrupt 0 edge detect. If external interrupt 0 is configured to be edge-sensitive (IT0 = 1), IE0 is set when a negative
edge is detected on the INT0 pin and is automatically cleared when the EZ-USB vectors to the corresponding interrupt ser-
vice routine. In this case, IE0 can also be cleared by software. If external interrupt 0 is configured to be level-sensitive
(IT0 = 0), IE0 is set when the INT0 pin is 0 and automatically cleared when the INT0 pin is 1. In level-sensitive mode, soft-
ware cannot write to IE0.
TCON.0 IT0 - Interrupt 0 type select. INT0 is detected on falling edge when IT0 = 1; INT0 is detected as a low level when IT0 = 0.
196 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Timers/Counters and Serial Interface
Figure 14-2. Timer 0/1 - Mode 2
14.2.2.3 Mode 2, 8 Bit Counter with Auto-
Reload — Timer 0 and Timer 1
In mode 2, the timer is configured as an 8 bit counter, with
automatic reload of the start value on overflow. TL0 (or TL1)
is the counter, and TH0 (or TH1) stores the reload value.
As illustrated in Figure 14-2, mode 2 counter control is the
same as for mode 0 and mode 1. When TL0/1 increments
from 0xFF, the value stored in TH0/1 is reloaded into TL0/1.
14.2.2.4 Mode 3, Two 8 Bit Counters — Timer
0 Only
In mode 3, Timer 0 operates as two 8 bit counters. Selecting
mode 3 for Timer 1 simply stops Timer 1.
As shown in Figure 14-3 on page 197, TL0 is configured as
an 8 bit counter controlled by the normal Timer 0 control bits.
TL0 can either count CLKOUT cycles (divided by 4 or by 12)
or high-to-low transitions on the T0 pin, as determined by
the C/T Bit. The GATE function can be used to give counter
enable control to the INT0 pin.
TH0 functions as an independent 8 bit counter. However,
TH0 can only count CLKOUT cycles (divided by 4 or by 12).
The Timer 1 control and flag bits (TR1 and TF1) are used as
the control and flag bits for TH0.
When Timer 0 is in mode 3, Timer 1 has limited usage
because Timer 0 uses the Timer 1 control bit (TR1) and
interrupt flag (TF1). Timer 1 can still be used for baud rate
generation and the Timer 1 count values are still available in
the TL1 and TH1 Registers.
Control of Timer 1 when Timer 0 is in mode 3 is through the
Timer 1 mode bits. To turn Timer 1 on, set Timer 1 to mode
0, 1, or 2. To turn Timer 1 off, set it to mode 3. The Timer 1
C/T Bit and T1M Bit are still available to Timer 1. Therefore,
Timer 1 can count CLKOUT/4, CLKOUT/12, or high-to-low
transitions on the T1 pin. The Timer 1 GATE function is also
available when Timer 0 is in mode 3.
TL0 (or TL1)
07
Divide by
Divide by 4
T0 (or T1)
TR0 (or TR1)
GATE
INT0 (or
INT1) pin
70
TF0 (or TF1)
TH0 (or TH1)
T0M (or T1M)
RELOAD
INT
0
10
1
To Serial Port
(Timer 1 only)
CLKOUT
CLK
C/ T
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 197
Timers/Counters and Serial Interface
Figure 14-3. Timer 0 - Mode 3
14.2.3 Timer Rate Control
By default, the EZ-USB timers increment every 12 CLKOUT
cycles, just as in the standard 8051. Using this default rate
allows existing application code with real-time dependen-
cies, such as baud rate, to operate properly.
Applications that require fast timing can set the timers to
increment every four CLKOUT cycles instead, by setting bits
in the Clock Control Register (CKCON) at SFR location
0x8E. (See Table 14-4).
Each timer’s rate can be set independently. These settings
have no effect in counter mode.
14.2.4 Timer 2
Timer 2 runs only in 16 bit mode and offers several capabili-
ties not available with Timers 0 and 1. The modes available
for Timer 2 are:
■16 bit timer/counter
■16 bit timer with capture
■16 bit timer/counter with auto-reload
■Baud rate generator
The SFRs associated with Timer 2 are:
■T2CON (SFR 0xC8) Timer/Counter 2 Control register,
(see Table 14-5 on page 198).
■RCAP2L (SFR 0xCA) Captures the TL2 value when
Timer 2 is configured for capture mode, or as the LSB of
the 16 bit reload value when Timer 2 is configured for
auto-reload mode.
■RCAP2H (SFR 0xCB) Captures the TH2 value when
Timer 2 is configured for capture mode, or as the MSB of
the 16 bit reload value when Timer 2 is configured for
auto-reload mode.
■TL2 (SFR 0xCC) The lower eight bits of the 16 bit count.
■TH2 (SFR 0xCD) The upper eight bits of the 16 bit count.
TL0
07
Divide by
Divide by
T0 pin
TR0
GATE
INT0 pin 7
0
TF0
TH0
T0M
INT
TR1
TF1 INT
0
10
1
CLKOUT CLK
C/ T
Table 14-4. CKCON (SFR 0x8E) Timer Rate Control Bits
Bit Function
CKCON.5 T2M - Timer 2 clock select. When T2M = 0, Timer 2 uses CLK-
OUT/12 (for compatibility with standard 8051); when T2M = 1,
Timer 2 uses CLKOUT/4. This bit has no effect when Timer 2
is configured for baud rate generation.
CKCON.4 T1M - Timer 1 clock select. When T1M = 0, Timer 1 uses CLK-
OUT/12 (for compatibility with standard 8051); when T1M = 1,
Timer 1 uses CLKOUT/4.
CKCON.3 T0M - Timer 0 clock select. When T0M = 0, Timer 0 uses CLK-
OUT/12 (for compatibility with standard 8051); when T0M = 1,
Timer 0 uses CLKOUT/4.
198 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Timers/Counters and Serial Interface
14.2.4.1 Timer 2 Mode Control
Table 14-6 summarizes how the T2CON bits determine the
Timer 2 mode.
14.2.5 Timer 2: The 6 Bit Timer/Counter
Mode
Figure 14-4 illustrates how Timer 2 operates in timer/counter
mode with the optional capture feature. The C/T2 Bit deter-
mines whether the 16 bit counter counts CLKOUT cycles
(divided by 4 or 12), or high-to-low transitions on the T2 pin.
The TR2 Bit enables the counter. When the count incre-
ments from 0xFFFF, the TF2 flag is set and the T2OUT pin
goes high for one CLKOUT cycle.
14.2.5.1 Timer 2 The 16 Bit Timer/Counter
Mode with Capture
The Timer 2 capture mode (Figure 14-4) is the same as the
16 bit timer/counter mode, with the addition of the capture
registers and control signals.
The CP/RL2 Bit in the T2CON SFR enables the capture fea-
ture. When CP/RL2 = 1, a high-to-low transition on the T2EX
pin when EXEN2 = 1 causes the Timer 2 value to be loaded
into the capture registers RCAP2L and RCAP2H.
Table 14-5. T2CON Register — SFR 0xC8
Bit Function
T2CON.7 TF2 - Timer 2 overflow flag. Hardware sets TF2 when the Timer 2 overflows from 0xFFFF. TF2 must be cleared to 0 by the software. TF2 is
only set to a ‘1’ if RCLK and TCLK are both cleared to ‘0’. Writing a one to TF2 forces a Timer 2 interrupt if enabled.
T2CON.6 EXF2 - Timer 2 external flag. Hardware sets EXF2 when a reload or capture is caused by a high-to-low transition on the T2EX pin, and
EXEN2 is set. EXF2 must be cleared to ‘0’ by software. Writing a one to EXF2 forces a Timer 2 interrupt, if enabled.
T2CON.5 RCLK - Receive clock flag. Determines whether Timer 1 or Timer 2 is used for Serial Port 0 timing of received data in serial mode 1 or 3.
RCLK=1 selects Timer 2 overflow as the receive clock; RCLK=0 selects Timer 1 overflow as the receive clock.
T2CON.4 TCLK - Transmit clock flag. Determines whether Timer 1 or Timer 2 is used for Serial Port 0 timing of transmit data in serial mode 1 or 3.
TCLK=1 selects Timer 2 overflow as the transmit clock; TCLK=0 selects Timer 1 overflow as the transmit clock.
T2CON.3 EXEN2 - Timer 2 external enable. EXEN2=1 enables capture or reload to occur as a result of a high-to-low transition on the T2EX pin, if
Timer 2 is not generating baud rates for the serial port. EXEN2=0 causes Timer 2 to ignore all external events on the T2EX pin.
T2CON.2 TR2 - Timer 2 run control flag. TR2=1 starts Timer 2; TR2=0 stops Timer 2.
T2CON.1 C/T2 - Counter/Timer select. When C/T2 = 1, Timer 2 is clocked by high-to-low transitions on the T2 pin.When C/T2 = 0 in modes 0, 1, or 2,
Timer 2 is clocked by CLKOUT/4 or CLKOUT/12, depending on the state of T2M (CKCON.5). When C/T2 = 0 in mode 3, Timer 2 is clocked
by CLKOUT/2, regardless of the state of CKCON.5.
T2CON.0 CP/RL2 - Capture/reload flag. When CP/RL2=1, Timer 2 captures occur on high-to-low transitions of the T2EX pin, if EXEN2 = 1. When CP/
RL2 = 0, auto-reloads occur when Timer 2 overflows or when high-to-low transitions occur on the T2EX pin, if EXEN2 = 1. If either RCLK or
TCLK is set to ‘1’, CP/RL2 does not function and Timer 2 operates in auto-reload mode following each overflow.
Table 14-6. Timer 2 Mode Control Summary
TR2 TCLK RCLK CP/RL2Mode
0 X X X Timer 2 stopped
1 1 X X Baud rate generator
1 X 1 X Baud rate generator
1 0 0 0 16 bit timer/counter with auto-reload
1 0 0 1 16 bit timer/counter with capture
X = Don’t care
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 199
Timers/Counters and Serial Interface
Figure 14-4. Timer 2 - Timer/Counter with Capture
14.2.6 Timer 2: 16 Bit Timer/Counter
Mode with Auto-Reload
When CP/RL2 = 0, Timer 2 is configured for the auto-reload
mode illustrated in Figure 14-5. Control of counter input is
the same as for the other 16 bit counter modes. When the
count increments from 0xFFFF, Timer 2 sets the TF2 flag
and the starting value is reloaded into TL2 and TH2. Soft-
ware must preload the starting value into the RCAP2L and
RCAP2H registers.
When Timer 2 is in auto-reload mode, a reload can be
forced by a high-to-low transition on the T2EX pin, if enabled
by EXEN2 = 1.
Figure 14-5. Timer 2 - Timer/Counter with Auto Reload
07
Divide by 12
Divide by 4
CLKOUT
T2 pin
TR2
CLK
70
EXF2
T2M
INT
RCAP2L
TL2 TH2
RCAP2H
815
815
EXEN2
T2EX pin
CAPTURE TF2
0
10
1
C/ T2
CP/RL2 = 1
07
Divide by
Divide by 4
CLKOUT
T2 pin
TR2
CLK
70
EXF2
T2M
INT
RCAP2L
TL2 TH2
RCAP2H
815
815
EXEN2
T2EX pin
TF2
0
10
1
C/ T2
CP/RL2 = 0
200 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Timers/Counters and Serial Interface
14.2.7 Timer 2: Baud Rate Generator
Mode
Set either RCLK or TCLK to ‘1’ to configure Timer 2 to gen-
erate baud rates for Serial Port 0 in serial mode 1 or 3.
Figure 14-6 on page 200 is the functional diagram for the
Timer 2 baud rate generator mode. In baud rate generator
mode, Timer 2 functions in auto-reload mode. However,
instead of setting the TF2 flag, the counter overflow is used
to generate a shift clock for the serial port function. As in
normal auto-reload mode, the overflow also causes the pre-
loaded start value in the RCAP2L and RCAP2H Registers to
be reloaded into the TL2 and TH2 Registers.
When either TCLK = 1 or RCLK = 1, Timer 2 is forced into
auto-reload operation, regardless of the state of the CP/RL2
Bit. Timer 2 is used as the receive baud clock source when
RCLK=1, and as the transmit baud clock source when
TCLK=1.
When operating as a baud rate generator, Timer 2 does not
set the TF2 Bit. In this mode, a Timer 2 interrupt can only be
generated by a high-to-low transition on the T2EX pin set-
ting the EXF2 Bit, and only if enabled by EXEN2 = 1.
The counter time base in baud rate generator mode is CLK-
OUT/2. To use an external clock source, set C/T2 to ‘1’ and
apply the desired clock source to the T2 pin.
Note The maximum frequency for an external clock source
on the T2 pin is 6 MHz.
Figure 14-6. Timer 2 - Baud Rate Generator Mode
Divide
by 2
T2
TR2
0
1
CLK
CLKOUT C/ T2
Divide by
16
Divide by
16
RX
CLOC
TX
CLOCK
TCL
0
0
1
Divide
by 2
0
1
1
TL2 TH2
EXF TIMER 2 INTERRUPT
EXEN2
T2EX
TIMER 1 OVERFLOW
07
70
RCAP2L RCAP2H
815
815
SMOD
RCL
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 201
Timers/Counters and Serial Interface
14.3 Serial Interface
The EZ-USB provides two serial ports. Serial Port 0 oper-
ates almost exactly as a standard 8051 serial port; depend-
ing on the configured mode (see Table 14-7), its baud-clock
source can be CLKOUT/4 or CLKOUT/12, Timer 1, Timer 2,
or the High-Speed Baud Rate Generator (see section 14.3.2
High-Speed Baud Rate Generator on page 202). Serial Port
1 is identical to Serial Port 0, except that it cannot use Timer
2 as its baud rate generator. The number of serial ports
available externally vary depending on the package. See
package information in Introducing EZ-USB® chapter on
page 13.
Each serial port can operate in synchronous or asynchro-
nous mode. In synchronous mode, the EZ-USB generates
the serial clock and the serial port operates in half duplex
mode. In asynchronous mode, the serial port operates in full
duplex mode. In all modes, the EZ-USB double buffers the
incoming data so that a byte of incoming data can be
received while firmware is reading the previously received
byte.
Each serial port can operate in one of four modes, as out-
lined in Table 14-7.
The registers associated with the serial ports are as follows.
(Registers PCON and EICON also include some functional-
ity which is not part of the Serial Interface).
■PCON (SFR 0x87) Bit 7, Serial Port 0 rate control
SMOD0 (Table 14-13 on page 203)
■SCON0 (SFR 0x98) Serial Port 0 control (Table 14-11 on
page 203)
■SBUF0 (SFR 0x99) Serial Port 0 transmit/receive buffer
■EICON (SFR 0xD8) Bit 7, Serial Port 1 rate control
SMOD1 (Table 14-12 on page 203)
■SCON1 (SFR 0xC0) Serial Port 1 control (Table 14-14
on page 203)
■SBUF1 (SFR 0xC1) Serial Port 1 transmit/receive buffer
■T2CON (SFR 0xC8) Baud clock source for modes 1 and
3 (RCLK and TCLK in Table 14-5 on page 198)
■UART230 (0xE608) High-Speed Baud Rate Generator
enable (see section 14.3.2 High-Speed Baud Rate Gen-
erator)
Table 14-7. Serial Port Modes
Mode Sync/ Async Baud-Clock Source Data Bits Start/
Stop 9th Bit Function
0 Sync CLKOUT/4 or CLKOUT/12 8 None None
1 Async Timer 1 (Ports 0 and 1),
Timer 2 (Port 0 only), or
High-Speed Baud Rate Generator (Ports 0 and 1)
8 1 start, 1 stop None
2 Async CLKOUT/32 or CLKOUT/64 9 1 start, 1 stop 0, 1, or parity
3 Async Timer 1 (Ports 0 and 1),
Timer 2 (Port 0 only), or
High-Speed Baud Rate Generator (Ports 0 and 1)
9 1 start, 1 stop 0, 1, or parity
Note: The High-Speed Baud Rate Generator provides 115.2K or 230.4K baud rates (see section 14.3.2 High-Speed Baud Rate
Generator on page 202).
202 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Timers/Counters and Serial Interface
14.3.1 803x/805x Compatibility
The implementation of the serial interface is similar to that of
the Dallas Semiconductor, DS80C320. Table 14-8 summa-
rizes the differences in serial interface implementation
between the Intel 8051, the Dallas Semiconductor
DS80C320, and the EZ-USB.
14.3.2 High-Speed Baud Rate Generator
The EZ-USB incorporates a high speed baud rate generator
which can provide 115.2K and 230.4K baud rates for either
or both serial ports, regardless of the EZ-USB’s internal
clock frequency (12, 24, or 48 MHz).
The high-speed baud rate generator is enabled for Serial
Port 0 by setting UART230.0 to ‘1’; it is enabled for Serial
Port 1 by setting UART230.1 to ‘1’.
When enabled, the high speed baud rate generator defaults
to 115.2K baud. To select 230.4K baud for Serial Port 0, set
SMOD0 (PCON.7) to ‘1’; for Serial Port 1, set SMOD1
(EICON.7) to ‘1’.
Note When the High-Speed Baud Rate Generator is
enabled for either serial port, neither port may use Timer 1
as its baud-clock source. Therefore, the allowable combina-
tions of baud clock sources for Modes 1 and 3 are listed
below.
14.3.3 Mode 0
Serial mode 0 provides synchronous, half duplex serial com-
munication. For Serial Port 0, serial data output occurs on
the RXD0OUT pin, serial data is received on the RXD0 pin,
and the TXD0 pin provides the shift clock for both transmit
and receive. For Serial Port 1, the corresponding pins are
RXD1OUT, RXD1, and TXD1.
The serial mode 0 baud rate is either CLKOUT/12 or CLK-
OUT/4, depending on the state of the SM2_0 bit (or SM2_1
for Serial Port 1). When SM2_0 = 0, the baud rate is CLK-
OUT/12, when SM2_0 = 1, the baud rate is CLKOUT/4.
Mode 0 operation is identical to the standard 8051. Data
transmission begins when an instruction writes to the
SBUF0 (or SBUF1) SFR. The USART shifts the data, LSB
first, at the selected baud rate, until the 8 bit value has been
shifted out.
Mode 0 data reception begins when the REN_0 (or REN_1)
bit is set and the RI_0 (or RI_1) bit is cleared in the corre-
sponding SCON SFR. The shift clock is activated and the
USART shifts data, LSB first, in on each rising edge of the
shift clock until eight bits have been received. One CLKOUT
cycle after the eighth bit is shifted in, the RI_0 (or RI_1) bit is
set and reception stops until the software clears the RI bit.
Figure 14-7 on page 204 through Figure 14-10 on page 205
illustrate Serial Port Mode 0 transmit and receive timing for
both low speed (CLKOUT/12) and high speed (CLKOUT/4)
operation. The figures show Port 0 signal names, RXD0,
RXD0OUT, and TXD0. The timing is the same for Port 1 sig-
nals RXD1, RXD1OUT, and TXD1, respectively.
Table 14-8. Serial Interface Implementation Comparison
Feature Intel 8051 Dallas
DS80C320 EZ-USB
Number of serial ports 1 2 2
Framing error detection not imple-
mented implemented not imple-
mented
Slave address compari-
son for multiprocessor
communication
not imple-
mented implemented not imple-
mented
Table 14-9. UART230 Register — Address 0xE608
Bit Function
UART230.7:2 Reserved
UART230.1 230UART1 - Enable high-speed baud rate generator for
serial port 1. When 230UART1 = 1, a 115.2K baud (if
SMOD1 = 0) or 230.4K baud (if SMOD1 = 1) clock is pro-
vided to serial port 1. When 230UART1 = 0, serial port 1’s
baud clock is provided by one of the sources shown in
Table 14-7 on page 201.
UART230.0 230UART0 - Enable high-speed baud rate generator for
serial port 0. When 230UART0 = 1, a 115.2K baud (if
SMOD0 = 0) or 230.4K baud (if SMOD0 = 1) clock is pro-
vided to serial port 0. When 230UART1 = 0, serial port 0’s
baud clock is provided by one of the sources shown in
Table 14-7 on page 201.
Table 14-10. Allowable Baud-Clock Combinations for
Modes 1 and 3
Port 0 Port 1
Timer 1 Timer 1
Timer 2 Timer 1
Timer 2 High Speed Baud Rate Generator
High Speed Baud Rate Generator High Speed Baud Rate Generator
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 203
Timers/Counters and Serial Interface
Table 14-11. SCON0 Register — SFR 98h
Bit Function
SCON0.7 SM0_0 - Serial Port 0 mode bit 0.
SCON0.6 SM1_0 - Serial Port 0 mode bit 1, decoded as:
SM0_0 SM1_0 Mode
0 0 0
0 1 1
1 0 2
1 1 3
SCON0.5 SM2_0 - Multiprocessor communication enable. In modes 2 and 3, this bit enables the multiprocessor communication feature. If SM2_0 = 1
in mode 2 or 3, then RI_0 is not activated if the received ninth bit is zero.
If SM2_0=1 in mode 1, then only RI_0 is activated if a valid stop is received. In mode 0, SM2_0 establishes the baud rate: when SM2_0=0,
the baud rate is CLKOUT/12; when SM2_0=1, the baud rate is CLKOUT/4.
SCON0.4 REN_0 - Receive enable. When REN_0=1, reception is enabled.
SCON0.3 TB8_0 - Defines the state of the 9th data bit transmitted in modes 2 and 3.
SCON0.2 RB8_0 - In modes 2 and 3, RB8_0 indicates the state of the 9th bit received. In mode 1, RB8_0 indicates the state of the received stop bit.
In mode 0, RB8_0 is not used.
SCON0.1 TI_0 - Transmit interrupt flag. Indicates that the transmit data word has been shifted out. In mode 0, TI_0 is set at the end of the 8th data bit.
In all other modes, TI_0 is set when the stop bit is placed on the TXD0 pin. TI_0 must be cleared by firmware.
SCON0.0 RI_0 - Receive interrupt flag. Indicates that serial data word has been received. In mode 0, RI_0 is set at the end of the 8th data bit. In mode
1, RI_0 is set after the last sample of the incoming stop bit, subject to the state of SM2_0. In modes 2 and 3, RI_0 is set at the end of the last
sample of RB8_0. RI_0 must be cleared by firmware.
Table 14-12. EICON (SFR 0xD8) SMOD1 Bit
Bit Function
EICON.7 SMOD1 - Serial Port 1 baud rate doubler enable. When SMOD1 = 1 the baud rate for Serial Port is doubled.
Table 14-13. PCON (SFR 0x87) SMOD0 Bit
Bit Function
PCON.7 SMOD0 - Serial Port 0 baud rate double enable. When SMOD0 = 1, the baud rate for Serial Port 0 is doubled.
Table 14-14. SCON1 Register—SFR C0h
Bit Function
SCON1.7 SM0_1 - Serial Port 1 mode bit 0.
SCON1.6 SM1_1 - Serial Port 1 mode bit 1, decoded as:
SM0_1 SM1_1 Mode
0 0 0
0 1 1
1 0 2
1 1 3
SCON1.5 SM2_1 - Multiprocessor communication enable. In modes 2 and 3, this bit enables the multiprocessor communication feature. If SM2_1 = 1
in mode 2 or 3, then RI_1 is not activated if the received ninth bit is ‘0’.
If SM2_1=1 in mode 1, then only RI_1 is activated if a valid stop is received. In mode 0, SM2_1 establishes the baud rate: when SM2_1=0,
the baud rate is CLKOUT/12; when SM2_1=1, the baud rate is CLKOUT/4.
SCON1.4 REN_1 - Receive enable. When REN_1=1, reception is enabled.
204 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Timers/Counters and Serial Interface
Figure 14-7. Serial Port Mode 0 Receive Timing - Low Speed Operation
Figure 14-8. Serial Port Mode 0 Receive Timing - High Speed Operation
Note At both low and high speed in Mode 0, data on RXD0 is sampled two CLKOUT cycles before the rising clock edge on
TXD0.
SCON1.3 TB8_1 - Defines the state of the ninth data bit transmitted in modes 2 and 3.
SCON1.2 RB8_1 - In modes 2 and 3, RB8_1 indicates the state of the ninth bit received. In mode 1, RB8_1 indicates the state of the received stop bit.
In mode 0, RB8_1 is not used.
SCON1.1 TI_1 - Transmit interrupt flag. Indicates that the transmit data word has been shifted out. In mode 0, TI_1 is set at the end of the eighth data
bit. In all other modes, TI_1 is set when the stop bit is placed on the TXD1 pin. TI_1 must be cleared by the software.
SCON1.0 RI_1 - Receive interrupt flag. Indicates that serial data word has been received. In mode 0, RI_1 is set at the end of the eighth data bit. In
mode 1, RI_1 is set after the last sample of the incoming stop bit, subject to the state of SM2_1. In modes 2 and 3, RI_1 is set at the end of
the last sample of RB8_1. RI_1 must be cleared by the software.
Table 14-14. SCON1 Register—SFR C0h
Bit Function
CLKOUT
D0 D1 D2 D3 D4 D5 D6 D7
RI
TXD0
RXD0
RXD0OUT
TI
D0 D1 D2 D3 D4 D5 D6 D7
CLKOUT
RI
TXD0
RXD0
RXD0OUT
TI
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 205
Timers/Counters and Serial Interface
Figure 14-9. Serial Port Mode 0 Transmit Timing - Low Speed Operation
Figure 14-10. Serial Port Mode 0 Transmit Timing - High Speed Operation
14.3.4 Mode 1
Mode 1 provides standard asynchronous, full-duplex com-
munication, using a total of 10 bits: one start bit, eight data
bits, and one stop bit. For receive operations, the stop bit is
stored in RB8_0 (or RB8_1). Data bits are received and
transmitted LSB first.
Mode 1 operation is identical to that of the standard 8051
when Timer 1 uses CLKOUT/12, (T1M=0, the default).
14.3.4.1 Mode 1 Baud Rate
The mode 1 baud rate is a function of timer overflow. Serial
Port 0 can use either Timer 1 or Timer 2 to generate baud
rates. Serial Port 1 can only use Timer 1. The two serial
ports can run at the same baud rate if they both use Timer 1,
or different baud rates if Serial Port 0 uses Timer 2 and
Serial Port 1 uses Timer 1.
Each time the timer increments from its maximum count
(0xFF for Timer 1 or 0xFFFF for Timer 2), a clock is sent to
the baud rate circuit. That clock is then divided by 16 to gen-
erate the baud rate.
When using Timer 1, the SMOD0 (or SMOD1) Bit selects
whether or not to divide the Timer 1 rollover rate by 2.
Therefore, when using Timer 1, the baud rate is determined
by the equation:
Equation 1
When using Timer 2, the baud rate is determined by the
equation:
Equation 2
CLKOUT
RI
TXD0
RXD0
RXD0OUT
TI
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
CLKOUT
RI
TXD0
RXD0
RXD0OUT
TI
Baud Rate 2SMODx
32
------------------Timer 1 Overflow=
Baud Rate Timer 2 Overflow
16
------------------------------------------=
206 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Timers/Counters and Serial Interface
To use Timer 1 as the baud rate generator, it is generally
best to use Timer 1 mode 2 (eight bit counter with auto-
reload), although any counter mode can be used. In mode 2,
the Timer 1 reload value is stored in the TH1 register, which
makes the complete formula for Timer 1:
Equation 3
To derive the required TH1 value from a known baud rate
when T1M=0, use the equation:
Equation 4
To derive the required TH1 value from a known baud rate
when T1M=1, use the equation:
Equation 5
Note Very low serial port baud rates may be achieved with
Timer 1 by enabling the Timer 1 interrupt, configuring Timer
1 to mode 1, and using the Timer 1 interrupt to initiate a 16
bit software reload.
Table 14-15 lists sample reload values for a variety of com-
mon serial port baud rates, using Timer 1 operating in mode
2 (TMOD.5:4=10) with a CLKOUT/4 clock source (T1M=1)
and the full timer rollover (SMOD1=1)
More accurate baud rates may be achieved by using Timer
2 as the baud rate generator. To use Timer 2 as the baud
rate generator, configure Timer 2 in auto-reload mode and
set the TCLK and/or RCLK bits in the T2CON SFR. TCLK
selects Timer 2 as the baud rate generator for the transmit-
ter; RCLK selects Timer 2 as the baud rate generator for the
receiver. The 16 bit reload value for Timer 2 is stored in the
RCAP2L and RCA2H SFRs, which makes the equation for
the Timer 2 baud rate:
Equation 6
To derive the required RCAP2H and RCAP2L values from a
known baud rate, use the equation:
Equation 7
When either RCLK or TCLK is set, the TF2 flag is not set on
a Timer 2 rollover and the T2EX reload trigger is disabled.
Table 14-16 lists sample RCAP2H:L reload values for a vari-
ety of common serial baud rates.
Baud Rate 2SMODx
32
------------------CLKOUT
12 8 T1M–256 TH1–
---------------------------------------------------------------------------
=
TH1 256 2SMODx CLKOUT
384 Baud Rate
-------------------------------------------------–=
TH1 256 2SMODx CLKOUT
128 Baud Rate
-------------------------------------------------–=
Baud Rate CLKOUT
32 65536 256 RCAP2HRCAP2L+–
---------------------------------------------------------------------------------------------------------------=
RCAP2HL 65536 CLKOUT
32 Baud Rate
-------------------------------------
=
Table 14-15. Timer 1 Reload Values for Common Serial Port Mode 1 Baud Rates
Nominal
Rate
CLKOUT = 12 MHz CLKOUT = 24 MHz CLKOUT = 48 MHz
TH1
Reload
Value
Actual
Rate Error
TH1
Reload
Value
Actual
Rate Error
TH1
Reload
Value
Actual
Rate Error
57600 FD 62500 +8.50% F9 53571 -6.99% F3 57692 +0.16%
38400 FB 37500 -2.34% F6 37500 -2.34% EC 37500 -2.34%
28800 F9 26786 -6.99% F3 28846 +0.16% E6 28846 +0.16%
19200 F6 18750 -2.34% EC 18750 -2.34% D9 19230 +0.16%
9600 EC 9375 -2.34% D9 9615 +0.16% B2 9615 +0.16%
4800 D9 4807 +0.16% B2 4807 +0.16% 64 4807 +0.16%
2400 B2 2403 +0.16% 64 2403 +0.16% — — —
Settings: SMOD=1, C/T=0, Timer1 Mode=2, T1M=1
Note Using rates that are off by 2% or more do not work in all systems.
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 207
Timers/Counters and Serial Interface
14.3.4.2 Mode 1 Transmit
Figure 14-11 on page 208 illustrates the mode 1 transmit
timing. In mode 1, the USART begins transmitting after the
first rollover of the divide-by-16 counter after the software
writes to the SBUF0 (or SBUF1) register. The USART trans-
mits data on the TXD0 (or TXD1) pin in the following order:
start bit, 8 data bits (LSB first), stop bit. The TI_0 (or TI_1)
bit is set 2 CLKOUT cycles after the stop bit is transmitted.
14.3.5 Mode 1 Receive
Figure 14-12 on page 208 illustrates the mode 1 receive tim-
ing. Reception begins at the falling edge of a start bit
received on the RXD0 (or RXD1) pin, when enabled by the
REN_0 (or REN_1) Bit. For this purpose, the RXD0 (or
RXD1) pin is sampled 16 times per bit for any baud rate.
When a falling edge of a start bit is detected, the divide-by-
16 counter used to generate the receive clock is reset to
align the counter rollover to the bit boundaries.
For noise rejection, the serial port establishes the content of
each received bit by a majority decision of 3 consecutive
samples in the middle of each bit time. For the start bit, if the
falling edge on the RXD0 (or RXD1) pin is not verified by a
majority decision of 3 consecutive samples (low), then the
serial port stops reception and waits for another falling edge
on the RXD0 (or RXD1) pin.
At the middle of the stop bit time, the serial port checks for
the following conditions:
■RI_0 (or RI_1) = 0
■If SM2_0 (or SM2_1) = 1, the state of the stop bit is 1
(If SM2_0 (or SM2_1) = 0, the state of the stop bit does
not matter.
If the above conditions are met, the serial port then writes
the received byte to the SBUF0 (or SBUF1) Register, loads
the stop bit into RB8_0 (or RB8_1), and sets the RI_0 (or
RI_1) Bit. If the above conditions are not met, the received
data is lost, the SBUF Register and RB8 Bit are not loaded,
and the RI Bit is not set.
After the middle of the stop bit time, the serial port waits for
another high-to-low transition on the (RXD0 or RXD1) pin.
Table 14-16. Timer 2 Reload Values for Common Serial Port Mode 1 Baud Rates
Nominal Rate
CLKOUT = 12 MHz CLKOUT = 24 MHz CLKOUT = 48 MHz
RCAP2H:L
Reload
Value
Actual
Rate Error
RCAP2H:L
Reload
Value
Actual
Rate Error
RCAP2H:L
Reload
Value
Actual
Rate Error
57600 FFF9 53571 -6.99% FFF3 57692 +0.16% FFE6 57692 +0.16%
38400 FFF6 37500 -2.34% FFEC 37500 -2.34% FFD9 38461 +0.16%
28800 FFF3 28846 +0.16% FFE6 28846 +0.16% FFCC 28846 +0.16%
19200 FFEC 18750 -2.34% FFD9 19230 +0.16% FFB2 19230 +0.16%
9600 FFD9 9615 +0.16% FFB2 9615 +0.16% FF64 9615 +0.16%
4800 FFB2 4807 +0.16% FF64 4807 +0.16% FEC8 4807 +0.16%
2400 FF64 2403 +0.16% FEC8 2403 +0.16% FD90 2403 +0.16%
Note using rates that are off by 2.3% or more do not work in all systems.
208 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Timers/Counters and Serial Interface
Figure 14-11. Serial Port 0 Mode 1 Transmit Timing
Figure 14-12. Serial Port 0 Mode 1 Receive Timing
14.3.6 Mode 2
Mode 2 provides asynchronous, full-duplex communication,
using a total of 11 bits: one start bit, eight data bits, a pro-
grammable ninth bit, and one stop bit. The data bits are
transmitted and received LSB first. For transmission, the
ninth bit is determined by the value in TB8_0 (or TB8_1). To
use the ninth bit as a parity bit, move the value of the P bit
(SFR PSW.0) to TB8_0 (or TB8_1).
The Mode 2 baud rate is either CLKOUT/32 or CLKOUT/64,
as determined by the SMOD0 (or SMOD1) bit. The formula
for the mode 2 baud rate is:
Equation 8
Mode 2 operation is identical to the standard 8051.
14.3.6.1 Mode 2 Transmit
Figure 14-13 on page 209 illustrates the mode 2 transmit
timing. Transmission begins after the first rollover of the
divide-by-16 counter following a software write to SBUF0 (or
SBUF1). The USART shifts data out on the TXD0 (or TXD1)
pin in the following order: start bit, data bits (LSB first), ninth
bit, stop bit. The TI_0 (or TI_1) Bit is set when the stop bit is
placed on the TXD0 (or TXD1) pin.
14.3.6.2 Mode 2 Receive
Figure 14-14 on page 209 illustrates the mode 2 receive tim-
ing. Reception begins at the falling edge of a start bit
received on the RXD0 (or RXD1) pin, when enabled by the
REN_0 (or REN_1) Bit. For this purpose, the RXD0 (or
RXD1) pin is sampled 16 times per bit for any baud rate.
When a falling edge of a start bit is detected, the divide-by-
Write to
SBUF0
RI_0
TXD0
RXD0
RXD0OUT
SHIFT
TX CLK
TI_0
D0 D1 D2 D3 D4 D5 D6 D7 STOP
START
RI_0
TXD0
RXD0
RXD0OUT
SHIFT
RX CLK
TI_0
D0 D1 D2 D3 D4 D5 D6 D7 STOP
START
Bit detector
sampling
Baud Rate 2SMODx CLKOUT
64
-------------------------------------------------=
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 209
Timers/Counters and Serial Interface
16 counter used to generate the receive clock is reset to
align the counter rollover to the bit boundaries.
For noise rejection, the serial port establishes the content of
each received bit by a majority decision of three consecutive
samples in the middle of each bit time. For the start bit, if the
falling edge on the RXD0 (or RXD1) pin is not verified by a
majority decision of three consecutive samples (low), then
the serial port stops reception and waits for another falling
edge on the RXD0 (or RXD1) pin.
At the middle of the stop bit time, the serial port checks for
the following conditions:
■RI_0 (or RI_1) = 0
■If SM2_0 (or SM2_1) = 1, the state of the stop bit is ‘1’.
(If SM2_0 (or SM2_1) = 0, the state of the stop bit does
not matter.)
If the above conditions are met, the serial port then writes
the received byte to the SBUF0 (or SBUF1) Register, loads
the stop bit into RB8_0 (or RB8_1), and sets the RI_0 (or
RI_1) Bit. If the above conditions are not met, the received
data is lost, the SBUF Register and RB8 Bit are not loaded,
and the RI Bit is not set. After the middle of the stop bit time,
the serial port waits for another high-to-low transition on the
RXD0 (or RXD1) pin.
Figure 14-13. Serial Port 0 Mode 2 Transmit Timing
Figure 14-14. Serial Port 0 Mode 2 Receive Timing
RI_0
TXD0
RXD0
RXD0OUT
SHIFT
TX CLK
TI_0
D0 D1 D2 D3 D4 D5 D6 D7 STOP
START
Write to
SBUF0
TB8
RI_0
TXD0
RXD0
RXD0OUT
SHIFT
RX CLK
TI_0
D0 D1 D2 D3 D4 D5 D6 D7 STOP
START RB8
Bit Detector
Sampling
210 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Timers/Counters and Serial Interface
14.3.7 Mode 3
Mode 3 provides asynchronous, full-duplex communication,
using a total of 11 bits: one start bit, eight data bits, a pro-
grammable ninth bit, and one stop bit. The data bits are
transmitted and received LSB first.
The mode 3 transmit and operations are identical to mode 2.
The mode 3 baud rate generation is identical to mode 1.
That is, mode 3 is a combination of mode 2 protocol and
mode 1 baud rate. Figure 14-15 illustrates the mode 3 trans-
mit timing. Figure 14-16 illustrates the mode 3 receive tim-
ing.
Mode 3 operation is identical to that of the standard 8051
when Timer 1 uses CLKOUT/12, (T1M=0, the default).
Figure 14-15. Serial Port 0 Mode 3 Transmit Timing
Figure 14-16. Serial Port 0 Mode 3 Receive Timing
RI_0
TXD0
RXD0
RXD0OUT
SHIFT
TX CLK
TI_0
D0 D1 D2 D3 D4 D5 D6 D7 STOP
START
Write to
SBUF0
TB8
RI_0
TXD0
RXD0
RXD0OUT
SHIFT
RX CLK
TI_0
D0 D1 D2 D3 D4 D5 D6 D7 STOP
START RB8
Bit Detector
Sampling
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 211
15. Registers
15.1 Introduction
This section describes the EZ-USB registers in the order they appear in the EZ-USB memory map, see Figure 5-4 on
page 76. The registers are named according to the following conventions.
Most registers deal with endpoints. The general register format is DDDnFFF, where:
DDD is endpoint direction where:
❐IN or OUT with respect to the USB host.
n is the endpoint number where:
❐’ISO’ indicates isochronous endpoints as a group.
FFF is the function where:
❐CS is a control and status register.
❐IRQ is an interrupt request bit.
❐IE is an interrupt enable bit.
❐BC, BCL, and BCH are byte count registers. BC is used for single byte counts, and BCH/BCL are used as the high and
low bytes of 16-bit byte counts.
❐DATA is a single-register access to a FIFO.
❐BUF is the start address of a buffer.
15.1.1 Example Register Format
❐EP1INBC is the Endpoint 1 IN byte count.
15.1.2 Other Conventions
USB indicates a global (not endpoint specific) USB function.
ADDR is an address.
VAL means valid.
FRAME is a frame count.
PTR is an address pointer.
212 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Registers
The register table above illustrates the register description format used in this chapter.
■The top line shows the register name, functional description, and address in the EZ-USB memory.
■The second line shows the bit position in the register.
■The third line shows the name of each bit in the register.
■The fourth line shows CPU accessibility: Read, Write, or R/W.
■The fifth line shows the default value. These values apply after a hard reset.
15.2 Special Function Registers
EZ-USB implements many control registers as SFRs (Special Function Registers). These SFRs are shown in Table 15-1.
Bold type indicates SFRs that are not in the standard 8051, but are included in the EZ-USB.
Register Name Register Function Address
b7 b6 b5 b4 b3 b2 b1 b0
bitname bitname bitname bitname bitname bitname bitname bitname
R, W access R, W access R, W access R, W access R, W access R, W access R, W access R, W access
Default val Default val Default val Default val Default val Default val Default val Default val
Table 15-1. EZ-USB Special Function Registers (SFR)
x8x 9x Ax Bx Cx Dx Ex Fx
0IOA IOB IOC IOD SCON1 PSW ACC B
1SP EXIF INT2CLR IOE SBUF1
2DPL0 MPAGE INT4CLR OEA
3DPH0 OEB
4DPL1 OEC
5DPH1 OED
6DPS OEE
7PCON
8 TCON SCON0 IE IP T2CON EICON EIE EIP
9 TMOD SBUF0
ATL0 AUTOPTRH1 EP2468STAT EP01STAT RCAP2L
BTL1 AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H
CTH0 EP68FIFOFLGS TL2
DTH1 AUTOPTRH2 GPIFSGLDATH TH2
ECKCON AUTOPTRL2 GPIFSGLDATLX
FAUTOPTR-SETUP GPIFSGLDATLNOX
All unlabeled SFRs are reserved.
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 213
SFR
15.3 About SFRs
Because the SFRs are directly addressable internal registers, firmware can access them quickly, without the overhead of
loading the data pointer and performing a MOVX instruction. For example, the firmware reads the EZ-USB Port B pins using
a single instruction, as shown below.
Single instruction to read port B:
mov a,IOB
In the same manner, firmware writes the value 0x55 to Port C using only one MOV instruction, as shown below.
Single instruction to read port C:
mov IOC,#55h
SFRs in rows 0 and 8 are bit-addressable; individual bits of the registers may be efficiently set, cleared, or toggled using spe-
cial bit-addressing instructions (for example, setb IOB.2 sets bit 2 of the IOB register).
IOA Port A (bit addressable) SFR 0x80
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
IOB Port B (bit addressable) SFR 0x90
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
AUTOPTRH1 Autopointer 1 Address HIGH SFR 0x9A
b7 b6 b5 b4 b3 b2 b1 b0
A15 A14 A13 A12 A11 A10 A9 A8
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
AUTOPTRL1 Autopointer 1 Address Low SFR 0x9B
b7 b6 b5 b4 b3 b2 b1 b0
A7 A6 A5 A4 A3 A2 A1 A0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
214 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
SFR
Writing any value to INT2CLR or INT4CLR clears the INT2 or INT4 interrupt request bit for the INT2/INT4 interrupt currently
being serviced.
Note Writing to one of these registers has the same effect as clearing the appropriate interrupt request bit in the EZ-USB
external register space. For example, suppose the EP2 Empty Flag interrupt is asserted. The EZ-USB automatically sets bit 1
of the EP2FIFOIRQ register (in External Data memory space, at 0xE651), and asserts the INT4 interrupt request.
Using autovectoring, the EZ-USB automatically calls (vectors to) the EP2_FIFO_EMPTY 2 Interrupt Service Routine (ISR).
The first task in the ISR is to clear the interrupt request bit, EP2FIFOIRQ.1. The firmware can do this either by accessing the
EP2FIFOIRQ register (at 0xE651) and writing a ‘1’ to bit 1, or simply by writing any value to INT4CLR. The first method
requires the use of the data pointer, which must be saved and restored along with the accumulator in an ISR. The second
method is much faster and does not require saving the data pointer, so it is preferred.
AUTOPTRH2 Autopointer 2 Address HIGH SFR 0x9D
b7 b6 b5 b4 b3 b2 b1 b0
A15 A14 A13 A12 A11 A10 A9 A8
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
AUTOPTRL2 Autopointer 2 Address Low SFR 0x9E
b7 b6 b5 b4 b3 b2 b1 b0
A7 A6 A5 A4 A3 A2 A1 A0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
IOC Port C (bit addressable) SFR 0xA0
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
INT2CLR Interrupt 2 Clear SFR 0xA1
b7 b6 b5 b4 b3 b2 b1 b0
xxxxxxxx
W W W W W W W W
x x x x x x x x
INT4CLR Interrupt 4 Clear SFR 0xA2
b7 b6 b5 b4 b3 b2 b1 b0
xxxxxxxx
W W W W W W W W
x x x x x x x x
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 215
SFR
The bits in EP2468STAT correspond to Endpoint Status bits in the EZ-USB register file, as follows:
Note The Endpoint status bits represent the Packet Status.
EZ-USB provides two identical autopointers. They are similar to the internal ‘DPTR’ data pointers, but with an additional fea-
ture: each can automatically increment after every memory access. Using one or both of the autopointers, EZ-USB firmware
can perform very fast block memory transfers.
The AUTOPTRSETUP register is configured as follows:
■Set APTRnINC=0 to freeze the address pointer, APTRnINC=1 to automatically increment it for every read or write of an
XAUTODATn register. This bit defaults to ‘1’, enabling the auto increment feature.
■To enable the autopointer, set APTREN=1. Enabling the Autopointers has one side-effect: any code access (an instruction
fetch, for instance) from addresses 0xE67B and 0xE67C return the AUTODATA values, rather than the code-memory val-
ues at these two addresses. This introduces a two-byte ‘hole’ in the code memory.
The firmware then writes a 16 bit address to AUTOPTRHn/Ln. Then, for every read or write of an XAUTODATn register, the
address pointer automatically increments (if APTRnINC=1).
EP2468STAT Endpoints 2,4,6,8 Status Flags SFR 0xAA
b7 b6 b5 b4 b3 b2 b1 b0
EP8F EP8E EP6F EP6E EP4F EP4E EP2F EP2E
R R R R R R R R
01011010
Table 15-2. SFR and EZ-USB Register File Correspondences
Bit EPSTAT SFR EZ-USB Register.Bit EZ-USB Register File address
7EP8 Full flag EP8CS.3 E6A6
6EP8 Empty flag EP8CS.2 E6A6
5EP6 Full flag EP6CS.3 E6A5
4EP6 Empty flag EP6CS.2 E6A5
3EP4 Full flag EP4CS.3 E6A4
2EP4 Empty flag EP4CS.2 E6A4
1EP2 Full flag EP2CS.3 E6A3
0EP2 Empty flag EP2CS.2 E6A3
EP24FIFOFLGS Endpoints 2, 4 Slave FIFO Status Flags SFR 0xAB
b7 b6 b5 b4 b3 b2 b1 b0
0EP4PF EP4EF EP4FF 0EP2PF EP2EF EP2FF
R R R R R R R R
00100010
EP68FIFOFLGS Endpoints 6, 8 Slave FIFO Status Flags SFR 0xAC
b7 b6 b5 b4 b3 b2 b1 b0
0EP8PF EP8EF EP8FF 0EP6PF EP6EF EP6FF
R R R R R R R R
01100110
AUTOPTRSETUP Autopointers 1 and 2 Setup SFR 0xAF
b7 b6 b5 b4 b3 b2 b1 b0
00000APTR2INC APTR1INC APTREN
R/W R/W R/W R/W R/W R/W R/W R/W
00000110
216 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
SFR
EZ-USB I/O ports PORTA-PORTD appear as bit addressable SFRs. Reading a register or bit returns the logic level of the port
pin that is two CLKOUT clocks old. Writing a register bit writes the port latch. Whether or not the port latch value appears on
the I/O pin depends on the state of the pin’s OE (Output Enable) bit. The I/O pins may also be assigned alternate function val-
ues, in which case the IOx and OEx bit values are overridden on a bit-by-bit basis.
IOD is bit-addressable. Use Bit 2 to set PORTD - single instruction:
setb IOD.2 ; set bit 2 of IOD SFR
I/O port PORTE is also accessed using an SFR, but unlike the PORTA-PORTD SFRs, it is not bit-addressable.
Use OR to set bit 3:
mov a,IOE
or a,#00001000b ; set bit 3
mov IOE,a
IOD Port D (bit addressable) SFR 0xB0
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
IOE Port E SFR 0xB1
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 217
SFR
The bits in 0EA - 0EE turn on the output buffers for the five I/O Ports PORTA-PORTE. Set a bit to ‘1’ to turn on the output buf-
fer, set it to ‘0’ to turn the buffer off.
OEA Port A Output Enable SFR 0xB2
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
OEB Port B Output Enable SFR 0xB3
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
OEC Port C Output Enable SFR 0xB4
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
OED Port D Output Enable SFR 0xB5
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
OEE Port E Output Enable SFR 0xB6
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
EP01STAT Endpoint 0 and 1 Status SFR 0xBA
b7 b6 b5 b4 b3 b2 b1 b0
00000EP1INBSY EP1OUTBSY EP0BSY
R R R R R R R R
00000000
218 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
SFR
Most of these SFR registers are also accessible in external RAM space, at the addresses shown in Table 15-3.
GPIFTRIG
see Section 15.15 Endpoint 2,4,6,8 GPIF Slave
FIFO Trigger SFR 0xBB
b7 b6 b5 b4 b3 b2 b1 b0
DONE 0 0 0 0 R/W EP1 EP0
R/W R R R R R/W R/W R/W
1 0 0 0 0 x x x
GPIFSGLDATH GPIF Data HIGH (16-bit mode only) SFR 0xBD
b7 b6 b5 b4 b3 b2 b1 b0
D15 D14 D13 D12 D11 D10 D9 D8
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
GPIFSGLDATLX GPIF Data Low w/Trigger SFR 0xBE
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
GPIFSGLDATLNOX GPIF Data Low w/No Trigger SFR 0xBF
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R R R R R R R R
x x x x x x x x
Table 15-3. SFR Registers and External Ram Equivalent
SFR Register Name Hex External Ram Register Address and Name
EP2468STAT AA E6A3-E6A6 EPxCS
EP24FIFOFLGS AB E6A7-E6AA EPxFIFOFLGS
EP68FIFOFLGS AC
EP01STAT BA E6A0-E6A2 EP0CS, EP1OUTCS, EP1INCS
GPIFTRIG BB E6D4, E6DC, E6E4, E6EC EPxGPIFTRIG
GPIFSGLDATH BD E6F0 XGPIFSGLDATH
GPIFSGLDATLX BE E6F1 XGPIFSGLDATLX
GPIFSGLDATLNOX BF E6F2 XGPIFSGLDATLNOX
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 219
WAVEDATA
E400-
15.4 GPIF Waveform Memories
15.4.1 WAVEDATA
GPIF Waveform Descriptor Data Register
*Accessible only when IFCFG1:0 = 10.
The four GPIF waveform descriptor tables are stored in this space. See the General Programmable Interface chapter on
page 121 for details.
WAVEDATA GPIF Waveform Descriptor 0, 1, 2, 3 Data E400-E47F*
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
220 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
CPUCS
E600
15.5 General Configuration Registers
15.5.1 CPUCS
CPU Control and Status Register
5PORTCSTB PORTC access generates RD and WR strobes.
The 100- and 128-pin EZ-USB packages have two output pins, RD and WR, that can be used to syn-
chronize data transfers on I/O PORTC. When PORTCSTB=1, this feature is enabled. Any read of
PORTC activates a RD strobe, and any write to PORTC activates a WR strobe. The RD and WR
strobes are asserted for two CLKOUT cycles; the WR strobe asserts two CLKOUT cycles after the
PORTC pins are updated.
If a design uses the 128-pin EZ-USB and connects off-chip memory to the address and data buses,
this bit should be set to zero. This is because the RD and WR pins are also the standard strobes used
to read and write off-chip memory, so normal reads/writes to I/O Port C disrupt normal accesses to
that memory.
4:3 CLKSPD[1:0] CPU Clock Speed
These bits set the CPU clock speed. On a hard reset, these bits default to ‘00’ (12 MHz). Firmware
may modify these bits at any time.
2CLKINV Invert CLKOUT Signal.
0 CLKOUT signal not inverted (as shown in all timing diagrams).
1 CLKOUT signal inverted.
1CLKOE Drive CLKOUT Pin.
0 CLKOUT pin floats.
1 CLKOUT pin driven.
0 8051RES 8051 Reset.
The USB host writes ‘1’ to this bit to reset the 8051, and ‘0’ to run the 8051. Only the USB host writes
to this bit (via the 0xA0 firmware load command).
CPUCS CPU Control and Status E600
b7 b6 b5 b4 b3 b2 b1 b0
0 0 PORTCSTB CLKSPD1 CLKSPD0 CLKINV CLKOE 8051RES
R R R/W R/W R/W R/W R/W R
00000010
Bit Name Description
CLKSPD1 CLKSPD0 CPU Clock
0 0 12 MHz (Default)
0 1 24 MHz
1 0 48 MHz
1 1 Reserved
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 221
IFCONFIG
E601
15.5.2 IFCONFIG
Interface Configuration (Ports, GPIF, Slave FIFOs) Register
7 IFCLKSRC FIFO/GPIF Clock Source.
This bit selects the clock source for both the FIFOS and GPIF.
0 The external clock on the IFCLK pin is selected.
1 An internal 30 or 48 MHz (default) clock is used (default).
6 3048MHZ Internal FIFO/GPIF Clock Frequency
This bit selects the internal FIFO and GPIF clock frequency.
0 30 MHz (default)
1 48 MHz
5 IFCLKOE IFCLK pin output enable.
0 Tri-state
1Drive
4 IFCLKPOL Invert the IFCLK signal.
This bit indicates that the IFCLK signal is inverted.
0 The clock has the polarity shown in all the timing diagrams in this manual.
1 The clock is inverted.
Figure 15-1. IFCLK Configuration
3 ASYNC Slave FIFO Asynchronous Mode.
0 The Slave FIFOs operate synchronously. A clock is supplied either internally or externally
on the IFCLK pin; the FIFO control signals function as read and write enable signals for the
clock signal.
1 The Slave FIFOs operate asynchronously. No clock signal input to IFCLK is required; the
FIFO control signals function directly as read and write strobes.
(continued on next page)
IFCONFIG Interface Configuration(Ports, GPIF, slave FIFOs) E601
b7 b6 b5 b4 b3 b2 b1 b0
IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0
R/W R/W R/W R/W R/W R/W R/W R/W
10000000
Bit Name Description
0
1
30 MHz
48 MHz 0
1
0
1
1
0
Internal
IFCLK
Signal
IFCFG.7
IFCFG.4
IFCFG.6 IFCFG.4 IFCFG.5
IFCLK
Pin
222 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
IFCONFIG
E601
15.5.2 IFCONFIG (continued)
2GSTATE Drive GSTATE [2:0] on PORTE [2:0]. When GSTATE = 1, three bits in Port E take on the signals
shown below. The GSTATE bits, which indicate GPIF states, are used for diagnostic purposes.
1:0 IFCFG[1:0] Select Interface Mode (Ports, GPIF, or Slave FIFO)
00 Ports
01 Reserved
10 GPIF Interface (internal master)
11 Slave FIFO Interface (external master)
These bits control the following EZ-USB interface signals, as shown below.
I/O Pin Alternate Function
PE0 GSTATE[0]
PE1 GSTATE[1]
PE2 GSTATE[2]
IFCFG[1:0] = 00
(Ports) IFCFG[1:0] = 10
(GPIF Master) IFCFG[1:0] = 11
(Slave FIFO)
PD7 FD[15] FD[15]
PD6 FD[14] FD[14]
PD5 FD[13] FD[13]
PD4 FD[12] FD[12]
PD3 FD[11] FD[11]
PD2 FD[10] FD[10]
PD1 FD[9] FD[9]
PD0 FD[8] FD[8]
PB7 FD[7] FD[7]
PB6 FD[6] FD[6]
PB5 FD[5] FD[5]
PB4 FD[4] FD[4]
PB3 FD[3] FD[3]
PB2 FD[2] FD[2]
PB1 FD[1] FD[1]
PB0 FD[0] FD[0]
INT0/PA0 INT0/PA0 INT0/PA0
INT1/PA1 INT1/PA1 INT1/PA1
PA2 PA2 SLOE
WU2/PA3 WU2/PA3 WU2/PA3
PA4 PA4 FIFOADR0
PA5 PA5 FIFOADR1
PA6 PA6 PKTEND
PA7 PA7 PA7/FLAGD/SLCS
PC7:0 PC7:0 PC7:0
PE7:0 PE7:0 PE7:0
Note Signals shown in bold type do not change with IFCFG; they are shown for completeness.
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 223
PINFLAGSxx
E602
15.5.3 PINFLAGSxx
Slave FIFO FLAGA-FLAGD Pin Configuration Registers
EZ-USB has four FIFO flag output pins, FLAGA, FLAGB, FLAGC and FLAGD. These flags can be programmed to represent
various FIFO flags using four select bits for each FIFO. The PINFLAGSAB register controls the FLAGA and FLAGB signals,
and the PINFLAGSCD register controls the FLAGC and FLAGD signal. The four bit coding for all four flags is the same, as
shown in Table 15-4 on page 223. In the ‘FLAGx’ notation, ‘x’ can be A, B, C or D.
Note FLAGD defaults to EP2PF (fixed flag).
(continued on next page)
PINFLAGSAB
see Section 15.15 Slave FIFO FLAGA and FLAGB Pin Configuration E602
b7 b6 b5 b4 b3 b2 b1 b0
FLAGB3 FLAGB2 FLAGB1 FLAGB0 FLAGA3 FLAGA2 FLAGA1 FLAGA0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
PINFLAGSCD
see Section 15.15 Slave FIFO FLAGC and FLAGD Pin Configuration E603
b7 b6 b5 b4 b3 b2 b1 b0
FLAGD3 FLAGD2 FLAGD1 FLAGD0 FLAGC3 FLAGC2 FLAGC1 FLAGC0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Table 15-4. FIFO Flag Pin Functions
FLAGx3 FLAGx2 FLAGx1 FLAGx0 Pin Function
0 0 0 0
FLAGA=PF, FLAGB=FF, FLAGC=EF, FLAGD=EP2PF
(Actual FIFO is selected by FIFOADR[0,1] pins)
0 0 0 1
0 0 1 0 Reserved
0 0 1 1
0 1 0 0 EP2 PF
0 1 0 1 EP4 PF
0 1 1 0 EP6 PF
0 1 1 1 EP8 PF
1 0 0 0 EP2 EF
1 0 0 1 EP4 EF
1 0 1 0 EP6 EF
1 0 1 1 EP8 EF
1 1 0 0 EP2 FF
1 1 0 1 EP4 FF
1 1 1 0 EP6 FF
1 1 1 1 EP8 FF
224 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
PINFLAGSxx
E602
15.5.3 PINFLAGSxx (continued)
For the default (0000) selection, the four FIFO flags are indexed as shown in the first table entry. The input pins FIFOADR1
and FIFOADR0 select to which of the four FIFOs the flags correspond. These pins are decoded as follows:
For example, if FLAGA[3:0]=0000 and the FIFO address pins are driven to [01], then FLAGA is the EP4-Programmable Flag,
FLAGB is the EP4-Full Flag, and FLAGC is the EP4-Empty Flag, and FLAGD defaults as PA7. Set PORTACFG.7 = 1 to use
FLAGD which by default is EP2PF(fixed flag).
The other (non-zero) values of FLAGx[3:0] allow the designer to independently configure the four flag outputs FLAGA-FLAGD
to correspond to any flag—Programmable, Full, or Empty—from any of the four endpoint FIFOS. This allows each flag to be
assigned to any of the four FIFOS, including those not currently selected by the FIFOADDR pins. For example, external logic
could be filling the EP2IN FIFO with data while also checking the full flag for the EP4OUT FIFO.
FIFOADR1 Pin FIFOADR0 Pin Selected FIFO
0 0 EP2
0 1 EP4
1 0 EP6
1 1 EP8
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 225
FIFORESET
E604
15.5.4 FIFORESET
FIFO Reset Register
Write 0x80 to this register to NAK all transfers from the host, then write 0x82, 0x84, 0x86, or 0x88 to continue to NAKALL and
reset an individual FIFO. This will restore endpoint FIFO flags and byte counts to their default states. Write 0x00 to restore
normal operation.
7 NAKALL NAK all.
NAK all transfers from the host.
3:0 EP3:0 Endpoint.
By writing the desired endpoint number (2,4,6,8), EZ-USB logic resets the individual endpoint.
FIFORESET
see Section 15.15 Restore FIFOs to Default State E604
b7 b6 b5 b4 b3 b2 b1 b0
NAKALL 0 0 0 EP3 EP2 EP1 EP0
W W W W W W W W
x x x x x x x x
Bit Name Description
226 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
BREAKPT
E605
15.5.5 BREAKPT
Breakpoint Register
3 Break Enable Breakpoint.
The BREAK bit is set when the CPU address bus matches the address held in the bit breakpoint
address registers (0xE606/07). The BKPT pin reflects the state of this bit. Write a ‘1’ to the BREAK bit
to clear it. It is not necessary to clear the BREAK bit if the pulse mode bit (BPPULSE) is set.
2 BPPULSE Breakpoint Pulse Mode.
Set this bit to ‘1’ to pulse the BREAK bit (and BKPT pin) high for eight CLKOUT cycles when the 8051
address bus matches the address held in the breakpoint address registers. When this bit is set to ‘0’,
the BREAK bit (and BKPT pin) remains high until it is cleared by firmware.
1 BPEN Breakpoint Enable.
If this bit is ‘1’, a BREAK signal is generated whenever the 16 bit address lines match the value in the
Breakpoint Address registers (BPADDRH:L). The behavior of the BREAK bit and associated BKP pin
signal is either latched or pulsed, depending on the state of the BPPULSE bit.
BREAKPT Breakpoint Control E605
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 BREAK BPPULSE BPEN 0
R R R R R/W R/W R/W R
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 227
BPADDRx
E606
15.5.6 BPADDRx
Breakpoint Address High, Breakpoint Address Low Registers
15:0 A[15:0] High and Low Breakpoint Address.
When the current 16 bit address (code or XDATA) matches the BPADDRH/BPADDRL address, a
breakpoint event occurs. The BPPULSE and BPEN bits in the BREAKPT register control the action
taken on a breakpoint event.
BPADDRH Breakpoint Address High E606
b7 b6 b5 b4 b3 b2 b1 b0
A15 A14 A13 A12 A11 A10 A9 A8
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
BPADDRL Breakpoint Address Low E607
b7 b6 b5 b4 b3 b2 b1 b0
A7 A6 A5 A4 A3 A2 A1 A0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
Bit Name Description
228 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
UART230
E607
15.5.7 UART230
230K Baud Clock (T0, T1, T2) Register
1:0 230UART[1:0] Set 230K Baud Operation.
Setting these bits to ‘1’ overrides the timer inputs to the USARTs, and USART0 and USART1 use the
230K baud clock rate. This mode provides the correct frequency to the USART regardless of the CPU
clock frequency (12, 24, or 48 MHz).
UART230 230K Baud Clock for T1 E608
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 230UART1 230UART0
R R R R R R R/W R/W
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 229
FIFOINPOLAR
E609
15.5.8 FIFOINPOLAR
Slave FIFO Interface Pins Polarity Register
5PKTEND FIFO Packet End Polarity. This bit selects the polarity of the PKTEND FIFO input pin.
0 Selects the polarity shown in the data sheet (active low)
1 Selects active high
4SLOE FIFO Output Enable Polarity. This bit selects the polarity of the SLOE FIFO input pin.
0 Selects the polarity shown in the data sheet (active low)
1 Selects active high
3SLRD FIFO Read Polarity. This bit selects the polarity of the SLRD FIFO input pin.
0 Selects the polarity shown in the data sheet (active low)
1 Selects active high
2SLWR FIFO Write Polarity. This bit selects the polarity of the SLWR FIFO input pin.
0 Selects the polarity shown in the data sheet (active low)
1 Selects active high
1EF Empty Flag Polarity. This bit selects the polarity of the Empty Flag output pin.
0 Selects the polarity shown in the data sheet (active low)
1 Selects active high
0FF Full Flag Polarity. This bit selects the polarity of the Full Flag output pin.
0 Selects the polarity shown in the data sheet (active low)
1 Selects active high.
FIFOPINPOLAR
see Section 15.15 Slave FIFO Interface Pins Polarity E609
b7 b6 b5 b4 b3 b2 b1 b0
0 0 PKTEND SLOE SLRD SLWR EF FF
R R R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
230 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
REVID
E60A
15.5.9 REVID
Chip Revision ID Register
7:0 RV[7:0] Chip Revision Number.
These register bits define the silicon revision.
REVID Chip Revision ID E60A
b7 b6 b5 b4 b3 b2 b1 b0
RV7 RV6 RV5 RV4 RV3 RV2 RV1 RV0
R R R R R R R R
00000001
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 231
REVCTL
E60B
15.5.10 REVCTL
Chip Revision Control Register
Note DYN_OUT and ENH_PKT default to ‘0’ on a hard reset. Cypress highly recommends setting both bits to ‘1’.
1DYN_OUT Disable Auto-Arming at the 0-1 transition of AUTOOUT.
0 The core automatically arms the endpoints when AUTOOUT is switched from ‘0’ to ‘1’. This
means that firmware must reset the endpoint (and risk losing endpoint data) when switching
between Auto-Out mode and Manual-Out mode.
1 The core disables auto-arming of the endpoints when AUTOOUT transitions from ‘0’ to ‘1’.
This feature allows CPU intervention when switching between AUTO and Manual mode
without having to reset the endpoint.
Note When DYN_OUT = 1 and AUTOOUT = 1, the CPU is responsible for ‘priming the
pump’ by initially arming the endpoints (OUTPKTEND w/SKIP = 1 to pass packets to host).
0 ENH_PKT Enhanced Packet Handling.
0 The CPU can neither source OUT packets nor skip IN packets; it has only the following
capabilities.
OUT packets: Skip or Commit
IN packets: Commit or Edit/Source
1 The CPU has additional capabilities:
OUT packets: Skip, Commit, or Edit/Source
IN packets: Skip, Commit, or Edit/Source
REVCTL
See Section 15.15 Chip Revision Control E60B
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 DYN_OUT ENH_PKT
R R R R R R R/W R/W
00000000
Bit Name Description
232 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
GPIFHOLDAMOUNT
E60C
15.5.11 GPIFHOLDAMOUNT
GPIF Hold Time Register
For any transaction where the GPIF writes data onto FD[15:0], this register determines how long the data is held. Valid
choices are ‘0’, ‘½’, or ‘1’ IFCLK cycle. This register applies to any data written by the GPIF to FD[15:0], whether through a
flow state or not.
For non-flow states, the hold amount is really just a delay of the normal (non-held) presentation of FD[15:0] by the amount
specified in HOLDTIME[1:0].
For flow states in which the GPIF is the master on the bus (FLOWSTB.SLAVE = 0), the hold amount is with respect to the
activating edge (see FLOW_MASTERSTB_EDGE) of Master strobe (which is a CTL pin in this case).
For flow states in which the GPIF is the slave on the bus (FLOWSTB.SLAVE = 1), the hold amount is really just a delay of the
normal (non-held) presentation of FD[15:0] by the amount specified in HOLDTIME[1:0] in reaction to the activating edge of
master strobe (which is a RDY pin in this case). Note the hold amount is NOT directly with respect to the activating edge of
master Strobe in this case. It is with respect to when the data normally comes out in response to master strobe including any
latency to synchronize master strobe.
In all cases, the data is held for the desired amount even if the ensuing GPIF state calls for the data bus to be tri-stated. In
other words the FD[15:0] output enable is held by the same amount as the data itself.
1:0 HOLDTIME[1:0] GPIF Hold Time.
00 0 IFCLK cycles
01 ½ IFCLK cycle
10 1 IFCLK cycle
11 Reserved
GPIFHOLDAMOUNT E60C
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 HOLDTIME[1:0]
R R R R R R RW RW
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 233
EP1OUTCFG
E610
15.6 Endpoint Configuration
15.6.1 EP1OUTCFG
Endpoint 1-OUT Configuration Register
7VALID Activate an Endpoint. Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All EZ-
USB endpoints default to VALID. An endpoint whose VALID bit is ‘0’ does not respond to any USB
traffic.
5:4 TYPE[1:0] Defines the Endpoint Type.
00 Invalid
01 Invalid
10 Bulk (default)
11 Interrupt
EP1OUTCFG Endpoint 1-OUT Configuration E610
b7 b6 b5 b4 b3 b2 b1 b0
VALID 0TYPE1 TYPE0 0 0 0 0
R/W RR/W R/W R R R R
10100000
Bit Name Description
234 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP1INCFG
E611
15.6.2 EP1INCFG
Endpoint 1-IN Configuration Register
7VALID Activate an Endpoint. Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All EZ-
USB endpoints default to VALID. An endpoint whose VALID bit is ‘0’ does not respond to any USB
traffic.
5:4 TYPE[1:0] Defines the Endpoint Type.
00 Invalid
01 Invalid
10 Bulk (default)
11 Interrupt
EP1INCFG Endpoint 1-IN Configuration E611
b7 b6 b5 b4 b3 b2 b1 b0
VALID 0TYPE1 TYPE0 0 0 0 0
R/W RR/W R/W R R R R
10100000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 235
EPxCFG
E612
15.6.3 EPxCFG
Endpoint 2, 4, 6 and 8 Configuration Registers
These registers configure the large, data handling EZ-USB endpoints.
7VALID Activate an Endpoint.
0 Deactivate an endpoint. An endpoint whose VALID bit is 0 does not respond to any USB
traffic.
1 Activate an endpoint (default)
6DIR Sets Endpoint Direction.
0OUT
1IN
5:4 TYPE[1:0] Defines the Endpoint Type. The TYPE bits apply to all of the large-endpoint configuration registers.
00 Invalid
01 Isochronous
10 Bulk (default)
11 Interrupt
3SIZE Sets Size of Endpoint Buffer. Endpoints 4 and 8 can only be 512 bytes. Endpoints 2 and 6 are
selectable.
0 512 bytes
1 1024 bytes
(continued on next page)
EP2CFG Endpoint 2 Configuration E612
b7 b6 b5 b4 b3 b2 b1 b0
VALID DIR TYPE1 TYPE0 SIZE 0BUF1 BUF0
R/W R/W R/W R/W R/W RR/W R/W
10100010
EP4CFG Endpoint 4 Configuration E613
b7 b6 b5 b4 b3 b2 b1 b0
VALID DIR TYPE1 TYPE0 0 0 0 0
R/W R/W R/W R/W R R R R
10100000
EP6CFG Endpoint 6 Configuration E614
b7 b6 b5 b4 b3 b2 b1 b0
VALID DIR TYPE1 TYPE0 SIZE 0BUF1 BUF0
R/W R/W R/W R/W R/W RR/W R/W
11100010
EP8CFG Endpoint 8 Configuration E615
b7 b6 b5 b4 b3 b2 b1 b0
VALID DIR TYPE1 TYPE0 0 0 0 0
R/W R/W R/W R/W R R R R
11100000
Bit Name Description
236 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EPxCFG
E612
15.6.3 EPxCFG (continued)
1:0 BUF[1:0] Buffering Type/Amount.
00 Quad
01 Invalid
10 Double
11 Triple
Note The Valid bit is ignored when buffer space is allocated by the EZ-USB (for example, BUF[1:0] takes precedence over the Valid bit).
When you are not using all of the endpoints in the endpoint configuration, disable the unused endpoints by writing a zero into the “valid” bit of
the corresponding EPxCFG register without disturbing the default state of the other bits in the register.
For example, if the endpoint configuration 11 (see 1.17 EZ-USB Endpoint Buffers on page 30), which uses only endpoints 2 and 8, must be
used, configure the endpoints as follows.
EP2CFG = 0xDB;
SYNCDELAY;
EP8CFG = 0x92;
SYNCDELAY;
EP4CFG &= 0x7F;
SYNCDELAY;
EP6CFG &=0x7F;
SYNCDELAY;
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 237
EPxFIFOCFG
E618
15.6.4 EPxFIFOCFG
Endpoint 2, 4, 6 and 8/Slave FIFO Configuration Registers
6INFM1 IN Full Minus One.
When a FIFO configuration register’s ‘INEARLY’ or INFM bit is set to ‘1’, the FIFO flags for that end-
point become valid one sample earlier than when the FULL condition occurs. These bits take effect
only when the FIFOs are operating synchronously—according to an internally or externally supplied
clock. Having the FIFO flag indications a clock early simplifies some synchronous interfaces (applies
only to IN endpoints).
5OEP1 OUT Empty Plus One.
When a FIFO configuration register’s ‘OUTEARLY’ or OEP1 bit is set to ‘1’, the FIFO flags for that
end point become valid one sample earlier than when the EMPTY condition occurs. These bits take
effect only when the FIFOS are operating synchronously—according to an internally or externally
supplied clock. Having the FIFO flag indications a clock early simplifies some synchronous interfaces
(applies only to OUT endpoints).
4 AUTOOUT Instantaneous Connection to Endpoint FIFO. This bit applies only to OUT endpoints.
0 As soon as a buffer fills with USB data, an endpoint interrupt is asserted. The connection of
the buffer to the endpoint FIFO is under control of the firmware, rather than automatically
being connected. Using this method, the firmware can inspect the data in OUT packets, and
based on what it finds, choose to include that packet in the endpoint FIFO or not. The firm-
ware can even modify the packet data, and then commit it to the endpoint FIFO. Refer to
Enhanced Packet Handling in section Chip Revision Control Register on page 231.
1 As soon as a buffer fills with USB data, the buffer is automatically and instantaneously com-
mitted to the endpoint FIFO bypassing the CPU. The endpoint FIFO flags and buffer counts
immediately indicate the change in FIFO status. Refer to the description of the DYN_OUT
bit in section Chip Revision Control Register on page 231.
The SKIP bit (in the EPxBCL registers) chooses between skipping and committing packet data. Refer
to OUTPKTEND in section Force OUT Packet End Register on page 255.
(continued on next page)
EP2FIFOCFG
see Section 15.15 Endpoint 2/Slave FIFO Configuration E618
EP4FIFOCFG
see Section 15.15 Endpoint 4/Slave FIFO Configuration E619
EP6FIFOCFG
see Section 15.15 Endpoint 6/Slave FIFO Configuration E61A
EP8FIFOCFG
see Section 15.15 Endpoint 8/Slave FIFO Configuration E61B
b7 b6 b5 b4 b3 b2 b1 b0
0INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE
RR/W R/W R/W R/W R/W RR/W
00000101
Bit Name Description
238 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EPxFIFOCFG
E618
15.6.4 EPxFIFOCFG (continued)
3 AUTOIN Auto Commit to SIE. This bit applies only to IN endpoints.
EZ-USB has EPxAUTOINLEN registers that allow the firmware to configure endpoints to sizes
smaller than the physical memory sizes used to implement the endpoint buffers (512 or 1024 bytes).
For example, suppose the firmware configures the EP2 buffer to be 1024 bytes (this must match the
wMaxPacketSize value in the endpoint descriptor), and then sets up EP2 as a 760 byte endpoint by
setting EP2AUTOINLEN=760. This makes EP2 appear to be a 760 byte endpoint to the USB host,
even though EP2's physical buffer is 1024 bytes.
0 Each packet has to initially be manually committed to SIE, (prime the pump). See section
Chip Revision Control Register on page 231.
1 EZ-USB automatically packetizes and dispatches IN packets according to the packet length
value it finds in the EPxAUTOINLEN registers. In this example, the GPIF (or an external
master, if the EZ-USB is in Slave FIFO mode) could load the EP2 buffer with 950 bytes,
which the EZ-USB logic would then automatically send as two packets, of 760 and 190
bytes. Refer to Enhanced Packet Handling in section Chip Revision Control Register on
page 231.
2 ZEROLENIN Enable Zero length IN Packets.
0 Zero length packets are sent on PKTEND.
1 A zero length packet is sent when PKTEND is activated and there are no bytes in the cur-
rent packet.
0WORDWIDE Select Byte/Word FIFOs on PORTB/D Pins.
This bit selects byte or word FIFOS on the PORTB and PORTD pins. The WORD bit applies ‘for
IFCFG =11 or 10’.
The OR of all four WORDWIDE bits is what causes PORTD to be PORTD or FD[15:8]. The individual
WORDWIDE bits indicate how data is to be passed for each individual endpoint.
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 239
EP2AUTOINLENH
E620
15.6.5 EP2AUTOINLENH
Endpoint 2 AUTOIN Packet Length High Register
2:0 PL10:8 Packet Length High.
High three bits of Packet Length.
EP2AUTOINLENH
see Section 15.15 Endpoint 2 AUTOIN Packet Length High E620
b7 b6 b5 b4 b3 b2 b1 b0
00000PL10 PL9 PL8
R R R R R R/W R/W R/W
00000010
Bit Name Description
240 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP6AUTOINLENH
E624
15.6.6 EP6AUTOINLENH
Endpoint 6 AUTOIN Packet Length High Register
2:0 PL[10:8] Packet Length High.
High three bits of Packet Length.
EP6AUTOINLENH
see Section 15.15 Endpoint 6 AUTOIN Packet Length High E624
b7 b6 b5 b4 b3 b2 b1 b0
00000PL10 PL9 PL8
R R R R R R/W R/W R/W
00000010
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 241
EP4AUTOINLENH
E622
15.6.7 EP4AUTOINLENH
Endpoint 4 AUTOIN Packet Length High Register
1:0 PL[9:8] Packet Length High.
High two bits of Packet Length.
EP4AUTOINLENH
see Section 15.15 Endpoint 4 AUTOIN Packet Length High E622
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 PL9 PL8
R R R R R R R/W R/W
00000010
Bit Name Description
242 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP8AUTOINLENH
E626
15.6.8 EP8AUTOINLENH
Endpoint 8 AUTOIN Packet Length High Register
1:0 PL[9:8] Packet Length High.
High two bits of Packet Length.
EP8AUTOINLENH
see Section 15.15 Endpoint 8 AUTOIN Packet Length High E626
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 PL9 PL8
R R R R R R R/W R/W
00000010
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 243
EPxAUTOINLENL
E621
15.6.9 EPxAUTOINLENL
Endpoint 2, 4, 6, 8 AUTOIN Packet Length Low Registers
7:0 PL[7:0] Packet Length Low. Low eight bits of packet length.
These registers can be used to set smaller packet sizes than the physical buffer size (refer to the pre-
viously described EPxCFG registers). The default packet size is 512 bytes for all endpoints. Note that
EP2 and EP6 can have maximum sizes of 1024 bytes, and EP4 and EP8 can have maximum sizes of
512 bytes, to be consistent with the endpoint structure.
EP2AUTOINLENL
see Section 15.15 Endpoint 2 AUTOIN Packet Length Low E621
EP4AUTOINLENL
see Section 15.15 Endpoint 4 AUTOIN Packet Length Low E623
EP6AUTOINLENL
see Section 15.15 Endpoint 6 AUTOIN Packet Length Low E625
EP8AUTOINLENL
see Section 15.15 Endpoint 8 AUTOIN Packet Length Low E627
b7 b6 b5 b4 b3 b2 b1 b0
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
244 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EPxFIFOPFH
E630
15.6.10 EPxFIFOPFH
Endpoint 2, 6/Slave FIFO Programmable Level Flag High Registers
Note Buffer size is in bytes: 64 = Full speed Bulk/Int; 1023 = Full speed ISO, 1024 = High speed ISO/Int; 512 = All others.
These registers control the point at which the programmable flag (PF) is asserted for each of the four endpoint FIFOs. The
EPxFIFOPFH:L fields are interpreted differently for OUT and IN endpoints.
The polarity of the programmable flag pin depends on the DECIS bit. If DECIS=0, then PF goes high when the byte count is
equal to, or less than what is defined in the PF registers. If DECIS=1, (default) then PF goes high when the byte count is
equal to, or greater than what is set in the PF register. For OUT endpoints, the byte count is the total number of bytes in the
FIFO that are available to the external master. For IN endpoints, the byte count is determined by PKTSTAT bit as explained
below.
(continued on next page)
EP2FIFOPFH
see Section 15.15 Endpoint 2/Slave FIFO Programmable-Level Flag High
[High-Speed (480 Mbps) Mode and
Full-Speed (12 Mbps) Iso Mode]
E630
b7 b6 b5 b4 b3 b2 b1 b0 Buffer Size
DECIS PKTSTAT
IN: PKTS[2] IN: PKTS[1] IN: PKTS[0]
0PFC9 PFC8 1024
OUT:PFC12 OUT:PFC11 OUT:PFC10
PFC11 PFC10 PFC9 PFC8 512
R/W R/W R/W R/W R/W RR/W R/W
10001000
EP2FIFOPFH
see Section 15.15 Endpoint 2/Slave FIFO Programmable-Level Flag High
[Full-Speed (12 Mbps) Non-Iso Mode] E630
b7 b6 b5 b4 b3 b2 b1 b0 Buffer Size
DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0PFC9 IN: PKTS[2]
OUT:PFC8 64
R/W R/W R/W R/W R/W RR/W R/W
10001000
EP6FIFOPFH
see Section 15.15
Endpoint 6/Slave FIFO Programmable-Level Flag High
[High-Speed (480 Mbps) Mode and
Full-Speed (12 Mbps) Iso Mode]
E634
b7 b6 b5 b4 b3 b2 b1 b0 Buffer Size
DECIS PKTSTAT
IN: PKTS[2] IN: PKTS[1] IN: PKTS[0]
0PFC9 PFC8 1024
OUT:PFC12 OUT:PFC11 OUT:PFC10
PFC11 PFC10 PFC9 PFC8 512
R/W R/W R/W R/W R/W R/W R/W R/W
00001000
EP6FIFOPFH
see Section 15.15 Endpoint 6/Slave FIFO Programmable-Level Flag High
[Full-Speed (12 Mbps) Non-Iso Mode] E634
b7 b6 b5 b4 b3 b2 b1 b0 Buffer Size
DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0PFC9 IN: PKTS[2]
OUT:PFC8 64
R/W R/W R/W R/W R/W R/W R/W R/W
00001000
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 245
EPxFIFOPFH
E634
15.6.10 EPxFIFOPFH (continued)
Each FIFO’s programmable-level flag asserts when the FIFO reaches a user-defined fullness threshold. That threshold is
configured as follows:
1. For OUT packets: The threshold is stored in PFC12:0. The PF is asserted when the number of bytes in the entire FIFO is
less than/equal to (DECIS = 0) or greater than/equal to (DECIS = 1) the threshold.
2. For IN packets, with PKTSTAT = 1: The threshold is stored in PFC9:0. The PF is asserted when the number of bytes writ-
ten into the current, not-yet-committed packet in the FIFO is less than/equal to (DECIS = 0) or greater than/equal to
(DECIS = 1) the threshold.
3. For IN packets, with PKTSTAT = 0: The threshold is stored in two parts: PKTS2:0 holds the number of committed packets,
and PFC9:0 holds the number of bytes in the current, not-yet-committed packet. The PF is asserted when the FIFO is at
or less full than (DECIS = 0), or at or more full than (DECIS=1), the threshold.
By default, FLAGA is the programmable-level flag for the endpoint currently pointed to by the FIFOADR[1:0] pins. For EP2
and EP4, the default endpoint configuration is BULK, OUT, 512, 2x, and the PF pin asserts when the entire FIFO has greater
than/equal to 512 bytes. For EP6 and EP8, the default endpoint configuration is BULK, IN, 512, 2x, and the PF pin asserts
when the entire FIFO has less than/equal to 512 bytes.
In other words, the default-configuration PFs for EP2 and EP4 assert when the FIFOs are half-full, and the default configura-
tion PFs for EP6 and EP8 assert when those FIFOs are half-empty.
In the first example below, bits 5-3 have data that is required to complete the transfer. In the second example, bits 5-3 do not
matter - those bits are don’t cares because PKTSTAT = 1:
Example 1:
Assume a Bulk IN transfer over Endpoint 2 and PKTSTAT = 0:
■EP2FIFOPFH = 0001 0000
❐b6 = 0 (or PKTSTAT = 0): this indicates that the transfer includes packets (as defined by bits 5, 4, and 3) plus bytes
(the sum in the flag low register)
❐b5b4b3 = 010 binary (or 2 decimal): this indicates the number of packets to expect during the transfer (in this case,
two packets…)
■EP2FIFOPFL = 0011 0010
❐…plus 50 bytes in the currently filling packet
(the sum of the binary bits in the EP2FIFOPFL register is 2 +16 + 32 = 50 decimal)
DECIS = 0, thus PF activates when the FIFO is at or less full than 2 PKTS + 50 bytes.
Example 2:
To perform an IN transfer of a number over the same endpoint, set PKTSTAT = 1 and write a value into the EP2FIFOPFL reg-
ister:
■EP2FIFOPFH = 0100 0000
■EP2FIFOPFL = 0100 1011 (75 bytes)
Setting PKTSTAT = 1 causes the PF decision to be based on the byte count alone, ignoring the packet count. This mode is
valuable for double-buffered endpoints, where only the byte count of the currently-filling packet is important.
DECIS = 0, thus PF is asserted when the currently filling packet is at or less than 75 bytes.
1:0 PFC[9:8] PF Threshold.
Bits 1:0 of EP2FIFOPFH are bits 9:8 of the byte count register.
Bit Name Description
246 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EPxFIFOPFH
E632
Endpoint 4, 8 Slave FIFO Programmable Level Flag High Registers
.
Refer to the discussion for EP2FIFOPFH.
7DECIS PF Polarity.
See EP2FIFOPFH and EP6FIFOPFH register definition.
6PKSTAT Packet Status.
See EP2FIFOPFH and EP6FIFOPFH register definition.
Bit 4-3 PKTS1:0 / PFC10:9 PF Threshold.
See EP2FIFOPFH and EP6FIFOPFH register definition.
Bit 0 PFC8 PF Threshold.
See EP2FIFOPFH and EP6FIFOPFH register definition.
EP4FIFOPFH
see Section
15.15
Endpoint 4/Slave FIFO Programmable-Level Flag HIGH
[High-Speed (480 Mbps) Mode and
Full-Speed (12 Mbps) Iso Mode]
E632
b7 b6 b5 b4 b3 b2 b1 b0
DECIS PKTSTAT 0IN: PKTS[1]
OUT:PFC10
IN: PKTS[0]
OUT:PFC9
0 0 PFC8
R/W R/W RR/W R/W R R R/W
10001000
EP4FIFOPFH
see Section
15.15
Endpoint 4/Slave FIFO Programmable-Level Flag HIGH
[Full-Speed (12 Mbps) Non-Iso Mode] E632
b7 b6 b5 b4 b3 b2 b1 b0
DECIS PKTSTAT 0OUT:PFC10 OUT:PFC9 0 0 PFC8
R/W R/W RR/W R/W R R R/W
10001000
EP8FIFOPFH
see Section
15.15
Endpoint 8/Slave FIFO Programmable-Level Flag HIGH
[High-Speed (480 Mbps) Mode and
Full-Speed (12 Mbps) Iso Mode]
E636
b7 b6 b5 b4 b3 b2 b1 b0
DECIS PKTSTAT 0IN: PKTS[1]
OUT:PFC10
IN: PKTS[0]
OUT:PFC9
0 0 PFC8
R/W R/W RR/W R/W R R R/W
00001000
EP8FIFOPFH
see Section
15.15
Endpoint 8/Slave FIFO Programmable-Level Flag HIGH
[Full-Speed (12 Mbps) Non-Iso Mode] E636
b7 b6 b5 b4 b3 b2 b1 b0
DECIS PKTSTAT 0OUT:PFC10 OUT:PFC9 0 0 PFC8
R/W R/W RR/W R/W R R R/W
00001000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 247
EPxFIFOPFL
E631
15.6.11 EPxFIFOPFL
Endpoint 2, 4, 6, 8/Slave FIFO Programmable Level Flag Low Registers
7:0 PFC[7:0] PF Threshold. This register contains the current packet bytes to be transferred when the EPxFI-
FOPFH register requires data.
Note Bits 9:8 of the byte count are in bits 1:0 of EP2FIFOPFH/EP6FIFOPFH.
Note Bit 8 of the byte count is bit 0 of EP4FIFOPFH/EP8FIFOPFH.
EP2FIFOPFL
see Section 15.15 Endpoint 2/Slave FIFO Prog. Flag Low E631
EP4FIFOPFL
see Section 15.15 Endpoint 4/Slave FIFO Prog. Flag Low E633
EP6FIFOPFL
see Section 15.15 Endpoint 6/Slave FIFO Prog. Flag Low E635
EP8FIFOPFL
see Section 15.15 Endpoint 8/Slave FIFO Prog. Flag Low
[High-Speed (480 Mbps) Mode and
Full-Speed (12 Mbps) Iso Mode]
E637
b7 b6 b5 b4 b3 b2 b1 b0
PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
EP2FIFOPFL
see Section 15.15 Endpoint 2/Slave FIFO Prog. Flag Low E631
EP4FIFOPFL
see Section 15.15 Endpoint 4/Slave FIFO Prog. Flag Low E633
EP6FIFOPFL
see Section 15.15 Endpoint 6/Slave FIFO Prog. Flag Low E635
EP8FIFOPFL
see Section 15.15 Endpoint 8/Slave FIFO Prog. Flag Low
[Full-Speed (12 Mbps) Non-Iso Mode] E637
b7 b6 b5 b4 b3 b2 b1 b0
IN: PKTS[1]
OUT:PFC7
IN: PKTS[0]
OUT:PFC6
PFC5 PFC4 PFC3 PFC2 PFC1 PFC0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
248 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EPxFIFOPFL
E631
15.6.11.1 IN Endpoints
For IN endpoints, the Trigger registers can apply to either the full FIFO, comprising multiple packets, or only to the current
packet being filled. The PKTSTAT bit controls this choice.
Example 1:
The following is an example of how you might use the first case.
Assume a Bulk IN transfer over Endpoint 2. For Bulk transfers, the EZ-USB packet buffer size is 512 bytes for high-speed
mode. Assume you have set up an EP2AUTOINLENH:L value of 100 bytes per packet, and you have configured the endpoint
for triple-buffering. This means that whenever 100 bytes are loaded into a packet buffer, the EZ-USB logic commits that
packet buffer to the USB interface, essentially adding 100 bytes to the ‘USB-side’ FIFO.
You want to notify the external logic that is filling the endpoint FIFO under two conditions:
■Two of the three packet buffers are full (committed to sending over USB, but not yet sent).
■The current packet buffer is half-full.
In other words, all available IN endpoint buffer space is almost full. You accomplish this by setting:
■EP2FIFOPFH = 0001 0000
❐b6: PKTSTAT = 0 to include packets plus bytes
❐b5b4b3 = 2: two packets…
■EP2FIFOPFL = 0011 0010
❐…plus 50 bytes in the currently filling packet
Example 2:
If you want the PF to inform the outside interface (the logic that is filling the IN FIFO) whenever the current packet is 75% full,
set PKTSTAT=1, and load a packet byte count of 75:
■EP2FIFOPFH = 1100 0000
■EP2FIFOPFHL = 0100 1011 (75 bytes)
Setting PKTSTAT=1 causes the PF decision to be based on the byte count alone, ignoring the packet count. This mode is
valuable for double buffered endpoints, where only the byte count of the currently-filling packet is important.
DECIS=1, thus PF is asserted when the currently filling packet is at or greater than 75 bytes.
Table 15-5. Interpretation of PF for IN Endpoints
PKTSTAT PF applies to: EPxFIFOPFH:L format
0PKTS + Current packet bytes PKTS[ ] PBC[ ]
1Current packet bytes only PBC[ ]
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 249
EPxFIFOPFL
E631
15.6.11.2 OUT Endpoints
For OUT endpoints, the PF flag applies to the total number of bytes in the multi-packet FIFO, with no packet count field.
Instead of representing byte counts in two segments, a packet count and a byte count for the currently emptying packet, the
byte Trigger values indicate total bytes available in the FIFO. Note the discontinuity between PFC10 and PFC9.
Notice that the packet byte counts differ in the upper PFC bits because the endpoints support different FIFO sizes: The EP2
FIFO can be a maximum of 4096 bytes long, the EP6 FIFO can be a maximum of 2048 bytes long, and the EP4 and EP8
FIFOS can be a maximum of 1024 bytes long. The diagram below shows examples of the maximum FIFO sizes.
Figure 15-2. Maximum FIFO Sizes
512
512
512
512
EP2
EP4
512
512
512
512
EP2
512
512
512
512
EP6
EP8
512
512
512
512
EP6
512
512
512
512
EP2
512
512
EP6
1024
1024
EP2
1024
1024
EP6
1024
1024
EP2
1024
1024
1024
EP2
1024
1024
512
512
EP8
512
512
EP8
250 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP2ISOINPKTS
E640
15.6.12 EP2ISOINPKTS
Endpoint 2 ISO IN Packets per Frame Register
The FX2LP has the capability of sending zero length isochronous data packet (ZLP) when the host issues an IN token to an
isochronous IN endpoint FIFO and the SIE does not have any data packets available. A zero length IN packet is automatically
sent in the micro-frame if the IN FIFO has no committed packets.
This feature is very useful when designing high bandwidth isochronous applications. When an isochronous IN endpoint is
configured for greater than one packet per micro-frame, there is a possibility of the core not having more than one packet
available in a micro-frame. In this case, when the host issues an IN token, the FX2LP core automatically sends a zero length
packet in response to each of the IN tokens received from the host. Hence avoiding the occurrence of a scenario where the
host may encounter a turnaround timeout error on not receiving any data when requesting more than one packet per micro-
frame.
In full-speed mode, the EZ-USB only sends one packet per frame, regardless of the EPxISOINPKTS register setting. If the IN
endpoint does not have any data packets available, the core automatically sends a zero length packet.
7 AADJ Auto Adjust.
If AADJ is set to ‘1’, the FX2LP automatically manages the data PID sequencing for high-speed, high-
bandwidth isochronous IN endpoints that require additional transactions per micro-frame.
Upon receiving the first IN token in the micro-frame, the FX2LP logic evaluates the fullness of com-
mitted packets in the IN FIFO. If the logic detects a committed short packet that contains less than
1024 bytes, no further packets beyond the short packet are sent in the micro-frame. If the IN FIFO
has no committed packets, then a single zero length packet is sent in the micro-frame.
If the IN FIFO is full of 1024 byte packets, then the number of packets sent in the micro-frame is lim-
ited by the INPPF[1:0] setting.
In both high-speed and full-speed modes, the EZ-USB sends a zero length IN packet if the IN FIFO
has no committed packets.
If AADJ is set to ‘0’, for IN transactions within the micro-frame, the FX2LP always starts with a data
PID corresponding to the number of packets per micro-frame specified in INPPF[1:0]. For example, if
INPPF[1:0]=10 (two packets per micro-frame), the FX2LP returns a data PID of DATA1 for the first IN
transaction in the micro-frame, even if the data packet is short, or no data is available to be sent for
the next IN transaction in the micro-frame.
In full-speed mode, the EZ-USB only sends one packet per frame, regardless of the EPxISOINPKTS
register setting.
1:0 INPPF[1:0] IN Packets per Frame.
If EP2 is an ISOCHRONOUS IN endpoint, these bits determine the number of packets to be sent per
micro-frame (high-speed mode). Allowed values are 1, 2, or 3.
EP2ISOINPKTS Endpoint 2 (if ISO) IN Packets Per Frame E640
b7 b6 b5 b4 b3 b2 b1 b0
AADJ 0 0 0 0 0 INPPF1 INPPF0
R/W RRRRRR/W R/W
00000001
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 251
EP4ISOINPKTS
E641
15.6.13 EP4ISOINPKTS
Endpoint 4 ISO IN Packets per Frame Register
EP4 is not high-bandwidth ISO capable and is only allowed to send up to one packet per micro-frame in high-speed mode,
and one packet per frame in full speed mode.
In both high-speed and full-speed modes, EZ-USB sends a zero length IN packet if the IN FIFO has no committed packets.
7 AADJ Auto Adjust.
If AADJ is set to ‘1’ and the IN FIFO has no committed packets, then a single zero length packet is
sent in the micro-frame.
1:0 INPPF[1:0] IN Packets per Frame.
If EP4 is an ISOCHRONOUS IN endpoint, these bits determine the number of packets to be sent per
micro-frame (high-speed mode). INPPF1:0 is hardcoded to ‘01’.
EP4ISOINPKTS Endpoint 4 (if ISO) IN Packets Per Frame E641
b7 b6 b5 b4 b3 b2 b1 b0
AADJ 0 0 0 0 0 INPPF1 INPPF0
R/W R R R R R R R
00000001
Bit Name Description
252 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP6ISOINPKTS
E642
15.6.14 EP6ISOINPKTS
Endpoint 6 ISO IN Packets per Frame Register
The FX2LP has the capability of sending zero length isochronous data packet (ZLP) when the host issues an IN token to an
isochronous IN endpoint FIFO and the SIE does not have any data packets available. A zero length IN packet is automatically
sent in the micro-frame if the IN FIFO has no committed packets.
This feature is very useful when designing high bandwidth isochronous applications. When an isochronous IN endpoint is
configured for greater than one packet per micro-frame, there is a possibility of the core not having more than one packet
available in a micro-frame. In this case, when the host issues an IN token, the FX2LP core automatically sends a zero length
packet in response to each of the IN tokens received from the host. Hence avoiding the occurrence of a scenario where the
host may encounter a turnaround time-out error on not receiving any data when requesting more than one packet per micro-
frame.
In full-speed mode, the EZ-USB only sends one packet per frame, regardless of the EPxISOINPKTS register setting. If the IN
endpoint does not have any data packets available, the core automatically sends a zero length packet.
7 AADJ Auto Adjust.
If AADJ is set to ‘1’, the FX2LP automatically manages the data PID sequencing for high-speed, high-
bandwidth isochronous IN endpoints that require additional transactions per micro-frame.
Upon receiving the first IN token in the micro-frame, the FX2LP logic evaluates the fullness of com-
mitted packets in the IN FIFO. If the logic detects a committed short packet that contains less than
1024 bytes, no further packets beyond the short packet are sent in the micro-frame. If the IN FIFO
has no committed packets, then a single zero length packet is sent in the microframe. If the IN FIFO
is full of 1024-byte packets, then the number of packets sent in the micro-frame is limited by the
INPPF[1:0] setting.
In both high-speed and full-speed modes, the EZ-USB sends a zero length IN packet if the IN FIFO
has no committed packets.
If AADJ is set to ‘0’, for IN transactions within the micro-frame, the FX2LP always starts with a data
PID corresponding to the number of packets per micro-frame specified in INPPF1:0. For example, if
INPPF[1:0]=10 (two packets per micro-frame), the FX2LP returns a data PID of DATA1 for the first IN
transaction in the micro-frame, even if the data packet is short, or no data is available to be sent for
the next IN transaction in the micro-frame.
In full-speed mode, the EZ-USB only sends one packet per frame, regardless of the EPxISOINPKTS
register setting.
1:0 INPPF[1:0] IN Packets per Frame
If EP6 is an ISOCHRONOUS IN endpoint, these bits determine the number of packets to be sent per
micro-frame (high-speed mode). Allowed values are ‘1’ or ‘2’.
EP6ISOINPKTS Endpoint 6 (if ISO) IN Packets Per Frame E642
b7 b6 b5 b4 b3 b2 b1 b0
AADJ 0 0 0 0 0 INPPF1 INPPF0
R/W RRRRRR/W R/W
00000001
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 253
EP8ISOINPKTS
E643
15.6.15 EP8ISOINPKTS
Endpoint 8 ISO IN Packets per Frame Register
EP8 is not high bandwidth ISO capable and is only allowed to send up to one packet per micro-frame in high-speed mode,
and one packet per frame in full speed mode.
In both high-speed and full-speed modes, EZ-USB sends a zero length IN packet if the IN FIFO has no committed packets.
7 AADJ Auto Adjust.
If AADJ is set to ‘1’ and the IN FIFO has no committed packets, then a single zero length packet is
sent in the micro-frame.
1:0 INPPF[1:0] IN Packets per Frame.
If EP8 is an ISOCHRONOUS IN endpoint, these bits determine the number of packets to be sent per
micro-frame (high-speed mode). INPPF[1:0] is hardcoded to ‘01’.
EP8ISOINPKTS Endpoint 8 (if ISO) IN Packets Per Frame E643
b7 b6 b5 b4 b3 b2 b1 b0
AADJ 0 0 0 0 0 INPPF1 INPPF0
R/W R R R R R R R
00000001
Bit Name Description
254 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
INPKTEND
E648
15.6.16 INPKTEND
Force IN Packet End Register
.
7SKIP Skip Packet.
When ENH_PKT (REVCTL.0) is set to ‘1’, setting this bit to a ‘1’ causes the IN packet to be skipped.
Clearing this bit to ‘0’ automatically dispatches an IN buffer.
3:0 EP[3:0] Endpoint Number. Duplicates the function of the PKTEND pin. This feature is used only for IN
transfers.
By writing the desired endpoint number (2, 4, 6 or 8), EZ-USB logic automatically dispatches an IN
buffer, for example, it commits the packet to the USB logic, and writes the accumulated byte count to
the endpoint’s byte count register, thus arming the IN transfer.
INPKTEND
see Section 15.15 Force IN Packet End E648
b7 b6 b5 b4 b3 b2 b1 b0
SKIP 0 0 0 EP3 EP2 EP1 EP0
W W W W W W W W
x x x x x x x x
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 255
OUTPKTEND
E649
15.6.17 OUTPKTEND
Force OUT Packet End Register
7SKIP Skip Packet.
When ENH_PKT (REVCTL.0) is set to ‘1’, setting this bit to a ‘1’ causes the OUT packet to be
skipped. Clearing this bit to ‘0’ automatically dispatches an OUT buffer.
3:0 EP[3:0] Endpoint Number.
Replaces the function of EPxBCL.7=1 (Skip). This feature is for OUT transfers. By writing the desired
endpoint number (2, 4, 6, or 8), EZ-USB logic automatically skips or commits an OUT packet
(depends on the SKIP bit settings).
Note This register has no effect if REVCTL.0 = 0.
OUTPKTEND
see Section 15.15 Force OUT Packet End E649
b7 b6 b5 b4 b3 b2 b1 b0
SKIP 0 0 0 EP3 EP2 EP1 EP0
W W W W W W W W
x x x x x x x x
Bit Name Description
256 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EPxFIFOIE
E650
15.7 Interrupts
15.7.1 EPxFIFOIE
Endpoint 2, 4, 6, 8 Slave FIFO Flag Interrupt Enable Registers
The Interrupt registers control all the EZ-USB Interrupt Enables (IE) and Interrupt requests (IRQ). Interrupt enables and
request bits for endpoint FIFO: Programmable Flag (PF), Empty Flag (EF), and Full Flag (FF).
To enable any of these interrupts, INTSETUP.1 (INT4SRC) and INTSETUP.0 must be ‘1’.
3EDGEPF Firing Edge Programmable Flag.
0 The interrupt fires on the rising edge of the programmable flag.
1 The interrupt fires on the falling edge of the programmable flag.
Note In order for the CPU to vector to the appropriate interrupt service routine, PF must be set to a ‘1’
and INTSETUP.0=1 (AV4EN) and INTSETUP.1=1 (INT4SRC). Refer to section INT 2 and INT 4
Setup Register on page 274
2PF Programmable Flag.
0 The programmable flag interrupt is disabled.
1 The programmable flag interrupt is enabled on INT4.
1EF Empty Flag.
0 The empty flag interrupt is disabled.
1 The empty flag interrupt is enabled on INT4.
0FF Full Flag.
0 The full flag interrupt is disabled.
1 The full flag interrupt is enabled on INT4.
EP2FIFOIE
see Section 15.15 EP2 Slave FIFO Flag Interrupt Enable (INT4) E650
EP4FIFOIE
see Section 15.15 EP4 Slave FIFO Flag Interrupt Enable (INT4) E652
EP6FIFOIE
see Section 15.15 EP6 Slave FIFO Flag Interrupt Enable (INT4) E654
EP8FIFOIE
see Section 15.15 EP8 Slave FIFO Flag Interrupt Enable (INT4) E656
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 EDGEPF PF EF FF
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 257
EPxFIFOIRQ
E651
15.7.2 EPxFIFOIRQ
Endpoint 2, 4, 6, 8 Slave FIFO Flag Interrupt Request Registers
These are the Interrupt enables and request bits for endpoint FIFO: Programmable Flag (PF), Empty Flag (EF), and Full Flag
(FF).
2PF Programmable Flag.
EZ-USB sets PF to ‘1’ to indicate a ‘programmable flag’ interrupt request. The interrupt source is
available in the interrupt vector register IVEC4.
1EF Empty Flag.
EZ-USB sets EF to ‘1’ to indicate an ‘empty flag’ interrupt request. The interrupt source is available in
the interrupt vector register IVEC4.
0FF Full Flag.
EZ-USB sets FF to ‘1’ to indicate a ‘full flag’ interrupt request. The interrupt source is available in the
interrupt vector register IVEC4.
Note Do not clear an IRQ bit by reading an IRQ register, OR’ing its contents with a bit mask, and writ-
ing back the IRQ register. This clears all pending interrupts. Instead, simply write the bit mask value
(with a ‘1’ in the bit position of the IRQ you want to clear) directly to the IRQ register.
EP2FIFOIRQ
see Section 15.15 EP2 Slave FIFO Flag Interrupt Request (INT4) E651
EP4FIFOIRQ
see Section 15.15 EP4 Slave FIFO Flag Interrupt Request (INT4) E653
EP6FIFOIRQ
see Section 15.15 EP6 Slave FIFO Flag Interrupt Request (INT4) E655
EP8FIFOIRQ
see Section 15.15 EP8 Slave FIFO Flag Interrupt Request (INT4) E657
b7 b6 b5 b4 b3 b2 b1 b0
00000PF EF FF
R R R R R R/W R/W R/W
00000000
Bit Name Description
258 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
IBNIE
E658
15.7.3 IBNIE
IN-BULK-NAK Interrupt Enable Register
5:0 EP[8,6,4,2,1,0] Endpoint Specific Interrupt Enable.
These interrupts occur when the host sends an IN token to a Bulk-IN endpoint which has not been
loaded with data and armed for USB transfer. In this case the EZ-USB SIE automatically NAKs the IN
token and sets the IBNIRQ bit for the endpoint.
Set IE=1 to enable the interrupt, and IE=0 to disable it.
An IRQ bit is set to ‘1’ to indicate an interrupt request. The interrupt source is available in the interrupt
vector register IVEC2. Note The firmware clears an IRQ bit by writing a ‘1’ to it.
Note Do not clear an IRQ bit by reading an IRQ register, OR’ing its contents with a bit mask, and writ-
ing back the IRQ register. This clears all pending interrupts. Instead, simply write the bit mask value
(with a ‘1’ in the bit position of the IRQ you want to clear) directly to the IRQ register.
IBNIE IN-BULK-NAK Interrupt Enable (INT2) E658
b7 b6 b5 b4 b3 b2 b1 b0
0 0 EP8 EP6 EP4 EP2 EP1 EP0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 259
IBNIRQ
E659
15.7.4 IBNIRQ
IN-BULK-NAK Interrupt Request Register
5:0 EP[8,6,4,2,1,0] Endpoint Specific Interrupt Enable.
These interrupts occur when the host sends an IN token to a Bulk-IN endpoint which has not been
loaded with data and armed for USB transfer. In this case the EZ-USB SIE automatically NAKs the IN
token and sets the IBNIRQ bit for the endpoint.
Set IE = 1 to enable the interrupt, and IE = 0 to disable it.
An IRQ bit is set to ‘1’ to indicate an interrupt request. The interrupt source is available in the interrupt
vector register IVEC2. Note The firmware clears an IRQ bit by writing a ‘1’ to it.
Note Do not clear an IRQ bit by reading an IRQ register, OR’ing its contents with a bit mask, and writ-
ing back the IRQ register. This clears all pending interrupts. Instead, simply write the bit mask value
(with a ‘1’ in the bit position of the IRQ you want to clear) directly to the IRQ register.
IBNIRQ IN-BULK-NAK Interrupt Request (INT2) E659
b7 b6 b5 b4 b3 b2 b1 b0
0 0 EP8 EP6 EP4 EP2 EP1 EP0
R R R/W R/W R/W R/W R/W R/W
0 0 x x x x x x
Bit Name Description
260 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
NAKIE
E65A
15.7.5 NAKIE
Endpoint Ping-NAK/IBN Interrupt Enable Register
Bit 7-2 EP[8,6,4,2,1,0] Ping-NAK INT Enable.
These registers are active only during high-speed (480 Mbps) operation.
USB 2.0 improves the USB 1.1 bus bandwidth utilization by implementing a PING-NAK mechanism
for OUT transfers. When the host wishes to send OUT data to an endpoint, it first sends a PING token
to see if the endpoint is ready, that is, it has an empty buffer. If a buffer is not available, the SIE
returns a NAK handshake. PING-NAK transactions continue to occur until an OUT buffer is available,
at which time the FX2LP SIE answers a PING with an ACK handshake. Then the host sends the OUT
data to the endpoint.
The OUT Ping NAK interrupt indicates that the host is trying to send OUT data, but the SIE
responded with a NAK because no endpoint buffer memory is available. The firmware may wish to
use this interrupt to free up an OUT endpoint buffer.
Bit 0 IBN IBN INT Enable.
This bit is automatically set when any of the IN bulk endpoints responds to an IN token with a NAK.
This interrupt occurs when the host sends an IN token to a bulk IN endpoint which has not yet been
armed. Individual enables and requests (per endpoint) are controlled by the IBNIE and IBNIRQ regis-
ters. Write a ‘1’ to this bit to clear the interrupt request.
The IBN INT only fires on a 0-to-1 transition of an ‘OR’ condition of all IBN sources that are enabled.
NAKIE Endpoint Ping-NAK/IBN Interrupt Enable (INT2) E65A
b7 b6 b5 b4 b3 b2 b1 b0
EP8 EP6 EP4 EP2 EP1 EP0 0IBN
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 261
NAKIRQ
E65B
15.7.6 NAKIRQ
Endpoint Ping-NAK/IBN Interrupt Request Register
7:2 EP[8,6,4,2,1,0] Ping-NAK INT Request.
These registers are active only during high-speed (480 Mbps) operation.
USB 2.0 improves the USB 1.1 bus bandwidth utilization by implementing a PING-NAK mechanism
for OUT transfers. When the host wishes to send OUT data to an endpoint, it first sends a PING token
to see if the endpoint is ready, that is, it has an empty buffer. If a buffer is not available, the SIE
returns a NAK handshake. PING-NAK transactions continue to occur until an OUT buffer is available,
at which time the FX2LP SIE answers a PING with an ACK handshake. Then the host sends the OUT
data to the endpoint.
The OUT Ping NAK interrupt indicates that the host is trying to send OUT data, but the SIE
responded with a NAK because no endpoint buffer memory is available. The firmware may wish to
use this interrupt to free up an OUT endpoint buffer.
0IBN IBN INT Request.
This bit is automatically set when any of the IN bulk endpoints responds to an IN token with a NAK.
This interrupt occurs when the host sends an IN token to a bulk IN endpoint which has not yet been
armed. Individual enables and requests (per endpoint) are controlled by the IBNIE and IBNIRQ regis-
ters. Write a ‘1’ to this bit to clear the interrupt request.
The IBN INT only fires on a 0-to-1 transition of an ‘OR’ condition of all IBN sources that are enabled.
Note The firmware clears an IRQ bit by writing a ‘1’ to it.
Note Do not clear an IRQ bit by reading an IRQ register, OR’ing its contents with a bit mask, and writ-
ing back the IRQ register. This clears all pending interrupts. Instead, simply write the bit mask value
(with a ‘1’ in the bit position of the IRQ you want to clear) directly to the IRQ register.
NAKIRQ Endpoint Ping-NAK/IBN Interrupt Request (INT2) E65B
b7 b6 b5 b4 b3 b2 b1 b0
EP8 EP6 EP4 EP2 EP1 EP0 0IBN
R/W R/W R/W R/W R/W R/W RR/W
x x x x x x 0 x
Bit Name Description
262 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
USBIE
E65C
15.7.7 USBIE
USB Interrupt Enable Register
6 EP0ACK EndPoint 0 Acknowledge.
Status stage completed.
5 HSGRANT Grant High-Speed Access.
The FX2LP SIE sets this bit when it has been granted high-speed (480 Mbps) access to USB.
4 URES USB Reset Interrupt Request.
The USB signals a bus reset by driving both D+ and D- low for at least 10 milliseconds. When the
USB core detects the onset of USB bus reset, it activates the URES interrupt request. The USB core
sets this bit to ‘1’ when it detects a USB bus reset. Write a ‘1’ to this bit to clear the interrupt request.
3SUSP Suspend Interrupt Request.
If the EZ-USB detects 3 ms of no bus activity, it activates the SUSP (Suspend) interrupt request. The
USB core sets this bit to ‘1’ when it detects USB SUSPEND signaling (no bus activity for 3 ms). Write
a ‘1’ to this bit to clear the interrupt request.
2SUTOK Setup Token.
The USB core sets this bit to ‘1’ when it receives a SETUP token. Write a ‘1’ to this bit to clear the
interrupt request.
1SOF Start of Frame.
The USB core sets this bit to ‘1’ when it receives a SOF packet. Write a ‘1’ to this bit to clear the inter-
rupt request.
0 SUDAV SETUP Data Available Interrupt Request.
The USB core sets this bit to ‘1’ when it has transferred the eight data bytes from an endpoint zero
SETUP packet into internal registers (at SETUPDAT). Write a ‘1’ to this bit to clear the interrupt
request.
Note Do not clear an IRQ bit by reading an IRQ register, OR’ing its contents with a bit mask, and writ-
ing back the IRQ register. This clears all pending interrupts. Instead, simply write the bit mask value
(with a ‘1’ in the bit position of the IRQ you want to clear) directly to the IRQ register.
USBIE USB Interrupt Enables (INT2) E65C
b7 b6 b5 b4 b3 b2 b1 b0
0EP0ACK HSGRANT URES SUSP SUTOK SOF SUDAV
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 263
USBIRQ
E65D
15.7.8 USBIRQ
USB Interrupt Request Register
6 EP0ACK EndPoint 0 Acknowledge.
Status stage completed.
5 HSGRANT Grant High-Speed Access.
The FX2LP SIE sets this bit when it has been granted high-speed (480 Mbps) access to USB.
4 URES USB Reset Interrupt Request.
The USB signals a bus reset by driving both D+ and D- low for at least 10 milliseconds. When the
USB core detects the onset of USB bus reset, it activates the URES interrupt request. The USB core
sets this bit to ‘1’ when it detects a USB bus reset. Write a ‘1’ to this bit to clear the interrupt request.
3SUSP Suspend Interrupt Request.
If the EZ-USB detects 3 ms of no bus activity, it activates the SUSP (Suspend) interrupt request. The
USB core sets this bit to ‘1’ when it detects USB SUSPEND signaling (no bus activity for 3 ms). Write
a ‘1’ to this bit to clear the interrupt request.
2SUTOK Setup Token.
The USB core sets this bit to ‘1’ when it receives a SETUP token. Write a ‘1’ to this bit to clear the
interrupt request.
1SOF Start of Frame.
The USB core sets this bit to ‘1’ when it receives a SOF packet. Write a ‘1’ to this bit to clear the inter-
rupt request.
0 SUDAV SETUP Data Available Interrupt Request.
The USB core sets this bit to ‘1’ when it has transferred the eight data bytes from an endpoint zero
SETUP packet into internal registers (at SETUPDAT). Write a ‘1’ to this bit to clear the interrupt
request.
Note Do not clear an IRQ bit by reading an IRQ register, OR’ing its contents with a bit mask, and writ-
ing back the IRQ register. This clears all pending interrupts. Instead, simply write the bit mask value
(with a ‘1’ in the bit position of the IRQ you want to clear) directly to the IRQ register.
USBIRQ USB Interrupt Requests (INT2) E65D
b7 b6 b5 b4 b3 b2 b1 b0
0EP0ACK HSGRANT URES SUSP SUTOK SOF SUDAV
RR/W R/W R/W R/W R/W R/W R/W
0 x x x x x x x
Bit Name Description
264 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EPIE
E65E
15.7.9 EPIE
Endpoint Interrupt Enable Register
These Endpoint interrupt enable/request registers indicate the pending interrupts for each bulk endpoint. For IN endpoints,
the interrupt asserts when the host takes a packet from the endpoint; for OUT endpoints, the interrupt asserts when the host
supplies a packet to the endpoint.
The IRQ bits function independently of the Interrupt Enable (IE) bits, so interrupt requests are held whether or not the inter-
rupts are enabled.
Note Do not clear an IRQ bit by reading an IRQ register, OR’ing its contents with a bit mask, and writing back the IRQ regis-
ter. This clears all pending interrupts. Instead, simply write the bit mask value (with a ‘1’ in the bit position of the IRQ you want
to clear) directly to the IRQ register.
EPIE Endpoint Interrupt Enables (INT2) E65E
b7 b6 b5 b4 b3 b2 b1 b0
EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 265
EPIRQ
E65F
15.7.10 EPIRQ
Endpoint Interrupt Request Register
These Endpoint interrupt enable/request registers indicate the pending interrupts for each bulk endpoint. For IN endpoints,
the interrupt asserts when the host takes a packet from the endpoint; for OUT endpoints, the interrupt asserts when the host
supplies a packet to the endpoint.
The IRQ bits function independently of the Interrupt Enable (IE) bits, so interrupt requests are held whether or not the inter-
rupts are enabled.
Note Do not clear an IRQ bit by reading an IRQ register, OR’ing its contents with a bit mask, and writing back the IRQ regis-
ter. This clears all pending interrupts. Instead, simply write the bit mask value (with a ‘1’ in the bit position of the IRQ you want
to clear) directly to the IRQ register.
EPIRQ Endpoint Interrupt Requests (INT2) E65F
b7 b6 b5 b4 b3 b2 b1 b0
EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
266 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
GPIFIE
E660
15.7.11 GPIFIE
GPIF Interrupt Enable Register
1GPIFWF FIFO Read/Write Waveform.
GPIF-to-firmware ‘hook’ in waveform, when waveform descriptor is programmed to assert the
GPIFWF interrupt.
0GPIFDONE GPIF Idle State.
0 Transaction in progress.
1 Transaction Done (GPIF is idle, hence GPIF is ready for next transaction). Fires IRQ4 if
enabled.
Note The firmware clears an interrupt request bit by writing a ‘1’ to it.
Note Do not clear an IRQ Bit by reading an IRQ register, OR’ing its contents with a bit mask, and writ-
ing back the IRQ register. This clears all pending interrupts. Instead, simply write the bit mask value
(with a ‘1’ in the bit position of the IRQ you want to clear) directly to the IRQ register.
GPIFIE
see Section 15.15 GPIF Interrupt Enable (INT4) E660
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 GPIFWF GPIFDONE
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 267
GPIFIRQ
E661
15.7.12 GPIFIRQ
GPIF Interrupt Request Register
1GPIFWF FIFO Read/Write Waveform.
GPIF-to-firmware ‘hook’ in waveform, when waveform descriptor is programmed to assert the
GPIFWF interrupt.
0GPIFDONE GPIF Idle State.
0 Transaction in progress.
1 Transaction Done (GPIF is idle, hence GPIF is ready for next transaction). Fires IRQ4 if
enabled.
Note The firmware clears an interrupt request bit by writing a ‘1’ to it.
Note Do not clear an IRQ Bit by reading an IRQ register, OR’ing its contents with a bit mask, and writ-
ing back the IRQ register. This clears all pending interrupts. Instead, simply write the bit mask value
(with a ‘1’ in the bit position of the IRQ you want to clear) directly to the IRQ register.
GPIFIRQ
see Section 15.15 GPIF Interrupt Request (INT4) E661
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 GPIFWF GPIFDONE
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 x x
Bit Name Description
268 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
USBERRIE
E662
15.7.13 USBERRIE
USB Error Interrupt Enable Register
7:4 ISOEP[8,6,4,2] ISO Error Packet.
The ISO EP Flag is set when ISO OUT data PIDs arrive out of sequence (applies to high speed only)
and an ISO OUT packet was dropped because no buffer space was available for an OUT packet (in
either full or high-speed modes).
0 ERRLIMIT Error Limit.
ERRLIMIT counts USB bus errors — CRC, bit stuff, and so on, and triggers the interrupt when the
programmed limit (0-15) is reached.
The firmware clears an interrupt request bit by writing a ‘1’ to it.
Note Do not clear an IRQ Bit by reading an IRQ register, OR’ing its contents with a bit mask, and writ-
ing back the IRQ register. This clears all pending interrupts. Instead, simply write the bit mask value
(with a ‘1’ in the bit position of the IRQ you want to clear) directly to the IRQ register.
USBERRIE USB Error Interrupt Enables (INT2) E662
b7 b6 b5 b4 b3 b2 b1 b0
ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 269
USBERRIE
E663
15.7.14 USBERRIE
USB Error Interrupt Request Register
7:4 ISOEP[8,6,4,2] ISO Error Packet.
The ISO EP Flag is set when ISO OUT data PIDs arrive out of sequence (applies to high speed only)
and an ISO OUT packet was dropped because no buffer space was available for an OUT packet (in
either full or high-speed modes).
0 ERRLIMIT Error Limit.
ERRLIMIT counts USB bus errors — CRC, bit stuff, and so on, and triggers the interrupt when the
programmed limit (0-15) is reached.
The firmware clears an interrupt request bit by writing a ‘1’ to it.
Note Do not clear an IRQ Bit by reading an IRQ register, OR’ing its contents with a bit mask, and writ-
ing back the IRQ register. This clears all pending interrupts. Instead, simply write the bit mask value
(with a ‘1’ in the bit position of the IRQ you want to clear) directly to the IRQ register.
USBERRIRQ USB Error Interrupt Request (INT2) E663
b7 b6 b5 b4 b3 b2 b1 b0
ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT
R/W R/W R/W R/W R R R R/W
0 0 0 0 0 0 0 x
Bit Name Description
270 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
ERRCNTLIM
E664
15.7.15 ERRCNTLIM
USB Error Counter Limit Register
7:4 EC[3:0] USB Error Count.
Error count has a maximum value of ‘15’.
3:0 LIMIT[3:0] Error Count Limit.
USB bus error count and limit. The firmware can enable the interrupt to cause an interrupt when the
limit is reached. The default limit count is ‘4’.
ERRCNTLIM USB Error Counter and Limit E664
b7 b6 b5 b4 b3 b2 b1 b0
EC3 EC2 EC1 EC0 LIMIT3 LIMIT2 LIMIT1 LIMIT0
R R R R R/W R/W R/W R/W
x x x x 0 1 0 0
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 271
CLRERRCNT
E665
15.7.16 CLRERRCNT
Clear Error Count Register
Write any value to this register to clear the EC (Error Count) bits in the ERRCNTLIM register.
CLRERRCNT Clear Error Count EC3:0 E665
b7 b6 b5 b4 b3 b2 b1 b0
xxxxxxxx
W W W W W W W W
x x x x x x x x
272 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
INT2IVEC
E666
15.7.17 INT2IVEC
INT 2 (USB) Autovector Register
6:2 I2V[4:0] INT 2 Autovector.
To save the code and processing time required to sort out which USB interrupt occurred, the USB
core provides a second level of interrupt vectoring, called Autovectoring. When the CPU takes a USB
interrupt, it pushes the program counter onto its stack, and then executes a jump to address 43,
where it expects to find a jump instruction to the INT2 service routine.
I2V indicates the source of an interrupt from the USB Core. When the USB core generates an INT2
(USB) interrupt request, it updates INT2IVEC to indicate the source of the interrupt. The interrupt
sources are encoded on I2V[4:0].
INT2IVEC INTERRUPT 2 (USB) Autovector E666
b7 b6 b5 b4 b3 b2 b1 b0
0I2V4 I2V3 I2V2 I2V1 I2V0 0 0
R R R R R R R R
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 273
INT4IVEC
E667
15.7.18 INT4IVEC
INT 4 (slave FIFOs and GPIF) Autovector Register
5:2 I4V[3:0] INT 4 Autovector.
To save the code and processing time required to sort out which FIFO interrupt occurred, the USB
core provides a second level of interrupt vectoring, called Autovectoring. When the CPU takes a USB
interrupt, it pushes the program counter onto its stack, and then executes a jump to address 53,
where it expects to find a jump instruction to the INT4 service routine.
I4V indicates the source of an interrupt from the USB Core. When the USB core generates an INT4
(FIFO/GPIF) interrupt request, it updates INT4IVEC to indicate the source of the interrupt. The inter-
rupt sources are encoded on I4V[3:0].
INT4IVEC Interrupt 4 (slave FIFOs and GPIF) Autovector E667
b7 b6 b5 b4 b3 b2 b1 b0
1 0 I4V3 I4V2 I4V1 I4V0 0 0
R R R R R R R R
10000000
Bit Name Description
274 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
INTSETUP
E668
15.7.19 INTSETUP
INT 2 and INT 4 Setup Register
3 AV2EN INT2 Autovector Enable.
To streamline the code that deals with the USB interrupts, this bit enables autovectoring on INT2.
1INT4SRC INT 4 Source.
0 INT4 is supplied by the pin (default)
1 INT4 is supplied internally from FIFO/GPIF sources
0 AV4EN INT4 Autovector Enable.
To streamline the 8051 code that deals with the FIFO interrupts, this bit enables autovectoring on
INT4.
INTSETUP INT 2 and INT 4 Setup E668
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 AV2EN 0INT4SRC AV4EN
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 275
PORTACFG
E670
15.8 Input/Output Registers
15.8.1 PORTACFG
I/O PORTA Alternate Configuration Register
The PORTxCFG register selects alternate functions for the PORTx pins.
7FLAGD FlagD Alternate Configuration.
If IFCFG[1:0] = 11, setting this bit to '1' configures the PA7 pin as FLAGD, a programmable FIFO flag.
6SLCS SLCS Alternate Configuration.
If IFCFG[1:0] = 11, setting this bit to '1' configures the PA7 pin as SLCS, the slave FIFO chip select.
1:0 INT[1:0] Interrupts Enabled for Alternate Configuration.
Setting these bits to '1' configures these PORTA pins as the INT1 or INT0 pins.
Note Bits PORTACFG.7 and PORTACFG.6 both affect pin PA7. If both bits are set, FLAGD takes precedence.
Note Bit 3 is the WU2EN bit in the Wakeup register.
PORTACFG I/O PORTA Alternate Configuration E670
b7 b6 b5 b4 b3 b2 b1 b0
FLAGD SLCS 0 0 0 0 INT1 INT0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
276 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
PORTCCFG
E671
15.8.2 PORTCCFG
I/O PORTC Alternate Configuration Register
7:0 GPIFA[7:0] Enable GPIF Address Pins.
0 Configure this as Port C.
1 Configure this port to output the lower address of enabled GPIF address pins. Additional bit
set in PORTECFG, bit 7.
PORTCCFG I/O PORTC Alternate Configuration E671
b7 b6 b5 b4 b3 b2 b1 b0
GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 277
PORTECFG
E672
15.8.3 PORTECFG
I/O PORTE Alternate Configuration Register
7GPIFA8 Enable GPIF Address Pin. GPIF address bit 8 pin.
0 Configure this as Port E.
1 Configure this port to output the high address of enabled GPIF address pins.
6T2EX Timer 2 Counter.
Timer/Counter 2 Capture/Reload Input.
5INT6 INT6 Interrupt Request.
1 Configure this Port E pin as INT6.
4RXD1OUT Mode 0: USART1 Synchronous Data Output.
3RXD0OUT Mode 0: USART0 Synchronous Data Output.
2:0 T2OUT, T1OUT, T0OUT Serial Data.
Serial mode 0 provides synchronous, half duplex serial communication. For Serial Port 0, serial data
output occurs on the RXD0OUT pin, serial data is received on the RXD0 pin, and the TXD0 pin pro-
vides the shift clock for both transmit and receive. Mode 0: Clock Output Modes 1-3: Serial Port 0
Data Output.
PORTECFG I/O PORTE Alternate Configuration E672
b7 b6 b5 b4 b3 b2 b1 b0
GPIFA8 T2EX INT6 RXD1OUT RXD0OUT T2OUT T1OUT T0OUT
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
278 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
I2CS
E678
15.8.4 I2CS
I²C Bus Control and Status Register
For additional information refer to “Registers” on page 190 of the Input/Output chapter.
7START Signal START Condition.
1 The next write to I2DAT generates a ‘start’ condition followed by the byte of data written to
I2DAT. The START bit is automatically cleared to ‘0’ after the ACK interval.
6STOP Signal STOP Condition.
1 After the ACK interval, a ‘stop’ condition is generated. STOP may be set by firmware at any
time before, during, or after the 9 bit data transaction. STOP is automatically cleared after
the ‘stop’ condition is generated. Data should not be written to I2CS or I2DAT unless the
STOP bit is 0.
An interrupt request is available to signal that the stop condition is complete; see ‘STOPIE’.
5LASTRD Last Data Read.
An I2C master reads data by floating the SDA line and issuing clock pulses on the SCL line. After
every eight bits, the master drives SDA low for one clock to indicate ACK. To signal the last byte of a
multi-byte transfer, the master floats SDA at ACK time to instruct the slave to stop sending.
When LASTRD = 1 at ACK time, the EZ-USB floats the SDA line. The LASTRD bit may be set at any
time before or during the data transfer; it is automatically cleared after the ACK interval.
Note Setting LASTRD does not automatically generate a ‘stop’ condition. At the end of a read trans-
fer, the STOP bit should also be set.
4:3 ID[1:0] Boot EEPROM ID.
These bits are set by the boot loader to indicate whether an 8-bit address or 16-bit address EEPROM
at slave address 000 or 001 was detected at power-on. Normally, they are used for debug purposes
only.
00 No EEPROM found
01 8-bit EEPROM found at slave address 000
10 16-bit EEPROM found at slave address 001
11 Not used
(continued on next page)
I2CS I²C Bus
Control and Status E678
b7 b6 b5 b4 b3 b2 b1 b0
START STOP LASTRD ID1 ID0 BERR ACK DONE
R/W R/W R/W R R R R R
0 0 0 x x 0 0 0
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 279
I2CS
E678
15.8.4 I2CS (continued)
2BERR Bus Error.
This bit indicates a bus error. BERR=1 indicates that there was bus contention during the preceding
transfer, which results when an outside device drives the bus when it should not, or when another bus
master wins arbitration and takes control of the bus.
When a bus error is detected, the EZ-USB immediately cancels its current transfer, floats the SCL
and SDA lines, then sets DONE and BERR. BERR remains set until it is updated at the next ACK
interval. The I2C master will not drive SCL till BERR is reset. If the bus error causes the master to
detect bus contention and slave to be stuck in the middle of a transfer. Then there is no in-built con-
tention resolution method to workaround this deadlock. If there is a possibility of this condition then
the design must implement a method of resetting the slave or clocking the slave till the next ACK.
DONE is set with BERR only when bus contention occurs during a transfer. If BERR is set and the
bus is still busy when firmware attempts to restart a transfer, that second transfer is cancelled but the
DONE flag is not set. If contention is expected, EZ-USB firmware should incorporate a timeout to test
for this condition. See Steps 1 and 3 of sections 13.5.3 Sending Data and 13.5.4 Receiving Data on
page 191.
1 ACK Acknowledge Bit.
During the ninth clock of a write transfer, the slave indicates reception of the byte by driving SDA low
to acknowledge the byte it just received. The EZ-USB floats SDA during this time, samples the SDA
line, and updates the ACK bit with the complement of the detected value: ACK=1 indicates that the
slave acknowledged the transfer, and ACK=0 indicates the slave did not. The USB core updates the
ACK bit and at the same time it sets DONE=1.
The ACK bit is only meaningful after a write transfer. After a read transfer, its state should be ignored.
0DONE Transfer DONE.
The EZ-USB sets this bit whenever it completes a byte transfer. The EZ-USB also generates an
interrupt request when it sets the DONE bit. The DONE bit is automatically cleared when the I2DAT
register is read or written, and the interrupt request bit is automatically cleared by reading or writing
the I2CS or I2DAT registers (or by clearing EXIF.5 to 0).
280 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
I2CDAT
E679
15.8.5 I2CDAT
I²C Bus Data Register
For additional information refer to “Registers” on page 190 of the Input/Output chapter.
7:0 Data Data Bits.
Eight bits of data; writing or reading this register triggers a bus transaction.
I2DAT I²C Bus Data E679
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 281
I2CTL
E67A
15.8.6 I2CTL
I²C Bus Control Register
For additional information refer to “Registers” on page 190 of the Input/Output chapter.
1STOPIE Stop Interrupt Enable Bit.
Setting this bit enables the STOP bit interrupt request, which is activated when the STOP bit makes a
1-to-0 transition.
0 400KHZ High-Speed I2C Bus.
For I2C peripherals that support it, the I2C bus can run at 400 kHz.
0 The I2C bus operates at approximately 100 kHz.
1 The I2C bus operates at approximately 400 kHz.
I2CTL I²C Bus Control E67A
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 STOPIE 400KHZ
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
282 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
XAUTODATx
E67A
15.8.7 XAUTODATx
AUTOPOINTERs 1 and 2 MOVX Access Registers
7:0 Data AUTODATAx.
Data read or written to the XAUTODATx register accesses the memory addressed by the AUTOP
RHn/Ln registers, and optionally increments the address after the read or write.
XAUTODAT1 AUTOPTR1 MOVX Access E67B
XAUTODAT2 AUTOPTR2 MOVX Access E67C
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
Bit Name Description
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XAUTODATx
E67A
15.9 ECC Control and Data Registers
15.9.1 ECC Features
The EZ-USB can calculate Error Correcting Codes (ECCs) on data that passes across its GPIF or Slave FIFO interfaces.
There are two ECC configurations: Two ECCs, each calculated over 256 bytes (SmartMedia Standard); and one ECC calcu-
lated over 512 bytes.
The ECC can correct any one-bit error or detect any two-bit error.
15.9.2 ECC Implementation
The two ECC configurations are selected by the ECCM bit.
ECCM = 0 Two 3-byte ECCs, each calculated over a 256-byte block of data. This configuration conforms to the
SmartMedia™ Standard.
Write any value to ECCRESET, then pass data across the GPIF or Slave FIFO interface. The ECC
for the first 256 bytes of data are calculated and stored in ECC1. The ECC for the next 256 bytes are
stored in ECC2. After the second ECC is calculated, the values in the ECCx registers does not
change until ECCRESET is written again, even if more data is subsequently passed across the inter-
face.
ECCM = 1 One 3-byte ECC calculated over a 512-byte block of data.
Write any value to ECCREST then pass data across the GPIF or Slave FIFO interface. The ECC for
the first 512 bytes of data are calculated and stored in ECC1; ECC2 is unused. After the ECC is cal-
culated, the value in ECC1 does not change until ECCRESET is written again, even if more data is
subsequently passed across the interface.
Note To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
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XAUTODATx
E67A
15.9.3 ECC Check/Correct
The following code demonstrates the ECC correction algorithms for 256-byte and 512-byte ECCs. In the 256-byte example,
the calculated_ecc[] array contains the contents of the appropriate ECCx registers; in the 512-byte example, the ECC1 regis-
ters are read directly.
//
// ECC Check/Correct for 256-byte ECC.
//
// Enter with 256 bytes of received data in data[], 3 bytes of received ECC in
// received_ecc[], and the ECC calculated by the EZ-USB in calculated_ecc[].
//
UINT8 received_ecc[3];
UINT8 checkECC (void) {
UINT8 a,b,c,x,y;
a = received_ecc[0] ^ calculated_ecc[0];// Calculated ecc = received ecc?
b = received_ecc[1] ^ calculated_ecc[1];
c = received_ecc[2] ^ calculated_ecc[2];
if ((a | b | c) == 0) return (ECC_OK);// If so, no error; return.
if ((((a^(a>>1)) & 0x55) == 0x55) && // Does each pair of parity bits contain
(((b^(b>>1)) & 0x55) == 0x55) && // one error and one match?
(((c^(c>>1)) & 0x54) == 0x54)) {
x = (a & 0x80); // If so, there's a one-bit error in data[].
if (a & 0x20) x |= 0x40; // Find which byte is in error...
if (a & 0x08) x |= 0x20;
if (a & 0x02) x |= 0x10;
if (b & 0x80) x |= 0x08;
if (b & 0x20) x |= 0x04;
if (b & 0x08) x |= 0x02;
if (b & 0x02) x |= 0x01;
y = 0; // ... and which bit...
if (c & 0x80) y |= 0x04;
if (c & 0x20) y |= 0x02;
if (c & 0x08) y |= 0x01;
data[x] ^= (1 << y); // ... and correct it.
return (ECC_DATA_FIXED); // Return with one bit fixed.
}
y = 0xFF; // If each pair didn't contain one error
if ((a | b) == 0) y = c; // and one match, check to see if only
if ((a | c) == 0) y = b; // one bit is in error (which would mean
if ((b | c) == 0) y = a; // that the received ecc is erroneous).
if ((y & (y-1)) == 0) { // If so...
received_ecc[0] = calculated_ecc[0];// Replace the received ecc with our
received_ecc[1] = calculated_ecc[1];// calculated ecc.
received_ecc[2] = calculated_ecc[2];
return (ECC_ECC_FIXED); // Return with received ecc fixed.
}
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E67A
return (ECC_ERROR); // Uncorrectable error in data or received ecc;
// return with data[] and received_ecc[]
// unchanged.
}
-----------------------------------------------------------------------------------
//
// ECC Check/Correct for 512-byte ECC.
//
// Enter with 512 bytes of received data in data[], 3 bytes of received ECC in
// received_ecc[].
//
UINT8 received_ecc[3];
UINT8 checkECC (void) {
UINT8 a,b,c,y;
UINT16 x;
a = received_ecc[0] ^ ecc1B0; // Calculated ecc = received ecc?
b = received_ecc[1] ^ ecc1B1;
c = received_ecc[2] ^ ecc1B2;
if ((a | b | c) == 0) return (ECC_OK);// If so, no error; return.
if ((((a^(a>>1)) & 0x55) == 0x55) &&// Does each pair of parity bits contain
(((b^(b>>1)) & 0x55) == 0x55) &&// one error and one match?
(((c^(c>>1)) & 0x55) == 0x55)) {
x = (a & 0x80); // If so, there's a one-bit error in data[].
if (a & 0x20) x |= 0x40; // Find which byte is in error...
if (a & 0x08) x |= 0x20;
if (a & 0x02) x |= 0x10;
if (b & 0x80) x |= 0x08;
if (b & 0x20) x |= 0x04;
if (b & 0x08) x |= 0x02;
if (b & 0x02) x |= 0x01;
if (c & 0x02) x |= 0x100;
y = 0; // ... and which bit...
if (c & 0x80) y |= 0x04;
if (c & 0x20) y |= 0x02;
if (c & 0x08) y |= 0x01;
data[x] ^= (1 << y);// ... and correct it.
return (ECC_DATA_FIXED);// Return with one bit fixed.
}
y = 0xFF; // If each pair didn't contain one error
if ((a | b) == 0) y = c;// and one match, check to see if only
if ((a | c) == 0) y = b;// one bit is in error (which would mean
if ((b | c) == 0) y = a;// that the received ecc is erroneous).
if ((y & (y-1)) == 0) { // If so...
received_ecc[0] = ecc1B0;// Replace the received ecc with our
received_ecc[1] = ecc1B1;// calculated ecc.
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received_ecc[2] = ecc1B2;
return (ECC_ECC_FIXED);// Return with received ecc fixed.
}
return (ECC_ERROR); // Uncorrectable error in data or received ecc;
// return with data[] and received_ecc[]
// unchanged.
}
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ECCCFG
E628
15.9.4 ECCCFG
ECC Configuration Register
Bit 0 ECCM Select ECC Block Size.
ECCM selects the ECC block size mode.
0 The ECC logic operates on two blocks of 256 bytes each.
1 The ECC calculator operates on one block of 512 bytes.
ECCCFG ECC Configuration E628
b7 b6 b5 b4 b3 b2 b1 b0
0000000ECCM
R R R R R R R R/W
00000000
Bit Name Description
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ECCRESET
E629
15.9.5 ECCRESET
ECC Reset Register
Writing any value to this register resets the ECC logic. After ECCRESET is written, ECC is calculated on the next 512 bytes
passed across the GPIF or Slave FIFO interface.
ECCRESET ECC Reset E629
b7 b6 b5 b4 b3 b2 b1 b0
xxxxxxxx
W W W W W W W W
00000000
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ECC1B0
E62A
15.9.6 ECC1B0
ECC 1 Byte 0 Register
7:0 LINE[15:8] Bits 8-15 of the line parity. See the SmartMedia Specification.
ECC1B0 ECC 1 Byte 0 E62A
b7 b6 b5 b4 b3 b2 b1 b0
LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8
R R R R R R R R
00000000
Bit Name Description
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ECC1B1
E62B
15.9.7 ECC1B1
ECC 1 Byte 1 Register
7:0 LINE[7:0] Bits 0-7 of the line parity. See the SmartMedia Specification.
ECC1B1 ECC 1 Byte 1 E62B
b7 b6 b5 b4 b3 b2 b1 b0
LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0
R R R R R R R R
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 291
ECC1B2
E62C
15.9.8 ECC1B2
ECC 1 Byte 2 Register
7:2 COL[5:0] 6-bit column parity. See the SmartMedia Specification.
1:0 LINE[17:16] If ECCM = 0, these bits are set to ‘11’ per the SmartMedia Specification. If ECCM = 1, these bits hold
bits 16 and 17 of the line parity.
ECC1B2 ECC 1 Byte 2 E62C
b7 b6 b5 b4 b3 b2 b1 b0
COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16
R R R R R R R R
00000000
Bit Name Description
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ECC2B0
E62D
15.9.9 ECC2B0
ECC 2 Byte 0 Register
7:0 LINE[15:8] Bits 8-15 of the line parity. See the SmartMedia Specification.
ECC2B0 ECC 2 Byte 0 E62D
b7 b6 b5 b4 b3 b2 b1 b0
LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8
R R R R R R R R
00000000
Bit Name Description
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ECC2B1
E62E
15.9.10 ECC2B1
ECC 2 Byte 1 Register
7:0 LINE[7:0] Bits 0-7 of the line parity. See the SmartMedia Specification.
ECC2B1 ECC 2 Byte 1 E62E
b7 b6 b5 b4 b3 b2 b1 b0
LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0
R R R R R R R R
00000000
Bit Name Description
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ECC2B2
E62F
15.9.11 ECC2B2
ECC 2 Byte 2 Register
7;2 COL[5:0] This is the 6-bit column parity. See the SmartMedia Specification.
ECC2B2 ECC 2 Byte 2 E62F
b7 b6 b5 b4 b3 b2 b1 b0
COL5 COL4 COL3 COL2 COL1 COL0 1 1
R R R R R R R R
00000000
Bit Name Description
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UDMACRCx
E67D
15.10 UDMA CRC Registers
15.10.1 UDMACRCx
UDMA CRC Registers
These two registers are strictly for debug purposes. The CRC represented by these registers is calculated based on the rules
defined in the ATAPI specification for UDMA transfers. It is calculated automatically by the GPIF as data is transferred on
FD[15:0].
These registers return the live calculation of the CRC at any point in the transfer, but are reset to the seed value of 0x4ABA
upon the GPIF entering the IDLE state. These registers are writable, therefore, the currently calculated CRC including the
seed value can be overwritten at any time.
UDMACRCH
see Section 15.15 E67D
b7 b6 b5 b4 b3 b2 b1 b0
CRC[15:8]
RW RW RW RW RW RW RW RW
01001010
UDMACRCL
see Section 15.15 E67E
b7 b6 b5 b4 b3 b2 b1 b0
CRC[7:0]
RW RW RW RW RW RW RW RW
10111010
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UDMACRCQUALIFIER
E67F
15.10.2 UDMACRCQUALIFIER
UDMA Qualifier Register
This register only applies to UDMA IN transactions that are host terminated. Otherwise, this register can be completely
ignored.
This register covers a very specific and potentially nonexistent (from a typical system implementation standpoint*) UDMA
CRC situation. However rare the situation may be, it is still allowed by the ATAPI specification and thus must be considered
and solved by this register.
The ATAPI specification says that if the host (in this case the GPIF) terminates a UDMA IN transaction, that the device (e.g.,
the disk drive) is allowed to send up to three more words after the host deactivates the HDMARDY signal. These ‘dribble’
words may not be of interest to the host and thus may be discarded. However, CRC must still be calculated on them since the
host and the device must compare and match the CRC at the end of the transaction to consider the transfer error-free.
The GPIF normally only calculates CRC on words that are written into the FIFO (and not discarded). This poses a problem
since, in this case, some words are discarded but still must be included in the CRC calculation. This register gives a way to
have the GPIF calculate CRC on the extra discarded words as well.
The user would program this register in the following way. The QENABLE bit would be set to ‘1’. The QSIGNAL[2:0] field
would be programmed to select the CTL pin that coincides with the UDMA STOP signal. The QSTATE bit would be pro-
grammed to be ‘0’. This instructs the GPIF to calculate CRC on any DSTROBE edges from the device when STOP=0, which
solves the problem.
7 QENABLE This bit enables the CRC qualifier feature, and thus the other bits in this register.
3QSTATE This bit determines what state the CRC qualifier signal (selected by QSIGNAL[2:0] below) must be in
to allow CRC to be calculated on words being written into the GPIF.
2:0 QSIGNAL[2:0] These bits select which of the CTL[5:0] pins is the CRC qualifier signal.
Note A typical UDMA system has the device, instead of the host, terminate UDMA IN transfers thus completely avoiding this situation.
UDMACRCQUALIFIER E67F
b7 b6 b5 b4 b3 b2 b1 b0
QENABLE 0 0 0 QSTATE QSIGNAL[2:0]
RW RRRRW RW RW RW
00000000
Bit Name Description
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USBCS
E680
15.11 USB Control
15.11.1 USBCS
USB Control and Status Register
7HSM High-Speed Mode.
If HSM = 1, the FX2LP SIE is operating in High-Speed Mode, 480 bits/s. Zero-to-one transition of this
bit causes a HSGRANT interrupt request.
3DISCON Signal a Disconnect on the DISCON Pin.
DISCON is one of the EZ-USB control bits in the USBCS (USB Control and Status) register that con-
trol the ReNumeration process. Setting this bit to ‘1’ causes a disconnect from the USB bus by
removing the internal 1.5K pull up resistor from the D+. A boot EEPROM may be used to default this
bit to ‘1’ at startup time. This bit also resets several registers. See the Resets chapter on page 83 for
details.
2NOSYNSOF Disable Synthesizing Missing SOFs.
1 Disable synthesizing missing SOFs.
1 RENUM Renumerate.
This bit controls whether USB device requests are handled by firmware or automatically by the EZ-
USB. When RENUM=0, the USB core handles all device requests. When RENUM=1, the firmware
handles all device requests except Set_Address. Set RENUM=1 during a bus disconnect to transfer
USB control to the firmware. The EZ-USB automatically sets RENUM=1 under two conditions.
■Completion of a ‘C2’ boot load
■When external memory is used (EA=1) and no boot EEPROM is used
0SIGRSUME Signal Remote Device Resume.
Set SIGRSUME=1 to drive the ‘K’ state onto the USB bus. This should be done only by a device that
is capable of remote wakeup, and then only during the SUSPEND state. To signal RESUME, set SIG-
RSUME=1, wait 10-15 ms, then set SIGRSUME=0.
USBCS USB Control and Status E680
b7 b6 b5 b4 b3 b2 b1 b0
HSM 0 0 0 DISCON NOSYNSOF RENUM SIGRSUME
R R R R R/W R/W R/W R/W
x 0 0 0 0 0 0 0
Bit Name Description
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SUSPEND
E681
15.11.2 SUSPEND
Enter Suspend State Register
7:0 Suspend Enable Suspend Regardless of Bus State.
Write any value to this register to prepare the chip for standby without having to wait for a bus sus-
pend.
SUSPEND Put Chip into SUSPEND State E681
b7 b6 b5 b4 b3 b2 b1 b0
xxxxxxxx
W W W W W W W W
x x x x x x x x
Bit Name Description
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WAKEUPCS
E682
15.11.3 WAKEUPCS
Wakeup Control and Status Register
EZ-USB has two pins that can be activated by external logic to take EZ-USB out of standby. These pins are called WAKEUP
and WU2.
7WU2 Wakeup Initiated from WU2 Pin.
The EZ-USB sets this status bit to ‘1’ when wakeup was initiated by the WU2 pin. Write a ‘1’ to this bit
to clear it.
6WU Wakeup Initiated from WU Pin.
The EZ-USB sets this bit to ‘1’ when wakeup was initiated by the WU pin. Write a ‘1’ to this bit to clear
it.
5WU2POL Polarity of the WU2 Pin.
0Active low
1 Active high
4WUPOL Polarity of the WU Pin.
0Active low
1 Active high
2 DPEN Enable/Disable DPLUS Wakeup.
Activity on the USB DPLUS signal normally initiates a USB wakeup sequence.
0Disable
1 Enable
1WU2EN Enable WU2 Wakeup.
1 Enable wakeup from WU2 pin
0WUEN Enable WU Wakeup.
1 Enable wakeup from the WAKEUP pin
WAKEUPCS Wakeup Control and Status E682
b7 b6 b5 b4 b3 b2 b1 b0
WU2 WU WU2POL WUPOL 0DPEN WU2EN WUEN
R/W R/W R/W R/W RR/W R/W R/W
x x 0 0 0 1 0 1
Bit Name Description
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TOGCTL
E683
15.11.4 TOGCTL
Data Toggle Control Register
7Q Data Toggle Value.
0 Indicates DATA0 and
1 Indicates DATA1, for the endpoint selected by the IO and EP3:0 bits. Write the endpoint
select bits (IO and EP3:0), before reading this value.
6S Set Data Toggle to DATA1.
After selecting the desired endpoint by writing the endpoint select bits (IO and EP3:0), set S=1 to set
the data toggle to DATA1. Do not change the endpoint selection bits while this bit is being written.
5R Set Data Toggle to DATA0.
1 Set the data toggle to DATA0. Do not change the endpoint selection bits while this bit is
being written.
4IO Select IN or OUT Endpoint. Set this bit to select an endpoint direction prior to setting its ‘R’ or ‘S’ bit.
0 Selects an OUT endpoint
1 Selects an IN endpoint
3:0 EP[3:0] Select Endpoint.
Set these bits to select an endpoint prior to setting its ‘R’ or ‘S’ bit. Valid values are 0, 1, 2, 4, 6, and 8.
TOGCTL Data Toggle Control E683
b7 b6 b5 b4 b3 b2 b1 b0
Q S R IO EP3 EP2 EP1 EP0
R R R R/W R/W R/W R/W R/W
x 0 0 0 0 0 0 0
Bit Name Description
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USBFRAMEH
E684
15.11.5 USBFRAMEH
USB Frame Count High Register
2:0 FC[10:8] High Bits for USB Frame Count.
Every millisecond the host sends a SOF token indicating ‘Start Of Frame,’ along with an 11 bit incre-
menting frame count. The EZ-USB copies the frame count into these registers at every SOF. One use
of the frame count is to respond to the USB SYNC_FRAME Request. If the USB core detects a miss-
ing or garbled SOF, it generates an internal SOF and increments USBFRAMEL-USBRAMEH.
USBFRAMEH USB Frame Count High E684
b7 b6 b5 b4 b3 b2 b1 b0
00000FC10FC9FC8
R R R R R R R R
0 0 0 0 0 x x x
Bit Name Description
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USBFRAMEL
E685
15.11.6 USBFRAMEL
USB Frame Count Low Register
7:0 FC[7:0] Low Byte for USB Frame Count.
Every millisecond the host sends a SOF token indicating ‘Start Of Frame,’ along with an 11 bit incre-
menting frame count. The EZ-USB copies the frame count into these registers at every SOF. One use
of the frame count is to respond to the USB SYNC_FRAME Request. If the USB core detects a miss-
ing or garbled SOF, it generates an internal SOF and increments USBFRAMEL-USBRAMEH.
USBFRAMEL USB Frame Count Low E685
b7 b6 b5 b4 b3 b2 b1 b0
FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0
R R R R R R R R
x x x x x x x x
Bit Name Description
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MICROFRAME
E686
15.11.7 MICROFRAME
USB Microframe Count Register
2:0 MF[2:0] Last Occurring Microframe.
MICROFRAME contains a count 0-7 which indicates which of the eight 125-µs microframes last
occurred. This register is active only when FX2LP is operating at high speed (480 Mbps).
MICROFRAME USB Microframe Count, 0-7 E686
b7 b6 b5 b4 b3 b2 b1 b0
00000MF2MF1MF0
R R R R R R R R
0 0 0 0 0 x x x
Bit Name Description
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FNADDR
E687
15.11.8 FNADDR
USB Function Address Register
6:0 FA[6:0] USB Function Address.
During the USB enumeration process, the host sends a device a unique 7 bit address, which the USB
core copies into this register. There is normally no reason for the CPU to know its USB device
address because the USB Core automatically responds only to its assigned address.
FNADDR USB Function Address E687
b7 b6 b5 b4 b3 b2 b1 b0
0 FA6 FA5 FA4 FA3 FA2 FA1 FA0
R R R R R R R R
0 x x x x x x x
Bit Name Description
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EP0BCH
E68A
15.12 Endpoints
15.12.1 EP0BCH
Endpoint 0 (Byte Count High) Register
7:0 BC[15:8] High Order Byte Count.
Even though the EP0 buffer is only 64 bytes, the EP0 byte count is expanded to 16 bits to allow using
the SUDPTR with a custom length, instead of USB-dictated length (from Setup Data Packet and
number of requested bytes). The byte count bits in parentheses apply only when SDPAUTO
(SUDPTRCTL.0) = 0.
The SIE normally determines how many bytes to send over EP0 in response to a device request by
taking the smaller of (a) the wLength field in the SETUP packet, and (b) the number of bytes available
for transfer (byte count).
EP0BCH Endpoint 0 Byte Count High E68A
b7 b6 b5 b4 b3 b2 b1 b0
(BC15) (BC14) (BC13) (BC12) (BC11) (BC10) (BC9) (BC8)
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
Bit Name Description
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EP0BCL
E68B
15.12.2 EP0BCL
Endpoint 0 Control and Status (Byte Count Low) Register
7:0 BC[7:0] Low Order Byte Count.
Even though the EP0 buffer is only 64 bytes, the EP0 byte count is expanded to 16 bits to allow using
the SUDPTR with a custom length, instead of USB-dictated length (from Setup Data Packet and
number of requested bytes). The byte count bits in parentheses apply only when SDPAUTO
(SUDPTRCTL.0) = 0.
EP0BCL Endpoint 0 Byte Count Low E68B
b7 b6 b5 b4 b3 b2 b1 b0
(BC7) BC6 BC5 BC4 BC3 BC2 BC1 BC0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
Bit Name Description
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EP1OUTBC
E68D
15.12.3 EP1OUTBC
Endpoint 1 OUT Byte Count Register
6:0 BC[6:0] Endpoint 1 OUT Byte Count.
EP1OUTBC Endpoint 1 OUT Byte Count E68D
b7 b6 b5 b4 b3 b2 b1 b0
0 BC6 BC5 BC4 BC3 BC2 BC1 BC0
R/W R/W R/W R/W R/W R/W R/W R/W
0 x x x x x x x
Bit Name Description
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EP1INBC
E68F
15.12.4 EP1INBC
Endpoint 1 IN Byte Count Register
6:0 BC[6:0] Endpoint 1 IN Byte Count.
EP1INBC Endpoint 1 IN Byte Count E68F
b7 b6 b5 b4 b3 b2 b1 b0
0 BC6 BC5 BC4 BC3 BC2 BC1 BC0
R/W R/W R/W R/W R/W R/W R/W R/W
0 x x x x x x x
Bit Name Description
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EP2BCH
E690
15.12.5 EP2BCH
Endpoint 2 Byte Count High Register
2:0 BC[10:8] Endpoint 2 Byte Count High.
EP2 can be maximum of either 512 or 1024 bytes. These are the high 3 bits of the byte count.
EP2BCH
see Section 15.15 Endpoint 2 Byte Count High E690
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 BC10 BC9 BC8
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 x x x
Bit Name Description
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EP6BCH
E698
15.12.6 EP6BCH
Endpoint 6 Byte Count High Register
2:0 BC[10:8] Endpoint 6 Byte Count High.
EP6 can be maximum of either 512 or 1024 bytes. These are the high 3 bits of the byte count.
EP6BCH
see Section 15.15 Endpoint 6 Byte Count High E698
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 BC10 BC9 BC8
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 x x x
Bit Name Description
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EP4BCH
E694
15.12.7 EP4BCH
Endpoint 4 Byte Count High Register
1:0 BC[9:8] Endpoint 4 Byte Count High.
EP4 can be 512 bytes only. These are the high 2 bits of the byte count.
EP4BCH
see Section 15.15 Endpoint 4 Byte Count High E694
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 BC9 BC8
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 x x
Bit Name Description
312 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP8BCH
E69C
15.12.8 EP8BCH
Endpoint 8 Byte Count High Register
1:0 BC[9:8] Endpoint 8 Byte Count High.
EP8 can be 512 bytes only. These are the high 2 bits of the byte count.
EP8BCH
see Section 15.15 Endpoint 8 Byte Count High E69C
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 BC9 BC8
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 x x
Bit Name Description
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EPxBCL
E691
15.12.9 EPxBCL
Endpoint 2, 4, 6, 8 Byte Count Low Registers
7:0 BC[7:0] Byte Count.
Low byte count for Endpoints 2, 4, 6, and 8.
EP2BCL
see Section 15.15 Endpoint 2 Byte Count Low E691
EP4BCL
see Section 15.15 Endpoint 4 Byte Count Low E695
EP6BCL
see Section 15.15 Endpoint 6 Byte Count Low E699
EP8BCL
see Section 15.15 Endpoint 8 Byte Count Low E69D
b7 b6 b5 b4 b3 b2 b1 b0
BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
Bit Name Description
314 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP0CS
E6A0
15.12.10 EP0CS
Endpoint 0 Control and Status Register
7 HSNAK Hand Shake w/NAK.
The STATUS stage consists of an empty data packet with the opposite direction of the data stage, or
an IN if there was no data stage. This empty data packet gives the device a chance to ACK, NAK, or
STALL the entire CONTROL transfer. Write a ‘1’ to the NAK (handshake NAK) bit to clear it and
instruct the USB core to ACK the STATUS stage. The HSNAK bit holds off completing the CONTROL
transfer until the device has had time to respond to a request.Clear the HSNAK bit (by writing ‘1’ to it)
to instruct the USB core to ACK the status stage of the transfer.
1 BUSY EP0 Buffer Busy.
BUSY is a read only bit that is automatically cleared when a SETUP token arrives. The BUSY bit is
set by writing a byte count to EP0BCL.
0STALL EP0 Stalled.
STALL is a read/write bit that is automatically cleared when a SETUP token arrives. The STALL bit is
set by writing a ‘1’ to the register bit.
While STALL=1, the USB core sends the STALL PID for any IN or OUT token. This can occur in
either the data or handshake phase of the CONTROL transfer.
Note To indicate an endpoint stall on endpoint zero, set both the STALL and HSNAK bits. Setting the
STALL bit alone causes endpoint zero to NAK forever because the host keeps the control transfer
pending.
EP0CS Endpoint 0 Control and Status E6A0
b7 b6 b5 b4 b3 b2 b1 b0
HSNAK 0 0 0 0 0 BUSY STALL
R/W R/W R/W R/W R/W R/W RR/W
10000000
Bit Name Description
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EP1OUTCS
E6A1
15.12.11 EP1OUTCS
Endpoint 1 OUT Control and Status Register
1 BUSY OUT Endpoint Busy.
The BUSY bit indicates the status of the endpoint’s OUT Buffer EP1OUTBUF. The USB core sets
BUSY=0 when the host data is available in the OUT buffer. The firmware sets BUSY=1 by loading the
endpoint’s byte count register.
When BUSY=1, endpoint RAM data is invalid—the endpoint buffer has been emptied by the firmware
and is waiting for new OUT data from the host, or it is the process of being loaded over the USB.
BUSY=0 when the USB OUT transfer is complete and endpoint RAM data in EP1OUTBUF is avail-
able for the firmware to read. USB OUT tokens for the endpoint are NAK’d while BUSY=1 (the firm-
ware is still reading data from the OUT endpoint).
A 1-to-0 transition of BUSY (indicating that the firmware can access the buffer) generates an interrupt
request for the OUT endpoint. After the firmware reads the data from the OUT endpoint buffer, it
loads the endpoint’s byte count register with any value to re-arm the endpoint, which automatically
sets BUSY=1. This enables the OUT transfer of data from the host in response to the next OUT
token. The CPU should never read endpoint data while BUSY=1.
0STALL OUT Endpoint Stalled.
Each bulk endpoint (IN or OUT) has a STALL bit in its Control and Status register (bit 0). If the CPU
sets this bit, any requests to the endpoint return a STALL handshake rather than ACK or NAK. The
Get Status-Endpoint Request returns the STALL state for the endpoint indicated in byte four of the
request. Note that bit seven of the endpoint number EP (byte 4) specifies direction.
EP1OUTCS Endpoint 1 OUT Control and Status E6A1
b7 b6 b5 b4 b3 b2 b1 b0
000000BUSYSTALL
R/W R/W R/W R/W R/W R/W RR/W
00000000
Bit Name Description
316 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP1INCS
E6A2
15.12.12 EP1INCS
Endpoint 1 IN Control and Status Register
1 BUSY IN Endpoint Busy.
The BUSY bit indicates the status of the endpoint’s IN Buffer EP1INBUF. The USB core sets
BUSY=0 when the endpoint’s IN buffer is empty and ready for loading by the firmware. The firmware
sets BUSY=1 by loading the endpoint’s byte count register.
When BUSY=1, the firmware should not write data to an IN endpoint buffer, because the endpoint
FIFO could be in the act of transferring data to the host over the USB. BUSY=0 when the USB IN
transfer is complete and endpoint RAM data is available for firmware access. USB IN tokens for the
endpoint are NAK’d while BUSY=0 (the firmware is still loading data into the endpoint buffer).
A 1-to-0 transition of BUSY (indicating that the firmware can access the buffer) generates an interrupt
request for the IN endpoint. After the firmware writes the data to be transferred to the IN endpoint buf-
fer, it loads the endpoint’s byte count register with the number of bytes to transfer, which automati-
cally sets BUSY=1. This enables the IN transfer of data to the host in response to the next IN token.
Again, the CPU should never load endpoint data while BUSY=1.
The firmware writes a ‘1’ to an IN endpoint busy bit to disarm a previously armed endpoint. (This sets
BUSY=0.) The firmware should do this only after a USB bus reset, or when the host selects a new
interface or alternate setting that uses the endpoint. This prevents stale data from a previous setting
from being accepted by the host’s first IN transfer that uses the new setting.
0STALL IN Endpoint Stalled.
Each bulk endpoint (IN or OUT) has a STALL bit in its Control and Status register (bit 0). If the CPU
sets this bit, any requests to the endpoint return a STALL handshake rather than ACK or NAK. The
Get Status-Endpoint Request returns the STALL state for the endpoint indicated in byte four of the
request. Note that bit seven of the endpoint number EP (byte 4) specifies direction.
EP1INCS Endpoint 1 IN Control and Status E6A2
b7 b6 b5 b4 b3 b2 b1 b0
000000BUSYSTALL
R/W R/W R/W R/W R/W R/W RR/W
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 317
EP2CS
E6A3
15.12.13 EP2CS
Endpoint 2 Control and Status Register
6:4 NPAK[2:0] Number of Packets in FIFO.
The number of packets in the FIFO. 0-4 Packets.
3FULL Endpoint FIFO Full.
1 Indicates that the Endpoint FIFO is full.
2EMPTY Endpoint FIFO Empty.
1 Indicates that the Endpoint FIFO is empty.
0STALL Endpoint STALL.
1 Stall an endpoint
0 Clear a stall
When the stall bit is ‘1,’ the USB core returns a STALL handshake for all requests to the endpoint.
This notifies the host that something unexpected has happened.
EP2CS Endpoint 2 Control and Status E6A3
b7 b6 b5 b4 b3 b2 b1 b0
0 NPAK2 NPAK1 NPAK0 FULL EMPTY 0 STALL
R R R R R R R R/W
00101000
Bit Name Description
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EP4CS
E6A4
15.12.14 EP4CS
Endpoint 4 Control and Status Register
5:4 NPAK[1:0] Number of Packets in FIFO.
The number of packets in the FIFO. 0-2 Packets.
3FULL Endpoint FIFO Full.
1 Indicates that the Endpoint FIFO is full.
2EMPTY Endpoint FIFO Empty.
1 Indicates that the Endpoint FIFO is empty.
0STALL Endpoint STALL.
1 Stall an endpoint
0 Clear a stall
When the stall bit is ‘1,’ the USB core returns a STALL handshake for all requests to the endpoint.
This notifies the host that something unexpected has happened.
EP4CS Endpoint 4 Control and Status E6A4
b7 b6 b5 b4 b3 b2 b1 b0
0 0 NPAK1 NPAK0 FULL EMPTY 0 STALL
R R R R R R R R/W
00101000
Bit Name Description
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EP6CS
E6A5
15.12.15 EP6CS
Endpoint 6 Control and Status Register
6:4 NPAK[2:0] Number of Packets in FIFO.
The number of packets in the FIFO. 0-4 Packets.
3FULL Endpoint FIFO Full.
1 Indicates that the Endpoint FIFO is full.
2EMPTY Endpoint FIFO Empty.
1 Indicates that the Endpoint FIFO is empty.
0STALL Endpoint STALL.
1 Stall an endpoint
0 Clear a stall
When the stall bit is ‘1,’ the USB core returns a STALL handshake for all requests to the endpoint.
This notifies the host that something unexpected has happened.
EP6CS Endpoint 6 Control and Status E6A5
b7 b6 b5 b4 b3 b2 b1 b0
0 NPAK2 NPAK1 NPAK0 FULL EMPTY 0 STALL
R R R R R R R R/W
00000100
Bit Name Description
320 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP8CS
E6A6
15.12.16 EP8CS
Endpoint 8 Control and Status Register
5:4 NPAK[1:0] Number of Packets in FIFO.
The number of packets in the FIFO. 0-2 Packets.
3FULL Endpoint FIFO Full.
1 Indicates that the Endpoint FIFO is full.
2EMPTY Endpoint FIFO Empty.
1 Indicates that the Endpoint FIFO is empty.
0STALL Endpoint STALL.
1 Stall an endpoint
0 Clear a stall
When the stall bit is ‘1,’ the USB core returns a STALL handshake for all requests to the endpoint.
This notifies the host that something unexpected has happened.
EP8CS Endpoint 8 Control and Status E6A6
b7 b6 b5 b4 b3 b2 b1 b0
0 0 NPAK1 NPAK0 FULL EMPTY 0 STALL
R R R R R R R R/W
00000100
Bit Name Description
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EP2FIFOFLGS
E6A7
15.12.17 EP2FIFOFLGS
Endpoint 2 Slave FIFO Flags Register
2PF Programmable Flag.
State of the EP2 Programmable Flag.
1EF Empty Flag.
State of the EP2 Empty Flag.
0FF Full Flag.
State of the EP2 Full Flag.
Note FIFOPINPOLAR settings do not affect the behavior of these bits.
EP2FIFOFLGS Endpoint 2 Slave FIFO Flags E6A7
b7 b6 b5 b4 b3 b2 b1 b0
00000PFEFFF
R R R R R R R R
00000010
Bit Name Description
322 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP4FIFOFLGS
E6A8
15.12.18 EP4FIFOFLGS
Endpoint 4 Slave FIFO Flags Register
2PF Programmable Flag.
State of the EP4 Programmable Flag.
1EF Empty Flag.
State of the EP4 Empty Flag.
0FF Full Flag.
State of the EP4 Full Flag.
Note FIFOPINPOLAR settings do not affect the behavior of these bits.
EP4FIFOFLGS Endpoint 4 Slave FIFO Flags E6A8
b7 b6 b5 b4 b3 b2 b1 b0
00000PFEFFF
R R R R R R R R
00000010
Bit Name Description
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EP6FIFOFLGS
E6A9
15.12.19 EP6FIFOFLGS
Endpoint 6 Slave FIFO Flags Register
2PF Programmable Flag.
State of the EP6 Programmable Flag.
Note The default value is different from EP2FIFOFLGS.PF and EP4FIFOFLGS.PF.
1EF Empty Flag.
State of the EP6 Empty Flag.
0FF Full Flag.
State of the EP6 Full Flag.
Note FIFOPINPOLAR settings do not affect the behavior of these bits.
EP6FIFOFLGS Endpoint 6 Slave FIFO Flags E6A9
b7 b6 b5 b4 b3 b2 b1 b0
00000PFEFFF
R R R R R R R R
00000110
Bit Name Description
324 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP8FIFOFLGS
E6AA
15.12.20 EP8FIFOFLGS
Endpoint 8 Slave FIFO Flags Register
2PF Programmable Flag.
State of the EP8 Programmable Flag.
Note The default value is different from EP2FIFOFLGS.PF and EP4FIFOFLGS.PF.
1EF Empty Flag.
State of the EP8 Empty Flag.
0FF Full Flag.
State of the EP8 Full Flag.
Note FIFOPINPOLAR settings do not affect the behavior of these bits.
EP8FIFOFLGS Endpoint 8 Slave FIFO Flags E6AA
b7 b6 b5 b4 b3 b2 b1 b0
00000PFEFFF
R R R R R R R R
00000110
Bit Name Description
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EP2FIFOBCH
E6AB
15.12.21 EP2FIFOBCH
Endpoint 2 Slave FIFO Total Byte Count High Register
4:0 BC[12:8] Byte Count High
Total number of bytes in Endpoint FIFO. Maximum of 4096 bytes.
EP2FIFOBCH Endpoint 2 Slave FIFO Total Byte Count High E6AB
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 BC12 BC11 BC10 BC9 BC8
R R R R R R R R
00000000
Bit Name Description
326 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP6FIFOBCH
E6AF
15.12.22 EP6FIFOBCH
Endpoint 6 Slave FIFO Total Byte Count High Register
3:0 BC[11:8] Byte Count High.
Total number of bytes in Endpoint FIFO. Maximum of 2048 bytes.
EP6FIFOBCH Endpoint 6 Slave FIFO Total Byte Count High E6AF
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 BC11 BC10 BC9 BC8
R R R R R R R R
00000000
Bit Name Description
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EP4FIFOBCH
E6AD
15.12.23 EP4FIFOBCH
Endpoint 4 Slave FIFO Total Byte Count High Register
2:0 BC[10:8] Byte Count High.
Total number of bytes in Endpoint FIFO. Maximum of 1024 bytes.
EP4FIFOBCH Endpoint 4 Slave FIFO Total Byte Count High E6AD
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 BC10 BC9 BC8
R R R R R R R R
00000000
Bit Name Description
328 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP8FIFOBCH
E6B1
15.12.24 EP8FIFOBCH
Endpoint 8 Slave FIFO Total Byte Count High Register
2:0 BC[10:8] Byte Count High.
Total number of bytes in Endpoint FIFO. Maximum of 1024 bytes.
EP8FIFOBCH Endpoint 8 Slave FIFO Total Byte Count High E6B1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 BC10 BC9 BC8
R R R R R R R R
00000000
Bit Name Description
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EPxFIFOBCL
E6AC
15.12.25 EPxFIFOBCL
Endpoint 2, 4, 6, 8 Slave FIFO Byte Count Low Registers
7:0 BC[7:0] Byte Count High.
Low byte for number of bytes in Endpoint FIFO.
EP2FIFOBCL Endpoint 2 Slave FIFO Total Byte Count Low E6AC
EP4FIFOBCL Endpoint 4 Slave FIFO Total Byte Count Low E6AE
EP6FIFOBCL Endpoint 6 Slave FIFO Total Byte Count Low E6B0
EP8FIFOBCL Endpoint 8 Slave FIFO Total Byte Count Low E6B2
b7 b6 b5 b4 b3 b2 b1 b0
BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
R R R R R R R R
00000000
Bit Name Description
330 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
SUDPTRx
E6B3
15.12.26 SUDPTRx
Setup Data Pointer High and Low Address Registers
15:0 A[15:0] Setup Data Pointer.
This buffer is used as a target or source by the Setup Data Pointer and it must be WORD (2-byte)
aligned. This 16-bit pointer, SUDPTRH:L provides hardware assistance for handling CONTROL IN
transfers.
When the firmware loads SUDPTRL, the SIE automatically responds to IN commands with the appro-
priate data. If SDPAUTO=1, the length field is taken from the packet or descriptor. If SDPAUTO=0,
SUDPTRL triggers a send to the host and the length is taken from the EP0BCH and EP0BCL bytes.
SUDPTRH Setup Data Pointer High Address Byte E6B3
b7 b6 b5 b4 b3 b2 b1 b0
A15 A14 A13 A12 A11 A10 A9 A8
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
SUDPTRL Setup Data Pointer Low Address Byte E6B4
b7 b6 b5 b4 b3 b2 b1 b0
A7 A6 A5 A4 A3 A2 A1 A0
R/W R/W R/W R/W R/W R/W R/W R
x x x x x x x 0
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 331
SUDPTRCTL
E6B5
15.12.27 SUDPTRCTL
Setup Data Pointer Auto Register
0 SDPAUTO Setup Data Pointer Auto Mode.
To send a block of data using the Setup Data Pointer, the block’s starting address is loaded into
SUDPTRH:L. The block length must previously have been set; the method for accomplishing this
depends on the state of the SDPAUTO bit.
0 Manual Mode. Used for general purpose block transfers. Firmware writes the block length
to EP0BCH:L.
1 Auto Mode. Used for sending Device, Configuration, String, Device Qualifier, and Other
Speed Configuration descriptors only. The block length is automatically read from the length
field of the descriptor itself; no explicit loading of EP0BCH:L is necessary.
Writing to SUDPTRL starts the transfer; the EZ-USB automatically sends the entire block, packetizing
as necessary.
Note When SDPAUTO = 0, writing to EP0BCH:L only sets the block length; it does not arm the trans-
fer (the transfer is armed by writing to SUDPTRL). Therefore, before performing an EP0 transfer
which does not use the Setup Data Pointer (such as, one which is meant to be armed by writing to
EP0BCL), SDPAUTO must be set to ‘1’.
SUDPTRCTL Setup Data Pointer AUTO Mode E6B5
b7 b6 b5 b4 b3 b2 b1 b0
0000000SDPAUTO
R/W R/W R/W R/W R/W R/W R/W R/W
00000001
Bit Name Description
332 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
SETUPDAT
E6B8-
15.12.28 SETUPDAT
Setup Data - Eight Bytes Registers
The setup data bytes are defined as follows:
SETUPDAT[0] = bmRequestType
SETUPDAT[1] = bmRequest
SETUPDAT[2:3] = wValue
SETUPDAT[4:5] = wIndex
SETUPDAT[6:7] = wLength
This buffer contains the eight bytes of SETUP packet data from the most recently received CONTROL transfer.
The data in SETUPBUF is valid when the SUDAV (Setup Data Available) interrupt request bit is set.
SETUPDAT 8 Bytes of Setup Data E6B8-E6BF
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R R R R R R R R
x x x x x x x x
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 333
GPIFWFSELECT
E6C0
15.13 General Programmable Interface
15.13.1 GPIFWFSELECT
GPIF Waveform Selector Register
7:6 SINGLEWR[1:0] Single Write Waveform Index.
Index to the Waveform program to run when a ‘Single Write’ is triggered by the firmware.
5:4 SINGLERD[1:0] Single Read Waveform Index.
Index to the Waveform program to run when a ‘Single Read’ is triggered by the firmware.
3:2 FIFOWR[1:0] FIFO Write Waveform Index.
Index to the Waveform program to run when a ‘FIFO Write’ is triggered by the firmware.
1:0 FIFORD[1:0] FIFO Read Waveform Index.
Index to the Waveform program to run when a ‘FIFO Read’ is triggered by the firmware.
Select waveform 0 [00], 1 [01], 2 [10] or 3 [11].
GPIFWFSELECT Waveform Selector E6C0
b7 b6 b5 b4 b3 b2 b1 b0
SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0 FIFORD1 FIFORD0
R/W R/W R/W R/W R/W R/W R/W R/W
11100100
Bit Name Description
334 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
GPIFIDLECS
E6C1
15.13.2 GPIFIDLECS
GPIF Done and Idle Drive Mode Register
7DONE GPIF Idle State.
0 Transaction in progress.
1 Transaction Done (GPIF is idle, hence GPIF is ready for next transaction). Fires IRQ4 if
enabled.
0 IDLEDRV Set Data Bus when GPIF Idle.
When the GPIF is idle:
0 Tri-state the Data Bus.
1 Drive the Data Bus.
GPIFIDLECS GPIF Done, GPIF Idle Drive Mode E6C1
b7 b6 b5 b4 b3 b2 b1 b0
DONE000000IDLEDRV
R/W R/W R/W R/W R/W R/W R/W R/W
10000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 335
GPIFIDLECTL
E6C2
15.13.3 GPIFIDLECTL
CTL Output in Idle Register
7:4 CTLOE[3:0] CTL Output Enables.
5:0 CTL[5:0] CTL Output States.
See GPIFCTLCFG register on page 336.
GPIFIDLECTL CTL Output States in Idle E6C2
b7 b6 b5 b4 b3 b2 b1 b0
0/‘CTLOE3 0/CTLOE2 CTL5/
CTLOE1
CTL4/
CTLOE0
CTL3 CTL2 CTL1 CTL0
R/W R/W R/W R/W R/W R/W R/W R/W
11111111
Bit Name Description
336 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
GPIFCTLCFG
E6C3
15.13.4 GPIFCTLCFG
CTL Output Drive Type Register
7TRICTL Number Active Outputs/Tri-stating.
5:0 CTL[5:0] CTL Output Drive Type
The GPIF Control pins (CTL[5:0]) have several output modes:
■CTL[3:0] can act as CMOS outputs (optionally tri-statable) or open-drain outputs.
■CTL[5:4] can act as CMOS outputs or open-drain outputs. If CTL[3:0] are configured to be tri-stat-
able, CTL[5:4] are not available.
During the IDLE State, the state of CTL[5:0] depends on register bits:
TRICTL (GPIFCTLCFG.7)
GPIFCTLCFG[5:0]
GPIFIDLECTL[5:0]
The combination of these bits defines CTL5:0 during IDLE as follows:
■If TRICTL is 0, GPIFIDLECTL[5:0] directly represent the output states of CTL5:0 during the IDLE
State. The GPIFCTLCFG[5:0] bits determine whether the CTL5:0 outputs are CMOS or open-
drain: If GPIFCTLCFG.x = 0, CTLx is CMOS; if GPIFCTLCFG.x = 1, CTLx is open drain.
■If TRICTL is 1, GPIFIDLECTL[7:4] are the output enables for the CTL[3:0] signals, and GPI-
FIDLECTL[3:0] are the output values for CTL[3:0]. CTL4 and CTL5 are unavailable in this mode.
(continued on next page)
GPIFCTLCFG CTL Output Drive Type E6C3
b7 b6 b5 b4 b3 b2 b1 b0
TRICTL 0 CTL5 CTL4 CTL3 CTL2 CTL1 CTL0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
TRICTL
(GPIFCTLCFG.7) GPIFCTLCFG[5:0] CTL[3:0] CTL[5:4]
0 0 CMOS, Not Tri-statable CMOS, Not Tri-statable
0 1 Open-Drain Open-Drain
1 X CMOS, Tri-statable Not Available
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 337
GPIFCTLCFG
E6C3
15.13.4 GPIFCTLCFG (continued)
TRICTL Control Output Output State Output Enable
0
CTL0 GPIFIDLECTL.0
N/A
(CTL Outputs are always
enabled when TRICTL = 0)
CTL1 GPIFIDLECTL.1
CTL2 GPIFIDLECTL.2
CTL3 GPIFIDLECTL.3
CTL4 GPIFIDLECTL.4
CTL5 GPIFIDLECTL.5
1
CTL0 GPIFIDLECTL.0 GPIFIDLECTL.4
CTL1 GPIFIDLECTL.1 GPIFIDLECTL.5
CTL2 GPIFIDLECTL.2 GPIFIDLECTL.6
CTL3 GPIFIDLECTL.3 GPIFIDLECTL.7
CTL4 N/A
(CTL4 and CTL5 are not available when TRICTL = 1)
CTL5
338 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
GPIFADRH
E6C4
15.13.5 GPIFADRH
GPIF Address High Register
0GPIFA8 High Bit of GPIF Address.
See GPIFADRL register on page 339.
GPIFADRH
see Section 15.15 GPIF Address High E6C4
b7 b6 b5 b4 b3 b2 b1 b0
0000000GPIFA8
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 339
GPIFADRL
E6C5
15.13.6 GPIFADRL
GPIF Address Low Register
7:0 GPIFA[7:0] Lower eight bits of GPIF Address.
Data written to this register immediately appears as the bus address on the ADR[7:0] pins.
GPIFADRL
see Section 15.15 GPIF Address Low E6C5
b7 b6 b5 b4 b3 b2 b1 b0
GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
340 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
FLOWSTATE
E6C6
15.13.7 FLOWSTATE
GPIF Flow State Register
Any one (and only one) of the seven GPIF states in a waveform can be programmed to be the flow state. This register defines
which state, if any, in the next invoked GPIF waveform will be the flow state.
7FSE Global Flow State Enable.
Global enable for the flow state. When it is disabled all flow state registers are don’t care and the next
waveform invocation does not cause a flow state to be used.
2:0 FS[2:0] Flow State Selection.
Defines which GPIF state is the flow state. Valid values are 0-6.
FLOWSTATE E6C6
b7 b6 b5 b4 b3 b2 b1 b0
FSE 0 0 0 0 FS[2:0]
RW R R R R RW RW RW
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 341
FLOWLOGIC
E6C7
15.13.8 FLOWLOGIC
GPIF Flow State Logic Register
The bit definitions for this register are analogous to the bit definitions in the RDY LOGIC opcode in a waveform descriptor.
Except, instead of controlling the branching for a decision point, it controls the freezing or flowing of data on the bus in a flow
state.
The user defines the states of CTL[5:0] for when the flow logic equals ‘0’ and ‘1’ (see FLOWEQ0_CTL and FLOWEQ1_CTL).
This is useful in activating or deactivating protocol ready signals to hold off an external master (where the GPIF is acting like
a slave) in response to internal FIFO flags warning of an impending underflow or overflow situation.
In the case where the GPIF is the master, the user also defines whether Master strobe (a CTL pin in this case; see FLOW-
STB) toggles (reads or writes data on the bus) when the flow logic evaluates to a ‘1’ or a ‘0’. This is useful for the GPIF to con-
sider protocol ready signals from the slave as well as FIFO flags to decide when to clock data out of or into the FIFOs and
when to freeze the data flow instead.
It should be noted that this flow logic does not replace the decision point logic defined in a waveform descriptor. The decision
point logic in a waveform descriptor is still used to decide when to branch out of the flow state. The decision point logic can
use an entirely different pair of ready signals than the flow logic in making its decisions.
7:6 LFUNC[1:0] Flow State Logic Function.
00 A AND B
01 A OR B
10 A XOR B
11 !A AND B
Since the flow logic decision can be based on the output being a ‘1’ or a ‘0’, NAND, NOR, XNOR and
!(!A AND B) operations can be achieved as well. Note that !(!A AND B) is the same as (A OR !B).
5:3 TERMA[2:0] Flow State Logic Function Arguments.
2:0 TERMB[2:0] 0 RDY[0]
1 RDY[1]
2 RDY[2]
3 RDY[3]
4 RDY[4]
5 RDY[5] or TC-Expiration (depending on GPIF_READYCFG.5)
6 FIFO Flag (PF, EF, or FF depending on GPIF_EPxFLGSEL)
7 8051 RDY (GPIF_READYCFG.7)
FLOWLOGIC E6C7
b7 b6 b5 b4 b3 b2 b1 b0
LFUNC[1:0] TERMA[2:0] TERMB[2:0]
RW RW RW RW RW RW RW RW
00000000
Bit Name Description
342 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
FLOWEQxCTL
E6C8
15.13.9 FLOWEQxCTL
GPIF Flow Logic CTL Output Drive Registers
FLOWEQ0CTL defines the state of the CTL5:0 pins when the output of the flow logic equals zero; FLOWEQ1CTL defines the
state when the logic output equals one. During a flow state, the CTL opcode in the waveform descriptor is completely ignored
and the behavior of the CTL[5:0] pins are defined by these two registers instead.
CTLOEx If TRICTL = 1, CTL5:4 are unused and CTLOE3:0 specifies whether the corresponding CTL3:0 out-
put signals are tri-stated.
0 Tri-state CTLx
1Drive CTLx
CTLx Specifies the state to set each CTLx signal to during this entire State.
1 High level
If the CTLx bit in the GPIFCTLCFG register is set to ‘1’, the output driver is an open drain.
If the CTLx bit in the GPIFCTLCFG register is set to ‘0’, the output driver is driven to CMOS levels.
0 Low level
Defined by FLOWEQxCTL and these bits, instead:
TRICTL (GPIFCTLCFG.7), as described in section 10.2.3.1 Control Output Modes on page 124.
GPIFCTLCFG[5:0].
The combination of these bits defines CTL5:0 during a Flow State as follows:
■If TRICTL is ‘0’, FLOWEQxCTL[5:0] directly represent the output states of CTL5:0 during the
Flow State. The GPIFCTLCFG[5:0] bits determine whether the CTL5:0 outputs are CMOS or
open drain: If GPIFCTLCFG.x = 0, CTLx is CMOS; if GPIFCTLCFG.x = 1, CTLx is open drain.
■If TRICTL is ‘1’, FLOWEQxCTL[7:4] are the output enables for the CTL[3:0] signals, and
FLOWEQxCTL[3:0] are the output values for CTL[3:0]. CTL4 and CTL5 are unavailable in this
mode.
(continued on next page)
FLOWEQ0CTL E6C8
b7 b6 b5 b4 b3 b2 b1 b0
CTLOE3 CTLOE2 CTLOE1/ CTL5 CTLOE0/ CTL4 CTL3 CTL2 CTL1 CTL0
RW RW RW RW RW RW RW RW
00000000
FLOWEQ1CTL E6C9
b7 b6 b5 b4 b3 b2 b1 b0
CTLOE3 CTLOE2 CTLOE1/ CTL5 CTLOE0/ CTL4 CTL3 CTL2 CTL1 CTL0
RW RW RW RW RW RW RW RW
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 343
FLOWEQxCTL
E6C8
15.13.9 FLOWEQxCTL (continued)
TRICTL Control
Output Output State
Drive Type
(0 = CMOS,
1 = Open-Drain)
Output Enable
0
CTL0 FLOWEQxCTL.0 GPIFCTLCFG.0
N/A
(CTL Outputs are always
enabled when TRICTL = 0)
CTL1 FLOWEQxCTL.1 GPIFCTLCFG.0
CTL2 FLOWEQxCTL.2 GPIFCTLCFG.0
CTL3 FLOWEQxCTL.3 GPIFCTLCFG.0
CTL4 FLOWEQxCTL.4 GPIFCTLCFG.0
CTL5 FLOWEQxCTL.5 GPIFCTLCFG.0
1
CTL0 FLOWEQxCTL.0 N/A
(CTL Outputs are always
tri-statable
CMOS when TRICTL = 1)
FLOWEQxCTL.4
CTL1 FLOWEQxCTL.1 FLOWEQxCTL.5
CTL2 FLOWEQxCTL.2 FLOWEQxCTL.6
CTL3 FLOWEQxCTL.3 FLOWEQxCTL.7
CTL4 N/A
(CTL4 and CTL5 are not available when TRICTL = 1)
CTL5
344 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
FLOWSTB
E6CB
15.13.10 FLOWSTB
GPIF Flow Master Strobe Register
Based on suggested FLOW_LOGIC settings.
This register defines the Master strobe that causes data to be read or written during a flow state.
For transactions where GPIF is the slave on the bus, the Master strobe is one of the RDY[5:0] pins. This includes external
masters that can either write data into GPIF (for example, UDMA IN) or read data out of GPIF.
For transactions where GPIF is the master on the bus, the Master strobe is one of the CTL[5:0] pins. This includes cases
where the GPIF writes data out to a slave (for example, UDMA OUT) or reads data from a slave.
7SLAVE 0 GPIF is the master of the bus transaction. This means that one of the CTL[5:0] pins is the
Master strobe and the particular one is selected by MSTB[2:0].
1 GPIF is the slave of the bus transaction. This means that one of the RDY[5:0] pins is the
Master strobe and the particular one is selected by MSTB[2:0].
6 RDYASYNC If SLAVE is ‘0’ then this bit is ignored, otherwise:
0 Master strobe (which is a RDY pin in this case) is synchronous to IFCLK.
1 Master strobe (which is a RDY pin in this case) is asynchronous to IFCLK.
5 CTLTOGL If SLAVE is ‘1’ then this bit is ignored. Otherwise, this bit defines which state of the flow logic (see
FLOWLOGIC) causes Master strobe (which is a CTL pin in this case) to toggle. For example, if this bit
is set to ‘1’, then if the output of the flow logic equals ‘1’ then Master strobe toggles causing data to
flow on the bus. If in the same example the output of the flow logic equals ‘0’ then Master strobe
freezes causing data flow to halt on the bus.
4SUSTAIN If SLAVE is ‘1’ then this bit is ignored. Upon exiting a flow state in which SLAVE is ‘0’, Master strobe
(which is a CTL pin in this case) normally goes back to adhering to the CTL opcodes defined in the
waveform descriptor.
2:0 MSTB[2:0] If SLAVE is ‘0’ then these bits select which CTL[5:0] pin is the Master strobe. If SLAVE is ‘1’ then
these bits select which RDY[5:0] pin is the Master strobe.
FLOWSTB E6CB
b7 b6 b5 b4 b3 b2 b1 b0
SLAVE RDYASYNC CTLTOGL SUSTAIN 0 MSTB[2:0]
RW RW RW RW RRW RW RW
00100000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 345
FLOWHOLDOFF
E6CA
15.13.11 FLOWHOLDOFF
GPIF Flow Holdoff Register
For flow state transactions that meet the following criteria:
1. The interface is asynchronous.
1. GPIF is acting like a slave (FLOWSTB.SLAVE = 1), and thus Master strobe is a RDY pin.
2. Data is being written into the GPIF.
3. The rate at which data is being written in exceeds 96 MB/s for a word wide data bus or 48 MB/s for a byte wide data bus.
7:4 HOPERIOD[3:0] Defines how many IFCLK cycles to assert not ready (HOCTL) to the external master in order to allow
the synchronization interface to catch up.
3HOSTATE Defines what the state of the HOCTL signal should be in to assert not ready.
2:0 HOCTL[2:0] Defines which of the six CTL[5:0] pins is the HOCTL signal that asserts not ready to the external mas-
ter when the synchronization detects a potential overflow coming. It should coincide with the CTL[5:0]
pin that is picked as the ‘not ready’ signal for the (macro-level) endpoint FIFO overflow protection.
FLOWHOLDOFF E6CA
b7 b6 b5 b4 b3 b2 b1 b0
HOPERIOD[3:0] HOSTATE HOCTL[2:0]
RW RW RW RW RW RW RW RW
00010010
Bit Name Description
346 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
FLOWSTBEDGE
E6CC
15.13.12 FLOWSTBEDGE
GPIF Flow Master Strobe Edge Register
This register defines whether the Master strobe (see FLOWSTB) causes data to read or write on the falling edge, the rising
edge, or both (double edge).
1FALLING 0 Data is not transferred on the falling edge of Master strobe
1 Data is transferred on the falling edge of Master strobe
0 RISING 0 Data is not transferred on the rising edge of Master strobe
1 Data is transferred on the rising edge of Master strobe
To cause data to transfer on both edges of Master strobe, set both bits to ‘1’.
FLOWSTBEDGE E6CC
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 FALLING RISING
R R R R R R R/W RW
00000001
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 347
FLOWSTBHPERIOD
E6CD
15.13.13 FLOWSTBHPERIOD
GPIF Flow Master Strobe Half Period Register
If the flow state is such that the GPIF is the master on the bus (FLOWSTB.SLAVE = 0) then Master strobe is one of the
CTL[5:0] pins (see FLOWSTB). While in the flow state, if the flow logic (see FLOWLOGIC) evaluates in such a way that Mas-
ter strobe toggles (see FLOWSTB.CTLTOGL), then this register defines the frequency at which it toggles.
More precisely, this register defines the half period of the Master strobe toggling frequency. Furthermore, to give the user a
high degree of resolution this Master strobe, half period is defined in terms of half IFCLK periods. Therefore, if IFCLK is run-
ning at 48 MHz, this gives a resolution of 10.4 ns.
7:0 D[7:0] Master Strobe Half-Period.
Number of half IFCLK periods that define the half period of Master strobe (if it is a CTL pin). The value
must be at least ‘2’, meaning that the minimum half period for Master strobe is one full IFCLK cycle.
FLOWSTBHPERIOD E6CD
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
RW RW RW RW RW RW RW RW
00000010
Bit Name Description
348 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
GPIFHOLDAMOUNT
E60C
15.13.14 GPIFHOLDAMOUNT
GPIF Hold Amount Register
For any transaction where the GPIF writes data onto FD[15:0], this register determines how long the data is held. Valid
choices are 0, ½ or 1 IFCLK cycle. This register applies to any data written by the GPIF to FD[15:0], whether through a flow
state or not.
For non-flow states, the hold amount is really just a delay of the normal (non-held) presentation of FD[15:0] by the amount
specified in HOLDTIME[1:0].
For flow states in which the GPIF is the master on the bus (FLOWSTB.SLAVE = 0), the hold amount is with respect to the
activating edge (see FLOW_MASTERSTB_EDGE) of Master strobe (which is a CTL pin in this case).
For flow states in which the GPIF is the slave on the bus (FLOWSTB.SLAVE = 1), the hold amount is really just a delay of the
normal (non-held) presentation of FD[15:0] by the amount specified in HOLDTIME[1:0] in reaction to the activating edge of
Master strobe (which is a RDY pin in this case). Note that the hold amount is NOT ‘directly with respect to’ the activating edge
of Master strobe in this case; it is with respect to when the data normally comes out in response to Master strobe including
any latency to synchronize Master strobe.
In all cases, the data is held for the desired amount even if the ensuing GPIF state calls for the data bus to be tri-stated. In
other words the FD[15:0] output enable is held by the same amount as the data itself.
1:0 HOLDTIME[1:0] GPIF Hold Time.
00 0 IFCLK cycles
01 ½ IFCLK cycle
10 1 IFCLK cycle
11 Reserved
GPIFHOLDAMOUNT E60C
b7 b6 b5 b4 b3 b2 b1 b0
000000 HOLDTIME[1:0]
R R R R R R RW RW
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 349
GPIFTCBx
E6CE
15.13.15 GPIFTCBx
GPIF Transaction Count Byte Registers
31:0 TC31:0 GPIF Transaction Count.
Note Registers GPIFTCB3, GPIFTCB2, GPIFTCB1, and GPIFTCB0 represent the live update of GPIF transactions.
GPIFTCB3
see Section 15.15 GPIF Transaction Count Byte 3 E6CE
b7 b6 b5 b4 b3 b2 b1 b0
TC31 TC30 TC29 TC28 TC27 TC26 TC25 TC24
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
GPIFTCB2
see Section 15.15 GPIF Transaction Count Byte 2 E6CF
b7 b6 b5 b4 b3 b2 b1 b0
TC23 TC22 TC21 TC20 TC19 TC18 TC17 TC16
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
GPIFTCB1
see Section 15.15 GPIF Transaction Count Byte 1 E6D0
b7 b6 b5 b4 b3 b2 b1 b0
TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
GPIFTCB0
see Section 15.15 GPIF Transaction Count Byte 0 E6D1
b7 b6 b5 b4 b3 b2 b1 b0
TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0
R/W R/W R/W R/W R/W R/W R/W R/W
00000001
Bit Name Description
350 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EPxGPIFFLGSEL
E6D2
15.13.16 EPxGPIFFLGSEL
Endpoint 2, 4, 6, 8 GPIF Flag Select Registers
1:0 FS[1:0] GPIF Flag Select.
00 Programmable
01 Empty
10 Full
11 Reserved
Only one FIFO flag at a time may be made available to the GPIF as a control input. The FS1:FS0 bits
select which flag is made available.
EP2GPIFFLGSEL
see Section 15.15 Endpoint 2 GPIF Flag Select E6D2
EP4GPIFFLGSEL
see Section 15.15 Endpoint 4 GPIF Flag Select E6DA
EP6GPIFFLGSEL
see Section 15.15 Endpoint 6 GPIF Flag Select E6E2
EP8GPIFFLGSEL
see Section 15.15 Endpoint 8 GPIF Flag Select E6EA
b7 b6 b5 b4 b3 b2 b1 b0
000000FS1FS0
R/W R/W R/W R/W R/W R/W R/W R/W
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 351
EPxGPIFPFSTOP
E6D3
15.13.17 EPxGPIFPFSTOP
Endpoint 2, 4, 6, and 8 GPIF Stop Transaction Registers
0 EP[2,4,6,8]PF Stop on Endpoint Programmable Flag.
1 GPIF transitions to ‘DONE’ state when the flag selected by EPxGPIFFLGSEL is asserted.
0 When transaction count has been met.
EP2GPIFPFSTOP Endpoint 2 GPIF Stop Transaction E6D3
EP4GPIFPFSTOP Endpoint 4 GPIF Stop Transaction E6DB
EP6GPIFPFSTOP Endpoint 6 GPIF Stop Transaction E6E3
EP8GPIFPFSTOP Endpoint 8 GPIF Stop Transaction E6EB
b7 b6 b5 b4 b3 b2 b1 b0
0000000FIFO[2,4,6,8]FLAG
R/W R/W R/W R/W R/W R/W R/W R/W
0000000 0
Bit Name Description
352 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EPxGPIFTRIG
E6D4
15.13.18 EPxGPIFTRIG
Endpoint 2, 4, 6, and 8 Slave FIFO GPIF Trigger Registers
Write 0xFF to this register to initiate a GPIF write. Read from this register to initiate a GPIF read.
EP2GPIFTRIG
see Section 15.15 Endpoint 2 Slave FIFO GPIF Trigger E6D4
EP4GPIFTRIG
see Section 15.15 Endpoint 4 Slave FIFO GPIF Trigger E6DC
EP6GPIFTRIG
see Section 15.15 Endpoint 6 Slave FIFO GPIF Trigger E6E4
EP8GPIFTRIG
see Section 15.15 Endpoint 8 Slave FIFO GPIF Trigger E6EC
b7 b6 b5 b4 b3 b2 b1 b0
xxxxxxxx
W W W W W W W W
x x x x x x x x
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 353
XGPIFSGLDATH
E6F0
15.13.19 XGPIFSGLDATH
GPIF Data High (16 Bit Mode) Register
7:0 D[15:8] GPIF Data High.
Contains the data written to or read from the FD[15:8] (PORTD) pins using the GPIF waveform.
XGPIFSGLDATH GPIF Data HIGH (16 Bit Mode) E6F0
b7 b6 b5 b4 b3 b2 b1 b0
D15 D14 D13 D12 D11 D10 D9 D8
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
Bit Name Description
354 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
XGPIFSGLDATL
E6F1
15.13.20 XGPIFSGLDATL
Read/Write GPIF Data Low and Trigger Transaction Register
7:0 D[7:0] GPIF Data Low /Trigger GPIF Transaction.
Contains the data written to or read from the FD[7:0] (PORTB) pins. Reading or writing low-byte trig-
gers a GPIF transaction.
XGPIFSGLDATLX Read/Write GPIF Data Low and Trigger Transaction E6F1
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
x x x x x x x x
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 355
XGPIFSGLDATLNOX
E6F2
15.13.21 XGPIFSGLDATLNOX
Read GPIF Data Low, No Transaction Trigger Register
7:0 D[7:0] GPIF Data Low / Do Not Trigger GPIF Transaction.
Contains the data written to or read from the FD[7:0] (PORTB) pins. Read or write low byte does not
trigger GPIF transaction.
XGPIFSGLDATLNOX Read GPIF Data Low, No Transaction Trigger E6F2
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R R R R R R R R
x x x x x x x x
Bit Name Description
356 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
GPIFREADYCFG
E6F3
15.13.22 GPIFREADYCFG
GPIF RDY Pin Configuration Register
7INTRDY Force Ready Condition.
Internal RDY. Functions as a sixth RDY input, controlled by the firmware instead of a RDY pin.
6SAS RDY Signal Connection to GPIF Input Logic.
Synchronous/Asynchronous RDY signals. This bit controls how the RDY signals connect to the GPIF
input logic.
If the internal IFCLK is used to clock the GPIF, the RDY signals can make transitions in an asynchro-
nous manner, i.e. not referenced to the internal clock. Setting SAS=0 causes the RDY inputs to pass
through two flip-flops for synchronization purposes.
If the RDY signals are synchronized to IFCLK, and obey the setup and hold times with respect to this
clock, the user can set SAS=1, which causes the RDY signals to pass through a single flip flop.
5TCXRDY5 TC Expiration Replaces RDY5.
To use the transaction count expiration signal as a ready input to a waveform, set this bit to ‘1’. Set-
ting this bit takes the place of the pin RDY5 in the decision point of the waveform. The default value of
the bit is zero (in other words, the RDY5 from the pin prevails).
GPIFREADYCFG GPIF RDY Pin Configuration E6F3
b7 b6 b5 b4 b3 b2 b1 b0
INTRDY SAS TCXRDY5 0 0 0 0 0
R/W R/W R/W R R R R R
00000000
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 357
GPIFREADYSTAT
E6F4
15.13.23 GPIFREADYSTAT
GPIF RDY Pin Status Register
Bit 5-0 RDY5:0 Current State of Ready Pins.
RDYx. Instantaneous states of the RDY pins. The current state of the RDY[5:0] pins, sampled at each
rising edge of the GPIF clock.
GPIFREADYSTAT GPIF RDY Pin Status E6F4
b7 b6 b5 b4 b3 b2 b1 b0
0 0 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0
R R R R R R R R
0 0 x x x x x x
Bit Name Description
358 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
GPIFABORT
E6F4
15.13.24 GPIFABORT
Abort GPIF Cycles Register
Write 0xFF to immediately abort a GPIF transaction and transition to the Idle State.
GPIFABORT Abort GPIF E6F5
b7 b6 b5 b4 b3 b2 b1 b0
xxxxxxxx
W W W W W W W W
x x x x x x x x
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 359
EP0BUF
E740-
15.14 Endpoint Buffers
15.14.1 EP0BUF
EP0 IN-OUT Buffer Register
7:0 D[7:0] EP0 Data.
EP0 Data buffer (IN/OUT). 64 bytes.
EP0BUF EP0 IN/OUT Buffer E740-E77F
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
X X X X X X X X
Bit Name Description
360 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP1OUTBUF
E780-
15.14.2 EP1OUTBUF
Endpoint 1-OUT Buffer Register
7:0 D[7:0] EP1-Out Data.
EP1-Out Data buffer. 64 bytes.
EP1OUTBUF EP1-OUT Buffer E780-E7BF
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
X X X X X X X X
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 361
EP1INBUF
E7C0-
15.14.3 EP1INBUF
Endpoint 1-IN Buffer Register
7:0 D[7:0] EP1-IN Buffer.
EP1-IN Data buffer. 64 bytes.
EP1INBUF EP1-IN Buffer E7C0-E7FF
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
X X X X X X X X
Bit Name Description
362 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP2FIFOBUF
F000-
15.14.4 EP2FIFOBUF
Endpoint 2/Slave FIFO Buffer Register
7:0 D[7:]0 EP2 Data.
512/1024-byte EP2 buffer.
EP2FIFOBUF 512/1024-byte EP2/Slave FIFO Buffer F000-F3FF
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
X X X X X X X X
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 363
EP4FIFOBUF
F400-
15.14.5 EP4FIFOBUF
512-byte Endpoint 4/Slave FIFO Buffer Register
7:0 D[7:0] EP4 Data.
512 byte EP4 buffer.
EP4FIFOBUF 512-byte EP4/Slave FIFO Buffer F400-F5FF
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
X X X X X X X X
Bit Name Description
364 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
EP6FIFOBUF
F800-
15.14.6 EP6FIFOBUF
512/1024-byte Endpoint 6/Slave FIFO Buffer Register
7:0 D[7:0] EP6 Data.
512/1024 byte EP6 buffer.
EP6FIFOBUF 512/1024-byte EP6/Slave FIFO Buffer F800-FBFF
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
X X X X X X X X
Bit Name Description
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 365
EP8FIFOBUF
FC00-
15.14.7 EP8FIFOBUF
512-byte Endpoint 8/Slave FIFO Buffer Register
7:0 D[7:0] EP8 Data.
512 byte EP8 buffer.
EP8FIFOBUF 512-byte EP8/Slave FIFO Buffer FC00-FDFF
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
X X X X X X X X
Bit Name Description
366 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Registers
15.15 Synchronization Delay
Under certain conditions, some read and write accesses to EZ-USB registers must be separated by a synchronization delay.
The delay is necessary only under the following conditions:
■Between a write to any register in the 0xE600-0xE6FF range and a write to one of the registers in Table 15-6.
■Between a write to one of the registers in Table 15-6 and a read from any register in the 0xE600-0xE6FF range.
The minimum delay length is a function of the IFCLK and CLKOUT (CPU Clock) frequencies, and is determined by the equa-
tion:
Equation 1
The required delay length is smallest when the CPU is running at its slowest speed (12 MHz, 83.2 ns/cycle) and IFCLK is run-
ning at its fastest speed (48 MHz, 20.8 ns/cycle). Under those conditions, the minimum required delay is:
Equation 2
The longest delay is required when the CPU is running at its fastest speed (48MHz, 20.8 ns/cycle) and IFCLK is running
much slower (e.g., 5.2 MHz, 192 ns/cycle):
Equation 3
The most typical EZ-USB configuration, IFCLK and CLKOUT both running at 48 MHz, requires a minimum delay of:
:Equation 4
The Frameworks firmware supplied with the EZ-USB Development Kit includes a macro, called SYNCDELAY, which imple-
ments the synchronization delay. The macro is in the file fx2sdly.h.
These delay cycles are in addition to the two clocks used by the MOVX instruction.
Table 15-6. Registers that Require a Synchronization Delay:
FIFORESET FIFOPINPOLAR ECCCFG
INPKTEND EPxBCH:L ECCRESET
EPxFIFOPFH:L EPxAUTOINLENH:L ECC1B0
EPxFIFOCFG EPxGPIFFLGSEL ECC1B1
PINFLAGSAB PINFLAGSCD ECC1B2
EPxFIFOIE EPxFIFOIRQ ECC2B0
GPIFIE GPIFIRQ ECC2B1
UDMACRCH:L GPIFADRH:L ECC2B2
GPIFTRIG EPxGPIFTRIG
OUTPKTEND REVCTL
GPIFTCB3 GPIFTCB2
GPIFTCB1 GPIFTCB0
Minimum Sync Delay, in CPU cycles 1.5 IFCLK Period
CLKOUT Period
----------------------------------------- 1+


=Note
n means “round n upward”
1.5 20.8
83.2
---------- 1+


1.5 1.251.875 2 CPU Cycles===
1.5 192
20.8
---------- 1+


1.5 10.2315.3 16 CPU Cycles===
1.5 20.8
20.8
---------- 1+


1.5 23 3 CPU Cycles===
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 367
Appendix A. Descriptors for Full-
Speed Mode
Table A-1 through Table A-25 show the descriptor data built into the EZ-USB logic. The tables are presented in the order that
the bytes are stored.
The Device Descriptor specifies a MaxPacketSize of 64 bytes for endpoint 0, contains Cypress Semiconductor Vendor, Prod-
uct and Release Number IDs, and uses no string indices. Release Number IDs (XX and YY) are found in individual Cypress
Semiconductor data sheets. The EZ-USB logic returns this information response to a Get_Descriptor/Device host request.
Table A-1. Default USB Device Descriptor
Offset Field Description Value
0bLength Length of this Descriptor = 18 bytes 12h
1bDescriptorType Descriptor Type = Device 01h
2bcdUSB (L) USB Specification Version 2.00 (L) 00h
3bcdUSB (H) USB Specification Version 2.00 (H) 02h
4bDeviceClass Device Class (FF is Vendor Specific) FFh
5bDeviceSubClass Device Sub-class (FF is Vendor Specific) FFh
6bDeviceProtocol Device Protocol (FF is Vendor Specific) FFh
7bMaxPacketSize0 Maximum Packet Size for EP0 = 64 bytes 40h
8idVendor (L) Vendor ID (L) Cypress Semi = 04B4H B4h
9idVendor (H) Vendor ID (H) 04h
10 idProduct (L) Product ID (L) FX2LP = 8613H, FX1 = 6473H 13h
11 idProduct (H) Product ID (H) 86h
12 bcdDevice (L) Device Release Number (BCD,L) (see individual data sheet) xxh
13 bcdDevice (H) Device Release Number (BCD,H) (see individual data sheet) xxh
14 iManufacturer Manufacturer Index String = None 00h
15 iProduct Product Index String = None 00h
16 iSerialNumber Serial number Index String = None 00h
17 bNumConfigurations Number of Configurations in this Interface = 1 01h
368 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Descriptors for Full-Speed Mode
The configuration descriptor includes a total length field (offset 2-3) that encompasses all interface and endpoint descriptors
that follow the configuration descriptor. This configuration describes a single interface (offset 4). The host selects this configu-
ration by issuing a Set_Configuration requests specifying configuration #1 (offset 5).
Table A-2. Device Qualifier
Offset Field Description Value
0bLength Length of this Descriptor = 10 bytes 0Ah
1bDescriptorType Descriptor Type = Device Qualifier 06h
2bcdUSB (L) USB Specification Version 2.00 (L) 00h
3bcdUSB (H) USB Specification Version 2.00 (H) 02h
4bDeviceClass Device Class (FF is Vendor Specific) FFh
5bDeviceSubClass Device Sub-class (FF is Vendor Specific) FFh
6bDeviceProtocol Device Protocol (FF is Vendor Specific) FFh
7bMaxPacketSize0 Maximum Packet Size for other speed = 64 bytes 40h
8bNumConfigurations Number of other Configurations = 1 01h
9bReserved Must be set to zero 00h
Table A-3. USB Default Configuration Descriptor
Offset Field Description Value
0 bLength Length of this Descriptor = 9 bytes 09h
1 bDescriptorType Descriptor Type = Configuration 02h
2 wTotalLength (L) Total Length (L) Including Interface and Endpoint Descriptors (171 total) ABh
3 wTotalLength (H) Total Length (H) 00h
4 bNumInterfaces Number of Interfaces in this Configuration 01h
5 bConfigurationValue Configuration Value Used by Set_Configuration Request to Select this interface 01h
6 iConfiguration Index of String Describing this Configuration = None 00h
7 bmAttributes Attributes - Bus Powered, No Wakeup 80h
8 MaxPower Maximum Power - 100 mA 32h
Table A-4. USB Default Interface 0, Alternate Setting 0
Offset Field Description Value
0bLength Length of the Interface Descriptor 09h
1bDescriptorType Descriptor Type = Interface 04h
2bInterfaceNumber Zero based index of this interface = 0 00h
3bAlternateSetting Alternate Setting Value = 0 00h
4bNumEndpoints Number of endpoints in this interface (not counting EP0) = 0 00h
5bInterfaceClass Interface Class = Vendor Specific FFh
6bInterfaceSubClass Interface Sub-class = Vendor Specific FFh
7bInterfaceProtocol Interface Protocol = Vendor Specific FFh
8iInterface Index to string descriptor for this interface = None 00h
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Descriptors for Full-Speed Mode
Table A-5. USB Default Interface 0, Alternate Setting 1
Offset Field Description Value
0bLength Length of this Interface Descriptor 09h
1bDescriptorType Descriptor Type = Interface 04h
2bInterfaceNumber Zero based index of this interface = 0 00h
3bAlternateSetting Alternate Setting Value = 1 01h
4bNumEndpoints Number of endpoints in this interface (not counting EP0) = 6 06h
5bInterfaceClass Interface Class = Vendor Specific FFh
6bInterfaceSubClass Interface Sub-class = Vendor Specific FFh
7bInterfaceProtocol Interface Protocol = Vendor Specific FFh
8iInterface Index to string descriptor for this interface = None 00h
Table A-6. Endpoint Descriptor (EP1 out)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint direction (1 is in) and address = OUT1 01h
3bmAttributes XFR Type = Bulk 02h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for ISO) 00h
Table A-7. Endpoint Descriptor (EP1 in)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN1 81h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
Table A-8. Endpoint Descriptor (EP2)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT2 02h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
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Descriptors for Full-Speed Mode
Table A-9. Endpoint Descriptor (EP4)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT4 04h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
Table A-10. Endpoint Descriptor (EP6)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN6 86h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
Table A-11. Endpoint Descriptor (EP8)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN8 88h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
Table A-12. Interface Descriptor (Alt. Setting 2)
Offset Field Description Value
0bLength Length of the Interface Descriptor 09h
1bDescriptorType Descriptor Type = Interface 04h
2bInterfaceNumber Zero based index of this interface = 0 00h
3bAlternateSetting Alternate Setting Value = 2 02h
4bNumEndpoints Number of endpoints in this interface (not counting EP0) = 6 06h
5bInterfaceClass Interface Class = Vendor Specific FFh
6bInterfaceSubClass Interface Sub-class = Vendor Specific FFh
7bInterfaceProtocol Interface Protocol = Vendor Specific FFh
8iInterface Index to string descriptor for this interface = None 00h
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Descriptors for Full-Speed Mode
Table A-13. Endpoint Descriptor (EP1 out)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT1 01h
3bmAttributes XFR Type = INT 03h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 0Ah
Table A-14. Endpoint Descriptor (EP1 in)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN1 81h
3bmAttributes XFR Type = INT 03h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 0Ah
Table A-15. Endpoint Descriptor (EP2)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT2 02h
3bmAttributes XFR Type = INT 03h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 0Ah
Table A-16. Endpoint Descriptor (EP4)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT4 04h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
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Descriptors for Full-Speed Mode
Table A-17. Endpoint Descriptor (EP6)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN6 86h
3bmAttributes XFR Type = INT 03h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 0Ah
Table A-18. Endpoint Descriptor (EP8)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN8 88h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
Table A-19. Interface Descriptor (Alt. Setting 3)
Offset Field Description Value
0bLength Length of the Interface Descriptor 09h
1bDescriptorType Descriptor Type = Interface 04h
2bInterfaceNumber Zero based index of this interface = 0 00h
3bAlternateSetting Alternate Setting Value = 3 03h
4bNumEndpoints Number of endpoints in this interface (not counting EP0) = 6 06h
5bInterfaceClass Interface Class = Vendor Specific FFh
6bInterfaceSubClass Interface Sub-class = Vendor Specific FFh
7bInterfaceProtocol Interface Protocol = Vendor Specific FFh
8iInterface Index to string descriptor for this interface = None 00h
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Descriptors for Full-Speed Mode
Table A-20. Endpoint Descriptor (EP1 out)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT1 01h
3bmAttributes XFR Type = INT 03h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 0Ah
Table A-21. Endpoint Descriptor (EP1 in)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN1 81h
3bmAttributes XFR Type = INT 03h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 0Ah
Table A-22. Endpoint Descriptor (EP2)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT2 02h
3bmAttributes XFR Type = ISO, No Synchronization, Data endpoint 01h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 01h
Table A-23. Endpoint Descriptor (EP4)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT4 04h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
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Descriptors for Full-Speed Mode
Table A-24. Endpoint Descriptor (EP6)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN6 86h
3bmAttributes XFR Type = ISO, No Synchronization, Data Endpoint 01h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 01h
Table A-25. Endpoint Descriptor (EP8)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN8 88h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 375
Appendix B. Descriptors for High-
Speed Mode
Table B-1 through Table B-25 show the descriptor data built into the FX2LP logic. The tables are presented in the order that
the bytes are stored.
The Device Descriptor specifies a MaxPacketSize of 64 bytes for endpoint 0, contains Cypress Semiconductor Vendor, Prod-
uct and Release Number IDs, and uses no string indices. Release Number IDs (XX and YY) are found in individual Cypress
Semiconductor data sheets. The FX2LP logic returns this information response to a Get_Descriptor/Device host request.
Table B-1. Device Descriptor
Offset Field Description Value
0bLength Length of this Descriptor = 18 bytes 12h
1bDescriptorType Descriptor Type = Device 01h
2bcdUSB (L) USB Specification Version 2.00 (L) 00h
3bcdUSB (H) USB Specification Version 2.00 (H) 02h
4bDeviceClass Device Class (FF is Vendor-Specific) FFh
5bDeviceSubClass Device Sub-class (FF is Vendor-Specific) FFh
6bDeviceProtocol Device Protocol (FF is Vendor-Specific) FFh
7bMaxPacketSize0 Maximum Packet Size for EP0 = 63 bytes 40h
8idVendor (L) Vendor ID (L) Cypress Semi = 04B4H B4h
9idVendor (H) Vendor ID (H) 04h
10 idProduct (L) Product ID (L) FX2LP = 8613H 13h
11 idProduct (H) Product ID (H) 86h
12 bcdDevice (L) Device Release Number (BCD,L) (see individual data sheet) xxh
13 bcdDevice (H) Device Release Number (BCD,H) (see individual data sheet) xxh
14 iManufacturer Manufacturer Index String = None 00h
15 iProduct Product Index String = None 00h
16 iSerialNumber Serial Number Index String = None 00h
17 bNumConfigurations Number of Configurations in this Interface = 1 01h
Table B-2. Device Qualifier
Offset Field Description Value
0bLength Length of this Descriptor = 10 bytes 0Ah
1bDescriptorType Descriptor Type = Device Qualifier 06h
2bcdUSB (L) USB Specification Version 2.00 (L) 00h
3bcdUSB (H) USB Specification Version 2.00 (H) 02h
4bDeviceClass Device Class (FF is vendor specific) FFh
5bDeviceSubClass Device Sub-class (FF is vendor specific) FFh
6bDeviceProtocol Device Protocol (FF is vendor specific) FFh
7bMaxPacketSize0 Maximum Packet Size for other speed = 64 bytes 40h
8bNumConfigurations Number of other Configurations = 1 01h
9bReserved Must be set to Zero 00h
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Descriptors for High-Speed Mode
Table B-3. Configuration Descriptor
Offset Field Description Value
0bLength Length of this Descriptor = 9 bytes 09h
1bDescriptorType Descriptor Type = Configuration 02h
2wTotalLength (L) Total length (L) including Interface and Endpoint descriptors (171 total) ABh
3wTotalLength (H) Total Length (H) 00h
4bNumInterfaces Number of Interfaces in this Configuration 01h
5bConfigurationValue Configuration value used by Set_Configuration Request to select this interface 01h
6iConfiguration Index of String Describing this Configuration = None 00h
7bmAttributes Attributes - Bus Powered, No Wakeup 80h
8MaxPower Maximum Power - 100 mA 32h
Table B-4. Interface Descriptor (Alt. Setting 0)
Offset Field Description Value
0bLength Length of the Interface Descriptor 09h
1bDescriptorType Descriptor Type = Interface 04h
2bInterfaceNumber Zero based index of this interface = 0 00h
3bAlternateSetting Alternate Setting Value = 0 00h
4bNumEndpoints Number of endpoints in this interface (not counting EP0) = 0 00h
5bInterfaceClass Interface Class = Vendor Specific FFh
6bInterfaceSubClass Interface Sub-class = Vendor Specific FFh
7bInterfaceProtocol Interface Protocol = Vendor Specific FFh
8iInterface Index to string descriptor for this interface = None 00h
Table B-5. Interface Descriptor (Alt. Setting 1)
Offset Field Description Value
0bLength Length of the Interface Descriptor 09h
1bDescriptorType Descriptor Type = Interface 04h
2bInterfaceNumber Zero based index of this interface = 0 00h
3bAlternateSetting Alternate Setting Value = 1 01h
4bNumEndpoints Number of endpoints in this interface (not counting EP0) = 6 06h
5bInterfaceClass Interface Class = Vendor Specific FFh
6bInterfaceSubClass Interface Sub-class = Vendor Specific FFh
7bInterfaceProtocol Interface Protocol = Vendor Specific FFh
8iInterface Index to string descriptor for this interface = None 00h
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Descriptors for High-Speed Mode
Table B-6. Endpoint Descriptor (EP1 out)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT1 01h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
Table B-7. Endpoint Descriptor (EP1 in)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN1 81h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
Table B-8. Endpoint Descriptor (EP2)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT2 02h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
Table B-9. Endpoint Descriptor (EP4)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT4 04h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
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Descriptors for High-Speed Mode
Table B-10. Endpoint Descriptor (EP6)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN6 86h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
Table B-11. Endpoint Descriptor (EP8)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN8 88h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
Table B-12. Interface Descriptor (Alt. Setting 2)
Offset Field Description Value
0bLength Length of the Interface Descriptor 09h
1bDescriptorType Descriptor Type = Interface 04h
2bInterfaceNumber Zero based index of this interface = 0 00h
3bAlternateSetting Alternate Setting Value = 2 02h
4bNumEndpoints Number of endpoints in this interface (not counting EP0) = 6 06h
5bInterfaceClass Interface Class = Vendor Specific FFh
6bInterfaceSubClass Interface Sub-class = Vendor Specific FFh
7bInterfaceProtocol Interface Protocol = Vendor Specific FFh
8iInterface Index to string descriptor for this interface = None 00h
Table B-13. Endpoint Descriptor (EP1 out)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT1 01h
3bmAttributes XFR Type = INT 03h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 01h
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Descriptors for High-Speed Mode
Table B-14. Endpoint Descriptor (EP1 in)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN1 81h
3bmAttributes XFR Type = INT 03h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 01h
Table B-15. Endpoint Descriptor (EP2)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT2 02h
3bmAttributes XFR Type = INT 03h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 01h
Table B-16. Endpoint Descriptor (EP4)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT4 04h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
Table B-17. Endpoint Descriptor (EP6)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN6 86h
3bmAttributes XFR Type = INT 03h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 01h
380 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Descriptors for High-Speed Mode
Table B-18. Endpoint Descriptor (EP8)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN8 88h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
Table B-19. Interface Descriptor (Alt. Setting 3)
Offset Field Description Value
0bLength Length of the Interface Descriptor 09h
1bDescriptorType Descriptor Type = Interface 04h
2bInterfaceNumber Zero based index of this interface = 0 00h
3bAlternateSetting Alternate Setting Value = 3 03h
4bNumEndpoints Number of endpoints in this interface (not counting EP0) = 6 06h
5bInterfaceClass Interface Class = Vendor Specific FFh
6bInterfaceSubClass Interface Sub-class = Vendor Specific FFh
7bInterfaceProtocol Interface Protocol = Vendor Specific FFh
8iInterface Index to string descriptor for this interface = None 00h
Table B-20. Endpoint Descriptor (EP1 out)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT1 01h
3bmAttributes XFR Type = INT 03h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 01h
Table B-21. Endpoint Descriptor (EP1 in)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN1 81h
3bmAttributes XFR Type = INT 03h
4wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40h
5WMaxPacketSize (H) Maximum Packet Size - High 00h
6bInterval Polling Interval in Milliseconds (1 for iso) 01h
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 381
Descriptors for High-Speed Mode
Table B-22. Endpoint Descriptor (EP2)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT2 02h
3bmAttributes XFR Type = ISO, No Synchronization, Data endpoint 01h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 01h
Table B-23. Endpoint Descriptor (EP4)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = OUT4 04h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
Table B-24. Endpoint Descriptor (EP6)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN6 86h
3bmAttributes XFR Type = ISO, No Synchronization, Data endpoint 01h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 01h
Table B-25. Endpoint Descriptor (EP8)
Offset Field Description Value
0bLength Length of this Endpoint Descriptor 07h
1bDescriptorType Descriptor Type = Endpoint 05h
2bEndpointAddress Endpoint Direction (1 is in) and address = IN8 88h
3bmAttributes XFR Type = BULK 02h
4wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00h
5WMaxPacketSize (H) Maximum Packet Size - High 02h
6bInterval Polling Interval in Milliseconds (1 for iso) 00h
382 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Descriptors for High-Speed Mode
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 383
Appendix C. Device Register
Summary
The following table is a summary of all the device registers.
In the ‘b7-b0’ columns, bit positions that contain a ‘0’ or a ‘1’ cannot be written to and, when read, always return the value
shown (‘0’ or ‘1’). Bit positions that contain ‘-’ are available but unused.
The ‘Default’ column shows each register’s hard reset value (‘x’ indicates ‘undefined’).
The ‘Access’ column indicates each register’s read or write, or both accessibility.
384 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Device Register Summary
Register Summary
Table C-1. EZ-USB® Registers and Buffers
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access Notes
GPIF Waveform Memories
E400 128 WAVEDATA GPIF Waveform Descriptor 0, 1, 2, 3 data D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW Associated / pointed to by
GPIFWFSELECT
E480 128 reserved
GENERAL CONFIGURATION
E600 1CPUCS CPU Control and Status 0 0 PORTCSTB CLKSPD1 CLKSPD0 CLKINV CLKOE 8051RES 00000010 rrbbbbbr PORTCSTB=1: reads/writes to
PORTC generate RD# and WR#
strobes
CLKSPD1:0=8051 clock speed:
00=12, 01-24, 10=48, 11=X
CLKINV=1 to invert CLKOUT sig-
nal
CLKOE=1 to drive CLKOUT pin
8051RES=1 to reset 8051
E601 1IFCONFIG Interface Configuration (Ports, GPIF, slave
FIFOs) IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0 10000000 RW IFCLKSRC: FIFO/GPIF Clock
Source: 0:external (IFGCLK pin);
1:internal
3048MHZ: Internal FIFO/GPIF
clock freq: 0=30 MHz, 1=48 MHz
IFCLKOE: FIFO/GPIF Clock Out-
put Enable (on IFCLK pin)
IFCLKPOL: FIFO/GPIF clock po-
larity (on IFCLK pin)
ASYNC: 1=Slave FIFOs operate in
asynchronous mode;
0=Slave FIFOs operate in synchro-
nous mode
GSTATE: 1:drive GSTATE[0:2] on
PORTE[0:2]
IFCFG[1:0]: 00: ports;
01: reserved; 10: GPIF;
11: Slave FIFO (ext master)
E602 1PINFLAGSAB
see Section 15.15 Slave FIFO FLAGA and FLAGB Pin Config-
uration FLAGB3 FLAGB2 FLAGB1 FLAGB0 FLAGA3 FLAGA2 FLAGA1 FLAGA0 00000000 RW FLAGx[3:0] where
x = A,B,C or D FIFO Flag:
0000: PF for FIFO selected by FI-
FOADR[1:0] pins.
0001-0011: reserved
0100: EP2 PF, 0101: EP4PF, 0110:
EP6PF, 0111: EP8 PF
1000: EP2 EF, 1001: EP4EF, 1010:
EP6EF, 1011: EP8 EF
1100: EP2 FF, 1101: EP4FF, 1110:
EP6FF, 1111: EP8FF
E603 1PINFLAGSCD
see Section 15.15 Slave FIFO FLAGC and FLAGD Pin Con-
figuration FLAGD3 FLAGD2 FLAGD1 FLAGD0 FLAGC3 FLAGC2 FLAGC1 FLAGC0 00000000 RW
E604 1FIFORESET
see Section 15.15 Restore FIFOS to default state NAKALL 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx WSet flags and byte counts to default
values; write 0x80 to NAK all trans-
fers, then write NAKALL OR’ed with
FIFO number, then write 0x00 to re-
store normal operation
E605 1BREAKPT Breakpoint Control 0 0 0 0 BREAK BPPULSE BPEN 000000000 rrrrbbbr
E606 1BPADDRH Breakpoint Address H A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW
E607 1BPADDRL Breakpoint Address L A7 A6 A5 A4 A3 A2 A1 A0 xxxxxxxx RW
E608 1UART230 230K baud internally generated reference
clock 0 0 0 0 0 0 230UART1 230UART0 00000000 rrrrrrbb If ‘1’, overrides timer inputs to
UART. 230 rate valid for any CPU
clock rate.
E609 1FIFOPINPOLAR
see Section 15.15 Slave FIFO Interface pins polarity 0 0 PKTEND SLOE SLRD SLWR EF FF 00000000 rrbbbbbb 0=active low, 1=active high
E60A 1REVID Chip Revision rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 RevA
00000001 RChip revision number
E60B 1REVCTL Chip Revision Control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 rrrrrrbb
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 385
Device Register Summary
UDMA
E60C 1GPIFHOLDAMOUNT MSTB Hold Time (for UDMA) 0 0 0 0 0 0 HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
3reserved
ENDPOINT CONFIGURATION TYPE[00] = Illegal; 01=ISO,
10=BULK, 11=INT. dir=0:OUT;
dir=1:IN
BUF1:0: 00=quad, 01=illegal,
10=double, 11=triple
SIZE=0: 512 bytes, SIZE=1: 1024
bytes
E610 1EP1OUTCFG Endpoint 1-OUT Configuration VALID 0TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr Default: BULK OUT 64
E611 1EP1INCFG Endpoint 1-IN Configuration VALID 0TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr Default: BULK IN 64
E612 1EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPE0 SIZE 0BUF1 BUF0 10100010 bbbbbrbb Default: BULK OUT 512 double
buffered
E613 1EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 10100000 bbbbrrrr Default: BULK OUT (512 double
buffered only choice)
E614 1EP6CFG Endpoint 6 Configuration VALID DIR TYPE1 TYPE0 SIZE 0BUF1 BUF0 11100010 bbbbbrbb Default: BULK IN 512 double buff-
ered
E615 1EP8CFG Endpoint 8 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 11100000 bbbbrrrr Default: BULK IN (512 double buff-
ered only choice)
2reserved
E618 1EP2FIFOCFG
see Section 15.15 Endpoint 2 / slave FIFO configuration 0INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE 00000101 rbbbbbrb INFM1 (In FULL flag minus 1):
0=normal, 1=flags active one byte
early
OEP1 (Out EMPTY flag plus 1):
0=normal, 1=flags active one byte
early
AUTOOUT=1--valid OUT packet
automatically becomes part of OUT
FIFO
AUTOOUT=0--8051 decides if to
commit data to the OUT FIFO
AUTOIN=1--SIE packetizes/dis-
patches IN-FIFO data using EPx-
AUTOINLEN
AUTOIN=0--8051 dispatches an IN
packet by writing byte count
WORDWIDE=1: PB=FD[0:7],
PD=FD[8:15]; =1: PB=FD[0:7],
PD=PD
ZEROLENIN: 0=disable; 1=send
zero len pkt on
PKTEND - If any of the four WORD-
WIDE bits=1, core configures PD
as FD15:8
E619 1EP4FIFOCFG
see Section 15.15 Endpoint 4 / slave FIFO configuration 0INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE 00000101 rbbbbbrb
E61A 1EP6FIFOCFG
see Section 15.15 Endpoint 6 / slave FIFO configuration 0INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE 00000101 rbbbbbrb
E61B 1EP8FIFOCFG
see Section 15.15 Endpoint 8 / slave FIFO configuration 0INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE 00000101 rbbbbbrb
E61C 4reserved
E620 1EP2AUTOINLENH
see Section 15.15 Endpoint 2 AUTOIN Packet Length H 00000PL10 PL9 PL8 00000010 rrrrrbbb Default is 512 byte packets; can set
smaller IN packets.
SIE divides IN-FIFO data into this-
length packets when AUTOIN=1.
When AUTOIN=0, 8051 loads a
byte count for every packet
(in EPxBCH/L).
EP2,6 can have 1024 max bytes,
EP4,8 can have 512 max bytes.
these registers only used for
AUTOIN
E621 1EP2AUTOINLENL
see Section 15.15 Endpoint 2 AUTOIN Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E622 1EP4AUTOINLENH
see Section 15.15 Endpoint 4 AUTOIN Packet Length H 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
E623 1EP4AUTOINLENL
see Section 15.15 Endpoint 4 AUTOIN Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E624 1EP6AUTOINLENH
see Section 15.15 Endpoint 6 AUTOIN Packet Length H 00000PL10 PL9 PL8 00000010 rrrrrbbb
E625 1EP6AUTOINLENL
see Section 15.15 Endpoint 6 AUTOIN Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E626 1EP8AUTOINLENH
see Section 15.15 Endpoint 8 AUTOIN Packet Length H 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
E627 1EP8AUTOINLENL
see Section 15.15 Endpoint 8 AUTOIN Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
Table C-1. EZ-USB® Registers and Buffers (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access Notes
386 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Device Register Summary
E628 1ECCCFG ECC Configuration 0 0 0 0 0 0 0 ECCM 00000000 rrrrrrrb ECCM selects the ECC block size
mode.
E629 1ECCRESET ECC Reset x x x x x x x x 00000000 WECC RESET: This is an action reg-
ister; it resets the ecc calculation
E62A 1ECC1B0 ECC1 Byte 0 LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 RLINE [15:8] This is the second eight
bits of the line parity
E62B 1ECC1B1 ECC1 Byte 1 LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 00000000 RLINE[7:0] This is the lower eight bits
of the line parity
E62C 1ECC1B2 ECC1 Byte 2 COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 00000000 RCOL[5:0]: This is the 6 bit column
parity
LINE[17:16]: This is the upper two
bits of the line parity
E62D 1ECC2B0 ECC2 Byte 0 LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 RLINE[15:8]: This is the second eight
bits of the line parity
E62E 1ECC2B1 ECC2 Byte 1 LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 00000000 RLINE[7:0]: This is the lower eight
bits of the line parity
E62F 1ECC2B2 ECC2 Byte 2 COL5 COL4 COL3 COL2 COL1 COL0 0 0 00000000 RCOL[5:0]: This is the 6-bit column
parity
E630
H.S. 1EP2FIFOPFH
see Section 15.15 Endpoint 2 / slave FIFO Programmable
Flag H DECIS PKTSTAT IN:PKTS[2]
OUT:PFC12
PFC11
IN:PKTS[1]
OUT:PFC11
PFC10
IN:PKTS[0]
OUT:PFC10
PFC9
0PFC9 PFC8
PFC8
10001000 bbbbbrbb For complete details about this reg-
ister, refer to Section .
E630
F.S. 1EP2FIFOPFH
see Section 15.15 Endpoint 2 / slave FIFO Programmable
Flag H DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0PFC9 IN:PKTS[2]
OUT:PFC8 10001000 bbbbbrbb
E631
H.S. 1EP2FIFOPFL
see Section 15.15 Endpoint 2 / slave FIFO Programmable
Flag L PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E631
F.S 1EP2FIFOPFL
see Section 15.15 Endpoint 2 / slave FIFO Programmable
Flag L IN:PKTS[1]
OUT:PFC7 IN:PKTS[0]
OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E632
H.S. 1EP4FIFOPFH
see Section 15.15 Endpoint 4 / slave FIFO Programmable
Flag H DECIS PKTSTAT 0IN: PKTS[1]
OUT:PFC10 IN: PKTS[0]
OUT:PFC9 0 0 PFC8 10001000 bbrbbrrb Maximum 1024
E632
F.S 1EP4FIFOPFH
see Section 15.15 Endpoint 4 / slave FIFO Programmable
Flag H DECIS PKTSTAT 0OUT:PFC10 OUT:PFC9 0 0 PFC8 10001000 bbrbbrrb Maximum 1024
E633
H.S. 1EP4FIFOPFL
see Section 15.15 Endpoint 4 / slave FIFO Programmable
Flag L PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E633
F.S 1EP4FIFOPFL
see Section 15.15 Endpoint 4 / slave FIFO Programmable
Flag L IN: PKTS[1]
OUT:PFC7 IN: PKTS[0]
OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E634
H.S. 1EP6FIFOPFH
see Section 15.15 Endpoint 6 / slave FIFO Programmable
Flag H DECIS PKTSTAT IN:PKTS[2]
OUT:PFC12
PFC11
IN:PKTS[1]
OUT:PFC11
PFC10
IN:PKTS[0]
OUT:PFC10
PFC9
0PFC9 PFC8
PFC8
00001000 bbbbbrbb For complete details about this reg-
ister, refer to “Endpoint 2, 6/Slave
FIFO Programmable Level Flag
High Registers” on page 244.
E634
F.S 1EP6FIFOPFH
see Section 15.15 Endpoint 6 / slave FIFO Programmable
Flag H DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0PFC9 IN:PKTS[2]
OUT:PFC8 00001000 bbbbbrbb
E635
H.S. 1EP6FIFOPFL
see Section 15.15 Endpoint 6 / slave FIFO Programmable
Flag L PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E635
F.S 1EP6FIFOPFL
see Section 15.15 Endpoint 6 / slave FIFO Programmable
Flag L IN:PKTS[1]
OUT:PFC7 IN:PKTS[0]
OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E636
H.S. 1EP8FIFOPFH
see Section 15.15 Endpoint 8 / slave FIFO Programmable
Flag H DECIS PKTSTAT 0IN: PKTS[1]
OUT:PFC10 IN: PKTS[0]
OUT:PFC9 0 0 PFC8 00001000 bbrbbrrb Maximum 1024
E636
F.S 1EP8FIFOPFH
see Section 15.15 Endpoint 8 / slave FIFO Programmable
Flag H DECIS PKTSTAT 0OUT:PFC10 OUT:PFC9 0 0 PFC8 00001000 bbrbbrrb Maximum 1024
E637
H.S. 1EP8FIFOPFL
see Section 15.15 Endpoint 8 / slave FIFO Programmable
Flag L PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E637
F.S 1EP8FIFOPFL
see Section 15.15 Endpoint 8 / slave FIFO Programmable
Flag L IN: PKTS[1]
OUT:PFC7 IN: PKTS[0]
OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
8reserved
E640 1EP2ISOINPKTS EP2 (if ISO) IN Packets per frame (1-3) AADJ 00000INPPF1 INPPF0 00000001 brrrrrbb INPPF1:0: 00=illegal,
01=1 per frame, 10=2 per frame,
11=3 per frame
E641 1EP4ISOINPKTS EP4 (if ISO) IN Packets per frame (1) AADJ 00000INPPF1 INPPF0 00000001 brrrrrrr
E642 1EP6ISOINPKTS EP6 (if ISO) IN Packets per frame (1-2) AADJ 00000INPPF1 INPPF0 00000001 brrrrrbb
Table C-1. EZ-USB® Registers and Buffers (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access Notes
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 387
Device Register Summary
E643 1EP8ISOINPKTS EP8 (if ISO) IN Packets per frame (1) AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrrr
E644 4reserved
E648 1INPKTEND
see Section 15.15 Force IN Packet End Skip 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx WSame function as slave interface
PKTEND pin, but 8051 controls dis-
patch of IN,
Typically used after a GPIF FIFO
transaction completes to send jag-
ged edge pkt, user needs to check
status of FIFO full flag for available
buffer before doing
PKTEND
E649 7OUTPKTEND Force OUT Packet End Skip 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx WREVCTL.0=1 to enable this feature
INTERRUPTS
E650 1EP2FIFOIE
see Section 15.15 Endpoint 2 slave FIFO Flag Interrupt
Enable 0 0 0 0 EDGEPF PF EF FF 00000000 RW EDGEPF=0; Rising edge
EDGEPF=1; Falling edge
E651 1EP2FIFOIRQ
see Section 15.15 Endpoint 2 slave FIFO Flag Interrupt
Request 00000PF EF FF 00000000 rrrrrbbb Note: Can only reset, can not set
E652 1EP4FIFOIE
see Section 15.15 Endpoint 4 slave FIFO Flag Interrupt
Enable 0 0 0 0 EDGEPF PF EF FF 00000000 RW
E653 1EP4FIFOIRQ
see Section 15.15 Endpoint 4 slave FIFO Flag Interrupt
Request 00000PF EF FF 00000000 rrrrrbbb Note: Can only reset, can not set
E654 1EP6FIFOIE
see Section 15.15 Endpoint 6 slave FIFO Flag Interrupt
Enable 0 0 0 0 EDGEPF PF EF FF 00000000 RW
E655 1EP6FIFOIRQ
see Section 15.15 Endpoint 6 slave FIFO Flag Interrupt
Request 00000PF EF FF 00000000 rrrrrbbb Note: Can only reset, can not set
E656 1EP8FIFOIE
see Section 15.15 Endpoint 8 slave FIFO Flag Interrupt
Enable 0 0 0 0 EDGEPF PF EF FF 00000000 RW
E657 1EP8FIFOIRQ
see Section 15.15 Endpoint 8 slave FIFO Flag Interrupt
Request 00000PF EF FF 00000000 rrrrrbbb Note: Can only reset, can not set
E658 1IBNIE IN-BULK-NAK Interrupt Enable 0 0 EP8 EP6 EP4 EP2 EP1 EP0 00000000 RW
E659 1IBNIRQ IN-BULK-NAK interrupt Request 0 0 EP8 EP6 EP4 EP2 EP1 EP0 00xxxxxx rrbbbbbb 1 = clear request, 0= no effect, note:
can only reset, can not set
E65A 1NAKIE Endpoint Ping-NAK / IBN Interrupt
Enable EP8 EP6 EP4 EP2 EP1 EP0 0IBN 00000000 RW OUT endpoint was pinged and
NAK'd
E65B 1NAKIRQ Endpoint Ping-NAK / IBN Interrupt
Request EP8 EP6 EP4 EP2 EP1 EP0 0IBN xxxxxx0x bbbbbbrb note: can only reset, can not set
E65C 1USBIE USB Int Enables 0EP0ACK HSGRANT URES SUSP SUTOK SOF SUDAV 00000000 RW
E65D 1USBIRQ USB Interrupt Requests 0EP0ACK HSGRANT URES SUSP SUTOK SOF SUDAV 0xxxxxxx rbbbbbbb 1 = clear request, 0= no effect, note:
can only reset, can not set
E65E 1EPIE Endpoint Interrupt Enables EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 00000000 RW
E65F 1EPIRQ Endpoint Interrupt Requests EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 00000000 RW 1 = clear request, 0= no effect, note:
can only reset, can not set
E660 1GPIFIE
see Section 15.15 GPIF Interrupt Enable 0 0 0 0 0 0 GPIFWF GPIFDONE 00000000 RW WF--8051 ‘hook’ in waveform,
DONE-returned to IDLE state
E661 1GPIFIRQ
see Section 15.15 GPIF Interrupt Request 0 0 0 0 0 0 GPIFWF GPIFDONE 000000xx RW Write ‘1’ to clear
E662 1USBERRIE USB Error Interrupt Enables ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 00000000 RW ISO endpoint error: PID sequence
error or dropped packet (no avail-
able buffer)
E663 1USBERRIRQ USB Error Interrupt Requests ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 0000000x bbbbrrrb Note: Can only reset, can not set
E664 1ERRCNTLIM USB Error counter and limit EC3 EC2 EC1 EC0 LIMIT3 LIMIT2 LIMIT1 LIMIT0 xxxx0100 rrrrbbbb Default limit count is 4
E665 1CLRERRCNT Clear Error Counter EC3:0 x x x x x x x x xxxxxxxx W
E666 1INT2IVEC Interrupt 2 (USB) Autovector 0I2V4 I2V3 I2V2 I2V1 I2V0 0 0 00000000 R
E667 1INT4IVEC Interrupt 4 (slave FIFO and GPIF)
Autovector 1 0 I4V3 I4V2 I4V1 I4V0 0 0 10000000 R
Table C-1. EZ-USB® Registers and Buffers (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access Notes
388 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Device Register Summary
E668 1INTSETUP Interrupt 2 and4 Setup 0 0 0 0 AV2EN 0INT4SRC AV4EN 00000000 RW INT4IN=0: INT4 from pin; 1: INT4
from FIFO/GPIF interrupts
E669 7reserved
INPUT / OUTPUT
E670 1PORTACFG I/O PORTA Alternate Configuration FLAGD SLCS 0 0 0 0 INT1 INT0 00000000 RW
E671 1PORTCCFG I/O PORTC Alternate Configuration GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 00000000 RW
E672 1PORTECFG I/O PORTE Alternate Configuration GPIFA8 T2EX INT6 RXD1OUT RXD0OUT T2OUT T1OUT T0OUT 00000000 RW GSTATE bit =1 overrides bits 2:0.
E673 1reserved
E678 1I2CS I2C-Compatible Bus
Control and Status START STOP LASTRD ID1 ID0 BERR ACK DONE 000xx000 bbbrrrrr
E679 1I2DAT I2C-Compatible Bus
Data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx RW
E67A 1I2CTL I2C-Compatible Bus
Control 0 0 0 0 0 0 STOPIE 400KHZ 00000000 RW
E67B 1XAUTODAT1 Autoptr1 MOVX access, when
APTREN=1 D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW AUTOPTRSETUP bit
APTREN=1: off-chip access use
this reg - code-space hole at this
location
AUTOPTRSETUP bit
APTREN=0: on-chip access use
duplicate SFR @ 9C, no code-
space hole
E67C 1XAUTODAT2 Autoptr2 MOVX access, when
APTREN=1 D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
UDMA CRC
E67D 1UDMACRCH
see Section 15.15 UDMA CRC MSB CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8 01001010 RW
E67E 1UDMACRCL
see Section 15.15 UDMA CRC LSB CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 10111010 RW
E67F 1UDMACRC-
QUALIFIER UDMA CRC Qualifier QENABLE 0 0 0 QSTATE QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb
USB CONTROL
E680 1USBCS USB Control and Status HSM 0 0 0 DISCON NOSYNSOF RENUM SIGRSUME x0000000 rrrrbbbb
E681 1SUSPEND Put chip into suspend x x x x x x x x xxxxxxxx WWrite any value to suspend
E682 1WAKEUPCS Wakeup Control and Status WU2 WU WU2POL WUPOL 0DPEN WU2EN WUEN xx000101 bbbbrbbb
E683 1TOGCTL Toggle Control Q S R IO EP3 EP2 EP1 EP0 x0000000 rrrbbbbb
E684 1USBFRAMEH USB Frame count H 0 0 0 0 0 FC10 FC9 FC8 00000xxx R
E685 1USBFRAMEL USB Frame count L FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 xxxxxxxx R
E686 1MICROFRAME Microframe count, 0-7 0 0 0 0 0 MF2 MF1 MF0 00000xxx R
E687 1FNADDR USB Function address 0FA6 FA5 FA4 FA3 FA2 FA1 FA0 0xxxxxxx R
E688 2reserved
ENDPOINTS
E68A 1EP0BCH Endpoint 0 Byte Count H (BC15) (BC14) (BC13) (BC12) (BC11) (BC10) (BC9) (BC8) xxxxxxxx RW Even though the EP0 buffer is only
64 bytes, the EP0 byte count is ex-
panded to 16-bits to allow using the
Autoptr with a custom length, in-
stead of USB-dictated length (from
Setup Data Packet and number of
requested bytes).
The byte count bits in parentheses
apply only when SDPAUTO = 0
E68B 1EP0BCL Endpoint 0 Byte Count L (BC7) BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E68C 1reserved
E68D 1EP1OUTBC Endpoint 1 OUT Byte Count 0BC6 BC5 BC4 BC3 BC2 BC1 BC0 0xxxxxxx RW
E68E 1reserved
E68F 1EP1INBC Endpoint 1 IN Byte Count 0BC6 BC5 BC4 BC3 BC2 BC1 BC0 0xxxxxxx RW
Table C-1. EZ-USB® Registers and Buffers (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access Notes
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 389
Device Register Summary
E690 1EP2BCH
see Section 15.15 Endpoint 2 Byte Count H 00000BC10 BC9 BC8 00000xxx RW EP2,6 can be 512 or 1024
EP4,8 are 512 only
E691 1EP2BCL
see Section 15.15 Endpoint 2 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E692 2reserved
E694 1EP4BCH
see Section 15.15 Endpoint 4 Byte Count H 0 0 0 0 0 0 BC9 BC8 000000xx RW
E695 1EP4BCL
see Section 15.15 Endpoint 4 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E696 2reserved
E698 1EP6BCH
see Section 15.15 Endpoint 6 Byte Count H 00000BC10 BC9 BC8 00000xxx RW
E699 1EP6BCL
see Section 15.15 Endpoint 6 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E69A 2reserved
E69C 1EP8BCH
see Section 15.15 Endpoint 8 Byte Count H 0 0 0 0 0 0 BC9 BC8 000000xx RW
E69D 1EP8BCL
see Section 15.15 Endpoint 8 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E69E 2reserved
E6A0 1EP0CS Endpoint 0 Control and Status HSNAK 0 0 0 0 0 BUSY STALL 10000000 bbbbbbrb
E6A1 1EP1OUTCS Endpoint 1 OUT Control and Status 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb
E6A2 1EP1INCS Endpoint 1 IN Control and Status 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb
E6A3 1EP2CS Endpoint 2 Control and Status 0NPAK2 NPAK1 NPAK0 FULL EMPTY 0STALL 00101000 rrrrrrrb NPAK2:0=number of packets in the
FIFO, 0-4.
NPAK1:0=number of packets in the
FIFO, 0-2
OUT: Packets received from USB.
IN: Packets loaded and armed.
FULL / EMPTY status bits duplicat-
ed in SFR space, EP2468STAT
E6A4 1EP4CS Endpoint 4 Control and Status 0 0 NPAK1 NPAK0 FULL EMPTY 0STALL 00101000 rrrrrrrb
E6A5 1EP6CS Endpoint 6 Control and Status 0NPAK2 NPAK1 NPAK0 FULL EMPTY 0STALL 00000100 rrrrrrrb
E6A6 1EP8CS Endpoint 8 Control and Status 0 0 NPAK1 NPAK0 FULL EMPTY 0STALL 00000100 rrrrrrrb
E6A7 1EP2FIFOFLGS Endpoint 2 slave FIFO Flags 00000PF EF FF 00000010 RNot affected by FIFOPINPOLAR
bits.duplicated in SFR space,
EP24FIFOFLGS and
EP68FIFOFLGS
E6A8 1EP4FIFOFLGS Endpoint 4 slave FIFO Flags 00000PF EF FF 00000010 R
E6A9 1EP6FIFOFLGS Endpoint 6 slave FIFO Flags 00000PF EF FF 00000110 R
E6AA 1EP8FIFOFLGS Endpoint 8 slave FIFO Flags 00000PF EF FF 00000110 R
E6AB 1EP2FIFOBCH Endpoint 2 slave FIFO total byte count H 000BC12 BC11 BC10 BC9 BC8 00000000 ROUT: full byte count; IN: bytes in
current packet
EP2 max 4096
EP4 max 1024
EP6 max 2048
EP* max 1024
E6AC 1EP2FIFOBCL Endpoint 2 slave FIFO total byte count L BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
E6AD 1EP4FIFOBCH Endpoint 4 slave FIFO total byte count H 00000BC10 BC9 BC8 00000000 R
E6AE 1EP4FIFOBCL Endpoint 4 slave FIFO total byte count L BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
E6AF 1EP6FIFOBCH Endpoint 6 slave FIFO total byte count H 0 0 0 0 BC11 BC10 BC9 BC8 00000000 R
E6B0 1EP6FIFOBCL Endpoint 6 slave FIFO total byte count L BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
E6B1 1EP8FIFOBCH Endpoint 8 slave FIFO total byte count H 00000BC10 BC9 BC8 00000000 R
E6B2 1EP8FIFOBCL Endpoint 8 slave FIFO total byte count L BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
E6B3 1SUDPTRH Setup Data Pointer high address byte A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW
E6B4 1SUDPTRL Setup Data Pointer low address byte A7 A6 A5 A4 A3 A2 A1 0xxxxxxx0 bbbbbbbr Must be word-aligned (i.e., must
point to even-numbered address-
es)
E6B5 1SUDPTRCTL Setup Data Pointer Auto Mode 0000000SDPAUTO 00000001 RW Clear b0 to supply SUDPTR length
(override USB length)
2reserved
E6B8 8SETUPDAT 8 bytes of SETUP data D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R
Table C-1. EZ-USB® Registers and Buffers (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access Notes
390 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Device Register Summary
SETUPDAT[0] = bmRequestType D7: Data Transfer Direction;
0=host-to-device, 1=device-to-host
D6…5 Type; 0=standard, 1=class,
2=vendor, 3=reserved
D4…0 Recipient; 0=device,
1=interface, 2=endpoint,
3=other, 4…31=reserved
SETUPDAT[1] = bmRequest Specific request
SETUPDAT[2:3] = wValue Word-sized field that varies
according to request
SETUPDAT[4:5] = wIndex Word-sized field that varies
according to request; typically used
to pass an index or offset
SETUPDAT[6:7] = wLength Number of bytes to transfer if there
is a data stage
GPIF
E6C0 1GPIFWFSELECT Waveform Selector SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0 FIFORD1 FIFORD0 11100100 RW Select waveform
E6C1 1GPIFIDLECS GPIF Done, GPIF IDLE drive mode DONE 0 0 0 0 0 0 IDLEDRV 10000000 RW DONE=1: GPIF done (IRQ4).
IDLEDRV=1: drive bus, 0:TS
DONE duplicated in SFR space,
GPIFTRIG bit 7
E6C2 1GPIFIDLECTL Inactive Bus, CTL states 0 0 CTL5 CTL4 CTL3 CTL2 CTL1 CTL0 11111111 RW
E6C3 1GPIFCTLCFG CTL Drive Type TRICTL 0CTL5 CTL4 CTL3 CTL2 CTL1 CTL0 00000000 RW 0=CMOS, 1=open drn.
E6C4 1GPIFADRH
see Section 15.15 GPIF Address H 0 0 0 0 0 0 0 GPIFA8 00000000 RW GPIFADRH/L active immediately
when written to
E6C5 1GPIFADRL
see Section 15.15 GPIF Address L GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 00000000 RW
FLOWSTATE
E6C6 1 FLOWSTATE Flowstate Enable and Selector FSE 0 0 0 0 FS2 FS1 FS0 00000000 brrrrbbb
E6C7 1FLOWLOGIC Flowstate Logic LFUNC1 LFUNC0 TERMA2 TERMA1 TERMA0 TERMB2 TERMB1 TERMB0 00000000 RW
E6C8 1FLOWEQ0CTL CTL Pin States in Flowstate
(when Logic = 0) CTL0E3 CTL0E2 CTL0E1/
CTL5 CTL0E0/
CTL4 CTL3 CTL2 CTL1 CTL0 00000000 RW
E6C9 1FLOWEQ1CTL CTL Pin States in Flowstate
(when Logic = 1) CTL0E3 CTL0E2 CTL0E1/
CTL5 CTL0E0/
CTL4 CTL3 CTL2 CTL1 CTL0 00000000 RW
E6CA 1FLOWHOLDOFF Holdoff Configuration HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0 HOSTATE HOCTL2 HOCTL1 HOCTL0 00010010 RW
E6CB 1FLOWSTB Flowstate Strobe Configuration SLAVE RDYASYNC CTLTOGL SUSTAIN 0MSTB2 MSTB1 MSTB0 00100000 RW
E6CC 1FLOWSTBEDGE Flowstate Rising/Falling Edge Configura-
tion 0 0 0 0 0 0 FALLING RISING 00000001 rrrrrrbb
E6CD 1FLOWSTBPERIOD Master-Strobe Half-Period D7 D6 D5 D4 D3 D2 D1 D0 00000010 RW In units of IFCLK/2. Must be >= 2
E6CE 1GPIFTCB3 GPIF Transaction Count Byte 3 TC31 TC30 TC29 TC28 TC27 TC26 TC25 TC24 00000000 RW Reading these registers give you
the live Transaction Count.
Default=1
E6CF 1GPIFTCB2 GPIF Transaction Count Byte 2 TC23 TC22 TC21 TC20 TC19 TC18 TC17 TC16 00000000 RW
E6D0 1GPIFTCB1 GPIF Transaction Count Byte 1 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 00000000 RW
E6D1 1GPIFTCB0 GPIF Transaction Count Byte 0 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 00000001 RW
2reserved 00000000 RW
reserved
reserved
E6D2 1EP2GPIFFLGSEL
see Section 15.15 Endpoint 2 GPIF Flag select 0 0 0 0 0 0 FS1 FS0 00000000 RW 00: Programmable flag;
01: Empty, 10: Full,
11: reserved
E6D3 1EP2GPIFPFSTOP Endpoint 2 GPIF stop transaction on pro-
gram flag 0 0 0 0 0 0 0 FIFO2FLAG 00000000 RW 1=override TC value, stop on FIFO
Prog. Flag.
E6D4 1EP2GPIFTRIG
see Section 15.15 Endpoint 2 GPIF Trigger x x x x x x x x xxxxxxxx WStart GPIF transactions, duplicated
in SFR - GPIFTRIG
3reserved
reserved
reserved
Table C-1. EZ-USB® Registers and Buffers (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access Notes
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 391
Device Register Summary
E6DA 1EP4GPIFFLGSEL
see Section 15.15 Endpoint 4 GPIF Flag select 0 0 0 0 0 0 FS1 FS0 00000000 RW 00: Programmable level;
01: Empty, 10: Full,
11: reserved
E6DB 1EP4GPIFPFSTOP Endpoint 4 GPIF stop transaction on GPIF
Flag 0000000FIFO4FLAG 00000000 RW
E6DC 1EP4GPIFTRIG
see Section 15.15 Endpoint 4 GPIF Trigger x x x x x x x x xxxxxxxx WStart GPIF transactions, duplicated
in SFR - GPIFTRIG
3reserved
reserved
reserved
E6E2 1EP6GPIFFLGSEL
see Section 15.15 Endpoint 6 GPIF Flag select 0 0 0 0 0 0 FS1 FS0 00000000 RW 00: Programmable flag;
01: Empty, 10: Full,
11: reserved (PF)
E6E3 1EP6GPIFPFSTOP Endpoint 6 GPIF stop transaction on prog.
flag 0000000FIFO6FLAG 00000000 RW
E6E4 1EP6GPIFTRIG
see Section 15.15 Endpoint 6 GPIF Trigger x x x x x x x x xxxxxxxx WStart GPIF transactions, duplicated
in SFR - GPIFTRIG
3reserved
reserved
reserved
E6EA 1EP8GPIFFLGSEL
see Section 15.15 Endpoint 8 GPIF Flag select 0 0 0 0 0 0 FS1 FS0 00000000 RW 00: Programmable flag;
01: Empty, 10: Full,
11: Reserved (PF)
E6EB 1EP8GPIFPFSTOP Endpoint 8 GPIF stop transaction on prog.
flag 0000000FIFO8FLAG 00000000 RW
E6EC 1EP8GPIFTRIG
see Section 15.15 Endpoint 8 GPIF Trigger x x x x x x x x xxxxxxxx WStart GPIF transactions, duplicated
in SFR - GPIFTRIG
3reserved
E6F0 1 XGPIFSGLDATH GPIF Data H (16-bit mode only) D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW Duplicated in SFR space,
SGLDATH / SGLDATLX /
SGLDATLNOX
E6F1 1XGPIFSGLDATLX Read/Write GPIF Data L and trigger trans-
action D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW 8051read or write triggers GPIF
transaction
E6F2 1XGPIFSGLDATLNOX Read GPIF Data L, no transaction trigger D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R8051 reads data w/o GPIF transac-
tion trig. (e.g. last byte)
E6F3 1GPIFREADYCFG Internal RDY, Sync/Async, RDY pin states INTRDY SAS TCXRDY5 0000000000000 bbbrrrrr INTRDY is 8051 'ready', like RDYn
pins. RDYn indicate pin states
SAS=1: synchronous, 0:asynchro-
nous (2-flops) RDYn inputs
E6F4 1GPIFREADYSTAT GPIF Ready Status 0 0 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 00xxxxxx RRDYn indicate pin states
E6F5 1GPIFABORT Abort GPIF Waveforms x x x x x x x x xxxxxxxx WGo To GPIF IDLE state. Data is
don’t care
E6F6 2reserved
ENDPOINT BUFFERS
E740 64 EP0BUF EP0-IN/-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E780 64 EP10UTBUF EP1-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E7C0 64 EP1INBUF EP1-IN buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
2048 reserved RW
F000 1024 EP2FIFOBUF 512/1024-byte EP 2 / slave FIFO buffer
(IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW For 512 use only 0xF000-0xF1FF
F400 512 EP4FIFOBUF 512 byte EP 4 / slave FIFO buffer
(IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
F600 512 reserved
F800 1024 EP6FIFOBUF 512/1024-byte EP 6 / slave FIFO buffer
(IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW For 512 use only 0xF800-0xF9FF
Table C-1. EZ-USB® Registers and Buffers (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access Notes
392 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Device Register Summary
FC00 512 EP8FIFOBUF 512 byte EP 8 / slave FIFO buffer
(IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
FE00 512 reserved
xxxx I²C Compatible Configuration Byte 0DISCON 0 0 0 0 0 400KHZ xxxxxxxx n/a
00000000
If no
EPROM de-
tected
DISCON = copied into DISCON bit
(USBCS.3) for power-on USB con-
nect state
400KHZ = 1 for 400 KHz I2C com-
patible bus operation
Note: If no EEPROM is connected
all bits default to register default
values.
Special Function Registers (SFRs)
80 1IOA(1) Port A (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
81 1SP Stack Pointer D7 D6 D5 D4 D3 D2 D1 D0 00000111 RW
82 1DPL0 Data Pointer 0 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
83 1DPH0 Data Pointer 0 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
84 1DPL1(1) Data Pointer 1 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
85 1DPH1(1) Data Pointer 1 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
86 1DPS(1) Data Pointer 0/1 select 0 0 0 0 0 0 0 SEL 00000000 RW
87 1PCON Power Control SMOD0 x 1 1 x x x IDLE 00110000 RW
88 1TCON Timer/Counter Control (bit addressable) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000 RW
89 1TMOD Timer/Counter Mode Control GATE CT M1 M0 GATE CT M1 M0 00000000 RW
8A 1TL0 Timer 0 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
8B 1TL1 Timer 1 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
8C 1TH0 Timer 0 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW
8D 1TH1 Timer 1 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW
8E 1CKCON(1) Clock Control x x T2M T1M T0M MD2 MD1 MD0 00000001 RW MOVX = 3 instr. cycles (default)
8F 1reserved
90 1IOB(1) Port B (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
91 1EXIF(1) External Interrupt Flags IE5 IE4 I²CINT USBNT 1 0 0 0 00001000 RW
92 1MPAGE(1) Upper Addr Byte of MOVX using
@R0 / @R1 A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW Used with the indirect addressing
instructions, i.e. MOVX @R0,A
where
MPAGE = upper addr byte and R0
contains lower addr byte
an app. example would be to copy
EP1 out/in data to a buffer
93 5reserved
98 1SCON0 Serial Port 0 Control (bit addressable) SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00000000 RW
99 1SBUF0 Serial Port 0 Data Buffer D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
9A 1AUTOPTRH1(1) Autopointer 1 Address H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
9B 1AUTOPTRL1(1) Autopointer 1 Address L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
9C 1reserved
9D 1AUTOPTRH2(1) Autopointer 2 Address H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
9E 1AUTOPTRL2(1) Autopointer 2 Address L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
Table C-1. EZ-USB® Registers and Buffers (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access Notes
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 393
Device Register Summary
9F 1reserved
A0 1IOC(1) Port C (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
A1 1INT2CLR(1) Interrupt 2 clear x x x x x x x x xxxxxxxx W
A2 1INT4CLR(1) Interrupt 4 clear x x x x x x x x xxxxxxxx W
A3 5reserved
A8 1IE Interrupt Enable (bit addressable) EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00000000 RW
A9 1reserved
AA 1EP2468STAT(1) Endpoint 2,4,6,8 status flags EP8F EP8E EP6F EP6E EP4F EP4E EP2F EP2E 01011010 RCheck Empty/Full status of
EP 2,4,6,8 using MOV
AB 1EP24FIFOFLGS(1) Endpoint 2,4 slave FIFO status flags 0EP4PF EP4EF EP4FF 0EP2PF EP2EF EP2FF 00100010 RCheck Prg/Empty/Full status of
EP 2,4 slave FIFO using MOV instr.
AC 1EP68FIFOFLGS(1) Endpoint 6,8 slave FIFO status flags 0EP8PF EP8EF EP8FF 0EP6PF EP6EF EP6FF 01100110 RCheck Prg/Empty/Full status of EP
6,8 slave FIFO using MOV instr.
AD 2reserved
AF 1AUTOPTRSETUP(1) Autopointer 1 and 2 Setup 00000APTR2INC APTR1INC APTREN 00000110 RW APTRxINC=1 inc autopointers; AP-
TRxINC=0 freeze autopointers
APTREN=1 RD/WR strobes as-
serted when using MOVX version
B0 1IOD(1) Port D (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
B1 1IOE(1) Port E (NOT bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
B2 1OEA(1) Port A Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B3 1OEB(1) Port B Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B4 1OEC(1) Port C Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B5 1OED(1) Port D Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B6 1OEE(1) Port E Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B7 1reserved
B8 1IP Interrupt Priority (bit addressable) 1PS1 PT2 PS0 PT1 PX1 PT0 PX0 10000000 RW
B9 1reserved
BA 1EP01STAT(1) Endpoint 0 and 1 Status 00000EP1INBSY EP1OUTBS
YEP0BSY 00000000 RCheck EP0 and EP1 status using
MOV instruction
BB 1GPIFTRIG(1)
see Section 15.15 Endpoint 2,4,6,8 GPIF slave FIFO Trigger DONE 0 0 0 0 RW EP1 EP0 10000xxx brrrrbbb RW=1 reads, RW=0 writes;
EP[1:0] = 00 EP2, = 01 EP4, = 10
EP6, = 11 EP8
BC 1reserved
BD 1GPIFSGLDATH(1) GPIF Data H (16-bit mode only) D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW Efficient versions of their MOVX
buddies
BE 1GPIFSGLDATLX(1) GPIF Data L w/ Trigger D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
BF 1GPIFSGLDATLNOX (1) GPIF Data L w/ No Trigger D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RNote: READ only, this should help
you decide when to appropriately
use it
C0 1SCON1(1) Serial Port 1 Control (bit addressable) SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00000000 RW
C1 1SBUF1(1) Serial Port 1 Data Buffer D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
C2 6reserved
C8 1T2CON Timer/Counter 2 Control
(bit addressable) TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 00000000 RW
C9 1reserved
CA 1RCAP2L Capture for Timer 2, auto-reload,
up-counter D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
CB 1RCAP2H Capture for Timer 2, auto-reload,
up-counter D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
CC 1TL2 Timer 2 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
CD 1TH2 Timer 2 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW
CE 2reserved
Table C-1. EZ-USB® Registers and Buffers (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access Notes
394 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Device Register Summary
D0 1PSW Program Status Word (bit addressable) CY AC F0 RS1 RS0 OV F1 P00000000 RW
D1 7reserved
D8 1EICON(1) External Interrupt Control SMOD1 1ERESI RESI INT6 0 0 0 01000000 RW RESI - reflects D+ / WU / WU2 src
while SUSPEND (PCON.1), clocks
off
D9 7reserved
E0 1ACC Accumulator (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
E1 7reserved
E8 1EIE(1) External Interrupt Enables 1 1 1 EX6 EX5 EX4 EI²C EUSB 11100000 RW
E9 7reserved
F0 1 B B (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
F1 7reserved
F8 1EIP(1) External Interrupt Priority Control 1 1 1 PX6 PX5 PX4 PI²C PUSB 11100000 RW
F9 7reserved
(1) SFRs not part of the standard 8051 architecture.
Table C-1. EZ-USB® Registers and Buffers (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access Notes
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 395
Index
#
100 pin package 22
128 pin package 22, 23
230 Kbaud clock register 228
56 pin SSOP 22
56 pin VFBGA 22
803x/805x feature comparison 171
8051 enhancements 170
A
abort GPIF cycles register 358
aborting packets in FIFO 120
ACC register 179
access to endpoint data 89
access to IN packets 116
accessible memory spaces 96
accumulator 179
addressing an I2C peripheral 189
asynchronous FIFO IN data transfers 119
asynchronous FIFO reads 109, 110
asynchronous FIFO writes 108, 109
asynchronous mode 100
auto mode 118
auto-in initialization 117
auto-in mode 111
auto-out initialization 117
auto-out mode 111
autopointer setup registers 215
autopointers 96
AUTOPOINTERs 1 and 2 MOVX access
registers 282
autovector coding 68
autovectoring 67
B
B register 179
block diagram
EZ-USB 21
simplified package 19
BPADDRx register 227
breakpoint address registers 227
breakpoint control register 226
BREAKPT register 226
bulk transfers 16
burst transactions 150
C
C0 load format 53
C2 load format 53
chip revision control register 231
chip revision ID register 230
CKCON register 178, 179, 197
clear error count register 271
clear feature 43
clearing interrupt requests 65
CLRERRCNT register 271
code example
aborting packets in FIFO in AUTOIN mode 120
asynchronous slave FIFO IN data transfers 119
AUTOIN = 1 115
AUTOOUT=0, commit packet 113
AUTOOUT=0, skip packet 114
AUTOOUT=0, source 114
committing a packet via INPKTEND 116
committing an OUT packet 165
committing packets via EPxBCL 156
committing packets via INPKTEND 155
committing packets via OUTPKTEND 163
configuring AUTOIN 112
configuring AUTOOUT 112, 113
configuring AUTOOUT = 1 164
ECC check/correct 284
editing a packet via EPxBCH 117
FIFO-read transaction code 156
FIFO-read transaction functions 154
FIFO-write transaction code 164
FIFO-write transaction functions 162
GPIF framework and functions 137
initialization code for AUTOOUT=0 165
initialization code for single-read 146
initialization code for single-write transactions 149
initialization for FIFO read transactions 155
initialization for FIFO-write transactions 163
OUT endpoint initialization 114
single-read transaction functions 145
single-write transaction functions 149
skipping a packet via INPKTEND 117
skipping an OUT packet 166
skipping out packets in AUTOOUT mode 119
sourcing an IN packet 116, 158
sourcing an OUT packet 166
synchronous slave FIFO IN data transfer 118
writing INPKTEND with EPx number 157
396 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Index
compatibility
feature-by-feature 171
configuration descriptor
high speed 376
control of endpoints 89
control transfers 16
CPU access to IN packets 115
CPU access to OUT packets 112
CPU control and status register 220
CPU reset 84
CPU reset effects 84
CPUCS register 220
CTL output drive type register 336
CTL output in idle register 335
CTL output states in idle 335
CY7C68013A and CY7C68015A differences 22
D
data memory 76
data pointers 179
data toggle control register 300
default USB device 52
default USB device respond 56
descriptors for high speed mode 375
device descriptor
full speed 367
high speed 375
device qualifier
full speed 368
high speed 375
document history 35
DPH0 register 179
DPH1 register 179
DPL0 register 179
DPL1 register 179
DPS register 179
DPTR0 179
DPTR1 179
E
ECC See error correcting codes
ECC check/correct code example 284
ECC configuration register 287
ECC control and data registers 283–294
ECC generation 167
ECC reset register 288
ECC1B0 register 289
ECC1B1 register 290
ECC1B2 register 291
ECC2B0 register 292
ECC2B1 register 293
ECC2B2 register 294
ECCCFG register 287
ECCRESET register 288
EEPROM boot loader 192
EEPROM boot-load data format 52
EEPROM configuration byte 55
eight bytes of setup data 332
endpoint ’x’/slave FIFO programmable-level flag
registers 244, 246, 247
endpoint 0 registers 305, 306
endpoint 1 IN byte count register 308
endpoint 1 OUT byte count register 307
endpoint 2 byte count registers 309, 313
endpoint 4 byte count registers 311, 313
endpoint 6 byte count registers 310, 313
endpoint 8 byte count registers 312, 313
endpoint buffer registers 359–365
endpoint buffers
access to 87
how the CPU configures 88
large and small 87
endpoint configuration registers 233–255
endpoint descriptor
full speed 369, 370, 371, 372, 373, 374
high speed 377, 378, 379, 380, 381
endpoint registers 305–332
endpoint x AUTOIN packet length registers 239,
240, 241, 242, 243
endpoint x configuration registers 235
endpoint x control and status registers 314, 315,
316, 317, 318, 319, 320
endpoint x GPIF flag select registers 350
endpoint x GPIF stop transaction registers 351
endpoint x ISO IN packets per Frame 251, 252, 253
endpoint x ISO IN packets per frame register 250
endpoint x slave FIFO flags registers 321, 322,
323, 324
endpoint x slave FIFO GPIF trigger registers 352
endpoint x slave FIFO total byte count
registers 325, 326, 327, 328, 329
endpoint zero 37
endpoint/slave FIFO configuration registers 237
endpoints 89
EP0BCH 90
EP0BCL 90
IN 248
OUT 249
enter suspend state register 298
enumeration 16
enumeration and ReNumeration 51
EP01STAT 91
EP0BCH register 305
EP0BCL register 306
EP0BUF register 359
EP0CS 90
EP0CS register 314
EP1INBC 92
EP1INBC register 308
EP1INBUF register 361
EP1INCFG register 234
EP1INCS 91
EP1INCS register 316
EP1OUTBC 91
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 397
Index
EP1OUTBC register 307
EP1OUTBUF register 360
EP1OUTCFG register 233
EP1OUTCS 91
EP1OUTCS register 315
EP2468STAT 92
EP2AUTOINLENH registers 239
EP2BCH register 309
EP2CS register 317
EP2FIFOBCH register 325
EP2FIFOBUF register 362
EP2FIFOFLGS register 321
EP2ISOINPKTS register 250
EP4AUTOINLENH register 241
EP4BCH register 311
EP4CS register 318
EP4FIFOBCH register 327
EP4FIFOBUF register 363
EP4FIFOFLGS register 322
EP4ISOINPKTS register 251
EP6AUTOINLENH register 240
EP6BCH register 310
EP6CS register 319
EP6FIFOBCH register 326
EP6FIFOBUF register 364
EP6FIFOFLGS register 323
EP6ISOINPKTS register 252
EP8AUTOINLENH register 242
EP8BCH register 312
EP8CS register 320
EP8FIFOBCH register 328
EP8FIFOBUF register 365
EP8FIFOFLGS register 324
EP8ISOINPKTS register 253
EPIE register 264
EPIRQ register 265
EPx memories 111
EPxAUTOINLENL registers 243
EPxBCH low 93
EPxBCL registers 313
EPxCFG registers 235
EPxCS 92
EPxFIFOBCL registers 329
EPxFIFOCFG registers 237
EPxFIFOIE registers 256
EPxFIFOIRQ registers 257
EPxFIFOPFH registers 244
EPxFIFOPFL registers 247
EPxGPIFFLGSEL registers 350
EPxGPIFPFSTOP registers 351
EPxGPIFTRIG registers 352
EPxISOINPKTS 92
ERRCNTLIM register 270
error correcting codes 283
external data memory 71, 72
external FIFO interface 31
external program memory 71, 72
external program/data memory map 75
EZ-USB
and DS80C320 differences 172
architecture 18
block diagram 21
CPU 169
differences with DS80C320 interrupts 172
endpoint buffers 30
endpoint FIFOs signals 23
feature summary 20
input output systems 181
instruction set 176
integrated microprocessor 20
internal RAM 172
IO ports 173
low-power mode implementation 173
package types 22
package types signal names 24
performance overview 170
register interface 172
registers 211
registers and buffers summary 384
software compatibility with 8051 171
supported interrupts 173
EZ-USB chips
100 pin 73
128 pin 73
56 pin 73
EZ-USB CPU Features 169
EZ-USB FIFOs
in GPIF master mode 33
in slave FIFO mode 32
EZ-USB FX1
part numbers 34
EZ-USB FX2LP
package diagrams 25
part numbers 34
F
FIFOmaximum sizes 249
FIFO cleared after a hard reset 167
FIFO data bus 101
FIFO flag pin functions 223
FIFO flag pins 103
FIFO programmable-level flag 111
FIFO reset register 225
FIFO/GPIF autovector coding 70
FIFO/GPIF interrupt 69
FIFOINPOLAR register 229
FIFO-read transaction 151
FIFO-read transaction waveform 152
FIFORESET register 225
FIFO-write transaction 159
firmware access to IN packets 156, 157
firmware access to OUT packets 164, 165
firmware FIFO access 110
firmware load 56
firmware ReNumeration 57
FLAGx pins 103
398 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Index
FLOWEQxCTL registers 342
FLOWHOLDOFF register 345
FLOWLOGIC register 341
FLOWSTATE register 340
FLOWSTB register 344
FLOWSTBEDGE register 346
FLOWSTBHPERIOD register 347
FNADDR register 304
force IN packet end register 254
force OUT packet end register 255
G
general configuration registers 220–232
general programmable interface (GPIF) 121
get configuration 47
get descriptor 43
get interface 48
get status interface 42
Get_Descriptor requests 44
Get_Status request 41
GPIF8/16-bit data path 125
address OUT signals 124
and the EZ-USB system 122
byte order for 16-bit transactions 125
connecting signal pins to hardware 126
control out signals 124
decision point (DP) 129, 130
default pins configuration 124
example hardware interconnect 126
external interface 124
flag selection 150
flag stop 150
framework and functions source code 137
GSTATE OUT signals 124
IDLE state 128
interrupt enable register 266
interrupt request register 267
non-decision point (NDP) 128
programming the waveforms 127
ready IN signals 124
re-executing a task within a DP state 131
registers 127, 333–358
registers associated with firmware 137
terminating a transfer 136
transaction waveform 123
waveform descriptor 219
GPIF address low 339
GPIF address registers 338, 339
GPIF data high (16 bit mode) register 353
GPIF done and idle drive mode register 334
GPIF done, GPIF idle drive mode 334
GPIF flow holdoff register 345
GPIF flow logic CTL output drive registers 342
GPIF flow master strobe edge register 346
GPIF flow master strobe half period register 347
GPIF flow master strobe register 344
GPIF flow state logic register 341
GPIF flow state register 340
GPIF hold amount register 348
GPIF hold time register 232
GPIF ready pin configuration register 356
GPIF ready pin status register 357
GPIF transaction count byte registers 349
GPIF waveform memories registers 219
GPIF waveform selector register 333
GPIFABORT register 358
GPIFADRH register 338
GPIFADRL register 339
GPIFCTLCFG register 336
GPIFHOLDAMOUNT register 232, 348
GPIFIDLECS register 334
GPIFIDLECTL register 335
GPIFIE register 266
GPIFIRQ register 267
GPIFREADYCFG register 356
GPIFREADYSTAT register 357
GPIFTCBx registers 349
GPIFWFSELECT register 333
H
hard reset 83
high speed and full speed differences 87
I
I/O PORTA alternate configuration register 275
I/O PORTC alternate configuration register 276
I/O PORTE alternate configuration register 277
I/O ports 181
I2C bus
control and status register 278
control register 281
data register 280
interrupt 68
I2C bus controller 189
I2C bus usage 54
I2C registers 191
I2CDAT register 280
I2CS register 278
I2CTL register 281
IBNIE register 258
IBNIRQ register 259
IFCFG selection of port IO pin functions 188
IFCLK configuration 102
IFCONFIG register 221
initialization, auto-in/auto-out 117
INPKTEND register 254
input/output registers 275–282
instruction cycle 178
instruction set 175
instruction timing 178
INT 2 (USB) autovector register 272
INT 2 and INT 4 setup register 274
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 399
Index
INT 4 (slave FIFOs and GPIF) autovector
register 273
int0_n 63, 194
int1_n 63, 194
INT2IVEC register 272
int4 63
INT4IVEC register 273
int5_n 63
interface clock 102
interface clock (IFCLK) 125
interface configuration register 221
interface descriptor
full speed 370, 372
high speed 376, 378, 380
interface modes 23
interface pins polarity register 229
interfacing to I2C peripherals 189
internal data memory 71
internal data RAM 71
lower 128 72
special function register 72
upper 128 72
interrupt
compatibility 61
enabling 62
latency 63
masking 62
priorities 62
processing 62
sampling 62
service routine 62
transfers 16
wakeup 81
interrupt enable registers
endpoint 264
endpoint ping-NAK/IBN 260
endpoint x slave FIFO flag 256
GPIF 266
IN-BULK-NAK 258
USB 262
USB error 268
interrupt registers 256–274
interrupt request registers
endpoint 265
endpoint ping-NAK/IBN 261
endpoint x slave FIFO flag 257
GPIF 267
IN-BULK-NAK 259
USB 263
USB error 269
interrupts 59
endpoint interrupts 66
EP0ACK interrupt 66
EPxISOERR interrupt 67
EPxPING interrupt 66
ERRLIMIT interrupt 67
FIFO/GPIF 69
high speed 66
in-bulk-NAK 66
start of frame 66
SUDAV 66
suspend 66
SUTOK 66
USB bus reset 66
introduction to USB 13
INTSETUP register 274
IO port alternate functions 183
isochronous transfers 16
J
jump instruction and autovectoring 67
M
memory
external data 72
external data memory 71
external program 72
EZ-USB 72
internal data RAM 71
standard 8051 72
memory maps 74
MICROFRAME register 303
N
NAKIE register 260
NAKIRQ register 261
non-decision point state instruction 134
O
off chip program memory 76
on chip data memory 76
OUTPKTEND register 255
P
pin assignment
100 pin TQFP 26
128 pin TQFP 25
56 pin QFN 28
56 pin SSOP 27
56 pin VFBGA 29
PINFLAGSxx register 223
PKTEND 104
port A alternate functions 185
port B and port D alternate functions 186
port C alternate functions 187
port E alternate functions 188
PORTACFG register 275
PORTCCFG register 276
PORTECFG register 277
ports, GPIF, slave FIFOs register 221
power management 77
program status word 179
programmable-level flag 111
PSW register 179, 180
400 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Index
R
RCAP2H register 197
RCAP2L register 197
read GPIF data low, no transaction trigger
register 355
read/write GPIF data low and trigger transaction
register 354
receive data 191
register summary
endpoint buffers 391
endpoint configuration 385
endpoints 388
flowstate 390
general configuration 384
GPIF 390
GPIF waveform memories 384
I2C compatible configuration byte 392
input/output 388
interrupts 387
special function registers (SFR) 392
UDMA 385
UDMA CRC 388
USB control 388
registers
conventions 211
endpoint configuration 233–255
general configuration 220–232
GPIF waveform memories 219
special function 212–218
registers associated with EP0 control transfers 39
registers that control all endpoints
CLRERRCNT 94
EPIE 94
EPIRQ 94
ERRCNTLIM 94
IBNIE 93
IBNIRQ 93
NAKIE 93
TOGCTL 95
USBERRIE 94
registers that control EP2, EP4, EP6, and EP8 92
registers that require a synchronization delay 366
remote wakeup 81
RENUM bit 56
ReNumeration 18
resets 83
CPU reset 84
EZ-USB disconnect 85
hard reset 83
summary 85
USB bus reset 85
REVCTL register 231
REVID register 230
rxd0_in 202, 207
rxd0_out 202
rxd1_in 202
rxd1_out 202
S
SBUF0 register 201
SBUF1 register 201
SCON0 register 201
SCON1 register 201
send data 191
serial interface
description 201
serial interface engine (SIE) 17
serial port 0/1
description 201
mode 0 202
mode 1 205
mode 2 208
mode 3 210
modes 201
set address 48
set descriptor 46
set interface 47
setup data pointer 95
setup data pointer address registers 330
setup data pointer AUTO mode register 331
setup data registers 332
SETUPDAT registers 332
SFR registers and external RAM equivalent 218
single-read transactions 143
single-write transaction waveform 147
single-write transactions 147
skipping a packet 157
skipping out packets while in AUTOOUT mode 119
slave FIFO
chip select (SLCS#) 104
control pins 103
firmware 110–120
hardware 99–110
pins 100
slave FIFO’s 99, 101
SOF interrupt 66
SP register 179
special function register space 72
special function registers 59, 174, 212–218
stack pointer 179
start of frame Interrupt 66
startup modes 51
SUDAV interrupt 66
SUDPTRCTL register 331
SUDPTRx registers 330
summary of interrupt sources 62
suspend interrupt 66
SUSPEND register 298
suspend register 79
suspend state 298
suspend-resume control logic 78
SUTOK interrupt 66
switching between manual-out and auto-out 120
sync frame request 49
synchronization delay 366
synchronization delay registers 366
synchronous FIFO IN data transfer 118
EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F 401
Index
synchronous FIFO reads 107
synchronous FIFO writes 105, 106
synchronous mode 100
T
t0 194
t0_out 194
t1 194
t1_out 194
t2 198
t2_out 198
T2CON register 197
t2ex 198
TCON register 193
TH0 register 193
TH1 register 193
TH2 register 193, 197
Timer 0/1
mode 0 194
mode 1 195
mode 2 196
mode 3 196
modes 193
rate control 197
Timer 1
serial port baud rate generator 205
Timer 2
auto-reload mode 199
baud rate generator mode 200
capture mode 198
timer/counter mode 198
timer/counters 193
TL0 register 193
TL1 register 193
TL2 register 193, 197
TMOD register 193
TOGCTL register 300
tokens and PIDs 14
transaction counter 150
transfer length fields 96
txd0 207
txd1 202, 207
typical GPIF interface 123
U
UART230 register 228
UDMA CRC registers 295–296
UDMA interface 167
UDMA qualifier register 296
UDMA transfers 295
UDMACRCQUALIFIER register 296
UDMACRCx register 295
USB about frames 49
about STALL 42
bus reset 85
control and status register 57, 297
control and status register bit definition 297
control registers 297–304
control transfer 38
default configuration descriptor 368
default device descriptor 367
default interface 0, alternate setting 0 368
default interface 0, alternate setting 1 369
direction 14
error counter limit register 270
frame count registers 301, 302
function address register 304
interrupt enable register 262
interrupt request register 263
interrupt sources 63
interrupts 64
microframe count register 303
requests 39
resume 81
specification 14
suspend 79
transfer types 15
USB frame count low 302
USB frames 15
USB microframe count 303
USBCS register 297
USBERRIE register 268, 269
USBERRIRQ 94
USBFRAMEH register 301
USBFRAMEL register 302
USBIE 91
USBIRQ 91
USB-specific interrupts 63
W
wakeup control and status register 299
wakeup control register 80
wakeup interrupt 81
wakeup/resume sequence 80
WAKEUPCS register 299
WAVEDATA register 219
waveform descriptor structure 136
WORDWIDE bits 125
WU2 function 81
X
XAUTODATx register 282
XGPIFSGLDATH register 353
XGPIFSGLDATL register 354
XGPIFSGLDATLNOX register 355
Z
zero length isochronous data packet 250
402 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *F
Index

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