0117 0257 10_K105 D_Logic_Analyzer_Addendum_68000_Disassembler_Feb84 10 K105 D Logic Analyzer Addendum 68000 Disassembler Feb84

User Manual: 0117-0257-10_K105-D_Logic_Analyzer_Addendum_68000_Disassembler_Feb84

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Publication Number 0117-0257-10
Release 1.0
February 1984

Kl05-D LOGIC ANALYZER
USERS MANUAL ADDENDUM

68000 DISASSEMBLER

Gould Inc., Design &Tes~ Systems Division
4600 Old Ironsides Drive
Santa Clara, CA 95050-1279
Telephone: (408) 988-6800
TWX/TELEX # 910-338-0509

P-2/84

Copyright © 1984. No part
of this publication may be
reproduced without written
permission from Gou!d !nCej
Design and Test Systems
Division. Printed in U.S.A.

CONTENTS

"'.

f'h:::lln+o ....

....."."'"'..,.

Page

INTRODUCTION
INTRODUCTION • • • • • • •
LOADING THE DISASSEMBLER

....... ...

• • • • • • 1-1
• • • • • 1-7

2

SPECIFICATIONS
PHYSICAL DIMENSIONS AND WEIGHT • • • • • • • • • • • • • • • • 2-1

3

DISPLAYS
SCREEN DISPLAYS OF PREPROGRAMMED SET UP MENUS • • • • • • • • 3-1

4

INSTRUCTION SET
68000 INSTRUCTION SET • • • • • • • • • • • • • • • • • • • • 4-1

Figure
1-1
1-2
3-i

3-2
3-3
3-4
3-5

68000 Microprocessor Pinout Diagram. • • • • • • • • • • •
•
Typi ca I RTE to Target System Connection • • •
• •••••••
Oi sassemb;er Data Format Set Up Menu. • • • • • • • • •
• ••
Clock Set Up Menu • • • • • • • • • • • • • • • • • • • • • • • •
Trace Contro I Set Up Menu • • • • • • •
• • • • • • • • • •
Captured Data in Disassembled Format • • • • • • • • • • • • • • •
Expanded , nstruction. • • • • • • • • •
• •••••••••

1-1
1-5
3-1
3-2
3-3
3-4
3-6

iif

Chap"ter 1

I NTROOLCT I ON

I NTROOOCT ION

This addendum provides the user with specific information on the 68000 target
microprocessor Disassembler. Included in the addendum are a microprocessor
pinout diagram, microprocessor-to-Iogic analyzer connection data, screen
displays of the preprogrammed menus, a screen display of captured data in the
disassembled format and special notes on the disassembler/logic analyzer.

04
03
02
01
00
AS
UDS

-LDS

1
2
3
4

•

64
63
62
61

5
6
7

60
59
58

0
0

57

R/W
OTACK
BG
BGACK
BR

9
10
11
12
13
vCC 14
ClK 15
GNO 16
HALT 17
RESET 18
VMA 19
E 20
VPA 21
BERR 22
IPl2 23
IPL1 24
IPlO 25
FC2 26
FC1 27
FCO 28
A1 29
A2 30
A3 31
A4 32

--

--

56
55
54
53
52
51
50

68000

49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

05
06
07
08
09
010
011

Oi2
013
014
015
GNO
A23
A22
A21

VCC
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5

0257-1-1

Figure 1-1. 68000 Microprocessor Pinout 0 i agram

1-1

I NTRODUCT ION

Table 1-1.

Microprocessor-To-logic Analyzer Connection Data

68000
SIGNAL

68000
PIN

K105-0
PIN
ASSIGNMENT

04
03
02
01
DO
AS
UOS
lOS
R/W
OTACK
BG
BGACK
BR

A4
A3
A2
A1
AO
BJ

--

1
2'3
4
5
6
7
8
9
10
11
12
13
..

ClK
GNO
HALT
RESET
VMA
E
VPA
BERR
IPl2
IPl1
IPlO
FC2
FC1
FCO
A1
A2
A3
A4

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

BK
GNO-A-B-C-O SECT IONS

Yvv

1-2

BO

CF
CE

CO
CC
CB
CA
C9
C8
B1
B2
B3
B4

I NTfO)l£TION

Tabie i-i.

Microprocessor-Io-Logic Anaiyzer Connection Data (Cont'd)

68000
SIGNAL
D5
D6
D7
D8
D9
Dl0
D11
D12
D13
D14
D15
GND
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13
A12
All
Al0
A9
A8
A7
A6
A5

68000
PIN
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

Kl05-D
PIN
ASSIGNMENT
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
GND-A-B-C-D SECTIONS
C7
C6
C5
C4
C3
C2
Cl
CO
BF
BE
BD
BC
BB
BA
B9
B8
B7
B6
B5

1-3

I NTROOUCT I ON

ATIACl-IMENT TO A TARGET SYSTEM

Figure 1-2 illustrates a typical RTE to target systeM connection.
* * * * * * * * * * * * * * * * * * * * * * * * *

*
*
*

CAUTION

*
*

In the event the microprocessor on your target*
* system is hard-wired to the board, there is
*
* the possibi lity of inducing reflective noise *
* into the test signals. To eliminate this
*
* problem, we recommend varying the threshold *
*
* vo It age Ieve I s
* * * * * * * * * * * * * * * * * * * * * * * * *
NOTE:

1-4

Figure 1-2 shows one of several possible connections of the RTE to a
target system. As the configuration of the microprocessor pinouts
change, the RTE to target system interface may also change.

INTRODUCTION

Figure 1-2.

Typical RTE

~o Targe~ Sys~em

Connection

The RTE probe connectors are labeled to identify the input probe that Must be
plugged into a specific connector. The user shal I remove the probe tips and
instal I the probes, label up, into the RTE connectors. When connecting the
microprocessor dip-clip cable into the RTE, special attention should be given to
the keyed position of the connectors. The user should also ensure that pin 1 of
the dip-clip is al igned with pin 1 of The microprocessor when connecting to the
target microprocessor.

1-5

I NlROOUCT I ON

LOAD I NG THE DISASSEMBLER

The following procedure provides step-by-step instructions for loading the
Disassembler:
a.

Enter the Disk Operating System screen.

b.

Gently insert the disk into Drive B, with the disk slot toward the rear
of the unit and the label up. Next, lock the disk in p'ace with the
drive latch handle.

c.

Depress function keyF3 to display the B directory.

d.

Depress 1 to select the Recall function.

e.

Use the right arrow cursor to enter the filename field and then use
either the up or down cursor to seJect the Disassembler.

f.

Depress function key F4 to load the Disassembler.

g.

Depress the Format key to enter the' Format screen.

h.

Depress 6 and then Data to enter Disassemb'er mode.

* * * * * * * * * * * * * * * * * *

*
*
*
*
*
*
*
*

CAUTION

*
*
*
*

It is suggested that the user
make a backup copy of the
*
master disk prior to attempting*
use of the disassembler.
*

*

* * * * * * * * * * * * * * * * * *

1-7

Chapter 2

SPEC I FICATIONS

PHYS ICAL DIMENS IONS AND WE IGHT
Height - 2.25 inches (5.7 cm)
Width - 9.5 inches (24.1 cm)
Depth - 5.5 inches (14 cm)
Weight - 1 lb. 14 oz. (.84 kg) with flat cable and device clip

ELECTRICAL DiARACTERI STICS
loading (Signal Inputs)
Input Resistance - 1 megohm +2% to threshold (-1.4 volts)
Input Impedance - 150 ohms (approximate)
Typical Rise/Fal I Distortion - heavi Iy dependent on reserve drive of microprocessor and its support devices. The 68000
microprocessor typically slows 1.5 nanoseconds
on edge rates.

loading (Ground/Reference Input)
Input Resistance - Less than 1 ohm referenced to target system ground.
Ground Difference Immunity - + 0.25 volts between logic analyzer ground and
target system ground.

Reflected Noise Into Target System
Probed with Dip Clip or Circuit Board Socket - heavi Iy dependent on target
system ground. Typically, the system noise is reduced due to slower edge rates
caused by probe load. This condition occasionally masks the problem being
pursued.

2-1

, Chapter 3

DISPLAYS

SCREEN DISPLAYS OF PREPROGRAMMED SET UP MENUS
Figures 3-1 through 3-3 illustrate the preprogrammed setup menus downloaded from
disk to the K105-D. Figures 3-4 and 3-5 illustrate the Disassembled Data and an
Extended Instruction, respectively. When in the Disassembled Data display,
sequential depression of the SHIFT and V keys causes the software version number
for the disassembler to be displayed.

SET UP

MAIN FORMAT

DATA F'ORMAT

RADIX
SECTION

L ADDR

I NPLns

STATUS

DATA

cesses

ecce ecce

AAAA

73F'B73
62EA62
51D951

F'EDCBA99

FB73
EA62
D951
C840

40C940

DATA INPUTS

HRESHOLD

Df'-D8
D7-D0
CF-C8

C7-C0
BF-SS

B7-·E0

FORMATI
MEMOR'T'=t-1 MAIN

Figure 3-1.

1. 4
1. 4

+

1. 4

1. 4
L 4

+ 1. 4
+ 1. 4
+ 1. 4
+ 1. 4

AF-AS
A7-A0
CLOCK INPUTS
~~DATA

+
+
+
+

~~TOP

++++
++++
++ ++

++++
++++
++++
++t+ ++++
++++ + +++
++++ 1++++

+++,+

++,++

++++

++++

THRESHOLD
MAIN=RDY

Disassembler Data Fonmat Set Up Menu

3-1

DISPLAYS

SCREEN DISPLAYS OF PREPROGRAMMED SET UP MENUS (cont'd)

SET UP

MAIN CLOCKS

=

CLOCK SOURCE

-,.._.

=•

MASTER CLOCK

SECTION D

c

-

ON

L ...

lI.ldl.

-.1111
SECTION B - _ i i ON IISliilll
SECTION A - SAMPLE ON H'
SECTION

SAMPLE

ON

•••

EXTERNAL CLOCK COMBINATION DErINITIONS
NAME:

CLOCK INPUT S:

12111··..0

(111+-'+'-'.,

=

<• • • • GII• • ) +

=

<• • • • • • •) + (~.+ID+.)

=

<• • • • • • • ) + (111+111+111+111)

=

(• • • • • • • >+ (11+.+. . . .)

HEMORY=M MAIN

Figure 3-2.

3-2

MAIN=RDY

Clock SeT Up Menu

DISPLAYS

smEEN D I SPLAYS OF PREPROGRAMJED SET UP tENUS

SET UP

(cont' d )

MAIN TRACE

LVL
COMMAND SEQUENCE:
0:TRACE UNTIL
SAMPLE = ENABLE
l:TRACE UNTIL
SAMPLE = TRIGGER
2:LINK ON ENTRY TO LEVEL
TRACE FOR
00508 CLOCKS

PATTERN DEFINITIONS:
NAME:
ADDR
STATUS
00 ENABLE =XXXXXK
XXXXXXXX
01 TRIGGER =XXXXXX
XXXXXXXX
02 _

=XXXXXX

~TOP CMDJ

~~TOP

H£HORY=M MAIN

Figure 3-3.
NOTE:

DATA

XXXX
XXXX

XXXXXXXX

XXXX

PTRN

Trace

MAIN=RDY

Con~rol

Set Up Menu

In disassembler mode, the trace control patterns are formatted into
address, status and data. When the Status field is selected as the
active field, the possible choices are the status conditions of the processor as fol lows:

( 2)
(3 )
(4)
( 5)
(6)

S-PROG-R
U-PROG-R
U-DATA-R
U-DATA-W
U-PROG-W
S-DATA-R
S-DATA-W

(7)

S-PROG-\~

(0 )
(1)

(8) ACK
( 9) INTl
(A) INT2
(8) INT3
(C) INT4
(D) INT5
(E) INT6
(F) INT7

In Edit mode, status bits can be edited on a bit-by-bit bas i s.
selects al I don't-cares.

"X"

3-3

DISPLAYS

SCREEN DISPLAYS OF

PRBPROGR~MED

SET UP MENUS (cont'd)

MC68000 DISASSEMBLER
S=XXXXXX XXXX
FRAME ADDR
OBJECT 'CODE
25 000754 S-DATA-~
26 000756

29 ee991E 46FC2700
31 009922 S-PROG-R
32 009922 21CF0444
34 009926 4FFA000A

35 081444 S-DATA-~
36 080446 S-DATA-W
38 ~~~~~A £l~r~~Ub
40 ee992E 6000F35C

44 008C9C 4Fr90444

41 0004D6 S-DATA-~
42 0004DS S-DATA-W

46 00SC90)4SE7FFFE
48 00SC94 4FF8178A
49 000442
5@ 000440

51

000~3E

S-DATA-~

S-DATA-~

S-DATA-W

52 008430 S-DATA-W

2704

100e
000e

S-DATA-~

27 00007C S-DATA-R
29 08007E S-DATA-R

C

MNEMONIC

CLK=EXT.HLT.

MOVE
NOVE.L

LEA

2

21CF

2
2
2
2

t$2700,SR
A',$444

$A(PC)JA7
0000

2

BRA.L

~

$F35C(PC)
000e

LEA

$444~A7

2
2
2
2

0540

2

9932

HOVEM.L D0/DI/D2/D3/D4/D 2
$78A~A7
2
LEA
0540
2
0000
2
0080

CONTROL=0846
REF=1023
R-C=+ 977
UP ~PG DOWN ~~DSPLY DBJ ~DSPLY MNEMONICS
MEMORY=A MAIN
MAIN=RDY

3-4

2

~/J~4Ub

~~PG

Figure 3-4.

2
2
2

991E

0754
MUV~.L

X
L

Captured Data In Disassembled Fonmat

2

DISPLAYS

NOTES:
1.

After the disassembler data format, and clock select menus of the logic
analyzer are pre-programmed, the trace control selections must be made by
the user before making a recording. The trace control selections determines
exactly which portions of the data stream are recorded or ignored.

2.

The object code or operand of an instruct ion may be too long in some cases
to be displayed on the K105-D screen. In these cases, a greater than symbol
(» is used to mark the code that has been truncated. The user can move the
cursor to the indicated frame, depress the SHIFT key and then the E key to
obtain an instruction expansion on the screen (see Figure 3-5).

3.

When monitoring the 68000 pinout, words with "Program Read" status are being
fetched to be put into the queue. Not al I instruction words fetched are
executed", Instruction words not executed are displayed with the "Program
Read" status. Refer to the ~68000 Users Manua I.

4.

The SEARCH and COMPARE keys are not active in the Data Display Screen. The
Edit mode can be used to change the search word. After leaving Edit mode,
the NEXT and PREVIOUS keys locate target data in memory. If the search word
is not active, the NEXT and PREVIOUS keys update the display to the next or
previous trace level transition.

5.

Depression of the F3 function key changes the display of recorded information. Code is not disassembled, but recorded information is displayed
from the control cursor (C) position to the end of memory as frame number,
address, status and data.
If recorded data is displayed in object format, depressing the F4 function
key invokes the disassembly process for data from the control cursor to the
end of memory.

6.

II legal instructions are displayed as 111.

7.

A Move to SR or CCR causes an extra clock cycle and duplication of the
address and data. See Figure 3-4, frames 31 and 32.

8.

The disassembler is first downloaded from disk to the K105-D and the
disassembler format is selected. Then the trace patterns are configured ,as
desired. It is suggested that the user make a backup copy of the master
disk prior to attempting use of the disassembler.

3-5

DISPLAYS

NC68008 DISASSEMBLER

CLK=EXT. ML T•

INSTRUCTION EXPANSION
FRANE:

46

ADDRESS:

008C90

DEJECT CODE:

48E7 rFFE

MNEMONIC CODE:

MOVEM.L

OPERAND CODE:

D0/Dl;D2/D3/D4/D5~D6/D7/A0/A1/
•.

CONTROL=0046

-~

.... _ -

••••

REF=1023

, .'-"P

•• ...,.....

....."..r

R-C=+ 977

PRESS ANY HEX KEY TO LEAVE EXPANDED DISPLAY
MEHORY=A MAIN
MAIN=RDY

Figure 3-5.

3-6

Expanded Instruction

Chapter 4

I NSTRJCT I ON SET

68000 I NSTRUCT I ON SET
Condition
Mnemonic

Description

Codes

Operation

X N Z V C
ABCD

Add Decimal with Extend

ADD

Add Binary

(Destination) + (Source) -

Destination

.. U .. U ..
.. .. .. .. ..

ADDA

Add Address

(Destination) + (Source) -

Destination

- - - - -

ADDI

Add Immediate

(Destination) + Immediate Data- Destination

ADDQ

Add Quick

(Destination) + Immediate Data- Destination

ADDX

Add Extended

(Destination) + (Source) + X -

AND

AND Logical

!Destination) A (Source) -

ANDI

AND Immediate

!Destination) A Immediate Data -

ASL.ASR

Arithmetic Shift

(Destination) Shifted by  -

BCC

Branch Conditionally
Test a Bit and Change

(Destination) 10 + (Source)1O- Destination

.. .. .. .. ..
.. .. .. .. ..

..

··.
··
·.- · ..

If CC then PC+d- PC

-

-

bit number» OF Destination-Z
- « bit number» OF Destination< bit number> OF Destination

-

-

bit number» OF Destination - Z
0 -  -OF Destination

-

-

Branch Always

PC+d-PC

-

Test a Bit and Set

-«bit number» OF Destination-Z
1 - < bit number> OF Destination

-

-

BSR

Branch to Subroutine

PC-SP@-; PC+d-PC

- -

BTST

Test a Bit

-«bit number» OF Destination-Z

-

-

-

0

Destination

Destination
Destination
Destination

.. ..
-

-

- «

BCHG

BClR
BRA
BSET

1- «

ITest a Bit and Clear

CHK

Check Register against Bounds

If On  «ea» then TRAP

CLR

Clear an Operand

0 - Destination

CMP

Compare

(Destinationi - (Source)

CMPA

Compare Address

(Destination) - (Source)

CMPI

Compare Immediate

(Destination) - Immediate Data

CMPM

Compare Memory

(Destination) - (Source)

DBCC
DIVS

Test Condition. Decrement and Branch

If- CC then Dn-1- On; if Dn* -1 then PC+ d - PC

Signed Divide

(Destination) I (Source) -

Destination

DIVU

Unsigned Divide

(Destination)1 (Source) -

Destination

EOR

Exclusive OR Logical

!Destination). (Source) -

EORI

Exclusive OR Immediate

(Destination) • Immediate Data- Destination

EXG

Exchange Register

Rx-Ry

-

Destination

EXT

Sign Extend

(Destination) Sign-extended- Destination

JMP

Jump

Destination -

JSR

Jump to Subroutine

PC- SP@-; Destination- PC

LEA

Load Effective Address

Destination -

LINK

Link and Allocate

An-SP@-; SP-An; SP+d-SP

LSL. LSR

Logical Shift

(Destination) Shifted by  -

MOVE

Move Data from Source to Destination

(Source) -

PC
An

Destination

MOVE to CCR Move to Condition Code

(Sourcel- CCR

MOVE to SR

(Source)- SR

• affected
- unaffected

Move to the Status Register

o cleared

Destination

·

0

0
0

.-

0
.-

-

-

-

··-

-

·- ·-

-

-

U U U
1 0

0

·.. · ·.. ...
"

"

"

"

·

.. .. .. ..
- - - - - ..
0
- .. .. .. 0
- .. .. 0 0
.. 0 0
- - - - .. 0 0
- - - - - - - - - - - - -

··

·

·

. · ..

-

-

..
.. ..
.. ..

-

-

0 ..
0 0

-

·
··
· ..

..

..

U defined

1 set

4-1

I NSTRUCT I ON SET

68000 I NSTRUCT I ON SET (cant' d )
Condition
Codes
X N Z V C
- - - -

Operation

Description

Mnemonic

MOVE from SR Move from the Status Register

SR -

Destination

-

MOVE USP

Move User Stack Pointer

USP- An; An- USP

-

-

-

Move Address

(Source) -

-

-

MOVEA

-

-

-

-

MOVEM

Move Multiple Registers

Registers- Destination
(Source) - Registers

-

-

-

-

-

MOVEP

Move Peripheral Data

(Source) -

-

-

-

-

-

MOVEQ

Move Quick

Immediate Data -

MULS

Signed Multiply

(Destination)' (Source) -

Destination

-

MULU

Unsigned Multiply

(Destination)'(Source) -

Destination

-

NBCD

Negate Decimal with Extend

0-\Destination)1O- X -

Destination

Destination

Destination

NEG

Negate

0- (Destination) -

NEGX

Negate with Extend

0- (Destination) - X- Destination

NOP

No Operation

-

Logical Complement

-\Destination) -

OR

Inclusive OR Logical

(Destination) v (Source) -

ORI

Inclusive OR Immediate

\Destination) v Immediate Data -

PEA

Push Effective Address

Destination- SP@-

RESET

Reset External Devices

-

ROL, ROR

Rotate (Without Extend)

\Destination) Rotated by

-

\Destination) Rotated by

RTE

SPrn>

RTR

--

-I- -

-

Destination

ROXL, ROXR Rotate with Extend

C::R· C::Pi/V

Destination

-I- -

Destination
Destination

pr

Return and Restore Condition Codes

SP@+ -CC; SP@+-PC

RTS

Return from Subroutine

SP@+ -

SaCD

Subtract Decimal with Extend

\Destination) 10- (Source)1O- X -

SCC
STOP

Set According to Condition

If CC then 1's- Destination else O's- Destination

Load Status Register and Stop

Immediate Data- SR; STOP

SUB

Subtract Binary

\Destination) - (Source) -

Destination

SUBA

Subtract Address

\Destination) - (Source) -

Destination

SUBI

Subtract Immediate

\Destination) - Immediate Data -

SUBQ

Subtract Quick

\Destination) -Immediate Data- Destination

SUBX

Subtract with Extend

(Destination) - (Source) - X- Destination

PC
Destination

Destination

SWAP

Swap Register Halves

Register [31:16]- Register [15:0]

TAS

Test and Set an Operand

\Destination) Tested- CC; 1 - [7] OF Destination

TRAP

Trap

PC-SSP@-; SR-SSP@-; (Vector)-PC

TRAPV

Trap on Overflow

If V then TRAP

TST

Test an Operand

\Destination) Tested -

UNLK

Unlink

An-SP; SP@+ -An

[

] = bit number

• affected
- unaffected

4-2

o cleared
1 set

U defined

CC

0 0
0 0

U

-

··

-

0 0

-

··
··-

-

-

-

-

-

-

-

-

Destination

< count> < count> -

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EXIF Metadata provided by EXIF.tools