03 0027 02_Z80_CPU_Product_Specification_Mar78 02 Z80 CPU Product Specification Mar78
User Manual: 03-0027-02_Z80_CPU_Product_Specification_Mar78
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Z80':CPU Z80A-CPU Product Specification MARCH 1978 multiple level interrupts, unlimited subroutine nesting and simplification of many types of data handling. The Zilog Z80 product line is a complete set of microcomputer components, development systems and support software. The Z80 microcomputer component set includes all of the circuits necessary to build high-performance microcomputer systems ,with virtually no other logic and a minimum number of low cost standard memory elements. The two 16-bit index registers allow tabular data manipulation and easy implementation of relocatable code. The Refresh register provides for automatic, totally transpare'nt refresh of external dynamic memories. The I register is used in a powerful interrupt response mode to form the upper 8 bits of a pointer to a interrupt service address table, while the interrupting device supplies the lower 8 bits of the pointer. An indirect call is then made to this service address. The Z80 and Z80A CPU's are third generation single chip microprocessors with unrivaled computational power. This increased computational power results in higher system through-put and more efficient memory utilization when compared to second generation microprocessors. In addition, the Z80 and Z80A CPU's are very easy to implement into a system because of their single voltage requirement plus all output signals are fully decoded and timed to control standard memory or peripheral circuits_ The circuit is implemented using an N-channel, ion implanted, silicon gate MaS process. FEATURES • Single chip, N-channel Silicon Gate CPU. • 158 instructions-includes all 78' of the 8080A instructions with total software compatibility. New instructions include 4-, 8- and 16-bit operations with more useful addressing modes such as indexed, bit and relative. • 17 internal registers. • Three modes of fast interrupt response plus a nonmaskable interrupt. • Directly interfaces standard speed static or dynamic memories with virtually no external logic. • 1.0 /ls instruction execution speed. • Single 5 VDC supply and single-phase 5 volt Clock. • Out-performs any other single chip microcomputer in 4-, 8-, or 16-bit applications. • All pins TTL Compatible • Built-in dynamic RAM refresh circuitry. Figure 1 is a block diagram of the CPU, Figure 2 details the internal register configuration which contains 208 bits of Read/Write memory that are accessible to the programmer. The registers include two sets of six general purpose registers that may be used individually as 8-bit registers or as 16-bit register pairs. There are also two sets of accumulator and flag registers. The programmer has access to either set of main or alternate registers through a group of exchange instructions. This alternate set allows foreground/ background mode of operation or may be reserved for very fast Interrupt response. Each CPU also contains a 16-bit stack pointer which permits simple implementation of a-BIT DATA BUS , 13 CPU AND SYSTEM ~:;'~}:L~L \:"~Hi%:1 MAIN REG SET ALTERNATE REG SfT v ACCUMULATOR A fLAGS F ACCUMULATOR A' FLAGS F' B C B' C' D E D' E' H L H' L' INTERRUPT MEMORY REFRESH !i!:;!!'!'{i;;g;'T;;;HTH;;';;H; VECTOR I :L!!ii;ijI' R INDEX REGISTER IX INDEX REGISTER IV STACK POINTER SP SPECIAL PURPOSE rrr PROGRAM COUNTER REGISTERS PC iHi1f.iiiiU3i,;;;;V +5V GNO 'I' 16-81T ADDRESS BUS Z80, Z80A CPU REGISTERS Z80, Z80A CPU BLOCK DIAGRAM 1 " ] GENERAL PURPOSE REGISTERS Z80, Z80A-CPU Pin Description "0 A, A, A3 A, Ml MREQ SYSTEM CONTROL { 19 20 !.::RQ RD ViR RFSH RFSH (Refresh) Output, active low. RFSH indicates that the lower 7 bits of the address bus contain a refresh address for dynamic memories and the current MREQ signal should be used to do a refresh read to all dynamic memories. HALT (Halt state) Output, active low. HALT indicates that the CPU has executed a HALT software instruction and is awaiting either a nonmask able or a maskable interrupt (with the mask enabled) before operation can resume. While halted, the CPU executes NOP's to maintain memory refresh activity. WAIT (Wait) Input, active low. WAIT indicates to the Z-80 CPU that the addressed memory or I/O devices are not ready for a data transfer. The CPU continues to enter wait states for as long as this signal is active. INT (Interrupt Request) Input, active low. The Interrupt Request signal is generated by I/O devices. A request will be honored at the end of the current instruction if the internal software controlled interrupt enable flip-flop (IFF) is enabled. NMI (Non Maskable Interrupt) Input, active low. The non-maskable nterrupt request line has a higher priority than INT and is always recognized at the end of the current instruction, independent of the status of the interrupt enable flip-flop. NMI automatically forces the Z-80 CPU to restart to location 0066H' RESET Input, active low. RESET initializes the CPU as follows: reset interrupt enable flip-flop, clear PC and registers I and R and set interrupt to 8080A mode. During reset time, the address and data bus go to a high impedance state and all control output signals go to the inactive state. BUSRQ (Bus Request) Input, active low. The bus request signal has a higher priority than NMI and is always recognized at the end of the current machine cycle and is used to request the CPU address bus, data bus and tri-state output control signals to go to a high impedance state so that other devices can control these busses. BUSAK (Bus Acknowledge) Output, active low. Bus acknowledge is used to indicate to the requesting device that the CPU address bus, data bus and tri-state control bus signals have been set to their high impedance state and the external device can now control these signals. AS A, " A7 ADDRESS AS BUS A, HALT AIO WAIT { CPU CONTROL ~ NM' RESET ZBO-CPU Z80A·CPU A" A" A" A14 A" CPU {BUSAa BUS CONTROL BUSAK 'SV GND Z80, Z80A CPU PIN CONFIGURATION AO-A15 (Address Bus) Tri-state output, active high. AO-A15 constitute a 16-bit address bus. The address bus provides the address for memory (up to 64K bytes) data exchanges and for I/O device data exchanges. DO-D7 (Data Bus) Tri-state input/output, active high. DO - D7 constitute an 8-bit bidirectional data bus. The data bus is used for data exchanges with memory and I/O devices. Ml (Machine Cycle one) Output, active low. M1 indicates that the current machine cycle is the OP code fetch cycle of an instruction execution. MREQ (Memory Request) Tri-state output, active low. The memory request signal indicates that the address bus holds a valid address for a memory read or memory write operation. 10RQ (Input/ Output Request) RD (Memory Read) WR (Memory Write) Tri-state output, active low. The 10RQ signal indicates that the lower half of the address bus holds a valid I/O address for a I/O read or write operation. An 10RQ signal is also generated when an interrupt is being acknowledged to indicate that an interrupt response vector canbe placed on the data bus. Tri-state output, active low. RD indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O device or memory should use this signal to gate data onto the CPU data bus. Tri-state output, active low. WR indicates that the CPU data bus holds valid data to be stored in the addressed memory or I/O device. 2 Timing Waveforms INSTRUCTION OP CODE FETCH The program counter content (PC) is placed on the address bus immediately at the start of the cycle. One half clock time later MREQ goes active. The falling edge of . MREQ can be used directly as a chip enable to dynamic memories. RD when active indicates that the memory data should be enabled onto the CPU data bus. The CPU samples data with the rising edge of the clock state T3. Clock states T3 and T 4 of a fetch cycle are used to refresh dynamic memories while the CPU is internally decoding and executing the instruction. The refresh control signal RFSH indicates that a refresh read of all dynamic memories should be accomplished. -,AD"" A15 4JL-':":'---+---l-A-~==r-:="---!A---+- L ______ co- 01 _ IN MEMORY READ OR WRITE CYCLES Illustrated here is the timing of memory read or write than an OP code fetch (M 1 cycle). The MREQ and RD signals are used exactly as in the fetch cycle. In the case of a memory write cycle, the MREQ also becomes active when the address bus is stable so that it can be used directly as a chip enable for dynamic memories. The WR line is active when data on the data bus is stable so that it can be used directly as a R/W pulse to virtually any type of semiconductor memory. cycl~ther -,AD .... A15 DATA OUT IN 00-07 WAIT -=-____- :IL-_- - INPUT OR OUTPUT CYCLES Illustrated here is the timing for an I/O read or I/O write operation. Notice that during I/O operations a single wait state is automatically inserted (Tw*). The reason for this is that during I/O operations this extra state allows sufficient time for an I/O port to decode its address and activate the WAIT line if a wait is required. -~~~ ~ -,. PORT ADDRESS AD .... A7 } -1---- --- ------ 00"" 07 ...d Cvcle ...!!:!.., 00-0,' ---- --:,---c: -----OUT ~ INTERRUPT REQUEST/ACKNOWLEDGE CYCLE The interrupt signal is sampled by the CPU with the rising edge of the last clock at the end of any instruction. When an interrupt is accepted, a special M1 cycle is generated. During this M 1 cycle, the IORQ signal becomes active (instead of MREQ) to indicate that the interrupting device can place an 8-bit vector on the data bus. Two wait states (Tw*) are automatically added to this cycle so that a ripple priority interrupt scheme, such as the one used in the Z80 peripheral controllers, can be easily implemented. Last M C y c l e _ - - I - o _ _ - - - - - - M ' - - - - - - - - - o f Instruction AO"" A15 ~===t:==:t:x==::t:::::JPC~:::t===~==~E '.E~F.~EESH lORD ,....,-1}..-- 00- 07 WAIT 3 -.....;; -_ --------r----r----~----,,--r------- - - - _____1-_ _ _ _ 1-____ J L_ - - __ Z80, Z80A Instruction Set d dd e - The following is a summary of the Z80, Z80A instruction set showing the assembly language mnemonic and the symbolic operation performed by the instruction. A more detailed listing appears in the Z80-CPU technical manual, and assembly language programming manual. The instructions are divided into the following categories: 8-bit loads Miscellaneous Group 16-bit loads Rotates and Shifts Exchanges Bit Set, Reset and Test Memory Block Moves Input and Output Memory Block Searches Jumps 8-bit arithmetic and logic Calls 16-bit arithmetic Restarts General purpose Accumulator Returns & Flag Operations any 8-bit destination register or memory location any 16-bit destination register or memory location 8-bit signed 2's complement displacement used in relative jumps and indexed addressing L 8 special call locations in page zero. In decimal notation these are 0, 8, 16, 24,32,40, 48 and 56 n - any 8-bit binary number nn any 16-bit binary number r any 8-bit general purpose register (A, B, C, D, E, H, or L) s - any 8-bit source register or memory location a bit in a specific 8-bit register or memory location sb ss any 16-bit source register or memory location subscript "L" == the low order 8 bits of a 16-bit register subscript "H" == the high order 8 bits of a 16-bit register In the table the following tenninology is used. () b cc == the contents within the ( ) are to be used as a pointer to a memory location or I/O port number 8-bit registers are A, B, C, D, E, H, L, I and R 16-bit register pairs are AF, BC, DE and HL 16-bit registers are SP, PC, IX and IY a bit number in any 8-bit register or memory location flag condition code NZ non zero Z zero NC non carry C carry PO Parity odd or no over flow PE Parity even or over flow P Positive M Negative (minus) Addressing Modes implemented include the following: Immediate Immediate extended Modified Page Zero Relative Extended combinations of Indexed Register Implied Register Indirect Bit Mnemonic Symbolic Operation Comments Mnemonic Symbolic Operation LD r, s r +- s s == r, n, (HL), (IX+e) , (IY+e) LDI LD d, r d+-r d==(HL),r (IX+e) , (IY+e) LDIR LDd,n d+-n d == (HL), (IX +e), (IY+e) (DE) +- (HL), DE +- DE+l HL +- HL+l, BC +- BC-l (DE) +- (HL), DE +- DE+ 1 HL +- HL+l, BC +- BC-l Repeat until BC = 0 (DE) +- (HL), DE +- DE-l HL +- HL-l, BC +- BC-l (DE) +- (HL), DE +- DE-l HL +- HL-l, BC +- BC-l Repeat until BC = 0 LDA,s A+- s LDd,A d+-A LD dd, nn dd +- nn LD dd, (nn) dd +- (nn) LD (nn), ss (nn) +- ss LD SP, ss PUSH ss SP +- ss (SP-l) +- sSH; (SP-2) +- sSL POPdd dd L +- (SP); dd H +- (SP+l) EX DE,HL EX AF,AF' EXX DE AF EX (SP), ss LDD s == (BC), (DE), (nn), I, R d == (BC), (DE), (nn), I, R LDDR dd == BC, DE, HL, SP, IX, IY dd == BC, DE, HL, SP, IX, IY ss== BC, DE, HL, SP, IX, IY SS = HL, IX, IY ss = BC, DE, HL, AF, IX, IY dd = BC, DE, HL, AF, IX, IY HL <+ AF' <+ (BC) (BC) DE <+ DE' HL HL' (SP) H ssu (SP+ I) B sSH ss == HL, IX, IY 4 CPI A-(HL), HL +- HL+l BC +- BC-l CPIR A-(HL), HL +- HL+l BC +- BC-l, Repeat until BC = 0 or A = (HL) CPD A-(HL), HL +- HL-l BC +- BC-l CPDR A-(HL), HL +- HL-l BC +- BC-1, Repeat until BC= 0 or A = (HL) ADDs ADC s SUB s SBC s ANDs ORs XORs A+-A+s A +- A + S + CY A+-A-s A +- A - s - CY A+-Al\s A+-AVs A+-AEllS Comments A-(HL) sets the flags only. A is not affected CY is the carry flag s == r, n, (HL) (IX +e), (IY+e) Mnemonic Symbolic Operation Comments Mnemonic Symbolic Operation Comments CP s A- s s = r, n (HL) (IX+e), (IY+e) BIT b, s SET b, s Z~Sb d = r, (HL) (IX+e), (IY+e) RES b, s Z is ze ro flag s = r, (HL) (IX+e), (IY+e) INC d DECd d ~d+ 1 d ~ d-I HL~HL+ss ADDHL, ss ADC HL,ss SBC HL, ss ADD IX, ss HL ~ HL + ss + CY HL ~ HL - ss - CY IX ~ IX + ss ADD IY, ss IY ~ IY + ss INC dd dd ~ dd + 1 DEC dd dd ~dd DAA Converts A contents into packed BCD following add or sub tract. ss=BC, DE, IX, SP ss=BC, DE, IY, SP INI (HL) ~(C),HL ~ HL + 1 B~B -1 INIR (HL) ~(C),HL ~ HL + 1 B~B -1 Repeat until B = 0 IND OUTen), A OUT(C), r (HL) ~(C),HL ~ HL - 1 B~B -1 (HL) ~(C), HL ~ HL - 1 B~ B-1 Repeat until B = 0 (n) ~A (C)~ r Operands must be in packed BCD format OUTI (C)~ OTIR - CPL NEG CCF SCF A~A A~OO-A OUTD CY~CY CY~ NOP HALT DI EI 1M 0 1M 1 1M 2 RLCs 1 OTDR No operation Halt CPU Disable Interrupts Enable Interrupts Set interrupt mode 0 Set interrupt mode 1 Set interrupt mode 2 8080Amode Call to 0038H Indirect Call L&=l7_0~ RL s s S ~7_0~ s RRs [g--/7 _ ol--u s SRAs SRLs RLD RRD s = r, (HL) (IX+e), (IY+e) cS7°~ o~ s 1\ 413 ~ ~ 71(HL) 17 A413 ~ ~ ~ ol(HL) NC C JP (ss) DJNZ e PC ~ss B ~ B-1, if B = 0 continue, else PC ~ PC + e ss = HL, IX, IY CALL nn (SP-I) ~ PC H (SP-2) ~ PCL> PC ~ nn If condition cc is false continue, else same as CALLnn If condition cc is true PC ~ nn, else continue cc PC~PC+e RSTL (SP-I) ~PCH (SP-2) ~ PCL' PC H ~ 0 PCL ~L RET PCL ~(SP), PC H ~(SP+l) If condition cc is false continue, else same as RET RETcc 5 PC~nn kk{~Z s SLAs (HL), HL+ HL + 1 B ~B-l (C)~ (HL), HL ~ HL + 1 B ~ B-1 Repeat until B = 0 (C)~ (HL), HL ~ HL - 1 B~B -1 (C)~ (HL), HL ~ HL - 1 B ~B-l Repeat until B = 0 If condition kk is true PC ~ PC + e, else continue CALL cc, nn ~7_0~ Set flags rz~C JRe JRkk, e ~7~OiJ r ~(C) PO PE P M JP nn JP cc, nn s RRC A~(n) INDR dd =BC, DE, HL, SP, IX, IY dd =BC, DE, HL, SP, IX, IY - 1 IN A, Cn) IN r, (C) },,: BC, DE HL,SP sb ~ 1 sb ~O RETI Return from interrupt, same as RET RETN Return from nonmaskable interrupt cc rz~C PO PE P M cc rz~c PO PE P M Z80-CPU A.C. Characteristics TA = oOe to 70 0e, Vee = +5V ± 5%, Unless Otherwise Noted. Signal 4> Ao-15 DO_7 Symbol Parameter Min Max Unit Ic Iw (4)H) Iw «I>Ll Ir.f Clock ("lock Clock ("lock .4 180 180 1121 [E) 2000 30 .usee ID(AD) IF(AD) tea teal' Address Oulput Delay Delay 10 Floal Address Slable Prior 10 MREO (Memory Cycle) Address Slable Prior 10 10RO. RD or WR (I/O Cyde) Address Slable from RIJ, IORQ or MREQ Address Sloble From RD or WR During Floal ID(D) IF(D) IS(D) ISi"(D) tdem Idci Icdf Dala OulpUI Delay Delay 10 Floal During Wrile Cyde Dala Selup Time 10 Rising Edge of ("lock During M I Cyde Dala Selup Time 10 Falling Edge of Clock During M2 10 MS Dala Slable Prior 10 WR (Memory Cyeie) Dala Slable Prior 10 WR (1/0 Cyeie) Dala Slable From WR taclll taei Period Pulse Widlh. ("lock High Pulse Widlh. Clock Low Rise ond Fall Time 145 110 13 Wb nsec osec nsec osec osec nsec osec III Test Condition CL = 50pF [I) lacm = 1w(H) + If-75 osec [2) laci = tc -80 osec osec [3) lea = 1w(L) + Ir - 40 [4) leaf= 1w(L) + Ir - 60 [5) tdcm = tc - 210 [6) tdci = tw(4)L) [7) tcdf= tw(4)L) + tr-80 [8) Iw (MRL) = Ic - 40 [9) Iw(MRH) = 1w(H) + If - 30 osec 141 230 ~u osec nsec ~u 60 15 16 171 C L = 50pF osec osec IH Any Hold Time for Selup Time IDLi" (MR) IDH (MR) IDHi"(MR) Iw(MRL) Iw(MRH) MREO Delay From Falling Edge of Clock, MREO Low MREO Delay From Rising Edge of Clock, MREO High MREO Delay From Falling Edge of Clock, MRE'jHigh Pulse Widlh, MREO Low Pulse Widlh, MREO High 10RO IDL (IR) IDLij;(lR) IDH (IR) IDHi"(1R) 10RO Delay 10RO Delay 10RO Delay 10RO Delay RD IDL (RD) IDLij;(RD) IDH (RD) IDHi" (RD) RD RD RD RD Rising Edge of Clock, RD Low Falling Edge of Clock, RD Low Rising Edge of Clock, RD High Falling Edge of Clock, RD High 100 130 100 osec osec lIu "sec IDL (WR) IDLi"(WR) tDHi"(WR) Iw(WRL) WR Delay From Rising Edge of Clock, WR Low WR Delay From Falling Edge of Clock, WR Low WR Delay Fr~ Falling Edge of Clock, WR High Pulse Width, WR Low 80 90 100 osec osec osec osec MI IDL(MI) tDH(MI) M I Delay From Rising Edge of Clock, M I Low MI Delay From Rising Edge of Clock, MI High 130 130 osec osec C L = 50pF RFSH tDL(RF) tDH(RF) RFSH Delay From Rising Edge of Clock, ~ Low RFSH Delay From Rising Edge of Clock, RFSH High 180 150 osec osec C L =50pF WAIT Is(WT) WAIT Selup Time 10 Falling Edge of Clock HALT ID(HT) HALT Delay Time From Falling Edge of Clock INT MREO WR Delay Delay Delay Delay From From From From From From From From osec 0 100 100 100 18 191 Rising Edge of Clock, 10RO Low Falling Edge of Clock, 10RO Low Rising Edge of Clock, IORO High Falling Edge of Clock, 10RO High [101 osec osec osec osec C L = 50pF osec osec osec osec osec C L = 50pF C L = 50pF CL = 50pF nsec 70 300 osec IS (IT) INT Selup Time 10 Rising Edge of Clock 80 osec NMI Iw(NML) Pulse Widlh, NMI Low 80 osec BUSRO IS (BO) BUSRO Selup Time 10 Rising Edge of Clock 80 osec BUSAK IDL(BA) IDH(BA) BUSAK Delay From Rising Edge of Clock, BUSAK Low BUSAK Delay From Falling Edge of Clock, BUSAK High RESET IS (RS) .RESET Selup Time 10 Rising Edge of Clock IF(C) Delay 10 Floal (MREO, 10RO, RD and WR) Imr Mi 120 110 90 osec osec CL = 50pF C L = 50pF osee 100 1111 osec osec [II] Imr = 21c + Iw(H) + If - 80 NOTES: A. Dala should be enabled onlo Ihe CPU dalO bus when RD is active. During inlerrupl acknowledge dala should be enabled when Mi and 10RO ore bOlh aClive. B. All control signals are internally synchronized, so they may be totally asynchronous with resp~ct 10 Ihe clock. C. The RESET signal must be active for a minimum of 3 clock cycles. D. OUlpul Delay .s. Loaded Capacilance TA = 70°C Vcc = +5V ±5% E. Add 10nsec delay for each 50pf increase in load up to a maximum of 200pf for the data bus & lOOpf for address & control lines Allhough sIalic by design. lesting guaranlees 1w(H) of 200 j.lsec maximum 6 210 osec 90 110 100 110 Slable Prior 10 IORO (lnlerrupl Ack.) + tr - R.- 2.1 KQ TEST POINT = Load circuil for OulpUI A.C. Timing Diagram Timing measurements are made at the following' voltages, unless otherwise specified: "0" "I" CLOCK OUTPUT INPUT FLOAT _IC_ ~ Vee -.6V .4SV 2.0 V 2.0 V I!. V .8V .8V ±O.S V H W ....J f---l tw «I>\.) --== .. - A O-A15 10 (AD) AO- 15 --- ~~ Jd----It-.....I""I'r-----t"'"' - p ----- ---r-:x ,~--- H~-- -----", ';, IN .. --- _=- 10 (D) 00-1 { -')t, OUT t---+-1~IOL (M1) ~~ ___ ~r------+-+-." r- ~ ---Iac-mi-+t!l. H'OL'T' RD ---~N ---~HM_~~- ~.~:!:.}MR(pr _ tOL;j". IMlRII II (R~: •• IOH.i. (MRl-- V~ (r\-_ _ _-+'I (( I OH'f> (MR)- V-""'""""'"'M-_~(rrlr-+-_I+II_--+...,. IW (MRL) ++-__-H_ _+-__- + +__+--t~O..:.L;-~i.(WR) WR I_ lORa r-- tmr - tOH.I. (lR)- tOL·i. (lR) r=1r---ti---r----+~__~~...... ~r--"". . -~~ tOH'f> ~R):- tTi(RO)- RD IOL'i' (WR) ~ -------~---------H_-~---~_+~ ~~ ~ I---I~ 10H (RDI- 11 _ _ _H-__ II'_ _ _ _ _ _ _ _+ ~-- I I. :=-ItW~MRH) tOH ClOck Capacitance 35 pF CIN Input Capacitance 5 pF COUT Output Capacitance 10 pF Z80-CPU Ordering Information C P S E M- Ceramie Plastic Standard 5 V ± 5% 0° too 70 0 C ° Extended 5V ±5% -40 to 85 C Military 5V ±10% _55 0 to 125°C T A = 25°(, f = I MHz. unmeasured pins returned to ground Max. Supply Symbol Capacitance Z80A-CPU D.C. Characteristics Parameter Icc = 200 rnA Capacitance Z80-CPU D.C. Characteristics Symbol For ZSO-CPU all AC and DC characteristics remain the same for the military grade parts except Icc. CC ~.4 90 200 Test Condition III A 8 Symbol Parameter Max. Unit (',~ ell,)I":" CapJI.'llarh:l' 35 pF ('IN Input '; pc eOl Il Output 10 pF CapJI.'lIJlh:l' Clpa(IIJIl\.'l' Z80A-CPU Ordering Information C - Ceramic P - Plastic S - Standard 5V ±S% 0° to 70°C A.C. Characteristics TA = oOe to 70°C, Vee Z80A-CPU = +5V ± 5%, Unless Otherwise Noted. [1] laem = Iw(4>H) + If - 65 [2] I,ei = Ie -70 [3] tea = tw(L) + tr - 50 [4] leaf = tw(4)L) + Ir -45 [5] tdem = tc - 170 [6] tdci = tw(L) + tr -170 [7] tcdf = tw(L) + tr - 70 [8] Iw (MRL) = Ie - 30 [9] Iw(MRH) = Iw(4>H) + If - 20 [10] tw(WRL) NOTES: TEST POINT A. Data should be enabled onlo Ihe CPU dala bus when Ri5 is active. During interrupt acknowledge data should be enabled when iiI and IORQ are bolh aclive. B. All control signals are internally synchronized, so they may be totally asynchronous with respect 10 Ihe clock. C. The RESET signal must be aclive for a minimum of 3 clock cycles. D. Oulpul Delay vs. Loaded Capacitance TA = 70°C Vee = +5V ±5% Add 10nsec delay for each 50pf increase in load up to maximum of 200pf for data bus and 100pf for address & control lines. E. Allhough sIalic by design, lesling guaranlees 1w(4)H) of 200 p.sec maximum 9 = Load circuit for OUlpUI =tc -30 Package Configuration A11 A12 A 13 A14 A 15 40 39 38 37 36 35 34 33 32 3 4 6 04 03 05 06 +5V O2 07 Z·80A 13 CPU· DO 01 INT MREQ IORQ 18 19 20 23 22 21 Package Outline I~:::::::g::::::::1 A 10 A9 A8 A7 A6 A5 A4 Aa A2 Al AD GNO RFSH Ml RESET BUSRQ WAIT BUSAK WR 0.02LIN 10.05081 .0151.03811 _ .023 1.05841 II I _ . -. RD I-- .0901.22861 .1001.2541 TYP. .51411.30561 .58811.49351 I .230 MAX 1.58421 I J ! .1001.2541 '"i5O"13siT ". ~ , ~ .59011.49861 _I .71011.80341 * Dimensions for metric system are in parentheses ZILOG U.S. DISTRJ[BUTORS EASTERN Hallmark Electronics 4739 Commercial Drive Huntsville, AL 35805 TEL 205 8378700 TWX 810726 2187 Hallmark Electronics 1302 West McNab Road Fort Lauderdale, FL 33309 TEL 305 971 9280 TWX 510956 9720 Hallmark Electronics 7233 Lake Ellenor Drive Orlando, FL 32809 TEL 305 855 4020 TWX 8108500183 Hallmark Electronics 3355 Amberton Drive Baltimore MD 21227 TEL 301 796 9300 TWX 710862 1942 Hallmark Electronics 1208 Front Street Building K Raleigh, NC 27609 TEL 919 8324465 TWX 5109281831 Hallmark Electronics Pike Industrial Park Huntington Valley, PA 19006 TEL 215 355 7300 TWX 5106671750 Summit 916 Main Street Buffalo, NY 14202 TEL 716 884 3450 Wilshire Electronics 2554 State Street Hamden, CT 06517 TEL 203 281 1166 TWX 800 922 1734 Hallmark Electronics 13789 Rider Trail Earth City, MO 63045 TEL 3142915350 TWX 9107600671 RM Electronics 47 Chestnut Lane Westmont, Illinois 60559 TEL 312 323 9670 R. V. Weatherford Co. 1550 Babbitt Avenue Anaheim, CA 92805 TEL 7146349600 TWX 910593 1334 Wilshire Electronics 1855 New Highway Farmingdale, LI, NY 11735 TEL 5162935775 TWX 212895 8707 Wilshire Electronics One Wilshire Road Burlington, MA 01803 TEL 617 272 8200 TWX 710 332 6359 Hallmark Electronics 6969 Worthingtoll Galena Road Worthington,OH 43085 TEL 6148461882 MOUNTAIN R.V. Weatherford Co. 1095 East Third Street Pomona, CA 91765 TEL 714623 1261 TWX 9105813811 Hallmark Electronics 4846 S. 83rd E. Avenue Tulsa, OK 74145 TEL 918835 8458 TWX 910845 2290 Hallmark Electronics 3100-A Industrial Terrace Austin, TX 78758 TEL 5128372841 TWX 9108742031 Hallmark Electronics 9333 Forest Lane Dallas, TX 75231 TEL 214 234 7300 TWX 9108674721 Wilshire Electronics 1111 Paulison Avenue Clifton, NJ 07015 TEL 201 340 1900 TWX 7109897052 MIDWESTERN Hallmark Electronics 180 Grossen Avenue Elk Grove Village, IL 60076 TEL 3124378800 TWX 9102233645 WESTERN Intermark Electronics 1802 E. Carnegie Avenue Santa Ana, CA 92705 TEL 714540 1322 TWX 910595 1583 Intermark Electronics 4040 Sorrento Valley Blvd. San Diego, CA 92121 TEL 714 279 5200 7144539005 TWX 910335 1515 Hallmark Electronics 8000 Westglen Houston, TX 77063 TEL 713 7816100 TWX 9108812711 Hallmark Electronics 11870 West 91st Street Congleton Industrial Park Shawnee Mission, KS 66214 TEL 9138884747 TWX 9107496620 Hallmark Electronics 9201 Penn Avenue South Suite 10 Bloomington, MN 55435 TEL 6128849056 TWX 9105763187 Century Electronics 121 Elizabeth, NE Albuquerque, NM 87123 TEL 505 292 2700 TWX 9109890625 Intermark Electronics 1020 Stewart Drive Sunnyvale, CA 94086 TEL 408738 1111 TWX 9103399312 Hallmark Electronics 237 Sou th Curtis West Allis, WI 53214 TEL 414476 1270 TWX 9102623186 R. V. Weatherford Co. 6921 San Fernando Road Glendale, CA 91201 TEL 213 8493451 TWX 910498 2223 RM Electronics 4860 South Division Kentwood, MI 49508 TEL 616 531 9300 TWX 810 273 8779 R.V. Weatherford Co. 3240 Hillview Avenue Stanford Industrial Park Palo Alto, CA 94304 TEL 4154935373 R. V. Weatherford Co. 3311 W. Earll Drive Phoenix, AZ 85017 TEL 602 272 7144 TWX 9109510636 Sterling Electronics 5608 6th Avenue South Seattle, WA 98108 TEL 206 7629100 TLX 32-9652 Western Microtechnology 977 Benicia Avenue Sunnyvale, CA 94086 TEL 4087371660 CANADA Future Electronics 5647 Ferrier Street Montreal, Quebec, CANADA H4P 2K5 TEL 5147355775 TWX 6104213251 ZIJLOG SALlES OFFICES EASTERN REGION Zilog, Inc. 76 Treble Cove Road No. Billerica, MA 01862 TEL 617667 2179 TWX 7103476660 MIDATLANTIC REGION Zilog, Inc. P.O. Box 92 Bergenfield, NJ 07625 TEL 201 385 9158 TWX 7109919771 10460 Bubb Road, Cupertino, California 95014 03-0027-02 MIDWESTERN REGION Zilog, Inc. 1701 Woodfield Place Suite 417 Schaumburg,IL 60195 TEL 312 8858080 TWX 910 291 1064 SOUTHWESTERN REGION Zilog, Inc. 17982 Sky Park Circle Suite C Irvine, CA 92714 TEL 714 549 2891 TWX 910 5952803 Telephone: (408) 446-4666 EUROPEAN HDOTS Zilog (UK) Ltd. Nicholson House Maidenhead, Berkshire England TEL (0628) 36131/2/3 TWX 848 609 1WX: 910-388-7621 Printed in U.S.A. Copyright ©1977 by Zilog. Inc.
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