03 Cortex A Programmer Guide
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- ARM Cortex-A Series Programmer’s Guide
- Contents
- Preface
- 1: Introduction
- 2: ARM Architecture and Processors
- 2.1 Architectural profiles
- 2.2 Architecture history and extensions
- 2.2.1 DSP multiply-accumulate and saturated arithmetic instructions
- 2.2.2 Jazelle
- 2.2.3 Thumb Execution Environment (ThumbEE)
- 2.2.4 Thumb
- 2.2.5 Thumb-2
- 2.2.6 Security Extensions (TrustZone)
- 2.2.7 VFP
- 2.2.8 Advanced SIMD (NEON)
- 2.2.9 Coprocessors
- 2.2.10 Large Physical Address Extension (LPAE)
- 2.2.11 Virtualization
- 2.2.12 big.LITTLE
- 2.3 Processor properties
- 2.4 Cortex-A series processors
- 2.5 Key architectural points of ARM Cortex-A series processors
- 3: ARM Processor Modes and Registers
- 4: Introduction to Assembly Language
- 5: ARM/Thumb Unified Assembly Language Instructions
- 6: Floating-Point
- 7: Introducing NEON
- 8: Caches
- 8.1 Why do caches help?
- 8.2 Cache drawbacks
- 8.3 Memory hierarchy
- 8.4 Cache architecture
- 8.5 Cache policies
- 8.6 Write and Fetch buffers
- 8.7 Cache performance and hit rate
- 8.8 Invalidating and cleaning cache memory
- 8.9 Point of coherency and unification
- 8.10 Level 2 cache controller
- 8.11 Parity and ECC in caches
- 9: The Memory Management Unit
- 10: Memory Ordering
- 11: Exception Handling
- 12: Interrupt Handling
- 13: Boot Code
- 14: Porting
- 15: Application Binary Interfaces
- 16: Profiling
- 17: Optimizing Code to Run on ARM Processors
- 17.1 Compiler optimizations
- 17.2 ARM memory system optimization
- 17.2.1 Data cache optimization
- 17.2.2 Loop tiling
- 17.2.3 Loop interchange
- 17.2.4 Structure alignment
- 17.2.5 Associativity effects
- 17.2.6 Optimizing instruction cache usage
- 17.2.7 Optimizing L2 and outer cache usage
- 17.2.8 Optimizing TLB usage
- 17.2.9 Data abort optimization
- 17.2.10 Prefetching a memory block access
- 17.3 Source code modifications
- 18: Multi-core processors
- 18.1 Multi-processing ARM systems
- 18.2 Symmetric multi-processing
- 18.3 Asymmetric multi-processing
- 18.4 Heterogeneous multi-processing
- 18.5 Cache coherency
- 18.6 TLB and cache maintenance broadcast
- 18.7 Handling interrupts in an SMP system
- 18.8 Exclusive accesses
- 18.9 Booting SMP systems
- 18.10 Private memory region
- 19: Parallelizing Software
- 20: Power Management
- 21: Security
- 22: Virtualization
- 23: big.LITTLE
- 24: Debug
- A: Instruction Summary
- A.1 Instruction Summary
- A.1.1 ADC
- A.1.2 ADD
- A.1.3 ADR
- A.1.4 ADRL
- A.1.5 AND
- A.1.6 ASR
- A.1.7 B
- A.1.8 BFC
- A.1.9 BFI
- A.1.10 BIC
- A.1.11 BKPT
- A.1.12 BL
- A.1.13 BLX
- A.1.14 BX
- A.1.15 BXJ
- A.1.16 CBNZ
- A.1.17 CBZ
- A.1.18 CDP
- A.1.19 CDP2
- A.1.20 CHKA
- A.1.21 CLREX
- A.1.22 CLZ
- A.1.23 CMN
- A.1.24 CMP
- A.1.25 CPS
- A.1.26 DBG
- A.1.27 DMB
- A.1.28 DSB
- A.1.29 ENTERX
- A.1.30 EOR
- A.1.31 ERET
- A.1.32 HB
- A.1.33 ISB
- A.1.34 IT
- A.1.35 LDA
- A.1.36 LDAB
- A.1.37 LDAEX
- A.1.38 LDAEXB
- A.1.39 LDAEXD
- A.1.40 LDAEXH
- A.1.41 LDAH
- A.1.42 LDC
- A.1.43 LDC2
- A.1.44 LDM
- A.1.45 LDR
- A.1.46 LDR (pseudo-instruction)
- A.1.47 LDRD
- A.1.48 LDREX
- A.1.49 LEAVEX
- A.1.50 LSL
- A.1.51 LSR
- A.1.52 MCR
- A.1.53 MCR2
- A.1.54 MCRR
- A.1.55 MCRR2
- A.1.56 MLA
- A.1.57 MLS
- A.1.58 MOV
- A.1.59 MOVT
- A.1.60 MOV32
- A.1.61 MRC
- A.1.62 MRC2
- A.1.63 MRRC
- A.1.64 MRRC2
- A.1.65 MRS
- A.1.66 MSR
- A.1.67 MUL
- A.1.68 MVN
- A.1.69 NOP
- A.1.70 ORN
- A.1.71 ORR
- A.1.72 PKHBT
- A.1.73 PKHTB
- A.1.74 PLD
- A.1.75 PLDW
- A.1.76 PLI
- A.1.77 POP
- A.1.78 PUSH
- A.1.79 QADD
- A.1.80 QADD8
- A.1.81 QADD16
- A.1.82 QASX
- A.1.83 QDADD
- A.1.84 QDSUB
- A.1.85 QSAX
- A.1.86 QSUB
- A.1.87 QSUB8
- A.1.88 QSUB16
- A.1.89 RBIT
- A.1.90 REV
- A.1.91 REV16
- A.1.92 REVSH
- A.1.93 RFE
- A.1.94 ROR
- A.1.95 RRX
- A.1.96 RSB
- A.1.97 RSC
- A.1.98 SADD8
- A.1.99 SADD16
- A.1.100 SASX
- A.1.101 SBC
- A.1.102 SBFX
- A.1.103 SDIV
- A.1.104 SEL
- A.1.105 SETEND
- A.1.106 SEV
- A.1.107 SHADD8
- A.1.108 SHADD16
- A.1.109 SHASX
- A.1.110 SHSAX
- A.1.111 SHSUB8
- A.1.112 SHSUB16
- A.1.113 SMC
- A.1.114 SMLAxy
- A.1.115 SMLAD
- A.1.116 SMLAL
- A.1.117 SMLALxy
- A.1.118 SMLALD
- A.1.119 SMLAWy
- A.1.120 SMLSLD
- A.1.121 SMMLA
- A.1.122 SMMLS
- A.1.123 SMMUL
- A.1.124 SMUAD
- A.1.125 SMUSD
- A.1.126 SMULxy
- A.1.127 SMULL
- A.1.128 SMULWy
- A.1.129 SRS
- A.1.130 SSAT
- A.1.131 SSAT16
- A.1.132 SSAX
- A.1.133 SSUB8
- A.1.134 SSUB16
- A.1.135 STC
- A.1.136 STC2
- A.1.137 STL
- A.1.138 STLB
- A.1.139 STLEX
- A.1.140 STLEXB
- A.1.141 STLEXD
- A.1.142 STLEXH
- A.1.143 STLH
- A.1.144 STM
- A.1.145 STR
- A.1.146 STRD
- A.1.147 STREX
- A.1.148 SUB
- A.1.149 SVC
- A.1.150 SWP
- A.1.151 SXT
- A.1.152 SXTA
- A.1.153 SYS
- A.1.154 TBB
- A.1.155 TBH
- A.1.156 TEQ
- A.1.157 TST
- A.1.158 UADD8
- A.1.159 UADD16
- A.1.160 UASX
- A.1.161 UBFX
- A.1.162 UDIV
- A.1.163 UHADD8
- A.1.164 UHADD16
- A.1.165 UHASX
- A.1.166 UHSAX
- A.1.167 UHSUB8
- A.1.168 UHSUB16
- A.1.169 UMAAL
- A.1.170 UMLAL
- A.1.171 UMULL
- A.1.172 UQADD8
- A.1.173 UQADD16
- A.1.174 UQASX
- A.1.175 UQSAX
- A.1.176 UQSUB8
- A.1.177 UQSUB16
- A.1.178 USAD8
- A.1.179 USADA8
- A.1.180 USAT
- A.1.181 USAT16
- A.1.182 USAX
- A.1.183 USUB8
- A.1.184 USUB16
- A.1.185 UXT
- A.1.186 UXTA
- A.1.187 WFE
- A.1.188 WFI
- A.1.189 YIELD
- A.1 Instruction Summary
- B: Tools, Operating Systems and Boards
- C: Building Linux for ARM Systems
- Index