0943441 9701_990_Assembly_Language_Programming_Guide_Oct78 9701 990 Assembly Language Programming Guide Oct78
User Manual: 0943441-9701_990_Assembly_Language_Programming_Guide_Oct78
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TEXAS INSTRUMENTS
Improving Man's Effectiveness Through Electronics
.1
Model 990 Computer
TMS- 9900 Microprocessor
Assembly Language Programmer's Guide
MANUAL NO. 943441-9701
ORIGINAL ISSUE 1 JUNE 1974
REVISED 15 OCTOBER 1978
Digital Systems Division
©
Texas InstrlJllents Incorporated 1978
All Rfghts Reserved
The fnfonnatfon and/or drawings set forth in this doclJllent and all rights in and
to inventions disclosed herein and patents which might be granted thereon disclosing or employing the materials, methods, techniques or apparatus described herein
are the exclusive property of Texas Instruments Incorporated.
LIST OF £F FECTIVE PAGES
INSERT LATEST CHANGED PAGES DESTROY SUPERSEDED PAGES
Note: The portion of the text affected by the changes is
indicated by a vertical bar in the outer margins of
the page.
Model 990 Computer TMS9900 Microprocessor Assembly Language
Programmer's Guide (943441-9701)
Original Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 June 1974
Revised . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 October 1978 (ECN 446281)
Total number of pages in this publication is 366 consisting of the following:
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J}n)\
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943441-9701
PREFACE
This manual describes the assembly language for the Model 990 Computer and the TMS 9900
microprocessor as implemented by PX9ASM, a one-pass assembler that executes under the Prototyping System PX990; by TXMIRA, a two-pass assembler that executes under TX990; by SDSMAC,
a two-pass assembler that executes under Disc Executive DXI 0; and by the Cross Assembler, a twopass assembler that is part of the Cross Support System. Except for a few differences that are
expressed in Appendix L, the TMS 9940 microcomputer uses the same assembly language as the
TMS 9900 microprocessor. However, the assembly language for the TMS 9940 microcomputer can
be implemented only by the TXMIRA and the SDSMAC assemblers.
This manual describes:
•
Source statement formats and elements
•
Addressing modes
•
Assembler directives and pseudo-instructions
•
Assembly instructions
•
Macro language, supported by SDSMAC
•
Assembler output
Appendixes contain:
•
The character set
•
Instruction tables
•
Directive tables
•
A macro language summary
•
CRU and TILINE examples
•
TMS 9940 programming considerations.
This manual assumes that the reader is familiar with the computer architecture and I/O capabilities
as described in the 990 Computer Family Systems Handbook.
The following documents contain additional information related to the assembly language:
Part Number
Title
990 Computer Family Systems Handbook
945250-9701
Model 990 Computer Pro to typing System
Operation Guide
945255-9701
iii
Texas Instruments Incorporated
~------~
943441-9701
Title
Part Number
Model 990 Computer DXIO Operating System
Documentation, Volume 4 - Development
Operation
946250-9704
Model 990 Computer DXIO Operating System
Documentation, Volume 3 - Application
Programming Guide
946250-9703
Model 990 Computer TX990 Operating
System Programmer's Guide (Release 2)
946259-9701
Model 990 Computer Cross Support System
User's Guide
945252-9701
Model 990 Computer TMS 9900 Microprocessor
Cross Support System Installation and Operation
945420-9701
Model 990 Computer Terminal Executive Development
System (TXDS) Programmer's Guide
946258-9701
DXIO Operating System Production Operation
Guide
946250-9702
TMS 9940 16-Bit Microcomputer Data Manual
*
*
Available from:
Texas Instruments Incorporated
Microprocessor Marketing
Mail Station 653
P. O. Box 1443
Houston, Texas 77001
iv
Texas Instruments Incorporated
~~------------------~
943441-9701
TABLE OF CONTENTS
Paragraph
Title
Page
SECTION I. INTRODUCTION
1.1
1.2
Assembly Language Definition .
Assembly Language Application
1-1
1-1
SECTION II. GENERAL PROGRAMMING INFORMATION
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
2.5
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.8
2.8.1
2.8.2
2.9
2.9.1
2.9.2
2.9.3
2.9.4
2.10
2.11
2.12
2.13
Byte Organization
Word Organization
Transfer Vectors
Status Register
Logical Greater Than
Arithmetic Greater Than
Equal
Carry
Overflow
Odd Parity
Extended Operation
Status Bit Summary
Memory Organization
Privileged Mode
Source Statement Format
Character Set
Label Field
Operation Field
Operand Field
Comment Field
Expressions
Well-Defined Expressions
Arithmetic Operators
Constants
Decimal Integer Constants
Hexadecimal Integer Constants
Character Constants
Assembly-Time Constants
Symbols
Predefined Symbols
Terms
Character Strings
2-1
2-1
2-2
2-2
24
24
24
24
2-4
2-5
2-5
2-5
2-5
.2-10
.2-10
.2-11
.2-11
.2-11
.2-13
.2-13
.2-13
.2-14
.2-14
.2-15
.2-15
.2-15
.2-15
.2-15
.2-15
.2-16
.2-16
.2-17
SECTION III. ASSEMBLY INSTRUCTIONS
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
General
Addressing Modes
Workspace Register Addressing
Workspace Register Indirect Addressing
Symbolic Memory Addressing
Indexed Memory Addressing
Workspace Register Indirect Autoincrement Addressing
v
3-1
3-1
3-2
3-2
3-2
3-2
3-3
Texas Instruments Incorporated
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943441-9701
TABLE OF CONTENTS (Continued)
Paragraph
3.3
3.4
3.5
3.6
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.7
3.7.8
3.7.9
3.7.10
3.7.11
3.7.12
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
3.36
3.37
3.38
3.39
Title
Program Counter Relative Addressing
CRU Bit Addressing
Immediate Addressing
Addressing Summary .
Addressing Formats
Format I - Two Address Instructions
Format II - Jump Instructions .
Format II - Bit I/O Instructions
Format III - Logical Instructions
Format IV - CRU Instructions .
Format V - Register Shift Instructions
Format VI - Single Address Instructions
Format VII - Control Instructions
Format VIII - Immediate Instructions
Format IX - Extended Operation Instructiqn
Format IX - Multiply and Divide Instruction
Format X - Memory Map File Instruction
Instruction Descriptions
Arithmetic Instructions
Add Words A
Add Bytes AB
Add Immediate AI
Subtract Words S
Subtract Bytes SB
Multiply MPY
Divide DN
Increment INC
Increment By Two INCT
Decrement DEC
Decrement By Two DECT
Absolute Value ABS
Negate NEG . . . . . .
Jump and Branch Instructions
Branch B . . . . . . . .
Branch and Unk BL
Branch and Load Workspace Pointer BLWP
Return with Workspace Pointer RTWP
Unconditional Jump JMP
Jump If Logical High JH . .
Jump If Logical Low JL . .
Jump If High Or Equal JHE
Jump If Low Or Equal JLE
Jump If Greater Than JGT
Jump If Less Than JLT
Jump If Equal JEQ . .
Jump If Not Equal JNE
Jump On Carry JOC
Jump If No Carry JNC
Jump If No Overflow JNO
vi
Page
3-3
3-3
3-4
3-4
3-6
3-6
3-7
3-7
3-8
3-8
3-9
.3-10
.3-10
.3-11
.3-12
.3-12
.3-13
.3-13
.3-15
.3-15
.3-16
.3-17
.3-18
.3-19
.3-20
.3-21
.3-23
.3-24
.3-25
.3-26
.3-27
.3-28
.3-29
.3-30
.3-31
.3-32
.3-33
.3-34
.3-35
.3-36
.3-37
.3-38
.3-39
.3-40
.3-41
.3-42
.3-43
.3-44
.3-45
Texas Instruments Incorporated
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943441-9701
TABLE OF CONTENTS (Continued)
Paragraph
3.40
3.41
3.42
3.43
3.44
3.45
3.46
3.47
3.48
3.49
3.50
3.51
3.52
3.53
3.54
3.55
3.56
3.57
3.58
3.59
3.60
3.61
3.62
3.63
3.64
3.65
3.66
3.67
3.68
3.69
3.70
3.71
3.72
3.73
3.74
3.75
3.76
3.77
3.78
3.79
3.80
3.81
3.82
3.83
3.84
3.85
3.86
3.87
3.88
Title
Jump If Odd Parity JOP
Execute X . . . .
Compare Instructions
Compare Words C .
Compare Bytes CB
Compare Immediate CI
Compare Ones Corresponding COC
Compare Zeros Corresponding CZC
Control and CRU Instructions
Reset RSET
Idle IDLE
Clock Off CKOF
Clock On CKON
Load or Restart Execution LREX
Set CRU Bit to Logic One SBO
Set CRU Bit to Logic Zero SBZ
Test Bit TB
Load CRU LDCR . . . .
Store CRU STCR . . . .
Load and Move Instructions
Load Immediate LI . . .
Load Interrupt Mask Immediate LIMI
Load Wcxkspace Pointer Immediate LWPI
Load Memory Map File LMF
Move Word MOV
Move Byte MOVB
Swap Bytes SWPB
Store Status STST
Store Workspace Pointer STWP
Logical Instructions
AND Immediate ANDI
OR Immediate ORI
Exclusive OR XOR
Invert INV . . .
Clear CLR . . . .
Set to One SETO .
Set Ones Corresponding SOC
Set Ones Corresponding, Byte SOCB
Set Zeros Corresponding SZC
Set Zeros Corresponding, Byte SZCB
Workspace Register Shift Instructions
Shift Right Arithmetic SRA
Shift Left Arithmetic SLA
Shift Right Logical SRL .
Shift Right Circular SRC .
Extended Operation XOP
Long Distance Addressing Instructions
Long Distance Source LDS . .
Long -Distance Destination LDD
vii
Page
.3-46
.3-47
.3-48
.3-48
.3-49
.3-50
.3-51
.3-52
.3-53
.3-53
.3-54
.3-55
.3-56
.3-57
.3-58
.3-59
.3-60
.3-61
.3-62
.3-63
.3-63
.3-64
.3-65
.3-66
.3-68
.3-69
.3-70
.3-71
.3-72
.3-72
.3-73
.3-74
.3-75
.3-76
.3-77
.3-78
.3-79
.3-80
.3-81
.3-82
.3-84
.3-84
.3-85
.3-86
.3-87
.3-88
.3-89
.3-89
.3-90
Texas Instruments Incorporated
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943441-9701
TABLE OF CONTENTS (Continued)
Paragraph
3;89
3.89.1
3.89.2
3.89.3
3.89.4
3.89.5
3.89.6
3.89.7
3.89.8
3.89.9
3.89.10
Title
Programming Examples
ABS Instruction . .
Shifting Instructions
Incrementing and Decrementing
Subroutines . . . .
Interrupts
...... .
Extended Operations . . .
Special Control Instructions
CRU Input/Output
TILINE Input/Output
Re-Entrant Programming
Page
.3-91
.3-92
.3-93
.3-95
.3-98
3-103
3-107
3-110
3-113
3-117
. 3-117
SECTION IV. ASSEMBLER DIRECTIVES
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
4.2.11
4.2.12
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.6
4.6.1
4.6.2
Introduction
Directives that Affect the Location Counter
Absolute Origin AORG
Relocatable Origin RORG
Dummy Origin DORG
Block Starting with Symbol BSS
Block Ending with Symbol BES
Word Boundary EVEN
Data Segment DSEG
Data Segment End DEND
Common Segment CSEG
Common Segment End CEND
Program Segment PSEG
Program Segment END PEND.
Directives that Affect the Assembler Output
Output Options
Program Identifier IDT
Page Title TITL
List Source LIST
No Source List UNL
Page Eject PAGE
Directives that Initialize Constants
Initialize Byte BYTE
Initialize Word DATA
Initialize Text TEXT
Define Assembly-Time Constant EQU
Directives that Provide Linkage Between Programs
External Definition DEF
External Reference REF
Secondary Extemal Reference SREF
Force Load LOAD
Miscellaneous Directives
Define Extended Operation DXOP
Program End END
viii
4-1
4-1
4-2
4-2
4-3
4-5
4-5
4-5
4-6
4-7
4-7
4-9
4-9
04-10
A-II
A-II
04-11
04-12
04-13
04-13
04-13
04-14
04-14
04-14
04-15
04-15
04-16
04-16
04-17
04-17
04-18
.4-19
.4-19
04-19
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943441-9701
TABLE OF CONTENTS (Continued)
Paragraph
Title
Page
SECTION V. PSEUDO-INSTRUCTIONS
5.1
5.2
5.3
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
No Operation NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Return RT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
SECTION VI. ASSEMBLERS
6.1
6.2
6.2.1
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.4.9
6.4.10
6.4.11
6.4.12
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Prototyping System Assembler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Terminal Executive Development System Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Cross Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Program Development System Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Uses of Parenthesis in Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Right Shift Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Logical Operators in Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Relational Operators in Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Output Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Workspace Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Copy Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Conditional Assembly Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Define Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-10
Transfer Vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Set Maximum Macro Nesting Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-11
Symbolic Addressing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12
SECTION VII. MACRO LANGUAGE
7.1
7.2
7.3
7.4
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.lO
7.5.11
7.5.12
7.5.13
7.5.14
7.5.15
7.5.16
7.5.17
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Processing of Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Macro Translator Interface with the Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Macro Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Macro Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Labels . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Strings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Constants and Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Model Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Symbol Attribute Component Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Parameter Attribute Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Verbs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
$MACRO . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . . . . . . . . . . . . . . '" ........ 7-9
$VAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-13
$ASG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-13
$NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-15
$GOTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-15
$EXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-15
$CALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16
$IF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16
$ELSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17
ix
Digital Systems Division
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943441-9701
TABLE OF CONTENTS (Continued)
Paragraph
7.5.18
7.5.19
7.6
7.6.1
7.6.2
7.6.3
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
Title
Page
$ENDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17
$END . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17
Assembler Directives to Support Macro Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
LIBOUT Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
LIBIN Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
Macro Library Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19
Macro Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
Macro GOSUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
Macro EXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
Macro ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22
Macro UNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-23
Macro GENCMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-24
Macro LOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-24
Macro TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-25
Macro LISTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-26
SECTION VIII. RELOCAT ABILITY AND PROGRAM LINKING
8.1
8.2
8.2.1
8.3
8.3.1
8.3.2
8.4
8.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Relocation Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Relocatability of Source Statement Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Reference Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Definition Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Identifier Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linking Program Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . .
8-1
8-1
8-1
8-2
8-2
8-2
8-3
8-3
SECTION IX. OPERATION OF THE MACRO ASSEMBLER
9.1
9.2
9.2.1
9.2.2
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating the Macro Assembler ........ '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Completion Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating the Assembler in Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-1
9-1
9-4
9-4
SECTION X. ASSEMBLER OUTPUT
10.1
10.2
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.4
10.5
10.5 .1
10.5 .2
10.5 .3
10.5.4
10.5.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 0-1
Source Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 0-1
Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 0-3
PX9ASM Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3
Cross Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 0-5
SDSMAC Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5
SDSMAC Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 0-5
TXMIRA Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
Cross Reference Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
Object Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
Object Code Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
Machine Language Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
Symbol Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
Object Code Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
Procedures for Changing Object Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
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943441-9701
APPENDIXES
Appendix
Page
Title
A
Character Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . A-I
B
Instruction Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
C
Program Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ .... C-1
D
Hexadecimal Instruction Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
E
Alphabetical Instruction Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
F
Assembler Directive Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1
G
Macro Language Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-1
H
CRU Interface Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-1
I
TILINE Interface Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I-I
J
Example Program .. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .J-1
K
Numerical Tables . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . K-l
L
TMS 9940 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L-1
LIST OF ILLUSTRATIONS
Figure
2-1
2-2
2-3
24
2-5
2-6
2-7
2-8
3-1
3-2
3-3
34
3-5
3-6
3-7
3-8
3-9
3-10
Title
Page
Memory Byte . . . . . . . . . .
. . . . . . . . . . . . .
Memory Word . . . . . . . . . .
. . . . . . . . . . . . .
Typical Memory Map for Model 990 Computer/TMS 9900 Microprocessor
Status Register, Model 990 Computer TMS 9900
Status Register, Model 990/10 with Map Option .
Model 990 Computer Workspace . . . . . . . .
Address Development, Model 990/10 Map Option
Source Statement Formats
...... .
2-4
2-8
2-9
.2-12
Common Workspace Subroutine Example .
PC Contents after BL Instruction Execution
Context Switch Subroutine Example . .
After Execution of BLWP Instruction
After Return Using the RTWP Instruction
Interrupt Processing Example
Memory Contents after Interrupt
Extend Operation Example
Extended Operation Example after Context Switch
Re-entrant Procedure for Process Control
.3-99
.3-99
3-100
3-101
3-102
3-108
3-108
3-110
3-111
3-118
xi
2-1
2-1
2-3
24
Texas Instruments Incorporated
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943441-9701
LIST OF ILLUSTRATIONS (Continued)
Figure
Title
Page
7-1
Macro Assembler Block Diagram
7-1
9-1
9-2
Macro Assembly Stream
Macro Assembly Stream for Cards
9-5
9-6
10-1
10-2
10-3
10-4
10-5
Cross Reference Listing Format
Object Code Example
External Reference Example
Machine Instruction Formats
Object Code Listing Format .
10-15
10-16
10-19
10-21
10-22
LIST OF TABLES
Table
Title
Page
2-1
Status Bits Affected by Instructions
2-6
3-1
3-2
3-3
3-4
3-5
3-6
3-7
Addressing Modes . . . . . . .
Instruction Addressing . . . . .
Status Bits Tested by Instructions
Interrupt Vector Addresses
....... .
Interrupt Mask
Error Interrupt Logic CRU Bit Assignments
XOP Vectors _ . . . . . . . . . . . .
3-1
3-5
7-1
7-2
7-3
7-4
Variable Qualifiers . . . . .
Variable Qualifiers for Symbol
Symbol Attribute Keywords .
Parameter Attribute Keywords
9-1
Abnormal Completion Messages
Completion Messages . . . . .
9-2
Error Codes . . . . . . . . .
Cross Assembler Error Messages
SDSMAC Listing Errors .
TXMIRA Fatal Errors
TXMIRA Nonfatal Errors
Symbol Attributes
990 Object Tags . . . .
.104
9-2
10-1
10-2
10-3
10-4
10-5
10-6
10-7
. . . . . .
Components
.
.
3-29
3-104
3-105
3-107
3-109
7-5
7-7
7-8
7-9
9-4
.10-7
.10-9
10-14
10-14
10-15
10-17
xii
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~
SECTION I
INTRODUCTION
1.1 ASSEMBLY LANGUAGE DEFINITION
An assembly language is a computer-oriented language for writing programs. It consists of
mnemonic instructions and assembler directives. In assembly instructions, the user assigns symbolic
addresses to memory locations and specifies instructions by means of symbolic operation codes
called mnemonic operation codes. The user specifies instruction operands by means of symbolic
addresses, numbers, and expressions consisting of symbolic addresses and numbers. Assembler directives control the process of making a machine language program from the assembly
language program, place data in the program, and assign symbols to values to be used in the
program. Assembler directives that place data in memory locations allow the user to assign
symbolic addresses to those locations.
An assembly language is computer-oriented in that the mnemonic operation codes correspond
directly with machine instructions. The chief advantage an assembly language offers over machine
language is that the symbols of assembly language are easier to use and easier to remember than
the zeros and ones of machine language. Other advantages are the use of expressions as operands
and the use of decimal numbers in expressions and as operands.
1.2 ASSEMBLY LANGUAGE APPLICATION
An assembly language program, called a source program, must be processed by an assembler to
obtain a machine language program that can be executed by the computer. Processing of a
source program is called assembling, because it consists of assembling the binary values that
correspond to the mnemonic operation code with the binary address information to form the
machine language instruction.
To illustrate the place of assembly language in the development of programs, consider the
following steps in program development:
1.
Define the problem.
2.
Flowchart the solution to the problem.
3.
Code the solution by writing assembly language statements (machine instructions and
assembler directives) that correspond to the steps of the flowchart.
4.
Prepare the source program by writing the statements on the medium appropriate to
the installation; i.e., keypunch the statements if a card reader is to be used as input to
the assembler, etc.
5.
Execute the assembler to assemble the machine language object code corresponding to
the source program.
6.
Debug the resulting object code by loading and executing the object code and by making
corrections indicated by the results of executing the object code.
7.
Repeat steps 5 and 6 until no further correction is required.
1-1
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The use of assembly language in program development relieves the programmer of the tedious
task of writing machine language instructions and keeping track of binary machine addresses
within the program.
1-2
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~
SECTION II
GENERAL PROGRAMMING INFORMATION
2.1 BYTE ORGANIZATION
Memory for the Model 990 Computer/TMS 9900 Microprocessor is addressed using byte
addresses. A byte consists of eight bits of memory, as shown in figure 2-1. The bits may
represent the states of eight independent two-valued quantities, or the configuration of a
character in a code used for input, output, or data transmission. The bits also may represent a
number which is interpreted either as a signed number in the range of -128 through +127 or as
an unsigned number in the range of 0 through 255. The 990 computers and TMS 9900 microprocessor implements signed numbers in 2's complement form.
The most significant bit (MSB) is designated bit 0, and the least significant bit (LSB) is
designated bit 7. A byte instruction may address any byte in memory.
2.2 WORD ORGANIZATION
A word in the memory for the Model 990 Computer/TMS 9900 Microprocessor consists of 16
bits, a byte at an even address and the following byte at an odd address. As shown in figure 2-2,
the most significant bit of a memory word is designated bit 0, and the least significant bit is
designated bit 15. A word may contain a computer instruction in machine language, a memory
address, the bit configurations of two characters, or a number. When a word contains a number,
the number may be interpreted as a signed number in the range of -32,768 through +32,767, or
as an unsigned number in the range of 0 through 65,535. (Signed numbers are implemented in
2's complement form.)
Word boundaries are assigned to even-numbered addresses in memory. The even address byte
contains bits 0 through 7 of the word, and the odd address byte contains bits 8 through 15.
When word instructions address an odd byte, the word operand is the memory word consisting
of the addressed byte and the preceding even-numbered byte. This is the memory word that
would be accessed by the odd address minus one. For example, a memory address of 1023 16
used as a word address would access the same word as memory address 1022 16 ,
NOTE
All instructions must begin on word boundaries. Instructions are
I, 2, or 3 words long.
(MSB)
(L.SB)
Figure 2-1. Memory Byte
(MSB)
(L.SB)'.
2
3
4
5
6
7
8
9
10 11
12 13 14
151
(WORD BOUNDARY)
Figure 2-2. Memory Word
2-1
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2.3 TRANSFER VECTORS
A transfer vector is a pair of memory addresses in two consecutive words of memory. The first
word contains the address of a l6-word area of memory, called a workspace. The second word
contains the address of a subroutine entry point. The Model 990 Computer/TMS 9900 Microprocessor uses a transfer vector in a type of transfer of control called a context switch. A
context switch places the contents of the first word of a transfer vector in the Workspace
Pointer (WP) register, making the workspace addressed by that word tbe active workspace. The
16 words of the active workspace become workspace registers 0 through 15, which are available
for use as general purpose registers, address registers, or index registers. A context switch places
the contents of the second word of a transfer vector in the Program Counter (PC), causing the
.
instruction at that address to be executed next.
A context switch transfers control to an interrupt subroutine whenever an interrupt occurs. The
transfer vectors for interrupt levels 0 through 15 are located in memory locations 0000 16
through 003E 16 , as shown in figure 2-3. The address of the first byte of the vector for an interrupt
level is the product of the level number times four.
The Model 990 Computer/TMS 9900 Microprocessor supports extended operations implemented
by subroutines. These extended operations are effectively additional instructions that may
perform user-defmed functions. Up to 16 extended operations may be implemented. An
extended operation machine instruction results in a context switch to the specified extended
operation subroutine. The transfer vectors for extended operations 0 through 15 are located in
memory locations 0040 16 through 007E 16 as shown in figure 2-3. The address of the first byte
of the vector for an extended operation is the hexadecimal sum of the product of the extended
operation number times four, plus 40 16 •
In the Model 990/10 Computer, an extended operation may be implemented with user-supplied
hardware. When a hardware module is connected for an extended operation, no context switch
occurs for that operation, and the hardware performs the operation. Program execution continues when the operation has completed.
A context switch using the transfer vector at memory location FFFC 16 transfers control to a
subroutine to load or restart the computer. Execution of an LREX instruction or activation of a
switch on the control panel initiates the context switch.
A context switch to a user subroutine is performed by the BLWP instruction. The transfer vector
is placed at a user defined location in memory.
2.4 STATUS REGISTER
The configuration of the Status Register of the Model 990 Computer and the TMS 9900
Microprocessor is shown in figure 2-4. The configuration of the Status Register of the Model
. 990/1 () Computer with map option is shown in figure 2-5. Bits 0 through 6 and 12 through 15
are identical, and are the bits that are set and reset by the machine instructions. These bits have
the following meanings:
•
L>, bit 0 - Logical greater than
•
A>, bit 1 - Arithmetic greater than
•
EQ, bit 2 - Equal
•
C, bit 3 - Carry
2-2 .
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AREA
DEFINITION
MEMORY
ADDRESS
(HEXADECIMAL)
INTERRUPTS
LEVELS 0 THROUGH 7
(MODEL 990/4)
0000
LEVEL 0 INTERRUPT
TRANSFER VECTOR
0004
LEVEL 1 INTERRUPT
TRANSFER VECTOR
0008
LEVELS 0 THROUGH 15
(MODEL 990/1 0)
::~
003C
LEVEL 15 INTERRUPT
TRANSFER VECTOR
0040
XOP 0 TRANSFER VECTOR
0044
XOP 1 TRANSFER VECTOR
0048
EXTENDED OPERATIONS
o THROUGH 15
=--
007C
GENERAL MEMORY FOR
EXECUTIVE, PROGRAMS.
AND DATA
~ ...
XOP 15 TRANSFER VECTOR
0080
.,.,
GENERAL
MEMORY
AREA
.~
TILINE
~
PROGRAMMER PANEL
AND LOADER
"-
F7FE
F800
TILINE PERIPHERAL
CONTROL SPACE
(MODEL 990/10)
FBFE
PROM
(MODEL 990/4.990/10)
FCOO
.
FFFA
LOAD OR RESTART
FUNCTION
FFFC
RESTART TRANSFER VECTOR
FFFE
(A) 13 2200
Figure 2-3. Typical Memory Map for Model 990 Computer/TMS 9900 Microprocessor
•
OV, bit 4 - Overflow
•
OP, bit 5 - Odd parity
•
X, bit 6 - Extended operation
•
Bits 12-15 - Interrupt mask
Two of the reserved bits in the Model 990/4 Status Register are defined for the Status Register of
the Model 990/10. Bit 7, the PR bit, is set to one to inhibit execution of the privileged instructions.
When execution of a privileged instruction is attempted with the PR bit set to one, an illegal
instruction error occurs. Bit 7 must be set to zero-to execute these instructions. An additional
bit, bit 8, the Map File (MF) bit, specifies the memory map file for the memory mapping option. The memory mapping option provides access to memory addresses outside of the range
2-3
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Figure 2-4. Status Register, Model 990 Computer TMS 9900
o
2
3
IL>IA>IEQI C
4
5
6
7
\oviopi xIPR
8
9
10 11
12
13
14
15
/MFtI)'IlA INllfA~~T
Figure 2-5. Status Register, Model' 990/10 With Map Option
of addresses (32K words) of the address portions of instructions. When bit 8 is set to 0, the six
mapping registers for map
are active. When bit 8 is set to I, the six mapping registers for
map I are active.
°
2.4.1 LOGICAL GREATER THAN. The logical greater than bit of the Status Register contains
the result of a comparison of words or bytes as unsigned binary numbers. In this comparison,
the most significant bits of words being compared represent 2 15 , and the most significant bits of
bytes being compared represent 27.
2.4.2 ARITHMETIC GREATER THAN. The arithmetic greater than bit of the Status Register
contains the result of a comparison of words or bytes as two's complement numbers. In this
comparison, the most significant bits of words or bytes being compared represent the sign of the
number, zero for positive, or one for negative. For positive numbers, the remaining bits represent
the binary value. For negative numbers, the remaining bits represent the two's complement of
the binary value.
2.4.3 EQUAL. The equal bit of the Status Register is set when the words or bytes being
compared are equal. Whether the comparison is that of unsigned binary numbers or two's
complement numbers the significance of equality is the same.
2.4.4 CARRY. The carry bit of the Status Register is set by a carry out of the most significant
bit of a word or byte (sign bit) during arithmetic operations. The carry bit is used by the shift
operations to store the last bit shifted out of the workspace register being shifted.
2.4.5 OVERFLOW. The overflow bit of the Status Register is set when the result of an
arithmetic operation is too large or too small to be correctly represented in two's complement
representation. In addition operations, the overflow bit is set when the most significant bits of
the operands are equal and the most significant bit of the result is not equal to the most
significant bit of the destination operand. In subtraction operations, the overflow bit is set when
the most significant bits of the operands are not equal, and the most significant bit of the result
is not equal to the most significant bit of the destination operand. For a divide operation, the
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overflow bit is set when the most significant sixteen bits of the dividend are greater than or
equal to the divisor. For an arithmetic left shift, the overflow bit is set if the most significant bit
of the workspace register being shifted changes value. For the absolute value and negate
instructions, the overflow bit is set when the source operand is the maximum n.egative value,
8000 16 •
2.4.6 ODD PARITY. The odd parity bit of the Status Register is set in byte operations when
the parity of the result is odd, and is reset when the parity is even. The parity of a byte is odd
when the number of bits having values of one is odd; when the number of bits having values of
one is even, the parity of the byte is even. The odd parity bit is equal to the least significant bit
of the sum of the bits in the byte.
2.4.7 EXTENDED OPERATION. The extended operation bit of the Status Register is set to
one when a software implemented extended operation is initiated. An extended operation is
initiated by a context switch using the transfer vector for the specified extended operation. After
the WP and PC have been set to the values in the transfer vector, the extended operation bit is
set.
2.4.8 STATUS BIT SUMMARY. Table 2-1 lists the instructions of the Model 990 Computer/
TMS 9900 Microprocessor instruction set and the status bits affected by each instruction. The
effectivity column contains A to indicate applicability to all Model 990 Computers and the
TMS 9900 Microprocessor. The column contains C to indicate applicability to all Model 990
Computers but not to the TMS 9900 Microprocessor. The column contains M to indicate
applicability only to Model 990/1 0 Computers with mapping option. The interrupt mask is explained in a subsequent paragraph.
2.S MEMORY ORGANIZATION
Figure 2-3 shows a generalized memory map applicable to Model 990 Computer/TMS 9900
Microprocessor memories. The area of low-order memory from address 0 through 7F 1 6 is used
for interrupt and extended operation transfer vectors as previously described. Addresses reserved
for transfer vectors that are not used (interrupt levels 8 through 15 in Model 990/4 computers)
may be used for instructions and/or data. Since many memory configurations are available as
options, the programmer should ascertain the memory configuration for his system.
The area of memory from address 80 16 through address F7FE 16 is available for workspaces, instructions, and data. Many users of Model 990 Computers will place an executive (PX990, TX990 or
DXlO) in a portion of this area. The remainder of this area (as supplied) is available for
workspaces, instructions, and data for user programs. TMS 9900 users, and Model 990 Computer
users who do not use PX990, or TX990 or DX1 0 may use the entire area (as supplied).
Various types and sizes of memory are available for the TMS 9900 Microprocessor and the Model
990/4 Computer. Addressing is not necessarily continuous. Addresses may be assigned according
to the needs of an application, omitting addresses as appropriate.
In the Model 990/10 Computer, addresses F800 1 6 through FBFE 16 are reserved for TILINE
communication with peripheral devices. These addresses may be assigned to registers in controllers for direct memory access devices. Input/Output from or to these devices is performed using
any instruction that may be used to access memory. For I/O, the address in the instruction must
be the TILINE address assigned to the appropriate register. An example of TILINE interface is
shown in Appendix I.
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Table 2-1. Status Bits Affected by Instructions
Mnemonic
Eff.
L>
A>
EQ
C
OV
OP
X
Mnemonic
Eff.
L>
A> EQ
C
OV
OP
X
\0
N
0-.
;;t
A
A
X
X
X
X
X
AB
A
X
X
X
X
X
~
X
DIV
A
IDLE
C
~
~
~
::i
~
(;t
~
~
~
~
q;Cl
~
~
,
A
X
X
X
X
X
INC
A
X
X
X
X
X
AI
A
X
X
X
X
X
INCT
A
X
X
X
X
X
ANDI
A
X
X
X
INV
A
X
X
X
B
A
JEQ
A
BL
A
JGT
A
BLWP
A
JH
A
C
A
X
X
X
JHE
A
CB
A
X
X
X
JL
A
CI
A
X
X
X
JLE
A
CKOF
C
JLT
A
CKON
C
JMP
A
CLR
A
JNC
A
COC
A
X
JNE
A
CZC
A
X
JNO
A
DEC
A
X
X
X
X
X
JOC
A
DECT
A
X
X
X
X
X
JOP
A
X
w
\0
ABS
),c
~
X
-...)
0
.....
~
Table 2-1. Status Bits Affected by Instructions (Continued)
Mnemonic
Eff.
D
A>
EQ
C
OV
OP
X
Mnemonic
Eff.
L>
A>
EQ
C
OV
OP
X
\I;)
LDCR
A
LDD
M
X
X
~
X
SBZ
A
SETO
A
w
~
~
I
\I;)
LDS
M
LI
A
LIMI
-..J
0
SLA
A
X
X
X
SOC
A
X
X
X
A
SOCB
A
X
X
X
LMF
M
SRA
A
X
X
X
X
LREX
C
SRC
A
X
X
X
X
LWPI
A
SRL
A
X
X
X
X
MOV
A
X
X
X
STCR
A
X
X
X
MOVB
A
X
X
X
STST
A
MPY
A
STWP
A
NEG
A
X
X
X
SWPB
A
ORI
A
X
X
X
SZC
A
X
X
X
RSET
C
SZCB
A
X
X
X
RTWP
A
X
X
X
X
X
TB
A
S
A
X
X
X
X
X
X
A
2
2
2
2
2
2
2
~
SB
A
X
X
X
X
X
XOP
A
2
2
2
2
2
2
2
~
SBO
A
XOR
A
X
X
X
NI
-..J
loc
::;(I)
~
§
~
e;;-
::;C')
~
~
Q
] 'b ... opcode'b ... [] [,] ... 'b ... []
This syntax definition means that a source statement may have a label, which is defined by the
user. One or more blanks separate the label from the opcode. Mnemonic operation codes,
assembler directives codes, and user-defined operation codes are all included in the generic term
opcode, and any of these may be entered. One or more blanks separate the opcode from the
operand, when an operand is required. Additional operands, when required, are separated by
commas. One or more blanks separate the operand or operands from the comment field.
Comment statements consist of a single field starting with an asterisk (*) in the first character
position followed by any ASCII character including a blank in each succeeding character
position. Comment statements are listed in the source portion of the assembly listing and have
.
no other effect on the assembly.
The maximum length of source records is 60 characters. However, only the first 52 characters
will be printed on the Model 733 ASR Data terminal. The last source statement of a source
program is followed by the end-of-record statement for the source medium, i.e., for punched
cards, a card having a slash (/) punched in column I and an asterisk (*) punched in column 2.
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Figure 2-8 shows source statements written on a coding form illustrating alternative methods of
entering statements. The first four statements illustrate the alignment of the label, opcode,
operands, and comments to begin in the same column in each statement. This method promotes
readability, but may be time-consuming on some input devices, particularly data terminals. The
last four statements show the use of horizontal tab characters represented by
to separate the
fields. On the Model 733 ASR Data Terminal, the tab character is entered by holding the CTRL
key while pressing the I key. PX9 ASM does not implement this use of ~ .
¥
2.7.1 CHARACTER SET. The assemblers for the Model 990 Computers and the TMS 9900
Microprocessor recognize ASCII characters as follows:
•
The alphabet (capital letters only) and space character
•
The numerals
•
Twenty-two special characters
•
Five characters defined for this language, that are undefined as ASCII characters
•
The null character
•
The tab character
Appendix A contains tables that list all 66 characters and show the ASCII and Hollerith codes
for each.
2.7.2 LABEL FIELD. The label field begins in character position one of the source record and
extends to the first blank. The label field contains a symbol containing up to six characters the
first of which must be alphabetic. Additional characters may be any alphanumeric characters. A
label is optional for machine instructions and for many assembler directives. When the label is
omitted, the first character position must contain a blank. A source statement consisting of only a
label field is a valid statement; it has the effect of assigning the current location to the label. This is
usually equivalent to placing the label in the label field of the following machine instruction or assembler directive. However, when a statement consisting of a label only follows a TEXT or BYTE
directive and is followed by a DATA directive or a machine instruction, the label will not have the
value of a label in the following statement unless the TEXT or BYTE directive left the location
counter on an even (word) location. An EVEN directive following the TEXT or BYTE directive
prevents this problem.
2.7.3 OPERATION FIELD. The operation (opcode) field begins following the blank that terminates the label field, or in the first non-blank character position after the first character
position when the label is omitted. The operation field is terminated by one or more blanks, and
may not extend past character position 60 of the source record. The operation field contains an
opcode, one of the following:
•
Mnemonic operation code of a machine instruction
•
Assembler directive operation code
•
Symbol assigned to an extended operation by a DXOP directive
•
Pseudo-instruction operation code
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1
*
OPERAND
OPER
LABEL
6
8
"
C 0 N V E N T I o N A L S 0 U R C E S T A T E ME N T F 0 R MA T ""
13
11
v;;;
COMMENTS
25 26
21
30
35
45
~
50
55
W
~
~
60
1
S T ART
LI
3 ,
A
5 , 3
>
L0 AD
25
ADD
RT
R
W
\0
-.J
o
3
TO
WR 5
RE T URN T 0
WR3
C A L L I N G P R o G RAM
i
*
P AC KE D S 0 UR C E
S T ART ~ L I ~ 3
~
, >
DD
~
A~ 5 , 3
~
R T ~ ~ R E T URN
~A
S T A T E ME N T
2 5 ~ L oAD
HR5
TO
W
F 0 R MA T
US I NG T A B S
R 3
WR3
N
T0
P R o G RAM
C A L L I NG
~
~
~
S~
~
~
~
Cit
SC\
~
~
PROGRAM
-------
CHARGE
PROGRAMMED BY
--
-----
-
-
--
---.----~-.-
------------
(A) 132203 A
~
~
~
Figure 2-8. Source Statement Formats
PAGE
------------- - - - -
Of'
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2.7.4 OPERAND FIELD. The operand field begins following the blank that terminates the
operation field, and may not extend past character position 60 of the source record. The
operand field may contain one or more expressions, terms, or constants, according to the
requirements of the opcode. The operand field is terminated by one or more blanks.
2.7.5 COMMENT FIELD. The comment field begins following the blank that terminates the
operand field, and may extend to the end of the source record if required. The comment field
may contain any ASCII character, including blank. The contents of the comment field are listed
in the source portion of the assembly listing and have no other effect on the assembly.
2.8 EXPRESSIONS
Expressions are used in the operand fields of assembler directives and machine instructions. An
expression is a constant or symbol, or a series of constants, a series of symbols, or a series of
constants and symbols separated by arithmetic operators. Each constant or symbol may be
preceded by a minus sign (unary minus). An expression may contain no embeded blanks, or
symbols that are defined as extended operations. Symbols that are defined as external references
may not be operands of arithmetic operations. For PX9ASM, only one symbol in an expression
may be subsequently defined in the program, and that symbol must not be part of an operand in
a multiplication or division operation within the expression. For the Cross Assembler, TXMIRA,
and SDSMAC, an expression may contain more than one symbol that is not previously defined.
When these symbols are absolute, they may also be operands of multiplication or division operations within an expression. In all assemblers, an expression that contains a relocatable symbol or
relocatable constant immediately following a multiplication or division operator is an illegal expression. Also, when the result of evaluating an expression up to a multiplication or division
operator is relocatable, the expression is illegal. An expression in which the number of relocatable
symbols or constants added to the expression exceeds the number of relocatable symbols or constants subtracted from the expression by more than one is an illegal expression.
If NA = Number of relocatable values added and
NS = Number of relocatable values subtracted and
Then if
0 The expression is absolute
NA - NS = { 1 The expression is relocatable .
Other than 0 or I, the expression is illegal
An expression containing relocatable symbols or constants of several different relocation types
(see Section VIII) is absolute if it is absolute with respect to all relocation types. If it is relocatable
with respect to one relocation type and absolute with respect to all other relocation types, then the
expression is relocatable. For example, the expression
RED + BLUE - GREEN + 2
is program-relocatable if BLUE is a program-relocatable Symbol and the symbols RED and GREEN
are both data-relocatable. If the symbols RED, BLUE, and GREEN were program-relocatable,
data-relocatable, and common-relocatable, respectively, the expression would be invalid. TXMIRA
and PX9ASM only support program-relocatable symbol.
In TXMIRA, if the current value of an expression is relocatable with respect to one relocation type,
a symbol of another relocation type may not be included until the value of the expression becomes
absolute. For example, the expression
BLUE - GREEN - RED
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would be valid if BLUE and GREEN are of the same relocation type but would be invalid otherwise.
The following are examples of valid expressions:
BLUE+ I
The sum of the value of symbol BLUE plus 1.
GREEN-4
The result of subtracting 4 from the value of symbol GREEN.
2*16+RED
The sum of the value of symbol RED plus the product of 2 times 16.
440/2-RED
The result of dividing 440 by 2 and subtracting the value of symbol
RED from the quotient. RED must be absolute.
2.8.1 WELL-DEFINED EXPRESSIONS. Some assembler directives require well-defined expressions in the operand fields. For an expression to be well-defined, any symbols or assembly-time
constants in the expression must have been previously defined. Also, the evaluation of a
well-defined expression must be absolute, and a well-defined expression may not contain a
character constant.
2.8.2 ARITHMETIC OPERATORS. The arithmetic operators in expressions are as follows:
•
+ for addition
•
- for subtraction
•
* for multiplication
•
/ for signed division
•
/ / for logical right shift (SDSMAC only)
In evaluating an expression, the assembler first negates any constant or symbol preceded by a
unary minus, then performs the arithmetic operations from left to right. The assembler does not
assign precedence to any operation other than unary minus. All operations are integer operations.
The assembler truncates the fraction in division.
For example, the expression 4+5*2 would be evaluated 18, not 14, and the expression 7+1/2
would be evaluated 4, not 7.
The logical right shift operator (/ /) allows a logical division by a power of two.
Examples:
>80001/1 = >4000
>FFFF //0 = >FFFF
>AAAB//l = >5555
>FFFF //16 = >0000
SDSMAC checks for overflow conditions when arithmetic operations are performed at assembly
time and gives a warning message whenever an overflow occurs, or when the sign of the result is
not as expected in respect to the operands and the operation performed. Examples where a VALUE
TRUNCATED message is given are:
>4000*2
>8000*2
>7FFF+l
>8000-1
-1 *>8000
-2*>8001
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2.9 CONSTANTS
Constants are used in expressions. The assemblers recognize four types of constants: decimal
integer constants, hexadecimal integer constants, character constants, and assembly-time constants.
2.9.1 DECIMAL INTEGER CONSTANTS. A decimal integer constant is written as a string of
numerals. The range of values of decimal integers is -32,768 to +65,535. Positive decimal integer
constants greater than 32,767 are considered negative when interpreted as two's complement
values. Operands of arithmetic instructions other than multiply and divide are interpreted as two's
complement numbers, and all comparisons compare numbers both as signed and unsigned values.
The following are valid decimal constants:
WOO
Constant, equal to 1000 or 3E8 16 .
-32768
Constant, equal to -32768 or 8000 16 .
25
Constant, equal to 25, or 19 16 .
2.9.2 HEXADECIMAL INTEGER CONSTANTS. A hexadecimal integer constant is written as a
string of up to four hexadecimal numerals preceded by a greater than (» sign. Hexadecimal
numerals include the decimal values 0 through 9 and the letters A through F.
The following are valid hexadecimal constants:
>78
Constant, equal to 120, or 78 16 .
>F
Constant, equal to 15, or F 16.
>37AC
Constant, equal to 14252 or 37AC 16 .
2.9.3 CHARACTER CONSTANTS. A character constant is written as a string of one or two
characters enclosed in single quotes. For each single quote required within a character constant,
two consecutive single quotes are required to represent the quote. The characters are represented
internally as eight-bit ASCII characters, with the leading bit set to zero. A character constant
consisting only of two single quotes (no character) is valid, and is assigned the value 0000 16 .
The following are valid character constants:
'AB'
Represented internally as 4142 16 •
'C'
Represented internally as 0043 16 .
'N'
Represented internally as 004E 16 ·
Represented internally as 2744 16 .
2.9.4 ASSEMBLY-TIME CONSTANTS. An assembly-time constant is written as an expression in
the operand field of an EQU directive, described in a subsequent paragraph. When using TXMIRA
or PX9ASM, any symbol in the expression must have been previously defined. The value of the
label is determined at assembly time, and is considered to be absolute or relocatable according to
the relocatability of the expression, not according to the relocatability of the location counter value.
'''0'
2.10 SYMBOLS
Symbols are used in the label field, the operator field, and the operand field. A symbol is a
string of alphanumeric characters, (A through Z and 0 through 9), the first of which must be an
alphabetic character (A through Z), and none of which may be a blank. When more than six
characters are used in a symbol, the assembler prints all the characters, but accepts only the first
six characters for processing. User-defined symbols are valid only during the assembly in which
they are defined.
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Symbols used in the label field become symbolic addresses. They are associated with locations in
the program, and must not be used in the label field of other statements. Mnemonic operation
codes and assembler directive names are valid user-defined symbols when placed in the label field.
NOTE
When using SDSMAC, the ';' and '$' characters are
alphabetic.
The DXOP directive defines a symbol to be used in the operator field.
the operand field must be placed in the label field of a statement, or in
directive except for a symbol in the operand field of a DXOP
symbol.
considered
Any symbol that is used in
the operand field of a REF
directive or a predefined
2.11 PREDEFINED SYMBOLS
The predefined symbols are the dollar sign character ($) and the workspace register symbols.
the dollar sign character is used to represent the current location within the program. The
workspace register symbols are as follows:
Value
Symbol
RO
Rl
R2
R3
0
1
2
3
Symbol
R4
R5
R6
R7
Symbol
Value
R8
R9
RIO
Rll
4
5
6
7
Value
8
9
10
11
Symbol
R12
R13
R14
R15
Value
12
13
14
15
NOTE
The workspace register symbols (RO, RI ... ) are normally undefined in PX9ASM and TXMIRA. However, they can be optionally
defined.
The following are examples of valid symbols:
START
Assigned the value of the location at which it appears
in the label field.
Al
Assigned the value of the location at which it appears
in the label field.
OPERATION
OPERAT is assigned the value of the location at which
it appears in the label field.
$
Represents the current location.
2.12 TERMS
Terms are used in the operand fields of machine instructions and an assembler directive. A term
is a decimal or hexadecimal constant, an absolute assembly-time constant, or label having an
absolute value.
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The following are examples of valid terms:
12
The value is 12, or C16 .
>C
The value is 12, or C16 •
WR2
Valid if WR2 is defined having an absolute value.
R3
Predefined as a value of 3.
If START were a relocatable symbol, the following statement would not be valid as a term:
WR2
EQU
START+4
WR2 would be a relocatable value 4 greater than the
value of START. Not valid as a term, but valid as
a symbol.
2.13 CHARACTER STRINGS
Several assembler directives require character strings in the operand field. A character string is
written as a string of characters enclosed in single quotes. For each single quote in a character
string, two consecutive single quotes are required to represent the required single quote. The
maximum length of the string is defined for each directive that requires a character string. The
characters are represented internally as eight-bit ASCII characters, with the leading bits set to
zeros. Appendix A gives a complete list of valid characters within character strings.
The following are valid character strings:
Defines a 14-character string
consisting of:
SAM P L E h PRO G RAM.
'SAMPLE PROGRAM'
'PLAN
Defines an 8-character string
consisting of:
PLANb'C'.
"c'"
'OPERATOR MESSAGE
* PRESS
START SWITCH'
2-17/2-18
Defines a 37-character string
consisting of the expression
enclosed in single quotes.
Texas Instruments Incorporated
~------~
943441-9701
SECTION III
ASSEMBLY INSTRUCTIONS
3.1 GENERAL
This section describes the mnemonic instructions of the assembly language for the PX9ASM,
TXMIRA and SDSMAC assemblers, and for the Cross Assember. Detailed assembly instruction
descriptions follow descriptions of the addressing modes used in the assembly language and the
addressing formats of the assembly instructions. The section also includes examples of programming
the various instructions.
3.2 ADDRESSING MODES
One of five addressing modes may be used in the instructions that specify a general address for
the source or destination operand. Table 3-1 lists these modes and shows how each is used in the
assembly language. Each of the modes is described in a subsequent paragraph.
Table 3-1. Addressing Modes
Addressing Mode
T field value
(Note 1)
Workspace Register
o
Workspace Register
Indirect
Note
Example
5
*7
Symbolic Memory
2
@LABEL
2,3
Indexed Memory
2
@LABEL(S)
2,4
Workspace Register
Indirect Autoincrement
3
*7+
Notes:
1. The T field is described in the addressing format descriptions.
2. The instruction requires an additional word for each T field
value of 2. This word contains a memory address.
3. The S or D field is set to zero by the assembler.
4. Workspace register 0 cannot be used for indexing.
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3.2.1 WORKSPACE REGISTER ADDRESSING. Workspace register addressing specifies a workspace register that contains the operand. A workspace register address is written as a term having
a value of 0 through 15.
The following examples show the coding of instructions that have two workspace register
addresses each:
MOV R4,RS
Copy the contents of workspace register 4 into
workspace register S.
COC RlS,RIO
Compare the bits of workspace register 10 that
correspond to the one bits in workspace register
15 toone.
3.2.2 WORKSPACE REGISTER INDIRECT ADDRESSING. Workspace register indirect addressing specifies a workspace register that contains the address of the operand. An indirect workspace
register address is written as a term preceded by an asterisk (*). The following example shows
coding of instructions having workspace register indirect addresses.
A *R7,*R2
Add the contents of the word at the address in
workspace register 7 to the contents of the word
at the address in workspace register 2, and place
the sum in the word at the address in workspace
register 2.
MOV *R7,RO
Copy the contents of the address in workspace
register 7 into workspace register O.
3.2.3 SYMBOLIC MEMORY ADDRESSING. Symbolic memory addressing specifies the memory
address that contains the operand. A symbolic memory address is written as an expression preceded
by an at sign (@). The following are coding examples of instructions having symbolic memory
addresses:
S
@TABLEl,@LIST4
Subtract the contents of the word at location TABLE 1
from the contents of the word at location LIST4, and
place the remainder in the word at location LIST4.
C RO,@STORE
Compare the contents of workspace register 0 with
the contents of the word at location STORE.
MOV
Copy the word at address OOOC 16 into location 007C 16 •
@12,@>7C
NOTE
When using SDSMAC, symbols previously defined as having
relocatable values or values greater than 15 need not have the '@'.
3.2.4 INDEXED MEMORY ADDRESSING. Indexed memory addressing specifies the memory
address that contains the operand. The address is the sum of the contents of a workspace register
and a symbolic address. An indexed memory address is written as an expression preceded by an at
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sign and followed by a term enclosed in parentheses. The workspace register specified by the term
within the parentheses is the index register. Workspace register 0 may not be specified as an index
register. the following are examples of coding of instructions having indexed memory addresses:
A @2(R7),R6
Add the contents of the word at the address computed
by adding the contents of workspace register 7 and
2 to the contents of workspace register 6, and place
the sum in workspace register 6.
MOV R7,@LIST4-6(R5)
Copy the contents of workspace register 7 into a
word of memory. The address of the word of memory
is the sum of the contents of workspace register 5
and the value of symbol LIST4 minus 6.
3.2.5 WORKSPACE REGISTER INDIRECT AUTO-INCREMENT ADDRESSING. Workspace
register indirect auto-increment addressing specifies a workspace register that contains the address
of the operand. After the address is obtained from the workspace register, the workspace register
is incremented by 1 for a byte instruction or by 2 for a word instruction. The workspace register
increment is one for byte operations and two for word operations. A workspace register autoincrement address is written as a term preceded by an asterisk and followed by a plus sign (+).
The following are coding examples of instructions having workspace register indirect auto-increment
addresses:
S *R3+,R2
Subtract the contents of the word at the address in
workspace register 3 from the contents of workspace
register 2, place the result in workspace register
2, and increment the address in workspace register
3 by two.
C
Compare the contents of workspace register 5 with
the contents of the word at the address in workspace
register 6, and increment the address in workspace
register 6 by two.
R5,*R6+
3.3 PROGRAM COUNTER RELATIVE ADDRESSING
Program counter relative addressing is used by the jump instructions. A program counter relative
address is written as an expression that corresponds to an address at a word boundary. The
assembler evaluates the expression and subtracts the sum of the current location plus two.
One-half of the difference is the value that is placed in the object code. This value must be in
the range of -128 through + 127. When the instruction is in relocatable code (that is, when the
location counter is relocatable), the relocation type of the evaluated expression must match the
relocation type of the current location counter. When the instruction is in absolute code, the
expression must be absolute. The following example shows a program counter relative address:
JMP
THERE
Jumps unconditionally to location THERE.
3.4 CRU BIT ADDRESSING
The CRU bit instructions use a well-defined expression that represents a displacement from the
CRU base address (bits 3 through 14 of workspace register 12). The displacement, in the range
of -128 through + 127, is added algebraically to the base address in workspace register 12. The
following are examples of CRU bit instructions having CRU bit addresses:
SBO
8
Sets CRU bit to one at the CRU address 8 greater
than the CRU base address. If workspace register
12 contained 0020 16 , CRU bit 24 would be set
by this instruction. (24 = (2016 /2) + 8)
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SBZ
Sets CRU bit to zero. Assuming that DTR has the
. value lO, and workspace register 12 contains 0040 16 ,
the instruction sets bit 42 to zero. (42 = (40 16 /2) + 10)
DTR
3.5 IMMEDIATE ADDRESSING
Immediate instructions use the contents of the word following the instruction word as an
operand of the instruction. The immediate value is an expression, and the value of the expression
is placed in the word following the instruction by the assembler. Those immediate instructions
that require two operands have a workspace register address preceding the immediate value. The
following are examples of coding immediate instructions:
LIMI 5
Places 5 in the interrupt mask, enabling interrupt
levels 0 through 5.
LI R5,>1000
Places 1000 16 into workspace register 5.
NOTE
When using SDSMAC, an @ sign may proceed an immediate
operand.
3.6 ADDRESSING SUMMARY
Table 3-2 shows the addressing required for each instruction of the Model 990/TMS 9900
instruction set. The first column lists the instruction mnemonics, and the second column lists the
effectivity of the instruction. This column contains A for those instructions that apply to the
Model 990/TMS 9900, and C for those instructions that apply to the Model 990 but not to the
TMS 9900. The column contains M for those instructions that apply only to the Model 990
Computers with mapping option. The third and fourth columns specify the required address,
as follows:
•
G - General address:
Workspace register address
Indirect workspace register address
Symbolic memory address
Indexed memory address
Indirect workspace register auto-increment address
•
WR - Workspace register address
•
PC - Program counter relative address
•
CRU - CRU bit address
•
I - Immediate value
•
* - The
address into which the result is placed, when two operands are required.
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Table 3-2. Instruction Addressing
Mnemonic
A
AB
ABS
AI
ANDI
B
BL
BLWP
C
CB
CI
CKOF
CKON
CLR
COC
CZC
DEC
DECT
DIV
IDLE
INC
INCT
INV
JEQ
JGT
JH
JHE
JL
JLE
JLT
lMP
JNC
JNE
JNO
JOC
JOP
Eff.
A
A
A
A
A
A
A
A
A
A
A
C
C
A
A
A
A
A
A
C
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
First
Operand
Second
Operand
G
G
G
WR*
WR*
G
G
G
G
G
WR
G*
G*
G
G
G
G
G
G
Mnemonic
LDCR
LDD
LDS
LI
LIM I
LMF
LREX
LWPI
MOV
MOVB
MPY
NEG
ORI
RSET
RTWP
S
SB
SBO
SBZ
SETO
SLA
SOC
SOCB
SRA
SRC
SRL
STCR
STST
STWP
SWPB
SZC
SZCB
TB
X
XOP
XOR
I
I
G
G
WR
WR
WR*
G
G
G
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
Eff.
A
M
M
A
A
M
C
A
A
A
A
A
A
C
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
First
Operand
Second
Operand
G
G
G
WR*
I
WR*
Note 1
I
G
G
G
G
WR*
G
G
CRU
CRU
G
WR*
G
G
WR*
WR*
WR*
G*
WR
WR
G
G
G
CRU
G
G
G
Note 2
G*
G*
WR*
G*
G*
Note
G*
G*
Note
Note
Note
Note
3
3
3
3
1
G*
G*
Note 4
WR*
Notes:
1. The second operand is the number of bits to be transferred, 0-15, 0 = 16 bits.
2. The second operand specifies a memory map file, 0 or 1.
3. The second operand is the jhift cQunt, 0 - 15. 0 means count is in bits 12 - 15 of workspace
register O. When count = 0 and bits 12 - 15 of workspace register 0 = 0, count is 16.
4. Second operand specifies the extended operation, 0 - 15. Disposition of result mayor may
not be in the first operand address, determined by the user.
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3.7 ADDRESSING FORMATS
The required addressing previously described relates to the ten addressing formats of the Model
990 Computer/TMS 9900 Microprocessor. These formats are shown and described in the following paragraphs.
3.7.1 FORMAT 1- TWO ADDRESS INSTRUCTIONS. The operand field of Format I instructions contains two general addresses separated by a comma. The first address is the source
address; the second is the destination address. The following mnemonic operation codes use
Format I.
A
MOV
soc
AB
MOVB
SOCB
C
S
SZC
CB
SB
SZCB
The following example shows a source statement for a Format I instruction:
SUM
A
@LABELl,*R7
Adds the contents of the word at location LABELl to
the contents of the word at the address in workspace
register 7, and places the sum in the word at the
address in workspace register 7. SUM is the location
in which the instruction is placed.
The assembler assembles Format I instructions as follows:
Iii
o
2
3
4
5
6
OP CODE
8
7
9
I
D
10
I
1112
Ts
13
14
~
15
I
The bit fields are:
•
Op Code - Three bits that define the machine operation.
•
B - Byte indicator, 1 for byte instructions, 0 for word instructions.
•
T d - Addressing mode (table 3-1) for destination.
•
D - Destination workspace register.
•
Ts - Addressing mode (table 3-1) for source.
•
S - Source workspace register.
When Ts or Td is equal to 10 2 , the instruction occupies two words of memory, and the second
word contains a memory address used with S or D, respectively, in developing the effective
address. When both Ts and Td are equal to 10 2 , the instruction occupies three words of
memory. The second word contains the memory address for the source operand, and the third
word contains the memory address for the destination operand.
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3.7.2 FORMAT II - JUMP INSTRUCTIONS. Format II instructions use program counter relative
addresses which are coded as expressions that correspond to instruction locations on word
boundaries. The following mnemonic operation codes are Format II jump instructions:
JEQ
JLE
JNE
JGT
JLT
JNO
JR
JMP
JOC
JRE
JNC
JOP
JL
The following is an example of a source statement for a Format II jump instruction:
Jumps unconditionally to the instruction at location
BEGIN. The address of location BEGIN must not be
greater than the address of location NOW by more
than 127 words, nor less than the address of location
NOW by more than 128 words.
NOW JMP @BEGIN
The assemblers assemble Format II instructions as follows:
o
2
3
4
5
6
7
8
9
10
i i i
OP CODE
11 12 13-14
iii
I
15
DISPLACEMENT
The bit fields are:
•
Op Code - Eight bits that define the machine operation.
•
Displacement - Signed displacement value.
The signed displacement value is shifted one bit position to the left and added to the contents of
the PC after the PC has been incremented to the address of the following instruction. In other
words, it is a displacement in words from the sum of the instruction address plus two.
3.7.3 FORMAT II - BIT I/O INSTRUCTIONS. The operand field of Format II CRU bit I/O
instructions contains a well-defined expression. It is a CRU bit address, relative to the contents
·of workspace register 12. The following mnemonic operation codes are Format II CRU bit I/O
instructions:
SBZ
SBO
TB
The following example shows a source statement for a Format II CRU bit I/O instruction:
SBO
5
Sets a CRU bit to one. If workspace register 12 contains
10 16 , CRU bit 13 is set by this instruction.
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The format assembled for Format II instructions is shown and described in the preceding
paragraph. For CRU bit instructions the signed displacement is shifted one bit position to the
left and added to the contents of workspace register 12. In other words, it is a displacement in
bits from the contents of bits 3 through 14 of workspace register 12.
3.7.4 FORMAT III - LOGICAL I~STRUCTIONS. The operand field of Format III instructions
contains a general address followed by a comma and a workspace register address. The general
address is the source address, and the workspace register address is the destination address. The
following mnemonic operation codes use Format III:
COC
CZC
XOR
The following example shows a source statement for a Format III instruction:
COMP XOR @LABEL8(R3),RS
Perform an exclusive OR operation of the contents
of a memory word and the contents of workspace
register 5, and place the result in workspace
register S. The address of the memory word is
the sum of the contents of workspace register 3
and the value of symbol LABEL8.
The assemblers assemble Format III instructions as follows:
o
2
3
I
4
5
6
7
8
9
10
11
1213
14
15
I
OP CODE
D
Ts
s
The bit fields are:
•
Op Code - Six bits that define the machine operation.
•
D - Destination workspace register.
•
Ts - Addressing mode (table 3-1) for source.
•
S - Source workspace register.
When Ts is equal to 10 2 , the instruction occupies two words of memory. The second word
contains the memory address for the source operand.
3.7.5 FORMAT IV - CRU INSTRUCTIONS. The operand field of Format IV instructions
contains a general address followed by a comma and a well defined expression. The general address
is the memory address from which or into which bits will be transferred. The CRU address for the
transfer is the contents of bits 3 through 14 of workspace register 12. The term is the number of
bits to be transferred, a value of 0 through 15 (a 0 value transfers 16 bits). For 8 or fewer bits the
effective address is a byte address. For 9 or more bits the effective address is a word address. The
following mnemonic operation codes use Format IV:
LDCR
STCR
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The following example shows a source statement for a Format IV instruction:
LDCR *R6+,8
Place 8 bits from the byte of memory at the address
in workspace register 6 into eight consecutive CRU
lines at the CRU base address in workspace register
12.
The assemblers assemble Format IV instructions as follows:
o
234
5
6
7
8
9
10
11 12
13
.14
15
I
OP CODE
C
5
TS
The bit fields are:
•
Op Code - Six bits that define the machine operation.
•
C - Four bits that contain the bit count.
•
Ts - Addressing mode (table 3-1) for source.
•
S - Source workspace register.
When Ts is equal to 10 2 , the instruction occupies two words of memory. The second word
contains the memory address for the source operand.
3.7.6 FORMAT V - REGISTER SHIFT INSTRUCTIONS. The operand field of Format V
instructions contains a workspace register address followed by a comma and a well defined
expression. The contents of the workspace register are shifted a number of bit positions specified by
the term. When the term equals zero, the shift count must be placed in bits 12-15 of workspace
register O. The following mnemonic operation codes use Format V:
SLA
SRC
SRL
SRA
The following example shows a source statement for a Format V instruction:
SLA
Shift contents of workspace register 6 to the
left 4 bit positions, replacing the vacated bits
with zero.
R6,4
The assemblers assemble Format V instructions as follows:
o
2
3
4
5
6
7
8
9
10
11
12
13
14
15
I
OP CODE
C
w
The bit fields are:
•
Op Code - Eight bits that define the machine operation.
•
C - Four bits that contain the shift count.
•
W - Workspace register to be shifted.
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3.7.7 FORJ\1AT VI - SINGLE ADDRESS INSTRUCTIONS. The operand field of Format VI
instructions contains a general address. The following mnemonic operation codes use Format VI:
ABS
CLR
INCT
NEG
B
DEC
INV
SETO
BL
DECT
LDD
SWPB
BLWP
INC
LDS
x
The following example shows a source statement for a Format VI instruction:
Adds one to the contents of workspace register 7,
and places the sum in workspace register 7. CNT is
the location into which the instruction is placed.
CNT INC R7
The assemblers assemble Format VI instructions as follows:
o
2
3
4
~
5
I
7
8
9
10
1112
1314
15
I
s
OP CODE
The bit fields are:
•
Op Code - Ten bits that define the machine operation.
•
Ts - Addressing mode (table 3-1) for source.
•
S - Source workspace register.
When Ts is equal to 102 , the instruction occupies two words of memory. The second word
contains the memory address for the source operand.
3.7.8 FORMAT VII - CONTROL INSTRUCTIONS. Format VII instructions require no operand
field. The following operation codes use Format VII:
CKOF
IDLE
RSET
CKON
LREX
RTWP
The following example shows a source statement for a Format VII instruction:
Returns control to the calling program, and restores
the context of the calling program by placing the
contents of workspace registers 13, 14, and 15 into
the WP register, the PC, and the ST register.
RTWP
The assemblers assemble Format VII instructions as follows:
o
2
3
4
5
6
7
8
9
10
11
12
13
14
15
i
OP CODE
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The Op Code field contains eleven bits that define the machine operation. The five least
significant bits are zeros.
3.7.9 FORMAT VIII - IMMEDIATE INSTRUCTIONS. The operand field of Format VIII
instructions contains a workspace register address followed by a comma and an expression. The
workspace register is the destination address, and the expression is the immediate operand. The
following mnemonic operation codes use Format VIII:
AI
CI
ANDI
LI
ORI
There are two additional Format VIII instructions that require only an expression in the operand
field. The expression is the immediate operand. The destination is implied in the name of the
instruction. The following mnemonic operation codes use this modified Format VIII:
LIMI
LWPI
Another modification of Format VIn requires only a workspace register address in the operand
field. The workspace register address is the destination. The source is implied in the name of the
instruction. The following mnemonic operation codes use this modified Format VIII:
STST
STWP
The following are examples of source statement for Format VIII instructions:
ANDI
4,>OOOF
Perform an AND operation on the contents
of workspace register 4 and immediate operand
OOOF 16 •
LWPI
WRKI
Place the address defined for the symbol WRK I
into the WP register.
STWP
R4
Place the contents of the WP register into
workspace register 4.
The assemblers assemble Format VIII instructions as follows:
o
2
3
4
5
6
7
8
OP CODE
9
10
0
11
12 13
I I
0
14
15
W
The bit fields are:
•
Op Code - Eleven bits that define the machine operation.
•
W - Workspace register operand.
A zero bit separates the two fields. The instructions that have no workspace register operand
place zeros in the W field. The instructions that have immediate operands place the operands in
the word following the word that contains the Op Code; i.e., these instructions occupy two
words each.
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3.7.10 FORMAT IX - EXTENDED OPERATION INSTRUCTION. The operand field of a
Format IX Extended Operation instruction contains a general address and a well defined expression.
The general address is the address of the operand for the extended operation. The term specifies the
extended operation to be performed and must be in the range of to 15. The mnemonic operation
code is XOP.
°
The following example shows a source statement for a Format IX Extended Operation
instruction:
XOP @LABEL(R4), 12
Perform extended operation 12 using the address
computed by adding the value of symbol LABEL
to the contents of workspace register 4.
The assemblers assemble Format IX instructions as follows:
o
2
3
4
5
6
~p ~ODE
7
8
0
9
:
10
11
12
I I
T!
13
I
14
~
15
I
The bit fields are:
•
Op Code - Six bits that define the machine operation.
•
D - Four bits that define the extended operation.
•
Ts - Addressing mode (table 3-1) for source.
•
S - Source workspace register.
When Ts is equal to 10 2 , the instruction occupies two words of memory. The second word
contains the memory address for the source operand.
3.7.11 FORMAT IX - MULTIPLY AND DIVIDE INSTRUCTIONS. The operand field of
Format IX Multiply and Divide instructions contains a general address followed by a comma and
a workspace register address. The general address is the address of the multiplier or divisor, and
the workspace register address is the address of the workspace register that contains the
multiplicand or dividend. The workspace register address is also the address of the first of two
workspace registers to contain the result. The mnemonic operation codes are MPY and DIV.
The following example shows a source statement for a Format IX Multiply instruction:
MPY @ACC,R9
Multiply the contents of workspace register
9 by the contents of the word at location
.ACC, and place the product in workspace
registers 9 and 10, with the 16 least
significant bits of the product in workspace
register 10.
The assembler assembles Multiply and Divide instructions similarly to the format shown in the
preceding paragraph, except that the D field contains the workspace register operand.
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3.7.12 FORMAT X - MEMORY MAP FILE INSTRUCTION. This format applies only to the
Model 990 Computer with map option. The operand field of a Format X Memory Map File instruction contains a workspace register address followed by a comma and a well defined expression
which evaluates to either a 0 or a 1. The workspace register address specifies a workspace register
that contains the address of a six-word area of memory that contains the map file data. The term
specifies the map file into which the data is to be loaded. The mnemonic operation code is LMF.
The following example shows a source statement for a Format X Memory Map File instruction:
LMF
R4,0
Load memory map file 0 with the six-word
area of memory at the address in workspace
register 4.
The assembler assembles a Format X instruction as follows:
o
2.34567
B
9
10
"
12. 13 14
15
OP CODE
The bit fields are:
•
Op Code - Eleven bits that defme the machine operation.
•
M - A single bit that specifies a memory map file, 0 or 1.
•
W - Workspace register operand.
3.8 INSTRUCTION DESCRIPTIONS
The instruction descriptions in the following paragraphs are divided into the following functional
categories:
•
•
•
•
•
•
•
•
•
Arithmetic Instructions
Branch Instructions
Compare Instructions
Control and CRU Instructions
Load and Move Instructions
Logical Instructions
Shift Instructions
Extended Operation Instruction
Long Distance Addressing Instructions
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The syntax definition for each instruction is shown, using the conventions described in a
previous paragraph. The generic names used in these definitions are:
•
gas - General address of source operand
•
gad - General address of destination operand
•
wa - Workspace register address
•
iop - Immediate operand
•
wad - Destination workspace register address
•
disp - Displacement of CRU lines from the CRU base register
•
exp - Expression that represents an instruction location.
•
cnt - Count of bits for CRU transfer
•
m - Memory map file
•
scnt - Shift count
•
op - Number (0-15) of extended operation
Source statements that contain machine instructions use the label field, the operation field, the
operand field, and the comment field. Use of the label field is optional for machine instructions.
When the label field is used, the label is assigned the address of the machine instruction. The
assembler advances the location to a word boundary (even address) before assembling a machine
instruction. The operation (opcode) field contains the mnemonic operation code of the
instruction. The contents of the operand field is defined for each instruction. The use of the
comment field is optional. When the comment field is used, it may contain any ASCII character,
including blank, and has no effect on the assembly process other than to be printed in the
listing.
A description of the operation of the instruction follows the syntax definition. The status bits
affected by the instruction are listed. In the execution results, the following conventions are
used:
•
( ) Indicates "the contents of'
•
-+
•
II Indicates the absolute value
Indicates "replaces"
The generic names used in the syntax definitions are also used in the execution results.
Application notes are included, referring to a fuller explanation in the programming examples
paragraphs as appropriate.
The Op Code given for each instruction is a four hexadecimal digit number corresponding to an
instruction word in which the address fields contain zeros. Next is the addressing mode. The
instruction formats show the machine language form of the instruction, and use the terminology
previously defined for the addressing formats.
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3.9 ARITHMETIC INSTRUCTIONS
The arithmetic instructions are described in the following paragraphs. The instructions are:
Mnemonic
Instruction
3.10 ADD WORDS
Paragraph
Add Words
A
3.10
Add Bytes
AB
3.l1
Absolute Value
ABS
3.21
Add Immediate
AI
3.12
Decrement
DEC
3.19
Decrement by Two
DECT
3.20
Divide
DIV
3.16
Increment
INC
3.17
Increment by Two
INCT
3.18
Multiply
MPY
3.15
Negate
NEG
3.22
Subtract Words
S
3.13
Subtract Bytes
SB
3.14
A
Op Code: AOOO
Addressing mode: Format I
Format:
6
Syntax definition:
[