1977_National_Memory_Databook 1977 National Memory Databook
User Manual: 1977_National_Memory_Databook
Open the PDF directly: View PDF 
.
Page Count: 566
| Download | |
| Open PDF In Browser | View PDF |
~_Nationai
~ Semiconductor
Edge Index
by Product Family
This is National's 1917 Memory handbook containing information on MOS and Bipolar Memory
Components, Systems, Application Notes and Support Circuits. For detailed information on Interface
Circuits and other major product lines, contact a National sales office, representative, or distributor.
MOS RAMs
D
Bipolar PROMs
fAIl
D
91
GIl
MOS ROMs
-[;II
Bipolar ROMs
III
Shift Registers
[;J
Bipolar RAMs
CMOS RAMs
MOS EPROMs
Memory Systems
Interface
App Notes/Briefs
0
1m
-ill
© National Semiconductor Corporation
2900
Semiconductor
Drive,
San~a
Manufactured under one or more of the following U.S. patents:
Clara,
California
3083262,
3381071,
3519897,
3579059,
3633052,
95051,
(40il) 737-5000/TWX (910) '339-9240
National does not assume any responsibility for
USB
of any circuitry
described; no circuit patent licenses ar. implied, and National'
reserves the right, at any time without notice. to change said circuitry_
2
3189758,
3408542,
3557431,
3593069,
3638131,
3231797,
3421025,
3560765,
3597640,
3648071,
3303356,
3426423,
3566218,
3607469,
3651565,
3317671,
3440498,
3571630,
3617859,
3693248,
3323071,
3518750,
3575609,
3631312,
Table of Contents
Edge Index by Product Family ............................... , . . ..
Alpha·Numerical Index ...................................... ; . . .
RAM Cross Reference Guide .......................... ; . . . . . . . . ...
Bipolar RAM Cross Reference Guide ............... , . . . . . . . . . . . . . . . .
Bipolar PROM Cross Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bipolar PROM/ROM Selection Guide. . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .
...................
...................
...................
...................
. . . . . . . . . . .. . . . . . . .
...................
..
..
..
..
..
..
1
9
13
14
15
16
MM1101, MM11011 256·Bit (256 xl) Static. . .. .. . . . .. . .. . . .. .. . . . . . . . . .. . . .. .. . . . .. . .. . .
MM1101A, MM1101A1, MMll01A2 256·Bit (256x 1) Static.. ... .. ........... . ..... .........
MM2101, MM2101·1, MM2101·2 1024·Bit (256 x 4) Static with Separate I/O........... . .........
MM2102, MM2102·1, MM2102·2 1024·Bit (1024 xl) Static... ... ............................
MM2102A, MM2102AL Family 1024·Bit (1024 x 11 Static ...................................
MM2102MD, MM2102·2MD 1024.Bit(1024x 1) Static, Military Temperature Range ...............
MM2111, MM2111·1, MM2111·2 1024·Bit (256 x 4) Static with Common Data I/O. . . . . . . . . . . . . ...
MM2112, MM2112·21024·Bit (256 x 4) Static with Common Data I/O .........................
MM4250 256·Bit (256 xl) Static, Military Temperature Range. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .
MM5269 1024·Bit (256 x 4)Static with On·Chip Registers ............... ; . . . . . . . . . . . .. . . . . ..
MM42704096·Bit (4096 xl) TRI·SHARETM Port, Dynamic .................................
MM5270 4096·Bit (4096 xl) TRI·SHARPM Port, Dynamic .................................
MM5270A 4096·Bit (4096 x 1) Dynamic, ..... , ..............................•..... ; .....
MM5270·5 4096·Bit(4096 xl) TRI·SHARETM Port, Dynamic ........................... , . . ..
MM5271 4096·Bit (4096 x 1) Fully TTL Compatible, Dynamic ..•............ , ............ " ..
MM5271A 4096·Bit (4096 xl) rRI·SHARETM Port, Dynamic .......................... " .. ..
MM4280 4096·Bit (4096 xl) Dynamic . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . ..
MM5280 4096·Bit (4096 x 1) Dynamic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5280A 4096·Bit (4096 x 1) Dynamic.. . . .. .. .. .. .. .. .... . . . . ... ..... .. . . ... . . . . .. ....
MM5280·54096·Bit (4096 x 1) Dynamic .................................................
MM5281 4096·Bit (4096 x 1) Fully TTL Compatible, Dynamic. .. .. . . .. ... . .. . . . . .. . . . ... . ....
MM5290 16,384~Bit(16,384 x 1) Dynamic ........................................... _...
1·1
1·1
1·5
1·8
1·12
1·15
1·19
1·22
1·1
1·26
1·28
1·33
1·38
'·44
1-46
1·51
1·56
1·60
1·64
1·70
1-72
1·76
Section 1-MOS RAMs
Section 2-Bipolar RAMs
DM5489/DM7489 64-Bit (16 x 4) Open·Coliector . . . . . . . . . .. . . .. . . . . . . . . . . . . . .. . . . . . . . . . . . . 2·1
DM54LS189/DM74LS189 64·Bit (16 x 4) TRI-STATE®, Low Power Schottky. ... . . ... . .. .. . ... . 2·4
DM54S189/DM74S189 64·Bit (16 x 4) TRI·STATE® Schottky............ _. . . . .. . .. . . . .. . .. . . 2-7
DM54S200/DM74S200 256·Bit (256 x 1) TRI·STATE® Schottky .....••....................... 2;11
DM54S206/DM74S206 256·Bit (256 x 1) Open-Collector Schottky ..... _.................... , .. 2·15
DM54LS289/DM74LS289 64·Bit (16 x 4) Open·Coliector, Low Power Schottky ........ , ......... 2·19
3
Table of Contents
(Continued)
Section 2-Bipolar RAMs
(Continued)
DM54S289/DM74S289 64-Bit (16 x 4) Open-Collector Schottky. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-22
2-25
DM7599/DM859964-Bit (16 x 4) TRI-STATE® .•.•....................................... 2-29
DM93415, DM93415A 1024-Bit (1024 x 1) TTL, Fully Decoded. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-33
DM93425, DM93425A 1024-Bit (1024 x 1) TTL, Fully Decoded .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-34
DM85S68 64-Bh OEix 4) S·chottky Edge-Trig9~i:ed Register. : .............................. "
Section 3-CMOS RAMs
MM54C89/MM74C89 64-Bit (16 x 4lTRI-STATE® ........................ _... . .... ........
MM54C200/MM74C200 256-Bit (256 xl) TR I-STATE® ..•...............•. _. . . . . . . . . . . . . . . .
MM54C91O/MM74C910 256-Bit (256 xl) TRI-STATE®.. . ...... .. .. . . .. .... ... ... .. . .......
MM54C920/MM74C920 1024-Bit (256 x 4) Static Silicon Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM54C921/MM74C921 1024-Bit (256 x 4) Static Silicon Gate ........ : . . . . . . . . . . . . . . . . . . . . . ..
MM54C929/MM74C929 1024-Bit (1024 x 1) Static Silicon Gate ...............................
MM54C930/MM74C930 1024-Bit (1024 x 1) Static Silicon Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-1
3-5
3-8
3-12
3-12
3-19
3-19
Section 4-MOS EPROMs
MM1702A 2048-Bit (256 x 8) Electrically Programmable and Erasable ROM. . .. .. .. . ... .. ..... . ..
4-1
MM2704 4096-Bit (512 x 8) UV Erasable and Electrically Programmable ................ '.' . . . . . . 4-7
MM2708 8192.Bit (1024 x 8) UV Erasable and Electrically Programmable. . . . . . . . .. . . . . . . . . . . . . . 4-7
MM4203/MM5203 2048-Bit (256 x 8 or 512 x 4) Electrically Programmabie and Erasable ROM ....... 4-12
MM4:t041MM5204 4096-Bit (512 x 8) Electrically Programmable and Erasable ROM . . . . . . . . . . .. . .. 4-17
Section 5-Bipolar PROMs
PROM Programming Procedure.... .. .. .. .. ......... ..... . . .. ..... . . .... . . . ..... .... ....
DM54S188/DM74S188 256-Bit (32 x 8) Open-Collector Schottky........ .... . . . . .. .... ........
DM54S287/DM74S287 1024-Bit (256 x 4) TRI-STATE® Schottky.. .. ... . .... . . . ..... . .... ....
DM54S288/DM74S288 256-Bit (32 x 8) TRI-STATE® Schottky ............................ ,.
DM54S387/DM74S387 1024:Bit (2!56x 4) qpen·Coliector Schottky .............. " .. . .........
DM54S470/DM74S470 2048-Bit (256 x 8) Open·Collector Schottky. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S471/DM74S471 2048-Bit.(256 x 8) TRI-STATE® Schottky.... .. . . . .. . . . . ..... .........
DM54S472/DM74S472 4096-Bit (512 x 8) TRI-STATE® Schottky .............................
DM54S473/DM74S473 4096-Bit (512 x 8) Open-Collector Schottky ............................
DM54S570/DM74S570 2048-Bit (512 x 4) Open-Collector Schottky........... , ................
DM54S571/DM74S571 2048-Bit (512 x 4) TRI·STATE® Schottky.............................
DM54S572/DM74S572 4096-Bit (1024 x 4) Open-Collector Schottky. . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54S573/DM74S573 4096-Bit (1024 x 4) TRI·STATE® Schottky............................
DM7577/DM8577 256-Bit (32 x 8) Open-Collector. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7578/DM8578 256-Bit (32 x 8) TRI-STATE® .............. , ...........................
DM77S221/DM87S221 2048·Bit (256 x 8) Open·Collector Schottky with Latches. . . . . . . . . . . . . . . ..
DM77S222/DM87S222 2048-Bit (256 x 8) TRI·STATE® Schottky with Latches ..................
DM77S228/DM87S228 8192·Bit (1024 x 8) TRI-STATE® Schottky............................
DM77S229/DM87S229 8192-Bit (1024 x 8) Open-Collector Schottky. . . . . . . . . . . . . . . . . . . . . . . . . ..
DM77S295/DM87S295 4096-Bit (512 x 8) Open-Collector Schottky. . . . . . . . . . . . . . . . . . . . .. . . . . ..
DM77S296/DM87S296 4096-Bit (512 x 8) TRI-STATE® Schottky.............................
5-1
5-2
5-4
5-2
5·4
5-9
5-9
5-11
5-11
5-13
5-13
5·18
5-18
5-20
5-23
5-26
5-26
5-28
5-28
5-30
5-30
Section 6-MOS ROMs
MM 1742 2048-Bit (256 x 8) Electrically Programmable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM2316A 16,384-Bit (2048 x 8) Mask Programmable ..•....................................
MM4210/MM5210 1024-Bit (256 x 4) Mask Programmable ... , ...............................
MM4211/MM52111024-Bit (256 x 4) Mask Programmable ...................................
MM5212 12,2BB-Bit (1 k x 12) Mask Programmable ....•....................................
MM4213/MM5213 2048-Bit (256 x 8 or 512 x 4) Mask Programmable ..........................
MM4214/MM5214 4096-Bit (512 x 8) Mask Programmable ...................................
MM521512,288·Bit (lk x 12) Mask Programmable .........................................
4
6-1
6-12
6-16
6-19
6-22
6-24
6-26
6-28
Table of Contents
(Continued)
Sedion 6-MOS ROMs
(Continued)
MM4220/MM5220 1024-Bit (128 X 8 or 256 x 4) Mask Programmable ..........•............... 6-30
MM4220AP/MM5220AP BCDIC to ASCII. Code Converter............ _......... , ............. 6-34
MM4220BM/MM5220BM Sine Look-Up Table. . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . .. 6-36
MM4220DF/MM5220DF "Quick Brown Fox" Generator....... _ . • . • .. . .. . • . . . . . . . . . . . . . . . . .. 6-40
MM4220EK/MM5220EK BCDIC to EBCDIC/ASCII to EBCDIC Code Converter........ _.....•.... 6-42
MM4220LR/MM5220LR BCDIC to ASCII-7/ASCII-7 to BCDIC Code Converter................... 6-45
MM4221/MM5221 1024-Bit (128 x 8 or 256 x 4) Mask Programmable. . . . . . . . . . . . . . . . . . . . . . . ... 6-48
MllA4221 RR/MM5221 RR ASCII-7 to EBCDIC Code Converter ............ _................... 6-52
MM4230/MM5230 2048-Bit (256 x 8 or 512 x 4) Mask Programmable .......................... 6-55
MM4230BO/MM5230BO HoUerith to ASCII Code Converter. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. 6-59
MM4230KP/MM5230KP ASCII-7 to Selectric Code Converter .................•.........•..... '6-61
MM4231/MM5231 2048-Bit (256x 8 or· 512 x 4) Mask Programmable .......................... 6-64
MM4231CMUlMM5231CMU Hollerith to ASCII Code Converter. _ .•............ _.............. 6-59
MM4231 RP/MM5231 RP EBCDIC to ASCII-7 Code Converter ................................ 6,68
MM4232/MM5232 4096-Bit (512 x 8 or lkx 4) Mask Programmable ............................ 6-73
MM4232AEI/MM5232AEI Sine Look-Up Table .. , ......... ,. _............................. 6-76
MM4232AEJ/MM5232AEJ Sine Look-Up Table............................. , .............. 6,76
MM4232AEK/MM5232AEK Sine Look-Up Table ............. _..•.•........................ 6-76
MM4240/MM5240 2560-Bit (64-8 x 5) Static Character Generator........................ 6-79, 11'23
MM4240AAlMM5240AA ASCII-7 Upper Case, Horizontal Scan Character Generator .......... 6-79, 11-22
MM4240AE/MM5240AE ASCII-7 Lower Case, Horizontal. Scan Character Generator .......... 6-79, 11-22
MM4240ABU/MM5240ABU Hollerith Character Generator .............................. 6-83, 11-23
MM4240ABZ/MM5240ABZ EBCDIC-8 Character Generator ... __ ........................ 6-85, 11-23
MM4240ACA/MM5240ACA EBCDIC Character Generator ..............•............... 6-86,11-23
MM4241/MM5241 3072-Bit (64 x 6 x 8) Mask Programmable ............................ 6-87, 11-24
MM4241ABL/MM5241ABL ASCII-7 Vertical Scan Character Generator •........... , ....... 6-87,11·24
MM4241ABV/MM5241ABV ECMA-7 Scandinavian Vertical Scan Character Generator ...•..... 6-87,11-24
MM4241ABW/MM5241ABW ECMA-7 German Vertical Scan Character Generator ............ 6-87,11-24
MM4241ABX/MM5241ABX ECMA-7 European Vertical Scan Character Generator ..... , ..... 6-87,11·25
MM4241ABY/MM5241ABY ECMA-7 Spanish Vertical Scan Character Generator ............. 6-87, 11-25
MM4242/MM5242 8192-Bit (1024 x 8) Mask Programmable .............................. , . " 6-90
MM4243/MM5243 2048-Bit (256 x 8 or 512 x 4) Electrically Programmable. . . . . . .. . . . . . . . . . . . . .. 6-5
MM4244/MM5244 4096-Bit (512 x 8) Electrically Programmable. . . . . . . . . . . . . . . . . . . . • . . . . . . . .. 6,8
MM4246/MM5246 16,384-Bit (2048 x 8) Mask Programmable................................. 6-94
MM4247/MM5247 16,384-Bit (4096 x 4) Mask Programmable................................. 6-94
SK0003 Sine/Cosine Look-Up Table ................................................. 6-114, 11-1
Sedion 7 -Bipolar ROMs
DM5488/DM7488 256-Bit (32 x 8) Open-Collector Mask Programmable •.......... ; . . . . . . . . . . . ..
7-1
DM54187/DM74187 1024-Bit (256 x 4) Open-Collector Mask Programmable............. . ..... . . 7-5
DM54L 187A/DM74L 187A 1024-Bit (256 x 4) Low Power Open-Collector Mask Programmable. . . . . .. . 7-8
DM54S187/DM74S187 1024-Bit (256 x 4) Open-Collector Schottky Mask Programmable. . . . . . • . . .. 7-11
DM54S270/DM74S270 2048-Bit (512 x 4) Open-Collector Schottky. . . . .. . . . . . • . . . . . . . . . . . . . . .. 7-13
DM54S271/DM74S271 2048-Bit (256 x 8) Open-Collector Schottky. . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-15
DM54S370/DM74S370 2048-Bit (512 x 4) TRI-STATE® Schottky. • . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·13
DM54S371/DM74S371 204B-Bit (256 x 8) TRI-STATE® Schottky............................. 7-15
DM75S28/DM85S28 8192-Bit (1024 x 8) TRI·STATE® Schottky .............................. 7-17
DM75S29/DM85S29 8192·Bit (1024 x 8) Open-Collector Schottky. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-17
DM7575/DM8575 Programmable Logic Array .. '" ...•............................. ; ...... 7-19
DM7576/DM8576 Programmable Logic Array ........................................'. . . .. 7-19
DM7597/DM8597 1024-Bit(256 x 4) TRI-STATE® Mask Programmable ........................ 7-26
DM75S97/DM85S97 1024-Bit (256 x 4) TRI-STATE® Schottky Mask Programmable .............. 7-11
DM7598/DM8598 256-Bit (32 x 8) TRI-STATE® Mask Programmable ......................... 7-29
DM8678 64-Character (5 x 7 or 7 x 9) Character Generator ...........•........•.......... '..... 7-35
DM76L97/DM86L97 1024-Bit (256 x 4) TRI-STATE® Low Power Mask Programmable ........ " .. 7-47
DM77S201/DM87S201 2048-Bit (256 x B) Open-Collector Schottky with Latches. . . . . . . . . . . . . . . .. 7-50
I?M77S202/DM87S202 2048-Bit (256 x 8) TRI-STATE® Schottky with Latches .................. 7-50
5
/
I
Table of Contents
(Continued)
Section 8-Shift Registers
MM1402A Quad 256-Bit Dynamic.. . ... .. . ... .. . ... . ....... . ... .. . .... . ... ..... ..... . . .
MM1403A Dual 512-Bit Dynamic... . ..... ..... . . ..... ..... . . . ... . . .......... ... .•... . ..
MM1404A 1024-Bit Dynamic .•......................... _............................ ..
MM4016/MM5016 512-Bit Dynamic. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5024A 1024-Bit Dynamic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4025/MM5025 Dual 1024-Bit Dynamic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4026/MM5026 Dual 1024-Bit Dynamic ..... , . .. . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4027/MM5027 2048-Bit Dynamic....... , .. , . , ..................... , . , ... , . , . _. . . . . . .
MM4052/MM5052 Dual 80-Bit Static ... , , ., .... ; .... , . , .. _ , ........ ; ..... ,... .. . . ... . . . ..
MM4053/MM5053 Dual l00-Bit Static ... , , ..... , .. , ....... , .. , . , , ............. , , ... , ....
MM5054 Dual 64/72/80-Bit Static .. ,. " ...... ,. " .. , , . " " .... , ' .. ,., .. , ... ' ...........
MM4055/MM5055 Quad 128-Bit Static ... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. • . . . ..
MM4056/MM5056 Dual 256-Bit Static. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . . . . . . . . ..
MM4057/MM5057 512-Bit Static ........ , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5058 1024-Bit Static. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . ..
MM5060 Dual 144-Bit Mask Programmable Static ............ ; . . . . . . . . . . . .. . . . . . . . . . . . . . . ..
MM5061 Quad 100-Bit Static. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. • . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4104/MM5104 Multiple Length, Electrically Adjustable .............................' ......
8-1
8-1
8-1
8-5
8-1
8-8
8-8
8-8
8-13
8-13
8-16
8-19
8-19
8-19
8-24
8-27
8-30
8-33
Section 9-Memory Systems
370-Add-On Memory Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-1
NS3-1 Bulk Storage Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .
9-3
NSII Memory Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-5
NSII/03 Memory Card. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-6
NS21 Memory Card...................... , ..... , ........................ " ..........•. _ 9-7
NS32 Memory Card .......... _............ '....... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
9-8
NS400-N Series Memory Cards .'.. . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . .
9-9
NS400-C Series Memory Cards .. , ... , ................. , ..... , . . . . . . . . . . . . . . . . • . . . . . . . •. 9-10
NS3000-1 Memory Card ............... ; ....... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-11
Memory Systems Testing. , . ',' ........ , ............... , , ...... , ................... , . . . .. 9-13
Section 10-lnterface
DS0025/DS0025C 2-Phase MOS Clock Driver............................................ _. 10-1
DS0026 5 MHz 2-Phase MOS Clock Driver ............................................... _ 10-2
DS0056 5 MHz 2-Phase MOS Clock Driver .......... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-2
DS1603/DS3603 Dual MOS Sense Amplifier ................ ' ........................... _. 10-;3
DS3604 Dual MOS Sense Amplifier .................................................... 10-3
DS1605/DS3605 High Speed Hex MOS Sense Amplifier. .. ..... . . ...... . ... ......... ....... .. 10-4
DS1606/DS3606 High Speed Hex MOS Sense Amplifier. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. 10-4
DS1607/DS3607 High Speed Hex MOS Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 10-4
DS1608/DS3608 High Speed Hex MOSSense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. 10-4
DS3625 Dual High Speed MOS Sense Amplifier .......................•.•..........." . . . . .. 10-5
DS3629 Memory Driver with Decode Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-6
DS1640/DS3640 Quad TRI-SHARETM MOS Driver.. .. .. . . .. . . ........ ........ ........ .. . .. 10-7
DS1642/DS3642 Dual Bootstrapped MOS Clock Driver. . .. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. 10-8
DS3643 Decoded Quad MOS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. 10-9
DS1644/DS3644 Quad MOS Clock Driver ...........................•..... _.............. 10-10
,DS1645/DS3645 Hex TRI-STATE® MOS Latch/Driver .. , ................................... 10-11
DS1646/DS3646 6-BitTRI-STATE® MOS Refresh Counter/Driver ............................. 10'12
DS1647/DS3647 Quad TRI-STATE® Memory I/O Register ................................... 10-13
OS1648/DS3648 TRI-STATE® MOS Multiplexer/Driver ................................... _. 10-14
DS1649/0S3649 Hex TRI-STATE® MOS Driver ............................................ 10-15
DS3651 Quad High Speed MOS Sense Amplifier............................................ 10-16
DS3653 Quad High Speed MOS Sense Amplifier, .. , ........................................ 10-16
DS1670/DS3670 Quad TRI-SHARETM MOS Driver .. , , , , , .... , , ......... , . . .. . . . . . . . . . . • . .. 10-7
OS1671/DS3671 2-Phase Bootstrapped MOS Clock Driver, , ., , . , ., .... , .. , ... ,., .. , .. ,., ..... 10-17
6
Table of Contents
(Continued)
Section 10-lnterface
(Continued)
OS1672/0S3672 Oual Bootstrapped MaS Clock Oriver ..............•...................... 10-8
OS3673 Oecoded Quad MaS Clock Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10·9
OS1674/0S3674 Quad MOS Clock Oriver ..•...........•................................. 10-10
OS1675/0S3675 Hex TRI-STATE@ MaS Latch/Oriver ........................... '" ........ 10-11
OS1676/0S3676 6-Bit TRI-STATE@ MaS Refresh Counter/Oriver. ............... , ...•........ 10-12
OS1677/0S3677 Quad TRI-STATE@ MaS Memory I/O Register ..............•............... 10-13
OS1678/0S3678 TRI-STATE@ MOS Multiplexer/Oriver ..... , ............................... 10-14
OS1679/0S~679 Hex TRI-STATE@ MaS Oriver ....................................... ': ... 10-15
OS16147/DS36147 Quad TRI-STATE@ MaS Memory I/O Register ............................ 10-13
OS16149/0S36149 Hex MaS Oriver ..............•............•........................ 10-18
OS16177/0S36177 Quad TRI-STATE® MaS Memory I/O Register ............................ 10-13
OS16179/0S36179 Hex MaS Oriver ..... , .... ; .......................................... 10-18
OS55107/0S751070ual Line Receiver .....•.............................................. 10-3
OS551 08/DS751 08 Oual Line Receiver ....•......................................... " .. 10-3
OS55109/0S75109 Oual Line Oriver .. , .......•......................................... 10-19
OS55110/DS75110 Oual LineDriver ., ...... '" ......................................... 10-19
OS55.121/0S75121 Oual Line Oriver .................................................... 10-20
OS551.22/0S75122 Triple Line Receiver ......................•.......................... 10-21
OS75123 Dual Line Oriver .... " ....................... '" ............................ 10-22
OS75124 Triple Line Receiver ............•............................................ 10-23
OS75150 Dual Line Oriver ............................................................ 10-24
OS75154 Quad Line Receiver .................................•........................ 10-25
OS752070uai Line Receiver ......................................................... , 10-3
DS75208 Dual Line Receiver .................................... , ................... " 10-3
OS75324 Memory Driver with Oecode Inputs....... ; ...........•.......................... 10-26
OS55325/0S75325 Memory Oriver ..................................................... 10-27
DS75361 Dual TTL to MaS Driver ..•........................... '" ................. " .. 10-28
DS75362 Dual TTL to MaS Oriver .......... , .................................... ~ ..... 10-29
OS75364 Dual MaS Clock Driver ... ; ................................................... 10-30
OS75365 Quad TTL to MaS Oriver ..................................................... 10-31
OS7803/DS8803 2-Phase Oscillator/Clock Driver ..... _.................................... 10-32
OS7807/0S8807 2-Phase Oscillator/Clock Oriver ..... : ..................................... 10-33
OS8813 2-Phase Oscillator/Clock Driver .......... _... _............................ _..... 10-32
DS8817 2-Phase Oscillator/Clock Oriver .................................................. 10-33
Section 11-App Notes/Briefs
AN-40 The Systems Approach to Character Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-1
AN-44 High Voltage Shift Registers Move Oisplays .......................................... 11-13
AN-55 Low Frequency Operation with Oynamic Shift Registers ....... , ....................... 11-17
AN-57 American and European Fonts in Standard Character Generators ......................... 11-21
AN-76 Applying Modern Clock Orivers to MaS Memories .................................... 11-27
AN-85 Saving ROMs in High-Resolution Dot-Matrix Displays and Printers ........................ 11-37
AN-86 A Simple Power Saving Technique for the MM5262 2k RAM ............................ 11-45
AN-89 How to Design with Programmaple Logic Arrays ....................................... 11-49
AN-l00 Custom ROM Programming ..................................................... 11-57
AN-l44 Designing Memory Systems Using the MM5262 ...................................... 11-65
AN-167 OM8678 Bipolar Character Generator ............................................. 11-78
AN-171 PROM Power-Down Circuits .................................................... 11-82
MB-l0 Trig Function Generators........................................................ 11-86
MB-14 Mask Programming Specializes MaS Shift Register Designs .............................. 11-88
MB-16 Oouble-Clocking Cuts Standard Registers to NOn-Standard Sizes.......................... 11-90
Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions ............. '................. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
A1
A3
i
Alpha-Numerical Index
DM5488/DM7488 256.-Bit (32 x 8) Open-Collector Mask Programmable ROM ..•. . . . . .. . . . . . . . . . . 7-1
DM5489/DM7489 64-Bit (16 x 4) Open-Collector RAM ......•........•.... ,. ..... . . ....... ..
2-1
DM54187/DM74187 1024-Bit (256 x 4) Open:Coliector Mask Programmable ROM. ..... .... ...... 7·5
DM54L 187A/DM74L187A 1024·Bit (256 x 4) Low Power Open·Collector Mask Programmable ROM ..
7~8
DM54S187/DM74S187 1024-Bit (256 x 4) Open-Collector Schottky Mask Programmable ROM. . . . . .. 7·11
DM54S188/DM74S188 256·Bit (32 x 8) Open-Collector Schottky PROM. . . . . . . . . . . . . . . . . . . . . . . . 5-2
DM54LS189/DM74LS189 64·Bit (16 x 4) TRI-STATE®, Low Power Schottky RAM. . . . . . . . . . . . . . . 2·4
DM54S189/DM74S189 64-Bit (16 x 4) TRI-STATE® Schottky RAM. . . . . . . . . . . . . . . . . . . . . . . . . . .
2-7
DM54S200/DM74S200 256-Bit (256 xl) TRI-STATE® Schottky RAM ........•.. " ............ 2-11
DM54S206/DM74S206 256-Bit (256 x 1) Open-Collector Schottky RAM ..................... ~ .. 2.15
DM54S270/DM74S270 2048-Bit (512 x 4) Open·Collector Schottky ROM. . . . . . . . . . . .. . . . . . . . . .. 7·13
DM54S271/DM74S271 2048·Bit (256 x 8) Open-Collector Schottky ROM. . . . . . . . . . . . . . . . . • .. . .. 7·15
DM54S287/DM74S287 1024·Bit (256 x 4) TRI·STATE® Schottky PROM. . ... .. ...... .. .. .... ..
5-4
DM54S288/DM74S288 256-Bit (32 x 8) TRI-STATE® Schottky PROM. . . . . . . . . .. . . . . . . . . . . . . . . 5-2
DM54LS289/DM74LS289 64·Bit (16 x 4) Open·Collector, Low Power Schottky RAM. . . . . . . • . . • . .. 2·19
DM54S2B9/DM74S289 64·Bit (16 x 4) Open-Collector Schottky RAM. . . . . . .. . .. • . . . . . . . . . . .. .. 2·22
DM54S370/DM74S370 2048-Bit (512 x 4) TRI·STATE® Schottky ROM ........................ 7·13
DM54S371/DM74S371 2048-Bit (256 x 8) TRI·STATE® Schottky ROM ... , .................... 7·15
DM54S387/DM74S387 1024·Bit (256 x 4) Open·Collector Schottky PROM. . . . . . . . . . . . . . . . . . . . . . 5·4
DM54S470/DM74S470 2048·Bit (256 x 8) Open·Collector Schottky PROM. . . . . • . . . . . . . . . . . . . . . . 5"9
DM54S471/DM74S471 2048·Bit (256 x 8) TRI~STATE® Schottky PROM. ..................... 5·9
DM54S472/DM74S472 4096-Bit (512 x 8) TRI-STATE® Schottky PROM ....................... 5-11
DM54S473/DM74S473 4096-Bit (512 x 8) Open-Collector Schottky PROM. . . . . • . . . . . . . . . . . . . . .. 5·11'
DM54S570/DM74S570 2048-Bit (512 x4) Open·Collector Schottky PROM. . . . . . . . . . . . . . . . . . . . .. 5-13
DM54S571/DM74S571 2048-Bit (512 x 4) TRI·STATE® Schottky PROM. . . . . . • . . . . . . . • . . . . . . .. 5-13
DM54S572/DM74S572 4096-Bit (1024 x 4) Open·Collector Schottky PROM. . . . . . . . . . . . . . . . . . . .. 5·18
DM54S573/DM74S573 4096-Bit (1024 x 4) TRI·STATE® Schottky PROM ....................... 5-18
DM75S28/DM85S28 8192-Bit (1024 x 8) TRI·STATE® Schottky ROM .....••................... 7-17
DM75S29/DM85S29 8192-Bit (1024 x 8) Open·Collector Schottky ROM. . . . . . . . . . . . . . . . . . . . • . .. 7·17
DM7575/DM8575 Programmable Logic Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·19
DM7576/DM8576 Programmable Logic Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-19
DM7577/DM8577 256-Bit (32 x 8) Open-Collector PROM. . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .. 5-20
DM7578/DM8578 256-Bit (32 x 8) TRI-STATE® PROM ......... '" ...........•............. 5-23
DM7597/DM8597 1024-Bit (256 x 4) TRI-STATE® Mask Pn;>grammable ROM ................... 7·26
DM75S97/DM85S971024·Bit (256 x 4) TRI·STATE® Schottky Mask Programmable ROM .......... 7·11
DM7598/DM8598 256-Bit (32 x 8) TRI-STATE® Mask Programmable ROM ............•........ 7·29
DM7599/DM8599 64·Bit (16 x 4) TRI-STATE® RAM .................................... , .. 2·29
DM8678 64·Character (5 x 7 or 7 x 9) Character Generator. . . . . • . . . . . • . . . . . . . . . . . . . . . . . . . . • .. 7·35
P~76L97/DM86L97 1024-Bit (256 x 4) TRI-STATE® Low Power Mask Programmable ROM ...... .-. 7-47
DM77S201/DM87S201 2048-Bit (256 x 8) Open-Collector Schottky ROM with Latches. . . . . . . . . . .. 7-50
DM77S202/DM87S202 2048-Bit (256 x 8LTRI-STATE® Schottky ROM with Latches ......•...... 7·50
DM77S221/DM87S221 204B-Bit (256 x 8) Open-Collector Schottky PROM with Latches. . . . . . . . . . .5-26
DM77S222/DM87S222 2048-Bit (256 x 8) TRI-STATE® Schottky PROM with Latches ... " . . .. . . .. 5-26
DM77S22B/DM87S228 8192.Bit (1024 x 8) TRI-STATE® Schottky PROM ....... , .............. 5-28
DM77S229/DM87S229 8192-Bit (1024 x 8) Open-Collector Schottky PROM .... , ..... '" ........ 5-28
DM77S295/DM87S925 4096-Bit (512 x 8) Open-Collector Schottky PROM. . . • . . . . . . . .. . . . . . . . .. 5-30
9
Alpha-Numerical Index
(Continued)
OM77S296/0M87S296 4096-Bit (512 X 8) TRI-STATE® Schottky PROM ....................... 5·30
OM93415, OM93415A 1024·Bit (1024 X 1) TTL, Fully Decoded RAM .......................... 2-33
OM93425, OM93425A 1024·Bit (1024 x 1) TTL, Fully Decoded RAM .......................... 2-34
OS0025/0S0025C 2-Phase.MOS Clock Driver........... , .................................. 10-1
OS0026 5 MHz 2-Phase MOS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10·2
OS0056 5 MHz 2-Phase MOS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10·2
OS1603/0S3603 Dual MaS Sense Amplifier ...................... , . . . . . . . . . . . . . . . . . . . . . .. 10-3
OS3604 Dual MOS Sense Amplifier .................................................... 10-3
051605/0S3605 High Speed Hex M05 Sense Amplifier. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. 10-4
051606/0S3606 High 5peed Hex MaS Sense Amplifier. . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . .. 10-4
051607/0S3607 High 5peed Hex MaS Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-4
051608/0S3608 High Speed Hex MaS Sense Amplifier. . . .. ... . . . . . .. . . . . . . . .. . . .. .. .. .... .. 10-4'
OS3625 Dual High Speed MOS Sense Amplifier. . .•. ... . . . . . . . ... . . .. . . . . . . .. . . .. .. .. .. . . .. 10-5
OS3629 Memory Driver with Decode Inputs. . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-6
051640/0S3640 Quad TRI-SHARETM MOS Driver. ...... , ... , ............................. 10-7
051642/0S3642 Dual Bootstrapped MaS Clock Driver. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .. 10-8
OS3643 Decoded Quad MOS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-9
051644/0S3644 Quad MOS Clock Driver ................................................ 10-10
051645/0S3645 Hex TRI-STATE® MaS Latch/Driver ..................................... 10·11
051646/0S3646 6-Bit TRI-STATE® MOS Refresh Counter/Driver ............................. 10-12
OS1647/0S3647 Quad TRI-STATE® Memory I/O Register ................................... 10·13
OS1648/0S3648 TRI·STATE® M05 Multiplexer/Driver ..................................... 10-14
OS1649/0S3649 Hex TRI·STATE® MaS Driver .......................................... 10-15
OS3651 Quad High Speed MOS Sense Amplifier..................................... , ...... 10-16
053653 Quad High Speed MOSSense Amplifier .......................................... ,.. 10-16
OS1670/0S3670 Quad TRI-SHARPM MaS Driver ......................................... 10-7
OS1671/0S3671 2-Phase Bootstrapped MaS Clock Driver .......................... , ......... 10-17
OS1672/0S3672Dual Bootstrapped MOS Clock Driver.. . . . . . . . ... .. .. . . . . . . ... . . . ... . .... .. 10·8
OS3673 Decoded Quad MOS Clock Driver ......... ' .... " ..... , ... . . .. .. . . .. .. . . .. . . ... . .. 10-9
OS1674/0S3674 Quad MaS CI.ockDriver ....................................... ; ........ 10-10
OS 1675/0S3675 Hex TR I-STATE® MOS Latch/Driver ...................................... 10-11
OS1676/0S3676 6-Bit TRI-STATE® MaS Refresh Counter/Driver ............................. 10·12
OS 1677/0S3677 Quad TRI·STATE® MaS Memory I/O Register .............................. 10-13
OS1678/0S3678 TRI·STATE® MOS Multiplexer/Driver ........................... '" ....... 10-14
OS 1679/0S3679 Hex TR I-STATE® MOS Driver ........................................... 10-15
OS16147/0S36147 Quad TRI-STATE® MOS Memory I/O Register ............................ 10-13
OS16149/0S36149 Hex MOS Driver .................................................... 10-18
OS16177/0S36177 QuadTRI-STATE® MaS Memory I/O Register ..........•................. 10·13
OS 16179/0S36179 Hex MOS Driver .................................................... 10-18
OS55107/0S75107 Dual Line Receiver .... , .... , . .. . . . . . . . . ... .. .. . . .. . ... . . . . ... . ... . .. 10-3
OS55108/0S75108 Dual Line Receiver .................................................. 1()"3
OS55109/0S75109 Dual Line Driver .................................................... 10·19
OS55110/0S75110 Dual Line Driver .......................................•............ 10-19
OS55121/0S75121 Dual Line Driver .................................................... 10-20
OS55122/0S75122 Triple Line Receiver ........................ ; ......... , .............. 10-21
OS75123 Dual Line Driver ........................................ , .... , .............. 10-22
OS75124 Triple Line Receiver ......................................................... 10-23
OS75150 Dual Line Driver ............................................................ 10-24
DS75154 Quad Line Receiver .......................................................... 10-25
OS75207 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . • . . . . . . . . . . . . . . . . . . . . . . . . .. 10-3
OS75208 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. 10-3
DS75324 Memory Driver with Decode Inputs.............................................. 10-26
DS55325/0S75325 Memory Driver .......................................... " ......... 10·27
DS75361 Dual TTL to MaS Driver ...................................................... 10-28
DS75362 Dual TTL to MaS Driver. ..................................................... 10-29
DS75364 Dual M05 Clock Driver. , .............................. ' ....................... 10-30
0575365 Quad TTL to MaS Driver ..................................................... 10-31
DS7803/D58803 2·Phase Oscillator/Clock Driver ........................................... 10-32
057807/058807 2-Phase Oscillator/Clock Driver ........................................... 10-33
DS8813 2-Phase Oscillator/Clock Driver ......................... ; ........... , ............ 10·32
10
Alpha-Numerical Index
(Continued)
DS8817 2-Phase Oscillator/Clock Driver ..................................................
MM1101 256-Bit (256 x 1) Static RAM ..................................................
MMll01A 256-Bit (256 x 1) Static RAM.................................................
MM1101A1256-Bit(256x 1) Static RAM ....................................•...........
MMI101A2 256-Bit (256 x 1) Static RAM. , ................................ '" .. . •. . . .. . .
MMll011256-Bit(256xl)StaticRAM ............................................... "
MM1402AQuad 256-Bit Dynamic Shift Register, ......................... " ... .. .. . ... ....
MM1403A Dual 512-Bit Dynamic Shift Register.................. " . . . . ..... . .. .. . . .. .. . .. .
MM1404A 1024-Bit Dynamic Shift Register. . . . . . . . .. . . . .. . .... ... . . . . . ... . . . . .. .. .. . . . .. .
MM1702A2048·Bit (256 x8) Electrically Programmable and Erasable ROM .......... , ... . ... .. . .
MM1742 2048-Bit (256x8) Electrically Programmable ROM...... ...... ...... ....... ........
MM21011024-Bit (256 x 4) Static RAM with Separate I/O. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
MM2101-1 1024-Bit (256 x 4) Static RAM with Separate I/O ............ ;..... ....... .. ......
MM2101.2 1024·Bit (256 x4) Static RAM with Separate I/O ... ,.................... .........
MM2102 1024-Bit (1024 x 1} Static RAM ......... " ..... . .. . .. . . . . .... . .. . .. .. ... . . . .. . .
MM2102A, MM2102AL Family 1024·Bit (1024x 1) Static RAM .. , ........... ; ...............
MM2102MD 1024·Bit (1024 x 1) Static RAM,Military Temperature Range ..................•...
MM2102-.1 1024·Bit (1024 x 1) Static RAM ........... , ..... ; . . . . . • . . . . . . . . . . . • . . . . . . . . . ..
MM2102·2 1024-Bit (1024 x 1) Static RAM........ .... .... .. ...... . .............. .... ....
MM2102·2MD 1024·Bit (1024 xl) Static RAM, Military Temperature Range. . . . . . . . . . . . . . . . . . . ..
MM2111 1024-Bit (256 x 4) Static RAM with Common Data I/O .. ; . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM2111·1 1024·Bit (256 x 4) Static RAM with Common Data I/O ........................ ; ....
MM2111·2 1024-Bit (256 x 4) Static RAM with Common Data I/O ............................ ,
MM2112 1024·Bit (256 x 4) Static RAM with Common Data I/O . . . .. . . . . . . . . . . . . . . . . . . . . . . . ..
MM2112·2 1024·Bit (256 x 4) Static RAM with Common Data 110 ............................ ,
MM2316A 16,384·Bit (2048 x 8) Mask Programmable ROM. . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . ..
MM27044096·Bit (512 x 8) UV Erasable and Electrically Programmable ROM. . . . . . . . . . . . . . . . . . . .
MM2708 8192·Bit (1024 x 8) UV Erasable and Electrically Programmable ROM.. .. ..... . •. . .... ..
MM4016/MM5016 512·Bit DynamicShift Register .............................•. ; . . . . . . . . .
MM5024A 1024·Bit Dynamic Shift Register ....... ; . . . . . . .. .. . . .. .. . . . ..•.. . .. ...... . . . . ..
MM4025/MM5025 Dual 1024·Bit Dynamic Shift Register ............ , . . .. . . . . . . . . . . . . . . .. . . .
MM4026/MM5026 Dual 1024-Bit Dynamic Shift Register ........... ; .. ( . . . . . . . . . . . . . . . . .. . . .
MM4027!MM5027 2048-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4052/MM5052 Dual 80·Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . ..
MM4053!MM5053 Dual 1OO·Bit Static Shift Register. . . .. . . . . . . . . . . . .• . . . . . . . . . . . . . . . . . . . . ..
MM5054 Dual 64/72/80.Bit Static Shift Register. .. . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . ...
MM4055/MM5055 Quad 128·Bit Static Shift Register. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . ..
MM4056!MM5056 Dual 256-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . ..
MM4057/MM5057 512·Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5058 1024·Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . ..
MM5060 Dual 144·Bit Mask Programmable Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5061 Quad 100·Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . ..
MM4104/MM5104 Multiple Length, Electrically Adjustable Shift Register ..................... ; ..
MM4203/MM5203 2048-Bit (256 x 8 or 512 x 4) Electrically Programmable and Erasable ROM .......
MM4204!MM5204 4096-Bit (512 x 8) Electrically Programmable and Erasable ROM. . . . . . . . . . . . . ..
MM4210!MM5210 1024·Bit (256 x 4) Mask Programmable ROM ..............................
MM4211/MM5211 1024·Bit (256 x 4) Mask Programmable ROM. . . . . . . . . . . . . . . . . . . . . . • . . . ....
MM5212 12,288-Bit (lk x 12) Mask Programmable ROM ............................ _........
MM4213/MM5213 2048·Bit (256 x 8 or 512 x 4) Mask Programmable ROM ......................
MM4214/MM5214 4096-Bit (512 x 8) Mask Programmable ROM ..............................
MM5215 12,288·Bit (1 k x 12) Mask Programmable ROM. . . . . . . . . . . . • . . . . . . . . . . . . . . . .. . . . . . ..
MM4220/MM5220 1024·Bit (128 x 8 or 256 x 4) Mask Programmable ROM ......................
MM4220AP/MM5220AP BCDIC to ASCII Code Converter. . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . ..
MM4220BM/MM5220BM Sine Look-Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4220DF/MM5220DF "Quick Brown Fox" Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4220EK/MM5220EK BCDIC to EBCDIC/ASCII to EBCDIC Code Converter...................
MM4220LR/MM5220LR BCDIC to ASCI 1:7/ASCI 1·7 to BCDIC Code Converter...................
MM4221/MM5221 1024-Bit (128 x 8 or 256 x 4) Mask Programmable ROM ... , ..................
MM4221 RR!MM5221 RR ASCII-7 to EBCDIC Code Converter .............................. ,.
MM4230/MM5230 2048·Bit (256 x 8 or 512x4) Mask Programmable ROM ......................
11
10-33
'-1
1-1
1-'
1-1
1·1
8-1
8-1
8-1
4·1
6-1
1-5
1-5
1·5
1·8
1,12
1·15
1·8
1·8
1·15
1-19
1·19
1·19
1-22
1·22
6-12
4·7
4·7
8·5
8·1
8-8
8·8
8'8
8·13
8·13
8·16
8-19
8·19
8·19
8·24
8·27
8·30
8-33
4·12
4·17
6-16
6-19
6-22
6-24
6-26
6-28
6-30
6-34
6-36
6-40
6-42
6-45
6-48
6-52
6-55
Alpha-Numerical Index
(Continued)
MM4230BO/MM5230BO Hollerith to ASCII Code Converter .................................. 6·59
MM4230KP/MM5230KP ASCII· 7 to Selectric Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-61
MM4231/MM5231 2048-Bit (256 x 8 or 512 x 4) Mask Programmable ROM ...................... 6·64
MM4231CMU/MM5231CMU Hollerith to ASCII.Code Converter. .. , .... , ...................... 6-59
MM4231 RP/MM5231 RP EBCDIC to ASCII·7 Code Converter .......................... , .... " 6-68
-MM4232/MM5232 4096·Bit (512 x.8 or 1k x 4) Mask Programmable ROM ....................... 6·73
MM4232AEI/MM5232AEI Sine Look·Up Table .................................. , . . . . . . . .. 6·76
MM4232AEJ/MM5232AEJ Sine Look-Up Table ................. , ........................ " 6-76
MM4232AEK/MM5232AEK Sine Look-Up Table ......................................... " 6-76
MM4240/MM5240 2560-Bit (64-8 x 5) Static Character Generator ........................ 6-79, 11-23
MM4240AA/MM5240AA ASCII-7 Upper Case, Horizontal Scan Character Generator ROM ..... 6-79, 11~22
MM4240ABU!MM5240ABU Hollerith Character Generator ..................... " ....... 6-83, 11-23
MM4240ABZ/MM5240ABZ EBCDIC-8 Character Generator ............................. 6-85, 11-23
MM4240ACA/MM5240ACA EBCDIC Character Generator .............................. 6-86, 11-23
MM4240AE/MM5240AE ASCII-7 Lower Case, Horizontal Scan Character Generator ROM ...... 6-79,11-22
MM4241/MM5241 3072-Bit (64 x 6 x 8) Mask Programmable ROM ......... , ............. 6-87, 11-24
MM4241ABL!MM5241ABL ASCII-7 Vertical Scan Character Generator ROM ............... 6-87, 11-24
MM4241ABV/MM5241ABV ECMA-7 Scandinavian Vertical Scan Character Generator ROM .... 6-87, 11-24
MM4241ABW/MM5241ABW ECMA-7 German Vertical Scan Character Generator ROM ........ 6-87,11-24
MM4241ABX/MM5241 ABX ECMA-7 European Vertical Scan Character Generator ROM ....... 6-87, 11-25
MM4241ABY /MM5241ABY ECMA-7 Spanish Vertical Scan Character Generator ROM ........ 6-87, 11-25
MM4242/MM5242 8192-Bit (1024 x 8) Mask Programmable ROM ................ _............ 6-90
MM4243/MM5243 2048:Bit (256 x 8 or 512 x 4) ElectricallY Programmable ROM. . . . . . . . . . . . . . .. . 6-5
MM4244/MM5244 4096-Bit (512 x 8) Electrically Programmable ROM ........... _. _. . . • . . . . . . . . 6-8
MM4246/MM5246 16,384-Bit (2048 x 8) Mask Programmable ROM .......................... " 6-94
MM4247/MM5247 16,384-Bit (4096 x 4) Mask Programmable ROM ................... ; . . . . . . .. 6-94
MM4250 256-Bit (256 xl) Static RAM, Military Temperature Range ....................... " ..
1-1
MM5269 1024-Bit (256 x 4) Static RAM with On-Chip Registers .......... _..... _. . . . . . . . . . . . .. 1-26
MM4270 4096-Bit (4096 x 1) TRI-SHARETM Port, Dynamic RAM. . . . . . . . . . . . . . . . . . . .. . . . . . . .. 1-28
MM5270 4096-Bit (4096 xl) TRI-SHARE:rM Port, Dynamic RAM, ............. , .............. 1-33
MM5270A 4096-Bit (4096 x 1) Dynamic RAM ., ............... " ... '" . . . .. . . .. .. . .. . .... 1-38
MM5270-5 4096-Bit (4096 xl) TRI-SHARETM Port, Dynamic RAM.. . . . .. . . . . .... . . . .. . ...... 1-44
MM5271 4096-Bit (4096 x 1) Fully TTL Compatible RAM ................................... 1-46
MM5271A 4096-Bit (4096 xl) TRI-SHARETM Port, Dynamic RAM.. .. . . .. .. . ... . . ..... .. .... 1-51
MM4280 4096-Bit (4096 x 1) Dynamic RAM ........................ __ .................... 1-56
MM5280 4096-Bit (4096 x 1) Dynamic RAM .............................. _. . . . . . . . . . . . . .. 1-60
MM5280A 4096-Bit (4096 x 1) Dynamic RAM. . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . .. . . . . . . .. 1-64
MM5280-5 4096-Bit (4096 x 1) Dynamic RAM. . . . . .. .. . .. . . . . . . . . . . ... . . . .. .. . . ... ..... .. 1-70
MM5281 4096-Bit (4096 x 1) Fully TTL Compatible Dynamic RAM ...... _..... _. . . . . . .. . .... .. 1-72
MM5290 16,384-Bit (16,384 x 1) Dynamic RAM ........................... _............... 1-76
MM54C89/MM74C89 64-Bit (16 x 4) TRI-STATE® CMOS RAM .............. _...............
3-1
MM54C200/MM74C200 256-Bit (256 x 1) TRI-STATE® CMOS RAM .......... _. .. . . .... . .. ...
3-5
MM54C910/MM74C910 256-Bit (256 xl) TRI-STATE® CMOS RAM .......... _......... .... ..
3-8
MM54C920/MM74C920 1024-Bit (256 x 4) Static Silicon Gate RAM .......... , _............... 3-12
MM54C921/MM74C921 1024-Bit (256 x 4) Static Silicon Gate RAM .......... _................ 3-12
MM54C929/MM74C929 1024-Bit (1024 x 1) Static Silicon Gate RAM ........ _. _............... 3-19
MM54C930/MM74C930 1024-Bit (1024 xl) Static Silicon Gate RAM .......... _. . . . . . . . . . . . . .. 3-19
NS3-1 Bulk Storage Memory ... _. . . . . . . . . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . 9-3
NSll Memory Series ................... , . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
NS11/03 Memory Card. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . 9-6
NS21 Memory Card ......................................... " . . . . . . . . . . . . . . . . . . . . . . . 9.. 7
NS32 Memory Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . 9-8
NS400-C Series Memory Cards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-10
NS400-N Series Memory Cards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
NS3000-1 Memory Card .... , . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-11
SK0003Sine/Cosine Look-Up Table ................................................ 6-114,11-1
370-Add-On Memory Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 9-1
12
BIPOLAR RAMs
OTHER SOURCE
w
NATIONAL
AMD
AM27LSODC
AM27LSOOM
AM27LSOIC
AM27LSOIM
AM27LS02C
AM27 LS02M
AM72L503C
AM27 LS03M
AM27S02C
AM27S02M,
A!yI27S03C
AM27S03M
AM3101
AM3101A
AM31 LOIC
AM31LOIM
DM74S200
DM54S200
DM74S206
DM54S206
DM74LS289
DM54LS289
DM74LS189
DM54L5189
DM74S289
DM54S289
DM74S189
DM54S189
DM7489
DM74S289
DM74LS289
DM54LS289
Fairchild
93403
93411C
93411M
93415AC
93415C
93421C
93421M
DM745289
DM74S206
DM54S206
DM93415
DM93415
DM14S200
DM54S200
Intal
3101
3101A
M3101
M3101A
3106
310SA
3107
3107A
DM7489
OM745289
DM5489
DM54S289
OM74S200
DM74S200
DM745206
DM74S206
Intersil
IM5501C
IM5501M
IM5523C
IM5523M
IM5533C
IM6533M
DM7489
DM5489
DM74S200
DM54S200
DM74S206
DM54S206
MOSRAMs
OTHER SOURCE
NATIONAL
MMI
5530
5531
5560
5561
6530
653'
6560
6561
L5560
L5561
L6560
L656'
DM54S206
DM54S200
DM54S289
DM54S189
DM74S206
DM74S200
DM745289
DM74S189
OM54L5289
DM54LS189
DM74L5289,
DM74LS189
Signetics
N8225
N82S06
N82S07
N82S10
N82S16
N82517
NB2S21
N82525
N825116
N825117
S82506
582507
582S16
5825t7
582525
DM7489
DM74S200
DM74S206
DM93415
DM74S200
DM745206
DM86521
DM74S289
DM745200
DM74S206
DM545200
DM54S206
DM54S200
DM54S206
OM54S289
OTHER SOURCE
AMD
AMll01A
AMl101Al
AM1101A1M
AM2101
AM2102
AM2111
AM21l2
AM9060C
AM90600
AM9060E
AM9101A
AM9101B
AM9101C
AM9101D
AM9102
AM91L02
AM9102A
AM91 L02A
AM9102B
AM91 L02B
AM9102C
AM91 L02C
AM91020
AM9102E
AM9111A
AM9111B
AM9111C
AM9111D
AM9112A
AM9112B
AM91-12C
AM9112D
,
Texas Instruments
SN5489
5N7489
SN54S189
, SN54S201
SN54S289
SN54S301
SN74S189
SN74S201
SN74S289
SN74S301
SN74S309
--------
OM5489
DM7489
DM54S189
DM54S200
DM54S289
DM54S206
OM74S189
DM74S200
OM74S289
OM74S206
DM93415
c_
AMS
AMS6003
AMS7270
AMS7270-5
AMS7271
AMS7299
AMS7280-5
AMS7281
NATIONAL
MMll01A
MMll01Al
MM4250
MM2101
MM2102
MM2111
MM2112
MM5280-5
MM5280
MM5280
MM2101-1
MM2101A*
MM2101A-2*
MM210]A-2*
MM2102A-6
MM2102-6L
MM2102-4
MM2102A-4L
MM2102A
MM2102A-L
MM2102A-2
MM2102A-2L
MM2102A-2
MM2102A-l
MM2111-1
MM2111A*
MM2111A-2*
MM2111A-2*
MM2112-1
MM2112A
MM2112A-2*
MM2112A-2*
MM5262
MM5270
MM5270-5
MM5271
MM5210
MM5280-6
MM5281
OTHER SOURCE
NATIONAL
Fairchild
2102
21L02
2102-1
21 L02A
21 L02B
2102F
2102F2
MM2102-2
MM2102A-6L
MM2102A-4
MM2102A-4L
MM2102A-L
MM2102A
MM2102A-2
Intal
1101A
llMAl
2101A
2101A-2
21 01 A-4
2101
2101
2101-1
2101-2
2102A
2102A-2
2102A-4
2102AL
2102AL-2
2102AL-4
2107B
2107B·4
2111A
2111A-2
2111A-4
2111
2111-1
2111-2
2112A
2112A-2
2112A-4
2112
2112-2
2114
MM1101A
MMll01A·l
MM2101A*
MM2101A-2*
MM2101A-4*
MM2101
MM5269
MM210H
MM2101-2
MM2102A
MM2102A-2'
MM2102A-4
MM2102AL
MM2102AL-2
MM2102AL-4
MM5280
MM5280·5
MM2111A*
MM2111A-2*
MM2111A-4*
MM2111
MM2111-1
MM2111-2
MM2112A*
MM2112A-2*
MM2112A-4*
MM2112
MM2112-2
MM2114
MMl
2110
2171
2180
2181
MM5270
MM5271
MM5280
MM6281
OTHER SOURCE
NATIONAL
Signetics
21F02
21 F02-2
21 F02-4
2102
2102-1
2102-2
21L02-1
21 L02-3
2501
2680
2680-1
2613
2614
MM2102A
MM2102A-2
MM2102A-4
MM2102
MM2102-1
MM2102-2
MM2102A-L
MM2102A-2L
MM1101Al
MM5280
MM5280-5
MM5257
MM2114
Texas Instruments
TM54033
TMS4034
TMS4035
TMS4039
TMS4039-1
iMS4039-2
TMS4042
TMS4042-1
TMS4042-2
TMS4043,
TMS4043-1
TMS4043-2 '
TMS4060
TMS4060-1
TMS4060-2
MM2102A-4
MM2102-2
MM2102
'MM2101
MM2101-2
MM2101A-4
MM2111
MM2HI-2
MM2101A-4
MM2112
MM2112-2
MM2112A-4
. MM5280-5
MM5280
MM5280
CMOS RAMs
Intersil
IM6551
IM6508
IM6518
MM74C921
MM74C929
MM74C930
* Available 3rd ""arter 1977
AU.partI ara pin """"",tiIIIle: Check
Nat4Jnai data sheeu for specification
details_
-------------
ep!n9
3:JU3J8J3Y SSOJ!)
W'dl:l
Bipolar RAM Cross Reference Guide
"
,
I
I
SIZE AND
ORGANIZATION
64-Bit (16 x 4)
High Speed
64-Bit (16 x 4)
~
OUTPUT
!
NATIONAL
AMD
F.S.C.
INTEL
MIL/COM
M=MIL
C=COM
M=MIL
C=COM
M=MIL
P=COM
OC
DM5489/DM7489
TS
DM7599/DM8599
OC
T5
DM54S289/DM74S289
DM54S189/DM745189
Low Power
64-Bit (16 x 4)
OC
DM54LS289/DM74LS289
TS
DM54LS189/DM74L5189
File Reg. (16 x 4)
T5
DM75S68/DM85568
256-Bit (256 xl)
OC
DM545206/DM74S206
3101
AM3101
AM27502
AM27S03
93403
INTERSIL
M=MIL .
P =.COM
SIGNETICS
T.I.
MIL/COM
S=Mll
N=COM
MIL/COM
IM5501
3101A
5560/6560
8225
SN5489/7489
82525
SN54S289/74S289
5561/6561
5N545189/745189
L5560/L6560
AM27L502
AM27LS03
AM27S01
MMI
L5561/L6561
93411
3107
93411 A
3107A
93421
3106
93421A
3106A
IM5533A
5530/6530
82507
5N54S30 1/74530 1
82S17
825117
TS
1024·Bit (1024 xl)
OC
TS
DM54S200/DM74S200
AM27S00
DM93415AM/DM93415AC
93415
DM93425AM/DM93425AC
93415A
93425
93425A
82506
SN54200/74200
82516
SN545200/745200
825116
SN54S201 /745201
IM5508
IM5508A
82510
SN54S309/745309
IM5518
82511
5N54S209/745209
IM5523A
IM5518A
5531/6531
Note: All manufacturer's PROMs program differently.
* Future products
8p!n9 8:lU9J8j.8l:1
SSOJ~ WOl:ld J81 0d!8
Bipolar PROM/ROM Selection Gui~e
I
TOTAL BITS
256
1024
2048
4096
-
4096
en
8192
2048
2048
4096
PART NUMBER
PROM
ROM
DM7577
DM8577
DM7578
DM8578
DM54S387
DM74S387
DM54S287
DM74S287
DM54S570
DM74S570
DM54S571
DM74S571
DM54S572
DM74S572
DM54S573
DM74S573
DM77S295
DM87S295
DM77S296
DM87S296
DM77S229
DM87S229
OM 77S228
DM87S228
DM77S221
DM87S221
DM77S222
DM87S222
OM 54S470
DM74S470
DM54S471
DM74S471
DM54S473
DM74S473
DM54S472
DM74S472
DM5488
DM7488
DM7598
DM8598
DM54S187
DM74S187
DM75S97
DM85S97
DM54S270
DM74S270
DM54S370
DM74S370
DM77S95
DM87S95
DM77S96
DM87S96
DM75S29
DM85S29
DM75S28
DM85S28
DM77S201
DM87S201
DM77S202
DM87S202
DM54S271
DM74S271
DM54S371
DM74S371
Note. All PROMS are direct equivalents to their respective ROMS.
ORGANIZATION
32 x 8
32x 8
32 x 8
32 x 8
256x4
256x 4
256 x 4
256x4
512 x 4
512 x 4
512 x 4
512 x 4
lk x 4
lk x 4
lk x 4
lk x 4
512 x 8
512 x 8
512 x 8
512 x 8
lk x 8
lk x 8
lk x 8
lk x 8
256 x 8
256x 8
256x 8
256 x 8
256 x 8
256 x 8
256 x 8
256 x 8
512 x 8
512 x 8
512 x 8
512 x 8
OC
OC
TS
TS
OC
OC
TS
TS
DC
OC
TS
TS
DC
OC
TS
TS
OC
OC
TS
TS
OC
OC
TS
TS
OC
OC
TS
TS
OC
OC
TS
TS
OC
OC
TS
TS
NUMBER OF PINS
TEMPERATURE
RANGE
MAXIMUM ADDRESS
ACCESS (tAA)
MAXIMUM SUPPL V
CURRENT( ICC)
16
16
16
16
16
16
16
16
16
16
16
16
18
18
18
18
24
24
24
24
24
24
24
24
20
20
20
20
20
20
20
20
20
20
20
20
-55°C to +125°'C
o°c to +70°C
-55°C to +125°C
0°Cto+70°C
-55°C to +125°C
o°c to +70°C
-55°C to +125°C
o°c to +70°C
-55°C to +125°C
O°Cto +70°C
-55°C to +125°C
o°c to +70°C
-55°C to +125°C
o°c to +70°C
-55°C to +125°C
o°c to +70o C
-55°C to +125°C
o°c to +70°C
-55°C to +125°C
o°c to +70°C
-55°C to +125°C
o°c to +70°C
-55°C to +125°C
o°c to +70°C
55°C to +125°C
o°c to +70°C
-55°C to +125°C
o°c to +70°C
-55°C to +125°C
o°c to +70°C
-55°C to +125°C
O°C to +70°C
-:55°C to +125°C
o°c to +70°C
-55°C to +125°C
o°c to +70°C
70
50
70
50
60
50
60
50
70
55
70
55
75
60
75
60
80
65
80
65
90
70
90
70
75
60
75
60
75
60
75
60
80
65
80
65
110
110
110
110
130
130
130
130
130
130
130
130
140
140
...
140
140
170
170
170
170
170
170
170
170
150
150
150
150
150
150
150
150
165
165
165
165
~National
MOSRAMs
~ Semiconductor
MM1101. MM11011. MM1101A. MM1101A1.MM1101A2. MM4250
256-bit fully decoded static random access memory
general description
The MM1101 family of fully d!lCoded 256 word x
1-bit random access memories are monolithic MOS
integrated circuits using silicon gate low threshold
t!lChnology to achieve bipolar compatibilitV_ They
are static, require no clocks, and hold information
indefinitely, subject to the integrity of the power
supply voltages.
•
Fewer system components - bipolar compatible
input and output
• Second source flexibility - MM1101, MM1101A
MM11011. MM1101Al second sources available
• TRI-STATETM output - wired OR capability
• Specified ambient temperature O°C to + 70°C,.
for MM1101 family; -55°C to +125°C for'
MM4250
features
•
•
•
Fast access times
MM1101A2 500 nsmax
MM11011, MM1101A1 1.0 ps max
MM1l01, MM1101A 1.5 ps max
MM4250 650 ns max
MM1101A2
I mproved speed/power product
1/3 of 1101A
1.5 mW/bit
Low power operation
applications
•
High speed buffer memories
•
Local memory store
block and connection diagrams
Dual·ln-Line Package
INPUT As
A,
18~
1
"
INPUT., 2
A,
256 BIT
A,
PLANE
RAM
INPUT ~ J
READ/WRITE
14' DATA OUT
13 DATA OUT
A,
12
DATA IN
11 INPUT A3
DATA
OUT
"
INPUT AI
9
INPUT A2
v~
DATA
OUT
rOPYI!W
Order Number MM1101D,
MM1101AD, MM1101A1D,
MMll01A2D, MMll0llD
orMM4250D
os
RIW
OATAIN
"12
See Package 3
Vee "'PIN 5
Vo =-PIN4
Order Number MMll01N.
MMll01AN, MMll01A1N,
MMll01A2N Dr MM11011N
So. Package 15
VoD ",PIN8
1-1
D
absolute maximum ratings
All Input or Output Voltages with Respect to the Most Positive Supply
Voltage, Vss
Supply Voltages VOD and Vo with
Respect to Vss
Power Dissipation at Room Temperature
OPerating Temperature
MM1101 Family
MM4250
Storage Temperature
Lead Temperature (Soldering, 10 sec)
+O.3V to -20V
-16V
700mW
0° C to +70° C ambient
_55°C to +125 °c ambient
-66'C to +160°C
300'C
dc characteristics
o°c to +70°C for MM1101 Family. TA "" _55°C to +125~C for MM4250;
Vss· +5V ±5%, Vo = VOO = -9V ±5%lor MM4250, MM1101A, MMll01A1, MM1101A2;
TA ::
Vss = +5V ±5%. Va "" -10V ±5%" Voo :;::'-7V ±5%, for. MM1101, MM1101' (unless otherwise specified).
I"
r
lco
MM4250
MMll01A
MM1101Al
MMll01A2
I
MM1101
MM11011I
Input Load Current
(All Input Pins)
V IN - 0.0
Output Leak.a!Je Current
Vour'" a.av, CS '" Vss - 2.0V
Power Supply Current. Voo
"'~')
too
I
0
Power Supply Current, Voo
T A. " 0 °c
Power Supply Current, Vo
TA.
10
Power Supply Current, Vo
TA =0 C
V"
Input LOW Voltage
=
2~OC
,
MM4250
MM1101 FAMIL'"
CONDITIONS
TEST
SYMBOL
MIN
TVP
MAX
0.001
D.'
0.001
13.0
ContinUOU5
Operation
101. "O.OmA
TVP
MIN
D.'
1.0
19.0
13.0
18.0
12.0
24,0
Vss -10
UNITS
1.0
25.0
12.0
MAX
Vss -4.2
Vss -10
Vss + 0.3
\Iss - 2.0
19.0
rnA
25.0
rnA
18.0
mA
24.0
mA
Vss - 4.2
V'N
Input HIGH Voltage
lac
Output Sink Current
V OUT = +O.45V, T A" 2SoC
3.0
~Cl.
Output Sink Current
Vour" +0.45V, T A, " 70°C
2.0
'e,
Output Clamp Current
Your '" ·1.0V. TA, = OoC
ION
Ololtput SO\Jrce Current
VOUT '" O.OV, T A, '" +2SoC
-3.0
-8.0
-3.0
-8.0
rnA
ION
Output Source Current
Vour" a.DV, TA "" +70"C
-2.0
-7.p
-2.0
-7.0
mA
3.S
4.9
Vss - 2.0
Output HIGH Voltage
Input Capacitance (Note 3)
(All Input Pins)
IOI-! = -100pA
Cour
Output Capacitance
Vour'''' Vss
Cv
Vo Power Sl,Ipply
Capacitance
Vo" VS;o
100
Power Supply Current, Voo
TA0250CI
10
Power Supply Current. Vo
TA." 2SoC
f" 1 MHl
Continuous
Operation
101. :"O.OmA
Vss +0.3
3.0
mA
8.0
2.0
6.0
.... )
VON
C'N
8.0
mA
6.0
13.0
13.0
4..
3.S
rnA
7.0
10.0
7.0
10.0
pF
7.0
10_0
7.0
10,0
pF
20.0
35.0
20.0
35.0
pF
14.0
18.0
mA
17.0
20.0
mA
ac characteristics
= o°c to +70oC for MM1101 Family, TA = -SSoC to +12SQ C for MM42S0;
Vss = +5V ±5%, Vo = Voo = -9V ±5% for MM4250, MM1101A, MMll01Al. MM1101A2;
Vss = +SV ±5%. V D :: -10V ±5%, V DD = -7V ±5%. for MM 1101. MM11011 (unless otherwise specified),
TA,
SYMBOL
TEST
MIN
Read Cycle MM1101, MM1101A
MMll0ll, MM1101A1
MM1101A2
MM4250
1.5
1.0
500.0
650.0
'.
1.2 (Note 4)
0.7 (Note 4)
0.2 (Note 4)
0.35 (Note 4)
Access Time MM1101, MM1101A
MM11011 , MMll01A1
MM1101A2
MM4250
Previous Read Dqta Valid
1:
2:
3:
4:
MAX
0.85
0.65
400.0
400.0
50.0
Air volulge measurements are referenced to ground.
Typical values are at TA = +25°C and nominal supply Voltages.
Capacitances are' measured periodically only.
Maximum value for tac measured at minimum read cycle.
1-2
UNITS
/1S
/1s
ns
ns
Address tci"-Chip Select Delay
MM1101, MMll01A,
MMll0l1, MM1101Al
MMll01A
MM4250
t~
Note
Note
Note
Note
TYP
(Note 2)
1.5
1.0
500.0
650.0
/1'
/1S
/1'
/1s
/1s
I1S
ns
n,
ns
ac characteristics (can't)
WRITE CYCLE (MMll0l. MMll0ll. MMll01A. MMll01AI. MMll01A21
TEST
SYMBOL
TYP
(Note 21
MIN
MAX
UNITS
'we
Write Cycle
0.8
'wo
'Addr... to Writ. Pulse Delay
0.3
I"
twp
Write Pulse Width
0.4
I"
tow
Data Set up Time
0.3
Ils
.tOH
Data Hold Time
0;1
IlS
I"
WRITE CYCLE (MM42501
tw.
Writ. Cycle
1.0
IlS
twd
Address to Write Pulse Delay
0.35
I"
two
Write Pulse Width
0.50
IlS
!ow
Data Set·up Time
0.35
IlS
toh
Data Hold Time
0.15
Ils
CHIP SELECT AND DESELECT (MM1101. MMll011. MM1101A. MMll01Al. MM1101A2. MM42501
'0.4
Chip Select Puis. Width
tew
tcs
jJ.S
Access Time Through Chip
0.2
0.3
IlS
0.1
0.3
jJ.S
Select Input
Chip Deselect Time
teo
Note
Note
Note
Note
1:
2:
3:
4:
All voltage measurements are referenced to ground.
Typical values are at TA = +25"C and nominal supply voltages.
Capacitances are ~easured periodically only.
Maximum value for' tac measured at minimum read cycle.
tYpical performance characteristics
Typical Access Time ..
VClltage
1I11III
!
!
i!!
~
800
700
600
....
.~.JIVt-
1....
t7!~,,-IY,t:
IZIII
_l1tJA .....
:±. ~OCIht'"
-
...1tOtAi~
~~ ~~
y .....y
.Yoor-.>-:,
...vTt-
+
Jooa-av
++Voo-..w
VDOs~ttV ~ ~
:i~'i"
~
ZOO
-7
-II
-II
..
!!
~
....
.-
c. =Z1Ipf
MMtlOIA <- I-
~~
~
&all
400
~
,
-lO
-II
-
~
D
:>
HI , I - MMtlBIAZ. MiM2so'.
~
-10
T.=UoC
Vcc' 5.OV'
I TTL LOAD
!Iooe . .milA;
~
;:: 800
;.~
41'1
MM1101A, MM1101Al.
MM1101A2, MM4250
Operating Region
Typical Access Time VI
Temperature
-II
18
--
sa
3D
II
17
II
15
II
•
7.
Test Setup for MMll01A and MM1101A Speed M..... rement
..v
+:n
ADD....
INPUT
1VG 1VD 1v..o...
_Itlll
.,una
omaT
'f . .
C'..,.
CONDITIONS OF TEST
Input pulse amplitudes: OV tOi +S.DV.
Input pulse rise arul fall times s: IOns.
Speed measurements are ftferenClid 10 the 1.5V leval (unless othlfWise nDled);
at the output of the TTL gate hpj ::; 10 ns) CL ~ 20 pf.
1-3
TTL BATE
["!
PlCAL OPERATING
R~GI~N 11i' P'l
-[i
ac test circuit
..v
'7
:J
12
TEMPERATURE (OC)
Vo (VI
-I-
I• - I - II"GUARANTEE
_ 8PtRATINGr..
13
REGION
,
OUTPUT
I I
10
12
I.
V.. -Voa(V)
16
D
switching time waveforms
Read Cycle
Chip Select and Deselect
r-----.,,---~__1
'~/ ______________________
ADDRESSES
ADDRESSES
D~~l
It:)-
---------.-~~
REAOIWRITE
OUTPUTS
OUTPUTS
·.---u--t-~
D ----------------'
Write Cycle
Power Switching For Reduced Power Applications
ADDRESSES
ADDRESS..:
-y
_____________________
--fl,;:~Om
v" ________
v~ AND
B LEAD
v.
READIWRITE
OUTPUTS
DATA IN
VDD "-9Vt.5%
Note 1: All inputs of the MMll01A accept standard TTL outputs with VCC; +5.0V ±5%.
Note 2: Maximum value for tAC measured at minimum read cycle.
1·4
-:-:~
~National
MOS RAMs
~Semiconductor
MM2101, MM2101-1, MM2101-2 1024-bit (256 x 4)staticMOS RAM
with separate I/O
general description
features
The National MM2101 isa 256 word by 4 bit static
random access memory element fabricated usingNChannel enhancement mode Sil icon Gate technology.
Static storage cells eliminate the need for refreSh and
the additional peripheral circuitry associated with refresh.
The data is read out nondestructively and has the same
polarity as the input data.
• Organization 256 Words by 4 Bits
• Access Time - 0.5 to 1.0 J.lS Max.
• Single +5 V Supply Voltage
• Directly TTL Compatible - All Inputs and Outputs
• Static MOS - No Clocks or Refreshing Required
.• Simple Memory Expansion - Chip Enable Input
The 2101 is directly TTL compatible in all respects:
inputs, outputs, and a single +5 V supply. Two chipenables allow easy. selection of an individual package
when outputs are OR-tied. An output disable is provided
so that data inputs and outpllts can be tied for common
I/O systems. The featqres of this memory device can be
combined to make. a low cost, high performance, and
easy to manufacture memory system.
•
Low Cost Packaging -22 Pin Epoxy B Dual-In-Line
Configuration
•
Low Power - Typically 150 mW
• Tri-State ® Output - OR-Tie Capability
• Output Di.sable Provided for Ease of Use in Common
Data Bus Systems
National's silicon gate technology also provides protec·
tion against contamination, and permits the use of. low
cost Epoxy B packaging.
block and connection diagrams
-.Eo
-...!.o
ROW
SELECT
CEll ARRAY
J2ROWS
J2 COLUMNS
A4 -------._---'
RIW ';;";""--"""'-
INPUT
DATA
CONTROL
OIJ ---I~c-l
eE2
AJ
G~O
A2
A4
Al
RIW
eEl
AO
A3
OIZ
vee
Vec
A5
18
00
A6
17
CE2
004
A1
16
GNO
15
014
01,
14
OOJ
001
10
13
OIJ
012
11
12
002
PIN NAMES
01 1- 0.14
Ao- A7
R/W
CEl, CE2
00
001 004
.;.;...-----L.J
Vcc
00
DATA INPUT
AODRESS INPUTS
READ/WRITE INPUT
CHIP ENABLE
OUTPUT DISABLE
DATA OUTPUT
POWER (+5VI
Order Number MM21010,
MM2101-10 or MM2101-2D
See Package 5
Order Number MM2101.N,
MM2101·1N or MM2101-2N
See Package 17
1-5
II
absolute maximum ratings
O°Cto +70°C
Ambient Temperature Under Bias
_65°C to +150°C
Storage Temperature
Voltage on Any Pin With Respect to Ground
-0.5 V to +7 V
Power Dissipation
1 Watt
dc electrical characteristics
Symbol
Parameter
Min.
III
ILOH
ILOL
ICCl
Input Current
I/O Leakage Current[2)
I/O Leakage Current[2)
Power Supply Current
ICC2
Power Supply Current
VIL
VIH
VOL
VOH
Input "Low" Voltage
Input "High" Voltage
Output "Low" Voltage
Output "High" Voltage
Note 1:
Note 2:
TA ~ o°c to +70°C, VCC ~ 5 V ± 5% unless otherwise specified.
Typ.ll)
Max.
Unit
pA
pA
pA
30
10
15
-50
60
mA
70
rnA
+0.65
VCC
+0.45
V
V
V
V
-0.5
2.2
2.2
Test Conditions
VIN ~ 0 to 5.25 V
CEl = 2.2 V, VOUT ~ 4.0 V
CEl = 2.2 V, VOUT ~ 0.45 V
VIN = 5.25 V, 10 = 0 rnA
TA = 25°C
VIN = 5.25 V, 10 ~ 0 rnA
TA =O°C
IOL = 2.0 rnA
IOH=~150pA
Typical values are for T A = 25°C and nominal supply voltage.
Input and Output tied together.
capacitance
T A = '25° C, f = 1 MHz
Symbol
GIN
GOUT
limits (pF)
Test
Typ.
Input Capacitance (All Input Pins) VIN
Output Capacitance VOUT ~ 0 V
~
0 V
Max.
4
8
8
12
switching time waveforms
READ CYCLE (RIW
.-
~
~
"1 ")
WRITE CYCLE[2)
.
.
'RCV
eEl-
eE2
-
h
/
~......-tco __
\
-
-
DATA OUT
11-
.......--tco-.....
;.,."I .... tOD+
OD ICOMMON 1/01 III
~t!..---=-
----.I
---,"-tCw~
r-
eEl- """""\
\. I--
,--
['OH+
-
CE2
I--
tDFliJl..--.
DATA OUT VALID
.....
/
--J
--'CW-------
~
.-
DATA IN
--
t~l~tDW--OO
X
DATA IN STABLE
~---,wp
tDF is with respect to the trailing edge of CEl, CE2, or 00, whichever occurs first.
During the write cycle, 00 is a logic~1 1 for common I/O and "don't care" for separate 1/0 operation.
00 should be tied low for separate 1/0 operation.
'·6
r-
\. r-
00
R/W-
Note 1:
Not. 2:
Not. 3:
.
'WCy
ADDRESS
ADDRESS
~ l--tDH
X
twR ....
ac electrical characteristics
TA = o"c to +70"C, VCC = 5 V ± 5%, unless otherwise specified.
MM2101
Symbol
Parameter
Min.
Typ.
Max.
Unit
1,000
800
700
200
ns
ns
ns
ns
ns
ns
Test Conditions
READ CYCLE
tRCY
tA
tco
too
tDF[1]
tOH
Read Cycle
Access Time
Chip Enable to Output
Output Disable to Output
Data Output to High Z State
Previous Data Read Valid after
change of Address
1,000
a
a
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL= 100 pF
WRITE CYCLE
tWCY
tAW
tcw
tDW
tDH
twp
tWR
Write Cycle
Write Delay
Chip Enable toWrite
Data Setup
Data Hold
. Write Pulse
Write Recovery
Parameter
1,000
150
900
700
100
750
50
ns
ns
ns
ns
ns
ns
ns
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF
Min.
Typ.
Max.
Unit
500
350
300
150
ns
ns
ns
ns
ns
ns
Input Pulse Levels.: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF
ns
ns
ns
ns
ns
ns
ns
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level. : 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF
Test Conditions
READ CYCLE
tRCY
tA
tco
tOD
tDF[1]
tOH
Read Cycle
Access Time
Chip Enable to Output
Output Disable to Output
Data Output to High Z State
Previous Data Read Valid after
change of Address
500
0
0
WRITE CYCLE
tWCY
tAW
tcw
tDW
tDH
twp
tWR
Write Cycle
Write Delay
Chip Enable to Write
Data Setup
Data Hold
Write Pulse
Write Recovery
500
100
400
280
100
300
50
MM2101·2 (650 ns Access Time)
Symbol
Parameter
Min.
Typ.
Max.
Unit
650
400
350
150
0
ns
ns
ns
ns
ns
ns
Input Pulse Levels: +0,65 to +2.2 V
Input Pul.se Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF
650
150
550
400
100
400
50
ns
ns
ns
ns
ns
ns
ns
Input Pulse Levels: +0.65 to +2:2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF
Test Conditions
READ CYCLE
tRCY
tA
tco
too
tOF[1]
tOH
Read Cycle
Access Time
Chip Enable to Output
Output Disable to Output
Data Output to High Z State
Previous Data Read Valid after
change of Address
650
a
WRITE CYCLE
tWCY
tAW
tcw
tow
tDH
twp
tWR
Note 1:
Write Cycle
Write Delay
Chip Enable to Write
Data Setup
Data Hold
Write Pulse
Write Recovery
tOF is with respect to the trailing edge ,of
...
N
g
MM2101·1 (500 ns Access Time)
Symbol
!:
!:
eel. CE2; or DO, whichever occurs first.
1-7
I
N
D
N,
N
...
o
N
:!
'?JI National
a Semiconductor
MOS RAMs
::i
MM2102, MM2102-1, MM2102-2
1024-bit fully decoded static random access memories
general description
features
The MM2102 family of 1024 word by one bit static
random access read write memories are manufactured
using N-channel enhancement mode silicon gate technology. Static storage cells eliminate the need for clocks
and refresh. Data in and data out have the same polarity
and the read operation is nondestructive.
• Single +5V supply
• All inputs and output directly DTLITTL compatible
• Static operation-no clocks or refreshing required
150 mWtyp
• Low power
• Fast access
MM2102
MM2102-1
MM2102-2
Low threshold silicon gate N-channel technology allows
complete DTLITTL compatibility of all' inputs and
outputs, as well as uingle +5V supply. The separate
chip enable input (CE) controlling the TRI·STATE®
output allows easy memory expansion by OR-tying
individual devices to a data bus.
1/-1S
500 ns
650 ns
• TRI-STATE output for bus interface
• Chip enable allows simple memory expansion
• On chip address decode
The simple interface and high performance make the
MM2102 family ideally suited for those applications,
for large and small. storage capacity, where cost is an
important design consideration.
• All inputs protected against static discharge
•
Low cost 16-pin Epoxy B package .
block and connection diagrams
Dual-ln·Line Package
A,
A,
CELL
ARRAY
32 ROWS
32 COLUMNS
A,
12 OATAOUT
COLUMN 1111 CIRCUITS
A,
n DATAl'
COLUMN SELECTOR
A.
ta Vee
Ao
• aND
TO'V'EW
Order Number MM2102D,
MM2102-1D or MM2102-2D
See Package 3
Order Number MM2102N,
MM2102-1N or MM2102-2N
See Package 15
'·8
absolute maKimum ratings
3:
3:
(Note 1)
N
5N
-o.5V to +7.0V
OoC to HO°C
-5SoC to +l50°C
lW
300°C
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Lead Temperature (Soldering, 10 seconds)
.
3:
3:
dc electrical characteristics
(TA within operating temperature range, Vee = SV ±S%, unless otherwise noted.)
CONDITIONS
PARAMETER
N
MIN
Logical"l"lnput Voltage (V IH )
2.2
. Logical "0" Input Voltage (Vld
-0.5
TYP
MAX
UNITS
Vee
V
0.6S
V
V
2.2
Logical "1" Output Voltage (V OH )
IOH =-l00IlA
Logical "0" Output Voltage (Vod
IOL = 1.9 rnA
0:45
V
Input Load Current (ILl)
V IN = 0 to S.2SV
10
/lA
Output Leakage Cu rrent II LOH )
CE = 2.2V, VOUT = 4.0V
10
/lA
Output leakage Current (J Lod
CE
Power Supply Current Hee ,)
All Inputs = S.2SV, Data Out Open,
TA =2SoC
Power Supply Current (lee2)
All Inputs = S.2SV, Data Out Open,
TA =·O°C
=2.2V, VOUT =0.4SV
30
.,
-100
/lA
60
rnA
70
rnA
MAX
UNITS
ac electrical characteristics
(TA within operating temperature range, Vee = SV ±S%, unless otherwise specified.)
See ac test circuit and switching time waveforms.
PARAMETER
CONDITIONS
MIN
TYP
READ CYCLE
Read Cycle (tRc!
MM2102
MM2102·1
MM2102·2
ns
ns
ns
1000
RtW= V IH
RtW= V IH
RtW= VIH
500
650
Access Time itA)
MM2102
MM2102·1
MM2102-2
1000
500
650
Chip Enable to Output Time (teo)
MM2102
MM2102-1
MM21 02-2
500
350
400
ns
ns
ns
ns
ns
ns
Previous Read Data Valid with
Respect to Address (tOH ,)
50
ns
Previous Read Data Valid with
Respect to Chip, Enable ItOH2 )
0
ns
1-9
o,
N
N
D
N
I
N
ac electrical characteristics (con't)
...
o
N
I
PARAMETER
2!
~
I
CONDITIONS
MIN
I
TYP
I
MAX
I
UNITS
WRITE CYCLE
N
o
...
N
~
~
Write Cycle (twc)
MM2102
MM2102-1
MM2102-2
650
ns
ns
ns
Address to Write Set-up Time (tAW)
MM2102
MM2102-1
MM2102-2
200
150
200
ns
ns
ns
Write Pulse Width (twp)
MM2102
MM2102-1
MM2102-2
750
300
400
ns
ns
ns
Write Recovery Time (tWR)
50
ns
1000
500
I
!
i
Data Set-up Time (tow)
MM2102
MM2102-1
MM21 02-2
800
330
450
ns
ns
ns
Data Hold Time ItOH )
100
ns
Chip Enable to Write Set-up Time (lew)
MM2102
MM2102-1
MM2102-2
.900
400
550
ns
ns
ns
CAPACITANCE
J
Input Capacitance (All Inputs) (C ,N )
(Note 4)
V ,N =OV.TA = 25°C. f=1.0MHz
(Note 2)
3,0
5.0
pF
Output Capacitance (COUT ) (Note 4)
V OUT = OV. TA = 25°C. f = 1.0 MHz
(Note 2)
7.0
10_0
pF
Note': "Absolute Maximum Ratings" are those values beyond which the satety of the device cannot be guaranteed. Except tor "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Positive true logic notation is used: logiCal "1 U ... most posi"tive voltage level, Logical "0" = most negative voltage lavel.
Note 4: Typical values are for TA = 25'C and nominal supply voltage.
switching time waveforms
Write Cycle
RndCycle
...
ADDRESS VIM,
V1L
CHIP
...
--'
~~~
ENABLE
v"
v..,
t'
DATA
OUT
V~
....
r-
v~,
ADDRESS
~
VM-,
v.-
CHIP
ENAlLE
tl f--.....
'-
~Ir
....
V:~~_
V~
~
WRITt
~ I\,I--
- ....
V.
DATA
III
"o~AI .........""'IIIi1hNlfld .. 1JiV"'"
1IIIi1bt,IIMI1ts2G ....
l-10
v... _I.
D~
CHAIGI
v...
...
PATAITAILE
-
~
f--...
r-
....
DATACM
CMAlIE
ac· test .citcuit
AIY m SATE
T'..
Co.
··F
typical performance characteristics
Power Supply Current YO
Temperature
"-"::l
.~
4D
0-
::
..!i!~
~
.ll
30
r--.
20
10
VQ\ :
~
....
t- t- t-
-
25
L-~~~~~~~
-75 -50 -25
50 15 100 '25
°
25
50
AM'IEN.T TEMPERATURE ("el
Input Level. vs Power
Supply Voltage
o
__~~
-15 -50 -25
75 100 125
T. - AMBIENT TEMPERATURE
re)
TA
]
1.75
600
;"',
§ 1.50
0-
~
Vee = 4.5V
500
0-
300
-15 -50 -25
POWER SUPPLY VOLTAGE (V)
....-v /
~~ ......V
< 400
1.25
25
50
]
..
~
200
100
o
0
25
50
15 '00 125
T. - AMBIENT TEMPERATURE
1-11
re)
I
300
V
«
~
0
15 100 125
AMBIENT TEMPERATURE ("C)
400
:I
~
~
.4.~ ~ r--: ::::;:
Write Pulse Width and Chip
Enable-To Output Delay vs
Temperature
Access Time vs Temperature
700
~
Vee
0.~5V
Vl:5 15V
::::::::::;:
r- --
o
0
N
VI T~mper,ature
- -
-75 -50 -25
3C
OutPUt Sink Current
Vee: S.5V
All lNrUT~: 5.5V
DATA OUT OPEN
o
TA
~
Output Source Current
Temperature
VI
f".,
Teo
Vee = 4,5
T~
Vee =4.5
Vee;= 5.5
Teo
T -I
Two
VrT
-15 -50
~25
I
0
25
50
15 100 125
T. - AMBIENT TE~ERATURE
re)
($
NI
N
~
e ~National
.... ~ Semiconductor
II(
MOS RAMs
«I
u.
N
opo
N
:E
:E
tti.
N
opo
N
:E
:E
MM2102A, MM2102AL family
1024-bit (1024 x 1) static random access memories
general description
The MM2102A family of high speed 1024 x l·bit static
random access read/write memories are manufactured
using N-channel depletion·mode silicon gate technology.
Static storage cells eliminate the need for clocks or
refresh circuitry and the resultant cost associated with
them.
a maximum operating current of 33 mA and a guaranteed standby mode down to a power supply voltage
of 1.5V.
features
• Single 5V supply
Low threshold silicon gate N·channel technology allows
complete DTLrrTL compatibility of all inputs and
outputs as well as a single 5V supply. The separate
chip enable input (eE) controlling the TRI-STATE®
output allows easy memory expansion by OR·tying
individual devices to a data bus. Data in and data out
have the same polarity.
• All inputs and outputs directly DTLrrTL compatible
• Static operation-no clocks or refresh
• TRI-STATE output for bus interface
• All inputs protected against static charge
In addition to the MM2102A, a low power version,
the MM2102AL, is also available. This selection offers
• Access time down to 250 ns
block diagram
connection diagram
Dual·ln-Line Package
16 A7
A6
AO
15 AS
A5
~Vee
AI
CEll
ARRAY
32 ROWS
A2
~GND
14
R{W
A.
CE
AI
13
A2
12 DATA OUT
3z COLUMNS
AJ
11 DATA IN
AJ
A4
lU
A4
•
AO
Vee
GNO
COLUMN 1/0 CIRCUITS
R/W
TOP VIEW
COLUMN SELECTOR
AS
A6
A1
A8
Order Number:
MM2102AN-2L
MM2102AN-2
MM2102AN·L
MM2102AN
MM2102AN-4L
MM2102AN-4
MM2102AN-6L
MM2102AN-6
Se. Package 15
Order Number:
MM2102AJ-2L
MM2102AJ-2
MM2102AJ-L
MM2102AJ
MM2102AJ-4L
MM2102AJ-4
MM2102AJ-6L
MM2102AJ-6
See Package 10
A.
truth table
logic symbol
AU
AI
CE
H
L
L
L
RIW
X
L
L
H
DIN
X
L
H
X
MODE
DOUT
Hi-Z
Not selected
Write "0"
L
H
Write "1"
DOUT Read
01.
A2
Al
A4
A5
A6
A7
Dour
AB
A9
1-12
RM
CE
absolute maximum ratings
operating conditions
(Note 1)
-{l.5V to +7V
Voltage at Any Pin
dc electrical characteristics
SYMBOL
Supply Voltage (VCC)
Ambient Temperature (TA)
-{l.5V to +7V
~5°C to +150°C
1W
300"C
Voltage at Any Pin
Storage Temperature
Power Dissipation
Lead Temperature (Soldering, 10 seconds)
MIN
MAX
4.75
5.25
Input Low Voltage
0
-{l.5
Input High Voltage
2.0
+70
0.8
UNITS
V
'c
V
V
VCC
T A; oOe to +7oo e, Vee; ±5%, unless otherwise specified.
PARAMETER
MM2102A,
MM2102A-2,
MM2102A-4,
MM2102A-6
MAX
MIN
CONDITION
MM2102A·L,
MM2102A·2L,
MM2102A-4L,
M1YI2102A·6L
MIN
MAX
UNITS
III
I nput Load Current
VIN = 0 to 5.25V
10
10
ILOH
Output Leakage Current
cr = 2V, VOUT = 2.4V
5
5
!J.A
ILOL
Output Leakage Current
CE
-10
-10
!J.A
ICC
Power Supply Current
45
31
mA
50
33
mA
=
2V, VOUT = 0.4V
All Inputs = 5.25V,
!J.A
III
Oata Output Open,
TA = 2SOC
Power Supply Current
ICC
All Inputs = 5.25V,
Data Output Open,
TA=O°C
VOL
Output Low Voltage
10L = 3.2 rnA
VOH
Output High Voltage
10H = -200!J.A
0.4
0.4
2.4
2.4
V
V
'.
Note 1: "Absolute Maximum Ratings" are those values beyond which the device may be permanently damaged. They do not mean the device
may be operated at these values.
ac electrical characteristics
PARAMETER
SYMBOL
I
(With standard load) TA; oOe to +7oo e, Vee; 5V ±5% unless otherwise specified.
MM2102A·2,
MM2102A·2L
MIN
MAX
MM2102A,
MM2102A-L
MIN
MAX
MM2102A-4,
MM2102A-4L
MIN
MAX
MM2102A·6,
MM2102A·6L
MIN
MAX
250
350
450
650
UNITS
READ CYCLE (Figure 1)
ns
tRC
Read Cycle
tA
Access Time
250
350
450
650
ns
tco
Chip Enable to Output
100
150
200
200
ns
Time
tOHl
Previous Read Data Valid
40
40
40
50
ns
0
0
0
0
ns
ns
with Respect to Address
tOH2
Previous Read Data Valid
with ·Respect to Chip
Enable
WR ITE CYCLE (Figure 2)
twc
Write Cycle
250
350
450
650
tAW
Address to Write Set-Up
20
20
20
20
ns
twp
Write Pulse Width
100
150
200
200
ns
tWR
Write Recovery Time
0
0
0
0
ns
tow
Date Set· Up Time
85
125
175
175
ns
tOH
Data Hold Time
0
0
0
0
ns
tcw
Chip Enable To Write
100
150
200
200
ns
Set·Up
1-13
ac electrical characteristics
ac test circuit
T A = 25°C, f = 1 MHz
Vce
I
SYMBOL
LIMIT (pF)
PARAMETER
TYP
I
MAX
I
5
1.Z4I<
CAPACITANCE 2
CIN
I
COUT
Input Capacitance (All Inputs VIN = OV)
3
Output Capacitance, Vo = OV
4
1.13k
6
Note 2: This parameter is guaranteed by periodic testing
T
CL=10DpF
switching time waveforms
VIH
VIH
ADDRESS
ADDRESS
VIH-+---"
CiiW
EMm
VIL
VIH
"fIIili
EiiAm
--+-----"'----+_+'
VIL -+-,~------------+'
toH2
VDH----------"'"\
DATA
READI
WRITE
OUT
VDL-------------'
VIH
VIL ----,~-------
toHl
FIGURE 1. Read Cycl.
-
30
~
20
Output Sink Current
vs Temperature
Vee = S.5V
All INPUTS '" 5.5V
DATA OUT OPEN
.!S
~
Output Source Current
Temperature
V5
i'- .......
>-
t--
1
--
~
~
I--
~
e- -
'"in"
>-
'"
Vee
'4.~J::::=,.1"""
~
>~
o
10
I
I
o
o
o'-~--'--'----'--'--'--'---'
-75 -50 -25
TA
-
0
25
50
-75 -50 -25
75 100 125
0
25
50
75
-75 -50 -25
100 125
Access Time vS Temperature
"~
600
un
.
>-
4.75
5.00
5.25
POWER SUPPLY VOLTAGE IV)
5.50
,/
...... /
Vee'" 4.5V
500
1 .1,
'"
1.25
400
75
100 125
I
300
;:
>~
50
400
700
-
1.75
~
25
Write Pulse Width and Chip
E nab Ie-ToO utput Delay vs .
Temperature
Input Levels V5 Power
2.00 . - - - - - , - - - . . . , - - , - - - . . . ,
0
TA - AMBIENT TEMPERATURE (Oc')
TA - AMBIENT TEMPERATURE (OC)
AMBIENT TEMPERATURE f'C)
Supply Voltage
~
'" ~::::::: Ve~ 'sl,v
~
Jl
j
.L
VOjI -. O.45V
,~
>-
I-"
300
- 75 -50 -25
~
0
25
/'
50
/
w
'"
75 100 125
Vee'" 4.5
........
Tw,
V;e •
Vee - 5.5
T,o
200
;:
100
TA - AMBIENT TEMPERATURE /"C)
1-18
]:
Teo
~75
~.5
Tw,
TT
-50 -25
I
0
25
50
75
100 125
TA - AMBIENT TEMPERATURE eel
MOS RAMs
~National
a·Semiconductor
s:
s:
....::::t
I\)
s:
s:
~
....
.....
MM2111. MM2111-1. MM2111-21024 -bit (256 x 4) static MOS RAM
with common 1/0 and output disable
general description
features
The National MM2111 is a 256 by 4 static random
access memory element fabricated using N-channel
enhancement mode Silicon Gate technology. Static
storage cells eliminate the need for refresh and the
peripheral circuitry associated with refresh. The data is
read out nondestrlictively and has .the same polarity as
the input data. Common Data Input/Output pins are
provided.
•
The 2111 is directly TTL in all respects: inputs, outputs
and a single +5 V supply. The two Chip·enables allow
easy selection of an individual package when outputs
are OR-tied. The features of this memory device can be
combined to make a low cost. high performance. and
easy to manufacture memory system.
• Simple Memory Expansion -Chip Enable. Input
Organization 256 Words by 4 Bits
• Common Data Input and Output
• Single +5 V Supply Voltage
•
Directly TTL Compatible - All Inputs and Outputs
• Static MOS •
No Clocks or Refreshing Required
Access Time - 0.5 to 1.0 I1S Max.
•
Low Cost Packaging - 18 Pin Epoxy B Dual-In-Line
Configuration
•
Low Power - Typically 150 mW
• Tri-State ® Output - OR-Tie Capability
National's silicon gate technology provides excellent
protection against contamination and permits the use of
low cost Epoxy B packaging.
block and connection diagrams
-.2!0 Vce
-.!.o GNO
AD
ROW
SElECT
RIW
A,
AZ
A,
16
RlW
AD
15
eE,
A5
'4
I/O.
A6
13
1/03
Ai
lZ
I/Oz
GNO
11
1/01
00
'0
GEz
MEMORY ARRAY
32 ROWS
32 COLUMNS
COLUMN I/O CIRCUITS
'NPUT
DATA
CONTROL
Vec
A3
COLUMN SELECT
PIN NAMES
ADDRESS INPUTS
OUTPUT D'SABLE
R/W
READ/WRITE INPUT
CEI
CHIP ENABLE 1
CE2
CHIP ENABLE 2
1/0,. 1104 DATA INPUT/OUTPUT
AO·A7
00
Order Number MM2111D,
MM2111·1D or MM2111-2D
See Package 4
Order NumberMM2111N,
MM2111-1N or MM2111-2N
See Package 16
00
1-19
II
absolute maximum ratings
O°C to +70°C
Ambient Temperature Under Bias
Storage Temperature
-65°C to +150°C
Voltage On Any Pin With Respect to Ground -O.5Vto+7V
Power Dissipation
1 Watt
dc electrical characteristics
Symbol
Parameter
III
ILOH
ILOL
ICCl
Input Current
I/O Leakage Current[2]
I/O Leakage Current 121
Power Supply Current
ICC2
Power Supply Current
VIL
VIH
VOL
VOH
Input" Low" Voltage
Input "High" Voltage
Output "Low" Voltage
Output "High" Voltage
Note 1:
TA = o°c to +70°C, VCC = 5 V ±5%, unless otherwise specified.
Min.
Typ.11]
Max.
Unit
Test Conditions
30
10
15
-50
60
/J. A
/J. A
/J. A
mA
70
mA
VIN=Ot05.25V
CE = 2.2 V, VI/O = 4.0 V
CE = 2.2 V, VI/O = 0.45 V
VIN = 5.25 V, 11/0 = 0 mA
TA = 25°C
VIN = 5.25 V, 11/0 = 0 mA
TA = O°C
+0.65
VCC
+0.45
V
V
V
V
-0.5
2.2
2.2
Typical values are for T A::;: 25°C and nominal supply voltage.
capacitance
T A = 25°C, f = 1 MHz
Symbol
i
Limits (pF)
Test
Input Capacitance (All Input Pins) VIN = 0 V
I/O Capacitance VI/O = 0 V
CIN
CI/O
10L = 2.0 rrA
IOH=-150/J.A
Typ.
Max.
4
10
8
15
.
switching time waveforms
READ CYCLE (R/W = "1")
.
WRITE CYCLE
.
tRCY
.
1--
ADDRESS~
-
. 1 - tCD -
.... too ......
\.
_________ t A _
-- -----
DATA 110
;- r-
\.
~I
OUTPUT OISABLE
-- -----
1
tOH .....
'l--'OF(1}.....
DATA OUT VAllO
CEI, CE2,
--
.1-+---------tCW----\.
1-
r
OUTPUT DISABLE
--J
DATA 110
-
--tDF--::::-I_
X
tOW-------+-
DATA IN STABLE
tDH~t::
.t..
twp-----------.. -tWR .....
READ/WRITE
Note 1:
1,--
ADDRESS
1CEI, CE2
.
twCY
tOF is with respect to the trailing edge of CE1, CE2, or 00, whichever occurs first.
1-20
-.-tAW______.'
r-
ac electrical characteristics
TA ~ o°c to +70°C,Vcc ~5 V ± 5%, unless otherwise specified.
MM2111
Symbol
Parameter
Min.
Typ.
Max.
Unit
1,000
800
700
200
ns
ns
ns
ns
ns
Test Conditions
READ CYCLE
tRCY
tA
tco
tOD
tDF[1]
tOH
Read Cycle
Access Time
Ch ip Enable to Output
Output Disable to Output
Data Output to High Z State
Previous Data Read Valid after
change of Add ress
1,000
0
0
ns
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20.ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL ~ 100 pF
WRITE CYCLE
tWCY
tAW
tcw
tDW
tDH
twp
tWR
..
Write Cycle
Write Delay
Chip Enable to Write
Data Setup
Data Hold
Write Pulse
Write Recovery
1,000
150
900
700
100
750
50
nS
ns
ns
ns
ns
ns
ns
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5V
Output Load: 1 TTL Gate and
CL ~ .100 pF
MM2111-1 (500 ns Access Time)
Symbol
Parameter
Min.
Typ.
Max.
Unit
500
350
300
1.50
ns
ns
ns
ns
ns
. Test Conditions
READ CYCLE
tRCY
tA
tco
too
tDF[1]
tOH
Read Cycle
Access Time
Chip Enable to Output
Output Disable to Output
Data Output to High Z State
Previous Data Read Val id after
change of Address
500
0
0
ns
500
100
400
280
100
300
50
ns
ns
ns
ns
ns.
ns
ns
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5V
Output Load: 1 TTL Gate and
CL ~ 100 pF
WRITE CYCLE
tWCY
tAW
tcw
tow
tDH
twp
tWR
Write Cycle
Write De.lay
Chip Enable to Write
D.ata Setup
Data Hold
Write Pulse
Write Recovery
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL~100pF
MM2111-2 (650ns Access Time)
Symbol
Parameter
Min.
Typ.
Max.
Unit
650
400
350
1.50
ns
ns
ns
ns
ns
Test Conditions
READ CYCLE
tRCY
tA
tco
too
tDF 111
tOH
Read Cycle
Access Time
Chip Enable to Output
Output Disable to Output
Data Output to High Z State
Previous Data Read Valid after
change of Address
650
0
0
ns
650
150
550
400
100
400
50
ns
ns
ns
ns
ns
ns
ns
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL~100pF
WRITE CYCLE
tWCY
tAW
tcw
tow
tDH
twp
tWR
Write Cycle
Write Delay
Chip Enable to Write
Data Setup
D.ata Hold
Write Pulse
Write Recovery
1·21
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL ~ 100pF
:s:
:s:
N
...........,
N
o
N,
N
...
N
~
~
MOS RAMs
~National
a
Semiconductor
MM2112, MM2112-2 1024-bit (256 x 4) static MOS RAM
with common data I/O
general description
features
The National MM2112 is a 256 by 4 static random
access memory element fabricated using N-Channel
enhancement mode Silicon Gate technology. Static
storage cells eliminate the need for refresh and the
peripheral circuitry associated with refresh. The data is
read out nondestructively and has the same polarity as
the input data. Common Data Input/Output pins are
provided.
• Organization 256 Words by 4 Bits
The MM2112 is directly TTL in all respects: inputs,
outputs and a single +5 V supply. The Chip-enable
allows easy selection of an individual package when
outputs are OR-tied. The features of this memory device
can be combined to make a low cost, high performance,
and easy to manufacture memory system.
• Simple Memory Expansion - Chip Enable Input
• Common Data Input and Output
• Single +5 V Supply Voltage
• Directly TTL Compatible - All Inputs and Outputs
• Static MOS - No Clocks or Refreshing Required
• Access Time - 0.65 to 1 fJ.S Max.
•
Low Cost Packaging - 16 Pin Epoxy B Dual·ln·Line
Configuration
•
Low Power - Typically 150mW
• Tri-State ® Output - OR-Tie Capability
National's silicon gate technology provides excellent
protection against contamination and permits the use of
low cost Epoxy B packaging.
block and connection diagrams
AU
ROW
SElECT
MEMORY ARRAY
32 ROWS
32 COLUMNS
- - - - 0 VCC
16
A3
----.!!..o GNO
A2
15
A4
AI
14
R/W
VCC
AO
13
CE
As
12
1104
A6
II
1103
A1
10
1102
GNO
110 1
COLUMN 110 CIRCUITS
INPUT
DATA
CONTROL
1103
COLUMN SElECT
12
1104
PIN NAMES
ADDRESS INPUTS
FlEAD/WRITE INPUT
CHIP ENABLE INPUT
110 1. 1/ °4 DATA INPUT/OUTPUT
POWER (+5 Vl
VCC
AO·A7
FlIW
CE
Order Number MM2112D
or MM2112-2D
See Package 3
Order Number MM2112N
or MM2112-2N
See Package 15
R/W
1-22
absolute maximum ratings
O°C to +70°C
Ambient Temperature Under Bias
-65°C to +150°C
Storage Temperature
Voltage On Any Pin With Respect to Ground -0.5 V to +7 V
1 Watt
Power Dissipation
s:
s:N
....
....
N
dc electrical characteristics
Parameter
Symbol
Min.
III
ILOH
ILOL
ICCl
Input Current
I/O Leakage Current
1/0 Leakage Current
Power Supply Current
ICC2
Power Supply Current
VIL
VIH
VOL
VOH
Input "Low" Voltage
Input "High" Voltage
Output "Low" Voltage
Output "High" Voltage
Typical values are for T A
Note 1:
capacitance
::;0
Typ.I!1
Max.
Unit
Test Conditions
30
10
15
-50
60
pA
pA
pA
mA
70
mA
VIN = 0 to 5.25 V
CE = 2.2 V, Vila = 4.0 V
CE = 2.2 V, VI/O: 0.45 V
VIN = 5.25 V, 11/0: 0 mA
TA = 25°C
VIN: 5.25 V, 11/0 = 0 mA
TA = O°C
+0.65
VCC
+0.45
V
V
V
V
-0.5
2.2
2.2
10L = 2 mA
IOH=-150pA
25°C and nominal supply voltage.
T A = 25°C, f = 1 MHz
Symbol
CIN
CliO
N
TA = o°c to +70°C, VCC = 5 V ± 5% unless otherwise specified.
Limits (pF)
Test
Typ.
4
10
Input Capacitance (All Input Pins) VIN = 0 V
1/0 Capacitance VI/O = 0 V
Max.
8
18
switching time waveforms
READ CYCLE (RIW = "1 ")
'H'
- H+
1-
-
J-
CE
~
,"ru, ,"u ... ,
-
.
WRITE CYCLE #1
IWCYT
.
ADDRESS
--. _1-----teST
....--.r~CHl
~
1
CE
:1+-'OW1DATA IN
X
INPUT/OUTPUT
-
REAOIWRITE
-.
STABLE
'OH1(1)-
t~\:U
-;z.;:::1
iX
-.
ADDRESS
.
WRITE CYCLE #2
----N
1-:--
I~
..-tCS2
i--
~
REAOIWRITE
'AWl _ t W P I _ ....-tWRt--
-STABLE
tW02 __
.. tAW2 ...
CH2
~1_tDW2"
IDATA IN
INPUT/OUTPUT
--t
1....
I
CE
X
,
tWCV2
X
'1-'oH2 11)
_'WR2 .... 1
I
Note 1:
Data Hold Time (TOHI is referenced to the trailing edge of CHIP ENABLE (CE) or READ/WR ITE (R/W) whichever comes first.
1-23
o
ac electrical characteristics
T A = 0° C to +70° C, VCC = 5 V ± 5% unless otherwise specified.
MM2112
Symbol
Parameter
Min.
Typ.
Max.
Unit
1,000
800
200
ns
ns
ns
ns
ns
Test Conditions
READ CYCLE
tRCY
tA
tco
tCD
tOH
Read Cycle
Access Time
Chip Enable to Output Time
Chip Enable to Output Disable Time
Previous Read Data Valid After
Change of Address
1,000
0
50
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL=100pF
WRITE CYCLE #1
Write Cycle
tWCYl
Address to Write Setup Time
tAWl
WTite Setup Time
tDWl
Write Pulse Width
tWPl
Chip Enable Setup Time
tCSl
Chip Enable Hold Time
tCHl
Write Recovery Time
tWRl
Data Hold Time
tDHl
WRITE CYCLE #2
tWCY2
tAW2
tDW2
tW02
tCS2
tCH2
tWR2
tDH2
Write Cycle
Address to Write Setup Time
Write Setup Time
Write to Output Disable Time
Chip Enable Setup Time
Chip Enable Hold Time
Write Recovery Time
Data Hold Time
50
100
ns
ns
ns
ns
ns
ns
ns
ns
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF
1,050
150
650
200
0
0
50
100
ns
ns
ns
ns
ns
ns
ns
ns
Input Pulse Levels:+0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF
850
150
650
650
0
100
a
1-24
ac electrical characteristics
(Continued) TA" o°c to +70°C, VCC = 5 V ± 5% unless otherwise specified,
MM2112·2 (650 ns Access Time)
Symbol
Parameter
Min.
Typ.
Max.
Unit
650
500
150
ns
ns
ns
ns
ns
Test Conditions
READ CYCLE
tRCY
tA
tco
tCD
tOH
Read Cycle
Access Time
Chip Enable to Output Time
Chip Enable to Output Disable Time
Previous Read Data Valid After
Change of Address
650
0
50
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL=100pF
WRITE CYCLE #1
Write Cycle
twCYl
Address to Write SetupTime
tAWl
Write Setup Time
tOWl
Write Pulse Width
tWOl
Chip Enable Setup Time
tCSl
Chip Enable Hold Time
tCHl
Write Recovery Time
twRl
Data Hold Time
tDHl
WRITE CYCLE #'l.
tWCY2
tAW2
tDW2
twD2
tCS2
tCH2
twR2
tDH2
Write Cycle
Address to Write Setup Time
Write Setup Time
Write to Output Disable Time
Chip Enable Setup Time
Chip Enable Hold Time
Write Recovery Time
Data Hold Time
500
100
350
350
0
0
50
50
50
700
100
350
200
0
0
50
50
1·25
ns
ns
ns
ns
ns
ns
ns
ns
Input Puise Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF
ns
ns
ns
ns
ns
ns
ns
ns
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100pF
o
~National
MOSRAMs
~ Semiconductor
MM5269 1024-bit (256 x 4) fully decoded static RAM
with on chip registers
general description
National's Silicon Gate process provides protection
against contamination and permits the use of low cost
Epoxy B packaging_
The National MM5269 is a 256 word x 4 bit Static
Random Access Memory device fabricated using NChannel enhancement mode Silicon Gate technology_
Static storage cells eliminate the need for refresh and
the additional peripheral circuitry associated with refresh_
Data in and data out have the same polarity_
features
• Organization 256 Words by 4 Bits
• Access Time - 0.5 to 1.0 Ils
The MM5269 is fully TTL compatible including inputs,
outputs and power supply_ The chip enable input allows
memory expansion and the address latch feature eliminates the need for external address registers_ The output
enable is provided for systems which use a common
input/output data bus_ All of the features of this
memory device can be combined to make a low cost,
high performance and easy to manufacture memory
system_ System design costs are also minimized because
of the ease-of-use of the MM5269_
• On Chip Address and Chip Enable Registers
• Directly TTL Compatible - All Inputs and Outputs
• Single +5 V Power Supply
• Tri-State ® Output - OR-Tie Capability
• Output Enable for Common Data Bus Systems
• Static Memory - No Refresh Required
•
Packaged in a 22 Pin Epoxy B Dual-In-Line
block and connection diagrams
All
..
22
8
AI
0 vee
- - - 0 GND
MEMORY ARRAY
J2 ROWS
J2 COLUMNS
Vce
AJ
A2
21
A4
AI
20
WE
AO
19
fE
AJ
A5
18
DE
A4
A6
17
LATCH
ROW
SELECT
A2
A7
16
DO.
GNO
15
D••
15
0',
I.
OOJ
13
00,
10
lJ
DIJ
11
012
11
12
002
0'4
D'J
0'2
01,
CE
LATCH
WE
DE
Order Number MM5269D
See Package 5
Order Number MM5269N
See Package 17
19
EE
REG'STER
17
20
18
1-26
s:
s:.U1
absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Power Dissipation
Lead Temperature (10 sl
-0.5 V to +7.0 V
aOCta +70°C
-65°C to +l50°C
1 Watt
300°C
dc electrical characteristics
Symbol
VIH
VIL
VOH
VOL
III
ILOH
ILOL
ICC
Min.
LogiG "1" Input Voltage
Logic "0" Input Voltage
Logic "1" Output Voltage
Logic "0" Output Voltage
Input Load Current
Output Leakage Current
Output Leakage Current
Power Supply Current
Typ.
2.2
-0.5
2.2
Max.
Unit
VCC
0.65
V
V
'V
V
/lA
/lA
/lA
mA
0.45
10
15
-50
70
acelectrical characteristics
Symbol
CD
(VCC; 5.0 V ± 5%, o°c.;;;; TA';;;; +70°CI
Parameter
?
N
en
Test Conditions
10H; -150 /lA
10L; 2.0 mA
o V .;;;; VIN .;;;; 5.0 V
CE; 2.2V, Vo ; 4.0 V
CE; 2.2 V, VO; 0.45 V
VIN'= 5.25 V, 10; 0 mA, TA; O°C
u
(VCC; 5.0 V ± 5%, o°c.;;;; TA';;;; +70°CI
Parameter
Min.
Typ.
Max.
Unit
1,000
ns
ns
Test Conditions
READ CYCLE
Read Cycle
Access Time
tRCY
tA or
tACL
tOE
tLP
tAS
tAH
1,000
Output Enable to Output Time
Latch Pulse Width
ADD & CE to Latch Setup Time
ADD & CE to Latch Hold Time
200
100
100
ns
ns
ns
ns
1,000
200
ns
ns
650
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
500
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL; 100 pF
WRITE CYCLE
Write Cycle
Address and CE to Write Setup
Time
Write Pulse Width
Write Recovery Time
Write to Output Disable Time
Data Setup Time
Data Hold Time
Ch ip Enable to Write
Latch Pulse Width.
Add & CE to Latch Setup Time
Add & CE to Latch Hold Time
tWCY
tAW
twp
tWR
too
tow
tOH
tcw
tLP
tAS
tAH
400
350
100
750
200
100
100
Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL;100pF
switching time waveforms
READ CYCLE (WE; "0")
..
tRCY
~
tAS -1-
tAH
1'1/1/1
STABLE
MAY CJ./ANGE',
CE~
SJSlE
LAT.........
ADDRESS;'
/1/
WRITE CYCLE
~[
LAT••
--t.::;!:;t
tAO
lAS
ADDRESS )twjj/Z;/x]
.. /'.
......
CE~
,......
STABLE
I
'oe
DATA OU10/,1//;0 ~!.t:!;"i/:;;/,;:>,~ 'TRI-STATE',' .',
--
~ -·~----tACl
' '1-'. 'i,,' )NVAllD
MAY CHANGE
-'AW-we
'A
:<
----_.-
VALID
DATA OUT
1·27
':MAV CHANGE
~"MAV CHANGE
DATA IN/~/·I,/,/"",;,
f-
oe
--Lr
t.w. v: - - . - - - - . - ·
.x
'wp
10.::-'00--*
RAY CHANGE
STABLE
J:--'-~DW
~[
~\
TRI-$TATE
,14.-tDH
-'WR
lI?A National
~ Semiconductor
MOS RAMs
MM4270 TRI-SHARE™extended temperature range
4096-bit dynamic random access read/write memory
general description
The MM4270 is a 4096·bit dynamic random access
memory with TRI·SHARE. Because of this unique
design featiJre, National is able to package a 4k device
in an lS-pin dual·in·line package. The device is manu·
factured using N·channel silicon gate technology with a
single transistor cell which provides higher density on a
monolithic chip and thus lower cost.
write. the TSP must be pulsed low after the minimum
hold time and the appropriate data placed on the I/O.
When the MM4270 goes into write, the output ci rcuit is
disabled. If the TSP is low at the start of the cycle, the
memory is not selected but it will be refreshed if the
chip enable clock is pulsed.
The TRI·SHARE Port (TSP) is a multifunction input
that. along with a common input/output, allows National
to manufacture an 18'pin version ofa 4k RAM. The
functions controlled by the TSP are read/write. VCC.
and logical chip select. In order to understand how the
TSP works, consider the timing diagrams. The state of
the TSP at the leading 'edge of the chip enable clock
determines whether the device is selected. If it is at a
TTL high level, the chip is selected and the device goes
into a read mode after chip enable goes high. This high
level also performs a VCC function in that it enables
a reference voltage for a TTL high output. The supply
for the output buffer is VOO, not the TRI·SHARE Port;
thus. no special driver is required. In order to perform a
features
•
•
•
•
•
•
•
•
•
•
4096 x 1 bit organization
Access time 270 ns maximum
Cycle time 470 ns minimum
TRI·SHARE port
High memory density-18'pin package
TTL compatible inputs (except chip enable)
TRI·STATE@ common input/output
Registers on chip for addresses and chip select
Two power supplies, +12V. -5V
Simple read·modify·write operation
block and connection diagrams
Dual·ln·Line Package
TSP(5)
CHIP
Vss
All (4)
AtO(3)
A8
1.
17
Al
A6
1&
15
V 0
ENABLE
14
AS
13
A4
12
11
A3
lD
A9{Z)
ABU')
Al(16)
A6(15)
AS (12)
..-...."0
A411f1
).)
All101
A2(9)
AHa)
AD(')
~
M
W
rn
~
M
Order Number MM4270D
See Package 4
Voo (141 _ _ +lZV
vssual - -
~
TO. VIEW
CEI13.1
OV
Pin Names
Vaa (1) _ _ ,-5V
AO-All
CE
TSP
I/O
Address Inputs *
Chip Enable
TRI·SHARE Port
DIN/DoUT
"Refresh Addsss AO-A5
1·28
Vss
VDD
Power (-5V)
Power (+12V)
VSS
Ground
M
M
eril
3:
3:
absolute maximum ratings
.a::.
-55°C to +85°C
4J5°C to +150o C
-o.3V to +25V
Operating Temperature Range
Storage Temperature
All Input or Output Voltages with Respect
to the Most Negative Supply Voltage, VBB
Supply Voltages VDD and VSS with
Respect to VBB
Power Dissipation
N
....
0
-o.3V to +20V
1.0W
ac electrical characteristics
T A = -55°C to +85°C, VDD = 12V ±5%, VBB (Note 2) = -5V ±10%, VSS = OV,.unless otherwise noted
SYMBOL
~fol
PARAMETER
CONDITIONS
MIN
TYP(3)
MAX
UNITS
III
Input Load Current
VIN = OV to VIH max. (All Inputs Except CE)
0.Q1
10
ILC
I nput Load Current
VIN =OV to VIHC max
0.Q1
10
IlA
IILOI
Output Leakage Current Up
CE = VILC, Va
0.01
10
IlA
IDDl
VOO Supply Current During
110
200
IlA
20
50
mA
35
70
mA
= ov to 5.25V
IlA
For High Impedance State
CE = -IV to +0.6V, (Note 4)
CE "OFF"
IDD2
VDO Supply Current Du'ring
CE = VIHC, TA
= 25°C
I
CE "ON"
~
IDDAV1
Average VDO Current
TA
= 25°C, Cycle T;me = 470 ns, tCE = 300 ns
5
100
IlA
0.6
V
VCC+l
V
188
Vas Supply Current Average
VIL
Input Low Voltage
VIH
I nput High Voltage
VILC
CE Input Low Voltage
-1.0
1.0
V
VIHC
CE Input High Voltage
VDD-1
VDD+l
V
VOL
Output Low Voltage
IOL = 2.0 mA
0.45
V
VOH
Output High Voltage
IOH
tT
= 20 ns,
-1.0
(Figure 4)
2.2
0.0
= -2.0 mA
V
2.4
Note 1: uAbsol'ute Maxi'mum Ratings" are those values beyond which the safety of the device cannot be g,uaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: The only requirement for the sequence of applying voltage to the device is that VOD or VSS should never be O.3V more negative than
VB8·
/
Note 3: Typical values are for T A = '2SoC and nominal power supply voltages.
Note 4: The IDO current is to VSS: The IS8 current is the sum of all leakage currents.
ac electrical characteristics
SYMBOL
TA = _55°C to +85°C, VDD = 12V ±5%, VBB = -~V ±10%
PARAMETER
CONDITIONS
MIN
TVP
MAX
UNITS
READ, WRITE, READ/MODIFY!WRITE, AND REFRESH CYCLE
ms
Time Between Refresh
o
ns
Address Hold Time
100
ns
CE "OFF" Time
130
ns
CE Transition Time
10
CE "OFF" to Output High
o
ns
o
ns
50
ns
Address to CE Set-Up Time
tAC is Measured From End of Address Transition
40
ns
Impedance State
tTC
IX)
is tl
is th
v is
, is
TR I·SHARE Port to CE Set·Up
Ti'me
tTH
TRI·SHARE Port Hold T;me
READ CYCLE
ns
470
tCY
Cycle Time
tCE
CE "ON"Time
tT
tco
CE Output Delay
CLOAD = 50 pF, Load
tACC
Address to Output Access
Ref 1 = 2.0V. Ref 0 = O.BV
tTL
CE to TSP
tAce = tAC + teo + tT
~
20 ns
300
c
One TTL Gate
1-29
3000
ns
250
ns
270
o
ns
ns
I
0
I'
C'I
switching time wave
,...0
N
o::t
o::t
~
~
~
~
ac electrical characteristics
SYMBOL
ADDRESS
VIL
ADORES
CAN,
~
tAC
VIHC
CE
VILC
I
VIH
TSP
TSP CAN
CHANGE
VIL
I
-'
VOH
DOUT
VOL
PARAMETER
T A = _55°C to +85"C. VDD
CONDITIONS
READ/MODIFY/WRITE CYCLE
tRWC
VIH
(Continued)
Read Modify Write (RMW)
Cycle Time
tCRW
CE Width During RMW
twc
TSP to CE "ON"
tT'" 20 ns
tW2
TSP to CE "OFF"
CLOAD = 50 pF. Load = One TTL Gate
twp
TSP Pulse Width
Ref 1 = 2.0V. Ref 0
tD
DIN to CE "OFF"
tACC = tAC + tco + tT
tDH
DIN Hold Time
tco
CE to Output Delay
tACC
Access Time
tWD
TSP to Output High Impedance
tM
MOdify Time
= O.8V
CAPACITANCE (Note 1)
CS
CAD
Address Capacitance,
CCE
CE Capacitance
VIN = Vss
CliO
Data 1/0 Capacitance
VOUT = OV
CIN
TSP Capacitance
VIN
VIN = Vss
= Vss
Note 1: Capacitance measured with Boonton Meter or effective capacitance calculated from the e
equal to a constant 20 rnA.
switching time waveforms
(Continued)
Read Modify Write Cycle
VIH
ADDRESS
VIL
-
V"IH
ADDRESS
ADDRE
CAN
CHAN!
tAC
Vil
CE
VIHC
VILe
----t-"q
CE
TSP
VILC - - -
Vil
VIH
VIH
D'N
TSP
VIL
TSP C,
CHAN
----+
Vil
----t---f----+-h
----t--+----+-t-'
VOH DOUT
-
VOL -
-
-HIGH IMPEDANCE
--1- - -
I-t
HIGH IMPEDANCE
""'---...,f--------
ACC( Z 7 0 ) -
Note 1; If DIN is forced prior to DOUT becoming high impedance (tW[
then maximum ambient temperature should be derated by TOV/TCYCL
Where TOV is time betwe.n.forcingDIN and DOUT becoming TRI-STA'
Note 2: V I L MAX is the reference level, for measuring timing of the
Note 1; For Refr'
entire tAH period.
Note 2;, VILMAX
Note 3; VIH MIN
Note 4; VSS + 2,C
i
TSpand
Note 3:
TSp and
Note 4:
DINVIH MIN is the reference level for measuring timing of the,
DIN.
VSS + 2.0V is the reference level for measuring timing of CEo
Note 5: VOO - 2V is the reference level for measuring timing of CEo
Note 5; VDD - 2'
Note 6: VSS + 2.0V is the reference level for measuring timing of DC
+ 2.e
Note 7; VSS + O.~
high output.
Note 6; VSS
Note 7: VSS + O.8V is the reference level for measuring timing of DC
low output.
Note 8: For minimum cycle, tM == 0, for test purposes tM .. 10 ns.
1-32
absolute maximum ratings
-ssOe to +8Soe
--usoe to +lS0oe
-o.3V to +2SV
OiJerating Temperature Range
Storage Temperature
All Input or Output Voltages with Respect
to the Most Negative Supply Voltage, VSS
Supply Voltages VDD and VSS with
Respect to VSS
Power Oissipation
-o.3V to +20V
1.OW
ac electrical characteristics
T A = -ssoc to +8soe, VOD = 12V ±S%, VSS (Note 2) = -5V ±10%, VSS = OV, unless otherwise noted
SYMBOL
CONDITIONS
TYP(31
MAX
UNITS
0.01
10
IJA
= OV to VIHC max
0.01
10
JJA
VILC, Vo
0.01
10
IJA
110
200
JJA
20
50
mA
35
70
rnA
PARAMETER
MIN
III
Input Load Current
VIN = OV to VIH max. (All Inputs Except CEI
ILC
I nput Load Current
VIN
llLOI
Output Leakage Current Up
CE
100.1
VOO Supply Current During
CE "OFF"
=
=
OV to 5.25V
For High Impedance State
CE = -IV to+0.6V; (Note 41
VDO Supply Current During
1002
CE "ON"
Average VDO Current
100AVl
ISB
VBS Supply Current Average
VIL
1nput Low Voltage
VIH
Input High'Valtage
VILC
VIHC
TA = 25'C. Cycle Time = 470 ns. tCE = 300 ns
5
100
IJA
-1.0
0.6
V
2.2
VCC+l
V
CE Input Low Voltage
-1.0
1.0
V
CE Input High Voltage
VOO-l
VOO+l
V
0.45
tT = 20 ns. (Figure 4)
VOL
Output Low Voltage
IOL = 2,0 mA
0.0
VOH
Output High Voltage
IOH = -2.0 rnA
2.4
V
V
Note 1: ,. Absolute Maximum Ratings H are those values beyond whictl the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated
at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Not. 2: The only requirement for the sequence of applying voltage to the device is that VD.D or VSS should never be 0.3V more negative than
VBS·
No!e 3: Typical values are for T A = 25'C and nominal power supply voltages.
Note 4: The 100 current is toVSS. The ISS current is the sum of all leakage currents.
ac electrical characteristics
SYMBOL
I
TA =-SSOc to +8SoC, VDD = 12V ±S%, Vss = -sv ±10%
PARAMETER
CONDITIONS
I
MIN
I
TYP
I
MAX
I
UNITS
READ, WRITE, READIMOOIFY/WRITE, AND REFRESH CYCLE
tREF
Time Between Refresh
tAC
Address to CE Set·Up Time
tAH
ms
o
ns
Address Hold Time
100
ns
tcc
CE "OFF" Time
130
tT
CE Transition Time
10
tCF
CE "OFF" to Output High
Impedance State
o
ns
TRI~SHARE
o
ns
50
ns
'TC
tAC is Measured From End of Address Transition
Port to CE Set·Up
ns
40
ns
Time
tTH
TRI·SHARE Port Hold Time
READ CYCLE
tCY
Cycle Time
tCE
CE "ON" Time
tT= 20 ns
tco
CE Output Delay
CLOAD = 50 pF. Load = One TTL.Gate
tACC
Address to Output Access
Ref 1 = 2.0V. Ref 0
tn
CEtoT~P
tACC = tAC + tco + 'T
470
300
= O.SV
1·29
o
ns
3000
ns
250
ns
270
ns
ns
D
switching time waveforms
Read Cycle
TCY(470}
VIH
ADDRESS
VIL
ADDRESS ) (
CAN
CHANGE
~
tV
CD
-
--tAH(100) __
tAC(O)-
CE
@
-TSPCAN
CHANGE
en )(
ADDRESS CAN CHANGE
~
- - - - TCE(3DO)
/
CD
\
-
V
--- tCC(130)--
V0
~V
CHANGE 1\
J
tCD(250)
~
~
tACC(210)
Refresh Cycle
..
VIH
ADDRESS )
CAN
CHANGE
K
I--tCF(O)
Soe to +lS0oe
-O.3V to +25V
Operating Temperature Range
Storage Temperature
All Input or Output Voltages with Respect
to the Most Negative Supply Voltage, V BB
Supply Voltages Voo and Vss with
Respect to V BB
Power Dissipation
-o.3V to +20V
1.0W
dc electrical characteristics
TA = oOe to +7ooe, Voo = +12V ±5%, VBe (Note 2) = -SV ±S%, Vss = OV, unless otherwise noted
PARAMETER
SYMBOL
Input Load Current
ILl
CONDITIONS
VIN
=OV
MIN
TYP(;J)
MAX
0.01
10
IlA
to V 1H max, (All Inputs
UNITS
Except CE)
I LC
Input Load Current
VIN "" OV to V 1HC max
0,01
10
IlA
I LO
Output Leakage Current Up
For High Impedance State
CE = VILe, Vo = OV to 5.25V
0.01
10
IlA
Voo Supply Current During
CE = -IV to +0.6V, (Note 4)
110
IlA
CE = V IHe • TA = 25'C
20
mA
35
mA
1001
CE "OFF"
V 00 Supply Current During
1002
CE"ON"
100 AVl
Average Veo Current
T A = 25°C, Cycle Time = 400 ns, tCE·= 230 ns
Ico
Average Voo Current
TA
AV2
I ••
V B6 Supply Current Average
V IL
Input Low Voltage
V IH
Input High Vol tage
VILe
CE Input Low Voltage
V 1HC
CElnput High Voltage
VOL
= 25°C. Cycle Time = 1000 ns,
tCE
= 230 ns
mA
15
100
5
tT = 20 ns. (Figure 4)
IlA
0.6
-1.0
V
Vec +l
2.4
V
V
1.0
-1.0
V
= 2.0 rnA
Output Low Voltage
IOL
Output High Voltage
IOH = -2.0 mA
V
0.45
0.0
,
V OH
V
2.4
Note 1: Absolute Maximum Ratings" are those. values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Chara~eristics"
provides conditions for actual device operation.
Note 2: The only requirement for the sequence of applying voltage to the device is that VDD or VSS should never be 0.3V more negative than
II
VBB·
Note 3: Tvpical values are for T A = 25° C and nominal power supply voltages.
Note 4: The I~D current is to VSS. The IBB current is the sum of all leakage currents.
ac electrical characteristics
SYMBOL
I
TA = oOeto +7oo e, Voo
PARAMETER
= 12V ±S%, VBB
CONDITIONS
= -SV ±S%
I
MIN
I
TYP
I MAX I
UNITS
READ, WRITE, READ/MODIFYIWRITE, AND REFRESH CYCLE
2
Time Between Refresh
tcc
ms
o
ns
Address Hold Time
50
ns
CE "OFF" Time
130
CE Transition Time
10
CE "OFF" to Output High
o
ns
TRI·SHARE Port to CE Set·Up
Time
o
'TIS
TRI·SHARE Port Hold Time
50
Address to CE Set·Up Time
tAc is MeasuredFrom End of Address Transition
ns
40
ns
Impedance State
READ CYCLE
tCY
~cleTime
tCE
CE "ON" Time
tT
CE Output Delay
Address to Output Access
ns
400
:= 20 ns
CL~AD = 50 pF, Load = One TTL Gate
Ref 1 = 2.0V, Ref 0
230
= 0.8V
1·34
ns
180
ns
200
o
CE to TSP
3000
n$
ns
3:
3:
U'I
N
.....
o
switching. time waveforms
Read Cycle
ADDRESS
CAN
CHANGE
V'He
CE
o
V,H
TSP CAN
CHANGE
TSP
VOH
Dour
-
- - -
VOL'
-
- -
HIGH IMPEDANCE
HIGH IMPEDANCE
Refresh Cycle
V,H
ADDRESS
V,l
--
ADDRESS
CAN
CHANGE
DC Electrical Characteristics
TA = oDe to +70o e, VOO = 12V ±5%, VBB (Note 4) = -5V ±5%, VSS = OV, unless otherwise noted.
SYMSiX
III
PARAMETER
I nput Leakage
Output Leakage for High
ILO
I mpedance State
VOO Supply Current Ouring
1001
CE OFF
VOO Supply Current Ouring
1002
CEON
CONDITIONS
MIN
. VBB = -5V, VIN =OV to'VIH Max,
TYP(Z)
MAX
UNITS
0.01
10
p.A
CE = VI LC, VOUT = OV to 5.25V
0.01
10
p.A
CE = -lV to 0.6V
100
p.A
CE = VIHC
10
mA
Pins Not Under Test = OV
MM5270A
37
45
MM5270A-12
40
50
MM5270A·l0
44
56
Average VOO Current
Tcy=AOOns, Min tCE and IT,(Note 3)
24
32
mA
IOOAV3
Average VOO Current
TCY = 1000 ns, Min tCE and tT, (Note 3)
10
13
rnA
IBB
Average VBS Current
5
100
pA
VIL
Input Low Voltage
(Note 4)
-1.0
VIH
Input High Voltage
(Note 4)
2.4
VILC
CE Input Low Voltage
(Note 4)
VIHC
CE Input High Voltage
(NOte 4)
VOL
Output Low Voltage
IOL= 2 mA, (Note 4)
0.0
0.45
V
VOH
Output High Voltage
IOH = -2 mA, (Note 4)
2.4
VCC
V
100AVl
100AV2
Average VooCurrent
Minimum Cycle Timing,
(Note 3)
0.6
rnA
V
VCC+l
V
-1.0
1.0
V
VOO-l
VOO+1
V
Note 1: '''Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to' imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Typical values are at 25°C, tv'pical 'power,supply voltage.
Note 3: The equation for defining 'DD(AVEI is:
(MaxIIDD(AVE)
~
CCE
+ tT
-.- -) 15.0+ (.1
- -) 10.0 x 103
TCY
TCY
where teE, tT and TCY are expressed in nanoseconds.and the resultant 'OO(AVE} is expressed in milliamps.
Note 4: 'All voltages referenced to VSS. When applying voltages to the device, VOO or VSS'should never be O.3V more negative than VSS.
I
I
I
,
,
1·39
..
AC Electrical Characteristics
TA= o°c to +70°C, VDD = 12 ±5%, VBB = -5 ±5% (Note 4), VSS = 0, t"f = 10 ns
PARAMETER
SYMBOL
CONDITIONS
MM5270A-10
MIN
MAX
MM5270A-12
MIN
MAX
MM5270A
MIN I MAX
UNITS
COMMON TO ALL CYCLES
tREF
Time Between Refresh
tAC
Address to CE Set-Up
(Note 5)
2
2
0
2
ms
0
0
ms
Time
tAH
Address Hold Time
40
40
40
ns
TCC
CE OFF Time
80
90
100
ns
t"f
(Note 6)
CE Transition Time
5
40
10
40
10
40
ns
tCF
CE OFF to Open Output
0
0
0
ns
t"fc
TSP to CE Set-Up Time
0
0
0
ns
tTH
TSP Hold Time
40
40
40
ns
READ CYCLE
tCY
Cycle Time
210
tCE
CEON Time
110
245
tco
CE to Output Access
(Note 7)
90
tACC
Address to Output
(Notes 7 and 8)
100
3000
280
3000
135
ns
3000
ns
115
140
ns
125
150
ns
160
Access
"
tTL
CE toTSP
0
0
0
ns
Note 5: For Refresh Cycle, Rowand Column Addresses must be stable before tAC and remain stable for entire tAH period_
Nota 6: For test purpose, input levels should swing between OV and 3V. VIH(MINI and VI L(MAXI are reference levels for measuring transition
times and timing of input signals.
Note 7: VOH =VSS + 2.0V and VOL =Vss + O.SV are the reference levels for measuring timing of teo and tACC.
Nota 8: tACC =tco ±tT + tACo For test purposes tT = IOns.
Switching Time Waveforms
Read Cycle
~
ADDRESS •
'AC- I--
...
'K"
-V-'T
CE
'rc,-
'1-
r-
1
I'lL
~
TSP~ ~
i---'Cf -
'CO
°iiUl
r-
~-
---- -----~~----~----~
,·M.-
1-40
VALID
Jr----------\
OPEN
AC Electrical Characteristics
TA'=
o°c to +70°C, Voo
~ 12
±5%, VBB
~
PARAMETER
SYMBOL
(Continued)
-5±5%, (Note 4). VSS ~O, tT
CONDITIONS
~ 10 ns
MM5270A-10
MM5270A-12
MIN
MIN
MAX
MAX
MM5270A
MIN
MAX
UNITS
WRITE AND READ·WHILE·WRITE CYCLE
tCY
Cycle Time
210
tCE
CE ON Time
110
tw
TSPtoCEOFF
30
40
50
ns
twp
TSP Pulse Width
30
40
50
ns
to
DIN to CE OFF Set·Up Time
30
40
50
ns
tOH
DIN Hold Time
0
0
0
ns
240
285
330
ns
245
3000
135
ns
280
3000
160
3000
ns
READ·MODIFY·WRITE CYCLE
TRWC
Read·Modify·Write Cycle
(Note 9)
Time
TCRW
Read·Modify·Write CE ON
140
3000
175
3000
3000
210
ns
Time
twP
TSP Pulse Width
30
40
50
ns
tw
TSP to CE OFF
30
40
50
ns
to
DIN
30
40
50
ns
tOH
DIN Hold Time
0
0
0
ns
tco
CEto Output Access
(Note 7)
90
115
140
ns
tACC
Address to Output Access
(Notes 7 and 8)
100
125
150
ns
two
TSP to Open Output
40
ns
to CE OFF Set·Up Time
10
30
10
30
10
REFRESH CYCLE
245
ns
tCY
Cycle Time
210
tCE
CE ON Time
110
tcc
CE OFF Time
80
90
100
ns
tAC
Address to CE Set·Up
0
0
0
ns
40
40
10
10
3000
135
280
3000
160
3000
ns
Time
tAH
Address Hold Time
tT
CE Transition Time
Capacitance (Note 10)
SYMBOL
40
(Note 6)
5
40
40
ns
40
ns
T A ~ 25°C
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2
pF
15
pF
VOUT=OV
5
pF
VIN= VSS
4
pF
= VSS
CAD
Addres,s Capacitance, CS
VIN
CCE
CE Capacitance
VIN~
COUT
Data Output Capacitance
CIN
01 N and WE Capacitance
VSS
Note 9: For minimum cycle time, tM = 10 os.
Note lQ: Capacitance measured with Boonton Meter or effective capacitance calculated from the equation C =
equal to a constant 20 rnA.
1-41
lL1t/~V
with the CUrrent
Switching Time Waveforms
(Continued)
Write Cycle
ADDRESS
CE
TSP
liD
·"~
~
I
OPEN
~-------------------------------------Read-Modify-Write Cycle (Note. 9 and 10)
ADDRESS
'AC
CE
TSP
"~i!
[.,.
DI!UT _ _ _ _
OPEN
Refresh Cycle (Note 5)
ADDRESS
CE
OPEN
00lrf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - : - - - - - - -
Block Diagram
MEMORY INVERTS DATA
TSP ffil
I
r
cs
LATCH
ATI'(4)
ATO(3)
A9,l2)
A8(11)
Al (16)
A6(15)
AS (12)
A4.(111
A100l
A2(!)
AI (8)
ADm
MEMORY
ARRAY'
4096 BITS
D
VOD (14) - - +T2V
Vss fl'8) _ . - DV
V8S{1l - - -5V
1-43
~National
MOS RAMs
~ Semiconductor
MMS270-S TRI-SHARETM4096-bit random access read/write memory
general description
features
The MM5270·5 is a slower speed version of National's
MM5270 dynamic RAM. Please refer to the MM5270
specification for pin configuration, block diagram and
switching time waveforms.
• Access time-270 ns
• Cycle time-470 ns
absolute maximum ratings
(Note 1)
Order Number MM5270D·5
O°C to +70°C
-u5 C to +150°C
-0.3V to +25V
Operating Temperature Range
Storage Temperature
All Input or Output Voltages with Respect
to the Most Negative Supply Voltage, V SB
Supply Voltages V DD and Vss with
Respect to V BB
Power Dissipation
See Package 4
Q
-0.3V to +20V
1.0W
dc electrical characteristics
TA = o°c to +70°C, Voo = +12V ±5%, VSB (Note 2) = -5V ±5%, Vss = OV, unless otherwise noted
SYMBOL
ILl
PARAMETER
Input Load Current
CONDITIONS
MIN
TYP (3)
0.01
VIN "" OV to V 1H max, (All Inputs
MAX
UNITS
10
p.A
Except CE)
ILe
Input Load Current
VIN "" OV 'to V 1HC max
0.01
10
p.A
IILOI
Output Leakage Current, Up
CE = V'Le, Va = OV to 5.25V
0.01
10
p.A
CE = -lV to +0.6V, (Note 4)
110
p.A
20
rnA
35
mA
For High Impedance State
1001
Voo Supply Current During
CE "OFF"
IOD2
Voo Supply Current During
CE "ON"
100 AV1
Average Voo Current
T A ,.,. 25-'C, Cycle Tune
100 AV2
Average Voo Current
T A '" 25'~C. Cycle Time == 1000 ns, teE = 300 ns
IBB
V BS Supply Current Average
V'L
Input Low Voltage
V ,H
Input High Voltage
VILe
CE Input Low Voltage
==
470 ns, teE
=;
300 ns
5
tT :::
20 ns
mA
15
-1.0
100
p.A
0.6
V
1.0
V
V
2.4
-1.0
VOD~1
V 1HC
CE Input High Voltage
VOL
Output Low Voltage
IOL =2.0 mA
0.0
V OH
Output High Voltage
IOH "" -2.0 rnA
2.4
V
0.45
V
V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operat.ing
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: The only requirement for the sequence of applying voltage to the device is that VOO or VSS should never be O.3V more negative than
VSB'
Note 3: Typical values are for T A = 2SoC and nominal power supply voltages.
Note 4; The 11)0 current is to VSS. The ISS current is the sum of all leakage CUrrents.
1·44
ac electrical characteristics
TA
= o°c to +70~C, V DO = 12V ±5%, V ss = -5V ±5%
SYMBOL
CONOITIONS
PARAMETER
TY?
MIN
MAX
UNITS
READ, WRITE, READ/MODIFY/WRITE, AND REFRESH CYCLE
tREF
Time Between Refresh
tAc
Address to CE Set-Up Time
tAH
2
ms
0
ns
Address Hold Time
50
ns
tcc
CE "OFF" Time
130
tT
CE Transition Time
10
tCF
CE "OFF" to Output High
0
ns
0
-ns
80
ns
t AC is MeasuredFrom End of Address Transition
ns
40
ns
lmpedance State
tTc
TRI·SHARE Port to CE Set·l1p
Time
tTH
TR I-SHARE Port Hold Time
READ CYCLE
tCY
Cycle Time
tCE
CE "ON" Time
tT
=- 20
470
ns
ns
300
3000
os
C LOAD =- 50 pF. Load::::; One TTL Gate
tco
CE Output Delay
tAce
Address to Output Access
tTL
CE to TSP
0
tCY
Cycle Time
470
tCE
CE "ON" Time
300
tw ,
TSP to CE "OFF"
150
tcw
CE to TSP
tD
D'N to CE "OFF"
150
os
tOH
D1i\] Hold Time
0
os
twp
TS? Pulse Width
50
os
650
os
Ref 1 = 2.0V, Ref 0
tAct ~ t AC
= 0.8V
250
ns
270
os
+ teo + tT
os
WRITE CYCLE
os
3000
os
20 ns
tT ==
os
115
os
READ/MODIFY/WRITE CYCLE
t RWC
Read Modify Write (RMW)
Cycfe Time
Durin~
3000
480
RMW
os
tCRW
CE Width
twc
TSP to CE "ON"
tT ::.
t";2
TSP to CE "OFF"
C LOAD
twp
TSP Pulse Width
Ref 1 2.aV, Ref a
tD
DIN
tOH
DIN Hold Time
tco
CE to Output DelC1Y
180
tAce
Access Time
270
ns
two
TSP to Output Hiqh Impedance
250
os
tM
Modify Time
to CE "OFF"
20 ns
tAce
:=
=
50 pF, LOdd "" One TT L Gate
t AC
= a.BV
+ tco +
tT
0
os
200
os
50
os
150
os
0
os
0
ns
os
CAPACITANCE (Note 11
I
C AO
Address Capaclt;lnCe, CS
V IN "" Vss
2
pF
CeE
CE Capacitance
V 1N
15
pF
CI/O
Data 110 Capacitance
V OUT
==
B
pF
C IN
TSP Capacltarlce
V'N
Vss
5
pF
-~
-'=
Vss
OV
Note 1: Capacitance measured with Boonton Meter.or effective capacItance calculated fror:n the equation C
constant 20 rnA.
1-45
=:
IAt/.a.V with the current equal to a
o
MOS RAMs
~National
~ Semiconductor
MM5271 TRI-SHARETM4096-bit fully TTL compatible
dynamic random access read/write memory
general description
The MM5271 is a fully TTL compatible 4096-bit dynamic
random access memory with TRI-SHARE. Because of
this unique design feature, National is able to house a
4k device in an 18-pin dual-in-line package. The device
is manufactured using N·channel silicon gate technology
with a single transistor cell which provides higher density
on a monolithic chip and thus lower cost.
write, the TSP must be pu Ised low after the minimum
hold time and the appropriate data placed on the I/O.
When the MM5271 goes into write, the output circuit is
disabled. If the TSP is low at the start of the cycle, the
memory is not selected but it will be refreshed when the
chip enable clock is pulsed.
The TRI-SHARE Port (TSP) is a multifunction input
that, along with a common input/output, allows National
to manufacture an 18-pin version of a 4k RAM. The
functions controlled by the TSP are read/write, Vee,
and logical chip select. In orde.r to. understand how the
TSP works, consider the timing diagrams. The state of
the TSP at the leading edge of the chip enable clock
determines whether the device is selected. If it is at a
TTL high level, the chip is selected and the device goes
into a read mode after chip enable goes high. This high
level also controls the Vee function in that it enables
a reference voltage for a TTL high output. The supply
for the output buffer is V aa , not the TRI-SHARE Port;
thus, no special driver is required. In order to perform a
features
• 4096 x 1 bit organization
• Access time 250 ns maximum
• Cycle time 400 ns minimum
• TRI-SHARE port
• High memo;y density-18-pin package
• TTL compatible inputs
• TRI-STATE® common input/output
• Registers on chip for addresses and chip select
• Two power supplies, +12V, -5V
• Simple read-modify-write operation
block and connection diagrams
r-------------------------------------~CO:~OL
TSP(51
Dual-In-Line Package
os
LATCH
CHil'
Vss
All (4)
AS
I"
Al0(3)
17
A1
,.
A6
15
VDD
ENAIt'E
"
A!i
Il
12
A9(2)
A4
A3
"
"
AS (171
A7 (16)
A6\1Sj
Mit2'1
r-
A4111l
l-
Al(10j
A2(9)
AlIB)
AO(7)
2
I
Vu
A9
,
AlO
• , •
AU
TSP
I/O
1
AO
TQPVIEW
CE(ll)
Order Number MM52710
See Package 4
VI)\) (14) - - +12V
Vss (1Bl--OV
VBs (11---5V
Pin Names
AO--A11
Address Inputs'
V BB
Power (-5VI
CE
Chip Enable
V DO
Power (+12V)
TSP
TRI-SHARE Port
Vss
Ground
I/O
D'N/DoUT
"'Refresh Addess AO-AS
1-46
,
AI
I'
A2
absolute maximum ratings
(Note 1)
O°C to +70°C
..,u5°e to +150 o e
-O.3V to +25V
Operating Temperature Range
Storage Temperature
All Input or Output Voltages with Respect
to the Most Negative Supply Voltage, VBB
Supply Voltages VDDand Vss with
Respect to V BB
Power Dissipation
-O.3V to +20V
1.0W
dc electrical characteristics
TA
oOe to +70°C, VDD = +12V ±5%, VSB (Note 2) : -5V ±5%, Vss = OV, unless otherwise noted
:
SYMBOL
PARAMETER
CONDITIONS
III
Input Load Current
V 1N
tlLOI
Output Leakage Current Up
a
MIN
OV to'Vn-j max
=
= V'H' Va = OV to 5.25V
TYP (3)
MAX
0.Q1
10
J1A
0,01
10
pA
UNITS
For High Impedance State
1001
1002
AVl
1
mA
20
mA
35
mA
"OFF"
V DO Supply Current During
a
I DO
a.= V'H' INote4)
Voo Supply Current During
a
CE
= V;l' T A
TA
::
==
2SOC
"ON"
Average
VOD
Current
25°C, Cycle Time
100 AV2
Average V DO Current
I BS
V B8 Supply Current Average
V'L
Input Low Voltage
V'H
Input High Voltage
VOL
Output Low Voltage
10l :::
VO H
Output High Voltage
IOH =- -2.0 mA
==
400 ns, tee::: 240 ns
T A = 2Soc, Cycle Time = 1000 ns, tee
==
240 ns
tT = 10 ns', (Figure 4)
mA
15
5
100
J1A
0.6
-1.0
V
2.4
V
0.45
0.0
2.0 mA
V
2.4
V
Notel: "Absolute, Maximum Ratings" are those value's beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not, meant to imply that the devices should be operated at these limits. The table ,of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2; The only req~irement' for the sequence of applying voltage to the device is that VOD or VSS should never be O.3V more negative than
Vss·
Note' 3: Typical values are for T A = 25°C and nominal power supply voltages'.
Not8 4; The 'DO current is to VSS. The ISB-current is the sum of all leakage currents.
ac electrical characteristics
SYMBOL
TA
:
oOe to +70 o e, V DD : 12V ±5%,V BS
PARAMETER
CONDITIONS
:
-5V ±5%
MIN
TYP
MAX
UNITS
READ. WRITE, READ/MODIFYIWRITE, ANDREFRESH CYCLE
Time Between 'Refresh
Address to
tcc
ms
CE Set· Up Time
t AC
is MeasuredFrom End of Address Transition
o
100
ns
a."OFF" Time
140
ns·
CE Transition Time
tCF
ns
Address Hold Time
a
40
"OFF" to Output High
50
ns
o
'flS
Impedance State
TR.I·SHARE Port to a
Set-Up
Time
TRI·SHARE Port Hold Time
ns
100
READ ItYCLE
tCY
Cycle Time
tCE
a
teo
CE Output Delay
tT :::
400
10 ns
"ON" Time
Address to Output Access
CLOAD =50 pF.Load = One TTL Gate
Ret 1
240
=2.0V, Ret 0 = 0.8V
o
CE to TSP
1-47
ns
3000
ns
250
ns
250
ns
ns
0
~
N
It)
switching time wave f orms
:E
:E
Read Cycle
Tcy (4001
I--'AH (1001-
V,H
ADDRESS
VIL
ADDRESS )
CAN
CHANGE
Q)
Q)
0
0;
K
ADDRESS CAN CHANGE
t-- 'T(101
TCE (2401
tAC (01_
V,H
Q)'\
CHIP ENABLE
VIL
--j
V,H
TSP
V,L
VOH
-
VOL
I-'T (101
l@
i--Icc (1401_
'TC (01 I -
TSPCA~/ ICD
~
CHANGE
CHANGE
-
- -- -----
teo (2501
). k.®0
HIGH IMPEDANCE
DOUT
-
--- -----
=r
'ACC (2501
'TL (01
-----
HIGH IMPEDANCE
-----
I-tcF (50)
Refresh CYcle (Se. Note 1)
~----------------Tcy(~OII----------------~
V,H
ADDRESS
V'L
ADDRESS
CAN
CHANGE
'AC (01
V,H
CHIP ENABLE
V,L
'TC (01
V,H
TSP CAN
CHANGE
TSP
V,L
VOH--
HIGH IMPEDANCE
~------------------Notl! 1: For Refresh cycle. row and totumn addrla'sses mus1 be stable before lAC and remain stable for
entire tAH period.
Note 2: V1l. MAX is the reference leyel for measuring timing of the addresses, Tsp and DIN and CE.
Note 3: VIH M1N is the reference level for measuring timing of the addresses, Tsp and DIN and CE.
Note 4: Vss + 2.0V is the reference level for measuring the timing of Dour for a high output.
Note 5: Vss + O.BV is the reference levei for measuring timing of DouT for a low output.
1-48
ac electrical characteristics (con't)
SYMBOL
TA =
PARAMETER
oOc to +70°C,V oo
= 12V ±5%, VeB' = -'5V ±5%
CONDITIONS
MIN
TYP
MAX
UNITS
WRITE CYCLE
:tCY
Cycle Time
400
tCE
CE 1'ON" Time
240
tw ,
TSP to CE "OFF"
100
tcw
CE to TSP
to
D'N to
tOH
twp
-
tT
=;
10 ns, {Note 4)
ns
3000
130
IT "OFF"
os
ns
OS
70
os
DIN Hold Time
50
ns
TSP Pulse Width
50
ns
switching time waveforms (con't)
Write Cycle
D
is•• Note 4)
Tev (400)
-"H(100)V'H
~ CD
CD
ADDRESS
V'L
-
V'H
V"
TSP
V"
I
.TeIO)1
TSP
CAN,
CHANGE
ADDRESS CAN CHANGE
teE 1240)
'AC 10)
CD\
CHIP ENABLE
V'H
CD
CD
1\
CD
--tCW/MAX)
/
(130)---
1\\
1-
ITH
r'
wp
'"
[
I~O)r
V TS~
D'N CAN CHANGE
tee 1140)
~
+N CHANGE
-N
1100)-
V'H
D'N
--tT (10)
I--'Tll0) ~'Wl(100)-
D'N SThBLE
__ tDH
(50)
D'N CAN CHANGE
I
V"
- -- - - - - --'0170)
VOH~--------
1-
HIGH IMPEDANCE
Dour
VOl-------~
--.----- ----
\
Note 1: Fat Refresh cycle, row and column addresses must be stable before tAC and remain stable for
entire t.AH period.
Note 2: V1l MAX is the reference illYel for me and DIN and CE.
Note 4: If tC'INIMAX) is greater than 130 'ns then memory operation is like Read/ModifylWrite cycle.
1-49
:l
- -
ac electrical characteristics (can't)
SYMBOL
TA =O°Cto +70°C, Voo = 12V±5%, V BB =-5V±5%
UNITS
CONDITIONS
PARAMETER
READ/MODIFY/WRITE CYCLE
Re'-ad Modify Write (RMW)
tAWC
560
ns
Cycle Time
tCRw
CE W;dth
tW2
TSP to
twp
TSP Pulse Width
tD
D'N to
tDH
DIN Hold Time
tco
CE to Output Delay
250
ns
tAce
Access Time
250
ns
tWD
TSP to Output High Impedance
50
ns
tM
Modify Time
Dur;ng RMW
CE
CE
400
tT"'" 10 ns
~
C LOAD
"OFF"
50 pF, Load
Ref 1 ~ 2.0V, Ref 0"
=:
One TTL Gate
oav
tAce ';: t AC + teo
"OFF"
3000
ns
150
ns
50
ns
70
ns
50
ns
-
a
ns
CAPACITANCE INot. 1)
CAD
Address Capacitance. CS
V'N - Vss
2
C CE
CE Capacitance
V 1N
5
pF
CliO
Data 1/0 Capacitance
V OUT
=:
8
pF
C'N
TSP Capacitance
Y'N
Vss
5
pF
""
;-;0
Vss
ov
pF
Note 1: Capacitance measured with Boonton Meter or effective capacitance calculated from the equation C = l6.t/.6. V with the current equal to a
constant 20 mAo
switching time waveforms (can't)
Read Modify Write Cycle
I----------TR"" ( 5 6 0 ) - - - - - - - - - 1
V,H
ADDRESS
V"
ADDRESS
CAN
CHANGE
ADDRESS CAN CHANGE
tT
110)
V,H
CHIP ENABLE
V,I..tT
lID)
V,H
TSP
V"
V,H
D,N
D'N CAN CHANGE
V,L
"of
1-=,--+---------["=-+----------
Vo ... -~-
HIGH IMPEDANCE
DOUT
V OL - - -
tAce (250)
Note 1: For Refresh cycle, row and column addresses must be stable before
tAC
and remain stable for
entire tAH period.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
V1L MAX is the reference level for measuring timing of the addresses, Tsp and DIN and tE.
V1H MIN is the reference level/for measuring timing of the addresSes. TSf' and DIN and CE.
Vss + 2.0V is the reference level for measuring the timing of DouT for a high output.
Vss + O.BV is the referencedevel for measuring timing of DouT for a low output.
For minimum cycle, tM '" 0, for test purposes ~ = 10 os.
If DIN is forrred prior to DouT becoming high impedance (twDtMAX'), then maximum
ambient temperature should be derated by TovfTCYCLE (3S"'C). Where Tov is time
between forcing DIN and DouTbecoming TRI-STATE.
1-50
~National
~. Semiconductor
MOSRAMs
MM5271 A TRI-SHARETM 4.Q96-Bit Fully TTL Compatible
Dynamic Random Access Read/Write Memory
General Description
The MM5271A is a 4096-bit dynamic randOm access
memory with TRI-SHARE. Because of this unique
design feature, National. is able to package a 4k device
in an l8·pin dual·in·line package. The device is manu·
factured using N-channel silicon gate technology with a
single transistor cell Which provides higher densitY on a
monolithic chip and thus lower cost.
start of the cycle, the memory is not selected, but it
will be refreshed if the chip enable clock. is pulsed.
The RAM must be refreshed every 2 ms. This can be
accomplished by performing a cycle at each of the 64
row addresses (AO-A5).
Addresses (A6-A 11) must have a stable address during
the refresh cycle. Any address is satisfactory as long as
the address set·up and hold times are met. The chip
select input can be either high or low for refresh.
The TRI·SHARE Port (TSP) is a multifunction input
that, along with a common input/output,allows National
to manufacture an. 18'pin version of a4k RAM. The
functions controlled by the TSP are read, write,
and logical chip select. In order to understand how the
TSP works, consider the timing diagrams. The state of
the TSP at the leading edge of the chip enable clock
determines whether the device is selected. If it is at a
TTL high level, the chip is selected and the device goes
into a read mode after chip enable goes high. This high
level also enables a reference voltage for a TTL high
output. The supply for the output buffer is V oo , nOt
the lR I-SHARE· Port; thus, no special driver is required.
In order to perform a write, the TSP must be pulsed low
after the. minimum hold. time and the appropriate data
placed on the I/O. When the MM527.1A goes into write,
the output circuit is disabled. If the TSP is lowat the
Features
• 4096 x 1 bit organization
• Access time-115 ns max MM5271 A·1
140 ns max MM5271 A
• Cycle time'-215 ns min MM5271A1
260 ns min MM5271A
• TRI·SHARE port
• High memory density-18'pin package
• All pins TTL compatible
• TRI-STATE® common input/output
• Registers on chip for addresses and chip select
• Two power supplies, +12V, -5V
• Simple read·modify·write operation
Connection Diagram
Block Diagram
MEMORY INVERTS DATA
Dual-I n-l ine Package
...--.,.,---.,---.,-------'-'-----ICO~:Ol
1B
1SP (5)
Order Number MM5271AD
See Package 4
Order Number MM5271AJ
See Package lOA
Order Number MM5271AN
Se. Package 16
All (4)
A111(3)
1.912)
AllIIn
Al\l6/
A!i1l21
"'-_-:-_..-!COlUMNDfC.OOEA(t-641
A.111I
,..-
no)
A21!}
~.,--;7ij'I
Ifij~
AIO
16 A1
All
15
voo
13
1/0
1/0
SENSE AMPLIFIERS!64}
Afllm
AI
11 A4
A2
"
MEMORV
ARRAV
TOP VIEW
40!16111TS
Logic Symbol
,......,----'---'---,
V$II.I1'I--
A'
AI
ov
A2
VIIII !1l _ _ ·_SY
.3
••
Pin Names
AS
Dl/D
AS
Address'lnputs
Vee
Power (-5VJ
A7
CE
Chip Enable
Voo
Power (+12VI
TSP
TRI·SHARE Port
Vss
Ground
.,
ilO
PIN/OoUT
·AO.-Al1
A.
AI'
All
"Row address AO-A5
1·51
a
12 A!i
1.1111
VCJDI1.tI--·UV
A6
14
~(6)
Cf (,1l)
V~
T1 A8
TSP
AiUSI
Al
v"
..
TSP
A3
Absolute Maximum Ratings
Operating Temperature Range
Storage Temperature
Power Dissipation
(Note 1)
DC Electrical Characteristics
SYMBOL
T A = oOc to +70°C,
PARAMETER
I nput Leakage
III
Output Leakage for High
ILO
-0.3V to +20V
Voltage on Any Pin Relative to VBB
(VSS - VSS :-,. 4.5V)
Lead Temperature (Soldering, 10 seconds)
300°C
O°Cto +70°C
-65°C to +150°C
1.0W
Impedance State
voo =
12 ±5%, VSS = -5 ±5% (Note 4), VSS = 0
TYP(2)
MIN
CONDITIONS
VSS = -5V, VIN = OV to VIH Max, Pins
During CE OFF
VOO Supply Current
1002
During CE ON
UNITS
0.01
10
pA
CE = VIH, VOUT = OV to 5.25V
0.Q1
10
pA
CE = VIH
1
mA
CE-=VIL
10
mA
Not Under Test = OV
VOO Supply Current
1001
MAX
Minimum Cycle Timing,
I MM5271A
I MM5271A-l
36
45
42
55
mA
mA
24
32
mA
10
13
mA
5
100
pA
IOOAVl
Average VOO Current
IOOAV2
Average VOO Current
TCY = 400 ns, Min tCE and t" (Note 3)
IOOAV3
Average VOO Current
TCY = 1000 ns, Min tCE and
IBB
Average VSB Current
VIL
Input Low Voltage
(Note 4)
-1.0
0.6
V
VIH
Input High Voltage
(Note 4)
2.4
VCC+1
V
VOL
Output Low Voltage
IOL = 2 mA, (Note 4)
0.0
0.45
VOH
Output High Voltage
IOH = -2 mA, (Note 4)
2.4
(Note 3)
AC Electrical Characteristics
SYMBOL
PARAMETER
T A = o°c to +70°C,
CONDITIONS
r., (Note 3)
voo = 12 ±5%, VBS = -5 ±5%
MM5271A
MIN
MAX
V
V
(Note 4), VSS = 0
MM5271A-1
MIN
MAX
UNITS
COMMON TO ALL CYCLES
tREF
Time Between Refresh
tAC
Address to CE Set-Up Time
(Note 5)
2
2
-15
ms
-15
ns
tAH
Address Hold Time
70
70
ns
tcc
CE OFF Time
100
BO
ns
r.
Transition Time
tCF
CE OFF to Open Output
tTC
TSP to CE Set-Up Time
tTH
TSP Hold Time
(Note 6)
3
50
3
35
ns
25
25
ns
-15
-15
ns
70
70
ns
260
215
ns
READ CYCLE
TCY
Cycle Time
tCE
CE ON Time
tco
CE Output
~elay
tACC
Address to Output Access
tTL
CE toTSP
150
(Note 7)
3000
125
150
(Notes 7, 8)
140
0
1-52
0
3000
ns
125
ns
115
ns
ns
AC Electrical Characteristics
s:
s:
U1
(Continued)
TA = O~C to+70°C, VOO = 12±5%, VBB = -5±5%, (Note 4), VSS= 0
~
....
~
SYMBOL
CONDITIONS
PARAMETER
UNITS
»
WRITE CYCLE
TCY
Cycle Time
260
tCE
CE ONTime
150
tw
TSPto CE OFF
40
30
ns
twp
TSP Pulse Width
40
30
ns
to
01 N to CE OFF Set-Up Time
0
0
ns
tOH
DIN Hold Time
40
two
TSP to Open Output
10
CHIPENABLE
TSP
DIN
{
OPEN
OPEN
'-53
3000
10
ns
ns
30
ns
0
Write Cycle
_
125
ns
30
Read Cycle
DOUT-----
3000
40
Switching Time Waveforms
1/0
215
AC Electrical Characteristics
(Continued)
TA; o°c to +70°C, Voo; 12 ±5%, VBB; -5 ±5% (Note 4). VSS; 0
SYMBOL
MM5271A
CONDITIONS,
PARAMETER
MIN
MM5271A-l
MAX
MIN
MAX
UNITS
READ-MODIFY-WRITE CYCLE
(Note 9)
TRWC
Read-Modify-Write Cycle Time
TCRW
CE ON Time in RMW Cycle
195
tw
TSP to CE OFF
40
twP
TSP Pulse Width
tD
DIN to CE OFF Set-UpTime
tDH
DIN Hold Time
40
30
10
305
250
3000
ns
160
3000
ns
30
os
40
30
ns
0
0
ns
ns
twD
TSP to Open Output
tco
CE Output Delay
(Note 7)
150
125
ns
tACC
Address to Output Access
(Notes 7,8)
140
115
os
Switching Time Waveforms
40
10
30
os
(Continued)
Read-Modify-Write Cycle (Note' 0)
tAC _ _
'AWC
1+'
AOOAESS~
tT
~ -'C""
-
-+--
---
CHIP ENABLE
tTC
--'1
f---
tT~1
TSP~
I/O
{
'''~
,-
l-tT
L
-~P1 I--
--
~
~
I~- ~tOH
r3i~W;,OCVALIOOATA~~
-'I~
two
OPEN
° O U T - - - ~--'------1
~tACC·-
-------~--
VALID
DATA
"tAce := teo + t7 + tAC
1-54
AC Electrical Characteristics
(Continued)
TA; aOc to +7aOc, VDD; 12 ±5%, VBB ; -5 ±5% (Note
PARAMETER
SYMBOL
4), Vss; a
CONDITIONS
MM5271A
MIN
I
MM5271A·'
MAx
MIN
MAX
I
I
UNITS
REFRESH CYCLE
TCY
Cycle Time
260
tCE
CE ON Time
150
tcc
CE OFF Time
100
tAC
Address to CE Set·Up Time'
tAH
Address Hold Time
trc
TSP to CE Set·Up Time
trH
TSP Hold Time
Capacitance
SYMBOL
215
3000
125
ns
ns
3000
ao
ns
-15
-15
ns
70
70
ns
-15
-15
ns
70
70
ns
TA; 25°C, (Note 11)
MIN
CONDITIONS
PARAMETER
TYP
MAX
UNITS
VIN; VSS
2
pF
CE Capacitance
VIN = VSS
15
pF
ClIO
Data I/O Capacitance
VOUT= OV
8
pF
CIN
TSP Capacitance
VIN = VSS
5
pF
CAD
CCE
Address Capacitance, CS
Nota 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operati,ng Temperature Range" they are not meant to imply that the devices should be 'operated at these limits. The table of "·Electrical
Characteristics" provides conditions for actual device operation.
Nota 2: Typical values are at 25°C, typical power supply voltage.
Nota 3: The equation for defining IDD(AVE} .is:
100(AVE}
= .(tCE+tr)
- - - 15.0 + (_1_) 10.0x 103
TCY
TCY
where tCE, tr and TCY are expressed in nanoseconds and the resultant IDD(AVE} is expressed in milliamps.
Nota 4: All voltages referenced to VSS. When 'applying voltages to' the device VDD or VSS should never be 0.3V more negative than
Vaa·
Nota 5: For Re~resh Cycle, Rowand Column Addresses must be stable before tAC and remain stable for e~.tire tAH period.
Note 6: For test purpose, inputs levels should swing between OV and 3V VIH(MIN} and VIL(MAX} are reference levels for measuring
transition times and timing of input signals.
Note 7: VOH = Vss + 2Vand VOL = VSS + O.SV are the reference levels for measuring timing of tco and. tACC.
Nota 8: tACC = te~ + tr + tACo For test purposes tr = 5 ns.
Nota 9: For minimum cycle time, tMOO S 35 ns.
Note 10: If DIN is forced prior to 00UT becoming high impedance (twO(MAX}), then maximum ambient temperature should be
derated by (TOV/TCYCLE}(35"C), Where TOV is time between forcing DIN and DOUT becoming TRI-STATE®.
:Note 11: Capacitance measured with I!oonton Meter or effective capacitance calculated from the equation C ;oIAt!AV with the current
equal to a constant 20 mAo
Switching Time Waveforms
(Continued)
Rafresh Cycla (Note 5)
'AC_
--
I-'A~-I
,. -
ADDRESS Wff////;.?J
CHIP ENABLE
.Y
(-ze)
q"C-
TSP~
'" -
,)~lr'T(5}
(6}'T-
~
(801
:-
'--
~~---------~~-~-----~~1·55
o
~NaHonal
MOS RAMs
~ Semiconductor
MM4280 4096-bit dynamic random access read/write memory
with extended temperature range
general description
National'sMM4280 is a 4096 word by 1 bit dynamic
RAM. It incorporates the latest memory design features
and can be used in a wide variety of applications, from
those which require very high speed to ones where low
cost and large bit capacity are the prime criteria.
The single device cell, along with unique design features
in the on·chip peripheral circuits, yields a high perfor·
mance memory device.
features
The MM4280 must be refreshed every 1 ms. This can be
accomplished by performing a read cycle at each of the
64 row addresses (AO-A5). The chip select input can
be either high or low for refresh. Addresses (A6-A 11)
must have a stable address during the refresh cycle.
Any address is satisfactory as long as the address set-up
and hold times are met. The chip select input can be
either high or low for refresh.
•
•
•
•
•
The MM4280 has been designed with minimum produc·
tion costs as a prime criterion. It is fabricated using
N-channel silicon gate MOS technology, which is an ideal
choice for high density integrated circuits. The MM4280
uses a single transistor cell to minimize the device area.
•
•
•
•
Extended temperature range: _55°C to +85°C
Organization: 4096 x 1
Access time 270 ns maximum
Cycle time 470 ns minimum
Easy system interface
• One high voltage input-chip enable
• TTL compatible:"'all other inputs and outputs
Address registers on·chip
TRI,sTATE® output
Simple read-modify-write operation
Industry standard pin configuration
connection diagram
block diagram
Dual-In-Line Package
1ft:(12)---------------------ICO:~OL
22 Vss
VBB
i:!151
A9
A11141
A10
21 AI
"
All III
A9(Z)
19
AI1
A7
A6
AI (2t)
A712Dl
18 Vou
i:!
AI/l11l
A5(15)
11CE
DIN
A4(14)
rrm
A3(13)
AZUO)
16
.,
Alii)
AOIBI
14 ..
".,
A2 'O
Vee
CEIUI
11
"WI!
TOP VIEW
Otder Number MM4280D
See Package 5A
Vou (111-- +12V
VSS{221--0V
YBBt1l---·V
logic symbol
vcc l1 ll--,+5'11
Memory Inverts From Data In to Data Out
AD
Al
Pin Numbers
A'
A3
*
VBB
Power (-5VI
Chip Enable
VCC
Power (+5VI
Chip Select
VDD
Power (+12VI
D1N
Data Input
Ground
DDUT
NC
Data Output
Vss
WE
AO-All
Address Inputs
CE
Cs
Write Enable
Not Connected
* Refresh Address AO-A5
1-56
Ne
15 A5
AD
absolute maximum ratings
(Note 1)
-55"c to +85°C
-65°C to +150°C
...{l.3V to+20V
Operating Temperatu" Range
Storage Temperature
Voltege on any Pin Relative to Ves
(VSS - VSS ~ 4.5V)
Power Dissipation
1.25W
dc electrical characteristics
TA = -55°C to +85°e, Voo = 12V ±5%. Vee = 5V ±5%, vee (Note 2) = -5V ±IO%, vss = OV. unless otherwise noted.
PARAMETER
III
CONDITIONS
MIN
VIN = OV to VIH max. (All Inputs
. Except CE)
Input Load Current
=OV to VIHC max
= VILC or CS =VIH. Vo =OV to 5.25V
TVP
MAX
0.01
10
UNITS
IlA
ILC
Input Load Current
VIN
0.Q1
10
Il A
IILOI
Output Leakage Current Up For
CE
0.01
10
IlA
High Impedanee State
IDOl
VOO Supply Current During
CE "OFF"
CE" -IV to O.IIV. (Note 4)
110
200
IlA
1002
VOO Supply Current During
CE "ON"
CE = VIHC. TA = 25°C
20
50
mA
100AVI
Average VOO Current
Cycle Time" 470 ns. tCE = 300 ns
35
70
mA
ICCI
VCC Supply Current During
CE "OFF"
CE = VILC Or
0.Q1
10
IlA
lee
Vee Supply Current Average
5
100
IlA
VIL
Input Low Voltage
VIH
Input High Voltage
VILC
CE Input Low Voltage
CS" VIH (Note 5)
tT=20ns
-1.0
0.6
2.2
VCC+l
V
V
-1.0
1.0
V
VIHC
CE Input High Voltage
VOO-l
VOD+l
V
VOL
Output L.ow Voltage
IOL" 2mA
0
0.45
V
VOH
Output High Voltage
IOH =-2 mA
2.4
VCC
V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should l:Ie operated at these limits. The table of "Electrical Characteristics"
pJ:ov:ides conditions for actual device operation.
Note 2: All volteges referenced to VSS and Vas must be applied ~fore and removed after other supply voltages.
Note 3: Typical vaiues are for T A = 2SoC and nominal power supply voltages.
Note 4: The IDO arid ICC currents flow to VSS. The ISB current is the sum of all leakage currents.
Note 5: During CE "ON" VCC supply current is dependent on output loading. VCC is .connected to output buffer only.
ac electrical characteristics
PARAMETER
TA =-55°e to +85°e. Voo = 12V ±5%. Vee = flV ±5%, Vaa =-5V ±10%
CONDITIONS
MIN
READ. WRITE, READ/MODIFVIWRITE. AND REFRESH CYCLE
Time Between Refresh
tREF
tAC
Address to CE Set·Up Time
tAH
TVP
MAX
1
tAC is Measured From End of Address Transition
UNITS
ms
0
ns
Address Hold Time
100
ns
tcc
CE "OFF" Time
130
tT
CE Transition Time
10
CE "OFF"to Output High
Impedance State
READCVCLE
Cycle Time
tcv
ns
40
0
tCF
ns
ns
470
ns
tCE
CE"ON"Time
tco
CE Output Delay
tACC
Address to Output Access
tWL
CEtoW!:
0
ns
lWC
WE to CE "ON"
0
ns
300
CLOAD = 50 pF. Load. = 1 TTL Gate. Ref
=
ns
250
ns
270
ns
2V.
tACC = tAC +tco + 1 tT
1·57
3000
0
MIN
TVP
MAX
470
300
n.
3000
n.
130
n.
150
n.
0
n.
50
n.
Read and Refresh Cycle
READ-MODI FY-WRITE CYCLE
(Note 9)
285
240
330
ns
TRWC
Read-Modify-Write Cycle Time
TCRW
Read-Modify-Write CE ON Time
140
tcw
CE ON toWE
50
60
70
ns
tVVP
WE Pulse Width
30
40
50
ns
tw
WE to CE OFF
30
40
50
ns
to
DIN to CE OFF Set-Up Time
30
40
50
ns
tDH
DIN Hold Time
0
0
0
ns
3000
3000
175
210
3000
ns
tco
CE to Output Access
(Note 7)
90
115
140
ns
tACC
Address to Output Access
(Notes 7 and 8)
100
125
150
ns
Capacitance
0
(Note 10) T A = 25°C
PARAMETER
CONDITIONS
CAD
Address Capacitance, Cs
VIN = VSS
2
pF
CCE
CE Capacitance
VIN = VSS
15
pF
COUT
Data Output Capacitance
VOUT= OV
5
pF
4
pF
SYMBOL
CIN
DIN and WE Capacitance
Switching Time Waveforms
MIN
VIN = Vss
(Continued)
Ro.d-Modity-Write Cycle (Note 9)
1-67
TYP
MAX
UNITS
«o
CO
N
AC Electrical Characteristics
(Continued)
TA = O°C to +70°C, VOO = 12 ±5%, \!.BB = -5 ±5% (Note 4) VSS = 0, tT = 10 ns
It)
:E
:E
CONOITIONS
PARAMETER
SYMBOL
MM5280A-2
MAX
MM5280A-'
MIN
MAX
MIN
245
MM5280
MIN
MAX
UNITS
REFRESH CYCLE
tCY
Cycle Time
210
tCE
CE ON Time
lio
tcc
CE OFF Time
80
90
100
n'
tAC
Address and Chip Select to
0
0
0
ns
40
40
40
n.
3000
280
135
3000
n.
160
3000
n'
CE Set-Up Time
tAH
Address and Chip Select Hold
Hold Time
tT
CE Transition Time
(Note 6)
5
40
10
40
10
40
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed_ Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits_ The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Typical values are at 25°C, typical power supply voltage_
Note 3: The equation for defining IOOIAVE) is:
IMax) IOO(AVE)
=~tCETCY
+ t,-)
150 +(_1_)10_0 x 103
TCY
t,-
where tCE, and TCY are expressed in nanoseconds and the resultant IOO(AVE) is expressed in millamps_
Note 4: All voltages referenced to VSS- When applying voltages to the device VOOor VSS should never be 0_3V more negative than VBB.
Note 5: For Refresh Cycle, Rowand Column Addresses must be stable before tAC and remain stable for entire tAH period.
Note 6: For test purpose, input levels should swing between OV and 3V. VIH(MIN) and VILIMAX) are reference levels for measuring
transition times and timing of input signals.
Note 7: VOH = VSS + 2;OV and VOL = VSS + 0.8V are the reference levels for measuring timing of tco and IACC.
Note 8: IACC = tco
+ lAC. For test purposes tT = IOns.
±t,-
Nota 9: For minimum cycle time, tM = 10 ns.
Note 10: CapaCitance measured with Boonton Meter or effective capacitance calculated from the equation C = l.6.t/AV with the current
equal to a constant 20 rnA.
Switching Time Waveforms
(Continued)
Refresh Cycle (Note 5)
-
'AO
.." ~
AOORESS~
-;
,
I~
-'
CE
'II
1\
--,
-
rIJ~~''"l
os
.'T-
...,
-
I
'T~
~
~
-------------------------DOUT
OPEN
---------------------------1-68
s:
s:
Block Diagram
U'I
N
CO
o
S151
»
Alt (4)
AtOll)
Pin Names
A91Z1
AIIZl)
A1(ZO)
AI 1191
'AD-A11
CE
~
A5(1&1
A4114}
OIN
A31131
°OUT
NC
VBB
VCC
VOO
AlUIIJ
All1l1
AD II)
VSS
m
CE(17)
*Row address AD-AS
"00 (18) - - .12V
"SSI22I--0V
VB8 111 - - -5V .
Address Inputs
Chip Enable
Chip Select
Oatalnput
Oata Output
Not Connected
Power (-SV)
Power (SV)
Power (12V)
Ground
Write Enable
Memory inverts from Data In to Data Out
VCC(W--"V
1-69
D
~National
MOS RAMs
~ Semiconductor
MM5280-5 4096-bit dynamic random access read/write memory
general description
features
The MM5280-5 is a slower speed version of National's
MM5280_ Please refer to the MM5280 specification
for pin configuration, block diagram and switching
time waveforms_
•
•
absolute maximum ratings
Operating Temperature Range
Storage Temperature
All Input or OutPUT Voltages with Respect
(Note 1)
o°C to +70°C
Order Number MM5280D-5
~5°C to +150°C
to the Most Negative Supply Voltage. Vss
Supply Voltages VDD. VCC and VSS with
Respect to VSB
See Package 5
--{)_3V to +25V
--{).3V to +20V
Power Dissipation
1.25W
dc electrical characteristics
T A = O°C to +70°C Voo = +12V ±5%, Vee = +5V ±5%, V BB
SYMBOL
III
Access time-270 ns
Cycle time-470 ns
PARAMETER
Input Lo'ad Current
(Note 2)
= -5V ±5%, Vss = OV, unless otherwise noted.
CONDITIONS
VIN
==-
OV
MIN
to V 1H max, (All Inputs
TYP
MAX
UNITS
0_01
10
I'A
0.01
10
I'A
0.01
10
I'A
Except CE)
I Le
Input Load Current
VIN
IILol
Output Leakage Current, Up For
CE'~
;0:
OV
to V 1HC max
VILe or CS
= V ,H • Va = OV to 5.25V
High Impedance State
'001
V DO Supply Current During
CE = -lV to +6V. Note 4
110
I'A
20
mA
35
rnA
CE "OFF"
100:2
Veo Supply Current During
CE "ON"
= 230 ns
'DO AVl
Average Veo Current
Cycle Time = 400 ns.
I DO AV2
Average V DO Current
Cycle Time"" 1000 ns. teE = 230 ns
Iccl
V cc Supply Current During
tCE
rnA
15
0_01
10
I'A
100
I'A
CE "OFF"
5
IBB
Vss Supply Current Average
V IL
Input Low Voltage
-1.0
V ,H
Input High Voltage
2.4
VILC
CE Input Low Voltage
V 1HC
CE Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
-1.0
10L = 2.0 rnA
0.0
IOH = -2.0 mA
2.4
0.6
V
V cc +l
V
1.0
V
V oo +l
V
0.45
V
Vee
V
Note 1: '~Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: The only requirement for the sequence of applying voltage to the device is that VDO; Vee, and VSS should never be O.3V more negative
than VBB.
Note 3: Typical values are for T A = 25° C and nomi'nal power supply voltages.
Note 4: The I DD and ICC currents flow to VSS. The ISS current, is the sum of all leakage currents.
Note 5: During CE "ON" Vee supply current is dependent on output loading, Vee is connected to output buffer only.
1-70
s:
s:U1
ac electric,al characteristics
TA
=o°c to +70°C, V DD = 12V ±5%, Vce = 5V ±5%, VB!> =-5V ±5%
SYMBOL
I
PARAMETER
I
CONDITIONS
N
CO
I
MIN
I
I
TYP
READ, WRITE, READ/MODIFYIWRITE, AND REFRESH cYCLE
MAX
I
o
UNITS
tREF
Time Between Refresh
tAC
Address to CE Set-Up Time
tAH
Address Hold Time
5.0
ns
tec
CE "OFF" Time
13.0
ns
2
t AC is Measured, From End of Address Transition
.0
tT
CE Transition Time
1.0
tCF
CE "OFF" to Output High
.0
I
U1
ms
ns
.'
4.0
ns
"s
Impedance State
READ CYCLE
tCY
Cycle 'Time
47.0
tCE
CE "ON" Time
300
tco
CE Output Delay
tAce
Address to Output Access
tWL
CE to
WE
.0
ns
twc
WE to
CE "ON"
.0
n'
n.
C LOAD "5.0 pF, Load" 1 TTL Gate, Ref" 2,.oV,
tAce = tAC + teo +
3.0.0.0
ns
25.0
ns
27.0
ns
1 tT
WRITE CYCLE
tCY
Cycle Time
47.0
tCE
CE "ON" Time
3.0.0
tw
WE to CE"OFF"
15.0
ns
tew
CE to WE
13.0
ns
10
DIN to CE Set~Up
15.D
ns
tOH
DIN Hold Time
.0
ns
twP
WE Pulse Width
5.0
ns
09.0
ns
tT' = 20
ns
ns
3.0.0.0
ns
READ/MODIFYIWRITE CYCLE
tAWC
Read Modify W.rite (RMW)
Cycle Time
t CAW '
CE Width During RMW
Iwp
WE to CE "ON"
WElD CE "OFF"
WE Pulse Width
to
DIN
tOH
DIN Hold Time
tco
CE to Output Delay
two
WE to 00UT Invalid
tAce
Access Time
twc
tw
42.0
tT
0;;
20 ns, C LOAO
Ref =- 2.0V,
=:
50 pF, Load::o 1 TTL Gate,
tAce = t AC
+ teo + 1 tT
to CE Set-Up
3.00.0
ns
.0
ns
15.0
n5
5.0
ns
15.0
ns
.0
ns
250
ns
27.0
n,
0
CAPACITANCE (Note 1)
TA " 25°C
'CS
~
CAO
Address· Capacitance,
2
pF
CCE
CE Capacitance
Vj(\) ~ Vss
15
pF
COUT
Data Output Capacitance
V OUT == OV
5
pF
C'N
DIN and WE Capacitance
V 1N
4
pF
V 1N
=:
V ss'
Vss
Note 1: Capacitance measured with Boonton Meter or effective capacitance calculated from the equation C"'" l,1.t/AV with the current
equal'to a constant 20 rnA.
1-71
u
~National
MOS RAMs
~ Semiconductor
MM5281 4096-bit fully TTL compatible dynamic
general description
National's MM5281 is a 4096 word by 1 bit fully TTL
compatible dynamic RAM. It incorporates the latest
memory design features and can be used in a wide variety
of applications, from those which require very high
speed to ones where low cost and large bit capacity are
the prime criteria.
The single device cell,' along with unique design features
in the on-chip peripheral circuits, yields a high perfor·
mance memory device.
The MM5281 must be refreshed every 2 ms. This can be
accomplished by performing a read cycle at each of the
64 row addresses (AO-A5). The chip select input can
be either high or low for refresh.
•
•
•
•
•
•
•
•
features
The MM5281 has been designed with minimum production costs as a prime criterion. It is fabricated using
N·channel silicon gate MOS'technology, which is an ideal
choice for high density integratedcircuits. The MM5281
uses a single transistor cell to minimize the device area.
Organization: 4096 x 1
Access time 250 ns maximum
Cycle time 400 ns minimum
TTL compatible
Address registers on-chip
TRI-STATE@ output
Simple read-modify-write operation
Industry standard pin configuration
block and connection diagrams
WE (12)
Dual-I n-Line Package
CSl51
'S
~
LATCH
121
All (4)
~
M
20
21
M
19
~
~
18
~
16
17
M
15
Al0 (3)
AA
"
~
U
13
12
A9(2)
1\8 (21)
11.7 (20)
A6 (19)
A5 (15)
44(14)
A3(13)
A21101
Allg)
AD (a)
1
2
3
4
Al0
All
5
6
1
DIN
DOUT
MEMORY
ARRAY
Vee
4096 BITS
A9
CS
-
8
AD
TOP VIEW
"1111
Order Number MM5281 0
See Package 5
Voo (14) - - +12V
Vss ( 1 B l - - BV
Y.(1) - - -5V
Pin Names
AD-A11
Address Inputs*
V BB
Power 1-5V)
CE
Chip Enable
Power 1+5VI
CS
Chip Select
Vee
V DD
D'N
DouT
Data Input
Vss
WE
Ground
NC
Not Connected
Data Output
*Refresh Address AO-A5
1-72
Power (+12V)
Write Enable
,
Al
10
AZ
1'1
Vee
"
absolute maximum ratings
Operating Temperature Range
Storage Temperature
All Input or Output Voltages with Respect
to the Most Negative Supply Voltage, VBB
(Note 1)
oOe to +70o e
-65°e to +150o e
-o.3V to +25V
Supply Voltages VDD, Vee and VSS with
Respect to VBB
'
-o.3V to +20V
Power Dissipation
1.25W
dc electrical 'characteristics
T A = oOe to +7oo e V DD = +12V ±5%,' Vee = +5V ±5%, Vss (Note 2) = -5V ±5%, Vss = OV, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
=OV
IL'
Input Load Current
V 1N
IiLol
Output Leakage Current Up For
High Impedance State
CE = V'H or
V OD
1001
Supply Current During
CE
MIN
to V 1H max
CS = V'H. Vo
= OV to 5.25V
= V'H
TYP
MAX
0.01
10
UNITS
/J.A
0.01
10
IJ.A
1
mA
20
mA
35
mA
CE "OFF"
Voo Supply Current' During
CE'''ON''
1002
'ODAV1
Average V DO Current
'DO AV2
Average Voo Current
'eel
Vee Supply Current During
CE=V'L. TA = 25°C
Cycle Time
TA = 25'C
= 400 ns, teE
= 240 ns
Cycle Time = 1000 ns, t CE
CE = V'H or
= 240 ns
mA
15
CS = V,H.llllote 5)
0.Q1
10
IJ.A
CE "OFF"
I ••
V BB SupplV Current Average
V'L
Input low Voltage
V'H
Input High Voltage
5
-1.0
tT = 10 ns (Figure 4)
100
iJ.A
0.6
V
2,4
VOL
Output Low Voltage
IOL = 2.0 mA
0.0
0,45
V
V OH
Output High Voltage
IOH = -2.0 mA
2,4
Vee
V
Note 1: "Absolute Maximum Rat'ings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Tem~
perature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: The only requirement for the sequence of applying voltage to the device is that Voo, Vee. and Vss should never be 0.3V more negative
than VBS'
Not~ 3: Typical values are for TA = 25°C and nominal power supply voltages.
Note 4: The IDO and ICC currents flow to VSS' The IBB current is the sum of all leakage currents,
Note 5: During CE "ON" Vee supply current is dependent on output loading, Vee is conne~ted to output buffer only.
ac electrical characteristics
~YMBOL
I
T A = O°C to +7ooe. V DD
PARAMETER
= 12V :';5%, Vee = 5V ±5%. Ves = -5V ±5%
CONDITIONS
I
MIN
I
TYP
I
MAX
I
UNITS
READ. WRITE. READ/MODIFY/WRITE. AND REFRESH CYCLE
Time Between Refresh
Address to CE Set-Up Time
2
tAC
is Me~sured From End of Address Transition
Address Hold Time
tee
CE "OFF" Time
EE Transition Time
ns
100
ns
ns
140
40
CE "OFF"to Output High
ms
a
ns
ns
50
Impedance State
READ CYCLE
tcv
Cycle Time
400
tCE
CE "ON" Time
240
tco
CE Output Delay
Address to Output Access
CE to
e LOAO = 50 pF. load = 1 TTL Gate. Ref; 2,OV.
tAce
= tAc + teo
ns
3000
ns
250
ns
250
WE
WE to CE "ON"
1-73
ns
o
ns
a
ns
...
00
N
It)
:!!
:!!
ac electrical characteristics (con't)
+7aoc, V OD = 12V ±5%, Vcc = 5V ±5%, Vee =-5% ±5%
T A = aOc to
SYMBOL
I
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
WRITE CYCLE
tCY
Cycle Time
400
tCE
CE "ON" Time
WE to CE "OFF"
240
tw
tcw
to
CE to WE
0 ,,, to CE
100
tT ::: 10 ns
Set-Up
ns
3000
ns
ns
150
ns
100
ns
tDH
o IN
Hold Time
50
ns
twp
WE Pulse Width
50
ns
switching
time waveforms
Read and Refresh Cycle (See Note 1)
f - - - - - - - - - - - I c v (400)--------~--I
ADDRESS
ANDCS
V,L
1 - - - - - - - - - I c E (240) - - - - - - - 1
vlH---f-",
V,L----4---P~-----------------~
V'H---tir-~-------------------t,.-,~---+--V,L
i - - - - - - - - - I c o (2501-----~__l
1---------~tACC
(250) ---------I~_i
Write Cycle
i-----------Icv (400)-----------l
VIH
ADDRESS
APiD CS
ADDRESS CAN CHANGE
V,L
V,H
~
V,L
V,H
WE
WE CAN CHANGE
V,L
V,H
D,N CAN CHAPIGE
DIN
V,L
V""---DOUT
1------'0 nOD) ---~
I-
HIGH
IMPEDAPICE
VOL - - - -
Note 1:
Note 2:
Note 3:
Note 4:
UNDEFINED
For refresh cyde, row and column addresses must be stable before tAC and remain stable fOr entire tAH period.
V,L mal( is the reference level for measuring timing of the address, CS and D,N.
V,H min is the reference level for measuring timing of the addresses, CS and D,N.
Vss + 2.0V is the reference level for measuring the timing of OOUT for a high OUlput.
1-74
ac electrical characteristics (con't)
T A : o°C to +70°C,V DO= 12V ±5%, Vee = 5V ±5%,
PARAMETER
SYMBOLJ
V BB
= -,-5% ±5%
MIN
CONDITIONS
TYP
MAX
UNITS
READ/MOOIFYJWRITE CYCLE
tAwc
ns
510
Read Modify Write (RMW}
Cycle Time
tCRW
CE Width
Iw
twP
WE
to
DIN
tOH
DIN Hold Time
to
10 ns, C lOAD
50 pF, Load"" 1 ITl Gate,
Ref;:: 2.0V, t Ace ;:: 'tAc + teo
tT '"
Pulse Width
'wo
tAce
Access Time
ns
3000
0
ns
100
ns
50
ns
100
ns
;::
CE Set-Up
CE to Output Delay
w-E" to DOUT' Invalid
teo
350
During RMW
WE 10 CE"ON"
WE to CE "OFF"
twc
ns
50
250
ns
250
ns
0
CAPACITANCE (Nat. 11
T A = 25"C
CAD
Address Capacitance, CS
VIN = Vss
2
pF
CeE
CE Capacitance
VIN =Vss
5
pF
COUT
Data Output Capacitance
V OUT
5
pF
C 'N
DIN .and ~E Capacitance
V 1N =Vss
==
OV
4
pF
l~t/.6.V
Note 1: Capacitance measured with Boonton Meter or effective capacitance- calculated from the equation C.:=:
with the current
equal to a constant 20 rnA
switching time waveforms (con't)
,
Read Modify Write Cycle
I
tRWC
(510)
I--'AH (1001_
ADDRESS VIH=>.
AND CS
V"
-
~
-
)C -
ADDRESS CAN CHANGE
ICRW (350)
0
-H
WE
V,L-----J
'--
....--twc (0)
~'wp(501-
0\
1/
V
-tce (1401_
WE CAN_fHANGE
I
tD (100)
V,H
D,.CAN CHANGE
D,N
V"
)
VaH-----1\
HIGH
rlMPEDANCE VoL---I- - t A c e (250)
~
)
@VALID
-
I
K
D,N VALID
r - - - t e o (2501_
DOUT
-IT (101
_-'T(10) -
-lw(100)~~-
\0
CE
V,H
K
tAc(oi
V,H
v"
AhDRESS VALID
tWalD)
-
CAN
CHANGE
I-- IDH (50)
I
~UNDEFINE~~ ~I;;;; ~
Note 1 WE must be high until end of teo.
Note 2: V1L max is the reference level for measuring timing of the address, ES,
/
D,N
IMPEDANCE
----
and
WE.
Note,3; V'IH inin is the,refercn;::e level for measuring timing of t.he address, CS, DIN and WE.
Note 4: Vss + 2.DV is the referenCe lev-el for measurillg the timilig of DOU'T for a high ou'tput.
1-75
DIN
~National
MOS RAMs
~ Semiconductor
MM5290 16,384 )( 1 Bit Dynamic RAM
General Description
The MM5290 is a 16,384 x 1 bit dynamic RAM. It
features a multiplexed address input with separate row
and column strobes. This added flexibility allows the
MM5290 to be used in page mode operation.
by the use of a 16-pin dual-in-line package for the
MM5290.
The MM5290 must be refreshed every 2 ms. This can be
accomplished by performing any cycle which brings the
Row Address Strobe active including an RAS-only
cycle at each of the 128 row addresses.
•
•
•
•
•
Features
Access times: 150 ns,' 200 ns, 300 ns
Low power:462 mW max
TTL compatible: all inputs and output
Gated.CAS-noncritical timing
Read, Write, Read-Modify-Write and RAS-only
Refresh cycles
• Page mode operation
• Industry standard 16-pin configuration
N-channel double-poly silicon gate technology, developed
by National, is used in the manufacture of the MM5290.
This process combines high density and performance
with reliability. Greater system densities are achievable
Block and Connection Diagrams
Voo
AD-
l1V
02-
..-
vee
V58
VBB
5V
GNO
l
-5V
~
~
Al-
01
~
A3AS-
COLUMN
CLOCKS
A6-
ROW
CLOCKS
ROW
CLOCKS
MEMORY ARRAY
64 X 111
~
'"
COLUMN
CLOCKS
~
I!
WRITE
~LoeKS
SENSE AMPLIFIERS 112I}
00
MEMORY ARRAY
64 X 128
Dual-In-line Pac:kage
1& Vss
VBB
15
01
14
lil
13
m
12
AD
"
A2
10
Al
•
Voo
m
Pin Names
00
RAS
A6
CAs
.
WE
AD-A6
A3
A5
01
DO
•
VDD
Vce
VSS
VBB
Vee
TOP VIEW
Dreier Number MM5290J
See Pac:kage 10
1-76
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Data Input
Data Output
Power (12V)
Power (5V)
Ground
Power (-5V)
Absolute Maximum Ratings
Operating Temperature Range
Storage Temperature
Power Dissipation
(Note 1)
O°C to +70°C
-65°C to +150 oC
lW
Voltage on Any Pin Relative to VBB
-o.3V to +20V
(VSS - VBB 24.5VI
Lead Temperature (Soldering, 10 secondsl
300 0
e
s:
s:
U1
N
CD
o
Recommended DC Operating Conditions
MIN
PARAMETER
SYMBOL
TA
Ambient Temperature
VOO
Supply Voltages
0
MAX
UNITS
70
°c
NOTES
10.8
13:2
V
Vce
4.5
5.5
V
2, 3
VSS
0
0
V
2, 3
VBB
-4.5
-S.S
V
2, 3
2.7
7.0
V
2
2.4
7.0
V
2
-1.0
0.8
V
2
VIHC
Input High Voltage, RAS, CAS, WE
VIH
Input High Voltage, AO-AS, 01
VIL
Input Low Voltage, All Inputs
2, 3
DC Electrical Characteristics
TA = oOe to +70 0 e, Voo
= 12V ±10%,
Vce =
sv ±10%, VBB = -sv ±10%,VSS = OV, (Notes 2 and 31
PARAMETER
SYMBOL
MIN
MAX
UNITS
1001
Operating Current
ICCl
Average Power Supply Operating Current
35
mA
ISBl
I RAS, CAS Cycling; tRC = 37S nsl
200
{JA
1002
Standby Current
leC2
Power Supply Standby Current IRAS = VIHC,
1.S
mA
10
ISB2
00= High Impedancel
100
{JA
{JA
1003
Refresh Current
leC3
Average Power Supply Current, Refresh Mode
25
mA
10
iJ. A
ISB3
IRAS Cycling, CAS = VIHC; tRC = 375 nsl
ioo
{JA
1004
Page Mode Current
27
mA
ICC4
Average Power Supply Current, Page Mode
IBB4
I RAS = V I L, CAS Cycl ing; tpe = 225 nsl
200
{JA
IIILI
Input Leakage
-10
10
{JA
-10
10
{JA
V
V
NOTES
4
5
-10
-10
4
4
5
I nput Leakage Current, Any Input
IVSB
~
-SV, OV -s:; VIN -s:; 7V, All Other
Pins not Under Test
lOlL)
~
OVI
Output Leakage
Output Leakage Current (00 is Disabled,
OV -s:; VOUT -s:; S.5VI
Output Levels
~
VOH
Output High Voltage IIOUT
VOL
Output Low Voltage (lOUT ~ 4.2 mAl
-S mAl
2.4
0.4
CAPACITANCE
CI
Input Capacitance AO-AS, 01
5
pF
6
Cc
Input Capacitance RAS, CAS, WE
10
pF
6
Co
Output Capacitance, DO
7
pF
6
Note. 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of NRecommended DC Operating
Conditions" provides conditions for actual device operation.
No.te 2: All voltages referenc~d to VSS. When applyin-g voltages to the devic~, VOD, Vce orVSS should,never be' O.3V more negative than VBS.
l\Iote 3:
l\Iot.4:
l\Iot85:
l\Iote 6:
Severa,1 cyd€!s are required after power·up before proper device operation is achieved. Any 8 RAS cydes are adequate for this purpose.
1001,IOD3, and 1004 depend on cycle rate.
ICC tRCD(MAX)'
Note 10: Equivalent load is 2 standard TTL inputs plus 100 pF.
Note 11: CAS going high disables the Data Output. tOFF i. the delay to the high impedance state.
Note 12: These parameters are referenced to the negative edge of CAS in an early,write cycle and to the negative edge of WE in a Read·Modify·
Write cycle. (See Note 12. below).
Note 13: If twcs ,2: twCS(MIN). the Data Output i. guaranteed to remain in the high impedance state for the duration of the cycle. This is the
uearly..write" cycle.
Note 14: If tCWD 2: tCWD(MINI and tRWD 2: tRWD(MIN). the Data Output will contain the original data in the selected cell. This i. the Read·
Modify·Write cycle. If either of these conditions is not satisfied, the output will be indeterminate unless the early·write condition of Note 12 is met.
1·78
Switching Time Waveforms
Read Cycle
WE VIHCVIL -
DO
""''"''"''""'''"'I''''''="-''J
i - - - - - - ' C A C ----.-1~
:::= ___________
(---~-~-~A-o--'-OF-F~-------
OPEN _ _ _ _ _ _ _ _ _ _ _ _
Write Cycle (Early Writel
RAS
VIHCVIl-
tACO
CAS
AD-A6
VIHC~
Vll-
VIH-
VIL-
WE
VIHCVIL -
01
V'HVIL -
DO
VOH-
OPEN
VOL -
1-79
Switching Time Waveforms
(Continued)
Read-Write Cycle, Read-Modify-Write Cycle
liAS
rn
AO-A6
VIHCVll-
VIHC VIl-
VIH-
Vll-
Wi'
DO
VIHC Vll-
VOH VOL -
RAS-Only Refresh Cycle
AO-AS
DO VOHVOl- -------------------------------------OPEN--------------~--------------------Note, CAS
=
VIHC, WE
=
don't care
1-80
Switching Time Waveforms
(Continued)
Page Mode Read Cycle
1m ~'He
VIl-
AD-A6
DO
VDHVOL-
------~IOPl'N-----_<
Ii
Page Mode Write Cvcle
1m
v'HeV'L-
eA!I
v'HeV'L-
flr vIHC-
v'L- ~~~~~~~~-~~~~~~~~~~-~~~~~~I~~~~~-----1~~~~
1-81
o
~
Timing Flow Chart
It)
:E
:E
ACTIVE
TRANSFER DATA FRDM SELECTED
COLUMN IN MEMORY ARRAY
TO I/O LINES IN READ MODE
AND VICE VERSA IN WRITE MODE
PRECHARGE
1-82
~ National
a
Bipolar RAMs
Semiconductor
DM5489/DM7489 (SN5489/SN7489)
64-bit random access read/write memory
general description
Memory Enable input is in the logical "1" state,
the outputs will go to the logical "1" state.
The DM5489/0M7489 is a fully decoded 64-bit
RAM organized as 16. 4-bit words. The memory is
addressed by applying a binary number to the four
. Address inputs. After addressing, information may
be either written into or read from the memory_
To. write, both the Memory Enable and the Write
Enable inputs must· be in the logical "0" state.
Information applied to the four Write inputs will
then be written into the addressed location. To.
read information from the memory the Memory
Enable input must be in the logical "0" state and
the Write Enable input in the logical "1" state.
Information will be read as the complement of·
what was written into the memory. When the
features
•
•
•
•
•
•
Series 54/74 compatible
Organized as 16 4-bit words
Typical access from chip enable 23 ns
Typical access 35 ns
Typical power dissipation 400 mW
Open collector outputs to permit "wire OR"
capability
block diagram
~~:
A,
AD8REIS
IIIPUTS
~A'
"
A,
A'~~.,
~~:
DI
s,
~
DATA
''''''''
"
SEilS!
OUTPUTS
~
~
connection diagram
truth table
Dual-In-Line Package
Order Number DM5489J
or DM7489J
.
See Package 10
MEMORY' WRITE
ENABLE
ENABLE
0
1
Write
Read
1
X
Hold.
Order Number DM7489N
See Package 15
TOtvlEW
2-1
OPERATION
0
0
OUTPUTS
Logical "1" State
Comptement of Data
Stored in Memory
Logical "1" State
absolute maximum ratings
(Note 1)
7V
Supply Voltage
Input Voltage
5.5V
Output Voltage
5.5V
Operating Temperature Range
-55°C to +125°C
DM5489
O°C to +70°C
DM74S9
-65°C to +150°C
Storage Temperature Range
300°C
Lead Temperature (Soldering, 10 sec)
electrical characteristics
INote 2)
PARAMETER
CONDITIONS
MIN
MAX
TVP
UNITS
Logical "1" Input Voltage
DM5489
DM7489
Vee = 4.5V
Vee - 4.75V
Logical "0" I nput Voltage
DM5489
DM7489
Vee = 4.5V
Vee - 4.75V
Logical "1" Output Current
DM5489
DM7489
Vee = 5.5V
Vee = 5.25V
Logical "0" Output Voltage
DM5489
DM7489
Vee= 4.5V
Vee = 4.75V
Logical "I" Input Current
DM5489
DM7489
Vee = 5.5V
Vee - 5.25V
V,N = 2.4V
40
IlA
OM5489
DM7489
Vee = 5.5V
Vee - 5.25V
V,N = 5.5V
1
mA
Logical "0" I nput Current
OM5489
DM7489
Vee = 5.5V
Vee - 5:25V
-1.6
mA
Supply Current
DM5489
OM7489
Vee = 5.5V
Vee - 5.25V
Input Clamp Voltage
DM5489
OM7489
Vee = 4.5V
Vee - 4.75V
switching characteristics
2.0
V
0.8
100
20
Vo = 5.25V
10 = 12 mA
0.4
All Inputs at GNO
80
120
Vee
-1.5
I'N=-12mA
V
JJ.A
IlA
V
mA
V
(Over recommended operating ranges of Vee and TAl
PARAMETER
CONDITIONS
DM5489
MIN
tpLH
DM7489
TYP
MAX
MIN
TYP
MAX
UNITS
34
80
34
60
35
80
35
60
ns
ns
23
55
23
40
ns
23
55
23
40
ns
Access Time From Address
tpHL
tpLH
Disable Time from Memory Enable
tpHL
Enable Time From
Memo~y
tSETUP Setup Time
Enable
Address to Write
Enable
Data to Write Enable
Memory Enable To
tHOLD
Hold Time
Write Enable
,Address From Write
Ru =300n
RL2 = 600n
CL = 30 pF
Enable
Data From Write
Enable
Memory Enable
From Write Enable
twp
Write Pulse Width
tSR
Sense Recovery Time
0
-14
0
-14
ns
0
15
0
15
ns
0
-10
0
-10
ns
5
-7
5
-7
n,
0
-14
0
-14
n,
0
-10
0
-10
n,
40
'20
50
20
31
65
31
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "o.perating Temperature Range" they are not meant to imply that the
devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions
for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the -55'e to +125'e temperature
range for the DM54B9 and across the oOe to 7fi'e range for the DM74B9. All typicals are given for
Vce = 5.0V and T A = 25°C.
2·2
ns
55
ns
typical performance characteristics
Delay from Memory Enable
to Output
Delay from Address to Output
80
80
Vee~'
Vee:o 5.0V
>-
g
5.0V
70
70
60
60
50
!>-
.50
~
30
,- ~
tpLH
40
40
S
30
'i
tp'o:.:;
HL
20
10
10
o
50 .75
-75 -50 -25
1(10 125
---,-
I
o
25
-75 -50 -25
E::: ~
IL
20
0 .25
50
75 100 125
TEMPERATURE ('CI
TEMPERATURE ('CI
Minimum Write Pulse Width
Sense 'Recovery Time
80
40
Vee'" 5.DV
Vee '" 5.nV
35
70
60
30
!
50
40
t- I--
30
20
'"\;
25
jO
20
~
15
t""
I- J--
--
10
10'
o
o
-75 -50 -25
0
25
50
75 100 125
-75 c50 -25
TEMPERATURE ('CI
0
25
50
75
100 125
TEMPERATURE ('CI
ac test circuit and switching time waveforms
50V
Read Cycle
Write Cycle
ME~
~ f--t~L
.
.
t"H~
f-ME
WE---:-+-"""\J
ADOR£SS-----...J
'.
address
addres~
address
B
C
'"~
OUTPUT
"OutputsholNlllnJ stored data in
address A ~ 1,
inadd'e~
B= 0
2·3
1-
~National
Bipolar RAMs
~ Semiconductor
OM54LS189/0M74LS189 low power 64-bit
random access memories with TRI-STATE® outputs
general description
These 64-bit active-element memories are monolithic
Schottky-clamped transistor-transistor logic (TTL) arrays
organized as 16 words of 4 bits each. They are fully
decoded and feature a chip enable input to simplify
decoding required to achieve the desired system organization. This device is implemented with low power
Schottky technology resulting in one-fifth power while
retaining the speed of standard TTL.
but it will allow the bus line to be driven by another
active output or a passive pull-up if desired.
Read Cycle: The stored information (complement of
information applied at the data inputs during the write
cycle) is available at the outputs when the read/write
input is high and the chip enable is low. When the chip
enable input is high, the outputs will be in the high
impedance state.
The TR I-STATE output combines the convenience of
an open-collector with the speed <>f a totem-pole output;
it can be bus-connected to other similar outputs, yet it
retains the fast rise time characteristics of the TTL
totem-pole output. Systems utilizing data bus lines with
a defined pull-up impedance can employ the opencollector DM54LS289.
features
• Schottky-clamped for high speed applications
Access from chip enable input-40 ns typ
Access from address inputs-60 ns typ
• TR I-STATE outputs drive bus-organized systems
and/or high capacitive loads
• Low power-75 mW typ
• DM54LS189 is guaranteed for operation over the full
military temperature range of-55°C to +125°C
• Compatible with most TTL and DTL logic circuits
• Chip enable input simplifies system decoding
Writa Cycle: The complement of the information at the
data input is written into the selected location when
both the chip enable input and the read/write input are
low. While the read/write input is low, the outputs are in
the high impedance state. When a number of the
DM54LS189 outputs are bus-connected, this high
impedance state will neither load nor drive 'the bus line,
connection diagram
truth table
Dual-In-line and Flat Package
SELECT INPUTS
'B
/"
DATA
0'
15
14
INPUT
4
13
12
INPUTS
DATA
OUTPUT
Y4
11
INPUT
J
OUTPUT
V3
10
FUNCTION
CHIP
ENABLE
READ/
WRITE
OUTPUT
Write
L
L
Hz
Read
L
H
Stored Data
Inhibit
H
X
Hz
9
(Store Complement of Data)
p-
r-
I
2
SELECT
CHIP
INPUT A ENABLE
3
READI
WRITE
,
DATA
INPUT
1
5
OUTPUT
Yf
TOP VIEW
6
DATA
INPUT
2
high level
H
~
L
= low level
X
= don't care
Order Number DM54LS189J or DM74LS189J
See Package 10
Order Number DM74LS189N
Se. Package 15
Order Number DM54LS189W
See Package 28
7
OUTPUT
Y2
GNO
"
2-4
absolute maximum ratings
Supply Voltage, Vec
I nput Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
operating conditions
(Note 1)
~5·C
Supply Voltage (Vee)
DM54LSI89
DM74LSI89
Temperature (TA)
DM54L.SI89
DM74LS189
7V
5.5V
5.5V
to +150·C
300·C
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
55
0
·e
·e
+125
+70
electrical characteristics
Over recommended operating free·air temperature range (unless otherwise noted) (Notes 2 and 3)
PARAMETER
CONDITIONS
High Level Input Voltage
Low Leve.1 Input Voltage
VOH
High level Output Voltage
UNITS
V
V
0.8
IOH
Vee~Min
Low level Output Voltage
Vee
~
Min
~.-2
mA
2.4
3.4
2.4
3.2
v
IOL ~ 4 mA
DM54LS189
0.45
IOL ~8 rnA
DM74LS189
0.5
=' 2.7
High Level Input Current
Vee = Max, VI
High Level· Input Current at Maximum Voltage
Vee = Max, VI = 5.5V
IlL
Low Level Input Current
Vee = Max, V, = 0.45V
lOS
Short·Circuit Output Current (Note 4)
VCC
ICC
Supply Current (Note 5)
Vce= Max
VIC
Input Clamp Voltage
VCC
= Min, II = -18 mA
10ZH
TR I.'ST ATE Output Current, Hi.9h Level
VCC
= Max,
IOZl
TR I·STATE Output CUrrent, Low Level
Vee
= Max, Vo = 0.45V
II
MAX
2
Vll
VOL
TYP
MIN
10
Jl.A
1.0
mA
-100
= Max, Va = OV
-30
15
= 2.4V
Va
v
-100
mA
29
mA
-1.2
V
40
Vol tage Appl ied
40
Voltage Applied
switching time waveforms
C1tIPlNA8LE
3V
IN~UT
(SEE NOTE 3)
IV
"<1.sv
f-""-1
-
I
,,,'
Voe
Vo ,
Yak
(SH NOTE 1)
'-"1.5V
INPUTS
/T
!
.> "1.5V
1.liV
'- -'-
3V-----1-----+----~
CHIP,ENABLE
INPUT
tl;li2"
---'
ov--3V --c"\.
' O.5V
-'...
ov __ J
DATA
tNrUTS
~
:--r
f- ..,.--{
WAVEFDRMZ
AODRESS
.., L. D.'V
~T
WAVEFORM 1
(SEE NOTE 1)
f ~I-'A"'r ~
3V
.?t;.v
~.v
,
1-""'-
'","
.
~-------~---+------------+---,
3V
Enable a.nd Disable Time From Chip Enable
READIWAITE
INI'Ul
DV
ADDRESS
INPUTS
{NOTE 2)
OUTPUT
3V~.r"_""-----""
>1.5V
.¥~--..,.--.
'AA==!.
~~'AAI ~
:: -.--,.._ - - ~~.v
. . •. /"V .
WAVEfORM 1
(NQTE 11
av--/ ',::
Voe
WA\lHDRM2
___.,-_+__L)<+'
YO"
(SIOPEN
52 CLOSED)
(N,OlE 1)
1.5V
IT
I--- '.""'. -::I-_~I---c"'\J O'V
"T
'.".'"
-x·
'1
.
I
m
Write Cycle
Access Time From Address Inputs
FIGURE 1
Note 1: Waveform 1 is for the' output with internal conditions such that the outp'ut is low except when disabled. Waveform 2 is for'the output
with internal conditions such that the output is high except when disabled.
Note 2. When measuring delay times from address inputs, the chip enable input is, low and the, read/write input ·is high.
Note 3: When measuring delay times from' chip enable input, the address inputs are steady-state and the read/write input is high.
Note 4: Input waveforms are supplied by' p,ulse generators having the following characteristics: tr
ZOUT
~
501!.
..
2·5
:S 2.5 ns, tf :S '2.5 ns, PRR S 1 MHz, and
switching characteristics
Over recommended operating ranges of TA and
Vee
(unless otherwise noted)
PARAMETER
CONDITIONS
DM54lS189
MIN
TYP(1)
DM74lS189
MAX
MIN
TYP(1)
MAX
UNITS
tAA
Access Times From Address
60
100
60
80
ns
teZH
Output Enable Time to
40
80
40
60
ns
40
80
40
60
ns
60
100
60
80
ns
60
100
60
80
ns
40
80
40
60
ns
40
80
40
60
ns
teZl
High Level
Access Times From
Output Enable Time to
Chip Enable
Low Level
twZH
twZl
eL = 30 pF, RL
= 1 k~,
Output Enable Time to
High Level
Sense Recovery Times
Output Enable Time to
From ReadIWrite
Low level
teHZ
telz
Output Disable Time
From High Level
Disable Times From
Output Disable Time
Chip Enable
F rom Low Level
twHZ
twlZ
Cl=5pF, RL = 1
k~,
Output Disable Time
From High Level
Disable Times,From
Output Disable Time
ReadIWrite
40
40
40
40
ns
From Low ',Level
twP
Width of Write Enable Pulse (ReadIWrite low)
80
60
tASW
Set-Up Time
a
0
Address.to ReadIWrite
tDSW
Data to ReadIWrite
100
80
'CSW
Chip Enable to
0
0
Address From ReadlWrite
10
5
tDHW
Data From Read/Write
0
0
'CHW
Chip Enable From
0
0
ns
ns
ReadIWrite
'AHW
Hold Time
ns
Read/Write
Note 1; "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical c'haracteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply aCrOSS the ~55°C to +12SoC temperature range for the DM54LS189 and across the O°C
to +70o e range for the DM74LS189. All typicals are given for Vee
= 5V and T A = 25°e,'
Note 3: All currents into device pins shown as positive, out of device pins as negatil{e. all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value b~sis.
Note 4: Only one output at a time should be shorted.
Note 5; ICC is measured with all inputs grounded, and the outputs open.
2-6
~National
a
Bipolar RAMs
Semiconductor
DM54S189/DM74S189 64-bit random access
memories With TRI-STATE®outputs
general description
input is high and the chip-enable is low. When the chipenable input is high, the outputs will be in the highimpedance state.
These &i-bit active-element memories are monolithic
Schottky-clamped transistor-transistor logic (TTL) arrays
organized as 16 words of four-bits each_ They are fully
decoded and feature a chip-enable input to simplify
decoding required to achieve the desired system organization_ The' memories feature PNP input transistors that
reduce 'the low level input current requirement to a
maximum of -0_25 mA, only one-eighth that of a
DM54S/DM74S standard load factor. The chip-enable
circuitry is implemented with minimal delay times to
compensate for added system decoding_
The fast access time of the DM54S189 makes it
particularly attractive for implementing high-performance
memory functions requiring access times on the order
of 25 ns. The high capacitive-drive capability of the
outputs permits expansion without additional output
buffering. The unique functiortal capability of the
DM54S 189 outputs being at a high impedance during
writing 'combined with the data inputs being inhibited
during reading means that both data inputs and outpufs
can be connected to the data lines of a bus-organized
system without the need for interface circuits.
The TRI-STATE output combines the convenience of
an open-collector with the speed of a totem-pole output;
it can be bus-connected to other similar outputs, yet it
retains the fast-rise-time characteristics of the TTL
totem-pole output_ Systems utilizing, data-bus lines with
a defined pull-up impedance can employ the opencoliectorDM54S289_
features
Write eYllle: The complement of the information at the
data input is written into the selected location when both
the chip-enable input and the read/write input are low.
While the read/write input is low, the outputs are in the
high-impedance state. When a number of the DM54S1S9
outputs ,are bus-connected, this high-impedance state
will neither load nor drive the bus line, but it will allow
the bus line to be driven by another active output or a
passive pull-up if desired.
Read Cycle: The stored information (complement of
information applied at the data inputs during the write
cycle) is available at the outputs when the read/write
• Schottky-clamped for high-speed applications:
access from chip-enable input
12 ns typ
access from address inputs
25 ns typ
• TRI-STATE outputs, drive bus-organized systems
and/or high capacitive loads
• DM54S289, DM74S289 are functionally equilvalent, have open-collector outputs, and' are compatible with Intel 3101A inmost applications
• DM54S189 is guaranteed for operation over the full
military temperature range of -55°C to +125°0
• Compatible with most TTL and DTL logic circuits
• Chip·enable input simplifies system decoding
connection diagram
truth table
Dual-In-Lina Package
SELECT INPUTS
VTCC
16
o'
'a
15
14
DATA
IN~UT
12
13
DU~:UT
11
DATA
INPUT
OUTPUT
3
V3
10
INPUTS
FUNCTION
CHIP
ENABLE
READI
WRITE
OUTPUT
High Impedance
,Witte
(Store Complement of .Datal
0-
H
~
Read
H
Stored Data
InhIbit
x
High Impedance
High L,eve!
L ~ Low Level
X,"- Don't CiJre
'3
SHECT
CHIP
INPUT A ENABLE
READI
WRITE
4,
DATA
INPUT
1
OUTPUT
VI
DATA
INPUT
2
, ,Order Number OM64S189J or DM74$189J
Sea. Package 10
Ordar Number DM74$189N
Sao Packag. 15
OUTPUT
V2
TOP VIEW
2-7
absolute maximum ratings
Supply Voltage, Vee
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
operating conditions
(Note 1)
7.0V
5.SV
5.SV
·~5°e to +150o e
3000 e
Supply Voltage (Vee)
DM54S189
DM74S189
Temperature (TA)
DM54S189
DM74S189
MIN
MAX
4.5
4.75
5.5
-55
0
UNITS
5.25
V
V
+125
+70
°e
°c
electrical characteristics
over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
(Notes 2 and 3)
LIMITS
CONDITIONS
V'H
High Level Input Voltage
V'L
Low-Level Input Voltage
VOH
Hi~h·Level
VOL
Low Level Output Voltage
UNITS
TVP
MIN
MAX
V
2
0.8
. I 10H" -2.0 rnA, DM54S189
Output Voltage
Vee
=Min
I 10H =-6.5 rnA, DM74S189
.
Vee'" Mm, IOL
-=;
16 rnA
I
I
2.4
3.4
2.4
3.2
V
V
DM54S189
0.5
DM74S189
0.45
V
"H
High Level Input Current
Vee:::: Max, VI = 2.7
25
/lA
I,
High Level Input Current at Maximum Voltage
Vee = Max, VI = S.SV
1.0
rnA
I,L
Low Level Input Current
Vee =, Max, V r :::: O.4SV
los
Short Circuit Output Current (Note 4)
Vee = Max. Va:::: OV
Icc
Supply Current (Note 5)
Vee:::: Max
V'C
Input Clamp Voltage
Vee;::' Min, ') '" -1BmA
-1.2
V
IOZH
TRI-STATE Output Current, High Level Voltage
Vee'" Max, Vo .::: 2.4V
50
/lA
-50
)1A
-30
75
-250
/lA
-100
rnA
110
rnA
Applied
IOZl
TRI-STATE Output Current, Low Level Voltage
Vee = Max, Vo = O.45V
Applied
switching characteristics
over recommended operating ranges of
TA
and
V cc
(unless otherwise noted)
LIMITS
PARAMETER
CONDITIONS
DM54S189
MIN
DM74S189
TVP(l)
MAX
MIN
UNITS
TVP(l)
MAX
tAA
Access Times From Address
25
50
25
35
ns
tCZH
Output Enable Time to
12
25
12
17
ns
12
25
1?
17
ns
22
40
22
35
ns
22
40
22
35
ns
tezl
High Level
Access Times From
Output Enable Time to
Chip Enable
Low Level
tWZH
twZL
CL o30pF, RL
~280!1,
(Figure 1)
Output Enable Time to
High Level
Sense Recovery Times
Output Enable Time to
From ReadIWrite
Low Level
2-8
switching characteristics (con't)
LIMITS
PARAMETER
MIN
tcHZ
telZ
Output Disable Time
From High Level
Disable Times From
Output Disable Time
Chip Enable
From Low Level
'tWHZ
tWlZ
UNITS
DM74S189
DM54S189
CONDITIONS
TYPll1
MAX
25
12
17
ns
25
12
17
ns
TYP!1}
MAX
12
12
MIN
CL~5pF.RL~280n
(Figure 1)
Output Disable Time
F rom High Level
Disable Times From
Output Disable Time
Readi'Nrite
12
12
ns
12
12
ns
From,Low Level
"
twp
Width of Write-Enable Pulse (ReadIWrite Low)
25
25
tASW
Set· Up Time (Figure 1)
0
Address to ReadIWrite
0
tosw
Data to ReadIWrite
25
25
tcsw
Chip-Enable to
0
0
Address From Read/Write
0
0
tOHW
Data From Read/Write
0
0
tcHW
Chip-Enable From
0
0
ns
ns
Read/Write
tAHW
Hold Time (Figure 1)
ns
Read/VVrite
Note 1: "Absolute Maximum Ratings" are those values beyond' which the 'safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device,operation.
Note 2: Unless otherwise specified min/max' limits apply across the -55° C to +125°C temptarature range for the DM54S189 and across the 0° C to
+70 0 e range for the DM74S189. All typical, are given for Vec = 5,OV and T A = 25°C.
Note 3: AI'! currents into device pins shown as positive, out of device'pins as negative,'all voltages referenced,to ground lInle,ss otherwise noted. All
values shown as 'max or min on absolute value basis.
Note 4:, Only one output at a time should be shorted.
Note 5: ICC is measured with all inputs grounded, and the outputs open.
switching time waveforms
CHIP ENABLE
INPUT
(SEE NOTtJl
3V
,5V
OV
-1c"--1 1.
'*.T
'>1.5V
WAVEFORM 1
(SEE NOTE 1)
Voe
WAVEFORM 2
(SEE NOTE·ll
tcLz
;¥--f.v
---I
"'1.!iV
c--
7~
-Ic"~
VO"
ADDRESS
INPUTS
/-<5V
'-,-,-
~
Ov--~r--
1,-",. 3V
O.liV
I
-I
DATA
INPUTS
C~IP-ENABLE
:-T
INPUT
tCHZ
3V------...
Enable and Disable Time From Chip Enable
HEAOIWt:l.lTE
INPUT
ADDRESS
INPUTS
(NDTE 2)
OV - - -"
DUTPUl
::~
,
~
,
_-'I
(NOTE 1)
v"
WAVEFORM 2
(51 OPEN,
52 CLOSED]
(NOTE 1)
/':5V
Access Time From Address Inputs
1--__ '""
I
----+--..L-r'.'r . I
v"" _ _--..,;..f----.,:'"::;,..,.,:.....
1.
"_'~o~
.w _ _ _ _ _ _ _ _ _
__t
__+-...::::::......;.
"~/fii:sv
WAvefORM 1
'-'::-4=
_ _ _ _ _-'-c-_ _ __ _'_'.':5V
/~liV
LSV
DV------'-j--'
. lOV ------+-.:::c~--l--~
,
1.5V'
~'A' =:j,"
r-""'i __ ' " "
3V~;-- _ _ --"""-",~
_ _ ,.,.."l",,!iV
1.!iV
OV----~--_+----~------~--;
I-- .. 'w",
~~._l-
-
___
O.!iV
--"1
)(r
~
~
Write Cycle
FIGURE 1
Note 1; Waveform 1 is fO.r the output with internal conditions such that the output is low exce'pt when disabled, Waveform 2 is for the output
with internal conqitions such that the output is high except when disabled.
Note,2. When measuring delay times from address inputs, the chip enable input is low and the read/~rite input is high.
Not8 3: When measuring delay times from chip enable input, the address inputs 'are steady-state arid the read/write input is high.
Note 4: Input waveforms are supplied by pulse gen'erators having the follOwing characteristics: tr ~ 2.5 ns, If ::S. 2.5 ns, PRR :S 1 MHz, and
ZOUT ~ 50n.
2-9
block diagram
ac test circuit
V"
ADDRES'
INPUTS l: "
14
C
o
ADDRESS
BUFFERS
64·Bll MEMORY
MATRIX
ORGANIZED
16x4
1 OF 16
DECODERS
TEST
POINT
R,
FROM
OUTPUT
1J
UNOfA
TEST
C,
!Ok
CHIP ENABLE (EE)
R,EADIWRIlE IRtW!
r
-::Ct Includes probe and tlg eaPil~ltillI(:e
ArldiolWsalelN30&4.
02
DATA INPUTS
03
0'
"
,V,
V2
V3
"
V4,
OUTPUTS
2-10
~National
Bipolar RAMs
~ Semiconductor
c
3:
UI
~
C/)
N
o
o
......
c
DM54S200/DM74S200256-bitraad/write schottky
memories with TRI-STATE® outputs
3:
~
C/)
N
general description
The DM54S200/DM74S200 256-bit active-element
memories are monolithic transistor-transistorlogic
(TTL) integrated circuits organized as 256 words
of one bit each. They are fully decoded and have
three gated memory·enable inputs to simplify
decoding required to achieve the desired system
organization. The memories feature PNP input
transistors which reduce the low-level input current
requirement to a maximum of -0.25 milliamperes,
only one-eighth that of a normalized Series 54S1
74S load factor. The memory-enable circuitry is
implemented with minimal delay times to compensate for added system decoding.
be driven by another active output or a passive
pull-up if desired.
Read Cycle: Thestored information (complement
of information applied at the data input during
the write cycle} is aVailable at th'e output when the
write-enable input is high and the three memoryenable inputs are low. When anyone of the
memory enable inputs is high, the output will be
in the high~impedance state.
features
The TRI-STATE output combines the convenience
of an open-collector with the speed of a totempole output; it can be bus-connected to other
similar outputs, yet it retains the. fast-rise-time
characteristics of the TTL totem-pole output.
• Schottky-clamped for high-speed memory
systems:
Access from memory-enable inputs 20 ns typ
Access from address inputs
31 ns typ
Powe( dissipation
1.7 mW/bit typ
• TRI-STATE output for driving bus-organized
systems and/or highly capacitive loads
Write Cycle: The complement of the information
at the data input is written into the .selected
location when all memory-enable inputs and writeenable input are 10w .. While thewdte-enable input
is low, the output is in the high-impedance state.
When a number of outputs are bus·connected, this
high·impedance output state will neither load nor
drive the bus line, but it wi.1I allow the bus rine to
•
Fully decoded, organized as 256 words of one
bit each
• Compatible with most TTL and DTL logic
circuits
•
Multiple memory-enable inputs to minimize
external decoding
block and connection diagrams
OuaH "-Line and Flat Package
A[]ORESS
IIIIPUTS
ADDRESS
ME,
!"
G
1101
ADQRES!>
INPUTS
F
~
. E (9)
o
,
ME,
INPUTS
(J)
' -.....- .....-<~ ......- ....-<~.....+;~;>O'i;7.;~6~TPUT
,
2·11
0
OuTPUT ADDRESS
AODR~SS
1NPUT
rOPVIEW
Order Number DM54S20OJ
or DM74S200J
See Package 10
Order Number DM74S200N
See Package 15
Order Number DM54S200W
Or DM74S200W
See Package 28
o
o
o
o
C'II
en
~
::i!!
Q
.......
o
o
C'II
en
absolute maximum ratings
operating conditions
(Note 1)
Supply Voltage, VCC
Input Voltage
Output Voltage
7.0V
5.5V
5.5V
Storage Temperature Range
-jJ5' C to +150' C
Lead Temperature (Soldering, 10 seconds)
300'C
Supply Voltage (VCC)
DM54S200
DM74S200
Temperature (TAl
DM54S200
DM74S200
'lit
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
+70
'c
°c
Lt)
:t
Q
recommended operating conditions
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
-2.0
-5.2
rnA
rnA
,16
rnA
High Level Output Current '(lOH)
DM54S200
DM74S200
Low Level Output Current' (loLl
Width of Write Enable Pulse (tw I
ns
50
40
DM54S200
DM74S200
Setup Time (tSETUP)
Address to Write Enable
Data to Write Enable
ns
0
0
0
ns
Address from Write Enable
Data from Write Enable
10
10
Memory Enable from 'Write Enable
0
ns
ns
ns
Memory Enable to Write Enable
ns
ns
Hold'Time (tHOLD)
electrical characteristics
PARAMETER
(Note 2)
CONDITIONS
MIN
High Level Input Voltage (V'HI
TYP
~18
Input Clamp Voltage (V,I
Vee::::: Min, 11 =
High Level Output Voltage (V OH I
Vee = Min, V'H = 2.0V,
V 1L ='O.8V, IOH := Max
-1.2
rnA
Vee::::: Min, V 1H = 2.0V
V 1L
: : : Q,SV, '01.. : : : Max
Off State (High Impedance Statel
Output Current (lO(OFF))
Vee = Max, V'H = 2.0V
Vo = 2.4V
Vo = 0.5V
Input Current at Maximum Input
Voltage (1,1
Vee = Max, V, = 5.5V
High Level Input Current (lIH)
Low Leve! Input Current (IlL)
Short Circuit Output Current (los)
(Note 31
Vee = Max
Supply Current (Icc I
V ce = Max (Note 51
UNITS
V
0.8
Low Level Input Voltage (V'LI
Low Level Output Voltage (VOL I
MAX
2.0
V
V
V
2.4
0.5
0.45
DM54S200
DM74S200
50
-50
V
IlA
IlA
1.0
rnA
Vee = Max, V, =2.7V
25
IlA
Vee = Max, V, = O.5V
-250
f.l.A
-100
rnA
130
rnA
-30
2·12
87
o
switching characteristics All Typic~1 Values.are at Vce ~ 5.0V, T A ; 25°C.
SYMBOL
PARAMETER
CONDITIONS
PARAMETER
Propagation Delay Time,
tpLH
Low to High Level Output
TEST
CONDITIONS
Access Time. from
Address
33
High to Low Level Output
Output Enable Time to
Access Times from
High Level
Memory Enable
C L =30pF,
tZL
Output Enable Time to
Low Level
Access Times from
Memory Enable
RL = 300n
tZH
Output
MAX
70
33
50
ns
29
70
29
50
os
21
45
21
35
ns
10
30
10
20
ns
24
50
24
40
ns
Output Enable Time to
Sense Recovery Times
from Write Enable
12
50
12
40
ns
Disable Times from
Memory Enable
7.0
30
7.0
20
ns
20
45
20
35
ns
13
40
13
30
ns
16
40
16
30
ns
Output Disable Time from
High Level
Output Disable Time from
Low Level
Disable Times from
Memory Enable
C L = 5.0 pF
tHZ
Output Disable Time from
High Level
Disable Times from
Write Enabl,e
RL = 300n
tLZ
Output Disable Time from
Lo'w Level
Disable Times from
Write Enable
tLZ
TYP
MIN
Sense Recovery Times
from Write Enable
Low Level
tHZ
MIN
Time to
High,Level
tZL
UNITS
MAX
tZH
~nable
DM74S200
TYP
Access Time from
Address
Propagation Delay Time,
tpHL
DM54S200
3:
U'I
,J:o.
(Note 2)
Note 1: "Absolute Maximum Ratings" are those values beyo'nd which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range'" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides cond:itions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55D C to +125°C temperature range for DM54S200 and
across the aOc to +70°C range for the DM74S200. All typicals are given for VCC = S.OV and TA = +2SoC.
Note 3: Duration of the short-circuit should not exceed one second.
Note 4: All voltage values are with respect to network grou,nd terminal.
Note 5: ICC is measured with the write enable and memory enable inputs grounded, all other inputs at 4.SV, and the output
open.
truth table
ac test circuit
INPUTS
FUNCTION
OUTPUT
MEMORY
ENABLEt
WRITE
ENABLE
L
L
High Impedance
Read
L
H
Stored Data
Inhibit
H
X
High Impedance
Write (Store
Complement
of Data)
H
hlgh,level, L" low level" X "'·'irrelevant
tFor memory enabl",: L" i'lll ME Inputs low;
Cl INClUIlES PROBE AND JIG CAPACITANCE
All DIOOESARE lN301i4
H - one or more ME i("lputs higtl
2-13
o
N
o
o
.......
o
3:
~
o
N
o
o
o
o
N
(J)
switching time waveforms
;:t
~
C
.......
o
o
N
,,'RESS
INPUT
"EEN",,"
m=f---,::-..J . . '1
"'\~
1 5V
15V
J.IIV
ADDRESS
-_
--
~e:--t
INPUTS
l,IIV
OUTPUT
\ . 5V
f.5V
vo, - - -
(J)
.q.
It)
J.IIV
MEMORY
~
C
ENABLE
INPUTS
MEMORY ENABLE
lNI'UTS (SEE 1II0TE C)
WRITE
3.GV
ENABLE
INPut
"' _---j_'-_ _ _ _ _ _.-J
WAVEFDRM 1
{SEE NOTE A)
WAVHORM2
(SEE NOTE M
NOTE A: WAVEfORM liS FOR THE OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE
OUTPUT 'SLOW EXCEPT WHEN DISABLED. WAVEfORM 2 IS FDA THE OUll'UTWITH INTERNAL
CDNOITlONSSUCH THAT THE OUTPUT IS HIGH EXCEPT WHEN DISABLED.
NOTE 8: WHEN MEASURING OElAY TtMES FROM ADDRESS INPUTS, THE MEMORY ENABLE
INPUTS ARE LOW AND THE WRITE ENABLE INPUT IS HIGH
NOTE C: WHEN MEASliRING DElAY TIMES fROM MEMORY ENABLE INPUTS, THE ADDRESS
INPUTS ARE STEAOY-STATE AND THE WRITE ENABlE INPUT IS HIGH
N(lTE D: INPUT WAVEfORMS ARE SUPPLIED BY PULSE GENERATORS HAVING THE FOllOWING
CHARACTERISTICS: t, ~ 2_S ns, II ._ 2.5 "$, PRR ~ 1.0 MI:Il, ANO lOUT ~ 50~~
2-14
.
~ Semiconductor
~National
Bipolar RAMs
OM54S206/0M74S206 256-bit read/write schottky
memories with open-collector outputs
general description
The DM54S206!DM74S206 256-bit active-element memories are manalithic transistar-trar:lsistar lagic (TTL)
integratec:l circuits arganized as 256 wards af ane bit
each_ They .are fully decaded and have three gated
memory-enable inputs to. simplify decoding required to.
achieve· the desired system organization_ The memories
feature PNP input transistors which· reduce the lowlevel input current requirement to a maximum of
-Q_25 milliamperes, only orie-eighth that of a narmalized Series 545/745 load factar_ The memoryenable circuitry is implemented with minimal delay
times to. compensate for added system decoding.
Read Cycle: The stored information (complement of
infarmatian applied at the data input during the write
cycle) is available. at the output when the write-enable
input is. high and the three memory-enable inputs are
low. When anyone of the memory enable inputs is
high, the output will be off.
features
• Schattky-clamped for high-speed memory systems:
Access from memary-enable inputs
17 ns typ
Access fram address inputs
35 ns typ
Pawer dissipatian
1.4 mW!bit typ
• Open-collector output far word expansio'1
• Fully decoded. arganized as 256 words af one bit
each
• Compatible with most TTL and DTL logic circuits
• Multiple memory-enable inputs to minimize external
decoding
Write Cycle: The camplement af the information at
the data input is written into the selected la.catian
when all memary-enable inputs and write-enable input
are low. While the write-enable input is low. the out·
put is off.
block and connection diagrams
Dual-In-line and Flat Package
...
'.
~
ME,
ME,
ME3
ADDRESS
INPUTS
OU~PUT ADD~ESS
GND
INPUT
TOP VIEW
Ordar Number OM54S206J Dr DM74S206J
SeePack_'0
Ordar Number DM74S206N
Se8 Pacicage 15
Order Number DM54S206W ·or DM74S206W
See Package 28
2-15
absolute maximum r:atings
Supply Voltage, Vee
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
operating conditions
(Note 1)
Supply Voltage (Veel
DM54S206
DM74S206
7.0V
5.5V
5.5V
-65°e to +150o e
300 0 e
Temperature (TAl
DM54S206
DM74S206
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
+125
+70
°e
-{is
0
a
e
operating conditions
PARAMETER
CONDITIONS
MIN
TYP
Low Level Output Current (lad
MAX
UNITS
16
mA
Widthof Write Enable Pulse (tw)
DM54S206
OM 74S206
50
40
ns
Setup Time (tSETUP)
Address to Write Enable
Data to Write Enable
Memory Enable to Write Enable
0
0
0
ns
ns
ns
Hold Time (tHOLO)
Address from Write Enable
Data from Write Enable
Memory Enable from Write Enable
10
10
0
ns
ns
ns
electrica.1 characteristics
ns
(Note 2)
PARAMETER
CONDITIONS
High-Level Input Voltage (V ,H )
MIN
TYP
MAX
2
V
Low-Level Input Voltage (V,d
0.8
V
-1.2
V
/lA
/lA
Input clamp voltage
Vee = Min, I, = -18 mA
High-Level Output Current (loHI
Vce= Min, V'H = 2V, V ,L = O.BV
V OH = 2.4V
V OH = 5.5V
40
Vee = Min, V ,H = 2V, V ,L = 0.8V,
IOL = Max
0.5
0.45
Low-Level Output Voltage (Vod
OM54S206
DM74S206
UNITS
100
V
Input Current at Maximum Input Voltage (I,)
Vee = Max, V, = 5.5V
1
mA
High-Level Input Current (I'H)
Vee = Max, V, = 2.7V
25
/lA
Low-Level Input Current (I,d
Vee = Max, V, = 0.5V
-250
/lA
S~pply Current (leel
Vee = Max, Note 2
130
mA
2-16
70
switching characteristics
All typical values are at Vce
=5.0V, T A =25°C.
(Note 2)
LIMITS
PARAMETER
CONDITIONS
DM74S206
DM54S206
TYP
MAX
Access Times from Address (tPLH)
38
Access Times from Address (tPHd
,32
21
MIN
Disable Time from Memory Enable (tPLH)
Enable Time from Memory Enable (tPHL)
CL = 30 pF, RL = 300n
MIN
UNITS
TYP
MAX
80
38
60
ns
80
32
60
ns
45
21
35
ns
13
35
13
25
ns
Disable Time from Write Enable (tPLH )
20
50
20
40
ns
Sense·Recovery Time (tSR )
14
50
14
40
ns
Note 1: "Absolute Maximum Ratings" are those values beyond,which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are 'not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides con-ditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -5SoC to +12SoC temperature range for DM54S206 and across the oOe to
+70o erange for the DM74S206. All typical. are given for Vee" 5..0V and TA ~ +25°e.
Note 3: All voltage values are with respect to network ground terminal.
Note 4: ICC is measured with the write enable and memory enable inpiJts grounded, all other inputs at 4.5V. and the output open.
truth table
ae test circuit
INPUTS
FUNCTION
MEMORY
ENABLEt
WRITE
ENABLE
OUTPUT
Write IStore
Complement
L
L
H
Read
L
H
Stored Data
Inhibit
H
X
H
of Data)
H ., high level, L '" low level, X '" irrelevant
tFor memory enable. L '" all ME inputs lOW:
H '" one or more ME. inputs high.
CL includes probe ilnd jig capacitance.
2·17
switching time waveforms
Write.cycle
ADDRESS JV
INPUTS OV __ -"
l:P~~~
:-i'SETUP
. ~;
'--t----+-'
JV
OV __ J
:1ISETUP
JV
Access (Enable) Time and Disable Time from Memory Enable
Access Time from Address I "puts
MEMORY3V~
EI~~~~~
1.5V,
UV
(NOTE!:) OV
~
tPHl.,r
DUTI>UT
(NOTE,A)
VOH---'---~V
ADDRESS
INPUTS
uv
A'
B;
C;
0:
UV'
OUTPUT V
VOl-------''-------.J.
Note
Note
Note
Note
JV~'
r------~
)j(1.5V
(NOTER) OV--'/'PHL::1
tPlfl
OH
VOL
--'---.-
.
~.5V
.
Wavefor/11 shown is for the output with internal conditions slJch that the output is low except when disabled.
WheJl measuring delay times from addles; inputs, the memory-enable inputs are low and the write~nable input is high.
Whell measuring delilY times from memory·enable inputs, the address inputs are steady·state and the write-enable input is Iligh.
Input Wilveforms are supplied by plllse generators having the following tharactelistics: t,'" 2.5 ns, tt": 2.5 ns, PRR "- 1 MHz, and
2-18
'
:..j'-;p:-F-=:"
Y,.5V
•
lOUT "" 5D~·1.
.
Semiconductor
~National
_
DM54LS28.9/DM74LS289 low power 64-bit
ran.dom .access memories with open-collector outputs
general description
These 54-bit active-element memories are monolithic
Schottky·cl~mped transistor-tr~nsistor logic (TTL) arrays
organized as 16 words of 4 bits ea<;h.They are fully
decoded and feature a chip enable input to simplify
decoding required to achieve the desired system organi·
zation. This. device is implemented with low· power
Schottky technology resulting in one·fifth power .while
retaining the·speed of.standard TTL.
input are low. While the read/write input is low, the
outpu.ts are in the high-logic level (OFF).
Read Cycle: The ~stored information (complement of
information applied at the data inputs during the write
cycle) is avaHable at the· outputs when the read/write
input is high and the chip.enable·is low. When the chipena!;lle input is high, the outputs are high (OF F).
.features
The open-collector outputs are ideal for controlled·
impedanCe bus lines.
• Schottky-clamped for high speed applications
. Access from chip enable. input-40 nstyp
Access from address inputs--60 ns typ
• Open-collector outputs for controlled·impedance
bus lines
• DM54LS189/DM74LS189 are functionally equivalent,
but have TRI-STArE@ outputs
• DM54LS289 is guaranteed for operation over the full
military temperature range of -55°C to+125°C
... Compatible with most TTL and DTt logic circuits
• Chip enable input simplifies system decoding
The unique functional capability of the DM54LS289
outputs being at a high during writing combined with
the data inputs being inhibited during reading means
that both data inputs and outpu.ts can be connected to
the data lines of a bus·organized system without the
need.for interface circuits.
Write. Cycle: The c0rT\plement of the information at
the data input is wdtten into the selected. location
when both the chip·enable input and the read/write
connection diagram
truth table
Dual-in·Line and Flat Package
SELEn I~PUTS
fa
Vec
1,.
o'
"
DA1'A
INPUT
4
13
14
DATA
lNPUT
J
OUTtiur
V4
12
OUTPUT
V3
•
I.
11
INPUTS
,..
FUNCTION
CHIP
ENABLE
READ!
WRITE
OUTPUT
Write
l
l
H
Read
l
H
Stored Data
Inhibit
H
X
H
~
(Store Complement of Data)
1
SELECT
2
CHIP
INPUT A ENABLE
•
3
5
READI
DATA
OUTPUT
WRITE
INPUT
VI
1
8
DATA
INPUT
2
1
OUTPUT
VI
J8
GND
H = high level
L = low level
X = don't care
TOP VIEW
Order Number DM54LS289J
or DM74LS289J
sa. Padt<~---~~
N..,I:
~mllSt,",brou"'I"'ighftutr.lE
"utIIZ:
t,·lt~ZOmforllljltflllb.
3-11
~':j8
Vee
9.1 Vee
DATA OUT
_ _ ndl _ _ nevuyaddrM$ehtnp.
D
- ' - - TRISTATE
~National
CMOS RAMs
~ Semiconductor
MM54C920/MM74C920, MM54C921/MM74C921
1024-Bit Static Silicon Gate CMOS RAMs
General Description
these RAMs ideal elements for use in microproCeSsor,
minicomputer as well as main frame memory applications.
The M1iII54C920/MM74C920 256 x 4 random access
read/write memory is manufactured using silicon gate
CMOS technology. Data output is the same polarity as
data input. Internal latches store address inputs. CES
and data output. This RAM is specifically designed to
operate from standard 54/74 TTL power supplies.
All inputs and outputs are TTL compatible.
Features
•
256 x 4-bit organization
•
Access time
250 ns max MM74C920, MM74C921
275 ns max MM54C920, MM54C921
300 ns max MM74C920-1, MM74C921-3
The MM54C921/MM74C921 is identical to the
MM54C920/MM74C920, except data inputs are inter·
nally connected to data outputs; the number of package
leads thereby is reduced to 18.
• TRI·STATE outputs
Complete address decoding as well as 2-chip select
functions, eEL and CES, and TRI·STATE® outputs
allow easy expansion with a minimum of extl!rnal com·
ponents. Versatility plus high speed and low power make
• low power
• On-chip registers
• Single 5V supply
• Data retained with VCC as low as 2V
Connection Diagrams
Logic Symbols
Dual-In· Line Package
Dual· In· Line Package
Z2
AJ
Vee
18
A3
A2
21 A4
Al
20 __
WE
19
AD
m
15
AO
A'
MM54C!121/
MM74C921
MM54C9201
MM74C921I
17
A.
A2
WE
A'
A.
m
I. Sf
12
Al 1
A'
DD>
A5
MMi4C920J
AS
MM74C92D
A6
DD3
DD4
to
01/01 9
DD4
014
0I{02
fi'
DD3
011
001 10
wI
C!f
m
TOP VIEW
013
11
12 002
TOP VIEW
Ordering Information
MILITARY
MM54C920,
MM54C921
01/02
A'
A.
A'
Al
'"
01104
1'01/03
GND 8
01/01
Al
01/03
01/04
A7
011
GND
012
AO
001
013
16
Al
m
AO
Al
13C!f
A' •
A6
vee
,,-
Al
IBSf
Ai
17
A2 2
COMMERCIAL
X
PACKAGE*
J,D
MM74C920,
MM74C921
X
N, J, 0
MM74C920-1,
MM74C921-3
X
N,J,D
*J and N package available mid-1977
3-12
Sf 1'1£ ffi
en
,
Absolute Maximum Ratings
S:~
Operating. Conditions
S:S:
UlUI
MIN
Supply Voltage (Vec)
MM54C920, MM54C921
4.5
MM74C920, MM74C921
4.5
MM74C920-1, MM74C921-3
4.75
Ambient Temperature (T A)
MM54C920, MM54C921
-55
MM74C920, MM74C921
-40
MM74C920-1. MM74C921-3
0
7V
Supply Voltage, VCC
Voltage at Any Pin
-o.3V to V CC + 0.3V
Storage Temperature Range
-65°C to +150°C
Power Dissipation
300°C
Lead Temperature (Soldering, 10 second,)
MAX
UNITS
5.5
5.5
5.25
V
V
V
+125
+85
+70
°c
°c
°c
~~
nn
(0(0
NN
.... 0
"S:s:
S:s:
........
~~
nn
ln:m777777m=+-I
o
85
25
125
TA (OC)
Dynamic Current vs Power
Supply Voltage (VIH = VCC.
VIL=OVI
Output Source Current YS
Output Voltage
-20
VCC' 5V
TA'25"C
i
~
2.5
.!
...
li'l
a:
'"
B
-17.5
V
,/
1.5
./
./'"
I I
-15
I I
-12.5
V
"
TA~
.! -10
:c
S' -7.5
V
>
~
••
-5
0.5
-2.5
o
o
3
4.5
3.5
5'
5.5
v:
~ P""
:;..
.....
i"""
I-""TA:~
TA -lZ5"C
I I
54.543.532.521.51
VCC(V)
VOUT (V)
Output Sink Current VI
Output Voltage
40
VCC' 5V
35
l-l-
TA' -55°C
3D
1
25
~
20
!E'
",.
/
1/
15
-
..... "'" 1
'/ /'
10
0.5
....
TA • 125°C
hV
II'
o
o
Test Limit MM54C920. MM54C921
TA:Z5'C
I
I
1
1.5
2
2.5
3
Test Limit MM74C920. MM74C921
3.5
4
VOUT (V)
3-18
CMOS RAMs
~National
~ Semiconductor
MM54C929/MM74C929, MM54C930/MM74C930
1024-Bit Static Silicon Gate CMOS RAMs
General Description
Features
The MM54C929/MM74C929 and the MM54C930/
MM74C930 1024 X 1 random access read/write memories
are manufactured using silicon gate CMOS technology.
These RAMs are specifically designed to opemte from
standard 54/74 TTL power supplies; all inputs and
outputs are TTL compatible. Data output is the same
polarity as. data input. Internal latches store the address
inputs and data output. Chip select input CSl serves
as a chip strobe, controlling address and data latching.
The Data·ln and Data·Out terminals can be tied together
for commonl/O applications. Complete address decoding,
3·chip select functions (MM54C930/MM74C930) and
TRI·STATE® output allow easy memory expansion and
organization. The MM54C929/MM74C929 differs from
the MM54C930/MM74C930 only in that CS1, CS2 and
CS3 are internally connected together, providing a single
chip·select input CS.
•
•
•
•
•
•
•
•
Fast access-250 ns max
TRI·STATE outputs
lowpower-l0 pA max standby
On·chip registers
Single 5V supply
Inputs and output TTL compatible
Data retained with VCC as low as 2V
Can be operated common I/O
Functional Description
Address inputs are clocked into the input latches by the
falling edge of chip strobe CS1; set·up and hold times
must be observed on these input signals (see timing dia·
gram). The true and complement address information is
fed to the row and column ·decoders which select one of
the 1024·bit locations. The addressed bit is fed, via a
sense amplifier, to the output register and TRI·STATE
buffer. The information is latched into the output
register on the rising edge of chip strobe CS1. The out·
put is in a high impedance state when the chip is not
selected (CS2 or CS3 high) or when writing (WE low).
Output buffer control is independent of chip strobe CS1.
Versatility, high speed, and low power make these RAMs
ideal elements for use in many microprocessor mini·
computer and main frame memory applications.
Block and Connection Diagrams
AD
AI
.2
A3
A4
01--..,...."-+----1>1
00
CSI
(STROBEl
FIGURE 1
Dual-ln'·Line Package
Dual-In-line Package
vee
DI
We
AS
Aft
Al
AB
lD24X 1
At
A2
AJ
A4
ES3
DI
Order Number MM54C929D or MM74C929D
See Package 3A
Order Number MM74C929N
See Package 15
Order Number MM54C9300 or MM74C930D
See Package 4
Order Number MM74C930N
See Package 16
MM54C9Z9/MM74C929
CS
Vee
A5
DO
3·19
A9
AB
.7
A.
A5
A4
00
6NO
MM54C930iMM14C930
11124 x 1
CS2
(iNO
WE
CST
AD
AI
A2
A3
Absolute Maximum Ratings
Supply Voltage, Vee
Voltage at Any Pin
Storage Temperature Range
7V
-Q.3V to Vee + 0.3V
-65"e to +150o e
Operating Temperature Range
MM54C929, MM54C930
MM74e929, MM74C930
MM74C929-3, MM74C930-3
-55°e to +125°e
-400 e to +85° e
oOe to +700e
DC Electrical Characteristics
=Operating Range, unless otherwise noted
MM54e929,
MM54e930
CONDITIONS
PARAMETER
SYMBOL
Vee = 5V ± 10%, T A
MAX
Vec-2.O
Vee
Vec-2•O
Vee
Vec-2:O
0
O.B
a
O.B
a
Logical "I" Input Voltage
VIL
Logical
VOHI
logical "I" Output Voltage
10H
VOH2
logical "I" Output Voltage
IOUT~O
Logical
10L =2.0mA
VOL2
"a" Output Voltage
logical "a" Output Voltage
IlL
I nput Leakage
OV:5 VIN:5 Vec
-1.0
10
Output Leakage
OV:5 Vo:5 Vee, eEL = Vee
-1.0
ICC
Supply Leakage Current
VIN = VCC, Vo
VOR
Vce for Data Retention
(Note 2)
lOR
ICC for Data Retention
Vee = 2V, (Note 2)
VOLI
MM74C930-3
MIN
VIH
"a" Input Voltage
~
MM74C929-3,
MM74C929,
MM74C930
MAX
MIN
MIN
2.4
2.4
Vec-O· 1
Vec-O· 1
om
IOUT=O
= OV
0.4
0.01
1.0
-1.0
1.0
-1.0
2.0
V
0.01
V
1.0
-1.0
1.0
jJ.A
1.0
-1.0
1.0
jJ.A
100
jJ.A
10
20
V
V
V
0.4
0.4
Vee
O.B
V
2.4
Vec-O·01
1 rnA
UNITS
MAX
2.0
2.0
V
jJ.A
Note 1: Vec=5V±5%.
Note 2: ~or ~ orCS= Vce - 2V or = 2V, whichever is greater.
AC Electrical Characteristics
Vee = 5V ±10%, TA = Operating Range
TTL Interface tvlH = Vee - 2V, VIL = O.BV,lnput tRISE = tFALl = 5 ns, load
SYMBOL
MM54e929,
MM54C930
PARAMETER
MIN
MAX
290
=1 TTL Gate + 50 pF)
MM74C929-3,
MM74C929,
MM74C930-3
MM74C930
MIN
MAX
MIN
255
330
UNITS
MAX
ns
te
Cycle Time
tAee
Access Time From Address
265
240
315
ns
tAcs,tAesl
Access Time From CS, ~
250
225
300
ns
tAS
Address Set-Up Time
15
15
15
ns
tAH
Address Hold Time
50
50
50
ns
toE
Output Enable Time
150
130
130
ns
too
Output Disable Time
150
130
130
ns
tC§,tesl
(Note 3)
CS, CSI Pulse Width (Negative)
150
130
165
ns
tCS,tCSl
CS, CSI Pulse Width (Positive)
140
125
165
ns
!WP
Write Pulse Width (Negative)
150
130
165
ns
tDS
Data Set-Up Time,(Note 4)
150
140
140
ns
tDH
Data Hold Time, (Note 4)
a
0
0
ns
Note 3: Greater than minimum CS pulse width must be used when reading data from the MM54C929/MM74C929 to ensure that output TRISTATI NG does not occur before data becomes valid. Writing has no such limitation.
Note 4: tos and tDH are reference._-----
MM54C929/MM74C929
I
)
!{
J
\c
DOUT -
-
-TRI-STATE®- -
--,
, ------
-100-
-tOE-
DATA OUT VALID
MM54C930IMM74C930
FIGURE 4_ Output Enable/Disable
3-22
J
Typical Performance Characteristics
o.
AcCess Time vs Ambient
Access Time vs Power Supply
Tem,perature
Voltage
400
Minimum Write Pulse Width
YS, Ambient Temperature
200
300
TA"25'C
250
300
ca
g
::.'"'"
150
:g
200
~
200
'\
150
........
100
]: 100
t'-..
100
are
Iran
rta
~
r-- t -
50
o
25
85
3
125
3.5
4.5
TA I'CI
VCC
5.5
125
(vi
In (
Minimum CSI Pulse Width
renl
Data-In Set-Up Time vs
Ambient Temperature
ligl
ew
I ir
(Positive),vs Ambient
Temperature
Ambient Temperature
200
; nc
!Iy
Data-In Hold Time vs
25
rr,---,--r-----r---n
200 rrT~T'"-r----"'-r---T1
150
g
~
g
100
~
Q
d I
ctic
50
~
··25
Xl
-50
-15
-55-40
25
85
-55-40
125
gr
Address Hold Time vs
Ambient Temperature
JUTP,
IUFFE
25
~
::."
85
-55-40
125
TA('CI
TA rCI
Address Set-Up Time vs
Ambient Temperature
30
200
60
20
150
'"
~
!w
10
125
100
Q
20
50
-10
25
85
125
,-",==="""""-"=="",,,"",,O-J
-55-40
85
125
-55_40
TA I"CI
25
TA rCI
Minimum CS1 Pulse Width
(Negative) vs Ambient
Temperature
ami
AI
85
Output Enable Time vs
Ambient Temperature
80
4D
25
TA ('C)
200
Test L.imit MM54C929, MM54C930
rr,---,--,-----,---,-
C~
D,
Test Limit MM74C929, MM74C930
50
-55-40
85
125
se
170
alll
3-23
85
12'3
m
Typical Performance Char
Dynamic Current vs Power
SupplV Voltage
(VIH = Vee, VIL = OV)
TA " 25"e
%:
2.5
~
«
.§
~~
V
./
1.5
,/
fl
i
••
~
V
absolute maximum ratings
(Note 1)
Ambient Temperature
Storage Temperature
Power Dissipation
Read Operation
Input Voltages and Supply Voltages with
Respect to V cc
Program Operation
Input Voltages and Supply Voltages with
Respect to Vee
Lead Temperature (Soldering, 10 seconds)
O°C to +70°C
-65°C to +125°C
2W
+0.5V to -20V
-48V
0.5
o
3
3.5
4.5
Vee IVI
read operation dc characteristics
T A = O°c to +70°C, V cc = +5V ±5%, V DO = -9V ±5%, V GG = -9V ±5%, ur
voltages and T A = 25° C. (Note 2)
PARAMETER
ILl
Address and Chip Select
CONDITIONS
V 1N = O.OV
Input Load Current
I LO
Output Leakage Current
V OUT = O.OV, CS = V ce -2
1000
Power Supply Current
VGG = Vee, CS = V ec -2
10L = 0.0 mA, T A = 25°C,
(Note 2)
1001
Power Supply Current
CS
= Vee -2, 10L = 0.0 mA,
T A =25°C
= 0.0, 10L = 0.0 mA, T A = 25°C
1002
Power Supply Current
CS
1003
Power Supply Current
CS = Vee -2, 10L
-
= 0.0 rnA,
T A = O°C
= -1.0V, T A = O°c
ICF1
Output Clamp Current
V OUT
ICF2
Output Clamp Current
V OUT =-1.0, TA
IGG
Gate Supply Current
V 1L1
= 25°C
I nput Low Voltage for
TTL Interface
V 1L2
Input Low Voltage for
MOS Interface
V 1H
Address and Chip
Select Input High
Voltage
IOL
Output Sink Current
V OUT
= 0.45V
IOH
Output Source Current
V OUT = O.OV
VOL
Output Low Voltage
IOL = 1.6 mA
V OH
Output High Voltage
IOH
= - lOOI1A
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause pel
and functional operation of the device at these or at any other condition above tho~
not implied. Exposure to Absolute Maximum Rating conditions for extended period
Note 2: Power-Down Option: VGG may be clocked to reduce power dissipation. TI
on the VGG duty cycle (see typical characteristics). For this option, please specify MIV
4·2
CMOS RAMs·
~National
~ Semiconductor
MM54C929/MM74C929, MM54C930/MM74C930
1024-Bit Static Silicon Gate CMOS RAMs
General Description
Features
The MM54C929/MM74C929 and the MM54C930/
MM74C930 1024 x. 1 random access read/write memories
are manufactured using silicon gate CMOS technology.
These RAMs. are specifically designed to operate from
standard 54/74 TTL power supplies; all inputs arid
outputs are TTL compatible. Data output is the same
polarity as. data inpl)t. Internal latches store the address
inputs and data outpUt. Chip select input CS1· serves
as a chip strobe, controlling address and data latching.
The Data·ln and Data·Out terminals can be tied together
for common I/O applications. Complete address decoding,
3·chip select functions (MM54C930/MM74C930) and
TRI·STATE@output allow easy memory expansion and
organizatiCln.The MM54C929/MM74C929 differs from
the MM54C930/MM74C930 only in that CS1 ,CS2 and
CS3. are internally connected together, providing a single
chip·select input CS.
•
•
•
•
•
•
•
•
Fast access-250 ns max
TRI·STATE outputs
Low power-1O.!lA max standby
On·ch ip registers
Single 5V supply
Inputs and output TTL compatible
Data retained with VCC as low as 2V
Can be operated common .1/0
Functional Description
Address inputs are clocked into the input latches by the
falling edge of chip strobe CS1; set·up and hold times
must be observed on these input signals (see timing dia,
gram). The true and complement address information is
fed to the row and column decoders which select one of
the .1024·bit locations. The addressed bit is fed, via a
sense amplifier, to the output register and TRI·STATE
buffer. The information is latched into the output
register on the rising edge of chip strobe CS1. The out·
put is in a high impedance state when the chip is not
selected (CS2 or CS3 high) or when writing (WE low).
Output buffer control is independent of chip strobe CS1.
Versatility, high speed, and low power make these RAMs
ideal elements for use in many microprocessor mini·
computer and main frame memory applications.
Block and Connection Diagrams
AD
A1
A2
A3
A4
01----+----+1
DO
CSl
(STROBE)
CSl-DoO--..........,r"\
FIGURE 1·
Dual·ln-line Package
Dual·ln·Line Package
Vee
OJ
WE
A!l
All:
A7
A6
vee
A5
csj
01
WE
A'
AS
A7
AS
A5
10
Order Number MM54C929D or MM74C929D
See Package 3,11.
Order Number MM74C929N
See Package 15
Order Number MM54C930D or MM74C930D
See Package 4
Order Number MM74C930N
See Package 16
MM54C9291MM14C929
lD24X 1
B
AD
A2
A3
A4
DO
MM!i41;930/MM74C931t
11124 x 1
m
GND
3·19
fSi
AO
AI
A2
AJ
A4
DO
GNO
Absolute Maximum Ratings
Supply Voltage, Vce
Voltage at Any Pin·
Storage Temperature Range
Operating Temperature Range
MM54C929, MM54C930
MM74C929, MM74C930
MM74C929-3, MM74C930-3
7V
-o.3V to Vce + 0.3V
-a5°e to +150°C
-5SoC to +125°.C
-400 C to +85· C
O°C to +70·C
DC Electrical Characteristics
PARAMETER
SYMBOL
Vee" 5V ±10%, TA" Operating Range, unless otherwise noted
CONDITIONS
MM54C929,
MM74C929,
MM74C929·3,
MM64C930
MAX
MIN
MM74C930
MM74C93Q.3
MIN
MAX
MIN
Vec-2:O
VIH
logical "1" Input Voltage
Vec-2.O
Vce
Vec-2.O
Vee
VIL
logical "0" Input Voltage
0
0.8
0
0.8
VOHI
logical "I" Output Voltage
10H= 1 rnA
VOH2
logical "1" Output Voltage
10UT=0
VOLI
logical "0" Output Voltage
10l = 2.0 mA
2.4
2.4
Vec-O.D1
Vec-O· 1
0.4
VOl2
logical "0" Output Voltage
10UT=0
III
Input leakage
OV~VIN~Vee
-1.0
10
Output Leakage
OV~Vo~Vee.m=Vee
-1.0
ICC
Supply Leakage Current
VIN = Vee. Vo = OV
VDR
Vee for Data Retention
(Note 2)
lOR
ICC for Data Retention
VCC= 2V, (Note 2)
0
-1.0
1.0
-1.0
20
V
V
0.4
0.01
1.0
-1.0
1.0
-1.0
10
2.0
V
V
2.4
0.01
1.0
Vce
0.8
Vec-O·l
0.4
0.01
2.0
UNITS
MAX
V
V
1.0
IlA
1.0
IlA
100
IlA
V
2.0
I1A
Note 1: VCC = 5V ±5%.
Note 2: es2"or ~ or <:S" = Vee - 2V or = 2V, whichever is greater.
AC Electrical Characteristics
Vee" 5V ±lO%, T A'" Operating Range
TTL Interface (VIH = Vec - 2V, VIL m O.BV,lnput tRISE" tFALL = 5 ns, Load" 1 TTL Gate + 5DpF)
SYMBOL
PARAMETER
MM64C929,
MM74C929,
MM64C930
MAX
MIN
MM74C930
MIN
MAX
MIN
290
255
330
MM74C929-3,
MM74C930·3
UNITS
MAX
te
Cycle Time
tACC
Access Time From Address
265
240
315
ns
tACS,tACSl
Access Time From ~. CST
250
225
300
ns
tAS
Address Set·Up Time
15
15
15
ns
tAH
Address Hold Time
50
50
50
ns
toE
Output Enable Time
150
130
130
ns
too
Output Disable Time
150
130
130
ns
tcs,tes1
(Note 3)
es, CSI Pulse Width (Negative)
150
130
165
ns
tes,tesl
CS, eSl Pulse Width (Positive)
140
125
165
ns
twP
Write Pulse Width (Negative)
150
130
165
ns
tos
Data Set·Up Time,(Note 4)
150
140
140
ns
tOH
Data Hold Time, (Note 4)
0
0
0
ns
ns
Note 3: Greater than minimum CS pulse width must be used when reading data from the MM54C929/MM74C929 to ensure that output TRI·
STATING does not occur before data becomes valid. Writing has no such limitation.
Note 4: tos and tOH are reference._-----
3: 3:
3: 3:
Typical Performance Characteristics
Access Time vs Power Supply
Voltage
Acc:ess Time vs Ambient
Temperature
400
U1 U1
.j:lo .a::(") (")
Minimum Write Pulse Width
vs Ambient Temperature
200
300
CD CD
TA=25°C
WN
OCD
......
,
250
150
lOO
200
]
I:!
:!...
...
200
:f-
"
150
:f-
100
!
.........
~
100
}
3: 3:
3:3:
-.J .....
100
.a::-.a::-
-r-
(")(")
CD CD
50
50
»
25
85
3
125
l.5
5.5
4.5
0
Vee (V)
TAIOC)
Data·ln Set·Up Time vs
150
.9
.:.
~
!?
50
150
100
50
-15
0
Z5
85·
LL<=========
85
-55-40
lZ5
125
Z5
fA 1°C)
"
85
lZS
TAIOC)
Address Hold Time vs
Ambient Temperature
:!
WN
OCD
zoo
..
~ .-25
100
125
Minimum CSi Pulse Width
(Positive)vs Ambient
Tampersture
25 nr;-~;--'-----'---n
200
85
TA 1°C)
Data·ln Hold Time vs
Ambient Temperature
Ambient Temperature
!
25
Address Set·Up Tim. vs
Output Enable Time vs
Ambient Temperature
Ambient Temperature
80
lo nr;---T--,-----,---n
zoo
60
20
1++-+-+---1--+1
150
1
40
5
:f-
..
--:a
10
"100
!?
zo
50
0
25
85 .
o
125
TA·IOC)
25
85
125
-55-40
0
TAtOCI
TA
Minimum CS1 Pulse Width
(Negative) vs Ambient
Test Limit MM54C929, MM54C930
Temperature
200
..,..-r---,-....,---y--."
Test Limit MM74C929, MM74C930
3·23
25
85
rc)
125
DI
Typical Performance Characteristics
(Continued)
.
Dynamic Current vs Power
Output Sink Current VI
Output Source Current vs
Supply Voltage
(VIH = Vee. VIL = OVI
Output Voltage
Output Voltage
-20
TA=25°C
2.5
./
/
1.5
40
VCC' 5V
-17.5
V
I I
I I
-15
-12.5
V
1
V
~
/
o~
3
3.5
4.5
5.5
!
V I-' ~lr
oS'
15
".
-7.5
-2.5
o
T~.-J5°C
5
R"=2~OC
I.......: ~ ~~
4.5
4
]
2.5
VOUT(V)
Vee IV)
3-24
2
1.5
TA' 25°C
.......
/
20
/./
'/ /"
hV
10
.'TA'" 1Z5°C
tp'
I I
3.5
~
TA -125°C
~
L
TA ' _55°C
30
25
-10
-5
0.5
Vce' 5V
35
1
o
0.5
1
1.5
2
z.s
VOUT(V)
3
3.5
4
~National
MOS EPROMs
~ Semiconductor
MM1702A 2048-bit electrically programmable ROM
general description
The MM1702A is a 256 word by a-bit electrically
programmable ROM ideally suited for uses where fast
turn-around and pattern experimentation are important_
The MM1702A undergoes complete programming and
functional testing on each bit position prior to shipment,
thus insuring 100% programmability_
The MM1702A is fabricated with silicon gate technology_
This low threshold technology allows the design and
production of higher performance MaS circuits and
provides a higher functional density on a monolithic
chip than conventional MaS technologies_
The MM1702AQ is packaged in a 24-pin dual-in-line
package with a transparent lid_ The transparent lid allows
the user to expose the chip to ultraviolet light to erase
the bit pattern_ A new pattern can then be written into
the device_ The MM 1702AD is packaged in a 24-pin
dual-in-line package with a metal lid and is not erasable_
features
Tbe circuitry of the MM1702A is entirely static; no
clocks are required_
A pin-for-pin metal mask programmed ROM, the
MM1302 is ideal for large volume production runs of
systems initially using the MM1702A.
•
Fast programming-30 seconds for all 2048 bits
•
All 2048 bits
factory tested
•
•
•
•
•
•
Fully decoded, 256 x a organization
Static MOS-no clocks required
Inputs and outputs DTL and TTL compatible
TRI-STATE® output-OR-tie capabilitY
Simple memory expansion-chip select input lead
Direct replacement for the Intel 1702A
block and connection diagrams
guaranteed
programmable-l00%
Dual·1 n·Line Package
PRO·
AJ
A4
21
Al~
:
INPUT _
DRIVERS
.,4,--
2D
A6
19
A7
18
VGG
11
Vie
16
15
B' GRAM
14
13
CS
PROGRAM
A._'--
At.
-
DATA
20UBIT
DE- ____ ROM ....:........a. OUTPUT
CODER r--"" MATRIX ----.. BUFFERS
(256118/
_
_
~~UTl
I
I
-
L....!.-.... DATA
,---I
-OUT'
Notl: In Iha read modI!! I logIC
''1'''tthelddreninpuulnddltl
lIutputl " • hillh .~d IOIl'C "0" I~
a low.
,. " ..1"
A2
Al
AD
\1
1
Lsa
*IlATA OUT
TDPVIEW
6,
MSB
Vee
tTlli.p~nlGth.dateiOpUlllllddulingpID9IDmmlng,
Pin Names
Order Number MM1702AD
See Package 6
AD-A7
Address Inputs
CS
Chip Select Input
DOUT 1 - DOUT a
Data Outputs
Order Number MM1702AQ
See Package 21
Pin Connections"
MODE/PIN
Read
Programming
12
13
14
15
16
22
23
(Vee)
(PROGRAM)
(eS)
(VBB)
(VGG)
(Vee)
(Vee)
GND
GND
Vee
Vaa
Vec
Vee
Vee
Pulsed VaG (V'L4P)
GND
GND
Vcc
Vee
GND
Program Pul se
·The external lead connections to the MM1702A differ, depending on whether the device is being programmed or used in
read mode. (See following table.) In the programming mode, the data inputs 1-8 are pins 4-11 respectively.
4-1
absolute maximum ratings
(Note 1)
Ambient Temperature
Storage Temperature
Power Dissipation
Read Operation
Input Voltages and Supply Voltages with
Respect to Vee
Program Operation
Input Voltages and Supply Voltages with
Respect to Vee
Lead Temperature (Soldering, 10 seconds)
O°C to +70°C
-{l5°C to +125°C
2W
+0.5V to -20V
-48V
300°C
read operation de characteristics
T A = o°c to +70°C, Vee = +5V ±5%, Voo
voltages and T A = 25° C. (Note 2)
= -9V ±5%, VGG = :-9V ±5%, unless otherwise noted. Typical values are at nominal
PARAMETER
III
Address and Chip Select
CONDITIONS
MIN
TYP
V'N = O.OV
MAX
UNITS
1
pA
Input Load Current
I LO
Output Leakage Current
V OUT = O.OV, CS = V ee -2
1000
Power Supply Current
VGG
= Vee, CS = V ee -2
1
pA
5
10
rnA
35
50
rnA
32
46
rnA
38.5
60
rnA
8
14
mA
13
mA
1
pA
10L = 0.0 rnA, T A = 25°C,
(Note 2)
1001
Power Supply Current
CS = Vee -2, 10L = 0.0 rnA,
TA = 25°C
I D02
Power Supply Current
1003
Power Supply Current
CS = 0.0, 10L = 0.0 rnA, T A
= 25°C
-
CS = V cc -2, 10L = 0.0 rnA,
T A = O°C
ICF1
Output Clamp Current
V OUT =-1.0V, TA =O°C
ICF2
Output Clamp Current
V OUT = -1.0, T A = 25°C
IGG
Gate Supply Cu rrent
V'L1
Input Low Voltage for
-1.0
V ec -4.1
V
V ce -6
V
Vec+0.3
V
TTL Interface
V'L2
Input Low Voltage for
V OD
MOS Interface
V'H
Address and Chip
V ce -2
Select Input High
Voltage
IOL
Output Sink Current
V OUT = 0.45V
IOH
Output Source Current
V OUT = O.OV
VOL
Output Low Voltage
10L = 1.6 mA
V OH
Output High Voltage
10H = -1 ~OpA
1.6
4
mA
-2.0
rnA
-0.7
3.5
4.5
0.45
V
V
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Note 2: Power~Down Option: VGG may be clocked to reduce power dissipation. The average IDO will vary between 1000 and 1001 depending
on the VGG duty cycle (see typical characteristics)' For this option, please specify MM1702AL.
4·2
read operation ac characteristics
T A =o°c to i-70?C, Vee =+5V ±5%, V DD = ---9V ±5%, VGG
= ---9V ±5%, unless otherwise noted.
TYP
MIN
PARAMETER
MAX
UNITS
Freq.'
Repetition Rate
1
tOH
Previous Read Data Valid
100
ns
1
fJ.s
0.7
MHz
tAee
Address to Output Delay
tDVGG
ClOcked V GG Set· Up (Note 1)
tcs
Chip SelectDelay
100
ns
teo
Output Delay From CS
900
ns
too
Output Deselect
300
ns
tOHe
Data Out Hold in Clocked VGC Mode (Note 1)
5
fJ.s
1
fJ.s
capacitancech~racteristics T A = 25°C (Note 3)
CONDITIONS
PARAMETER
TYP
MIN
MAX
UNITS
C 'N
Input Capacitance
All Unused
Y'N = Vee
8
15
pF
COUT
Output Capacitance
Pins Are
CS = Vee
10
15
pF
CVGG
VGG CaPacitance
(Note 1)
At ac
Ground
V OUT = Vee
30
pF
-
VGG = Vee
Nota 3: This parameter i. periodically sampled and is not 100% tested.
read operation switching time waveforms
(b) Power·Down Option (Note 1)
(a) Constant VGG Operation
I--CYCLETlME=1/f,~'
ADDRESS
a
CLOCKED
VaG
DATA
OUT
VOH
-+------'--....
DATA
OUT
Vo,--+-------------""'""-...J.
AODRE§
:::X:
f i I O% .
~
,
:,:'i~.~_ . ~".~
V"
II
::_~~=='=AOC=:=-I--~ ~_~_TE_'.,.'____
DATA OUT ..
INVALID
\1
Ir .
C
ADDRESS V"
a
DATA OUT
INVALID
Vo,----------~~"----~~-----V'H~LECTIO' OF DATA OUTPUT
OESELECTION OF DATA OUTPUT IN DR-TIE OPERATION
"
v---
V'H-:-y.,11'10
I
"O;!'~:::::-..
V,.
I. ORTIE OPERATION
___ _
I
I
'-+-'--'
VOH
DATA OUT
Cllndilions of Te51:
tnpufllUlsellmplltudts: 0--4V.l" ft :s;5Dns.O\lqlllllcadis1TTL9IIte; measure·
""nlimlde II output of TTL gate {tpg s; 15 ns}, CL = 15 pF.
Note 1: Th, output willnlltain valid for toMe 1$ 10"1 IS docked VGG nit Vee. An
,dllreu I:hlnp may o"ur 1$ sOOllllthe DIIlput 1$$Iflsrtl (clocked Vee may S1l1llN1u
Vee). OiltJ b.~omes ill•• for the ollllllddf1. when clocked VGG i,$ returned to VGG •
'td
Nl1le2; "CS mlku,a tra/Kilion 'rom VI~ to VIii while clocked VGG is at VOG. tbfn
."'''tioll of output Ocellll.t 100 IS shown in $1ItH: opef.tion with tonslllll VaG.
4·3
<
N
0
.........
,
programming operation dc characteristics
TA = 25°C. Vcc = OV. V BB = 12V ±10%. CS = OV unless otherwise noted .
:iE
:iE
PARAMETER
I L11P
Address and Data Input
CONDiTIONS
M.IN
TVP
MAX
UN.ITS
V 1N = -48V
10
mA
V 1N =-48V
10
mA
Load Current
I LI2P
Program and V GG Load
Current
IBB
V BB Supply Load Current
(Note 5)
10
100
mA
loop
Peak
Voo = V PROG =-48V
200
300
mA
0.3
V
100
Supply Load
Current
V 1HP
Input High Voltage
V 1L1P
Pu Ised Data I nput Low
VGG = -35V (Note 4)
~48
V
-40
-48
V
-46
-48
V
-35
-40
V
-46
Voltage
V 1L2P
V 1L3P
Address Input Low Voltage
Pulsed Input Low Voo and
Program Voltage
V 1L4P
Pulsed Input Low VGG
Voltage
Note 4: lOOp flows only during VOO. VGG on time. lOOp should not be al!'owed to exceed 300 mA for greater than lOOps. Average
power supply current lOOp is typically 40 mA at 20% duty cycle.
Note 5: The VSS supply must be limited to 100 mA max current to prevent damage to the device.
programming operation ac characteristics
TA = 25°C. Vcc = OV. V BB = 12V ±10%. CS = OV unless otherwise noted.
PARAMETER
CONDITIONS
MIN
Duty Cycle (V oo • V GG )
t.ppw
Program Pulse Width
TVP
MAX
20
VGG =-35V. Voo =
3
UNITS
%
ms
V PROG = -48V
tow
Data Set· Up Time
25
/J.s
tOH
Data Hold Time
10
/J.s
tvw
Voo. VGG Set· Up
100
V oP • VGG Hold
10
tvo
tAcw
Address Complement
/J.S
100
/J.S
(Note 6)
25
/J.s
(Note 6)
25
/J.s
Set· Up
tACH
Address Complement
Hold
tATW
Address True Set· Up
10
/J.s
tATH
Address True Hold
10
/J.s
Nota 6: All 8 address bits must be in the complement state when pul.ed VOO and VGG move to their negative level., The addresses
(0-255) must be programmed as shown in the timing diagram until data reads true. then over-programmed 4 times that amount.
(Symbolized by x + 4x.)
4·4
programming operation switching time waveforms
CQ"dil1on, 01 T~!!:
!Iljlut
~"Iser;l'
and
lallllm~
_
1~1
CS=Ov
typical performance characteristics
Output Current vs V DO
100 Current vs Temperature
;;;
.5
~
B
.E
39
38
37
36
35
34
3J
J2
Jl
30
Vee::: +5V
Voo '" -9V
VGG , "'-9V
INPUTS = Vee
OUTPUTS ARE OPEN
~~~c~
"';;;
1
"
IA
E
~~
"'w
~~
-
-
~1
"'.,
"'0:
-3
0>>-w -3.5
is'"'
20
40
60
80
100
120
I
-5
-6
~0:
5
-4
-7
-8
-9
12
10
cYA? ~
'"'"
'"
....
.~
./
-4
'"
-3 -2
A
-1
/
~
!i
w
~
~
'"
I
25
,/
,/'
V
,/
10
DUTY CYCLE (%)
Access. Time vs Temperature
1000
900
800
700
600
'"
w
'"
u
400
;:: 500
~
200
1-+-+-+-+. 1 TTllOAO ~ 20 OF
I--l-+-+-+ Vee =+5V
100
1-+-++-+ VaG ~ -9V
300
"
70
700
600
gj
~
400
300
100
10 20 30 40 50 60 70 80 90 100
!il
60
~
;:: 500
200
1/
]:
50
800
./
20
15
OUTPUT VOLTAGE (VI
40
900
Voo '" -9V
CS '" V1H
TA '" +25°&
30
0
30
1000
ClOCKED'V GG ",--!V
35
"Jl
20
Access Time vs load
Capacitance
45
40
10
AMBIENT TEMPERATURE I·CI
Average Current vs Duty
Cycle for Clocked V GG
(Note 11
Vee ='+5V
Voo '" -9V
VGG ~ -9V
TA =t25"C
14
L--L_L--L~L--L_L-...J
o
-10
SUPPl V VOLTAGE (V)
16
....
<'- f.-c-<'- i---
1
I
-4
Output Sink Current vs
Output Voltage
.5
N
1--------1
VGG =-9V
AMBIENT TEMPERATURE ICI
;;;
SPECIFIED
VOl.. '" +O.45V
TA '" +25°&
~o:
>-",
27
Vee == +5V
VOD '" -9V
- - OPE~A;~~~
0,-,
Vee'" +S!V
CS" O.OV
29
2R
Program Waveforms
Supply Voltage
VDO =-9V
10 20 30 40 50 60 70 BO 90
AMillENTTEMPERATURE (OC)
4-5
I--+-+-+---l--+-.J.- 1 TTl·LOAO
I--+-+-+---l--+-.J.- Vee' '" +5V
VOD '" -9V
I--+-+-+-+-+-.J.- VGG '" ~V
y~25°~
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (OF I
operation of the MM1702A in program mode
Initially, all 2048 bits of the ROM are in the "0"
state (output low). Information is introduced by selec·
tively programming "1 's" (output high) in the proper bit
locations.
minimum of 10/1s before the program pulse is applied.
The addresses should be programmed in the sequence
0-255 for a minimum of 32 times. The eight output
terminals are used as data inputs to determine the
information pattern in the eight bits of each word. A low
data input level (-48V) will program a "1" and a high
data input level (ground) will leave a "0" (see table on
page 4-4). All eight bits of one word are programmed
simultaneously be setting the desired bit information
patterns on the data input terminals.
Word address selection is done by the same decoding
circuitry used in the READ mode (see table for logic
levels). All 8 address bits must be in the binary complement state when pulsed V DD and VGG move to their
negative levels. The addresses must be held in their binary
complement state for a minimum of 25/1s after VDD and
VGG have moved to their negative levels. The addresses
must then make the transition to their true state a
During the programming, VGG , V DD and the Program
Pulse are pulsed signals.
MM1702A erasing procedure
out short-wave filters, and the.MM1702A to be erased
should be placed about one. inch away from the lim\p
tubes. There exists no absolute rule for erase time_
Establish a worst case time required with the equipment.
Then over·erase by a factor of 2, Le., if the device
appears erased after 8 minutes, continue exposure for
an additional 16 minutes for a total of 24 minutes.
(May be expressed as x + 2x.)
The MM1702A may be erased by exposure to high
intensity short-wave ultraviolet light at a wavelength of
2537A. The recommended integrated dose (i.e., UV
intensity x exposure time) is 6W sec/cm 2 . Examples of
ultraviolet sources which can erase the MM1702A in 10
to 20 minutes are the Model UV5-54 and Model 5-52
short-wave ultraviolet lamps manufactured by UltraViolet Products, Inc. (5114 Walnut Grove Avenue,
San Gabriel, California)_ The lamps should be used with-
4-6
s:
MOS EPROMs s:...,
o
II?'A National
N
~ Semiconductor
CO
MM2708, MM2704 8k and 4k UV Erasable PROM
General Description
Features
The MM2708, MM2704 are high speed 8192!4096-bit
UV erasable and electrically reprogram mabie EPROMs
ideally suited for applications where fast turn-around
and pattern experimentation are important requirements.
• 512 x 8 organization (MM2704)
•
1024 x 8 organization (MM27081
• 800.mW max
•
The MM2708, MM2704 are packaged in a 24-pin dual-inline package with transparent lid. The transparent lid
allows the user to expose the chip to ultraviolet light to
erase the bit pattern. A new pattern can then be written
into the devices by following the programming procedure.
Low power during programming
• Access time-450 ns max
• Standard power supplies: 12V, 5V, -5V
• Static-no clocks required
•
The MM2708, MM2704 is fabricated with the reliable,
high volume, time proven. N-channel silicon gate
technology.
Inputs and outputs TTL compatible during both
read and program modes
• TRI-STATE® output
Dual-In-Line Package
Block and Connection Diagrams
24
AJ
v"
23 A8
A6
____ Voo + 12V
22 NOTE 1
A'
"'-vcc .. sv
,-vss GND
+--vss--sv
"
M
DATA OUTPUTS (PROGRAM INPUTS)
VBS
26 CSIW~
A3
01-08
CfiWe
A2
"
A1
"
CHIP SELECT AND WRITE ENABLE lOGIC
..... _ PROGRAM
1
PULSE
I
17
AD
16
01
I
I
I
02
I
I
I
I
L ____ ~_~---~--_------~
OJ
Vss
15
10
11
,.
12
13
VDD
PROGRAM
DB
DJ
D6
D'
D.
TOP VIEW
Order Number MM270S0 or MM27040
See Package 21
Order Number MM270SJO or MM2704JO
S.e Package lOe
Pin Connection During Read or Program
MODE
PIN NUMBER
18
19
Note. MM2704: Pin 22
MM2708: Pin 22
9-11,13-17
12
21
24
Read
°OUT
VSS
VSS
VDD
VIL
20
VBB
Vee
Program
DIN
VSS
Pulsed
VOD
VIHW
VBB
Vee
VIHP
4-7
~
=
VSS
A9
Pin Description
AO-A9
01-08
CS/WE
Address inputs
Data outputs
Chip select/write enable input
Absolute Maximum Ratings
(Note 1)
-25°C to +85°C
-65°C to +125°C
20V to-o.3V
15V to -D.3V
Temperature Under Bias
Storage Temperature
VDD with Respect to VBB
VCC and VSS with Respect to VBB
All Input or Output Voltages with
Respect to VBB During Read
CS/WE Input with Respect to VBB
During Programming
20V to-o.3V
Pr~gram Inputwith Respect to VBB
35V to-o.3V
Power Dissipation
1.5W
Lead Temperature (Soldering, 10 seconds)
300°C
15V to-o.3V
Read Operation
DC Operating Characteristics
TA = o°c to +70°C, VCC = 5V ±5%, VDD = 12V ±5%, VBB = -5V ±5%, VSS = ov, unless otherwise noted, (Note 3)
CONDITIONS
PARAMETER
III
Address and Chip Select Input
MIN
TYP
MAX
UNITS
VIN = 5.25V or VIN = VI L
1
10
J1A
Sink Current
ILO
Output Leakage Current
VOUT = 5.25V, CS/WE = 5V
1
10
J1A
IDD
VDD Supply Current
Worst-Case Supply Currents, All Inputs
44
65
mA
7
10
mA
34
45
mA
High, CS/WE = 5V, TA = O°C
ICC
Worst-Case Supply Currents, All Inputs
VCC Supply Current
High, CS/WE = 5V, T A = O°C
IBB
Worst-Case Supply Currents, All Inputs
VBB Supply Current
High, CS/WE = 5V, T A = O°C
VIL
Input Low Voltage
VSS
0.65
V
VIH
Input High Voltage
3.0
VCC+l
V
VOHl
Output High Voltage
IOH = -100J1A
3.7
V
VOH2
Output High Voltage
IOH=-lmA
2.4
V
VOL
Output Low Votlage
IOL= 1.6mA
PD
Power Dissipation
0.45
V
800
mW
TYP
MAX
UNITS
AC Electrical Characteristics
TA = o°c to +70°C, VCC = 5V ±5%, VDD = 12V ±5%, VBB = -5V ±5%, VSS = ov, unless otherwise noted
CONDITIONS
PARAMETER
MIN
tACC
Address to Output Delay
Output Load: 1 TTL Gate and CL = 100 pF,
2BO
450
ns
tco
Chip Select to Output Delay
Input Rise and Fall Times:::: 20 ns: Timing
60
120
ns
120
ns
tDF
Chip Deselect to Output Delay
tOH
Address to Output Hold
Measurement Reference Levels: 0.8V
and 2.BV for Inputs; O.BV and 2.4V for
Outputs, Input Pulse Levels: 0.65V to 3V
0
0
ns
CAPACITANCE, (Note 2)
CIN
Input Capacitance
COUT
Output Capacitance
Note 1; "Absolute Maximum Ratings
n
VIN = OV, T A = 25°C, f = 1 MHz
4
6
pF
VOUT= OV, TA = 25°C, f= 1 MHz
8
12
pF
are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature"Range" they, are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics'"
provides conditions for actual device operation.
Note 2: tapacitance is guaranteed by periodic testing. TA
= 25°C, f "" 1 MHz
= 5V, VDD = 12V, VaB - -5V, and VSS - OV.
Note 3: Typical conditions are for operation at: TA = 25"e, Vee
4-B
Switching Time Waveforms
ADDRESS
K
)<
'un
\
CS,wE
1'DF
.I--.Cli-
-,
D~~~_
I-
~t~~~~~~
Programming Instructions
Initially, and after each erasure, ali bits of the MM2708,
MM2704 are in the "1" state (output high). Information
is introduced by selectively programming "0" into the
desired bit locations. A programmed "0" can only be
changed to a "1" by UV erasure.
required is a function of the program pulse width (tPW)
according to N x tPW ~ 100 ms.
The width of the program pulse is from 0.1 to 1 ms. The
number of loops (N) is from a minimum of 100 (tpw =
1 ms) to greater than 1000 (tpw = 0.1 ms). There must
be N successive loops through all 1024 addresses. It is
not permitted to apply N program pulses to an address
and then change to the next address to be programmed.
The circuit is set up for programming operation by
raising the CE!WE input (pin 20) to +12V. The word
address is selected in the same manner as in the read
mode. Data to be programmed are presented, 8 bits in
parallel, to the data output lines (01-08). Logic levels
for address and data lines and the supply voltages are
the same as for the read mode. After address and data
set up, one program pulse per address is applied to the
program input (pin. 18). One pass through all addresses
is defined as a program loop. The number of loops (N)
Caution should be observed regarding the end of a program sequence. The CS!WE falling edge transition must
occur before the first address transition when changing
from a program to a read cycle. The program pin should
also be pulled down to VILP with an active instead of a
passive device. This pin will source a small amount of
current (lIPU when CSIWE is at VIHW (12V) and the
program pulse is at V I LP.
Programming Characteristics
TA = 25°C, VCC = .5V ±5%, VDD = 12V ±5%. VaB = -5V ±5%, VSS = OV, unless otherwise noted
DC Programming. Characteristics
PARAMETER
MIN
TVP
MAX
UNITS
10
fJ.A
'Program Pulse Source Current
3
mA
IIPH
Program Pulse Sink Current
20
mA
100
VDD Supply Current
44
65
mA
7
10
mA
34
45
mA
III
Address and Cf;!WE Input
CONDITIONS
VIN = 5.25V
Sink Current
IIPL
Worst-Case Supply Currents, All Inputs High,
CS/WE
ICC
VCC Supply Current
= 5V, TA = O°C
Worst-Case Supply Currents, All Inputs High,
CS/WE = 5V, T A = 0° C .
IBB
VBB Supply Current
Worst-Case Supply Currents, All Inputs High,
CSIWE = 5V, TA = O°C
VIL
VIH
Input Low Level (Except
Program)
VSS
0.65
V
Input High Level, All
3.0
VCC+1
V
11.4
12.6
V
Addresses and Data
VIHW
CS/WE Input High Level
VIHP
Program Pulse High Level
Referenced to VSS
25
27
V
VILP
Program Pulse Low Level
VIHP - VILP= 25V Min
VSS
1
V
Referenced to VSS
4-9
AC Programming Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tAS
Address Set-Up Time
10
j1s
tcss
CSIWE ,Set-Up Time
10
j1S
tos
Data Set-Up Time
10
j1s
tAH
Address HoldTime
1
j1S
tCH
CS/WE Hold Time
0,5
j1S
tOH
Data Hold Time
1
j1S
tOF
Chip Deselect to Output Float Delay
0
tOPR
Program to Read Delay
tpw
Program Pulse Width
0.1
tpR
Program Pulse Rise Time
0.5
2.0
j1S
tPF
Program Pulse Fall Time
0.5
2.0
j1S
120
j1S
10
j1S
1.0
ms
Programming Waveforms
READ
(AFTER N PROGLOOPS)
1 OF N PROGRAM LOOPS
VIHW
CSIWE
ADDRESS
VIL~
t CH(0.5J--j -
f-- tCSS(IOJ ~
(NOTE I)
VI~=>
ADDRESS 0
VIL
-
t---tAS(IO)-
DATA
X=ESSI
VI~=>
VIL
f-- tDsll0)-
t--- tAH(1)
- K:
I-- tOHII)
(O.1msMIN)
- t p w (1.0 ms MAX"---1
tPRI0.5)-
ADDRESS 0
ADDRESS 1023
-
tAH(1)
tAce 450 ns MAX
~nATADUT~
~DATAOU:§
INVALID
VALID
-
l--
tOH(1)
C-- t pFI0.5)
tDPR(IO MAX)
VIHP
PROGRAM
PULSE
il
VIL
\
'---!
Note 1: The CS/WE transition must occur after the program pulse transition and before the address transition.
Note 2: Numbers in parentheses indicate minimum timing in microseconds unless otherwise specified.
4-10
Typical DC
P~rformance
Characteristics
Maximum Junction
Temperatura V$ Ambient
Range of Supply Currents
Temperature
Temperature
YS
18 ,-r---'---:~=~:-1
......,
iii!
i
100
~--~~~--+-----~~
,50
~--~+-----+-'"--+~
!
;~
'JA -811"CtW
iii
VCC' 5.2&V
VOO'12.BV
VBB =5.25V
I
~
20
&0
40
70
20
TA - AMBIENT TEMPERATURE rei
40
60
80
100
TA - AM81ENT TEMPERATURE rCI
Output Sink Current
YS
Output Voltage
10
17-':"':::::-,-,,--"'--'
10
VOL - OUTPUT VOLTAGE (V)
Typical AC Performance Characteristics
AcceSs Time V$ Load
Access Time
YS
Temperature
Capacitance
500
400
TA' 25°C
-------
1 TTL LOAD + tOO pF
!
400
iI:i
30G
!i
200
~
..,..,I
--:
:f- lOG
---
...-
g
.....
300
!
B 20a
'"..,
I
$
o
100
o
-20
20
40
60
80
TA - AMBIENT TEMPERATURE rC)
i""'"
o
100
200
300
400
CL - LOAD CAPACITANCE Ipf)
4·11
500
~National·
MOS EPROMs
~ Semiconductor
MM4203/MM5203 electrically programmable
2048-bit read only memory (pROM)
general description
The MM4203/MM5203 is a 2048-bit static readonly memory which is electrically programmable
and uses silicon gate technology to achieve bipolar
compatibility. The device is a non-volatile memory
organized as a 256-8-bi.t words or 512-4-bit words.
Programming of the memory contents is accom·
plished by storil)g a charge in a cell location by
programming th~t location with a 50 volt pulse.
Separate output supply lead is provided to reduce
internal power dissipation in the output stage
(VLd·
• Pin compatible with MM5213, MM5231 mask
programmable ROMs
• Static operation - no clocks required
• Co.mmon data busing (TRI-STATE@output)
• "Q" quartz lid version erasable with short wave
ultra-violet light (i.e. 253.7 n.m.)
• Ch ip select output control.
• 256 x 8 or 512 x 4 organization
applications
•
•
•
•
•
features
• Field programmable
• Bipolar compatibility
• High speed operation
+5V, -12V operation
l/ls max access time
block and connection
Code conversion
Random logic synthesis
Table look-up
Character gener~tor
Micro-programming
~iagrams
Dual-ln-LinePac,,-
.,
1/11
LSI A,
I,
I,
n ...
,
UPROGR_
·
.
..
".
"
,
"
·
.. ·
.
0,
I,
A,
. .. . .,
I
"A,
I
""
"VIID
'1 lit
IS :::ROL
1.11
I.Ci
YI5 'Z
13
~MS8
Order Number MM4203D or MM5203D
See Package 6
Order Number MM4203Q or MM5203Q
See Package 21
typical applications
256 x 8 PROM Showil19 TTL Interface
'
f
.
Operating Modes
256 )( 8 ROM connection (shownl
Mode Contro" - HIGH 1VSSI
Ag
- LOW
5:12 x 4 ROM connections
Mode Control - LOW {GNO or VOOI
Ag
- Logic HIGH enables the odd (B1. 83.. 8,) outputs
- Logic LOW enables the even (82. 84,. BSI outputs
MODE
COrrrRtL
.
..
.
'n
'
..
"
"
The outpuU are enabled when a logic LOW is applied to
the Chip Select line .
Programming is accomplished in 256 x 8 mode only .
, "
, "
1
"
1
tSto .......... _
Note: For programming information see AN-lOO.
4·12
absolute maximum ratings
All Input or Output Voltages with
Power Oissipati~n
Operating Temper.ture
~.nge
MM4203
MM5203
_65°C to 125°C
300·C
Storage Te,mperature Range
Lead Temperature (Soldering, 10 sec)
+.3V to-20V
lW
_5.5°C toS5°C
O·C to 70°C
R!!lspeCt to Vee Except During Programming
electrical ..characte. ristics
T ... within operating temperature range.
Vss = +5V 15%. Voo '" V LL = -12V. ±5%. V BB ", PROGRAM = V~ unless otherwise noted.
MIN
CONDITIONS
PARAMETER
Input CUrrent. 1",
Y'N =OV
Output Leakage. I CO
VOUT = OV
Power Supply Current. Iss
T" = 25°C CS =Vss -2.0
CS = Vs ,
TVP
MAX
-2.0
35
p.A
1
/LA
mA
55
4.0
Input LOW Voltage.·",L
Vs , - 10
Vss -
InpUt HIGH. Voltage. V ,H
V's - 2.0
Vss +.3
Output LOW Voltage. VOL
Output Clamp Current"I CF
1.6 mA sink -1·2.6V < V LL < -3V
VLL = -3.0V VOUT = -1.0V (Note8lTA = O°C
V LL = -12.6V VOUT = -1.0V (Not. 8) T" = OoC
:40
6.0
15.0
3.5
8.0
2.4
Output HIGH Voltage. VOH
0.8 rnA source
Data Hold Time. TOH
(Min Access Time) Figures 1 & 2
UNITS
1
V
V
V
mA
mA
V
100
ns
1
/LS
Access Time, T Ace
T" = 25°C Figures 1 & 2 (Note 6)
Chip Selec~ Time, T co
Figures 1 & 3
500
ns
.Chip Deselect Time, Too
Figures 1 & 3
500
ns
Figures 1 & 2
100
ns
8
15
pF
8
15
pF
Allowable Chip Select Delay. teg
.700
Allow~ble
delay in selecting chip after change
of address without affecting access tim~.\
Input Capacitance, C IN
Y'N = Vss
Output Capacitance. COUT
V OUT
}
f· 1.0 MHz (Nole 2)
= Vss
CS = Vss - 2.0
programming characteristics
TA = 25°C, Vss = OV. Vss = +12V ±10%.
D
(see Figure 4)
CS = OV unless otherwise noted
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNITS
Address and Data Input Load Current. I LO
VIN = -50V
0
10
rnA
Pr~gram Load Current. I LP
Y'N =-50V
a
10
rnA
0
10
mA
VBB Supply Load Current. ILB
'v DO = V program =-SOV
Peak Ico Supply Load Current I LCO (Note 3)
Input High Voltage. V ,HP
Address and Data Input Low Voltage. V'LP
Pulsed Input Low Voltage;
Voo. and Program. VOLP
V LL
(Note 5)
-2
+.3
V
-50
-40
V
-50
-50
-48
V
V
Voo Pulse Duty Cycle
V DO = V program
Program Pulse Width. tpw (Ncte 4)
rnA
650
=-:-50V
0
2
%
., 20
ms
Data and Address Set Up Time. tow
1
)J.s
Data and Address Hold Time.to H
0
)J.s
Pulsed V DO Supply Overlap. tss
1
Pulsed V DO Supply Overlap. tSH
-.1
Voo. Program. Address. and Input Rise
and Fall Times
.
a
Notal: During prograMming, data is always applied in the 256 x mode, reg,ardl~ of, the logic state of Ag and MODE
CONTROl.
Note 2: Capacitances. are
tested on a produc;tion basis but are periodically sampled.
Note 3: lOop flows onlv during program PerIod tpwp. Average power SupplV current I LDD is typicallv 15 rnA at 2% duty cvcle.
N_ 4: Maximum duty cycle of, tpw should not be greater than 2% o~ cycle time so that power dissipation Is minimized. The
program CVde ,t\ould be repeated until the data '!lads true, then over-program three times that number, of cyeles (symbolized
as X+3X programming.
'
Note 5: \ILL i$ .... ot ne~ded during grogramming but may be tied to VDO for convenience.
Not. 6: TACe,'" 1000 .... $ + 251N-11 where N is the number of chips wif1!d.oR together.
Not. 7: Measured under contlnUQUS operation.
Note 8: ICF flows 01.11 the VLL Pifl. II dOH not flow out the VOP pin.
"ot
4·13
.100
)J.s
3
ms
1
)J.s
access time diagrams
+5.0V±5%
INPUT
-12Vo!5lI
Figure 1
H
Xi
ADDRESS •
~.
) C VSS -2.OV
__________
~_____
Vss-4.0V
_-"","",""TcsrI
CHIP SELECT
Vss - 2.0V
--- T""
1--Vss -4.0V
H----~Yl/$////////l;",.".".,,,.,,.,,,.,,.,"!D-A-TA-OU-T..,1llllllllll/llN.,..,,.,.,..,,.,.,..,,.,""
DATA OUT
: .rriA't""dUT
~NOTVALlD~1' -_ _V;.;.A;.;.L;.;.ID;....._--'!1~lJ!I}ID
DATA OUT
TMX-------;~~·
f4
Figure 2
H------""\
CHIP SELECT
j'"------Vss -2.0V
' - _ _ _ _ _ _ _ _J
DATA
DATA VALID
Figure 3
program waveforms
INPUT STABLE
VDD
Figur.4
4·14
Vss-4.OV
operation of the MM4203/MM5203 in program mode
Initially, all 2048 bits of the MM4203/MM5203
are. in the HIGH state. Information is introduced
by selectively programming LOWS in the proper
bit locati.ons. (Note 1)
1-8.are pins 4-11 respectively regardless of the
logic state of Ag and mode control. Chip select
should be disabled (HIGH).
Positive lagic is used during the read mode far
addresses and data Qut. Address 0 corresponds to
all address inputs at V,L and address 25510 co.r.
responds to. all address inputs at V ,H . A "1" ora
Pat a data output corresponds to VoH.A "0" ar
an N at a data output correspands to VOL' Posi.
tive logic is also used during the programming mode
for addresses. Address 0 corresponds to all address
inputs at V,L ? and address 255 10 correSponds to
all address inputs at V ,HP '
Word address selection is done by the same decod·
ing circuitry used in the Read mode. The eight
output terminals are used as data inputs to deter·
mine the information pattern in the eight bits of
each word. A LOW data input level (-50V) will
leave a HIGH and a HIGH data input level will
allow programming of a LOW. All eight bits of one
word are programmed simultaneously bY setting
the desired. bit information patterns on the data
input terminals. The duty cycle of the V DO pulse
(amplitude and width as specified on page· 4)
should be limited to 2%. The address should be
applied for at least 1 IlS before application of the
Program pulse. In programming. mode, data inputs
Negative 199icis used during the programming mode
for data in. A "1" or a P at a data input corres.
pands to V ,LP ' A "0" or an N at a data Input
corresponds to. V I H p.
DATA AND ADDRESS LINES
Vss
VB.
voo
PROGRAM
CS
VLL
+5
v",
-.2
Vss - 4V
-3V tp-12V
GND
,.2
vss
-48
-48
(pulse)
GND
GND to" SOY
MODE
HIGH
LOW
Read
Vss - 2.0
Vss
Program
Vss -2.0
Vsf; - 40
~
4.0
(Pulsel
erasing procedure
minutes. Examples of UV sources include the
Model UVS·54 and Model S-2 manufactured by
Ultra-Violet Products, Inc. (5114.Walnut Grove
Avenue. San Gabriel, Califernia). Tho I"mps
should· be used without short-wave filters. The
MM4203/MM5203 should be placed. about one
inch away from the lamp for about 20-30
minutes.
The MM42030/MM52030 may be erased by
expo.sure to sho.rt-wave ultravialet light-253.7nm.
There exists no. abselute rule for erasing time or
dislance from source. The erasing equipment
output capability should be calibrated. Establish a
worst-case time required with .the equipment.
Then over-erase by a factor of 2, i.e .• if the device
appears erased after 8 minutes, continue exposure
for an additional 16 minutes for a total of 24
preferred tape format
from model 33 teletype or TWX. The paper tape
should be as the following example:
The custom patterns may be sent in on a Telex or
submitted as a Paper tape in a 7 bit ASCII. code
Start Character,~ ,Stop Ch.aracter~.,
Leader; Rubout for
~~tr::e':'~~;,~:
,
,
fr
Carriage return line feed
allowed between F Bnd B.
Data Field~
I
MSB (Pin 11)
lSB (Pin 41
Itt
~PPPN P PNN'F,BNN PP NNPPF . . 'BNPNPNNNNF
25 frames.)
~~e~;r '~~':~e~r
fortelex(atleast
25 frames.)
Word 0
Word 1
Word 255
~
All Address Inputs HIGH
All Address Inputs LOW
*Data field: Must have only P's or N's typed between Band' F No nulls or ru1:.out5. Must have e:o;a(~tly ii"ht P and N
characters between Band F _ Any characters except Band F may be typed between the F stop character and the B star'
character. If an error is made in preparing a tape the entire word including the Band F start and stop charactftS must
be rubbed out. Data for exactly 256 words' must be entered, beginning with ward 0,
4-15
alternate format
[Punched Tape (Note 1) or Cards]
~
PO~~V:2~~gic
.b8'MSBIPinlll
b1. LSB (Pin 4)
2 Spaces-+---,
t oooooono
AOOO
AOO I
0
OOf)l')oon~
\~
:
~~g~ 6~~:?:rl):
Af1(1'i
Afl06
A')07
ADOI'<
00011-)00
Note 1: The code is a 7-bit ASCII code on 8 punch tape. The tape
should hflgin and end with 25 or more "RUBOUr' punches.
_______
Note 2: The ROM input address is expressed in decimal form and is
preceded by the letter A.
Note 3: The total number of "1" bits in the outpul word.
Note 4: The total number of "1"' bits in each output column or bit
position.
1--1 Space
3
onf'jnr)oo'1 0
00111100
4
Ow)()()()on (l
0101')I01.!t
A~II
181'\
Note 3
onr)oooo~ ~
!~oo~
Note 4
140
187 I~n
186 ?'50
lAS 40f)
194 01 n
1AJ 1 no
IB2 299
1811197
L__~1=======t--
1 Space
typical performance characteristics
Maximum Access Time (T Ace)
Maximum Supply Current ISS
as a Function of Temperature
as a Function of
Voltage
'""=+==+=l=l=+=v:;;:-::v;rv:l
r-T--r'-r-T--r.-rr-r"'-'~-'--'
80
H+H++-I-++-H-+-t-t-l
1700
1600
70
f-kl-+-l-+,
1500 ~+-+--+-+--+-+--+-+---I
(Note 1)
_'+5lLUy-±t±t
I
VI'T-i
60 H""""",,KI=:!:N.d-+-_f-+NOM SUPPLY
=
30
!:i
30
tM
E
tEA
tEA
20
20
tER
10
t~R
10
o
0
-55
25
TA _ AMBIENTTEMPERATURE
4.5
125
rei
5.0
5.5
SUPPl Y VOLTAGE (VI
equivalent circuits
Equivalent of Each Input
vee
Typical TRI·STATE Output
vee
INPUT 0-..,.....--1
L..............-uts
VCC" Max. VIN
= 2.7V
II
Input Leakage Current. All Inputs
Vce
=
5:5V
VOL
Low Level Output Voltage
Vec = Min, IOL " 16 rnA
=
Max, VIN
MIN
TYP
-80
0.35
MAX
3:
........
DM87S221, 87S222
MIN
TYP
MAX
UNITS
~250
jJ.A
25
25.
jJ.A
1.0
1.0
rnA
-250
-80
0.35
0.45
0.80
0.45
VIL
VIH
High Level Input Voltage
ICEX
Output Leakage Current
VCC." Max, VCEX ·02.4V
(Open·Coliector Only) INote 5)
VCC" Max., VCEX
Ve
Input Clamp Voltage
VCC" Min, liN" -18 rnA
GIN
Input ,Capacitance
Vce = 5V, VIN" 2V. TA" 25°C.
1 MHz
4.0
4.0
pF
Co
Output Capacitance
VCC " 5V, VO." 2V. TA " 25'C,
1 MHz, Output "OFF"
6.0
6.0
pF
Ice
Power Supply Curreflt
VCe" Max, All Inputs Grounded.
120
2.0
= 5:5V
-0.8
V
V
50
50
jJ.A
100
100
jJ.A
-1.2
-0.8
120
150
-1.2
150
V
rnA
All Outputs Open
TRI-STATE PARAMETERS
Ise
OtJtput
Shor~
Circuit Current
VO" OV: Vec " Max, INote 41
-2,0
~45
-70
-20
-45
-70
rnA
t50
J1A
(Note 51
1HZ
Output Leakage ITR I·ST ATEI
Vce = Max, Vo
=
0.45
to'
2AV,
±50
Chip Disabled
VOH
Output Voltage High, INote 5)
IOH
=
:'2 rnA
2.4
3.2
V
IOH - -6.5mA
ac electrical characteristics
2.4
V
(With standard load)
DM77S221,775222
PARAMETER
3.2
DM875221, 875222
SV±10%;-SSOCto +12soe 5V ±S%; O°C to +7o o e
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tAA
Address Access Time
40
75
40
60
ns
tEA
Enable Access Time
20
40
20
30
ns
tER
Enable Recovery Time
20
40
20
30
ns
tLO
Latch To Output
15
30
15
20
ns
1: Absolute maximum ratings are those values beyond which the device may' be permanently damaged. They do not mean that the device
may be operated at these values.
Note 2: These ,limits do not apply during pr:ogramming. For the programming ratings, refer to the programming instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee -- 5V and TA -- 25~C.
Note 4: During ISC measurement. only one output at a time should be gr()unded. Permanent damage may otherwise result.
Note 5: To measure YOH • .ICEX or ISC on an unprogrammed part"apply 10;5V.
NDt~
5-27
N
N
......
o
3:
CO
....
C/)
Low Level Input Voltage
2.0
0.80.
V
C/)
N
N
N
N
00
N
N
tJ)
I'
00
~
~National
Bipolar PROMs
~. Semiconductor
C
......
00
N
N
en
f::
~
c
en
N
N
en
I'
00
~
C
......
en
N
N
en
f::
DM77S229/DM87S229 open-collector 8192-bit PROM
DM77S228/DM87S228 TRI-STATE® 8192-bit PROM
features
general description
Tl1ese Schottky PROM memories are organized in the
popular 1024 words by 8 bits configuration. Four
memory enable inputs are provided to control the
output states. WhenEl and E2 are low and E3 and E4
are high, the output presents the contents of the selected
word.
• Advanced titanium-tungsten (Ti-Wl fuses
If El or E2 are high, or E3 or E4 are low, it causes all
8 outputs to go to the "OFF" or high impedance state.
The memories are available in both open··collector and
TRI-STATE versions and are available as ROM's as
well as PROM's .
• PNP inputs reduce input loading
• Schottky-cl amped for high speed
Address access-70 ns max
Enable access-45 ns max
• All dc and ac parameters guaranteed over temperature
• Low voltage TRI-SAFETM programming
PROM's are shipped from the factory with lows in all
locations. A high may be programmed into any selected
location by following the programming instructions.
Once programmed, it is impossible to go back to a low.
• Board level programming
• ROM mates are DM85S29 and DM85S28
~
c
Commercial
OpenCollector
DM87S229
X
X
DM87S228
X
Military
DM77S229
X
DM77S228
X
TRI-STATE.
Package
X
N, J
N,J
X
J
X
block diagram
J
connection diagram
Dual-In-Line Package
"
A7
A'
Vee
"
AI
"
AI
A4
"rr
A3
"'1
BI92;-8ITARRAY
128 X Ii4·BIT
MEMORY MATRIX
A2
19 [3
AI
18 E4
A'
08
16 07
02
rr~,r--,
'1
"
IS 06
03 It
05
GNU 12
13 04
L..---:::
V--lEW--'
TO-',
..
E3
01
07
.
05
The device is enabled when:
..
logic symbol
03
E1 • E2 • E3 • E4
02
01
A'
02
A3
Q3
A'
A'
A'
04
AI
AI
08
A7
5-28
"
A2
"
"
absolute maximum ratings
Supply Voltage (Note 2)
Input Volta.ge (Note 2)
Output Voltage (Note 2)
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
o
3!:
:::I
en
. operating conditions
(Note 1)
to +7V
-1.2V to +5.5V
-o.5V to +5.5V
-65·e to +150·e
300·e
-~.5V
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
+70
·e
·e
o
3!:
Logical "0" Input Voltage (Low)
0
0.8
V
......
Logical "1"· Input Voltage (High)
2.0
5.5
V
Supply Voltage (Vee)
PM77S229, OM77S228
OM87S229,OM875228
Ambient Temperature (TA)
OM775229, OM77S228
OM87S229, OM875228
N
N
CD
......
CIO
en
N
N
CD
dcelectrical Characteristics
-
(Note 3)
.
PARAMETER
OM77S229,77S228
CONDITIONS
MIN
I.nput Load CUrrent, All Inputs
Vec = Max, VIN = 0.45V
IIH
Input Leakage Current, All Inputs.
VCC = Max, VIN
II
I nput Leakage Current, All Inputs
VCC = Max, VIN = 5.5V
VOL
Low Level Output Voltage
VCC = Min, IOL = 16 mA
IlL
TVP
-80
= 2.7V
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
ICEX
Qutput L~akage Current
(Open·Coliector Only) (Note 5)
VCC = Max, VCEX = 2.4V
0.35
MAX
oM87S229, 8.7S228
MIN
-250
TVP
-80
Inpul Clamp Voltage
VCC = Min; liN = -1S mA
Input Capacitance
VCC = 5V,VIN
1 MHz
Co
Output Capacitance
ICC
Power Supply Current
-=
-
tM
4B
30
tEA
20
t~R
10
o
25
4.5
125
5.0
5.5
SUPPL V VOLTAGE (VI
TA - AMBIENT TEMPERATURE nl
equivalent circuits
Equivalent of Each Input
Vee
Typical TRI·STATE Output
vee
INPUT 0--...--1
L--.!H~-o OUTPUT
S·32
Typical Open·Coliector Output
equivalent circuits
(Continued)
Programming Equivalent Circuit -for One Memory Output
(Applies to All. NSC Generic Schottky.PROMs)
Vee
c
s:-.J
-.J
Ch
N
CD
c:n
........
c
s:CO
-.J
Ch
N
CD
1--'-....-ilNIr-........- .......-o OUTPUT
programming procedure
These parts are shipped from the factory with all fuses
intact. As a result, the outputs will be low (logical "0")
for all addresses. In order to generate a high level on the
outputs, the part must be programmed. Information on
available programming equipment may be obtained from
National. However, if it is desired to build your own
programmer, the following conditions must be observed.
b) Increase VCC to 10.5V ±0.5V with the rate of
increase being between 1.0 and 10.0 Vips. Since
VCC.supplies the current to program the fuse as
well as the ICC of the device at programming
voltage, it must be capable of supplying 400 mA
at 11.0V.
c) Select the output where. a high level is desired by
raising that output voltage to 10.5V ±0.5V. Limit
the rate, of increase to a value between 1.0 and
10.0 V//ls. This voltage change may occur simul·
taneously with the increase in VCC but must not
precede it. It is critical that only one output at a
timebe programl)1ed since the internal circuits can
only supply programming current to one bit at a
time .. Outputs not being programmed must. be left
open or tied to a high impedance source of at least
20 kn. (Remember that the outputs of the device
are still disabled at this time.)
1. Programming should be attempted only at tempera·
tures between 15°C and 30°C.
2. Addresses and chip enable pins must be driven from
normal TTL logic levels during both programming
and verification.
3. Programming will occur at a selected address when
VCC is held at 10.5V, the appropriate output is held
atl0.5V and the chip is subsequently enabled. To
achieve these conditions in the appropriate sequence,
the following procedure must be followed:
a) Select the desired word by applying a high or.low
level to the appropriate address inputs. Disable the
chip by applying appropriate level to the. enable
inputs.
5·33
c:n
programming procedure
en
N
Ch
,....
co
~
C
Lt)
f) Following verification, apply five additional programming pulses to the bit being programmed.
The programming procedure is now complete for
the selected bit.
g) Repeat steps a through f for each bit to be programmed to a high level. If the procedure is
performed on an automatic programmer, the duty
cycle of Vee at programming voltage must be
limited, to a maximum of 25%. This is necessary to
minimize chip junction temperatures. After, all
selected bits ,are programmed, the entire contents
of the memory should be verified.
d) Enable the device by applying appropriate levels to
the chip enable inputs. This is done with a pulse
of 10 J,ts. The 10 J,ts duration refers to the time that,
the circuit is enabled. Normal input levels are
used and rise and fall times are not critical.
e) Verify that the bit has been programmed by first
removing the programming voltage from the
output and then reducing Vce to 4.0V ±O.2V.
Verification at a Vee level of 4.0V will guarantee
proper output states over the Vee and temperature range of the programmed part. The chip
must be enabled to sense the state of the outputs.
During verification, the loading of the output
must be within specified IOL and IOH limits.
Steps b, c and d must be repeated 10 times or
until verification that the bit has programmed.
Lt)
.......
(Continued)
programming parameters
Note: Since only an enabled cnip is programmed, it is
possible to program these parts at the board level if all
programming parameters are complied with.
Do not test or you may program the device .
en
N
Ch
,....
,....
~
C
PARAMETERS
CONDITIONS
Vee for Programming
VCCP
Required
ICCp
ICC During Programming
RECOMMENDED
VALUE
MAX
10.0
10.5
11.0
400
VCC=llV
VOP
Required Output Voltage for Prograf'Pming
lOp
Output Current white Programming
10.0
Rate of Voltage Change of
Programming Pulse Width (Enabled)
VCCV
Required
MDC
Maxim~m Duty Cycle for
11.0
10.5
20
VOUT"llV
Vee or Output
tRR
PWE
Vee for
MIN
1.0
Verification
10.0
3.8
4.0
4.2
V
25
25
%
+-----..__---------.....,
I
w
veev
L-_ _ _ _ __
-
-~:;f7!
-1" I-
:::'~I--
OUTPUT
II
VOl-
ENABLE 2.4VT05.5V
OVTOO.5V.
- - - . - , - .
I
~i
T3
r--
~''''''----------Ij
"';;:;;;Y".
W
= 100 ns min
T2 = 5 /.IS min (T2 may be
--j
T4
I---
11----------
-I~PwE'--j
T1
2:
a if VCCP rises at the same rate or faster than VOp)
T3 = 100 ns min
T4 = 100 ns min
T5 = 100 ns min
*PWE is repeated for 5 additional pulses -after verification of VOH indicates
a bit has programmed
5-34
VIjJ.s
11
Vee at Veep
veep ------..
V
rnA
10
2.4VT05,5V, ~,/
...
OV TO 0.5V
'-----------------'
vee
V
mA
9
programming waveforms
ADDRESS
UNITS
jJ.S
~NaHonal
_
MOS ROMs
Semiconductor
MM1742 2048-bit read only memory
genera I description
The MM1742is a .2048:bit static Read Only Memory
which is electrically programmable and uses silicon gate
technology to achiEivebipolar cOI:npatibility.The device
is a non-volatile memory organized as 256 ~-bit words.
Programming of the memory is accomplished by storing
a charge in a cell location by applying a -47V pulse.
Although· a PROM di.e is used, factory. programming
is. required.
.
• Bipolar compatible
• TR I-STATE® outputs
• Pin compatible with the MM1702A, C1702A, and
C1302.
.applications
•
•
•
•
•
features
•
•
Electrically programmed for fast turn-around
Fully decoded, 256 x 8organiz.atiorl
Code conversion
Table look-up
Micro·programming
Character generator
Random logic synthesis
block and connection diagrams
AO---+-
DATA
DUTI
A I " , INPUT
I
DRIVERS
DATA
AI I
OUTS
Note: In the read mode a logic •• ,"' at the address inputs
and da.ta outPU~s is a high and logic·"O" is a low.
Dual-In-Line Package
VOD vee vee
t
23
Z2
A3
21
A4
A5
20
19
A6
18
VGG Vee
AI
11
16
15
Vee
CI
14
13
Pin Names
-
l-
AD-A7
Address Inputs
CS
Chip Select Input
DOUT 1 - DOUT8 Data Outputs
I
A2
2
Al
3
AU
4
5
6
1
8
9
10
11 .1'2
~.1::-;";"_'-'~-"""---""'-::MS::::88' Vee
'LS8
DATA OUT
TOP VIEW
Ordor Number MM1742J
See Package 11
6-.1
absolute maximum ratings
(Note 1)
Ambient Temperature
Storage Temperature
Power Dissipation
Read Operation
Input Voltages and Supply Voltages with
Respect to Vec
lead Temperature (Soldering, 10 seconds)
0° C to +70° C
-£5°C to +125°C
2W
+0.5V to -20V
300°C
dc characteristics
TA = oOe to +70°C; Vec = 5V ±5%, Voo = -9V ±5%, VGG = -9V ±5%, unless otherwise noted. Typical values are at nominal
voltages and T A = 25°C. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
III
Address and Chip Select
Input load Current
VIN =OV
1
ILO
Output leakage Current
VOUT = OV, es = Vce - 2
1
Jl.A
1000
Power Supply Current
VGG = Vce, CS = Vce - 2
IOl = 0 mA, TA = 25°C,
(Note 2)
5
10
rnA
1001
Power Supply Current
CS = Vee - 2, tOl= 0 mA,
TA = 25°C
35
50
rnA
1002
Power Supply Current
es = 0, IOl = 0 mA, TA = 25°C
32
46
rnA
ID03
Power Supply Current
CS=VCe- 2,IOl=OmA,
TA = DoC
38.5
60
rnA
8
ICFl
Output Clamp Current
VOUT=-lV, TA=Ooe
leF2
Output Clamp Current
VOUT = -lV, TA = 25°C
IGG
Gate Supply Current
VIL1
Input low Voltage for
TT l Interface
-1
VIL2
Input low Voltage for
MOS Interface
VIH
Address and Chip
Select Input High
Voltage
IOl
Output Sink Current
VOUT= 0.45V
IOH
Output Source Current
VOUT=OV
VOL
Output Low Voltage
IOl = 1.6 mA
VOH
Output High Voltage
IOH = -1001lA
Jl.A
14
rnA
13
rnA
1
Jl.A
Vec-4 .1
V
VDO
VCC-6
V
Vee-2
Vce+O.3
V
1.6
4
mA
-2
rnA
-0.7
3.5
4.5
0.45
V
V
Note 1: Stresses above those listed under" Absolute Maximum Ratings" may cause perma~ent damage to the device. This is a stress rating on'ly and
and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to Absolute Maximum.Rating conditions for extended periods may affect device reliability.
Note 2; Power-Down Option: VGG may be. clocked to reduce power dissipation. The average 100 will vary between 1000 and 1001 depending
on the VGG duty cycle (see typical characteristics). For this option, please specify MM1742ALJ.
6·2
s:
s:....
ac characteristics
....
TA = o°c to +70°C, VCC = 5V ±5%,VDD =.-9V ±5%, VGG = -9V ±5%, unless otherwise noted.
PARAMETER
Freq.
Repetition Rate
tOH
Previous Read DataValid
~
. TYP
MIN
MAX
UNITS
MHz
100
ns
tACC
Address to Output Delay
tDVGG
Clocked VGG Set-Up,(Note 1)
tcs
tco
Chip Select Delay
100
ns
Output Delay From CS
900
ns
tOD
Output Deselect
300
ns
tOHC
Data Out Hold in Clocked VGG Mode, (Note 1)
5
j1S
capacitance characteristics
0.7
j1s
j1S
TA =25°C (Note 3)
PARAMETER
CONDITIONS
TYP
MIN
MAX
UNITS
CIN
Input Capacitance
All Unused
VIN =VCC
8
15
pF·
COUT
Output Capacitance
Pins Are
cs= VCC
10
15
pF
CVGG
VGG Capacitance,
(Note 1)
At ac
Ground
VOUT= VCC
VGG = VCC
pF
30
Note 3: Th'is parameter is periodically sampled and is not 100% test'itd.
read operation switching time wavefonns
Ib) Power-Down Option INote 1)
la) Constant VGG Operation
r--
~CYCU:TIME~'1/f~
V'HJ:'~
mRESS VIL·
.
~ :,7 r-
cs VrH
C
1
ADDRESS V
t-tqH
1'
Vil
CLOCKED Vce
VOl--+--------------~--~
DATA
OUT
OESElECTlON, OF DATA OUTPUT IN OR·TIE OPERATION
ADDR'SS
::~x:
:-l
\1
C
YD.
c,o,,~
tOVGG
VGGV~G"':""
DATA OUT
INVALID
~
-1\911%_
~:::i
,
·0.-+-...,-----"\
DATA
OUT
V--
Y'H-V'11/.
CYCLE TIME" liF-'---i
r-
tACC=\J~ ~~~~cu
DATA OIJT
,-----DATA OUT
INVALID
VDl-.------
INVALID
V,. j"CT'DN OF DATA OUTPUT 'N OR·TIE O,",RATION
ADDRESS Vll
I
v,.
es
VOH--t---,.
Conditions of Test:
Input pulse amplitudes: 0-4V. t r • tf:S. 50 ns.
Output load is 1 TTL gate; measurements made
at output of TTL gate ((PO:::; 15 I\s,) CL
DATA OUT
VOL
_+-____-}-_______
T
= 15 pF.
Note
1: The
output will
remain valid for
tOHC as Iang as clocked V GG is at V CC. An
address change may occur as soon as the oUtput
is sensed !clocked V GG may still be at V CCI.
Data becomes invalid for the· old address when
clocked VGG is returned to VGG.
Note 2: If CS makes a transition from VIL to
VIH while clocked VGG is at VGG, then
deselection of output occurs at
too
as shown
in static operation with constant VGG-
6-3
N
typical performance cha racteristics
100 Current VI Temperatura
;;:
.!
Iill
.
..
8
~
39
38
37
31i
35
..
Vec = SV
VOO=-IV
VOG =-IV
INPUTS- Vce
OUTPUTS ARE OPEN
34
33
32
31
3D
21
;;:
4
~;
3
2 f--t-
ti=
.....
~=~c~
..~1
i!;
fi
....
ZI
21
0'"
0
100
20 40 &0 10
AMIIENT TEMPERATURE rc)
1 f--I-
...
lZ
,g
I-
z
l!!
8
z
;;
...
5
eo
(Nota
;;:
..
...
.!
...'"
~
ty ~ t--
2
0
-4
!l:
'"
l/f
1
Z
~§
lef=r
0
....
S!;
fAt;
1- ...
-7
-9
-9
3
4
OUTPUT VOLTAGE IV)
0
i-"
til
30
40
SO
60
70
~
700
600
5011
4UU
~ 3Uo
100
1 TIL LOAD
VCC = SV
VDU=-9V
VGG' -IV
TA =2S'C
0
o 10 20 3D 40 50 60 10 80 90 100
0 10 20 30 40 50 60 10 80 90 100
OUTY CYCLE l%l
LOAD CAPACITANCE IpF)
-
700
600
i= SOD
400
100
:g
i=
'"
til
2DIi
20
100
~
ZUD
900
~ 300
10
l-
900
,/
800
~
I
1000
Access Time vs Temperature
-
!!f=OV
-4
Acc:ea Time vs Load
Capecitance
lOUD
:g
j-.:-~
AMBIENT TEMPERATURE ec)
V
lU
Vec =5V
VDO "-IV
VOG '-IV
VOH =ev
-3
-10
i""'"
15
Vec'SV
VOO"-IV
VGG =-IV
VOL -0.45V
1 .1
~c
:o,g
11
ZO
NJ' i"-
0 ...
Z5
0
0
-6
4
~'"'
4S
40 t- CLOCKED VOG'-IV
VOU --IV
35
CS=VIH
TA =zs'e
3D
5
..... V
-3 -Z -1
Sill
Average Current vsOuty
Cycle for Clocked VGG
/
4
SPECI~IEO
OPERR~~:~
SUPPLY VOLTAGE IV)
10
6
E
0'"
-S
Vee' SV
VOO" -IV
VGG --9V
TA =Z5'C
8
5
;;:
iii;:
-4
lZ0
16
14
A
z
o t-vcc'&V
VGG"-IV
-3
VOL =G.45V
TA ·25"C
-3.5
Output Sink Current vs
Output Voltage
;;:
..
5
ZE
iii;:
!!foov
Output Current VI Ambient
Temperatura
Output Current vs Voo
Supply Voltage
1 TTL LOAD" "ZO pF
VCc·SV
Voo=-9V
VGG "-:9V
0
0 10 ZO 30 40 50 80 70 80 10
AMBIENT TEMPeRATURE ('C)
6-4
~National
~. Semiconductor
MOS ROMs
MM4243/MM5243 2048-bit read only memory
general description
The MM4243/MM5243 is a 2048·bit static Read Only
Memory which is electrically programmable and uses
silicon gate technology to achieve bipolar compatibility,
The device is a non·volatile memory organi;!ed as 256
8·bit words or 512 4·bit words. Programming of the
memory is accomplished by storing a charge in a cell
locatio!) by applying a -50V pulse. Although a PROM
die is used, factory programming is required, Separate
outPUt supply lead· is provided to reduce internal power
dissipation in the output stage (VLL).
features
•
Pin compatible with MM5203Q, EPROM and the
MM5213 masked ROM
•
•
Static operation - noclocks required
Common databusing(TR I.STATE@output)
•
•
Chip select output control
256 x 8 or 512 x 4 organization
applications
•
•
Code conversi on
Random logic synthesis
•
Electrically programmed for fast turn·around
•
Table look·up
•
Bipolarcompatibility
•
Ch.aracter generator
•
High speed operation
•
Micro'programming
+5V, -12V operation
11ls max access time
block and connection diagrams
If01
CONT-~
" Vss
AI
AS-..-----,
co
Dual·ln·Line Package
'3
1108
22 Vss'
lS8A1
_ _- - '
21M
B1
OUTPUT
AI
A2
Al ·A4· ;"7
typical application
BZ
20 AS
.."
.."
19,A6
~7
AI
18 Vi:JD
B1 10
15 MODE
CONTROL
Bi'l
14
Vss 12
cs
13 A!I MSB
""-------'
256 x8 PROI).I Showing TTL Interface
TOP VIEW
Order Number MIIII4243J or MM5243J
See Pac""gell
Operating Modes
256 x 8 ROM connection (shown)
Mode Control-HIGH (VSS)
A9
-LOW
512 x 4 ROM connections
Mode Control - lOW (GND or VOD)
A9
- Logic HIGH enables the odd (B1, B3 ... B7) outputs
A9
- Logic lOW enables the even (82, B4 ... B8) outputs
The outputs are enabled when a logic LOW is appl ied to
the Chip Select line.
absolute maximum ratings
All Input or Output Voltages with Respect
to
Vss
0.3V to -20V
1W
Power Dissipation
Operating Temperature Range
MM4243
MM5243
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
-55°C to +85°C
O°Cto +70°C
-65°C to +125°C
300°C
electrical characteristics
TA within operating temperature range, VSS = 5V ±5%, VDD = VLL= -12V ±5%, unless otherwise noted.
CONDITIONS
PARAMETER
III
Input Current
MIN
TYP
MAX
UNITS
VIN =OV
1
ILO
Output Leakage
VOUT= OV, CS = VSS - 2
1
IJA
ISS
Power .Supply Current
CS = VSS - 2, TA = 25°C
55
mA
VIL
Input LOW Voltage
VSS-l0
VSS-4
V
VIH
Input HIGH Voltage
VSS-2
VSS+0.3
V
VOL
Output LOW Voltage .
1.6 rnA sink, _12.6V < VLL <-3V
0.4
V
ICF
Output Clamp Current
VOUT=-lV, TA=O°C, (Note 4)
6
15
mA
mA
35
VLL = -3V
3.5
V'LL = -12.6V
8
VOH
Output HIGH Voltage
0.8 mA source
TOH
Data Hold Time
(Min Access Time), (Figures 1 and 2)
TACC
Access Time
TA = 25°C, (Note 2),(Figures 1 and 2)
TCO
Chip Select Time
TOO
tcs
IJA
V
2.4
100
ns
1
jJ.S
(Figures 1 and 3)
500
ns
Chip Deselect Time
(Figures 1 and 3)
500
ns
Allowable Chip Select Delay
(Figures 1 and 2)
100
n,
.'.
0.7
Allowable delay in selecting chip after change
of address without affecting access time
CIN
Input Capacitance
VIN = VSS, f = 1 MHz, (Note 1)
8
15
pF
COUT
Output Capacitance
VOUT= VSS,CS= VSS - 2, f= 1 MHz,
(Note 1)
8
15
pF
Note 1: Capacitances are not tested on a production basis but are periodically sampled.
Note 2: TACC = 1000 ns + 25(N-l) )IIIhere N is the number of chips wired-OR together.
Note 3: Measured under continuous operation.
Note 4: ICF flows out the VLL pin, it does not flow out the VOO pin.
typical performance characteristics
Maximum Access Time (T ACC)
as a Function of VOO Supply
Voltage
Maximum Supply Current ISS
as a Function of Temperature
1100
'"=+=+=+++::';;;;;':7.j;:::j
I-
VSS=4.75V
15DO
1--+-+-++-1-- VLL • Voo
I--+-+-++-I--t--t--l-;
1400
1=l~;++++=H~
1200
1--+-+-,....o:Ir-...f-"''''''':I-+-+~
1600
~1300 I--~~~~~~r-I--+-+-+~
-511 -25
0
25
50
-9
75 100 125
-10
-11
VOD (VOLTS)
TAI'C)
6-6
-12
-13
access time diagrams
5V±5%
-IZV±5%
FIGURE 1. AC Test Circuit
H~I--------------------------~X==V~-2V
L
ADDRESS
!
~--------------......
.
VSS-4V
Vss -2V
tlrrInA"'OUT
DATA OUT
, -_ _V_A_l_ID_ _-,~i2l~~LlO
DATA OUT
~
1-1
_ _ __
FIGURE 2. Ace... Time From Address
, - - - - - - Vss - tv
CHIP SElECT
VSS-4V
DATA
FIGURE 3. Aceess Time From Chip Select
6·7
~NaHonal
MOS ROMs
~ Semiconductor
MM4244/MM5244 4096-bit read only memory
general description
The MM4244/MM5244 is a 4096-bit static Read Only
Memory which is electrically programmable and uses
silicon gate technology to achieve bipolar compatibility.
The device is a non-volatile memory organ ized as 512
words by 8 bits per word. Programming of the memory
is accomplished by storing a charge in a cell location by
applying a -50V pulse. Although a PROM die is used,
factory programming is required. A logic input, "Power
Saver," is provided which gives a 5:1 decrease in power
when the memory is not being accessed.
Pin compatible with the MM5204 and the MM5214
Standard power suppl ie,
5.0V, -12V
Static operation-no clock requiTed
Easy memory expansion-TRI-STATE® output Chip
Select input (CS)
• Low power dissipation
• "Power Saver" control for low power applications
features
•
•
•
•
•
•
•
•
•
Electrically programmed for fast turn-around
Fast access time
MM4244
MM5244
DTUTTL compatibility
•
•
•
•
applications
1.25/1,
l/1s
Code conversion
Random logic synthesis
Table look-up
Character generator
Microprogramming
Electronic keyboards
block and connection diagrams
Dual-I n-Line- Package
AU
...,l!.VLl
Al
.,E-VDD
A2
A3
X
DECODER
INPUT
BUFFERS
4096-BIT
ROM
512
J(
CHiiiSEITCf
Vll
2J
POWER SAVER
"""!'-'vss
MATRIX
2.
Vss
VOO
3
12 81
.-.!!-vss
8
21
Vss
~Vss
A'
20
A6
AS
A6
Al
"
A2 7
18
A3 8
17
A7
POWER SAVER
A8
16
A.
CONTROL
CIRCUITS
CS
A5 10
15
11
I.
12
13
A6
Vss
B6
E5
E'
E3
.,"
BO
AB
A7
22
TOP VIEW
80 81 82 83 84 85 B6 81
Order Number MM4244J or MM5244J
See Package 11
6·8
absolute maximum ratings
(Note 1)
All Input or Output Voltages with
Respect to Vss
Power Oissipation
Lead Temperature (Soldering, 10 seconds)
dc electrical characteristics
Operating Temperature Range
MM5244
O.3V to -20V
750mW
300°C
DOC to +70 o e
-55°e to +85°e
--65°e to +125°e
MM4244
Storage Temperature Range
TA within operating temperature range, VLL
= OV, MM4244:
VSS
= 5V ±10%,
VDD = -12V ±10%, MM5244: VSS= 5V ±5%, VOD =-12V ±5%, unless otherwise noted.
PARAMETER
CONDITIONS
TYP
(Note 5)
MAX
Vil
Input low Voltage
VDD-14
VSS-4.2
VIH
Input High Voltage
VSS-1.5
VSS+0.3
IU
Input Current
VIN
VOL
Output low Voltage
IOl = 1.6 rnA
VOH
Output High Voltage
IOH
I LO
Output Leakage Current
VOUT ~ OV,
I DO
Power Supply Current
TA=O°C,CS~VIH
ISS
OV
V
V
1
~-0.8rnA
pA
Vll
0.4
V
2.4
VSS
V
CS ~ VIH
1
pA
40
mA
50
mA
mA
mA
Power Saver = V1L
Power Saver;;::: VIL
28
MM5244
Power Saver -= V I H
6
MM4244
Power Saver == V I H
8
10
MM5244
Power Saver == VIL
42
MM4244
Power Saver = V IL
52
mA
MM5244
Power Saver = VIH
10
mA
MM4244
Power Saver:= VIH
12
mA
ac electrical characteristics
VDD
~
UNITS
MM4244
MM5244
mA
TA within operating temperature range, VLL = OV, MM4244: Vss = 5V ±1O%,
= -12V ±1O%, MM5244: Vss =5V :!:5V, VDD = -12V ±5%, unless otherwise noted.
PARAMETER
tACC
t
MIN
IPO
tco
Access Time
CONDITIONS
TA = 70"C
MM4244
TA = 85°C
MAX
UNITS
0.75
1
/1S
1.25
/1S
(Figure 1),
MM5244
1.8
ps
MM4244
2
!-IS
Chip Select Delay
(Figure 1)
MM5244
500
ns
MM4244
600
ns
30
50
MM5244
30
300
500
ns
MM4244
30
300
600
ns
ns
tOH
Data Hold Time
(Figure 11
'ODC
Chip Select Dese!ect Time
(Figure 1)
tODP
TYP
(Note 5)
(Figure 1), (Note 4)
MM5244
Power Saver Set-Up Time
MIN
Power Saver Deselect Time
ns
(Figure 1)
MM5244
30
300
500
MM4244
30
300
600
5
8
pF
8
15
pF
CIN
Input Capacitance (All Inputs)
VIN ~ VSS, f
COUT
Output Capacitance
(AIIOutputsi
VOUT ~ VSS, CS ~ VIH
f ~ 1 MHz, (Note 2)
=
1 MHz. (Note 2)
ns
Note 1: "Absolute Maximul;11 Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides co~ditions for actual device op~ratjon.
by periodic 'testing.
Note 3: Positive true 'logic notation is used
Note 2: Capacitance is guaranteed
Logic "1".= mOst positive voltage level
Logj'c "0" == most negative voltage level
Note 4: 'ACC = 1000 ns + 25 (N-1) where N is the number 6f devices wire-OR'd logether.
Note 5. Typical values are for nominal voltages and T A -= 25CJ C,onless otherwise specified.
6·9
ac test circuit
5.0V:':5%
Vss
TYPICAL
INPUT
MM4244/
MM5244
EJM74[]O
AO-A8
OV
'tAce, tOH. teo and too measured at output of MM4244/MM5244
typical application
CHIP
SElECT
'"'"~{
80
INPUTS
MM4244/
MM5244
87
,t5%
Voo
5.0V ±5%
VSS
OV
Vn
~12V
POWER
ON
switching time waveforms
V,H
AOORESS
V,l
____________
~----AO-O-R-E-SS-S-T-A8-l-E------
--.-..,---
v,
POWER SAVER
V,l
CHIP SElECT
DATA
Vll _ _ _ _ _ _ _ _-'-I_'-"___I--___- J
our
Note: All times measured with respect to 1.5V level with tr and tf:::; 20 ns.
FIGURE 1. Read Operation
6-10
preferred format
MM1742.MM4243/MM5243. MM4244/MM5244
The custom patterns may be sent in. on a Telex or submitted as a paper tape in a 7·bit ASCII code from model 33 tele·
type or TWX. The paper tape should be as the following example:
St?ort Character
l
Stop Charact."
Leader: Rubout for
T:~t~;e':t,~;,~:,;
fr
Carriage return line feed
allowed between,F and B.
1. I ,
..'Data Fi'e. Id"
MSB (Pin 11)
~
I
LSB (Pin, 4)
~
Trailer: Rubout for
TWX or letter Key
for telex' (at least
B P P P N P P N N F B N N PP N N P P F . . B N P N P N N N N F
I\..~_ _- - . . . - - - -
25 frames!.
Ward 0
25
Word ,1
,
WordS11
All Address Inputs LOW
frames~.
,
All Address Inputs HIGH
*Oata Field:, Must have only P's or N's typed b'etween Band F,. No nulls or rubauts. Must have exactly eight P and N characters between
Band F. Any characters except 8 and F may be typed between the F stop character and the B start character .-If an efror is made in p,reparrng. a tape. the entire word including the -B and F start and 'stop 'characters n:-ust be' rubbed out. Data for exactly 256. or 512 VV'ords
must ~ entered beginning with word O.
alternate format
MM1742. MM4243/MM5243. MM4244/MM5244
[Punched Tape (Note 1) or Cards]
b7. MSB (Pin 221
MM __ ,-_
bOo LSB (Pin 151
Positive Logic
2 Spaces
--+---,--,
i\llf) I)
()flnn,)nnn n
~'\ (). 1 1
i\nn<:,
,\nnJ
(I.)n",
.\!Hl')
;:,I);'n
-
~'\
TBJ
T81
4
f)rllil I I I
r)[1f1 I I 11)f)
,
"
"
(j')l),lI)r)f)'1
I I I 1 nn
n I,' I '111) 1
14n
1 Space
0
4
"
-
Note4
l'1fl
'S;l
4nn
oln
100
fB2
T 80
1)\ 01:1 In I
(In<"lr)'-l'lnn
51I
TBI
TBG
TBo
TS4
n
nn
\"),;{
!\I")~
---->.'\""""-Note 3
0(1f1'111 1')1') 11
t
;,?9Q
J9 7
1 Space
Note 1: The code is a 7-bit ASCII code .on 8 punch tape. The
tape should begin and end with 25 or more "RUBOUr: punches.
Note 2: The ROM input address is expressed in decimal form
and is preceded by the letter A.
Note 3: The total number of "1", bits in the output word.
Note 4: The total number of ", .. bits in each output'colurim or
bit position.
6·11
~National
MOS ROMs
~ Semiconductor
MM2316A 16.384-bit read only memory
general description
features
The MM2316A is a static MOS 16,384-bit read-only
memory organized in a 2048-wqrd-by-8:bit format.
It is fabricated using N-channel enhancement and
depletion-mode silicon-gate technology which provides
complete DTLITTL compatibility and single powersupply operation.
•
•
•
•
•
•
•
•
Three programmable chip selects controlling the TR 1STA TE® outputs allow for memory expansion.
Fully decoded
Single 5V power supply
Inputs and outputs TTL compatible
Static operation
TRI-STATE outputs for bus interface
Programmable" chip selects
2048 word by 8-bit organization
Maximum access time-450 ns
applications
Programming of the memory array and chip·select
active levels is accomplished by changing one mask
during fabrication.
• Microprogramming
• Control logic
• Table look-up
block and connection diagrams
logic symbol
Dual-I n-line Package
A7
A8
A9
AID
A7
Z4 Vee
AI
23 01
AI
AD
AID
A2
A3
Al
AD
AD
Al
A4
05
AS
AZ
06
AS
A7
A8
A3
07 .
Al
A2
MEMORV
MATRIX
2048 X I
A3
A4
AS
MMZ316A
A6
08
A4
A5
CSI
CS2 CS3
01 02 03 04 05 06 07 08
10
CSI
A6 11
14
GNO 12
n
TOP VIEW
Ortler Number MM2316AJ
Sae Package 11
Order Number MM2316AN
See Package 1SA
6-12
CSZ
CS3
01
02
03
04
05
06
07
08
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Lead Temperature (Soldering, 10 seconds)
dc electrical characteristics
....
-
,1f)OJ
t SP'"
A,V' ...
Note 2
""orr,
"':'')
rrpr\llJ1'I'l
'I
r)'l'l·I'ln'1'l
n·"1IIII00
I)
ClI·'IIlI'!1
"
4
i;,;" 140 _ _ _ _ _+_Note4
iE-7 I
~rI
Ti:." ·'5,1
If,S 4'1'1
B-Bit Tape Format
Note 1: The code is. 7-bit ASCII code on 8 punch tape.
Note 2: The ROM input address is expressed in decimal form and is preceded by the
letter A.
Note 3: The total number of "1" bits in the output word.
Note 4: The total number of "1" bits in each output column or bit position.
Nato 5: Specify product type.
Note ·6: Must type POS logic, or NEG logic depending on ,which is u""d. Logic on addresses
and outputs must be the ""me leither POS or NEG).
Note 7: Specify the pattern necessary to select the ROM.
L_~======:t-1Space
6-14
card entry format
s:
s:
N
...
...en
W
12345618910 II 12 13 14
I~
16 11 18 19 20 2\
n
23 24 25 26 <7 2819:W 31 32 33 34 35 36 37 3B 39 40 41 424344454647 4e
4~
5051 525354 55 56 57 58 sa so 61 626364 65 66 67 6a 69 7071 72
n
74 1'S 71> 77 78 79 80
--.---'.~~-~--~.-.-.--.----~
Ic:-:-c--.,---:-:c-:-------..----~---~- ... ----
.----~-----'-------_--_i
------
----'--~-.-~~-~---- ..
f.":':'':''....:cX-":.:.-=-t.C-,'...
__,______ ~____,-'--..~----.---~-~_________- - ,...
+
--~.------.-_._~
F--=----=-F'----~------··-~-····-~·-~---··-~~-~---~-------·--·----
~-~-~----------.---.-'-~-~- ... "---.--.~-.---~----.--.--------~-~~~-~--_i
bS
NO •• S
l-::oo=-_ _==::::",,-,1~.4
btl,
.'
__ ~_ _~_. __ ~_ _ _ . _ _ _ _
. _ _ _~
AOoOO 000(1)(100
00000000
0(1000000
01010101
4
'~o.'<_,_____._'.'__ ,~. ________._._.. _
~------~'-I
r
r
0011,,11
~:'o:c-:-:==..c:_:_:':__:_:-:_:__==-.--~.--~--
'--.
-------------~----------_j
I--c:---,-----------------c--_-~~-----------
rc-=-'---'-t---~~---.--.-.~-~~-
..-... ~-- --.---- ... ~~- -..
.- -.---....~."- ....~.------~--.- . -------~__1
.•.. .-.------..
....
_._
~.----.--~
...
r~"_I_~___:------~· .-~--.----~ ...
r'--""_I____:-------·--·-----------·-·-· .
... -.--~---~--
;.:.::.:-='--I----------~.---~.-~-.-
~.---~.-.--
... -- .------~-----.
F--'''--+.::::.c..:--~·------~------~~-~··~---~
-.... - -
- ~----~
~
---~--
~.~-.------
--~--.-
F--=:+--··--~--·~-·--·
---.-----------.~~
~~.-----------~--~-----'-_1
,-~---.-~.--~----------.---
..- - - . - - - - -----.~~-__i
--~---.-------.-~------~-~-------j
..--.~. -------.... ~.--.----~---_____1
... ~ .--~-~-~-----~.----- .. - - - - - - - - - - - i
1------._----------- .. --~..- - - -..---. --.~-----~-.- .. ~ ....~----.-~---- ...~------1 - - - - - - - - - - - - ---~-.-- --'-' ~------.. - ...-.. --~~-..-.---.-.~---.---.-..- - - - - - - _ i
f - - - - - - - - - - - - - - - . -..--. - -
1-------_.__ .. _._-----1234567891011121314151617 IS Ig 202' '1'2
n
.---~--
..~ --.-.----- ....~ ~~--------------'
.
-
.... - - - ..- .. -.-
..
----.-.-.~--.-~---.--~--~-~
.. - ; - -
14"l'> 2627 282g3~.J;-J?3J-3-43~36-3:;383940414243.U4S~~47484-s-5oSi""~5s5657~S85s6U~61-6263646-56S"6,S8&91071 727374 75 7677 7B
1eao
~'-----------------------~--~--------------~--------------~
Note 1: Specify product type.
Note 2: Must type POS logic or NEG logic depending on which is used. Logic on addresses, outputs and chip seleds must be the
same (either POS or NEG).
Note 3: Specify the chip select logic levels that will enable the ROM.
Note 4: The first ROM input address per card is expressed in decimal form and is preceded by the letter A.
Note 5: Punch fQur address locations per e;ard# .only .first location_on each carp has the address location expressed in decimal form.
Note 6: The total number of "1 U bits in all four addresses.
Note 7: Leading zeros must be punched.
Note 8: The tota"' number of 011" bits in each output column or bit position.
6-15
l>
~National
MOS ROMs
~ Semiconductor
MM4210 I MM5210 1024-bit read only memory
general description
no clocks required
output wire AND
capability
• Chip enable output control.
The MM4210/MM5210 is a 1024-bit static read
only memory. It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold technology. The device is a non·volatile
memory organized as 256-4' bit words. Programming of the memory contents is accomplished by
changing one mask during device fabrication. Customer programs may be supplied in a tape, card, or
pattern selection format.
• Static operation
• Common data busing
applications
•
•
•
•
•
features
• Bipolar compatibility
• High speed operation
500 ns typ
Code conversion
Random logic synthesis
Table look·up
Character generators
Microprogramming.
block and connecti'on diagrams
Dual·ln·Line Package
INPUT As
16
VOD
INPUT A,
15
INPUT A4
LSD INPUT A1
14
INPUT A5
lSB OUTPUT B,
13
INPUT At>
12
INPUT A7 MSB
SENSE
INPUTS
OUTPUTS t
AMPL.fFI£AS
(tSB) A,
6, (lS8)
A,
B,
OUTPUT 82
OUTPUT BJ
,
11
VGG
"
CHIP
ENABLE
B,
MSB OUTPUT 84
7
v"
B
B,
A.
INPUT As
TOP VIEW
CHIP'
*The output is Enabled by applying
ENABLE
a logic "1" to the Chip Enable line.
tThe outputs are connected to
VOD through an internal MOS
resisttJr when Disabled.
Order Number MM4210J Or MM5210J
See Package 10
Order Number MM5210N
See Package 15
typical application
256 x 4 Bit ROM Showing TTL Interface-12V _ _ _ _. . -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.............._ . . - - .
+---<.-...._..-------------,
+12V _ _ _ _
.5V---.--+-t--t-+-----------+--~-t-+-t---~-
...
(
l.OK
AB
J.OK
6.IIK
CHIP
'Io--t_+_....._---!';:.A:::B~LE"IIO
7 B,
'-~:-_ _ _ _...:VG"'tG 11
6 B,
UK
UK"
B,
'10-,---....------412
MM42'10/MM5210
UK
B,
1l
DTl/TTl lOGIC
14
15
Voo
'"'Resistor value can vary from 150n
to 30 kit depending on speed requirements.
':"
Note: For programming information see AN-100.
6·16
absolute maximum ratings
V G G· Supply Voltage
Voo Supply Voltage
Input Voltage
(V ss -20)V
Storage Temperature
.
Operating Temperature MM4210
MM5210
Lea.d Temperature (Soldering, 10 see)
<
Vss-30V
V ss -15V
V'N
(Vss +0.3)
_65°C to +150°C
_55°C to +125°C
O°C to +70°C
300°C
<
electrical characteristics
TA within operating temperature range, Vss~ +12V ±5% and VGG ~ -.12V ±5%, unless otherwise specified.
PARAMETER
Output Voltage Levels
MOSto MOS
Logical "1"
Logical "0"
MOSto TTL
Logical "1"
Logical "0"
CONDITION
1 MQ to GND Load
MIN
TYP
MAX
UNITS
Vss -9.0
V
V
+0.4
V
V
Vss -8.0
V
V
Vss -1.0
6.8 kQ to V GG Plus One
Standard Series 54174 Gate Input
+2.4
Input Voltage Levels
Logical "1"
Logical "0"
Power Supply Current
Vss
V GG (Notell
Vss -2.0
TA
= 25°C
19
Y'N = Vss-12V
I nput Capacitance
f; 1.0 MHz
Access Time (Notes 2, 31
T A ; 25°C
(See Timing Diagram)
Vss; +12V V GG ; -12V
Output AND Connection
mA
}J.A
I nput Leakage
T ACCESS
25
/lA
pF
5
V'N= OV
150
MOS Load
TTL Load
500
650
ns
3
8
Note'1:· The VGG supplV may be clocked to· reduce ,device power'without affecting access time.
Note 2,: Address time is measured from the change 9f data'on any input or 'Chip Enable line to the output of a TTL gate.
See Timing Diagram.
Note 3: The access time in the TTL load configuration follows the equation: TACCESS
where N :; number of AND connections.
6·17
=
the specified time + IN - 11 1501 ns
g
performance characteristics
Guaranteed Access Time vs
Supply Voltages
ITA"25'C
1000
..,
Typical Access Time vs
Supply Voltages
1000
TA.::: 7f1"C
800
!! 600
~ 600
J
800
]
TA - 25°c
oS
~
I-
400
400
12S'C
200
tt+
I-\./oci 1);-[
200
2S'C
10.8
13.2
12.0
tn.8
Vss & VGG (V)
Power Supply Current vs
Voltage
Power Su pply Current vs
Temperature
TA -ZSOC
24
I
GUARANTEED
26
.Y
22
<:
.E
..If
TYPICAL
20
;;:
22
.§
e
.Ii 18
Jl
16
14
18
13,2
12.0
~UARA.TEEo
l"'-
"' ....
......
f'..
TYPICAL
-50 -25
Vss & VaG (V)
Vss :;+12:0V
VGG' -12.OV
"'\
"\
14
10.8
13.2
12.0
. Vss & VGG (V)
0
25
50 75 100 125
TEMPERATURE I'C}
timing diagram/address time
+lv
I
.3TL
I
l.OK
'5V
INPUT AN
'5V
MM4210/MM521U
EIN/
DV
OM8810
DM8812
-:T'DPF
.f
I
OUTPUT ~
* *
101l'F.L
I
6.8K
ANYDTl/TTL .L1!iPF
GATE
..Iv
+12V
r------,
EITHER
DV
E"
+12v
DV
'JV
~
I~
~T""~I
~
1.5V
0
Eour
.3.
DV
1.5V
I
time
EOUT
~National
MOS ROMs
~ Semiconductor
The MM4211/MM5211 is a 1024-bit static read
only memory. I t is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold technology. The device is a non-volatile
memory organized as 256-4 bit words. Programming of the memory contents is accomplished by
changing one mask during device fabrication.
• Common data busing
output wire AND
capability
• Chip enable output control
applications
•
•
•
•
•
features
+5V. -12V operation
< 700 ns typ
no clocks required
Code conversion
Random logic synthesis
Table look-up
Character generators
Microprogramming
Dual-In-Line Package
block and connection diagrams
INPUT AJ
SENSE
AMPLIFIERS
INPUT Al
15
INPUT A4
LSB INPUT A,
14
INPUT
LSD OUTPUT 81
13
INPUT AI;
OUTPUT B2
12
INPUT A1 MSB
10
CHIP
ENABLE
OUTPUTS t
A~
H, (LSB)
B,
OUTPUTB3
B,
MSB OUTPUT B.~
1
V"
,
B,
' -_ _ _-19
INPUT As
TlIiVIEW
*The output is Enabled bvapplyinga logiC "l"to the Chip Enahlelme.
Order Number MM4211J
or MM5211J
See Package 10
CHIP'
tTht outputs are Cllnnected to Voo through an IIIternal MOS resistor
\lllhenDisabled.
ENABLE
Order Number MM5211N
See Package 15
typical application
256 x 4 Bit ROM Showing TTL I ntorlaco
........-..,
-I2V----.------------------.~
....~
.,v-.--4-----------------~-4--r__i-_t~A.
,-{
6.BK
CHIP
ENABLE
1i,IIK
6.8K
6.aK
B,
}...
10
v"
A,
ANYL~~~~TTL :
I
I
B,
I
I
"
B,
MM42111MM~211
B,
ANY Dil/TTl
LDGIC
14
I
I
I
"
"
"
"
Vpo
t :
~
....
....N
.......
MM42111MM52111024-bit read only memory
general description
• Bipolar compatibility
• High speed operation
• Static operation
s:
s:
16
1
Note: For programming information see AN-100.
6-19
s:
s:c.n
........N
absolute maximum ratings
Vss - 20V
VGG Supply Voltage
VSS -20V
Voo Supply Voltage
Input Voltage
(V ss - 20)V < ViN < (V ss +0.3)V
-65°C to +150°C
Storage Temperature
_55°C to +125°C
Operating Temperature MM4211
MM5211
O°C to +70o C
300°C
Lead Temperature (Soldering, 10 sec)
electrical characteristics
TA within operating temperature range, Vss = +5V ±5%, VGG = Voo = -12V ±S%, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
6.8K ±5% to VGG Plus One
Standard Series 54/74 Gate
+2.4
TVP
MAX
UNITS
+0.4
V
V
Output Voltage Levels
MaS to TTL
Logical" ,.'
Logical· "0"
Output Current Capability
Logical "0"
V OUT = 2.4V
Input Voltage Levels
Logical "1"
Logical "0"
Power Supply Current
IOD
IGG (Note 1)
Vss - 4.2
Vss - 2.0
Input Capacitance (Note 4)
V GG Capacitance (Note 4)
f = 1.0 MHz, VIN = OV
f = 1.0 MHz, VIN = OV
Address Time (Note 2)
See Timing Diagram
TA = 25°C,
Vss = 5V
VGG = Voo = -12V
12.0
1
mA
p.A
1
p.A
5
15
25
pF
pF
700
950
ns
6.5
Vss = +5V
VGG = Voo = -12V
VIN = Vss - 12V
Output AN D Connection
(Note 3)
V
V
TA = 2SoC
I nput Leakage
T ACCESS
mA
2.5
6.8K ±5% to VGG Plus One
Standard Series 54/74 Gate
Note 1: The VGG supply may be docked to reduce device power without affecting access time;
Note 2: Address time is measured from the change of data on any input Of Chip Enable line to the
output of a TTL gate. (See Timing Diagram.) See curves for guaranteed limit over temperature.
Note 3: The address time in the TT.L load configuration follows the equation:
~ The specified limit + (N -1) (50) ns
Where N : : : Number of AND connections.
T ACCESS
Note 4: Capacitance guaranteed by design.
6·20
8
performance chara'cteristics
Power Supply Current YS
Power Supply Voltages
Power Supply Current vs
Ambient Temperature
16
16
Vss '" +5.0v
Voo'" VGG
TA'25C
14
14
Voo - VGG = 7.2V
12
12
MAXIMUM
MAXIMUM
~ 10
Q
.E
10
~
.§
.§
8
8
TYPICAt_
Q
a
6
6
TYPICAl.
4
4
2
2
0
0
1).0
16.0
18.0
-50 -25
1400
Voo
800
~
100
125
1200
"25'"C
1 1000
+10°C
J
+125°C
+25~C
!IE
;:: 600
9
15
Voo := VGG
]
1 '000
~
50
1400
=VGG
1200
to
25
Guaranteed Access Time vs
Power Supply Voltages
Typical Ace",," Time.vs
Power Supply Voltages
~
0
AMBIENT TEMPERATURE ("CI
Vss - VaG (V)
+70"C
+25"'C
800
!IE
;:: 600
~
400
400
:;!
200
200
0
0
litO
18.0
11;0
16.0
17.0
18.0
Vss - VaG (V)
Vss - VGG (V)
timing diagram/address time
.5V
'5V
·JTL
,V
'5V
1
I
ANYG~WDTl
E,.~.
..
~ lOp'
'1
I
OUTPUT Btoll
'NPUT A:rj
I1
MM421I1MM!i211
Eolly
lOIlF.L
UK
~
ANVTTL/DTl
GATE
.,Iv
v!;& -2Dv
E,.
,v
'5V
.J'Vv
~
Vss -42
E'"""- •
i;:.Jv"."
1.SV
,
EOUl
·JV
t5V
'v
I
.. tIme
6·21
l
~
15Pf
~National
MOS ROMs
~ Semiconductor
MM5212 12,288-bit read only memory
general description
The MM5212 12,288-bit read only memory is a
P-channel enhancement mode monolithic MaS
integrated circuit utilizing a low threshold voltage
technology and ion-implanted resistors. Open drain
outputs provide a TIL compatible wire OR capability with the addition of a 6.8 kn resistor. The
ROM is organized in a 1024 word by 12-bit
organization.
•
Standard suppl ies
Open drain outputs
•
Static operation
•
TTL compatible inputs and outputs
No clocks
applications
features
+5.0V,-12V
•
Character generator'
•
Random logic synthesis
•
Microprogramming'
•
Table look-up
schematic diagram
0'2 (MS.)
0"
0,.
0,
0,
0,
OUTPUT
DRIVER
0,
0,
0,
0,
0,
0 1 (LSB)
*The output is enaWed by applying a Logic High to the Chip E... bll.
"CHIP ENABLE
connection diagram
Dual-I n-Line Package
Ne
VDD
MS'
0.,., Ou
0 10
0.
O.
0,
O.
CHIP
05 ENABLE 0..
03
O2
"
A3
Note: For programming
information see AN-IOO.
Az
TOP VIEW
Order Number MM5212AD
Sae Package 7
A10
MSa
A,
UB
A.
Aw
A,
0,
LSB
Order Number MM5212AN
See Package 19
6-22
Wire OR capability
•
absolute maximum ratings
Vss + 0.5V to Vss - 22V
800mW
O°C to+70°C
-65°C to +150°C
300°C
Voltage at Any Pin
Power Dissipation at 25°C Ambient
Operating Temperature
Storage Temperature
Lead Temperature ISoldering, 10 seconds)
electrical characteristics
TA within operating temperature range, Vss ; +5.0V ±5%, V DD
CONDITIONS
PARAMETER
;
-12V ±5%, unless otherwise specified.
MIN
Data Input Levels (Note 1 )
Logical High Level (V IH )
Logical Low Level IV IL )
TYP
UNITS
+0.8
V
V
+0.4
V
V
+2.8
Data Output Levels INote 1)
Logical High Level (V OH )
Logical Low Level IV 0 L)
6.8 kQ ±5% to V DD Plus One
Standard Series 54/74'Gate
Output Current Capability
Logical High Level IV IH
V OUT
)
Power Supply Current
= 2.4V
T A ; 25°C, Vss
V DD = -12V
IDD
Standby Power Dissipation
Input Leakage
+2.4
mA
2.5
= +5'OV
6.0
= -12V
Vss =+5.0V, V DD
Chip Enable LOW
V IN = Vss -10V
Address Time
..
TAccEss
MAX
See Timing Diagram
T A ; 25°C, Vss =+5.0V
V DD =-12V
3.5
Note 1: Positive logic definition.
switching time waveforms
><==
ADDRESS==::x_ _ _ _ _ _ _ _ _ _ _
CHIP ENABLE -~---
-j-I.SV
i
-T-
[--'IOATA NOT VAlIOI---!
OATAOUTPUTU~-- _ ..
uu_
-
-
-
-,~~.,r-----"'L
~TAO""-~
10.0
mA
170.0
mW
1.0
IJ.A
5.0
IJ.S
a
~National
a
MOS ROMs
Semiconductor
MM4213/MM5213 2048-bit read only memory
general description
The MM4213/MM5213 is a 2048-bit static read
only memory. It is a P·channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold voltage technology. The device is a nonvolatile memory organized as a 256-8 bit words or
512-4 bit words. Programming of the memory
contents is accomplished by changing one mask
during the device fabrication.
• Static operation
features
•
•
•
•
•
• Bipolar compatibility
• High speed operation
No clocks required
Output wire AND
capability
• Common data busing
• Chip enable output control
• TRI-STATE output
applications
+5V, -12Voperation
600 ns typ
• Pin compatible with MM5203 pROM
Code conversion
Random logic synthesis
Table look-up
Character generator
Microprogramming
block and connection diagrams
Dual-In-Line Package
..
INPUT A,
A' "sal
A,
\
:
I
liIPOTA4
LSI OUTPUT 8f
B,
I
A,
N'
LSllIffIUTA1
a,
A,
INPUTS
V"
Ne
IfIIPUTA t
MEMORY
ADDRESS
DECODER
"
..
OUTPUTS
OIlTflUTBI
IIIfIUTA5
OUTPUT III
IIIPllr",
,OUTPUT B..
IIU'UTA1
"
OUmlTi,
INPUTA. MS8,
B,
DUT'P1,IT1le
v~
..
UOOE
OUTPUT B7
CONTROL
IIISB OUTPUT I,
11
v"
"
ENABLE
""
TO'VIEW
"
IIIPUrAa
Order Number MM4213J
orMM5213J
S"'; Package 11
Order Number MM5213N
SeeP.ck.... 18
Note: For progr.mming information see AN-l00.
6-24
absolute maximum ratin.gs
VLL Supply Voltaile
Voo Supply Voltage
Input Voltage
Storage Temperature
Operating Temperature MM4213
(V ss - 20) V
<
MM5213
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
Vss - 20V
Vss - 20V
V ,N
(V ss + 0.3) V
':"65°e to +150o e
-55°e to +125°e
oOe to +70o e
300 0 e
<
(Note 1)
CONDITIONS
MIN
TVP
MAX
UNITS
Output Current Capability
• 200
V OUT = 2.4V
VOUT= O.4V
Logical "'"
Logical '·0"
IlA
inA
-1.6
I nput Voltage Levels
Logical "0"
Logical ", ..
Vss - 4.0
Vss - 2.0
TA = 25°C
Vss = +5V
V LL = Vee
Power Supply Current
Iss (Note 2)
I nput Leakage
V'N = -12V
I nput Capacitance (Note 5)
f
20
V
V
35
rnA
1
IlA
= -12V
= 1.0 MHz,
pF
5
V'N = OV
Address Time
TA = 25°C. Vss = +5.0V
VGG - Voo = -12.0V
TAccESS
600
850
ns
io
Output AND Connections (Note 4)
Note 1: These specifications apply forVss = +5.0V ±5%, VLL = -12V, and TA = -55°C to +125°C (MM4213). TA =.-25"C to
+70~C (MM5213) unleSS otherwise specified.
Note 2: Outputs open.
Note 3: Address time is measured from the change of data on any input or Chip Enable line to the output of a TTL gate.
Note 4: The address time in the TTL load configuration follows the equation: T ACCESS = The specified limit + (N - ,) (25)
ns. Where N = Number of AND connections.
Note 5: Capacitances are measured on a lot sample basis only.
[II
typical applications (con't)
-uv
..v __
~
______
~
__
~
__________________________
~
______
~~A~'+'~'--------~'~2~
J
L...-+__=
...••",--I
~
___
J
15
" 1-':.'---1
....-""v.-,-I"
'~'''----'
}-
COIITROL
Ae-n
'-0,
,-"
Ar "
~
____~~____~Ae~a
A.!,- Z1
sf-a,
,
,,
,,,
,,
,,
\ DTLITTL LODIC
256x8 R.OM connection (shown)
Ag
I
I
I
,,"
I
I
,
I
1
tSae opel1lting mode notes.
I
1
6-25
- L"i!ic"O"
512x4 ROM connection
Mode Control - logic "0"
As
- Logic "1" Enables the odd
(B,. 83' .. B9) outputs
- Logic "0" Enables the ENen
(B 2 • 8 4 ... 8S) outputs.
I
NC- ..
Operating Modes
Mode Control - logic "1"
I
NC_ U
------~~~8tE
MODE COI'lTAOl
------1-../
Order Number MM4220J
or MM5220J
See Package 1'1
Order Number MM5220N
See Package .18
Note: For programming information see AN-l00.
6-30
a.bsolute maximum ratings
VGG Supply Voltage
Voo Supply Voltage
Input Voltage
Storage Temperature
Operating Temperature MM4220
(V ss -20)V
<
MM5220
Lead Temperature (Soldering, 10 sec)
Vss-30V
V s s-15V
VIN
(V ss +O.3)V
-65°C to +150o e
_55°C to +125°e
oOe to +70o e
300°C
<
electrical characteristics
TA within operating temperature range, Vss = +12V ±5% and VGG = -12V ±5%, unless otherwise specified.
PARAMETER
Output Voltage Levels
MaS to MaS
Logical "1"
Logical "0"
MaS to TTL
Logical "1"
Logical "0"
MIN
CONDITION
1 Mn to GND Load (Note 1)
TA = 2SoC
Input Leakage
Y'N
'Input Capacitance
f
Access Time (Notes 2, 3)
TA = 25°C
(See Timing Diagram)
Vss = +12V VGG = -12V
Output AND ConneCtion
UNITS
Vss -9.0
V
V
+0.4
V
V
V s • -8.0
V
V
+2.4
Vs" -2.0
Power Suppi,y Current
Vss
VGG (Note 1)
TACCESS
MAX
Vss-l.0
6.B kn to VGG Plus One
Standard Series 54/74 Gate Inpu!
Input Voltage Levels
Logical "1"
Logical "0"
TVP
19
= Vss -12V
= 1.0 MHz
Y'N
25
1
mA
tJ.A
1
tJ.A
pF
5
= OV
150
500
650
MaS Load
TTL Load
ns
3
8
Note 1: The VGG supply may be clocked to reduce device power
withou~
affecting access time.
Note 2: Address time is measured from the change of data on any input or Chip Enable line to the output of a TTL gate.
See Timing Diagram.
Note 3: The access time in the TTL load configuration follows the equation: T ACCESS = the specified time
where N == number of AN 0 connections.
6·31
+ (N - 1) (50) ns
a
performance characteristics
Guaranteed Access Time vs
Supply Voltages
Typical Access Time
Supply Voltages
YS
1000
800
.s
"'"
~ 600
~
,.. 400
200
10.8
12.0
125"C
13.2
+,1/+
'7ri·J
200
I-+-H++-++H+I-+-H-H
Vss& VGG (V)
Power Supply Current vs
Voltage
Power Supply Current vs
Temperature
T(1 25"C
GUARANTEED
IA""
TYPICAL
1 2P
8
26
.i...'
22
1
22
18
18
16
14
14
10.8
12.0
13.2
+12V
rI
L
-12V
tlZV
OV
E"
+lZV
.,vov
"
""
GUARANTEED
.......
......
.......
TYPICAl'
I I
TEMPERATURE (OC)
timing diagram/address time
+3V-
"-
I vss" +12.0.V
I vee' -12.0V
I
-50 -25 0 25 50 75 100 125
Vss & VGG·(V)
ov..J
13.2
12.0
10.8
Vss & VGG (V)
24
l't/i
Z5" C/"'I
T"'''~I
1.5V
f:OUT
·,v
1.5V
ov
6-32
I
typical application
128-8 Bit ROM Showing TTL Interface
."v------....._-_____________....................,
..v
"
"
'" "
I:HIP
~NA8U
o,
" "
"
o,
t MODE
COIliTROL
vcu:i
o,
"
MMaZ1lJMM522D
.. .
-{
.,
.,
.
I,
I,
3.811*
A.
I,
"
OMII1D Oft oMII12
.."
tTL GATES
v"
fSeeoperiitingmodenDtts.
"
.
A,
.".
.... R WIIlues can VItfY from ,740 ~o 31) kn depending an speed requirements.
OPERATING MODES
128x8 ROM connection
Mode Control - Logic "0"
A8
- Logic "1"
256x4 ROM connection
Mode Control - Logic "1"
As
- Logic "0" Enables the odd
(6i ... 6 7 ) outputs
- Logic "1" Enables the even
(8 2 ..• 6 s ) outputs.
The o.utputs are "Enabled" when a logic "1" is
applied to the Chip Enable line.
The outputs are connected to VDO through an
internal MaS resistor when "Disabled."
The logic levels are in negative voltage logic notation.
6·33
•
1--
_National
a Semiconductor
MOS ROMs
MM4220AP/MM5220AP
BCDIC-to-ASCII code converter
general description
The MM4220AP/MM5220AP is used for the conversion of the Binary Coded Decimal Interchange
Code(BCOIC) to the American Standard Code for
Information Interchange (ASCII).
The output is a seven-bit ASCII code, with an
eighth bit generated for even parity.
The input is a seven-bit ecolc code with the
exception of the parity (check) bit (pin 18) which
is returned to +12V dc. The alternate set of input
symbols is also shown in the Conversion Table for
reference.
device characteristics
For full electrical, environmental, and mechanical
details, refer to the MM4220/MM5220 1024-bit
read only memory data sheet.
typical application
connection diagram
Dual-tn-Line Package
.... ----------------........--,
....--------=~---+--+-+--~---
A,
A, ,
"
..
..
..
..
..
..
:p---+_..:"=-j"
....
....
A, l'
....
TYnCAl,
'~llIn
'u
·,.. ----....."""".......4~"44.....!i~f'--..._j
lAo
'AllIlY
'"
..c.
"
".
CIIIOTUSEDI
.
.
~.--
II.C.
..
..
..
I,
".,
..
..
...,
..
'.. .
A,
....
'00
CONTROL
ID
11
13
I.C.
TUPVIEW
DTLlrTLLD&11:
Order Number MM4220AP/J or MM5220AP/J
See Package 11
Order Number MM5220AP/N
See Package 18
-a."EIIAILE
fMoDECOITROL-----.....
tMlld. Control = Logic "II," As .. Logic "1:'
"Chip Enlble .. Logic "I" to obtain outputs.
Lo,t Ltv8ls:
DTLlTn (~xcept at MOS/RDM interhcel. logic "1," +5.DV. NOM. logic "0," gfound, NOM.
MOS/ROM mputs and OUlp"ts. Logic "I," mare negative. Logic "0," more positive.
6·34
code conversion table
CODE
FUNCTION
INPUT
ROM
ADDRESS
BCOIC
SYMBOL
0
Space
INPUT
OutPUT
ASCII
SYMBOL
C
0
D
E
OUTPUT
BCDIC
ASCII
B
A
8
4
2
1
E
P
b7
b6
b5
b4
b3
b2
~1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
1
1
0
0
2
2
2
0
3
3
3
0
0
0
0
0
1
0
1
0
0
1
1
0
0
1
1
4
4
4
0
0
0
0
0
1
0
0
1
'0
1
1
0
1
0
0
a
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
0
1
1
1
1
0
1
1
0
0
1
0
1
1
1
0
0
0
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
0
1
0
Space
5
5
5
6
6
6
0
0
0
0
7
7
7
0
0
a
8
8
9
8
0
0
0
1
9
0
0
0
9
10
or-
11
:!;;
12
@or'
~
@
13
14
>
15
J
16
Blank
17
,>
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
0
0
0
0
1
0
1
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
!
0
0
1
0
0
0
0
1
1
0
1
1
0
1
I
0
0
1
a
0
0
1
1
a
1
0
1
1
1
1
0
0
1
0
0
I
0
0
1
0
1
U
0
1
1
0
0
0
1
18
5
5
19
T
T
0
.0
1
1
1
1
1
0
U
U
0
,0
1
0
1
0
0
0
1
0
1
0
0
1
20
1
0
1
21
v
v
0
0
1
0
1
0
1
0
1
1
0
1
1
0
22
W
W
0
0
1
0
1
1
0
1
1
0
0
1
0
1
1
1
23
x
x
0
0
1
0
1
1
1
1
1
1
0
24
0
1
1
0
0
0
1
1
0
1
Z
Z
0
1
1
0
1
1
0
1
1
0
1
0
26
j
LF
0
1
1
1
0
0
0
0
a
1
0
1
0
1
1
1
1
1
0
1
0
1
1
0
0
or (
%
0
1
1
1
0
0
1
a
1
0
0
1
0
v
HT
0
0
0
0
0
0
0
0
0
0
1
25
0
0
0
0
0
y
0
0
1
y
1
1
1
0
1
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
"
0
0
1
1
1
1
1
0
0
1
1
-
0
1
0
0
0
0
1
J
1
0
0
1
1
1
0
K
K
1
0
0
0
0
0
0
J
0
0
0
0
0
0
-'"
0
0
1
0
27
28
29
30
31
32
~o
,
,
0
1
0
0
1
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
1
a
35
L
L.
0
0
0
1
0
0
0
1
1
1
1
1
1
0
36
M
0
1
0
0
1
a
0
1
a
1
1
0
1
37
N
N
0
1
0
0
1
a
a
0
0
0
M
1
a
1
0
0
1
1
1
0
38
0
P
0
0
1
0
1
0
1
1
0
0
1
1
1
1
p
0
1
a
a
a
1
39
1
1
1
0
1
0
1
0
0
a
0
40
Q
0
0
1
0
1
0
a
0
1
1
U
1
0
41
R
R
0
1
a
1
0
0
1
1
1
0
1
a
0
1
0
42
!
0
1
0
1
0
1
0
0
0
1
0
0
0
0
1
a
a
a
1
0
1
a
1
1
0
0
1
0
a
1
0
0
1
0
1
1
0
0
1
0
1
0
1
a
1
0
1
a
1
1
0
1
1
a
1
0
1
0
a
1
0
1
0
1
1
1
0
1
0
1
1
1
0
1
1
0
1
0
1
1
1
1
1
1
a
1
1
1
0
1
0
1
1
0
0
0
0
1
0
1
0
0
1
1
0
a
a
1
0
a
1
0
a
a
0
0
1
0
1
a
33
34
44
.
45
I
43
$
46
,
.
$
I
47
b
,
48
& or +
&
49
A
A
0
1
1
0
0
a
1
50
B
B
1
1
a
a
1
a
C
1
1
0
0
1
1
1
1
a
a
a
0
0
0
1
52
C
D
a
a
D
0
1
1
a
1
0
0
a
1
0
0
0
1
0
53
E
E
0
1
1
0
1
1
1
0
0
0
1
F
a
1
1
a
1
a
1
1
0
0
0
0
0
1
F
0
1
1
54
1
1
0
1
1
51
1
55
G
G
0
1
1
0
1
I'
1
a
1
0
a
1
56
H
H
1
1
1
0
a
a
0
1
1
0
a
0
,
0
0
0
57
0
0
0
1
1
0
1
0
0
0
1
1
1
1
1
0
0
58
I
1
1
1
a
0
1
1
1
a
a
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
0
1
1
~
0
1
1
1
1
a
a
1
1
a
1
1
1
I
,
59
60
tl or)
61
I
(
0
1
1
1
1
0
1
0
0
1
0
1
0
0
0
62
<
<
0
1
1
1
1
1
0
0
0
1
1
1
1
0
a
1
1
1
1
0
a
0
1
I
0
1
A2
A,
B8
B7
B6
B5
B4
B3
B2
B,
63
*
CR
0
1
1
A7
A6
A5
1
A4 A3
6-35
~Nattonal
a
MOS ROMs
Semiconductor
MM4220BM/MM5220BM sine look-up table
general. description
The MM4220BM/MM5220BM is al024-monolithic MOS read only memory th8't has been
programmed to solve for the sine value x of a
known angle 0; i.e., to obtain the SOlution of the
equation x z sin O.
"I" it carried into the LSB of·the eight bit code,
where Ae was a binary "0" it was simply dropped.
Values of 8 are defined in the 10Qk up table fQr
0° < 0 < 90° (quadrant I) Which has corresponding solutions of 0 ::;; x < 1. For values Qf
'90° < 8 <180° (quadrant 11), enter the complement (180° - 8) to obtain the correct Solution,
Solutions for quadrants 111 and IV differ in sign
with I and 11. This is·summariled in Table 1.
Find the sine of 45?
The input address is (45/90) 128 z 64 or
1000000, as expressed in binary. The converter
generates the output .10110101 whose decimal
equivalent is 0.707131. Thus, sin 45° z 0.707.
Find the sine of 21 o?
EXAMPLE
This value is in quadrant 111; therefore 8 1 = 210° 180° = 30°. The input address is then (30/90)
128'i!! 43 to the nearest ~hole integer. The binary
input to tile ROM is then 0101011. The output
value is .10000001 or 0.503906. Thus, sin 210° =
:"0.504, with the sign genereted by the external
logic. The solution is within 1%; note that address
43 is actually equal to 30.23°.
This input is divided into 128 pilrts for 0 in each
quadrant. Thus, the appropriate input address is
(0'/90°)(128) to the nearest whole integer. The
actual input code to the ROM is the input address
expressed ·in binary., with A, being the' ieast
significant bit..
The output is the value of X expressed in binary.
The output lines B1 , B2 , .•..• Ba are binary place
values 1/2, 1/4, .. _ ... 1/256. The sign for nega·
tive values of X is externally generated.
device characteristics
For full electrical, environmental and mechanical
details refer to the MM4220/MM5220 1024-bit read
only memory data sheet.
The 8 bit output code has been rounded off from
a larger word code, i.e., where Ae was a binary
connection diagram
Dual-In-line Package
1
24I- Voo
.,_ z
al- •.•
A,_ ,
ul- •.c.
A*_
. -.
..- .
,,-,
1,- 4
21t- A•
"I-A,
"I-"
11-"7
a,-I
17 -VOG
a,-I
,· ..... : : :RG1
.,-10
11 __ : :... 1:
,,_11
1 4 - ..
v.. -
13~ •.1:.
12
TDPYIEW
Order Number MM4220BM/J or MM5220BM/.
See Package 11
Order Number MM52208M/N
See Package 18
6-36
pattern selection form
ADDRESS
REfERENCE
0
1
2
3
4
5
6
7
8
9
10
fUNCTION
CODE
INPUT
OllT1'UT
RADIANS
B8
B7
B8
as
.00
.70
.000
.012
0
0
Q
0
1.41
,025
1
2.11
.037
,049
.061
.074
0
1
1
0
0
1
DEGREES
2.81
3.52
4.22
4.92
5,63
6.33
7.03
7,73
11
12
13
14
15
16
11.25
11
11.95
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
4;
42
43
44
12.66
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
8.44
9.14
9.84
10.55
.086
.098
.110
.123
.135
.147
.16'0
.172
.184
.196.
14.77
.209
.221
.233
.245
.258
15.47
,270
13.36
14.06
16.17
.282
16.88
17.58
18.28
.295
,307
18.98
.331
.344
.356
.368
.380
19.69
20.39
21.09
21.80
22.50
23.20
23.91
24.61
25.31
26.02
26.72
27.42
28.13
28.83
.319
.393
.405
.417
.430
.442
.454
.466
.479
.491
.503
29.53
,515
30.23
30.94
.528
.540
31.64
.~2
32.34
.665
.577
33.05
33.76
34.45
35.16
35,86
36.56
37.27
37.97
38.67
39.37
40.08
40.78
41.48
42.19
42.89
43.59
44.30
.689
.601
.614
.626
.638
.660
.663
.675
.687
.699
.712
.724
.736
.749
.761
.773
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
0
1
1
0
0
,
,
1
0
0
0
1
6·37
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1,
84
B3
82
B,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
0
1
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
1
1
1
0
1
1
1
1
,
0
0
1
0
0
0
0
1
1
1
0
0
0
1
1
1
0
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
0
0
0
,
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
,
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
Q
1
0
1
1
1
1
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
'0
0
0
0
0
1
1
1.
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
0
0
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
0
·0
1
1
1
1
1
1
0
~
0
1
,
1
I
Il
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
,
1
1
1
1
,
~
a:I
o
C'II
pattern selection form(con't).
('II
at)
~
~
......
:E
a:t
o
C'II
N
•
~
:IE
ADDRESS
REFERENCE
64
66
66
61
68
69
10
11
12
13
14
15
16
71
18
19
80
81
82
83
84
85
86
81
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
,OS
109
110
III
112
113
'114
115
116
117
118
119
120
12,
122
123
124
125
126
127
FUNCTION
COOE
INPUT
OUTPUT
DEGREES
RADIANS
Sa
87
86
B5
B4
B3
B2
B1
46.00
45.70
46.41
4.7.11
47.81
48.52
49.22
49.92
60,62
.785
.198
.810
.822
.834
.847
.859
1
1
1
1
1
0
0
0
0
0'
0
1
1
1
1
1
1
0
0
0
1
1
0
0
0
1
0
0
1
0
0
1
0
1
1
0
1
0
1
0
I
0
0
1
0
1
0
0
1
1
0
0
1
1
0
0
I
1
1
1
1
1
1
1
0
1
0
1
0
0
1
0,
1
0
1
1
0
0
1
0
0
1
1
0
0
0
1
1
0
0
1
'I
0
0
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
"
5':33
52.03
52.73
53 . 44
54.14
54.84
55.55
56.25
56.95
51.66
58.36
59.06
59.'11
60.41
61.17
61.87
62.58
63.28
63.98
64.69
65.39
66.09
66.80
61.50
68.2,0
68.91
69.61
70.31
11.02
71.72
72.42
73.12
73.83
74.53
75.23
75.94
76.64
77.34
78.05
78.75
79.45
80,16
80.86
81.56
82.27
82.97
83.67
84.38
85.OS
85.78
86.48
87.19
87.89
88.59
89.30
.871·
:884
.896
.9OS
.920
.933
.946
.951
.969
.982
.994
1.006
1.019
1.031
':043
1.055
1.068
I.OS0
1.092
1.104
1.117
1.129
1.141
1.154
1.166
1.178
1.190
1.203
1.215
1.227.
1.239
1.252
1.264
1.276
1.289
1.301
1.313
1.325
1.338
1.350
1.362
1.374
1.387
1399
1.411
1.i424
1.436
1.448
1.460
1.473
1.485
1.491
1.509
1.522
1.534
1.546
1,559
6-38
t
1
0
1
0
1
0
1
0
1
1
0
1
0
r
1
0
1
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
1
I
1
1
•
1
1
1
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
t
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
I
1
1
1
1
1
1
1
I
1
1
1
1
1
1
1
t
1
1
1
0
0
0
0
0
0
0
0
Q
Q
0
0
1
1
1
·1
I
1
1
1
·1
1
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
1
1
1
1
1
1
1
1
1
1
1
'1
1
I,
1
1
1
I
1
1
,
1
1
1
1
"
1
1
1
1
1
I
1
1
1
1
1
1
1
I
t
1
1
1
1
1
1
1
1
,
1
1
1
1
1.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
1
1
I
1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
t
1
1
1
j
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
1
1
1
,
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
typical application
-12'0'--------...,...--_____....__..........
Yo;
A,
11
A,
B,
A,
B,
A.
S,
A,
. ""
6.~K.
v,"
TYPICAL,
8 LINES
GATESDM7_00
0,
b,
b,
S,
MM4l2DIIM/
MM521G8M
b.
S,
b,
9 B.
A7 18
l.OK,
b,
a,
TYPICAL,
b,
7 LINES
. . . .~-i
So
V"
-4~.....:9:..~.::--...J;.~~---
+121,1 - - - - -. . .
.
OTt/TTL lOGIC
tA.
~tHIP
ENABLE,
tMOOE CONTROL - - - - - - '
tMode Control'" logic "0," As " logic "1,"
"Chip Enable" logIC "1" to obtain outputs.
logic levels:
Oll/TTl {~xcept at MOS/ROM mterface!. logic "1," +5.DV, NOM. LOllie "0," ground, NOM.
MaS/ROM inputs and outputs. Logic "1," more negative. logic "0," mOle positive.
Table 1. SINE
Quadrant
I
II
III
IV
INPUT
Entry to ROM (0' )
Range
> 0 < 90
> 90° < 180
> 180 < 270
> 270 $ 360
0
1800
0
-
Direct Reading
+
Direct Reading
+
-
0
0
X - 1800
Direct Reading
0
0
360° - X
Direct Reading
III
+1
-1
6-39
Sign
X
Direct
0
OUTPUT
Binary Value
IV
~National
MOSROMs
~ Semiconductor
MM4220DF/MM5220DF
"quick brown fox" generator
general description
The MM4220DF/MM5220DF is designed for exer·
cising and rapid testing of ASCII and Baudot·
coded keyboards, typing mechanisms, and data
communiCations links by generating the interna·
tionally accepted "Quick Brown Fox" message.
along with an even parity bit for a binary count
input of 64 to 127.
device characteristics
The input is a 7·bit binary sequential count. The
output of a 6 stage up-counter can be used; a
seventh bit selects the desired code. The message
is generated in the 5·bit Baudot Communicati.ons
Set code with a binary count input of 0 to 63. The
message is generated in the 7-bit American Stan·
dard Code for Information interchange (ASCII)
The message generator is fully contained on a
monolithic MOS integrated circuit chip utilizing
low threshold voltage technology for increased
DTLlTTL compatibility. For complete electrical,
environmental, and mechanical details,refer to the
MM4220/MM5220 1024·bit read only memory
data sheet.
typical. applications
connection diagram
Dual-In-Line Package
"
"
"
1
.
.
a,
Ao
"
"
"
'"
MODE
I
j
...
!
a,
a.
..
..
tOllrilOl
t"1P
.
(IIAIL£
'
tMode Control = Logic "fI," As = lo:gic "1."
*Chip Enable = Logic "," to obtain outpuls.
Logic Levels:
OlL/TIL (except at MOStROM interface). Logic "1," +S.OV. NOM. logic "0," ground, NOM.
MOS/ROM inputs and outputs. logic "1," more negative. Logic "0," more pD'Sitive.
Outputs for circuit shown
BaudOI: Logic"O" = "punch"
ASCII: logic inversion
A typical application showing the ASCII~coded test
message as received at a computer terminal.
THE
tHE
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
QUICK
QUICM
QUICI(
QUICK
QUICM
QUICM
QUICI(
QUICK
QUICK
QUICK
QUICK
QUICK
BRIilWN
3R0WN
BR0WN
BR0WN
BR0WN
B~ewN
BReWN
BReWN
BR0WN
BReWN
BRilWN
BR0WN
Fex
FeX
FeX
Fex
Fex
F0x
Fex
Fex
Fex
F"ex
rex
Fex
JUMPS
JUMPS
JUMPS
.JUMPS
JUMPS
.JU":PS
.JUMPS
JUMPS
JUMPS
JUMPS
JUMPS
JUMPS
0VER
"0VER
eVER
0VER
eYER
0VER
eYER
eYER
IilYER
eVER
THE
THE
THE
THE
THE
THE
THE
THE
THE
tHE
~YE~ THE
eYER THE
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
D0G
"00G
peG
D0G
DIilG
DeG
DeG
DeG
OeG
DeG
DeG
DeG
123./1)67890
1234567890
"123-'1561890
123./1561890
123.561890
1234567890
1234567890
1234567890
1234567890
12304567890
1234567890
1234567690
6·40
DE
DE
UE
OE
DE
DE
DE
DE
DE
OE
DE
DE
Order Number MM4220DF/J
Or MM5220DF/J
See Package 11
Order Number MM5220DF/N
See Package 18
s:
s:
code conversion table
~
N
N
o
Baudot
ADDRESS
OUTPUT
CHARACTER
-
-
-
5
4
3
2
1
ADDRESS
0
1
CR
CR
1
1
1
1
1
1
1
1
6.
65
2
3
LF
1
1
1
a
1
Ltr.
1
1
1
1
1
a
a
1
1
1
1
1
0
0
0
1
1
1
1
5
T
H
0
1
6
7
E
0
1
1
1
SP
B
Q
9
10
11
12
13
a
a
a
0
0
1
0
0
C
0
0
0
1
1
1
0
1
1
0
1
0
1
1
1
a
a
0
0
1
1
1
•
u
I
K
,.
SP
15
R
16
17
18
19
20
21
22
23
B
0
W
1
1
1
0
0
1
a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
.1
1
1
F
1
1
1
1
0
X
1
1
SP
N
SP
2'
25
26
J
1
1
u
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a
1
1
1
1
1
a
.0
0
1
1
1
1
0
1
0
1
1
44
45
46
47
48
49
50
51
52
53
54
55
56
57
D
0
G
SP
Fig.
1
2
3
4
5
6
7
8
9
0
1
0
0
1
1
1
0
1
0
0
0
1
1
1
1
0
1
1
58
59
SP
60
Ltr.
61
D
E
62
63
se
1
77
7B
SP
B
R
a
0
0
=
w
1
1
0
0
1
1
1
0
0
a
1
a
a
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
B7
86
0
0
a
0
0
a
0
1.
1
0
1
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
1
a
1
lOB
109
110
1
1
1
1
106
107
1
a
a
a
1
1
1
0
1
a
a
1
1
1
0
1
1
1
L
A
1
1
0
a
0
0
103
10.
lOS
1
1
1
1
1
0
a
1
0
0
T
a
1
0
1
1
98
9.
100
SP
1
1
1
0
1
1
0
1
1
1
1
0
1
a
a
1
0
1
0
0
0
1
1
1
1
0
1
0
0
a
a
a
a
1
1
1
1
0
0
1
0
0
0
0
0
0
1
a
a
111
112
113
""
115
116
117
118
119
0
0
1
1
1
1
1
0
1
0
1
1
a
1
1
1
1
0
1
a
a
1
1
1
0
1
1
a
a
1
a
D
0
1
a
a
0
G
1
a
1
1
1
1
1
1
1
SP
0
a
a
0
0
0
1
a
2
3
0
1
1
1
4
5
6
a
1
1
1
0
0
1
1
a
a
0
0
1
1
1
1
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
1
1
0
1
1
1
a
1
1
0
0
0
a
a
0
0
0
a
a
0
85
B4
B3
B2
81
a
DEL
a
0
127
DEL
0
0
118
87
8S
a
0
0
ASCII: Logic inversion
6-41
1
0
1
0
Note: When chip enable input is at a logical O. all outputs are at a logical 1.
0
0
1
SP
Space
1
1
0
1
125
126
81
1
1
0
0
1
a
0
0
0
1
1
1
0
1
0
1
82
1
1
0
0
a
a
1
D
E
B3
1
1
1
0
1
1
1
123
12.
B5 B4
1
1
1
1
1
1
0
1
1
1
1
0
1
0
1
1
a
1
1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
1
1
1
1
1
0
a
0
a
1
0
0
9
SP
1
a
a
1
1
1
1
1
1
122
1
1
1
1
120
121
0
0
1
1
1
1
0
1
1
7
8
1
1
1
a
0
1
a
se
Z
y
1
1
V
E
a
1
1
E
H
a
0
1
96
97
SP
1
1
1
1
95
102
1
1
0
0
1
9.
101
a
0
1
0
0
1
1
1
1
1
a
0
0
1
1
1
1
0
1
a
R
0
0
0
a
0
1
1
1
1
0
0
1
Q
1
0
0
0
a
0
0
1
se
1
1
1
0
0
1
0
1
a
a
1
1
1
1
1
1
1
1
a
0
1
1
0
0
1
0
1
1
0
1
1
1
1
1
0
1
1
0
1
1
1
1
0
1
a
0
1
1
1
0
1
0
1
1
0
0
1
0
1
0
1
a
0
1
1
1
1
0
0
1
a
1
1
1
1
a
0
1
a
1
1
1
1
0
a
a
1
0
1
1
S
1
1
0
1
0
1
1
0
1
1
1
0
1
0
1
P
1
0
1
0
0
0
1
1
1
1
1
1
1
1
M
1
a
1
1
1
1
90
91
0
0
1
1
a
'2
93
1
Baudot: Logic "0" ::: "punch"
SP
K
1
1
1
88
a
a
1
1
1
1
1
1
0
0
1
0
1
a
1
1
a
1
1
1
1
1
1
I
C
0
0
1
1
1
1
1
U
1
0
1
1
0
1
1
1
1
73
7.
75
76
1
0
0
1
1
1
a
0
1
1
1
1
1
1
0
0
Q
E
1
1
1
1
1
1
1
1
1
1
1
SP
72
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a
1
1
1
1
1
1
1
1
1
J
0
1
1
0
1
u
1
1
1
1
1
8.
0
1
1
1
1
69
70
71
88
0
0
1
1
1
a
a
a
0
0
1
1
1
1
0
1
a
0
1
1
1
a
a
a
0
1
1
1
a
1
1
a
1
0
1
0
1
1
1
1
1
1
0
a
1
0
a
a
1
1
1
1
0
1
0
a
1
1
1
1
1
0
1
1
1
1
0
1
E
1
a
1
se
0
1
X
1
37
38
1
SP
1
1
36
1
a
a
86
87
1
1
1
1
a
a
a
1
a
a
0
1
1
1
1
1
a
a
1
1
1
a
0
0
1
a
F
0
a
1
1
1
b1
8'
85
1
R
b2
0
1
0
T
H
b3
1
a
se
b4
0
1
0
1
1
1
b5
a
1
E
LF
T
H
bS
N
0
1
CR
CR
b1
SP
1
1
1
NULL
"s:
ASCII
Y
a
a
1
1
0
V
Z
y
a
OUTPUT
CHARACTER
."
P
A
R
I
T
7'
80
81
82
83
1
1
31
SP
0
1
1
1
0
32
42
43
0
0
a
SP
L
A
a
0
a
1
1
1
39
40
41
1
0
0
1
0
1
1
S
34
35
1
1
1
1
1
1
66
67
6B
1
1
1
P
33
0
1
1
1
1
1
M
27
28
29
30
0
1
1
1
1
o
OUTPUTCQDE
OUTPUT CODE
1
1
s:
U'I
N
N
o
o
."
~National
MOS ROMs
~ Semiconductor
MM4220EK/MM5220EK
BCDIC-to-EBCDIC and ASCIl-to-EBCDICcode converter
general description
ASCII code in addresses 64 through 127 has a "1"
in the most significant (A 7 ) bit which is used with
the selection 10gic.The resulting 6-bit ASCII input
is for display-only upper case and numerical
codes. since it will not accept the control commands or the lower case characters.
TheMM4220EK/MM5220EK isa 1024-bitread only
memory that has been programmed to convert
both Binary Coded Decimal Interchange Code
(BCD IC) and the American Standard Code for
Information Interchange' (ASCII) to Extended Binary Coded Decimal Interchange Code: (EBCDIC).
The BCDIC-to-EBCDIC converter is located in the
first 64 B-bit bytes of the ROM. The unused parity
check bit (the most significant input BCDIC bit) is
always a "0".
device characteristics
For full electrical. environmentai and mechanical
details.' refer to the MM4220/MM5220 1024-bit
read only memory data sheet.
The ASCII-to-EBCDIC converter is located in the
second 64 B-bit bytes of the ROM. Thus. the input
typical application
connection diagram
Dual-In-Line -Package
-12"-----_----------...
-4~_,
"
",.';
,
b,
2
b,
4
~
22
B,
2T
..
"
4
.
J
~:
B,
'.
B.
"
B,
v"
"
"
B,
B,
UK,
B.
TYPICAL.
'.
" "
0
8!:!
~8
A7'8
"CODE'·
~
I
..
b.!B
5
'.
"
.
" .
"
'"
"
A,
b.
v,,
"
GAHS UMII81B on DM83ll
1 LINES
V"
"
MOUE
CONTROL
CHIP
ENABLE
'.
"
onml LOGIC
Order Number MM4220EK/J
or MM5220EK/J
tMODE CONTROL - - - _ , _ - - '
tMode Control'" logic "0," As -= lO!lic "1."
"Chip Enable'" logic ''1'' to I)btain outputs,
logic levels'
OTlITTl (except at MOS/ROM interfacd. Logic "1:· +5.0V. NOM. logic "0," ground, NOM
MOS/ROM inputs and outputs. logic "1," more negative, logic "0," more flositive.
6'42
See Package 11
Order Number MM5220EK/N
See Package 18
code conversion tables
FUNCTION
INPUT
COOE
INPUT
OUTPUT
OUTPUT
C
ROM
ADDRESS
aCDlc '
SYMBOL
EBCDIC
SYMBOL
0
1
10
Space
1
2
3
4
5
6
7
8
9
0
11
#or-
#
12
@or'
@
2
3
4
5
6
7
8
9
BCDIC
A8
4
2
1
0
1
2
3 4
5
6
7
Space
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
2
3
0
0
0
0
0
0
0 0
0'0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
4
0
0
0
0
1
0
1
1
1
0
0
0
1
0
1
1
0
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
6
7
0
0
0
1
1
5
1
1
1
1
0
1
1
1
1
1
1
1
0
8
9
0
1
1
1
1
0
1
1
1
1
1
1
0
1
0
0
1
0
0
1
1
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
0
1
1
1
0
0
0
0
17
18
I
S
I
S
19
T
T
20
U
U
V
0
1
0
0
0
W
X
0
0
0
0
X
1
0
0
>
V
1
1
0
TM
W
1
1
1
0
0
0
0
1
Space
23
1
0
0
1
1
Space
22
1
1
1
0
0
J(TM)
21
1
0
1
0
0
1
1
0
1
1
0
0
15
16
1.
EBCDIC
E B
13
>
0
0
1
1
0
1
1
0
1
0
1
1
1
0
0
0
1
0
0
1
1
1
0
1
1
0
0
011
1
0
1
1
1
1
1
0
0
1
0
1
0
1
1
0
0
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0
0
1
0
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
0
0
1
1
1
1
1
0
1
1
0
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
26
27
0
0
0
1
0
1
0
%or (
0
0
1
0
1
1
28
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
0
1
1)
0
0
1
0
0
1
0
1
0
0
0
0
M
0
0
0
0
0
L
0
0
1
0
L
0
0
1
0
M
0
0
1
0
35
36
0
1
1
J
1
0
1
1
K
1
0
1
1
K
0
0
0
1
1
J
0
0
0
0
1
1
32
33
0
0
0
0
3.
0
1
1
0
0
+
0
1
1
1
0
•
0
1
1
0
\
0
0
1
0
1
1
y
v
0
0
0
Z
.
0
1
0
0
y
31
1
1
0
0
Z
29
30
1
1
0
0
,(AM)
%
0
1
0
0
25
RM
1
0
0
1
0
0
0
0
0
0
1
2.
0
1
1
1
1
1
1
1
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
1
1
1
0
0
0
1
0
1
1
37
N
N
0
1
0
1
0
0
1
0
0
0
1
0
0
1
1
0
1
1
0
0
1
38
1
0
1
P
P
0
1
0
1
1
1
o
1
1
0
1
0
0
0
1
1
0
1
0
1
1
Q
1
0
1
Q
0
1
1
,1
0
39
40
0
0
0
0
0
1
0
1
1
0
1
1
1
1
1
A
,
A
,
0
1
0
0
1
1
1
a
1
1
0
0
1
0
1
0
1
1
0
42
0
1
0
0
1
0
0
1
0
$
$
0
1
0
1
0
1
1
0
1
0
1
1
1
43
0
I
)
1
1
0
0
0
0
1
41
44
45
46
;
0
0
1
47
(',
"
0
1
48
0
0
0
1
a
1
1
1
1
1
0
1
1
1
1
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
0
0
1
1
1
1
0
0
0
0
& or +
&
0
1
0
a
0
A
1
1
0
0
0
B
A
B
0
50
0
1
0
0
1
1
0
51
C
0
1
0
0
1
1
52
0
0
1
1
0
1
a
1
1
1
54
F
F
0
1
1
0
0
1
1
0
E
1
1
1
53
D
E
C
0
1
1
1
1
G
G
0
1
1
1
H
H
0
1
0
1
1
56
1
1
1
1
1
55
0
1
0
0
0
1
1
57
,
I
0
1
1
1
0
0
1
?
0
0
1
1
1
0
1
1
1
1
1
0
1
1
0
0
1
0
1
1
1
1
1
1
I
59
60
t:1 or)
61
62
63
I
"I
0
1
1
<
<
0
1
1
1
0
1
1
1
"
6-43
~-+
1
49
58
~
~
1 1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
1
a
0
0
1
0
0
0
0
1
1
1
0
0
1
0
1
0
1
1
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
1
a
0
1
0
1
1
0
1
0
1
1
1
0
0
1
0
1
a
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
code conversion tables(con't)
FUNCTION
INPUT
CODE
OUTPUT
INPUT
ASCII
SYMBOL
EBCDIC
SYMBOL
C
0
D
E
&4
65
66
@
@
1
0
A
A
B
67
68
69
70
71
72
73
74
75
C
C
0
0
0
D
E
F
G
E
F
1
1
1
1
1
G
H
H
I
I
J
ROM
ADDRESS
B
J
K
D
K
L
L
M
M
1
1
1
1
1
1
1
76
77
78
79
0
0
1
1
1
80
P
P
1
81
82
83
0
a
1
1
1
N
N
A
A
S
T
S
U
U
86
87
88
89
v
w
v
w
X
v
X
y
90
91
92
z
Z
I
I
\
\
93
94
95
J
I
8.
8S
96
97
""or {\
T
--.
-
Space
!
Space
.
98
..
99
100
#
#
$
$
%
&
%
&
10'
102
103
104
105
106
107
108
109
110
111
112
113
114
,
!
I
I
I
I
+
+
I
I
0
1
2
0
1
2
115
116
3
3
4
4
117
118
119
6
5
6
7
120
121
122
123
124
125
126
127
6
7
8
9
8
9
;
;
<
>
<
>
?
,
?
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
,
1
1
1
1
1
1
1
1
1
1
bfi
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
,
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OUTPUT
ASCII
b5 b4 ba b2 bl 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
O.
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
,0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
1
0
0
0
1
0
1
0
1
0
1
1
,
1
0
, ,
0
0
6-44
0
0
0 1
0
0
1
1 0
1 0
1 0
1 0
1 1
1 1
1 'I
1
1
1
1
1
1
1
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
0
,
1
1
1
1
1
1
0
1
1
0
1
1
2
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
1
,
0
1
1
1
1
1
0
,
1
1
,
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
EBCDIC
a 4 5
1
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
,
0
1
1
0
1
1
0
0
0
0
0
1
1
1
1
1
1
0
6
7
1
0
0
0
0
1
1
1
0
1
0
0
1
1
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
1
1
0
0
1
1
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
,
0
,
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
.
~ Semiconductor
~National
MOS ROMs
s:
~
.po
N
N
o
r-
::D
.....
MM4220LR/MM5220LR BCDIC to ASCII-71
ASCII-7 to BCDIC code converter
genera I description
The MM4220LR/MM5220LR .is a 128 x 8 read
only memory which has been programmed to con·
vert the 64 characters of the Binary Coded Decimal
Interchange Code (BCDICI to the American Stan. dard code for Information Interchange in seven
bits (ASCII-JI.
~
s:
U'I
address 63, converts the 64 character ASCII
graphic subset to BCDIC. The tables show the
character assignments and their binary equivalents.
For electrical, environmental and mechanical datails, refer to the MM4220/MM5220 data sheet.
typical applications and connection diagram
BCOIC to ASCII
Oual-ln'Line Package
"
'.
"
"
"
"
&aIT
KOIC
IN.Ut'
"
"'3
.. I
..
.l.llK,
TYPICAL,
"
5 LIliES.
".
4CHIP'ENABu:.
'lMOD~CONTROL----""
tMode Control = Logic "0," As '" Logie "1."
·Chip Enable'" Lallie "1" tDoiltain outputs.
Logic Levets:
DTlfTTL (except at MOS/ROM interface). logic "1," +5.0V, NOM. Logic "0:' ground, NOM,
MilS/ROM iltplIts and outputs. Logic "1," more negative, Logic "0," more positive.
"IT
Ascn
DunUT
.
"
,
."
"
"
-,
..
"
B,
CONTROL
CHIP
EIIAilE
0,
"
'" "
Order Number MM4220LR/J
or MM5220L RIJ
See Package 11
Ordor Number MM5220LR/N
See Package 18
ASCII to BCOIC
Ih.MOT
"
",
GIlT
ASI:I.
lVUl
II;.
"
US~D)
lie
"
"
o
r::D
The first half of the ROM, from address 0 to
6AlESDMB8100RDMU12
N
N
....
..
&BIT
I&DICOll11'IIT
tMDDECDNtADL--_ _.J
tMode Control =- logic "0," Ae =- logtc "1,"
*Chlp Enable" Logic "1"to obtain DutpUU.
lI;Jgic Lewis:
OTLmL (except at MOS/AOM interface). Logic "1," +5.DV, NOM. logic "9," ground, NOM.
MOS/ROM inputs and Dutputs.. logic "1," mor~ negative. Logic "0," more positive.
6-45
a::
...J
o
N
N
code conversion tables
Il)
~
~
.......
ASCII to BCOIC
a::
o
FUNCTION
...J
N
N
~
~
~
ROM
ADDRESS
,
CODE
INPUT
OUTPUT
ASCII
SYMBOL
BCOIC
SYMBOL
0
SP
,
SP
2
3
4
5
6
7
8
9
10
11
12
"
+++
'3
"
15
16
17
,.,8
20
2'
22
23
2'
25
26
27
28
2.
30
31
32
33
34
35
3.
37
38
39
40
41
#
,
#
$
$
%
%
&
&
V
I
Blank
)
f,
VT
CR
1
I
I
I
,
0
1
2
3
4
5
0
2
3
4
5
•
7
8
9
•
7
8
9
;
>
<
v'
>
@
@
<
,
,
A
A
8
C
B
C
D
D
E
E
F
F
G
G
H
H
I
I
'2
43
44
45
46
47
J
J
K
K
L
L
M
M
N
N
0
0
48
P
P
49
50
51
52
53
54
55
56
57
58
59
BO
Q
Q
R
R
S
S
B'
62
63
T
T
U
U
V
V
W
W
X
X
Y
Y
I
Z
I
\
\
)
)
Z
~
"
C
0
0
E
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUTPUT
INPUT
b7
bS
0
0
0
0
0
0
ASCII
b4
b3
0
0
0
0
0
Mel
b2
b,
DATA
0
0
1
1
0
0
0
,
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
,
, ,
, ,
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
1
1
1
1
1
1
1
1
1
1
1
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A7
A6
,
,
,
,
,
,
,
1
,
1
1
,
,
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
,
1
1
,
1
1
1
,
,
,
1
,
,
0
0
,
,
0
0
1
,
0
,
0
0
,
, ,
0
0
0
,
,
0
0
0
1
1
0
0
0
1
0
1
0
1
1
0
0
0
0
,
,
0
0
0
0
1
0
,
,
,
1
,
,
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
,
0
0
1
1
1
0
0
0
,
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
,
,
,
1
1
AS
A.
1
1
1
,
0
0
0
0
1
1
1
,
0
0
,
0
0
0
0
1
1
,
,
1
0
0
,
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
.1
1
0
0
1
1
0
0
1
1
A3
A2
1
1
0
0
0
0
1
1
,
6-46
,
,
,
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
,
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
E
P
B
, ,
,
,
,
,
,
, ,
0
0
0
1
0
0
0
,
,
0
,
0
,
0
,
0
0
1
0
0
0
0
0
, ,
, ,
,
,
,
0
0
0
0
,
,
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
,
1
0
,
0
1
0
1
0
0
1
,
0
1
0
0
1
1
0
0
0
1
0
1
1
0
0
1
0
1
0
,
1
0
0
1
0
1
1
1
1
1
1
1
1
,
1
1
1
1
1
1
1
1
1
B8
B7
BS
,
,
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
,
1
0
0
0
0
0
0
0
0
0
,
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
0
0
0
0
,
, ,
, ,
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
1
0
0
0
1
,
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
o.
1
1
,
,
1
0
0
1
,
0
0
1
,
0
0
0
,
1
0
0
1
1
0
0
1
1
0
0
1
,
,
0
0
0
0
B,
B3
B2
,
0
1
1
1
l
l
1
1
0
BS
l
0
,
,
, ,
,
,
, .,
, ,
,
0
, ,
, ,
0
0
0
1
0
0
0
1
1
1
0
,
0
0
, ,
,
,
,
, , ,
0
,
,
2
, ,,, ,
,
, ,
0
0
1
A,
0
0
0
1
1
0
,
0
1
,
,
0
,
,
,
,
0
1
0
0
1
1
0
0
0
1
0
1
0
0
4
0
0
0
,
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
,
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BCDIC
A
8
,
,
,
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
l
0
0
B,
s:
s:.,.
code conversion tables(con't}
N
N
Q
,...
Bcorc to ASCII
::r:J
.......
FUNCTION
RDM
ADDRESS
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
7.
80
81
82
83
84
8'
86
87
..
OUTPUT
SCDIC,
SVMBOL
ASCII
SYMBOL
SP
1
2
3
4
5
6
7
8
9
0
#
01>
SP
1
2
3
4
5
>
>
.,[
=
6
7
8
9
0
#
01>
Blank
(
I
5
I
5
T
T
U
U
V
V
W
W
X
X
y
y
89
Z
Z
90
!
VT
9'
92
93
94
95
96
97
98
99
100
'01
102
103
104
101>
106
107
108
109
110
111
112
113
114
115
116
117
118
11.
120
121
122
123
'24
'25
126
127
C
0
0
E
1
1
1
1
1
1
1
1
1
1
1
1
1
1
,
,
1
A4
L
M
L
M
I'
N
,
,
$
$
,
1
1
1
1
1
1
1
1
1
1
,
1
1
1
1
1
1
1
)
)
;
;
A
)
&
&
A
B
C
0
E
F
A
B
1
1
,
,
C
,
,
1
1
1
1
1
1
1
1
1
1
0
E
F
G
H
G
I
J
I
?
I
"I
.
H
<
<
*
CA
,
1
1
,
,
,
1
1
1
1
1
1
1
1
1
,
1
1
1
1
1
1
0
0
0
0
0,
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
,
1
1
1
,
1
0
0
0
0
1
,
1
1
0
0
0
0
1
1
,, , ,
As
J
K
A
0
0
1
1
0
0
1
1
0
0
1
1
0
0
As
J
K
Q
,
0
0
0
0
0
0
0
0
1
1
1
1
1
1
A7
+++
.
1
1
1
1
1
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
,
,
Q
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0,
0
0
1
1
1
1
1
1
1
1
1
BCDIC
8
4
1
1
1
"
p
A
,
1
1
1
1
1
\
0
p
B
1
1
1
1
1
,
\
N
0
INPUT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
V
%
s:
s:U'I
CODE
INPUT
1
0
0
0
0
1
,.
,
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Aa
6·47
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
,
0
0
1
1
0
0
1
1
0
0
1
1
A2
,
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
A
R
I
T
V
0
,1
1
0
1
0
0
1
1
0
0
1
,
,
0
,
0
1
0
1
0
0
1
,
0
0
1
1
1
0
0
0
0
1
0
,
0
0
1
0
1
1
0
0
1
1
1
1
,
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
1
0
1
At
as
,
OUTPUT
ASCII
b7
bj;
bs
b.\
b:l
b:z
b,
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
,
1
1
1
1
1
1
1
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
,
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
B7 '
,
0
i
,,
,
1
0
0
0
0
0
0
0
0
0
,
,
,
0
1
0
0
0
0
0
0
0
0
0
0
1
,
,
,
,,
0
0
0
0
0
0
0
0
0
0
, , , ,
, ,
1
0
0
,
,,
,
1
1
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
ci
1
0
1
1
1
,
,
,
1
0
0
0
0
0
,
1
1
1
0
0
0
0
0
0
0
0
1
,
,
,
,
0
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
1
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
,
1
0
0
1
0
1
1
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
,
,
Ii
0
1
0
,
0
1
0
1
0
1
1
,0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
1
0'
1
0
1
0
,
,
,
, , , , ,
,
,
,
0
0
0
1
1
0
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
as
lis
II.!
113
B2
B,
0
0
0
1
1
1
1
0
,N
N
o
,...
::r:J
MOS ROMs
~National
~ Semiconductor
MM42211MM52211024-bit read only memory
general description
The MM4221/MM5221 is a 1024-bit static read
only memory. It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold voltage technology. The device is a nonvolatile memory organized as 128-8-bit words or
256-4-bit words. Programming of the memory
contents is accomplished by changing one mask
during the device fabrication.
•
Static operation
•
Common data busing
no clocks requ ired
•
Chip enable output control
output wire AND
capability
applications
features
•
•
Code conversion
Random logic synthesis
•
Bipolar compatibility
+5V, -12V operation
•
•
Table look-up
Character generators
•
High speed operation
<700 ns typ
•
Microprogramming.
block and connection diagrams
1 ___l-__
~·::{EHSEAMPl.IFIERS
Dual-I n-Lin. Pa""-
fUI) A,
.
IIilPUTA,
"
"
..
..
-,...
AODRESS
DECODER
"
lSBIIIPUTA,
,
LS80UTPtJT.,
4
OUTPUT..,
OUTPtlTB3
OUTPUTS.
OUTPtJTBs
..
OUTPUTIIa
OUT'UTB1
.
.
"
IMSB'OIftPU'ta.
..- -.....- - - ' L..f.....-----~:~Il£
>••
INPUTA l
>"
.."
'''''''''
"
"
"
II'UTA.,
..
IIiPIITAs
IIPUTA, MS.
>00
...
MDD'
tlNlTllOL
DlAILE
' ' UTA.,
"
Order Number MM4221 J
or MM5221J
MODECDIIITflOL----I-.-J
See Package 11
Order Number MM5221N
See Package 18
Note: For programming information see AN-100.
6-48
absolute maximum ratings
VGG Supply Voltage
Vee Supply Voltage
Input Voltage
(V ss - 20)V
Storage Temperature
Operating Temperature MM4221
MM5221
Lead Temperature (Soldering, 10 sec)
Vss -20V
Vss - 20V
< V 1N < (V SS +0.3)V
_65°C to +150°C
_55°C to +125°C
DoC to +70°C
300°C
electrical characteristics
T A within operating temperature range, Vss = +5V ±5%, V GG = Vee = -12V ±5%, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
Output Voltage Levels
MOS to TTL
Logical "1"
Logical "0"
6.8 kn ±5% to V GG Plus One
Standard Series 54/74 Gate
Output Current Capabil ity
Logical "0"
V OUT = 2.4V
Input Voltage Levels
Logical ;'1"
Logical "0"
Power Supply Current
lee
IGG (Note 1)
+0.4
f = 1.0 MHz, V1N = OV
f = 1.0 MHz, V1N = OV
Address Time (Note 2)
See Timing Diagram
TA = 25°C,
Vss = 5V
VGG = Vee = -12V
2.5
rnA
6.5
12.0
1
V
V
mA
IlA
IlA
5
15
25
pF
pF
700
950
ns
8
6.8 kn ±5% to VGG Plus One
Standard Series 54/74 Gate
Note 1: The VGG supply may be clocked to reduce device power without affecting access time.
Note 2: Address time is measured from the change of data on any input except mode control or Chip
Enable line to the output of a TTL gate. (See Timing Diagram). See curves for guaranteed limit
over temperature~
Note 3: The address time in the TTL load configuration follows the equation:
T ACCESS = The specified limit + (N - 11 (501 ns
Where N
V
Y
TA = 25°C
Vss = +5V
VGG = Vee = -12V
Input Capacitance
VGG Capacitance (Note 4)
UNITS
+2.4
Vss - 4.2
V 1N = Vss - 12V
Output AND Connections
(Note 3)
MAX
Vss - 2.0
I nput Leakage
TACCESS
TYP
= Number of AND connections.
Note 4: CapaCitance guaranteed bV design.
6-49
\
a
performance characteristics
Power Supply Current vs
Power Supply Current vs
Ambient Temperature
Power Supply Voltages
,
V "V
EEEEffiH~
DD
16
"
1
14
lz5~~
111
12
MAXIMUM
10
8
j
V.. -+5.0V
Voo =Voo =-IZV
aG
~=WC
6
4
MAXIMUM
1
10
j
TYPICAL
TYPICAL
z
0
o
11.0
16.0
18.0
-50 -26
1400
18.0
17.0
50
75 100
rr'-~,.."-'r-r.,.-"-'--r-,.,
H-++t-1H-++t- VDD = VaG
16.0
17.0
Vss - Vo• (V)
18.0
Vss - VaG (V)
timing diagram/address time
.,vI
.,v
+3V-rI
.v...J
L
At.~
L OUTPUT 1M
MM4221fMM5221 Ill"
ANYTTl/DTl EI"~10PF
r
10PF~~_
•
INPUT
VIS -2.0V
,~
I1
~
GAT.
EITHER
UK
ANYTTL!OH
GATE
~
f4---TACCESS - - - - ~
+5V
I
OR
/
Vss-2.1tV
.,v.V f-----I
'OUT
"--"'--"'--1
...I
r---\
.v
125
Power Supply Voltages
rr....-.,-,rr....-.,-,-,-...-.,-,r-r,
H'-+++-H'-+++ VDD '" VaG
16.0
Z5
Guaranteed Access Time vs
Typical Ace ... Time vs
Power Supply Voltages
1400
0
AMBIENT TEMPERATURE!"CI
Vss - Vo. (V)
1.5V
•
.,v
1.SV
.V
lim.
6·50
"*
-i. 15PF
'w,
typical application
128·8 Bit ROM Showing TTL Interface
..
,.
~
~
..
..
-(
: ANVl:~rTl
.
"
.... VOTLlTTLLllIiIt
I
I
I
I
I
I
I
I
I
I
"
I,
...
I
I,
I
I
"
.. .
1
"
'
"
I
1
tSeaoperatingnt8c1eno1es.
1
OPERATING MODES
128x8 ROM connection
Control - Logic "0"
As
- Logic "I"
256x4 ROM connection
Control - Logic" 1"
Ag
- Enables the odd (B 1
(B 2 ••• B8 ) outputs:
.••
B7 ) or even.
The outputs are "Enabled" when a logic "1" is
applied to the Chip Enable line.
The outputs are connected to ground through an
internal MOS resistor when "Disabled."
Logic levels are negative true MOS logic.
Mode control should be "hard wired" to either
Voo (logical "1 ") or Vss (logical "0").
The logic levels are in negative voltage logic notation.
6·51
}-
~National
MOS ROMs
~ Semiconductor
MM4221RR/MM5221RR ASCH-7 to EBCDIC code converter
general description
The MM4221RR/MM5221RR is a 1024-bit readonly memory that has been programmed.to convert between the 128 characters of ASCIi-7. the
American Standard Code for Information Interchange in seven bits. and E8CD IC. an extended
binary coded decimal interchange code. This conversion follows the EBCDIC character assignments
used in the IBM 1130 computer.
Certain arbitrary assignments have also been made
for maximum usefulness. and in thElse two areas
the part differs from the MM4230QYIMM5230QY,
which follows American National Standard ANSI
X3.26 recommendations for character assignments.
For electrical, environmental and mechanical details, refer to the MM4221/MM5221 data sheet.
typical application
ASCII-7 to EBCDIC
'"v
_11-1
EBCDIC
BINARY
In.11
MS8
.. o--.!.!
..
"
..
~
lSI
A,
b2~
A,
0-2
A,
b1
MM4221RRI
So
C(:>--->,
B,
d'>--o.
;:
•
~.
B,
S,
•
'!i,17,241
MS'
1
MM&221RR
lOW
TnUE
•
X
~z
...
..1-0
B,
A,
b3o--!
..
11
A,
.
.. o----!!
.. O--!! .
.
"IG" TRUE
·'f·.
;:
-v
UK
UK
UK
U.
UK
~Jv
Order NumberMM4221RR/J or MM5221RR/J
See Package 11
Order Number MM5221 RR/N
See Package 1B
6-52
UK
UK
7
LSI
code conversion tables
FUNCTION
INPUT
OUT1lUT
ROM
ASCII
ADORESS
SYMBOL
EBCDIC
SYMBOL
0
1
2
3
4
5
6
7
a
9
10
11
12
13
14
16
.. 16
17
IS
19
20
21
22
23
24
25
26
27
2B
29
30·
31
32
NUL.L
SOH
STX
ETX
EOT
ENQ
AC'K
BEL
BS
HT
LF
VT
FF
CR
SO
SI
DLE
DCl
DC2
DC3
DC4
NAK
SVN
ETa
CAN
EM
SUB
ESC
FS
NULL
SOH
S'(X
ETX
EOT
ENQ
ACK
BEL
BS
HT
LF
VT
FF
CR
SO
SI
DLE
DCl
DC2
DC3
RS
NAK
SVN
EOB
CAN
EM
SUB
BYP
FLS
GS
GS
RS
US
SP
RD!'
I
..
.
#
#
$
37
,.
,.
38
&
&
39
40
41
42
43
I
«
)
)
+
+
33
34
35
36
US
SP
COOE
INPUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
.
45
0
1
2
3
4
5
6'
1
2
3
4
7
7
B
9
a
9
68
,
59
;
;
60
61
62
63
<
-
>
<
=
>
?
?
48
52
53
54
55
56
57
j)
0
0
0
0
0
P
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
.1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
I
I
I
0
0
0
I
I
5
I
,
I
I
A1
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
B8
B1
1%
85
0
0
0
0
0
Q
0
I
6
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
o·
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
lAs lAs 1A4I A 3
6-53
A2
I A,
.
LSB
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
0
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
I
I
I
46
49
50
51
Q
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
I
$
I
0
0
0
0
.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
MSB
CONTINUING BINARY
SEQUENCE
I
I
0
0
LSB
I
I
44
47
OUT1IUT
MSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
'I
0
0
0
0
1
1
1
1
0
0
1
0
0
0
'0
0
0
0
0
0
1
.1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
1
1
.1
0
1
1
1.
1
0
1
1
1
1
1
0
1
1
1
1
1
1
0
1
0
0
0
0
.0
0
0
0
0
1
1
1
1
1
1
1
1
B4
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
1
'1
'0
1
1
1
1
1
1
0
0
1
0
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
0
1
1
1
1
0
0
.0
0
0
0
1
1
0
1
0
Q
0
0
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
B3
82
0
0
1
0
1
1
1
0
1
0
1
1
1
0
1
0
1
0
.1
0
1
1
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
1
0
l'
0
1
0
1
0
1
0
1
0
0
0
0
0
1
B,
a:
a:
N
N
code conversion tables(con't)
an
::IE
::E
......
a:
a:
po
N
N
•::E
::E
FUNCTION
CODE
INPUT
OUTPUT
ASCII
SYMBOL
EBCDIC
SYMBOL
MSB
64
@
@
1
65
66
67
A
8
A
8
c
C
0
ROM
ADDRESS
6B
0
69
70
E
F
E
F
71
G
H
G
H
72
73
74
75
76
I
I
J'
J
INPUT
,
OUTPUT
LSB
1 01010101010
I
I
I
K
L
L
77
M
M
78
79
80
81
82
N
0
p
N
0
p
I
a
a
R
R
CQNTINUING BINARY
SEQUENCE
83
84
85
86
87
S
S
T
v
T
U
V
W
x
W
88
89
90
91
92
93
94
95
96
97
Y
z
x
y
Z
I
I
\
I
NL
1\
,r
RES
a
b
b
99
100
101
102
'103
e
e
d
f
f
9
h
i
j
9
h
i
j
107
k
k
I
I
m
m
n
n
0
0
•
•
,
,
q
q
· ·
t
u
t
v
u
w
v
w
x
y
x
y
z
z
!
,,
,
-
OEL
0
0
a
0
A71
A6
1
1
1
a
a
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
a
a
a
a
a
0
1
a
a
6·54
A,
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
°
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
I As I A4 J A3 I A21
,I
a
1
1
,
1
1
1
1
1
a
1
1
I
I
t
OEL
1
a
a
a
I
I
I
I
I
I
I
I
I
I
· ·
d
108
109
110
111
112
113
114
115
f16
117
118
119
120
121
122
123
124
125
126
127
1
a
98
104
105
106
1
I
I
I
I
I
a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
L5B
a
1
1
1
K
U
MSB
1
1
a
0
0
0
a
0
0
0
0
0
a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
a
a
a
a
a
a
1
1
1
1
1
a
0
a
a
1
1
1
1
1
1
1
1
1
0
P
°
0
0
°a
a
0
1
1
1
0
1
a
a
a
a
a
a
a
0
a
1
1
1
1
1
1
1
1
1
0
0
0
lis
B7
Bt;
BS
a
a
1
0
a
a
a
a
a
a
0
0
0
1
1
a
a
a
a
a
0
1
1
1
a
1
1
1
0
a
a
a
a
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
° °
°a 0°
°0
a
0
1
0
1
0
0
0
a
0
1
1
1
1
1
0
0
0
0
0
°
0
0
0
0
a
0
0
1
a
1
1
1
1
1
1
°
B4
0
1
1
1
1
a
°
°
0
1
1
1
1
0
a
1
1
1
1
1
°
1
1
0
1
a
a
a
0
1
1
a
a
1
a
1
a
1
a
1
1
a
a
a
a
1
a
1
0
a
a
a
0'
a
1
a
a
1
1
0-
0
1
1
1
1
0
1
1
1
0
'0
a
a
a
°
°
1
0'
'I
1
1
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
0
1
1
a
0
a
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
a
1
a
1
a
1
0
·1
0
1
1
0
1
0
1
0
1
°a
°
1
1
0
a
a
0'
1
1
°
1
0
0
1
1
1
1
1
1
0
1
0
1
1
1
1
'0
1
B3
B2
B,
a
0
1
a
1
1
"
Semiconductor'
~National
a
MOS ROMs
s:
s:
~
N
W
o
.......
s:
s:
MM4230 / MM5230 2048-bit read only memory
UI
N
W
o
general description
The MM4230/MM5230 is a 2048·bit static read
only memory. It is a P·channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold voltage technology. The device is a non·
volatile memory organized as 256·8 bit words or
512·4 bit words, Programming of the memory con·
tents is accomplished by changing one mask during
the device fabrication. Customer programs may be
supplied in a tape, card, or pattern selection format.
no clocks req uired
output wire AND
capability
• Chip enable output control.
• Static operation
• Common data busing
applications
•
•
•
•
•
features
• Bipolar compatibility
• High speed operation
500 ns typ
Code conversion
Random logic synthesis
Table look·up
Character generators
Microprogramming.
block and connection diagrams
SENSE AMPLIFIERS
INPUTS
OllTPtlTSt
Dual·ln·Line Package
BI(LSSI
.,
A,
A,
lNPUTA3
"
LSI INPUT A,
"
..
..
A,
"
.,
..
Ne
LSI QUTPUT 8,
INPUT~
OUTPUT8~
INPUT ArJ
OUTf'UTB3
INPUT At
OUTPUT 8.
INPlITA1
OUTPUlls
INPUT A, MBI
OUTPU18 6
v..
OUTPUTh
MODE
CONTROL
"
MSB OUTPUlls
v"
..
v"
INPUTA~
14
"
TOP VIEW
"
CHIP
ENABLE
INPU1A,
CHIP
UIAIILE'"
MODECONmOL
Note: For programming information see AN . . 100.
6·55
Ordor Number MM4230J
orMM5230J
See Package 11
Ordor Number MM5230N
See Package 18
[II
absolute maximum ratings
VGG Supply Voltage
Voo Supply Voltage
Input Voltage
(Vss -20)V
Storage Temperatu re
Operating Temperature MM4230
MM5230
Lead Temperature (Soldering, 10 sec)
V ss -30V
V ss -15V
< VIN < (Vss +O,3)V
_65°C to +150°C
_55°C to +125°C
O°C to +70°C
300°C
electrical characteristics
T A within operating temperature range, Vss = + 12V ±5% and V GG = -12V ±5%, unless otherwise specified.
PARAMETER
Output Voltage Levels
MOSto MOS
Logical"'"
Logical "a"
MOS to TTL
Logical "1"
Logical "a"
CONDITION
MIN
, Mil to GND Load (Note 1)
6.8 kil to VGG Plus One
Standard Series 54n4 Gate Input
Input Voltage Levels
Logical "I"
Logical "a"
Power Supply Current
Vss
VGG (Note 1)
TA
UNITS
Vss -9.0
V
V
+0.4
V
V
Vss -8.0
V
Vss -1.0
+2.4
V
= 25°C
24
= Vss -12V
VIN
Input Capadtance
f = 1.0 MHz
Access Time (Notes 2, 3)
TA = 25°C
(See Timing Diagram)
Vss = +12V VGG = -12V
Output AND Connection
MAX
Vss -2.0
Input Leakage
TACCESS
TYP
VIN
= OV
40
1
mA
J1.A
1
IlA
pF
5
150
500
MOS Load
TTL Load
725
ns
3
8
Note 1: The VGG supply may be clocked to reduce device power without affecting access time.
Nota 2: Address time is measured from the change of data on any input or Chip Enable line to the output of a TTL gate.
See Timing Diagram.
Note 3: The access time in the TTL load configuration follows the equation: T ACCESS = the specified time + (N - 1) (50) ns
where N = number of AND connections.
Note 4: The above logiC levels afe indicated in negative logic notation.
6·56
performance characteristics
Typical AccesS Time vs
Supply Voltages
Guaranteed Access Time
vs Supply Voltages
.~
• 'll5"C
1000
]:
T••
1000
;;:r
T•• lS"c
BOD
800
]:
J:
.
if
H
600
... 400
!Z5"e
I I
10"e
200
200
10.8
12.0
10.8
13.2
12.0
Power Supply Current
vs Temperature
60
TA "'25'C
Vss .. +12.0V
40
MAX
50
36
~
13.2
V.. &Vo. (VI
Power Supply Current
vs Voltages
0
'11:
·f5IC~
V.. & v.o (VI
<-.§
H:)I+-
40
<-.§
32
28
;
TVPICAL-
VGG
MAX
-
f-iVPleAL
......
3D
18
20
I"-
io....
20
24
=-12.0V
.l'o
0
10.8
12.0
13.2
~5O
-25
Vss & VGG (V)
0 25 50 75 100 125 150
TEMPERATURE eel
timing diagram/address time
+lv
.,v
"TL
.V .
I
UK
I
INPUT At.!
OM881D
E...
E,.
ov
+12V
.,v.V
'O~
I
MM423D!MM5Z30
-!: '-
T
'OPF
~
+12V
·,v
OUTPUT 11M
I
I
10 pF
6.8K
j::
--
ANY OHlTTl
GATE
-Jv
-----,
EITHER
~'--I
~~
1.5V
•
.,v
1.5V
OV
time
6·57
j::
--
EOUT
15 pF
typical application
256 x 8 Bit ROM Showing TTL Interface
-12V
tlZY
.,.
--~------~--~-----------------t ..
CHIP
ENAILE
f
MODE
CONTROL
13
"
"
..
..
11
A,
-t
... ....
l.oKA.
......
TTLeATES
N.C.
N.C.
v,.
..
Uk
I,
ts
Y"
A,
________~__~-+__+-__~.-_.,v
U.
I.
MM42J0IMM5lJO
".
I,
"
"
21
I,
..
A,
>,
"
>,
tSee operating mode notes.
*R willes can vary from 140U to 3(1 kn.
OPERATING MODES
128x8 ROM connection
Mode Control - Logic "0"
Ag
- Logic "1"
256x4 ROM connection
Mode Control - Logic "1"
Ag
- Logic "0" Enables the odd
(B I ••• B7 ) outputs
- Logic "1" Enables the even
(B 2 ••• B8 ) outputs.
The outputs are "Enabled" when a logic "1" is
applied to the Chip Enable line.
The outputs are connected to V DO through an
internal MaS resistor when "Disabled."
The logic levels are in negative voltage logic notation.
6·58
}--
~National
MOS ROMs
~ Semiconductor
s:
s:
..
N
W
o
OJ
o
......
MM4230 BO/MM5 230BO, MM4231CMU/MM 5231CMU
hollerith to ASCII code converter
gener~1 description
s:
s:
U'I
line binary encoded form suitable for use by the
read-only memory. This application is shown
below.
The MM4230BO/MM5230BO 204B-bit MOS readonly memory has been programmed to convert the
12 line Hollerith punched card code to eight level
ASCII. This conversion conforms to the Amer.ican
National Standard (ANSI x 3.26 - 1970). Three
TTL 4-input NAND gates, and three inverters are
used' to compress the 12 Hollerith lines to eight-
For electrical, environmental and mechanical de·
tails, refer to the MM4230/MM5230 or the
MM4231/MM5231 data sheets.
N
W
o
OJ
o
s:
s:
..
N
typical application
IIDlURITHTDASCII
'
~
..
n
MODE
tQNIROl
DUTPUT,
ASCU-8
"
.,
",
s:
c:
......
s:
s:U'I
"
N
W
'.
(")
'.
c
~
PUNCHED
CARD.
DAta
lll'UT
AS
za
ZO"'(,:_------"'j
'.
"
PUNCHES
,,-----------------'''1
ANYOTL/TTL
Note 1: Vss" +12V '10%. Voo = GND. VGG " -12V !tD%.
DEVICE
Note 2: The Holielith input data (lines 1 throu!lh 12) is considered to be from
nOflniilly open switctles returned, in the case of a pinched hole,. to GND IS shown.
VOD
connection diagram
V(lC
Dual~ln~Li'le Package
.,
24
Vou
"
E,
."
0,
E,
Eo
"
"
E,
.
'"
a,
10
B.
11
MDD~
CONTROL
'"
"
ENABLE
6-59
Order Number MM4230BO/J
MM5230BO/J, MM4231CMU/J
or MM5231CMU/J
llee Package 11
Order Number MM5230BO/N
or MM5231CMU/N
See Package 1 B
'.
HIGH
TRUE
s:
~
:E
U
;;
code conversion table
N
Hollerith to ASCII
In
:E
':E
12
12
......
12
11
11
0
~
:E
u
....
('I)
0
11
0
12
11
0
12
11/10
10/8
11/1
11/9
8/1
12
11
0
&
-
if>
SP
I
,,
1 A
J
/
1
a
j
-
13/9
SOH
OCI
2
K
S
2
b
k
5
13/10
STX
B
I
12
11
11
0
0
12
11
0
12/3
12/10
13/1 .13/8
9/1
10/0
10/9
9/15
11/11
9
8-1
DC2, 8/2
SYN
10/1
10/10
11/2
11/12
9 -2
OC3
-1
N
3 C
L
T
3
c
I
t
13/11
liTX
8/3
9/3
10/2
10/11
11/3
11/13
9
:E
:E
4
0
M
U
4
d
m
u
13/12
9/12 9/13 8/4
9/4
10/3
10/12
11/4
11/14
9 -4
5
E
N
V
5
e
n
y
13/13
HT
B/5
LF
9/5
10/4
10/13
11/5
11/15
9
-5
6
F
0
W 6
f
0
13/14
8/6
BS
ETB
9/6
10/5
10/14
11/6
12/0
9
-6
7 G
X
7
13/15
DEL B/7
ESC
~OT
10/6
10/15
1117
12/1
9 -7
Y
8
9
h
P
B H
P
Q
w
x
q
y
14/0
9/7
.CAN 8/8
9/8
10/7
11/0
11/8
12/2
9
9
R
Z
9
i
,r
z
14/1
8113
EM
8/9
9/9
NUL
OLE" 8/0
.9/0
9-8-1
1
\
15/10 9-8-2
=
12/8
12/15 13/6
14/6
SO
RS
ACK
9/14
14/12
15/2
15/8
15/14 9-B-6
?
"
12/9
13/0
14/7
51
U5
BEL
SUB
14/13 15/3
15/9
15/15. 9-8-7
$
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 data sheet.
typical applications
"12 ______________- - ,
.--------" 1
n-------,
r-----,.-~"
CUDE
' 'fROM'
PUT$,
SELECTRIC
,----li1
Ri
R2=H~~E~~~~jj
"lCASi
"H-----+-jH-H-Mr-".
I
s~~~~~~~o ~
,_
'++-+1-1----,
··H-----....-1f+H+lr..
'+++++---"'
1
L.+-++---J;, ,
'+++---~
ASCII !
TRUf:
l
r"-------"" ~~~:~~
R2A
BAil
1::'.:\':::'
11$, _ _ _ _ _ _- '
t=EiQ-~!==""JI
",----------'
. '", _ _ _ _ _ _.J
~:~i! A---:':;;":;:;GH;:,=,,,:::,.-;~:::_=·-:,::::..~=,--""'-""'-i
"LOWStIICtrictur.stlllnpul
Encoding 'Space' by Gating' In on Input
ENCODIIIlG
'SI'~CE'BYGAnNG1N
Decoding 'Space' on Output
SELECTRIC TA"lE SHOWS 9'ACE AS %, T" R,
OEC061NG
'gAtE'
,,-------m
'SPAC~'
CLOSIIRE
r"
r:-:.~>---"
-+-------""
.J,
i"
I
BAtl CODE FROM
CONI/ERTER
LOW TRuE
_~LJOO----'IT
n
Iii
"
Sl'ACEMAGNET
r----'
DRIVfR
I
I
I
I _ _ _ _ JI
....
LM351 PERIPHERAL
I~
~--~--i------'IT
l CASE
Order Number MM4.230KP/J or MM5230KP/J
Order Number MM5230KPIN
See Package 11
See Package 18
6-61
code conversion tables
Table 1. ASCII·7 to Selectric
~"
•
.
b4
b3
t
t
bf
0
0
0
..
t
•~
0
0
1
1
0
0
1
0
2
0
0
1
,
3
0
1
0
I)
4
0
,
5
0
1
1
0
6
0
1
,
1
7
1
0
0
0
8
1
0
0
,
9
1
0
1
0
A
1
0'
1
1
B
1
1
0
0
C
·1
1
0
0
0
1
D
1
1
1
0
E
1
1
1
1
F
0
0
1
1
0
0
Row
0
0
1
0
b1
0
0
.
OLE
SOH
1
1
1
1
1
0
@
P
!
1
A
Q
a
q
"
2
B
R
b
r
62
IA
DC2
0
0
0
SP
DCI
STX
1
0
5
OA
12
1
1
4
2
02
1
3
1
NUL
0
0
6
7
25
P
22
2A
ETX'
32
DC3
'3A
==
3
C
S
c
5
EOT
DC4
OB
$
4
q
T
d
t
%
5
E
U
e
u
&
6
F
V
f
v
7
G
W
9
w
(
8
H
X
h
)(
)
9
I
Y
i
Y
Z
i
z
03
ENQ
NAK
13
1B
SYN
ACK
23
BEL
2B
ETB
33
BS
3B
25
CAN
42
4A
HT
EM
5A
52
LF
SUB
53
VT
6A
ESC
7A
72
FF
.
+
72
48
GS
51
58
SO
63
RS
SI
Lis
73
6B
7B
6·62
K
<
FS
CR
J
40
-
=
..
>
I
?
L
M
[
7F
\
60
I
77
1\
50
N
0
70
-
k
I
I
:
m
I
n
0
7F
48
77
- 58
DEL
00
1
code conversion tables (con't)
Table 2. Selectric to ASCII·7
RS
,
T,
0
R2A
R2
R,
K
Row -
I I I l •
0
0
0
0
0
0
1
1
0
1
2
b
w
0
0
T2
S
0
0
0
1
0
1
1
1
1
0
1
0
1
1
0
3
4
5
6
0
-'
2/0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
Q
k
0
1
0
1
5
P
e
0
1
1
0
6
0
1
1
1
7
J
t
1
0
0
0
8
-
B
W
(
1
0
0
1
9
y
H
S
)
1
0
1
0
A
1
0
1
1
B
1
1
0
0
C
Q
1
1
0
1
0
P
E
1
1
1
0
E
+
N
y
h
s
.
3/0
0
I
I
SIC
1
F
4
6/F
~ ~ ~ ~ ~ ~ ~~ ~
~ ~ ~~ ~~ ~ ~
=
3/0
i
n
6
2/C
c
•
·8
d
r
7
217
5
2/E
2
f
u
v
3
z
9
X
m
1
%!
2/1
3/B
~~ W
L
?
0»
0
$
4/F
~ ~ ~ ~~~ ~ ~
~ ~ ~ ~~ ~ ~ ~
K
~
I
4/9
"
2IE
2/C
6/3
C
A
.
%
:
0
R
&
@
F
U
V
#
Z
G
X
M
%,0
1
7
~ ~ 'l/U W~
9
0
0
1
1
•
0
1
1
J
T
F/F
±[
5/B
ASCII shown thus, Column No./Row No,
6·63
~National
MOS ROMs
~ Semiconductor
MM42311MM5231 2048-bit read only memory
general description
The MM4231/MM5231 is a 2048-bit static read
only memory_ It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold voltage technology_ The device is a nonvolatile memory organized as a 256-8 bit words or
512-4 bit words. Programming of the memory
contents is accompl ished by changing one mask
during the device fabrication.
Bipolar compatibility
High speed operation
Static operation
Common data busing
No clocks required
Output wire AND
capability
•
Chip enable output control
a ppl ications
•
•
•
•
•
features
•
•
•
•
+5V, -12V operation
640 ns typo
Code. conversion
Random logic synthesis
Table look-up
Character generator
Microprogramming
block and connection diagrams
Dual-In-Line Package
SENSE AMPLIFIERS
OUTPurst
"
U.n! AI
A,
IfilPUTAl
"
lNPUTA z
" "
"
B,
22
LSB1NPUTA1
A.
"
..
MEMORY
.
ADDRESS
DECODER
..
"
.
LSa OUTf'UTBI
OUTPUT 82
MODECOMTROL-----t....J
tThe OutPUtslf9 open when Di5llbled.
* The olrtput is enabled by applving a Logic "1" to tfte Chip E\1able line,
Note: For programming information see AN-100.
6-64
.
INPUT",
11
INPUTA7
OUTf'UT B3
IHPUTAs,
IIilPUTAc;
OUTPUT I.
OUTpUlls
IIIIPUT~
OUT1'UT~
V"
OUTPUT 17
10
"
MSB OU1PUlia
V"
A. _ _ _. - _............_ - - - - - CHIP
EIIABLE·
Voo
"
"
TOP VIEW
"
MODE
CONTROL
till'
ENABLE
INPUT""
Order Number MM4231J
orMM5231J
See Package 11
Order Number MM5231N
See Package Uf
MSB
s:
s:
absolute maximum ratings
~
N
...
to)
VGG Supply Voltage
Voo Supply Voltage
Input Voltage
Storage Temperature
Operating Temperature
(VSS - 20)V
<
MM4231
MM5231
Lead Temperature (Soldering, 10 sec)
.......
V SS - 20V
Vss - 20V
VIN
(V ss + 0.3)V
_65°C to +150°C
_55°C to +125°C
O°C to +70°C
300°C
s:
s:
U'I
<
N
...
W
electrical characteristics
PARAMETER
CONDITIONS
MIN
Output Voltage Levels
MOS to TTL
Logical "1"
Logical "0"
6.8 kn ±5% to Voo Plus One
Standard Series 54/74 Gate
Output Current Capabil ity
Logical "0"
VOUT= 2.4V
Input Voltage Levels
Logical "1"
Logical "0"
Power Supply Current
100
IGG (Note 1)
Input Leakage
TYP
MAX
UNITS
+0.4
2.4
V
V
2.5
mA
Vss - 4.2
V
V
30
1
mA
/lA
1
/lA
Vss - 2.0
TA = 25°C
Vss = +5V
VGG = Voo= -12V
15
VIN = -12V
Input Capacitance
f = 1.0 MHz, VIN = OV
5
pF
V GG Capacitance
f = 1.0 MHz, VIN = OV
15
pF
Address Time (Note 2)
See Timing Diagram
T A = 25°C Vss = +5.0V
VGG = \!oo = -12.0V
TACCESS
Output AND Connections
(Note 3)
640
6.8 kn ±5% to Voo Plus One
Standard Series 54/74 Gate
Note 1: These specifications apply for VSS = +5V ±5%, VGG ~ VOO ~ -12V, ±5%, and TA ~ -55"C
to +1250 C (MM4231), TA ~ _25°C to +"?OoC (MM5231) unless otherwise specified.
Note 2: The VGG supplV may be clocked to reduce device power without affecting access time.
Note 3: Address time is measured from the change of data on any input or Chip Enable line to the
output of a TTL gate. (See Timing Diagram.) See curves for guaranteed limit over temperature.
Note 4: The address time in the TTL load configuration follows the equation:
TACCESS ~ The specified. limit + (N - 1) (50) ns.
Where N = Number of AND connections.
Note 5: Capacitances are measured on a lot sample basis only.
6·65
950
8
ns
performance characteristics
Guaranteed Access Time- (T A)
vs Power Supply Voltage
Typical Acee.. Time (TAl
YS Power Supply Voltage
1400
1400
voo = vGG
1200
1000
Voo = VaG
+)2~'e
1200
+70 C
1000
Q
+25 0'e
.s
"'"
....
<
800
]
800
+1,25~C
600
~ 601)
+2S C
400
400
200
200
~70~C
Q
0
0
16.0
11.0
18.0
16.0
11.0
Power Supply Current vs
Ambient Temperature
Power Supply Current vs
Power Supply Voltage
40
32
T. - 25'C
28
24
:c
.e
0
.E
Vss '" +6.0V'
36
32
7u':.~~':T~~D
:c
24
0
20
16
E
16
0
TYPICAL
..L.L I II
-
MAX1MU'i?;:
GUARANTEED
-
IIII
J-+.WJ.
12
8
·'Tn
8
4
4
0
IIII
0
16.0
-SO -25
18.0
11.0
J+.
VOD '" VGG =-12V
28
20
12
18.0
Vss - VaG (V)
Vss - VaG (V)
0 +25 +50 +15 +100+125
TA reI
Vss - VGG (VI
timing diagram/address time
1\
€ITHER
E"
I~
-.::.J~T""~I
v~ - 2.0V
1.5V
EOUT
I
1.SV
time
"J"L
OV
.,.I
ANY TTL/DTl
GATE
~ivss
INPUT AN
fiN
'*
--::I....
'5'
I
OUTPUT 1M
MM4ZJ1!MM5231
10 pF
v••
Ir
6-66
111 pF
6.BK
* *
~
ANY TTl/DTl
GATE
-tTv
l15 pF
fOUT
3:
3:
typical application
~
N
W
....
......
3:
3:
256 x 8 Bit ROM Showing TTL Interface
U'I
N
....
W
..V
A,
t
.
eKIP
ENAILE
.,
B,
t
MODE
CONTROL
..
..
v"
..
A,
11
MM42J11MM!!Z31
.'"
-(
tSee Dperating mode notes.
DTUTTLlDGIC
"
B,
"
" "
B.
NO
A,
v••
1
}-
U •
S.
A.
TTLGATU
u•
A.
l<
A.
I
1
1
Operating Modes
256 x 8 ROM connection (shown)
Mode Control - Logic "0"
Ag
- Logic "1"
512 X 4 ROM connection
Mode Control - Logic "1"
Ag
- Logic "0" Enable. the odd
161 • B3 ... Bg) outputs
- Logic "1" Enables the even
(B2. B4 ... B8) outputs.
The outputs are "Enabled" when a logic "'" is
applied to the Chip Enable line.
Logic levels are negative true MOS logic.
Mode Control should be "hard wired" to VDD
(Logical "1") or VSS (Logical "0").
The logic levels are in negative voltage logic notation.
6·67
~National
MOS ROMs
~ Semiconductor
MM4231RP/MM5231RP EBCDIC to ASCII-7 code converter
general description
The MM4231RP/MM5231RP is a 2048-bit readonly memory that has been programmed to convert from EBCDIC, an extended binary coded
decimal interchange .code used in the IBMl130
computer, to ASCII-7, the Americ.an Standard
Code for Information Interchange in seven bits.
conversiol"J of the MM42300X/MM523QQX in that
it follows certain earlier IBM 1130 character assigl"Jments_ Also certain EBCDIC control codes are
arbitrarily preserved and translated (see translation chart on truth tablel.
For electricai, envi~onmental and mechanical details. refer to the MM4231/MM5231 data sheet.
This conversion differs from the ANSI x 3_26
typical application.
EBCDIC TO ASCII-7
••v
l,t"
.u,
"
'ItO
LOWT
....
lit
o-!!. ..
a, u
~
B,
.
o-!!- ..
.
o-.!!. At
LSI
ASC"
HIGM TR
o--!!- ..
o---!- ..
o---!- ..
o---!- A,
...."
.. U...... ic
c[>- HIGH
LOW-C.ntral
.....
"
~::-
. •
.. •,
.
.. ,•
11.24,13
b,
v--o
.......
~
~
-"
a,
I,
u,
~'
e
!UK
UK
U'
UK
&.IK
UK
U.
U.
.......
.-.:;'"
...
-12V
Ordor Number MM4231 RP/J '" MM5231 RP/J
Order Number MM5231 RP/N
See Package 11
See Package 18
6-68
code conversion tables
COOE
FUNCTION
ROM
AOORESS
0
1
2
3
4
5
•
7
8
..
INPUT
OUTPUT
EBCOIC
SYMBOL
ASCII
NULL
SOH
STX
ETX
Pf
HT
CC
eEC
10
11
12
13
14
SMM
VT
ff
CR
15
I.
17
18
51
eCE
eCl
I.
20
21
2.
23
24
25
26
27
28
29
3.
31
3'
33
34
3.
36
37
3B
39
SO
eC2
eC3
RES
NC
8S
IDC
CAN
EM
CC
CUI
fCS
GS
RDS
US
SYMBOL
MSB
NUC
SOH
STX
ETX
0
0
0
0
0
HT
\
0
0
0
0
•
0
0
0
0
0
MSB
0
0
0
0
0
0
1
0
I
I
I
I
I
I
\
CAN
EM
fS
GS
RS
US
SDS
fS
LSB
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0,
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
•
1
0
0
1
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
•
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0,
0
0
0
0
•
'0
1
'I
1
0
1
0
0
•
0
0
0
0
• •
•
0
1
1
0
0
1
1
0
1
1
0
1
0
1
Q
CONTINUING BINARY
SEQUENCE
END
ACK
BEC
SYN
SYN
I
I
I
PN
FlS
54
Oc
55
EDT
E.OT ..
CU3
DCA
NAK
NAK
SUB
SUB
0
I
I
I
I
I
.......
DCO
56
51
56
,
As
A7
As
AsI'"
0
0
••
• •
I
49
.2
53
0
0
0
0
I
Cf
ETB
ESC
END
ACK
BEc
ea
CC/G
0
1
I
ss
SM
CU2
6'
62
LSB
I
eCl
eC2
DC3
44
46
45
47
4B
59
60
0
0
0
1
1
0
I
I
VT
ff
CFI
SO
SI
eCE
4.
43
50
•
0
0
0
0
1
I
4.
41
.,
0
0
0
0
0
0
0
0
"""
eEC
os
BYP
Cf
EOB
PRE
OUTPUT
INPUT
\
Aa
6-69
A2
A,
0
1
•
•
0
•
0
0
0
0
1
0
1
0
•
0
•
0
0
0
1
0
0
•
0
•
1
0
,
0
,
0
0
0
Be
B7
B8
1
as
1
1
0
1
0
B4
83
B2
8,
Q.
...a::
M
N
code conversion tables(con't)
It)
:t
:t
.......
-
...
a::
M
N
~
:t
:t
CODE
FUNCTION
Q.
ROM
ADDRESS
64
65
INPUT
OUTPUT
EBCDIC
ASCII
SYMBOL
SYMBOL
S?
SP
MSB
\
--...-
66
68
69
70
71
73
7.
75
,
<
77
{
(
78
+
+
&
&
88
89
90
I
,
91
$
$
)
,
;
A
I
0
0
LSB
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
0
0
1
0
1
0
0
a
0
1
1
a
1
0
1
0
1
0
a
1
1
1
1
1
1
a
1
1
0
1
0
0
1
1
1
0
1
a
0
0
1
1
1
I
I
I
105
106
%
-
%
>
>
?
?
1
1
I
I
I
I
I
113
11.
115
116
1
0
1
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
1
a
0
1
1
0
1
1
1
1
0
1
1
0
0
0
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
0
1
1
1
1
1
1
0
1
0
1
1
0
0
1
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
I
1-17
118
I
I
I
119
120
121
122
123
0
CONTINUING BINARY
SEQUENCE
101
12'
125
126
127
0
I
)
;
102
103
104
110
111
112
0
I
-
96
97
98
99
100
109
1
I
I
8'
85
.86
87
107
108
0
I
I
:
82
83
9'
95
MSB
1
I
I
-
<
92
93
CCIG
I
I
76
79
80
81
LSB
I
67
72
OUTPUT
INPUT
#
#
@
@
..
..
~B I
A7
-
I AS I AS I A4. I A3 I A2 I A~
6-70
1
0
1
1
1
0
1
1
1
1
0
0
1·
0
0
1
1
1
B8
B7
B6
1
1
0
1
0
0
0
1
1
0
0
0
1
0
1
1
0
0
0
B.
1
0
0
1
1
1
0
B3
B2
8,
0
0
0
BS
1
code conversion tables(con't)
FUNCTION
ROM
ADDRESS
CODE
INPUT
OUTPUT
EBCDIC
SYMBOL
ASCII
SYMBOL
a
12.
130
a
b
b
131
c
.
132
133
13.
135
136
137
.
d
f
9
h
i
i
,.,
,.2
143
14.
145
j
146
k
k
147
14B
I
I
m
m
14'
150
n
n
0
0
151
152
P
P
q
q
153
I
I
I
I
I
j
,
154
155
156
157
1
0
.0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
a
a
1
0
1
1
1
0
0
1
1
a
1
0
0
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
1
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
.0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
1
0
1
SEQUENCE
,
,
t
t
1
1
164
u
u
165
166
167
lG8
v
x
v
w
x
V
V
1
1
1
1
171
172
173
17.
1
1
0
1
1
1
169
170
1
1
0
a
a
1
0
1
1
CONTINUING BINARY
158
15.
lGO
lGl
162
lG3
1
1
1
1
1
1
1
1
I
I
I
13B
13.
140
LSB
MSB
1
1
I
f
CC/G
I
I
d
h
.......
I
c
g
LSB
MSB
\
128
OUTPUT
INPUT
w
,
,
I
I
I
I
1
1
1
1
1
1
1
0
0
0
1
1
a
1
0
0
0
1
1
0
1
0
1
1
0
1
1
0
1
1
1
0
1
Bs
BS
B4
B3
B2
B,
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
B8
B7
0
1
1
175
176
177
17B
179
180
,.,
,.2
183
18'
185
18G
187
188
,.9
,
......
190
191
;8
I A7 I As I As I A4 I A3 I A2 I A,
6-71
A-
a:
~
N
In
code conversion tables(con't)
:E
......
==
a.
a:
FUNCTION
INPUT
OUTPUT
~
ROM
ADDRESS
EBCDIC
SYMBOL
ASCII
SYMBOL
~
'.2
"3
194
195
196
191
+ZERO
A
B
N
==
~
,.8
e
0
E
0
E
G
H
201
202
203
204
205
206
201
208
209
210
211
I
I
I
I
I
I
I
-ZERO
J
J
K
K
L
L
M
M
N
N
0
P
0
P
a
a
R
R
CCIG
LSB
MSB
J
I
I
I
I
F
G
H
1
1
1
1
1
1
1
1
1
1
I
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
I
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
I
0
0
0
0
0
0
0
0
0
1
1
I
1
1
1
1
1
0
0
0
0
0
1
1
I
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
1
1
1
1
0
0
0
0
I
0
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
,
0
0
0
0
0
0
0
0
1
1
86
B!i
B.
83
82
,
1
1
, ,
I
21'
220
221
222
223
CONTINUING BINARY
SEQUENCE
22'
I
I
I
~25
24'
246
241
248
24.
250
251
252
253
254
255
LSB
A
I ••
226
221
228
229
230
231
232
233
23.
23.
236
231
238
239
240
241
242
243
244
OUTPUT
....,.
B
200
2'2
213
21.
215
216
211
218
MSS
\.
e
F
CODE
INPUT
S
S
T
T
U
U
V
V
W
W
X
X
Y
Y
Z
Z
0
1
2
3
4
0
1
2
3
•
6
7
8
9
1
1
1
1
I
1
1
1
I
I
I
1
1
1
1
1
1
1
1
I
I
"
5
6
7
8
9
I
I
1
1
1
1
,
,
1
1
1
1
1
1
1
1
1
,
A4
A3
A2
A,
1
1
1
A7
As
As
6-72
1
1
1
I
1
0
0
1
B8
87
1
1
1
1
1
1
1
1
1
,
1
1
1
,
1
0
1
0
1
0
1
0
1
,'\
1
As
0
1
1
1
1
1
I
1
1
1
1
1
1
0
0
0
0
0
0
0
0
,
A.
1
1
1
0
0
0
1
0
1
B,
~National
MOS ROMs
~ Semiconductor
MM4232/MM5232 4096-bit static read-only memory
general description
features
The MM4232/MM5232 4096-bit static read-only
memory is a P-channel enhancement mode monolithic MaS integrated circuit utilizing a low threshold voltage technology to achieve bipolar compati·
bility. TRI·STATE™ outputs provide wire ORed
capability without loading common data lines or
reducing system access times. The ROM is organ·
ized in a 512 word x B-bit or 1024 word x 4-bit
memory organization that is controlled by the
mode control input. Programmable Chip Enables
(CE I and CE 2 ) provide logic control of up to 16K
bits without external logic. A separate output
supply lead is provided to reduce internal power
dissipation in the output stages.
•
Bipolar compatibility
No external
components required
• Standard supplies
•
+5V. -12V
Bus aRable output
TR I-STATE outputs
• Static operation
No clocks requ ired
•
Two-programmable
Chip Enable lines
Multiple ROM control
applications
• Character generator
• Random logic synthesis
• Microprogramming
• Table look-up
logic and connection diagrams
A,
Dual-In-Line Package
24
Cf,
23
I--i'ot-~ B,
A,
I--i'ot-i:-O B,
A.
MODE CONTROL
A.
Ba
21
87
20
..
~--D---I~ B.
..
10
A]
11
14
~
ViiS
12
Il
..
I---tt===l'-o B.
I---Qo-l~.,
A,
A,
II,
1
•
111
84
11
83
1682
158, LSI
TOP VIEW
A"
Order Number MM4232J
orMM5232J
See Package 11
CE,o---------I
ce,o---------I
Order Number MM5232N
See Package 18
Note: For programming information see AN-100.
6·73
MSB
" ..
•
B,
MEMORY
ARRAY
.
VGG
22
.
I--~Fr-OB,
A,
A,
Vu
MSB
absolute maximum ratings
VGG Supply Voltage
V LL Supply Voltage
I nput Voltage
(V ss - 20)
Storage T emperatu re Range
Operating Temperature Range MM4232
MM5232
Lead Temperature (Soldering, 10 sec)
electrical characteristics
TA
v<
V ss - 20V
V ss -20V
V 1N < (V ss + .03)V
-65°C to +150°C
-5SoC to +125°C
O°C to +70°C
300°C
POSITIVE LOGIC
within operating temperature range, Vss
PARAMETER
= +5.0V ±5%, V GG = Vee = -12V ±5%, unless otherwise noted.
CONDITIONS
Output Voltage Levels
Logical "0", VOL
MIN
TYP
MAX
.4
IL == 1.6 rnA Sink
IL
Logical "1", VOH
::=.
UNITS
V
2.4
100J.{A Source
Y
Input Voltage Levels .
Y ss - 4.0
Vss + 0.3
Y
V
23
12
37
mA
mA
5
15
pF
10
pF
1000
n5
Y GG
·Y ss -2.0
Logical "0", V 1L
l;.ogical "1", V 1H
Power Supply Current
Vss=5.VGG=-12,VLL=-12,TA=25°C
Vss" 5. VGG "-12. V LL "-3. TA = 125'C
Iss (Note 4)
Iss (Note 4)
1
Input Leakage
VIN = Vss - lOV
Input Capacitance (Note 1)
f:= 1.0 MHz, V IN
'"
OV
Output Capacitance (Note 1)
f = 1.0 MHz, V IN
'"
OV
Address Time (Note 2)
TA" 25"C, Vss" 5
VGG
TACCESS
= VLl
20
4
150
p.A
'" -12V
20
Output AND Connections (Note 3)
Note 1: Capacitances are measured periodically only.
Note 2: Address time is measured from the change of data on any input or Chip Enable line to the output of a TTL gate.
(See Timing Diagram.)
Note 3: The address time follows the following equation: T ACCESS = the specified limit + (N -11 x 25 ns where N = Number
of AND connections.
Note 4: Outputs open.
timing diagram/address time
IV
..v
':JL
..v
E"
MM4232/MM5231
54/7.
GATE
*lDPF
.t; T
10 PF
....,.
GATE
E~
I,r-'1.5
Tn"
TIME
6-74
performance characteristics
1100_
••
I_
1
Guaranteed Access Time vs
Supply Voltage
Typical Access Time vs
Supply Voltage
1600
VLL - VGG
VLL =VOG
1400
121i'C
12110 T.-7I1"C
21i'C
1000
1210
I
~IOO
125"C
1000 T.-70"C
25°C
BOO
4
.... alO
:
400
ZOU
20U
17.B
17.0
11.2
11.2
v.. + IVOGI IVI
Power Supply Current YS
17.'
Power Supply Current YS
Voltage
.
T emperatu re
BO
17.0
Vss + IVoG I (V)
V.. - 5.0V
70
70
YGc· VLL = -12V
·10
10
01 50
01 50
.540
IllAXIMUM
~
30
.540
MAXIMUM
3D
TYPICAL
~
TYPICAL
20
20
10
10
-50 -25
0
25
50
75 IOU 125
1&.2
TEMPERATURE lOCI
17.0
17.1
V.. +IVGGIIVI
typical applications
TTllMOS Interface
..
FIGURE 1. Power Saver for
Small Memory Arrays
FIGU RE 2. Power Saver for
large Mem e>ry Arrays
--,
....
r----,
I
I
I
I
-=
I
I
I
I
I
I
I
L ___
L ___ ..J
ASSUME IIVLL 1111111 = II-:JV II
VOO-YLLMIN"R f1.BnlA) (Nlwllere
tE.o------'
tE,o-----'---'
Mode Control
"zN"'tfor6xlfolll
1 for 5x 1foat.
Operating Modes
1024 x 4 ROM connection
Mode Control = V I L
Al0 = VI L enables the odd (81 ... B7) outputs
VIH enables the even (82' .. 8a) outputs
512 x 8 ROM connection
= VIH
AlO=VIL
=
=.,
Note: Both chip enables may be programmed to provide any of four combinations: Example if CE, 1 and CE2
outputs (Positive Logic) would be enabled only when device pins 2 and 3 are logic "'''. The outputs will be in the
third state when disabled.
6·75
I
I
~
MOS ROMs
~National
~ Semiconductor
w
«
N
(¥)
N
an
:E
:;
"N
(¥)
N
~
MM4232/MM5232 AEL AEJ, AEK sine look up table
general description
meet almost any system requ irement for generation 'of the sine function.
The MM4232/MM5232 AEI, AEJ and AEK are all
P-channel enhancement mode MOS read-only memories, each storing 4096 bits. They are programmed
to generate the sine function of any angle expressed as a binary fraction of a right-angle. They
may be combined and arranged to provide a lookup table of varying resolution and accuracy, to
application information
Figures 1 through 4 show the four ways that these
parts ma'y be combined. The table shows the performance of all combinations.
:E
:E
performance specifications
FIGURE
ROM NO. USED
RESOLUTION
(= INPUT
WORD
LENGTH)
OUTPUT WORD
LENGTH
ACCURACY
ADDER PACKAGES
REQUIRED
+0
1
AEI
9 bits
8 bits
2
AEI + AEJ
9 bits
16 bits
± 112 bit in 16
0
3
AEI + AEJ +
AEK
12 bits
16 bits
± 3/4 bit in 14
4
4
AEI + AEJ +
2 AEK's
15 bits
16 bits
±1 bit in 14
6
sine of an angle
in the range 0:<::::
Theoretical Background
into 2 15 increments
This error, due to the mathematical approximation,
is ±3.2 x 10-5 maximum, corresponding to ±1 bit in
15 bits. In addition to the mathematical error, an
inevitable round-off error in the 16th bit is introduced. As there are 3 LSB outputs to be added
(Figure 4), the maximum round-off error will be
±1-112 bit in 16 bits or ±2.3 x 10'5. The theoretical
maximum total error will then be ± (3.2 + 2.3)
.x 10-5 = ±5.5 x 10.5 , which is slightly less than ±1
bit in 14 bits.
The table is based upon the equation:
= sin M cos L + cosM sin L
0
bit in 8
e resolved
e < rr/2.
SINE LOOK-UP TABLE WITH HIGH
RESOLUTION AND ACCURACY
sin (M + L)
~1
(I)
By splitting M and L each into two parts MM,
ML, and LM, LL, and (assuming M» L) the following equation is obtained.
(2)
sin (M + L) '" sin (MM + ML)
+ cos (MM + 1/2 LSB of MM) sin LM
+ cos (MM + 1/2 LSB of MM) sin LL
'" sin (MM +M L)
+ cos (MM + 1/2 LSB of MM) (sin LM + sin LL)
A computer analysis shows that the actual errors
in the table as implemented are as follows:
+4.4 x 10- 5 (at 61.872°)
The following approximations have been used:
~4.7 x
cos (LM + LL) '" 1
sin (LM + LL) '" sin (LM) + sin (LL)
cos (MM + M L) '" cos (MM + 1/2 LSB of MM)
10- 5 (at 83.142°)
As the sine function is very linear in the LM-LL
range, the third term of Equation 2 cim be considered as being 1/(2)3 of the second term without
significant error. Therefore, the same pattern can
be used for the two lower ROMs in Figure 4, and a
total of three different masks are needed. In addition, six 4-bit adders are used.
By taking MM = 6 bits, ML = 3 bits, LM = 3 bits,
and LL = 3 bits, 15 bits resolution is obtained. The
accuracy has been computed by comparing the
values of Equation 2 with the ideal value of the
Order Number MM4232J Dr MM5232J
See Package 11
Order Number MM5232N
See Package 18
6-76
(8 " 'If/2
..
....
",
(8 " n/2 RADIANS)
"'- ..
r-, ..
,..-.... .
,~..,..
A,
"1-"
A.
~- A,
...-
,~
"'-.,..
SINO
A,
SINo
A"GlE
RAmANS~
MM4232/
M~32
AEI
CEl =0
CU=O
A.
A,
.. I-"
"I-"
a. r->'
',1-2"
A,
A,
eE1 CE2
AEI
eEt =0
CE2=O
A.
r---
A,
,..-A,
r-
a,l->'
a,
MM4232/
MM52l2
f-"
,-'
FIGURE 1
f-- ,.
1--Z-1
1IJ1--2"'o
.....32/
MM5232
AOJ
CEt =0
CEl" t
A,
,-'
a,
B2
.,t-"
A,
2~
B.. ~z-6
CEt eE2:
A,
~
"f-"
8, ...... z4
A,
..
..
..
..,..
..
...
ANGLE
" r-"
.. r-'"
a, r-"
a,f-2"
A,
Be I-- 2'11
851--2"'Z
t-- r"
a, 1-'"
B..
821--2"''15
A,
8,
A,
tEl eE2
ALL
.
..
..
..
A,
...--
..
,-
A,
ro-
A,
A,
2~
A,
2~
A,
2~
.
A,
"
A,
...
CEI =0
eE2 =I
'.
"
A,
B,
..
L - - A.
2-10
A,
2-11
A,
2-12
A,
r-_
B.
" ~,.
,.1-.~3 ~Z-'0
I z _2-11
Il~Z-'Z
CD
I
C,
A,
~ .. ~Z-13
"
I3~2·'"
A,
~2
A,
B,
B,
_2"'5
I, ~Z-16
CD
*
B,~
A.
A,
.----
A,
CE. CE2
A,
C,
B,
A,
B,
. - - - A,
.,
CD
"
AEJ
-!i
ci
A,
B,
MMl232:i
MM5232
A,
."
.
'
.. r- 2
~21-2·7
A.
B,
~
::':3I-Z.e
"a,
..
..
A,
I---
I
C.
B,
B,
A.
,4
!;, ~2'"
CD
A,
A.
,.
!;2 ~2.:J
A,
,..
,.'
.
B.
B.
B,
eEl cn
2~
A,
...
AEI
A,
ANGLE
2-1
a,
A,
a,
B,
CEI" 0
CE2= 0
~31-2-2
A,
MM4232:i
MM5232
SINO
~41-2"'
B,
B,
A.
,------
..'.
DM5483/
OM74IJ
MM4232/
..f--B.t--
MM5232
AU
CEt =I
en ~ t
B,I--B,
a,
a,
CEI eE2
FIGURE J.
Note: Angles are expressed as binary fractions of a right-angle.
6·77
l>
m
'"
F,IGURE 2
(0" ft/2RADIANS)
t-- rIB
,
~
'"...,.
'"
oc(
oc(
..,j
'"
(Il • -.,
M..-,I- .
llz"f-..-
..
A,
oc(
N
-
,"-
(W)
N
It)
:E
....:E
1-
l1-
A,
~[:
.
..
B,
A,
":"
·AEI
B.
S,
A,
B,
..
B,
A,
.
(W)
N
....
1I-
~
~
-
Ao
..
..
A,
-At
::l-
Ml ,..
r'
A,
a,
A,
B,
-
A.
A,
A,
B,
A,
B,
I,
A.
S,
B,
A,
B,
A,
..
I,
;!:zl----
B,
-
I--
DM7483
l:1~
A,
CO
MM5232
AEO
.
-A.
":"
...
,-
A,
A,
..
e.
B,
..
B,
-A,
B,
B,
A,
B,
B,
t,
DII7483
I,
r-- A,
CE1CE2
",f----
I,
CO
B8
..
-Ao
-
B,,.....
.... -
- -'"
-At
-
Ll
..
A,
'--
MM5232
AEO
B.~
A,
B,
r 14
A,
B,
.-"
A,
B,
CI1CE!
FIGURE 4
Note: Angles are expressed as binary fractions of a right angle.
6-78
II- z'
t,
~
"
I, ,....
"z'
I
c•
I.
l-
I,
l-
t,
I-
DM1413
I, "-
CD
I
C•
l:.~
I,
I-
DM14b
l'2~
I, -
CO
-!.
a,
t,
CO
-A,
..
-At
0.7413
A.
..
t.
C.
B,
r - - ..
CE1CE2
_ A,
-
r----
B,
.
I-
I
B,
, . . . . - - A,
B.
1-
_
B,
Af'
.... 1-
-
.
MM5Z32
1- A.
..
A.
I,
A,
I,
Ao
1_ A,
":"
t,
CO
a,
<,
CE1CEZ
N
t,
B,
a,
A,
...
.'
z'
z'
t,
OM7413
A,
B,
MM5232
A,
"'I-
8,
B,
A.
Sill x
II.
a,
""
Ao
MM
..
..
RADIANS!
LE
."."
'""
."
~National
MOS ROMs
·~·Semiconduclor
MM4240/MM5240 2560-bit static character generator
general description
features
The MM4240/MM5240 2560·bit static character
generator is a P·channel enhancement mode
monolithic MOS inteilrated circuit utilizing a low
threshold voltage technology. Six character ad·
dress and three row address input lines provide
access to 64-8 x 5 characters. Customer·generated
single or multiple package characterfonts are easily
programmed by completing a pattern selection
form. A standard 7 x 5 raster scan font is available by
ordering the MM4240AA/MM5240AA
•
•
•
•
•
Bipolar compatibility
High speed operation-500 ns max
± 12 volt power suppl.ies
Static operation-no docks required
Multiple ROM logic application-chip enable
output control
• Standard fontsavailable-off·the·shelf delivery
applications
•
•
•
•
The MM4240/MM5240 may be used as a
512 x 5·bit read only memory for applications
other than character generation.
Character generation
Random logic synthesis
Micro·programming
Table look·up
connection diagram
...{"
ADDAESS
'00
l2
13
..
'"I'UTS
" "
.,
j
"j
"
DATA
OUTPUTS
"
"
"
Order Number MM4240J or MM5240J
See Package 11
Order Number MM5240N
See Package 18
lilillE
.INP\ITS
.
"
.
8J
"
..
'"
CIII'
fUIU
L."_ _ _ _ _J
TOPVIEft
"
typical application
+l1V
,"
LaADIMCIRCU~ATl
LOAtllRECllICULATE
COIITL~"_'_ _ _~_ _ _'~O"~~
'AGIREfMESH
MEMOR't
______ ~_~
",
",
LtNERIFRESK
MlMDII'I'
Note: For additional information refer to AN-40.
Note: For programming information se. AN·1 00.
Note: Chi" enable tied to V DO to enable.
6·79
absolute maximum ratings
VGG Supply Voltage
Voo Supply Voltage
Input Voltage
(V ss - 20)V
Storage Temperature
Operating Temperature MM4240
MM5240
Lead Temperature (Soldering, 10 sec)
electrical characteristics
(Note 1)
CONDITIONS
PARAMETER
Output Voltage Levels
MOSto MOS
Logical "1"
Logical "0"
Vss - 30V
Vss -15V
< VIN < (VSS +0.3)V
-65°C to +150°0
-55°C to +125°C
O°Cto +70°C
300°C
MIN
TYP
MAX
Vss -9.0
IMnto GND
6.8 kn to VGG Plus One
Standard Series 54174 Gate
Output Current Capability
Logical "0"
V OUT = Vss - 6.0V
+0.4
v
V
+2.5
mA
2.5
Input Voltage Levels
Logical "1"
Logical "0"
v
V
Vss - 1.0
MOS to TTL
Logical "1"
Logical "0"
UNITS
Vss -8.0
V
V
Vss - 2.0
Power Supply Current
25
100
IGG (Note 2)
Input Leakage
VIN = Vss -12V
Input Capacitance (Note 5)
VGG Capacitance (Note 5)
f = 1.0 MHz, VIN = OV
f = 1.0 MHz, VIN = OV
Address Time (Note 3)
See Timing Diagram
TA = 25°C
TACCEss
Output AND .Connection
(Note 4)
150
IlA
1
IlA
5
8
25
40
pF
pF
425
500
ns
4
MOS Load
TTL Load
10
Note 1: These specifications apply for VSS = +12V ±5%, VGG = -12V ±5%, and TA
+125'C (MM4240) TA = O'C to +70'C (MM5240) unless otherwise specified.
= _55°C
to
Note 2: The VGG supply may be clocked to 'reduce device power without affecting access time.
Note 3:. Address time is me~sured from the change of data on any input or Chip Enable line to the
output of a TTL gate. (See Timing Diagram). See curves for guaranteed limit over temperature.
Not~ 4: The address time in the TTL load configuration follows the equation:
T ACCESS = The specified limit + (N - 1) (50) ns
Where N = Number of AND connections.
The number of AND ties in the MOS load configuration can be increased at the expense of MOS "0"
level.
Note 5: Guaranteed by design.
6-80
mA
40
1
performance characteristics
·Typical Access Time (TAl ys
Supply Voltagor
G"amnteed Access Time ITAI'
VI Supply Voltagor
1000 r---.,.---r---,r--...,
1201
'.
laao
8001---1"""",
'.
]
600
···
,~"
~ 400
200
lI'c
ZS'C
200
0
10
12
11
Vss & -
13
V•• '
VDD Power Supply Current YS
Temperature
TA ·2S'C
50
50
40
~
20
10
10
13.2
12.0
Vss
,.....,
-~
TYPICAL
r--..
20
10.8
VSS ., +12.DV
VGG ;-12.0V
MA~
,
T~plcAL
30
13.2
-V•• (V)
&0
I I
40
11.0
10.8
14
v•• IV)
Power Supply Current VI
Voltage
1
12S'C
-50 -25
r- .
r- ,.....
0 25 50 75 100 125 150
TEMPERATURE ('C)
& -VGG (V)
timing diagram/address time
+UV
'.
0.
t12V
0.
+3V
1.SY
'0.,
+3.
1.5V
0.
+'V-rI
0.-1 L
D-4....-o '•."
6·81
MM4240AA/MM5240AA character font
... · .... ... ere ..............
·.·aa:
I.··. I 'I· IeI · ·•r· "....I·:•
••a...•••al··
.,. 11.··1
. :-. : t;·11···1 L··...'
I
"a .:••: ..... •1M••• •••
00
m
~
~
000000
000001
000010
000011
000100
~
~
~
000101
00II110
000111
1···1 .I. ....:: e. I.... I II ••.
: ,. :
12
001010
13
DOl 011
14
15
16
17
0011~O
001101
001110
0011n
.... ... .... ........ • II
I :1 :: •••• • 1
001000
.""
ADDRESS
OUTPUTS
81B2~s..Bs
000
um
010
011
100
101
110
111
I. :
•• ••••
• :•
I
11
001001
!...•..
.. :..iI:. ....... .:
~
~
22
~
N
010000
010001
010010
010011
010100
Ii .•
••••r·.1
I ...: -,.
25
010101
2&
010110
21
010111
.. -a:.-. ....•••: •••••• ••• ··1 ..:-.•• •
• : • ~I···
•
••••• • •
: :.
•• ••• •• •
• • • ••••• ••••
" "
"
• • • ••••
•
••:a
.::
::
i•
:.
:
:
: ::
•
•• •• • ••
..:
I :If:: ·.i••• u •••••
i
::
•
•• ••
••.,
" "
"
"
•••• •••
..... ..: ::.1. ····1 i···. ..I• i
•••• •ia. 1-.. ••••• : ••_ ••_ •••
"
••• ••• I. •• ••• ••••• ••• •••:
•..•••,. ::...
I •• :: •••• •••• I•
•• •• ••
"
"
3D
0"000
31
01'001
12
011010
100000
.
41
100001
100010
101000
101 DOl
4Z
......
1110lI0
..........
.. .....
.... .. .......
37
011100
011101
011110
011111
43
100011
44
100100
45
100101
4&
IOU 110
47
100111
•
..... ..... .- I···· .......•
60
110000
35
011011
52
101010
62
110001
.
110011t
71
72
111001
111010
101011
101100
6-82
101110
51
101111
63
..
64
65
116
61
110011
111t lDO
110101
110110
110111
76
111011
111100
77
111111
..-.
7.
FIGURE 4
Note: Negative logic assumed.
55
101101
111101
111110
~National
MOS ROMs
~ Semiconductor
MM4240ABU/MM5240ABU hoUerith character generator
general description
up a 64-character set may be accomplished as
shown in the typical appl ication.
The MM4240ABU/MM5240ABU is a 64 x 8 x 5
read-only memory programmed to display a 64character subset of the Hollerith 12-line code,
normally used in punching 80 column cards. Compression from 12 lines to the six needed to make
For electrical, environmental and mechanical details. refer to the MM4240/MM5240 data sheet.
typical application
ow
SERIAL
DATA
"IT
g
r---
D-
>>-
IIDLLERITH
CODf
...d
o--
~>-
B,
r- ..
B,
r- "
lUll;
'NO
'ABE
STORE
(SEEAIilIlD)
v~-
r-"
B,
DMl5!ID
.
t-- .,
•. 8K
r-
1--"
c,
pc.
c.
As' A4
11 = As
o = A..
•
rR~
LINE
COUNTER
g,= A3
r----
B,
I-- "
I I I
12"
'----
NlM4240AiWl
MM524GAIU
Ao
No«: Hold present gives closure to GNU.
Order Number MM4240ABU/J or MM5240ABU/J
See Package 11
Order Number MM5240ABU/N
See Package 18
6-83
-IZV
v~
---r
character font
code tabl,e
HOLLERITH
INPUT CODE
INONoCClMPRESSEDI
OCTAL
GRAPH IC
SEQUENCE DISPLAY
00
(space)
01
4
5
6
8
10
11
8
8
8
8
12
13
14
15
8
4
5
6
7
o
o
1
2
3
4
5
o
o
o
o
o
o
o
o
o
6
7
MM4240ABUIMM5240ABU
•••• •••• -I r.:•••"
·i ....
: -: ::.:. ·"1
.......
III
23
24
25
26
27
28
T
U
8
33
34
3S
8
8
36
6
7
11
11
42
4
5
6
7
11
11
8
8
8 4
11
8
8
11
8
5
6
7
6
8
7
1M
~~
115
11&
.... m
07
~
~m
~m
.·1 ····1 .:::
••....
i i.
.
r-.. e.:....
., ..:..... I.
:
13
GIl 011
010001
010010
n
010011
: :
I.
14
001100
15
001101
16
001110
M
0101110
H
"
010101
010110
II
..... I· I: ::
••
3D
011 BOO
'17
001111
31
an 001
32
011 OtD
33
011011
•• ••
34
011100
35
011101
36
011110
V
.....
••
018111
I.
•
"
011111
• • • • •••••••••
.•L· •..·1• •..··1•••••
. - .....•.
II·:
1... 11·_·
: ..... : I I I . : :
J
K
43
L
44
45
M
N
46
o
47
50
Q
51
R
4G
1011 01tO
41
100 001
m
1010110
~
R
101001
101 DID
.:::'1
•
A
62
63
64
65
66
B
C
67
G
70
H
43
100011
1M
100 tOO
45
100101
D
I
E
F
70
I
11180D
(period)
74
75
76
77
6-84
n
101011
46
108 110
H
101180
101'01
M
U
m~
m~
I :.:
81
m~
61
42
tOO 010
47
108 111
..... I···. . :--: · ) :::...i-.
i.:.! t::: 1:"1 U, .:. " •••
.••:..•• ""I... -:!.:..
..: ..........
:..-,.... ....
J..
. .... .....i ri.....r· I....•.
: :
.............
_. .·1
1-·1
] .....
52
53
54
55
56
57
73
03
~m
.....
I···. :...
_._e .....
..... Ii _::- =••:
-.- ........
.:: ,,!I.
..- •
0100110
72
8
8
12
001010
"
y
Z
71
8
n
001001
•• •••
: : .~
7
X
60
4
5
10
001000
37
40
41
D2
.... m
:
P::i i. II:.::
:--1
··11 I
.. .•: .::-••••1" i•......
V
W
32
3
8 4
J.
D1
DIXIOOt
I.... .....
:::
........:::.- .:::
21
22
11
11
11
11
11
11
1
2
16
17
20
30
31
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
02
03
04
05
06
07
m~
I
II
111U111
U
mm
"
111U1U
n
mrn
:113
111U11
56
51
101110
101111
H
n
i
14
111101
15
111 Hit
mm mm
••
1&
111110
.:..:
77
111111
.r-~~------~--~--------~--~--~----~--~-
~National
~. Semiconductor
~
MOS ROMs ,,~
~
.1:10
o
l>
til
N
MM4240ABZ/MM5240ABZ EBCDIC-8 character generator
......
~
~
(71
N
general description
.1:10
The MM4240ABZ/MM5240ABZ is a 64 x 8 x 5
read only memory that has been programmed to
display the 64 character graphic subset of EBCDIC8, an Extended Binary Coded Decimal Interchange
Code with character assignments and locations conforming to the American Standard x 3.26-1970
(see MM52300X data sheet for full EBCDIC-8
table).
six nee.ded for a 64-character subset is accomplished by simply ignoring the two most significant
EBCDIC bits, bit 0 and bit 1.
The octal character address digits are then formed
as shown below.
For electrical, environmental and mechanical details, refer to the MM4240/MM5240 data sheet.
Compression of the eight bits of EBCDIC-8 to the
character font
:.... .I···· .:........
·•.....r··.,.···.
.. ..
..
•
"
.•
···.....
• •••
• ·• •• •••
• .
• •••
•
•
•
.
.
•
.
:
·• •... .. •. ·••• ·• •••
: .
: .:.
•.
..
.. .. .... .. " .. .
··........
.. .....·...
: .. :.... ......
: :: ::...::.
•• ..
•• .••••
•
••
·:••.......:••·.:.:.....••• •••...:•: .......':'.·... ...
':1:· ••• ::•
...
•· •
·
...... ..
.,.
..
.... ....i.'.:..........
..
e... ·! .Ii:.:
..... .•'·..••
· ... · ... . . .. .
"
.". .....:
·.............' ·•• .. ...
.
...
.... .." .
·· ......
. ·"• ..: ...
.: :....
.... ..." .....:
·••••.•• ...-i·: :'"......•.....":...
,:.-!- ! r": ."
..." . ......" : .. •Li•••••: :• ·•• .••
·.....
:...: .. .. .:.:..': :
• •••••
• • ••• •••
••
•
• I••••• :
:••••••
:. : •••••••••
: ••••
01
02
03
G4
05
000(100
000001
0000111
000011
000100
DUO lOt
10
11
IHiIOtlO
001001
12
001010
1l
001011
14
001100
15
001101
06
DOD 110
•
•••
••••:
01
000111
•••••
G.
••
21
(110001
U
otD DIU
D
010011
EBCDIC BITS
17
001111
• • • • •••••••••
I : : : -.1: : I ••••
: ·1.-:
20
010000
001110
M
2~
25
27
010100
010101
DID 110
010111
J4
011100
J5
011101
36
37
011110
1}11111
44
100100
45
100101
46
100110
41
100111
•••••
56
101110
51
101111
MSB
MSD
~
234
567 LSB
'/
'./
1
2
LSD
~
OCTAL DIGITS
'
••••
3D
011000
31
011001
•
100000
41
100001
J2
33
1111010
011011
42
100010
II}II 011
43
'
50
51
101001
101000
101010
S3
101011
54
101 100
10;~ot
••••
•••••
•••
~
~
1100111
110011
1101110
~
110000
110001
:
"
~ •••
~
1101111
: I:
'
11100II
•
11
111 001
12
111010
• ..
~
110110
OUTPUTS
8,8 2 8 3 84 85
000.
•
001..
•
010 • • •
RDW 011.
• •
ADDRESS 100.
•
101.
•
110.
111
•
e
61
110111
•••••
::
',1.'
13
14
111 811
111100
•••••
15
111101
"
111116
1J
111111
Order Number MM4240ABZ/J or MM5240ABZ/J
See Package 11
Order Number MM5240ABZ/N
See Package 18
6-85
o
l>
til
.N
~·National
MOSROMs
~ Semiconductor
MM4240ACA/MM5240ACA EBCDIC character. generator
general description
The MM4240ACA/MM5240ACA is a 64 x 8 x 5
read only memory that has been programmed to
display the 64 character graphic subset of EBCDIC,
an Extended Binary Coded Decimal Interchange
.
code typically used in IBM systems.
plished by simply ignoring the two most significant
E8CDIC bits, bit zero and bit one.
The octal character address digits are then formed
as shown below.
Compression of the eight bits of EBCDIC to the
six needed for a 64-character subset is accom-
For electrical, environmental and mechanical details, refer to the MM4240/MM5240 data sheet.
character font
I
"
•• ••
:...:
• ••
• •
000000
•••••
.-.I r·····
..·•: ..··:····:····
••••·:
::•• :.. I
•....:
••
" .
"
••••; i•••: :•••• i ...
. : i.... i
...
D1
0011001
DIlDo,!1
01
03
000011
000100
000101
... ·
D00110
000111
• • • ••
•
•••
•• •• ••1•• I•••
:
I
•• • ••
• •'. •• :•
••
"
"
•• ••
• •••••••••
•• ••••
•••••••
•••••
•:• :.'
•• •••I• •::::'.11
II
•
•
••
••
••:
•
••
•••••
•
•
:
•••
:
I
:
I
I
'. I •••• I
•• •
:...: i···: ! .-1··
.::
· ...·
10
001000
20
010000
11
001001
....
21
010001
12
001010
22
0100111
001100
001101
001110
001111
23
24
25
26
27
010011
010100
010101
010110
010111
.:.
:Si: .)
_-:.-...
30
011000
3J
011011
32
011010
17
14
001011
:•••••
• : :'1'
:•
: a.
31
011001
16
34
011100
JS
011101
101000
36
011110
41
100001
42
100010
4l
100011
"I":i
••~ • • •~.
101001
101010
·53
101M1
44
100100
45
1011101
~:.:~
•
46
100110
41
100111
'::- ..:::
54·· ••:5•• •
~
~,
10l1Dfl
IDItOl
101110
101111
&4
110100
65
110101
66
110110
110111
.·1 I:::· .•.. •••:=
..
: .... ···:·i· :r":"
I ••: .:. :.... ••••• , ••••• ••• :
60
61
110000
110001
·...·.
••••• ••••
••••••• ·-1
•••
"
71
111001
i2
110010
63
110011
567 LSB
'-'"
1
2
LSD
'--/
DCTAL DIGITS.
37
011111
:••: -I ••••: ••••:
111000
234
'V'
:.···.··r·: :: :: :: :
:'i: :::::
~
MSB
MSD
II
....:•
._
..... ...•. .....
... .I i...1·:.:·1.·.1.:·:.
. . .. .
40
100000
EBCDIC BITS
~
.....
OUTPUTS
8,82838485
~~I··.I
ROW
ADDRESS
100
101
110.
•
111
61
• • f":
•• :•
••
••
n
•• .:.:.
·i·:·
••..
•
••••
••
•• • •• •
"
"
_.
72
111010
111011
74
75
111100
111101
111110
17
111111
Order Number MM4240ACA/J or MM5240AC.t\IJ
See Package 11
Order Number MM5240ACA/N
See Package 1B
6-86
~·National
~ Semiconductor
MOS ROMs
MM42411MM5241 3072-bit static read.only memory
general description
features
The MM4241/MM5241 3072-bit static read-only
memory is a P-channel enhancement mode monolithic MOS integrated circuit utilizing a low threshold voltage technology to achieve bipolar compatibility_ TRI-STATETM outputs provide wire ORed
capability without loading common data lines or
reducing system access times_ The ROM is organized in a 64 x 6 word by 8-bit memory organization_ Programmable Chip Enables (CE, and CE 2 )
provide logic control of multiple packages without
external logic. A separate output supply lead is
provided to reduce internal power dissipation in
the output stages.
• Bipolar compatibility
• Bus ORable output
TRI-STATE outputs
• Static operation
No clocks requ ired
• Multiple ROM .control
Two programmable
Chip Enable lineS
applications
•
•
•
•
Character generator
Random logic synthesis
Microprogramming
Table look-up
Dual-In-Line Package
lsa
"2
+5V. -12V
• Standard supplies
logic and connection diagrams
A,
No external
components required
103
··
" ·
,
"
EE,
....
..
r----'-I---I:t---o
LIB"
y
MEMORV
DECODE
ARRAY
0,
0,
B,
t,
v.
"t,
CE,o--------i
CE,o--------i
S
S
.".." ·•
"
LSB
"
"
"
"
zo
v"
v"
"
s,
..
..
"
" ..
I
CE,
B,
B,
" ""
""
"
"
13
"t,
Order Number MM4241J
orMM5241J
Sea Package 11
Order Number MM5241 N
See Package 18
CHIP
(liABLE
ARRAY
typical applications
FIGURE 1_ Powor Savor for
Small Memory Arrays
TTL/MOS Interfaco
...
.....
....
j
~"---'
E
r. -.'''--,
..
..
f
I
I .
f
ANYTTLIIITL
DEVitt
AIVTTlfOTL
DEVICE
FIGURE 2_ Power SaVor for
Large Memory Arrays
v,"
I
I
I
I
A
___
..J
v"
I
-: f
I
f
I
I
I .
f
L ___ ..J
ASSUME iiVu IIMIN" If:-lV II
VOG - VLt MIN = R (t6mA) INI where N '" lf9r 5.1 font .
CE,
... _ _ _..J
N=8torh8foM.
Note: Both chip enables mav be programmed·to provide any of four combinations_ Example: If CEI = 1 and CE2 = 1 outputs
(Negative Logic) would be enabled only when device pins 2 and 3 are negative (LogiC "I"). The outputs will be in the third state
when disabled. LO. L1 and L2 (device pins 11. 13 and 14) are in positive logic (1 = most positive voltage levels =Vs - 2V; 0 =
most negative voltage level = VSS - 4Vl.
Note: For programming information see AN·l00.
6-87
absolute maximum ratings
V GG Supply Voltage
V LL Supply Voltage
I riput Voltage
Storage Temperature Range
Operating Temperature Range
Vss - 20V
V ss - 20V
(V ss - 20) V < V IN < (V ss + .03)V
-65°C to + 150°C
-55°C to +125°C
MM4241
MM5241
-25°C to + 70°C
Lead Temperature (Soldering, 10 sec)
300°C
electrical characteristics
NEGATIVE LOGIC (Note 5)
T A within operating temperature range, Vss ~ +5.0V ±5%, V GG ~ V DO ~ -12V ±5%, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage Levels
Logical "1"
Logical "0"
.4
V
V
4.0
V
V
IL"" 1.6 mA sink
lL
=:
100 pA source
2.4
Input Voltage Levels
Logical "1"
Logical "0"
Vss
Vss
~
~
2.0
Power Supply Current
Iss (Note 4)
Iss (Note 41
Vss = 5, VGG::: -12, V LL ::: -12, TA = 25°C
Vss -'" 5, VGG::: -12, V LL = -3. T A = 125°C
Input Leakage
V 1N
Input Capacitance (Note 1)
j= 1.0MHz,V,,=OV
Output Capacitance (Note 1)
j = 1.0 M Hz, V IN = OV
Address Time (Note 2)
T A"" 25°C, Vss::: 5
VGG '" V LL '" -12V
TACCESS
;0;
23
37
20
5
15
pF
4
10
pF
700
900
ns
1
Vss - 10V
150
rnA
rnA
MA
20
Output AND Connections (Note 3)
Note 1: Address time is measured from the change of data on any input or Chip Enable line to the output of a TTL gate.
(See Timing Diagram.) See curves for guaranteed limit over temperature.
Note 2: Capacitances are measured periodically only.
Note 3:. The address time follows the following equation: T ACCESS = the specified limit + (N - 1) x 25 ns where N = Number
of AND connections.
Note 4: Ou,tputs open.
Note 5: All addresses and outputs are in negative true logic with the exception of La, Ll, and L2 which are in positive logic.
6·88
performance characteristics
Typical ,Access Time vs
Supply Voltage
Guaranteed Access Time vs
Supply Voltage
1400
1000
.
]: 800
VtL '" Voo
L
1200
112n
'TA < 70"C
25"C
.. 600
400
200
11.0
16.2
16.2
17.8
17.0
17.8
Vss+IVCG I (V)
Power Supply Current
Temperature
Power SupplV Current
115 Voltag;,
YS
80
1
.}
80
Vss < 5.0V
VOG:- VLL '" -12V
70
TA."'25°C
70
60
60
50
-:i 50
40
_IVI';~G'i
MAXIMUM
540
MAXIMUM
.}
30
30
TYPICAL
20
20
10
10
-so -25
0
25
50
TYPICAL
16.2
75 100 125
TEMPERATURE rCI
11.0
Vss+IVmi I (V)
timing diagram/address time
TIME
6-89
17.8
~Nattonal
MOS ROMs
~ Semiconductor
MM4242/MM5242 1024 x a-bit ROM
general description
features
These static, 8192-bit ROMs are fabricated using NChannel enhancement and depletion mode silicon gate
technology _ This provides complete DTL/TTL compatibility and single power supply operation_
•
•
•
•
•
•
•
•
Chip select inputs control the TR I-STATE® outputs and
allow for memory expansion_ The chip select code is programmed at the same time as the memory matrix and a
code of 1: 16 for the MM4242/MM5242 must be selected_
Fully decoded
Single +5V supply
All inputs and outputs directly DTL/TTL compatible
Static operation
TRI-STATE outputs for bus interface
Programmable chip selection
Maximum access time 450 ns
Pin compatible with National's 4k and 16k ROMs
applications
Military
• Microprogramming
• Control logic
• Random logic synthesis
• Table lookup
MM4242
Organization
Commercial
X
MM5242
X
connection and block diagrams
Package
1024 x 8
J
1024 x 8
N,J
logic symbol
Dual-I n-line Package
GNO
24 AD
01
23 Al
02
22 A2
03
21 A3
04
20 A4
A4
19
AS
A6
AO·
AS
MM42421 MM5242
IS
06
17
07
16
08
052
A3
AD
A7
A6
A7
AS
A9
A9
AS
10
15
11
14
12
13 CS3
A9
OS4
OSI eS2 eS3 e54
Vee
A2
Al
05
OS 1
Al
01 02 03 04 05 06 07 08
TOP VIEW
6-90
01
absolute maximum ratings
operating conditions
(Note ,)
Voltage At Any Pin
Storage Temperature Range
Power Dissipation
Lead Temperature (Soldering. 10 seconds)
Supply Voltage (V CC)
MM4242
MM5242
-{l.6V to +7 .OV
~5·C to +150··0
1.0W
300·e
MIN
MAX
UNITS
4~5
5.5
5.25
V
V
+125
+70
·e
·C
+0.65
V
Vee
V
4.75
Ambient Temperature (TA)
MM4242
MM5242
Logical "0" Input Voltage (Low)
-55
0
-{l.S
Logical "1'" Input Voltage (High)
2.0
dc electrical characteristics (Note 2)
PARAMETER
MM424~
CONDITIONS
MIN
TYP
MM5242
MAX
MIN
TYP
MAX
UNITS
VIH
Logic "1" Input Voltage
2.0
VCC
2.0
VCC
V
VIL
Logic "0" Input Voltage
-
1111111 j
I Space
,Il-),>
_ _ _ _ _+_Not84
L_----.:======j--l
Note 1: The code is a 7-bit ASCII code on 8 punch tape.
Note 2: The ROM input address is expressed in deCimal form and,is preceded by the
letter A.
Note 3: The total number of "1"bits in the output word.
Note 4: The total number of "1" bits in each output column or bit position.
Note 5: Specify product'type.
Note 6: Must type POSlogic, or NEG logic depending on which is used. Logic on
addresses and outputs must be the'same (either POS or NEG),
Note' 7: Specify the pattern necessary to select the ROM
Space
6-92
card entry format
-,
12:!45S789101l12Ig'415t61718192021222J24252627282930313233343S3I>3738394(1414243'144546474849&05152/135455565158596061828364656&6768$707112737415761118'19110
MM42XX
~~~:..:.:=..:.:..~.~..~;;~~===~~.r.~':=.=.:~:~.==.=,.=,=.,=.-,--f~N_~'_==~_~-~~~~_-_-__-____-===========================================~
AG004
00111 III
1--:-'--'-+:'
,......:;:."-'----------------------------------------.-~----------------------------------------------1
E---=--t--:-----~-:----"------------- -----~---------:-----___l
1 - - : - - - - - - - - - - - - - - - - -------------------------------1
12341SS1891011121314fSI61118 19202122232425262728293031323334'3536313839404142434<145464748495051 52~3S4 5556516859110 61626364$!;666769697071127)7416:76n1879a:1
./
Note 1: Specify product type;
Note 2: Must type POS logic or NEG logic depending on which is used. Logic on addresses. outputs and chip selects must be the
same (either POS 'or NEGI.
Note 3: Sp";'ify the chip select logic levels that will enable the ROM.
Note 4: The first ROM input address per card is expressed in 'decimal form and is preceded by the letter A.
Not.5: Punch four address locations per card. only first location on each<;ard has the address location expressed in decimal form.
Note 6: The total number of "1" bits in all four addresses.
Note 7: Leading zeros must be punched.
Note 8: The total number of
bits in each output colu~n or bit position.
u'"
6·93
~National
MOS ROMs
~ Semiconductor
MM4246/MM5246 2048 x 8-bit ROM
MM4247/MMS247 4096 x 4-bit ROM
general description
features
These static, 16,384-bit ROMs are fabricated using
N-channel enhancement and depletion-mode silicon-gate
technology. This provides complete DTL(TTL compatibility and single power supply operation.
•
•
•
•
•
•
•
•
Chip select inputs control the TRI-STATE® outputs and
allow for memory expansion. The chip select code is
programmed at the same time as the memory matrix and
a code of 1:8 for the MM4246/MM5246 and 1 :4 for the
MM4247/MM5247 must be selected.
Fully decoded
Single +5V supply
All inputs and outputs directly DTL/TTL compatible
Static operation
TR I-STATE outputs for bus interface
Programmable chip selection
Maximum access time 450 ns (MM5246. MM5247)
Pin compatible with NatKmal 4k and 8k ROMs
applications
•
•
•
•
Military
MM4246
Microprogramming
Control logic
Random logic synthesis
Table lookup
Commercial
Organization
X
X
MM5246
MM4247
X
X
MM5247
Package
2048 x 8
J
2048 x 8
4096x4
J
4096x4
N.J
N.J
logic symbols
block and connection diagrams
MM4247/MM5247
MM4246/MM5246
AD Al AZ AJ All
MM4246/MM5246
AD
AI
01
.2
A2
A4
AO
A5
AS
A5
A3
AO
••
Al
Al
A'
AO
A'
A.
AI.
AlO
CSO
Cst
Cs>
01 02 03 04 05 06 01 01
A.
A.
CSI
C"
.,
.2
03
AD
20
0.0
AD
01
.,
23 Al
O.
22 A2
NC
22 AZ
03
21 AJ
.2
21 AJ
Al
DO
lD A4
NC
ZD A4
.,
19 AS
.3
19
O.
cso
CSI
Vee
"
.,
A4
A5
A5
lB AI
A'
Al
MM424U"""5247
18 AU
MM4247/MM5247
AD
At
MM4246/MMi248
.,
08
.0
23 At _
O.
.5
Dual-In-Line Package
20
.5
.,••
A.
Al
Dual-In-Line Package
0 ••
.3
.0
AS
Ne
Al
.0
" Al
,.
16 AI
Ne
16 AI
15 AI
cso
11
14 AID
eSl
12
13 tSZ
Vee 12
10
15 A9
11
14 AID
13 A11
TOP VIEW
TOP VIEW
6-94
02
03
A.
A'
AlO
All
.0
eso
eSl
absolute maximum ratings
operating conditions
(Note 1)
~.5V
Power 0 issipation
Lead Temperature (Soldering, 10 seconds)
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
-55
0
+125
+70
°e
°c
Logical "0" Input Voltage (Low)
-{l.S
+0.65
V
Logical "I" Input Voltage (High)
2.0
Vee
v
Supply Voltage (Vee!
MM4246, MM4247
MM5246. MM5247
to +7 .OV
-15 to 2.4V,
Chip Disabled
VOH
Output Voltage High
IOH=-2mA
-20
--45
-70
-45
±50
2.4
-70
rnA
±50
IJA
3.2
IOH =-6.5mA
ac electrical characteristics
-20
2.4
V
V
3.2
(With standard load)
i
PARAMETER
DM545271,54S371
DM745271,745371
5V ±10%;-55°eto'+I25°C 5V ±5%;Ooe to +70o e
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tAA
Address Access Time
37
75
37
60
ns
tEA
Enable Access Time
18
40
18
30
ns
tER
Enable Recovery Time
18
40
18
30
ns
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device
may be operated at these values.
Note 2: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vec = 5V and TA = 25°C.
Note 3: Ouring ISC measurement. only one output at a time should be grounded. Permanent damage may otherwise resUlt.
7·16
c
'?A N~tional
Bipola"rROMs at~
"
~ semiconductor
f/)
N
CD
......
C
~
OM75S29/0M85$29 open-collector 8192~bit ROM
OM75S28/0M85S28 TRI-STATE® 8192-bit ROM
00
C1I
f/)
N
CD
general description
features
These Schottky ROM memories are organized in the
popular .1024 words by 8 bits configuration. Four
memory enable inputs are provided to control the out·
put states. When E1 and E2 are 10VII and E3 and E4 are
high, the output presents the contents of tlie selected
word.
• Schottky-clamped for high speed
Address access-70 ns max
Enable access-45 ns max
• PNP inputs reduce input loading
• All dc and ac parameters guaranteed over temperature
• PROM mates are DM87S229 and DM87S228
C
f/)
N
(X)
Open-
Collector
X
X
DM85S28
DM75S28
TRI-STATE
Package
X
N, J
X
N,J
X
X
X
DM75S29
J
X
block diagram
J
connection diagram
. v"
Dual-ln·Line Package
A7
23 AI
A'
"
..
At
128XJ4.BIT
.
" n
.,
.,t2·8ITARRAV
. ~f;MORV MA1RIX
"n
A2
11 E3
AI
11 E4
11 D.
AI" •
1. 01
Dt
"n
n
•
02 11
15 0&
03' 11
14 05
ala II
.."
t3 04
TOPVlfW
•0
•7
.
••
D4
D3
..
.,
logic" symbol
DI
The device is enabled when:
C
00
U'I
Commercial
DM85S29
N"
00
......
:s::
If E1 or E2 are high, or E3 or E4 are low, it causes ail
8 outputs to go to the "OFF" or high impedance state.
The memories are available in both open-collector and
TR I-STATE versions and are available as PROM's as
well as ROM's.
"
Military
~
U'I
f/)
••
IT • E2 • E3 • E4
...
03
•0
.7
••
nnElU
7-17
absolute max.imum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage TemperatUre
Lead Temperature (Soldering, 10 seconds)
operating conditions
(Note 1)
-o.5Vto +7V
-1.2V to +5.5V
-o.5V to +5.5V
-6S"C to+I50°C
300°C
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
--55
0
+125
+70
°c
°c
Logical "0" Input Voltage (Low)
0
0.8
V
logical "1" Input Voltage (High)
2.0 .
5.5
V
Supply Voltage Ncd
DM7.5S29, DM75S28
DM85S29,DM85S28
Ambient Temperature (TA)
DM75S29, DM75S28
DM85S29,DM85S28
.
G)
N
tn
dc electrical characteristics
(Note 2)
It)
00
DM75S29, 75S28
~
DM85S29, 85S28
CONDITIONS
PARAMETER
UNITS
o
......
IlL
Input Load Current, All Inputs.
VCC = Max, VIN = 0.45V
N
IIH
Input Leakage Current, All (nputs
VCC", Max, VIN
= 2.7V
25
25
p.A
II
Input Leakage Current, All Inputs
VCC = Max,VIN' = 5.5V
1.0
1.0
mA
Vee = Min, IOL = 16 mA
G)
tn
,...
It)
~
o
MIN
VOL
Low Level Output Voltage
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
ICEX
Output Leakage Current
Vc
Input Clamp Voltage
CIN
Input CapaCitance
VCC = 5V, VIN = 2V, TA = 25°C,
Co
Output Capacitance
VCC = 5V, Vo = 2V, TA.= 25°C,
(Open-Collector Only)
TVP
-80
0.35
MAX
MIN
-250
0.5
TVP
MAX
-89
-250
0.35
0.80
2.0
V
V
SO'
p.A
100
p.A
V
50
100
VCC = Max, VCEX = 5.5V
--0.8
VCC = Min, liN = -18 mA
0.5
0.80
2.0
'VCC = Max, VCEX = 2.4V
-1.2
!LA
--0.8
-1.2
V
4.0
4.0
pF
6.0
6.0
pF
1 MHz
1 MHz, Output "OFF"
ICC
Power Supply Current
VCC = Max, All Inputs Grounded,
·140
170
140
170
mA
-100
mA
±50
p.A
All Outputs Open
TRI-STATE PARAMETERS
ISC
Output Short Circuit Current
1HZ
Output Leakage (TRI-STATE)
Vo = OV, VCC.= Max, (Note 3),
VCC = Max, Vo
-30
--60
= 0.45 to 2.4V,
-100
-30
--60
±50
Chip Disabled
VOH
Output Voltage High
IOH =-2 rnA
2.4
.3.2
V
IOH =-6.5 rnA
ac electrical characteristics
2.4
(With standard load)
.
,
V
,
DM75S29, 75S28
PARAMETER
3.2
DM85S29, 85S28
5V ±10%;-55°Cto+125°C 5V ±5%;0°C to +70°C
CONDITIONS
MIN
TVP
MAX
MIN
TVP
UNITS
MAX
tAA
Address Access Time
47
.90
47
70
ns
tEA
Enable Access Time
30
50
30
45
ns
tER
Enable Recovery Time
30
50
30
45
ns
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently demaged. They do not mean that the device.
.
may be operated at these values.
Note 2: These limits apply over the entire operating range unless stated otherwise. All typical values are for VCC = 5V and TA = 25"C.
Note 3: DU~fng ISC measurement. only one output at a time should be grounded. Permanent damage may otherwise result.
7-18
c
Bipolar ROMs
~National
~ Semiconductor,
3:
.....
CJI
.....
CJI
.....
c
3:
DM7575/DM8575, DM7576/DM8576
programmable logic array (PLA)
CO
CJI
.....
CJI
general description
The DM7575/DM8575 and DM7576/DM8576 are
mask-programmable logic arrays designed for uSe
in applications where random logic is required. The
devices have fourteen data inputs and eight outputs. Each output provides a sum of product terms
where each product term can contain any combination of 14 variables or their complements. The
total number of product terms which can be provided Is 96. Any product term which is repeated
is counted only once. Since some functions are
more easily represented in their inverted form, an
option is provided to allow for either the true or
complement of the function on each output. The
products are particularly useful in providing control logic for digital systems. The DM7575!
DM8575 has a conventional totem-pole output
whereas the DM7576/DM8576 is provided with
a passive pullup output. This latter configuration
is useful in expanding functions by connection of
outputs of different packages.
.....
c
features
CO
ell
•
3:
.....
0)
A 2 14_by·8 (128k) bit memory would be needed
to provide equivalent function
90 ns
• Typical delay
550mW
• Typical power dissipation
• Series 54/74 compatible
logic and connection diagrams
Dual·. n-line P~ckage
,~
""
J.."
IMPI,I1"S
19 ~J
DAHl
It.rPUTS
.Of.
'"
'
.
" '.
lS f ,
'"
1~ F,
'" '"
,qf,
GNO'2
L-_ _ _----'
""
Order Number DM7575J, DM8575J,
DM7576J or DM8576J
See Package 11
Order Number DM8575N or DM8576N
See Package 18
7-19
c
3:
.....
CJI
.....
0)
CD
r0-
an
co
~
C
......
CD
roan
ro-
absolute maximum ratings (Note 1)
operating conditions
MIN
Supply Voltage
I nput Vol tage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
7.0V
5.5V
--65°e to +150o e
300°C
Supply Voltage (Vee)
DM7575. DM7576
DM8575. DM8576
Temperature (TA)
DM7575. DM7576
DM8575.• DM8576
~
C
an
an
r0-
electrical cha racteristics
4.5
4.75
--55
0
MAX
5.5
5.25
+125
70
UNITS
V
V
°e
°e
(Note 2)
CO
~
C
......
an
roan
ro:E
C
PARAMETER
CONDITIONS
Vee'" Min
Logical "0" Input Voltage
Vee'" Min
Logical "',. Output Voltage
(DM7575/DM85750nlyl
V
Logical "1" Output Current
(DM7576/DM85760nlyl
Vee = Max, V OUT = 5.5V
Logical "0" Output Voltage
Vee -= Min, YIN(1)
Logical "1" Input Current
_
VIN = 2.4V
Vee - Max, VIN "" 5.5V
fl.'r
TYP
V 1N (1l
-=
2V, V1N(O) ::
O.BV
In, lOUT'" -800.uA
Vee = Max, VIN
DM7575!76
DM8575/76
Supply Current
Inpul Diode Clamp Voltage
Propagation Delay to a Logical "0" from Data
Inputs to Outputs, tpdQ
Propagation Delay to a Logical "1" from Data
Inputs to Outputs, tpdl
=
2.4
100
0.4
40
1
-1.0
-20/-1.75
-18/~1.65
TA
5.0V· C -50 F R -400n
Lp, L -
= 25°C
Vee = 5.0V
TA =2 SoC
~A
V
jJ.A
rnA
rnA
-55/-3.5
--55/-3.3
rnA
170
mA
-1.5
V
100
150
ns
80
150
ns
110
Vec=Min, I =-12 A
=,25°C IN
m
TA
o
V
V
O.4V
Vee = Max
UNITS
V
=
Vee =.Max, V OUT = OV
V cc
MAX
0.8
2V. VIN{c) = O.BV
lOUT = +12 mA
Logical "0" Input Current
Output Short Circuit Current
(Note 31
""
, cc -
MIN
2
Logical "1" Input Voltage
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at ,these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply acros!) 'the -5SoC to'+12SoC temperature range for the DM7575/76
and across the oOe to 70°C range for the DM8575176. All typicals are given for Vee
Note 3: Only one output at a time should be shorted.
7·20
= 5.0V and T A = 25°C.
information needed to program the PLA
Information to program the PLA can be supplied
Col. 35,39: (Blank I
in one of two formats:
Col. 40-75: This space is reserved for any unique
letter/number desired by the customer (special
part number, program number, etc.1 However the
exact combination of characters must appear on
all cards, but only those cards, associated with that
particular deVice. The purpose of this section is to
1. Punched 80·column cards
2. The applicable section of this data sheet (manual
entry of informationl.
punched cards
prevent mixing of cards.
CARD 1: (Used to determine whether outputs are
presented in their true or inverted form. If this
card is not used it is assumed that all eight outputs
are true.1
Col. 76,78: (Blankl
Col. 79-80: Product Term Number 0,1 to 96. (All
96 cards need not be used.1 Zero in column 79 may
be suppressed.
Col. 1,6: DM7575 or DM8575 or DM7576 or
DM8576.
Col. 7,9: (Blankl
manual entry
The matrix,blank shown in this data sheet can be
used in lieu of punched cards to submit information
for programming the PLA.
Col. 10,17: Output Data, Outputs are Fa (most
significantl to F, (least significantl. All eight
outputs must be specified.
A 'T' in an output location indicates that the
Olltput is true.
A 'C' in an output location indicates that the
output is complemented (invertedl.
Col. 18-39: (Blankl
INSTRUCTIONS
1. Circle the appropriate part,number. In the event
a catalog part is not being purchased, circle the
closest catalog part .number. If an electrical
screen is required between the ·military and
commerical devices, the military designation
should be circled.
Col. 40-75: This space is ".served for any unique
letters/numbers desired by the customer (special
part number, program number, etc.l. However the
ex'act combination of characters must appear on
all cards, but only those cards. associated with that
.particular device.
Col. 76,78: (Blank I
Col. 79,80: 00
2. Customer should write the name of his company.
3. Enter the total number of unique product terms
found in all eight outputs. Repeated terms
count only once.
4. Output Inverter Option. Under the appropriate
output designation specify a 'r when the high
(truel level is desired on the output for the
gi.ven input conditions. Specify a 'C' if the
complement is needed.
CARDS 2,97: Term Data Cards. Used to specify the
i,nput and output conditions.
Col. 1,6: DM7575 or DM8575 or DM7576 or
DM8576:
Col. 7,9: (Blankl
Col. 10-17: Output Connections. Outputs are Fa
(most significantl to F, (least significantl. This
field describes the outputs on wh ich ,the product
term appears.
5. Matrix
a. Input data. This block is used to describe
what comprises each of the 96 (maximum)
product terms. lri each row, opposite the'
app,,:ipriate Product Term number, information on the fourteen Input Data locations is
entered. Information must be entered on all
14 inputs.
A '+' in one of the eight output locations indicates that the term described by the card is one
of the "OR" terms in that output.
A '(blank I' in one of the eight output locations
ipdicates that the term described by the card
is not one of the "OR" terms in that output.
(Care should be exercised in punching this particular field; since in most cases, unless a product term
is repeated, this field will appear as one '+' and
seven blanks. I
Col. 18: (Blank)
Col. 19: = (equal sign)
an "H" under the appropriate
input designation if that particular input
appears in the product term as a high
(true I level.
1). Enter
2). Enter an "L" under the appropriate in-
put designation if that particular input
appears in the product term a,. a low
(complemented) level.
3). Enter an "X" u... der the appropriate input
designation if that particular input does
not appear in the product term.
If less than 96 product terms are used leave
all spaces for the unused terms blank.
Col. 20: (Blank)
Col. 21,34: Input DatM8S7'AAA I 'DM757'AAA" 2)M8501,AAA
2. CUSTOMER IDENTIFICATION-
SrANDAaO "iiJ'TTERIIJ - f..Icx.lJ£e/7U
3. TOTAL NO. OF UNIQUE PRODUCT TERMS USED -
(Repeated Terms Count Only Once)
lq (XP.lHJ To Asel I
b
q
4. OUTPUT INVERTER OPTION
5. MATRIX
7·24
~------------------------------------------------IC
~.....
truth table/order blank (con't)
U'I
"C
s:co
U'I
C;f
C
s:.....
~
0)
"C
s:co
U'I
.....
0)
7-25
~National
Bipolar ROMs
DSemiconductor
DM7597/DM8597 TRI-STATE®1024-bit read only memory
general description
The DM7597/DM8597 is a custom-programmed
read-only memory organized as 256 four-bit words_
Selection of the proper word is accomplished
through the eight select inputs_ Two overriding
memory enable inputs are provided, which whl!n
mask-programmed in one' of three options described will cause all four outputs to either read
the normal memory contents or go to the "h igh
impedance" state_ In this state both the upper and
lower output transistors are turned off_ The outputs may therefore be paralleled to increase word
capacity; since in the high-impedance state they
present only a minimal load to the active output_
features
• Pin compatible with SN54187/SN74187
• 35 ns typ ical del ay from address to output
• Can be expanded to 32,768 4-bit words by
simple paralleling of outputs
• Programmable memory enable inputs
logic diagram
BINARY
SELECT
III
MEMoRY
ENAILE
{"',~I~i===:l::)--~4.;----~~------J.t,iU---.J
ME
31
21,4)
:;~
·IIPIlOIiIZ
truth table
connection diagram
Dual-In-Line Package
TABLE of Programmable Memory Enable Options
,
OPTION
ME'
ME2
, ,
, ,
, ,
0
0
X
X
2
0
X
3
X
0
x
TOP VIEW
Order Number DM7597J or DM8597J
See Package 10
Order Number DM8597N
See Package 15
7-26
='
don't care
OUTPUTS
Normal
HIGH Impedance
HIGH Impedance
Normal
X
HIGH Impedance
0
HIGH
0
Normal
X
Impeda~e
HIGH Impedance
HIGH Impedance
absolute maximum ratings
(Note 1)
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM7597
DM8597
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
7V
5.5V
5.5V
_55°C to +125°C
O°C to +70°C
_65°C to +150°C
300°C
,
electrical characteristics (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logical "1" Input Voltage
DM7597
DM8597
Vee = 4.5V
Vee =4.75V
Logical "0" Input Voltage
DM7597
DM8597
Vee =4.5V
Vee - 4.75V
Logical ''1'' Output Voltage
DM7597
DM8597
Vee = ".5V
Vee = 4.75V
10 = -2mA
10 = -5.2 rnA
Logical "0" Output Voltage
DM7597
DM8597
Vee = 4.5V
Vee = 4.75V
10 = 16mA
Third State Output Current
DM7597
DM8597
Vee = 5.SV
Vee 5.25V
Vo = 2.4V
Vo = O.4V
40
-40
/lA
/lA
logical "1" Input Current
DM7597
DM8597
Vee = 5.5V
Vee - 5.2SV
VIN = 2.4V
40
/lA
DM7597
DM8597
,Vee = 5.5V
Vee - 5·2SV
V'N = 5.5V
1.0
rnA
DM7597
DM8597
Vee = 5.5V
Vee = S.25V
,V'N = 0.4V
-1.0
rnA
DM7597
DM8597
Vee = 5.5V
Vee - 5.25V
Vo = O.OV
DM7597
DM8597
Vee = 5.5V
Vee = 5.25V
All Inputs at GND
DM7597
DM8597
Vee = 4.5V
Vee - 4.75V
liN
Logical "0" Input Current
: Outpu't Short Circuit Current
(Note 3)
Supply Current
V
2.0
0.8
2.4
V
V
0.4
-20
75
= -12 rnA
V
-70
rnA
110
rnA
.,1.5
V
39
60
ns
Vee = 5.0V
TA = 25'e
31
60
ns
Delay from Enable to High Impedance
State ,(from Logical"1" Level). t1H
Vee = 5.0V
TA = 25'e'
,13
30
ns
Delay from Enable to H'igh'lmpedance
Vee = 5.0V
TA = 2S'e
16
30
ns
Delay from Enable to Logical "1" Level
(from High Impedance State), tH1
Vee = 5.0V
TA = 25'e
18
30
ns
Delay from Enable to LOgical "0" Level
(from High Impedance State), tHO
Vee = 5.0V
TA = 25'e
20
30
nS
Input Cla'm'p Voltage
Propagation Delay to a Logical "0" from
Address to Output, ~dO
Vee = 5.DV
TA=25'e
Propagation Delay to a Logical"'" from
Address to Output. Ipd1
State {from logical ItO" Levell.
tOH
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for, "Operating Temperature Range" they are not meant to imply that the
devices should be op,erated at these limits. The table of "Electrical Characteristics" provides cond!tions
for actual device operation.
Note 2: Unless btherwise specified minImax limits apply across 'the ·_55°c' to +125°C temperature
range for the DM7597 and across the DoC to 70'e range for the DM8597. All typieals are given for
Vee = 5.0V and TA = 25°e.
Note 3: Only one output at a time should be shorted.
7-27
...
ordering instructions
Programming instructions for the DM7597 or
DM8597 are solicited in the form of a sequenced
deck of 32 standard 80-column data cards providing the information requested under data card
format, accompanied by a properly sequenced
listing of these cards, and the supplementary
ordering data. Upon receipt of these items, a computer run will be made from the deck of cards
which will produce a complete truth table of the
requested part. This truth table, showing output
conditions for each of the 256 words; will be
forwarded to the purchaser as verification of the
input data as interpreted by the computer-automated design (CAD) program. This single run also
generates mask and test program data; therefore,
verification of the truth table should be completed
promptly.
·10-13
14
15-18
19
20·23
24
25-28
29
E.ac,", card in the data deck prepared by the purchaser identifies the eight words specified and
describes the conditions at the four outputs for
each of the eight words. All addresses must have
all outputs defined and columns designated as
"blank" must not be punched. Cards should be
punched according to the data card format shown.
30-33
34
35-38
39
4043
supplementary ordering data
44
4548
Submit the following information with the data
cards:
49
a) Customer's name and addreSs
b) Customer's purchase order number
c) Customer's drawing number.
50-51
52
53-55
data card format
56
Column
1- 3
4
5- 7
8- 9
57-58
Punch "H", "L", or "X" for bits four,
three, two, and one (outputs Y4, Y3, Y2,
and Yl in that order) for the first set of
outputs specified on the card. H = high·
level output, L = low·level output, X =
output irrelevant.
Blank
Punch "H", "L", or "X" for the second
set of outputs.
Blank
Punch "H'i, '''L'', or "X" for the third set
of outputs.
Blank·
Punch "H", "L", or "X" for the fourth set
of outputs.
Blank
Punch "H", "L", or "X" for the fifth set
of outputs.
Blank
Punch "H", "L", or "X" for the sixth set
of outputs.
Blank
Punch "H", "L", or "X" for the seventh
set of outputs.
Blank
Punch "H", "L", or "X" for the eighth
.
set of outputs.
Blank
Punch a right-justified integer representing
the current calendar day of the month.
Blank
Punch an alphabetic abbreviation repre·
senting the current month.
Blank
Punch the last two digits of the current
year.
Punch a right-justified integer representing
the binary input address (000-248) for
the first set of outputs described on the
card.
60-61
Punch a "-" (Minus sign)
62·65
Punch a right-justified integer representing
the binary input address (007·255) for
the last set of outputs described on the
card.
66-70
Blank
71
Punch 1, 2, or 3 for memory enable
option desired (assumed 1 if not punched).
59
Blank
7-28
Blank
. Punch "OM"
Punch 7597 or 8597
c
~National
Bipolar ROMs
~ Semiconductor
3:
~
CD.
00
"-
c
3:
00
OM7598/0M8598 TRI-STATE®256-bit read only memory
C7I
.CD
00
general description
The DM7598/DM8598 is a customer programmed
256-bit read only memory, organized as 32 8-bit words.
A 5-bit input code selects the appropriate word which
then appears on the eight outputs. An enable input
overrides the select inputs and blanks all outputs.
speed would be achieved. The low output impedance of
the DM7598/DM8598 provides good capacitance drive
capability and rapid transition from the logical "0" to
logical "1" level thus assurin9 both speed and waveform
integrity.
Although the DM7598/DM8598 can have its outputs
tied together for word-expansion, the outputs are not
open·collector, but rather the familiar totem·pole output
with the capability of being placed in a "third·state."
This unique TRI·STATE concept allows outputs to be
tied together and then connected to a common bus line.
Normal TTL outputs cannot be connected due to the
low·impedance logical "1" output current which one
device would have to sink from the other. If, however,
on all but one of the connected devices both the upper
and lower output transistors are turned "OFF," then the
one remaining device in the normal low impedance state
will have to supply to or sink from the other devices
only a small amount of leakage current. This is exactly
what occurs on the DM7598/DM8598.
It is possible to connect as many as 128 DM8598s to a
common bus line and still have adequate drive capability
to allow fan·out from the bus. The example shown in
Figure 2 indicates how this guarantee can be made under
worst-case conditions.
Figure 3 indicates how multiple packages can be used to
increase word length.
features
•
•
•
•
•
•
•
A typical system connection demonstrating expansion to
greater numbers of words is shown in Figure 1. While it
is true that in a TTL system open·collector gates could
be used to perform the logic function of these three·
state elements, neither waveform integrity nor optimum
Pin compatible with SN5488/SN7488
Organized as 32 8·bit words
Full internal decoding
26 ns typical access time
350 mW typical power dissipation
Input clamp diodes
Designed for bus-organized systems
logic and connection diagrams
Dual-ln~Line
{lID ......
Y>-
(111
I"
Package
V
BINARY
SElECT
C
(12,
(IJI
I"...
"
(14)
.E
(15)
I"v
L,;
"...
I
OUTPUTS
{il
PROGRAMMING
NOT
SHOWN
va
(7J
'1J
(6)
'16
~t51
v&
(41
'14
OUTPUTS'
(3)
Y3
f1
(2)
'12
TOPVIEW
VI
Order Number OM1598J or PM8598.1
S~e
Package 10
Order Number DM8598N
See Package 15
7·29
00
0')
It)
absolute maximum ratings
operating conditions
(Note 1)
00
:!:
c
00
Operating Temperature Range
.......
0')
DM7598
DM8598
It)
r..
:!:
c
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
Temperature, T A
DM7598
DM8598
-·55°C to +125"C
aOc to +70°C
-55°C to +150°C
300°C
CONDITIONS
VIH
Logical "1" Input Voltage
Vee::: Mm
VIL
Logical "0" Input Voltage
Vee::: Min
VOH
Logical" 1" Output Voltage
Vee
VOL
Logical "0" Output Voltage
loz
TRI·STATE Output Current
= Min
10 ~ -2 mA, DM7598
204
10= -5.2 mAo DM8598
2.4
Vee:::: Max
TYP
MAX
Vee = Max
V
V
-40
V
I1A
V ,N = 2.4V
25
I1A
V ,N = 5.5V
1
mA
= Max, V ,N
Supply Current
Vee
VIC
Input Clamp Voltage
Vee = Min, liN = -12 mA
switching characteristics
UNITS
V
Va = O.4V
ICC
tLZ
°c
°c
40
Vee
1HZ
+125
+70
0.4
Vee = Max, Vo = OV, (Note 3)
tZL
V
V
Va = 2.4V
Logical "0" I nput Current
tZH
5.5
5.25
0.8
Output Short Circuit Current
IpHL
4.5
4.75
2.0
IlL
tPLH
UNITS
Vee = Min, 10 = 12 mA
Logical" 1" I nput Current
PARAMETER
MAX
-55
0
MIN
los
SYMBOL
MIN
(Note 2)
PARAMETER
SYMBOL
IIH
Supply Voltage, VCC
DM7598
DM8598
7V
5.5V
5.5V
Supply Voltage
Input Voltage
Output Voltage
= OAV
20
= Max, Inputs Grounded
-1.0
mA
-70
mA
99
mA
-1.5
V
70
(Note 2)
PARAMETER
CONDITIONS
TEST
CONDITIONS
Propagation Delay Time,
Access Time from
Low to High Level Output
Address
Propagation Delay Time,
Access Time from
High to Low Level Output
Address
C L =50pF,
Output Enable Time to
Access Times from
RL = 400n
High Level
Memory Enable
Output Enable Time to
Access Times f.rom
Low Level
Memory Enable
Output Disable Time from
Disable Times from
High Level
Memory Enable
C L = 5.0 pF,
OUlput Disable Time from
Disable Times from
RL = 400n
Low Level
Memory Enable
DM8598
DM7598
UNITS
MIN
TYP
MAX
23
MIN
TYP
MAX
65
23
50
ns
29
65
29
50
ns
16
40
16
30
ns
20
40
20
30
ns
10
30
10
~O
ns
22
45
22
40
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device can-not be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the ·-5SoC to +125°C temperature range for the DM7598 and across the oOe to
+70°C range for the DMB598. All typicals are given for VCC = 5.0V, and TA = 25°C.
Note 3: Only one output at a time should be shorted.
7·30
c
:;:
typical applications
.....
U'I
CD
00
.......
C
:;:
00
.us [
j'"
UTPUTS
OFO THER
MEM DRIES
LINE.
r
II
VI
V2
'1'3
'1'4
'1'5
'1'6
Y7
II
VI
VB
r--<
OM759S/DM8598
ME
A
B
C
0
,
V2
YJ
'1'4
Y5
'1'6
V7
'1'8
DM7598/DM8598
ME
A
•
C '0
f
I
INARY
} SUE
TO. &T INPUTS
OFO TilER
M'. DRIES
TO ENABLE INPUTS OF OTHER MEMORIES
1
0
'1 11
•
2
3
4
5
•
7
DM54154/DM741S4
A
I
A
8
C
0
E
F
I
C
0
10
11
12
.,
.2
ENABLE
lOW
! tl'
13
14
15
'/
III
H
•
9
J
BINARY SElECT REGISTEh
FIGURE 1. Expansion tQ Larger Word CaPacity
16-8ITWDRD
O.120mA
DM759B/DM8S9Ss
GATED INTO
lOW IMPEDANCE
LOGICAL "1"
STATE
ME
GATED INTO
HIGH IMPEDANCE
DM759B1DM~598
OM7598/DM8598
ABC
0
E
ABC
0
E
40j.lA l( 127 '" S.De mA
STATE
GATED INTO
HIGH IMPEDANCE
STATE
OTHER DM1598/0M8598
BUS LINE
ENABLE
OUTPUTS
BINARY SELECT
REGISTER
FIGURE 2.
FIGURE 3.
7-31
U'I
CD
00
00
en
It)
truth table/order blank
00
~
A special pattern has been generated for the DM7598/DM8598. The AA pattern provides a sine table. The 5·bit input code linearly divides
90° into 32 equal segm~nts. Eaoh 8~bit output is therefore the sine of the angle applied.
00
EXAMPLE: Input 11010 means 26/32 of 90°, or about 73°. The corresponding output 1110100 indicates (1/2 + 114 + 1/8 + 1/16 +
1/64) or about 0.95, which is close to the sine of 73°. Rounding~off has not been employed, since without rounding-off it is possible to
extend toe accuracy with additional ROMs.
c
.......
en
It)
,...
OUTPUTS
INPUTS
~
WORD
c
C
B
A
ME
V,
Y7
V.
V5
V,
V3
V2
Y>
0
0
0
0
0
0
0
0
0
0
0
I
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
I
0
0
0
0
0
I
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
a
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
I
0
0
0
15
16
1
n
1
18
1
19
1
20
1
21
I
1
2
,
•,
,
3
5
9
10
11
12
13
14
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ENABLE
81NARY SELECT
E
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
0
0
1
1
0
Q
1
1
1
0
0
0
0
0
0
0
0
a
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
I
1
I
0
0
0
1
1
1
1
0
1
1
1
1
1
I
0
0
I
1
1
1
1
1
0
0
0
0
0
0
I
1
0
0
0
0
0
1
1
I
a
1
Q
0
I
1
1
1
1
1
1
I
1
1
0
1
1
1
1
1
1
1
1
Q
1
0
0
0
1
1
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
I
I
1
1
0
1
1
1
1
0
0
I
1
1
1
1
0
0
0
1
1
1
0
I
0
0
1
1
0
0
0
0
0
1
1
1
1
0
1
1
1
0
1
1
I
0
1
1
1
0
1
1
1
0
·0
0
1
1
1
0
0
0
0
0
1
I
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
22
1
"
I
0
0
0
0
24
1
1
1
I
1
I
1
1
1
1
1
0
0
0
0
0
0
0
0
X
X
X
X
X
1
25
1
I
0
0
2.
1
1
0
1
27
28
29
30
31
All
1
1
0
I
I
1
1
1
1
1
0
0
0
1
1
1
1
1
0
I
1
1
1
1
I
1
1
1
1
0
0
0
1
I
1
1
1
1
0
0
0
1
1
1
1
1
I
1
0
0
1
1
1
I
1
1
1
1
I
0
1
1
1
1
1
1
I
I
0
1
I
I
1
1
1
1
1
Hi·2
Hi-Z
Hi-2
Hi-Z
Hi·Z
Hi·Z
Hi-Z
Hi-Z
1
1
1
Do e· tear",
The output levels are not shown on the truth table since the customer specifies the output condition he desires at each of the eight outputs
for each of the 32 words (256 bits). The customer does· this by filling out the Truth Table
this data sheet, and sending it in with"his
purchase order.
on
INPUTS
WORD
BINARY SELECT
OUTPUTS
ENABLE
ME
VB
Y6
Y5
Y4
Hi·Z
Hi-Z
Hi·Z
V2
10
12
13
"
16
17
"
20
21
"
24
25
"
28
"
30
31
Hi·Z
Hi-l
Hi·'Z
Hi-Z
Hi·Z
x - Don"tear!!
Notice: This 5h~t muH be completed and signed by an authoriled representative of the
order can be entered
To be used by·Natlonal only
cu~tomer'<;
Authoriled Representative
company before an
Date
_ _ _ _ _ Part Numm.r
_ _ _ _ _ S.D. Number
Company
Date Received
Desired Part
7-32
o
OM7598
D DM8598
typical performance characteristics
Delay from Enable to High
Impedanc:a State
'oelay from Enable to Low
Impedance State
Delay from Address to Output
40
40
35
50
30
I
25
>
:!i
20
~
15
10
5
r- -
30
~
"-z
I
>
-
~
40
30
......
20
10
oL.......l-...L.-I.--l_L-.L-...l-....I
0
25
o
50 15 100 125
~~
-~
,,"L
ItpLH
"'Z
-15 -50 -25
35
1-+-+-f--t---t--1--t--I
I
:!
25
~CI
20
>
10-"".
' tZL
15
10
~
-
..- ~
'ZH
5
L-~~~-L-L~~~
-15 -50 -25
0
25
50
oL-~...l-...L.-L~--l~~
-15 -50 -25
15 100 125
TEMPERATURE ("CI
TEMPERATURE rCI
_i--'"
0
25
50 15 100 125
TEMPERATURE rCI
ac test circuit and switching time waveforms
~~NL~~~
V'"
TEST
POINT
..
FROM
OUTPUT
R,
;T::"
1.011
I.SV
v:--'
___ -""\
~.'j
OUTPUT
\5V
1.5V
~~:1=
J1.5V
vo,------'---.,--...J-
,.
....
UNDER
TEST
3OV:~
3.DV
lIE
~,.
~,.
"<1.5V
-
t,,,
vO ,
CLitdudllprobeandjigcapacitiMe.
Vo.
OUTPUT
'" 1.5V
-
t-j
\
OUTPUT
All diOdnlre lN31J114.
J
r\:'V
DV
O.5V
1\'
tll-
t.5V
)1
'I
1-.
,~
J
V....l
r
D.5V
O.SV
- '.,
~
110.: Inpll1wlVtformsM"ewppliedby pull2tenetlton
h8ll'ingthefoliowingm.lcteristics:t n "$10ns,tsSl0ns.
PRR '$1.0MH:Zlnd louT "" 511n.
ordering instructions
Progr~mming instructions for the DM7598/DM8598 are
solicited in the form of a sequenced deck of 32 standard
80-column data cards providing the information
requested under "data card format," accompanied by a
properly sequenced listing of these cards, and the supple·
mentary ordering data. Upon receipt of these items, a
computer run will be made from the deck of cards
which will produce a complete function table of the
requested part. This function table, showing output
conditions for each of the .32 words, will be forwarded
to the purchaser as verification of the input data as
interpreted by the computer·automated design (CAD)
program. This single run also generates mask and test
program data; therefore, verification of the function
table should be completed promptly.
Each card in the data deck prepared by the purchaser
identifies the word specified and describes the levels at
the eight outputs for that word. All addresses must
have all outputs defined and columns designated as
"blank" must not be punched. Cards should be punched
according to the data card format shown.
7·33
HI
ordering instructions (con't)
SUPPLEMENTARY ORDERING DATA
Col. 26-29: Blank
Submit the fallawing infarmation with the data cards:
Col. 30: Punch "H" ar "L" for autput Y3.
a)
b)
cl
Cal. 31-34: Blank
Customer's name and address
Custamer'spurchase arder number
Custamer's drawing number
Col. 35: Punch "H" ar "L" far autput Y2.
The fallawing infarmation will be furnished to. the
custamer:
al Natianal's part number
b) Natianal's sales arder number
cl Date received
Col. 36-39: Blank
Col. 40: Punch "H" or "L" for autput Y1.
Col. 41-49: Blank
DATA CARD FORMAT
Col. 50-51: Punch a right-justified integer representing
the current calendar day af the manth.
Col. 1-2: Punch a right-justified integer representing
the positive-logic binary input address (00-31) far the
ward described an the card.
Cal. 52: Blank
Col. 3-4: Blank
Col. 53-55: Punch an alphabetic abbreviation representing the current month.
Cal. 5: Punch "H" ar "L" far autput Y8. H : highvoltage level output, ·L : low-voltage level output.
Col. 56: Blank
Col. 6-9: Blank
Col. 10: Punch "H" or "L" far autput Y7.
Col. 57-58: Punch the last twa digits af the current
year.
Col. 11-14: Blank
Col. 59: Blank
Col. 15: Punch "H" or "L" for output Y6.
Col. 60-61: Punch "DM,"
Col. 16-19: Blank
Col. 62-66: Punch "7598" ar "8598."
Col. 20: Punch "H" or "L" far autput Y5.
Col. 67-68: Blank
Col. 21-24: Blank
Col. 69-80: These columns· may be used for any custamer informatian ar identification.
Col. 25: Punch "H" ar "L" far autput Y4.
7-34
Bipolar ROMs
~National
~Semiconductor
DM8618 bipolar character generator
general description
the character addresses "fall through" the latch. And
when the address latch control signal goes low, the
character addresses are latched.
The DM8678 is a 64·character bipolar character generator
with serial output designed primarily for the CRT display marketplace, and packaged in a standard 16·pin DIP.
The DM8678 incorporates several CRT system level
functions, aswell as a 7 X 9 or 5 X 7 row scan character
font. The DM8678 performs the system functions of
parallel to serial shifting, character address latching,
character spacing and character line spacing. These
system functions have required extra packages in the
past.
features
•
• Shifted lower case descending characters
• Serial output
• 16·pin package
• 20 MHz clock rate
• On·chip input latches
• On·chip shift register
• On·chip dot blanking
• On·chip row blanking
• TRI·STATE@ output
Shifted cnaracters can be generated by the on-chip
subtractor.
The clear input and the load enable input are active low.
Load enable is synchronous with the dot clock. Both
the line clock and the dot clock are positive edge·
triggered. When the address latch control signal is high,
ROW SCAN
7x9
X
X
X
X
DM8678BWF
DM8678CAE
DM8678CAB
DM8678CAH
DM8678CAD
DM8678BTK
DM8678CAS
X
X
X
X
X
64-character-row scan
• 5 X 7 or 7 X 9 font
5x7
FONT
PACKAGE
N,J
N,J
N,J
N,J
N,J
N,J
N,J
Upper Case Block Letters
Shifted Lower Case Block
X
Upper Case Block Letters
X
Shifted LowerCase Block
Kata Kana
Upper Case Script Letters
X
X
X
IBM 3741 Selectric
block diagram
connection diagram
Du.al~ln·Line
Package
"
AJ
ADDRESS LATCH
CONTROL
14
A1
LATCH
AS
ADDRESS LATCH
!3
4
CONTROL
LATCH
12
CLEAR
A.
M
15
A2
LATCH
11
LINE CLOCK
54X646IT
FONT
MATRIX
10
CLOCK CONTROL
LATCH
Vee
A'
A5
AS
OUTPUT
EN"ABU
OUTPUT
LOAD ENABLE
AJ
DOT CLOCK
GNO
lATCH
A'
TOP VIEW
A1
logic symbol
ADDRESS LATCH
CONTROL
co~~~~~----r""'\l
A1
A2
AJ
A.
liNE
A5
AS
ClOCK
fiEAR-----------~
SERIAL
OUTPUT
DOT
CLOCK
LOAD
OUTPUT
ENABI1:
ENABLE
tiNE
CLOCK
7·35
CLOCK
CONTROL
00
"'00"
(I)
:iE
0
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Lead Temperature (Soldering. 10 seconds)
operating conditions
(Note 1)
-{).5V to +7V
-1.5V to +5.5V
-{).5V to +5.5V
~5°e to +150o e
300"e
dc electrical characteristics
MIN
4.75
0
0
2.0
Supply Voltage (Vee)
Ambient Temperature (T A)
Logical "0" Input Voltage (Low)
Logical "1" Input Voltage (High)
UNITS
V
°e
V
V
MAX
5.25
+70
0.8
5.5
(Note 2)
PARAMETER
CONDITIONS
IlL
Input Load Current. All Inputs
VCC = Max. V,N = 0.45V
"H
Input Leakage Current. All Inputs
VCC = Max. V,N = 2.4V
II
Input Leakage Current. All Inputs
VCC = Max. V,N = 5.5V
VOL
Low Level Output Voltage
VCC = Min. IOL = 16 mA
V,L
Low Level Input Voltage
VCC= Min
V,H
High Level Input Voltage
VCC= Min
Vc
Input Clamp Voltage
VCC = Min. liN = -12 mA
C'N
I nput Capacitance
VCC; 5V. V,N = 2V, TA = 25°C.
MIN
TYP
MAX
-{J.8
-1.6
mA
40
/lA
1
mA
0.35
UNITS
0.45
V
0.80
V
2.0
V
-{J.8
-1.5
V
4.0
pF
6.0
pF
1 MHz
Co
Output Capacitance
VCC = 5V. Vo = 2V. TA = 25°C,
1 MHz. Output "OFF"
ICC
Power Supply Current
115
VCC = Max. All Inputs Grounded.
145
mA
All Outputs Open
TRI·STATE PARAMETERS
ISC
Output Short·Circuit Current
'HZ
Output Leakage
Va = OV. VCC = Max
-15
VCC = Max. Va = 0.45 to 2.4V.
-50
mA
±40
/lA
Ch ip Disabled
VOH
Output Voltage High
ac electrical characteristics
2.4
'OH = -2mA
V
3.2
(With standard load) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Access Time
TOO
Dot Clock to Output
35
55
ns
TEA
Output Enable
20
45
ns
TER
Output Disable
20
45
ns
Set·Up Time
TSl
Load to Dot Clock
40
25
TS2
Add ress to Load
350
200
TS3
Clear to Load
350
TS4
Control to Line Clock
40
ns
TS5
Line Clock to Load
950
ns
Address to Address Latch
40
ns
TS6
See Switching Time Waveforms
ns
ns
ns
Hold Time
THl
Load from Dot Clock
0
ns
TH2
Add ress from Load
0
ns
TH3
Control from Line Clock
100
ns
TH4
Address from Address Latch
40
ns
7.36
ac electrical characteristics
c
s:
00
(Continued) . (With standard load) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Line Clock
TW1
TW2
TW3
TW4
40
40
Clear
Dot Clock
TW5
fMAX
en
.....
00
Minimum Pulse Width
See Switching Time Waveforms
Load
30
60
Address Latch
40
Maximum Clock Frequency
ns
ns
ns
ns
ns
20
16
MHz
Note 1: Absolute m.axim~m ratings are those values beyond which the device may be permanently damaged. They do not mean that the device
may be operated at these values.
Note 2: These I imits,apply over the entire operating range unles~ stated otherwise. All typical values are for Vee = 5V ,and T A :::: 2S' c.
standard test load
VCC
•
300
DEVICE
OUTPUT
~
•
T'"
Ik
Input waveforms are supplied by a pulse generator
having the following characteristics: PRR = 1 MHz,
ZOUT = 50 Q, tr < 5 ns .andtf < 5 ns (between
1.0V and 2.0V).
TDO is measured with ou'tput enable at a steady low
level.
=-
switching time waveforms
I-TS6
3V
ADDRESS INPUT
'\ II.
r\.SV
~
OV
j
TWI
~v
TS4
CLOCK CONTROL
~11
)1\
TS2-
~
ADDRESS
lATCH CONTROL
LINE CLOCK
TH4
TH2
1\
I- TWS-
i
TSS
x
TH3
TS3 .
TW4-
TW2U
CLEAR
THt
I-TSI
\
LOAD ENABLE
TW3
DOT CLOCK
r
\
-----. TOO
y-'\.-/::~
l.SV
OUTPUT ENABLE
LTER
\111 SV
/'\.
OUTPUT
7·37
L
truth tables
a) Address Latch
b) Output
OUTPUT
ENABLE
FUNGTION
PERFORMED
Latched
Fall Through
ADDRESS LATCH
CONTROL
0
1
1
0
STATE OF
THE OUTPUT
Output Hi-Z
Data Out
c) 4-Bit Line Counter
CLOCK CONTROL
LINE CLOCK
CLEAR
H
:..F
X
X
H
L
Increment line counter
Asynchronous clear
LINE COUNTER
L
X
H
'-
H
H
resets counter
Clock inhibited
No change on high-tolow clock edge
x = Don't'care
definitions
A l-A6: Character address_ A 6-bit code which selects
1 of the 64 characters in the font_
Load Enable: Active low load command which routes
data from the character ROM to the "0" inputs of the
7-bit sh ift register_
Clear: Active low clear for mod 16 row counter, (can be
used'to truncate mod 16 counter)_
Dot Clock: A low-to-high transitIOn of the dot clock
loads the shift register if load enable is low or shifts
data if load enable is high.
Line Clock: Clock that advances the line counter.
Advances counter on the low-to-high transition_
Output Enable: An active low output enable_ When high
the output is in the Hi-Z state_
Clock Control: Enables - line clock when high and
disables line clock when low_
Output: .A TTL TRI-STATE output buff.er.
functional description
To select a character, a 6-bit binary word must be
present at the address inputs A l-A6 when the address
latch control is high. This address can be latched by
bringing the address latch control signal low after
40 ns set-up time. When the clear input receives a low
pulse, the counter is reset to zero_ The shift register can
be Io:>aded (TS2 ns) after the character is addressed_
Data, representing one horizontal Iine of the addressed
character, is available at the output when the load
enable input is brought low_ As shown in Figure 1,
valid data arrives serially at the output. Dot clock
pulses beyond that required to shift out one line of the
character will add lows to the end of character. This
provides a horizontal spacing between characters.
a
pulses at the line clock input. Any additional line
clocks beyond that required to display the character
will put a vertical space between characters_ This spacing
can be truncated by bringing the clear input low_
Detailed system application infomation is contained in
application note AN-167 available from National.
A two character display example is shown in Figure 3
and a typical system timing waveform is shown in
Figure 4_
A chip select input is provided for expansion of the
character font_ The various standard fonts are shown in
Figures 5,6,7,8,9 and 10_
Figure 2 shows how the counter sequences through the
rows of addressed lines with the application of clock
7-38
c
functional description
s:00
(Continued)
Character Cycle - ROM data corresponding to one
line of characters is loaded into the shift register TS2
after the ROM is addressed. When load enable goes low,
ROM data is allowed to be present at the D input of
the shift register via the MUX. The first bit of the ROM
data is transferred to the output at the next low-to-high
transition of the dot clock: After load enable goes back
high, the second to seventh clock pulses shift out the
rest of the selected row of the addressed character.
Additional clock pulses will shift out low data used
for spacing.
LINE
CLOCK
Line Cycle - The line counter is a mod 16 counter.
A low-to:high transition of the line clock advances the
line counter to the next count. If, for any reason, the
counts need to be truncated, a low signal at the crear
input resets the counter to zero. The clock control may
be used as a line clock disable. A high signal at the line
clock control terminal enables the counter and a low
signal disables the line clock.
~
.
V ,.,-.
CH~~~~:~~ ________________--J)(~
______________________~__________________________________________~
v
DOT CLOCK
n n
..,..JI \...____---'__________________________-:-__.......1 \
OUTPUT __________
OUTPUT
ISE~~~TEI
/
.......
~----------------
I
f-._ _ _ _ _ _ _ _ _ _
VALID DATA OUT - - - - - - - - - - 1
Note. Output goes and stays low following the leading edge of the eighth Dot-Clock pulse until Load enable is enabled again a,nd new parallel data
is loaded into th,e shift register.
FIGURE 1. Character Cycle
CHARACTER
ADDRESS
INPUT ______________________
-+-'
LINE
CLOCK
CLOCK
CONTROL
---------------------~+---------------------'
DISPLAY
FIRST LINE
OF N CHARACTERS
FIGURE 2. Line Cycle
7-39
DISPLAY
DISPLAY
SECOND LINE
THIRD LINE
OF N CHARACTERS
OF N CHARACTERS
m
.....
00
CIO
~
functional description
(Continued)
CIO
~
C
I-
TWO CHARACTER CYCLE
'I
Al--.J
A2
ASCII
CODED
ADDRESS
INPUTS
AJI
A41
AS--.J
A6
LOADLJ
ENABLE
U
U
DOT
CLOCK
CLOCK
LINE
OUTPUT
CO NTROL CLOCK CLEAR ENABLE
ADDITIONAL
LINE COUNTS
FOR VERTICAL
SPACE
FIGURE 3. Example of Two Characters Display Timing
7-40
it
j
$l
S'
j
~
Q.
m
..,
'S'
(')
0'
I.
j
rn.=u
~B.-
AOO:~~:~~~.~= · ~~
~
mAR
~
.....
;,.
-
/
l50ns.
:. -
()
o
;:;
:;'
0:
'"a.
-
-'
,
-. (
...
01:0 nl
LlNECLOCK~.
"'~~~
CLOCK
CONTROL
me'
_
.~
....
__
LOAD
ENAm
DOT CLOCK
OUTPUT~~
~
1--~------------VALlDDDT DATA---------~--_t--_:_-
r
.Shown here for operation- with dynamic memory. ;For static .memory operation the. address latch control would be tied high and the character
addresses would be stable between each address ch~nge occurring 350 ns before the hlgh-ta-Iow transition of Load enable.
FIGURE 4. Typical System Timing Waveform
.~
/(
SL98wa
functional description
(Continued)
FIGURE 5. DM8678BWF
"Shifted character. (see Figure 72)
FIGURE 6. DM8678CAE
Note. A ufilled in" dot represents a high memory output.
7·42
c
functional description
s:00
(Continued)
O'l
~
FIGURE 8. DM8678CAH
7·43
~
CD
IX)
:E
C
functional description
(Continued)
Kata Kana Font will be Available in October 1977
FIGURE 9. DMB678CAD
FIGURE 10. DMB67BBTK
FIGURE 11. DM8678CAS
7-44
functional description
c
s:CO
(Continued)
en
"""
CO
FIGURE 12. Shifted Characters for CAE
ordering information
FIGURE 13. Shifted Characters for CAH
(For special character font for device OM8678).
CUSTOMER CARD INPUT FORMAT
Column '1-3
2-digit character address, from· 0-63 preceded by
a letter "C".
Column 17
Blank
Column 18
Row SUM-Total number of "1 's" presents in row
data and tag bit expressed in decimal.
Column 4
Blank
Column 5-6
1·digit Iine address, from 0-8, preceded by a let·
ter "L".
"TB" CARD FORMAT (total of eight cards)
Column 7
Blank
Immediately following the data cards, there should be
"TB" cards t~ indicate the column sum.
Column 8-14
Row data which represents one horizontal row· of
dots at the specified line address and character
address, with first dot at Column 8 and seventh dot
at Column 14. Character for TTL high level is 1,
for low level is O.
Column 1-2
The character "TB".
Column 15
Blank
Column 4
Blank
Column 16
Tag bit-O for normal character and 1 for shifted
character only .
Column 5-7
Column SUM-Total number of "1 's" in column
expressed in decimal.
Column 3
1·digit corresponding to Dot number. Use number 8
for tag bit.
7·45
co
~
truth table input format
CO
:E
c
CHARACTER
ADDRESS
LINE
ADDRESS
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
a
8
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
~OT
DATA
01,02,03,04,05,06,07
7
TB
7-46
TAG BIT
SUM
.
Semiconductor'
~National
a
Bipolar ROMs
DM76L97/DM86L97 TRI-STATE@low power
1024-bit read only memory
general
des~ription
features
The DM76L97/DM86L97.is a custom-programmed
Read Only Memory organized as 256 four-bit
words. Selection of the proper word is accomp:
lisheo;1 through the eight select inputs.
• Full tenth-power technology
• Pin compatible with SN54187/SN74187
• Typical power dissipation
Two overriding memory enable inputs are provided
which when mask·programmed in one of the
three options described will cause all four outputs
to read· either the normal memory contents or
go to the high impedance state.
75mW
• Typical access time
70 ns
• Custom-programmed memory enable inputs
• TRI-STATE outputs
logic and connection diagrams
1....... ' . . .IIYtt;u
a ••
• IIIOIIYIII\TIIII
IIf11~IIT
SlUtT
IIIlIIDII,r·"""~"'==::::rJ--I+--I-t--I-l---,
'li"k(l"Etoil~
Dual-In-Line and Flat Package
MEMORY
OUTPUTS
ENABLE
. 1.1"', .......---- ,. ,- - - - - -.....
Vee
S£LECT H
ME2
ME,·
VI
Order Number DM76L97J
or DM86L97J
SaePackage10
Order Number DM76L97N
or DM86L97N
See Package 15
Order Number OM76L97W
or OM86L97W
See Package 28
BINARY SElEn
TOP VIEW
7-47
absolute maximuni ratings
(Note 1)
Supply Voltage (VCC)
DM76l97
DM86l97
7.0V
Supply Voltage
5.5V
Input Voltage
5.5V
Ou tput Voltage
-65°C to +150·C
Storage Temperature Range
300°C
lead Temperatu,e (Soldering, 10 seconds)
electrical characteristics
PARAMETER
operating conditions
Temperature (TA)
DM76L97
DM86l97
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
~55
0,
+125
+70
°c
°c
(Note 2)
CONDITIONS
MIN
TYP
MAX
UNITS
0.7
V
V
2.0
Logical "I" Input Voltage
Vee = Min
Logical "0" Input Voltage
Vee=Min
Logical "1" Output Voltage
Vee = Min, 10 = -1.0 rnA
Logical "0" Output Voltage
DM76L97
DM86L97
Vee = Min, 10 = 2,0 rnA
Vee = Min, 10 = 3.2 mA
Third State Output Current
DM76L97
DM86L97
Vee = Max, Vo = 204V
Vee = Max, Vo = Oo4V
Logical "I" Input Current
Vee = Max, V'N = 2.4V
Vee = Max, V'N = 5.5V
Logical "0" Input Current
Vee = Max, V'N = 0.3V
Output Short Circuit Current (Note 3)
Vee = Max, Va = OV
V
2.4
0.3
004
V
V
±40
±40
10
100
-180
-6.0
15
-30
rnA
20
rnA
Supply Current
Vee,:, Max, All Inputs at GND
Third State Output Current
Vee = Max, VOUT = 2.4V
Vee = Max, VOUT = 0.4V
Input Clamp Voltage
Vee=Min,I'N =-12mA
Propagation Delay to a Logical "0"
From Address to Output (tpdo)
Vee 5.0V, C L = 50 pF
TA = 25°C
55
85
ns
Propagation Delay to a Logical "1"
Vee = 5.0V, CL = 50 pF
TA = 25°C
86
130
ns
From Address to Output (tpd ,)
Delay From Enable to High Impedance
State (From Logical "1" Level) (t'H)
Vee = 5.0V, C L = 5.0 pF
TA = 25"C
15
23
ns
Delay From Enable to High Impedance
State (From Logical "0" Level) (tOH )
Vee = 5.0V, C L = 5.0 pF
TA=25"C
57
86
ns
Delay From Enable to Logical "1" Level
(From Hi~ Impedance State) (tH')
Vee = 5.0V, C L = 50 pF
TA=25"C
34 .
51
ns
Delay From Enable to Logical "0" Level
(From High Impedance State) (tHO)
Vee = 5.0V, C L = 50 pF
TA = 25"C
47
70
ns
=
+40
-40
-1.5
Note 1: "Absofute Maximum Ratings" are tho5e,values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range", they are not meant to imply that the devices should be operated at these limits.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125"C temperature range for the DM76L97
and across the Q"C to +70°C range for the DM86L97. All typicals are given for Vce = 5.0V and T A = 25°C.
Note 3: Only One output' at a time should be shorted.
7-48
o
s:.....
ordering instructions
en
Programming instructions for the DM76L97 or
DM86L97 are solicited in the form of a sequenced
deck of 32 standard 80·column data cards pro·
viding the information requested under data card
format, accompanied' by a properly sequenced
listing of these ,cards, and the s\lpplementary
ordering data. Upon receipt of these items, acom·
puter run will be made from the deck of cards
which wil,1 produce a complete truth table of the
requested part. This truth table, showing output
conditions for each' of the 256 words, will be
forwarded to the purchaser as verification of the
input data as interpreted by the computer·auto·
mated design (CAD) program. This single run also
generates ma.sk and test program data; therefore.
verification of the truth table, should be completed
promptly.
Punch "H", "L", or "X" for bits four,
three, two, and one (outputsY4, Y3, Y2,
and Y1 in that order) for the first set of
outputs specified on ,the card.H = high·
level output, L = low·level output, X =
output irrelevant.
10·13
14
Blank
15·18
Punch "H", "L", or "X" for the second
set of outputs.
Blank
19
20·23
Punch "H", "L", or "X" for the third,set
of outputs.
Blank
24
Punch "H", "L", or "X" for the fourth set
of outputs.
25·28
29
Each card in the data deck prepared by the pur·
chaser identifies ,the eight words specified and
describes the conditions at the four outputs for
each of the eight words. All addresses must have
all outputs defined and columns designated as
"blank" must not be punched. Cards should be
punched according to the data card format shown.
Blank
Punch "H", "L", or "X" for the fifth set
of outputs.
30·33
Blank
34
Punch "H", "L", or "X" for the sixth set
of outputs.
35-38
Blank
39
supplementary ordering data
Blank
49
Punch a right·justified integer representing
the current calendar day of the month.
50-51
52
Column'
1· 3
Punch a right-j\lstified integer representing
the binary input address (000·248) for
the first set of, O\ltputs described on the
card.
8· 9
Punch "H", "L", or "X" for the eighth
set of outputs.
45·48
data card format
4
Blank
44
Submit the following information with the data
cards:
a) Customer's name and address
b) Customer's purchase order number
c) Customer's drawing n\lmber.
5· 7
Punch "H", "L", or"X" for the seventh
set of outputs.
40-43
Blank
Punch an alphabetic abbreviation repre·
senting the current month.
53-55
Blank
56
Punch the last two digits of the current
year.
57·58
Punch a "-" (Minus sign)
59
Punch a right·justified integer representing
the binary input address (007·255) for
the last set of outputs described oh the
card.
Blank
Blank
60-61
Punch "DM"
62·67
Punch the National Semiconductor part
number DM76L97 or DM86L97.
68·70
Blank
truth table
OUTPUTS
OPTION
ME,
ME2
1
0
0
Normal
High Impedance
2
3
1
X
X
1
High Impedance
1
1
Normal
0
X
High Impedance
X
0
High Impedance
1
0
Normal
X
1
X
High I m'pedance
0
X'" Don't care
7·49
Hi~h
Impedance
(D
~
o
s:CO
en
r
(D
.....
N
o
N
en
""~
CO
C
.......
N
o
N
en
""""~
C
~
o
N
en
""~
co
C
Bipolar ROMs
~National
~ Semiconductor.
DM77S201/DM87S201 open-collector 2048-bit ROM with latches
DM77S202/DM87S202 TRI-STATE® 2048-bit ROM with latches
features
general description
These Schottky ROM memories are organized in the
popular 256 words by 8 bits configuration. A memory
enable input is provided to control the output states.
When the enable input is in the low state, the outputs
present the contents of the selected word_ An output
latch control is provided. If the latch control pin is high,
the data falls through to the output enable gate. If the
latch control pin is low, the data is latched and the
·address may be changed without affecting the output
data.
• Schottky-clamped for high speed
Address access-60 ns max
Enable access-30 ns max
• PNP inputs reduce input loading
• All dc and ac parameters guaranteed over temperature
• Open-collector or TRI-STATE® outputs
• High density 20-pin package
• PROM mates are DM87S221 and DM87S222
.......
(5
N
en
""""C~
Commercial
OpenCollector
DM87S201
X
X
DM87S202
X
MIlitary
DM77S201
DMT7S202
X
X
TRI-STATE
Package
X
N, J
N, J
X
J
X
J
connection diagram
block diagram
Dual-In-Line Package
.----,---,----, ' ' vee
An
Z048·BIT ARRAY
32 X 64·BIT
MEMORVIAATRIX
A\
19 A1
AZ
A.
A'
A'
A.
16Ei
.\
lSIA"i"CR
CONTROL
.8
.2 '
rn&ii
13
.."
" .6
GN.
to1-_ _ _ _ _--1 '1 05
CONTROL
TOP VIEW
logic symbol
DB
05
04
"
oz
.\
A'
01
"
..••
.,
03
•6
.8
7-50
.,
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Le,ad Temperature (Soldering, 1.0 seconds)
o
operating conditions
(Note 1)
MIN
MAX
UNITS
4.5
4,75
5.5
5.25
V
V
-55
0
+125
+70
°c
°e
Logical "0" Input Voltage ILow)
0
0.8
V
Logical "1" Input Voltage IHigh)
2.0
5.5
V
Supply Volta~IVcc)
DM77S201, DM77S202
DM87S201, DM87S202
-O.SV to +7V
-1.2V to +5.5V
-O.5V to +5.5V
--b5°C to +150°C
300°C
Ambient Temperature (T A)
DM77S201, DM77S202
DM87S201; DM87S202
s:.....
.....
en
N
o
...
........
o
s:CO
.....
en
N
o....
dc electrical characteristics
o
(Note 2)
s:.....
DM77S201, 77S202
DM87S201, 87S202
CONDITIONS
PARAMETER
MIN
TYP
MAX
-80
-250
MIN
TYP
-80
UNITS
MAX
IlL
Input Load Current, All Inputs
Vee = Max, VIN = OA5V
-250
/lA
IIH
Input' Leakage Current, All Inputs
VCC = Max, VIN = 2.7V
25
25
/lA
II
Input Leakage Current, All Inputs
VCC = Max, VIN = S.SV
1.0
10
rnA
VOL
Low Leitel Output Voltage
Vee = Min, IOL = 16 rnA
0.35
0.35
0.45
0.80
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
ICEX
Output Leakage Current
VCC = Max, VCEX ·2.4V
100
VCC = Max, VCEX = 5.5V
I nput Clamp Voltage
VCC = Min, liN = -18 rnA
CIN
I nput Capacitance
VCC = 5V, YiN = 2V, TA = 25°C,
Co
Output Capacitance
VCC = 5V, Vo = 2V, TA
V
V
50
IOpen·Collector Only)
V
0.80
2.0
2.0
Vc
0.45
"0.8
-1.2
-0.8
50
/lA
100
p.A
-1.2
V
4.0
4.0
pF
6.0
6.0
pF
1 MHz
c.
25°C,
1 MHz, Output "OFF"
ICC
Power Supply Current
120
Vee = Max, All Inputs Grounded,
150
120
150
rnA
All Outputs Open
TRI·STATE PARAMETERS
Ise
Output Short Circuit Current
1HZ
Output Leakage (TRI·STATE)
Vo =
av,
VCC = Max, (Note 3)
-20
-45
-20
-70
-45
+50
Vee = Max, Vo = 0.45 to 2.4V,
-70
rnA
±50
p.A
Chip Disabled
VOH
Output Voltage High
2.4
IOH=-2mA
3.2
V
IOH - -6.5 mA
ac electrical characteristics
2.4
V
(With standard load)
DM77S201,77S202
PARAMETER
3.2
DM87S201,87S202
SV +10%;-5S'Cto+125"e 5V t5%; aCe to +70 c e
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tAA
Address Access Time
38
75
38
60
ns
tEA
Enable Access Time
18
40
18
30
ns
tER
Enable Recovery Time
18
40
18
30
ns
tLO
Latch To Output
14
30
14
20
ns
Note 1: Absol,ute maximum ratings are those values beyond which the device may be permanently damaged. They do nOt mean that the device
may be oper:ated at these values.
Note 2: These limits apply over the entire operating range unless stated otherwise. All typical values are for
Note 3:
Vee
==
5V and- T A ;:: 25°C.
During ISC 'measUrement, only one output at a time should be grounded. Permanent damage may otherwise result.
7·51
.....
en
N
o
N
........
o
s:CO
.....
en
N
o
N
~National
a
Shift Registers
Semiconductor
MM1402A, MM1403A, MM1404A, MM5024A
1024-bit dynamic shift registers
general description
The MM1402A,MM1403A,MM14Q4A"MM5024A
1024-bit dynamic shift registers are MOS monolithic Integrated circuits using silicon gate technology to achieve bipolar compatibility. 5 MHz
data rates are achieved by' on-chipmultiplexing.
The clock rate is one-half the data rate; i.e.,
one data bit is entered for each 1/>1 and 1/>2 clock,
pulse.
• Seven standard configurations
MM1402AD
"
Quad 256-bit
Quad 256-bit
MM1402AN
Dual 512-bit
MM1403AH
Dual 512·bit
MM1403AN
Single 1024-bit
MM1404AH
Single Hi24-bit
MM1404AN
Single 1024.-bit with
MMS024AH
internal pull-down resistor
All devices in the family can oj:leratefrom +5V,
-5V, or +5V, -9V power supplies.
'
, applications
features
• Radar and sonar processors
• CRT displays
• Terminals
• Desk top calculators
• Disk and drum replacement
.Com!luier peripherals
• Suffer memory
• Special purpose computers-signal processors,
digital filtering and correlators, receivers,spectral cOmpre~s and digital differential analyzers
• Telephone equipment
• . Medical equipment
• Guaranteed 5 MHz operation
•
.1 mW/bit at 1 MHz
Low power dissipation
• DTl/TTL compatible
• Low clock capacitance
125 pF
•
::;;: 1 IJA
Low clock leakage
• Inputs protected against Static charge
• Operation from +5V, -5V or +5V, -9V power
supplies
connection diagrams
Metal Can Package
Metal CanPacld. IPd versus temperature curves. The lowest guaranteed clock frequency can be attained by making
q,d equal to (Pd' The minimum guaranteed clock frequency is:
d), where the variables may not exceed thegU'aranteed
Note 2: Capacitance is guaranteed by periodic testing.
8·2
typical application
OTL/TTL to MOS Interface
R L Load Resistor Value
for Oifferent VOO Supplies
Vss ~ 5V
V OD ~ -5V
IRL1
RL2
I RL3
'voo
V~U·
"
U
4.7k
Not required
Voo = -9V
4.7k
6.8k
N'ot required
V~
v~
v~
~A
3.01<
Vss '5V
4.7
k~) re~istors
is illcluded on the chip in the MM5D24A
and is connected between Pin 6 and VOl)'
performance curves
1
Guaranteed Maximum Data
Phase Delay Times vs
Temperature INote 1)
Guaranteed Minimum Data
Frequency vs Temperature
INote 1)
10k
100
~
.
~
;
...>
1
I\.
10
1fi
;!
~
~
..
:i
'"
100
'"
10
10 os
-..,i" r-- c--
/
:;:-:~~J~~M~
I
0.1
~
id '"
~
f-¢~-.~-IOns
I~
~
"...
;;
'"z
iii
f- .... -130ns
I
g;
"'\
1.0
." OR
Ik
'"
_20
~O
20
100
60
-611
T. - AMBIENT TEMPERATURE (OC)
-20
20
60
100
T. - AMBIENT TEMPERATURE rCI
switching time waveforms
liT liNES
I
BITl
I
Bin
I
BIlJ
I
BITC
1
.,
I
I
LJ I U
I
LJ I LJ
I
I
I
I
I
DA.Ti1llln
I
I
I
I
I
I
I
I
"
''1''
DATA 1111
I
I
~DATAINI
1
. 2
....
I
"
"1"
..
"1"
I
-'"
I
I
I
I
I
LJ
LJ I
Lr
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DATA OUT
Shown is a simplified illustration of the timing of a 4·bit multiplexed register showing
input output relationships with respect to the clock. If data enters the register at <1>1
time, it exists at r/>1 time. (Beginning on <1>,.. negative going edge and ending on the
succeeding <1>2'0 negative going edge.)
8·3
timing diagram
BIT1
BITN+l
81Tl
8IT'N+2
BITZ
10%U--~VOH
<,
I
CLOCK
,
.,
BIT N
BIT2
CLOCK
I
I
I
1-
II
~l¢d:---
I
1,
I
90%-1 --
90%
Ir---r- CLOCK PERIOD - - - - I
~--I ______ [ I
I
------~:~:-.,"0%~'
I
I
I
:
"
... - - j
I
:
---Vo<
.'-'t- -11-<,
II
I
I
I
I- I
I
I
- I ."" I-DATA PERIOO.....j
i
I
I
I
I
r------------~~---------r~----~,-----·~
~
'\.___.
IN BIT 1
II
II
I
"
IiI
I I
"'-;--1
L-----
II
II
IN 81T 2
.
tpdH
-II :-
;;:;;U;-------------------U---~~-----1..
-l1 [__
I
,*-=~f;VABOVEGNO(VDO)
------------' \- OUT iiTi
------------------------------~n'
8-4
VII.
tp6l.
_J
OUT BIT 2
VOL
~National
Shift Registers
~ Semiconductor
MM4016/MM5016 512-bit dynamic shift register
general description
• Military and Commercial Temperature Ranges
_55°C to +125°C
MM4016
DoC to +70°C
MM5016
The MM4016/MM5016. 512-bit dynamic shift register is a monolithic MOS integrated circuit utilizing P channel enhancement mode low threshold
technology to achieve bipolar compatibility. An
input tap provides the option. of using the device
as either a 500 or 512-bit register.
•
Low power dissipation
at 1 MHz max.
30 IlW/bit
at 100 kHz typo
<
features
•
Bipolar compatibility
•
Package option
•
Fewer clock drivers requ ired
•
System flexibility
< O. 17 mW/bit
+5V, -12V operation
No pull-up or pull-down
resistors requ ired.
TO'1000r choice of two
Dual-I n-Line Packages
applications
• Glass and magnetostrictive delay line replace·
ment.
• CRT refresh memory.
Clock line
capacitance of
100 pF typ
• Radar delay line.
300 Hz guaranteed min.
operating frequency at 25°C.
500 or 512-bit register length.
• Drum memory storage (silicon store)
• Long serial memory.
connection diagrams
Metal Can Package
Dual-tn-Line Package
Dual-In-Line Package
16 Nt
NC
SOD·SIT
INPUT
v"
Note: Pin 5 connected to
ca~e.
TOP VIEW
TOP VIEW
Order Number MM4016H
or MM5016H
Order Number MM5016N
See Package 24
See Package 12
See Package 3
typical application
TT LIMOS I nter!ace
.,V
I
I
L------T-~~~~~~J
Vee
-12V
!\lute: The ullUud input pin must be connocted to Vss.
8-5
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
Vss + 0.3V to Vss -22V
_55°C to +125°e
oOe to +70oe
_65°C to +150o e
300°C
MM4016
MM5016
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
T A within operating temperature range, Vss = +5.0V ±5%, VGG = -12.0V ±10%, unless otherwise specified.
MIN
CONDITIONS
PARAMETER
Data I nput Levels
Logical HIGH Level IV ,H )
Logical LOW Level IV,LI
Vss - 2.0
Vss - 18.5
Data I nput Leakage
V ,N = - 20V, T A = 25°C,
All Other Pins GN D
Data Input Capacitance
V ,N = O.OV, f = 1 MHz,
All Other Pins GND, INote 21
Clock Input Levels
Logical HIGH Level (V¢HI
Logical LOW Level IV f(mini
=
1
i
T,N
+ TOUT
where T,N and TOUT do not exceed the guaranteed maxin:"!ums.
Note 2: Capacitance is guaranteed by periodic testing.
8-6
:s:
s:.p..
performance characteristics
Typical Minimum Clock
...oen
Typical Maximum TIN
and TOUT vs Temperature
(Note 1)
Frequency vs'Temperature
(Note 1)
MM4016
r-t-
~ 2K
..
TLN
200
;-=c-
j"-:;
d100
20
t; 10
~ 5.0
Z
.= 2.0
Tou:=
iii
TIN or TOUT =200ns
'"
=> 50
Z 20
'"
i
i
I'~
~ 500
~
50
MM5018:;#::;~ ~:;z t-
~ lK
'x"
'"'"
I I
10
·zo
-60
20
60
100
;<
E 1.0
0.5
MM501S"('!
o.z
-60
-zo
'h"'lMHz
Vss - 5.0V
4.0
3.5
;<
E 3.0 ",...
j
1.5
",... I--'
_55°C
=25°C ..... ",...
""...
Vss - 5.0V
VGG = -12.0V-+--l---1~--l
IZ5°C....
~ f-"'"
1.0
16
15
Typical O.t. Output Sink
Current vs Voltage
DATA:c.o~ ~
T.
Z.O
H+I1Hll1f-l-+l+HIH--i V~L - -12.0V
DATA- 0-1-0-1
0.1 L..J,-L.UlJIII..-W.llIJIILLu.wu.'--'-........wII
0.01
0.10
1.0
10.0
0.001
CLOCK FREOUENCV ••,1MHz)
Typical Data Output Source
Current YS Voltage
vr I---"
2.5
140
100
150 ns
Vss '"'" S.OV
~tJIEe[lmS 4?w
VGG '" -12.0V
V¢lL =: -1,2V
.... 1---"
.....
60
"l
TEMPERATURE eC)
Tvpical Power Supply
¢trw =150 ns
ZO
0.3
MM4016
I
0.1
Current vs Voltage
5.0
o
o
'"
1.0
140
+++.!JMh"-+flll!Il
3.0
I'
TEMPERATURE 1°C)
4.5
V¢l '" -12.0V
17
4
19
18
Vss - VGG (VI
-1
VOUT (V)
VOUT (V)
ac test circuit
switching time waveforms
'5V
OK
¢ouT
s:
:s:en
10.0~
100
I-t-
.......
Typical Power Supply
Current vs Clock Frequency
ClOCK
-'--------..
VSS·UV
_'''t1.5~'"
"'r
--"y,;-
_ _ _-:-_ _ _
8-7
...oc:n
~National
Shift Registers
~ Semiconductor
MM4025/MM5025 dual 1024-bit dynamic shift register
MM4026/MMs026 dual 1024-bit dynamic shift register
MM4027/MM5027 2048-bit dynamic shift register
general description
these 2048-bit dynamic shift registers are MOS
monolithic integrated .circuits using P-channel silicon gate technology_ They employ a push-pull
output for bipolar compatability and on-chip
multiplexing to achieve a 6 MHz data rate. The
clock rate is one-half the data rate, i.e., one data
bit is entered for each <1>1 and <1>2 clock pulse.
Ln
N
o
Ln
::E
::E
N
•
Bipolar compatibility
•
High frequency of operation
120 !.lW/bit
rate O°C, guaranteed
190 pF max
•
Low clock capacitance
•
Wide operating temperature range
MM4025,MM4026,MM4027 -55°C to +125°C
MM5025,MM5026,MM5027
The MM4026/MM5026 has an individual logicselect line to load one of the two inputs on each
of the 1024-bit registers_
features
o
'It
::E
::E
Low power dissipation
at 1 MHz
The 'MM4025/MM5025 and MM4027/MM5027
have on-chip Ipgic to load and recirculate data.
......
Ln
•
applications
Standard +5V, -12V
power su ppl ies
6 MHz
guaranteed
•
"Silicon store" replacement for drum and disc
memories
•
CRT displays
•
Buffer memories
logic and connection diagrams
Military Temperature Range
Dual-I n-Line Package
Flat Package
Dual-I n-Line Package
" '0.
LOAD
1
'.
.
120ATA
INPUT
CONTRO~
•
OATA
tOPVlfW
Order Number MM4025D
orMM5025D
See Package 3
Order Number MM4026D .
orMM5026D
See Package 3
Order Number MM4027F
or MM5027F
See Package 26
Commercial Temperature Range
Dual-In-Line Package
Dual-. "-Line Package
Dual-In-Line Package
tOAD
CONTROL
IN'IIT211
'.
Order Number MM5025N
Order Number MM5026N
Order Number MM5027N
~ee Package 13
See Package 15
See Package 12
8-8
absolute maximum ratings
+0.3 to -20.0V
Voltage at Any Pin With Respect to Vss
Operating Ambient Temperature Range
MM4025.MM4026,MM4027
MM5025,MM5026,MM5027
-55°C tQ.+125°C
aOc to +700e
-65°C to +150°C
300"C
Storage Temperature Range
Lead Temperature {Soldering, 10 s'ec,l
electrical characteristics
Vss = +5.0V ± 5%, Voo = GND,V GG = -12.0V±10%
TA within operating temperature range unless otherwise stated.
MAX
UNITS
Data Input Levels
Logical High Level (V. H )
PARAMETER
Vss + 0.3
Logical Low Level (V ILl
Vss - 4.2
V
V
CONOITIONS
MIN
TYP
s:
s:
~
o
Data Input Leakage
YIN'" -10V, TA '" 25°C. AU other pinsGN,D
O.Ql
LO
~A
N
Data I nput Capacitance
VIN '" OV. f'" 1 MHz, All other pins GND (Note 1)
25
5.0
pF
.......
Vss + 0.3
V
V
Load/Select Input Levels
Logical High Level (VIt"d
Logical Low Level (V1ll
Vss-4.2
Load/Select 'I nput Leakage
VIN
Load/Select Input Capacitance
VIN '" OV, f
='
-lOY, T A == 25°C, All other pins GND
=
1 MHz, All other pin.s GND (Note 1)
Clock Input Levels
Lbgical High Level (V 1>H)
Clock Input Leakage
V¢ = -15V, T A = 25°C, All other pins GND
Clock Input Capacitance
Vq; = OV, f '" 1 MHz. AI! other pins GND (Note 1)
1.0
)lA
o
4.0
7.0
pF
en
Vss + 0.3
Vss - 14.5
.05
-0.5
'SOURCE'"
ISINK '"
1.6
190
N
V
V
MA
pF
I
2.4
0.0
rnA
mA
10
165
Data Output Levels
Logical High Level (V OH )
Logical Low Leve! (Vad
U1
0.01
Vss - 1.0
Vss -18.5
Logical Low Level (V4>d
en
s:
s:
0.4
V
V
3.5
3.5
3.5
mA
mA
mA
Vss
Power Supply Current
IGG
TA '" 25°C. VGG = -12.0V, ¢pw = 160 ns
Vss = 5.0V, V¢L = -12.0V, DATA == Note 4
Voo = O.OV
2
2
2
0.01 MHz S $f S 0.1 MHz
¢f = 1.0MHz
¢f'" 3.0 MHz
100
0.01 MHz ¢f S 0.1 MHz
8
¢," 1.0 MHz
9," 3.0 MHz
22
48
15
32
70
mA
mA
mA
Clock ,Freque'ncy (OPf)
MM4025,MM4026,MM4027
MM5025,MM5026,MM5027
rpt, '" .ptt
=
20 ns (Note 2, Note 3 & Note 5)
0.03
0.003
¢t, = (/>tf
'"
20 ns, Data Rate
0240
0.240
. 2.0
4.0
1.0
1.25
MHz
MHz
Clock Pulsewidth (¢pw)
MM4025,MM4026,MM4027
MM5025,MM5026,MM5027
Clock Phase Delay Times i¢d,1)d l
See Curves
=
2 ¢f
gs
0.5
~s
~s
10
Clock Transition Times (¢t,. 4>tt)
Partial Bit Times (I)
T 1 Partial Bit Time
8.0
10
~s
ns
(Note 2, NO,te 3)
MM4025.MM4026,MM4027
MM5025,MM5026,MM5027
0.5
0.4
16.5
165
T2 Partial BitTime
MM4025,MM4026,MM4027
MM5025,MM5026,MM5027
0.5
0.4
16.5
165
~s
~s
Data & Load/Select Input Setup Time (tdS)
35
ns
Data & Load/Select Input Hold Time (t d ",)
20
os
Data Output Propagation Delay from 4>
Delay to High Level (tP<*-I)
Delay to. Low Level (tpdd
15 pF Output Capacitance
Note 1: Capacitance is guaranteed by periodic testing
Nqte 2: Minimum clock frequency i,s a function of temperature and partial bit ti~.es (T, and T2) as shown by 1>f versu~
temperature and Tl, T2 versus temperature curves. The lowest guaranteed clock frequency for any temperature can ,be
attained by, making Tl equal 'to T2. The minimum guaranteed clock frequency: ¢f (min) =-l/(T, + T2) where Tl and T2 do
not exceed the guaranteed maximum.
Note 3: Minimum clock frequency and partial bit time curves are guaranteed by testing at a high temperature point~
Note 4: For'data pattern of 1111000011110000 etc.
Note 5: Maximum frequency, limited by maximum package power dissipation for MM4025, MM4026 and MM4027.
8-9
160
160
ns
ns
[;]I
typical performance characteristics
Typical Minimum Clock
. Frequency ys Temperature
(Note 21
Typical Maximum T 1 and
T2 YS Temperature (Note 21
lOOk
..
g
>-
~ 10k
rlN
OR t ouT ,='200 n
~
~ 1.0k
~
V
~ 100
",.'"
=1==
TIN. TOUT
10
-60
-28
20
60
100
AMBIENT TEMPERATURE
0.01 '--'--'--'---'---'---'--'_'-'''--'
20
60
140
-20
-60
100
140
rei
AMBIENT TEMPERATURE
10
~
82 -.-eu ..
78 vV~'_lUV
.. ' GNU
VGc·· 1lI,5V
74 ",'l.OM".
70 OATp'~
66
62 - t - t-ITA~
58
_f-'
54
.J...r~O°C
50 ~F===
46
42
38
34 .-I-'
-5.0
-5.5
-
1.0
~
IPpw=80ns V¢=-18.5V ~
Voo --5.3V
Vss -GNO -
I
;:
".E0
0
=
TA =+25°C ..
VGG ,,-18.5V
.01
o
10 20 3D 40 50 60 70 80
90
100 (mA)
64
.E-
.E
56
~:
52
~
~
V¢=-18.5V
Yoo '" -S.3V
Vss:: GND
\.
48
g;
r-
DATA:NDt~4
I .....
54
1 52
j
..........
40
50
36
46
32
44
-40
40
TEMPERATURE
80
re)
L
48
120
V
1/
.E-
o
.E 40
r- I -
32
24
-14
-12
-6.0
'I
80
-16
vGG "'-lB.5V
V¢ = -18.5V
voo '" -5.JV
Vss '" GRD
rh=3mHz
4.7
~-
4.6 1 -
~
4.5
>~
~
"~
~
'><"
........
Voo = -5.0V
VGG = -t7.0V
Vr>'" -l1.DV
Vss = GND-
"
"'\
4.4
'\
4.3
4.2
4.1
;1i
4.0
100
¢VW I",)
8·10
-20
Maximum Clock Frequency
vs Temperature
DATA'" Note4
90
-18
V¢ IV)
/
j
~~r--
./
;; 4B
.....
/'" f-"'"
56
I-
ns tVGG '" -lB.5V
¢PW'" 80
z 44
;;:
r-
¢t=3~OMHz
\.
I-'
Power Supply Current vs
Clock Pulse Width 1>PW
58
\
VoD "-5.JV-OATA"Note4
56
Voo (V)
Power Supply Current vs
Temperature
;; 60
~;.:~~z -~:SG"~G'~~!iV r-r-r--
64
I-l_125o~~
.-1- n
I~ f,.-
=
~
68
72
- - T~-~W~ ~
1
~
Power Supply Current
YS CloGk Voltage V 1>
Power Supply Current vs
VOO
Power SupplV Current
vs Data Rate
rc)
110
20
40
60
80
TA =OC
"
100
120
140
.s:
s:
typical performance characteristics (con't)
~
"~
~
..~
....
;5
r--r---,.,---,---,.,----r--,
2c4
.
9.5
~
2.2
.§
....
2.0
~
1.8
~
9.0
t----t--t--f--
¢Ipw '"
80 ns
t----t--t--f-- ~~:~"'G~~5V
8.5
""z
1.6
;;;
1.4
t----t--t--f-- ~:: ~~~~~
8.0
-4.S
T Vpical Data Output Sou rce
Current vS Data Output
Voltage
Tvpical Sink Current us VGG
Maximum Data Rate vs VOO
10.0
,1::0
o
./
./ ./
-+T~~+2IsoC
_ T.
0
I
Q
=v ss -
s.OV +-i~F'-1:--l
'-... / /
/
.'),/
N
U'I
"-. , /
/
'" '"
,/
'-" . / , /
Vss '" +5V
Voo = GNU
,/
V¢I=Vss-14.5V
Vour" O.4V
1/ , /
1.2
cS.O
-S.5
-u
10
14.0
12
Your
VDO(V)
typical applications
Memory Expansion
INPUT lA
M
't ,t
r-----------
INPUT1Ao--;_ _ _.,
INPUT SELECT A
----~
1
I
I
OUTPUT A
INPUT 2A o - - ' - - - - - L . J
6
0----4---.,
INPUT 18
INPUT
SELECT B
OUTPUT S
t2
INPUT 28
0--;-----L....I
I
---'---r---r--.-J
MM5026
130
INDEPENDENT
INPut
VeG
'15
VDD
INPUT2B
TTL/MOS Interface
+5V·5%
r---------
v~---------l
I
I
I
INPUT
B
I
I
L.:?AD _J
I
I
L ____ ~[-:
VeG -12V
8-11
_~[-~[----J
VDO
'h
s:
s:
U'I
o
.",. /
8SoC
I
TA "'+125 C
Voo
N
U'I
......
9~
8
Vss
truth tables
Positive Logic
Input Select A
Logic" 1" == V IH = Logical High Level
LogiC "0"
-:=
Function
Select Input 2A
Select Input lA
1
V 1L ,= Logical Low Level
0
Input Select B
Write/Recirculate
1
0
Function
Function
1
Select Input 2B
Recirculate
Load Data
0
Select Input 1B
switching time waveforms
8ITTIMES
I
BIT 1
I
I
BITl
BITl
!
8tH
)
.,
;,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LJ
I
LJ
I
LJ
I
LJ
I
LJ
I
LJ
I
U-
I
I
I
I
I
I
I
I
I
I
I
I
I
DA~tINFl
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DATA IN
"'"
~DATAINI
1,
2
"1"
"0"
DATA OUT
enters the register at 1>, time, it exits at 1>1 time,
(beginning on 1>", negative going edge and ending
on the succeeding 1>2', negative going edge),
Shown is a simplified illustration of the timing of
a 4-bit multiplexed register showing input output relationships with respect to the clock, If data
timing diagram
"'r--r
,.,-!u~--------
"
CLUCK
II
II
M,~II_
"
ClOCJ(
~_I
iL
:: "
t... ---r--I
:
;;;';1.
~
10%
1--- I
i
-I
1'.....
I
If'
9Q'U
I
I---DATA PERIOD-I
II
II
-[1-"1.,
/VO"
'D%W-
i·
I
--Vo,
I
' :
:
X"------------~~----------r4-----:-----~
\'iNBiT"
IN81l2
!
t ....H __ :
Vo •
:__
_:
;_tpdL
V'H
VlI..
~~;u;-----------------~ll-----------x------~~~VA80VEGNO (V
OUT BIT 1
8-12
OUT BIT 2
DO )
~National
Shift Registers
~ Semiconductor
MM4052/MIVI5052 dual 80 bit static shift register
MM4053/MM5053 dual 100-bit static shift register
general description
The MM4052/MM5052 dual 80-bit and MM4053/
MM5053 dual 100-bit static shift registers are
monolithic integrated circuits utilizingP channel
enhancement mode low threshold technOlogy to
achieve direct bipolar compatibility on the inputs
and outputs. The devices require only a single
phase clock.
.. High frequency operation
• Improved driv,e capability
push-pull outputs
applications
• Static data buffer
features
• Bipolar compatibility
1.6 MHz guarantee
• Single phase clock
• Serial memory storage
+5, -12V operation
No pull-up or pull·
down resistors needed
• Printer memory
• Telemetry systems and data sampling
connection diagram
Metal Can Pa.kage
Ne
V.
TOP VIEW
Order Number MM4052H, MM5052H,
MM4053H or MM5053H
See Package 24
typical application
..v
V~
r--,
L_l_J
I
V.
I 1
I
I •
I
VGG
ANY annTL DEVICE
ANY DTLITTl DEVICE
8·13
absolute maximum ratings
Voltage @ Any Pin
Operating Temperature Range
MM4052/MM4053
MM5052/MM5053
Storage Temperature Range
Vss +O.3V to Vss -22V
_55°C to +85·C (Ambient)
-55°C to+125°C (Case)
O°C to +70°C (Ambient)
_65°C to +150·C
300°C
Lead Temperature (Soldering, 10 sec)
electrical characteristics
T A within operating temperature range, Vss
PARAMETER
= +5.0V
±5% and VGG
VSS - 2.0
Vss - 18.5
Data Input Leakage
Y,N = -20V, TA = 25°C
All other pins GND
Data I nput Capacitance
Y,N = O.OV, f = 1.0 MHz
All other pins GND
Clock Input Levels
Logical High Lev\.1 (Vq,H )
Logical Low Level (Vq, ~ !
Y'N = -20V, TA = 25°C
All other pins GN 0
Clock Input Capacitance
Y'N = O.OV, f = 1.0 MHz
All other pins GND
(V OH )
(V o~ )
(V OH )
(Vo~)
Power Supply Current
(lGG) MM40S2/MMS052
.01
3.0
Vss - 1.5
Vss - 18.5
Clock Input Leakage
ISOURCE = -500 IlA
ISINK = 1.6mA
ISOURCE =-10IlA
ISINK = lallA
Clock Frequency
(q,,)
Clock Pulse Width (q,pw)
Clock Transition Times
Risetime (q,t,)
Falltime (q,t,)
UNITS
Vss - 4.2
V
V
0.5
IlA
5.0
pF
Vss
Vss -IU
V
V
1:0
IlA
22
28
pF
2.4V
4.8
-3.0
Vss - 1.0
Vss
Vss - 12.0
Vss
0.4
Vss
Vss - 7.0
V
V
V
V
9.S
12:S
mA
12.0
16.0
rnA
200
200
300
300
ns
ns
TA =2SoC
q" = 1.6 MHz
VGG = Vss - 17V
Vq,~ = Vss - 17V
(lGG) MM40S3/MMSOS3
Propagation Delays from Clock
Propagation Delay to a High (tpdH )
Propagation Delay to a Low (tpd~)
MAX
TYP
MIN
CONDITIONS
Data Input L""els
Logical High Level (V,H)
Logical Low Level (V I~)
Data Output Levels
Logical High Level
Logical Low Level
Logical High Level
Logical Low Level
= -12V ±10%, unless otherwise specified.
See waveform
See waveform
See operating curves
a
1.6
MHz
See operating curves
q,t, .. q,pw+ q,t, :<::: 10.Slls
0.25
10
lIS
S
S
JlS
JlS
q,t, + q,pw + q,t,:<::: 10.5 JlS
q,t, + q,pw + q,t,:<::: 10.S JlS
Data Input Setup Time (td.)
80
SO
Data I nput Hold Time (tdh)
20
a
8-14
ns
. ns
s:
s:.j:;ro.
guaranteed performance characteristics
1.0 MHz Operating Curve
500
!
lOCI
'"
~
~4-~-4--t-
__-+~~
!
400
600
i
300
400
~:;
200
~
~
~
'"'"
~
ZOO
~4--+--~~-+--~~~
14
16
Vss - VG(.i (VI
~
..-
I
;;i
I
::....
1.4
~
1.2
....
'"
1.0
:E
.8
~
I
;0:
MIN¢pw
I
V1L
V1H
'"
'"
-
n.BV
l.GV
¢i,"'¢lt '" 20 ItS
E
rI-r-
TA RANGE'" _55°t to +8SoC -
100
N
.......
~ 2.2
,; 2.0
~AxL
r-.....
:~~~6D:HZ
o
20
"
.....
i.-
o(J1
Maximum Data' Input 'Low
I.,evel YS Supply Voltage
1.6 MHz Operating Curve
."
==
s:
s:
1.8
(J1
o(J1
1.6
N
s:
s:
'"
.j:;ro.
;;(
12
16
14
18
20
'"'"
12
14
16
18
20
5.0
.......
Data Output Sink Current
Data Output Voltage
s:
s:
10.0
,--,.;;:-.,---,--r---r---.
8.0
k::--I--""..q,--'""",.-+-::--,=~
.10
Vss = s.nv
4'
I
4.0
J.O
I---~-I--+--+---h"'"
1---1--I--+~'f-7'T-7'1
~
'"g;
2.0 1----1--~_F:ifC 7"~-+_:__;
....5l
~
1
'"
oS
i
Jl
'"~
1--1---;---+--+--"'''''':''''1
4.0
~co;:'
1--1---;---+---+----1--1
2.0
VGO '" -12V
Vss l: 5.0V
co
5.0
4.0
J.O
2.0
1.0
0.0
ii
~ 6.0
B
;;
1.0 ~---1~>-f'--+--+---I----1
;::
5.0
-1.0
4.0
J.O
2.0
1.0
0.0
-1.0
~
'"
~
'"
w
f/Jrw"" 2511n'
TA
.08
"
+25"'C
tPf ::: 1.0 MHz
DATA'" 1-0-1-0
-
.06
.04
.02
V'
/'
,/
o
12
16
14
18
20
Vss - VGG IV)
VOUT (V)
VOUT (VI
o
U1
Vss ~ 5.0V
VaG'" -12V
.§
U1
Power Supply Current
YS
,-~--~--.,...--r----r---'
Power Supply Current
.10
11111111
I
.08
l-
i; ~I~~~oc I,
"
.06
l-
TA - +25"'C
-"
w
.04
~
.02
~
~
oS
0
'"
11111111
l- TA .~5oc
1-lIl1ll!
11111111
11111111
"
o
10
U1
w
Vss - VGG (V)
typical performance characteristics
Data Output Source Current
YS Data Output Voltage
o
/
I
I Vo• - -12V
j'L
100
I I ~:T~:~~-I-O
II .... ·2500$
1000
10.000
OPERATING FREQUENCY (kHd
switching time waveforms
ac test circuit
DATA INPUT
!i.DV
4K
DATA OUTPUT
8-15
o-...........- ..-+o.......-~'--..+-.........-,
~National
Shift Registers
~ Semiconductor
MM5054 dual 64172/S0-bit static shift register
general description
The MM5054 dual 80-bit static shift register is a
monolithic MOS integrated circuit utilizing silicon
gate low threshold technology to achieve complete
bipolar compatibility. The device has input and
output taps that also provide register lengths of
64 or 72 bi ts.
The single phase bipolar compatible clock lines
may be driven by any conventional DTL or TTL
circuit. The registers may be operated as a dual
register by connecting the clock Iines A and B
together, or as, two independent registers. Two
clock control lines provide independent logical
control of the shift register clock lines.
High freq. operation
• Single phase clock
•
•
DC to 3.0 MHz typ
DTLlTTL compatible
on·chip clock driver
Low clock line capacitance
• System flexibility
8.0 pF max
Split clock or common
clock operation. Logical
control of clock lines
<600 /1W/bit typ
Low power dissipation
applications
features
•
+5.0V, -12V
• Standard supplies
•
Complete bipolar compatipility
DTL/TTL
input/output and
clock line compatibility
without additional
components
•
•
•
•
Teletype data buffers
Printer memory - 80, 128, 136, 144 bit lengths
Telemetry and data sampling systems
Serial memory storage
logic diagram
OATA
INPUT
DATA
OUTPUT
1.15
3,13
DATA
INPUT
2,140---------1
4,12
CLOCK
I.'~-_--l"-,
CLOCK
CONTAOl
6,11)
TIle unused data inputs and clock controls should be connected to Vss to el)sure proper operation.
Logic diagram shows 1/2 of the unit
.connection diagram
truth table
Dual-In-Line Package
INPUT·A-12!80 1
16 Voo
INPUI-A-64/72 2
15 INPUT-B-12IBII
OUTPUT-A-72/80 J
14 lNPUT-B-64172
OUTPUT-A-64172 4
13 OUTPUT-B-72IBD
Ne ,
Positive Logic
12 OUlPUT·B-64172
CLOCK CONTROL A 6
10 CLOCK CONTROL 8
CLOCK A 1
v~
9
8
CLOCK B
TOP VIEW
Order Number MM5054D
See Package 3
Order Number MM5054N
See,Package 15
8·16
CLOCK
CONTROL
CLOCK
Low
Inhibited
High
Active
absolute maximum ratings
Vss + 0:3V to Vss - 20V
O°C to +70°C
-65°C to +150°C
300°C
600 mW@25°C
Voltage at Any Pin
Operating Ambient Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Power Dissi pation
dc electrical characteristics
TA within operating range, VGG = -12V ±10%, Voo = GND, Vss = 5.0V ±5%, unless otherwise noted.
CONDITIONS
PARAMETER
MIN
TVP
MAX
UNITS
Data, Clock Control. and Clock Levels
Vss - 4.2
V1N
Input Leakages
Vss +0.3
Vss - 1.5
Logical High Level (V IH)
Logical Low Level' (V1Ll
::::
lOV, TA ;;- 25°C
V
V
0.5
~A
All Other Pins GNO
Data Ir;lput Capacitanc~
V 1N
= av, f == 1.0 MHz
All Other Pins GND INote 11
4.5
6.0
pF
Clock and Clock Control
Capacitance
V'N=OV.f=I.0MHz
.INote 11
6.0
80
pF
Data Output Levels
(Figure 1)
0.15
Vss
0.4
V
V
7.0
5.0
10
8.0
mA
mA
Logical High Level (V OH )
Logical Low Level (Vad
Power Supply Current
(lGG
+ I Do = Iss)
IGG
100
'SOURCE'" -0,5 mA
'SINK:::: 1.6 rnA
2.4
9, = 1.5 MHz. T A = 25°C
Vss = 5.0V. Voo = GNO
V GG =-12V
ac electrical characteristics
T A within operating range, VGG =-12V ±10%, Voo = GND, Vss = 5.0V ±5%, unless otherwise noted.
PARAMETER
Clock Frequency (¢tl
9t,; ¢t,
CONDITIONS
MIN
TVP
MAX
UNITS
s: 10 nslNote 21
DC
3.0
1.5
MHz
0.25
0.180
10
Clock Pulsewidth ltf = 10 ns
60
30
n,
Data Input Hold Time Itdh I
(Figure 11 -
ill
3.0
.
2.0
'"~
"z
M1No..w
I
100
o1It,"'dl1f'" lOBS
100
15.5
II I
Mlx'o2
500
15
Typical Data Output Sink
Current vs V GG
900
600
+70'C-
:::::::~
DoC 1""""
1fJt."'rpt f=10ns
800
e
~
ViL = a.BV
V1H "" 3.0V
~
~ r- r::::: ::3=
Vss - Vaa (VI
1000
Vss =5.0.
VDO =GND
%
200
I-
10M
1.0M
Operating Curve
%
~
2.0
I,.>f(Hz)
]:
~
~
lOOk
(Hz)
t-t-
~
;
-1
VGG '" -12V
10k
]
e
111111
,~~.\~~
Typical 2.2 MHz
!!l
~
DATA =
Vss =+5.0V
VDD =- GNO
1.0
VOD" GND
3.0
llLllJ
4.0
10M
I
~
+lDoC
t-
Operating Curve
400
l-
r-
O'C
6.0
5.0
vss".+§·ov
111111
3.0
2.0
=-12.0V
1.0M
III
III
vsVGG
16
11
18
1.0
'---'--'-'--'--!---'---'----'
12
13
14
Vss - Vaa (VI
switching time waveforms
15
16
17
IB
19
Vss - VaG (VI
ac test circuit
=---.. . .
...
I·
CLOCK
A""
=O-I-'-i ¢tf :::; 10 ns (See ac Test Circuit)
510 ns (Note
5)
10 ns (See ac Test Circuit)
0.400
0.400
6.5
10.5
9.0
15.5
rnA
rnA
13
15
18
20
rnA
mA
2.2
1.0
MHz
0.280
0.160
10
de
ps
ps
Data Input Setup Time (td $)
260
ns
Data Input Hold rime (t d H)
120
ns
Recirculate Setup Time (tds)
260
ns
120
ns
Recirculate Hold Time (tdH)
t"tf5'10ns
For Load Conditions See ac Test eire'uit
Data Output Propagation Delay
Delay to. High Level (tpd H)
Delay to. Low Level (tpdd
350
350
8-20
700
700
ns
ns
electrical characteristics (con't) (MM5055, MM5056, MM5057) ,.
TA =O°C to +70°C, Vss = 5.0V ±5%, VGG =-12V ±5%, Voo =OV, unless otherwise noted.
PARAMETER
Data. Recirculate
an~
CONDITIONS
MIN
TYP
MAX
UNITS
Vss + 0.3
Vss - 4.2
v
Clock, Input Levels
Logical High L~vel (V 1H )
Vss - 1.5
Vss -15
Logical Low Level (V ILl
= 25°C
Data, Recirculate and Clock Input
VIN =-10V.T A
Leakage
All Other Pins GNO
Data Input Capacitance
VIN =OV,f=l MHz,
V
0.Q1
0.5
~A
4.5
6.0
pF
All Other Pins GND (Note 2)
Recirculate Input Capacitance
VIN = OV, f = 1 MHz,
All Other Pins GND (Note 2)
3.0
6.0
pF
Clock Capacitance
VIN =OV,f= 1 MHz.
10
14
pF
All Other Pins GND (Note 2)
Data Output Levels
Logical High Level (V OH )
Logical Lo\(" LevellVod
= -0.5 rnA
= 1.6 rnA
'SOURCE
2.4
Vss
v
ISINK
Voo
0.4
V·
T A = 25°C, VGG = -12V. Vss = 5.0V
Voo = OV; pw = 230 ns
Datao 0·1·0·1 •••
Power Supply Current
~,SO.1
100 (Note 4)
MHz
6.5
<1>, S?.2 MHz
13
9.0
19
rnA
rnA
~,SO.1
13
15
18
20
rnA
rnA
3.0
1.5
MHz
100
de
MHz
<1>, S2.2 MHz
tPtf , tPtf
Clock Frequency (tPt)
~ 10 ns (Note 5)
Clock Pulse Width
!!m}
IN
IlS
ns
30
ns
150
ns
30
ns
Delay to High Level (~dH)
200
200
Delay to Low Level (tpdd
300
300
ns
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guar,anteed. Except
for "Operating Temperature Range" they ,are not meant to imply thi'lt the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Positive true logic notation is used: Logic "1" = most positive voltage level; Logic "0"= most negative voltage level.
Note 4: Typical value, apply for VSS ~ 5.0V, VGG ~ -12V, VOO
8·25
= OV, and T A = 25°C.
[;)II
typical performance characteristics
Typical Power Supply Current
vs Temperature
50
a:
3:~
40
I
....
~z
"w
!'!a:
~a:
>:0
.... u
'>
~~
jCIJ
3D
20
10
0
50
I I _.
I ,I
-..J..
r-t-:.""
0.5
~
Typical Power Supply Current
vs Supply Voltage
Qf"'1.5MHz
¢pw =
a:
.r-
333 ns
Vss '" +5.0V, VGG = -12V
Voo =- OV
-
TA ~ 25' Ct""'''
-
'>
20
Jcn
10
~~
I
I
r-:
r-
14
15
16
TA - AM81ENTTEMPERATURE rCI
]
"....0
1000
900
i
800
~
700
w
!
~
'"~
>
....
,
!
600
500
G
17
18
vsVGG
Vss' 5.0V
VGG '" -12V
]
I I I
I
I I
I
I I
10
~
~
~
~
r--
~
liAr)
I I
1-.1
300
200
300
~
l-
200
~,
I
600
OUTPUT LOAD'" 1 TTL GATE
I I
OJ,
I I
~
~
r- t-
IDO
-11.8
::::
3.0
-.1J
~
"'
IMIN)
",
1.0
.x
-12
-12.2
r-- i"--
r~~
-12.4
."". 50%
VDD "'-12V
Vss '" 5.0Y
Voo =DV
0
10 20 30 40 50 60 10 80 90 100
TA lOCI
VGG {V)
T A - AMBIENT TEMPERATURE (OC)
r-t-
OUTPUT LOAD· 1 TTL GATE j - r -
"
I
-II .•
4.0
2.0
I I
0
.1020 30.40 50 60 70 80 90 100
:::
IrAi l
10 20 30 40 50 60 70 80 90 100
switching time waveforms
"N
:Y-'-l
__ t08 _
V'H
,
r---''''\
STREAM SELECT
VO,
DATA OUTPUT
Voc
\
} \
,
1--'0'- !-'OH-
II
\
V"
V"
tOH_
\
DATA INPUT
V'H
_
¢;;;
II
j
I
\
r---"'-'-""-I
--tsH--
"\
II
J
-.0'----1
~---
I
s:
NOTE 1; TIMES MEASURED AT 50% POINTS WITH 1" tt
10 ns.
NOTE 2: fOR DC STORAGE CLOCK MUST REMAIN AT VL'
8-26
Voo = OV
'" -12.6V
5.0
800
200
r-
Typical Maximum Frequency
vs Ambient Temperature
I I
400
Vss • 5.25
VGG
~
Vss =5.0V
Voo =OV
TA '" 25°C
5
IMI~I
100
~
0
-.1J
Of:: 1,5 MHz
w
OUTPUT LOAO' 1 TIL INPUT,_
t-
1000
:;"
¢t"'1.5MHz
r,/Ipw;;; J33 ns
DAtA IN '" 1010 ...
TA - AM81ENTTEMPERATURE ("CI
Typical Clock Pulse Width
Voo '" OV
~
400
Vss - VGG (V)
vs Ambient Temperature
,,'1.5MH,
OUTPUT LOAD' 1 TIL INPUT
600
500
19
r-- f-
700
ei
a:
c- r-
Typical Clock Pulse Width
400
0
'i
0
'0 20 30 40 50 60 70 80 90 100
~"
r- r-
I
I-~
_L1
"
>=
c
I
Sl'ECIFIEO
OPERAHNGRMGE
~a:
~
.5 800
'''
~ r:r:
3D
>:0
.... u
§' 900
r-
DATA IN = 10]0
Voo =0 ....
5~
_a:
-+- c-
OUTPUT LOAD· 1 TTL 'NPUT _
OATA' 'DID ...
-tt'i_-t
40
~;(
~,..s
1ODD
I
~,U.T~~TM~~~O' 1 TTL INPUT
,_=333",
Guaranteed Power Consumption
vs Temperature
t
·~National
a
Shift Registers
Semicqnduclor
MM5060 dual 144-bit mask programmable
static shift register
general description
The MM50S0 is a monolithic dual 144·bitstatic
shift register/accumulator utilizi!1g a silicon gate
low threshold P·channel enhancement mode tech'
nology to achieve complete bipolar compatibility.
The device can be programmed by metal mask
option to custom lengths from 125 to 144·bits
in ·one bit increments.
register/accumulator in an 8·lead cavity dual-in·
line package. Pattern. codes are assigned by· Na·
tional upon entry of order.
features
• Complete bipolar compatibility - input/output
and clock input completely DTL/TTL compati·
ble without additional components
Standard Lengths:
MM50S0AA
Dual
MM50S0AB
Dual
MM50S0AC
Dual
MM5060AD
Dual
• Standard Supplies
128·Bit Shift Register/Accumulator
•
132·Bit Shift. Register/Accumulator
+5V. -12V
High frequency operation typical
DC to 3;0 MHz
• Single phase clock - DTL/TTL compatible on
chip clock
133·Bit Shift Register/Accumulator
•
144·Bit Shift Register/Accumulator
S.O pF max.
Low clock line capacitance
Custom Lengths:
applications
The programmed shift registers are assigned a let1:er
code .for each option. These are designated by a
pair of letters after the number code but before
the package designation such as MM50S0AD/D
which is a O°C to +70°C dual 144·bit shift
• Printer rnemory 144·bits per line
any length from 125 to
• Telemetry systems and data sampling
• Serial memory storage
logic and connection diagrams
Dual·1 R·Line Package
LOAD
1
Vss
CONTROL
INZ
OUTI
CON~~~~ 0-+-----1-1-.....
INI o--=+---~HL.....
¢INo--=+---~I--------~
OIN
IN Z o--+-----1Hr.......
TDPVIEW
O~der Number MM5060AAlD.
MM506DAB/D. MM5060AC/D.
MM5060AD/D or MM5060XX/D
See Package 1
OnierNumber MM5060AAlN.
MM5060AB/N. MM5060AC/N.
MM5060AD/N or MM5060XX/N
See Package 12
truth table
LOAD CONTROL
INPUT
o
0
1
Recirculate
Recirculate
o
"0" is written
o
FUNCTION
"'" is written
8·27
absolute maximum ratings
+0.3V to -20V
Data and Clock Input Voltages and Supply
Voltages with respect to Vss
Power Dissipation
Operating Temperature Range
MM5060
Storage Temperature
Lead Temperature (Soldering, .10 sec)
600 mW
@
T A : 25°C
O°C to +70 o C (Ambient)
_65°C to +150°C
300°C
electrical characteristics
TA within specified operating temperature range, Vss : 5.0V ±5%, VGG -12.0V ±5%, unless otherwise specified.
CHARACTERISTICS
CONDITIONS
MIN
TVP
MAX
UNITS
Vss + 0.3
Vss - 4.2
V
Data Input' Levels
Logical High Level (V IH )
Logical Low Level (V IL )
Vss - 1.5
Vss -10.0
Data Input Leakage
V IN = -10V, TA = 25°C
All Other Pins GND
0.Q1
0.5
/.IA
Data Input Capacitance
V IN = O.OV, f = 1 MHz
All Other Pins GND
(Note 1)
3.0
5.0
pF
Vss + O.~
Vss - 4.2
V
V
Load Control Input Levels
Logical High Leval (V H)
Logical Low Level (Ve!
Vss -1.5
Vss - 10.0
Load Control Input Leakage
V IN = -10V, TA = 25°C
All Other Pins GND
0.01
0.5
/.IA
Load Control Input Capacitance
VIN = O.OV. f = 1 MHz
All Other Pins GND
(Note 1)
3.0
5.0
pF
Vss + 0.3
Vss - 4.2
V
V
~Iock
Input Levels
Logical High level (VIjJH)
V" -1.5
V's -10.0
Logical Low. Level (V. L)
Clock Input Leakage
V. =-10.0V. TA = 25°C
All Other Pins GND
0.Q1
0.5
/.IA
Clock Input Capacitance
V. = O.OV, f = 1 MHz
All Other Pins GND
(Note II
3.5
6.0
pF
0.4
V
V
V
24.0
25.0
26.0
mA
mA
mA
1.5
MHz
Data Output Levels TTL Load
Logical High Level (VoHI
Logical High Level MOS Load (VoHI
Logical Low Level (Voe!
'SOURCE ==
-0.5 rnA
-0.01 '.1lA
ISINK = 1.6 mA
'SOURCE =
3.0
4.0
TA = 25°C, VGG =-12V
¢pw = 300 ns, Vss "" +5.0V
Data = 0-1-0-1
0.01 MHz S ¢, S 0.1 MHz
¢, = 1.0 MHz
¢, = 1.5 MHz
Power Supply Current (lGGI
Clock Frequency (¢,I
t, = t,
Clock Pulsewidth (¢pw I
(¢pwl
¢t, = ",t,
3.5
4.5
20.0
21.0
22.0
= 10 ns. T A = 25'C
DC
= 10 ns. T A = 25°C
0.300
0.200
3.0
0.100
Clock Pulse Transition (,pt n tPtrJ
100
DC
/.Is
/.IS
1
/.IS
Data Input Setup Time (..,I
TA "" 25°C. t r, tf
= 10 ns
70
ns
Data Input Hold Time ("h)
TA '"" 2SoC. t r • tf
= 10 ns
50
ns
Load Control Setup (td.)
TA = 25°C, t p tt = 10 ns
70
ns
Load Control Hold ("h I
TA = 25°C, t r, tf'" 10 ns
50
ns
Data Output Propagation Delay from
Delay to High Level (tpdH)
tP in
TA = 25°C, t r• tf'" 10 ns
250
250
Delay to Low Level (t.dd
Note 1; Capacitance i5 guaranteed by periodic testing.
8·28
350
350
ns
ns
s::
3C
UI
o
en
o
typical performance characteristics
Guaranteed 1.5 MHz
Operating Curve
Guaranteed Input Voltage
Levels vs 'Supply Voltage
TypicallGG .s Clock
Frequency Under TTL Lolld
2& r-~~~~~~rTrrrrm
TA o.H"C
V~~.
500
Vas = +5.(1
UII
VOH"UV
o>t. ·~·t'lI
Va·5.I11
I
o."ILNd ••II:~r
I'"'"
~
,
,.'NPW
I
,
II
I
MINIMUM .,~PW
,
I
I.
T 1,
G~ARANTEE~t'"=POWER SUPPLY LIMITS
I
200
_15.0
16 L-.L.J..WlUI-.J..J..L.UJ.W.....J....L.J.I.I.I.W
-16.0
-17.0
-18.0
-1&.0
-1 •.0
-17.0
Typical Power Supply Current
vs Voltage Under TTL Load
1.0
Va
6.0
23 r-+--r-t--r-+--r-t~
15.0
...
ffi
4.0
~
3.0
~
r";~
TA = O'C
TA~.J5't±t
I I
~~
TA =+10'C
1.0
-11.0
-11.5
-18:0
V.. - V•• (VI
+4.0
+2.0
-2.0
-4.0
OUTPUT VOLTAGE (V)
v..
V"
,.
18MHz
4.0
Vss
1 3.0 R:
5 2.5
'"~ 2.0
~
1.5
"'"~
1.0
'= +5.0V
12.0V
VaG ..
3.5
K.TA =O'C
~
TA ""+25°C
I
i'l - T I - +:O'C''''''
AI
I--
0.5
switching time waveforms
,,,
1 MHz
. Typical Output Source
Current vs Output Voltage
= +5.0V
VaG = -12.0V
'"~ 2.0
-16.5
100kHz
.,(MHz)
Typical Output Sink Current
vs Output Voltage
1-+--1-+--+-1--+--1--1
-1&,0
10kHz
Yss - VaG (VI
Vss - VaG (V)
24
D.,.
I
MAXIMUM
300
VGG '" -12.0
~:o: 300ns
= 1-0-1"0
24
I
vM
DATA
V"
v.
LOAD
CONTROL
V,
Vo.
UATA
OUTPUT
V••
Note: DC ,storage is Icwmplished during ¢low time.
8-29
-6.0
o
o
1.0
2.0
3.0
4.0
OUTPUT VOL TAGE (V)
S;O
~National
Shift Registers
~ Semiconductor
MM5061 quad 100-bit static shift register
general description
The MM5061 quad 100-bit static shift register is a
MOS monolithic integrated circuit using silicon
• gate technology to ach'ieve bipolar compatibility.
It' has a guaranteed operating frequency of 1.5
MHz and an on-chip clock generator.
•
Low clock capacitance
•
•
•
Operates from +5V. GND. and -12V
Configuration
Quad 100-bit
Internal recirculate
10 typo 14 max,
applications
features
•
•
•
•
• Guaranteed 1.5 M Hz operation
• Single TTL compatible clock on chip clock
generator
CRT displays
Terminals
Disk and drum replacements
Buffer memory
logic and connection diagrams
Dual-I n-Line Package
RECIRCULATE
..!
U
INPUTA....!
.,...!
-:::~;::
~ OUTPUlA
t1!.
OUTPUT B..!
INPUTB
~OUTPUTC
IIfPUTe..!
N, -!
~ INPUT 0
~UTPUT • ...?
DATA
INPUT
tlivoo
t-!!- NC
t-!2- VaG
Vss...!
r!-<>'N
TDPVIEW
Order Number MM5061D
See Package 3
Order Number MM5061N
Se. Package 15
test circuit
truth table
..v
RECIRCULATE
CONTROL
4K
FUNCTION
Data Recirculates
o
8-30
Register Accepts
Input Data
absolute maximum ratings
(Note 1)
Data and Clock Input Voltages and
Supply Voltages with Respect to Vss
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
+O.3V to -20V
600 mW @ T A = 25°C
oOe to +70 o e
-65°e to +160o e
300°C
electrical characteristics
T A within operating temperature range, Vss :: +5V ±5%,. V GG = -12V '± 1 0%, unless otherwise specified.
PARAMETER
CONDITIONS
Data I nput Level
Logical High Level (V ,H )
Logical Low ,Level (V ,L )
MIN
TYP
Vss - 1.5
Vss - 10
MAX
UNITS
Vss + 0.3
Vss -4.2
V
V
Data I nput Leakage
V ,N " -10.0V, T A " 2SoC,
All Other Pins GND
0.01
0.5
/1A
Data I nput Capacitance
(Note 21
V ,N " O.OV. f " 1 MHz.
All Other P;ns GND
4.5
6.0
pF
Recirculate Input Levels
Log;c.1 H;gh Level (VHI
Logical Low Level (V d
Vss - 1.5
10
Vss + 0.3
Vss - 4.2
Vss
V
V
Recirculate Input Leakage
V ,N " 10.OV. T A " 25°C.
All Other Pins GND
am
0.5
/1A
Recircul,ate Input Capacitance
V ,N " O.DV. f " 1 MHz.
All Other Pins GND
3.0
6.0
pF
Clock Input' Levels
Logical High Level (V OH )
Vss - 1.0
Vss - 10.0
Logical Low Level (VOL)
Vo" -10.0V, T A " 25°C.
All Other P;ns GND
Clock Input Leakage
001
Clock Capacitance (Note 2)
10.0
Data Output Levels
Logical High Level (V OH )
Logical Low Level (Vod
'SOURCE
Power Supply Current 'I GG )
TA
2.85
-3.0 rnA
1.6 rnA
ISINK ;;-
0::
V
V
13.0
lS.0
18.0
20.0
rnA
rnA
1.5
MHz
10.0
/1S
/1s
MHz
""
3.0
, <;0.1 MHz
¢t, " , <;2.2
en
..
>
o
E
CIl
~
Standard
Memories
National's standard product line offers you a
selection of reliable memories for a wide range
of OEM and end-user applications. Including
both "add-on" and "add-in" versions for specific
minicomputers and micro-processors, the standard product line features memories designed
for core memory card replacement, alphanumeric displays and general use in communications, instrumentation, intelligent terminals,
and many other applications These memory
products are described on the following pages.
Custom
Memories
If the memory you need isn't presently available
in our standard line, our memory systems team
will design one to meet your specifications. After
your first prototypes are built and fully tested,
you can either have National build your memory
systems or build them in your own plant with a
licensing agreement: National will provide
the first systems and the design, and you may
use National as an alternate source.
Reliability
National has an outstanding reputation for reliability, and our memory systems are no exception.
Every National memory is thoroughly inspected,
"burned in" and tested at both the component
and system levels before shipment.
State-of-the-A rt
Design
As improved memory technology becomes
available, National memories are automatically
design-uPdated. Custom memories are designupdated, with customer approval, with no interruption in production. This assures you of a
memory system that is constantly competitive in
cost and performance, without additional capital
investment or design cost.
9-2
NS3-1
Bulk .Storage Memory
s:
CD
3
...
0
<
A compact, 256k byte random access memory
system with .integral power supply and cooling in
a standard 5.25" x 19" rackcmountable enclosure. The NS3-1 combines fully engineered reliability with designed-in flexibility. It is highly cost·
effective in a wide range of applications, including graphics terminals, PBX, mini- and microcomputers, time-share systems, process control,
automatic testers, and medical analyzers.
High Speed
Core-Compatible
Timing
Error Check
and Correction
Parity
Byte Control
Modular Memory.
Custom Interface
Refresh Control
Data Bus
Features
280 ns access, 430 ns read or write cycle
650 ns cycle
Two or four bytes, optional
Checking and/or generation
One, two, or four byte control
64k byte modules, 256k bytes max.
For individual processors
Synchronous or asynchronous
Unidirectional or bidirectional
Modular Design
The NS3-1 is part ot National's growing NS3
family of modular bulk storage systems. These
systems are slated for continuous technological
update and development of additional compatible modules to provide enhanced performance, capacity and economy.
Capacity
Operating Modes
Cycle Times:
standard
core-compatible
EGG option
Interface
Power
Dimensions
Temperature
9-3
Specifications
256k x 11 bit bytes maximum
1, 2, or 4 byte words
Read, Write, Read/Modify/Write;
Partial-Store with ECC option
280 ns access, 430 ns cycle,
650 ns split cycle
280 ns access, 650 ns cycle,
750 ns split cycle
425 ns access, 650 ns cycle,
795 ns split cycle
TIL-compatible
Integral power supply, 115/208 VAC,
50/60 Hz
Standard 19"W x 22.5"L x 5.25"H
0-50°C, operating
en
CIJ
~
o
E
Q)
::?!
Custom Interface CardFor specially designed interface; breadboard available for
customer design
Special Features CardOffers special
options, including ECC,
4-byte word structure,
and others
Timing and Control CardInCludes master control, parity and refresh
circuits control logic
Memory Storage CardsUp to four Memory
cards, each with
64k bytes, various word
structures optional
Enclosure & Power UnitStandard 5.25" x 19"
rack-mountable chassis
with integral power
supply and cooling.
Table-top cabinet and
interface cables
optional
9-4
NS11
Memory Series32K x18 Bits
s:
CD
3
o
-<
en
en
...>
o
E
Q)
:E
A double-density random access memory card
that is fully hardware and software compatible
with LSI11 and PDP11/03 processors. The
NS11/03 is a direct plug-in replacement for
four 4k·cards.
Features
Kigh Speed
Double-Density
Compatibility
Expandable
Low Power
High Reliability
400 ns access, 1100 ns full cycle
16k card replaces four 4k cards
Plug-in replacement; can be intermixed with
DEC memory cards
To24k or 32k
11.5 W/card
Specifications
Capacity:
basic card
option
Address
Operating Modes
Cycle Times:
access
cycle
Interface
Power
Dimensions
Temperature
9-6
16k x 16 bits
Bk x 16 bits,. by depopulation
Jumper-selectfible in 4k blocks
Read, Write, Read/Modify/Write, Refresh
400 ns
1100 ns for Read-Modify-Write,
BOO ns for Read, Write or Refresh
Hardware and software compatible with
PDP11/03 series processors
+5Vat 1.1A; +12V at 0.5A
10.44"W x B.9"L
0-70°C.
Memory Card 16K x 17 Bits
NS21
s:
(1)
3
o
-<
en
....
(1)
<(/I
3
en
A double-density random access memory card for
replacingtwoBkcards inthe Hewlett-Packard 21 MX
family of computers. Also for general use, the NS21
features easy flexibility for large or small systems.
Use with HP21MX or NS21 Control Card.
Features
335 ns access, 650 ns cycle
16k card replaces two 8k cards
Plug-in replacement; can be intermixed with HP
memory/control cards
Expandable
to 192kwords
DIP-Switch Address Select
Extended Warranty 1 year
High Speed
Double-Density
Com pati bi lity
Specifications
Capacity:
basic card
option
Address
Operating Modes
Access and Cycle
access
16k x 17 bits, expandable to 192k
8k x 17 bits, expanaable to 12Bk
DIP-switch-selectable in 4k blocks
Read, Write, Refresh
Times:
335 ns from .address
290 ns from clock
full cycle 650 ns
Standard TTL, hardware and software
Interface
compatible with HP21MX series processors
±5V, ±12.4V; all voltages ±5%
Power
7. 75"W x B.92"L
Dimensions
0-70°C, operating
Temperature
9-7
NS32
Memory Card 32K x 16 Bits
A random access memory card designed forvideographics, computer language storage and other
cyclic applications. Special features include prog ram mabie add ress formats, byte select, on- board
refresh, and a high speed write-mask mode for
video-compatible read/!Jpdate cycles.
High Speed
Write-Mask Mode
Programmable
Format
On-Board Refresh
Simple Interface
Low Power
Features
380 ns Read or Write cycle
Writes only "zeros" or "ones"
Selects 32k x 16 or 16k x 32 bit
Synchronous.
Self-contained, TTL-compatible, standard NS3
card size
35 W/card
Specifications
32k x 16, 16k x 32 (16 bits write) programmable
Read, Write or Masked Write (copies only "zeros" or
only "ones" into memory)
Access and Cycle Times:
read or write 340 ns access, 380 ns cycle
Interface
TTL-compatible
Power
+12V, +5V, -5V (optional +15V, +5V, -5V)
11.8"W x 15.4"L
Dimensions
Temperature
0-50°C, operating
Capacity
Operating Modes
9-8
· NS400:-N
Memory Cards 4K x 8, 9 or 10 Bits .
3:
CD
g
-<
C/)
en
Memory Card,s 4K x 8, 9 or 10 Bits
NS400-C
series
...>
o
E
C1l
::E
A selection of compact, self-contained 4k memory cards that use static CMOS RAM's to eliminate refresh and minimize power usage in battery
back-up applications. Choice of high speed,
low power NS 400-CL version or ultra-low power
NS 400-CC version. Simple interfacing, modular flexibility.
High Speed
Static RAM's
Simple Interface
Expandable
Compact
Ultra-Low Power
Wide Voltage
Range
Features
400 or 575 ns access time
No clocks or refresh circuits
Single +5V supply
4k x 8, 9 or 10 bits, expandable to 32k
3.93" x 6.3" cards
Less than 450 mW operating, 5 mW
standby (-CC)
3.5 to 5.5V (400-CC)
Specifications
Capacity:
basic card
system
Address
Operating Modes
Cycle Times:
NS400-CL
NS400-CC
4k x 8, 9 or 10 bits, optional
Expandable to 32k in 4k increments
Jumper-selectable in 4k blocks
Read or Write
400 ns access, 500 ns cycle
575 ns access, 700 ns cycle
Power
NS400-CL
NS400-CC
Dimensions
Temperature
9-10
+5V; 1.5W, max.
+3.5V to 5.5V; 0.5W, max.
3.93"W x 6.3"L
0-70°C, operating
NS3000·1
Memory Card 16K x 20 Bits
s:
CD
3
...o
<
en
The "Make
If you can't decide whether to build your own
memory or have National build it for you,
consider the following reasons why our customers have chosen National Semiconductor
Memory Systems:
or Buy"
Decision
~
o
E
Q)
Design Expertise
We specialize in memory systems. Utilizing National's memory expertise leaves your engineers
free to do what they do best.
~
Technology Advances
We provide continual design update to guarantee against obsolescence.
Component Availability
Our long-lead procurement cycle and secondsourcing of all components assures uninterrupted memory production.
Inventory
We minimize your inventory and simplify your
purchasing by establishing production rates that
match your needs.
Quality
Our extensive inspection, burn-in and testing
procedures have reql!ired substantial investment, but they are essential to guarantee the reliability of National memories.
Cost-Performance
Our memories provide the highest performance
at the lowest cost.
9-12
National's Memory Systems Testing
s:CD
3
o
..(
en
-<1/1
...
CD
3
1/1
Components Test
System Test
1. Evaluate devices: Review sche- 9. Single card test to meet specifications: Use fully loaded card
matics, design rules, process
characteristics, vendor test protested in macrodata 100 to verify
cedures, in process controls,
if board is operational and sat isvendor measured characteristics.
fies margins at room temperature.
2. Characterize devices: Define
10. Multiple card test at maximum
optimum reliable area of operaspecification ambient: Boards
are tested for a minimum of
tion (widest operating margins).
The process takes 3 to 6 months.
24 hours (must run error tree)
3. Generate test specifications:
at lO°C.
Specifications written around
11. Visual inspection and documentation: Visual check of workoperating margins as defined
by component characterization.
manship and check for completness of documentation.
8.100% temperature screen test:
Component is exercised under
full voltage margins at 70°C
ambient.
9-13
.
~ Semiconductor
~National
Interface
c
o
(I)
2
UI
......
C
fI)
8N
OS0025/0S0025C tWo phase MOS clock driver
general description
features
The DS0025/DS0025C is monolithic, low cost,
two phase MOS clock driver that is designed to be
driven by TTL/DTL line drivers or buffers such as
the DM932, DS8830 or DM7440. Two input
coupling capacitors are used to perform the level
shift froin TTL/DTL to MOS logic levels. Optimum
performance in turn-off delay and fall time are
obtained when the output pulse is logically controlled by the input. However, output pulse widths
may be set by selection of the input capacitors
eliminating the need for tight input pulse control.
•
UI
n
8-lead TO-5 or 8-lead dual·in-line package
• High Output Voltage Swings-up to .30V
• High Output' Current Drive Capability-up to
1.5A
•
Rep. Rate: 1.0 MHZ into> 1000 pF
•
Driven by OM932, OS8830, OM7440 (SN7440)
• "Zero" Quiescent Power
connection diagrams
Metal Can Package
Dual-in-Line Package
y'
8 NC
NC I
INPUT A 2
V-
-+_..-1;00---....-
6 V'
3
INPUT B 4 -+--t~---tl'- i
V-
Note: Pin 4 ..on~ected to CIKI.
TOP II~EW
TOP VIEW
Order Number DS0025H or DS0025CH
Order Number DS0025CN
See Package 23
See P.ckag~ 12
typical application
tim ing diagram
-
--sv
A.'npllIP~lsewidtb~V'.
pulse
~Iock
width
OV
ac test circuit
------5V
B.,nputpUlsewidlb~9D%-sets
widthclock pulSll
Clock pulse
outPlit
10%
10%
50%
InpUl waveform:
PRR=O.5MHz
Vp·p"5.0V
t,"'t,$10ns
Pulse width:
A.1.O;u
B.ZOOns
v"
' - -_ _ _ _ _ _ BV
IdON
7 OUTPUT A
r,'_'o_'_'____
VJ=OV
10%
50%
F=--=~---1------ Vz =-16V
*Q1 jsselected high speed NPN switching transistor.
10-1
OUTPUT B
,co
10
o
oCI)
c
co
~National
g
050026. 050056 5 MHz two phase MOS clock drivers
general description
Interface
~ Semiconductor
N
~
050026/050056 are low cost monolithic high speed
two phase Ma5 clock drivers and interface circuits.
, Unique circuit design provides both very high speed
operation and the ability to drive large capacitive loads.
The device accepts standard TTL/OTL outputs and
converts them to Ma5 logic levels. They may be driven
from standard 54/74 series and 545/745 series gates
and flip-flops or from drivers such as the 058830 or
OM7440. The 050026 and OS0056 are intended for
applications in which the output pulse width is logically
controlled; i.e., the output pulse width is equal to th!l
input pulse width.
in pulling up the output when it is in the high state. An
externai resistor tied betwe,en these extra pins and a
supply higher than V+ will cause the output to pull up
to (V+ - 0.1 V) in the off state,
For 050056 applications, it is ,required that an external
resistor be used to prevent damage to the device when
the driver switches low. A typical VBB connection is
shown on the next page.
These devices are available in 8-lead Ta·5, one watt
copper lead frame 8-pin mini·OIP, and one and a half
watt ceramic DIP, and Ta·8 packages.
The OS0026/050056 are designed to fulfill a wide
variety of Ma5 interface requirements. As a Ma5 clock
driver for long silicon·gate shift registers, a single device
can drive over 10k bits at 5 MHz. Six devices provide
input address arid precharge drive for a 8k by 16-bit
1103 RAM memory system. Information on the correct
usage of the 050026 in these as well as other systems is
included in the application note AN-76A.
features
• Fast rise and fall times-20 ns with 1000 pF load
• High output swing-20V
• High output current drive-±1.5 amps
• TTL/OTL COmpatible inputs
• High rep rate-5 to 10 MHz depending on power
dissipation
• Low power consumption in MaS "0" state-2 mW
• Drives to 0.4V of GNO for RAM address drive
The 050026 and 050056 are identical except each
driver in the OS0056 is provided with a VBB connection
to supply a higher voltage to the output stage. This aids
connection diagrams
TO·5 Package
(Top Views)
Dual·ln·Line Package
Ne
aUTA
v+
OltTI
Nt
INA
y-
INB
TO.a Package
Dual-I n-Line 'Package.
y+
Ne
OUTI
Ne
INB
Nt
Ne
Ne
Ne
DUTA
Ne
INA
Nt
y-
".
Note: Pin 4 eonnettedto CHe.
Order Number OS0026H
or DSOO26CH
Order Number OSOO26CN
See Package 12
See Package 23
TO-5 Package
Dual-ln·Line Package
DUTA
v+
YUB
Order Number DSO026G
or DSOO26CG
See Package 25
TO.a Package
OUT8
V·
Note: Pill4CGnJlectldtoCISII.
Order Number DS0056H
or DS0056CH
See Package 23
Dual-I n-Line Package
V'"
VUI
our8
Ne
INB
Ne
Ne
Ne
V_A
OUT A
Ne
IN A
Ne
v~
IN.
•
V'
Order'Number DSOO26J, 0s0026CJ
or DSOO26W
See Package 9 or Z1
I••
VBBA
INA
V-
INB
Order Number DSOO56CN
See Package 12
Order Number DSOO56G
or DSOO56CG
See Package 25
10-2
Order Number DS0056J
or DSO056CJ
See Package 9
o
.
~ Semiconductor
~,National
Interface
en
....
en
o
~
o
en
w.
en
o
OS1603/0S3603. OS3604. OS55107IOS75107.
OS55108/0S75108. OS75207. OS75208 dual line receivers
~
o
en
w
en
general description
features
The nine products described herein are TTL
compatible dual high speed circuits intended for
sensing in a broad range of system 'applications.
While the primary usage will 'be for line receivers
or MOS sensing, any of the proqucts may effec·
tively be used as voltage comparators" level trans·
lators, window detectors, transducer preamplifiers,
and in other sensing applications. As digital line
receivers the products are applicable with. the
OS55109/0S75109 and OS55110/0S75110 com·
panion drivers, or may be used in other balanced
or unbalanced party-line data transmission systems.
The im'proved input sensitivity and delay specifi- .
cations of the OS75207, OS75208 and.0S3604
make them ideal for sensing high performance
MOS memories as well as high sensitivity line
receivers and voltage comparators. TRI·STATE®
products enhance bused organizations.
• Diode protected input stage for power "OFF"
condition
o
~
....
• TTL compatible
• ±10 mVor±25 mV input sensitivity
• ±3V input common-mode range
• High inPUt impedance with normal Vee, or
Vee =OV
• Strobes for channel selection
• TRI-STATE outputs for high speed buses
• Oual ci'rcuits
• Sensitivity gntd. over full common-mode range
• Logic input clamp diodes-meets both "A" and
"B" version specifi!=ations
• ±5V standard supply voltages
connection diagrams
Itwut
Vc;c-
ZA
INPUT
n
.~
en
'-I
U1
6
~
o
en
U1
~
o
CO
"o
~
Dual-In-Line Package
Vcc +
o
en
U1
U1
• 17 ns typ high speed
Dual-In-line Package
OUTPUT
STROBE
2V
ZG
Ne
Vcc-
INPUT
ZA
.
INPUT
Ne
OUTPUT
STROBE
ZY
2i;
U1
.....
o
CO
o
~
flo,)
~
o
~
INPUT
lA
INPUT
18
Ne
OUTPUT
IV
STROBE
16
STROlE
S
INPUT
lA
GNO
INPUT'
II
lOP VIEW
Order Number DS55107J. DS75107J,
DS55108J, DS75108J. DS75207J
or DS75208J
See Package 9
Order Number DS75107N, DS75108N,
DS75207N or DS75208N
.See Package 14
Order Number DS55107W or DS55,108W
See Package 27
'Ie
OU1P1,11
IV
TOP VIEW
PACKAGEINPUT SENSITIVITV4
-55°CST/J,. 5+125°C
O°C$TA $+70°C
CAVITY DIP
CAVITY OR MOLDED OIP
.t25mV
:!:25mV
±10mV
D575107
OS75207
0575108
053603
0575208
053604
OUTPUT LOGIC!
TTL Active Pult-up
TTL Ope" Collector
TTL TRI·STATE
DISABLE
D
Orda; Number DS1603J. DS3603J
DS3604J or DSI603W
See Package 9 or 27
Order Number DS3603N or DS3604N
Se. Package 14
product selec,tion guide
TEMPERATURE-
STROlE
16
0555107
0555108
051603
10-3
GND
U1
flo,)
0,
CO
00
o
CD
M
C/)
C
.......
~National
Interface
~ Semiconductor
00
o
...
CD
C
D51605/053605, 051606/053606, 051607/053607,
D51608/053608 hex M05 sense amplifiers (M05 to TTL converters)
,...;
general description
C/)
o
CD
M
C/)
C
r:::
o
...
CD
C/)
C
CD
o
CD
M
C/)
C
.......
CD
o
...
CD
The OS3605 series is a new series of programmable
hex MOS sense amplifiers featuring high speed direct
MOS sense capability with high impedance states to
allow use of a common bus line. The OS1605/0S3605
and the OS1606/0S3606 have TRI-STATE® outputs.
The OS1607/0S3607 and OS1608/0S3608 have both
TR I-STATE inputs and outputs. High impedance states
are controlled by an enable input.
Outputs are high current drivers capable of sinking
50 mA in the low state and sourcing 5 mA in the high
state.
features
•
Non·inverting inputs (OS1605/0S3605, OS1607/
OS3607)
Inverting inputs (OS1606/0S3606, OS1608/0S3608)
No external components required (direct MOS sensing)
Programmable input thresholds
Current sensing-l00pA minimum
50 mA drive capability
TR I-STATE control
Single 5V supply
15 ns typical propagation delay (OS3605)
Input current threshold (the level at which the output
changes state) is determined by the current at the
programming pin. The current threshold is 100f.LA with
the programming pin grounded and 250f.LA with the pin
unconnected. The threshold can be set from 100f.LA to
300f.LA by connecting a resistor from the pin to ground,
and set above 300f.LA by connecting a resistor from the
pin to the positive supply .
•
•
•
•
•
•
•
•
connection diagram
typical application
C/)
o
It)
o
CD
M
C/)
C
.......
PACE Interface
Dual-tn-Line Package
It)
o
...
CD
10MIIS31
C/)
BUFFERS
C
ROM
ADDRESS
lATCH
30S361lB
-{>-HEX SENSE
AMPS
'TOP VIEW
30M8091
PACE
MICROPROCESSOR
ordering information
ORDER NUMBERS
DATA AND ADDRESS
OUTPUT
- (SOURCE)
t-"NI.-.-----1>--II4---JVV\r---:rt~~~
MODE SEleCT
ADDRESS
INPUTS
ISOURCEf$INK)
~
SWITCH.PAtR
SELEL
00--.-+--1--'
'--------~>_--~-~--~--~-~---_;OG~D
Dual-In-Line Package
Dual-I n-Line Package
(;NO'
2
OUTPUT
OUTi'UT
l
Y
(SINK)
Vee
SOUR~E
(JUTPUT OUTPUT
COLLEC
X
(SaURCEi TORS ISOURCE)
W
(SINK)
G
OUTPUT
GNO'
1
l
(SUliK)
Vee
OIjTPUT
v
SOURCE
COLlEe
OUTPUT
)(
OUTPUT
(SOURCE)
TORS
ISOURCE)
(SINKI
w
ADDRESS
INPUTO
AODRESSINPUTS
ADDRESS INPUTS
TOPVIEW
"GND 1 and GND 2 are to be
TIMING INPUTS
TOPVIEW
u~ed
in
parall~L
Order Number OS3629J
Order Number OS3629N
See Package 10
See Package 14
10·6
~National
.
Interface
~·Semiconductor
Advance Informatioli*
051640/053640. 051670/053670 quad M05 TRI-SHARE™port drivers
general description
The DS1640/DS3640and DS1670/DS3670 are quad
MaSTRI~SHARE port drivers with outputs designed to
drive large capacitive loads up to 500 pF associated
with MaS memory systems. PNP input transistors are
employed to reduce input current, allowing the large
fan·out to these drivers needed in meniory systems.
The circuit has Schottky·ciampedtransistor logic for
minimum propagation delay,
The DS1640/DS3640 has a 15 ohm resistor in series
with the outputs to dampen transients caused by the
fast switching output circuit. The DS16701DS36}0 has
a direct, low impedance output source for use with or
without an external· resistor.
The DS1640/DS1670 has two address inputs which
decode to one·of-four-high outputs. Provisions are made
fot address expansion. For example, two packages may
be used to implement a three-input, eight-output decoder.
Also included isa refresh control, read/write, and strobe
input. These functions are required by the MM5270
. 4k TRI·SHARE MaS RAM.
features
•
•
•
•
•
TRI·SHARE port driver for MM5270 RAM
TTL/DTL compatible inputs
PNP inPuts minimize loading
Capacitance-driving outputs
Built-in damping resistor (DS1640/DS3640)
logic and connection diagrams
Dual-in-Line Package
ADDRESS'A:~H=~?>-rn~~~~~~~~t)
A.DDRESS
DISABLE
ADDRESS B
EXPANSION
OUT
A"
o-+......-L../
o-~f=====ft~~~~~~~t)
EXPN
OUTPUT
114
!3
ADO A
12
OUT
A-S
ST'
10
11
,
A·,
•
OUTPUT
A-g
r-
D-OUTPut
"A-B
REFRESHo-~~~~~=~~~~~~~~~~~
1
OUTPUT
A-Ii
ReADAARITEo-----~------------~~-f~
ADO
DIS
,
3
,
,
,
AOD BOUT
EXPN
REFSH
OUT
A·a
17
GNo
joB
TOP VIEW
Order Number DS1640J, DS1670J, DS3640J,
DS3670J, DS3640N or DS3670N
See Package 9 or 14
STROBE o - - - - - - - - - - - - - - - - - - - - < l > - i - - '
schematic diagram
EQUIVALENT OUTPUT
EQUIVALENT INPUT
;-----------------t---------------~-----1~~--OVcc
r-
------,
I
I
I
INPUT
I
I
I
I
I
15 (DS164OJOS3640 ONL V)
' - - - -.....""VW-o OUTPUT
INTERNAL
LOGIC
CIRCUITRY
I
L
L--6-----------------:I~OTSTRAP
EXTUINAl
BOOTSTRAP
CAPACITOR
connection diagrams
Metal Can Package
G"'
Order Number DS1642H, DS3642H,
DS1672H or DS3672H
See Package 23
(Top Views)
Dual-In-line Package
Dual-In-Line Package
Vee
IN 2
B2
OUT Z
IN 1
81
.OUT 1
GNO
Order Number OS3642N
or OS3672N
See Package 12
IN 1
81
rue
NC
Ne
OUT 1
Order Number DS1642J, DS3642J,
DS1672J or DS3672J
GNO
See Package 9
"Specifications may change.
10-8
.~National
.
Interface
·~Semiconductor
Advance Information*
o
o
w
0)
DS3643, OS3673 decoded quad MOS clock drivers
general description
The OS3643 and OS3673 are quad bipolar-to-MOS
decoder/clock drivers with TTL/OTLcompatible inputs_
They are designed to provide high output current and
voltage capabilities necessary for optimum driving of
high capacitance N-channel MOS memory systems_
switching output, while the OS3673 has a direct, low
impedance output, for use with or without an external
resistor.
The device features full decoding of input address lines
froin two inputs to one of four outputs. Also featured is
the. capability of expanding to three inputs to one of
eight outputs with . the use of the· Expansion and
Expansion inputs. Also included are clock and refresh
inputs.
features
•
•
•
•
The circuit was designed for driving large capacitive
loads at high speeds and uses Schottky-clamped transistors. PNP transistors are used on all inputs, thereby
minimizing input loading.
•
•
•
The OS3643 has a lOa damping resistor in series with
each output to dampen transients caused by the fast
•
TTL/OTL compatible inputs
Operates from standard bipolar and MOS supplies
PNP inputs minimize input loading
Full logic decoding for either two inputs to one of
four outputs or three inputs to one of eight outputs
High voltage/current outputs
Input and output clamping diodes
Control logic optimized for use with MaS memory
systems
Built-in damping resistors (OS3643)
logic and connection diagrams
AI
Dual-I n·Line Package
Veel
,.
OUT 4
elK
RFSH
EXPN
OUT J
11
10
•
12
13
Vee3
,
-
......
-
r--
1
,
VCC2
OUT 1
,
•
3
AI
fR1SN
A2
•
OUT2
,
GND
TOP VIEW
Order Number DS3643J
or 0S3643N
Order Number 0S3673J
or DS3673N
See Package 9 or 14
truth table
OUTPUTS
INPUTS
,
REFRESH
EXPANSION
EXPANSION
A2
A,
OUT,
OUT 2
OUT 3
OUT4
X
X
X
0
0
,
.,
1
1
,
0
1
X
X
0
0
0
0
0
0
0
0
0
X
X
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
X
X
X
0
0
0
0
0
0
1
CLOCK
0
0
0
0
0
0
0
X
1
1
)
0
0
X
0
0
1
1
0
x = Doo't Care State.
0
1
X
X
X
0
0
0
0
0
1
0
0
9
0
1
1
0
0
0
"Specifications may change.
1O·9
~
'~National
Interface
~ Semiconductor
Advance Information *
051644/053644. 051674/053674 quad TTL to M05 clock drivers
general description
The 051644/053644 and 051674/053674 are quad
bipolar-to-M05 clock drivers with TTL/DTL compatible
inputs. They are designed to provide high output current
and voltage capabilities necessary for optimum driving
of high capacitance N-channel M05 memory' systems.
has a direct. low impedance output for use with or
without an external damping resistor.
features
•
•
•
•
•
•
•
TTL/OTL compatible inputs
12V clock or 5V clock driver
Operates from standard bipolar and MOS supplies
PNP inputs minimize loading
High voltage/current outputs
Input and output clamping diodes
Control logic optimized for use with M05 memory
systems
• Pin and function compatible with MC3460 and
3235
• Built-in damping resistors (0516441053644)
The device features two common enable inputs. a
refresh input, and a clock control input for simplified
system designs. The circuit was designed for driving
highly capacitive loads at high speeds and uses 5chottkydamped transistors., PNP transistors are used on all
'inputs thereby minimizing input loading.
The circuit may be connected to provide a 12V clock
output amplitude as required by 4k RAMs or a 5V clock
output amplitude as required by 16k RAMs.
The 051644/D53644 contains a 10D resistor. in series
with each output to dampen the transients caused by
the fast-switching output, while the 051674/053674
schematic and connection diagrams
Veca
EQUIVALENT INPUT
EQUIVALENT OUTPUT
I
INPUT
10*
L - - -................./V'y-o OUTPUT
INTERNAL
LOGIC
CIRCUITRY
1
/r-'
, 'I
I
I
1
L ___ _
--------4----.. .
------~--~G.D
L-.....
* OS1644/053644 only
Dual·. n-L'ine Package
Vee1
OUT 0
SEL 0
EN 1
EN 2
VCC2
OUT A
SEl A
eLK
RFSH
IN
IN
TOPYIEW
SEL C
OUT C
VetJ
SEl BOUT B
GNU
Order Number DS3644J. DS3674J,
DS3644N or DS3674N
See Package 10
or 15
~Nalional
Interface
~ Semiconductor
Advance Infprmation *
051645/053645, 051675/ OS 3675
hexTRI-5TATE'® TTL to MOS latch/drivers
general description
The OS1645/0S3645 and OS1675/0S3675 are hex
MOS latch/drivers with outputs designed to drive large
capacitive loads up to 500 pF associated with MOS
memory systems. PNP input transistors are. used to
reduce input currents, allowing the. large fan-out to
these drivers needed in memory systems. The circuit
has Schottky-clamped transistor logic for minimum
propagation delay, and TRI-STATE® outputs which
allow bus operation.
The circuit employs a fall-through-Iatch which captures
the data in parallel with the output, thereby eliminating
the delay normally encountered in other latch circuits.
The OS1645/0S3645 and OS1675/053675 may be
used for inpu,t addres.s lines or inPut/output data lines
of a M05 memory system.
•
•
•
•
•
TTLIOTL compatible inputs
PNP inputs minimize loading
Capacitance-driving outputs
TRI-5TATE outputs
Built-in damping resistor (OS1645/DS3.645)
r--------------.
I
I
1
I
Dual~In-Line
I
Vee
I,.
1
1
:s~~
DATA F
lS
OF
Package
DATA E
12
13
1.4
DE
DATA 0
11
lIn
,
10
IL ______ _
DATAC
o-C
o-C
DATAD
o-C
DATAS
o-C
DATAf o-C
DATAE
~~!:~~
== =~ ===
r-
=
=
===== ====:J-onc
==
==
==
==
==
= -..:..===:J-ono
=
=
=
=== == = =====:J-o
===
li
~
,
IN
,
3
2
DATA A
-
QA
INPUT
ENABLE
OUTPUT
DISABLE
DATA
OUTPUT
1
1
0
Data Feed-Thrqugh
0
1
Data Feed-Through
0
0
0
0
X
Q
Latched to Datil. Present
when Enable Went Low
X
1
X
Hi-Z
High Impedance Output
10-11
•
DATA C
7
iIc
I'
GND
Order Number DS1645J, DS1675J, DS3645J,
DS3675J, DS3645N or DS3675N
Seo Package 10 or 15
truth table
. X = Don t care
Hi-Z = TRI-STATE mode
i1B
T(JPVIEW
o------t"><:>------------J
1
,
4
DATA B
ENBl
:::J-o OF
UI
......
c
w
en
en
UI
logic and connection diagrams
DATA A
en
-'
en
.....
.....
featureS
The 051645/D53645 has a 15.n resistor in series
with the outputs to dampen transients caused by the
fast switching output circuit_ The 051675/053675
has a direct, low impedance output for use with or
without an external resistor.
c
OPERATION
~
c.c
en
('I)
o
.......
Interface I
~National
~ Semiconductor
Advance Information*
~
c.c
en
o
c.c
OS1646/0S3646, 051676/0S3676 6-bit TRI-STATE®
MOS refresh counter/driver
or::t
general description
('I)
The OS1646/0S3646 and OS16761OS3676 are 6-bit
refresh counters with outputs designed to drive large
capacitive loads up to 500 pF associated with MOS
memory systems. PNP input transistors are employed
to reduce input currents. The circuit has Schottkyclamped transistor logic for minimum propagation delay,
and TR I-STATE outputs allow it to be used on common
data buses.
<0
en
o
.......
<0
or::t
....c.c
en
o
The OS1646/0S3646 has a 15Q resistor in series with
the outputs to dampen transients caused by the fast
switching output circuit. The 0516761OS3676 has
a direct, low impedance output, for use with or without
an external resistor.
The counter uses as its input the RAM clock signal, and
with each clock input, it advances the count by one,
thus generating a new refresh address_
Extra pins in the package are used for a 2-input NAND
gate and a 2-input NOR gate, both of which have capacitive drive outputs.
features
•
•
•
•
•
•
•
•
Circuit counts when clock goes high
TTL/OTL compatible inputs
PNP inputs minimize loading
Capacitance-driver outputs
TRI-STATE outputs
Extra gates on unused pins
Built-in damping resistor (OS1646/0S3646)
Initialize input
logic diagram
{JUT 2
OUT 1
OUT J
OUT 4
OUTS
OUT 6
elK
INITIALIZE
o--c>o-.....- -.............- .......>---4......-_~---l
connection diagram
IJ6
OUT
ENBL
>5
OUT Ii
"
OUT 5
The OS1646/0S3646 and OS1676/0S3676 have TRISTATE outputs which can be tied to the outputs of
another TRI-STATE driver. The refresh counter can
control the address lines into a memory array during
a short refresh cycle, and then return to the highimpedance state to allow the primary driver to control
the address lines.
INIT
OUT 4
n
11
"
10
,
OS36451
r-
083675
INPUTS
,
eLK
,
J
OUT lOUT 2
,
•
B
typical application
Dual-In-line Package
Vee
A
,
OUT 3
TOP VIEW
"""'"I
REfRESH
CONTROL
7
A:s
I'
DRIVER
LATCH
J.'
MEMORY
ARRAY
OUTPUT
DISABLE
GNO
Order Number DS1646J, DS1676J, DS3646J,
DS3676J,DS3646N.orDS3676N
OUTPUT
ENABLE
See Package 10 or 15
CLOCK
053645/
OS3616
RefRESH
COUNTER
·Specifications may change.
10-12
~National
Interface
~Semiconductor
Advance "Information *
OS1647/0S3647, OS167710S3677, OS16147/0S36147, OS16177/DS36177
quad TRI-STATE® MOS memory 1/0 registers
general description
The OS1647/0S3647 series are 4·bit I/O buffer registers
intended for use in MOS memory systems. The circuits
employ a fall-through latch for data storage. This method
of latching captures the data in parallelwith the output,
thus eliminating the delays encountered in other designs.
The circuits use Schottky-ciamped transistor logic for
minimum propagation delay and employ PNP input
transistors'so that input currents are low, allowing large
fan-out to these circuits needed in a memory system.
OSl647/0S3647 and OS1677/0S3677 they are TRI·
STATE. The "8" port outputs are also designed for use
in bus organized data transmission systems and cansink
80 mA and source -5.2 mAo The "Au port outputs in
all four types are TRI·STATE.
Oata going from port "A" to port "8" is inverted in the
OS1647/0S3647 and OS16147/0S36147 and is not
inverted in the 051677 /053677 and 0516.177 /OS36177.
"Data going from port "8" to port "A" is inverted in
all four types.
Two pins per bit are provided, and data transfer is bi·
directional so that the register can handle both input and
output data. The direction of data flow is controlled
through the input enables. The latch control, when
taken low, will cause the register to hold the data present
at that time and display it at the outputs. Data can be
latched into the register independent of the output
qisables or EXPANSION input. Either or both of the
outputs may be taken to the high-impedance state with
the output disables. The EXPANSION pin disables both
outputs to facilitate multiplexing with other I/O registers on the same.data lines.
features
.j:Iro
o
• PNP inputs minimize loading
C/)
w
0)
...
• Propagation delay of only 15 ns
• Bi-directlonal data flow
!j
o
C/)
• TTL/DTL compatible
0)
• Transmission line driver output
~
• TRI·STATE outputs
• EXPANSION control_
......
o
w
0)
logic and connection diagrams
C/)
....
r-----------~---------,
I
I
16
Bl
VCC
15 B4
Al
INPUT {A J
ENABLE
B
Al
_____ J
=====}-oB2
=====}-oBJ
=====}-oB4
-----,
AZo-[= === =
AJo-[=====
Mo-[=====
r----I
I
I
I
L
::J
Dual·ln·Line Package
~
I
I
I
I
I
I
L ____ _
I
I
I
___ JI
____ _
A
INPUT
ENABLES
...
~
• Fall-through latch design
The "8" port outputs in the OS16147/DS36147 and
0516177/0S36177 are open collectors, and in the
o
....
0)
C/)
0iiTPuT B EXPANSION
DISABLES
*Inverting DS1647/0S3647 and OS16147/0S36147 only
10-13
:: :XP) OUHUT
DISABLE
LATCH
11 B
A2
10 AJ
82
9 83
GND
TOP VIEW
Order Number DS1647J. DS3647J. DS1677J,
0S3677J, DS11!147J. DS36147J, OS16177J,
DS36177J,DS3647N.DS3677N,DS36147N
" or 0836177111
See Package 10 Dr 15
~National
Interface
~ Semiconductor
Advancelnformation*
OS1648/0S3648, OS1678/0S3678 TRI-STATE® MOS multiplexer/drivers
general description
D53678 has a direct, low impedance output for use
with or without an external resistor.
The OS1648/0S3648 and OS1678/0S3678 are quad
2-input multiplexers with TRI-5TATE outputs designed
to drive the large capacitive loads (up to 500 pF)
associated with M05 memory systems. A PNP input
structure is employed to minimize input currents so that
driver loading in large memory systems is reduced. The
circuit employs Schottky-clamped transistors for high
speed and TR I-STATE outputs for bus operation.
features
• TRI-5TATE outputs interface directly with system
bus
• Schottky-clamped for better ac performance
• PNP inputs to minimize input loading
• DTL and TTL compatible
• High-speed capacitive load drivers
• Built-in damping resistor (D516481053648 only)
The OS16481053648 has a 15 ohm resistor in series
with the outputs which dampens the transients caused
by the fast-switching output circuit, while the OS16781
logic and connection diagrams
OUTPUT
Dual-In-Line Package
115)
CONTROL
A1~12~)--______________r-~
OUTPUT
Vee
V1
B1~P~)------+---------~~
A2
15)
B2
18)
CONTROL
/16
INPUTS
~
A4
84
14
15
OUTPUT
Y4
13
INPUTS
..----..
AJ
83
10
11
12
OUTPUT
Y3
--
9
p-
A3 1111
V3
B3~11~0I-------r-------t-f--~
2
1
A.~I1~')-------r-------t-f--~
SElECT
v.
113)
B'~~----~r-------t-r-~
A1
,
J
B1
~
INPUTS
Y1
OUTPUT
7
6
5
A2
82
'-v---"
INPUTS
Y2
OUTPUT
I'
GNO
TOP VIEW
Order Number DS1648J, DS1678J, DS3648J, DS3678J,
DS3648N or DS3678N
See Package 10 or 15
SELECT
schematic diagram
EOUIVALENT OUTPUT
EQUIVALENT INPUT
r-------------------.-----------------.-------.------ov,'
.I
I
I
15 (OS1648/DSJ648 ONLY)
L-------1~'V'v"'""-o OUTPUT
INTERNAL
INPUT
lOGIC
CIRCUITRY
~~~----------------~~--------------~~----~~-----oGNO
. . Specifications may change.
10·14
~National
Interface
~ Semiconductor
Advance Information*
OS1649/0S3649. OS1679/0S3679 Hex TRI-STATE® MOS drivers
general description
The 051649/053649 and 051679/053679 are Hex
TRI-5TATE MOS drivers with outputs designed to drive
large capacitive loads up to 500 pF associated with M05
memory systems. PNP input transistors are employed to
reduce input currents allowing the large fan-out to these
drivers needed in memory systems. The circuit has
5chottky-clamped transistor logic for minimum propagation delay, and TRI-STATE outputs for bus operation.
impedance output for use with or without an external
The 051649/053649 has a 15 ohm resistor in series with
the outputs to dampen transients caused by the fastswitching output. The 051679/053679 has a direct low
•
resistor.
features
•
High speed capabilities
•
•
Typ 7 ns driving
Typ 25 ns driving
TRI·STATE outputs for data bussing
•
Built-in 15 ohm damping resistor (OS1649/053649)
•
Same pin-out as 058096 and 0574366
schematic diagram
.----------=,......,....--....---1---o v
EQUIVALENT OUTPUT
EQUIVALENT INPUT
oo
15 (DSl649/DS36490NLYJ
'-----<......""'-0 OUTPUT
INPUT
L _ _ _ __
'--~-----~~=1~~~~=-=--~--~---OGND
connection diagram
typical application
Dual-In-Line Package
0936149
6 BIT RAM
ADDRESS
r----.,
OR
0S36179
f-----,
MOS
DRIVER
~-----'-i
1-___
-,-..,
DISABLE
I
I
ADDRESS
LINES
MM52:1Q
DR
MM52:80
MOSRAM
ARRAV
H-'+...._--iREFRtSH&
68ITRAM
DIS1
IN!
~Ull
INZ
Dun
OUT3
H-++,....._-.~I~~~ESS
ADDRESS
GND
DISABLE
Order Number DS1649J, DS1679J,
DS3649J. DS3679J, DS3649N
or DS3679N
See Package 10 or 15
DS3646
OR
053676
truth table
DISABLE INPUT
DIS 1
DIS 2
I
I
I
I
I
I
I
I
"DS
COUNTER
ORiVER
INPUT
OUTPUT
ENABLE
ADDRESSOR
Don't care
HI'Z = TAI·STATE mode
=
COUNT SELECT
"O--ADDRESS
"1"COUNT£R
HI-Z
Hi-Z
x
HI-Z
*SpecifJc:ations may change.
10-15
~National
Interface
~ Semiconductor
Advance Information*
053651, 053653 quad high speed M05 sense amplifiers
general description
features
The OS3651 and OS3653 are TTL compatible high speed
circuits intended for sensing in a broad range of MOS
.memory system applications. Switching speeds have been
enhanced over conventional sense amplifiers by applica·
tion of Schottky technology, and TR I-ST ATE® strobing
is incorporated offering a high impedance output state
for bused organ ization.
15 ns (typ)
• High speed
• TTL compatible
±7 mV
• Input sensitivity
• TRI·STATE outputs for high speed buses
±5V
• Standard supply voltages
The OS3651 has active pull·up outputs, and the OS3653
offers open collector outputs providing implied "AND"
operations.
• Pin and function compatible with MC3430 and
MC3432
connection diagram
truth table
Dual-In-line Pack~ge
Vee
-IN B
-tIN BOUT B
VEe
iOUT 0
+IN 0
-IN 0
STROBE
INPUT
VIO
TA
2+7.0mV
= aOc to +70°C
STB
OUT C
+IN C
-IN C
GND
TOP VIEW
Order Number DS3651J, DS3653J, DS3651N
orOS3653N
See Pack_l0 or 15
H
Open
H
Open
Open
-7.0mV5VID S+7.0mV
L
X
X
H
Open
Open.
VIO ~-7.0 mV
OUT A
053653
L
TA = aOc to +70°C
TA '"
-IN A
OUTPUT
053651
aOc to +70°C
L
l
L
H
Open
Open
L = Low logIC state
H = High logic state
Open = TRI-5TATE
X
=:
Indeterminate State
typical applications
A Typical MOS Memory Sensing Application for a 4k word by 4-bit
memory arrangement employing 1103 type memory devices
053651
r----'
0S3653
I-t=-:.;:.--.o-......-I~
200
DATA 8114
I
I
DATA BIT3
Jo---1h:i-O DATA BIT 3
200
I
DATA BIT 2
~-+--t--oDATABIT2
200
DATA BIT 1
+wo-~VVv--.~--------------~----o-~-t~
18k
Nate: Only fuur devices are rtquired for a4k
word by 1&-hit memOTV system:
p-+-....,..-<) DATA BIT I
200
STROBEo-----<>--t--I
L ____ J
*Specifications may change
10·16
~National
Interface
aSemieonductor
Advance Information"
081671/083671 bootstrapped two phase M08 clock driver
general description
The OS1671/0S3671 is a high speed dual MOS clock
driver and interface circuit. Unique circuit design pro·
vides both very high speed operation and the ability
to drive large capacitive loads: The device accepts
standard TTLlOTLoutputs and converts them to MOS
logic levels. It may be driven from' standard 54fl 4
and 54Sfl4S series gates and flip·flops or from drivers
such as the OS8830 or OM7440. The circuit can be used
in both P·channel and N·channel MOS memory system
drive applications.
Each driver uses output bootstrapping to provide a
higher voltage to the output stage, thus, eliminating the
need for an additional Vee supply. Th~ bootstrapping
function is accomplished by connecting a small value
capacitor (typically 200 pF) from each output to each
drivers bootstrap node.
'
features
•
•
•
•
•
Fast rise and fall times-20 ns with 1000 pF load
High outputswing-20V
High output current drive-±1.5A
TTL/OTL compatible inputs
High rep rate-5 to 10 MHz depending ,on power
diSSipation
• Low power consumption in MOS "0" state-2 mW
• Swings to O.4V of GNO for RAM address drive
The DS1671/0S3671 is intended to fulfill a wide
variety of MOS interface requirements. As a MOS clock
driver for long silicon gate shift registers, a.singledevice
can drive over 10k bits at 5 MHz. Six devices provide
input address and precharge drive for an 8k by 16-bit
1103 RAM memory system.
connection diagrams
Dual-I n-Line Package
Dual-I n-Line Package
Metal Can Package
DUTI
v+
B2
QUTZ
V'
v'
BZ
QUT2
13
"
Ne
'.2
Nt
Ne
INI
Ne
Ne
12
vrOPVIEW
81
Order Number DS1671H
or DS3671H
SeaPack_23
IN 1
V-
IN2
Ne
B1
OUTI
TOP VIEW
TOP VIEW
Order Number DS3671N
Se. Package 12
Order Number DS1671J or DS3671J
S•• Package 9
typical applications
v~Ef
GRAPH fOR VALUE
DS3671 Operating with Extra Supply
to Inhance O,utput Voltage Level
Bootstrap Clock Driver Driven from a TTL Gate
·Specificatlons may change.
10-17
~National
~ Semiconductor
Interface
Advance Information*
OS16149/0S36149, OS16179/0S36179 Hex MOS drivers
general description
The DS16149/oS36149 and OS16179/DS36179 are
Hex MaS drivers with outputs designed to drive
large capacitive loads up to 500 pF associated with MaS
memory systems. PNP input transistors are employed to
reduce input currents allowing the large fan-out to these
drivers needed in memory systems. The circuit has
Schottky·clamped transistor logic for minimum propaga·
tion delay, and a disable control that places the,outputs in
the logical "1" state (see truth table). This is especially
useful in MaS RAM applications where a set of address
lines has to be in the logical "1" state during refresh.
fast-switching output. The 0516179/DS36179 has a
direct low impedance output for use with or without
an external resistor.
features
The 0516149/D536149 has a 15 ohm resistor in series
with the outputs to dampen transients· caused by the
•
High speed capabilities
• Typ 7 ns driving 50 pF
• Typ 25 ns driving 500 pF
•
Built·in 150hm damping resistor (0516149/0S36149)
• Same pin-out as OS8096 and OS74366
schematic diagram
15 (OS161491DS36149 ONLY)
L---t-'VVlr-O
L-~--
___
connection diagram
Dual~1 n~line
"00
OIU
IN &
L ___ _
~~~~
______
4-~_~
__
"""T
~.'D
typical application
Package
OUTS
OUT &
OUH
·0Sl1149
OR
...,r----'
t-_ _ _
05311111
MO.
181TRAM
ADDRESS
DRIVER
1 - - - - - - 1 ADDRESS
1------, LINES
....",
DR
....",
MOSRM
0"'"
DR
..,
"RRAY
053&19
G81lHAM
DRIVER
ADDRESS
L ___ _
TOP VIEW
Order Number DS16149J, DS16119J, DS36149J,
DS36119J, DS36149N or DS36179N
See Package 10 or 15
......
DR
053&76
truth table
.os
DISABLE INPUT
DIS 1
DlS2
0
0
0
0
,
0
,
x
,
,
0
COUNnR
DRIVER
INPUT
OUTPUT
,
0
x
x
x
,
0
,
,,
ENAILE
ADDRESSOR
.COUNTSElECT
"O"AOORESS
"l COUNTER
H
.. Don tcare
·Specifications may change.
10·18
c
Ch
Interface
~National
~·SemiConductor
Advance Information*
UI
UI
-'
o
CD
.....
C
Ch
0555109/0575109, 0555110/0575110 dual line drivers
....UI
general description
CD
These products are TTL compatible high speed
differenti·al line drivers Intended for use in terminated twisted-pair party-line data transmission
systems. They may also be used for level shifting
since oUtput common-mode range is -3V to +10V.
An internal current sink is switched to either
output dependent on input logic conditions. The
current sink may be turned off by appropriate
inhibit, input conditions.
o
•
High speed
•
Wide output common-mode range
•
High output impedaRce
C
15 ns max
CJ)
features
•
-'
Tightly controlled output currents over temperature, V cc, and common-mode variations
•
Inhibits for party-line applications
•
Current sink outputs
•
Dual circuits
•
Standard supply voltages
•
I nput clamp diodes
•
14 pin cavity or molded DIP
UI
UI
6 or 12 rnA
±5V
connection diagram
schematic diagram
D'ual ..ln-Line Package
OUTP~T
I~PUT
JII
V1
OUlPUT
II
INPUT
81
It.lHIB1T
Cl
INHIBIT
C2
INPUT
A2
OlHI'Ul
OUTPUT
"
"
I"PUT
Bl
Order Number DS55109J, DS55110J,
DS75109J or DS75110J
S--+--+--+-0 OUTPUT
INPUT
1 5V
tp~ H
(NOTE B)
OUTPUT
Note 1: The lIulse generators have the foUowin~ characteristics:
lOUT"=' SOn, tw " 200 ns, duty cycte " 50%,1, -" tr " 5.0 ns.
Z~ CL includes lI!obe and jig capil~itan~e
10-20
.-1 1- ~.S.D",
1 5V .
oJO% . !
C,
Note
1:-.
3.0V~90%
90%
VOH
-1-------1
:
IpH
10%
~ -1---'"~
-~-~
VOl~
1.5V
L
o
~National
Interface
~ Semiconductor
(J')
U'I
U'I
....
N
N
........
o
(J')
.....
~
0555122/0575122 triple line receivers
N
N
general description
features
The OS55122/0S75122 are triple line receivers
designed for digital data transmission with line
impedances from 50n to 500n. Each receiver has
one input with built-in hysteresis which provides a
Iqrge noise margin. The other inputs on each
receiver are in a standard TTL configuration. The
DS55122/0S75122 are compatible with standard
TTL logic and supply voltage levels.
• Built-in input threshold hysteresis
• High speed ... typical propagation delay time
20m
• Independent channel. strobes
• Input gating increases application flexibility
• Single 5.0V supply operation
• Fanout to 10 series .54/74 standard loads
• Plug-in replacement for the SN55122/SN7 5122
and the 8T14
connection diagram
truth table
Dual-In-Line I'ackage
A
INPUTS
Bt
R
S
OUTPUT
y
L
H
H
X
X
X
X
L
H
L
L
X
H
X
H
L
X
X
L
H
X
L
H
X
H
X
L
X
L
H
H,;, high level, L '" tow level, X = irrelevant
tB input and last two lines of the truth table
are applicable to receivers' 1 and 2 only.
.., .,
.2
52
.2
V2
GNO
TOP VIEW
O.de. Numbe. DS55122J, DS75122J, DS75122N
or DS55122W
See Package 10, 15 or 28
ac test circuit and switching time waveforms
v,,
2.6V
,~5.0ns
2.6V
lN301i4
INPUT
OUTPUT
OUTPUT
voc
..".
Note 1:' The pulse generator hilS the following characteristics:
Zout "'" son, t~ '" 200 ns, duty cycle", 51J'l1,; t f '" If .. 5.0 os.
Note 2:, CL inc'ud~ probe and jig capacitance.
10-21
ml
~National
Interface
~ Semiconductor
0575123 dual line driver
general description
features
The 0575123 is a monolithic dual line driver
designed specifically to meet the I/O interface
specifications for IBM System 360 .. It is compatiblewith standard TTL logic and supply voltage
levels.
• Meet I BM System 360 I/O interface specifica,
tions for digital data transmission over 50n to
500n coaxial cable, strip line, or terminated
pair transmission lines
• TTL compatible with single 5.0V supply
• 3.11 V output at IOH ;
The low-impedance emitter-follower outputs of
the DS75123 enable driving terminated low impedance lines. In addition the outputs are uncommited allowing two or more drivers to drive
the same line.
• AND-OR logic configuration
• Plug-in replacement for the SN75123 and the
8T23
connection diagram
typical performance
characteristics
Dual-I n-line Package
"
02
E2
15
C2
B2
rnA
• Short circuit protection
Output short-circuit protection is incorporated
to turn off the output when the output voltage
drops below approximately 1.5V.
F1
~59.3
• Open emitter-follower output structure for
party-I ine operation
A2
V2
Output Current vs Output Voltage
-300
14
~ ~250
J)5JV
c
V1H = 2.0V
--
.§.
i
TA
0-
-200
'\.
~ -150
~
1\
-101)
1\
I
~
-50
I-
o
lA
Cl
B1
FI
01
E1
TOP VIEW
VI
= 25"C
-
\
0.5 1.0 1.5 2.0 2.5 3.0 3.54.0 4.5 5.0
Vo - OUTPUT VOLTAGE IV)
GNO
Order Number OS75123J
truth table
See Package 10
Order Number OS75123N
OUTPUT
INPUTS
See Package 15
y
A
B
C
0
E
F
H
H
H
H
X
X
H
X
X
X
X
H
H
H
All Other Input Combinations
H ,= high level, L
ac test circuit and switching time waveforms
3.0V
}--I-....- -...-o OUTPUT
C,
(NOTE 2)
Notel: THE PULSE GENERATORS HAVE THE FOLLOWING CHARACTERISTICS: lOUT
tw = 200 ns, 0 UTV CV CLE = 50%.
Note 2:
'>0
5011,
C, INCLUDES PROBE AND JIG CAPACITANCE.
10-22
= low level,
L
X
=
irrelevant
~National
Interface
.~ Semiconductor
0575124 triple line receivers
general description
features
The DS75124. is designed to meet the input/
output interface specifications, for I BM System
360. it has built·in hysteresis on one input on
'each of the tllree· receivers to provide large noise
margin. The. other inputs on each receiver are in
a standard TTL configuration. The DS75124 is
compatible with standard TTL logic and supply
voltage levels.
•
•
•
•
•
•
Built-in input threshold hysteresis
High speed ... ty~ propagation delay time 20 ns
I ndependent channel strobes
I nput gating increases application flexibility
Single 5.0V supply operation
Plug-in replacement for the SN75124 and the
8T24
connection diagram and truth table
Dual-In-Line Package
Vee
.,
VI
A3
S3
INPUTS
Bt
R
A
S
OUTPUT
y
H
H
X
X
L
X
X
L
H
L
L
X
H
X
H
L
X
X
L
H
X
L
H
X
H
X
L
X
L
H
H :: high level, L = low level, X = irrelevant
ta input and' last two lines, o'f the truth table
are applicable to receivers 1 and 2 only.
TOP VIEW
Order Number DS75124J
See Package 10
Order Number DS75124N
See Package 15
typical application
A
r - - - - -:-- - --,I
8
C
o
95 COAXIAL CA8LE
.r+~~~------++~~~
95
r---.
A -.......
8--"_,,
L __ '~7~ __ -.J
10-23
~.National
Interface
~ Semiconductor
0575150 dual line driver
general description
features
The OS75150 is a dual monolithic line driver designed
to satisfy the requirements of the standard interface
between data terminal equipment and data communication equipment as defined by EIA Standard RS·232-C.
A rate of 20,000 bits per second can be transmitted with
a full 2500 pF load. Other. applications are in data·
transmission systems using relatively short single lines,
in level translators, and for driving MaS devices. The
logic input is compatible with most TTL and OTL
families. Operation is from -12V and +12V power
supplies.
• Withstands sustained output short·circuit to any
low impedance voltage between -25V and +25V
• 21ls. max transition time through the -3V to +3V
transition region under full 2500 pF load
• Inputs compatible with most TTL and OTL families
• Common strobe input
• Inverting output
• Slew rate can be controlled with an external capacitor
at the output
• Standard supply voltages
±12V
schematic and connection diagrams
I
Dual-I n·Line Packag..
+Vee
1Y
lY
-Vee
. .vcc:<>---<~---------~~-
Compolllm vlllun.awn Ire nominll
lJ2ofcin:uitsliown
lie
INPUl
2A
TDPYlEW
PositiftLogicy=Ai
Order Number DS75150J
SeePack_9
10·24
~National
Interface
~ Semiconductor
0575154 quadruple line receiver
general description
The OS75.154 is a quad monolithic line receiver
deSigned to satisfy the requirements of the standard
interface between data terminal equipment and data
communication equipment as defined by EIA Standard
RS-232C. Other applications are in relatively short,
single·line, point-to-point datatransmission systems and
for level translators. Operation is normally from a single
5V supply; .however, a built-in option allows operation
from a 12V supply without the use of additional components. The output is compatible with most TTL and
OTL circuits when either supply voltage is used.
the negative-going threshold voltage to be above zero.
The positive-going threshold voltage remains above zero
as it is unaffected by the disposition of the threshold
terminals .. In the fail-safe mode, if the input voltage goes
to zero or an open-circuit condition, the output will go
to the high level regardless of the previous input condition·,
features
In normal operation, the threshold-control terminals are
connected tothe V CC1 terminal, pin 15, even if power is
being supplied via the alternate V cc2 terminal, pin 16.
This provides a wide hysteresis loop which is the difference between the positive-going and negative-going
threshold voltages. In this mode,if the input voltage
goes to zero, the output voltage will remain at the low or
high level as determined by the previous input.
•
Input resistance, 3 H2 to 7 kS1 over full RS-232C
voltage range .
•
Input threshold adjustable to meet "fail-safe" requirements without using external components
Inverting output compatible with OTL or TTL
Built-in hysteresis for increased noise immunity
Output with active pull-up for symmetrical switching
speeds
Standard supply voltage-5V or 12V
•
•
•
For fail-safe operation, the threshold-control terminals
are open. This reduces the hysteresis loop by causing
•
schematic and connection diagrams
COMMON Til 4 CIRCUITS
.....CC2
---""'--1
{NOTE)
Vee1
1>-+------....
I
I
I
I
Dual-I n-L ine Package
THRESHOLD
I
ALT
I
GND
TH~~~~~~~
NORM
CONT
OT
V~,
OUTPUTS
,v
lV
4Y
R1
1>-,------'-+-+ I
o-+J\I\,..,.......-,.
I-t-JVVIr"
OUTPUT
GND
THRESHOLD
INPUr
CONTROLS
1>-+-"""N-+-~H
I
I
IL-'- _ _ _ _ _ _ _ _ _ _ _ .J
1k
Note: When using Vee1 (pin 15), VCC2 (pin 16) may be left ~pen or shorted to Vee1 .
When using VCC2 , VC(':l must be left (I,pen Of connected to the thr~shold conttol pins.
10-25
TOPVIEW
Order Number DS75154J or DS75154N
See Package 10 or 15
~Nat1onal
Interface
~ Semiconductor
0575324 memory driver with decode inputs
general description
features
The DS75324 is a monolithic memory driver
which features two 400 mA (source/sink) switch
pairs along with decoding capability from four
address lines. Inputs Band C function as mode
selection lines (source or sink) while lines A and
D are used for switch-pair selection (output pair
VIZ or W/X).
•
•
•
High voltage outputs
Dual sink/source outputs
Internal decoding and timing circuitry
• '400 mA output capability
• DTLlTTL compatible
• Input clamping diodes
schematic and connection diagrams
r---~-'-----------'--~----------------t-------------ov~
.......- - - - - - - -.....- 0
r+'
MODE SfUCT
ADDRUS
lIIPurs
~r:~NO"~~t---t~~::::~
. .yetl"AIA
SELfL PD--++---lf-J
Dual-I n-Line Package
PI"""
GilD
Z
Z
is'''')
Dual-In-Line Package
DUT1'UTSOUlitEOU1"tUT DUmlT
Y
Yee
I:OLUc.
X
W
ISIIUIIC:EI MRS ISGUIICE) (Stllll)
AiiOiiu'nllPurs
nMlIIG
II.IID
1
1""1n
GNO 1 and GNO 2 Ire to b. used in parallel.
Order Number DS75324J
Order Number DS75324N
See Package 10
See Package 14
10-26
:~:rTW
~National
Interface
~ ·Semiconductor
o(/)
CTI
CTI
W
N
CTI
........
o
~
CTI
0555325/0575325 memory drivers
general description
The OS55325 and OS75325 are monolithic memory drivers which feature high current outputs as
well as internal decoding of logic inputs. Th"se eire
cuits are designed for use with magnetic memories.
W
N
operate at higher source currents for a given
junction temperature. If thiS metho.d of source
current setting IS not desired, then Nodes Rand
R'NT can be shorted externally activating an
internal re.sistor connected from V CC2 to Node R.
This .provides adequate base drive for source
currents up to 375 mA with Vet2 ~ 15V 01
.600 mA with Vec2 ~ 24V:
The circuit contains two 600 mA sink·switch
pairs and two 600 mA source·switch pairs. Inputs
A and B determine source selection while the
source strobe (S, ) allows the selected source turn
on. In the same manner, inputs C and 0 determine
sink selecti.on while the. sink strobe (S2) allows the
selected sink turn on.
The OS55325 operates over the fully military
temperature range of -55°C to +125°C, while the
OS5325 operates from O°C to +70°C.
Sink·output collectors feature an internal pull·up
resistor In parallel with a damping diode connected
to . V CC2' This protects the outputs from VOltage
surges associated with sWitching inductive loads.
features
The source stage features Node R. which allows
extreme flexibility in source current selection by
contro'lling the amount of base drrve to each source
transistor. This method of setting the base drive
brings the power associated with the resistor out·
side the package thereby allOWing the circuit to
•
600 mA output capability
•
24V output capability
•
Dual sink and dual source outputs
•
Fast switching times
•
Source base drive externally adjustable
•
Input clamping diodes
•
OTLITTL compatible
schematic and connection diagrams
Dual-I n-Line Package
~,'"
SOURCE
COLLECTORS
APDRESSA
OUTI'UTW
SOURCE
W
CnLlHTORS
"
"
~
$TRDMS
tOP'VIEW
ADDRESSfl.
~.t,-'-::j--r--i~
Order Number DS55325J, DS75325J,
DS75325N or DS55325W
See Package 10, 15 or 28
truth table
STAOIES2
~++--=j--t::---{,
ADDRESS INPUTS
SOURCE
...---+*"""....+~OUTI'UTZ
ADDRESS 0
SINK
OUTPUTS
STROBE INPUTS
SOURCE SINK
SOURCE
SINK
• •
c
0
51,
52
W
X
v
Z
L
X
X
L
H
H
ON
OFF
OFF
OFF
OFF
H
H
L
X
x
L
H
L
OFF
ON
OFF
OFF
X
X
X
L
H
OFF
X
ON
OFF
X
X
H
L
H
L
OFF
OFF
ON
X
X
H
H
OFF
OFF
OFF
H
H
H
H
X
OF,F
OFF
OFF
OFF
OFF
OFF
X
H '" high level, L "" low level. X '" irrelevant
NOTE: Not more than one output is to be on at anyone time.
10·27
CTI
....
co
M
It)
,....
en
c
~National
Interface
~ Semiconductor
D575361 dual TTL-to-M05 driver
general description
features
The DS75361 is a monolithic integrated dual TTL-toMOS driver interface circuit. The device accepts standard
TTL and DTL input signals and provides high-current
and high-voltage output levels for driving MOS circuits.
It is used to drive address, control, and timing inputs
for several types of MOS RAMs including the 1103 and
MM5270 and MM5280
• Capable of driving high-capacitance loads
• Compatible with many popular MOS RAMs
• VCC2 supply voltage variable over wide range to 24V
•
Diode-clamped inputs
• TTL and DTL compatible
• Operates from standard bipolar and MOS supplies
The DS75361 operates from standard TTL 5V supplies
and the MOS Vss supply in many applications. The
device has been optimized for operation with VCC2
supply voltage from 16V to 20V; however, it is designed
for use over a much wider range of VCC2'
• High-speed switching
• Transient overdrive minimizes power dissipation
•
Low standby power dissipation
connection diagrams
Dual-In-Line Package
Vee1
.,
V1
V2
Vee.
A2
GNO
Dual-I n-L ine Package
NC
TOP VIEW
TOP VIEW
Order Number OS75361 N
Order Number OS75361J
See Package 12
See Package 9
10·28
GNO
~National
Interface
~ Semiconductor
0575362 dual TTL-to-M05 driver
general description
features
The DS75362 is a dual monolithic integrated TTL-toMaS driver and interface circuit that accepts standard
TTL and DTl input signals and provides high-current
and high-voltage output levels suitable for driving MaS
circuits. It is used to drive address, control, and timing
inputs for several types of MaS RAMs including the
1103.
• Dual positive-logic NAND TTl-to-MOS driver
• Versatile interface circuit for use between TTL and
hi gh-cu rrent, high-vol tage systems
• Capable of driving high-capacitance loads
• Compatible with many popular MaS RAMs
• V CC2 supply voltage variable over wide range to 24 V
maximum
• V CC3 supply voltage pin available
• V CC3 pin can be connected to VCC2 pin in some
applications
• TTL and DTL compatible diode-clamped inputs
• Operates from standard bipolar and MaS supply
voltages
• High-speed switching
• Transient overdrive minimizes power dissipation
• Low standby power dissipation
The DS75362 operatesfromthe TTL 5V supply and the
MaS Vss. and Vee supplies in many applications. This
device has been optimized for operation with VCC2
supply voltage from 16V to 20V, and with .nominal
VCC3 supply voltage from 3V to 4V higher than VCC2 '
However, it is designed so as to be usable over a much
wider range of VCC2 and VCC3' In some appl ications the
VCC3 power supply can be eliminated by connecting the
VCC3 pin to the VCC2 pin.
schematic and connection diagrams
Dual-In-line Package
TO
OTHER
DRIVERS
INPUTA
{+--------J----.
0-----...-+.....-1
A1
VCC3
A2
GND
TOP VIEW
Order Number DS75362N
See Package 12
, Dual-I "-Line Package
TO OTHER
DRIVERS
+------__
NC
VI
NC
A1
NC
Y2
NO
VCC2
VCC3
A2
N&
GNO
-------~-----~~__oGNn
ONE OF 2 SHOWN
NC
TOP VIEW
Order Number DS75362J
See Package 9
10-29
~·National
Interface
~ Semiconductor
0575364 dual M05 clock driver
general description
The DS75364 is a dual MOS driver and interface circuit
that operates with either current source or voltage
source input signals. The device accepts signals from
TTL levels or other logic systems and provides high
current and high voltage output levels suitable for
driving MOS circuits. It may be used to drive address,
control and/or tim ing inputs for several types of MOS
RAMs and MOS shift registers.
shifting may be done with an external PNP transistor current source or by use of capacitive coupling and
appropriate input voltage pulse characteristics.
The OS75364 is characterized for operation over the
O°C to +70°C temperature range.
features
•
The OS75364 operates from standard MOS and bipolar
supplies, and has been optimized foroperation with Vcc,
supply voltage from 12-20V positive with respect to
VEE, and with nominal V CC2 supply voltage from 3-4V
more positive than Vcc,. However, it is designed so as to
be useable over a much wider range of V ec , and VCC2.
In some applications the VCC2 power supply can be
eliminated by connecting the VCC2 pin to the V CCl pin.
•
•
•
•
Inputs of the OS75364 are referenced to the VEE ter·
minal and contain a series current limiting resistor. The
device will operate with either positive input current sig·
nals or input voltage signals which are positive with respect to VEE' In many applications the VEE terminal is
connected to the MOS V OD supply of -12V to -15V
with the inputs to be driven from TTL levels or other
positive voltage levels. The required negative level
•
•
•
•
•
Versatile interface circuit for use between TTL levels
and level shifted high current, high voltage systems
Inputs may be level shifted by use of a current source
or capacitive coupling Of driven directly by a voltage
source
Capable of driving high capacitance loads
Compatible with many popular MOS RAMs and MOS
shift registers
Vcc, supply voltage variable over wide range to 22V
maximum with respect to VEE
V CC2 pull·up supply voltage pin available
Operates from standard bipolar and/or. MOS supply
voltages
High·speed switching
Transient overdrive minimizes power dissipation
Low standby power dissipation
connection diagrams
Dual-in-Line Package
Dual-In-Line Package
V CC1
NC
A1
v"
A2
TOP VIEW
NC
v,
NC
V1
NC
A2
NC
NC
A1
NC
TOP VIEW
Order Number OS75364N
Order Number DS75364J
See Package 12
See Package 9
10·30
NC
~National
Interface
~ Semiconductor
OS75365 quadTTL-to-MOS driver
general description
The .OS75365 isa quad monolithic integrated TTL-toMOS driver and interface circuit that accepts standard
TTL arid OTL input signals and. provides high-current
and high-voltage output levels suitable for driving MOS
circuits. It is used to drive address, control, and timing
inputs for several types of MOS RAMs including the
1103.
• Capable of driving high-capacitance. loads
The OS75365. operates from the TTL 5V supply and the
MOS Vss andV BB supplies in many applications. This
device has been optimized for operation with V CC2
supply voltage from 16Vto 20V, and with nominal
VCC3 supply voltage from 3V to 4V highe.r than VCC2 '
However, it is designed so as to be usable over a. much
wider range of VCC2 andV CC3 ' In some applications the
VCC3 power supply can be eliminated by connecting the
VCC3 pin to the VCC2 pin.
• VCC3 supply voltage pin available
• Compatible with many popular MOS RAMs
• Interchangeable with Intel 3207
• VCC2 supply voltage variable over wide range to 24V
maximum
• VCC3 pin .can be connected to VCC2 pin in some
applications
• TTL and DTL compatible diode-clamped inputs
• Operates from standard bipolar and MOS supply
voltages
• Two common enable inputs per gate-pair
features
• High-speed switching
• Quad positive-logic NAND TTL-.to·MOSdriver
• Transient overdrive minimizes power dissipation
• Versatile interface circuit for use between TTL and
high-current, high·voltage systems
•
Low standby power dissipation
schematic and connection diagrams
Dual-In-line Package
+---........
TO OTHER {..,.._ _ _ _ _ _ _
DRIVERS
.....
V4
~E2
A4
14
INPUT'
2E1
.3
Y3
VCc3
lE2
.2
V2
GNO
13
0------....-t.........--1
....
ENABLE El o---'-~--+"
ENABLE EZ
--+".....
<>---11-....
VI
.,
lEI
TOP VIEW
TO OTHER {
DRIVERS
PosmlleLogic: Y"'A'El'E2
Order Number DS15365J
or DS75365N
See Package 10 or 15
ONE OF 4 SHOWN
10-31
('I')
.....
co
co
en
C
~National
Interface
~ Semiconductor.! ,
M
o
CO
CO
en
c.......
M
o
CO
~
C
057803/058803, 058813 two phase oscillator/clock driver
general description
The DS7803 is a self contained two phase oscillator/
clock driver. It requires no external components to
generate one of three primary oscillator frequencies
and pulse widths. Other frequencies can easi Iy be
obtained by programming input voltages. Three sets of
outputs are provided: damped and undamped MOS
outputs and TTL monitor outputs. The MOS outputs
easily drive 500 pF loads with less than 150 ns rise and
fall times. In addition the outputs h.ave current limiting
to protect against momentary shorts to the supplies.
The DS7803 and DS8803 are available in a 14-lead cavity
DIP. The DS8803 is also available in a 14-pin molded
DIP. The DS8813 comes in an 8-pin molded DIP,
providing damped MOS outputs only.
features
•
•
•
•
•
•
Two phase non-overlapping outputs
No external timing components required
Frequency adjustable from. 100 kHz to 500 kHz
Pulse width adjustable from 260 ns to l.4l1s
Damped and undamped MOS outputs
TTL monitor outputs
block and connection diagrams
057803/058803
Dual~ln~Line
Package
.-.....__+'''-0 v~
14 Vss
INHIBIT
WIDTH
CONTROL
MUS
DAMPED.p.
2
13 TEST
,
12 FRED
CONTROL
MOS",
V"
TTL'il,
'--<1>-+::..0 GND
R,
+--,---,\I\"IIr--t.::.'
-0 ~2~PED 1>,
R,
TTL¢:!
MDS¢2
Voo
...1-_.....,.,"",...-+'=-0 ~:PEO 92
'-----+'-OMOS.;o,
'------!-'-<;) MOS2'
TEST
V"
TTL 91
voo
MOSo 1
Voo
,
MOSQ2
MOS
DAMPED
DAMPED
V'"
INHI81T
OS8817
Dual-In-Line Package
FREDUENCV
CONTROL
PULSE
1
INHIBIT
WIDTH
PULSE WIDTH
CONTROL
,]
10
TEST
MOS
DAMPED
FREO
CONTROL
OUTPUTS
10
Q,
TOP VIEW
Order Number OS8817N
See Package 12
V"
Voo
TEST
01)
01)
~
The DS7807 and DS8807 are available ina 14·lead
cavity DIP. The DS8807 is also available in a 14-pin
molded DIP.
FREQUENCY
CJ)
INHIBIT
10-33
I
~National
App Notes/Briefs
~ Semiconductor
THE SYSTEMS APPROACH TO CHARACTER GENERATORS
A huge new market. for man/machine interfaces is
being'created by the increasing availability of low
cost data processing through computer time
sharing, LSI cat'culators, minicomputers and digital
business and control systems. In turn, the pressure
is on to design CRT terminals, displays and teleprinters that are at least as compact and inexpensive as the new data processors.
MOS ROMS AND REGISTERS
Large capacity, high speed, and bipolar compatibility strike directly at the problems involved in
lowering data terminal costs. To generate and update readouts with many characters and symbols
takes thousands of bits of storage and fast manipulation of data and control signals. If this capability
is supplied in 'a central processor, it must be paid
for in the form of central system overhead and
communications costs. Using pre-LSI memory
techniques in the terminals, however, can easily
double the cost of each console.'
Mas integrated circu it producers are in the thick
of this competition. They have begun making
read only memories and shift registers with enough
storage capacity to put an appreciable dent in
terminal and printer costs. Entire alphanumeric
character fonts and CRT refresh channels now can
be fabricated as single-chip arrays. Low threshold
MaS processes and designs have been refined to
make the storage arrays more compatible with
bipolar logic and standard power supplies.
Storage capacities per MOS chip have increased at
least tenfold in the past few years, with comparable reductions in assembly costs. By the close of
1969, MaS/TTL character generators cost about
half as much as those bu ilt with bipolar devices.
The newest ROMs (read only memories) for charactergeneration represent the integration of some
3,000 diodes ,and 50 packages of IC gates. One
terminal manufacturer who made the changeover
late in 1969 replaced six large' printed circuit
boards with one plug-in card.
These developments have won MaS a place on the
alphanumeric side of the readout family tree in
Figure 1 (and some inroads are being made on the
other side-see Appendix in this App. Note. In fact,
MaS has pushed beyond the state of the art.
MaS/TTL assemblies can generate characters
faster than they can be handled by moderately
priced CRT video circuitry or printer mechanisms.
However,the increased storage capacity and speed
also make higher performance systems feasible.
For exarnple, designers are considering larger fonts
that make characters more legible. Large fonts
have generally been economically impractical in
the past because even a small increase in font size
can double the memory size needed.
..
'"
DISCHAAIIE
,
Q
(')
:r
...DIDI
...
n
...
CD
The largest MaS ROMs mass produced last year
stored 1024 and 2048 bits-general purpose sizes
used for table lookup, microprogramming and
random-logic functions as well as character genera·
tion. A typical generator contained three 1024·bit
ROMs, such as National Semiconductor's SKoo01
and SK0002 kits (see Table 1 and Figures 2. and
3). Generating the standard 64 ASCII-selected
characters in a 5 x 7 font requires a storage capac-
Hl~ENT
NEON
...
lUSE
SEGMENTED
"
RASHRSCAII
DISPLAY
TERMINALS
(Ht.MMERORUU)
8ILLlIOAR(lS
VERTICAL SCAN
TAPEPIlNCIfES
DISPLAYS
$.P!lINTERS
SCAN·TYPE
ElPANHS
jFIlTUAE)
READOUT
TYPEWRITERS
''TICICEflTA.P£''
DISPLAYS
VECTOR
IlISFLAY$
&HLf.f'flINTEFIS
TH~RNAl.
~~~tTROSTATtC.
OSCillOSCOPES
RADAR,
MIUTARY
He
LE_tnlIlT·nIUTnNG
EL-EI.EC11'lQLUUJNESCEItT
Figure 1. ,'Oisplay'Familv Tree
11·1
HI
en
"-
....IVo
"CD
C
CD
Two new soon-to-be-announced ROMs are the
MM5240, storing 64 x 8 x 5 bits, and the MM5241
storing 64 x 6 x 8 bits. Each chip also contains
decoding logic and sense amp Iifiers (as do the
1024 and 2048-bit chips). Thus, one ROM is
ample for a standard 5 x 7 or 7 x 5. font. The
added capacity can implement special needs, such
as dropping comma tails below the other characters and symbols. But its main purpose is in
providing the logic and programming flexibility
that enables ROMs to be operated in tandem to
generate the larger font sizes indicated in Table 1.
The additional capacity costs little in terms of
silicon real estate because these devices are made
by low-threshold processes with p-channelenhancement mode MOSFETs as the storage
elements-the most LSI-able type of MOS.
ity of at least 5 x 7 x 64. Each logical "]" bit
stored in the ROM produces a black dot on a
printout or a bright spot on a CRT screen, and
each "0" bit a blank space.
(!)
"-
....CD
(,)
IV
"IV
.c
(.J
Table 1.
CHARACTERISTICS
Raster Scan
SKOOOl
or MM524Q
Vertical Scan
SKOOO2
or MM5241
7,5
.c
(,)
7,9
IV
9,)
0.
c(
static ROM required
MM5240
(2 requiredl
MM5241
10 x 8
Vertical Scan
static ROM required
MM5240
9 x 11
Raster Scan
MM5240
(3 required)
Vertical Scan
MM5241
In the past, when diode matrixes were used as
character generators, the 5 x 7 or 7 x 5 fonts gave
the best cost/legibility tradeoff. Because the new
ROMs lower the cost per function, the 8 x 10 font
will probably become the most attractive.
(2 required)
VJ
CD
Vertical Scan
Raster Scan
11 x 9
.c
MM5241
(2 required I
8 x 10
....ellen
>
Raster Scan
static ROM required
en
E
PARTS REQUIRED
FONT
5, )
S
e0.
ROM Combinations for Various Fonts
(2 required)
static AOM required
(3 required~
12 x 16
Raster Scan
MM523
16 x 12
Vertical Scan
MM5241
static ROM required
(4 required)
The input-output configurations of the MM5240
and MM5241 are outlined in Figure 4 for a standard ASCII-addressed font. The 6-bit ASCII code
words will address any of 64 characters (2 6 ). The
control logic generates the three additional address
(6 required)
~
o
'ItI
Z
B, ' " 1 2 J 4 5
82~.OOO.
c(
B
••
00.
'---- • • 0 0 .
a.-eo.o.
B _____ eoo ••
a:/:gg~:
.,/
All GATES ARE
IIM80UO OR DM8BIO
LINE RATE
ClOCKINrUT
UNESELEtTCOUNHR
Figure 2b. Character Generator For Tape Printers and
Other Vertical Scan Applications
Figure 2a. Three-ROM Raster Scan Character Generators
11-2
»
z
~
o
CHARACTER SELECT
I,
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
I,
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
I,
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
I,
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CHAR.
0
8
4
12
2
10
6
"
1
9
5
13
3
11
7
15
ROW
16 III
-t
:::T
CD
CJ)
<(II
S'
... :. ..·•••• i···i,
.: .....
....i••: .: ......
.: ••.,•• ... .....
•.....
:,
:
:
::
:
:
••
: :....·· ··
: : '::
:.- : .: :...: i
..-:':':.. ::...:.:
... :........:
:........ : : :': : .:. i::.. ·
····...··: ··..·.... .....
. ...·. :..:
·.. .....··: .... ··:
...· .·....... :: ····· ·.....::: ...·...
····· .........:·.... :: : ·· ·.·....
: ':
··
·
·
·
·
. .........
. ....
......
·....•••..••••
.... ..·.. :....::....:: .... .::.. ·.·.. ·:.-.:·:: .::....
1:·
: ••....
:•••••
,••••
.
..
.
.
: ::, :
:: .. :.... : · :.:.: : :.... ..! -..:. i.. · .
.....·......
.....::
... ..'. ·......:....
·.... :·..........:.···i·
....
.....
.
.•.
...... ...·....:............. :::: i.···..
:.· .
... ... ...'i
.:' ,S
:
,
:.:
o
:::: .... = ..... ..... ::
=.. :
3(II
»
...
o
'C
'C
Q)
n
:::T
g
(")
:::T
...
n
....CD
Q)
Q)
...
C)
CD
:::I
...
....o
CD
Q)
Figure 3a. Raster Scan Character F'ont
ii1
CHARACTER SELECT
I,
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
I,
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
I;
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
I,
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CHAR.
0
8
•
12
2
10
6
I.
1
9
5
13
3
11
7
15
o
1
...:...-i':.....!:::.:::
. .."..........
·!....!:! :i···: .,.:
:.... .:. :.... :. : ..... .·.. !i····
...
:
.
'
.!:
i···:.:
i···
I··.:
i···:
·
:
..
..
·.......... ...... .....
.... . ...· ..... ., ... . .............
.... ... ...
.::. ....,:. ::...
.... .....
: ..
·.. .....· ··· ··..
·
·
:·· .....
·
.....
.
·
·
.....
·
· .....
.
". ··i·· .:
·· · .. ·.. · ··
·
:.... : : ........................ . ... ....
...·• .I"".. ·::.....·:: .··....·
i···· :.: 1. •...::i·:·:.. :....:
.•.• :::. ··i··
!, ••!':.:..: .i....i ..:: .:...
: ::
: .. .
·
.....
...
..
....
.
...
.
.
...
..
...
.
..
.
..
..··:. .·· ... .. . ·..... ·....·i ····1.·.... .·· ···..:
.
i,..•.! ·........
·....:...: · ··.. ......· . :...: ..· ...... ...· ·...·· ·...···· ··· ··
'
o
1
Figure 3b. Vertical Scan Character Font
11-3
III
...
...
en
o
+"
III
Q)
bits needed to select the individual lines or columns of dots that form the characters in the
Also, special requirements of data entry and output for display formatting and editing can be
implemented much more easily with registers than
with physical delay lines. Data bit positions in the
recirculation loops are maintained in alignment
and can be monitored and modulated precisely by
the control logic (one recirculation loop is needed
for each data bit-six loops, for example, in an
ASCII·addressed systeml. Data entry and output
for display or transmission thus becomes a
straightforward exercise in logic design.
c::
Q)
(!).
...
Q)
+"
(J
DATA
~
OUTPUTS
III
.c.
U
o
+"
.c.
~
...o
LINE ADDRESS
INPUTS
CHfP ENABLE
Figure 4a. MM5240
Element
RECIRCULATION lOOP
Raster Scan Character Generator
DATA
INPUT
16 BITS!
0.
0.
«
en
E
Q)
6 LINE ASCII
INPUT
lJ
+"
>
C/J
Q)
.c.
tO
~
DATA
OUTPUTS
en
UNESHECT
COLUMN ADDReSS
INPUTS
"Figure 5. Basic Digital Character Generator and CRT
Refresh Memory
CHIP ENABLE
Figure 4b. MM5241
Element
BIPOLAR COMPATIBILITY
Vertical Scan Character Generator
A dynamic register is one that must be clocked at
some minimum frequency. Data is rc!Dined in the
form of charge storage and the charges would
eventually leak out of the storage nodes if not
re·established. In contrast, the ROMs being dis·
cussed are static devices, generating an output only
when addressed. Specifically, they are designedand programmed to be sequenced by TTL ICs.
Furthermore, th)}ITew generations of ROMs and
registers accept/and put out bipolar level signals
and operate off +5 volt and -12 volt power
supplies.
I
Z
«
5 x 7 X 64 dot matrix. The output bits forming
each dot line or column are presented in parallel.
The parallel outputs are serialized by a TTL regis·
ter and used to control the CRT beam or the
printer mechanism. To simplify the selection
process, the ROMs are programmed to generate
the lines or columns in the correct sequence when
addressed by the sequential outputs of a TTL
counter.
As for registers, they became quite popular during
1969 because a CRT refresh memory of up to
about 5,000 bits-enough for a display of more
than 800 characters-could be built less expen·
sively with MOS dynamic registers than with delay
lines 2 This was achieved with registers containing
200 storage stages per chip. During 1970, dynamic
registers up to 512 bits long will go into mass
production, giving rise to predictions of significant
savings in refresh memory costs. Whether savings
that large can actually be realized will depend
upon how quickly the new devices catch on and go
into volume production.
These features eliminate any need for special
level-translating circuits between the MOS and
bipolar devices. Also, special pOlfl(er supplies are
not generally requ ired because ±ii 2V as well as
±5V supplies are usually provided in terminals for
other parts of the system. Such compatibility is a
convenience and a cost saver in any digital system
containing MOS storage subsystems and bipolar
logic, since it mi,limizes the interface and drive
complexity. In terminals, though, compatibility is
practically essential for efficient operation and
lowest cost per function.
First, as the detailed system diagrams show, many
of the interconnections. have a MOS device at one
end and a TTL device at the other, so that a large
number of level translators would be needed if
they were not compatible.
Aside from cost per function, other pertinent con·
sideration are temperature sensitivity and func·
tional flexibility. In a refresh memory, register
outputs are fed back to the inputs. On each recir·
culation, the data readdresses the ROM, regenera,..
ting (refreshingl the display (Figure 51. The recirculation times must correspond to the CRT scan·
ning time to keep the display legible. MOS register
delay times are relatively insensitive to tempera·
ture variations because they are established by
system clock rates rather than physical parameters.
Second, several control logic operations must
occur between memory outputs, and the outputserializing device must operate at least six or eight
times as fast as the word (dot line or columnl
output rate of the' ROM. Obviously, if high speed
11·4
control logic-preferably TTL MSI devices such as
single-chip binary counters and 8-bit parallelinput/serial-output shift registers-were not used,
the character gef)erating process would be slowed
excessively. This would limit the number of characters that could be displayed .in a CRT refresh
cycle or printed out in. a .given time; The new
generation of MaS ROMs can deliver up to eight
bits in parallel in about 700 nanoseconds, compared with a microsecond or more for last year's
models. Logic speeds around 10 MHz are therefore
desirable (several tirnes higher than the speect that
can be achieved by MaS gates.) Likewise,dynamic
registers can now easily be run at rates· above
2 MHz-double the speed of early mass produced
registers-so the logic controlling refresh storages
must also be faster.
,.
As before, coded data from a communications link
or the console keyboard passes through the registers and addresses the character generator. In these
examples, the 6-bit ASCII input and the 3-bit
control logic input generate raster scan character
formats that allow a conventional TV man itor to
be used as a display. Communications codes other
than ASCII can be used.
'
If the ROM contains a 5 x 7 font, each 5-bit character line output will form five horizontal bright
spots on the CRT. That is, each ROM output
generates one-seventh of each character in a row of
displayed characters. The output is'·serialized by
the TTL register and used. to' intensity modulate
the CRT beam 'as it sweeps across the screen.
The improved compatibility and higher speed are
I~rgely due to better design and processing of the
input and output stages of. the registers and the
sense amplifiers of the ROMs. They don't increase
the complexity of the MaS circuitry, unlike other
techniques for increasing MaS speed, and there'
fore they have permitted the capacity increases
cited.
MlOOP
DATA
INPUT
(I BITS)
The net benefit to the system designer of this
approach t;-MaS design is that it enables the
system designer to capi~alize on. the best features
of each technology-MOS storage for high density
and low cost, and TTL for high speed processing
of data and control signals. This is what produces
lowest cost per function in most digital systems.
Figure 6. (M-NI+N Technique for Large Page Displavs
The refresh memory registers are divided into M-N
and N sections to f)lcilitate page displays. M is the
total number of characters displayed in several
rows (lines of the pager and N is the number of
characters in each row. To ·form such a display
with single-loop registers, as in .Figure 5, would
take seven recircul
(/)
CD
,r:.
t-
O
~
,
Z
c(
Now, the contents of the N register are not returned to the input of the N register. Instead, they
are fed back to the input of the M-N register and
this register is clocked to load the N register with
the second group of N characters. The M-N register
is then held still while the N register recirculates
seven times to generate the second row of characters on the display. After all M characters are on
the display, the first group of N characters is
reloaded into the. N register and the entire process
is repeated to refresh the display.
Human factors-chiefly the eye's response timedictate that the display be refreshed at least 30 to
35 times a second for good legibility. Most designers prefer to refresh at 60 Hz power line .fre·
quency because it is generally the most convenient
frequency.
As shown in Figure 7, the raster scan 'system uses
nine clock intervals to generate a row of characters
on the display. Seven are for the high-speed recirculations. During the other two intervals, the
first N characters are fed back from the output of
the N register to the input of the M-N register
while the N register is loaded from the M-N register with a new row's worth of characters. Si nce
two intervals are used for this operation, the registers operate at only half the character rate. The
rest of the time, the M-N register is chargequiescent. Its average clock frequency is only
about .11 % of the character rate.
Besides generating the line address inputs (that is,
the number of recirculations of the N register), the
control logic keeps track of the number of dots
and spaces in he output bit stream_ The spaces
between characters in a display row are inserted as
"0" bits when the ROM outputs are serialized by
the TTL register. The counters also control the
loading and recirculations of the MOS registers in
the refresh memory subsystem.
In other words, most of the refresh memory
(perhaps 90% in a large display system) operates at
only half the character rate (say 1 MHz instead of
2 MHz) only two-ninths of the time. The savings in
the drive network alone can be judged from the
power-frequency plot for a typical MOS dynamic
register (Figure 8)3. In addition, the designer can
A mUltiple row raster scan display could be generated with the M-Ioop technique in Figure 5 but,
the implementation is difficult and impractical.
This technique is more appropriate for single row
displays. Using this method of display, all M characters to be displayed must recirculate seven times
to generate a 5 x 7 horizontal scan, so all stages of
the registers must operate at the full character
rate. To form several rows with a single-loop
memory requires an interlaced scan rather than an
ordinary raster scan. The first series of 5-dot lines
are generated by the first N character outputs as
before, but the next set of N inputs to the ROM
will generate the first group of 5-dot lines in the
second row of characters on the display. There·
fore, the beam must jump to the new line position.
To display four rows of 5 x 7 characters, for
instance, would require a staircase generator that
would step the beam by the height of nine scan
lines (seven dot lines, plus two blank spacing lines
between rows)" three times after the initial scan.
"rIT~I J'I-"I'Cl lil
VpU",·,ov
V~·-15V
II
:i
Ii
0."
1.001
0.I11III1
I
II
lDO
1,DOD
MAXIMUM OPERATING FREQUENCY IKHd
Figure 8. Power vs Frequency Plot of Typical MOS
Dynamic Register
increase the number of characters generated per
refresh cycle, for a larger display, or increase the
number of dot lines, for a larger font, or both.
11-6
Remember, though', that dynamic registers must
select the dot lines and the 6-l1it ASCII code from
be clocked to retain data; How long can the M-N
the2~6 (28 ) word locations in each ROM_ These
register be, turned off? Long enough for practical
applicatipns_ The guaranteed minimum frequency
is temperature dependent, since temperature
affects charge-storage time_ The minimum for
National Semiconductor's MM-seriesregisters is
500 Hz at 25°C, rising to 3 kHz at 70°C (maximum operating temperature is'125°C, but that is
not a display environment)_ At room temperature,
the registers can safely, be quiescent for as lonll as
2 msec_ (The typical MM register will actually hold
data for 10 msec_) Suppose the N register stores 40
characters and operate,s at 2 MHz_The quiescent'
p~riod can be as shortas 40 x 7 x 0_5 ; 140 /-IS. ,If
standard TV raster timing ,is maintained then the,
qu ieseent period will be 7 x 63 ,/-IS ; 441 jJ.S_
Obviously, the designer has great leeway in character rates, operating temperatures, and register
capacities,
two additional bits are supplied by the A andB
outputs of a TTL binary counter
DM8533 (SN7493) and the counter's C output is
used to commutate, the MK001 and MK002. The
ROMs are enabled by an output at the TIL logical
"0" level. Thus, with the gating shown, th~
MK001 is enabled during'the, first four of seven
line-rate clock inputs and the MK002 during the
remaining three inputs.
The MK003 is continuously enabled by grounding
the chip-enabled pin, CEo ,It mu'st generate a l:bit
output for each of. the 7 x 64 dot Iines in the
,64'character set, which implies it 9-bit address_
Rather than produce 'a special ROIlil just for this
function-:which would make it expensive-the
MM521 was' programmed to generate 256 2-bit
outputs from the 8-bit address. The counter's C
output simply gates out the unwanted bit.
Other applications in displays for clock modulation include. input-output' buffering of data during
data reception and transmission,2 or during dis·
play editing 'and formatting through the console
keyboard. The register rates can be adjusted, via
control logic to accommodate differences between
I/O and recirculation rates. Note that the gating in
Figure 7 permits data entry under TTL control
into either register section.
..
....
....
Q)
For a, 5 x 7 font, the new single-chip character
generators are simply programmed to generate all
5 bits in each dot line, from a9,-bit address, Standard programming provides the 64-character
ASCII set, but special characters can be substituted by changing the stored dot patterns. The
reprogramming process consists of altering an
etching mask that controls gate insultation thick'
ness, in the MOS field effect transistors of the
storage array. If the, oxide is left thick, the transistor will not switch when selected by the decoding
logic, generating a "0" output from that location.
CHARACTER GENERATION
The first generally available MOS character generators were kits such as those in Figure 2, using
three 1024-bit ROMs (MM521). Although singlechip generators were being devek>ped in 19~.
they were in very short supply. The kits cost aboot
half as much as diode generators and thus allowed
terminal manufacturers to start the changeover to
MOS_
Q)
n
CD
'
C')
CD
::s
CD
Q)
o
iil
Figure 9 indicates why the storage capacity of the
MM5240 is 5 x 8 x 64 rather than 5 x 7 x 64-each
ROM can ,generate half of the 8 x 10 x 64 character set:, The ROMs can be addressed simulta<
neously. as bef9re, and be' commutated by the
L ! _5241
.. I-·.... -·I-~
The kits are 'also a good place to, begil, describing
character generat9foperation in' this applicaticm
note, b~use they provide an "explo<;led view" of
multi:ROM generator operation. Similar tech.
niques wit,1 b~ needed"to buVdlarger fontswith the
new devices. Th~ external gating fimctio~s shown
in FigiJr~;2'are,not needed .for these.fo~ts when
the MM5240and ~M5241~~e used: The ';ai'semb!y'"
'the dot patterns taken care of ,in .the
programming of the ROMs. Howev,er, to generate a
large font, such as $ x'10 or 12 x 16, with tile new
ROMs will require operation of two, to four ROMs.
of
o::r
:
I
'..
MM5241
-j
(5.1'
• IlID RASTER SCAli CHARACTER
....,,, ....
.
':!!~' i : : ~i'
is
.
,
______ t.v. . .I..... :.. ___ _
fIlM_I
i•
:
-....... .-
Ih&l.
~1
'h'l
~
Each MM521 in the SKOOO1 raster scan kit can
store 256 4-bit dot patterns. As the inset letter
"N" in' Figure 2a indicates, the MK001 ROM
stores the first four 4-dot line segments of each of
the 5 x 7 characters, the MK002 sto~es 4·bit
segments of the other three·dot lines, and MKOO:3
sup'plies the fifth bit of each of the seven-dot lines.
All ROMs are addressed simultaneously.
11.12 Yf'R1:ICAL SCAN
Figure 9. Multiple ,RO~ Character, Fonts
cont~ol logic'to put out the 8-dot horizo~tallines
in the correct sequence. For very high speed char·
acter generation, the addressing of the ROMs can
be skewed or overlapped so that the outputs from
one are generated while the inputs to the other are
being decoded. The only real limitations to the
The 6-bit ASCII code was devised to select 64 (2 6 )
characters, However. an 8-bit address is used to
11-7
III
character generation rates achievable with such
techniques are the speed of the bit serializing logic
and the bandwidth of the video circuitry.
.
....
CD
u
f!
as
.t:.
(,)
S
.t:.
U
.
as
o
g;
~
en
E
...en
CD
>
en
CD
...
.t:.
..
o
I
Z
c:(
the DM8533 TTL binary counter will reset on the
count of 16. And with the gating and interconnections shown, the column select cycle is:
CONTROL LOGIC
Counter Outputs DCB
ROM. Enabled
DCB
000
001
010
011
100
101
MK004
MK005
MK004
MK005
MK006
reset (instantaneous)
Starting with the dot/character or dot and space
counter in Figure 7, the counter m.oduli are set to
accomplish the following functions:
• The dot and space counter determines the num·
ber of horizontal spacing bits between characters in the character row on the display. Its
output is loaded into the parallel inputs of the
DM8590 serial·in/parallel·out shift register. For
a 5 x 7 font, for example, a modulus of six
inserts one spacing bit (logical "0" bit) between
each 5-dot group in the serialized stream.
During line recirculation periods, this counter
also drives the N counter at the character shift
rate of the N register.
A CRT beam can be intensity modulated by the
serialized output, as. in the raster scan technique.
However, the electron beam traces either a sawtooth or pedestal·type scan pattern on the screen
(Figure 10). Every column of each character in the
display line is scanned in sequence, starting at the
left-hand side of the screen.
• The N counter causes the line select counter to
change state at the end of every recirculation of
the row data in the N register. It generates a
pulse at intervals of 6N dot clock periods
(assuming one spacing bit).
The' sawtooth scan is straightforward, but the
pedestal scan requires that the bit order be reversed in the second and fourth columns. To do
this, the outputs of the MK005 ROM are simply
connected to the output buses in the reverse order
(Le., output 1 to bus 7, output 2 to bus 6, etc.).
• The line select counter generates seven sets of
the three ad
en
II)
.t:.
tO
~
2
«
The data transfer from the character generator to
the bipolar memory in Figure 12 is accomplished
by sequencing the column address lines and enabling the 'appropriate memory simultaneously.
Each pair of DM8550s (SN7475s) then contains
the data for one of the five columns in a character.
The DM8842 (SN7442)-one in 10 decoder provides the decoding functions which are connected
to the enable line on the quad latches.
A second consideration which should not be overlooked in systems cost is tile compatibility of
ROMs in multi-package character fonts. Optimum
ROM usage and organization will result in lower
systems cost. ROMs will also find applications in
micro-programming and code conversion where
synchronous operation is preferred.
LARGER, FASTER SYSTEMS
Most low cost terminal designs have been based on
the 5x 7 font because of the high cost of diode
matrixes and wideband video circuits. But it is by
no means the most legible font. A 5 x 7 font is
acceptable for applications in which the display
changes slowly, but human engineering studies
indicate that it causes severe eyestrain when an
operator reads rapidly changing data.
The 8 x 10 font is much better and 12 x 16 is
almost optimum for legibility. Small, lower case
characters can be sharply. defined, too, and they
almost appear to be drawn with continuous
strokes.
System designers considering these fonts for lowcost displays run, at present, into CRT cost problems. The least expensive displays are televisiontype CRTs with limited video bandwidth. Bandwidth also limits the number of characters that can
be displayed simultaneously. Not counting the
times required for .beam retrace and functions
other than character generation, which reduce the
time available in a refresh cycle for dot handling,
the necessary bandwidth is roughly:
The greatest portion of the discussion has dealt
with a 5 x 7 font. A full 64 character display can
be coded into a single MaS package. Now that LSI
has entered the scene, we see a different trend
towards larger, more stylized font. The economy
of MaS ROMs will provide the customer with a
more legible character font at the present cost of
"discrete" character generators. An analysis of the
most practical solutions to various fonts are tabulated in Table 2. The part types which have been
used to generate a 64 x 7 x 5 raster scan font are
the SKOOOl-3 ROM kit or the MM5240 which is
under development. The vertical scan font is satisfied by the SK0002-3 ROM bit or the MM5241
which is under development. If we examine the
other possible fonts, these same two mono I ithic
elements will satisfy the requirements if they were
64 x 8 x 5 and 64 x 6 x 8 respectively. Therefore,
the added memory storage is being incorporated
into the MM5240 and MM5241. In some of th~se
cases the font is scanned in the horizontal dimension while in others the font is scanned in the
vertical dimension. You find both the 8 x 5 and
6 x 8 elements capable of satisfying the font
matrix requirement. Since all the ROMs listed are
static by design, there are no special clocking hardships induced with the solution of any of these
larger fonts. This is not true for all dynamic ROM
solutions.
TV-type CRTs have a maximum bandwidth of
about 4 MHz, of which only about 2.5 MHz is
generally useful. If one uses a 5 x 7 font with one
spacing bit (6 x 7 total) at a 60·Hz refresh rate,
each displayed character needs 2.52 kHz of bandwidth, so the limit is about 1,000 characters. In
contrast, the new ROMs take as little as 700 nanoseconds to generate a dot line, or about 5 J.l.S per
character. That's ·fast enough to generate 200,000
characters a second, or a display of more than
3,000 characters at the 60-Hz refresh rate. The
actual dot rate in the serial bit stream to the CRT
can approach 10 MHz. And if larger fonts are
generated in some multiplexed addressing mode,
the required bandwidth can be much higher.
As mentioned before and shown in the table, the
same ROM element is used in both raster scan or
vertical scan applications. If we recall the design
solutions showing the refresh memory and character generator for a 5 x 7 display, the first thing
Luckily, these problems are not insurmountable
and there are alternatives to using oscilloscopequality CRTs or storage tubes, which are fine for
high performance applications but too rich for
low cost terminals.
BW
= (dots and spacing bits per character)
X (characters per display row or page)
X (refresh rate)
11-10
The register stages can either shift the bits to the
serial output for recirculation or store the data
indefinitely. Hence, displayed charac.ters can be
swept along a line of indicators, "frozen'" on a
stationary display, or made to reappear period-.
ically at any desired repetition rate.
Obviously, the designer can prop the refresh rates.
New eRTs with longer persistence Ilhosphors
facilitate this. Also, CRT manufacturers have been
responding to the new terminal market by working
on bandwidth improvements, and, they are appar·
ently going to reach 10 MHz in moderately priced
video systems soon.
A code-cohverting/character-generating ROM can
be placed at the register input, to display numbers
and symbols or alphanumerics. A designer can get
almost as much flexibility from a lamp or panel
display as from a CRT display. In fact, th"e first
application of the MM5081is controlling a matrix
of neon lamps in a moving billboard display.
Finally, the designer is not obliged to display his
characters digitally just because he uses aMOS
ROM. Don't forget that the ROM is really workiAg
as a code converter, generating a 35·bit machine
language code from a communications code. The
language translation can be whatever the situation
requires.
Some applications for character generators in instruments' are also cropping up. Displaying range
scales on an oscilloscope is a good idea that can be
improved upon with the new ROMs. The display
frees the operator of the chores of menta"y'c!lIculating scale factors and manually writing these on
scope photos. With an alphanumeric font, the
camera can also record information such as test
conditions. date and time of test, identification
numbers, etc. Photo sequences anp the data
needed to analyze the curves can be coordinated
automatically.
A" that ,need be done is update methods used in
analog displays, which form characters with
strokes rather than dot lines or columns. The
ROMs can be programmed such that the bit outputs, when integrated, control X and Y ramp
generators. The slopes of the ramp functions are
determined by the number of bits in a sequence
and the lengths are determined by the locations
chosen for turn-off bits. As in the vertical scan
technique, the ROM is addressed at the character
rate.
Even though some characters can be formed with
one or two strokes (I, L, etc.l. equal 'time should
be given to a" characters in a page display to keep
the character rows aligned. A standard sized area
of the MOSFET array, such as 6 x 8 or 5 x 8
should be used for each character. Most patterns
would thus be a combination of stroke and nostroke outputs. The single-chip fonts' have an
8-stroke capacity for each of 64 characters wh ich '
is more legible than the standard segmented type
of instrument readout, since slant lines could be
generated wherever needed.
Similarly, a ROM can be programmed to display
standard curves for go-no-go equipment cheCkout
operations. For example, if a radar's pulse ampli·
fier should have certain output characteristics, the
ROM generates the correct output curves through
a digital-to·analog converter and stroke generator.
When an actual operating characteristic and the
reference curve are displayed simultaneously, the
operator can tell at a glance whether the radar is
functioning properly. Many curves or general purpose curve segments can be programmed into a
ROM and picked out as needed with selector
switches or a ROM microprogrammer.
APPENDIX
ROMs can be programmed as lookup tables,
random-logic synthesizers, 4 encoders, decoders;
and microprogrammers as well as character generators. A single ROM can perform limited combina·
tions of these functions, virtually qualifyin\l it. as a
'microcomputer. It has been suggested that this
capabil ity be used in control panels to perform
functions like actuating an alarm when a transducer level \loes out of range and initiating 'corrective action. ROM addresses can be derived from
digital meter circuitry. In multi-point measuring
systems, this would provide the sOlid state equivalent of a rack of meter relays.
WHAT ABOUT INSTRUMENTS
AND CONTROLS?
While it is safe to predict that 1970 wi" be "the
year of the MaS" in alphanumeric terminals, MOS
applications in numeric readouts are just beginning
to emerge.
A new device with considerable promise in this
field is a high voltage, MOS static shift register, the
MM5081. Developed by National, it has a TTLcompatible serial input, 10 parallel outputs that
can stand, off -55V, 10 latching-type storage
stages, and a serial output.
DEFINITIONS OF DISPLAY TERMS
Font: A set of printing o~ display characters of ,a
particular style, and size. A typical dot-character
font is 5 x 7, referrin\l to the number of dot locations per character.
This novel combination of functions means that
the MM5081 can drive lamps, numeric indicator
tubes, filament tubes in segmented number" and
symbols displays, electroluminescent panels, and
the new gas-cell arrays. In short, it provides MOS
with a good foothold on the numeric side of the
readout family tree in Figure 1.
Dot Character: A character formed by a pattern of
bright dots on a CRT screen or dark spots on hard
copy, rather than by continuous strokes. The dot
l1-11
01
pattern corresponds to ·bit·storage patterns in a
digital. memory.
..
Column: In a dot character matrix for vertical
scanning, a column is a vertical series of dots. On a
page ·display, a column contains several vertically
aligned characters. In this article, a column refers
to a dot column.
f!
Row: .A horizontally aligned group of characters
on a display.
~
ca
~
CJ
S
~
u
ca
Page: A display consisting of several rows of char·
acters, corresponding to lines on a printed page.
Q.
Q,
Raster Scan: See Figure 9.
co
c.
.!!!
c
Q)
>
The lJSe of high-speed logic for control is facilitated by making the MM5081 with low-threshold •
p-channel, enhancement-mode MOS transistors. As
a rule, a low threshold device allows data to be
entered at bipolar logic levels.
brings the serial output back to the serial input
through the top gate when the. "new data enable"
line is low (DTLlTTL logical "0") or permits the
registers to be reloaded with new data when the
enable line is high. A pull-down resistor is placed
on the register output to handle 1.6 mA the current sinking required for operation of the TTL or
DTL recirculation control gate.
o
~
...
UI
Q)
ti
0')
Q)
a:
The output transistors do not need a large gatevoltage change to turn on and off. They are also
low-threshold devices in this sense. But they have
to withstand transients up to 100 volts and stand
off steady state voltages up to 55V to operate
lamp-type displays reliably. Adequate gate logic
voltages for the output transistors must be ensured
to make the lamps glow brightly when they should
be on or to make them free of any residual glow
due to .switch leakage when the switching transistors are turned off. That is, a low RON and high
ROFF must be ensured despite very high voltage
on the MOSFET drains. Because a pullup resistor
is used, the input gate should be a TTL or DTL
device with an uncommitted-collector output able
to withstand at least 1OV. Among such devices are
the DM8810, DM8811 or DM7426 (SN7426) quad
NOR.gates, or the DM8812 hex inverter. All these
TTL devices will stand off to 14V.
TICKER-TAPE DISPLAY
A straightforward type of moving lamp display is
illustrated in Figures 2 and 3. Simple messages such
as CALLING DR. CASEY ... CALLING DR.
CASEY ... DR. CASEY; PLEASE REPORT TO
SURGERY ... or stock quotes, or a series of
instrument readings would be displayed as 7X5
characters by this system. That is, each character
wou Id be a lighted lamp pattern selected from a
moving matrix seven lamps high by five lamps
with a moving column of lamps turned off between
characters. The off column is a space bit in each
lamp row.
Assume that the display is· long enough for 33
characters_ Each row requires 33X6 lamps and
198 register stages. Each row is a cascade of 20
MM5081's. The input of the first register and the
The .other two gates used in the input switch can
be any TTL or DTL types. The arrangement shown
FIGURE 2. 7XN Bit Shift Register and Display
11-14
l>
2
output of the last register are connected as in
Fi.gure 1, and the registers in between are simply
daisy-chained by connecting each serial output to
the next serial input. All seven rows would use
140 register packages.
switch. The purpose is to limit the current and
voltage across the lamps and the MaS qutput transistors to ensure that they operate reliably and
have long Iives. Also, the method reduces power
consumption and allows lower power, inexpensive
highevoltage power supplies to be used.
The character data for this type of system can be
formatted by a standard character generator. For
instance,· the standard ASCII code can address a
bipolar compatible read-only memory such as
National's MM5241AA, which is programmed to
generate 5X7 dot-type chilracters for CRT display.
However, in the lamp display system,. the display
refresh function is handled without an additional
memory. The column bits are entered in each
register chain, as before, through the input gating
at.a rate determined by the clock rate supplied
the MH0025C .clock driver. The MH0025C is a
two-phase driver. However, since the MM5081
takes a single-phase clock input (converted to a
two-phase clock inside the register package), only
one of the dual drivers in the MH0025C package
is shown (the other half can be used to share the
clock-drive load).
The high-voltage switch seen in Figure 3 and
detailed in Figure 4 switches at a rate of 50Hz and
a duty cycle of 25% .. Thus, when any of the MaS
output. transistors is. on, the lamp that is "on"
during that 250 msec display-rate interval (100%
duty cycle at 2 Hz).is actually on for only 5 msec
at a time_ Then it turns off for .15 msec .. Th is refresh rate was chosen because it provides a good
lamp intensity with no apparent flicker.
::xJ
~
(Q
~
...
~
(/I
s:o
<
~
After the registers are loaded, the clock into the
driver is dropped to a frequency of 2 Hz, if the
regi ster was loaded at a higher frequency. Th is rate
is stabilized by the coupling capacitor Ce . The
coupling capacitor on this type of driver determines the maximum Pulse width, but the minimum pulse width is established by the clock
signal. So, at the lower frequency, the characters
sweep smoothly from right to left across the display lamps. They repeat the message every 100
seconds because 200 register stages are in each of
the seven parallel rows.
o
(/I
"C
Q)
<(/I
FIGURE 4. High Voltage Switch
Both the clock driver and the regiSters operate off
the 10V and ..--6V power supplied.
I
S8H.
The -125V supply turns on the lamps, and the
-45V supply turns them off. But what is actually
being used is the voltage difference, or bias. Most
glow-discharge lamps require a 65V starting voltage
and a 60V holding voltage. The switch keeps the
lamps alternating between these levels while the
MOS transistors are on, but imposes a maximum
voltage of only -65V on the MaS transistors (that
is, 125-60V) for the 5. msec "on" time. The
MM5081 can easily take this - the spec -allows
-100V at 60 Hz (or 16.66 msec) and they are
stress-tested to this level.
,
~:5~'
OH
Off
NEWDAlll
INPUT
INDUSTRIAL DISPLAYS
The characters displayed can be any kind of
symbol within the resolution of the lamp array from letters to cartoon characters - and within the
flexibility of .the controls. Getting patterns to
move back and forth while changing shape is
technically feasible, but would require complex
clocking techniques to put the bits in the desired
location. Static pictorial displays would be fairly
simple to implement, merely requiring loading of
the registers at a high rate followed by storage at
a DC display rate for the desired time; Although
the characters would appear static, the high-voltage
switch would keep the actual duty rate low.
FIGURE 3. System Block Diagram
DISPLAY DRIVE
The high voltage supply (shown in the block diagram in Figure 3) is generated from a high voltage
11-15
III
>
«I
Q.
.~
Q
Q)
o>
:E
...
III
Q)
ti
Cl
Q)
a:
There are many potential new applications for
moving-lamp displays in industrial control systems .
Functions such. as process flow rates through
several feeder pipelines or subassembly line rate
in an assembly plant, cannot easily be set up on a
CRT display. Complex computer graphic techniques or very expensive multi-gun displays may
be needed.
of rates. This is a visual approach to a problem that
generally requ ires complex mathematics and analog computers to solve.
Nor do the rows of lamps have to be aligned.
Individual rows might represent route sections in
a transportation network between junctions. By
driving each section at a display rate simulating
the speed of a particular train, and switching the
"train" of moving lights from row to row via
switches at the junctions (serial output to serial
input register connections), control pe rso n n el
could simulate system operation_ Problems such
as tie-ups - or worse - at junctions could be worked out by varying display rates for the trains whose
schedu les conflicted.
The clock rates and lengths of a number of rows
of lamps can readily be adjusted by hand-operated
controls, such as voltage-controlled oscillators and
gating between registers chosen by selector switches. Any feeder-line display rate that can be represented by the display rate could therefore be varied
at a compressed scale of time and distance until the
display operator arrived at the optimum balance
11-16
)It
~National
_
AppNotes/Briefs
Semiconductor
Z,
en
en
o
,..
~
.
."
CD
.Q
C
CD
::s
(')
<
o
LOW FREQUENCY OPERATION WITH DYNAMIC
SHIFT REGISTERS
..
1
I»
o·
::s
..
~
In many dynamic shift register applications, it is
advantageous to operate the circuit at IQw clock
frequencies or in clock burst modes where high
frequency clock rate periods are follow!!d by long
intervals in which the clocks are absent. To insure
that his system will operate correctly under these
conditions, the designer should be aware of the
limitations of the type of shift register he is using.
When
o
...
.r:.
FIGUR!; lb, Ratio Type Dynamic Shift Register Cell
'i
.....
c
o
CO
CD
Q.
o
>
c.J
c:
CD
;:,
c::r
...CD
LL
~
o
.....I
Ln
Ln
,
OOUT
CLOCK
Z
«
-
OATA OUTPUT
-"'{
1.SV
"'~
'-_ _ _ _ _ _ _ _....J
1.5V
FIGURE 2. Timin!! Diagram For Two Phase Dynamic Shift Registers
The ratio dynamic shift register cell of Figure 1 b
has only one isolated node which limits minimum
frequency operation. It, like the ratioless cell, is
the gate node of the logic transistor. The ratio cell
does not rely on stored precharge to establish a
"'" level on a succeeding logic gate mode. If a
"0" level had been transferred to node A of the
ratio cell by 0 1 during ¢IN time, 0i would be off.
A ¢OUT "'" level would turn on 0 3 and 0 4 creat·
inga charging path between node C and V oo ,
resulting in a "1" level at node C. The node would
be isolated by 0 4 , just as in the ratioless cell,
when ¢OUT returns to a "0" level.
establish a "O"at node B in that case, an electrical
ratio between the on impedance of O2 and 0 3
must be considered .by the cell designer.
Charge must be stored at the logic transistor gate
node of the ratioless cell for the period of time
between leading edges of the two phase clocks.
This is because no charge enters the node B andC
network after the leading edge of the transfer
clock (¢OUT) and there is no way for charge which
leaks off the nodes to be replaced. This portion
of the clock period is defined as a Partial Bit Time.
The Partial Bit Time between the leading edge of
¢IN and the leading edge of ¢OUT is the TIN period,
and. the time between the leading edge of ¢OUT
and the leading edge of ¢IN is TOUT (Figure 2).
If the data coupled by 0 1 had been a "1", both
O2 and 0 3 would be on during ¢OUT time. To
11·18
The period of the minimum operating frequency
is the sum of the two, or
Where
(1 )
d; the time between the trailing
edge of f (MIN) '" 4>IN PW + 4>d + 4>ouT PW + 4>d
assuming clock rise and fall time«
en
(2)
':1'
.......
4>pw.
,.I
Optimum low frequency operation can be obtained
when the clock· pulsewidths and phase delays are
maximized and made equal. In most cases this
would mean 10 IlS clock pulsewidths and 50%
clock phasing. For power or system application
reasons it is usually not convenient to use such
wide pulsewidths, and the minimum clock frequency is simpl ified to
1
4>f (MIN) ==.~
'I'd + 'I'd
assuming 4>pw«
-60
-211
20
..
"
.DII
140
AMBIUT TEMPERATURE nl
FIGURE 3. Maximum Partial Bit Time
Ambient Temperature
V$
(3)
4>d or ¢d'
TIN .-TO\,lT "MrNIMUM
Y
Maximum Partial Bit Times and Clock Phase Delays
for a given Circuit are a measure of the .ability
of the critical nodes within the cell to store a
minimum voltage level. Charge is usually lost due
to leakage currents associated with the semicon·
ductor junctions of the nodes. The total reverse
leakage current for a. p·n junction is the sum of
three components; the bulk diffusion current,
charge generation current and surface leakage cur·
rent. Within the normal operating junction temp·
erature range of MOS shift registers (-55°C to
1SOoCl. the charge generation current is the pri·
mary component of leakage. Charge generation is
usually attributed to recombination centers with·
in the depletion layer of the junction. Leakage
current generated in this manner is usually ap·
proximated by the expression
i>'"
llN-TOUT-f--
-10
-20
18
81
,.
, ...
AMBIENT TEMPERATURE ie)
FIGURE 4. Minimum Clock Frequency YS
Ambient Temperature
If the shift. register utilizes a ratio cell, a curve
identical to Figure 3 could be us.ed to obtain maxi·
mum Clock Phase Delays for any required tempera·
ture. Equation 2 or Equation 3 could then be used
to calculate minimum clock frequency at that
temperilture.
(4)
11·19
l1li
..,.
~
.l:
en
,~
E
to stay away from very high supply voltages. When
both the dock driver reference voltage and VGG
or VOb are the same supply, the best tradeoff is
toward the higher end of the specified range, however. One other consideration Which applies during
operation at any frequency, but particularly at low
frequency, is excursions of the dock line more
positive than Vss. This forward biases internal
junctions which results in parasitic PNP transistors.
If the collector of the parasitic PNP happens to be
a critical node, the circl.lit will fail. Bec~use critical
nodes are often closer to the minimum required
voltage during low frequency operation, registers
are usually more sensitive to positive dock spikes.
The shift register user can often increase his margin of safety when operating at low frequency, or
for long periods of time with the clocks stopped,
by designing the system with that operation in
mind. The ambient operating temperature of the
registers should always be minimized_ The cell requires a minimum voltage at the critical node to
operate, and the time to discharge the node to that
value is dependent upon the initial voltage, as well
as capacitance and leakage:
IV
c:
>
C
.l:
..,.
TIN or TOUT for ratioless cells;
'~
¢d or ¢d for ratio cells
Total capacitance at critical node
c:
o
VINITIAL
...CD
Voltage at critical node immediately
after isolation of that node by transfer clock.
o
Minimum voltage required at critical
node for operation.
>
(.)
IL ; Total leakage current at critical node.
';:
IV
Q.
When calculating temperature effects Of a system
operating in the clock burst mode, the designer
must remember that power dissipation in the shift
register is approximately double at 2.5 MHz what
it is at 100kHz. High frequency bursts will heat
the chip, causing high junction temperatures which
reduce the time the clocks can be off.
SUMMARY
c:
CD
::J
tT
...
CD
LL
~
o
-'
In
In
,
Z
«
The initial voltage can be optimized in two ways:
by using the highest clock amplitude possible and
by allowing something greater than minimum clock
pulsewidth to insure that the maximum amount of
charge is coupled to the node (and in the case of
the ratioles$ cell, that the maximum precharge
voltage is obtained before transfer). A high value
of VGG or Voo , the negative supply voltage, increases on-chip power and therefore junction temperature, as well as increasing the minimum required node voltage_ It is a good idea, therefore,
Dynamic shift registers can be operated at very
low dock· rates if manufacturers data sheets are
consulted and the. proper dock phasing is used .
Added margin can be designed into systems by
keeping clock amplitudes high, the dock pulsewidths 10 to 20% wider than specified minimums,
power supplies low and temperatures as low a.s
possible. Beware of circuit board hot spots which
increase the temperature of individual packages,
or extensive interlead coupling or ringing which
could result in positive clock spikes.
11·20
~National
App Notes/Briefs
~·SemicondiJctor
»
2
~
»
3
...
c:r
I»
CD
=
I»
AMERICAN AND EUROPEAN FONTS IN
STANDARD CHARACTER GENERATORS
=
CI.
m
Ten popu lar American andEu ropean 64-character
subsets for displays and printers are now available
from ·Nalional as single-chip, standard cha~acter
generators. These parts, listed in Table 1, are sold
.off-the-shelf without a ROM masking charge.
Input-output configurations and character formats
for the ROMs are shown in Figures 1 and 2; Application Note AN-40 The Sysrems Approach to
Characrer Generators gives examples of line and
column address-contrallogic, and CRT and printer
operating techniques.
The ROMs are static, bipolar-compatible types,
operating without clocks on standard power supplies. Rowand column access times are typically
450 and 700 ns respectively. An M!\II4240/MM5240
2560-bit ROM is used for the 5 x 7 horizontal-scan
fonts and an MM4241/MM5241 3072-b't ROM for
the 7 x 5 vertical-scan fonts. The MM4240 and
MM4241 operate at -55°C to +125°C and the
MM5240 and MM5241 at _25°C to +70°C.
TYPE NUMBER
c
a
:=
g.
11)'
:r
..=
tJ)
I»
CI.
I»
a.
CODE
o::T
FIGURE
64-CHARACTER SUBSET
I»
iii
Horizontal Scan (5 )( 7)
MM4240AA/MM5240AA
ASCII
Upper-case alphanumeric
3
MM424OAEIMM5240AE
ASCII
Lower-case alpha and symbols
4
MM4240ABU/MM5240ABU
Hollerith
Upper-case alphanume':ic
5
MM4240ABZ/MM5240ABZ
EBCDIC-8
Upper-case alphanumeric
6
MM4240ACA/MM5240ACA
EBCDIC
Uppet-case alphanumeric (IBM)
7
MM'I241ABL/MM5241ABL
ASCII
Upper-case
MM4241ABV/MM5241·ABV
ECMA
Upper-case A/N, Scandinavian
MM4241ABW/MM5241ABW
ECMA
UpPer-case AIN, German
MM4241ABX/MM5241ABX
ECMA
Upper-case AIN, general
MM4241ABY /MM5241ABY
ECMA
Upper-case A/N. Spanish
~...
Vertical Scan t7 x 5t
8
alphan~mer.ic
European {.French. British,
9
10
ltalian~
11
12
TABLE 1.. Single-Chip. Standard ,Horizontal~Scan and Vertical-Scan Ch,aracter G~nerators
v.
-j
IN.UTS
ICHARAtTER
ADDRESS}
IIOW
ADDRESS
'NPUTS
".,
r
v"
"
CODE
IN'UTS
"
-...
~
MM1240/
-,
B,
.,
"
J '.t,
l
v.
v,,
o,
'.
(CHARACTER.
ADDRESS)
...
..:::1.
OUTPUTS
•
ro,,", { <,
8,8,8,8.8,
101.
110.
111.
i
ADDRESS
'N'UTS
••
•
t
'
<.
COLUMtl
OUTPUTS
COLUMN
ADDRESS
iii",,!;!
"r I
. t.
OUTPUT$I.
PROGRAMMABLE I
CHII'ENAUE I
CHARACTER FORMAT
~)
J
~
"
"
OUTPuTS
IIOW DII • •
AOOIIESSUM) • •
(KI'ENABLE
"
:;1
AOMtDNFIGURA7'ON
FIGURE 2. Vertical-Scan Character Gene,.,to, ROM
FIGURE 1. Hori.ontal-Sean Character Generator ROM
11·21
_,
'z. •
"
CHARACTER FORMAT
OJ
.
~
I!as
.J:.
(,)
'E
"C
'0
~
.5
:l
!c
"
&
e;:,
w
'0
c
as
c
characteristics of alf the horizontal-sean character
generators)_
.
Note that each ROM has a chip-enable input to
permit multi-ROM operation with common control
logic_ For instance, two horizontal-scan ASCII
character generators may be operated in tandem to
obtain upper anCl lower-case characters. In this
case, chip-enable would be controlled with bit bs
of the normal 7-bit ASCII code, and its complement, bs .
MM4240AElMM5240AE generates unique symbols
describing the ASCII-7 control codes, as well as
lower-case letters (Figure 4)_ The designer may not·
wish to display or dot-print the symbols_ Since the
symbols are generated only wilen the most significant address bit is logic "0", this bit line may be
used to disable the cllip, and blank the screen when
control signals are transmitted_ If not, tile system
designer can use the symbols as he likes_
HORIZONTAL SCAN FONTS
The subsets of 64 5 x 7 characters in the horizontal-scan fonts are the ones most cOmmonly
used in low-cost TV and CRT raster-scan displays
and dot-matrix line prin~ers.
...:. ......
: ...
.
I ! .! .•.::
...: I:.:! II
,
•• • M ••:.. ••••1••••! ..:..
:. .: :.:.:
M
MM4240AAlMM5240AA contains the ASCII-6 preferred graphic subset, formed from ASCII-7 by
ignoring bit be. The remaining six bits form two
octal address characters_ One is formed by the
three more significant bits, b7 , bs and b4 , and the
second by ba, b2 andb 1 ·
..... ..... ..... . ...
••··1 i··....... :..: :..: .... :.: :.:.:
~
00000II
··1
10
001000
c
rn,
z
c
••
•
20
aIDa
12
001
rno
13
001011
14
001100
I.:• • •
,
...
• •••
Zl
22
010010
010011
24
IITOIDO
H
31
U
011010
011081
011010
.
41
1110001
, ""
•• ••
I. ••I
",000 "
50
101001
•••
n
01101.'
J4
lrI
36
31
11111111
011110
011111
TDOOl1
.+.
52
1011110
101111
..
IDOnll
54
55
101180
101'01
56
101110
111_
"
110001
UOOIO
"
nOoll
110100
"
U010t
nOflO
"
•••
•
"
II
"
111_
"
11118'1
"
111'1'8
"
111011.
"
111110
111111
11
001111
n
n
N
25
H
n
0101/11
DID HID
010101
DIU 110
010111
30
31
J2
]j'
011000
011001
0110111
011011
J4
011100
35
36
31
011101
011110
1111111
-••41 1. : ....
: ••••••••
: ....:
U
U
M
100001
100010
100011
'.'
I· ••
51
181001
1111010
"
53
1111011
1"00100
....
101100
••••
~
~
100101
100110
:
n
I:
101 HII
~
100111
: •••••
56
101 tID
51
101111
:... :...::::::
':.: :.:.:
6!io
110
110iHlO
61
1101101
62
1101110
6J
110011
64
110100
1111101
"
1111101
"
111010
"
til 011
"
74
111100
1f1101
111000
"
66
110110
61
110111
"
111111
111110
"
FIGURE 4_ MM4240AE/MM5240AE Horizontal-Scan
ASCtt-7 Lowe.r-Case Graphic and Control
Symbol Subset
,...
111110
16
001110
. . .•. ,·• .•. ...' ...
..
......... :::.i..···r
.....
::.. ·•• • •·• • .......
100111
The Hollerith character su bset in Figure 5b is
formed by using six gates to compress the 12line Holleritll code to the 6-bit address for 64
characters, as shown in Figure 5a_
111m
1...... ..... . , ._.......
.
a .:.. ..... •• ...,
a ,
,...1'_1
..... • 1•
••
'...' ...
(I..
II i·.·
~10010
i··· •• ! i.:::·
J i. ~.:•• :: .: ,., H
ii -I··
•••..• ..••
••..·.a·
.. ....•• ..
" " ID.'" l00t.o,
•
.....
•
:·tn·
p:
'i
a
•
"
"
....: ....,.j .r"·
••••••••
...
I
.... ••• I.e.
I .....•·
100010
15
001101
21
... ...
.
I· Ii .!:.··..·····I··
21
Ota1\!
011101-
'4
001100
01(1001
50
101000
··1
I
·1· .:::. ••••
13
001011
H
r·i '..
11
001111
26
010110
12
001910
~
0011"1
... :1:-:·
.
. . ...
.. .: ........
: ... :.: ..
.·11..•··:··•••:
"
.5 ..i .. .I .r.·....:........
:
!
.. ..
•••
25
010101
11
001001
~
000110
~!
I··· :.... 1 ·t· oJ:.... .
..... I ..
.
.......
.
.
16
DOl 1111
···'····i:'··
•• ••
21
010001
I ••: I ••: ••-:'
...
15
001 Hll
I·· .....
1100101
1:·:1............................
I·!·! !·r! !.. i·l·i i·rl 1·"1 I····.:
..!:.:!
!.!.! 5.!.! i•••! i•••! !•••! !.i.! !.i.!
I·i'·i ··1Ir]
HI. ..J'Ir:·.· 1.... 1:,
L..
·t..·'I..·i :...: .......... iii i~· I
11
001001
~
000100
010 DOlI
".000
10
001Il00
~
OUOOll
••• .1. .:. •.• ••• •.• .1. .1.
Co)
E
~
000010
i···!
! ! rl·!
... !e..:·1 I·:e..! Ie:'!
.:. !.1.:-! 1:·:1
••• !.1.
.:.
Also, characters 36 and 37 in ASCII (x3.4 1968)'
are respectively a carat (or circumflex), and an
underscore. These are awkward in a video display,
so they are replaced by the more useful arrows_
(The arroWs are related to characters in an older
teletypewriter set)_ Tllis font, sho~n in Figure 3,
is also described ,on the MM4240/MM5240 data
sheet (wllicll sllould be referred to for operating
ftI
·c.,
000001
As shown in Figure 6, an ASCII-compatible subset
is provided by the EBCDIC-8 cllaracter generator
(MM4240ABZ/MM5240ABZ) by simply ignoring
the two most significant bits, bo and b 1 , in the
EBCDIC-8 code. The ABZ version follows the
ANSI standard, while the ACA version follows the
IBM style_ A cent sign, and IBM's logical OR and
logic NOT signs are given by tile ACA subset
(cllaracters 12, 17, and 37). And a plus or minus
sign is provided, as cllaracter 52. (See Figure 7_)
"
110111
"
111111
FIGURE 3. MM4240AA/MM5240AA Horizontal-Scan
ASCtt-7 Graphic Subset
'American National Standards Institute jANSI)
11-22
..... ... • • c:- .... "'.e.a
.,• ....
.:. :......... . ·
• .......... :·
" '" "
"".00 " "
...
...
...
..
.
..
.
....... .·....
a
·
....
..
..•..
·:·i
:.:
i
.
·..... . .." · ·:.. ,:: .:. u
··..•... ·:• :•·.•• .•........·.•··1··. ·i•••••,. ··: .a..: ·: ....
··.·•.·
" " "
" " "
:..
: ...:: .....
a ••
. . .:•• ... . .......
•
I .1
• •• I":.
'
I·
I
on
"
I
0000111
000010
~.,:'~
12
\J
001001
001010
001011
0101161
010010
010011
MMS2UUU
0110011
A,
"
50
101000
..
31
32
011001
011010
41
100001,
000011
000100
~
H
~
l1li0101
000110
000111
DO
OOOIKIO
·• I•
I·'""
:.. :: '.:.. ( ··1"
"
" " "
.:.: .ii.···i
." " .ra1S··.ii
..
.........
.
ii...:
:.:,: ....: ! •.. i .... I I,i i,i...: 'i
•
••• .
•••• ... .·r·
• .:.. •. ..
•• ...
• ·
•• ·
• · ea·. .-au.
•
··1.llea·
·
•
..
·
..
••.• ·
• .• •••·
• •· "
" " " " " "
:• ••• ••••·
•
..... ...'•• .•...•·•.• .....:••• ...i• ·•i• .•• :• l.eJ
•••••
•. •e •
.. ·• •••" • •••"
•• •
••.. •...
..
• ••
·••••: ·• .....
.
'
•
••
••
.
.....•" ··"•• ••••" • •• •· ··"•=
• ·
••••. .:. ••••: ••••, •.: '1:- •••• ..-::
: '......:• i : '....
:.... .....••• :.J...: ..........
•....
.. . : "
" "
..... .....
:....
...: :...
..·1 I::: .:.:e.
..... Ii
+i••-: :
001010
001000
001011
001100
001101
001110
w
21
n
D
N
2S
~
27
010001
010010
010011
011)100
Dill 101
010110
010111
. I
~"..
'OOIOtla
•••
:.: •
011010,
011011
011100
011101
u
DIBDOO
41
50
tDIOGO
180001
43
100010
100100
100011
•
101001
10.1 010
101011
110110
63
110011
.1.
1111000
110001
•••
Me
10
11
11:
111M
111011
111010
54··
101100
1101110
os
1001111
100'110
.~• •
101101
~
011111
011000
nOl01
110110
40
10000G
111811
1111111
75
111'01
"
111110
~
101011
"
101100
U
110011
110010
111010
1111101
~
M"
110100
4&
IDOUO
41
100111
56
101,110
57
101111
67
110111
$
110110
110101
14
111100
111011
111101
.:•.1
"
"
111110
111111
:s
...
fA
AI
:s
Co
AI
a.
os
·OJ
.000'001
000010
OO~
000100
011
001001
001 DID
001011
:: •• :
I I·:!
000101
21
010001
31
011101
n
010010
I
D
010011
000110
DOG"!
. .. "• ·• ·•
•
••1..
~.
I
" "
: • .::. : I·": :....
001100
001101
001110
00111\
! • !·I
··1 'I ! I····
: : ::.•.::
N
010100
25
~
27
010101
010110
011)111
u·:'· • .:.- •••
101000
~
~
~
~
011'Otl
011100
011101
011110
41
100001
42
110010
lIJ1001
101010
43
i...I:
V
011111
I····
:i
!.·.I :.-.:
1:1
10D~11
44
100 100
101011
45
180101
46
100110
110lIII0
110001
•••.
eM
IZ
nlOl0
~
"
FIGURE 6. MM4240BABZ/MM5240BABZ Horizontalsean EBCDIC-8 Graphic Subset
11
111 D01
72
m01D
110 on
II
13
111011
41
100 111
•
·S4··.~·56
1'1100
••
:.... •••••.
I ••.' I ...: ::
111111
'01101-
• H.
I e_
11011111
101,111
101110
•
•
... :
110101
nOllO
110111
1111111
111111
111111
~:oi
._
74
111100
FIGURE 7. MM4240ACA/MM5240ACAHorizontalScan IBM EBCDIC Graphic Subset
11-23
...
g.
...
en
AI
: ••-. "r-: •• •• •• •
•
10
11t DOD
:s
CD
!
n
011010
:......::. ..
i
: ..1
nlll1
CD
::
~
101111
CO')
..*.::p:... := ••••
I
I
.•" -.1.,.
11
611111
·.••••.......
..-.-1--• ..0: ..."-•• ....• •..'•. •••••..
•
....." ....." •"
• ·
•
"
"
..·• .:• .-.
..
....
:
..
•••••••••• .:
.' ·
·..· .."·:. "••• :•..:. . II···:··
" "
.
..
i
.1-£.
....... Ii
:..;.: ... :: ...:......
" " "
47
1011111
56
!01t10
~
In 0111
:•••: i"·:
1:1
1000110
36
011110
I·
: ••
101010
n
61
110001
:.:.: lea:.
II
01,1110
011101
'44
45
100100100101
••••••••••• ·.1•••• :
3D
D111101
011100
43
100,011
• •••
• ::
:• :• .:.
" " " "
001111
010000
I
I
010111
• 'r·· ....... ·····1···· ...
1:1" i::;" I...:1....1 i:.. r'" I..~"
·:•...·:• •••·: ::...• .•·• ·••• • ·•
••
·1··
010110
Scan H911erith Graphics Subset
•••• r··: ,j!••• I..•• !..~. I···· :••••
:••••••1
i•..d,t···
.: i-i·· :1 •••••••• 1•••• •••• 1
000010
:. '1 I
· ...
011011
42
100010
51
11110111
111 DOD
OOOGOI
11
00"11
FIGURE 5b. MM4240ABU/MM52~OABU Horizontal
FIGURE 5a. MM4240ABU/MM5240ABU.Typical
Address I"puts
008000
16
OOIIH'
.
"
110000
: :
0101Dl
I
';:L..: •••
A.
~
010100
I
• '!.; :.. : ...::
n
00"0'
.i...':: . ) ;.:.'....;.i... ....
.. ... ...... . " .. .
· ....: ::.....:::
,...............
.
··i:::.- I....
: :
...·' I··.:
.!
:..
:..
:
.•
••• : i.:•••••••·.:.. :•••• : •••J
...·: ...·: .'• .......... •.• ..:•
·
··•••••
·
·• " ·: ...·" ..."'·. ..••" '.··· " •..'
40
100000
A,
~
001100
.: I.
..... •••• II
"I ::..• "Ip· •" " "
: i.·· i i·.,·! i-. i r··1 i···:
••••• ::•• i : : : ·:1 II···
••••• : ....... ': I': ::....:
IIIM124IABU!
~
000111
~
••: •• ::.: II
A,
H
IIGOnD
ObOIOI
·
:: I
~.
010000
II···.
008100
,
II
001000
OJ
000011
ID
...
...
III
S1'0
Q)
c
Q)
C!)
... ... .... ... ... ..... ..... ...
.. . .. .. .. . . ..
•••• : : I ••• • ••••• :... I •••• I
••••:
VERTICAL SCAN FONTS
:... i•••! I.•.=! .! .: i... I... ! .:
'
All five of the standard vertical-scan subsets in
Figures 8 through 12 are generated with &bit
codes derived from code recommendations R646
of the International Organization for Standardization. These recommendations cover ASCII- 7, European ECMA'7 and CCITT alphabet number 5.
00
01
···'" .·. .·
OOOOOU
000001
~
ro
~
000010
000011
000100
: .. :
.....: ·E·: .!... :.::
~.
··1~·
:
001001
001010
001011
a~
~
01
000101
000110
000111
:..::. : •..•.
! : i :.. :: :
1]"" :.~ •• :
:.~:
.... .... ...... :.:..: :..: .
I:::: ...:I:::
i·::. ....
: !...•..
·· ...... ....... ••...: .i . !...'. . .:.:.... .I.':.!.
... ::::: :...: ,:::, . I .
·:.:. ........
......
. ... . . ..
. .. .. ... ...
......
··.. ·i····...........
··i·.
... .::...
..... . ...
... "
'"
"
.. ·.: ··...·.... .......
:
...
I. ... · :.:
:
"
.: ••..: ••• :. .-! I:::· ........::
.':.....
..
..
: . ..
! .....
:....
:. ::
.....
.
..
.
-....
.
.
..... .....
.....
...
.
...
.
·........" ."........... . .: .:·.. .'..:.·.......
...
·........
001000
001100
15: :
001101
16::
001110
001111
'
"E
1'0
"0
The ASCII subset for American use, in Figure 8,
is practically identical to the horizontal-scan subset.
Those in Figures 9 through 12 follow preferred
character styles in the countries indicated. The
underscore (character 37) is dropped below the
line so that it may be used as a cursor.
10
....1'0
c
...c
III
o
Q)
0-
...o:::J
W
"0
C
CO
C
CO
...
.2
Q)
Vertical-scan character generators are generally
used in dot-matrix tape printers, ink-dot spray
printers and high-definition sawtooth or pedestalscan CRT displays. They may also be used to
control raster-scan TV tubes or CRTs if the tube
is turned on· its side so that the raster scan is made
vertically to provide a page-like format.
E
«
r-.
LO
Z
«
II••• •••••·:••• 1•••• 1
~
~
~
00
••••
:
n
000011
000100
000101
000110
00illl1
~
_."
31
32
33
~
l~
011000
011001
011010
011011
011100
011101
~3
100000
1011001
100010
100011
44
100100
45
100101
46
100110
100111
53
101G11
54
101100
~5
1011\/1
56
1011111
57
101111
31
011111
~2
101000
101001
101010
61
110001
~
63
~
65
~
110000
110010
110011
110100
110101
110110
70
111000
11
111001
12
111010
111011
"
75
111101
73
111100
61
.. ·
lti
111110
71
ECMA~7
Font for Scandinavian Use
...
i... : .:
·............ 1i•••...:1' I....i......::: :........ IS...••••.: iI....'........-!.....
:•••!
,
... ... .·• • .·.... ·•• •.....
: ·.'.:
···:...·.·:: ...·· ...·· ···..• ..•......
·
•.
• ...:....i
·
·
·
"
"·
"
....
:
...........
:
..
:
:
:
:: .
:
..
.."': ......
:I"':
...
:
-.:
ie::
:.
!
!
:.:
i.:.!
:
.. .. . .... ..... .
·"......."..
. ..... .- : ... ...: .
.
.:.. .... j ...: I .·
... i .....
: : : :.... •••
"
." .....
......
. ..:.
.... .·.
·: ··.. ....::.......
:.:. .:..
..
..:. : ... .,
"
:.. ..: .
... •.. .·1·......::".. :
.....:
~
non OlD
21
010111
FIGURE 9. MM4241ABV/MM5241ABV Vertical Scan
,
01
26
010110
,
... ,... .... ... ... ..... ........
0011001
15
30
,,"
:: ....
:-i i...1
i -:'1...
I .:
..i.....1 I • ..
. .I... ..
•••
I
00
24
OUll00
,~
With standard programming, the bits in the column
outputs are sequenced for a sawtooth scan with
dot columns running in the same direction, as
illustrated in Figure 13a. For a pedestal scan,
Figure 13b, alternate columns can be reversed
by putting an 8-bit shift left/shift right TTL
shift register (DM74198) on the output as illustrated in Figure 14.
oonooa
23
01DOll
~.:..
LL
C
1'0
U
010010
~.
C
fJ)
21
010001
00
01
~
~
~
~
000000
000001
000010
000011
000100
000101
I i -:. .!. i.·· :
i
I •• : :.
00
000110
01
000111
i·.·!::! :-..!
·..i .1-·.. ......
i ! . ! ! ·:i. I...:
.. .....
.
..... ..•.. .......
..
..
.
.
·
..... .... : ... ••·• ••
· " "
" "
..
·:.........
.·
:.. : !! i i !
·!.......:.:.:... :....:...........
..
..
...
.
. · :::
.......: 5 :•••• ::
· ......
·· .........-... ... • .5, •.:.I •
·.........
· .........
. ......... .. .....
· . ..
·.. .....·... .......
. ...
. ...
. ..
.
.
...
.
..
....
..
- ........
.....
. ....... "
'"
...:
1••
..... ··:= :·i·:·· ..:.:
·:
"
.....
.: ..... ..... .:.
.
.......
··..............·.......
! .... ..
:, i·.... ........ ....: ::.L..
. ••••
.....
... .
... ...
.. .. ...
··••••·•• •_.•• · .··• ...··.. " ...·.•• ··•..•
"
"
"
FIGURE 8. MM4241ABL/MM5241ABL Vertical-Scan
ASCII-7 Graphic Subset
FIGURE 10. MM4241ABWfMM5241ABW Vertical-Scan
ECMA-7 Font for German Use
001000
11
0010al
12
001010
11
001011
14
001100
n
~
20
21
22
010060
010001
(l100TO
30
011000
31
011001
32
33
I···!
11
001101
001110
001111
25
n
21
010101
010110
(110111
35
36
011110
0111110
37
011111
100010
4]
100011
44
1011100
45
IUD 101
46
100-110
·...• •...•
60
1100011
61
1101101
52
101010
53
10101t
54
1011011
55
101101
56
101110
62
63
~
~
66
1100111
110011
110100
1I01nl
110110,
51
101111
61
110111
..... ••• .1
111000
111001
71
111010
73
111011
14
111100
111110
15
001101
16
001110
001111
20
010000
21
010001
22
1110010
23
010011
24
010100
25
26
010110
21
010 111
••
I.••::
:
30
1I
32
33
34
35
36
DIlUllO
011001
all OlD
011011
011100
011101
011110
31
011111
,~
~
U
M
~
46
100061
10110111
100011
\-110100
100101
100110
100111
"
52
53
!i4
101000
101001
101010
un all
1011011
55
101101
56
101110
51
101111
&1
110001
~
~
110010
110011
"
1101M
&5
11111111
~
110000
IlOIlO
67
110111
NO
•••eI
111010
111011
l1fl00
111101
111110
10
31
111101
14
001100
:
·
" "
.....
.: ..... ..... .: :.... ........:
i •• •• ..
·i.··i'·
..
..." _...
..... ....: ::.L..
. ••••...:..i·....... ..;•.
101001
13
001011
100000
"
101000
12
001010
"
lUOll1
11
001001
.:.
::.~
40
100000
.~.
10
001000
111000
111111
11-24
11
111001
73
16
111111
l>
..
I.•.
:5 I.....J ......' i...• I....: .i.............
.
I... I .:
:5 i.....J i.......: i...-.1...-. .I..............
I
!~
·i
••••
...... .1 ii...=II...a ·i..··L... i ...a
"
-1-: •• - :.,.::.: ••..i
i :
I···!
I :
.
01
~~
~~
~w
N
~
~
~~
~~
~m
•..1 I·:·. 1.... 1·1 r·:1 1...:
12
001010
"
001000
13
001011
14
001\00
15
001UII
16
01)1110
I!
.......·.1···••••••••••••
17
001111
II
I,
:
t,.•• :' iz·· ••~..
20
••
.-ts..
......I ,.i ••..-:: I·· ]
01011011
010001
010010
1110011
I ••:
:
!
•
21·
:
30
00000
010100
010101
1&
:.1.:
010110
I ••••
I~.
32
:
011001
" "
•• • ••• •
I: ·1···
·:1:: .:••••i::.
011010
011011
011100
0111\11
41
42
100001
100010
so
101 DOl
101000
•: •••••:. : I: •••••
~l
1011011
44
1110100
45
100101
4&
100110
56
101110
52
53
S4
~~
"11010
101011
101100
101101
··'1··
..'
.....
lO
011000
011111
I
:
'
"
111Il10
110001
ti~
010
110011
11010(1
110101
110118
41
.100111
40
100000
111
O~D·
m'Ol1
111100
1111111
111118
M
~
•
W
000100
lIDO 101
000.110
II8IIln
11
001001
12
001011)
13
001011
',4
OU1DO
·IS
001101
16
001110
1J
001111
21
010001
22
OfllDIO
23
IlIDDII
31
OIlDDI
II
0110n
'32
DI1010
010100
010101
34
35
011100
011101
•
41
100001
42
100010
:
H
010110
t
011110
43
100011
45
100101
44.
,00100
21
010111
"
:: •
'.1... • ••••••
46
100110
011111
41
100111
..... :...:
.....
.::: ...•.
....... :··r.
.: I····-.
..•.....
:
........
.
,:...
....:: ........
...
.
.!
!
...
:
........ . ... ... .
....
.. .... .... ........
·I::;.....~::I.
.
.: .:... .........
••
(. .) :·i·:
. .J:.:
51
101111
so
51
101lJOlJ
101001
52
101010
5]
101011
54'
101100
55
101'101
56
101110
57
101111
I·
110111
••
111001
~
000011
:: :
63
110000
~
000010.
: :: : :
••
•
: :
:
.
. :.1-:. ••1••
:
:.
.'. :::" . :.' •
.... .:: ............•.. .._' .:,.. ....••••• ............:
.:-.
: ..•.
.••.••• •••"
...." ":"... :......" ....• . •• ••••" ·• ....
.....
....• • .'.••• ....
...........
•••• '..-•.
... ..." •" .:" .,," " ..."• .•
40
100000
01
ODDQDI
.
:.I .·.i: .1....
•• ··i··
... •.:.: ..........• i ......
• .....
.. ...
... ...... . ..
•••• ..'!.:•••••.••••:••
I •••:
31
i···: :•••.: r··: :.... ..:.. : I! !i I
I··· :.:-: i·::..:::: ~'.: :.'·rs·'•• .:-: I:..I ·!
III
20
010000
010111
71
111111
R
61
~
"
~
&5
~
61
110000
110001
110010
110011
l1Dl00
110101
118110
110111
10
I1f ODD
FIGURE 11. MM4241ABX/MM5241ABX Vertical-Scan
ECMA-7 Font for General European Use
IF,ench. British. Italian)
~
3
10
001'000
I····: I' • I' I··.··· ..... :. I'·. I.:•••
.....
••••
. i i i...: :.... I..•· .:.... i ~..J
OJ.''
- -I·; ••.,. :•• •. : ·i:.:.1:.
: •••••
!. i-·.:: :
•••• : ·.1•••• : :: .: .....
·1···1.. .1....
IIODIlI
2
0,
11
12
73
14
111 DDI
111 Ol~
111011
111100
15
111101
1&
111110
•n
mill
FIGURE 12. MM4241ABY/MM5241ABY Vertical·Scan·
ECMA-7 Font for Spanish Use
...
cr
CD
QI
;::J
:s
c.
m
c...
o
'tI
CD
QI
;::J
"T1
o;::J
io+
III
5'
o....
III
;::J
Q.
III
....
C.
(")
-:r
III
....
QI
n
....
CD
....
Ci)
.~
CD
....
:.1:.I.
QI
....
o
PEDESTAL DISPl"V
SAW TOOTlf DISPLAY
....
__ -, ..... ' r----'
•
J
I
:J
:
.1
J
i i
! l
: : :.1 I
I
•
!,
It,.
L. . . . . .
L._J
III
i
l
I
NEXT
CHARACTER
I
:
:
t
FIGURE 13a. Sawtooth Vertical Scan
FIGURE 13b. Pedestal Vertical Scan
III
11-25
CHARA!;TUI
GENERATOR
...
~aI
IN.UT
CIIARAClER
. .IA
DM14191
tEFT/RIGHT
SHIFTER
.
..
ZAIUS
MODULATION
aI
.&:
(J
"tS
aI
.
X·AXISINCIIEMENT
"tS
r-.....-=~-'~--------~~~~~:~~~~ri::r~~)
C
aI
(I)'
.S
...c
(II
,~,
COUlTER
FIGURE 14. Conversion of Sawtooth Output to Pedestal Scan
o
u..
:;
CD
Q.
2
::s
w
"tS
C
aI
C
aI
U
..::
For example, the extra height may be used in an
otherwise 5 x 7 font to drop the tails of commas,
semicolons and lower·case letters below the bottom
line of the capital letters. Fonts as lCirge as 16 x 12
are entirely practical without additional control
logic, using the chip·enable feature of four
MM5241 s. Large·font organizations are discussed in
AN·40.
CUSTOM FONTS
The two ROMs can also be custom·programmed
to prov ide special characters, or fonts larger than
5 x 7. The MM4240/MM5240 actually stores 64
5 x 8 characters or character segments and the
MM4241/MM5241 stores 64 8 x 6 characters or
segments. They are not limited to 5 x 7 and 7 x 5.
CD
e
c(
.....
~
I
Z
c(
11-26~
,
. .
·Semiconductor
~National
a
App Notes/Briefs
APPLYING MODERN CLOCK
DRIVERS TO MOS MEMORIES
INTRODUCTION
MaS memories present unique system and circuit
challenges to the engineer since they require precise
tim ing of input wave forms.· Since these inputs present
large capacitive loads. to drive circuits, it is often that
timing problems are not discovered until an entire
system is constructed. This paper covers the practical
aspects of using modern clock drivers in MOS memory
systems. Information includes sel;ection of packages and
heat sinks, power dissipation, rise and fall time consid·
erations, power· supply decoupling, system clock line
ringing and crosstalk, input coupling techniques, and
example calculations. Applications covered include
driving various types shift registers and RAM's (Random
Access Memories) using logical co"trol as well .as other
techniques to assure correct non·overlap of timing wave·
forms.
Although the information given is generally applicable
to any type of driver, monolithic integrated circuit
drivers, the OS0025, OS0026 and DS0056 are selected
as examples because of their low cost.
The OS0025 was the first monOlithic clock driver.
It is intended for applications up to one megacycle
where l.ow cost is of prime concern. Table I illustrates
its performance while Appendix I describes its circuit
operation. Its monolithic, rather than hybrid or module
construction, was made possible by a new· high voltagegold doped process utilizing a collector sinker to mini·
mizeVCESAl;.
'rABLE
PARAMETER
The OS0026 is a high speed, low cost, monolithic clock
driver intended for applications above one megacycle.
Table II illustrates its performance characteristics while
its unique circuit design is presented in Appendix II.
The OS0056 is a variation of theOS0026 circuit which
allows. the system designer to modify the output performance of the. circuit. The OS0056 can be connected
(using a second power supply) to increase the positive
output voltage level and reduce the effect of cross
coupling capacitance between the clock lines in the
system. Of course the above are just examples of the
many different types that are commercially available.
Other National Semiconductor MaS interface circuits
are listed in Appendix II I.
The following section will hopefully al.low the design
engineer to select and apply the best circuit to his particular application while avoiding common system pro·
blems.
PRACTICAL ASPECTS OF USING
MOS CLOCK DRIVERS
Package and Heat Sink Selection
Package type should be selected on power handling
capability, standard size, ease of handling,availability
of sockets, ease or type of heat sinking required, reliability and cost. Power handling capability for various
Packages is illustrated in Table III. The following guideIines are recommended:
I. DS0025 Characteristics
CONDITIONS (V+ - V-I ; 17V
tON
VALUE
UNITS
15
ns
ns
tOFF
CIN ; 0.0022j.lF, RIN ; on
30
t,
CL ; O.OOOlj.lF, RO; 50n
25
ns
150
ns
V+ -0.7
V
t,
-V-=OV,I OUT = -1 rnA
Positive Outpu't Voltage Swing
VIN
Negative Output Voltage Swing
'iN:; lOrnA, lOUT = 1rnA
On Supply Current (v+)
I,N:= lOrnA
V- + 1.0
V
17
rnA
TABLE II. DS0026 Characteristic.
PARAMETER
CONDITIONS IV+ - V") ; 17V
VALUE
UNITS
7.5
ns
CIN ; O.OO1jlF. RIN ; all
7.5
ns
RO ; 50n, CL = 1000 pF
25
25
ns
ns
V
tON
tOFF
t,
t,
=av. rOUT =-lrnA
= lOmA,l oUT = 1mA
Positive Output Voltage Swing
VI~ - V~
v+ - 0.7
Negative Ou~put Voltage Swing
liN
V- + 0.5
V
On Supply Current (v+)
liN; lamP.
28
mA
OJ
II)
Q)
';:
o
E
Q)
:E
en
o
:E
The TO·5 ("H") package is rated at 750 mW still air
(derate at 200°C/W above 25°C) soldered to PC board.
This popular cavitY package is recommended for small
systems. Low cost (about 10 cents) clip·on heat sink
increases driving capabilitY by 50%.
where:
v+ Req
Additional information is given in the section of this
data book on Maximum Power Dissipation (page 2).
= Equivalent devit;e resistance in the
"ON" state
The S·pin ("N") molded mini·DIP is rated at 600 mW
still air (derate at 9O°C/W above 25°C) .soldered to PC
board (derate at 1.39W). Constructed with a special cop·
per lead frame, this package is recommended for
medium size commercial systems particularly where
automatic insertion is used. (Please note for prototYpe
work, that this package is only rated at 600 mW when
mounted in a socket and not one watt until it is soldered
down.)
To TO·S ("G") package is rated at 1.5W still air (derate
at 100"C/W above 25°C) and 2.3W with clip'on heat
sink (Wakefield type 215·1.9 or equivalent·derate at
15 mWfC). Selected for its power handling capabilitY
and moderate cost, this hermetic package will drive very
large systems at the lowest cost per bit.
V-,;, Total voltage acros's the driver
(3)
DC
= Duty Cycle
"ON" Time
=-----------------"ON" Time + "OFF" Time
For the DS0025, Req is tYpically 1 kn while Req is
typically 600n for the DS0026. Graphical solutions for
Poc appear in Figure 1. For example if V+ = +5V,
V- = ":"12V, Req = 500 n, and DC = 25%, then Poc =
145 mW. However, if the duty cycle was only 5%,
Poc = 29 mW. Thus to maximize tlie number of regis'
ters that can be driven by a given clock driver as well as
minimizing average system power, the minimum allow·
able clock pulse width should be used for the particular
type .of MaS register.
Power Dissipation Considerations
The amount of registers that can be driven by a given
clock driver is usually limited first by internal power
dissipation. There are four factors:
Z25
l'
1.
2.
3.
4.
.ez
Package and heat sink selection
Average dc power, Poc
Average ac power, PAC
Numbers of drivers per package, n
c
i=
:
'~ --
150
i -' /
I .I /
125
100
~
15
f
From the package heat sink, and maximum ambient
temperature one can determine PMAX , which is the
maximum internal power a device can handle and still
operate reliably. The total average power dissipated in a
driver is the sum of dc power and ac power ·in each
driver times the number of drivers. The total of which
must be less than the package power rating.
175
iii
a
c:
V
.L /I /
20v/]./'1
,,17;,
20V
zoo
0
V.
;~ V
V
zv
50
25
'I
e-"
0
10
v+ivp
i---'1
_IRE02500
-REQ=1k
20
30
40
50
60
10
DUTY CYCLE I%}
FIGURE 1. Poe vs Duty Cycle
(1)
In addition to Poc , the power driving a capacitive load
is given approximately by:
Average dc power has three components: input power,
power in the "OFF" state (MaS logic "0") and power
in the "ON" state (MaS logic "1").
(2)
+
-2
PAC = (V - V ) x f X C L
where:
f
For most types of clock drivers, the first two terms are
negligible (less than 10 mW) and may be ignored.
Thus:
x (DC)
(4)
= Operating frequency
C L = Load capacitance
Graphical solutions for PAC are illustrated in Figure 2.
Thus, any tYpe of clock driver will dissipate internally
290 mW per MHz per thousand pF of load. At 5 MHz,
this would be 1.5W for a 1000 pF load. For long shift
register applications, the driver with the highest package
power rating will drive the largest number of bits.
Combining equations (1), (2), (3) and (4j yields a criterion for the maximum load capacitance which can be
d riven by a given driver:
500
C!=zlnF
I
400
!i
~
300
0;
200
iii
I
1/11/
~
~
r!,
100
./
,/
o Ii~
o
I I
IA
I I J..~sOI'F
"I
1.0
1.5
2.0
i
Power Supply Decoupling
2.5
Although power supp"y decoupling is a vvide spread and
accepted practice, the question often arises as to how .
much and how· often. Our own experience indicates
that each crock driver should haveet least O.lpF de·
coupling to ground at the V+ and V- supply leads.
Capacitors should be located as close as is physically
possible to each driver. Capacitors should be non·induc·
tive ceramic discs. This decoupling is necessary because
currents in the order of 0.5 to 1.5 amperes flow during
logic transitions.
REPETITION FREOUENCY {MHzl
FIGURE 2. PAC vs PRF
_ (DC)]
Req
(5)
As an example, the OS0025CN can dissipate 890 mW at
T A = 70°C when soldered to a printed circuit board.
Req is approximately equal to 1k. For V+ = 5V, V- =
-12V, f = 1 MHz, and.dc = 20%, CL is:
CL
~
CL
Note the definition <:>f rise and fall times in this appli·
cation note follow the convention that rise time is the
transition from logic "0" to logic "1" levels and vice
versa for fall times. Since MOS logic is invert.ed from
normal TTL, "rise time" as used in this note is "voltage
fall" and "fall time" is "voltage rise."
7'
v+ - v- = 17V
0.5.
P~LSE
CL = 1000 ,F
lOUT PEAK
Logic rise and fall times must be known in order to
assure non-overlap of system timing.
......CL = SOD ,F
V".. i-""
IJJ.
-=
I I ~~L=r5nF
~
II
I
/
I
a:
ilV
ilT
Tilere is a high current transient (as high as 1.5A)
during the· output transition from high to l.ow through
the V-lead .. If the external interconnecting wire hom
the driving circuit to the V- lead is electrically long, or
has significant de ·resistance the current transient will
appear· as negative feedback and subtract from the
switching response. i<;> minimize this effect, short inter·
connecting wires are necessary and high frequency
power supply dec6upl ing capacitors are required if V- is
different from the ground of the driving circuit.
Clock Line Overshoot and Cross Talk
1340 pF (each driver)
Overshoot: The output waveform of a clock driver can,
and often does, overshoot. It is particularly evident on·
faster drivers. The overshoot is due to the finite indue·
tanc~ of the clock lines. Since most MaS registers require
that clock signals not exceed V5S, some method must be
found in large. systems to eliminate. overshoot. A straight·
forward approach is shown in Figure 3. In this instance,
A typical application might involve driving an MM5013
triple 64·bit shift register with the OS0025. Using the
conditions above .and the clock line capacitance of the
MM5013 of 60 pF, a single OS0025 can drive 1340 pFi
60 pF, or 00 MM5013's.
In summary, the maximum capacitive load that any
clock d~iver can drive is determined by package type and
rating, heat sink technique, max·imum system ambient
temperature, ac power (which depends on frequency,
voltage across the device, and capacitive load) and dc
power (which is principally determined by duty cycler
Rise and Fall Time Considerations
In ·general rise and fall times are determined by (a) clock
driver design, (b) reflected effects of heavy external
load, and (C) peak transient current available. Details of
these are included in Appendixes I and II. Figures A/·3,
A/·4, AII·2 and AII/·3 illustrate performance under
various operating conditions. Under light loads, per·
formance is determined by internal design of the driver·;
for moderate loads, by load CL being reflected (usually
as CLIP) into the driver, and for large loads by peak
output current where:
ID
FIGURE 3. Use of Damping Resistor to Eliminate
Clock Overshoot
11·29
III
4)
";:
o
E
4)
::E
a small damping resistor is inserted between the output
of the clock driver and the load. The critical value for
Rs is given by:
(/)
r--
I
I
I
(6)
o
::E
....
o
III
4)
>
".:;
Q
~
,g
(.)
I
I
I
In practice, analytical determination of the value for
Rs is rather difficult. However, Rs is readily deter·
mined empirically, and typical values range .in value
between 10 and son.
I
Use of the damping resistor has the added benefit of
essentially unloading the clock driver; hence a greater
number of loads may often be driven by a given driver.
In the limit, however, the maximum value that may be
used for Rs will be determined by the maximum allow·
able rise and fall time needed to assure proper operation
of the MOS register. In short:
tr(MAX) = tfIMAX)
:S 2.2 Rs CL
-12V
FIGURE 5. Clock Line Cross Talk
The negative going transition of r/J, (to MOSlogic "1")
is capacitively coupled via CM to ¢Z. Obviously, the
larger CM is, the larger the spike. Prior to r/J, 's transi·
tion, Q1 is "OFF" since only jJ.A are drawn from the
device.
(7)
One last word of caution with regard to use of a damp.
ing resistor should be mentioned. The power dissipated
in Rs can approach (V+ - V-)2fC L and accordingly
the resistor wattage rating may be in excess of 1W.
There are, obviously, applications, where degradation of
tr and tf by use of damping resistors cannot be tolerated.
Figure 4 shows a practical circuit which will limit over·
shoot to a diode drop. The clamp network should
physically be located in the center of the distributed
load in order to minimize inductance between the
clamp and registers.
if1t-F"ft-
The OS0056 connected as shown in Figure 6 will mini·
mize the effect of cross talk. The external resistors to
the higher power supply pull the base of a Q1 up to a
higher level and forward bias the collector base junction
of Q1. In this bias condition the output impedance of
the OS0056 is very low and will reduce the amplitude
of the spikes.
+5V +8V +8V
5V
- - - - ' 0 '- , , - - - - - ,
l"<
r - --,
20C c
""'ft"'- "
02
1N9'14
Jrf"
-
-12V
FIGURE 6. Use of OS0056 to Minimize
Clock Line Cross Talk
-12V
Input Capacitive Coupling
FIGURE 4. Use!)f High Speed Clamp to Limit
Clock Overshoot
Generally, MOS shift registers are powered from. +5V
and -12V supplies. A level shift from the TTL levels
(+5V) to MOS levels (-12V) is therefore required. The
level shift cou.ld be made utilizing a PNP transistor or
zener diode. The disadvantage to de level shifting is the
increased power dissipation and propagation delay in the
level shifting device. Both the OS0025, DS0026 and
OS0056 utilize input capacitors when level shifting from
Cross Talk: Voltage spikes from r/J, may be transmitted
to rh. (and vice versa) during the transition of q" to MOS
logic "1." The spike is due to mutual capacitance
between clock Iines and is, in general, aggravated by long
clock lines when numerous registers are being driven.
Figure 5 illustrates the problem.
n·30
TTL to negative MOS capacitors. Not only do the
capacitorS perform the leve.1 shift function without
inherent delay and power dissipation, but as will be
shown later, the capacitors also enhance the performance
of these circuits.
When the output.of the TTL driver goes high, currentis
supplied to the base of 01, through CIN , turning it "ON."
As the collector of Q1 goes negative, Q2 tums "OFF."
Oiode CR2 assures .turn-on of Q1 prior to o2's turn-off
minimizing current spiking on the V+ line, as well as
providing a low impedance path around Q2's base emit.ter junction.
CONCLUSION
The negative voltage transition (to MOS logic "1 ") will
be quite linear since the capacitive load will force Q1
into its linear region until the load is discharged and Q1
saturates. Turn-off begins when the input current de·
cays to zero or the output of the TTL driver goes low.
Ql turns "OFF" and Q2 turns "ON" charging the load
to within a V SE of the V+ sUPply.
The practical aSpects of driving MOS memories with. low
cost clock drivers has been discussed in detail .. When the
design guide lines set forth in this paper are followed and
reasonable care is taken in circuit 'ayout, the 050025,
050026 and 050056 provide superior performance for
most MOS input interface applications.
REFERENCES
Rise Time Considerations
1. Bert Mitchell, "New MaS Clock Driver for MaS
Shift Registers," National Semiconductor, AN·1B,
March 1969.
The logic rise timelvoltage fall) of the OS0025 is primarily a function of the ac. load; CL , the available input
current and total voltage swing. As shown in Figure AI-2,
2. John Vennard, "MaS Clock Drivers," National
Semiconductor,MB·9,December 1969.
V.'
3. Oale Mrazek, "MaS Delay Lines," National Semi·
conductor, AN·25, April 1969.
4. Dale Mrazek, "MaS Clock Savers," National Semi·
conductor, MB·5.
5. O'ale Mrazek,
"Silicon Disc's Challenge Magnetic
Disc ,Memories," EON/EEE Magazine, Sept.. 1971.
6. Richard Percival,
"Dynamic MaS Shift Registers
Can Also Simulate Stack and Silo Memories," Elec·
tronics Magazine, November B, 1971.
7. Bapat and Mrazek, "Dynamic MaS Random Access
Memory System Considerations,"National Semiconductor, AN·50, August 1971.
8. Don Femling, "I/sing the MM5704 Keyboard Interface in Keyboard Systems, " National Semiconductor,
AN-52.
FIGURE AI·2.Ri .. Time Model for the 050025
the input current must charge the Millercapacitance of
01, CTC, as well as supplV: sufficient base drive to 01
to discharge CL rapidly. By inspection:
APPENDIX I
OS0025 Circuit Operation
The schematic diagram of the OS0025 is shown in
= 'M
Figure AI-f. With the TTL driver in the logic "0" state
liN
01 is "OFF" andQ2 is "ON" and the output is at
approximately one V BE below the V+ supply.
liN ~ 'M+ 's, for 1M »IRl & Is »IRl
+ Is + IRl
IlV
Ilt
(Al·l)
(AI-2)
If the currentthrough R2 is ignored,
+-.......,...
(AI-31
~o OUTPUT
INPUT
CR,
where:
Rl
IL =
250
L-~-4~--~----~
CL
IlV
Ilt
__OVCombining equations AI-l, AI·2, AI·3 yields:
FIGURE AI-l. OS00265chematic (One·HalfCircuitl
tl-3J
:
I;'
III
14
Q)
AV
- , [C L + CTC (h FEQ1 + ,1)]
At
"~
o
E
Q)
:E
en
(AI·4)
voltage rise and optimistic values at the end. Figure'
AI·5 shows tl as function of CL ·
zoo
or
o
>
"~
.::t.
y,
Equation (AI·5) may be used to predict t, as a function
of C L and AV. Values for eTC and hFE are 10 pF and
25 respectively. For example, if a OM7440 with peak
output current of 50 mA ·were used to drive a 050025
loaded with 1000pF, rise times of:
(1000 pF + 250 pF) (17V)
...c
(50 mAl (20)
u
tZO
:E
Assuming hFE2 is a constant of the total transition:
or 21 ns may be expected for V+; 5.0V, V- ; -12V,
Figure AI·3 gives rise time for various values ,of C L •
AV
At
(~)
">
(AI·6) .
CTCQ1 + CL/hFEQ1~1
Q.
Z4
~
..r
~.
~
;::
Z
~
I
("!
FIGURE AI·5. OS0025 Fall Time vsCL
c
CD
"","""
LOAD CAPACITANCE. CL
CJ)
.'i
~
100 ' - ' - ' - ' - ' - - ' - - , - , - - , - - , - - ,
o 200 400 600 BOD 1000
Q)
o
i.--' f-""
~
;:: t40
...
:::
.S':!
"'C
25°C
!
(AI·5)
2
C
"
160
:E
f?Q)
v+ - v-", 20V
TA
w
20
or
I-
(AI·7)
16
lZ
B
t:::
~
200
>--:
600
~,'I,"
,I'lrORAM
~
V
300
100
-
DUTPU; PULSE WIDTH' INPUT PUlS{ WIDTH
1000 14110
CIN
~
-.,Jf
--¥-
r-
5~(rLl1r
1800
+ZDV
L.
2200
(pF)
FIGURE,AI·7. Output PW Controlled by CIN
OM74"
.J
L.
OS002&CN
.J
FIGURE AI-S. ,DC Coupled OS0025 Driving 1103 RAM
'5V
6U'~
r-I-I,
.sv
O.l/JF
410
6q
r"--,-=TTL!
INPUTS
L.
MH002seN
I-;r
.J
0-12V
J
~O.M
C"p,~
-12V
FIGURE AI-9. DC Coupled Clock Oriver Using OS0034
-
FIGURE AI-l0. TransistorCoupled OS0025 Clock Driver
11-33
w
III
CD
".:
APPENDIX II
Rise Time Considerations
E
DS0026 Circuit Operation
:::E
rn
The schematic of the DS0026 is shown in Figure AII-T.
The device is typically ac coupled on the input and
responds to input current as does the DS0025. Internal current gain allows the device to be driven by standard TTL gates and flip-flops.
Predicting the MOS logic rise time (voltage fall) of the
DS0026 is considerably involved, but a reasonable
approximation may be made by utilizing equation
(AI-5), which reduces to:
o
CD
o
:::E
~
f!
CD
>
"0:
Q
.:JI.
~
CJ
...c
CD
'C
o
c
"S.
a.Q.
«
For CL
With the TTL input in the low state 01, 02, 05,06 and
07 are "OFF" allowing 03 and 04 to come "ON." R6
assures that the output will pull up to within a VBE of
V+ volts. When the TTL input starts toward logic "1,"
current is supplied via C, N to the bases of 01 and 02
turning them "ON." Simultaneously, 03 and 04 are
snapped "OFF." As the input voltage rises (to about
1.2V l. 05 and 06 turn-on. Multiple emitter transistor
05 provides additional base drive to 01 and 02 assuring their complete and rapid turn-~n. Since 03 and
04 were rapidly turned "OFF" minimal power supply
current spiking will occur when 07 comes "ON."
:::E
Cl
(AII-1)
1000 pF, V+ ; 5.0V, V- ; -12V, tr "" 21 ns_
;
Figure AII-2 shows DS0026 rise times vs CL .
25
M
20
~
v' - v-, 20V ~~
!
15
~
~
~V
10
0:
I-'
.-:;.-
Z
I
V· - V-'17V
~
~
R~
"50!\
TA '" 2SOC
v'
200
1
400
600
8110
1000 1200
LOAD CAPACITANCE IpFI
EXTERNAL
C"
T
:eZ
D1
I
«
RD
R'
"!
INPUT
Rl
R.
Vcl1
~
~'
D.
I
R2
FIGURE AII·2. Rise Time vs Load Capacitance
~D~
Fall Time Considerations
D.
The MOS logic fall time of the DS0026 is determined
primarily by the capacitance Miller capacitance of 05
and Oland R5. The fall time may be predicted by:
01
>--I+--
~Q5
01
....
RJ
(AII-2)
~ >----ODU TPUT
I'tQ~
OJ
R.
~
,
~
AS
10k
....
Q•
-r
DD
I
where:
~Q'
010
A7
i
Cs ; Capacitance to ground seen at the base of 03
; 2 pF
hFE2 ;
(h FEQ3 + 1) (h FEQ4 + 1)
v-
"" 500
FIGURE AII-l. DS0025 Schematic lOne-Half Circuit}
For the values given and CL
06 now provides sufficient base drive to 07 to turn it
"ON." The load capacitance is then rapidly discharged
toward V-. Diode 04 affords a low impedance path to
06's collector which provides additional drive to the
load th rough current gain of 07. Diodes D 1 and 02 prevent avalanching 03's and 04's base-emitter junction as
the collectors of Oland 02 go negative. The output of
the OS0026 continues negative stopping about 0.5V
more positive than V-.
;
1000 pF, tf "" 17.5 ns.
Figure A 11-3 gives tf for various values of CL .
25
v·
M
~
-v~"
15Vto20V
20
Z
..........
I
!
!
~
~
~
When the TTL input returns to logic "0," the input
voltage to the OS0026 goes negative by an amount
proportional to the charge on C,N • Transistors 08 and
09 turn-on, pulling stored base charge out of 07 and 02
assuring their rapid turn-off. With 01, 02, 06 and 07
"OFF," Darlington connected 03 and 04 turn-on and
rapidly charge the load to with in a V BE of V+
15
.... 1"""
~
10
Ro = 50n
5
TA '" 25' C
II
a
100
400
600
aoo
1000
lOAD CAPACITANCE (pF)
FIGURE
11-34
AII~3.
Fall Time vs Load Capacitance
»
DS0026 Input Drive Requirements
z,
5.0
The OS0026 was designed to be driven by standard
54/74 elements. The device's input characteristics are
shown in Figure AII-4. There is breakpoint at V ,N ==
0.6V which corresponds to turn-on of 01 and 02. The
input current then rises. with a slope of about 600.11
(R21i R3) until a second breakpoint at.approximately
1.2V is encountered, corresponding to the turn-on of 05
and 06. The slope at this point is about 150.11 (R1 II
R2 II R3 II R4).
.....
0)
4.0
?:
1:"
>
»
""<
S·
3.0
2.0
10.
1.0
3:
o
10
20
~
(\)
40
30
...
16
TA =25°C
14
~
.§
r-
~
12
tOUT (rnA)
v+ '" 20V
v-",uv
ID
1''"l
V
....
1/
~
0"
(')
A
o...
;;r
...
(\)
........
1.0
(")
In actual' practice it's a good idea to use values. of about
twice those predicted by equation (AII-4) in order to
account for manufacturing tolerances in the gate., 050026
and temperature variatiol)s.
V
.,'"
0.5
:::s
FIGURE A11·5. Logical "'" Output Voltage
vs Source Currer,t
1.~
2.0
A plot of optimum value ·for G'N vs desired output pulse
width is shown in Figure AIl-6.
2.5
INPUT VOLTAGE (V)
FIGURE AII-4. Input Current vs Input Voltage
J 2400
The current demanded by the input is in the 5..c 10 rnA
region. A standard 54/74 gate can source currents in
excess of 20 mA into 1.2V. Obviously, the minimum
"1" output voltage of 2.5V under these conditions cannot be maintained. This means that a 54/74 element
must be dedicated to driving 1/2 of a 050026. As far as
the DS0026 is concerned, the current is the determining
tur.n-on mechanism not the voltage output level of the
54/74 gate.
S 800
~ !:~
Input Capacitor Selection
~
~ 2000
5~ 1800
1600
~
b
3:
CD
3
..tOM14S00-
1200
....,
~ 1000
/
r+
o
3:
(J)
.L
..
5' 1400
D~~VO~N2~-
o...
,
(;j'
...d":.l
(/I
t""" TRANSISTO~'--
~ 20~ l - t--- ~ +5V OR~~~~~~~~~~-
'"
A major difference between the OS0025 and D50026 is
that .the 050026 requires that the output pulse width
be logically controlled. In short, the input pulse width ==
output pulse width. Selection of G'N boils down to
choosing a capacitor small enough toassure the capacitor
takes on nearly full charge, but large enough so that the
input current does not drop below a minimum level to
keep the 050026 "ON." As before:
IMAX
t, '= ROG 'N In - IMIN
V+ -V-=20V
TA = 25~C
CL = 1000 pF
~' 2200
(/I
0
100 200 300 400 !iDD 600 700 800
OUTPUT PULSE WIDTH Ins!
FIGUR E AII-S. Suggested I.nput Capacitance
vs Output Pulse Width
DC Goupled Applications
The DS0026 may be applied in direct coupled applications. Figure AII-l shows the device driving address or
pre-charge lines on an MM 11 03 RAM.
(AII-3)
or
t,
ROln
+17V
(AII-4)
100pF
IMAX
IMIN
In this case RO equals the sum of the TTL gate output
impedance plus the input impedance of the .050026
(about 1500). IMIN from Figure AII-5 is about 1 mAo
A standard 54/74 .series gate has a high state output
impedance of about 150.11 in the logic "1" state and an
output (short circuit) current of about 20 mA into 1.2V.
For an output pulse width of 500 ns,
500 x 10- 9
(150.11 + 150n)1n
10DpF
DSO026CN
1
TO A.OORESS
LINES ON
MEMORY
SYSTEM
1/20M7400
111
; 560pF
20mA
FIGURE AII·7. DC Coupled RAM Memory Address or
Precharge Driver (Positive Supply Only)
1 mA
11-35
For applications requiring a dc level shift, the circuit of
Figure AII·8 or A 11·9 are recommended.
-+5.0V
051673
Quad decoded MOS clock driver.
051674
Quad MOS clock driver.
0575361
Dual TTL·to-MOS driver.
0575365
Quad TTL-to-MOS driver.
MOS Oscillator/Clock Drivers
1
rNP~i 2
,2
OS7803/0S7807,
OS7813/0S7817
7 ,)1 OUTPUT
8
Complete two phase clock system
for MOS microprocessors .and cal·
culators.
5 92 OUTPUT
INPUT 9
MOS RAM Memory Address and Precharge Drivers
'--....._ _ _ _ _+--;01~
OS0025
Oual address and precharge driver.
OS0026
Oual high speed address and precharge driver.
-12V
TTL to MOS I nterfac.
FIGURE AII-S. Transistor Coupled MOS Clock·Driver
TTL
INPUTS
{
0--.-......
OH0034
Oual high speed TTL to negative
level converter.
OS7800
Oual TTL to negative level con·
verter.
OM7810/0M7812/ Open collector TTL to positive
OM7819
high level MOS .convertergates.
OM78L12
I
TO SHIFT
REGISTERS
Active pull·up TTL to positive high
level MOS con·verter gates.
OS1640/0S1670
Quad MOS TRI-SHARETM driver.
OS1645/0S1675
Hex TRI-STATE@ MOS driver.
OS1646/DS1676
6-bit TR I-STA TE MOS driver refresh counter.
OS1647/0S1677
Quad TRI·STATE MOS driver I/O
register.
OS1648/0S1678
TRI·STATE
plexer.
OS1649/0S1679
Hex TRI·STATE MOSdriver.
-12 V
FIGURE AII-9. DC Coupled MOS Clock Driver
APPENDIX III
MOS
driver
multi-
OS16149/0S16179 Hex TRI·STATE MOSdriver.
MOS I nterface Circuits
MOS to TTL Converters and Sense Amps
MOS Clock Drivers
MH0007
Direct coupled, single phase, TTL
compatible clock driver.
OS7802, OS7806."
OS 165 Series"
Oual sense amp for MM5262 2k
MOS RAM memory.
Hex sense amp MOS to TTL.
MH0009
Two phase, direct or ac coupled
clock driver.
OS163,OS75107,
OS75207"
Dual sense amp for MM 11 03 1k
MOS RAM memory.
MH0012
10 MHz, single phase direct coupled
clock driver.
Voltage Regulators for MOS Systems
MH0013
Two phase, ac coupled clock driver.
OS0025
Low cost, two phase clock driver.
OS0026
DS1671
Low cost, two phase, high speed
clock driver.
Dual bootstrapped MOS driver.
D51672
Dual TTL bootstrapped MOS driver.
LM109, LM140
Series
Positive regulators.
LM 120 Series
Negative regulators.
LM 125 Series'
Oual +/- regulators.
*To be announced
11-36
~Nat1onal
a
App Notes/Briefs
Semiconductor
»
z
Co
(11
tJ)
m
<
:i'
(C
SAVING ROMs IN HIGH-RESOLUTION DOT-MATRIX DISPLAYS AND PRINTERS
~
o
s::
INTRODUCTION
1/1
Conventionally, the number of bits in.a digital
character generator's read only memory is proportional to the number of dots in the character
matrix. That is, the ROM array ordinarily doubles
and redoubles in size as one scales up the resolution or changes from an upper-case to an uppercase/lower-case font.
One version of this new technique automatically
proportions character widths as in letterpress
printing. This gives each character a more natural
shape andel iminates the irregular spacings usually
seen 'around "I" and other narrow characters, Yet
the control logic is simple and the ROM savings
approach 40% at. typical font sizes.
Fortunately, such progressions may not be required. Reorganizing the ROMs to suit the specific
application often save thousands of bits and
allows the designer to use smaller, faster, more
economical monolithic ROMs. As a simple example,
expanding the array. in 32-character subsets rather
than the more conventional 64-character subsets
will enhance performance and save up to 25% of
ROM capacity in typical UC/LC applications.
Such advantages are available immediately, without
development of special ROMs. The designs can
be implemented with standard MaS or bipolar
ROMs currently in production. In fact,intermediate coding broadens the cost/performance
options by allowing a combination of MaS and
bipolar ROMs to be used.
Savings much greater than 25% are possible when
the matrix size reaches a point where several
monolithic ROMs are needed to stoce the font.
We have found a two-stage, column-generation
approach called "intermediate coding" to be much
more efficient than straightforward dot-matrix
generation. It exploits the fact that column
patterns tend to become highly redundant as the
matrix size increases.
Dot'char.acter styles ranging in complexitY from
5 x 7to 12 x 24 or more dots per character have
been developed to meet the human-engineering
standard of various industries using digital displays
and printers. The more popular sizes are listed in
Table I.
DOTS PER
CHARACTER
:::t:
cO'
:r
,
~
(1)
1/1
o
i:
r+
0'
:J
C
g,,
s::
I»
...)C'
r+
DOT-CHARACTER FONTS
The 5 x 7 fonts, such as Figure 1, lead in applications volume due to their use in low-cost data
THEORETICAL
CHARACTER ROM
DESIGN
EFFECTIVENESS
o
iii'
"C
iii"
<1/1
I»
:J
Co
"...5'
r+
TABLE I. Typical Dot-Matrix Character Fonts
SIZE AND
SCANNING
:r
...
1/1
(1)
PRACTICAL
DESIGNS
5x7
Horizontal
35
64 x 7 x 5 "- 2 - , 12k
LaO
Fig.3
35
64 x 5 x 7
2,560
LbO
Fig.3
63
64 x 9 x 7 "4.032
0.67
Fig.6
7x5
Vertl,cal
=.
7 x9
Horizontal
9x7
63
64 x 7 x 9 '" 4.032
1.00
Figs.5&8
7x12&8x12
Horizontal
96
64x 12x8=6,144and
96x 12x8=8,216
1.00
1.00
Figs', -6 & 7
12)(7&12x8
64, Cha'racter Vertical
96 Character Vertical
96
96
64 x 8 x 12 = 6,144
96x,8 x 12 = 9,216
1.00
1.00
Flg.8C
Fig.88
192
192
64 x 16 x 12 '" 12.288
96x 16x 12= 18,432
1.,50 for F Ig'- 9 A
1.50 Fig. 9
Fig.9A
Fig_ 98
64 Character Vertical
96 Ch(lracter Vertical
192
192
64 x 12 x 16 =; 12.288
96 x 12 x 16 ;: 18,432
1.50 for Fig. 9A
1.50 ,for Fig, 98
Figs. 6, 7, & 9
24 x 12
64 Character Vertical
288
64 x: 12 x 24;: 18,432
2.00'for Fig. 98
Figs. 6, 7, & 9
208
64 x 13 x 16 = 13,312
3.06 for Fig. 10
Fig.10
Vertical
12 x 16
64 Chal"(lcter Horizontal
96 Character Horizontal
16 x 12
64 x: 13x 10t064x13x 16
64 Ch(lracter Variable
Font Width
11-37
ID
f!
!c
.~
a..
~
c
ca
(I)
>
ca
Q.
.!!!
C
)(
...ca
.~
~
~
c
c
o
.2
o
•.j:i
(I)
G)
a:,
.r:.
.21
J:
c
(I)
~
oa:
c:n
.s;c
ca
en
In
co,
z
«
••••: ••••• -io .: I···· -i··: i···· i··.. I-
: :1- I·· : 0:
·.1.·: : .1••• •.... .1••• I.... :,
00
000000
:
01
0001101
.:.
· ...:.
I ••':
I 10 :
02
000 010
11
001001
03
00001'
04
000100
I!.·-!
•
05
000101
U
001011
06
000 '10
....:
01
0011111
i-.-il-.ir.,
::-.:
Ie:: a:: :
••••• : •• : •••• :
12
001010
interface terminals (although some terminal manufacturers are going to larger sizes in response to
complaints that 5 x 7 presentations cause eyestrain)_ In other applications, a standard is often
set by older printing techniques_ To cite a few
examples: business-machine users are accustomed
to typewriting; advertisers want characters. with
"sales appeal" on their billboard displays; scoreboards and traffic-control signs must be read
easily at a distance; and electronic printing systems
may have to simulate several metal type fonts_
H -
.-:::•..: I··.:
14
001100
I:
15
001'01
::.••:
16
001110
17
.... ... .... ... ......
.. .
: :: i i...: .... i : :: : i !
-.
..
:
:
i
I::
i•··· I·.·:,·.
.. .. . ... . ... :••••:.
001000
•·
•• ·
····•..· ··:. ·.....
.·· ···••••_. :···• .......•i ·1·-1···
·• ."
"· "
"
" ·
.n. ..·... · ••. • • ..
·• ·".. ·". ......·• ·• .••..·.......• •
... ·• :: ..... •.•
..:.. ··i··
····· .'·•: .....
:1 :·
..: : ••· ·......" • •-...· ··"·..·. ....I····" : :•·...•" "•
·· · · : • ··
•... · .1.
" "
"
... ..::: ..:: ....•• .:•• .....
• •••:
:...: :.·
·...·• .. ·• '. ..... ···.' ·
...• .: ·....
..· ·:.... ·· ··• .......
.
····...
·"·.. ·: .....· .....·.....··...• ·........ ..........
........
.....
...
...... .....
.......·..
..... .....
.. .....
.. .... .....
....
: :.. ..... .:. .:::. .... i : i·:·
· . . :.....: :.....: :......: :....: : :.:.:
.....
·:.......·..:- :......:.:..:.:......:. ...............
.... .... ... .... ....
:.......: .:.:.:
:.:.: :.:.: :...:..:...:.
. . .:.:.:
. ..:...:........
·.................
...............
........... .....
_....................
.
· ·. ........
m
m_
OllaoO
21
m_
0111)01
22
mm
31
011010
23
24
m_
25
m~
26
27
mm
mm
36
J3
011100
011011
011110
011111
:I
.: :. .:::•••••• 1.1
4D
"
100000
45
100010
The matrix size is frequently enlarged to improve
lower-case character definition in UC/LC appl ications. A 5 x 7 font typically grows to 7 x 9 for UC
and 7 x 12 for LC, as in Figure 2. Likewise, 7 x 9
is expanded to 8 x 12 and 12 x 16 to 12 x 24 for
lower-eases_
1001111
47
100100
100111
,
,,
~
I
"
50
101aoO
101001
53
101010
101101
101011
lBl110
6J
110011
64
65
110100
1111101
110110
110111
,,
,
11
111010
13
111011
74
15
111101
16
111100
111110
17
lIlli'
61
11
111 (}Of
(AI
Upper~Case
OJ
0001110
OJ
000011
04
05
000001
000100
110(1101
(100110
10
001000
11
1101'001
12
0011110
13
001011
14
001100
15
001101
16
001110
11
20
010000
21
010001
22
1110010
23
010011
~
25
010101
~
010100
010110
21
010111
At 5 x 7, .it is most economical, as a rule, to program a "full set" of 128 UC/LC characters in
standard character-generator ROMs. The full set
in Figure 1 is stored in two 64-character MaS
ROMs. This provides a mass-production base and
equalizes access times. If the 32 special symbols
generated with the ASCII control codes are not
usable, they are simply blanked by disenabling
the lower-case ROM when the seventh ASCII bit
is "0_" But if the font is scaled up to simulate
typewriting, for example, this practice becomes
wasteful since 96 characters would suffice_
07
'
32
33
Another compl ication is that many special ized font
sizes, such as 11 x 9, do not fit neatly into standard
ROMs made in building block sizes. In other
words, one cannot store the font in a minimumsized ROM array without paying the extra costs
of custom ROM development or specialized low,
volumn ROMs.
'
~
35
~
31
·
.. ...
I···! .I:::· ·1·.. ..:•••...:
·.. ·:.......: .·!.........: :........ ..
.... .... .-' . ... ... ...
·..I: ...I ·:..' ...-I .I.··
·-.........- .............
:... I. ·
011001
011010 _0"011
011100
011101
011110
011111
41
106001
112
160010
43
10111111
44
100100
45
100101
46
IfI(lI1D
47
100111
51
101001
'52
53
101011
54
101100
5S
101 UI
56
101110
57
101111
'.
100000
50
CHARACTER-GENERATOR ROMs
. ...... ....
....- ........
.. .
·.. .....
·...
I··· •• '! : .:::. :••• ':••-! :.: :.:.:
: . ..... . ·
......
..
···..·...........
...
........ -;.· : .': ·......
.:.:.
·" "
1010011
noaOD
61
110001
110010
10
111000
71
111001
12
111010
~
~
~
~
~
~
67
110100
110101
110110
110111
:
111100
Consequently, character-generator ROMs have been
developed that adapt to a variety of font sizes_
They may not exactly fit the theoretical matrix
array at odd sizes. but that is easily offset by
the economy of parts standardization .
:'
73
111011
111101
76
n
111110
111111
Two such MaS ROMs are outlined in Figure 3
with their addressing for 5 x 7 horizontal sc;anning
and 7 x 5 vertical scanning_ The vertical-scan subsystem in Figure 4 shows the amount of support
logic typically required in a display_
(8) Lower-Case Font
FIGURE 1_
12345$112]45611134567
Matrix Sizes
:··:::::::::::1 I::::::
31
12J.5GI
:.
Font
000000
~
12345
FIGURE 2_ UC/LC Character. at 5 x 7 and 7 x 12
:
OJ
••
ll3.5
,~
I
70
O
!:
• I ••:.
•........ I
I .........
110(110
1234$
......... •••••-i' ••••••: : .: ••
.ii··:.
! i···· .
.i:......
. ··.. :........·:-.. ......-..
....... .
101111
•••••
I I
.:...
..·: .:.......:: ··.....: ..::.
...
.. · ···... .
...... ··
i :
ASCII Full Set Font of 1285 x 7 Characters
11-38
CHARACTER
CODe
rt,
}~" . :
...•
/JUTfJlITS
.....
•....
"
'"2)4'
A3
A.
A,
A,
ROW
ADDRESS
CHARACTER
••w
.~
COLUMN
ADDRESS
S(:AN
'"
rt,
}~"
.
A,
ADDRESS
USE 2 ROMs AND
Al'PlY A7 TO CE
FOR 121 CHARACTERS
R
cone
"
AJ
A•
COLUMN ADORESS
.....: .
00,'00
... .
011110"
~
~ OUTPUTS
Cal
C.,
~
"
(A~
5)( 7 Horizontal-Scan, 64-Characters
(8) 7
X
5 Vertical-Scan, 64-Characters
FIGURE 3. MM5240 and MM5241 Standard Character·Generator ROMs
CHARACi(R
GENE.RAtOR
ZAXIS
MOD.
INPUT
CHARACTER
DATA
OUTPUT REGISTER
PARAllEL
ENABLE
LINE
COUNTER
tiNE
[HVIDfR
COLUMN
COUNTER
DOT/COLUMN
DIVIDER
FIGURE 4. Typical 7 x 5 Ve,tical-Scan Display Generator Subsystem
The MM5240 expands straightforwardly in 64·
character increments to larser fonts, such as the
9 x 7 or 10 x 8 arrays in Figure 5A. An expansion
such as Figure 5B would be used to provide a full
set UC/LC font. These expansions keep the
character rate the same as at 5 x 7, whereas
doubling the size of each monolithic ROM would
nbt.
However, the chief attraction of this conversion-is
in UC/LC applications. Figure 7 shows how to
use three R OMs to generate 96 7 x 9 to 8 x 12
horizontal·scan characters-a 25% savings compared
with a "full set" expansion. The chip·enable inputs
are programmed to sense the sixth and seventh
character·address bits. External decoders aren't
needed.
32·CHARACTER BLOCKS
If each ROM in Figure 7 is r.eplaced with a parallel
assembly of three ROMs (24 outputs l. the result
is a 24 x 12, 96·character vertical·scan generator
with the same character rate as at 8 x 12. In other
words, the 32·character approach maintains the
benefits of parts standardization and performance
up to a very high resolution.
A similar expansion of the MM5241, as in Figure
6A, would provide 7 x 9 to 8 x 12 horizontal·scan
fonts. However, the direct 64·character expansion
places a ROM·enabling operation in the middle of
the character. Such operations are common in
large·fqnt generator designs.
Other ROMs can be used in this fashion. In Figure
8, the MM5227 TRI·STATE® and MM5288 256 x
12 ROMs are shown in expansions that comple·
ment those of the MM5241. These ROMs provide
access times well under a microsecond. For rates
in the nanosecond range, general·purpose bipolar
ROMs with four or eight outputs, such as the
DM8597 256 x 4 and DM8596 512 x 8 can be
worked into similar organizations.
A simple solution to this problem is to "steal"
a character·address input, use it as a row·address
input, and then use a chip·enable input as a
character input (Figure 6B). This provides a 32·
character or 64·character block enabled during the
between·characters spacing interval. A 32·character
block would be the only ROM required in a
system using only numbers and symbols.
11·39
CDLUMII!
OUTPUT
D.....
P~
RE~ISTER
•
C",.-Cu
SPACE
jCOlUMN
II I II. It 1 It 1
'::~~~~i:
ADORESS
o
0
,
••
••
•
•
l
l
•
.:
•
o
oo
. ' ROM
• •: : OUTPUTS
0
0
0
,
•
•
10
SPACE
CE
(AI 9 x 7 or 10x 8 ",rtie.l-5ean, 64-Ch.r.ete...
(Bl 9 x 1 or 10 x 8 Vertical-5ean, 128-Char.ct....
FIGURE 5. Expansion of MM5240 to L.rger Fonts
PIS
In
CHARACTER
CLOCK
PIS
o-.-H--...J
OUTPUTS
'l34567e
o
•
••
•
•
•
o••
•
CE
o
•.010
II It 1
•
•
•
It
I I
ROM
NO. I
. , It It
• • , II'
• "
OQ'
0•0
'}
•
II 1 II
.~~!
101
0
:. ::
:..
o
O .... }
•oo
ROM
NO.2
o
0
0
0
O.••
0
CE
\
(Bl 7 x 9 to 8 x 12 Horizont.l-sean, 64-Ch.raetors
(AI 7 x 9 to 8 x 12 Horizont.l-5ean, 64-Ch.r.eters
FIGURE 6. Conv.ntional and Improved MM5241 Exp.nsions to 8 x 12
11-40
..W
ADDRESS
OUTf'UT
R" - R,.o--~H-{
.. o-.....+t----'
·,o-...HH---.,......-.....
·.. ..
··..· ....... ·.........:
·.....
OUTPuTSIEAI:HROMI
RO.
AOOIIESS
CE PIIOGIIAM fOR ASCII
ROM NO. 1 ~ : O. A1 ~ '11 (CAPlTAL LETTERS)
ROM NO.2 AI ~ I, AJ • 0 (NUMBERS. $YMIOLSI
ROM NO. 3 ~ = 1, A1 = 1 fLOWEfl.CASE LETTERSI
:I;
FIGURE 7. Using 32·Character Expansions for 7 x 12 or 8 x 12, 96-Character Generator
A,
CODE
ADDR • .,
A4
"
"
"
OUTPUT
A,
CHIP SELECT
!PROGRAMMABLE)
{c"
"
~
c,,_'-_,....._..r~12
CE
(AI Ba.ic ROM
A, _ A..
OUTPUT
HH
As-A.;o-. . .
CE
(CI 12 x 16 Horizontal.scan, 64-Characters
(BI 9 x 7 tD 12 x 8 Vartical.scan, 96-Charactars
FIGURE 8. Addressing Ganeral.furpose ROMs as Character CanaratDrs
11-41
ill
...en
...c
II)
.>:
0.
"tJ
C
CIS
!
Q.
.!!!
o
)(
...
.>:
INTERMEDIATE CODING
Designs proportioned to the matrix size are not
the most efficient at the larger font sizes. It pays
to analyze the actual character patterns to deter·
mine whether other organizations can be used.
Theoretically, they could all have been unique,
since there is a possible pattern variation ranging
from 128 to 65,536 (2 7 to 2'6). UC/LC and
horizontal-scan fonts are more variable than uppercase vertical-scan fonts, but they are still f~r fr?,,:,
worst-case.
For example, the full-dot columns in such verticalscan characters as b, B, d, D, H, T, etc., are
usually identical. An upper-case font typically
contains only 60 unique column patterns at 7 x 5,
110 at 9 x 7, 120 at 11 x 9, and 122 at 16 x 12.
This analysis led to the organization in Figure 9A.
Instead of doubling the 64 x 12 x 8 organization to
produce fonts up to 16 x 12, it adds only a 2k
CIS
::?!
~
o
..
PARALLEL
TO SERIAL
CONVERTER
MM~2Jl
256 ~ •
COLUMN
GENERATOR
OUTPUT
DATA
c
o
::::I
~II)
CHARACTER
(A.
INPUT DATA
At
o-.-H-t------'
a::,
. .,
123_561891011,2
..t:.
••••••
:
.21
J:
e.
.!:
en
1
:
•
5
112 COLUMN
ClOCt<
-.: i;
••••••••
1/2 COLUMN
.:::
CLOCK =
Ii
IAl12 x 16 Vertical Scan IUC)
CI
c
.~
C/)
-1
A, - A, 0 - - -....
&I)
co,
Z
<
A.
o---1~+---'
A,o-....t-
co
Q.
,!!!
C
)(
...
~,
...o
';:
co
Proportional spacing is inherent. So is high·speed
since the input ROM is a small bipolar array. The
main ROM can be either MaS or bipolar general·
purpose ROMs. This organization should also
expand efficiently since the repeat probability
tends to rise with matrix width.
to time out in four column intervals, the address
counter advances again, and word 00110010 is
accessed during four intervals.
This last word includes an EOC bit. When EOC
and the time·out state of the master counter
coincide, gate 1 clears the address counter. Now
address 0000 0000 generates the space pattern in
two spacing columns. When the master counter
reaches its second state, gate 2 enables the address
counter's paraliel preset inputs. Finally, the input
ROM sets the counter to the starting address for
I and the process continues through I, M and B.
SPACE CODE
C
COUNT~R OUTPUT
14lS6)
c::
o
';;
: ",":
In printing applications involving more corri"plex
characters, the operational advantages might be of
more interest than ROM savings. For example, two
64 x 6 x 8 or 512 x 8 ROMs might be used as an
UC/LC generator with the ninth address input a
direct shift control.
~:ooo~ 11' ~ " 0 n11 ~, \ U 1 0 1 0.010 1 ,~~
00, I , ,
..
::
1
,
1
.........:.
..... ...::
1 0 0 1 1 Q 0 ~ 0 Q 0 1 1 00 1 1 00 l i n 0 0 0 0 , 1 0 0 0 Q Q 1 , 000
......
..
..::.. ...
~~ ~ ~~~ g~ g~~ ~~g ~~ ~ ~ ~ 6~~ ~~
::
::
:=:=::
ci
~ ~i~ ~ ~:: ~ ~~ ~ ~ ~~;; ~;:
.•::.::5i
::is-:: -:-
66
:: ::•
::::::
::::........ ..::.. ::::
:5 ii
::
::.....:.
.......... ...... ::..
.. .........
.2
o
In
Q)
COlUMNS ,,"
a:,
REPEAT CODE
113
~
1
~
6 7 5 910
~ J , , 0 3 2 10
lUl
EOe CODE 000 a 0 al"
.l:
,2l
I
(Repeat Pattern Character Quality and Coding Example)
:I:
,5
In
~
oa:
~
c::
':;
co
(/)
INPUT
'OATA
"""TEA
1
DMJ488
(2 REnl
It)
Oil
z
+--------_c:>O------*Note A: Repeat code group.
FIGURE 10. Repeat·Pattern Vertical·Scan Generator
11·44
0
H~xl-'
~National
~Semiconductor
App Notes/Briefs
A SIMPLE POWER SAVING TECHNIQUE FOR THE
MM5~62
2k RAM
INTRODUCTION
and the enablill9 of Phase 1 is not delayed. The
chip will receive one extra, Phase 1 pulse to
disable it and will no longer .draw power until
it is again enabled. The power then becomes
worst case when alternately accessing two chips.
Both chips will draw power 'cohtinuously while
all other deselected chips draw 0.1 mA each.
Table I shows expected power supply currents
for various size memories per bit of word width:
column II - average power supply current with
only one chip selected; column III - a~erage
power supply current under worst case conditions
of alternately selecting two chips; and column V worst case average current including refresh (ass.uming a 635 ns cycle time). Thepeak current during
refresh, assuming all chips are refreshed 'at the
same time, is equal to the total number of chips
multiplied by 20 mA maximum per chip. During
an interval of 2.0 ms, the memory will cycle
almost 3,000 times, of which only 32 cycles
must be devoted to refresh; therefore, the average
refresh power will be one percent of the peak
power or' 0.2 mA per chip. Comparable savings
in clock driver power dissipation are also realized.
The MM5262 is a state of the art· RAM designed
to operate efficiently in modern. bus organized
systems. Most bused systems present the' address
information to the data bus only during the early
portion of the machine cycle and then transfer
data during the remainder of the cycle. The
MM5262, unlike many other RAMs, does not need
a memory address register to. hold the address
stable on its inputs during the complete cycle
because the address is clocked into the MM5262
on-chip address register by Phase 1. The address
and chip select signals need only be applied during
Phase 1 and the Phase 1 to Phase 2 gap.
SAVING POWER
Because of the very low power dissipation of
the MM5262 when the clocks are turned off
« 2.0 mW), a method for decoding the clocks
of unselected chips in the memory array
would·r.esult in a sizable decrease in power consumption, A problem arises beca",se to deselect
a chip, a Phase 1 pulse must be applied to cl<,ck
the disable signal into the chip. There would
be little advantage in allowing Phase 1 to free
run and dec~ding only Phase 2 and Phase 3
because approximately 75%, of the power dissipation .is associated with Phase 1. The best
solution is a decoding arrangement where the
disabling of Phase 1 is delayed by one cycle
Using the data from Table I for a common
application, such as an Bk-by-16 memory for a
minicomputer, the power is cut to half that
required without decoding. In a large memory,
such as 64k words, the power is cut by a factor
TABLE I.
MAXIMUM POWER SUPPLY CURRENT (mAIIPER BIT OF WORD WIDTH
NUMBER
OF WORDS
CHIPS
PER BIT
OF WORD
WIDTH
I
II
III
IV
V
NO
CLOCK
DECODING
CLOCK
DeCODING
ONE CHIP
SELECTED
CLOCK
DECODING
TWOCHIPS
-!'I,TERNATELY
SELECTED
ADDITIONAL
AVeRAGE
REFRESH
CURRENT
NS
TOTAL
WORST
CASE
2.048
1.0
20
4,096
2.0
40
20.1
40
0
6003
(4mA
STANDBY
CURRENT)
20
10
40
20
8.192
4.0
80
20.3
40.2
0.4
40.6
28.2
16.384
8.0
160
20.7
40.6
1.2
41.8
44.6
32,768
16
320
21.5
41.4
2.8
44.2
65.536
32
640
23.1
43
6.0
49
143
131.072
64
1.280
26.3
46.2
58.6
274
12.4
77.4
N'" Number of words In 2048 inc....,.antl N ~ 4096
B - Number of bits/words
tcVCLE - Memory cycJe time
100 (AVGIMAX = B
~
V
-2)
12.< 20 + (~
2048
\
x 0.1 +
I
Y
(_N_ . , 2) x ~
x
2 ms
2048
'~
________
~y~
IV
III
11-45
20\
________
~1
ID
of 13. Figure 1 shows a plot of memory current
as a function of memory size with a comparison
of the nearest equivalent 2k RAM.
In operation the clock decoder in Figure 2 will
supply clock pulses during any cycle iii which
the chip is selected (Figure 3 -, cycle 1 and
cycle 6) or when the memory is being refreshed
(Figure 3 - cycle 4) ,and will supply an extra
Phase 1 pulse on the first cycle after deselecting
the chip (Figure 3 - cycle 2). During all remaining Cycles the chip is deselected and no clock
pulses are supplied to the chips.
~P"SE'
'.
.,
2k
4k
8k
16k 32k 64k 128k
MHOII26
MEMORY SIZE (WORDS)
FI G U R E 1.
.
Q)
~
o
a..
.!!
Q.
.5
«
CD
z
«
lIII~mory Size vs 2k RAIIII Power
Supply Current
MHOO26
"
A memory system configured as Sk words by
16·bits per word, for example, Would draw SO
mA times 16-bits (1.2S Amps) if undecoded.
If the same memory is decoded, the ,current
drops to 40.6 mA times 16-bits (650 mAl which
is half the current of the undecoded memory.
In a large system, such as 64k words by 32-bits
per word the savings is even greater. Undecoded
the supply current is 640 mA times 32-bits
(20.5 Amps) while the same memory when the
clocks are decoded draws 49 mA times 32·bits
(1.6 Amps). The power for the decoded memory
then is one-thirteenth of that required for the
undecoded memory .
R H R i s H - - -....._ - '
FIGURE 2, l1lil1li5262 Clock Decoding Logic
There are three practical conSiderations to be
aware of when using this circuit. First is t11at,
although the power supplies need only be large
enough to supply the average current to the
memory and its clock drivers, the capacitance
bypassing the power supplies should be large
enough to supply the peak current during refresh
without excessive power supply droop. The second
consideration is that if Tl goes to the low state
prior to CS or REFRESH going low,the leading
edge of Phase 1 will be delayed according to the
delay in chip select and Tl pulse width may
have to be increased to ensure that the minimum
Phase 1 pulse width is supplied to the chip. The
third is that if REFRESH goes high after Tl goes
low a glitch will be produced on Phase 1. If
REFRESH is connected to the clear input of
LOGIC IMPLEMENTATION
Figure 2 shows the logic required to implement
the power saving technique, Figure 3 is a timing
diagram for the logic, and Figure 4 is' a block
diagram of an Sk word by l6-bit/word module.
CYCLE 1
CYCLE 2
~PtlASE3
"
(f)
co,
MHII826
~PH"'SE2
CYCLE J
CYCLE 4
CYCLE 5
CYCLE 6
T,
T,
T,....,I-""";'-...,
~-r--------~~
REFRESH....,----~----4_-------4---------~
cs'-i--------+_'
CLOCKS DECODED
EXTRA PHASE 1
CLOCK DECODED
RURESH CYCLE
CLOCKS DECODED
CLOCK DECODED
TO ON STATE
PULSE TO DESElECT
TO OFF STATE
CLDCKS TURNED ON
TO OFF STATE
TO ON STATE
CHIP
FIGURE 3. l1lil1li5262 Clock Oecoding Timing Diagram
11-46
It is perhaps of more interest to examine an
actual system to determine the effects of clock
decoding. As an example a complete 8k·by·16·bit
memory has been designed and is shown in
Figure 4. This system is not optimized but will
serve a~ a good comparative example. Table II
shows power consumPtion foroJ)!!rating and
standby modes with clock decoding and Table III
gives power consumption without clock decoding.
A comparison . between these tables shows a
42% decrease in power consumption by employ·
ing clock decoding. Table IV shows various memories mechanized using the basic 8k·by·16 module.
Power consumption is given with and without
clock decoding for cycle times of 635 ns and
1.000 ns. It is clear· from these tables that as
memory size increases clock decoding becomes
essential. Saying this another way, the ratio of
a memory components operating power to standby
power is an important parameter for the designer.
the DM7474 •. as shown by the dotted line in
Figure 2. the glitch will be extended into a full
Phase 1 pulse.
The extra Phase 1 pulse after a refresh cycle
will not cause any problems but it will. change
the value of the refresh current. If refresh is
implemented by doing one refresh cycle every
62.4~. the. refresh power will be doubled over
what· it would be if 32 refresh cycles are done
consecUth,ely every 2.0 ms. This is due to the
fact that with 32 consecutive refresh cycles the
memory receives 33 Phase 1 clocks and with a
refresh cycle every 62.41's the memory receives
64 Phase 1 clocks.
One advantage 6f connecting REFRESH to the
clear input of tha DM7474 is that REFRESH is
no longer required to be applied for the entire
cycle and may return to a one after the positive
edge of T1.
TABLE II. Power Consumption of 8k x 16 Module (With tcYCLE = 635 ns and Clock Decoding)
.
r+
Icc (mAl @ 5.25V
OPERATING
100 (mAI@-16V
STANDBY
TTL
1.180
·'.'80
MHOO26
124
1.2
MM6262
699
Total Curre(1tTotal Powe'r (Watts)
OPERATING
lea (mAl @8.75V
STANDBY
0
OPERATING
STANDBY
0
0
0
111
1.1
0
0
12.8
660
19.2
8.0
6.5
2.003
1.194
761
20.3
8.0
6.5
10.5
6.3
12.2
0.33
0.07
0.057
:::T
CD
Total Operating Power = 10.5 + 12.2 + 0.07 '" 22.8 Watts
Total Standby Power = 6.3 + 0.33 + 0.057 = 6.7 Watts
TABLE III. Power Consumption of 8k x 16 Module (With tcYCLE = 635 ns and No Clock Decoding)
Icc {mAl @ &.25V
100 {mAI@-16V
OPERATING
OPERATING
. lea (mAl @8.75V
OPERATING
TTL
1.180
0
0
MHOO26
241
231
0
MM5262
1.333
1,290
9.6
Total Current
2.7&4
1.521
9.6
Total Power (Watts)
14.4
24.4
0.875
Total Operating Power = 14.4 + 24.4 + 0.875 '" 39.3 Watts
TABLE IV. Power Consumption of Large. Memory'Systems Using Multiple 8k x 16 Modules
MEMORY
SIZE
TOTAL POWER (Wattsl 'cVClE
=635 ns
TOTAL POWER (W.... , 'cVClE ·1.000 os
NUMBER
OF CARDS
CLOCK DECODING
NO CLOCK DECO.IIING
8k)( 16
1
22.8
39.3
16.9
&.32
2
45.6
78.6
33.8
51.6
16k x 16
.2
29.5
78.6
23.5
51.6
103.2
CLOCK DECODING
NO CLOCK DECODING
25.8
16k '" 32
4
59
157.2
47
32k.16
4
42.9
157.2
36.7
103.2
32kx 32
8
85.8
314.4
73.4
206.4
11·47
OJ
s.
;
""s,
•s,
•s,•
~
0,
",
•
III
~
.2"
c:
..t:
(J
III
I-
en
.S:
>
CO
CJ)
"-
III
:..t:i±.t -- -- -
r
L
I
I
I
-r-e
::
«
(0
---(>o----o'2
c:
I
I
C)
'0
Q)
o
g
OF 8
I
I
BOF8
OATA
OUTPUT
FIGURE 2.
~
o
l:
en
CIOI
Z
«
It is possible to combine or colle.ct by mask option
any of the product terms for 'any of the several
outputs to establish the output code combinations
desired, Logically any or all ohhe partial product
terms (AND terms) can be combined (ORed) at
each output.
at the outputs. The system designer must test the
possible choices to be used within the PLA. He
should combine all mutual terms within the same
package. Commonly grouped product term a'dds to
the efficiency of the PLA or PLA array as indicated in the previously mentioned equations.
The equations for the output group have the
following form:
WHY A PLA?
a,
~ P, + P'6 ~ P2~ + P42 +
P92
02~P6+P'6+P17+P42+
PS2
03
~P,
The application of the PLA in a digital solution is
a natural evolution in system design. Several years
ago digital systems were designed with gates and
dual D memory elements. The system atthat time,
was conceived and implemented in its best possible
way. A later development in system design util·ized
ROM's to provide the complex decoding for the
control necessary to satisfy the same system
design objective. Now we are in a new era. The
design of the same system control function can be
achieved by utilizing the desirable charac'teristics
of the PLA (Programmable Logic Array). The
reason for this evolution of design is based upon
one or more of three possibilities. F'irst, the new
design will yield a higher performance solution.
This generally relates to an improvement in system
dynamic performance because fewer levels of logic
are required to provide the same control function.
Second, .the design will. result in a lower parts cost.
This is due to the more efficient use of the memory
array as compared with the normal rectangular
array ROM. The third possible advantage comes
from the reduction in system manufacturing cost
brought about because of the reduction in component assembly cost, the reduction in printed
circuit board cost or possibly connector cost within
the system. Each time a system's physical size can
be reduced by the use ··of more complex elements
such as a PLA (Programmable Logic Array) the
cost of that system decreases also because fewer
cards and connectors are required.
+P 20 +P 36 + ... P96
Each of the partial product terms labeled P,
through PS6 are shown as they appear at each
output. Note that the same product term may be
used in as many output equation groups as required.
It can be seen that P" the first product term,is
used in both outputs one and three and P'6 and
P42 are used in outputs one and two.
A PLA need not have more than one output but it
is generally mpre efficient to build the PLA or
ROM witl1 more than one output. The PLA in this
discussion. has eight output terminals which reflect
the sil.icon efficiencies of today's technology. This
product has the ability to be masked with outputs
in. either a .positive true state or a negative true
state. (Figure 2) These capabilities enhance the
elements value when applied to the system solution
since the inverter at the output terminal is not
required.
To use this memory storage device, the memory
storage equations must be written or tabulated so
they can be stored within the mask programmed
element. A large number of possible choices exist
when the equations or product terms are collected
11-50
An' invalid input is designed to produce an all-high
output state. by virtue of the fact that it is not
a recognizable product term.
THE PLA AS A CODE CONVERTER
Being a device, which from its input terminals produces outputs in accordance with a predefined set
of rules, a PLA can be viewed as.a memory storage
device (Le_, a limited capability ROM)_ Hence, if all
the partial product terms for a particular code
conversion can be limited to the 96 available, then
the PLA could be used in this application.
THE PLA AS A D.ECODE ELEMENT
IN A DIGITAL PROCESSOR
Why. does it naturally folloW that the PLA lends
itself to the control function of a digital processor
or other simularly organized system? Many processor oriented systems have control instruction
codes which are much wider (a large number of
inputs bits) than that which can be easily satisfied
with ROM's.
Recall that a product term consists of a combination of input variables which can represent a
characters code, then the code conversion is
possible for a 96 character set_ Take the. case of
12-line Hollerith to 8-line. ASCII conversion as an
example_ Theoretically, 12-line input represents
the possibility of 4kwords_ Actually, seven of.the
12 Hollerith lines are not binary coded lines, they
are ordinary decimally coded lines_. So that a ROM
structure with 12 input lines are not used, these
3 binary
seven Ii nes must first be encoded
lines usiri9 additionallogic elements prior to being
presented into a common 8-input ROM (Figure 3A)_
In addition, the 12-input ROM would have to
decode all the non-existent input possibilities
into don't care (or error) output states_
+5.OV
to
puNCHED
tARO
DATA
INPUT
"""
OUTPUT
The PLA solves this problem efficiently_All 12
inputs are presented to the PLA_ Since selective
decoding is a feature of the PLA no provision need
be made for pre-encoding of the inputs (Figure 3B)_
FIGURE 3B.
HDlLERITKTOASCU
.ow
• ,III'UT JlAftlI) Ul'ES ARE
,JlVEIITERSARE
I)Mf431TYP(S
0MII12'TVflU
MaDE
CoNTAO,"
v"
OUTJ'UT.
4.JK
ASCII·'
"
",
"
Al
....
PUIICNED
"
11.421
DATA
' ' 'Uf
AS ZG
M'I1SlID8ROM
. .{,:,------=:j
PUWCMES
"'-------------------=t"1 11
E,
NOTES;
1. V.z+IUV "I%,VDD:GIIIIII, VIIG~-II.OV -11%
2. Thl Hllllri.....t d... 0... 1 tIIrolllh IZ)ilcon..r.ed
.bI'~nOfllllll¥ .... ~"JflUfI'IN.i • .,~of.
UK
py!ldotd'""'... Il .... IId ...........
j."
.r:'IIES1T01
~jUK
':"
CH'"
~""IlE
LlIIUI ro 11
FIGURE lA.
11-51
WDD
v"
UK
AJlVDTlfTTl
HIGH
OEVICE
TRUE
UK
ID
~
.
«
~
.~
C')
o
...I
Q)
j5
ltI
E
..
E
ltI
C')
e
0..
.t:
....
.~
c::
These types of applications have nine to eleven
logical control code inputs. The timing code is also
significant since the input instruction code must be
logically "ANOed" with timing to form the output
control signals. This results in a total input control
group of eleven to thirteen bits to effect output
control. Standard ROM's can be used to solve the
the design problem. They have been used in the
past but at the expense of system in component
expense and generally in dynamic performance.
If a complete input to output decode is solved, the
cost of the complete ROM array is quite expensive.
Two levels of logic are required to decode the
proper ROM element group and enable the input
data word to propagate to the output terminals
(Figure 4). The technique is generally quite expen·
sive since the quantity of ROM elements can be
large.
A PLA solution would simply involve generating
the logic equations for the outputs, isolating the
common product terms, and implementing it in a
masked PLA. Figure 6 illustrated how a PLA solution might look for the same 20~bit output word
structure. The advantages of this approach are
obvious.
First, the PLA design yields a higher performance
solution. System dynamic performance will improve
due to the reduction of signal paths interconnections and signal skewing. Secondly, a ROM solution
is inefficient, requiring more silicon than is necessary to do the job and hence higher cost. Lastly,
a reduction is effected in manufacturing costs due
to the reduction in component assembly cost,
P.C. Board cost, and interconnection cost.
.21
(/)
Q)
o
....o
TI;IE PLA AS A SEQUENTIAL CONTROLLER
In actual system use, not all combinations of codes
of instruction data and timing data are used therefore, it is possible at times to lise data compression
techniques to reduce the number of ROM's neces·
sary to store the output data. The technique
normally used is to multiplex the required codes
into the ROM elements as required by timing or a
particular section of the input code group.
Another system application of the PLA is in
sequential controllers. A sequential controller us,
ually requires that a random set of input variables.
occur simultaneously to satisfy the condition of a
particular state. This condition then allows advanc'
ing to the next controller state of ·the sequencer.
An ilil'stration of the use of the PLA in a sequencer
application is that of a traffic controller. Referring
to Figure 7, it is assumed that traffic can flow at
high rates in any of four directions. It is also
assumed that each.direction has a left turn internal
and that there is also provision for manual inputs
to the. system. It is also required to modify the
timing interval depending upon the detected flow
rate in any direction. The PLA is used as the
controller for this adaptive sequence timer.
An example of such a multiplexer data decoder
solution using ROM's is shown in Figure 5. Note
that this solution technique uses two levels of
multiplexers (OM74153's) to route the proper
data to the ROM group. The use of these multiplexers significantly reduces the number of ROM's
required but adds to the delay time to achieve the
proper output levels. This technique also requires
many engineering hours to first achieve a solution
and even more to effect a change.
It would be possible to start the sequence within
any of its possible status .. While in each state, the
other possible states are scanned to determine if
the present state should be shortened or made
longer in the exampl.e case, states B, C and 0 are
checked as to the traffic status while the sequencer
is in state A.
All five multiplexers and a ROM element are used
toprecode the inputs V of A POP-S system control ROM set.
""TPUT
CODE
ROM
INPUT
ADDRESS
MEMORv
1
CE
SELECT
I~
:~
,~
l~
-
r--
DM]G42
~l~,
"'"'
-
r--
'--
'-----
r--
ROM
ROM'S
---rcrFIGURE 4.
11-52
f---
l>
INPUfCONTROL
CODE
-
-
=
= -
r-:::=:::
-
DM141SJ
~
f-INSTRUCTION
r---'-
r=
r-r--
DM74153
f-+::
REGISTER
INPUT
WORD
r;::
OM8S!'
f--o
f--o
:::t
0
~
f-o
-
r+
0
0
r---o
C1I
CII
cC'
--<>
DM14153
DM8591
::s
--<>
--<>
~
~
TL
::+
::I"
."
r--'-
h
DM74153
t::::
1
r--
~-
--<>
OM7415J
OM8591
--<>
---Q
~
---Q
p
1
---Q
--<>
--<>
'---
=&
DATA!
IWPUl
{
-
laD-BIT
WORD}
a
...
IC
Ql
3
3
c:r
--<>
MAJOR!
CONTROL
WORD
(i"
.-----
CYCLE
TIMING
OUTPUT
Ql
'---
DMB5g,
SUBT~~f~~
CO
CD
r--o
~
-~
r-=
2,
r
0
IC
eli'
...l>
QJ
<"
CII
f---<>
f---<>
FIGURE 5.
INSTRUCTION
CODEINl'UT
TIMING
CODE INPUT
o~,
O~'
4
lB· BIT OUTPUT WORD
O~,
o~,
FIGURE 6.
11-53
ID
!II
e>
o.
oe(
,!=l
en
0
......
CD
75
DMB554
lDF4
tU
E
E
tU
PLA
o.
en
IlM8S75
e
a.
....
J:.
'~
C
en
'iii
CD
C
UM14163
....0
~
%
en
00
I
Z
oe(
CLOCK
FIGURE 7.
FIGURES.
"·54
l>
Z,
lem. The input control code is 14'bits wide and
the output control word is 28·bits wide, Figure 9.
This means that we would use four !'LA's to
generate the dec,oder solution if none of the packages required more than 96 partial product terms,
In our example assume that there are four output
codes which have, 90' partial p~oduct solutions
without considering the terms required by the
four other output term inals ,of the !'LA under
question.
Note that the state diagram Figure 8 shows that'
the maximum time interval X is checked to be
greater, than the present value of the A elapsed
time counter. If this is true, the state counter
indexes to the next machine state (state B). The
output data transmitted to the holding memory
(DM8551's in Figure 7) will be changed with every
state step in the system, ,The four packages of
holding memories are used to store the control
information for the traffic indicators. The memories
(DM8551's) are sequentially updated by using the
same scan decoder which is used as a multiplex
decode of remote traffic counters (DM85L54's).
o
:e
g
o
CD
(II
~.
:e::+'
:r
"'tI
a
...I»
\Q
3
3
I»
!2:
CD
S
c:r
l>
...
INPUT
ADDRESS
GROUP
\Q
iil
~
It shou Id be noted that the sequence order need
not be orderly. The sequence of states through a
complete cycle may have repeat intervals or jump
commands in any step within the vastly variable
complete sequence loop. There is no special require·
ment that the sequencer be designed with .order in
mind if some sort of disorder will yield an improve·
ment in performance. The performance advantage
may relate to a'dynamic performance improvement
or it may relate to a cost performance improve·
ment. Generally a cost improvement results when
fewer parts are required in the overall solution.
~
%
::::l
The initial thought about solving this problem,
would suggeg the use of an additional PLA with
inputs and outputs connected together to obtain
the extra product terms. Since the four PLA's
have a total of 32 outputs and only 28 anl required,
the 4 unused additiona'i outputs may be coupled
from a second PLA to the PLA which first contained the 4 high usage partial, product groups of
terms (Figure 9).
The control coding developed allows a state
interval to be shortened because one of the cross
streets has detected on coming traffic. Also, the
state interval can be lengthened if no cross or left
turn traffic is de'tected. As the sequencer steps from
state to state the other state conditions are tested.
In other words, while in state B state conditions for
A, C and Dare tested for the necessary conditions
which might modify the timing of state B. The four
traffic counters which are shown in Figure 7 as
DM8554 elements are multiplexed sequentially into
the !'LA sequencer controller where they are logi·
cally "ANDed" with present state timing. Using this
information the sequencer period is modulated per
the equations defined by the state equations.
DESIGNING WITH
CO
CD
OUTPUT
CONTROL
CODE
!200UTPUT5!
FIGURE 9.
PLA
How should a P LA solution be developed? An
orderly approach to the solution is necessary when
the control word is wide and complex in form. The
following techniques may be of some help in
determining the decode combinations when using
a PLA solution.
Doing this allows half of the partial product terms
to be placed in each of two separate PLA's. PLA's
can be connected with common inputs and common
outputs. It 'should be noted that the output code
for the common terms must be programmed using
a negative true logic for, since this permits "wire·
OR'ing" the outputs. This very significant design
possibility would not be allowed if standard ROM
techniques are used.
1. List all input control codes which are required
for each output.
2. Reduce this list logically to minimize the number
of partial product terms.
This interesting observation shows' that, memory
expansion for this product (PLA) is different than
other memory elements. The normal .Read Only
Memory (ROM) or Random Access Memory (RAM)
elements have chip select inputs which must be
decoded and selected before the package is actio
vated. When these types of memories are expanded,
additional de~oder logic elements are required to
select the proper memory array Figure 4. In case
where there are more than one output terminal,
3. Combine similar terms which may be used on
more than one output terminals.
4. Group outputs which can share the largest per·
centage of the same partial product terms.
There are some additional considerations with the
general solution. Let's assume the following prob·
11-55
OJ
en
~
~
«
,~
it is necessary to activate the entire package group
and therefore an entire memory word must be
used for the address.
CONCLUSION
The two example applications, that of the control
decoder within the digital processor and the traffic
light sequencer, show the economic advantages of
using the PLA because a reduction in circuit
complexity and quantity results. The processor
example application results also in an improve·
ment. in dynamic performance. Additionally both
of these examples have a convenience of design
which allows the system's work function to be
modified without changing the overall system.
Only a change of PLA programming need be
accomplished to change the function of the decoder
or. controller system.
C)
o
-'
II,)
::is
(II
E
E
(II
~
C)
e
Il..
oS
'~
cC)
'in
II,)
C
....o
~
Neither of these conditions are necessary for the
PLA. If the partial product does not exist as a
decoder or programmed condition, the outputs do
not change but if that product term does exist the
outputs respond to the solution. I.n the PLA case
it is possible for anyone or combination of outputs
to be selected from different but mutually connected packages (e: igure 9). This element technique
ofgrQuping common control codes can simplify the
solution. The technique may be used with multiple
outputs to any degree which can prove economically
efficientto the system design.
There are many more design ideas which will
become apparent within your system when the
PLA is applied to the system design. More design
flexibility than that available with the ROM or
random logic design can be achieved with theappli·
cation of PLA elements to the system. The overall
result will be more logic function per system
dollar.
This last technique is a variation of items.3 and 4
in the. design suggestions listed earlier. Utilization
of this technique can result in significant improvements in memory storage efficiencies when compared different PLA solutions.
::t
0')
CO,
z
«
11-56
~NatIOn8l
_
l>
.
App Notes/Briefs
Semiconductor
:2
~
o
o
(")
c(II
g
3
:2J
o
~
"o....
CUSTOM ROM PROGRAMMING
CQ
;;
3
3
INTRODUCTION
entering ROM' codes that it is clear which logic
ievel is used_ National has programs to convert
NEGATIVE logic to POSITivE or POSITIVE to
NEGATIVE so ROMs can be entered in either
logic but the customer must specify which logic
it is.
Custom ROM programs are submitted to National
in three fClrmats: paper tape, punched cards -or
truth table with punched cards being the preferred.
These programs are converted into machir)~ Ian;
guage and outputted on a magnetic tape" This
magnetic tape- is used to make the programmable
gate mask and the test tape. Wafers are held in
inventory at gate mask. The wafers are then completed using the custom gate mask ·and tested at
the wafer level. The wafer is then scri bed .and the
good dice assembled. After assembly the units are
tested using the custom test tape to assure the
correct output pattern for every address.
:i'
CQ
DEFINITIONS
Logic Definitions
NEGATIVE Logic: "0'.' = VH = the more positive
.voltage,·'l" = V L = the more negative voltage_
When MOS was in its infancy the design engineers
called a logic ONE a low voltage because a Pcham,el MOS transistor is turned on with a negative
bias applied. This became known as NEGATIVE
logic and was the opposite of TTL's POSITIVE
logic. As the MOS technology evolved and TTL
compatibility became a reality it became desirous
to use the. same logic. in MOS as in TTL Therefore
the first ROMs to come out were specified in
NEGATIVE logic and the new ROMs are specified
in POSITIVE logic. Extra care must be taken in
POSITIVE Logic: "0" =. VL = the more negative
voltage. "1" = VH = the more positive voltage.
Input Output Definitions
Address: A, is the least significant input address
on ROMs. Lo is the least significant input address
on character generators.
.
Outputs: B, is the least significant output.
INFORMATION NEEDED
So that National can better serve its customers ttle following information must be submitted with each ROM
code.
.
NATIONAL PART NUMBER
National S.... iconductor Corpol1ltion
2900 Semiconductor Dr., Santa Clara, CA 95051
Phone (4081 732-5000
TWX 910-339-9240
ROM LETTER CODE (NA1"ONAL USE ONLY!
NAME
DATE
AOOAESS
CUSTOMER PAINT OR 1.0. NO .
CITY
TELEPHONE
. lSTATE
ZIP
PURCHASE ORDER NO.
INAME OF PERSON NATIONAL' CAN CONTACT (PRINTI IAUTHORllED SI~NATURE
11-57
IDATE
OJ
~ ~--------------------------~----------------------~--------------~
c
E
E
~
.8'
D.
:E
oa:
E
TRUTH TAB'-E FORMS
Use the appropriate form for subm itting truth tables.
Form I
MM3501
MM5201
MM5202
MM4203/MM5203
(II
ADD·
RESS
__ 0
t.)
-_ _ 21
sa
;::,
o
MM5204
MM4210/MM5210
MM4211/MM5211
MM4213/MM5213
OUTPUT CODE NOTE, 1
BS
B7
85
B6
B4
B3
B2
MM4214/MM5214
MM4220/MM5220
MM4221/MM5221
MM4230/MM5230
ADD·
RESS
LSB
Bl SUM
....,
z
B7
OUTPUT COOE
B6 B5 B4 B3
82
LSB
Bl SUM
53
54
55
_56
51
58
59
60
61
6
1
__8
__ 9
c(
B8
50
51
_52
3
4
__ 5
o·
MM4231/MM5231
MM4232/MM5232
MM4233/MM5233
_10
11
62
63
64
65
12
_13
I.
15
16
_17
~66
61
. 68
18
19
20
_21
_22
_23
69
70
71
12
. 73
14
15
16
77
78
79
24
25
26
21
28
29
30
31
80
81
82
83
84
85
86
87
32
_33
34
_35
_36
_31
38
39
40
41
88
_89
90
91
92
93
94
95
96
91
42
_43
_44
45
46
_41
48
49
TB
98
99
TB
-
Note 1: The Appropriate. Logic Level box must be checked or order will not be accepted.
o POSITIVE Logic on Addresses and Ouiputs
o NEGATIVE Logic on Addresses and Outputs
Nate 2: Th,e MM42321MM5232 and MM42331MM5233 have programmable chip selects and the logic level to enabre the
chip must be specified. CS 1 _ CS 2 _ CS 3 _ CS 4_
Note 3: TB is the total "'" bits in a column expre-ssed in Decimal.
Note
4:
SUM is the total '"
U
bits in a row expressed in Decimal.
'~H;8
l>
2
.:..
Form II
o
o
C')
c
~
o
MM5212
MM5215
MM4229/MM5229 (Positive logic only)
3
::J:I
o
OUTPUT CODE NOTE: 1
ADD·
B12 811 810 B9
RESS
B8
B7
B5 B4
B6
B3
LSB
B2 B1
OUTPUT CODE NOTE: 1
ADD-
SUM
RESS
812 611 810 B9
B8
B7
B6
85
~
LSB
B4
B3
B2
B'
SUM
...o
'"0
-- 0
_50
1
__ 2
51
52
eQ
3
4
53
II)
54
-- 5
55
56
_'57
3
3
---
6
7
8
__ 9
58
10
11
60
61
12
62
-
-
5'
eQ
59
13
63
14
64
15
65
66
_
16
17
67.
18
68
--+'.
69
f--=.}9
20
70
71
I
21
72
22
23
73
I
74
24
25
-
...
75
26
76
27
77
I
28
78
79
29
_
30
80
_8,
31
32
33
82
83
34
84
35
85
36
86
37
87
38
88
89
90
39
40
41
_9'
92
42
43
93
44
45
94
_95
46
96
47
97
48
98
49
99
TB
TB
Note 1: The Appropriate Logic Level box must be checked or order will not be accepted.
[l
POSITI VE. Logic Or) Address and Outputs
CI
NEGATIVE Logic on Address and Outputs
Note 2: The MM4229/MM5229 has programmable chip selects. Specify the Logic Level to enable the Chip (Positive Logic)
CSI
CS2
CS3
Note J: TB is the total "1" bits in a column expressed in Decimal.
Note 4: SUM is the total "1" bits in a row expressed in Decimal.
11-59
ill
g)
c
'E
E
e
..~
Form III
MM4240/MM5240
D.
::E
0
CHARACTER
ADDRESS
LINE
ADDRESS
(DECIMAL)
(DECIMAl)
_0
0
0
0
...,.
..••
Z
,"
IE:
.
OUTflUTWORO
• 3 84 85 SUM
CHARACTER
ADDRESS
(DECIMAL)
LINE
ADDRESS
CHARACTER
OUTPUT WORD
(DECIMALI .1 82
B3 14
8s SUM
_4
LINE
ADDRESS
ADDRESS
(DECIMAL)
IDECIMALI
_8
0
OUTPUT WORD
8, 82
.J ....
SUM
~'tJ~"
E
,
1
2
2
o~ 1
3
1
0
1;;
=
0
•
,
•
•
11O,
0
11.
"';"
«
.,
,
7
-'
...
.,.
."
,·
..•
".
0
_9
_5"
1
D.,
1
2
2
3
3
·•
•
0
"0
,
7
_2
0
",
.....
0
1
_6
TB
,
2
D' •
."•
".•
3
, .0
0
"0
7
...•
",
_3
_7
D.1 ,
2
D1D
."
3
•
•
'.D
".
"." ,
0
'7
TB
TB
Note 1: A logic "1" = most" negative voltage. A logic "0" = most positive voltage,
Note 2: Line address (L o • Ll ,"L2 ) are the row or column select lines in a character generator application. In a read only mem~
Dry application, A, shall be considered the MSB and LD the LSB.
Note 3: TB is the total "1" bits in a column expressed in Decimal.
Note 4: SUM is the total "1" bits in a row expressed in Decimal.
,1-1-60
»
z
I
Form IV
MM4241/MM(;241
..Ii
o
o
(')
CHARACTER
LINE
ADDRESS
(DECIMAL)
ADDRESS
DECIMAL
_0
LSB
OUTPUT CODE
Bl B2 B3 B4 85 86
87
B8
SUM
CHARACTER
A,OORESS
IDECIMAL)
_5
0
L1L] Lo
o
LINE
ADDRESS
[S8
OECIMAL
8'
c
OUTPUT CODE
B2
83 B4
85· B6
B7
B8 SUM
0
0 0
1
1
001
2
2
010
3
3
01 1
4
4
5
5
1 1 0
_6
0
000
0
,
1
o
3:
"'1:J
o
...
AI
3
3
:r
CO
001
2
2
010
:::D
CO
100
_1
!:!l
o
3
_...
-
. --, --,--. t-- ._.- j - -
3
3
01 1
4
4
100
5
5
110
_2
_7
0
a
000
1
1
001
2
2
010
3
3
01 1
4
100
4
I
5
5
1 1 0
_3
_8
0
0
000
,
,
001
2
2
010
3
3
01 1
4
4
100
5
'0 ,
_4
5
_9
0
,
0
1
2
2
3
3
4
4
5
5
T8
TB
Note 1: On the character address and output word negative logic' is used:
A' logic "'" most negative voltage
A logic "0" most positive voltage
on the line address positive logic is used:
A logic "0" most' negative voltage
A logic "'" most positive voltage
Nots 2: Line address (Lo • L 1 • L 2 ) are the column select lines in a character generator application. In a read only me":1ory
application A. shall be considered the MSB and L. the LSB:
Note 3: TB is the total "'" bits in a column expressed in Decimal.
Note 4: SUM is the total "1" bits in a row expressed in Decimal.
,Jl-6·1
ID
Q r-------------------------------------------------------------------~
.5
E
E
1!
TAPE ENTRY FORMAT
Tape format for the follOWing ROMs.
Q
e
a..
:i!!
oa:
E
MM4214/MM5214
MM4220/MM5220
MM4221/MM5221
MM4230/MM5230
MM3501
MM4210/MM5210
MM4211/MM5211
MM4213/MM5213
Note 5
Note 6
be, MSB
Note B
bl. LSB
MM4231/MM5231
MM4232/MM5232
MM4233/MM5233
2 $paces-+-"---,
---",--Note3
S
~
u
o
o
OOF)'1",.,rHl
()lOIO 111\
1 Space
1"1"111111
Note 2
:1(H111In'" .\
. . "'1,,
.'~.).)
Ij'lfFlflf)fl'l
1)111111 nn 1I
I
."\1':110
~
O"'''q.)lIf'lfJ
fl
(1\.)I'HllI
is? loQll
T;1 I ~f1
T:'h .'S·l
t,
':\'::'''>
z
c(
I)
T!-5
Note 4
41")
i:;'4 {lin
I no
TMJ
H'G 1 l-;,
T91
I'n
L-__~::::::::::::::r---1S~C~
II-BIT TAPE FORMAT
Note 1; The code is a 7·bit ASCII code on 8 punch tape.
Note 2: The ROM input addre.. is expressed in decimal form and is preceded by the letter A.
Note 3: The total number of "1" bits in the output word.
Note 4: The total number if "1 bits in each output column or bit positi'on.
j,
Note
Note
Note
Note
5:
6;
7;
8;
Specify product type.
Must type POS logic, or NEG logic depending on which is used.
LOGIC ON ADDRESS AND OUTPUTS must be the same (either POS or NEG),
Specify the pattern necessary to enable the ROM on the ROMS that need chip selects.
Tape format for the MM5202. MM4203/MM5203 and MM4204/MM5204.
PROM TAPE PAND N FORMAT
S~r1 Cnill'3l:lter ---,
Stop Character - - ,
,
,
fr
Carriage return line feed
allowed betweeen F and 8.
qat.
Field'
I
MSB (Pin 1 H
t
I
LSB IPm4)
I
B PPPN P PN N FBN N PP N N PPF ... BNPNPNNNN F
Ward 0
Word 255
Word 1
All Address Inputs LOW
All Address Inputs HIGH
-Data Field: Must have only P's or N's typed between Band F. No nulls Or rubouts. Must have exactly eight P and N
characters between 8 and F. Any characters except Band F may be typed between the F stop character and the B start
be rubbed out. Data "for exactly 256 words"must be entered, beginning with, word O. P = "1° or the more positive voltage.
N = "0" Or most negative voltage. When the MM4204/MM5204 is used the word length is 512.
P~O~
TAPE BINARY FORMAT
o
r----~O~--------,-.-BITl
00
0
0
o
00
0
...................
.......... .
~
00
00
00
00
00
0
0
0
0
0
~:~:~;
L...-----r--------...l_BITS
WORON
WORDO.
START
Nota 1; Tape must be all blank except for the 513 words punched.
Nota 2: Tape must start with a START punch.
Note 3: Data is comprised of two wonds the first being the actual Data the second ~ing the complement of the data.
Note 4: A punch is equal to a "1" or most positive voltage and the omission of a punch is a "O~' or the more negative vol,tage.
When programming the MM5202 or MM4203/MM5203 it should be remembered that the opposite logic from what is
programmed will appear on the output of the PROM. In otherwords a P on the tape will program a Logic "0" or VL in
the PROM.
1.1-62
)I-
Z
!.
CARD ENTRY FORMAT
MM3501
Card format for the:
MM4210/MM.5210
MM4211/MM5211
MM4221/MM5221
MM4230/MM5230
IIiIM4231/MM5231
MM4213/MM5213
MM4214/MM5214
MM4220/MM5220
MM42321MM5232
MM4233/MM5233
o
o
n
c
g
3
:2J
o
~
"v
r-' r"
ADO,'"
1011
tODD
a
...
,AliT 1
TOOODOOO
CD
"
ill
3
3
5'
'--
CD
....
~-.
Not. 1 :
Nate 2:
Note 3:
Note 4:
Note 5:
Note 6:
Not. 7:
Note 8:
Note 9:
Punch three input addresses per card with the first address in columns 1-25. the second in columns 26-50 and the third in columns 51!-80.
The ROM input address is expressed' in decimal form an~ is 'preceded by the letter A.
The total number of "1" bits in the output word.
The total number if "1" bits in each output column or bit position.
Specify product type.
Must type P9S logic ,or NE.G logic depending on which i~ used.
LOGIC 'ON ADDRESS, OUTPUTS AND CHIP' ENABLE must ,be the same (either POS or NEG),
Leading zeros must be punched.
Specify the Chip Select LOgic ~evels that will enable .the ROM where necessary.
Card format for the MM5212.
AOOOO
0110000000000,00
A 0 0 0, ~
Ii a
0 0 0 0 0
11.000800000000'0000
TIO'
a
0 0 /) 0
0101,0101010-1
1 1 . 0 0 0 3 " " " " , 1 I 11
0101010.10101
""
20'
..
Note 1:
Note 2=
Note 3:
Ncrta4:
_
6:
_
6:
_7:
Note 8:
Note 9:
Punch three input addresses per card with the first address in (:OIumnl '.-25, the second in columns 26-50 and the third
The ROM input address. is expressed in deeimal form and is 'preceded by the letter A.
The total number of "1" bits ,in the outpiut word.
"the total number if ", .. bitl in each ou.tput column or bit position.
Specify product type.
Must type POS logic.
POSITIVE LOGIC ON ADDRESS ANO OUTPUTS.
.",. more positive output. ,"0" more negative outpu~.
l.eading zeroes must be punched.
.
i~
columns 51~.
III
c:7)
c
"e
E
!
Card format for the- MM5215;
.
f
Q.
:I
a:
o
Abooa 000000.0 II 0 a 0
","0.1,0.000000'0. 1 •
E
S
II)
:::J
(.)
o
o'P,"
T,O,2
•••
z
c
~ 1:
Note 2:
Note 3:
Note 4:
Ncm 5:
Pul)Ch three input addresses per card with the fint in I:o!umns 1-25.
the second in columns 26-50. and the third in Columns 51-80.
The ROM input addreu,i, Hprnsed in decimal form end is preceded
by the Iettw A.
The totel number of '~1" bit. in the output word.
The tot" number if "1" bib in eac:h outPl,lt column or bit position.
~
6:
Note 7:
NoWe:
Nag 9:
Specify produce type.
Must type negative logic.
NEGArlVE LOGIC ON ADDRESS ANO OUTPUTS.
"1" more neptive OUtPUt. ''0'' mora _till, output.
Leading zeroes nv.Ist be P'Jnc:hed.
Card format for the MM4229/MM5229.
12~"5.,
•• 'o-1f 1211 1•. 1'" 17 "'12021
'"
•• 000000000
n
23~
2li2l21 28a .3132.»31 .. :11;0 31 • .0 •• UU44 ."' • •, "' • • 11 WI3I4 ..... I1 . . . . . .I.aa . . . . . . . . JO 11 12 73 H 7&JII" Jill •
........
DOD""
II 00'1
TO.'
.to
It11111111.11
00 I
6 0 . 0 0 . II 0 0 0 0 0
01 0'1 III i 0 I 0 1 •
........
,
.110
-=--,.
Note 1:
Note 2:
Note 5:
Thecade is Hollerith 81 punched on 1,8M Modet 029.
Corrnponds to Pin 16
Corresponds to Pin 15
Cotrespondlto Pin 14
The ROM Input Iddrel$ is expressed in decimal farm Ind is
NoN 6:
All 256 address tQ..255J must be codict.
Note 3:
HOhlt:
uc:h
The totel number of !','s" in
input word.
The ~ .number of ""s'.' in ead'I outpUt column.
LNding zeros mutt be punched.
ThII custo,,* ""~ use his own ID dnigMtion If he does not
punf;t\ the fint column.
'
Ntri. 11: Positive logic on ~ ¥1d ~tp,lU "1" more positive
vol., "0" mare negative voItigl.
NoN 7:
Mole 8:
Note 8:.
Note 10:
pnM:eded 'by the tetter" A.
1Hi4
~National
a
App Notes/Briefs
Semiconductor
z»,
~
,J:Io
,J:Io
o
~
ca'
DESIGNING MEMORY SYSTEMS
USING THE MMS262
:2,
:s
CQ
3:
INTRODUCTION
CD
The objective of this application note. is to describe, in
detail, the operation of the MM4262/MM5262 Dynamic
2K P·channel silicon gate RAM and how to apply this
RAM in designing memory systems. Specifically the
topics to be covered are:
t.
II.
Detail description of operation of MM4262/
MM5262
Memory Systems Application of
MM5262
A.
B.
C.
D.
E..
lit.
information can be read from the memory or written
into the memory. "Dynamic" says the information is
stored in the form of voltages on capacitors. Lastly
"MOS" says the device is manufactured using MetalOxide-Semiconductor technology.
Inputs consist of eleven address inputs (2 11 = 2048), Chip
Select, Read/Write Control, Data. In, three clocks and
three power supplies. All inputs except clocks and power
supplies can be driven by standard TTL circuits. The
power supplies. are nominally VDD= -15V, VSS = +5V
and V BB = +8.5V. The cI.ocks swing from VDD to VSS
nominally. There is one output which sources turrent.
MM4262/
Interface
System Timing
Refresh Requirements
Power Considerations
Printed Circuit Layout Considerations
3
o
-<
CJ)
<
~
3
III
C
III
:s.
CQ
A logic diagram for the MM4262/MM5262 is shown in
Figure 1.. Because dynamiciogic is difficult to represent
in standard logic symbols it is necessary to show actual
transistors in some cases. Further, the internal logic .is
shown in negative logic notation. In this notation a logic
"1" is the most negative voltage level and a logic "'0" is
the most positive voltage leVet. This is opposite to the
normal TTL logic convention.· It may seem, at first, that
this change in logic convention introducesunnectessary
confussion, particularly since all inputs and outputs to
the MM4262/MM5262 are specified using standard TTL
logic convention. However, once the negative logic cpn·
vention is accepted and inputs are translated to this convention it wilt be much easier to understand the internal
operation of the MM4262/MM5262.
A 16K x .10 Memory Application Example
Although the MM4262/MM5262 device is being used as
the primary example, many of the topics discussed are
of general application to the design of memory systems.
I. Detail Description of Operation of MM4262/MM5262
The MM4262/MM5262 is a 2048 x 1 random access
read/write dynamic MOS memory. "2048 x 1" says the
device is organized as 2048 words with each word con·
taining one bit. "Random access" says that words may
be accessed in any sequence. "Read/write" says that
To aid in this translation Table 1. shows inputs and out·
puts in TTL positive logic format and in the negative
logic format used in Figure 1. See page 11.
TTL Positive Logic
Notation (VDD = -15V, VSS = +5V)
Voltage Level
LogiC Level
3.5V to 6V
1
Negative Logic
Notation Used In
Figure 1 (V DD = -15V, VSS = +5V)
Voltage Level
3.5V t06V
Lpgic Level
0
Inputs
-5V to 0.8V
0
-5V .to 0.8V
1
;;. 500iLA @ 1.8V
1
;;. 500!1A @ 1.BV
0
.;; 100!1A @OV
0
.;; 100!1A @OV
1
4V to 6V'
1
4V to 6V
0
-16V to -14V
0
-16V to -14V
1
5V
1
+5V
0
-15V
0
-15V
1
Outputs
Clocks
Internal
Levels
Table 1
11·65
m
and the Y Write line will go to a logic "1"when4>3 is a
logic "1".
Using the negative logic notation described in Table 1 a
logic "1" (-15V) applied to gate of an MOS transistor
will cause that transistor to turn on giving a low
impedance between the drain and source terminals, while
a logic "0" will cause that transistor to turn off giving a
high impedance between the drain and source terminals.
1(1 order for the MM4262/MM5262 to operate properly
the clocks 4>1, 4>2, and 4>3 must be applied in sequence.
Also, as can be seen from the above description of its
operation, the clocks must not overlap one another. For
instance, if 2 were both on simultaneously, the
XN lines could not be discharged properly by the
memory cell transistors, 0A2 and 0A3' If 4>2 and 4>3
were On together, the memory cell would quickly lose
the information stored there.
Detail A, shown in Figure 1, shows the basic memory ce.II
used in the MM4262/MM5262. Information is written
into the cell and read out of the cell via the column line
XN' The Write and Read operation are controlled by the
two row lines, YMW and YMR respectively. Information
is stored in the cell as a voltage level on capacitor CA'
The refresh of a row will then be accomplished when
the clocks 4>1, 4>2 and 4>3 are applied in sequence. The
sequence of events would occur as follows:
At 4>1 time, 4>1 clock at logic "1", all X lines are pre·
charged to a "1" level by the transistors labeled 01.
This "1" level is maintained by the capacitance of the X
lines until it is conditionally discharged by the cells of
the selected row.
The conditional discharge of the X lines takes place
when Y read line, Y MR , goes to a logic "1" turning on
0A2'. If a logic "1" is stored on, capacitor CA, 0A3 is
conducting, allowing the XN line to discharge to VSS
(+5V). If, on the other hand, a logic "0" is stored on
capacitor CA, 0A3 is not conducting and the XN line
will maintain the logic "1" level established during (,11
time. Note that information being read out of the
selected cells on the X lines is of the opposite level as
that stored on capacitor CA'
(1)
All X lines are precharged to a logic "1" at 4>1
time.
(2)
The complement of the data stored on the cell
capacitors of the- selected row, is stored on the
X lines at 4>2 time.
(3)
The information stored on the X lines is written
back into the cells of the selected row at 4>3
time.
There is then only one remaining question to resolye. The
above refresh cycle restores not ,the original voltage
stored 9n capacitor CA, but its complement. Whe~ the
information is eventua'ily read out of the cell, how can
we tell if the cell contains a logic "1" or "0", since the
voltage alternates wi~h each application of the 4>3 clock?
The answer is the Dummy Cell shown in detail B of
Although the information from only one cell will be
output from the RAM, when the YMR line of a particular
row is taken to a logic "1 ", all 64 X lines will assume the
complement of the data stored in the 64 memory cells
of that row. This characteristic is fundamental to the
refresh operation of the MM4262/MM5262 and will be
discussed in the following text.
Figure 1.
There are 32 Dummy Cells; one for each row. The out·
put, DC,. of the Dummy Cell corresponds to the. XN line
of the memory cell. Like XN of a memory cell, DC is
precharged to a "1" level at 4>1 time (through Q5)'
Since the YMR and YMW lines are the same for the
Dummy Cell and its corresponding row, the output, DC,
of the Dummy Cell will alternate between a logic "1"
and a logic "0" each time the 4> 1, 4>2, and 4>3 clocks are
applied. As will be discussed, the output, DC, is used to
complement or not complement the input and output
information. The Dummy Cell is equivalent to a one bit
counter and determines if the row has been comple·
mented an even or an odd number of times. Since DC is
changing in synchronism with all memory cells in its
corresponding row, the voltage out of any cell will be
properly interpreted logically to the outside world.
The WrJte operation is controlled by the Y write line,
YMW ' When YMW of a particular row goes to a logic "1"
level 0A 1 conducts charging the storage capacitance,
CA, to t~e same logic state that existed on the XN line
prior to YMW going to a logic "1". Note that when the
Yrviw line of a particular row goes to a logic "1" the
information on the 64 X lines will be transferred to the
64 cells of the selected row.
Sinee the information is stored as a voltage on a capacitor
this voltage must be restored or "refreshed" periodically
or leakage currents will cause its loss. As described above
information can be read out of a cell on to its cor·
responding X line and also can be read from the X line
back to the storage capacitor, CAo Referring to Figure 1,
the row lines YMR and YMW (M = 1 through 32) are
driven by transistors 03 and 04 respectively. Address
inputs AO through A4 select which row is to be. driven
by tak ing the gates of 03 and 04 to a logic "1". As can
be seen from the logic diagram the Y Read line of the
selected row will go to a logic "1" when 4>2 is 'a logic "1"
The description of the basic memory storage mechanism
is now complete. All [hat remains is a description of the
circuitry requ.ired to 'transfer information into and out
of a particular cell. In order to understand the input/
output circuitry, it is necessary to specify the timing
11·66
l>
requirements of the MM4262/MM5262. Figure 2 shows
these timing requirements.' The necessity of non·over·
lapping clocks has already been discussed. The timing
diagram quantitatively shows this with the timing
intervals T 12, T 23 and 131' In general, it requires a
certain amount of time for information to propagate
through the internal logic elements. This propagation
time limits the minimum allowable clock pulse widths
(T 1PW, T 2 PW and T3PW) and the minimum allowable
time between clocks (TI2, T23 and T31)' Input signals
in general must be in a stable logic state prior to a clock
edge, input set up time, aot;! after a Clock edge, input
hold time. These signals are subscripted "S" (set up) and
"H" (hold) respectively on tile timing diagram. Set up
and hold times are also determined by internal propagation delays.
Any of the basic functional bloqks is simple taken by
itself. When considered in total, they only seem complex. Let us exam ine each, for the MM4262tiv1M5262,
in turn:
(1)
(2)
Up to this point, the description of the MM4262/
MM5262 has proceeded from the inside out, so to speak.
Cllanging our perspective at this time will make the
description of the input/output circuitry more easily
understood. To do this, let us consider the basic func·
tional blocks ot, th is, and aimost any other RAM for that
matter.
cS'
:;,
:r
CO
Input Data Buffer
3en
The Input Data Buffer converts TTL input voltage
levels to MOS voltage levels and gates the input
data to the Write Circuit. The gating of input data
is controlled by the CS, RIW and
00---<
The three clocks are obviously fundamental to the operation of the MM4262/MM5262. It is helpful to think of
them in terms of the functions they control. These
functions are:
~
¢1 - Latches input addresses and precharges internal
nodes.
Vee
.
.,
Dz
FIGURE 3. Typical TTL Gate
Under what conditions will the "1" level output of a
TTL gate equal 2.4 volts? Several conditions have to
exist simultaneously. For a military grade part (_55°C
to +125°C) the "1" level output will equal 2.4 volts,
whenVCC = 4.5 volts, Vin(O) = 0.8 volts, lout = 400,uA
and the ambient temperature is _55°C. Remember the
25°C value under the conditions of "in(O) = 0.4 volts,
lout = 0 is VCC - 1.4 volts. The temperature coefficient
of a forward biased diode is approximately -2 mvfC.
Going to ,_55°C will then degrade the "l'/'level by
(25°C - (_55°C)) x 2 mvfC = 0.16 volts or
Vout (1)/-55°C = VCe - 1.56 volts. At Vee = 4.5 volts
Vout (1)/-55°C = 4.5 - 1.56 = 2.94 volts. As the input
"0" level degrades to 0.8 volts vansistor 02 starts turning on causing a voltage drop of IC2 x 1.6K to further
degrade the output. All these affects combine to produce a worst case "1" level output of 2.4 volts. If a "1"
level of VSS - 1.5 volts must be guaranteed, under all
the above condition, the TTL gate by itself can not
drive the MM4262/MM5262 inputs.
¢2 - Reads information from selected cells.
¢3 - Writes information into selected cells.
II. Memory System Application of
the MM4262IMM5262
A. Interface
In applying the MM4262/MM5262 device to any system
three distinct types of interface must be considered. The
'inputs, the output and the clocks each has unique inter,face requirements.
The inputs are TTL compatible. Let's look in detail at
what "TTL compatible" means. It does not mean that
the user can drive the MM4262/MM5262 inputs with any
TTL gate without giving it another thought. "TTL com·
patible" means that the MM4262/MM5262 can be driven
by TTL, if done properly, without the need of voltage
translation.
11·68
One solution, that will absolutely guarantee that the
VSS - 1,.5 volts "1" level requir.ement is met, with ample
noise margin, is to use a resistor connected between the
TTL output and the VSS supply. The penalties that are
. paid for this are increased number of components and a
slight increase in power. The TTL output will pull to the
VSS s,upplywith an RC time constant of the pull up
resistor and the capacitance of, the line, after the
maximum TTL "1" level has been reached. Figure 4
shows the form the TTL output would take when going
from a ,"0" to a "1". There would be no appreciable
difference between tlie "1" to "0" transistion with or
without the pull-up resistor. The pull·up resistor should
be selected to meet speed requirements and at the same
time keep power dissipation and load on the TTL gate
with:in allowable limits. Since most manufacturers of
standard 54/74 TTL specify speed with 50 pF load,
eight MM4262/MM5262 device inputs (8 x 7 pF = 56 pF)
coul.d be driven by a single 54/74 device. If more drive
capability is required, other devices such as the OM7096/
8096 hex Tri·State tID inverters are capable of driving
twice the capacitance that a 5404/7404 can drive, with
the same rise ti me.
in package count. It performs both the function -of
converting current to TTL levels as well as increasing fan·
out.
The OS1605/3605 family and the OS3625 sense ampli·
fiers are recommended for use with the MM42621
MM5262. The DS3625 is a dual sense amplifier and
ilTcdrporates a latch. The OS1605/2605 family isa hex'
se~se'amplifier. All have Tri-State tID outputs for bus
interface capability.
The clock signals for the MM4262/MM5262 have three
requirements which have the potential of generating
problems for the user. These requirements, high speed,
large voltage swing and large capacitive loads, ~ombine
to provide ample opportunity for inductive ringing on
clock lines, coupling clock signals to other clocks andlor
inputs and outputs and generating noise on the power
suppl ies. All of these problems have the potential of
causing the memory system to malfunction. ReCognizing the source and potential of these problems early in
the design of a memory system is the most critical
step. The object here is to point out the source of these
problems arid give a quantitative feel for their magnitude.
Line ringing comes from the fact that at a high enough
frequency any line must be considered as a transmission
line with distributed inductance and capacitance. To see
how much ringing can be tolerated we must examine the
clock voltage specification. Figure 6 shows the clock
specification, in diagram form, with idealized ringing
sketched in. The ringing 6f the clock about the VSS
level is particularly critical. If the VSS - 1 volt is not
maintained, at.£!! times, the information stored in the
memory could be altered. Referring to Figure 1, if the
threshold voltage of a transistor were -1.3 volts, the
clock going to VSS - 1 would mean that all the devices,
whose gates are tied to that clock, would be only
300 MV from turning on. The internal circuitry needs
this noise margin and from the functional description
of the RAM it is easy to see that turning a clock on at
the wrong time can have disasterous results.
v"
Vee
--- -
r--~--"""-'---
t
rVCC-vOUTU!
\,IOUTnl
_________"="l
vou,,"
V,N
Vout
FIGURE 4. Form of TTL Output With Resistive Pull· Up Driving
Capacitance Load
The output of the MM4262/MM5262 is of the current
sourcing type. A "1" level is represented as current of at
least 600l.lA (5001.lA for the MM4262) at an output
voltage of 1.8 volts. A "0" level is represented as a
current of less than 100l.lA at a voltage of 0 volts. It is
desirable to be able to tie the outputs of many RAMs
together. This can, in a large system represent a significant cepacitance. Since p-channel MaS does not have
large current drive capability current outputs are the
logical choice. They minimize the amount of output
voltage swing required. Which, for capacitive loads,
greatly reduces current drive requirements. The current
output does necessitate using a sense amplifier, but,this
is not a significant penalty. TTL output compatible
MaS circuits can typically drive only one standard TTL
load. They must therefore be buffered to increase fan·
out. The sense amplifier, in the case of the MM4262/
MM5262, takes the place of this buffer at no net increase
·VT{MIN)" minimum threshold II(llbge
FIGURE 6. Clock Waveform
Controlling the clock ringing is particularly difficult
because of the relative magnitude of the allowable ring·
ing, compared to the magnitude of the transition. In
this case, it is 1 volt out of 20 volts or only 5%. Ringing
can be controlled by damping the ciock driver and
minimizing the line inductance.
11·69
lD
N
CD
N
ID
:::E
:::E
Q)
..t:
+"
C)
c:
'iii
:::>
III
E
i
(/)
>
...
o
E
Q)
:::E
C)
c:
'2
.21
~
C
"It
~
Z
«
Damping the clock driver by placing a resistance in series
with its output is effective, but there is a limit since
excessive resistance will slow down the rise and fall time
. '.
of the clock signal. Because the typical clock driver can
be much faster thim the worst case driver, the damping
resistor serves the useful function of limiting the mini~
mum rise' and fall time. This is very important because
the faster the rise and fall times the worse the .ringing
problem becomes. The size of the damping resistor varies
because it is dependent on the details of the actualappli·
cation. It must be determined empirically. In practice
a resistance of 10D to 20D is usually optimum.
.~
"
~
",
'.
K- ----t:: "
"
......
"
"
'.
"
*
'J
Limiting the inductance of the clock lines can be accom·
plished by minimizing .their length and by laying out
the lines such that the return current is closely coupled
to the clock lines. When minimizing the length of clock
lines it is important to minimize the distance from the
clock driver output to the furthest point being driven.
Because of this, memory boardS are usually designed
with clock drivers in the center of the memory array,
rather than on one side, reducing the maximum distance
by a factor of 2.
h"
'J
'.
1v"
..'.
~
v"
"
r
'.
101\0
Using multilayer printed circuit boards with clock lines
sancjwiched between the VDO and VSS power plains
minimizes the inductance. of the clock lines. It also
serves the function of preventing the clocks from
coupling noise into input and output lines. Unfortun~
ately multilayer printed circuit boards are more expen·
sive than two sided boards, The user must make the
decision as to the necessity of'multilayer boards. Suffice
it to say here, that reliable memory' boards can be
designed using two sided printed circuit boards. The 16K
words x 10 bits memory board described in the example
at the end of this application note demonstrates this.
f-o
OUTPUT
'lD
V
...... "
"
FIGURE 7. Schematic of 1/2 DS0056
VOUT
+8.5 V
lAMP _ _
The recommended clock driver for use with the
MM4252/MM5262 is the OS0056/0S0056C dual clock
driver, This device is designed specifically for use with
dynamic circuits using a substrate, VeB supply. Typically
it will drive a 1000 pF load with 20 ns rise and fall times.
Figure 7 shows a schematic ofa single driver.
FIGURE 8. Clock Waveforms (Voltage and Currentl
In the case of the MM4262/MM5262 V+ is +5 volts and
V BB is +8,5 volts. VBB should be connected to the V BB
pin shown in Figure 7 through a 1 K resistor. This allows
transistor 08 to saturate pulling the output to within a
VCE(SAT) of the V+ supply. This is critical because as
was shown before the VSS - 1.0 volt clock level must
not be exceeded at any time. Without the VBB pull up
on the base of 04 the output at best will be 0.6 volt
below the V+ supply and can bel volt below theV+
supply reducing the noise .margin or this line to zero.
Because of the amount of current that the clock driver
must supply to its capacitive load, the distribution of
power to the clock driver must be considered. Figure 8
gives the idealized voltage and current waveforms for a
clock driver driving a 1000pF capacitor with 20 ns rise
and fall ti me.
11-70
As can be seen the current is significant. This current
flows in the VOD and VSS power lines~ Any significant
inductance in the lines will produce large voltage tran~
sients on the pow~r supplies. A bypass capacitor, as
close as possible to the clock driver, is essential inmini·
mizing this problem. This bypass is most effective when
connected between the VSS and VDD supplies, Abypass
capacitor for each OS0056 is recommended. The size
of the bypass capacitor depends on the amount of
capacitance being driven. Using a low inductance
capacitor, such as a ceramic or silver mica, is most effec·
tive. Another helpful technique is to run the V DO and
VSS lines, to the clock driver, adjacent to each other.
Thls tends to reduce the lines inductance and therefore
the magnitude of the voltage transients.
The output current of the clock driver during the transition from high to low or low to high may be as high as
l.5amps when driving a large capacitive load. Duringthe
transition from high to low thiscurrent.is also conducted
through the V- lead. If the external interconnective Vwire between the clock driver and the circuit driving the
clock driver is electrically long, or has significant DC
resistance, the .current transient will appear as negative
feedback and subtract from the switching response. To
minimize this effect short interconnecting wires are
necessary and high frequency power supply decoupling
capacitors are again required.
The output is current, so it is more meaningful to
examine the current that is coupled through a 1 pF
parasitic capacitance. The current would be:
This exceeds the total output current swing so it is
obviously significant.
Clock coupling to inputs and outputs can be minimized
by using multilayer printed .circuit boards, as mentioned
previously, physically isolating clock lines and/or running
clock lines at right angles to input/output Iines. All of
these techniques tend to minimize parasitic coupling
capacitance from the clocks to the signals in question.
While discussing the ciock driver it should be pointed
out that the DS0056 is a relatively low 'input impedance
device. It is possible to couple current noise into the
input without seeing a significant voltage. Since this
noise is difficult to detect with an oscilloscope, it is
often overlooked.
In considering clock coupling it is also important to have
a detail knowledge of the functional characteristics of
the device being used. As an example, for the MM4262/
MM5262, coupling noise from the ¢2 clock to the
address Iines is of no particular consequence. On the
other hand the address inputs will be sensitive to noise
coupled from the ¢ 1 clock.
An excellent source of information on MOS clock drivers
is Application Note AN-76, Applying Modern Clock
Drivers to MOS Memories. AN-76 is of general applica·
tion and it is recommended that the memory design·er
be familiar with it.
B. System Timing
Lastly the clock lines must be considered as noise
generators. Figure 9 shows a clock coupled through a
parasitic coupling capacitor, Cc ' to eight data input lines
being driven by a 7404. A parasitic lumped line induct·
ance, L, is also shown. Let us assume for the sake of
argument, that Cc is 1 pF and that the rise time of the
ciock is high enough to completely isolate the clock
transient from the 7404 because of the inductance, L.
With a clock transition of 20 volts the magnitude of the
voltage generated across CL is:
The timing diagram in Figure 2 defines the critical timing
parameters on the MM4262/MM5262. Timing parameters
are either generated by the system or controlled by the
physical characteristics of the MM4262/MM5262. There
is sometimes confusion regarding the definition of maxi·
mum .and minimum for these parameters. For instance,
the ¢1 clock pulse width, T 1 PW, is generated by the
system a~d for the MM5262 has a minimum value of
95 ns and a typical value of· 70 ns. It does not sound
correct to have the typical value less than the minimum
value. This specification simply means that the typical
MM5262 will function properly with a.T 1 PW of 70 ns
but a T 1 PW of at least 95 ns must be supplied if all
MM5262 devices are to function properly.
Cc
1
V ; 20V x - - - ; 20V x - - ; 0.35 volts
CL + Cc
56 + 1
Th is has been a hypothetical example to emphasize that,
with 20V fast rise/fall time transitions, parasitic elements can not be neglected. In this example 1 pF of
parasitic capacitance could cause system· malfunction,
because a 7404 without a pull up resistor has typically
only 0.1 volts of noise margin in the "1" state at 25°C.
Of course it is stretching things to assume that the
inductance, L, completely isolates the .clock transient
ftom the 7404. However, it does point .out the need to
minimize inductance in input/output as well as ciock
lines.
On the other hand Read Access Time, T ACC2, is an
MM4262/MM5262 characteristic. For the MM5262 it is
specified as 195 ns maximum and 150 ns typical. This
simply means that a typical MM5262 has a T ACC2 of
150 ns and no MM5262 has an access of greater than
195 ns.
Other parameters, such as T ACC1, are dependent on
both system generated timing (T AS and T 12) and
MM4262/MM5262 characteristics IT ACC1). T ACC2
maximum is obtained by setting T AS and T 12 to their
minimum and T ACCl to its maximum.
When setting up the system timing adequate margins
must be maintained such that under· worst case conditions all of the timing requirements are met. The main
point to considetin establishing these margins is the
variation in propagation delay of the components driving
FIGURE 9. Clock Coupling
1).71
OJ
From table 2:
the MM4262/MM5262. An example will best serve to
illustrate the type of problem that must be considered.
T3(min) -.T2(max) '" i 1 - 12'" -11 ns
Let us look at the timing of the rising edge of 1/>1 and
address inputs to the RAM. As we saw before it is
critical to maintain address setup and hold times
(TAS and T AH) for proper operation. Figure 10 shows
the logic diagram and timing for this example. Table 2
gives the minimum and maximum propagation delays to
AO and.pl·
Minimum
INA to AO
INB to 1/>1
Therefore, since -11 ns
The worst case conditions for T AH occur when' the'.p1
delay is maximum and the AO delay is minimum. From
Flgure2: .
Maximum
tpd 1
5 ns
22 ns
tpd 0
3 ns
15 ns
tpd 1
12 ns·
35 ns·
tpd 0
11 ns*
34 ns·
Substituting from table 2 gives:
TIAH +3 ns -34ns;;;'90 ns
or
*Estimated Using DS0056 Data Sheet
With the estimated worst case time of Table 2, TIAH,
input address hold time must be at least 59 ns.
Table 2
"A
This example demonstrates how the memory system
designer must account fl)r variations in propagation
delays of logic elements used to drive the MM42621
MM5262. As the details of the externa~ logic vary the
determination of critleal timing paths also vary. Some
tracking of delays in this logic can usually be anticipated.
In the above example we have assumed none. Tracking
of delays will produce, in general, a faster system. As
system performance depends more and more on component tracking to reach speed goals the risk of failure
also increases. The memory designer, with knowledge
and experience, must trade off this improved performance against risk.
><>---+---i~' --~""::",
-::'
-
'.
lJ10M14D4
IN·V
IIfiOMfolOl
>-12 ns all is well.
1120lDllSi
C. Refresh Requirements
In section I, detail description of operation of MM42621
MM5262, the need for restoring or "refreshing" the
information stored in the RAM was indicated. The
internal leakage is such that each cell of a MM5262
least every 2 milliseconds and the
must be refreshed
MM4262 at least every 1 millisecond. Since the RAM
refreshes on a row basis (32 rows) refresh could be
accomplished by applying 32 1/>3 clocks every 2 ms (1 ms
,
for MM4262). One 1/>3 clock for each row.'
at
FIGURE 10.
In this case, assuming there is no tracking of delays, the
worst case situation will occur for TAS when the.p1
delay is minimum and the AO delay is max;mum~ From
Figure 2:
Although address inputs AO through A4' row addresses,
must clearly.be defined during refresh, it is also necessary
that normal' ,set up and hold times be observed for the
column addresses, A5 through Al0' A reasonablealternative is to force. them to a logic "1" or "0" state and
sequence AO through A4 through their 32 states. U it is
more convenient to let A5 through Al0 vary, T AS and
T AH must be observed on those adtjresses during refresh.
Setting T 1PW at its minimum allowable value gives:
T AS '" T 3(min) + 95 ns - T 2(max) ;;. 80 ns
T 3(min) - T 2(max);;' -15 ns
11-72
D. Power Considerations
"'-0"
'===.
'1
.15"
Calculation of peripheral circuit power; assuming it is
TTL, is straight forward and won't be descri~ed here.
Clock power, which is dissipated almost entirely in the
clock driver, ,is completely described in application note
AN-76 mentioned previously. Again it is recommended
that the memory designer be familiar with this applica·
tion note.
,"' -_---------.
"
In describing power consumed by the MM4262/MM5262
the terms de and ac power should be defined. When
there is a resistive, .path for the cu rrent it is termed dc
power, even though the current may be switching. When
there is a capacitive path for the current it is termed, ac
power. These are not conventional definitions but it is
necessary to, make some distinction between the two
types of current. OC power is proportiomil to the duty
cycle of the clocks while AC power is proportional to
the frequency of the clocks.
. r-----
U
-tSV
n
1SOmA
.
1111mA
'
10m.
'm. _
"
..........,
?
,:\-.
- - - - - -___..,-_.J
Figure 11 shows 100 'for a typical ~M5262 operating at
FIGURE
T A = 25° C with a cycle of 840 ns. As can be seen a large
'current transient, 150 mA peak, occurs during the ~1
clock time. Current during ~1 clock time is, composed
of de and ac current. The dc current, 20 mA, is approxi·
mately constant throughout the ~1 clock interval. The
ac current results from precharging internal capacitive
nodes du,ring the ~l clock time. The remainder of the
currents are basically a combination of ac and dc
currents.
n.
.... ....=
TypioallOO at T A
III...
25°(:
The pi-imary purpose for showing the 100 current wave·
form' js to point out the magnitude of the current
transient during ~1 time. If the worst case current is
calculated using the above equation, with worst case
value forA, Band C with TCYC = 635 ns we get:
100 ma)( = 3 mA + 1.7 mA+ 15.7 mA
= 20.4 mA
Note 17, on the MM4262/MM5262 data sheet, gives an
approximate relationship for calculating 100' This rela·
tionship is:
T
'l .r
U
,.....---T",
....
Power consumed by a memory system using the
MM4262/MM5262 can be divided into four categories:
(1) Power required for peripheral circuitry, (2) Clock
power, (3) de power required by the MM4262/MM5262
and, ,(4) ac power required by the MM426,2/MM5262.
The initial ae transient accounts for approximately 77%
(15.7/20.4) of the total power ,dissipation of the RAM.
In addition to the 100 current there is also a current
transient due to the input clock capacitance of ~1 that
must be considered. With 20 ns rise time on the ~1 clock
this current is:
T
100=Ax 1PW+ Bx 2PW+ Cx 1000ns
TCYCTCYC
'TCYC
With the aid of Figure 11 the terms A, Band C can be
readily identified.
1= 50 x 10":12 farads x 20 volts/20)( 10- 9 sec = 50 mA
The A term is the value of the dc current during the ~1
clock ,interyal, T 1pw. The resulting average current is
simply A times the duty cycle (A x T 1PWrTCYC)' Tile
B term is the same thing for the ~2 clock interval, T 2PW'
The,pur~ose of pointing out all these transient currents
and their magnitude is to demonstrate the need far using
bypass capacitors with the MM4262/MM5262. If there is
significant inductance in the VOO. VSS and/or VBB
lines, serious voltage transients will result unless suffi·
cient bypass capacitors are used. Requirements vary with
actual application, but 0.1 I1F, from VOO to VSS and
from VOO to VBB, for every other RAM is usually
sufficient. Again. since bypass capacitors are attempting
to defeat line resistance and/or inductance, it is
important to place them physically as close as possible
The C'term accounts for the shaded area, Oc in Figure
11. Clc is the amount of charge transferred to the
internal node capacitance each Cl/cle. Therefore the
amount of charge' per unit time, I, is:, I = Oc/T CYC'
In the 'above formula for 100, C = Ocl1 0-6 sec. This
corresponds to an on chip capacitance of approximately
500 pF with which the chip bypass capacitors must
charge share.
11·73
III
Clock lines are by far the worst noise generators. Their
effects can be minimized by using series damping
resistors to guarantee that the clock voltage transitions
are no fastenhan is absolutely necessary.
to the RAMs they are intended to bypass. Using one
centrally located capacitor is effective for decoupling
transients generated on one board from getting into
another board" but usually will not help decoupl'l tran·
sient internal to the board.
Figure 12 gives a printed circuit pattern for laying out a
memory array using the MM4262/MM5262. This pattern
has been used successfully on RAM boards of up to 16K
words by 10 bits.
For techniques of minimizing total system' power the
reader is referred to application note AN·86. A Simple
Power Saving Technique for the MM5262 2K RAM.
AN-86 explores the use of clock decoding to minimize
the number of clocks that must be applied. It is easy
to see from the above discussion that this could produce
significant power savings since an unclocked RAM draws
only 10Cl/.LA from the VDD lirie.
'
E.
Ill. A 16K words J!: 10 bits Memory Application
Example
The MM4262/MM5262 has a wide variety of applications. One example is an 16K words x 10 bits memory
board developed by National Semiconductor's Memory
Systems Division. Photographs of the memory board are
included.
Printed Circuit Layout Considerations
All of the consideration in laying out printed circuit
boards for RAMs center around minimizing the induct·
ance of lines and capacitance coupling from ohe line to
another.
I II
I
I
Capacitive coupling is minimized by physically isolating
or shielding noise sources. Shielding using multilayer
printed circuit boards is probably the most effective but
is also the most expensive. Physical isolation can be
accomplished by running sensitive lines such as the data
out line at rig~t angles to the clocks and addresses.
Inductance can be minimized ,by keeping line lengths as
short as possible. Also, running a line and the return for
the line close together will reduce the effective inductance of the line. The effect of inductance on power
supply lines can be reduced with the use of bypass
capacitors. This solution is, of course, not acceptable for
data or clock lines.
VIS
VDO DATA DATA Vss
OUT
IN
FIGURE 12.
11-74
r--L
:.
I
I
iL
.r
~
z
1
I
T
:
I
II
"
l:.po
i~.~·~
1 ' TTT d
-----1'
:
1
I
c
!1
., T 1 "T
I
cQ'
:s
S·
I
I
I
j
I
:f"'" T
I
I
A Ii
n
A
CO
TtTt
s:CD
..3
......
......- ....
_--.. '! ..
~
.... •
o
<
,
C/)
~CD
3UI
c:
UI
~.
hI•
.-+
:sCD
:s:
s:
U'I
N
,.:
w
a:
:l
c.?
u::
------1
I
I
I
I
I
I
---,
.....---,.r--~f ~
'IL-r---t. .
"
J
I
I
G
II
~
I
I I
I
L-f'---f- J;
I
I
I
rJ~·i·r·~·H'··~r:I:·r~r l
11111~
; :;,
1 ,
~
'-d~¥fl¥¥¥¥~¥~F~ i
11·75
0'1
N
C
II:
~
~
aI
w >
II:
;;;
D-
0
~
0
:0
IU
:0
::
"
:.:
:2
11-76
l>
Z
tc
Ii
cS'
:::I
5'
ec
s:
3
()
.<
tJ)
-<
(/)
S
3
(/)
c::
(/)
5'
ec
...
i"
s:
s:c.n
N
G)
N
ID
11·77
.e
~
o
CD
c
CD
~
~National
App Notes/Briefs
~ Semiconductor
DM8678 BIPOLAR CHARACTER GENERATOR
The DM8678 is a 64 character bipolar character generator
with serial output, and packaged in a standard 16·plt(·
DIP designed primarily for the CRT display marketplace:
The DM8678 incorporates sevllral CRT system hivel
functions, as well as a 7 x 9 row scan character font.
The DM8678 performs the system functions of parallel
to serial shifting, character address latching, character
spacing, and character line spacing which are normally
done with extra packages. Figure 1 is a block diagram of
the DM8678.
Address Latch
The address . hitches are "Fall Through". or "Feed
Through" latches. The addre~ latches are illustrated in
Figure 2. When the address latch control signal is high,
the character addresses "Fall Through" the latch. And
when the address latch control signal goes low, the
character addresses are latched. A 40 ns address set:up
time is required.
ADDRESS .
LATCH
CONTROL
A6
A5
CHARACTER 64
ADDRESS
DECODER
1/64
A4
A3
. 64 X 63
ROM
A2
Al
CLOCK ____________~r-~r-------_,
CONTROL
LINE
CLOCK
EDGE·TRIGGER
GENERATOR
emrn -------------1
OUTPUT
OUTPUT
EmIm
F,GURE 1. Slocl< Diagram
ADDRESS
IN
A
,..-----A
---+---=t._/
1,
A~Z
B~
:::[)o--Z
ADORESS
LATCH
CONTROL
FIGURE 2. Addr... Latch
11·78
A
B
Z
0
0
0
1
1
0
0
0
0
1
1
A
B
Z
0
0
0
1
1
1
1
0
0
0
0
1
1
Logic operation is ~s follows: When the address latch
control signal is high, "AND" Gate A lis ,enabled and
"AND" gate A2 is disabled. In this 'mode, data "falls
through" the latch. When the address latch/!s control
signal goes low, Gate A 1 is disabled, blocking any new
address inputs. Gate A2 is enabled by, a high on input
"A" which allows the feedback todetermine the output
of gate A2. If the ,feedback is low, the output of A2 will
be low. If the feedback is high, the output of gate A2
will be high, Note that there are two inversions from the
output of gate A2 (01 and 11 ) to the.feedback loop.
Thus the feedback maintains the level that was present
on inverter 11 when the address latch control goes low,
The line counter is a mod 16 counter and its count can
which resets the counter to its
be shortened by
first state, when it goes to low state. "
crear,
7·Bit Shift Register
A 10bit parallel·in serial·out shift register is used to
serializ/!. the output data. Seven "0" flip·flops' and
seVen 2·line·to+line multiplexers are used to perform
the parallel to serial conversion. (Figure 4)
Operation of the parallel to serial converter is as follows:
the cycle begins with load enable going low. This routes
data from the ROM via the MUX to the "0" ,inputs of
the 7 flip·flops. The data at the "D" inputs is clocked
into the flip·flops on the next low·to-high transition of
the dot clock. Next,the load enable, goes high switching
the mux. Now data at the ''0'' input comes from the
"a" output of the preceding flip·flop stage.
ROM
The ROM is 64 x 7 x 9 = 4032 bits. The ROM comes
with a, standard upper case characterset.,And, it is possi·
ble ,to have custom fonts. A coding sheet is, included
with the data sheet. Obviously it is possible to make
smaller characters by not using all of the ROM. For
example, a 5 x 7 character set could be made. Also, it is
possible to use two chips to obtain a larger cHaracter set.
..
:r
..
...
(")
«»
I»
(')
CD
The first stage in the shift register is an exception and
the ml,lxroutes a low to its ''0'' input, with the, first
stalles "0" input low. After 7 clocks, all stages are low
and any additional clocks will produce a low output.
This feature is used for horizontal spacing between
characters.
Lin!! Counter
The line counter consists of a 4-bit ripple counter with
an asynchronous clear input. The input dock is shaped
by an edge·triggered clock generator. The clock genera·
tor's output clock pulse is enabled by the Clock control
signal. The, output pulse from the clock generator goes
to one input of a ,two input "AND" gate and the clock
control signal goes to the other input of the "AND"
gate. When the c,lock control, signal is low the clock pllise
is blocked by the "AND" gate. The line counter is
illustrated in Figure 3.
Output Buffer
The output buffer is a standard TTL TRI~TATE® out·
put circuit. The output enable is the TR I·STATE control
and when the enable is high, the output is in the Hi·Z
state. The output can sink 16 mA at 0.45V for a low
signal out, and,will source 2 mA at 2.4V for a high
signal out.
-F,
lINECP
~----------~~>-------4-----~------4-~~~
FIGURE 3. Line Counter
OJ
~-·r::>---....I
-F CLg~~-----L>---""
FIGURE 4. 7-Bit Parallel·ln Serial·Out Shift Register with Synchronous Load
11-79
on the next low-to-high transItion of the dot clock
with Line 1 of the character"N." The next 6 dot clocks
will shift out the rest of the first line of character .oN,"
If only a single character in a row was generated, the
line clock would go from low-to-high advancing the line
counter which in turn switches the multiplexer to Line 2
of the character. Line 2 contains the next 7 bits required
for generating "N." This would continue until the 9th
line has been clockeo out. Any additional line clocks
will put a vertical space between characters. This is
illustrated in Figure 5 .
OPERATION OF THE DM8678 CHARACTER
GENERATOR'
To illustrate operation <;>f the DM8678, an example is
given tracing the sequence of events involved in
generating a character. The character "N" is used in this
example. (Figures 1 and 5).
..
ctI
i
iii
co
.....
(0
co
::!:
o
.....
....
(0
I
Z
«
Generation of the character uN" begins with the appropriate 6·bit character address becoming valid on the
address inputs A1 to A6. This address can be latched by
bringing the address latch control signal low. There are
address set-up and hold times of 50 ns and 40 lis
respectively _
In a typical application, more than one character is
displayed in a row,(FigufYJ6) The sequence is as follows:
Line 1 of the first character is c:locked out'. Note that
7 dot clocks are required to shift out one line in a character. Additional dot clocks will add lows to the end of
the line. This provides a horizontal space between
characters. There is no limit to the number of clocks
which can be used to generate horizontal spacing. The
address· is changed to select the second character. Then
the first line of the second character is docked out,
next, the 'first line of the third. character is clocked out,
continuing until the first line of the last character in the
row has been clocked out. At this time, the line counter
of the DM8678is clocked, advancing the line counter
to Line 2. The first character is addressed again, and the
process of the scanning continues until. the 9th line of
the last character in the first row has been shifted out.
The output of the address latch is decoded in the
character address decoder. This is a 1/64 active high
decoder. The word line which contains the code would
go high.
The ROM contains the code required for generating the
64 7 x 9 characters. The ROM is organized 64 words
each, 63 bits long (7 x 9 = 63). In the ROM, the first
7 bits of 63 are line 1 of the character, the next 7 bits
store line 2 of the character and so on.Note that 1 bit =
1 dot. The lines and dots for our example "N" are
illustrated in Figure 5. The code for UN" would be:
1000001
Line 1
1000001
Line 2
1100001
Line 3
1000011
Line 7
1000001
Line 8
1.000001
Line 9
Then the line clock is again clocked, incrementing the
line counter to Line 10. All characters in the row are
scanned. (Figure 6) The output of the character generator for lines 10 to 16 is all lows. This provides a vertical
space between rows. The number of lines used to space
can be controlled by clear going low after the desired
number of lines of vertical space have been generated.
After the access time has elapsed (tasl =350 ns). the output of the ROM for Line 1 of the character (N for this
example) c~n be loaded into the shift register. When
load enable is brought low, the shift register is loaded
'.
1
COLUMNS
2
3
4
5
6
7
••
4. •• •••
••••
9.• ••
CH 1
ROW1~
2.
3 ••
LINES
5.
6.
•
•
•
7.
10
11
"DOTS
DISPLAY CAN BE UPTO
80 CHARACTERS/ROW
AND 24 ROWS
VERTICAL SPACE
13
14
• • • • 0
01-
12
SPACE
CH 2
0 .0 0
0
0
ROW"M"_
OTD
0
-1 1_
• • • • D
HORIZONTAL SPACE
15
16
L
COLUMN 1
COLUMN
"N"~
FIGURE 6. Display Example
FIGURE 5. Character Example
11-80
Clear: Active low dear for mod 1.6 row counter, (can
be used to truncate mod 16 counter) .
Next, the first line of the first character of the second
row is addressed and scanned.This continues until the 9th
line plus lines for vertical spacing of the last character
in the last row has been scanned. At this time the
display field has been written. For a CRT Display, it is
necessary to refresh the display. Displays are typically
refreshed 30 to 60 times each second. Memory is required
to store the character address so that they may be called
up when required for refresh.
Line Clock: Clock .that. advances the line counter.
Advances counter on the low·to-high transition.
Clock .Control: Enables line clock when high and
disables line clock when low.
Load Enable: Active low load command which routes
data. from the character ROM to the "D" inputs of the
7·bitshift register.
Figure 7 is the connection diagram and logic symbol.
Dot Clock: . A low·to·hightransition of the dot clock
loads the shift register if load .is low or shifts data if load
is hig!).
DEFINITIONS
»
2
...
I
0)
.....
c
:s:CO
0)
.....
CO
o:.J
-6'
o
...Qj'
Output Enable: An active low output enable. When high
the output is in the Hi·Z st~te.
(")
A1-A6: Character address. A 6·bit code which selects
1 of the 64 characters in the font.
Output: A TTL TRI·STATE output buffer.
Ql
:r
..,
Ql
(')
.....,
CD
Dual-In-line Package
Al
VCC
15
A2
14
Al
ADDRESS LATCH
CONTROL
C')
CD
16
4
A4
A5
::l
CD
...
iil
o...
A6
!!tEAR
OUTPUT ENABLE
OUTPUT
LINE CLOCK
LOAD ENi\ilU
CLOCK CONTROL
DOT. CLOCK
GND
TOP VIEW
FIGURE 11a). Connection Diagram
ADDRESS LATCH
CONTROL
Al
A2
Al
A4
A5
A6
LINE
CLOCK
CLOCK
CONTROL
FIGURE 7(b). Logic Symbol DM8678
1111
11·81
~National
a
App Notes/Briefs
Semiconductor
..
I
Q)
~
0-
~
o
~
PROM Power-Down Circuits
description
Inexpensive bipolar PROMs can be used in high perfor·
mance, low power applications if powered down when
they are not being accessed. Since the access time of the
circuit of Figure 1 is less than 80 nanoseconds, the
power saving can be greater than 10 to 1 if cycled every
microsecond. Longer cycle times, or decoding of the
power switching to multiple packages, cah yield even
more impressive ratios.
system cycle. Turning the PROM off when it is not
needed saves power and the aceess time is increased
by only the delay of the power down circuit.
The basic power down circuit is illustrated in Figure 2.
A TTL level. input signal drives the TTL logic input of
the power down circuit. The logic input is drawn as a
noninverting buffer; however, circuit operation is not
limited to noninverting buffers. Logic Tabl.e 1 illustrates
several logic implementations of both inverting and
non inverting inputs with different speed·power tradeoffs.
Bipolar PROMs with on-chip power-down have power-up
to power,down ratios of 3:1. Using the PROM powerdown technique illustrated in Figure 1, ratios considerably higher than 3:1 can be obtained. National's PROMs
perform well in this application. With power removed,
the Tri-State® parts revert quickly to the third (open
high Z) state. Because there are no clamp diodes from
the outputs to Vee, the powered down device presents
only leakage to the output bus.
Circuit operation is as follows. When the logic input to
R2 goes low, base drive is supplied to the PNP switch,
turning the switch on. C1 is aspeed·up capacitor which
decreases the switching time of the PNP switch. In
applications where high speed is not importantC, is
not necessary. When the PNP saturating switch is on
Vee (+5 V) is applied to the PROM. The time delay
from power up command to power up on the PROM
ranges from about 10 ns to 100 os, depending upon the
PNP switch and the TTL logic driving the switch.
PROMs do not need to be continuously powered in
many applications. Often data is required from a PROM
on system power up or for a small percentage of a
1JlJ7J
+5
,
~--'---~----------5V
TL LEVEL
INPUT SIGNAL
(ACTIVE LOW)
100 pF
ITIIT21
LEVEL
U
U rrn
INPUT SIGNAL
Cl
100 pF
OM14S281
Figure 1. PROM Power Down Circuit
Figure 2. PROM Power Down Circuit
11-82
l>
Z
We are now ready to calculate the value of resistor R2.
Resistor R2 is used to limit the base drive current of
the PNP 2N3467 transistor. The value of R2 is calculated
from the voltage across R2 and the base current required
to supply the Icc current required for the PROM.
log.ic table
i>LOGIC
cs
=D-14SOt1
74LSDO
Resistor calculation:
~
-a
:::D
o
3i:
""CI
Vcc
~
"..
VCC
• Fast
I
• Active High Selects
74S00Speed
74LSOO Speed and Low Power
2N3467
VSE
SAT·1VM~X
VOL
I
• Fast
cs --[>o--f>14S04
74lSG4
130mAMAX
rORPROM
• Active Low Selects
74S04 Speed Only
74LS04 Speed and Low Power
TTL OUTPUT
Of lOGIC CIRCUI
DRIVING THE
PNPSWITCH
• Very Low Power
cs--[>-- • Active Low Selects
MM14C9DZ
Ie =
Buffers can be connected in
parallel for additional current
130 mA = Icc
hfe =40
= 3.25 mA
min
Base current calculation:
Vcc - (VBE(SAT) + VOLIMAXI)
~
1/10
DECODER
MM74C42
~
R2=------~~----~--
• Very Low Power
• Memory Expansion
~ No Resistors Required
R1 and R2, Figure 2, not
required
IBVBE(SATI
+--R, = B20
R _ 5 - (1 T 0.5) V
2 - (3.25 + 1.0) mA
R2=~=823n
4.25mA
R2 = 820 n, rounding to the nearest standard value.
design example
Design a minimum power memory that has a 200 ns
access time, a 1000 ns cycle time, and a 256x8 memory.
Two DM74S287 PROMs will be used for the 256x8
memory. DM74S287s have a ± 5% power supply tolerance. Since there will be about a 0.2 V drop across the
PNP switch we need to ensure that the VCC requirement
of the PROM is met.
R, is chosen to be equal to the R2 to simplify the parts
list and this allows resistor packs (8 identical resistors
in a 16-pin package) to be used when appropriate.
Figure 3A is the final circuit for the 256 x B memory.
Performance of the 256x8 power down memory 'is:
Power when selected 1345 mW max
Power when deselected 0 mW with 74C902 buffer
Access time 180 ns max
Stnce speed is not of prime importance in this application
we will select "slow'~ low power parts in the power
down circuit. The 74C902 noninverting buffer will be
used as the logic input device. This device is selected for
its low power. 2N3467 PNP switch will be used as the
pass transistor.
Average power is a function of duty cycle, and for
our 256xB power down example average power is:
on time
200 ns
Pave(maxl = --.-.-. Power max = - - - . (665) (2)
off time
. 1000 ns
From the data sheets:
2N3467 PNP Saturating Switch
VCE(SAT)
Ic= 150mA typ=O.165 max = 0.3
hfe
Ic = 150 mA typ = 120
min = 40
max = 1 V
VBE(SATl
Ie =; 150 rnA typ =0.8
DM74S287 PROM
Icc = 80 mA typ, 130 mA max
74C902 Buffer
Icc = 15 JJ.A max
1
Pave(maxl =-(1330) = 265 mW max
5
The 265 mW assumes that all parts are maximum at
the same time. The more likely situation is that parts
will be at or near their tYPical value.
For our example:
1
Pave(typl ='5(830) = 166 mW avetyp
11-83
ID
Vce
I
C2 0.2~F
1I374C90Z
SELECT
--I I- . . ,. .-1
ZOO
"H"
SOD
LJ
MEMORY
~
ENABLE
SIGNAL
TTL "L"
.
I
Figure 3A. 256x8 Power Down Memory
VCC
RZ
S20n
1I674C902
1/674C902
Figure 3B.
VCC
1I614C90Z
1/6 74C902
Figure
3e.
11·84
»Z
....
vee
.r.
I
~
C2 0,2.F
"tJ
::D
0
s:
1/374C902
"tJ
0
.:E
CD
I
-::-
0
-::-
0
:E:::I
Figur.3o.
.
Q
n
c:
;:+
resistor
performance table
en
RADB
16
Typ
Access Time Max
74C902 Buffer
2N3467 PNP Switch
74S287 PROM
54 ns
20 ns
35 ns
--'109 ns
Power Selected
16 2N3467
74C902
74S287 at 5 V, 6.65 mW each
IS
13
14
12
11
10
9
Max
90 ns
40 ns
50 ns
--lBO ns
15 mW
-1330 mW
R
1
R
Z
3
R
R
R
4
5
R
6
R
7
R
B
TOP VIEW
buffer
MM54C9OZ/MM74C9DZ
MMMC904/MM74C904
1345 mW
Power Unselected
16 2N3467
74C902
74S287
o (leakage)
a (75/J.W)
a
OmW
TOP VIEW
GND
38 since the base current for the 2N3467 will be at least
9 mA, and typically will be higher. This adds some
power dissipation when the PROMs are powered up.
Figure 38 illustrates, a circuit simplification ,of removing
R, (the Ib2 resistor). Eliminating R,' saves a resistor and
the power dissipated by the resistoL R2 still determines
the base drive current which is VIR. This circuit will be
slightly slower than the circuit.s in figures 3A or 3C.
Figure 3D represents a minimum part count circuit for
the 256 x 8 PROM memory.
This application note illustrates several ways to power
down National's Schottky TRI·STATE® PROMs.
Powering down PROMs is a cost-effective method for
obtaining low power and fast access time.
Figure 3C illustrates a further reduction in the number
of resistors. Neither R 1 nor R2 is used. Speed will be
good and power will be higher than in figures 3A or
01
11-85
...
...IU
en
....o
Q)
C
~National
App Notes/Briefs
~ Semiconductor
Q)
(!J
C
o
TRIG FUNCTION GENERATORS
CJ
Accuracy is the major design variable of trigona·
metric lookup tables built with MaS read·only
memories. Only a few ROMs are needed for most
practical applications, but accuracy can be made
to increase very rapidly with memory capacity if
interpolation techniques are used.
+i
c
::s
u..
.~'
...
t-
......
O
G)
".:::
m
,--
I
I
I
I
For instance, without interpolation a single
1024·bit ROM can store 128 angular increments
and generate an 8·bit output that will be better
than 99.9% of the handbook value (Table 1).
en
o
BINARY
OUTPUT
0
1
2
0
0.7
I.'
2.1
00000000
00000011
0.012
.0000011Q
00001001
O,Q23
0.035
89.3
,11111111
0.996
127
ounUT
I
SINE
DEGREES
3
12611
l'IIR~O-OA
DECIMAL
ADDRESS
:e
"',;.:.":...,1-:-___--.___
0.000
(al
TABLE 1.MM422BM/MM522BM Sine Function Generator
f - -....---,.,
If one simply cascaded ROMs to improve input
resolution and output accuracy for a high-accuracy
trig solution (X~sin 0) as in Figure 1, large numbers of ROMs might be needed. This 24-ROM
system stores 2048 12-bit values of sin x (or other
trig functions), giving angular resolution of 1 part
in 211 (0.05%) and output accuracy of 1 part in
212 (0.024%). The system in Figure 2 has the
same resolution and is accurate to the limit of its
12 output bits (0.024%), which makes it just as
good. But it only requires four 1024·bit ROMs and
three 4-bit TTL full adders, so it only costs about
one-fifth as much as the more obvious solution of
. Figure 1.
Instead of producing x ~ sin 0, the Figure 2 system
divides the angle into two parts and implements
the equation
x
~
sin
f---H~--'-'
=l
==L-...!!....~:t+;::'-'
2- 4
...--'
~_...r-
"
,,,
e ~ sin (M + L)
~
sin M cos L
+ cos M sin L
It can be programmed for any angular range.
Assume the range is 0 to 90 degrees and let M be
the 8 mog significant bits of and L be the 3 least
significant bits of
(0 being' the 11-bit input
angular increments, equal to 90°/2048, pr
0.044 deg.) as in Table 2.
e
e
With an 8-bit address, the three 256x4 ROMs will
give the 12-bit value of sin M at increments of
M ~ 90° 12 8 , or 0.352 deg. The cos L can only vary
between 1 and 0.99998. So we assume cos L ~ 1
and store values of sin M at 0.352 deg. resolution
(bl
FIGURE 1. Conventional 204B-lncrement Sine Table Uses
24 ROMs
11-86
in the top three ROMs, reducing the equation to
sin
Since we are using an approximation, accuracy is
not quite as good as. the Figure 1 system. The
additional error term is cos L, assumed 1 but
actually is a variable between 1 and 0.9999B. At
every eighth increment, L is zero, making cos M
e ~ sin M + cos M sin L
Values of the second term are stored in the fourth
ROM, The maximum value of the second term in
th e above equation can only be cos Msin L
~ 0.00539 where cos Mmax = 1, sin Lmax
= 0.00539. This is the maximum value to be added
to sin M above. Only the five least significant bits
of a 12·bit output are needed to form th.e maxi·
mum output, so an MM522 is used in its 12BxB
configuration.
M
ADDRESS
L
M,
0
I
2
0
I L
I 0
3
I I
4
5
6
7
8
,--9
~
16
32
64
128
256
512
1024
204a·1
I
I
o
o
I
I
I 0
I 1
o 0
1 o 0
ro0 0
I
1
I 0 0' 0
1 o 0 o 0
1 0 o 0 o 0
1 0 0 o 0 o 0
1 o 0 0 o 0 o 0
1 0 o 0 o 0 o 0 0
I I I 1 I 1 1 I 1
..
tD
CD'
...o....
.
-I
cC'
0
I
0 M
1
3:
en
o
'T1
C
:;,
...0'
(')
=
0.3520
0
0 0
0 0
0 0
:;,
Ci)
CD
.....
o..
0 0
::l
o
o
II)
0
0
1 1
TABLE 2. Programming of 2048-hicrement Sine Table
CD
en
sin Le'O, and sin x=sinM to 12·bit accuracy. Then
the error rises to a limit of near 0.002% at every
eighth increment where L is 0.352-0.044. This
error can be halved by adjusting the fourth ROM's
output so that
sin () = sin M + cos (M-2.B1°) sin L
If five ROMs are used-'four MM521's andall eight
outputs of the MM522-15-bit accuracy can be
achieved, and thus improving the accuracy by a
factor of eight. The resolution could also be
smaller~ of course, if the angular range were
smaller as in an application involving a sensor with
a limited field of view. Variati.ons of the system
could be used to space the increments irregularly
to compensate for sensor nonlinearities, to improve accuracy in specific angular ranges.
,I
1
MM522
]lEASTSIG8ITS~r
MM521in 128 X 8 MODE-generates cos (M 4
sin L 3 MM521 generate sin M
$in a = sin M + cos (M4 - 2.8) ~io L
-
U)
This example has a binary fraction output, like the
sine function generator in Table 1. For instance,
the 8-bit output at the 64th increment representing sin x = sin 45° is 10110101 ... This equals
1 X T' + 0 X T2 + 1 X 2- 3 + 1 XT 4 + 0 X T S
+ 1 X T6 + 0 X T7 + 1 X T 8 , which reduces to
1811256 or 0.7070. Handbooks give the four-place
sine of 45° as 0.7071, so at this increment the
output .is accurate to approximately 0.01 %. This
table, the MM422BM/MM522BM, is used in fast
Fourier transform, radar,. and other signal-processing applications.
FIGURE 2. Four-ROM Lookup Table Generates 2048
Values of Sin x by Interpolation Technique.
Let the 4 most significant bits of M be called M4
and the angle at these increments tie Xm= 90° /2 4
= 5.63 deg. Sin L (the 3 least significant bits of e)
has the same maximum as before and cos M4 has a
maximum of cos 5.63 deg. = 0.99517, and continuing as follows:
cos (11.26)
~
0.98076
cos (16.B9) = 0.95686
cos (84.37) = 0.09810
Other standard tables that are available off the
shelf include an arctan generatpr, several code
generators (EBCDIC to ASCII, BCD to Selectric,
and Selectric to BCD) and ASCII-addressed charayter generators for electrpnic, electriCal and electromechanical display and printout systems. All
interface with TTL logic and operate off J 2-volt
power supplies. Write for data sheets, or use one of
our programming tables to jot down any special
input-output logic functions you need.
'through the 16 increments of M4 . Now
sin
e = sin M + cos M4 sin L
and the appropriate cos M sin L values are stored
in the fourth ROM. In effect, we have divided the
0° to 90° sine curve into 16 slope sectors with M4 ,
each sector into 16 subsections with M, and each
subsection 'into ·B interp~lation segments with L.
ll-B7
iD
~National
.
App Notes/Briefs
~ Semiconductor
...
Q)
Ul
tn
Q)
IX:
Ul
Q)
.~
CD
CJ
Q)
Co
en
tn
r::
E
E
.
.
CD
MASK PROGRAMMING SPECIALIZES
MOS SHIFT REGISTER DESIGNS
There are enough storage cells, I/O stages, clock
and power supply lines on each MM4007 chip
to make up to two 100-bit registers. The minimum
length of each register half, MA and Ms , is 20 bits.
The programmable parts, PA and Ps , may be 0 to
80 bits long. Lengths need not be equal. For
instance, register A may be 29 bits and register B
76 bits (P A = 9, Ps = 56).
A quick. economical way of customizing MOS
shift register bit lengths is programming the metal·
lization mask. the mask that defines the thin·film
wiring pattern etched on the silicon wafer. Metallization etching is the most convenient process step
to specialize because it is consistent from wafer
to wafer and is the last major process step before
testing.
Utilizing this technique, National Semiconductor
has developed two variable-length dynamic MOS
register designs. 60th of them, MM4007/MM5007
and MM4019/MM5019, are bipolar compatible.
Dual registers 20 to 256 bits long, single registers
40 to 512 bits long, and a variety of taps and
pinouts provide the system designer with a. method
of obtaining custom length shift registers quickly
and at reasonable cost .
v§
TOPVIEW
tn
o
I:L.
~
Ul
CD
~
...
o::t
Q)
.;:
FIGURE 1. Dual Shift Registers
Up to metal masking, wafer design and fabrication
are standardized. No time is lost-or money spentin developing custom arrays or tuning up the
process. Automatic test systems further reduce
turnaround. time and production costs.
An MM4019/MM5019 chip is similarly organized,
except that MA and Msare 40 bits and PA and
Ps vary from 0 to 216 bits. Again, lengths may
be unequal, such as 240 bits in the A half and 136
bits in the B half.
Clock and supply line pin locations are standardized, but I/O pinouts are selectable. The I/O
terminals on the chip may be bonded to package
pins which are more convenient for the PC board
layout. For· example, a couple of board feedthroughs might be eliminated by bonding the A
register input to Pin 7 (rather than Pin 1) if data
comes in from the right and exits on the left. Or, .
A and 6 could share an input pin when they have
the same signal source.
Programming the metallization. mask mainly involves routing signal connections past sel.ected
storage cells to adjust total register length to the
desired number of cells. Wire-bonding changes
provide oLitput tap options,
DUAL REGISTER DESIGNS
Basically, each of the variable-length types is a
dual register (Figure 1 and Table 1A).
TABLE 1 Register Length Options
MM4007/MM5007
MM4019IMMS019
M
(BITSI
P
(BITS)
TOTAL
(BITS)
M
(BITS)
P
(BITS)
TOTAL
(BITS)
A Register
20
a to 80
20 to 100
40
20
Oto 80
20 to 100
40
o to 216
a to 216
40 to 256
B Register
MA +M.
PA + p.
MA +M.
PA + p.
80
o to 432
A. DUAL REGISTERS
40to 256
B. SINGLE REGISTERS
40
o to 160
40 to 200
80to 512
C. TAPPED SINGLE REGISTERS
Total register length same as Single registers with tap locations determined by either half of the dual registers.
11-88
v..
SINGLE-REGISTER OPTIONS
Since clock rates' are synchronized by the common
clock inputs, the registers may also be. serially
connected inside the package, as diagrammed in
Figure 2.' One output is internally connected to
the other input.
This extends the maximum length of an MM40011
MM5007 to 200 bits and. the MM4019/MM5019
maximum to 512 bits. However, each half still
has the same minimum, so the minimums become
40 and 80 bits, respectively (Table· 18). Again,
the customer specifies the most convenient I/O
pin connections.
TDPVIEy/
FIGURE 30
vo_
V"
TOP VIEW
FIGURE3b
FIGURE 3. Output Tap Options
OPERATING CHARACTERISTICS
FIGURE 2.
All specifications, except bit lengths, are the same
as those of other MM4000/MM5000 series dynamic
shift registers with the same number of 110 stages.
v..
Clock-line capacitance, power dissipation, as well
as other AC and DC .parameters, are independent
of the lengths programmed. This is accomplished
by standardizing clock and. supply wiring patterns
to achieve minimum turnaround time and cost.
v.
The MM4007/MMS007 and MM4019/MMS019 are
fabricated using a low-threshold, p·channel enhancement'mode technology developed for th'e
MM4000/MMSooO series of registers. This means
that t~ey are bipoll!r compatible, sensing TTL or
DTL data without input pull-up resistors and
driving TTL or DTL loads without output pulldown resistors. They operate on standard +SV
and -12V supplies. The clock frequency range
is also the same, from 300 Hz to' 2.S MHz,
guaranteed.
TOPVIEW
FIGURE 2b
FIGURE 2. Single Register.
Going to the output tap designs of Figure 3
takes only one more wire bond; from the first
register output to any available pin. Tap locations
are selected by specifying the bit lengths of each
of the dual registers. For example, an MM5007
105 bits long may be tapped at any stage' from
20 to 85 bits: Generally; this flexibility makes
input taps unnecessary-an output at 29 bits in
105;bit register usually serves the same purpose
as an input at 76 bits.
3:
en
o
fA
..
..
':T
:;;
::D
CD
CD
In
CD
cCD
In
to'
:::s
In
Either TO-99 or dual-in-line packages may be
specified. MM4007 and MM4019 \>perate at -SSoC
to +12SoC. MMS007 and MMS019are commerical
types, specified for -2SoC to +70°C.
.
a
OJ
11-89
!II
CD
N
i:ii
'E
App Notes/Briefs
~National
.~ Semiconductor
tV
"0
C
tV
....
C/)
I
C
o
Z
S
f
DOUBLE·CLOCKING CUTS STANDARD
REGISTERS TO NON-STANDARD SIZES
CD
,;
C)
CD'
a:
"c
"-
tV
"0
INTRODUCTION
C
S
C/)
!!::s
o
C)
,5
..lI!:
CJ
o
C3
It may be more economical to make a standard
MOS register appear shorter, logically, than to
have a special register made to order. A doubleclocking techriique uses up the unwanted length
by causing input bits to be stored twice .and then
to be read out as individual bits when they reach
the end of the re.gister ..
Suppose a parallel array of eight 1991-bit registers
is needed to store 1991 8-bit words in a buffer
memory. Each could be a subassembly as in
Figure 2. the MM5013 and MM5016 are standard
1024-pit and 512·bit register and the MM5019 is
.mask·programmed to order in sizes up to single
512 or dual 256-bits.
Figure 1 .shows the clock format. A doubl.e clock
applied for N of the normal input data intervals
at a fixed portion of tl1e total reCirculation time
The design in Figure 3 provides the same length
with two MM5013 registers. The eight registers
are assembled with 16 instead of 24 packages.
cD
Also, the second MM5013 costs less than an
MM5016/MM5019 combination (the longer the
register the less the cost per bit). The only addition
to overhead logic is the decoder and dual clock
generator formed with the logic in the dotted
lines-one DM7473 dual J-K flip-flop and half a
package each of DM7400 and DM7420 gates.
:a::s
o
Q
...
CD
i
't;
m
C/)
DOUB~HlO~~
NORMAl·CLOCK
FIGURE 1. Clock rate is doubled for N data i"put periods
to make the regist~r appear shorter by N bits.
In the example, N=2048-1991, or 57. Therefore,
the registers should be clocked at double frequency
for the first 57 data periods of ~he recircula·
tion time. The extra logic decodes the bit~counter
output and generates the 114 clocks needed.
anc;l then resumes normal frequency.
o
:E
will shorten the register by
periods. If N is 2, a '·0 input
be stored as 1:' ·0·0. Since
output at the time. the dock
output gate only detects '·0.
N stages and clock
data sequence would
these appear as the
is again doubled, the
There are some limitations to this technique.
Obviously, the normal rate should not be more
than half the maximum clock rate for the registers
DATA OUTPUT
FIGURE 2. Mask-programmable MM5019 register may be used to assemble odd-length registers.
11-90
3:
used .. Also, if too many bits are subtracted, the
clock-drive loading may be affected adversely. The
driver power requirement is propOrtional to average
frequency. In the example, it is increased by
f(2048/1991) or 2.8%, which has little effect.
But if an MM5016 was shortened from 512 to
397 bits, the increase in power would be 28%. In
this case, instead of shortening the MM50l6, it
may be more practical to order an MM5019 at
the desired length. At still shorter lengths, the
MM5007 mask-programmable dual 100-bit pro:
granima"ble register should be. considered. Generally
speaking, double-clocking becomes more costeffective when the system register length is long.
o(I)
III
~
CD'
....,
...
CJ)
oo
c
cr
DATA INPUT
DATA OUTPUT
(i'
,
n
g
7t:'
~---------------l
I
I
I
I
II
I
I
IL
I
A,
112DM7473
S'
(Q
(')
C
r+
C/I
"I"
en
r+
A, - - - - - i . - : /
III
:::I
Q.
III
a.
_____________ _
:D
CD
(Q
!'
CD
U1
r+
o
Z
FIGURE 3.
A 2048·bit register is made to appear only 1991 bits long
by the logic within the dotted lines.
'
o
:::I
en
r+
III
:::I
Q.
III
a.
(I)
N'
CD
C/I
(II
11-91
~National
~ Semiconductor
Definition of Terms
-I
...
CD
Clock Repetition Rate: The range of clock frequencies for which regis,er operation is guaranteed.
Data Output Voltage Levels: The output voltage
levels (logic VOL or VOH ) which the output will
assume under normal operating conditions.
Clock Frequency d: L to VH transition and the start
of a ¢2 VH to VL transition. The same spacings
apply, when q,2 precedes q,1_
Partial Bit Times TIN. TOUT: The time between
leading edges of clocks, measured at the V¢H
levels_ TIN is the time between the leading edge of
OUT and the
leading edge of q,IN'
Output Resistance to. Ground: The resistance
between the output termin.al and ground with the
output in the logic Va H state.
Clock Phase Delay : The time delay between
the 10% and 90% voltage points on the clock pulse
as it traverses between its logic VL and logic VH
levels.
Output Source Current: The current which flows
out of the output terminal of the register when the
output is a logical High level. Conventional current
flow is assumed.
Clock Pulse Falltime, tf: The time delay between
the 10% to 90% voltage points on the clock pulse
as it traverses between its logic V1>H and logic VL
levels_
Clock Pulse Width, L
or V H) which the clock driver must assume to
insure proper device operation.
VGG Current Drain: The average current flow out
of the VGG terminal of the package with the output open circuited.
Clock Control Setup Time, t".: The time prior to
the clock Low to High transition at which the
clock control must be at its desired logic level.
Power Supply Voltage, VGG: The negative power
supply potential required for proper device operation; referenced to VssPower Supply Return, VSS: The Vss terminal is
the reference point for the device. It must always
be the most positive potential applied to the
device.
Clock Control Hold Time, fch: The time after the
High to Low transition for which the clock control
must be held at its desired logic level.
Data Setup Time, tds: The time prior to the clock
High to Low transition at which the data input
level must be present to guarantee being Clocked
into the register by that clock pulse.
Vss Current Drain: The average current flow into
the Vss terminal of the package. It is equal to the
sum of the IGG and IDD currents.
Data Pulse Width, tdw: The time during which the
data pulse is in its VI H or VI L state.
Power Supply Voltage, Vo D: The negative power
supply potential required for proper device operation, referenced to Vss.
Data Hold Time, tdh: The time after the clock
High to Low transition which the data input level
must be held to guarantee being Clocked into the
register by that clock pulse.
Clock Input Voltage Levels, VHVl: The voltage
levels (logic "1" or "0") which the clock driver
must assume to insure proper device operation_
Data Output Voltage Levels, VOH, VOL: The output voltage levels (logic "1" or "0") which the
output will assume with a specified load connected
between output and Vss line.
Data Input Voltage Levels: The voltage levels
(logic VI L or V IH ) which the data input terminal
must assume to insure proper logic inputs.
A1
3
III
II)
E
CD
to-
....o
c
o
:-e
c
;;::::
CD
C
Data Input Voltage Levels, VIHVIL: The voltage
levels (logic "1" or "0") which the data input
termi nal must assume to insure proper logic
inputs.
Control Initiate Window: The time in which a load
command signal must be appl ied to affect bit time
tn' This time extends from the start of to' to the
start of tes'
Control Release Time, fer: The maximum time
that a load command signal can be changed prior
to the V,pL to V,pH transition of the output clock,
.::
a..
PackageS
40-Leed Cavity DIP (D)
NS Package Number D40C
....
.....
...
ii:i3ii
iiiiii
UIO-I.328
.A•
0-110
~~"J
I~~
i-=:~~~, .I
,:.:::,
MAX 10TH EIOS
tl'
0.1&0
GLASS
(l.38._,.,"'....
"ALANT
--l ~
0.200
~,::.:=::, J
--i
13.17i,
~
(9.719 tlW51
i5.iiii
~[r!f'~'
,::,
MAX
r
0.125
(1tJij
MI.
MI.
Package 9
14-Lead Cavity DIP (J)
NS Package Number J14A
Package 10
l6-Lud Cavity DIP (J)
NS Package Number J16A
'.IU
ii.iiii
RAD
GLASS
SEALANT
h
UIO:l:O.ol.'
l2.5411tOJ541 TV'
Package lOA
18-LeadCavity DIP (J)
NS Package Number J1SA
A6
0.12&
(3.175)
MIN
....
...
~
............
I-I'-+---L iiiii=f.jjjj
Packa9a 108
22·Lead Cavity DIP.(J)
NS9ackage Numb.... J22A
.IIl'
(ijjij
.AD
-
§~.
T
G.ltS
~.1"1
MIN
Pac~1OC
24·Lead UV Window Cavity DIP (JQ)
NS Package Number J24C
'I f·....
et......
AX
.oz.
...
~~~--rGLOA
(a_)
0.515-0.&25
~Trr,rTrr~;r.rr.""~;rr.r",";m",~~3.ml
Package 11
24·LtIad C••ity DIP (J)
NS Package Number J24A
A7
ml
(II
c
o
'0
c
G)
.5
• .1125
(0.635)
c
AA.
0.515-e.s25
~7rr.TTIT~~rr.~~orr.r~~~~~~ """113"~
Cij
(,)
i.c
a..
0.0211-0.070
-jf,
0.018
~D.II02
~
Package 11A
28-Lead Cavity DIP ID}
NS Package Number J2SA
...,
...,
.
0.570
GU4.478)
MAX--j
IUB&,NOM -
(2.3311
os
DlA
DIANOM
11
&
•
7
~
I
_ __
I
a.1371
N.M
PIM NO.1 INDENT
0250t0..005
PIN NO. t IDENT
~~~F.F~9ffirl~
'.0lD
1~r
--
,-.~
::=Li
I
D.121i +0 025
(0.229-0.3811
0 OQ5tD !l15
(D.Ii08j
0.1110
-alii
D07",~1 ~ 1--J1--"18,:=r-r
..
-
0. 125 (~:81
I:::
(2;540)
~)-......l
0.325~:~~
13.1751
(1255 +0.136)
~
rl'O"'--tt---ilr
. ' -'.OZ.
MIN
IJ
'
'
- .," ~ I cl-.
''''-0.0''
I
D.I30±OJlll5
0.065
:~:I MIN
(8.255:~~)
~
(O.457.tO.D78J
8.100
(~!~:l
MIN
(2.5411)
TY'
TY'
Package 12
8-Lead Molded DIP IN)
NS Package Number NOSA
Package 13
10-Lead Molded DIP IN)
NS Package Number N10A
,.",
tum
OIA NOM
PIN NO. t INDENT
O.OlD
1I.JOO.--O.320
0.030
(7JW1-11ZII
(0.162)
I I l~tX
~f==l
I.H5
~
~JC:JF
. -+10.2211-""1
I
0.325 :~:
I
0.300-0.110
0040
IJ
0.015+0015
(1.90S±O.lIU
~'OZ::1211
013010005
9,·121;
{""I
I~
1-
L
O.tllO
~2v~1
.~.
11.6511
PI. . -,· " 'J
~D
----1- ;'''1
II D0181:0.003 ~
~f-~(~~51
W
I:::'
I
MIN
~
+8.o25!
0.325 .....815
0.015 ±D.olli
(1.905:t8.JI1)
(8'''~::::)
(e.z5S~::~)
Package 14
l4-Lead Molded DIP IN)
NS Package Number N14A
Package 15
l6-Lead Moldad DIP IN)
NSPackage Number N16A
AS
O.13hO.OO5
1-~~~~_(;;~"108)~~~~-:-I
0.092
/2.331)
DIA NOM
0.092
(2.337)
DIA NOM
PIN NO. llDENT
MAX
PIN NO.1 IDENT
/6.350±O.121j
~nTTi;rrrrr.rr.iT1'ffr.rr.~--L
0.300-0.320
0.300-0,320
11.620-8.128)
£1.0<30
(0.162)
rr.~". "~Jl t-- J
~
I 0325~:~~ !
(8.255 ~~;)
9.025±0015
10635+0.381)
DIDO
(2
\--18.763) ---{
MAX
MAX
/0.762)
0.130 ±MOS
I
-a.IODio,.OI0--l
j--{2.540:tD.254)
(0.457 ±O:016)'
Package 16A
20-Lead Molded DIP (N)
NS Package Number N20A
b.12~:BI.AX=-:J
,.n" ""
20"
0.350",0.005
PIN NO.1
~
1r.i=r.;'f\T'F.T~=rn=T1T~-r;;;d~
'."'-'.OI'J I-
-~
0.425-+0,025
I-~~
(10.115 ~:::~)
"·"1
RAD {1.57S)
IDENT
11.050 ±O.DIS
~
,-J I0.100±0.010
~
(0.457;1:0.076)
Package 17
22 Lead Molded DIP (N)
NS Package Number N22A
I
0.063
O.540±O.OO5
(1.6(10)
~"""ffi'm=r.r=r.";;nm-ffi'T.i=r.;Ff.;nm=!'J
RAD
1271
1---(15.Z.40_'5'748)~.
.~~
~::1271
0.601HU20
(1.905)
(1.016)'
rill'
~
0.6Z5+0.025
-11.015
t---('5.875~::~)-------l
(0.229-0.381),
0.015;1;0.015
(1.905 ±D.J81)
11.160 ±0.005
n
~~
-ct.
I .'N
.
'''''_D.DI5~
.
I
f---
~
'
0.10iJ
I--(Z.540)
TYP
Package 18
24,Lead Molded DIP (N)
NS Package Number N24B
A9
==L.""
r- O.018±o.oOl --{I~
I
(I.90St-D.127)
Package 16
18-Lead Molded DIP (N)
NS Package Number N18A
""
::s
~~----------++--------'~L
~~
0.062
3
GI
0.1130
1 ,.34,1
I 'II UII±O.QUJ
~ 1'-10"" ;0.07&1
g
,--1
0.018:1:0.003
--11--(0.457:':0.'076)
0.125
13.175)
MIN
(3.175)
MIN
UI
o·::s
UI
O.!ZO
1•• 508)
MIN
II)
c
o
r-~-~--
'iii
I "
cCI)
E
23
22
21
1.210
(32.258)MAX
20
I
0.062
I
11.575)
c
0.540:,;11005
RAD
(13.716 ~O.1l7'
I
~~~~~~~~~
IV
(.)
'iii
>
.r:.
c..
0.030
om
D~
(1905)
-.:..........
...
II.160±0.D05
~~~L
TYP,
J
0.009...(1015
(0229-03111
0075,0015
(1.90!i!O.361) -)
,.,.1 ":811
0015
I--
1
I
--;
1_
D111D
1(2.540)
TYP
_ "- "18".,
II(O.451:tD.016)
~
(3.175)
MIN
Package 18A
24-Lead Molded DIP (N)
NS Package Number N24A
1.410
0.062
(1.575)-..........
RAD
PIN NO. I INDENT
~
~ ....""...,,,,-,.,.,..-=...,,,~"r"T,,....,.,,...=-=..,.,,r-TO,,...,,,,...=-' ~
0.030
~
f
1
0.600-0.620
~}
=
---l~
(O.762J~
MAX 11.524)
-LL-l
t::J-th-r 0009-0 DIS
0.625 +0.025,
~~-------1
(15.875
0.050
~(1270)---I U1300005)
~:~!~)
(0229-0 J81)
0075-0015
It 905 +0 3811
~~~(J3Q2'ilI271
L
J
~
1
--l
I
r-
I
0.100
r-- ~v~O)
--11
r--
----+
0018·0003
(0
~o
(0508)
(t;~:l MIN
457 =0 076)
Package 19
28-Lead Molded DIP (N)
NS Package Number N28A
2.070
I
0.062
(1.515)
I
O.!i50±O.OO5
(1J.970:,;O.127)
RAD
PIN NO.1 INDENT
'=rn=r;;=r,;=;~~~~~;;=r.:;=;~~~ J-
t"f T~(5:
"'"'"II.DlD
0.060 10.162)
0.050
f-lr-(1'·~74'1
-::;j
t
TVP
0.009-0.015
r----- O.~.25'--o:D15 ---1
+G025
(15.815 +O.6J5)
~
I
"-----,:T
~.
11.015 to.D15 ~
(1.905 ±O.Jll)
,
I
r-
~I
j
~
112.540)
TVP
Package 20
40-Lead Molded DIP (N)
NS Package Number N40A
A10
---II--
O.018·±O.uDl
(0.457 ±O.076)
--+ ~o
(~:)
0.125
(3.175)
~
f--'------I~~!I----,----!II
MAX
,• • n l'
'.17I_uI1B~i;'1
1
UII
i15.iiii
NO. 1.IDENT
~- <" - r:rT;" "'iT'imr:ri T'r.rm-r: lI"'T.':" ":r'J
Package 21
24-Lead Ouartz Lid Cavity DIP (0)
NS Package Number D24C
~':-lYtT000
I~:::::'..j I-
1::'
(1~:'
MAX
Package 22
4- Lead TO· 72 Metal Can
Paokage (H)
NS Package Number H04C
0.335-6.l7D
DIA ~ -t-~---:--'"i
0.165-0.185
r---~*(~::;=::l
~14---H-------->
CIA
0.185-0.11&
(4.1.1-4....1
0.040
-I-::;::=i:!:::;;;;;::;;;::;;;;::~-.r- (UlIl
~~8LEADS
LlAX
(:!:=::~I
'M'
t-rt!~~
112.(5)
MI.
DIA
0.821-0.131
iUii=i:iiiJ
Package 23
S·Lead TC>-5 Metal Can
Package (H)
NS Package Number HOSC
Package 24
10-Lead TO-5 Metal Can Package (H)
NS Package Number H10A
A11
Package 25
12- Lead TO·S Metal Can Package (H)
NS Package H12B
III
r:::
"iii
r:::
Q)
o
E
c
co
(J
"iii
.r:::>
'''''
usn
(2.032) MAX
Il.
0.025±0.010
D.060±D.OO5
(0.&35t0.254)
(U10±O.1271
0.004-0.006
(0.ID2-0.1U)
PIN NO.1
IDENT
J
I ,.,"-,...,
I-~
Package 26
14,Lead Flat Package (F)
NS Package Number Fl4B
Package 25A
IO·Lead Flat Package (F)
NS Package Number FIOA
0.050-D.DlO ~
.~l
1:~::=:::::}1··f· I:~:.;=::)
O.DIM-o.006
10.102-0,152)
I
(OJ02-o.1S2~m
o.050±O.ODS
0.010-0.02&
(0.254-0.&35)
.
i
':~::=::':~.
"'' -1'-_ __
_ _ _ copies@$3.00,FETDatabook, 77; ........................................... Total $,_ __
_ _ _ copies@$4.00,lnterface Databook, 10/75................................ Total $,_ __
_ _ _ copies@$4.00,LinearApplications,Vol.l, 2173....................... Total $,_ __
_ _ _ copies@$4.00,LinearApplications,Vol.lI, 7/76 ...................... Total $,_ __
_ _ _ copies@$4.00,LinearDatabook, 6/76 ...................................... Total $'1>-_ _
_ _ _ copies@$3.00,Memory Databook.1/76 ................................... Total $,_ __
_ _ _ copies@$5.00,PACEDesigner's Guide, 1977 ...... ;................. Total $,_ __
_ _ _ copies@$4.00,MOS/LSIDatabook,1977 ................................ Total $,_ __
_ _ _ copies @ $5.00, 8080A Microprocessor
System Design Manual, 3/77 .................... :....... Total $'-.--_ _
_ _ _ copies @ $5.00, PACE Microprocessor Assembly
Language Programming Manual, 1/77 ............ Total $,_ __
_ _ _ copies @ $5.00, PACE Microprocessor System
Design Manual, 3/77 ........................................ Total $,_ __
_ _ _ copies@$3.00,PowerTransistorDatabook,1977 ................... Total $,_ __
_ _ _ copies @ $5.00, SC/MP Microprocessor
Applications Handbook,
~_ _ copies
.
H~77..
....................... Total $,_ __
@ $5.00, SCIMP Microprocessor Assembly
Language Programming ManuaL....... ............ Total $'--_ _
_ _ _ copies@$3.00,SpeciaIFunction Databook,4/76 ..................... Total $'--_ _
_ _ _ copies @ $4.00, TTL Databook, 2/76 ................ :.................. ,..... Total $_ __
_ _ _ copies @ $3.00, Voltage Regulator Handbook, 5/75.................. Total $_ __
Subtotal '11-$_ __
(California. Residents Add 6% Sales Tax*) '1'-$_'_ _
*(San Francisco 8ayArea Residents Add6V2%'Sales Tax)
Grand Total $ _ - -
MAIL TO:
NATIONAL SEMICONDUCTOR CORP., c/o MIKE SMITH
P. O. BOX 60876, SUNNYVALE, CA. .94088
Postage wl.11 be paid by National Semiconductor Corp. Please allow 6-8 weeks for delivery.
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No Create Date : 2016:08:12 18:46:15-08:00 Modify Date : 2016:08:12 19:33:52-07:00 XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Metadata Date : 2016:08:12 19:33:52-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:5facb5c0-9f82-8a43-a022-4130efec1a3b Instance ID : uuid:5c96d0a6-4996-d547-811a-dfdf29a6d59b Page Layout : SinglePage Page Mode : UseNone Page Count : 566EXIF Metadata provided by EXIF.tools