1977_Signetics_Bipolar_and_MOS_Memory 1977 Signetics Bipolar And MOS Memory

User Manual: 1977_Signetics_Bipolar_and_MOS_Memory

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2

Si!lDotiCS

RaPid improvement in both the cost and performance of
semiconductor memories has led to a dramatic increase in
their usage in today's highly sophisticated electronic systems.
Signetics has worked diligently over the the last 10 years to
develop the various technologies necessary to satisfy the
broad range of users' semiconductor memory requirements.
As a result, in 1977, Signetics is able to offer the broadest
bipolar and MaS memory product lines available in the
industry.
Signetics offers a complete line of bipolar Schottky RAMs,
PROMs and other special memory products for high speed
applications. These products are available with organizations
ranging from 64 to 1024 bits for the RAM family and 256 to 8K
bits for the PROM family. All Signetics' bipolar products are
fabricated with double level metalization for maximum packaging density and low cost. PROM fuses are constructed with
nichrome links for the highest reliability and programming
yield in the industry. Signetics will continue to advance bipolar
memory "state of the art" in 1977 with the introduction of our
new 16K PROM, 4K RAM and programmable array logic products.
The MaS memory standard product line spans the many
diverse memory application requirements of today's industry.
Signetics' dynamic RAMs offer high bit density coupled with
low standby power, while our static RAM family offers speed
and ease of use. Ultra-violet (UV) eraseable EPROMs are
available for use in development programs, with their ROM
counterparts, in 8K and 16K densities in volume production. All
Signetics' MaS 2600 series ROMs have a single +5V power
supply and all industry standard pinouts are available. The
MaS memory division also offers a complete shift register and
character generator line.
The 1977 Signetics Memory Data Manual contains all necessary data on currently available products and those products
which will be available in the future. In addition, the following
pages provide product selection guides to aid the user in
quickly selecting the optimum product for his particular system application.
Signetics reserves the right to make changes in the products
contained in this book in order to improve design or performance and to supply the best possible products. Signetics also
assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from
patent infringement.

Si!lDotiCS

3

4

StgDotiCS

TillE OrCOnTEnTJ
INTRODUCTION ................................. i . . . . . . . . . . . . . . . . . . . . . ;. . .... . . . .

.. . . . . . . . . .. . . . . . . . . . . .

9

Bipolar Memory Cross Reference ....................................•........ '" .... '" . . . . . ... . . . . . . . . . . . .
Bipolar Memory Selection Guide ...................................,.... ,...................................
MOS Memory Cross Reference ............................................................................
MOS Memory Selection Guide....... . . . .... . . . ......................... ........... ........................

11
12
14
17

BIPOLAR MEMORY DATA SPECiFiCATIONS..............................................................

21

CAMs
10155

16-Bit ECl CAM (8X:!!) ..................................................................

23

32-Bit Bipolar Multiport Memory (8X4) ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-Bit Bipolar Multiport Memory (8X4) ...................................................

27
27

SAMs
82S12 (O.C')
82S112 (T.S')

RAMs
8'2S25 (O.C')
3101A (O.C'>
54174S89 (O.C'>
54174S1~9 (T.S'>
82S21 fO.C')
82S16 (T.S')
82S116 (T.S'>
82S17 (O.C')
828117 (O.C')
54174S200 n:.s,)
54174S201 n.s')
54174S301 (O.C')

82809 (O.C'>
82S10 (O.C')
82S110 (O.C'>
82S11 (T.S')
82S111 (T.S,)
93415A (O.C')
93425A (T.S')
82S208 (T.S')
82S210 (T.S')
82S400 (O.C')
82S400A (O.C')
82S401 (T.S.)
82S401A (T.S')

64-Bit Bipolar Scratch Pad Memory (16X4) ..............................................
32
64-Bit Bipolar Scratch Pad Memory (16X4) ..............................................
32
64-Bit Bipolar Scratch Pad Memory (16X4) ............................................... 32
64-Bit Bipolar Scratch Pad Memory (16X4) ..............................................
32
64-Bit Bipolar Write-While-Read RAM (32X2) ............................................
36
256-Bit Bipolar RAM (256X1) ............................................................
43
266-Bit Bipolar RAM (256X1) .......... ,.................................................
43
256-Bi't Bipolar RAM f256X1) ............................................................
43
256-Bit Bipolar RAM (256Xn ............................................................
43
256.;3it TTL RAM (256X1) ...............................................................
47
256~Bit TTL RAM (256X1) ..... ;........... ..............................................47
256-Bit TTL RAM (256X1) ......................•........................................
47
576-Bit Bipolar RAM (64X9) .............................................................
52
1024-Bit Bipolar RAM (1024X1) .........................................................
56
1024-Bit Bipolar RAM (1024X1) .........................................................
56
1024-Bit Bipolar RAM (1024X1) .........................................................
56
1024-Bit Bipolar RAM (1024X1) .........................................................
56
1024-Bit Bipolar RAM (1024X1) .........................................................
60
1024-Bit Bipolar RAM (1024X1) .........................................................
60
2048-Bit Bipolar RAM (256X8) " . . ..•. . . . . . . . ... . . . . . .. . . . . . .. ...• .. . . ... . . . . . . . . .. . .. . . .
64
2304-Bit Bipolar RAM (256X9) ...........................................................
64
4096-Bit Bipolar RAM (4096X1) ............. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
4096-Bit Bipolar RAM (4096X1) .........................................................
67
4096-Bit Bipolar RAM (4096X1) .........................................................
67
4096-Bit Bipolar RAM (4096X1) .........................................................
67

ROMs
82S226
82S229
82S214
82S230
82S231
82S215
82S240
82S241
8228

(O.C')
(T.S')
(T.S'>
(O.C')
(T.S')
(T.S')
(O.C')
(T.S')

1024-Bit
1024-Bit
2048-Bit
2048-Bit
2048-Bit
4096-Bit
4096-Bit
4096-Bit
4096-Bit

Bipolar ROM
Bipolar ROM
Bipolar ROM
Bipolar ROM
Bipolar ROM
Bipolar ROM
Bipolar ROM
Bipolar ROM
Bipolar ROM

(256X4)
(256X4)
(256X8)
(512X4)
(512X4)
(512X8)
(512X8)
(512X8)
(1024X4)

70
70
72
75
75
72
77
77

........................... ', ............................ .
S!!)RotiCS

80

5

82S280
82S281
82S290
82S291

(O.C')
(T.S')
(O.C')
 •...•..•....
16,384-Bit Static MOS ROM (2048X8) .••.................................•...............
16,384-Bit Static MOS ROM (2048X8) ....................................................
16,384-Bit Static MOS ROM (2048X8) ....................................................
16,384-Bit Static MOS ROM (2048X8) ....................................................

221
225
232
236
236
239
242
242
246
250
250
254
254

CHARACTER GENERATORS
2513
256o-Bit Static Character Generator (64X8X5) ............................................
2516
3072-Bit Static Character Generator (64X6X8) ............................................
2526
5184-Bit Static ROM/Character Generator (64X9X9) ........................•.............

258
263
268

UV EPROMs
1702A
2704
2708

2048-Bit Electrically Programmable MOS ROM (256X8) ..............•...................•
4096-Bit Erasable and Electrically Reprogrammable MOS ROM (512X8) .•.................
8192-Bit Erasable and Electrically Reprogrammable MOS ROM (1024X8) ..•...............

274
279
279

Hex 32-Bit Static Shift Register (32X6) ................................••...............•.
Hex 40-Bit Static Shift Register (40X6) ...............•••. ,...............................
Dual 50-Bit Static Shift Register (50X2) ................••....••..........•••.............
Quad 80-Bit Static Shift Register (80X4) ....•...•................•..•..••........••......
Dual 10o-Bit Static Shift Register (100X2) ................................................

283
283
286
289
286

Dynamic
llD3
2660
2660-1
2660-2
2660-3
2680
2680-1
2680-2
ROMs

Sialic
2530
2609
2607
2608
2608-1
2580
2600
2600-1
2600-1
2616
2616-1
2617
2617-1

SHIFT REGISTERS

Sialic
2518
2519
2509
2532
2510

SmnOliCS

7

2521
2522
2511
2527
2528
2529
2533

Dual 128-Bit Static Shift Register (128X2) ..•..•••.•••••.•••••••••••.•.....••.••.••..•.•..
Dual 132-Bit Static Shift Register (132X2) •....• ,.........................................
Dual 200-Bit Static Shift Register (200X2) •••.••••••••••••••••..•.••........•..•..•.....•.
Dual 240-Bit Static Shift Register (240X2) .....•.•••.•.••••••••..••••............•.•......
Dual 250-Bit Static Shift Register (250X2) ........•....••.••••..•••••••............•....•.
Dual 256-Bit Static Shift Register (256X2) .........•.•.•.•••••..••••..••..•...............
1024-Bit Static Shift Register (1024X1) ..•••••.••••••••••••••••....•.....•..•••.••.•.....•

292
292
286
295
295
295
298

Dynamic
2506
2507
2517
2505
2524
2502
2503
2504
2512
2525

DuaI100-Bit Dynamic Shift Register (100X2) ..••••••.•..•••..................••.•.•.•...•
Dual100-Bit Dynamic Shift Register (100X2) ..•.•••.••...••....•..••.••.•....•..•••...•..
Dual 100-Bit Dynamic Shift Register (100X2) ...••.•..•..•••....•..•..••.•..•...•.•..••...
512-Bit Recirculating Dynamic Shift Register (512X1) ••••••••••...•.......•...•.•.•.•...•
512-Bit Recirculating Dynamic Shift Register (512X1) •..••••.•.••••.•.•.........•........
1024-Bit Multiplexed Dynamic Shift Register (256X4) •••••••..•..•.....................•..
1024-Bit Multiplexed Dynamic Shift Register (512X2) •••••••.•••••.••.•.••...•.....•......
1024-Bit Multiplexed Dynamic Shift Register (1024X1) •...••.•••••.••••.••..........•...•.
1024-Bit Recirculating Dynamic Shift Register (1024Xll .•••..•.••.•.••.•......•.•.••...••
1024-Bit Recirculating Dynamic Shift Register (1024Xll •.••••.••.•....•...........•......

300
300
300
302
305
307
307
307
302
305

MILITARy................................................................................................
PACKAGES ..............................................................................................
SALES OFFICES ................................. ',' . . . .. . . . . . . . . . . . . . . . . . .. . . . . . .. ... . .. . . . . . . . .. . . . . . . . . .
INDEX ...... ......... ........ ........ .......... ...... ......... .................. ......... .... ............

311
329
345
349

8

SmODtiDS

InTRODUCTion

SmOOliCS

9

10

9~nD1iI:9

BIPOLAR MEMORY CROSS REFERENCE
AMD

SIGNETICS

HARRIS

SIGNETICS

INTERSIL

SIGNETICS

MMI

SIGNETICS

2700/27LSOO
2701/27LS01
27S08/27LS08
27S09/27LS09
27S10
27S11
3101
3101A/27S02
93415
93415A
93425
93425A

82S16
82S17
82S23
82S123
82S126
82S129
82S25
3101A
82S10
82S10
82S11
82S11

10149
10144
10410
10415
93403
93406
93411
93411A
93415
93415A
93417
93419
93421
93421A
93425A
93427
93431
93436
93438
93441
93442
93446
93448
93452
93453
93454
93457
93464
93467

10149
10144
10144
10146
82S25
82S226
82S17
82S117
82S10
82S10
82S126
82S09
82S16
82S116
82S11
82S129
82S130
82S130
82S140
82S131
82S240
82S131
82S141
82S136
82S137
82S280
82S126
82S281
82S129

5501
5508
5508A
5518
5518A
5523
5523A
5533
5533A
5600
5603A
5604
5605
5610
5623A
5624
5625
56506
56526

82S25
82S10
82S10
82S11
82S11
74S201
82S16
74S301
82S17
82S23
82S126
82S130
82S140
82S123
82S129
82S131
82S141
82S136
82S137

82S140
82S141
82S146
82S147
82S136
82S137
82S180
82S181
82S2708
82S17
82S16
82S09
82S25/3101A

SIGNETICS

82S25
82S23
82S123
82S2708
82S126
82S129
10149
82S130
82S131
82S140
82S141
82S136
82S137
82S115
82S180
82S181
82S184
82S185

6340-1
6341
6348
6349
6352
6353
6380
6381
6385
6530
6531
H6555
6560

FAIRCHILD

0064
HM7602
HM7603
HM7608
HM7610
HM7611
7615
HM7620
HM7621
HM7640
HM7641
HM7642
HM7643
HM7647
HM7680
HM7681
HM7684
HM7685

NATIONAL

SIGNETICS

INTEL

SIGNETICS

2708
2716
3101
3101A
3106/A
3107/A
3301A
3302
3322
3601
3602
3604
3605
3608
3622
3624
3625
3628

82S2708
82S2716
82S25
3101A
82S16
82S17
82S226
82S230
82S231
·82S126
82S130
82S140
82S136
82S180
82S131
82S141
82S137
82S181

MOTOROLA

SIGNETICS

4004A
4064
4256
5005
10139
10144
10149

82S226
82S25
82S16
82S126
10139
10144
10149

74187
74S188
74S287
74S288
74S387
74S570
74S571
74S572
74S573
8582
86L99
87S295
87S296

82S226
82S23
82S129
82S123
82S126
82S130
82S131
82S136
82S137
82S17
82S25
82S140
82S141

MMI

SIGNETICS

T.I.

SIGNETICS

6200
6201
6205
6206
6246
6247
6300-1
6301-1
6305-1
6306-1
6330
6331

82S226
82S229
82S230
82S231
8204
8205
82S126
82S129
82S130
82S131
82S23
82S123

2708
74187
74S188
74S189
74S200
74S201
74S209
74S270
74S287
74S288
74S289
74S301
74S309
74S370
74S387
74S472
74S473
74S474
74S475
74S476
74S477

82S2708
82S226
82S23
74S189
74S200
74S201
82S11
82S23O
82S129
82S123
3101A
74S301
82S10
82S231
82S126
82S147
82S146
82S141
82S140
82S137
82S136

Parts are pin for pin functional replacements except where noted. Signetics supplies most devices
in both commercial and military temperature ranges.

Smnotics

11

BIPOLAR MEMORY SELECTION GUIDE
ORGANIlATION

OUTPUT
CIRCUlT1

CAMS
10155

8X2

DE

SAMS
82S12
82S112

8X4
8X4
16X4
16X4
. 16X4
16X4

DEVICE

RAMS
82S25
3101A

54/74S89
54/74S189
82S21
82S16
82S116
82S17
82S117
541 74S2OO

54/74S201
54/74S301

32X2
256Xl
256Xl
256Xl
256Xl
256Xl
256Xl
256Xl

82S09
82S10
82S110
82S11
82S111
93415A
93425A
82S20882S21082S40082S401-

1024Xl
1024X 1
1024Xl
1024X 1
1024Xl
1024Xl
256X8
256X9
4096Xl
4096Xl

64X9

ROMS
82S226
82S229
82S214

256X4
256X4
2;j6X8

ACCESS
TIME [ns)'

TEMPERATURE
RANGP

PACKAGE

NO.
OF PINS

MAX.
ICC [rnA)'

-

13

e

F,N

18

140

oe
TS

T
T

40
40

e
e

F,N
F,N

24
24

160
160

oe
oe
oe
TS
oe
TS
TS
oe
oe
TS
TS
oe

B
B

M,e
M,e
M,e
M,e
e
M,e
e
M,e
e
M,e
M,e
M,e

F,N
F,N
F,N
F,N
F,N
F,N
F,N
F,N
F,N
F,N
F,N
F,N

16
16
16
16
16
16
16
16
16
16
16
16

T

50
35
50
35
50
50
40
50
40
50
50
50
45

M,e

I,N

28

105
105
105
110
130
115
115
115
115
130
130
130
190

B
B
B
B
B
B
B
B
B
B

45
35
45
35
45
45
60
60
70
70

M,e
e
M,e
e
M,e
M,e
e
e
e
e

F,N
F,N
F,N
F,N
F,N
F,N

16
16
16
16
16
16
22
24
18
18

170
170
170
170
170
170
185
185
155
155

-

50
50
60

M,e
M,e
M,e
M,e
M,e

F,N
F,N
F,N

16
16
24

120
120
175

F,N
F,N
F,N
F,N
F,N
F

16
16
24
24
24
16

140
140
175
175
175
170

24
24

140
140

24
24

170
170

oe
oe
oe
TS
TS
oe
TS
TS
TS
oe
TS
oe
TS
TS

82S230
82S231
82S215
82S240
82S241
8228

512X4
512X4
512X8
512X8
512X8
1024X4

TTL

82S280
82S281

1024X8
1024X8

oe
TS

82S290
82S291

2048X8
2048X8

oe
TS

oe
TS
TS
oe
TS

OUTPUT
LOGIC!

T

B
T
T
T
T
T

B
B
B

-

-

-

50
50
60
60
60
50
70
70
80
80

*To be announced
NOTES·

1. Output circuit:
3. Temperature range:
OE =Open emitter
C =Commercial (0 0 C to +75 0 C)
OC = Open collector
M = Military (-55 0 C to +125 0 C)
TS =Tri-state
All ECl 10.000 series (-30 0 C to +85 0 C)
2. Output logic:
4. Commercial (O°C to +75° C)
T = Transparent-input data appears on output during Write
B = Blanked-output is blanked during Write

12

Si!lnOliCS

M,e
M,e
M,e
e
M,e
M,e
M,e
M,e

F
F,N
I
I

F,N
F,N
F,N
F,N

'.

BIPOLAR MEMORY SELECTION GUIDE
DEVICE

DRGANIZATION

(Cont'd)

OUTPUT
CIRCUIT'

OUTPUT
LOGIC'

ACCESS
TIME Insl

TEMPERATURE
RANGE'

PACKAGE

NO.
OF PINS

MAX.
ICC ImAI

EQUIVALENT ROM

-

50
50
15

M,e
M,e
e

F,N
F,N
F,N

16
16
16

77
77
145

-

40
50
50
20

F
F,N
F,N
F

16
16
16
16

140
120
120
150

82S226
82S229

F,N
F,N
F,N
F,N
F,N
F,N

24
16
16

175
140
140

82S214
82S230
82S231

24
24
24

175
175
175

82S215
82S240
82S241

PROMS
82S23
82S123
10139

32X8
32X8
32X8

oe
TS
OE

82S27
82S126
82S129
10149

256X4
256X4
256X4
256X4

oe
oe
TS
OE

-

-

-

-

-

82S114
82S130
82S131

256X8
512X4
512X4

TS
oe
TS

-

-

60
50
50

82S115
82S140
82S141

512X8
512X8
512X8

TS
oe
TS

-

60
60
60

e
M,e
M,e
e
M,e
M,e
M,e
M,e
M,e
M,e

82S136
82S137

1024X4
1024X4

oe
TS

-

-

60
60

M,e
M,e

F,N
F,N

18
18

140
140

-

82S180
82S181
82S2708

1024X8
1024X8
1024X8

oe
TS
TS

-

-

-

70
70
70

M,e
M,e
M,e

24
24
24

175
175
175

82S280
82S281

82S184
82S185

2048X4
2048X4

oe
TS

-

100
100

M,e
M,e

F,N
F,N
F,N
I
I

18
18

120
120

-

82S190
82S191

2048X8
2048X8

oe
TS

-

-

70
70

M,e
M,e

I
I

24
24

175
175

82S290
82S291

FPLAS
82S100
82S101

16X48X8
16X48X8

TS
oe

-

50
50

M,e
M,e

I,N
I,N

28
28

170
170

-

PLAS
82S200
82S201

16X48X8
16X48X8

TS
oe

-

50
50

M,e
M,e

I,N
I,N

28
28

170
170

-

FPGAS
82S102
82S103

16X9
16X9

oe
TS

-

30
30

M,e
M,e

I,N
I,N

28
28

170
170

-

-

-

-

-

-

-

-

"To be announced
NOTES
1. Output circuit:
OE = Open em itter
OC = Open collector
TS = Tri-state
2. Output log ic'
T = Transparent-input data appears on output during Write
B = Blanked-output is blanked during Write
3. Temperature range:
C = Commercial (0 0 C to +75 0 C)
M = Military (_55 0 C to +125° C)
All ECl 10.000 series (-30° C to +85 0 C)
4. Commercial (O°C to +75°C)

SfgDDliCS

13

MOS MEMORY CROSS REFERENCE
SIGNETICS
RAMs
AMD
AM2101/9101
AM2111/9111
AM2112/9112
AM2102/9102
AM9060
AM9216
AM9208
AM1402
AM1403
AM1404
AM1405
AM1506
AM1507
AM2806
AM2807
AM2808
AM2809
AM2833

ROMs

E
PROMs

SHIFT
REGISTERS

2101
2111
2112
2102/2102A
2680
2617
2608
2502·
2503
2504
2505
2506
2507/2517
2512
2524
2525
2521
2533

AMI
6830

2608

EA
2308/8308
4600

2608
2600

FAIRCHILD
35L38
2102
4096
3343
3343
3347
3349
3533

CHARACTER
GENERATORS

2101
2102
2660
2521
2522
2532
2518
2533

GI
2513
2516
2530
2580
9316A1B
2509
2510
2511
2533
INTERSIL
IM7552
IM7712
IM7722
IM7780

14

2530
2580
2616

2513
2516

2509
2510
. 2511
2533
2102
2512
2525
2532

9i!100liC9

MOS MEMORY CROSS REFERENCE (Conl'd)
SIGNETICS
RAMs
INTEL
2101
2111
2112
2102/2102A
1103
21078
2104
2115
2125
2114
2308
2316E
2704
2708
1402A
1403A
1404A
1405A
MOSTEK
MK4007
MK4102
MK4096
MK4027
MK30000
MK34000
MK3708
MK1007
MOTOROLA
21021 A
6604
6830
6570
NATIONAL
MM2101
MM2111
MM2112
MM2102
MM5280
MM506
MM507
MM1402A
MM1403A
MM1404A
MM2521
MM2522
MM5058

ROMs

CHARACTER
GENERATORS

E
PROMs

SHIFT
REGISTERS

2101
2111
2112
2102/2102A
1103
2680
2660
2115"
2125"
2614"
2607
2616
2704
2708
2502
2503
2504
2505

2501
2102
2660
2627*
2607
2316
2708
2532

2102/2102A
2660
2608
2609

2101
2111
2112
2102
2680
2506
2507/2517
2502
2503
2504
2521
2522
2533

S(gDotiCS

15

MOSMEMORY CROSS REFERENCE

(Cont'd)

SIGNETICS
RAMs

ROMs

CHARACTER
GENERATORS

E
PROMs

SHIFT
REGISTERS

TI
TMS4039
TMS4042
TMS4043
TMS4033-35
TMS1103
TMS4060
TMS4700
TMS3112
TMS3120
TMS3128
TMS3129
TMS3133

16

2101
2111
2112
2102/2102A
1103
2680
2607
2518
2532
2521
2522
2533

SI!IDltiCS

MOS MEMORY SELECTION GUIDE
OUTPUT
CIRCUIT'

DEVICE

ORGANIZATION

RAMS
Static
2501
25LOl
2101
2101-1
2101-2
2111
2111-1
2111-2
2112
2112-1
2112-2
2606
2606-1
2102
2102-1
2102-2
2102A
2102AL
2102A-2
2102AL-2
2102A-4
2102AL-4
2102A-6
21F02
210F02-2
21 F02-4
21L02
21L02-1
21 L02-2
21 L02-3
2115'
2115L'
2125'
2125L'
2614'
2613'

256Xl
256Xl
256X4
256X4
256X4
256X4
256X4
256X4
256X4
256X4
256X4
256X4
256X4
1024X 1
1024Xl
1024Xl
1024Xl
1024X 1
1024X 1
1024X 1
1024Xl
1024X 1
1024X 1
1024Xl
1024Xl
1024Xl
1024X1
1024Xl
1024X 1
1024Xl
1024X 1
1024X 1
1024Xl
1024Xl
1024X4
4096Xl

TTL
TTL
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS

Dynamic
1103
2660
2660-1
2660-2
2660-3
2680
2680-1
2680-2
2627'
2627-1'
2627-2'
2690'

1024Xl
4096Xl
4096Xl
4096Xl
4096Xl
4096Xl
4096Xl
4096Xl
4096Xl
4096Xl
4096Xl
16,384Xl

00

00
00
TS
TS
TS
TS

TS
TS
TS
TS
TS
TS
TS
-

-

ACCESS/CYCLE TEMPERATURE
TIME (nsl
RANGE!

PACKAGE

NO. OF PINS

CLOCK/CE/TTL
COMPATABILITY

POWER
SUPPLIES (VI

+5, -9
1:5, -12
~5, Gnd
+5, Gnd
+5, Gnd
+5,Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5,Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd

1000/1000
1000/1000
100011000
500/500
650/650
1000/1000
500/500
650/650
1000/1000
500/500
650/650
7501750
500/500
1000/1000
500/500
650/650
350/350
350/350
250/250
250/250
450/450
450/450
650/650
350/350
250/250
450/450
1000/1000
500/500
650/650
400/400
45/45
45/45
45/45
45/45
200/200
200/200

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

I, N
I, N
F, N
F, N
F, N
.I, N
I, N
I, N
F, N
F, N
F, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N

16
16
22
22
22
18
18
18
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
18
18

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

300/480
250/375
300/425
350/500
140/375
200/400
270/470
350/800
150/320
200/200
250/250
150/375

C
C
C
C
C
C
C
C
C
C
C
C

I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F, I, N
F
F
F

18
16
16
16
16
22
22
22
16
16
16
16

No
Yes
Yes
Yes
Yes
No
No
No

-

-

-

-

+20, +16,
+12, 1:5,
+12, :!:5,
+12, :!: 5,
+12, 1:5,
+12, :!:5,
+12, :!:5,
+12,:!:5,
+12, :!:5,
+12, :!:5,
+12, :!:5,
+12, 1:5,

Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd

'To be announced
NOTES
1. Output circuit:
TS =Tri-state
00 =Open drain
BO = Bare drain
PO = Pull down
PP =Push-pull
2. Temperature range:
C = Commercial (0 'C to +75 ~C)
M = Military (-55' C to +125 'C)

Si!)DotICS

17

MOS MEMORY SELECTION GUIDE
DEVICE

ORGANIZATION

ROMS
Static
2530
512X8
2609
128X9X7
2607
1024X8
2608
1024X8
2608-1
1024X8
2580
2048X4
2600
2048X8
2600-1
2048X8
2616
2048X8
2616-1
2048X8
2617
2048X8
2617-1
2048X8
2632"
4096X8
2633"
4096X8
CHARACTER GENERATORS
2513
64X8X5
2516
64X6X8
2526
64X9X9
UV EPROMS
1702A
2704
2708

256X8
512X8
1024X8

OUTPUT
CIRCUITI

ACCESS/CYCLE TEMPERATURE
RANGE!
TIME (ns)

TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS

(Cont'd)

PACKAGE

NO. OF PINS

CLOCK/CE/TTL
COMPATABILITY

POWER
SUPPLIES (V)

-

700/700
500/500
500/S00
550/550
450/450
950/950
500/500
300/300
450
350
450
350
SOO/500
450/450

C
C
C
C
C
C
C
C
C
C
C
C
C
C

I, N
F,I, N
F,I, N
F,l, N
F,I, N
I, N
F,I, N
F,I, N
F,I, N
F,I, N
F,I, N
F,I, N
I, N
I, N

24
24
24
24
24
24
24
24
24
24
24
24
24
24

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

-

:!:5, -12
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, -12
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd
+5, Gnd

TS
TS
TS

600/600
600/600
700/700

C
C
C

I, N
I, N
I, N

24
24
24

Yes
Yes
Yes

:!:5, -12
:!:5, -12
+5, -12

TS
TS
TS

1000/1000
450/450
450/450

C
C
C

I
I
I

24
24
24

Yes
Yes
Yes

+5, -9
+12, :!: 5, Gnd
+12, :!: 5, Gnd

STANDARD ROM CODE
DEVICE

STATIC ROM
2530
2608
2609
2580

CODE NO.

DESCRIPTION

CM3530
CNOOOO
CN6571
CN6571A
CN6575
CMXXXX

Code Converter, ASCH to EBCDIC and EBCDIC to ASCII
10X7 Upper and Lower Case ASCII Character Generator
128 ASCII Characters in 7X9 Matrix Count Down
128 ASCII Characters in 7X9 Matrix Count Up
128 ASCII Characters in 7X9 Matrix Count Up with Special Characters
Random code pattern for evaluation purposes

CHARACTER GENERATOR
2513
CM2140
CM2170
CM3021
CM3030
CM4800
2516
CM2150
CM3001/3010
CM3041
CM3970/3980
2526
CM3400
CM3940
CM6760

New ASCII Character Generator, Upper Case, 7X5, Horizontal Scan
ASCII Character Generator, UpperCase with Yen Sign, 7XS, Horizontal Scan
ASCII Character Generator, Lower Case, 7XS, Horizontal Scan
Old ASCII Character Generator, Upper Case, 7X5, Horizontal Scan
Katakana Character Generator, 7X5, Horizontal Scan
ASCII Character Generator, Upper Case, 5X7, Vertical Scan
ASCII Character Generator, Upper Case, 10X7, Vertical Scan (2 chips)
ASCII Character Generator, Lower Case, 10X7, Vertical Scan
ASCII Character Generator, Upper Case, 12X8, Vertical Scan (2 chips)
ASCII Character Generator with EBCDIC and BAUDOT code translations, Upper Case, 7X9, Vertical Scan
ASCII Character Generator, UpperCase, 7X9, Horizontal Scan
Katakana Character Generator, 7X9, Horizontal Scan

°To be announced
NOTES
1. Output circuit:
TS ; Tri-state
00 ; Open drain
Bo ; Bare drain
PO; Pull down
PP ; Push-pull
2. Temperature range:
C; Commercial (0' C to +75· C)
M ; Military (-55' C to +125' C)

18

s~nDtics

MOS MEMORY SELECTION GUIDE

:

DEVICE

OUTPUT
ORGANIZATION CIRCUIT'

SHIFT REGISTERS
Static
2518
32X6
2519
40X6
50X2
2509
2532
80X4
100X2
2510
128X2
2521
2522
132X2
2511
200X2
2527
240X2
250X2
2528
256X2
2529
1024X1
2533
Dynamic
2506
2507
2517
2505
2524
2502
2503
2504
2512
2525

100X2
100X2
100X2
512X1
512X1
256X4
512X2
1024X1
1024X 1
1024X1

TEMPERATURE
ON CHIP
RECIRCULATE
RANGf2
PACKAGE

(Cont'd)

NO. OF

NO. OF

PINS

CLOCKS

TYPICAL CLOCK/CE/TTL
SPEED COMPATABILITY
(MHzj

POWER
SUPPLIES (VI

PP
PP
PP

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Jumper

C
C
C
C
C
C
C
C
C
C
C
C

N
N
N, K
N
N, K
N
N
N, K
N
N
N
N

16
16
14/10
16
14/10
8
8
14/10
8
8
8
8

1
1
1
1
1
1
1
1
1
1
1
1

3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
2.5
2.5
3.0
2.0

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

+5, -12
+5, -12
+5, -5, -12
+5, -12
+5, -5,-12
+5, -12
+5, -12
+5, -5, -12
+5, -12
+5, -12
+5, -12
+5, -12

SD
7.5KPD
20KPD
SD
SD
SD
SD
SD
SD
SD

No
No
No
Yes
Yes
No
No
No
Yes
Yes

C
C
C
C
C
C
C
C
C
C

T, N
T, N
T, N
K
N
N
TA, N
TA,N
K
N

8
8
8
10
8
16
8
8
10
8

2
2
2
2
2
2
2
2
2
2

4.0
4.0
4.0
3.0
5.0
10.0
10.0
10.0
5.0
3.0

No
No
No
No
No
No
No
No
No
No

+5, -5
+5, -5
+5,-5
+5, -5
+5, -5
+5, -5
+5, -5
+5, -5
+5, -5
+5, -5

SD
SD
TS
PP
TS
PP
PP
TS

pp

*To be announced

NOTES
1. Output circuit:
TS = Tri-state
00 = Open drain
BO = Bare drain
PO = Pull down
PP = Push-pull
2. Temperature ran~:
C = Commercial (0 0 C to +75 0 C)
M =Military (-55 0 C to +125 0 C)

s~nDtics

19

20

s~nDtics

IIPOIAR mEmORY
DATA SPEClrlCATlons

9illDOtiC9

21

22

91!1DOtiC9

16 BIT ECL CAM (8X2)

10155
10155. F,N

DESCRIPTION

FEATURES

The 10155 is a 16-bit ECl Content Addressable Memory (CAM) organized as an array
of 8 words by 2 bits. Each cell of the array
consists of a D-type latch and an exclusiveOR comparator, along with control logic for
reading, writing and masking.

•
•
•
•
•
•

The modes of operation possible with the
10155 are associate, masked associate,
read, write, and hybrid. Lines YO-Y 7 are used
for linear word select in the read/write
mode, and are used as outputs for match/
mismatch information in the associate
mode.
In associate operation, 10 and 11contain information to be compared. If the latches at a
particular Y location are in a state matching
the input data, that Y line goes low.
The Y outputs are open emitters, allowing
expansion in multiples of 2 bits by tying
additional 10155's to the Y bus lines. To
inhibit comparison of a particular bit, the
corresponding Ao or A1 line is held low.
In the read mode, the state of the selected
cells appears on outputs Do and D1. In the
write mode, these outputs are transparent,
following the state of 10 and 11,
In Hybrid mode, one of the 10 or h data
inputs may be associated with the QnO or
Qn1 cells respectively. If a match exists, the
corresponding Yn line(s) will go low, and can
be used to address the other half of the
memory for writing new data. Thus, it is
possible to write i1 in Qn1 where 10 matches
QnO or vice versa.

BLOCK DIAGRAM

PIN CONFIGURATION

12ns associate time (max.)
linear address select
Single bit masking
50 0 output drive
ECl 10K compatible
Open emitter match lines for easy bit
expansion
• 50kO input puildown resistors (except
on Y lines)

F,N PACKAGE"

=

o

APPLICATION
• Content addressable memory systems

'F = Cerdip
N = Plastic

• VCC1 = VCC2 = OV
• V E~ = -S.2V ±5%

TRUTH TABLE (POSITIVE LOGIC)
MODE

AD A1

10

11

W Oil

01

Qilo

Qn1

Yn

Associate 1

1

1

1/0 1/0

X

0

0

QnO

Qn1

QnoEEl 10 + Qn1 EEl i1

Associate 1,2
(masked)

1

0

1/0

X

1

0

D1

QnO

Qn1

QnoEEllo

Associate1,2
(masked)

0

1

X

1/0

1

Do

0

QnO

Qn1

Qn1 EEl i1

Read3

0

0

X

X

1

D02 D12

QnO

filn1

Write3.4

0

0

1/0 1/0

0

o (Selected address)
o (Selected address)

HybridS

1

0

1/0 1/0

0

HybridS

0

1

1/0 1/0

0

10

11

0

i1
i1

QnO

11·Yn

QnoEEllo

11

0

10·Yn

Qn1

Qn1 EEl i1

10

X
Dont care
anO =: Contents of address n, Bit 0 (n =: 0 to 7)
an1 = Contents of address n, Bit 1
NOTES
1. 1 (high) =: Mismatch, 0 (low) = Match
2. Read mode: Do = 000 • Yo + 010 • Y1 + •••

01

=

001 •

+ 070 • Y7
Yo + 011 • Vi" ••• + Q71 • y:,

3. In normal operation a Single Y address is selected for read or write
4. Write is transparent
5. Simultaneous Associate and Write at all "Match" addresses.

LOGIC DIAGRAM (TYPICAL BIT)

Y,

16-BIT LATCH
AND COMPARATOR
ARRAY

Y,

17)

161

(12)

E
w
E

RECOMMENDED
OPERATING VOLTAGES

(13)

Gi!lDotiCG

10155

16. BIT ECL CUM (8X2)

10155. F,N

ABSOLUTE MAXIMUM RATINGS

VCC1 = VCC2 =

PARAMETER

VEE
VIN
10
TA
TJ
TSTG

Supply voltage
Input voltage
Output source current
Temperature Range
Operating
Operating junction
Storage

ov

RATING

UNIT

-8
o to VEE
40

Vdc
Vdc
mAdc
°C

-30 to +85
125
-55 to +125

DC ELECTRICAL CHARACTERISTICS.1 VCC1 = VCC2 = OV, VEE = -5.2V, RL = 50n to -2V
PARAMETER

CONDITIONS

VIL
VIH
VILA
VIHA

Input voltage
Low
High
Low threshold
High threshold

VOL
VOH

Output voltage
Low
High

VOLA
VOHA

Low threshold
High threshold

IlL
IIH

Input current
Low
High

lEE

Supply current

-30°C

TEST

+25 °C

+85°C
UNIT

Min

Typ

Max

Min

Typ

Max

Typ

Min

Max

V
-1.850

-1.890

-1.825

-0.890
-1.500

-0.810
-1.475

-0.700
,..1.440

-1.205

-1.105

-1.035

VIH = Max, VIL = Min

-1.89
-1.06

-1.675 -1.65 -1.70
-0.89 -0.96 -0.89

-1.85 -1.825
-0.81 '-0.89

-1.615
-0.70

-1.655

-1.63

-1.595

VIHA = Min, VILA = Max

-1.08

V

-0.98

Y,A,I,W = VIL Min
A = VIH Max
I,W= VIH Max
Y= VIH Max

-0.91

J.iA

0.5
220
200
50
115

VIH Max

140

mA

AC ELECTRICAL CHARACTERISTICS2 -30°C:5 TA:5 +85°C, VCC1 = VCC2 = +2V, VEE = -3.2V, RL = 50n to ground
PARAMETER

LIMITS
FROM

TO

TEST CONDITIONS

Min3

UNIT

Typ4

Max

ns

Associate time
TAl
TA2

It
A+

Yt
Y+

8
9

12
12

AA+
Y+

YDD-

8
4
9

12
7
13

W+
AW+
Y+
W+
It

A+
YYt
wIt
w+

Disable time
T01
T02
T03
TH1
TS2
TH2
TS3
TH3
TS4

Setup and hold time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time

Tw

Write pulse width

TA3
TA4
TA5
TA6
NOTES
1.

Access time
Write
Write
Read
Read

ns

ns
0
11
1
2
1
3

10

5

ns
ns

w1+,YA-

Dt
D+,D+
D+

Each Eel 10K series device has been designed to meet 'the de and ae specifications after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board
and transverse air flow greater, than 500 linear fpm is maintained.

24

1
15
3
3
3
5

Si!jOotiCS

TS4~Tw

13
9
6
4

2. Refer to de characteristics.
3. Minimum allowed.
4. All typical values are at TA = +250 C.

17
13
10

IE 811

f'

CAM

fe' "
10155. F,N

VOLTAGE WAVEFORMS
READ CYCLE

A

MOOE SELECT

Y

SELECTEDY
(ONE LINE)

Y

UNSELECTED Y
(7 LINES)

D

DATA OUT

=
o
e
w

E

WRITE CYCLE

•c:

MODe SELECT

-"

o
&.

SELECTED Y
(ONE LINE)

-

UNSELECTED Y
"""'0IIIl1.IIW0IIIl1.IIW_ (7 LINES)

II

WRITE PULSE

INPUT DATA

DATA OUT

ASSOCIATE CYCLE

MODE SELECT

Y OUTPUT

INPUT DATA

9!!1DOtiC9

25

16:-BIJ EeL CAM (8X2)
10155. F,N

MEASUREMENT CIRCUIT
ASSOCIATE TIME I TO Y (T A1)
PULSE
GENERATOR

+2.0V
SCOPE

_ _ _ _ _ 710

+1.2V

-*---"
JUMPER

A
JUMPER

50n
INPUTS

Ao

-3.2V

26

Gi!lDOliC9

82812 (0 C ) 82$'11 (I S )

32 BII BIPOLAR MULTIPORT MEMORY (814)

82S12-F,N .82S112-F,N

DESCRIPTION

FEATURES

Data is stored in a single storage matrix
which is addressed via 2 independent sets of
address inputs, designated respectively as
Port A and Port B.

•
•
•
•
•
•

Data can be read from memory via either
Port A or B, through their respective output
sets. However, input data (latched on the
leading edge of write enable in the input
data latches) is written only in memory
locations specified by the address on Port
A, regardless of Port B.

•
•
•
•
•
•

PIN CONFIGURATION

Address access time: 40ns max
Write cycle time: 65ns max
Power dissipation: 8.5mW/bit typ
Input loading: -250f.LA max
On-chip address decoding
Output options:
82S12 Open collector
82S112 Tri-state
Non-inverting outputs
Input data latches
Two write enable lines
Separate output enable lines
Output follows data Input during write
TTL compatible

When both Port addresses are equal, data
from the same location can be read in either
or both Port output sets by means.of output
select lines SA and Sa. During Write, new'
data stored in memory is immediately transAPPLICATIONS
ferred on both Port output sets.
• Buffer memory
When both Port addresses are different, 2 • Accumulator register
• Data routing/shifting
different locations can be simultaneously
• ALU control
read from memory. It is also possible to
• Multiprocessor memory management
simultaneously read through Port B while
writing new input data through Port A by • Bandwidth increase by multi-operand
fetch
utilizing the "AN" address to specify the
location of the word to be written, and the • Communication controllers
• I/O data packing/unpacking
"BN" address to specify the word to be read.
• Large FIFO memories
Both devices are ideally suited for high
speed accumulator and buffer memories,
and can be readi Iy expanded to form larger
arrays by means of their output select and
write enable lines.

F,N PACKAGE"

~

a,

0
E
W
E

a,

Sa
04 a
03A

03a

GND

01a

02a

-=

CI
..,

'F = Cerdip
N = Plastic

...-.
0

Both the 82S12 and 82S112 are available
overthe limited temperature range of+10°C
to +75°C. Over this temperature range,
specify N82S12/82S112F,N.

TRUTH TABLE
PORT
MODE

W~

WE

IN

Disabled

X

or
Read

X

Write

1

1

0

SB

1

1

0

X

0

SA

1/0

ADDRESS (ON)A (ON)B (ON)A (ON)B

X

0

0

0

0
1
0

1
0
0

1
0
1
0

1
1
0
0

1
0
1
0

1
1
0
0

1
Stored
Data

1

1

82S112

82S12

A=B

A;I'B

A=B

A;I'B

1

Hi-Z

Hi-Z

1

Stored
Data

Hi-Z

Stored
Stored
Hi-Z
1
Data
Data
Stored Stored Stored Stored
Data Dafa
Data
Data
Hi-Z
1
[AN]
[AN]
Hi-Z
1
[BN]
[BN]
[BN]
[AN]
[AN]
[BN]
Hi-Z
1
1
Hi-Z
Hi-Z
1
IN
IN
Hi-Z
IN
1
IN
IN
IN
IN
IN
1
IN
1
IN

1
1
[BN]
[BN]

Hi-Z
IN
Hi-Z
IN

Hi-Z
Hi-Z
[BN]
[BN]

x=

Don't care
[ J = Contents of

Smnotics

27

82S12-F,N .82S112-F,N

BLOCK DIAGRAM

I,

I,

I,

WE r.-.-.----..,.
WE~c-L.._

,,/~

(READ/WRITE)
ADDRESS
(READIWRITE)

/

/

(4)

/

.. AII

/

s,

/

s,

8 WORD X 4-BIT ]
STORAGE MATRIX

[

A,

;-

A,
./

B,

/

/

/

/

/

//

01A

(READ ONLY)

02A

03A

04A

018

028

03A

048

ABSOLUTE MAXIMUM RATINGS
PARAMETERl

Vee
V,N
VOH
Va
liN
lOUT
TA
TSTG

28

Supply voltage
Input voltage
Output voltage
High (82S12)
Off-state (82S112)
Input current
Output current
Temperature range
Operating
Storage

RATING

UNIT

+7
+5.5

Vdc
Vdc
Vdc

+5.5
+5.5
±30
+100

rnA
rnA

o to +75
.,.65 to +150

SfgOObBIi

·C

82S12-F,N .82S112-F,N

DC ELECTRICAL CHARACTERISTICS +10°C:::; TA:::; 75°C, 4.75V:::; Vee:::; 5.25V
82S12
PARAMETER1

VIH
VIL
Vie

Input voltage
High1
Low 1
Clamp1.3

VOH
VOL

Output vollage
High 1,4
Low1.5

IIH
IlL

Input current
High
Low

10LK
10(OFF)

Output current
Leakage 6
Hi-Z state6

los

Short circuit3.7

TEST CONDITIONS

Min

Typ2

82S112
Max

Min

Typ2

Max

UNIT
V

Vee = 5.25V
Vee = 4.75V
Vee = 4.75V, liN = -18mA

2

2
-0.8

Vee = 4.75V
iOH = -2mA
IOL = 9.6mA

0.85
-1.2

0.85
-1.2

-0.8

V
2.4
0.35

0.45

0.35

0.45

p.A
VIN = 5.5V
VIN = 0.45V
Vee = 5.25V
VOUT = 5.25V
VOUT = 5.25V
VOUT = 0.45V
VOUT = OV

1
-10

25
-250

1

40

1
-10

25
-250

1
-1

40
-40
-70

rnA

110

160

rnA

-20

lee

Vee supply currentS

Vee = 5.25V

110

CIN
VOUT

Capacitance
Input
Output

Vee = 5.0V
VIN = 2.0V
VOUT = 2.0V

5
8

160

p.A
p.A

pF
5
8

AC ELECTRICAL CHARACTERISTICS +10°C:::;TA:::;+75°C,4.75V:::;Vee:::;5.25V, R1 =4700, R2=1kO, CL=30pF
LIMITS
PARAMETER

TAA
TSE
TSD
TWD
TWSA
TWHA

Access time
Address
Port select
Disable time
Port deselect
Valid time
Setup and hold time
Setup time
Hold time

TWSD
TWHD

Setup time
Hold time

Twp

Pulse width
Write enable

TO

FROM

Output
Output

Address
Output enable

40
30

Output
Output

Output enable
Write enable

30
40

Write enable

Address

15
5

Write enable

Data in

15
10

Min

Typ2

Max

UNIT
ns

ns
ns
ns

10
0

ns
45

NOTES
1.
2.
3.
4.
5.
6.
7.
S.

All voltage values are with respect to network ground terminal.
All typical values are at Vee ~ 5V. TA ~ 25'e.
Test one at the time.
Measured with V,L applied to
and a logic high stored.
Measured wit~ a logic low stored. Output sink current is supplied through a resistor to Vee.
Measured with V,H applied to
Duration of short circuit should not exceed 1 second.
Icc is measured with all inputs at 4.5V and the outputs open.

Sx

Sx.

91!)DotiC9

29

=
o
E
w
E

...o
e.
•lie

C

32 BII BIPOLAR MULTIPQRT MEMORY (8X4)

82S12 (0 C ) 82S1I2 (I S )
82S12-F,N • 82S112-F,N

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM
LOADING CONDITION

INPUT PULSES

ALL INPUT PULSES

6n.

+3.0V~0%
190%

OV - - _

-

-6nl

-...

_5nl

'5Y

R,
OUT

Measurements: AI' circuit delays are measured at the
+1.5V level of inputs and output.
R,

CL
(CAPACITANCE INCLUDING
SCOPE AND JIG)

'0----;$.
GNO

TIMING DIAGRAMS
READ CYCLE
~~-----------------------------------------'3Y
AN~8N~~·5_Y_________________________________________

W

, . - - - - - - - - - '3Y

+1.SV

Port Adaress: AN = BN

AN~_·5Y_______________________________
8N~_·5Y____________________________________________

+3V

OY
+3Y
oV

+3Y

YOH
1.SY

YOH
1.5V

Port Address: AN ¥ BN

30

Si!lDotiCS

82S12 (0 G) 828112 (l 8 )

22l2JHI BIPOEARZMI1ETIPORT MEMORY (8X4)

82S12-F,N .82S112-F,N

TIMING DIAGRAMS

MEMORY TIMING
DEFINITIONS

(Cont'd)

SIMULTANEOUS READ/WRITE CYCLE

TSE

~-------------------------------------~:~

::~=======================~:

TSD

- - - +3V

.N--_t----

'---------~-------oV

~---_t--------~--~,

,..--~I_----- '3V

TWHD

WE:::::~::::::::::::~~~~~~~~~~t;.~~~::~:::OV
-----+3V

'--------------------------OV
,J>o. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

VOL

----------+3V

Twp
TWSA

TWSD

TWD

'-------------------------------------OV
"1"

-----------------V~

... VOL

~--------------~--------

TWHA

Delay between beginning of Output Enable low (with Address
valid) and when Data Output
becomes valid.
Delay between when Output Enable becomes high and Data
Output is in Hi-Z or high state.
Delay between beginning of valid
Address (with Output Enable low)
and when Data Output becomes
valid.
Required delay between end of
Write Enable pulse and end of
valid Input Data.
Width of Write Enable pulse.
Required delay between beginning of valid Address and beginning of Write Enable pulse .
Required delay between beginning of valid Data Input and end of
Write Enable pulse.
Delay between beginning of Write
Enabie pulse and when Data
Output reflects the Data Input.
Required delay between end of
Write Enable pulse and end of
valid Address.

Port Address: AN "" BN
AN = Write
BN == Read

PORT A WRITE CYCLE

AN"BN~_·5V___________________________________'.5~:~
"1"

---+3V

'------------+-----OV

·N----_t-------'

~ -----I-------...!:~~~r;::!;~=::!......:...::::...

WE _____t--------------,
- - - - - - - - - - - - - - - - - - - - - -.......-

·3V

'-----+---- ov
----- -

-

- - -_ -

_ _ _ +3V

'-------------~~~-----OV
IN'" "0"

;/~'/"~~f<~--.....;:.....:...-----

VOL

Port Address: AN = BN

Si!lDntms

31

I;

o
E
w
E

..:

a:
~

oc.

-

II

64 BIT BIPOLAR SCRATCH pnD

82S25 (0 C) nOlA (0 C )
54 14589 (O.C) 54 745189 (r 5 )

MEMORY (16X4)

82S25-F,N • 3101A-F,N • 54174S89-F,N .54/74S189-F,N

DESCRIPTION

APPLICATIONS

This family of Read/Write Random Access
Memories is ideal for usein scratch pad and
high-speed buffer memory applications.

•
•
•
•

These products are fully decoded memory
arrays with separate input and output lines.
They feature pnp inputs and 1 chip enable
line for ease of memory expansion.

PIN CONFIGURATION

5cratch pad memory
Bulfer memory
Push down stacks
Control store

F,N PACKAGE

During Write, the outputs of each product
assume a logic state by the output access
time and the truth table.
The family is available in the commercial
and military temperature ranges. For the
commercial temperature range (O°C to
+75° C) specify the N prefix, and forthe military temperature range (-55°C to +125°C)
specify the S prefix. The 54174S89/189 military temperature range product is ordered
as S54S89/189. The S grade product is
supplied in the F package only.

'F = Cerdip
N = Plastic

TRUTH TABLE

FEATURES
• Output access time:
N82S25: 50ns
N3101A: 35ns
N54174S89: 50ns
N54/745189: 35ns
• Power dissipation: 6.25mW/bit, typ
• Input loading:
N grade: -100",A max
5 grade: -150",A max
• On-chip address decoding
• Output options:
82525: Open collector
3101A: Open collector
54/74589: Open collector
54/745189: Tri-state
• 5chottky processed
• TTL compatible

82525

-CE

-WE

DIN

Read

0

1

X

Write "0"
Write "1"
Disable

0
0

0
0
X

0

1

54/748189

DATA OUT
Stored
data
1
1
1

1
X

54/74889

3101A

Stored
data
1
1
1

Stored
data
Hi-Z
Hi-Z
Hi-Z

Stored
data
1

0
1

BLOCK DIAGRAM

ADDRESS
DECODING

Ao ___
(1)

_ ___
(2)
ce

CHiP ENABLE

1-;t===t;~==:::1~;:t==:::1;-;:t~
READ/WRITE

(3)

WE---+BIT 1

«)t
vcc =

(16)

= 181
( ) = Pin number

GND

32

SrnDotiCS

ILl

BIT3

81T2

(5)

I
DATA IN AND OUT

81T4

82825-F,N • 3101A-F,N • 54174889-F,N .54/748189-F,N

ABSOLUTE MAXIMUM RATINGS
PARAMETER1

RATING

UNIT

Vee

8upply voltage

+7

Vdc

VIN

Input voltage

+5.5

Vdc

VOH

Output voltage
High

+5.5

TA

TSTG

Vdc

Temperature range
Operating
N grade
8 grade
Storage

=
E

°C

o to +75
-55 to +125
-65 to +150

C
I'W

E
DC ELECTRICAL CHARACTERISTICS

N grade: O°C S TA S +75°C, 4.75V S Vee S 5.25V
8 grade: 55°C S TA S +125°C, 4.5V S Vee SS.5V

II

N GRADE
PARAMETER

TEST CONDITIONS

Vil
VIH
Vie

Input voltage
Low
High
Clamp

Vee = Min
Vee = Max
liN = -12mA, Vee = Min

VOL
VOH

Output voltage
Low3,4
High (541748189)

lOUT = 16mA, Vee = Min
lOUT = 2mA

hl
hH

Input current
Low
High

IOlK
los
10(OFF)

Output current
Leakage
8hort circuit (541748189)
Hi-Z (541748189)

lee

8upply current4

Max

Min

Typ2

Max

UNIT

.80

.85
2.0

2.0
-1.0

-1.5

-1.0

-1.5

0.35

0.45

0.35

0.5

-10

-150
25

<1

100
-100
±50

80
80
80

120
120
110

V
2.4

2.4
p.A

VIN = 0.45V
VIN = 5.5V

-.10

-100
10

CE = high, VOUT =5.5V, Vee = Min
VOUT = OV
2.4 2: VOUT 2: O.4V

<1
-30

100
-100
±50

80
80
80

105
105
110

-30

"
p.A
mA
p.A
mA

3101A
541748189

Capacitance
Input
Output

Typ2

V

82825,54174889

CIN
COUT

Min

S GRADE

Vee = 5.0V
VIH = 2.0V
VOUT = 2.0V, CE = high

SmootiCS

pF
5
8

5
8

33

G
1IIIIIIII

C

•e.

82525(0 C ) 3101A (0 C )
54 14589 (0 C ) 54 14S189 (r 5 )

64 BIT BIPOLAR SCRATCH PAD
MEMORY (1614)

82S25-F,N • 3101A-F,N • 54/74S89-F,N .54174S189-F,N

AC ELECTRICAL CHARACTERISTICS

R1 = 270n, R2 = 600n, CL = 30pF, See ac test load
N grade: O°C:5 TA:5 +75°C, 4.75V:5 VCc:5 5.25V
S grade: -55°C:5 TA:5 +125°C, 4.5V:5 Vcc:5 5.5V

PARAMETER

TO

Min
TAA
TCE

Access time
Address
Chip enable

TCD

Disable time

Output

Two

Response time

Output

TWR

Write recovery time

Setup and hold time
Setup time
TWSA
Hold time
TWHA

N3101A,
N745189

582525,
554589

N82525,
N74589

FROM

Typ2 Max

Min

Typ2

Max

Min Typ2

53101A,
5545189
Max

Min

ns

Chip
enable
Write
enable

35
20

50
35

35
20

60
35

25
12

35
17

25
12

50
25

20

35

20

35

12

17

12

25

ns

20

25

20

30

15

25

15

30

ns

35

50

35

60

22

35

22

40

ns
ns

Write
enable

Address

5
5

-8
0

10
10

-8
0

0
0

0
10

TWSD
TWHD

Setup time
Hold time

Write
enable

Data in

30
5

15
-3

30
10

15
-3

25
0

30
10

Twsc
TWHC

Setup time
Hold time

Write
enable

CE

0
5

-5
0

0
5

-5
0

0
0

0
0

30

18

30

18

25

30

Twp

UNIT

Typ2 Max

Pulse width
Write enableS

ns

1

NOTES
1. AU voltage measurements are referenced to the ground terminal. Terminals not specifically
anced are left electrically open.
2. Typical values are at Vee = +5.0V and TA = +25°C.
3. Output sink current is supplied through a resistor to Vee.
4. All sense outputs in low state.
5. To guarantee a Write into the slowest bit.
6. Positive current is defined as into the terminal referenced.
7. Positive logic definition: high == +5.DV, low = GND.

refer~

8. Test each input one at a time.

VOLTAGE WAVEFORM

TEST LOAD CIRCUIT
LOADING CONDITION

INPUT PUL5E5
ALL INPUT PULSES
+3.0V - - - - " . . - - - - - " ' "

ov
+3.0V

+S.OV

r!i.
""'-<>---..... ce
GND

IINCLUDES JIG ANO SCOPE CAPACITANCE)

34

SmDntics

Measurements: All circuit delays are measured at the
+1.5V level of inputs and output.

82S25-F,N • 3101A-F,N • 54174S89-F,N .54/74S189-F,N

TIMING DIAGRAMS
READ CYCLE

....

ADDRESS,

WRITE CYCLE

+.

1.SY

OV

"0" STORED
ON

-

*,.5V

VOL

TAA'~

Address Access Time

HIP.
~
ENABLE

YOH.

"1" STORED

::t' 1.SY

1.SV

...

3V

--

OV

TCE~
TC0:f,7v----.;;.:...=
------VOH
ON

~V

_

1.5V VOL

Chip Enable/Disable Times

Si!JDDliCS

35

82521 (0 C )

64 IUT BIPOLAR WRITE WIIILE READ RAM (3212)

82S21-F,N

DESCRIPTION

APPLICATIONS

The 82S21 is ideally suited for high speed
buffers and as the memory element in high
speed accumulators.

•
•
•
•

Words are selected through a 5-input decoder when the chip enable input, CE is at
logic high. WSo and WS1 are the write select
inputs for the bit 0 and bit 1 of the word
selected. WE is the write control input.
When WSN and WE are both at logic low
data on the Dloand.Dh data lines are written
into the addressed !Nord. The read function
is enabled when eitherWSNorWE isat logic
high.
An internal latch provides the Write-WhileRead capability. \~'nen the latch control line
(strobe) is logic high and data is being read
from the 82S21, the latch is effectively
bypassed. The data at the output will bethat
of the addressed word. When strobe goes
from a logic high to logic low, the outputs
are latched and will remain latched regardless of the state of any other address or
control line. When strobe goes from low to
high, the outputs unlatch and will assume
the contents of the present address word.

TRUTH TABLE
CE WE WSO WS1 STROBE

(

MODE

OUTPUTS

1
0

X
X
X
1

X
X
X
1

0
0
1 or j
1 or I

1

0

0

0

0

Write data

1
1

0

0

0

0

0
1

1
X

Write data
Write data into bit 0 only

1

0

1

0

X

Write data into bit 1 only

X
0
1
1

X
X

Output hold
DON = (AM) at last CE = high
DON = high
Disabled
Read (transparent/latched)
DON = (AM)
Read (transparent/latched)
DON = (AM) at last strobe =

= High -

low transition

ABSOLUTE MAXIMUM RATINGS
PARAMETER1

TA
TSTG

Supply voltage
Input voltage
Output voltage
Input cu rrent
Output current
Temperature range
Operating
Storage

S!!)DotiCS

j

DON =DIN
If strobe = low:
DON = (AM) at last strobe = I
If strobe = high:
DON = DIN or (AM) as perWSN

) = Contents of
j

Vee
VIN
VOH
liN
lOUT

36

F,N PACKAGE

*F :::;; Cerdip
N = Plastic

FEATURES
• Address access time: SOns max
• Write cycle time:
Transparent mode: 45ns max
Latched mode: 60ns max
• Power dissipation: 7.5mW/bit typ
• 32mA output sink capability
• On-chip output latches
• Bit masking control lines
• Write-While-Read function
• Non-inverting open collector outputs
• TTL compatible

PIN CONFIGURATION

Scratch pad memory
Buffer memory
Accumulator register
Control store

RATING

UNIT

+7
+5.5
+5.5
±30
+100

Vdc
Vdc
Vdc
mA
mA
°C

o to +75
-65 to +150

82S21-F.N

LOGIC DIAGRAM

(13) Ao

(12) A,

(11) A2

(10) A3

(4) A,

Lt»-

=
E

Lt»Lt»- .

E

C

4>=

•

II
G
.-

4>=

..•-

C

(5) CE

(6) STROBE

Vee
GND

=

=
( ) =

(16)
(8)
Pin number

DC ELECTRICAL CHARACTERISTICS

O°C:S; TA :S;75°C. 4.75V:S; Vee:S; 5.25V

LIMITS
PARAMETER1

TEST CONDITIONS

Vil
VIH
Vie

Input voltage
Low1
High1
Clampl.3

Vee = 4.75V
Vee =5.25V
Vee = 4.75V. liN = -18mA

VOL

Output voltage
Low1,4

Vee

III
IIH

Input current
Low
High

IOlK

Min

Typ2

UNIT
Max
V
0.85

2
-0.8

-1.2

0.35

0.45

VIN = 0.45V
VIN = 5.5V

<1

-1.6
25

Output current
LeakageS

Vee = 5.25V
VOUT = 5.25V

1

40

lee

Vee supply current6

Vee

100

130

CIN
COUT

Capacitance
Input
Output

Vee = 5.0V
VIN = 2.0V
VOUT = 2.0V

V
~

4.75V. IOl = 32mA

= 5.25V

S(gnotics

mA
p,A

p.A
mA
pF·
5
8

37

64 BII BIROEAR WRITE WHILE READ RAM (32X2)

82S21 (0 C )
82S21-F,N

AC ELECTRICAL CHARACTERISTICS
PARAMETER

O°C::; TA::; +75°C, 4.75V::; VCC ::;5.25V, R1 = 1500, R2 = 6000, CL =30pF

TO

LIMITS

TEST CONDITIONS

FROM

Min

Max

ns

TAA
TCE

Access time
Address
Chip enable

Output
Output

Address
Chip enable

Latched or transparent read

40
40

50
50

Tco

Disable time
Chip enable

Output

Chip enable

Latched or transparent read

40

50

Setup and hold time
TWSA Setup time
TWHA Hold time

ns
ns
Write

Address

Latched or transparent write

15
5

10
0

Twso
TWHD

Setup time
Hold time

Write

Data in

Latched or transparent write

25
5

0

Twsc
TWHC

Setup time
Hold time

Write

CE

Latched or transparent write

15
5

10
0

TCES
TCEH

Setup time
Hold time

Strobe

Chip enable

Latched read

50
5

40
0

TADH

Hold time

Output

Address

Latched read

5

0
ns

Pulse width
Tsw Strobe
Twp Write inputs
Latch time
TSLR Read strobe
TSLW Write strobe
TLRW WWR strobe
TOL
TWD

Address
Write
Strobe

Delatch time
Strobe

Output

Strobe

TCD

TAA

Twsc

TWHC

TWSA

TWHA

TWSD

30
25

Latched read
Latched write
Write while read

50
40
10

Valid time

Output

Write

40
30
5
ns

MEMORY TIMING
DEFINITIONS
TCE

Latched read
Latched or transparent write

ns
Strobe
Strobe
Write

NOTES
1. All voltage values are with respect to network ground terminal.
2. All typical values are at Vee = 5V, TA = +25°C.
3. Test each input one at a time.
4. Measured with a logic low stored. Output sink current is supplied

38

UNIT

Typ2

Delay between beginning of Chip
Enable high (with Address valid)
and when Data Output becomes
valid.
Delay between when Chip Enable
becomes low and Data Output is
in high state.
Delay between beginning of valid
Address (with Chip Enable high)
and when Data Output becomes
valid.
Required delay between beginning of valid Chip Enable and
beginning of Write Enable pulse.
Required delay between end of
Write Enable pulse and end of
Chip Enable.
Required delay between beginning of valid Address and beginning of Write Enable pulse.
Required delay between end of
Write Enable pulse and end of
valid Address.
Required delay between begin-

TWHD

Twp
TWD

TCES

TCEH

TSLR

Tsw

TADH

Latched read

20

25

Latched or transparent write

30

40

ns

through a resistor to Vee.
5. Measured with Vil applied to CE, and VIH to strobe.
6. Icc is measured with all inputs at 4.5V, and the outputs open.

ning of valid Data Inputand end of
Write Enable pulse.
Required delay between end of
Write Enable pulse and end of
valid Input Data.
Width of Write Enable pulse.
Delay between beginning of Write
Enable pulse and when Data
Output reflects the contents of the
Data Input.
Minimum delay between leading
edge of Chip Enable and trailing
edge of Strobe, for latching valid
output data.
Required delay between trailing
edge of Strobe and end of Chip
Enable, for latching valid output
data.
Minimum delay between Address
valid time and trailing edge of
Strobe, for latching valid output
data.
Minimum width of Strobe pulse
req u i red to update contents of
output data latches.
Required delay between trailing
edge of Strobe and end of val id

Si!)notiCs

TDL

TSLW

Address.
Delay between leading edge of
Strobe and when output data
latches are released.
Minimum delay required between
trailing edge of Strobe and leading edges of Write Enable or Write
Select for latching old output data
(being read) while new data is
being written (at the same address),
Minimum delay between leading
edge of Write Enable or Write
Select and trailing edge of Strobe
for latching data being written in
output data latches.

82S21-F,N

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM
INPUT PULSES

=
o

QY----'I
+5.0V

1K

~

-t3.0V---,""

E
w

DO,
OUT

Measurements: All circuit delays are measured at the
+1.SV level of input§ and outputs.

DO,
(INCLUDES JIG &
SCOPE CAPACITANCE)

'o----\5TR08E

GNO

TIMING DIAGRAMS
TRANSPARENT READ

STROBE

,.~------------------------------------------------+3V
I
_J__ - - - - - _____ ~ ______ .-----'--- ov
,.--------------------------------------------~+3V

ADD

------- +3V

'---------------------------------------------___ OV
r------------------~1.SV

1.5Y

-'11"--"""";'1---

CE _ _--1_ _ _ _

I-TCE---i

OV

. i--TCO-l

------~--~------~~~~~"'I,.-------'~'l-"------~r_-----VOH
1.5Y
1.SY
" -_______";;,0'_'_ _ _ _ _ _ _ _ _ VOL
~--------TAA--------~

Output Latches Not Used

S(gDDtiCS

39

E

82S21-F,N

TIMING DIAGRAMS

(Cont'd)
LATCHED READ
_-----.3V

1.SV

1.SV

~----------------------____-JI~________

ADD

,-----------"""'\--1------1M

1

1SV

1-.1

.: ".--:-I---~---

1

CE _ _ _

I-----IEE

GNO

Measurements: All circuit delays are measured at the +1.SV level of inputs and output.

62

SmDotiCS

6Ma

93415A-F,N .93425A-F,N

TIMING DIAGRAMS

MEMORY TIMING DEFINITIONS
TWR

READ CYCLE
ADDRESS

+3

\/
Jt..'5V

OV
~"'~"~S~TO~R~ED~-------VOH

DOUT

t" t :
CHIP ENABLE

DOUT

\/,.5V

_4-____-J/~~"O~"~ST~O~R~ED~_______
'"

i-- TAA _

TCE-j _ _ _ _ _ _

VOL

TCE

~:.D_=i_-r VOH

\'5V

,5VI

TCD

VOL

TAA
Chip Enable/Disable Times

Address Access Time

Twsc
WRITE CYCLE

,------------+3
ADDRESS

1-----

TWHD

~------------'ov
TWSD - - - -......

,------------+3
1.5V

Twp
TWSA

'-----------ov
~--------+3

CHIP ENABLE

Twso

1.BV

'-----__!---------__!------J'4----------- ov

,------------------+3

Two

WRITE ENABLE

"--------J'~----------~-------ov

. . . ...;..-----

r------

TWR\j

\

,

TWHC

DIN:"'"

,.5VO

_

SmOOliCS

VOH

="0"
IN

VOL

TWHA

Delay between end of Write Enable pulse and when Data Output
becomes valid. (Assuming Address still valid--not as shown.)
Delay between beginning of Chip
Enable low (with Address valid)
and when Data Output becomes
valid.
Delay between when Chip Enable
becomes high and Data Output is
in off state.
Delay between beginning of valid
Address (with Chip Enable low)
and when Data Output becomes
valid.
Required delay between beginning of valid Chip Enable and
beginning of Write Enable pulse.
Required delay between end of
Write Enable pulse and end of
valid Input Data.
Width of Write Enable pulse.
Required delay between beginning of valid Address an.d beginning of Write Enable pulse.
Required delay between beginning of valid Data Input and end of
Write Enable pulse.
Delay between beginning of Write
Enable pulse and when Data Output is in off state.
Required delay between end of
Write Enable pulse and end of
Chip Enable.
Required delay between end of
Write Enable pulse and end of
valid Address.

I;
0

E
W
E

-=

a:
~

0

-

&.
II

82S208-F .82S210-F,N

OBJECTIVE SPECIFICATION

DESCRIPTION
The 82S208 and 82S210 data inputs and
outputs are common (common I/O) with
separate output disable (00) line that allows
ease of read/write operlitions using a common bus.
The address inputs have a latch feature
controlled bya latch control pin (D. In the
Transparent mode, the L pin is held high
and the read or write location is accessed
directly from the address inputs. In th~
Latched mode, a negative transition on the L
line causes the present address state to be

held in the address latches, independent of
any other control signals. A positive pulse
on the [ line will cause a new address state
to be strobed into the latches.

PIN CONFIGURATION
82S208
F PACKAGE"

FEATURES

Vee

• Access time:
Address: 60ns max
Strobe: 70ns max
• On-chip address latches
• Tri-state outputs
• Schottky clamped TTL

..
A,

A,
A.
A,
0,

A,

TRUTH TABLE

A"

MODE

Disable output
Disable RIW
Write
Read
Transparent address
Hold address

WE

CE

00

[

ON
IN/OUT

X
X
0
1
X
X

X
1
0
0
X
X

1
X
1
0
X
X

X
X
X
X
1
0

High Z
High Z
Data in
Data out

-

WE

[

Co

82S210
F,N PACKAGE"

D.

x = Don't care

0,
D.

BLOCK DIAGRAM

0,
D.

+

A"
A,

.

..
A,

A,

0,

A,

+

0,

A,

0,

...

MEMORY CELL MATRIX

00

32X72::: 2304

10

Ai

0,

A,.
BUFF.

..

_72

32

ADOR.

vee

10F
32

i:
Ne

WITH
LATCH

GND

Co

A,
A,_

OF = Cerdip
N"'" Plastic

A,_

w _r--------~~w~.e~E~.r~------------------------~~
CONTROL
LOGIC

v

OE

00_

ABSOLUTE MAXIMUM RATINGS
PARAMETER

Vee
VIN
Vo
TA
TSTG

64

Supply voltage
Input voltage
Off-state output voltage
Temperature range
Operating
Storage

TYPICAL I/O STRUCTURE

RATING

UNIT

+7
+5.5
+5.5

Vdc
Vdc
Vdc
°C

o to +75
-65 to +150
9i!1nl!tic~

OBJECTIVE SPECIFICATION

82S208-F .82S210-F,N

DC ELECTRICAL CHARACTERISTICS O·C:5 TA +75·C, 4.75V:5 Vee 5.25V1
LlMITS2
PARAMETER

VIL
VIH
Vie

Input voltage
Low
High
Clamp4

VOL
VOH

Output voltage
Low
High

ilL
IIH

Input current
Low
High

IO(OFF)

Output current
Hi-Z state
Short circuit4.5

los
Icc

Supply current

CIN
COUT

Capacitance
Input
Output

TEST CONDITIONS

Min

. Typ3

Max

UNIT

V
.85

=
o

2.0
-0.8

liN = -18mA
CE = Low, 00 = Low
lOUT =9.6mA
lOUT =-2mA,
High stored

-1.2
V
0.5

2.4

3.3

Ii
w

p.A
VIN = 0.45V
VIN + 5.5V

-100
25

CE = Low, 00 = High, VOUT = 5.5V
CE = High, VOUT = 0.5V
VOUT = OV

40
-100
-70

mA

185

mA

-20
135

Vee = 5.0V
VIN = 2.0V
VOUT = 2.0V, CE = High, 00 = High

E

p.A

pF
5
8

AC ELECTRICAL CHARACTERISTICS O·C:5 TA:5 70·C, 4.75V::; Vee:5 5.25V
PARAMETER

TO

FROM

LIMITS
Min

Typ

UNIT
Max

TAA
TAL

Access time
Address
Strobe

Output
Output

Address
Latch

60
70

ns

TOE
TCE

Enable time
Output
Output

Output
Output

00
Chip enable

35
35

Too
Tco

Disable time
Output
Output

Output
Output

00

35

TWL
Tw

Pulse width
Strobe
Write

TSL
THL
TSSA

Setup and hold time
Setup time
Hold time
Setup time (strobe)

ns

ns
Chip enable
ns
20
40
ns
Latch
Address
Latch

Address
Latch
Address

5
10
0

Tse
THC

Setup time
Hold time

Write
Chip enable

. Chip enable
Write

5

Tso
THO

Setup time
Hold time

Write
Data

Data
Write

35
10

TSA
THA

Setup time
Hold time

Write
Address

Address
Write

10

TSLW
THLW

Setup time
Hold time

Write
Latch

Latch·
Write

15
10

TS01

Setup time (from
disabled state)
Setup time (from
enabled state)
Hold time

Chip enable

00

5

Data in

00

35

00

Chip enable

5

TS02
THO
NOTES on following page.

SjgDOliDS

65

.:

...o
a:

...-.

OBJECTIVE SPECIFICATION

82S208-F .82S210-F,N

NOTES
1. The operating ambient temperature ranges are guaranteed with transverse air flow
exceeding 400 linear feet per minute and a 2~minute warmup.
All voltages are with respect to network ground terminal.
All typical values are at Vee '= 5V, TA = 25°C.
Measured on one pin at a time.
Duration of los test should not exceed one second.

2.
3.
4.
5.

TIMING DIAGRAMS
ENABLE/DISABLE

READ MODE

________~X~~

~
1~
j.: TSL TTHL ==i=TSSA -!-=TWL::I

----1--""\

r-

(LATCHED)

'I
_DO..,U_T_ _ _ _ _ _ _ _ _...I*
,

-r::::::\ .

(LATCHED)

~TAL===I

TAA

lr---

WRITE MODE

----,*

lr----

1

-A

;========1
====*.~o, i'~1========
w--------,\
1

I-TSD

I-

THD-I

fr-~----

'---TW~--t'

1+1

I

~-I---~LA~c:;~--I-t ." .....

~TSLW-l

66

.

-I

!-THLW

9i!1nOliG9

OBJECTIVE SPECIFICATION

82S400/400A - I • 82S401/401A - I

PIN CONFIGURATION

DESCRIPTION

FEATURES

The 82S400 and 82S401, with typical access
time of 45ns, are ideal for cache buffer applications and for systems requiring very high
speed main memory. The 82S400A and
82S401A are devices selected for speed
compatibility with industry standard 1024bit RAMs having 45ns access time.

• Address access time:
82S400/401: 70ns max
82S400A/401A: 45ns max
• Write cycle time: 70ns max
• Power dissipation: 0.12mW/blt typ
• Input loading: -150J.LA max
• On-chip address decoding
• Output options:
82S400: Open collector
82S401: Trl-state
• Non-inverting output
• Blanked output during Write
• Fully TTL compatible

Both devices require a single +5V power
supply, feature very low current pnp input
structures, and include on-chip decoding
and a chip enable input for ease of memory
expansion. They feature either open collector or tri-state outputs for optimization of
word expansion in bused organizations.

I PACKAGE"

I;

o
*1

APPLICATIONS
•
•
•
•

High speed main frame
Cache memory
Buffer storage
Writable control store

E
w

= Ceramic

E
a:
,.,

TRUTH TABLE
CE

WE

DIN

82S400

82S401

Read

0

1

X

Stored
data

Stored
data

Write "0"
Write "1"

0
0

0
0

0
1

1
1

High-Z
High-Z

Disabled

1

X

X

1

High-Z

MODE

•

DOUT

oe.

.-.

x - Cont care

BLOCK DIAGRAM
01

An

An

A,

1:64

Ixl

A,

DECODER

A,
A•

... <>,-'-I._ _...J

DO

...
A,

An. An

A•

...

A"

ABSOLUTE MAXIMUM RATINGS
PARAMETER1

RATING

UNIT

Vee

Power supply voltage

+7

Vdc

V'N

Input voltage

+5.5

Vdc

VOH
Vo

Output voltage
High (825400)
Off-state (825401)

+5.5
+5.5

TA
TSTG

Temperature range
Operating
Storage

Si!lROliCS

Vdc

o to +75

°C

-65 to +150

67

4()9U 811 BIPOlAR RAM (4096XI)

82SiO() iOOA (0

e ) 81'S4() I

OBJECTIVE SPECIFICATION

40 IA (l SJ

82S400/400A - I • 82S401/401A - I

DC ELECTRICAL CHARACTERISTICS

O°C <
- TA <
- +75°C 4 75V <
- Vee <- 525V
LIMITS

PARAMETER

TEST CONDITIONS

Vil
VIH
Vie

Input voltage
Low1
High1
Clamp1.3

Vee = Min
Vee = Max
Vee = Min. liN = -12mA

VOL
VOH

Output voltage
Low1,4
High (82S401)1.5

Vee = Min
10l = 16mA
10H = -2mA

III
/IH

Input current
Low
High

10lK
10(OFF)

Output cu rrent
Leakage (82S400)6
Hi-Z state (82S401)6

los
lee

Typ2

Min

V
.85
2.0
-1.0

-1.5

0.35

0.45

VIN = 0.45V
VIN = 5.5V

-25
1

-150
25

Vee = Max
VOUT = 5.5V
VOUT = 5.5V
VOUT = 0.45V
VOUT = OV

1
1
-1

40
60
-60
-100

V
2.4
/J.A

Short circuit (82S401)7
Vee supply current8

-20

Vee =Max
0< TA < 25°C

Capacitance
Input
Output

Vee = 5.0V
VIN = 2.0V
VOUT = 2.0V

AC ELECTRICAL CHARACTERISTICS

0°

S;

mA

155
130
pF

4
7

TA S; +75°C, 4.75V s; Vee s; 5.25V, R1= 2700.,H2 = 6000., Cl = 30pF
N82S400A/401A

PARAMETER

iJ,A
iJ,A

mA
120
105

TA~25°C

CIN
COUT

UNIT

Max

TO

FROM

Output
Output

Address
Chip enable

Output
Output

Typ2

N82S400/401

Typ2

Max

45
30

45
30

70
45

Chip enable
Write enable

30
30

30
30

45
45

Output

Write enable

30

30

45

Write enable

Address

5

10

5

Min

Max

Min

Access time
TAA
TeE

ns

Disable time
Teo
Two
TWR

Recovery time

TWSA
TWHA

Setup and hold time
Setup time
Hold time

ns

Setup time
Hold time

Write enable

Data in

35
5

50
10

35
5

Twse
TWHe

Setup time
Hold time

Write enable

CE

5

10

5

35

50

35

ns

Pulse width9
Write enable

NOTES
1. All voltage values are with ,respect to network ground,termin'aL
2. All. typical values are at Vcc :::: 5V, TA 25° C.
3. Test each input one _ at a,time.
4. Measured with a logre, low stored. Output sink current is supplied through a resistor to Vee.
5. Measured with V,L applied to CE and a logic high stored.
6. Measured with V,H applied to CE.
7. Duration of the short circuit should not exceed 1 second.
8. Icc is measured with the write enable and memory enable inputs grounded, all other inputs-at 4.SV,
and the output open.
9. Minimum required to guarantee a Write into the slowest bit.
10. The operating ambient temperature ranges are guaranteed with transverse airflow exceeding 400 linear feet per minute and a 2-minutewarm-up. Typical thermal resistance values of the package at maximum temperature are:
0JA junction to ambient at 400fpm air flow - 50°C/watt
0JA junction to ambient - still air - 9O°C/watt
0JA junction to case - 20°C/watt

68

ns
ns

Twso
TWHO

Twp

UNIT

Smnl!tiCS

8;;!S4QU 4adA (0 C) 898401 401A (T

4096 BIT BIPOI AR RAM (40961 I)
OBJECTIVE SPECIFICATION

SF

82S400/400A - I • 82S401/401A - I

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM
INPUT PULSES

LOADING CONDITION

ALL INPUT PULSES

'3.0V--..,----~90~·O%

"I~
5n$

ov--:ll

5ns
~~

Vee

--to-

+3.0V~

~

ov------~-~-I
5ns
5ns

R,

-'It-

-.~

Dour

R2

Cl
(CAPACITANCE INCLUDING
SCOPE AND JIG)

Measurements: All circuit delays are measured at the
+1.5V level of inputs and output.

C-----Ic.

-

~-------.3

-l~'.5V

J!\'---_ _ _ _ _ _ OV

1.SV

ADDRESS

1------'--

~··,-··~ST~O~R~ED~----VOH

~------ov
TWSD - - - - - \ "1"

\V'5V
VOL

r------------+ 3
I

1.5V

'------OV

~TAA_

,-----.3

Address Access Time

CHIP ENABLE

1.SV

~----I-----~---~·~-----OV

~---------'3
WRITE ENABLE

~----J+------~----OV
T
W R \ ) ,-------VOH
D'N=3"1"
____
_

\

' ',.svo
_

= "0"

IN

VOL

Chip Enable/Disable Time

TIMING DEFINITIONS
TWR

TCE

TCD

TAA

Delay between end of Write Enable pulse and when Data Output
becomes valid (assuming Address still valid-not as shown).
Delay between beginning of Chip
Enable low (with Address valid)
and when Data Output becomes
valid.
Delay between when Chip Enable
becomes high and Data Output is
in off state.
Delay between beginning of valid

c:

II

WRITE CYCLE

READ CYCLE

STORED

E
a:

oe.

ADD;RE:.;;S.;;.S_ _ _ _ _ _ _ _ _ _ _ .3
\

-+___J/I\ "0'

E
w

~

GND

TIMING DIAGRAMS

DOUT

=:o

Twsc

TWHD

Twp
TWSA

Address (with Chip Enable low)
and when Data· Output becomes
valid.
Required delay between beginning of valid Chip Enable and
beginning of Write Enable pulse.
Required delay between end of
Write Enable pulse and end of
valid Input Data.
Width of Write Enable pulse.
Required delay between beginning of valid Address and beginning of Write Enable pulse.

smootiCS

Twso

Two

TWHC

TWHA

Required delay between beginning of valid Data Input and end of
Write Enable pulse.
Delay between beginning of Write
Enable pulse and when Data
Output is in off state.
Required delay between end of
Write Enable pulse and end of
Chip Enable.
Required delay between end of
Write Enable pulse and end of
valid Address.

69

828226-F,N • 828229-F,N

DESCRIPTION
The 828226 and 828229 include on-chip
decoding and 2 chip enable inputs for ease
of memory expansion. They feature either
open collector or tri-state outputs for optimization of word expansion in bused organizations.
Both 828226 and 828229 devices are available in the commercial and military temperature ranges. For the commercial temperature range (O°C to +75°C) specify
N828226/229, F or N, and for the military
temperature range (-55°C to +125°C specify 8828226/229, F only.

FEATURES
• Address access time:
N82S226/229: SOns max
S82S226/229 70ns max

• Power dissipation: 0.5mW/bit typ
• Input loading:
N82S226/229: -100!,A max
S82S226/229: -150!,A max
• On-chip address decoding
• Output options:
82S226: Open collector
82S229: Tri-state
• Fully compatible with Signetics
82S126/129 1024-bit PROMs
• Fully TTL compatible

•
•
•
•
•
•
•

Volume production
Sequential controllers
Microprogramming
Hardwired algorithms
Control store
Random logic
Code conversion

32X32

ABSOLUTE MAXIMUM RATINGS.

Y,N
VOH
Vo
TA

TSTG

70

8upply voltage
Input voltage
Output voltage
High (828226)
Off-state (828229)
Temperature range
Operating
N828226/229
8828226/229
8torage

Vee
CE,

'F
N

MATRIX

PARAMETER

F,N PACKAGE"

APPLICATIONS

BLOCK DIAGRAM

Vcc

PIN CONFIGURATION

RATING

UNIT

+7
+5.5

Vdc
Vdc
Vdc

+5.5
+5.5
°C

o to +75
-55 to +125
-65 to +150

SmDotiCS

= Cerdip
= Plastic

82S226-F,N .82S229-F,N

DC ELECTRICAL CHARACTERISTICS

Vil
VIH
VIC
VOL
VOH

Output voltage
Low
High (82S229)

III
IIH

Input current
Low
High

10lK
1010FF)

Output current
Leakage (82S226)
H i-Z state (82S229)

.85

CIN
COUT

Capacitance
Input
Output

.80
2.0

2.0
-0.8

liN = -18mA

-0.8

-1.2

0.45

0.5
2.4

2.4

p.A
VIN = 0.45V
VIN = 5.5V

-100
40

-150
50

CE1 or CE2 = High, VOUT = 5.5V
CE1 or CE2 = High, VOUT = 5.5V
CE1 or CE2 = High, VOUT =0.5V
VOUT = OV

40
40
-40
-70

60
60
-60
-85

mA

125

mA

-20
105

-15
105

120

5
8

5
8

R1 = 2700, R2 = 6000, Cl = 30pF
N82S226/229: 0° CST A S +75° C, 4.75V S V cc S 5.25V
S82S226/229: -55° C :<; T A S +125° C, 4.5V S V cc S 5.5V

N825226/229
Typ2
Max

5825226/229
Typ2
Max

TO

FROM

Output
Output

Address
Chip enable

35
15

50
25

35
15

70
35

Output

Chip disable

15

25

15

35

PARAMETER

Min

Min

ns

Disable time
TCD

UNIT
ns

Access time
TCE

p.A
p.A

pF

Vcc = 5.0V
VIN =2.0V
VOUT = 2.0V

AC ELECTRICAL CHARACTERISTICS

TAA

-1.2
V

lOUT = 16mA
CE1 = CE2 = Low, lOUT = -2mA,
High stored

Short circuit 182S229)
Vcc supply current

..

Min

V

Input voltage
Low
High
Clamp

Icc

5825226/229
UNIT
Typ2 Max

N825226/229
Min Typ2 Max

TEST CONDITION51

PARAMETER

los

N82S226/229: O°C S TA S +75°C, 4.75V S Vcc S 5.25V
S82S226/229: -55°C S TA S +125°C, 4.5V S Vcc S 5.5V

NOTES
1. Positive current is defined as into the terminal referenc.ed.
2. Typical values are at Vee = 5.0V, TA = +25°C.

VOLTAGE WAVEFORM

TEST LOAD CIRCUIT
Vee

o-Ao
o-A,
o-A,
o-A,
O-A,
o-A,
o-A,
o-A,
0 - eE,

READ CYCLE

, - - - - - - - - - - - - - - - ' - - - - - - - ·3.0V

~---~~-----~-------OV

0,
R,
OUT

,----·3.0V

0,

1.5V
'-_________....J.+ _____

0,
0,
R2

I.

C L (INCLUDES SCOPE &
JIG CAPACITANCE)

OV

VOH
1.SV

-=

0 - CE2
GNO

-=

All inputs: tr = tl = 5ns (10% to 90%)

71

=
o
....
E
w

E

a:

oc.

--=

B2S214-F,N • B2S215-F,N

DESCRIPTION
The 82S214 and 82S215 include on-chip
decoding and 2 chip enable inputs for ease
of memory expansion. They feature tri-state
outputs for optimization of word expansion
in bused organizations. A O-type latch is
used to enablethetri-state output drivers. In
the Transparent Read mode, stored data is
addressed by applying a binary code to the
address inputs while holding Strobe high.ln
this mode the bit drivers will be controlled
solely by CEl and CE2 lines.
In the Latched Read mode, outputs are held
in their previousstate(high,loworhigh Z) as
long as Strobe is low, regard less of the state
of address or chip enable. A positive Strobe
transition causes data from the applied
address to reach the outputs if the chip is
enabled, and causes outputs to go to the
high Z state if the chip is disabled.
A negative Strobe transition causes outputs
to be locked into their last Read Data condition if the chip was enabled, or causes
outputs to be locked into the high Z condition if the chip was disabled.

Both 82S214 and 82S215 devices are available in the commercial and military temperature ranges. For the commercial temperature range (O°C to +75° C) specify
N82S214/215, F or N, and for the military
temperature range (-55° C to +125° C) specify S82S214/215, F.

P·IN CONFIGURATIONS
F,N PACKAGE"
82S214
A,

VCC

A.

A,
A,

FEATURES

...

• Address access time:
N828214/215: 60ns max
882S214/215: 90ns max
• Power dissipation: 165!'W/bit typ
• Input loading:
N828214/215: -100!,A max
8828214/215: -150!,A max
• On-chip data output registers
• On-chip storage latches
• 8chottky clamped
• Fully compatible with Signetics
828114/115 PROMs
• Fully TTL compatible

A,

CE,

A,

CE,
STROBE

0,

O.

0,

0,

O.

0,

NC

0,

GND

NC

F,N PACKAGE"
828215

APPLICATIONS
•
•
•
•
•

Microprogramming
Hardwire algorithms
Character generation
Control store
Sequential controllers

BLOCK DIAGRAM
CE,
STROBE

A,D--r---,.J
0,
ADDRESS
LINES

A,

0,

0---1.---+1

O.

0,

NC

0,

GND

NC

... 0------- ' -_ _..J

OF

(18)

STROBE

Ce,

0-:-'------_---1

n-(2_0)~r---....

0,

= (241

GND = (12)
( )

O2 0,

0 4 Os

0, 0 7 0,

OUTPUT LINES

= Pin number

ABSOLUTE MAXIMUM RATINGS
PARAMETER
Vcc
VIN
TA

Supply voltage
Input voltage
Temperature range
Operating
N82S214/215
S82S214/215

TSTG

·72

Storage

= Cerdip

N = Plastic

CE, """'("'"'19-)""""'----'

VCC

O.

RATING

UNIT

+7
+5.5

Vdc
Vdc
°C

o to +75
-55 to +125
-65 to +150
SmDotiCS

82S214-F.N .82S215-F.N

DC ELECTRICAL CHARACTERISTICS

N82S214/215: O°C S TA S +75°C. 4.75V S Vcc S 5.25V
S82S214/215: -55°C S TA S +125°C. 4.5V S VCC S 5.5V

S82S214/215

N82S214/215
TEST CONDITIONS'

PARAMETER

VIL
VIH
VIC

Input voltage
Low
High
Clamp

VOL
VOH

Output voltage
Low
High

IlL
IIH

Input current
Low
High

10(OFF)

Output current
Hi-Z state

los

Min

Typ2

Max

Typ2

Min

Max

UNIT
V

.80

.85
2.0

2.0
liN

= -18mA

-0.8

-0.8

-1.2

-1.2
V

lOUT = 9.6mA
CE, = Low. CE2 = High. lOUT
High stored

0.5

0.5

= -2mA.

2.7

2.4

3.3

3.3
p.A

VIN = 0.45V
VIN = 5.5V
CE,
CE,

Short circuit3

Icc

Vcc supply current

CIN
COUT

Capacitance
Input
Output

= High or CE2 = Low. Your = 5.5V
= High or CE2 = Low. Your = 0.5V
VOUT = OV

-20
130

Vcc = 5.0V
VIN = 2.0V
VOUT = 2.0V, CE, = High or CE2

AC ELECTRICAL CHARACTERISTICS

R,

-100
25

-150
50

40
-40
-70

100
-100
-85

mA

815

mA

-15
130

175

p.A

pF

= Low

5
8

5
8

II

S82S214/215: -55°C S TA S +125°C. 4.5V S Vcc S 5.5V

TO

FROM

Output
Output

Address
Chip enable

Output

Chip disable

Access time4
TAA
TCE

TAOH
Tcos
TCOH

Setup and
hold timeS
Hold time
Setup time
Hold time

S82S214/215

Min Typ2 Max Min Typ2 Max
35
20

60
40

35
20

90
50

20

40

20

50

ns

Latched or transparent read
Latched read only
Output
Output

ns

Address

0

-10

5

-10

Chip enable

40
10

0

50
10

0

30

20

40

20

60

35

90

35

Latched read only

Tsw

Pulse widthS
Strobe
Latch timeS
Strobe

Latched read only

TSL

Delatch timeS
Strobe

Latched read only

TOL

UNIT
ns

Latched or transparent read

Disable time 4
Tco

N82S214/215
TEST CONDITIONS

ns
ns
ns
30

35

NOTES
1. Positive current is defined as into the terminal referenced.
2. Typical values are at Vee = +5.0V and TA = +25°C.
3. No more than one Qutputshould be grounded at the same time and strobe should be disabled. Strobe
is in high state.
4. If the strobe is high, the device functions in a manner idential to conventional bipolar ROMs. The
timing diagram shows valid data will appear TA nanoseconds after the address has changed and T CE
nanoseconds after the output circuit is enabled. T CD is the time required to disable the output and
switch it to an "off" or high impedance state after it has been enabled.
5. In Latched Read Mode data from any selected address will be held on the output when strobe is
lowered. Only when strobe is raised will new location data be transferred and chip enable conditions
be stored. The new data will appear on the outputs if the chip enable conditions enable the outputs.

StgOotiCS

E
w
E
..:
c;:

-

= 4700. R2 = 1kO. CL = 30pF

N82S214/215: O°C S TA S +75°C. 4.75V S Vcc S 5.25V

PARAMETER

=
o
....o

73

82S214-F,N .82S21S-F,N

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM
···Vee

INPUT PULSES

, .:~

"INPUT

AI;.L INPUT PULSES
+3.0V -, - -

-::r-------::lL

Vee

OV

R,

0,

5ns

PULSE
GENERATOR·

'3'OV~_
10%0,
R, ':"

ICL

90%

~---

---

- - 5no

_.

.
- - 5no

(INCLUDES JIG '&
SCOPE CAPACITANCE)

TIMING DIAGRAMS
TRANSPAR.ENT READ

LATCHED READ

_.J. . _,.-------------------.:i.OV
. . - :_-__. . . . .______.___ " - __._,_____ . . ___

STROBE ;I

Oy

~_---

Act·· .A n

____ J

____________________

+3.0V

r------;:::':~:":=1=~:L.

r------

·3.0V

1.SV

'-------------------OV
&£,
....;.--+--, ~-----'"' ~---- .~.OV

' - : - - - - : - - - - - OV

' - - - ' - - - , . . . . . OV

VOH

Output Latches Not Used

74

,3.0V

Output. Latches Used

82S230 (0 C ) 82S131 (1 S )

,n4R BIT BIPOlAR RIIM (51214)

82S230-F,N .82S231-F,N

DESCRIPTION

• Power dissipation: 0.3mW/bit typ
• Input loading:
N825230/231: -100JLA max
5825230/231: -150JLA max
• On-chip address decoding'
• Output options:
825230: Open collector
825231: Tri-state
• Fully compatible with 5ignetics
825130/131 PROMs
• Fully TTL compatible

The 82S230 and 82S231 include on-chip
decoding and 1 chip enable inputforeaseof
memory expansion. They feature either
open collector or tri-state outputs for optimization of word expansion in bused organizations.
Both 82S230 and 82S231 devices are available in the commercial and military temperature ranges. For the commercial temperature range (Q°C to +75°C) specify
N82S230/231, F or N, and for the military
temperature range (-55° C to+125°C) specify S82S230/231, F.

PIN CONFIGURATION
F,N PACKAGE·

Vee
A,

=

A,

Co
0,

0
Ii
w
Ii

0,

APPLICATIONS
•
•
•
•
•
•

FEATURES
• Address access time:
N825230/231: SOns max
5825230/231: 70ns max

0,

5equential controllers
Microprogramming
Hardwired algorithms
Control store
Random logiC
Code conversion

'F

~

N

= Plastic

Cerdip

•a:..,

BLOCK DIAGRAM

..-

0

(1)
32X16

A,
A,
A,
A,
A,
A,
A,
A,
A,
A,

II

32X16

32X16

0,
32X16

(32)

ABSOLUTE MAXIMUM RATINGS
PARAMETER

Vcc
VIN
VOH
Vo
TA

TSTG

Supply voltage
Input voltage
Output voltage
High (82S230)
Off-state (82S231)
Temperature range
Operating
N82S230/231
S82S230/231
Storage

RATING

UNIT

+7
+5.5

Vdc
Vdc
Vdc

+5.5
+5.5
°C

o to +75
-55 to +125
-65 to +150

SrnDotiGS

75

2048 BIT BIPOEnR ROM (51214)

825230 (0 C ) 825231 (J 5 )
828230-F,N .828231-F,N

DC ELECTRICAL CHARACTERISTICS

N828230/231: O°C S TA S +75°C, 4.75V S Vcc S 5.25V
8828230/231: -55°C S TA S +125°C, 4.5V S VCC S 5.5V

'.

VIL
VIH
VIC

I nput voltage
Low
High
Clamp

VOL
VOH

Output voltage
Low
High (828231)

ilL
ilH

Input current
Low
High

10LK
10(OFF)

Output current
Leakage (828230)
Hi-Z state (828231)

Typ2

Min

Max

Min

Typ2

Max

UNIT
V

.85

.80
2.0

2.0
liN = -18mA

-0.8

-1.2

-0.8

-1.2
V

lOUT = 16mA
CE = Low, lOUT = -2mA,
High stored

0.45
2.4

0.5
2.4
p.A

8hort circuit (828231)

los

5825230/231

N825230/231
TE5T CONDITION5 1

PARAMETER

Icc

Vcc supply current

CIN
COUT

Capacitance
Input
Output

VIN = 0.45V
VIN = 5.5V

-100
40

CE = High, VOUT = 5.5V
CE = High, VOUT = 0.5V
CE = High, VOUT = 5.5V
VOUT = OV

40
-40
40
-70

-20
120

Vcc - 5.0V
VIN= 2.0V
VOUT = 2.0V

AC ELECTRICAL CHARACTERISTICS

-150
50

-15

140

120

60
-60
60
-85

mA

140

mA

p.A
p.A

pF
5
8

5
8

R1 = 2700, R2 = 6000, CL = 30pF1
N828230/231: 0° CSTA S +75° C, 4.75V S V cc S 5.25V

8828230/231: -55° C S TA S +125° C, 4.5V S Vcc S 5.5V
N825230/231
PARAMETER

TO

FROM

Output
Output
Output

5825230/231

Typ2

Max

Address
Chip enable

40
20

Chip disable

20

Min

Typ2

Max

50
30

40
20

70
35

30

20

35

Min

UNIT
ns

Access time
TAA
TCE

ns

Disable time
TCD
NOTES
1. Positive current is defined as into the terminal referenced.
2. Typical values are at Vee == S.OV, TA = +25°C.

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM

Vee

READ CYCLE
~---------------- '3.0V
' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OV

Vee

~---+3.0V

0,

1.5V

A,

' -_ _ _ _ _ _ _ _ _

0,

- - - - - - - OV

Teo

0,

o.

1.5V

All inputs

76

.J~

Si!JnntiCs

tr ==

tt

= 5ns (10% to 90%)

4096 BIIBIPOIAR ROM (51)118)

8?Sll40 (U G ) 89S'41 (I

S)

828240-F,N .828241-F,N

DESCRIPTION
The 828240 and 828241 are mask programmable, and include on-chip decoding and 4
chip enable inputs for ease of memory expansion. They feature either open collector
or tri-state outputs for optimization of word
expansion in bused organizations.
Both 828240 and 828241 devices are available in the commercial and military temperature ranges. For the commercial temperature range (O°C to +75°C) specify
N828240/241 , For N, and for the military
temperature range (-55° C to +125° C) specify 8828240/241, F.

FEATURES
• Address access time:
N825240/241: 60ns max
5825240/241: 90ns max

• Power dissipation: .17mW/bit typ
• Input loading:
N825240/241: -100IlA max
5825240/241: -150I'A max
• On-chip address decoding
• Output options:
825240: Open collector
5825241: Tri-state
• Fully TTL compatible

PIN CONFIGURATION
F,N PACKAGE'

=
o
..
o
.-.

APPLICATIONS
•
•
•
•
•
•
•

Volume production
5equential controllers
Microprogramming
Hardwired algorithms
Control store
Random logic
Code conversion

E
w
E
a:

0,

0,
GNO

·F
N

BLOCK DIAGRAM

=

O.

Cerdip

= PlastiC

~

c.

t-;I

A,

I
I

ADORES S
LINE S

II

1:64 DE·
CODER

I

I
I
I

A.

I
I
I
I
I
I
I
I

64X64 MATRIX

t---!.-

1-------------------1
A.
A,

1:8
MUX

1:8

1:8

MUX

1:8
MUX

1:8

MUX

1:8
MUX

1:8

MUX

MUX

MUX

1

1

1

1

1

1

1

1

1:8

A,

CE;
CE,
CE,
CE,

~

""\
f

11 1 1 1 1 1 1
OUTPUT LINES

ABSOLUTE MAXIMUM RATINGS
PARAME'tER
Vee
VIN
VOH
Vo
TA

8upply voltage
Input voltage
Output voltage
High (828240)
Off-state (828241)
Temperature range
Operating

N828240/241
8828240/241
TSTG

8torage

RATING

UNIT

+7

Vdc
Vdc
Vdc

+5.5
+5.5
+5.5

°C

o to +75
-55 to +125
-65 to +150

SmDl!tiCS

77

828240-F,N .828241-F,N

DC ELECTRICAL CHARACTERISTICS

N828240/241: O°C:S TA:S +75°C, 4.75V:S Vee:S 5.25V
8828240/241: -55°C:s TA:S +125°C, 4.5V:S Vee:S 5.5V
N82S240/241

PARAMETER

VIL
VIH
Vie

Input voltage
Low
High
Clamp

VOL
VOH

Output voltage
Low
High (828241)

ilL
IIH

Input current
Low
High

10LK

Output current
Leakage (828240)

10(OFF)

Hi-Z state (828241)

TEST CONDITIONS1

Vee supply current

CIN
COUT

Capacitance
Input
Output

S82S240/241

Max

Min

Typ2

Max

UNIT
V

.80
2.0

2.0
liN = -18mA

-0.8

-0.8

-1.2

-1.2
V

IOUT= 9.6mA
CE1 = Low, lOUT =-2mA, CE2 = Low,
CE3 = High, CE4 = High, High stored

CE1
CE1

2.4

2.4

J1A

= High, VOUT = 5.5V, CE2 = High,
CE3 = Low, CE4 = Low
= High, VOUT = 0.5V, CE2 = High,
CE3 = Low, CE4 = Low
= High, VOUT = 5.5V, CE2 = High,
CE3 = Low, CE4 = Low
VOUT = OV

-20

Vee = 5.0V
VIN = 2.0V
VOUT = 2.0V

-100
40

-150
50

40

60

J1A

-40

-60

J1A

40

60

-70
140

AC ELECTRICAL CHARACTERISTICS

0.5

0.45

VIN = 0.45V
VIN = 5.5V

8hort circuit (828241)

lee

Typ2

.85

CE1
los

Min

-15
140

175

-85

mA

185

mA
pF

5
8

5
8

R1 = 470.0, R2 = 1kn, CL = 30pF
N828240/241: O°C:S TA:S +75°C, 4.75V:S Vee :S 5.25V
8828240/241: -55°C:s TA:S +125°C, 4.5V:S Vec:S 5.5V
S82S240/241

N82S240/241

TO

FROM

Output
Output
Output

PARAMETER

Typ2

Max

Address
Chip enable

40
20

Chip disable

20

Min

Min

Typ2

Max

60
40

40
20

90
50

40

20

50

ns

Access time
TAA
TCE

ns

Disable time
Teo
NOTES
1. Positive current is defined as into the terminal referenced.
2. Typical values are at Vee == S.OV, TA == +25°C.

78

UNIT

Smnotics

4051. Bit BII

m ;I(

RUM (b I '18)
82S240-F,N .82S241-F,N

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM

+ 3.0V

OV

A,
A,

=

+ 3.0V

VCC
CHIP ENABLES

A,
A,

0,

TCO

R,

A,

0
E
W
E

VOH

OUT

A,

01

08

A.
A,

R,

A.

~

CE,

CE,

CE,

~

GND

CL
I('NJIG
CLUOES
SCOPE &
CAPACITANCE)

All inputs; tr =

tt = 5ns

(10% to 90%)

.-c:...
0

":'

e.

II

StgDotiCS

79

4096 BIT BIPOtARROM (Hl24X4)
8228-F

DESCRIPTION

FEATURES

The 8228, available in a 16-pin dual-in-line
package, can provide very high bit packing
density by replacing 4 ,standard 256X4
ROMs.

•
•
•
•

This device includes on-chip decoding, and
has a typical access time of 50ns with a
power consumption of only .125mW per bit.
The standard 8228 ROM pattern is the
USASCII Row Character Generator code;
however; custom patterns are also 1t\lai 1able. The standard pattern is specified as
the N82281-CB162, while custom circuits
are identified as N82281-CXXX.

PIN CONFIGURATION

Buffered address lilies
Totem pole outputs
Diode protected inputs
Fully TrL compatible

F PACKAGE"

APPLICATIONS
•
•
•
•
•

Microprogramming
Hardwired algorithms
Character recognition
Character generation
Control store

*Oual-in-line (1/3 size of 24-pin package)

BLOCK DIAGRAM
INPUT
SCHEMATIC

Vee

OUTPUT
SCHEMATIC

Vee

64X64 BIT
STORAGE MATRIX

ADDRESS
LINES

64-4·8IT
MULTIPLEXER

GND

= 1161
= 181

(

= Pin number

vee
)

OUTPUT DATA

DC ELECTRICAL CHARACTERISTICS

O°C:S TA:S 75°C, 4.75V:S Vee:S 5.25V
LlMtTS

'"

PARAMETER

VIL
VIL
VIC

80

.1!1Put voltage
. Low
High
Clamp

TEST CONDITIONS

Min

Typ

Max

UNtT

V
.85
liN

= -18mA

VOL
VOH

Output voltage
Low
High

IlL
IIH

Input current
Low
High

VIN = 0.45V
VIN = 5.5V

los

Output current
Short circuit

VOUT

Icc

Power consumption

2.0
-1.2
V

lOUT
lOUT

= 11.2mA
= -1.0mA

0.5
2.7
/lA
-10
1

-400
25
mA

01

= OV
to 03 = Low

Si,gRHtiCS

-20

-70
140

170

mA

8228-F

AC ELECTRICAL CHARACTERISTICS

0:S TA:S 75°C, 4.75:S Vee:S 5.25V

LIMITS
PARAMETER

TO

FROM

Output

Address

Min

Typ

Max

50

70

Access time 1
TAA

UNIT

ns

=
o

NOTES
1. Rise and fall time for this test must b~ less than 5ns. Input amplitudes are 3.0V and all measurements
are made at 1.SV.
2. Positive current is defined as into the terminal referenced.
3. No more than 1 output should b~ grounded at the same time.
4. Manufacturer reserves the right to make design and process changes and improvements.

TEST LOAD CIRCUIT

E
w
E
..:
c:

VOLTAGE WAVEFORM
READ CYCLE

360,0;

~

oe.
-=

-

5K

SillllDtiGS

81

82S280-F,N • 828281-F,N

DESCRIPTION

FEATURES

The 828280 and 828281 include on-chip
decoding and 4 chip enable inputs for ease
of memory expansion. They feature either
open collector or tri-state outputs for optimization of word expansion in bused organizations.

• Address access time:
N82S280/281: 70ns max
S82S280/281: 100ns max
• Power dissipation: 6OI'W/bit typ
• Input loading:
N82S280/281: -100IlA max
S82S280/281: -150I'A max
• On-chip address decoding
• Output options:
82S280: Open collector
82S281: Tri-state
• Enable =
E3 • E4
• Fully TTL compatible

Both 828280 and 828281 devices are available' in the commercial and military temperature .ranges. For the commercial temperature range (O°C to +75° C) specify
N828280/281, F or N, and for the miiitary
temperature range (-55° C to +125°C) specify 8828280/281, F only.

PIN CONFIGURATION
F,N PACKAGE"

E1. E2 •

BLOCK DIAGRAM

A,

'F

A,

N
ADD
'NY
AND
1164
DEC

A,
A,
A,

64X128
MEMORY ARRAY

A,

A,
A,
A,
A,

E,

e;
E,
E.

vec = 24
GND

= 12

ABSOLUTE MAXIMUM RATINGS
PARAMETER

Vec
VIN
Vo
TA

TSTG

82

8upply voltage
Input voltage
Output voltage
Off-state
Temperature range
Operating
N828280/281
8828280/281
8torage

RATING

UNIT

+7
+5.5

Vdc
Vdc
Vdc

+5.5
°C

o to +75
-55 to +125
-65 to +150

SmOOllCS

= Cerdip
= Plastic

82S280-F,N • 82S281-F,N

DC ELECTRICAL CHARACTERISTICS

N82S280/281: O°C::; TA::; +75°C, 4.75V::; Vcc::; 5.25V
S82$280/281: -55°C::; TA::; +125°C, 4.5V::; Vcc::; 5.5V

N82S280/281 1

PARAMETER

VIL
VIH
VIC

Input voltage
Low
High
Clamp

VOL
VOH

Output voltage
Low
High

hL
hH

Input current
Low
High

IO(OFF)

Output current
Hi-Z state

los
Icc
CIN
COUT

Short circuit3

TEST CONDITIONS

Min

Typ2

Max

Typ2

Max

= -18mA

-0.8

-1.2

-0.8

-1.2
V

lOUT = 9.6mA
CE1 = Low, CE2 = High, lOUT
High stored

0.5

0.45

= -2mA,

2.4

2.4
p.A

VIN = 0.45V
VIN = 5.5V
CE1
CE1

= High or CE2 = Low, VOUT = 5.5V
= High or CE2 = Low, VOUT = 0.5V
VOUT = OV

-20
100

Vcc = 5.0V
VIN = 2.0V
VOUT = 2.0V

AC ELECTRICAL CHARACTERISTICS

-100
25

-150
50

40
-40
-70

100
-100
-85

rnA

150

rnA

-15
100

140

p.A

pF
5
8

5
8

TO

FROM

Output
Output
Output

S82S280/281

Typ2

Max

70
40

40
20

100
50

40

20

50

Typ2

Max

Address
Chip enable

40
20

Chip disable

20

Min

Min

UNIT

ns

Access time

ns

Disable time
NOTES
1. Positive current is defined as into the terminal referenced.

2. Typical value. are al Vee = +5.0V and TA = +25' C.
3. No more Ihan one oulpul should be grounded allhe same lime.

9!!)DOliC9

Ii
w
Ii

5-=

oe.

ii

R1 = 4700, R2 = 1kO, CL = 30pF
N82S280/281: O°C:5 TA:5 +75°C, 4.75V::; Vec::; 5.25V
S82S280/281: -55°C::; TA:5 +125°C, 4.5V::; Vcc:5 5.5V
N82S280/281

TCD

=
o

.80
2.0

2.0
hN

Capacitance
Input
Output

TAA
TCE

UNIT

V
.85

Vcc supply current

PARAMETER

S82S280/281 1

Min

83

8192 BIT BIPOLAR ROM (W24X8)

828280 (0 C ) 828281 (T 8 )
82S280-F,N .82S281-F,N

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM
INPUT PULSES
Vee
ALL INPUT PULSES
+3,QV - - - - :::r----------~

INPUT

A,

Vee

OV

+3.0V

0,

R,

PULSE

GENERATOR

A,

0,
R,

(INCLUDES JIG &
SCOPE CAPACITANCE)

TIMING DIAGRAM

Ao ... An

______ J'"

" , . . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + 3.0V
1.SV

' - - - - - - - - - - - - - - -______________________ oV

eE,
_~----+3_0V

CHIP ENABLE

eE

84

1.5V

' - - - -_ _ oV

Si!)nl!tiCs

OBJECTIVE SPECIFICATION

82S290-F,N • 82S291-F,N

PIN CONFIGURATION

DESCRIPTION

FEATURES

The 82S290 and 82S291 include on-chip
decoding and 3 programmable chip enable
inputs for ease of memory expansion. They
feature either open collector or tri-state
outputs for optimization of word expansion
in bused organizations.

• Address access time:
N82S290/291: 80ns max
S82S290/291: lOOns max
• Power dissipation: 40l'W/bit typ
• Input loading:
N82S290/291: -lOOIlA max
S82S290/291: -150I'A max
• On-chip address decoding
• Output options:
82S290: Open collector
82S291: Tri-state
• Fully compatible with Signetics
82S190/191 PROMs
• Fully TTl.. compatible

Both 82S290 and 82S291 devices are available in the commercial and military temperature ranges. For the commercial temperature range (O°C to +75° C) specify
N82S290/291, F or N, and for the military
temperature range (-55° C to +125° C) specify S82S290/291, F.

F,N PACKACE*

I;

o

E
w
E
c:

APPLICATIONS
•
•
•
•
•
•

Sequential controllers
Microprogramming
Hardwired algorithms
Control store
Random logic
Code conversion

'F
N

~
~

.-...

...-.

Cerdip
Plastic

o

BLOCK DIAGRAM

r--------------------------------------'

~O-~----~__

I
I

AOD

ADDRESS
LINES

I
I
I
I

INV

128X,28
MEMORY ARRAY

",2.
DEC

A"

eE,/eE,o------,
CE~/CE2

0-------1

CEJ/CEJ

0-----'

vcc

~

24

GND

~

12

ABSOLUTE MAXIMUM RATINGS
PARAMETER

Vec
VIN
VOH
Vo
TA

TSTG

Supply voltage
Input voltage
Output voltage
High (82S290>
Off-state (82S291)
Temperature range
Operating
N82S290/291
582S290/291
Storage

RATING

UNIT

+7
+5.5

Vdc
Vdc
Vdc

+5.5
+5.5
o.C

o to +75
-55 to +125
-65 to +150
S!!IDotiCS

85

OBJECTIVE SPECIFICATION

82S290-F,N .82S291-F,N

DC ELECTRICAL CHARACTERISTICS

N82S290/291: O°C $ TA

s; +75°C, 4.75V $

Vcc $ 5.25V

S82S290/291: -55°C $ TA $ +125°C, 4.5V $ Vcc $ 5.5V

VIL
VIH
VIC

Input voltage
Low
High
Clamp

VOL
VOH

Output voltage
Low
High (825291)

IlL
hH

Input current
Low
High

10lK
10(OFF)

Output current
Leakage (82S290)
Hi-Z state (82S291)

los

Vcc supply current

CIN
COUT

Capacitance
Input
Output

S82S290/291
Max

Typ2

Min

Typ2

Max
.80

2.0
liN

= -18mA

2.0
-1.2

-0.8

-0.8

-1.2
V

lOUT = 9.6mA
CE = Low, lOUT = -2.4mA,
High stored

0.45

0.5

2.4

2.4
J.lA

VIN = 0.45V
VIN = 5.5V
CE
CE
CE

= High, VOUT = 5.5V
= High, VOUT = 0.5V
= High, VOUT = 5.5V
VOUT = OV

-20
130

Vcc = 5.0V
·VIN = 2.0V
VOUT = 2.0V

TO

-100
40

-150
50

40
-40
40
-70

60
-60
60
-85

mA

180

mA

-15
130

170

pF

R1 = 2700, R2 = 6000, Cl = 30pF1
N82S290/291: O°C $ TA $ +75°C, 4.75V $ Vcc $ 5.25V
S82S290/291: -55°C $ TA $ +125°C, 4.5V $ Vcc $ 5.5V

882S290/291

N82S290/291

FROM
Min

Typ2

Max

.Min

Typ2

Max

UNIT
ns

Output
Output

Address
Chip enable

50
20

80
40

50
20

100
50

Output

Chip disable

20

40

20

50

ns

Disable time
TCD

J.lA
J.lA

5
8

5
8

Access time
TAA
TCE

UNIT
V

AC ELECTRICAL CHARACTERISTICS

PARAMETER

Min

.85

Short circuit (82S291)

Icc

N82S290/291

TEST CONDITION81

PARAMETER

NOTES
1. Positive current is defined as into the terminal referenced.
2. Typical values are at Vee = S.OV, TA = +25°C.

VOLTAGE WAVEFORM

TEST LOAD CIRCUIT

READ CYCLE

,_-----------------.3.0V

INPUT

~--------

_ _ _ _ _ _ _ _ _ OV

,_----·3.0V
CE

(INCLUDES JIG &
SCOPE CAPACITANCE)

86

G[gDotiCG

1.SV
_ T A A - ' - _ _ _ _ _ _ _ _J

PROGRAMMING INFORMATION
Programming Equipment for
Signetics PROMs

Curtis Enterprises
P.O, Box 40.90.
Mountain View, Calif, 940.40.
(415) 964-3136

Programming equipment is available from
several manufacturers, including Curtis Enterprises, Data 110, and Pro-Log. Choice of
equipment varies from manual duplicators
to fully automatic programmers which read
paper tape coded in a variety of formats.

Data 1/0 Corporation
P,O, Box 30.8
Issaquah, Washington 980.27

=
o

Pro-Log Corporation
2411A Garden Road
Monterey, Calif. 93940.
(40.8) 372-4593

For more information, contact 8ignetics
Memory Marketing or any of the following
programmer manufacturers:

E
w

CURTIS ENTERPRISES REFERENCE
PROM TYPE

ORGANIZATION

OUTPUTS

MANUAL PROGRAMMER

8223
82823
828123
82827
828126
828129
828114
828115
828130.
828131
10.139

32X8
32X8
32X8
256X4
256X4
256X4
256X8
512X8
512X4
512X4
32X8

OC
OC
T8
OC
OC
T8
T8
T8
OC
T8
(ECl)

PR-23B or PR-1369A
PR-1369A
PR-1369A
PR-27
PR-1369A or PR-1269
PR-1369A or PR-1269
PR-145
PR-145
PR-1369A
PR-1369A
PR-1o.139

E

DUPLICATOR
PR-23o.o.
PR-23o.o.8
PR-23o.o.8

II:
c;:

o--

PR~270o.8

...-.

PR
PR-260o.8A
PR-1145
PR-1145
PR-26o.o.8A
PR-26o.o.8A
-

PRO-LOG REFERENCE
PROM TYPE

ORGANIZATION

82823
828123
828126
828129
828130.
828131
828114
825115
10.149
828136
828137
828184
828185
828180.
828181

32X8
32X8
256X4
256X4
512X4
512X4
256X8
512X8
256X4
1o.24X4
1o.24X4
2o.48X4
2o.48X4
1o.24X8
1o.24X8

OUTPUTS

(ECl)

MANUAL PROGRAMMER
PM9o.1o.
PM9o.1o.
PM9o.o.8
PM9o.o.8
PM9o.o.8
PM9o.o.8
PM9o.21
PM9o.21
N/A'
N/A*
N/A*
N/A*
N/A*
N/A*
N/A*

·Contact Signetics or PrO-Log

!i~nl!tiC!i

87

DATA 1/0
MODEL V UNIVERSAL PROGRAMMER
MODEL IX PORTABLE PROGRAMMER
MODEL X FPLA PROGRAMMER

CONFIGURATION

MANUFACTURERS'
PART NO.

DATA 1/0
PROGRAM
CARD SET

32X8 CFU
32X8 CFU
32X8CFU
256X8 CFU
512X8 CFU
256X4 CFU
256X4 CFU
512X4 CFU
512X8 CFU
1024X4 CFU
1024X8.CFU
2048X4 CFU
2048X8 CFL)

8223
10139 ECL
82823, 828123
828114
828115
10149 ECL
828126,828129
828130. 82S131
82S140, 828141
82S136,82S137
828180,82S181,8282708
82S184,82S185
82S190,82S191

1051-1
1051-2
1051-7
1226-2'
1226-2'
1144-1
1226-2'
1226-2'
1226-2'
1226-2'
1226-2'
1226-2'
1226-2"

PRO·
GRAMMED
LOGIC
LEVEL

READ.ONLY
CARD

READ·ONLY
SOCKET
ADAPTER

1034
1034
1034
1096
1097
1003-4
1035-1
1035-2
1033-2
1039-3
1033-3
1039
1033

VOH
VOH
VOH
VOH
VOH
YOH
VOH
VOH
VOH
VOH
YOH
VOH
VOH

1142
1142
1142
1142
1142
1187-13
1142
1142
1142
1142
1142
1142
1142

1037
1037
1037
1096
1097
1003-4
1035
1035
1033
1039
1033
1039
1033

'Generlc Program Cards

88

READ·ONL Y OPTIONS

PROGRAM
SOCKET
ADAPTER

SmODtiCS

82823-F,N • 828123-F,N

DESCRIPTION

FEATURES

The 82823 and 828123 are field programmable, which means that custom patterns
are immediately available by following the
fusing procedure given in this data sheet.
The standard 82823 and 828123 devices are
supplied with all outputs at logical low.
Outputs are programmed to a logic high
level at any specified address by fusing a NiCr link matrix.

• Address access time:
N82S23/123: SOns max
S82523/123: 65ns max
• Power dissipation: 1.3mW/bittyp
• Input loading:
N82523/123: -lOOf.LA max
582523/123: -150f.LA max
• On-chip address decoding
• Output options:
82523: Open collector
825123: Tri-state
• No separate fusing pins
• Unprogrammed outputs are low level
• Fully TTL compatible

These devices include on-Chip decoding
and 1 chip enable input for ease of memory
expansion. They feature either open collector or tri-state outputs for optimization of
word expansion in bused organizations.
Both 82823 and 828123 devices are available in the commercial and military temperature ranges. For the commercial temperature range (O°C to +75° C) specify
N82823/123, N or F, and forthe militarytemperature range (-55°C to +125°C) specify
882823/123, F only.

PIN CONFIGURATION
F,N PACKAGE

o==
E
w

E

APPLICATIONS
•
•
•
•
•
•

Prototypinglvolume production
Sequential controllers
Format conversion
Hardwired algorithms
Random logic
Code conversion

•...

G:

oe.

-..

LOGIC DIAGRAM

32X8 ARRAY

e,

8,

B,

8,

B,

B.

8,

Vee ~ (16)
GND ~ (8)

ABSOLUTE MAXIMUM RATINGS
PARAMETER
Vee
VIN
VOH
Vo
TA

TSTG

8upply voltage
Input voltage
Output voltage
High (82823)
Off-state (828123)
Temperature range
Operating
N82823/123
882823/123
8torage

SegDotiGS

RATING
+7
+5.5

UNIT
Vdc
Vdc
Vdc

+5.5
+5.5
°C

a to +75
-55 to +125
-65 to +150
89

82S23 (0 C ) 82S123 (IS )

256 BIT BIPOLAR PROM (3218)

82S23-F,N .82S123-F,N

DC ELECTRICAL CHARACTERISTICS

N82S23/123: O°C:S TA:S +75°C, 4.75V:s Vcc:S 5.25V
-55°C:S TA:S +l25°C, 4.5V:S Vcc :S 5.5V

S82S23/123:

,"

PARAMETER

VIL
VIH
VIC

Input voltage
Low
High
Clamp

VOL
VOH

Output voltage
Low
High

ilL
IIH

Input current
Low
High

10LK
10(OFF)

Output current
Leakage (82S23)
Hi-Z state (82S123)

los

Vcc supply current

CIN
COUT

Capacitance
Input
Output

Typ

Min

S82S23/123

Max

Min

Typ

Max

UNIT
V

0.85
2.0

0.8
2.0

-0.8

liN = -18mA

-0.8

-1.2

-1.2
V
0.5

0.45

lOUT = 16mA
CE= Low, louT=-2mA, High stored

2.4

2.4
/lA

Short circuit (82S123)

Icc

N82S23/123

TEST CONDITIONS1

VIN = 0.45V
VIN = 5.5V

-100
50

-150
50

CE = High, VOUT = 5.5V
CE = High, VOUT = 5.5V
CE = High, VOUT = 0.5V
VOUT = OV

40
40
-40
-90

50
50
-50
-100

mA

85

mA

-20
65

5
8

5
8

R1 = 270.0, R2 = 600.0, CL = 30pF1
N82S23/123: 0° C :S T A :S +75° C, 4.75V :S Vcc :S 5.25V
S82S23/123: -55°C <
- Vcc <
- 5.5V
- TA -< +125°C, 4.5V <
,

PARAMETER

65

pF

VCC = 5.0V
VIN = 2.0V
VOUT = 2.0V

AC ELECTRICAL CHARACTERISTICS

-20

77

/lA
/lA

TO

FROM

Output
Output
Output

N82S23/123

S82S23/123

Typ2

Max

Address
Chip enable

35
25

Chip disable

25

Min

UNIT

Typ2

Max

50
35

35
25

65
40

35

25

40

Min

Access time

ns

TAA
TCE
Disable time

ns

TCD
NOTES

1. Positive current is defined as into the terminal referenced.
2. Typical vaJu8S,are at Vee = ,S.OV, TA = +25°C.

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM
, . - - -_ _ _ _ _ _ _ _ _ _ _ _ _ .3,OV

~~

_______________________ ov

~----+3.0V

",

":""'1

C

(INCLUDES SCOPE &.
L

JIG CAPACITANCE)

GND

All inputs: t,

90

S~nl!tics

~

tf

~

5ns 110% to 90%1

82S23-F,N .82S123-F,N

PROGRAMMING SPECIFICATIONS

(Testing of these limits may cause programming of deviceJ TA = +25°C
LIMITS

PARAMETER

Veep

Power supply voltage
To program 1

VCCH
VCCL

Verify limit
Upper
Lower

Vs
Iccp

Verify threshold2
Programming supply current

VIH
VIL

Input voltage
High
Low

IIH
IlL

Input current
High
low

VOUT
lOUT
TR
tp
tv
to
TPRI
Tps
TPR

---TPR+Tps

Output programming voltage3
Output programming current
Output pulse rise time
CE programming pulse width
Verify delay
Pulse sequence delay
Initial programming time
Programming pause

TEST CONDITIONS

Iccp = 250 ± 50mA,
Transient or steady state

UNIT

Min

Typ

Max

9.5

10.0

10.5

5.3
4.3

5.5
4.5

5.7
4.7

0.9
200

1.0
250

1.1
300

0.4

5.5
0.8

V

V

Vccp = +10.0 ± 0.5V

o==

V
mA

E
w
E
c:

V
2.4
0

.....
..o-

p.A
50
-500

VIH =+5.5V
VIL = +O.4V
lOUT = 65 ± 3mA,
Transient or steady state
VOUT = +15.5 ± 0.5V

Vce = Vccp
Vec = OV

15.0
60
10
0.3
50
10

15.5

16.0

V

0.4

50
0.5

mA
P.s
ms
P.s

12
6
50

Programming duty cycle4

sec
sec
%

II

NOTES
1. Bypass Vee to GND with a 0.01 /-IF capacitor to reduce voltage spikes.
2. Vs is the sensing threshold of the PROM output voltage for a programmed bit. It normally const,itutes
the reference voltage applied to a comparator circ~it to verify a successful fusing attempt.
3. Care should be taken to insure that +15.5 ± O.5V output voltage is maintained during theentirefusing
cycle. The recommended supply is a constant current source clamped at the specified voltage limit.
4. Continuous fusing for an unlimited time is also allowed, provided thata 50% duty cycle is maintained.
This may be accomplished by using a programming time and pauses of 6~ each.

PROGRAMMING PROCEDURE
1. Terminate all device outputs with a 10KO
resistor to Vcc.
2. Select the address to be programmed,
and raise Vcc to Vccp = +10 ± 0.5V.
3. After 10p.s delay, apply lOUT = 65 ± 3mA
to the output to be programmed. Program one output at a time.
4. After 10p.s delay, pulse the CE input to
logic low for 0.3 to 0.5p.s.
5. After 10p.s delay, remove lOUT from the
programmed output.
6. After 10p.s delay, return Vec to OV.
7. To verify programming, after 50p.s delay,
raise Vec to VCCH = +5.5 ± .2V, and apply
a logic low level to the CE input. The
programmed output should remain in the
high state. Again, lower Vcc to VeCL =
+4.5 ± .2V, and verify that the programmed output remains in the high
state.
8. Raise Vec to Vecp = +10 ± 0.5V and
repeat steps 3 through 7 to program other
bits at the same address.
9. After 10p.S delay, repeatsteps2through 8
to program all other address locations.

SmDOliCS

91

II

III

82S23-F,N • 82S123-F.'N

TYPICAL FUSING PATH

r---------- --,
I

4K

I
I

-

I

I

:

8 BIT
LINES

1 of 32

I
I

1

DECODE

6K

I

3K

I.

OUTPUT

DISABLE I

I

I

I
I
I
I
I

I1

_

&... --,-~--------~

,K

6K

TYPICAL PROGRAM.MING SEQUENCE

~~~"~':',"",'4

-:._-,-_-+1+1_.......;~___·A_l.;.A_S_T~'- ~""""'

_ _ _ _ _ _ _ _ _ _ _A_F_'R_S_T_ _ _ _ _

__

T PRI

(INITIAL PROGRAM)

--I tvlVccp ___ r--I
~_+=:::H--------------- ~'O __ ---- - -------,2sec

vcc~
OV

I

II.

U

~t+-

~_VCCl

VERIFY'

+15.5V - - - - - 90%

B,

OUTPUT

VOLTAGE
OV

"'" .,.,.""";r-'--\
CE

*Programming verification at both high and low Vee margins is optional for convenience. Verification can
also be executed at the operating Vee limits specified in the de characteristics.

92

-1'
t
..
___ flLJ[

'01_
-------lJlj-----U

"0"

--1,~~.-, r---

I'

1

256 BIT EeE It IGII PERFORMANCE PROM (32X8)

10139
10139-F,N

DESCRIPTION

FEATURES

The 10139 is organized as an array of 32
words and 8 bits. The initial unprogrammed
state is 0 (low). The user may program 1's to
obtain any desired pattern. Outputs go to
the 0 (low) state when the chip enable input
is high, allowing wired-OR output connections. A son output drive capability makes
the part suitable for use in high performance
ECl systems.

•
•
•
•
•
•
•

PIN CONFIGURATION

Access time: 15ns typ
Power dissipation: 580mW typ
Field programmabl~(':'Ii-Cr link)
Fully decoded
High impedance inputs (50kn pulldown)
Open emitter outputs (SOn drive)
Fully compatible with Signetics ECl 10K
products

F,N PACKAGE'

=:o

APPLICATIONS
•
•
•
•

Programmable logiC
Control stores
Microprogramming
Hardwired algorithms

E
w

*F = Cerdip
N = Plastic

RECOMMENDED OPERATING
VOLTAGE
•

VCC = GND, VEE = -5.2V

E
c:

•...

± 5%

BLOCK DIAGRAM

o
e.

C'E-------------l

-

32X8

FUSE
ARRAY

">-----

I II

D.

A,

A,

ADDRESS
BUFFER

A,

>----0,

ABSOLUTE MAXIMUM RATINGS
PARAMETER
TA

Temperature range
Operating

RATING

UNIT
°C

-30 to +85

Si!)DutiCS

93

10139-F,N

DC ELECTRICAL CHARACTERISTICS Vee = OV, Vee = -5 2V , RL = 50n to -2V, Vdc -+ 1%
PARAMETER

VIL
VIH
VILA
VIHA

Input voltage
Low
High
Low threshold
High threshold

VOL
VOH

Output voltage
Low
High
Low threshold
High threshold'
Input current
Low
High

VOLA
VOHA
IlL
IIH
lee

TEST CONDITIONS

-30·C
Min

Typ

+25·C
Max

Min

Typ

+8S·C
Max

Min

Typ

V
-1.890

-1.825.

-1.850
-0.890
-1.500

-1.205

-0.810
-1.475

-0.700
-1.440
-1.035

-:1.105

V
VIH
VIHA

= Max, VIL = Min

-1.89
-1.06

= Min; VILA = Max

-1.08

. VIL
VIH

-1.675
-0.89

-1.70
-0.89

-1.65 -1.825
-0.81 -0.89

-1.615
-0.70

-1.63

-1.595
-0.91

-0.98

pA

= Min
= Max

0.5
265
110

AC ELECTRICAL CHARACTERISTICS Vee
PARAMETER

-1.85
-0.96

-1.655

Power supply drain
current

145

mA

= 2V, RL = 50n to ground, -30·C S; TA S; 85·C, Vee = -3.2V
LIMITS
Typ

TO

FROM

Output
Output

Address
Chip enable

15
10

22
17

Output

Chip disable

10

17

Min

Max

Tee

ns

Disable time
Teo

94

UNIT

ns

Access time

TAA

t+
t-

UNIT

Max

Rise and fall time
Rise time (20-80010)
Fall time (20-80%)

ns
4.0
4.0

SmODliDS

10139-F,N

TEST LOAD CIRCUIT

VOLTAGE WAVEFORMS
ADDRESS ACCESS TIME

YCC1" VCC2
+2.0VDC

2.5/-1F

~

~ O.1JJ.F

ADDRESS

==*"

500,'0

t--TM--I

V OUT

OUTPUT

:'

----------~

'

SOn
A,

A,

A,

0,

A.

0,
DUT

PULSE GENERATOR

Inpul pulse condilions: Vo = 0.31V, V, = I .11V, I, = 2ns
120 10 80%1, If = 2ns 120 10 80%1

0,

A,

0,

CHIP ENABLE/DISABLE TIMES

O.

0,
0,
0,

CE

*,O.1/-LF
VEE

= -3.2VDC
Inpul pulse conditions: VQ=0.31V. V, = 1.11V, 1,=2ns
(20 10 80%1, If = 2ns (20 10 80%1

Inpul pulse: I. = 1_ = 2.0 - 0.2no (20 10 80%1

1. Dc and Be specifications apply after thermal equilibrium has been established, with transverse airflow
greater than 500 linear fUm;n.
2. For Be tests, all input and output cables to the scope are equal lengths of 50n coaxial cable. Wire
length should be < 1/4 inch from TPIN to input pin and TPOUT to output pin. A son termination to
ground is located in each scope input. Unused outputs are connected to a 50n resistor to ground.

3. Test procedures are shown for only 1 input or set of input condjtions. Other inputs are tested in the
same manner.

PROGRAMMING SYSTEMS SPECIFICATIONS

Vccp
Vccv

Power supply voltage
To program
To verify

Iccp

Programming supply current

VIH
VIL

Address voltage
High
Low

lop
tp

td
td1

TEST CONDITIONS

Min

LIMITS
Typ

Max

11.5
5.0

12.0
5.2

12.5
5.4

UNIT
V

250

Vcc = 12.0V

mA
V

4.6
1.0

4.0
0

Max time at Vcc = Vccp
Output programming .current
Output program pulse width
Output pulse rise time

3.75
0.5

Programming pulse delay'
Following Vcc change
Between output pulses

4.25

1.0
4.75
1.0
10

sec
mA
ms
IJ.s

ms
0.1
0.01

1.0
1.0

*Maximum is specified to minimize the amount of time Vee is at 12V.

SmnOliCS

E
w
E

•c:-..o

II

NOTES

PARAMETER

=
o

95

10139-F,N

PROGRAMMING PROCEDURE
The 10139 is shipped with.all bits at logical
low. To program logical high's, proceed as
follows:
1. Connect a 7.5kO resistor from each
output to ground. This prevents crosstalk
into unselected outputs during programming.
2. Connect pin 8 (VEE) to ground and pin 16
(Vee) to +5.2V.
3. Address the desired word location using
oto 1.0V for a logic low and 4.0 to 4.6Vfor
a logic high.
4. Raise Vee to 12V. Wait 100~ (min) for

settling. Maximum time at 12V is 1.0sec.
5. Apply a +4.25mA current pulse to the first
output to be programmed. Output pin
voltage will be approximately 1.2V above
Vee, and the 7.5kO resistor will take
1.75mA. Pulse duration is 0.5 to 1.0ms.
Other outputs may be programmed
sequentially using a delay of .01 to 1.0ms
between current pulses.
6. Return Vee to 5.2V and verify the word.
Repeat step 5 once only if any bit failed to
program.
7. Repeat steps 3, 4, 5 and 6 for all address
locations to be programmed.
8. Verify complete truth table.

TYPICAL FUSING PATH
+12V

I---------------~~­

I

----------,I

I

I

I

I
I

I

I

I

I

I

I

I

I

I

I

I

I
I

I
I
I
I
I
I

I

I

I
I

IL __ -..,. ______ _

96

-

4.25mA

________________ ...1I

sagnotics

7.5k

82S27-F

DESCRIPTION

FEATURES

The 82S27 is field programmable, which
means that custom patterns are immediately available by following the fusing procedure given in this data sheet. The standard
82S27 is supplied with all outputs at logical
low. Outputs are programmed to a logic
high level at any specified address byfusing
a Ni-Cr link matrix.

•
•
•
•
•
•
•

The device includes on-chip decoding, 2
chip enable inputs. and open collector outputs for ease of memory expansion.
The 82S27 is available in the commercial
temperature range (DoC to +75°C) and is
specified as N82S27, F.

PIN CONFIGURATION

Address access time: 40ns max
Power dissipation: 0.6mW/bit typ
Input loading: 1.6mA max
On-chip address decoding
No separate fusing pins
Unprogrammed outputs are low level
Fully TTL compatible

F PACKAGE"

=
o

APPLICATIONS
•
•
•
•
•
•
•

Proto typing/volume production
Sequential controllers
Microprogramming
Hardwired algorithms
Control store
Random logic
Code conversion

'F

~

E
w

Cerdip

E

BLOCK DIAGRAM
NI-Cr FUSE ARRAY
(1)

A~
•

Al

(0)

A,~

A,

0,

(7)
(4)

A)
A.
A
5

0(;)'~

'0-2!(1)

ADDRESS
BUFFER

1-32 DECODER

32X32
MATRIX

0,

0,

A.~

(15)

A,~

o.
(32)

Vee
GND

~
~

( ) =

1161
18)
Pin number

ABSOLUTE MAXIMUM RATINGS
PARAMETER
VCC
VIN
VOH
TA
TSTG

Supply voltage
Input voltage
Output voltage
High
Temperature range
Operating
Storage

RATING'
+7
+5.5

UNIT
Vdc
Vdc
Vdc

+5.5

o to +75

°C

-65 to +150

S!!)nl!tiCs

97

82S27 (0 C )

1024 BITBIPIHAR PROM (256X4)

82S27-F

DC ELECTRICAL CHARACTERISTICS

O°C:S TA:S +75°C, 4.75V:S Vee:S 5.25V
LIMITS

PARAMETER

UNIT

TEST CONDITIONSl

Typ2

Min

Max

Vil
VIH
VIC

Input voltage
Low
High
Clamp

hN = -12mA

-1.0

-1.5

VOL

Output voltage
Low

lOUT = 32m A

0.45

0.50

hl
hH

Input current
Low
High

IOlK
CIN
COUT

V
.80
2.0
V

VIN = 0.50V
VIN = 2.4V
VIN = 5.5V

-1.6
40
1

Output current
Leakage

CEl or CE2 = High, VOUT = 5.5V

100

Capacitance
Input
Output

Vee = 5.0V
VIN = 2.0V
VOUT = 2.0V, CEl or CE2 = High

mA
,.,.A
mA
,.,.A

AC ELECTRICAL CHARACTERISTICS

pF
5
8

O°C:S TA:S +75°C, 4.7SV:S Vee :SS.2SV, Rl = 270n, R2=600n, Cl =30pF
LIMITS

PARAMETER

TO

FROM

Min

Typ2

Max

Access time

UNIT
ns

TAA
TeE

Output
Output

Address
Chip enable

30
15

40
20

Output

Chip disable

15

20

Disable time

ns

Teo
NOTES

1. Positive current is defined as into the terminal referenced.
2. Typical values are at Vee = S.OV, TA =:: 25 0 C.

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM

Vee
, -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ·3.0V
~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OV

0 - - A,

Vee

o--A,

,----+3.0V
1.SV

'--__-:--______-'+_ -- - -

0 - - A,
0 - - A,
0 - - A.

0,
OUT

0,

0 - - A,

0,

0 - - A,

0.

R,
1.5V

R2

o--A,

0 - - CE1

I

CL (INCLUDES SCOPE &
JIG CAPACITANCE)

All inputs: tr '= Tf = 5ns (10% to 90%)

0 - - CE2
GND

':'

98

Smnlltics

ov

PROGRAMMING SYSTEMS SPECIFICATIONS (Testing of these limits may cause programming of device.> TA = +25°C
LIMITS
PARAMETER

TEST CONDITIONS

Min

Typ

Max

Vccp

Power supply voltage
To program 1

VCCH
VCCL

Verify limit
Upper
Lower

5.0
4.5

5.25
4.75

5.5
5.0

Vs

Verify threshold2

0.9

1.0

1.1

VIH
VIL
VIN

Input voltage
High (except CEl)
Low
Program level (CE1 only)

3.0
0
14.0

0.4
14.5

5.0
0.5
15.0

hH
IlL
hN

Input current
High
Low
Program level (CE1 only)

VOUT

Output programming voltage:!

lOUT
TR
tp
to
TPR
Tps
TPR
TPR + Tps

Output programming current
Output pulse rise time4
Programming pulse width
Pulse sequence delay
Programming time
Programming pause

UNIT

V

Iccp = 300 ± 50mA,
Transient or steady state

5.25

5.0

=
o
.....
..o•-

V

V

E
1M
E
c:

V

VIH = +3.0V
VIL = +0.5V
VIN = +15.0V
lOUT = 115 ± 10mA,
Transient or steady state
VOUT = +17.0 ± 0.5V

100
-1.6
15

p.A
mA
mA

16.5

17.0

17.5

V

105
0.2
0.25
10

115

125
0.5
0.5

mA

Vcc = Vccp
Vcc = OV

Programming duty cycleS

12
6
50

p'S

ms
P.s
sec
sec
%

NOTES
1. Bypass Vee to GND with a 0.01 ~F capacitor to reduce voltage spikes.
2. Vs i. the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes
the reference voltage applied to a comparator circuit to verify a successful fusing attempt.
3. Care should be taken to insure the 17 ± O.5V output voltage is maintained during the entire fusing
cycle. The recommended supply is a constant current source clamped at the specified voltage-limit.
4. Measured with a 1K dummy load connected across the fusing source.
5. Continuous fusing for an unlimited time is also allowed. provided that a 5O!!I> dutycycie is maintained.
This may be accomplished by following each Program Verify cycle with a rest period (Vee = OVI of
O.Sms.

PROGRAMMING PROCEDURE

Program-Verify Sequence

The 82827 is shipped with all bits at logical
low. To write logical high, proceed as folloiNs:

1. Raise Vcc to Vccp, and address the word
to be programmed by applying TTL high
and low logic levels to the device address
inputs.
2. After 10p.s delay, apply to CE1 (pin 13) a
voltage source of 14.5 ± 0.5V, with 15mA
sourcing current capability.
3. After 10p.s delay, apply a voltage source
of +17.0 ± 0.5V to the output to be programmed. The source must have a current limit of 115mA. Prgram one output at
the time.
4. After 10p.s delay, remove +17.0V supply
from programmed output.

Set-up
1. Apply GND to pin 12.
2. Terminate all device outputs with a 10kO
resistor to Vcc.
3. Set CE2 to logic low.

SjgOOliCS

5. To verify programming, after 1Op.s delay,
return CEl to OV. Raise Vcc to VCCH =
+5.25 ± .25V. The programmed output
should remain in the high state. Again,
lower Vcc to VCCL = +4.75 ± .25V, and
verify that the programmed output remains in the high state.
.6. Raise Vcc to Vccp, and repeat steps 2
through 5 to program other bits at the
same address.
7. Repeat steps 1 through 6 to program all
other address locations.

99

82S27-F

TYPICAL FUSING PATH
CE1

1------..,
I
I

I
I

I
I
I

Y ADDRESS
(10'3)

I

I
I
I

./~_+----~I_?(~

'-~----~

r---

I

I
I

I
I

I
I
I
I
I
I
I

I
OUTPUT

CE

TYPICAL PROGRAMMING SEQUENCE

A~:'11

I

"::; J

I

OV

-I'

I'm

F RST
A •
TpR-(PROGRAM)

O /-

A

LAST

I ===[==~
IL1 60 SEC. MIN

12 SEC. MAX
•

TPS~(PAUSE)

"~O:r.:...-;;:--------.fILst-----------nl'
~ --~VERIFY·
I
I~
r-----,
I
L-~ _____ J
L___
J
"'1---___. .r-,

1l-·

"4.5V-r--I

C:~---1

.17.0v--i]

OUTPUT

.

90%

VOLTAGE
OV

B.

-

.

'o-1!-'p-1

;-=1
1-'0 I
L.__
L.___ _______
L... _ _ _ _ _

0 '--'.
I

TR

____ J

"

I

8N·1

8N

I'

I.

-11-'0
.

!

I
I

-j'

I

.

II

""Programming verification at both high and low Vee margins is optional. For convenience, verification
can also be executed at the operating Vee limits specified in the de characteristics.

100

Gi!lnDtiCG

"1 t-·O

-1!-.0

L.. _ _ _ _ _ _ _J

828126 (0 C) 828129 IT S )

m24 BITBIPOlARPROM (256X4)

828126-F.N .828129-F.N

DESCRIPTION

FEATURES

The 828126 and 828129 are field programmable, which means that custom patterns
are immediately available by following the
fusing procedure given in this data sheet.
The standard 828126 and 828129 devices
are supplied with all outputs at logical low.
Outputs are programmed to a logic high
level at any specified address by fusing a NiCr link matrix.
.

• Address access time:
N82S126/129: SOns max
S82S126/129: 70ns max
• Ppwer dissipation: 0.5mW/bit typ
• Input loading:
N82S126/129: -100,uA max
S82S126/129: -150,uA max
• On-chip address decoding
• Output options:
82S126: Open collector
82S129: Tri-state
• No separate fusing pins
• Unprogrammed outputs are low level
• Fully TTL compatible

These devices include on-chip decoding
and 2 chip enable inputs for ease of memory
expansion. They feature either open collector or tri-state outputs for optimization of
word expansion in bused organizations.
Both 828126 and 828129 devices are
available in the commercial and military
temperature ranges. For the commercial
temperature range (DoC to +75°C) specify
N828126/129, For N. and for the military
temperature range I-55° C to +125°C) specify 8828126/129. F only.

PIN CONFIGURATION

APPLICATIONS
•
•
•
•
•
•
•

F,N PACKAGE"

=
o
*F

= Cerdip

N

= Plastic

E
w

E

Prototypinglvolume production
Sequential controllers
Microprogramming
Hardwired algorithms
Control $tore
Random logic
Code conversion

•a:
...tIl

oe.

-

BLOCK DIAGRAM
NI-Cr FUSE ARRAY

II

A,
A,
A,
A,
32X32

A.
A,

MATRIX

A,

ABSOLUTE MAXIMUM RATINGS
PARAMETER

Vee
VIN
VaH
Va
TA

TSTG

8upply voltage
Input voltage
Output voltage
High (828126)
Off-state (828129)
Temperature range
Operating
N828126/129
8828126/129
8torage

RATING

UNIT

+7
+5.5

Vdc
Vdc
Vdc

+5.5
+5.5
°C

o to +75
-55 to +125
-65 to +150

Si~nDtiC!i

101

825126(0 C ) 829129 (l S )

1024 81T 81 POEAR PROM (256X4)

828126-F,N .828129-F,N

DC ELECTRICAL CHARACTERISTICS

N828126/129: O°C:S TA:S +75°C, 4.75V:S Vee:S 5.25V
8828126/129: -55°C:S TA:S + 125°C, 4.5V:S Vee:S 5.5V

N825126/129

TE5T CONDITION5 1

PARAMETER

Min
VIL
VIH
Vie

Input voltage
Low
High
Clamp

VOL
VOH

Output voltage
Low
High (828129)

IlL
IiH

Input current
Low
High

10LK
10(OFF)

Output cu rrent
Leakage (828126)
H i-Z state (828129)

Max

Min

Typ2

UNIT

Max
V

.85
2.0
liN = -18mA

.80
2.0

-1.2

-0.8

-0.8

-1.2
V

lOUT = 16mA
CEl = CE2 = Low, lOUT = -2.0mA,
High stored

0.45
2.4

0.5
2.4
/LA

8hort circuit (828129)

los

Typ2

5825126/129

lee

Vee supply current

CIN
COUT

Capacitance
Input
Output

VIN = 0.45V
VIN = 5.5V

-100
40

-150
50

CEl or CE2 = High, VOUT = 5.5V
CEl or CE2 = High, VOUT = 5.5V
CEl or CE2 = High, VOUT = 0.5V
VOUT = OV

40
40
-40
-70

60
60
-60
-85

mA

125

mA

-20
105

Vee = 5.0V
VIN = 2.0V
VOUT = 2.0V

AC ELECTRICAL CHARACTERISTICS

-15

120

105

/LA
/LA

pF
5
8

5
8

Rl = 270n, R2 = 600n, CL = 30pF
N828126/129: O°C:s TA:S +75°C, 4.75V:S Vee:S 5.25V .
8828126/129: -55°C:s TA :S+125°C, 4.5V:S Vee:S 5.5V

PARAMETER

TO

FROM

N825126/129

Min

Typ2

Max

5825126/129

Min

Typ2

Max

UNIT
ns

Access time
TAA
TeE

Output
Output

Address
Chip enable

35
15

50
25

35
15

70
35

Output

Chip disable

15

25

15

35

ns

Disable time
TeD
NOTES
1. Positive current is defined as into the terminal referenced.
2. Typical values are at Vee = 5.0V, T A = +25 0 C.

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM

Vee

~-----~---------+3,OV

Vee

~----------------OV

,-------'3.0V

R,

1.5V

~----~-----4---------0V
TCD

(INCLUDES SCOPE &
JIG CAPACITANCE)

102

S!!IDl!tiCS

-+----""- -------------------------- 1,5V

VOH

S2S Oil

1d24 iii I iilPDUtl PRDIli (256](4)

('"

)

SiB129 (I S I

82S126-F,N .82S129-F,N

PROGRAMMING .SYSTEM SPECIFICATIONS

(Testing of these limits may cause programming of device.) TA = +25°C

LIMITS
PARAMETER

UNIT

TEST CONDITIONS
Min

Typ

Max

8.5

8.75

9.0

V

Vccp

Power supply voltage
To program'

VCCH
VCCL

Verify limit
Upper
Lower

5.3
4.3

5.5
4.5

5.7
4.7

Vs

Verify threshold 2

1.4

1.5

1.6

V

Iccp

Programming supply current

300

450

mA

VIH
VIL

Input voltage
High
Low

2.4
0

5.5
0.8

IIH
IlL

Input current
High
Low

VOUT

Output programming voltage3

Iccp = 375 ± 75mA,
Transient or steady state

=
o

V

Vccp = +8.75 ± .25V

E
w
E
c:

V
0.4

•...
o

pA
VIH = +5.5V
VIL = +0.4V
lOUT = 200 ± 20mA,
or steady state

50
-500
16.0

17.0

18.0

V

180

200

220

mA

50
0.5

liS
ms

12

liS
sec

..-

Tran~ient

VOUT = +17 ± 1V

lOUT

Output programming current

TR

Output pulse rise time

10

tp

CE programming pulse width

0.3

tD

Pulse sequence delay

10

TPR

Programming time

TpSI

Initial programming pause

TPR

Vcc = Vccp
Vcc = OV

0.4

II

sec

6

-TPR+Tps

Programming duty cycle4

50

%

FL

Fusing attempts per link

2

cycle

NOTES
1. Bypass Vee to GND with a O.OlIlF capacitor to reduce voltage spikes.

2. Vs is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes
the reference Yoltage applied to a comparator circuit to verify a successful fusing attempt.
3. Care should be taken to insure the 17 ± lV output voltage is maintained during theentirefusing cycle.
The recommended supply is a constant current source clamped at the specified voltage limit.
4. Programming duty cycle is 50% after continuous programming at 100% duty cycle.
5. This is an updated method of programming and does not obsolete any programming systems
presently being used.

PROGRAMMING PROCEDURE
1. Terminate all device outputs with a 10kO
resistor to Vce. Apply CE, = High, CE2 =
Low.
2. Select the Address to be programmed,
and raise Vcc to Vccp = 8.75 ± .25V.
3. After 10l's delay, apply VOUT = +17 ± 1V
to the output to be programmed. Program one output at the time.

4. After 10l'S delay, pulse the CE, input to
logic low for 0.3 to 0.5ms.
5. After 10l's delay, remove +17V from the
programmed output.
6. To verify programming, after 10l's delay,
lower V cc to VCCH = +5.5 ± .2V, and apply
a logic low level to the CE input. The
programmed output should remain in the
high state. Again, lower Vccto VCCL =

9~nDtic9

+4.5 ± .2V, and verify that the programmed output remains in the high
state.
7. Raise Vcc to Vccp = 8.75 ± .25V, and
repeat steps 3 through 6 to program other
bits at the same address.
8. After 10l's delay, repeat steps 2 through 7
to program all other address locations.

103

]024 BIT BIPOLAR PROM (256X4)

828126 (0 C ) 82&129

n S)

82S126-F,N .82S129-F,N

TYPICAL PROGRAMMING SEQUENCE

","

,",~r----------------------:-..,..------------..,'-

A LAST

ADD
"0"

"""t---------:;:;;;;-:;;;;;;;;;;:;:;;-II----~

Vee
OV

OUTPUT

VOLTAGE

OV

"1"

eE1
"0"

*Programming verification at both high and low Vee margins is optional. For convenience verification
can also be executed at the operating Vee limits specified in the de characteristics.

104

HU49

1024 BIT ECL PROM (25614)

10149-F

DESCRIPTION

APPLICATIONS

The 10149 is field programmable, meaning
that custom patterns are immediately available by following the fusing procedure given in this data sheet. The standard device is
supplied with all outputs at logical low.
Outputs are programmed to a logic high
level at any specified address by fusing a NiCr link matrix.

•
•
•
•
•
•

The 10149 is suitable for use in high performance ECl systems. The outputs are capable of driving 5000 loads.
A chip enable input is provided for ease of
memory expansion.

PIN CONFIGURATION

Sequential controllers
Microprogramming
Hardwired algorithms
Control store
Random logic
Code conversion

F PACKAGE"

=
o

RECOMMENDED OPERATING
RANGES
• VCC1 = VCC2 = GND
• VEE = -5.2V ± 5%
• T A = -30·Cto +85·C ambient

E
w

"F = Cerdip

FEATURES
•
•
•
•
•
•
•

Address access time: 20ns max
Power dissipation: 0.66mW/bit typ
High impedance Inputs (50kO pulldown)
Open emitter outputs (50kO drive)
On-chip address decoding
No separate fusing pins
Fully compatible with ECl 10K series

E
c:
..,

•

BLOCK DIAGRAM
NI-CR FUSE ARRAV
A,

A,

...
A.

A.

A.

A,

o&.

(2)

•-

(3)

(4)

X
DeCODE

32X32
STORAGE MATRIX

1 OF 32

(5)

(10)

(S)

m

y

DECOOE
10F.

A,

CE

(.)
(13)

O.

0,

0,

0,

ABSOLUTE MAXIMUM RATINGS

Vee
VIN
10
TA
TJ
TSTG

PARAMETER1

RATING

UNIT

Supply voltage (Vee = Ol
Input voltage (Vee = 0)
Output source current
Temperatl.Jre range
Operating
Operating junction
Storage

8
o to Vee
40

Vdc
Vdc
mAdc
·C

SmootiCS

-30 to +85
125
-55 to +125

105

1024811 ECl PROM (25614)

10149
10149-F

DC ELECTRICAL CHARACTERISTICS
PARAMETER1

VCC1 = VCC2 = OV, VeE = ~5.2V, Rl == 50n to -2V
'-30°C

TEST CONDITIONS
Min

Vil
VIH
VilA
VIHA

Input voltage2,3
Low
High
Low threshOld
High threshold

Val
VOH

Output voltage
Low
High

VOLA
VOHA

Max

Min

Typ

Max

Min

Typ

UNIT
Max

V
-1.890

-1.850
-0.890
-1.500,

-1,205

-1,825
-0.810
-1.475

-1:105

-0.700
-1.440
-1.035
V

-1,89
-1.06

VIH = max
Vil = min

Low threshold
High threshold

VIHA = min, VilA = max

hl
hH

Input current
Low
High

lEE

Supply drain current

~1.675

~1.85

-0.89

-0.96

-1.70
-0,89

-1.655
-1.08

-1.65
-0.81

-1,825
-0.89

-1.63
-0.98

-1.615
-0.70
-1.595

-0.91
/lA

VIH = max
Vil = min

0.5
265

,,',

130

AC ELECTRICAL CHARACTERISTICS TA = +25°C, VEE = -3.2V,
VeC1 =VCC2 = 2V, Rl = 50n to ground
LIMITS

PARAMETER

TO

FROM

Output
Output
Output

UNIT
Min

Typ

Max

Address
Chip enable

12
5.5

20
8

Chip disable

5.5

8

Access time

ns

TAA
TCE
TCD

Disable time

t+
t-

Rise and fall time
Rise time (20-80%)
Fall time (20-80%)

ns
ns

I

4.0
4.0

NOTES
"

1. All voltage measurer:nents are referenced-to the groun:d terminal. Terminals not
specifically referenced are left e1e:ctrically open.
2, Vdc ± 1%.
3. Each Eel 10K series device has
designed'tel meet 'the de specification after
thermal equilibrium has been estabHshed. The circuH is in a test socket or mounted or
a printed circuit board and transverse air flow greater than 500 linear fpm is
maintained. Voltage 'levels will shift approximately 4rrlV with an air flow of 200 linear
1pm. Outputs are terminated through-s 50.0 resistor to -2V.

been

106

+85°C

+25°C

Typ

HillBllties

150

mA

10149

1024 BIT ECL PROM (256X4)

10149-F

TEST LOAD CIRCUIT
VCC1 = VCC2
+2.0YDC

=
o

YOUT

50

PULSE GENERATOR

n

E
w
E

OUT

INPUT PULSE
t + -I = 2.0 -0.2n8
(20% TO 80%)

*,O.'J..1.F
VEE'" -3.2VDC

NOTES
A. For ae tests. all input and output cables to the scope are eq uallengths of 50n coaxial
cable. Wire length should be < 1/4 inch from TP1N to input pin and TPOUTto output pin.
A son termination to ground is located in each scope input. Unused outputs are
connected to a 50n resistor to ground.
B. Test procedures are shown for only one input or set 01 input conditions. Other inputs
are tested in the same manner.
C. Normal practice in test fixtures layout should be followed. Lead lengths, particularly to
the power supply, should be as short as possible. A 1QJ..IF capacitor between Vee, and
Vee terminals, located as close to the device as possible, is recommended to reduce
ringing.

VOLTAGE WAVEFORMS
ADDRESS ACCESS TIME

. ,:q-------------------=~~:*\------0 1 -4

,-----------

CHIP ENABLE/DISABLE
PROPAGATION DELAYS

9i!JDOliC9

107

10149

1024611 ECL PROM (25614)

10149-F

PROGRAMMING SPECIFICATIONS

(Testing of these limits may cause programming of device.) TA = +25°C
LIMITS

PARAMETER

VEE
VCC1p
VCC1v

TEST CONDITIONS

Power supply voltage
Programlverify
To program
To verify

UNIT

Min

Typ

Max

See steps 4 and 8 in Programming Procedure

-5.46
5.7

-5.2
6.0
0

-4.94
6.3

VEE = -5.2V
Vce1 = 6.0V

300
150

V

mA

Programming supply current
IEEP
Icc1p

V

Input voltage
High
Low

VIH
VIL
VOUT
VVOUT
tp

Output voltage
Programming
Verify 1
Verify 0

lOUT

-.75
-1.80

-0.60
-1.60

1.50
-1.0

1.70

1.90
-1.50

V

= 4.0mA

.25

Output programming
pulse width
Pulse sequence delay
Programming time
Programming pause

tD
TpR
Tps

-0.90
-2.0

.5

ms

6

,"s
sec
sec

100
Vee1 = +6V
VCC1 = VCC2 = VEE

TYPICAL PROGRAMMING SEQUENCE

= OV

6

TYPICAL FUSING PATH

r-"_---_------_-u
PROGRAM

+sv

+1.7V PULSE

+6.0V

I

+1.TV
PROGRAM MING
VOLTAGE
OPEN

\

I
7:5K

...e;: 1--100~s

...::::

MIN.

I

100.us
MIN.

\
O.5ms MAX.

"

ReXT

c---1

PROGRAMMING PROCEDURE
The 10149 is shipped with all bits at logical
low. To write logical high, proceed as follows:
1. Terminate all device outputs with
7.5kO to -5.2V.
2. Connect VEE (pin 8) to -5.2V ± 5% and
VCC2 (pin 16) to GND (OVl.
3. Address the desired location byapplying a voltage of -.75 ± .15V for a high
and a voltage of -1.80 ± .20V for a low at
the address inputs.
4. Apply +6.0V ± 5% to VCC1 (pin 1).
5. Allow a minimum delay of 100,"5 and
apply a voltage of +1.7V ± 0.2V to the

108

V CC1 =

VERIFY

6.

7.

8.
9.

10.

-5.2V

output to be programmed. Program
one output at a time.
Hold the output programming voltage
for 0.25 to 0.5ms, and then di.sconnect
the voltage source from the programmed output.
.
.
Allow a minimum delay of 100,"s and
then reduce Vce1 to GND (OV) to verify
programmed output.
Repeat steps 4 through 7 to prog ram
other bits of the word.
Change the address and repeat steps 4
through 8 until the entire bit pattern is
programmed into your custom 10149.
Verify complete. truth table.

GjgnDtiCG

2048 BIT BIPOUlR PROM (256X8)
4096 Hit HI POLAR PROM (51218)

828114 (I S )

825115 (F S )
82S114-F,N .82S115-F,N

DESCRIPTION
The 82S114 and 82S115 are field programmable and include on-chip decoding and 2
chip enable inputs for ease of memory expansion. They feature tri-state outputs for
optimization of word expansion in bused
organ izations. A D-type latch is used to
enable the tri-state output drivers. In the
Transparent Read mode, stored data is addressed by applying a binary code to the
address inputs while holding Strobe high. In
this mode the bit drivers will be controlled
solely by CE1 and CE2 lines.
In the Latched Read mode, outputs are held
in their previous state (high, low, or high Z)
as long as Strobe is low, regardless of the
state of address or chip enable. A positive
Strobe transition causes data from the. applied address to reach the outputs if the chip
is enabled, and causes outputs to go to the
high Z state if the chip is disabled.

FEATURES

PIN CONFIGURATIONS

• Address access time:
N825114/115: 60ns max
5825114/115: 90ns max
• Power dissipation: 1651'W/bit typ
• Input loading:
N825114/115: -100IlA max
5825114/115: -150I'A max
• On-Chip storage latches
• Schottky clamped
• Fully compatible with 5ignetics 825214
and 825215 ROMs
• Fully TTL compatible

F,N PACKAGE
825114

Ne

=
o

A,

STROBE

E
w
E

APPLICATIONS
•
•
•
•
•

Microprogramming
Hardwire algorithms
Character generation
Control store
Sequential controllers

aND

•a:

FE,

F,N PACKAGE
825115

A negative Strobe transition causes outputs
to be locked into their last Read Data condition if the chip was enabled, or causes
outputs to be locked into the high Z condition if the chip was disabled.

.",

A,

Vcc

A,

A,

oe.

--=

A,

A,

Both 82S114 and 82S115 devices are available in the commercial and military temperature ranges. For the commercial temperature range (DOC to +75°C) specify
N82S114/115, F or N, and for the military
temperature range (-55° C to+125° C) specify S82S114/115, F.

A.
CE,

A,

CE,

0,

STROBE

0,

0,

0,

0,

0,

0,

FE,

0,

GNO

FE,

BLOCK DIAGRAM

A, U----''-------~

(18)

STROBE o----------....-----1~

CE,

Q

LATCH

CE,

FE1

8·BIT OUTPUT LATCH

= 1131, FE2 = 1111

8 TRI-STATE DRIVERS

OUTPUT LINES

Vec = 1241. GNO = 1121, 1 1 = Pin Number

SjgDl!tiCS

109

111111111111111111 1II1II
82S114-F,N • 82S115-F,N

ABSOLUTE MAXIMUM RATINGS
PARAMETER

Vee
VIN
TA

Supply voltage
' Input voltage
Temperature range
Operating

UNIT

+7
+5.5

Vdc
Vdc
°C

o to +75
-55 to +125
-65 to +150

N82S114/115
S82S114/115

Storage

TSTG

RATING

DC ELECTRICAL CHARACTERISTICS

N82S114/115:
S82S114/115:

0° C ::;TA ::; +75° C, 4.75V :5 Vee::; 5.25V
-55°C <
- TA::; +125°C, 4.5V <- Vee <- 5 5V
N82S114/115

PARAMETER

VIL
VIH
Vie

Input voltage
Low
High
Clamp

VOL
VOH

Output voltage
Low
High

IlL
IIH

Input current
Low
High

10(OFF)

Output current
Hi-Z state

TEST CONDITIONS

S82S114/115

Typl Max

Typl Max

Min

UNIT

V
.85

.8
2.0

2.0

'.

liN = -18mA

-0.8

-1.2

-0.8

-1.2

lOUT = 9.6mA
CEl = Low, CE2 = High,
lOUT = -2mA, High stored

0.4
3.3

0.45

0.4
3.3

0.5

V
2.7

2.4

p.A

Short circuit2

los

Min

lee

Vee supply current

CIN
COUT

Capacitance
Input
Output

VIN = 0.45V
VIN = 5.5V

-100
25

-150
50

CEl =HighorCE2=O, VouT=5.5V
CEl =HighorCE2=O, VouT=0.5V
VOUT= OV

40
-40
-70

100
-100
-85

mA

185

mA

.,

-20
130

-15

175

130

p.A

pF

Vee = 5.0V, VIN = 2.0V
Vee = 5.0V, VOUT = 2.0V
-oEl = High or CE2= 0

5

5

8

8

AC ELECTRICAL CHARACTERISTI,CS Rl = 4700, R2 = 1kO, CL = 30pF
N82S114/115: 0° ::; TA::; +75°C, 4.75V::; Vee::; 5.25V
S82S114/115: -55°C :5 TA:5 +125°C, 4.5V:5 Vee:5 5.5V

PARAMETER

TO

FROM

Min

..

Output
Setup and hold time4
Setup time
Output
Hold time
Hold time

Output Address
Latched read only

Latch time4
Strobe

Latched read only

TSL

Delatch time4
Strobe

Latched read only

TOL

110

90
50

40

20

50

60

20
Latched read only

Chip
enable

Pulse width4
Strobe

page.

40

35
20

35
20

ns

Cnip
disable

Tsw

NOTES on following

Max

Min

Latched or transparent read

Disable time3

TAOH

UNIT

Typl

Max

ns

Output Address
Chip
Output
enable

Teo

S82S114/115

Typl

Latched or transparent read

Access time3
TAA
TeE

Teos
TeoH

N82S114/115

TEST CONDITIONS

ns
40
10
0

0

50
10

0

-10

5

-10

30

20

40

20

60

35

90

35

ns
ns
ns
30

.'

s;,gnotiCs

35

,
l
82S114-F,N .82S115-F,N
NOTES

1. Typical values are at Vee = +S.OV and TA = +25°C.
2. No more than one output should be grounded at the same time and strobe should be disabled. Strobe
is in high state.
3. If the strobe is high, the device functions in a manner identical to conventional bipolar ROMs. The
timing diagram shows valid data will appear TA nanoseconds after the address has changed the T CE
nanoseconds after the output circuit is enabled. Teo is the time required to disable the output and
switch it to an off or high impedance state after it has been enabled.
4. In Latched Read Mode data from any selected address will be held on the output when strobe is
lowered. Only when strobe is raised will new location data be transferred and chip enable conditions
be stored. The new data will appear on the outputs if the chip enable conditions enable the outputs.
5. During operation the fusing pins FE1 and FE2 may be grounded or left floating.
6. Positive current is defined as into the terminal referenced.

=
o

VOLTAGE WAVEFORM

TEST LOAD CIRCUIT
Vcc

E
w
E
a:

INPUT PULSES
Vcc

~

•...
o

Ji!;;%
10%

R,

il

(INCLUDES JIG &
SCOPE CAPACITANCE)

5n,

=.b

'30V

ov------- -

.-.
e.

90%

5n5-

-5n5

TIMING DIAGRAMS
TRANSPARENT READ4
,.

LATCHED READS
+3.0V

+3.0V

STROBE,'
- - - - ' - - - - - - - - - - - - - - - - - - - - - --OV
~~5~-- - - - - - - - - - - - - - - - - - - --+3.0V

GE,

'-------------------------ov
C;;;;E~,____I_--""',.--------""'_.,.--------+3.0V
'--------ov

CHIP ENABLE

+3.0V

OV

CE,

1.5V

STROBE

OV

CE,

0, .. 'Oe

VO"

0,. .. 0 8

Output Latches Used

Output Latches Not Used

SmDotiCS

111

Ille 11111111111'11111111111_1iii_liiiil;lllnllll~lJIIil
82S114-F,N· a2S115-F,N

PROGRAMMING SYSTEMS SPECIFICATIONS (Testing of these limits may cause programming of device.) TA = +25°C
PARAMETER

Vccp

Power supply voltage
To program 1

VCCH
VCCL

Verify limit
Upper
Lower

Vs
Iccp

Verify threshold2
Programming supply current

VIL
VIH

Input voltage
Low
High

ilL
IIH

Input current (FEI & FE2 only)
Low
High

ilL
IIH
VOUT
lOUT
TR
tp
To
TPR
Tps
TPR
TPR+Tps

LIMITS

TEST CONDITIONS

UNIT

Min

Typ

Max

4.75

5.0

5.i15

5.3
4.3

5:5
4.5

5.7
4.7

0.9
175

1.0
200

1.1
225

0
2.4

0.4

0.8
5.5

V
Iccp = 200 ± 25niA,
Transient or steady state

.

Vccp = +5.0 ± .25V

V

V
rnA
V

Input current (except FEI & FE2)
Low
High
. Output programming voltage 3
Output programming current
Output pulse rise time
FE2 programming pulse width
Pulse sequence delay
Programming time
Programming pause

VIL = +0.45V
VIH = +5.5V

-100
10

VIL = +0.45V
VIH = +S.5V

-100
25
18.0

p,A
mA
p,A

lOUT - 200 ± 20mA,
Transient or steady state
VOUT = +17 ± 1Y

Vcc = Vccp
Vcc =ov

Programming duty cycle4

16.0

17.0

180
10
0.3
10

200
0.4

220
50
0.5
12

6
50

V
mA
p,s
ms
p,s
sec
sec
%

NOTES
1. Bypass vee to GND with a 0.01 ~F capacitor to reduce voltage spikes.
2. Vs Is the sensing threshold of the PROM output voltage for a programmed btt.lt norma.lly constitutes
the reference voltage applied to a comparator circuit to verity a sl:Jccessful fusing attempt.
3. Care should be taken to insure the 17 ± 1Voutput voltage is maIntained during theentire fusing cycle.
4. Continuous fusing for an unlim~ted time is also allowed, provided thata60%dutycycleis maintained.
This may be accomplished by following ea~h Program-Verify cycle with a Rest period (Vee =OVI of
3ms.

RECOMMENDED
PROGRAMMING PROCEDURE
The 82S114/115 are shipped with al.1 bits at
logical low. To write logical high, proceed
as follows:
SET-UP
1. Apply GND to pin 12.
2. Terminate all device outputs with a 10kO
resistor to Vcc.
3. Set CEI to logic low, and CE2 to logic
high (TTL levels),
4. Set Strobe to logic high level.

Program-Verify Sequence
1. Raise Vcc to Vccp, and address the word
to be programmed by applying TTL high
and low logic levels to the device address
inputs.
2. After 10ILS delay, apply to FEI (pin 13) a
voltage source of +5.0± 0.5V, with 10mA

112

sourcing current capability.
3. After 10p,s delay, apply a voltage source
of +17.0 ± 1.0V to the output to be pro~
grammed. The source must have a current limit 2oomA. Program on output at
the time.
4. After 10p,s delay, raise FE2 (pin 11) from
OV to +5.0 ± 0.5V for a period of 1ms, and
then return to OV. Pulse source must have
a 10mA sourcing current capability.
5. After 10p,s delay, remove +17.0V supply
from programmed output.
6. To verify programming, after 1OILS delay,
return FEI to OV. Raise Vcc to VCCH =
+5.5 ± .2V. The programmed output
should remain in the high state. Again,
10werVcc to VCCL =+4.5± .2V, and verify
that the programmed output remains in
the high state.
7. Raise Vcc to Vccp and repeat steps 2
through 6 to program other bits at the

SmDOliCS

same address.
8. Repeat steps 1 throUgh 7 to program all
other address locations.

82S114-F,N .82S115-F,N

TYPICAL PROGRAMMING SEQUENCE

. ,".,.".;",...-----------------'r.:>;r-----------,

ADD
"0" ""'""'!-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

=

o
E
w

E
..:

OUTPUT
VOLTAGE

...o
c:

..•-

*Programming verification at both high and low Vee margins is optional. For convenience, verification
can also be executed at the operating Vee limits specified in the de characteristics.

G~nDtiCG

113

2048 BIT BIPOLAR PROM (51214)

82S130 (0 C) 828131 (I S)
828130-F,N .828131-F,N

DESCRIPTION

FEATURES

The 828130 and 828131 are field programmable, which means that custom patterns
are immediately available by following the
fusing procedure given in this data sheet.
The standard 828130 and 828131 are supplied with all outputs at logical low. Outputs
are programmed to a logic high level at any
specified address by fusing a Ni-Cr link
matrix.

• Address access time:
N82S130/131: SOns max
S82S130/131: 70ns max
• Power dissipation: 0.3mW/bit typ
• Input loading:
N82S130/131: -100~A max
S82S130/131: -1S0~A max
• On-chip address decoding
• Output options:
82S130: Open collector
82S131: Tri-state
• No separate fusing pins
• Unprogrammed outputs are low level
• Fully TTL compatible

These devices include on-chip decoding
and 1 chip enable input for ease of memory
expansion. They feature either open collector or tri-state outputs for optimization of
word expansion in bused organizations.
Both 828130 and 828131 devices are available in the comr(lercial and military temperature ranges. For the commercial temperature range (0° to +75°C) specify
N828130/131 , F or N, and for the military
temperature range (-55°C to +125° C) specify 8828130/131, F.

PIN CONFIGURATION

OF
N

APPLICATIONS
•
•
•
•
•
•
•

Prototyping/volume production
Sequential controllers
Microprogramming
Hardwired algorithms
Control store
Random logic
Code conversion

BLOCK DIAGRAM
NI-Cr FUSE ARRAY

111

32X16

32X16

--------

1:32 DECODER

32X16

13_1

32X16

ABSOLUTE MAXIMUM RATINGS
PARAMETER

Vee
VIN
VOH
Vo
TA

TSTG

114

8upply voltage
I nput voltage
Output voltage
High (828130)
Off-state (828131)
Temperature range
Operating
N828130/131
8828130/131
8torage

RATING

UNIT

+7
+5.5

Vdc
Vdc
Vdc

+5.5
+5.5
°C

o to +75
-55 to +125
-65 to +150

9~nDbC9

F,N PACKAGE'

= Cerdip
= Plastic

828130 (II

2048 BII BIPOLAR PROM (512)(4)

Ii )

828131 (I S )

828130-F,N .828131-F,N

DC ELECTRICAL CHARACTERISTICS

N828130/131:
8828130/131:

O°C:5 TA:5 +75°C, 4.75V:5 Vcc:5 5.25V
-55°C:5 TA:5 +125°C,,4.5V:5 Vcc:5 5.5V

N82S130/131
PARAMETER

Vil
VIH
VIC

I nput voltage
Low
High
Clamp

VOL
VOH

Output voltage
Low
High (8281311

ill
IIH

Input current
Low
High

10lK
10(OFFI

Output current
Leakage (828130)
H i-Z state (8281311

TEST CONDITIONS

Icc

Vcc supply current

CIN
COUT

Capacitance
Input
Output

Typl

S82S130/131

Max

Typl

Min

UNIT
Max

=

V
.80

.85
2.0

2.0
-0.8

liN = -18mA

-1.2

0.8

-1.2

o

V
lOUT = 16mA
CE = low,IOUT=-2mA high stored

0.5

0.45
2.4

2.4

J.1.A
4f)
.85

VIN = 0.45V
VIN = 5.5V
CE = high, VOUT = 5.5V
CE = high, VOUT = 5.5V
CE = high, VOUT = 0.5V
VOUT = OV

8hort circuit (8281311

los

Min

"

-26
120

-150
50
40
40
-40
-70

-15

140

120

60
60
-60
-85

mA

140

mA

VIN = 2.0V, Vcc = 5.0V

pF
5
8

AC ELECTRICAL CHARACTERISTICS

Rl = 270n, R2 = 600n, Cl = 30pF2
N828130/131: 0° :5 TA:5 +75°C, 4.75V:5 Vcc:5 5.25V
8828130/131' -55°C <
- 5 5V
- TA <
- +125°C 4 5V <
- Vcc <

S825130/131
UNIT

Typl

Max

Min

Typl

Max
ns

Access time
TAA
TCE

Output
Output

Address
Chip enable

40
20

50
30

40
20

70
40

Output

Chip disable

20

30

20

40

ns

Disable time
TCD
NOTES
1. Typical values are at Vee == S.OV, TA = +25°C.

2. Positive current is defined as into the terminal referenced.

VOLTAGE WAVEFORM

TEST LOAD CIRCUIT

READ CYCLE

r----------------.
__ ____________________ OV

3 ,ov

~

~

R,

,._----.3,OV
1.5V

04

~------------,,+----------OV
TCD
-+-----~-

(INCLUDES SCOPE &
JIG CAPACITANCE)

--------------------------- - VOH

0,

All inpuls: Ir

~04

1.SV

= If = 5ns 110% to 90%1

SjgnotiCs

a:

~

oe.

II

FROM
Min

~

-

5
8

N82S130/131
TO

PARAMETER

J.1.A
J.1.A

E
w
E

115

82S1 III (8 G1 82S131

1018 BII BIPOI AI PRONi (SUI4)

ns )

82S130-F,N .82S131-F,N

PROGRAMMING SYSTEMS SPECIFICATIONS (Testing of these limits may cause programming of device.) TA = +25 C
0

LIMITS
TEST CONDITIONS

PARAMETER

Min

Typ

Max

8.5

8.75

9.0

5.3
4.3

5.5
4.5

5.7
4.7

1.4

1.5

V

Vccp

Power supply voltage
To program 1

VCCH
VCCL

Verify limit
Upper
Lower

Vs

Verify threshold2

Iccp

Programming supply current

VIH
VIL

Input voltage
High
Low

IIH
IlL

Input current
High
Low

VOUT

Output programming voltage3

lOUT

Output programming current

Iccp = 375 ± 75mA,
Transient or steady state

V

Vccp = +8.75 ± .25V

1.6

V

300

450

mA

2.4
0

5.5
0.8

V

IJ.A

lOUT = 200 ± 20mA,
Transient or steady state
VOUT = +17 ± 1V

50
-500
16.0

17.0

18.0

V

180

200

220

mA

50
0.5

IJ.s
ms

12

sec

TR
tp

Output pulse rise time
~ programming pulse width

0.3

to

Pulse sequence delay
Programming time

TpSI

Initial programming pause

TPR
TPR+Tps
FL

0.4

VIH = +5.5V
VIL = +0.4V

10

TPR

UNIT

0.4

10
Vccp = Vccp
Vcc = OV

IJ.S

6

sec

Programming duty cycle4

50

0/0

Fusing attempts per link

2

cycle

NOTES
1. Bypass Vee to GND with a O.01.uF capacitor to reduce voltage spikes.
2. VS is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes
the reference voltage applied to a comparator Circuit to verify a successful fusing attempt.
3. Care should be taken to insure the 17 ± 1V output voltage is maintained during theentire fusing cycle.
The recommended supply is a constant current source clamped at the specified voltage limit.
4. Programming duty cycle is 50% after continuous programming at 100% duty cycle.
S. This is an updated method of programming and does not obsolete any programming systems
presently being used.

PROGRAMMING PROCEDURE
1. Terminate all device outputs with a 10K
resistor to Vcc. Apply CE1 = High.
2. Select the Address to be programmed,
and raise Vcc to Vccp = 8.75 ± .25V.
3. After 10l-'s delay, apply VOUT = +17 ± 1V
to the output to be programmed. Program one output at the time.
4. After 10l-'s delay, pulse the CE1 input to

116

logic low for 0.3 to 0.5ms.
5. After 10l-'s delay, remove +17V from the
programmed output.
6. To verify programming, after 10l-'s delay,
lowerVcc toVccH=+5.5± .2V, and apply
a logic low level to the CE input. The
programmed output should remain in the
high state. Again, lower Vcc to VCCL =
+4.5 ± .2V, and verify that the pro-

GtgnotiCG

grammed output remains in the high
state.
7. Raise Vcc to Vccp = 8.75 ± .25V, and
repeat steps 3 through 6 to program other
bits at the same address.
8. After 10l-'s delay, repeat steps 2 through 7
to program all other address locations.

2948 BIT BIPOLAR PRoM (51214)

828130 (Q C.) 82SJ31 (l S)
82S130-F,N .82S131-F,N

TYPICAL PROGRAMMING SEQUENCE

"'" .".,,.,.;r--------------------:-,,-;--------------,
ADD
"0"

""""1-____________________....:......:........___________.......
ALAST

=
o

Vee
OV

E
w
E

OUTPUT
VOLTAGE

OV _---1...... '0% I

•a:

"'" .,.,.,m""--i

CE

"0"

~

oe.
--=

·Programming verification at both high and low Vee margins is optional. For convenience, verification
can also be executed at the operating Vee limits specified in the de characteristics.

Smnl!tiCS

117

87S 1411 (0 c: ) 825141 (I 5 )

1096 BIT BIPOLAR PROM (512X8)

828140-F,N • 828141-F,N

PIN CONFIGURATION

DESCRIPTION

FEATURES

The 828140 and 828141 are field programmable, which means that custom patterns
are immediately available by following the
fusing procedure given in this data sheet.
The standard 828140 and 828141 are
supplied with all outputs at logical low.
Outputs are programmed to a logic high
level at any specified address by fusing a NiCr link matrix.

• Address access time:
N825140/141: 60ns max
5825140/141: 90ns max
• Power dissipation: .17mW/bit typ
• Input loading:
N825140/141: -100!,A max
5825140/141: -150!,A max
• On-chip address decoding
• Output options:
5825140: Open collector
5825141: Tri-state
• No separate fusing pins
• Unprogrammed outputs are low level
• Fully TTL compatible

These devices include on-Chip decoding
and 4 chip enable inputs for ease of memory
expansion. They feature either open collector or tri-state outputs for optimization of
word expansion in bused organizations.
Both 828140 and 828141 devices are
available in the commercial and military
temperature ranges. For the commercial
temperature range (00 C to +75 0 C) specify
N828140/141 , F, and for the military temperature range (-55 0 C to +125 0 C) specify
8828140/141, F.

APPLICATIONS
•
•
•
•
•
•
•

A,

Prototyping/volume production
5equential controllers
Microprogramming
Hardwired algorithms
Control store
Random logic
Code conversion

A,O--'----I

Aoo----~TTTlII---n

A,o---------4

A,cr-----UJ...,J-.-L...L,...L..-W

CE,o-_q-.......

~~
~-----I
CE.o---'--O2

0

3

o~

0,

06

0

7

OB

OUTPUT LINES

ABSOLUTE MAXIMUM RATINGS
PARAMETER
Vcc
VIN
VOH
Vo
TA

TSTG

118

8upply voltage
Input voltage
Output voltage
High (828140)
Off-state (828141)
Temperature range
Operating
N828140/141
8828140/141
8torage

RATING

UNIT

+7
+5.5

Vdc
Vdc
Vdc

+5.5
+5.5

°c

o to +75
-55 to +125
-65 to +150

smnotics

As

NC

0,

0,

GNO

1:64 DE·
CODER

0,

Vee

A,

'F ~ Cerdip
N = Plastic

0--,----1

LINES

A7

0,

BLOCK DIAGRAM

ADDRESS

F,N PACKAGE'

0.

S,SI'n (0 C J 82&141 (I S )

.096 BIT BIPm AR PROM (51218)

828140-F,N .828141-F,N

DC ELECTRICAL CHARACTERISTICS

N82S140/141: O°C~ TA ~+75°C, 4.75V ~ Vcc ~ 5.25V
S828140/141: -55°C ~ TA ~ +125°C, 4.5V S Vcc ~ 5.5V
N82S140/141

PARAMETER

V,l
V,H
V'c

Input voltage
Low
High
Clamp

VOL
VOH

Output voltage
Low
High (82S141)

ill
IIH

Input current
Low
High

10LK

Output current
Leakage (828140>
Hi-Z state (82S141)

10(OFF)

Short circuit (828141)

los

TEST CONDITIONS1

Min

C,N
COUT

S82S140/141

Max

Min

Typ2

Max

UNIT
V

.85
2.0

.80
2.0

liN = -18mA

-0.8

-1.2

-0.8

-1.2
V

lOUT = 9.6mA
CE1 = Low, lOUT = -2mA, CE2 = Low,
CE3 = High, CE4 = High, High stored

0.5

0.45
2.4

2.4

p.A
V,N =0.45V
V,N = 5.5V

-100
40

-150
50

CE1 = High, VOUT = 5.5V, CE2 = High,
CE3 = Low, CE4 = Low
CE1 = High, Vour= 0.5V; CE2 = High,
CE3 = Low, CE4 = Low
CE1 = High, VOUT = 5.5V, CE2 = High,
CE3 = Low, CE4 = Low
VOUT = OV

40

60

p.A

-40

-60

p.A

40

60

-20

. Vcc supply current

Icc

Typ2

-70
140

Capacitance
Input
Output

140

-85

mA

185

mA
pF

Vcc = 5.0V
V,N = 2.0V
VOUT = 2.0V

AC ELECTRICAL CHARACTERISTICS

-15

175

5
8

5
8

R1 = 470n, R2 = lkn, Cl = 30pF
N82S140/141: O°C ~ TA ~ +75°C,4.75V ~ Vcc ~ 5.25V
S828140/141' -55°C <
- TA <
- +125°C, 4.5V <
- Vce <
- 5 5V
N82S140/141

PARAMETER

TO

FROM
Min

S82S140/141

Typ2

Max

Min

Typ2

Max

ns

Access time
TAA
TCE

. Output
Output

Address
Chip enable

40
20

60
40

40
20

90
50

Output

Chip disable

20

40

20

50

ns

Disable time
TCD

UNIT

NOTES
1. Positive current is defined as into the terminal referenced.
2. Typical values are at Vee = 5.0V, TA = +25°C.

Si!)OOtiCS

119

=
o
E
w

e

•a:
oe.--

III

82S140-F,N .82S141-F,N

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM
,..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ·3.0V

'1.5V
-____________________________ ov
A.
A,
A,

Vee

0,

o.

v

o

-

-

-

-

-

-

~

-

' -___________________

~

CHIP ENABLES

J

, . ._ _ _ _ _ ·3.0V

A,
A,
A,

1.6V

tr = If = 5ns (10% to 90%)

PROGRAMMING SYSTEMS SPECIFICATIONS

(Testing of these limits may cause programming of device.) T A = +25°C
LIMITS

PARAMETER

Vccp

Power supply voltage
To program 1

VCCH
VCCL
Vs
Iccp

Verify limit
Upper
Lower
Verify threshold2
Programming supply current

VIH
VIL

Input voltage
High
Low

IIH
ilL

Input current
High
Low

VOUT

Output programming voltage3

Min

Typ

Max

8.5

8.75

9.0

5.3
4.3

5.5
4.5

5.7
4.7

1.4

1.5

V
Iccp = 375 ± 75mA,
Transient or steady state

Vcep = +8.75

± .25V

V

1.6

V

300

450

mA

2.4
0

5.5
0.8

V
0.4

VIH = +5.5V
VIL = +0.4V
lOUT = 200 ± 20mA,
Transient or steady state
VOUT = +17

± lV

50
-500

JJA

16.0

17.0

18.0

V

180

200

220

mA

lOUT

Output programming current

TA

Output pulse rise time

10

tp

CE programming pulse width

0.3

0.4

50

~

0.5

ms

12

sec

10

~

to

Pulse sequence delay

TPA

Programming time

Tpsi

Initial programming pause

TpA
TPR+Tps

Programming duty cycle4

50

%

FUSing attempts per link

2

cycle

FL

Vcc = Vccp
Vcc =OV

NOTES
1. Bypass Vee to GNO with a O.OI#F capacitor to reduce voltage spikes.
2. Vs is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes
the reference voltage applied to a comparator circuit to verify a successful fusing attempt.
3. Care should be taken to insure the 17 ± 1V output voltage is maintained during the entire fusing cycle,
4. Programming duty cycle is 50% after continuous programming at 100'10 duty cycle.
5. This is an updated method of programming and does not obsolete any programming systems
presently being used.

120

UNIT

TEST CONDITIONS

S!)OOtIGS

sec

6

8l'S 14n (U C ) 82S 141 (I S )

4096 BIT BIPOLAR PROM (512181

82S140-F,N .82S141-F,N

PROGRAMMING PROCEDURE
1. Terminate all device outputs with a 10k!}
resistor to Vee. Apply CE, = High, CE2 =
Low, CE3 = High and CE4 = High.
2. Select the Address to be programmed,
and raise Vee to Veep = 8.75 ± .25V.
3. After 10l'S delay, apply VOUT = +17 ± 1V
to the output to be programmed. Program one output at the time.

4. After 10l's delay, pulse the CE, input to
logic low for 0.3 to 0.5ms.
5. After 1OI's delay, remove +17V from the
programmed output.
6. To verify programming, after 10j.ls delay,
lower Vec to VCCH = +5.5 ± .2V, and apply
a logic low level to the CE input. The
programmed output should remain in the
high state. Again, lower Vee to VeeL =

+4.5 ± .2V, and verify that the programmed output remains in the high
state.
7. Raise Vec to Vecp = 8.75 ± .25V, and
repeat steps 3 through 6 to program other
bits at the same address.
8. After 10j.ls delay, repeat steps 2 through 7
to program all other address locations.

o==

TYPICAL PROGRAMMING SEQUENCE

"'"
ADD
"0"

E
w

,,"~r---------------------:-':""""-----------""
,",~,-

E
..:

ALAST
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...!.....!.-_ _ _ _ _ _ _"",,_ _.....J

...o
a:

Vee
OV

--=
e.

OUTPUT

VOLTAGE
OV _ _'-1,0%1

----u

"'" ""'=I~--i

CE,

"0"

I

-

I

*Programming verification at both high and low Vee margins is optional. For convenience, verification
can also be executed at the operating Vee limits specified in the de characteristics

smnntms

121

82S136-F,N • 828137-F,N

DESCRIPTION

FEATURES

The 828136 and 828137 are field programmable, which means that custom patterns
are immediately available by following the
fusing procedure given in this data sheet.
The standard 828136 and 828137 are supplied with all outputs at logical low. Outputs
are programmed to a logic high level at any
specified address by fusing a Ni-Cr link
matrix.

• Address access time:
N825136/137: 60ns max
5825136/137: 80ns max
• Power dissipation: .13mW/bit typ
• Input loading:
N825136/137: -1001'A max
5825136/137: -150I'A max
• On-chip address decoding
• Output options:
825136: Open collector
825137: Tri-state
• No separate fusing pins
• Unprogrammed outputs are low level
• Fully TTL compatible

These devices include on-chip decoding
and 2 chip enable inputs for ease of memory
expansion. They feature either open collector or tri-state outputs for optimization of
word expansion in bused organizations.
Both 828136 and 828137 devices are available in the commercial and military temperature ranges. For the commercial temperature range (0° C to +75° CI specify
N828136/137, F or N, and for the military
temperature range (-55°C to +125° C) specify S828136/137, F.

PIN CONFIGURATION
F,N PACKAGE"
Vee
A,

A,

A.

A.

A,

A.

A,

0,

A,

0,
0,

Ce l
CE 2
*F == Cerdip
N == Plastic

BLOCK DIAGRAM
r----------------------~---------__,

(15)

A.

0'--'---1

STORAGE

MATRIX

1 :64
DECODER

64X64

(7)

A,O'----l

A,

(4)

(5(

A,

GEt
CE2

(8)

(10j

0,

0,

0,

0,

ABSOLUTE MAXIMUM RATINGS
PARAMETER
Vee
V(N
VOH
Vo
TA

TSTG

122

8upply voltage
Input voltage
Output voltage
High (8281361
Off-state (828137)
Temperature range
Operating
N828136/137
882S136/137
Storage

Si!lDOliCS

RATING

UNIT

+7
+5.5

Vdc
Vdc
Vdc

+5.5
+5.5
°C

a to +75
-55 to +125
-65 to +150

828136-F,N .828137-F,N

DC ELECTRICAL CHARACTERISTICS

N828136/137: O°C::; TA::; +75°C, 4.75V::; Vcc::; 5.25V
8828136/137: -55°C::; TA::; +125°C, 4.5V::; VCC::; 5.5V
N825136/137

PARAMETER

Vil
VIH
VIC

Input voltage
Low
High
Clamp

VOL
VOH

Output voltage
Low
High (828137)

TEST CONDITION5 1

5825136/137

Max

Typ2

Min

Max

UNIT
V

.80

.85
2.0

2.0
-0.8

liN = -18mA

-0.8

-1.2

-1.2
V

lOUT = 16mA
CE = Low, IOUT= -2mA, High stored

10lK
10IOFF)

Input current
Low
High
Output current
Leakage (828136)
Off-state 1828137>

los
Icc

Vcc supply current

CIN
COUT

Capacitance
Input
Output

III
IIH

Typ2

Min

0.5

0.45
2.4

2.4
/lA

8hort circuit 1828137>

VIN = 0.45V
VIN = 5.5V

-100
40

-150
50

CE = High, VOUT = 5.5V
CE = High, VOUT = 0.5V
CE = High, VOUT = 5.5V
VOUT = OV

40
-40
40
-70

60
-60
60
-85

mA

140

mA

-20
105

105

pF

Vcc = 5.0V
VIN = 2.0V
VOUT = 2.0V

AC ELECTRICAL CHARACTERISTICS

-15

140

/lA
/lA

5
8

5
8

Rl = 2700, R2 = 6000, Cl = 30pFl
N828136/137: O°C::; TA::; +75°C, 4.75V::; Vcc::; 5.25V
8828136/137: -55°C::; TA::; +125°C, 4.5V::; Vcc::; 5.5V

N825136/137
PARAMETER

TO

FROM

Output
Output
Output

Min

5825136/137
Typ2

Max

60
30

40
20

80
40

30

20

40

Typ2

Max

Address
Chip enable

40
20

Chip disable

20

Min

UNIT
ns

Access time
TAA
TCE

ns

Disable time
TCD
NOTES
1. Positive current is defined as into the terminal referenced.
2. All typical values are at Vee = 5V, TA = 25°C.

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM

Vee

READ CYCLE
, - - - - - - - - - - - - - - - - - ·3.0V
ADDRESS

A.

'-----------------------------oV

A,

A,

,----+3.DV

R,

Teo

0,

A.
A,

1.5V
'-_________--.J'+ _______
OV

0,

A,
OUT

0,
1.5V

O.

1.5V

'-----------------~-- VOL

A,
A,
A,

All inpuls: I,

= If = 5ns 110% to 90%1

eE,
CE 2 Q-__--'

Si!lDotiCS

123

o==
E
w

E
.:

...o
c:

..-..

82S136-F,N .82S137-F,N

PROGRAMMING SYSTEMS SPECIFICATIONS (Testing of these limits may cause.prograrnming of device.) T A = +25°C
LIMITS

Vccp
VCCH
VecL
Vs
Iccp

UNIT

TEST CONDITIONS

PARAMETER

Iccp = 375 ± 75mA,
Transient or steady state

Power supply voltage
To program 1
, Verify limit
Upper
Lower
Verify threshold2
Programming supply current

Vcep

= +8.75 ± .25V

Min

Typ

Max

8.5

8.75

9.0

5.3
4.3

5.5
4.5

5.7
4.7

1.4

1.5

V
V

1.6

V

300

450

rnA

2.4
0

5.5
0.8

V

VIH
VIL

Input voltage
High
Low

ItH
IlL

Input current
High
Low

VOUT

Output programmingvoltage3

VIH
VIL

pA

= +5.5V
= +O.4V

lOUT = 200 ± 20mA,
Transient or steady state

= +17 ± 1V

50
500
16.0

17.0

18.0

V

180

200

220

rnA

lOUT

Output programming current

TR

Output pulse rise time

10

tp

CE programming pulse width

0.3

to

Pulse sequence delay

10

TPR

Programming time

TpSI

Initial programming pause

TPR
TPR+Tps

Programming duty cycle4

50

%

Fusing attempts per link

2

cycle

FL

VOUT

0.4

= Vccp
Vec = OV

Vce

0.4

50

IJS,

0.5

ms

12

IJS
:sec

.

6

sec

NOTES
1. Bypass Vee to GND with a 0.01 ~F capacitor to reduce voltage spikes.

2. Vs is the sensing threshold of the PROM output voltage for a programmed bit. It normallyconstitutes
the reference voltage applied· to a comparator circuit to verify a successful fusing attempt.
3. Care should be taken to insure the 17 ± 1V output voltage is maintained during the entire fusing cycle.
The recommend~d supply is a constant current source clamped at the specified voltage limit.
4. Programming duty cycle Is 50% after cpntinuous: programming at 100% duty cycle.
5. This is an updated method of programming and does not obsolete any programming systems
presently being used.

PROGRAMMING PROCEDURE
1. Terminate all device outputs with a 10Kn
resistor to Vce. Apply CE1 = High CE2 =
Low.
2. Select the Address to be programmed,
and raise Vec to Vccp = 8.75 ± .25V.
3. After 10J's delay, apply VOUT = +17 ± 1V
to the output to be programmed. Program one output at the time.

124

4. After 1OJ's delay, pulse the CEl input to
'logic low for 0.3 to 0.5ms.
5. After 1OJ's delay, remove +17V from the
programmed output.
6. To verify programming, after 1OJ's delay,
lower VCC VCCH = +5.5 ± .2V, and apply a
logic low level to the CE input. The p.rograrnmed output should remain in the
high state. Again, lower Vce to VCCL =

SmDotiCS

+4.5 ± .2V, and verify that the programmed output remains in the high
state.
7. Raise Vce to Vccp = 8.75 ± .25V, and
repeat steps 3 through 6 to prog ram other
bits at the same address.
,
8. After 1OJ's delay, repeat steps 2 through'"
to program all other address locations.

409S BIT BIRDI AR RRUM (102414)

828136 (0 C) 828137 (T S )
82S136-F,N .82S137-F,N

TYPICAL PROGRAMMING SEQUENCE

"1"

ADD
"0"

~-------:-:-----""------I---

"""=""""___________________-:--;-___________
AFIRST

ALAST

~------

---

=
o
e

6 SEC MIN

Vee
OV

w

OUTPUT
VOLTAGE

OV _

"1"

ee,

e

B,
.....1-110%1

-----~-----

"0"

·Programming verification at both high and low Vee margins is optional. For convenience, verification
can also be executed at the operating Vee limits specified in the de characteristics.

Si!lnotiCs

125

82818O-F,N ;, 828181-F,N

DESCRIPTION

FEATURES

The 828180 and 828181 are field programmable, which means that custom patterns
are immediately available by following the
fusing procedure given in this data sheet.
The standard 828180 and 828181 are supplied with all outputs at logical low. Outputs
are programmed to a logic high level at any
specified address by fusing a Ni-Cr link
matrix.

• Address access time:
N82S180/181: 70ns max
S82S180/181: 90ns max
• Power dissipation: 85"W/bll typ
• Input loading:
N82S180/181: -100"A max
S82S1801181: -150"A .max
• On-Chip address decoding
• Output options:
82S180: Open collector
82S181: Trl-state
• No separate fusing pins
• Unprogrammed outputs are low level
• Fully TTL compatible

These devices include on-Chip decoding
and 4 chip enable inputs for ease of memory
expansion. They feature either open collector or tri-state outputs for optimization of
word expansion in bused organizations.

PIN CONFIGURATION

•
•
•
•
•
•
•

Prototyplng/volume production
Sequential controllers
Microprogramming
Hardwired algorithms
Co.ntrol store
Random logic
C.ode conversion

N = Plasilc

CODER

0--1.----1

0---------1

A,o--------~

A,o-------~~~rL~~~Lr~

Ci'o-__...

Ci·~=Lj----1
g~o
0,

o.

01

04

0&

O.

07

0,

DUTPUTLINES

ABSOLUTE MAXIMUM RATINGS
UNIT

8upply voltage

+7

Vdc

VIN

Input voltage

+5.5

Vdc

VOH
Vo

Output voltage
High (828180)
Off-state (828181)

+5.5
+5.5

Tsm

126

RATING

Vee

Temperature range
Operating
N828180/181
8828180/181
8torage

0,

OF = Cerdip

A, o---------r-"-T-,r-.,-..,......,.-r-"T""~

TA

CEo

Vdc

·C

o to +75
-55 to +125
-65 to +150

stgnotics

0,
0,

1:64 DE·

PARAMETER

CE,

GND

... 0-....-----4

A,

CE,
CE.

0,

BLOCK DIAGRAM

A,

Vcc

...
...

0,

APPLICATIONS

The 828180 and 828181 are available in
both the commercial and military temperature ranges. For the commercial temperature range (O°C to +75° C) specify
N828180/181 , For N, and for the military
temperature range (.,.55°Cto +125°C) specIfy 8828180/181, F.

ADDRESS
LINES

F,N PACKAGE·

o.

8192 hll BIPOE"R PROM (1024IS)

Sz:.180 (n

r: ) ijb 181

(I S )

82S180-F,N .82S181-F,N

DC ELECTRICAL CHARACTERISTICS

N82S180/181: O°C:5 TA:5 +75°C, 4.75V:5 Vcc:5 5.25V
S82S180/181: -55°C:5 TA:5 +125°C, 4.5V:5 Vcc :5 5.5V

S82S180/181

N82S1801181
PARAMETER

Vil
VIH
VIC

Input voltage
Low
High
Clamp

VOL
VOH

Output voltage
Low
High (82S181)

hl
hH

Input current
Low
High

IOlK

Output current
Leakage (82S180)

IO(OFF)

Hi-Z state (82S181)

Short circuit (82S181)

los
Icc

Vcc supply current

CIN
COUT

Capacitance
Input
Output

TEST CONDITIONS'

Typ2

Min

Max

Typ2

Min

UNIT

Max

=
o

V
.80

.85
2.0
liN

2.0

= -18mA

-0.8

-0.8

-1.2

-1.2
V

lOUT = 9.6mA
GEl = low, lOUT = -2mA, CE2 = low,
CE2 = high, CE4 = high, high stored

2.4

J.JA

= high,

VOUT = 5.5V, CE2
CE3 = low, CE4 = low
CE, = high, VOUT = 0.5V, CE2
CE3 = low, CE4 = low
CEl = high, VOUT = 5.5V, CE2
CE3 = low, CE4 = low
VOUT = OV

-100
40

-150
50

= high,

40

60

J.JA

= high,

-40

-60

J.JA

= high,

40

60

J.JA

-85

mA

185

mA

-20

-70
140

Vcc = 5.0V
VIN = 2.0V
VOUT = 2.0V

AC ELECTRICAL CHARACTERISTICS

Rl

= 4700,

E
w

2.4

VIN = 0.45V
VIN = 5.5V

CEl

0.5

0.45

-15

175

140

pF
5
8

R2

5
8

= 1kO, Cl = 30pF

N82S180/181: O°C :5 TA:5 +75°C, 4.75V:5 Vce:5 5.25V
S82S180/181: -55°C:5 TA:5 +125°C, 4.5V:5 Vcc 5.5V

N82S180/181
PARAMETER

TO

S82S1801181
UNIT

FROM
Min

Typ2

Max

Min

Typ2

Max

Access time
TAA
TCE

ns
Output
Output

Address
Chip enable

50
20

70
40

50
20

90
50

Output

Chip disable

20

40

20

50

Disable time
TCD

ns

NOTES
1. Positive current is defined as into the terminal referenced.
2. Typical values are at V ce = 5.0V, T A = +25·C.

Smnotics

127

E

•c:

...."

o

II

82S180-F,N .82S181-F,N

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM

,_-----------------------+3.oV

Vee

'-____________ ______________________________ OV
1,6V

A,
A,
A,
A,

Vee.

~

,..-----+3.0V

.........

CHIP ENABLES

'-__________________________

RI' CL ~~~~~D:~IG

A,

A,

-'_~,---------OV

CAPACITANCE)

eE,

ee.
0, ..,.GND

"::""::"

o.

1.&V

'

All inputs: t, = tf =.5ns ('0% to 90%1

PROGRAMMING SYSTEMS SPECIFICAtiONS (Testing of these limits may cause programming of device.) T A = +25'C
LIMITS
PARAMETER

Vccp

Power supply voltage
To program'

VCCH
VCCl
Vs
Iccp

Verify limit
Upper
Lower
Verify threshold2
Prd'gramming supply current

VIH
Vil

Input voltage
High
Low

ilH
ill

Input current
High
Low

..

Max

8.5

8.75

9.0

5.3
4.3

5.5
4.5

5.7
4.7

1.4

1.5

V
Icep = 375 ± 75mA,
Transient or steady state

Vccp

= +8.75 ± .25V

1.6

V

300

450

mA

2.4
0

5.5
0.8

VIH
VIL

lOUT = 200 ± 20mA,
Transient or steady state

50
-500·
17.0

18.0

V

180

200

220

mA

Output programming current
Output pulse rise. time

10

tp

CE programming pulse width

0.3

to

Pulse sequence delay
Programming time

Tpsi

Initial programming pause.

= +17 ± 1V

0.4

50

fJS

0.5

ms

12

sec

10
Vcc = Vccp
Vcc

= OV

Programming duty cycle4
Fusing attempts per link

Bypass Vee to GNO with a 0.0' "F capacitor to reduce voltage spikes.

2. Vs is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes
the reference voltage applied to a comparator circuit to verify a successful fusing attempt.
3. Care should be taken to Insure the 17 ± tV output voltage is maintained during the entire fusing cycle.
4. Programming duty cycle is 50% after continuous programming at '00% duty cycle.

5. This Is an updated method of programming and does not obsolete any programming systems
presently being used.

.S~DDtiGS

JJA

16.0

TR

VOUT

0.4

= +5.5V
= +O.4V

lOUT

TPR

V

V

NOTES

128

Typ

Output programming voltage3

Fl

..:-

Min

VOUT

TPR
TPR+Tps

,.

UNIT

TEST CONDITIONS

fJS

6

sec
50

%

.2

cycle

8192 BIT BIPO[nR PROM (1024X8)

825180 (0 C ) 825181 (J 5 )
82Si80-F,N .82S181-F,N

PROGRAMMING PROCEDURE
1. Terminate all device outputs with a 10kO
resistor to Vcc. Apply CE1 = High, CE2 =
Low, CE3 = High and CE4 = High.
2. Select the Address to be programmed,
and raise Vcc to Vccp = 8.75 ± .25V.
3. After 10"s delay, apply VOUT = +17 ± 1V
to the output to be programmed. Program one output at the time.

4. After 10"s delay, pulse the CE1 input to
logic low for 0.3 to 0.5ms.
5. After 10"s delay, remove +17V from the
programmed output.
6. To verify programming, after 10"s delay,
lower Vcc to VCCH =+5.5± .2V, and apply
a logic low level to the CE1 input. The
programmed output should remain in the
high state. Again, lower Vcc to VCCL =

+4.5 ± .2V, and verify that the programmed output remains in the high
state.
7. Raise Vcc to Vccp = 8.75 ± .25V, and
repeat steps 3 through 6 to program other
bits at the same address.
8. After 10"s delay, repeat steps 2 through 7
to program all other address locations.

TYPICAL PROGRAMMING SEQUENCE

A~~
"0"

AFIRST

ALAST

---1---

""""1---------------------...:.....1-------------....1------ -_-

=:o
E
w

E

6 SEC MIN

~

a:

Vee

~

oe.

DV

-

OUTPUT
VOLTAGE

DV _

II

........,·'0·,.1

"1"

CEl
"0"

·Programming verification at both high and tow Vee margins is optional. For convenience, verification
can also be executed at the operating Vee limits specified in the de characteristics.

Smnl!tiCS

129

819' BIT BIPOLAR PROM (102418)

82827118 (T S )
8282708-F,N

DESCRIPTION

FEATURES

The 8282708 is field programmable, which
means that custom patterns are immediately available by following the fUSing procedure given in this data sheet. The standard
8282708 is supplied with all outputs at logical low. Outputs are programmed to a logic
high level at any specified address by fusing
a Ni-Cr link matrix.

• Address access time:
N82S2708: 70ns max
S82S2708: 90n5 max
• Power dissipation: 85!'W/bit typ
• Input loading:
N82S2708:-100!,A max
S82S2708:-150!'A max
• Chip enable input
• On-Chip address decoding
• No separate fusing pins
• Unprogrammed outputs are low level
• Pin for pin replacement for 2708 EROM
• Fully TTL compatible

This device includes on-chip decoding and
1 chi p enable input for ease of memory
expansion. It features tri-state outputs for
optimization of word expansion in bused
organizations.

PIN CONFIGURATION
F,N PACKAGE"

N.C.

A,

N.C

0,
0,

The 8282708 is available in both the commercial and military temperature ranges.
For the commercial temperature range (0°
to +75°C) specify N8282708, and for the
military temperature range (-55° C to
+125°C) specify 88282708.

APPLICATIONS
•
•
•
•
•
•
•

0,

GND

0,

'F ~ Cerdip
N = Plastic
NC = No connection

BLOCK DIAGRAM

Prototyping/volume production
Sequential controllers
Microprogramming
Hardwired algorithms
Control store
Random logic
Code conversion

01

O2

0,

04

Os

06

07

08

OUTPUT LINES

ABSOLUTE MAXIMUM RATINGS
PARAMETER

UNIT

Vee

8upply voltage

+7

Vdc

VIN

Input voltage

+5.5

Vdc

VOH
Vo

Output voltage
High
Off-state

+5.5
+5.5

TA

TSTG

130

RATING

Temperature range
Operating
N8282708
88282708
8torage

StgDl!tiCS

Vdc

°C
0 to +75
-55 to +125
-65 to +150

8282708-F,N

DC ELECTRICAL CHARACTERISTICS N8282708: O°C::; TA ::;+75°C, 4.75V::; Vee::; 5.25V
$8282708: -55°C::; TA::; +125°C, 4.5V::; Vee::; 5.5V
S82S2708

N82S2708
PARAMETER

VIL
VIH
Vie

I nput voltage
low
High
Clamp

VOL
VOH

Output voltage
low
High

ilL
IIH

Input current
low
High

IO(OFF)

Output current
Hi-Z state

TEST CONDITIONS1

Max

Min

Typ2

UNIT

Max

V
.80

.85
2.0

2.0
-0.8

liN = -18mA

-0.8

-1.2

-1.2
V

lOUT = 9.6mA
lOUT = -2.0mA, CE = low,
High stored

0.45
2.4

0.5
2.4

IJA

8hort circuit

los

Typ2

Min

lee

Vee supply current

CIN
COUT

Capacitance
Input
Output

VIN = 0.45V
VIN = 5.5V

-100
40

-150
50

CE = High, VOUT = 0.5V
CE = High, VOUT = 5.5V
VOUT = OV

-40
40
-70

-60
60
-85

mA

185

mA

-20
140

-15
140

175

IJA

pF

Vee = 5.0V
VIN = 2.0V
VOUT = 2.0V

5
8

5
8

= 4700., R2 = 1ko., CL = 30pF
N8282708: O°C::; TA::; +75°C, 4.75V::; Vee ~ 5.~V
88282708: -55°C::; TA::; +125°C, 4.5V::; Vee::; 5.5V

S82S2708

N82S2708
TO

FROM

Output
Output
Output

Typ2

Max

Address
Chip enable

50
20

Chip disable

20

Min

Typ2

Max

70
40

50
20

90
50

40

20

50

Min

UNIT

Access time

ns

TAA
TeE

ns

Disable time
Teo
NOTES
1. Positive current is defined as into the terminal referenced.

2. Typical value. are Vee = S.OV. TA = +2SO C.

VOLTAGE WAVEFORM

TEST LOAD CIRCUIT

, . . . - - - - - - - - - - - - - - - - - - - - ".OV

VCC

1.SV

A.
A,

~-------------------------ov

VCC

, _ - - - - - - - ".OV

A,

A,
A.
A,
A.
A,
A.
A.

1.5V

CHIP ENABLE

I

R,

(INCLUDES

1,5V

0,-0.

Ctscope&JIG

ce

":"":"

-=

GND

CAPACITANCE,

All inputs: I, = It = 5ns 110% 10 90%1

GtgnotiCG

E
w

E
..:

...o
c:

e.

II

AC ELECTRICAL CHARACTERISTICS R1

PARAMETER

=
o

131

82S2708-F,N

PROGRAMMING SYSTEMS SPECIFICATIONS

(Testing of these limits may cause programming of device.) TA = +2.5°C
LIMITS

PARAMETER

UNIT

TEST CONDITIONS
Iccp = 375 ± 75mA,
Transient or steady state

Vccp

Power supply voltage
To program 1

VCCH
VCCL
Vs
Iccp

Verify limit
Upper
Lower
Verify threshold2
Programming supply current

VIH
VIL

I nput voltage
High
Low

IIH
IlL

Input current
High
Low

VOUT

Output programming voltage 3

Vccp

= +8.75 ± .25V

Min

Typ

Max

8.5

8.75

9.0

5.3
4.3

5.5
4.5

5.7
4.7

1.4

1.5

V

V

1.6

V

300

450

mA

2.4
0

5.5
0.8

V

= +5.5V
= +0.4V
lOUT = 200 ± 20mA,

0.4

VIH
VIL

50
-500

/-IA

16.0

17.0

18.0

V

180

200

220

mA

Transient or steady state
Output programming current
Output pulse rise time

10

tp

CE programming pulse width

0.3

tD

Pulse sequence delay

TPR

Programming time

Tpsi

Initial programming pause

TPA
TpA+Tps

Programming duty cycle4

FL

VOUT

= +17 ± 1V

lOUT
TR

0.4

50

f.1S

0.5

ms

12

sec

10

= Vccp
Vee = OV

Vcc

Fusing attempts per link

/..IS

6

sec
50

%

2

cycle

NOTES
1. Bypass Vee to GNO with a 0.01 /.LF capacitor to reduce voltage spikes.
2. Vs is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes
the reference voltage applied to a comparator circuit to verify a successful fusing attempt.
3. Care should be taken to insure the 17 ± 1V output voltage is maintained during the entire fusing cycle.
4. Programming duty cycle is 50% after continuous programming at 100% duty cycle.
5. This is an updated method of programming and does not obsolete any programming system"s
presently being used.

PROGRAMMING PROCEDURE
1. Terminate all device outputs with a 10kn
resistor to Vcc. Apply CE = High.
2. Select the Address to be programmed,
and raise Vcc to Vccp = 8.75 ± .25V
3. After 10,.,s delay, apply VOUT = +17 ± 1V
to the output to be programmed. Program one output at the time.
4. After lO,.,s delay, pulse the CE input to

132

logic low for 0.3 to 0.5ms.
5. After 10,.,s delay, remove +17V from the
programmed output.
6. To verify programming, after 10,.,s delay,
lower Vcc to Vccw=+5.5 ± .2V, and apply
a logic low level to the CE input. The
programmed output should remain in the
high state. Again, lower Vcc to VCCL =
+4.5 ± .2V, and verify that the pro-

Si!JDOliCS

grammed output remains in the high
state.
7. Raise Vcc to Vccp = 8.75 ± .25V, and
repeat steps 3through 6to program other
bits at the same address.
8. After 1O,.,s delay, repeat steps 2 through 7
to program all other address locations.

8192 BIT BIPOLAR PROM (102418)
82S2708-F,N

TYPICAL PROGRAMMING SEQUENCE

"1"

~~r----------------------:-"-------------"I-'--'-'A LAST

ADD

"0"

Veep

=

'""4'---------;;;:;.;;;;:-;--JI----~

---i-----....,

o

Vee
OV

E
w
E

OUTPUT
YOLTAGE

•

OV

"1"

c:

-'...:..-i

.....

CE

".,

oe.

"0"

-

II

*Programming verification at both high and low Vee margins is optional. For convenience, verification
can also be executed at the operating Vee limits specified in the de characteristics.

Gi!lDotiCG

133

82S184-1 .82S185-1

DESCRIPTION

FEATURES

The 82S184 and 82S185 are field programmable, which means that custom patterns
are immediately available by following the
fusing procedure given in this data sheet.
The standard 82S184 and 82S185 are
supplied with all outputs at logical low.
Outputs are programmed to a logic high
level at any specified address by fusing a NiCr link matrix.

• Low power dissipation: 50!-'W/bit typ
• Address access time:
N825184/185: 100ns max
5825184/185: 150ns max
• Input loading:
N825184/185: -100!-,A max
5825184/185: -150!-,A max
• On-chip address decoding
• Output options:
825184: Open collector
825185: Tri-state
• No separate fusing pins
• Unprogrammed outputs are low level
• Fully TTL compatible

These devices include on-chip decoding
and 1 chip enable input for ease of memory
expansion. They feature either open collector or tri-state outputs for optimization of
word expansion in bused organizations.
Both 82S184 and 82S185 devices are
available in the commercial and military
temperature ranges. For the commercial
temperature range (QoC to +75°C specify
N82S184/185, I, and for the military temperature range (-55° C to +125° C) specify
S82S184/185, I.

*1::::: Cerdip

BLOCK DIAGRAM

(8}

A"

I
I

I
I
I

I
I

I

I

I
I
I
I

A,

"

(2}

1:64

DECODER

I
I
I

STORAGE

MATRIX
64X128

I
I
I
I

I
I

I I I I I I I

(3}

I--

A.

I
(5}

A,

1:32

I--

~

flO)
CE

~

'-'l

1

1

1:32

DECODER

-

1

I

(12)

0

134

1:32
DECODER

I--

(11)

0.

-

I-1:32
DECODER

DECODER

I

I PACKAGE'

0,

11 4}

(13)

0,

SmnotiCs

0,

8192 BIT BIPOLAR PROM (2048)(4)
828184-1·828185-1

ABSOLUTE MAXIMUM RATINGS
PARAMETER
8upply voltage
Input voltage
Output voltage
High (828184)
Off-state (828185)
Temperature range
Operating
N828184/185
8828184/185
8torage

Vee
VIN
VOH
Vo
TA

TSTG

RATING

UNIT

+7
+5.5

Vdc
Vdc
Vdc

=

+5.5
+5.5
°C

o

o to +75
-55 to +125
-65 to +150

DC ELECTRICAL CHARACTERISTICS

N828184/185: O°C S TA S +75°C, 4.75V S Vee S 5.25V
8828184/185: -55°C S TA S +125°C, 4.5V S Vee S 5.5V

TEST CONDITIONS1
Min

VIL
VIH
Vie
VOL
VOH

Output voltage
Low
High (828185)

IlL
hH

Input current
Low
High

10LK
10 (OFF)

Output current
Leakage (828184)
Hi-Z state (828185)

lee

Vee supply current

CIN
COUT

CapaCitance
Input
Output

Typ2

Max

Min

Typ2

Max

UNIT
V

.80

.85
2.0
liN = -18mA

2.0
-0.8

-1.2

-0.8

-1.2
V

lOUT = 16mA
CE = Low, lOUT = -2mA, High stored

0.5

0.45
2.4

2.4
I"A

8hort circuit (828185)

los

S82S1841185

N82S184/185

PARAMETER
Input voltage
Low
High
Clamp

E
w
E

VIN= 0.45V
VIN = 5.5V

-100
40

-150
50

CE = High, VOUT = 5.5V
CE = High, VOUT = 0.5V
CE = High, VOUT = 5.5V
VOUT = OV

40
-40
40
-70

60
-60
60
-85

mA

130

mA

-20
80

80

pF

Vee = 5.0V
VIN = 2.0V
VOUT = 2.0V

AC ELECTRICAL CHARACTERISTICS

-15

120

I"A
I"A

5
8

5
8

R1 = 270n, R2 = 600n, CL = 30pF3
N828184/185: O°C S TA S +75°C, 4.75V S Vee S 5.25V
8828184/185: -55°C S TA S +125°C, 4.5V S Vee S 5.5V
N82S184/185

PARAMETER

TO

FROM
Min

Typ2

Max

S82S184/185

Min

Typ2

Max

Access time
TAA
TeE

ns
Output
Output

Address
Chip enable

70
30

100
40

70
30

125
60

Output

Chip disable

30

40

30

60

Disable time
TeD

UNIT

ns

NOTES
1. All voltage values are with respect to network ground terminaL

2. All typical values are at Vee

= 5V. TA = 25' e.

3. Positive current is defined as into the terminal referenced.
4. Duration of the short circuit should not exceed 1 second.

SmDotiCS

135

-=

c:
fIIIIIII

oe.

-

II

8192 BIT DIPO[uR PROM (2048X4)

825184 (0

e ) 825185 (J 5 )
828184-1 • 828185-1

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM

Vee

,...------------------.3.0V

A"
A,

Vee

1.5V

ADDRESS

'---------------------------OV

A,
A,

,...------.3.0V

0,

A.

CE 1 ,2

OUT

A,

1.SV

'-----------------------"+- - - - -

A,

0,

--r----""""'"+-------------

A,

1.5V

A,

ov
VOH

1.5V

'---------------------J·--VOL

A,
A,"

CE
_

GND

PROGRAMMING SYSTEMS SPECIFICATIONS

All inputs: t,

~

It

~

5ns 110% to 90%1

(Testing of these limits may cause programming of device.) T A = +25°C
LIMITS

PARAMETER

Vccp

Power supply voltage
To program 1

VCCH
VCCL
Vs
lecp

Verify limit
Upper
Lower
Verify threshold2
Programming supply current

VIH
VIL

I nput voltage
High
Low

IIH
IlL

I nput current
High
Low

VOUT

Output programming voltage 3

Max

8.5

8.75

9.0

5.3
4.3

5.5
4.5

5.7
4.7

1.4

1.5

V
Iccp = 375 ± 75mA,
Transient or steady state

Vecp

= +8.75 ±

.25V

1.6

V

300

450

mA

2.4
0

5.5
0.8
50
-500

lOUT = 200 ± 20mA,
Transient or steady state

= +17 ±

17.0

18.0

V

180

200

220

mA

10

tp

CE programming pulse width

0.3

Pulse sequence delay
Programming time

Tpsi

Initial programming pause

~

Programming duty cycle 4

1V

0.4

50

J1S

0.5

ms

12

sec

10

= Veep
Vee = OV

Vce

Fusing attempts Per link

Bypass Vee to GND with a 0.01 ~F capacitor to reduce voltage spikes.
Vs is the sensing threshold of the PROM output VOltage for a programmed bit. It normally constitutes
the reference voltage applied to a comparator circuit to verify a successful fusing attempt
Care should be t.::lken to insure the 17 ± 1 Voutput voltage is maintained during the entire fusing cycle.
Programming duty cycle is 50% after continuous programming at 100% duty cycle.
This is an updated method of programming and does not obsolete any programming systems
presently being used

SmnotiCs

J.JA

16.0

Output pulse rise time

to

VOUT

0.4

= +5.5V
= +O.4V

VIH
VIL

Output programming current

TpR

V

V

NOTES

136

Typ

lOUT

FL

3

Min

TR

TPR+ Tps

1.
2.

UNIT

TEST CONDITIONS

J1S

6

sec
50

%

2

cycle

82S184-1 .82S185-1

PROGRAMMING PROCEDURE
1. Terminate all device outputs with a 10kO
resistor to Vee. Apply CE = High.
2. Select the Address to be programmed,
and raise Vee to Veep = 8.75 ± .25V.
3. After 10,..s delay, apply VOUT = +17 ± 1V
to the output to be programmed. Program one output at the time.

4. After 1O,..s delay, pulse the CE input to
logic low for 0.3 to 0.5ms.
5. After 10,..s delay, remove +17V from the
programmed output.
6. To verify programming, after 1O,..s delay,
lower Vee to VecH =+5.5± .2V, and apply
a logic low level to the CE input. The
programmed output should remain in the

high state. Again, low Vcc to VecL = +4.5
± .2V, and verify that the programmed
output remains in the high state.
7. Raise Vce to Vccp = 8.75 ± .25V, and
repeat steps 3through 6 to program other
bits at the same address.
8. After 10,..s delay, repeat steps 2 through 7
to program all other address locations.

TYPICAL PROGRAMMING SEQUENCE

. ,.
"0"

Vee

E
w
E

_~r---------------------""'''''''------------''''-

ADD

A lAST

""'~!-

=
o

___________________-:--!-___________--1

...o-=

'--"--VeeL

c;:

DV

e.

OUTPUT
VOLTAGE

II

DV

"1"

Co
"0"

*Programming verification at both high and low Vee margins is optional. For convenience, verification
can also be executed at the operating Vee limits specified in the de characteristics.

S!!)OOtiCS

137

825190-1 .825191-1

OBJECTIVE 5PECIFICATION

.DESCRIPTION

APPLICATIONS

The 825190 and 825191 are field programmable, which means that custom patterns
are immediately available by following the
fusing procedure given in this data sheet.
The standard 825190 and 825191 are supplied with all outputs at logical low. Outputs
are programmed to a logic high level at any
specified address by fusing a Ni-Cr link
matrix.

•
•
•
•
•
•
•

PIN CONFIGURATION

Prototypinglvolume production
Sequential controllers
Microprogramming
Hardwired algorithms
Control store
Random logic
Code conversion

I pACKAGE*

These devices include on-chip decoding
and 3 chip enable inputs for ease of memory
expansion. They feature either open collector or tri-state outputs for optimization of
word expansion in bused organizations.
Both 825190 and 825191 devices are available in the commercial and military ranges.
For the commercial temperature range (0° C
to +75°C) specify N825190/191 , I, and for
the military temperature range (-55°C to
+125°C) specify 5825190/191, I.

FEATURES
• Address access time:
N82S190/191: 80ns max
S82S190/: 100ns max
• Power dissipation: 40/LW/blt typ
• Input loading:
N82S190!191: -100ILA max
S82S190/191: -150ILA max
• 3 chip enable inputs
• On-chip address decoding
• Output options:
82S190: Open collector
82S191: Tri-state
• No separate fusing pins
• Unprogrammed outputs are low level
• Fully TTL compatible

*' =Ceramic
BLOCK DIAGRAM

~

I
I

ADDRESS
LINES

CODER

I
I

A"

I
I

1:128 DE·

128X128
MATRIX

I

I

r--

1-------------1

A,
A,
A,
A,

CE;
CE,
CE,

;;:;.

1,16

1:16

1:16

1:16

MUX

MUX

MUX

MUX

1:1.
MUX

1:16

1:16

1:16

MUX

MUX

MUX

1 1 1 1 1 1 1 1

,...

~

::::

~

bbbbbbbb

01

O.

03

0..

Os

O.

0,

O.

OUTPUT LINES

ABSOLUTE MAXIMUM RATINGS
PARAMETER

VOH
Vo

5upply voltage
Input voltage
Output voltage
High (825140)
Off-state (825141)

TA

Temperature range
Operating

Vee
VIN

N825190/191
5825190/191

TSTG

138

5torage

SsgDotiCS

RATING

UNIT

+7
+5.5

Vdc
Vdc
Vdc

+5.5
+5.5
°C

o to +75
-55 to +125
-65 to +150

OBJECTIVE SPECIFICATION

82S190-1 .82S191-1

DC ELECTRICAL CHARACTERISTICS

N82S190/191: O°C:5 TA:5 +75°C, 4.75V:5 Vee:5 5.25V
S82S190/191: -55°C:5 TA:5 +125°C, 4.5V:5 Vee:5 5.5V
N82S190/191

PARAMETER

VIL
VIH
Vie

Input voltage
Low
High
Clamp

VOL
VOH

Output voltage
Low
High (82S191)

ilL
IIH

Input current
Low
High

10LK

Output current
Leakage (82S190)

10(OFF)

los

TEST CONDITIONS1

CIN
COUT

Capacitance
Input
Output

Max

Min

Typ2

Max

UNIT
V

2.0
liN

.80
2.0

= -18mA

-0.8

-1.2

-0.8

-1.2
V

lOUT = 9.6mA
lOUT = -2mA, CE1 = Low,
CE2 = High, CE3 = High,
High stored

0.45
2.4

0.5
2.4

p.A
VIN = 0.45V
VIN = 5.5V
VOUT = 5.5V,
CE2 = Low,
VOUT = 0.5V,
CE2 = Low,
VOUT = 5.5V,
CE2 = Low,
VOUT

Short circuit (82S191)
Vee supply current

Typ2

.85

Hi-Z state (82S191)

lee

Min

S82S190/191

-CE1 = High,
CE3 = Low
CE1 = High,
CE3 = Low
CE1 = High,
CE3 = Low
= OV

-20

-150
50

40

60

",A

-40

-60

",A

40

60

-70
130

Vee = 5.0V
VIN = 2.0V
VOUT = 2.0V

AC ELECTRICAL CHARACTERISTICS

-100
40

-15

175

130

-85

mA

185

mA
pF

5
8

5
8

R1 = 4700, R2 = lkO, CL = 30pF
N82S190/191: O°C:5 TA:5 +75°C, 4.75V:5 Vee:5 5.25V
S82S190/191: -55°C:5 TA:5 +125°C, 4.5V:5 Vee:5 5.5V
N82S190/191

PARAMETER

TO

FROM

Output
Output
Output

Min

S82S190/191
Typ2

Max

80
40

50
20

100
50

40

20

50

Typ2

Max

Address
Chip enable

50
20

Chip disable

20

Min

Access time
TAA
TeE

ns

Disable time
TCD

UNIT

ns

NOTES
1. Positive current is defined as into the terminal referenced.

2. Typical values are at Vee

= S.OV. TA = +2S'C.

!i[gDOIICS

139

=

o

E
w
E

...o
III:

a:

-

&.
II

8 'SUu Ute) 82SUI (I , )

IG.38 4 BIIBIPUEAR PHOM (2UUI8)
OBJECTIVE SPECIFICATION

828190-1 -82S191-1

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM

,r----------------YCC

A,

- - I - \ . ,-----------------_.,-----

A,

0,

A,

...

----+.1

J

R,

OUT

A.

0,

A,

·3.0Y

'--------------------------------OY

A,

1.5Y

,,----~------------_~--

·3.0Y

__ OY

TCD

0,

o.

1.SY

1.SY

'-----------'--·YOL

C L (INCLUDES SCOPE 6

A,

.,~~,~'"

A,

CE,
eEl.

All inputs: tr = t, • 5n. (10% to 90%)

-=- GND

PROGRAMMING SYSTEMS SPECIFICATIONS (Testing of these limits may cause programmin'g of device.) T A = +25°C
LIMITS
PARAMETER

Vccp

Power supply voltage
To program 1

VCCH
VCCL
Vs
Iccp

Verify limit
Upper
Lower
Verify threshold2
Programming supply current

VIH
VIL

Input voltage
High
Low

IIH
ilL

Inp.ut current
High
Low

VOUT

Output programming voltage 3

TEST CONDITIONS

Iccp = 375 ± 75mA.
Transient or steady state

Vccp

= +8.75 ± .25V

Typ

Max

8.5

8.75

9.0

5.3
4.3

5.5
4.5

5.7
4.7

1.4

1.5

V

1.6

V

450

mA

2.4
0

5.5
0.8

V

VIH
VIL

lOUT = 200 ± 20mA.
Transient or steady state

pA

= +17 ± 1V

50
-500
16.0

17.0

18.0

V

180

200

220

mA

50
0.5

iJS
ms

12

iJS
sec

Output programming current
Output pulse rise time

10

tp

CE programming pulse width

0.3

to

Pulse sequence delay
Programming time

Tpsi

Initial programming pause

TpR
TpR+Tps

Programming duty cycle4

VOUT

0.4

= +5.5V
= +O.4V

lOUT

TPR

V

300

TR

FL

0.4

10

= Vccp
Vcc = OV

Vcc

Fusing attempts per link

NOTES
1. Bypass Vee to GND with a O.otI'F capacitor to reduce voltage spikes.
2. Vs is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes
the reference voltage applied to a comparat.or circuit to verify a successful fusing attempt.
3. Care should be taken to insure the 17 ± 1Voutput voltage is maintained during theentire fusing cycle.
4. Programming duty cycle is 50% after continuous programming at 100% duty cycle.
S. This is an updated method of programming and does not obsolete any programming systems
presently being used.

1.40

UNIT
Min

6

sec
50

%

2

cycle

OBJECTIVE SPECIFICATION

PROGRAMMING PROCEDURE
1. Terminate all device outputs with a 10kD
resistor to Vcc. Apply CE, = High, CE2 =
High and CE3 = High.
2. Select the Address to be programmed,
and raise Vcc to Vccp = 8.75 ± .25V.
3. After 10l-'S delay, apply VOUT = +17 ± 1V
to the output to be programmed. Progam
one output at the time.

82S190-1 .82S191-1
4. After 10l-'s delay, pulse the CE, input to
logic low for 0.3 to 0.5ms.
5. After 10l-'S delay, remove +17V from the
programmed output.
6. To verify programming, after 1Ol-'S delay,
lower Vcc to VCCH=+5.5± .2V, and apply
a logic low level to the CE, input. The
programmed output should remain in the
high state. Again, lower Vcc to VCCL =

+4.5 ± .2V, and verify that the programmed output remains in the high
state.
1. Raise Vcc to Vccp = 8.75 ± .25V, and
repeat steps 3 through 6 to program other
bits at the same address.
8. After 10l-'s delay, repeatsteps2through 7
to program all other address locations.

w

"'" ~~------------------:--:------------.,---'-ADD

"0"

e

A LAST

AF1RST

"'""4------------------..!-L-----------..J
-----------------~---

Vee
OV

OUTPUT
VOLTAGE

=
e

o

TYPICAL PROGRAMMING SEQUENCE

BN

OV

B,

-

r

e.

II

"1"

CE,
"0"

*Programming verification at both high and low Vee margins is optional. For convenience, verification
can also be executed at the operating Vee limits specified in the de characteristics.

SmootiCS

...o

II:
G:

141

828100-I,N .82810H,N

DESCRIPTION

APPLICATIONS

The 828100 (tri-state outputs) and the
828101 (open collector outputs) are Bipolar
Programmable Logic Arrays, containing 48
product terms (AND terms), and 8 sum
terms (OR terms). Each OR term controls an
output function which can be programmed
either true active-high (Fp), or true activelow (Fil). The true state of each output
function is activated by any logical combination of 16-input variables, or their complements, up to 48 terms. Both devices are
field prog·rammable, which means that
custom patterns are immediately available
by following the fusing procedure outlined
in this data sheet.

•
•
•
•
•
•
•
•
•
•
•
•
•

PIN CONFIGURATION

CRT display systems
Random logic
Code conversion
Peripheral controllers
Function generators
Look-up and decision tables
Microprogramming
Address mapping
Character generators
Sequential controllers
Data security encoders
Fault detectors
Frequency synthesizers

I,N PACKAGE-

The 828100 and 828101 are fully TTL compatible, and include chip-enable control for
expansion of input variables, and output
inhibit. They feature either open collector or
tri-state outputs for ease of expansion of
product terms and application in busorganized systems.
Both devices are available in commercial
and military temperature ranges. For the
commercial temperature range (00 C to
+75° C) specify N828100/101,I or N, and for
the military temperature range (-55°C to
+125°C) specify 8828100/101,1.

FPLA EQUIVALENT LOGIC PATH

GND

'" = Ceramic
N = Plastic
tOpen during normal operation

TRUTH TABLE
MODE
Disabled
(828101)
Disabled
(828100)

Read

Pn CE Sr ~ f(Pn) Fp F-P
1

X

1

1

THERMAL RATINGS
TEMPER·
ATURE

X
Hi-Z Hi-Z

1
0

0
0

Yes

X

0

No

1
0

0
1

0

1

Maximum
junction
Maximum
ambient
Allowable thermal
rise ambient
to junction

Mill·
TARY

COMMER·
CIAL

175°C

150°C

125°C

75°C

50°C

75°C

LOGIC DIAGRAM
16
INPUTS
SUM MATRIX
(POSITIVE "OR" GATES)

"5 • • • • • • 11

.... F p. Fp·

'I>--a~

..

LOGIC FUNCTION

PRODUCT
TERMS

Typical Product Term:
Po = 10 • 11 • i;. 15· i;
Typical Output Functions:
Fo = (CE) + (Po + P1 + P2 ) @ 8 = Closed
Fa = (GE) +
f5;) @ 8 = Open

(Po· p,.

Vee

NOTE
For each of the 8 outputs. either the function Fp

(active-high) or F p (active low) is available, but not
both. The required function polarity is programmed
via link (5).

142

Si!JDotiCS

!!~

Fiiiiiiiiiiiiiillll'ISI'CIJOI(iTiSI'iai82Isl1CIJ11(IOICltli'

UIS Ie ARRAY (1&1' 811)

828100-I,N .828101-I,N

ABSOLUTE MAXIMUM RATINGS1
RATING

PARAMETER
Min

8upply voltage
Input voltage
Output voltage
Input currents
Output currents
Temperature range
Operating
N828100/101
8828100/101
8torage

Vee
VIN
VOUT
liN
lOUT
TA

TSTG

-30

0
-55
-65

DC ELECTRICAL CHARACTERISTICS
PARAMETER

Max

+7
+5.5
+5.5
+30
+100

UNIT

Vdc
Vdc
Vdc
mA
mA
°C

=
o

+75
+125
+150

E
w

E

N828100/101: 0° :5 TA:5 +75°C, 4.75V:5 Vee:5 5.25V
8828100/101: -55°C:5 TA:5 +125°C, 4.5V:5 Vee:5 5.5V

N82S1 00/1 01

TEST CONDITIONS

Min

Typ

S82S1 00/1 01
Typ

Min

Max

Max

UNIT

V

VIH
VIL
Vie

Input voltage3
High
Low
Clamp3,4

VOH
VOL

Output voltage
High (828100)3.6
Low3,6

Vce = Min
10L = 9.6mA
10H = -2mA

IIH
ilL

Input current
High
Low

10LK
IO(OFF)

Output current
Leakage7
Hi-Z state (828100)7

los

8hort circuit (828100)4.8

lee

Vee supply current9

CIN
COUT

Capacitance7
Input
Output

Vee = Max
Vee = Min
Vee = Min, liN = -18mA

2

2
-0.8

0.85
-1.2

0.8
-12

-0.8

V
2.4

2.4
0.45

0.35

0.50

VIN =5.5V
VIN = 0.45V

<1
-10

25
-100

<1
-10

50
-150

Vee = Max
VOUT =5.5V
VOUT = 5.5V
VOUT = 0.45V
VOUT= OV

1
1
-1

40
40
-40
-70

1
1
-1

60
60
-60
-85

mA

180

mA

p.A

-15

Vee = Max

120

170

120

Vee = 5.0V
VIN = 2.0V
VOUT = 2.0V

8

8

17

17

p.A
p.A

pF

AC ELECTRICAL CHARACTERISTICS R1 = 4700, R2 = 1kO, CL = 30pF
N8281oo/101: O°C:5 TA:5 +75°C, 4.75V:5 Vee:5 5.25V
8828100/101: -55°C:5 TA:5 +125°C, 4.5V:5 Vee:5 5.5V
PARAMETER

TO

FROM

Min

N82S1 00/1 01
Typ2 Max

S82S100/101

Min

Typ2

Max

TIA
TeE

Access time
Input
Chip enable

Output
Output

Input
Chip enable

35
15

50
30

35
15

80
40

TCD

Disable time
Chip disable

Output

Chip enable

15

30

15

40

UNIT

ns

ns

NOTES on follOWing page.

GlnatiCG

G:
~

oe.

-

II

0.35

-20

•

143

82S100-I,N .82S10H,N
NOTES
1. Stresses above those listed under"AbsoJute Maximum Ratings" may cause permanent damage to,the
device. This is a stress rating only and functional operation 01 the device of these or any other
I

condition above those indicated in the operation of the device speCifications is not implied.

2. All typical values are at Vee

= 5V, TA = 25"C.

3. All voltage values are with respect to network ground terminal.

4. Test one at the time.
5. Measured with V,L applied to CE and a logic high stored.
.
6. Measured with a programmed logic condition for which the output" test is at a low logic level. Output
sink current is applied thru a resistor to Vee.

7. Measured with: V,H applied to CE.
8. Duration of short circuit should not exceed 1 second.
9. Icc is measured with the chip enable input grounded, all other inputs at 4.5V and the outputs open.

VOLTAGE WAVEFORM

TEST LOAD CIRCUIT

INPUT PULSES

Vec

'5V

'

~r

QY----'I

~----

cL

R

:t

'":"

-

(INCLUDES
SCOPE AND JIG
CAPACITANCE)

Measurements: All circuit delays are measured at the

+1.5V level of inputs and outputs.

TIMING DIAGRAM
Output Polarity

READ CYCLE
+3.0V

OV
+3.0V

CE
OV
V OH

TIMING DEFINITIONS

3. The "OR" Matrix contains all 48-P-terms.

TCE

4 .The polarity of each output is setto active
high (Fp function).
5. All outputs are at a low logic .level.

TCD

TIA

Delay between beginning of Chip
Enable low (with Address valid)
and when Data Output becomes
valid.
Delay between when Chip Enable
becomes high and Data Output is
in off state (Hi-Z or high).
Delay between beginning of valid
Input (with Chip Enable low) and
when Data Output becomes valid.

VIRGIN DEVICE
The 82S100/101 are shipped in an unprogrammed state, characterized by:
1 . All internal Ni-Cr links are intact.
2. Each product term (P-term) contains both
true and complement values of every
input variable 1m (P-terms always logicalIy"false").

144

RECOMMENDED
PROGRAMMING PROCEDURE
To program each of 8 Boolean logic functions of 16 true or complement variables,
including up to 48 P~terms, follow the Program/Verify procedures for the "AND" matrix, "OR" matrix, and output polarity outlined below. To maximize recovery from
programming errors, I.eave all links in unused device areas intact.

SET-UP
Terminate all device outputs with a 10K
resistor to +5V. Set GND (pin 14) to OV.

S(gnatics

PROGRAM ACTIVE LOW
(Fp FUNCTION)
Program output polarity before programing "AND" matrix and "OR" matrix. Pro~
gram 1'output at the time. (S) links of unused
outputs are not required to be fused.

1.
2.
3.
4.

Set FE (pin 1) to VFEL.
Set Vcc (pin 28) to VCCL ..
Set CE(pin 19), and 10 through 115 to VIH.
Apply VOPH to the appropriate output,
and remove after a period tp.
5. Repeat step 4 to program other outputs.

VERIFY OUTPUT POLARITY
1. Set FE (pin 1) to VFEL; setVcb (pin 28) to
Vccs.
2. Enable the chip by setting CE (pin 19) to
VIL.
3. Address a non-existent P-term byapplying VIH to all inputs 10 through 115.
4. Verify output polarity by sensing the
logic state of outputs Fo through F7. All
outputs at a high logic level are programmed active low (Fp function), while
all outputs a't a low logic level are programmed active high (Fp function).
5. Return Vcc to Vccpor VCGL,

82S100-I,N .82S101-I,N

"AND" Matrix
PROGRAM INPUT VARIABLE
Program one input at the time and one Pterm at the time. All input variable links of
unused P-terms are not required to be
fused. However, unused input variables
must be programmed as Don't Care for all
programmed P-terms.
1.
2.
3.

4.

5 a.

5 b.

5 c.

6 a.
6 b.
6 c.
7.
8.
9.
1 O.

Set FE (pin 1) to VFEL, and Vee (pin 28)
to Veep.
Disable all device outputs by setting
CE (pin 19) to VIH.
Disable all input variables by applying
VIX to inputs 10 through I1s.
Address the P-term to be programmed
(No. 0 through 47) by forcing the corresponding binary code on outputs Fo
through Fs with Fo as LSB. Use standard TTL logic levels VOHF and VOLF.
If the P-term contains neither 10 nor TO
Q.nput is a Don't Care), fuse both 10 and
10 links by executing both steps 5b and
5c, before continuing with step 7.
!.!.the P-term contains 10, set to fuse the
10 link by lowering the input voltage at
10 from VIX to VIH. Execute step 6.
If the P-term contains 10, set to fuse the
10 link by lowering the input voltage at
10 from VIX to VIL. Execute step 6.
After to delay, raise FE (pin 1) from VFEL
to VFEH.
After to delay, pulse the CE input from
VIH to VIX for a period tp.
After to delay, return FE input to VFEL.
Disable programmed input by returning 10 to VIX.
Repeat steps 5 through 7 for all other
input variables.
Repeat steps 4 through 8 for all other Pterms.
Remove VIX from all input variables.

VERIFY INPUT VARIABLE
1. Set FE (pin 1) to VFEL: set Vee (pin 28) to
Veep.
2. Enable F7 output by setting CE to VIX.
3. Disable all input variables by applying VIX
to inputs 10 through I1s.
4. Address the P-term to be verified (No. 0
through 47) by forcing the corresponding
binary code on outputs Fo through Fs.

5. I nterrogate input variable 10 as follows:
A. Lower the input voltage at 10 from VIX
to VIH, and sense the logic state of
output F7.
B. Lower the input voltage at 10 from VIH
to VIL, and sense the logic state output
F7.
The state of 10 contained in the P-term is
determined in accordance with the following truth table:
INPUT VARIABLE STATE
CONTAINED IN P-TERM

10

F7

0
1

1
0

10

0
1

0
1

10

0
1

1
1

Don't Care

0
1

0
0

(10), (1;;)

"OR" MATRIX
PROGRAM PRODUCT TERM
Program one output at the time for one Pterm at the time. All Pn links in the "OR"
matrix corresponding to unused outputs
and unused P-terms are not required to be
fused.

4.

6a.
6b.
6c.
6d.

7.

9.

6. Disable verified input by returning 10 to
VIX.
7. Repeat steps 5 and 6 for all other input
variables.
8. Repeat steps 4 through 7 for all other Pterms.
9. Remove VIX from all input variables.

3.

5b.

8.

Note that 2 tests are required to uniquely
determine the state of the input variable
contained in the P-term.

1.
2.

5a.

Set FE (pin 1) to VFEL.
Disable the chip by setting CE (pin 19)
to VIH.
After to delay, set Vee (pin 28) to Vees,
and inputs 16 through I1s to VIH, VIL, or
VIX.
Address the P-term to be programmed
(No. 0 through 47) by applying the
corresponding binary code to input

Si!lDotiCS

variables 10 through Is, with 10 as LSB.
If the P-term is contained in output
function Fo (Fo = 1 or Fa = 0), got to step
6, (fusing cycle not required),
If the P-term is not contained in output
function Fo (Fo = 0 or Fa = 1), set to fuse
the Pn link by forcing output Fo to
VOPF.
After to delay, raise FE (pin 1) from
VFEL to VFEH.
After to delay, pulse the CE input from
VIH to VIX for a period tp.
After to delay, return FE input to VFEL.
After to delay, remove VOPF from output Fo.
Repeat steps 5 and 6 for all other output functions.
Repeat steps 4 through 7 for all other
P-terms.
Remove Vees from Vee.

VERIFY PRODUCT TERM
1. Set FE (pin 1) to VFEL.
2. Disable the chip by setting CE (pin 19) to
VIH.
3. After to delay, set Vee (pin 28) to Vees,
and inputs lothrough 115 to VIH, VIL, or VIX.
4. Address the P-term to be verified (No. 0
through 47) by applying the corresponding binary code to input variables 10
through Is.
5. After to delay, enable the chip by setting
CE (pin 19) to VIL.
6. To determine the status of the Pn link in
the "OR" matrix for each output function
Fp or Fp, sense the state of outputs Fo
through F7. The status of the link is given
by the following truth table:
OUTPUT

Active High Active Low
(Fp)
(Fp)

0
1

1
0

P-TERM LINK

Fused
Present

7. Repeat steps 4 through 6for all other Pterms.
8. Remove Vees from Vee.

145

=
o
E
w

E

82S100-I,N • 82S10H,N

OUTPUT POLARITY PROGRAM-VERIFY SEQUENCE (TYPICAL)

VOPH~90%Fp
TR

OUTPUT

VOLTAGE VOPl 10%
V

Vee

tp

~_ _ _ _ _-J~~_______

-!

_____

'ot-

0

ees_~~_~:.(V_E~RI_~-'.~_ _-r__~

VCCl

VIH--+--";"'.,

(PAUSEI

(PROGRAM)

"AND" MATRIX PROGRAM-VERIFY SEQUENCE (TYPICAL)

Vee = Veep
VOHF"""T------------------- ---- - ~ -VOLF-+_ _ _ _ _ _ _ _ _P_N_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~1 _ _ _

I-r----:....."..u----r--...--....."..--;'---~- - - - --..,.- - - -IL. _________
'm ~ L , . J

IL. ____ _

~

F,
(VERIFY OUTPUT)

_____ J

FUSE
ENABLE VFEl

CE

V,H1 _ _ _.;...J
VIL _ _ _

...:....:::!----'~

_____ --F______________________ _

"OR" MATRIX PROGRAM-VERIFY SEQUENCE (TYPICAL)
Vees ,......_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Vee

Vcep...J

-N
:,,: . .II------------P
- ------: ===::r::N~ ==
-)tol_ (Pn NOT IN Fp/Fp)

vOPF----y-- _ _ _ _ _ _ _ ,

V OH

fUSE
ENABLE

_I

'01__-::-:::=::-+-_1-,,-:-':''-:-1

vFEH -

V,H---H

146

r-----

,..-------...,

L..I

J-----.,

______ J______ ---1"-

Si!lnotics

~

i

i

82S100-I,N • 82S101-I,N
PROGRAMMING SYSTEM SPECIFICATIONS1
PARAMETER

Veel
lees

Vee supply (program/verify
"OR", verify output polarity)2
Vee supply (program output polarity)
lee limit (program "OR")

VOPH
VOPl

Output voltage
Program output polarity3
Idle

Vees

IOPH

Output current limit (Program output
polarity)

VIH
Vil

Input voltage
High
Low

ilH
ill

Input current
High
Low

VOHF
VOlF

Forced output voltage
High
Low

IOHF
IOlF

Output current
High
Low

VIX

CE program enable level

ilX1

Input variables current

ilX2

CE input current

VFEH

FE supply (program)3

VFEl

FE supply (idle)

IFEH

FE supply current limit

Veep

Vee supply (program/verify "AND")

leep

lee limit (program "AND")

VOPF

Forced output (program)

IOPF

Output current (program)

TR

Output pulse rise time

(TA = +25° C)
TEST CONDITIONS
lees = 550mA, min,
Transient or steady state

Min

LIMITS
Typ

Max

8.5

8.75

9.0

V

0
550

0.4

0.8
1,000

V
mA

Vees

= +8.75 ± .25V

IOPH

= 300 ± 25mA

16.0
0

17.0
0.4

18.0
0.8

= +17 ± lV

275

300

325

0.4

5.5
0.8

VOPH

UNIT

V

mA

V
2.4
0

JJ.A

VIH = +5.5V
Vil = OV

50
-500
V
2.4
0

0.4

VOHF = +5.5V
VOlF = OV

5.5
0.8

100
-1
9.5

10

JJ.A
mA

10.5

V

2.5

mA

5.0

mA

18.0

V

= +10V
VIX = +10V
IFEH = 300 ± 25mA,

16.0

17.0

Transient or steady state
IFEl = -lmA, max

1.25

1.5

1.75

V

275

300

325

mA

4.75

5.0

5.25

V

1,000

mA

VIX

VFEH = +17 ± 1V
leep = 550mA, min,
Transient or stead v state
Veep

= +5.0 ± .25V

550

10.5

V

10

mA

10

50
0.5

/J.s
ms5

9.5

tp

CE programming pulse width

0.3

tD

Pulse sequence delay

10

TPR

Programming time

10

0.4

/J.s
ms

0.6

TPR
Programming duty cycle
TPR + Tps
Fusing
attempts per link
Fl
Verify threshold4
Vs

1.4

1.5

50

%

2

cycle

1.6

V

NOTES

1. These are specifications which a Programming System must satisy in order to be qualified by
Signetics.
2. Bypass Vee to GND with a O.01~f capacitor to reduce voltage spikes.
3. Care should be taken to ensure that the voltage is maintained during the entire fusing cycle. The
recommended supply is a constant current source clamped at the specified voltage limit.
4. Vs is the sensing threshold of the FPLA output voltage for a programmed link. It normally constitutes
the reference voltage applied to a comparator circuit to verify a successful fusing attempt.
5. These are new limits resulting from device improvements, and which supersede, but do not obsolete
the performance requirements of previously manufactured programming equipment.

s;,gnDtics

147

=
o
E
w
E
c:

•...
o

e.
II

!trOLAR FilED eRQ§RJlMMABLE

82S100 (I S) 825101 (0 C )
82S100-I,N .82S10H,N

16X48X8 FPLA PROGRAM TABLE
PROGRAM TABLE ENTRIES
INPUT VARIABLE
Ul

1m

1m

OUTPUT FUNCTION
Prod. Term
Present in Fp

Don't Care

(.,)

A

Active
Low

H

L

j:

H
NOTE

NOTES

NOTES

Enter (-J for unused inputs of used
P-terms.

1. Entries independent of output polarity.
2. Enter (AJ for unused outputs 01 used P-terms.

1. Polarity programmed once only.
2. Enter (H) for all unused outputs.

"iii>-

L

(dash)

Active
High

Z

w

-

OUTPUT ACTIVE LEVEL

Prod. Term Not
Present in Fp

ID

PRODUCT TERM'
INPUT VARIABLE'
1- -1-

o
w
I-

w

...J

1"

1-'- '1-

NO.

--

0.

:IE

o(.,)

w

ID

oIZ

• (period)

---

.

--

---

21-

'3

-0

'! •. ,~

.." I

.....

:...... ..; :, .•. j'\. I:'

j:

a:

l:.'.:...:.:

.•.•. ' .

I'"
......••:.
1.'....... 1··· I ; . '

o0.
Ul

:t

'4

'5-

..... ' . ..

o

I-

6

I

.............'1>

.' ".' L .. i>

1,< I

-1- , , -

OUTPUT FUNCTION'

-7-

.'. '"

1 " ..... .... ' . .
. . . . ' : ~ b"
I, ·.····.1
........., i .. , .'..........,. i. ., ...., <;
Jf
L. ~,l..l>

.11

T-I- "

_-'_L-'._I_L_L-l._

5432109876543210

o .' . .

ACTIVE LEVEL'

-

.. 91
10
11
12
13
14
15
16
17
18
19

I:'

.',

.20'·'1"

:. .•. . . .........

1

•.. . .

.. .

1

•. , .. '

J..

24 I> ,'.'"
271
28 ..·1·.··

'."".

c·.

......;

>
....

I

. . .•. I
......

•· . 1.

I.

••.•......

; . . . •.

.... t

h:

..•:.

1

'j

•.•.

25 .....•
26,
. . I'"

, ','1\ :.•.,."'.

··.···.··1.

c.•. b
23

',,1...:.:

I.

.•.• •

.

I "

L___

L

::.::. L
-=
. . •.
..............

'"

I::.::. ___ ___
..

.....

...:.:
I

", ..

L

. .....•

I

~

L

--->L--->

30
31
32
33
34
35
36
37
38
39

'. 4C1'

...... ,.....

'.,

.'.

41

L.

42
43

......

... ,'.

;".'

44

"".
,

46
47

.• : I'·

I····

,',

......

r

I

" I. "."

";

S!!IDl!tiCS

.. '

................ ·.····1. ,. .

• Input and Output fields of unused p-terms can be left blank. Unused Inputs and outputs are F PLA terminals left floating.

148

....

....

, I,·,'

'.

.

.....
."

...•... Ii

....

......~

82S100-I,N .82S10H,N

PUNCHED CARD CODING
FORMAT

using standard 80-column IBM cards. For
each FPLA Program Table, the customer
should prepare in input card deck in accordance with the following format. Product
Term cards 3 through 50 can be in any

The FPLA Program Table can be supplied
directly to Signetics in punched card form,

order. Not all 48 Product Terms need to be
present. Unused Product Terms require no
entry cards, and will be skipped during the
actual programming sequence:

CARD NO.1-Free format within designated fields.
1 2 3 4 5 6 7 8 9

11 1 11 11 11 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 44 44 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 8
1 2 3 4 5 6 7 8 90 1 2 3 4 5 6 7 8 9 o , 2 3 4 5 6 7 8 9 0 1 2 34 5 6 7 8 9 o 1 2 3 4 5 6 7 8 9 o , 2' 3 4 5 6 78 9 0 , 2 3 4 5 6 7 8 9 0

o

C ,

REV

SIGNiTies

cusToM1R

1
PROGRAM TABLE NO.

NAME

I

REVISION
(1 ALPHA CHAR.)
SYMBOLIZED PART NO.

DEVICE NO

II

II

E
w
E

olTe

CARD NO. 211

, 2 3 4 5 6 7 8 9

o ,

, ,,, ,,, ,

2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 77 77 7 8
2 3 4 5 6 7 8 9 0 , 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 , 2 3 4 5 6 7 8 9 o , 2 3 4 5 6 7 8 9 o , 2 3 4 5 6 7 8 9 0 , 2 3 4 5 6 7 8 90

5 T X

"

I

"

OUTPUT ACTIVE LEVEl fS)

c.

COMMENTS (FREE FORMAT)

CARD NO.3 through NO. 50
,

'1'1'1,1'1'1' 2212121212121212213133333133313444414441444 • • 1• • • 1• • 1• • 1.16 61_1_1_1 __ 1_1 __ 17171717 7 7 717 7 7 8

2314151617181901121314151617189101'2345167 al9 0 123145617 B 90112341561781910 '12131415 6171s s101'1213

, 2

I

I

I

I I I II

1'5

I

I
10

I I I I I I

F7

I I

I

I

I

I

I

I

I

I

I

I I I I

I I

II I I

4 56\7890
I

Fo

'---'-N-PU-T-V-A-!r'A-B-l-E-{'-6-'---' oLU-TP-U-T-,-urIN-CT-'-O-N-'{BI
COMMENTS

'(~REE

FORMAT)

PRODUCT TERM NO. (00 THROUGH 47)

CARD NO. 51
, 2 3 4

.

_

__

,,,,,,
78 90 ,

•• ~I~ W
*I~

, , 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 • 5 5 • • 5
6 6 7 7 7 7 7 77 77 7 8
2 3 4 5 6 7 B 9 0 , 2 3 4 5 678 90 , 2 34 5 6 7 B 9 0 , 2 3 4 • 6 7 8 9 o , 2 3 4 • 6 7 85 9 0 , 2 3 4 5 6 7 8 9 0 , 2 3 4 • 6 78 9 0

E T X

I

I

II

I

COMMENTS (FREE FORMAT)

Output Active Level entries are determined
in accordance with the following table:

Input Variable entries are determined in
accordance with the following table:

OUTPUT ACTIVE LEVEL

INPUT VARIABLE

Active high
H

Active low
L

1m
H

-

1m
L

Don't care
- (dash)

Output Function entries are determined in
accordance with the following table:
OUTPUT FUNCTION
Product term
present in Fp
A

Product term not
present in Fp
• (period)

NOTES

NOTE

NOTES

1. Polarity programmed once only.

Enter (-) for unused inputs of used' P-terms.

1. Entries independent of output polarity.
2. Enter (A) for unused outputs of used P-terms.

2. Enter (H) for all unused outputs.

Smnl!tiCS

•a:...
o

.-.

I

TOTAL PRODUCT TERMS useD (2 DECIMAL DIGITS)

=
o

149

82S100-I,N .82S10H,N

TWX TAPE CODING FORMAT
The FPLA Program Table can be sent to
Signetics in ASCII code format via airmail
using any type of 8-level tape (paper, mylar,
fanfold, etc.), or via TWX: just dial (910) 339-

9283, tell the operator to turn the paper
puncher on, and acknowledge. At the end of
transmission instruct the operator to send
tape to Signetics Order Entry.

quentially assembled on a continuous tape
as follows, however limit tape length to a roll
of 1.75 inch inside diameter, and 4.25 inch
outside diameter:

A number of Program Tables can be se25
RUBOUTS
MIN.

(C/R)
MIN.

25 ., - - - -1-':' 1

SUB- I -

25
I PROGRAM TABLE:
I
DATA (1)
I

HEADING
(N)

I

I

1;:-

17

I PROGRAM TABLE I ilITRAILER(
DATA (N)
I tJ I (C/R) 1\
---1 _ _ _ _ I....:::L _-1-;;'

RUBOUTS
MIN.

_ _ 1_ _

A. The MAIN HEADING atthe beginning of tape includes the following information, with each entry preceded by a ($) character,
whether used or not:
1. Customer Name

4. Purchase Order No. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

2. Customer TWX No. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

5. Number of Program Tables _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

3. Date _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

6. Total Number of Parts _ _ _ _ _ _ _ _ _ _ _ _- - - - - -

B. Each SUB HEADING should contain specific information pertinent to each Program Table as follows, with each entry
preceded by a ($) char--t>""'"- F p. Fp·

LOGIC FUNCTION
Typical Product Term:
Po = 10 • I,.
Is· I;;;

G·

Typical Output Functions:
Fo = (CE) + (Po + P, + P2 ) @ S = Closed
Fa = (CE) +
15;) @ S = Open

(Po'. p;.

Vee
NOTE
For each of the B outputs, either the function Fp
(active-high) or
(active Jow) is available, but not

Fp

both. The required function polarity is programmed

via link (S)

152

SmnOlms

BIPOLAR MASK PROGRAMMABLE

[OGIC ARRAY (16X4IXI)
82S200-I,N .82S20H,N

ABSOLUTE MAXIMUM RATINGS 1
RATING
UNIT

PARAMETER
Vee
VIN
VOUT
hN
lOUT
TA

TSTG

Supply voltage
I nput voltage
Output voltage
I nput currents
Output currents
Temperature range
Operating
N82S200/201
S82S200/201
8torage

DC ELECTRICAL CHARACTERISTICS

-30

0
-55
-65

+7
+5.5
+5.5
+30
+100

Vdc
Vdc
Vdc
mA
mA
°C

=
o

+75
+125
+150

E
w

N825200/201

PARAMETER

TE5T CONDITIONS

VIH
Vil
Vie

Input voltage3
High
Low
Clamp3,4

VOH
VOL

Output voltage
High (828200)3,5
Low3,6

Vee = Min
10H = -2mA
10l = 9.6mA

hH
hl

Input current
High
Low

10lK
10(OFF)

Output current
Leakage7
Hi-Z state (828200)7

los

8hort circuit (828200)4,8

lee

Vee supply current9

CIN
COUT

Capacitance7
Input
Output

E

N828200/201: 0° :S TA:S +75°C, 4.75V :S Vee:S 5.25V
8828200/201: -55°C:S TA:S +125°C, 4.5V S; Vee:S 5.5V

Min Typ2 Max

5825200/201

Min Typ2 Max

UNIT
V

Vee = Max
Vee = Min
Vee = Min, liN 7 -18mA

2

2
-0.8

0.85
-1.2

-0.8

0.8
-1.2
V

2.4

2.4
0.35

0.45

0.35

0.50

VIN = 5.5V
VIN = 0.45V

<1
-10

25
-100

<1
-10

50
-150

Vee = Max
VOUT = 5.5V
VOUT = 5.5V
VOUT = 0.45V
VOUT = OV

1
1
-1

40
40
-40
-70

1
1
-1

60
60
-60
-85

mA

180

mA

fJ.A

-20

Vee Max

120

Vee = 5.0V
VIN = 2.0V
VOUT = 2.0V

8
17

SagDotiCS

170

-15
120

fJ.A
fJ.A

pF
8
17

153

•c:...
o

-..
c.

1
825200-I,N • 825201-I,N

AC ELECTRICAL CHARACTERISTICS R1

= 4700, R2 = 1kO, CL = 30pF
N825200/201: O°C:5 TA :5 +75°C, 4.75V:5 Vee :5 5.25V
5825200/201: -55°C:5 TA:5 +125°C, 4.5V:5 Vee:5 5.5V

PARAMETER

TO

FROM

N82S200/201
Typ2
Min
Max

S82S2OO/201
Typ2
Min
Max

UNIT
ns

TIA
TeE

Access time
Input
Chip enable

Output
Output

Input
Chip enable

35
15

50
30

35
15

80

Teo

Disable time
Chip disable

Output

Chip enable

15

30

15

50

50
ns

NOTES
1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only. and functional operation of the device of these or any other
condition above those indicated in the operation of the device specifications is not implied.
2. All typical values are at Vee = 5V, TA = 25°C.
3. All yoltage values are with respect to network ground terminal.
4. Test one at the time.
5. Measured with Vil applied to CE and a logic high stored.
6. Measured with a programmed logic condition for which the output test is at a low logic level. Output
sink current is applied thru a resistor to Vee.
7. M~.asured with: VIH applied to CE.
8. Duration of short circuit should not exceed 1 second.
9. Icc is measured with the chip enable input grounded, all other inputs at 4.SV and the outputs open.

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM
INPUT PULSES

Vcc

'6V

F.

F,

~
'_ r
'

R

-

-

'!Y-------'I

+30V---_

CL
IINCLUDES
SCOPE AND JIG
CAPACITANCE)

Measurements: All circuit delays are measured at
the +1.5V level of inputs and outputs.

TIMING DIAGRAM
READ CYCLE

.OV
r--------.. . . .---------.3
'--------------------OV
r-------

TIMING DEFINITIONS
TeE

'3.0V

'--------------J+-----------OV

Teo

,--------~----+~VOH

TIA

154

S!!I00liCS

Delay between beginning of Chip
Enable low (with Address valid)
and when Data Output becomes
valid.
Delay between when Chip Enable
becomes high and Data Output is
in off state (Hi-Z or highl.
Delay between beginning of valid
Input (with Chip Enable low) and
when Data Output becomes valid.

82S200-I,N • 82S201-I,N

16X48X8 PLA PROGRAM TABLE
PROGRAM TABLE ENTRIES
INPUT VARIABLE
1m

-1m

Don't Care

H

L

-

III

0

i=
W

Z
CJ

iii
>

""

lII:

I-

z

«CL

i=

UJ

0

t::::!
--'

0

0

II:
Q.

0

~

::;;

I-

00

aJ

:r:

>

II:

~
LL

u

UJ

>

ijj

00

UJ

U

I-

0

II:

00

I-

::;;
::;;

u

0

U

X ::;;
X
X

0

I-

:J

UJ

UJ

«

z

UJ

0

00

III:

UJ

::i!:

"" U*'

II:

UJ

UJ

«CL

u.
0

*'

UJ

0 :;: a: ...J UJ
CD I« a:
UJ UJ
Z 0 0 aJ « «
I- 0

II:
UJ

::i!:
0

I-

(J)

:l
U

UJ

(J)

:l

Cl

::i!:

::i!:
«
« Ui= z II:
J: UJ ...J
U Z « Cl
Ia:
(J)

Q.

iii

:J

0

I-

0

B:

I

>
UJ
a:

H

L

1. Entries independent of output polarity.
2. Enter (Al for unused outputs of used P-terms.

,. Polarity programmed once only.
2. Enter (~) for all unused outputs.

~

0

Active
Low

Enter (-J for unused inputs of ·used
P-terms.

Q.

0
w

• (period)

Active
High
NOTES

NO.

aI

A

(dash)

OUTPUT ACTIVE LEVEL

NOTES

cW

0

Prod. Term Not
Present in Fp

NOTE

aI

IW
-t

OUTPUT FUNCTION
Prod. Term
Present in Fp

PRODUCT TERM"
INPUT VARIABLE"
---r--1- 1 1 1 1 1
f5 4 3 2 1 0 9 8 7 6

--

r-.,.

--- --5 4 3 2 1 0

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

ACTIVE LEVEL"

-1-

r -, -1-'-"'-

1--'- L....L _1_ L_L...1_
OUTPUT FUNCTION"
1 - - - .- - r
-r-7 6 5 4 3 2 1 0

I;

o

E
w
E
c:

.-...

..o•-

.

-Input and Output fields of unused P-terms can be left blank. Unused inputs and outputs are PLA terminals left floating.

Smnotics

155

I

II

82S20Q-I.N • 82S201-I,N

PUNCHED CARD CO.DING
FORMAT
The PLA Program Table can be supplied
directly to Signetics in punched card form,

using standard SO-column IBM cards. For
. each PLA Program Table, the customer
. should prepare an input card deck inaccordance with the following format. Product
Term cards 3 through 50 can be in any

order. Not all 48 Product Terms need to be
present. Unused Product Terms require no.
entry cards, and will be skipped during the
actual programming sequence:
.

CARD NO.1-Free format within designated fields.

,,,,,,,,

, , 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4444 4 4 4 5 6 5 5 6 6 5 6 6 5 6 6 6 6 6 6 6 6 . 6 7 77 7 7 777 7 78
, 2 3 45 6 7 8 9 0 1 2 3 4 6 67 8 9 0 , 2 34 5 6 7 • 9 0 , 2 34 5 6 7 8 9 0 , 2 34 5 6 7 8 9 0 , 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 90 , 2 34 567 . 9 0

C F

REV

S'GNiTics

1

CUSTOM!R NAME

PROGRAM TABLE NO.

DEVICE NO.

I

REVISION
(1 ALPHA CHAR.)
SYMBOLIZEO PART NO.

II

olTE

CARD NO. 2-

,,

, 2 3 4 5 6 7 .8 9

o,

,"

, 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 444 4 4 4 5 5 5 6 6 5 5 6 6 5 6 6 6 . 6 6 6 • 66 7 77 7 7 777778
1,',1
2 3 4 6 6 7 8 9 0 , 2 3 4 5 • 7 8 • o , 2 3 4 5 6 7 8 9 0 1 2 3 4 6 • 7 8 9 0 , 2 3 45 6 78 90 , 2 34 6 6 7 8 . 0 , 2 3 4 687890

S T X

F,

F,

I

TOTAL PRODUCT TERMS USED (2 DECI~AL DIGITS)

OUTPUT ACTIVE LEVEL (8)

CARD NO.3 through NO. 50

I

COMMENTS (FREE FORMAT)

..

,, ,"
"
"

, 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 44 4 4 • • • 5 5 6 5 5 5 6 5 5 •. 6 6 • 6 6 • 6 6 • 6 77 7 7 7 777 778
, 2 3 • 5 6 7 8 9 0 , 2 3 • 6 6 7 8 9 0 , 2 3 • 6 • 7 8 9 o , 2 3 4 5 6 7 B 9 0 , 2 3 4 6 6 7 8 9 0 , '2 3 • 5 6 7 8 9 0 , 2 3 • 5 6 7 • 9 0 , 2 3 • 6 • 7 . 9 0

I,

I"

INPUT VAl,ABLE ('6)

F,

OUTPUT

F,

FU~CTION

(8)

COMMENTS (tREE FORMAT)

PROOUCT TERM NO. (00 THROUGH 41)

CARD NO. 51

,," , ,
"

•• ••

••

., 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 . 4 4 • 4 4 • 444- 5 6 5 5 ~ 5 6 5 5 6
;
6 7 77 7 7 7 7 77 7 B
6 ••
, 2 3 . 5 • 7 890 , 2 3 4 5 6 7 B 9 0 , 2 3 4 6 • 7 B 9 0 , 2 3 • 5 • 7 B 9 0 , 2 34 6 6 7 B 9 o , 2 3 • 5 • 7 B 9 0 ' 2 3 45 6 7 B 9 0 , 2 3 • 5 6 7 B 9 0
E T X

I

COMMENTS (FREE FORMAT)

Dutput Active Level entries are determined
in accordance with the following table:

Input Variable entries are determined in
accordance with the following table:

OUTPUT ACTIVE LEVEL

INPUT VARIABLE

Active high
H

Active low
L

1m
H

1m
L

[lon't care
- (dash)

NOTES

NOTE

1. Polarity programmed once only.
2. Enter (H) for all unused outputs.

Enter (-) for unused inputs of used P-terms.

156

smootiCS

Output Function entries are determined in
accordance with the following table:
OUTPUT FUNCTION
Product term
present in Fp
A

Product term not
present in Fp
-(period)

NOTES
1. Entries independent of output polarity.
2. Enter (A) for unused outputs of used P-terms.

~

i

1111

i
82S200-I,N • 82S20H,N

TWX TAPE CODING FORMAT
The PLA Program Table can be sent to
Signetics in ASCII code format via airmail
using any type of 8-level tape (paper, mylar,
fanfold, etc.), or via TWX: just dial (910) 339-

quentially assembled on a continuous tape
as follows, however limittape length to a roll
of 1.75 inch inside diameter, and 4.25 inch
outside diameter:

9283, tell the operator to turn the paper
puncher on, and acknowledge. At the end of
transmission instruct the operator to send
tape to Signetics Order Entry.
A number of Program Tables can be se25

I

25

RUBOUTS I PROGRAM.T ABLE I (C/R) .
MIN.
I
DATA (1)
I MIN.

25 --, - - -

1;;-

SuB- I -1--;:'
'7
HEADING I RUBOUTS I PROGRAM TABLE I
I TRAILERk
(N)
I MIN. I
DATA (N)
I b I (C/R) I,

-

it

_ ' _ _ -1 _ _ _ _ I-::::'L_...L..:'>

A. The MAIN HEADING at the beginning oftape includes the following information, with each entry preceded by a ($) character,
whether used or not:
1. Customer Name

4. Purchase Order No. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

2. Customer TWX No. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

5. Number of Program Tables _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

3.0ate _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

6. Total Number of Parts _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

B. Each SUB HEADING should contain specific information pertinent to each Program Table as follows, with each entry
preceded by a ($) character, whether used or not:
1. Signetics Device No.

4. Oate _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

2. Program Table No. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

5. Customer Symbolized Part No. _ _ _ _ _ _ _ _ _ _ _ _ _ __

3. Revision

6. Number of Parts

~---

C. Program Table data blocks are initiated with an STX character, and terminated with an ETX character. The body of the data
consists of Output Active Level, Product Term, and Output Function information separated by appropriate identifiers in
accordance with the following format:

II

START OF DATA TEXT
(CONTROL A or B)
START OF DATA
FIELD
ACTIVE LEVEL
IDENTIFIER
[ ACTIVE LEVEL DATA
(8 DIGITS. H/L)

STX' A

I

I

frU[

START OF DATA FIELD
~ PRODUCT TERM IDENTIFI ER
[
1 SPACE (MANDATORY)
PRODUCT TERM NUMBER
(2 DECIMAL DIGITS)
START OF DATA FIELD
INPUT VARIABLE IDENTIFIER
INPUT VARIABLE DATA
I
(16DIGITS,H/LI-)

F7F6F5F4F3F2F1Fo' P

[

1

OUTPUT FUNCTION IDENTIFIER
OUTPUT FUNCTION DATA
INPUT AND OUTPUT DATA FOR
(8 DIGITS, No)
ALL PRODUCT TERMS USED

i i i

1

END OF DATA TEXT
(CONTROL C)

START OF DATA FIELD

I.- _ _ _ _ ~ _ _ _ _ _ _ ..,

00' I 1'51'41'31'21,,1'019161716151413121,10' F F7F6F5F4F3F2F,Fo' P

01 .... :

F .... :

P .......... Fo ETX

Entries for the 3 Data Fields are determined in accordance with the following Table:
INPUT VARIABLE
1m
H

Tm
L

Don't care
- (dash)

NOTE
Enter (-) for unused inputs of used

P~terms.

OUTPUT FUNCTION
Product term
present in Fp
A

Product term not
present in Fp
o (period)

OUTPUT ACTIVE LEVEL

Active high
H

Active low
L

NOTES

NOTES

1. Entries independent of output polarity.

1. Polarity programmed once only.

2. Enter (A) for unused outputs of used P-terms.

2. Enter (H) for all unused outputs.

Although the Product Term data are shown entered in sequence, this is not necessary. It is possible to input only one Product
Term, if desired. Unused Product Terms require no entry. ETX signalling end of Program Table may occur with less than the
maximum number of Product Terms entered.
NOTES
1. Corrections to any entry can be made by backspace and rubout. However, limit consecutive rubouts
to less than 25.
2. P-Terms can be re-entered any number of times. The last entry for a particular P-Term will be
interpreted as valid data.
3. Any P-Term can be deleted entirely by inserting the character (E) immediately following the P-Term
number to be dele'ed. i.e .• 'P 25E dele'es P-Term 25.
4. To facilitate an orderly Teletype print out, carriage returns, line feeds, spaces, rubouts etc. may be
interspersed between data groups, but only preceding an asterisk (*).
5. Comments are allowed between data fields. provided that an asterisk (*) is not used in any Heading or
Comment entry.

Si!lDotiCS

157

=
o
E
w
E

-=

a:
..,

..-

o

II

82S200-I,N • 82S201-I,N

TYPICAL APPLICATIONS
SUBROUTINE ADDRESS MAP

(4)
STATUS
(PLA) 2

(4)

BRANCH LOGIC

JUMP CONDIT.
(8)

CONTHOL FIELD

SEQUENTIAL CONTROLLER

PARITY

DATA

(12)

PARITY

GENERATOR

CLOCK - - - - -....

158

sagDOliCS

BIPOLAR FIELD PROGRAMMABLE GAIEARRAY (16X9)

82S)02 (0 C ) 828103 (J 8 )
828102-I,N .828103-I,N

DESCRIPTION

FEATURES

The 828102 and 828103 are Bipolar programmable AND/NAND gate arrays, containing 9 gates sharing 16 common inputs.
On-chip input buffers enable the user to
individually program for each gate either
the True (Iml, Complement (1;;;1, or Don't
Care (XI logic state of each input. In addition, the polarity of each gate output is
individually programmable to implement
either AND or NAND logic functions.

•
•
•
•
•

Alternately, if desired, ORINOR logiC functions can also be realized by programming
for each gate the complement of its input
variables, and output (DeMorgan theorem\.
Both devices are field-programmable,
which means that custom patterns are
immediately available by following the fusing procedure outlined in this data sheet.
The 828102 and 828103 include chipenable control for output strobing and inhibit. They feature either open collector or
tri-state outputs for ease of expansion of
input variables and application in busorganized systems.
Both devices are available in the commercial and military temperature ranges. For
the commercial range (0°Cto+75° C) specify N82S102/103, lor N, and for the military
range (-55° C to +125° C) specify
S82S102/103, I.

•
•

•

•

•

PIN CONFIGURATION

Field programmable (Ni-Cr link)
16 input variables
9 output functions
Chip enable input
1/0 propagation delay:
N825102l103: 30ns max
5825102/103: SOns max
Power dissipation: 600mW typ
Input loading:
N825102/103: -100I'A max
5825102/103: -150I'A max
Output options:
825102: Open collector
825103: Tri-state
Output disable function:
825102: Hi
825103: Hi-Z
Fully TTL compatible

I,N PACKAGE'

Random logic
Address decoders
Code detectors
Peripheral selectors
Fault monitors
Machine state decoders

(Is)

;,(Ie)

0
E
w
E

I" (to)

I,,; (IF)

CE

APPLICATIONS
•
•
•
•
•
•

=

(IA)

1

-=
c:
0

...

GND
*1

= Ceramic

N = Plastic

LOGIC DIAGRAM
,-----------------------------------,

F.

F.

For each of the 9 outputs, either the function Fp (active high) or Fp (active lowl is available, but not both.
The required function polarity is user programmable via fuse (S)'

S!!Inl!tiCS

159

..--=

82S102-I,N .82S103-I,N

ABSOLUTE MAXIMUM RATINGS
.

PARAMETER

Supply voltage
I nput voltage
Output voltage
High (825102)
Off-state (825103)
I nput current
Output current
Temperature range
Operating

Vee
V,N
VOH
Vo
liN
lOUT
TA

UNIT

+7
+5.5

Vdc
Vdc
Vdc

+5.5
+5.5
±30
+100

:=D-z:=D-z

1

1

RexT

I

I

I

I

I

I"

old
I

IS)

:

The Field Programmable Gate Array consists of 9 gates with individually programmable inputs and outputs.
The inputs to each gate can be programmed
either True (1m), Complement (i;;;), or Don't
Care via corresponding links (j) and (kl. The
outputs of each gate can be programmed
active-high (Fp) or active-low (F~) via corresponding links (5). Thus, each gate provides
either of 2 output logic functions in terms of
external input logic variables Xm as defined
below (positive logic):
AtS=Open:
Fp

= OE + (Xo •

Xl • X2 ••... Xm)

= Yp

At S = Closed:

Fp = CE + (Xo + Xl + X2 + .... Xm) = yp
m

= 0,1,2, ..... 15

:··i I
~!.
I

1

FIELD
PROGRAMMABLE

~~,

Ii,m.

p = 0,1,2, ..... 8
and where Xm = 1m, i;;;, Don't Care, as assigned by programming polarity of Inputs
Io-hs.

When CE = low, all gates are enabled, and
Fp = I'p giving yp = Yp.

PROGRAMMABLE LOGIC
FUNCTIONS
All internal links of virgin FPGAs are intact.
Therefore, as shown in the Equivalent Logic
Path, all symbolic switches are initially
closed. Selective programming (opening) of
links (J), (K), and (5) enables the user to
assign input and output polarities to each
gate for implementing NAND, NOR, AND,
OR logic functions without changing the
routing of input and output wires. This is
shown in the following diagrams for a typical gate in terms of 2 input variables, which
can be readily extended up to 16.

IF,,.....
I

~T:~____________~~

160

Y~ Y~

OR

<;>

l

X~·z·X~z

mA
mA
·C

EQUIVALENT LOGIC PATH

I

OR

o to +75
-55 to +125
-65 to +150

N82S102/103

88251021103
Storage

TSTG

RATING

9i!110liC9

82S102-I,N .82S103-I,N

DC ELECTRICAL CHARACTERISTICS
PARAMETER1

N82S1 02/1 03: O°C:S TA:S +75°C, 4.75V:S Vee:S 5.25V
8828102/103: -55°C:s TA:S +125°C, 4.5V:S Vee:S 5.5V
TEST CONDITIONS

VIL
VIH
Vie

Input voltage
Low1
High1
Clamp1.3

VOL
VOH

Output voltage
LOW1.4
High (828103)1.S

ilL
IIH

Input eurrent
Low
High

IOLK
10(OFF)

Output current
Leakage (828102)6
H i-Z state (828103)6

S82S1021103
Typ2
Min
Max

0.85

0.8

UNIT
V

Vec = Min
Vec = Max
Vcc = Min, liN = -18mA

Ice

Vee supply currentS

CIN
COUT

Capacitance
Input
Output6

2.0

Vcc = Min
10L= 9.6mA
10H = -2mA

Short circuit (828103)3,7

los

N82S1021103
Typ2
Min
Max

R1

-1.2

-0.8

-1.2

0.35

0.45

0.35

0.50

V
2.4

2.4
/-I A

VIN = 0.45V
VIN = 5.5V

-10
<1

-100
25

-10
<1

-150
50

Vec = Max
VOUT = 5.5V
VOUT = 5.5V
VOUT = 0.45V
VOUT = OV

1
1
-1

40
40
-40
-70

1
1
-1

60
60
-60
-85

mA

= Max

120

170

120

180

mA

Vcc = 5.0V
VIN = 2.0V
VOUT = 2.0V

8
15

Vec

AC ELECTRICAL CHARACTERISTICS

2.0
-0.8

-20

-15

w

/-I A
/-I A

pF

= 470.0, R2 = 1k.o,

CL

8
15

= 30pF

N828102/103: O°C:S TA:S +75°C, 4.75V:S Vcc:S 5.25V
8828102/103: -55°C:S TA:S +125°C, 4.5V:S Vcc:S 5.5V
PARAMETER

TO

FROM

N82S10211 03
Typ2
Max
Min

S82S103/103
Min

Typ2

Max

UNIT
ns

TIA
TCE

Access time
Input
Chip enable

Output
Output

Input
Chip enable

20
15

30
30

20
15

50
40

TCD

Disable time
Chip disable

Output

Chip enable

15

30

15

40

ns

NOTES
1. All voltage values are with respect to network ground terminal.
2. All typical values are at Vee SV. TA 2SoC.

=

=

3. Test each output one at a time.

4. Measured with a programmed logic condition for which the output under test is at a low logic level.
Output sink current is supplied through a resistor to Vee.
Measured with Vil applied to 'O'E' and a logic high at the output.
Measured with V,H applied to ~.
Duration of short circuit should not exceed 1 second.
Icc is measured with the chip enable input grounded, all other inputs at 4.5V and the outputs open.

5.
6.
7,
S.

TEST LOAD CIRCUIT

VOLTAGE WAVEFORM
,..-------------------.3.ov

'-----------------------------w
cc

Fo

Fa

~

,...----.3.0V

R,

R,

~----------------------J'+_---------OV

Cl
IUNClUDES
SCOPE AN 0 JIG

,...------------------------~TVOH
1.SV

':' -= CAPACITANCE)

All inputs: t,

Si!lnOliCS

=
a

= tf = Sns 110% to 90%1

161

E

•a:-oe.

.-.

82S102-I,N .82S103-I,N

OUTPUT POLARITY PROGRAM-VERIFY SEQUENCE (TYPICAL)
Vccp __......_ _ _ _ _ _.,
Vcc
VCCv

J

(Fp)

U

(Fp-+')

u

Input Matrix
PROGRAM INPUT VARIABLE

(Fp+2)

Program one input at a time for one gate at a
time. Input variable links of unused gates
are not required to be fused. However, unused input variables must be programmed at
Don't Care for all used gates.
1.

L._-I

cr

V,H _ _ _ _..J

INPUT MATRIX PROGRAM-VERIFY SEQUENCE (TYPICAL)
TPR (PROGRAM)

- I (P:~~E) r--

_ _ _ ..!..m"::,,H___ ...,
tOf-

vccp Vcc

Vil __ L

,....J
...

I _ _ _ _~.l
_ _ _ _ _ -',....J
L

-i------.,

vOH---.Jf

crV1H - - - " " ; ; " : " : : ;
V 1L - -

VIRGIN DEVICE
The 82S102/103 are shipped in an unprogrammed state, characterized by:
1 . All internal Ni-Cr links are intact.
2. Each gate contains both true and complement values of every input variable 1m
(logic Null state).
3. The polarity of each output is set to active
low (Fp function).
4. All outputs are at a high logic level.

RECOMMENDED
PROGRAMMING PROCEDURE
To program each of 9 Boolean logic functions of 16 True, Complement, or Don't Care
input variables follow the program/verify
procedures for the Input Matrix and Output
Polarity outlined below. To maximize recovery from programming errors, leave all
links of unused gates intact.
SET-UP
Terminate all device outputs with a 10K!}
resistor to +SV.

Output Polarity
PROGRAM ACTIVE HIGH (Fp FUNCTION)
Program output polarity before programming inputs (for convenience). Program one
output at a time. (S) links of unused outputs
are not required to be fused.

162

1. Set GND (pin 14JtoOV, and Vee (pin 28) to
Veev.
2. Disable all device outputs by setting CE
(pin 19) to VIH.
3. Disable all input variables by applying VIX
to inputs 10 through 115.
A .Raise Vee (pin 28) from Veev to Veep.
B After to delay, force output to be programmed to VOPF.
C .Afterto delay, pulsethe CE input from VIH
to VIX for a period tp.
D .After to delay, remove VOPF voltage
source from output being programmed.
E .After to delay, return Vee (pin 28Jto Veev,
and verify.
F. Repeat steps A through E for any other
output.
VERIFY OUTPUT POLARITY
1 . Set GND (pin 14) to OV, and Vee (pin 28) to
Veev.
2. Disable all input variables by applying VIX
to inputs 10 through 11!).
A .After to delay, set the CE input to VIL.
B .Verify output polarity by senSing the
logic state of outputs Fo through Fa. All
outputs at a low logic level are programmed active low (Fp function), while
all outputs at a high logic level are programmed active high (Fp function).

Set GND(pin 14JtoOV,andVee(pin28)
to Veev.
2. Disable all device outputs by setting
CE (pin 19) to VIH.
3. Disable all input variables by applying
VIX to inputs 10 through 115.
A -1 .If a gate contains nether 10 nor iO (input
is a Don't Care), fuse both j and k links
by executing both steps A-2 and A-3,
before continuing with step C.
A - 2 .If a gate contains 10, set to fuse the k
link by lowering the input voltage at 10
from VIX to VIH. Execute step B.
A-3.lf a gate contains iO, settofusethej link
by lowering the input voltage at 10 from
VIX to VIL. Execute step B.
B-1 .After to delay, raise Vee from Veev to
Veep.
B-2.After to delay, force output of gate to
be programmed to VOPF.
B-3.After to delay, pulse the CE input from
VIH to VIL for a period tp.
B -4 .After to delay, remove VOPF voltage
source from output of gate being programmed.
B -S .After to delay, return Vee (pin 28) to
Veev, and verify.
C. Disable programmed input by returning 10 to VIX.
D. Repeat steps A through C for all other
input variables.
E. Repeat steps A through D for all other
gates to be programmed.
F. Remove VIX from all input variables.
VERIFY INPUT VARIABLE

Unambiguous verification of the logic state
programmed for the inputs of each gate
requires prior knowledge of its programmed
output polarity. Therefore, the output polarity verify procedure must precede input
variable verify.
1. Set GND (pin 14JtoOV, and Vee (pin 28) to
Veev.
2. Enable all outputs by setting CE (pin 19)
to VIL.
3. Disable all input variables by applying VIX
to inputs 10 through 115.
A . Interrogate input variable 10 as follows:
Lower the input voltage to 10 from VIX to
VIL, and sense the logic state of outputs

Fo-a.
Raise the input voltage to 10 from VIL to
VIH and sense the logic state of outputs

Fo-a.

Si!lnotics

82S102-I,N • 82S103-I,N
The state of 10 contained in each gate is
determined in accordance with the given
truth table. Note that 2 tests are required
to uniquely determine the state of the
input variable contained in each gate.
B. Disable verified input by returning 10 to
VIX.
C .Repeat steps A and B for all other input
variables.
D .Remove VIX from all input variables.

TRUTH TABLE FOR INPUT VERIFICATION
10

Fp

Fp

INPUT VARIABLE STATE

LINK FUSED

0
1

1
0

0
1

10

j

0
1

0
1

1
0

10

0
1

1
1

0
0

Don't care

0
1

0
0

1
1

(10), (jQ)

PROGRAMMING SYSTEMS SPECIFICATIONS1
PARAMETER

Vccp

Vcc supply
Program2

TEST CONDITIONS

Neither

Min

LIMITS
Typ

Max

8.5

8.75

9.0

4.75

5.0

5.25

400

450

500

mA

16.0

17.0

18.0

V

125

150

175

mA

0.4

5.5
0.8

UNIT
V

Iccp = 350 ± 50mA,
Transient or steady state

Vccv

Verify
Icc limit (program)

VOPF

Forced output voltage3 (program)

IOPF

Output current limit (program)

VIH
VIL

Input voltage
High
Low

IIH
IlL

Input current
High
Low

VIH = +5.5V
VIL = OV

VIX
IIX1
IiX2

CE program enable level
Input variables current
CE input current

VIX
VIX

TR
tp
to
TPR
TPR

Output pulse rise time
CE programming pulse width
Pulse sequence delay
Programming time

TPR+Tps
FL
Vs

=
o

Both

TA = 25°C

Iccp

---

k

Vccp = +8.75 ± .25V,
Transient or steady state
lop = 150 ± 25mA,
Transient or steady state
Vop = +17 ± 1V,
Transient or steady state

V
2.4
0

p.A
50
-500
9.5

10

10
0.3
10

0.4

= +10V
= +10V

10.5
5.0
10.0

V
mA
mA

50
0.5

P.s
ms
P.s
ms

100

%

2
1.6

cycle
V

0.6

Programming duty cycle
Fusing attempts per link
Verify threshold 4

1.4

1.5

NOTES
1. These are specifications which a Programming System must satisfy in order to be qualified by
Signeties.
2. Bypass Vee to GNO with a 0,01 ~F capacitor to reduce voltage spikes.
3. Care should be taken to ensure that the voltage is maintained during the entire fusing cycle. The
recommended supply is a constant current source clamped at the specified voltage limit.
4. Vs is the sensing threshold of a gate output voltage for a programmed link. It normally constitutes the
reference voltage applied to a comparator circuit to verify a successful fusing attempt.

sagnotics

163

E
w
E

•-..o
c:

•-

BIPOLAR FIELD PROGRAMMABLE GATE ARRAY (IGI9)

82$ 102

(~C)

II2S 1lJ] (T S )
82S102-I,N .82S103-I,N

PROGRAMMING
In a virgin device all Ni-Cr links are intact.
The initial programmed state of each gate is
shown in the Typical Gate illustration.
To program inputs and outputs of each gate
for implementing the desired logic function,
fuse Ni-Cr links as indicated in the fuse link
diagrams.

TYPICAL GATE

r------,

I

I

NULL = "0"

OUTPUT ACTIVE HIGH

=

FUSE LINK S

INPUT f m = FUSE LINK J

INPUT 1m

= FUSE

LINK K

INPUT DON'T CARE = FUSE BOTH LINKS J, K
DON'T
CARE

~-{~t~]1 ~~
i1 OF '6,

164

'1

S!!)OOtiCS

FPGA MANUAL FUSER

Diodes = 1N457
97
Resistors = 2N6
LEOs = 521-9165

INPUTS (16)

SmnotieS

821102 (0 C ) 825103 (J 5 )

BIPOLAR FIELD PROGRAMMABLE GAlE ARRAY (16X9)

82S102-I,N .82S103-I,N

16X9 FPGA PROGRAM TABLE
CUSTOMER NAME _ _ _ _ _ _ _ _ _ _ _ _ __

THIS PORTION TO BE COMPLETED BY SIGNETICS

PURCHASE ORDER # _ _ _ _ _ _ _ _ _ _ _ __

CF(XXXX) _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____

SIGNETICS DEVICE # _ _ _ _ _ _ _ _ _ _ _ __

CUSTOMERSYMBOLIZEDPART# _ _ _ _ _ _ _ __

TOTAL NUMBER OF PARTS _ _ _ _ _ _ _ _ _ __

DATE RECEIVED _ _ _ _ _ _ _ _ _ _ _ _ _ __

PROGRAM TABLE # _ _ _ _ _ _ _ _ _ _ _ _ __

COMMENTS _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____

Fo= - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -_ __

F1 = - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - F2 = - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

F3= - - - - - - - - - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ __
F4= - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Fs= - - - - -____________________________________________
Fa= - - - - - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
F7= - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ ____
Fe= - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____

OUTPUT

INPUT VARIABLE

POLARITY

I,

11

I.

13

I.

Is

16

IA

19

IB

Ie

10

IE

IF

Fa

0

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

F1

16

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

F,

32

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

F3

48

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

F.

64

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

Fs

80

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

F6

96

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

F7

112

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

Fs
128
Active-high = H
Active-low = L

1m -H
= L

r;;;

Don't Care = -

The number in each cell in the table denotes its address for programmers with a decimal
address display.

166

Is

17

Si!lnOliCS

mOSmEmORY
DATA SPEClrlCATIOnS

Si!lDOliCS

167

168

Si!)DotiCS

!i
250H,N
DESCRIPTION
The 2501 employs enhancement mode pchannel MOS devices integrated on a Single
monolithic Chip.
Low cost silicone DIP packaging is implemented and reliability is assured by the use
of Signetics unique silicon gate MOS process technology. Unlike the standard metal
gate MOS process, the silicon material over
the gate oxide passivates the MOS transistors, and the deposited dielectric material
over the silicon gate-oxide-substrate structure provides an ion barrier. In addition,
Signetics' proprietary surface passivation
and silicone packaging techniques result in
an MOS circuit with inherent high reliability
and demonstrating superior moisture resistance, mechanical shock and ionic contamination barriers.

APPLICATIONS

PIN CONFIGURATION

• Small buffer stores
• Small core memory replacement
• Bipolar compatible data storage

I,N PACKAGE
ADDRESS 6

1

CHIP SELECT

ADDRESS 8

2

RIW

ADDRESS 7

3

DATAOU'T
DATA OUT

DATA IN
ADDRESS 5

6

ADDRESS 1

7

11

ADDRESS 4
ADDRESS 2
ADDRESS 3

BLOCK DIAGRAM
,..---------------------------------,

The use of Signetics' unique silicon gate low
threshold process allows the design and
production of higher performance MOS
circuits and provides higher functional density on a chip than other MOS technologies.

A,7

256-81T RAM PLANE

A,9

o==

All inputs of the 2501 can be driven directly
by standard bipolar integrated Circuits (TTL,
DTL, etc.). The data output buffers are capable of sinking a minimum of 1.6mAwhich is
sufficient to drive one standard TTL load.
The maximum power dissipation of
1.6mW/bit is required only during read or
write. For standby operation, 150,",W/bit is
obtained by removing Vo and reducing Voo
to -4.0V. Removal of Voalonewill cut power
dissipation by a factor of 1.5.
The outputs of the 2501 are effectively open
circuited when the device is not selected
(logic high on chip select). This feature
allows OR-tying for memory expansion.

E
w

DATA OUT 13

E

o""

DATA OUT 14

E

CS16lJ------~

FEATURES
• Fully decoded addresses
• Access time: 1.0,",s guaranteed
• Power dissipation: 1.6mW/blt max
• Standby power dissipation: 150,",W/blt
• DTL and TTL compatible
• Chip select and output wired-OR capability
• Standard 16-pln DIP
• P-MOS silicon gate technology
• Completely static
• Requires no clocking

R/W15

DATA IN 12

Vee

=5
=

VDO
8
VD =4

ABSOLUTE MAXIMUM RATINGS1
PARAMETER
TA
TSTG

Po

Temperature range
Operating
Storage
Power dissipation
I package
N package
All input or output voltages
with respect to the most
positive supply voltage, Vee
Supply voltages Voo and Vo
with respect to Vee

SrnootiCS

RATING

o to +70

UNIT

·c

-65 to +150
mW
800
640
+0.3 to -20

V

-18

V

169

2501-I,N

DC ELECTRICAL CHARACTERISTICS TA = O°C to 70 a,Vee = +5V2, VDD = VD = -9V ± 5%
0

unless otherwisespecified.3.4.5;6.7.8,9

LIMITS
PARAMETER

VIL
VIH

I nj:>ut voltage
Low
High

VOL
VOH

Output voltage
Low
High

III

Input current
Load (All input pins)

ILO

Output current
Leakage

TEST CONDITIONS

Min

Typ

Max

V
-5.0
Vee-2.0

Vee-4.5
Vee+0.3
V

10L = 3.0mA
10H = -100~
VIN

VOUT

= OV,

= OV,

TA

3.5

-0.7
4.5

0.45

<1.0

500

<1.0

1000

= +25°C

Chip select input
TA = 25°C

nA

= 3.3V,

= 0.45V, TA = +25°C
= 0.45V, TA = +70°C
VOUT = -0.7V
VOUT = OV
TA = +25°C
TA = +70°C
TA = +25°C, VDD = VD = -9V
VOUT
VOUT

Source
IOH1
IOH2
Supply current
VDD
VD

CIN
COUT

Capacitance
Input (All pins)
Output

AC ELECTRICAL CHARACTERISTICS

nA
mA

Sink
10L1
IOL2
IOL3

IDD
ID

UNIT

10L

3.0
2.0

6
5

6

13
mA

-3.0
-2.0

4
3
mA

= OmA

f = 1MHz
VIN = 5V
VOUT = 5V

13.0
8.5

18
12

7
7

10
10

pF

TA = O°C to +70°C, Vee = 5V2, VDD = VD = -9V ± 5%,
Input pulse amplitudes = 0 to 5V, Input pulse rise and fall times = <10ns,
Speed measurements referenced to 1.5V levels, Output load = 1 TTL gate,
Measurements made at output of TTL gate (tpd :5 10ns),
unless otherwise specified.

LIMITS
PARAMETER
READ CYCLE
Access time
tA
WRITE CYCLE
Write time
tw
Delay time
twD
twp
Write pulse width
Data-write pulse overlap
tDO

TO

FROM

Output

Address

Write

Address

NOTES
1. Stress'es above those listed under Absolute Maximum Ratings may cause pe~rnanent
damage to the device. This is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in the operational sections of
this specification is not implied.

2. Vee tolerance is ±5%. Any yariation in actual Vee will be tracked directly by VIL. VIH
and VOH which are stated for a Vee of exactly 5V.
3. For operating at elevated temperatures the device must be derated based on a +150°C
maximum junction temperature and a thermal resistance of 100°CIW junction to

170

Min

Typ

Max

1000
300
300
400
100

UNIT

ns
ns
ns
ns
ns

ambient for the I package or 1S0°C/W for the N package.
All inputs are protected against static charge.
Parameters are valid over operating temperature range unless specified.
All voltage measurements are referenced to ground.
Manufacturer reserves the right to make design and process changes ana
improvements.
8. Typical values are at +25° C and typical supply voltages.
9. Special device are available 10r operation at Voo = -7V, Vo = -10V. Contact your
Signetics Representative for details.

4.
5.
6.
7.

Sjgnntics

2U BIT REAIl V.IIIIE STATn: MOS RAM (25liXI)

2601
2501-I,N

TEST LOAD CIRCUIT
SPEED MEASUREMENT
CP
PULSE GENERATOR
SET

pos

TRIG
OUT

8 STAGE
SYNCHRONOUS
PRESET COUNTER

OUT

NOTES

A. Each clock"time is split into a Read followed by a Write. Read and Write times can be
varied by adjustment of the delay and width controls at the pulse generator.
B. Data generator produces a 256-bit block of data, 32 bits repeated 8 times. PCM mode

used so data can be changed in 32 bits of the 2501 from one cycle to the next.
C. All inputs to the 2501 are standard TTL outputs with Vee = 5V ± 5%.
D. Access time is measured between A 1 (least significant address input) and pOints 1 and

=
o

2.

VOLTAGE WAVEFORMS

E
w
E

WRITE CYCLE

READ CYCLE

CS--1--...

cs--t-......

o'"

:550ns

RIW

E

RIW---~---------'

1__-I'A-~WOUTPUTS

~
'DO

For Measurement Purpose Only

For Measurement Purpose Only

SjgDOliCS

171

25L01-I,N
DESCRIPTION
The 25L01 employs enhancement mode pchannel MOS devices integrated on a single
monolithic chip.
Low cost silicone DIP packaging is implemented and reliability is assured by the use
of Signetics' unique silicon gate MOS process technology. Unlike the standard metal
gate MOS process the silicon material over
the gate oxide passivates the MOS transistors, and the depOSited dielectric material
over the silicon gate-oxide substrate structure provides an ion barrier. In addition,
Signetics' proprietary surface passivation
and silicone packaging techniques result in
an MOS circuit with inherent high reliability
and demonstrating superior moisture resistance, mechanical shock and ionic contamination barriers.

APPLICATIONS
• Small buffer stores
• Small core memory replacement
• Bipolar compatible data storage

I,N PACKAGE
CHIP SELECT

AIW

DiTAOi:iT
DATA OUT

DATA IN

ADDFtESS 1

ADDRESS 2
ADDRESS 3

BLOCK DIAGRAM
,------------------------------------.
A,7

All inputs ofthe 25L01 can be driven directly
by standard bipolar integrated circuits (TIL,
DTL, etc.). The data output buffers are capable of sinking a minimum of 1.6mA, sufficient to drive one standard TIL load.
The maximum power dissipation of
1.7mW/bit is required only during read or
write. For standby operation 100/tW/bit is
obtained by removing Vo and redu'cing Voo
to -a.ov. Removal of Vo alone wll cut power
dissipation by a factor of almost 3.

PIN CONFIGURATION

256~BIT

RAM PLANE

A,9

DATA OUT 13

The outputs of the 25L01 are effectively
open circuited when the device is not selected (logic high on chip select). This feature
allows OR-tying for memory expansion.
DATA OUT

FEATURES
• Fully decoded addresses
• Access time: 1.0/ts guaranteed
• Power disslpatlcm: 1.7mW/blt max
• Standby power dissipation: 100/tW/blt
• DTL and TIL compatible
• Chip select and output wired-OR cepabillty
• Standard 16-pln DIP
• P-MOS silicon gate technology
• Fully static
• Requires no clocking
• Optimized with +5 and -12V supplies

14

RIW15

DATA IN 12

Vee =5
Voo=8
Vo =4

ABSOLUTE MAXIMUM RATINGS1
PARAMETER
TA
TSTG
Po

172

Temperature range
Operating
Storage
Power dissipation
I package
N package
All input or output voltages
with respect to the most
positive supply voltage, Vee
Supply voltages \(00 and Vo
with respect to Vee

Gi!lDOliCG

RATING

UNIT

DC

o to +70
-65 to +150
mW
BOO
640
+0.3 to -20

V

-1B

V

25LOI

256 IUT READ WRITE STATIC MllS RA. (25611)

25L01-I,N

DC ELECTRICAL CHARACTERISTICS TA = O°C to 70°C, Vee = +5V ± 5%, Voo = Vo = -12V ± 5%
unless otherwise specified.2.3,4,S.6,7,
PARAMETER

LIMITS

TEST CONDITIONS
Min

VIL
VIH

Input voltage
Low
High

VOL
VOH

Output voltage
Low
High

III

Input current
Load (All input pins)

ILO

Output cu rrent
Leakage

Typ

Max

UNIT
V

-12
Vee-2.0

Vee-4.5
Vee+0.3
V

IOL 3.0mA
IOH = -100f.LA

3.5

-0.7
4.5

0.45

<1.0

500

<1.0

1000

6
5
6

13

VIN = OV, TA = +25°C

nA

VOUT = OV, Chip select input = 3.3V,
TA = 25°C

nA

Sink
IOL1
IOL2
IOL3
Source
IOH1
IOH2
100
10

Supply current
Voo
Vo

CIN
COUT

Capacitance
Input (All pins)
Output

VOUT = 0.45V, T A = +25° C
VOUT = 0.45V, TA = +70°C
VOUT = -0.7V
VOUT = OV
TA = +25°C
TA = +70°C

3.0
2.0

mA
-3.0
-2.0

4
3
mA

TA = +25°C

9

IOL= OmA

5
11

16

f = 1MHz
VIH = 5V
VOUT = 5V

7
7

10
10

o

pF

E
w
E

AC ELECTRICAL CHARACTERISTICS TA=0°Ct0+70°C, Vee=5V±5%, Vot> = Vo = -12V ± 5%,
Input pulse amplitudes = 0 to 5V, Input pulse rise and fall times = <10ns,
Speed measurements referenced to 1.5V levels, Output load = 1 TTL gate,
Measurements made at output of TTL gate (tpd ~ 10ns),
unless otherwise specified.

'"
o

LIMITS
PARAMETER
READ CYCLE
Access time
tA
WRITE CYCLE
Write time
tw
Delay time
two
twp
Write pulse width
Data-write pulse overlap
too

TO

FROM

Output

Address

Write

Address

Min

Typ

Max
1000

300
300
400
100

UNIT

ns
ns
ns
ns
ns

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in the operational sections of
this specification is not implied.
2. For operating at elevated temperatures the device must be derated based on a +150°C
maximum junction temperature and a thermal reSistance of 10Q"CIW junction to
ambient for the I package or 150°C/W for the N package.
3. All inputs are protected against static charge.
4. Parameters are valid over operating temperature range unless specified.
5. All voltage measurements are referenced to ground.
S. Manufacturer reserves the right to make design and process changes and
improvements.
7. Typical values are at +25°C and typical supply voltages.

S!,gnotics

r;

173

E

25L01-I,N

TEST LOAD CIRCUIT
SPEED MEASUREMEf:oIT
CP
• STAGE
SYNCHRONOUS

PULSE GENERATOR
TRIG
. OUT

seT

POS
OUT

PRESET COUNTER

NOTES
A. Each clock time Is split Into a Read followed by a Write. Read and Write times can be
varied by adjustment of the delay and width controls of the pulse generator.
6. Data generator produces a 256-bit block of data, 32 bits repeated 8 times. PCM mode
used so data can be changed in 32 bits of the 2501 from one cycle to the next.
C. All inputs to the 25L01 are standard TTL outputs with Vee = 5V ± 5%.
D. Access time is measured between A1 (leest signlficimt address Input) and points 1 and
2."
'.

VOLTAGE WAVEFORMS
READ CYCLE

WRITE CYCLE

cs--1-'\.
:S;SOns

RIW
iiIW--~~-----'

I....._-c-:--:-IA,--_r-~
OUTPUTS

~

For Measurement Purpose Only

174

For Measurement Purpose Only

1024 BIT STATIC MOS RAM (256X4)

2101 2101 1 2101 2
2101-F,N • 2101-1-F,N .2101-2-F,N

DESCRIPTION

FEATURES

The 2101 series is high performance, low
power static read/write RAM's.

• Fully static
• No refresh operations, sense amps or
clocks required
• All inputs and outputs are TTL compatible
• One 5V power supply required

The 2101 series is fabricated with n-channel
silicon gate technology which allows the
design of high performance easy to use
MOS circuits and provides a high functional
density on a given monolithic chip.

PIN CONFIGURATION
F,N PACKAGE

BLOCK DIAGRAM
~Vcc
~GND
ROW
SELECT

R/W

CELL ARRAY
32 ROWS
32 COLUMNS

=

o

COLUMN I/O CIRCUITS

E
w
E

COLUMN SELeCT

01,
INPUT

DATA

01,

CONTROL

....o

00,
01,

01,

00,

E

00,

DO,

CE20----l

00

ABSOLUTE MAXIMUM RATINGS1
PARAMETER

TA
TSTG
PD

Temperature range
Operating under bias
Storage
Power dissipation
Voltage on any pin with
respect to ground

RATING

o to 70
-65 to 150
1
-0.5 to 7

S!!)Dl!tiCS

UNIT

°C

W
V

175

1024 BII STATIC MUS RAM (25614)

2101 2101 1 21012
2101-F,N • 210H-F,N .2101-2-F,N

DC ELECTRICAL CHARACTERISTICS

Input voltage
Low
High

VOL
VOH

Output voltage
Low
High

III

Input current

unless otherwise specified

LIMITS
Min

Supply current

0.45
2.2

VIN = 0 to 5.25V

10

CE1 - 2.2V
VOUT = 4.0V
VOUT= OA5V

15
-50
30

60
70

VIN = OV
VOUT = OV

4
8

8
12

mA

pF

TA =O°C to 70°C, Vee = 5V ± 5%, Input pulse levels = +0.65V to 2.2V,
Input pulse rise and fall times = 20ns, Timing measurement reference level = 1.5V,
Output load = 1 TTL gate and CL = 100pF, unless otherwise specified.
2101-1

2101

tow
tOH

TO

FROM

READ CYCLE
Read cycle
Access time
Chip enable
Output disable
Data output

Previous read data valid
after change of address

WRITE CYCLE
Write cycle
Write delay

tos

Setup time

twp
tWR

Write pulse
Write recovery

Min

0
40

Max

Min

Typ

2101-2

Max

500
1,000
800
700
200

0
40

Min

Typ

Max

650
500
350
300
150

0
40

500
100
400

650
150
550

Write

Chip enable

1,000
150
900

Rise of RIW
Change of
data in
Output

Data in
Rise of R/W

700
100

280
100

400
100

Output disable

200

150

150

750
50

300
50

400
50

650
400
350
150

UNIT

ns
ns
ns
ns
ns
ns

ns
ns
ns
ns

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other
condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. Typical values are for TA = 25° e and typical supply voltage.
3. This parameter is periodically sampled and is. not 100% tested.
4. tOF is with respect to the trailing edge of CE1, CE2 or 00, whichever occurs first.
5. CD should be tied low for separate 1/0 operation.

176

Typ

1,000
Output
Output
High Z state

Setup and hold time
Setup time
Hold time

I'A
I'A

VIN - 5.25V, 10 - OmA
TA = 25°C
TA = O°C

Capacitance3
Input (All pins)
Output

AC ELECTRICAL CHARACTERISTICS

twe
tAW
tew

0.65
Vee
V

10L = 2.0mA
10H = 15Ol'A

ICC1
ICC2

tRe
tA
teo
too
tOF4
tOH

UNIT

Max

V

ILOH
ILOL

PARAMETER

Typ2

-0.5
2.2

I/O leakage current3

CIN
COUT

± 5%,

TEST CONDITIONS

PARAMETER

VIL
VIH

TA = O°C to 70°C, Vee = 5V

s~nDtics

ns
ns

zlOl zlQ) ) ZIOI Z

1024 BII SIAIIGMOS RAM (25614)

2101-F.N • 2101-1-F.N .2101-2-F.N

TIMING DIAGRAMS
WRITE CYCLE

READ CYCLE

!.------twc-----.-I
ADDRESS

'----tcw--~

ffi

CE2
CE2

k---tcw---+-l
00

15)

00

=

o
E
w
E

'"
o

E

Si!)Dl!tiCS

177

2111 2111 I 2111 ,

1024 Bit SIAIIG MOS RAM (25614)

2111-1.N. 2111-1-I.N. 2111-2-I.N

PIN CONFIGURATION

DESCRIPTION

FEATURES

The 2111 series is a high-performance. lowpower static read/write RAM.

• Fully static
• Requires no refresh operations, sense
amps or clocks
• Completely TTL compatible
• Only one 5V power supply required

The 2111 series is fabricated with n-channel
silicon gate technology which allows the
design of high performance easy to use
MOS circuits and provides a high functional
density on a given monolithic Chip.

I,N PACKAGE
Vee

A,

A,
R/W

00

BLOCK DIAGRAM
18

A,

-----<>Vee
8
----OGNO

A,

ROW
SELECT

A,

MEMORY ARRAY
32 ROWS
32 COLUMNS

A,

R/W

liD,

Ce,

Ce,o---OI
00

ABSOLUTE MAXIMUM RATINGS1
PARAMETER

TA
TSTG

Po

178

Temperature range
Operating under bias
Storage
Power dissipation
Voltage on any pin with
respect to ground

G~nDtiCG

RATING

o to 70
-65 to 150
1
-0.5 to 7

UNIT

°C
W
V

211H,N. 2111-1-I,N. 2111-2-I,N

DC ELECTRICAL CHARACTERISTICS TA = O°C to 70°C, Vee = 5V ± 5%, unless otherwise specified.
LIMITS
PARAMETER

TEST CONDITIONS

Input voltage
Low
High

VOL
VOH

Output voltage
Low
High

III

Input load current

V,N = 0 to 5:25V

10

I/O leakage cu rrent

CEI =CE2=2.2V
V1/0 = 4.0V
V1/0 = 0.45V

15
-50

V
-0.5
2.2

Supply current

0.45
2.2

mA

TA=25°C,f=1MHz
V,N = OV
V,/O = OV

AC ELECTRICAL CHARACTERISTICS

twe
tAw
tew
tow
tOH
tos

twp

twR

FROM

4
10

8
15

2111-1

Min

Typ

Max

lie
o

Chip enable
Output disable
Data output

WRITE CYCLE
Write cycle
Write delay

0
40

Min

Typ

2111-2
Max

500

1,000

Previous read data valid
after change of address

Setup and hold time
Setup time
Hold time
Setup time

60
70

TA = O·C to 70·C, Vee =.5V ± 5%, unless otherwise specified,
Input pulse levels = 0.65V to 2.2V, Input pulse rise and fall times = 20ns,
Timing measurement reference level = 1.5V,
Output load = 1 TTL gate and CL = 100pF

READ CYCLE
Read cycle
Access time
Output
Output
High Z state

30

pF

2111
TO

!LA
!LA

V,N =5.25V, 1,/0 = OmA
TA = 25°C
TA = O·C

Capacitance3
Input
1/0

PARAMETER

0.65
Vee
V

10L = 2.0mA
10H = -15O!LA

lecl
lee2
C'N
CliO

UNIT

Max

V,L
V,H

ILOH
ILOL

tRe
tA
tee
too
tOF3
tOH

Typ2

Min

1,000
800
700
200

0
40

Min

Max

650
500
350
300
150

0
40

Write

Chip enable

900

500
100
400

RIW
Data
Output

Data

700
100
200

280
100
150

400
100
150

750
50

300
50

400
50

1,000
150

Typ

650
150
550

650
400
350
150

UNIT

ns
ns
ns
ns
ns
ns

ns
ns
ns
ns

RIW
Output disable

Write pulse
Write recovery

ns
ns

NOTES

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of thedevice

at these or at any other condition above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2. Typical values for TA = 25' e and supply voltage.
3. This parameter is periodically sampled and is not 100% tested.

9~nDtic9

179

E

w

...o
E

E

2111 21111 2111 2

1024 BIT STATIC MOS RAM (25614)

2111-1,N. 2111-1-I,N. 2111-2-I,N

TIMING DIAGRAMS
READ CYCLE

.

WRITE CYCLE
I~"------

.

'RC

ADDRESS

CHIP
ENABLES

__

+---,.I~"----

' w c - - - - - - - i..
~1

'CW---."

(CE 1 -eE 2)

CHIP
ENABLES

(CEI-CEll
OUTPUT
DISABLE

DATA 110

.

'A--------------

IOH-"

.......-t OF --.-

-

OUTPUT
DISABLE

STABLE

__+-__

~ ~ tWP--'1-tWR---"

READ;

stgnatics

tOH"-

DATA IN

DATA 110

DATA OUT
VALID

WRITE

180

---..

-

,Aw-I'------~

2112 2112 I 2II22

1024 BIT STATIC MOS RAM (256X4)

2112-F,N. 2112-1-F,N. 2112-2-F,N
DESCRIPTION

FEATURES

The 2112 series is high performance, low
power static read/write RAMs.

• Fully static
• No refresh operations, sense amps or
clocks required
• Directly TTL compatible
• One 5V power supply

The 2112 series is fabricated with n-channel
silicon gate technology which allows the
design of high performance easy to use
MOS circuits and provides a high functional
density on a given monolithic chip.

PIN CONFIGURATION
F,N PACKAGE

BLOCK DIAGRAM

,.
--<)Vcc

A'o--~

=
e

8

--<)GNO
ROW
SELeCT

MEMORY ARRAY
32 ROWS
32 COLUMNS

o
w

I/O,

e

,.

.....

INPUT

o

DATA
CONTROL

1/0 2

11

e

lJOJ

12
1/0 4

Ceo--~

,.

R/Wo-----'

ABSOLUTE MAXIMUM RATINGS1
PARAMETER
TA
TSTG

PD

Temperature range
Operating under bias
Storage
Voltage on any pin with
respect to ground
Power dissipation

Si!lnlJtiCs

RATING

o to 70

UNIT

°C

-65 to 150
-0.5 to 7

V

.,

W

181

2112 2112 1 2112 2

1024 BIT STATIC MOS RAM (25614)

2112-F,N • 2112-1-F,N .2112-2-F,N

DC ELECTRICAL CHARACTERISTICS

TA = O°C to 70°C, VCC = 5V ± 5% unless otherwise specified.
LIMITS

PARAMETER

Vil
VIH

Input voltage
Low
High

VOL
VOH

Output voltage
Low
High

III

Input current

TEST CONDITIONS

0.45
2.2

= 0 to 5.25V
CE = 2.2V
VIIO = 4.0V
VI/O = 0.45V

10

VIN

Supply current

TA

1/0

AC ELECTRICAL CHARACTERISTICS

15
-50
mA

= 25°C, f = 1MHz
VIN = OV
VI/O = OV

TO

FROM

Chip enable
Chip enable

Previous read data val id
after change of address

tWP1
tWR1

4
10

8
15

Min

Typ

0
40

850

2112-2

2112-1
Max

Min

Typ

Max

1000
800
200

0
40

500

Min

Typ

Max

650

500

1000
Output
Output disable

tAW1
tOW1
tCS1
tCH1
tOH1
tCW1

60
70

TA = O°C to 70°C, Vcc = 5V ± 5% unless otherwise specified,
tR and tF = 20ns, VIN = 0.65V to 2.2V, Timing reference = 1.5V,
Load = 1 TTL gate and Cl = 100pF

READ CYCLE
Read cycle
Access time

Setup and hold time
Setup time
Setup time
Setup time
Hold time
Hold time
Setup time

30

pF

2112

WRITE CYCLE #1
Write cycle

!LA
!LA

VIN - 5.25V, 1110 - OmA
TA = 25°C
TA = O°C

Capacitance3
Input (All pins)

tWC1

0.65
Vcc
V

10l = 2mA
10H = -150!LA

ICC1
ICC2

tRC
tA
tco
tco
tOH

UNIT
Max
V

IlOH
IlOl

PARAMETER

Typ2

-0.5
2.2

1/0 leakage current

CIN
CliO

Min

500
150
100

0
40

500

650
500
150

UNIT

ns
ns
ns
ns
ns

ns
ns

150
650
0
0
100
650

100
250
0
0
50
250

100
280
0
0
50
350

Write pulse width
Write recovery time

650
50

250
50

350
50

ns
ns

tWC2

WRITE CYCLE #2
Write cycle

1050

500

650

ns

tAw2
tOW2
tCS2
tCH2
tOH2

Setup and hold time
Setup time
Setup time
Setup time
Hold time
Hold time

tW02
tWR2

Disable time
Write recovery time

Write
RIW high
CE low
CE high
Data
R/W high

Address
Data
R/W low
R/W high
RIW high
CE low

ns
Write
R/W high
CE low
CE high
Data

Address
Data
R/W low
R/W high
R/W high

150
650
0
0
100

100
250
0
0
50

100
280
0
0
50

RIW high

Data

200
50

200
50

200
50

NOTES on following page.

182

Si!lnotics

ns
ns

2112-F,N. 2112-1-F,N. 2112-2-F,N
NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage tathe device. This is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2. Typical values are for TA = 25° C and typical supply voltage.
3. This parameter is periodically sampled and is not 100% tested.

4. Output is enabled and teo commences only with both CE low and WE high.
5. Output is disabled and tOF combined from either the (ising edge of CE or. the falling
edge of WE.
6. Minimum twp is valid when CE has been high at least tOF before WE goes low.

Oherwise

twP(mln)

= -tOW(min) + tOF(max).

•

7. When WE goes high althe end of the write cycle, It will be possible to turn on the output
buffers if CE is still low. The data out will be the same as the data just written and so will
nol conflict with input data that may still be on the I/O bus.

VOLTAGE WAVEFORMS
WRITE CYCLE #2

WRITE CYCLE #1

r;
o

...

E
E

READ CYCLE

...o
E

smOOlies

183

1024 BIT READ WRITE STATIC Mas RAM (256X4)

2606 2606 1
2606-F,I,N • 2606-1-F,I,N

DESCRIPTION

FEATURES

The 2606 is fabricated with n-channel silicon gate MOS technology and achieves an
access time of less than 750ns.

• Fully decoded
• No clocks required
• All interface Signals, including power
supply directly TTL compatible

PIN CONFIGURATION
F,I,N PACKAGE

BLOCK DIAGRAM
v S5 (GND)

1'.
+

Vee

1/0 3

16

lS

'i'1'

•

2

1

+

+

+

+

~ ~ ~ ~
OUTPUT

OUTPUT

R/W

A,

•

t , ,

~

--·CS

DATA I/O

READ CYCLE

ADDRESSES STABLE

REAOtW'RiTE

CHIP ENABLE

WRITE CYCLE B

=~100n.

.----

,.--- - ---- --- -".' ---'-_______
____ J",

--(

1024 BIT READ WRITE STATIC MOS RAM (102411)
2102-F,I,N • 2102-1-F,I,N .2102-2-F,I,N

DESCRIPTION

FEATURES

The 2102, 2102-1and 2102-2 are static random access read/write memories fabricated with low threshold n-channel silicon
gate technology.

•
•
•
•
•

PIN CONFIGURATION

Fully static
Require no clocks
Completely DTL/TTL compatible
Single 5V power supply
Three-state output for OR-tie capability

F,I,N PACKAGE

BLOCK DIAGRAM
Vee

GND

10

32 ROWS
32 COLUMNS

=

o
E
w
E

....o

1 OF 32 COLUMN DECODER

E

II,

II,

II,

II.

II.

ABSOLUTE MAXIMUM RATINGS1
PARAMETER

TSTG
PD

Temperature range
Storage
Power dissipation 2
N package
F package
I package
All input, output and supply
voltages with respect to ground

RATING

UNIT

°C
-65 to 150
640
1
1
-0.5 to 7

S!!IDotiCS

mW
W
W
V

187

2102-F,I,N • 2102-1-F,I,N • 2102-2-F,I,N

DC ELECTRICAL CHARACTERISTICS TA = O·C to 70·C, Vcc = 5V ± 5% unless otherwise specified.
LIMITS

PARAMETER

TEST CONDITIONS

VIL
VIH

Input voltage
Low
High

VOL
VOH

Output voltage
Low
High

ILl

Input load current (All input pins)

VIN = 0 to 5.25V

Leakage current

CE = 2.2V
VOUT = 4.0V
VOUT = 0.45V

Typl

Min

Max

IJNIT

V
-0.5
2.2

0.65
Vcc
V

IOL = 1.9mA
IOH = -100!,A

ILOH
ILOL
Supply current

0.45
2.2
10
10
-100

All inputs = 5.25V, Data out open
TA = 25·C
TA=O·C

ICCl
ICC2

!,A
!,A

mA
30

60

70

AC ELECTRICAL CHARACTERISTICS TA = O·C to 70·C, Vcc = 5V ± 5% unless otherwise specified.
2102-1

2102
PARAMETER

tRC
tA

FROM

READ CYCLE
Read cycle
Access time

teo
tOHl
tOH2
twc
twp
twR

WRITE CYCLE
Write cycle
Write pulse width
Write recovery time

tAW
tow
tOH

Setup and hold time
Setup time
Setup time
Hold time
Setup time

Min

Min

Chip enable

Typ

2102-2
Max

500
1,000
500

Min

Typ

Max

650
650
400

500
350

50
0

50
0

50
0

1,000
750
50

500
300
50

650
400
50

Address
Data in
Rise of Rm

200
800
100

150
330
100

200
450
100

Chip enable

900

400

550

UNIT

ns
ns
ns
ns

ns
ns
ns
ns

Write
Rise of Rm
Change. of
data in
Write

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is $ stress rating only and functional operation of the device of these or any other

condition above those indicated in the operation of the device oUhese or any other conditl,on above
those indicated In the operation sections of this specification is not implied.
2. For operating at elev8.ted temperatures the device must be derated based on a +150°C maximum
junction temperature and a thermal resistance of 150°C/W junction to ambient ("S" packagel.

3. All inputs prolecled againsl sIalic charge.
4. Parameter valid over operating temperature range unless otherwise specified.
5. All voltage measurements are referenced to ground.
6. Manufacturer reserves the right to make design and process char:-ges and improvements.

7. Typical values are al +25'C and typical supply vollages.

188

Typ Max

1,000
Output

Previous data valid with
respect to
Address
Chip enable

tcw

TO

.

Smnotics

1824 BIT READ WRITE STAIIC MOS RAM (1024X))

2102 2102 I '102 2
2102-F,I,N • 2102-1-F,I,N .2102-2-F,I,N

TIMING DIAGRAMS
READ CYCLE

WRITE CYCLE
~1'-----'WC------f'1

AOOR:;K----------~r

If.·-----'-- 'RC ------11
~~--------~~

ti\-

AOOR~

I

r---'co---l

i

~-~1---~~

I

CHiP

:~

cw

ENABLE

r

--J'WRI--

I

:-nr----·

-----1.I: l

! \~_:__--------...;.J.

REAO-'--.!1-~.A~w:;\·i;----·wP-----t.

r - :

~~~A

I~'-----'A

rli--' OH2

XJX
I

I

!1 .

WRiTE"

r-

---'Ow--=:!--I
'OH
__ I

___________

1+1.

----~Ir_-----

DATA
IN

DATA CAN
CHANGE

DATA STABLE

~

o
E
w

E

....o
E

SmootiCS

2102A SERIES-F,I,N

DESCRIPTION

FEATURES

The 2102Ais a high speed stl!tic random
access memory element using n-channel
MOS devices integrated on a monolithic
array. It uses fully dc stable (static) circuitry
and therefore requires no clocks or refreshing to operate. The data is read out nondestructively and has the same polarity as the
input data.

•
•
•
•
•
•
•

The 2102A is designed for memory applications where high. performance, low cost,
large bit storage, and simple interfacing are
important design objectives. A low standby
power version (2102AU is also available,
and has all the same operating characteristics of the 2102A with the added feature of
35mW maximum power dissipation in
standby and 174mW in operations.
A separate chip enable (CE) lead ailows easy
selction of an individual package when outputs are OR-tied.
The 2102A is fabricated with n-channel
silicon gate technology, which allows the
design and production of high performance, easy-to-use MOS circuits and provides a higher functional density on a monolithic chip than either conventional MOS
technology or p-channel silicon gate technology.

PIN CONFIGURATION

Single 5V supply Yoltage
Fully TTL compatible
Standby power mode (2102AL)
Trl-state output
OR-tie capability
All Inputs protected against static charge
Low cost packaging

F,I,N PACKAGE

Vee

PIN DESIGNATION
PIN NO.

SYMBOL

FUNCTION

11
1,2,48,14,16
3
13
12
10

DIN
Ao-A9

Data input
Address inputs

RIW
CE
DOUT

9

GND

Read/write input
Chip enable
Data output
Power (5V)
Ground

Vee

TYPE

TRUTH TABLE
CE

R/W

DIN

DOUT

MODE

H
L
L
L

X

X

L
L
H

L
H

High Z
L
H
DOUT

Not selected
Write "0"
Write "1"
Read

X

BLOCK DIAGRAM

(10)

---0 Vee
(9)

--0

GND

CELL

ARRAY
32 ROWS
32 COLUMNS

DATA

R/W

COLUMN 110 CIRCUITS

OUT

DATA

IN

A,

( ) = Pin number

190

SillOOliCS

A,

A,

A,

A.

1024 BIT STATIC MOS RAM (1024X1)

2102" SERIES
2102A SERIES-F,I,N

ABSOLUTE MAXIMUM RATINGS1
RATING

PARAMETER

TA
TSTG
PD

Temperature range
Operating under bias
Storage
Power dissipation
Voltage on any pin with
respect to ground

°C
-10 to 80
-65 to 150
1
-0.5 to 7

DC ELECTRICAL CHARACTERISTICS

PARAMETER

VIL
VIH

Input voltage
Low
High

VOL
VOH

Output voltage
Low
High

III

Input load current
Output leakage current

ILOH
ILOL
Icc

Supply current3

CIN
COUT

Capacitance4
Input (All pins)
Output

STANDBY CHARACTERISTICS

UNIT

W

V

TA = O°C to 70°C, Vee = 5V

TEST CONDITIONS

± 5%

unless otherwise specified.

2102A-21

21 02A/21 02A-41
2102AL/2102AL-4

2102AL-2

Min Typ2 Max

Min Typ2 Max

Min

Typ2 Max

-0.5
2.0

-0.5
2.0

-0.5
2.2

0.65
Vee

2102A-6

V
0.8
Vee

0.8
Vee

V
IOL = 2.1mA
IOH = -100f.LA

0.4
2.4

0.4

VPD

Vee in standby

VeEs

CE bias in standby6

0.45
2.2

2.4

VIN = 0 to 5.25V

1

10

1

10

1

10

(;E - 2.0V
VOUT = VOH
VOUT = O.4V

1
-1

5
-10

1
-1

5
-10

1
-1

5
-10

45

65

33

55

3
7

5
10

3
7

5
10

Data out open,
TA = O°C

33

VIN = OV
VOUT = OV

3
7

tep
tR

mA
pF

5
10

TA = O°C to 70°C
TEST CONDITIONS

2.0V S VPD S Vee max
1.5V S VPD < 2.0V

Min

Typ5

Max

2102AL-2
Min

Typ5

Max

UNIT

1.5

1.5

V

2.0
VPD

2.0
VPD

V

Standby current

mA
All inputs = VPDl = 1.5V
All inputs = VPD2 = 2.0V

IPDl
IPD2

f.LA
f.LA

2102AL,2102AL-4
PARAMETER

UNIT

Chip deselect to standby
time
Standby recovery time?

SegDDtiCS

15
20

23
30

20
25

28
38

0

0

ns

tRe

tRe

ns

191

=

o
e
w
e
.....
o
e

2102A SERIES-F.I.N

AC ELECTRICAL CHARACTERISTICS

TA = O°C to 70°C. Vee = 5V ± 5% unless otherwise noted.
Input pulse levels = 0.8V to 2.0V. Input rise and fall times = 10ns.
Timing measurement reference level inputs = 1.5V
Output = 0.8V and 2.0V. Output load = 1 TTL gate and CL = 100pF
2102A"2,2102AL-2

PARAMETER

tRe
tA
teo

FROM

TO

Min

READ CYCLE
Read cycle
Access time

Max

250
Output time

2102A,2102AL
Min

Max

350

Chip enable

350
180

UNIT

ns
ns
ns
ns

tOH1
tOH2

40
0

40
0

twe
twp
tWR

WRITE CYCLE
Write cycle
Write pulse width
Write recovery time

250
180
0

350
250
0

tAW
tow
tOH
tew

Setup and hold time
Setup time
Setup time
Hold time
Setup time

20
180
0
180

20
250
0
250

tRe
tA
teo

Typ

250
130

Previous read data val id
with respect to
Address
Chip enable

PARAMETER

ns
ns
ns
ns

Write
R/W
Output
Data

Address
Data
Data
R/W

TO

FROM

2102A-4,2102AL-4
Min

READ CYCLE
Read cycle
Access time

Typ

Max

450
Output time

2102A-6
Min

Chip enable

Typ

Max

650
650
400

450
230

UNIT

ns
ns
ns
ns

tOH1
tOH2

Previous read data valid
with respect to
Address
Chip enable

40
0

50
0

twe
twp
tWR

WRITE CYCLE
Write cycle
Write pulse width
Write recovery time

450
300
0

650
400
50

lAw
tow
tOH
tew

Setup and hold time
Setup time
Setup time
Hold time
Setup time

20
300
0
300

200
450
20
550

ns
ns
ns
ns

Write
RIW
Output
Data

Address
Data
Data
R/W

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other
condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. Typical values are for TA = 250 C and typical supply voltage.

3. The maximum Icc value is 5SmA for the 2102A and 2102A-4. and 33mA forthe2102ALand 2102AL-4.
4. This parameter is periodically sampled and is not 100% tested.
S. Typical values are for TA = 25° C.
6. Consider the test conditions as shown: if the standby voltage (Vpo) is between 5.25V (Vcc max) and
2.0V. then CE must be held at 2.0V min IV,H!. If the standby voltage is less than 2.0V but greater than
1.5V (VPD min), then CE and standby voltage must beat least the same value or, if they are different, BE
must be the more positive of the 2.
7. tR = tRC (read cycle time).

192

Typ

Gi!lDotiCG

!i
2102A SERIES-F,I,N

VOLTAGE WAVEFORMS
READ CYCLE

STANDBY

~------IRe __-----~
i----STANOBY M O O E - - - . j
ADDRESS

vee----"

CHIP
ENABLE

OV -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

DATA
OUT _ _ _ _ _ _ _ _ _ _ _ _ _

.J.

WRITE CYCLE
'we

=

lew

0

E
W
E

'W.
READI
WRITE

lOW
DATA

IN

DATA CAN
CHANGE

~

DATA
STABLE

0

E

SI!I0otiCS

193

21 F02-F,I,N • 21 F02-2 - F,I,N. 21 F02-4 - F,I,N

DESCRIPTION

FEATURES

The 21 F02 is a high speed static random
access memory element using n-channel
MOS devices integrated on a monolithic
array. It uses fully dc stable (static) circuitry
and therefore requires no clocks or refreshing to operate. The data is read out nondestructively and has the same polarity as the
input data.

• Fully TTL compatible
• Single 5V supply

The 21 F02 is designed for memory applications where high performance, low cost,
large bit storage, and simple interfacing are
important design objectives. A separate
chip enable (CE) lead allows easy selection
of an individual package when outputs are
OR-tied.

PIN CONFIGURATION
F,I,N PACKAGE

BLOCK DIAGRAM

The Signetics 21 F02 is fabricated with nchannel silicon gate technology. This technology allows the design and production of
high performance easy to use MOS circuits
and provides a higher functional density on
a monolithic chip than either conventional
MOS technology or p-channel silicon gate
technology.

Vee

GND

10

32 ROWS
32 COLUMNS

1 OF 32 COLUMN DECODER

A,

194

GjgDotiCG

A,

A,

A,

21F02,21F02 2 2IF02 4

1024 BIT READ WRITE STATIC MOS RAM (102411)

21 F02-F,I,N • 21 F02-2 - F,I,N. 21 F02-4 - F,I,N

ABSOLUTE MAXIMUM RATINGS1
RATING

PARAMETER
TSTG
Po

Temperature range
Storage
Power dissipation2
N package
F package
I package
All input, output and supply
voltages with respect to ground

UNIT
°C

-65 to 150
640
1
1
-0.5 to 7

mW
W
W
V

DC ELECTRICAL CHARACTERISTICS TA = O°C to 70°C, Vcc

= 5V

± 5% unless otherwise specified.
LIMITS

PARAMETER

TEST CONDITIONS

VIL
VIH

Input voltage
Low
High

VOL
VOH

Output voltage
Low
High

III

Input load current (All input pins)

Typ3

Min

UNIT

Max

V
0.8
Vcc

-0.5
2.0

V
IOL = 2.1mA
IOH = -1 OO!LA
VIN = 0 to 5.25V

0.4
2.4
10

CE = 2.0V
VOUT = 2.4 to Vcc
VOUT = 0.4V
All inputs = 5.25V, Data out open
TA = 25°C
TA = O°C

Output leakage current
ILOH
ILOL
Supply current
ICCl
ICC2

!LA
!LA

5
-10
rnA
30

60
70

e

.....

AC ELECTRICAL CHARACTERISTICS TA = O°C to 70°C, Vcc

= 5V ± 5% unless otherwise specified,
Input pulse levels = 0.65 to 2.2V, Input pulse rise and fall times = 20ns,
Timing measurement reference level = 1.5V,
Output load = 1 TTL gate and CL = 100pF

PARAMETER

tRC
tA
tco

TO

FROM

READ CYCLE
Read cycle
Access time
Output time

tOHl
tOH2

Previous read data valid
with respect to
Address
Chip enable

twc
twp
twR

WRITE CYCLE
Write cycle
Write pulse width
Write recovery time

tAw
tow
tOH
tcw

Setup and hold time
Setup time
Setup time
Hold time
Setup time

21F02

21 F02-2

Min Typ3 Max

Min Typ3 Max

Min

350

250

450
450
230

250
130

350
180

Chip enable

21 F02-4

Typ3 Max

40
0

40
0

40
0

350
250
20

250
180
20

450
300
20

20
250
0
250

20
180
0
180

20
300
0
300

UNIT

ns
ns
ns
ns

ns
ns
ns
ns

Write
Output
Output
Write

Address
Data
Data
Chip enable

NOTES on following page.

G!Rl!tiCG

=

o
ew

195

o
e

1024 BIT READ WRITE STATIC MOS RAM (102411)

2IFO' 'HII2 2 'IEOz 4
21 F02-F,I,N • 21 F02-2 - F,I,N. 21 F02-4 - F,I,N

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation 131 the device
of these or any other condition above those indicated in the operation sections of this
specification is not implied.
2. For operating at elevated temperatures the device must be derated based on a +150°C
maximum junction temperature and a thermal resistance of 150°CIW junction to
ambient 16 packagel.
3. Typical values are at +25°C and typical supply voltages.
4. All inputs protected against statiC charge.
5. Parameter valid over operating temperature range unless otherwise specified.
6. All voltage measurements are referenced to ground.
7. Manufacturer reserves the right to make design and process changes and
improvements.

TIMING DIAGRAMS
READ CYCl.E

WRITE CYCLE
~I'---------------'wc--------------~'I

~------------------------~.

;C

AOOR:;K,'
,

i

~[-E~i------~~

~I'------'A

=--t-'\;----.cw------r.': T'

ENABLE

:~

, rl l-' OH2

READI

WRiTE

~~

________________________~.

'\

----------~

DATA

,N

196

!

r

I-'Aw-tl~'-----.wp-----ll

XIt

g~~A_______________

I,

I ~'---------------------~---'WR~

CHiP

-------~-------------- I

I+---'co--l

I'i\....-

ADDR:Ji\

I~'------'RC --------ll

Smnotics

DATA CAN
CHANGE

I-----.DW----=:J-I !-'DH
r------------~I

OATA STABLE

21L02-F,I,N. 21L02-1-F,I,N. 21 L02-2-F,I,N .21L02-3-F,I,N

DESCRIPTION

FEATURES

The 21 L02, 21 L02-1, 21 L02-2, and 21 L02-3
are low power static random access read/
write memories fabricated with low threshold n-channel silicon gate technology.

•
•
•
•
•

PIN CONFIGURATION

Fully static
Requires no clocks
Completely DTL/TTL compatible
Single 5V power supply
Three-state output for OR-tie capability

F,I,N PACKAGE

BLOCK DIAGRAM
Vee

GND

10

32 ROWS
32 COLUMNS

=
o
E
w
E

....o

1 OF 32 COLUMN DeCODER

E

ABSOLUTE MAXIMUM RATINGS1
PARAMETER

TSTG
Po

Temperature range
Storage
Power dissipation 2
N package
F package
I package
All input, output and
supply voltages with
respect to ground

RATING

UNIT

°C
-65 to 150
640
1
1
-0.5 to 7

SjgnotiCS

mW
W
W
V

197

21L02-F,I,N. 21 L02-1-F,I,N • 21 L02-2-F,I,N .21L02-3-F,I,N

DC ELECTRICAL CHARACTE.RISTICS
PARAMETER

TA = O·C to 70·C, Vcc = 5V

LIMITS

TEST CONDITIONS

VIL
VIH

Input voltage
Low
High

VOL
VOH

Output voltage
Low
High

III

Input load current (All input pins)

Min

Typ3

Max

UNIT
V

-0.5
2.2

0.65
Vcc
V

IOL = 1.9mA
IOH = -100j.lA

0.45
2.2

VIN = 0 to 5.25V

Output leakage current

10

CE = 2.2V
VOUT= 4.0V
VOUT = 0.45V

ILOH
ILOL
Supply current

AC ELECTRICAL CHARACTERISTICS

TO

j.lA
j.lA

10
-100

All inputs = 5.25V, Data out open
TA = 25·C
TA = O·C

ICCl
ICC2

PARAMETER

± 5% unless otherwise specified.

mA
40
40

30

TA = O·C to 70·C, Vcc = 5V ± 5% unless otherwise specified,
Input pulse levels = 0.65V to 2.2V, Input pulse rise and fall times = 20ns,
Timing measurement reference level = 1.5V, Output load = 1 TTL gate
and CL = 100pF

21L02

FROM

21 L02-1

21 L02-2

21 L02-3

Min Typ Max Min Typ Max Min Typ Max Min Typ Max
tRC

tA

READ CYCLE
Read cycle
Access time
Output time

tco

tOHl
tOH2

TWR
tAW
tDW
tDH
tcw

Setup and hOld time
Setup time
Setup time
Hold time
Setup time

twp

1,000
500

Chip enable

400
3.00

50
0

50
0

50
0

1,000
750
50

500
300
50

650
400
50

400
250
50

150
330
100
400

200
450
100
550

100
300
50
300

ns
ns
ns

ns
ns
ns
ns

Write
Address
200
Rise of RtW
Data .in
800
Change of data in Rise of RtW 100
Write
Chip enable 900

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device of these or any other
condition above those indicated in the operation sections of this specification is not Implied.
2. For operating at elevated temperatures the device must be derated based on +150°C maximum
junction temperature and a thermal resistance of 150°CIW junction to ambient (8 package).

3. Typical values are at +25' C and typical supply voltages.
All inputs protected against static charge.
Parameter valid ov~r operating temperature range unless otherwise specified.
All voltage measurements are referenced to ground.
Manufacturer reserves the right to make design and process changes and improvements.

198

650
400

50
0

NOTES

4.
5.
6.
7.

400

650
500
350

ns

Previous read data valid
with respect to
Address
Chip enable

WRITE CYCLE
Write cycle
Write pulse width
Write recovery time

twc

500

1,000

UNIT

smnRties

1024 BIT READ WRITE STATIC MuS RAM (1lJ24XI) 2IL02 2IL02 I 2ILO.! 2 21 102 3
21 L02-F,I,N .21 L02-1-F,I,N .21 L02-2-F,I,N .21 L02-3-F,I,N

TIMING DIAGRAMS
READ CYCLE

WRITE CYCLE
II-·--~--twc------ll

Ii\.......
~-~-----_ _--~~~I

I------t"c------II

CHiP

,

I----tco-l

~BL-E-*I---~~

11------tA

I

I I
----jtWRI:-n:----tcw------I,I

ENABlE

:~

! \\...__________I'-J

'\

!-tAw ......
I·----twP-----!·1

XJX

g~~A____________

,

r
r

ADO"::J1\

AOOR~~---------....,~

t-II- tOH2

READI

WRiTE

'I-'---tow--=:!-I :-- tOH
__ I

-------~Ir_-------

DATA
IN

DATA CAN
CHANGE

DATA STABLE

r;
o
E
w
E

8
E

S!!Inotics

199

2115 2) 151 2)25 2U5t

W24 HI1 SIAlIC MOS RAM (1024Xl)

2115/2115L-F,I,N·2125/2125L-F,I,N

OBJECTIVE SPECIFICATION

PIN CONFIGURATION

DESCRIPTION

FEATURES

The 2115 and 2125 family are read/write
RAMs which are designed for buffer control
storage and high performance main memory applications.

• Power dissipation: O.2mW/bit typ (2115L,
2125L)
• Output options:
2115: Uncommitted collector"
2125: Three-state
• Non-inverting data output
• Dual-in-line package
• N-channel MOS silicon gate technology
• Fully pin compatible to 93415 (2115) and
93425 (2125)
• Fully compatible with TTL logic families
including inputs, output and single 5V
supply

These devices offer the advantages of high
performance, low power dissipation, and
system cost savings, making them ideal
where cost is a prime factor. N-channel
technology allows the design and production of high speed MOS RAMs which are
compatible to the performance of Bipolar
RAMs.

F,I,N PACKAGE

* The 2115 is an MOS device and the output is actually an

uncommitted drain.

PIN DESIGNATION

TRUTH TABLE
INPUTS
CS
H
L
L
L

WE
X
L
L
H

DIN
X
L
H
X

OUTPUT
2115 FAMILY

OUTPUT
2125 FAMILY

DOUT
H
H
H
DOUT

DOUT
High Z
High Z
High Z
DOUT

MODE

Not selected
Write "0"
Write "1"
Read

PIN NO.

SYMBOL

1
2-6,
9-13

AO-9

FUNCTION

es

7
8
14
15

Chip select
Address inputs
Data output
Ground
Write enable
Data input

DOUT
GND

WE
DIN

BLOCK DIAGRAM

r---

WORD

DRIVER

32X32
ARRAY

~

i

SENSE AMPS
AND
WRITE
DRIVERS

-

CONTROL

lOGIC
(SEE TRUTH
TABLE)

i
ADDRESS
DECODER

200

ADDRESS
DECODER

iii i t
Ao

Al

A2

A,

A,

t iii i

-

es

WE

D,N

(2)

(3)

(4)

(5)

(6)

(9) (10) (11) (12) (13)

(1)

(14)

(15)

Smnotics

A,

A,

A,

As

As

Dour
(7)

2115 2115L 21?S 2125L

1024 BIT !llIiTlO MOS RAM (1024}[1)

1

2115/2115L-F,I,N.2125/2125L-F,I,N

OBJECTIVE SPECIFICATION
ABSOLUTE MAXIMUM RATINGS1
PARAMETER
TA
TSTG

UNIT

RATING

·C

Temperature range
Operating
Storage
All output or supply voltages
All input voltages
Dc output current

-10 to 85 .
-65 to 150
-0.5 to 7
-0.5 to 5.5
20

DC ELECTRICAL CHARACTERISTICS2
PARAMETER

VCC = 5V

V
V
mA

± 5%, TA = O·C to 75·C
2115/2115L

TEST CONDITIONS
Min

Vil
VIH

Input voltage
Low
High

VOL
VOH

Output voltage
Low
High

III
hH

Input current
Low
High

ICEX
10FF
IOS3

Output current
Leakage
High Z
Short circuit

Vcc = Max
VOUT = 4.5V
VOUT = 0.5V/2.4V
Vcc = 4.5V

Supply current
2115L, 2125L
2115,2125

All inputs grounded, output open

ICCl
ICC1
CIN
COUT

Capacitance
Input
Output

Typ

2125/2125L

Max

Min

Max

V
2.1

2.1
V

10l = 16mA
10H = -3.2mA

0.45

0.45
2.4

2.4

Vcc = Max
VIN = O.4V
VIN =4.5V

p.A
-1
1

-40
40

10

100

PARAMETER
READ CYCLE
Chip select time
Chip select recovery time
Access time
Previous read data valid
after change of address

-1
1

-40
40

10

50
-100

65
100

50
75

65
100

4
5

8
8

4
5

8
8

All inputs - OV, Output open

pF

CS=5V
VCC = 5V
TO

± 5%, TA = O·C to 75·C
FROM

Min

2115L/2125L

Typ

Max

Min
5

75

45
40
95

5
Output

Address
10

Typ

Max

75

50
40
95

10

WRITE CYCLE
Enable time
tws
tzws
tWR
tw

Write recovery time
Write pulse width

twSD
tWHD

Setup and hold time
Setup time prior to write
Hold time after write

(2125,2125U

p.A
p.A
mA
mA

50
75

2115/2125

UNIT

ns
ns
ns
ns

ns
Write enable
High Z

Data out
Write enable

40

5

45

40

50

5
50

WE
Data

Data
WE

5

15

twSA
tWHA

Setup time
Hold time

WE
Address

Address
WE

30
5

30
15

twscs
tWHCS

Setup time
Hold time

WE
Chip select

Chip select
WE

5

15

NOTES on follOWing

UNIT

0.8

0.8

AC ELECTRICAL CHARACTERISTICS

tACS
tRCS
tAA
tOH

Typ

50

ns
ns
ns

page.

Smnotics

201

o==
E
w

E

o
E

OBJECTIVE SPECIFICATION

2115/2115L-F,I,N .2125/2125L-F,I;N

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any -other
condition above those indicated in the operational sections of this specihcation is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The operating ambient temperature ranges are guaranteed with transverse air flow exceeding 400
linear feet per minute and a 2 minute warm-up. Typical thermal resistance values of the package at
maximum temperature are:
OJA I@ 400fpm air flow) ~ 45° CfW
8JA (still air) = 60° elW
OJC ~ 25° CfW.
3, Duration of short circuit current should not exceed 1sec.

TEST LOAD CIRCUITS
2115/2125

2125

AC AND DC LOADING CONDITIONS
4.7SY

5V
750n

T

A'N

30pF

2125

5pF

(INCLUDING
SCOPE AND

~JIG)
LOAD 1

2115
330n
600n

L

RIN

2125
330n
300n

Write Enable to High Z Delay

VOLTAGE WAVEFORMS
2115/2125

2125

_

3F:0.5VP:P---';';-;';-';:-;;'-"'-"'-"'-"'-=-"-"'-~-'K:---90%
__ -:- ___________ ;.\ __ 10%
I
I

GN?' ~

I
I

.-10ns

11
I I

CHIP SELECT _ _ _ _1,,1 1.SV

DOUT
DATA OUTPUT

-.. .-10ns

~~-----------A--l0%

-r--i' -- - - -. _ --.: t-1Ons

2125

cs

ALL INPUT PUlSES

-1-:,-90%

~ !-10ns

GND-

-~

r-----

"0" lEVEL

~} O~~~H Z

"1" lEVel

} O.SV

DOUT
DATA OUTPUT

WE
WRITE ENABLE
DOUT
DATA OUTPUT

\...._~~~~

tzws
"0" LEVel

r-'H-;G;i
_ } O.sv

DOUT
DATA OUTPUT

Propagation Delay from Chip Select
to High Z
All tzxxx parameters are measured at a delta of
O.5V from the logic level and using Load 1.

Write Enable to High Z Delay

TIMING DIAGRAMS
2115 READ CYCLE

2115 WRITE CYCLE
Ae-Ag

~I

--~--------------

DATA VALID

°OUT

Propagation Delay from Chip Select
All measurements referenceq to 1.5V

202

All measurements referenced to 1.5V

Si!lDotiCS

)024 BII SIAliC MOS RAM (1024Xl)
2115/2115L-F,I,N.2125/2125L-F,I,N

OBJECTIVE SPECIFICATION

TIMING DIAGRAMS

(Cont'd)
2125 READ CYCLE

2125 WRITE CYCLE

A'." _ _

..-J~'-_ _ _ _ _ _ _ _ _ _ __
I

DATA VALID

Propagation Delay from Chip Select

=
o

All measurements referenced to 1.5V

All measurements referenced to 1.5V

TYPICAL PERFORMANCE CHARACTERISTICS

100

:;-

80

~

60

r-...

5
0

::>

40

V~C=

.........

ICC vs VCC

ACCESS TIME vs CAPACITANCE

ICC vs TEMPERATURE

110

5V

:--- ~
.,.,

0

80

0-

70
20

T T
or-TA= 25°C

./

90

I-- _2115LJ~125L-

/

60

/

0

/

0

--;7

0

----

20

40

60

TEMPERATURE (0 C)

80

100

50

o

E

i---

o'"
E

TA= 25°C
Vee= 4.7SV

0

~

;:;
o
o

E
w

100

./

100

0

100

200

300
CL (pF)

G!!)DotiCS

400

500

600
Vee (V)

203

1103-I,N

DESCRIPTION
The 1103 is designed for main memory
applications where high performance, low
cost and.. large bit storage are important
design objectives. It is a random access
memory element using enhancement mod.e
p-channel MOS devices integrated on a
monolithic array. It is fully decoded, permitting the use of an 18-pin dual in-line package. The dynamic circuitry dissipates sig-

nificant power only during precharge.
Information stored in the memory is nondestructively read. Refreshing of all 1024
bits is accomplished in 32 read cycles and is
required every 2ms. A separate cenable
(chip enable) lead allows easy selection of
ari individual package when outputs are
OR-tied. Use Signetics 8T25 sense amp,
and 3207 clock driver.

PIN CONFIGURATION
I,N PACKAGE
READIWRITE

A.

Yss

Ao

CENABLE

DffiOUT

DATA IN

A,

BI,.OCK DIAGRAM

1 OF 32

READI
WRITE
AMPLIFIERS

ROW
SELECTOR

.

MEMORY MATRIX

32 ROWS
32 COLUMNS
(1024 BITS)

..
Vaa

0--

Vas

0--

VDD

0--

PAECHARGE

0--

CENABLE

0--

READIWRITE

0--

DATA IN

REFRESH AMPLIFIERS
AEADIWRITE CDLUMN
GATING

LOGIC 0= HIGH VOLTAGE
LOGIC 1 = LOW VOLTAGE

VSS

1 OF 32
COLUMN SELECTOR

A.

Ao

A,

Ao

At

ABSOLUTE MAXIMUM RATINGSl
PARAMETER

TA
TSTG
Po

204

Temperature range
Operating
Storage
Power dissipation
All input or output
voltages with respect to the most
positive supply voltage, VBB
Supply voltages Voo and Vss
with respect to VBB

9!!JDDliCS

RATING

o to 70

UNIT

·c

-65 to 150
1
-25 to 0.3

W

-25 to 0.3

V

V

1103-I,N

DC ELECTRICAL CHARACTERISTICS

TA = O°C to 70°C, VSS2 = 16V
unless otherwise specified.

± 5%,

(Vss - VsS)3

= 3V to

4V, Voo

= OV

LIMITS
PARAMETER

VIL1 4
VIL2 4
VIL34,5
VIL44,5
VIH1
VIH2
VOL

TEST CONDITIONS

TA = O°C
TA = 70°C
TA = O°C
TA = 70°C

High4
Ail inputs
Ail inputs

TA = O°C
TA = 70°C

Output voltage
Low 7
High

RLOAO

TA
TA

VOH1
VOH2

1001
1002
1003
1004
100AV
Iss

Typ

TA

During TPC8
During Tov8
During TPOV8
During TCp8
Average9

Vss
Vss
Vss
Vss

-

UNIT

Vss-14.2
Vss-14.5
Vss-14.7
Vss-15.0

17
17
17
17

Vss
Vss

Vss - 1
Vss - 0.7

+1
+1

= 10006

= 25°C
= 70°C

mV

60
50

Ail addresses = OV,
Precharge = OV
Cenable = Vss
Cenable = OV
Cenable = OV
Cenable = Vss
Cycle time = 580ns,
Precharge width = 190ns

90
80

400
400

= 25°C,

mA
37
38
5.5
3
17

Vss supply current

56
59
11
4
25
100

Output current
High

RLOAO

IOH1
IOH2

TA
TA
Capacitance 10

Max

V

input voltage
Low
All address and data in lines
All address and data in lines
Precharge, Cenable, Read/write inputs
Precharge, Cenable, Read/write inputs

Supply current

Min

f

= 10006

= 25°C
= 70°C

J.l.A
600
500

900
800

4000
4000

= 1MHz,

All unused pins are at
ac ground, VIN = Vss

J.l.A

pF

CAD
CPR

Address
Precharge

7
18

CCE
CRW

Cenable
Read/write

18
15

Data input
Cenable = OV
Cenable = Vss

CIN1
CIN2

5
4

Data output
COUT

VOUT

Smnotics

= OV

3

205

=

o

E
w
E

o
E

1103-I,N

AC ELECTRICAL CHARACTERISTICS

TA = O°C to 70°C, VSS = 16

± 5%,

(VSS - VSS);: 3:0V t04.0V, VOO =OV

LIMITS
PARAMETER

TO

FROM

TEST CONDITIONS

Min Typ Max

UNIT

READ, WRITE AND READIWRITE CYCLE
TREF

Time between refresh

tAc
tCA

Setup and hold time
Setup time 11
Hold time

2

ns
Cenable
Address

Address
Cenable

115
20

Cenable
Precharge

Precharge
Cenable

125
85

Delay time
tPcll
tcP

tovL
tOVH
toVM

ns

ns

t = 20ns

Precharge and cenable
overlap
Low
High
50% pOints

READ CYCLE

tRC

25

75
140

45

95

tAC(min) + tOVL(min + tPO(max) =
2t, tPC(min) +tOVL(min) +tPO(max)
+ 2t, t = 20ns, CLOAO = loopF,
RLOAO = 100, VREF = 40mV

Read cycle11

ns

480

Delay time
tpov
tpo

ns
End of
cenable
Output

Precharge

Output
Output

Address
Precharge

165

End of
precharge

500
120

ns

Access timell
tACCl
tAcc2

WRITE OR READIWRITE CYCLE
twc
tRWC

300
310
CLOAO= 100pF, RLOAO=loo, VREF=40mW
t = 20ns
t = 20ns

Write cycle11
Read/write cycle11

ns
ns

580
580

ns

Delay time
tpw
tpo

tw

,.;:,

tow

Setup time

tOH
tew

Hold time
Hold time

twp
tp

Precharge
End of
precharge

165

Chip enable Read/write
high
Chip enable
Data
high
Data
RIW high
RIW high Chip enable
high

80

Read/write
Output
Setup and hold time
Setup time

ms

500
12.0
ns

105
10
10

Read/write pulse width
Time to next precharge

50
0

ns
ns

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This Is a stress rating only and functional operation oltha device

6. This value of load reSistance Is used for measurement purposes. In applications the

at these or at any other condition above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for

7. The output current when reading a low output is the leakage current of the 1103 plus

extended periods may affect device reliability.
2. The Vss current drain is equal to 1100 + IOH) or 1100 + IOl).
3. NeB - Vs.) supply should be applied at or before Vss.

external noise coupled into the output line from the clocks. VOL equals IOl across the
load resistor.

8. See Supply Current vs Temperature for guaranteed current at the temperature
extremes. These values are taken from a single pulse measurement.

4. The maximum values for V,L and the minimum values for V,H are linearly related to

temperatura between O· C and 70·C. Thus any value in between O· C and 70· C can be
calculated by using a straight-line relationship.
5. The maximum values for V,llfor precharge. cenable and read/write) may be Increased
to Vss - 14.2 at O·C and Vss - 14.5 at 70·C (same values as those specified for the
address and data-in linesl with a 40ns degradation (worst casel in lAc. tpc. tRC. IwC,
tRWC. tACC1 and tACC2.

206

resistance may range from 1000 to lkO.

9. This parameter is periodically sampled and is not 100% tested.
10. This parameter Is periodically sampled and is not 100% tested. It is measured at worst
case operating conditions. CapaCitance measurements for plastiC package only.
11. These times will degrade by 40n8 (worst case) if the maximum values for VIL (for

pracharge, cenable and read/write Inputsl go to Vss-14.2V atO·C and Vss -14.5V at
70'C.

!ijgnotiGS

1103-I,N

TIMING DIAGRAMS
WRITE CYCLE OF READ/WRITE CYCLE
'we OR 'Rwe

.~~

ADDRESS

B

~ 1\

CHANGE
V IL

,~

-

ADDRESS STABLE

-=::;

A

f4-" 'OVH .....
!-'AC-

CAN CHANGE

IC~

TOV~

PRECHARGE

KADDRESS

~ I'--

VIL

-

IpC
VIH
CENABLE

V,L

~

I-

~IW-

k::

I

IpW

~IWp----l

0

REAOIWRfTE
V,L

-

~IDW(N"'C)

V ,H

DATA IN

I - " " - ' cp -

tOVL

)<

DATA CAN CHANGE

-

'CW

I-""-'p-

II
tDH (Nole DJ

K

STABLE DATA TIME

DATA CAN CHANGE

V,L
Ipo

VOH

V

DmOUT

VOL

------ ,
-- om
,

:~~~~!O~~n ~"3 I'.

C LOAD
I ACC1

=100pF

=

OUT NOT VALID

C
E
u

DifA OUT VALID
tACC2

READ CYCLE

E

'RC

V,H

ADJ~
ADDRESS
CAN
C H~

V,L

V,H

,~

B
ADDRESS STABLE

A
f---IAC-

PRECHARGE

CENABLE

II- ....
I ~

'PO-

~

H'ov

"

'CA

(

1\

,'OVH

V,L
V ,H

-

/-'OVH_

ADDRESS CAN CHANGE

E

!+--'cp-

~
14-

'POV

READ/WRITE
V ,L

(.4--'po-

/

-'I

=

V REF 70mV
R LOAO = 100n~

C LOAD

= 10rF

t ACC1

-- ,,

I'\..

DATA OUT VALID

IACe2

NOTES
A.
B.
C.
D.

VDD + 2V
tT is defined as the transitions between these two points.
Vss - 2V
tow is referenced to point 1 of the rising edge of cenable of read/write whichever occurs first.
toH is referenced to point 2 of the rising edge of cenable or read/write whichever occurs first.

!ii!lDotiC!i

207

2660-F,I,N .2660-1 - F,I,N .2660-2 - F,I,N • 2660-3 - F,I,N

DESCRIPTION

PIN CONFIGURATION

The 2660 is fabricated with n-channel silicon gate technology for high performance
and high functional density, and uses a
single transistor dynamic storage cell and
dynamic circuitry to achieve high speed and
low power dissipation.

F,I,N PACKAGE

The unique design of the 2660 allows it to be
packaged in the industry standard 16-pin inline package, which provides the highest
system bit densities and is compatible with
widely available automated handling equipment.
The use of the 16-pin package is made
possible by multiplexing the 12 address bits
(required to address 1 of 4096 bits) into the
2660 on 6 address input pins. The two 6-bit
address words are latched into the device by
the 2 TTL clocks, Row Address Strobe (RAS)
and Column Address Strobe (CAS), Noncritical clock timing requirements allow use
of the multiplexing technique while maintaining high performance.
The single transistor dynamic storage cell
provides high speed along with low power
dissipation. The memory cell requires refreshing for data retention, and this is most
easily accomplished by performing a read
cycle at each of the 64 row addresses every
2ms.

FEATURES
• Standard 16-pin DIP
• All inputs Including clocks TTL compatible
• On chip latches for address, chip select
and data In
• Tri-state TTL compatible output
• Output data Is latched and valid into next
cycle
• Read and write cycle time:
2660: 375ns
2660-1: 425ns
2660-2: 500ns
2660-3: 375ns
• Access time:
2660: 250ns
2660-1: 300ns
2660-2: 350ns
2660-3: 250ns
• Low power:
Operating: <380mW
Standby: <24mW
• RAS only refresh (no dummy cycles required)
• Page mode addressing: 2660-3
• ±10% power supply margins: 2660-3
• T RPW = RAS pulse width of 321Ls: 2660-3

208

BLOCK DIAGRAM
WAITE--------------~==c::>---2S~TR~O~B~E~--_.

CHIP SEL.~EC=T==j~;~1__t__;~..:....-.....:l::=:.~~~~
(CS) _

A,
A,
A,
A,

...
A,

4096 BIT

- 4 - - Vas
. . - Voo

STORAGE ARRAY

. . . . - Vee
~GND

CLOCK GENERATOR NO.1

ROW
(RAS)

ADDRESS STROBE.

ABSOLUTE MAXIMUM RATINGS1
PARAMETER

TSTG

Temperature range
Storage
All input or output voltages
with respect to the most
negative supply voltage Vee
Supply voltages Voo, Vee and Vss
with respect to Vee

S~DDtiCS

RATING

UNIT
·C

-55 to 150
+25 to -.5

V

+20 to -.5

V

2660-F,I,N • 2660-1 - F,I,N • 2660-2 - F,I,N • 2660-3 - F,I,N

DC ELECTRICAL CHARACTERISTICS TA = O·C to 70·C, V002 = 12V ± 5% (10%), Vee = 5V ± 10%, Vee = -5V ± 10%,
VSS = OV unless otherwise specified.
LIMITS
PARAMETER

VIL
VIH

Input voltage3
Low
High

VOL
VOH

Output voltage
Low
High

ilL
IOL

Leakage current
Input4
Output5

1001
1002

Voo current
Average6
Supply

lee
lee
CAO
Ce
COUT

Vee supply current7
Average Vee current
Capacitance

TEST CONDITIONS

Min

Typ

Max

Any input

UNIT

V
-1.0
2.4

0.8
7.0

0.0
2.4

0.4
Vee

V
IOL = 2.0rnA
IOH = -5.0rnA
Any input

p.A
5
10
rnA

CAS and RAS at VIH
Deselected

Addr~_

1

35
1.5
10
75

p.A
p.A
pF

10
7
8

CAS,RAS,CS,DIN,WRITE
Output

=
E
C
UI

E

'"
C

E

!i~nl!tiC!i

209

2660-F,I,N .2660-1 - F,I,N .2660-2 - F,I,N .2660-3 - F,I,N

AC ELECTRICAL CHARACTERISTICS8 TA = O·C to 70·C, V002 = 12V ± 5% (10%), VCC

= 5V ± 10%, Vee = -5V ± 10%,

VSS = OV, unless otherwise specified.
PARAMETER

TO

Min

tREF
tRP
tcp
tRCl
tCRl

READ, WRITE AND READ
MODIFY WRITE CYCLES
Time between refresh
RAS precharge time
Column precharge time
Lead time
Leading edge9
Trailingedge lO

2660-1

2660

FROM

Typ

Max

Min

Typ

2
115

CAS

-RAS

Output
Output

CAS
RAS

60
-40

UNIT
Max

2
125

110
40

135
50

80
-50

Access time
tCAcll
tRAC12
tT
tOFF

ns
140
250

Rise and fall time13
Output buffer turnoff delay

3
0

Setup and hold time
CAS
Address or CS
Setup time
Address or CS
CAS
Hold time
READ CYCLE
Random read cycle time12,14
tRC
Pulse width
tcpw
CAS
RAS
tRPW
Setup and hold time
Setup time
WE high
CAS low
tRCS
tRCH
CAS high
Hold tiiTle
WE low
Hold time
tRSH
R""~ high
CAS low
Hold time
tCSH
CAS high
RAS low
WRITE CYCLE
Random write cycle time12,14
tRC
Pulse width
tcpw
CAS
RAS
tRPW
twp
Write command
Setup and hold time
Setup time15
CAS
Data in
tos
Hold time 15
Data in
tOH
CAS
Hold time
tRSH
RAS high
CAS low
Hold time
tCSH
CAS high
RAS low
Hold time16
tWCH
WE high
CAS low
tCWl Lead time
~high
WE low
READ MODIFY
WRITE CYCLE
tRMw Read modify write cycle
time12,14
Cycle width
CAS
tCRW
RAS
tRRW
Pulse width
twp
Write command
Setup and hold time
Setup time
Data in
CAS
tos
Hold time
Data in
CAS
tOH
Setup time
tRCS
~Iow
WE high
Hold time
tRWH
~high
WE low
Hold time
tCWH
CAS high
RAS low
tCWl Lead time
CAS high
WE low
tMOO Modify time
WE low
Data out

50
65

165
300
50
80

3
0

ns
ns
ns

0
60

0
80

375

425

tAS
tAH

210

ms
ns
ns
ns

140
250

10000
10000

ns
ns
10000
10000

165
300

ns
0

0

140
210

165
250

375

425

ns
ns

140
250
110

9i!100tiC9

10000
10000

165
300
130

10000
10000
ns

0
130
165
250
130
130

0
110
140
210
110
110

ns

475

10000

555

10000

250
360

10000
10000

295
430

10000
10000

ns
ns

ns
110

130

0
110
0
110
360
110
0

0
130
0
130
430
130
0

ns

ns
ns

2660-F,I,N • 2660-1 - F,I,N .2660-2 - F,I,N • 2660-3 - F,I,N

AC ELECTRICAL CHARACTERISTICS8 (Cont'd) TA = O°C to 70°C, V002 = 12V ± 5% (10%), Vcc = 5V ± 10%,
Vee
PARAMETER

tAEF
tAP
tcp
tACl
tCAl

READ, WRITE AND READ
MODIFY WRITE CYCLES
Time between refresh
RAS precharge time
Column precharge time
Lead time
Leading edge9
Trailing edge 10
Access time

tCAcll
tRAC12
tT
tOFF
tAS
tAH
tAC
tcpw
tRPw
tACS
tRCH
tASH
tCSH
tRC
tcpw
tRPw
twp
tos
tOH
tRSH
tCSH
tWCH
tcwl

tRMW

tCRw
tRRw
twp
tos
tOH
tRCS
tRWH
tCWH
tcwl
tMOO

Rise and fall time 13
Output buffer turnoff delay
Setup and hold time
Setup time
Hold time
READ CYCLE
Random read cycle time12.14
Pulse width
CAS
RAS
Setup and hold time
Setup time
Hold time
Hold time
Hold time
WRITE CYCLE
Random write cycle time12.14
Pulse width
CAS
RAS
Write command
Setup and hold time
Setup time15
Hold time15
Hold time
Hold time
Hold time16
Lead time
READ MODIFY
WRITE CYCLE
Read modify write cycle
time12.14
Cycle width
CAS
RAS
Pulse width
Write command
Setup and hold time
Setup time
Hold time
Setup time
Hold time
Hold time
Lead time
Modify time

NOTES on following

TO

= -5V ± 10%, VSS = OV, unless otherwise specified.
FROM

2660-2
Min

Typ

2660-3
Max

Min

2
150

CAS

-RAS

Output
Output

CAS
RAS

110
-50

Typ

Max

2
115
110

150
50

60
-40

UNIT

ms
ns
ns
ns

110
40
ns
140
250

200
350

3
0

50
100

3
0

50
65

ns
ns
ns

CAS
Address or CS
CAS
AddB[sor

0
100

0
60

500

375

200
350

10000
10000

140
250

r;
o

ns
ns
32000
32000
ns

CAS low
WE low
RAS high
CAS high

WE high
CAS high
CAS low
RAS low

0

0

200
350

140
210

500

375

200
350
150

10000
10000

140
250
110

E
w

E

....o

ns
ns
32000
32000

E

ns
CAS
Data in
RAS high
CAS high
WE high
CAS high

Data in
CAS
CAS low
RAS low
CAS low
WE low

0
150
200
300
150
150

0
110
140
210
110
110

ns

650

10000

475

32000

350
500

10000
10000

250
360

32000
32000

ns
ns

ns
150

110

0
150
0
150
500
150
0

0
110
0
110
360
110
0

ns
CAS
Data in
~A2low
RAShigh
CAS high
CAS high
WE low

Data in
CAS
WE high
WE low
RAS low
WE low
Data out

ns
ns

page.

G~nl!tiCG

211

2660-F,I,N .2660-1 - F,I,N • 2660-2 - F,I,N .2660-3 - F,I,N
10. Implies ItcRll :S40ns only for minimum cycle time; otherwise ItCAll >40ns is legal for
other than minimum cycle time.
11. Assumes tRCl + tT > tRCl (max). If not, the access time is controlled by tRAC.
12. Assumes that tRCl + tT < tACl (max). If tRCl + tr > tRCl (max), then tAC and tRAC will be
longer by the amount tRCl + h exceeds tRCL (max),
13. Rise and fall times measured between VIH and Vil.
14. The minimum cycle time is achieved by compensating for RAS rise and fall times with
tCAl. The minimum cycle time is then constrained by tRCL (max) + tcpw + tAP.
15. These parameters are referenced to the CAS leading edge in random write cycle
operation and to the Write leading edge in read~write or read-modify-write cycle.
16. Write command hold time is important only when performing normal random write
cycles. During read-write or read-modify-writecycles, the write command pulse width
is the limiting parameter.
17. All voltages reference to Vss.
18. Output voltage will swing from Vss to Vcc independent of differential between Vss
and Vec.

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation 91 the device
at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reffability.
2. Voo = 12 ± 10% for the 2660-3.
3. Input voltages greater than TTL levels (0 to 5V) require device operation at reduced

speed.
4. All device pins at OV except Vee at -5V and pin under test which is at +10V.
5. Output disabled by chip select input.
6. Current is proportional to clock speed with maximum current measured at fastest
cycle rate.
7. Oepends upon output loading. The Vec supply is connected to the output buffer only.
8. Assumes tT == 5ns.
9. For minimum cycle, tACl has a maximum value of 110ns.

TIMING DIAGRAMS
READ CYCLE
' RC

1..--

tRPW
V,H
A

"AS
VIL

i\

J

•

tRP - - - - . . .

F

tCSH
....--tRCL~

V,H
CAS
V,L
tASV,H
ADDRESSES
V,L

:~

~

.... ,AH . . .

ROW
ADDRESS

0

A

'ASVIH

cs

A~

-

r\\ \\ •
_

'AS

V,H

WE
V,L

K
_'AH-

-,

:t.

'OFF_
VOH
DOUT
VOL

/

-

I-'RCS

IRAC

212

;+--'AH _

COLUMN
ADDRESS

-

"V

tcpw

B

VIL

tCRL I -

IRSH

-C

lo

Sjgnotics

tCAe

I

'--

VALID
DATA OUT

tRCH

266D-F,I,N • 2660-1 - F,I,N .2660-2 - F,I,N .2660-3 - F,I,N

TIMING DIAGRAMS

(Cont'd)
WRITE CYCLE

..

'RC

"'~'RP-

'RPW
V'H

~

RAS

.I{i

8
V'L

F

leSH

V'H

r\\\ \ 1<-,

~

CAS
V'L
IAS-

V'H
ADDRESSES
V'L

~

I-

--'AH-

A

ROW
ADDRESS

B

tCAl

IRSH

-'RCL

~

'AS-

0

V'H

!-'AH-

X

COLUMN

ADDRESS

~

'AS-

!-'AH-

V

\ ..

Cli
V'L

~

'CPW

tCWL

ViH

WE
V'L

V'H
D'N

I-'WCH~

"

-'DS

K

B

'DI'f'DOUT

o

'DH

..
)

V'L

VDH

=

'WP

8

E
w

f1\(:

E

E

Ill)
VOL

o
E

!imDatiC!i

2t3

2660-F,I,N .2660-1 - F,I,N • 2660-2 - F,I,N .2660-3 - F,I,N

TIMING DIAGRAMS

(Cont'd)
READ MODIFY WRITE CYCLE

•

tRMW

~IRP_

tRRW

V,H

A

RAS

~

-

a
V'L
ICWH
.....-- tRCL--..

V,H

~

CAS
V'L

'AH

ADDRESSES'
V'L

~

~~

r-+
ROW

a

ADDAESS

V,H

K)
A~

Ci

~.AH_

COLUMN
ADDRESS

~

K
V
i-

-i'RCSI-

'wp_

V,H

WE

a.if

V'L

IMOC-

i-

-~

V,H

~

D,N
V'L

-

IT

"

!-'DH_
rot-'DS

:

DATA IN
VALID

tRAC

VOH
COUT

tOFF

t~

·CAe
HIGH
IMPEDANCE

VALID

DATA OUT

0

VOL

NOtES
A,B.VIHMIN and VILMAX are reference levels for measuring timing of input signals.
C,D.VOHMIN and VOLMAX are reference levels for measuring timing of Dour with 100pf load.
E. If WE goes low while CAS is low, Dour could go either VOL or VOH after tCAe. Dour will be in open
circuit state (write cycle waveforms), If WE goes Low before CAS goes low. In a read-modlfy-write
cycle DOULls data read and does not change during modify-write portion of the cycle.
F. For minimum cycletiming, tcRLmust beOto 40ns forthe 2660 and 2660-3; Oto 50ns for the 2660-1 and
2660-2.

RAS ONLY REFRESH CYCLE

tr=

ADDRESSE~,L

'RC~~

~~ "~'M~- ~_~:.: ~_-_-_tR_P= = =

-:: ___

...x

'M

_ ___

__

AD~~~SS ~,,----------------

VOH--------------------------------------------------------

DOUT
V DL

214

•

IcWL

!+-·AH ....

a

V'L

t-

1I
~'RWH-

~

·AS ....

A

'CAL

a

~

'AS

V,H

tCRW

ItF

!ii!JDotiC!i

K

2660-F,I,N .2660-1 - F,I,N • 2660-2 - F,I,N .2660-3 - F,I,N

TIMING DIAGRAMS (Cont'd)
2660-3
PAGE MODE READ CYCLE
V'H

I'~-------------------------'APW-------------------------'I

AAS
V'L

V'H
CAS
V'L

V'H
ADDRESSES
V'L

V'H

CS
V'L

VOH

I;

°OUT
VOL

o

':"=-,-1:

--------~~----------~~~--------~ll~---------r------------

V'H

WRiTE

E
w

V'L

2660-3
V'H~

~

'APW

AAS

'2

V'L

~tRCL""

_'CPW_

V'H
CAS

'w -

t:::
1/1.

_'CPW _

;

_

E

f'·~

PAGE MODE WRITE CYCLE

o
E

_'ASH

-l).----....

~'CPW·-

~

:;

V'L

ADDRESSES

V IH

~ COL'AS
~~

I
ROW
ADD

ADD

V'L-""'":""'"""

.....

'AS-+!

K

es

V'H

AOO

~

,

l1"

V'L
.... 'OFF_I

Dour
VOL

-.

V'H
V'L

V'H

"'

1
- -

V'L

HIGH
,MPEOANCE

I~

tWCH

·rll~
)t
l(

r--

~'CWL_

:;

VALID
DATA

COL
ADO

--..i.

IOS-

;

-

;
'WP

r--

l4-'jL-.

1 T

_I=!

'DS-

l(
"

9jgDDliG9

IWCH

~

I-

-I~
VALID
DATA

[(

"'

"

'WP

D'N

I

'AS_

;

-I-

tos-

~

It'AH-'
"

~'CWL_

WRITE

X

W,::H-

"1r

'WCH

'AS-j

~

'AS

V OH

_-'AH

n.

f'coL""(

'AH . . .

~

_-'AH

-tAH

I-r'AH

X

'WP

i-

'DH
~

VALID
DATA

[(
215

!i
268Q-F,I,N • 2680-1-F,I,N .2680-2-F,I,N

PIN CONFIGURATION

DESCRIPTION
The 2680 incorporates the latest memory
design features and can be used in a wide
variety of applications, from those which
require very high speed to ones where low
cost and large bit capacity are the prime
criteria.

F,I,N PACKAGE
Voo (GNO)

A,
A,

The 2680 must be refreshed every 2ms. This
can be accomplished by performing a read
cycle at each of the 64 row addresses (AoAs). The chip select input can be either high
or low for refresh.
The 2680 has been designed with minimum
production costs as a prime criterion. It is
fabricated using n-channel silicon gate
MaS technology, which is an ideal choice
for high density integrated circuits. The
2680 uses a single transistor cell to minimize
the device area. The Single device cell,
along with unique design features in the onchip peripheral circuits, yields a high performance and low cost memory device.

VOO (12)
CE CLOCK
HC

BLOCK DIAGRAM
AD
Al
A2

ROW DECODE

64

MEMORY

ARRAY
64X84

AND BUFFER

A3

REGISTER

A4

AS

64

COLUMN
AMPLIFIERS

CE

AS

A7

AI

A9

A10

A11

ABSOLUTE MAXIMUM RATINGS
PARAMETER

TA
TSTG
Po

216

Temperature range
Operating under bias
Storage
Power dissipation
All input or output voltages with
respect to the most negative
supply voltage, VBB
Supply voltages Voo, Vee, and
VSS with respect to VBB

Si!lDOliCS

RATING

o to 70

UNIT

·C

-65 to 150
1.25
20 to -0.3

W
V

20 to -0.3

V

268D-F,I,N • 2680-1-F,I,N .2680-2-F,I,N

RECOMMENDED OPERATING CONDITIONS
LIMITS
PARAMETER

Min

Typ

Max

4.75
11.4

5
12
0
-5

5.25
12.6

UNIT

Supply voltage
VCC
Voo
Vss
VBB

V

-4.5

DC ELECTRICAL CHARACTERISTICS
PARAMETER

-5.5

TA = O·C to 70·C unless otherwise specified
LIMITS

TEST CONDITIONS
Min

VIL
VIH
VILC
VIHC

Input voltage
Low
High
CE low
CE high

VOL
VOH

Output voltage
Low
High

ILC
III

Input load cu rrent
CE
All inputs except CE

IILol

Output leakage current
high impedance state

1001
1002

Supply current (Voo)
During CE off3
During CE on

100AV1

Average Voo current

ICC1
IBB

Supply current
VCC4
VBB

CAD
CCE
CIN
COUT

Capacitance5
Address, CS
CE
Input and WE
Output

Typ2

UNIT
Max
V

-1.0
2.4
-1.0
Voo -1

0.6
Vcc +1
1.0
Voo +1

0.0
2.4

0.45
Vcc

=
o

V
IOL = 2.0mA
IOH = -2.0mA

/Jo A

VIN = 0 min to VIHC max
VIN = 0 min to VIH max, CE = VILC or VIHC

.01
.01

2
10

CE = VILC or CS = VIH, Vo = OV to 5.25V

.01

10

/Jo A

CE = -1V to 6V
CE = VIHC, CS = VIL

50

200
60

/Jo A
mA

Cycle time = 400ns, CS = VIL. tCE = 230ns,
TA = 25·C

35

54

mA

CE = VILC or CS = VIH

.01
5

10
100

/Jo A

pF
VIN = Vss
VIN = Vss
VIN= Vss
VOUT= OV

9~nl!tic9

4
13
5
4

6
25
10
7

217

E
w
E

...o
E

2680-F,I,N • 2680-1-F,I,N .2680-2-F,I,N

AC ELECTRICAL CHARACTERISTICS Over recommended supply voltage range,
TA

= O°C to 70°C, tr = 20ns, CL = 50pF,
= 1 TTL gate, tACC = tAC + tco + 1tT

Load

2680
PARAMETER

TO

tREF

READ, WRITE, AND
READ MODIFY!
WRITE CYCLE
Time between refresh

tAc
tAH

Setup and hold time
Setup time
Hold time

tcc

tr
tCF
tCY
tCE
teo
tAcc
twL
twc

READ CYCLE
Cycle time
CE on time
CE output delay time
Access time

Min

Typ

Output

Address
CE

0
100

CE off

130
10
0
400
230

O~ut

WE
CEon

Address
CE
WE

2680-2

2680-1
Max

Min

Typ

Max

4000
180
200

130
10
0
470
300

40

4000
250
270

Max

1

380
10
0
800
380

40

4000
320
350

0
0

0
0

0
0

Typ

UNIT

ms
ns

10
100

0
100
40

Min

2

2
CE
Address

CE off time
CE transition time
CE high impedance state

FROM

ns
ns
ns
ns
ns
ns
ns
ns
ns

~

tCY
tCE
tw
tcw

WRITE CYCLE
Cycle time
CE on time

tow
tOH

Setup and hold time
Setup time6
Hold time

twp

WE

470
300
150
150

CE off
WE

WE
CE

400
230
150
150

WE
DIN

DIN
CE

0
0

0
0

0
0

50

50

100

4000

800
4000 380
200
150

4000

ns

ris

Pulse width

tRwC
tCRW
tw
twc

READ, MODIFY,
WRITE CYCLE
Cycle time
CE width during cycle

tow
tOH

Setup and hold time
Setup time
Hold time

twp

Pulse width
WE

tco
tACC

Delay time
Access time

590
420
150
0

960
4000 540
200
0

CE off
CEon

WE
WE

520
350
150
0

WE
DIN

DIN
CE

0
0

0
0

0
0

50

50

100

4000

4000

ns
ns
ns
ns
ns

ns
Output

CE

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This Is a stress retlng only and functional operation of the device at these or any other
conditions above those Indicated in the operational seclions of this specification is not Implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. Typical values are for TA = 25'C and typical power supply voltages.
3. The 100 and Icc currents flow to Vss. The lae current Is the sum of all leakage currents.

4. During CE on Vee supply current is dependent on output loading Vee is connected to output buffer
only.
5. Capacitance measured with Boonton Meter or effective capacitance calculated from the equation
with the current equal to a constant 20mA.
'6. "WE is low before 9E goes high then OON must be valid when CE goes high.
7. The only requirement lor tne sequence of applying voltage to the device is that Vee. Vee. and Vss
should never be .3V more negative than V8B.

218

ns
ns
ns
ns

9!!1notic9

180
200

250
270

320
350

ns
ns

2680-F,I,N • 2680-1-F,I,N .2680-2-F,I,N

TIMING DIAGRAMS
READ AND REFRESH CYCLE A
~---------------------------------ICy--------------------------------~·1

V ,H
ADDRESS
ANDCS

V ,L

IAH-

~----------------------ICE--------------------~

V,HC

-----+------+_.W---------------------------------------------------~

CE

VILC -----~--.::...II

V,H----~----~4_+_----------------------------------------------------4_+_~----------+_------

WE
V IL ----~--,
~---------------------ICO------------------·I
V OH - - -

Dour

-IMP~~~CE-

VOL - -

r;
o

----

VALID

-1fo~----------'-------------------------,ACC------------------------~1

E
w

WRITE CYCLE

.,;=:)

'Cy

... c

ADORE,!!
ANDes

' AC VIHC

ADDRESS STABLE

B

V,L

I

-

K

AJORESS STABLE

ADDRESS CAN CHANGE

-....

IAH
'CE
E

I

CE

I

D,
VILe

'CW

V,L

-

V,H

o IN CAN CHANGE

D,N

V,L

VOH--- - - - DOUT""-

\[-

WE CAN CHANGE

IMP~6G~CE--

VOL-------

r\

/

J
s~nDliC!i

I
-

WE CAN CHANGE

-

-lOW

~

_IT

.--

I - 'c c -

! - IWp -

WE

----

. \r-

IW

V,H

-IT

...

- t OH

J<

DIN STABLE

DIN CAN

CHANGE

-----UNDEFINED

-

----

IMP~~~~CE-

-----

-ICF

~

IE

....o
E

2680-F,I,N • 268Q-1-F,I,N .2680-2-F,I,N

TIMING DIAGRAMS

(Cont'd)
READ, MODIFY, WRITE CYCLE

.
V'H
ADDRESS

ANDCS

V'L

~
--

'AWC(A)

C
ADDRESS STABLE

B

~K

ADDRESS CAN CHANGE

.,

f--'AC
'AH

II

VILe

WE

I-I-'wc

t-'CC-

)

i-:-- DH

-~

...--tow

K

D'NCAN
CHANGE

DIN STABLE

------r\
~~::::-=-

F

)

HIGH

VALID

lAce

'CF-

NOTES

A. For Refresh.cycle row and column addresses must be stable before tAC and remain stable for entire
tAH period.
S VIL max is the reference level for measuring timing of the addresses, es, WE, and DIN.
C. V'H min is the reference level for measuring timing of the addresses, CS, WE, and D'N.
D. Vss +2.0V is the reference level for measuring timing of CEo
E. Voo -2V is the reference level for measuring ti~ing of CEo

F. Vss +2.4V is the refe.rence level for measuring the timing of Dour.

220

We CAN CHANGE

'CO

HIGH
IMPEDANCE'"

--l~ I ~

A

V

r\

D IN CAN CHANGE

..

-

!-'wP--<

.-J

-----r\

1\

'w

..

D

-

l:'"'-

-'

E

CE

'T- I -

~'T

tCRW

VIHC

stgnotics

-

2530-I,N

DESCRIPTION

PIN CONFIGURATION

The 2530 has a read input which controls
the entry of data from the ROM into output
latches. Three-state outputs allow OR-tying
for implementing larger memories. Two
mask programmable output enables control
the 8 output devices without affecting address circuitry.

I,N PACKAGE
OUTPUT 8

1

OUTPUT 7

2

OUTPUTS

OUTPUT'

3

OUTPUT 4

VDD(GNO)

4

A,
OUTPUT
ENABLE 1
OUTPUT

7

READ

8

NC

ENABLE 2

9

At

BLOCK DIAGRAM

A.

0,

VGG

At

,.,

At

ROW
DECODER
10F84

409681T
ROM MATRIX
512X 8

~

OUTPUT
LATCHES
(8)

o

.....---~-oo,

E
w

...o
E

READ

E

ABSOLUTE MAXIMUM RATINGS 1
PARAMETER

TA
TSTG
Po

Temperature range
Operating
Storage
Power dissipation at 70·C2
Input and supply voltages
with respect to Vee3

RATING

UNIT

·C

o to 70
-65 to +150
730

mW

+0.3 to -20

V

SillBOlies

221

2530-I,N

DC ELECTRICAL CHARACTERISTICS TA = O·C to 70·C, Vee = 5V ± 5%, Von = OV, VGG '" -12V ± 5%,
unless otherwise specified.4,5,8,7
LIMITS
PARAMETER

Vil
VIH

Input voltage 8
Low
High

VOL
VOH

Output voltage
Low
High

III

'.

TEST CONDITIONS

Min

Typ

Max

UNIT
V

0.6
5.3

-5
3.4

V
0.5

IOl = 1.6mA
IOH = 100ILA

3.8

Input load current

VIN = -5.5V, TA = 25°C

10

500

ILO

Output leakage current

VOUT =OV, TA = 25·C

10

1000

Icc
IGG

Supply current9
Vee
VGG

CIN

Address input capacitance

nA
nA
mA

30

30
VIN = Vee, VAe = 25m p-p, f=1MHz

45
45
10

pF

o·c to 70·C, Vee = 5V ± 5%, VDD = OV, VGG = -12V ± 5%,
unless otherwise specified.

AC ELECTRICAL CHARACTERISTICS TA =

LIMITS
PARAMETER

tRPW
tfjpw

Pulse width
Readl0
Readll

tAD
tAG

Address time12
Delay
Read

FROM

TO

Min

Typ

250
500

200
400

Max

ns

Address
Read high

Fi'8ad low

tAl13
tA213

Output
Output

tOE

Output

Address
End of read
pulse
Output enable

ns
50
50

Address

Delay time

ns

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may ~use permanent damage to the
device. This is a stress rating only and functional oparation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied;
2. For opareling at elevated tempareturea the device must be derated based on +lSO'C maximum

junction temperature and a thermal resistance of 110°CIW junction to ambient.
3. All inpulS are protected against static charge.
4. Parameters are valid over oparetlng tempareture range unless specified.
5. All voltage measuraments are referenced to ground.
6. Manufacturer reserves the right to make design and process changes and improvements.
7. Typical values are at +25'C and typical supply voltages.
8. Guaranteed Input levels are stated for worst case conditions Including a ±5% variation in Vee and a
tempareture variation of O'e to TO'C. Actual input requirements with respect to Vee are V,H = Vee
-1.85V and V,L = Vee -4.15V.
..
9. Outputs open, tRPw = 25Ons, tiipw = SOOns.
10. During tiiPWl addresses are decoded and sent to the memory matrix and the stored memory data is
movad to the data inputs of the output RS latches. This data is clockad Into the output latches at the
end (rising edge) of the iii8d pulae. After tA2 data appears at the output terminals.
11. During tRPW' data is clocked Into the output latches and the address decoders are precharged In
preparation for the next cycle.
12. Addresses must be atablewlthln SOns after the re8ci line falls and must remain stable until at least50ns
before the re8ci line goes high.
13. IA = O'C to +70'C.

222

UNIT

s~nmies

625
200

700
250

100

250

ID96 811 HIGH SPEED STIITIC MuS ROM (51218)

2531J
2530-I,N

TIMING DIAGRAM
, -....o----t.pw---~
---------+7----~

ADDRESSES

ADDRESSES MAY CHANGE

I

--.~I----,---'''~~­
X
L
OUTPUTS

All tImes measured from 50% points. for all input waveforms tr

CUSTOM CODING
INFORMATION
Data Card Format
HEADER CARD
Card No.1
Columns
1-5
6-14
15-19
20
21
22
23
24-71
72
73-80

2530N or 25301
Blank
CODED
Blank
Logie state of Output Enable
#2, (CS2)-Most Significant Bit
Logic state of Output Enable
#1
Blank
Customer company name
Blank
Date

1.0./ COMMENT CARDS
Card No.1
Columns
1
C
2
Blank
3-80
Person responsible for reviewing Signetics truth table and
company name
Card No.2
Columns
1
C
2
Blank
3-80
Customer city, state, zip

= tf = 10n5.

DATA CARDS
Card No.1
Columns
1-3
Decimal address (blank, blank,
Ol
4
Blank
5-12
8-digit binary output (MSBleft)"
13-20
Blank
21-33
Decimal address (blank, blank,

=
o
..
E

1)

24
25-32
33-40
41-43

Blank
8-digit binary output (MSBleft)"
Blank
Decimal address (blank, blank,

...o
E

2)

44
45-52
53-60
61-63

Blank
8-digit binary output (MSBleft)"
Blank
Decimal address (blank, blank,

E

3)

64
65-72
73-80

Blank
8-digit binary output (MSBleft)"
Blank

Card No.2
Same format as Card No. 1
Card No.12B
128
Same format as Card No.1
'MSB~

o.

SmootiCS

223

2530-I,N

EXAMPLES
Header Card
'?~30

C1"3~31

COFEF 00 PSCII TO EBCDIC PND HcnlC TO PSCII C[1DE CONV

I

I III

I III

111111 I I 111111

I III I II I

I

II

0001000000,0000000' 0 011 0 01 0 I 0 01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Oil 0 0 01 0 0 0 0 0 I BOO 0 0 01 0 0 0 0 01 0 01 0 0 0
I 234 S' 1 • Illllll1nHS111FI"UlnUtlMZ5I12121n.31.J;Sl4!SlI11 • • • ".UUU'.4141"Sl5TSZU" • • 5lSlStIlJ1Rllf.t • • J7 ... ,.nnnl0511r".I..1

11111111111111111111111111111111111111111111111111111,111111111111111111111111111

12122222222222222222222/12222222 2122 2 2 22 2 2 2212 2 2 2 22 2 2 21222 2 2 22 2 2 22 2 2 22 2 22 212 2 2!2
331333313131331333333333313331331313313333333133131333313 3 313 3 3 313 3 3 3 3 3 313 3 3 3 3 3 3

44144141144444441114444444141444444144444144441444144 4 4 44444 414444444 4 444 4 414141
SIS 5 555555155555515555555555555 SIS 5 5 5 5 5 51 5 SIS 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 515 5 5115 5 5 5 5 5 5 5 5 5 5 5
6666666666666661666666 I I 6 6 6 6 6 61S 6 66 6 6 6 6 6 6 66 6 6 66 6 6 611S 66 6 66 6616 6111G 6 6 6 6 6 6 &6 6 6 &6 &

7777777777777777777777777777777777777777777777777 7777 7777777 7777 7 7777 7 77 77777117
888888888888888888888888 B8 8 88 8 8 8 B8 8 B8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 88 88 8 8888 8 8 8 8 8 B8 8 8 8 8 8 8 8 8 8
99999999999999999919999999119999999919999999999199999 9 9 9119 9 9 919 9 9 9 9 9 9 9 99 9 919 9 9 9
1 , 3 . S S 1 I t IDtlIl13141S1111l1llZfZl U!lZHHUfZlZllUI3Z333US3631311:1940414t4I4HSlUlqc,5Q51

S2~54S55UUU!ll"U2635415."HII1~II1!I114151I1'1J'IIO

I."IJIII[)

First Data Card

o

0'0000000

1 00000001

001011111111 0 0 0 0 B0 I 0 0 0 011111111 0 0 0 0 00000000011111111 0 0 0 0010000001111110000000000
, 13 4

$"

I I IDlI1211141SIIIfItIUUliI223rUnlrrzu.,.:nIUU415.» • • • n4UU41541414lUSI51 !l2USU551U5IS..IIIIIU3101IS1U,II.la,, '111 ,. IS lUI II 11.

111111111111111111111111111111111111111111111111111 fl111111111111111111111111111

2222222222222222222222222222222222222222221222222222 2 22 222 2 22 22 2 22 2 2 22 2 2 22 2 222 2 2
33333 n 33 3 3 3 3 3 3 3 3 3 3333 3 33 3 3 33 3 3 3 3333 3 3 3 3 33 3 3333333 33333333333313 3 3 333 3 333 3 333 3 3 3

44441114414444444144441441441141444444144441141444444414444141444411444444444444
55iS555SSS5SS55555S55555S5555555555555555555555555S55555555555555555555555555555
t6 I 6 6 6 6 6 6 6 6 6 6 611116 I 6 666 6 616 611" i 116 16 6 6 61616166116 1616 6 616 6 6 6 116 6 66 6 6 66 6 616 661

7777777777777777777777777777777 7 7 7 77 7 77 7 7 77 7 7 7 77 77 7 7 77 77 7 7 7 77 7 7 7 77 7 7 77 7 77 7 77 7 77 7
1888888888881881111881188818888 8 8811818 811181888 88 8 i 11181888 8 8 8 8118 8888118 8 8 8 818
99919999999999999919999999919991999999119999919999999919999119999999999199199999

12 I 4 S 11 I II0I1I!UI415\&1,..,UUI!2ZUU521UnaaJ1RUMluuun.4I4I4UU445.U,,4I5UI S2SU4KSlSUII • • ll IZIUU$M&J • • ",I rm I. IUHI JI lUll

_1lIIOl

Last Data Card

/oe

00{IQOM0

~o,.

00000000

510 00000000

511 00000000

0100111111110000000001001111111100000000001111111111 D0 0 DI 0 0 0 0 0 0 011111111 0 0 0 0 0 0 0 0
12 I. S 17. ,""'ZIIt415111J1I1UUIIU3N152112121Z1»J1321IMJ5:113UI3I411414UUU5QUQ4l5l5l,.SSMB!IlIUSI.All I2UNluu,.,uen nil 141UI fHtJllD

11111111111111111111111111111111111111111111111111111111111111111111111111111111

2212222222222222222222222221222112211 2 2 222 2 21 22 2 22 122 2 2 22 2 2 22 11 2 2 2 22 2 2 22 22 2 2 2 22 2
333333333333333333333333333333333333333333333 31333333 33331333333 3 3 3 333 3 3 333 3 3 311

44444444444444444444444444444444444444444444444444444444444444414444444444444444
- 55555555555555 S5S551S55555555S555S5!55 5155555555 5555555SS551i5SS5SSSSS55 5555555
61161666666666161111661166166'111661&1111161666661166611i161166616i6661116616i666

7717777777777717177777777717717777 7 7 77 7 717 7 77 717 7 7 7 717 7 7 7 77 7 7 77 717 711717 7 7177 77 7
88188881888ii811111Bi11888181118i81Uli1118B181B888111111818811181188'18181188888
999999111119 91119111!!! 11911119 9 91919 91119119 9 999 919 911119 9 9 9119 91919 9 9 9 9 91919 9 9
I r I ' 5 11'11 .'::.g&j"SllIrlln.2u2Z3NI5.Ufta."u:luus." . . . . . 'U3414H.O • • • nSliJ54S~.5J5I •• ll.UN.5I.., • • ,.nnllH'51fn1l7l"

224

9~nDliC9

OBJECTIVE SPECIFICATION

2609-F,I,N

DESCRIPTION

FEATURES

The 2609 is a mask-programmable 8192-bit
row select character generator. It contains
128 characters in a 7X9 matrix, and has the
capability of shifting certain characters that
normally extend below the baseline, such as
j, y, g, p and q. Circuitry is supplied internally to effectively lower the whole matrix for
this type of character, a feature previously
requiring external circuitry.

•
•
•
•
•
•
•
•

A 7-bit address code is used to select 1 of
the 128 available characters. Each character
is defined as a specific combination of logic
"1 "s and "O"s stored in a 7X9 matrix. When a
specific 4-bit binary row select code is applied, a word of 7 parallel bits appears atthe
output. The rows can be sequentially selected, providing a 9-word sequence of 7 parallel bits per word for each character selected
by the address inputs. As the row select
inputs are sequentially addressed, the devices will automatically place the 7X9 character in 1 of 2 pre-programmed positions on
the 16-row matrix, with the positions defined by the 4 row select inputs.
Complete TTL compatibility is provided, as
well as direct interfacing with other NMOS
devices, and with CMOS when using a +5V
power supply. Maximum access time is
500ns; however, if a device is programmed
without shifted characters, the access time
is reduced.

PIN CONFIGURATION

Static operation-no clocks
Access time: 500ns max
Single 5V power supply
TTL compatible inputs and outputs
Power dissipation: 525mW
N-channel silicon gate technology
Standard 24-pin package
All inputs are capacitive and do not sink
or source current

F,I,N PACKAGE
RS4
RS3
RS2
RS1

B,

NIC

A,
NIC
VSS

=

BLOCK DIAGRAM

o

20 81

A1 15

A2 16
S 82

A3 12
A4 11
AS

9

A6

•

A7

4

ADDRESS
DECODE

MEMORY
MATRIX
(8064)

ROW

DECODE

19

83

•

B4

13

85

OUTPUT
BUFFERS

E
w
E

....o

7 86

17 87

SHIFT
CONTROL

MATRIX
(128)

E

Vcc- PIN2

AS1

RS2

RS3

RS4

ABSOLUTE MAXIMUM RATINGS1
PARAMETER

TA
TSTG

Temperature range
Operating
Storage.
All input, output and supply voltages
with respect to ground pin

GillDnliCG

RATING

UNIT
°C

o to 70
-65 to +150
-0.5 to +7

V

225

OBJECTIVE SPECIFICATION

2609-F,I,N

DC ELECTRICAL CHARACTERISTICS TA = O°C to 70°C, Vee = 5.0V ± 5% unless otherwise specified.
LIMITS
PARAMETER

TEST CONDITIONS

VIL
VIH

Input voltage
Low
High 1

Driven by TTL

0
2.2

Vos
Voo

Output voltage
Low (Blank)
High (Dot)

IOL = 1.6mA
IOH = -40!,A

0
2.4

IIH

Leakage current

VIH = 5.25V, Vee = 4.75V

lee

Supply current

CIN
COUT

Capacitance 2
Input
Output

UNIT

Max

Typ

Min

V
0.65
Vee
V
0.4
10

!,A

80

100

mA

4.0

7.5
15

f = 1.0MHz, TA = 25°C

AC ELECTRICAL CHARACTERISTICS

pF

TA = O°C to 70°C, Vee = 5V ± 5% unless otherwise specified,
VIN levels = 0.65V and 2.2V or driven by TTL, Input tr and tl < 20ns,
Measurement reference level = 1.5V, Output loading = 1 TTL gate +130pF
LIMITS

PARAMETER

TO

FROM

Output
Output

Address
Row select

Min

Typ

Max

350
300

500
500

400

525

Access time

ns

tAeC(A)
tACC(RS)
Power dissipation

Po

UNIT

mW

NOTES
1. No pullup resistors are required.
2. Capacitances are periodically sampled rather than 100% tested.
3. This is advance information and specifications are subject to change without notice.

MEMORY OPERATION USING
POSITIVE LOGIC (Most positive

TIMING DIAGRAMS

level = 1, most negative level =

ADDRESS ACCESS

Q)

Address
:t!'p~~ESS

'

r--

~
'-------'
50%

-1~I-

OUTPUT

--.t-

+1.5V

"'-

Address inputs are set in a de state

To select 1 of the 128 characters, apply the
appropriate binary code to the address inputs (Al-A7l.

ROW SELECT- ' "
INPUT

OUTPUT

-l~1
--.t+1.5V

~

These devices have the capability of displaying characters that descend below the
bottom line (such as lowercase letters j, y, g,
p and q). Internal circuitry effectively drops
the whole matrix for this type of character.
Any character can be programmed to occupy either of the 2 positions in a 7X16
matrix.

Row select inputs are set in a de state

226

MEMORY TIMING DEFINITIONS
tACC(A)

Row Select
To select 1 of the rows of the addressed
character to appear at the 7 output lines,
apply the appropriate binary code to the row
select inputs (RS1-RS4l.

Shifted Characters
ROW SELECT ACCESS

Output
For these devices, an output dot is defined
as a logic "1" level, and an output blank is
defined as a logic "0" level.

SmOl!tiCS

tACC(RS)

Address Access Time:
The time delay between a
change in the address inputs
and a corresponding change
at the output lines with all other inputs held stable, and with
the recommended load.
Row Select Access Time:
The time delay between a
change in the row select inputs
and the appearance of valid
information at the output lines,
with all other inputs held
stable.

DISPLAY FORMAT
Figure 1 shows the relationship between the
logic levels at the row select inputs and the
character row at the outputs. The 2609
allows the user to locate the basic 7X9 font
anywhere in 7X16 array. In addition, a shift-

2609-F,I,N

OBJECTIVE SPECIFICATION
ed font can be placed anywhere in the same
7X16 array. For example, the basic CN6571
font is established in rows R14-R6. All other
rows are automatically blanked. The shifted
font is established in rows R11-R3. Thus,
while anyone character is contained in a
7X9 array, the CN6571 requires a 7X12 array
on the CRT screen to contain both normal
and descending characters. Other uses of
the shift option may require as much as the
full 7X16 array, or as little as the basic 7X9
array.
The 2609 can be programmed to be scanned
either from bottom to top or from top to
bottom. This is achieved through the option
of assigning row numbers in ascending or
descending count, as long as both the basic
font and the shifted font are the same. For
example, an up counter will scan the
CN6571 from bottom to top.

FORMAT FOR PROGRAMMING GENERAL OPTIONS
ORGANIZATIONAL DATA
SIGNETICS 2609 MOS ROM
Customer ______________________________________________________
Customer part no. ______________________________~Rev. ----------Row number for top row of non-shifted characters _______________________
Row number for top row of shifted characters ___________________________
Countup

Count down

ROW SELECT INPUT CODE AND
SAMPLE CHARACTERS
FOR CN6571

DATA ENCODING SHEET
FORMAT
Character Number ___6_6__

TRUTH TABLE

CUSTOM PROGRAMMING
FOR 261)9

RS3

RS2

RS1

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

RO
R1
R2
R3

R

0
0
0
0

1
1
1
1

0
0
1
1

0
1
0
1

R4
R5
R6
R7

R "
R 7
R 8

1
1
1
1

0
0
0
0

0
0
1
1

0
1
0
1

R8
R9
R10
R11

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

R12
R13
R14
R15

By programming of a single photomask, the
customer may specify the content of this
memory. Encoding of the photomask is
done with the aid of a computer. Use of the
computer provides aquick and efficient way
to implement a custom bit pattern, while
reducing the cost of implementation.
Information on the general options of the
2609 should be submitted on an Organizational Data Form.
Programming of the memory content
should be transmitted to Signetics as completed data encoding sheets. The Data Encoding Sheet Format illustration details the
requirements for proper completion of the
data encoding sheets.
Three examples are shown to indicate proper character encoding. The following rules
apply:
1. Enter the character number in the space provided above each dot matrix. Address 0000000
is used for character number' 1, with other
character numbers following in the normal
binary progression.
2. Indicate the rows to be used in the space
provided to the left of each dot matrix. Note that
characters may be positioned in either of two
7X9 locations on a 7X16 matrix; however, only 2
positions are allowed per mask option. The
character for a given address may occupy only
1 of these positions
3. Column zero is added to the dot matrix on the
format sheet for use in indicating shifted characters. If a character is to be shifted, a dot
should be entered into the first row of the first
(zero) column (see the third example, jl.
4. The desired character should be entered in the
matrix, using only columns 81-87.

R I

OUTPUT

RS4

R

R
R

R

II

B1

B7

I )

( 1 1

•

(

8

I

L/
S-

9

~W)

t

I

J t

I
I
I

1 I

81

=

I

I

o

o
E
w

1 t
J t

--

83 84

87

...o
E

Non-Shifted Character

98

Characte r Number

R

I ()

R

:2-

(

R

:3

(
(

R5"

(

R

4

R ~
R '1

ROW
NO.
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
RO

:L'

R

R

X
I )

•

I

..

l

1 I

J l

'1'

'1

E

X}

I

l~

o

81

8384

87

Non-Shifted Character
~

•

Character Number __1
_ O_7_
]r

7'"

R
R
Ii""

•

1 I

1 l
J l

(

R '"
R

87

7

1 I.

R '¥

1 I

R .,

1 l

R

B1

4
S-

R

I"
II

•

Ii 12-

o

81

8384

87

Shifted Character

!ii!lDotiC!i

227

OBJECTIVE SPECIFICATION

2609-F,I,N

DATA ENCODING SHEET FOR 2609
Customer _ _ _ _ _ _ _ _ _ _ Customer Part No. _ _ _ _ _ _ _ Rev. _ _ Page _ _ _ of _ _ _ _ Pages

Character Number _ _ __

R

(J

R

R

(
(
(
(
(
(

)
)
)
)
)
)
)

R

(

R

(

R
R

R

R

o

B1

B3 B4

(

(

R

)

R

(

)

R

}

R

(

)

R

)

R

R

o

(

R

(

R

(

)

- ---- ..J

R
R

(

)

R

R

(

)

R

R

R

o

R

R
R

R

)

R

R

)

R

R

)

R

R

R
R

(

R

R

(
(
(

R

(

R

o

B1

)
)

R

)
)
)

R

R

-.-- ----~
91

F.I

(

R

R

)

R

R

}

R

(

R

)

R

B3 B4

Smnotics

B7

(J

R

»

><

B3 B4

Character Number _ _ __

>< ><

B1

B7

R

(
(
(
(
(

o

--

)

o

'Y'

(
(

B384

R

B7

B3 B4

R

B7

B1

Characte r N um ber

X

(
(
(

R

B3 B4

R

o

y
(

(X

R

B1

)
}
)
)

B7

Character Number _ _ __

R

R

U

o

B7

(
(
(

R

)

R

(

)

R

R

R

)

)

)

(

R

()

)

R

R

R

R

R

R
R

R

)

)

R

lJ

)

Character Number _ _ __

U

R

R

B3 B4

B3 B4

R

R

R
R

B1

B1

Charact er N um ber

-

B7

B3B4

..;;.

u(

R
OR

B1

Character Number _ _ __

(
(
(
(
(

R

-

(

o

B7

B3 B4

)
)
)
)
)
)
)

R

B7

CY' . . . . '" ,... .....................

o

B1

Character Number _ _ __

Charact er N um ber

228

R

B7

R

R

-(

R

R

-

l 1

R

R

R

R

R

(
(
(
(

B3 B4

R

(

R

LB1

}

(

)
)
)
)
)
)
)

o

0-(

R

lJ

R

R

R

R

R

R

)
)
)

Character Number _ _ __

R

Character Number _ _ __

Character Number _ _ __

R

B7

R

(

o

B1

B3B4

B7

OBJECTIVE SPECIFICATION

2609-F.I.N

USASCII CHARACTER GENERATOR CODE
The CN6571 has been programmed with the characters shown. No attempt has
been made on this figure to indicate columns and rows actually used on the
display for each character.
AODRESS(A)

7

•

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

I
1
I
I
I
I
1
I

0
0
0
0

1
I
1
I

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

5
0
0
0
0
0
0
0
0

4
0
0
0
0
0
0
0
0

3
0
0
0
0

2
0
0
1

1
1
1
1

0
0
1

0
0
0
0
0
0
0
0

1
1
1
1

1

1

1
0
1
0
1
0
1

0

DISPLAYED
CHARAqrER

P
"Y

,.
~

0
0
0
0

0
0

0

1
1

0

A

1

~

1
1
1
1

0
0

0

v

1
1
1

1

{

1
1

0

0

1

7r

1
1
1
1

0
0
0
0

0
0
0
0

0
0

0

P

1

a

1
1

0

T

1

v

1
1
1
1

0
0
0
0

1
1
1
1

0
0

0



1

X

1
1

0

I
1
1
I

I
1
1
1

0
0
0
0

0
0

0

1
I

0

I
I
I
1

I
I
I
1

I
1
I
1

0
0

0

I

I

-;-

1
1

0

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

Blank

-

1

!

1
I

0

I
1
1
1

0
0

0

•$

I

%

1
1

0

&

1
1
1
I

0
0
0
0

0
0

0

1
1

0

.

I

+

1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
I
I

I
1
1
I

0
0

0

I
I

0
1

I

1
1
1
I

1
1
1
1

0
0
0
0

0
0

0

;r

I

1
1

0

1
2

1

3

I
I
1
1

1
1
1
1

0
0
0
0
0
0
0
0

1
1
I
I

0
0

0

4

1

5

1
1

0
1

6
7

1
1
1
I

1
1
1
1

1
1
1
1

0
0
0
0

0
0

0

8

I

1
1

0
I

9
:
;

I
1
I
I

1
1
I
1

1
1
I
1

1
I
1
1

0
0

0

<

1

=

I
I

0

>

I

?

1
1

I

1

yes
yes

1
I
I
I

6

1

I

7

a

1

1

ADDRESS (A)
SHI,-rED

1
1
I
1

yes

8

,

1
1
1
I

"

'"'"

yes

I
1
1
I

0

-:£

I
I

I

(
)

-

yes

SjgnDtics

1
0

1
1

0

I
I
1
1

0
0

o.

1
1

0

I
I
I
1

0
0
0
0

0
0

0

1
1

0

J

I

K

1
1
I
1

I
1
1
1

0
0

0

L
M

1
1

0

N

I

0
0
0
0

0
0

0
1

Q

1
1

0

R

I

S

1
1
I
1

0
0
0
0
0
0
0
0

0
P

1
1
I
I

0
0

0

1
1

0
1

T
U
V
W

1
I
I
1

1
1
1
1

0
0
0
0

0
0

0

X

1

Y

1
I

0

Z

1
1
I
I

I
I
1
1

1
I
1
1

0
0

0

I
1

0

0
0
0
0

0
0
0
0

0
0

0
I

a

I
1

0

b

1

c

0
0
0
0

1
1
1
1

0
0

0

I
I

0

d
e
f

I

9

I
I
1
1

0
0
0
0

0
0

0

h
i

I
1

0

j

1

k

I
1
1
1

I
I
I
I

0
0

0

I

I

m

I
I

0

n

I

0

0
0
0
0

0
0

0
I

p
q

I
I

0

r

I

s

I
I
I
1

0
0

0

I

1

I
1

0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

I
I
I
1
1

1

B
C
0
E
F
G
H
I

I
1
I
I

1
1
1
1

1
1
1
1

I
I
I
1

I
I
I
I

I
1
1
1

1
I
I
I

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
I

1
I
I
I

1
1
I
1

I
I
I
I
1
1
I
I

I
I
I
I

I
I
I
I

0
0
0
0
0
0
0
0

1

u
v
w

I
I
1
1

1
1
I
1

1
1
1
1

0
0
0
0

0
0

0

x

I

Y

1
1

0

I
I
I
I

I
1
I
I

I
I
1
1

I
I
1
1

1
1
1
I

0
0

0

1

I
1

0

I
I
I
1

I

SHIFTED

@
A

I
1
1
I

1
1
I
I

..;

0
0
0
0
0
0
0
0

2
0
0

4

I
I
1
I

1
I
1
1

yes

DISPLAYED
CHARACTER

3
0
0
0
0

5

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
I

yes

8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

=
o
e...

1
1
1

1

1

1

I
I

1

--

e

C
E

yes

yes

yes
yes

yes

}
Solid

229

OBJECTIVE SPECIFICATION

2609-F,I,N

CARD FORMAT HEADER CARDS

CHARACTER SET UP CARD

Card #6

IDENTIFICATION CARDS
Column 8, 9
Custom designation "CN"

Column 10, 11, 12, 13,
Custom number (assigned
by Signetics)
Column 26-80
Customer identification

Column 2-6
Basic part type

ACf"'!f I"ff'lDPlfS PflI

'" , "
,

'III

Columns
1

10 & 11

13-18
19 & 20

1~21f-l

"

"
" " " " ' " 00""" II" 0' II 0' II" I 01111111 0111111111111111111111 00' 01111I11111
1 r , I S I I I 1101,,: 11141S1IUIIIIIDZllZZJIU!5I1!JZlZI.JI.,nUI.I7 • • • ~CZ04l • • " • • • II.U" . . . . . . . . aa . . . . I1 • • "nnJlfUUU'"J1.

22-27
28 & 29

111111111" 111111111111111111111111111111111111111111111111111111' 11111111111111

22' 2 22 2 2 2 2 2 2 2 22 22 22 2 2 2 2 i22 2 22 22!! 2 2 2 2' 2 2 22!! !!II!! 22 2222222 22 2 22!! 2222 2 2!!Z Z2 ZZZ

Person responsible for reviewing Signetics
computer generated truth table
~)Hi.

~~'.n·CIf·I:TF.

"

111111
, , , ,

;:~rT.

When "ON" is punched this
adds -1 to the number of top
row of character to get the
second row; third rowis-2; etc.

,.(:;.

II"
II'
"

~ ~ ~~ ~ ~ ~ ~ ~ ,~,~ ,~ t~ ,~ I~:~ ~,~ ,~! ~ ~ ~1~ l~' ~ ~ {~,~! ~ 1~~! ~ R~ l~!~'~ n,~,~ ~,~ ~(~ ~\~ ~~ ~s~ ~~ ~ ~ !~, ~~,~(O\~I,D, ~~ ~~ ~l ~l~' ~ ~~ ~, ~,!
11111111111111111il111111111111111111111111111111illlJ111111111111111111111111"11
2 2 2 2 2 2 2 212 2 2 2 2 2 2 2 2 2 ~ 1 2 2 2 ? 2 2 2 2 2 1 2 2 2 2 2 2 2 ~ 2 ~ 2 2 2 2 l 2 2 2 2 ? Z2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Streetad;d~re~s~s~

..:

::'~(o(l

____________________________________________~

~!lNIING

, "'

II

~ ~ ~ ~ ~ ~ ~ ~ ~ ,~ ,~ ~1 ~ ~ ,~ ~ ~,~ ~! ~ ~ ~1~ 1~ 1~ ~ I~'O,!~ ~l~!! ~l~!)~!~ e.~ ~~! ~!! ~~ ~ ~ ~j~!\~I~!~!~' ~1~!~!~ ~~ ~I ~ ~'~l ~ ~ ~I ~r ~ ~!~
11111111111111111111111111111111111111111111111111111111111111111111111111' 11111

2222 2 2 2 2 2 2 22 2 21 2 2 n 2 l2 2 2 2 2222 2 2222 22 22 2 2 2 Z22 2 2 2 2 22 2 Z22 22 22 2 2 21212 2 2 2 n 2 2 2l 2 22 2 22

State

City

Zip

.: ,?I't!t''r''..'PI F.

,

riJI1Fn:'f"T~ Q4(1~~

"""

30-78
79 & 80

II

"' ""
~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~,~,~ I~'~!~'~ ~ Ju~ ~ ~ ~~i~! ~ ~l ~~. ~! ~.l~ ~ ~ ~l ~f~. ~ ~l~~ ~\~ ~,~.~R ~ ~ .~~ ~I~I ~ ~ ~~, ~1 ~j~' ~'~':1~'~9 ~a ~ ~I ~l ~'~I ~i ~, ~l~'~"
J.

,0,

11111111111111111111111111111111111111111111111111111111111111111111111111111111

This format identifies characters by numerical sequence beginning with 001 (the first
character of the set) and ending with 128
(the last character of the setL Address
0000000 is used for character #1, with other
characters following in normal binary progression with Al the LSB and A7 the MSB.
Columns
1-3

22'22222222 £ 2 2 2 2 2 Z2 2 2 2 2 2'2 2 2 2222? 2 2 22 2 2 2 2 2 2 2 2 22 2 2 2 ~ 2 2 2 2 1 2 2 2 22 2 L 2 2 i 2 ~ I. 1 ? 2 2 2 Z2 , 2 2 1 2
Company~n~a~m~e~
~.

,

p~Nr,[./'1

____________________________________________,

f>1f1'TPlf'? H·(.

"

II

'"

""'111
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~,~,~ ,~ !~, ,~ ,~ ~~~ ~1~~' ~ ~I~'~ ~!!~ ~1~1! ~!~! ~!~ ~,Jl~l~jOI ~ ~ ~!! ~ ~1 ~J! ~I~ e!! ~ ~, ~2 ~l~ !~I ~,!~, ~I ~, ~1 ~l~' ~\ ~I ~1~' ~~

4
5
6
7-13

11111111111111111111111111111111111111111111111111111111111111111111111111111111

22222222222222221222222222222222222122222222222222222222222222222222222222222222

CHARACTER SET UP CARD

14
15-21

/rl

I

~

=1.1 Sf.' FT-l1 C[!l'tJT=f'

'" .

"'

,

,

"'~ ~ ~ ~ ~ ~ ~ ~ ~ ,~ ,~ ,~~ ,~ ,~ ,~~!'~!~~!"t~!l~!!!~, !l~ ~!!~ !!!~ !I~I~~IOS~!!!~ !!! ~!I~I~!!~~Z~I!!! ~,~!! ~ ~ ~~I~!~ ~ ~~,!
11111111111111111111111111111111111111111' 1111111111111111111111111' 1,11111' 1111

222122 Z2 2 2 2 212 2 2 2 2 22222222222222222 Z222 22 2 Z22 22 2 22 2 22 2 2 2 2 2 Z2 22 2 Z2 2 2 2 2 2 2 2 n 22 2 2 22
313 3 J 3l1] 3 3 3 3 3 3313 33 313 3 313 3 3 3333 3 313 3313 33 3 3 3 3 33] 3 3 3 33333 J 3 3 3 33 33 J 3 3 333 3 3 33333 3
4444444444144444444444 U 4 4 4,4 4 4 4 H 4 44 4 4 4 4.444444444 4 ~4 4 4 4 4 4 4 44 44 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

1515 ~ ~ 5 5 5 5 5 5 5 55 5 S5 55 5 5 5 515 5 515.5 5 5 555555 ! 5 55 5 5 5 S5555555555555555555555 S5 5 5 5 5 5 55 5 5
61 G6 6flGI B6 6 5 SGI6I6 6 t 616 6 GIS 6 66 6 6 666 G6 G66 66 GG6G£ 6 6 GGS6 56 6 GG" G66 66 66 66 6 6 5 6 &6 6 66 6
11'177717777177117711111171117171111111717111117111111111111111111111111111111111
a B~ BI BS318 a a alB R81 ~ 3 8 B8 F UBIB 8 DBB8 8 BB8 H8 8 8 B8 9 a II B8 B8 8 8 Be 88 8 8 B8 8 8 8 B8 B88 8 8 8118 8 8 8 88 8 B
9 S 9 ~ 919 9 ~ 9 9 9 9 ql9 9 9 9 9 9 9 ~ 9 9 9 9 911 9 9 9 g 9 9 g!l ~ ~ 9 9 9 9 9 9 S 9.9 9 9 9 9' 9 9 9 9 9 9 9 9 9 9 9 9 9 9 ~ 9 9 9 9 g ~ 9 9 9 9 g 9
1• 3, >" , , !

230

";.'~~"

i6:1U .llil'

Leave blank
Enter truth table number

CHARACTER CARDS

PC ... !'

,,"

,

Type in -, NONSHIFT =
Enter decimal number that
corresponds to TOP row of the
nonshifted characters
Type in -, SHIFT =
Enter decimal number that
corresponds to TOP row of
shifted characters
Type in -, COUNT =
These columns are used to
identify the direction of the
numerical count for the subsequent row numbers.

1:'1:1;'.'<11!5Z1II1IZ1l1l1:1II::.llHilr3lIUIIII4Z4UH511IUHH05ISIU~lliii515l1in'lIaal4i5I1i1.'llOlInfI141111111l1ftll
,~

NOTES
A. An entered dot corresponds to a high voltage output
B.. A complete card deck consists of 5 header cards, 1 set up card and 128 character cards

!ifgDotiC!i

231

8192 BIf SlATlG MnS ROM (102418)

2607
2607-F.I.N

FEATURES
•
•
•
•
•
•
•
•
•
•

•

•

•

PIN DESIGNATION

Static operation-no clocks
Access time: 450ns max
Single 5V power supply
TTL compatible inputs and outputs
Power dissipation: 525mW
Tri-state outputs
Mask programmable chip select for easy
word expansion
N-channel silicon gate technology
Standard 24-pin package
Designed for system applications requiring high performance, large bit storage
and simple interfacing
2 chip selects (CS1, negative true;
CS 2/CS 2, either negative true or positive
true at mask level)
Pin for pin compatible with Intel 2708
electrically programmed erasable ROM
and Intel 2308/8308 ROM, except only
requiring +5V supply
All inputs capacitive and do not sink or
source current

PIN CONFIGURATION

PIN NO.

FUNCTION

ArrAs
0,-08
CS,. CS2
NC

Address inputs
Data outputs
Chip select inputs
No connect

Vee
A.
A,

He

CS 1
He
CS,/CS 2

o.
0,
0,

0,
0,

Vss

0,

BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS1
PARAMETER

F,I,N PACKAGE

RATING

UNIT
DATA OUT 8

DATA OUT 1

TA
TSTG

Temperature range
Operating
Storage
All input. output. and supply voltages
with respect to ground pin

o to 70
-65 to +150
-0.5 to +7

°C

V

OUTPUT
BUFFERS

8192 BIT
ROM MATRIX
(1024X8)

232

S!!Inl!tiCS

2607-F,I,N
TA = O·C to 70·C, Vee = 5V ± 5%, Vss = OV
unless otherwise specified.

DC ELECTRICAL CHARACTERISTICS

LIMITS

TEST CONDITIONS

PARAMETER

Min

Typ2

Max

VIL
VIH

Input voltage
Low
High

VOL
VOHI

Output voltage
Low
High

ILl

Input load current

VIN = 0 to 5.25V

10

ILO

Output feakage current

Chip deselected

10

lee
Po

Supply current

V
0.65
Vee+1.0

2.2

V
0.45

IOL= 2mA
IOH = 1mA

2.4

Power dissipation
Capacitance

JIoA
p.A

80

100

mA

400

525

mW
pF

TA = 25°C, f = 1MHz, Vee and all
other pins tied to Vss

Input
Output

CIN
COUT

UNIT

7.5
15

=
o

AC ELECTRICAL CHARACTERISTICSTA = O·C to 70·C, Vee = 5V ± 5%, VSS = OV
unless otherwise specified, Output load = 1 TTL gate,
Input pulse levels = .65V to 2.2V, Input pulse rise and fall times = 20ns,
Timing measurement reference level: VIH = 2.0V, VOH = 0.8V, VIL = VOL
PARAMETER

TO

LIMITS

FROM
Min

UNIT

Typ

Max

Delay time
tAee
teol
tC02
tOF

Float time

ns
Output
Output
Output

Address
Chip select 1
Chip select 2

200
85
85

450
160
160

Output data

Chip deselect

70

160

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2. Typical values for TA = 25'e and typical supply voltages.

TIMING DIAGRAM
\-----ACC

ADDRESS

Ao

A9

-----I

------~~-------------+--------_ _ _ _.;T",;. _ _ _ _ _ _ _ _ _ _ _
IC01

cs,

--------~r_----------~--~~
1----IC02 - - - . j
DATA

0,

07

[===== ==D:~N::= === ==~~~-D-AT-A-V-AL-ID-+~~~~ID
ssgnotics

E
1M
E
~

ns

o
E

26n}

8192 BIT STATIC MOS ROM (102418)

2607-F,I,N

CARD FORMAT
IDENTIFICATION CARDS
Column 10, 11, 12,13,
Column 8, 9
Custom number (aSSigned
Custom designation UCN"\bY SjignetiCS)

Basic part type

Column 15, 16, 17, 18, 19
"Coded"

Column 22
Chip select code
(CS2)

~r--""---!.---.!---':::--""::="---~==------------'"
(" 26 fJ7l/CN

CODfIt

pCf'lE I'4[M[lPIES

p~

I

I III

III I
II
I I III

I I

I

I

13~216-1

000 nI 0 010 0 0 DO 0 0 00 0 0 0 00 0 0 0 0 0 0a0 0 0 0 0 00 010 010 00 oao&oo. 1I00Itlili IIIIIIOD 11111'"

It.

I I I ' 5 I 11 '101111131""illlI1!:t!1lllI1l1$3UzrlU0313l1311lHI11 • • • 41t1'I~G." • • • 51RUM5tllViI • • 1II1aM • • Il • • "nl21lf4nllrrll".

1111 , 11111 11 , 11 111 , 11111 '1111 I , II 1 111 1111111111'111111111111111111111111111 , 1111

111" 22222222222I 222222222 2211212 2222112 22222212 I 12 I I 2I 11 11 11 11 11 111111 11111 111 1

Person responsible for reviewing Signetics
computer generated truth table
.. In', 5-p.n·(Ir-ETF'. Fi=Tr. ,'(r.:,

II

111111

I
I

I

I

II
I

III

II
I I

~ ~ ~!~ ~ ~ ~ ~ ~ ,~ ,~ ~ ~ 1~ IDS ~ ~ l~ ~a ~ ~ ~ ~ R~ ~ ~ ~ ~ ~ ~1 ~l~ !5~'~ ~ J~ ~ ~ f}l~ ~,~ ~I~'~' ~,~ ~ ~I ~sDs ~~ ~~! ~~ ~I~l ~~5 ~i~1 !"IOj ~o ~ ~1 ~I ~,~ ~i ~I ~I ~9 ~
11111111111111111111111111111111111111111111111111111111111111111111111111111111

22222221112122222121212 1 ~ 2 2 2 1 2 1 222221222'- 2 2 2 12 12 1 2? 2 2 12 2 2 2 2 2 2 2 2 22222222221212121

Street add ress
.,:- ::':'5['(1

I

~JINHt1G

P[HI!

1111
II
I I II

~ ~ ~ ~ ~~ ~ ~ ~ ~ l~ ,°1 ,0, ~ ,Ol'~'~'~'~ ~1~ 101~ ~ R~IO'!~! ~ ~~! ~\~'~r ~~ ~~~ 4~ ~ ~"~j~'~! ~ ~ ~ ;OI\~~ \~ ~ ~,~ \~ .Ol~!' ~~ ~~ ~~~,~, ~ ~ ~,~ ~,~ ~,~. ~I~I
11 111 111111111 ) 1111111111111111 111111111111111111111111111111 1111 1111 11111111 J 11

222 2 122 2 12 2 2 2 n 2 III 22 2 2 2 2 2 2 11 22 2 12 22 22 22 22 2 111 2 111 n 11 2 2 212 2 12 22 2 2 22222222222 2 1 2

City

State

Zip

~--------------------------------------~
, ::1.'~j~IY~I~'l r. CPt IFrFO·t;I~ Q.:!C':~'f

111111
II

I

II
III

~ ~ ~ ~ ~ ~ ~~ ~ 1~ ,~ ~ 1~ ,~ ,~ I~'~ R~l~ ~ R:J~' ~\I~! ~'~ ~ ~ ~'~J ~ ~ ~ ~ ~ ~3 ~~, ~ f) ~.~ ~ fr f.~ ~o~ ~ :0; ~'i~ R~ ~I' ~;'~, ~ ~1~l ~'~<~b~! ~g ~G ~, ~1~] ~, ,°5 ~i ~l ~3~! ~J
11111111111111111 11111111 111 i 11111111 i 111111 III r 111111 1111 11111111111111111 11 111

221121222122112222221222111212 i 2 i 12 2 2 i i 2 i 2 2 2 2 2 2 21 2 2 2 2 1 212 22 2 2 1 2 1 2 2 ~ 7. 2 '( 2 2 11 2 2 2 2 2 1

Company name
.'

PptHi(~f'1

fo1frTP I E~ I t~( •

III
111111
I I II I III
I
000 n0 0 0 0 noD 000001 0 0 °0000 °0 0 0 DODO °0 fl °0 0 0 0 00000 °0 0 0 0 0 0 0 0 0 °0 0 0 0 °0 0 0 0 0 0 0 0 0 °°0 0 0 0 0 0 0 0
1 1 1 , S ! 1 6 9 lG II 111]" illS" Ii II 1a 11121) II 2\ IS 2111 19 JG 11 31)j 3;Jllilllll9 '001 '1') U'~ 'i.1 'I1511nIl511,rll>HHIII'H-ITt.

II

:f;'.~r::-Ir-rfF,

I

111111
I I I I

I

'll 2 l21l?1

n

.~~~T,

II
III

.(~.

II
I I

1212 '2 21212122 '( 2 2 222 221222 2 2, '2;' 21211.1212? '2 lll? 21? 21111? 221

~ '2

2 21/21212

'2

Street address
r---------------------------------------~
. :. ::'~N' PlhI HK~ F'[i-l51~EIWIHH''''I!U'111I

rlllU lS11 11 II I!1G

111111111111111111111 11111111111111111111111111111111111111111111111111111111111

! Zl2 2 2 2 2 2 2 2 2 2 22 22 2 2 2 2 22 2 2 2 2 2 2 2 2 2 2 2 222222222221222222 Z2 2 2 Z2 Z2 2 2 2 ZZ 2 2 2 ZZZZ1 ZZ2 ZZZZ

Company name
_ P':'I·lI,nt

~tf/'"'['P

6-9
10
11-14

Decimal equivalent of first
data word location
Example: 0124
Note: Leading zeros must be
used for addresses from
0000 to 0999
Dash (-) to separate numbers
Address of last word on card
Blank
First data word (04, 03, 02,
01)

15
16-19
Etc. thru 71
72-80

Blank
Second data word
Reserved for comments
(these columns are ignored
by the computer)

Up to twelve (12) data words can be coded
on one card. Less than 12 may be used as
long as the first and last addresses are given
in columns 1-9.

IE.'" HIe.

III
111111
11111111
I
0600000060 Q0 0 0 0 01 0 0 0 0 0 0 0 00 0 0 aDO 0 00 0 0 0 0 60 0 0 0 0 0 0 n 0 0 00 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0
~
~ 'j'; 'I' '1"1' '1"1' L; 'I' '\"1"I'1'11'~"I';"{'17~'I' i'I"I'll'~'I"I"I'ili' ;1;1;';'i'i'i7ii'iiliiiiiiii')'i'iiii'ii'ltl'

;;;i ;;;

;l;';"I"ti' ;';'j

21222 Z2 2 2 222222212222222222222 Z2 2 2 2 2 2 2 2 2 2 2 2 212 2222222222 Z2 2 2 2 2 2 2 2 2 22222222222222

EXAMPLE

1111011 0 0 01111 0111 0 011 01 011 0 0 01 011 01 01 0 01 0 01 01 0 0 0 0 0111 0 011 0 0 01 01 0 01 0 0 0
1234;; J I 9101111lJ14151iHlI192021112lZ42526ZlZlZ93031lHlJ.4l!i!6lJJ8.l94011(24HUS(64nUHO,152535U510151585I&061626lU6SI6U6869iJ

11111 I 1111 I III I I 11111 III I I 111111111 11111 111111111111 111111111111111111

1111111111111111111111111111111111111111111111211111112 211111111121111
3333 3J 3 J 3 3 3 3333333333333333333333333333333333333333333333333333 3 3 3 3 3 J J

44444444444444444444444444444444444444444444444444444444444444444444444
5555555555555555555555555555555555555555555555555555555555555555555555
666666" 6 E6 6666666666666666 S 6 6 6 6 6 6 6 6 6 6 6.666666666666666666.666.666656 G
77 7177 111 77 71 711 71177 77 71771 7111177 77 71111 7717111 711 77177 7177 1711 71 711
HH86008HHHHBHHHHHHHHHHHHHOHHHHHH80HH8H838H8H08888888H8UB838688B8886880
99999S9999999999999999999999999999999999999999999999999999999999199"99
1 1 J 4 5;) I 6 9

1~;1 i

'151illIS:9101122212'15'6112nglOll31J3'~J •

.i03ln;gi041 414.14"5('4!<1;"U5i >l\JS4555")5amlJSI61i.lEH>!Sfi6HHO

S!!)DOliCS

241

=

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E

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E

2600-F,I,N .2600-1 - F,I,N

DESCRIPTION

FEATURES

The 2600 outputs appear and remain in a
steady state condition until a new address is
read. The 16,384 bits are organized as 2048
addresses with 8 output lines. Full address
decoding is performed on chip. The 2600's
size enhances its usage in any high density,
fixed memory application such as logic
function generation or microprogramming.
Programming of the device is accomplished
via the use of one custom mask during
device fabrication.

• Completely static
• Utilizes MOS n-channel si-gate
technology
• Clocked or unclocked operation
• Access time: 300/550ns max
• Single +5V power supply
• 2 output enable controls allow:
Wire OR'O three-state outputs for expanded memories
2048X8 or 4096X4 organization
• All inputs and outputs directly TTL
compatible
• Pin compatible with EA4600 and EA4900

PIN CONFIGURATION
F,I,N PACKAGE

BLOCK DIAGRAM

Vee

.,

AR

OE,

13
23

A,

0,

"g~~

...

~Oz

~::Eo

II,

ffi

.... 1;;
;it;

12

A,

ZW
_IX

11
II,

...
A..

22

0
W

A,

A,

II,

0,

10

••

21

.,

THRU
A..

20
2048X8
MEMORY MATRIX

,.

DeCODE

•

,.
GND

18
17

,.

0,
0,

o.
0,

0.
0,

0.,

ABSOLUTE MAXIMUM RATINGS1
PARAMETER
TA
TSTG
Po

242

Temperature range
Operating
Storage
Power dissipation
Voltages on all inputs and
supply pins

Si!lDlltms

RATING

o to 70
-65 to +150
Hermetic 1.25
-0.5 to +7.0

UNIT

°C
W
V

2600:2600 1

16,384 BII SIATIC MOS ROM (204BI8)

2600-F,I,N .2600-1 - F,I,N

ELECTRICAL DRIVE REQUIREMENTS O°C ~ TA ~ HO°C, 4.75V

~ Vee ~ 5.25V

LIMITS

TEST CONDITIONS2,3

PARAMETER

Min
Address read, address input and
output enable

Input voltage

V
-0.5
2.2

Low
High

VIL
VIH

TTL interlace
10 = 1.6mA
10 = -100!-'A

VOL
VOH

Output voltage
Low data
High data

III

Input leakage current

Icc

Supply current

CIN
CAR
COUT

Capacitance
Address input
AR input
Output

0.8
Vee
V
0.2
3.5

2.4

Test pin at V = Vee max, Other
pins at ground
Vee = Vee max 25°C

0.4
Vee
10

!-,A

80

115

mA

5
5
7

7.5
7.5
10

OV bias, 1= 1MHz

TIMING SPECIFICATIONS O°C
PARAMETER

UNIT
Max

Typ

pF

~ TA ~ HO°C, 4.75V ~ Vee ~ 5.25V

TO

TEST
CONDITIONS2,3

FROM

CLOCKED MODE
Cycle time
Teye
Pulse width
Address read
ARpw

2600
Min

Typ

2600-1
Mllx

Min

Typ

UNIT
Max
ns
ns

300

500
300

150

75

450
140

100
150

30
70

100

50

0

200
30

50
100

0
50

ns

Delay time
Output
Output disturb

TAee
TARO

Address
Address read

Address lead time
TLo
Address lag time
TLG
UNCLOCKED MODE
Cycle time
Teye

Standard

550

500

300
ns
ns
ns
ns

300

Delay time
tAee
TO~~

OUTPUT ENABLE
(CLOCKED OR
UNCLOCKED MODE)
Delay time
Teo
Too

Output
Output disturb

Address

Output on
Output off

Output enable
Output enable

0

450
50

500

100
150

300
400

0

200
30

300

(50)
100

150
200

ns

NOTES
1. Stresses more severe than those listed under Absolute MaximUm Ratings may cause
permanent damage to the device. This ,is a stress rating only and operation of the
device at any condition above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability,
2. All voltages are referenced to Vss. Positive current flows into the referenced pin.

3. Output load

= 50pF plus 1 standard TTL input.

Si!lDOlms

243

=

o

E
w
E

...o
E

2600-F.I.N .2600-1 - F.I.N

TIMING DIAGRAMS

DEFINITIONS
Clocked Mode

CLOCKED MODE

ADDRESS
READ

ADDRESS
INPUTS

INVALID
VI:;.L_ _ _ _J

l.",,~~~,"4

"""",,""''''''''''...,(J '-______
INVALID

'-_ _....II

VOH

DATA
OUTPUTS VO~L,--_ _ _ _ _ _ _ _ _ _ _ _ _ _-,

1. Tcyc. Cycle Time is the time between
successive address read pulses.
2. TLD. Address Lead Time is the minimum
time required for the address to be valid
prior to the falling edge of the AR pulse.
3. TLG. Address Lag Time is the minimum
amount of the time required for the address to remain valid after the falling edge
of the AR pulse.
4. TARO. Address Read to Output Disturb
Delay is the minimum time between the
AR pulse and the first output transition
when a new address is present.

Unclocked Mode
UNCLOCKED MODE (AR

1. TCyc. Cycle Time is the time between
application of successive addresses.
2. T ACC. Address to Output Delay Time is
the maximum time between a new valid
address and the corresponding valid output.
3. TODD. Output Disturb Delay is the minimum time between the address change
and the first output transition.

VCC)

=

VIH:...._ _ _...
ADDRESS
INPUTS
VIL

ADDRESS Y
VALID

ADDRESS X
VALID

ADDRESS Z

VALID

·1

~--------TACC--~~~I
VOH"-_ _ _ _ _ _...

DATA
OUTPUT

OUTPUT

OUTPUT

VO:..L_ _
'N_V_AL_'D
_ _J

,,~. .~~ , -_ _
'N_VA_L_'D
_ _-, ,,~:;..:.."~

OUTPUT ENABLE (CLOCKED OR UNCLOCKED MODE)

OUTPUT

ENABLE

DATA

_VI : . ; . L - - - -- ' ' _ _
TCO

~~~PUT

1

.,..,"7"t.

HIGH IMPEDANCE _.,.,..,..............

OUTPUT

HIGH IMPEDANCE

OUTPUTS VOL

244

9i!1DotiC9

OUTPUT
VALID

Output Enable
1. Tco. Output Enable to Output ON Delay
Time is the minimum time required for
the output. in high impedance state. to
become valid after rising edge of the
output enable pulse.
2. Too. Output Enable to Output ON Delay
Time is the minimum time required for
the output to become high impedance
after the falling edge of the output enable
pulse.

2600-F,I,N .2600-1 - F,I,N

CARD FORMAT

CUSTOM PATTERN PRO·
GRAMMING INSTRUCTIONS

IDENTIFICATION CARDS

iom" ""'' '"' ,

Column 8, 9

Column 26-80

C"~~ '~""'t;o" "CN"

Column 10, 11, 12, 13,
Custom number (assigned
Signetics)

Basic part type

JY

L 2E ('(II

ACI"r "'E""'PPIES Pd'.! 136217-1

/(lJ

I

II I I
II
I I III

I
I

I I

I

~ ~ ~ ~" ~, ~ 1~ I~ R1~ ,~ i~ Rl~ I~ 1~1~1~!~ l~ ~ 1~ ~1~! ~!3~ el~! l~ l~~!! 2! ~I~'~j~!~ ~~~!I~!~ ~~!~ !!!~!!!~!~!!~~ ~ ~~I ~5~1 ~,~~!

1111 111111 I 11111111111 I 111111 11 1 11111111111111 111 '111111 111 1111111 J 1111111111111

22122122221212122 2 122 2 l2 2 2 2 22 2 1212 1 2 1122 2 21 212122 1 2 Z21 zz 2 2 Z22 Z2 22 2 2 2 Z22 2 212 22 2 Z2

Person responsible for reviewing Signetics
computer generated truth table
,:.THi,

I I

::~'.

Et'I..: I t,[[F'.

111111

I
I

I

I

I

I

F~

r:r .

...

II

~'C;::-

•

I I
I I

on 0110 0 010 0 DODD 0000100 0 Don 000 00 000000 0 0 00 noon 00 0 0 000000000000000 0 000·0 0 0000000000
1 , l ' \ f ' !,'O" 111)"'\"""191011,11)1'1\1'1111<130l1 !11lJOllli:<13!lHO1n1['PIES' If'lC.

I

I I
I
II
I I II I III

I II
I

~ ~ ~ ~ ~ ~ ~ ~ ~ I~'~ I~ l~ I~'~ I~ ~ L~ l~ 1~1~ 1~1~ 1~ R1~ 1~ 2~1~1~l~ l~ l~ 3~ ~l~l~'~l~ ~~.~ .~.~ jOU~ ~~ ~'~'~I~'~ ,~ 5~~ ~~ I~~ ~~6~'~ &~IOIiO'~I~I~I~ fo ~ ~ !l~ ~ ~ ~ ~ ~n~
1111111111111!111111111111111111111111111111111'111111111111111111111111111111111

The required punching format is described
below. All addresses must be included with
their outputs defined. That is, no assumptions are made regarding the bit configuration of undefined outputs. Therefore the
customer must submit cards defining the
entire ROM contents, even though part or
portions of the ROM may be unused (zeros).

Data Card Format
for Custom ROMs
Each card is to be punched as follows. Note
that for the Signetics 2600, a 3-digit octal
number is used for representing the 8 ROM
outputs .
Column
1-4
Punch. a 4-digit octal number representing the input address for
the first of the 16 output words
appearing on this card. (This is the
initial address)
5-7
Punch a 3-digit octal number representing the outputs for the
initial input address.
8-10
Punch a 3-digit octal number representing the outputs for the
initial input address +1.
11-13
Punch a 3-digit octal number representing the outputs for the
initial input address +2.

50-52

121212111211111111111211221212112121212211212221212 2 212 2 2 2 21112 212111212 2 2121212

69-80

Punch a 3-digit octal number representing the outputs for the
initial input address +15.
The unique number assigned to
this ROM pattern by Signetics
must be punched in this field enclosed by blank spaces. This
number can be obtained by contacting your local Signetics salesman, representative, or the marketing department at the factory
directly.

Each card, therefore, carries (in octaD the
initial input address for the 16 output words
contained on that card, the 16 output words
themselves (in octaD and the unique ROM
number. The card must be provided for all
possible sequential address locations (in
blocks of 16>' A 2048 word ROM, therefore,
requires 128 cards, with all 16 output words
defined on each card.

5egOOtiC5

245

r;

o
E
w

E

....o
E

·2600-1

16,384-811 STATIC ROM-ADVANTAGES OVER THE EA 4600
2600-1 MEMORY APPLICATION MEMO

GENERAL
The Signetics 2600-1 is a high speed 16K
MOS ROM that utilizes the n-channel silicon gate technology. The maximum access
and cycle time is 300ns. The memory is
organized in a 2048X8 configuration at the
outputs, however, two separate output enable signals allow the memory to also operate as a 4096X4 organization, where required.
The TTL compatibility of all inputs and
outputs including the power requirements
of only a single +5V supply, coupled with
Signetics' process and design, results in a
denser, more economical and more reliable
part at the system level, where it counts.
Figure 1 illustrates the 2600-1 block diagram, while Figure 2 illustrates the pin configuration.

2600-1 BLOCK DIAGRAM

OE,

AR
A,

13
2

A,

3

A,

•

A,
A,

1 9

~

5

g~~

6

~

"
~~
~~
"

12

"

10
A,

.--

.

0
ww"0>

7

A,

t

A,

THRU
A"
DECODE

t

TECHNOLOGY ADVANTAGE
The 2600-1 is fabricated using the MOS nchannel silicon gate process in favor of
metal gate to produce a smaller die size and
a more reliable part. The Signetics proprietary version of the n-channel was developed
to achieve the speed goal of 300ns access as
the major speed distribution under worst
case temperature, supply voltage and input/
output voltage levels. Figure 3 is an illustration of the Signetics manufacturing
process advantages.

22
OUTPUT

BUFFER

21
20

.

19
OUTPUT

1. More system timing margins for system currently designed to the EA 4600 ROM. Eliminates critical timing problems and "soft" errors
due to worst case data settling times, crosstalk,
and coincident timings where several timing
pulse edges often line up during the access
time to latch the data at the earliest possible
time in order to meet system timings.
2. Upgrade current systems using the EA 4600
with the 2600-1 where the ROM is the gating
item for performance. The instruction fetch
time, for example, can be sped up by 45 percent
for program store applic~tions.
3. Anticipate future requirements for faster
ROMs. Microprocessors, for example, are go-

246

0,
0,

BUFFER

'7

0,

,6

1"

OE,

Figure 1

2600-1
PIN CONFIGURATION

N-CHANNEL SILICON GATE
TECHNOLOGY

Figure 2

ing to single +5V supply and becoming progressively faster. A ROM which covers this
spectrum means fewer changes at the system
level which ultimately translates into valuable
development and design time savings and less
dollars spent on qualification, documentation,
design, etc.

SPECIFICATION ADVANTAGE
Power Supply Requirements
The Signetics 2600-1, like the EA 4600,
operates from a single +5V supply and both

ADVANTAGES
Smaller Die
Higher Yield
Lower Production Cost/Die
Better Reliability
Gate Oxide Protection
Self Aligning Gates
Lower Internal CapaCitance
Figure 3

0.

0,

"--r
GNO

Si!)Dl!tiCS

0,

'8

PERFORMANCE ADVANTAGE
The Signetics 2600-1 is specified at 300ns
maximum access/cycle compared with
competition's 550ns access/500ns cycle.
This means a 45 percent improvement in
performance over the EA 4600 equivalent
device, at the same maximum power consumption. What this means to the system
designer is this:

0,

~

J1

The 2600-1 is pin compatible to the EA 4600,
but outperforms it by nearly a 2:1 margin in
access/cycle times. The Signetics 2600-1
also offers many other advantages over EA's
part which will be discussed in the following
paragraphs.

23

'----

-

-

.-L

2048x8
MEMORY MATRIX

8
'5

12.

0,

2600-1

16,384-BIT STATIC ROM-ADVANTAGES OVER THE EA 4600
2600-1 MEMORY APPLICATION MEMO

specify the supply current ICC = 115mA
maximum. The big difference is the speed!
power ratio. Table 1 shows this difference.

Signetics 2600-1

Normalized, this ratio becomes 1 for the
Signetics 2600-1 and 1.8 for the EA 4600.
The 2600-1 is, therefore, nearly two times
more efficient with the same maximum power consumption of 603mW (115mA X 5.25V).
To the system designer this means:
1. No change in power supply ratings is required
when replacing or upgrading systems currently
using EA 4600's with Signetics 2600-1's, although the most performance improvement is
almost double that over EA's part.
2. Cost savings in implementing noise suppression techniques (additional bypass capacitors,
bigger ground/power PC traces, and bus bars)
where multiple ROM chips are employed for a
given speed of operation.

550ns
115mA

EA 4600

Table 1

300ns
115mA

= 2.6 = 1 normalized
= 4.78 = 1.8 normalized

COMPARISON OF POWER SUPPLY REQUIREMENTS
SIGNETICS
2600-1

EA
4600

lOOns min.

300ns min.

300ns min.

500ns min.

300ns max.

550ns max.

TLD

Address to output
delay
Address lead time

50ns min.

100ns min.

TLG

Address lag time

100ns min.

150hs min.

T ARD

Address read to
output disturb

Ons min.

75ns min.

PARAMETER
ARpW
TCYC
TACC

Address read pulse
width
Cycle time

COMMENTS
..

Timing Requirements
The 2600-1 is capable of operation in the
fully static unclocked mode or the clocked
mode. The difference is that in clocked
mode, the input address to the ROM is
latched internally, controlled by the Address Read (AR) input signal, thereby holding the output data valid until the AR signal
allows the next address to be propagated. If
it is desired that the output data changes
with the input addresses, the Address Read
signal is not used and is tied to V ce. It is
also possible to operate in the clocked
mode during other times by controlling the
AR input signal.

Table 2

CLOCKED MODE TIMING COMPARISON

ADDRESS

_ yI;

READ

ADDRESS
INPUT

CYC
T

~

e

....o

-1

"-:~:-;j ~

lr------,~

I
I

e

_______~>K
X
X
r::="":=jx::x
-1 t''"'
----VALID

VALID

DATA O U T P U - T S - - - - - - - - - - - - -

DEFINITIONS
1. T eye Cycle Time-The time between successive address read pulses.
2. T LD Address Lead Time-The minimum time required for the address to be valid prior to the falling
edge of the AR p'ulse.
3. T LG Address Lag Time-The minimum amount of the time required for address to remain valid after
the falling edge of the AR pulse.
4. TARO Address Read to Output Disturb Delay-The minimum time between theAR pulse and the first
output transition when a new address is present.

Figure 4

Si!lDotiCS

=
o
e
w

CLOCKED MODE TIMING

1. Clocked Mode

In the clocked mode of operation, the Address
Read (AR) input signal controls the input address latches similar to a clock controlling a Dlatch where the contents of this set of latches
(the address) selects the corresponding eight
bits of data which become out 0 through out 7.
As long as AR is held high, the input addresses
are allowed to propagate through the latches. If
the addresses change, the address latches will
reflect this change and the selection of the
corresponding data bits begins. However,
when AR is brought to the low level, the addresses are latched to the state of the address
lines prior to the negative transition of AR.
There are minimum set-up and hold time requirements indicated by TLD (address lead
time) and TLG (address lag time). They are the
minimum times the address must be valid before and after the falling edge of the AR signal.
The 2600-1 requires TLD of SOns and TLG of
lOOns compared to EA's lOOns and 150ns,
respectively. This means that for the address to
be latched (thereby the output data is effectively latched) it need only be present in a given
cycle for 150ns compared to EA's requirement
of 250ns. This frees up the address bus for an
extra lOOns where other operations may take
advantage of the bus. A timing diagram for the
clocked mode is shown in Figure 4, while Table
2 is a competitive comparison.

Signetics2600-1 is
twice the speed.
Signetics 2600-1 is
twice the speed.
Signetics 2600-1 is
250ns faster.
Signetics 2600-1 has
100ns margin over
EA 4600.
Signetics 2600-1 has
100ns margin over
EA 4600.
No timing skews

247

2600-1

16,384-BIT STATIC ROM-ADVANTAGES OVER THE EA 4600
2600-1 MEMORY APPLICATION MEMO

The clocked mode is useful when cycle time is
greater than the minimum cycle where, for
example, in common bussed lines it is desirable
to free the bus up as quickly as possible so that
it may be used to initiate another device between memory accesses. Using the ROM in the
clocked mode therefore eliminates the need for
a set of input address latches.
2. Unc/ocked Mode
The 2600-1 is fully static allowing it to be
operated in the unclocked mode. That is, the
output data always reflects the stored data at
the address location of the input address de.layed by the access time when the address is
valid for the minimum specified time. The AR
input is held high when it is desired to operate
in the unclocked mode.
The Signetics 2600-1 output will become valid
300ns from address valid. There is no timing
skew between the minimum cycle and the
maximum access times. Figure 5 shows the
unclocked mode timing diagram and Table 3
presents a competitive comparison.

PARAMETER

TCYC

Address to output
delay
Cycle time

TODD

Output disturb delay

TACC

Table 3

For applications that require the 8 bits of
output data to be multiplexed onto a 4-bit
bus, the Output Enable signal (OE, and
OE2 ) must be timed serially so as not to
garble the output data. Figure 7 illustrates
the 2048X8 organization.

300ns max.

500ns max.

300ns min.

500ns min.

Ons min.

75ns min.

Signetics 2600-1 is
200ns faster.
Signetics 2600-1 is
twice the speed.

UNCLOCKED MODE TIMING COMPARISON

ADDRESS Z
VALID

ADDRESS Y

ADDRESS X
VALID

Vil

VALID

VOH
OUTPUT
INVALID

DATA
OUTPUT

INVALID

VOL

DEFINITIONS
1. T eye Cycle Time-The time between application of successive addresses.
2. TACe Address to Output Delay Time-The maximum time between a new valid address and the
corresponding valid output.
3. TODD Output Disturb Delay-The minimum time between the address change and the first output
transition.

Figure 5

4096X4 CONNECTION DIAGRAM

CONTROL

It is desirable to have as quick a response as
possible in order to minimize these overhead delays.

--

Vee = +5
AR
13
23

..... A.

O.

22

.....A,

21

..... A,

20

..... A,
ADDRESS
INPUTS

0,

DATA
OUT

0,

0,

..... A.
..... A.
~A,

..... A,

12

..... A.
~A'0

2600-1

11

19

10

1.

..... A.

17
15

16

Figure 6

248

COMMENTS

V ,H
ADDRESS
INPUTS

Figure 8 shows the turn-on and turn-off
timing diagrams. The turn-on and the turnoff delay times dictate the minimum time
required to strobe data onto the bus.

The 2600-1 has 550ns (TCO + 2 TOO) of
overhead while the EA 4600 has lOOns of
overhead. The bus is in an indeterminable
state during this time period and cannot be
used to transmit information.

EA
4600

UNCLOCKED MODE TIMING DIAGRAM (AR TIED TO V CC)

Output Flexibility
The 2600-1 is configured as a 2048X8 bits
memory, however because there are separate output enable control signals for the
lower and upper 4 bits of data out, the
corresponding output lines may be OR-tied
to achieve a 4096X4-bit organization. The
output enable signals (OE, and OE2 ) are
then used as A11 and A11 . Figure 6 illustrates
the 4096X4 organization.

SIGNETICS
2600-1

Smnotics

O.

0,

0,
0,

-

-

2600-1

16,384-BIT STATIC ROM-ADVANTAGES OVER THE EA 4600
2600-1 MEMORY APPLICATION MEMO

2048 X 8 MULTIPLEXED ONTO A 4-BIT BUS

VCC"+5V

CONTROL

~AR

13
23

~A,
~A,

DATA
OUT

0,

20

~A,

INPUT

0,

21

~A,

ADDRESS

0,

21

0,

~A,

~A,

2600-1

12

~A,

,.

"

~A,

0,

18

10

~A.

0,
17

~A,

-

0,
15

16
0,

--'-A\o

2'
OUTPUT ENABLE 1

~OE,

=
o

OUTPUT ENABLE 2 ~ DE2

Figure 7

TURN-ON/TURN-OFF TIMING DIAGRAMS

4,---,-1--Tco-----,~ >--I~TOO

DE,

----«

DATA OUT 0-3 _ _ _ _

DE,

E
w

E

o'"

OUTPUT VALID

----------------~I
--«

DATA OUT 4-7 _ _ _ _ _ _ _ _ _ _ _ _

L
___--____,1
OUTPUT VALID

>--r-

E

TOO

Figure 8

SIGNETICS
2600-1

EA
4600

Technology
Performance Access

N-channel, silicon gate
300ns

N-channel, metal
550ns

Cycle
Power Supply
Power Consumption

300ns
+5V
603mW max.

500ns
+5V
603mW max.

150ns max.
200ns max.

300ns max.
400ns max.

PARAMETER

Output Delay
TCO
TOO

Table 4

COMMENTS

Smaller, more reliable die with Signetics process
Signetics 2600-1 is nearly two times faster than
EA's 4600.
Both are fully TTL compatible
Signetics' 2600-1 has the same power consumption
with twice the performance.
Signetic's 2600-1 has less overhead time.
Faster throughout for OR-tied multiple 8-bit output

SIGNETICS 2600-1 VERSUS EA 4600-SUMMARY

Si!lDOlms

249

2616-F.I.N • 2616-1 - F.I.N

DESCRIPTION
The Signetics 2616 is a 16.384-bit static
MOS read-only memory organized as 2048
words by 8 bits. This ROM is designed for
memory applications where high performance. large bit storage. and simple interfacing are important design objectives.
The inputs and outputs are fully TTL compatible. This device operates with a single
5V power supply. The three chip select
inputs are programmable. Anycombination
of active high or low level chip select inputs
can be defined by the designer and the
desired chip select logic level is fixed during
the masking process. These three programmable chip select inputs. as well as OR-tie
compatibility on the outputs. facilitates easy
memory expansion.

The 2616 read-only memory is fabricated
with n-channel silicon gate technology.
This technology provides the designer with
high performance. easy-to-use MOS circuits. Only a single 5V power supply is
needed and all devices are directly TTL
compatible.

PIN CONFIGURATION
F,I,N PACKAGE

FEATURES
• Single 5V power supply
• Guaranteed 350/450ns access lime
• Directly TTL compalible-all inputs and
outputs
• Three programmable chip select inputs
for easy memory expansion or no connection option
• Three-state output-OR-tie capability
• Fully decoded-on chip address decode
• Inputs protected-all inputs have protection against static charge

BLOCK DIAGRAM

A.
A.
A,
A,
A,
A,
A,
A,

U>

~

::>

w

...,

e

U>

J

'"
....
::>

::la:

.
C
C

A,

C

cs,!CS,

i;l
c

::>

a:

.

l:

16,38481T
CELL MATRIX

....

CHIP
SELECT

INPUT

CS:/CS2

BUFFERS

A,
CS)/CI3

A"

ABSOLUTE MAXIMUM RATINGS1
PARAMETER
TA
TSTG

Po

250

Temperature range
Operating
Storage
Supply voltage to ground potential
Applied voltage
Input
Output
Power dissipation

!ii!lDotiC!i

RATING

o to 70
-65 to 150
-0.5 to 7
-0.5 to 7
-0.5 to 7
1

UNIT

·c
V
V

W

16,384 BIT STATIC MOS ROM (204818)

2616 2616 1
2116-F,I,N .2616-1 - F,I,N

DC ELECTRICAL CHARACTERISTICS

TA = O°C to 70°C, Vee = 5.0V

VOL
VOH

Input voltage 2
Low
High
Output voltage
Low
High

III
ILO
lee

Input load current
Output leakage current
Supply current
Capacitance 3

CIN
Co

unless otherwise specified
LIMITS

TEST CONDITIONS

PARAMETER

VIL
VIH

± 5%

Min

Typ

Max

UNIT
V

-0.5
2.2

0.8
Vee
V

Vee - 4.75V
IOL = 1.6mA
IOH = -100JiA

2.4

Vee = 5.25V, OV S VIN S 5.25V
Chip deselected, VOUT = O.4V to Vee
Output unloaded,
TA=25°C, Vee = 5.25V, VIN=Vee
T A = 25° C, f = 1.0MHz, all pins except
pin under test tied to ac ground

0.4
Vee
10
10

JiA

115

mA

JiA

pF
7
10

Input
Output

AC ELECTRICAL CHARACTERISTICS TA = O°C to 70°C, Vee = 5.0V ± 5%, Output load = 1 TTL load and 100pF,
Input transition time = 20ns, Timing reference levels: Input = 0.8V and 2.2V,
Output = 0.4V and 2.4V unless otherwise specified.
PARAMETER
tAee
teo
tOF
tOH

Address access time
Chip select delay
Chip deselect delay
Previous data valid after
address change delay

2616-1

2616
Min

Typ

Max

Min

Typ

Max
350
150
150

450
200
200
20

20

~

UNIT

o

ns
ns
ns
ns

e

III

e

NOTES

.....

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in the operational sections 01
this specification is not implied. Exposure to absolute maximum rating conditions for

o

extended periods may affect device reliability.
2. Input levels that swing more negative than -O.SV will be clamped and may cause
damage to the device.

e

3. This parameter is periodically sampled and is not 100% tested.

TIMING DIAGRAM

Si!l0otiCS

251

16,384 BIT STATIC MaS ROM (2048X8)

2616 2616 1
2616-F,I,N • 2616-1 - F,I,N

PROGRAMMING
INSTRUCTIONS
2616

CARD FORMAT
IDENTIFICATION CARDS
Column 10,11,12,13
Custom number (assigned
by Signetics)
Column 21, 22, 23
CS codes for CS1 (Col. 21), CS2 (Col. 22),
CS3 (Col. 23) such that "0" low selects
or "1" high selects or "N" is no connection.
Column 79, 80
Column 26-78
Truth Table
Customer name and part number

number
C[1prr nt

('l

, "'

ClInpl"H' ~p!"f MJI' PPPT tlLt~1Pn:' (lUT l[l ctllllt'l~ 78

,

"

, '"

II

"'" ""'"

,

,

12222222222222222222222222212222222222222222222222 21Z 2 Z2 2 2 Z2 22 22 2222222222222222

Person responsible for reviewing Signetics
computer generated truth table
ATT~.

SF:.ff'l~Wf[~,

PP[lI'. I'IGP.

" '"""
""III"""

0001100010000006000100 DO 00000 006 DO

oonooo 00000000000000000000000000000 00 00 DO 0 DODO

1 I) I S1'1' IOIlI!1l1111101/1I1Il\1!I!1!1l1!Uill~!'I~llltIUHI.lIJllllll1.!4H'11I1IIIa"SI515111>.~5U'5f1t1UIIUUnHIiIIUOI0111!1!UIi'il1l11!1O
111111111111111111111111111111111111111111111111111111 J J 111111111111111111111111

22212222122222222222222222222222222222222222 2222 22222222 2 2 222 22 2 2 2 222 2 2222222 2 2 2

Street address
,:'

Vrl'lf'If'lG Ff'pP

?~O(,

,

',",' II II

000011010 n noD 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0000000000000000000001100000000000000000000000000
, ! l I I . I I! 1011 11'l II 15 II 11 II II lIIll U1HIII!'I1I!'I1!I19JI lI111l3HI!JJlI!lIlllnlllll""
11111111111111111111111111'11111111111111111111111111111111111111111111111111111

"1!~11;253SH>IUIIIUIUIIUI~ISIIUI~$IJOn'!11lrl'SlinI11!10

2Z 22 2 2 2 2 Z2 2 2 2 22 2 Z2 2 2 2 2 12 2 2 2 2 2 2 Z2 2 2 22 2 2 2 2 2 2 2 212 2 2 n 2222 2 2 2 2 2 2 2 22 2 2 2 222 2 2 2 2 2 2 2 2 2 2 l

City

Zip

State

...~ $l'tJJ'-IYVAl f

"

~

CAL J F[lP~ I P ,?408f

""

"' '"'
;:: 1i 1;

II

0011001100010001160,000000001000001}0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 0 0 000 00 0 0 0 0 0 0 0 0 0

;IJ;1;\lrl'II:I:I:llll;I;111rl'lril{~1~ill!llill!'i'{11liilliiuI5;'iHlull~~;51!i~i~S{ill!iHi~;5i~1I11;!rl'11!;lIttt'l11r,!j

221222 2 2 2 2222 2 2 2 2 2 2 2 2 22 2 2 2 2 2 2 22 2 2 2 2 2 2 2 2 2 22222222 2 2 22 2 2 22 222 2 2 Zn 2 2 2222 2 2 2 2 2 2 2 222

Company name
C'

F'~~'JI(l"~

""

folfM(TF'IF-s

I , II , " '

A. Title card
B. Comment cards
C. Data cards

II II

00000000 noD 0 0 0 0 60 0 0 DI 01 0 0 01" 0 0 00 0 000000000000100100 GO DOl' DIDO 0 0 nln 0 0 0 0 0 0 0 0 00000
II! I 5 I 1 I 11 1011 1;11 IlI,IIII1111:/1111 Unl<1!/l;ZI1t1'JleI1311111l5JiII1111!,III1'IIHI'!i!U II '11111 52 IHIl55f\I51 5HUI I;IIHH56utll fill n IIIH,l\ 161111 '!III
11111111111111111111111111111111111111111111111111111111111111111111111111111111

,-'

All Signetics Read Only Memories utilize
computer aided techniques to manufacture
and test custom bit patterns. The custom bit
pattern is supplied on standard 80 column
computer cards in the format described below.
All address and related output patterns
must be completely defined. Each deck of
cards defining a specific ROM bit pattern
consists of:

It'C.

"'"
,

0000000000 n0 0 0 0 01 0 0 0 0 0 0 0 0 0 0 0 0 00.0 0 0 0 0 0 0 0 00000000000000000000000000000 DII 0 0 0 0 0 0 0 0 0 0
, 1 1 j \ • I B ! ,on '1111.1511111111101\ U131H51IUll~l:;ll1ll)j3\JllI!83!11'1.1tJt"!li4lIH9!O\J r.!IHH;il5JII59IlJfI>Z~I~IIII&!tU'l~1I11111t111~1I111110
1111111111111111111111111111111 \ 111111111111! 11111111111111111111111111111111111

For the user's convenience the data cards
consisting of address and bit patterns can
be specified in anyone of three formats:
1. The hexadecimal format, where each
data card carries (in hexadecimal) the
initial input address for the 32 output
words contai ned on that card, the 32
output words themselves (in hexadecimal) and the ROM truth table number. An
N word ROM, therefore, requires n/32
cards, with all 32 output words defined on
each card.
2. The octal format, where each data card
carries (in octal) the initial input address
for the 16 output words contained on thai
card, the 16 output words themselves (in
octal) and the ROM truth table number.
An N word ROM, therefore, requires N/16
cards, with all16 output words defined on
each card.
3. The binary format, where each data card
carries (in decimal) the initial input address for the 8 output words contained on
that card, the 8 output words themselves
(in binary) and the ROM truth table number. An N word ROM, therefore, requires
N/8 cards, with al18 output words defined
on each card.
Positive logic is used on all input cards; a
logic "1" is the most positive voltage level
and a logic "0" is the most negative level.

2222222222222 Z2 212 2 Z2 2 2 2 212 2 Z 2 2 2 Z2 2 2 212 2 2 2 2 2 2 2 22222222222212222222222'21222221212

Title Card
COLUMN

1-4
7-13

15-19
21

252

SjgDl!tiGS

INFORMATION
Signetics Part Number, that is,
2600, 2616, 2620, etc.
Leave bl.ank _._. Pattern
Number to be lissigned by Signetics.
Punch the letters "CODED"
CS1/eS1/NC Chip Select Logic Level (If low selects chip,
punch "0"; if high selects chip,
punch "1"; if no connection,
punch "N".)

16,384 BIT STnTIC MOS ROM (2048X8)
2616-F,I,N • 2616-1 - F,I,N

PROGRAMMING
INSTRUCTIONS
2616 (Cont'd)
22
23
26-78
79-80

9-10
11-12

CS2/CS2/NC Chip Select Logic Level
CS3/CS3/NC Chip Select Logic Level
Customer Identification
ROM Truth Table Number
(may be left blank)

Output data for initial input
address +1.
Output data for initial input
address +2.

:

69-70
79-80

Output data for initial input
address +30.
Output data for initial input
address +31.
ROM truth table number (may
be left blan k)

Comment Cards
Any number of comment cards may be used
for specifying the user's name, telephone
number, address, any special instructions,
etc. On these cards the letter "C" must be
punched in column 1 and comments can be
punched in columns 2-80.

Hexadecimal Format Data Cards
COLUMN
1-5

7-8

Octal Format Data Cards
COLUMN
1-4

5-7

INFORMATION
Hexadecimal equivalent of the
binary input address (Ao =
LSB)' This is the initial input
address and is punched right
justified, that is,
00000,00020,00040, etc.
Hexadecimal equivalent of the
binary output data (00 = LSB)
for initial input address. EXAMPLE: Column 7 is upper 4
bits.

o

0

-A

COLUMN
1-5

7-14

10100101
Col. 7 1

16-23

7----0

25-32

10100101

34-41

Col. 51

I Col. 7

43-50
52-59

Col. 6

8-10
11-13

Output
address
Output
address

data for initial input
+1.
data for initial input
+2.
I

,
I

I

47-49

I

INFORMATION
Decimal equivalent of the
binary input address (Ao =
LSB)' This is the initial input
address and is punched right
justified, that is, 00000, 00008,
00016, etc.
Binary output data (00 = LSB)
for initial input address. Output data can also be punched
with a "P" or an "N" instead of a
"1" or a "0," respectively.
0
0
7------0

245

5

Col. 8

0

---

I

Col. 7

INFORMATION
Octal equivalent of the binary
input address (AD = LSB)' This
is the initial input address and
is punched right justified, that
is, 0000, 0020, 0040, etc.
Octal equivalent of the binary
output data (00 = LSB) for
initial input address. EXAMPLE:

o

7----0
10100101

79-80

Output data for initial input
address +15.
ROM truth table number (may
be left blank),

Binary Format Data Cards

I
I

I

67-68

50-52

61-68
70-77
79-80

I Col. 14

Output data for initial input
address +1.
Output data for initial input
address +2.
Output data for initial input
address +3.
Output data for initial input
address +4.
Output data for initial input
address +5.
Output data for initial input
address +6.
Output data for initial input
address +7.
ROM truth table number (may
be left blank),

I

Output data for initial input
address +14.

Smnotics

253

=
a
w

E

....
o
E

16,384 BIT STATIC

ios ROM (20n8X8)

26172617 1
2617-F,I,N • 2617-1 - F,I,N

DESCRIPTION
The Signetics 2617 is a 16,384-bit static
MOS read-only memory organized as 2048
words by 8 bits. This ROM is designed for
memory applications where high performance, large bit storage, and simple interfacing are important design objectives.
The inputs and outputs are fully TTL compatible. This device operates wfth a single
5V power supply. The two chip select inputs
are programmable. Any combination of active high or low level chip select inputs can
be defined by the designer and the desired
chip select logic level is fixed during the
masking process. These two programmable
chip select inputs, as well as OR-tie compatibility on the outputs, facilitate easy memory
expansion.

The 2617 read-only memory is fabricated
with n-channel silicon gate technology.
This technology provides the designer with
high performance, easy-to-use MOS circuits. Only a single 5V power supply is
needed and all devices are directly TTL
compatible.

PIN CONFIGURATION
F,I,N PACKAGE

FEATURES
• Single 5V power supply
• Guaranteed 350/450ns access time
• Directly TTL compatible-all inputs and
outputs
• Two programmable chip select inputs for
easy memory expansion or no connection option
• Three-state output-OR-tie capability
• Fully decoded-on chip address decode
• Inputs protected-all inputs have protection against static charge

BLOCK DIAGRAM

0 1 O2 0 3 0 4 0 5 0 6 0 1 0 8

A.
A,
A,
A,

y DECODER 1 OF 16X8

"'ill

A,

It

A,

ID
I-

A.
A,
A.
A.

:>

...,
:>

::l"'0:
C
C

CS/CSl
16,384~BIT

CELL MATRIX

"
cs.rcs-;

A"

ABSOLUTE MAXIMUM RATINGSl
PARAMETER
TA
TSTG

Po

254

Temperature range
Operating
Storage
Supply voltage to ground potential
Applied voltage
Input
Output
Power dissipation

G~nl!tiCG

....

RATING

o to 70
-65 to 150
-0.5 to 7
-0.5 to 7
-0.5 to 7
1

UNIT

°c
V
V

W

16,384 BITSTllTlC MOS ROM (2048X8)

2617 2617 1
2617-F,I,N .2617-1 - F,I,N

DC ELECTRICAL CHARACTERISTICS
PARAMETER

TA = O°C to 70°C, Vee = 5.0V
TEST CONDITIONS

VOL
VOH
III
ILO
Icc

Input load current
Output leakage current
Supply current

Vee = 5.25V, OV:S VIN :S 5.25V
Chip deselected, VOUT=O.4Vto Vee
Output unloaded,
T A = 25° C, Vee = 5.25V, VIN = Vee

Capacitance 3

T A = 25° C, f = 1.0MHz, all pins except
pin under test tied to ac ground

CIN
Co

Vee = 4.75V
IOL = 1.6mA
IOH = -100",A

Address access time
Chip select delay
Chip deselect delay
Previous data valid after
add ress change delay

Max

UNIT

0.8
Vee
V

2.4

0.4
Vee
10
10

",A
",A

115

mA
pF

7
10

AC ELECTRICAL CHARACTERISTICS

tAee
teo
tOF
tOH

LIMITS
Typ

V
-0.5
2.2

Input
Output

PARAMETER

unless otherwise specified
Min

Input voltage 2
Low
High
Output voltage
Low
High

VIL
VIH

± 5%

TA = O°C to 70°C, Vee = 5.0V ± 5%, Output load = 1 TTL load and 100pF,
Input transition time = 20ns, Timing reference levels: Input = 0.8V and 2.2V,
Output = O.4V and 2.4V unless otherwise specified.

2617
Min

Typ

2617-1
Max

Min

Typ

450
200
200
20

Max

350
150
150
20

=

UNIT

o

ns
ns
ns
ns

E
w
E

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2. Input levels that swing more negative than -O.SV will be clamped and may cause
damage to the device.
3. This parameter is periodically sampled and is not 100% tested.

o'"
E

TIMING DIAGRAM

Si!ln~tics

255

16,384 BIT S11111C MOS ROM (2048X8)

2617 '2617 1
2617-F,I,N • 2617-1 - F,I,N

CARD FORMAT

PROGRAMMING
INSTRUCTIONS

IDENTIFICATION CARDS

2617

Column 10, 11, 12, 13
Custom number (assigned
by Signeticsl
Column 8, 9
Custom
designation
"CN"

Column 21, 22,
CS codes for CS1 (Col. 21), CS2 (Col. 22),
such that "0" low selects
or "1" high selects or "N" is no connection
Column 79, 80
Column 26-78
Truth Table
Customer name and part number

Column 1-4
Basic device
number
2';'·17

CI"

("-['T'ff' ('1

U!~'T[1~\fP

I

I III

I

h>I"[ pt'lf' FpPT

111111
11111
I II

tJ!.'~1PfP

['L'T Tr'

II
II

en Uf"~J

7::>

I
II

I

II II

~ ~ ~ ~ ~ ~ ~ ~ ~ ,~ L~ ~ ,0, ~ 1~'~ ~ 1011~!! ~~, ~.~ ~.~,!!~' ~ ~,~, ~R ~ ~r ~.~.~,f"Ol?l~'~ !~,~ R!~, ~,~ ~ ~~ ~ !~,!~t ~ ~l~~S!~'~'~'~' ~, ~1 ~,~,~,~. ~1 ~I ~i~
1 111 1 1111 1 11111111 11111 I 1 I 1 I 11 111 11111111 1 , 11111 1 1 1111 1 I 11 I 111 11111 11 I 1 1 11 II I 111

12222222222222222 Z222 2 2 2 2 2 212 2 222 2 2 2 2 2 2 2 2 2 2112 212121l'2 2 2 2 2 2 2 2 2 2 2 2 2 22221221222212

Person responsible for reviewing Signetics
computer generated truth table
L

S"j;'.[tJ(-;n'fTR, FF-PP.

~nrj.

II

I

111111
I I I I

~lGP.

II
III
I I
00011 0 0 01 0 0 0 0 0 0 0 0 0 01 0 0 nnoD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Don 0 0 0 0 0 0 0 00000000000 nOD 0 0 0 0 0 0 0 1).0 0 0 0 0 0 0 0
I

II

I 11.5 i I I ! IDlll1'1"'\1611,eU1B!1112Jl'151611111!1II11nll)O!llSlI3l11'O';'1'1"'I"4!""~11115H'I\!o15111\9&11l1aiU6'1>S611S8S91Ul1I1J;I'I\!6111!I'1O

11111111111111111111111111111111111111111111111111111111111111111111111111111111

22222222122222222222222222222222222222222222"222222222 2 2 2 2 2 2 2 2 2 2 2 Z2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Street address
.,:" 3:50('

~IH~DHJG

I

l>'[1pTI

1111
I

II
II

I

0000110100000000000000000000000000000000000000 0000 00000110000000000 0000000 00 00 0 00
1 1 1 , I 6 J S 9 1011 1113 1411 I! 11I81!2lIlll:113142516111!1'lW)t 31 !l 3415 163131 lHOli

'141'''''''III4H~11l1!311155&115l1~ISUI ~1illU5SUlstMIO!IIl!114111InlI1HO

111111111111 J 11 t 1111111111111111111111 J 11111111111111111111111111111111111111111

2222222222222 22222 222222

City

n

2 2 2 11 2 22 2 22 2 2 222 Z2 22 2 2 n 12 2222 222 2 2 22 22 2 2 2 2 2 2 2 22 2 Z2 12 2

Zip

State

r---------------------------------------~
C S"tlt'lFy'VPLf, CALIF[lFtlIA '?40::~6

I I
II

II II
II
I III

0011 0 011 0 0 01 0 0 0 0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 DO 0 0 00 0 n0 0 0 0 0 0 0 0 0 0 0 0 0 II 0 0
I 1 1 • 5 , 1 ! ! 101111:311

1~lil1l! 191BlI1113111516111!1!3IIlll7l311313;U383!11Jj)I1'HHI"U~I"'0515.!5lI1515&!1115UGll'H3«IIIU1I!1Y1II1I!1lf'l1161J!81!l1l

111111111111111111 1 ! 1111 J 1111111 J 1111111 J 111111111111111111111111111111111111111

22122222222222222.2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2222122222212222222222222222222222222222222

Company name
..~ )o'AJ'lDt:1'I f'lff'l[lRIfS

I~(',

III
111111
I I II I III
0000000
I 1 1 , I

~

no 0000 00010000000000 00000000 0000 0000 0000 000 00 0000 00 00000000000000 00000000

1 I ! 101111131.151111

1l1l10112I2HHIlS11111l!311l112l3l1l!3iJ111lHBUI1'J"'5'''1's!i5051111:l~~SiIJ5I\!6(l111!131115S16161IHlnnllI4111611!11181

11111111111111111111111111111111111111111111111111111111111111111111111111111111

2222222222222 z.2 2122 2 2 22 22 2 222 2 2 2 2 222 2 222 2222 2 222 2 2 2222 22 22 22 22 22 22222222222 2 2 2 22

All Signetics Read Only Memories utilize
computer aided techniques to manufacture
and test custom bit patterns. The custom bit
pattern is supplied on standard 80 column
computer cards in the format described
below.
All address and related output patterns
must be completely defined. Each deck of
cards defining a specific ROM bit pattern
consists of:
A. Title card
B. Comment cards
C, Data cards

For the user's convenience the data cards
consisting of address and bit patterns can
be specified in anyone of three formats:
1. The hexadecimal format, where each
data card carries (in hexadecimall the
initial input address for the 32 output
words contained on that card, the 32
output words themse.lves (in hexadecimall and the ROM truth table number. An
N word ROM, therefore, requires N/32
cards,with all 32 output words defined on
each card.
2. The octal format, where each data card
carries (in octall the initial input address
for the 16 output words contained on that
card, the 16 output words themselves (in
octall and the ROM truth table number,
An N word ROM, therefore, requires N/16
cards, with all16 output words defined on
each card.
3. The binary format, where each data card
carries (in decimali the initial input address forthe 8 output words contained on
that card, the 8 output words themselves
(in binary) and the ROM truth table
number, An N word ROM, therefore,
requires N/8 cards, with all 8 output
words defined on each card.
Positive logic is used on all input cards; a
logic "1" is the most positive voltage level
and a logic "0" is the most negative level.

Title Card
COLUMN
1-4
7-13

15-19
21

256

Smnl!tiCS

INFORMATION
Signetics Part Number, that is,
2600, 2616, 2620, etc,
Leave blank ___ Pattern
Number to be assigned by
Signetics,
Punch the letters "CODED"
CS1/CS1/NC Chip Select Logic Level (If low selects chip,
punch "0"; if high selects chip,
punch "1"; if no connection,
punch "N"J

16,384 BIT STuTIC MOS ROM (2048X8)

2617 2617 1
2617-F,I,N .2617-1 - F,I,N

PROGRAMMING
INSTRUCTIONS

2617

11-12

Output data for initial input
address +2.
I

(Cont'd)

22
26-78
79-80

CS2/CS2/NC Chip Select Logic Level
Customer Identification
ROM Truth Table Number
(may be left bank)

I

67-68
69-70
79-80

50-52
79-80

,
Output data for initial input
address +30.
Output data for initial input
address +31.
ROM truth table number (may
be left blank)

Binary Format Data Cards
COLUMN
1-5

Comment Cards
Any number of comment cards may be used
for specifying the user's name, telephone
number, address, any special instructions,
etc. On these cards the letter "C" must be
punched in column 1 and comments can be
punched in columns 2-80.

Hexadecimal Format Data Cards
COLUMN
1-5

7-8

Octal Format Data Cards
COLUMN
1-4

5-7

INFORMATION
Hexadecimal equivalent of the
binary input address (Ao =
LSBl. This is the initial input
address and is punched right
justified, that is,
00000, 00020, 00040, etc.
Hexadecimal equivalent of the
binary output data (00 = LSB)
for initial input address. EXAMPLE: Column 7 is upper 4
bits.

o

0

o

-A

5

t

t

Col. 7 Col. 8

9-10

Output data for initial input
address +1.

7-14

245
Col. 5 t

t Col. 7
Col. 6

8-10
11-13

Output
address
Output
address

data for initial input
+1.
data for initial input
+2.

10100101
Col. 7 t

16-23

47-49

25-32
34-41
43-50
52-59
61-68

I

I
I

70-77

I

Output data for initial input
address +14.

Si,gDotiCS

0

7------0

10100101

~

INFORMATION
Decimal equivalent of the
binary input address (Ao =
LSBl. This is the initial input
address and is punched right
justified, that is, 00000, 00008,
00016, etc.
Binary output data (00 = LSB)
for initial input address. Output data can also be punched
with a "P" or an "N" instead of a
"1" or a "0", respectively.

o

0

7------0

7------0

10100101

INFORMATION
Octal equivalent of the binary
input address (Ao = LSBl. This
is the initial input address and
is punched right justified, that
is, 0000, 0020, 0040, etc.
Octal equivalent of the binary
output data (00 = LSB) for
initial input address. EXAMPLE:

Output data for initial input
address +15.
ROM truth table number (may
be left blank>.

79-80

t Col. 14

Output data for initial input
address +1.
Output data for initial input
uddress +2.
Output data for initial input
address +3.
Output data for initial input
address +4.
Output data for initial input
address +5.
Output data for initial input
address +6.
Output data for initial input
address +7.
ROM truth table number (may
be left blank>.

257

~

o

E
w
E

o
E

2560 BIT STATIC CHARACTER GENERATOR (64X8X5)

2M3
2513-I,N

FEATURES
•
•
•
•

TRUTH TABLE

Standard 7X5 dot matrix fits well
TTL level interface signals
Tri-state outputs
Direct, low cost interfacing with TTL,
DTL, CMOS and Signetics MOS 2500
series

PIN CONFIGURATION

CE

OUTPUT

0
1

Data
Open

I,N PACKAGE

BLOCK DIAGRAM

eE
A,
OUTPUT BUFFERS

A,

-----

A,

VGG
MEMORY MATRIX

(2560 BITS)

Voo

A,

-----

A,

COLUMN
ADDRESS DECODER

Vee

A,

A,

A,

A,

ABSOLUTE MAXIMUM RATINGS1
PARAMETER
TA
TSTG
Po

258

Temperature range
Operating
Storage
Power dissipation at TA = 70°C2
Input3 and supply
voltages with respect
to Vee

s~nDtics

RATING

o to 70

UNIT
°C

-65 to 150
730

mW

0.3 to -20

V

2513

2560 BIT SIAlIC CHARACTER GENERATOR (641815)

2513·I,N

DC ELECTRICAL CHARACTERISTICS

TA = O°C to 70°C, Vee = 5V ± 5%, Voo = -5V ± 5%,
VGG = -12V ± 5% unless otherwise specified. 4,5,6.7

PARAMETER

LIMITS

TEST CONDITIONS
Min

VOL
VOH
III
ILO

Input load current
Output leakage current

100

IGG

Supply current
Voo
VGG

CIN

CapaCitance
Address input

0.6
5.3

3.4
One TTL load

V
0.4

-5
3.0
VOUT

VIN = -5.5V, TA = 25°C
= -5.5V, TA = 25°C, VeE = Vee

10
10

500
1000

12
10

15
25

nA
nA

Outputs open
VCE
f

AC ELECTRICAL CHARACTERISTICS

TO

PARAMETER

mA

= Vec

pF

= 1MHz, VIH = Vee, 25mV p.p

10

TA = O°C, to 70°C, Vee = 5V ± 5%, Voo
unless otherwise specified.
FROM

= -5V ± 5%, VGG = -12V ± 5%,
LIMITS

TEST CONDITIONS
Min

teA
tRA
teE

UNIT

Max

V

Input voltageS
Low
High
Output voltage
Low
High

VIL
VIH

Typ

Access time
Character (CM2140)
Row (A1·A3)

Typ

Max

500
450
150

600
500

UNIT

See ac test setup

Output

ns

Chip enable

E
w
E

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other
condition above those indicated in the operational sections of this specification is not implied.
2. For operating at elevated temperatures the device must be derated on a +150°C maximum junction
temperature and a thermal resistance of 110°C/W junction to ambient.
3. All inputs are protected against static charge.
4. Parameters are valid over operating temperature range unless specified.
5. All VOltage measurements are referenced to ground.
6. Manufacturer reserves the right to make design and process changes and improvements.
7. Typical values at +25°C and typical supply voltages.
8. Guaranteed input levels are stated for worst case conditions including a ±5% variation in Vee and a
temperature variation of O°C to +70°C. Actual input requirements with respect to Vee are VIH = Vee
-1.85V and V,L = Vee ·4.15V.

TEST LOAD CIRCUIT

~

o
E

TIMING DIAGRAM

r-------------.----------.------.()+5v

~

CHARACTER ADDRESS
(A4~Ag)

-

V:rn-v

3.OV

ov
S OV
Y-+ov :

~A~~3~DDRES~;:. The devices may also be used in
pairs to provide 9X7 and 10X8 vertical scan
formats.

Person responsible for reviewing Signetics
computer generated truth table
I--IH'. :F'.tr-CrH"fh

ORGANIZATION AS ROM

CUSTOM DEVICES
For unique custom memory patterns, this
form should be used to transmit coding
instructions. The nomenclature for a custom device will consist of the basic product
type followed by a unique CM number assigned by Signetics, Le,2513N/CM2141.
•

Programming with punched cards:
For maximum accuracy and minimum cost and
turn-around time, the truth table should be
transmitted to Signetics in the form of punched
cards according to the format indicated on the
following pages.

260

"i"-;;:.

~ ~ ~ ~ ~ ~ ~ ~ ~ ,~ ~ ~ ~,~ ~ ,O,'~ ,~ ~! ~~, ~7~ R1~ ~,~,~,~ ~ ~ ~ ~ ~ ~ ~ ~ l~ ~,~~. ~ ~ ,oIR,~ ~ ~ ~ ~ I~ ~l~ IO,R ~ ~~, ~~, ~1~Oj~'~ ~~r ~'~o, ~~ ~ ~'~l ~ ~ ~~r~. ~,~
1 III 1 I 1 I 111 11 1 1 I 1 : 11 I 111111111 1111111111111111 I ) 1 i 1111111111 1111111111111111 1111

122 221211? 11212 212 2 Z12 /1112 2 2121 22i 212 ~ 2 ~ 212211112? 21122121111122 2121121112 21121

Street address
.,::

?~(,(,

,

For a straight 512X5 ROM, the 5 outputs will
display anyone of 512 5-bit stored words
corresponding to a 9-bit address applied to
Al-Ag.

;::~~l.

,"""
, , , "'"""

"

~IHU,nlG

pr.-....I'

'II'
II
, , II

~ ~ ~ ~ ~ ~ ~ ~ ~ ,~,~ ,~,~,~,~ I~'~ l~'~ l~~ 1~ ~ ~ ~ ~ ~,~ ~ ~ ~ ~ ~ l~ ~~ )0, J~ l~ ~ ~ ~I ~J~ ~,.~ I~ ~ ~ ~ ~ ~ ~ ~ ~I~ ~~ I~ ~Oi~ ~ ~l~ ~~IOr~I~1 ~ ~ ~~ ~l ~~; .O~ ~I ~1~9!
11111111111111111111 1111 1111111111111 I I 1111 II 11111111111111111111 111111111111111

22111211111122222222212122212122 Z2 11. 1 2 2 2 2 2 ~ 1 2 'I 2 2 2 2 2 2 Z2 2 'I 2 2 2 2 2 2 'I 2 2 'I 2 2 1 2 12 'I 2 1 2 'I 2 'I 'I

City
~'

State
,?l'~'t'y\I~!

II

F. cpt

Zip
IFrf'~~lp

~.l(l?';:

" " " II
, "'

~ ~ ~ ~ ~ ~ ~ ~ ~ 10~,~~, ~ ~ ~\ ~~, ~,'~ ~"~ ~~;l~' ~ ~ ~ ~8'~ ~1~~' ~1~ ~~, ,~, ~~,~,~,~, ~l~' ~\ ~~ ~I? f9~O ~~, ~J~' ~I~' ~ ~~)~,.o; ~1 ~l~ ~.~,~, ~8f! ~l~' ~1 ~J~' ~I ~, ~I~; ~1~"
1111111111111111 1111111111 11 i 111111 11 i 11 1 111111 1 11 1111 111 111111111111 1111111 1111

221222'1212122'1'122'12122111 '2 2112 2 2 2 'I 212 2 2 2 2 2 2 i' 2 2 212 2 2 212 2 2 2 2 'l2 2 ZZ21

z: 2 2 7 2 2 2 2 2 Z2 22 Z

Company name
...' j;'M1I,r::r1

III

/,jE"rrF-!f~

H'C.

'"'"

, , II , " '

~ ~ ~ ~ ~ ~ ~ ~ ~ I~'~'~ I~ ,~ I~'~ ~,~ I~ 1~~ ~ ~ 1~ ~ ~ ~ ~ ~ ~ ~ 1°1 ~! ~l~ ~ l~ ,~.O~~~ ~ ~.~,~ R~.O"O!IOI ~ ~ ~l~ l~ ~ ~!~ \~! ~I ~1fOl~ ~,~ ~~.o, ~G ~ ~1 ~l ~ ~\~ ~r ~I fi~
11 '111111111111111' 1111111 111111111111111111 J 1111111111111111111111 1111111111111

22222222'1212221212'1'122'1'1'122'12'121222 l2 'I 'I 2 21 21 2 2 2 2 'I 2 'I 2 2 2 2 2 ~ 1 2 2 'I 2 2 2 'I 2 22222222,. 2 2 222

S!!Inotics

2iSO BIT STATIC CHARACTER GENERATOR (64X8X5)

2513
2513-I,N

CARD FORMAT (Cont'd)
DATA CARDS
Character number
(Data card ~er)

outPUj 05 - 01 respectively
''-·C(

"c'

(111

(I

1 ('CC'l 1:'(:,'("

1:'~'('1

(,~

It ('e'l ('I' I'C'I'I"C' 1"('1(1('

?

•~~ ~~ ~ ~ ~ ~ ,~ ~ ,~ ,~!!! ~ ,~ ~U! ~ ~ !~I! ~ !!!'1 ~l! t~!!!!! ~!!.D~!tOR~ ~u~ ~ ~~ ~IOI~T2 ~i ~o~ ~ ~,~,~\ ~i~l~i~9 ~ ~ ~1~1 f. ~> ~&~ !J~ ~

I 1111111111111111 \ 11 1 111 11 !II 11 1111 1 1\ 11 111111 I 1111 11 111111 1 11 11111111 11 111 1 1 \ 1 1

222212122 111 2 1 221 Z2 1 2 1 2 1 221122 22 2 21 2 22 12 22 2 l2 1:2 1 22 2 1 21£2 l

n. , 122 2 1 n

2 122 1 2 2 1 2'111 2

Row address

\

\

\

\

\

\

\

\

000 001 010 011 100 101 110 111
.(oo('e'(,

\)! 11(r

1 PDf'l

HIli 1('101 1f'111

I

(1(1('('

(re'c'

('Ill I)

11111 01 00010011100010000010100010000 Olin 0100 016 0 0 0 0 0 0 0 0 {I0 0 0 0 0 0 0 0 n00000000000111
I I l

~

\ ! I I 1 '0 II lilli' 1116 II 'I 11 IU'

1111101\1i1121nl~31

3111)1 !!l&1I18 J!lC4I ll'H .. \ .!IHI'iSGIII2S3S01 \611515U'H1I1!1" !;6!1J Sill

J~

11 11I3IIJ5

liJlI!J91~

111111 t 1111111 I \1111111111111111111111 I 1 I 1111111 11 11 I \ 11111 111 t I 111 I 11 I 1 11 1 I 1 I 1 I
22222221: 1: 22 2 1: 22 21 2 1. 22 2 1: Z2 22 21 Z2 1: 1: 1: 22 U 1 2 1 2 1 2 1112 12 2 1: 1: 122 1: 22 1: 2'11 n 11l 111: 12 12 12 1. 2 1

~

Basic device type
Leave cOlumn\ 10,11,12,13 blank for assignment of

eM

No. bySignetics

o

.e:513H)VC"

I
I

E
w
E

I

~ ~ ~ ~ ~~, ~ ~ 1~ ~ ~ ~ 1~ I~ ~ ,~! I~! ~ 2°, ~~~! ~ !DI~~ ~! ~l~~! ~~ ~~.~ ~'~I~.DI~I~ 2.D!~~ ~ ~ ~:,~~ ~~ ~~I ~!~l~~>~ ~r! ~9 ~6~1 ~1 ~l~' ~~ ~.~ ~1~9 ~e
1111111111111111111111111 t 111111111111111111111111111111111111 J 1\11 J 1111 ! 11111 11
1 Z1: 22 12 1 1: 'I 22 1: 22 12 12 12 221 22 2 1 1: l2 1: 22 1: i 1: 1 22 1. 1: 12 1: 1: 1: 22 2 22 1 212 22 1: 22 11 1: 22 1: 1: 1: 1: 1: 1 1: 1: 1: 221 1: 1:

....o

Character number is in columns 78, 79 and 80. Note that each group of 5-bit words is treated as a
character for convenience of coding.

E

G!!IDl!tiCG

261

2560 BIT STATIC catARACTER GENERATOR (641815)

2513
2S13-I,N

ASCII CHARACTER FONT

For 'upper case order CM2140; For lower case order CM3021.

262

Smnotics

2516-I,N

FEATURES

TRUTH TABLE

• 5V TTL level Input signals
• Tri-state outputs
• Direct, low cost Interfacing with TTL,
DTL and Signetics MOS 2500 series

PIN CONFIGURATION

CE

OUTPUT

0
1

Data
Open

I,N PACKAGE

BLOCK DIAGRAM

CE

=

0
E
w
E
0
E

...

0--t---1
A,

A.
A,

Ao
A,

Vce

A.

A,

A,

A,

ABSOLUTE MAXIMUM RATINGS1
PARAMETER
TA
TSTG
Po

Temperature range
Operating
Storage
Power dissipation at 70·C2
Input3 and supply voltages
with respect to Vee

GwnotiCG

RATING

UNIT
·C

o to 70
-65 to 150
730
0.3 to -20

mW
V

263

3072 BIT STATIC CHARACTER GENERATOR (64X6X8)

2516
2S16-I,N

DC ELECTRICAL CHARACTERISTICS

TA = O°C to 70°C, Vee = sv ± S%, VDD = -SV
VGG = -12V ± S% unless other noted.4.5.6.7

PARAMETER

TEST CONDITIONS

± S%,
LIMITS

VIL
VIH

Input voltageS
Low
High

VOL
VOH

Output voltage9
Low
High

III
ILO

Input load current
Output leakage current

IDD
IGG

Supply current
VDD
VGG

CIN

CapaCitance
Address input

Min

Typ

UNIT
Max
V

-S
3.4

0.6
S.3

-S
3.8

O.S

V
IOL = 1.6mA
IOH = 100,uA
VIN - -S.SV, T A - 2So C
VOUT = -S.SV, TA = 2Soc, VeE = Vee

10
10

SOO
1000

14
8

21
12

Outputs open

nA
nA
mA

pF
10

f = 1MHz, VIH = Vee, 2SmV p-p

AC ELECTRICAL CHARACTERISTICS

TA'= O°C to 70°C, Vee = sv ± S%, VDD = -SV
VGG = -12V ± S%, unless otherwise noted.

± S%,
LIMITS

PARAMETER

TEST CONDITIONS
Min

Max

SOO
400

600
SOO

See test load circuit

Access time
Character
Column (A1-A3)

teA
teLA

UNIT

Typ

ns

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied.
2. For operating at elevated temperatures the device must be derated based on a +150°C maximum
junction temperature and a thermal resistance of 110°C/W junction to ambient.
3. All inputs are protected against static charge.
4. Parameters are valid over operating temperature range unless specified.
5. All voltage measurements are referenced to ground.
6. Manufacturer reserves the right to make design and process changes and improvements.
7. Typical values are at +25°C and typical supply voltages.
8. Guaranteed input levels are stated for worst case conditions including a ±5% variation in Vee and a
temperature variation of aoc to +70°C. Actual input requirements with respect to Vee are VIH = Vee
-1.S5V and V,L ~ Vee -4.15V.
9. Vee tolerance is ±5%. Any variation in actual Vee will be tracked directly by VIL. VIH and VOH, which
are stated for a Vee of exactly 5V.

TEST LOAD CIRCUIT

TIMING DIAGRAM
:-:'::':'----------------+5.0V
'ti l3.DV

+5V

VI CHARACTER~;
(A4 wA 9)
:

AN

2516

OM

Va

7

7
-5V

-12V

-=

I-=-

!

Vo OUTPUT
(O,wOa)

=ya.DV

---+I-~·
,
,
~tCA~

teA = Character access time
telA = Column access time

264

DV

i

,,

15pF
I'DP.

7

DV

,
,,

Vee

sagnotics

i

~,-,;3~.D:::V------+5V

,

~~D_··_ _ _ _ _ _ _ _ DV

~tCLA-i

2516-I,N
for each custom device will consist of the
basic product type followed by a unique CM
number assigned by Signetics, i.e.,
2516N/CM2151.

CHARACTER FORMAT

COLUMN

A,

0

0

0

0

1

1

A,

0

0

1

1

0

0

A,

0

1

0

1

0

1

0

0

0

0

0

0

0,
0,

ADDRESS

will prepare a computer tabulation of the
instructions and return to the address indicated. If errors are detected, they should be
transmitted to Signetics as quickly as pOSSible.

•

Programming with punched cards:
For maximum accuracy and minimum cost and
turn-around time, the truth table should be
transmitted to Signetics in the form of punched
cards according to the format indicated on the
following pages.
• Programming with written truth table:
When punched data cards cannot be supplied,
the truth table may be transmitted in written
form using the attached blank truth table.

0

0

1

1

~

0

0

1

0

0

0

1

0,

0

1

0

0

0

0

O.

0

0

1

1

1

0

0,

0

0

0

0

0

1

0,

0

1

0

0

0

1

0,

VERIFICATION

0

0

1

1

1

0

0,

Upon receipt of either punched card or
written truth table information, Signetics

OUTPUTS

EXAMPLE "S"

LOGIC CONVENTION
Logic "1 "s of blackened squares in the truth
table will result in high output from the
indicated output terminal, i.e., +3.6V minimum. Similarly, a "1" address input level is
interpreted as +3.2V minimum.
Undefined addresses result in "1" level outputs.

CHARACTER ADDRESS

CARD FORMAT
Undefined (column) addresses result In "1" level
(high) outputs.

IDENTIFICATION CARDS
Indicates "comment" card

APPLICATIONS DATA
Output Interfacing Notes
The tri-state outputs on this device exhibit 3
states:
1. "I" = Low impedance to +5V
2. "0" = Low impedance to -SV
3. Off = High impedance, 10m

The off state is controlled by the chip enable
control input.

Custom ROM Organizations
The 2516 is a static ROM with a total
64X6X8-bit capacity. This allows a standard
5X7 font to be encoded In the ROM, e.g., the
2516/CM2150 ASCII font standard product.
A custom coding configuration may make
use of the full 6X8 dot matrix if desired.

~

(" SIGNETICS 251fl'l)<'/n1

11111
I

I

A 6-bit binary address (A4-Ag) selects 1-of64 matrix characters arranged 6 dots horizontally and 8 dots verticaliy. A 3-bit binary
address code (At-A3) selects 1 of 6 columns.
Eight outputs display a complete column of
the character matrix.

STANDARD PATTERN
A standard ASCII Character Font is available for the 2516. This device
(2516N/CM2150) may be used for ASCII
character generation or for device evaluation.

I
I

I

/

pPt~n[l1'1 "'rf'1[lf'JE~

p/f'l

II
I II
I I II I III

I I

For unique custom memory patterns, the
following formats should be used to transmit coding instructions. The nomenclature

13~?lf-l

I

22122212221212222222222222222222222222212 222222212222 2 22222 2 22222 2 2 2 2 2 22 2 2 222 22 2

E

Person responsible for reviewing Signetics
computer generated truth table
~"~".rh"It"rrp.

1-'11T.

II

I
I

I

111111
I I I

n[T.

"1":;:.

II

II
II

III

....o

~ ~ ~ ~, ~ ~ ~ ~ ,~ ,~ ,~ I~'~ ,~ ,~ ,~ ,~ ,~t~ ~~ 1~ 1~ 2~1~1~ !~~~l~l~ ~ l~ ~ !~"~ 3~!!.~ ~,~,O.~ ~.~ !,~ !I~ ~I~~I~! ~1~5~!~ 60Z~1~ ~ ~~!~ ~ ~ ~ ~ ~ ~ ~I ~ ~IJOII~

E

l111111111111111111111111111111111111111111111111illli11111111111111111111111111
22222222122222222222222212222222222222;22222222222122222222222222222222222222222

Street add ress
~JlNI'ING

I

peA!!

I II I II
I I II

0000110100000000000000000000 0000000000800000000000100 0000000000 000000000000000 0 0
I ZliS i ' 1IIInIlIIIIII111111Iltl!I!!1l1l2'!'Z/1IIl.11i!lH41$1111H»IIIII'ZlI'UlliU4141!1111 IlI3IUSlUI51l1lDllltcISlIUi616IiHIIII J!lIJl 1116J11t 111m
11111111111111111111111111111111111111111111111111111111111111111111111\11111111
2222222222222222 Z2 Z2 2 2 2 2 2 2 2 2 2 2 22 22 2 2 Z2 2 2 2 2 22 2 2 Z2 2 2 2 2 Z2 2 2 2 2 2 ZZ2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

City
...'

State

Zip

f.

IFrpl'IIP ":I.1(J::"1S

:;'l!~lrl'(\"pl

r~l

II 1111 II
I
I III
'011 0 011 0 0 OJ 0 0 0 0 0 0 0 0 0 0 0 0 0 01 0 BOO Q ~ 0 DOD 0 0 0 0 0000000000000000000 aDO 0 Don 0 0 0 0 0 0 0 aDon 0 0

I

II

;: : i : :; i11°111l;I;'I;"illi;'i;'12Ii;I~;llrl'll';1 i~~ilJti7i7i' ~ili'ili'1Ji'i~~';!11;'~~i1I;l~~'1!1'~;'~~J~~'lI1'

l'11;ltri'tl!j

! 21 Z2 2 222 2 2 2 2 2 2 Z2 Z2 2 2 2 2 2 2 Z2 2 2 2 2 Z2 222222 Z2 2 22 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 22.2222222222222

Company name
.::

F'~NI,r.foI

f'lff"r'F' I ES' 'nIt.

I II
I II
I I II I III
I ZJ I

~

I

J

I II
I

oonolo 00000110000800000000000000000000
000 DO
s:lSliUUUI51l1lDtiltIUll$iUI6tllltn IZ 11 IllS JI 1111 11 ID

1IIInl!lI"ISI11nlll~21n21Z1ZHi!1Z12\110nllD3I1SH1JII!I*41I!1!1.ISIIIHIlI1051

111111111111111111111111111111111111111111111111111111111111111111111111111 J 1111

2 ZZ22 Z2 2 Z 2 2 Z2 ZZll2 2 2 2 ZZ2 Z2 ZZZ2 Z2 2 2 2 222 2 ZZ2 2 2 Z2 2 2 2 2 2 2 2 Z2 2 2 2 2 2 Z2 2 2 2 2 2 22 22222222222

S!!IDotiCS

=
o
E
w

~ ~ ~ ~ ~ ~ ~ ~ ~,~ ~ ,~ ,~ ,~ ~ I~'~! ~ ~!~ 101~ ~~ ~ R!~!~'~l~ ~ ~!! ~IOi~! ~ttO!~I!!5!S~~!~G~ ~!~!DS~ g,~ ~!~ ~2~1~!! ~ ~ ~ ~I ~~! ~l ~I ~5 ~I ~J ~I~I~

OGODOOODOOlloooaoloDOOOOODoooonOOOOODOO

CUSTOM DEVICES

/customer PIN identification

11 11 1 111 11111111111111 I 11 1111111 111111111111111 111111111 111 11 1 111 , 111 1 1 1 1 1 1 111 11

.: 25(,(1

ORGANIZATION AS
CHARACTER GENERATOR

Leave columns 22, 23, 24, 25, 26 blank
for assignment of CM No. by Signetics

Basic part type

265

2S16-I,N

CARD FORMAT (Cont'd)
DATA CARDS
Decimal character address
(Data card number 001 - 064)

output7 01 respectively

~

OIP

OO(l(l{l:(I(I(I QOl11111 101(1{10(l(l 00001111 101010100(\00000(1

(THIS EXAMPLE ILLUSTRATES OUTPUT SEQUENCE)
11111111011 00 0 a00 0 II 011111 01111 D. 0 00 0111 01111111111110 0 III 0 0 DI O. D0 0 0 I 0 I 0 00 0 01111

' f I. I I ' 11'lnt!IJ'.'5Nl1'lIllIlIZUIIUUU'lIa.JI.D~ • • 17 • • • 61QIU"I.U4l.51515UJ5IUIIJr • • • II • • 14 • • " . . . ""11r.N"'UJ1tn.

11111111111111111111111111111111111111111111111111111111111111111111111111111111
12/2//1222121122122212122111212/1///2//22///2/2/2//1///2//!2//2/222122///2/22212

, , , ,

Column address (A3,A2,A1)

\

000

001

010

I(lt(l(l(l(l(l

(lO(l(l(l{l11

tIt I (1(111

011

100

\

101

00(111111 11(11);0(1(1(1 (I(I{I(I(IO(l(l

0 ••

(THIS EXAMPLE ILLUSTRATES COLUMN ADDRESS SEQUENCE)
0101111101111110000.1011 0 D0111 0'" 0, D1111111 '11111111' II'" 8 D"""""" 0I 001, 0
1 Z J i l l ' I I If II IZlIl"SII",lltllIlInnzHUU'1I1I5IIIJI'IUIIIIJlII • • • IUIIUUS4IIIUl4115UUnUIIlIlIrIl • • I1IZ1UUS." • • ""'lIl1ftSllntlna

1111111111111111111111111111111.111.1111111111111111111111111111111111 11111111111

/2221/ / 21 2 2 2 / 2 2ZZ /22 2 / / 22 / 1 / /2 212 I / / 2 2 I / 1 I 2 I 2 / 22 1 2 /2/ / ZZ 2/ /22 22 1 2 22 22 /2 222 I 2/ / 2 /

Basic device type
Leave columns 10,11,12,13 blank for assignment of CM No. by Signetics
~516,..)1/CM

I
I

I

(HEADER CARD)

~ ~~ ~~" ~ ~! ~ !~1~!!!!!!~ !!!!!!!!!! !!!!! !!!!!!I~!!!!!!!: !!!!!!!5~!~ !!!!!!!~I!~ !~!~ ~I~'!~!
1111111111111111111111111111111111111111111111111111111111111111 011111111111111

UHZ 2 2 22222 Z22HZ 2222 2 2 Z2 22 ZZZ2 2 2 n 2 Z22 2 2 22 2 2 2 2 2 2 2Z2 22 2 ZZZ2 2 n 2 2 2222 22 222 2 22 2 2 2

Character number is in columns 78, 79 and 80.

266

SillBOlies

3072 BIT STATIC CllARACTER GENERAIOR (641618)

2518
2516-I,N

ASCII CHARACTER FONT

Excess addresses yield logic "1" outputs.

S(gnotiCs

267

5184 BIT STATIC ROM CHARACTER GENERATOR (64X9X9)

2526
2526-I,N

DESCRIPTION

PIN CONFIGURATION

The 2526 high speed ROM may be organized as 64X9X9 for use as a character generator, or as a 512X9 ROM for general purpose
use. A read input controls the entry of data
from the ROM into output latches. Threestate outputs allow OR-tying for implementing large memories. Output enable controls the 9 output devices without affecting
address circuitry.

I,N PACKAGE
Vee
OUTPUT 5
OUTPUT 4

OUTPUT 2
OUTPUT 1

BLOCK DIAGRAM
OUTPUT

A.

ENABLE

+-----::~O 0,

COLUMN
DECODER
1 OF 9

5184 BIT
ROM MATRIX
64X9X9

OUTPUT

lATCHES
(9)

+------::~OO,

READ

ABSOLUTE MAXIMUM RATINGS1
PARAMETER

RATING

°0

Temperature range
TA
TSTG

Operating
Storage
Power dissipation at 70°0 2
Input and supply voltages
with respect to Voo3

268

UNIT

o to 70
-65 to 150
730
0.3 to -20

Si!lDDtiCS

mW
V

!i
2526-I,N
TA = O°C to 70°C, Vcc = 5V ± 5%, VGG = -12V
unless otherwise specified 4 ,5,6,7

DC ELECTRICAL CHARACTERISTICS

PARAMETER

± 5%,
LIMITS

TEST CONDITIONS
MIn

VIL
VIH

Input voltageB
Low
High

VOL
VOH

Output voltage
Low
High

III
ILO

Input load current
Output leakage current

Icc
IGG

Supply current9
Vcc
VGG

CIN

Address input capacitance

UNIT
Max
V

-5
3.4

PARAMETER

V

tRpw
tAD
tAG

Address time12
Delay
Pulse gap

3.8

VIN - -5.5V, TA - 25°C
VOUT = OV, TA = 25°C, VCE = Vcc

10
10

500
1000

30
30

55
55

nA
nA
mA

10

f -1MHz, VAC - 25mV p-p, VIN - Vcc·

TA = O°C to 70°C, Vcc = 5V

TO

Pulse width
Readl0
Read 11

0.6
5.3
0.5

IOL = 1.6mA
IOH = 100ILA

AC ELECTRICAL CHARACTERISTICS

tRPW

Typ

± 5%, VGG

= -12V

pF

± 5% unless otherwise specified.

LIMITS
FROM

MIn

Typ

250
500

200
400

Max

UNIT
ns

Address
Read high

Read low

Output
Output
Output

Address
End of read pulse
Output enable

E
w
E

ns
50
50

Address

Delay time

o
E

ns

tAI'3

tA2 13
toE

625
200
100

700
250
250

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and fUnctional operation of the device at these or any other
conditions above those Indicated in the operational sections of this specification is not implied.
2. For operating at elevated temperatures the device must be derated based on a +15O°C maximum

junction temperature and a thermal resistanctt of 1100 elW junction to ambient.
3. All inputs are protected against static charge.
4. Parameters are valid over operating temperature range unless specified.
5. All Yoltage measurements are referenced to ground.
6. Manufacturer reserves the right to make design and process changes and improvements.
7. Typical values are at +25· C and typical supply voltages.
8. Guaranteed input I~els are stated for worst case conditions Including a ±5% variation in Vee and a
temperature variation of OOC to 700 C. Actual input requirements with respect to Vee are VIH = Vee1.85V and V,L = Vee - 4. t5V.
9. Outputs open, tRPW 250ns, tRPW 500ns.
10. During tRPW1 addresses are deccded and sent to the memory matrix and the stored memory data is
moved to the data inputs of the output RS latches. This data is clocked into the output latches at the
end (rising edge) of the read pulse. After 1A2, data appears at the output terminals.
II. During tRPW1 data is clocked into the output latches and t~e address decoders are precharged in
preparation for the next cycle.
12. Addresses must be stable within sans after the read line falls and must remain stable until at least sans
before the read line goes high.
13.1A = O"C to +70·C.

=

=

S!!)DotiCS

=
o

269

2526-I,N

TIMING DIAGRAM
---------+~----~

ADDRESSES

I

ADDRESSES MAY CHANGE

_
_
OUTPUTS

:

~J----,...-------...''''~~_

X

L

All times measured froni 50% pOints.
tr = tf = 10ns or less

CUSTOM CODING
INFORMATION
Data Card Format
I.D.lCOMMENT CARDS
Card No.1
Columns
C
1
Blank
2
SIGNETICS 2526N/CM
3-17
Blank
18-26
Customer 1.0. (company, pro27-71
ject, part no., etc')
Blank
72
Date
73-80
Card No.2
Columns

1
2
3-80

C
Blank
Person responsible for reviewing Signetics truth table

Card No.3
Columns

1
2
3-80

C
Blank
Customer street address

Card No.4
Columns

1
2
3-80

C
Blank
Customer city, state, zip

Card No.5
Columns
1

2
3-80

270

C
Blank
Name

DATA CARDS
Card No.1
Columns
Binary outputs of rows 9
1-9
through 1 (MSB at 9), first column, first character (first character is 000), logic high is high
output (3.2V min)
Blank
10
11-19
Binary outputs of second column, first character
Blank
20
21-29
Third column
Blank
30
Fourth column
31-39
Blank
40
41-49
Fifth column
Blank
50
Sixth column
51-59
Blank
60
Seventh column
61-69
70-71
Blank
Data card number of first char72
acter (1)
Blank
73
74-76
Anything-customer option
Blank
77
Decimal character number
78-80
(000)

Card No.2
Columns
1-9
Eighth column
Blank
10

SjgnRties

11-19
20-70
71
72
73
74-76
77
78-80

Ninth column
Anything-customer option
Blank
Data card number offirst character (2)
Blank
Customer option
Blank
Decimal character number
(000)

Card No.3
Columns
First column, second charac1-9
ter, rows 9 through 1
(etc., as
MSB at (91. Second character is
Card 1)
001.
Card ,No. 4
Columns
(etc., as
Card 2)

Card No. 128
Columns
Decimal
78-80
(063)

character

number

5184 alf SIATIC ROM CM"RACIER GENERATOR (6410X9)

2526
2526-I,N

EXAMPLES
1.0. Card
C"'3200
I

...

Yr~TICj)l

I

sc,:atl C"H¢lR GEN IJIT.., IICJlIC ~j\ll' Pt')lIJ)[lT TtT ,:IS'eII C(ltf,'E'PSJlJN
II III II
I I 11111 I I II I
I ... I
I I

I
I
I
II I II
I
I
I
00,0,00.0001101.010000010,000100.00001110000.00001.,.0101I11.01l0000001l0DlOOooo
I

1 II"

~

I

I

III ,1IT1ll1l1111Ii1JlIIUUUZlnUf.IJltlUIIIJIlUUS.Il • • • f1t1":UU5." • • 5151DDIUUUlIU•• IlIUI .. a5lIJ • • "nIl1J11I1"n""51

11111111111111111111111111111111111111111111 I 11111111111111111111111111111111111

12222222221222222222222122222222222222222212! 2 2 2 2!! 2122 2! 222! 2212 2 22 2 2 22 2 21112 2 2

First Data Card-First Character
(1101 00000 O(\'O'H~Ot'OO {ltt 11 n 00 HIOOOOOIO 1011 (I (lOt (I t 0101 0010 101001016

t··

0

I II 011111 DIIIIIIIII 01.000. 'II 0 '111111 01' 'I' 0111 , .. II 'UIlIiO Olllllloi." 00 0 0 00 II

·1! 1111111.111Z1l1111111'IIIt.rtlllnuullla . . . .ul • • • JI . . . . . . . . . . . . . . 5I5I115U' • • 5I5I • • lIlIa • • • a • • "nnI1IUUIIHI1'I5I

1111111111111111111 1"111111111111111111111111111111111111111111111111111111111111
2ft 22 22 2 222 2 zZ2 ZZ Z!Z 22 2 2 22 2 Zl2 2 Z22 2Zt Z!2 ZZZZ HZ 2 HZ 22 22 222HZ 2ll 2 ZZ2 Z22HZ ZZ22 Z2

Second Data Card-First Character
2

001111100 OO(100{l(t(lO

0

°

II
0 0 0 0 'II 0111111111 0'" 0 I •• , 0.""., 0 0'" 0' "" 0"" "'" " " " " 1 0' 10' 0.0' 0' 01
1 I I • i l l . 11111111116111111 III.al1ilrlullianall.U.D:II".U . . . . . ClQ* • • "DDW5ISlSU• • • g • • • llallM • • 1I • • ,,"fUJlUII,""".
11111111111111111111111111111111111111111111111111111111111111111111111111111111

!22222121222!21112!!1222222!!122!!2!!!1122!2!!2!!2!2!2!!!222!2222!22222122222!22

~
o
E
w

First Data Card-Last Character
1 (1'0(111 (I! (111111111 (1(1'(1(1(1'(1(11(1 O(I:OOOOO{lI 11 01 00001 000010{l(li (100001001

T

.3

1111 0 01' 01 0 0 0.0' 0 0 01111111 01 011111111 0' 1'1'1111 0 01111 0111 0011111011 0 0 00 0 0' 00 0 0 O.
I 2 I • 5 I f 111011

12U~I$IIIl""!D"U'IIIIItI""I!II.n"":IIlnlll • • • '1qQ ....itl.u".5nI5n'Sl5iIU'.5I."Cl13M.II'IIIIIIIII1

IUlllnllllllfllD

1111111111111111111 , 1111111111 1 I I I I I '.'111.1 I I II' 1 , 11111111111111111111111111 111

222222222222222222222222222222222222·22222222222222221222222222222222222222222222

Second Data Card-Last Character
"00000110 000000(100

•

.3

E

1111111 'I '111111111 01 0 0 0 0 0' 0 0' 0 I 0' 0 0 0 00 0I' 0.0' 0 10' 0" I 0 '" DOl' 0 0' o. 0 0 0 0 O. 0' o. 0 00
1 I I . i III t 1111 11 11111S1I1I""11It1 1IIUUUUI'III1I1J1 I'U'JI".31 • • • "IU,.UUUI' • • "tlRU5I15.$l • • • ,laUIlIi.IlI111ll11nTI'I'II$I'lIIIH.

(5

1111' 111111111111111111111111111111111111111111111111111111111111111111111111111

222222222! 212 2 2 2!2 2 2 22 2 2 22! 2 22 2 22 22 2 2! 2 2 2 22! 2 2 2 212 2! 2 !2! 2 22! 2 2 22 2 21121112 2 2 212 22

E

Smnotil:S

271

5184 BIT STATIC ROM CHARACTER GENERATOR (64X919)

2526
2526-i,N

STANDARD CHARACTER FONTS
CM 3400
ASCII SET, VERTICAL .SCAN 7X9 WITH CODE CONVERSION

COLUMN ADDRESSES

A, 0 1 01 0 1 0 1 0
A2001100110
A3 00001 1 1 1 0
A4000000001

•••••••
••••••••
••••••••
••••••••
••••••••
••••••••
••••••••
.i~

DECIMAL ADD "0" (As-A,o)

DECIMAL ADDRESS ."

DECIMAL ADDRESS "2"

DECIMAL ADDRESS "J"

DECIMAL ADDRESS "4"

DECrMAlADORESS "5"

DECIMAL AODRESS "6'

DECIMAL ADDRESS "1"

DECIMAL ADDRESS '8'

tlECIMAlADDRESS "9'

DECIMALAODRESS "10'

DECIMAL ADDRESS "11"

DECIMAL ACDRESS "12"'

DECIMAlACDRESS "13"

DECIMALAODRESS "14"

DECIMAL ADDRESS "15"

DECIMALACDRESS "16'

DECIMAL AODRESS "17"

DECIMALAOORESS '"18"

DECIMAL ADDRESS "19"

DeCIMAlACDRESS "20"

DECIMAL ADDRESS "21"

DECIMAL ADDRESS "22"

DECIMAL ADDRESS "23"

•. .• .• . .
•

•.•:.• .• :. . .

DECIMAL ADDRESS "24"

DeCIMALADDRESS"2S"

DeCIMALAOOReSS"26

DeCIMAL ADDRESS "'21"'

DECIMAL ADDRess "'28"'

DeCIMAL ADDRess '"29""

DECIMAlADDReSS"'30'"

DeCIMAL ADDRESS "3''"

DECIMAL ADDRESS ""32'"

DeCIMAL ADDRESS '"33"'

DECIMAL ADDRESS '"34"

DECIMAL 'ADDRESS ""35"'

DeCIMAL ADDRESS "'36"'

DECIMAL ADDRESS "37"

DECIMAL ADDRESS "38'"

DECIMAL ADDResS "'39"

DECIMAL ADDRESS ""40"'

DECIMAL ADDRESS "'41"

DECIMAL ADDRESS "'42"

DECIMAL ADDRESS ""43"'

DECIMAL ADDRESS "'44""

DECIMAL ADDRESS '"45'"

DECIMAL ADDRESS ""46"'

DECIMAL ADDRess "47"

DECIMAL ADDRESS "48"'

DECIMAL ADDRESS '"49""

DeCIMAlADOReSS"'50"

DECIMAL ADDRESS "51""

DeCIMAL ADDRess "'52"

DECIMAL ADDRESS "53"

DeCIMAL ADDRESS '"54"

DeCIMAL ADORESS ""55"'

DECIMAL ADORESS "56"

DECIMAL ADDRESS ""51"'

DECIMAL ADDRESS "58"'

DECIMAL ADDRESS "59'

DECIMAL ADDRESS ""SO"

DECIMALADORESS '"61""

DECIMAL ADDRESS "'62"'

DECIMAL ADDRESS "63""

:

.. .;: . : ••••.••
:
•
: .: . • . ..:.:: I I : : ..• : :
;,;:~

,

,::}

:::::::

::~:::

:,::::

NOTES

A. BCOIC to ASCII in leftmost column, Baudot to ASCII in next column to right.
B. Undefined addresses result in all outputs going low (TTL "0").
C. Black squares in character font are high (TTL "1 "l.

272

S!!IDl!tiCS

;::;'

,

-:::{

=::::i

>;:

'

5184 BIT STATIC ROM CHARACTER GENERATOR (64X9X9)

2526
2S26-I,N

STANDARD CHARACTER FONTS

(Cont'd)

CM 3941
ASCII SET, RASTER SCAN 7X9 WITH CODE CONVERSION

0 0 0 0
0 0 0 1
0 0 1 0
o1 1 1
0 1 0 0
9 1 0 1
o 1 1 0
0 1 1 1
1 0 0 0

,

w""
•
::

•
:;;

:':,'.:;:

DECIMAL ADDRESS "1"

DECIMAL ADDRESS "2"

DECIMAL ADDRESS "3"

DECIMAL ADDRESS "4'

~~ " ·
.
,,t
'"
:~:~
~f,
::'::::

r:: ;:;:;

F ::::;:

DECIMAL ADDRESS "8"

DECIMAL ADDRESS "9'

DECIMAL ADDRESS "10'

: j: ~: ::.,.::

DECIMAL ADORESS "11'

Y

%

DECIMAL ADDRESS "5"

OECIMAlADDRESS "6"

-~: :;~;

$

::: i'
DECIMAL ADDRESS "7"

."!:, •
. I"'I.'.':; : : ' ; : : : ' : ; : '
,e"
.:.

"",.

':~;_

.~': . : : : f . . 1 :

: : " ;: . : ,

.• .':::: . ' 111.'\;':'

DECIMAL ADO "0" (A5-A,ol

"\ %,

;~: :.::;'

t:

': ~

DECIMAL ADDRESS "12"

OECIMALAODRESS"13'

-""

':::.,; :,~:

::" :.;;;

',? :w

DECIMAL ADDRESS "14"

'

DECIMAL ADDRESS "15"

••••••••
••••••••
••••••••
.:i
.
g , ( ."'.;; .;;.';
••••••••
DECIMAL ADDRESS "16"

DECIMALADDRESS"11"

DECIMAL ADDRESS "HI"

DECIMAL ADDRESS "19"

DECIMAL ADDRESS "20

DECIMAL ADDRESS "21"

DECIMALADDRESS"22"

DECIMAL ADDRESS '"23"

DECIMALADDRESS "24"

DeCIMAL ADDRESS "25'"

DECIMAL ADDRE5S "'26

DECIMAL ADDRESS "27'

DECIMAL ADDRESS "28'"

DECIMALADORESS"29'

DECIMAL ADDRESS "'30'

DECIMAL ADDRESS "'31'"

.:•;.
•

•........
i:
•.....
:.;
_it; . ; :
H
:/:

::::":

DECIMAL ADDRESS "32"

DECIMAL ADDRESS "'33"

DECIMAL ADDRESS "34"

DECIMAL ADDRESS '"35'

DECIMAL ADDRESS "'36'"

DECIMAL ADDRESS "'31'"

DECIMAL ADDRESS "38"

DECIMAL ADDRESS "39"'

DECIMAL ADDRESS "40"

DECIMAL ADDRESS '"41"

DECIMAL ADDRESS "42'"

DECIMAL ADDRESS "43'"

DECIMAL ADDRESS "'44"

DECIMAL ADDRESS "45"

DECIMAL ADDRESS "46"

DECIMAL ADDRESS "41"'

t,,';

:;;:':''';

';:;~;

.;:'

m.:

NOTES

s
' M
.'::. .;:':: . " ' .

-':~::

-'::~

.:':"-

'lr

.~c

,:;,~:

::::-;~

',c::,

.~;...... ..~;: .
.~ "
n

=,;.-

W

':':'<

.:

::::i.

'-.' ::,~

B;1: . : ' : •
;W
.
:L"
;;.,.i
,.,,';'.

DECIMAL ADDRESS "48'

DECIMAL ADDRESS "49'

DECIMAL ADDRESS "50"

DECIMAL ADDRESS "51"

DECIMAL ADDRESS "'52"

DECIMAL ADDRESS "53"

DECIMAL ADDRESS "54"

DECIMAL ADDRESS "55"

DECIMAL ADDRESS "56'

DECIMAL ADDRESS "51"

DECIMAL ADDRESS "58"

DECIMAL ADDRESS "59"'

DECIMAL ADDRESS "60"

DECIMAl-ADDRESS "'61"

DECIMAL ADDRESS "62"

DECIMAl. ADDRESS "63'"

A. BCOIC to ASCII in leftmost column, Baudot to ASCII in next column to right.
B. Undefined addresses result in ali outputs gOing low (TTL "0"1.
C. Black squares in characer font are high (TTL "1"1.

SmDotiCS

273

rae

o
E
1M
E

...C

E

17021

2048 BIT ELECTRICALlY PROGRAMMABLE MOS ROM (25618)

1702A-1

DESCRIPTION

FEATURES

The 1702A is ideally suited for uses where
fast turn-around and pattern experimentation are important. The device undergoes
complete programming and functional testing on each bit position prior to shipment,
thus insuring 100% programmability.1

• Fast programming for all 2048 bits: 2
minutes
• All 2048 bits guaranteed programmable
• 100% factory tested
• Fully decoded
• Static MOS: No clocks required
• Inputs and outputs DTL and TTL compatible
• Trl-state output: OR-tie capability
• Simple memory expansion
•. Chip select Input lead

The 1702A is packaged in a 24-pin dual inline package with a UV transparent lid. The
transparent lid allows the user to expose the
chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written
into the device.

PIN CONFIGURATION

The 1702A is fabricated with silicon gate
technology. This low threshold technology
allows the design and production of high
performance MOS circuits and provides a
higher functional density on a monolithic
chip than conventional MOS technologies.

I PACKAGE

DATA OUT 1

4

DATAOUT2

5

DATAOUt3

6

DATAOUT4

7

DATA OUTS

8

DATA OUT 6

9

DATAOUT7

DATA OUT 8

'1

Vee

BLOCK DIAGRAM

PIN DESIGNATION2

t--------t

Read mode
12

Vee

Vee

13

Program

Vee

14

CS

GND

15

Vee

Vee

16

VGG

VGG

22

Vee

Vee

23

Vee

DATA OUT 8

DATAOUTl

PIN.NO. SYMBOL NAME & FUNCTION

OUTPUT
BUFFERS

es - +

t
PROGRAM

-

2048 BIT
ROM MATRIX

(256'8)

t

Vee
Programming mode

12

Vee

13

Program

14

-CS

GND

DECODER

Program pulse

t

GND

15

Vee

Vee

16

VGG

Pulsed VGG (VIL4P)

22

Vee

GND

23

Vee

GND

INPUT
DRIVERS

t ,---------t
Ao A,

ABSOLUTE MAXIMUM RATINGS3

TA
TSTG
Po

274

PARAMETER

RATING

Temperature range
Operating
Storage

o to +70

Power dissipation
Soldering of leads (10sec)
Input voltages and supply
voltages with respect to Vee
Read operation
Program operation

SillBOlies

UNIT
·C

-65 to +125
2
300

0.5 to -20
-48

W

·C
V

1702A-1

DC ELECTRICAL CHARACTERISTICS

PARAMETER

TA = O°C to 70°C, Vee = 5V ± 5%, Voo
unless otherwise specified. 4

= -9V ± 5%, VGG3 = -9V ± 5%
LIMITS

TEST CONDITIONS
Min

VIL1
VIL2
VIH

VOL
VOH
III
ILO

Input voltage
Low for TTL interface
Low for MOS interface
Address and chip
select high

leF1
ICF2
IOL
IOH
CIN
COUT

IOL = 1.6mA
IOH = -100"A

Address and chip select
input load current
Output leakage current

VIN

3.5

-.7
4.5

= O.OV

= O.OV, CS = Vee -2
IOL = O.OmA
CS = Vee -2, TA = 25°C
CS = 0.0, TA = 25°C
CS = Vee -2, TA = O°C

VOUT

35
32
38.5

Gate

Sink
Source
CapacitanceS
Input
Output

VOUT = -1.0V
TA = O°C
TA = 25°C
VOUT = 0.45V
VOUT = O.OV
All unused pins are at ac ground
VIN = Vee, CS = Vee
VOUT = Vee, VGG = Vee

AC ELECTRICAL CHARACTERISTICS

PARAMETER

0.45
1

"A

1

"A
mA

50
46
60
1
mA

8
1.6
-2.0

14
13

==
o

4

ew

pF
8
10

15
15

e

....o

TA = O°C to 70°C, Vee = 5V ± 5%, Voo = -9V ± 5%
unless otherwise specified, Input pulse amplitudes = 0 to 4V, tR, tF S 50ns,
Output load is 1 TTL gate, Measurements made at output of TTL gate
(tpo ~ 15ns), CL = 15pF

TO

LIMITS

FROM
Min

Freq
tOH

0.65
Vee-6
Vee+0.3
V

Output voltage
Low
High

Output current
Clamp

UNIT
Max
V

-1.0
Voo
Vee-2

Supply current
1001
1002
1003
IGG

Typ

Typ

Repetition Rate
Previous read data valid

UNIT
Max
1
100

MHz
ns

1
100
900
300

"s
ns
ns

Delay time
tAec 1
tcs
teo
too

Output
Output
Output

Address
Chip select
CS

Output deselect

0.7

ns

NOTES
1. Signetics liability shall be limited to replacing any unit which fails to program as desired.
2. The external lead connections to the 1702A differ depending on whether the. device is being
programmed or used in read mode. In the programming mode, the data inputs 1-8 are pins 4-11
respectively.
3. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other
condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
4. Typical values are TA = 25°C and at typical supply voltages.
5. This parameter is perdiodically sampled and is not 100° tested.

SmDDtiCS

275

e

1702A

2048 BIT EEECI RICAHt PRlUiRAMMABLE MOS ROM (25618)

1702A-1

TIMING DIAGRAMS
DESELECTION OF DATA OUTPUT IN OR-TIE OPERATION

READ OPERATION
1""--

CYCLE TIME ::: 1/FREQ

~

VIHX
\10%

xi-I- - -

V 1L

•

1=::..-_ _ _ _ _ _ _ _~1

ADDRESS

_90%

IICS t-

V,L

V,L

_

I

X:'

X

It---------..J.

VIH~

'OH

l----l

1

cs

L _ _ __

I

~
: I

VIH

,H
ADDRESS V

I:

10%

V,L

I

I

:

I

VOH

DATA OUT

DATA
OUT

1

DATA OUT

DATA
OUT

1

VOH---t

1

1...- - - -

DATA OUT

:

INVALID

I
-t

INVALID
VOL

INVALID
ICO

'ACC

I'

TYPICAL PERFORMANCE CHARACTERISTICS

39
38
37

;;
S.

36

illa:

34
33

...

a:

35

'\

c

_0

31

29

INPUTS", Vee
OUTPUTS ARE OPEN

\.

'\

"'\ '\
'\..

32

30

Voo= -9V
VGG= -9V

:J

0

tt

Vee= +5V

--

Cs::: O.ov

Vee::: +5V

'"

;;
S.

0.

...0

28
27

40

60

.... ,....

80

~

-

....

c
w

T A = 25°C

10.0

/

8.0
6.0

Cs:::

/'

O.OV

/

600

:&

500

::l
0

400

"

300

.,>=

0

200

4.0

1-

100

VGG= -9Y

::>

0

700

Voo::: -9V

12.0

:J

"- I......

800

14.0

...OJ ...
... ~
:J a:

~=VCC

.....
20

900

IIIIZ

r-..

ACCESS TIME va
LOAD CAPACITANCE

OUTPUT SINK CURRENT
va OUTPUT VOLTAGE

100 CURRENT va TEMPERATURE

2.0

-

V V

-4

120

-3

AMBIENT TEMPERATURE ("C)

-2

100

V

o

10

20

30

40

50

60

70

80

90 100

LOAO CAPACITANCE (pF)

~1

OUTPUT VOLTAGE (VOL T5)

OUTPUT CURRENT va
VDDSUPPLY VOLTAGE

ACCESS TIME va
TEMPERATURE

OUTPUT CURRENT vs
TEMPERATURE

900
800
700

!w
:&

>=

en
en
w

0
0

"

600

-

Vee::: +5V
YGG= -9V

-

~~
~~
-~~

YOLO +.45V /

TA = 2SOC

500
Specified
Operallng Range

400
300
200
100

-:11

VOO= -9V
VGG= -9V

1

-3

Vee= +5V

::>

VOG= -9V
Y OH ::: O.OY
T A = 2s"C

a:

AMBIENT TEMPERATURE (OC)

.,o
...::>
~

l~~

..........

o

1l
~

-4

~ ~-3
:J

o
r
o

a:

:J

O

-4
-6

-7

-8

-9

VOO SUPPLY VOLTAGE (V)

276

I

Til

;(

enS.
......
::> z

S
-s

1

es= O.DV

t"-..~r-

I---

-3.5

:J

1
"

~

J:

w

o

~

+5V
-9V
-9V
+.45V

~~

1 TTL LOAD::: 20pF

Vee= +5V

~

VCC=
Voo=
VGG=
VOL =

Si!lnotics

-10

r-

Vee=
Voo=
V GG,=
V OH =

+5V
-9V
-9V
o.ov

I

.J.

r1I

I-

-- I I
~

0102030405060

cs= o.ov

7080

AMBIENT TEMPERATURE (0 C)

90

1702A-1

DC AND OPERATING PROGRAMMING CHARACTERISTICS TA = 25°C, Vee = OV, Vss = +12V ± 10%,
CS = OV unless otherwise specified.
LIMITS
PARAMETER

TEST CONDITIONS

VIL4P

Input voltage
High
Pulsed data low
Address low
Pulsed low Voo and
program
Pulsed low VGG

IU1P
IU2P
Iss
loop

Load current
Address and data input
Program and VGG
Vss supply'
Peak 100 supply2

VIHP
VIL1P
VIL2P
VIL3P

Min

Typ

-46
-40
-46

0.3
-48
-48
-48

-35

-40

10
200

10
10
100
300

UNIT

Max

V

mA
VIN
VIN
Voo

= -48V
= -48V

= Vprog = -48V, VGG = -35V

AC PROGRAMMING CHARACTERISTICS TA = 25°C, Vec = OV, Vss = +12V ± 10%, CS = OV, unless otherwise specified,
Input rise and fall times = < 1J.1s unless otherwise specified.
LIMITS
PARAMETER

tllPW

Duty cycle (Voo, VGG)
Program pulse width

tow

Setup and hold time
Setup time

tOH

Hold time

tvw

Setup time

tvo

Hold time

tAcw

Setup time3

tACH

Hold time3

tATW

Setup time

tATH

Hold time

TO

FROM

TEST CONDITIONS

Voo

Min

Typ

Max
20
3

= Vprog = -48V, VGG = -35V

UNIT
%

ms
J.ls

Programming
pulse
Data

Data

25

Programming
pulse

10

Programming
pulse
Pu Ised power
supply

Pulsed power
supply
Programming
pulse

100

Pulsed Voo
power supply
Address

Address

Programming
pulse
Address

10

25

Address

10

Programming
pulse

10

E

NOTES
1. The Vee supply must be limited to l00mA current to prevent damage to the device.

2. loop flows only during Voo, VGG on time. loop should not be allowed to exceed 300mA for greater than
100",8. Average power supply current loop is typically 40mA at 20% duty cycle.

3. AilS address bits must be in the complement state when pulsed Voo and VGG move to their negative
levels. The addresses (O~255) must be programmed as shown in the timing diagram.

SfgRotiCS

E
w
E

o'"

100

25

Pulsed Voo
power supply

=

o

277

1702A-1

TIMING DIAGRAM
PROGRAM MODE
-t'ACH

'------'Acw-----•.jl
I
ADDRESS

1-

I

I

I

r---------------~

I

I

I
I
I
I

BINARY COMPLEMENT
ADDRESS OF WORD
TO BE PROGRAMMED

-4010-48

BINARY ADDRESS

OF WORDTD BE
PROGRAMMED

I

PULSED VOO

I
I
-48
I
I
_____________________ I I

POWER SUPPLY

-4610

~Fi

PULSED VGG
POWER SUPPLY

--i-----+'

t-I\[:jlI

-35 to -40

I 'vw I

i-'pw-l

PROGRAMMING
PULSE

I

I

I

-46to-48

I_'OW _I

~

DATA INPUT

8t;V~~~

I

:-'ATH-t

I

I

I
I

....:.-t'OH I-

~~~~~~~~~~
DATA STABLE

~~~~~~~~~~~~~_ _ _T_'M_E_ _ _~~~~~~
-46 to -48:'::
LINES)

OPERATION IN PROGRAM
MODE
Initially, all 2048 bits of the ROM are in the
low state. Information is introduced by selectively programming high's in the proper
bit locations.
Word Address selection is done by the same
decoding circuitry used in the Read mode
(see dc Electrical Characteristics tablel. All
8 address bits must be in the binary complement state when pulsed Vee and VGG move
to their negative levels. The addresses must
be held in their binary complement state of a
minimum of 251's after Vee and VGG have
moved to the negative levels. The addresses
must then make the transition to their true
state a minimum of 10l's before the program
pulse is applied.
The 8 output terminals are used as data
inputs to determine the information pattern
in the 8 bits of each word. A low data input
level (-48V) will then program a "1" and a high
data input level (ground) will leave a "0" (see
dc and Operating Programming Characteristics tablel. All 8 bits of one word are pro-

278

grammed simultaneously by setting the
desired bit information patterns on the data
input terminals.
During the progamming, VGG, Vee and the
program pulse are pulsed signals. We recommend the P+4P smart programming routine where P = the number of programm ing
pulses for data to read true; P max = 256;
and 4P = the number of over programming
pulses applied.

ERASING PROCEDURE
The 1702A may be erased by exposure to
high intensity short-wave ultraviolet light at
a wavelength of 2537A 0 • The recommended
integrated dose (i.e., UV intensity x exposure time) is 6W-sec/cm2. Examples of ultraviolet sources which can erase the 1702A
in 10 to 20 minutes are the Model UVS-54
and Model S-52 short-wave ultraviolet
lamps manufactured by Ultra-Violet Products, Inc., 5114 Walnut Grove Avenue, San
Gabriel, Ca. The lamps should be used
without short-wave fi Iters, and the 1702A to
be erased should be placed about one inch
away from the lamp tubes.

Sjgnotics

IIII~III ~IIII~IIII 1111111111111111111111111111111111111

Iii

2704-1 .2708-1

DESCRIPTION

FEATURES

The 2708/2704 are high speed Erasable and
Electrically Reprogrammable ROMs
(EPROM) ideally suited where fast turn
around and pattern experimentation are important requirements.

• Organization:
2708:1024X8
2704: 512X8
• Fast programmlng-l 00 sec. typ for all8K
bits
• Low power during programming
• Access time: 450ns
• Standard power supplies 12V, ±5V
• Static-no Clocks required
• Inputs and outputs TTL compatible durIng both read and program modes
• Three-state output-OR-tle capability

The 2708/2704 are packaged in a 24 pin
dual-in-line package with transparent lid.
The transparent lid allows the user to expose the chip to ultraviolet light to erase the
bit pattern. A new pattern can then be written into the device.

PIN CONFIGURATION
I PACKAGE

*
vee

A pin for pin mask programmed ROM, the
Signetics 2607, is available for large volu me
production runs of systems initially using
the 2708.

o.

The 2708/2704 is fabricated with the time
proven n-channel silicon gate technology.

0,

'2708= Ag
2704 = vss

BLOCK DIAGRAM

I;

DATA OUTPUT

o

0,,,0.

I

CHIP SELECT
LOGIC

OUTPUT BUFFERS

y
DECODER

YGATING

X
DECODER

ROMAARAV

Ii
1M
Ii

o
Ii

A,-A,
ADDRESS
INPUTS

--

64 X 128

ABSOLUTE MAXIMUM RATINGS1
PARAMETER
TA
TSTG
Po

Temperature range
Operating
Storage
Power dissipation
All input or output voltage
with respect to Vee
(except program)
Program input to Vee
Supply voltages Vee and
Vss with respect to Vee
Voo with respect to Vee

S(gnotics

RATING

UNIT

·C
Oto 70
-65 to 125

1.5

W

15 to -0.3
35 to -0.3
15 to -0.3

V
V
V

20 to -0.3

V

279

Bfi#BfT ERmm~RleAttY REPROGRAMMABEEJlOS ROM (S12X8) 2704
-mmL.JIIIDlSDtf?AND RElRIGALE' REPROGRAMMABEE MOS ROM (102418) 2708
2704-1 • 270B-1

DC ELECTRICAL CHARACTERISTICS

PARAMETER

VIL
VIH

Input voltage
Low
High

VOL
VOH1
VOH2

Output voltage
Low
High
High

Vee = 5V ± .25V, Vss = -5V ± .25V, Voo = 12V ± .6V, Vss
TA = O°C to 70°C, Output load = 100pF plus HTL input.

ILO

Min

VIH

3.7
2.4

= 5.25V

itA
10

= 5.25V,

CSIWE

CIN
COUT

Capacitance3
Input
Output

AC ELECTRICAL CHARACTERISTICS

0.65
Vee + 1
0.45

CSIWE

= 5V

VOUT

Power dissipation

UNIT

V
IOL = 1.6mA
IOH = -1OOItA
IOH = -1mA

Worst case supply currents,
All inputs high

Po

Max

V

Output leakage current

Voo
Vee
Vss

Typ2

Vss
3.0

Supply current
100
lee
Iss

LIMITS

TEST CONDITIONS

Input load current
Address and chip select

III

= OV,

= 5V; TA =

10

50
6
30

O°C

TA - 70°C
TA

itA
mA

65
10
45
BOO

= 25°C, f = 1MHz
VIN = OV
VOUT = OV

mW
pF

4
B

6
12

Output load = 1 TTL gate and CL = 100pF,
Input rise and fall times = 20ns,
Timing measurement reference levels = O.BV and 2.BV for inputs,
O.BV and 2.4V for outputs. Input pulse levels = 0.65V to 3.0V
LIMITS

PARAMETER

TO

FROM

Output
Output

Address
Chip select

Output
Output

Chip deselect
Address

Min

Typ

Max

2BO

450
120

ns

Delay time
tAee
teo
tOF
tOH

Float time
Hold time

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditionsabovethose indicated in the operational sections of this specification is not implied. Exposureto
absolute maximum rating conditions for extended periods may affect device reliability.
2. Typical values are for TA = 25°C and typical supply voltages.

3. This parameter is periodically sampled and not 100% tested.
4. The program input (pin 18) may be tied to Vss during the read mode.
5. 8ignetics reserves the right to make changes in specification at any time and without notice. The information furnished by 8ignetics in this publication is believed to be accurate and reliable. However,
no responsibility is assumed by 8ignetics for its use; nor any infringements of patents or other rights
of third parties resulting from its use. No license is granted under any patents or patent rights of 8ignetics.

280

UNIT

SillDl!tiCS

0
0

120

ns
ns

2704-1 • 2708-1

TIMING DIAGRAMS
READ MODE

ADDRESS ________

~~~-------------------------------~~I~__________________
\--'OH--I

I

---------rl--~

iI

CS1WE

I~~I---------

\

I:

~.cO---l

I

II

1

J'""' DF

I-'ACC-I

~~~~~I________________~_~t_~_~_'~_T_

DATA
OUT

WRITE MODE

1 - - - - - - - - - - - - - - ONE PROGRAM LOOP----X--/~==-=--=--=--=----~------I}_

..""~.

ADDRESS

=.m ,

J. -------------"- _

ADDRESS 1023

=
o

"----

20V
PROGRAM
PULSE

OV----------'

E
w
E

DATA
0 1 -0 5

o---

Program Mode: CS/WE = +12V

E

~~~~ --~·-tl-------------------- PR~OG;:M -----------------~~-- ~6~~

~~~
-I}----

ADDRESS

12V
Cs/WE 5V

26V
PROGRAM
PULSE

DATA OUT

VALID

Read/Prog ram/Read Transitions
logic levels and timing reference levels same as in the Read Mode unless noted otherwise.

SjgD8tiCS

281

IIII~IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII.IIIIIIIII 11111

I.

2704-1 • 2708-1

PROGRAMMING SPECIFICATIONS TA = 25'C
PARAMETER

tAS
tAH
tcss
tCH
tos
tOH
tOF
tOPR
tpw
tPR
tPF
Ip
Vp

Setup and hold time
Address setup
Address hold
CS/WE setup
CSIWE hold
Data setup
Data hold
Chip deselect to output
float delay
Program to read delay
Program pulse width
Program pulse rise time
Program pulse fall time
Programming current
Program pulse amplitude

LIMITS

Min

Typ

Max

UNIT
p's

10
1
10
.5
10
1
0

.1
.5
.5
10
25

120

ns

10
1.0
2.0
2.0
20
27

p's
ms
p's
p.A
mA
V

PROGRAMMING PROCEDURE

ERASING PROCEDURE

At shipment and after each erasure, all bits
of the 2708/2704 are in the logic high state
(output high). The device is put into the program mode by raising the CS/WE input (pin
20> to +12V. While in the program mode,
data to be stored is presented on lines 0,Os, forming an 8-bit word. Word addresses
are selected in the same manner as in the
Read mode. After each address and data
word is set up, one program pulse (Vp) is applied to the program input (pin 18J. Referto
the Program Mode timing diagram. A program loop is defined as one pass through all
device addresses. The number of loops (N)
required is dependent upon the program
pulse width (tpw) according to N* tPW 2:
100ms.

The 2708/2704 may be erased by exposure
to high intensity short-wave ultraviolet light
at a wavelength of 2537A2'. The recommended integrated dose (i.e., UV intensity x
exposure time) is 10W-sec/cm2. Examples
of ultraliiolet sources which can erase the
2708/2704 in 30 to 60 minutes are the Model
UVS-54 and Model S-52 short-wave ultraviolet lamps manufactured by Ultra-Violet
Products, Inc., 5114 Walnut Grove Avenue,
San Gabriel, California. The lamps should
be used without short-wave. filters, and the
2708/2704 to be erased should be placed
about 1 inch away from the lamp tubes. Both
Cervue and UV glass lids are available.

Program and read loops may be alternated
as shown in the Read/Program/Read Transitions timing diagram.

282

S[gnotics

:

!

2518-N .2519-N

DESCRIPTION

TRUTH TABLE

The 2518 32-bit and the 2519 40-bit recirculating static shift registers consist of enhancement mode p-channel silicon gate
MOS devices intergrated on a single monolithic chip. Internal recirculation logic plus
TTL/DTL level clock signals are provided
for maximum interfacing ease.

PIN CONFIGURATION

RECIRCULATE

INPUT

FUNCTION

1
1
0
0

0
1
0
1

Recirculate
Recirculate
"0" is written
"1" is written

N PACKAGE

Data is read out when output enable is low. Output is tristated when output enable is high.

BLOCK DIAGRAM

1----0 OUT,
IN,o--+--;-,

OUT2

=

IN,

0

OUT 3

IN,

E
W
E

...0

OUT4

IN,

E

OUTs
IN,

IN,

o--+-+-----Ir-"

1----0 OUT,

RECIRCULATE

ABSOLUTE MAXIMUM RATINGS1
PARAMETER

TA
TSTG
Po

Temperature range
Operating2
Storage
Power dissipation at TA = 70·C
Data and clOCk input voltages
and supply voltages with
respect to Vee

RATING

UNIT
·C

o to +70
-65 to 150
640
0.3 to -20

Sjgnotics

mW
V

283

III ;I~III ;IIIIIIIIIIIIII;IIII;III~
2518-N .2519-N

DC ELECTRICAL CHARACTERISTICS

TA = O°C to +70°C, VCC = +5V ± 5%, VGG = -12V
unless otherwise specified. 3,4,S;6,7

± 5%

LIMITS
PARAMETER

VIL
VIH
VILC
VIHC

Input voltageS
Low
High
Clock low
Clock high

VOL
VOH

Output voltage
Low
High

ILO
ILC

Leakage current
Output
Clock

III
IGG

Input load current
Supply current

CIN
C

Capacitance
Input
Clock

AC ELECTRICAL CHARACTERISTICS

TEST CONDITIONS

Min

Typ

Max

UNIT.
V

0.6
5.3
0.6
5.3

3.4
3.4

V
0.5

IOL= 1.6mA
IOH = 100ILA

3.8
nA

TA = 25°C
VILC = GND
VIN = -5.5V, TA = 25°C
Continuous operation,
TA = 25°C, f = 1.5MHz

10
10

1000
500

10
16

500
25

5
6

7
7

nA
mA
pF

At 1MHz, VAC = 25mV p-p
VIN=VCC
V=Vcc

TA = O°C to +70°C, VCC =,+5V ± 5%, VGG = -12V

± 5%, VILC = 0.4V to 4.0V

LIMITS
PARAMETER
Freq.

Clock rep rate

tpw
~pw

Pulse width
Clockl0
Clock

tos
tOH
tRS
tRH
tR,tF
tA

Setup and hold time
Setup time
Hold time
Setup time
Hold time
Clock pulse transition
Clock to data out delay

FROM

TO

Typ

Max

de

3

2

UNIT
MHz
ILS

.300
.200

100
de
ns

Clock in
Data in
Clock
Recirculate

Data in
Clock in
Recirculate
Clock

Data

Clock

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operati~n of the device at these or at any of this
specification is not implied.
2. For operating at elevated temperatures the device must be derated based on a 150°C maximum
junction temperature and a thermal resistance of 125°C elW, junction to ambient.

3. All inputs are protected against statiC charge.
4. Parameters are valid over operating temperature range unless specified.
5. All voltage measurements Bre referenced to ground.
S. Manufacturer reserves the right to make design and process changes and improvements.
7. Typical values are at +2S"C and typical supply voltages.
8. Guaranteed input levels are stated for worst case conditions including a ±5% variation in Vee and a
temperature variation of O°C to +70°C. Actual input requirements with respect to Vee are VIH = Vee
-1.SSVand V,L = Vee - 4.1SV.
9. VOL Is dependent on RL and input characteristics of driven gate.
10. Input rise and fall times = 10ns. Output load is 1 TTL gate.
11. For static operation, clock must be stopped in TTL high state in order to retain data (see clock pulse
width specification).

284

Min

SmootiDS

100
70
150
50
300

5
350

ILS

ns

2518-N • 2519-N

TIMING DIAGRAM

+5
CLOCK INPUT

+5----~
DATA IN

DAIAOUT

+5------------~--------~

=
o

RECIRCULATE

NOTES
A. Input rise and fall times

= IOns. Output load is 1 TTL gate.

B. For static operation. clock must be stopped in TTL high state in order to retain data

E!
w
E!

'-

o

E!

Si!lDotiCS

285

2509-N.K • 2510-N.K .2511-N.K

DESCRIPTION

TRUTH TABLE

The 2509 50-bit. 2510 100-bit. and the 2511
200-bit recirculating static shift registers
consist of enhancement mode p-channel
silicon gate MOS devices integrated on a
single monolithic chip. Internal recirculation logic plus TTLlDTL level clock signals
plus tri-state outputs are provided for maximum interfacing ease.

PIN CONFIGURATIONS

RECIRCULATE

INPUT

FUNCTION

0
0
1
1

0
1
0
1

Recirculate
Recirculate
"0" is written
"1" is written

"0"

N PACKAGE
RECIRCULATE

Vee

1

IN,

= OV; "1" = +5V.
VGG

BLOCK DIAGRAM

9

OUTPUT
ENABLE

8

PW
[4;PW

Pulse width
Clock
Clock

tos
tOH

Setup and hold time
Setup time
Hold time

0.6
S.3
0.6
S.3

3.8
3.6

3.S
nA
10
10

1000
SOO

6.S
12
20
4.S

1S
30
40
7.S

10

SOO

Continuous operation, TA = 2SoC, f = 1.SMHz

rnA

VIN=-S.SV, TA=2SoC
At 1MHz; V AC = 2SmV p-p
VIN =VCC
VOUT= VCC
V"'= Vcc

S
S
S

VCC = SV4, Voo = -SV
TA = O°C to 70°C.

± S%,

TO

TEST CONDITIONS

FROM

VILC = O.4V to 4V, VGG = -12V

Min
de
.290
.210

± S%,

LIMITS
Typ
3

Max

1S0

100
de

1.S

.pin
Data in

Data in
.pin

Data out

Clock

Select time
Deselect time

tR,tF

Clock pulse transition

UNIT
MHz
JLS

SO
70
ns
200

Data out

Output
enable

3S0
SOO
300
300
1

NOTES
1. Stresses above those listed under absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and fUnctional operation of thedevice
at these or at any other condition above those indicated in the operational sections of
this specification is not implied.
2. For operating at elevated temperatures, the device must be derated based on a 150°C
maximum junction temperature and a thermal resistance of 150°C/W.
3. All inputs are protected against static charge accumulation.

ns
ns
JLS

4. Guaranteed input levels are stated for worst case conditions including a ±5%variation
in Vee and a temperature variation of O°C to 70°C. Actual input requirements with
respect to Vee are V,H = Vee -1.S5V and V,L = Vee -4.15V.
5. Parameters are valid over operating temperature range unless otherwise specified.
6. All voltage measurements are referenced to ground.
7. Manufacturer reserves the right to make design and process changes and
improvements.
8. Typical values are at 25°C and typical supply voltages.

SmootiCS

r;
o
E
w

ns

IOL = 1.6mA

Tcs
TOE

nA
pF

Propagation delay
tA
tA

UNIT

O.S

TA = 2SoC
VCE = 1.0SV, VOUT = -SV
VILC = GND

AC ELECTRICAL CHARACTERISTICS
PARAMETER

Max

V
IOL = 1.6mA
IOH = 100JLA

IGG
Input load current

LIMITS
Typ

3.4
-S
3.4

Leakage current
Output
Clock

III

± S%

V

Output voltage
Low
High
Driving MOS

Supply current
Dual SO
Dual 100
Dual 200

VGG = -12V

287

E
~

o
E

;;;1

IIIIIII~IIIIIII 111111111111111 11111;1

2509-N,K • 251O-N,K • 2511-N,K

TIMING DIAGRAM

+5
~IN

-I----I---+_ 'DH
+5------------~
DATA IN

50%

~----------

DATA OUT

+5--------------------+-------------~

0--------

RECIRCULATE

Ir=:~:

OUTPUT
ENABLE

__-

+5 - - - - ----y~_-_-_-_-_-_-_-_-

tR = tF < 10n8 for all inputs

TYPICAL APPLICATION
EXAMPLE FOR 4-BIT SHIFT REGISTER

I

BIT 1

DATA IN

RECIRCULATE

+:

WRITE CYCLE

I

BIT

21 BIT 31 BIT 4

I

RECIRCULATE CYCLE

BIT 1

I

BIT

21 BIT 31 BrT 4

I

READ/RECIRCULATE CYCLE

BIT 1

I

BIT

21 BIT 31 BIT 4

I

-FBiTl2ndBIT3rdBITI4th BITLI____________...;;D~O~N;.;O;.;T_C;.;A;.;R;,.;E__________- - - - -

+:-.J

OUTPUT
ENABLE

DATA OUT

:: __.a...__...;.;PR;,.;E;,;V.;,;IO;,;U;,;S;,.;D;,;A;,;T.;,;A__.....'1 •• BITL..::I-T~!J4Ih BIT

11t BIT'2ndBIT3rdBITF

2nd BIT

NOTES

A. Write Cycle: The positive going edge of the recirculate control is coincident with the negative-golng
clock edge. The output enable control may be either high or low. If it is high, previous data will be read,
and the 1st bit will be read after the fourth rising clock edge.
B. Recirculate Cycle: Data Recirculates while the recirculatecontro.1 is low. Output enable may be either
high or low. If it is low, the output is in the high Impedance state.
C. Read/Recirculate Cycle: Data Is read out while the output enable is high. Data is also recirculated as
long as the recirculate control is low.

288

QUAB 8D III SI'IIC SHIfT KEGISIEK (8uA4,
2532-N

DESCRIPTION
The 2532 static shift register consists of
enhancement mode p-channel silicon gate
MOS devices integrated on a single monolithic Chip. Each of the four aO-bit registers
is provided with an independent input,
push-pull output and recirculation control.
The Single phase clock is common to all 4
registers. All inputs and outputs including
the clock interface directly with TTL or DTL
circuits without external components.

logic high, data recirculates and is continuously available at the output, data input is
inhibited. When the recirculate control is at
a logic low, data is entered.

PIN CONFIGURATION
N PACKAGE
VCC
RECIRCULATE 1

2

IN 4

TRUTH TABLE
RECIRCULATE

"0"

FUNCTION

INPUT

"0" is written
"1" is written
Recirculate
Recirculate

0
0
1
1

Data is entered when the clock is at a logiC
high. Data is shifted when the clock goes
low. When the recirculate control is at a

RECIRCULATE 4

0
1
0
1

OUT 2

OUT 4

RECIRCULATE 2

IN 2
IN3
V DO (GND)

8

L...-_---I

9

RECIRCULATE 3

= ov, "1" = +5V

BLOCK DIAGRAM
VCC

·,No-------------1
IN

=
o

CLOCK

GENERATOR

0-----1""""""
OUT

8O-BIT

E
w

REGISTER

REC

0-.......>.---1""""""

VDD

E

....o

ABSOLUTE MAXIMUM RATINGS1
PARAMETER

TA
TSTG
Po

Temperature range
Operating 2
Storage
Power dissipation at T A = 70· C
Data and clock input voltages and
supply voltages with respect to Vee

!itgDDtiC!i

RATING

o to 70
-65 to 150
640
+0.3 to -20

E

UNIT

·c
mW
V

289

2532-N

DC ELECTRICAL CHARACTERISTICS

TA = O°C to 70°C, VCC = 5V

PARAMETER

± 5%,

VGG = -12V

± 5%

LIMITS

TEST CONDITIONS
Min

VIL
VIH
VILC
VIHC

Input voltage3
Low
High
Clock low
Clock high

VOL
VOH

Output voltage
Low
High

unless otherwise specified.

Typ

UNIT
Max
V
0.6
5.3
0.6
5.3

3.4
3.4

V
IOL = 1.6mA
IOH = 100"A

0.5
3.8

Supply current

mA

IGG

6

Continous operation,
f = 1.5MHz, T A = 25° C, Outputs open

Icc
III
ILC

Input load current
Clock leakage current

CIN
C

Capacitance
Input
Clock

VIN - 5.5V, T A-25° C
VILC = av, TA = 25°C

PARAMETER
Freq.

Clock rep rate

tPW
t;,6pw

Pulse width
Clock
Clock

tR,tF

Clock pulse transition

tos
tOH
tRS
tRH

Setup and hold time
Setup time
Hold time
Setup time
Hold time

tA

Delay time

20

10
10

500
500

nA
nA
pF

5
5

TA = O°C to 70°C, VCC = 5V ± 5%, VGG = -12V ± 5%,
Input rise and fall times = 10ns, Output load = HTL gate

TO

FROM

LIMITS

TEST CONDITIONS
See timing diagram

Min
dc

Typ
3.0

UNIT
Max
1.5

MHz
"s

0.33
0.33

t/>in
Data in
t/>in
Recirculate

Data in
t/>in
Recirculate
t/>in

Data out

Clock

IOL= 1.6mA

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other

condition above those indicated in the operationals9ctions of this specification is not implied.
2. For operating at elevated temperatures the device must be derated based on a 150°C maximum
junction temperature and a thermal resistance of 125°CIW junction to ambient.

3. Guaranteed input levels are stated for worst CBse conditions including a ±5% variation in Vee and a
temperature variation of O°C to +70°C. Actual input requirements with respect to Vee are VIH = Vee
-1.85Vand V,L = Vee -4.15V.
4. All inputs are protected against static charge.
S. Parameters are valid over operating temperature range unless specified.
6. All voltage measurements are referenced to ground.
7. Manufacturer reserves the right to make design and process changes and improvements..
8. Typical values are al +25'C and typical supply vollages.

S!!I0otiCS

100
dc
5

"s
ns

400

ns

120
70
150
70

NOTES

290

12

At 1MHz, VAC = 25mV p-p
VIN=VCC
V= VCC

AC ELECTRICAL CHARACTERISTICS

10

-.~-.-----

---

----

2532-N

TIMING DIAGRAM
l-tdJPW~I""--I;jipW----"1

+5

I

I

~IN

I

'Ds-l--I-i-'DH
+5

:uxlr~""'\1

50%

DATA IN

0------'

+5
DATA OUT

I
I I
-II-'R
10%

I

I

50%

'----------

I
I-'A
:

'I

'v~3.0V----

0--------I------l~..0.;;.;4V----I

'RS-j-I-I-'RH
RECIRCULATE

NOTES

----:~~---------

o==

A. IR = tF IOns for all inputs.
B. Clock must be stopped in the TTL low state to retain data during static operation.

Ii
w
Ii

o
Ii

Si!l00liCS

291

2521

DUIIL 128 BIT SHHIC SHIFT REGISTER 02812)
OIiAL 132 BII SIAliC SHiEl REGISTER (13212)

2522
2521-N • 2522-N

DESCRIPTION
The 2521 128-bit and the 2522 132-bit recirculating static shift registers consist of enhancement mode p-channel silicon gate
MOS devices integrated on a single monolithic Chip.

TRUTH TABLE

PIN CONFIGURATION

RECIRCULATE

INPUT

FUNCTION

0
0
1

0
1
0
1

Recirculate
Recirculate
"0" is written
"1" is written

1 ..
"0"

~

ov,

"1"

~

N PACKAGE

o.
8

Vee

2

7

IN2

OUT1

3

6

OUT 2

VaG

4

5

¢IN

RECIRCULATE

IN,

+5V.

BLOCK DIAGRAM

N

~

128 for 2521, N

~

132 for 2522

ABSOLUTE MAXIMUM RATINGS1
PARAMETER

TA
TSTG

PD

292

Temperature range 2
Operating
Storage
Power diSSipation at T A = 70° C
Data and clock input voltages and
supply voltages with respect to Vee

smnntms

RATING

o to 70
-65 to 150
535
0,3 to -20

UNIT

°C

mW
V

DUAL 128 BIT STATIC SHIFT REGISTER (128X2)
DUAL 132 BIT blAIIC SHIEl REGISTER (13212)

2521

2522
2521-N • 2522-N

DC ELECTRICAL CHARACTERISTICS

TA = O°C to 70°C; VCC = 5V

PARAMETER

VIL
VIH
VILC
VIHC

Input voltage 3
Low
High
Clock low
Clock high

VOL
VOH

Output voltage
Low
High

III
ILC
IGG

Input load current
Clock leakage current
Supply current

CIN

CapaCitance
Input
Clock

C.p

Freq.

Clock rep rate

t in high
Recirculate
Fiecirculate  in high

Data



in high

75
70

.....

50
250

350

ns

o
E

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and fUnctional operation of the device at these or at any other
condition above those indicated in the operational sections of this specification is not implied.
2. For operating at elevated temperatures the device must be derated based on a +150°C maximum

junction temperature and a thermal resistance of 150°CIW junction to ambient.
3. Guaranteed input levels are stated for worst case conditions including a ±5% variation in Vee and a
temperature variation of 0° C to +70° C. Actual input requirements with respect to Vee are VIH=Vee1.85V and V,L = Vee - 4.15V.
4. All inputs are protected against static charge.
5. Parameters are valid over operating temperature range unless specified.
6. All voltage measurements are referenced to ground.
7. Manufacturer reserving the right to make design and process changes and improvements.
8. Typical values are at +25°C and typical supply voltages.

stgnl!tics

=
o

293

~
l

~ !i

!i

; !i

1

~

~

~

2521-N • 2522-N

TIMING DIAGRAM

j-tcbpw-I- t"¢pw-I
+5

1

1

I

I

/
/90%

1

/ ~I;";"""--"';;;J,

-I

I

'os -1-/-1- 'OH

~:rt""'\:
I

+5
DATA IN

50%

50%

o----~

~---------

I

I-'A

I

I

+5
DATA OUT

0- _______

'iiS

RECIRCULATE

J-'F

II

I-_____
I

·1

·1

I

\t~3.0V---J~.;.;0.4~V_ _ _ __

/'FiH

I

-_-_-_-_-~~Oo/~~ ________ _

NOTES
A. tR = tF < 10ns for all inputs.
B. For static operation, clock must be stopped in TTL high state in order to retain data (see clock pulse
width specification).

294

SjgOotiCS

DUAL 240 BIT STATIC SHIFT REGISTER (240X2)

lill
2527-N • 2528-N .2529-N

DESCRIPTION
The 2527 240-bit, 2528 250-bit, and the 2529
256-bit recirculating static shift registers
consist of enhancement mode p-channel
silicon gate MOS devices integrated on a
single monolithic chip.

TRUTH TABLE

DB

PIN CONFIGURATION

RECIRCULATE

INPUT

FUNCTION

0
0
1
1

0
1
0
1

Recirculate
Recirculate
"0" is written
"1" is written

N PACKAGE

RECIRCULATE

"0" ~ ov; "1·' ~ +5V

Vcc

2

7

IN2

OUT 1

3

6

OUT 2

VGG

4

5

'IN

IN,

BLOCK DIAGRAM
+Vcc

RECIRCULATE

1-------------------,
I

I
I

I
I

N·BIT REGISTER

I

IN,o--!--t--l_r-"1o'-

=
o

I

I
·,No-+--i----------j

N·BIT REGISTER

IN,o--t-t---L~

E
w

OUT 2

I
IL __________________ _

E

~

o

+Vcc
N

~

240 for 2527. N

~

250 for 2528. N ~ 256 for 2529

E

ABSOLUTE MAXIMUM RATINGS1
PARAMETER
TA
TSTG
Po

RATING

Temperature range 2
Operating
Storage
Power dissipation at TA = 70 0
Data and clock input voltages and
supply voltages with respect to Vee

e

Smnotics

UNIT

°C
Ot070
-65 to 150
535
0.3 to -20

mW
V

295

DUAL 240 BIT STATIC SIIIFf REGISTER (240X2)
DUnL 250 BIT STATIC SHIfT REGISTER (25012)
DIIAI 256 BIT STATIC SHIFT REGISTER (256X2)
DC ELECTRICAL CHARACTERISTICS

2527
2528

2529

2527-N • 2528-N • 2529-N
TA = 0° C to 70° C, Vcc = 5V ±5%, VGG = -12V ±5% unless otherwise specified.
LIMITS

PARAMETER

VIL
VIH
VILC
VIHC

Input voltage3
Low
High
Clock low
Clock high

VOL
VOH

Output voltage
Low
High

'll
ILC
IGG

Input load current
Clock leakage current
Supply current

CIN
C",

Capacitance
Input
Clock

TEST CONDITIONS

Freq.

Clock rep rate

t",pw
t¢"pw

Pulse width
Clock
Clock

tR.tF

Clock pulse transition

tDS
tDH

Setup and hold time
Setup time
Hold time

tRS
tRH

Setup time
Hold time

tA

Delay time

3.4

UNIT

V
IOL = 1.6mA
IOH = 100!-,A

0.5
3.8

VIN = 5.5V, TA = 25°C
VILC = OV, TA = 25°C
Continuous operation, T A = 25° C, f = 1.5MHz,
Outputs open

10
10
28

At 1MHz, VAC = 25mV p-p
VIN = VCC
V¢= Vcc

TO

500
500
35

nA
nA
mA
pF

5
5

TA = DOC to 70°C, Vcc = 5V ±5%, VGG = -12V +5%,
Input rise and fall times = 10ns, Output load = HTL gate.
FROM

LIMITS

TEST CONDITIONS
See timing diagram note

UNIT
Min

Typ

Max

dc

2.5

1.5

0.2
0.2

0.1

100
dc

MHz
!-'s

1

j.LS

ns
 25°C2
Data and clock input
voltages and supply
voltages with respect to Vcc

TA
TSTG
Po

RATING

UNIT

°C

o to 70
-65 to 150
535
0.3 to -20

mW
V

DC ELECTRICAL CHARACTERISTICS TA = O°C to 70°, Vcc = 5V ± 5%, VGG = -12V+ 5% unless otherwise specified.
LIMITS
PARAMETER

V,L
V,H
V,LC
V,HC

Input voltage3
Low
High
Clock low
Clock high

VOL
VOH

Output voltage
Low
High

ILl
ILC

Input load current
Clock leakage current

Icc
IGG
C'N
COUT
C

298

Supply current

Capacitance
Input
Output
Clock

TEST CONDITIONS

Min

Typ

Max

UNIT

V

Vcc =5V
0.6
5.3
0.6
5.3

3.4
3.4

V
IOL = 1.6mA
IOH = 100~
V,N = 0, TA = 25°C
V,LC = GND, TA = 25°C
Continuous operation, f = 1.5MHz

At 1MHz; VAC = 25mV pop
V,N = Vcc
VOUT= Vcc
V=Vcc

StgDotiCS

0.5
3.8
10
10

500
500

16
5.0

30
7.5

nA
nA
mA

pF
5
5
5

1024 BIT STATIC SIlIFI REGISTER

2533
2533-N

AC ELECTRICAL CHARACTERISTICS

TA = 25°C, Vee = 5V ± 5%, VGG = -12V ± 5%

LIMITS

PARAMETER

FROM

TO

tq,PW
t;PW
tR,tF
tow
tOH

Setup and hold time
Setup time
Hold time
Setup time
Hold time

tsss
tSSH

UNIT

Typ

Max

2

1.5

MHz

100
de
1

ns

.350
250

/JoS
/JoS

ns
Write
Clock

Data
Data

Stream select
Clock in
Clock in
Stream select

Delay time

tA

Min

See timing diagram

Clock and data rep rate
Pulse width
Clock
Clock
Clock pulse transition

TEST CONDITIONS

Data out

Clock

50
70
80
50
200

300

ns

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other
condition above those indicated in the operational sections of this specification is not implied.
2. For operating at elevated temperatures the device must be derated corresponding to a thermal
resistance'of 150°CIW junction to ambient.
3. Guaranteed input levels are stated for worst case conditions including a ±5% variation in Vee and a
temperature variation of 0° C to +70 0 C. Actual input requirements with respect to Vee are VIH = Vee1.B5V and VIL ~ Vee - 4.15V.
4. All inputs are protected against static charge.
5. Parameters are valid over operating temperature range unless specified.
6. All voltage measurements are referenced to ground.
7. Manufacturer reserves the right to make design and process changes and improvements.
8. Typical values are at +2S o C and typical supply voltages.

TIMING DIAGRAM

~

o
E
w
E

TEST LOAD CIRCUIT

+5V

+5V

CLOCK IN

o'"

..---------t~pw,--------~·~I



E

+5V----------------------~
DATA IN

Measure tA between device input and point (aJ. Gates
are standard 7400.

--~~-....*-tSSH
+5V--------------~

STREAM
SELECT

'-------------

Mn: _____________~~~------NOTES
A. Times measured at 50% points with input tR tF ~ 10ns.
8. Clock must be stopped in TTL low state to retain data during statiC mode operation.

Si!lDotiCS

299

2506 2507 2517

DIIAL 100 811 UINA.IC SHIFT REGISTER (100X2)

2506-T,N • 2507-T,N .2517-T,N

DESCRIPTION

BLOCK DIAGRAM.

These Signetics 2500 Series dual 100-bit
Dynamic Shift Registers consist of enhancement mode p-channel MaS devices
integrated on asinglemonolithic chip. They
use 2 clock phases.

IN1~

100 BITS

IN'2~

tOO BITS

PIN CONFIGURATIONS

1--[:>0--1--[:>0---

T PACKAGE
OUT 1

VDD

OUT 2

FEATURES
• 2506: Bare drain
• 2507:7.5K Pull down
• 2517: 20K Pull down

PARAMETER

TA
TSTG
Po

Temperature range
Operating
Storage
Power diSSipation at TA = 70°C2
T package
N package
Clock input voltages
with respect to Vee 3
Supply and data input voltages
with respect to Vee3

0
Vee

ABSOLUTE M.AXIM.UM. RATINGS1
RATING

N PACKAGE

UNIT

o to 70

°C

CLOCK
(01)
OUTPUT
OUTPUT 2

-65 to 150
mW
535
455
0.3 to -20

V

0.3 to-12

V

1

2

,

8

Vee

7

INPUT
CLOCK (0 2 )

INPUT 2

3

6

OUTPUT 1

Voo

4

5

INPUT 1

DC ELECTRICAL CHARACTERISTICS TA = O°C to 70°C, Voo = -5V ± 5%, Vee = 5V4, unless otherwise specified. 5•6•7,B
LIMITS
PARAMETER

VIL
VIH
VILe
VIHe

Input voltage9
Low
High
Clock low
Clock high

VOH1

Output voltage9
High (driving MaS)

VOH2
III

High (driving TTU
Load current
Input 1
Input 2

ILO

Leakage current10
Out 1
Out 2

ILe

300

Clock leakage current
1
2

100

VOD supply current

CIN
C

CapaCitance
Input (1 and 2)
Clock input (1,2)

TEST CONDITIONS

Min

Typ

1.05
5.3
-10
5.3

-5
3.2
-12
4
RINT = 7.5k typ, CL = 10pF, 2507 only
RINT = 20k typ, 2517 only
RL =3.3k, Voo = -5V, 2506 only
TA = 25°C
OUT 1, 1, 2 and Vee = 5V,
IN 2, OUT 2 and IN 1 = -5.5V, Voo = -4.5V
OUT 2, 1, 2 and Vee = 5V,
IN 1, OUTl and IN 2 = -5.5V, Voo = -4.5V
"""

TA= 25°C
IN 1, Vee, OUT 2 and 2 = 5V,
IN 2, Voo and OUT 1 = -5.5V,  1 = -5V
IN 1, OUT 1, Vee and 
l = -12V
V2 = -12V
Outputs at logic low or high
3MHz, 1 = 150ns, 2 = 100ns
1MHz, 25mV p-p
VIN = Vee
V = Vee

Gi!lDOliCG

Max

3.4

4.0

3.0

3.5

UNIT

V

V

nA
10

500

10

500

10

1000

10

1000

10
10

1000
1000

12

26

2.5
25

5
40

nA

nA

mA
pF

2506-T,N • 2507-T,N .2517-T,N

AC ELECTRICAL CHARACTERISTICS

TA

= 25°C,

VDD

= -5V ± 5%,

Vee

= 5V4,

VILe

= -11V
LIMITS

PARAMETER

FROM

TO

TEST CONDITIONS

Freq.

Clock rep rate
At 3MHz

1PW
2PW

Pulse width
Clock <1>1
Clock <1>2
Clock pulse delay
Clock pulse transition
Setup time
Data in overlap
Delay time

At 3MHz
At 3MHz

d
tR,tF
tw
too
tA+

Min

Typ

Max

.0006

4

3

UNIT
MHz
ns

150
100

<1>2

Data in

Data out

<1>1

V

tR02 = tR01 = 10ns
-16V, Data out

= Vee

10
10
75
10

= 2.5V

1000

90

150

ns
ns
ns
ns
ns

NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and fUnctional operation of the device at these or at any other
condition above those indicated in the operational sections of this specification is not implied.
2. For operating at elevated temperatures the device must be derated based on a +150°C maximum
junction temperature and a thermal resistance of 150°CIW (T package) or 175°CIW (V packageJ.
3. All inputs are protected against static charge.
4. Vee tolerance is±5%. Anyvariation in actual Vee will be tracked directly by VIL. VIH and VOHwhich are
stated for a Vee of exactly 5 volts.
5. Parameters are valid over operating temperature range unless otherwise specified.
6. All voltage meuurements are referenced to ground.
7. Manufacturer reserves the right to make design and process changes and improvements.
B. Typical values are at +25°C and typical supply voltages.
9. logic Convention: Data lines - Positive; Clocks -Negative.
10. VOL (for this bare drain device) is a function only of the driven gate characteristics
together with the external pull-down resistor. (Rpol.

=
o
E
w
E

TIMING DIAGRAM
2INPUT

U

+5V

u~::o

2Pw-I-1

1-160-1

'F

I

411 OUTPUT

-I

r::'i

1-

-11V

~

'R

o

+5V

1
1

I
'w-II-'Do-I

~,.'"~

E

-11V

1--1-·----FREQUENCY----

~~l

+5V

_-_'PW _ _ _ __
OV

I

-I I-'A+

.J!

DATA OUT _ _ _ _ _ _ _ _ _

\

SmnDtics

+5V

OV

301

2505-K • 2512-K

DESCRIPTION
The 2505 512-bit and the 2512 1024-bit recirculating dynamic shift registers consist
of enhancement mode p-channel MOS devices integrated on a single monolithic chip.
Internal recirculation logic plus write and
read controls, together with 2 chip select
controls are included on the chip.

TRUTH TABLE
WRITE READ
0
0
1
1

0
1
0
1

PIN CONFIGURATION
FUNCTION

Recirculate, Output is '0'
Recirculate, Output is data
Write mode, Output is '0'
Read/write, Output is data

K PACKAGE
VDD

SELECT 1

WAITE

READ

INPUT

OUTPUT

q, 2 INPUT CLOCK

BLOCK DIAGRAM
Vee

WRITE

READ

(W)

(R)

NOTES

A. N = 512 or 1024. Low = OV. High = +5V.
B. When 81 or 52 is low, data recirculates.
C. When S1 and S2 are high. see Truth Table.

ABSOLUTE MAXIMUM RATINGS1
PARAMETER
TA
TSTG
Po

302

Temperature range2
Operating
Storage
Power disSipation at TA > 70°C2
Data and clock input
voltages and supply
voltages with respect to Vee

RATING

o to 70
-65 to 150
535
0.3 to -20

G[gnotiCG

UNIT
°C

mW
V

~

5

j
2505-K • 2512-K

DC ELECTRICAL CHARACTERISTICS

TA = O°C to 70°C, Vcc = 5V

± 5%,

Voo = -5V

VOL
VOH1
VOH2

Output voltage
Low
High, driving 1 TTL load
High, driving MOS

UNIT

ILO
ILC

TA= 25°C
VpW= 150ns,1 MHz,
VILC=-12V.TA = 25°C, Voo=-5.5V

CIN
COUT
C

Capacitance
Input
Output
Clock

PARAMETER

tA+,tA-

Delay time

2.4
3.6

0.6 -5.0
5.3
3.4
-10.0 -12.0
5.3
4.0
-1.0
3.5
4.0

2.4
3.6

10

VIN = 5.5V, TA = 25°C

500

Max
0.6
5.3
-10.0
5.3

FROM

10

nA

500

10
10

1000
1000

10
10

1000
1000

15

25

25

35

mA
pF

5
5
50

TA = 25°C, Vcc = 5V3, Voo = -5V

TO

-1.0
3.5
4.0
nA

1 MHz, VAC = 25mV p-p
VI = Vcc
Vo = Vcc
V= Vce

AC ELECTRICAL CHARACTERISTICS

tow
tOH

Typ

V
RL = 3.0K, 1 TTL load IlL = 1.6mA)4
RL = 3.0K, 1 TTL load ilL = 1OOItA)
RL = 5.6K, CL = 10pF

Input load current

Setup and hold time
Setup time
Hold time

Min

V

Leakage current
Output
Clock

Clock
Clock
Clock
Clock

Max

Typ

-5.0
3.4
-12.0
4.0

III

Freq.
t'iii%O%

__11_ 'w-

I

L

I

-li-,cs-

~

I

I

I

I

OUTBIT'

'cs+--II--i1-'C9II;';"---i-\
I \'-._ _ _ _ __
~.

'R+::..j

2)

I- --II- 'R-

\'-______

NOTES
A. N = 512 lor the 2505, N = 1024 lor the 2512.
8. Note that the read input is ANO'ed with tP1: therefore this function is not valid until

304

q,1 occurs,

Si!lDotiCS

:::fU:liIIMltlWSI"a.tIM Iflllllll' flllk!)
2524-N • 2525-N

DESCRIPTION
The 2525 1024-bit recirculating dynamic
shift register consists of enhancement
mode p-channel MOSdevices integrated on
a single monolithic chip. Internal recirculation logic plus write and read controls are
included on the chip.

TRUTH TABLE
WRITE READ
0
0
1
1

0
1
0
1

PIN CONFIGURATION
FUNCTION

N PACKAGE

Recirculate, Output is '0'
Recirculate, Output is data
Write mode, Output is '0'
Read mode, Output is data

¢"NPUTOa vee
CLOCK
OUTPUT

2

READ
Y oo

7

<1>, OUTPUT
CLOCK

3

6

INPUT

4

5

WRITE

BLOCK DIAGRAM

N ~ 512 or .1024. Low ~ av. High

~

+5V

=
o

ABSOLUTE MAXIMUM RATINGS1
PARAMETER
TA
TSTG
PD

DC ELECTRICAL CHARACTERISTICS
PARAMETER

UNIT

RATING

Temperature range2
Operating
Storage
Power dissipation at T A > 70° C2
Data and clock input
voltages and supply
voltages with respect to Vcc

°C

o to 70
-65 to 150
535
0.3 to -20

E
w
E

mW
V

TA = O°C to 70°C, Vcc = 5V ± 5%, VDD = -5V ± 5% unless otherwise specified.
TEST CONDITIONS

Min

2524
Typ

Max

Min

2525
Typ

Max

UNIT
V

VIL
VIH
VILC
VIHC

Input voltage3
Low
High
Clock low
Clock high

VOL
VOH1
VOH2

Output voltage
Low, driving 1 TTL load
High, driving 1 TTL load
High, driving MOS

III

Input load current

ILO
ILC

Leakage current
Output
Clock

TA = 25°C
V1>2 = V1>1 = -12V, VDD = -5, VOUT = -5.5V
VILC = -12V

IDD

Supply current

Continuous operation, pW = 150ns,
f = 1MHz, VILC = -12V, TA = 25°C,
VDD= -5.5V

CIN
COUT
C'"

Capacitance
Input
Output
Clock

0.6 -5.0
5.3
3.4
-10.0 -12.0
5.3
4.0

-5.0
3.4
-12.0
4.0

0.6
5.3
-10.0
5.3
V

RL = 3.0K, 1 TTL load IlL = 1.6mA)4
RL = 3.0K, 1 TTL load IlL = lOOILA)
RL = 5.6K, CL = 10pF
VIN = -5.5V, TA = 25°C

1MHz, VAC = 25mV p-p
VI = Vcc
Vo = Vcc
V =Vcc

SmnOliCS

2.4
3.6

-1.0
3.5
4.0

2.4
3.6

-1.0
3.5
4.0

10

500

10

500

10
10

1000
1000

10
10

1000
1000

15

35

25

35

nA
nA

mA

pF
5
5
80

5
5
160

305

....o
E

2524

512 BII REGlRGlJLATlNB DYNAMIC SHIFT REGISHR(512XI)
1024 BIT RECIRCUUHING DYNAMICSIIIFT REGISTER (1024Xl)

2525
2524-N • 2525-N

AC ELECTRICAL CHARACTERISTICS

TA = 25°C, Vee = 5V ± 5%, Voo = -5V ± 5%, VILe = -11V,
Input rise and fall times = 10ns, Output load = 1 TTL gate
TO

PARAMETER
Freq.
t1

l1 occurs.

Smnotics

ns
ns
ns

~

~ !i

~ !

~

i

2502-N • 2503-TA,N .2504-TA,N

DESCRIPTION

PIN CONFIGURATIONS

These 2500 Series 1024-bit multiplexed dynamic shift reg isters consist of enhancement mode p-channel MOS devices integrated on a single monolithic chip. Due to
on-chip multiplexing, the data rate is twice
the clock rate.

2502

2503

N PACKAGE

N PACKAGE

QUT'OS

Vee

IN2

2

7

<111

4>2

3

6

IN,

Voo

4

5 'OUT,

OUTPUT BUFFER

2504
TA PACKAGE
Vee

2503
TA PACKAGE
Vee

=
o

Vee

2504
N PACKAGE

QU.TOS

E
w
E

Vee

$2

2

7

Ne

He

3

6

$,

Voo

4

5

IN

...o

ABSOLUTE MAXIMUM RATINGS1
PARAMETER

TA
TSTG
PD

Temperature range 2
Operating
Storage
Power dissipation TA = 70°C2
TA and N (8-pin) package
N (16-pin) package
Data and clock input
voltages and supply
voltages with respect to Vcc 3

Smnotics

RATING

o to 70

UNIT

°C

-65 to 150
mW
535
640
0.3 to -20

V

E

1024 BIT MULTIPLEXED DYNAMIC SHIH REGISTER (256X4)
1024 BIT MULTIPLEXED DYNAMIC SHIFT REGISTER (512X2)
1IJ24 BII MIIIIIPI EIEIl U'NAMIC SHIFT RFGISlFR (10241))

2502

2503
2504
2S02-N • 2S03-TA,N .2S04-TA,N

DC ELECTRICAL CHARACTERISTICS

TA

= O°C to 70°C, VOO = -5V ± S%, Vcc = 5V4 unless otherwise specified5,6,7,8

PARAMETER

VIL
VIH
VILC
VIHC

Input voltage
Low
High
Clock low
Clock high

VOL
VOH1
VOH2

Output voltage
Low
High, driving MOS
High, driving TTL

III

Input load current

ILO
ILC

Leakage current
Output
Clock

100

Supply current

CIN
COUT
C
0- 1- - - -1

I

I

;
I

I

IctrlPW-I-:1
II
¢2CLOCK

I

90%-1 --

tI
-90%
~I t@olI
1
l-r-=-=-+--CLOCKRATE-I

:

II
II

!

I

0

10%

;::
~

"

1...I

tDW-}-:

!

/

u;

90%

1:

I~l

I:

:__ I t 
..-

DATA
OUTl

J>-+-4...J.-.c

OUT 2

}O-r---"""-l-vel 2 Qualification
* = In process

LOGIC-5400 SERIES (Cont'd)
JAN
QUAL

:.:

JAN
MIL
PRoeESSED REL/883

:.:

()

DEVICE
54161
54162
54163
54164
54165
54166
54170
54174
54175
54180
54181
54182
54190
54191
54192
54193
54194
54195
54198
54199
54221
54279
54298
54365
54366
54367
54368

DESCRIPTION
Synchronous 4-Bit Binary
Counter
Synchronous 4-Bit Decade
Counter
Synchronous 4-Bit Binary
Counter
8-Bit Parallel-Out Serial
Shift Register
Parallel-Load 8-Bit Shift
Register
8-Bit Shift Register
4X4 Register File
Hex D-Type Flip-Flop
with Clear
Quad D-Type Edge-Triggered
Flip-Flop
8-Bit OddlEven Parity Checker
4-Bit Arithmetic Logic Unit
Look-Ahead Carry Generator
Synchronous UplDown Counter
(BCD)
Synchronous UplDown Counter
(Binary)
Synchronous Decade UplDown
Counter
Synchronous 4-Bit Binary
UplDown Counter
4-Bit Bidirectional Universal
Shift Register
4-Bit Parallel-Access Shift
Register
8-Bit Sh ift Reg ister
8-Bit Shift Register
Dual Monostable Multivibrator
Quad S-R Latch
Quad 2-lnput Mux with Storage
Hex Buffer w/Common Enable
(3-State)
Hex Buffer w/Common Enable
(3-State)
Hex Buffer, 4-Bit and 2-Bit
(3-State)
Hex Buffer, 4-Bit and 2-Bit
(3-State)

JM38510
SLASH
SHEET

a.

0

«a.
l«
....I

t5«

()

a.

LL.

0

«a.
I«....I

a.

LL.

0

....I

a.

I-

«

LL.

101306

1

1

F

W

F

W

101305

1

1

F

W

F

W

101304

1

1

F

W

F

W

100903

1

-

F

-

F

W
W
-

100904

*
-

101801
101701

-

·

-

F

W

-

-

-

F
F
F

1

1

F

W

F

W

101702

1

1

F

W

F

W

101901
101101
101102

-

2

1
1

1

F
I
F

F
I
F

W
W

-

-

-

-

W
W
-

-

-

-

-

-

. .
. .

F

W

F

W

F

W

F

W

F

W

F

W

F

W

F

W

-

-

· ·
·
· ·
· ·

101308
101309

*

100905
100906
-

-

-

-

-

/16301
/16302
/16303
/16304

-

-

*

Q

-

-

-

F
F
F

W
W
W

*

*

F

W

F

W

F

W

-

· · ·
· · ·
· · · ·
· · · ·
*

I

-

NOTE
Per QPL 38510-28 dated 1 Apr. 1977
1 = Levell Qualification
2 = Level 2 Qualification
* = In process

S!!IDI!tiCS

319

LOGIC-S4H SERIES
JAN
QUAL

"AN
MIL
PROCESSED REL/883
lII:

lII:

DEVICE
54HOO
54H01
54H04
54H05
54H08
54H10
54H11
54H20
54H21
54H22
54H30
54H40
54H50
54H51
54H52
54H53
54H54
54H55
54H60
54H61
54H62
54H71
54H72
54H73
54H74
54H76
54H101
54H102
54H103
54H106
54H108

DESCRIPTION
Quad 2-lnput NAND Gate
Quad 2-lnput NAND Gate
with ole
Hex Inverter
Hex Inverter with ole
Quad 2-lnput AND Gate
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate
Dual 4-lnput NAND Gate
Dual 4-lnput AND Gate
Dual 4-lnput NAND Gate
with ole
8-lnput NAND Gate
Dual 4-lnput NAND Buffer
Expandable Dual 2-Wide
2-lnput A01
Dual 2-Wide 2-lnput A01 Gate
Expandable 4-Wide 2-2-2-3
Input AND-OR Gate
4-Wide 2-lnput A01 Gate
(Expandable)
4-Wide 2-lnput A01 Gate
2-Wide 2-lnput A01 Gate
Dual 4-lnput Expander
Triple 3-lnput Expander
3-2-2-3 Input AND-OR
Expander
J-K Master-Slave Flip-Flop
with AND-OR Inputs
J-K Master-Slave Flip-Flop
Dual J-K Master-Slave
Flip-Flop
Dual D-Type Edge-Triggered
Flip-Flop
Dual J-K Master-Slave
Flip-Flop
J-K Negative Edge-Triggered
Flip-Flop
J-K Negative Edge-Triggered
Flip-Flop
Dual J-K Negative EdgeTriggered Flip-Flop
Dual J-K Negative EdgeTriggered Flip-Flop
Dual J-K Negative EdgeTriggered Flip-Flop

JM38510
SLASH
SHEET
/02304

102306
102305

-

115501
102303
115502
102302
115503
102307
102301
102401
104001
104002

(.)

(.)

CC

CC

a.
a.

is

~

...I
II..

CC

a.
a.

is

a.

~
...I

a.

II..

is

II..

W
W

I-

~

1
1

1
1

F
F

W
W

F
F

1

1

F

W

1

-

F

W

F
F
F
F
F
F
F
F

W
W
W
W
W
W
W
W

1
1
1

1
1
1

F
F
F

W
W
W

F
F
F

W
W
W

- - - 2 F 1
1 F W
2 F 1
1 F W
2 F -

1

F

W

-

- - -

F
F

W
W

104003

1

1

F

W

F

W

104004
104005

1
1

1
1
-

F
F

W
W

-

F
F
F
F
F

W
W
W
W
W

-

-

1

- - -

-

-

-

F

W

102201
102202

1
1

1
1

F
F

W
W

F
F

W
W

102203

1

1

F

W

F

W

102204

1

1

F

W

F

W

102205

1

1

F

W

F

W

- - - -

F

W

1

F

W

F

W

F

-

-

102206

-

1

F

W

- - - - - - -

NOTE
Per QPL 38510-28 dated 1 April 1977.
1 = level 1 Qualification
2 = Level 2 Qualification

320

lII:

(.)

Sjgnotics

LOGIC-54LS SERIES
JAN
QUAL

JAN
MIL
PROCESSED REL/883

loI::

loI::

U

DEVICE
54LSOO
54LS01
54LS02
54LS03
54LS04
54LS05
54LS08
54LS09
54LS10
54LS11
54LS12
54LS13
54LS14
54LS15
54LS20
54LS21
54LS22
54LS26
54LS27
54LS28
54LS30
54LS32
54LS33
54LS37
54LS38
54LS40
54LS42
54LS51
54LS54
54LS55
54LS73
54LS74
54LS75
54LS76
54LS78
54LS83A
54LS85
54LS86
54LS90
54LS92
54LS93
54LS95
54LS96

DESCRIPTION
Quad 2-lnput NAND Gate
Quad 2-lnput NAND Gate
with o/c
Quad 2-lnput NOR Gate
Quad 2-lnput NAND Gate
with o/c
Hex Inverter
Hex I nverter with o/c
Quad 2-lnput AND Gate
Quad 2-lnput AND Gate
with o/c
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate
with o/c
Dual NAND Schmitt Trigger
Hex Schmitt Trigger
Triple 3-lnput AND Gate
with o/c
Dual 4-lnput NAND Gate
Dual 4-lnput AND Gate
Dual 4-lnput NAND Gate
with o/c
Quad 2-lnput NAND Gate
with o/c
Triple 3-lnput NOR Gate
Quad 2-lnput NOR Buffer
8-lnput NAND Gate
Quad 2-lnput OR Gate
Quad 2-lnput NOR Buffer
with o/c
Quad 2-lnput NAND Buffer
Quad 2-lnput NAND Buffer
with o/c
Dual 4-lnput NAND Buffer
BCD-to-Decimal Decoder
Dual 2-Wide 2-lnput A01 Gate
4-Wide 2-lnput A01 Gate
2-Wide 4-1 nput A01 Gate
Dual J-K Master-Slave
Flip-Flop
Dual D-Type Edge-Triggered
Flip-Flop
Quad Bistable Latch
Dual J-K Master-Slave
Flip-Flop
Quad Bistable Latch
4-Bit Binary Full Adder
4-Bit Magnitude Comparator
Quad 2-lnput Exclusive-OR
Gate
Decade Counter
Divide-by-Twelve Counter
4-Bit Binary Counter
4-Bit Left-Right Shift
Register
5-Bit Shift Register

JM38510
SLASH
SHEET

0..

i5

«0..
I«
....I
LL

loI::

U

U

«0..

0..

i5

~

....I

LL

0..

i5

«
Do.
I«
....I
LL

130001
-

-

-

F
F

W
W

F
F

W
W

130301
130002

2
1

2
1

F
F

W
W

F
F

W
W

130003
130004
131004
-

1

1
1
2

F
F
F

-

- -

W
W
W

-

F
F
F
F

W
W
W
W

130005
131001
130006

1
2
1

1
2
1

F
F
F

W
W
W

F
F
F

W
W
W

131301
131302
131002

·· ··

2

2

F
F
F

W
W
W

F
F
F

W
W
W

130007
131003
130008

1
2
1

2
1

F
F
F

W
W
W

F
F
F

W
W
W

F

W

F

W

F
F
F
F

W
W
W
W

W
W
W
W
W

132101

2

1
2

2

1

· ·
· ·
2

2

-

2
2

2
2

-

-

-

-

F
F
F
F
F

130202
130203

2

2

F
F

W
W

F
F

W
W

130201
130703
103401
130402

2

2

F

W

2
2

2
2

F
F

W
W

-

F
F
F
F
F
F

W
W
W
W
W
W

F

W

F

W

F
F

W
W

F
F

W
W

-

-

F
F
F

W
W
W

F
F
F
F

W
W
W
W

F
F
F
F

W
W
W
W

F
F
F
F

W
W
W
W

F

W

F

W

130302
130204
130009
130501

-

130101
130102

130110

131201
131101
130502
131501
131510
131502
130603
130604

· ·
· · . .

- - - - -

·
·
··
·
···
·
·

·
·
···
···
·

·

Smnotics

-

NOTE
Per QPL 38510-28 dated I April 1977.
1 = Level 1 Qualification
2 = Level 2 Qualification

321

LOGIC-54LS SERIES (Cont'd)
JAN
QUAL

JAN
MIL
PROCESSED REL/883

lie:

DeVICE

54LS107
54LS109
54LSl12
54LSl13
54LSl14
54LS122
54LS125
54LS126
54LS132
54LS136
54LS138
54LS139
54LS145
54LS151
54LS153
54LS154
54LS155
54LS157
54LS158
54LS160
54LS161
54LS162
54LS163
54LS164
54LS170
54LS173
54LS174
54LS175
54LS181
54LS190
54LS191

DESCRIPTION

Dual J-K Master-Slave
Flip-Flop
Dual. J-K Positive EdgeTriggered Flip-Flop
Dual J-K Negative EdgeTriggered Flip-Flop
Dual J-K Negative EdgeTriggered Flip-Flop
Dual J-K Negative EdgeTriggered Flip-Flop
Retriggerable Monostable
Multivibrator
Quad Bus Buffer Gate
w/Tri-State Outputs
Quad Bus Buffer Gate
wlTri-State Outputs
Quad Schmitt Trigger
Quad Exclusive-OR with olc
3-to-8 Line Decoder/Demux
Dual 2-to-4 Line Decoderl
Demux
BCD to Decimal DecoderlDye
8-Line to 1-Line Mux
Dual 4-Line to 1-Line Mux
4-Line to 16-Line Decoderl
Demux
Dual 2-Line to 4-Line
Decoder/Demux
Quad 2-lnput Data Selector
(non-inv)
Quad 2-lnput Data Selector
(invJ
Synchronous 4-Bit Decade
Counter
Synchronous 4-Bit Binary
Counter
Synchronous 4-Bit Decade
Counter
Synchronous 4-Bit Binary
Counter
8-Bit Parallel-Out Serial
Shift Register
4X4 Register File
Quad D-Type Flip-Flop
(Tri-State) (8T1 Q)
Hex D-Type Flip-Flop
with Clear
Quad D-Type Edge-Triggered
Flip-Flop
4-Bit Arithmetic Logic Unit
Synchronous UplDown Counter
(BCD)
Synchronous UplDown Counter
(Binary)

JM38510
SLASH
SHEET

130108
130109
130103
130104
130105
131403
132301
132302
131303

-

ec

DlD-

is

ec
....I

u..

· ·
· ·
· ·
· ·
· ·
-

-

· ·
· ·
·
- -·
·· ··

CJ

:

ID-

ec

I-

D-

u..

is

u..

F

W

F

W

F

W

F

W

F

W

F

W

F

W

F

W

F

W

F

W

-

-

-

-

F

W

F

W

F
F
F
F

W
W
W
W

· ·
· ·
F

W

-

·· ··
- .
·· -·· · ·

-

-

-

·
·
·
·
·
·
·

·
·
· · ·

/30701
130702

-

/30901
130902

130903
130904
131503
131504
/31511
131512
130605

/30106
/30107
/03801
131513
131509

-

-

-

·
-

-

· ·

· ·
· ·
· ·
2

....I

.

-

-

F

W

F

W

F

W

-

-

I

Q

-

-

F

W

F

W

F

W

F

W

F

W

F

W

F

W

F

W

F

W

F

W

· · ·
· · ·

·

ec

is

....I

F

W

F

W

-

-

F
F

W
W

F

W

F

W

F

W

F

W

I
F

-

I
F

Q

W

F

W

F

W

- -

NOTE
Per QPl 38510-28 dated 1 April 1977.

1 = Level 1 Qualification
2 = level 2 Qualification

322

lie:

~
ec
D-

CJ

S!!IDotICS

W

LOGIC-54LSSERIES (Cont'd)
JAN
QUAL

JAN
MIL
PROCESSED REL/883

!II:

!II:

~

Q

<
.a..
<
-'

DEVICE

54LS192
54LS193
54LS194
54LS195
54LS196
54LS197
54LS221
54LS251
54LS253
54LS257
54LS258
54LS260
54LS261
54LS266
54LS279
54LS280
54LS283
54LS290
54LS293
54LS295A
54LS298
54LS365
54LS366
54LS367
54LS368
54LS375
54LS386
54LS395
54LS445
54LS670

DESCRIPTION

Synchronous Decade UplDown
Counter
Synchronous 4-Bit Binary
UplDown Counter
4-Bit Bidirectional Universal
Shift Register
4-Bit Parallel-Access Shift
Register
Presettable Decade Counterl
Latch (8290)
Presettable Binary Counterl
Latch (8291)
Dual Monostable Multivibrator
Data Selector/Mux with
3-State Outputs
Dual 4-Line to 1-Line Data
Selector/Mux
Quad 2-Line to 1-Line Data
Selector/Mux
Quad 2-Line to 1-Line Data
Selector/Mux
Dual 5-lnput NOR Gate
2X4 Parallel Binary Multiplier
Quad Exclusive-NOR Gate
Quad S-R Latch
9-Bit OddlEven Parity
GeneratorlChecker
4-Bit Adder
Decade Counter
4-Bit Binary Counter
4-Bit Right-Shift Left-Shift
Register
Quad 2-lnput Mux with Storage
Hex Buffer w/Common Enable
(3-5tate)
Hex Buffer w/Common Enable
(3-State)
Hex Buffer, 4-Bit and 2-Bit
(3-State)
Hex Buffer, 4-Bit and 2-Bit
(3-5tate)
Quad Latch
Exclusive-OR Gate
4-Bit Cascadeable Shift
Register (3-State)
BCD to Decimal DecoderlDye
4X4 Register File ITri-State)

*

F

*

*

130601

*

*

130602

*

.*

131601

· ·

a..

Q

II.

131507

*

131508

131602
131402
130905
130908
130906
130907

130303
131202
132003
132004
130606

132201
132202
132203
132204

130607

-

!;(
-'

· ·
·· ··

· ·

...

CJ

<
a..

.a..

Q

5

W

F

W

F

W

F

W

*

*

*

*

a..

II.

II.

· · ·
· · · ·
· · · ·
·· ·· · ··
·
*

F

W

· ·
· · · ·
F

W

- - - - - - 2 F W
2
- - - - - - -

··
··
·
·
·
·

!II:

CJ

CJ

JM38510
SLASH
SHEET

·· ·
·· ·
- · ·
· ·
· ·
· ·
F
F

·
·

W
W

-

·

·
·
·

- - - - - - -

· · · ·

- - - - - - -

F

W

F

W

F

W

F
F
F
F

W
W
W
W

F
F
F
F

W
W
W
W

F
F

W
W

F

W

F

W

F

W

F
F
F

W
W
W

F
F

W
W

· ·

NOTE
Per OPL 38510-28 dated 1 April 1977.
1 = Level 1 Qualification
2 = Level 2 Qualification

!i~nDtiC!i

323

LOGIC-54S SERIES
JAN
QUAL

JAN
MIL
PROCESSED REL/883
~

~

0

DEVICE
54800
54802
54803
54804
54805
54808
54809
54810
54811
54815
54820
54822
54830
54832
54840
54851
54864
54865
54874
54885
54886
548112
548113
548114
548133
548134
548135
548138
548139
548140
548151
548153
548157
548158
548174
548175
548181
548182
548194
548195

324

DESCRIPTION
Quad 2-lnput NAND Gate
Quad 2-lnput NOR Gate
Quad 2-lnput NAND Gate
with olc
Hex Inverter
Hex I nverter with olc
Quad 2-lnput AND Gate
Quad 2-lnput AND Gate
with olc
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate
Triple 3-lnput AND Gate
with olc
Dual 4-lnput NAND Gate
Dual 4-lnput NAND Gate
with olc
8-lnput NAND Gate
Quad 2-lnput OR Gate
Dual 4-lnput NAND Buffer
Dual 2-Wide 2-lnput
A01 Gate
4-2-3-2 Input A01 Gate
4-2-3-2 Input A01 Gate
Dual D-Type Edge-Triggered
Flip-Flop
4-Bit Magnitude Comparator
Quad 2-lnput Exclusive-OR Gate
Dual J-K Negative EdgeTriggered Flip-Flop
Dual J-K Negative EdgeTriggered Flip-Flop
Dual J-K Negative EdgeTriggered Flip-Flop
13-lnput NAND Gate
12-lnput NAND Gate wITri8tate Outputs
Quad Exclusive-OR/NOR Gate
3-to-8 Line DecoderlDemux
Dual 2-to-4 Line Decoderl
Demux
Dual 4-lnput NAND Line Driver
8-Line to 1-Line Mux
Dual 4-Line to 1-Line Mux
Quad 2-lnput Data 8elector
(non.inv.l
Quad 2-lnput Data 8elector
(inv.l
Hex D-Type Flip-Flop with
Clear
Quad D-Type Edge-Triggered
Flip-Flop
4-Bit Arithmetic Logic Unit
Look-Ahead Carry Generator
4-Bit Bidirectional Universal
8hift Register
4-Bit Parallel-Access 8hift
Register

~

0

c(

0

c(

JM38510
SLASH
SHEET

Q

Ii.

Q

107001
107301
107002

1
2
2

1
2
2

F
F
F

107003
107004
108003
108004

1
1

1
1

-

107005
/08001
108002

0-

c(

0-

l-

0-

I0-

!;;c

Q

Ii.

W
W
W

F
F
F

W
W
W

F
F
F

W
W
W

-

-

-

F
F
F
F

W
W
W
W

2
2
2

2
2
2

F
F
F

W
W
W

F
F
F

W
W
W

107006
107007

2
1

2
1

F
F

W
W

F
F

W
W

107008

-

-

-

-

-

-

/07201
/07401

2
2

2
2

F
F

W
W

F
F
F

W
W
W

107402
107403
/07101

2
2
2

2
2
2

F
F
F

W
W
W

F
F
F

W
W
W

F
F
F

W
W

F

W

F

W
W
W

0-

c(
...I

· .

0-

c(
...I

Ii.

-

-

...I

/08201
/07501
/07102

·

-

2

2

F
F

-

-

-

/07103

-

-

-

/07104

-

-

-

W
-

107009
107010

2
2

2
2

F
F

W
W

F
F

107502
107701
107702

-

-

-

- -

-

-

-

-

-

108101
107901
107902
107903

2
2
2
2

2
2
2
2

-

-

-

F

W

F
F
F
F

W
W
W
W

F
F
F
F

W
W
W
W

F

W

F

W

·
·
··

-

-

107904

· .

107106

-

-

-

-

107105

-

-

-

107801
107802
107601

·

-

-

-

-

-

107602

-

-

-

-

·
·
·
-

-

-

-

-

I

s~nDtics

I

NOTE
Per QPL 38510-28 dated 1 April 1977.
1 == Level 1 Qualification
2 = Level 2 Qualification

LOGIC-54S SERIES

(Cont'd)
JAN
QUAL

JAN
MIL
PROCESSED REL/883

~

~

(J

DEVICE

DESCRIPTION

548251

Data Selector/Mux with 3-5tate
Outputs
Dual 4-Line to 1-Line Data
Selector/Mux
Quad 2-Line to 1-Line Data
Selector/Mux
Quad 2-Lint to 1-Line Data
Selector/Mux
Dual 5-lnput NOR Gate
9-Bit Odd/Even Parity
Generator/Checker
4/6 Bit Shifter-Tri-State

54S253
548257
54S258
548260
54S280
54S350

JM38510
SLASH
SHEET

108905

107906
/07907

/07703

-

::
11-

Q

!c
..I
II-

~

(J

(J

::

::

I-

11-

Q

:5II-

- - - - - - - - - - - - - - - - - - - -

11-

Q

!c

..I
II-

- F

W

-

-

F

W

-

- F -

NOTE

Per QPL 38510-28 dated 1 Apr. 1977
1 = Level 1 Qualification
2 = Level 2 Qualification

SjgDotiCS

325

LOGIC-8200/9300/9600 SERIES
JAN
QUALIFIED'
DEVICE

DESCRIPTION

8200
8201
8202
8203
8230
8231
8232
8233
8234
8235
8241
8242
8243
8250
8251
8252
8260
8261
8262
8263
8264
8266
8267
8268
8269
8270
8271
8273
8274
8275
8276
8277
8280
8281
8284
8285
8288
8290
8291
8292
8293
9300
9301
9308
9309
9310
9312
9316
9322
9324
9334
9602

Dual 5-Bit Buffer Register
Dual 5-Bit Buffer Register with D Inputs
10-Bit Buffer Register
10-Bit Buffer Register with D Inputs
8-lnput Digital Multiplexer
8-lnput Digital Multiplexer
8-lnput Digital Multiplexer
2-lnput 4-Bit Digital Multiplexer
2-lnput 4-Bit Digital Multiplexer
2-lnput 4-Bit Digital Multiplexer
Quad Exclusive-OR Gate
Quad Exclusive-NOR Gate
8-Bit Position Scaler
Binary-to-Octal Decoder
BCD-to-Decimal Decoder
BCD-to-Decimal Decoder
Arithmetic Logic Unit
Fast Carry Extender
9-Bit Parity Generator and Checker
3-lnput 4-Bit Digital Multiplexer
3-lnput 4-Bit Digital Multiplexer
2-lnput 4-Bit Digital Multiplexer
2-lnput 4-Bit Digital Multiplexer
Gated Full Adder
4-Bit Comparator
4-Bit Shift Register
4-Bit Shift Register
10-Bit Serial-In. Parallel-Out Shift Register
10-Bit Parallel-In. Serial-Out Shift Register
Quad Bistable Latch
8-Bit Serial Shift Register
Dual 8-Bit Shift Register
Presettable Decade Counter
Presettable Binary Counter
Binary UplDown Counter
Decade Up/Down Counter
Divide-by-Twelve Counter
Presettable High Speed Decade Counter
Presettable High Speed Binary Counter
Presettable Low Power Decade Counter
Presettable Low Power Binary Counter
4-Bit Shift Register
BCD to Decimal Decoder
Dual 4-Bit Latch wlClear
Dual 4-lnput Multiplexer
4-Bit Decade Counter
8-lnput Digital Multiplexer
4-Bit Binary Counter
Data Selector-Multiplexer
5-Bit Comparator
8-Bit Addressable Latch
Dual Monostable Multivibrator

JM38510
SLASH
SHEET

-

-

-

101402

Flat
Pack

-

-

-

-

*

*

-

-

-

-

-

-

-

-

-

-

-

-

115901
115206
-

115002
116001
-

Per QPL 38510-28 dated 1 Apr. 1977

1 = Level 1 Qualification
2 = Level 2 Qualification

S~nl!tics

-

-

-

-

-

-

-

-

2
2
2

2
2
2

F
F
F

W
W
W

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

*
2

*
2

-

I

-

I

-

101402

-

W

-

-

101404

-

-

F

-

115204
115205
115206

-

-

-

-

-

-

Flat
Pack

-

-

-

Dip

-

-

NOTE

326

Dip

JAN
PROCESSED

*

*

-

-

-

-

*

*

*

*

-

-

-

-

-

-

-

-

-

-

-

-

-

F
F

W
W

F
-

-

F

W

W

-

-

F

WF

-

-

F

W

MIL
REL/883
MIL TEMP
Dip
I
I
I
I
F
F
F
F
F
F
F
F
I
F
F
F
I
F
F
I
I
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
I
F
F
F
F
F
W
F
F

Flat
Pack
Q
Q
Q
Q
W
W
W
W
W
W
W
W
Q
W
W
W
Q
W
W
Q
Q
W
W
Q
W
W
W
W
W
W

W
W
W
W
W
W
W
W
W
W
W
Q
W
W
W
W
W

W
W

LOGIC-8T INTERFACE SERIES

DEVICE

8T04
8T05
8T06
8T09
8T10
8T13
8T14
8T18
8T20
8T22
8T26A
8T28
8T31
8T32
8T33
8T35
8T37
8T38
8T80
8T90
8T95
8T96
8T97
8T98

DESCRIPTION

7-Segment Decoder Display Driver (Active-Low Outputs)
7-SegmentDecoder Display Driver (Active-Hi Outputs)
7-Segment Decoder Display Driver (Active-Low Outputs)
Quad Bus Driver with Tri-State Outputs
Quad 0-Type Bus Latch (Tri-State)
Dual Line Driver
Triple Line Receiver/Schmitt Trigger
Dual 2-lnput NAND (High Voltage to TTL Interface)
Bidirectional Monostable Multivibrator (Diff. Input)
Retriggerable Monostable Multivibrator (54122/9601)
Quad Bus Driver/Receiver (Tri-State Outputs)
Quad Non-Invertinll Bus Driver/Receiver (Tri-State Outputs)
8-Bit Bidirectional I/O Port
Programmable 8-Bit, 1/0 Port (3-State)
Programmable 8-Bit, 1/0 Port (Open Collector)
Asynchronous Programmable 8-Bit 1/0 Port (Open Collector)
Hex Bus Receiver with Hysteresis-Schmitt Trigger (DM8837)
Quad Bus Transceiver (Open Collector) (DM8838)
Quad 2-lnput NAND Gate (High Voltage)
Hex Inverter (High Voltage)
High Speed Hex Buffersllnverters (74365/DM8095)
High Speed Hex Buffers/Inverters (74366/DM8096)
High Speed Hex Buffers/Inverters (74367/DM8097)
High Speed Hex Buffersllnverters (74368/DM8098)

JAN
M3851 0
SHEET

-

:-

-

MIL REL/883
MIL TEMP
Dip

Flat
Pack

F
F
F
F
F
F
F
F

W
W
W
W
W
W
W

.
.
F

F
F

I
I
I
F
F
F
F
F
F
F
F

W

·

W
W
W

···

·

W
W
W
W
W
W
W
W

.. = Qualification planned

9i!1DOtiG9

327

LINEAR INDUSTRY CROSS REFERENCE
DEVICE··

DESCRIPTION

SE521
SE526
SE521
SE529
LH2111
LM111
LM119
LM139
LM193/193A
!4A710
!4A711

COMPARATORS
Dual Comparator
Analog Voltage Comparator
Analog Voltage Compa'rator
Analog Voltage Comparator
Dual Comparator
Comparator
Dual Comparator
Quad Comparator
Dual Comparator
Differential Voltage Comparator
Comparator

SE510
SE511
SE515
p.A733

DIFFERENTIAL AMPUFIERS
Dual Diffe~ential Amplifier
Dual Differential Amplifier
Differential Amplifier
Video Amplifier

LF155/156
LH2101A
LH~108A

LM101
LM101A
LM107
LM108
LM108A
LM124
LM158
MC1556
MC1558
SE532
SE535
SE538
!4A709
p.A709A
p.A741
!4A747
!4A748

328

OPERATIONAL AMPLIFIERS
FET OpAmp
Dual Op Amp
Dual Op Amp
High Perf. Op Amp
High Perf.Op Amp
General Purpose Op Ainp
Precision Op Amp
Precision Op Amp
Quad Op Amp
Dual Op Amp
OpAmp
,
DualOpAmp
DualOpAmp
Hi Slew Rate Op Amp
Hi Slew Rate Op Amp
OpAmp
OpAmp
General Purpose Op Amp
Dual Op Amp
General Purpose Op Amp

PACKAGE

F
F

F
F
F
F
F
F

K
K
K

T
K

F
F

T
T
K

F
F
F
F

K
K

T
F
F
F
F
F
F
F
F

T
T
F
T
T

-

T
T
T
T

T
T
F
F
F
F
F

T
T
T
K
T

F
F

DEVICE

DESCRIPTION

PACKAGE

SE567.

PHASE LOCKED LOOPS
Tone Decoder P11

F

DM7820
DM7830

LINE RECEIVERS
Dual Differential Line Receiver
Dual Differential Line Receiver

F
F

SE555
SE556
SE558/9

TIMERS
Timer
Dual Timer
Quad Timer

F
F
F

,LM109
SE5554
78XX (7)
79XX (7)
79MXX (7)
p.A723

VOLTAGE REGULATORS
5 Volt Regulator
Dual Track Reg
Positive Reg
~egative Reg
Med Power Reg
Precision Voltage Regulator

DA
F
DA
DA
DB
F

DS1611-1614

DRIVERS
Peripheral Drivers

MC1508-8
SE5008
SE5009

D/A
8-Bit D/A
8-Bit D/A
8-Bit D/A

T

T

L
T

F
F
F

PAeRAGEI

GjgDotiCG

329

330

Smnotics

PJu;KURES

INTRODUCTION
The following information applies to all
packages unless otherwise specified on
individual package outline drawings.

General
1. Dimensions shown are metric units (millimeters), except those in parentheses
which are English units (inches).
2. Lead spacing shall be measured within
this zone.
a. Shoulder and lead tip dimensions
are to centerline of leads.

3. Tolerances non-cumulative
4. Thermal resistance values are determined by utilizing the lineartemperature
dependence of the forward voltage drop
across the substrate diode in a digital
device to monitor the junction temperature rise during known power application across vee and ground. The values
are based upon 120 mils square die for
plastic packages and a 90 mils square die
in the smallest available cavity for hermetic packages. All units were solder
mounted to p.e. boards, with standard
stand-off, for measurement.

Plastic Only
5. Lead material: Alloy 42 or equivalent,
solder dipped.
6. Body material: Plastic
7. Round hole in top corner denotes lead
No.1.
8. Body dimensions do not include molding flash.

Hermetic Only
9. Lead material

PLASTIC PACKAGES

NO. OF

DESCRIPTION1

LEADS
Standard Dual-in-Line
8
NE
14
NH
16
NJ
18
NK
20
NL
22
NM
24
NN
28
NO
40
NW3

162/65
150/65
137/53
135/53
135/53
120/53
116/53
116/53
110/50

Power Dual-in-Line
NHA2
14
NJA2
16
NKA2,3
18
NLN,3
20
NNA2
24
28
NON

95/33
95/33
90/26
90/26
60/23
56/21

Butterfly
Butterfly
Butterfly
Butterfly
Butterfly
Butterfly

Power
3
3
3 + GND
4 + GND
12 + GND

200nO
75/3
95/15
95/15
95/15

TO-92
TO-220
Single-in-Line (SIL)
Single-in-Line (SIL)
Batwing

S
U
GB3
GO
PH/PHA3

TO-116/MO-001
MO-001

MO-015
MO-015
MO-015

PAGE

3
3
3
3
3
3
4
4

4

3
3

3
3

4
4
5

5
5
5
5

12.Signetics symbol. angle cut, or lead tab
denotes Lead NO.1.
13.Recommended minimum offset before
lead bend.
14. Maximum glass climb .010 inches.
15.Maximum glass climb or lid skew is .010
inches.
16. Typical four places.
17. Dimension also applies to seating plane.

a.Alloy 52-gold plated, or solder dipped.
b.ASTM alloy F-15 (KOVAR) or equivalentgold plated, tin plated, or solder dipped.
c.ASTM alloy F-30 (Alloy 42) or equivalenttin plated.
d.ASTM alloy F-15 (KOVAR) or equivalentgold plated.
e.ASTM alloy F-15 (KOVAR) or equivalenttin plated.

10. Body Material
a.l0l0 Steel-nickel plated or tin plate over
nickel.
b. Eyelet, ASTM alloy F-15 or equivalent-gold
or tin plated.
c. Eyelet, ASTM alloy F-15 orequivalent-gold
or tin plated, glass body.
d.Ceramic with glass seal at leads.
e. BeO ceramic with glass seal at leads.
f. Ceramic with ASTM alloy F-15 or equivalent.

11. Lid Material
a.l0l0 steel, nickel plated. or tin-plate over
nickel, weld seal.
b.Nickel or tin plated nickel, weld seal.
c. Ceramic. glass seal.
d.ASTM alloy F-15 or equivalent, gold plated.
e.BeO Ceramic with glass seal.
f. Translucent A1 2 0 3 , glass seal.

smootiCS

331

pnCKnGES
HERMETIC PACKAGES
NO. OF
LEADS

PACKAGE
Sjal S jc (oC/W)
CODE

DESCRIPTION1

PAGE

Metal Headers
2
3
4
4
8
10
10

DA
DB
DC
DE
T
K
L

TBD
TBD
TBD
TBD
150/25
150/25
150/25

TO-3 Solid Header
TO-39 Solid Header. Short Can
TO-72 Solid Header
TO-72 Glass Filled Header
TO-99 Header (,200 Dia,)
TO-100 Header, Short Can
TO-100 Header, Tall Can

6
6
6
6
7
7
7

Flat Packs
10
14
16
24
16
18
24
28
40
10
14
16
24
10
14
16
24

WF
WH
WJ
WN
RJ/RJA
RKA3
RNA
ROA
RWA
OF
OH
OJ
ON
OFA
OHA
OJA
ONA

240/50
205/50
200/50
155/40
133/30
TBD
TBD
TBD
TBD
230/55
185/45
170/45
155/44
230/55
185/45
170/45
155/44

Flat
Flat
Flat
Flat
Flat
Flat
Flat
Flat
Flat
Flat
Flat
Flat
Flat
Flat
Flat
Flat
Flat

8
8
8
8
8

Cerdip Family
14
16
18
22
24

FH
FJ
FK
FM
FN

110/30
100/30
93/27
75/27
60/26

Dual in-Line
Dual-in-Line
Dual-in-Line
Dual-in-Line
DuaHn-Line

Laminated Ceramic, Side Brazed Lead
lEA
100/30
8
14
95125
IHA
16
IJA
90/25
IKA
18
88/25
22
IMA
80/25
24
INC/IND
65125
28
lOA
60/25
40
IWA
55/25
50
IZA
TBD

Dip
Dip
Dip
Dip
Dip
Dip
Dip
Dip
Dip

Ceramic
Ceramic
Ceramic
Ceramic
Ceramic, BeO
Ceramic, BeO
Ceramic, BeO
Ceramic, BeO
Ceramic, BeO
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic Laminate
Ceramic Laminate
Ceramic Laminate
Ceramic Laminate
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic

11
11
11
11
11
12
12
12
12
12
12
13
13
13

Laminate
Laminate
Laminate
Laminate
Laminate
Laminate
Laminate
Laminate
Laminate

NOTES

1.

Dual-in-Line packages unless otherwise described
Package outline is the same as corresponding standard Dual-in-Line package with identical number
of leads
3. Package not yet available, scheduled for 1977 release
2,

332

8
9
9
9
9
9
9
10
10
10
10

SmDotiCS

PLASTIC: Standard and Power Dual-In-Line

U

NE Package

NH Package and NHA Package
lEAD NO. 1

LEAD ND. 1

o

[!]

01

o

:::t::
J

I. OS",.

9.271.31161

.1

1.32(0521
1.121.044)

NJ Package and NJA Package

NK Package and NKA Package

r-LEADNO.1

[!]

N L Package and N LA Package

NM Package

si!lDoliDS

333

PLASTIC: Standard and Power Dual-In-Line (cont'd.)

NN Package and NNA Package

NO Package and NOA Package

NW Package

Package not yet available
Scheduled for 1977 release

334

S(gOOtiCS

PLASTIC: Power (Not Dual-In-Line)

S Package

U Package
1:4 5.21 (.205IDIA. ~ I

&r.-n4.441.1751

3.06~

2Ji4(.1aoj

~+=-y RATIOOP~N'
0 0 IIlJ'
!

12.71JI MIN.

--'---==r='-'\L--'L-_ _ _-'! !.!!!~)I
~MAX~

/ 3 L.EADS

!:!!,1.1101
2.281.0101

.48 (.0191
Al (.01SI

'~~.g!

-r~t

2.671.1051
U1 (.085)

I
• -----'--.;-1-++,.

....

-1!- 7.&"12xIREF
1

jj~

1

e

~
~
t-----'t
~

-I-f--'-'--.l...i.+

SEATING PlANE - '........

.181,0301

~::::..,

x
x

(.1151

un"',

J~.)

~~

.30(.0121

NOTE: 1. LEAD MATERIAL - COPftER. NICKEL PLATED. SOLDER DIPPED •
t.056)

1.141.045}

...-+..........:+4I----

ooTPUT

COMMON
2.67(.1061
4044(.0801

2.671.1051
2.031.0801

GB Package

GC Package

Package not yet available
Schedu led for 1977 release

Package not yet available
Scheduled for 1977 release

PH/PHA Package

PH

NOTE: 1. FRAME MATERIALCOPPER. SILVER PLATED.

PH
PH

!ii!lDDIiG!i

335

HERMETIC: Metal Headers

DA Package

DB Package
\.22.23 (0.8751 MAX. DIA.i

.Q
'
·
l
F -t
9.02(.3&6)

8.28(.32B1

370l

L .... '. '.IDIA.. j --rl.'~

- ' - - - flU3~

riL.l~___

"'II-'-I_ _ _ _

--'-'~~~~

~

~1.03OIr-

7.93 (.3121 MIN.

os,

i

iiiCiiii

0 0---=t::

U201 3LEADSAJ
(1.48(.0191

U,(Jiii)

3.01 (.115) DIA

-.
r ......nat

........

4.78 (.111S) R. MAX.

Pint-Input

PIn 2 - Output

ca.e

11.18 (MOl

-Ground

8.8& {.0341

10.87 jA2i1

ii:iit:iiii)

2 MOUNTING
HOLES

TERMINAL CONNECTIONS
PIN 1-INPUT
PIN 2 - OUTPUT
CASE - GROUND
PtNNO.l
CONSTRUCTION NOTES: III. ,Oa, " .

2 PINS

~

t:::

~:: ~:~: DIA.

CONSTRUCTION NOTES: Ib, lllb. llb

OIA.

DC Package

DE Package

.,A.

DIA.

H~::::::,

r*i ::~~:"'I

!~ -.
I

. .1~
r
&.33 (.210)

5.33 1.210)

i.32 (.1701

j

---.£:

nn
".22ft·""'1 n
UUU}

12.70 1.500)

_5.64 1.230)

0.78 {.0301
MAX.

71ll

".22~_ nUnUnU}•- '

•

LEADS

'2.70

~~.I

f.iiiiii

LEADS

0A8 (.Otl)

DAll.OtB)

_5.84 (.23OJ

5.ii'i:2iM

5".311.2<»1

DIA.

DIA.

CONSTRUCTION NOTES: lb. lOb, llb

336

---.£: 0.781._
MAX.

CONSTRUCTION NOTES: lib. lOCI. 11b

IjgRDliCS

1ii1 f.iiil

HERMETIC·• Metal Headers (cont'd.)

T Package

K Package

I__

1_ ~:~~;: -I

-1- .

OlA

-1-

W.l:~:;:~ r~:::~:
-1-

-

~

(.325)

8.00

i31si DIA.

~ US5)
4.19

--I

~

LOlC}

[0.51 COlm

C'-S51

1I___ ;-c:::;:;:;:;::;:;::;::;;;:;:::!J -

r~

0.38 (.0151
(.045) INSULATOR

I
14.28 (,562)

14.28 1.562)
12.70 C.600)

-

I

DO 0 00

,.1,0451

[38 LOIS) INSULATOR
~t.OI91

(1411.016) DlA.

12.70 (.500)

10 LEADS

j

~ 1.019)

0.41 (.016) DIA.
_ _ 9.40 {.37,o)

9.02 1.355) OIA. ___

S LEADS
_~('370)

9.02 (.J55) D I A , - -

1

5.33 C2l0}

~j'-'__--A-'---"-

4.831.'

CONSTRUCTION NOTES: 9b, IOc, lIb

L Package

I

1_ _

~(·3251

8.00.:,.-;;01A·-1

~
6.91 1.236)

f~
0,6\ (.020)

(.255)

I
I

(.030)

I

~1.5621

12.111.5001

1.14 (.045)

r~ ,.,'"""""

0~ 0 nu0

~ ::~~::OIA.
10 LEADS

____ 9.40 (.370)
9.02 (.355) DIA. ______

CONSTRUCTION NOTES: 9b.1Oc.l1b

337

HERMETIC: Flat Packs

WH Package

WF Package

m

0.131.0061 MIN

~ I!!l LEAD NO.1

0.51 1.020)

~I

rr-

!:!!!.(~

1.141.(45)

~~I[JI~;b3~: . f"\: ~:~!: ~
L'!,!!'·019,
0.38 f.Ol&1

7.87 {.3l0}

7.24(.2861

~ 1.280)

-.-1

I

I

~ 5.97'.2361~

1 - - - - - - 21.14(.860)-------;...
21.34(.840)

---I r--

±1

@]

-±--:==7E1
t~) II ==~~~
J L

CONSTRUCTION NOTES: ge. lad,lle

0.08 (.003)

~ ~ 0.78 1.030)
~

1.02 '.!MO)
0.51 (.020)

~ (.086,

1.40 (.055)

CONSTRUCTION NOTES: ge, lOd, 11c

WN Package

WJ Package
---1

fi!I

LEAD NO. 1

D.51 1.0201

!

[!]

!:!! I:!!!I

0.51 (.020)

'.14(.045)

jlt[.~~3a14~]'.1~
8.84(.340)

-L

lO.48 (.019)

8.40(.370)

0.381.015)

8.381.3301

8.22 (.245)

[H]1r-

MIN

~

L_~~~I~~I
~~~±~
l~.....
I
0.08'.0031

--i ~o.78I.03011!!1

o:3iic:01i)

L
....t

::~:---------l

.GOOMIN

0.41 loOtS)

[ill

I

t!!9.<.!!!!---+-!O!!(.21&·-I

t
I!!J

...

I

9.40(.310)

6.991.2751

w(:33i1

i:22(:zii,

1-------:::=-------1

~:~j l~~

1

lo.1

CONSTRUCTION NOTES: Be, 1Od, 111:

~r= 0.161.0301

I

6 1.0061
0.081.0031

0.10(.0041 MIN

~

----1.1
----...1-

2.181.0861

t '·40t'""'
1.0Z(.040)

ii:51{.0201
CONSTRUCTION NOTES: 9II.1Od,11c

RJ and RJA Package

RNA Package
---l

r.:;,

I!l

1.521.0601

~j..l,·. ·
alD
't
CLEADNO.18

I

1.02(:0401

9.401.3701

~-

-L

MIN

14.22 1.&801

~ ffiiT.iiOJ

t0A81.0191

O.3B{.015)

RJA.131.0051

9 .401.3701

_1_7.'S1f.290I_,

i3i1:i3iiI----r-W(.256)---J

I

.,N I-_______ :::~~-------I.

15.88(.826)

:J-IT

0.64 (.Q26)

iL2i{:ii1ii,

381.015)

~1 ~IDCONFIOURATIONFORRJON~

L.~~~I~~I;;;;~~~
1i:::::
-11--0.761.0301 rw
~(~J [!:!!I~)
L!!.I

RJA CONSTRUCTION NOTE&. 9e, lOe. 11e
Ad CONSTRUCTION NOTES: 9d. 10e. lld

0.611.0201

1.27(.050)

~
8.38(.3301

10.161.4001
11.141.380)

I
---4

I--------=:~:::-------I

~"t. .

0.101.0D41

338

I
--+--

Smnotics

1ID1 r
I

o. " ' -

j
2.1.UEJ
1.271.G15OJ

f

HERMETIC: Flat Packs (cont'd.)

ROA Package
0.51 (.020) -

-4lJ

RWA Package

/!§]

0.51 (.020) - -

J

1.52(0001 j
1.02(.040)

IT!
~

-----0

1,6.76 (.660)

~Iill

11111[111111

'52[.06011.
~

116.261,6401

1.021.040)

15.BatS2S)
14.99(.590\

r

12]

.

0.48(.019)

~

0.38(.0151

24.38 (.960)
23.88 {.940}

15.88 {.625}

15.09 \.5941

i

0.48 (.019)
0.38(.015)

0.15 (.008)

"'1'04)

1~

~O.76('0301§]

I

2.16 (.085)
1.27 {.050)

IIJ 111111111

I

=t
t

15.88 (.625)
I
15.09 {.594l---------+j

\.-- .9.40 1.370)
8.38(.330)

I.

1.02(.040)
0.511.020)

~----------------------~~~:~~5:~~:~~~~:----------~

1 r-§l

CONSTRUCTION NOTES: ie, Hie, 118

j

I

I

t

0.15,.006)
0.10 \.004)

1.02 (.040)
0.51 (.020)

OH Package

OF Package

r

10.38

0.48 (.019) TYP
(.015)
.

=-

'2

DJ

L
3:'005)

1.27\.050\

I

CONSTRUCTION NOTES: 9c.l0e, 118

MIN

2.16 (.085)

t:=G1l

0.76 (.0301---1

t

-

~

r--!cE

--I

@l

f--

I

L

04S1019}

=F~(015}

L

!,4!!(055}
1.14Ul45J

.t('!l

0.13
U)OS)
MIN

0.5.1 !.020)

t_7'.7 (.310)
f.24 (.285)

~ 1.006)

I
I

~

1.91 (.075)
W(.OSO)

0.51 r.0201

-+-

660 (260)
6.iO (.240)
21.84 (.860)
21.34 (.840)

--I

'50}
'30(

2}
0.31 (.01

~

0.76(.0301

I :J:
l~1.O2.}

J

--lI I~~
-

I --..l II----

0.10(.004)

[II

J

7.75 (.305)
7.49 (.295)

t

6'' )

~(.031)

0.76 t030} MIN.

1~{'055)
1.14 (.045)

(3]

t0

0.31 (.al2)

I

- - 0.51 (.020)

1

0.97 (.038) ~

21.84 1.860)
21.34 '.8401

@]

6.60 (. 260}
240)

L

t310lL
1.260}
7.37 (.290)
6.10 (.240)

l~t-

I
j

--oj

LEAD NO. 1

1.91 (.075)
1.27 (.050)

0.79 (.0311

@]

0:51 /.020)

CONSTRUCTION NOTES: 9d, lOcI. 11c
CONSTRUCTION NOTES: 9d, lCd, 11c.

ON Package

OJ Package
LEiNO.'I~

[!] 0.51 (.020)

0.51(.020}_

1-0
If

L@I

~ : : : : TYP. [!]

II

.J ".J.",,}

13.72 (.540)
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,345

SIGNETICS
HEADQUARTERS
811 East Arques Avenue
Sunnyvale, California 94066
Phone: (408) 739·7700 .
ALABAMA
Huntsville
Phone: (205) 534·5671
ARIZONA
Phoenix
Phone: (602) 971-2517
CALIFORNIA
Inglewood
Phone: (213) 670·1101
Irvine
Phone: (714) 833·8980

(213) 924-1668

San Diego
Phone: (714) 560·0242
Sunnyvale
Phone: (408) 736·7565
COLORADO
Parker
Phone: (303) 841-3274
FLORIDA
Pompano Beach
Phone: (305) 782-8225
ILLINOIS
Rolling Meadows
Phone: (312) 259·8300
INDIANA
Noblesville
Phone (317) 773·6770
KANSAS
Wichita
Phone: (316) 683·5652
MARYLAND
Columbia
Phone: (3011 730·8100
MASSACHUSETTS
Woburn
Phone: (617) 933-8450
MINNESOTA
Edina
Phone: (612) 835-7455
NEW JERSEY
Cherry Hill
Phone: (609) 665·5071
Piscataway
Phone: (201) 981·0123
NEW YORK
Wa~PingerS Falls
hone: (914) 297-4074
Woodbury, LI.
Phone: (516) 364-9100

346

OHIO

MARYLAND

WASHINGTON

Worthington
Phone: (614) 888·7143

Glen Burni
Microcom8' Inc.
Phone: (3 1) 761·4600

Bellevue
Western Technical Sales
Phone: (206) 641·3900

TEXAS

MASSACHUSETTS

Dallas
Phone: (214) 661·1296

WISCONSIN

Reading
Kanan Associates
Phone: (617) 944·8484

REPRESENTATIVES

MICHIGAN

CALIFORNIA

Bloomfield Hills
Enco Marketing
Phone: (313) 642·0203

San Diego
Mesa En;ineering
Phone: ( 14) 278·8021

MINNESOTA

Sherman Oaks
Astralonics
Phone: (213) 990·5903

Edina
Mel Foster Tech. Assoc.
Phone: (612) 835·2254

CANADA

NEW JERSEY

Cal~a!1' Alberta

Haddonfield
Thomas Assoc. Inc.
Phone: (609) 854·3011

P ihps Electronics Industries ltd.
Phone: (403) 243·2710

Montreal, Quebec
Philips Electronics Industries Ltd.
Phone: (514) 342·9180
Ottawa, Ontario
Phillips Electronics Industries ltd.
Phone: (613) 237·3131
Scarborough, Ontario
Philips Electronics Industries ltd.
Phone: (416) 292·5161
Vancouver, B.C.
Philips Electronics Industries ltd.
Phone: (604) 435-4411
COLORADO
Denver
Barnhill Five, Inc.
Phone: (303) 426·0222
CONNECTICUT
Newtown
Kanan Associates
Phone: (203) 426·8157

NEW MEXICO
Albuquerque
The Staley Company, Inc.
Phone: (505) 821·4310/11
NEW YORK
Ithaca
Bob Dean, Inc.
Phone: (607) 272·2187

Altamonte Springs
Semtronic Associates
Phone: (305) 831-8233
Largo
Semtronic Associates
Phone: (813) 586·1404
ILLINOIS
Chicago
L·Tec Inc.
Phone: (312) 286·1500

DISTRIBUTORS
ALABAMA
Huntsville
Hamilton! Avnet Electronics
Phone: (205) 533·1170
ARIZONA
Phoenix
Hamilton! Avnet Electronics
Phone: (602) 275·7851
Uberty Electronics
Phone: (602) 257·1272
CALIFORNIA
Costa Mesa
Avnet Electronics
Phone: (714) 754·6111
Schweber Electronics
Phone: (213) 537-4320

NORTH CAROLINA

Culver City
Hamilton Electro Sales
Phone: (213) 558·2173

Cary
Montgomery Marketing
Phone: (919) 467·6319

EI Segundo
Uberty Electronics
Phone: (213) 322-8100

OHIO

Mountain View
Elmar Electronics
Phone: (415) 961-3611

Centerville
Norm Case Associates
Phone: (513) 433·0966
Fairview Park
Norm Case Associates
Phone: (216) 333·4120
OREGON

FLORIDA

Greenfield
L·Tec,lnc.
Phone: (414) 545·8900

Portland
Western Technical Sales
Phone: (503) 297·1711
TEXAS
Austin
Cunningham Co.
Phone: (512) 459·8947
Dallas
Cunn ingham Co.
Phone: (214) 233-4303
Houston
Cunningham Company
Phone: (713) 461-4197

INDIANA

UTAH

Indianapolis
Enco Marketing
Phone: (317) 546·5511

West Bountiful
Barnhill Five, Inc.
Phone: (80l) 292·8991

SI!IDOtiCS

Hamilton! Avnet Electronics
Phone: (415) 961·7000
San Diego
Hamilton! Avnet Electronics
Phone: (714) 279·2421
Uberty Electronics
Phone: (714) 565·9171
Sunnyvale
Intermark Electronics
Phone: (408) 738·1111
CANADA
Downsview, Ontario
Cesco Electronics
Phone: (416) 661·0220
Mississauga, Ontario
Hamilton! Avnet Electronics
Phone: (416) 677·7432
Montreal, Quebec
Cesco Electronics
Phone: (514) 735·5511
Zentronics ltd.
Phone: (514) 735·5361

Ottawa, Ontario
Cesco Electronics
Phone: (613) 729-5118
Hamilton! Avnet Electronics
Phone: (613) 226-1700
Zentronics ltd_
Phone: (613) 238-6411
Toronto, Ontario
Zentronics ltd_
Phone: (416) 789-5111
Vancouver, B.C.
Bowtek Electronics Coo, ltd_
Phone: (604) 736-1141
Ville St. Laurent, Quebec
Hamilton! Avnet Electronics
Phone: (514) 331-6443
COLORADO
Commerce City .
Elmar Electronics
Phone: (303) 287-9611
Denver
Hamilton! Avnet Electronics
Phone: (303) 534-1212
Lakewood Acacia Sales
Phone: (303) 232-2882
CONNECTICUT
Danbury
Schweber Electronics
Phone: (203) 792-3500
Georgetown
Hamilton! Avnet Electronics
Phone: (203) 762-0361
Hamden
Arrow Electronics
Phone: (203) 248,3801
FLORIDA

Ft. Lauderdale

Arrow Electronics
Phone: (305) 776-7790
Hamilton! Avnet Electronics
Phone: (305) 971-2900
Hollywood
Schweber Electronics
Phone: (305) 922-4506
Orlando
Hammond Electronics
Phone: (305) 241-6601
GEORGIA
Atlanta
Schweber Electronics
Phone: (404) 449-9170
Norcross
Hamilton! Avnet Electronics
Phone: (404) 448-0800

ILLINOIS

MISSOURI

Elk Grove
Schweber Electronics.
Phone: (312) 593-2740
Elmhurst
Semiconductor Specialists
Phone: (312) 279-1000
Schiller Park
Hamilton! Avnet Electronics
Phone: (312) 671-6082

Hazelwood
Hamilton! Avnet Electronics
Phone: (314) 731-1144

Albuquerque
Hamilton! Avnet Electronics
Phone: (505) 765-1500

INDIANA

NEW YORK

Indianapolis
Semiconductor SpeCialists
Phone: (317) 243-8271
KANSAS
Lenexa
Hamilton! Avnet Electronics
Phone: (913) 888-8900
MARYLAND
Baltimore
Arrow Electronics
Phone: (301l 247-5200
Gaithersburg
Pioneer Washington Electronics
Phone: (301)948-0710
Hanover
Hamilton! Avnet Electronics
Phone: (301l796-5000
Rockville
Schweber Electronics
Phone: (301)881-2970
MASSACHUSETTS
Waltham
Schweber Electronics
Phone: (617)890-8484
Woburn
Arrow Electronics
Phone: (617) 933-8130
Hamilton! Avnet Electronics
Phone: (6m 933-8000
MICHIGAN
Livonia
Hamilton! Avnet Electronics
Phone: (313) 522-4700
Troy
Schweber Electronics
Phone: (313) 583-9242
MINNESOTA
Eden Prairie
Schweber Electronics
Phone: (612) 941-5280
Edina
Hamilton! Avnet Electronics
Phone: (612) 941-3801
Minneapolis
Semiconductor Specialists
Phone: (612) 854-8841

NEW MEXICO

Buffalo
Summit Distributors
Phone: (716)884-3450
East Syracuse
Hamilton! Avnet Electronics
Phone: (315) 437-2642
Farmingdale, LI.
Arrow Electronics
Phone: (516) 694-6800
Rochester
Hamilton! Avnet Electronics
Phone: (716) 442-7820
Schweber Electronics
Phone: (716) 461-4000
Westbury, LI.
Hamilton! Avnet Electronics
Phone: (516) 333-5800
Schweber Electron ics
Phone: (516) 334-7474
NORTHERN NEW JERSEY
Cedar Grove
Hamilton! Avnet Electronics
Phone: (201l 239-0800
Saddlebrook
Arrow Electronics
Phone: (201) 797-5800
SOUTHERN NEW JERSEY
AND PENNSYLVANIA
Cherry Hill, N.J.
Milgray-Delaware Valley
Phone: (609) 424-1300
Moorestown, N.J.
Arrow! Angus Electronics
Phone: (609) 235-1900
Mt. Laurel, N.J.
Hamilton! Avnet Electronics
Phone: (609) 234-2133
CENTRAL NEW JERSEY
AND PENNSYLVANIA
Somerset, N.J.
Schweber Electronics
Phone: (201)469-6008
Horsham, PA
Schweber Electronics
Phone: (215) 441-0600

NORTH CAROLINA
Greensboro
Hammond Electronics
Phona: (919) 275-6391
OHIO
Beechwood
Schweber Electronics
Phone: (216) 464-2970
Cleveland
Arrow Electronics
Phone: (216) 464-2000
Hamilton! Avnet Electronics
Phone: (216) 461'1400
Pioneer Standard Electronics
Phone: (216) 587-3600
Dayton
Arrow Electronics
Phone: (513) 253-9176
Hamilton! Avnet Electronics
Phone: (513) 433-0610 .
Pioneer Standard Electronics
Phone: (513) 236-9900
TEXAS
Dallas
Component S~ecialties
Phone: (214) 57-4576
Hamilton! Avnet Electronics
Phone: (214) 661-8661
Schweber Electronics
Phone: (214) 661-5010
Houston
Component Specialties·
Phone: (713) 771-7237
Hamilton! Avnet Electronics
Phone: (713) 780-1771
Schweber Electronics
Phone: (713) 784-3600
UTAH
Salt Lake City
Alta Electronics
Phone: (801l486-7227
Hamilton! Avnet Electronics
Phone: (801l972-2800
WASHINGTON
Bellevue
Hamilton! Avnet Electronics
Phone: (206) 746-8750
Seattle
Liberty Electronics
Phone: (206) 763-8200
Intermark Electronics
Phone: (206) 767-3160
WISCONSIN
New Berlin
Hamilton! Avnet Electronics
Phone: (414) 784-4510

347

FOR SIGNETICS
PRODUCTS
WORLDWIDE:

FINLAND
Oy Philips Ab
Helsinki·
Phone: 1 72 71

JAPAN
Signeties Japan, Ltd.
Tokyo
Phone: (03) 230·1521

SPAIN
Copresa S.A.
Barcelona
Phone: 329 63 12

ARGENTINA
Fapesa l.y.C.
Buenos·Aires
Phone: 652·7438/7478

FRANCE
R.T.C.
Paris
Phone: 355-44·99

KOREA
Kumho & Co.
Seoul
Phone: (76) 5271-5

SWEDEN
Elcoma A.B.
Stockholm
Phone: 08/67 97 80

AUSTRIA
Osterreiehlsche Philips
Wien
Phone: 93 26 11

GERMANY
Yalvo
Hamburg
Phone: (040) 3296·1

MEXICO
Electronica S.A. de C.Y.
Mexico D.F.
Phone, 533-1180

AUSTRALIA
Philips Industries·ELCOMA
Lane-Cove, N.S.W.
Phone: 421261

HONG KONG
Philips Hong Kong, Ltd.
Kwuntong
Phone: 3-427232

NETHERLANDS
Philips Nederland B.Y.
Eindhoven
Phone: (040)79 33 33

BELGIUM
M.B.L.E.
Brussels
Phone: 523 00 00

INDIA
Semiconductors, Ltd.
(REPRESENTATIVE ONLY)
Bombay
Phone: 293-667

NEW ZEALAND
E.D.A.C., Ltd.
Wellington
Phone: 873 159

BRAZIL
Ibrape, S.A.
Sao Paulo
Phone: 284-4511

INDONESIA
P.T. Philips·Ralln Electronics
Jakarta
Phone: 581058

NORWAY
Electronica U.
Oslo
Phone: (02) 15 05 90

CANADA
Philips Electron Devices
Toronto
Phone: 425-516l

IRAN
Berkeh Company, Ltd.
Tehran
Phone: 831564

PHILIPPINES
Philips Industrial Dev., Inc.
Makata-Rizal
Phone: 868951-9

CHILE
Philips Chilena $.A.
Santiago
Phone: 39-4001

ISRAEL
Rapac Electronics, Ltd.
Tel Aviv
Phone: 477115.6-7

SINGAPORE/MALAYSIA
Philips Singapore Pte., Ltd.
Toa Payoh
Phone: 538811

DENMARK
Miniwatt A/S
Kobenhavn
Phone: (OIl 69 1622

ITALY
Philips S.p.A.
Milano
Phone: 2-6994

SOUTH AFRICA
E.D.A.C. (PTY!, Ltd.
Johannesburg
Phone: 24-6701-3

348

IImHOfiGII

SWITZERLAND
Philips A.G.
Zurich
Phone: 01/4422 11
TAIWAN
Philips Taiwan, Ltd.
Taipei
Phone: (02) 551-3101-5
THAILAND/LAOS
Saeng Thong Radio, Ltd.
Bangkok
Phone: 527195,519763
UNITED KINGDOM
Mullard, Ltd.
London
Phone: 01·580 6633
UNITED STATES
Signetics International Corp.
Sunnyvale, California
Phone: (408) 739-7700
VENEZUELA, PANAMA,
ARUBA, TRINIDAD
Instrulab C.A.
Caracas
Phone: 614138

InDEH

Si!loOliCS

349

BIPOLAR MEMORY
3101A (O.C')
54174S89 (d.c')
54/74S189 (T.S')
54174S200 (T.S')
54/74S201 (T.S')
54174S301 (O.C,)

82S09 (O.C,)
82S10 (O.C,)
82S11 (T.S')
82S12 (O.C,)
82S16 (T.S')
82S17 (O.C,)
82S21 (O.C,)
82S23 (O.C,)
82S25 (O.C,)
82S27 (O.C,)
8228
82S100 (T.S')
82S101 (O.C,)
82S102 (O.C,)
82S103 (T.S')
82S110 (O.C,)
82S111 (T.S')
82S112 (T.S')
82S114 (T.S')
82S115 (T.S')
82S116 (T.S')
82S117 (O.C,)
82S123 (T.S')
82S126 (O.C,)
82S129 (T.S')
82S130 (O.C,)
82S131 (T.S')
82S136 (O.C,)
82S137 (T.S')
82S140 (O.C,)
82S141 (T.S')
82S180 (O.C,)
82S181 (T.S')
82S184 (O.C,)
82S185 (T.S')
82S190 (O.C,)
82S191 (T.S')
82S200 (T.S')
82S201 (O.C,)
82S208 (T.S')
82S210 (T.S')
82S214 (T.S')
82S215 (T.S')
82S226 (O.C,)
82S229 (T.S')
82S230 (O.C,)
82S231 (T.S')
82S240 (O.C,)
82S241 (T.S')
82S280 (O.C,)
82S281 (T.S')
82S290 (O.C,)

350

64-Bit Bipolar Scratch Pad Memory (16X4) ..............................................
64-Bit Bipolar Scratch Pad Memory (16X4) ..............................................
64-Bit Bipolar Scratch Pad Memory (16X4) ..............................................
256-Bit TTL RAM (256X1) ...............................................................
256-Bit TTL RAM (256X1) ...............................................................
256-Bit TTL RAM (256X1) ...............................................................
576-Bit Bipolar RAM (64X9) .............................................................
1024-Bit Bipolar RAM (1024X1) .........................................................
1024-Bit Bipolar RAM (1024X1) .........................................................
32-Bit Bipolar Multiport Memory (8X4) ...... .. . .. . . . .. . .. . . .. . . . .. .. .. . . . . .. .. .. . . .. . . .. .
256-Bit Bipolar RAM (256X1) ............................................................
256-Bit Bipolar RAM (256X1) ............................................................
64-Bit Bipolar Write-While-Read RAM (32X2) ............................................
256-Bit Bipolar PROM (32X8) ...........................................................
64-Bit Bipolar Scratch Pad Memory (16X4) ..............................................
1024-Bit Bipolar PROM (256X4) .........................................................
4096-Bit Bipolar ROM (1024X4) .........................................................
Bipolar Field Programmable Logic Array (16X48X8) ......................................
Bipolar Field Programmable Logic Array (16X48X8) ......................................
Bipolar Field Programmable Gate Array (16X9) ..........................................
Bipolar Field Programmable Gate Array (16X9) ..........................................
1024-Bit Bipolar RAM (1024X1) .........................................................
1024-Bit Bipolar RAM (1024X1) .........................................................
32-Bit Bipolar Multiport Memory (8X4) ....... . .. .. . . . . . .. . . .. .. . .. .. .. .. .. .. .. .. .. .. . .. ..
2048-Bit Bipolar PROM (256X8) .........................................................
4096-Bit Bipolar PROM (512X8) .........................................................
256-Bit Bipolar RAM (256X1) ............................................................
256-Bit Bipolar RAM (256X1) ............................................................
256-Bit Bipolar PROM (32X8) ...........................................................
1024-Bit Bipolar PROM (256X4) .........................................................
1024-Bit Bipolar PROM (256X4) .........................................................
2048-Bit Bipolar PROM (512X4) .........................................................
2048-Bit Bipolar PROM (512X4) .........................................................
4096-Bit Bipolar PROM (1024X4) ........................................................
4096-Bit Bipolar PROM (1024X4) ........................................................
4096-Bit Bipolar PROM (512X8) .........................................................
4096-Bit Bipolar PROM (512X8) .........................................................
8192-Bit Bipolar PROM (1024X8) ........................................................
8192-Bit Bipolar PROM (1024X8) ........................................................
8192-Bit Bipolar PROM (2048X4) ........................................................
8192-Bit Bipolar PROM (2048X4) ........................................................
16.384-Bit Bipolar PROM (2048X8) ......................................................
16.384-Bit Bipolar PROM (2048X8) .............................•........................
Bipolar Mask Programmable Logic Array (16X48X8) ......................................
Bipolar Mask Programmable Logic Array (16X48X8) ......................................
2048-Bit Bipolar RAM (256X8) ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2304-Bit Bipolar RAM (256X9) ...........................................................
2048-Bit Bipolar ROM (256X8) ..........................................................
4096-Bit Bipolar ROM (512X8) ..........................................................
1024-Bit Bipolar ROM (256X4) ..........................................................
1024-Bit Bipolar ROM (256X4) ..........................................................
2048-Bit Bipolar ROM (512X4) ..........................................................
2048-Bit Bipolar ROM (512X4) ..........................................................
4096-Bit Bipolar ROM (512X8) ..........................................................
4096-Bit Bipolar ROM (512X8) ..........................................................
8192-Bit Bipolar ROM (1024X8) .........................................................
8192-Bit Bipolar ROM (1024X8) .........................................................
16.384-Bit Bipolar ROM (2048X8) ........................................................

Si!lDotiCS

32
32
32
47
47
47
52
56
56
27
43
43
36
89
32
97
80
142
142
159
159
56
56
27
109
109
43
43
89
101
101
114
114
122
122
118
118
126
126
134
134
138
138
152
152
64
64
72
72
70
70
75
75
77
77
82
82
85

82S291 (T.Sol
82S400 (O.Col
82S400A (O.Col
82S401 (T.S')
82S401A (T.S')
82S2708 (T.S')
93415A (O.C')
93425A (T.S')
10139
10149
10155

16,384-Bit Bipolar ROM (2048X8) .......................................•................
4096-Bit Bipolar RAM (4096Xl) ......................................•..................
4096-Bit Bipolar RAM (4096Xl) .........................................................
4096-Bit Bipolar RAM (4096Xl) .........................................................
4096-Bit Bipolar RAM (4096Xl) ......................................•..................
8192-Bit Bipolar PROM (1024X8) ........................................................
1024-Bit Bipolar RAM (1024Xl) .........................................................
1024-Bit Bipolar RAM (1 024Xl) ...........................................• . . . . . . . . . . . . .
256-Bit ECl High Performance PROM (32X8) ...............................•............
1024-Bit ECl PROM (256X4) ............................... "............... ~.............
16-Bit ECl CAM (8X2) .............................................•....................

85
67
67
67
67
130
60
60
93
105
23

1024-Bit Dynamic Decoded MOS RAM (1024Xl) .........................................
2048-Bit Electrically Programmable MOS ROM (256X8) ..................•.•..•...........
1024-Bit Static MOS RAM (256X4) .......•................................•..............
1024-Bit Static MOS RAM (256X4) .......................................................
1024-Bit Static MOS RAM (256X4) .......................................................
1024-Bit Read/Write Static MOS RAM (1024Xl) ..........................................
1024-Bit Read/Write Static MOS RAM (1024Xl) ..........................................
1024-Bit Read/Write Static MOS RAM (1024Xl) ..........................................
1024-Bit Static MOS RAM (1024Xl) .....................................................
1024-Bit Static MOS RAM (1024Xl) .....................................................
1024-Bit Static MOS RAM (1024Xl) .....................................................
1024-Bit Static MOS RAM (1024Xl) .....................................................
1024-Bit Static MOS RAM (1024Xl) .....................................................
1024-Bit Static MOS RAM (1024Xl) .....................................................
1024-Bit Static MOS RAM (1 024Xl) .....................................................
1024-Bit Read/Write Static MOS RAM (1024Xl) ..........................................
1024-Bit Read/Write Static MOS RAM (1024Xl) ..........................................
1024-Bit Read/Write Static MOS RAM (1024Xl) ..........................................
1024-Bit Read/Write Static MOS RAM (1024Xl) ..........................................
1024-Bit Read/Write Static MOS RAM (1024Xl) ..........................................
1024-Bit Read/Write Static MOS RAM (1024Xl) ................... ,......................
1024-Bit Read/Write Static MOS RAM (1024Xl) ..........................................
1024-Bit Static MOS RAM (256X4) .......................................................
1024-Bit Static MOS RAM (256X4) .......................................................
1024-Bit Static MOS RAM (256X4) .......................................................
1024-Bit Static MOS RAM (256X4) .......................................................
1024-Bit Static MOS RAM (256X4) .......................................................
1024-Bit Static MOS RAM (256X4) .......................................................
1024-Bit Static MOS RAM (1024Xl) .....................................................
1024-Bit Static MOS RAM (1024Xl) .....................................................
1024-Bit Static MOS RAM (1024Xl) ....................................•................
1024-Bit Static MOS RAM (1024Xl) .....................................................
256-Bit Read/Write Static MOS RAM (256Xl) ............................................
256-Bit Read/Write Static MOS RAM (256Xl) ............................................
1024-Bit Multiplexed Dynamic Shift Register (256X4) ............................•........
1024-Bit Multiplexed Dynamic Shift Register (512X2) .....................................
1024-Bit Multiplexed Dynamic Shift Register (1024Xl) ....................................
512-Bit Recirculating Dynamic Shift Register (512Xl) .........................•..........
Duall00-Bit Dynamic Shift Register (100X2) .............................................
Duall00-Bit Dynamic Shift Register (100X2) .............................................
Dual 50-Bit Static Shift Register (50X2) ..................................................
Duall00-Bit Static Shift Register (100X2) ................................................
Dual 200-Bit Dynamic Shift Register (200X2) .............................................
1024-Bit Recirculating Dynamic Shift Register (1024Xl) ........................•.......•.
2560-Bit Static Character Generator (64X8X5) •.............................•............•
3072-Bit Static Character Generator (64X6X8) ..............................•...•.........

204
274
175
175
175
187
187
187
190
190
190
190
190
190
190
194
194
194
197
197
197
197
178
178
178
181
181
181
200
200
200
200
169
172
307
307
307
302
300
300
286
286
286
302
258
263

MOSMEMORY
1103
1702A
2101
2101-1
2101-2
2102
2102-1
2102-2
2102A
2102Al
2102A-2
2102Al-2
2102A-4
2102Al-4
2102A-6
21F02
21 F02-2
21 F02-4
21102
21l02-1
21l02-2
21l02-3
2111
2111-1
2111-2
2112
2112-1
2112-2
2115
2115l
2125
2125l
2501
25101
2502
2503
2504
2505
2506
2507
2509
2510
2511
2512
2513
2516

9!!1DOtiC9

351

2517
2518
2519
2521
2522
2524
2525
2526
2527
2528
2529
2530
2532
2533
2580
2600
2600-1
2606
2606-1
2607
2608
2608-1
2609
2616
2616-1
2617
2617-1
2660
2660-1
2660-2
2660-3
2680
2680-1
2680-2
2704
2708

352

Dual 100-BitDynamic Shift Register (100X2) ....•..........................•.............
Hex 32-Bit Static Shift Register (32X6) ... . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .
Hex 40-Bit Static Shift Register (40X6) ...............................................•. , .
Dual 128-Bit Static Shift Register (128X2) ..................................•.............
Dual 132-Bit Static Shift Register (132X2) ................................................
512-Bit Recirculating Dynamic Shift Register (512X1) ............. ;......................
1024-Bit Recirculating Dynamic Shift Register (1024X1) ...............................•..
5184-Bit Static ROM/Character Generator (64X9X9) ............••...........•.....•......
Dual 240-Bit Static Shift Register (240X2) .................... ;...........................
Dual 250-Bit Static Shift Register (250X2) ........................................•.......
Dual 256-Bit Static Shift Register (256X2) ................................................
4096-Bit High Speed Static MOS ROM (512X8) ..........................................
Quad 80-Bit Static Shift Register (80X4) .................................................
1024-Bit Static Shift Register (1024X1) ..................•..... ...........................
8192-Bit Static MOS ROM (2048X4) ........................................•............
16,384-Bit Static MOS ROM (2048X8) ....................................................
16,384-Bit Static MOS ROM (2048X8) . ........................ ...........................
1024-Bit ReadlWrite Static MOS RAM (256X4) ...........................................
1024-Bit ReadlWrite Static MOS RAM (256X4) ...........................................
8192-Bit Static MOS ROM (1024X8) ..............................................•......
8192-Bit Static MOS ROM (1024X8) ............................................••.......
8192-Bit Static MOS ROM (1024X8) .....................................................
8192-Bit Static MOS ROM (128X9X7) ....................................................
16,384-Bit Static MOS ROM (2048X8) ....................................................
16,384-Bit Static MOS ROM (2048X8) .........................................•........•.
16,384-Bit Static MOS ROM (2048X8) ........... . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . • . . . . . . .
16,384-Bit Static MOS ROM (2048X8) .................................•..................
4096-Bit Read/Write Dynamic MOS RAM (4096X1) ..................................•....
4096-Bit ReadlWrite Dynamic MOS RAM (4096X1) ...............................•.......
4096-Bit Read/Write Dynamic MOS RAM (4096X1) .......................................
4096-Bit Read/Write Dynamic MOS RAM (4096X1) .......................................
4096-Bit Read/Write Dynamic MOS RAM (4096X1) .......................................
4096-Bit ReadlWrite Dynamic MOS RAM (4096X1) .......................................
4096-Bit ReadlWrite Dynamic MOS RAM (4096X1) ....... .,...............................
4096-Bit Erasable and Electrically Reprogrammable MOS RdM (512X8) ...................
8192-Bit Erasable and Electrically Reprogrammable MOS ROM (1024X8) ..................

GjgnDliCG

300
283
283
292
292
305
305
268
295
295
295
221
289
298
239
242
242
184
184
232
236
236
225
250
250
254
254
208
208
208
208
216
216
216
279
279

,.

Si!lDotiCS
a subsidiary of U.S. Phmps Corporation'
Signetics Corporatrn
Po.80x9052
811 East Arques Avenue
SumyvakJ, California 94086
l€Iephone 408/739-7700

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Pr inted in USA Jun. 1977
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