1978_Fairchild_Linear_Interface_Data_Book 1978 Fairchild Linear Interface Data Book
User Manual: 1978_Fairchild_Linear_Interface_Data_Book
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F=AIRCHIL.C
464 Ellis Street, Mountain View, California 94042
c?
1978 Fairchild Camera and Instrument Corporation/464 Ellis Street, Mountain View, California 94042/(415) 962-5011/TWX 910-379-6435
INTRODUCTION
The increase in complexity and diversity of Linear Integrated Circuits over
the last few years has necessitated a change in the format of the Fairchild
Linear Data Books. In this data book, Fairchild is pleased to present important technical information on one of the industries broadest and most advanced family of Linear Interface, Comparator and Data Conversion circuits.
Other Fairchild Linear data books will cover Operational Amplifiers, Consumer and Regulator devices.
Fairchild continues to be a pioneer in Linear Interface and Data Conversion
products. Today Fairchild's state-of-the-art technology is bringing forth devices like the 9643; MOS/CCD driver, 75S20 series of Schottky core memory
sense amplifiers, 9634/6/7/8 series of RS422/423 compatible line circuits,
f.LA9708; micro-processor based 8-bit AID subsystem, and the CMOS processed f.LA9706; micro-processor compatible 8 channel, 6-bit D/A converter.
You'll find complete specifications on Fairchild's MOS/CCD memory interface, data transmission, peripheral driver, memory sense amplifier, display
interface, data conversion, comparator and special functions. Also included
is advanced information on some of Fairchild's Interface circuits to be introduced shortly.
To expedite the designer's search for the right devices to meet various system requirements, several helpful aids are provided - selection guides by
function, an LlC cross reference identifying competitive devices with their
Fairchild direct replacements or nearest equivalents and the numerical indexes will let you locate specific type numbers quickly. For the Hi Rei customer, Fairchild's Hi Rei processing and Matrix VI are given in a separate
section.
TABLE OF CONTENTS
1.
Alpha Numerical Index of Interface Devices and Selection Guides ............ 1-3
Chapter 2.
Linear I ndustry Cross Reference ............................................ 2-3
3.
Quality, Reliability and Hi Rei Processing ................................... 3-3
Chapter 4.
Voltage Comparators ...................................................... 4-3
Chapter 5.
Data Acquisition ........................................................... 5-3
Chapter 6.
Line Circuits -
Chapter 7.
Peripheral and Display Drivers ............................................. 7-3
Chapter
8.
Memory Interface .......................................................... 8-3
Chapter 9.
Transistor Arrays and Special Functions .................................... 9-3
Chapter 10.
Data Transmission Information ........................................... 10-3
Chapter 11.
Order Information, Dice Policy and Package Outlines ...................... 11-3
Chapter 12.
Fairchild Field Sales Offices, Representatives and Distributors ............. 12-3
Chapter
Chapter
Drivers, Receivers and Transceivers ......................... 6-3
ALPHA NUMERICAL INDEX OF INTERFACE
DEVICES AND SELECTION GUIDES
Alpha Numerical Index of Interface Devices .............................................. 1-3
Selection Guides ....................................................................... 1-7
ALPHA-NUMERICAL INDEX
DEVICE
DESCRIPTION
PAGE
J.lAF111
FET-Input Voltage Comparator ......................................... 4-3
J.lAF311
FET-Input Voltage Comparator ......................................... 4-3
J.lAF198
Monolithic Sample and Hold ........................................... 5-3
J.lAF298
Monolithic Sample and Hold ........................................... 5-3
J.lAF398
Monolithic Sample and Hold ........................................... 5-3
J.lA0801 (DAC-08) 8-Bit High-Speed Multiplying D/A Converter ............................ 5-4
J.lA0802 (MC1408)8-Bit Multiplying D/A Converter ...................................... 5-10
J.lA111
Voltage Comparator ................................................... 4-8
J.lA311
Voltage Comparator ................................................... 4-8
J.lA139
Low-Power, Low-Offset Quad Voltage Comparator .................... 4-13
J.lA139A
Low-Power, Low-Offset Quad Voltage Comparator .................... 4-13
J.lA1488
Quad EIA RS-232C Line Driver ......................................... 6-3
J.lA1489
Quad EIA RS-232C Line Receiver .................................... 6-43
J.lA 1489A
Quad EIA RS-232C Line Receiver .................................... 6-43
J.lA2240
Programmable Timer/Counter ... , .................................... 9-36
J.lA239
Low-Power, Low-Offset Quad Voltage Comparator .................... 4-13
p.A239A
Low-Power, Low-Offset Quad Voltage Comparator .................... 4-13
J.lA2901
Low-Power, Low-Offset Quad Voltage Comparator .................... 4-13
J.lA3018
Matched Monolithic Transistor Array ................................... 9-3
J.lA3018A
Matched Monolithic Transistor Array ................................... 9-3
J.lA3019
Diode Array ........................................................... 9-3
p.A3026
Transistor Array ....................................................... 9-3
J.lA3036
Transistor Array ....................................................... 9-3
p.A3039
Diode Array ........................................................... 9-3
J.lA3045
Transistor Array ....................................................... 9-3
p.A3046
Transistor Array ....................................................... 9-3
p.A3054
Transistor Array ....................................................... 9-3
p.A3086
Transistor Array ....................................................... 9-3
p.A3302
Low-Power, Low-Offset Quad Voltage Comparator .................... 4-13
J.lA339
Low-Power, Low-Offset Quad Voltage Comparator .................... 4-13
J.lA339A
Low-Power, Low-Offset Quad Voltage Comparator .................... 4-13
p.A4151
VOltage-to-Frequency Converter ..................................... 5-15
J.lA555
Single Timing Circuit ................................................ 9-26
J.lA556
Dual Timing Circuit ................................................. 9-31
J.lA71 0
High-Speed Differential Comparator .................................. 4-21
J.lA710C
High-Speed Differential Comparator .................................. 4-21
p.A711
Dual High-Speed Differential Comparator ............................. 4-25
J.lA711 C
Dual High-Speed Differential Comparator ............................. 4-25
p.A7151
VOltage-to-Frequency Converter with Op Amp ........................ 5-15
J.lA 726
Temperature-Controlled Differential Pair .............................. 9-23
J.lA734
Precision Voltage Comparator ....................................... 4-29
J.lA7391
DC Motor-Speed Control ............................................ 9-48
1-3
•
ALPHA-NUMERICAL INDEX (Cant.)
DEVICE
!J,A7392
!J,A760
!J,A8T13
!J,A8T14
!J,A8T23
!J,A8T24
!J,A8T26A
!J,A8T28
!J,A9706
!J,A9706A
!J,A9708
55107A
551078
55108A
551088
55110A
55122
55S20
55S24
55S234
55232
55238
5528
55325
55326
55327
55450A
554508
55451A
554518
55452A
554528
55453A
554538
55454A
554548
55460
55461
55462
55463
DESCRIPTION
PAGE
DC Motor-Speed Control ............................................ 9-58
High-Speed Differential Comparator .................................. 4-36
Dual Single-Ended Line Driver ......................................... 6-7
Triple Line Receiver ................................................. 6-47
Dual IBM 360/370 1/0 Single-Ended Line Driver ....................... 6-13
Triple IBM 360/370 1/0 Line Receiver ................................. 6-50
Quad 3-State Inverting 8us Transceiver .............................. 6-87
Quad 3-State Non-Inverting 8us Transceiver .......................... 6-87
8-Channel, 12-8it, !J,P Compatible DI A Converter ...................... 5-21
7-Channel, 12-8it, !J,P Compatible DI A Converter ...................... 5-21
6-Channel, 8-8it, !J,P Compatible AID Converter Subsystem ............ 5-27
Dual General-Purpose Line Receiver ................................. 6-53
Dual General-Purpose Line Receiver ................................. 6-53
Dual General-Purpose Line Receiver ................................. 6-53
Dual General-Purpose Line Receiver ................................. 6-53
Dual General-Purpose Line Driver .................................... 6-13
Triple-Line Receiver ................................................. 6-47
Dual Schottky ±2.5 mV Sense Amp with Complementary Outputs ...... 8-22
Dual Schottky ±2.5 mV Sense Amp ................................... 8-22
Dual Schottky ±2.5 mV Sense Amp ................................... 8-22
Dual Sense Amp with Open Collector Outputs ........................ 8-41
Dual Sense Amp with Preamplifier Test Points ........................ 8-41
Dual Sense Amp with Preamplifier Test Points ........................ 8-41
Dual Core Memory Drivers ........................................... 8-59
Quad Positive OR Sink Core Memory Drivers ......................... 8-71
Quad Core Memory Switches ........................................ 8-71
Dual Positive AND Peripheral Driver .................................... 7-3
Dual High-Speed Positive AND Peripheral Driver ...................... 7-17
Dual Positive AND Peripheral Driver .................................... 7-3
Dual High-Speed Positive AND Peripheral Driver ...................... 7-17
Dual Positive NAND Peripheral Driver .................................. 7-3
Dual High-Speed Positive NAND Peripheral Driver .................... 7-17
Dual OR Positive Peripheral Driver ..................................... 7-3
Dual High-Speed OR Positive Peripheral Driver ....................... 7-17
Dual Positive NOR Peripheral Driver .................................... 7-3
Dual High-Speed Positive NOR Peripheral Driver ...................... 7-17
Dual High-Voltage Positive AND Peripheral Driver .................... 7-31
Dual High-Voltage Positive ANd Peripheral Driver ..................... 7-31
Dual High-Voltage Positive NAND Peripheral Driver ................... 7-31
Dual High-Voltage Positive OR Peripheral Driver ...................... 7-31
1-4
ALPHA-NUMERICAL INDEX (Cant.)
DEVICE
55464
55471
55472
55473
55474
55491
55491A
55492
55492A
75107A
75107B
75108A
75108B
75110A
75112
75121
75122
75123
75124
75150
75154
75S20
75S24
75S234
75232
75238
7528
75325
75326
75327
75450A
75450B
75451A
75451 B
75452A
75452B
75453A
75453B
75454A
75454B
75460
DESCRIPTION
PAGE
Dual High-Voltage Positive NOR Peripheral Driver .................... 7-31
Dual High-Voltage Positive AND Peripheral Driver .................... 7-42
Dual High-Voltage Positive NAND Peripheral Driver ................... 7-42
Dual High-Voltage Positive OR Peripheral Driver ...................... 7-42
Dual High-Voltage Positive NOR Peripheral Driver .................... 7-42
Quad MOS-to-LED Segment Drivers .................................. 7-54
Quad MOS-to-LED Segment Drivers .................................. 7-54
HEX MOS-to-LED Digit Drivers ...................................... 7-54
HEX MOS-to-LED Digit Drivers ...................................... 7-54
Dual General-Purpose Line Receiver ................................. 6-53
Dual General-Purpose Line Receiver ................................. 6-53
Dual General-Purpose Line Receiver ................................. 6-53
Dual General-Purpose Line Receiver ................................. 6-53
Dual General-Purpose Line Driver .................................... 6-13
Dual General-Purpose Line Driver ...................................... 6-7
Dual Single-Ended Line Driver ......................................... 6-7
Triple Line Receiver ................................................. 6-47
Dual IBM 360/370 I/O Single-Ended Line Driver ....................... 6-10
Triple IBM 360/370 I/O Line Receiver ................................. 6-50
Dual EIA RS-232C/MIL-STD-188C Line Driver ........................ 6-18
Quad EIA RS-232C Line Receiver .................................... 6-60
Dual Schottky ±2.5 mV Sense Amp with Complementary Outputs ...... 8-20
Dual Schottky ±2.5 mV Sense Amp ................................... 8-20
Dual Schottky ±2.5 mV Sense Amp ................................... 8-20
Dual Sense Amp with Open-Collector Outputs ........................ 8-39
Dual Sense Amp with Preamplifier Test Points ........................ 8-39
Dual Sense Amp with Preamplifier Test Points ........................ 8-39
Dual Core Memory Drivers ........................................... 8-57
Quad Positive OR Sink Core Memory Drivers ......................... 8-69
Quad Core Memory Switches ........................................ 8-69
Dual Positive AND Peripheral Driver .................................... 7-3
Dual High-Speed Positive AND Peripheral Driver ...................... 7-17
Dual Positive AND Peripheral Driver .................................... 7-3
Dual High-Speed Positive AND Peripheral Driver ...................... 7-17
Dual Positive NAND Peripheral Driver .................................. 7-3
Dual High-Speed Positive NAND Peripheral Driver .................... 7-17
Dual OR Positive Peripheral Driver ..................................... 7-3
Dual High-Speed OR Positive Peripheral Driver ....................... 7-17
Dual Positive NOR Peripheral Driver .................................... 7-3
Dual High-Speed Positive NOR Peripheral Driver ...................... 7-17
Dual High-Voltage Positive AND Peripheral Driver .................... 7-31
1-5
•
ALPHA-NUMERICAL INDEX (Cant.)
DEVICE
75461
75462
75463
75464
75471
75472
75473
75474
75491
75491A
75492
75492A
9612
9612A
9612E
9613
9613C
9614
9615
9616
9617
9622
9624
9625
9627
9634
9636A
9637A
9638
9640 (26S 101
9641 (26S111
9642
9643
9644
9645 (32451
9646 (OS0026 1
9650
9665 (ULN2001 1
9666 (ULN20021
9667 (ULN20031
9668 (ULN20041
DESCRIPTION
PAGE
Dual High-Voltage Positive AND Peripheral Driver .................... 7-31
Dual High-Voltage Positive NAND Peripheral Driver ................... 7-31
Dual High-Voltage Positive OR Peripheral Driver ...................... 7-31
Dual High-Voltage Positive NOR Peripheral Driver .................... 7-31
Dual High-Voltage Positive AND Peripheral Driver .................... 7-42
Dual High-Voltage Positive NAND Peripheral Driver ................... 7-42
Dual High-Voltage Positive OR Peripheral Driver ...................... 7-43
Dual High-Voltage Positive NOR Peripheral Driver .................... 7-42
Quad MOS-to-LED Segment Drivers .................................. 7-54
Quad MOS-to-LED Segment Drivers .................................. 7-54
HEX MOS-to-LED Digit Drivers ...................................... 7-54
HEX MOS-to-LED Digit Drivers ...................................... 7-54
Dual Differential Line Driver ......................................... 6-22
Dual Differential Line Driver ......................................... 6-22
Dual Differential Line Driver ......................................... 6-22
Dual Differential Line Receiver ....................................... 6-65
Dual Differential Line Receiver ....................................... 6-65
Dual Differential Line Driver ......................................... 6-26
Dual Differential Line Receiver ....................................... 6-69
Triple EIA-RS-232C/MIL-STD-188C Line Driver ....................... 6-30
Triple EIA RS-232C Line Receiver .................................... 6-74
Dual Line Receiver .................................................. 6-76
Dual TTL-to-MOS Interface Element. ................................... 8-3
Dual TTL-to-MOS Interface Element. ................................... 8-3
Dual EIA RS-232C/MIL-STD-188C Line Receiver ...................... 6-80
Dual 3-State EIA RS-422 Differential Line Driver ..................... , 6-33
Dual Programmable Slew Rate EIA RS-423 Line Driver ................ 6-36
Dual EIA RS-422/423 Differential Line Receiver ....................... 6-84
Dual EIA RS-422 High-Speed Differential Line Driver ................. , 6-40
Quad General-Purpose Bus Transceiver .............................. 6-94
Quad General-Purpose Bus Transceiver ............................. , 6-94
Quad General-Purpose Bus Transceiver with Hysteresis ............... 6-94
Dual AND TTL-to-MOS/CCD Driver .................................. 8-10
Dual NAND TTL-to-MOS/CCD Driver ................................ 8-10
Quad TTL-to-MOS/CCD Driver ...................................... 8-13
Dual 5 MHz Two Phase MOS Clock Driver ............................ 8-16
4-Bit Precision Current Source ....................................... 5-35
Seven High-Voltage, High-Current Darlington Drivers ................. 7-49
Seven High-Voltage, High-Current Darlington Drivers ................. 7-49
Seven High-Voltage, High-Current Darlington Drivers ................. 7-49
Seven High-Voltage, High-Current Darlington Drivers ................. 7-49
1-6
VOLTAGE COMPARATOR SELECTION GUIDE
.
o
Z
a
=
iiiCtao
=-M'
I»
.e-
U
1:;-<~
&I
::
C
~
c
c
~:::Ec
u
::1.
=_
=C.
O
O~cao
'S:;::E~
Q,.U-
I»
iAJi
:::Q):EU
-i
0.»
=
C)_
O!!_o.e:
50I~
ft:.
-.:.=E
~
,_
OA
>~
:?--
8;>
~
~
GI
~_...J
t:.
a.I~""'5"
-Fto
~
g-;
~i
iii
D.C
c ....
a;
:.
~
~
.,
era
.:
~
Q.
~
....
~
I'AF111
Fet-lnput Voltage Comparator
005
0000025
4.0
200K
+36
200
2
M
58,6A
I'AF311
Fet-lnput Voltage Comparator
0 15
0000075
10
200K
+36
200
2
C
58,6A
I'A111
Voltage Comparator Strobed Inputs,
Single Supply, Low Ie
0 1
004
0.7
200K
±15
200
5
M
58
I'A311
Voltage Comparator Strobed Inputs,
Single Supply, Low Ie
0.25
0 OS
2.0
200K
±15
200
5
C
58
I'A139
Quad Comparator Single Supply,
CMRR inc!. gnd
0 1
0025
5.0
200K
±1 to ±t8 or from
2 to 36 and gnd
1300
1
M
6A
I'A139A
Quad Comparator Single Supply,
CMRR inc!. gnd
01
0025
2.0
200K
±1 to ±t8 or from
2 to 36 and gnd
1300
1
M
SA
I'A239
Quad Comparator Single Supply,
CMRR inc!. gnd
025
005
50
200K
±t to ±t8 or from
2 to 36 and gnd
1300
1
A
6A,9A
I'A239A
Quad Comparator Single Supply,
CMRR inc!. gnd
025
005
20
200K
±t to ±t8 or from
2 to 36 and gnd
1300
1
A
SA,9A
I'A339
Quad Comparator Single Supply,
CMRR inc!. gnd
025
005
5.0
200K
±t to ±18 or from
2 to 36 and gnd
1300
1
C
6A,9A
I'A339A
Quad Comparator Single.Supply,
CMRR inc!. gnd
025
005
2.0
200K
±lto ±t8 or from
2 to 36 and gnd
1300
1
C
SA.9A
I'A710/C
High Speed Differential
Voltage Comparator
20,25
30/50
20/5.0
1 75K
+12, -6
40
1
M, C
58. 3F, SA. 9A
I'A711/C
Dual High Speed
Differential Comparator
75 100
10/15
35/50
15K
+12, -6
40
1
M. C
3F. 5F. SA. 9A
I'A734
Precision Comparator
Low Drifl-3.5I'V/oC
015
0025/005
50/30
25K
±5to ±15
200
2
M. C
5N.6A
I'A760
High Speed Differential Comparator
60
75
SO
5K
±4.5to ±6.5
252M. C
58.6A
I'A2901
Quad Comparator Single Supply,
CMRR inc!. gnd
025
005
70
200K
± 1 to 1'18 or from
2 to 36 and gnd
1300
1
A
SA.9A
I'A3302
Quad Comparator Single Supply,
CMRR inc!. gnd
05
0 1
200
200K
±1 to ±18 or from
2 to 36 and gnd
1300
1
C
SA.9A
•
DATA ACQUISITION PRODUCTS SELECTION GUIDE
(%FS)
Supply
Voltage
(V)
Package(s)
-55/+125
±0.1
±15
68
-55/+125
±0.19
±15
68
0/+70
±0.1
±15
68,98
MAOBOl E (OAC-OBE)
01+70
±0.19
±15
68,98
MAOB01C (OAC-OBC)
0/+70
±0.39
±15
68,98
MAOB02 (MC150B-B)
-551+125
±0.19
0/+70
±0.19
MAOB02B (MC140B-7)
0/+70
±0.39
MA0802C (MC1408-6)
01+70
±0.78
6 channel, 8 bit
IlP compatible AID converter
-551+125
0/+70
±0.2
MA9706
8 channel, 12 bit
IlP compatible D/A converter
0/+70
'+:0.01
pA9706A
7 channel, 12 bit
IlP compatible D/A converter
0/+70
pA4151
Voltage to frequency
converter
Of+70
MA7151
Voltage to frequency
converter with op amp
0/+70
MAF198
Sample and hold Amplifier
MAF398
9650
Device Number
Function
MAOB01A (OAC-OBA)
MA0801 (OAC-OS)
MAOB01H (OAC-OBH)
MAOB02A (MC140B-B)
~
a,
MA9708
8 bit high speed
multiplying D/A converter
8 bit multiplying
D/A converter
Operating
Temp. Range (' C)
Maximum
Non·Linearity
68
+5
and
-5to-15
68,98
68,98
68,98
78
+4.75 to +15
78,98
+5
6A,9A
+5
78, 98
+8 to +15
5S,6T,9T
+8to+15
6A,9A
-55/+125
±5 to±18
5S
Sample and hold Amplifier
0/+70
±5 to ±18
5S
4-bit current source
AID or D/A
01+70
~0.01
:':0.5
:':0.2 to ±001
+4.5 and -14
or
+5.5 and -16
68
LINE DRIVER SELECTION GUIDE
Description
Output
Current
Capability
(mA)
Propagation.
Delay Time S = Single Ended Party Line
Typical (ns)
o = Dillerential Operation
Strobe
Power
Supplies
(V)
Yes
5
Device TYpe For
Temperature Range
55°C to 125°C
20
S,D
Yes
75450B
6A
6A,9A
2
75451B
6T
6T,9T
2
75121/1'A8T13
6B
6B,9B
2
751221
I'A8T14
9612E
6T,58
6T,9T,5B
2
9613
Complimentary
Outputs
6B
6B,9B
2
9615
3 Input ANDI
NAND Function
2
751241
I'A8T24
55451B
Drivers
.....,
Drivers
Meeting
EIA
Standards
Yes
Yes
5
100
22
S
Yes
Yes
5
40
12
S,D
No
No
5
40
15
S, 0
Yes
Yes
5
9614
100
20
S
Yes
Yes
5
751231
I'A8T23
50
10
D
Yes
Yes
5
9634
6B
6B,9B
2
9637A
3-State Output
RS-422
10
60
S
No
Yes
±12
75150
6A,9A,
6T,9T
2
75154
9627,9617
RS-232CI
MIL-STD-188C
10
220
S
No
Yes
±12
I'A1488
6A,9A
4
I'A1489
I'A1489A
RS-232C
30
320
S
No
No
±12
9616C, E
6A
6A,9A
3
I'A1489/A
9617,9627
RS-232CI
MIL-STD-188C
40
10
D
No
No
5
9638
6T
6T,9T
2
9637A
RS-422,
HighSpeea
17
.
S
No
No
±12
9636A
6T
6T,9T
2
9637A
D
Yes
Yes
±5
75112
6A,9A
2
75107A1B
75110A
6A
6A,9A
2
9612A
9616DM
9638RM
18
Current
Mode
Drivers
Function
S
9634RM
<0
And Logic
20
9614DM
360/3701/0
Interface
9615
751221
I'A8T14
300
55121/1'A8T13
General
Purpose
Additional
Features
O°Cto 70°C
55450B
300
Drivers
Companion
Per
Package Receivers
Package
TYpe
6.5
9
9
D
Yes
Yes
±5
9636ARM
55110A
6B,9B
RS-423, Slew Rate
Programmable
7510BA/B
·9636A output slew rates are jointly controlled by a single external resistor.
•
Glitchless
Cu rrent Outputs
LINE RECEIVERS SELECTION GUIDE
Type Of
Output'
Propagation
Delay Time
Typical (ns)
Party line
Operation
Strobe
D
T
17
Yes
Yes
D
0
19
Yes
Yes
S ~ Single Ended
Description
o=
Differential
Power
Supplies
(V)
Device Type For
T
17
Yes
Yes
0
19
Yes
6A,9A
2
75107A
6A,31
6A, 9A
2
751078
6A,31
6A,9A
2
75108A
6A,31
6A,9A
2
751088
6A,31
6A,9A
2
30
Yes
751221
68
68,98
75110A,
55110A
±5
8 versions have input
protection diodes for
power off condition
75110A,
75112
Yes
5512211'A8T14
T
Features
75208'
551088
S
Additional
Drivers
2
55108A
D
Companion
6A,9A
551078
General
Purpose
Receivers
Per
Package
75201'
55107A
D
Receivers
Package
55° C to 125° C O°C to 70°C Type
Temperature Range
Yes
5
751211
Hysteresis for improved
noise immunity
3
I'A8T13
2
9614
2
9612
±15V CMRR
9621
Wire - or capability
751231
Hysteresis
I'A8T14
~
I
~
a
Receivers
For 360/370
110 Interface
D
OorT
20
Yes
Yes
5
D
T
25
No
No
5
S
T
35
Yes
Yes
+5 and
-10
S
T
20
No
Yes
5
9615DM, FM
9615
9613
9613C
6T, 9T
9622C
6A
6A,9A
2
751241
68,98
3
I'A8T24
T
S
22
No
No
+50r+12
S
R
S
R
D
T
25
50
60
No
No
No
No
±12
No
Yes
±12
75154
68, 98
4
I'A1489
6A, 9A
4
I'A1489A
6A, 9A
4
9617
6A, 9A
3
9616
2
9616
9627
68,98
68,98
Also meets MIL-STD-188C
Hysteresis
13
Yes
No
2
9634
9638
9636A
±30mV built in Hysteresis
Schottky circuitry also
meets MIL-STD-188C
75150
I'A1488
9627DM
9637ARM
T
S, D
±500 mV input sensitivity,
±15 CMRR
I'A8T13
5
Receivers
Meeting
EIA Standard
RS-422/423
6T
9622
Receivers
Meeting EIA
Siandard
RS-232-C
68,4L
68,98
6T
5
9637A
6T,9T
-
"T - Totem pole, 0 = Open collector, R = ReSistor pull-up
. Not recommended for new deSigns, but Fallchlld Will continue to supply these devices for eXisting applications.
Hysteresis
Response threshold
control, 1489A has more
Hysteresis than 1489
QUAD BUS TRANSCEIVERS
Driver
Characteristics
Output
• Schottky Circuitry
Device Type For
Temperature Range
Capability
(mA)
tPD
Typical
(ns)
Strobe
Or
Enable
tPD
Typical
(ns)
Strobe
Or
Enable
100
10
Strobe
10
Strobe
100
12
Strobe
10
Strobe
100
15
Strobe
8
Strobe
Current
Common Features
Receiver
Characteristics
_55° C to 125° C
O°Cto70°C
Package
Type
9640/26S10
6B
6B,9B
9641/26S11
6B
6B,9B
9642
6B
6B,9B
9640DM/26S10
• Single 5 V Supply
9641 DM/26S11
• Party Line Operation
9642DM
• TTL-Compatible Driver Inputs
• Totem-Pole Receiver Outputs
• Four Transceivers
6B
J.LA8T26ADM
48
12
Enable
8
Enable
48
12
Enable
8
Enable
J.LA8T26A
6B,9B
f'A8T28
6B
6B,9B
Per Package
-'
I
• P-N-P Outputs To
Reduce Input Loading
J.LA8T28DM
Additional Features
• Inverting Bus on 9640/26S10, 9642
• Non-Inverting Bus on 9641/26S11
• 600 mV Receiver Hysteresis on 964 2
For Maximum System Noise Margir
•
•
•
•
•
3-State Driver and Receiver Output~
J.LA8T26A - Inverting Bus
f'A8T28 - Non-Inverting Bus
J.LP Bus Extender
Replaces NE8T26A and NE8T28
-'
LED DISPLAY DRIVERS
Descrlpllon
Input
Compallbility
Segment
Power
Driver.
Supplies
(V)
Per
Package
Device
Type
Package
Type
10
4
75491
6A,9A
20
4
75491 A
6A,9A
10
6
75492
6A,9A
20
6
75492A
6A,9A
Additional F.atur••
-SOmA source/sink capability
Drivers
MOS
Digit
Drivers
.250mA sink capability
•
PERIPHERAL DRIVERS
Maximum
Oll-SIale
Voltage
(V)
30
30
,
Minimum
Lalch-up
Voltage
(V)
20
20
Maximum
Recommended
Current
(mA)
300
300
Typical
Delay
Time
(n5)
25
21
Oulpul
Clamp
Diodes
No
No
Drivers
Per
Package
2
2
Device
Inpul
Compatibility
~
30
300
33
No
2
-55°C 10 125°C
DOC 10 70°C
Logic
Funcllon
And'
55450A
6A
75450A
6A,9A
55451A
6T
75451A
6T, 9T
And
55452A
55453A
6T
75452A
6T, 9T
Nand
6T
75453A
6T, 9T
Or
55454A
6T
75454A
6T, 9T
Nor
55450B
6A
75450B
6A,9A
And'
55451B
6T
75451B
6T, 9T
And
55452B
6T
75452B
6T,9T
Nand
55453B
6T
75453B
6T, 9T
Or
55454B
6T
75454B
6T, 9T
Nor
55460
6A
75460
6A, 9A
And'
55461
55462
6T
75461
6T,9T
And
6T
75462
6T, 9T
Nand
55463
6T
75463
6T, 9T
Or
55464
6T
75464
6T, 9T
Nor
9665
6B, 9B
14-V to 25-V P-MOS
9666DM
6B
9666
6B, 9B
Inverting
TTL and 5-V CMOS
9667DM
6B
9667
6B, 9B
Buffer
6-V to 15-V P-MOS. CMOS
9668DM
6B
9668
6B, 9B
TTL, DTL
TTL, DTL
~
35
lYpe And Package'
TTL, DTL
I\)
TTL, DTL, CMOS, P-MOS
Yes
50
80
50
55
350
300
200
33
. Wltn output transistor base connected externally to output of gate
t All plastic packages are on copper lead frames
(350mA)
No
7
2
TTL, DTL
55471
6T
75471
6T, 9T
And
55472
6T
75472
6T,9T
Nand
55473
6T
75473
6T, 9T
Or
55474
6T
75474
6T. 9T
Nor
MOS AND CCD DRIVERS
Supply
Vollage
(V)
--'
I
--'
Propagalion
Delay
Time (Typical)
(ns)
VOH
(Min)
(V)
VOL
(Max)
(V)
Device
Type
Package
Type
Drivers
Per
Package
Features
Vee t5
Voo ~ 0 10 -30
50
+3.5
0.2
9624
6A,9A
2
• Dual MOS-to-TTL converter
• Non-inverting buffer
Vee ----r5
Voo ~ 0 to -30
50
+2.6
0.2
9625
6A,9A
2
• Dual MOS-to-TTL converter
• Inverting buffer
Veel "'-- +5
Vee2 - ~510 +12
9
VCC2 - 0.5
0.3
9643
6T, 9T, 6A, 9A
2
•
•
•
•
•
•
Veel ,-- +5
Vee2 ~ +510 +12
6
Vce - 0.5
0.3
9644
6T,9T
2
• Dual positive NAND TTL-to-MOS/CCD
• Same features as 9643
VDD - 0.5
0.45
9645
132451
7B,9B
4
• Quad TTL-to-MOS/CCD driver
• Replaces Intel 3245
• Satisfies F464 CCD memory requirements
(-VI +1.0
9646
1DS0026 1
6A,9A
6T,9T
2
• Dual two phase MOS clock driver
• Replaces DS0026
• +1.5Amp output current capability
Vee - +5
voo ~ +12
10
±V ~O to ±20
10
W
(+VI -1.0
Positive AN D TTL-to-MOS/CCD driver
Replaces SN75322 and SN75363
9643/4 does not require two external PNP's
High voltage Schottky technology
VCC3 supply is not needed
Satisfies F464 CCD memory clock
requirements
•
SENSE AMPLIFIERS
Device Type For
Common-
Threshold
Description
Sensitivity
Mode
Range
Typel Propagation
Delay
Of
Time
Output
Temperature Range
Package
-55°C to 125°C
O°C t070°C
Type
75320
68
68,98
1
• Internally compensated ref. amp
• Provides memory data register
• Complementary outputs
75324
68
68,98
2
• Internally compensated ref. amp
• Independent strobes
7528
68
68,98
2
• Independent strobes
• Test points for strobe timing
adjustment
75232
68
68.98
2
• Independent strobes
• Internally compensated reference
amplifier
753234
68
68,98
2
• Independent strobes
• Internally compensated reference
amplifier
75238
68
68,98
2
• Independent strobes
• Internally compensated reference
amplifier
• Test points for strobe timing
adjustment
75107A'
6A,31
6A,9A
2
• Independent strobes
2
• Independent strobes
2
55320
±2.5mV
R
35ns
±2.5mV
R
25ns
±4.0mV
R
25ns
O-C
25ns
R
25ns
55324
5528
Core Memory
Sense
Amplifiers
55232
±4.0mV
±2.5V
553234
±2.5mV
Units
Per
Package
,
~
Additional Features
~
"""
55238
±4.0mV
R
25ns
T-P
17ns
55101'
±25mV
±3V
MOS-Memory
Sense
Amplifiers
55108A'
±25mV
±10mV
t T-P --::: Totem Pole. O-C
±3V
O-C
19ns
75108A'
6A,31
6A,9A
T-P
17ns
75201'
6A,9A
O-C
19ns
7520B'
6A,9A
±3V
• Independent strobes
= Open Collector, R.;;:: Resistor Pull-Up
See Line Circuit Section for details
MEMORY DRIVERS*
Maximum
Output
Cunent
Description
Propagallon
Delay
Time
(ns)
Dual
Sink/Source
Memory
Drivers
Sink Memory
35
55325
35
Vccl-5V
VCC2 variable
to 24 V
55327
30
VCC =5 V
55326
Drivers
Quadruple
Memory
Drivers
- - _ .. _ -
Device Type For
Temperature Range
_55' C 10 125' C O'C to 70'C
Vccl-5V
VCC2 variable
to 24 V
600mA
Quadruple
Power
Supplies
--'-----
Package
Type
Additional Features
75325
78, 4L
78, 98
-Also used for high-voltage, high-current
driver applications
-Output transient voltage protection
-Source output terminals swing between
VCC2 and ground
75327
78,4L
78, 98
-Also used for high speed magnetic
memory applications
-Output transient voltage protection
-Output capable of swinging between
VCC2 and ground
75326
78,4L
78, 98
-Also used for high-voltage, high-current
driver applications
-Output transient voltage protection
.24V output capability
----
'Also see MOS/CCO driver section
,
~
~
(Jl
SPECIAL FUNCTIONS-TIMERS AND COUNTERS
Supply
Voltage
V (Max)
Timing
Error
200
+18
1.0
5S, 6T, 9T, 6A
TTL
200
+18
1.0
6A,9A
TTL
5.0
+18
0.5
78,98
Time
Delay
Hours
Free Running
Frequency
(kHz)
Output
Compatibility
Single Timer
1.0
100
TTL
~A556
Dual Timer
1.0
100
~A2240
Programmable Timer-Counter
120
Device
Number
Function
~A555
-
Output
Current
(rnA)
Package(s)
%
•
SPECIAL FUNCTIONS-TRANSISTOR AND DIODE ARRAYS
Function
Balanced
Input
uA72S'
Temp Controlled
Diff Pair
•
uA301S'
Matched Transistor
Array
•
uA301SA'
Matched Transistor
Array
•
•
uA3019'
Quad Plus Two
Diode Array
-
-
-.
-
-
-
uA302S'
Dual Diff Amp
Transistor Array
-
-
--
-
-
-
uA303S'
Dual Darlington
Transistor Array
•
•
•
-
•
uA3039'
Hex Ultra Fast
Diode Array
-
-
-
-
uA304S'
Diff Pair Plus
Three Transistors
·
-
uA3046
Dill Pair Plus
Three Transistors
·
·
•
uA3054
Dual Diff Amp
Transistor Array
-
uA3086
Dual Diff Plus
Th ree Transistors
•
Device
Number
-'
~
0>
'Military grade available
Balanced
Output
Low
Multiple
Unit
Wideband
AGC
Capability
-
-
-
-
•
·
-
•
•
Switching
Application
VCBo-V
VCEo-V
VEBo-~
-
40
30
5.0
5.0
2.5
5U
·
-
20
15
5.0
50
5.0
50
•
-
30
15
5.0
50
2.0
50
-
-
-
-
5.0
50
-
20
15
5.0
50
5.0
50
-
-
30
15
5.0
50
-
50
-
-
.
-
-
-
-
5.0
50
-
•
•
-
20
15
5.0
50
5.0
6A
-
-
•
•
-
20
15
5.0
50
5.0
6A,9A
-
-
-
-
-
20
15
5.0
50
5.0
6A,9A
•
-
-
•
-
20
15
5.0
50
-
6A,9A
Noise
· .
·
·
·
.
Ic-MA VBE or Vo
PackageCs)
LINEAR INDUSTRY CROSS REFERENCE
Li near I ndustry Cross Reference ......................................................... 2-3
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
1458CE
1458CP
1458E
1458P
1558E
3207A
3245
527
532
536
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
Part
Number
flA1458CHC
flA1458CTC
flA1458HC
flA1458TC
flA1558HM
9645
9645/3245
flA760HM
flA798TC
flA740AHM
Fairchild
Direct
Replacement
741CJ
741CP
747BE
747BL
747CE
flA741PC
flA741TC
flA747HfvI
flA747DM
flA747HC
747CJ
747CL
748BE
748BH
748BL
flA747PC
flA747DC
flA748HM
flA748FM
flA748DM
flA748HC
flA748DC
flA748TC
556CJ
709AE
709AH
709AL
709BE
flA556PC
flA709AHM
flA709AFM
flA709ADM
flA709HM
748CE
748CL
748CP
75S107
75S108
709BH
709BL
709CE
709CJ
709CL
flA709FM
flA709DM
flA709HC
flA709PC
flA709DC
75S207
75S208
75322
75361
75361A
710BE
710BH
710BL
710CE
710CL
flA710HM
flA710FM
flA710DM
flA710HC
flA710DC
75363
75450N
78M05BE
78M05CE
78M06BE
9643DC
75450APC
flA78M05HM
flA78M05HC
flA78M06HM
711 BE
711 BH
711 BL
711CE
711 CJ
flA711HM
flA711 FM
flA711DM
flA711HC
flA711 PC
78M06CE
78M08BE
78M08CE
78M12BE
78M12CE
flA78M06HC
flA78M08HM
flA78M08HC
flA78M12HM
flA78M12HC
711 CL
723BE
723BL
723CE
723CJ
flA711DC
flA723HM
flA723DM
flA723HC
flA723PC
78M15BE
78M15CE
78M20BE
78M20CE
78M24BE
flA78M15HM
flA78M15HC
flA78M20HM
flA78M20HC
flA78M24HM
723CL
733DC
733DM
733FM
flA723DC
flA733DC
flA733DM
flA733FM
flA78M24HC
flA8T26A
flA8T26APC
flA8T26ADC
fl A8T28
733HC
733HM
741 BE
741 BH
741 BL
741CE
flA733HC
flA733HM
flA741HM
flA741FM
flA741OM
flA741HC
78M24CE
8216
8T26A
8T26A
8T28
AN217
AM26LS29
AM26LS30
AM26S10
AM26S11
AN559
2-3
Fairchild
Functional
Equivalent
•
75107APC
75108APC
75207PC
75208PC
9643DC
9644DC
9643DC
flA721 PC
9634
9636A
9640
9641
I-'A0802
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
Fairchild
Functional
Equivalent
Part
Number
Fairchild
Direct
Replacement
MA703HC
MA703HC
MA703HC
CA3064E
CA3064T
CA3065E
CA3070E
CA3071 E
MA3064PC
MA3064HC
MA3065PC
MA780PC
MA781 PC
CA3008
CA3008A
CA3010
CA3010A
CA3011T
MA741 FM
MA741 FM
MA741HM
MA741HM
MA753TC
CA3072E
CA3075E
CA3078AS
CA3078AT
CA3078S
MA746PC
MA3075PC
CA3012T
CA3013T
CA3014T
CA3015
CA3015A
MA753TC
MA753TC
MA753TC
MA741HM
MA741HM
CA3078T
CA3079
CA3085
CA3085A
CA3085AF
MA776HC
MA742DC
MA723HC
MA723HC
MA723DC
CA3016
CA3016
CA3018
CA3018A
CA3019
MA741FM
MA741FM
CA3085AS
CA3085B
CA3085BF
CA3085BS
CA3085F
MA723DC
MA723HM
MA723DM
MA723DC
MA723DC
Part
Number
CA1190
CA1310
CA3004T
CA3005T
CA3006T
CA3021T
CA3022T
CA3023T
CA3026
CA3028AT
TDA1190Z
MA1310
MA3018HM
MA3018HM
MA3019HM
MA757DC
MA757DC
MA757DC
CA3085S
CA3086
CA3088E
CA3089E
CA3090E
MA3026HM
MA703HC
CA3028T
CA3029
CA3029A
CA3030
CA3030A
MA703HC
MA741TC
MA741TC
MA741TC
MA741TC
CA3036
CA3037
CA3037A
CA3038
CA3038A
MA3036HM
CA3039
CA3041 E
CA3024E
CA3043
CA3044T
MA3039HM
CA3045
CA3046
CA3045
CA3058E
CA3059
MA3045DM
MA3046DC
MA3054DC
CA3123E
CA3126Q
CA3134
CA3458S
CA3458T
CA3558S
CA3558T
CA3741CS
CA3741CT
CA3741S
MA741DM
MA741DM
MA741DM
MA741DM
MA776DM
MA776HM
MA776TC
MA723DC
MA3086DC
MA720PC
MA3089PC
MA758PC
MA720PC
MA787PC
TDA1190
1458TC
1458HC
1558HM
1558HM
MA741TC
MA741HC
MA741HM
MA3065PC
MA3065PC
MA3065PC
MA3064
CA3741T
CA3747CE
CA3747CF
CA3747CT
MA741HM
MA747PC
MA742DC
MA742DC
CA3747E
CA3747F
CA3747T
CA3748CS
CA3748CT
MA747DM
MA747DM
MA747HM
MA748TC
MA748HC
2-4
MA747DC
MA747HC
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
CA37488
CA3748T
CA758E
OAC-08
OAC-08A
Fairchild
Direct
Replacement
Part
Number
j.LA0801C
j.LA0801 E
9646/0026
083645
083691
083692
088834
088835
9645/3245
Fairchild
Direct
Replacement
LH0061K
LH101H
LH201H
LH2101AO
LH740AH
j.LA748HM
j.LA748HC
j.LA758PC
j.LA0801
I'A0801A
OAC-08C
OAC-08E
080026
083486
083487
0878L8120
088T26A
HA1156
HA11226
LA 1201
Fairchild
Functional
Equivalent
j.LA791KM
j.LA741HM
j.LA741HM
j.LA747AOM
j.LA740AHM
9637A
9634
LM101AO
LM101AF
LM101AH
LM1010
LM101 H
j.LA101AOM
j.LA101AFM
j.LA101AHM
j.LA101DM
j.LA101HM
9636A
9634
j.LA8T26A
j.LA8T26A
LM1011
LM102H
LM104H
LM105H
LM106F
j.LA102HM
j.LA104HM
j.LA105HM
9637A
j.LA8T26A
j.LA 1310
j.LA7300
j.LA721 PC
j.LA710FM
LM106H
LM107H
LM108AO
LM108AF
LM108AH
j.LA107HM
j.LA108AOM
j.LA108AFM
j.LA108AHM
j.LA710HM
j.LA1080M
j.LA108FM
j.LA108HM
j.LA109KM
j.LA111HM
j.LA78H05KC
j.LA78H12KC
j.LA78H15KC
j.LAF111HM
j.LAF155AHM
LM1080
LM108F
LM108H
LM109K
LM111 H
LF155H
LF156AH
LF156H
LF157AH
LF157H
j.LAF155HM
j.LAF156AHM
j.LAF156HM
j.LAF157AHM
j.LAF157HM
LM117
LM120H-05
LM120H-12
LM120H-15
LM120K-05
LF211 H
LF311H
LF355AH
LF355H
LF356A
j.LAF211 HM
j.LAF311HC
j.LAF355AHC
j.LAF355HC
j.LAF356AHC
LM120K-12
LM1240
LM1303N
LM1304N
LM1307N
LF356H
LF357
LF357A
LHOO02
LHOO21CK
j.LAF356HC
j.LAF357HC
j.LAF357AHC
8HOO02
j.LA 1310
j.LA1390M
j.LA139AOM
j.LA791 KC
LM1310
LM139
LM139A
LM1414J
LM1458H
j.LA791KM
j.LA791KMQB
j.LA759HM
j.LA791KC
j.LA791 KM
LM1458N
LM1488J
LM1489AJ
LM1489J
LM1496H
j.LA1458TC
j.LA1488
j.LA1489A
j.LA1489
j.LA796HC
2-5
I
j.LA7300
LA81405
LA81412
LA81415
LF111 H
LF155AH
LH0021 K
LH0021 K/883
LHOO41
LH0061 C
LH0061CK
Fairchild
Functional
Equivalent
j.LA78GKM
j.LA79M05HM
j.LA79M12HM
j.LA79M15HM
j.LA7905KM
j.LA1240M
j.LA7912KM
j.LA35030M
j.LA749PC
j.LA732PC
j.LA767 PC
j.LA711 DC
j.LA1458HC
96160C
96170C
9617DC
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
LM1496N
LM1514J
LM1558H
LM160H
LM1800N
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
MA796PC
MA711 DM
MA1558HM
MA760HM
MA758PC
Part
Number
Fairchild
Direct
Replacement
LM3018H
LM3019H
LM302H
LM3026H
LM3039H
MA3018HM
MA3019HM
MA302HC
MA3026HM
MA3039HM
MA304HC
MA3045DM
MA3046DC
MA305AHC
MA305HC
LM1820N
LM1829N
LM1841N
LM1850N
LM198
MA720PC
MA787PC
MA2136PC
MAF198
LM304H
LM3045D
LM3046N
LM305AH
LM305H
LM210AF
LM201AH
LM201D
LM201 H
LM202H
MA201AFM
MA201AHM
MA201DM
MA201HM
MA202HM
LM3053N
LM3054N
LM306H
LM3064H
LM3065N
MA753TC
MA3054DC
LM204H
LM205H
LM206F
LM206H
LM20lH
MA204HM
MA205HM
MA20lHM
LM30lH
LM30lN
LM3070N
LM3075N
LM308AD
MA30lHC
MA30lTC
MA780PC
MA3075PC
M308ADC
LM208AD
LM208AF
LM208AH
LM208D
LM208F
MA208ADM
MA208AFM
MA208AHM
MA208DM
MA208FM
LM308AH
LM308D
LM308H
LM308N
LM3086N
MA308AHC
MA308DC
MA308HC
MA308TC
MA3086DC
LM208H
LM209K
LM220H-05
LM220H-12
LM220H-15
MA208HM
MA209KM
LM309K
LM311 H
LM311N
LM320H-05
LM320H-12
MA309KC
MA311HC
MA311TC
LM220K-05
LM220K-12
LM220K-15
LM222N
LM224D
LM2901N
LM2902N
LM2904N
LM2905N
LM2907N
LM291lN
LM301AD
LM301AH
LM301AN
LM3018AH
MA7390PC
MA710FM
MA710HC
MA79M05HM
MA79M12HM
MA79M15HM
MA710HC
MA3064HC
MA3065PC
MA79M05HC
MA79M12HC
MA7905KM
MA7912KM
MA7915KM
MA555TC
LM320H-15
LM320K-05
LM320K-12
LM320K-15
LM320MP-12
MA79M15HC
MA7905KC
MA7912KC
MA7915KC
MA79M12AUC
MA775PC
LM320MP-15
LM320MP-5.0
LM320MP-6.0
LM320MP-8.0
LM320T-12
MA79M15AUC
MA79M05AUC
MA79M06AUC
MA79M08AUC
MA7912UC
LM320T-15
LM320T-18
LM320T c 24
LM320T-5
LM320T-6
MA7915UC
MA7918UC
MA7924UC
MA7905UC
MA7906UC
MA224DM
MA2901 PC
MA2902PC
Fairchild
Functional
Equivalent
MA798TC
MA555TC
MA4151TC
MA7151PC
MA301ADC
MA301AHC
MA301ATC
MA3018HM
2-6
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
Part
Number
Fairchild
Direct
Replacement
LM4250H
LM5108AJ
LM55107AJ
LM55108AJ
LM55109J
75108ADC
55107ADM
55108ADM
55109DM
I'A776HM
LM320T-8
LM323K
LM323K
LM324D
LM324N
8H323KC
I'A78H05KC
I'A324DC
I'A324PC
LM339A
LM340K-05
LM340K-06
LM340K-08
LM340K-12
I'A339ADC
I'A7805KC
I'A7806KC
I'A7808KC
I'A7812KC
LM55110J
LM5524J
LM5528J
LM5534J
LM555CN
55110A
55824
5528DM
558234DM
I'A555TC
LM340K-15
LM340K-18
LM340K-24
LM340T-05
LM340T-06
I'A7815KC
I'A7818KC
I'A7824KC
I'A7805UC
I'A7806UC
LM556CN
LM703LH
LM709CH
LM709CN
LM709H
I'A556PC
I'A703HC
I'A709HC
I'A709PC
I'A709HM
LM340T-08
LM340T-12
LM340T-15
LM340T-18
LM340T-24
I'A7808UC
I'A7812UC
I'A7815UC
I'A7818UC
I'A7824UC
LM710CH
LM710CN
LM710H
LM711CH
LM711 CN
I'A710HC
I'A710PC
I'A710HM
I'A711 HC
I'A711PC
LM711H
LM723CD
LM723CH
LM723CN
LM723D
I'A711HM
I'A723DC
I'A723HC
I'A723PC
I'A723DM
LM723H
LM725AH
LM725CH
LM725H
LM733CD
I'A723HM
I'A725AHM
I'A725HC
I'A725HM
I'A733DC
LM733CH
LM733CN
LM733D
LM733H
LM741CD
I'A733CH
I'A733PC
I'A733DM
I'A733HM
I'A741DC
}1A7307
I'A739PC
TBA820L
LM741CH
LM741CN-08
LM741CN-14
LM741 F
LM741H
I'A741HC
I'A741TC
I'A741 PC
I'A741FM
I'A741HM
I'A555TC
I'A776HM
I'A776HC
I'A776DC
LM746N
LM747CD
LM747CH
LM747CN
LM747D
I'A746PC
I'A747DC
I'A747HC
I'A747PC
I'A747DM
I'A7908UC
LM342P-12
LM342P-15
LM342P-18
LM342P-24
LM342P-5.0
LM342P-6.0
LM432P-8.0
LM350N
LM351 N
LM358H
LM360H
LM376N
LM380N
LM381AN
LM381 N
LM382N
LM383
LM386
LM387N
LM388N
LM390
LM3905N
LM4250H
LM4250CH
LM4250CN
I'A3403DC
I'A3403PC
I'A78C12U1C
I'A78C15U1C
I'A78C18U1C
I'A78C24U1C
I'A78C08U1 C
75453BPC
75453BPC
I'A798HM
I'A760HC
I'A376TC
TBA820L
I'A739DC
I'A739PC
I'A739PC
TDA2002
I'AF398
2-7
Fairchild
Functional
Equivalent
•
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
Part
Number
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
LM747H
°LM748CH
LM748CN
LM748H
LM75107AJ
MA747HM
MA748HC
MA748TC
MA748HM
75107ADC
MC1326P
MC1327
MC1328P
MC1339P
MC1350P
MA746PC
TDA2522
MA746PC
MA749PC
MA757DC
LM75107AN
LM75108AN
LM75109J
LM75109N
LM75110J
75107APC
75108APC
75109DC
75109PC
75110A
MC1351P
MC1352P
MC1353P
MC1355P
MC1357P
MA3065PC
MA757DC
MA757DC
MA3065PC
MA2136PC
LM75110N
LM75150J
LM75150N
LM75154J
LM75154N
75110A
75150DC
75150PC
75154DC
75154PC
MC1358P
MC1364P
MC1370P
MC1371 P
MC1375P
MA3064PC
MA780PC
MA781PC
MA3075PC
LM75207J
LM75207N
LM75208J
LM75208N
LM7524J
75207DC
75207PC
75208DC
75208PC
75S24
MC1391
MC1394P
MC1398P
MC1408L6
MC1408L7
MA1391TC
MA1394TC
LM7524N
LM7528J
LM7528N
LM75325J
LM75325N
75S24
7528DC
7528PC
75325DC
75325PC
MC1408L8
MC1410G
MC1411
MC1412
MC1413
MA0802A
LM7534J
LM7534N
LM7535J
LM7535N
LM75450J
75S234DC
75S234PC
7535DC
7535PC
75450BDC
MC1414L
MC1414P
MC1416
MCi420G
MC1435G
LM75450N
LM75451 N
LM75452N
LM75453N
LM75454N
75450BPC
75451 BTC
75452BTC
75453BTC
75454BTC
MC1435L
MC1437L
MC1437P
MC1438R
MC14443
MA749DC
MA749DC
MA749PC
MA791KC
MA9708
MA732PC
MA7307
MC14447
MC1456CG
MC1456CL
MC1456G
MC1456L
MA9708
MA776HC
MA776DC
MA776HC
MA776DC
MA746PC
MC1458CG
MC1458CP1
MC1458G
MC1458P1
MC1496G
M51728
MC1303P
MC1304P
MC1305P
MC1306
MC1307P
MC1310P
MC1311P
MC1312P
MC1324P
9616DC
9617DC
MA7392
MA749PC
MA732PC
MA767PC
MA1310PC
MA758PC
MA1312PC
2-8
MA3065PC
MA787PC
MA0802C
MA0802B
MA733HC
9665
9666
9667
MA711 DC
MA711PC
9668
MA733HC
MA749DHC
MA1458CHC
MA1458CTC
MA1458HC
MA1458TC
MA796HC
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
MC1496P
MC1508L8
MC1510F
MC1510G
MC1514F
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
Part
Number
pA796PC
pA0802
Fairchild
Direct
Replacement
IlA733FM
IlA733HM
IlA711 FM
MC1712F
MC1712L
MC1723CG
MC1723CL
MC1723G
pA702FM
IlA702DM
IlA723HC
IlA723DC
IlA723HM
MC1514L
MC1520G
MC1535G
MC1535L
MC1537L
IlA711DM
IlA733HM
IlA749HM
IlA749DM
IlA749DM
MC1723L
MC1741CG
MC1741CG
MC1741CL
MC1741CP1
IlA723DM
pA741HC
IlA747HC
IlA741DC
IlA741TC
MC1550G
MC1556G
MC1556L
MC1558G
MC1560G
IlA757DC
IlA776HM
IlA776DM
IlA78MOOHM
MC1741CP2
MC1741F
MC1741G
MC1741L
MC1747CL
IlA741 PC
IlA741FM
IlA741HM
IlA741 OM
IlA747DC
MC1560R
MC1561G
MC1561R
MC1563G
MC1563R
IlA7800KM
IlA78MGHM
IlA78MGHM
IlA79MGHM
IlA79MGHM
MC1747G
MC1747L
MC1748CG
MC1748CP1
MC1748G
IlA747HM
IlA747DM
IlA748HC
IlA748TC
IlA748HM
MC1569G
MC1569R
MC1590
MC1596G
MC1709CG
IlA78MGHM
IlA78GKM
IlA757DC
IlA796HM
IlA709HC
MC1776CG
MC1776G
MC3245
MC3301P
MC3302P
IlA776HC
IlA776HM
9645/3345
IlA3301 PC
IlA3302PC
MC1709CL
MC1709CP1
MC1709CP2
MC1709F
MC1709G
IlA709DC
IlA709TC
IlA709PC
IlA709FM
IlA709HM
MC3360
MC3401 P
MC3403L
MC3403P
MC3425
IlA3401 PC
IlA3403DC
IlA3403PC
MC1709L
MC1710CG
MC1710CL
MC1710CP
MC1710F
IlA709DM
IlA710HC
IlA710DC
IlA710PC
IlA710FM
MC3430
MC3433
MC3440
MC3441
MC3443
MC1710G
MC1710L
MC1711 CG
MC1711CL
MC1711CP
IlA710HM
IlA710DM
IlA711 HC
IlA711D C
IlA711PC
MC3448A
MC3456
MC3476
MC3486
MC3487
IlA3448A
IlA556PC
IlA776PC
MC1711F
MC1711G
MC1711L
MC1712CG
MC1712CL
IlA711 FM
IlA711HM
IlA711DM
IlA702HC
IlA702DC
MC3503L
MC75107L
MC75107P
MC75108L
MC75108P
IlA3503DM
75107ADC
75107APC
75108ADC
75108APC
IlA1558HM
2-9
Fairchild
Functional
Equivalent
•
IlA7307
IlA7390TC
75107APC
75108APC
9642DC
9642DC
9642DC
9637A
9634
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
Part
Number
Fairchild
Direct
Replacement
MC75109L
MC75109P
MC75110L
MC75110PC
MC75207L
75109DC
75109PC
75110ADC
75110APC
75207DC
MC7824CK
MC7824CP
MC7905CK
MC7905CP
MC7906CK
jlA7824KC
jlA7824UC
jlA7905KC
jlA7905UC
jlA7906KC
MC75207P
MC75208L
MC75208P
MC7524L
MC7524P
75207PC
75208DC
75208PC
75824
75824
MC7906CP
MC7908CK
MC7908CP
MC7912CK
MC7912CP
jlA7906UC
jlA7908KC
jlA7908UC
jlA7912KC
jlA7912UC
MC7528L
MC7528P
MC75325L
MC75325P
MC7534L
7528DC
7528PC
75325DC
75325PC
755234DC
MC7915CK
MC7915CP
MC7918CK
MC7918CP
MC7924CK
IlA7915KC
jlA7915UC
jlA7918KC
IlA7918UC
jlA7924KC
MC7534P
MC75365
MC75450L
MC75450P
MC75451 P
755234DC
75450BDC
75450BPC
75451 BTC
MC7924CP
MC8T13L
MC8T13P
MC8T14L
MC8T23P
IlA7924UC
jlA8T13DM
jlA8T13PC
IlA8T14DM
jlA8T23PC
MC75452P
MC75453P
MC75454P
MC75491P
MC75492P
75452BTC
75453BTC
75454BTC
75491 PC
75492PC
MC8T24P
MC8T26A
MFC4060A
MFC4062A
MFC4063A
IlA8T24PC
IlA8T26A
9645PC
Fairchild
Functional
Equivalent
jlA78MGT2C
jlA78MGT2C
jlA78MGT2C
MC7705CP
MC7706CP
MC7708CP
MC7712CP
MC7715CP
jlA78M05UC
jlA78M06UC
IlA78M08UC
jlA78M12UC
IlA78M15UC
MFC4064A
MFC6030A
MFC6032A
MFC6033A
MFC6034A
jlA78MGT2C
jlA78MGT2C
jlA78MGT2C
jlA78MGT2C
jlA78MGT2C
MC7718CP
MC7720CP
MC7724CP
MC7805CK
MC7805CP
jlA7818UC
jlA78M20UC
jlA78M24UC
jlA7805KC
jlA7805UC
MFC8000
MFC8001
MFC8002
MFC8030
MFC8070
jlA739PC
jlA739PC
IlA739PC
jlA703HC
jlA742DC
MC7806CK
MC7806CP
MC7808CK
MC7808CP
MC7812CK
jlA7806KC
jlA7806UC
jlA7808KC
IlA7808UC
IlA7812KC
MLM101AG
MLM104G
MLM105G
MLM107G
MLM109G
MC7812CP
MC7815CK
MC7815CP
MC7818CK
MC7818CP
jlA7812UC
jlA7815KC
IlA7812UC
jlA7812KC
jlA7812UC
MLM109K
MLM110G
MLM201AG
MLM204G
MLM205G
2-10
jlA101AHM
IlA104HM
jlA105HM
jlA107HM
jlA78M05HM
IlA109KM
jlA110HM
jlA201AHM
IlA204HM
IlA205HM
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
Part
Number
N8T13B
N8T13F
N8T14B
N8T14F
N8T15F
MLM207G
MLM209G
MLM209K
MLM210G
MLM301AG
,uA207HM
MLM301AP1
MLM304G
MLM305G
MLM307G
MLM309G
,uA301ATC
,uA304HC
,uA305HC
IlA307HC
MLM309K
MLM310G
MLM311G
MLM311P1
ML 1408-6L
IlA309KC
IlA310HC
IlA311HC
IlA311TC
IlA0802CDC
N8T26A
OP-02
OP-04
OP-05
OP-07
ML 1408-7L
ML 1408-8L
ML 1508-8L
MMH0026
NE515A
IlA0802BDC
IlA0802ADC
IlA0802DM
9646/0026
IlA733PC
PA239A
RC1488D
RC1489AD
RC1489D
RC4136D
,uA209KM
,uA210HM
,uA301AHC
,uA78M05HM
,uA7805KM
N8T16F
N8T23B
N8T23F
N8T24B
N8T24F
IlA78M05HC
Fairchild
Direct
Replacement
,uA8T13PC
,uA8T13DC
,uA8T14PC
,uA8T14DC
9616DC
9627DC
,uA8T23PC
IlA8T23DC
IlA8T24PC
IlA8T24DC
IlA8T26A
IlA741AHM
IlA741AHM
IlA714HC
IlA714HC
IlA 1488
IlA1489A
IlA1489
1lA4136DC/DM
NE515K
NE521A
NE521F
NE522A
NE522F
IlA733HC
75107APC
75107ADC
75108APC
75108ADC
RC4136DB
RC4136DP
RC4151
RC4152
RC4558DN
1lA4136PC
1lA4136PC
1lA4151
NE526A
NE526K
NE527K
NE529K
NE536T
IlA760DC
IlA760HC
IlA760HC
IlA760HC
IlA740HC
RC4558T
RC55109D
RC555DN
RC556D
RC556DP
1lA4558HC
55109DM
IlA555TC
IlA556DC
,uA556PC
IlA7300
IlA723PC
IlA723HC
RC733TF
RC75107AD
RC75107AP
RC75108AD
RC75108ADP
IlA733HC
75107ADC
75107APC
75108ADC
75108APC
75109DC
75109PC
75110ADC
75150DC
75154DC
75S24DC
75S24PC
7528DC
7528PC
75325DC
NE545
NE550A
NE550L
NE555V
NE556A
IlA740HC
IlA555TC
,uA556PC
NE556F
NE592A
NE645
N10145
N10149
IlA556DC
10145A
10146
RC75109D
RC75109DP
RC75110D
RC75150D
RC75154M
N5071A
N5072A
N5558T
N5558V
N5570B
IlA781 PC
IlA746PC
IlA1458HC
IlA1458TC
IlA780PC
RC7524M
RC7524MP
RC7528M
RC7528MP
RC75325M
IlA733PC
IlA7300
2-11
Fairchild
Functional
Equivalent
1lA4558TC
IlA739PC
9616DC
9617DC
9617DC
IlA7151
,uA7151
•
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
Part
Number
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
RC75325MP
RC8T13M
RC8T13MP
RC8T14M
RC8T14MP
75325PC
IlA8T13DC
IlA8T13PC
IlA8T14DC
IlA8T14PC
SN52702L
SN52709J
SN52709L
SN52710J
SN52710L
IlA702HM
IlA709DM
IlA709HM
IlA710DM
IlA710HM
RC8T23M
RC8T23MP
RC8T24M
RC8T24MP
RC9621 D
IlA8T23DC
IlA8T23PC
IlA8T24DC
IlA8T24PC
9621DC
SN52711J
SN52711L
SN52723J
SN52723L
SN52741J
IlA711DM
IlA711HM
IlA723DM
IlA723HM
IlA741DM
RC9622D
RM4136D
RM55107AD
RM55108AD
RM55110D
9622DC
1lA4136DM
55107ADM
55108ADM
55110DM
SN52741L
SN52747J
SN52747L
SN52748J
SN52748L
IlA741HM
IlA747DM
IlA747HM
IlA748DM
IlA748HM
RM5524M
RM5525M
RM55325M
RM555T
RM556D
5524DM
5525DM
55325DM
IlA555HM
IlA556DM
SN52771J
SN52771 L
SN52777J
SN52777L
SN52810J
RM733TF
RM8T13M
RM8T14M
SE515K
SE526A
IlA733HM
IlA8T13DM
IlA8T14DM
IlA733HM
IlA760DM
SN52810L
SN52811 J
SN52811 L
SN52820J
SN529K
IlA710HM
IlA711DM
IlA711 HM
IlA711DM
IlA733HC
SE526K
SE527K
SE529A
SE529K
SE536T
IlA760HM
IlA760HM
IlA733DM
IlA760HM
IlA740HM
SN5510FA
SN5510L
SN55107AL
SN55107BJ
SN55108AJ
IlA833FM
IlA733HM
SE550L
SE592K
SH76008
SH76018
SN2660JA
IlA723HM
IlA733HM
TDAA2002
TDA2002
IlA776DM
SN551088J
SN55109J
SN5511FA
SN5511 L
SN55110J
55108BDM
55109DM
SN52L022L
SN52L044JA
SN52309LA
SN52506J
SN52510L
IlA798HM
IlA3503DM
IlA78M05HM
IlA711DM
IlA710HM
SN55112J
SN55114J
SN55114SB
SN55115J
SN55115SB
55112DM
9614DM
9614FM
9615DM
9615FM
SN52514J
SN52520J
SN52558L
SN52660L
SN52702J
IlA711DM
IlA710DM
SN5512L
SN55121J
SN55122J
SN55123J
SN55124J
55121DM
55122DM
55123DM
55124DM
IlA1558HM
IlA776HM
IlA702DM
2-12
IlA776DM
IlA776HM
IlA777DM
IlA777HM
IlA710DM
55107ADM
55107BDM
55108ADM
IlA733FM
IlA733HM
55110ADM
IlA733HM
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
Part
Number
Fairchild
Direct
Replacement
SN5514L
SN55207J
SN55208J
SN55234J
SN5524J
55207DM
55208DM
55S234DM
55S24DM
SN72376P
SN72440J
SN72440N
SN72506J
SN72506N
SN55325J
SN55325SB
SN55326SB
SN55327SB
SN55450BJ
55325DM
55325FM
55326FM
55327FM'
55450BDM
SN72510J
SN72510L
SN72510N
SN72514J
SN72514N
SN55450J
SN55451 BL
SN55451L
SN55452BL
SN55452L
55450DM
55451 BHM
55451 HM
55452BHM
55452HM
SN72555P
SN72556N
SN72558L
SN72558P
SN72660JA
SN55453BL
SN55453L
SN55454BL
SN55454L
SN55460J
55453BHM
55453HM
55454BHM
55454HM
55460DM
SN72660L
SN72660N
SN72660P
SN72702J
SN72702L
I'A702DC
I'A702HC
SN55461L
SN55462L
SN55463L
SN55464L
SN71710J
55461 HM
55462HM
55463HM
55464HM
I'A710DC
SN72709J
SN72709L
SN72709P
SN72710L
SN72710N
I'A709DC
I'A709HC
I'A709TC
I'A710HC
I'A710PC
I'A711 DC
I'A711HC
I'A711 PC
I'A733HM
I'A376TC
I'A742DC
I'A742DC
I'A711DC
I'A711PC
I'A710DC
I'A710HC
I'A710PC
I'A711DC
I'A711 PC
I'A555TC
I'A556PC
I'A1458HC
I'A 1458TC
I'A776DC
I'A776HC
I'A776DC
I'A776TC
SN72L022L
SN72L022P
SN72L044JA
SN72L044N
SN72301AN
I'A301ADC
SN72711 J
SN72711 L
SN72711N
SN72720J
SN72720N
SN72301L
SN72301 P
SN72304L
SN72305AL
SN72305L
I'A301AHC
I'A301ATC
I'A 104HM
I'A305AHC
I'A305HC
SN72723J
SN72723L
SN72723N
SN72733J
SN72733L
I'A723DC
I'A723HC
I'A723PC
I'A733DC
I'A733HC
SN72307L
SN72307P
SN72308AL
SN72308AN
SN72308L
I'A307HC
I'A307TC
I'A308AHC
I'A308ADC
I'A308HC
SN72733N
SN72741J
SN72741L
SN72741N
SN72741P
I'A733PC
I'A741DC
I'A741HC
I'A741PC
I'A741TC
SN72308N
SN72309LA
I'A308DC
SN72310L
SN72311 L
SN72311 P
I'A310HC
I'A311HC
I'A311TC
SN72747J
SN72747L
SN72748J
SN72748L
SN72748N
I'A747DC
I'A747HC
I'A748DC
I'A748HC
I'A748DC
I'A798HC
I'A798TC
I'A3403DC
I'A3403PC
I'A78M05HC
2-13
Fairchild
Functional
Equivalent
I'A710DC
I'A710PC
•
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Fairchild
Functional
Equivalent
Part
Number
/lA776DC
/lA776HC
/lA776DC
/lA776TC
SN75121N
SN75122J
SN75122N
SN75123J
SN75123N
75121PC
75122DC
75122PC
75123DC
75123PC
75124DC
75124PC
/lA710DC
SN75124J
SN75124N
SN75124L
SN7514P
SN75150J
SN72810L
SN72810N
SN72811J
SN72811 L
SN72811 N
/lA710HC
/lA710PC
/lA711 DC
/lA711 HC
/lA711 PC
SN75150P
SN75152J
SN75154J
SN75182N
SN75183N
75150PC
9627DC
75154DC
SN72820J
SN72820N
SN7496
SN7497
SN7510L
/lA711 DC
/lA711 PC
SN75188J
SN75189AJ
SN75189J
SN7520
SN75207J
1488DC
1489ADC
1489DC
75S20
75207DC
Part
Number
Fairchild
Direct
Replacement
SN72748P
SN72771J
SN72771L
SN72771 N
SN72771 P
/lA748TC
SN72777J
SN72777L
SH72777N
SN72777P
SN72810J
/lA777DC
/lA777HC
/lA777DC
/lA777TC
7496
7497
/lA733HC
Fairchild
Direct
Replacement
75150DC
SN75107AJ
SN75107AN
SN75107BJ
SN75107BN
SN75108AJ
75107ADC
75107APC
75107BDC
75107BPC
75108ADC
SN75207N
SN75208J
SN75208N
SN75224J
SN75224N
75207PC
75208DC
75208PC
75S24DC
75S24PC
SN75108AN
SN75108BJ
SN75108BN
SN75109J
SN75109N
75108APC
75108BDC
75108BPC
75109DC
75109PC
SN75225J
SN75225N
SN75232J
SN75232N
SN75234J
75225DC
75225PC
75232DC
75232PC
75S234DC
75S234PC
75235DC
75235PC
75238DC
75238PC
SN7511 L
SN7511 N
SN75110AJ
SN75110AJ
SN75110J
75110ADC
75110APC
75110ADC
SN75234N
SN75235J
SN75235N
SN75238J
SN75238N
SN75110N
SN75112J
SN75112N
SN75114J
SN75114N
75110APC
75112DC
75112PC
9614DC
9614PC
SN7524J
SN7524N
SN7528J
SN7528N
SN75325J
75S24DC
75S24PC
7528DC
7528PC
75325DC
SN75115J
SN75115N
SN7512L
SN7512N
SN75121J
9615DC
9615PC
SN75325N
SN75326J
SN75236N
SN75327J
SN75327N
75325PC
75326DC*
75326PC*
75327DC
75327PC
/lA733HC
/lA733PC
/lA733HC
/lA733PC
75121DC
2-14
Fairchild
Functional
Equivalent
/lA733HC
/lA733PC
9616DC
9616DC
9617DC
9615DC
9614DC
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
Fairchild
Direct
Replacement
SN7534J
SN7534N
SN75450BJ
SN75450BN
SN75450N
75S234DC
75S234PC
75450BDC
75450BPC
75450BPC
SN76242N
SN76243N
SN76246N
SN7629BN
SN76545
}lA7BOPC
}lA7B1PC
}lA746PC
SN75451 BL
SN75451 BP
SN75451 P
SN75452BL
SN75452BP
75451BHC
75451BTC
75451BTC
75452BHC
75452BTC
SN76565N
SN76591P
SN76594P
SN76600P
SN76635N
}lA3064PC
}lA1391TC
}lA1394TC
SN75452P
SN75453BL
SN75453BP
SN75453P
SN75454BL
75452BTC
75453BHC
75453BTC
75453BTC
75454BHC
SN76642N
SN76650N
SN76666N
SN76669N
SN76675N
SN75454P
SN75460J
SN75460N
SN75461L
SN75461L
75454BTC
75460DC
75460PC
75461HM
75462HM
SN7667BP
SN766B9N
SSS725AJ
SSS725BJ
SSS725EJ
SN75461P
SN75463P
SN75464L
SN75464P
SN75471L
75461TC
75463TC
75464HM
75464TC
75471HC
SSS741 CJ
SSS741J
SSS747CK
SSS747CP
SSS747K
SN75471P
SN75472L
SN75472P
SN75473L
SN75473P
75471TC
75472HC
75472TC
75473HC
75473TC
SSS747P
SSS140BA-6
SSS140BA-7
SSS140BA-B
SSS150BA-B
SN75474L
SN75474P
SN75491N
SN75492N
SN76001N
75474HC
75474TC
75491 PC
75492PC
TBA641A12
S555BT
S5596K
SBT13F
SBT14F
SBT15F
SN76005ND
SN76024ND
SN76104N
SN76105N
SN76111N
SN76115
SN76116N
SN76131N
SN76149N
SN76227
Fairchild
Functional
Equivalent
Part
Number
SBT16F
TA7157
TAA630S
TBA396
TBA510
p.A706BPC
}lA706BPC
p.A732PC
p.A732PC
p.A767PC
TBA520
TBA530
TBA540
TBA560C
TBA570
p.A1310
p.A75BPC
p.A739PC
}lA749PC
TDA2522
2-15
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
}lA7B7PC
TBA920
}lA757PC
}lA720PC
}lA2136PC
p.A757PC
p.A3065PC
p.A2136PC
}lA3075PC
p.A753TC
p.A30B9PC
p.A725AHM
p.A725EHM
p.A725EHC
p.A741 EHC
p.A741AHM
p.A747EHC
p.A747EDC
p.A747AHM
p.A747ADM
}lAOB02C
p.AOB02B
p.AOB02A
}lAOB02
p.A155BHM
p.A796H
p.ABT13DM
p.ABT14DM
9616DM
9627DM
p.A1310
TAA630S
TDA2522
TDA2560
TBA510
TBA520
TBA530
TBA540
TBA560C
TDA2522
TDA2530
TDA2560
p.A721PC
•
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
Part
Number
Fairchild
Direct
Replacement
TBA641A12
TBA641 B11
TBA800
TBA810AS
TBA810DS
TBA641A12
TBA641B1l
TBA800
TBA810AS
TBA810DS
ULN2121A
ULN2122A
ULN2124A
ULN2126A
ULN2127A
TBA810DAS
TBA810S
TBA920
TBA920S
TBA970
TBA810DAS
TBA810S
TBA920
TBA920S
TBA970
ULN2128A
ULN2129A
ULN2136A
ULN2137A
ULN2165A
IlA767PC
TBA990
TCA600
TCA610
TCA900
TCA910
TBA990
TDA2522
IlA7392
IlA7392
IlA7392
IlA7392
ULN2209M
ULN2210A
ULN2224A
ULN2228A
ULN2244A
IlA753TC
IlA783P4C
ULN2298A
ULX2262A
ULX2264A
ULX2267A
ULX2289A
IlA787PC
IlA3064PC
IlA3067PC
IlA3089PC
YKB2219
IlA709CA
IlA709CT
IlA7090
IlA709T
IlA1310
IlA709PC
IlA709HC
IlA709FM
IlA709HM
IlA710CA
IlA710CT
IlA7100
IlA710T
IlA711CA
IlA710HC
IlA710HC
IlA710FM
IlA710HM
IlA711PC
IlA711CK
IlA711 K
IlA723CA
IlA723CL
IlA723L
IlA711HC
IlA711HM
IlA723PC
IlA723HC
IlA723HM
IlA711 HM
IlA733A
IlA733CK
IlA733C1
IlA733K
IlA7330A
IlA733DM
IlA733HC
IlA733DC
IlA733HM
IlA733PC .
IlA2136PC
IlA3065PC
IlA7331
IlA740CT
IlA741CA
IlA741CT
IlA741CV
IlA733DM
IlA740HC
IlA741PC
IlA741HC
IlA741TC
TCA940
TDA1170
TDA1270
TDA1037
TDA1190
TDA1190Z
TDA1327
TDA2002
TDA2002A
TDA2150
TDA2160
TDA2521
TDA2522
TDA2530
TDA2560
TDA2590
TDA2610
TL081
TL081A
TL810
TL811
ULN2001A
ULN2002A
ULN2003A
ULN2004A
ULN2111A
ULN2113A
ULN2114A
ULN2114K
ULN2120A
TDA1170
TDA1270
TDA2002
TDA1190
TDA1190Z
TDA2522
TDA2002
TDA2002A
TDA2560
TDA2522
TDA2521
TDA2522
TDA2530
TDA2560
TDA2590
TDA1190
IlAF771C
IlAF771
IlA710HM
9665
9666
9667
9668
IlA746PC
IlA746HC
IlA732PC
2-16
Fairchild
Functional
Equivalent
IlA767PC
IlA732PC
IlA780PC
IlA739PC
IlA781 PC
IlA3075PC
IlA2136PC
IlA720PC
IlA3065PC
IlA758PC
IlA788PC
IlA788PC
IlA758PC
IlA787PC
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
~A741T
~A741HM
~A7812CKC
~A7812UC
~A747CA
~A747PC
~A7812MKA
~A7812KM
~A747CK
~A747HC
~A7815CKA
~A7815KC
~A747K
~A747HM
~A7815CKC
~A7815UC
~A748CA
~A748DC
~A7815MKA
~A7815KM
~A748CT
~A748HC
~A7818CKC
~A7818UC
~A748CV
~A748TC
~A7818MKA
~A7818KM
~A748T
~A748HC
~A7824CKC
~A7824UC
~A78L02ACLP
~A78L26AWC
~A7824MKA
~A7824KM
~A78L05ACLP
~A78L05AWC
~A7885CKA
~A7885KC
~A78L06ACLP
~A78L62AWC
~A7885CKC
~A7885UC
~A78L08ACLP
~A78L08AWC
~A7885MKA
~A7885KM
~A78L 12ACLP
~A78L12AWC
~A79M05CKC
~A79M05AUC
~A78L 15ACLP
~A78L15AWC
~A79M05CLA
~A79M05AHC
~A78M05CKC
~A78M05UC
~A79M05MLA
~A79M05HM
~A78M05CLA
~A78M05CHC
~A79M06CKC
~A79M06AUC
~A78M05MLA
~A78M05HM
~A79M06CLA
~A79M06AHC
~A78M06CKC
~A78M06UC
~A79M06MLA
~A79M06HM
~A78M06CLA
~A78M06CHC
~A79M08CKC
~A79M08AUC
~A78M06MLA
~A78M06HM
~A79M08CLA
~A79M08AHC
Part
Number
Fairchild
Direct
Replacement
~A78M08CKC
~A78M08UC
~A79M08MLA
~A79M08HM
~A78M08CLA
~A78M08CHC
~A79M12CKC
~A79M12AUC
~A78M08MLA
~A78M08HM
~A79M12CLA
~A79M12AHC
~A78M12CKC
~A78M12UC
!lA79M12MLA
~A79M12HM
~A78M12CLA
~A78M12CHC
~A79M15CLA
~A79M15AHC
~A78M12MLA
~A78M12HM
~A79M15MLA
~A79M15HM
~A78M15CKC
~A78M15UC
~A79M20CKC
~A79M20AUC
~A78M15CLA
~A78M15CHC
~A79M20CLA
~A79M20AHC
~A78M15MLA
~A78M15HM
~A79M20MLA
~A79M20HM
~A78M20CKC
~A78M20CUC
~A79M24CKC
~A79M24AUC
~A78M20CLA
~A78M20CHC
~A79M24CLA
~A79M24AHC
~A78M20MLA
~A78M20HM
~A79M24MLA
~A79M24HM
~A78M24CKC
~A78M24CUC
~A7905CKA
~A7905KC
~A78M24CLA
~A78M24CHC
~A7905CKC
~A7905UC
~A78M24MLA
~A78M24HM
~A7905MKA
~A7905KM
!lA7805CKA
~A7805KC
~A7906CKA
~A7906KC
~A7805CKC
~A7805UC
~A7906CKC
~A7906UC
~A7805MKA
~A7805KM
~A7906MKA
~A7906KM
~A7806CKA
~A7806KC
~A7908CKA
~A7908KC
~A7806CKC
~A7806UC
~A7908CKC
~A7908UC
~A7806MKA
~A7806KM
~A7908MKA
~A7908KM
~A7808CKA
~A7808KC
~A7912CKA
~A7912KC
~A7808CKC
~A7808UC
~A7912CKC
~A7912UC
~A7808MKA
~A7808KM
~A7912MKA
~A7912KM
~A7812CKA
~A7812KC
~A7915CKA
~A7915KC
2-17
Fairchild
Functional
Equivalent
•
LINEAR INDUSTRY CROSS REFERENCE GUIDE
Part
Number
",A7915CKC
",A7915MKA
",A7918CKA
",A7918CKC
Fairchild
Direct
Replacement
Fairchild
Functional
Equivalent
Part
Number
",A7915UC
",A7915KM
",A7918KC
",A7918UC
",A7918MKA
",A7924CKA
",A7924CKC
",A7924MKA
2-18
Fairchild
Direct
Replacement
",A7918KM
",A7924KC
",A7924UC
",A7924KM
Fairchild
Functional
Equivalent
QUALITY, RELIABILITY AND HI REL PROCESSING
Quality, Reliability and Hi Rei Processing ................................................ 3-3
QUALITY, RELIABILITY AND HI REL PROCESSING
Introduction
There are three basic ingredients in the manufacture of reliable Linear Circuits. First, the device must be
designed with the user's applications and reliability requirements in mind. Secondly, the device must be
manufactured with the optimum technology for the application. Thirdly, controls must be established to
assure maintenance of the quality/reliability levels established in the design of the device. Consideration
is given to the reliability influence of each part of the manufacturing and testing cycle with constant feedback from internal reliability monitoring; customer feedback on the results is a vital factor. The Fairchild
reliability concept can be presented as constant feedback system which begins and ends with the customer (Figure 3-1).
Areas of Consideration
Device Applications and Reliability
The reliability cycle begins with the customer. His device application, environment for its usage and endproduct reliability requirements are major factors in establishing the quality/reliability levels. The customer is the final judge.
FAIRCHILD
PURCHASED MATERIAL
QUALITY CONTROL
FAIRCHILD
MANUFACTURE
ASSEMBLY
TEST
Customer Design Breadboard
Fig. 3-1 Customer Feedback System
3-3
II
Device Design
Inherent component reliability is a function of the product/process design. New Fairchild designs as well as
modifications or extensions of existing designs with known performance and reliability characteristics are
rigorously evaluated. Three different factors in the manufacture of an IC significantly affect its reliability.
The Silicon Chip- Fairchild's design-technology capability utilizes epitaxial layer to achieve the
desired electrical parameter characteristics. The surface influences long-term gain and voltage/leakage stability. The metallization determines mechanical integrity and current distribution.
Chip Assembly - The process and materials used to assemble the chip and package must preserve
the inherent reliability of the chip and be inherently reliable to withstand thermal, mechanical and
electrical stresses.
The Package - The package must effectively transfer heat from the chip to the outside world and
protect the chip during handling and use.
Incoming Quality Control (IQC)
All purchased materials for Fairchild Linear circuits are controlled through central specification control,
product engineering, and reliability and quality assurance (R&OA) located in Mountain View. Materials
are purchased and inspected per control documents using three IOC methods.
Direct visual and mechanical inspection
Functional testi ng
Composition analysis utilizing chemical and x-ray techniques from both internal and external sources.
In addition to centralized IOC, each manufacturing facility has a local, fully equipped IOC department.
These facilities concentrate on cleanliness, plating quality and functionality. A computer file is made on
each vendor's performance and quarterly reports are generated and analyzed.
Wafer Manufacture
Wafers used to fabricate Fairchild Linear Circuits are made at Fairchild. This includes crystal pulling,
slicing, polishing and epitaxial layer growth. Fairchild designs rely on accurate control of thickness and
resistivity. All operations have laminar-flow clean-air hoods directly over the work areas. Wafer
fabrication is essentially a series of masking and furnace cycles in which geometries are defined and
impurities (dopants) introduced to form emitter, base and resistor regions. Daily controls are maintained
on furnace temperatures to within ±1°C. Resistivities (ps) of diffused layers are recorded on every run.
Each masking step defines a new portion of the device geometry. A post develop inspection is performed
to assure that each wafer has been properly exposed and chemically developed before final etching.
When the masking and etching procedures are completed, a final inspection assures that the geometry is
properly aligned, etched and cleaned. Following each production masking step, a sample inspection is
performed by quality control inspectors to verify correct process implementation.
After masking and diffusion, the metallization process completes wafer manufacture. Fairchild uses
electron-beam evaporation techniques to deposit gold and aluminum. DepOSits are controlled through
utilization of automated process sequencing,which includes an automatic thickness controller. Every
run is gated through a first optical ("I st opU inspection before it leaves the wafer fabrication area.
Cleanliness, mask alignment, metal adherence (front and back) and general workmanship are inspected.
3-4
Wafer Probing
IOC Area
Crystal Puller
3-5
I
Wafer Testing
Before the wafers are scribed and broken into dice for assembly onto headers or shipment toa customer
as probed dice, they are electrically sorted. Each wafer is automatically probed with multiple tests to
duplicate or correlate the dice to the final product test requirements. Rejected dice are ink marked and
later scrapped. A final quality control gate is performed before the probed wafers can be forwarded to
assembly.
Device Assembly
After the wafers are scribed and broken, a second optical (2nd opU QC inspection is performed. The dice
are inspected for wafer fabrication (handling) damage, as well as for defects which may cause assembly
problems or result in latent reliability problems.
Monitors are performed on both assembly equipment and operators. Machines are shut down if defect
control limits are exceeded and suspect material is rejected and 100% screened. Key items inspected are
die orientation, voids under die, proper bond formation, wirepull strength and cleanliness.
A third optical (3rd opU gate is performed prior to final device sealing. If rejected, the lot is 100% screened
by production and resubmitted to QC. Accepted lots are sent to the final seal operation, where the
packages are monitored for weld strength and hermeticity (except plastic packages).
Device Testing
Before shipment, all devices are 100% production tested to the following minimum inspection levels.
0.25% AQL
0.65% AQL
1.5% AQL
1.5% AQL
0.65% AQL
15/0 LTPD
1.0% AQL }
0.4% AQL
Hermetic Devices Only.
Functional dc
25°C dc
25°C ac
Temperature dc
MechanicallVisual
Marking Performance
Fine Leak
Gross Leak
Customers with special testing requirements are accommodated through an internal specification
system. All internal test speCifications formatted frbm customer documents are signed off by QA before
they can be issued to the test area.
Device Application
The total reliability effort is completed full-cycle with the customer. Operation in the customer application is the final consideration in device reliability. How each device is handled during system assembly by
the customer, heat-sunk (mounted) and cooled during operation, and the amount of overload stresses
(due to the system malfunction or misuse) greatly impacts the device reliability. Thus, the customer's
specification requirements, the manufacturer's device design, manufacture, test, the actual circuit into
which the device is inserted and the equipment containing that circuit in the field all affect the device and
reliability.
Failure Analysis
Failure analYSis results performed by customers and by Fairchild on returned devices provide one of the
most important inputs for consideration in Fairchild's total linear reliability concept. Failures generated
by line monitors, life tests and field applications are analyzed to provide corrective action in terms of
product design, assembly and testing methods. A scanning electron microscope (SEM) and an Auger
electron microscope for chemical analysis are available for inspection of materials.
3-6
DlG Probing
3-7
Reliability Monitor and Control
Line Monitors
Line monitors are used to monitor the production line on a weekly basis. These monitors are designed to
provide a constant feedback on product reliability. The following assembly/test monitors are conducted
on a routine basis.
Assembly
Test
Package integrity
High-temperature reverse bias
Lead integrity
Intermittent operating life (power cycling)
Die integrity
High-temperature storage
Die-attach integ·rity,
Temperature cycling
Bond integrity
Thermal shock
Autoclave-Applied to plastic devices only.
85% R.H.l85° C biasedExtended Reliability Tests
In conjunction with the weekly line-monitor program, Fairchild employs an extended reliability test program which is designed to reflect the long-term stability of Fairchild's Linear products. A summary of
these reliability tests is shown in Table 3-1.
Quality and Reliability Data
Supplemental brochures are published on an annual basis which provide detailed failure rate data.
Please contact Fairchild Sales Offices for additional reliability and quality information.
EXTENDED RELIABILITY TESTS
·"",,·re.ra.~reo~tlng"um
':TA:::.l5G"~'
" ,""', " "',,' :
F\eaO<,>lita< 't.g:.168.500,fOPO Hours
l'ctn)~.~:~~:,~~~C~+1SO<>C '
lmPact$h6ctc,
,~
x
x
x
"
1~QO"fix5aJ9W&, '" ,::,
, tMJL,~STD~Mett:Jod26(2)::
x
':'~.. ·~F"n!'J",."
x
'(·Mf1.,,$T~. ~thOd 20071'
'• • Huw.d., "", .,
.:TA';:8~t;,~8''';85% '".
PLASTIC
x
,tMtt;;~~ ..~;M&tfl0j;11Ql0~ l "
MiL~$ro-aoo:M.ethodjo11.G~tiQIlC c'
x
":",:
,
;Aut<»CIaq.,;,
11."; 125<>:C. ft;~o;C
x
"t5PSI,2.(l-burs
Table 3-1
Reliability Test Summary
3-8
',>
HI REL PROCESSING - MIL-M-38510/MIL STD-883
A unique "company", within Fairchild Linear, is totally dedicated to the processing of high reliability
products and to serving the special needs of the HI REL community. It consists of marketing, engineering, production control, manufacturing and quality assurance. Fairchild's HI REL processing facilities
are among the most modern and sophisticated in the semiconductor industry. Screening procedures are
set up to conform to the most recent version of MIL-STD-883, in conjunction with MIL-M-38510, which
establishes standardized requirements for design, material, performance, control and documentation
needed to achieve prescribed levels of device quality and reliability.
HI REL Unique II Program
Fairchild's Unique II program fills a longstanding need for a definite and comprehensive program
covering HI REL semiconductor products ... a program offering users a selection among multi-level
screening flows and reliability requirements ... a program providing clear and precise definitions on all
areas of contractual performance ... a program designed to reduce the high costs and delivery delays
normally associated with HI REL. The objectives and benefits of the Unique II program for integrated
circuits are these:
•
•
•
•
•
•
Offers a full spectrum of processing options, including full compliance JAN and 883 Classes S, B,
and C.
Offers full compliance with JAN MIL-M-38510 and emphasizes the importance of this program.
Accommodates the special needs of users' source control and specification control drawings.
Offers models to aid users in development of source control drawings.
Takes the mystery out of in-house processing to MIL-STD-883 and to MI L-M-3851 0 detail specifications. The Unique II program is definitive as to the similarities and differences in these requirements.
Provides users with alternatives that may be used when JAN slash sheets or QPLs are unavailable, or
for programs that demand the highest level of quality and reliability.
Fairchild offers a complete processing capability to fulfill requirements ranging from the least demanding to the most complex, including the following:
•
•
•
•
•
•
Scanning Electron Microscope (SEM) Inspection
Level A Visual
Bond Pull and Die Shear Testing
Read and Record and ~ Drift Parameters
Particle Impact Noise Detection (Pin-OJ Testing
Group A, B, C and D Qualification Testing.
Standard Unique II processing flows are given on the following pages; special flows will be quoted on an
individual basis.
MATRIX VI- COMMERCIAL AND INDUSTRIAL RELIABILITY PROGRAM
Commercial and industrial users increasingly demand optimized quality and reliability for the semiconductor integrated circuits purchased for their systems. Specific factors - increased integrated circuit
usage per board, high costs for receiving inspection, pc board and systems repair, and the frequently
immeasurable cost associated with field failures- require the user to attain high quality and reliability
coupled with total cost. Matrix VI is designed to meet these user requirements.
Fairchild's Matrix VI Program offers a broad spectrum of screens and high technology/high volume
integrated circuit products to meet the user's quality and reliability requirements typically associated
with the commercial and industrial marketplace. There are two screening options for each package type,
each with a separate degree of reliability and cost level. To simplify a cost-effective analysis, reliability
factors have been assigned to each screening level. (See following pagesJ
It is the goal of Matrix VI to aChieve the highest possible reliability consistent with the user's needs and to
avoid "over-buying". Cost-effective reliability is the essence of Matrix VI, the most comprehensive
program of its kind now offered to the industrial/commercial marketplace.
3-9
I
JAN PART NUMBERING SYSTEM
J M 38510/ 101 01 B G C
-r-
-r0o-
~
- ..
T
JAN DESIGNATOR
Cannot be marked with "J"
unless qualified on Part I
or Part II of QLP-38510
~
LEAD FINISH
A
B
C
X
Defines
Device
Type
Hot Solder DIP
Tin Plate
Gold Plate
Any of the above
I
General Procurement Spec.
PACKAGE TYPE
A
B
C
D
E
F
G
H
I
J
K
L
X
Y
Z
I
REFERS TO DETAIL SPEC
101
102
103
104
105
106
107
108
109
110
Op Amps
Voltage Regulators
Comparators
Interface
733
Voltage Followers
3-Terminal Voltage Regulators
Transistor Arrays
Timers
Quad Op Amps
14-pin '/4 x '/4 Flatpak
14-pin '/4 x '/8 Flatpak
14-pin '/4 x 'I. DIP
14-pin '/4 x % Flatpak
16-pin '/4 x 'I. DIP
16-pin '/4 x % Flatpak
8-pin Can
10-pin '/4 x '/4 Flatpak
10-pin Can
24-pin '/2 x 1'/4 DIP
24-pin % x '/, Flatpak
24-pin % x '/2 Flatpak
3-pin TO-5 Can
2-pin TO-3 tan
24-pin '/4 x 3/, Flatpak
PROCESSING LEVEL
S
B
C
LINEAR JAN GENERIC
PART NUMBERS - EXAMPLES
JM38510/
01
02
03
04
05
06
07
101
741
747
lOlA
108A
2101
2108
118
102
723
08
09
103
710
711
106
111
2111
104
55107
55108
9614
9615
55113
7831
7832
7820
7830
105
733
106
102
110
2110
107
109
78M05
78M12
78M15
78M24
7805
7812
7815
7824
108
3018
3045
109
555
556
110
148
149
4741
4136
124
Note: Dated material. Please contact Fairchild for latest revisions.
3-10
10
HI REL PROCESS SCREENING REQUIREMENTS
JAN M38510
MI L-STD-883B
TEST METHODS
DESCRIPTION
Preseal Visual
MTD.2010
Cond, A Maximum Visual Criteria
Condo B. Optimum Visual Criteria
Bond Strength
MTD 2011
Bond strength is monitored on a sample
basis three times per shift per machine
Seal
Devices are hermetically sealed for
compliance to MIL-STO-883 requirements
H igh Temp Storage
MTD 1008
Temperature Cycle
MTD 1010
Condo C Tstg
~
I
150°C
TEMP CYCLE
CONDo C
Condo C -65°/150°C 10 cycles
Constant Acceler
atian
CENTRIFUGE
CONDo E
Y1 ONLY
MTD 2001 I Note1l
Hermetic Seal
MTD 1014 INote 1l
Cand A Fine-Helium 5x10· 8 CCjsec
Cond B Fm€-Radlflo 5x10- 8 CCisec
Cond C Gross-FC43/Hot 10-3 cc/sec or
Gross-FC78/Vacuum 10-5 cc/sec
Pre Burn-In
Electrical
MTD 5004
25°C de electrical testing
to remove rejects prior to
submiSSion to burn·ln screen
Burn-In Screen
MTD 1015
Cond A. Cond 8. Cond C
Cond D. Cond E. Cond F
Post Burn-In
Post Burn-In electrical screening to cull
out devices which failed as a result of
burn-in. Test Parameters may Include
25°C de. 125°C dc. -55°C dc. 25°C dc.
25°C ac and 25°C Functional tests
Electrical
MTD 5004
TEMP CYCLE
CONDo C
Quality Conformance
Inspection
MTD 5005
Group A Electrtcal Characteristics
Group B Package onented Tests
Group C: Life Tests
Group D: Environmental Tests
External Visual
MTD 2009
3X, lOX magnification: Verify dimenSions,
configuration, lead structure, marking
and workmanship
RE LIA81 LlTY
ORDERING
Figure of Merit
Part Number
Part Marking
HERMETICITY
CONDo A/8
CONDo C
PST 8/1 ELECT
25°C de
+ 125°C dc
~55°C de
25°C ac
10% PDA
ELECTRICAL
25°C de
25°C FUNCTIONAL
QUALITY
CONFORMANCE
Gp A, B, C
and D
QUALITY
CONFORMANCE
Gp A, B, C
and D
EXTERNAL
VISUAL
100%
EXTERNAL
VISUAL
100%
15
2
JM3851 01
101018C8
JM38510/
10101CC8
JM38510/
101018C8
JM38510/
10101CC8
NOTE: RELIABILITY Figure of Merit is the Reliability Improvement Factor from RADC Reliability Notebook,
Vol. II, RADC-TR-67-108, Table XII-G, page419.
1. Not Applicable for TO-3 Cans
·Time Temperature Curve (method 1015) may be used.
3-11
UNIQUE II
~--
-- - .. - - - T
CLASS
QS
(883S)
-- ----------1
CLASS
CLASS
08
OC
1883B)
1883C)
':"
~
I\)
TEMP CYCLE
1010
TEMP CYCLE
COND. C
CDND. C
1010
HERMETICITY
COND. AlB
COND.C
HERMETICITY
COND. AlB
CDND. C
HERMETICITY
COND. AlB
COND.C
1014
1014
POST BII ELECT
25°C DC
125"C DC
- 55"C DC
25"C AC
25"C FUNCTIONAL
5004
POST BII ELECT
25"C DC
125"C DC
-55"C DC
25"C AC
25"C FUNCTIONAL
5004
5004
QUALITY
CONFORMANCE
5005 GP A, B, C & D
QUALITY
CONFORMANCE
5005 GPA,B,C & D
ELECTRICAL
25°C DC
25"C FUNCTIONAL
I
I
c.v
~
c.v
EXTERNAL VISUAL
2009
100%
IlA741 DMQS
EXTERNAL VISUAL
100%
2009
IlA741 DMQB
I
I
I
EXTERNAL VISUAL
100%
2009
IlA741 DMQC
•
MATRIX VI PROCESS FLOW OPTIONS & COST EFFECTIVENESS
r
I"
PLASTIC MOLDED DEVICES
{PC, TC, UCI
KEY
100% OPERATION
J
~"'='~~"g
>ClASAMPLEil
HERMETIC PACKAGED DEVICES
{DC, HC, KC, RCI
FINISHED GOODS STORES
LEVEL 1,
(PC)
LEVEL 2,
(PCOM)
LEVEL 3,
(DC)
LEVEL 4.
(DCOM)
LEVEL 5,
(PCOR)
LEVEL 6,
(DCOR)
THERMAL SHOCK
LlQUID-lO-L1QUID
THERMAL SHOCK
LIQUID· TO·LlQUID
TO + 100°C
aoc TO
aoc
+l00°C
883/1011/A
883/1011/A
DC & FUNCTIDNAL
+25°C
1 % PDA LOT REJECTION
CRITERIA APPLIED TO
LOTS EXHIBITING MORE
THAN 1 % INTERMITIENTS
THROUGH HOT RAIL TEST
..... , . ' , ' , ....... -.... -.. -..... -..,'-.-.
QA ACCEPTANCE
.:. FINE LEAK, 883/1014/8,
··1% AOL; GROSS LEAK,
. 883/1014/C, 0.4% AOL;
: FUNCTIONAL +25" C,
0.15% AOL; DC, O"C,
: 1% AOL; DC, +25"C,
0.25% AOL; DC, +70"C, 1%:
,.. AOL;AC, +2S"C,1%AOL
Colo. ACCEPTANCE
:FUNCTIONAL, +25"C, 0.15% AOL
'DC, O"C, 1% AOL
:·DC, +25" C, 0.25% AOL
,'DC, +70"C, 1% AOL
>.AC.,.+25"e;,.1.%.AOL
Ul
~
(J1
QAACCEI'TANCE
. FINE LEAK 883/1014/8,
., 1% AOL; GROSS LEAK,
B83/1014/C, 0.4% AOL;
.. FUNCTIONAL +25" C,
>0.15% AOL; DC, 0" C,
.; 1% AOL; DC, +25" C,
,.; 0.25% AOL; DC, +70" C, 1%
'·'.AOL; AC.,. +25"C,.1.% ..A9L. ;..
.i
. i
COST EFFECTIVENESS ANALYSIS
RELIABILITY FACTOR
olX
QUALITY GUARANTEE
ON FUNCTIONALITY
o 0.2B%AQL
COST SEQUENCE 1
RELIABILITY FACTOR
=1.4X
QUALITY GUARANTEE
ON FUNCTIONALITY
oO.15%AQL
COST SEQUENCE 2
RELIABILITY FACTOR
=2X
QUALITY GUARANTEE
ON FUNCTIONALITY
00.2% AQL
COST SEQUENCE 3
RELIABILITY FACTOR
" 2.3X
QUALITY GUARANTEE
ON FUNCTIONALITY
RELlA81L1TY FACTOR
COST SEQUENCE 4
COST SEQUENCE 5
=0.15% AQl
=- 7.5X - 9X
(2)
QUALITY GUARANTEE
ON FUNCTIONALITY
=O.15%AOL
RELIABILITY FACTOR
=14X
QUALITY GUARANTEE
ON FUNCTIONALITY
= O.15%-AQl
COST SEQUENCE 6
NOTE:
(1) Temperature Accelerated Testing may be used for MIL·STD·883 method 1015 Test Condition F.
(2)
Burn~ln has the same relative effectiveness for plastic molded devices as for ceramic/hermetic packaged devices. Assuming a controlled (air conditioned and constant power) field application/environment, the reliability factor would be approximately 9x. But should the field application be in a less controlled and power on/off application, the reliability would be approximately 7.5X.
•
VOLTAGE COMPARATORS
MAF111/MAF311
FET-Input Voltage Comparator ................................. 4-3
MA 111/MA311
Voltage Comparator .......................................... .4-8
MA 139/MA239/MA339
Low-Power, Low-Offset Quad Voltage Comparator ............ 4-13
MA 139A/MA239AIMA339A ,Low-Power, Low-Offset Quad Voltage Comparator ............ 4-13
MA2901
Low-Power, Low-Offset Quad Voltage Comparator ............ 4-13
MA3302
'Low-Power, Low-Offset Quad Voltage Comparator ............ 4-13
MA71 O/MA71 OC
High-Speed Differential Comparator .......................... 4-21
MA711/MA711 C
Dual High-Speed Differential Comparator ..................... 4-25
MA 734
Precision Voltage Comparator ., ............................. 4-29
MA760
High-Speed Di.fferential Comparator .......................... 4-36
IJAFlll • IJAF311
FET INPUT VOLTAGE COMPARATORS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The IlAF111 and IlAF311 are monolithic, FET input Voltage Compare-
tors, constructed using the Fairchild Planar* epitaxial process. The ,uAF111 series operates from the
single 5 V integraetd circuit logic supply to the standard ±15 V operational amplifier supplies. The
.uAF111 series is intended for a wide range of applications including driving lamps or relays and
switching voltages up to 50 Vat currents as high as 50 rnA. The output stage is compatible with RTL,
DTL. TTL and MOS logic. The input stage current can be raised to increase input slew rate.
•
-.
•
•
•
•
CONNECTION DIAGRAMS
8·PIN METAL CAN
(TOP VIEW)
PACKAGE OUTLINE 5S
PACKAGE CODE H
EXTREMELY LOW INPUT BIAS CURRENT ... 50 pA MAX (IlAF111l, 150 pA MAX (IlAF311)
EXTREMELY LOW INPUT OFFSET CURRENT ... 25 pA MAX (IlAF111l, 75 pA MAX (IlAF311)
DIFFERENTIAL INPUT VOLTAGE ... ±30 V
POWER SUPPLY VOLTAGE SINGLE 5.0 V SUPPLY TO ±15 V
OFFSET VOLTAGE NULL CAPABILITY
STROBE CAPABILITY
ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals
36 V
50 V
Output to V- (IlAF111)
(IlAF311)
40V
Ground to VDifferential Input Voltage
Input Voltage (Note 1)
Internal Power Dissipation (Note 2)
Output Short Circuit Duration
Storage Temperature Range (Metal Can)
30 V
±30 V
±15 V
500mW
105
_65" C to +150" C
-55"C to +125°C
Metal Can
Hermetic DIP
v-
ORDER INFORMATION
TYPE
PART NO.
IlAF111
IlAF111HM
IlAF311
IlAF311 HC
NOTE: Pin 4 connected to case.
Operating Temperature Range
_55° C to +125° C
O°Cto+70°C
Military (IlAF111)
Commerc'ial (,uAF311)
Pin Temperature
Metal Can, Hermetic DIP (Soldering, 60 5)
CONNECTION DIAGRAM
14-PIN DIP
(TOP VIEW)
PACKAGE OUTLINE 6A
PACKAGE CODE D
EOUIVALENT CIRCUIT
14
NC
GROUND
NC
+INPUT
NC
-INPUT
v.
NC
NC
v-
OUT
BALANCE
BALANCE!
STROBE
ORDER INFORMATION
TYPE
PART NO.
IlAF111DM
IlAF111
IlAF311 DC
IlAF311
4-3
I
FAIRCHILD • JLAF111 • JLAF311
j.lAFlll
ELECTRICAL CHARACTERISTICS: Vs
~
±15 V, TA
CHARACTERISTICS
~
-55'C to +125'C unless otherwise specified, Note 3.
MIN
MAX
UNITS
Input Offset Voltage (Note 4)
T A = 25°C, RS ",; 50 kf!
CONDITIONS
0.7
4.0
mV
Input Offset Current (Note 4)
T A = 25°C, VCM = 0 (Note 6)
5.0
25
pA
Input Bias Current
T A - 25°C, VCM - 0 (Note 6)
20
50
Voltage Gain
TA-25°C
200
V/mV
Response Time (Note 5)
TA = 25°C
200
ns
Y,N ",; -5 mY, lOUT - 50 mA
Saturation Voltage
0.75
TA = 25°C
TA - 25°C
Strobe On Current
1.5
3.0
V,N;' 5 mY, VOUT - 35 V
Output Leakage Current
TYP
TA = 25°C
pA
V
mA
0.2
10
nA
Input Offset Voltage (Note 4)
RS"'; 50 kf!
6.0
mV
Input Offset Current (Note 4)
Vs - ±15 V, VCM - 0 (Note 6)
2.0
3.0
nA
Input Bias Current
Vs - ±15 V, VCM - 0 (Note 6)
5.0
7.0
nA
+14
Input Voltage Range
V
-13.5
V+;, 4.5 V, V
Saturation Voltage
=0
Y,N ",; -6 mY, 'S'NK"'; 8 mA
V
0.23
0.4
V
Output Leakage Current
Y,N ;, 5 mY, VOUT - 35 V
0.1
0.5
}J.A
Positive Supply Current
TA = 25°C
5.1
6.0
mA
Negative Supply Current
TA - 25'C
4.1
5.0
mA
MAX
UNITS
j.lAF311
ELECTRICAL CHARACTERISTICS: Vs
CHARACTER ISTICS
~
±15 V, TA
~
O'C to +70'C unless otherwise specified, Note 3.
CONDITIONS
MIN
TYP
Input Offset Voltage (Note 4)
T A = 25'C, RS"'; 50 kf!
2.0
10
mV
Input Offset Current (Note 4)
TA = 25'C, VCM = 0 (Note 6)
5.0
75
pA
Input Bias Current
TA = 25°C, VCM = 0 (Note 6)
25
150
Voltage Gain
TA - 25°C
200
V/mV
Response Time (Note 5)
TA - 25'C
200
ns
Saturation Voltage
Strobe On Current
Output Leakage Current
V,N"'; -10 mY, lOUT - 50 mA
TA = 25°C
TA = 25'C
0.75
1.5
3.0
V,N;' 10 mY, VOUT - 35 V
TA = 25°C
0.2
pA
V
mA
10
nA
15
mV
Input Offset Voltage (Note 4)
RS"'; 50 kn
Input Offset Current (Note 4)
Vs = ±15V, VCM = 0 (Note 6)
1.0
nA
Input Bias Current
Vs - ±15 V, VCM - 0 (Note 6)
3.0
+14
nA
-13.5
V
Input Voltage Range
V+;, 4.5 V, V
Saturation Voltage
=0
Y,N ",; -10 mY, ISINK ",; 8 mA
0.23
V
0.4
V
Positive Supply Current
TA=25°C
5.1
7.5
mA
Negative Supply Current
TA = 25'C
4.1
5.0
mA
NOTES:
1. This rating applies for ± 15 V supplies. The positive input voltage limit is 30 V above the negative supply. The negative input voltage limit is
equal to the negative supply voltage or 30 V below the positive supply, whichever is less.
2. Rating applies to ambient temperatures up to 70 o e. Above 700 e ambient derate linearly at 6.3 mwle for metal can; 8.3 mwle for mini
DIP.
3. The offset voltage, offset current and bias current specifications apply for any supply voltage from a single 5 V supply up to ± 15 V supplies.
4. The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with a 1 mA
load. Thus, these parameters define an error band and take into account the worst case effects of voltage gain and input impedance.
5. The response time specified (see definitions) is for a 100 mV input step with 5 mV overdrive.
6. For input voltages greater than 15 V above the negative supply the bias and offset currents will increase ~ see typical performance curves.
4-4
FAIRCHILD • /.LAF111 • /.LAF311
TYPICAL PERFORMANCE CURVES
INPUT BIAS CURRENT
AS A FUNCTION OF
COMMON MODE VOLTAGE
INPUT BIAS CURRENT
AS A FUNCTION OF
TEMPERATURE
10.000~mm
10,000
TA ~+26°C
..
/
1,000
1,000
ru
i
1/
_NciRMALtOUTP0T
RL
~
1k
50 -V++=50V
I
100
TRANSFER FUNCTION
60
100
"
~
V
..L
~
20
/
10
~-'"
r-~~~:6E:ER
t-?UTPUT
R L =600
0
4.0
8.0
12.0
16.0
20.0
24.0
"~~55"-_"':-5-!:15'--5::':.0'--2~5-'4!;;5---:'''"5--;!85'-1;!;05~125
2ao
w
~
g
I
RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES
I I
5.0
2.0
1.0
'.0
2.0
1.0
Vlpl500 _
~
0
2 +
0.4
I
I I
t::'"
I I -;,vi·"iv
TA=25°~- t -
I I
0.2
0.8
r"'i II
/
5.0rnv.I
0
fl L.4-
5-6.0
.v'
V
r~
2.0mV
-
o
~ -~ 0
1
VOUT
IIAF111
V-
0
~
2.0
1.0
0
-1 0
I
w
-1
~\
,\
2Omv.,.
5.0mV
2.DmV
\
100
_L
I
20
o
5.0
'0
0.'
0
TA
-:".c
0
POSITIVE SUPPLY-
0.5
~
OUTPUT LOW
4. 0
.4
/
V
2. 0
v
........ V
V
/
OJ
I
I
4
J
I l
'.0
4.0
t--..
POSITIVE SUPPlY-
~PUTW.l- l -t -
......,..... I'---l.
l- t- t-!POSI~~
10
OUTPUT VOLTAGE-V
0
o
o
15
r-
IOUTrUT H(GH1
o
-55 -35
-15
25
45
65
85
105 125
OUTPUT LEAKAGE CURRENT
AS A FUNCTION OF
TEMPERATURE
''''7~~
----
~
'''''_M!./~
/ ' OUTPUT VOUT"' SOV
POSITIVE AND
NEGATiVe SUPPLYaUTPUTHIGH
1....
r CIRfUIT CUrRENT
.,
r-
NEGATIVE SUPPL y-
21- t"- t-
TEMPERATURE -"C
SUPPLY CURRENT
AS A FUNCTION OF
SUPPLY VOLTAGE
0
Slid.
/
'r----
~!:~~~~- r-
1.0
f--
.......
/
40
VOUT
v-
J
0
..
\. 1,/
/'
60
o
~
..&.'~"
..r
~~
\
so
~
1
TlMES-l's
T)"·C- 12
I
SUPPLY CURRENT
AS A FUNCTION OF
TEMPERATURE
8
2K
r-\
\il.
•
HlO
~
OUTPUT LIMITING
CHARACTERISTICS
120
....
0.' t--h"1-:;~'-t--t---t-f--+-+-I
...
Vs= ±15V
-
"AFll1
TIMES-ItS
140
f
~
<0
10
2
Y,N
g ..
vS'''~~+
Tt''';C
i-,oo
5. 0
~
~
I I I
g .....
"\ :-\
10
0_5. 0
2K
,
Q-" !L:
//
V·
5
~
VIN~
r- r- T A = -55°C."k."r-s.oI
~VF··-+-t-+--I
10
I
~
~
o
>
•••• ~
o.8
•0
0.4
>
I I
OUTPUT SATURATION VOLTAGE
0.'""-,,,-,.,--,-,
0.5
IIAf111
RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES
0
~
2.0mV
RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES
~~
~
0.0
I
I -1
5'i mv r.
TIMES-:-lIs
'0 l20m
0.5
0.' t-+--t---t-t--t---t-.."'~5-I"""'''-H
VOUT
TIME-ItS
1
-1.0
0.7
7
100
0.2
~
J
2OmV':;j
2 +
.
IIAF111
0
I
VIN
.1
-;?-"
VOUT
50
>
pl600
\
4.0
S.OV
;;;?--
\
5.0V
'.0
10 rl" VJ=:tl~V I Tr";Cfmv ~ II
5.0mV J
I
II
I I
2!omv l/J II
4.0
3.0
I"
DIFFERENTIAL INPUT VOLTAGE - mV
RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES
I
I
J
o
TEMPERATURE "C
INPUT COMMON MODE VOLTAGE - V
>
T A s 25"C_
II
II
30
~
0
~s·,civ__
I
I
40
~_
10-10~~
o
5.0
10
15
20
SUPPLY VOLTAGE - V
4-5
25
'0
10- 11
!::"-'--:~--:05~--:8~5---:'0!::'-~125
TEMPERATURE _ ·C
•
FAIRCHILD • p.AF111 • p.AF311
TYPICAL APPLICATIONS
10 Hz TO 10 kHz VOLTAGE CONTROLLED OSCILLATOR
RELAY DRIVER WITH STROBE
Cl
1000 pF t
VH
Rl
10k
TRIANGULAR
5,0 mV ............ 5.0V
5.0 mV
R2
WAVE
t~N;,~0 o-~__-t__-'l",22",k..-_.,.....,
01
2N3972
OUTPUT
Q2
2N5019
aI'
R3
33Qk
V-15V
SQUARE
L--~~-------~~-4~---~~~~)WAVE
OUTPUT
R9
10k
RlO
1.0k
• Adjusts for symmetrical square
wave time when VIN = 5.0 mV.
R1
lk
-=-
TTL STROBE
Rll
1.0k
tMinimum capacitance 20 pF.
Maximum frequency 50 kHz.
-15V
"'Absorbs inductive kickback of
relay and protects Ie from severe
voltage transients on v++ line.
STROBING OFF BOTH INPUT"
AND OUTPUT STAGES
FREQUENCY DOUBLER
v+ '=
5.0V
Rl
10k
OUTPUT
*Typical input current is
Frequency rango!
50 pA with inputs strobed
off.
Input - 5.0 kHz to 50 kHz
Output - 10 kHz to 100 kHz
ZERO CROSSING DETECTOR
DRIVING MOS SWITCH
ZERO CROSSING DETECTOR
DRIVING MOS LOGIC
DRIVING
GROUND·REFERRED LOAD
r--~-oV'
r--~---~OV'
INPUT
L1
V+ '" 5 V
TO
I)''---''-.--O MOS
LOGIC
R3
10k
V-"'-lOV-=-
4-6
·'nput polarity is reversed when
using pin 1 as output
FAIRCHILD • p,AF111 • p,AF311
TYPICAL APPLICATIONS (Cont'd)
POSITIVE PEAK DETECTOR
COMPARATOR AND SOLENOID DRIVER
01
lN4001
o-~-f('I- 5 mV, VOUT = 35 V
0.2
T A = 25"C
Input Offset Voltage (Note 4)
RS';; 50 kit
Input Offset Current (Note 4)
Input Bias Current
V
mA
10
nA
4.0
mV
20
nA
150
nA
±14
Input Voltage Range
Saturation Voltage
1.5
V
V+ ;> 4.5 V, V- = 0
VIN .;; -6 mV, ISINK';; 8 mA
0.23
0.4
V
Output Leakage Current
VIN ;> 5 mV, VOUT = 35 V
0.1
0.5
!J.A
Positive Supply Current
T A = 25°C
5.1
6.0
mA
Negative Supply Current
TA - 25"C
4.1
5.0
mA
TYP
MAX
ELECTRICAL CHARACTERISTICS: Vs
CHARACTERISTICS
= ±15 V, TA = O·C to
+70·C unless otherwise specified, Note 3.
CONDITIONS
MIN
UNITS
Input Offset Voltage (Note 4)
T A = 25"C, RS';; 50 kit
2.0
7.5
mV
I nput Offset Current (Note 41
TA=25"C
6.0
50
nA
Input Bias Current
T A = 25"C
100
250
nA
Voltage Gain
TA = 25"C
200
V/mV
Response Time (Note 5)
T A = 25"C
200
ns
Saturation Voltage
Strobe On Current
Output Leakage Current
VIN .;; -10 mV, lOUT - 50 mA
TA = 25"C
0.75
TA = 25"C
3.0
V
mA
VIN ;> 10 mV, VOUT = 35 V
TA = 25"C
Input Offset Voltage (Note 4)
1.5
0.2
RS';; 50 kit
Input Offset Current (Note 4)
Input Bias Current
Input Voltage Range
50
nA
10
mV
70
nA
300
nA
±14
V
Saturation Voltage
V+;> 4.5 V, V- =0
0.23
0.4
II
Positive Supply Current
TA = 25"C
5.1
7.5
mA
Negative Supply Current
TA = 25°C
4.1
5.0
mA
VIN .;; -10 mV, ISINK .;; 8 mA
NOTES:
1.
2.
3.
4.
5.
This rating applies for ±15 V supplies. The positive input voltage limit is 30 V above the negative supply. The negative input voltage limit is
equal to the negative supply voltage or 30 V below the positive supply, whichever is less.
Rating applies to ambient temperatures up to 70°C. Above 70°C ambient derate linearly at 6.3 mW/oC for metal can; 8.3 mW/C for
mini DIP.
The offset voltage, offset current and bias current specifications apply for any supply voltage from a single 5 V supply up to ± 15 V supplies.
The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with a
1 mA load. Thus, these parameters define an error band and take into aCCOl..,lnt the worst case effects of voltage gain and input impedance.
The response time specified (see definitions) is for a 100 mV input step with 5 mV overdrive.
4-9
•
FAIRCHILD· JLAn1 • JLA311
TYPICAL PERFORMANCE CURVES FOR /lAlll
INPUT BIAS CURRENT
AS A FUNCTION OF
TEMPERATURE
INPUT OFFSET CURRENT
AS A FUNCTION OF
TEMPERATURE
OFFSET VOLTAGE
AS A FUNCTION OF
INPUT RESISTANCE
~TA-25'C
MAXIMUM
~
a
.
0
201--*-t----If--+--t-----I-+-+---I
TYPICAL
...-
,
a
~
o
TEMPERATURE - 'C
I
Iiii'll 1'1'1 'ioisl
,
""
'0
.Pins 5,6 and 8 are shorted.
INPUT BIAS CURRENT
AS A FUNCTION OF
01 FFERENTIAL INPUT VOLTAGE
rt+-r+++-r+++-rf'sl~!"G
TA" 25"C
COMMON MODE LIMITS
AS A FUNCTION OF
TEMPERATURE
" _~~FERJED Tb
,
OUTPUT VOLTAGE
AS A FUNCTION OF
DIFFERENTIAL INPUT VOLTAGE
_NORMAL OUTPUT~f--+---I-+---1
50 _~~+~zl;Oe
SUPPLY VOLTAGES
--
.0
"...
(
,-
'-
I
I
I ,,'"
-
d.•
0.'
,-
f-~~~~1~ER-"-'V
Vs -
LEAKAGE CURRENTS
AS A FUNCTION OF
TEMPERATURE
~15
V
,
~
"
~TIVESUPPLY-_
0JPurtw.l.
-
t--
'+-. 1--.l -.
-lpOSI~I~ b;
t, -- - I
1-- t-4
-
-
NEGATIVE SUPPL Y_
OUTrUT H1IGH
-
o
-OS
5
25
45
65
TEMPERATURE -"C
4-10
85105125
TEMPERATURE -
'c
FAIRCHILD eILA111 eILA311
TYPICAL PERFORMANCE CURVES FOR pA311
INPUT BIAS CURRENT
AS A FUNCTION
OF TEMPERATURE
OFFSET VOLTAGE
AS A FUNCTION
OF INPUT RESISTANCE
INPUT OFFSET CURRENT
AS A FUNCTION
OF TEMPERATURE
5oor--.--.---r--_'-L-'--'5'_lr."-5'~
'00---
I
RAIS;;;;--- _ _
""'f-----t--+--f-----+--+---j~-l
3 10 f-------+--+--+----+--+--I---1
-
~
200
NORMAL
'00
1
30
0
0
"
20
" -"c
50
60
~z"_ "'I
R VI"IIII'1"I"II
~
1
TYPICAL
I
30
TEMPERATURE
TEMPERATURE -
'c
*Pins 5, 6 and 8 are shorted.
INPUT BIAS CURRENT
AS A FUNCTION OF
DIFFERENTIAL INPUT VOLTAGE
225
v+.
200
OUTPUT VOLTAGE
AS A FUNCTION OF
01 FFERENTIAL INPUT VOLTAGE
COMMON MODE LIMITS
AS A FUNCTION
OF TEMPERATURE
r- ,REF~RRED ITO~~+--t-----+--I
SUPPLY VOLTAGES
-O.SI---t-+-+--t--t----jI----1
H5
60 Vs i 30 v _+---j_+---j_+---+
50 TA- 25 C,__+---+_JOAM2L OUrlpUT
0
'50
'"
'00
0' f-------+-+-+--t-+-f-----l
"
50
"I-+1-I1-+--III\.---'<-+--+---+-----1
25
~16
, ,
"
0
,
DIFFERENTIAL INPUT VOLTAGE -
o
10
20
30
40
50
HMPERATURE -
V
SATURATION VOLTAGE
AS A FUNCTION
OF CURRENT
60
70
<,1".0-1....-~0.5,......J....LJ.0--...l-""'0~.5-.l--:'LO
'c
SUPPLY CURRENT
AS A FUNCTION
OF TEMPERATURE
LEAKAGE CURRENT
AS A FUNCTION
OF TEMPERATURE
10 ~ VSI= ±15 ),----+-+-+--t--I
,f-----+----I--+--t---I---I--I~
POSITIVE SUPPLY
OUTPUT LOW
0.'
o
f--------
1"-+-+-+--t--l-f-----t--++--1
tTI:=tl=t:::::t:t:Ltl
o
10
20
30
40
50
TEMPERATURE _ °C
TYPICAL APPLICATIONS
OFFSET NULL CIRCUIT
lr--"lVv--.--o
c:-
$
OFFSET BALANCING
STROBE CIRCUIT
INCREASING INPUT
STAGE CURRENT'
V,
pAll1
3
2N5961
TTL
STROBE
1kQ
STROBING
-=* I ncreases typical common mode slew rate
from 7.0 V/}.J.,sto 18 V/}Js.
4-11
•
FAIRCHILD· /-LA111 • /-LA311
TYPICAL APPLICATIONS (Cont'd)
ADJUSTABLE LOW VOL TAGE
REFE RENCE SUPPLY
ZERO CROSSING DETECTOR
DRIVING MOS LOGIC
POSITIVE PEAK DETECTOR
"3k
"
3k
·Solid tantalum
·Solid tantalum
STROBING OF BOTH INPUT
AND OUTPUT STAGES
DIGITAL
TRANSMISSION ISOLATOR
NEGATIVE PEAK DETECTOR
·Solid tantalum
-Typical input current is 50 pA
with inputs strobed off.
PRECISION PHOTODIODE COMPARATOR
SWITCHING POWER AMPLIFIER
RELAY DRIVER WITH STROBE
R1
'5 V
3.9 k
",
10
"
O.l,uF
• R2 sets the comparison level.
A t comparison, the photodiode has
less than 5 mV across it, decreasing
• Absorbs inductive kickback of relay
and protects Ie from severe voltage
transients on v++ line.
leakages by an order of magnitude.
SWITCHING POWER AMPLIFIER
..
3
"
620
'20
"620
OUTPUT
I
I
A11
620
-,
r 'r6
6
04
03
1" I
R3
620
~Al11
3
61
2'
NS121
R4
300k
510
A12
2N6125
2N6125
I'Al~
'"
W
02_~
.)Q1
AS
39k
1
AlO
620
A13
300k
AS
39k
A14
510
AS
15k
INPUT
t~1
O.22f,lF
"
15k
4-12
p.A139/239/339 • p.A139A/239A1339A
p.A2901 • p.A3302
LOW-POWER, LOW OFFSET VOLTAGE QUAD COMPARATORS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The p.A 139 series consists of four independent precision
voltage comparators designed specifically to operate from a single power supply.
Operation from split power supplies is also possible and the low power supply current
drain is independent of the supply voltage range. Darlington connected PNP input
stage allows the input common-mode voltage to include ground.
•
•
•
•
•
•
•
•
CONNECTION DIAGRAM
14-PIN DIP
PACKAGE OUTLINES 6A 9A
PACKAGE CODES D' P
•
SINGLE SUPPLY OPERATION -+2.0 V TO +36 V
DUAL SUPPLY OPERATION-±1.0 V TO ±18 V
ALLOW COMPARISON OF VOLTAGES NEAR GROUND POTENTIAL
LOW CURRENT DRAIN-800 JJ.A TYP
COMPATIBLE WITH ALL FORMS OF LOGIC
LOW INPUT BIAS CURRENT-25 nA TYP
LOW INPUT OFFSET CURRENT-±5 nA·TYP
LOW OFFSET VOLTAGE - ±2 mV
SCHEMATIC DIAGRAM
v+
ORDER INFORMATION
+INPUT
t:r----l:
OUTPUT
-INPUTo--------+-----+------'
':'
':'
4-13
TYPE
JJ.A139A
JJ.A139
JJ.A239A
JJ.A239A
JJ.A239
JJ.A239
I'A339A
I'A339A
JJ.A339
JJ.A339
I'A2901
I'A2901
JJ.A3302
I'A3302
PART NO.
IlA139ADM
I'A139DM
JJ.A239ADC
JJ.A239APC
I'A239DC
JJ.A239PC
I'A339ADC
JJ.A339APC
I'A339DC
I'A339PC
I'A2901DC
I'A2901PC
I'A3302DC
I'A3302PC
ELECTRICAL CHARACTERISTICS
I'A239A, I'A339A
I'A139A
MIN
Input Offset Voltage
TA -- 25"C, ,Note g,
Input Bias Current
I'N") or IINH with Output in
Linear Range, TA = 25" C, ,Note 5,
Voltage Gain
!...
25
co
ro,
MAX MIN
TYP
MAX
MIN
I'A239, I'A339
±1.0 ±2.0
100
25
I'A2901
±5.0
0
±25
V'-1.5
0.8
on all Comparators, TA = 25°C
MAX
±2.0
±5.0
25
100
MIN
TYP
MAX
MIN
±2.0 ±5.0
TYP
MAX MIN
TYP MAX
±2.0
±7.0
±3.0
±20
mV
25
250
25
500
nA
."
250
25
250
±5.0
V+-1.5
0
2.0
±50
0.8
±5.0
0
2.0
V·-1.5
0.8
±5.0
±25
V·-1.5
0
0.8
2.0
±50
±5.0
0
2.0
50
200
Large Signal
Response Time
Y,N = TTL Logic Swing, Vref =
1.4 V, VRL = 5.0 V, RL = 5.1 kll,
TA=25"C
300
Response Time
VRL = 5.0 V, RL = 5.1 kll,
T A = 25" C, ,Note 7,
1.3
Output Sink Current
V,N(-) ? 1.0 V, VIN(.) = 0,
Va <; 1.5 V, TA = 25"C
Saturation Voltage
VIN(-)? 1.0 V, VIN(.) =0,
Ismk <; 4.0 mA, TA = 25"C
50
200
200
300
200
300
25
±50
V·-1.5
0.8
1.0
V·= 30 V, TA = 25"C
RL? 15 kll, V· = 15 V ,To
Support Large Va Swingl, TA = 25"C
I'A3302
UNITS
TYP
±5.0
0
1.0
2.5
100
0.8
2
±100
nA
V·-1.5
V
2.0
30
mA
VlmV
300
300
ns
300
1.3
1.3
1.3
1.3
I's
l>
.....
Ct.)
co
Ct.)
co
16
mA
co
•
1::
6.0
16
6.0
16
6.0
16
6.0
16
6.0
16
2.0
l>
.....
Ct.)
250
400
250
400
250
400
250
400
250
400
500
mV
co
l>
"I\)
200
Ct.)
200
200
200
Input Offset Voltage
INote 91
4.0
4.0
9.0
9.6
9.0
15
40
mV
Input Offset Current
I'N(.) - I'N(-)
±100
±150
±100
±150
50
200
300
nA
Input Bias Current
IiN(.) or IiN(-) with Output in
Li near Range
300
400
300
400
200
500
1000
nA
200
nA
~
"Ct.)
Ct.)
co
l>
•
1::
l>
0
= 0,
•
1::
Ct.)
1.3
200
V,N(-)? 1.0 V, V'N(')
Islnk'S 4 rnA
J:
rC
"Ct.)
VIN(.)? 1.0 V, V,NH = 0,
Vo =30 V, TA = 25"C
Saturation Voltage
o
"I\)
Output Leakage
Current
Input Common-Mode
Voltage Range
~
JJ
I'N(,! - I'N(-), TA = 25"C
RL =
RL=
TYP
±1.0 ±2.0
Input Common-Mode TA = 25"C, INote 6,
Voltage Range
Supply Current
I'A139
CONDITIONS
CHARACTERISTICS
Input Offset Current
!
~
IV+ = 5 V, Note 4)
V·-2.0
700
0
V·-2.0
700
0
V·-2.0
700
0
V·-2.0
0
700
V·-2.0
400
700
0
V·-2.0
V
700
mV
I\)
co
c
.....
•
1::
l>
Output Leakage
Current
VIN(') ? 1.0 V, V'N(-) = 0,
Vo = 30 V
1.0
1.0
1.0
1.0
Differential Input
Voltage
Keep all VIN's? 0 V (or V-,
if used), (Note 8)
V'
V·
36
36
1.0
1.0
I'A
V'
Vee
V
Ct.)
Ct.)
c
I\)
0
FAIRCHILD. f,tA139/239/339. f,tA139A/239A/339A. f,tA2901· f,tA3302
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V+
Differential Input Voltage
Input Voltage Range
Power Dissipation (Note 1)
9A, 6A
Output Short-Circuit to Gnd, (Note 2)
Input Current (VIN < -0.3 V), (Note 3)
Operating Temperature Range
I-'A339, I-'A339A
I-'A239, I-'A239A
I-'A139,I-'A139A
I-'A2901, I-'A3302
Storage Temperature Range
Pin Temperature (Soldering,
10 seconds)
I-'A 139/I-'A239/I-'A339
I-'A 139A1I-'A239A/I-'A339A
I-'A2901
I-'A3302
36 V or ±18 V
36 V
-0.3 V to +36 V
28 V or ±14 V
28 V
-0.3 V to +28 V
1W
Continuous
50 mA
1W
Continuous
50 mA
O°C to +70°C
-25° C to +85° C
-55° C to +125° C
-40° C to +85° C
-65° C to +150° C
-65°C to +150°C
300°C
300°C
NOTES:
1. For operating at high temperatures, the /lA339/ .uA339A, ,...A2901 ,uA3302 must be derated based on a 125 0 C maximum junction temperature and a thermal
resistance of 125°C/W which applies for the device soldered in a printed circuit board, operating in a still air ambient. The ,uA139 and /-tA139A~
must be derated based on a 1500 C maximum junction temperature. The low bias dissipation and the "ON-OFF' characteristic of the outputs keeps thechip dissipation very small \PD -::; 100 mWI, provided the output transistors are allowed to saturate.
2. Short circuits from the output to V+ can cause excessive heating and eventual destruction. The maximum output current is approximately 20 mA independent of the magnitude of Vi.
3. This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP
transistors becoming forward biased and thereby acting as input diode clamps. In addition tiode action, there is also lateral NPN parasitic transistor
action on the Ie chip. This transistor action can cause the output voltages of the comparators to go to the V+ voltage level lor to ground for a large overdrive I for the time duration that an input is driven negative. This is not destructive and normal output states will reestablish when the Input voltage, which
negative, again returns to a value greater than -0.3 V.
4. These specifications apply for V+ = 5.0 V and -55°e::; TA::; +125°C, unless otherwise stated. With the ~A239/~A239A,aJl temperature specifications
are limited to _25° C::; TA::; +85° e, the ,uA339/,uA339A temperature specifications are limited to 0° e::; TA::; +70°C, and the ,uA2901, ,uA3302 temperature
range is _40° e ::; T A ::; +85° C.
5. The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output so
no loading change exists on the reference or input lines.
6. The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the commonmode voltalge range is V+ -1.5 V, but either or both inputs can go to +30 V without damage.
7. The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 300 ns can be obtained; see typical performance
characteristics section.
8. Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, comparator will provide a proper output state. The low input voltage state must not be less than -0.3 V or 0.3 V below the magnitude of the negative power
supply, if used.
9. At output switch point, Va =: 1.4 V, Rs = on with V+ from 5 V; and over the full input common-mode range 10 V to V+ -1.5 VI.
10. For input signals that exceed VcC,-only the overdriven comparator is affected. With a 5 V supply, VIN should be limited to 25 V max, and a limiting resistor
should be used on all inputs that might exceed the positive supply.
4-15
•
FAIRCHILD.
~A139/239/339. ~A139A/239A/339A. ~A2901. ~A3302
TYPICAL PERFORMANCE CHARACTERISTICS
MA 139/MA239/MA339, MA 139A/MA239A/MA339A, MA3302
SUPPL Y CURRENT
--
1.0
'"
~ 0.8
l- f-
J
TA
I-- I-..- .L'" f-r-
I
...al 0.6
o"
.
TA
o
I 20
RL -
I I
a'J
o
10
20
30
SUPPLY VOLTAGE -
I",
V' -
TA --' 125°C
20
0
I
.0
SUPPLY VOLTAGE -
2D mV
.0
I
0
+
100 mV
0
..
4.0
~~
2
1.5
100
rnA
.0
.....
::II-
100
~o
5
.. "
/smv
II
I 1+50v_
20 mY
J
1.0
0
~5
rr
n
.1
1
3.0
~>
++~-
1.0
0.5
10
INPUT OVERDRIVE = 100 mY
.5.:z>
~a
I I I
I I I
0
1.0
OUTPUT SINK CURRENT -
0
5. 0
:> I
Iw
Vour-
0
0.1
10 -
S>
-
t
0
0.01
RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES - POSITIVE
TRANSITION
'~':=
V
I~~
~
,f%17
V
5.0 mY '" INPUT OVERDRIVE
.0
0.00
t125°~
-55°C
~ ~~A
V
~
~ V ""'TA ~, ,125oC
0.0 1
I
40
30
RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES - NEGATIVE
TRANSITION
..
~
r ,to'~f-
10
V
O. 1
~0:
I
0
40
TA
>
~
T\ -lj5°C
z
I I
o
"T
~
;!;
1. 0
~
55"C
;:r 006
a 40
I I
(I')
>
I
~
RIN (eM) '" 1Qgfl
f- TAI-
0:
+125°C
VIN {eM) =- 0 V
I
60
is0:
~-"+C
..-
" 0.2
...I
Q
~
~ 0.4
I
O'f
10
I
-55°C
TA - +25 C
;'
0:
0:
=
OUTPUT SATURATION VOLTAGE
INPUT CURRENT
80
TA
~~IT'
J
of0
T,-rC- -
+
Your
-
I
0.5
2.0
1.0
1.5
2.0
TIME-/-Is
TIME-/-Is
TYPICAL PERFORMANCE CHARACTERISTICS MA2901
SUPPLY CURRENT
RL - ..
.......- r-;:-A
1.2
E
I
ffi 1.0
I
.......-
<
/'
0:
0:
V" I--ir~
, / r-
"o "
~ 0.8
10
~
TA ,_40 C_ I--0
I
~ 60
o,h
"
o
'"
<
w
V
10
V' -
20
30
~
-
SUPPLY VOLTAGE -
TA
o
V' -
20
0.01
.;;:
30
SUPPLY VOLTAGE -
V
0.1
10 -
=
V
.0
20 mV
.0
.0
INPUT OVERDRIVE
.0
+5 V
'~"=
+
100 mV
5mV
.0
VOUT-
.0
I
a
of-
I
a
rr~-
0.5
1.0
TIME -
1.5
J
0
I I I
J
I
20 mY
I I I
a
a
n
r
.0
-
0
INPUT OVERDRIVE = 100 mV
.0
+
-
1.0
TIME-/-Is
MS
4-16
YOUT
I I I I
I I
0.5
2.0
..~~
T,orCf- f-
1.5
10
OUTPUT SINK CURRENT -
.0
5.0 mY
.0
~~
~v
0.001
0.01
40
!/
~~
"""
~V
RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES - POSITIVE
TRANSITION
.0
~1O
~
A
"# ~ '-TFO'C
Tf -iOOC
/~~
0:
I
10
V
0.1
;:
I . 85'IC
RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES - NEGATIVE
TRANSITION
.0
.
-
I
o
40
TA = +85 Q C
TA;" +25°C
>
TA~ -
"~' 20
I
~
o
40
...
f.-- ¢ ' 8 5 ' C
V
Cl
TA - DOC
iii
I
>
I
-
I
0:
0:
TA - +2SoC
/'
"'" 0.'
40°C
H-
f- V"
OUTPUT SATURATION VOL7AGE
INPUT CURRENT
80
=
2.0
100
rnA
FAIRCHILD. J..lA139/239/339. J..lA139A/239A/339A. J..lA2901. J..lA3302
APPLICATION HINTS
The fJ.A 139 series are high-gain, wide-bandwidth devices which, like most compaFators, can easily
oscillate if the output lead is inadvertently allowed to capacitively couple to the inputs via
stray capacitance. This shows up only during the output voltage transition intervals as the comparator changes states. Power supply bypassing is not required to solve this problem. Standard PC
board layout is helpful as it reduces stray input-output coupling. Reducing the input resistors to
< 10 kn reduces the feedback signal levels and finally, adding even a small amount (1.0 to 10 mV) of
positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback
are not possible. Simply socketing the IC and attaching resistors to the pins will cause
input-output oscillations during the small transition intervals unless hysteresis is used. If the
input signal is a pulse waveform, with relatively fast rise and fall times, hysteresis is not required.
~I pi~ of any unused comparators should be grOund:0
The bias network of the fJ.A 139 series establishes a drain current which is independent of the magnitude of the power supply voltage over the range of from 2 V to 30 V.
•
It is usually unnecessary to use a bypass capacitor across the power supply line.
G e differential input voltage may be larger than V+ without damaging the devi;;"rotection
should be provided to prevent the input voltages from going negative more than -ffi(at 25° C).
An input clamp diode can be used as shown in the applications section.
The output of the fJ.A139 series is the uncommitted collector of a grounded-emitter npn output
transistor. Many collectors can be tied together to provide an output ~Ring function. An output
pull-up resistor can be connected .to any available power supply voltage within the permitted
supply voltage range and there is no restriction on this voltage due to the magnitude of the voltage
which is applied to the V+ terminal of the fJ.A139 package. The output can also be used as asimple
SPSTswitch to ground (when a pull-up resistor is not used). The amount of current which the output device can sink is limited by the drive available (which is independent of V+) and the f3 of this
device. When th-e maximum current limit is reached (approximately 16 mAl, the output transistor
will come out of saturation and the output voltage will rise very rapidly. The output saturation
voltage is limited by the approximately 60 n saturation resistance of the output transistor. The
low offset voltage of the output transistor (1 mV) allows the output to clamp essentially to ground
level for small load currents.
TYPICAL APPLICATIONS (V+ = 15 V)
ONE-SHOT MUL TIVIBRATOR
AND GATE
39 k
3.0 k
10k
PW
;:I'"E:
1ms_ _--V'
100k
In
1N914
lOOk
lOOk
co--'./V'.---'
V;:r
0.001 F
"0" "1"
1N914
1.0M
OR GATE
BI-STABLE MULTIVIBRATOR
200 k
3.0k
15k
lOOk
51k
V~::rL
V'::::IL
o
4-17
100 k
50-""'--+--1
100 k
Ro-"""......----/
tl
o
FAIRCHILD· MA139/239/339. MA139A/239A/339A. MA2901. MA3302
TYPICAL APPLICATIONS (V+ = 15 V) IConU
LARGE .FAN-IN AND GATE
ONE-SHOT MUL TIVIBRATOR WITH INPUT LOCK OUT
V'
V'
10M
15k
560k
100 >
--rE
40"S~'"
'.V
1 "s
t" I,
o
240k
.2>
All DIODES 1N914
TIME DELAY GENERATOR
V'
ORING THE OUTPUTS
10>
15
>
V'
3.0 k
200 k
10M
10
>
V::.::.r
V,
",
v,
tJ
3.0 k
51k
10 M
INPUT GATING
SIGNAL
V~::rlI"
I~
3.0k
51 k
10 M
v+ -----------.;0&10 k
I
I
I
I
: -1
0 10
11
t2
IJ
V,
t~
-1--.
51k
PULSE GENERATOR
SQUAREWAVE OSCILLATOR
V'
V'
4.3k
lOOk
61.1~V+
lotI
12
V·D--"I>Iv-_e_-I
1.0 M
"FOR LARGE RATIOS OF R1JR2,
01 CAN BE OMITTED
4-18
FAIRCHILD. IlA139/239/339. IlA139A/239A/339A. IlA2901. IlA3302
TYPICAL APPLICATIONS (V+ = 15 V) l Cant.)
INVERTING COMPARATOR WITH HYSTERESIS
NON-INVERTING COMPARATOR WITH HYSTERESIS
Y+
Y+
. VIN
0------1
1.0 M
Y"
1.0M
1.0M
COMPARING INPUT VOLTAGES
OF OPPOSITE POLARITY
OUTPUT STROBING
BASIC COMPARATOR
Y+
Y'
'OR LOGIC GATE WITHOUT
PULL-UP RESISTOR
TWO-DECADE HIGH-FREQUENCY VCO
Y+
V'
100 k
3.0 k
'Vc
FREQUENCY
CONTROL
VOLTAGE
INPUT
0.1 pF
OUTPUT 1
20 k
OUTPUT 2
50 k
v+ ~30 V
1-250 mV Vc
'50 V
700 Hz· 10
100 kHz
CRYSTAL CONTROLLED OSCILLATOR
LIMIT COMPARATOR
v+
V'
(12 V)
2.0k
200 k
lOOk
10 k
V,
1100kHz
4-19
•
FAIRCHILD. /lA139/239/339· /lA139A/239A/339A· /lA2901. /lA3302
TYPICAL APPLICATIONS (V+ = 15 V) (Cont.)
LOW
F~EQUENCY
LOW FREQUENCY OP AMP
(Vo ~ 0 V FOR VIN ~ 0 V)
OP AMP
TRANSDUCER AMPLIFIER
v+
V+
10 k
MAGNETIC
PICKUP
3.0 k
II
v,
1.0k
Av
1.Ok
Av
100
100
10k
ZERO CROSSING DETECTOR (SINGLE POWER SUPPLY)
LOW FREQUENCY OP AMP WITH OFFSET ADJUST
V+
+-----,I\N----+-ov"
A2
1.0 k
10k
100 k
SPLIT-SUPPLY APPLICATIONS V+
= +15V
and V-
= -15V
ZERO CROSSING DETECTOR
MOS CLOCK DRIVER
V+
v+
3.9k
2.4 k
2.4 k
51k
V-
COMPARATOR WITH A NEGATIVE REFERENCE
V+
v-
4-20
lJA710
HIGH SPEED DIFFERENTIAL COMPARATOR
FAIRCH ILD LIN EAR INTEGRATED CIRCU IT
GENERAL DESCRIPTION -
The /lA710 is a Differential Voltage Comparator intended for
CONNECTION DIAGRAMS
8·PIN METAL CAN
(TOP VIEW)
PACKAGE OUTLINE 5S
PACKAGE CODE H
applications requiring high accuracy and fast response times. It is constructed on a single silicon chip
using the Fairchild Planar* epitaxial process. The device is useful as a variable threshold Schmitt
trigger, a pulse height discriminator, a voltage comparator in high speed AID converters, a memory
sense amplifier or a high noise immunity line receiver. The output of the comparator is compatible
with all integrated logic forms.
v+
•
•
•
•
5 mV MAXIMUM OFFSET VOLTAGE
5/lA MAXIMUM OFFSET CURRENT
1000 MINIMUM VOLTAGE GAIN
20 /lvl'c MAXIMUM OFFSET VOLTAGE DRIFT
I
v-
ABSOLUTE MAXIMUM RATINGS
NOTE: Pin 4 connected to case.
Positive Supply Voltage
Negative Supply Voltage
Peak Ouput Current
Differential Input Voltage
Input Voltage
Internal Power Dissipation (Note 1)
Metal Can
DIP
Flatpak
+14.0V
-7.0 V
10 mA
±5.0 V
±7.0 V
ORDER INFORMATION
TYPE
PART NO.
/lA71 OHM
/lA71 0
/lA710C
/lA710HC
14·PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 6A 9A
PACKAGE CODES D
P
500mW
670mW
570mW
Storage Temperature Range
-65°C to +150°C
_55° C to +125° C
Metal Can, Hermetic DIP and Flatpak
Molded DIP
NC
GND
Operating Temperature Range
Military (/lA710)
Commercial (/lA710C)
-55°C to +125°C
O°C to +70°C
+IN
-IN
Pin Temperature
Metal Can, Hermetic DIP and Flatpak (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
300°C
260°C
EOUIVALENT CIRCUIT
v+
NC
OUT
NC
NC
ORDER INFORMATION
TYPE
PART NO.
/lA710DM
/lA710
/lA710DC
/lA710C
/lA710PC
/lA710C
R5
3.9 kn
R3
1.1 kn
10·PIN FLATPAK
(TOP VIEW)
PACKAGE OUTLINE 3F
PACKAGE CODE F
R,
500n
NON·
INVERTING
INPUT
NC
v-
o---t--------;:::
GND
NC
-+:IN
NC
c:=:::l--'
NC C:=:::l--'
v+
-IN
v-
v-
NC
L-C:=::::J0UT
ORDER INFORMATION
TYPE
PART NO.
/lA710FM
/lA710
"'Planar is a patented Fairchild process.
Notes on following pages.
4-21
FAIRCHILD. MA710
MA7l0
ELECTRICAL CHARACTERISTICS: T A = 25°C, V+ = 12.0 V, V- = -6.0 V unless otherwise specified.
CHARACTER ISTICS
CONDITIONS
(Note 2)
MIN
TYP
MAX
!
UNITS
-Input Offset Voltage
Input Offset Current
RS <; 200
n
Input Bias Current
Voltage Gain
Output Resistance
Output Sink Current
Response Time (Note 3)
1250
2.0
Ll.VIN ;> 5 mV, VOUT - 0
The following specifications apply for - 55° C '" T A'" +125°C'
Input Offset Voltage
RS <; 200 n
Average Temperature Coefficient
RS 50 n, TA 25 C to TA +125 C
of Input Offset Voltage
R S = 50 n, T A = 25° C to T A = _55 0 C
TA - +125°C
TA = _55°C
Average Temperature Coefficient
T A-25° C to T A - +125° C
of Input Offset Current
T A = 25° C to T A = -55 0 C
I nput Bias Current
TA - -55~C
Input Voltage Range
V- -7.0 V
Common Mode Rejection Ratio
RS <; 200 n
~
Differential Input Voltage Range
Voltage Gai n
Output Sink Current
Positive Supply Current
Negative Supply Current
Power Consumption
2.0
3.0
20
mV
~---;A
I'A
n
mA
ns
~
3.5
2.7
0.25
1.8
5.0
15
27
~~~--.
Output HIGH Voltage
Output LOW Voltage
0.6
0.75
13
1700
200
2.5
40
Ll.VIN;> 5 mV,O <; lOUT <; 5.0 mA
Ll.VIN;>5mV
TA - +125°C, Ll.VIN;> 5 mV, VOUT-O
TA = -55°C,Ll.VIN;> 5 mV, VOUT =0
±5.0
80
±5.0
1000
2.5
-1.0
0.5
1.0
VOUT <; 0
VOUT Gnd, Inverting Input +5 mV
VOUT - Gnd, Inverting Input - +10 mV
3.0
10
10
3.0
7.0
25
75
45
mV
I'VI C
I'V/oC
4.0
0
V
V
mA
mA
mA
mA
mW
100
3.2
-0.5
1.7
2.3
5.2
4.6
90
9.0
7.0
150
I'A
I'A
nA/oC
nArC
I'A
V
dB
V
IlA7l0C
ELECTRICAL CHARACTERISTICS: T A = 25°C, V+ = 12.0 V, V- = -6.0 V unless otherwise specified
CHARACTER ISTICS
CONDITIONS
(Note 2)
Input Offset Voltage
RS <; 200
MIN
n
Input Offset Current
I nput Bias Current
Voltage Gai n
1000
Output Resistance
Output Sink Current
1.6
Ll.VIN;>5mV,VOUT=0
Response Time (Note 2)
TYP
MAX
UNITS
1.6
1.8
16
1500
200
2.5
40
5.0
5.0
25
mV
I'A
I'A
n
mA
ns
The following specifications apply for O°C",;;; T A"';;; +70°C:
Input Offset Voltage
Average Temperature Coefficient
RS <; 200 n
R S - 50 n, T A - 0" C to T A - +70° C
--
5.0
6.5
20
mV
I'vtc
15
24
25
7.5
50
100
40
I'A
nA/oC
nA/oC
3.2
0.5
4.0
0
V
V
mA
5.2
4.6
90
9.0
7.0
150
rnA
of Input Offset Voltage
Input Offset Current
Average Temperature Coefficient
of Input Offset Current
I nput Bias Current
Input Voltage Range
Common Mode Rejection Ratio
TA
TA
TA
V
RS
=25°Cto TA = +70°C
~ 25° C to T A ~ 0° C
_O°C
- -7.0 V
<; 200 n
±5.0
70
±5.0
800
Differential Input Voltage Range
Voltage Gain
Output HIGH Voltage
Output LOW Voltage
Output Sink Current
Positive Supply Current
Negative Supply Current
Power Consumption
Ll.VIN ;> 5 mV, 0<; lOUT <; 5.0 mA
Ll.VIN ;> 5 mV
Ll.VIN;> 5 mV, VOUT 0
VOUT <; 0
VOUT - Gnd, Inverting Input - +5 mV
VOUT - Gnd, Inverting Input +10 mV
NOTES:
1. Rating applies to ambient temperatures up to 70 o e. Above 70 D
2.
3.
e
2.5
1.0
0.5
98
I'A
V
dB
V
mA
mW
ambient derate linearly at 6.3 mW/oe" for Metal Can, 8.3 mW/e for DIP,
and 7.1 mW/e for the Flatpak.
The input offset voltage and input offset current (see definitions) are specified for a logic threshold voltage as follows: For 710,1.8 V at
_55°e, 1.4 V at +25°C, 1.0 V at +125°C. For 710C, 1.5 V at oDe, 1.4 V at +25°C, and 1.2 V at +70 oC.
The response time specified (see definitions) is for a 100 mV input step with 5 mV overdrive.
4-22
FAIRCHILD. J..IA710
TVPI~AL
PERFORMANCE CURVES FOR J..IA710
VOLTAGE GAIN
AS A FUNCTION OF
AMBIENT TEMPERATURE
VOLTAGE TRANSFER
CHARACTERISTIC
'"
v+·
r-..
ITOO
,_of-++-+--+-c1i
'f{-,i,/4-'++-+--1
,{~.V
" '\
1600
\
1\
'"
-------'ir-15"'-f-+-j
-l.O_5~.O;-'--:':;".;;-O...L-:-";';.O,..-l--;-I.';-O...L-''''.O;---'---,'5.0
V
V
''''' V
lJOO
V
V
:::::::
{~,.......,
{-.~P
./
'\
1500
if
t- T;-"!'
12V
v-·'6.0v
l ,I
i ..
1.0 r-t-t-t-+ih,
/;/\f-+-+-+-+-i
VOLTAGE GAIN
AS A FUNCTION OF
SUPPLY VOLTAGES
. / 1--"1
/'
/'
500
OJ
20
OJ
10
100
10
14)
11
lJ
POSITIVE SUPPLY VOLTAGE - V
TEMPERATURE _ °c
INPUTVOlTAGl - mV
COMMON MODE REJECTION RATIO
AS A FUNCTION OF
AMBIENT TEMPERATURE
INPUT OFFSET CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE
INPUT BIAS CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE
14
1.0
104
1
V
1---+--+----1--1+--+----1---1
0
I I
I I
f--+----+-----+---+-f---+----1
r-r-.
lOGIC1rI-fRESHtovolTAGf- -
I I
I I
NEGATlVEOUTPUTlfVEl
I I
-I. 0
TEMPERATURE" aC
RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVES
TEMPERATURE -
RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVES
"'
°c
70
COMMON MODE
PULSE RESPONSE
0
0
0
.fI
2{)mV-
0
i'-
S.OmV
0
Vi
IOmv
0
0
10
TEMPERATURE'OC
•. 0
70
V··12V
V···6.0Y
POSITlVEOUTPurUVEl
t-----t---+----ir------t----t----j-----i
l.O
60
OUTPUT VOLTAGE LEVELS
AS A FUNCTION OF
AMBIENT TEMPERATURE
l.>
e.---+--+----ie.-----t---+------t-----i
30
40
50
TEMPERATURE, 'c
/
W
U)mV -
0
2.0mV
\
10m'
Iv)·om' ;--.
100
20
«l
bO
TIME -
80
fl~
100
V"'llV
V'·-6.0V
0
I I
I I
I
0
I. 0
W
«l
fJJ
TIME - ns
4-24
80
\00
500.",111)(:
v o.,
--
---
0
\TC
0
120
g
~~
100
0
2. 0
I
-1. 0
V+··llV
V··'6.0V
TA ' 25°C
~
Or---rr- "M
Or- ~~
~
-1. 0
V···12V
V,··6V
1A ' 25¢C
0
~ 2,OmV
0
rn
"
TIME'
110
n~
I",
JLA711
DUAL HIGH-SPEED DIFFERENTIAL COMPARATOR
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION -
The IlA711 is a Dual, Differential Voltage Comparator intended
primarily for core~memory sense amplifier applications. The device features high accuracy, fast response
CONNECTION DIAGRAMS
10-PIN METAL CAN
(TOP VIEWS)
PACKAGE OUTLINES 5F 5N
PACKAGE CODES H
H
v+
times, large input voltage range, low powe~ consumption and compatibility with practically all
integrated logic forms. When used as a sense amplifier, the threshold voltage can be adjusted over a
wide range, almost independent of the integrated circuit characteristics. Independent strobing of each
comparator channel is provided, and pulse stretching on the output is easily accomplished. Other
applications of the dual comparator include a window discriminator in pulse height detectors and a
double-ended limit detector for automatic Go/No-Go test equipment. The ~A711, which is similar to
the ,uA710 differential comparator, is constructed using the Fairchild Planar* epitaxial process.
•
•
•
•
II
FAST RESPONSE TIME..
40 ns TYPICAL
5 mV MAXIMUM OFFSET VOLTAGE
10llA MAXIMUM OFFSET CURRENT
INDEPENDENT STROBING OF EACH COMPARATOR
vNOTE: Pin 5 connected to case,
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
I nput Voltage
Strobe Voltage
Internal Power Dissipation (Note 1)
Metal Can
DIP
Flatpak
Operating Temperature Range
Military (IlA711)
Commercial (IlA711C)
Storage Temperature Range
Pin Temperature
Metal Can, Hermetic DIP and Flatpak (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
ORDER INFORMATION
TYPE
PART NO.
IlA711
/lA711HM
IlA711C
/lA711HC
+14 V
-7.0V
50mA
±5.0 V
±7.0 V
o to +6.0 V
14-PIN DIP
PACKAGE OUTLINES 6A 9A
PACKAGE CODES D
P
500 mW
670mW
570 mW
NC
-55'C to +125'C
O°C to +70'C
_65°C to +150°C
STR08E A
+ IN A
GND
v-
300°C
260°C
NC
-IN A
v'
+ IN B
OUT
-IN B
STR08E 8
NC
NC
EaUIVALENT CIRCUIT
STROBE A
STROBE B
ORDER INFORMATION
TYPE
PART NO,
IlA711DM
/lA711
/lA711DC
/lA711C
IlA711PC
/lA711C
r---~------------~--~--~----~--~------------~--~--~v'
10-PIN FLATPAK
PACKAGE OUTLINE 3F
PACKAGE CODE F
c=::pq~;;:===l==::J STROBE A
+IN A
c=:::J---1V
GND
v'
-IN
t--;:==JOUT
Bc==t::li::::::::==:::1==::J STROBE B
ORDER INFORMATION
PART NO.
TYPE
/lA711FM
/lA711
Notes on following page.
·Planar is a patented Fairchild process,
4-25
FAIRCHILD • p,A711
[-
I
pA7ll
ELECTRICAL CHARACTERISTICS: TA= 25"C, V+= 12 V, V-= -6.0 V uriless otherwise specified
CONDITIONS
CHARACTERISTICS
Input Offset Voltage
Input Offset Current
MIN
VOUT = +1.4 V, RS <;;200
VOUT = +1.4 V, RS <;;200
n, VCM = 0
n
VOUT = 1.4 V
Input Bias Current
750
Voltage Gain
MAX
UNITS
1.0
3.5
mV
1.0
5.0
mV
0.5
10.0
IJ.A
25
75
IJ.A
TYP
1500
Response Time (Note 2)
40
Strobe Release Time
12
Input Voltage Range
V-=-7.0V
ns
ns
V
±5.0
V
±5.0
Differential Input Voltage Range
n
200
Output Resistance
4.5
Output HIGH Voltage
VIN;>10mV
Loaded Output HIGH Voltage
VIN ;> 10 mV, 10 = 5mA
Output LOW Voltage
2.5
3.5
VIN ;'10mV
-1.0
-0.5
-1.0
5.0
V
0
V
V
0
V
Strobed Output Level
VSTROBE <;;0.3 V
Output Sink Current
VIN;'1O mV, Vout;'O
Strobe Current
VSTROBE = 100mV
1.2
Positive Supply Current
VOUT = Gnd, Inverting Input = +5mV
8.6
mA
Negative Supply Current
VOUT = Gnd, Inverting Input = +5mV
3.9
mA
0.5
130
Power Consumption
mA
0.8
2.5
200
mA
mW
The following specifications apply for ·-55° C <;; T A <;; +125° C'
Input Offset Voltage (Note 3)
RS <;;200
RS <;;200
n,
n
VCM = 0
4.5
mV
6.0
mV
Input Offset Current (Note 3)
'20
IJ.A
Input Bias Current
150
IJ.A
Temperature Coefficient of
5.0
Input Offset Voltage
NOTES:
1. Rating applies to am~ient temperatures up to 70o e. Above 700
IJ.V;OC
500
Voltage Gain
e
ambient derate linearly at 6.3 mW/C for the Metal Can, 8.3 mW/C for
the DIP, and 7.1 mW/ C for the Flatpak.
2. The response time specified (see definitions) is for a 100 mV step input with 5 mV overdrive.
3. The input offset voltage is specified for a logic threshold as follows:
711: 1.8 Vat-55°C, 1.4 V at+ 2SoC, 1.0 V at+125°C
711C: 1.5 V at aOc, 1.4 V at +250C, 1.2 Vat +70o C
4-26
FAIRCHILD • /LA711
.uA711 C
ELECTRICAL CHARACTERISTICS: T A= 25°C, V+= 12 V, V-= -6.0 V unless otherwise specified
CONDITIONS
CHARACTERISTICS
MIN
TYP
MAX
UNITS
I
I nput Offset Voltage
I nput Offset Current
VOUT = +1.4 V, RS ";;200 n, VCM = 0
1.0
5.0
VOUT = +1.4 V, RS ";;200 n
1.0
7.5
mV
VOUT=+1.4V
0.5
15
"A
25
100
"A
Input Bias Current
Voltage Gain
700
mV
1500
Response Time (Note 2)
40
ns
Strobe Release Time
12
ns
I nput Voltage Range
V
= -7.0 V
±5.0
Differential Input Voltage Range
V
±5.0
Output Resistance
V
200
Output HIGH Voltage
VIN ;>1OmV
Loaded Output HIGH Voltage
VIN ;>10 mV, 10 = 5 mA
Output LOW Voltage
4.5
2.5
3.5
VIN ;> 10 mV
-1.0
-0.5
Strobed Output Level
VSTROBE ";;0.3 V
--1.0
Output Sink Current
VIN ;>10mV, VOUT;>O
Strobe Current
VSTROBE = 100 mV
1.2
Positive Supply Current
VOUT Gnd, Inverting Input = +10mV
S.6
Negative Suppfy Current
VOUTGnd, Inverting Input = +10mV
3.9
0.5
Power Consumption
n
5.0
V
0
V
V
0
O.S
130
V
mA
2.5
mA
mA
mA
230
mW
6.0
mV
The following specifications apply for 0° C ~ TA .::;;; +70 0 C·
Input Offset Voltage (Note 3)
RS.,;;200n,vCM=0
RS .,;; 200 n
I nput Offset Current (Note 3)
Input Bias Current
10
mV
25
"A
150
"A
Temperature Coefficient of
I nput Offset Voltage
5.0
Voltage Gain
500
4-27
}.NtC
•
FAIRCHILD • JLA711
TYPICAL PERFORMANCE CURVES FOR MA7ll AND MA7llC
VOLTAGE TRANSFER
CHARACTERISTIC
VOLTAGE TRANSFER
CHARACTERISTIC
ILA711
ILA711C
5.0
1100
5.0
V+· +12'0'
V-' -6,0'0'
~p,,
1'/
4.0
3.0
~
.,
il
/It
-
-1.0
-5.0
1.0
~
g
3.0
-5.0
-3.0
INPUT VOLTAGE -' mV
-i.0
1.0
INPUT VOLTAGE -
TA •
/'
21m
~7V
1600
V
/
1200
800
11
.--- ~
.---I -
V .--- ~
40010
V
3.0
5.0
~
~
--
!I~
>1.,
>100
v+-
1 1
+12'0'
v-' -b.av
TA ozsoc
2.0
.0 '..
~~
1 1 1 1 I
of--
3>
r-
~
50
"out
Ein
~~
II
1
3.0
,,>
10~
f---f.. -
f-- -
1
I
1 1 1 1
1 1 1 1
1.0
o
.,
0
14
POSITIVE SUPPLY VOLTAGE - V
INPUT BIAS CURRENT
AS A FUNCTION OF
AMBI ENT TEMPERA TUR E
80
TIME • ns
110
160
RESPONSE TIME
FOR VARIOUS INPUT
OVERDRIVES
5.0
"\
.,
>10
>60
TEMPERATURE"C
-10
COMMON MODE
PULSE RESPONSE
~~
12
1"1"-
1100
-60
mv
zsoc
1400
"-
.-
VOLTAGE GAIN
AS A FUNCTION OF
SUPPLY VOLTAGES
1800
"-
lJoo
--_. -
-- ,=
--
=
5.0
"-
1«XI
-I,D
+1.0
1500
t5
;
I
I
--f--
-1.0
3.0
o!tc
TA
+looe
'1/,1
I
0
-- '_~5°C
<25°C / ITA'
T,
'--
1.0
iii
+2SOC
+125°C
0
1,1,/
-
t5
iI/
1.0
1600
3.0
g
V+" +12'0'
V-' -6.0'0'
"-
f;?- -
4.0
!
/1/
ill
V+ • +12V
V- • -6,OV
I,
2.01
VOLTAGE GAIN
AS A FUNCTION OF
AMBIENT TEMPERATURE
>
V+" +12'0'
v-· -6.0V
g
\
I'\..
3D
4.0
3.0
t5
1:'
il
"'-
r--....
10
10mvri
2.0
I
VT
5.0mV
1.0
...l-2.0mV
IOmV
0
V+" +12'0'
V·, -6.0'0'
r... ·25°C
-1.0
~
I--
t5 100
~
~
10
0
-60
-10
>10
>60
TEMPERATURE - °c
>100
>1.,
1.0
60
'0'*--6.011 TA • 25~C
2.0
1.0
0
-1.0
la V
r- 4'
0
10
10
3D
TlNi - ns
4.0 _
tUFT
2.0
~/
o
OmV
-l.~mv
.,
.,
60
100
80
110
"'
1.,
v>l.
-
rj
~
'~~:V~I
f=
~ffi"~",c~""A'
1
1
0
100
130
~;" ~*4<- '12~
v-· -6.0'0'
TA "2SoC
j
r~l--l.omv
10
POWER CONSUMPTION
AS A FUNCTION OF
AMBIENT TEMPERATURE
~.~:.~:'
Iel
V+- +12'0'
0
5.0mV
0
OUTPUT PULSE
STRETCHING WITH
CAPACITIVE LOADING
3.0
/
0
TIM!
STROBE RELEASE TIME
FOR VARIOUS INPUT
OVERDRIVES
1.0
50
-w
-10
1'--1'-,
'\..
>..
>10
TEMPERATURE -
doo
"c
>1.,
lJA734
PRECISION VOLTAGE COMPARATOR
FAI RCH ILD LINEAR INTEGRATED CIRCU IT
GENERAL DESCRIPTION - The IlA 734 is a Precision Voltage Comparator constructed on a single
silicon chip using the Fairchild Planar* epitaxial proces~. It is specifically designed for high accuracy
level sensing and measuring applications. The ,uA734 is extremely useful for analog·to-digital
converters with twelve bit accuracies and one mega-bit conversion rates. Maximum reso1ution is
obtained by high gain, low input offset current, and low input offset voltage. Its superior temperature
stability can be improved by offset nulling which further reduces offset voltage drift. Balanced or
CONNECTION DIAGRAMS
10-PIN METAL CAN
(TOP VIEW)
PACKAGE OUTLINE
PACKAGE CODE
5N
H
unbalanced supply operation and standard TTL logic compatibility enhance the ,uA 734'5 versati Iity.
•
•
•
•
•
•
•
I
+ IN
CONSTANT INPUT IMPEDANCE OVER DIFFERENTIAL INPUT RANGE
HIGH INPUT IMPEDANCE - 55 MD
LOW DRIFT - 3.5 IlV/'C
HIGH GAIN - 60 k
BALANCED OFFSET NULL CAPABILITY
WIDE SUPPLY VOLTAGE RANGE - ±5 V to ±18 V
TTL COMPATIBLE
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
v-
±18 V
10 mA
±10 V
±13V
±0.5 V
Peak Output Current
Differential Input Voltage
Input Voltage Range (Note 1)
Voltage Between Offset Null and VInternal Power Dissipation (Note 2)
500 mW
670 mW
Metal Can
DIP
Operating Temperature Range
_55°C to +125°C
O°C to +70°C
Military (IlA734)
Commercial (/lA734C)
ORDER INFORMATION
PART NO.
TYPE
IlA734HM
IlA734
IlA 734HC
1l734C
Storage Temperature Range
-65°C to +150°C
300°C
Metal Can, DIP
Pin Temperature (Soldering, 60 s Maxi
EQUIVALENT CIRCUIT
RS
'00
R,
200
R6
14-PIN DIP
(TOP VIEW)
PACKAGE OUTLINE 6A
PACKAGE COD~ D
6.0k
NC
RS
0"
RW
"0
(-)
NC
OUT
v+
0"
R"
01
14 PULL-UP
RESISTOR
13
NC
v-
+IN
R"
,9<
NC
NC
-IN
Rn
(.,0---+---------1---------+-----'
0"
0>5
R>5
R18
3.6k
R"
3,6k
R"
"0
On
ORDER INFORMATION
PART NO.
TYPE
IlA734DM
IlA734
IlA 734DC
IlA 734C
*Planar is a patented Fairchild process.
Notes on following pages.
4-29
FAIRCHILD • I-tA734
±15 VOLT OPERATION FOR IlA734C
ELECTRICAL CHARACTERISTICS: TA
~
25'C, Pin 8 tied to +15 V, unless otherwise specified, Note 3.
CHARACTER ISTICS
CONDITIONS
Input Offset Voltage
MIN
RS';; 50 kD.
Input Offset Current
Input Bias Current
7.0
Input Resistance
input Capacitance
Offset Voltage Adjustment Range
RL
Large Signal Voltage Gain
~
1.5 kn to +5.0 V
35 k
TYP
MAX
UNITS
1.1
5.0
mV
3.5
25
nA
30
100
nA
55
MD.
3.0
pF
8.5
mV
60 k
V/V
Positive Supply Current - Output LOW
4.0
Negative Supply Current - Output LOW
1.5
2.0
mA
Power Consumption - Output LOW
82
105
mW
Transient Response
RL
~
1.5 kn to +5.0 V
5.0
mA
ns
200
5 mV Overdrive, 100 mV Pulse
The following specifications apply for
Input Offset Voltage
aOe
~ TA
< +70
Q
C
RS';; 50 kD.
1.2
7.5
mV
4.0
45
nA
3.5
20
iJ-V/'C
TA ~ +25'C to +70'C
0.02
0.3
nArC
TA ~ 125'C to O'C
0.05
0.75
nA/'C
Input Offset Current
Average Input Offset Voltage Drift
RS';; 50 n
Without External Trim
Average Input Offset Current Drift
Input Bias Current
large Signal Voltage Gain
150
RL
~
1.5 kr! to +5.0 V
25 k
nA
V/V
Input Common Mode Voltage Range
±10
V
Differential Input Voltage Range
±10
V
Common Mode Rejection Ratio
RS';; 50 kn
Supply Voltage Rejection Ratio
RS';; 50 kr!
VS~
70
100
6.0
dB
100
iJ-V/V
±5Vto±18V
lOUT ~ 0.080 rnA
7.0
lOUT ~ 0.080 rnA, Vs ~ +5.0 V
2.4
V
Output HIGH Voltage
5.0
V
0.4
V
7.0
rnA
Negative Supply Current - Output LOW
2.5
mA
Power Dissipation - Output LOW
145
mW
Output LOW Voltage
ISINK
~
3.2 rnA
Positive Supply Current - Output LOW
4-30
FAIRCHILD • p.,A734
±15 VOLT OPERATION FOR pA734
ELECTRICAL CHARACTERISTICS: TA ~ 25'C, Pin 8 tied to +15 V, unless otherwise specified, Note 3.
CHARACTERISTICS
Input Offset Voltage
CONDITIONS
MIN
RS'( 50 U,
TYP
0.9
MAX
UNITS
3.0
mV
Input Offset Current
1.5
10
nA
Input Bias Current
28
50
nA
60
Ml1
Input Capacitance
3.0
pF
Offset Voltage Adjustment Range
8.5
mV
70 k
V/V
20
Input Resistance
Large Signal Voltage Gain
RL
~
1.5 kl1 to +5.0 V
35 k
Positive Supply Current - Output LOW
4.0
5.0
mA
Negative Supply Current - Output LOW
1.5
2.0
mA
Power Consumption - Output LOW
82
105
mW
Transient Response
RL
~
ns
200
1.5 kl1 to +5.0 V
5 mV Overdrive. 100 mV Pulse
The following specifications apply for _55 0 C ~ T A
Input Offset Voltage
-<
+125° C
RS'( 50 kl1
Input Offset Current
Average Input Offset Voltage Drift
1.1
4.0
mV
3.0
20
nA
RS'( 50 kl1
2.5
15
"vtc
TA~+25°Cto+125°C
0.01
0.1
nAloC
T A ~ +250 C
0.05
0.4
nA/oC
150
nA
Without External Trim
Average I nput Offset Current Drift
to
_55' C
Input Bias Current
Large Signal Volt<::ge Gain
RL
~
1.5 kl1 to +5.0 V
Input Common Mode Voltage Range
RS'( 50 kl1
Supply Voltage Rejection Ratio
RS '( 50 kl1
~
V/V
±10
V
V
±10
Differential Input Voltage Range
Common Mode Rejection Ratio
Vs
25 k
70
100
5.0
dB
100
"V/V
±5 V to ±18 V
lOUT ~ 0.080 mA
7.0
lOUT ~ 0.080 mA, V8 ~ +5.0 V
2.4
V
Output HIGH Voltage
ISINK ~ 3.2 mA
5.0
V
0.4
V
Positive Supply Current - Output LOW
7.0
mA
Negative Supply Current - Output LOW
2.5
mA
Power Dissipation - Output LOW
145
mW
Output LOW Voltage
NOTES:
1.
2.
3.
Rating applies for ±15 V supplies. For other supply voltages the rating is within 2 V of either supply.
Rating applies to ambient temperatures up to 70°C. Above 70°C ambient derate linearly at 6.3 mW/C for metal can, 8.3 mW/C for DIP.
Pin numbers refer to metal can package.
4-31
•
FAIRCHILD • JLA734
TYPICAL PERFORMANCE CURVES FOR f.lA734 AND f.lA734C (Note 2)
UN·NULLED INPUT OFFSET
VOLTAGE AS A FUNCTION
OF AMBIENT
TEMPERATURE
TRANSFER
CHARACTERISTICS
8.0
0
VS"±15V
PIN 8 TlEO TO +15V
RL ·l.5kQTlEDTO+5V
6
INVERTING INPUT
\ /
I\1/
2.0
-400
-3OCI
-200
-100
0
"'-
-
100
,
~R5
I--
o.6
300
I
"-
4-"
-+-r-
,--,
~
L,
.~---
"\. \
INpUT BIAS CURRENT AS A
FUNCTION OF DIFFER·
ENTIAL INPUT VOLTAGE
+ r
1
I
AMBIENT TEMPERATURE
I
I
\
v..;..
I
.~
-(jJ
400
SOO
~
I
INPUT BIAS CURRENT AS A
FUNCTION OF AMBIENT
TEMPERATURE
I :!:5V<:' Vs ~ ±l5V
-+-
:11
200
VS· dSV
VO·l.4V
INHIAL OfFSET VCl.TAGl< I IlV
~
I
INPUT VOLTAGE -IlV
60
j
"- ~lOOk\1
1
NOO-INVERTING
lNPUf-
"-
V
o
1
I
I
4
,-\
J. .l J.
500
I
I
8
0.0
4.0
INPUT OFFSET VOLTAGE
CHANGE AS A FUNCTION OF
AMBIENT TEMPERATURENULLED TO ZERO AT 2SoC
--,.-
1Of\-+--+-++-+-+--+--j-H
H+--+-++-+-+--+--j-H
8.0
6.0 f-+\:+-++-+--t--t~r--t--t
~
IS
~
~--
-+-
---- - - -
10
I
-
-60
}l
--
I
I
100
1411
1
-10
1.0
I-+-+-++""-I5V
I
115
-00
AMBI£NTTEMPERAIURE
~
t15V
RL
~
1.5QTIED TO +5V
--
I
100.
--+- J
601
I"
1
"-
f- - -
I
.-
'::- r----
r-- : - -' - - - -.~
~
1
AMBIENTHMPERAIURE - °C
VS·±l5V
100
-./
f',.
f.-
+-, r- r-,5
"
"I
SUPPLYVOLTAGE-¥
'"
0.5
./
L ..l-..r
I~ (PIN 8 m:o TO +15VI
I
2.5
I.,
I
I I
f.-"" r--
I
"
1411
I
VOUTlOW
4.'
1
I
60
5.5
~
-
POSITIVE AND NEGATIVE
SUPPLY CURRENTS AS A
FUNCTION OF AMBIENT
TEMPERATURE
I
"1"'-
i
"'-
10
RL'1.5kQTlEDTO+5V
I
tl5V
SINK CURRENT - rnA
3'C
TA
101
l.
TA ~ 25°C
VIN) IOmV
140
VOL TAGE GAIN AS A
FUNCTION OF SUPPLY
VOLTAGE
1
81"
100
vs
100
AMBIENTTEMPERATURE-OC
VOLTAGE GAIN ASA
FUNCTION OF AMBIENT
TEMPERATURE
v5
00
.~
_oc
r::: ~gOPEN
./
---- r-- r--
f
V r::: V
f--
I
.vr
1;(PIN80PENJ
1
I
I; I I
1
1
-00
100
AMBIENTTEMPERATURE-"r.
4-32
140
FAIRCHILD • p.A734
TYPICAL PERFORMANCE CURVES FOR }JA734 AND }JA734C (Note 2)
RESPONSE TIME FOR
VARIOUS INPUT
OVERDRIVES
6_;;'_80P"
INPUT OFFSET VOLTAGE
DRIFT AS A FUNCTION
OF TIME
RESPONSE TIME FOR
VARIOUS INPUT
OVERDRIVES
-+r-
:~ -~"v
t--
2~ .Azmv
romV
IO'mV
~5mV
1
10
~
'II!
f-/¥-+-J-T-+--+--+-+-+--t---1
-50
OoLI/-L_~~~I~~~L-~~-L~~~~I~
~-IOO
160
lro
""
TlME-ns
HOURS
RESPONSE TIME FOR
VARIOUS INPUT
OVERDRIVES
>
J
PIN8TiEOTO+15V
Rl =lOkTlEOTD+15Y--+
I, ,·C
RESPONSE TIME FOR
VARIOUS INPUT
OVERDRIVES
_ro~v:',/
Ii -~·C
\\ \
i 'miv _
ioI
v~
2Omv---;----.
IOmv+--,;\I\-
~ -'00
-50
~
80
160
240
g~
50
~
0
f--
-'0
~
160
240
320
g
~~ ;5~~QTIEOTOtSV \1
4.0
=
~
Vs
1.0
TIME FROM POWER APPLICATION - SECONDS
RESPONSE TIME FOR
VARIOUS INPUT
OVERDRIVES
JOO
;;c 115J
I
I
!
r---
r---
-t---
/
-
PIN 8 TIED TO +15V
RL = I.SkQ TIED TO +5V
~ 100
TA-25°C
t---H---t--+
I
ao
lro
140
'60
~
TIME-ns
Iv,
VS=±15V
RS
-
-----t-I -!
---
=l--::: f=-
100
2~
320
0
40
400
OFFSET NULL CIRCUIT (NOTE 2)
'00
INITIAL OffSET VOLTAGE
< 1 ~V
ao
TlMEfROMHEATAPPLICATIOP-l- SECONDS
AC TEST CIRCUIT (NOTE 2)
+--
-
,
'00
80
,J--
VO'1.4V~_
50
TIME-ns
COMMON MODE REJECTION
RATIO AS A FUNCTION OF
AMBIENT TEMPERATURE
I
/
r---H---t--t--t--+-+-+--+-++-i
~ 0
I I I
~
-'0
-'00
0
~V
THERMAL RESPONSE OF
INPUT OFFSET VOLTAGE
TO STEP CHANGE OF CASE
TEMPERATURE
±ISV
~
~
11
TIME -IlS
H---t--:';!-O
m--:'+-i:::--Ht-I!J'-j--;/-t----t-;-±-H
2Omv-i--:
~
g
, I I
rlTr OFi sET rUY E<
400
1't- -1--
PIN8TIEDTO+l5V
Vs t15V
Ps 500
VO=1.4V- f-
10 kll TIE 0 TO +ISV
~6_0Pll~~~
V-I-/I
«:
-- -
V
I I
TIME -os
RESPONSE TIME FOR
VARIOUS INPUT
OVERDRIVES
f"'-
PIN 8 TIED TO +\5V
RL
80
320
I~
±IW
I
t: 100
~
•
1mV
' mV
I
I\-
--~
10
I
/
II
VS·±15V
8
STABILIZATION TIME OF
INPUT OFFSET VOL TAGE
FROM POWER TURN-ON
:
Ii
~
I
80
-t--- r--- 1--
,
I
_
mv
_HN·
I~ .1100 k;
:±IOY,_
0
-60
100
VIN
AMBIENTHMPERATURE·OC
4-33
~
-100 mV, 100 kHz
•
FAIRCHILD • IJ-A734
TYPICAL APPLICATIONS (Note 2)
STROBE CIRCUITRY
ALTERNATE STROBE CIRCUITRY
LEVEL DETECTOR WITH HYSTERESIS
VOUT
VO UT
i
"11f:~~"
2V ___
>'--.----<:JVOUT
I
V (MIN)
VREF
RS
* 1/2 9944
~ R, R2
FOR MINIMUM OFFSET
R, + R2
V HYS =
HIGH POWER OUTPUT CIRCUITS
A, {V OMAX - VOMtNl
PRECISION DUAL LIMIT GO-NO GO TESTER
>'----~r__OVOUT·
VOUT
FREE RUNNING OSCILLATOR
VOLTAGE CONTROLLED OSCILLATOR
• Adjusts ..;;.
PULSE WIDTH DISCRIMINATOR
FREQUENCY DIVIDER & STAIRCASE GENERATOR
IVREFI = 2VO + N [3.5T + 2VO
VOUT Pulse Appears
T In Seconds
Vo for FJT,lOQO
~
O.31V
Whenever T>
4-34
AI ~ 1~~
FAIRCHILD • JLA734
TYPICAL APPLICATIONS (Note 2)
I
12-BIT A/D CONVERTER
NO OF BITS
R VALUE
8
12.5kU
10
12
25kn
50kH
200kn
12-BIT A/D CONVERTER
__~_J
4-35
UA760
HIGH SPEED DIFFERENTIAL COMPARATOR
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The pA760 is a Differential Voltage Comparator offering considerable
speed improvement over the ,uA710 family and operation from symmetric supplies of from ±4.5 V to
±6.5 V. The MA76D can be used in high speed analog to digital conversion systems and as a zero
crossil19 detector in disc fi Ie and tape amplifiers. The .uA760 output features balanced rise and fall times
for minimum skew and close matching between the complementary outputs. The outputs are TTL
compatible with a minimum sink capability of two gate loads.
•
•
•
•
•
CONNECTION DIAGRAMS
8-PIN METAL CAN
(TOP VIEW)
PACKAGE OUTLINE 5S
PACKAGE CODE H
qUARANTEED HIGH SPEED - 25 ns MAX
GUARANTEED DELAY MATCHING ON BOTH OUTPUTS
COMPLEMENTARY TTL COMPATIBLE OUTPUTS
HIGH SENSITIVITY
USES STANDARD SUPPLY VOLTAGES
V+
1P2
ABSOLUTE MAXIMUM RATINGb
Positive Supply Voltage
Negative Supply Voltage
+8 V
-8 V
10mA
±5 V
V+;;, VIN;;' V-
Peak Output Current
Differential Input Voltage
Input Voltage
vNOTE: Pin 4 connected to case.
Internal Power Dissipation (Note 1)
500mW
670mW
Metal Can
DIP
Operating Temperature Range
_55°C to l25'C
O°C to 70°C
Military (pA760)
Commercial (pA760C)
ORDER INFORMATION
PART NO.
TYPE
pA760
pA760HM
pA760C
pA760HC
Storage Temperature Range
Metal Can and DIP
14-PIN DIP
(TOP VIEW)
EQUIVALENT CIRCUIT
PACKAGE OUTLINE 6A
PACKAGE CODE D
14
NC
NC
NC
NC
V+
1P2
1P1
0P2
v-
GND
NC
NC
ORDER INFORMATION
PART NO.
TYPE
pA760DM
pA760
pA760C
,uA760DC
Notes on following page.
4-36
FAIRCHILD • iJ-A760
f..l A760
ELECTRICALCHARACTERISTICS:VS
= ±4.5 V
CHARACTERISTICS
Input Offset Voltage
= -55°C
to ±6.5 V. TA
to +125°C. TA
TEST CONDITIONS
= 25°C
for typical figures unless otherwise specified.
MIN
RS <; 200[1
TYP
MAX
UNITS
1.0
6.0
mV
Input Offset Current
0.5
7.5
gA
Input Bias Current
8.0
60
gA
Output Resistance (either output)
Response Time
VOUT
= VOH
[1
100
Note 2. T A
= 25°C
Note 3, T A
= 25'C
18
30
ns
25
ns
ns
16
Note 4
-
Response Time Difference between
Outputs
(tpd of +VIN11- (tpd of - VIN21
Note 2, T A
= 25'C
5.0
ns
(tpd of +VIN21 - (tpd of - VINll
Note 2, T A
= 25'C
5.0
ns
(tpd of +VINll - (tpd of +VIN21
Note 2, TA
= 25°C
7.5
ns
(tpd of -VINll - (tpd of -VIN21
Note 2, T A
=
7.5
ns
Input Resistance
f
=
I nput Capacitance
f
= 1 MHz
Average Temperature Coefficient
RS
25°C
1 MHz
= 50[1, T A
=
12
krl
8.0
pF
3.0
gvtc
= +125°C
2.0
nAtC
_55° C
7.0
nAtC
±4.5
V
±5.0
V
2.4
3.2
V
2.4
3.0
-55'C to T A
=
+125°C
of Input Offset Voltage
Average Temperature Coefficient
of Input Offset Current
Input Voltage Range
TA
=
TA
= 25° C to T A
25°C to T A
Vs
= ±6.5V
=
±4.0
Differential I nput Voltage Range
0<; lOUT <; 5.0 mA
Output HIGH Voltage (either output I
Vs
= ±5.0V
= 80 gA,
lOUT
Output LOW Voltage (either outputl
ISINK
Positive Supply Current
Vs
= ±6.5V
Negative Supply Current
Vs
=
=
Vs
=
±4.5V
3.2 mA
±6.5V
4-37
V
0.25
0.4
V
18
32
mA
9.0
16
mA
•
FAIRCHILD • f-LA760
pA760C
ELECTRICALCHARACTERISTICS:VS
= ±4.5
V to ±6.5
CHARACTERISTICS
v,
TA = -55°C to +125°C, TA
= 25°C
MIN
TEST CONDITIONS
Input Offset Voltage
for typical figures unless otherwise specified.
RS "- 20011
Input Offset Current
Input Bias Current
Output Resistance (either output)
TVP
1.0
6.0
mV
7.5
MA
8.0
60
MA
VOUT = VOH
100
Note 2, T A = 25°C
18
Note 4
UNITS
0.5
Note 3, T A = 25°C
Response Time
MAX
11
30
ns
25
ns
16
ns
Response Time Difference between
Outputs
(tpd of +VIN1) - (tpd of - VIN2)
Note 2, T A = 25°C
5.0
ns
(tpd of +VIN2) - (tpd of - VIN1)
Note 2, T A = 2SoC
5.0
ns
(tpd of +VIN1) - (tpd of +VIN2)
Note 2, T A = 25°C
10
ns
(tpd of -VIN1) - (tpd of -VIN2)
Note 2, T A = 25°C
10
ns
f = 1 MHz
I nput Resistance
12
kl1
I nput Capacitance
f = 1 MHz
8.0
pF
Average Temperature Coefficient
RS = 5011, T A = 0° C to T A = +70° C
3.0
MVtC
TA =25°Cto TA = +70°C
5.0
nAtC
T A = 25° C to T A = 0° C
10
nA/oC
±4.5
V
-~ ~-
of Input Offset Voltage
Average Temperature Coefficient
of Input Offset Current
-~
I nput Voltage Range
~-----
Vs = ±6.5V
±4.0
±5.0
Differential Input Voltage Range
--
0"- lOUT "- 5.0 mA
Output HIGH Voltage (either output)
Output LOW Voltage (either output)
Vs = ±5.0V
2.4
3.2
V
lOUT = 80 MA, Vs = ±4.5V
2.5
3.0
V
0.25
ISINK = 3.2 mA
..
Positive Supply Current
~
V
0.4
_.
-
Vs = ±6.5V
18
34
mA
Vs = ±6.5V
9.0
16
mA
~~----~~~~-~.~~~-
Negative Supply Current
NOTES
1.
2.
3.
4.
Rating applies
for the DIP.
Response time
Response time
Response time
threshold.
to ambient temperatures up to 70o e. Above 70D
e
ambient rlerate. linearly at 6.3 mW/oC for metal can and 8.3 mW/C
measured from the 50% point of a 30 mVp-p 10 MHz sinusoidal input to the 50% point of the output.
measured from the 50% point of a 2 Vp-p 10 MHz sinusoidal input to the 50% point of the output.
measured from the start of a 100 m V input step with 5 m V overdrive to the time when the output crosses the logic
4-38
FAIRCHILD • IJ-A760
TYPICAL PERFORMANCE CURVES FOR pA760 AND pA760C
RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVES
RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVES
I v,.'"v
~ ,F=~~2O=m=v~r:I~J~-';~~m."v-+--+-~
>
4
RESPONSE TIME AS A
FUNCTION OF INPUT VOLTAGE
0
;~M~~.!~":
TA =2S'C
~ 21-~-i--~~~~"~m~v~--T-~
~ 11-~-4---+-~~~+--+--T-~
0
c:b
o 0~~~_ _'io~mv~~~~=f==f=9
~
~
1001-+-1-+-+-+--+-+--1
~r-
~~~-r-r~~~~
,
0
30
:--
0
SO
~
""'" .
35
W
6
6
"
INPUT VOLTAGE - mV peek to peak
RESPONSE TIME AS A
FUNCTION OF INPUT VOLTAGE
I-+-i-H-f-v,'. ,I)
1
1
VOLTAGE TRANSFER
CHARACTERISTIC
VOL TAGE TRANSFER
CHARACTERISTIC
1
lOMHz SINE WAVE INPUTS
= 2S"C
I-+++-+--t- TA
...
....
Ib."+-_TA- 2S"C
.-fj
.........
INPUT VOLTAG - mV pe-_--"-0 OUTPUT
INPUT
31
I
+
LOGIC:tC>~
LOGIC
REFERENCE
I
________ / /
"
••
71
I
IL ___________________________________
6
HOLD
CAPACITOR
5-3
~
PART NO.
p.AF198HM
p.AF298HC
p.AF398HC
jLA0801 (OAC-08) SERIES
8-BIT HIGH SPEED MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION -ThepAOB01 A. pAOB01 H,pAOB01 ,pAOB01 E andpAOB01 C
are B-bit multiplying Digital-to-Analog Converters constructed using the Fairchild Planar" epitaxial process. Advanced circuit design achieves very high speed performance
with outstanding applications capability and low cost. The pAOB01A and pAOB01 are
specified for the military temperature range (-55°C to +125°C) and the pAOB01 H,
pAOB01 E and pAOB01 C are specified for OoC to + 70°C operation.
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 6B 98 4L
PACKAGE CODE D P F
The pAOB01 series are pin-for-pin replacements of the DAC-OB series.
• FAST SETTLING TIME TO 1/2 LSB - 85 ns
• FULL SCALE CURRENT PREMATCHED TO ± 1 LSB
• DIRECT INTERFACE TO TTL, CMOS, ECL, HTl, PMOS, DTl
• . LINEARITY TO ± 0.1 % MAX OVER TEMPERATURE RANGE
• HIGH OUTPUT COMPLIANCE: -10 V TO +18 V
• TRUE AND COMPLEMENTED OUTPUTS
• WIDE RANGE MULTIPLYING CAPABILITY
• LOW FS CURRENT DRIFT:I+10 ppm;oC TYPICALLY
• WIDE POWER SUPPLY RANGE: ±4.5 V TO ± 18 V
• LOW POWER CONSUMPTION: 33 mW @ ±5 V
• EXTERNAL COMPENSATION FOR MAX BANDWIDTH
•
VLC
VREFH
vcc-
VREF(+)
lOUT
(MSB)
CaMP
lOUT
Vcc+
B1
BB
B2
B7
(LSB)
B6
85
LOW COST
ABSOLUTE MAXIMUM RATINGS
VCC+ to VCCLogic Inputs
VLC
Reference Inputs (V14, V15)
Reference Input Differential Voltage (V14 to V15)
Reference Input Current (114)
Power Dissipation
Derate above 90°C (Hermetic DIP)
Derate above BOoC (Flatpak)
Operating Temperature Range
pAOB01, pAOB01 A
pAOB01H,pAOB01E,pAOB01C
Storage Temperature Range
Pin Temperature
Hermetic DIP, Flatpak (Soldering, 60 s)
Molded DIP (Soldering, lOs)
36 V
VCC- to VCC- plus 36 V
VCC- to VCC+
VCC- to VCC+
±lBV
5.0 mA
500mW
B.3 mW;oC
7.1 mW;oC
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
ORDER INFORMATION
TYPE
pA0801A
/lA0801A
/lA0801
/lA0801
/lA0801H
/lA0801H
/lA0801E
/lA0801E
/lA0801C
/lA0801C
PART NO.
/lA0801AFM
/lA0801ADM
/lA0801FM
/lA0801DM
/lA0801HDC
/lA0801HPC
/lA0801EDC
/lA0801EPC
/lAO~OlCDC
/lA0801CPC
EQUIVALENT CIRCUIT AND PIN
CONNECTION DIAGRAM
"'Planar is a patented Fairchild process.
5-4
FAIRCHILD • J.tA0801 SERIES
ELECTRICAL CHARACTERISTICS: TA = 25°C
These specifications apply for Vee = ±15 V, IREF = 2.0 mA, TA = --55°C to +125°C for !lA0801A,!lA0801, TA = O°C to 70°C for !lA0801H,
!lA0801 E, !lA0801 C. Output characteristics refer to both lOUT and lOUT.
SYMBOL
CHARACTERISTICS
CONDITIONS
MIN
TYP
MAX
8
8
8
bits
Monotonicity
8
8
8
bits
±0.1
!lA0801 A, !lA0801 H
Non-linearity
!lA0801, !lA0801 E
±0.19
!lA0801C
±0.39
Is
Settling Time
To ± 1;2 LSB, all bits
switched ON or OFF
TA = 25°C
tPLH,tpHL
Propagation Delay
TA = 25°C
TCI FS
Full Scale Temperature
Coefficient
Voe
Output Voltage Compliance
IFs4
Full Scale Current
IFSS
Izs
IFSR
Full Scale Symmetry
VREF = 10.000 V,
R14, R15 = 5.000 kD.
TA = 25°C
135
!lA0801 E, !lA0801 C
85
150
Each bit
35
60
ns
All bits switched
35
60
ns
±10
±50
ppm/"C
+18
V
mA
1.984
1.992
2.000
!lA0801E,
!lA0801, !lA0801C
1.940
1.990
2.040
!lA0801 A, !lA0801 H
±0.5
±4.0
!lA0801, !lA0801 E
±1.0
±8.0
!lA0801C
±2.0
±16
!lA0801 A, !lA0801 H
0.1
1.0
!lA0801, !lA0801 E
0.2
2.0
!lA0801C
0.2
4.0
2.0
2.1
mA
0
2.0
4.2
mA
0.8
V
V
-2.0
-10
!lA
0.002
10
!lA
+18
V
VLe = 0 V
Input HIGH Current
VIN = 2.0 V to 18 V
VIS
Logic I nput Swing
Vee-
Logic Threshold Range
dl/dt
Reference Input Slew Rate
PSSIFs+
Power Supply Sensitivity
VLe = 0 V
Vee
= -15
=
2.0
VIN = -10 V to +0.8 V
V
-10
±115 V
-10
4.0
Vee+ = 4.5 V to 18 V
Vee- = -4.5 V to -18 V
IREF = 1.0 mA
1+
1-
Vee = ±5.0 V, IREF
= 1.0 mA
Vee+ = +5.0 V, Vee-
= -15
V, IREF
Vee =±15 V,IREF =2.0 mA
1+
1Power Dissipation
+13.5
-1.0
PSSIFS-
Power Supply Current
!lA
0
Input LOW Current
Reference Bias Current
!lA
Vee- = --5.0 V
hH
115
ns
Vee- = -7.0 V to -18 V
hL
VTHR
-10
!lA0801A,
!lA0801H,
IFS4 - IFs2
Input LOW Voltage
Input HIGH Voltage
PD
85
Zero Scale Current
Output Current Range
%FS
!lA0801A,
!lA0801, !lA0801 A
Full scale current change < V2 LSB,
ROUT> 20 mil
VIL
VIH
1+
1-
UNITS
Resolution
Vee =+5.0V,IREF =1.0 mA
Vee+ - +5.0V, Vee- - - 15 V,
IREF = 2.0 mA
Vee -±15 V, IREF - 2.0 mA
5-5
= 2.0 mA
-3.0
8.0
V
!lA
mA/!ls
0.0003
0.01
%1%
0.002
0.01
%/%
2.3
-4.3
3.8
--5.8
mA
mA
2.4
-£.4
3.8
-7.8
mA
mA
2.5
-£.5
3.8
-7.8
mA
mA
33
108
48
136
mW
mW
135
174
mW
•
FAIRCHILD • jLA0801 SERIES
TYPICAL PERFORMANCE CURVES
..
SMALL SIGNAL
1--1-1--++ VIN = 50 mVpk-pk
CENTERED AT +200 mV
1A = TMIN TO TMAX
ALL BITS "HIGH"
0
VIT
~,
r
0
~
o
3. 2
0
f-
U
REFERENCE AMP
COMMON MODE RANGE
REFERENCE INPUT
FREQUENCY RESPONSE
FULL SCALE CURRENT AS A
FUNCTION OF REFERENCE CURRENT
2. 0
/
V
~MITJJR
VCC-
=0-15 V
Vne-n-
oV
'.0
2.0
-2
~
CE
_6I---4
:;:N:.;T:;:'R:;:':;:O"A-,-T-,,+.>".0,-,v,-+\44+--1
T'\
II
R14
=
I
~
U
R15 = 1.0 kO
o
1\
VR15=OV,CC=15pF
o.
fREt ==
,j5V
I
2·r
rnA
I I
'REF
I
8
1.0mA
I I
•
'REF
0
-14 -10
FREQUENCY - MHz
REFERENCE CURRENT - rnA
II
I
•. 2
~
Rl;;;; 500 n
Vcc- == -5.0 V,
1. 6
1
vcc le
~
Eo.
T
I
-1. v
Ie
2. 0
-140·L.'--="0.-2..J.....L0.1..•_...J
•.LO-2.J..0-'-"-5.L.0-..J.0
'.0
4.0
ffi
\
ALL BITS "ON"
3.0
,
. I ~ 1\
~ ~:~~~~::~~~rl-.l}+---I
-10
I
I
V
~
~
~
f-
VCC
~ 2. 4
[/\
o
I'UMITFOR
V
•. 0
V
m
1A '" TMIN TO TMAX .
ALL BITS "ON"
2. 8
-6
-2 0 2
0.2 rnA
10
14
18
V15. REFERENCE COMMON MODE VOLTAGE - V
NOTE: POSITIVe COMMON MODE RANGE IS ALWAYS (VCC-) -1.5 V
OUTPUT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE
(OUTPUT VOLTAGE COMPLIANCE)
VTH - VLC
AS A FUNCTION OF
TEMPERATURE
>
I
2.0
3.2
..
2.8
6
.......
2.4
!"-....
1.2
~,
,
~
r--..
i
~ 0.8
U
S
~
Vec-
l~~e! -~.o V
50
100
I
'.6
0.8
'REF -1.0rnA
I
I
IREF" 0.2 rnA
-'0
-6
2 0 2
.0
BIT TRANSFER
CHARACTERISTICS
20
'.4 r--r-,--,--,--,--,--,--,
'6
'.2
~ER~ISsl'BLEI ouJpUTIVOL~AG~_
-
RANGE FOR Vcc- = 15 V
'REF";;: 2.0 rnA
,
POWER SUPPLY CURRENT
AS A FUNCTION OF VCC+
ALL BITS "HIGH' OR "LOW"
f-+-I-+-t-+--t-+---i
o.
'0
(FOR OTHER Vee
SEE FIGURE 12)
4.0
I
OR IREF.
0.8
0.470.2
50
.00
150
~
02
0
-
~~
~-
0
~
4.0
~~~-4-+-+-+-+~~
20
'2
NOTE;
LOGIC INPUT VOLTAGE - V
81 through B8 have identical transfer characteristics.
Bits are fully switched, with less than 1/2 LSB error. At
less than ±1 00 mV from actual threshold, these switch·
ing points are guaranteed to lie between 0.8 and 2.0 V
over the operating temperature range IVle = 0.0 V)
TEMPERATURE - °C
8.0
0
ALL BITS "HIGH" OR "LOW"
I
U
i
ffi
6. 0
II I
IRI"
4. 0
e
ALL BITS "HIGH" OR "lOW"
~ 7. 0
1-
~
12 . 0 Im A
I I I
IRi"
IREF
~
0
U
i
-1 •. 0 Im A
~
0.2 rnA
I I I
8.0
~
H
I II
III
0
3. 0
Vce+= 115V
2.
0
0
.2
.6
0
20
-50
Vec- - NEGATIVE POWER SUPPLY - Vdc
1-
IREF = 2.0 rnA
~
III
4.0
Vec- = -15 V
6. 0
~ 5. 0
1-
I
2. 0
Vee+ - POSITIVE POWER SUPPLY - Vdc
POWER SUPPLY CURRENT
AS A FUNCTION OF
TEMPERATURE
POWER SUPPLY CURRENT
AS A FUNCTION OF VCC-
~
2,0
04
05
f]
4.0
4.0 1-+--+--1--1--1-+--+--1--1--1
~
83
" - - I-U",
0
-'2
--12
-50
>
>
0
-8.0
1-
,
>
S
~
E
U
U 0.6
-4.0
~
1"01-+--+--1--1--1_+--+--1--1--1
~
8.0
.8
8.0
IREF --, 2.0 rnA
'2
.4
OUTPUT VOLTAGE - V
TEMPERATURE - °e
OUTPUT VOLTAGE COMPLIANCE
AS A FUNCTION OF TEMPERATURE
+15 V
I
'.2
0
-'4
150
1
2., rnA
IREi -
0.'
50
I-
vce -
=
2.0
0
0.4
I
1A - TMIN TO TMAX
ALL BITS "ON"
I II
I II
H
100
TEMPERATURE - °e
5-6
150
FAIRCHILD • ILA0801 SERIES
TEST CIRCUITS
BASIC POSITIVE REFERENCE OPERATION
-
RECOMMENDED FULL SCALE ADJUSTMENT CIRCUIT
LSB
MSB
B1 B2B3B4B5B687B8
LOWT.C.
IREF
+VREF
4.5 k
VREF(+)
-
10
RREF
(R14)
IREF(+) = 2 rnA
R1.
APPROX.
5k
0.1 pF
IFS .=
~~~~F
pADeDl
~-----'-~-i-'-,V_----i 15
VREF(-)
h
1-
~::
X
-=
10 + iO = IFS FOR ALL
LOGIC STATES
Vcc-
Vcc+
•
FOR FIXED REFERENCE. TTL
OPERATION. TYPICAL VALUES ARE:
VREF = +10.000 V
RREF = 5.000 k
R15
= RREF
Cc = O.01IJF
VLe ~ 0 v (GROUND)
Fig. 1
Fig. 2
BASIC NEGATIVE REFERENCE OPERATION
BASIC UNIPOLAR NEGATIVE OPERATION
MSB
LSB
81 82 83 84 86 86 87 B8
EO
RREF
...--'lM,--I14
IREF
""2.000 rnA
pA0801
15
-VREF
.255
IFS ~ RREF X
1m
B1 B2 B3 B4 B5 B6 B7 B8 lornA lornA
NOTE'
RREF sets IF$; R15 is for
bias current cancellation.
Full Scale
Full Scale - lSB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1.992
1.984
Half Scale + LSB
Half Scale
Half Scale - LSB
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
1
1.008
1.000
.992
+ LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
.008
.000
Zero Scale
Zero Scale
Fig. 3
£0
.000 -9.960
.008 -9.920
.000
-.040
.984 -5,040 -4.920
.992 -5.000 -4.960
1.000 -4.960 -5.000
1.984
1.992
-.040 -9.920
.000 -9.960
Fig. 4
HIGH NOISE IMMUNITY CURRENT
TO VOLTAGE CONVERSION
B1 B2 B3 B4 B5 B6 B7 B8
B1 B2 B3 B4 B5 B6 87 B8
Pos Full Scale
Pos Full Scale - LSB
5k
(+) Zero Scale
(-) Zero Scale
5k
+10
EO
vo--W.......-o--l
Neg Full Scale
Neg Full Scale
•
•
•
•
•
5k
+ LSB
EO
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
+9.920
+9.840
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
+0.040
-0.040
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
-9.840
-9.920
Provides isolation from ground loops
Symmetrical ±10 V output
Useful within systems between boards
True complementary/differential current transmission
High speed analog signal transmission
Fig. 5
+15V -15V
BASIC BIPOLAR OUTPUT OPERATION
B1 B2 B3 84 B5 B6 B7 B8
+10.000 V
10.000 kQ
(04
IREF(+ )
~2.00
~
EO
14
pA0801
10 2
Eo
10.000 kn
Fig. 6
5-7
EO
£0
Pas Full Scale
Pas Full Scale - LSB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
-9.920 +10.000
-9.840 +9.920
Zero Scale + LSB
Zero Scale
Zero Scale - LSB
1
1
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
1
0
1
-0.080
0.000
+0.080
+0.160
+0.080
1
Neg Full Scale + LSB
Neg Full Scale
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
+9.920
+10.000
-9.840
-9.920
0.000
•
FAIRCHILD • tLA0801 SERIES
TEST CIRCUITS (Cont'd)
POSITIVE LOW IMPEDANCE OUTPUT OPERATION
NEGATIVE LOW IMPEDANCE OUTPUT OPERATION
EO
41----1
pA0801
-10
41----.-;
EO
>-+--0
_10
o TO +IFS
pA0801
Rl
RL
IFS '"
For complementary output (operation as negative logic DAe),
connect inverting input of Op-Amp to iO (Pin 2); connect 10
(Pin 4) to ground.
~::
IREF
For complementary output {operation as a negative logic DACI.
connect non-inverting input of Op-Amp to
(Pin 4) to ground.
Fig. 7
iO (Pin 2); connect 10
Fig. 8
PULSED REFERENCE OPERATION
+VREF
)'
I
>
~RREF
1
RIN
ovJl..
TYPICAL VALUES,
RIN ~ 5 k
I
OPTIONAL RESISTOR
FOR OFFSET INPUTS
REO
=200
Rp
lOUT
pA0801
+VIN~10V
NO CAP
lOUT
Fig. 9
ACCOMMODATING BIPOLAR REFERENCES
+VREF
RREF
+VREFcr~~r----114
tJA0801
-'4:::r- ~ 5 (OPTIONAL)
IlA0801
I~~~ri~~~~ - -
15
L..._ _ _ _ _ _ _ _..... RREF = R15
+VREF must be above peak positive swing of VIN
IREF
~
peak negative swing of liN
Fig. lOa
Fig. lOb
5-8
FAIRCHILD • JLA0801 SERIES
TEST CIRCUITS (Cont'd)
INTERFACING WITH VARIOUS LOGIC FAMILIES
I
I
TTL,OTL
VTH = +1.4 V
I
I
I
I
I
JlA0801
I.
I
VTH=VlC+ 1 .4V
+15 V CMOS. HTL HNIL
VTH"" t7.5 V
+15 V
+12VTO
PMOS
VTH = 0 V
+15 V
1N4148
9.1 k
10k
VLe
VLe
6.2 V
ZENER
6.2 k
10 k
I
I
- - - - -:-5-;e-;;-o; - - -
-5 V TO -10 V
I
+--------I
I
I
I
I
VTH = +2.5 V
tJA 0 801
I
NOTE:
VTH = -1.29 V
+10 V CMOS
VTH" +5.0 V
•
+10 V
I
6.2 k
I
I
I
....-op--<> VLe
3.6 k
3.9 k
I
1N4148
~gG~giN~~~Eri~N~EEG~:16;c
T - 1. - 10 kEel - - - - - - - - - - -
I
I
1 k
-5.2 V
I
Fig. 11
SETTLING TIME MEASUREMENT
FOR TURN·ON, VL" 2.7 V
FOR TURN·OFF, VL ~ 0.7 V
+-_...._,
0.1 JiF
1 k
MINIMUM
JJ
Ol
. "F
CAPACITANCE
+.4V
~ov
fov
VOUT
1XPRO
>-....-t-'w.-+--+
RREF
+VREF O-.....W'.--I
-15V
TO O.U.T.
R15
O. 1J1F
-.4 V
r
-15V
+15 V
Fig. 12
5-9
JLA0802 (MC1508/1408) SERIES
a-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTER
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The pA0802, pA0802H, pA0802A, pA08028, and
pA0802C are monolithic 8-bit multiplying Digital-to-Analog Converters constructed
using the Fairchild Planar" epitaxial process. It is designed for use where the output
current is a linear product of an 8-bit digital word and an analog input voltage. The
pA0802 is specified for the military temperature range (-55°C to +125°C) and the
pA0802H, pA0802A, pA08028 and pA0802C are specified for O°C to 70°C operation.
CONNECTION DIAGRAM
l6·PIN
(TOPVIEWj
PACKAGE OUTLINES 68 98 4L
PACKAGE CODES 0 P F
The pA0802 series are pin-for-pin replacements of the MC1508/1408 devices.
16
RANGE 1
CONTROL 2
•
•
•
•
•
•
•
•
•
•
•
RELATIVE ACCURACY: ±0.1% ERROR MAXIMUM ILA0802H
RELATIVE ACCURACY: ±0.19% ERROR MAXIMUM ILA0802, ILA0802A
7 AND a-BIT ACCURACY AVAILABLE ILA0802B.ILA0802C
FAST SETTLING TIME TO 1/2 LSB - 8& ns
NON·INVERTING DIGITAL INPUTS ARE TTL AND CMOS COMPATIBLE
OUTPUT VOLTAGE SWING: +0.& V TO -&.0 V
HIGH·SPEED MULTIPLYING INPUT SLEW RATE 4.0 mAilLs
STANDARD SUPPLY VOLTAGES: +&.0 V AND -&.0 V TO -1& V
LOW FS CURRENT DRIFT: +10 PPMfOC TYPICALLY
LOW POWER CONSUMPTION: 33 mW @ ±& V
LOW COST
ABSOLUTE MAXIMUM RATINGS: TA
=
Vcc-
4
•
•
•
•
•
A·to-D Converters
2 1/2 Digit Panel Meters and DVM's
Waveform Synthesis
Sample and Hold
Peak Detector
Programmable Gain and Attenuation
•
•
•
•
•
•
•
•
(LSBI
A1
A2
A6
A4
5.5 Vdc
-16.5 Vdc
+5.5 Vdc
0.5 Vdc to -5.2 Vdc
5.0mA
5.5 Vdc, -16.5 Vdc
'---'-
AS
ORDER INFORMATION
TYPE
/lA0802
/lA0802
/lA0802H
/lA0802H
/lA0802A
/lA0802A
/lAOa02B
/lA0802B
/lA0802C
/lA0802C
PART NO.
/lA0802FM
/lA0802DM
/lA0802HDC
/lA0802HPC
/lA0802ADC
/lA0802APC
/lA0802BDC
/lA0802BPC
/lA0802CDC
/lA0802CPC
ADDITIONAL ORDER INFORMATION
TYPICAL APPLICATIONS
• Tracking A~to·D Converters
• Successive Approximation
3
lOUT
(MSB)
+25°C unless otherwise noted
VCC+
VCCDigital Input Voltage (V5 to V12)
Applied Output Voltage
Reference Current (114)
Reference Amplifier Inputs (V14, V15)
Operating Temperature Range
pA0802
pA0802H,pA0802A,pA08028,pA0802C
Storage Temperature Range
Pin Temperatures
Hermetic DIP, Flatpack (Soldering, 60 s)
Molded DIP (Soldering, lOs)
COMP
GND
Audio Digitizing and Decoding
Programmable Power Supplies
Analog-Digital Multiplication
Digital-Digital Multiplication
Analog-Oigital Division
Digital Addition and Subtraction
Speech Compression and Expansion
Stepping Motor Drive
• CRT Character Gene",ation
• Planar i. a patented Fairchild proc•••.
5-10
TYPE
ILA0802H
ILA0802 (MC1508L-8)
ILA0802A (MC1408L-8)
ILA0802B (MC1408L-7)
ILA0802C (MC1408L-6)
TEMPERATURE
RANGE
RELATIVE
ACCURACY
O°C to +70°C
-55°C to +125°C
O°C to +70°C
O°C to +70°C
O°Cto +70°C
±0.1 %
±0.19 %
±0,19 %
±0.39 %
±O.78 %
FAIRCHILD LINEAR INTEGRATED CIRCUITS. J1A0802 SERIES
ELECTRICAL CHARACTERISTICS: VCC+ = +5.0 V, VCC- = - 15 V, V REF /R14 = 2.0 rnA, /LA0802 TA = -55°C to 125°C.
/LAOS02HIAIB/C, T A
= O°C to
70°C, unless otherwise noted. All digital inputs at high logic level.
SYMBOL
CHARACTER ISTICS
Er
Relative Accuracy (Error Relative to Full Scale 10
flA0802H
flA0802, flAOS02A
flAOS02B, See Note 1
flA0802C, See Note 1
3
Setting Time to Within 1/2 LSB
(includes tPLHI (TA = +25 'C) See Note 2
ts
FIGURE
= +25°C
4
-
85
135
4
-
30
100
-
±20
Propagation Delay Time TA
Digital Input Logic Levels (MSBI
High Level, Logic "1"
Low Level, Logic "0"
2
VIH
VIL
2
IIH
IlL
Digital Input Current (MSBI
High Level, VIH - 5.0 V
Low Level, VIL - 0.8 V
115
Reference Input Bias Current (Pin 151
2
lOR
Output Current Range
VCC = -5.0 V
VCC = -6.0 to -15 V
2
1000
-
-
0.8
mA
-
0.04
-0.8
-
-1.0
-5.0
flA
a
a
2.0
2.0
2.1
4.2
mA
1.9
1.99
2.1
mA
mA
a
4.0
flA
2
Output Current (All bits lowl
2
Va
Output Voltage Compliance
(E r <; 0.19: at TA = +25°CI
VCC- = -5 V
VCC- below -10 V
2
5
SR IREF
Reference Current Slew Rate
PSRR(-I
Output Current Power Supply Sensitivity
ICC+
ICC
Power Supply Current
(All bits lowl
2
VCCR+
VCCR-
Power Supply Voltage Range
(TA = +25°CI
2
Po
Power Dissipation
All bits low
VCC- = -5.0 V
VCC- = -15 V
All bits high
VCC- = -5.0 V
VCC- = -15 V
2
-
V
-
-
-
-
4.0
-
mA/fls
-
0.5
2.7
flA/V
+13.5
-7.5
+22
-13.0
mA
+5.0
-15
+5.5
-16.5
V
-
+4.5
-4.5
mW
-
-
5-11
-0.6,+0.5
-5.0,+0.5
-
-
NOTES:
1. All current switches are tested to guarantee at least 50% of rated output current.
2. All bits switched.
ns
PPMoC
a
-0.4
-
10(minl
ns
V
2.0
-
n
UNITS
±0.1
±0.19
±0.39
±0.7S
-
Output Full Scale Current Drift
=
MAX
-
tpLH,tPHL
Output Current
VREF = 2,000 V, R14
TYP
%
-
TCIO
10
MIN
105
190
170
305
90
160
-
I
FAIRCHILD LINEAR INTEGRATED CIRCUITS. IlA0802 SERIES
TYPICAL APPLICATIONS
J1A0802
EQUIVALENT CIRCUIT
A2
Al
A4
A3
A5
AS
A7
AS
RANGE
CONTROL
13
VCC+
REFERENCE
CURRENT
VAEF(-)
AMPLIFIER
15
16
COM PEN
Vcc-..--
NPN CURRENT SOURCE PAIR
Fig. 1
NOTATION DEFINITIONS TEST CIRCUIT
TYPICAL VALUES:
-
R14 = R15 = 1k
VREF -'-' +20 V
C = 15 pf
114
Al
7
A3
DIGITAL
INPUTS
A5
10
A7
AS
The resistor tied to pin 15 is to temperature compensate the
bias current and may not be necessary for all applications.
15
A15
I2
Al
10 = K
-=OUTPUT
12
A2
+ 4"" -""
A3
a
A4
== R14
and AN = " ' " if AN is at high level
AN = "0" if AN is at low level
AL
t
ICC-
Fig. 2
5-12
A5
A6
+ 16 + 32 + 64 +
VAEF
where K
Vo
11
~
Vl
VI and II apply to inputs A 1 thru AS
VREF(+J
A14
115
I1A0802
SERIES
A4
A6
-
14
A2
A7
128
+
~
I
256 \
FAIRCHILD LINEAR INTEGRATED CIRCUITS. pA0802 SERIES
TYPICAL APPLICATIONS (Cont'd)
RELATIVE ACCURACY TEST CIRCUIT
MSB
A1
A2
A3
12-81T
D-TO-A
CONVERTER
A5
(±O.O1%
A6 ERROR MAX)
A4
r--
-
o TO +10 V OUTPUT
--,
5k
A7
A8
A10
A9
lSB
A12
A1l
t.J
0 1 pF
-=lc
+
vr
950
R14
MSB
~~,
1
VREF = 2 V
100
50 k
I 1 1 1
14
13
ERROR
(1 V= 1 %)
•
-=-
5
6
7
8
8-BIT COUNTER
~
jJAOB02
SERIES
9
10
11
12
lSB
1k
C
kEt
311
VccFig. 3
TRANSIENT RESPONSE AND SETTLING TIME
2.4V
1.4 V
+2.0 Vdc
0.4
1.0 k
0.1
v
I==~f------------+~===
2.0V
~F
USE RL TO GND FOR
FOR SETTLING TIME
MEASUREMENT.
(ALL BiTS SWITCHED
lOW TO HIGH)
SETTLING TIME
FOR FIGURE 4
TURN OFF
MEASUREMENT
o~---+--~-+------+-----~-------
VOUT
o
TRANSIENT
RESPONSE
mV-l00
VccFig. 4
5-13
RL = 50 0
PIN 4 TO GNO
_ \.-t
PlH
FAIRCHILD LINEAR INTEGRATED CIRCUITS. pA0802 SERIES
TYPICAL APPLICATIONS (Cont'd)
NEGATIVE V REF
POSITIVE VREF
Vcc+
VCC+
R14
==
R15
R142' R15
,.
A1
A2
,llAOB02
A.
A3
R15
"""L..r
15
,uA0802
SERIES
A'
SERIES
A5
10
RL
A6
11
A7
AS
7
S
A5
(-) VREF
R1'
A2
15
A3
A6
,.
A1
12
16
A7
1OL...r
AS
10
11
12
C
C
vcc-
VCC-
Fig. 5
Fig. 6
USE WITH CURRENT-TO-VOLTAGE CONVERTING OP AMP
Vcc+
VREF: 2.0 Vdc
R14=R15,=,,1.0kO
RO = 5.0 kO
MSB
A1
5
"
A2
A3
R15
JiAOB02
SERIES
A5
A7
THEORETICAL Vo
15
7
A.
A6
VREF
R1.
10
VREF
-=-
Vo =
R14
[A1
(RO)
A3
A4
AS
+ 16 + 32 +
AS, A7
64 1"- 128
+
AS]
256
ADJUST VREF R14 OR RO SO THAT Vo WITH ALL DIGITAL
INPUTS AT HIGH LEVEL IS EQUAL TO 9.961 VOLTS.
RO
11
12
AS
LSB
A2
"2 + ""4 + 8
•
VO =
2V
"1"k""
(5
k)
['
"2 +"41
"" 10 V
Fig. 7
5-14
255
256
+'"8
=
1
1
1
+ 16
+ 32
+ 64
+
9.961 V
1
128
+
1
256
J
JLA4151 • JLA7151
VOL TAGE-TO-FREQUENCY CONVERTERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
DESCRIPTION - The J.LA4151 is a monolithic building block used to convert dc voltage to
digital pulses. The frequency of the output pulses is proportional to the dc input voltage.
The J.LA4151 consists of a voltage comparator. a monostable multivibrator and a precision
switched current source (see block diagram).
The J.LA7151 is the same device as the J.LA4151 with a high performance operational amplifier
on the same chip. The single supply op amp conditions the input signal and provides a
significant improvement in system performance.
CONNECTION DIAGRAMS
14-PINDIP
(TOP VIEW)
PACKAGE OUTLINES 6A 9A
PACKAGE CODES
D
P
SCALE
FACTOR
•
•
•
•
•
•
•
•
•
•
•
SINGLE SUPPLY (+8 VDc TO +30 VDd
LINEARITY TO ±0.05%
PROGRAMMABLE SCALE FACTOR
PULSE OUTPUT COMPATIBLE WITH ANY LOGIC FORM
TEMPERATURE STABILITY TYPICALLY ±100 ppmrc
HIGH NOISE REJECTION
EASILY TRANSMITTABLE OUTPUT
SIMPLE FULL-SCALE TRIM
SINGLE-ENDED INPUT, REFERENCED TO GROUND
ALSO PROVIDES FREQUENCY-To-VOLTAGE CONVERSION
HIGH PERFORMANCE OP AMP INCLUDED IN JLA7151
ONE SHOT
RC
I
OPAMP
OUT
ORDER INFORMATION
PART NO.
TYPE
JLA7151PC
8-PIN MINI DIP
(TOP VIEW)
PACKAGE OUTLINES 9T
PACKAGE CODES
T
ABSOLUTE MAXIMUM RATINGS
32 V
670 mW
-0.2 V to +Vcc
-0.2 V to +Vcc
continuous
continuous
+13 V to -Vs
+2Vto+13V
O°C to +70°C
- 65°C to + 150°C
Supply Voltage
Internal Power Dissipation
Input Voltage (Comparator)
Input Voltage (Op Amp)
Logic Out Shorted-to-Ground
Op Amp Out Shorted-to-Ground
Op Amp Input Common Mode Voltage Range
Op Amp Output Voltage Range. RL = 10 k!l
Operating Temperature Range
Storage Temperature Range
Pin Temperatures
Molded DIP (Soldering. 10 s)
Hermetic DIP (Soldering. 60 s)
'0"'0'
F:g~~~
2
7
VIN
L.OGIC
3
6
THRESHOLD
GND
4
5
~~E SHOT
OUT
Vee
ORDER INFORMATION
PART NO.
JLA4151TC
TYPE
B-PIN METAL CAN
(TOP VIEW)
PACKAGE OUTLINE 5S
PACKAGE CODE
H
Vee
GNO
ORDER INFORMATION
5-15
TYPE
PART NO.
JLA4151
JLA4151HC
FAIRCHILD. ,uA4151 • ILA7151
ELECTRICAL CHARACTERISTICS: Vee = +15 V, TA = 25°C unless otherwise specified.
The following specs apply to the Converter Section only.
CONDITIONS
CHARACTERISTICS
8.0 V ..; Vee"; 15 V
15 V ..; Vee"; 22 V
22 V ..; Vee"; 30 V
Supply Current
MIN
TYP
MAX
UNITS
3.0
3.0
3.0
4.5
5.5
6.5
7.0
8.5
10.5
0.90
1.0
±1oo
0.2
1.10
kHz/V
ppm/"C
1.0
%N
5.0
10
±1oo
-300
mV
Vee-3.O
V
0.667
-100
0.70
-500
xVee
0.15
0.50
V
1.0
1.0
2.5
50
pA
pA
nA
1.9
2.08
V
0.15
0.10
0.1
0.50
0.35
1.0
V
V
pA
rnA
Conversion Accuracy
Scale Factor
Drift with Temperature
Figure 2, V1 = 10 V, Rs = 14 kO
Figure 2, Vl = 10 V
Drift with Vee
Figure 2, 8.0 V..; Vee"; 18 V, V1 = 1.0 V
Input Comparator
Offset Voltage
Offset Current
Inpu1 Bias Current
Common Mode Range (Note 1)
0
±50
-100
Oto
nA
nA
Vee-2
One-Shot
Threshold Voltage, Pin 5
Input Bias Current, Pin 5
0.63
Pin 5, I = 2.2 mA
ResetVsat
Current Source
Outpu1 Current (Vs-14 kO)
Change with Voltage
Off leakage
Reference Voltage
138.7
Pin 1, Figure 1, V = 0
Pin 1, V = OVtoV = 10V
Pin1,V=OV
1.70
Pin 2, Figure 1
nA
logic Outpu1
Pin 3, I = 3.0 mA
Pin 3, I = 2.0 rnA
Vsat
Vsat
Off leakage
NOTE 1: Input common mode range Includes ground.
jlA7151 Op-Amp
ELECTRICAL CHARACTERISTICS: Vs = +15 V and ground TA = 25"C unless otherwise specified.
TYP
MAX
Input Offset Voltage
2.0
5.0
Input Offset Current
10
50
nA
-50
-250
nA
CHARACTERISTICS
MIN
Input Bias Current
Inpilt Impedance
1.0
UNITS
mV
MO
Common Mode Rejection Ratio
70
90
dB
Large Signal Voltage Gain, RL = 10 k
50
200
V/mV
Slew Rate
V/p.s
0.6
15,
Power Supply Rejection Ratio
Ou1put Short Circuit Current
10
5-16
100
p.VN
40
mA
FAIRCHILD. f.LA4151 • f.LA7151
CIRCUIT DESCRIPTION
The /LA7151 consists of five circuit blocks as shown in Figure 1. The blocks may be connected in a
variety of ways to construct voltage-to-frequency converters (VFC), frequency-to-voltage cQnverters
(FVC), or other circuit functions. The circuit blocks are:
1. A differential input comparator featuring very high gain, low offsets, and a common mode range
which includes ground.
2. A one-shot multivibrator with the time constant set by an external RC (T = 1.1 RC) connected to
the RC terminal, triggered by the output of the comparator being high.
3. A precision switched current source that is turned on to the value of IREF when the one-shot is
on and goes to zero when the one-shot is off. The current IREF is set by an external Rs , connected from the scale factor terminal-to-ground and is equal to the reference voltage divided by
Rs and is optimized when set to 138 /LA.
4. An open collector output that provides a buffered output from tre one-shot.
5. An operational amplifier whose common mode range includes ground and has offset null capability. The op amp has high gain, low offset voltage, low input currents, good PSRR and CMRR,
and low drift.
PRINCIPLE OF OPERATION
Voltage to Frequency Conversion (VFC)
As a voltage to frequency converter the /LA7151/4151 can be connected in several configurations
depending on the input voltage, required accuracy, and response time. In all the applications we will
see that the input voltage is converted to a current and the circuit will turn the switched current
source on at the rate necessary so that the average current from the current source is equal to the
input current. As the input voltage (and current) increases, the current source must turn on more
often, and the output frequency increases.
SELECTING COMPONENTS FOR THE VFC
Voltage-to-frequency converters can be used for full scale voltages of 100 mV or greater and full
scale frequencies of 1 Hz to 100 kHz. Input voltages in excess of V cc+ can be accommodated with
appropriate resistor dividers to attenuate the voltages. The following components selection
guidelines should be used.
1. Rs should be approximately 14 kfl to optimize the system performance versus temperature. Rs
is normally a 12 kfl fixed resistor and a 5 kfl pot to be used to adjust the full scale output
frequency. Small variations in Rs have minimal effect on system temperature performance.
IREF = VREF/Rs = 1.95 V/Rs
2. Ro Co sets the one-shot pulse width, To = 1.1 Ro Co. This pulse width must be shorter than the
minimum period of the maximum frequency ie, set it equal to .75 (1/fo). Therefore, Ro Co = .68
(1/fo). Values of Ro should be between 6.8 kfl and 680.kfl and Co should be from .001 /LFto 1 /LF.
3. Rs should be as low as possible for the highest accuracy, (this reduces the effect of current
source ROUT) but must be large enough to insure that the current source output is greater than
VIN max/Rs· Therefore, choose Rs such that Rs - 1.33 VIN max/l o.
4. C s for Figure 2 must be chosen to trade-off between accuracy and response time. Larger values of C s give greater system accuracy but response time is limited by the Rs Ds time constant. A good choice for Ds is 1O-2 /fo.
5. C1 for Figures 3 and 4 can be selected depending on the output frequency. The smaller C1 is
the faster the system response wil be. C1 must be large enough to limit the amplifier swing. The
op amp will swing a voltage set by loTofC1 , so if the comparator is biased at 2/3 V cc + this
constrains C1 > 3 loTo/2 Vcc+. A nominal value of C1 = 5 x 1O-5 /fo meets this requirement.
COMPARISON OF VOLTAGE TO FREQUENCY CIRCUITS
Table I shows a comparison of the three basic circuits set-up for a 0 to 10 V input range and a full
scale output of 10kHz.
FREQUENCY TO VOLTAGE CONVERSION
The /LA7151/4151 can be connected as frequency-to-voltage converter (FVC). This circuit basically
works by putting out a current pulse per cycle of input frequency and intergrating the current pulses
across an output resistor to give an output voltage which is proportional to the average value of 10
(10TofIN)·
5-17
•
FAIRCHILD. J.l.A4151 • J.l.A7151
TABLE I - APPLICATIONS
Figure 2
Figure 3
Figure 4
1.0%
0.2%
0.05%
Frequency Offset
+10 Hz
0
0
Response Time
135/Ls
200/Ls
10/LS
Linearity
Input Voltage
+
+
-
Single Supply
yes
yes
yes
-
-
yes
Split Supply
CB +Vcc
0.1 "F
.01 "F
t
+Vcc
~
1----::---- TO PIN 6
Rs
100 k!l
7
V,
VOLTAGE
INPUT
"A
VFC
RB
-=-
12kll
4151
6
5kll
1---_-010
100 kll
10
RL
5.1 kll
lJlJ
T-j
Co
JO.l"F
Ro
6.8 kll
~
TO +Vcc
DESIGN EQUATIONS
Rs
10 ~ KV, Where K ~ 0.486. RBRoC o
T~
kHz
V
1.1 RoCo
Fig. 1
Fig. 2
PRECISION VOLTAGE TO FREQUENCY CONVERTER FOR POSITIVE INPUTS
,..-----<> v+
Cl 0.005 "F
,---
6
12
I,uA7151
5 kll
fO = VIN X 1 kHx/V
o < VI
< 10 V
LINEARITY 0.20%
RESPONSE TIME 200
OFFSET ZERO
o--'VII'v-~H
Ro
5 kll
6.8 kll
~-------4--oV+
Fig. 3
5-18
-=-
FREQUENCY
OUTPUT
"s
FAIRCHILD. JLA4151 • JLA7151
PRECISION VOLTAGE TO FREQUENCY CONVERTER FOR NEGATIVE INPUTS
,------<:> v +
Cl
=
0.005 /.'-F
6
12
r;:;:A71s1-
I
-10 ,'V ,N
1 kHz/V
Co
RO
.01 ",F
6.8 k
L--------~_oV"
Fig. 4
SINGLE SUPPLY FREQUENCY-TO-VOLTAGE CONVERTER
VOLTAGE
OUTPUT
Oto+l0V
+15 V
Vo
CB
10 kH
10 k!l
RS
MA
4151
FVC
5 kH
,.0 MF
r
RB
100 kU
PULSE
OUTPUT
(optional)
--uu-
5.0 V p-p
SaUARE
WAVE
DESIGN EQUATIONS
Vo =. I, K 1 Where K=O.486
R8:~CO ~
T = 1.1 RoC o
Fig. 5
PRECISION FREQUENCY TO VOLTAGE CONVERTER
V+
0.022 I'-F
f, N
0----1 f-.....-'+-i-I
>-,--+--<:>
10 kit
VOUT
10 k!!
100 k!!
Ro
6.8 kH
0.01 JLF
- V
Fig. 6
5-19
VOUT
=
fiN. 1 Vl1 kHz
•
FAIRCHILD. tLA4151 • tLA7151
LOW COST, REMOTE SENSED 8-BIT AID CONVERTER
RB
20 kO
5 kn
Rs
12 kfl
12.8 kfl
FI
CO
.001 JL
v+
fO'" 10 kHzjV
Fig. 7
MOTOR SPEED CONTROLLER
+15 V
RS
Sk!l
12 kH
C,
Fig. 8
FSK DEMODULATOR
1-15 V
Fig. 9
5-20
J,tA9706 • J,tA9706A
MULTI-CHANNEL, 12-BIT ACCURATE,
JLP COMPATIBLE, D/A CONVERTERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The }.LA9706 and }.LA9706A are digital-to-analog-converters which allow a microprocessor system to interface and control analog systems.
The }.LA9706 is programmed by 9-bit words, accepted in a serial format, while the
}.LA9706A accepts 9-bit words in parallel 3-bit groups. Both the }.LA9706 and }.LA9706A
provide conversions on all channels simultaneously and continuously as long as the
oscillator signal is present. Digital-to-analog conversion is accomplished using a
pulse-width ratio technique for directly controlling the duty cycle of the output pulse
streams. Each channel, when appropriately filtered, supplies 6-bit resolution, or 64
discrete analog levels. By properly summing two outputs, the resolution may be controlled up to 12 bits, or 4096 discrete levels. The }.LA9706 provides 8-channel operation,
whereas the }.LA9706A provides 7-channel operation. Each channel outpulrna'jntains
12-bit, or ±.01% full-scale, accuracy.
•
•
•
•
•
•
•
•
•
•
MICROPROCESSOR COMPATIBLE
CMOS TECHNOLOGY
LOW COST
8 CHANNELS (}.LA9706), 7 CHANNELS (}.LA9706A)
LINEARITY ±O.01%
EXPANDABLE TO 12-BIT RESOLUTION
INTERNAL MEMORY
SINGLE SUPPLY (+5 V)
EXCELLENT STABILITY - NO ADJUSTMENTS
SUITED FOR BUS ORIENTED APPLICATIONS
}.LA9706 - SERIAL INPUT FORMAT
}.LA9706A - PARALLEL INPUT FORMAT
Tuning, Volume, Color
Contrast, Intensity, Hue
• Remote Control Audio Systems - Stereo
Quadraphonic
• Microprocessor Control Systems - Games, Toys
Appliances
Automotive
Industrial Processes
Instrumentation
00
10 PORT
I
0,
0,
OATA
,P
INPUT J1A9706
OSC INPUT
WIR
06
DATA CLOCK
05
VDD(+V)
04
DATA INPUT
03
00
02
01
(-V) vss
5V
DATA
CLOCK
07
CONNECTION DIAGRAM
ILA9706A
16-PIN PACKAGE
(TOP VIEW)
PACKAGE OUTLlNES7B 9B
PACKAGE CODES D P
VARACTOR TUNED 12-BIT RECEIVER SYSTEM
W/R
(-V) vss
ORDER INFORMATION
TYPE
PART NO.
}.LA9706
}.LA9706PC
}.LA9706
ILA9706DC
APPLICATIONS
• Remote Control TV -
VOD
CONNECTION DIAGRAM
}.LA9706
14-PIN DIP PACKAGE
(TOP VIEW)
PACKAGE OUTLINES 7A9A
PACKAGE CODES D P
osc INPUT
07
WIR
06
DATA CLOCK
05
Voo (+V)
04
DBO
10 CLOCK
DB1
03
DB2
02
01
0,
TO
0"
OTHER
CONTROLS
0,
00
CLOCK
OSC
ORDER INFORMATION
TYPE
PART NO.
ILA9706A
ILA9706APC
ILA9706A
ILA9706ADC
0,
INPUT
V"
5-21
•
FAIRCHILD • JLA9706 • JLA9706A
FUNCTIONAL DIAGRAMS
IlA9706
a:
W
IUI
"t:
W
a:
UI
~
a:
w
it
I-
~
6 x 8 RAM
~L'6T6'K ----+-
..'"
::>
DATA
OUT
"0:z
OUTPUTS
""
g'"
:r
UI
w
"ow
"
DATA
DATA
W/i'i
INPUT
IlA9706A
DB, - - _ . - - - - - - - ,
DB,---~~-_+~--,
UI
DBo---~~-_+~--,
~...
..
::>
E
a:
UI
I-
6 x 8 RAM
e1 iii
M
""
w
"
~~
z"
-w
a:
ENABLE
DATA
CLOCK
'"
"z0:
:r
UI
w
o
w
a:
I-
10 CLOCK
DATA
OUT
W/i'i
5-22
OUTPUTS
FAIRCHILD • J.LA9706 • J.LA9706A
ABSOLUTE MAXIMUM RATINGS
-0.3 V to 5.5 V
-0.3 V to Voo +0.3 V
25mA
O°C to 85°C
- 65°C to + 150°C
260°C
Voo Relative to Vss
Digital Input Range
Output Sink or Source Current
Operating Temperature
Storage Temperature
Pin Temperature (Soldering, 10 s)
= +5 V Vss = 0 V TA = DoC to +70°C fose = 100 kHz
TYP
CHARACTERISTICS
MIN
Output Resistance (Channels 4 & 5)
30
Output Resistance (Channels 0, 1, 2, 3, 6, 7)
300
Oscillator Frequency
50
Data Clock HIGH Time
4
4
Data Clock LOW Time
W/R Pulse Width
4
Linearity
Voltage Input HIGH
Voltage Input LOW
0.8
Power Supply Current
40
Input Current
Input Capacitance
8
Input Rise Time
Input Fall Time
Input Set-up Time
ELECTRICAL CHARACTERISTICS: Voo
SYMBOL
Ro
Ro
fose
tH
tL
tw/R
Error
VIH
VIL
100
liN
CIN
tr
tf
ts
MAX
50
1000
2000
128/fosc
!l
!l
kHz
Ils
Ils
IlS
0.01
2.7
%
200
50
IlA
IlA
pF
1.0
1.0
1.0
Ils
IlS
IlS
FUNCTIONAL DESCRIPTION The functional blocks of the IlA9706 and p.A9706A are defined by the pulse-width ratio conversion
scheme that they employ. In addition, other requirements-which include microprocessor compatibility, multi-channel operation, and simultaneous conversion of all channels add to the basic
structure. The p.A9706 consists of seven functional blocks: a 6-bit binary counter, a pulse
distributor called a priority encoder, 6 x 8 RAM, 1-of-8 channel address decoder, 6-to-1 channeldata multiplexer, 9-bit input shift register, and a set of eight output buffers.
Tile pulse-width-ratio conversion scheme divides the conversion cycle into binary-weighted
time intervals and associates each time interval with a bit position in the 6-bit control word. The
control word residing in RAM is then addressed, bit by bit, each bit addressed for the associated
time interval. The value of each bit, "1" or "0", controls the output, HIGH or LOW, during this time
interval (see Figure 1). In this manner, an output pulse stream is generated with a duty cycle defined by the control word. When the pulse stream is filtered, a dc value is extracted that is proportional to the duty cycle of the pulse stream and, hence, proportional to the control word.
The 6-bit counter generates the fundamental time intervals for the system and may be driven
by any open-collector TTL or CMOS logic that produces a square-wave signal with a frequency
in the range of 50 kHz to 2 MHz. The time intervals (binary-weighted pulse widths) generated by the
counter are decoded by the priority encoder which serves two functions. First, it ensures that each
of the six time intervals (control pulses) is used once during the conversion cycle. Second, it distributes the control pulses to both the channel-data multiplexer and to the column-address inputs
of the 6 x 8 RAM.
5-23
UNITS
V
V
II
FAIRCHILD • ILA9706 • ILA9706A
USB
LSB
o
(DECIMAL 21) = RAM CONTENT
ONE OUTPUT CYCLE
r~---------------------------------------~'-------------------------------------~,
:~--------~
II
8 OSC CYCLES
16 OSC CYCLES
Ii
32 OSC CYCLES
64 OSC CYCLES
L------..,II-
1....
• __- - - - - - - - - - - - - - - - - - - 1 2 8 C Y C L E S - - - - - - - - - - - - - - - - 1
TIME
Fig. 1 Output Cycle Example
The channel-data multiplexer is enabled during the write mode so that the 6-bit control word
may be written. The 6 x 8 RAM provides the storage capability required forthe converterto operate
independently of the microprocessor, once the control information has been transferred. Since
the control information is stored in RAM, simultaneous conversions continue on all eight channels,
unaided by the microprocessor unless changes are required. This is accomplished by addressing
a single bit in each of the control words and reading the results out in parallel during each time
interval in the conversion cycle. The total cy~le time, which is the sum of the six binary-weighted
time intervals plus a unit interval (64 clock periods), requires 128 oscillator periods, since the basic
oscillator frequency is divided by a factor of two before driving the counter. Conversions may be
completed in as little as 64 p'S when operating at a 2 MHz clock rate. The control words read from
the RAM are directed to the output buffers, six of which have 1 kfl and two have 50 n output impedances. In general, these buffers should drive load impedances larger than the output impedance to reduce the errors caused by the finite output impedance.
Each output is capable of providing 64 discrete output levels representing 6-bit resolution. Since
each output pulse stream is accurate to 12 bits, it is possible to sum two outputs and expand the
resolution to 12 bits, providing 4096 discrete output levels. This may be easily accomplished by
weighting one of the outputs by a factor of 1/64 before summing.
Loading data is a simple procedure that does not affect the conversion cycle. For the p.A9706, the
6-bit control word (channel data) and the 3-bit channel address are serially transferred to the 9-bit
shift register on the HIGH-to-LOW transitions of the data clock (Figure 2). The data clock has a
maximum frequency of 125 kHz with a minimum HIGH and LOW time of 4 p.s. Once the nine bits
of data have been transferred into the shift register, the data clock must remain static until the write
operation is completed to prevent the data from being shifted out of the register. The write mode
may be selected after a minimum setup time of 1 P.s and is enabled bya HIGH-going W/R control
pulse. This sets an internal latch that enables the channel-address decoder, which decodes the
3-bit binary channel address, therefore effecting the transfer of the 6-bit control word from the
input register to RAM via the channel-data multiplexer at the beginning of the next conversion
cycle. The W/R pulse has two restrictions: first, it must be equal to or greater than 4 p'S in duration;
second, it must be less than 128/f05c . This latter restriction is necessary to eliminate the possibility
of multiple loads occurring from a single W/R pulse that could lead to incorrect control-word transfers under certain conditions.
The p.A9706A is basically the same as the p.A9706 except for two differences: input structure
and pin limitation. The p.A9706A has three 3-bit shift registers, used for temporary storage of the
3-bit channel address and 6-bit control word. This structure is bus oriented and provides for
parallel3-bit transfers between the microprocessor and the converter (Figure 3). Also, before any
transfers can take place, a 3-bit ID code must be accepted. The ID code is provided in parallel over
the ID clock and DBa, DBl and DB2 inputs. After the nine bits of data are transferred to the shift
registers, the operation of the p.A9706A is identical to the p.A9706. The p.A9706A provides 7-channel
operation as opposed to the 8-channel operation of the p.A9706.
5-24
T
OUTPUT
VOLTS
1
FAIRCHILD • J,.tA9706 • J,.tA9706A
FIRST BIT
LAST BIT
IN
CHANNEL-DATA
CHANNEL ADDRESS
IN
DATA INPUT
DATA
CLOCK
__________________________________________________________________________________________________
~~R
TIME-+-
tw/R'
Fig. 2 I'A9706 Input Timing and Format
I
FIRST BIT
IN
t
LAST BIT
~~_________________________________I~r____________________________________
ADDRESS
LSB
ADDRESS
Fig. 3
ADDRESS
MSB
I'A9706A Input Timing and Format
5-25
10 CLOCK
DBa
FAIRCHILD • JLA9706. JLA9706A
TYPICAL MA9706 SYSTEM
r
I+VDD~5V
5V
00
W/R
10 PORT
r----
011---
DATA
CLOCK
021---
DATA INPUT
031---
TYPICAL OF EIGHT CHANNELS
~A9706
"p
50 k
50 k
Vo TO HIGH
IMPEDANCE LOAD
04
J:0.002
CLOCK
2MHz
OSC
INPUT
10.002
I"F I"F
051---
061---
07
r----
VSS
~
~
/-LA9706 Fa OBJECT CODE SUBROUTINE
enter with Ro = data to be output to 9706
Rl = address to be output to 9706
entry = H'100'
F8 Object Code
M100-130
M0100=20
M0108=BO
M0110=24
M0118=50
M0120=43
M0128=94
M0130=1C
20
20
OC
42
52
E3
52
OF
BO
12
70
20
20
BO
24
52
51
OB
04
40
02
94
53
BO
53
22
BO
EF
40
20
20
FE
40
41
18
OF
07
18
12
50
18
BO
Port
Port
Port
Port
0
0
0
0
bit
bit
bit
bit
0
1
2
3
=
=
=
=
0
0
0
0
0
0
0
bit
bit
bit
bit
bit
bit
bit
0
1
2
3
4
5
6
=
=
=
=
Data Input
Data Clock
W/R
Scope Trigger
Exit = return. destroyed Ro. R1 • R2• R3 • Acc
/-LA9706A F8 OBJECT CODE SUBROUTINE
enter with Ro = data to be output to 9706A
R1 = address to be output to 9706A
entry = H'100'
F8 Object Code
M100-16D
M0100=20
M0108=41
M0110=52
M0118=F1
M0120=13
M0128=13
M0130=54
M0138=10
M0140=FO
M0148=BO
M0150=79
M0158=43
M0160=20
M0168=5F
61
18
20
12
13
C3
20
FO
12
20
BO
BO
10
BO
52
51
02
C4
C2
53
08
12
12
7F
42
20
C4
20
53
20
F1
54
52
20
FO
12
12
BO
BO
10
BO
7F
54
01
C3
20
20
04
12
C3
C4
20
20
C3
20
BO
40
F1
53
01
02
FO
C2
53
54
78
10
BO
7F
1C
18
13
20
FO
FO
13
52
20
20
BO
C2
44
BO
50
C2
04
13
13
C4
20
20
3F
20
BO
BO
20
Exit = return. destroyed Ro. R1• R2• R3 • R4 • Acc
5-26
Port
Port
Port
Port
Port
Port
Port
ID clock
DBo
DB1
DB2
= data clock
= w/Fi
= scope trigger
tL A9708
6-CHANNEL, a-BIT, MICROPROCESSOR COMPATIBLE
ANALOG-TO-DIGITAL CONVERTER SUBSYSTEM*
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The I'A9708 is a single slope 8-bit, 6-channel ADC subsystem that provides all of the necessary analog functions for a microprocessor-based
data control system. The device uses a microprocessor system like the F3870 or F6800
to provide the necessary addressing, timing and counting functions and includes a 1 of
8 decoder, 8-channel analog multiplexer, sample and hold, ramp integrator, precision
ramp reference, and a comparator on a single monolithic chip.
CONNECTION DIAGRAM
l6-PIN DUAL IN-LINE
(TOP VIEW)
PACKAGE OUTLINES 79 99
PACKAGE CODES
D P
A,
Ao
A2
RAMP
•
•
MPU COMPATIBLE
EXCELLENT LINEARITY OVER FULL TEMP RANGE - ±O.2% MAX
•
•
•
•
TYPICAL 300 I's CONVERSION TIME PER CHANNEL
WIDE DYNAMIC RANGE INCLUDES GROUND
AUTO-ZERO AND FULL-SCALE CORRECTION CAPABILITY
RATIOMETRIC CONVERSION-NO PRECISION REFERENCE REQUIRED
•
SINGLE-SUPPLY OPERATION
•
•
TTL COMPATIBLE
DOES NOT REQUIRE ACCESS TO DATA BUS OR ADDRESS BUS
Vee
START
CH
12
GNO
"
I,
RREF
RAMP
I,
STOP
16
VREF
ORDER INFORMATION
TYPE
PART NO.
I'A9708
I'A9708
I'A9708
I'A9708DM
I'A9708DC
I'A9708PC
BLOCK DIAGRAM
RAMP START
(FROM MPU)
r----------------------® ------------------1
I
I
II
ICD
7
RAMP STOP
~~
I
tI IREF
I.@
COMPARATOR
ANALOG
INPUTS
CONSTANT
CURRENT
SOURCE
1-0F-8
ADDRESS DECODER
I
I
L--------
-=-
REFERENCE
CURReNT
GENERATOR
i
@-----------@-0--0
RREF
'::'
Vee
VREF +Vcc
5-27
I
8)
VSE
I
I
I
_______ J
CH (RAMP CAPACITOR)
•
FAIRCHILD • MA9708
ABSOLUTE MAXIMUM RATINGS
18 V
-0.3 V to +18 V
-0.3 V to 30 V
-0.3 V to 30 V
10 mA
Supply Voltage (Vee)
Comparator Output (Ramp Stop)
Analog Input Range
Digital Input Range
Output Sink Current
Operating Temperature Range
I'A9708PC. I'A9708DC
I'A9708DM
Storage Temperature Range
Continuous Total Dissipation
Ceramic DIP Package
Plastic DIP Package
Pin Temperature. Ceramic DIP (Soldering. 60 s)
Plastic DIP (Soldering. 10 s)
O°C to 70°C
-55°C to 125°C
-65° C to +150° C
900 mW
1000 mW
300°C
260°C
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTICS
MIN
TYP
MAX
UNITS
Supply Voltage (Vee)
Reference Voltage (VREF)'
Ramp Capacitor (CH)
Reference Current OR)
Analog Input Range
Ramp Stop Output
Current
4.75
2.8
300
12
0
5.0
15
5.25
V
V
pF
I'A
V
mA
50
VREF
1.6
'2 V S VAEF S (Vee -2 VI
CHANNEL SELECTION
INPUT ADDRESS LINE
Ao
A2
A1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
SELECTED
ANALOG INPUT
Ground
0
1
0
1
0
1
0
1
h
12
i3
14
15
16
VREF
5-28
FAIRCHILD. MA9708
ELECTRICAL CHARACTERISTICS: Over recommended operating conditions, -55°C:O: TA:O: +125°C, for I'A970BDM and
O°C:o: TA:O: +70°C for I'A970BDC or MA970BPC; unless otherwise specified.
LIMITS
TYP
MAX
Over entire temperature range
INote 1)
±0.2
±0.3
%
Applies to anyone channel
INote 2)
±O.OB
±0.2
%
CHARACTERISTICS
SYMBOL
CONDITIONS
Conversion Accuracy
EA
Linearity
ER
MIN
UNITS
Channel ON
2.0
4.0
.mV
Conversion Time Per Channel
tc
Analog Input = Ov to VREF
CH = 300 pF, IREF = 50 MA
296
350
MS
Acquisition Time
tA
CH
20
40
Acquistion Current
IA
Multiplexer Input Offset Voltage
VOSM
= 1000 pF
150
MS
MA
Ramp Start Delay Time
to
100
ns
Multiplexer Address Time
tM
1.0
MS
Digital Input HIGH Voltage
VIH
Ao, At, A2, ramp start
Digital Inpul'LOW Voltage
Vil
Ao, At, A2, ramp start
Analog Input Current
16
Channel ON or OFF
Input LOW Current
III
Ao, At, A2, ramp start
Input HIGH Current
IIH
Ao, At, A2, ramp start
Input Offset Current
los
Comparator Logic "1" Output Leakage Current
10H
Comparator Logic "0" Output Voltage
VOL
Power Supply Rejection Ratio
PSRR
V
2.0
O.B
= 0.4 V
= 5.5 V
-3.0
-1.0
-15
-5
1.0
= 15 V
10l = 1.6 mA
VOH
MA
1.0
MA
3.0
MA
10
MA
0.4
INote 3)
V
MA
V
dB
40
dB
Crosstalk Between Any Two Channels
INote 4)
Power Supply Current
Icc
Vcc
Input Capacitance
CIN
3.0
pF
COUT
5.0
pF
Comparator Output Capacitance
60
= 5 V to
15 V, 10
=0
7.5
15
mA
NOTES:
1. Conversion accuracy is defined as the deviations from a straight line drawn between the pOints defined by channel address 000 (0 scale) and channel
address 111 (full scale) for all channels.
2. Linearity is defined as the deviation from a straight line drawn between the 0 and full scale points for each channel.
3. Power supply rejection ratio is defined as the conversion error contributed by power supply voltage variations while resolving mid scale on any channel.
4. Crosstalk between channels = 20
IOgl1~6iH
FUNCTIONAL DESCRIPTION
This Analog to Digital Converter is a single-slope 8-bit, 6-channel AID converter that provides all of
the necessary analog functions for a microprocessor-based data/control system. The device uses
the processor system to provide the necessary addressing, timing and counting functions and
includes a 1 of 8 decoder, 8-channel analog multiplexer, sample and hold, precision current
reference, ramp integrator and comparator on a single monolithic Chip.
For applications that require auto-zero or auto-calibration, (See Figures 2-5) line select address 0,
0, and 1, 1,1 may be used in conjunction with the arithmetic capability of the microprocessor to
provide ground and scaling factors. Address 0, 0,
internally connects the input of the ramp
generator to ground and may be used for zero offset correction in subsequent conversions.
Address 1,1,1 internally connects the input of the ramp generator, to the voltage reference, VREF,
and may be used for scale factor correction in subsequent conversions. For the following, refer to
the Functional Block Diagram.
°
°
Six separate external analog voltage inputs may come into terminals 1,-16 and the specific analog
input to be converted is selected via address terminals Ao-A2. The analog input voltage level is
transferred to the external ramp capacitor connected to pin 4 when the input to the ramp start
terminal (pin 3) is at a logic (See Figure 1). The time to charge the capaCitor is the acquisition time
°
5-29
•
FAIRCHILD • MA9708
which is a function of the output impedance of an amplifier internal to the AID and the value of the
capacitor. After charging the external capacitor the ramp start terminal is switched to a logic 1
which introduces a high impedance between the analog input voltage and the external capacitor.
The capacitor begins to discharge at a controlled rate. The controlled rate of discharge (ramp) is
established by the external reference voltage, the external reference resistor, the value of the
external capacitor and the internal leakage of the AID. Connected to the capacitor terminal is a
comparator internal to the AID with its output going to the ramp stop terminal (pin 7), The
comparator output is a logical one when the capacitor is charged and switches to a logic 0 when the
capacitor is in a discharged state. The ramp time is the time from when ramp start goes high (logic
"1") to when ramp stop goes low (logic "0"), The microprocessor must be programmed todetermine
this conversion time. The ideal (no undesirable internal source impedances, leakage paths, errors
on levels where comparator switches or delay time) conversion time is calculated as follows.
CH
Ramp Time = V1 II;"
Where
V1 = Analog Input Voltage being measured
CH =, External Ramp Capacitor
IR
Where
=
Vee - VREF
RREF
Vee = Power Supply Voltage
VREF = Reference Voltage
RREF = Reference Resistor
In actual use the errors due to a nonideal AID can be minimized by using a microprocessor to make
the calculations. (See Figures 2 through 5)
RAMP START
.: -----;r"~.--I
- - 22
-11~
~"'"::::;;-~-----------I--------j~~
I
Vee
() <..l.....;;:1
RAMP STOP
..
I~t-----'R------I~
O.4V _ _ _ _ _.I
1_
.. - - - , c - -__ I
Fig. 1
Equivalent Timing Waveform for Test Circuits and Applications
5-30
FAIRCHILD • J.(A9708
APPLICATION HINTS AND FORMULAS
1. The capacitor node impedance is approximately 30 ILO and should have no parallel resistance
for proper operation.
2. tA when VIN = 0 V will be finite (i.e., the comparator will always toggle for VIN ~ 0 VJ
3. The ramp stop output is open collector, and an external pull up resistor is required.
4. All digital inputs and outputs are TTL compatible.
5. For proper operation timing commences on the 0 to 1 transition of ramp start and terminates on
the 1 to 0 transition of ramp stop.
6. tA
~
CH
X VAEF
150 ILA-IA
.
CH
CH
7. tA (ramp time) =-1- X VIN, tAl
=-1 x VAEF
A
max
A
8. IR = Vee - VREF
RAEF
9. 2 V
~
VAEF
~
(Vee - 2 V)
10. Address lines NJ, A" A2 must be stable throughout the sampling interval, tAo
11. Pin 6 (RAEFl should be bypassed to ground via a 0.02 /LF capacitor.
•
AUTO-ZERO AND FULL-SCALE FEATURES
COUNT
COUNT
2 5 6 1 - - - - - - - - - - ,..
NF.S
N
128 1------7t"
I------------::".,...~
1------:::0..---
Nz
VREF
---.•
•
INPUT
VREF
NO ZERO OFFSET
NO FULL-SCALE ERROR
COUNT (N) =
~
INPUT
VREF
•
•
•
= 256
NF.S. '" 256
Nz '" 0
(N) HAS BOTH FULL-SCALE AND ZERO ERRORS
YREF
Fig. 2
Ideal Transfer Function
Fig. 3 Transfer Function with Zero and Full-Scale Error
COUNT
COUNT
N"F s
N'Fs
1------------::;>1""'
1-------------:,........
N"
N'I---------=:;>.........-
VREF
•
•
1-------:<
INPUT
VREF
N'=N-Nz
N' HAS FULL-SCALE ERROR
N" = (N-Nz) X
INPUT
~
(NF.S. -Nz)
Fig. 5 Both Zero and Full-Scale Correction Added
Fig, 4 Zero-Correction Added
5-31
FAIRCHILD • MA9708
TEST CIRCUITS
ANALOG INPUTS
,~
______--"A~______- , \
ALL COMPONENTS
±10%
+5V
Ao
11
Vee
12
b
14
15
Ie
MA9708
RAMP
RAMP
A2 STAATCHGNO RREFSTOPVREF
Al
1°.01
100
kn
I"F
-=-
2k
L3.3 k
-==
+5V
CONTROL I/O FROM MPU
(TIMING COMPATIBLE WITH FIGURE 1)
INPUT TIMING:
tA>
400 fJ.S
VREF
Ck~~ k~13
5-31
100 kO
IR ~
IR
~
I
~
kri) 5 V
~ 31 V
~ 19 p A
full scale ramp
Ilme~
max
0.01 X 10-6
19 X 10-6
X 3.1
~
I.6ms
NOTE:
For evaluation purposes, the ramp start timing generation can be implemented with a ",A555 timer (astable operation) or MPU
evaluation kit, and a time internal meter for ramp time measurement. The TIM meter will measure the time between theD to 1
transition of the ramp start and the 1 to 0 transition of the rampstop. The ramp stop isopen collector, and must have an external
pull up resistor to Vee.
Fig. 6
Slow Speed Evaluation Circuit lor Rallometrlc Operation
+5 V
Icc
Is, los
r-ll
Ao
11
,uA9708
RAMP
Al
RAMP
r2
1~00rio~ +'t~~
l
pF
IJ
14
15
16
/iA9708
Al
A2 START CH GND RREF STOPVREF
pF
I I I I
Vee 12
/iA
6/iA
RAMP
RAMP
A2 START CH GND RREF STOP VREF
1
J12
t~~
201- 2.75 V
kO
-=-
+4.75 V 4.75 V-
'-----y-----' +5 V
r::
1
-=-2.75 V
IOJ
+5 V +t 5 V
Vll, VIH,
Ill,IIH
Fig. 7
linearity/Acquisition Time/Conversion
Time Test Circuit
Fig. 8 Static Measurements
5-32
FAIRCHILD • J.LA9708
TYPICAL APPLICATIONS
Vcc+
Rs
F8
Vcc+
SYSTEM
R.S.
COMP
"
A3
'3
il A9708
3851
A,
'/0 PORT
"
'5
'6
R,
A,
CAP
VREF
Vee+
I
CH
R,
•
OUTPUT
t:l VI = (Applied Force) and can be Linearized (if necessary) in Fa Software.
Ratiometric Strain Gage Sensor/Controller
SENSOR
I
:lvee+
R3
F8
SYSTEM
Vee+
SOLUTION
'"0a:
'"zw
(DR,
'"a:w
vcc+
-=-
-- "
-"
--
R.S.
"
PHOTO
RESISTOR
....J:
R,
0
COMP
"
A3
jJA9708
'5
A,
'6
CAP
'R--'
IREF
VREF
GND
R,
3851
I/O PORT
A,
~
~
1
Vee+
R3
1°.
02
1
I
CH
CONTROL
CIRCUITS
RAMP CURRENT
APPLICATIONS:
•
•
•
BEVERAGE BREWERS/DISPENSERS
CHEMICAL SOLUTION CONTROL
AUTOMATIC LIQUID MIXING CONTROL
V,
~ (~R
)
Rx + B
RAMP TIME
(..2-)
R3
Vee+
~ V, ~; ~ (
Opaque Solution Controller
5-33
~ IR ~ Vee (_R_'_
)
R, + R2
RxR: Rs ) ( 1+
:~) ( CHR3 )
FAIRCHILD • J-LA9708
SYSTEM HINTS:
Several alternatives exist from a hardware/software standpoint in microprocessor based systems
using the I'A9708.
1. The ramp time measurement may be implemented in software using a register increment,
followed by a branch back depending on the status of the ramp stop.
2. Alternately, the ramp stop may be tied into the interrupt structure in systems containing a
programmable binary timer. This scheme has the following advantages:
A. The CPU is not committed during the ramp time interval.
B. It requires only 4 bits of an I/O port for control signals.
3. The auto-zero/auto-full-scale (see Figures 2-5) should use double precision, rounded (as
opposed to truncated) arithmatics. Several points are worth noting:
A. The subtractions are single op code instructions.
B. The full scale correction uses a multiply by 256 and can be accomplished by a shift left 8 bits
(usually one instruction) or placing (N-Nz) in the MSB register and setting the LSB register to
zero, for the double precision divide.
C. The divisor (NF.S. - Nz) MSB's register will always be zero.
These schemes have the following advantages:
A. No access to the data buss or address buss is required, by the A/D system.
B. 4 I/O bits completely support the AID system.
C. Since auto full scale/auto zero are implemented in software and long term drift (aging) effects
are eliminated.
D. Software overhead is minimal (typically 30 bytes)'
E. Where ratiometric operation is permissible, the 4 external components may be ±5% tolerance, including the power supply.
5-34
9650
4-81T CURRENT SOURCE
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The 9650 is a high speed, 4·Sit Precision Current Source, intended
for use in D/A and AID converters with up to 12-bit accuracy. It is constructed on a single silicon
chip, using the Fairchild Planar* epitaxial process and consists of a reference transistor and four logic
CONNECTION DIAGRAM
16·PIN DIP
(TOP VIEWI
PACKAGE OUTLINE 68
PACAKGE CODE D
operated' precision current sources connected to a single output summing line. Logic inputs are fully
TTL compatible under all temperature and supply conditions. A clamp c.ircuit is provided to prevent
turn on latchup on the reference input.
LSB IN
•
•
•
•
•
200 ns SETTLING TIME (12 ± 1/2 LSSI
STANDARD SUPPLY LEVELS
VARIABLE BIT CURRENTS
REFERENCE COMPENSATION
TTL COMPATIBLE
ABSOLUTE MAXIMUM RATINGS
+7 V
-18 V
2.0 mA
+5.5 V
730 mW
_65°C to +150"C
VCC+
VCCMSB Current
Logic Input Voltage
Power Dissipation (Note 1)
Storage Temperature
Operating Temperature
MSB OUT
BIT2 IN
BIT 2 OUT
MSB IN
BIT 3 OUT
v-
V RH -2
GND
LSB OUT
VREF -1
lOUT
REF OUT
IREF
•
ORDER INFORMATION
TYPE
PART NO.
9650·1C
9650·1 DC
9650·2C
9650·2DC
9650·3DC
9650·3C
OCC to 70 c C
+300°C
+7VtoV+18 V to VREF
Pin Temperature (Soldering, 60 sl
VREF Inputs
Output (V re ! voltage;;, -7.0 VI
vee
61T31N
EQUIVALENT CIRCUIT
~
~3
~2
_
r -______________~------~------4_I-N----~------~--IN----~------~-I-N----~------_r-IN--------------------ov+
R3
12k
10
;---~~------~~--1__+------~----+_~------~----r_---------------oIOUT
;-------------0 IREF
'-_r-----+----~~+_----~------4--+_----_r-----+--+_--~_r--~-:> VREF (1
&
2)
*Planar is a patented Fairchild process.
Notes on following page.
5-35
FAIRCHILD • 9650
9650-1 C • 9650-2C • 9650-3C
ELECTRICAL CHARACTERISTICS: TA = 25'C, Power Supply Range, 4.5V, -14 V to 5.5 V, -16 V, unless otherwise specified
CHARACTERISTICS
CONDITIONS (TYPE)
(see definitions)
MIN.
TYP.
MAX.
Linearity
(9650-1C)
(9650-2C)
(9650-3C)
±0.01
±0.05
10.2
Full Scale Output Current Error
(9650-1C)
(9650-2C)
(9650-3C)
±0.1
±0.2
±OA
(9650-1 C)
(9650-2C, 9650-3C)
±0.003
±0.012
UNITS
% of FSI
% of FSI
% of FSI
%
%
%
Power Supply Coefficient of Full
Scale Output Current
VBE Range
550
hFE of Reference Transist(Jr
Output Impedance
300
650
rnV
1000
All Bits On
The following specifications apply for O°C ~ T A";;; 700
%/V
%/V
Mf!
5.0
e
Accuracy
(9650-1 C)
(9650-2C)
(9650-3C)
[0.025
±O.1
'0.3
Full Scale Output Current Error
(9650-1C)
(9650-2C)
(9650-3C)
0.2
0.3
0.6
(9650-1C)
(9650-2C, 9650-3C)
'0.024
% of FSI
% of FSI
% of FSI
%
%
%
Power Supply Coefficient of Full
Scale Output Current
Input LOW Voltage
Each Bit On
Input HIGH Voltage
Each Bit Off
Input LOW Current
VIL=OAV
Input HI G H Current
VIH.=2AV
Output Current
Bit
Bit
Bit
Bit
Output Current
All Bits Off
(9650-1 C)
(9650-2C, 9650-3C)
Output Voltage
±0.006
0.8
2.0
1 (MSB)
2
3
4 (LSB)
Feeding Op Amp Summing Junction
Reference Current
-1.6
rnA
40
p.A
1.0
0.5
0.25
0.125
2.0
1.0
0.5
0.25
rnA
rnA
rnA
rnA
5.0
5.0
250
500
nA
nA
V+
V
V
0
1.0
Using Compensation Transistor
±1.0
VREF Current
20
V
V
-4.0
Resistive Load
%/V
%/V
rnA
"2.2
rnA
Reference Limit Current
VREF=OV
75
rnA
Positive Supply Current
(9650-1 C, 9650-2C)
(9650-3C)
8.0
10
rnA
rnA
Negative Supply Current
(9650-1 C, 9650-2C)
(9650-3C)
-11
-15
mA
rnA
NOTES:
1. Rating applies for ambient temperature to 70°C. Derate linearly at 9.1 mW/C for ambient temperatures above 70°C.
2.
VREF Voltage 7 -7.0 V.
5-36
FAIRCHILD • 9650
TYPICAL PERFORMANCE CURVES
SWITCHING TIME
AS A FUNCTION OF
MSB CURRENT
(50% IN TO 10% OUT)
OUTPUT CURRENT SETTLING TIME
AS A FUNCTION OF
MSB CURRENT
(0 TO FSI OUTPUT ± 1/2 LSB)
e
SUMMING JUNCTION LOAD
e
SUMMING JUNCTION LOAD
v+ ~ 50 V I
v·
~
,,:c
-
e
-
e_
e
l-
~
I I
,
-
=
5.0
v+--+-+-+-+-f---h>"i
r-~:: ;~'~cV+---+-+-+-+_--!-.J~'?)><0 -
f--+-~-r-T-+-f--t7;r4~.'~
I-
/' V
I I
o
e
'0
INPUT LOGIC
THRESHOLD VOLTAGE
AS A FUNCTION OF
AMBIENT TEMPERATURE
ee
i'-..
co
.'c
co
-75
0.8
~-BIT I
e
"
"
"
1 rnA MSB CURRENT
f--v+
LSI)
e
"
II
I I
I-
SETTLING TIME
AS A FUNCTION OF
LOAD RESISTANCE
(0 TO FSI OUTPUT ± 1/2 LSB)
LOAD RESISTANCE - kll
INPUT LOGIC
THRESHOLD VOLTAGE
AS A FUNCTION OF
SUPPLY VOLTAGE
FULL SCALE OUTPUT
CURRENT DRIFT
AS A FUNCTION OF
AMBIENT TEMPERATURE
•
1.315
v· -SOY
v- -15 V
TA
~
'" """
MSB CURRENT _ mA
~
1 rnA MSB CURRENT
25°C
0,004
1.310
1"~
""'
""
=
5.0
V-+-+--+-+--+-i
/"--
e-- ----
"CO
"CO
f- ~~
,..- r--e-- e--
;
/
1.285
I
"SO
-50
-25
AMBIENT TEMPERATURE _
'"
cc
C.,
-"
TRUTH TABLE
1.875
1000
0.875
0001
1.750
1001
0.750
0010
1.625
1010
0.625
0011
1.500
1011
0.500
0100
1.375
1100
0.375
0101
1.250
1101
0.250
0110
1.125
1110
0.125
0111
1.000
1111
0.000
°c
9650 KITS REQUIRED TO BUILD
DIA - AID CONVERTERS
NOMINAL
NOMINAL
LOGIC INPUT
OUTPUT
LOGIC INPUT
OUTPUT
CURRENT (rnA)
CURRENT (rnA)
0000
AMBIENT TEMPERATURE _
TYPE
TEMPERATURE RANGE
O°C to +70°C
9650·1C
9650-2C
9650·3C
NO. OF UNITS
Accu racy to:
8 Bits
10 Bits
12 Bits
5-37
0
0
1
0
1
1
2
2
1
FAIRCHILD • 9650
TYPICAL APPLICATIONS
VOLTAGE TO FREQUENCY CONVERTER
8-BIT D/A CONVERTER
r:------OIGITAL
INPUTS------~
5k
10
9650-3C
15k
lO-BIT D/A CONVERTER
LSB
810
89
' I i, ~ ~,
1
3
,
~, ~ ~ ~,
""
N,
n
"
-0
2
~
3
2
lOr---
1
9650-2C
6
51
k5
1
r- '
5~
9650-3C
,,5~
"
~pl
"
10-
,
68,-
9650-3C
~ ~ ~
3
2
f--
10
""
n
68-
"
5
'5
l~
" "
~~1;~:"
80 k
.--
40
~
FULL SCALE
Rl0
20<
8
R9
10
R8
~
80k
,
R2
'0<
G
"
5
A6
A5
'"
10k
"
~ ~'9
"'
A18
5'
k5
3~
djl="t/
kG
18
A13
Wk
,
19
3
,
,
A4
R3
R2
Al
SO,
'"
20'
kGk
QU5,ER
I "
~o
~8r
It~
5
G --0 ~OUl
J.1A777
R15
"
R17
135k
"
23
A16
AS FN215 RESISTOR Af1RAY
R20
6k
k3
9
kG
V
R14
14k
~
30
-"-
~
~~
8
ZERO ADJ
"
6
5 Mll
OUf~~rER
""'
"
5-38
~
'"
FAIRCHILD • 9650
TYPICAL APPLICATIONS (Cont'd)
8-BIT AID CONVERTER
SERIAL DATA
CLOCK OUTPUT
CONVERSION
1~4
-
1/4 :"'002
-
_
COMPLETE
al--------.--
J
1---1:><>--I--Icp
....-
SERIAL DATA
OUTPUT
>-(K'ap-'-r;;
"49002P
~-+
__- L______
~~+-
__
~~
____,
~~______~~+--~'~:OO~
CLOCK~ "?OO2
r-_D!I-~Y_+-"""L....J._,
EDAoA1A2
9334
8-BIT ADDRESSABLE LATCH
COl
2
3
4
5
6
7
-
LSB
PARALLEL
DATA
OUTPUT
M58
10V
Vref
"
'5V
~
' I.'~.~
,
,;A777
"----
ir=- ~
I
~L=-!-164---!:-----!',---'---"
Fa
>"-,
a --.---.---~
L7
.1~-Ir
1_ ,-----
30pF
9650·30
15
14
13
'0
11
51 ~
10k 20k. 401<. 80k
lOki
-15 V
"54V
12 15
14
13
~
10 +
96SO-3C
11
51
1
8
jJA734
-
5
10k 20k 40k 8Dk
-15V -
.
a
100 k
--'>---4--+.--4_>----4+-+-_ _-+--4_........---'
QUAD 2
F0777:::!
s::
~ Fom
DIVIO:b
lOon
220k
15k
-15 V
1 "
ANALOG
INPUT
NOTE: Digital gnd. indicated by
Analog gnd. indicated by
5-39
•
FAIRCHILD • 9650
TYPICAL APPLICATIONS (Cant'd)
lO-BIT AID CONVERTER
1,49002
...... 1/49002
CONVERSION
COMPLETE
~
'"'1:(""1 """; 0::- [r" ""
CP
9316
f<:
-<:
K
CP
°0 °1
'P-
K
-"8
---ra
18
I
~:'" :""
Te
°2 03
K
03
00 01
8
03
.
!! !
>----flc
Cl OCK
lJT
CET
CP
CP
'5V
SERIAL
DATA
OUTPUT
~
DATA
1(49002
CLOCK
.A
1/39003
l~f:02
1/49002.......
L L1
,
D
A,
AD
6
C
D
4
5
6
:I' f~
A,
AO
8
9334
r
I I j
6
,
A,
"'749002
y
9334
co,
7
,
r
I I
3
4
5
6
-lSB
'
5V
r~
iI
_M$B
, ,
7
3
4 LO
9650-3C
""
-PARALLEL DATA OUT
15 5 1
3
4LO
7
r-- , - - '
, ,
3
4LO
-7
6~
l4
l3
-
, ,
9650-3C
""
5~
15
l4
l3
,
""
6p-,.
155~
l4
l3
r---
6~
9650-3C
-.15 V
LO"
"
8"
80k
,
LO
8"
40.
8W
20k
89
1D k
8'D
6k
6
5
87
4Dk
86
'D k
85
1D k
8,8
5k
8"
5k
l4
PUlCSDACE [
'4
3
-=-
817
~
1
30pF
23
4
3
, ,
8,3
1D k
84
80k
83
4D k
8,
'Dk
816
815
1k
1k
13.5 k
16
[b-="l"10
10 V
Vrel
7
88
SDk
AS FN-215 RESISTOR ARRAY
13
8
18
19 QUAAI,DER
-¥o
8,
1Dk
~
E-
,.
6
S1H
f~;
t
~~
FDmf 1p
,A734
8 14
14 k
7
OUAFlDER
,.
ANALOG
IN?UT
1.
NOTE:
5-40
Digital gnd. indicated by
V
Analog gnd. indicated by
'*'
FAIRCHILD • 9650
TYPICAL APPLICATIONS (Cont'd)
12-BIT AID CONVERTER
A
1/39003
1/49002
II
'Tr..749002
1/39003
?/41 I
002
I I f
D
E
A,
AD
6
E
A,
D
AD
8
9334
1
A,
9334
A:
4
C
5
6
7
CD'
2
3
56
4
V
9
r
~
_ _ M58
lS8
,
4
3
2
7
9llS0-3C
1211
6~
,,51
" "
,
w-
3
2
7
4
12'1
'D~
"
68-
9650-3C
5~
" "
r-- ,
,
3
2
-7
'w I - -
,,51
6~
9650-3C
8
1211
" "
~-+---+--~--r--+---+~+-~~--~---r--r--+-----+--+----"V
,
" " wRW R,
R" R"
8D'
-
4D'
'Ok
10k
R20
8
7
'"
VIe!
C
4
2
1
RS
R4
R3
RZ
Rj
80k
40k
20k
10k
80 k
40 k
20 k
10k
Rn
1k
13.5k
5k
"
3~6
3
Rs
" "
FUllSCALE
ADJ.
5
R7
R"
"
6
RS
R14
'"
21
22
51.12
W'Jt~?:'"
051'F::!:
,02 ~F
1'"
'--------i----------------------------------------------------~o tNNp~~OG
NOTE: Digital gnd. indicated by
Analog gnd. indicated by
5-41
V
*
FAIRCHILD • 9650
TYPICAL APPLICATIONS (Cont'd)
12-BIT D/A CONVERTER
' " , l S = B - - - - - - - - - - - - - O I G I T A L INPUTS-------------IVI~c,fj\
8 12
8 11
810
89
B8
? ? ? ?
-L
'61
3
2
T61
4
96503C
13
1211
85
3
2
I---
84
155~
1211
6Ro-
r--
8,
3
4
lO-
9
C-- 7
6""?
96501C
8
155~_
11
13
82
2
161
4
9650-2C
83
L ? ? ? ?
.5 V
101--7
6R,.
14
86
>5V
10
7
87
-L ? ? ? ?
,5V
1211
11
13
15
5J
15V
12
8"
80<
11
10
Rl1
40<
8
9
810
2"
R9
10k
7
6
24
5
8 20
8 ,9
5l
6k
13
14
15
,
1
R6
85
8 ,3
R4
83
R,
8,
80<
40'
20k
10k
10k
80k
401(
7()k
10k
RIb
818
17
18
R'5
lk
"
;,35k
5k
15
3
4
87
AS FN 215 RESISTOR ARRAY
-
23
R8
1'14
14k
19 O U n ) [ R
-¥o
21
n
If''~
r--
=
5
frAlll
G
1
30
a ,.1
FULL SCALE [
AiJJ
&
Vref
3~6
2~;J
:
10k..t
0058F
5
3912
101
OUADtR
'm!1
:::
/Eno ADJ
2l
r--o
t
~5M"
~
sF
l,0 ,
2l
028F
TYPICAL DC TEST CIRCUIT
PReCISION
VOl fMLrEcIl
NOTES:
1.
Required resistor ratio tolerances of R, - R5 to test the various grades are as follows:
9650-1C, R5 to R2 to R1 - ±0.005%, R3 to R1 - ±0.01%, R4 to R1 - ±0.02%.
9650-2C, R5 to R2 to R 1 - ±0.025%, R3 to R 1 - ±0.05%, R4 to R 1 - ±0.1%.
9650-3C, R5 to R2 to R1 - ±0.1%,
R3 to R1 - ±0.2%, R4 to R1 - ±0.4%.
2. S1 closed and S2 open for output current (all Bits off) tests only.
5-42
LINE CIRCUITS
Line Drivers
J.LA1488
J.LA8T13
J.LA8T23
55/75110A
75112
75121
75123
75150
9612
9612A
9612E
9614
9616
9634
9636A
9638
Quad EIA RS-232C Line Driver .......................................... 6-3
Dual Single-Ended Line Driver .......................................... 6-7
Dual IBM 360/370 I/O Single-Ended Line Driver ........................ 6-10
Dual General-Purpose Line Driver ..................................... 6-13
Dual General-Purpose Line Driver ..................................... 6-13
Dual Single-Ended Line Driver .......................................... 6-7
Dual IBM 360/370 I/O Single-Ended Line Driver ........................ 6-10
Dual EIA RS-232C/MIL-STD-188C Line Driver .......................... 6-18
Dual Differential Line Driver ........................................... 6-22
Dual Differential Line Driver ........................................... 6-22
Dual Differential Line Driver ........................................... 6-22
Dual Differential Line Driver .......................................... , 6-26
Triple EIA RS-232C/MIL-STD-188C Line Driver ......................... 6-30
Dual 3-State EIA RS-422 Differential Driver ............................ 6-33
Dual Programmable Slew Rate EIA RS-423 Line Driver ................. 6-36
Dual EIA RS-422 High-Speed Differential Line Driver ................... 6-40
Line Receivers
J.LA1489
J.LA1489A
J.LA8T14
J.LA8T24
55175107A
55/75107B
55/75108A
55/75108B
55/75122
75124
75154
9613
9615
9617
9622
9627
9637A
Quad EIA RS-232C Line Driver ........................................
Quad EIA RS-232C Line Driver ........................................
Triple Line Receiver ..................................................
Triple IBM 360/370 I/O Line Receiver ..................................
Dual General-Purpose Line Receiver ...................................
Dual General-Purpose Line Receiver ...................................
Dual General-Purpose Line Receiver .................................. ,
Dual General-Purpose Line Receiver ...................................
Triple Line Receiver ..................................................
Triple IBM 360/370 I/O Line Receiver ..................................
Quad EIA RS-232C Line Receiver ..................................... ,
Dual Differential Line Receiver ....................................... ,
Dual Differential Li ne Receiver ........................................
Triple EIA RS-232C Line Receiver .....................................
Dual Line Receiver ....................................................
Dual EIA RS-232C/MIL-STD-188C Line Receiver .......................
Dual EIA RS-422/423 Differential Line Receiver .................... , ....
6-43
6-43
6-47
6-50
6-53
6-53
6-53
6-53
6-47
6-50
6-60
6-65
6-69
6-74
6-76
6-80
6-84
Transceivers
J.LA8T26A
J.LA8T28
9640 (26S10)
9641 (26S 11 )
9642
Quad
Quad
Quad
Quad
Quad
6-87
6-87
6-94
6-94
6-94
3-State Inverting Bus Transceiver ................................
3-State Non-Inverting Bus Transceiver ...........................
General-Purpose Bus Transceiver ...............................
General-Purpose Bus Transceiver ...............................
General-Purpose Bus Transceiver with Hysteresis ................
IJA1488
QUAD LINE DRIVER
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The jJA 1488 is an EIA RS-232C specified Quad Line
Driver. This device is used to interface data terminals with data communications equipment. The jJA 1488 is a pin-for-pin replacement of the MC1488.
•
•
•
•
CURRENT LIMITED OUTPUT - ± 10 rnA TYP
POWER-OFF SOURCE IMPEDANCE - 300 n MIN
SIMPLE SLEW RATE CONTROL WITH EXTERNAL CAPACITOR
FLEXIBLE OPERATING SUPPLY RANGE
Vee
ABSOLUTE MAXIMUM RATINGS (at 25°C unless otherwise noted)
Power Supply Voltages
VCC+
VCCInput Voltage Range (VIR)
Output Signal Voltage
Continuous Total Power Dissipation (Note 1)
Operating Temperature Range
Pin Temperature
Hermetic DIP (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
CONNECTION DIAGRAM
14-PIN DIP
(TOP VIEWI
PACKAGE OUTLINE 6A 9A
PACKAGE CODE
D
P
IN D1
OUT A
IN D2
IN B1
+15 V
-15 V
-15VDCto+7.0VDC
±15 V DC
800 mW
ooC to 70°C
-65°C to +150°C
300°C
260°C
IN Cl
OUT B
IN C2
GND
14o-----~--------------~----~--__.
INPUTS
6.2 k
\
I
V"""""""T\.'''- - - - ,
300
~--""",+-_""-"'¥r----o OUTPUT
PINS 5, 10, 13
PINS 6, B, 11 OR 3
7k
70
Vcc- 1 o---------------~~--+---------~~
6-3
OUT C
ORDER INFORMATION
TYPE
PART NO.
JlA1488
JlA1488DC
JlA1488
JlA1488PC
CIRCUIT SCHEMATIC (1/4 OF CIRCUIT SHOWN)
8.2 k
OUT D
IN 82
Note l' Above 60°C ambient temperatures, derate linearly at 8.3 mW;oC.
Vcc+
Vee!
IN A
II
FAIRCHILD.IlA1488
ELECTRICAL CHARACTERISTICS: VCC+ = +9.0 V ± 1%, VCC- = -9.0 V ± 1%, TA = 0 to +70 oC, unless otherwise noted.
SYMBOL
CHARACTER ISTICS
CONDITIONS
FIG.
MIN
TYP
MAX
1.0
1.6
mA
10
IlA
IlL
Input LOW Current
VIL =0
1
IIH
Input HIGH Current
VIH = 5.0 V
1
VIL = 0:8 V, RL = 3.0 kO
VCC+ = +9.0 V, VCC- = -9.0 V
2
+6.0
+7.0
VIL = 0.8 V, RL = 3.0 kO
VCC+ = +13.2 V, VCC- = -13.2 V
2
+9.0
+10.5
VIH = 1.9 V, RL = 3.0 kO
VCC+ = +9.0 V, VCC- = -9.0 V
2
-6.0
-7.0
VIH = 1.9 V, RL = 3.0 kO
VCC+ = +13.2 V, VCC- = -13.2 V
2
-9.0
-10.5
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
UNITS
V
V
10S+
Positive Output Short-Circuit Current
VIL = 0.8 V (Note 1)
3
+6.0
+10
+12
mA
10S-
Negative Output Short-Circuit Current
IVIH = 1.9 V (Note 1)
3
-6.0
-10
-12
mA
ROUT
Output Resistance
VCC+ = VCC- = 0 V, Vo = ±2.0 V
4
300
Positive Supply Current
RL = 00
VIH = 1.9 V, VCC+ = +9.0 V
VIL = 0:8 V, VCC- = +9.0 V
VIH = 1.9 V, VCC+ = +12 V
VIL = 0.8 V, VCC+ = +12 V
VIH = 1.9 V, VCC+ = +15 V
VIL = 0.8 V, VCC+ = +15 V
+15
+4.5
+19
+5.5
+20
+6.0
+25
+7.0
+34
+12
-13
ICC-
Negative Supply Current
RL = 00
VIH = 1.9 V, VCC- = -9.0 V
VIL = 0.8 V, VCC- = -9.0 V
VIH = 1.9 V, VCC- = -12 V
VIL = 0.8 V, VCC- = -12 V
VIH = 1.9 V, VCC- = -15 V
VIL ~ 0.8 V, VCC- = -15 V
-17
-15
-23
-15
-34
-2.5
mA
IlA
mA
IlA
mA
mA
Pc
Power Consumption
VCC+
VCC+
333
576
mW
TYP
MAX
UNITS
ICC+
5
°
-18
5
= 9.0 V, VCC- = -9.0 V
= 12 V, VCC- = -12 V
mA
AC CHARACTERISTICS: VCC+ = +9.0 V ± 1%, VCC- = -9.0 V ± 1%, TA = 25°C
SYMBOL
CHARACTER ISTICS
CONDITION
FIG.
MIN
tpLH
tpHL
Propagation Delay Time
RL
= 3.0 kO,
CL
=
15 pF
6
220
70
350
175
ns
tf
tr
Fall Time
Rise Time
RL
= 3.0 kO,
CL
=
15 pF
6
70
55
75
100
ns
NOTE 1: Maximum Package Power Dissipation may be exceeded jf all outputs are shorted simultaneously.
6-4
FAIRCHILD. JlA 1488
TYPICAL CHARACTERISTICS
TA = +25°C unless otherwise noted
TRANSFER CHARACTERISTICS
AS A FUNCTION OF
POWER SUPPLY VOLTAGE
SHORT CIRCUIT OUTPUT
CURRENT AS A FUNCTION
OF TEMPERATURE
'"E
,
>
6.0 -
w
"~
o
>
0
>-
~
::>
0_ 6 . 0
-12
Vee
+9V
Vee
+ 6 V
~
a:
I--+-+----l-+-I--+-+--I
6.0
a:
::>
u
V':~ V~CC+~_t--+--1
~
I I
>::>
V~Ttti:::::t:_::::t:j
ttt 1'
o
>:;
0~-1
u
a:
U -6.0
kO
o
-12 L-~~~_L--L_L-~_~~
-75
-25
0
25
75
125
INPUT VOLTAGE - V
TEMPERATURE - °C
OUTPUT SLEW RATE
AS A FUNCTION OF
LOAD CAPACITANCE
1 000
'is
~
'"
L......L........J.I_L......L...II.....J.I_,---,-I-,--,--,
o
0.4
0.8
1.2
1.6
2.0
-
Vcc- "'" -9.0V
>a:
20
r-1-nr-,,\-rrrr-''-nT-,-,--rrr-,
OUTPUT VOLTAGE AND CURRENT
LIMITING CHARACTERISTICS
12
[\-.. ........
-r--..,
\
I
4.0
~
a:
a:
0
>-
a
\
\
-4.0
\
>-
::>
eo
1.9V
6 -12
\
'\..
'OS
VOUT
\
~ I-0.8 V I
T Vee'" ±9 v -=-
V'N
-20
1.0
10
100
10,000
1000
-16
-8.0
8.0
OUTPUT VOLTAGE - V
CAPACITANCE - pF
MAXIMUM OPERATING TEMPERATURE
AS A FUNCTION OF
POWER SUPPLY VOLTAGE
>,
f---
113 kO
4.0
7
0
-75
,- -
1--
I-1
-=-
~. VC'r-25
0
25
TEMPERATURE - °C
6-5
7.
125
16
I
FAIRCHILD. pA1488
DC TEST CIRCUITS
Fig. 1.
Input Current
Fig. 2.
Output Voltage
·9 V -9 V
3
10
3k
VOH
12
'---.:---1
13
12
11
10.8 V
Fig. 3.
Output Short-Circuit Current
Fig. 4.
Output Resistance (Power-off)
VCCt Vcc-
1·1.9 V
I
'os-
VOUT
±2 Vdc
lOSt
12
10
L----.7~..J
+0.8 V
Fig. 5.
Power-Supply Currents
Fig. 6.
AC Test Circuit and Voltage Waveform
»------?-------1r------o VOUT
V'N
I-=-
3k
I
+1.9 V
V'H
15PF
Cl
14
,3V,-_ _"""",
11.5V-j-
." ---,;; I
7
VOUT
V'L
12
t
)
-E--:
t :-:-:H
------ 0
50'\
tf
'O.BV
tr and tf are measured 10% to 90%
Vcc·-
6-6
tr
v
jLA8T13 • 55121 • 75121
DUAL SINGLE-ENDED LINE DRIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The /lA8T13/55121/75121 Dual Line Drivers are designed for driving
50 .n to 500 n coaxial cable, strip line, or twisted pair transmission lines. All inputs are TTL or DTL
CONNECTION DIAGRAM
16-PIN
(TOP VIEW)
compatible and the emitter-follower outputs enable two or more drivers to operate on the same line
in parity line applications.
For a dual line driver to meet the IBM System/360 I/O Interface Specification, see 75123 or 8T23
data sheets.
•
HIGH OUTPUT DRIVE CAPABILITY
•
•
•
•
HIGH SPEED
INPUT CLAMP DIODES
SINGLE 5 V SUPPLY OPERATION
SHORT CIRCUIT PROTECTED
ABSOLUTE MAXIMUM RATINGS
Input Voltage (Note 1)
Output Voltage (Note 1)
Supply Voltage (Note 1)
PACKAGE OUTLINES 6B 9B
PACKAGE CODES D
P
+6.0 V
+6.0 V
+6.0 V
_55°C to +125°C
Storage Temperature Range
Operating Temperature Range
IN Al
vee
IN A2
IN B6
IN A3
IN 85
INA4
IN 84
IN A5
IN 83
IN A6
IN B2
OUT A
IN B1
GND
OUT B
_55°C to +125°C
O°C to +70°C
Military (55121, /lA8T13DM)
Commercial (75121)
Pin Temperatures
300°C
260°C
800mW
Hermetic DIP (Soldering, 60 5)
Molded DIP (Soldering, lOs)
Internal Power Dissipation (Note 2)
NOTES:
1. Voltages are with respect to the ground pin (pin 8)
2.
For He~metic DIP and M~lded DIP rating applies to ambient temperatures up to 60°C, above 60°C
ORDER INFORMATION
TYPE
PART NO.
ILA8T13/55121DM
/lA8T13/75121DC
/lA8T13/75121PC
J.LA8T13 or 55121
/lA8T13 or 75121
/lA8T13 or 75121
derate linearly at 8.3 mW/ C.
EQUIVALENT CIRCUIT (For Each Driver)
55/75121 FUNCTION TABLE
1.4 k
360n.
INPUTS
H
2
H
X
X
1
5
6
H
H
X
X
H
X
X
H
H
H
All Other Inputs
Combinations
7(9)
V OUT
2k
5k
6-7
3k
OUTPUT
4
3
L
I
FAIRCHILD • MA8T13 • 55121 .75121
55121,75121 RECOMENDED OPERATING CONDITIONS
Supply Voltage, V CC
MIN
TYP
MAX
4.75
5
5.25
V
-75
mA
-55
125
°c
0
70
°c
Output HIGH Current, 10H
Operating Ambient Temperature, T A 155121 /i,AST13
\75121/I'AST13
ELECTRICAL CHARACTERISTICS: V CC+
= 4.75 V
to 5.25 V, Ratings apply over recommended temperature range unless noted.
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIN
Input Clamp Voltage
VCC - 5.0 V, liN - -12 mA
V(BRlI
Input Breakdown Voltage
VCC
Output HIGH Voltage
VIH
VOH
UNITS
MIN
TYP
MAX
= 5.0 V,IIN = 10 mA
=
2.0 V, 10H
=
-75 mA
UNITS
V
2.0
O.S
V
-1.5
V
5.5
V
2.4
V
(Note 3)
VCC
Output HIGH Current
= 5.0 V, VIH = 4.5
V
VOH = 2.0 V, TA = 25°C
-100
-250
mA
-SO~
I'A
500
I'A
(Note 3)
VIL = O.S V, VOL = 0.4 V
Output LOW Current
(Note 3)
10UT(off)
Off·State Ou'tput Current
VCC - 0, VOUT - 3.0 V
Input HIGH Current
VtN - 4.5 V
-0.1
Input LOW Current
Short·Circuit Output Current
lOS
ICCH
Supply Current, Outputs HIGH
ICCL
Supply Current, Outputs LOW
VCC
= 5.0 V, TA = 25°C
V CC
=
40
I'A
-1.6
mA
-30
mA
2S
mA
60
mA
5.25 V, All inputs at 2.0 V
Outputs open
V CC
=
5.25 V, All inputs at O.S V
Outputs open
AC CHARACTERISTICS: V CC
=
5.0 V, T A
=
25°C.
CHARACTER ISTICS
SYMBOL
Propagation Delay Time
LOW·to-HIGH Output
Propagation Delay Time
HIGH-to-LOW Output
Propagation Delay Time
LOW-to-H I G H Output
Propagation Delay Time
HIGH-to-LOW Output
TEST CONDITIONS
RL
MIN
TYP
MAX
11
20
S.O
20
22
50
20
50
= 37 n, CL = 15 pF
ns
See Test Circuit
RL
= 37 n,cL = 1000pF
See Test Circuit
UNITS
ns
NOTE:
4. The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the function table
for the desired output.
AC CHARACTERISTICS
TEST CIRCUIT
INPUT
I
PULSE
GENERATOR
VOLTAGE WAVEFORMS
3.0 V
III-_~_--I
INPUT PULSE:
Amplitude = 2.6 V
tpw = 40 ns (50% Duty Cycle)
"'I neludes probe and jig capacitance.
6-8
FAIRCHILD. ILA8T13 .55121 .75121
TYPICAL PERFORMANCE CURVE FOR 55121/75121/flA8T13
OUTPUT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE
250
TA=25'C
Vee
--....
5.0 V
=
200
~
z
"-
150
'\
\
~
1\
~
U
~
~
100
\
~
~
0
50
t--
o
o
0.5
1,0
-
\
1.5
20
2.5
3.0
3.5
OUTPUT VOL T AGE - VOLTS
I
TYPICAL APPLICATIONS
75
I
\
75n
-
\
I
1
n
PARTY LINE (2 DRIVERS, 3 RECEIVERS)
I
\
-
75
n
1/355175122/8T14
COAX
~
\
I
1
I
\
\
I
I
NOTE: For party line operation, termination of each physical end of the line is recommended.
SIMPLEX OPERATION (1 DRIVER)
50n
NOTE: For simplex operation, the line should be terminated only at the distant receiver site.
6-9
JLA8T23 • 75123
DUAL SINGLE-ENDED LINE DRIVER
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCR'IPTION - The )lA8T23 175123 Dual Line Driver meets the requirements of the
IBM System/360 I/O Interface Specification for interface drivers, Inputs are TTLlDTL compatible,
Logic has been incorporated to ensure that no spurious noise is generated on the transmission line
during the power-up and power-down sequence. The outputs are protected from short circuits and
have lIncommitteed emitter outputs which allows DOT-OR logic to be performed in party line data
bus applications.
•
•
•
•
•
lOUT = 59,3 rnA AT 3,11 V
UNCOMMITTED EMITTER OUTPUTS FOR PARTY LINE/WIRED-OR APPLICATIONS
SHORT CIRCUIT PROTECTION
SINGLE 5,0 V SUPPLY OPERATION
AND-OR LOGIC CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Input Voltage (Note 1)
Output Voltage (Note 1)
Supply Voltage (Note 1)
IN A1
Vee
IN A2
IN B6
IN A3
IN B5
FUNCTION TABLE
IN A4
IN B4
INPUTS
IN AS
IN B3
OUTPUT
+5,5 V
+7,0 V
+7,0 V
-65°C to +150°C
1
2
3
4
5
6
H
H
H
H
X
X
O°C to 70°C
X
X
X
X
H
H
Storage Temperature Range
Operating Temperature Range
Pin Temperatures s
Hermetic DIP (Soldering, 60 s)
Molded DIP (Soldering, lOs)
I nternal Power Dissipation (Note 2)
ALL OTHER INPUT
300°C
260°C
800mW
COMBINATIONS
IN A6
IN B2
H
OUT A
IN B1
H
GND
OUT B
L
ORDER INFORMATION
H = HIGH
L = LOW
TYPE
X = Don't Care
PART NO,
)lA8T23 or 75123
)lA8T23 or 75123
NOTES:
1.
2.
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 6B 9B
PACKAGE CODES D P
I'A8T23/75123DC
)lA8T23/75123PC
Voltages are with respect to the ground pin (pin 8).
Rating applies to ambient temperatures up to 60°C. Above 60°C derate linearly at 8.3 mW;o C.
EQUIVALENT CIRCUIT (FOR EACH DRIVER)
vcc~------------------------t---~--------------~--------~----~--------------------------~~----~
4k
4 k
1k
360 S2
35!2
1.4 k
15H
INPUTS
1I 101 ~--t-------------..J
2(11)
3(12)
51 14)
VOUT
~. . .- -__,.
719)
1k
2k
5k
GNO~--'---------------~~--~~--------------~--~--~~---4----~--~~--~----------~
6-10
3k
FAIRCHILD • ILA8T23175123
RECOMMENOED OPERATING CONDITIONS
Supply Voltage, VCC
MIN
TYP
MAX
4.75
5.0
5.25
V
-75
mA
Output HIGH Current, 10H
o
Operating Ambient Temperature, T A
UNITS
70
ELECTRICAL CHARACTERISTICS: VCC ~ 4.75 V to 5.25 V (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN
CONDITIONS
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VI
Input Clamp Voltage
VCC
V(BR)I
Input Breakdown Voltage
VCC - 5.0 V,IIN - 10 mA
VOH
Output HIGH Voltage
TYP
MAX
V
2.0
0.8
~
5.0 V, liN
~
-1.5
-12 mA
ITA - 25°C
10H ~ -59.3 mA, See Note 31 TA
VCC
= 5.0 V, VIH
~
4.5 V, VOH
~
3.11
= O°C to
2.0 V,
10H
Output HIGH Current
VOL
Output LOW Voltage
10UT(off)
Off-State Output Current
= 0.8 V, 10L - -240 /J.A, See Note 3
VCC = 0, VOUT ~ 3.0 V
-250
-100
T A ~ 25" C, See Note 3
0.15
VIL
IIH
Input HIGH Current
VIN-4.5V
IlL
Input LOW Current
VIN
= 0.4
40
-0.1
V
V
V
2.9
70°C
V
V
5.5
VCC - 5.0 V, VIH - 2.0 V,
UNITS
mA
V
/J.A
40
/J.A
-1.6
mA
lOS
Short-Circuit Output Current
VCC ~ 5.0 V, TA - 25°C
-30
mA
ICCH
Supply Current, Outputs HIGH
VCC
~
5.25 V, All Inputs at 2.0 V, Outputs Open
28
mA
ICCL
Supply Current, Outputs LOW
VCC
~
5.25 V, All Inputs at 0.8 V, Outputs Open
60
mA
AC CHARACTERISTICS: VCC
= 5.0 V, TA
~ 25"C
CHARACTER ISTICS
TYP
MAX
12
20
See Test Circuit
12
20
Propagation Delay Time, Output LOW to HIGH
RL -50n, CL -100pF
20
35
Propagation Delay Time, Output HIGH to LOW
See Test Circuit
15
25
SYMBOL
CONDITIONS
tPLH
Propagation Delay Time, Output LOW to HIGH
RL
tpHL
Propagation Delay Time, Output HIGH to LOW
tPLH
tPHL
3.
~
50 n,cL
~
MIN
15 pF
UNITS
ns
ns
The output voltage and current limits are guaranteed for any appropriate combination of HIGH and LOW inputs specified by the function
table for the desired output.
AC CHARACTERISTICS
TEST CIRCUIT
WAVEFORMS
l_ _ tpw _ _ _ _1
INPUT
3.0 V
INPUT
--.111_tf
I
90%~1
1:
0%
1.5
I
v
I:
_111_"
_ __
10_%_
-
:
1.5V
10%
1
1
'---------
I~'PLH~V!\
I
OUTPUT
INPUT PULSE:
Amplitude"" 2.6 V
= 50 ns (50% Duty Cycle)
t r "" tf ~5 ns (10% and 90% measurement points)
tpw
15VT: 1\'5V
I-'PHL -I
*' neludes probe and jig capacitance
6-11
'------
II
FAIRCHILD • ~A8T23/75123
TYPICAL PERFORMANCE CURVE FOR 75123/,uA8T23
OUTPUT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE
I I
V CC =5.0 V
300
T A =25°C-
"E
I
e-
~
t---rk
PART NO.
75150DC
75150PC
8-PIN DIP
(TOP VIEW)
PACKAGE OUTLINE 9T, 6T
STROBE
TO OTHER
LINE DRIVER
IN A2
GND
ORDER INFORMATION
TO OTHER
LINE DRIVER
TYPE
75150
75150
Vee
Component values shown are nominal.
6-18
PART NO.
75150RC
75150TC
FAIRCHILD. 75150
ABSOLUTE MAXIMUM RATINGS (over operating free-air temperature range, unless otherwise noted).
15
-15
15
±25
Supply Voltage Vee+ (See Note 1)
Supply Voltage Vee- (See Note 1)
Input Voltage (See Note 1)
Applied Output Voltage (See Note 1)
Operating Ampient Temperature Range
Storage Temperature Range
V
V
V
V
ooe to 70 e
0
-65°e to 150 0 e
Note 1: Voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage VCC+
10.8
12
13.2
V
Supply Voltage VCC-
-10.8
-12
-13.2
V
5.5
V
0
Input Voltage, VI
Applied Output Voltage, Vo
0
Operating Ambient Temperature, TA
±15
V
70
°C
II
ELECTRICAL CHARACTERISTICS' Over Recommended Operating Free-Air Temperature Range (unless otherwise noted)
SYMBOL
CHARACTERISTICS
TEST
FIGURE
V IH
Input HIGH Voltage
1
VIL
Input LOW Voltage
2
MIN
TEST CONDITIONS
TYP'
MAX
(See Note 2)
V
2.0
0.8
V OH
Output HIGH Voltage
2
VCC+ = 10.8 V,
V IL = 0.8 V,
VOL
Output L.OW Voltage
1
VCC+ = 10.8 V,
VIH - 2 V,
IIH
Input HIGH Current
3
Vec- = -13.2 V,
VCC- = -13.2 V,
RL = 3 kO to 7 kO
VCC- = -10.8 V,
RL = 3 kO to 7 kO
5.0
UNITS
8.0
V
-8.0
-5.0
Data Input
1.0
10
Strobe Input
2.0
20
Data Input
-1.0
-1.6
Strobe Input
-2.0
-3.2
VCC+ = 13.2 V,
V
V
IlA
VI = 2.4 V
VCC+ = 13.2 V,
IlL
Input LOW Current
3
mA
VCC- = -13.2 V,
VI = 0.4 V
2.0
Va = 25 V
lOS
Short-Circuit Output Current
4
Va = -25 V
Vee- = --13.2 V
Va = 0 V, VI = 3 V
15
aV
-15
Va = 0 V, VI =
leCH+
Supply Current from V CC +' Output HIGH
leCH-
Supply Current from V ec -, Output HIGH
leeL+
Supply Current from Vee+- Output LOW
leeL-
Supply Current from V ee -, Output LOW
5
-3.0
VCC+ = 13.2 V,
VCC+ = 13.2 V,
VCC- = -13.2 V,
VI = 3 V,
RL = 3 kO,
TA = 25°C
5
VCC+ = 13.2 V,
Vee- = -13.2 V,
VI = 3 V,
RL = 3 kO,
TA = 25°C
mA
10
22
mA
-1.0
-10
mA
8.0
17
mA
-9.0
-20
mA
The algebraic convention where the most~positlve (least-negative) limit is designated as maximum is used in this data sheet for logiC levels only,
e.g .. when -5 V is the maximum, the tYPical value is a more negative voltage.
*AII typical values are at VCC+ = 12 V, VCC- -= --12 V, TA = 25°C.
NOTE 2:
6-19
FAIRCHILD. 75150
AC CHARACTERISTICS: VCC+ ~ 12 V, VCC_ ~ -12 V, TA ~ 25°C.
SYMBOL
TEST
CHARACTER ISTICS
FIGURE
TEST CONDITIONS
2500 pF.
0.2
1.4
2.0
/1S
~
3 kG to 7 kG
0.2
1.5
2.0
/1S
CL
~
15 pF.
tTHL
tTHL
Transition Time. Output LOW to HIGH
tTHL
Transition Time. Output HIGH to LOW
RL ~ 7 kG
tpLH
Propagation Delay Time. Output LOW to HIGH
CL
tpHL
Propagation Delay Time, Output HIGH to LOW
~
15 pF.
RL ~ 7 kG
40
ns
20
ns
60
ns
45
ns
CHARACTERISTICS MEASUREMENT INFORMATION
DC TEST CIRCUITS'
VIH
Each input is tested separately.
IH
~
VI-
_
J
SEE
NOTE
IlL
Fig. 4.
NOTE: When testing 'IH' the other input is at 3 V; when testing
'L' the other input is open.
Fig. 5.
lOS
lOS is tested for both input conditions at each
of the specified output conditions.
ICCH+' ICCH-' ICCL+' ICCL-
*Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
6-20
UNITS
~
Transition Time. Output HIGH to LOW
6
MAX
CL
Transition Time. Output LOW to HIGH
6
TYP
RL
tTLH
6
MIN
FAIRCHILD. 75150
CHARACTERISTICS MEASUREMENT INFORMATION (Cant'd)
SWITCHING CHARACTERISTICS
TEST CIRCUIT
~
l
~3V
:1~_vr~
___.....,
PULSE,l
GENERATOR
(SEE NOTE
~
L
d:
1----1
,
1
All
-
I
OUTPUT
RL l C L
(SEE NOTE
~
BI
-=
VOLTAGE WAVEFORMS
,;; 10
ns-l-l
I l'
l
~90%
INPUT
I
l-l-,;; 10 ns
__ - - - - - 3 V
___~=~I=_tI
90%
1.5V
I
1.5 V
, ,
_--,1.;;.0~",,"l'
:
I
~';.;O;.;%:...._ _ _ _ _ 0
V
l~5ojJ.s---~"'1
I.... tpHL~
1..- tPlH---'1
:
------~,
I
I
I
I
I
+3V
I
I
+} V
,
t I l'
I
r'1;..-...;3;..V.;...._-:-_-3::....:.V.JF - J... - - -
OUTPUT
tTHL ~_
NOTES:
A.
The pulse generator has the following characteristics: duty cycle
B.
CL includes probe and jig capacitance.
~
----j..j
tTLH
50%, ZOUT = 50
n.
TYPICAL ELECTRICAL CHARACTERISTICS
OUTPUT CURRENT VERSUS
APPLIED OUTPUT VOLTAGE
15
"E
I
~
VCC+ = 12 V
VCC- = -12 V
TA = 25'C
10
I-
Z
w
5.0
::>
0
«
«
()
l-
::>
Q.
I-
::>
0
I
-5.0
Vl=2~
f
I
:=/~
-
I -I - ~
I-
-RL=7kO
= 3 kO
. . . . Rl
-10
9
-15
-
~
vl-=O.4 V
I
-20
-25-20-15 -10 -5.0 0
I
5.0 10
15
20 25
Vo - APPLlEO OUTPUT VOLTAGE - V
Figure 7
6-21
VOH
VOL
II
9612 • 9612A • 9612E
DUAL DIFFERENTIAL LINE DRIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The 9612 Dual Differential Line Driver is designed specifically to drive
single ended or differential, back matched or terminated transmission lines. The outputs are similar to
totem pole TTL outputs, with active pull-up and pull-down, for use in simplex or simplex distribution
bus systems. The devices feature a short circuit protected active pull-up. The inputs and outputs have
clamp diodes to minimize the effect of line transients. The active pull-up output offers low output
impedance allowing back matching or parallel termination of the line. The 9612E and 9612A are
specified to drive 50
n
CONNECTION DIAGRAM
8-PIN MINIDIP
(TOP VIEW)
PACKAGE OUTLINE 9T 6T
PACKAGE CODE T R
transmission line at high speed while guaranteeing a maximum skew between
outputs of less than 3.5 ns for application requiring high performance line drivers. (9613 is the
functional complement).
9612/9612A/9612E
• SINGLE5VSUPPLY
• TTL COMPATIBLE INPUTS
• OUTPUT SHORT CIRCUIT PROTECTION
• INPUT CLAMP DIODES
• OUTPUT CLAMP DIODES FOR TERMINATION
OF LINE TRANSIENTS
• COMPLEMENTARY OUTPUTS
9612A/9612E
GUARANTEED MAXIMUM OUTPUT
SKEW
HIGH OUTPUT DRIVE CAPABILITY
FOR 50 n TRANSMISSION LINES
•
•
OUTA"
Vcc
OUT A
OUTS
INA
OUT B
GNO
IN B
ABSOLUTE MAXIMUM RATINGS
-65°C to +150o e
Storage Temperature
Operating Temperature
-55°C to +125°C
oOe to +70°C
9612A
9612,9612E
Vec
VIN
Internal Power Dissipation (Note 1)
ORDER INFORMATION
TYPE
9612
9612E
9612TC
9612ETC
800mW
9612A
9612
9612E
9612ARM
9612RC
9612ERC
Pin Temperature (Soldering, 10 s)
Hermetic Mini DIP (Soldering, 60 s)
Molded Mini DIP (Soldering, 10 s)
300°C
260°C
NOTE:
1.
For the Hermetic Mini DIP and Molded Mini DIP derate above 30°C at 6.7 mW/C.
EQUIVALENT CIRCUIT (1/2 of 9612)
6(21
OUTPUTS
+--+-..-......---01 117
5(3)
r4GROUND
6-22
PART NO.
+7.0 V
-0.5 V to +5.5 V
FAIRCHILD. 9612 • 9612A • 9612E
ELECTRICAL CHARACTERISTICS: VCC~ 5.0 V :': 10%, T A~ -55°C to +125°C, unless otherwise specified
LIMITS
SYMBOL
CHARACTERISTICS
CONDITIONS
UNITS
MIN
TYP
MAX
200
400
VOL
Output LOW Vol tage
10L -40 mA
VOLC
Clamped Output LOW Voltage
10LC - -40 mA
-1.5
-0.8
VOH
OutPut HIGH Voltage
10H - -40 mA
2.0
2.75
ISC
Output Short Circuit Current
VOUT - OV
-140
-77
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IlL
Input LOW Current
VIL~Oo4V
IIH
Input HIGH Current
IR
Input Reverse Current
VIH-204V
VR-4.5V
VCD
Input Clamp Diode Voltage
VCC - 4.75 V, IIC - -12 mA, T = 25°C
ICC
Supply Current
Inputs - 0 V , T = 25u C
'max
Max. Supply Current
Inputs - 0 V, V max
V
V
-42
0.8
V
mA
-1.6
7.0V, T-25u C
mA
V
2.0
-1.5
mV
40
!LA
1.0
mA
42
50
mA
59
70
mA
V
-0.8
ELECTRICAL CHARACTERISTICS: VCC= 5.0 V :':5%, TA= OUCto 70°C, unless otherwise specified
LIMITS
SYMBOL
CHARACTERISTICS
CONDITIONS
9612
MIN
Output LOW Voltage
VOL
IOL = 40 mA
9612E
TYP
MAX
200
400
MIN
IOL = 50 mA (9612E only)
Clamped Output LOW Voltage
VOLC
-1.5
IOLC = -40mA
-0.8
10LC = -50 mA(9612E only)
204
2.75
-140
-77
UNITS
TYP
MAX
200
400
mV
250
400
mV
-1.5
-0.8
-1.5
-0.9
V
204
204
2.75
V
2.60
-140
-77
V
VOH
Output HIGH Voltage
10H = -40 mA
ISC
Output Short Circuit Current
VOUT = OV
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IlL
Input LOW Current
VIL-004V
IIH
Input HIGH Current
VIH=204V
40
40
!LA
IR
Input Reverse Current
VR=4.5V
1.0
1.0
mA
VCD
Input Clamp Diode Voltage
VCC - 4.75 V, IIC - -12 mA
ICC
Supply Current
Inputs = 0 V
42
50
42
50
mA
'max
Max. Supply Current
Inputs = 0 V, V max = 7.0 V
59
70
59
70
mA
IOH = -50 mA (9612E only)
-42
0.8
AC CHARACTERISTICS: TA = 25°C, VCC = 5.0 V, RL = 100
n
SYMBOL
CONDITIONS
2.0
2.0
-1.6
-1.6
-1.5
-0.8
-1.5
V
-55
mA
0.8
V
V
mA
-0.8
V
(Note 1)
LIMITS
CHARACTERISTICS
MIN
n
tPLH
Turn Off Time
RL = 100
tpHL
Turn On Time
CL';;15pF
ts
Output Skew
See Fig. 1
NOTE:
9612A19612E
9612
TYP
(Note 1)
MAX
MIN
TYP
UNITS
MAX
30
20
ns
30
20
ns
+3.5
ns
-3.5
1. R L must be noninductive.
I
AC CIRCUIT AND WAVEFORMS
'5(Oll
~~
8
:;;. 1171
'1 1±
lOon
1
-=
VOUT
CL <15pF
315)
VIN
0---.--0--1
51 U
'15.ov
5%
Your
loon
"
INPUT PULSE
Frequency = 2 MHz
Fig. 1
6-23
Amplitude = 3.0 ± 0.1 V
Pulse Width = 250 ±1 0 ns
tr = tf ,,;;;; 5.0 ns
•
FAIRCHILD. 9612 • 9612A • 9612E
TYPICAL PERFORMANCE CURVES
0
OUTPUT LOW CURRENT
AS A FUNCTION OF
OUTPUT LOW VOLTAGE
'A
~ ......
25°C
0
VCC~5.5V ~
VCC~5.0V
0
J
0
~
~
Vcc~
IOH
2.5
~
-4OmA
--
'r#'
VCC~4,5V
1/
/
0'
0.5
0.3
AMBIENT TEMPERATURE _oC
OUTPUT LOW VOLTAGE-V
SUPPL Y CURRENT
AS A FUNCTION OF
SUPPLY VOLTAGE
0
5.0V
II
i"-,......
/#
OUTPUT VOLTAGE
AS A FUNCTION OF
AMBIENT TEMPERATURE
OUTPUT HIGH CURRENT
AS A FUNCTION OF
OUTPUT HIGH VOLTAGE
SUPPLY CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE
_:r"'o
SUPPLY CURRENT
AS A FUNCTION OF
OPERATING FREQUENCY
Vee- SOV
INPUTS GROUNDED
/
0
/
0
/
0
0
V
c/
:::
......... 1-"
AMBIENT TEMPERATURE
PROPAGATION DELAY TIME
AS A FUNCTION OF
AMBIENT TEMPERATURE
0
Vcc~
CL ~.3OpF
-~-
TRANSFER CHARACTERISTICS
AS A FUNCTION OF
SUPPLY VOLTAGE
5.0V
,.01--"+"_W-l'I_'0"_'II-"G_"+'' '_U-l''_I-+--+-+-1
0
0
--J,) 'if)
01-- I-- f---j tpHL
0
TRANSFER CHARACTERISTICS
AS A FUNCTION OF
AMBIENT TEMPERATURE
OPERATING FREQUENCY - MHz
0
v~c ~ 5~OV
0i- +-
_oc
V ......
l"'-
~'"
/'
0
0
--
0
475V
I I I
I I J-.J---f::::::""vOUT@vcc
0
20
AMBIENT TEMPERATURE _oC
INPUT VOLTAGE _ V
6-24
I I
VLT JV ccl=5.2kv
11 T
VOUT@VCC
0
20
I I I
I
I
VOUT@VCC=525V
111
475V
FAIRCHILD. 9612 • 9612A • 9612E
,-----------------------------------------------------------------------------------------------TYPICAL APPLICATIONS
SIMPLEX BALANCED DIFFERENTIAL OPERATION
V
eelS
I
I~
----
1/29612
TWISTED PAIR
LINE
~
DATA~'
INPUT
II ~
1
_
ow
~O---OUT,'UT
I -7---1
~2
BrVee
I
----<10------1
JLr-------~SH~I~EL~D~O~R~e~O~M~MO~N~G~R~D~U~ND--CO~N-N~EC~T~IO-N-------,Jl
TYPICAL REFLECTION DIAGRAM
TA = 25"C
200 -VCC
=
5.0V
r
-+---/+
1I---1
1--l+------l1.---.+-I_--t--.l----l
I----t-----t-+-+I LLOW STATE OUTPUT
DEVICE
I
! 1001--4---+---+~/-+---+------l---+----t------l--11
CHARtCTERISTICS
~
~
a:
~
/
/
V
- OUTPUT DEVICE_
§2 -100 I-____l----hfr/--+- HIGH STATE
CHARACTERISTICS
-200
I---I--.-,It--t--t--t--t--t--r--If----l
-2.0
o
2.0
4.0
OUTPUT VOLTAGE - V
6-25
6.0
II
9614
DUAL DIFFERENTIAL LINE DRIVER
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The 9614 is a TTL compatible Dual Differential Line Driver. It is
designed to drive transmission lines either differentially or single-ended, back-matched or terminated.
The outputs are similar to TTL, with the active pull up and the pull down split and brought out to
adjacent pins. This allows multiplex operation (Wired-OR) at the driving site in either the single-ended
mode via the uncommitted collector, or in the differential mode by use of the active pull ups on one
side and the uncommitted collectors on the other (See Fig. 5). The active pull up is short circuit
protected and offers a low output impedance to allow back-matching. The two pairs of outputs are
complementary providing NAND and AND functions of the inputs, adding greater flexibility.
The input and output levels are TTL compatible with clamp diodes provided at both input and
output to handle line transients.
CONNECTION DIAGRAM
16-PIN DIP
(TOPVIEWI
PACKAGE OUTLINES 68 98 4L
PACKAGE CODES 0
P F
ACTIVE
• SINGLE5VOlTSUPPLY
• TTL COMPATIBLE INPUTS
• OUTPUT SHORT CI RCUIT PROTECTION
• INPUT CLAMP DIODES
• OUTPUT CLAMP DIODES FOR TERMINATION OF LINE TRANSIENTS
• COMPLEMENTARY OUTPUTS FOR NAND, AND OPERATION
• UNCOMMITTED COLLECTOR OUTPUTS FOR WIRED-OR APPLICATION
• MILITARY TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS (above which the uselullile may be impariedl
Storage Temperature Range
VCC Pin Potential to Ground Pin
Input Voltage
Voltage Supplied to Outputs (Open Collectorl
Pin Temperature
Hermetic DIP, Flatpak (Soldering, 60 sl
Molded DIP (Soldering, 10 sl
I nternal Power Dissipation (Note 11
Operating Temperature Range
Military (96141
Commercial (9614CI
NOTE:
1. For Herme~ic DIP rating applies to amb~ent temperatures ~p to 70o e, ~bove 700
at 8.3 mW/ C. For the Flatpak, derate IlOearly at 7.1 mWI C above 60 C.
Vee
PULL UP Al
. OUT A'1
-65°C to +15D o C
-0.7 V to +7.0 V
-0.5 V to +5.5 V
-0.5 V to +12 V
_55° C to +125° C
O°C to +70°C
OUT A2
OUT 82
ACTIVE
PULL UP A2
OUT 81
IN A1
ACTIVE
PULL UP 81
IN A2
IN 83
IN A3
IN 82
GND
IN 81
ORDER INFORMATION
PART NO,
TYPE
9614
9614DM
9614
9614FM
9614C
9614DC
9614C
9614PC
e derate linearly
EQUIVALENT CIRCUIT (1/2 96141
r-~-~~--~---1-""''''''r---~---~-''''''---'''''r--~--o16VCC
0,
ACTIVE
PULL UP 1 2 1 4 ) 0 - - -.......-
......- - '
OUTPUT 13 (3)0---~_,
9(5)g====~===l=~0
INPUTS 10(6)
11(7)
.:::t--=-:3I---+.,r-t-----------~
6-26
)
TOOTHEA
DRIVER
FAIRCHILD. 9614
9614
ELECTRICAL CHARACTERISTICS: V CC ~ 5.0 V ± 10%.
LIMITS
SYMBOL
CHARACTERISTICS
-55"C
Output LOW Voltage
VOL
VOH1
Output HIGH Voltage
ICEX
Output Short-Circuit Current
Output Leakage Current
IF
I nput Forward Current
IR
Input Reverse Current
VIL
Input LOW Voltage
MIN
400
VOH2
ISC
+25"C
MAX
MIN
200
Input HIGH Voltage
Clamped Output LOW Voltage
ICC
UNITS
CONDITIONS
MAX
MIN
400
400
mV
IOL ~ 40 mA
VCC~4.5V
2.4
3.2
2.4
V
IOH ~ -10 mAJ
2.0
2.0
2.6
2.0
V
IOH - -40 mAl
-40
-90
-120
10
100
200
-1.10
-1.60
-1.60
mA
VF - 0.4 V
VCC-5.5V
35
60
100
iJ.A
VR-4.5V
VCC-5.5V
1.3
0.8
0.8
V
VCC - 5.5 V
V
VCC ~ 4.5 V
0.8
VOLC
+125"C
MAX
2.4
-1.60
VIH
TYP
2.0
2.0
1.5
2.0
VCC ~ 4.5 V
mA
VOUT ~ 0.0 V
iJ.A
VCEX ~ 12.0 V VCC~5.5V
VCC - 5.5 V
'OLC - -40 mA VCC ~ 5.5 V
-0.8
-1.5
V
Supply Current
34
50
mA
Inputs
~
0 V
VCC~5.5V
Imax
Supply Current
46
65
mA
Inputs
~
0 V
V max
tpLH
Turn-Off Time
14
20
ns
CL
tpHL
Turn-On Time
18
20
ns
See Fig. 1
VM
VCD
I nput Clamp Diode Voltage
-1.0
-1.5
V
VCC~4.5V
IIC ~ -12 mA
~
~
7.0 V
VCC~5.0V
30 pI'
~
1.5 V
9614C
ELECTRICAL CHARACTERISTICS: V CC ~ 5.0 V ± 5%.
LIMITS
MIN
MAX
MIN
450
Output LOW Voltage
VOL
VOH1
+25°C
O°C
CHARACTERISTICS
SYMBOL
+70"C
TYP
MAX
200
450
~
MIN
mV
450
ISC
Output Short-Circuit Current
ICEX
Output Leakage Current
IF
I nput Forward Current
IR
I nput Reverse Current
VIL
I nput LOW Voltage
Input HIGH Voltage
Clamped Output LOW Voltage
ICC
4.75 V
3.2
2.4
V
IOH - -10 mAl
2.0
2.0
2.6
2.0
V
'OH ~ -40 mAl
-40
-90
-120
10
100
200
-1.10
-1.60
-1.60
35
60
100
1.3
0.8
0.8
V
VCC ~ 5.25 V
\I
VCC ~ 4.75 V
V
IOLC ~ -40 mA VCC ~ 5.25 V
0.8
VOLC
VCC
2.4
-1.60
VIH
IOL - 40 mA
2.4
Output HIGH Voltage
VOH2
CONDITIONS
UNITS
2.0
2.0
1.5
2.0
VCC ~ 4.75 V
VCC ~ 5.25 V
mA
VOUT -0.0 V
iJ.A
VCEX ~ 5.25 V VCC ~ 5.25 V
mA
VF
iJ.A
VR - 4.5 V
~
VCC ~ 5.25 V
0.45 V
VCC - 5.25 V
-0.8
-1.5
Supply Current
33
50
mA
Inputs - 0 V
Imax
Supply Current
46
70
mA
Inputs
tpLH
Turn-Off Time
14
30
ns
CL - 30 pF
VCC-5.0V
tpHL
Turn-On Time
18
30
ns
See Fig. 1
VM ~ 1.5 V
VCD
I nput Clamp Diode Voltage
-1.0
-1.5
V
VCC - 4.75 V
Ilc--12mA
AC TEST CIRCUIT AND WAVEFORMS
~_V"
_J:-+-,.':'
'00
INPUT PULSE
~
~
'"
1
/J
/-l
V
""'"'
r
t
OL
~T
,
VOOT
w
i
j"
I
VM
I
1
t"
VOUT (Al
INPUT PULSE
Frequency = 500 kHz
= 3.0 ±O.l V
± 10 ns
Pulse Width = 110
= t f ::; 5.0 ns
tt
6-27
VCC - 5.25
0 V
V max - 7.0 V
.1,--:'
1
1-1''--PL"--',"L~+- -I
Amplitude
Fig. 1
~
VM
•
FAIRCHILD. 9614
TYPrcAL ELECTRICAL CHARACTERISTICS
ACTIVE PULL UP
OUTPUT HIGH CURRENT
AS A FUNCTION OF
OUTPUT HIGH VOL TAGE
ACTIVE PULL DOWN
OUTPUT LOW CURRENT
AS A FUNCTION OF
OUTPUT LOW VOL TAGE
LOGIC LEVELS
AS A FUNCTION OF
AMBIENT TEMPERATUf\E
Vee o5.0V
VOH - NO LOAD
J
I
I--
I
I
:
!
I
I
I
I
~ --
I
I
I
I
!
I
hL~'C: J,,~.::
._-
i
OUTPUT lOW VDLTAGE-V
AMBIENT TEMPERATURE -'C
SUPPL Y CURRENT
AS A FUNCTION OF
SUPPL Y VOL TAGE
SUPPLY CURRENT
AS A FUNCTION OF
TEMPERATURE
~~~~~rO~E~
r-._-.-
.
~.
SUPPLY CURRENT
AS A FUNCTION OF
OPERATING FREQUENCY
-
- 1-.
--
·-f-
I-- -
1--'i-r-
5
-
--
-
~
--
I
-1
_1._
f- -
I
--
I
-f.- -f-
L+
-j
-
1+!
I
++
i--
i
--I-
--
~
I-
I
o
.-
il
I
01
FREQUENCY- MHz
AMBIENT TEMPERATURE-'C
TRANSFER CHARACTERISTICS
AS A FUNCTION OF
TEMPERATURE
VCC 5 .DV
'-- -- --- - -h:'A"_l~"C;'C~I---i
4.0
-4-tt1
n--
--
I
20
·00
I
I
i
5
PROPAGATION DELAY TIME
AS A FUNCTION OF
TEMPERATURE
!
f;~~;~:~ 1 H I-
f-- --
L.....--t---------
t--------
-I--
TA:25'C
-
-
--
----
,0 r--+-++-tH-+-+-t---j
6-28
TRANSFER CHARACTERISTICS
AS A FUNCTION OF
SUPPLY VOL TAGE
FAIRCHILD. 9614
APPLICATIONS
DIFFERENTIAL MODE EXPANSION
MULTIPLEX OPERATION
J.1·~---------lWISTED PAIR L l N E - - - - - - - - - - - - l
Expand by tieing NAND active pull down outputs together
and by tieing AND active pull up outputs together.
The drivers can be inhibited by tak in9 one input to ground.
Fig. 2
Note: Only 1 Driver is Enabled At One Time
r-
SIMPLEX - DIFFERENTIAL OPERATION
'co
"":~ I
£
,w,,,m,,,,
'I'
I
1:'"
---I~
i
SHIELD OR COMMON GROUND CON:ECTION
SEE 9615 DATA SHEET FOR OPERATION OF 9615
See 9615 Data Sheet for operation of 9615.
Fig. 3
TYPICAL REFLECTION DIAGRAM
NOTE-SEE 9621 DATA SHEET FOR USAGE OF REFLECTION DIAGRAM
200
160
Vf-""
VCC=5.0V
TA=25°C
./
/
120
/..
~ 80
/
I
~
40
a
I
V
UJ
~
LOW STATE OUTPUT DEVICE
CHARACTERISTICS
0
/
5 -40
a..
1
-120
/
/
-160
200
-5
-4
-3
-2
-1
..........
1/
~~
o
HIGH STATE OUTPUT DEVICE_
- - CHARACTERISTICS
J
I-
6- 80
/'
.......... V
2
3
4
OUTPUT VOLTAGE - V
Fig. 4
6-29
5
6
7
8
9
10
•
9616
TRIPLE EIA RS-232-C/MIL-STD-188C LINE DRIVER
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The 9616 is a Triple Line Driver which meets the electrical interface specifications of EIA RS-232-C and CCITT V.24 and/or MIL-STD-188C
(by the appropriate device selection). Each driver converts TTL/DTL logic levels to EIA/
CCITT and/or MIL-STD-188C logic levels for transmission between data term ina I
equipment and data communications equipment. The output slew rate is internally
limited and can be lowered by an external capacitor; all output currents are short-circuit
limited. The outputs are protected against RS-232-C fault conditions. A logic HIGH on
the inhibit terminal interrupts signal transfer and forces the output to a VOL (EIA/CCITT
MARK) state.
CONNECTION DIAGRAM
14-PIN
(TOP VIEW)
PACKAGE OUTLINES 6A 9A
PACKAGE CODES
0
P
For the complementary function, see the 9617 Triple EIA RS-232-C Line Receiver and
the 9627 Dual EIA RS-232-C and MIL-STD-188C Line Receiver.
•
•
•
•
•
INTERNAL SLEW RATE LIMITING
MEETS EIA RS-232-C AND CCITT V.24 AND/OR MIL-STD-188C
LOGIC TRUE INHIBIT FUNCTION
OUTPUT SHORT-CIRCUIT CURRENT LIMITING
OUTPUT VOLTAGE LEVELS INDEPENDENT OF SUPPLY VOLTAGES
ORDER INFORMATION
TYPE
PART NO.
9616
9616DM
9616C
9616DC
9616E
9616EDC
9616PC
9616C
9616E
9616EPC
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Input or Inhibit Voltage
Output Signal Voltage
Internal Power Dissipation (Note 1)
Storage Temperature Range
Operating Temperature Range
RS-232 MIL-STD-188 (9616)
RS-232 (9616C)
RS-232 MIL-STD-188 (9616E)
Pin Temperatures
Hermetic DIP, Flatpak (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
±15 V
-1.5 V to +6.0 V
±15 V
670 mW
-65°C to +150°C
-55°C to + 125°C
O°C to 70°C
O°C to 70°C
300°C
260°C
NOTE
1 For Hermetic and Plastic DIP above BOoC derate linearly at 8.3 mW/oC.
INPUT
INHIBIT
OUTPUT
L
L
H
H
H
L
L
L
2
All Sections:
L
H
L
H
L
H
L
H
For Channels A and B add:
L
H
L
H
H
L
H
L
L
L
H
H
H
H
L
L
(For Channel C, omit INPUT 2 Column)
6-30
FAIRCHILD LINEAR INTEGRATED CIRCUIT. 9616
EQUIVALENT CIRCUIT (One of three channels)
1,5.13
INPUT 1
2,12
INPUT 2
GND
II
9616AND 9616E
RS-232-C and MIL-STD-188C
DC CHARACTERISTICS: VCC = ±12 V ±1 0%; RL ~ 3 kO, See Test Circuit, unless otherwise specified, Note 2
SYMBOL
CHARACTERISTICS
CONDITIONS
= VINHIBIT = 0.8
VOH
Output HIGH Voltage
VINl and/or VIN2
VOL
Output LOW Voltage
VINl
Ripple Rejection
Power Supply Ripple
VOL
Output HIGH Voltage to
Output LOW Voltage
Magnitude Matching Error
ISC+
Positive Output Short
Circuit Current
VOH
to
ISC-
Negative Output Short
Circuit Current
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Input HIGH Current
IIH
Input LOW Current
IlL
Positive Supply Current
1+
Negative Supply Current
1ROUT
ROUT
V
= VIN2 = VINHIBIT = 2.0 V
RL
=0
RL
= 00,
= 2.4 Vp-p, f = 400
0, VINl and/or VIN2
VINl
TYP
MAX
5.0
6.0
7.0
-7.0
-6.0
-5.0
Hz
= VINHIBIT = 0.8 V
= VIN2 = VINHIBIT
MIN
= 2.0 V
0.25
±10
%
-25
-12
rnA
+12
+25
+45
rnA
V
= VIN2 = 2.4 V
VINl
= VIN2 = 5.5
VINl
= VIN2 = 0.4 V
VINl
= VIN2 = VINHIBIT = 0.8 V
VINl
= VIN2 = VINHIBIT = 2.0
VINl
= VIN2 = VINHIBIT = 0.8 V
-1.0
0
VINl
= VIN2 = VINHIBIT = 2.0 V
-25
-15
=6
kO, Ll.IL
=
V
-1.6
V
RL
Output Resistance, Power Off
300
0.8
V
40
J1A
1.0
rnA
-1.2
rnA
15
25
7.5
15
75
10 rnA
,
V
-45
VINl
-2.0 V ,,; VOUT"; +2.0 V
All Inputs and Supply Pins Grounded
V
% of VOUT
2.0
Output Resistance, Power On
UNITS
rnA
rnA
°
°
NOTES:
The operating temperature range for the 9616 is -55°C to +125°C and 9616E is DoC to +70°C.
3.
An external capacitor may be needed to meet signal wave shaping requirements of MIL-STO-188C at the applicable modulation rate. No external capacitor is needed to meet RS-232-C over the operating temperature range of DoC to +70 0 e.
6-31
FAIRCHILD LINEAR INTEGRATED CIRCUIT. 9616
9616 AND 9616E
RS232-C and MIL-STO-188C (cont'd)
AC CHARACTERISTICS: 0"; TA"; 70 c C, Notes 2 and 3
SYMBOL
CHARACTERISTICS
tpLH
tpHL
CONDITIONS
MIN
TYP
MAX
4.0
15
30
UNITS
Vips
-30
-15
-4.0
Vips
Negative Slew Rate
o pF ,,; CL ,,; 2500 pF, RL;;' 3 kO
o pF ,,; CL ,,; 2500 pF, RL ;;. 3 kO
Propagation Delay Time
No Load
320
ns
No Load
320
ns
Positive S lew Rate
Propagation Delay Time
9616C
EIA RS-232-C
DC CHARACTERISTICS: VCC = ±12 V ±1 0%, over operating temperature range, See Test Circuit, RL = 3 kO,
unless otherwise specified
SYMBOL
CHARACTERISTICS
CONDITIONS
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VINl
ISC+
Positive Output Short
Circuit Current
RL
= 00,
ISC-
Negative Output Short
Circuit Current
RL
=0
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIH
Input HIGH Current
IlL
Input LOW Current
1+
1-
ROUT
VINl andlor VIN2
= VINHIBIT = O.B
= VIN2 = VINHIBIT = 2.0 V
VINl andlor VIN2
0, VINl
MIN
TYP
MAX
5.0
6.0
7.5
V
-7.5
-6.0
-5.0
V
V
= VINHIBIT = 0.8
V
UNITS
-25
mA
25
mA
= VIN2 = VINHIBIT = 2.0 V
2.0
Positive Supply Current
Negative Supply Current
Output Resistance, Power Off
V
VINl
= VIN2 = 2.4
V
VINl
= VIN2 = 5.5
V
VINl
= VIN2 = 0.4
V
VINl
= VIN2 = VINHIBIT = O.B
VINl
VINl
= VIN2 = VINHIBIT = 0.8
V
-1.0
0
VINl
= VIN2 = VINHIBIT = 2.0 V
-22
-15
-2.0 V ,,; VOUT ,,; +2.0 V
All Inputs and Supply Pins Grounded
300
-1.6
0.8
V
40
pA
1.0
mA
-1.2
mA
V
15
22
= VIN2 = VINHIBIT = 2.0 V
7.5
13
mA
mA
0
AC CHARACTERISTICS: 0"; TA"; 70 c C, Note 3
SYMBOL
CHARACTERISTICS
CONDITIONS
MIN
TYP
MAX
4.0
15
30
Vips
-30
-15
-4.0
Vips
UNITS
Negative Slew Rate
o pF ,,; CL ,,; 2500 pF, RL ;;. 3 kO
o pF ,,; CL ,,; 2500 pF, RL ;;. 3 kO
tpLH
Propagation Delay Time
No Load
320
ns
tpHL
Propagation Delay Time
No Load
320
ns
Positive Slew Rate
AC TEST CIRCUIT
VOLTAGE WAVEFORMS
1
+3.0 V,--,-_ _ _ _ _ _ _ _- ,
INPUT
(INHI~~R= toW) 0 v
~1'5V
'PHl-
'PlHi
VOH _ _ _-=.".,.
1/39616
OUTPUT
~"90%
OV-------'-0-%~~~~__-------------+~3=.O~V~~~O~v
-3V
VOl.-----------
-
~90%
f---'f
Input: Frequency = 50 kHz
Pulse Width = 20 ps
t r and tf = 10 ± 5 ns
Note: Omit VIN2 for channel "C".
6-32
J
10%+
,,---I
~
9634
DUAL 3-STATE DIFFERENTIAL LINE DRIVER
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The 9634 Dual3 - state Line Driver is designed specifically
to meet the EIA standard RS -422. It provides unipolar differential drive to twisted - pair
or parallel-wire transmission lines. The outputs are similar to totem - pole TIL circuits
but with the active pull- up and pull-down circuits split and brought out to adjacent pins.
The active pull- up circuit is short circuit protected. In addition to the normal lowimpedance HIGH and LOW states, the 9634 outputs provide a high-impedance OFF
state, which is controlled by the output STROBE function. When the output control
(STROBE) is HIGH, the associated outputs are high - impedance states neither driving
nor loading the line permitting flexibility in party-line or bus applications. The 9634 is
specified to drive 500 terminated transmission lines at high speeds. The inputs are
TIL and CMOS compatible.
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 6B 9B
PACKAGE CODES
0
P
II
Vee
OUT A SOURCE
2
15
OUT
OUT A SINK
•
•
•
•
•
•
•
•
•
•
B
OUT A SOURCE
OUT A SINK
5
STROBE A
IN A1
OUT B SOURCE
"
STROBE B
IN A2
GND
IN 82
ABSOLUTE MAXIMUM RATINGS
VCC Pin Potential to Ground Pin
Input Voltage
Internal Power Dissipation
Operating Temperature
9634DM
9634DC, 9634PC
Storage Temperatu re
Pin Temperature
Molded DIP (Soldering, lOs)
Hermetic DIP (Soldering, 30 s)
-0.5 V to +7.0 V
-0.5 V to +7.0 V
800 mW
-55°C to +125°C
OOC to 70°C
-65°C to +150°C
260°C
300°C
6-33
SOURCE
3
HIGH-IMPEDANCE OUTPUT STATE FOR PARTY-LINE APPLICATIONS
OUTPUT SHORT CIRCUIT PROTECTION
HIGH-OUTPUT DRIVE CAPABILITY FOR 50 (') TRANSMISSION LINES
INDIVIDUAL OUTPUT CONTROLS
INPUT CLAMP DIODES
SCHOITKY TECHNOLOGY
COMPLEMENTARY OUTPUTS
MEETS THE EIA-RS-422 SPECIFICATION FOR A BALANCED DRIVER
"GLITCH LESS" DIFFERENTIAL OUTPUT
DELAY TIME INCENSITIVE TO BOTH VCC AND TEMPERATURE
ORDER INFORMATION
TYPE
PART NO.
9634
9634DM
9634
9634DC
9634
9634PC
FAIRCHILD. 9634
RECOMMENDED OPERATING CONDITIONS
9634DC, 9634PC
9634DM
SYMBOL
VCC
CHARACTER ISTICS
UNITS
Supply Voltage
MIN
TYP
4.5
5.0
MAX
MIN
TYP
MAX
5.5
4.75
5.0
IOH
Output HIGH Current
-50
IOL
Output LOW Current
50
TA
Ambient Temperature
-55
125
0
5.25
V
-50
mA
50
mA
70
°c
ELECTRICAL CHARACTERISTICS: Over recommended ambient temperature, unless otherwise noted.
SYMBOL
V,H
CONDITIONS (Notes 1 and 2)
CHARACTERISTICS
MIN
TYP
MAX
2.0
Input HIGH Voltage
UNITS
V
9634DC, 9634PC
0.8
9634DM, 9634FM
0.7
V,L
Input LOW Voltage
V,
Clamped Input Voltage
VCC = Min, "N = 18 mA
VOH
Output HIGH Voltage
VCC = Min, V,H = V,H Min,
V,L = V,L Max
VOL
Output LOW Voltage
VCC = Min, V,H = V,H Min,
V,L = V,L Max, 10L = 50 mA
0.5
V
"N
Input Current at Maximum
Input Voltage
VCC = Max, VIN Max = 5.5 V
50
J1A
"H
Input HIGH Current
VCC = Max, V,H = 2.7 V
25
J1A
-200
J1A
-150
mA
V
',L
Input LOW Current
VCC = Max, V,L = 0.5 V
lOS
Short-Circuit Output Current
VCC = Max, VOUT = 0 V
VT/VT
Terminated Output Voltage
See Figure 1
IVT- vTI
Output Balance
-1.0
"OH =-10 mA
2.5
I'OH =-40 mA
2.0
V
-50
2.0
V
IVosl-rvos Output Offset Balance
I'xl
Output Leakage Current
-0.25 V < Vx
ICC
Supply Current (both drivers)
All input at 0 V, VCC = 5.5 V, no load
< 6.0 V
IOZ
Off State High-Impedance
State (lOUT)
VCC = Max, Strobe input at
V,L Max
,
,
48
VOUT = 2.4 V
VOUT= 0.4 V
NOTES:
1. Use Min/Max values specified in recommended operating conditions.
2. Typical limits are at Vee = 5.0 V and TA = 25°e.
TERMINATED OUTPUT VOLTAGE AND OUTPUT BALANCE
VOUT
VOUT
+
500
V,N
1/2
9634
VT
~
500
-
Fig. 1.
6-34
VOUT
V
3.5
See Figure 1
IVosl,IVosl Output Offset Voltage
-1.2
-200
0.4
V
3.0
V
0.4
V
100
J1A
69
mA
+200
J1A
FAIRCHILD. 9634
AC CHARACTERISTICS
SYMBOL
CHARACTER ISTICS
CONDITIONS
MIN
tpHL
tPLH
Propagation Delay
TA
CL
=
15 pF (Note 2), See Fig. 2
tf
Fall Time, 90% - 10%
15 pF (Note 2), RL
tr
TA = 25°C, CL
See Fig. 2
=
Rise Time, 10% - 90%
tpA - tPA
Skew Between Two Outputs
= 25°C,
TYP
MAX
10
10
15
15
10
15
ns
10
15
ns
= 100 n
UNITS
ns
ns
1.0
ns
AC RISE AND FALL TIME TEST CIRCUIT AND WAVEFORMS
3.0V
VOUT
l"e
1/2
9634
VIN
RL
100
r
V IN
VQUT-VOUT
n
-
1.5V-
L
~
+VOH _ _
--1.5 V
I1-
t
PLH
90%
~
90%
VOUT3J:~
VOUT
-VOH
10%
ICL
--.I
i
tPHL
10%
---
.-tr
f--tf
NOTES:
1. The pulse generator has the following characteristics:
ZOUT ~ 50
n,
PRR ~ 500 kHz
tw= 100 ns
2. CL includes probe and jig capacitance.
Fig. 2.
TYPICAL DELAY CHARACTERISTICS
."
16
16
14
14
10
I
:i
e..l
J:
e-
-
12
8
- I--
."
I-- ~
12
--
l10
I
:i
e-
8
..l
J:
6
e-
6
4
4
2
2
-50
-25
0
25
50
75
100
125
3
AMBIENT TEMPERATURE - °C
4
5
6
SUPPLY VOLTAGE - V
Fig. 3.
6-35
7
I
9636A
DUAL PROGRAMMABLE SLEW RATE LINE DRIVER
(EIA RS-423 DRIVER)
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The 9636A is a TTL/CMOS compatible, dual, singleended, line driver which has been specifically designed to satisfy the requirements of
EIA Standard RS-423.
The 9636A suitable for use in digital data transmission systems where signal wave
shaping is desired. The output slew rates are jOintly controlled by a single external
resistor connected between the wave shaping control (WS) pin and ground. This
eliminates any need for external filtering of the output signals. Output voltage levels
and slew rates are independent of power supply variations. Current limiting is provided
in both output states. The 9636A is designed for nominal power supplies of ±12 V.
CONNECTION DIAGRAM
a-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 9T 6T
PACKAGE CODES T R
Inputs are TTL compatible with input current loading low enough (1/10 U.U to be
also compatible with CMOS logic. Clamp diodes are provided on the inputs to limit
transients below ground.
•
•
•
•
•
PROGRAMMABLE SLEW RATE LIMITING
MEETS EIA RS-423 REQUIREMENTS
AVAILABLE IN COMMERCIAL OR MILITARY TEMPERATURE RANGE
OUTPUT SHORT-CIRCUIT PROTECTION
TTL AND CMOS COMPATIBLE INPUTS
WAVESHAPE
CONTROL
vcc+
IN A
OUT A
IN B
OUT B
OND
Vee
ABSOLUTE MAXIMUM RATINGS
Vcc+ Pin Potential to Ground Pin
Vcc- Pin Potential to Ground Pin
Vcc+ Pin Potential to Vcc- Pin
Output Potential to Ground Pin
Output Source Current
Output Sink Current
Internal Power Dissipation (Note) 9T
6T
Operating Temperature
Military (9636ARM)
Commercial (9636ARC, 9636ATC)
Storage Temperature
Pin Temperature
Molded DIP (Soldering, 10 s)
Hermetic DIP (Soldering, 60 s)
Vcc- to +15 V
+0.5 to -15 V
o to +30 V
±15 V
-150 mA
150 mA
1.3W
1.15W
-55 0 C to 125° C
0° C to 70° C
-65° C to 150° C
260°C
300°C
NOTE:
1. Derate at 7.7 mW;CC 10r ambient temperatures above 25°C for 6T package and derate 11.1 mW/oC for 9T
package.
RS-423 SYSTEM APPLICATION
TWISTED PAIR
OR
FLAT CABLE
Vcc-
6-36
r-5.0V
ORDER INFORMATION
TYP
PART NO.
9636A
9636ARM
9636A
9636ARC
9636A
9636ATC
FAIRCHILD. 9636A
RECOMMENDED OPERATING CONDITIONS
9636ARM
CHARACTERISTICS
Positive Supply Voltage (Vcc+)
Negative Supply Voltage (Vcc-)
Operating Ambient Temperature (TA)
MIN
TYP
10.8
-13.2
-55
12
-12
Wave Shaping Resistance (Rws)
25
9636ARC, 9636ATC
MAX
MIN
TYP
MAX
13.2
-10.8
125
10.8
-13.2
0
12
-12
13.2
-10.8
70
500
10
10
25
UNITS
V
V
·C
k{)'
1000
ELECTRICAL CHARACTERISTICS: Over recommended temperature supply voltage and wave shaping resistance ranges unless noted.
SYMBOL CHARACTERISTICS
CONDITIONS
VOHl
VOH2
RL to GND (RL
RL to GND (RL
RL to GND (RL
Output High Voltage
VOH3
VOLl
VOL2
VOL3
Output Low Voltage
Ro
Output Resistance
.
= )
= 3 k{)')
= 450{)')
RL to GND (RL = .. )
RL to GND (RL = 3 k{)')
Isc+
Isc-
Output Short Circuit Current
Output Short Circuit Current
lox
Output Leakage Current
VIH
Input High Voltage
VIL
Input Low Voltage
VCD
Input Clamp Diode
hL
Input Low Current
hH
Input High Current
Icc+
Positive Supply Current
Icc-
Negative Supply Current
TYP
MAX
5.0
5.6
5.6
6.0
6.0
V
V
5.0
4.0
-6.0
-6.0
-6.0
RL to GND (RL = 450{)')
VOUT = 0 V, VIN = 2.0 V
VOUT - ±6 V, Power-Off
(see note)
5.5
6.0
V
-5.7
-5.6
-5.0
-5.0
-5.4
-4.0
V
V
V
25
50
{).
-150
-60
-15
15
-100
60
150
100
rnA
rnA
450{)'~RL
VOUT = 0 V, VIN = 0 V
0.8
hN = 15 rnA
-1.5
-1.1
VIN = 0.4 V
-80
-16
VIN - 2.4 V
\,lIN = 5.5 V
Vcc+ = +12 V, Vcc- = -12 V
RL = .. , Rws = 100 k{)', VIN =0 V
!LA
V
2.0
VCC+ = +12 V, Vcc- = -12 V
RL = .. , Rws = 100 k{)', VIN =OV
UNITS
MIN
V
1.0
10
10
100
13
18
-18
-13
V
!LA
!LA
!LA
rnA
rnA
AC CHARACTERISTICS: TA = 25·C, Vcc = ±12 V ± 10%, see AC Test Circuit
UNITS
SYMBOL CHARACTERISTICS
CONDITIONS
MIN
TYP
MAX
Rws = 10 k{)'
Rws = 100 k{)'
0.8
8.0
1.1
11
1.4
14
,..s
t,
Rws = 500 k{)'
40
55
Rws = 1000 k{)'
80
110
70
140
,..s
,..s
Rws = 10 k{)'
Rws = 100 k{)'
0.8
8.0
1.1
11
1.4
14
. ,..S
Rws = 500 k{)'
40
Rws = 1000 k{)'
80
55
110
70
140
!L S
tf
Output Rise Time
Output Fall Time
NOTE: Only one output should be shorted at a time.
6-37
,..S
,..8
,..s
I
FAIRCHILD • 9636A
TYPICAL ELECTRICAL CHARACTERISTICS
INPUT/OUTPUT TRANSFER
CHARACTERISTIC AS A
FUNCTION OF TEMPERATURE
INPUT CURRENT
AS A FUNCTION OF
INPUT VOLTAGE
Vcc+ =; +12 V
VCC- ~ -12 V
RWS ~ 100 k(J
RL ~ 450 (J
>
I
6.0
"
4.0
w
~
150
I
I-
70°C
25°C
I-
5 --2.0
50
~
a:
0
a:
!.-L-f..
::>
()
-50
I-
f- -55'C
::>
~-'OO
f- 25°C
O°C
-4.0
-150
t-
55°C
-6.0
0.8
0.4
--1
1.8
1.6
1.2
INPUT VOLTAGE - V
OUTPUT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE
(POWER OFF)
OUTPUT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE
(POWER ON)
50
100
Rws
=
VCC± =
TA
100 k!l
12 V
-
w
a:
a:
VIN =
1.
I
2 V
I-
:sa:
10
I-
::>
::>
I-
-20
::>
7
r
-20
I
-50
-80
L...-'----'-_.L.-'----'-_.L.-'----'-_.L...J
·10
-8
-6
-4
-40
-60
I
-40
J
0
VIN = 0 V
-30
r-
- I--- J--
40
0-
0
SERIES WITH Vee PIN
20
()
-10
0-
I-
f-- I-IN
::>
()
::>
60
a:
::>
I-
f--
FOSOO DIODE CONNECTED
I\,
20
f-vL±LNI~o I f T _f--
80
25°C
=;
30
z
7
4
INPUT VOLTAGE - V
40
I-
125°C
-200
0
"EI
--
RI
125°C I -
"
125°C
0
::>
0-
25°C
"- 100
~ 2.0
I-
-55'C
Vcc+ == +12 V
VCC- ~ -12 V
RWS ~ 100 k(J
200
-2
8
-100
-10
10
I
·8
SUPPL Y CURRENT AS A
FUNCTION OF TEMPERATURE
v~e ~112J ,_
0
RI'S ~ ?OO kll
0
~
I
LOGIC
20
I-
0
w
a:
a:
0
JlVIN
::;
0-
a.
::l
()
-6
-4
-2
OUTPUT VOLTAGE - V
OUTPUT VOLTAGE - V
VIN = 1
)LOGIC
VIN = 1
1 "-
Icc-
\ILOGIC_
-2 0
VIN = 0
-3 0
f--
f--
I I
I I
-4 0
-55
25
70
TEMPERATURE-OC
6-38
125
8
10
FAIRCHILD. 9636A
TRANSITION TIME AS A FUNCTION OF Rws
1,000
0
~R~l=Fm
~
III
I
i=
....
....
~
~
,,,-<0
w
::;
100
25°C
,,,'"
:l:
~<>
.
c
z
w
en
"..
"
.0
I
.V
10k20k
5Qk100k
300k
1M
3M
Rws-WAVE SHAPING RESISTANCE-£l
II
SWITCHING TEST CIRCUIT AND AC WAVEFORMS
TEST CIRCUIT
AC WAVEFORMS
3.0 V
VIN
Amplitude - 3.0 V
Offset - 0 V
Pulse Width
PRR
VIN
5' n
4,5010
_
CL - Includes jig and probe capacitance
6-39
"1------
500
1 kHz
-- eo: 10
VOUT
__1" _ _
ns
jJ.s
9638
DUAL HIGH SPEED DIFFERENTIAL LINE DRIVER
(EIA-RS-422)
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The 9638 is a Schottky, TTL-compatible Dual Channel
Differential Line Driver, designed specifically to meet the EIA-RS-422 specifications. It
is designed to provide unipolar differential drive to twisted-pair or parallel-wire transmission lines. The inputs are TTL compatible. The outputs are similar to totem-pole
TTL outputs, with active pull-up and pull-down. The device features a short-circuit
protected active pull-up with low output impedance and is specified to drive 50 n
transmission lines at high speed. The mini DIP provides high package density.
SINGLE 5 V SUPPLY
SCHOTIKY TECHNOLOGY
TIL AND CMOS COMPATIBLE INPUTS
OUTPUT SHORT-CIRCUIT PROTECTION
INPUT CLAMP DIODES
COMPLEMENTARY OUTPUTS
MINIMUM OUTPUT SKEW «1 ns TYPICAL)
50 rnA OUTPUT DRIVE CAPABILITY FOR 50 n TRANSMISSION LINES
MEETS EIA-RS-422 SPECIFICATIONS
PROPAGATION DELAY OF LESS THAN 10 ns
"GLITCHLESS" DIFFERENTIAL OUTPUT
DELAY TIME STABLE WITH VCC AND TEMPERATURE VARIATIONS
«2 ns TYPICAL) (FIG. 3)
CONNECTION DIAGRAM
8-PIN DIP
PACKAGE OUTLINES 9T 6T
PACKAGE CODES
T
R
Vcc
IN CH. 1
IN CH. 2
GNO
CH.l
OUTB
CH.l
OUT A
CH.2
OUTB
CH.2
OUTA
ABSOLUTE MAXIMUM RATINGS
VCC Pin Potential to Ground Pin
Input Voltage
Internal Power DisSipation
Operating Temperature
9638RM
9638RC,9638TC
Storage Temperature
Pin Temperature
Molded DIP (Soldering, lOs)
Hermetic DIP (Soldering, 30 s)
-0.5 V to +7.0 V
-0.5 V to +7.0 V
800mW
-55°C to +125°C
ooC to 70°C
-65°C to +150 oC
6-40
ORDER INFORMATION
TYPE
PART NO.
9638
9638RM
9638
9638RC
9638
9638TC
FAIRCHILD. 9638
RECOMMENDED OPERATING CONDITIONS
9638RM
SYMBOL
UNITS
Supply Voltage
VCC
9638RC, 9638TC
CHARACTERISTICS
MIN
TYP
4.5
5.0
MAX
MIN
TYP
MAX
5.5
4.75
5.0
10H
Output HIGH Current
-50
10L
Output LOW Current
50
TA
Ambient Temperature
-55
125
0
5.25
V
-50
mA
50
mA
70
°c
ELECTRICAL CHARACTERISTICS: Over recommended ambient temperature, unless otherwise noted.
SYMBOL
CHARACTERISTICS
CONDITIONS (Notes 1 and 2)
MIN
Input HIGH Voltage
VIH
TYP
MAX
V
2.0
9638RC, 9638TC
0.8
9638RM
0.7
V
Input LOW Voltage
VIL
UNITS
VI
Clamped Input Voltage
VCC = Min, liN = -18 mA
VOH
Output HIGH Voltage
VCC = Min, VIH = VIH Min,
VIL = VIL Max
-1.0
IIOH=-10mA
2.5
IIOH = -40 mA
2.0
-1.2
V
3.5
V
VOL
Output LOW Voltage
VCC = Min, VIH = VIH Min,
VIL = VIL Max, 10L = 40 mA
0.5
V
liN
Input Current at Maximum
Input Voltage
VCC = Max, VIN Max = 5.5 V
50
/lA
IIH
Input HIGH Current
VCC = Max, VIH = 2.7 V
25
/lA
IlL
Input LOW Current
VCC = Max, VIL = 0.5 V
lOS
Short-Circuit Output Current
VCC = Max, VOUT = 0 V
VT, VT
Terminated Output Voltage
VT- VT
Output Balance
VOS, VOS
-50
-200
/lA
-150
mA
2.0
V
0.4
V
Output Offset Voltage
3.0
V
VOS- VOS Output Offset Balance
0.4
V
100
/lA
65
mA
See Figure 1
< Vx < 6.0 V
Ix
Output Leakage Current
-0.25 V
ICC
Supply Current (both drivers)
All input at 0 V, VCC = 5.5 V, no load
NOTES:
1. Use MIN/MAX values specified in recommended operating conditions.
2. Typical limits are at Vee = 5.0 V and TA = 25°C.
DC TEST CIRCUIT
TERMINATED OUTPUT VOLTAGE AND OUTPUT BALANCE
~* ~
9638
Fig,1
6-41
500
~
500
45
II
FAIRCHILD. 9638
AC CHARACTERISTICS
SYMBOL
Propagation Delay
If
Fall Time, 90%
Ir
Rise Time, 10%
IpA
~
IpB
CONDITIONS
CHARACTERISTICS
tpHL
IpLH
~
TA = 25°C, CL = 15 pF (Note 2),
RL = 1000, See Fig. 2
10%
~
MIN
90%
TYP
MAX
10
10
15
15
UNITS
10
15
ns
10
15
ns
ns
ns
1
Skew Between Outputs A and B
ns
AC TEST CIRCUIT AND VOLTAGE WAVEFORM
AC TEST CIRCUIT
VOUT
,~*
VIN
Rl
9638
I
Cl
1000
-
t
VOUT
Cl
VOLTAGE WAVEFORM
3.0
15V
J
Y,N
I
\
- - t,
f:::.
-
r\'
tPHl-~
/90%
tPlH-~
v
15V
10%
- . tf...-
90%\
10%
VOUT - VOUT
NOTES'
1. The pulse generator has the following characteristIcs:
2.
= 50 n,
PRR = 500 kHz
5 ns
CL Includes probe and jig capacitance.
ZOUT
tw
= 100
ns, tr
'-='
~
Fig,2
TYPICAL DELAY CHARACTERISTICS
14
14
-
12
10
f--"I'""
12
10
S
8
6
6
4
4
2
2
-50
-25
a
25
50
75
100
125
3
AMBIENT TEMP - °C
-
I--
4
5
Vee -V
FIG,3
6-42
6
l-
7
IJA1489 • IJA1489A
QUAD LINE RECEIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The JiA 1489 and the JiA 1489A are EIA RS-232C specified
Quad Line Receivers. These devices are used to interface data terminals with data communications equipment. The JiA 1489 and JiA 1489A are pin-for-pin replacements of the
MC1489 and MC1489A respectively.
•
•
•
•
INPUT RESISTANCE - 3.0 kO TO 7.0 kO
INPUT SIGNAL RANGE - ±30 V
INPUT THRESHOLD HYSTERESIS BUILT IN
RESPONSE CONTROL
a) LOGIC THRESHOLD SHIFTING
b) INPUT NOISE FILTERING
CONNECTION DIAGRAM
14-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 6A 9A
PACKAGE CODES
0
P
IN A
RESPONSE
CONTROL A
IN D
OUT A
IN B
RESPONSE 5
CONTROL B 6
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage
Input Voltage Range
Output Load Current
Continuous Total Power Dissipation (Note 1)
Operating Temperature
Storage Temperature
Pin Temperature
Hermetic DIP (Soldering. 60 s)
Molded DIP (Soldering. 10 s)
OUT B
+10 Vdc
±30 Vdc
20 mA
800 mW
OOC to 70°C
-65°C to +175°C
GND
ORDER INFORMATION
TYP
PART NO.
pA1489
pA1489DC
pA1489
pA1489PC
pA1489A pA1489ADC
pA1489A pA1489APC
Note 1: Above 60°C ambient temperature, derate linearly at 8.3 mW/oC.
CIRCUIT SCHEMATIC (1/4 OF CIRCUIT SHOWN)
. - - - - _ - -......--014 Vee
9 kO
RESPONSE
CONTROL 2
INPUT 1
o - - - - - - -......-'VV'v--t----+
5 kO
1.6 kO
3 OUTPUT
o---'VIIv-.....--........---t:
L--~---~---+--~~__o7GND
6-43
I
FAIRCHILD. IlA 1489 • IlA 1489A
ELECTRICAL CHARACTERISTICS: VCC
SYMBOL
= 5.0 V ±1%,
CHARACTER ISTleS
Response control pin is open, TA
Positive Input Current
IlL
Negative Input Current
VIL = -25 V
VIL = -3.0 V
VIHL
Input Turn-on Threshold Voltage
= 25°C,
TA
JlA 1489
VOL ~ 0.45 V
JlA 1489A
TA = 25°C,
VOH;:" 2.5 V,
IL = -0.5 mA
JlA1489
TYP
MIN
= 25 V
= 3.0 V
IIH
Input Turn-off Threshold Voltage
to 70°C unless otherwise noted.
FIG
CONDITIONS
VIH
VIH
VILH
= OoC
MAX
3.6
0.43
8.3
-3.6
-0.43
-8.3
1.0
UNITS
mA
mA
1.5
2
V
1.75
1.95
2.25
0.75
1.25
V
2
JlA1489A
0.75
0.8
1.25
2.6
4.0
5.0
2
0.2
0.45
3
3.0
VOH
Output HIGH Voltage
VJH = 0.75 V, IL = -0.5 mA
Input open circuit, IL - 0.5 mA
VOL
Output LOW Voltage
VIL
lOS
Output Short-circuit Current
ICC
Power Supply Current
VIH
= 5.0 V
4
20
26
mA
Pc
Power Consumption
VIH
= 5.0 V
4
100
130
mW
TYP
MAX
25
85
25
50
120
175
10
20
AC CHARACTERISTICS: VCC = 5.0 V ±1%, TA
SYMBOL
= 3.0
V, IL = 10 mA
CONDITIONS
RL
= 3.9
R
= 3900
Propagation Delay Time
tpHL
V
V
mA
= 25°C
CHARACTER ISTICS
tpLH
2
FIG.
MIN
kO
tr
Rise Time
RL = 3.9 kO
tf
Fall Time
RL
UNITS
ns
5
5
= 3900
ns
TYPICAL PERFORMANCE CURVES
INPUT CURRENT AS A
FUNCTION OF INPUT VOLTAGE
JlA1489
JlA1489A
INPUT THRESHOLD
VOLTAGE ADJUSTMENT
INPUT THRESHOLD
VOLTAGE ADJUSTMENT
'0
6.0
r--r---'---'--'r-~-r--.---r-.--,
Rr==5.0kO
Rr=oo
RT=11 kO
5 ._
0 -4
V
_"+"_--t
5.0 f-V.,..T-+"-,"_+5,_.0_Vr--.I-"'-rI---.f--'VI-T
/
6.0
V
I
2.0
/
4.0
L
-2.0
/'
-6.0
A
liN
VI~
I
I
,5
2.0
I-+-H-+--+-I\---'/f-it--+--+-I---l
10
I-+-H-I--l--I\---'/f--lf--I--l--I---l
5.0
0
5.0
INPUT VOLTAGE - V
'5
V,""
VILH ....
--r
-II -
b
-'0
25
1-++-I+-+-It---1I1--II-+-+---1-1
3.0 I-+-H-I--+-I\~/f--lf--I--l--I---l
-1
25
INPUT VOLTAGE - V
-
.O_~3..,..0-'--'--:---'--'-3-::-.0::-'---"---:'6.""0-'
INPUT VOLTAGE - V
TEST CIRCUIT SAME AS .uA1489
6-44
FAIRCHILD • /.LA 1489 • /.LA 1489A
TYPICAL PERFORMANCE CURVES (Cont'd)
INPUT THRESHOLD VOLTAGE
AS A FUNCTION
OF TEMPERATURE
2.4
INPUT THRESHOLD VOLTAGE
AS A FUNCTION OF
POWER SUPPLY VOLTAGE
.--r--r-r-,--r--r-r-,--r,
2.0
VIHl J.i!'1489A
>,
2.0
w
"~
o
w
1,6
"~
f-+-+-t-t-+-+-t-t-+---1
>
~
0
>
1.2
--=o.,uA1 4 BS
* _
:::c
i!:
Cl
,uA,14S9
~IHL
i
~~-~~~~r--t~
0,8
/..'414894
~I
0
i"' r-r-
pA1489A
>-
[
I
60
pA1489
I
i:
~
OL-~~~_~I~~I~~
-60
J--VILH
a:
V;--t--
J
~ ~4
VIHL pA1489
1.0
0
120
0
TEMPERATURE - °C
4.0
B.O
12
POWER SUPPLY VOLTAGE - V
DC TEST CIRCUITS
+y,:
VIN
IIH
~
IlL
?-
3
0---2-2
3
r-
f---2
-
~
4
~
5
6
2-
-
~
~
-9
r8
r-
9
10
~
12
10
12
11
VOH
13
r-
11
~
~
-=1-7
-=1-7
Input Current
Fig. 2.
Output Voltage and Input
Threshold Voltage
Vee
-
Vee
lee
f14
1
3
,-~
3
r-
-
4
-5
~
~
r!-o
10
4
~
5
6
-9
lOS
1 -1-
I8
I-
10
~
12
-----12
-
~
Fig. 3.
~14
1
~
2
~
~
-=-
~
-
-
13
Fig. 1.
II
+5.0V
11
~
f----
-:!:-7
11
I-
-:!:-7
Output Short-Circuit Current
Fig. 4.
6-45
Power Supply Current
FAIRCHILD. J1A 1489 • J1A 1489A
DC TEST CIRCUITS (Cont'd)
5.0 V
ALL DIDOES F0600
OR EQUIVALENT
----o
I<>--~--.....
VIN
J
--..
VOUT
CT
=
\1'3,,----'::
50%
1
I
. . - tPHl
trAND tf
MEASURED 10%-90%
I
.....
...- tPlH
15 pF = Total parasitic capacitance, which Includes
probe and jig capacitance.
Fig. 5.
VOUT
AC Test Circuit and Voltage Waveforms
R"
RESPONSE NODE
VIN
o---Qo-------o
VOUT
1/4 ~A14B9A
"Capacitor is for nOise filtering
**Resistor is for threshold shifting
Fig. 6.
Response Control Node
6-46
J..tA8T14 • 55122 • 75122
TRIPLE LINE RECEIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The 55122/75122/MA8T14 Triple Line Receiver is designed to receive
CONNECTION DIAGRAM
16-PIN
(TOP VIEW)
PACKAGE OUTLINES 68 98
PACKAGE CODES 0 P
digital information from coaxial cable, strip line, or twisted pair single ended transmission lines. High
input impedance (R::!30 kn) presents minimal loading to the transmission lines in multiple receiver
applications. The 55122/75122/MA8T14 has built-in hysteresis which makes it ideal for such applications
as Schmitt triggers, one-shots, and oscillators. Use the 75124 or 8T24 triple line receiver where IBM
System/360 I/O Interface Specification must be met.
•
•
•
•
•
BUILT-IN INPUT THRESHOLD HYSTERESIS
HIGH SPEED
INDEPENDENT CHANNEL STROBING
FANOUT OF 10 TTL LOADS
SINGLE +5.0 V SUPPLY OPERATION
IN C1
IN C2
FUNCTION TABLE
ABSOLUTE MAXIMUM RATINGS
Input Voltage (Note 1) R Input
1,2 or S Input
Output Voltage (Note 1)
Supply Voltage (Note 1)
Output Current
Storage Temperature Range
Operating Temperature Range
Military (55122, MA8T140M)
Commercial (75122)
INPUTS
+6.0 V
+5.5 V
+6.0 V
+6.0 V
±100 mA
_65° C to +150° C
_55 0 C to +125° C
O°C to +70°C
Pin Temperatures
Hermetic DIP (Soldering, 60 5)
Molded DIP (Soldering, 105)
OUTPUT
1
2'
R
S
H
H
X
X
X
X
L
H
L
L
X
H
X
H
X
X
L
H
L
H
X
H
X
L
X
L
H
~
HIGH
~
LOW
IN B
11
IN A2
STROBE B
OUT A
GND
OUT B
ORDER INFORMATION
X = Don't Care
I nternal Power Dissipation (Note 2)
OUT C
IN Al
L
L
RC
STROBE A
L
X
H
STROBE C
RA
* Input 2 and last two lines of the
Function Table are applicable
receivers A and Conly.
to
NOTES:
TYPE
IlA8T14 or 55122
IlA8T14 or 75122
MA8T14 or 75122
PART NO.
MA8T14/55122DM
IlA 8T14/75122DC
MA8T14/75122PC
1. Voltages are with respect to the ground pin (pin 8).
2. Above 60°C ambient temperature, derate !inearl~ at 8.3 mW/oC for Hermetic DIP and Molded DIP.
EQUIVALENT CIRCUIT (EACH RECEIVER)
680n
620n.
4k
800n
56n
3.5k
OUT
1k
3k
680n.
6.2k
360n.
50n
400n.
6-47
II
FAIRCHILD. J.!A8T14 .55122 • 75122
RECOMMENDED OPERATING CONDITIONS
Supply Voltage, VCC
MIN
TYP
MAX
4.75
5.0
5.25
V
-500
/lA
16
rnA
Output HIGH Current, 10H
Output LOW Current, 10L
Operating Ambient Temperature, TA
I
55122/ST14
UNITS
-55
°c
125
1~"--~75~1-2~2/~S-T~14~-------------+-----0---+--------+----------r--~---°c
70
ELECTRICAL CHARACTERISTICS: VCC = 4.75 V to 5.25 V, TA = 25"C (unless otherwise noted)
SYMBOL
CONDITIONS
CHARACTERISTICS
VIH
Input HIGH Voltage
All Inputs
VIL
Input LOW Voltage
All Inputs
VT+ - VT-
Hysteresist
R
VCC = 5.0 V, TA = 25"C
VIN
Input Clamp Voltage
Inl,20rS
VCC = 5.0 V,IIN = -12 mA
V(BR)IN
Input Breakdown Voltage
Inl,20rS
VCC = 5.0 V,IIN = 10 mA
MIN
MAX
O.S
0.3
0.6
2.6
V
VIN(A) = 0 V, VIN(B) = 0 V, VIN(S) = 2.0 V,
2.6
VIH = 2.0 V, VIL = O.S V, 10L = 16 mA,
0.4
See Note 3
Output LOW Voltage
V
V
5.5
VIN(R) = 1.45 V (See Note 4, 10H = -500 /lA
VOL
V
V
-1.5
See Note 3
Output HIGH Voltage
UNITS
V
2.0
VIH - 0 V, VIL = O.S V, 10H - -500 /lA,
VOH
TYP
V
VIN(A) = 0 V, VIN(B) = 0 V, VIN(S) = 2.0 V,
0.4
VIN(R) = 1.45 V (See Note 5),IOL = 16 mA
Inl,20rS
VIN =4.5 V
40
R
VIN = 3.S V
170
Inl,20rS
VIN -0.4 V
IIH
Input HIGH Current
IlL
Input LOW Current
lOS
Short·Circuit Output Current~
VCC = 5.0 V, TA = 25"C
ICC
Supply Current
VCC = 5.25 V
/lA
-0.1
-1.6
rnA
-50
-100
rnA
72
mA
tHysteresis is the difference between the positive-going input threshold voltage, VT+, and the negative-going input threshOld voltage, VT _, See
Hysteresis Test Circuit.
+Not more than one output should be shorted at a time.
NOTES:
3, The output voltage limits are guaranteed for any appropriate combination of HIGH and LOW inputs specified by the function table for
the desired output.
4.
5.
Receiver input was at a HIGH level immediately before being reduced to 1.45 V.
Receiver input was at a LOW level immediately before being raised to 1.45 V.
AC CHARACTERISTICS: VCC = 5.0 V, TA = 25°C
SYMBOL
CONDITIONS
CHARACTERISTICS
Propagation Delay Time, Output LOW to HIGH
MIN
See Test Circuit
Propagation Delay Time, Output HIGH to LOW
TYP
MAX
20
30
20
30
UNITS
ns
AC CHARACTERISTICS
VOLTAGE WAVEFORMS
TEST CIRCUIT
2.6 V
84.5.1'2
I
PULSE GENERATOR
T
:I--D. . .
>o--;"""\
3~ r-.V""""--1-LL-."
,y
C L* ~
1N306'
OUTPUT
1.5V
5kn
OUTPUT
---f-J
=30pF
---
INPUT PULSE
Amplitude = 2.6 V
tpw = 200 ns (50% 0 uty eycl e)
tr = tf <5 ns (10% and 90% measurement points)
* Includes
probe and jig capacitance.
6-48
tpLH
1.5V
I
!----
lPHLI-
FAIRCHILD. J.!A8T14 • 55122 .75122
HYSTERESIS TEST CIRCUIT
CURVE TRACER
TEK 575
11
1 4 1 - - - - - . . R INPUT
15'
101-----..
, -____- . , . -_ _-4k
12
L-------~-~V2----7V~,-r-~VIN
1.0V
2.0V
Verify in each of three (3) positions of S1 (Fig. 1) that the following occurs per Figure 2.
1.
V 1 and V2 must be between 0.8 V minimum and 2.0 V maximum.
2.
Hysteresis
=
V 1 - V2 ;;. 0.3 V.
APPLICATIONS
I
55/7 5122/8T 14
75.11 COAX
/~
55/75122/8T14
If more than one driver/receiver pair is to be used on each transmission
line, the line should be terminated at both ends7
SCHMITT TRIGGER APPLICATION
IN
OUT
IN
OV
55/75122/8T14
OUT
6-49
JlA8T24 • 75124
TRIPLE LINE RECEIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The I'A8T24/75124 Triple Line Receiver meets IBM System/360 I/O
Interface Specifications (File No. S360-191. Logic inputs are fully TTL or DTL compatible. The R
(Receivel input is designed to withstand a positive de input of +7.0 V with power on (VCC+ = 5.0 VI
and +6.0 V with power off, (VCC+ = 0 VI and a negative dc input of 0.15 V with power on or off.
This protection allows normal bus operation even if one or more receivers have been powered down.
•
•
MEETS IBM SYSTEM/360 I/O INTERFACE SPECIFICATION
BUILT-IN INPUT THRESHOLD HYSTERESIS
•
•
•
•
HIGH SPEED
INDEPENDENT CHANNEL STROBING
FANOUT OF 10 TTL LOADS
SINGLE +5.0 V SUPPLY OPERATION
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEWI
PACKAGE OUTLINES 6B 9B
PACKAGE CODES D P
IN Cl
FUNCTION TABLE
INPUTS
ABSOLUTE MAXIMUM RATINGS
Input Voltage
7.0 V
(Note 11
R Input with VCC Applied
6.0V
R Input with VCC not Applied
5.5 V
Logic Inputs
+7.0 V
Output Voltage (Note 11
±100 mA
Output Current
+7.0 V
Supply Voltage (Note 11
_65° C to +150° C
Storage Temperature Range
1
IN C2
OUTPUT
2'
R
S
Y
STROBE C
RA
RC
STROBE A
OUT C
H
H
X
X
L
IN Al
X
X
L
H
L
IN A2
L
X
H
X
H
L
X
X
L
H
X
L
H
X
H
X
L
X
L
H
IN B
11
STROBE B
OUT A
RS
GND
OUT B
DOC to +70° C
Operating Temperature Range
Pin Temperatures
H = HIGH
L
300°C
260°C
800mW
Hermetic DIP (Soldering, 60 sl
Molded DIP (Soldering, 10 sl
Internal Power Dissipation (Note 2)
X
= LOW
= Don't
Care
ORDER INFORMATION
* Input 2 and last two lines of the
Function
Table
are
applicable
receivers A and Conly.
to
PART NO.
TYPE
I'A8T24 or 75124
I'A8T24 or 75124
I'A8T24/75124DC
I'A8T24175124PC
NOTES:
1.
2.
Voltages are with respect to the ground pin (pin 8).
Rating applies to ambient temperatures up to 60°C. Above 60°C derate linearly at 8.3 mW/oC.
EQUIVALENT CIRCUIT (EACH RECEIVERI
16
vcc
56n
680n
620n
1k
4k
Boon
1k
OUTPUT
7,9,13
6.2k
3k
50n
4k
470n
lk
400n
1k
50n
6-50
3.5k
FAIRCHILD. J,lA8T24115124
RECOMMENDED OPERATING CONDITIONS
Supply Voltage, VCC
MIN
TYP
MAX
4.75
5.0
5.25
V
-75
mA
70
'c
Output HIGH Current, 10H
Operating Ambient Temperature, T A
0
UNITS
ELECTRICAL CHARACTERISTICS: VCC = 4.75 to 5.25 V, TA = O'C to 70'C lunless otherwise noted)
SYMBOL
CONDITIONS
CHARACTERISTICS
2.0
R
1.7
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VT+ - VT-
Hysteresist
R
VCC = 5.0 V, TA = 25'C
VIN
Input Clamp Voltage
In 1,2, or S
VCC - 5.0 V, liN - -12 mA
VIBR)IN
Input Breakdown Voltage
In 1,2, or S
VCC
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
O.B
0.7
= 5.0 V,
0.2
VIH
= VIH
0.4
Input HIGH Current
VIN
V
2.6
V
Min, VIL = VIL Max, 10L = 16 mA,
0.4
= 7.0 V
VIN=4.5V
R
VIN = 3.11 V
In I, 2, or S
5.0
5.0
VIN = 6.0 V, VCC = 0
In 1,2, or S
40
170
IlL
I nput LOW Current
lOS
Short-Circuit Output Current:j:
VCC = 5.0 V, TA = 25°C
ICC
Supply Current
VCC - 5.25 V
VIN=O.4V
V
5.5
See Note 3
R
V
V
-1.5
liN = 10 mA
UNITS
V
In 1,2, or S
10H = -800 jJ.A, See Note 3
Maximum Input Voltage
IIH
MAX
R
VIH - VIN Min, VIL - VIL Max,
Input Current at
liN
TYP
MIN
In 1,2, or S
V
mA
jJ.A
-0.1
-1.6
mA
-50
-100
mA
72
mA
tHysteresis is the difference between the positive-going input threshold voltage, VT+, and the negative-going input threshold voltage, VT _" See
Hysteresis Test Circuit.
+Not more than one output should be shorted at a time.
AC CHARACTERISTICS: VCC
= 5.0 V
SYMBOL
TA
= 25'C
CONDITIONS
CHARACTER ISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH from R Input
tPHL
Propagation Delay Time, Output HIGH to LOW from R Input
3.
See Test Circuit
MIN
TYP
MAX
20
30
20
30
UNITS
ns
The output voltage and current limits are guaranteed for any appropriate combination of HIGH and LOW Inputs specified by the Function
Table for the desired output.
6-51
II
FAIRCHILD • IlA8T2417S124
AC CHARACTERISTICS
TEST CIRCUIT
Vee'" 5.0V
MONITOR
INPUT PULSE
16
15
14
D, U. T.
SWITCH 2
84.SQ
2.6V
13
11
10
3 Receivers in the package.
Test each Receiver using switch
positions as shown in Table 1.
WAVEFORMS
TABLE 1
INPUT
Position
Receiver nO.
INPUT PULSE:
-+_J
OUTPUT _ _
Switch 1
Switch 2
2
3
Amplitude:=; 2.6V
Receiver 1
Pulse width = 200ns
(50% Duty Cycle)
tr = t f = 5ns (10% to 90%)
Receiver 2
2
Receiver 3
3
HYSTERESIS TEST CIRCUIT
VOUT
CURVE TRACER
TEK 575
11
1 4 1 - - - - - - . . R INPUT
15
101------..
12
O.7V
V2
V,
1.7V
Verify in each of three (3) positions of S 1 (F i9. 1) that
the following occurs per Fig. 2.
1.
V 1 x and V 2 must be between O.7V minimum and 1 7V
2.
maximum.
Hysteresis = V 1 -V2
Fig. 1
Fig. 2
TYPICAL APPLICATION
1/275123/8T23
1/375124/BT24
6-52
55/75107 A · 55/75108A
55/751078 · 55/751088
DUAL LINE RECEIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The 55/75107A/B and 55/75108A/B are high speed, two·channel
Line Receivers with common voltage supply and ground terminals. They are designed to detect input
signals of 25mV (or greated amplitude and convert the polarity of the signal into appropriate TTL
compatible output logic levels. They feature high input impedance and low input currents which
induce very little loading on the transmission line making these devices ideal for use in party line
systems. The receiver input common mode voltage range is ±3V but can be increased to .*; 15V by
the use of input attenuatars. Separate or common strobes are available. The 55175107A/B circuit
features an active pull·up (totem pole outputl. The
55/75108A/B
CONNECTION DIAGRAM
14·PIN DIP
(TOP VIEWI
PACKAGE OUTLINES 6A 9A 31
PACKAGE CODES D
P F
circuit features an open collector
output configuration that permits wired·QR connections. The receivers are designed to be used with
the 55109175109 and 55110175110 line drivers. The
55175107A/B
and
55/75108A/B
line
receivers are useful in high speed"balanced, unbalanced and party line transmission systems and as data
comparators. (See following description of A and B versions.)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
HIGH SPEED
STANDARD SUPPLY VOLTAGES
DUAL CHANNELS
HIGH COMMON·MODE REJECTION RATIO
HIGH INPUT IMPEDANCE
HIGH INPUT SENSITIVITY
INPUT COMMON·MODE VOLTAGE RANGE OF ±3 V
SEPARATE OR COMMON STROBES
TTL OR DTL DRIVE CAPABILITY
WIRED·OR OUTPUT CAPABILITY
HIGH DC NOISE MARGINS
STROBE INPUT CLAMP DIODES
55/75107B SERIES DEVICES ARE DIRECT REPLACEMENTS FOR
55175107A SERIES DEVICES
B VERSION AVAILABLE UPON REOUEST
INPUT IS DIODE PROTECTED AGAINST POWER·OFF LOADING
ON B VERSIONS DEVICES
IN A2
Ne
OUT A
STROBE A
STROBE
GND
The essential difference between the 55/75107A and 55/751078 versions is shown in the
following schematics of the input stage:
Vee+
---t---""'--""1"---,
A
vcc+--~~-~~--~--_,
A
"A" Version
"B" Version
The input protection diodes are useful in certain party·line systems which may have multiple
VCC+ power supplies and, in which case, may be operated with some of the VCC+ supplies
turned off. In such a system, if a supply is turned off and allowed to go to ground, the equivalent
input circuit connected to that supply would be as follows:
INPUT
--j>t-1-c!J--I
"A" Version
~
INPUT
--t>l--I<1-r--t
UB"version·
."
INA1
~ "*"
This would be a problem in specific systems which might possibly have the transmission lines
biased to some potential greater than 1.4 V. Since this is not a widespread application problem,
both the A and B versions will be available. The ratings and characteristic specifications of
the B versions are the same as those of the A versions. The B versions will be supplied upon
request.
6-53
IN 82
Ne
OUT B
STROBE B
ORDER INFORMATION
TYPE
PART NO.
55107AFM
55107ADM
55107A
55107A
75107A
75107A
55108A
55108A
75108A
75108A
75107ADC
75107APC
55108AFM
55108ADM
75108ADC
75108APC
55107B
55107B
75107B
75107B
55108B
55108B
75108B
75108B
55107BFM
55107BDM
75107BDC
75107BPC
55108BFM
55108BDM
75108BDC
75108BPC
•
FAIRCHILD. 55/75107A. 55/751078. 55/75108A. 55/751088
EQUIVALENT CIRCUIT
RI1
120n
Vee+ C>--.,....---.----r---1----r-------;----------+------+----"
R3
3 kn
Vee_C>--+-----;-~---_~
R.
3 kn
_ _...,..~-_+------~
R16
R17
3 kn
3 kn
t-----------I-1>-<> STROBE
r-----------~-----t--OSTR08E8
INPUTS {82
B1
+
o'----'I----t::
24
OUTB
Rl'
lkn
R18
R15
lkn
400n
R21
4 kn
NOTE:
Components shown with dashed lines are applicable to the 55107A/B and 75107A/B only. See preceding
description for differences between A and B versions.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Note 1)
Internal Power Dissipation (Note 3)
Differential Input Voltage (Note 2)
Common Mode Input Voltage (Note 1)
Strobe I nput Voltage (Note 1)
±7 V
670mW
±6 V
±5 V
5.5 V
Operating Temperature Range
55107 A/1 07B/1 08A/1 08B
_55" C tD +125° C
O"C to +70°C
-65"C to +150"C
75107 A/107B/1 08A/1 08B
Storage Temperature Range
Pin Temperature
300"C
260"C
Hermetic DIP, Flatpak (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
Notes on following pages.
6-54
FAIRCHILD. 55/75107A. 55/751078. 55/75108A. 55/751088
ELECTRICAL CHARACTERISTICS
55/75107A,55/75107B
(Ratings Apply Over Full Ambient Temperature Range WithVCC+= Max and VCC- = Max, unless otherwise noted) (Notes 4 & 6)
SYMBOL
CHARACTERISTICS
TYP
MAX
30
75
I'A
-10
I'A
VGATE = 2.4 V
40
I'A
VGATE = V+
1.0
rnA
Input HIGH Current
VDIFF = 0.5 V, VCM = -3 V to +3 V
IlL
Input LOW Current
VDIFF --2 V, VCM --3 Vto+3 V
IIH(G)
Gate Input HIGH Current
IlLIG)
Gate Input LOW Current
IIH(S)
Strobe Input HIGH Current
IIL(S)
Strobe I nput LOW Cu rrent
MIN
TEST CONDITIONS
IIH
VGATE = 0.4 V
VSTROBE = 2.4 V
VSTROBE - V+
VOH
Output HIGH Voltage
VSTROBE = 0.4 V
I L = -400 /JA, V CM = -3 V to +3 V
VCC+= MIN
UNITS
-1.6
rnA
80
I'A
2.0
rnA
-3.2
rnA
2.4
V
VCC- = MIN
VOL
Output LOW Voltage
ISINK = 16 rnA, VCM = -3 V to +3 V
VCC+= MIN
VCC- = MIN
0.4
V
-70
rnA
ISC
Short-Circuit Output Current
VOUT = 0 (Note 5)
ICC+
Positive Supply Cu rrent
VOUT = VOH, IL = 0, TA = 25'C
18
30
rnA
ICC-
Negative Supply Current
VOUT = VOH, IL = 0, TA = 25'C
-8.4
-15
rnA
tPLH (D)
17
25
ns
tpHL (D)
17
25
ns
tPLH(S)
10
15
ns
tPHL(S)
10
15
ns
-18
AC CHARACTERISTICS (VCC+ = +5 V, VCC- = -5 V, RL = 39011, CL = 50 pF, TA = 25'C. See Test Circuit)
Propagation Delay Time
55/75108A,55/75108B
ELECTRICAL CHARACTERISTICS
(Ratings Apply Over Full Ambient Temperature Range With VCC + = Max and VCC - = Max, unless otherwise noted) (Notes 4 & 6)
SYMBOL
CHARACTERISTICS
TYP
MAX
30
75
I'A
-10
/JA
VGATE = 2.4 V
40
I'A
VGATE = V+
1.0
rnA
-1.6
rnA
Input HIGH Current
VDIFF = 0.5 V, VCM = -3 V to +3 V
IlL
Input LOW Current
VDIFF =-2 V, VCM= -3 V to+3 V
IIH(G)
Gate Input HIGH Current
IIL(G)
Gate Input LOW Current
IIH(S)
Strobe Input HIGH Current
IILlS)
Strobe Input LOW Current
VOL
Output LOW Voltage
VIH
Output HIGH Current
MIN
TEST CONDITIONS
IIH
VGATE = 0.4 V
UNITS
VSTROBE = 2.4 V
80
/JA
VSTROBE = V+
2.0
rnA
-3.2
rnA
0.4
V
250
I'A
VSTROBE = 0.4 V
ISINK = 16 rnA, VCM = -3 V to +3 V
VCC+ = MIN
VCC- = MIN
VCC+ = MIN
VOUT = V+
VCC- = MIN
ICC+
Positive Supply Current
VOUT= VOH, IL =0, TA = 25'C
18
30
rnA
ICC-
Negative Supply Current
VOUT= VOH, IL =0, TA = 25'C
-8.4
-15
rnA
tPLH(D)
19
25
ns
tPHL (D)
19
25
ns
13
20
ns
13
20
ns
AC CHARACTERISTICS (VCC+ = +5 V, VCC- = -5 V, R L = 390 11, CL = 15 pF, T A = 25'C. See Test Circuit)
tPLH (S)
Propagation Delay Time
tPHL (S)
6-55
II
FAIRCHILD. 55/75107A. 55/751078. 55/75108A. 55/751088
TRUTH TABLE
RECOMMENDED COMBINATIONS
OF INPUT VOL TAGE FOR
LINE RECEIVERS
DIFFERENTIAL
INPUTS
STROBES
A-B
VID;' 25 mV
OUTPUT
G
S
Lor H
Lor H
H
Lor H
L
H
L
Lor H
H
H
H
INDETERMINATE
Lor H
L
H
L
Lor H
H
H
H
L
-25 mV < VID <25 mV
VID <-25 mV
TYPICAL PERFORMANCE CURVES
OUTPUT VOLTAGE
AS A FUNCTION OF
DIFFERENTIAL
INPUT VOLTAGE
,
,
,-
1NPr S
,
No1NVEL,NG
t-- f- /
INPUtS
--
--------
:cc' 0_"_
,
T~~~5'C
0
-30
-20
-
I--
55107A/B
75107AiB
2
-40
HIGH LOGIC LEVEL
SUPPLY CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE
55/75107A, 55/75107B
PROPAGATION DELAY TIME
(DIFFERENTIAL INPUTS)
AS A FUNCTION OF
AMBIENT TEMPERATURE
75108AiB
751OBAI8
INveJTlNG
INPUT HIGH CURRENT
INTO 1A OR 2A
AS A FUNCTION OF
AMBIENT TEMPERATURE
10
i
1.-...75107AiB _I
1- 75108A/B,
r
I
---
0
DIFFERENTIAL INPUT VOLTAGE - mV
55/75108A, 55/75108B
PROPAGATION DELAY TIME
LOW-TO-HIGH LEVEL
AS A FUNCTION OF
AMBIENT TEMPERATURE
AMBIENT TEMPERATURE _ °C
55/75108A, 55/75108B
PROPAGATION DELAY TIME
HIGH-TO-LOW LEVEL
AS A FUNCTION OF
AMBIENT TEMPERATURE
0
,
_I _
,!
0
,
0
,
0
55/75107A, 55/75107B
PROPAGATION DELAY TIME
(STROBE INPUTS)
AS A FUNCTION OF
AMBIENT TEMPERATURE
I
:;,;,;'1 v
:r-RL39l
'c
AMBIENT TEMPERATURE -
AMBIENT TEMPERATURE -
55/75108A, 55/75108B
PROPAGATION DELAY TIME
(STROBE INPUTS)
AS A FUNCTION OF
AMBIENT TEMPERATURE
o5
o
r-7S108A/B--I
I
,
I
0
,
f--75107A/B---1
1-
195 00
1
0;;'
w
~
5 V
-5 V
,~- 'M
I
::::=:::~
'c
-tl-----
')'1
I
I
I
I
AMBIENT TEMPERATURE -"C
AMBIENT TEMPERATURE -
I
I
r~U-j(SII
o_ILus\
,
r
0
I
--75108A!~A
~
/'
V
k:::
"c
NOTES:
1. These voltages are with respect to network ground terminal.
2. These voltage values are at the noninverting (+) terminal with respect to the inverting (-) terminal.
3.
For Hermetic DIP rating applies to ambient temperatures up to 70°C, above 70°C derate linearly at 8.3 mW/oC. For Flatpak derate linearly
at 7.1 mW/oC above 60°C.
4. For 55107A/8 and 55108A/8 guaranteed supply voltage range is ±4.5 V to ±5.5 V. Operating temperature range is _55°C ~ TA ~ +125°C.
For 75107A/8 and 75108A/B guaranteed supply voltage range is ±4.75 V to ±5.25 V. Operating temperature range is O°C ~ TA ~ 70°C.
5. Note more than one (1) output should be shorted at a time.
6. VCC- Max implies VCC_ = -5.5 V or -5.25 V, depending on device type.
6-56
FAIRCHILD. 55/75107A. 55/751078. 55/75108A. 55/751088
AC CHARACTERISTICS
AC TEST CIRCUIT
DIFFERENTIAL
INPUT
OUTPUT
55107A/B
75107A1B
See Note4
OUTPUT
i---.~-+--WI,--+--'-------<>55108A/B
75108A!B
STROBE
INPUT
o-----~---+-Wl,-___,
See Notf>?
II
NOTES:
1. The pulse generators have the following characteristics:
PRR ~ 500 kHz.
Zout "" 50 st, tr
=
tf
=
10 t
5 ns, tp1 = 500 ns, PRR
=
1 MHz, tp2 = 1 }is,
2.
Strobe input pulse is applied to Strobe A when inputs A1-A2 are being tested: to common Strobe when inputs A1-A2 or B1-82 are being
tested, and to Strobe B when inputs B 1 82 are being tested.
3.
4.
CL includes probe and jig capacitance.
All diodes are 1 N916.
VOLTAGE WAVEFORMS
----200mV
INPUT A
~---OV
3V
STROBE INPUT
A orS
~---------'~----OV
,-------\-r---OUTPUT A
6-57
V OH
FAIRCHILD. 55/75107A. 55/751076. 55/75108A. 55/751086
APPLICATION
BASIC BALANCED-LINE TRANSMISSION SYSTEM
TWISTED-PAIR OR EQUIVALENT
TRANSMISSION LINE
DATA 1
INPUT 2
INHIBIT
Zo=2Ar
STROBES
A
-I
DRIVER
RECEIVER
The
55/75107A/B dual line circuits are designed specifically for use in high speed data transmission systems that utilize balanced,
terminated transmission lines such as twisted~pair lines. The system operates in the balanced mode, so that noise induced on one line is
also induced on the other. The noise appears common-mode at the receiver input terminals where it is rejected. The ground connection
between the line driver and receiver is not part of the signal circuit so that system performance is not affected by circulating ground currents.
The unique driver output circuit allows terminated transmission lines to be driven at normal line impedances. High speed system operation is
ensured since line reflections are virtually eliminated when terminated lines are used. Cross·talk is minimized by low signal amplitudes and low
line impedances.
The typical data delay in a system is approximately (30+ 1.3L) ns, where L is the distance in feet separating the driver and receiver. This
delay includes one gate delay in both the driver and receiver.
Data is impressed on the balanced-line system by unbalancing the line voltages with the driver output current. The driven line is selected by
appropriate driver·input logic levels. The voltage difference is approximately:
VDIFF ~ 1/2 IOUT(on) • RT
High series line resistance will cause degradation of the signal. The receivers, however, will detect signals as low as 25 mV (or less). For normal
line resistances, data may be recovered from lines of several thousand feet in length.
Line-termination resistors (RT) are required only at the extreme ends of the line. For short lines, termination resistors at the receiver only may
prove adequate. The signal amplitude will then be approximately:
VOIFF ~ IOUT(on) • RT
DATA-BUS OR PARTY-LINE SYSTEM
RECEIVER 1
RECEIVER 2
STROBES
STROBES
RECEIVER 4
TWISTED·PAIR LINE
STROBES
RT
LOCATION 2
DRIVER 3
LOCATION 1
DRIVER 4
LOCATION 4
The strobe feature of the receivers and the inhibit feature of the drivers allow the 55/75107A/B dual line circuits to be used in data-bus or
party-line systems. In these applications, several drivers and receivers may share a common transmission line. An enabled driver transmits data
to all enabled receivers on the line while other drivers and receivers are disabled. Data is thus time-multiplexed on the transmission line. The
55/75107A/B device specifications allow widely varying thermal and electrical environments at the various driver and receiver locations.
The data-bus system offers maximum performance at minimum cost.
6-58
FAIRCHILD. 55/75107A. 55/751078. 55/75108A. 55/751088
APPLICATION (Cant'd)
UNBALANCED OR SINGLE·LINE SYSTEMS
55/75107A/B OR
55/75108A!B
INPUT~
V REF
o---------V"
~ OUTPUT
STROBES
The
55175107A/B
dual line circuits may also be used in unbalanced or single·line systems. Although these systems do not offer the same
performance as balanced systems for long lines, they are adequate for very short lines where environment noise is not severe.
The receiver threshold level is established by applying a de reference voltage to one receiver input terminal. The signal from the transmission
line is applied to the remaining input. The reference voltage should be optimized so that signal swing is symmetrical about it for maximum
noise margin. The reference voltage should be in the range of -3.0 V to +3.0 V. It can be provided by a voltage supply or by a voltage divider
from an available supply voltage.
•
PRECAUTIONS IN THE USE OF 55175107A/B AND 55/75108A/B DUAL LINE RECEIVERS
The following precaution should be observed when using or testing
55/75107 AlB
line circuits:
When only one receiver in a package )s being used, at least one of the differential inputs of the unused receiver should be terminated at some
voltage between -3.0 V and +3.0 V, preferably at ground. Failure to do so will cause improper operation of the unit being used because of
common bias circuitry for the current sources of the two receivers.
INCREASING COMMON·MODE INPUT
VOLTAGE RANGE OF RECEIVER
551 08A1751 08A DOT· OR OUTPUT CONNECTIONS
R'
R2
R2
-::-
>-;::::f~)o.--l:::r~-o
R'
OUTPUT
FOR BALANCED, TERMINATED LINES,
ZOUT = 2Rl + 2R2
The 55/75107A/B
and 55/75108A/B
line receivers feature a
common·mode input voltage range of ±3.0 V. This satisfies the require-
ments for all but the noisiest system applications. For these severe 'noise
environments, the common-mode range can be extended by the use of
external input attenuators. Common-mode input voltages can in this
way be reduced to ±3.0 V at the receiver input terminals. Differential
data signals will be reduced proportionately. Input sensitivity, input
The
55/75108A/B
line receivers feature an open·collector-output
circuit that can be connected in the DOT-OR logic configuration with
other
55/75108A/B
outputs. This allows a level of logic to be
implemented without additional logic delay.
impedance and delay times will be adversely affected.
6-59
75154
QUAD LI NE RECEIVER
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION -
The 75154 is a monolithic quadruple line receiver designed to satisfy
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 68 98
PACKAGE CODES D P
the requirements of the standard interface between data terminal equipment and data communication
equipment as defined by EIA Standard RS-232C. Other applications are for relatively sllOrt, single·line,
point-ta-point data transmission and for level translators. Operation is normally from a single 5 V
supply; however, a built-in option allows operation from a 12 V supply without the use of additional
components. The output is compatible with most TTL and DTL circuits when either supply
voltage is used.
In normal operation, the threshold control terminals are connected to the VCC1 terminal, pin 15,
even jf power is being supplied via the alternate VCC2 terminal, pin 16. This provides a wide hysteresis
loop which is the difference between the positive~going and negative-going threshold voltages. In this
mode of operation, if the input voltage goes to zero, the output voltage will remain LOW or HIGH as
determined by the previous input.
For fail~safe operation, the threshold~control terminals are open. This reduces the hysteresis loop by
causing the negative-going threshold voltage to be above zero. The positive~going threshold voltage
remains above zero as it is unaffected by the disposition of the threshold terminals. In the fail-safe
mode, if the input voltage goes to zero or an open~circuit condition, the output will go HIGH
regardless of the previous input condition.
•
•
•
•
v CC2
v CC1
1T
The 75154 is characterized for operation from 0° C to 70° C.
•
•
3T
2T
INPUT RESISTANCE ... 3 kn TO 7 kn OVER FULL RS-232C VOLTAGE RANGE
INPUT THRESHOLD ADJUSTABLE TO MEET FAIL-SAFE REQUIREMENTS WITHOUT
USING EXTERNAL COMPONENTS
BUILT-IN HYSTERESIS FOR INCREASED NOISE IMMUNITY
INVERTING OUTPUT COMPATIBLE WITH DTL OR TTL
OUTPUT WITH ACTIVE PULL-UP FOR SYMMETRICAL SWITCHING SPEEDS
STANDARD SUPPLY VOLTAGES ... 5 V OR 12 V
4T
IN A
OUT A
IN B
OUT B
IN C
OUT C
IN D
OUT 0
GND
R1
ORDER INFORMATION
TYPE
PART NO.
75154DC
75154
75154
75154PC
EQUIVALENT CIRCUIT
---------1
1---
COMMON TO 4 CIRCUITS
1 OF 4 RECEIVERS
5 kD
VCC2 o--+----~--...,
SEE NOTE
1.6 kn
l.4kn
BELOW
1.6 kD
I
I
I
140n
+---t--~,t+·~-+--~-I~
OPERATION -
OPERATION
NOTE
4.
For normal operation, the threshold controls are connected to V CC1, pin 15. For fail-safe operation, the threshold controls are open.
DC TEST CIRCUITSt
5,5V
o
0
13.2V
NOTES:
A. Momentarily apply -5 V, then 0.8 V.
B. Momentarily apply 5 V, then ground.
tArrows indicate actual direction of current flow. Current into a terminal is a positive value.
TEST TABLE
MEASURE
IN
T
OUT
VCCl
(PIN 151
Open-circuit input
VOH
Open
Open
IOH
4.5 V
Open
(fail safel
VOH
Open
Open
IOH
Open
10.8 V
VT+ min,
VOH
0.8 V
Open
IOH
5.5 V
Open
VT _ min (fail safe I
VOH
0.8 V
Open
IOH
Open
13.2 V
VOH
Note A
Pin 15
IOH
5.5 V and T
Open
VOH
Note A
Pin 15
IOH
T
13.2 V
Vll max,
VOH
-3 V
Pin 15
IOH
5.5 V and T
Open
VT _ min (normal I
VOH
-3 V
Pin 15
IOH
T
13.2 V
VIH min, VT+ max,
Val
3V
Open
IOl
4.5 V
Open
VT _ max (fail safel
Val
3V
Open
IOl
Open
10.8 V
VIH min, VT+ max
Val
3V
Pin 15
IOl
4.5 V and T
Open
(normal I
Val
3V
Pin 15
IOl
T
10.8 V
Val
Note B
Pin 15
IOl
5.5 V and T
Open
Val
Note B
Pin 15
IOl
T
13.2 V
TEST
VT+ min (normall
VT _ max (normal I
Fig. 1 VIH, Vll, VT+, VT_, VOH, Val.
6-62
VCC2
(PIN 161
FAIRCHILD. 75154
DC TEST CIRCUITSt (Cant'd)
TEST TABLE
VCCl
(PIN 15)
T
Open
5V
Open
Open
GND
Open
Open
Open
OUT
I
>0------;-- OPEN
VCC2
(PIN 16)
Open
Pin 15
T and 5 V
Open
Open
GND
GND
Open
Open
12V
Open
Open
GND
Pin 15
T
12 V
Pin 15
T
GND
Pin 15
T
Open
Fig. 2 RI
II
5.5V:1_[<>--<> 13.2 V
0
TEST TABLE
OPEN
I: -1
15
T
~
16
V CC2 - - -
Rll
OUTI
><>---+1-
V'(OtENlL'
i ---f---
J
OPEN
VCCl
(PIN 15)
VCC2
(PIN 16)
Open
Open
5.5 V
Pin 15
5.5 V
Open
Open
Open
13.2 V
Pin 15
T
13.2 V
Fig. 3 Vl(open)
OPEN
~T
-5.0 V
5.5 V
OPEN
OPEN
_h~6_~
V ee1
V CC2
Rl
liN
I
L
I
OUT
I
I /,os
---J--- J
GND
Each output is tested separately.
Fig.4 lOS
6-63
FAIRCHILD. 75154
DC TEST CIRCUITSt (Cont'd)
5.5V }CC~j~-f:j'CC~ 13.2V
OPEN
OPEN
I"i
-
I ....r
Vee1
VCC2
_--11I
Rl
DUTI
>0---=-;-OPEN
5.0V
All four line receivers are tested simultaneously.
Fig. 5 ICC
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
AC CHARACTERISTICS
TEST CIRCUIT
5.0V
INPUT
OPEN
OPEN
15_~_~_
Vee1
Al
VCC2
OUTPUT
I
OUTI
PULSE
GENERATOR
(SEE NOTE A)
L
----r---GND
J
r
CL "" 50 pF
{SEE NOTE 81
VOL TAGE WAVEFORMS
INPUT
OUTPUT
NOTES:
A. The pulse generator has the following characteristics: Zout = 50
B. CL includes probe and jig capacitance.
C. All diodes are 1 N3064
6-64
.n, tw = 200 ns, duty cycle'" 20%.
9613
DUAL DIFFERENTIAL LINE RECEIVER
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The 9613 is a Dual Differential Line Receiver designed to receive
differential digital data from transmission lines and operate over the military and industrial tempera-
ture range using a single 5.0 V supply. It can receive ± 500 mV of differential data in the presence of
high level (± 15 V) common mode voltag es and deliver undistrubed TTL logic to the output.
CONNECTION DIAGRAM
8-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 9T 6T
PACKAGE CODES T
R
•
•
•
•
TTL COMPATIBLE OUTPUT
HIGH COMMON MODE VOLTAGE RANGE
SINGLE 5.0 V SUPPLY VOLTAGES
MILITARY TEMPERATURE RANGE
OUT A
vee
+IN A
OUT B
-IN A
+\N B
GND
-IN B
ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Supply Voltage (VCC Potential to Ground)
Input Voltage Referred to Ground (Pins 2, 3, 5, 6)
Differential Input Voltage (+ Input Referred to - Input)
-0.5 V to +7.0 V
±20 V
±20 V
Internal Power Dissipation
Molded DIP, Hermetic DIP (Note 1)
800 mW
Operating Temperature
_55 0 C to +125° C
aoc to +70°C
-65"C to +150°C
9613
9613C
Storage Temperature
Pin Temperatur~
9613 Hermetic DIP (Soldering, 60 s)
9613C Molded DIP (Soldering, 10 s)
ORDER INFORMATION
TYPE
PART NO,
9613
9613RM
9613C
9613RC
9613TC
9613C
NOTES:
1.
Rating applies to ambient temperatures up to 30o e. Above 300
5.4 mW/
°c
for Molded DIP and 6.7 mW!
°c
e
ambient derate linearly at
for Hermetic DIP.
EQUIVALENT CIRCUIT (1/29613)
64 k
1.
t------+-1.5k--+--+8----+-.36k
8.36k
- INPUTS
~~15~)+--+------+-----~--~
-rr H
-t~ '''~
5k
---{
3k
OUTPUTS
~----~---i---r~1(7)
+ INPUTS
216)
r
6-65
TO OTHER
RECEIVER
•
FAIRCHILD. 9613
9613
ELECTRICAL CHARACTERISTICS: V CC ~ 5.0 V ± 10%, -55°C <; T A <; 125°C unless otherwise specified.
SYMBOL
CHARACTERISTICS
CONDITIONS
VOL
Output Low Voltage
IOL
~
16 rnA
VOH
ISC
Output High Voltage
IOH
~
-5 rnA
Output Short-Circuit Current
VOUT-OV
RIN
Input Resistance
VCM
Operating Common Mode Voltage Range
-1.0 V <; VDIFF <; +1.0 V
VTH
Differential Input Threshold Voltage
ICC
Power Supply Current
MIN
TYP
MAX
UNITS
0.4
2.4
-60
0.28
3.0
-28
V
V
rnA
3.0
4.2
-12
k!1
-15
+15
V
-5.0 V <; V CM <; +5.0 V
-0.5
+0.5
V
-15 V <; VCM <; +15 V
-1.0
VCC
~
+1.0
5.25 V
29
V
50
rnA
IMAX
Maximum Supply Current
VCC-7.0V
42
70
rnA
tpLH
Propagation Delay Time
TA ~ 25°C; VCC ~ 5.0 V; See
AC Test Circu it and Waveforms
25
40
ns
tpHL
Propagation Delay Time
TA ~ 25°C; VCC ~ 5.0 V; See
23
40
ns
AC Test Circuit and Waveforms
9613C
ELECTRICAL CHARACTERISTICS: V CC ~ 5.0 V ± 5%, O°C <; T A <; 70°C unless otherwise specified.
SYMBOL
CONDITIONS
CHARACTERISTICS
VOL
Output Low Voltage
IOL~16mA
VOH
ISC
Output High Voltage
-5 rnA
VOUT OV
RIN
Input Resistance
VCM
Operating Common Mode Voltage Range
-1.0 V <; VOIFF <; +1.0 V
VTH
Differential Input Threshold Voltage
IOH
Output Short-Circuit Current
ICC
Power Supply Current
IMAX
tpLH
~
MIN
TYP
MAX
UNITS
0.4
2.4
0.28
3.0
60
28
12
V
V
rnA
3.0
4.2
k!1
-15
+15
V
-5.0 V <; V CM <; +5.0 V
-0.5
+0.5
V
-15 V <; VCM <; +15 V
-1.0
+1.0
VCC - 5.25 V
29
Maximum Supply CUrrent
VCC - 7.0 V
Propagation Delay Time
TA ~ 25°C; VCC ~ 5.0 V; See
V
50
rnA
42
70
rnA
25
40
ns
23
40
ns
AC Test Circuit and Waveforms
tpHL
Propagation Delay Time
TA ~ 25°C; VCC ~ 5.0 V; See
AC Test Circuit and Waveforms
AC TEST CIRCUIT AND WAVEFORMS
V CC "'5.0V
~
3;;~
VINo---::.»
~i ~
;>0'_17.,1p-......,.......,IK·,A:/_....,
-13.51 t- ~
lr
cl
1/29613
3;;n !All DIODES
FD777 OR
-=-
-=-
V IN: (PU LSE)
Amplitude: 6.0 V
Pulse Width: 100 ns
Duty Cycle: 50 %
tr = tf
<5
ns
C L = 30 pF ±5 % I nclud ing jig capacitance.
6-66
EQUIVALENT
FAIRCHILD. 9613
TYPICAL ELECTRICAL CHARACTERISTICS CURVES
9613
INPUT DIFFERENTIAL
THRESHOLD AMBIGUITY
AS A FUNCTION OF
COMMON MODE
INPUT VOLTAGE
INPUT/OUTPUT TRANSFER
CHARACTERISTIC AS A
FUNCTION OF POWER
SUPPLY VOLTAGE
I-+-I++-+_~~~SW~TVCHING CIRCUIT
40
~)CC ~_25 J_t--F~R OUTPUT LOAO
INPUT CURRENT AS A
FUNCTION OF
INPUT VOLTAGE
."
iA .',;,,'
0
[
3D_ Vee
0 __
0_
r- -.t---0,_
OUTPUT HIGH CURRENT
AS A FUNCTION OF
OUTPUT HIGH VOLTAGE
OUTPUT LOW CURRENT
AS A FUNCTION OF
OUTPUT LOW VOLTAGE
0
'A
T A ~ 25°C
I
2S"C
0
Vee - u;,
~
VCC~5,25
V
~
uf'vcc
0
:-
4.75 V
~
0
V
c-'
1/
-
I
I
-t- -+- ~+- r-
-+
.-
V~H<)D Jec
I
'"
"
;
-
4 75V, 'Ol-! ~
:
_sOm!>.
I
I
[
I
0
"
L
7
tY ~
.-
; - -'O<,@'"
-- 0
-b
-.-
V
r-
OUTPUT VOLTAGE AS
A FUNCTION OF
AMBIENT TEMPERATURE
I II
V_ /
c--i
If.
Ii
I
POWER SUPPLY CURRENT
AS A FUNCTION OF
POWER SUPPLY VOLTAGE
.-
I
Vee -- 5.0 V
0
-+
. ;',
0
=
eo
0
,
;,0
o
,
o
,,;J
<
oc
16m~
,
;
OUTPUT HIGH VOLTAGE - V
POWER SUPPLY CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE
PROPAGATION DELAY
AS A FUNCTION OF
AMBIENT TEMPERATURE
0
.;:';\
T A ~ 25°C
0
0
0
Vee
~
L
o
o
'/
~ 2"
~
~", : ~','.
"rT-
S.DV
TEST CIRCUIT
I
0
I
~
V
SEE SWITCHING - + - + - - + - + - - 1
'"
I
!PL!!-~--
0
tpHL
i
0
0
j
0
0
6-67
FAIRCHILD. 9613
Photograph of a 9613 switching differential data in the presence
of high common mode noise.
+INPUTA=t>--{>- [
OUTPUT A
-INPUT A
_
VERTICAL
0
2.0 V DIV. HORIZONTAL
Fig. 1
STANDARD USAGE
I
--JH
W:-----LJ
, L_ _ _
~
TTL LOGIC
I
I
For example of operation see 9612 data sheet application section.
Fig. 2
6-68
0
50 ns/DIV.
9615
DUAL DIFFERENTIAL LINE RECEIVER
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The 9615 is a Dual Differential Line Receiver designed to receive
differential digital data from transmission lines and operate over the military and industrial temperature
ranges using a single 5 V supply. It can receive ±500 mV of differential data in the presence of high
level (± 15 V) common mode voltages and deliver undisturbed TTL logic to the output.
CONNECTION DIAGRAM
16·PIN
(TOP VIEW)
PACKAGE OUTLINES 68 98 4L
PACKAGE CODES D
P F
The,response time can be controlled by use of an external capacitor. A strobe and a 130 n terminating
resistor are provided at the inputs. The output has an uncommitted collector with an active pull up
available on an adjacent pin to allow either wire·OR or active pull up TTL output configuration.
•
•
•
TTL COMPATIBLE OUTPUT
HIGH COMMON MODE VOL TAGE RANGE
CHOICE OF AN UNCOMMITTED COLLECTOR OR ACTIVE PULL UP
•
•
•
•
•
STROBE
FULL MILITARY TEMPERATURE RANGE
SINGLE 5 V SUPPLY VOL TAGES
FREQUENCY RESPONSE CONTROL
130 n TERMINATING RESISTOR
vee
OUT A
ACTIV\E
PULL UP A
OUT B
STROBE A
RESP A
+IN A
ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
-65°C to +150°C
VCC Pin Potential to Ground Pin
-0.5 V to +7.0 V
Input Voltage Referred to Ground (Pins 5, 6, 7, 9,10,11)
±20 V
Voltage Applied to Outputs for HIGH output State without Active Pull Up -0.5 V to +13.2 V
Voltage Applied to Strobe
-0.5 V to +5.5 V
Pin Temperature Range
Hermetic DIP, Flatpak (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
Internal Power Dissipation (Note 1)
Operating Temperature Range
Military (9615)
Commercial (9615C)
RESP B
130n
+IN B
-IN A
130n
-IN B
GND
3000 e
260°C
ORDER INFORMATION
TYPE
PART NO.
9615
9615DM
9615FM
9615
9615DC
9615C
9615C
9615PC
670mW
_55°C to +125°C
O°C to +70°C
NOTE:
1. For Hermetic DIP rating applies to ambient temperatures up to 70o e, above 700
at 8.3 mwtC. For the Flatpak, derate linearly at 7.1 mwtC above 60°C.
e
derate linearly
EQUIVALENT CIRCUIT (1/29615)
1.64k
1.5k
1.64k
8.36k
8.36k
ACT.
INPUTS
7
PULLUP
;===~~Ilt 2.5k
191
INPUTS
5
1.1
pF
1151
OUTPUTS
1111
1.5k
7k
1101
TO OTHER
RECEIVER
6-69
I
9615
ELECTRICAL CHARACTERISTICS: VCC~ 5.0V:!: 10%
LIMITS
SYMBOL
_55°C
CHARACTER ISTICS
MIN.
'f
Cj
VOL
Output LOW Voltage
VOH
Output H IG H Voltage
ICEX
Output Leakage Current
ISC
Output Shorted Current
liN
I nput Current
IIN(ST)
Strobe I nput Current
+25°C
MAX.
0.40
2.2
VCM
~nput
MAX.
0.18
0.40
2.4
3.2
-15
-39
-80
-0.49
-0.7
-1.15
-2.4
-0.9
Current
Common Mode Voltage
-15
+15
-1.2
-3.4
-15
±17.5
Strobe Input
IR(ST)
RIN
VTH-l(-**
+125°C
TYP.
MIN.
200
-0.7
VCC
~
4.5 V, VOUT
VCC - 4.5 V, VOUT-
..
IOH = -5.0 rnA, 'VOIFF = -0.5 V
VCC - 5.5 V, "Vsc - 0 V,'VOIFF - -0.5 V
rnA
VCC = 5.5 V, VIN = 0.4 V
:lJ
:!:
VCC - 5.5 V, VIN - 0.4 V
r
'VOIFF ~ 0.5 V
C
VCC = 5.5 V, 'VOIFF ~ 0.5 V
+15
V
VCC ~ 5.0 V, 'VOIFF = +1.0V
5.0
J.!.A
-500
500
rnV
-1.0
1.0
-15
n
77
130
167
-500
80
500
Threshold Voltage
-1.0
1.0
-1.0
28.7
50
rnA
V
VCC ~ 4.5 V, 'VOIFF = -0.5 V
VR =4.5 V
VCC ~ 5.0 V, VIN(R) = 1.0 V, +Input = GNO
J
VCM - 0
-15" VCM" +15vj
VCC
~
5.5 V, -Inputs
ICC
Power Supply Current
tplH
Turn-Off Time
30
50
ns
Rl - 3.9
tPHl
Turn-On Time
30
50
ns
Rl - 390
-- - - - - - ----
*VOIFF isadifferential input voltage referred from "+IN A" to"-IN A" and from "+IN B" to "-IN S".
'T1
~
o
Other Input = 5.5 V
rnA
500
* * *See input-output transfer characteristic graphs on following pages.
••
VCEX -12 V, 'VOIFF -VCC - 4.5 V
-500
* *Connect Output "A" to Active Pull up "A" and Output "8" to Active Pull up "8".
~
IOl = 15.0 rnA, 'VOIFF ~ 0.5 V
J.!.A
Differential Input
Input Resistor
CONOITIONS
rnA
rnA
2.0
Leakage Current
V
V
2.4
+15
UNITS
MAX.
0.40
100
Response Control
IIN(R-C)
MIN.
VCC
~
~ 5.0V ±,10%
0 V, +Inputs = 0.5 V
kn, VCC - 5.0 V, Cl - 30 pF, Fig. 1
n, VCC - 5.0 V, CL - 30 pF, Fig. 1
•
CO
en
.....
U1
9615C
ELECTRICAL CHARACTERISTICS: VCC: 5.0V :!:5%
LIMITS
SYMBOL
DoC
CHARACTERISTICS
MIN.
'f
j
VOL
Output lOW Voltage
VOH
Output H IG H Voltage
ICEX
Output Leakage Current
ISC
Output Shorted Current
liN
Input Current
IIN(STI
Strobe Input Current
+25°C
MAX.
0.45
2.4
2.4
MAX.
0.25
0.45
3.3
MIN.
I nput Current
-15
+15
UNITS
2.4
-0.7
-1.15
-2.4
-1.2
-3.4
-15
±17.5
V
V
200
-100
-0.49
-0.7
+15
Leakage Current
Input Resistor
RIN
VTH
5.0
* ••
VCC - 5.25 V, *'VSC - 0 V, 'VOIFF - -{l.5 V
mA
V
130
179
-80
500
-500
500
1.0
-1.0
1.0
-500
500
-500
Threshold Voltage
-1.0
1.0
-1.0
Power Supply Current
tPlH
Turn-Off Time
tpHl
Turn-On Time
28.7
30
-
---------
---
30
-- --
---
-
-
.I'A
n
74
Differential Input
ICC
10
mV
V
VCC: 5.25 V, VIN - 0.45 V
:!:
'VOIFF = 0.5 V
o
•
VCC = 5.25 V, 'VOIFF = 0.5 V
CO
en
-"
U1
VCC - 4.75 V, *VOIFF - -{l.5 V
VR =4.5V
VCC = 5.0 V, VIN(RI = 1.0 V, +Input
J
VCM - OV
-15 <:; VCM <:; +15V
ns
Rl - 3.9
75
ns
Rl - 390
•
r-
VCC = 5.0 V, 'VOIFF = 1.0V
75
*VOIFF is a differential input voltage referred from "+IN A" to "-IN A" and from "+IN Bit to "-IN B".
o
VCC = 5.25 V, VIN = 0.45 V
mA
* "'Connect Output "A" to Active Pull up "Att and Output "8" to Active Pull up "8".
*** See input-output transfer characteristic graphs on following pages.
~
::0
Other Input: 5.25 V
50
-
"
IOH : -5.0 mA, 'VDIFF : -{l.5 V
VCEX - 5.25 V, ~VOIFF - VCC - 4.75 V
Strobe Input
IR(STI
IOl: 15.0 mA, 'VDIFF : 0.5 V
VCC - 4.75 V, VOUT-
I'A
mA
-15
VCC : 4.75 V, VOUT : "
mA
mA
+15
CONDITIONS
MAX.
0.45
100
-0.9
Common Mode Voltage
VCM
+70°C
TYP.
-14
Response Control
IIN(R-CI
MIN.
I
= GNO
VCC = 5.0V ± 5%
VCC = 5.25 V, +Inputs = 0.5 V, -Inputs = 0 V
kn, VCC - 5.0 V, CL - 30 pF, Fig.1
n, VCC - 5.0 V, CL - 30 pF, Fig. 1
FAIRCHILD. 9615
TYPICAL ELECTRICAL CHARACTERISTICS FOR 9615 AND 9615C
OUTPUT LOW VOL TAGE
AS A FUNCTION OF
OUTPUT LOW CURRENT
JOO
OUTPUT HIGH VOLTAGE
AS A FUNCTION OF
OUTPUT HIGH CURRENT
,.
0
4.
or--.
I
TA "25 D C
~
100
Vee·4.~~7'
-I
vee ·S.5V
V0
~
~
3.0
~
2. 0
--rv7-t;'
r-
I--- r-
kfl
100
--
r--
~
c
0
o
o
-20
·10
TA " 25'C
~ 4. 0
_VCC· 4•5V
3. 0
TA
0
".1
".2
I"
.Izsoc
0.1
0.2
TA ' _5S C
6.0
3.0
0
-0.4 -0.3
-0.2
'.0
0.1
0.2
0.3
0.4
o
1.0
4.0
3.0
2.0
INPUT CURRENT
AS A FUNCTION OF
INPUT VOL TAGE
6.0
TA ' 2:5 e
1/
Vee" 5.0V
UNTESTED INPUT 'OV
4.0
Vee ±5.0V
TA "2:5°e
Vee "4.5 V
3.0
\
.~
1.0
4.0
3.0
2.0
o
~~
I
-~
-15
POWER SUPPLY CURRENT
AS A FUNCTION OF
POWER SUPPLY VOL TAGE
70
I
60
WITH1ACTIVEIpULL
u~
o.ov
-10
5
w
0
5
I{)
IS
I
+ INPUTS
PULL DOWN ONLY
- INPUTS' OV
-Vee
.~
/'
V
20
25
~
/-
0
70
00
60
I
I
5.0
6.0
POWER SUPPLY VOLTAGE - V
~
-5
~
0
5
ro
e
~c'c.= 5.0V
I !
_V;;' -lVI,
~
0
\3O;f 7
40
j'UT('I
I---
,...-
20
l,L -
L-1
"- ;--.
30
~
--
tpLH
RL "3.9HI_ -
0
-INPUTS-Y ce
~
SWITCHING TIME
AS A FUNCTION OF
AMBIENT TEMPERATURE
V
/"
/
I;Hl
RL" 3900
Cl • 30pF
0
0
4.0
~
POWER SUPPLY CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE
tINPUT" vee
WITH rS'STOi P.ULt r 3.0
0
INPUT VOLTAGE-V
0
/0urs-r--o~.. ~.-
CONTROL PIN
~CR
Note: 1. CR>.Ol .uF may cause slowing of rise and fall
times of the output.
2. Due to the mechanism of induction of differential
noise, the use of the responce control is not
normaly needed.
CAPACITANCE->LF
6-73
=
50 ns/DIV
9617
TRIPLE EIA RS-232-C LINE RECEIVER
FAIRCHILD LINEAR INTEGRATED CIRCUIT
•
FOR NEW DESIGNS, THE ILA1489/1489A, 75154 OR THE 9637A ARE RECOMMENDED.
GENERAL DESCRIPTION - The 9617 is a monolithic Triple Line Receiver constructed using the
CONNECTION DIAGRAM
14·PIN DIP
(TOP VIEW)
PACKAGE OUTLINE 6A 9A
PACKAGE CODE D
P
Fairchild Planar* process. It is designed to meet the terminator electrical requirements of EIA RS~232-C
and CCITT V.24. It receives line signals produced by the 9616, an EIA/CCITT driver, and converts
them to TTL compatible logic levels. The inputs have a resistance between 3 kn and 7 kf2 and can
withstand ±25 V. Each receiver can operate in either hysteresis or non-hysteresis (slicing) modes, and
each receiver provides fail-safe operation as defined by Section 2.5 of RS-232-C. Noise immunity may
be increased by connecting a capacitor between the response control pin and ground.
For the hysteresis mode connect the RESP pin to the HYST pin, for the slicing mode leave these
pins open.
OUT A
•
•
•
•
•
•
MEETS ALL EIA RS·232-C AND CCITT V.24 SPECIFICATIONS
FAIL·SAFE OPERATION
HYSTERESIS OR NON-HYSTERESIS MODE
INDIVIDUAL RESPONSE CONTROLS
TTL COMPATIBLE OUTPUT
SINGLE +5 V SUPPLY
HYST A
RESP A
HYST B
IN A
RESP B
OUTC
IN B
HYST C
IN C
GND
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Input Voltage
Output Current
Internal Power Oissipation
Storage Temperature Range
Operating Temperature Range
Pin Temperature
Hermetic DIP (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
7V
±25 V
25mA
630mW
-65°C to +150°C
O°C to +70°C
vee
OUT B
RESP C
ORDER INFORMATION
TYPE
PART NO.
9617C
9617DC
9617C
9617PC
EQUIVALENT CIRCUIT (One of three identical circuits)
HY5T
c,
e,
e3
"'C
5kD
'kC
e6
ou,
21dl
RESP
"
e,
"" a3
I
Va,
a,
Hn
2~ 0,
e5
10k"
GND
*Planar is a patented Fairchild process.
6-74
FAIRCHILD • 9617
9617C
ELECTRICAL CHARACTERISTICS: V CC = +5.0 V ± 5%, T A = 25°C Response Pin Open, unless otherwise specified.
SYMBOL
CONDITIONS
CHARACTERISTICS
RIN
Input Resistance
VI = ±25V
EL
Input Voltage
Open Circuit
VTH+
Upper I nput Threshold Voltage
RESP - HYST Connected
VTH-
Lower Input Threshold Voltage
RESP - HYST Connected
VTHX
Open Loop Threshold Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
MIN
TYP
MAX
UNITS
3.0
4.0
7.0
kn
0.2
2.0
V
1.75
2.0
2.25
V
0.75
0.85
1.25
V
004
1.0
1.2
V
204
3.0
VIN = -3.0V, OV or open circuit
VCC = 4.5V, IL
=
-200"A
VIN = +3.0V
0.3
VCC = 4.5V, IL = 8.0mA
V
004
V
ISC
Output Short Circuit Current
Vo =OV
2.5
mA
ICC
Supply Current
VCC = +5.5V, VIN = 5.0V
12
mA
tpLH
Propagation Delay Time
RL = 3.9kn, Note 1
60
ns
tr
Rise Time
RL = 3.9kn , Note 1
150
ns
tpHL
Propagation Delay Time
RL = 390n ,Note 1
40
ns
Fall Time
RL = 390n ,Note 1
50
ns
tf
Note 1.
Vee
= 5.0 V, See AC Test Circuit and waveforms
I
AC TEST CIRCUIT
VOLTAGE WAVEFORMS
17I30V
,
'50V
IN
)_30V
0 V
50V
I
I
1/39617
o 8V
o 8V
Input Pulse Characteristics:
All diodes FDH600 or equivalent.
PRR
= 1 MHz
PW
= 500 ns
tr = tf = 10 ± 2 ns (10% to 90%)
NOTE: Wiring capacitance should be minimized between outputs, hysteresis and response pins.
6-75
9622
DUAL LINE RECEIVER
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The 9622 is a Dual Line Receiver designed to discriminate a worst case
logic swing of 2.0V from a ±10V common mode noise signal or ground shift. A 1.5V threshold is
built into the differential amplifier to offer a TTL compatible threshold voltage and maximum noise
immunity.
CONNECTION DIAGRAMS
14-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 6A 9A
p
PACKAGE CODES D
The offset is obtained by use of current sources and matched resistors and varies only
±5% (75 mY) over the military and industrial temperature ranges.
The 9622 allows the choice of output states with the inputs open without affecting circuit performance by use of S3 (Note 1). A 130[2 terminating resistor is provided at the input of each line
receiver. An enable is also provided for eachlline receiver. The output is TTL compatible. The
output HIGH level can be increased to +12V by tying it to a positive supply through a resistor. The
output circuits allow wired~OR operation.
•
•
•
•
•
•
•
•
•
TTL COMPATIBLE THRESHOLD VOL TAGE
INPUT TERMINATING RESISTORS
CHOICE OF OUTPUT STATE WITH INPUTS OPEN
TTL COMPATIBLE OUTPUT
HIGH COMMON MODE
WIRE-OR CAPABILITY
ENABLE INPUTS
FULL MILITARY TEMPERATURE RANGE
LOGIC COMPATIBLE SUPPLY VOLTAGES
GND
53
OUT B
OUT A
EN B
EN A
B+
A+
B 130,11
A 130n
B-
A-
ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Operating Temperature
Military (9622)
Commercial (9622C)
Internal Power Dissipation (Note 2)
Hermetic DIP, Molded DIP
VCC+ Pin Potential to Ground Pin
I nput Voltage
Voltage Applied to Outputs for Output HIGH State
VCC- Pin Potential to Ground Pin
Enable Pin Potential to Ground Pin
Pin Temperature
Hermetic DIP, (Soldering, 60 5)
Molded DIP, (Soldering, 10 s)
Vcc -
Vcc+
_55" C to +125" C
O°C to +70°C
670mW
--O.5V to +7V
±15V
-O.5V to +13.2V
-O.5V to -12V
-O.5V to +15V
ORDER INFORMATION
PART NO.
TYPE
9622DM
9622
9622DC
9622C
9622PC
9622C
NOTE
1. 53 connected to Vee-open inputs causes output to be HIGH.
53 connected to Ground-open inputs causes output to be LOW.
2.
Rating applies to ambient temperature up to 70°C. Above 70°C derate linearly at 8.3 rnW/C
for the Hermetic DIP.
EQUIVALENT CIRCUIT
veee 171
5kD
2kf1
2kH
5kH
5k.\1
2kD
6-76
2kH
2kD
5kH
2kD
ELECTRICAL CHARACTERISTICS: VCC+ = 5.0 V ± 10%, V CC- = -10 V ± 10%.
9622
LIMITS
SYMBOL
CHARACTER ISTICS
-55°C
MIN.
VOL
Output LOW Voltage
VOH
Output HI G H Vo ltage
ICE X
Output Leakage Current
ISC
Output Shorted Current
+25°C
MAX.
MIN.
0.40
2.8
TYP.
0.17
3.0
-3.1
MIN.
0.40
3.3
-1.4
-2.15
2.9
-3.1
-1.3
Enable Input
IR (ENABLE)
Leakage Current
Enable Input
IF (ENABLE)
Forward Current
+Input
IF (+Input)
Forward Current
-Input
IF (-Input)
9'
""""
VIL (ENABLE)
Forward Current
Input LOW Voltage
Differential Input
VTH
Thr~shold
Voltage
Volts
Volts
200
IlA
-3.1
rnA
2.0
5.0
IlA
-1.5
-0.96
-1.5
-1.5
rnA
-2.3
-1.67
-2.1
-2.0
rnA
-2.6
-1.87
-2.4
-2.3
rnA
1.3
1.0
UNITS
2.0
1.4
1.0
1.0
1.5
2.0
0.7
1.0
CONOITIONS
MAX.
0.40
100
50
-1.3
+125°C
MAX.
2.0
Volts
Volts
VCM
Common Mode Voltage
-10
±12
+10
Volts
100
130
175
n
R130n
Terminating Resistance
ICC
5 V Supply Current
13.7
22.9
rnA
lEE
-10 V Supply Current
-6.5
-11.1
rnA
tPLH
Turn-Off Time
38
50
tPHL
Turn-On Time
35
50
ns
ns
-
*VDIFF is a differential input voltage referred from A+ to A~ and from 8+ to B-.
•
VCC+ = 4.5 V
VCC- = -11 V
'VOIFF =2.0V
IOL = 12.4 rnA
VCC+ = 4.5 V
VCC- = -9.0 V
'VOIFF = 1.0 V
IOH = -0.2 rnA
VCC+ = 4.5 V
VCC- = -11 V
VCEX=12V
'VOIFF = 1.0 V
VCC+ = 5.0 V
VCC- - -10 V
'VOIFF = 1.0 V
VSC = 0 V
VCC+ = 4.5 V
S3=4.5V
VR=4.0V
Vec- = -11 V
VCC+ = 5.5 V
VCC- = -9.0 V
S~ =0
VF =0 V
V
VCC+ = 5.0 V
-Input = GNO
Vec- = -10 V
VF =0 V
'T1
!:
::0
VCC+, S3 - 5.0 V VCC- - -10 V
+Input = GNO
(')
VF =0 V
::I:
VCC+ = 5.0 V ±10 %
r
o
VCC- = -10 V ± 10 %
VCC+ = 5.0 V ±10 %
VCC- = -10 V ±10 %
VCC+ = 5.0 V
CD
Q)
VCC- = -10 V
I\)
I\)
'VOIFF = 1.0 V or 2.0 V
Vee+ = 5.5 V
VCC-
= -11 V
S3, + Inputs = 5.5 V, -Inputs = 0 V
VCC- - -11 V
Vee+ = 5.5 V
S3, + Inputs = 5.5 V, -Inputs = 0 V
VCC+ - 5.0 V
VIN Q-.3 V, RL
VCC- = -10 V
= 3.9 kn, CL = 30 pF See Ae Test Circuit
VCC- =-10V
VCC+ - 5.0 V
VIN Q-.3.0 V, RL = 0.39 kn, CL = 30 pF See AC Test Circuit
--
---
----
----
------
9622C
ELECTRICAL CHARACTERISTICS: V CC+ = 5.0 V ± 5%, V CC- = -10 V ± 5%.
LIMITS
OC C
CHARACTERISTICS
SYMBOL
MIN.
VOL
Output LOW Voltage
VOH
Output HIGH Voltage
ICEX
Output Leakage Current
ISC
Output Shorted Current
MIN.
0.45
2.9
TYP.
MAX.
0.17
0.45
3.0
3.3
-3.1
-1.4
-2.15
Enable Input
IR (ENABLE)
Enable Input
-1.5
-.96
UNITS
Volts
Volts
2.9
-3.2
-1.3
200
)1A
-3.1
rnA
-1.5
rnA
rnA
-2.9
-1.87
-2.7
-2.6
rnA
1.2
1.4
1.0
0.S5
Volts
1.0
1.5
2.0
2.0
Volts
VCM
Common Mode Voltage
-7.5
±12
+7.5
Volts
R130n
Terminating Resistance
91
130
185
n
ICC
5 V Supply Current
13.7
22.9
rnA
lEE
-10
-6.5
-11.1
rnA
tpLH
Turn-Off Time
38
100
tPHL
Turn-On Time
35
100
Forward Current
-.j
Input LOW Voltage
Differential Input
I
VCC- = -10.5 V
'VDIFF = 1.0 V
VCEX = 5.25 V
VCC+ = 5.0 V
VCC- = -10 V
'VDIFF = 1.0 V
VSC = 0 V
VCC+ = 4.75 V
VCC- = -10.5 V
S3 = 4.75 V
VR = 4.0 V
VCC+ = 5.25 V
VCC- = -9.5 V
VF = 0 V
-2.3
VTH
IOH = -0.2 rnA
VCC+ = 4.75 V
VCC- = -10 V
-2.4
VI L (ENABLE)
VCC- = -9.5 V
'VDIFF = 1.0 V
VCC+ = 5.0 V
-Input = GND
-1.67
'f
VCC+ = 4.75 V
S3 = 0 V
-Input
00
IOL = 14.1 rnA
Forward Current
Forward Current
IF (-Input)
VCC- = -10.5 V
'VDIFF =2.0V
+Input
-2.6
IF (+ Input)
VCC+ = 4.75 V
)1A
10
-1.5
CONDITIONS & COMMENTS
MAX.
0.45
"
Leakage Current
IF (ENABLE)
MIN.
100
SO
-1.3
70c C
+25°C
MAX.
Threshold Voltage
v Supply
Current
1.0
2.0
1.0
ns
ns
L.
*VOIFF is GIl differential input voltage referred from A+ to A- and from B+ to 8-.
"
!:
VF =0 V
JJ
o
VCC+, S3 - 5.0 V VCC- - -10 V
+Input = GND
:::t
VF = 0 V
r-
V CC+ = 5.0 V ±5 %
C
VCC- = -10 V ±5 %
V CC+ = 5.0 V ±5 %
<0
VCC- = -10 V ±5 %
VCC+ = 5.0 V
en
I\)
I\)
VCC- = -10 V
'VDIFF = 1.0 V or 2.0 V
VCC+ - 5.25 V
VCC- = -10.5 V
S3. +Inputs = 5.25 V, -Inputs = 0 V
VCC+ = 5.25 V
VCC- = -10.5 V
S3. + Inputs = 5.25 V. -Inputs = 0 V
VCC- = -10 V
VCC+ = 5.0 V
VIN 0~3.9 V. RL = 3.9 kn. CL = 30 pF See AC Test Circuit
VCC+ - 5.0 V
VIN
-_.
~3.0
--
---
VCC- = -10 V
V. RL = 0.39 kn. CL = 30 pF See AC Test Circuit
- - - - - - - - - - - - - - - - - - - - - - - - - - - _ . _ _. _ - -
-
FAIRCHILD • 9622
TYPICAL PERFORMANCE CURVES FOR 9622 AND 9622C
OUTPUT LOW VOLTAGE
AS A FUNCTION OF
OUTPUT LOW CURRENT
JO 0
'rc
~
LOGIC LEVELS
AS A FUNCTION OF
AMBIENT TEMPERATURE
~"",
- IOV
5
~
TA -2S"C
0
OUTPUT HIGH VOLTAGE
AS A FUNCTION OF
OUTPUT HIGH CURRENT
V
"~
100
V"""
5
0
00
W
100
1M
l~
INPUT CURRENT
AS A FUNCTION OF
INPUT VOLTAGE
I
I
f--+++---'-+--+ - 3.0
"
,
-~
1.0
-+
~±
-~~
!
I
10
I
0
1.2
1.8
-10
2.0
i-- -
-+-~
f--
1.0
~
AMBIEi'lTTE,\\PERAlURE - C
OUTPUT VOLTAGE
AS A FUNCTION OF
COMMON MODE VOLTAGE
i--+-+---ffi++--+-IH-HH+-+---j
-
..!.
',1.'0:A
mow
OUTPUT HIGH CURRENT - mA
1--
!
I
10
4.0
1.0--------
~~~~ : 4 I~~
I
T'iP' :ALV'OLV
VCC+=55V
-- -
I
5
VOUT - VDIFF TRANSFER
CHARACTERISTICS
-
!
I
0
15
2.0--
I
0
IOl OUTPUT LOW CURRENT -mA
3.0
I
5
o vee + ~ 5 ov
5.0
VOH :: I Oi-l ~ :0.21ll,A
I
!
~"'-
200
0
I
0
- - f--
---L-- ==
II
~
,-
I
!
VI ~
-4.0
-L1
=
2,0
0
;-
S.OV
L1
4.0
10
DIFFERENTIAL INPUT VOLTAGE-V
(OM,\\ON MODE VOLTAGE - V
iNPUTVOLTAGE-V
TURN ON TIME
AS A FUNCTION OF
AMBIENT TEMPERATURE
TURN OFF TIME
AS A FUNCTION OF
AMBIENT TEMPERATURE
POWER DISSIPATION
AS A FUNCTION OF
AMBIENT TEMPERATURE
-
I
=='t~
lCOPD''i'VCC-~45VVcC~
--4:':;:~~--
~F
o -r'bO
AMBIENT TEMPERATURE- °C
·20
0
AMBIENTTLMPERATUPL -'C
AC TEST CIRCUIT
WAVEFORMS
Vee
-:r
tPlH
I
tPHL
I
I I
VIN~.:
15V
ov--~:
VOUT
VOUT
~2~ ~
_
_'5V___
ov
~~
STANDARD USAGE
I
DRIVER SYSTEM
H
...._ _L_O_G_'C_ _..
'20
LINE DRIVER
Hf-H
I
I
6-79
r;
1+
cD
lO~
AMBIENT TEMPERATURE
RECEIVER SYSTEM
9622
H
LOGIC
_oc
J~O
9627
DUAL EIA RS-232-C/MIL-STD-188C LINE RECEIVER
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The 9627 is a Dual Line Receiver which meets the electrical interface
specifications of EIA RS·232~C and MIL-STO-188C. The input circuitry accomodates ±25V input
signals and the differential inputs allow user selection of either inverting or non-inverting logic for
the receiver operation. The 9627 provides both a selectable hysteresis range and selectable receiver
input resistance. When pin 1 is tied to VEE, the switching points are at +2.6V and -2~6V, thus
meeting RS-232-C requirements. When pin 1 is open·, the switching points are at +0.45V and -0.45V,
thus satisfying the requirements 10 MIL-STD-188C LOW level interface. Connecting the RIN pin to
the (-) input yields an input impedance in the range of 3kl1 to 7kl1 and satisfies RS-232-C
requirements; leaving R IN unconnected, the input resistance will be greater than 6kn to satisfy
MI L-STD-188C.
The output circuitry is TTL/DTL comDatible <'Inri will RllnI/\/ "rnllp,.'tn . . _rl ..... t:":i'"'~" ":':' 2~~~:-:~~ !~::;
wire-AND function. A TTL/DTL strobe is also provided for each receiver. The ErA failsafe mode of
operation is shown in the application section of this data sheet.
CONNECTION DIAGRAM
16-PIN
(TOP VIEW)
PACKAGE OUTLINES 68 98
PACKAGE CODES D P
HYSTERESIS
For the complementary function, see the 9616 triple E I A RS-232C/M I L-STD·188 line driver.
OUT A
OUT B
STROBE A
•
•
•
•
•
•
•
•
EIA RS-232-C INPUT STANDARDS
MIL-STD·188C INPUT STANDARDS
VARIABLE HYSTERESIS CONTROL
HIGH COMMON MODE REJECTION
RIN CONTROL (5kl1 DR 10kn)
WIRED-OR CAPABILITY
CHOICE OF INVERTING AND NON-INVERTING INPUTS
OUTPUTS AND STROBE TTL COMPATIBLE
-,IN A
+IN A
GND •
ABSOLUTE MAXIMUM RATINGS
VCC+ to Ground
V CC- to Ground
I nput Voltage Referred to Ground Pin
Strobe to Ground Voltage
Maximum Applied Output Voltage
Storage Temperature Range
Operating Temperature Range
Military (9627)
Commercial (9627C)
Internal Power Dissipation (Note 1)
Pin Temperature
Hermetic DIP, (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
OV to +15V
OVto -15V
±25V
·-0.5V to +5.5V
-0.5V to +15V
_65° C to +150° C
+IN B
.r-
_____
Vcc_
* I nternal Connection make no connection to this pin.
ORDER INFORMATION
_55°C to +125°C
O°C to +70°C
730mV\l
NOTE:
1.
-IN 8
For Hermetic DIP and Molded DIP rating applies to ambient temperatures up to 65°C, above
65°C derate linearly at 8.3 mW;oC.
6-80
TYPE
9627
9627C
9627C
PART NO.
9627DM
9627DC
9627PC
EQUIVALENT CIRCUIT
'~r------------~----~----~----~-------------4r---~----~------------------~----~----~--------~----------,
VCC+
c,
"11
"47
1.25kH
1.28kn
"49
6kn
8kn
lRl~3kn ~ ~:n
RIN A
0'8
"T1
l>
D30
1:0
0
'7'
031
°7
~
OUTS
3>
GNO
t~
to
en
~
N
~
vCC-
c,
~
II
C2
~
C3
~
C4
~
,., P F
Pin 4 and 13"" Internal Connection.
FAIRCHILD • 9627
9627 • 9627C
ELECTRICAL CHARACTERISTICS: VCC+ ~ 12 V
MIL-STD-188C
SYMBOL
CHARACTER ISTICS
VOL
Output LOW Voltage
VOH
Output HIGH Voltage
ISC
Output Shorted Current
± 10%, VCC-
~ -12 V
± 10% over Operating Temperature Range, unless otherwise specified
CONDITIONS
(Pins 6 and 11 Open. Inverting Inputs Open.
Pin 1 Open).
VCC+
~
+10.8 V, VCC-
Non-Inverting Input
~
~
~
TYP
-13.2 V
-0.6 V, IOL
~
6.4 mA
~
-0.5 mA
VCC+ ~ +10.8 V, VCC- ~ -13.2 V
Non-Inverting Input
MIN
+0.6 V ,IOH
MAX
0.4
UNITS
V
V
2.4
VCC+ ~ +13.2 V, VCC- ~ -10.8 V
Non-I nverting I nput
~
3.0
+0.6 V
mA
Outputs Grounded
IIH
(Strobe)
Input HIGH Current (Strobe)
RIN
I nput Resistance
VCC+ ~ +10.8 V, VCC- ~ -13.2 V
Non-Inverting Input
VCC+
~
~
+0.6 V
+13.2 V, VCC-
Non-Inverting Input
~
~
I Vs ~ 2.4 V
40
/lA
I Vs ~ 5.5 V
1.0
mA
-13.2 V
6.0
kl1
+3.0 V or -3.0 V
ITH+
Positive Threshold Current
VOUT ~ 2.4 V
ITH-
Negative Threshold Current
VOUT ~ 0.4 V
VIL
(Strobe)
Input LOW Voltage (Strobe)
VNon-lnverting Input ~ -0.6 V
VIH
(Strobe)
Input HIGH Voltage (Strobe)
1+
Positive Supply Current
VNon-lnverting Input ~ -0.6 V
ITA ~ +125"C (9627)
1-
Negative Supply Current
VNon-lnverting Input ~ +0.6 V
TA
100
-100
VCC+ ~ +13.2 V, VCC- ~ -10.8 V
r
/lA
0.8
VNon-lnverting Input ~ TO.6 V
V
V
2.0
18
12.4
-16
~ +125"C (9627)
/lA
mA
mA
-11.4
RS-232C
SYMBOL
CHARACTERISTICS
RIN
I nput Resistance
VIN
Input Voltage
VTH+
Positive Threshold Voltage
VTH-
Negative Threshold Voltage
CONDITIONS
(Non-Inverting Inputs Connected to Ground,
RIN Inputs Connected to Inverting Inputs)
MIN
TYP
MAX
UNITS
VIN
~
+3.0 V to +25 V
3.0
7.0
kl1
VIN
~
-3.0 V to -25 V
3.0
7.0
kl1
-2.0
2.0
V
0.6
V
Open Circuit
-0.6
V
AC CHARACTERISTICS: TA ~ +25°C, VCC+ ~ +12 V, VCC- ~ -12 V
MIL-STD-188C. RS-232-C
TYP
MAX
UNITS
tPLH
Propagation Delay Time
See AC Test Circuit
60
250
ns
tpHL
Propagation Delay Time
See AC Test Circuit
84
250
ns
SYMBOL
CHARACTERISTICS
CONDITIONS
6-82
MIN
FAIRCHILD • 9627
AC TEST CIRCUIT AND WAVEFORMS
392kll
~1%
+-J
16~VCC,~12V
VOUT _ _ _
8~GNO
9~VCC_"-12V
PIN 1 OPEN
THRESHOLD CURRENT MATCHING CIRCUIT
V,N
0-----I
470n
II
Vcc+~Vcc_
ADJUST POT TO ACH IEVE POSITIVE TH RESHOLD CU RRENT
AND NEGATIVE THRESHOLD CURRENT MATCHING
EIA RS-232-C INTERFACE WITH FAILSAFE RECEIVER
(PIN 1 OPEN)
'1396'6
~~
OATA 1
1/2 9627
EIA R S 2 3 2 . c - 1
INTERfACE
DATAL
>----------~)~>~4M~--_1
INHIBIT
10k
"
DATA OUT IS LOW
IF INPUT IS OPEN, OR
INPUT IS SHORTED TO AS, OR
DRIVER POWER IS OFF
DATA OUT IS HIGH IF
SPACE (LOGIC "0" OR "ON"
IS RECEIVED.
+5V
SIGNAL COMMON
RETURN
CIRCUIT
MIL-STD-1SSC INTERFACE
(PIN 1 OPEN)
1/6 9N04/7404
1~~1~ -ll:><>-.-'-'"
~MIL.STD
1
--l
188.C--1
INTERFACE
>
SIGNAL LEAD
)
DATA OUT
C·
r >>-__
T-=-.
);;.>---,
;CSI..:G;;:NA-;,L",C:;-;O",M",M..:;O-"N_ _ _
RETURN
..1
470"
-VCC~VCC_
.. Capacitor for Transmitter Waveshaping at Applicable Modulation Rate.
6-83
9637A
DUAL DIFFERENTIAL LINE RECEIVER
(EIA RS-422 AND RS-423 RECEIVER)
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The 9637A is a Schottky Dual Differential Line Receiver
which has been specifically designed to satisfy the requirements of EIA Standards RS422 and RS-423. In addition, the 9637A satisfies the requirements of MIL-STD 188-114
and is inter-operable with the International Standard CCITT recommendations. The
9637 A is suitable for use as a line receiver in digital data systems, using either singleended or differential, unipolar or polar transmission. It requires a single 5 V power
supply and has Schottky TTL compatible outputs. The 9637A has an operational input
common mode range ±7 V either differentially or to ground.
CONNECTION DIAGRAM
8-PIN DIP
(TOP VIEW)
PACKAGE OUTLINE 9T 6T
PACKAGE CODE
T R
Vcc+
OUT A
OUT B
•
•
•
•
•
•
•
•
DUAL CHANNELS
SINGLE 5 V SUPPLY
SATISFIES EIA STANDARDS RS-422 AND RS-423
BUILT IN ±35 mV HYSTERESIS
HIGH COMMON MODE RANGE
HIGH INPUT IMPEDANCE
TTL COMPATIBLE OUTPUT
SCHOTTKY TECHNOLOGY
GNO
ORDER INFORMATION
TYPE
PART NO.
9637A
9637A
9637A
9637ARM
9637ARC
9637ATC
EQUIVALENT CIRCUIT
+IN '(6)o--'--"""---H
Vo 2(3)
-IN '(5}o-4-"WI.--<>-t---+--~
4 (GND)
6-84
FAIRCHILD • 9637A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC Potential to Ground)
Input Potential to Ground Pin
Differential Input Voltage
Output Potential to Ground Pin
Output Sink Current
Internal Power Dissipation (Note 1) 9T
6T
Operating Temperature; 9637 ARM
9637ARC, 9637ATC
Storage Temperature
Pin Temperature
Molded DIP (Soldering, 10 s)
Hermetic DIP (Soldering, 30 s)
-0.5 V to 7.0 V
±15 V
±15 V
-0.5 V to 5.5 V
50 mA
1.3 W
1.15 W
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
NOTE:
1. For ambient temperatures above 25'C, derate at 7.7 mW/'C for 6T, and 11.1 mW/'C for 9T package.
RECOMMENDED OPERATING CONDITIONS
MIN
9637ARM
TYP
Supply Voltage (Vcc)
4.5
Operating Ambient Temperature (TA)
-55
CHARACTERISTICS
9637ARC, 9637ATC
TYP
MAX
UNITS
MAX
MIN
5.0
5.5
4.75
5.0
5.25
V
25
125
0
25
70
°C
ELECTRICAL CHARACTERISTICS: Over recommended temperature and supply voltage ranges, unless otherwise noted.
CONDITIONS (Note 1)
SYMBOL CHARACTERISTICS
MIN
LIMITS (Note 2)
TYP
MAX
UNITS
VTH
Differential Input
Threshold Voltage
-7.0 V,; VCM ,; 7.0 V (Note 3)
-0.2
0.2
V
VTH(R)
Differential Input
Threshold Voltage
-7.0 V'; VCM ,; 7.0 V (Note 4)
-0.4
0.4
V
liN
Input Current
Y,N
Y,N
1.1
-1.6
3.25
rnA
rnA
VOL
Output LOW Voltage
0.35
0.5
V
VOH
Output HIGH Voltage
Ise
Output Short
Circuit Current
lee
Supply Current
Vee = MAX, VIN(+) = 0.5 V,
V'N(-) = GND, (Both outputs low)
VHYST
Input Hysterisis
VeM
AC CHARACTERISTICS: Vcc
= 10 V, 0 ,; Vce ,; 5.5 V (Note 5)
= -10 V, 0'; Vee'; 5.5 V (Note 5)
10L = 20 rnA, Vec = MIN
IOH = -1.0 rnA, Vee = MIN
VOUT
= 5 V,
TA
= 0 V,
Vee
= MAX (Note 6)
-3.25
2.5
3.5
-40
-75
-100
rnA
35
50
rnA
= ±7 V (Figure 1)
V
70
mV
= 25'C
LIMITS
TYP
MAX
Figure 2
15
25
ns
Figure 2
13
25
ns
SYMBOL
CHARACTERISTICS
CONDITIONS
tpLH
Propagation Delay Ti me
LOW to HIGH
tPHL
Propagation Delay Ti me
HIGH to LOW
MIN
NOTES:
1. Use MINIMAX values specified in recommended operating conditions.
2. Typical limits are at Vce = 5.0 V and 25' C.
3. VOIFF !Differential Input Voltagel = [ (V'N+I - (VIN-I]
VCM (Common Mode Input Voltagel = [ (V'N+I - IVIN-I ]
4. 500 n ±1% in series with inputs.
5. The input not under test is tied to ground.
6. Only one output should be shorted at a time.
6-85
UNITS
•
FAIRCHILD. 9637A
TYPICAL INPUT/OUTPUT TRANSFER CHARACTERISTICS
v
C
::0
4.75 V
Vee = 5.25 V
I
I
I
I
I
I
I
I
~
w
~
o
I
I
I
>
~
...
0.
o
l~-=:-:
: VCM ~ ±7 V
1
~
0 V
I
I
I
:::l
I
I
i!::::l
-50
I
ii~
I~
~I
VCM ~O V I
I
I
o
1
I
I
I
·100
I
o
...>
-~I
I
o
"~
I
VCM
I
I
I
w
Ii
I
:::l
~
I
I
I
I
I
I
50
0
-100
100
INPUT VOLTAGE (mV)
-50
50
100
INPUT VOLTAGE (mV)
Fig. 1
SWITCHING TEST CIRCUIT AND AC WAVEFORMS
Vee
~5
V
Your
Vee
-6
.)_:p_:_~----~\.
+0.5 V - - - - - - , -_ _ _ _ _......,
~5V
VIN----J1-
."
'_PH_L_ _ __
v o u r - - - -......·
-
V'N
Amplitude: 1.0 V
Offset: 0.5 V
Pulse Width: 100 ns
PRR: 5 MHz
tr tt :s; 5 ns
*Includes Jig and Probe Capacitance.
All Diodes are F0700s or Equivalent.
tr, tf ~ 5 ns
Fig. 2
APPLICATIONS
RS-422 SYSTEM APPLICATION (FIPS 1020)
DIFFERENTIAL SIMPLEX BUS TRANSMISSION
TWISTED PAIR
OR
FLAT CABLE
+5 V
+5 V
t
....rL.
DUAL RS-422 LINE DRIVER
Rt ~ 50 fl for RS-422 operation
Rt combined with input impedance of receivers must be greater than 90
6-86
n
fLA8T26A • fLA8T28
QUAD 3-STATE BUS TRANSCEIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION -I'A8T26A and I'A8T28 are quad 3-state bus transceivers
featuring MPU or MOS compatibility. Both parts feature high-impedance PNP inputs
and high-speed operation made possible by the use of Schottky transistor technology.
. These devices are useful as bus extenders in systems employing the F6800, F3870 or
other comparable MPU families. Maximum input current of 200 I'A at the device input
pins assures proper operation despite limited drive capability of the MPU chip.
The I'A8T26A128 are identical to the NE8T26A/28 or the MC8T26A/28.
CONNECTION DIAGRAMS
16-PIN DIP ,TOP VIEW·
MA8T26A
PACKAGE OUTLINES
PACKAGE CODES
REL.~VER
ENABLE 1
INPUT
RECEIVER
OUTPUT 1
•
•
•
•
•
•
•
68 98
D P
Vee
DRIVER
ENABLE
INPUT
RECEIVER
OUTPUT 4
DRIVER
INPUT 1
RECEIVER
MABT26A -INVERTING BUS
MA8T28 - NON-INVERTING
MPU COMPATIBLE
HIGH-IMPEDANCE PNP INPUTS
HIGH-SPEED SCHOTTKY TECHNOLOGY
+5 V SINGLE SUPPLY OPERATION
3-STATE DRIVERS AND RECEIVERS
BUS 4
DRIVER
OUTPUT 2
INPUT 4
RECEIVER
OUTPUT 3
DRIVER
BUS 3
INPUT 2
DRIVER
INPUT 3
ORDER INFORMATION
TYPE
PART NO.
MA8T26A
MA8T26A
MA8T26A
MA8T26APC
MA8T26ADC
MA8T26ADM
BIDIRECTIONAL BUS APPLICATION
MA8T28
PACKAGE OUTLINES
PACKAGE CODES
68 98
D P
RECEIVER
ENABLE
INPUT
RECEIVER
RECEIVER
OUTPUTS
OUTPUTS
iJA8T26A
pA8T26A
OR
,.A8T28
.. AST28
1
RECEIVER
OUTPUT 1
DRIVER
RECEIVER
OUTPUT 2
DRIVER
DRIVER
INPUTS
INPUTS
ENABLE
INPUT
RECEIVER
OUTPUT 4
INPUT 1
OR
Vee
DRIVER
BUS 2 6
DRIVER
INPUT 2
BUS 4
DRIVER
INPUT 4
RECEIVER
OUTPUT 3
BUS 3
DRIVER
INPUT 3
TO OTHER
ORDER INFORMATION
DRIVERS/RECEIVERS
DRIVER
ENABLE
6-87
TYPE
PART NO.
MA8T28
MA8T28
MA8T28
MA8T28PC
I'A8T28DC
I'A8T28DM
II
FAIRCHILD • JlA8T26A • JlA8T28
ABSOLUTE MAXIMUM RATINGS: TA = 25°C unless otherwise noted
8.0 V
5.5 V
Power Supply Voltage (Vee)
Input Voltage (VI)
Junction Temperature (TJ)
Ceramic Package
Plastic Package
Operating Ambient Temperature Range (TA)
Storage Temperature Range (Tstg)
175°C
150°C
-55°C to +125°C
-65° C to +150° C
ELECTRICAL CHARACTERISTICS: 4.75 V:5 Vcc:5 5.25 V lor O°C:5 TA:5 70°C, and 4.5 V:5 Vcc:5 5.5 V,lor -55°C:5 TA:5 +125°C,
unless otherwise noted
SYMBOL
CHARACTERISTICS
MAX
UNITS
-200
-200
-200
-200
MA
-
-
-
-25
MA
-
MA
MIN
Ill(RE)
hl(DE)
Ill(D)
Ill(s)
Input Current - LOW Logic State
Receiver Enable Input, Vll(RE) = 0.4 V
Driver Enable Input, Vll(DE) = 0.4 V
Driver Input, VIL(D) = 0.4 V
Bus Receiver Input, ViliS) = 0.4 V
-
hl(D) DIS
Input Disabled Current - LOW Logic State
Driver Input, Vll(D) = 0.4 V
hHlRE)
IIH(DE)
hH(D)
hH(S)
Input Current - HIGH Logic State
Receiver Enable Input, VIHIRE) = 5.25 V
Driver Enable Input, VIH(DE) = 5.25 V
Driver Input, VIH(D) = 5.25 V
Receiver Input, VIH(B) = 5.25 V (MA8T26 only)
-
TYP
-
-
-
-
-
25
25
25
100
Vll(RE)
Vll(DE)
Vll(D)
VILIS)
Input Voltage - LOW Logic State
Receiver Enable Input
Driver Enable Input
Driver Input
Receiver Input
-
-
0.85
0.85
0.85
0.85
V
VIH(RE)
VIHIDE)
VIH(D)
VIHIS)
Input Voltage - HIGH Logic State
Receiver Enable Input
Driver Enable Input
Driver Input
Receiver Input
2.0
2.0
2.0
2.0
-
-
V
VOl(B)
VOl(R)
Output Voltage - LOW Logic State
Bus Driver Output, 10l(B) = 48 mA
Receiver Output, 10l(R) = 20 mA
-
-
Output Voltage - HIGH Logic State
Bus Driver Output, 10H(B) = -10 mA
Receiver Output, 10H(R) = -2.0 mA
Receiver Output, 10HIR) = -100 MA, Vcc
2.4
2.4
3.5
3.1
3.1
-
-
10Hl(S)
10Hl(R)
Output Disabled Leakage Current - HIGH Logic State
Bus Driver Output, VOH(B) = 2.4 V
Receiver Output, VOIj(R) = 2.4 V
-
-
100
100
MA
10ll(S)
10ll(R)
Output Disabled Leakage Current - LOW Logic State
Bus Output, VOl(S) = 0.5 V
Receiver Output, VOl(R) = 0.5 V
-
-
-100
-100
MA
-
VIC(DE)
VIC(RE)
VIC(D)
Input Clamp Voltage
Driver Enable Input IID(DE) = -12 mA
Receiver Enable Input hC(RE) = -12 mA
Driver Input hC(D) = -12 mA
-
-
-1.0
-1.0
-1.0
V
10S(B)
10S(R)
Output Short-Circuit Current, Vcc
Bus Driver Output
Receiver Output
-50
-30
80
50
-150
-75
mA
-
50
87
mA
VOH(S)
VOH(R)
= 5.0 V
-
-
-
0.5
0.5
V
-
V
= 5.25 V(n
Power Supply Current
Vcc = 5.25 V
Icc
111 Only one output may be short-circUited at a time
6-88
FAIRCHILD • J.tA8T26A • J.tA8T28
I'A8T26A SWITCHING CHARACTERISTlCS:Unless otherwise noted, specifications apply at TA
CHARACTERISTICS
= 25°C
= 5.0
and Vee
V
MAX
UNITS
tPLH(R)
Propagation Delay Time from Receiver (Bus) Input to
HIGH Logic State Receiver Output
1
9
14
ns
tPHL(R)
Propagation Delay Time from Receiver (Bus) Input to
LOW Logic State Receiver Output
1
6
14
ns
tPLH(D)
Propagation Delay Time from Driver Input to
HIGH Logic State Driver (Bus) Output
2
10
14
ns
tPHL(D)
Propagation Delay Time from Driver Input to
LOW Logic State Driver (Bus) Output
2
10
14
ns
tPLZ(RE)
Propagation Delay Time from Receiver Enable Input to
HIGH Impedance (Open) Logic State Receiver Output
3
10
15
ns
tpZL(RE)
Propagation Delay Time from Receiver Enable Input to
LOW Logic Level Receiver Output
3
15
20
ns
tPLZ(DE)
Propagation Delay Time from Driver Enable Input to
HIGH Impedance Logic State Driver (Bus) Output
4
15
20
ns
tpZL(DE)
Propagation Delay Time from Driver Enable Input to
LOW Logic State Driver (Bus) Output
4
19
25
ns
SYMBOL
FIGURE
TYP
II
tTLH S 5.0 ns
INPUT
oV _ _;';';;'''I
VOH ----..;.-""\.
OUTPUT
VOl-------~----------I
INPUT PULSE FREQUENCY = 5.0 MHz
DUTY CYCLE = 50%
2.6 V
TO SCOPE
(OUTPUT)
TO SCOPE
(INPUT)
RECEIVER ENABLE
INPUT
92
RECEIVER
(BUS)
1N916
OR EOUIV.
INPUT
PULSE
GENERATOR
51
fl
1.3 k
30 pF
DRIVER
ENABLE
INPUT
Fig. 1
I'A8T26A Test Circuit and Waveforms or Propagation Delay Time
from Bus (Receiver) Input to Receiver Output, tPLH(R) and tpHL(R)
6-89
fl
FAIRCHILD. J.tA8T26A • J.tA8T28
tTLH :S 5.0 ns
trHL
:s 5.0 ns
INPUT
OV _ _=~
VOH------------,
OUTPUT
VOL----------------~---------------------J
2.6 V
TO SCOPE
(INPUT)
INPUT PULSE FREQUENCY = 5.0 MHz
DUTY CYCLE = 50%
2.6 V
TO SCOPE
(OUTPUT)
DRIVER
ENABLE
INPUT
DRIVER
30
Jl
1N916
OR eOUtv.
(BUS)
OUTPUT
DRIVER
INPUT
PULSE
51
GENERATOR
260
fl
n
300 pF
RECEIVER
OUTPUT
RECEIVER
ENABlE:
INPUT
Fig. 2
I'A8T26A Test Circuit and Waveforms for Propagation Delay Time
from Driver Input to Bus (Driver) Output, tpLH(D) and tPHL(D)
tTLH -:: 5.0 ns
2.6 V
.....-- tTHl
~
5.0 ns
----t---Jc-::::::---------;=-:i..
INPUT
OV--=.;;Jj
<
3.5 V
------+---::;;..-________'""
INPUT PULSE FREQUENCY = 5 MHz
DUTY CYCLE"" 50%
OUTPUT
VOL _ _ _ _ _ _- ' 10%
TO SCOPE
(INPUT)
2.6 V
TO SCOPE
(OUTPUT)
RECEIVER
ENABLE
INPUT
5.0 V
240
2.4 k
fl
PULSE
GENERATOR
11.
51
fl
lN916
5.0 k
Fig. 3
30pF
I'A8T26A Test Circuit and Waveforms for Propagation Delay Time
from Receiver Enable Input to Receiver Output, tPLZ(RE) and tpZL(RE)
6-90
OR EQUIV.
FAIRCHILD • IlA8T26A • IlA8T28
tTLH :::; 5.0 ns
INPUT
ov----'I
03.5V----...;........
O'JTPUT
10%
VOL - - - - - - - ' - - - - - - - - - - - - '
TO SCOPE
(INPUT)
TO SCOPE
5.0 V
(OUTPUT)
+2.6 V
DRIVER
ENABLE
n
DRIVER
DRIVER
PULSE
GENERATOR
51
II
70
2.4 k
INPUT
INPUT
(BUS)
OUTPUT
n
RECEIVER
OUTPUT
5.0 k
300 pF
1N916
OR EQUIV.
RECEIVER
ENABLE
INPUT
Fig.4
j.lA8T26A Test Circuit and Waveforms for Propagation Delay Time
from Driver Enable Input to Driver (Bus) Output, tPLZ(DE) and tpZL(DE)
j.lA8T28 SWTICHING CHARACTERISTICS: Unless otherwise noted, Vee = 5.0 V and TAoC
SYMBOL
CHARACTERISTIC
FIGURE
tPLH(R)
tPHL(R)
Propagation Delay Time
tPLH(D)
tPHL(D)
Propagation Delay Time -
tpZL(RE)
tPLzIRE)
Propagation Delay Time -
tpzLIDE)
tPLzIDE)
Propagation Delay Time -
-
MAX
UNITS
-9
17
17
ns
TYP
-12
Receiver (CL = 30 pF)
5
Driver (CL = 300 pF)
6
-13
-13
17
17
ns
Receiver Enable (CL = 30 pF)
7
-18
-13
23
18
ns
Driver Enable (CL = 300 pF)
8
-21
-18
28
23
ns
6-91
FAIRCHILD. ,uA8T26A • ,uA8T28
ITHI. <
5.0 ns
2.6V _ _
~~
INPUT
OV----VOH-----"
OUTPUT
VOL--------'-----------------'
TO SCOPE
(INPUT)
INPUT PULSE FREQUENCY ::= 10 MHz
DUTY CYCLE = 50%
2.6 V
TO SCOPE
(INPUT)
RECEIVER
ENABLE
INPUT
92
1N916
OR eQulv.
RECEIVER
OUTPUT
DRIVER
INPUT
PULSE
GENERATOR
51
1.3 k
DRIVER
ENABLE
INPUT
Fig.5
J.lA8T28 Test Circuit and Waveforms for Propagation Delay Time
from Bus (Receiver) Input to Receiver Output, tPLH(R) and tPHL(R)
hHL < 5.0 ns
2.6V ___
~~
INPUT
OV----
VOH -------'"'\
OUTPUT
VOL-------·'---------------------'
2.6 V
TO SCOPE
(INPUT)
2.6 V
TO SCOPE
(OUTPUT)
DRIVER
ENABLE
INPUT
30
DRIVER
DRIVER
(BUS)
INPUT
OUTPUT
1N916
OR eQUlv.
PULSE
GENERATOR
Fig. 6
51
J.lA8T28 Test Circuit and Waveforms for Propagation Delay Time
from Driver Input to Bus (Driver) Output, tPLH(D) and tPHL(D)
6-92
FAIRCHILD • ILA8T26A • ILA8T28
trLH ::.:: 5.0 ns
~ tTHL
S 5.0 ns
...
2.6V ------t--::r.=-------~~
INP,UT
OV--=Ji
• 3.5 V
------+--:.....________-,.
INPUT PULSE FREQUENCY = 5.0 MHz
DUTY CYCLE = 50%
OUTPUT
VOL----------__--'
10%
TO SCOPE
(INPUT)
TO SCOPE
(OUTPUT)
5.0 V
2.6 V
2.4 k
RECEIVER
OUTPUT
PULSE
GENERATOR
240
51
5.0 k
Fig. 7
30 pF
1N916
OR eQUlv.
I"ABT2B Test Circuit and Waveforms for Propagation Delay Time
from Receiver Enable Input to Receiver Output, tpLZ(RE) and tpZL(RE)
tTLH ::.:: 5.0 ns
INPUT
ov---Ji
.3.5V----...;........
INPUT PULSE FREQUENCY = 5.0 MHz
DUTY CYCLE = 50%
OUTPUT
VOL ________ \ _____________..110%
TO SCOPE
(INPUT)
TO SCOPE
(OUTPUT)
DRIVER
+2.6
v
ENABLE
INPUT
5.0 V
2.4 k
DRIVER
INPUT
PULSE
GENERATOR
n
DRIVER
51
(BUS)
OUTPUT
RECEIVER
OUTPUT
RECEIVER
ENABLE
INPUT
5.0 k
1N916
OR eQUlv.
Fig. B I"ABT28 Test Circuit and Waveforms for Propagation Delay Time
from Driver Enable Input to Driver (Bus) Output, tPLZ(DE) and tpZL(DE)
6-93
•
9640/26510 • 9641/26511 • 9642
QUAD GENERAL PURPOSE BUS TRANSCEIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The 9640, 9641 and 9642 are High-Speed Quad Bus
Transceivers. Each driver output, which IS capable of sinking 100 mA at 0.8 V, is connected Internally to the high-speed bus receiver in addition to being connected to the
package pin. The receiver has a Schottky TTL output capable of driving ten Schottky TIL
unit loads. The bus output is capable of driving lines having 1000 impedance.
The line can be terminated at both ends and stl,ll give considerable noise margin at the
receiver. The receiver typical switching point IS 2.0 V.
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 68 98
PACKAGE CODES
D
P
Vce
GND 1
BUS 0
RECEIVER
CUTD
The 9640, 9641, and 9642 feature advanced Schottky processing to minimize propagation delay. The device package also has two ground pins to improve ground current
handling and allow close decoupling between Vee and ground at the package. Both
GND1 and GND2 should be tied to the ground bus external to the device package.
The 9640 and 9641 are pin for pin replacements of the AM26S 10 and AM26S 11 respectively.
The 9642 is the same device as the 9640 With hysteresis. The hysteresis characteristic
of the 9642 receiver is chosen so that the receiver switches to a HIGH logic level when
the receiver input is at a HIGH logic level and moves to 1.4 V typically, and switches to
a LOW logic level when the receiver Input IS at a LOW logic level and moves to 2.0 V
typically. This hysteresis characteristic allows for increased noise immunity in low speed
appl ications.
•
•
•
•
•
•
•
BUSD
14
RECEIVER
aUTO
12
DRIVER
IND
STROBE
RECEIVER
OUTB
BUSB
GND 2
11 DRIVER
INC
RECEIVER
OUTC
BUS C
IN D
STROBE
11 DRIVER
INC
RECEIVER
OUTC
BUSS
GND 2
BUS C
9640
ORDER INFORMATION
TYPE
9640
9640
9640
PART NO,
9640DM/26510
9640DC126510
9640PC/26510
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 68 98
PACKAGE CODES
D
P
INPUT TO BUS IS INVERTING ON 9640 AND 9642
INPUT TO BUS IS NON-INVERTING ON 9641
QUAD HIGH-SPEED OPEN COLLECTOR BUS TRANSCEIVERS
DRIVER OUTPUTS CAN SINK 100 mA AT 0.8 V MAXIMUM
ADVANCED SCHOTTKY PROCESSING
PNP INPUTS TO REDUCE INPUT LOADING
600 mVRECEIVER HYSTERESIS (9642 ONLY)
GND 1
DRIVER
GND 1
BUS 0
BUS A
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 68 98
PACKAGE CODES
D
P
RECEIVER
OUTA
DRIVER
INA
DRIVER
INB
RECEIVER
OUTS
3
6-94
DRIVER
12
5
11 DRIVER
10
BUSB
GND 2
INO
STROBE
6
7
____
~=.J,
INC
RECEIVER
OUTe
BUS C
9641
9642
ORDER INFORMATION
TYPE
PART NO.
9642
9642DM
9642
9642DC
9642PC
9642
RECEIVER
CUTO
4
ORDER INFORMATION
TYPE
9641
9641
9641
PART NO,
9641DM/26511
9641DC/26511
9641PC/26511
FAIRCHILD • 9640/26510 .9641/26511 • 9642
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Supply Voltage to Ground Potential
DC Voltage Applied to Outputs for High Output State
DC Input Voltage
Output Current, into Bus
Output Current, into Outputs (Except Bus)
DC Input Current
-65°C to +150°C
-0.5 V to +7 V
-0.5 V to +VCC Max
-0.5 V to +5.5 V
200 mA
30 mA
-30 mA to +5.0 mA
TRUTH TABLES
9640/42
INPUTS
E
9641
OUTPUTS
INPUTS
z
L
L
H
H
H
L
Y
Y
E
H
L
L
L
H
L
Y
Y
H
X
B
L
L
L
H
H
X
OUTPUTS
B
Z
I
I
H = HIGH Voltage Level
L = LOW Voltage Level
x=
Don't Care
Y = Voltage Level of Bus (Assumes Control
by another Bus Transceiver)
RECOMMENDED OPERATING CONDITIONS
DM
CHARACTERISTICS
DC, PC
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
Positive Supply Voltage
4.50
5.0
5.5
4.75
5.0
5.25
V
Operating Ambient Temperature - TA
-55
+25
+125
0
+25
+70
°c
ELECTRICAL CHARACTERISTICS: Over Operating Range, unless otherwise specified
SYMBOL
VOH
VOL
VIH
VIL
CHARACTERISTICS
Output HIGH Voltage
(Receiver Outputs)
VCC = MIN, IOH = -1.0 mA
VIN = VIL or VIH
Output LOW Voltage
VCC = MIN, IOL = 20 mA
(Receiver Outputs)
VIN = VIL or VIH
Input HIGH Level
Guaranteed Input Logical HIGH
(Except Bus)
for all Inputs
Input LOW Level
Guaranteed Input Logical LOW
(Except Bus)
for all Inputs
Input Clamp Voltage
VI
IlL
IIH
IIH
ISC
ICCL
(Except Bus)
Input LOW Current
Input HIGH Current
Input HIGH Current
Output Short Circuit
TYP
(Note 2)
DM
2.5
3.4
DC, PC
2.7
3.4
MAX
2.0
0.8
V
-1.2
V
ENABLE
-0.36
DATA
-0.54
mA
ENABLE
20
DATA
30
VCC = MAX, VIN = 2.7 V
VA
100
VCC = MAX, VIN = 5.5 V
DM
-20
-55
DC, PC
-18
-60
9640
VCC= MAX
Enable = GND
9641/42
6-95
V
V
VCC = MAX, VIN = 0.4 V
VCCr MAX, (Note 3)
UNITS
V
0.5
VCC = MIN, liN = -18 mA
Current (Except Bus)
Power Supply Current
(All Bus Outputs LOW)
MIN
CONDITIONS (Note 1)
45
VA
mA
70
80
'mA
I
- --
--
~
-
FAIRCHILD. 9640/26510 • 9641/26511 .9642
AC CHARACTERISTICS: TA
SYMBOL
= +25°C,
tPLH
tpHL
VCC
= 5.0 V
TYP
MAX
9640
10
15
Data Input to Bus
9642
10
15
tpLH
12
19
12
19
MIN
CONDITIONS
CHARACTERISTICS
9641
tpHL
RB
= 50 n,
CB
= 50 pF (Note
9640
14
18
tpLH
9642
13
18
15
20
Enable Input to Bus
9641
14
20
tpLH
9640/41
10
15
tpHL
9642
RB
10
9640/41
CL
tpHL
Bus to Receiver Out
tpLH
= 50 n, RL = 280 n,
= 15 pF (Note 1)
CB
= 50
pF,
10
Bus
If
Bus
RB
ns
15
= 50 n,
CB
= 50
pF (Note 1)
4.0
10
ns
2.0
4.0
ns
Note 1 Includes probe and jig capacitance.
AC TEST CIRCUIT
TEST
POINT
VCC
I
I
PULSE
9641
ONLY
RECEIVER
OUT
VIC
R8
50 n
GENERATOR~h:
•.n---i~--)o~~-.~-t>~-4rJ~__~lkIAt-__~
NO.1
II>
-V
I~t-~~
I~
INPUT
PULSE
GENERATOR
NO.2
STROBE
INPUT
Ca
50 pF
(Note 11
I
--
1
-=
RL
2aO n
~ '-
CL
'5 pF
(Note 1)
'"
'T
~~~~~°o"RES
..; ' - EQUIVALENT
'T
'"
--
-=
BUS
TEST I POINT
Note (1) CB and CL includes Probe and Jig Capacitance.
Fig, 1
WAVEFORMS
11~=~~
--Ji-------\----------------F---:::
__
-:::~
INPUT
ns
10
9642
tpHL
tr
ns
1)
tpLH
tpLH
UNITS
{I
I
/
t_~===~;:
\'._V___
71~' ~
P6~~!_tPLH_~ V~,~ ( ~ J7~ ~
r- j\
r- -,
f=_tPHL_:::
tPHl4-
\l
RECEIVEROUT _ _
-,
TEST POINT
v" \_/__
•
,-
"
VOL
VOH
1.5V
' - - - - - - ' - - - - - - - - VOL
Fig, 2
6-96
FAIRCHILD. 9640/26510 .9641/26511 .9642
BUS INPUT/OUTPUT CHARACTERISTICS
SYMBOL
CONDITIONS (Note 1)
CHARACTERISTICS
Output LOW Voltage
VCC
10FF
Bus Leakage Current
VCC
= 40
rnA
0.33
0.5
= 70
rnA
0.42
0.7
10L
= 100
0.51
0.8
10L - 40 rnA
0.33
0.5
10L
= 70
0.42
0.7
10L
= 100
Vo
= 0.8
V
-50
OM
Vo
= 4.5
V
200
DC,PC
Vo
= 4.5
V
100
= Min
Bus Leakage Current (Power Off)
Vo
= Max
= 4.5
rnA
rnA
0.51
rnA
Bus Enable
VCC = Max
Receiver Input HIGH Threshold
= 2.4 V
2.0
2.4
2.0
2.25
1.8
2.0
2.2
1.6
2.0
1.75
2.0
1.2
1.4
OM
DC, PC
9640/9641
VTL
Bus Enable
VCC = Min
Receiver Input LOW Threshold
= 2.4 V
OM
9640/9641
DC,PC
9642
(9642)
4.0,..--..,----,--,--..,----,----,
3.6
3.2
~
2.8 f---+--+--t--+--+--i
w
~ 2.4
!:;
2.0
~
1.6
~
o
f--+--+--I--+--+---I
f---+--+--t--+--t--i
f---+--+--t--+--+--i
1.2 f---+--+--t--+--t--i
o
>
f----+--+--+----j--l-----i
f----+--+---I--+--+----j
0.8
f----+--+--I--+----f---I
0.4 f--+--+--t--+--+---J
°1~.2~-J1.~4::~1~.5;:~1~.8::~2.~0::~2f.2~~2.4
INPUT VOLTAGE - V
Fig, 3
6-97
J.lA
J.lA
V
1.6
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical limits are at Vee"" 5.0 V, 25°C ambient and maximum loading.
3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
RECEIVER INPUT
HYSTERESIS CHARACTERISTIC
V
V
9640/9641
9642
UNITS
0.8
100
V
9640/9641
VTH
MAX
IOL
DC,PC
10
TYP
(Note 2)
10L
OM
VOL
MIN
•
PERIPHERAL AND DISPLAY DRIVERS
Peripheral Drivers
55/75450A
Dual Positive AND Peripheral Driver ..................................... 7-3
55/754508
Dual High-Speed Positive AND Peripheral Driver ....................... 7-17
55/75451A
Dual Positive AND Peripheral Driver ..................................... 7-3
55/754518
Dual High-Speed Positive AND Peripheral Driver ....................... 7-17
55/75452A
Dual Positive NAND Peripheral Driver ................................... 7-3
55/754528
Dual High-Speed Positive NAND Peripheral Driver ..................... 7-17
55/75453A
Dual OR Positive Peripheral Driver ...................................... 7-3
55/754538
Dual High-Speed OR Positive Peripheral Driver ........................ 7-17
55/75454A
Dual Positive NOR Peripheral Driver ..................................... 7-3
55/754548
Dual HighLSpeed Positive NOR Peripheral Driver ....................... 7-17
55/75460
Dual High-Voltage Positive AND Peripheral Driver ...................... 7-31
55/75461
Dual High-Voltage Positive AND Peripheral Driver ...................... 7-31
55/75462
Dual High-Voltage Positive NAND Peripheral Driver .................... 7-31
55/75463
Dual High-Voltage Positive OR Peripheral Driver ....................... 7-31
55/75464
Dual High-Voltage Positive NOR Peripheral Driver ...... ; ............... 7-31
55/75471
Dual High-Voltage Positive AND Peripheral Driver ...................... 7-42
55/75472
Dual High-Voltage Positive NAND Peripheral Driver •................... 7-42
55/75473
Dual High-Voltage Positive OR Peripheral Driver ....................... 7-42
55/75474
Dual High-Voltage Positive NOR Peripheral Driver ...................... 7-42
9665 (ULN2001) Seven High-Voltage, High-Current Darlington Drivers ................... 7-49
9666 (ULN2002) Seven High-Voltage, High-Current Darlington Drivers ................... 7-49
9667 (ULN2003) Seven High-Voltage, High-Current Darlington Drivers ................... 7-49
9668 (ULN2004) Seven High-Voltage, High-Current Darlington Drivers ................... 7-49
Display Drivers
55/75491
55/75491 A
55/75492
55/75492A
Quad MOS-to-LED Segment Drivers .................................. ,
Quad MOS-to-LED Segment Drivers .................................. ,
HEX MOS-to-LED Digit Drivers ....................................... ,
HEX MOS-to-LED Digit Drivers ........................................
7-54
7-54
7-54
7-54
55/75450A • 55/75451 A • 55/75452A
55/75453A • 55/75454A
DUAL PERI PHERAL DRIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The 55175450A, 55175451A, 55175452A, 55/75453A and 55/75454A are Dual High Speed General Purpose Interface
Drivers that convert TTL and DTL logic levels to high current drive capability. The 55450A and 75450A feature two TTL NAND gates and two
uncommitted transistors. The 55/75451A, 55/75452A, 55/75453A and 55175454A feature two standard series 74 TTL gates in AND, NAND, OR and
NOR configurations respectively, driving the base of two high voltage, high current, uncommitted collector output transistors.
The 55175450A series offers flexibility in designing high speed logic buffers, power drivers, lamp drivers, line drivers, MOS drivers, clock drivers and
memory drivers.
•
•
•
•
•
NO LATCH-UP AT 20 V
HIGH OUTPUT CURRENT CAPABILITY
TTL OR DTL INPUT COMPATIBILITY
INPUT CLAMP DIODES
+5 V SUPPLY VOLTAGE
I
TEST TABLE 1 - Operating Temperature Range and Supply Voltage Range
55450A Series
Temperature, T A
Supply Voltage, VCC
75450A Series
-55°C to +125°C
O°C to 70°C
+4.5 V to +5.5 V
+4.75 V to +5.25 V
ABSOLUTE MAXIMUM RATINGS
55450A
Supply Voltage, V CC (See Note 11
Input Voltage (See Note 11
Interemitter Voltage(See Note 21
V CC to Substrate Voltage (See Note 61
Collector to Substrate Voltage (See Note 61
Collector to Base Voltage
Collector to Emitter Voltage (See Note 31
Emitter to Base Voltage
Output Voltage (See Notes 1 and 41
Continuous Collector Current (See Note 51
Continuous Output Current (See Note 5)
Continuous Total Power Dissipation (See Note 7)
Operating Ambient Temperature Range
Storage Temperature Range
Pin Temperature
Molded DIP (Soldering, 10 sl
Hermetic DIP (Soldering, 60 sl
75450A
7V
5.5V
5.5V
35 V
35 V
35 V
30 V
5V
7V
5.5 V
5.5 V
35 V
35 V
35 V
30V
5V
300mA
300mA
800mW
_·55' C to +125° C
_65°C to +150°C
300°C
55451A
55452A
55453A
55454A
75451A
75452A
75453A
75454A
7V
5.5 V
5.5 V
7V
5.5 V
5.5V
30V
30V
800mW
O°C to 70°C
_65° C to +150° C
300mA
800mW
_55° C to +125° C
_65° C to +150° C
300mA
800mW
O°C to 70°C
_65° C to +150° C
260°C
300°C
260°C
300°C
260°C
300°C
NOTES:
1. Voltage values are with respect to network ground terminal unless otherwise specified.
2. This is the voltage between two emitters of a multiple-emitter input transistor.
3. This value applies when the base-emitter resistance (RS E) is equal to or less than 500 n.
4. This is the maximum voltage which should be applied to any output when it is in the off state.
5. Soth halves of these dual circuits may conduct rated current simultaneously.
6. For the 55450A and 75450A only, the substrate (Pin 8), must always be at the most negative device voltage for proper operation.
7. Above 60°C ambient temperature, derate linearly at 8.3 mW;oC for Hermetic DIP and Molded DIP. For the Molded Mini DIP and Ceramic Mini
DIP, derate at 6.7 mwtC above 30°C.
7-3
FAIRCHILD • 55450A/75450A SERIES
55450A175450A
DUAL POSITIVE AND PERIPHERAL DRIVER
EQUIVALENT f:LBCI::IlT
r------,----~-~-----o
CONNECTION DIAGRAM
14-PIN
(TOP VIEW)
PACKAGE OUTLINE 6A 9A
P
PACKAGE CODE D
vcc
GATE
1E
IN B
INA
OUT A
IN A
IB
1C
2B
1C
2C
1E
2E
SUB
GND
SUB
LOGIC FUNCTION
2C
IN B
Positive Logic: Z = XV (gate only)
Z = X Y (gate and transistor)
o--+-+---;
2E
ORDER INFORMATION
PART NO_
TYPE
55450A
55450ADM
75450A
75450ADC
75450A
75450APC
L--+-+-----~~--~--~----------_oGND
All resistor values in ohms.
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated
TTL Gates
SYMBOL
TEST
CHARACTERISTICS
VIH
Input HIGH Voltage
1
V IL
Input LOW Voltage
2
VCD
Input Clamp Diode Voltage
3
VOH
Output HIGH Voltage
2
VOL
Output lOW Voltage
1
Input Current at Maximum
II
-
Input Voltage
IIH
Input HIGH Current
III
Input lOW Current
Input A
Input G
Input A
Input G
Input A
Input G
lOS
Short Circuit Output Current (Note 9)
ICCH
Supply Current. Output HIGH
ICCl
Supply Current. Output lOW
= MIN, II = -12 mA
VCC = MIN, Vll =0.8 V
10H = -400J.lA
VCC = MIN, VIH = 2 V I
10L = 16 mA
1
=MAX, VI = 5.5 V
4
VCC
=MAX, VI = 2.4 V
3
VCC
= MAX, VI =0.4 V
VCC
=MAX
=MAX, VI =0 V
=MAX, VI = 5 V
VCC
VCC
NOTES:
=
MAX
=
8. All typical values at VCC 5 V, TA 25°C.
9. Not more than one output should be shorted at a time.
7-4
2.4
UNIT
V
VCC
VCC
6
TYP
(Note 8)
2
4
5
MIN
CONDITIONS
FIGURE
0.8
V
-1.5
V
3.3
V
55450A
0.22
0.5
75450A
0.22
0.4
1
2
40
80
-1.6
-3.2
-18
-55
2
4
6
11
V
mA
J.lA
mA
mA
mA
FAIRCHILD • 55450A/75450A SERIES
55450A/75450A
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use
Test Table 1, pg. 1, unless otherwise indicated
Output Transistors
SYMBOL
CHARACTER ISTICS
CONDITIONS
MIN
TYP
(Note 10)
MAX
UNIT S
V(BR)CBO
Collector to Base Breakdown Voltage
IC - 100llA, IE - 0
35
V
V(BR)CER
Collector to Emitter Breakdown Voltage
IC = 100 I'A, RBE = 50011
30
V
V(BR)EBO
Emitter to Base Breakdown Voltage
IE = 1OOllA, IC = 0
5
V
VCE - 3 V, IC = 100 mA, TA = 25°C
hFE
Static Forward Current Transfer Ratio
(Note 11)
VBE(sat)
VCE(sat)
Base to Emitter Voltage (Note 11)
Collector to Emitter Saturation Voltage
(Note 11)
25
VCE = 3 V, IC = 300 mA. TA = 25°C
30
VCE - 3 V,
IC = 100 mA
55450A
75450A
10
20
VCE - 3 V,
IC = 300 mA
55450A
75450A
25
15
IB = 10 mA.
55450A
0.B5
1.2
V
IC=100mA
75450A
0.B5
1.0
V
IB = 30 mA.
55450A
1.05
1.4
V
IC = 300 mA
75450A
1.05
1.2
V
IB 10mA,
IC = 100 mA
55450A
0.25
0.5
V
75450A
0.25
0.4
V
IB = 30 mA.
55450A
0.5
0.8
V
IC = 300 mA
75450A
0.5
0.7
V
I
NOTES:
to. All typical values are at Vee = 5 V. TA = 25°e.
11. These parameters must be measured using the pulse techniques. tw
= 300
,us, duty cycle ~ 2%.
AC CHARACTERISTICS: VCC = 5 V, TA = 25°C.
TIL Gates
CHARACTER ISTICS
SYMBOL
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
TEST
FIGURE
12
CONDITIONS
MIN
CL = 15 pF, RL = 400 11
TYP
MAX
UNITS
12
ns
8
ns
Output Transistors
SYMBOL
CHARACTERISTICS
td
Delay Time
tr
Rise Time
ts
Storage Time
tf
Fall Time
TEST
CONDITIONS
FIGURE
(Note 12)
13
MIN
TYP
MAX
UNITS
IC = 200 mA. VBE(off) = -1 V
10
ns
IB(1) = 20 mAo IB(2) = -40 mA
14
ns
CL = 15 pF. RL = 5011
10
ns
11
ns
Gates and Transistors Combined
SYMBOL
CHARACTERISTICS
tpLH
Propagation Delay Time. Output LOW to HIGH
tpHL
Propagation Delay Time. Output HIGH to LOW
tTLH
Transition Time. Output LOW to HIGH
tTHL
Transition Time. Output HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
TEST
CONDITIONS
FIGURE
14
MAX
UNITS
22
65
ns
22
50
ns
RL = 5011
10
20
ns
14
20
NOTE 12. Voltage and current values shown are nominal; exact values vary slightly with transistor parameters.
7-5
TYP
IC = 200 mAo CL = 15 pF.
Vs = 20 V. IC '" 300 mA
RBE = 500 11
15
MIN
Vs -6.5
ns
mV
FAIRCHILD • 55450A/75450A SERIES
55451A/75451A
DUAL POSITIVE AND PERIPHERAL DRIVER
CONNECTION DIAGRAM
8-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 9T ST
R
PACKAGE CODES T
EQUIVALENT CIRCUIT (Each Driver)
vee
4k
130
1.6 k
-------i:::
7.
INPUTS
OUTPUT
INA1~r----,
r-.,.
""cWl)
{ 1
~
2
2~
::is:
3
OUTA[:r?-4
500
1k
r
1~8
jvcc
::2:
~
GNOt
~""
6
:]IN81
5
jOUTB
GNO
-:Component values shown are nominal. All resistor values in ohms.
TRUTH TABLE
ORDER INFORMATION
PART NO_
TYPE
55451ARM
55451A
75451ARC
75451A
75451ATC
75451A
OUTPUT
INPUTS
2
1
(on state)
(on state)
(on state)
(off state)
L
L
L
H
L
L
L
H
H
H
L
H
Positive Logic: Z = X Y
H = HIGH Level, L"" LOW Level
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated.
SYMBOL
TEST
CHARACTER ISTICS
CONDITIONS
FIGURE
V IH
Input HIGH Voltage
7
V IL
Input LOW Voltage
7
VCD
Input Clamp Diode Voltage
8
10H
Output HIGH Current
7
VOL
Output LOW Voltage
7
II
Input Current at Maximum Input Voltage
9
IIH
Input HIGH Current
9
IlL
Input LOW Current
8
MIN
Supply Current, Output HIGH
ICCL
Supply Current Output LOW
NOTE 13. All typical values are at VCC
AC CHARACTERISICS: VCC
SYMBOL
=5 V, TA
MAX
08
V
-1.5
V
= MIN, II =-12 mA
VCC = MIN, VOH = 30 V
V IH = 2 V
VCC = MIN, V IL = 0.8 V
10L = 100 mA
55451A
0.25
0.5
75451A
0.25
0.4
VCC - MIN, VIL - 0.8 V
55451 A
0.5
0.8
= 300 mA
=MAX, VI = 5.5 V
Vec =MAX, VI = 2.4 V
VCC =MAX, VI = 0.4 V
V CC =MAX, VI = 5 V
Vce = MAX, VI = 0 V
75451A
0.5
0.7
VCC
55451A
300
75451A
100
1.0
VCC
10
UNITS
V
2
10L
leCH
TYP
(Note 13)
Jl.A
V
mA
40
Jl.A
-l.S
mA
7.0
11
mA
52
65
mA
-1.0
= 25°C.
=5 V, TA =25°C.
CHARACTER ISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
tTLH
Transition Time, OutP~t LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
TEST
CONDITIONS
FIGURE
10 '" 200 mA, e L
14
RL
15
Vs
7-S
MIN
= 15 pF,
= 50 n
=20 V, 10
'" 300 mA
Vs -6.5
TYP
MAX
UNITS
20
55
ns
20
40
ns
8
20
ns
12
20
ns
mV
FAIRCHILD • 55450A/75450A SERIES
55452A/75452A
DUAL POSITIVE NAND PERIPHERAL DRIVER
EOUIVALENT CIRCUIT (Each Drive,)
CONNECTION DIAGRAM
B-PIN DIP
ITOP VIEW)
PACKAGE OUTLINES 9T 6T
PACKAGE CODES T
R
vee
1.6 k
4'
n
INPUTS
r
*
~
2~
~
2~
1~8
OUTPUT
~2:
pvcc
INA1[-
.--
~
""r::3hJ
Ib f=P'6""
~
K
2
130
1.6 k
~INBl
aUTAe
4
1k
1k
5
GNOt
500
:JOUTB
GND
-=-
Component values shown, are nominal. All resistor values in ohms.
TRUTH TA.BLE
INPUTS
1
ORDER INFORMATION
PART NO_
TYPE
55452ARM
55452A
75452ARC
75452A
75452A
75452ATC
OUTPUT
2
L
L
H
H
L
H
H
H
L
H
H
L
loff state)
(off state)
loff state I
(on state)
Positive Logic: Z = XV
H == HIGH Level, L"'" LOW Level.
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated.
SYMBOL
TEST
CHARACTERISTICS
MIN
CONDITIONS
FIGURE
TYP
(Note 14)
MAX
V IH
Input HIGH Voltage
7
VIL
Input LOW Voltage
7
VCD
Input Clamp Diode Voltage
8
VCC = MIN, II = -12 mA
7
VCC = MIN, VOH = 30 V
V IL = 0.8 V
55452A
300
75452A
100
VCC = MIN, V IH = 2 V
55452A
0.25
0.5
10L = 100 mA
75452A
0.25
0.4
VCC - MIN, V IH - 2 V
55452A
0.5
0.8
10L = 300 mA
75452A
0.5
0.7
10H
VOL
Output HIGH Current
Output LOW Voltage
V
2
7
UNITS
0.8
V
-1.5
V
1J.A
V
II
Input Current at Maximum Input Voltage
9
VCC = MAX, VI = 5.5 V
1.0
IIH
Input HIGH Current
9
VCC = MAX, VI = 2.4 V
40
1J.A
IlL
Input LOW Current
8
VCC = MAX, VI = 0.4 V
-1.6
mA
ICCH
Supply Current, Output HIGH
ICCL
Supply Current Output LOW
NOTE 14. All typical values are at
Vee = 5 V, TA
10
-1.0
mA
VCC = MAX, VI = 0 V
11
14
mA
VCC=MAX,VI=5V
56
71
mA
= 25°C.
AC CHARACTERISTICS: VCC = 5 V, TA = 25°C
SYMBOL
CHARACTER ISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOYV
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
V OH
HIGH Level Output Voltage After SWitching
TEST
FIGURE
CONDITIONS
MIN
10'" 200 mA, CL = 15 pF,
14
RL = 50n
Vs = 20 V, 10 ~ 300 mA
15
7-7
Vs -6.5
TYP
MAX
UNITS
25
65
ns
25
50
ns
8
25
ns
12
20
ns
mV
I
FAIRCHILD • 55450A/75450A SERIES
55453A/75453A
DUAL POSITIVE OR PERIPHERAL DRIVER
EQUIVALENT CIRCUIT (Each Driver)
CONNECTION DIAGRAM
B-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 9T 6T
PACKAGE CODES T
R
vee
4k
1.6k
4k
130
V
1~8
OUTPUT
i~
INPUTS
I~
:s~
I
INA1~~
~
,"¢Wll
2-
OUTA[
4
r:?'"
~VCC
:]'N01
5
GND[
'2~
'2~
~
l
1k
500
GNO
Component values shown are nominal. All resistor values in ohms.
ORDER INFORMATION
TYPE
PART NO_
55453A
55453ARM
75453A
75453ARC
75453A
75453ATC
TRUTH TABLE
INPUTS
OUTPUT
,1
2
L
L
L
H
L
H
H
H
H
=
jOUTB
(on state)
(off state)
(off state)
(off state)
L
H
H
H
Positive Logic: Z
=X +
Y
HIGH Level, L = LOW ~evel
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated.
SYMBOL
CHARACTER ISTICS
TEST
MIN
CONDITIONS
FIGURE
TYP
(Note 15)
MAX
2
V
VIH
Input HIGH Voltage
7
V IL
Input LOW Voltage
7
VCD
Input Clamp Diode Voltage
8
VCC = MIN, II = -12 mA
7
VCC = MIN, V OH = 30 V
V IH = 2 V
55453A
300
75453A
100
VCC = MIN, VIL = 0.8 V
55453A
0.25
0.5
10L = 100 mA
75453A
0.25
VCC - MIN, V IL - 0.8 V
10L = 300 mA
55453A
75453A
0.5
0.4
0.8
0.5
0.7
10H
Output HIGH Current
UNITS
0.8
V
-1.5
V
!J.A
V
VOL
Output LOW Voltage
7
II
Input Current at Maximum Input Voltage
9
VCC = MAX, VI = 5.5 V
1.0
IIH
Input HIGH Current
9
VCC = MAX, VI = 2.4 V
40
!J.A
IlL
Input LOW Current
8
VCC = MAX, VI = 0.4 V
-1.6
mA
ICCH
Supply Current. Output HIGH
ICCL
Supply Current Output LOW
11
-1.0
mA
VCC = MAX, VI = 5 V
8.0
11
mA
aV
54
68
mA
VCC = MAX, VI =
NOTE 15. All typical values are at Vee = 5 V, TA = 25°e.
AC CHARACTERISTICS: VCC = 5 V, TA = 25 'C.
SYMBOL
CHARACTER ISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
TEST
CONDITIONS
FIGURE
10
14
~
MIN
200 mAo CL = 15 pF,
RL = 50!1
15
Vs = 20 V, 10
7-8
~
300 rnA
Vs -6.5
TYP
MAX UNITS
20
55
ns
20
40
ns
8
25
ns
12
25
ns
mV
FAIRCHILD • 55450A/75450A SERIES
55454A/75454A
DUAL POSITIVE NOR PERIPHERAL DRIVER
CONNECTION DIAGRAM
EQUIVALENT CIRCUIT (Each Driver)
8·PIN FLATPAK
(TOP VIEW)
PACKAGE OUTLINES 9T 6T
PACKAGE CODES T
R
vee
4k
2k
4k
2k
=J"
INPUTS
{~
I
I
=
~
-;~
'""'c:3hJ1
OUTA[:
4
f:J'"6"
~INBl
5
GNDC
~
1
1k
pvee
INAlr -
~
>-K
:;;s::
"2~
1~8
OUTPUT
"Z:
1k
JOUTB
500
GND
Component values shown are nominal. All resistor values in ohms.
ORDER INFORMATION
TYPE
PART NO.
55454A
55454ARM
75454A
75454ARC
75454A
75454ATC
TRUTH TABLE
INPUTS
OUTPUT
1
2
L
L
H
H
L
H
L
H
H
=
(off state)
(on state)
(on state)
(on state)
H
L
L
L
Positive Logic: Z
=
'X"'+Y
HIGH Level, L = LOW Level
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range. use Test Table 1, pg. 1,
unless otherwise indicated.
SYMBOL
CHARACTER ISTICS
TEST
CONDITIONS
FIGURE
V IH
Input HIGH Voltage
7
V IL
Input LOW Voltage
7
V CD
Input Clamp Diode Voltage
8
VCC
7
VCC = MIN, VO H
V IL = 0.8 V
10H
Output HIGH Current
Output LOW Voltage
7
II
Input Current at Maximum Input Voltage
9
IIH
Input HIGH Current
9
IlL
Input LOW Current
8
=MIN, II = ~12 mA
= 30 V
= MIN, V IH
10L = 100 mA
VCC ~ MIN, V IH
=2 V
= 300 mA
=MAX, VI
VCC = MAX, VI
VCC = MAX, VI
VCC = MAX, VI
~
2V
10L
ICCH
Supply Current, Output HIGH
ICCL
Supply Current Output LOW
NOTE 16. All typical values are at
Vee:::::
AC CHARACTERISTICS: VCC
SYMBOL
MAX
VCC
11
VCC
= MAX,
VI
UNITS
V
2
VCC
VOL
MIN
TYP
(Note 16)
0.8
V
~1.5
V
55454A
300
75454A
100
55454A
0.25
0.5
75454A
0.25
0.4
55454A
0.5
0.8
75454A
0.5
0.7
IlA
V
= 5.5 V
1.0
= 2.4 V
40
IlA
~1.6
mA
13
17
mA
61
79
mA
= 0.4 V
=a V
~1.0
=5 V
mA
5 V, TA = 25°C.
= 5 V,
TA
= 25°C.
CHARACTERiStiCS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
TEST
CONDITIONS
FIGURE
10
~
RL
= 50 n
14
15
Vs
7-9
200 mAo CL
= 20 V,
10
~
MIN
= 15 pF,
300 mA
Vs
~6.5
TYP
MAX
UNITS
25
65
ns
25
50
ns
8
20
ns
12
20
ns
mV
I
FAIRCHILD • 55450A/75450A SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
DC TEST CIRCUITt
Vee
VI L
o-------iL....J
VOH
VOL
1
1
I
Both inputs are tested simultaneously
1
Each input is tested separately.
Fig. 1
Fig. 2
4.5 V
Vee
Vee
~I
VIO
"1fT
1 1
--
OPEN
SUB
GND
Vlo-----~r-~
SUB
OPEN
GND
--
NOTES:
A. Each input is tested separately.
B. When testing VCD. input not under test
is open.
Each input is tested separately
Fig. 4
Fig. 3
lOS
Vee
Vee
Vlo---.......---{-,
110S
SUB
OPEN
GND
Each gate is tested separately.
Both gates are tested simultaneously.
(55450A!75450A only)
Fig. 5
Fig. 6
7-10
FAIRCHILD • 55450A/75450A SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
TEST TABLE II
Vee
CIRCUIT
-
IOH
A
V ,H
SEE
TEST
TABLE
V,L
CIRCUIT
UNDER
TEST
y
SEE
TEST
TABLE
VOH
55175451 A
:,\IOL
55175452A
55175453A
VOL
-::-
1I
55175454A
OUTPUT
INPUT
UNDER
TEST
OTHER
INPUT
V,H
V,I-!
VOH
IOH
V,L
VCC
IOL
VOL
V,H
V,I-!
IOL
VOL
V,L
VOH
IOH
V,H
Vce
GND
VOH
IOH
V,L
V,L
IOL
VOL
V,H
GND
IOL
VOL
V,L
V,L
VOH
IOH
APPLY
MEASURE
-::-
-::-
NOTE:
Each input is tested separately.
Fig.7
Vee
Vce
4.5 V
<>---f
SEE
.r-L',L
0TES
A,B
V , O - - - - ' - i CIRCUIT
OPEN
VIOf-~:"--
B,A
NOTES;
A. Each input is tested separately.
B. When testing II L 55/75453A and
55/75454A, the input not under test
is grounded. For all other circuits it is
UNDER
TEST
OPEN
Each input is tested separately.
Fig,9
at4.5V.
C, When testing V CD, input not under test
is open.
Fig, 8
'CCH.'CCL
FOR AND. NAND CIRCUITS
'CCH.'CCL
FOR OR. NOR CIRCUITS
Vee
vee
Both gates are tested simultaneously.
Fig. 11
Both gates are tested simultaneously.
Fig. 10
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
7-11
I
FAIRCHILD • 55450A/75450A SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
SWITCHING CHARACTERISTICS
PROPAGATION DELAY TIMES, EACH GATE
(55450A, 75450A ON LVI
TEST CI RCUIT
INPUT 2.4 V
PULSE
GENERATOR
(See Note A)
Vee
OUTPUT
5V
~J---~__.J~-T~~~
VOLTAGE WAVEFORMS
--i
1
1-1----"-+1- <;lOns
1
I
t--<;5ns
1
INPUT---.i~1
90%
1
1.5V
1
~~1
90%
1
10%
10%
1
1.5V
1
•-1
.:j--r - - - - - - I;~-=:::::::Qs;,-::::~~
0.5ps
~~---
_ _ _ _'_PL_H_.J'):
_
OUTPUT.
NOTES:
•
A. The pulse generator has the following characteristics:
PRR ~ 1 MHz, Zout '" 50 n.
B. CL include probe and jig capacitance.
C. All diodes are FD777.
Fig. 12
7-12
3V
OV
FAIRCHILD • 55450A/75450A SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
SWITCHING CHARACTERISTICS
SWITCHING TIMES, EACH TRANSISTOR
(55450A, 75450A ONL Yl
TEST CIRCUIT
INPUT
-IV
lOV
:>
<:>
:>
Ikll
.....-~--~--o OUTPUT
~-~
-l:
1
1--..........--111-.....-"1/\/'v--+
J SUB
1
L_
I1
CL
~
15 pF
IS.o Not. BJ
~
I
VOL TAGE WAVEFORMS
1•
~5
INPUT
I
1
vJ/f90%
IO";~;III
___
"I
0.3",
90%i\.f,W- - - - - - - - -
i i i ~O%
~';;;5ns
1
<5ns~
1
t,~
td-J----j
tf~
I--t-tr
OUTPUT----------I-~~~~:----------~~:90%-l~~k------------
NOTES:
A. The pulse generator has the following characteristics:
duty cycle
~
1%, Zout
~
50
n.
B. CL includes probe and jig capacitance.
Fig. 13
7-13
3V
OV
FAIRCHILD • 55450A/75450A SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
SWITCHING CHARACTERISTICS
SWITCHING TIMES OF COMPLETE DRIVERS
TEST CI RCUIT
INPUT
10V
2.4 V
....- ....- 0
OUTPUT
0.4 V
VOLTAGE WAVEFORMS
~
o%
INPUT
5517545QA
55/75451A
55/75453A
---i I--- ~
I - ~5 n,
--1
I
:
1.5 V
:
1
15V
I I
J
1_ _ _ _ _ _ _ _ _
1
90%
55175452A
I:
1
55/75454A
1
I_
10%_ _ _ _ _
"-~
•I
,
!
-,
°V
I
£'
-i,
tpHL
tPLHI--+__- -••
--~9~0%~:
NOTES:
V
---UJ=--<.20~----3V
90%
I
°
0.5", - - - - - - -•.jl
I.
: 1-<5n,
OUTPut
3V
0 :190%
1
. ..;1,::0..::%"-_ _ _ _ _ _ _ _ _ _ _';,;;{l;.;%:.J
I-
INPUT
n,
10
50%
50%
!'-'_O%
____________'_o%..... _
I--tTHL
tTLH---j
A. The pulse generator has the following characteristics:
PRR = 1 MHz, Zout ~ 50 f2.
B. When Testing 55450A/75450A, connect output Y to
transistor base and ground the substrate terminal.
C. CL includes probe and jig capacitance.
Fig. 14
7-14
90%
VO H
L___
VOL
,
I--
FAIRCHILD • 55450A/75450A SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
SWITCHING CHARACTERISTICS
LATCH-UP TEST OF COMPLETE DRIVERS
TEST CIRCUIT
Vee
24V
INPUT
~
20 v
5 V
1
55 75450A
55/75451 A
55 75452A
OUTPUT
PULSE
GENERATOR
lSee Note A)
CL = 15 ~'F
ISt."t' NOlI:' C
55175453A
55175454A
T~
I
0.4 V
VOLTAGE WAVEFORMS
----i
INPUT
55175450A
5517545iA
55/75453A
~0'%5V:I
I
I
. ._':.:0~%:....
Jf'
I•
~~:;~:~~~
:
~"lOns
''r:::-:::-____ 3 V
I
15~%
0I :
_ _ _ _ _ _ _ _ _ _~'0~%;.,j
I'
---I, I,
INPUT
--i
t--.;;;5ns
I
I
r-" 5 n,
1_________
1
40", - - - - - - -•.,1
---1
I
I- <
~'::9~0::;%------------:9~0~%\:-:-
1.5 V
, 5V
n,
------10
10%
OUTPUT
A. The pulse generator has the following characteristics:
PAR =: 12.5 kHz, Zout == 50 n.
B. When testing 55450A or 75450A, connect output Y
to transistor base with a 500·D resistor from there to
ground, and ground the substrate terminal.
C, CL includes probe and jig capacitance.
Fig. 15
7-15
3V
I
10%
NOTES:
0V
OV
FAIRCHILD • 55450A/75450A SERIES
TYPICAL PERFORMANCE CURVES FOR 75450A SERIES
55450A/75450A TTL GATE
HIGH-LEVEL OUTPUT
VOL TAGE AS A FUNCTION
OF HIGH-LEVEL OUTPUT
CURRENT
0
5
5
"
t------ ~ ~~~ "~5~~-
5
J"
55450A175450A TRANSISTOR
STATIC FORWARD CURRENT
TRANSFER RATIO AS A
FUNCTION OF
COLLECTOR CURRENT
I
0
TA=,l5 C
0
~
5
1\
0
5
:~
\
5
I
~,
III
-1::.s-
o
\
0
~
-
lI.-
I
l.-
I
0
I
l.-
~!- 11
II
I
5
0
-
S~~;,~~~,r
I
I
S~',"",e.'
I
!
COLLECTOR CURRENT-
TRANSISTOR COLLECTOREMITTER SATURATION
VOLTAGE AS A FUNCTION OF
COLLECTOR CURRENT
55450A175450A TRANSISTOR
BASE-EMITTER VOLTAGE
AS A FUNCTION OF
COLLECTOR CURRENT
,
~c.
"
o
SEBE
= 10
6
I
NO~E 1701.1
-3 ~
.-
9 _ TA=_55°C
,
-
_-1:
'6_
5
,
,~
,
,
-~'f-
I
~
I
70'C
3
,
I
II ,I
II II
10
I
I
125°C
'I
I I
\I
~~
" NOTE 17
SEE
,
~V
~
\'2S"C
5
,
I
0
I I
TL,25,1C
.a!iii
I"O~ ~
r~ ::::"
==~ ~~
1
I i
0
70100
COLLECTOR CURRENT -
NOTE 17: These parameters must be measured using pulse techniques. tw
7-16
_55 °C
=
rnA
300 Jls, duty cycle";;; 2%.
55/754508 • 55/75451 B • 55/754528
55/754538 • 55/754548
DUAL HIGH SPEED PERIPHERAL DRIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The 55/75450B, 55/75451 B, 55/75452B, 55/75453B and 55/75454B are Dual High Speed General Purpose Interface
Drivers that convert TTL and DTL logic levels to high current drive capability. The 55450B and 75450B feature two TTL NAND gates and two
uncommitted transistors. The 55/75451 B, 55/75452B, 55/75453B and 55/75454B feature two standard series 74 TTL gates in AND, NAND, OR and
NOR configurations respectively, driving the base of two high voltage, high current, uncommitted collector output transistors.
The 55/754508 series offers flexibility in designing high speed logic buffers, power drivers, lamp drivers, line drivers, MOS drivers, clock drivers and
memory drivers.
•
•
•
•
•
•
NO LATCH-UP AT 20 V
HIGH SPEED SWITCHING
HIGH OUTPUT CURRENT CAPABILITY
TTL OR DTL INPUT COMPATIBILITY
INPUT CLAMP DIODES
+5 V SUPPLY VOLTAGE
•
TEST TABLE 1 - Operating Temperature Range and Supply Voltage Range
55450B Series
Temperature, T A
Supply Voltage, V CC
75450B Series
_55° C to +125° C
O°C to 70°C
+4.5 V to +5.5 V
+4.75 V to +5.25 V
ABSOLUTE MAXIMUM RATINGS
55450B
Supply Voltage, V CC (See Note 1)
Input Voltage (See Note 1)
Interemitter Voltage(See Note 2)
VCC to Substrate Voltage (See Note 6)
Collector to Substrate Voltage (See Note 6)
Collector to Base Voltage
Collector to Emitter V.oltage (See Note 3)
Emitter to Base Voltage
Output Voltage (See Notes 1 and 4)
Continuous Collector Current (See Note 5)
Continuous Output Current (See Note 5)
Continuous Total Power Dissipation (See Note 7)
Operating Free-Air Temperature Range
Storage Temperature Range
Pin Temperature
Molded DIP (Soldering, 10 s)
Hermetic DIP
(Soldering, 60 s)
75450B
7V
5.5 V
5.5 V
35 V
35 V
35 V
30 V
5V
75451B
75452B
75453B
75454B
7V
7V
5.5 V
5.5 V
35 V
35 V
35 V
30 V
5V
5.5 V
5.5 V
7V
5.5 V
5.5 V
30 V
30 V
300mA
BOOmW
_55° C to +125° C
_65°C to +150°C
300mA
BOOmW
O°C to 70°C
_65° C to +150° C
260°C
300°C
260°C
300°C
300mA
300mA
BOOmW
_55°C to +125°C
_65° C to +150° C
BOOmW
O°C to 70°C
_65° C to +150° C
260°C
300°C
300°C
55451B
55452B
55453B
554548
NOTES:
1. Voltage values are with respect to network ground terminal unless otherwise specified.
2. This is the voltage between two emitters of a mu Itiple-emitter input transistor.
3. This value applies when the base-emitter resistance (RBE) is equal to or less than 500 n.
4. This is the maximum voltage which should be applied to any output when it is in the off state.
5. Both halves of these dual circuits may conduct rated current simultaneously.
6. For the 55450B and 75450B only, the substrate (Pin 8), must always be at the most negative device vo~tage for proper operation.
7. Above 60°C ambient temperature, derate linearly at B.3 mWtC for Hermetic DIP and Molded DIP. For the Molded Mini DIP and Hermetic Mini
DIP, derate at 6.7 mwtC above 30°C.
7-17
FAIRCHILD • 554508/754508 SERIES
554508/754508
DUAL POSITIVE AND PERIPHERAL DRIVER
EQUIVALENT CIRCUIT
r----~---.._-.._---_o
1.6 k
4'
CONNECTION DIAGRAM
14·PIN
(TOP VIEW)
PACKAGE OUTLINE 6A. 9A
PACKAGE CODE D
P
vcc
130
GATE
1E
INA
OUT A
INA
lB
lC
lC
lE
SUB
GND
LOGIC FUNCTION
2C
Positive Logic: Z
IN B
Z
0-+-1--+
= XV
=XY
(gate only)
(gate and transistor)
2E
ORDER INFORMATION
TYPE
PART NO.
55450B
55450BDM
75450B
75450BDC
75450B
75450BPC
L-~--~----~--~~~-----------oGND
All resistor values in ohms.
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated
TTL Gates
SYMBOL
TEST
CHARACTER ISTICS
CONDITIONS
FIGURE
V,H
Input HIGH Voltage
1
V,l
Input LOW Voltage
2
VCD
Input Clamp Diode Voltage
3
VCC = MIN, " = -12 mA
VCC = MIN, V ,L = 0.8 V
10H = -4001lA
VOH
Output HIGH Voltage
2
VOL
Output lOW Voltage
1
Input Current at Maximum
Input Voltage
Input A
Input G
Input A
"H
Input HIGH Current
',L
Input LOW Current
lOS
Short Circuit Output Current (Note 9)
'CCH
Supply Current. Output HIGH
'CCl
Supply Current, Output lOW
Input G
Input A
Input G
VCC = MIN, V ,H = 2 V
4
VCC = MAX, V, = 5.5 V
4
VCC = MAX. V, = 2.4 V
3
VCC = MAX, V, = 0.4 V
5
VCC = MAX
6
TYP
(Note 8)
MAX
2
'Ol = 16 mA
"
MIN
2.4
I 55450B
V
0.8
V
-1.5
V
3.3
V
0.22
0.5
0.22
0.4
V
I 75450B
1
2
40
80
-1.6
-3.2
-18
-55
VCC = MAX, V, = OV
2
4
VCC = MAX, V, = 5V
6
11
NOTES:
8. All typical values at Vce = 5 V, TA = 25°e.
9. Not more than one output should be shorted at a time.
7-18
UNITS
mA
IlA
mA
mA
mA
FAIRCHILD • 554508/754508 SERIES
55450B/75450B
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use
Test Table 1, pg. 1, unless otherwise indicated
Output Transistors
TYP
(Note 10)
SYMBOL
CHARACTERISTICS
V(BR)CBO
Collector to Base Breakdown Voltage
IC = 100",A, IE = 0
35
V
V(BR)CER
Collector to Emitter Breakdown Voltage
IC = 100, ",A.-R BE = 500 n
30
V
V(BR)EBO
Emitter to Base Breakdown Voltage
IE = 100yA, IC = 0
5
V
hFE
Static Forward Current Transfer Ratio
(Note 11)
VBE(sat)
VCE(sat)
Base to Emitter Voltage (Note 11)
Collector to Emitter Saturation Voltage
(Note 11)
CONDITIONS
MIN
VCE = 3 V, IC = 100 mA, TA = 25°C
25
VCE = 3 V, IC = 300 mA. TA = 25°C
55450B
VCE - 3 V,
30
IC = 100 mA
20
75450B
MAX UNITS
10
VCE - 3 V,
55450B
15
IC = 300 mA
75450B
25
IB =10mA.
IC = 100 mA
55450B
0.B5
1.2
V
75450B
0.85
1.0
V
IB = 30 mA,
55450B
1.05
1.4
V
IC = 300 mA
75450B
1.05
1.2
V
IB - 10 mA,
55450B
0.25
0.5
V
IC=100mA
75450B
0.25
0.4
V
IB - 30 mA,
55450B
0.5
0.8
V
IC = 300 mA
75450B
0.5
0.7
V
NOTES:
10. All typical values are at Vee = 5 V. TA = 25°e.
11. These parameters must be measured using the pulse techniques. tw = 300 f.,LS, duty cycle
s: 2%.
AC CHARACTERISTICS: VCC = 5 V, TA = 25°C
TTL Gates
CHARACTERISTICS
SYMBOL
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
TEST
FIGURE
12
CONDITIONS
MIN
C L = 15 pF, RL = 400 n
TYP
MAX UNITS
12
22
ns
8
15
ns
Output Transistors
CHARACTERISTICS
SYMBOL
td
Delay Time
tr
Rise Time
ts
Storage Time
tf
Fall Time
TEST
CONDITIONS
FIGURE
(Note 12)
13
MIN
TYP
MAX UNITS
IC = 200 mA. VBE(off) = -1 V
8
15
ns
IB( 1) = 20 mA. IB(2) = -40 mA
12
20
ns
7
15
ns
6
15
ns
CL = 15 pF, RL = 50 n
Gates and Transistors Combined
SYMBOL
CHARACTERISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
TEST
CONDITIONS
FIGURE
MIN
IC = 200 mA. CL = 15 pF,
14
RL = 50 n
Vs = 20 V, IC ~ 300 mA
RBE = 500n
15
NOTE 12. Voltage and current values shown are nominal; exact values vary slightly with transistor parameters.
7-19
Vs -6.5
TYP
MAX UNITS
20
30
ns
20
30
ns
7
12
ns
9
15
ns
mV
•
FAIRCHILD • 554508/754508 SERIES
55451 B/75451 B
DUAL POSITIVE AND PERIPHERAL DRIVER
CONNECTION DIAGRAMS
8-PIN DIP
(TOP VIEW)
PACKAGE OUTLINE 9T 6T
PACKAGE CODE T
R
EQUIVALENT CIRCUIT (Each Driver)
Vee
4k
1.6 k
'30
INPUTS
INAl
{~'~
IN A2
2
OUT A
Component values shown are nominal. All resistor values in ohms.
TRUTH TABLE
INPUTS
H
=
ORDER INFORMATION
TYPE
PART NO_
55451B
55451BRM
75451B
75451BRC
75451B
75451BTC
OUTPUT
X
Y
L
L
H
H
L
H
L
H
Z
L
L
L
H
(on state)
(on state)
(on state)
(off state)
Positive Logic: Z
~
XV
HIGH Level, L = LOW Level
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated
SYMBOL
CHARACTERISTICS
TEST
CONDITIONS
FIGURE
V IH
Input HIGH Voltage
7
V il
Input LOW Voltage
7
V CD
Input Clamp Diode Voltage
8
VCC = MIN, II = -12 mA
7
VCC = MIN, VO H = 30 V
V IH = 2 V
10H
Output HIGH Current
MIN
TYP
(Note 13)
MAX
UNITS
V
2
0.8
V
-1.5
V
300
55451B
75451B
100
VCC = MIN, Vil = 0.8 V
55451B
0.25
0.5
75451B
0.25
0.4
55451B
0.5
!0.8
10l = 300 mA
75451B
0.5
0.7
IlA
VOL
Output lOW Voltage
7
10L = 100 mA
VCC = MIN, V il = 0.8 V
II
Input Current at Maximum Input Voltage
9
VCC = MAX, VI = 5.5 V
1.0
IIH
Input HIGH Current
9
VCC = MAX, VI = 2.4 V
40
IlA
III
Input lOW Current
8
VCC = MAX, VI = 0.4 V
-1.6
mA
ICCH
Supply Current, Output HIGH
ICCl
Supply Current Output LOW
10
-1.0
V
mA
V CC = MAX, VI = 5 V
7.0
11
mA
VCC = MAX, VI = 0 V
52
65
mA
NOTE 13. All typical values are at Vee = 5 V. TA = 25°e.
AC CHARACTERISTICS: VCC = 5 V, TA = 25°C
SYMBOL
CHARACTERISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHl
Propagation Delay Time, Output HIGH to lOW
tTlH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
TEST
FIGURE
CONDITIONS
MIN
10 '" 200 mA, CL = 15 pF,
14
RL = 50
15
n
Vs = 20 V, 10 '" 300 mA
7-20
Vs -6.5
TYP
MAX UNITS
18
25
ns
18
25
ns
5
8
ns
7
12
ns
mV
FAIRCHILD • 55450B/75450B SERIES
554528/754528
DUAL POSITIVE NAND PERIPHERAL DRIVER
EQUIVALENT CIRCUIT (Each Driver)
CONNECTION DIAGRAMS
8-PIN DIP
(TOP VIEW)
PACKAGE OUTLINE 9T 6T
PACKAGE CODE T
R
vee
4k
1.6 k
1.6k
~
T.
INPUTS
{'
~
~
INA1~r-----,
2~
~INBl
aUlAC
4
1k
1k
~Vcc
"'~~ f?'"
~
K
~
2~
l~B
OUTPUT
::s~
K
2
130
5
GNOt
500
POUTB
GNO
-=-
Component values shown are nominal. All resistor values in ohms.
TRUTH TABLE
INPUTS
X
Y
L
L
H
H
L
H
L
H
H
=
ORDER INFORMATION
TYPE
PART NO_
55452B
55452BRM
75452B
75452BRC
75452B
75452BTC
OUTPUT
Z
(off state)
(off state)
(off state)
(on state)
H
H
H
L
Positive Logic: Z =
"XV
HIGH Level, L = LOW Level.
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated
SYMBOL
CHARACTERISTICS
TEST
V IH
Input HIGH Voltage
7
VIL
Input LOW Voltage
7
VCD
Input Clamp Diode Voltage
8
10H
Output HIGH Current
7
MIN
CONDITIONS
FIGURE
TYP
(Note 14)
MAX
V
2
VCC = MIN, II = -12 mA
VCC = MIN, V OH = 30 V
VIL = 0.8 V
UNITS
0.8
V
-1.5
V
300
55452B
75452B
100
VCC = MIN, V IH = 2 V
10L = 100 mA
55452B
0.25
0.5
75452B
0.25
0.4
VCC - MIN, V IH - 2 V
10L = 300 mA
55452B
0.5
0.8
75452B
0.5
0.7
p.A
VOL
Output LOW Voltage
7
II
Input Current at Maximum Input Voltage
9
VCC = MAX, VI = 5.5 V
1.0
IIH
Input HIGH Current
9
VCC = MAX, VI = 2.4 V
40
p.A
IlL
Input LOW Current
8
VCC = MAX, VI = 0.4 V
-1.6
mA
ICCH
Supply Current, Output HIGH
ICCL
Supply Current Output LOW
10
-1.0
V
mA
VCC = MAX, VI = 0 V
11
14
mA
VCC = MAX, VI = 5 V
56
71
mA
NOTE 14. All typical values are at VCC = 5 V, TA = 25°C.
AC CHARACTERISTICS: VCC = 5 V, TA = 25°C
SYMBOL
CHARACTER ISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
TEST
FIGURE
CONDITIONS
MIN
10 ", 200 mA, CL = 15 pF,
14
RL = 50n
15
Vs = 20 V, 10 '" 300 mA
7-21
Vs -6.5
TYP
MAX UNITS
25
35
ns
22
35
ns
5
8
ns
7
12
ns
mV
•
FAIRCHILD • 554508/754508 SERIES
554538/754538
DUAL POSITIVE OR PERIPHERAL DRIVER
EQUIVALENT CIRCUIT (Each Driver)
CONNECTION DIAGRAMS
a-PIN DIP
(TOP VIEW)
vee
1.6k
4'
PACKAGE OUTLINE 9T
PACKAGE CODE T
130
4'
V
r-.
'1
INPUTS
:
{
1~8
OUTPUT
:=:~
-
INA1~)----"'"
,"~c:Ulj
OUTA[
4
:::i~
'r-
1k
jvcc
~""
~IN81
5
GNO[
~
:::i~
r
6T
R
POUTB
500
GND
.".
ORDER INFORMATION
TYPE
PART NO.
55453B
55453BRM
75453B
75453BRC
75453BTC
75453B
Component values shown are nominal. All resistor values in ohms.
TRUTH TABLE
INPUTS
OUTPUT
X
Y
L
L
H
H
L
H
L
H
H
=
Z
L
H
H
H
(on state)
(off state)
(off state)
(off state)
Positive Logic: Z "" X
+Y
HIGH Level, L = LOW Level
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated
SYMBOL
CHARACTERISTICS
TEST
V IH
Input HIGH Voltage
7
V IL
Input LOW Voltage
7
V CD
Input Clamp Diode Voltage
8
10H
Output HIGH Current
7
VOL
Output LOW Voltage
7
II
Input Current at Maximum Input Voltage
9
IIH
Input HIGH Current
9
IlL
Input LOW Current
8
ICCH
Supply Current, Output HIGH
ICCL
Supply Current Output LOW
CONDITIONS
FIGURE
11
MIN
TYP
(Note 15)
MAX UNITS
2
= MIN, II =-12 rnA
VCC = MIN, VOH = 30 V
V IH = 2 V
VCC = MIN, V IL = 0.8 V
10L = 100 rnA
V
VCC
VCC - MIN, V IL - 0.8 V
10L = 300 rnA
=MAX, VI
VCC =MAX, VI
VCC =MAX, VI
VCC =MAX, VI
Vce = MAX, VI
VCC
0.8
V
-1.5
V
55453B
300
75453B
100
554538
754538
0.25
0.5
0.25
554538
754538
0.5
0.4
0.8
0.5
0.7
= 5.5 V
=2.4 V
=0.4 V
= 5V
=0 V
1.0
JlA
V
rnA
40
JlA
-1.6
rnA
8.0
11
rnA
54
68
rnA
-1.0
=5 V, TA =25°e.
VCC = 5 V, TA = 25°C
NOTE 15. All typical values are at Vee
AC CHARACTERISTICS:
SYMBOL
CHARACTERISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
TEST
CONDITIONS
FIGURE
10'" 200 rnA, CL
14
RL
15
Vs
7-22
MIN
= 15 pF,
= 50 n
= 20 V,
10 '" 300 rnA
Vs -6.5
TYP
MAX UNITS
18
25
ns
16
25
ns
5
8
ns
7
12
ns
mV
FAIRCHILD • 554508/754508 SERIES
55454B/75454B
DUAL POSITIVE NOR PERIPHERAL DRIVER
EQUIVALENT CI RCUIT (Each Driver)
4k
2k
4k
INPUTS
2k
I
{:
B-PIN DIP
(TOP VIEW)
PACKAGE OUTLINE 9T
PACKAGE CODE T
vec
OUTPUT
r:
INAlt~
~
,,,,cCIl
3
OUT A
V
ti}4
1
:Jvcc
~'""
6
j'N.'
5
GNDC
1k
6T
R
1~8
::s~
f---K
1k
~
tt
~
::;~
::;~
CONNECTION DIAGRAMS
jOUTB
500
GND
Component values shown are nominal. All resistor values in ohms.
ORDER INFORMATION
TYPE
PART NO_
55454B
55454BRM
75454B
75454BRC
75454BTC
75454B
TRUTH TABLE
INPUTS
X
Y
L
L
L
Z
H
L
H
=
HIGH Level, L
(off state)
(on state)
H
L
L
L
H
H
H
OUTPUT
=
(on state)
Positive Logic: Z=X+Y
(on state)
LOW Level
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated
SYMBOL
TEST
CHARACTERISTICS
CONDITIONS
FIGURE
V IH
Input HIGH Voltage
7
V IL
Input LOW Voltage
7
V CD
Input Clamp Diode Voltage
8
VCC
VCC = MIN, VOH = 30 V
V IL = 0.8 V
MIN
TYP
(Note 16)
MAX UNITS
V
2
0
MIN, II
0
-12 mA
0.8
V
-1.5
V
55454B
300
75454B
100
!J.A
10H
Output HIGH Current
7
VOL
Output LOW Voltage
7
II
Input Current at Maximum Input Voltage
9
VCC = MAX, VI = 5.5 V
1.0
IIH
Input HIGH Current
9
VCC = MAX, VI = 2.4 V
40
!J.A
IlL
Input LOW Current
8
VCC = MAX, VI = 0.4 V
-1.6
mA
ICCH
Supply Current, Output HIGH
ICCl
Supply Current Output lOW
NOTE 16. AII1ypieal values are at Vee
0
AC CHARACTERISTICS: VCC
5 V, TA
SYMBOL
0
11
5 V, TA
0
0
VCC = MIN, VIH = 2 V
55454B
0.25
0.5
10L = 100 mA
75454B
0.25
0.4
VCC - MIN, VIH - 2 V
55454B
0.5
0.8
10L = 300 mA
75454B
0.5
0.7
-1.0
V
mA
aV
13
17
mA
VCC = MAX, VI = 5 V
61
79
mA
VCC = MAX, VI =
25°e.
25°C
CHARACTERISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
V OH
HIGH Level Output Voltage After Switching
TEST
CONDITIONS
FIGURE
10
14
~
200 mA, CL = 15 pF,
RL = 50
n
Vs = 20 V, 10 ~ 300 mA
15
7-23
MIN
Vs -6.5
TYP
MAX uNITS
ns
27
35
24
35
ns
5
B
ns
7
12
ns
mV
II
FAIRCHILD • 554508/754508 SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
DC TEST CI RCUlTt
Vee
Vee
VIH
0 - - -.....- - 4
VIL
SUB
o-----t_)O-I~---,
GND
I
I
80th inputs are tested simultaneously.
Fig. 1
4.5 V
!
Each input is tested separately.
Fig. 2
Vee
Vee
OPEN
OPEN
NOTES:
A. Each input is tested separately.
8. When testing VCD, input not under test
is open.
Each input is tested separately
Fig. 3
Fig.4
lOS
Vee
Vee
VI
0---.---1-'
SUB
Each gate is tested separately.
(55450B/75450B only)
OPEN
GND
Both gates are tested simultaneously.
Fig. 5
Fig. 6
7-24
FAIRCHILD • 55450B/75450B SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
TEST TABLE II
VCC
CIRCUIT
A
SEE
TEST
TABLE
CIRCUIT
UNDER
TEST
Y
551154518
SEE t----OVOH
TEST
TABLEt--r____
IOL
~,
551154528
551154538
551154548
I
INPUT
UNDER
TEST
OTHER
INPUT
OUTPUT
VIH
VIH
VOH
IOH
Vil
VCC
IOl
VOL
APPLY
MEASURE
VIH
VIH
IOL
VOL
VIL
Vce
VOH
IOH
VIH
GND
VOH
IOH
VIL
VIL
IOL
VOL
VIH
GND
IOL
VOL
VIL
VIL
VOH
IOH
NOTE: Each input is tested separately.
Fig.7
II,IIH
Vec
VCC
4'5V~SEE
NOTES
-=VI
NOTES:
0
-
IlL
B, A
CIRCUIT
UNDER
TEST
y
II,IIH
OPEN
'I11IT 1
-=
A,B
VI
CIRCUIT
UNDER
TEST
B,A
-=-
A. Each input is tested separately.
Y
OPEN
Each input is tested separately.
B. When testing I, L 55/754538 and
Fig.9
55/75454B, the input not under test
is grounded. For all other circuits it is
at 4.5V.
C. When testing VeDI input not under test
is open.
Fig. 8
ICCH,ICCl
FOR AND, NAND CIRCUITS
ICCH,ICCl
FOR OR, NOR CIRCUITS
Vcc
Vcc
OPEN
OPEN
l
l
I
I
I
L
__ _
VI~----------+--i
I
-~
I
L __ _
Both gates are tested simultaneously.
Both gates are tested simultaneously.
Fig. 10
Fig. 11
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
7-25
I
I
I
•
FAIRCHILD· 55450B/75450B SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
AC CHARACTERISTICS
PROPAGATION DELAY TIMES, EACH GATE (55450B, 75450B ONLY)
TEST CIRCUIT
INPUT 2.4 V
Vee
OUTPUT
5V
PULSE
GENERATOR ..........---IL.J
(See Note A)
VOLTAGE WAVEFORMS
f--<;5ns
1----...1- <; 10ns
I
1
1
INPUT - - - - - ' "
3V
1
1.5V
1.5V
I
1
~I~.~::::::ii.0.5,5p:;s~:::~-=.:i.:T - - - - - - -
_
~L
_ _ _'_PL_H_oJ'){
OUTPUT.
NOTES:
A
OV
__
•
The pulse generator has the following characteristics: PRR = 1 MHz, Zout
B C L include probe and jig capacitance.
C All diodes are FD777.
Fig. 12
7-26
~
50
n
FAIRCHILD • 554508/754508 SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
AC CHARACTERISTICS
SWITCHING TIMES, EACH TRANSISTOR (55450B, 75450B ON L Y)
TEST CIRCUIT
-1 V
INPUT
19V
Q
'RL=50Sl
lkn
1I""'"' "
,...
0.1 MF
PULSE
GENERATOR
ISee Note AI
"-l:t
50 Sl
I
1
L~
62 Sl
-=
JSUB
~
OUTPUT
CL = 15 pF
•
VOL TAGE WAVEFORMS
I-
INPUT
I
9~W---------
i ~~
1O";~;I!!I
___
~"
1
1 ns
td-t---J
~
10%
NOTES:
OV
1
t,~
ir
tf~~_ _ _ __
!
~.,..:
3V
, ;;; 1 ns+------1
_ _ _ _ _~l----t-tr
OUTPUT
-I
0.3M'
I
~5M9~
_____
""'~ 1~
A. The pulse generator has the following characteristics:
B. CL includes probe and jig capacitance.
Fig. 13
7-27
duty cycle'::;;; 1%, Zout ~ 50
n.
FAIRCHILD • 554508/754508 SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
AC CHARACTERISTICS
SWITCHING TIMES OF COMPLETE DRIVERS
TESTCIRCUIT
INPUT
2.4 V
lOV
9
fI
RL
=
50
1554508
754508
754518
754528
PULSE
GENERATOR
(See Note A)
~
1754538
754548
6
I
n
~
OUTPUT
CI RCUIT
UNDER
TEST
(See Note B)
GND
CL=15pF
I
SU8
I
-::-
-.l
-::-
-::-
1""'="
-::-
0.4 V
VOL TAGE WAVEFORMS
INPUT
554508
754508
754518
754538
INPUT
754528
754548
OUTPUT
NOTES:
A. The pulse generator has the following characters: PAR = 1 MHz, Zout "" 500 fl.
8. When testing 5545081754508, connect output Y to transistor base and ground the substrate terminal.
C. CL includes probe and jig capacitance.
Fig. 14
7-28
FAIRCHILD • 55450B/75450B SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
AC CHARACTERISTICS
LATCH-UP TEST OF COMPLETE DRIVERS
TEST CI RCUIT
Vee'" 20 V
24V
INPUT
5V
1
551754508
551754518
551754528
L--+-...,..-o
OUTPUT
PULSE
GENERATOR
(See Note A)
CL=15pF
(See Note C)
551754538
551754548
T~
I
OA V
VOLTAGE WAVEFORMS
--1
O%
I
~
i 1\1_';.;;0~%;....
15 V
INPUT
55/754508
55/75451 B
551754538
t"--":Sns
J
I
__________
55/754526
55/754546
:
~10;.O.;;.J'ol
:- -
40)Js ------~•..,I
---l
5n,
I
1.5V
15V
10 %
NOTES:
-- -
1--'
-
-
- - - 0V
lOn,
I
~'.;.O.;%
\~
OUTPU f
3V
90%~:-:--------3V
I :90%
INPUT
I
090%
I
15 V
I
I.
- - l I t--'
~.;;; lOns
---,
I
I
_____ 0 V
___r:::
A. The pulse generator has the following characteristics:
PRR ~ 12.5 kHz, Zout ~ 50 n.
B. When testing 55450 or 75450, connect output Y to
transistor base with a 500-n resistor from there to
ground, and ground the substrate terminal.
C. CL includes probe and jig capacitance.
Fig. 15
7-29
FAIRCHILD • 554508/754508 SERIES
TYPICAL PERFORMANCE CURVES FOR 754508 SERIES
55450B/75450B TTL GATE
HIGH-LEVEL OUTPUT
VOL TAGE AS A FUNCTION
OF HIGH-LEVEL OUTPUT
CURRENT
55450B/75450B TRANSISTOR
STATIC FORWARD CURRENT
TRANSFER RATIO AS A
FUNCTION OF
COLLECTOR CURRENT
0
5
-2:~~tf,,~r
m
5
01'...
'"
5
0
5
08 V
0
TA=
5~
25
30
35
- 40
0
2
I I
I
I
I
5
1
~;10
o
SEE NOH 17
'C
-
'e
'e
3--::;:;--: Vt::;
_TA~'_5506
;,
-
I
TRANSISTOR COLLECTOREMITTER SATURATION
VOL TAGE AS A FUNCTION OF
COLLECTOR CURRENT
55450B/75450B TRANSISTOR
BASE-EMITTER VOL TAGE
AS A FUNCTION OF
COLLECTOR CURRENT
5
~
I I
5
0
e
I
0
1\
5
.-
I
l;:s.---
o
\
5~~i,-O~::'
I
H-f-- r-
5~_
1\
0
9
I
Jsoc
-
-
I
10
,
125°C
700~
70°C
25"C
~
SEE NOTE 17
5
3
1; 12S"C
250C~
T
2
2
~
~
I.e:ii~r;;
3
~
-S5 'C
1
.1
1
0
0
to
20
"
70
100
200
'00
NOTE 17: These parameters must be measured using pulse techniques. tw = 300 J..LS, duty cycle" 2%.
7-30
55/75460 • 55/75461 • 55/75462
55/75463 • 55/75464
DUAL HIGH VOLTAGE HIGH CURRENT PERIPHERAL DRIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The 55/75460 Peripheral Driver Series converts TTL and DTL logic levels to HIGH voltage, HIGH current levels. The
55/75460 Series is directly interchangeable with the 55/75450 Series and affords higher breakdown at the expense of speed.The 55/75460 Series features
two 54/74 TTL input gates and two HIGH voltage HIGH current npn uncommitted transistors.
The 55/75461, 55/75462, 55/75463 and 55/75464 feature two standard 54/74 TTL input gates in AND, NAND, OR and NOR configurations, respec·
tively. The logic gates are internally connected
•
•
•
•
•
•
tQ
the bases of the npn transistors.
NO OUTPUT LATCH·UP AT 30 V
MEDIUM SWITCHING SPEED
300 rnA OUTPUT CURRENT CAPABILITY
TTL OR DTL INPUT COMPATIBILITY
INPUT CLAMP DIODES
+5VSUPPLYVOLTAGE
I
TEST TABLE 1 - Operating Temperature Range and Supply Voltage Range
75460 Series
55460 Series
Temperature, T A
Supply Voltage, V CC
-55°C to +125°C
0°Cto70°C
+4.5 V to +5.5 V
+4.75 V to +5.25 V
ABSOLUTE MAXIMUM RATINGS
55460
Supply Voltage, VCC (Note 1)
Input Voltage (Note 1)
Interemitter Voltage (Note 2)
V CC to Substrate Voltage (Note 6)
Collector to Substrate Voltage (Note 6)
Collector to Base Voltage
Collector to Emitter Voltage (Note 3)
Emitter to Base Voltage
Output Voltage (Notes 1 and 4)
Continuous Collector Current (Note 5)
Continuous Output Current (Note 5)
Continuous Total Power Dissipation (Note 7)
Operating Ambient Temperature Range
Storage Temperature Range
Pin Temperature
Molded DIP (Soldering, 10 s)
Hermetic DIP (Soldering, 30 s)
55461
55462
55463
55464
75460
7V
5.5
5.5
40
40
40
40
V
V
V
V
V
V
5V
75461
75462
75463
75464
7V
7V
7V
5.5 V
5.5 V
40 V
40 V
40 V
40 V
5V
5.5 V
5.5 V
5.5 V
5.5 V
35 V
35 V
300 rnA
300 rnA
800mW
-55°C to +125°C
-65°C to +150°C
800 mW
O°C to 700 e
-65'C to +150°C
300 mA
800 mW
_55°C to +125°C
-65°C to +150°C
300 0 e
260°C
3000 e
260°C
300°C
300 rnA
800mW
O°C to 70°C
_65°C to +150o e
NOTES:
1. Voltage values are with respect to network ground terminal unless otherwise specified.
2. This is the voltage between two emitters of a multiple-emitter input transistor.
3. This value applies when the base-emitter resistance (RBE) is equal to or less than 500
4. This is the maximum voltage which should be applied to any output when it is in the off state.
5. Both halves of these dual curcuits may conduct rated current simultaneously.
6. For the 55460 and 75460 only, the substrate (Pin 8), must always be at the most negative device voltage for proper operation.
7. Above 70°C ambient temperature, derate linearly at 8.3 mW/oC for hermetic DIP.
For plastic Mini DIP and hermetic Mini DIP derate above 30°C at 6.7 mW/C.
n.
7-31
260°C
3000 e
FAIRCHILD • 55460/75460 SERIES
55460/75460
DUAL POSITIVE AND PERIPHERAL DRIVER
EQUIVALENT CIRCUIT
CONNECTION DIAGRAM
14-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES SA 9A
PACKAGE CODES D
P
r-------~------~--~-------ovcc
GATE
IN A
IN B
1E
OUT A
INA
OUT B
IN B
1C
SUB
2B
lC
2C
lE
2E
G
GND
SUB
LOGIC FUNCTION
Positive I..ogic:
2C
IN B o--+-+--+
Z = XV (gate only)
Z = XV (gate and transistor)
ORDER INFORMATION
2E
~-+-+-----~-~-~------oGND
All resistor values in ohms.
TYPE
PART NO.
55460
75460
75460
55460DM
75460DC
75460PC
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range. use Test Table 1. pg. 1.
unless otherwise indicated
TTL Gates
SYMBOL
TEST
FIGURE
CHARACTER ISTICS
CONDITIONS
VIH
Input HIGH Voltage
1
Vil
Input lOW Voltage
2
VCD
Input Clamp Diode Voltage
3
VCC
VCC =MIN. V il
10H =-400!-'A
VOH
Output HIGH Voltage
2
VOL
Output lOW Voltage
1
II
Input Current at Maximum
Input Voltage
IIH
Input HIGH Current
III
Input lOW Current
lOS
Short Circuit Output Current (Note 9)
ICCH
Supply Current. Output HIGH
'CCl
Supply Current. Output lOW
Input A. B
Gate
Input A. B
Gate
Input A. B
VCC
=MIN.
=MIN.
=-12 mA
=0.8 V
VIH
MAX
V
-1.2
2.4
V
-1.5
V
3.3
V
55460
0.25
0.5
I
75460
0.25
0.4
1
2
=MAX. VI = 5.5 V
4
VCC = MAX. VI = 2.4 V
3
VCC = MAX. VI = 0.4 V
5
VCC = MAX
UNITS
0.8
=2 V I
10l = 16 mA
40
80
V
mA
!-'A
-1.S
-3.2
rnA
-35
-55
mA
VCC = MAX. VI = 0 V
2.8
4
VCC = MAX. VI = 5 V
7
11
NOTES:
8. All typical values at VCC 5 V. TA 25°C.
9. Not more than one output should be shorted at a time.
=
II
VCC
S
TYP
(Note 8)
2
4
Gate
MIN
=
7-32
-18
mA
FAIRCHILD • 55460/75460 SERIES
55460/75460
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use
Test Table 1, pg. 1, unless otherwise indicated
Output Transistors
SYMBOL
CHARACTER ISTICS
MIN
CONDITIONS
TYP
(Note 10)
MAX
UNITS
V(BR)CBO
Collector to Base Breakdown Voltage
IC = 1001lA, IE = 0
40
V
V(BR)CER
Collector to Emitter Breakdown Voltage
IC = 100 IlA, RBE = 500 n
40
V
V(BR)EBO
Emitter to Base Breakdown Voltage
IE = 100 IlA, IC = 0
5
V
Static Forward Current Transfer Ratio
(Note 11)
VCE = 3 V, IC = 100 mA, TA = 25°C
VCE = 3 V, IC = 300 mA. TA = 25°C
VCE = 3 V,
55460 T A=-55'C
75460 TA=O'C
IC = 100 mA
hFE
V CE -3V,
55460
75460
IC = 300 mA
VBE(sat)
VCE(sat)
Base to Emitter Voltage (Note 11)
Collector to Emitter Saturation Voltage
(Note 11)
30
T A~-55'C
10
20
15
T A=O°C
25
75460
0.85
0.85
55460
1.0
75460
55460
75460
55460
1.0
0.25
0.25
55460
IB = 10mA.
IC=100mA
IB - 30 mA,
IC
IB
IC
IB
IC
25
= 300 mA
-10mA.
= 100 mA
= 30 mA.
= 300 mA
0.45
75460
0.45
1.2
V
1.0
1.4
1.2
V
V
V
0.5
0.4
0.8
0.7
V
V
V
V
I
NOTES:
10. All typical values are at Vee = 5 V. TA = 25°C.
11 These parameters must be measured using the pulse techniques. tw = 300 J.LS, duty cycle ~ 2%.
AC CHARACTERISTICS: VCC = 5 V, T A = 25'C
TTL Gates
CHARACTERISTICS
SYMBOL
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
TEST
FIGURE
12
CONDITIONS
MIN
CL = 15 pF, RL = 400 n
TYP
MAX
UNITS
22
ns
8
ns
Output Transistors
CHARACTERISTICS
SYMBOL
td
Delay Time
tr
Rise Time
ts
Storage Time
tf
Fall Time
TEST
FIGURE
13
CONDITIONS
(Note 12)
MIN
TYP
MAX
UNITS
IC = 200 mA, VBE(off) = -1 V
10
ns
IB(1) = 20 mA, IB(2) = -40 mA
16
ns
CL = 15 pF, RL = 50 n
23
ns
14
ns
Gates and Transistors Combined
SYMBOL
CHARACTERISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
TEST
FIGURE
CONDITIONS
MIN
MAX
45
65
ns
IC = 200 mA, CL = 15 pF,
35
50
ns
RL = 50n
10
20
ns
10
20
ns
14
VS=30V, IC~300mA
RBE = 500n
15
NOTE 12. Voltage and current values shown are nominal; exact values vary slightly with transistor parameters.
7-33
UNITS
TYP
Vs -10
mV
FAIRCHILD • 55460/75460 SERIES
55461/75461
DUAL POSITIVE AND PERIPHERAL DRIVER
EQUIVALENT CIRCUIT (Each Driver)
CONNECTION DIAGRAM
8-PIN DIP
(TOP VIEW)
PACKAGE OUTLINE
9T 6T
PACKAGE CODE
T R
Vee
1.6 k
4k
130
~
::!:~
71'<-
( 1
INPUTS
OUTPUT
INAl
......
IN A2
\2
*
-:;.
~
2
:;J
OUTA
~
4
1k
500
IN B2
6
~
GND [
Vee
7
3
-----K
i
'M'
c;::
c;
INBl
5
WOUTB
GND
Component val ues shown are nom ina!.
All resistor values in ohms.
ORDER INFORMATION
TRUTH TABLE
INPUT
OUTPUT
1
2
L
L
L
H
L
H
H
L
L
L
H
H = HIGH Level, L
H
=
TYPE
PART NO.
55461
75461
75461
55461RM
75461 RC
75461TC
Positjve Logic:
Z
=
XY
LOW Level
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated.
SYMBOL
CHARACTERISTICS
TEST
CONDITIONS
FIGURE
V IH
Input HIGH Voltage
7
V IL
Input lOW Voltage
7
V CD
Input Clamp Diode Voltage
8
Vec
7
Vee ~ MIN, VOH ~ 35 V
V IH ~ 2 V
10H
VOL
Output HIGH Current
Output lOW Voltage
MIN
TYP
(Note 13)
MAX
V
2
7
~
MIN, II
~ ~12
mA
-1.2
0.8
V
-1.5
V
55461
300
75461
100
Vee ~ MIN, Vil ~ 0.8 V
55461
.16
0.5
10L ~ 100 mA
75461
.16
0.4
55461
.35
0.8
75461
.35
0.7
VCC
~
MIN, V il
~
0.8 V
10l ~ 300 mA
~
~
UNITS
IJA
V
II
Input Current at Maximum Input Voltage
9
VCC
5.5 V
1.0
IIH
Input HIGH Current
9
VCC ~ MAX, VI ~ 2.4 V
40
IJA
IlL
Input lOW Current
8
Vce ~ MAX, VI ~ 0.4 V
~1.0
-1.6
mA
ICCH
Supply Current, Output HIGH
VCC ~ MAX, VI ~ 5V
8.0
11
mA
ICCl
Supply Current Output LOW
av
61
76
mA
NOTE 13. All typical values are at
Vee:::;
10
MAX, VI
V CC ~ MAX, VI ~
mA
5 V, TA ::: 25°C.
AC CHARACTERISTICS: V ec ~ 5 V, T A ~ 25°C
SYMBOL
CHARACTERISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
tTlH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VOH
HIGH level Output Voltage After Switching
TEST
CONDITIONS
FIGURE
MIN
10 '" 200 mA. CL ~ 15 pF,
14
RL
15
~
50
J].
Vs ~ 30 V, 10'" 300 mA
7-34
Vs -10:
TYP
MAX
UNITS
45
55
ns
30
40
ns
8
20
ns
10
20
ns
mV
FAIRCHILD • 55460/75460 SERIES
55462/75462
DUAL POSITIVE NAND PERIPHERAL DRIVER
CONNECTION DIAGRAM
a·PIN DIP
(TOP VIEwl
PACKAGE OUTLINE 9T 6T
PACKAGE CODE T
R
EQUIVALENT CIRCUIT (Each Driver)
r-----~----------~--~~------ovcc
4k
1.6 k
130
1.6 k
f lo-_-.T
Vcc
IN Al
INPUTS
~2o--+-~
IN A2
IN 62
OUT A
IN 61
OUT B
GNO
1k
500
1k
~---+-------+----~----~----+-~--~-oGND
Component values shown are nominal.
All resistor values in ohms.
ORDER INFORMATION
TRUTH TABLE
INPUT
2
L
L
L
H
H
H
L
H
H
H
H
L
PART NO.
7562RM
75462RC
75462TC
TYPE
55462
75462
75462
OUTPUT
(off state I
loff state I
(off state)
(on state)
Positive Logic:
2"" XY
H "" HIGH Level, L '" LOW Level.
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range use Test Table 1, pg. 1,
unless otherwise indicated
SYMBOL
TEST
CHARACTERISTICS
V IH
Input HIGH Voltage
7
V IL
Input LOW Voltage
7
VCD
Input Clamp Diode Voltage
8
VCC
7
VCC ~ MIN, VOH ~ 35 V
V IL ~ 0.8 V
IOH
Output HIGH Current
MIN
CONDITIONS
FIGURE
TYP
(Note 141
MAX
V
2
~
MIN, II
~
-12 mA
~ MIN, V IH
IOL ~ 100 mA
~
VCC - MIN, V IH
10L ~ 300 mA
~
VCC
-1.2
2V
UNITS
0.8
V
-1.5
V
55462
300
75462
100
55462
.16
0.5
75462
,16
0.4
55462
.35
,35
0.8
).I.A
VOL
Output LOW Voltage
7
II
Input Current at Maximum Input Voltage
9
VCC ~ MAX, VI ~ 5.5 V
1.0
IIH
Input HIGH Current
9
VCC ~ MAX, VI ~ 2.4 V
40
).I.A
IlL
Input LOW Current
8
VCC ~ MAX, VI ~ 0.4 V
-1.6
mA
ICCH
Supply Current, Output HIGH
ICCL
Supply Current Output LOW
10
NOTE 14. All typical values are at Vee
~
5 V, TA
~
2V
75462
V
0.7
-1.0
mA
aV
13
17
mA
VCC ~ MAX, VI ~ 5 V
65
76
mA
VCC ~ MAX, VI ~
25°e.
AC CHARACTERISTICS: VCC ~ 5 V, T A ~ 25°C
SYMBOL
CHARACTERISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VO H
HIGH Level Output Voltage After Switching
TEST
CONDITIONS
FIGURE
10 '" 200 mA, C L
14
RL
=15 pF,
=50n
Vs ~ 30 V, 10"" 300 rnA
15
7-35
MIN
Vs -10
TYP
MAX
UNITS
ns
50
65
40
50
ns
12
25
ns
15
20
ns
mV
I
FAIRCHILD • 55460/75460 SERIES
55463/75463
DUAL POSITIVE OR PERIPHERAL DRIVER
EaUIVALENT CIRCUIT (Each Driver)
CONNECTION DIAGRAM
r-------,--------,----~r_-------ovcc
( 1 <>--1'-----'
8-PIN DIP
(TOP VIEW)
PACKAGE OUTLINE, 9T 6T
PACKAGE CODE T R
INA1
INPUTS
INA2
l2o--f-----,-------1f--------'
OUTA
GNO
500
1k
~-----+------~------------~--~--~~GND
Component values shown are nominal.
All resistor values in ohms.
TRUTH TABLE
INPUT
ORDER INFORMATION
TYPE
55463
75463
75463
OUTPUT
1
2
L
L
H
H
L
H
L
H
(on state)
(off state)
(off state)
(off'state)
L
H
H
H
H ;:: HIGH Level, L
= LOW
PART NO.
55463RM
75463RC
75463TC
Positive Logic: Z
=X +Y
Level
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated
SYMBOL
CHARACTERISTICS
TEST
FIGURE
CONDITIONS
VIH
Input HIGH Voltage
7
VIL
Input LOW Voltage
7
VCD
Input Clamp Diode Voltage
8
VCC = MIN, I, = -12 mA
7
VCC = MIN, V OH = 35 V
V IH = 2 V
10H
Output HIGH Current
MIN
TYP
(Note 15)
MAX UNITS
V
2
VCC = MIN, V IL = 0.8 V
10L = 100 mA
VCC = MIN, V ,L - 0.8 V
-1.2
55463
75463
0.18
55463
75463
0.8
V
-1.5
V
300
100
/J A
0.5
0.4
0.8
O.lB
0.39
0.39
VOL
Output LOW Voltage
7
'I
Input Current at Maximum Input Voltage
9
VCC = MAX, VI = 5.5 V
1.0
"H
Input HIGH Current
9
VCC = MAX, VI = 2.4 V
40
/JA
I,L
Input LOW Current
8
VCC = MAX, VI = 0.4 V
-1.6
mA
'CCH
Supply Current Output HIGH
ICCL
Supply Current Output LOW
10L = 300 mA
NOTE 15. Aillypical values are at Vee
11
55463
75463
V
0.7
-1.0
mA
VCC = MAX, VI = 5 V
8.0
11
mA
VCC = MAX, V, = 0 V
63
76
mA
=5 V. TA =25°e.
ACCHARACTERISTICS: VCC = 5 V, T A = 25°C
SYMBOL
CHARACTERISTICS
tpLH
Propagation Delay Time, Output LOW to HIGf;I
tpHL
Propagation Delay Time, Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VO H
HIGH Level Output Voltage After Switching
TEST
FIGURE
CONDITIONS
MIN
10'" 200 mA. CL = 15 pF,
14
RL = 50n
15
Vs = 30 V, '0 '" 300 mA
7-36
Vs -10
TYP
MAX UNITS
45
55
ns
30
40
ns
8
25
ns
10
25
ns
mV
FAIRCHILD • 55460/75460 SERIES
55464/75464
DUAL POSITIVE NOR PERIPHERAL DRIVER
EQUIVALENT CIRCUIT (Each Driver)
CONNECTION DIAGRAM
r-------~------~----~--~--~-------ovcc
4k
2k
4k
2k
1.6k
130
(1o--~J
8-PIN DIP
(TOP VIEWI
PACKAGE OUTLINE
PACKAGE CODE
9T 6T
T R
IN Al
Vee
INA2
IN 82
INPUTS
l2o--~--~--+-----~
OUT A
IN 61
OUT 8
GND
500
1k
1k
GND
All resistor values in ohms.
ORDER INFORMATION
TRUTH TABLE
OUTPUT
INPUT
2
L
L
H
L
H
L
H
H
H
=;;
HIGH Level, L
=
H
loff state I
L
L
L
(on state)
(on statel
TYPE
PART NO.
55464
75464
75464
55464RM
75464RC
75464TC
(on state)
Positive Logic:
Z~X+Y
LOW Level
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Vollage Range, use Test Table 1, pg. 1,
unless olherwise indicated
SYMBOL
CHARACTERISTICS
TEST
CONDITIONS
FIGURE
Input HIGH Voltage
7
V il
Input lOW Voltage
7
V CD
Input Clamp Diode Voltage
8
VCC = MIN, II = -12 mA
7
VCC = MIN, VO H = 35 V
V il = 0.8 V
VIH
MIN
TYP
(Note 161
MAX
UNIT S
V
2
0.8
V
-1.5
V
55464
300
75464
100
p.A
10H
Output HIGH Current
VOL
Output lOW Voltage
II
Input Current at Maximum Input Voltage
9
VCC = MAX, VI = 5.5 V
1.0
IIH
Input HIGH Current
9
VCC = MAX. VI = 2.4 V
40
p.A
IlL
Input LOW Currenl
8
VCC = MAX. VI = 0.4 V
-1.6
mA
ICCH
Supply Current Output HIGH
ICCl
Supply Current Output LOW
7
11
VCC = MIN, V IH = 2 V
55464
0.17
0.5
10l = 100 mA
75464
0.17
0.4
VCC - MIN, V IH - 2 V
55464
0.38
10l = 300 mA
75464
0.38
0.8
0.7
-1.0
V
mA
VCC = MAX, VI = 0 V
14
19
mA
VCC = MAX. VI = 5V
72
85
mA
NOTE 16. All typical values are at VCC = 5 V, TA = 25'C.
AC CHARACTERISTICS: VCC = 5 V, TA ~ 25'C
SYMBOL
CHARACTERISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHl
Propagation Delay Time, Output HIGH to lOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VOH
HIGH level Output Voltage After Switching
TEST
FIGURE
CONDITIONS
MIN
10 "" 200 mA CL = 15 pF,
14
RL = 50
15
n
Vs = 30 V, 10 "" 300 mA
7-37
Vs -10
TYP
MAX
UNITS
50
65
ns
40
50
ns
12
20
ns
15
20
ns
mV
•
FAIRCHILD • 55460/75460 SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
DC TEST CIRCUITt
'cc
'IH
C>--I-r")c>-----.~::::::,
'" c>--'::=Lj>-,-==,
t
J
Both inputs are tested simultaneously.
NOTES:
Each input is tested separately.
Fig. 1
A. Each input is tested separately.
B. When t9sting V CD. input not under test
Fig.2
is open.
Fig. 3
ICCH.ICCl
" 0------1,'\
'I o--.-----r-'\
OPEN
Each input is tested separately
Each gate is tested separately.
155460/75460 only)
Fig.4
Both gates are tested simultaneously.
Fig. 6
Fig. 5
'cc
TEST TABLE II
INPUT
UNDER
TEST
OTHER
INPUT
V'H
VIL
55/75462
V'H
V'l
55/75463
V'H
V'l
V'H
V'l
CIRCUIT
55/75461
TEST
TABLE
'''n'OH 'OH
: , \ I OL
I1
55/75464
OUTPUT
APPLY
MEASURE
V'H
Vee
VOH
'OH
VOL
V,H
VOL
Vee
'Ol
VOH
GNO
VOH
V'l
'Ol
'OH
VOL
GNO
'Ol
VOH
V'l
'Ol
'OH
Val
'OH
A. Each input is tested separately.
B. When testing IlL 55/75463 and
55/75464, the input not under test
is grounded. For all other circuits
it is at 4.5V.
C. When testing VCD, input not under test
is open.
NOTE: Each input is tested separately.
Fig.7
Fig. 8
ICCH.ICCl
FOR AND. NAND CIRCUITS
'cc
"0---'-""1
OPEN
Each input is tested separately.
Fig. 9
'Io--.-4-.r.....
Both gates are tested simultaneously.
Fig. 10
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
7-38
ICCH.ICCl
FOR OR. NOR CIRCUITS
'cc
'I C>-----I-r'
Both gates are tested simultaneously.
Fig. 11
FAIRCHILD • 55460/75460 SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
SWITCHING CHARACTERISTICS
PROPAGATION DELAY TIMES, EACH GATE
(55460,75460 ONLY)
TEST CIRCUIT
INPUT 2.4 V
Vee
OUTPUT
VOLTAGE WAVEFORMS
5V
\--O(5ns
INPUT - - - - - , .
3V
OV
OUTPUT - -_ _ _.....
NOTES:
A. The pulse generator has the following characteristics:
PRR"" 1 MHz, Zout ~ 50 n.
B. CL include probe and jig capacitance.
C. All diodes are FD777.
Fig. 12
•
SWITCHING TIMES, EACH TRANSISTOR
(55460,75460 ON L Y)
TEST CIRCUIT
-,v
INPUT
VOLTAGE WAVEFORMS
,OV
1 kS1
1 -03 ""--1
Rl" 50
n
....- .....--1~-C
0.1 IJF
62
I
~5M90%
INPUT _ _ _'_O'OiIt/
i ~O%
i
t---+---.;:; 5
OUTPUT
I
90%~W---------
ns
I
50n
OUTPUT
n
A. The pulse generator has the following characteristics:
duty cycle ~ 1 %, Zout ;::,0 50 n.
B. CL includes probe and jig capacitance.
Fig. 13
7-39
~
I
td-J----I
l---j-t,
-------'O~,~ ~
9~
NOTES:
.;; 5 ns
t"~
tf~
} ~~W-%-------
~
3V
OV
FAIRCHILD • 55460/75460 SERIES
SWITCHING TIMES OF COMPLETE DRIVERS
VOLTAGE WAVEFORMS
TEST CIRCUIT
INPUT
,ov
2.4 V
t- ,e,
-1
I
INPUT
I
~;0".
55/75460
55/75461
55175463
--j
~:~ _____
u:~'
05
I'
I t-- "e,
,,,,I
55/75462
55175464
~lPHL
I
I
--j
NOTES:
tpLH
-~
0.4 V
OV
~"10ns
3V
~~:-----
I':V
OUTPUT
3V
I
J.iS
--j I
~-
INPUT
I
,O"}
'''I
OUTPUT
t-- '" 10m
--j
I
OV
-I
I'
if
Hl"
''''
~ITHL
--j
I
+---
VOH
VOL
~lTLH
A. The pulse generator has the following characteristics:
PRR ~ 1 MHz, Zout '" 50
n.
8. When testing 55460175460, connect output V to
transistor base and ground the substrate terminal
C. CL includes probe and jig capacitance.
Fig. 14
LATCH-UP TEST OF COMPLETE DRIVERS
TEST CIRCUIT
VOLTAGE WAVEFORMS
VCC=30V
INPUT
2.4 V
----i
5V
NPUT
55/75460
55/75461
55/75463
1:
55175460
55/75461
55/75462
I-
1"'-
I
.,:0
30
0
25
:;
'"
>
20
~
~
0
I
I
15
r
_.-
o
~
\
05
100
r-"
,.-
b....
...
-15
::2
~
50
u
:~
-20
75
~
--
~
25
I
w
1\
-10
f-- r-
i3
>
~5
TA=JsoC :--
-:::::r-
125
z
~
-25
o
-30
-35
~I
10
-40
VeE =3.0V
SEE NOTE 17
I
150
~
-
1\\
10
o
175
z
~
I
0
o
c::
5;"'9",,2
I
'"I
~
5V
20
40
70
100
200
500
Ie - COLLECTOR CURRENT - rnA
IOH - OUTPUT HIGH CURRENT - rnA
I
55460/75460 TRANSISTOR
BASE-EMITTER VOLTAGE
AS A FUNCTION OF
COLLECTOR CURRENT
TRANSISTOR COLLECTOREMITTER SATURATION
VOLTAGE AS A FUNCTION OF
COLLECTOR CURRENT
1.2
6
~
1.1
>
I
.,"
1.0
0.8
>
0.7
~
0.6
~
0.5
W
~
I
w
>fn
-<'
o'e
Noh 17
I_ r-"
_
TA =_55°(;
--
'B
....-
--:. l-
10
--=s:: ~
5 -SEE NO'TE 17
:---
4
~V
--:: --r r-
~
w
Ie
'" 10
SEE
_
~
o
'B
125°C
700~~
70"C
3
2Soc
250e~
TA=125°C
2
0.4
~
~
0.3
o. 2
~
_55°C
O. 1
0.1
o
10
20
40
70
100
Ie - COLLECTOR CURRENT -
200
0
400
20
10
40
70
100
200
Ie - COLLECTOR CURRENT -
rnA
NOTE 17. These parameters must be measured using pulse techniques. tw
7-41
=
300 J.,Ls, duty cycle";;;; 2%.
rnA
400
55/75471-55/75472·55/75473-55/75474
DUAL HIGH VOLTAGE HIGH CURRENT PERIPHERAL DRIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The 55/75471 series are dual very high voltage interface peripheral drivers with medium switching speeds. These devices
are pin-far-pin replacements of the (55/75451A-55/75454A), (55/75461-55/75464) and the (OS3611-0S3614) peripheral drivers.
The 55/75471 peripheral driver series converts TTL and OTL logic levels to high voltage, high current levels.
The 55/75471,55/75472,55/75473 and 55/75474 feature two standard TTL input gates in AND, NAND, OR and NOR configurations respectively.
The logic gates are internally connected to the bases of the npn transistors.
The 55/75471 series offers flexibility in designing very high voltage logic buffers, power drivers, lamp drivers, line drivers and relay drivers.
•
•
•
•
•
•
•
HIGH VOLTAGE OUTPUT (80 V)
NO LATCH·UP AT 55 V
HIGH SPEED SWITCHING
HIGH OUTPUT CURRENT CAPABILITY
TTL OR DTL INPUT COMPATIBILITY
INPUT CLAMP DIODES
+5VSUPPLYVDLTAGE
TEST TABLE 1 - Operating Temperature Range and Supply Voltage Range
55471 Series
Temperature, T A
75471 Series
_55' C to +125' C
O'Cto70'C
+4.5 V to +5.5 V
+4.75 V to +5.25 V
Supply Voltage, VCC
ABSOLUTE MAXIMUM RATINGS
55471
55472
55473
55474
Supply Voltage, VCC (See Note 1)
Input Voltage (See Note 1)
Interemitter Voltage (See Note 2)
Output Voltage (See Notes 1 and 3)
Continuous Collector Current (See Note 4)
Continuous Output Current (See Note 4)
Continuous Total Power Dissipation (See Note 5)
Operating Free~Air Temperature Range
Storage Temperature Range
Pin Temperature
Molded DIP (Soldering, 10 s)
Hermetic DIP (Soldering, 60 s)
75471
74572
75473
75474
7.0
5.5
5.5
80
V
V
V
V
7.0
5.5
5.5
80
V
V
V
V
300 mA
800mW
-55'C to +125'C
_65 0 C to +150' C
300mA
800mW
DoC to 70' C
-65' C to +150° C
260'C
300'C
260'C
300'C
NOTES:
1. Voltage values are with respect to network ground terminal unless otherwise specified.
2. This is the voltage between two emitters of a mUltiple-emitter input transistor.
3. This is the maximum voltage which should be applied to any output when it is in the off state.
4. Both halves of these dual circuits may conduct rated current simultaneously.
5. Above 60°C ambient teJYlperature, c;erate linearly at 8.3 mW/C for Hermetic DIP and Molded DIP. For the Molded Mini DIP and Hermetic Mini
DIP, derate at 6.7 mWI C above 30 C.
7-42
FAIRCHILD • 55471/75471 SERIES
55471/75471
DUAL POSITIVE AND PERIPHERAL DRIVER
CONNECTION DIAGRAMS
B·PIN DIP
(TOP VIEWI
PACKAGE OUTLINE 9T 6T
PACKAGE CODE T
R
EQUIVALENT CIRCUIT (Each Driver)
vee
1.6 k
4'
130
r----K
\ T
,
"*
OUTPUT
T~B
jvcc
*
7.
INPUTS
INA1[~
:::!~
3
OUTA[?J
500
1k
'r-
'S(;
INA2C
~
L
GNOc
7
jlNB2
~6jlNBT
(
:JOUTB
GNO
~
Component values shown are nominal. All resistor values in ohms.
TRUTH TABLE
INPUTS
1
H
2
L
L
L
H
H
H
H
=:
ORDER INFORMATION
PART NO.
TYPE
55471RM
55471
75471 RC
75471
75471
75471TC
OUTPUT
L
HIGH Level, L
=
(on statel
L
L
(on state)
L
H
(on statel
(off statel
Positive Logic: Z
=
XV
LOW Level
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated
SYMBOL
TEST
CHARACTERISTICS
V IH
Input HIGH Voltage
1
V IL
Input LOW Voltage
1
VCD
Input Clamp Diode Voltage
2
10H
VOL
Output HIGH Current
V
0.8
V
-1.5
V
VCC = MIN, V OH ~ 80 V
55471
300
V IH = 2 V
75471
100
VCC = MIN, V IL = 0.8 V
10L = 100 mA
55471
0.16
0.5
75471
0.16
0.4
VCC = MIN, V IL - 0.8 V
55471
0.35
0.8
10L = 300 mA
75471
0.35
0.7
/-LA
V
1.0
VCC = MAX, VI = 2.4 V
40
/-LA
2
VCC = MAX, VI = 0.4 V
-1.0
-1.6
mA
VCC = MAX, VI = 5 V
8.0
11
mA
aV
61
76
mA
IIH
Input HIGH Current
IlL
Input LOW Current
ICCH
Supply Current, Output HIGH
4
Supply Current Output LOW
VCC = MAX, VI =
v,
UNITS
3
3
= 5
MAX
VCC = MAX, VI = 5.5 V
Input Current at Maximum Input Voltage
NOTE 6. All typical values are at Vee
TYP
(Note 61
-1.2
VCC = MIN, II = -12 mA
1
Output LOW Voltage
MIN
2.0
1
II
ICCL
CONDITIONS
FIGURE
mA
T A = 25 C.
D
AC CHARACTERISTICS: VCC ~ 5 V, TA ~ 25'C
SYMBOL
CHARACTER I STI CS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
tTLH
Transition Ti.me, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
TEST
CONDITIONS
FIGURE
MIN
10 '" 200 mA, CL = 15 pF,
6
RL = 50
7
Vs
7-43
~
n
55 V, 10'" 300 rnA
Vs -18
TYP
MAX
UNITS
30
55
ns
25
40
ns
8.0
20
ns
10
20
ns
mV
•
FAIRCHILD· 55471/75471 SERIES
55472/75472
DUAL POSITIVE NAND PERIPHERAL DRIVER
EQUIVALENT CIRCUIT (Each Drived
CONNECTION DIAGRAMS
B-PIN DIP
(TOP VIEW)
PACKAGE OUTLINE 9T
PACKAGE CODE T
vee
1.6 k
4'
~
T,
INPUTS
I'
-t:::
OUTPUT
-
------K
"'c~
""~
--------K
DUTAC
2~
IJ'"
f~""'
PINBl
4
1k
1k
6T
R
1~8
~t.
------K
2
::2~
130
1.6 k
5
GND[
500
POUTS
GND
--:
Component values shown are nominal. All resistor values in ohms.
TRUTH TABLE
INPUTS
ORDER INFORMATION
PART NO.
TYPE
55472RM
55472
75472RC
75472
75472TC
75472
OUTPUT
1
2
L
L
H
H
L
H
L
H
(off state)
(off state)
(off state)
(on state)
H
H
H
L
Positive Logic: Z = X Y
H:= HIGH Level, L = LOW Level.
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated
SYMBOL
CHARACTERISTICS
TEST
V IH
Input HIGH Voltage
1
VIL
I nput LOW Voltage
1
VCD
Input Clamp Diode Voltage
2
10H
VOL
CONDITIONS
FIGURE
Output HIGH Current
1
Output LOW Voltage
1
MIN
Input Current at Maximum Input Voltage
IIH
Input HIGH Current
3
IlL
Input LOW Current
2
ICCH
Supply Current, Output HIGH
ICCL
Supply Current Output LOW
NOTE 7. All typical values are at
Vee
3
4
MAX
2.0
= MIN, II =-12 mA
VCC = MIN, VOH ~ 80 V
V IL = 0.8 V
VCC = MIN, V IH = 2 V
10L = 100 mA
UNITS
V
-1.2
VCC
0.8
V
-1.5
V
55472
300
75472
100
55472
0.16
0.5
75472
0.16
0.4
VCC - MIN, V IH - 2 V
55472
0.35
0.8
= 300 mA
= MAX, VI = 5.5 V
VCC = MAX, VI = 2.4 V
VCC =MAX, VI = 0.4 V
VCC =MAX, VI = a V
VCC =MAX, VI = 5 V
75472
0.35
0.7
10L
II
TYP
(Note 7)
1.0
VCC
IlA
V
mA
40
IlA
-1.6
mA
13
17
mA
65
76
mA
-1.0
= 5 V, T A = 25°C
AC CHARACTERISTICS: VCC ~ 5 V, TA ~ 25°C
SYMBOL
CHARACTER ISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
TEST
CONDITIONS
FIGURE
10 '" 200 mA. CL
6
RL
7
= 15 pF,
= 50n
VSS
7-44
MIN
~
55 V, 10 '" 300 mA
Vs -18
TYP
MAX UNITS
ns
45
65
30
50
ns
13
25
ns
10
20
ns
mV
FAIRCHILD· 55471/75471 SERIES
55473/75473
DUAL POSITIVE OR PERIPHERAL·DRIVER
EQUIVALENT CIRCUIT (Each Driver)
CONNECTION DIAGRAMS
a·PIN DIP
(TOP VIEW)
PACKAGE OUTLINE 9T 6T
PACKAGE CODE T
R
vce
4k
1.6 k
4k
i'
0:-
INPUTS
130
I:
l~B
OUTPUT
.. "[~
2::
...-...
2~
-=-
::;is::
f~'"'
GND[
POUTS
4
1
lk
""~
aUTAe
V
ORDER INFORMATION
TYPE
PART NO.
55473
55473RM
75473
75473RC
75473
75473TC
OUTPUT
2
L
L
L
H
L
H
H
H
H == HIGH Level. L
(on state)
(off state)
(off state)
(off state)
L
H
H
H
=
5
GNO
TRUTH TABLE
INPUTS
~INBl
500
Component values shown are nominal. All resistor values in ohms.
1
p'"
Positive Logic: Z
=
X + y
LOW Level
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range, use Test Table 1, pg. 1,
unless otherwise indicated
SYMBOL
TEST
CHARACTER ISTICS
CONDITIONS
FIGURE
.
V IH
Input HIGH Voltage
V IL
Input LOW Voltage
1
VCD
Input Clamp Diode Voltage
2
VCC = MIN, II = -12 mA
1
VCC = MIN, VO H = 80 V
V IH = 2 V
10H
MIN
1
Output HIGH Current
TYP
(Note 8)
MAX
UNITS
V
2.0
-1.2
0.8
V
-1.5
V
55473
300
75473
100
VCC = MIN, V IL = 0.8 V
55473
0.18
0.5
10L = 100 mA
75473
0.18
VCC - MIN, V IL - 0.8 V
10L = 300 mA
55473
75473
0.39
0.39
0.4
0.8
J.LA
VOL
Output LOW Voltage
1
II
Input C'urrent at Maximum Input Voltage
3
VCC = MAX, VI = 5.5 V
1.0
IIH
Input HIGH Current
3
VCC = MAX, VI = 2.4 V
40
J.LA
IlL
Input LOW Current
2
VCC = MAX, VI = 0.4 V
-1.6
mA
ICCH
Supply Current, Output HIGH
ICCL
Supply Current Output LOW
NOTE S. All typical values are at
Vee
=
5
=
0.7
-1.0
mA
VCC = MAX, VI = 5 V
8.0
11
mA
aV
63
76
mA
VCC - MAX, VI 5 V, T A
V
25°V
AC CHARACTERISTICS: VCC = 5 V, TA = 25°C
SYMBOL
CHARACTER ISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time, Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
TEST
CONDITIONS
FIGURE
10
6
~
200 mA, CL = 15 pF,
RL = 50
Vs
7
7-45
MIN
n
= 55V, 10 ~ 300 mA
Vs -18
TYP
MAX UNITS'
30
55
ns
25
40
ns
8
25
ns
10
25
ns
mV
•
FAIRCHILD • 55471/75471 SERIES
55474/75474
DUAL POSITIVE NOR PERIPHERAL DRIVER
EQUIVALENT CIRCUIT (Each Driver)
4"
4"
2"
2"
CONNECTION DIAGRAMS
1.6k
~'30
-K
INPUTS
I
{:
~~
':"
'NA'C~
,"~clJl
~
3
OUTA[ ~
-K
4
,"
1k
:;JVee
~'""
6
~INB'
5
GNO[
I-
::;;s;:
r
'~8
OUTPUT
::s~
H::
a-PIN DIP
(TOP VIEW)
PACKAGE OUTLINE 9T 6T
PACKAGE CODE T
R
vee
POUTB
600
GND
Component values shown are nominal. All resistor values in ohms.
TRUTH TABLE
INPUTS
1
2
L
L
H
H
L
H
L
H
H = HIGH Level, L
ORDER INFORMATION
TYPE
PART NO.
55474
55474RM
75474
75474RC
75474
75474TC
OUTPUT
(off state)
(on state)
(on state)
(on state)
H
L
L
L
=
Positive Logic: Z =
"X'+""V
LOW Level
ELECTRICAL CHARACTERISTICS: Guaranteed over Operating Temperature Range and Supply Voltage Range. use Test Table 1, pg. 1,
unless otherwise indicated
SYMBOL
CHARACTERISTICS
TEST
FIGURE
V IH
Input HIGH Voltage
1
VIL
Input LOW Voltage
1
V CD
Input Clamp Diode Voltage
Output HIGH Current
1
VOL
Output LOW Voltage
1
II
Input Current at Maximum Input Voltage
3
IIH
Input HIGH Current
3
IlL
Input LOW Current
2
ICCH
Supply Current. Output HIGH
ICCL
Supply Current Output LOW
AC CHARACTERISTICS: VCC
SYMBOL
Vee = 5
MIN
TYp.
(Note 9)
MAX UNITS
2.0
=MIN, II =-12 mA
=MIN, VO H = 80 V
VIL =0.8 V
VCC =MIN, VIH =2 V
10L = 100 mA
VCC MIN, V IH =2 V
10L =300 mA
VCC =MAX, VI =5.5 V
VCC =MAX, VI =2.4 V
VCC =MAX, VI =0.4 V
VCC =MAX, VI =a V
2
10H
NOTE 9. All typical values are at
CONDITIONS
V
VCC
55474
VCC
5
75474
0.8
V
-1.5
V
300
100
!lA
.55474
0.17
0.5
75474
0.17
0.4
55474
0.38
0.38
0.8
0.7
75474
1.0
VCC - MAX, VI - 5 V
V
mA
40
jlA
-1.0
-1.6
rnA
14
19
mA
72
85
mA
V, TA = 25°C
= 5 V, T A = 25°C
CHARACTER ISTICS
tpLH
Propagation Delay Time, Output LOW to HIGH
tpHL
Propagation Delay Time. Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time. Output HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
TEST
FIGURE
CONDITIONS
10'" 200 mA, CL
6
RL
7
Vs
7-46
MIN
=15 pF,
=50 n
= 55 V,
10 '" 300 mA
Vs -18
TYP
MAX
UNITS
40
65
ns
30
50
ns
8
20
ns
10
20
ns
mV
FAIRCHILD· 55471/75471 SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
TEST TABLE II
Vee
CIRCUIT
~
A
V ,H
V,L
SEE
TEST
CI RCUIT
UNDER
TABLE
TEST
Y
55/75471
VOH
SEE
INPUT
UNDER
TEST
OTHER
INPUT
vlH
VIH
VOH
IOH
VIL
VCC
IOL
VOL
OUTPUT
APPLY
MEASURE
TEST
: ' \ IOL
TABLE
55/75472
55/75473
55/75474
NOTE:
VIH
VIH
IOL
VOL
VIL
VCC
VOH
IOH
VIH
GND
VOH
IOH
vlL
VIL
IOL
VOL
VIH
GNO
IOL
VOL
VIL
VIL
VOH
IOH
Each input is tested separately
Fig. 1
II,IIH
Vee
45V;l
-
vee
SEE
NOTES
-=-
V,
UNDER
0
··1
NOTES:
CIRCUIT
',L
B, A
IT
1-=-
Y
II.IIH
OPEN
TEST
A,B
V,
CIRCUIT
y
UNDER
1
1
OPEN
TEST
BA
-=-
A. Each input is tested separately.
B. When testing I, L 55/75473 and
55/75474, the input not under
Each input is tested separately.
Fig. 3
test is grounded. For all other
circuits it is at 4.5 V.
c. When testing V CD, input not
under test is open.
Fig,2
ICCH,ICCl
FOR AND, NAND CIRCUITS
ICCH,ICCl
FOR OR, NOR CIRCUITS
Vee
VCC
OPEN
OPEN
'CCH
l
I
L
__ _
I
I
I
V,~
__________
1
l'cCL
+-~'--",
Both gates are tested simultaneously.
Both gates are tested simultaneously.
Fig.5
Fig.4
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
7-47
•
FAIRCHILD • 55471/75471 SERIES
CHARACTERISTICS MEASUREMENT INFORMATION
AC CHARACTERISTICS
SWITCHING TIMES OF COMPLETE DRIVERS
VOL TAGE WAVEFORMS
TEST CI RCUIT
INPUT
-I
10V
2.4 V
j-';;10ns
I
-,1r-:::90~%~---- 3 V
10%
10%
1------- O.5f.J.s - - - - - - - 1
t--~p--o OUTPUT
90%
55/75472
55/75474
r
I
INPUT
10%
~~~----OV
I
I
I
I
tpLH---j-.o~-_·"';1
l-r-tPHL
1
---90-%1\::
l
OUTPUT
0.4 V
50%
_ _ _ _ _ _ _ _ _ _~';;.O%;.J
I
-:
50%
...,;.;'rn~'
!-'THL
NOTES:
A. The pulse generator has the following characteristics: PRR
=:
1 MH2, Zout
~
_
'TLH--j
500
l
90%
VOH
L ___ VOL
I---
n.
B. CL includes probe and jig capacitance.
Fig. 6
TEST CIRCUIT
VOLTAGE WAVEFORMS
---I
VCC"'55V
r';;;10ns
I
..i1r-:::90~o/.:-.- - - - 3 V
INPUT
55/75471
55/75473
I
:
I
,;:1O::.%'!7._: _________ 0 V
~1;;:0~%:....._ _ _ _ _ _ _ _ _
1-1~----- 40" - - - - - _•...tl
INPUT
;;;;;:;~
jJ.'
---j I I- < 5 "'
:
90%
1.5 V
10%
55/75473
55/75474
OUTPUT
T~
0.4 v
NOTES:
A. The pulse generator has the following characteristics:
PRR = 12.5 MHz, Zout= 50 n.
B. CL includes probe and jig capacitance.
Fig. 7
7-48
----l I I-- <10",
90%X[:-:--------3V
15 V
I
10%
...... . ; . ; . . - - - - O V
9665-9666-9667-9668
HIGH VOLTAGE, HIGH CURRENT DARLINGTON DRIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The 9665, 9666, 9667 and 9668 are comprised of seven
high voltage, high current npn Darlington transistor pairs. All units feature common
emitter, open collector outputs. To maximize their effectiveness, these units contain
suppression diodes for inductive loads and appropriate emitter-base resistors for leakage.
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEW)
PACKAGE OUTLINE 68, 98
. PACKAGE CODE 0, P
The 9665 is a general purpose array which may be used with DTL, TTL, PMOS, CMOS,
etc. Input current limiting is done by connecting an appropriate discrete resistor to each
input.
The 9666 version does away with the need for any external discrete resistors, since each
unit has a resistor and a Zener diode in series with the input. The 9666 was specifically
designed for direct interface from PMOS logic (operating at supply voltages from 14 to
25 V) to solenoids or relays.
The 9667 has a series base resistor to each Darlington pair, thus allowing operation
directly with TIL or CMOS operating at supply voltages of 5 V.
IN A
OUT A
IN B
OUT B
IN C
OUT C
IN 0
OUT 0
IN E
OUT E
IN F
OUT F
IN G
OUT G
GND
CD·\I1MON
The 9668 has an appropriate input resistor to allow direct operation from CMOS or
PMOS outputs operating from supply voltages of 6 to 15 V.
ORDER INFORMATION
9665, 9666, 9667 and 9668 offer solutions to a great many interface needs, including
solenoids, relays, lamps, small motors and LEOs. Applications requiring sink currents
beyond the capability of a single output may be accommodated by paralleling the outputs.
_ SEVEN HIGH GAIN DARLINGTON TRANSISTOR PAIRS
_ HIGH OUTPUT VOLTAGE (VCE = 50 V)
_ HIGH OUTPUT CURRENT (IC = 350 rnA)
• DTL, TTL, PMOS, CMOS COMPATIBLE
• SUPPRESSION DIODES FOR INDUCTIVE LOADS
_ 2 WATT PLASTIC DIP PACKAGE ON COPPER PIN FRAME
EQUIVALENT CIRCUIT
(Each Device)
9665
TYPE
PART NO.
9665
9665
9666
9666
9667
9667
9668
9668
9665DC
9665PC
9666DC
9666PC
9667DC
9667PC
9668DC
9668PC
9667
COM
COM
2.7 k
COM
'COM
10.5 k
7-49
•
FAIRCHILD • 9665 • 9666 • 9667 • 9668
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Output Voltage, VCE
Input Voltage, VIN
Emitter-Base Voltage, VEBO
Continuous Collector Current, IC
Continuous Base Current, IB
Power Dissipation (6B, Kovar lead frame)
Power Dissipation (9B, Copper lead frame)*
Pin Temperature (Molded DIP, Soldering, lOs)
(Hermetic DIP, Soldering, 60 s)
Ambient Temperature Range (operating), TA
Storage Temperature Range, TS
55 V
30 V
6V
500 mA
25 mA
1.0W
2.0W
260°C
300°C
O°C to +85°C
-65°C to +150 oC
*Under normal operating conditions, these units will sustain 350 rnA per output with VCE(sat)::O; 1.6 V at 70 0 e with a pulse width of 20 ms and a duty cycle
of 30%.
ELECTRICAL CHARACTERISTICS: TA
SYMBOL
= 25°C
CHARACTERISTICS
Output Leakage Current
ICEX
VCE(sat)
IIN(ON)
(unless otherwise noted)
TEST
FIGURE
TEST CONDITIONS (Note 1)
la
VCE
lb
VCE
lb
VCE
Collector-Emitter Saturation
2
IC
Voltage
2
2
IC
Input Current
3
VIN
3
VIN
3
VIN
3
VIN
= 50 V,
= 50 V,
= 50 V,
= 70°C
= 70°C,
TA = 70°C,
TA
VIN
VIN
= 6 V (9666)
= 1 V (9668)
= 500/iA
IB = 350/iA
IB
100 rnA, IB = 250/iA
= 17 V (9666)
= 3.85 V (9667)
= 5 V (9668)
= 12 V (9668)
IIN(OFF)
Input Current
(Note 2)
4
VIN(ON)
Input Voltage
(Note 3)
5
= 500/iA. TA = 70°C
VCE = 2 V, IC = 300 mA (9666)
5
VCE
= 2 V,
Ic
5
VCE
= 2 V,
Ic
5
VCE
5
VCE
5
VCE
= 2 V,
= 2 V,
= 2 V,
= 275 mA (9668)
Ic = 350 rnA (9668)
Ic
IC
5
VCE
= 2 V,
= 2 V,
2
VCE
= 2 V,
5
VCE
TYP
TA
= 350 rnA.
IC = 200 rnA,
=
MIN
50
MAX
UNITS
100
/iA
500
/iA
500
/iA
1.25
1.6
V
1.1
1.3
V
0.9
1.1
V
0.85
1.3
mA
0.93
1.35
mA
0.35
0.5
mA
1.0
1.45
rnA
65
/iA
13
V
= 200 mA (9667)
2.4
V
= 250
mA (9667)
2.7
V
= 300 mA (9667)
Ic = 125 mA (9668)
IC = 200 mA (9668)
3.0
V
5.0
V
6.0
V
7.0
V
8.0
V
30
pF
IC
IC
hFE
DC Forward Current Transfer
Ratio
CIN
Input Capacitance
tpLH
Turn-On Delay
0.5 VIN to 0.5 VOUT
tpHL
Turn-Off Delay
0.5 VIN to 0.5 VOUT
IR
Clamp Diode L ·akage Current
6
VF
Clamp Diode F, ward Voltage
7
= 350 mA (9665)
1000
15
= 50 V
IF = 350 mA
/is
/is
VR
NOTES:
1. All limits stated apply to the complete Darlington series except as specified for a single device type.
2 The IIN(OFF) current limit guaranteed against partial turn-on of the output.
3. The VIN(ON) voltage limit guarantees a minimum output sink current per the specified test conditions.
7-50
1.7
50
/i A
2.0
V
FAIRCHILD • 9665 • 9666 • 9667 • 9668
TYPICAL ElECTRICAL PERFORMANCE
COLLECTOR CURRENT
AS A FUNCTION OF
SATURATION VOLTAGE
COLLECTOR CURRENT
AS A FUNCTION OF
INPUT CURRENT
800
2.0
400
I
~
~ 600
(~~~Cii~LLLELbo DEJICES)
~
I
-'
~
~
a: 400
t
I
8 200
TYPICAL
(SINGLE DEVICE)-
,',
a: 200
~
/
I
I
I
!d
I
/j
/
0.5
1.0
1.5
E 1.5
....
II:
II:
::>
U
~
~
I
~
,,
V
MAy ,
,
/
~
2.0
0.5
18
20
22
24
/ '
~
1.5
....
~
~
"
::>
MA),-
1.0
0
....
~
V/
('
~
I
,
~
0.5
(i)
V
"".-
I
,/
"
V
"
~
T;'e. ,
~
","
NOPPER LEAD FRAME
6QoCjW
1, 5
1.0
'\
~
w
CJ
;2
o
if
~
"
11
VIN - INPUT VOLTAGE - V
12
~~
TWLEAl
0.5 -~OVAR
1 25
00
r, ,
~
~
FRAM]E
50
,
100
~
I
~
~ 300~---+~~rl-~,-~__~----~
""~
u
~ 200 ~---+---~+""-->'<------->","----->"./
'"
~
"
DUTY CYCLE - %
7-51
,,
AMBIENT TEMPERATURE - °C
II:
DUTY CYCLE - %
,
,,
PEAK COLLECTOR CURRENT
AS A FUNCTION OF
DUTY CYCLE AND NUMBER
OF OUTPUTS
(CERAMIC PACKAGE)
PEAK COLLECTOR CURRENT
AS A FUNCTION OF
DUTY CYCLE AND NUMBER
OF OUTPUTS
(PLASTIC PACKAGE)
•
""\..EVICE LljlY
ffi
,,/
10
liN - INPUT CURRENT - rnA
'"
1i
26
2.0
z
o
"E
,,
/
1.5
I
16
ALLOWABLE AVERAGE
PACKAGE POWER
DISSIPATION
AS A FUNCTION OF
AMBIENT TEMPERATURE
2.0
Z
14
INPUT CURRENT
AS A FUNCTION OF
INPUT VOLTAGE
FOR TYPE 9668
....
:>
12
INPUT CURRENT
AS A FUNCTION OF
INPUT VOLTAGE
FOR TYPE 9667
I
~
.-
VIN - INPUT VOLTAGE - V
w
CJ
~ 1.0
.- .-
.- .-
V
o
600
400
0.5
TyJ ....
liN - INPUT CURRENT -I1A
TYP/
~
g
V
....
V
.-
/
1.0
VCE(sat) - SATURATION VOLTAGE - V
2.5
>
/
~
/
200
.- .-
.- .-
I
j
I
8100
./'LIMIT
/
I
/
My-
"
/
I
I
I
I
o
,,
,
I,
II
o
o
,
-/-
I
!d
300
::>
I
U
I
II:
II:
I
::>
MAy
TYPICAL
~
I
II:
II:
~
INPUT CURRENT AS A
FUNCTION OF INPUT
VOL TAGE FOR TYPE 9666
,
,
,
','
150
FAIRCHILD • 9665 • 9666 • 9667 • 9668
TEST CIRCUITS
Fig.1a
Fig.1b
OPEN +50 V
OPEN +50 V
I
Fig. 2
Fig. 3
OPEN
OPEN
VIN-=-
I
Fig. 4
Fig. 5
OPEN
OPEN +50 V
Ie
I
Fig. 6
Fig. 7
+50 V
7-52
FAIRCHILD • 9665 • 9666 • 9667 • 9668
TYPICAL APPLICATIONS
PMOS TO LOAD
+Vss
+v
16
15
14
4
l
13
9666
12
7
PMOS
OUTPUT
TTL TO LOAD
+Vcc
+v
16
I
15
14
4
13
9667
12
11
10
TTL
OUTPUT
-=
BUFFER FOR HIGHER CURRENT LOADS
+VOD
+v
16
15
3
14
4
~1
,.~
OUTPUT
-=
5
13
9668
12
11
10
7
-=
7-53
55/75491 • 55/75491 A
55/75492 • 55/75492A
MOS TO LED SEGMENT AND DIGIT DRIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION-The 55/75491 and 55/75491 A, LED Quad Segment Digit
Drivers interface MOS signals to common cathode LED displays. High output current capability makes the devices ideal in time multiplex systems using segment address or digit scan
method of driving LEDs to minimize the number of drivers required.
The 55/75492 and 55/75492A, Hex LED/Lamp Drivers convert MOS signals to high output
currents for LED display digit select or lamp select. The high output current capability makes
the devices ideal in time multiplex systems using segment address or digit scan method of
driving LEDs to minimize the number of drivers required.
CONNECTION DIAGRAMS
14·PIN DIP
(TOP VIEW)
PACKAGE OUTLINE 6A 9A
PACKAGE CODE
D P
55/75491 • 55/75491 A
lA " - - ---_ _.I"'I
55/75491 • 55/75491 A
•
•
•
•
•
50 mA SOURCE OR SINK CAPABILITY
LOW INPUT CURRENTS FOR MOS COMPATIBILITY
LOW STANDBY POWER
FOUR HIGH GAIN DARLINGTON CIRCUITS
10 V and 20 V OPERATION
lC
2C
2E
55/75492 • 55/75492A
•
•
•
•
•
250 mA SINK CAPABILITY
MOS COMPATIBLE INPUTS
LOW STANDBY POWER
SIX HIGH GAIN DARLINGTON CIRCUITS
10V and20V
ORDER INFORMATION
TYPE
PART NO.
55491
55491 DM
75491
75491 DC
75491
75491 PC
55491A
55491 ADM
75491 A
75491ADC
75491 A
75491APC
EQUIVALENT CIRCUITS
55/75492 • 55/75492A
1/2 OF 75491175491A
lY
COLLECTOR
INPUT
COLLECTOR
2Y
,----- -- --- - - -- -- ------l
I
I
I
I
INPUT 1 4 k ! !
I
6 k!l
2A
GND
3A
I
3Y
I
4Y
I
7 k!!
~~:~
__ __ __ __-+________
~
I
I
7 k!!
~
~
~~
__
I
TONEXT
I DRIVER
-+~I
vss
I
L ___ _
-l
GND
EMITIER
EMITIER
TO NEXT
DRIVER
7-54
ORDER INFORMATION
TYPE
PART NO.
55492
55492DM
75492
75492DC
75492
75492PC
55492A
55492ADM
75492
75492ADC
75492A
75492APC
FAIRCHILD. 55/75491/A. 55/75492/A
EQUIVALENT CIRCUIT
1/3 OF 75492/75492A
INPUT
OUTPUT
,--------- INPUT:
4.4 k!l
Vr--..
I
i
7k!l
I
'----
I
430!l
1::S~
OUTPUT
- - - - - - - - - -,
V- i
r--..
i
4.4 k!l
-K
7k!l
~
H::::
i
"":F-
I
I
430!l
f ____ J
! ~I---..........----t---....-----I
VSS
L __ _ __ _ _
_ ____
TO NEXT
DRIVER
L--_---''---_ 6~1~~~T
GND
ABSOLUTE MAXIMUM RATINGS
Supply Voltage 55/75491, 55/75492
55/75491A,55/75492A
Input Voltage (Note 1)
Collector (Output) Voltage (Note 2) 55/75491, 55/75492
55/75491A,55/75492A
Collector (Output) to Input Voltage 55/75491, 55/75492
55/75491 A, 55/75492A
Emitter to Ground Voltage (V IN ;. 5.0 V) 55/75491
55/75491 A
Emitter to Input Voltage 55/75491, 55/75491 A
Continuous Collector Current 55/75491, 55/75491 A
55/75492,55/75492A
Collector Output Current (75492 and 75492A only)
all collectors
Continuous Total Power Dissipation (Note 3)
Operating Temperature Range
Storage Temperature Range
Pin Temperature
Hermetic DIP (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
10 V
20V
-5.0 to Vss
10 V
20 V
10 V
20 V
10 V
20 V
5.0V
50mA
250mA
600mA
800mW
O°Cte 70°C
-55°C to +125°C
300°C
260°C
NOTES:
1. The input is the only device terminal which may be negative with respect to ground.
2. Voltage values are with respect to network ground terminal unless otherwise noted.
3. Above 60°C ambient temperature, derate linearly at 8.3 mWrC.
55/75491 • 55/75491 A
TRUTH TABLE
INPUT
L
H
OUTPUT
E
L
H
55175492 • 55175492A
TRUTH TABLE
I
OUTPUT
C
H
L
I
I
7-55
INPUT
L
H
I
I
I
OUTPUT
H
L
I
I
I
FAIRCHILD. 55/75491/A. 55/75492/A
55491 • 55491A
ELECTRICAL CHARACTERISTICS: Vss = 10 V for 55491, Vss = 20 V for 55491A,
TA = -55°C to +125°C unless otherwise specified.
SYMBOL
V CEL
TYP
MAX
UNITS
V, N = 8.5 V through 1.0 kfl
10L = 50 mA, V E = 5.0 V, TA = 25°C
0.9
1.2
V
Y,N = 8.5 V through 1.0 kfl
10L = 50 mA, V E = 5.0 V
0.9
2.0
V
250
I"A
250
I"A
CHARACTERISTICS
CONDITION
LOW Level Collector to Emitter Voltage
VCH - 10 V, 55491
ICH
Collector HIGH Current
I,
Input Current at Maximum Input Voltage
lEA
Reverse Biased Emitter Current
Iss
Supply Current
VCH - 20 V, 55491A
VE = 0,
V,N =0.7V
VCH - 10 V, 55491
V CH = 20 V, 55491A
V E = 0,
MIN
liN = 4Ol"A
Y'N - 10 V, 55491
10L = 20mA
Y'N = 20 V, 55491A
2.0
4.0
4.0
8.0
100
Ic = 0, Y'N = 0, VE = 5.0 V
mA
1.0
I"A
mA
TYP
MAX
UNITS
0.9
1.2
V
0.9
1.5
V
100
I"A
100
I"A
3.3
6.6
mA
75491 • 75491A
ELECTRICAL CHARACTERISTICS: Vss = 10 V for 75491, Vss = 20 V for 75491 A,
TA = O°C to 70°C unless otherwise specified.
SYMBOL
CHARACTERISTICS
CONDITION
MIN
Y'N = 8.5 V through 1.0 kfl
V CEL
LOW Level Collector to Emitter Voltage
10L = 50 mA, V E = 5.0 V, TA = 25°C
V, N - 8.5 V through 1.0 kfl
10L = 50 mA, VE = 5.0 V
V CH - 10 V, 75491
V CH = 20 V, 75491A
ICH
Coliector HIGH Current
VCH - 10 V, 75491
V CH - 20 V, 75491A
I,
Input Current at Maximum Input Voltage
IER
Reverse Biased Emitter Current
Iss
Supply Current
Y'N = 10 V, 75491
Y'N = 20 V, 75491A
V E = 0,
Y'N = 0.7V
VE = 0,
liN = 4Ol"A
2.0
10L = 20mA
4.0
100
Ic = 0, Y'N = 0, VE = 5.0 V
1.0
I"A
mA
MAX
UNITS
AC CHARACTERISTIC: Vss = 7.5 V, TA = 25°C.
SYMBOL
tpHL
tpLH
CHARACTERISTICS
Propagation Delay Time
CONDITION
RL = 200 fl, V ,NH = 4.5 V
C L = 15 pF, VE = 0
7-56
MIN
TYP
2Q
ns
100
ns
FAIRCHILD. 55/75491/A. 55/75492/A
55492 • 55492A
ELECTRICAL CHARACTERISTICS: Vss = 10 V for 55492, Vss = 20 V for 55492A,
TA = -55°C to
SYMBOL
VOL
+ 125°C unless otherwise specified.
CHARACTERISTICS
CONDITIONS
Output LOW Voltage
TYP
MAX
UNITS
V ,N = 6.5 V through 0.1 kD
10L = 250 mA, T A = 25°C
0.9
1.2
V
V,N = 6.5 V through 1.0 kD
10L = 250mA
0.9
2.0
V
500
I"A
500
I"A
VOH = 10 V, 55492
10H
VOH - 20 V, 55492A
VOH - 10 V, 55492
Output HIGH Current
I,
Input Current at Maximum Input Voltage
Iss
Supply Current
VOH = 20 V, 55492A
V,N = 10 V, 55492
V,N - 20 V, 55492A
MIN
liN = 40 I"A
V ,N
~
0.5 V
10L = 20 mA
2.0
4.0
4.0
B.O
mA
1.0
mA
TYP
MAX
UNITS
0.9
1.2
V
0.9
1.5
V
200
I"A
200
I"A
75492 • 75492A
ELECTRICAL CHARACTERISTICS: Vss = 10 V for 75492, V ss = 20 V for 75492A,
T A = O°C to 70°C unless otherwise specified.
SYMBOL
VOL
10H
CHARACTERISTICS
Output LOW Voltage
Output HIGH Current
CONDITIONS
VOH = 10 V, 75492
VOH = 20 V, 75492A
I,
Input Current at Maximum Input Voltage
Iss
Supply Current
MIN
V ,N = 6.5 V through 1.0 kD
10L = 250 mA, T A = 25°C
V ,N - 6.5 V through 1.0 kD
10L = 250mA
VOH - 10 V, 75492
liN = 4Ol"A
VOH - 20 V, 75492A
V,N = 10 V, 75492
V ,N - 20 V, 75492A
V ,N = 0.5 V
10L = 20 mA
2.0
3.3
4.0
6.6
1.0
mA
mA
AC CHARACTERISTICS: Vss = 7.5 V, TA = 25°C.
SYMBOL
tpHL
tpLH
CHARACTERISTICS
Propagation Delay Time
NOTE. All typical values are atTA
-
CONDITIONS
RL - 39 D, V ,N - 7.5 V
C L =15pF
25 C
7-57
MIN
TYP
30
300
MAX
UNITS
ns
ns
•
FAIRCHILD. 55/75491/A • 55/75492/A
WAVEFORMS
TEST CIRCUIT
VINH - - - - , - - - - - - - , .
7.5V
50%
PULSE
GENERATOR
(SEE NOTE A)
VOH---_.
1 kH
I-~Vv-~
VOL-------~---------J
NOTES:
A. The pulse generator has the following characteristics: ZoUT ~ 50 11, PRR ~ 100 kHz,
B. C L includes probe and jig capacitance.
lw
~
1 /Ls.
TYPICAL APPLICATION
Ivss_ _ ,
_ _ L"'
,
..L
I
I
I
I
I
__~________________________________~
Vss
~I
RL
~~-----------------
-------1
I
I
I 75491
I
DRIVER
: (3 PACKAGES)
I
I
I
I
-------------------~
I
L_~4~ ~~9~
_
~---I_--------------------......J
-=-
/ /
/ /
GND
I I
C).
I /
(J.
II
CI
II
I /
C). (J.
I
I
• 75491A
I QUAD SEGMENT
I
I
Vss
I
I
~DF6----------------------------l
..L
I
1011
I
I
I
I
I
I
I
I
I
I
I
..L
I
I
L - - . r - - -.J
-=-
I
:
I
i gR~~~~AGES)
I
I
I 75492 .75492A
I HEX DIGIT
I
I
I
I
I
L
75492 • 75492A____________________________
--lI
-=-
GND
GND
INTERFACING BETWEEN MOS CALCULATOR CIRCUIT AND LED MULTI-DIGIT DISPLAY
This example of time multiplexing the individual digits in a visible display minimizes display circuitry. Up to twelve digits of a 7-segment display
plus decimal point may be displayed using only two 75491/A and two 754921A drivers.
7-58
I
MEMORY INTERFACE
MEMORY INTERFACE
MOS/CCD Drivers
9624
Dual TTL-to-MOS Interface Element ..................................... 8-3
Dual TTL-to-MOS Interface Element ..................................... 8-3
9625
Dual AND TTL-to-MOS/CCD Driver ................................... 8-10
9643
9644
Dual NAND TTL-to-MOS/CCD Driver .................................. 8-10
9645 (3245)
Quad TTL-to-MOS/CCD Driver ........................................ 8-13
9646 (DS0026) Dual 5 MHz Two-Phase MOS Clock Driver ............................. 8-16
Core-Memory Sense Amplifiers
55175S20
Dual Schottky ±2.5 mV Sense Amp with Complementary Outputs .......
Dual Schottky ±2.5 mV Sense Amp ....................................
55/75S24
55/75S234
Dual Schottky ±2.5 mV Sense Amp ....................................
5517528
Dual Sense Amp with Preamplifier Test Points .........................
55175232
Dual Sense Amp with Open Collector Outputs .........................
55175238
Dual Sense Amp with Preamplifier Test Points .........................
8-22
8-22
8-22
8-41
8-41
8-41
Sink/Source Memory Drivers
55175325
Dual Core Memory Drivers ............................................ 8-59
55175326
Quad Positive OR Sink Core Memory Drivers .......................... 8-71
55175327
Quad Core Memory Switches ......................................... 8-71
9624-9625
DUAL TTL, MOS INTERFACE ELEMENT
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The 9624 is a Duar2-lnput TTL Compatible Interface Gate specifically
designed to drive MOS. The output swing is adjustable and will allow it to be used as a data driver,
clock driver or discrete MOS driver. It has an active output for driving medium capacitive loads.
The 9625 is a dual MOS to TTL level converter. It is designed to convert standard negative MOS logic
levels to TTL levels. The 9625 features a high input impedance which allows preservation of the driving
MOS logic level.
NOTE: The TTL and MOS devices manufactured by Fairchild Semiconductor are considered as positive
TRUE logic (the more positive voltage level is assigned the binary state of "'" or TRUE). Following
MI L-STD-806B logic symbol specifications, the 9624 is represented as a NAND gate and the 9625 as a
non-inverting buffer. This convention (of assuming MOS as a positive TRUE logic) has not been uniformly accepted by the industry; therefore, it is necessary to note that with negative TRUE MOS logic
(the more negative voltage level is assigned the binary state "'" or TRUE), the 9624 acts as an AND
gate and the 9625 as an inverter.
CONNECTION DIAGRAMS
9624
'4-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 6A 9A
PACKAGE COOES D P
GNO
NC
INA1
INA2
IN A3
•
•
•
IN AO
TTL COMPATIBLE INPUTS/OUTPUT
MOS COMPATIBLE OUTPUT/INPUTS
LOWPOWER
vOO
9624 EQUIVALENT CIRCUIT
15kn
5k"
14
Vee
13
TAP
500"
15""
500"
5k"
ORDER INFORMATION
TYPE
PART NO.
9624
9624DM
9624DC
9624C
9624PC
9624C
9625
14-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 6A 9A
PACKAGE CODES D P
GNO
NC
NC
9625 EQUIVALENT CIRCUIT
DUTA
14
Vee
INA
10kn
5
IN 1
5k"
5 k"
10""
22 kG
22 k!1
<>-""",......-r-
10
r-"l>IV--O IN 2
3 k"
7
V DO
3k"
8-3
NC
NC
VOO
NC
ORDER INFORMATION
TYPE
PART NO.
9625DM
9625
9625C
9625DC
9625C
9625PC
I
FAIRCHILD • 9624 • 9625
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Temperature (Ambient) Under Bias
vee Pin Potential to Ground Pin
Voltage Applied to Outputs for HIGH Output State (9624)
Voltage Applied to Outputs for HIGH Output State (9625)
I nput Voltage (de) (9624)
Input Voltage (de) (9625)
VOO Pin Potential to Ground Pin
VOO Pin Potential to Tap Pin (9624)
V TAP
Internal Power Dissipation (Note 3)
-65°C to +l50°C
_55°C to +125°C
V oo to+l0V
V 00 to +Vee value
-0.5 V to Vee value
-0.5 V to +5.5 V
Vee to Voo
-30 V to +0.5 V
-30 V to +0.5 V
Vee +0.5 V
'670mW
Pin Temperature
Hermetic DIP (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
Operating Temperature Range
Military (9624 and 9625)
Commercial (9624C and 9625C)
-5S'C to +125'C
o°c to +70°C
9624
ELECTRICAL CHARACTERISTICS: VCC = 5.0 V ± 10%.
LIMITS
SYMBOL
CHARACTERISTICS
-55°C
MIN
+25°C
MAX
MIN
UNITS
+125°C
TYP
MAX
MIN
CONDITIONS
MAX
VOHl
Output HIGH Voltage
-1.0
-1.0 -0.5
-1.0
V
Vcc = 4.5 V, VDD = -2B V,
VTAP = 0 V, IOH = -10pA
VOH2
Output HIGH Voltage
+3.5
+3.5 +4.0
+3.5
V
Vcc = 5.5 V, V DD = -20 V,
VTAP = 5.5 V, Inputs at V IL'
IOH =-10pA
VOL
Output LOW Voltage
(Note 1)
V
VCC = 4.5 V, IOL = 10 mA.
VDD = -15 to 28 V@VIH'
0';; VTAP ';; VCC (Note 2)
VIH
Input HIGH Voltage
V
Guaranteed Input HIGH
Threshold for all Inputs
VIL
Input LOW Voltage
1.4
1.1
0.8
V
Guaranteed Input LOW
Threshold for all Inputs
IF
Input Load Current
-1.40
-1.25
-1.13
rnA
VCC = 5.5 V, VF = 0.4 V,
VDD=-ll to-28 V
IR
Input Leakage Current
2.0
2.0
5.0
pA
VCC = 5.5 V, VR = 4.0 V,
VDD = -11 to -28 V
ICEX
Output Leakage Current
pA
VCC = 5.5 V, VTAP = 0 V,
VDD = -28 V, VOUT = 0 V
ISC
Output Short
Circut Current
rnA
VCC = 4.5 V, VTAP = 0 V,
VIN = 0 V, VDD = -11 V,
VOUT=-llV
IVCC
VCC Supply Current
6.1
rnA
VCC = 5.5 V, VDD = -15 V,
VTAP = 0 V, Inputs Open
IMAX
Max, Current
10
rnA
VCC = 10 V, VDD = -30 V,
VTAP = 0 V, Inputs Open
tpLH
Propagation Delay
190
250
ns
VCC = 5.0 V, See Figure 1
tpHL
Propagation Delay
50
100
ns
VDD =-13 V, VTAP=OV
2.1
1.7
1.9
50
-12
-31
-14
-32
8-4
-11
-28
FAIRCHILD· 9624 • 9625
9625
ELECTRICAL CHARACTERISTICS: V CC
~
5.0 V ± 10%.
LIMITS
SYMBOL
CHARACTERISTICS
-55°C
MIN
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
V IL
Input LOW Voltage
IF
Input Load Current
ICEX
Output Leakage Current
IVCCL
+25°C
MAX
2.5
MIN
UNITS
+125°C
MAX
TYP
2.6
MIN
CONOITIONS
MAX
2.5
V
VCC = 4.5 V, IOH = -60/lA.
VOO = -11 V, Inputs at V IH
0.5
0.5
0.5
V
VCC = 5.5 V, IOL = 1.5 rnA
VCC = 4.5 V, IOL = 1.2 rnA
VOO = -11 V, Inputs at VIL
-3.0
-3.0
-3.0
V
Guaranteed Input HIGH
Threshold for all Inputs
V
Guaranteed Input LOW
Threshold for all Inputs
-9.0
-9.0
-9.0
/lA
VCC = 5.0 V, V F = -3.0 V,
V OO=-13V
50
/lA
VCC = VCEX = 4.5 V,
VOO =-13 V
Supply Current
4.8
rnA
VCC = 5.5 V, VOO = -15 V,
VIN=-10V
IVCCH
Supply Current
2.1
rnA
VCC = 5.5 V, VOO = -15 V,
VIN =OV
IVOO
VOO Supply Clment
-9.0
rnA
VCC = 5.5 V, VOO = -15 V,
Input Open or GNO
IMAX
Max, VOO
Supply Current
-25
rnA
VCC = 8.0 V, VOO = -20 V,
VIN=OV
tpLH
Propagation Oelay
55
100
ns
VCC = 5.0 V, VOO = -13 V
tpHL
Propagation Oelay
90
150
ns
See Figure 2
210
210
210
9625 AC TEST CIRCUIT AND WAVEFORMS
Rep Rate = 500 kHz
Amplitude = -10 V
Pulse Width = 1.0 /-LS
t r , tf = 20 ns
TESTS
tPLL, tpHH
CONOITIONS
TA
(oC)
VCC
(Volts)
VOO
iVolts)
(kn)
25
5.0
-13
3.75
Fig. 2
8-5
R
I
- -
--
FAIRCHILD
- - -
. 9624 . 9625
9624C
ELECTRICAL CHARACTERISTICS: Vee = 5.0 V
±
5%.
LIMITS
SYMBOL
CHARACTERISTICS
OoC
MIN
+70 oC
+25°C
MAX
MIN
TYP
MAX
MIN
UNITS
CONDITIONS
MAX
-1.0
V
VCC = 4.75 V, V DD= -28 V,
VTAP = 0 V, IOH = -10 tJ A
+3.25
V
VCC = 5.25 V, V DD= -20 V,
VTAP = 5.25 V, Inputs at V IL,
IOH = -10 tJA
V
VCC = 4.5 V, IOL = 10 mA,
VDD = -11 to -28 V @
0':; VTAP':; VCC (Note 2)
V
Guaranteed Input HIGH
Threshold for all Inputs
V
Guaranteed Input LOW
Threshold for all Inputs
V OH1
Output HIGH Voltage
-1.0
VOH2
Output HIGH Voltage
+3.25
VOL
Output LOW Voltage
(Note 1)
VIH
Input HIGH Voltage
V IL
Input LOW Voltage
1.2
1.1
0.95
IF
Input Load Current
-1.32
-1.25
-1.20
rnA
VCC = 5.25 V, VF = 0.45 V
IR
Input Leakage Current
5.0
5.0
10
tJA
VCC
tJA
VCC = 5.25 V, VTAP - 0 V,
VDD = -28 V, VOUT = 0 V
rnA
VCC = 4.75 V, VTAP = 0 V,
VIN = 0 V, VDD = -11 V,
VOUT=-ll V
6.1
rnA
VCC = 5.25 V, V DD= -15 V,
VTAP = 0 V, Inputs Open
10
rnA
VCC = 8.0 V, V DD = -30 V,
VTAP = 0 V, Inputs Open
-1.0 -0.5
+3.25
+3.75
1.9
2.0
1.8
100
= 5.25
V, VR = 4.5 V
ICEX
Output Leakage Current
ISC
Output ShortCircut Current
'VCC
V CC Supply Current
IMAX
Max, Current
tpLH
Propagation Delay
190
250
ns
VCC
tpHL
Propagation Delay
50
100
ns
VDD - -13 V, VTAP - 0 V
-12
-31
-14
-32
-12
-31
9624 AC TEST CIRCUIT AND WAVEFORMS
Rep Rate = 500 kHz
Amplitude = 3 V
Pulse Width = 1 jls
t r , tf ~ 10 ns
C = 15 pF
CONDITIONS
TESTS
VDD
Tap
(Volts)
(Volts)
Voltage
5.0
-13
o
Vee
25
Fig. 1
8-6
= 5.0 V,
See Figure 1
FAIRCHILD • 9624 • 9625
9625C
ELECTRICAL CHARACTERISTICS: VCC = 5.0 V ± 5%.
LIMITS
SYMBOL
CHARACTERISTICS
O°C
MIN
V OH
Output HIGH Voltage
VOL
Output LOW Voltage
V IH
Input HIGH Voltage
V IL
Input LOW Voltage
IF
Input Load Current
ICEX
Output Leakage Current
IVCCL
+25°C
MAX
2.5
MIN
TYP
+70°C
MAX
2.6
MIN
UNITS
CONOITIONS
MAX
2.5
V
VCC = 4.75 V. I OH= -60pA
VOO = -11 V, Inputs at V IH
0.5
0.5
0.5
V
VCC = 5.25 V, IOL = 1.52 rnA
VC C =4.75V,I OL = 1.33 rnA
Inputs at VIL
-3.0
-3.0
-3.0
V
Guaranteed Input HIGH
Threshold for all Inputs
V
Guaranteed Input LOW
Threshold for all Inputs
-9.0
-9.0
-9.0
pA
VCC = 5.0 V, V F = -3.0 V,
VOO = -13 V
100
pA
VCC = V CEX = 4.75 V,
VOO=-13V
Supply Current
4.8
rnA
VCC = 5.25 V, V 00= -15 V,
VIN = -10 V
IVCCH
Supply Current
2.1
rnA
VCC = 5.25 V, V 00= -15 V,
VIN =OV
IVOO
VOO Supply Current
-9.0
rnA
VCC = 5.5 V, VOO = -15 V,
Input Open or GNO
I MAX
Max, VOO
Supply Current
-25
rnA
VCC = 8.0 V, VOO
VIN = 0 V
= -20 V,
tpLH
Propagation Oelay
55
100
ns
VCC = 5.0 V, VOO
= -13 V
tpHL
Propagation Oelay
90
150
ns
See Figure 2
210
210
210
NOTES
1. Max = Voo +1.0 V over Temperature Range. Typ = VOO +0.2 V over Temperature Range.
2. At no time shall the voltage from VOO to VTAP exceed 30 V. See Absolute Maximum Ratings.
3. For Hermetic DIP rating applies to ambient temperatures up to 70D e, above 700 e derate linearly at 8.3 mW/oC. For Flatpak derate linearly
at 7.1 mW/C above 60°C.
111
1/1
9625
=?
liN" +210 ~A
I>
*The extender pin allows the number of inputs to be extended by adding diodes or the DT,uL 933 extender.
* * Fan out into MaS is limited only by MOS leakage currents.
8-7
3/1
I
FAIRCHILD· 9624 • 9625
TYPICAL PERFORMANCE CURVES FOR 9624 AND 9624C
THRESHOLD VOLTAGE
AS A FUNCTION OF
AMBIENT TEMPERATURE
OUTPUT LOW CURRENT
AS A FUNCTION OF
OUTPUT LOW VOL TAGE
OUTPUT HIGH CURRENT
AS A FUNCTION OF
OUTPUT HIGH VOLTAGE
0
0""
0
-5_
i--i - i -
5
V,H
0
5
r- r-- r--
f--
.:;::..
Ot-51---
~
~
--
-20
-r-.
-
f---
I
-25
-55
25
50
75
AMBIENTTEMPERATLJR£-'C
100
125
-13
50
Ol
-Ii
-12
-10
-9.0
-8.0
-7.0
SWITCHING TIME
AS A FUNCTION OF
LOAD CAPACITANCE
" I--
25
50
AMBIENT TEMPERATURE -
75
100
125
./
~200 1--+--+---I---b7""'l-+-- -
~
1-1
-25
-16
~JOO I--+--+--I--+--+--'--j."'-I
~
\.~v.." /'
. -'---17;>'----
-- ~P'k:" - - -
100
i--T-t--t---j--t---I
j
-55
-12
_
~!_--+_i-I--+~ - t - -
-
i
-8.0
SWITCHING TIME
AS A FUNCTION OF
AMBIENT TEMPERATURE
I "fori , '" I--bf=-t-+~,,*===4===-l
--,-i - - -- --::::
-
-4.0
-
'--+--- f - -
OUTPUT 1-11 GH VOLTAGE - VOLTS
I
JO
o
OUTPUT LOW VOLTAGE - VOLTS
~ Ri-i --, -1--+1---r--c---1-:~+-[+=
VOO ·-15V 1
-'SC
__5"V__
-40
-6.0
"'"
I
-J5 - + ' -
-25
~
1-+-
I
I
POWER DISSIPATION
AS A FUNCTION OF
AMBIENT TEMPERATURE
00
\
I
0=
I
0
voo . -IlV
~
t--I-
-J
--,--
- - -- f-- -
-~
5
r--
- t-- t---
t--- t---
i, - '::.ov
l'..
1---1"--+-+--+--1-+-t--1
o~±t.=c:!::t~.
o
200
400
600
800
1000
55
-25
25
50
75
AMBIENT TEMPERATURE - °c
LOAD CAPACITANCE - pf
°c
100
-
125
TYPICAL PERFORMANCE CURVES FOR 9625 AND 9625C
THRESHOLD VOL TAGE
AS A FUNCTION OF
AMBIENT TEMPERATURE
POWER DISSIPATION
AS A FUNCTION OF
AMBIENT TEMPERATURE
SWITCHING TIME
AS A FUNCTION OF
AMBIENT TEMPERATURE
60
200
VDD ~ I]V
CL '15pF
! -
-8.0
..
--
100
30
Off
I
-2.0
1-
"
~
ON
I
r-r-- t--
I
AMBIENT TEMPERATURE-
-25
25
50
75
AMBIENTTfMPERATURE-OC
~
8-8
125
---
V
IplL
80
l---:-
tf'fll-i
40
100
-
:.1
"~
i
f55
-55
-
120
-55
-25
25
50
75
AMBIENT TEMPERATURE - °C
100
125
FAIRCHILD • 9624 • 9625
APPLICATIONS
9624 Clock Driving
(using a high capacitance drive scheme)
Vee
VOO=-27V
V TAP '" 0
v
Your
FOH60R
EQUIVALENT
TYPICAL SWITCHING TIMES
AS A FUNCTION OF
LOAD CAPACITANCE
I
200
ST~RAJE TIME
,so
I
./
I c P'" ~ f -
~
PI
RISE TIME
"
l-
--
-
f-
OE\"p.:{TIt<\E
I
I
"'00
CAPACITIVE LOAD _ pF
TYPICAL SYSTEM APPLICATION
8-9
I
9643· 9644
DUAL TTL TO MOS/CCD DRIVER
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The 9643 and 9644 are Dual Positive-Logic "AND" and
"NAND" TTL-to- MOS Drivers respectively. The 9643 DC/PC is a functional replacement
of the SN75322 with one important exception: the two external PNP transistors are no
longer needed for operation. The 9643 DC/PC is also a functional replacement for the
75363 with the important exception that the V CC3 supply is not needed. The 9644 is a
logical inversion of the 9643 and is a functional replacement for the 75361. The pin
connections normally used for the external PNP transistors are purposely not internally
connected to the 9643 DC/PC.
CONNECTION DIAGRAM
14-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 6A 9A
PACKAGE CODES
0
P
Both devices have separate driver address inputs with common strobe. Both devices
accept standard TTL and DTL input signals and provide high-current and high-voltage output levels suitable for driving MOS/CCD memories. The 9643 may be used to
drive the chip-enable clock of the TMS4030 MOS RAM. The 9644 is suitable for
driving both clock and address inputs for the TMS4062 and 1103 RAM. The 9643 and
9644 operate from the TTL 5 V supply and the MOS supply.
The 9643 and 9644 are available in a-pin DIPs for increased board efficiency.
•
•
•
•
•
•
•
•
•
SATISFIES CCD MEMORY AND DELAY LINE REQUIREMENTS
DUAL POSITIVE-LOGIC TTL·TO·MOS DRIVERS
OPERATES FROM STANDARD BIPOLAR AND MOS SUPPLY VOLTAGES
HIGH SPEED SWITCHING
TTL AND DTL COMPATIBLE INPUTS
SEPARATE DRIVER ADDRESS INPUTS WITH COMMON STROBE
VO H AND VOL COMPATIBLE WITH POPULAR MOS RAMs
DOES NOT REQUIRE EXTERNAL PNP TRANSISTORS OR V CC3
VO H MINIMUM IS VCC2 - 0.5 V
ABSOLUTE MAXIMUM RATINGS: Over operating ambient temperature range
(unless otherwise noted)
-0.5 V to 7 V
Supply voltage range of VCC1 (see Note 1)
-0.5 V to 15 V
Supply voltage range of VCC2
5.5 V
Input voltage
5.5 V
Inter-input voltage (see Note 2)
1000 mW
Continuous total dissipation at (or below) 25°C
ambient temperature
-55°C to 125°C
Operating free-air temperature range
-65°C to 150°C
Storage temperature range
Pin Temperature
Molded dip (Soldering, 10 s)
Hermetic dip (Soldering, 30 5)
NOTES'
1
2
Vortage values are with respect to network ground terrnlnal unless otherwise noted
This rating applies between any two Inputs of anyone of the gates
8-10
ORDER INFORMATION
TYPE
PART NO.
9643
9643DC
9643
9643PC
CONNECTION DIAGRAM
B-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 9T 6T
PACKAGE CODES
T
R
t:
~~
IN A ,
E:
IN B
.L~-
4
GND
Vee1
: aUT A
VCC2
5
-
OUT B
ORDER INFORMATION
TYPE
PART NO.
9643
9643RC
9643
9643TC
9644
9644RC
9644
9644TC
FAIRCHILD. 9643· 9644
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage. Vee 1
4.75
5.0
5.25
V
Supply Voltage. Vee2
4.75
12
15
V
70
°e
Operating Temperature. TA
0
ELECTRICAL CHARACTERISTICS: Over recommended ranges of V CC1 ' V CC2 and operating ambient temperature
unless otherwise noted.
SYMBOL
CHARACTERISTICS
V IH
Input HIGH Voltage
V IL
Input LOW Voltage
V OH
Output HIGH Voltage
VOL
Output LOW Voltage
TYP
(Note 1)
MIN
CONOITIONS
2.0
V CC2 -0.5
IOH -400!'A
IOL 010 mA
Input Voltage
V CC1 - 5.25 V. V CC2 - 11.4 V
V IN = 5.25 V
Input HIGH Current
VIN=2.4V
Input Current at Maximum
IIH
V CC2 -0.2
Input LOW Current
0.2
0.3
V
0.1
mA
80
Supply Current from V CC1
V CC1 = 5.25 V
No Load
All Outputs LOW
V CC2 = 12.6 V
Supply Cu rrent from V CC2
ICC21 L)
V CC1 =
5.25 V
V CC2 = 12.6 V
All Outputs LOW
Supply Current from VCC1
No Load
VCC2 = 13.2 V
Supply Current from VCC2
V CC1 =
5.25 V
V CC2 = 12.6 V
ICC2IH)
mA
-1.0
9644
-1.6
All Outputs HIGH
15
19
14
17
5.5
9.5
9.0
13
4.0
6.0
5.5
9.5
mA
9644
9643
9644
9643
VCC1 = 5.5 V
ICC1IH)
All Outputs HIGH
O.S
9643
ICCl (L)
!'A
0.5
9644
9643
E Inputs
V
40
E Inputs
V IN = 0.4 V
V
0.5
9643
IlL
V
0.4
A Inputs
A Inputs
UNITS
V
O.S
IOL - 1.0 mA
liN
MAX
mA
mA
9644
9643
9644
mA
NOTE1: All typical values are at V CC1 = 5.0 V. V CC2 = 12 V. and TA = 25°C unless otherwise noted.
AC CHARACTERISTICS: V CC1 = 5.0 V. VCC2 = 12 V. TA = 25°C
SYMBOL
CHARACTERISTICS
tDLH
Delay Time
tDHL
Delay Time
tTLH
Rise Time
tTHL
Fall Time
tTLH
Rise Time
tTHL
Fall Time
tpLH A tPLH B
tPHL A tpHLB
CONDITIONS ISee Figure 1)
9643
9644
9643
9644
C L = 300 pF
RSERIES = 0
C L = 300 pF
RSERIES = 10n
Skew between outputs
A and B
MIN
TYP
MAX
UNITS
5.0
3.0
9.0
6.0
17
15
ns
ns
5.0
3.0
9.0
6.0
17
15
ns
ns
6.0
11
17
ns
6.0
11
17
ns
9.0
14
20
ns
9.0
14
20
ns
0.5
8-11
ns
I
FAIRCHILD • 9643 • 9644
AC TEST CIRCUIT AND VOLTAGE WAVEFORMS
VCCl
VIN
~
~
5 V
VCC2
~
12 V
_ _J " " - _
VIN " - _ _J " " -........
I:>--'V\i'r-......-o OUTPUT
J-.JVItv-.......-o OUTPUT
CL
~
CL
300 pF
AC TEST NOTES:
1. The pulse generator has the following characteristics:
PRR ~ 1 MHz, ZOUT - 50 n
2. CL includes probe and jig capacitance.
<10
nS-1
-I
I
I
I-- <10 ns
I
VIN---~L
~~1:-:0"-%- 0,5 ps -~-C~
I
I-- trLH
tOAL-.!
9643 OUTPUT
l--f=r
C
E2
EI
INPUT
REFRESH
H
I
I
I
L
L
I
H
I
I
L
L
I
I
H
I
L
L
I
I
I
H
L
I
I
I
I
H
I
L
H ~ HIGH LOGIC STATE
L ~ LOW LOGIC STATE
I ~ IRRELEVANT
R
C ---------'
8-13
OUTPUT
L
L
L
L
H
H
I
FAIRCHILD • 9645/3245
ABSOLUTE MAXIMUM RATINGS
-10°C to +70°C
-65°C to +150°C
-0.5 V to +7.0 V
-0.5 V to +14.0 V
-1.0 V to Voo
-1.0 V to Voo +1 V
O°C to +70°C
175°C
150°C
Temperature Under Bias
Storage Temperature
Supply Voltage, Vee
Supply Voltage, Voo
All Input Voltages
Outputs For Clock Driver
Operating Temperature Range
Junction Temperature (TJI Ceramic Package
Plastic Package
DC CHARACTERISTICS: TA
= DoC to
70°C, Vcc
= 5.0 V ±5%,
Voo
= 12 V ±5%,
unless otherwise specified.
SYMBOL
CHARACTERISTICS
IFO
Input Load Current, INIA,B,C,DI
-0.25
mA
IFE
Input Load Current, I R, C, E,. E2
-1.0
mA
IRO
Data Input Leakage Current
10
p.A
IRE
Enable Input Leakage Current
40
p.A
0.45
V
VOL
MIN
TYP
Output LOW Voltage
MAX
UNITS
-1.0
V
Voo-0.50
V
VOH
Output HIGH Voltage
Vil
Input LOW Voltage, All Inputs
VIH
Input HIGH Voltage, All Inputs
ICCIH)
Current From Vcc
13
20
mA
IOOIH)
Current From VOO
14
20
mA
POI(H)
Power Dissipation
248
357
mW
Power Per Channel
62
90
mW
Voo
+ 1.0
V
TEST CONDITIONS
= 0.45 V
VF = 0.45 V
VR = 5.0 V
VR = 5.0 V
10l = 5 mA, VIH = 2 V
10l = -5 mA
10H = -1 mA, Vil = 0.8 V
10H = 5 mA
VF
V
2
V
ICCIl)
Current From Vcc
27
35
mA
IDOIl)
Current From Voo
12
15
mA
PD2Il)
Power Dissipation
296
373
mW
74
94
mW
Power Per Channel
8-14
Vcc
Voo
= 5,25 V
= 12.6 V
All Outputs HIGH
VCC
Voo
= 5.25 V
= 12.6 V
All Outputs LOW
FAIRCHILD • 9645/3245
AC CHARACTERISTICS: TA
SYMBOL
= O°C to 70°C, Vee = 5.0 V ±5%,Voo = 12 V ±5%,unless otherwise specified.
CHARACTERISTICS
t-+
Input to Output Delay
tOR
Delay Plus Rise Time
t+-
Input to Output Delay
toF1
Delay Plus Fall Time
tr
Output Transition Time
toR
toF2
MIN (1)
TYP (2,4)
5
11
MAX (3)
18
3
UNITS
32
7
TEST CONDITIONS
ns
RSERIES
ns
RSERIES
ns
RSERIES
18
32
ns
RSERIES
13
20
ns
RSERIES
Delay Plus Rise Time
27
38
ns
RSERIES
Delay Plus Fall Time
24
38
ns
RSERIES
10
=0
=0
=0
=0
= 200
= 200
= 200
NOTES:
11.> Cl = 150 pF
12.) Cl = 200 pF
13.1 Cl = 250 pF
14.1 Typical values are measured at 25°C
AC TEST CIRCUIT AND WAVEFORMS
~'~
------.. \.
.
"N5V
I
1i~V______ _
GNO _ _ _ _ _ _ _
I •
I.
~------------------------
~~~
~
.... ..-", l_ -
VIN_
lCL
Your
VOUT
GND
="=" '". . ",: 2~: f,.:. ",~.1V'i._' r"- - ~t_·I.--I-
~
AC Test Conditions:
input Pulse Amplitude = 3.0 V
Input PUlse Rise and Fall Times = 5 ns Between 1 voit and 2 volts
8-15
tOR
r-
l j'.l..~~~TV~
-=-.:r :-- -~ I 1
~
IOF
r.-
I
9646/0026
DUAL MaS CLOCK DRIVER
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The 9646/0026 is a low-cost monolithic dual MOS clock
driver, designed for high speed driving of highly capacitive loads in a MOS system. The
9646/0026 is intended for applications in which the output pulse width is logically
controlied, i.e., the output pulse width is equal to the input pulse width. 9646/0026 is
identical to the OS0026.
CONNECTION DIAGRAM
14-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES
PACKAGE CODES
•
•
•
•
•
•
•
6A
D
9A
P
FAST TRANSITION TIMES - 20ns WITH 1000 pF LOAD
HIGH OUTPUT SWING - 20 V
HIGH OUTPUT CURRENT DRIVE - ±1.5 A
HIGH REPETITION RATE - 5 TO 10 MHz DEPENDING ON LOAD
TTL OR DTL COMPATIBLE INPUTS
LOW POWER CONSUMPTION - 2 mW WHEN IN MOS "0" STATE
+5 V OPERATION FOR N-CHANNEL MOS CAPABILITY
ORDER INFORMATION
EQUIVALENT CIRCUIT
11/2 CIRCUIT SHOWN)
v-
...
R1
05
INPUT
PART NO.
9646/0026
9646/0026
9646PC/0026
9646DM/0026
J
R5
R7
TYPE
Jo,
R6
03
......
01
010
1
1...1
I~
R2
~.
t."
1
09
I
R3
I-
08~
I
f2
R11
1...1
I~
#
OUTPUT
I
01
~
..., ~ 06
Vr-.,. 02
0'
~
08
l
1....1
1'1
R'
J I
V 06
r-.,.
.....
05
~I
VI
07
1....1
r
...,
c
...
09¥J
~ R10
Yr-.,. 07
R8
R9
v-
8-16
FAIRCHILD. 9646/0026
ABSOLUTE MAXIMUM RATINGS
V+ - V- Differential Voltage
Input Current
Input Voltage (VIN -V-)
Peak Output Current
Operating Temperature Range
9646DM/0026
9646PC/0026
Storage Temperature Range
Pin Temperature (Soldering, 10 s)
22 V
100 mA
5.5 V
1.5 A
-55° C to +125° C
O°C to +70°C
-65° C to +150° C
300°C
ELECTRICAL CHARACTERISTICS: (Notes 2 and 3)
SYMBOL
CHARACTERISTICS
CONDITIONS
MIN
TYP
2
1.5
MAX
UNITS
VIH
Logic "1"
Input Voltage
V- = OV
hH
Logic "1"
Input Current
VIN -(V-) = 2.4 V
10
15
rnA
VIL
Logic "0"
Input Voltage
V- = OV
0.6
0.4
V
hL
Logic "0"
Input Current
VIN-(V-)=OV
-3
-10
JJ-A
VOL
Logic "1"
Output Voltage
VIN -(V-)= 2.4 V
(V-)+0.7
(V-)+1.0
V
VOH
Logic "0"
Output Voltage
VIN -(V-)= 0.4 V,VBB
ICC(ON)
"ON"
Supply Current
(V+) - (V-) = 20 V, VIN - (V-) = 2.4 V
one side on
30
40
rnA
ICC(OFF)
"OFF"
Supply Current
(V+) - (V-) = 20 V
VIN - (V-) = 0 V
10
50
100
500
JJ-A
JJ-A
MIN
TYP
MAX
UNITS
5
7.5
11
12
ns
ns
12
13
15
ns
ns
~
V+ +1.0 V
V+ -1.0
V
V
V+ -0.7
SWITCHiNG CHARACTERISTICS: TA = 25°C (Notes 5 and 7)
SYMBOL
CONDITIONS
CHARACTERISTICS
tON
Turn-on Delay
Figure 1
Figure 2
tOFF
Turn-oil Delay
Figure 1
Figure 2
tr
tf
Rise Time
Fall Time
Figure 1
Note 5
CL = 500 pF
CL = 1000 pF
15
20
18
35
ns
ns
Figure 2
Note 5
CL = 500 pF
CL = 1000 pF
30
36
40
50
ns
ns
Figure 1
Note 5
CL = 500 pF
CL = 1000 pF
12
17
16
25
ns
ns
Figure 2
Note 5
CL = 500 pF
CL = 1000 pF
28
31
35
40
ns
ns
NOTES:
1. "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual
device operation.
2. These specifications apply fori(V+1 - (V-) = 10 Vt020 V, CL = 1000 pF, overthetemperature range of -55' C to +125' Clor the 9646DM and 0' Cto +70' Clor
the 9646PC.
3. All currents into device pins shown as positive, out of device pins are negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis,
4. All typical values for the TA = 25' C.
5, Rise and fall time are given for MOS logic levels; i.e., rise time is transition from logic "0" to logic "1" which is voltage fall.
8-17
I
FAIRCHILD. 9646/0026
TV~CALPERFORMANCECURVE
INPUT CURRENT
VS INPUT VOLTAGE
TURN-ON AND TURN-OFF DELAY
VS TEMPERATURE
10
24
/
V
"EI
i
:'i
-
~
:::>
u
>-
ir
-2
V
/
,/
,.
18
it
Z
a:
14
0
12
:::>
10
>-
,/
to,
--
r-.....,
tOFF
...... V
t-
O
1.0
0.5
0.5
1.5
1.0
2.0
Vee = 20 V
;~~;o ~N~~~~~ pF -50
2.5
-25
INPUT VOLTAGE - V
40
FALL TIME VS LOAD
CAPACITANCE
/V;c T~ST IC'R~U'~
30
10
0
J.11
V
V
20
~
o
o
IFI'GUIRE
i)
U
I
(FIGURE 1)
~
;::
400
600
800
1000
1200
200
400
600
800
1000
DC POWER (PDC) VS
DUTY CYCLE
2000
1800
~~
1600
ffi 5
1400
~
20 V
L
~ ~ 1000
600
200
100
200
300
CL
V
V DRIVING
74S0~_
280
~
,6-
~
160
80
40
9646
700
200
120
......r--I
500, 600
"
~
TRANSISTOR
WITH 50 n
TO +5 Y DRIVING
400
V
I
,
00
800
/
/
V
Poe
L
20
8-18
L'/
V
/
~/
10
V
Jr-v , / / '
30
40
=
(v+-v )2(OC)_
I 0.6 ~
50
DUTY CYCLE - %
OUTPUT PULSE WIDTH - ns
/
L
V-.V i/
IVT) - (V-) ~ 20
IV+) -IV-)~17~
IV+) - IV-) " 12 V
240
I
~
......
10
320
V
...--
400
360
/
I
V
TA = 25 C
Q
1200
00
1200
400
V+ - IV-)
TA = 25°C
CL = 1000 pF
LOGICALLY CONTROLLED
PULSE (FIGURE 2)
a: ~ 800
::::)
o
RECOMMENDED INPUT COUPLING
CAPACITANCE
I
8
/.,,-
o
200
U-H
/ ,,- V ~c TEIST b.RL,) 17u~Ey I I ~
10
LOAD CAPACITANCE - pF
~
~~
V
~
--
TEST CIRCUIT
TGI"Et l I
V
20
~
~
-
2400
w
v;.,c
c
.....- rj T~ST IC'RL,~
V
Iv V
30
1'-
I
LOAD CAPACITANCE·-pF
2200
25
IF'jURE
i'
I
50
75
100
TEMPERATURE _ °C
RISE TIME VS LOAD
CAPACITANCE
-
Z
:::>
a:
>-
-4
-6
20
>
~
0
I
>-
;!;
22
60
I
70
80
125
FAIRCHILD • 9646/0026
INPUT
+5V
Il
o.1 /l F
OUTPUT
I
I
9646
I
I
I
+t>+
VIN = 5 V
PRF == 1 MHz
PW = 0.5 /-IS
Ir = 11 $10 ns
I
J--
I
L_
'--------~~~
5V
/
INPUT
OUTPUT
CL
11000 pF
90%
J-l0%
1\._
_
----1--.1
ION
Fig. 1
I
+20 V
PULSE GEN 10l..........INPUT
....
C,N
1000 pF
50
10
9646
CL
1000 pF
0-3V
Ir = If:::; 10 ns
Fig. 2
8-19
FAIRCHILD. 9646/0026
Vee
y
RS
V
04
V
07
r.,.
02
C'N
VINo---j
R3
Y...... 02
"...01
......
i
Your
Cl
R8
09-""""
/1
VEE
Fig. 3 SIMPLIFIED SCHEMATIC DIAGRAM
APPLICATIONS INFORMATION
OPERATION OF THE 9646/0026
The simplified schematic diagram of 9646/0026, shown in Figure 3 is useful in explaining the
operation of the device. Figure 3 illustrates that as the input voltage level goes high, diode D1
provides an 0.7 V "dead zone" thus ensuring that 02 is turned "on" and 04 is turned "off" before 07
is turned "on". This prevents undesirable "current spiking" from the power supply, which would
occur if 07 and 04 were allowed to be "on" simultaneously for an instant of time. Diode D2
prevents "zenering" of 04 and provides an initial discharge path for the output capacitive load by
way of 02.
As the input voltage level goes low, the stored charge in 02 is used advantageously to keep 02 "on"
and 04 "off" until 07 is "off". Again undesirable "current spiking" is prevented. Due to the external
capacitor, the input side of Gin goes negative with respect to VEE causing 09 to conduct
momentarily thus assuring rapid turn "off" of 07.
The complete circuit (equivalent circuit on front page) basically creates Darlington devices of
transistors 07,04 and 02 as shown in the simplified circuit of Figure 3. Note that when the input
goes negative with respect to VEE, diodes D7 through D10 turn "on" assuring faster turn "off" of
transistors 01, 02, 06 and 07. Resistor R6 insures that the output will charge to within one VSE
voltage drop of the Vee supply.
SYSTEM CONSIDERATIONS
Overshoot
In most system applications the output waveform of the 9646/0026 will "overshoot" to some degree,
However, "overshoot" can be eliminated or reduced by placing a damping resistor in series with the
output. The amount of resistance required is given by: Rs = 2.,ff]CL where L is the inductance of
Jhe line and GL is the load capacitance. In most cases a series of damping resistor in the range of 10to-50n will be sufficient. The damping resistor also affects the transition times of the outputs. The
speed reduction is given by the formula:
tTHL
~
trLH = 2.2 Rs GL (As is the dampi ng resistor>.
Crosstalk
The 9646/0026 is sensitive to crosstalk when the output voltage level is high (Va ~ Vee>' With the
output in the high voltage level state, 03 and 04 are essentially turned "off". Therefore, negativegoing crosstalk will pull the output down until 04 turns "on" sufficiently to pull the output back
8-20
FAIRCHILD. 9646/0026
towards Vee. This problem can be minimized by placing a "bleeding" resistor from the output to
ground. The "bleeding" resistor should be of sufficient size so that 04 conducts only a few
milliamperes. Thus, when noise is coupled, 04 is already "on" and the line is quickly clamped by
04. Also note that in the equivalent circuit 06 clamps the output one diode-voltage drop above Vee
for positive-going crosstalk.
Power Supply Decoupling
The decoupling of Vee and VEE is essential in most systems. Sufficient capacitive decoupling is
required to supply the peak surge currents during switching. At least a 0.1",F to 1.0 ",F low inductive
capacitor should be placed as close to each driver package as the layout will permit.
Input Driving
For those applications requiring split power supplies (VEE < GNO) ac coupling should be employed.
Selection of the input capacitor size is determined by the desired output pulse width. Maximum
performance is attained when the voltage at the input of the 9646/0026 discharges to just above the
device's threshold voltage (about 1.5 V). Performance curve shows optimum values for Gin versus the
desired output pulse width. The value for Gin may be roughly predicted by:
Gin = (2 x 10- 3 ) (PWo)·
For an output pulse width of 500 ns, the optimum value for Gin is:
If single supply operation is required (VEE = GNO), then dc coupling as illustrated in Figure 4 can be
employed. For maximum switching performance, a speed-up capacitor should be employed with
dc coupling. Performance curves show typical switching characteristics for various values of input resistance and capacitance.
TYPICAL APPLICATIONS
AC COUPLED MOS CLOCK DRIVER
Cl
~0t-P_F_ _2-1
7
t-9646
C2
5
~0I-P_F_ _4--1
TWO PHASE elK
) TO SHIFT
REGISTERS, RAMS, CCO ELEMENTS
t--
54/74 SERIES
GATES AND FLOPS
DC COUPLED RAM MEMORY ADDRESS OR PRECHARGE
DRIVER (POSITIVE SUPPLY ONLY)
~~
~.8
1/27400
+}:
2
7
9646
r-)
5
4
t--
1k
~
8-21
TO ADDRESS
LINES ON
MEMORY SYSTEM
I
55/75520 • 55/75524 • 55/755234
DUAL SCHOTTKY CORE MEMORY SENSE AMPLIFIERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - Th.e 55/75820 series of 8chottky sense amplifiers are designed for use with
high-speed core memory systems, where a guaranteed narrow threshold uncertainty of ±2.5 mV is guaranteed.
A unique 8chottky circuit design provides inherent stability of the very accurate input threshold levels over a
wide range of power supply voltage levels and temperature ranges.
These sense amplifiers detect bipolar millivolt-level differential input signals from the memory and provide the
interface circuitry between the memory and the logic section.
The Fairchild 75820 and 75824 do not require an external capacitor (C ext) to stabilize the pre-amplifier section
of the sense amplifier. No degradation of performance will result if a 100 pF capacitor is connected from pin 1
to ground.
The 55/75820 circuit may be used to perform the functions of a flip-flop or register which responds to the sense
and strobe input conditions.
The 55/75824 is intended to be used in systems where independent dual channel sensing with separate outputs are required. 55/758234 is similar to the 55/75824, but have inverted outputs.
• MAX ±2.5 mV OF THRESHOLD VOLTAGE UNCERTAINTY
• INTERNAL COMPENSATION
• SCHOTTKY TECHNOLOGY
• HIGH SPEED AND FAST RECOVERY TIME
• ADJUSTABLE THRESHOLD VOLTAGE LEVELS
• CHOICE OF OUTPUT CIRCUIT FUNCTION
• TTL OR DTL DRIVE CAPABILITY
• TIME AND AMPLITUDE SIGNAL DISCRIMINATION
ABSOLUTE MAXIMUM RATINGS Over Operating Ambient Temperature Range (unless otherwise noted).
Supply Voltages (see Note 1)
7V
Vcc+
Vcc_
Differential Input Voltage, V10 or VREF
-7 V
Voltage From Any Input to Ground (see Note 2)
5.5 V
±5V
5.5 V
Off-State Voltage Applied to Open-Collector Outputs
-65 °C to 150 °C
Storage Temperature Range
UNITS
MIN
TYP
MAX
Vcc± (see Note 1) 75 series
±4.75
±5
±5.25
Vcc± (see Note 1) 55 series
±4.50
±5
±5.5
V
40
mV
RECOMMENDED OPERATING CONDITIONS
15
V REF
V
-55 °C to 125 °C
Operating Ambient Temperature Range, 55S20 Series
75S20 Series
o °C to 70 °C
NOTES:
1. These voltage values are with respect to network ground terminal.
2. Strobe and gate input voltages must be zero or positive with respect to network ground terminal.
8-22
FAIRCHILD. 55/75820.55/75824.55/758234
55/75820
DUAL-CHANNEL SENSE AMPLIFIER WITH COMPLEMENTARY OUTPUTS
CONNECTION DIAGRAM
IS-PIN DIP
(TOP VIEW)
PACKAGE OUTLlNES6B 9B
PACKAGE CODES D P
FUNCTION TABLE
OUTPUTS
INPUTS
A
8
Gy
Gz
SA
SB
Y
Z
X
L
H
Gz
H
H
X
X
X
X
X
H
Gz
Gz
L
H
X
L
H
L
X
H
X
X
X
H
L
L
L
H
X
X
X
L
H
L
X
L
H
-VREFI4~I,.
~
H
X
X
X
X
X
X
X
X
H
X
X
L
L
L
H
+VREFl1
X
L
X
X
X
H
X
X
H
NC[I~li!IVCC+
I Atll~ ~ SA STRoaE
INPUTS
\ A2[!
c
r"
I II
Btl!
INPUTS
~ ely GATE
I
I
B2
~y
-=-' PI
O:~Z
1
,tIilSaSTRoaE
1-'
'---IEJ
vee-I!
DEFINITION OF LOGIC LEVELS
} OUTPUTS
Gz GATE
WGND
positive logic: Y; ~ + A . SA + a . sa
Z;.§Z+Y _ _ _ _
INPUT
H
L
X
AorBt
VIO " VTmax
VIO <;; Vi-min
Irrelevant
AnyGorS
VI ,. VIH min
VI <;; VILmax
Irrelevant
Z ; Gz + Gy(A + SAXB + SB)
ORDER INFORMATION
TYPE
PART NO.
55S2O
55S20DM
75S2O
75S20PC
75S2O
75S20DC
tA and 8 are differential voltages (VIO) between AI and A2 or 81 and 82,
respectively. For these circuits, VIO is considered positive regardless of
which terminal of each pair is positive with' respect to the other.
ELECTRICAL CHARACTERISTICS: Vcc+ = 5 V, Vee- = -5V, over recommended operating temperature range, unless otherwise noted.
SYMBOL
VT
V ICF
liB
110
V IH
V IL
CHARACTERISTICS
TEST FIGURE
Differential input threshold
voltage (see Note 4)
12.5
15
17.5
VREF = 40mV
37.5
40
42.5
VREF = 40 mY, VI(S) = V IH
None
Common-mode input pulse:
t,<;;15ns,t,<;;15ns,\w= 50ns
2
Vcc+ - 5.25 V, Vcc- - -5.25 V, VIO - 0
30
Differential-input offset current
2
Vcc+ - 5.25 V, Vcc- = -5.25 V, VIO = 0
0.5
High-level input voltage
(strobe and gate inputs)
Low-level input voltage
(strobe and gate inputs)
3
0.8
3
Vcc+ = 4.75 V, Vcc_ = -4.75 V, 10H = -400 !LA
Low-level output voltage
3
Vcc+ = 4.75 V, Vcc- = -4.75 V, 10L = 16 mA
4
Vcc+ = 5.25 V, Vcc- = -5.25 V, V IH = 2.4V
4
Vcc+ = 5.25 V, Vcc- = -5.25 V, V IL = 0.4 V
5
Vcc+ = 5.25 V, Vcc- = -5.25 V
Low-level input current
IlL
(strobe and gate inputs)
Short-circuit output
10S(Y)
current into Y
Short-circuit output
2.4
/LA
!LA
V
3
High-level output voltage
(strobe and gate inputs)
75
2
VOL
High-level input current
V
±2.5
Differential-input bias current
V OH
IIH
MAX UNITS
TYP:j:
MIN
mV
voltage (see Note 3)
Common-mode input firing
TEST CONDITIONS
VREF = 15mV
4
V
V
0.4
V
40
!LA
-1.6
rnA
-3
-5
mA
-2.1
-3.5
rnA
0.25
-1
10S(Z)
current into Z
5
Vcc+ = 5.25 V, Vcc- = -5.25 V
Icc+
Icc_
Supply current from Vcc+
6
Vcc+ = 5.25 V, Vcc- = -5.25 V, TA = 25°C
28
40
mA
Supply current from Vcc-
6
Vcc+ - 5.25 V, Vcc- - -5.25 V, TA = 25°C
-14
-20
rnA
;All typical values are at Vcc+ = 5 V, Vcc_ = -5 V, TA = 25"C.
NOlES: 3. The differential-input threshold voltage (VT) Is defined as the d-c differential-input voltage (VIO) required to force the output of the sense amplWer to the
logic gate threshold voltage level.
4. Common-mode Input firing voltage is the minimum common-mode voltage that will exceed the dynamic range of the input at the specified conditions and
cause the logic output to switch. The specnled common-mode input signal is applied with a strobe-enable pulse present.
8-23
•
FAIRCHILD. 55/75S20. 55/75S24. 55/75S234
55/75820
DUAL-CHANNEL SENSE AMPLIFIER WITH COMPLEMENTARY OUTPUTS
SWITCHING CHARACTERISTICS: Vcc+ ~ 5 V, Vcc- ~ -5 V, T A ~ 25°C
PROPAGATION DELAY TIMES
SYMBOL
FROM INPUT
TEST
TO OUTPUT
FIGURE
Y
15
TEST CONDITIONS
MIN
tpLH(DY)
Al-A2 OR Bl-B2
CL~
15pF,
RL~
TYP
MAX
25
40
288fl
UNITS
ns
20
tpHL(DY)
tpLH(DZ)
Al-A2 OR Bl-B2
Z
15
CL~
STROBEAORB
Y
15
CL ~ 15 pF, RL
15pF,
RL~
30
288fl
tpHL(DZ)
tpLH(SY)
~
35
55
15
30
288fl
ns
ns
20
tpHL(SY)
tpLH(SZ)
STROBEAORB
Z
CL ~ 15pF, RL
15
tpHL(SZ)
tpLH(GY, Y)
GATE Gy
Y
CL
16
~
15 pF, RL
~
30
288fl
~
288 fl
35
55
15
25
tpHL(GY, Y)
10
tpLH(GY,Z)
15
GATE G y
Z
C L ~ 15 pF, FL
16
tpHL(GY, Z)
tpLH(GZ, Z)
tpHL(GZ,Z)
GATE G z
Z
"17
CL ~ 15 pF, RL
~
288 fl
~
20
30
15
288 fl
10
20
ns
ns
ns
ns
TYPICAL RECOVERY AND CYCLE TIMES: Vcc+ ~ 5 V, Vcc_ ~ -5 V, TA ~ 25°C
SYMBOL
torD
tore
tcyc(min)
CHARACTERISTICS
TEST CONDITIONS
Differential-input overload recovery time
Differential Input Pulse:
(see Note 5)
VID
Common-mode-input overload recovery time
Common-Mode Input Pulse:
(see Note 6)
VIC ~ ±2 V, tr ~ tf ~ 20 ns
~
Minimum cycle time
2 V, tr
~ tf ~
20 ns
MIN
TYP
MAX
UNITS
20
ns
20
ns
200
ns
NOTES: 5, Differential input overload recovery time is the time necessary for the device to recover from the specified differential-in put-overload signal prior to the
strobe-enable signal,
6. Common-mode-input overload recovery time is the time necessary for the device to recover from the specified common-mode-input overload signal prior to
the strobe-enable signal,
8-24
FAIRCHILD. 55/75520.55/75524.55/755234
55/75824
DUAL SENSE AMPLIFIER
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEW)
PACKAGE OUTLlNES6B 9B
PACKAGE CODES D P
FUNCTION TABLE
INPUTS
OUTPUT
A
S
W
H
H
H
L
X
L
X
L
L
NC[I~Ii!IVCC+
INPUTS ( I A
'I..:;1 ' 2 ) n . h 1-1
.:.:0 IS STROBE
lA2[l
~
lW OUTPUT
i
13
-VAEF[! ~
+ VREF [[
;DE:r' :ill 2W OUTPUT
2A 116
INPUTS·L.::,
(
DEFINITION OF LOGIC LEVELS
11' 2S STROBE
I
~.
~ Ne
2A2[l
H
INPUT
~ 2 GND
X
L
At
Irrelevant
S
Irrelevant
vcc-I:!
]]1
GND
positive logic: W- AS
NG-No internal connection
tA is a differential voltage (V IO ) between A 1 and A2. For these circuits,
VIO is considered positive regardless of which terminal is positive with
respect to the other.
ORDER INFORMATION
TYPE
PART NO.
55524
55S24DM
75S24
75S24DC
75524
75S24PC
ELECTRICAL CHARACTERISTICS: Vee+ = 5 V, Vee- = -5V, over recommended operating temperature range, unless otherwise noted.
SYMBOL
VT
V leF
CHARACTERISTICS
Differential-input threshold
110
V IH
V il
17.5
V REF = 40 mV
37.5
40
42.5
VREF = 40 mV, VI(S) = V IH
Common-Mode Input Pulse:
tr '" 15 ns, ~ '" 15 ns,
current
Differential-input offset
current
High-level input voltage
t"
Low-level input voltage
2
Vee+ = 5.25 V, Vee- = -5.25 V, V IO = 0
30
2
Vee+ = 5.25 V, Vee- = -5.25 V, V IO = 0
0.5
7
Vee+ = 4.75 V, Vee- = -4.75 V, 10H = -400 ~
Low-level output voltage
High-level input current
7
Vee+ = 4.75 V, Vee- = -4.75 V, 10l = 16 rnA
Vee+ - 5.25 V, Vee- - +5.25 V, V IH - 2.4 V
Vee+ = 5.25 V, Vee- = -5.25 V, V IH = 5.25 V
9
Low-level input current
(strobe inputs)
9
Vee+ = 5.25 V, Vee- = -5.25 V, V il = 0.4 V
los
Short-circuit output current
10
Vee+ = 5.25 V, Vee- = -5.25 V
Ice+
Supply current from Vec+
6
Vee+ = 5.25 V, Vee- = -5.25 V, TA = 25°C
lee-
Supply current from Vee-
6
Vee+ = 5.25 V, Vee- = -5.25 V, TA = 25°C
5 V, Vee-
~
-5 V, TA
~
75
2.4
/1- A
/1- A
V
0.8
High-level output voltage
(strobe inputs)
V
2
7
(strobe inputs)
~
±2.5
= 50 ns
7
(strobe inputs)
UNITS
mV
Common-mode input firing
voltage (see Note 4)
#-11 typical values are at Vee+
MAX
15
Val
III
TYP:j:
12.5
V OH
IIH
MIN
V REF = 15 mV
8
voltage (see Note 3)
Differential-input bias
liB
TEST CONDITIONS
TEST FIGURE
V
4
0.25
V
0.4
40
V
/1- A
rnA
-1
-2.1
25
-15
-1.6
rnA
-3.5
rnA
40
rnA
-20
rnA
25 "C.
NOTES: 3. The differential-inputthreshold voltage (VTl is defined as the doc differential-input voltage (Viol required to force the output ofthe sense amplifier to the logic
gate threshold voltage level.
4. Common-mode input firing voltage is the minimum common-mode voltage that will exceed the dynamic range of the input at the specified conditions and
cause the logic output to switch. The specifiEid common-mode input signal is applied with a strobe-enable pulse present.
8-25
I
FAIRCHILD. 55/75520.55/75524.55/755234
55/75824
SWITCHING CHARACTERISTICS: Vcc+ = 5 V, Vcc- = -5 V, TA = 25°C
PROPAGATION DELAY TIMES
SYMBOL
TEST
TEST CONDITIONS
MIN
FROM INPUT
TO OUTPUT
FIGURE
A1-A2
W
18
C L = 15pF, RL = 2880
STROBE
W
18
CL = 15pF, RL = 2880
tpLH(O)
tpHL(O)
tpLH(S)
tpHL(S)
MAX
TYP
25
40
20
15
30
20
UNITS
ns
ns
TYPICAL RECOVERY AND CYCLE TIMES: Vcc+ = 5 V, Vcc- = -5 V, TA = 25°C
SYMBOL
torD
torC
CHARACTERISTICS
TEST CONDITIONS
MIN
Differential-input overload recovery time
Differential Input Pulse:
(see Note 5)
VIO = 2V, t, =
Common-mode-input overload recovery time
Common-Mode Input Pulse:
(see Note 6)
VIC = ±2 V, t, =
It =
TYP
20
ns
200
ns
20 ns
Minimum cycle time
tcyc(min)
UNITS
ns
20 ns
It =
MAX
20
NOTES: 5. DifferentiaHnput overload recovery time is the time necessary for the device to recover from the specified differential-input·overload signal prior to the
strobe-enable signal.
6. Common-mode-input overload recovery time is the time necessary for the device to recover from the specified common-mode-input overload signal prior to
the strobe-enable signal.
558234/758234
DUAL SENSE AMPLIFIERS
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEW)
PACKAGE OUTLlNES6B 9B
PACKAGE CODES D P
FUNCTION TABLE
INPUTS
OUTPUT
A
S
W
H
H
L
L
X
H
X
L
H
NeO::~~vee
~ 15 STROBE
~ 1W OUTPUT
1A2 3
I
VREF[I
~2 GND
CAlC[
INPUTS
1[2
. VREF[[
j2A1II
INPUTS
DEFINITION OF LOGIC LEVELS
INPUT
H
L
X
At
VIO~VTmax
V ,O ";; VTmin
Irrelevant
V,,,;; VILmax
Irrelevant
S
VI
~
V ,H min
2[[
,2A2 7
Vee II
~
~
positive logic: W
P212W OUTPUT
1] 25
1]1
AS
NC-No internal connection
tA is a differential voltage (VID) between A1 and A2. For these circuits, VID is
considere<\ positive regardless of which terminal is positive with respect to the
other.
ORDER INFORMATION
PART NO.
TYPE
55S234DM
55S234
75S234PC
75S234
75S234DC
75S234
8-26
STROBE
121 NC
GND
FAIRCHILD. 55/75S20. 55/75S24. 55/75S234
558234/758234
ELECTRICAL CHARACTERISTICS: Vcc+
SYMBOL
CHARACTERISTICS
=5
= -5V,
17.5
= 40 mV
VREF = 40 mY, VI(S)
37.5
40
42.5
- VIH
Common-Mode Input Pulse:
Differential-input bias
current
Differential-input offset
current
High-level input voltage
VIL
15 ns,
'"
±2.5
2
Vcc+
= 5.25 V,
=
-5.25 V, VID
=0
30
2
Vcc+
= 5.25 V, Vcc- =
-5.25 V, VIO
=0
0.5
Vcc-
High-level output voltage
12
Vcc+
VOL
Low-level output voltage
12
Vcc+ - 4.75 V, Vcc- - -4.75 V, 10L - 16 mA
High-level input current
/l-A
V
Low-level input current
13
(strobe inputs)
= 4.75 V, Vcc- = -4.75 V, IOH -
-400 /l-A
2.4
Vcc+
= 5.25 V, Vcc- =
-5.25 V, VIH
= 5.25 V
Vcc+
= 5.25 V,
-5.25 V, VIL
= 0.4 V
= 5.25 V, Vcc- = -5.25 V
= 5.25 V, Vcc- = -5.25 V, TA = 25 'C
= 5.25 V, Vcc- = -5.25 V, TA = 25 'C
los
Short-circuit output current
14
Vcc+
Icc+
Icc_
Supply current from Vcc+
6
Vcc+
Supply current from Vcc-
6
Vcc+
Vcc-
=
0.8
V
0.4
V
4
V
0.25
40
/l-A
1
mA
- 1.6
mA
Vcc+ - 5.25 V, Vcc- - -5.25 V, V IH - 2.4 V
13
(strobe inputs)
/l-A
2
V OH
IlL
75
12
(strobe inputs)
IIH
V
Iw = 50 ns
12
(strobe inputs)
Low-level input voltage
UNITS
mV
t r '" 15 ns, t f
V IH
MAX
15
VREF
voltage (see Note 4)
110
TYP:j:
12.5
11
Common-mode input firing
liB
MIN
TEST CONDITIONS
= 15 mV
VREF
voltage (see Note 3)
V ICF
over recommended operating temperature range, unless otherwise noted.
TEST CIRCUIT
Differential-input threshold
VT
V, Vcer-
-1
-2.1
-3.5
rnA
25
40
rnA
-15
-20
rnA
;AII typical values are at vcc+ = 5 V, Vcc- = -5 V, TA = 25 'C.
NOTES: 3. The differeotial-inputthreshold voltage (VT) is defined as the d-c differential·input voltage (V IO) required to force the output of the sense amplifier to the logic
gate threshold voltage level.
4. Common-mode input firing voltage is the minimum common"mode vottage that will exceed the dynamic range of the input at the specified conditions and
cause the logic output to switch. The specified common-mode input Signal is applied with a strobe-enable pulse present.
SWITCHING CHARACTERISTICS: Vcc+
= 5 V, Vcc- =
-5 V, TA = 25 'C
PROPAGATION DELAY TIMES
SYMBOL
tpLH(O)
FROM INPUT
AI-A2
tpHL(O)
tpLH(S)
STROBE
tpHL(S)
TEST
TO OUTPUT
W
19
CL = 15pF, RL = 2880
W
19
C L = 15pF, RL = 2880
TYPICAL RECOVERY AND CYCLE TIMES: Vcc+ = 5 V, VccSYMBOL
torD
tore
Icyc(min)
TEST CONDITIONS
FIGURE
=
-5 V, TA
CHARACTERISTICS
TEST CONDITIONS
Differential Input Pulse:
Common-made-input overload recovery time
Common-Mode Input Pulse:
(see Note 6)
VIC
= 2 V, tr =
=
Minimum cycle time
TYP
MAX
25
25
40
25
15
30
UNITS
ns
ns
= 25 'C
Differential-input overload recovery time
(see Note 5)
VIO
MIN
tf
= 20 ns
±2 V, t, = ~
= 20 ns
MIN
TYP
20
MAX
UNITS
ns
20
ns
200
ns
NOTES: 5. Differential-input overload recovery time is the time necessary for the device to recover from the specified differential~input-overload Signal prior to the
strobe-enable signal.
6. Common-made-input overload recovery time is the time necessary for the device to recover from the specified common-mode input overload signal prior to
the strobe-enable signal.
8-27
II
FAI RCHI LD • 55/75820 • 55/75824 • 55/758234
75820/75824/758234
DUAL CORE MEMORY SENSE AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS
TYPICAL THRESHOLD
VOLTAGE AS A FUNCTION
OF SUPPLY VOLTAGE
TYPICAL THRESHOLD
AS A FUNCTION,VOLTAGE
OF TEMPERATURE
2.
r- V~eF ~ 20 ~V
> 2.
TA=2S C
e
I 2'
20r-~-r-'--r-'--r-.--r-'-~
VREF=15 mY
'9 - Vee + = 5V
VCC_ = -5Y
+--+---,c-+-+--+-I
o
w
"~
0
>
<>
a
l:
(/)
W
a:
l:
I-
I
~
'.~~-r-i---t-+--r--+--~+-~
22
21
,.,.
20
'2r-T--r-i--r-T--r-t--r-t-,
17
,.
,.
"r-T--r-i--r-T--t~-t--r-t-,
:1:4.50
:1:4.75
Vee -
::!:S.OO
±S.25
:5.50
SUPPLY VOLTAGE -
1~SL..-_-"20-.-"L-...L.-:.!..0.-1-",."L,--L-,-00L.,...J._,.J.0 '
±5.75
TEMPERATURE (OC)
V
LOGICAL 1 LEVEL INPUT
CURRENTVS.
INPUT VOLTAGE
LOGICAL 0 LEVEL INPUT
CURRENTVS.
INPUT VOLTAGE
l' -2.00
I--v~e, ~5vl
VCC2=
-1.75
~
r...- vlc1 ",Isv
-1.50
t--
S
-1.25
~
-sv
r- TZYA= 25°C
VCC2= -5V
TA=25°C
13
~ -1.00 I'---- r-..,
~ -0.75
V
./
V
~
"
~
~
c;
g
j
r-....
'\
~ -0.25
/
1
-0.50
.........
/
00
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
YIN-INPUT VOLTAGE -
°0
5.0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
VIN-INPUT VOLTAGE -
V
OUTPUT VOLTAGE VS.
DIFFERENTIAL INPUT
VOLTAGE
s.0r---,..-=Q~O::U.:.:TP;.U~T.::0i-F:..:7':::S2;:0..::O:.::NrlY:'-r-....,
O,smmm
00
:1:5 :e10 :15 :!:20 ±2S :t30 ±35 ±40
VINO-OIFFERENTIAL-INPUTVOL lAilE - mV
8-28
V
FAIRCHILD. 55/75820.55/75824. 55/75S234
75520/75524/755234
DUAL CORE MEMORY SENSE AMPLIFIERS
TYPICAL PERFORMANCE CHARACTERISTICS (Cont'd)
OUTPUT VOLTAGE VS.
DIFFERENTIAL-INPUT
VOLTAGE
5.0
I I
> ..0
YREF=15mV
VREF=25 mY
I
w 4.0
0
>
I-
"f!:
"0i0
>"
'.0
75924 AND 0 OUTPUT OF 75820 ONLY
4••
"~
LOGICAL 1 OUTPUT
VOLTAGE VS.
LOAD CURRENT
...
VREF",,35 mY
...
>
I
w
- I--
"~
8
1.5
-L
1.0
I
0.'
-I-
15 %20 ±25 :t30 ::t3S ±4O
45
t-
I vJe11.v I
Vee.=-'V
'Ii
40 ~TA=ooCT070oC
I
w
3'
~9
:
m
:I:
•
o
i-
/
V
/
/
.0
/
~
0.3
.
ALL TYPES
~ 0.2
~
100 200 300 400 500 600 700 800 900 1000
o
o
4
6
8
10
12
14 16
I
~
+v
Vee1 =5V
VREF
10~--~--~~--1----i--~
= 1SmV
V
~
i!:
1
"~ 1.0f--+--If--+--tL.-I
./
..:Ii
~
20
25
-~MF
30
35 40
45
50
°ci~O·'=O':--:-O.=O':--=O.':-,---f'.O;:----1.'O:-~'00
0
I
45
!ii
I:!
a:
1l
35
~
30
~
Z
r-~gg~:~5V
40
--
............ :-
25
20
~ 1•
1.0
I
IB
0 .•
Iii
0.6
~
0.4
~
0.3
z
Z
0
1
I:!
~
is
j
'i
o~
Z
~
0
o
10
20
30
40
..
60
20
~
70
lA,AMBIENT TEMPERATURE _ DC
v~e1=.J
rVee.= -.V
0.8
0.7
0.5
r--.....
--- r--
0.'
0.1
00
10
20
30
40
50
60
TA"AMBIENT TEMPERATURE _ DC
8-29
30
40
50
80
lA-AMBIENT TEMPERATURE - C
DIFFERENTIAL-INPUT
OFFSET CURRENT VS.
AMBIENT TEMPERATURE
DIFFERENTIAL-INPUT BIAS
CURRENTVS.
AMBIENT TEMPERATURE
'i
10
PRR·PULSE REPETITION RATE - MHz
VREf"REFERENCE VOLTAGE - mY
..
I
MF
-Vee.= -5V
:J:
/
10 15
20
COMMON MODE FIRING
VOLTAGE VS.
AMBIENT TEMPERATURE
o
5
18
'SINK,SINK CURRENT - rnA
o
>
~
2
!A
NORMALIZED THRESHOLD
VOLTAGEVS.
PULSE REPETITION RATE
""
........ ~
I---- f-""
9is' o.1
'LOAD,LOAD CURRENT -
10
o
o
!;
O.S
THRESHOLD VOLTAGE VS.
REFERENCE
VOLTAGE
0.4
g
.......
ALL TYPES
o
o
VCC1=5V
YCC2= -6V
TA=25°C
o
VINO,DIFFERENTIAL·INPUT VOLTAGE - mV
..
~
..............
YCC2=-5V
TA=25°C
0 .•
w
~ 2.0
ILOAD= -400,..,
:t10
3.0
r--.
Ve~,=Jv
"0
TA=j'e I
:5
I-
>
I
l-
I I
o
o
3.'
"'N.
.." ...
=5V
1.• Vee1
YCC2= -5V
1.0
4.0
0
>
I I
'.0
4..
LOGICAL 0 OUTPUT
VOLTAGEVS.
SINK CURRENT
70
70
FAIRCHILD. 55/75S20. 55/75S24. 55/75S234
CHARACTERISTICS MEASUREMENT INFORMATION
DC TEST CIRCUITSt
V,O
~
SEE
TEST
TABLE
ANO
OTEA
I
I
VREF C > - - - - - - {
Z
j5 ________ "
I
L __________
I
I
TEST TABLE
CIRCUIT
TYPE
55/75S20
INPUTS
OUTPUTY
V,O
VREF
Vo
10H
Al-A2 or 81-82
Al-A2 or 81-82
15mV
15mV
.;12.5 mV
<>17.5 mV
.;OA V
Al-A2 or 81-82
Al-A2 or 81-82
40mV
40mV
.;37.5mV
.;OAV
<>42.5 mV
<>2A V
<>2.4 V
OUTPUTZ
10L
Vo
16mA
<>2A V
.;OA V
400fJ.A
16mA
<>2A V
- 400 fJ.A
- 400 fJ.A
10H
16mA
.;OA V
-400fJ.A
NOTE A: Each pair of differential inputs is tested separately with the other pair grounded.
Fig. 1
75820 VT
"(1)
---+
SEE
~ AN~~~SB
NOTES: A. Each preamplifier is tested separately. Inputs not under test are grounded.
B. liB ~ "(1) or "(2) ()imit applies to each); ',0 ~ ' 1(1) - "(2); "(1) and "(2) are the currents into the two inputs of the pair under test.
PIN CONNECTIONS (OTHER THAN THOSE SHOWN ABOVE)
CIRCUIT TYPES
55/75S20
APPLY Vcc+
Gy,G z
APPLYGND
G @
@, (jJ)
55/75S24
55/75S234
Fig. 2
LEAVE OPEN
Y,Z
SA,SB
@
@
1S, 2S, GND 2
1W,2W
@ (jJ) @
G
1S,2S, GND2
1W,2W
@ 1])
G
liB. 1'0
tArrows indicate actual direction of current flow. Current into a terminal is a positive value.
8-30
1J
@
@
10L
16mA
FAI RCHI LD • 55/75S20 • 55/75S24. 55/75S234
CHARACTERISTICS MEASUREMENT INFORMATION
DC TEST CIRCUITSt (Cont'd)
~
VID=40 mV
1{
SEE
FUNCTION
TABLE
TEST
PER
FUNCTION
TABLE
H=40 mV
L=GND
~
I
I
jf_______ j
+!,.OL
ij~'
I
c __________
IIH
VIHF.[iSEE
YIL
TEST
TABLE
IlL
VREF ~
15 mY
VOL
Y01H
l~1~I
-=-
-=-
~§~~~l=l-l
•
I
o---H§>
~--- -------r-------
!
J
TEST TABLE
TEST
IIH at STROBE SA
I'H at STROBE S8
IIH at GATE Gy
IIH at GATE GG
IlL at STROBE SA
I'L at STROBE S8
IlL at GATE Gy
I'L at GATE Gz
INPUT
A1
GND
GND
VIO
GND
V,O
GND
GND
GND
INPUT
B1
GND
GND
STROBE
STROBE
SA
V,H
VIL
V,H
V,L
VIL
V,L
V,L
VIL
S8
V,L
VIH
V,H
VIL
V,L
V,L
VIL
V,L
VIO
GND
GND
VIO
GND
GND
Fig. 4
IIH' IlL
tArrows indicate actual direction of current flow. Current into a terminal is a positive value.
8-31
GATE
Gy
VIL
V,L
V,H
VIH
V,L
V,L
VIL
V,L
GATE
GZ
V,L
VIL
VIL
V,H
V,L
V,L
YIL
VIL
FAIRCHILD. 55/75S20. 55/75S24. 55/75S234
CHARACTERISTICS MEASUREMENT INFORMATION
DC TEST CIRCUITSt (Cont'd)
VREF
=
15 mV
L ----
------1 --------
I
I
I
I
J
~'OS(Z) ~'OS(Y)
los
Fig. 5
NOTE A: When testing iOS(Y)' Pin to is open; when testing 'OS(Z)' Pin to is grounded.
TEST
POINTS
Vcc_ (OPEN)
STROBES
~~~
'cc-l1_~t~~____
i :
Vcc+
PIN CONNECTIONS (OTHER THAN THOSE SHOWN ABOVE)
_____k1J cc+
1
CIRCUIT TYPE8
:
55/75820
I
I
I
I
I
55/75824
=
15mV
18,28, GND 2
55/758234
:
~--------J
Icc+> Icc-
1
SEE
FUNCTION
TABLE
H=40 mV
L=GND
I
~
VREF
=
15 mV
@
@ @
Fig. 6
VID=40 mV
@ @ @
18,28, GND 2
I
I
:
ALL CIRCUIT TYPES
L __________
~
I
I
VREF
APPLY GND
Gy, Gz , 8 A , 8 8
---Hi
L ____ - - ____
1_'___
tArrows indicate actual direction of current flow. Current into a terminal is a positive value.
8-32
I
I
,I
J
@ @
@
LEAVE OPEN
Y,Z
@
@
1W,2W
~
@
1W,2W
~
@
FAIRCHILD. 55/75S20. 55/75S24. 55/75S234
CHARACTERISTICS MEASUREMENT INFORMATION
DC TEST CIRCUITSt (Cont'd)
TEST TABLE
CIRCUIT
TYPE
75S24
INPUTS
OUTPUT
VREF
V,o
A1-A2
A1-A2
15 mV
15 mV
,,;12.5 mV
A1-A2
40mV
;;,17.5 mV
,,;37.5mV
A1-A2
40mV
;;,42.5 mV
Vo
,,;0.4 V
;;,2.4 V
IOH
IOL
16mA
-400JJ.A
,,;0.4 V
16mA
;;,2.4 V
-400,...A
NOTE A: Each pair of differential inputs is tested separately with its corresponding output.
Fig. 8
VID=40
m~iE~~
'-=-L1<"-'-....
TABLE
I
75524, VT
>-_.L~----~OPEN
,'2W
,
I
VREF = 20 mV-----+-<,
I
L----------Jr-~--J
TEST TABLE
INPUT 1A1
INPUT 2A1
STROBE 1S
I'H at STROBE 1S
GND
GND
V'H
V'L
I'H at STROBE 2S
GND
GND
I'L at STROBE 1S
IlL at STROBE 2S
V,o
GND
GND
V'L
V'L
VIL
V'H
VIL
VIL
TEST
V,o
tArrows indicate actual direction of current flow. Current into a terminal is a positive value.
8-33
STROBE2S
FAIRCHILD. 55/75S20. 55/75S24. 55/75S234
CHARACTERISTICS MEASUREMENT INFORMATION
DC TE5T CIRCUIT5t (Cont'd)
VIO=40 mV-.~--v
,
2W
f f-'
I
VREF= 1SmV - - C ' , " " ,
I
I
L
- - - - - - - - - - -
10S~
~IOS
75524, los
Fig. 10
"l
{
TEST
TABLE
~IOl
;),IOH
I}1! 1I
VOH
CIRCUIT
TYPE
INPUTS
A1-A2
55175234
15mV
OUTPUTS
V 1D
VREF
,;;;12.5 mV
55/7S234
Va
?<2.4 V
A1-A2
15mV
?<17.5 mV
,;;;0.4 V
A1-A2
40mV
,;;;37.5 mV
?<2.4 V
A1-A2
40mV
?<42.S mV
';;;0.4 V
IOH
-400/LA
IOl
16mA
-400/LA
16mA
NOTE A: Each pair of differential inputs is tested separately with its corresponding output.
Fig. 11
Fig. 12
755234, VT
75S234, VIH, Vll, IOH, Val
tArrows indicate actual direction of current flow. Current into a terminal is a positive value.
8-34
II
FAIRCHILD. 55/75S20. 55/75S24. 55/75S234
CHARACTERISTICS MEASUREMENT INFORMATION
DC TEST CIRCUITSt (Cont'd)
VREF
=
15 mV - - - t - { !
TEST TABLE
TEST
INPUT 1A1
INPUT 2A1
STROBE 1S
STROBE2S
I'H at STROBE 1S
GND
GND
V ,H
I'H at STROBE 2S
GND
GND
V,L
V,L
V ,H
I'L at STROBE 1S
V ,D
GND
V,L
I'L at STROBE 2S
GND
V,D
V,L
Fig. 13
V,L
V ,L
755234, I'H' I'L
I
tArrows indicate actual direction of current flow. Current into a terminal is a positive value.
1A1
,,
lA2
2Al.Lj"'-L~".
2W'
2A2
VREF
=
15 mV
75S234
L __
,,
----------rf-' IOS~
Fig. 14
755234, los
8-35
~OS
FAIRCHILD. 55/75820.55/75824.55/758234
CHARACTERISTICS MEASUREMENT INFORMATION
SWITCHING CHARACTERISTICS
DIFFERENTIAL
INPUT
288Q
288Q
OUTPUT
Y
OUTPUT
Z
L'*'
Cl =15PF
(See Note C)
TEST CIRCUIT
T~
DIFFERENTIAL
INPUT PULSE
STROBE
!~PUT ~ 5V
PUl~L'
..
~ IWI
~20 mV
_
1\0 mV
20 mV
________J
-J
1
I
1
I
1
I
~--------~f
\
~
~ .-
15V
f, 1.5V
1:\
!.----i-
-----.j '------~H!-----.J
Iw2
I
IplH(Dy) -+11 F ; \--l
f . -I+I
I
!
OUTPUT Y
IpHl(DY)
IplH(SY)
I
1.5V:
Iw2
I-- IWI ~
-...J
-
-
- - 3.5V
I--
~---- OV
I
-o-l I-- IpHl(SY)
I~,---VOH
I
1.5V
-
,.5V
1
1.5V
'---------">~ 'rS- - - - - - '
I
I
\.5V
'-----VOl
I
--------~I~
~--~~5r---------~
1~1.5V
OUTPUT Z
IpHl(DZ)
-..l
!.=
I
--1
VOH
1.5V
:
f--
IplH(DZ)
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: Zo ~ 50 n, tr ~ 15 ± 5 ns, ~ ~ 15 ± 5 ns, twl = 100 ns, tw2 ~ 300 ns, and PRR
B. The strobe input pulse is applied to Strobe SA when inputs Al-A2 are being tested and to Strobe S8 when inputs Bl-B2 are being tested.
C. Cl includes probe and jig capacitance.
Fig. 15
55/75S20 PROPAGATION DELAY TIMES FROM DIFFERENTIAL AND STROBE INPUTS
8-36
= 1 MHz.
FAIRCHILD. 55/75820.55/75824.55/758234
CHARACTERISTICS MEASUREMENT INFORMATION
SWITCHING CHARACTERISTICS (Cont'd)
2882
2882
OUTPUT
Y
:!r-----<~
-::r:-
OUTPUT
z
CL= 15pF
(See Nole B)~
VREF=20 ;...m~v_+--+_I--{
50Q 502 502 502
GATE Gy
INPUT
TEST CIRCUIT
I~
I
'\:~,u
GATE Gy
INPUT
__
-----.~
-------. t--- Iw - - t
~
I
PHL(GY,Y)
:
'-,I
I
I
:
OUTPUT
Y
I
----1
i
I
VOH
I
: !.5V
:.5V
I
IpLH(GY,Z)
OU~_PU_T
__________
OV
i'o- IpLH(GY,y)
i-l
-
-
IpHL(GY,Z)
.J~"
-
-
-
-
-
-
-
VOL
I+-
' ( : - - ----VOH
....- - - - - - V O L
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo
B. CL includes probe andjig capacitance.
Fig. 16
= 50 n, t, =
15 ± 5 ns, It = 15 ± 5ns,
t,.
= 100 ns, and PRR
55175520 PROPAGATION DELAY TIMES FROM GATE Gy
8-37
= 1 MHz.
FAIRCHILD. 55/75520.55/75524.55/755234
CHARACTERISTICS MEASUREMENT INFORMATION
SWITCHING CHARACTERISTICS (Cont'd)
16
- - - - - -- -- 1
288Q
I
I
288Q
:I>-------1~ OU~UT
50Q 50Q 50Q 50Q
TEST CIRCUIT
\:-- --------3.5V
j~
GATE GZ
INPUT
------'
tpLH(GZ,Z)
~ tw ~ ' - - - - - - - - - - - - - ov
-...j
r-
--l
I+-
tpHL(GZ,Z)
\\..5V___---'!~
OUTPUT
Z
__
n
____
:~
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo
B. CL includes probe and jig capacitance.
Fig.17
= 5011, t, =
15 ± 5 ns, tf
=
15 ± 5 ns, tw
=
100 ns, and PRR
55/75S20 PROPAGATION DELAY TIMES FROM GATE Gz
8-38
=
1 MHz.
FAI RCHI LD • 55/75520 • 55/75524.55/755234
CHARACTERISTICS MEASUREMENT INFORMATION
SWITCHING CHARACTERISTICS (Cont'd)
DIFFERENTIAL
INPUT
2882
>---;::=:[:J~___pI1~W
14
I
,
I
I
288Q
OUTPUT
1W
;r
Cl=15 pF
>--j----rlf----L.d12 (500 NolO C)
12W
(;;O=N~I:~)
I
I
VREF=2O m V - - - + - {
*'
OUTPUT
2W
I
2S--1-~J
iI
11
-=
v
I
TEST CIRCUIT
DIFFERENTIAL
INPUT_P_U_LS_E_ _....{
~•
20 mV ~\..2O_m_V_ _~1
-I
r---1i
~IW1~
\:~V I
~
I
I.---tI
1w2
L
IL
1.5V
1.5V
+---l '---;I~_ _-' I--
--l
r--
IplH(D) ---..,
OUTPUT
I
t-- IpHL(D)
I
I
-.J
1w1
I
-
PlH(S) "
OV
-
I~~-
1.5V
------3.5V
-:\1.5V
--l '------_ 0 V
-.f
r--
IpHL(S)
~ .~:-
, - 1.5V
-------'
T
\1.5V
n
- - 40mV
--.f
1w2
I
I
-
20 mV
1.5V
-----VOH
~.5V
- - - - - - VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics:Zo = 500,1,. = 15 ± 5 ns, Ij = 15 ± 5ns, 1w1 = 100 ns, 1w2 = 300 ns, and PRR = 1 MHz.
B. The strobe input pulse is applied to Strobe lS when inpOis lAl-1A2 are being tested and to Strobe 2S when inputs 2A1-2A2 are being tested.
C. Cl includes probe and jig capacitance.
Fig. 18
55175824 PROPAGATION DELAY TIMES
8-39
FAIRCHILD. 55/75820.55/75824.55/758234
CHARACTERISTICS MEASUREMENT INFORMATION
SWITCHING CHARACTERISTICS (Cont'd)
DIFFERENTIAL
INPUT
288Q
l
I
lW
2882
OUTPUT
lW
VREF=20 mY---'l'---{i
TEST CIRCUIT
\ : O : V-
-
I.
+---..t '--...;>/'-------. I.-
tw2
tpHL(D)
I
--j
OUTPUT
8'~V-
I.SV
r-
-..j
t-- tpLH(D)
I
1I ,.sy
~
~'.SV
tpHL(S)
I '
~
-I .
twl
--l
I
---.,.--
l\
-
40 mY
OV
--001
tw2
I
-
-
-
-
---3.SV
0V
~ tpLH(S)
I ,._ _ _ _ _ V
\:JI
I.SV
OH
I.SV
_ _ _ _ _ _ _ _ VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: Zout = 50 n, t,. = 15 ± 5 ns, It = 15 ± 5 ns, twl = 100 ns, Iw2 = 300 ns, and PRR = 1 MHz.
B. The strobe input pulse is applied to Strobe 1S when inputs 1AHA2 are being tested and to Strobe 2S when inputs 2A1·2A2 are being tested.
C. CL includes probe and jig capacitance.
Fi9·19
55/755234 PROPAGATION DELAY TIMES
8-40
5520/7520 SERIES
CORE MEMORY SENSE AMPLIFIERS
FAIRCHILD LINEAR INTEGRATED CIRCU ITS
GENERAL DESCRIPTION - The 5520/7520 Series Dual Memory Sense Amplifiers are designed for use
in high speed core memory systems. These sense amplifiers detect the mV memory signals and transform
them into logic levels compatible with TTL and DTL circuits. Independent strobes for each channel provide the capability for performing time discrimination, resulting in the detection of the input signal when
the signal to noise ratio is at maximum. A common reference amplifier simultaneously sets the threshold of
each sense amplifier, and the r.eference amplifier and sense amplifier are compensated to reduce the effect
of power supply voltage or temperature variation. All gate inputs are compatible with TTL and DTL
circu its.
•
•
•
•
•
HIGH SPEED AND FAST RECOVERY TIME
NARROW THRESHOLD UNCERTAINTY REGION
ADJUSTABLE INPUT THRESHOLD VOLTAGE
TTL COMPATIBLE
VARIOUS LOGIC CONFIGURATIONS
COMPARISON CHART
The 7520 series of sense amplifiers provides a wide number of options which allow this device to be adapted
to a variety of special applications. Differences between the various sense amplifier devices are summarized
in the table below. 55XX numbers refer to military grade devices, while the corresponding 75XX number
refers to the identical circuit specified for commercial grade. Even numbered devices refer to sense amplifiers specified for a tight threshold voltage distribution.
DEVICE
DECOUPLING
CAPACITOR
AMPLIFIER
TEST POINTS
OUTPUT
STAGE
Yes
5528/7528
External
55232/75232
Internal
I nverted with
Open Collector
55238/75238
Internal
Inverted
Yes
FUNCTIONAL BLOCK DIAGRAM
STROBE 1
OUT 1
IN 1
REFERENCE VOLTAGE
IN 2
OUT 2
sTflOBE 2
8-41
I
FAIRCHILD • 5520/7520 SERIES
5520/7520 SERIES ABSOLUTE MAXIMUM RATINGS
Supply Voltages
±7.0 V
Differential I nput Voltage
±5.0 V
Logic I nput Voltage
±5.5 V
Strobe and Gate Input Voltage
+5.0 V
Off State Output Voltage
+5.5 V
Operating Ambient Temperature Range
5520 Series
_55° C to +125° C
7520 Series
O°C to +70°C
Storage Temperature Range
-65°C to +150°C
Pin Temperature
Hermetic DIP, (Soldering, 60 s)
+300°C
Molded DIP (Soldering, 10 s)
+260°C
I nternal Power Dissipation (Note 1 )
730mW
5520/7520 SERIES RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNITS
VCC+
4.75
5.0
5.25
V
VCC-
-4.75
-5.0
-5.25
15
VREF
V
40
mV
ELECTRICAL CHARACTERISTICS
All electrical characteristics and test conditions for the 5520 devices are identical to those of the corresponding 7520 device, with the exception
of the Differential Input Threshold Voltage and Differential Input Bias Circuit. Limits for these parameters are detailed in the table below. All
limits which apply to the 7520 circuits for temperatures of O°C to 70° C apply to the 5520 circuits for t~e range of -55°C to +125°C.
All ac switching characteristics are guaranteed at VCC+ = 5.0 V, VCC- = -5.0 V and TA = 25°C.
For details of the full electrical characteristics and test circuitry please refer to the corresponding 7520 data.
5520 SERIES VTH AND liB LIMITS
EVEN NUMBERED
ODD NUMBERED
5520 SERIES
5520 SERIES
TEST CONDITIONS
SYMBOL CHARACTERISTICS
DEVICES
MIN
TA = _55°C to DoC
V REF = 15 rnV
TA = DoC to 70°C
Differential Input
VT
and 70°C to 125°C
TA = _55°C to O°C
Threshold Voltage
V REF =40mV
and 70°C to 125°C
TA = O°C to 70°C
liB
Differential Input
VCC+ = 5.25 V, VCC- = -5.25 V,
TA = _55°C to O°C
Bias Current
VID=O
TA = O°C to 125°C
TYP
DEVICES
MAX
MIN
TYP
MAX
10
15
20
8.0
15
22
11
15
19
8.0
15
22
35
40
45
33
40
47
36
40
44
33
40
100
30
75
UNITS
mV
47
100
30
75
!J.A
NOTES,
1. Derate Hermetic DIP and Molded DIP above 60°C at 8.3 mW/oC.
2. The differential input threshold voltage (VT) is defined as the dc differential input voltage (VID) required to force the output of the sense
amplifier to the logic-gate threshold voltage level.
8-42
FAIRCHILD· 5520/7520 SERIES
7528
SENSE AMPLIFIERS
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 68 98
PACKAGE CODES D P
EXT·~'~g'6
CAP
VCC+
INA1~~P-'iTPA
3
ht
IN A2
~
t-
g
I
's~:
>VREF
r~" n
1r
~
IN 81
C
OUT A
g
I
7
INB2
STROBE A
~
~
I
-VREF
OUTB
ORDER INFORMATION
TYPE
PART NO.
5528
5528DM
7528
7528DC
7528
7528PC
STROBE B
10
~
~
TPS
P
8
9
VCC_ [ :
GND
DEFINITION OF LOGIC LEVELS
FUNCTION TABLE
INPUTS
INPUT
OUTPUT
H
x
l
S
A
Irrelevant
H
H
H
Irrelevant
L
X
l
X
L
l
A
tA
is a differential voltage (Vio' between A1 and A2. For
these circuits, VIO is considered positive regardless of which
terminal is positive with respect to the other.
ELECTRICAL CHARACTERISTICS: VCC+ = 5.0 V, VCC- = -5.0 V, TA = DoC to 70°C (unless otherwise specified)
SYM80l
VT
CHARACTERISTICS
Differential Input Threshold Voltage
(See Note 4)
MIN
TYP+
V REF = 15 mV
11
15
19
V REF =40mV
36
40
44
TEST CONDITIONS
None
V REF = 40 mV, Vt(S) - V IH
Common-Mode Input Pulse:
±2.5
liB
Differential Input Bias Current
2
VCC+ = 5.25 V, VCC- = -5.25 V, VID = 0
30
Differential Input Offset Current
2
VCC+ = 5.25 V, VCC- = -5.25 V, VID = 0
0.5
Input HIGH Voltage
Input lOW Voltage
(Strobe Inputs)
3
VOH
Output HIGH Voltage
3
VCC+ - 4.75 V, VCC- = -4.75 V, 10H - -400 IlA
VOL
Output lOW Voltage
3
VCC+ = 4.75 V, VCC- = -4.75 V, 10l - 16 mA
Input HIGH Current
4
(Strobe Inputs)
I nput LOW Current
IlL
(Strobe Inputs)
75
2.4
!J.A
!J.A
2.0
3
(Strobe Inputs)
VIL
IIH
V
t r " 15 ns, tf" 15 ns, tw = 50 ns
110
VIH
MAX UNITS
mV
(See Note 3)
Common Mode Input Firing Voltage
VICF
TEST
FIGURE
V
0.8
V
0.4
V
V
4.0
0.25
VCC+ - 5.25 V, VCC- - -5.25 V, VIH - 2.4 V
40
!J.A
VCC+ = 5.25 V, VCC- = -5.25 V, VIH = 5.25 V
1.0
mA
-1.6
mA
4
VCC+ = 5.25 V, VCC- = -5.25 V, Vil = 0.4 V
-1.0
-2.1
lOS
ShortwCircuit Output Current
5
VCC+ = 5.25 V, VCC- = -5.25 V
-3.5
mA
ICC+
Supply Current from V CC+
6
VCC+ = 5.25 V, VCC- = -5.25 V, TA = 25°C
25
40
mA
ICC-
Supply Current from V CC-
6
VCC+ - 5.25 V, VCC- - -5.25 V, TA - 25°C
-15
-20
mA
:tAli typical values are at VCC+
=
5.0 V, VCC- = -5.0 V, T A = 25°C.
NOTES:
3. The differential input threshold voltage (VT) is defined as the de differential input voltage (VID) required to force the output of the sense
amplifier to the logic gate threshold voltage level.
4. Common mode input firing voltage is the minimum common mode voltage that will exceed the dynamic range of the input at the specified
conditions and cause the logic output to switch. The specified common mode input signal is applied with a strobe enable pulse present.
8-43
I
FAIRCHILD • 5520/7520 SERIES
7528
SENSE AMPLIFIERS
AC CHARACTERISTICS: VCC+
= 5.0 V. VCC- = -5.0 V.
PROPAGATION DELAY TIMES
SYMBOL
tPLH(D)
tpHL(D)
tPHL(D)
FIGURE
A1-A2
A
7
CL
= 15pF. RL = 288.11
STROBE
A
7
CL
= 15pF. RL = 288.11
SYMBOL
tcyc(MIN)
TEST CONDITIONS
TO OUTPUT
TYPICAL RECOVERY AND CYCLE TIMES: VCC+
torC
= 25°C
FROM INPUT
tPHL(S)
torD
TA
TEST
= 5.0 V.
VCC-
MIN
TYP
MAX
25
40
20
15
30
20
UNITS
ns
ns
= -5.0 V. TA = 25°C
CHARACTER ISTICS
TEST CONDITIONS
Differential I nput Overload Recovery Time
Differential Input Pulse:
(See Note 5)
Common Mode Input Overload Recovery Time
VID = 2.0 V. tf = 20 ns
Common Mode Input Pulse:
(See Note 6)
V'C
= ±2.0 V.
tr
MIN
= tf = 20 ns
Minimum Cycle Time
TYP
MAX
UNITS
20
ns
20
ns
200
ns
NOTES:
5. Differential input overload recovery time is the time necessary for the device to recover from the specified differential input overload signal
prior to the strobe enable signal.
6.
Common mode input overload recovery time is the time necessary for the device to recover from the specified common mode input
overload signal prior to the strobe enable signal.
7528
EQUIVALENT CIRCUIT
Cext
~
>~
TEST POI NT 1P
J
11
.J?
~~
'"
---<>
kf
aUT A
r-K
STROBE A
'--
v'
INPUT Al
>-
INPUT A2
1
JL
J7
J
INPUT 81
INPUT 82
Vcc_
TEST POINT 2P
STROBE B
~
>-
I
If'-~~
OUTB
GND
"'l
8-44
FAIRCHILD • 5520/7520 SERIES
75232
SENSE AMPLIFIERS
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 6B 9B
PACKAGE CODES D P
1~16
NC
r-
n
vcc+
~
.~
IN Al
~~~
STROBE A
IN A2
r-
OUT A
1
'7
-VREFr;~
+VREF
IN Bl
~
ORDER INFORMATION
TYPE
PART NO.
55232
75232
75232
RGND2
¢:;,JE:+
I
~ OUT B
C
I
7
IN 62
n
P
STROBE B
10
~
~ NC
P
Vcc-t
GNDl
FUNCTION TABLE
INPUTS
A
S
55232DM
75232DC
75232PC
DEFINITION OF LOGIC LEVELS
OUTPUT
INPUT
H
X
L
A
Irrelevant
Irrelevant
H
H
L
L
X
H
X
L
H
tA
is a differential voltage (VID) between A1 and A2. For
these circuits, VI D is considered positive regardless of which
terminal is positive with respect to the other.
ELECTRICAL CHARACTERISTICS: VCC+ = 5.0 V. VCC- = -5.0 V. TA = O°C to 70°C (unless otherwise specified)
SYMBOL
TEST
CHARACTERISTICS
Differential Input Threshold Voltage
VT
Common Mode Input Firing Voltage
(See Note 4)
Typt
V REF =15mV
11
15
19
V REF = 40 mV
36
40
44
None
V REF = 40 mY. VI(S) = V IH
Common-Mode Input Pulse:
±2.5
liB
Differential I nput Bias Current
2
VCC+ = 5.25 V, VCC- = -5.25 V, VID = 0
30
Differential I nput Offset Current
2
VCC+ = 5.25 V, VCC- = -5.25 V, VID = 0
0.5
Input HIGH Voltage
(Strobe Inputs)
Input LOW Voltage
VIL
(Strobe Inputs)
0.8
V
IlA
Output HIGH CUrrent
3
VCC+ = 4.75 V, VCC- = -4.75 V, VOH = 5.25 V
3
VCC+ = 4.75 V, VCC- = -4.75 V, 10L = 16 mA
Input LOW Current
IlL
(Strobe Inputs)
V
250
Output LOW Voltage
(Strobe Inputs)
IlA
IlA
3
IOH
IIH
75
2.0
3
VOL
Input HIGH Current
V
tr ,;; 15 ns, tf ,;; 15 ns, tw = 50 ns
110
VIH
MAX UNITS
mV
(See Note 3)
VICF
MIN
TEST CONDITIONS
FIGURE
4
4
0.25
VCC+ = 5.25 V, VCC- = -5.25 V, VIH = 2.4 V
V
40
IlA
1.0
mA
-1.0
-1.6
mA
VCC+ = 5.25 V, VCC- = -5.25 V, VIH = 5.25 V
VCC+ = 5.25 \/, VCC- = -5.25 V, VI L = 0.4 V
0.4
ICC+
Supply Current from VCC+
6
VCC+ = 5.25 V, VCC- = -5.25 V, TA = 25°C
25
40
mA
ICC-
Supply Current from VCC-
6
VCC+ - 5.25 V, VCC- - -5.25 V, TA - 25°C
-15
20
mA
fAil typical values are at VCC+ = 5.0 V, VCC- = -5.0 V, T A
= 25°C.
NOTES.
3.
4.
The differential input threshold voltage (VT) is defined as the dc differential input voltage (VIO) required to force the output of the sense
amplifier to the logic gate threshold voltage level.
Common mode input firing voltage is the minimum common mode voltage that will exceed the dynamic range of the input at the specified
conditions and cause the logic output to switch. The specified common mode input signal is applied with a strobe enable pulse present.
8-45
I
FAIRCHILD • 5520/7520 SERIES
75232
SENSE AMPLIFIERS
AC CHARACTERISTICS' VCC+ = 5 0 V VCC
-- - 50 V
PROPAGATION DELAY TIMES
SYMBOL
tPLH(D)
TO OUTPUT
FIGURE
Al-A2
A
7
CL
= 15pF. RL = 230n
STROBE
A
7
CL
= 15 pF. RL = 230n
tpHL(S)
TYPICAL RECOVERY AND CYCLE TIMES' VCC+ = 5 0 V VCC
SYMBOL
tarO
torC
tcyc(MIN)
MIN
TEST CONDITIONS
FROM INPUT
tpHL(D)
tPHL(D)
T A - 25"C
TEST
-
- 50 V
MAX
25
40
25
25
15
30
TYP
MAX
UNITS
ns
ns
TA - 25°C
MIN
TEST CONDITIONS
CHARACTER ISTICS
TYP
Differential I nput Overload Recovery Time
Differential Input Pulse:
(See Note 5)
VID = 2.0 V. tr
Common Mode Input Overload Recovery Time
Common Mode I nput Pulse:
(See Note 6)
VIC
= '2.0
Minimum Cycle Time
20
ns
20
ns
200
ns
= tf = 20 ns
V. tr
= tf = 20
UNITS
ns
NOTES:
5.
6.
Differential input overload recovery time is the time necessary for the device to recover from the specified differential input overload signal
prior to the strobe enable signal.
Common mode input overload r"covary time is the time necessary for the device to recover from the specified common mode input
overload sig[lal prior to the strobe enable signal.
75232
EQUIVALENT CIRCUIT
vcc+o-------------------~r_----~--~----~
VREF +
VREF~
OUT A
STROBE A
INPUTAl
INPUT A2
OUT 8
INPUT 81
......-o
'-~'--+--
INPUT 82
Vcc- o-----t:::~::::::~==______1_t'
~ROBEBo-------------------------------~----~
8-46
ONO 2
FAIRCHILD • 5520/7520 SERIES
75238
SENSE AMPLIFIERS
CONNECTION DIAGRAM
16-PIN DIP
(TOP VIEW)
PACKAGE OUTLINES 6B 9B
PACKAGE CODES D P
EXTr~t'.!i
CAP
~
~
VCC+
H
STROBE A
INA1~~~TPA
r
.L:i
IN A2
-VREF
+VREF
IN Bl
~
I
Q
~~+1 ~
~~
C
n
I
~
Q
7
INB2
~
OUTB
STROBE B
TPS
P
8
ORDER INFORMATION
TYPE
PART NO.
55238
55238DM
75238
75238DC
75238
75238PC
OUT A
9
VCC- [:
GND
DEFINITION OF LOGIC LEVELS
FUNCTION TABLE
INPUTS
A
OUTPUT
INPUT
H
A
At
VID;;'VT(MAX)
S
S
H
H
L
L
X
H
X
L
H
x
L
Irrelevant
VID';; VT(MIN)
Irrelevant
tA
is a differential voltage (VIO) between A1 and A2. For
these circuits, V'D is considered positive regardless of which
terminal is positive with respect to the other.
ELECTRICAL CHARACTERISTICS: VCC+: 5.0 V, VCC-: -5.0 V, TA: O°C to 70°C (unless otherwise specified)
TEST
SYMBOL
CHARACTERISTICS
Differential Input Threshold Voltage
VT
(See Note 4)
Typt
V REF : 15 mV
11
15
19
VREF~40mV
36
40
44
MAX UNITS
mV
(See Note 3)
Common Mode Input Firing Voltage
VICF
MIN
TEST CONDITIONS
FIGURE
VREF: 40 mV, VI(S) : VIH
None
Common-Mode Input Pulse:
V
±2.5
tr ,;; 15 ns, tf ,;; 15 ns, tw : 50 ns
liB
Differential I nput Bias Current
2
VCC+ - 5.25 V, VCC- - -5.25 V, VID - 0
30
110
Differential I nput Offset Current
2
VCC+: 5.25 V, VCC-: -5.25 V, VID: 0
0.5
75
/.LA
Input HIGH Voltage
VIH
VLL
(Strobe Inputs)
I nput LOW Voltage
(Strobe Inputs)
3
3
0.8
Output HIGH Voltage
3
VCC+: 4.75 V, VCC-: -4.75 V, IOH: -400 /.LA
VOL
Output LOW Voltage
3
VCC+ - 4.75 V, VCC- - -4.75 V, IOL - 16 mA
Input HIGH Current
IIH
(Strobe Inputs)
Input LOW Current
V
2.0
VOH
4
2.4
/.LA
V
V
4.0
0.4
V
VCC+: 5.25 V, VCC- - -5.25 V, VIH - 2.4 V
40
/.LA
VCC+ - 5.25 V, VCC-: -5.25 V, VIH: 5.25 V
1.0
mA
-1.6
mA
-3.5
mA
0.25
4
VCC+: 5.25 V, VCC-: -5.25 V, VIL: 0.4 V
lOS
Short-Circuit Output Current
5
VCC+ - 5.25 V, VCC- - -5.25 V
ICC+
Supply Current from V CC+
VCC+ - 5.25 V, VCC- - -5.25 V, TA: 25°C
25
40
mA
ICC-
Supply Current from VCC-
6
6
VCC+ - 5.25 V, VCC-: -5.25 V, TA: 25°C
-15
-20
mA
IlL
(Strobe Inputs)
-1.0
-2.1
+AII typical values are at VCC+ = 5.0 V, VCC- = -5.0 V, TA = 25°C.
NOTES:
3. The differential input threshold voltage (VT) is defined as the dc differential input voltage (VI D) required to force the output of the sense
amplifier to the logic gate threshold voltage level.
4. Common mode input firing voltage is the minimum common mode voltage that will exceed the dynamic range of the input at the specified
conditions and cause the logic output to switch. The specified common mode input signal is applied with a strobe enable pulse present.
8-47
I
FAIRCHILD • 5520/7520 SERIES
75238
SENSE AMPLIFIERS
AC CHARACTERISTICS: VCC+
= 5.0 V,
VCC -
= -5.0 V, TA = 25°C
PROPAGATION DELAY TIMES
SYMBOL
tpLH(D)
TEST
TO OUTPUT
FIGURE
Al-A2
A
7
CL
= 15 pF, R L = 288 n
STROBE
A
7
CL
= 15 pF, R L = 288 n
tPHL(D)
tpHL(D)
tpHL(S)
TYPICAL RECOVERY AND CYCLE TIMES: VCC+
SYMBOL
'orD
torC
tcyc(MIN)
TEST CONDITIONS
FROM INPUT
= 5.0 V,
VCC -
MIN
TYP
MAX
25
25
40
25
15
30
TYP
MAX
UNITS
ns
ns
= -5.0 V, TA = 25°C
CHARACTERISTICS
TEST CONDITIONS
MIN
Differential Input Overload Recovery Time
Differential Input Pulse:
(See Note 5)
V ID
Common Mode Input Overload Recovery Time
Common Mode Input Pulse:
(See Note 6)
VIC
= 2.0 V, tf = 20 ns
= ±2.0 V,
Minimum Cycle Time
tr
= tf = 20
ns
UNITS
20
ns
20
ns
200
ns
NOTES:
5. Differential input overload recovery time is the time necessary for the device to recover from the specified differential input overload signal
prior to the strobe enable signal.
6. Common mode input overload recovery time is the time necessary for the device to recover from the specified common mode input
overload signal prior to the strobe enable signal.
75238
EQUIVALENT CIRCUIT
VREF
+
VREF-
OUT A
STROBE A
INPUT Al
INPUT A2
OUT B
TEST POINT lP
INPUT 81
GND
INPUT 82
Vcc_
TEST POINT 2P
STROBE B
8-48
FAIRCHILD • 5520/7520 SERIES
DC TEST CIRCUITS (Cent'd)
Vcc_
i
SEE
TEST
TABLE 2
7528
Vcc+
STROBE B
STROBE A
TEST
POINTS
(OPEN)
8
10
15
11
14
16
N~~ED_A_ _ _....::IN:..:A:..:l_ _:..:2:(rl--~r': ~rl- H~·I~ - ~ 13
_ _ _....::I~N:..:A2~_~3~1~1
'OUT A
~
I
I
Vi
I
IN Bl
611 r---....!
---~::'--~HI """
I
1"'
1-1>
:
~o-__________.:.50I
OUT B
L--i
+-I
L
l-(~If
fill
1'2
_____'N_B_2___7<~~~V
V REF
SEE
TEST 2
TABLE
I
..J
--1'- ---- -7528/7529
J:
-1"-l
I
II
-=
100pF
TEST TABLE
CIRCUIT
TYPE
INPUTS
Al-A2
7528
AND
81-82
OUTPUTS
V re!
VID
15 mV
0;;;11 mV
0;;;0.4 V
Vo
15 mV
;;'19mV
;;'2.4 V
40mV
,;;J6mV
0;;;0.4 V
40mV
;;'44mV
;;'2.4 V
IOH
IOL
16mA
-400/J.A
16mA
-400/J.A
NOTE A: Each pair of inputs is tested separately with its corresponding output.
Each pair of differential inputs is tested separately with the other pair grounded.
Fig_ 1. - 7528 V T
8-49
FAIRCHILD· 5520/7520 SERIES
DC TEST CIRCUITS (Cant'd)
75232
PARAMETER MEASUREMENT INFORMATION
SEE
TEST
TABLE
'm
~7=52=32_ _ _-,-_~'OH
TEST TABLE
OUTPUTS
CIRCUIT
TYPE
75232
INPUTS
V re !
75232
VID
Vo
IOH
",250 !J.A
A1-A2
15 mV
"",,11 mV
5.25 V
A1-A2
15mV
>19 mV
,,0.4 V
A1-A2
40mV
,,36mV
5.25 V
A1-A2
40mV
>44 mV
",0.4 V
16mA
",250 !J.A
NOTE A: Each pair of differential inputs is tested separdtely with its corresponding output,
Fig. 1b - 75232 V T
8-50
IOL
16mA
FAIRCHILD
__
_ _-=-_.~5:5~20~/7(t520 SERIES
DC TEST CIRCUITS (Cont'd)
75238
5238
SEE
TEST ]
TABLE
I
::\'OL
1
II
_ _ _ _ _ -TEST TABLE
CIRCUIT
TYPES
IOL
75238
NOTE A: Each pair of dlffe rentlal Inputs IS tested separately with Its corresponding output.
Fig. 1c - 75238 V
8-51
T
FAIRCHILD • 5520/7520 SERIES
DC TEST CIRCUITS (Cent'd)
ALL CIRCUIT TYPES
1
Vcc-
Vcc+
p6~~is (SSETER~::~l
SEE
8
NOTES
AANDB
12).
------0-1
(OPEN)
BELOW)
-
-
-?-9-I I
I
______~3~1~
I
16
n~'
,,...0 OUT A
I
I
i l
T
A
-------...;;~---I
... ~UTB
INSt
>------L...~
INB2
V REF = 20 mV
VCC+
r-1---
SEE
TEST
'J
12
OPEN
I
I
0--------\---<0--1
I
I
L~~~~-~Tr
7528/75238
"H
V'H~ TEST
SEE
VIL..-
STROBE A
STROBE B
TABLE 3 f-------V-CC-_--=-T"E'-'S-"T=..:,
IlL
POINTS
OPEN
SEE
TEST
rI
10 15 11
TABLE 3
VID • 40 mV
Q---
IN A1
>-~+-+--L..J
IN A2
)~
1 '3
1.
IN B1
OUTB
I
20mV
,...
~~EN
IN 82
V REF
OPEN
I
---t-.Q----I
I
0---------t--'-{:>---l
L
I
I
-r---:-----r-.J
I100PF
-=-
-=-
-=-
* Required for 7528
TEST TABLE 3
TEST
INPUT A1
INPUT B1
STROBE A
IIH at Strobe A
GND
GND
VIH
VIL
IIH at Strobe B
GND
GND
VIL
VIH
IlL at Strobe A
VID
GND
VIL
VIL
IlL at Strobe B
GND
VID
VIL
VIL
8-54
STROBE B
FAIRCHILD • 5520/7520 SERIES
DC TEST CIRCUITS (Cant'd)
7528
58
SA
TEST
POINTS
(OPEN}
-
10 15
VIO '" 40 mV
11
14
16
o-......---~>-I
13
OUT A
12
OUT B
I
I
I
I
L-~-------'f.~
J
lOS
~
l00pF
+lOS
+
Fig. 58 -lOS
II
75238
SB
ISA
TEST
POINTS
(OPEN)
10 15
11
14
16
13
OUT A
12
OUT B
B2
I
v REF
<=
20 mV
o-----4-=--1
L -
(see
r
15-"
50n
STROBEB-~
,on
1
STROBE
INPUT
(SEE NOTE BI
II
VOLTAGE WAVEFORMS
DIFFERENTIAL
INPUT PULSE
STROBE INPUT
PULSE
1.5 V
1.5 V
'----'----ty,2---;--tpLH(D) - -
OUTPUT
1.5 V
7528
OUTPUT
75232/75238
1.5 V
NOTES:
A. The pulse generators have the following characteristics: 20 = 50
n,
PRR = 1 MHz.
tr = 15 ± 5 ns, tf = 15 ± 5 ns, twl
=
100 ns, tw2
=
300 ns, and
B. The strobe input pulse is applied to strobe A when inputs Al-A2 are being tested and to strobe B when inputs 81-82 are being tested.
C. CL includes probe and jig capacitance.
'Required for 7528.
Fig. 7
8-57
FAIRCHILD • 5520/7520 SERIES
TYPICAL PERFORMANCE CURVES
THRESHOLD VOLTAGE
AS A FUNCTION OF
REFERENCE VOLTAGE
Jcc
,
THRESHOLD VOLTAGE
AS A FUNCTION OF
SUPPLY VOLTAGE
!
+= S.DY
DIFFERENTIAL INPUT BIAS
CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
I
2m)
3
VCC_ - -5.0 V
TA = IfC TO 70'C
v
-t--t--iV---,f-i--i
v
v
v
2f---
,
0
3
,
W
,I,
5
..........
--
-........
------
5
r--- ......
......
r------
0
,
5
I
o
~
o
REFERENCE VOLTI\GE - mV
DIFFERENTIAL INPUT OFFSET
CURRENT AS A FUNCTION OF
AMBIENT TEMPERATURE
2
I
INPUT HIGH CURRENT
AS A FUNCTION OF
INPUT VOLTAGE
INPUT LOW CURRENT
AS A FUNCTION OF
INPUT VOLTAGE
0
. ~h~_oI5,,1 - c---
2J
,~: '"'0
,
o-
Z
r-
6
,
---r-I-
~
V
2
:;;::
-
r-..
c-
--,----
-0 5
\
- -I---
V
(
0
OUTPUT VOL TAGE AS A
FUNCTION OF DIFFERENTIAL
INPUT VOLTAGE FOR ALL
NON-INVERTING SENSE AMPS
o
-
~
,
0
_5~
,I
0
~~1~:2~~'u~v~
~
:
I I I
SEE NOTE BELOW
~
15
OUTPUT LOW VOLTAGE
AS A FUNCTION OF
SINK CURRENT
Vcc_ ~ -5.0 V
TA = 25'C
mv(
+-+c---I---+--+-+--i
I I II
r
I I II
0
0
OUTPUT HIGH VOLTAGE
AS A FUNCTION OF
LOAD CURRENT
___ ;--..
VCC+~5,OV
IOH=400"A
V REF
0
I'---
0
-----
0
I'---r-..
V REF -25mV
0
0
~VREF~35mV
-I I I
0
0
i I I
.~i~-2'
I I I
0
50 --40
30
20
10
0
0
10
20
30
40
50
LOAD CURRENT - i'A
OUTPUT VOLTAGE AS A
FUNCTION OF DIFFERENTIAL
INPUT VOLTAGE FOR ALL
INVERTING SENSE AMPS
0
RL - 2k
ov-+--
TA - 25°C
-
IOH - -400 IJ.A
0
,
II
~,,:~
, ,
,
V1REF
i i
25
VREF
0
~
2
I
J
8
35mV
6
I
,
I
I
2
I
0
e o,,~:
;'SO
0
I
50 -40 -30 -20 -10
l,Il:I~5,1111
V
0
0
NORMALIZED THRESHOLD VOLTAGE
AS A FUNCTION OF
PULSE REPETITION RATE
0
V cc+- S.DV
VCC_~-5
0
COMMON MODE FIRING
VOL TAGE AS A FUNCTION OF
AMBIENT TEMPERATURE
I
10
0
20
30
DIFFERENTIAL INPUT VOLTAGE - mV
I
i
40
AMBIENT TEMPERATURE _
8-58
°c
PULSE REPETITION RATE - MHz
,
55325-75325
MEMORY DRIVER
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION-The 55325 and 75325 are Memory Drivers fat use in magnetic memo
ories constructed on a silicon chip using the Fairchild Planar* process. The device contains four
600 rnA switches, two source switches and two sink switches that can be selected by the appropriate
logic input and appropriate strobe. The device has adequate base drive to source currents up to 375 rnA
with VCC2 of 15 V or 600 rnA with VCC2 voltage of 24 V. In applications requiring drive to source
currents greater than 375 rnA, an external resistor may be used to regulate the source base current to
within ±5% and reduce the power dissipation to allow higher source currents at higher ambient
temperatures.
CONNECTION DIAGRAMS
16-PIN
(TOP VIEW)
PACKAGE OUTLINES 7B 9B 4L
PACKAGE CODES D P F
Internal voltage surge protection of each of the output sink transistors is provided for switching
inductive loads.
•
•
•
•
•
•
•
•
•
II
600 rnA OUTPUT CAPABILITY
FAST SWITCH TIMES
OUTPUT SHORT- CIRCUIT CURRENT
DUAL SINK AND DUAL SOURCE OUTPUTS
MINIMUM TIME SKEW BETWEEN ADDRESS AND OUTPUT CURRENT RISE
24 V CAPABILITY
TTL OR DTL COMPATIBLE
SOURCE BASE DRIVE EXTERNALLY ADJUSTABLE
INPUT CLAMP DIODES
POSITIVE LOGIC TRUTH TABLE
ADDRESS INPUTS
STROBE INPUTS
SOURCE
SINK
SOURCE
INA IN B IN C IN D
S1
L
H
X
X
X
H
H
L
X
X
X
H
X
X
L
H
X
H
X
X
H
L
X
H
L
L
H
H
H
X
H.= HIGH Level, L. = LOW Level, X
SINK
S2
H
H
L
L
H
X
OUTPUTS (Note 3)
SOURCE
A
B
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
SINK
C
D
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
ORDER INFORMATION
TYPE
55325
75325
55325
75325
PART NO.
55325DM
75325DC
55325FM
75325PC
= Don't Care
"'Planar is a patented Fairchild process.
8-59
*
EQUIVALENT CIRCUIT
V CC2
0
INTERNAL R
SOURCE
COLLECTORS
I
T
I 08)
I
f·~
SOURCE
OUT A
NOOE RO
I
!
I
R,
j
to
R17
r
1
. _:in i:~n
'"
0
*06 07
OVCCI
1
0y----'03~ O~ oi'
~~n O15~
~~~~CEO
I:~n
:~J ~:~n
5::n r 03
I
r
081
#"
f::" I
O~~~RESS
r
"TI
l>
SOURCE
STROBE Sl
,
_ ADDRESS
IN B
""t"
IK",L;
ii
0
:E:
r
C
•
C1I
C1I
Co)
Q21~
~I~:CO
,
N
C1I
~
I~
C1I
:~U24(
5kU25
.~·r
023!
::n
U
19
R
R
19
1_"(
Co)
ADDRESS
-INC
U 17
*09'
SINK
OUTO
.,
0 32
+-________________________
GNOO
•
•
•
0
~;NK STROBE
~------~o~~gRE~
I~
FAIRCHILD. 55325 • 75325
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VCC1 (Note 1)
Supply Voltage VCC2 (Note 1)
Input Voltage (Any Address or Strobe Input)
+7.0 V
+25 V
+5.5 V
_65° C to +150° C
Storage Temperature Range
Operating Temperature Range
_55° C to +125° C
O°C to +70°C
1W
55325
75325
I nternal Power Dissipation (Note 2)
Pin Temperature
Hermetic DIP (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
300°C
260°C
55325
ELECTRICAL CHARACTERISTICS: Ratings apply for -55°C";; TA";; 125°C, unless otherwise specified.
SYMBOL
CONDITIONS
CHARACTERISTICS
VIH
Input HIGH Voltage
Fig. 1 & 2
VIL
Input LOW Voltage
Fig. 3 & 4
MIN
TYP
MAX
UNITS
V
2.0
0.8
V
-1.7
V
VCC' ~ 4.5 V, VCC2 - 24 V
VCD
liN = -10 mA, TA = 25°C
Input Clamp Diode Voltage
-1.3
Fig.5
IOFF
Source-collectors Terminal Off-State Current
VOH
Sink Output HIGH Voltage
VCC' = 4.5 V, VCC2 = 24 V
Full Range
Fig. 1
TA = 25°C
VCC' = 4.5 V, VCC2 = 24 V
VCC1 - 4.5 V, VCC2 - 15 V
VSAT
RL = 24
n,
Isource '" -600 mA
See Notes 3 & 4, and Fig. 3
Saturation Voltage
VCC' = 4.5 V, VCC2 = '5 V
Sink Outputs
RL = 24
n,
Isink '" 600 mA
See Notes 3 & 4 and Fig. 4
liN
ICC(off)
Full Range
TA = 25°C
0.7
0.9
0.43
0.7
Input Current at Maximum
Address Inputs
VCC1 = 5.5 V, VCC2 = 24 V
1.0
Strobe Inputs
VIN = 5.5 V, Fig. 5
2.0
Input LOW Current
IlL
0.9
0.43
}J.A
V
23
Full Range
TA = 25°C
150
Input Voltage
Input HIGH Current
IIH
19
lOUT = 0, Fig. 2
Source Outputs
500
3.0
V
V
mA
Address Inputs
VCC1 = 5.5 V, VCC2 = 24 V
3.0
40
Strobe Inputs
VIN = 2.4 V, Fig. 5
6.0
80
Address Inputs
VCC1 = 5.5 V, VCC2 = 24 V
-1.0
-1.6
Strobe Inputs
VIN = 0.4 V, Fig. 5
-2.0
-3.2
14
22
7.5
20
55
70
mA
32
50
mA
Supply Current, All Sources
From VCC1
VCC1 - 5.5 V, VCC2 - 24 V
and Sinks Off
From VCC2
TA = 25°C, Fig. 6
}J.A
mA
mA
VCC' - 5.5 V, VCC2 - 24 V
ICC1
Supply Current from VCC1, Either Sink On
Isink = 50 mA, TA = 25°C
Fig.7
VCC' = 5.5 V, VCC2 = 24 V
ICC2
Supply Current from V CC2, Either Source On
Isource = -50 mA, T A = 25° C
Fig.8
NOTES:
1.
Voltage values are with respect to network ground terminal.
2.
Refer to Dissipation Derating Curve, Figure 13.
3.
Not more than one output is to be on at anyone time.
4.
Parameters measured using the following pulse techniques;
tw
=
200 MS, duty cycle':;;; 2%.
8-61
I
FAIRCHILD. 55325 • 75325
75325
ELECTRICAL CHARACTERISTICS: Rating apply for O°C <; TA <; 70°C unless otherwise specified.
SYMBOL
CONDITIONS
CHARACTERISTICS
VIH
Input HIGH Voltage
Fig. 1 & 2
VIL
Input LOW Voltage
Fig. 3 & 4
MIN
TYP
MAX
2.0
UNITS
V
0.8
V
-1.7
V
VCCl = 4.5 V, VCC2 = 24 V
VCD
Input Clamp Diode Voltage
-1.3
liN = -10 rnA, TA = 25°C
Fig.5
10FF
Source-collectors Terminal Off-State Current
VOH
Sink Output HIGH Voltage
VCCl = 4.5 V, VCC2 = 24 V
Full Range
Fig.l
TA=25°C
VCCl = 4.5 V, VCC2 = 24 V
VCCl = 4.5 V, VCC2 = 15 V
VSAT
19
lOUT = 0, Fig. 2
Source Outputs
R L = 24 fl., Isource '" -600 rnA
See Notes 3 & 4, and Fig. 3
Saturation Voltage
VCCl = 4.5 V, VCC2 = 15 V
Sink Outputs
RL = 24 fl., Isink '" 600 rnA
200
3.0
Full Range
0.9
TA = 25°C
0.43
Full Range
0.9
TA = 25°C
0.75
I nput Current at Maximum
Address Inputs
VCCl = 5.5 V, VCC2 = 24 V
1.0
Strobe Inputs
VIN = 5.5 V, Fig. 5
2.0
Input HIGH Current
IlL
Input LOW Current
ICC(off)
0.75
Input Voltage
IIH
Address Inputs
VCCl = 5.5 V, VCC2 = 24 V
3.0
40
Strobe Inputs
VIN = 2.4 V, Fig. 5
6.0
80
Address Inputs
VCCl - 5.5 V, VCC2 - 24 V
-1.0
-1.6
Strobe Inputs
VIN = 0.4 V, Fig. 5
-2.0
-3.2
Supply Current, All Sources From VCCl
VCCl = 5.5 V, VCC2 = 24 V
and Sinks Off
TA = 25°C, Fig. 6
From VCC2
p.A
V
23
See Notes 3 & 4, and Fig. 4
liN
200
V
V
rnA
p.A
rnA
14
22
7.5
20
55
70
rnA
32
50
rnA
rnA
VCCl - 5.5 V, VCC2 - 24 V
ICCl
Supply Current from VCC1, Either Sink On
Isink = 50 rnA, TA = 25°C
Fig.7
VCCl = 5.5 V, VCC2 = 24 V
ICC2
Supply Current from VCC2, Either Source On
Isource = -50 rnA, T A = 25° C
Fig.8
55325 • 75325
SWITCHING CHARACTERISTICS: VCCl = 50 V, TA = 25°C (See Test Circuit Figures 9 and 10)
SYMBOL
tpLH
CHARACTERISTICS
Propagation Delay Time to Source Collectors
tPHL
tTLH
Transition Time to Source Outputs
TEST
FIGURE
9
10
CONDITIONS
MIN
TYP
MAX
VCC2 = 15 V. RL = 24 fI.
25
50
CL = 25 pF
25
50
VCC2 = 20 V, RL = 1 kfl.
55
CL = 25 pF
7.0
tpLH
VCC2= 15 V, RL = 24f1.
20
45
CL = 25 pF
20
45
VCC2= 15 V, RL =24f1.
7.0
15
CL = 25 pF
9.0
20
15
30
Propagation Delay Time to Sink Outputs
tTLH
tTHL
ts
9
Transition Time to Sink Outputs
9
Storage Time to Sink Outputs
9
8-62
VCC2 - 15 V, RL - 24 fI.
CL = 25 pF
ns
ns
tTHL
tpHL
UNITS
ns
ns
ns
FAIRCHILD. 55325 • 75325
TYPICAL PERFORMANCE CURVES
OFF~TATECURRENTINTOSOURCE
SINK OUTPUT HIGH
VOL TAGE AS A FUNCTION
OF AMBIENT TEMPERATURE
COLLECTORS AS A FUNCTION OF
AMBIENT TEMPERATURE
24
400
4.5 V
VCC2=24V
See Fig. 1
Vee1
1
200
>-
100
3
40
~
~
~
0
20
0
Vee1 4.5 V
VCC2"24V
10"" a
16
>
>-
Ie
I
w
'":;
See Fig. 2
I
w
/
I
C'J
II
20
I
10
12
>-
"
/
to
0
I
~
a
8
Vi
4
"'-
I
..I'
I
1
-75
4
0
~
>
2
0
-50
-25
25
0
50
100
75
-75
125
-50
SOURCE OR SINK SATURATION
VOL TAGE AS A FUNCTION OF
SOURCE CURRENT OR
SINK CURRENT
VCC2=15V
'"
~
0
Rext-See Below
Rl-See Below
>=
/'"
V
0.4
:0
>-
;J;
0.3
'"
z
Vi
<;
:i:0
iiiI
~
'>
0.2
'"
~
>:;
F--TA='70 C
See F i9S. 3 and 4
>
z
0
F\
Q
0
>
z
100
75
125
°c
0.8
Vee1 '" 4.5 V
VCC2=15V
-I (Source) or I(Sinkl == 1
See Figs. 3
4
0.7
aId
I
0.6
i=
;i
V r--
0.5
f"'"
"" 600m
p." RL.1~
J..- I-~
\
2S n
:0
>-
=
50
0
V
TA
25
SOURCE OR SINK SATURATION VOLTAGE
AS A FUNCTION OF
AMBIENT TEMPERATURE
TA\,dvj
Vee1 "4.5 V
0
T A - AMBIENT TEMPERATURE _
TA - AMBIENT TEMPERATURE _ °C
>
~
-25
;J;
25°C
'"z
Vi
<;
r5C
OA
0.3
w
:i
~ V
~
r--- ~3~p;:;-:;-
~
I--
0.2
:0
0.1
Rext
730
RL 48
0
'1
w:
,
618
538
476
426
36
31
28
385
26
350n
41
350
400
450
500
550
600
;;-
24.1:2
0
250
300
0.1
a
650
-75
SUPPL Y CURRENT, ALL SOURCES
AND SINKS OFF AS A FUNCTION OF
AMBIENT TEMPERATURE
14
E
I
VCC11, 5.5
12
>-
~
10
3
~
8
'1
6
(3
4
-
ICC1(~ff)
600
0
:::>
z
z
1
0
400
'"
'X"
"'"
"
"
0, P
f'-
"I"
PKG
F
O. P
DERATE
6.0mwtC
10.4mWrC
I
!
..... c:--,
FROM
25°C
54°C
0
20
30
40
50
60
70
80
90
100 110 120 130
AMBIENT TEMPERATURE - °c
NOTES:
A. For clarity, partial logic diagrams of two 75325's are shown.
B. Source and sink shown are in different packages.
Fig. 13
Fig. 12
8-70
"I"
'"
:::>
200
I
-rj
I
"
;::
u
SERIES 55 _
MAXTA
~
"
0
~ 800
~~
SERIES 75
MAXT A
55326-75326-55327-75327
MEMORY DRIVERS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The 55326. 55327. 75326 and 75327 are monolithic
integrated circuit quad memory drivers. These devices accept standard TTL decoder
input signals and provide high-current and high-voltage output levels suitable for driv:
ing magnetic memory elements. Output transistor selection is determined by using one
of the four address inputs and the common timing strobe.
The 55326 and 75326 memory drivers can sink up to 600 mA and operate from a
single 5 V supply.
The 55327 and 75327 memory switches can source or sink up to 600 mA and operate
from two supplies; one of 5.0 V and the other from 4.5 V to 24 V. The 55327 and 75327
can function as either sink drivers or source drivers since the voltages at the output transistor terminals are capable of swinging between VCC2 and ground.
CONNECTION DIAGRAM
16-PIN (TOP VIEW)
PACKAGE OUTLINES 78. 98. 4L
PACKAGE CODES
D P F
55326/75326
GND
CLAMP A, 0
OUT A
aUTO
INA
R EXT
STROBE
NC
VCC
IN B
IN C
OUT B
OUT C
GND
CLAMP B. C
ORDER INFORMATION
55326. 75326 PERFORMANCE
TYPE
55326
55326
75326
75326
•
•
•
•
QUAD POSITIVE OR SINK MEMORY DRIVERS
600 mA OUTPUT CURRENT SINK CAPABILITY
24 V OUTPUT CAPABILITY
CLAMP VOLTAGE VARIABLE TO 24 V
•
•
•
•
QUAD MEMORY SWITCHES
600 mA OUTPUT CURRENT CAPABILITY
VCC2 DRIVE VOLTAGE VARIABLE TO 24 V
OUTPUT CAPABLE OF SWINGING BETWEEN VCC2 AND GROUND
PART NO.
55326DM
55326FM
75326DC
75326PC
55327. 75327 PERFORMANCE
CONNECTION DIAGRAM
16· PIN (TOP VIEW)
PACKAGE OUTLINES 78. 98. 4L
PACKAGE CODES
D P F
55327/75327
EASE OF DESIGN
VCC2
•
•
•
•
•
HIGH-REPETITION-RATE DRIVER COMPATIBLE WITH HIGH-SPEED
MAGNETIC MEMORIES
INPUTS COMPATIBLE WITH TTL DECODERS
MINIMUM TIME SKEW BETWEEN STROBE AND OUTPUT-CURRENT RISE
PULSE-TRANSFORMER COUPLING ELIMINATED
DRIVE-LINE LENGTHS REDUCED
COLA,O
OUT A
OUT 0
IN A
IN D
NODE R
STROBE
R INT
Vee1
IN B
IN C
OUT B
OUTe
OND
COLB, C
ORDER INFORMATION
TYPE
55327
55327
75327
75327
8-71
PART NO.
55327DM
55327FM
75327DC
75327PC
I
FAIRCHILD • 55326 • 75326 • 55327 • 75327
55326
ELECTRICAL CHARACTERISTICS' Ratings apply over recommended temperature range unless otherwise specified
CONDITIONSt
MIN
SYMBOL
CHARACTERISTICS
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VCD
Input Clamp Diode Voltage
VCC = 4.5 V, liN = -10 mA. TA = 25°C
VOH
Output HIGH Voltage
VCC I = 4.5 V, lOUT = 0
V SAT
Saturation Voltage
VF(clamp)
I(clamp)
liN
Sink Outputs
VCC= 4.5 V
Isink = 600 mA
See Note 3
l
Isink = 50 mA. TA = 25°C
Address Inputs
Input Voltage
Strobe Inputs
IlL
Input LOW Current
V
-1.7
V
V
0.9
25°C
Output Clamp Diode Current, One Output On
Input Current at Maximum
0.8
23
Full Range
I TA -
V(Clam%) = 0, I(clamp) = -10 mA.
TA = 2 °C
Input HIGH Current
MAX UNITS
V
-1.0
19
Output Clamp Diode, Forward Voltage
IIH
TYPtt
2.0
0.43
5.0
1.5
V
7.0
mA
1.0
VIN = 5.5 V
4.0
Strobe Inputs
VIN = 2.4 V
160
Address Inputs
Strobe Inputs
VIN = 0.4 V
40
Address Inputs
V
0.7
mA
/lA
-1.0
-4.0
-1.6
-6.4
mA
ICC(off)
Supply Current, All Outputs Off
All Inputs at 5.0 V, TA = 25°C
18
25
rnA
ICC(on)
Supply Current
Isink = 50 mA. TA = 25°C
58
75
mA
75326
ELECTRICAL CHARACTERISTICS' Ratings apply over recommended temperature range unless otherwise specified
SYM80L
CHARACTERISTICS
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
V CD
Input Clamp Diode Voltage
VCC = 4.5 V, liN = -10 mA. TA = 25°C
VOH
Output HIGH Voltage
V CC1 = 4.5 V, lOUT = 0
Saturation Voltage
V CC =4.5V
Isink = 600 mA
See Note 3
VSAT
CONDITIONSt
MIN
Sink Outputs
I Full Range
I TA - 25°C
Output Clamp Diode, Forward Voltage
V(Clam~ = 0, I(clamp) = -10 mA.
TA = 2 °C
I(clamp)
Output Clamp Diode Current, One OUlput On
Isink = 50 mA. TA = 25°C
Input Current at Maximum
Address Inputs
Input Voltage
Strobe Inputs
V
-1.0
19
Input HIGH Current
IlL
Input LOW Current
ICC(off)
Supply Current, All Outputs Off
ICC(on)
Supply Current
Strobe Inputs
V
-1.7
V
V
O.g
0.43
5.0
V
0.75
1.5
V
7.0
mA
1.0
VIN = 5.5 V
4.0
VIN = 2.4 V
160
40
mA
/lA
-1.0
-4.0
-1.6
-6.4
mA
All Inputs at 5.0 V, TA = 25°C
18
25
mA
Isink = 50 mA. TA = 25°C
58
75
mA
Address Inputs
Strobe Inputs
0.8
23
Address Inputs
IIH
t Unless otherwise noted, Vee
tt All typical values are at TA ~
MAX UNITS
2.0
VF(clamp)
liN
TYPtt
V IN = 0.4 V
~ 5.5 V, V(clamp) ~ 24 V. See Figure 3.
25°e.
NOTE 3: These characteristics must be measured using pulse techniques;
NOTE 4:' For these tests only' one output is to be on at anyone time.
tw =
8·72
200 /.15, duty cycle::;;;; 2 %.
FAIRCHILD • 55326 • 75326 • 55327 • 75327
55327
ELECTRICAL CHARACTERISTICS' Ratings apply over recommended temperature range unless otherwise specified
SYMBOL
CHARACTERISTICS
V IH
Input HIGH Voltage
V IL
Input LOW Voltage
V CD
Input Clamp Diode Voltage
I(off)
Collectors Terminal
Off-state Current
VC C1 = 4.5 V.
V(col) = 24 V
Full Range
TA - 25°C
V SAT
Saturation Voltage
VCC1 = 4.5 V, Vo = 0
Isource = -600 mA
See Notes 3 and 4
Full Range
MIN
CONDITIONSt
TYPtt
MAX UNITS
2.0
-1.0
VCC = 4.5 V. liN = -10 mA. TA = 25°C
Input Current at Maximum
Address Inputs
liN
Input Voltage
Strobe Inputs
IIH
Input HIGH Current
IlL
Input LOW Current
ICC(off)
Supply Current, All Outputs Off
From VCC 1
From V CC 2
ICC(on)
Supply Current
From V CC1
From VCC2
V
V
500
150
/lA
V
0.7
1.0
VIN = 5.5 V
4.0
V IN = 2.4 V
160
40
mA
/lA
-1.0
-1.6
-4.0
-6.4
All Inputs at 5.0 V, TA = 25°C
7.0
13
10
20
mA
Isource = -50 mA, V(col) = 6.0 V
TA = 25°C, See Note 3
8.0
36
12
55
rnA
Address Inputs
Strobe Inputs
V
-1.7
0.9
0.43
TA = 25°C
Address Inputs
Strobe Inputs
0.8
V IN = 0.4 V
mA
75327
ELECTRICAL CHARACTERISTICS' Ratings apply over recommended temperature range unless otherwise specified
SYMBOL
CHARACTERISTICS
V IH
Input HIGH Voltage
MIN
CONDITIONSt
VIL
Input LOW Voltage
Input Clamp Diode Voltage
VCC = 4.5 V, liN = -10 mA. TA = 25°C
I(off)
Collectors Terminal
Off-state Current
V CC 1 = 4.5 V,
V(col)= 24 V
VSAT
Saturation Voltage
V CC 1 = 4.5 V, Vo = 0
Isource = -600 mA
See Notes 3 and 4
Input Current at Maximum
Address Inputs
Input Voltage
Strobe Inputs
V
0.8
V
-1.7
V
Full Range
TA - 25°C
200
200
/lA
Full Range
0.9
TA = 25°C
-1.0
0.43
Input HIGH Current
IlL
Input LOW Current
ICC(off)
Supply Current, All Outputs Off
From VCC1
From V CC2
ICC(on)
Supply Current
From V CC1
From V CC2
Strobe Inputs
1.0
4.0
V IN = 2.4 V
160
40
mA
/lA
-1.0
-1.6
-4.0
-6.4
All Inputs at 5.0 V, TA = 25°C
7.0
13
10
20
rnA
Isource = -50 mA. V(col) = 6.0 V
TA = 25°C, See Note 3
8.0
36
12
55
mA
Address Inputs
Strobe Inputs
V
0.75
VIN = 5.5 V
Address Inputs
IIH
t
tt
MAX UNITS
2.0
V CD
liN
TYPtt
V IN = 0.4 V
Unless otherwise noted, Vee ~ 5.5 V, Vlclampl ~ 24 V. See Figure 3.
All typical values are at TA ~ 25°e.
NOTE 3: These characteristics must be measured using pulse techniques;
NOTE 4: For these tests only one output is to be on at anyone time.
tw =
8-73
200 JiS, duty cycle ~ 2 %.
mA
I
FAIRCHILD • 55326 • 75326 • 55327 • 75327
55326 • 75326
SWITCHING CHARACTERISTICS: V CC1 = 5.0
Ii,
TA = 25°C (See Test Circuit Figure 5)
----~---,-----,~---.---,-----
SYMBOL
CONDITIONS (See iIIote 4)
CHARACTERISTICS
MIN
TYP
MAX UNITS
50
Propagation Delay Time to A B, C or D
25
Vs = V(clamp) = 15 V, RL = 240,
Transition Time to A B, C or D
CL = 25 pF
Storage Time to A B, C or D
Vs = V(clamp) = 24 V, RL = 47 0,
CL = 25 pF, Isink = 500 mA
Output HIGH Voltage
ns
50
7.0
15
10
20
24
35
ns
ns
mV
Vs -25
55327 • 75327
SWITCHING CHARACTERISTICS: V CC1 = 5.0 V, TA = 25°C (See Test Circuit Figure 5)
CONDITIONS (See Note 4)
MIN
TYP
MAX UNITS
SYMBOL
CHARACTERISTICS
tpLH
Propagation Delay Time to
VS=VCC2= 15V, RL =240,
35
55
tpHL
Collectors AD or B,C
CL = 25 pF, See Figure 5 and Note 5
30
55
tTLH
Transition Time to AB,C or D
V(col) = VC C2 = 20 V, RL = 100 0,
30
CL = 25 pF, See Figure 6 and Note 5
10
tTHL
Vs = V CC 2 = 24 V, RL = 47 0,
CL = 24 pF, Isink = 500 mA,
See Figure 5 and Note 5
Output HIGH Voltage to
Collectors AD or B,C
VO H
t
ns
mV
Vs -25
Unless. otherwise noted, Vee = 5,5 V, V(clamp) = 24 V. See Figure 3.
typical values are at TA = 25°C.
tt All
tw
NOTE 3: These characteristics must be measured uSing pulse techniques;
-= 200 JiS, duty cycle :( 2 %
NOTE 4: For these tests only one output is to be on at anyone time,
NOTE 5: A 350 n resistor is connected between node R (pin 4) and V CC2 (pin 1) with Rint (pin 5) open
TYPICAL PERFORMANCE CURVES
OFF-STATE CURRENT INTO
SOURCE COLLECTORS AS A
FUNCTION OF AMBIENT
TEMPERATURE - 55327/75327 ONLY
SINK OUTPUT HIGH VOLTAGE
AS A FUNCTION OF AMBIENT
TEMPERATURE - 55326/75326 ONLY
400 r~::;;:7~+==t====1==t==+=!
Vee1
4.5 v
.. 200 VCC2 ~ 24 V+--I---+-+-+--II
>
1-.
>.-
"...
~
0
!
4
16 '10 ~ 0
vee1 "" 4.5 V
VCC2 "" 24 V
+--1---+-+-+---1
"
i
>-
.."
/
10
0
:J:
/
20
201---+-+-+--1--+-4--1--1
>
0:
""w
w
"~
~ 100~!~~~~1~
40
i0:::i
-
24IF=F=t==F=r==+=:J~
I
/
"-
>-
"0
'"z
--
iii
---- r--
I
:J:
0
>
__~__L--"
50
75 100 125
oL-~_~_~~~-L
25
50
75
100
~75
125
-50 -25
0
25
TA - AMBIENT TEMPERATURE - °C
TA - AMBIENT TEMPERATURE - °C
8-74
ns
TRANSISTOR ARRAYS AND SPECIAL FUNCTIONS
Transistor and Diode Arrays
IlA3018
Matched Monolithic Transistor Array .................................... 9-3
IlA3018A
Matched Monolithic Transistor Array .................................... 9-3
IlA3019
Diode Array ............................................................ 9-3
IlA3026
Transistor Array ..........................................•............. 9-3
IlA3036
Transistor Array ........................................................ 9-3
IlA3039
Diode Array ............................................................ 9-3
IlA3045
Transistor Array ........................................................ 9-3
IlA3046
Transistor Array ........................................................ 9-3
IlA3054
Transistor Array ........................................................ 9-3
IlA3086
Transistor Array ........................................................ 9-3
IlA726
Temperature-Controlled Differential Pair ............................... 9-23
Special Functions
IlA555
Single Timing Circuit ................................................. 9-26
IlA556
Dual Timing Circuit ................................................... 9-31
IlA2240
Programmable Timer/Counter ......................................... 9-36
IlA7391
DC Motor Speed Control ...............................................9-47
IlA7392
DC Motor Speed Control .............................................. 9-57
~A3018.~A3018A.~A3019.~A3026.~A3036
~A3039·~A3045·~A3046.~A3054.~A3086
TRANSISTOR AND DIODE ARRAYS
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - Fairchild Transistor and Diode Arrays consist of general purpose integrated circuit devices constructed
on a single substrate, using the Fairchild Planar' epitaxial process. These arrays are arranged to offer maximum flexibility in circuit
design for applications from dc to 120 MHz. Excellent transistor and diode matching and temperature tracking allow circuit
techniques unavailable when using discrete devices. Multiple devices in one package permit a greater packing density and cost saving
than with individually packaged transistors.
• PRECISION MONOLITHIC MATCHING
• DESIGN FLEXIBILITY
• CUSTOM APPLICATIONS
PACAKGE OUTLINE 5D
PACKAGE CODE H
PACKAGE OUTLINE 50
PACKAGE CODE H
PACKAGE OUTLINE 6A
PACKAGE CODE D
2
11
9~3
04
2
:4' of:
0
10
4
6
SUBSTRATE'
ORDER INFORMATION
TYPE
PART NO.
I'A3018
I'A3018A
jJ.A3018HM
I'A3018AHM
5
4
14
riHri
,
7
1
UW
~y~
12
1
9
10
12
13
SUBSTRATE
ORDER INFORMATION
TYPE
PART NO.
I'A3045DM
I'A3045
I'A3046
I'A3046DC
I'A3046PC
I'A3046
I'A3086
I'A3086DM
ORDER INFORMATION
TYPE
PART NO.
jJA3036HM
I'A3036
PACKAGE OUTLINE 5D
PACKAGE CODE H
PACAKGE OUTLINE 6A
PACAKGE CODE D
3
~
14JJ
~3
2
~2~~
6
~"
9 :':5
13
04
Q3
SUBS~RATE
4
3
ORDER INFORMATION
TYPE
PART NO.
jJA3026
I'A3026HM
5
ORDER INFORMATION
TYPE
PART NO.
I'A3054
I'A3054DC
PACAKGE OUTLINE 5D
PACAKGE CODE H
PACAKGE OUTLINE 50
PACKAGE CODE H
3
4
6
5
7
8
~~lwJ
I*'lI*'l~
-t>f
2
1
11
12
10
9
SUBSTRATE
ORDER INFORMATION
TYPE
PART NO.
I'A3019
IlA3019HM
ORDER INFORMATION
TYPE
PART NO.
I'A3039
IlA3039HM
"'ptanar is a patented Fairchild process.
9-3
FAIRCHILD. fLA30XX SERIES
,uA3018/3018A
•
MATCHED MONOLITHIC GENERAL PURPOSE TRANSISTORS
•
•
•
•
•
•
•
hFE MATCHED ±10%
VBE MATCHED ±2 mV 3018A (±5 mV 3018)
OPERATION FROM DC TO 120 MHz
WIDE OPERATING CURRENT RANGE
3018A PERFORMANCE CHARACTERISTICS CONTROLLED FROM 10 IJ,A TO 10 mA
LOW NOISE FIGURE - 3.2 dB TYPICAL AT 1 kHz
FULL MILITARY TEMPERATURE RANGE CAPABILITY (-55 TO +125°C)
APPLICATIONS
• General Use in Signal Processing Systems in de Through VHF
Range
• Custom Design Differential Amplifiers
• Temperature Compensated Amplifiers
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Note 1)
Any One Transistor
Total Package
Temperature Range
Operating Temperature
Storage Temperature
The following ratings apply for each transistor in the device:
Coliector·to·Emitter Voltage, VCEO
Coliector·to·Base Voltage, VCBO
Coliector·to·Substrate Voltage, VCIO (Note 2)
Emitter·to·Base Voltage, VEBO
Collector Current, IC
9-4
IJ,A3018
300mW
450mW
j.LA3018A
300mW
450 mW
_55°C to +125°C
-65°C to +200°C
_55°C to +125°C
_65° C to +200° C
15 V
20 V
20 V
5V
50mA
15 V
30 V
40V
5V
50mA
FAIRCHILD. /-LA30XX SERIES
ELECTRICAL CHARACTERISTICS FOR IlA3018: TA = 25°C unless otherwise specilied
SVMBOL
MAX
Collector Cutoff Current
VCB=10V,IE=0
0.002
100
nA
ICEO
Collector Cutoff Current
VCE=10V,IB=0
See Curve
5.0
IlA
CHARACTERISTICS
CONDITIONS
MIN
UNITS
TVP
ICBO
ICEOD
Collector Cutoff Current Darlington Pair
VCE=10V,IB=0
V(BR)CEO
Coliector·to·Emitter Breakdown Voltage
IC - 1 rnA, IB - 0
15
24
V
V(BR)CBO
Coliector·to·Base Breakdown Voltage
IC=1 0 IlA,IE=0
20
60
V
V(BR)EBO
Emitter·to·Base Breakdown Voltage
IE -10IlA,IC=0
5.0
7.0
V
V(BR)CIO
Coliector·to·Substrate Breakdown Voltage
IC=10IlA,ICI-0
20
60
V
VCES
Collector~to-Emitter
0.23
V
hFE
Saturation Voltage
Static Forward Current Transfer Ratio
IlA
IB = 1 rnA, IC = 10 rnA
VCE = 3 V
{IC=10mA
IC= 1 mA
100
30
Magnitude 01 Static· Beta Ratio
(Isolated Transistors Q 1 and Q2)
hFED
Static Forward Current Transfer Ratio
Darlington Pair (Q3 & Q4)
VBE
Base·to·Emitter Voltage
VBE1
Input Ollset Voltage
aVBE
Temperature Coefficient: Base-ta-Emitter
VCE = 3 V, ICl = IC2 = 1 mA
100
54
IC= 10llA
0.9
0.97
1500
5400
IC = 1 mA
VCE = 3 V
{
VCE = 3 V
{ IE = 10mA
IC= lOO IlA
IE =
1 mA
0.715
V
0.800
VCE=3V,IE=lmA
0.48
VCE=3V,IE=lmA
-1.9
5.0
mV
IVBE2 1
aT
Voltage Q1, Q 2
VBED
Base (Q3)·to.Emitter (Q4)
(V 9 · 1)
Voltage·Dariington Pair
aVBED
--aT
IE = 10 mA
1.46
1 mA
1.32
IE =
V
Temperature Coefficient:
Base·to·Emitter Voltage
Darlington Pair·Q3,Q4
VBE1, V BE2 Temperature Coefficie.nt:
Magnitude 01 Input·Offset Voltage
aT
NF
VCE=3V {
mVtC
Low Frequency Noise Figure
4.4
mV/oC
10
IlV/oC
3.25
dB
1=1 kHz, VCE = 3 V, IC = 1 mA
110
3.5
15.6
1.8x 10- 4
kS1
Ilmho
1=1 MHz, VCE = 3 V, IC = 1 mA
31 -j 1.5
0.3+j 0.04
0.001 + j 0.03
VCE=3V,IE=lmA
VCC = +6 V, VEE = -6 V
1= 1 kHz, V CE = 3 V, IC = 100 IlA
Sou rce resistance
=1
kS1
Low Frequency, Small-Signal Equivalent Circuit Characteristics:
hie
hie
hoe
h re
Forward Current-Transfer Ratio
Short Circuit Input Resistance
Open Circuit Output Conductance
Open Circuit Reverse Voltage-Transfer Ratio
Admittance Characteristics:
See Curve
mmho
mmho
mmho
mmho
IT
Gain·Bandwidth Product
VCE -3V,IC - 3 mA
500
MHz
Ceb
Emitter-to-Base Capacitance
VEB=3V,IE=O
0.6
pF
Ccb
Collector-to-Base Capacitance
VCB=3V,IC=0
0.58
pF
CCI
Coliector·to·Substrate Capacitance
VCI=3V,IC=0
2.8
pF
Vie
Vie
Voe
V re
Forward Transfer Admittance
Input Admittance
Output Admittance
Reverse Transfer Admittance
NOTES:
1. Derate at 5 mW/ o C for T A> 85° C.
2. Substrate must be connected to the most negative voltage to maintain normal operation.
9-5
I
FAIRCHILD • tLA30XX SERIES
ELECTRICAL CHARACTERISTICS FOR IlA3018A: TA = 25°C unless otherwise specified
TYP
MAX
ICBO
Collector Cutoff Current
VCB = 10 V, IE = 0
0.002
40
nA
ICEO
Collector Cutoff Current
VCE = 10 V, IB - 0
See Curve
0.5
IlA
5.0
IlA
SYMBOL
CHARACTERISTICS
CONDITIONS
MIN
UNITS
ICEOD
Collector Cutoff Current Darlington Pair
VCE = 10 V, IB = 0
V(BR)CEO
Collector·to-Emitter Breakdown Voltage
IC-1mA,IB·-0
15
24
V
V(BR)CBO
Coliector-to·Base Breakdown Voltage
IC= lO llA,IE=O
30
60
V
V(BR)EBO
Emitter-ta-Base Breakdown Voltage
IE= lO llA,IC-O
5.0
7.0
V
V(BR)CIO
Collector·to-Substrate Breakdown Voltage
IC= 10llA,ICI =0
40
60
VCES
Collector-ta-Emitter Saturation Voltage
IB = 1 mA, IC = 10 mA
hFE
Static Forward Current Transfer Ratio
VCE = 3 V
{ IC = 10mA
IC = 1 mA
IC = 10llA
hFED
Magnitude of Static· Beta Ratio
(Isolated Transistors Q, and Q2)
VCE = 3 V, ICl = IC2 = 1 mA
Static Forward Current Transfer Ratio
VCE = 3 V
{
{ IE = 10 mA
Darlington Pair (Q3 & Q4)
0.23
50
100
60
100
30
54
0.9
0.97
IC= 1 mA
2000
5400
IC = 100llA
1000
2800
0.600
0.715
0.800
0.800
0.900
2.0
IE =
1 mA
VBE
Base·to·Emitter Voltage
VCE = 3 V
jVBE,!
VBE2
Input Offset Voltage
VCE=3V,IE=lmA
0.48
L>VBE
Temperature Coefficient: Base-ta-Emitter
VCE=3V,IE'=lmA
-1.9
L>T
VBED
(Vg.,)
L>VBED
--L>T
VBE,·VBE2
L>T
NF
Voltage Q" Q 2
Base (Q3)·to-Emitter (Q4)
Voltage-Darlington Pair
VCE = 3 V
V
0.5
IE = 10 mA
{ IE =
1 mA
1.10
V
V
mV
mVtC
1.46
1.60
1.32
1.50
V
Temperature Coefficient:
Base·to·Emitter Voltage
Darlington Pair-Q 3 ,Q 4
Temperature Coefficient:
Magnitude of Input·Offset Voltage
VCE = 3 V, IE = 1 mA
VCC = +6 V, VEE = -6V
f= 1 kHz, VCE =3 V, IC = 100llA
Low Frequency Noise Figure
Sou rce resistance
=
1 kn
4.4
mVtC
10
IlV/oC
3.25
dB
110
3.5
15.6
1.8 x 10-4
kn
Ilmho
Low Frequency, Small-Signal Equivalent Circuit Characteristics:
hfe
hie
hoe
h re
Forward Current-Transfer Ratio
Short Circuit Input Resistance
Open Circuit Output Conductance
Open Circuit Reverse Voltage-Transfer Ratio
f = 1 kHz, VCE = 3 V, IC = 1 mA
Admittance Characteristics:
Yfe
Vie
Y oe
Y re
Forward Transfer Admittance
Input Admittance
Output Admittance
Reverse Transfer Admittance
f = 1 MHz, VCE = 3 V, IC = 1 mA
31-j 1.5
0.3+j 0.04
0.001 + j 0.03
See Curve
mmho
mmho
mmho
mmho
fT
Gain·Bandwidth Product
VCE=3V,IC~3mA
500
MHz
Ceb
Emitter-to-Base Capacitance
VEB = 3 V, IE = 0
0.6
pF
Ccb
Collector-to-Base Capacitance
VCB=3V,IC=0
0.58
pF
CCI
Coliector·to·Substrate Capacitance
VCI=3V,IC=0
2.8
pF
9-6
FAIRCHILD. J,LA30XX SERIES
TYPICAL PERFORMANCE CURVES FOR JlA3018/3018A
COLLECTOR-TO-BASE CUTOFF
CURRENT ASA FUNCTION OF
AMBrENT TEMPERATURE FOR
EACH TRANSISTOR
COLLECTOR-TO-EMITTER CUTOFF
CURRENT AS A FUNCTION OF
AMBIENT TEMPERATURE
FOR EACH TRANSISTOR
STATIC FORWARD CURRENTTRANSFER AND BETA RATIO FOR
TRANSISTORS 01, 02 AS A
FUNCTION OF EMITTER CURRENT
5.102
,
;:::: le- O
,
,
,
Vee '15V
1/1
,,- t- t-
'"
o
,
~1O-3
3
5xl0 .....
,
"
,
"
~
10- 1
5.10-2
~j 10- 2
8
10-3
"
AMBIENT TEMPERATURE _"C
,
~'.~,;-;";i.,,,~,.";c,e,.';-,";';.2--Ll;;\,,'--!,-,P-"+-,-;"
Ie - EMITTER CURRENT - mA
STATIC BASE-TO-EMITTER VOLTAGE
STATIC FORWARD CURRENTAND INPUT OFFSET VOLTAGE FOR
TRANSFER RATIO FOR DARLINGTON
CONNECTED TRANSISTORS 03, 04 AS A
01,02 AS A FUNCTION OF
FUNCTION OF EMITTER CURRENT
EMITTER CURRENT
,
10,000
veE ~ 3V
+
VeE" 3V
TA s25"C
T A : 25 C
f- r--
• 8000
"
,~~
• 7000
8
'"
~4000
•
,
3
,
,
I II IA
1, ,I , ,
,.,
INPUT OFFSET VOLTAGE - iV SE1
I II
,
",
"
OFFSET VOLTAGE CHARACTERISTIC
AS A FUNCTION OF
AMBIENT TEMPERATURE
,
Vce: 3V
3
le~ LOlA I---: f- V
,
7
~~~
~
,
V
-
1.0OlA
,
0.1 mA
-
,
7
AMBIENT TEMPERATURE -"C
0.'
0.6
STATIC INPUT VOLTAGE FOR
DARLINGTON PAIR (03,04'
AS A FUNCTION OF
AMBIENT TEMPERATURE
,
vee l. 3V
,
~~
50
75
AMBIENT TEMPERATURE -"C
9-7
~
,
''1)",,'''-1
Q~
25
0.2
EMITTER CURRENT - rnA
VeE -3V
~
II
,,/
"
BASE-TO-EMITTER VOLTAGE
CHARACTERISTIC FOR EACH
TRANSISTOR AS A FUNCTION
OF AMBIENT TEMPERATURE
f-
,
v
V aE2
EMITTER CURRENT
-
v
/ ,
6
./
·2000
,
STATIC INPUT VOLTAGE FOR
DARLINGTON PAIR 03,04ASA
FUNCTION OF EMITTER CURRENT
r-
---- ,
.7
~SOOl
23000
'
~ ~ t-
s:
"
100
,
~
~
'I~ ~~
,
,
"
~Ew3mA
~
,
"
AMBIENT TEMPERATURE
-"c
~
'"
FAIRCHILD. /LA30XX SERIES
TYPICAL AC CHARACTERISTICS FOR EACH TRANSISTOR
GAIN-BANDWIDTH PRODUCT (fT)
AS A FUNCTION OF
COLLECTOR CURRENT
NORMALIZED h PARAMETERS
AS A FUNCTION OF
COLLECTOR CURRENT
FORWARD TRANSFER ADMITTANCE (Yfe)
AS A FUNCTION OF FREQUENCY
I
VCE=3V
TA =25°C
-
VV
(
"" ,
FREOUENCY- MH.
INPUT ADMITTANCE (Yie)
AS A FUNCTION OF
FREQUENCY
.1
,.Ii
:'c-; ,m,'
I I
I
I
:,:.1,1
i
I
I
!
/
2
I
I
1
,
,
/1
'/
I
I
".
II
L
,
NOISE FIGURE
AS A FUNCTION OF
COLLECTOR CURRENT,
"
I-
!",~~
_·fL
,~_:'_;
~
",dj'l
0;
~r-
r-
"
0.01
'/
-
~&
1kHz
10kHz
/
V
/
11~
IJ
~
1
II
II
II
1/
,
l-!'
'/
,
V
JI
,
":'v
,L ~
NOISE FIGURE
AS A FUNCTION OF
COLLECTOR CURRENT,
/
,i
.il
~~
a~ I'
~t-
,
'C'mA
11
.,~
-,~.:;~
"
~
200 ,
NOISE FIGURE
AS A FUNCTION OF
COLLECTOR CURRENT,
"
~re
,
I
II
i
IL J ,,::~~:~:"~~~c+,,_
'0.
II
!
I
I
REVERSE TRANSFER ADMITTANCE (Y,e)
AS A FUNCTION OF FREQUENCY
2
II
I I
I
II
!
1
"
I
1,
-'co:, mA
b,e
I
,
OUTPUT ADMITTANCE (Y ae )
AS A FUNCTION OF FREQUENCY
V
/
L
1kHz
~HZ
"
COLLECTORCURflENT_mA
9-8
A
'/
V
FAIRCHILD. ILA30XX SERIES
MA3019
•
•
EXCELLENT DIODE MATCHING - 1 rnV TYP.
LOW REVERSE LEAKAGE CURRENT - 5 rnA TYP.
APPLICATIONS
• Modulator
• Mixer
• Balanced Modulator
• Analog Switch
• Diode Gate for Chopper-Modulator Applications
ABSOLUTE MAXIMUM RATINGS
Power Dissipation
For each Diode
Total For Device
Temperature Range
20mW
120mW
_65° C to +200° C
-55°C to +125°C
18 V
Storage Temperature
Operating Temperature
Voltage Between Any Pin and Pin 7 (Note 1)
ELECTRICAL CHARACTERISTICS FOR IlA3019: For each diode, TA = 25°C unless otherwise specified
SYMBOL
CONDITIONS
CHARACTERISTICS
MIN
TYP
MAX
UNITS
VF
DC Forward Voltage Drop
DC Forward Current, IF
= 1 rnA
-
0.73
0.78
V
BV
DC Reverse Breakdown Voltage (Any Diode)
DC Reverse Current, IR
= -10 IlA
4.0
6.0
-
V
DC Reverse Current, IR
= -10 IlA
25
80
-
V
DC Reverse Breakdown Voltage Between
B.VS
IR
any Diode Unit and Substrate
DC Reverse (Leakage) Current
DC Reverse (Leakage) Current Between
IR
any Diode Unit and Substrate
Magnitude of Diode Offset Voltage
1VFl . VF21
(Difference in DC Forward Voltage
DC Reverse Voltage, VR
= -4
V
-
0.0055
10
IlA
DC Reverse Voltage, VR
= -4
V
-
0.010
10
IlA
DC Forward Current, IF = 1 rnA
-
1.0
5.0
mV
-
1.8
-
pF
Pin2or6toPin7
-
4.4
-
2.7
See Figure 1
-
10
-
pF
Pin50rBtoPin7
Drops of any Two Diode Units)
CD
Single Diode Capacitance
Frequency, f
Frequency, f
CDQ_I
Diode Quad-to-Substrate
Capacitance
= 1 MHz
DC Reverse Voltage, VR
=1
Series Gate Switching Pedestal Voltage
V
MHz
DC Reverse Voltage, VR between
Pins 2,5,6, or 8 of Diode Quad
and Pin 7 (Substrate)
Vs
= -2
NOTE
1. Substrate (Pin 7) must be connected to the most negative potential.
9-9
= -2
V
pF
mV
•
FAIRCHILD. IJ.A30XX SERIES
TYPICAL PERFORMANCE CURVES FOR j.!A3019
DC FORWARD VOLTAGE DROP
(ANY DIODE) AS A FUNCTION OF
TEMPERATURE
REVERSE ILEAKAGE) CURRENT
(ANY DIODE) AS A FUNCTION OF
TEMPERATURE
1.',-r-,,-r--;-.,--,-......,
~
i
.'I--:l----1--1+-I-+--+-+--1
.,I-+.........
-f""""'b-+--+-+-+-i
~
.......
O.61-+--1I-+-I-+--+'::>'~:-l
0.415
50
25
0
25
50
75
"r-+-r--r~~+-i_~V,L~
" 20/-+-1-+--1-+-1-1--1
r---..
f'..r-.,.
3O/-+-1-+--11-+-I-+~
/
~
15
g
10r-+-r--r~r-~~-+-;
~~,,--,~.~_~=-~O~~~~~~~~75~1~OO~,~,
100125
AMBIENT TEMPERATURE _
AMBIENT TEMPERATURE _·C
DIODE CAPACITANCE
(ANY DIODE) AS A FUNCTION OF
REVERSE VOLTAGE
'r--r-r--r-,-,--,-,--.
°c
DIODE QUAD-TO-SUBSTRATE
CAPACITANCE AS A FUNCTION OF
REVERSE VOLTAGE
'r-'--r-'r-~-r-.--.-,
~ 11= 25.t_t-+_r-+~--I
r-~.Jc-l-+-t-+--t-f
f=lMHz
f"l MHz
r-_I--
DC REVERSE VOLTAGE ACROSSDIOOE _ V
DC REVERSE VOLTAGE BETWEEN PIN
2 OR BAND SUBSTRATE (PIN 71
SERIES GATE SWITCHING
TEST SETUP
DIODE QUAD-TO-SUBSTRATE
CAPACITANCE AS A FUNCTION OF
REVERSE VOLTAGE
'" 10mVP-P
DC REVERSE VOLTAGE BETWEEN PINS
50A 8 AND SUBSTRATE {PIN 71
-6V
Fig. 1
9-10
FAIRCHILD. M-A30XX SERIES
pA3026/3054
•
•
•
•
LOW INPUT OFFSET VOLTAGE - ±5 mV
WIDEBAND OPERATION
INDEPENDENTLY ACCESSIBLE INPUTS AND OUTPUTS
TWO MATCHED DIFFERENTIAL AMPLIFIERS
APPLICATIONS
• Dual Sense Amplifiers
• Dual Schmitt Triggers
• Multifunction Combinations - RF/Mixer/Osciliator; Converter/IF
• I F Amplifiers (Differential and/or Cascode)
•
Product Detectors
•
Doubly Balanced Modulators and Demodulators
•
•
Balanced Quadrature Detectors
Cascade Limiters
•
•
•
•
Synchronous Detectors
Pairs of Balanced Mi xers
Synthexizer Mixers
Balanced (Push-Pull) Cascode Amplifiers
ABSOLUTE MAXIMUM RATINGS (For Each Transistor)
Power Dissipation (Note 1 )
Any One Transistor
Total Package
Temperature Range
Operating Temperature
Storage Temperature
The following ratings apply for each transistor in the device
IlA3054
IlA3026
300 mW
600 mW
300 mW
750 mW
_55 0 C to +125° C
O'C to +85'C
_25' C to +85' C
_65' C to +200' C
15 V
20 V
20 V
5V
50 mA
Collector-to-Emitter Voltage, VCEO
Collector-to-Base Voltoge, VCBO
Collector-to-Substrate Voltage, VCIO (Note 2)
Emitter-to-Base Voltage, VEBO
Collector Current, IC
ELECTRICAL CHARACTERISTICS FOR IlA3026/3054: TA ~ 25'C unless otherwise specified
SYMBOL
VIO
110
II
IC(Ol) or IC(Q5)
IC(02)
IC(06)
LlIVIOI
LlT
CHARACTER ISTICS
CONDITIONS
For Each Differential Amplifier
Input Offset Voltage
I nput Offset Current
Input Bias Current
VCB
Quiescent Operating
Current Ratio
~
3 V
I E(03) ~ IE(C4) ~ 2 mA
Temperature Coefficient
Magnitude of Input-Offset Voltage
MIN
TYP
MAX
UNITS
-
0.45
0.3
10
5
2
24
mV
IlA
IlA
-
0.98 to
1.02
-
-
-
1.1
-
IlV/'C
-
0.630
0.715
0.750
0.800
0.700
0.800
0.850
0.900
V-
-
-1.9
-
mV/'C
For Each Transistor
VBE
LlVBE
LlT
ICBO
V(BR)CEO
VCB ~ 3 V
DC Forward Base-toEmitter Voltage
IC~50IlA
1 mA
3mA
10mA
Temperature Coefficient of Base
to-Emitter Voltage
VCB~
Coliector·Cutoff Current
VCB~10V,IE~0
-
0.002
IC~l mA,IB~O
15
Coil ector·to·Emitter
Breakdown Voltage
3
V,IC~
1 mA
100
nA
24
-
V
V(BR)CBO
Collector-to-Base
Breakdown Voltage
IC~10IlA,IE~0
20
60
-
V
V(BR)CIO
Collector-to-Substrate
Breakdown Voltage
IC~
20
60
-
V
5
7
-
V
V(BR)EBO
lOIlA,lCI
~O
IE~10IlA,IC~0
Emitter-to-Base Breakdown Voltage
NOTES
1. For T A> 55°C; 3026 derates at 5 mW/oC and 3054 at 6.67 mW/oC
2. The collector of each transistor of the 3026 and 3054 is isolated from the substrate by an integral diode. Substrate must be connected to the
most negative voltage to maintain normal operation.
9-11
I
FAIRCHILD. ILA30XX SERIES
. ELECTRICAL CHARACTERISTICS FOR IlA3026/3054: TA = 25'C unless otherwise specified (Cont'd)
CHARACTERISTICS (See Test Circuits)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CMRR
Common-Mode Rejection Ratio
for Each Ampl ifier
VCC=12V
-
100
-
dB
AGC
AGC Range, One Stage
VEE = -6 V
-
75
-
dB
AV
Voltage Gain, Single Stage Double-Ended Output
V x =-3.3V
-
32
-
dB
AGC
AGC Range, Two Stage
f - 1 kHz
-
105
-
dB
AV
Voltage Gain, Two Stage Double-Ended Output
-
60
-
dB
f = 1 kHz, VCE = 3 V,
IC= 1 mA
-
110
3.5
15.6
1.8x10-4
-
kn
Ilm ho
Low-Frequency. Small·Signal Equivalent·Circuit
Chara(~teristics (for Single Transistor):
Forward Current-Transfer Ratio
Short Circuit Input Resistance
Open Circuit Output Conductance
Open Circuit Reverse Voltage-Transfer Ratio
hfe
hie
hoe
h re
-
-
NF
1 Noise Figure (for Single Transistor)
f = 1 kHz, VCE = 3 V
-
3.25
fT
·Gain-Bandwidth Product (for Single Transistor)
VCE = 3 V,lc=3mA
-
550
-
VCB = 3 V
Each Collector
IC'" 1.25 mA
f = 1 MHz
-
-20+jO
0.22+j 0.1
0.01+j 0
-0.003+j 0
-
mmho
VC8 = 3 V
Total Stage
IC "'2.5 mA
f = 1 MHz
-
-
-
68-j 0
0.55+j 0
O+j 0.02
O.004-j 0.005
-
mmho
mmho
mmho
Ilmho
-
8
-
dB
dB
MHz
Admittance Characteristics; Differential Circuit
Configuration (for Each Amplifier):
Forward Transfer Admittance
Input Admittance
Output. Admittance
Reverse Transfer Admittance
Y21
Y11
Y22
Y12
-
mmho
mmho
mmho
Admittance Characteristics; Cascode Circuit
Configuration (for Each Amplifier):
Forward Transfer Adm ittance
Y21
Y11
Y22
Y12
NF
Input Admittance
Output Admittance
Reverse Transfer Admittance
f - 100 MHz
Noise Figure
-
TYPICAL PERFORMANCE CURVES FOR IlA3026/3054
COLLECTOR-TO-BASE CUTOFF
CURRENT AS A FUNCTION OF
AMBIENT TEMPERATURE
FOR EACH TRANSISTOR
INPUT BIAS CURRENT
CHARACTERISTIC AS A FUNCTION
OF COLLECTOR CURRENT
FOR EACH TRANSISTOR
BASE-TO-EMITTER VOLTAGE
CHARACTERISTIC FOR EACH
TRANSISTOR AS A FUNCTION OF
AMBIENT TEMPERATURE
2
=~~B-2~~~V
r-~CO
,
,
VCB -15V
&.".L- -
WV
9V-
,
VCB~
3.0V
0
5xl0-1
- -
0
0
9
2
L
/
9
8
~
-....;;:
2
9
9
6
3
5xl0-4
,
:v
05~ ~
9
,
-
AMBIENTTEMPERATURE-"C
~ ::::-..: ~, +,m~
r---.:: ~.......
- 50
25
AMBIENT TEMPFRATURE _
9-12
75
°c
100125
FAIRCHILD. JLA30XX SERIES
TYPICAL AC CHARACTERISTICS FOR EACH TRANSISTOR FOR /lA3026/3054
NORMALIZED h PARAMETER
AS A FUNCTION OF
COLLECTOR CURRENT FOR
EACH TRANSISTOR
GAIN BANDWIDTH PRODUCT (fT)
AS A FUNCTION OF
COLLECTOR CURRENT
Ves
V
30V
0
'A =;>S"C
V
0/
/
=lkHl
~ 2S'C
o
,
I I
,
.,
, '"
o Oi,
0
Ie lEACH TRANSISTOR) "
-
r-
h,e
,
0
OIFFERENTIAl CONFIGURATION
Vee ~ 30 V
f::::'" .L
~ l:::' '.~~"
o.!::,
-
0
,
ee -30V
f
TA
""'- /
.....- ......
.....-f-"
TA = 2Soc
,:;1["
h;:-
0.5
1
III
51020
FREQUENCY -
COLLECTOR CURRENT - rnA
COLLECTOR CURRENT rnA
INPUT ADMITTANCE (Yl1)
AS A FUNCTION OF
FREQUENCY
OUTPUT ADMITTANCE (Y22)
AS A FUNCTION OF
FREQUENCY
DIFFERENTIAL CONFIGURATION
VCB =3.0V
~
~
-
1 25 mA
'A"n
DIFFERENTIAL CONFIGURATION
Vee ~ 30V
Ie (EACH TRANSISTOR)
7
TA
921V
/
'i'!'K-
.1
0010.020.05010.2
Ie (EACH TRANSISTOR)
FORWARD TRANSFER
ADMITTANCE (Y21)
AS A FUNCTION OF
FREQUENCY
~
~
1 25 mA
50100 200
MHl
REVERSE TRANSFER
ADMITTANCE (Y12)
AS A FUNCTION OF
FREQUENCY
,-if
f- '
25"C
f--I--
w
I--f----
0.1
/
'n
'n
v
/
~.~.,~±t~t;t±f,~,ro:,to!t,to=wtoj,oo.
00001
0.01
0.1
50 100200
FREQUENCY _ MHz
FREQUENCY -
MHz
TYPICAL AC CHARACTERISTICS FOR EACH CASCODE AMPLIFIER FOR /lA3026/3054
FORWARD TRANSFER
ADMITTANCE (Y21)
AS A FUNCTION OF
FREQUENCY
INPUT ADMITTANCE (Yll)
AS A FUNCTION OF
FREQUENCY
'r-"~-'-'"r-r-T;Tr-r-'
- ;TC:G; ~cv= 2.5 mA++--+-+ttt-t-ff
'I
5-TA
'"
2S'C
\
VI
-20
Vee
=
3 V
STAGE Ie =
1-+-+++-+""fRf-"'f'il
-4°0,';-.,-,'::::,:"'";"C;;'C-7-:-..Ll!;-~f.;-l-":,l,,;-=:':::00:-:!.200
REVERSE TRANSFER
ADMITTANCE (Y12)
AS A FUNCTION OF
FREQUENCY
OUTPUT ADMITTANCE (Y22)
AS A FUNCTION OF
FREQUENCY
Ves • , v
I
STAGE Ie
'i-J
t-t-
IJ ,
Vea - 3 V
_~~AGE Ie - 25 mA
922
T A ~ 25°C
_·I--+-+++-+A~
1
1
\
1
I
000 1
01
51020
9-13
'"
~t-
b,;2= F
FAIRCHILD. p,A30XX SERIES
TYPICAL PERFORMANCE CURVES FOR MA3026/3054 (Cont'd)
OFFSET VOLTAGE CHARACTERISTIC
AS A FUNCTION OF
AMBIENT TEMPERATURE
FOR DIFFERENTIAL PAIRS
STATIC BASE-TO-EMITTER VOLTAGE
CHARACTERISTIC AND INPUT OFFSET
VOL TAGE FOR DIFFERENTIAL PAIRS
AS A FUNCTION OF EMITTER CURRENT
8
Ves
l
= 3.~y
TA - 25'C
I
7
..... V
Vee
3
.....-
I
/
/ ,
3
1
HH--+-+-+-+-I--:I
,
/
6
INPUT OFFSET VOLTAGE ~ IV SE , - VBEij
6
o. ,
75
100
I II
I II AI
1'11
I II
,
I
0
0.01
INPUT OFFSET CURRENT FOR
MATCHED DIFFERENTIAL PAIRS
AS A FUNCTION OF
COLLECTOR CURRENT
6~~~8_-7:-F
,
,
6
,
,
!
I
./
6
,
,
0.0
00'
II
I
0.05 0.1
0.2
0.5
1
COLLECTOR CURRENT - rnA
AMBIENT TEMPERATURE _ °C'
COMMON MODE REJECTION
RATIO
SINGLE STAGE VOLTAGE
GAIN
0
I
'",
I
I
I
r--
1---,
"",
SIGNAL INPUT VOLTAGE
0--
TWO-STAGE VOLTAGE
GAIN
0
6
----.....
lOmVrms.
0
/'"
!
0
/
0
/
-c-.
6
Vee= +12 v
0
\
6
80
0
o
DC BIAS VIL TAGE ON PINS 8,11 _ V
Vx
Vee
~
\.
-
6
DC BIAS VOLTAGE ON PINS 8, 11 - V
0
iEE:~ k6H~
SIGNAL INPUT VOLTAGE
6
I
I
I
9-14
1\
\
DC BIAS VOLTAGE ON PINS 2. 3 AND 8,11 - V
Test setup
Test setup
mv r1ms
\
O. 1 I'F
Pin numbers are shown forj3054 (DIP) only.
I
1
0
+12 V
"
Test setup
\
6
FAIRCHILD. ,uA30XX SERIES
IlA3036
•
•
•
MATCHED TRANSISTOR PERFORMANCE
LOW NOISE PERFORMANCE
200 MHz GAIN BANDWIDTH PRODUCT
APPLICATIONS
•
Stereo Phonograph Preamplifiers
•
•
Low level Stereo and Single Channel Amplifier Stages
Low noise, Emitter-follower Differential Ampl ifiers
•
Operational Amplifier Drivers
ABSOLUTE MAXIMUM RATINGS (For Each Transistor)
Power Dissipation
300mW
300mW
Any One Transistor
Total For Array
Temperature Range
_55° C to +125° C
_65° C to +200° C
Operating Temperature
Storage Temperature
The following ratings apply for each transistor in the array
Collector-to-Emitter Voltage, VCEO
Collector-to-Base Voltage, VCBO
Emitter-to-Base Voltage, VEBO
Collector Current, IC
15 V
30 V
5V
50mA
ELECTRICAL CHARACTERISTICS FOR IlA3036: TA = 25°C unless otherwise specified
SYMBOL
ICBO
ICEO
V(BR)CEO
V(BR)CBO
V(BR)EBO
MIN
TYP
MAX
UNITS
VCB= 5 V, IE =0
VCE=15V,IB=0
I C = 1 mA, I B = 0
IC= 101lA, IE=O
IE = 101lA, IC=O
15
30
5.0
20
44
6.0
0.5
5.0
-
IlA
IlA
V
V
V
ICl or IC3 = 1 mA
30
82
-
-
Emitter-ta-Base Breakdown Voltage
IE2 or IE4 = 10llA
10
12.6
-
V
Static Forward Current-Transfer Ratio
ICl + IC2 }
= 1 mA
or
1000
4540
-
-
f = 1 kHz
-
-
ICl or IC3= 1 mA
-
82
2.6
7.0
-
kn
Ilmho
-
9.8 x 10-5
-
-
1300
82
108
-
-
-
-
kn
Ilmho
2.7 x 10-3
-
-
CHARACTERISTICS
CONDITIONS
For Each Transistor (01,02,03, <4)
Collector Cutoff Current
Collector Cutoff Current.
Coliector-to:Emitter Breakdown Voltage
Collector-to-Base Breakdown Voltage
Emitter-to-Base Breakdown Voltage
-
For Either Input Transistor (01 or 03)
hFE
Static Forward Current-Transfer Ratio
For Either Darlington Pair (01,02 or 03,
V(BR)EBO(D)
hFE(D)
<4)
IC3 + IC4
hfe
hie
hoe
h re
For Each Input Transistor (01 or 03)
Short Circuit Forward Current-Transfer Ratio
Short Circuit Input Resistance
Open Circuit Output Conductance
Open Circuit Reverse Voltage-Transfer Ratio
For Either Darlington Pair (01,02 or 03,
hfe(D)
hie(D)
hoe(D)
hrelD)
EN
<4)
-
Open Circuit Output Conductance
ICl + IC2 }
or
= 1 mA
Open Circuit Reverse Voltage-Transfer Ratio
IC3 + IC4
-
f=100Hz
f = 1 kHz
f = 10 kHz
-
0.2
0.05
0.012
3.0
0.3
0.1
-
0.68 + j 7.9
4.4 + j 5.95
1.94 + j 2.64
-
mmho
mmho
mmho
-
Negligible
-
mmho
150
1.71 + j 2.8
3.96 + j 2.6
200
-
mmho
mmho
-
MHz
Short Circuit Forward Current-Transfer Ratio
Short Circuit Input Resistance
Noise Voltage
f = 1 kHz
IlV (rm s)
f(Hz
'./fTHz1
For Either Input Transistor (01 or 03)
Yfe
Forward Transfer Admittance
Vie
Input Admittance (Output Short Circuited)
Output Admittance (I nput Short Circuited)
Yoe
Reverse Transfer Admittance
Yre
YielD)
Yoe(D)
fT(D)
f = 50 MHz
I Cl or I C3 = 2 mA
(Input Short-Circuited)
For Either Darlington Pair (01,02, or 03, <4)
Input Admittance (Output Short Circuited)
Output Admittance (Input Short Circuited)
Gain-Bandwidth Product
f = 50 MHz
ICl + IC2 }
or
= 2 mA
IC3 + IC4
9-15
II
FAIRCHILD. ,uA30XX SERIES
IlA3039
•
•
•
EXCELLENT DIODE MATCHING - 1 mV TYP.
REVERSE RECOVERY TIME - 1 ns TYP.
LOW DIODE CAPACITANCE - 0.65 pF @VR= -2 V
APPLICATIONS
• Balanced Modulators or Demodulators
• Ring Modulators
• High Speed Diode Gates
•
Analog Switches
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (See note I
Any One Diode Unit
Total for Device
Temperature Range
Operating Temperature
Storage Temperature
Voltages and Currents
Peak Inverse Voltage, PIV for: 01 ·05
06
Peak Diode·to·Substrate Voltage, VOl for 01 - 05
(term. 1,4,5,8 or 12 to term. 10)
DC Forward Current, IF
Peak Recurrent Forward Current, If
Peak Forward Surge Current, If Isurge)
100mW
600 mW
_55" C to +125" C
_65" C to +200" C
5V
0.5 V
+20,-1 V
25 rnA
100 rnA
100 rnA
ELECTRICAL CHARACTERISTICS FOR MA3039: For each diode unit, TA = 25"C unless otherwise specified
SYMBOL
CHARACTERISTICS
CONDITIONS
MIN
TYP
MAX
UNITS
VF
DC Forward Voltage Drop
IF = 50 MA
1 mA
3mA
10mA
-
0.65
0.73
0.76
0.81
0.69
0.78
0.80
0.90
V
V
V
V
BV
DC Reverse Breakdown Voltage
IR = -10MA
5.0
7.0
-
V
IR = -10MA
20
-
-
V
VR = -4 V
-
0.016
100
nA
VR=-10V
-
0.022
100
nA
Magnitude of Diode Offset Voltage
(Difference in DC Forward Voltage
Drops of any Two Diode Units)
IF = 1 mA
-
0.5
5.0
mV
Temperature Coefficient of IVFl - VF21
IF = 1 rnA
-
1.0
-
MV/"C
Temperature Coefficient of Forward Drop
IF = 1 rnA
-
-1.9
-
mVI"C
VF
DC Forward Voltage Drop for
Anode-to·Substrate Diode IDS)
IF = 1 mA
-
0.65
-
V
trr
Reverse Recovery Time
IF = 10 rnA, IA'= 10 rnA
-
1.0
-
ns
RD
Diode Resistance
f=l kHz,IF=l rnA
25
30
45
D.
CD
Diode Capacitance
VR=-2V,IF=0
-
0.65
-
pF
COl
Diode-ta-Substrate Capacitance
VOl = +4 V, IF = 0
-
3.2
-
pF
DC Reverse Breakdown Voltage
BVS
Between any Diode Unit and Substrate
DC Reverse (Leakage) Current
IR
DC Reverse I Leakage) Current
IR
Between any Diode Unit and Substrate
IVFl . VF21
t.IVFl . VF21
t.T
t.VF
-t.T
NOTE: Derate at 5.7 mW/oC for TA
> 55°C.
9-16
FAIRCHILD • JLA30XX SERIES
TYPICAL PERFORMANCE CURVES FOR tlA3039
DC FORWARD VOL TAGE DROP
(ANY DIODE) AND DIODE OFFSET
VOLTAGE AS A FUNCTION OF
DC FORWARD CURRENT
DC REVERSE (LEAKAGE) CURRENT
(DIODES 1,2,3,4,5)
AS A FUNCTION OF
TEMPERATURE
DIODE OFFSET VOLTAGE
(ANY DIODE) AS A FUNCTION OF
TEMPERATURE
5
~+1~-+-+-H+-+-~H+-17
-
4
3
2
--
IF - ,b rnA
-
.7
6
~~rH--~r+~-+~7frr~'
g
c
0.01
0.05 0.102
0.51
f- f-" o.~lmA
4
0.5 ~:tt:;t::::tJ:j~......t'=i-·Ll!-:l10
.3
2
,.....,-
, mA
0.5
75
".,
/
DC FORWARD CURRENT - rnA
AMBIENT TEMPERATURE _ "C
AMBIENT TEMPERATURE _ "C
DC FORWARD VOLTAGE DROP
(ANY DIODE) AS A FUNCTION OF
TEMPERATURE
DC REVERSE (LEAKAGE) CURRENT
BETWEEN DIODES (1,2,3,4,5)
AND SUBSTRATE AS A FUNCTION OF
TEMPERATURE
DIODE RESISTANCE
(ANY DIODE) AS A FUNCTION OF
DC FORWARD CURRENT
2
,
T~ _12~J: =
IF - 1rnA
f~l
kHz-
0
9
,
7
r-....
0
i'-
0
........
6
r-.....
5
/
2
5
o4
-75
.......
0
.......
,
25
50
75
100
25
AMBIENT TEMPERATURE _ °C
50
75
AMBIENT TEMPERATURE _
DIODE CAPACITANCE
(DIODES 1,2,3,4,5)
AS A FUNCTION OF
REVERSE VOLTAGE
0.01 0.02
100
0.050.10.2
1
"c
DIODE-TO-SUBSTRATE CAPACITANCE
AS A FUNCTION OF
REVERSE VOLTAGE
,
'r-,--,--r--r-,--r--r-,
7r-T~ -Jc-+--+-+--+--+-----l
7-T!-2S!C
,
11'-0
IF
~
0
5"-..,
r-3
-
2
,
0
DC REVERSE VOLTAGE ACROSS DIODe -
0.5
DC REVERSE VOLTAGE BeTWeEN
v
PINS " 4, 5, '8. OR 12 AND SUBSTRATE {PIN 10)
9-17
5
10
I
FAIRCHILD. ILA30XX SERIES
IlA3045/3046/3086
•
•
•
LOW INPUT OFFSET VOLTAGE
WIDEBAND OPERATION
LOW NOISE
APPLICATIONS
• General Use in all Types of Signal Processing Systems Operating
Anywhere in the Frequency Range From DC to VHF
• Custom Designed Differential Amplifiers
• Temperature Compensated Amplifiers
ABSOLUTE MAXIMUM RATINGS (For Each Transistor)
Power Dissipation (N·ote 1)
Each Transistor
300mW
At TA = 25°C
At TA = 25°C to 511°C
300mW
At TA = 25°C to 75°C
Voltages and Currents
15 V
Collector,to-Emitter Voltage, VCEO
Collector-to-Base Voltage, VCBO
20V
Collector-to-Substrate Voltage, VCIO (Note 2)
20V
Emitter-to-Base Voltage, VEBO
5V
Collector Current, IC
50mA
Temperature Range
Operating Temperature
Storage Temperature
9-18
I'A3045
Total Package
750mW
I'A3046/3086
Each Transistor Total Package
300mW
750 mW
300 mW
750mW
750 mW
15V
20 V
20V
5V
50mA
(3046) O°C to +85°C
(3086) -40° C to +85° C
_55°C to +125"C
FAIRCHILD. p,A30XX SERIES
ELECTRICAL CHARACTERISTICS FOR "A3045/3046: TA = 25°C unless otherwise specified
SVMBOL
TVP
IC=10"A,IE=0
20
60
V(BR)CEO Collector-to-Emitter Breakdown Voltage
IC - 1 mA, IB = 0
15
24
V
Collector-ta-Substrate Breakdown Voltage
IC = 10 itA. IC = 0
20
60
V
V(BR)EBO
Emitter-to-Base Breakdown Voltage
IE = 10"A,IC=0
5.0
ICBO
Collector Cutoff Current
VCB=10V,IE=0
0.002
40
nA
ICEO
Collector Cutoff Current
VCE=10V,IB=0
See Curve
0.5
"A
2.0
"A
V(BR)CIO
hFE
CHARACTERISTICS
Static Forward Current-Transfer Ratio
(Static Beta)
CONDITIONS
MAX
MIN
V(BR)CBO Collector-to-Base Breakdown Voltage
VCE = 3 V
{IC= 10mA
IC= 1 mA
Q1 and Q2 11101 -11021
VBE
V
7.0
V
100
40
100
54
IC= 10"A
Input Offset Current for Matched Pair
UNITS
0.3
VCE=3V,IC=1 mA
0.715
{ IE = 1 mA
IE = 10 mA
V
Base-to-Emitter Voltage
VCE = 3 V
Magnitude of Input Offset Voltage for
Differential Pair IVBE1 - VBE21
VCE = 3 V, IC =1 mA
0.45
5.0
mV
VCE=3V,IC=1 mA
0.45
5.0
mV
VCE =3 V,IC= 1 mA
-1.9
mV/oC
IB=1mA,IC=10mA
0.23
V
VCE = 3 V, IC = 1 mA
1.1
"V/oC
3.25
dB
f= 1 kHz, VCE =3 V,IC= 1 mA
110
3.5
15.6
1.8x10-4
kr1
"mba
f = 1 MHz, VCE = 3 V, IC = 1 mA
31-j 1.5
0.3+jO.04
O.OO1+j 0.03
Magnitude of Input Offset Voltage for
Isolated Transistors IVBE3 - VBE41,
0.800
IVBE4 - VBE51, IVBE5 - VBE31
,WBE
-IlT
Temperature Coefficient of
Base-to-Emitter Voltage
VCE(sat)
Coliector-to~Emitter Saturation Voltage
1IlV101
--IlT
Temperature Coefficient:
NF
Low Frequency Noise Figure
Magnitude of Input-Offset Voltage
f= 1 kHz, VCE =3V,IC= 100"A
RS = 1 kr1
Low Frequency, Small-Signal Equivalent-Circuit Characteristics:
hfe
hie
hoe
h re
Forward Current-Transfer Ratio
Short-Circuit Input Resistance
Open-Circuit Output Conductance
Open-Circuit Reverse Voltage-Transfer Ratio
Admittance Characteristics:
Vfe
Vie
Voe
V re
Forward Transfer Admittance
Input Admittance
Output Admittance
Reverse Transfer Admittance
See Curve
300
550
MHz
fT
Gain-Bandwidth Product
VCE=3V,IC=3mA
CEB
Emitter-ta-Base Capacitance
VEB=3V,IE=0
0.6
pF
CCB
Collector-to-Base Capacitance
VCB=3V,IC=0
0.58
pF
CCI
Collector-ta-Substrate Capacitance
VCS=3V,IC=0
2.8
pF
NOTES:
1 . .uA3046 and IJA3086 derate at 6.67 mW/oC for TA > 55°C, .uA3045 at 8 mW/oC for TA > 75°C.
2. Substrate (Pin 13) must be connected to the most negative voltage to maintain normal operation.
9-19
II
FAIRCHILD. p,A30XX SERIES
ELECTRICAL CHARACTERISTICS FOR IlA3086: TA ~ 25°C unless otherwise specified
SYMBOL
CHARACTERISTICS
CONDITIONS
MIN
TYP
MAX
UNITS
V(BR)CBO Collector-to-Base Breakdown Voltage
IC-10IlA, IE ~O
20
60
V(BR)CEO Collector-to-Emitter Breakdown Voltage
IC - 1 mA, IB - 0
15
24
V
IC-l0IlA,IC~0
20
60
V
5.0
V(BR)CIO
Collector-to-Substrate Breakdown Voltage
V(BR)EBO
Emitter-ta-Base Breakdown Voltage
IE~10IlA,IC~0
ICBO
Collector Cutoff Current
VCB - 10 V, IE ~ 0
ICEO
Coliector Cutoff Current
VCE
~
~
10 V, IB
0
IC~10mA
hFE
Static Forward Current-Transfer Ratio
(Static Beta)
VCE
~
3 V
IC~
~
IC
Input Offset Current for Matched Pair
Ql and Q2 11101 - 11021
VBE
Base-ta-Emitter Voltage
Magnitude of Input Offset Voltage for
Differential Pair IVBEI - VBE21
Magnitude of Input Offset Voltage for
Isolated Transistors IVSE3 - VBE41,
VCE
~
3V,
VCE
~
3V
IC~
7.0
V
0.002
100
nA
See Curve
5.0
IlA
100
1 mA
40
10llA
100
54
1 mA
IlA
IE
~
1 mA
0.715
IE
~
10mA
0.800
VCE~3V,IC~1
V
V
mA
mV
VCE~3V,IC~lmA
mV
IVBE4 - VBE51, IVBE5 - VBE31
AVBE
AT
Temperature Coefficient of
Base-to-Emitter Voltage
VCE
~
3 V, IC
~
1 mA
VCE(sat)
Collector-ta-Emitter Saturation Voltage
IB~l mA,IC~10mA
IAVlOl
--AT
Temperature Coefficient:
Magnitude of Input-Offset Voltage
VCE
NF
Low Frequency Noise F:igure
~3
V,
IC~
f~
1 kHz, VCE
RS
~
-1.9
mV/oC
0.23
V
1 mA
~
3 V,
Ilvrc
IC~
100llA
1 kn
3.25
dB
110
3.5
15.6
.umbo
Low Frequency, Small-Signal Equivalent-Circuit Characteristics:
hfe
hie
hoe
h re
Forward Current-Transfer Ratio
Short-Circuit Input Resistance
Open-Circuit Output Conductance
Open-Circuit Reverse Voltage-Transfer Ratio
f
~
1 kHz, VCE
~
3 V, IC
~
1 mA
kn
1.8xl0-4
Admittance Characteristics:
Yfe
Yie
Y oe
Y re
Forward Transfer Admittance
Input Admittance
Output Admittance
f
~
1 MHz, VCE
~
3 V, IC
~
31-j 1.5
0.3+jO.04
0.001 +j 0.03
1 mA
Reverse Transfer Admittance
See Curve
fT
Gain-Bandwidth Product
VCE~3V,IC~3mA
550
MHz
CEB
Emitter·to~Base
VES ~3 V, IE-O
0.6
pF
CCB
Coliector·to·Base Capacitance
VCB~3V,IC~0
0.58
pF
CCI
Collector·to·Substrate Capacitance
VCS-3V,IC-0
2.8
pF
Capacitance
9-20
300
FAIRCHILD. /LA30XX SERIES
TYPICAL PERFORMANCE CURVES FOR J.lA3045/3046/3086
COLLECTOR-TO-BASE CUTOFF
CURRENT AS A FUNCTION OF
AMBIENT TEMPERATURE
FOR EACH TRANSISTOR
COLLECTOR-TO-EMITTER CUTOFF
CURRENT AS A FUNCTION OF
AMBIENT TEMPERATURE
FOR EACH TRANSISTOR
STATIC FORWARD CURRENTTRANSFER AND BETA RATIO FOR
TRANSISTORS Q1, Q2 AS A
FUNCTION OF EMITTER CURRENT
"0
I-- le"O
o
,
,
VC8~
15\'
'ov
~~ I-
'v- I- I-
,
v~-mv
TA
m
2S·C
1\,
"V
/
5.,0-1
5xl0-2
5.'0- 1
5.,0-3
5.,0 2
5.'0-4
5.'0- 3
V
1"""1 1""'1
hFE2 0 "
hFEI
1/
2
0
3
.
,0 V
0010.02
AMBIENT TEMPERATURE
_·c
AMBIENT TEMPERATURE
INPUT OFFSET CURRENT FOR
MATCHED TRANSISTOR PAIR
01, Q2 AS A FUNCTION OF
COLLECTOR CURRENT
5
60
.
,
O.
,
~.
,
~~
~ ~ "'-
~
2
6
-
v
O.02~Etm
INPUT OFFSET VOLTAGE
Ir T II
n~O~'~0~02~0~.0~'~0.~'~0~2~0~,~,I-~~-7.
Ie -
COLLECTOR CURRENT -
3
2
~
,
g
~
~
~
"
-
VeE'" 3.0 V
.-
.~
~
CA""''''''''6I3086 0
0.51
2
10
AMBIENT TEMPERATURE -
·C
,
.
-"
100
~
'c
GAIN-BANDWIDTH PRODUCT
AS A FUNCTION OF
COLLECTOR CURRENT
..-
Vce-J·av
T A "'2S·C
~+-++-+-tl-r-+-++---l
.,., I
01~le
75
~
o.
NORMALIZED h PARAMETERS
AS A FUNCTION OF
COLLECTOR CURRENT
~ I--"
50
VeE'" 30 V
AMBIENT TEMPERATURE -
0.1 rnA
" "
5
0
BOO
0
0
~
./
rnA
INPUT OFFSET VOLTAGE FOR
DIFFERENTIAL PAIR AND PAIRED
ISOLATED TRANSISTORS AS A
FUNCTION OF AMBIENT TEMPERATURE
.
0050102
1
BASE-TO-EMITTER VOLTAGE
CHARACTERISTIC AS A FUNCTION OF
AMBIENT TEMPERATURE
FOR EACH TRANSISTOR
V·
FOR DIFFERENTIAL PAIR AND
PAIRED ISOLATED TRANSISTORS
05
EMITTER CURRENT - mA
STATIC BASE-TO-EMITTER VOLTAGE
AND INPUT OFFSET VOLTAGE
AS A FUNCTION EMITTER CURRENT
veE ~ 3.0 V
TA - 2S·C
0.050102
_·c
0010.02005010.2
05
1
COLLECTOR CURRENT - mA
9-21
•
FAIRCHILD. JLA30XX SERIES
TYPICAL PERFORMANCE CURVES FOR J.jA3045/3046/3086 (Cont'd)
NOISE FIGURE
AS A FUNCTION OF
COLLECTOR CURRENT
NOISE FIGURE
AS A FUNCTION OF
COLLECTOR CURRENT
f--
I I~~
veE n 3.0 V
RS~ 5OO.Q
TA - 2S'C
I
5
r---
.t",
<;tr-
n
~.
0
r--..
5~
1/
0'<~<';
5~
I--
10kHz
I
0
I
10Hl
2SOC
«.-00«-"""
20
r7V
,~
l/lkHZ
10kHz
0
~
I
INPUT ADMITTANCE
AS A FUNCTION OF
FREQUENCY
COMMON EMITTER CIRCUIT, SASE INPUT
~ 9fe
3.0 V
/
FORWARD TRANSFER ADMITTANCE
AS A FUNCTION OF
FREQUENCY
-
=
~.
lkt;..-V
r--- Vl
TA
~
0
V
I
I I.~
I,,~,
--1-----1--+1 ,,:,
I------++++-+-l--c v)- f---
25 -
0'
6'
~,
~~
~ VeE
AS·
0~·7
5
0"L'~
3Or----r---r----r,--,------r----r-,-,--,
o~
veE - 30 V
AS - 1~
TA = 25 C
NOISE FIGURE
AS A FUNCTION OF
COLLECTOR CURRENT
- - v:: : 2S'C
"
f-----
COMMON
EMITTER CIRCUIT, BASE INPUT
TA - 25°C
-I-+I+-++l-+-I---l-l
IC- lOrnA
I,
II
\
/
'"
0-
v
.L.
REVERSE TRANSFER ADMITTANCE
AS A FUNCTION OF
FREQUENCY
OUTPUT ADMITTANCE
AS A FUNCTION OF
FREQUENCY
COMMON
COMMON - EMITTER CIRCUIT, BASE INPUT.
-
t--H-H-+-+-t+t--H
1.0 mAt--H-H-+-+-t+t--+--iI
boo
05_VeE-3.OV
Vce-3.0V
4 -
Ie -
EMITTER CIRCUIT, BASE INPUT
~TA-259C
TA -25°C
Ie = 1.0 rnA
I
I I
9re IS SMALL AT F1REQUENCIES
LESS THAN 500 MHz
I
IJ
II
-, L,-.LLl.,L-----,L,-,L-LLJ,50~1J,OO--,J200
51020
9-22
7
JJA726
TEMPERATURE-CONTROLLED DIFFERENTIAL PAIR
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The /lA 726 is a Monolithic Transistor Pair in a high thermal-resistance
package, held at a constant temperature by active temperature regulator circuitry. The transistor pair
CONNECTION DIAGRAM
10-PIN METAL CAN
(TOP VIEW)
PACKAGE OUTLINE 5U
PACKAGE CODE H
displays the excellent matching, close thermal coupling and fast thermal response inherent in
monolithic construction. The high gain and low standby dissipation of the regulator circuit permits
tight temperature control over a wide range of ambient temperatures. It is intended for use as an
input stage in very~low-drift de amplifiers, replacing complex chopper-,stabilized amplifiers. It is also
useful as the nonlinear element in logarithmic amplifiers and multipliers where the highly predictable
exponential relation between emitter-base voltage and collector current is employed. The device is
constructed on a single silicon chip using the Fairchild Planar* process.
E2
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
81
v+
E1
NC
-55°C to +125°C
Military (/lA726)
Commercial (/lA726C)
O°C to +85°C
-65°C to +150°C
Storage Temperature Range
300°C
Pin Temperature (Soldering, 60 seconds)
Supply Voltage
±18V
Internal Power Dissipation
v-
500mW
MAXIMUM RATINGS FOR EACH TRANSISTOR
Collector-to-Emitter Voltage, VCEO
30V
Collector-to-Sase Voltage, VCSO
40V
Collector-to-Substrate Voltage, VCIO
40V
ORDER INFORMATION
PART NO_
TYPE
/lA726
/lA726HM
/lA726C
/lA726HC
5V
Emitter-to-Sase Voltage, VESO
5mA
Collector Current, IC
EQUIVALENT CIRCUIT
r------.---------o v+
TEMP ADJ
R2
R,
21kQ
lko
0,
6.2V
R3
02
4.8kQ
6.2V
R,
2'0
R5
Q5
100
L-______________~------~------------------~__ov-
5
*Planar is a patented Fairchild process.
9-23
•
FAIRCHILD. IJ.A726
ELECTRICAL CHARACTERISTICS: -55"C <;; TA <;; +125"C, Vs = ±15V, Radj = 62kn unless otherwise specified.
CONDITIONS
TYP
MAX
UNITS
1.0
2.5
mV
10
50
nA
IC - 100MA, VCE - 5V
50
200
nA
Ic - 10MA, VCE - 5V
50
150
nA
IC - 100MA, VCE - 5V
250
500
nA
IC - 10MA, 5V <;; VCE <;; 25V, RS';;; 100kn
0.3
6.0
mV
IC - 100MA, 5V <;; VCE <;; 25V, RS <;; 10kn
0.3
6.0
mV
0.2
1.0
MVrC
0.2
1.0
MV/"C
CHARACTER ISTICS
I nput Offset Voltage
Input Offset Current
Average Input Bias Current
Offset Voltage Change
Input Offset Voltage Drift
Input Offset Voltage Drift
10MA <;; IC <;; 100MA, VCE
IC - 10MA, VCE
MIN
= 5V, RS <;; 50n
= 5V
10MA <;; IC <;; 100MA, VCE - 5V,
RS <;; 50n, +25°C <;; TA <;; +125°C
10MA <;; IC <;; 100MA, VCE - 5V,
RS <;; 50n, _55°C <;;TA <;; +25°C
IC - lOMA, VCE - 5V
10
pArC
IC - 100MA, VCE - 5V
30
pA/oC
Supply Voltage Rejection Ratio
10MA <;; IC <;; 100MA, RS <;; 50n,
25
MV/V
Low Frequency Noise
IC 10MA, VCE - 5V, RS <;; 50n
BW = .001 Hz to 0.1 Hz
4.0
MVP-P
Broadband Noise
IC = 10MA, VCE = 5V, RS <;; 50n
BW = 0.1 Hz to 10kHz
10
MVP-P
5.0
MV/week
I nput Offset Current Drift
Long~term
Drift
10MA <;; IC <;; 100MA, VCE
= 5V, RS <;; 50n, TA = 25"C
High Frequency Current Gain
f - 20MHz, IC - 100MA, VCE - 5V
Output Capacitance
IE - 0, VCB - 5V
1.0
Emitter Transition Capacitance
IE - 100MA
1.0
Collector Saturation Voltage
IB - 100MA, IC - 1 mA
0.5
1.0
V
TYP
MAX
UNITS
1.0
3.0
mV
10
100
nA
IC - 100MA, VCE - 5V
50
400
nA
Ic - 10MA, VCE - 5V
50
300
nA
= 100MA, VCE = 5V
Ic = 10MA, 5V <;; VCE <;; 25V, RS <;; 100kn
IC = 100MA, 5V <;; VCE <;; 25V, RS <;; 10kn
250
1000
nA
0.3
6.0
mV
0.3
6.0
mV
IC - 100MA, VCE - 5V, RS <;; 50n
0.2
2.0
MV/oC
IC
= 10MA, VCE = 5V
= 100MA, VCE = 5V
IC = 100MA, RS = 50n
10
pA/oC
IC
30
pA/"C
1.5
3.5
pF
pF
IJ.A726C
ELECTRICAL CHARACTERISTICS: O°C <;; TA <;; +85°C, Vs
CHARACTER ISTICS
Input Offset Voltage
I nput Offset Current
Average Input Bias Current
Offset Voltage Change
Input Offset Voltage Drift
I nput Offset Current Drift
Supply Voltage Rejection Ratio
Low Frequency Noise
Broadband Noise
=
±15V, Radj
=
75kn unless otherwise specified.
CONDITIONS
10MA <;; IC <;; 100MA, VCE
IC
MIN
= 5V, RS <;; 50n
= 10MA, VCE = 5V
IC
IC - 10MA, VeE - 5V, RS <;; 50n,
BW
= 0.001 Hz to 0.1 Hz
Ie -10MA, VeE - 5V, RS';;; 50n,
BW = 0.1 Hz to 10kHz
= 5V, RS <;; 50n, TA = 25°C
25
MV/V
4.0
MVP-P
10
MVp-P
5.0
MV/week
Long-Term Drift
IC - 100MA, VCE
High Frequency Current Gain
f - 20MHz, IC - 100MA, VCE- 5V
Output Capacitance
IE - 0, VCB - 5V
1.0
Emitter Transition Capacitance
IE - 100MA
1.0
Collector Saturation Voltage
IS - 100,uA, Ie - 1 rnA
0.5
9-24
1.5
3.5
pF
pF
1.0
V
FAIRCHILD. IlA726
TYPICAL PERFORMANCE CURVES FOR J.l.A726
CURRENT GAIN AS A FUNCTION
OF COLLECTOR CURRENT
SUPPL Y CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
Wr-r-'-'-'--.-'-.-.~-'
f-+-+-+-+++- ~~~i ;~~Q ~
16 f-+-+-+-+++---+'-+-I-I
~
11
~
1'--
6
I
I
""'-.l
I
~
iil
'"
4
i
0
110'
IIJ),JA
-60
lOrnA
lmA
-10
COLLECTOR CURRENT
I
10
60
Tf.MPERATURE _QC
'" ""'-.l
100
140
TYPICAL PERFORMANCE CURVES FOR J.l.A726C
CURRENT GAIN AS A FUNCTION
OF COLLECTOR CURRENT
SUPPL Y CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
10
1001
f-+-+-+-+-+-+V~
f--H++--+-I+f+~~£~:~;:V _
800
<,\SV
RiIlj
ROOj"m.Q-
~
r-H-t+--+--++++ o°c S TA~ 8SoC -
~
i
100/
8.0
~
6.0
_
7SkQ
",1
-r,
4.0
'1"--,
1.0
"'-
0
10
0
COlUCTOR ClJRRENT
40
60
TEMPERATlJRE -"C
80
100
I
TYPICAL X1000 AMPLIFIER CIRCUIT
+15V
r-----,
J- Radj
IN~bA
IA'
+15V
J'I
75kQ
25kQ
25kQ
''"~'::~'':'~~c--~__R_1_-.._R_2_-=t:t~i~
-=-
*'.-' _~
I 6_2do PF
-lSV
-15V
5nFL Rs
C1
75kQ
R7
Q1r~1B
2N2060
'----~_
-15V
50kQ
ALL RESISTORS 1%
9-25
1.5kQ
50Q
Rg
Eout
IJA555
SINGLE TIMING CIRCUIT
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The IlA555 Timing Circuit is a very stable controller for producing
accurate time delays or oscillations. In the time delay mode, the delay time is precisely controlled by
one external resistor and one capacitor; in the oscillator mode, the frequency and duty cycle are both
accurately controlled with two external resistors and one capacitor. By applying a trigger signal, the
timing cycle is started and an internal flip-flop is set, immunizing the circuit from any further trigger
signals. To interrupt the timing cycle a reset signal is applied ending the time-out.
CONNECTION DIAGRAMS
8-PIN MINI DIP
(TOP VIEW)
PACKAGE OUTLINE 9T
The output, which is capable of sinking or sourcing 200 mA, is compatible with TTL circuits and can
drive relays or indicator lamps.
GND
•
•
•
•
•
•
•
•
MICROSECONDS THROUGH HOURS TIMING CONTROL
ASTABLE OR MONOSTABLE OPERATING MODES
ADJUSTABLE DUTY CYCLE
200 mA SINK OR SOURCE OUTPUT CURRENT CAPABILITY
TTL OUTPUT DRIVE CAPABILITY
TEMPERATURE STABILITY OF 0.005% PER °c
NORMALLY ON OR NORMALLY OFF OUTPUT
DIRECT REPLACEMENT FOR SE555/NE555
TRIGGER
OUT
RESET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Power Dissipation (Note 1)
Operating Temperature Ranges
IlAS5STC/HC
IlA55SHM
Storage Temperature Range
Pin Temperature
Plastic Mini DIP(9T) (Soldering, 10 s)
Metal Can (ST) (Soldering, 60 5)
BLOCK DIAGRAM
Vee --()---t"-
THRESHOLD
CONTROL
VOLTAGE
+18 V
600mW
O°C to +70°C
-SSoC to +12SoC
-65°C to +150°C
260°C
300°C
------1
--<)----+--1
..-----(>--
ORDER INFORMATION
TYPE
PART NO.
IlA555
IlA555TC
8-PIN TO-lOa
(TOP VIEW)
PACKAGE OUTLINE 5T
+Vcc
DISCHARGE
--0----+--1
5kn
FLIPFLOP
S
Q
9ESET
INHIBIT!
RESET
TRIGGER
--0---+--1
RESET~_
o[>------¢--
----(-:>---_-_-_-_----..
_____
~
GND
9-26
OUTPUT
ORDER INFORMATION
TYPE
PART NO.
IlA555
IlA555HM
IlA555HC
IlA555
FAIRCHILD • JLA555
ELECTRICAL CHARACTERISTICS: TA= 25°C, VCC= +5.0 V to +15 V, unless otherwise specified
I'A555HM
CHARACTER ISTICS
TEST CONDITIONS
MIN
Supply Voltage
4.5
VCC = 5.0 V, RL =
Supply Current
TYP
~
I'A555TC/HC
MAX
MIN
18
4.5
TYP
MAX
UNITS
16
V
3.0
5.0
3.0
6.0
mA
10
12
10
15
mA
0.5
2.0
1.0
%
30
100
50
ppmfC
0.05
0.2
VCC=15V,RL=~
LOW State (Note 1)
Timing Error
Initial Accuracy
RA,RB=l kflto 100 kfl
Drift with Temperature
C = O.lI'F (Note 2)
Drift with Supply Voltage
Threshold Voltage
Trigger Voltage
2/3
V
VCC=15V
4.8
5.0
5.2
5.0
1.45
1.67
1.9
1.67
V
0.5
I'A
0.5
Reset Voltage
0.4
Reset Current
Control Voltage Level
%V
X VCC
VCC=5.0V
Trigger Current
Threshold Current
0.1
2/3
0.7
1.0
0.4
0.1
Note 3
0.7
1.0
0.1
V
mA
0.1
0.25
0.1
0.25
VCC-15V
9.6
10
10.4
9.0
10
11
V
VCc=5.0V
2.9
3.33
3.8
2.6
3.33
4.0
V
I'A
VCC-15V
0.1
0.15
0.1
0.25
V
0.4
0.5
0.4
0.75
V
IS INK -100 mA
2.0
2.2
2.0
2.5
V
ISINK = 200 mA
2.5
ISINK = 10 mA
ISINK = 50 mA
Output Voltage Drop (LOW)
-
2.5
V
VCC=5.0V
ISINK = 8.0 mA
0.1
0.25
V
ISINK = 5.0 mA
0.25
0.35
V
ISOURCE = 200 mA
12.5
Vce=15V
Output Voltage Drop (HIGH)
12.5
V
ISOURCE = 100 mA
VCC=15V
13
13.3
12.75
13.3
V
Vec= 5.0 V
3.0
3.3
2.75
3.3
V
Rise Time of Output
100
100
ns
Fa II Ti me of Output
100
100
ns
NOTES:
1. Supply Current is typically 1.0 rnA less when output is HIGH.
2. Tested at Vee = 5.0 V and Vee = 15 V.
3. This will determine the maximum value of RA + RS' For 15 V operation, the max total R == 20 MO.
4. For operating at elevated temperatures the device must be derated based on a +125° C maximum junction temperature and a thermal
resistance of +45 0 C/W junction to case for TO-5 and +150° C/W junction to ambient for both packages.
9-27
I
FAIRCHILD • J.tA555
TYPICAL PERFORMANCE CURVES
MINIMUM PULSE WIDTH
REQUIRED FOR TRIGGERING
0
./
5
VV
0-
V I-
l
5~
1-"7
e
0.4
r-
2SOC
a
6
§::
: -51~ICCi lr
4
10
50
SOURCE CURRENT - rnA
SUPPLY VOLTAGE.- V
LOW OUTPUT VOLTAGE
AS A FUNCTION OF
OUTPUT SINK CURRENT
II
Vcc- 5V
2SoC
,
0
LOW OUTPUT VOLTAGE
AS A FUNCTION OF
OUTPUT SINK CURRENT
0
I
I
1.0
~ n
0
0.1
I
~
,/
LOWEST VOLTAGE LEVeL OF TRIGGER PULSE - X Vee
0
U
~ 1.
./
0
,
I.
~1 4
./V
,/
'1S· C
k:::;:: ~ ~
01--
-
0
>
,
~1 6
,/
0
5
HIGH OUTPUT VOLTAGE
AS A FUNCTION OF
OUTPUT SOURCE CURRENT
TOTAL SUPPLY CURRENT AS A
FUNCTION OF SUPPL Y VOLTAGE
LOW OUTPUT VOL TAGE
AS A FUNCTION OF
OUTPUT SINK CURRENT
Vcc- IOV
VCC"15V
I-----
I
...-
J
/
25 0 ,
0.1
0.0 I
1.0
/
f---t--t++-...--7"F--t-H+-----I
v
O.O\'::.O--'--'-L.L-~IO:--L-L..Ll--:!,OO
100
SINK CURRENT - rnA
SINKCURAENT-mA
1.01 5
6
0
0
1.005
1.000
5
\
\
-,....
-
PROPAGATION DELAY
AS A FUNCTION OF
VOLTAGE LEVEL OF
TRIGGER PULSE
DELAY TIME
AS A FUNCTION OF
AMBIENT TEMPERATURE
DELAY TIME
AS A FUNCTION OF
SUPPLY VOLTAGE
V
---
- --
J
if\. ~V
I--
~;: ~ ~
I-- f-- f--
0."5
II--
0
,
5
~,
0
25
0
25
50
75
AMBIENT TEMPERATURE -'C
9-28
100
0.1
02
03
0.4
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE - X Vee
FAIRCHILD • ,uA555
EQUIVALENT CIRCUIT
FM
vcc~--~------~----------~~r-------~-------t--~------1r---r----~----,
THRESHOLD
OUTPUT
TRIGGERO-,'-----------f------t:'
RESET
DISCHARGE
o-''-------t;::
0-'-----,
GND~------~--~~------4---~--~----~~----~~~~----~
TYPICAL APPLICATIONS
MONOSTABLE OPERATION
In the monostable mode, the timer functions as a one-shot. Referring
to Figure 1 the external capacitor is initially held discharged by a
transistor inside the timer.
until the set time has elapsed, even if it is triggered again during
this interval. The duration of the output H'IGH state is given by
t = 1.1 Rlel and is easily determined by Figure 3. Notice that since
the charge rate and the threshold level of the comparator are both
directly proportional to supply Voltage, the timing interval is inde·
pendent of supply. Applying a negative pulse simultaneously to the
Reset terminal (lead 4) and the Trigger terminal (lead 2) during the
timing cycle discharges the external capacitor and causes the cycle
to start over. The timing cycle now starts on the positive edge of the
reset pulse. During the time the reset pulse is applied, the output
is driven to its LOW state.
When a negative trigger pulse is applied to lead 2, the flip-flop is
set, releasing the short circuit across the external capacitor and
drives the output HIGH.The voltage across the capacitor, increases
exponentially with the time constant T = R1Cl. When the voltage
across the capacitor equals 2/3 Vee, the comparator resets the
flip·flop which then discharges the capacitor rapidly and drives the
output to its LOW state. Figure 2 shows the actual waveforms
generated in this mode of operation.
The circuit triggers on a negative-going input signal when the level
reaches 1/3 Vee. Once triggered, the circuit remains in this state
'Vce - 5 TO 15V
When Reset is not used, it should be tied high to avoid any
possibility of false triggering.
I
0---------------,-------,
Fig. 1
t~O'l
TIME DELAY AS A FUNCTION
OF Rl ANoel
msiDIV
INPUT-2.0V/DIV
I
I
I
I rr--
I
II
I I
11
I
OUTPUT VOLTAGE - 5.0 VtDlV
I
V1
CAPACITOR VOLTAGE
I I
V1
I
/
I
2.0VfDIV
TIME DELAY
Rl"'9.1kfl,Cl-0.01#F,RL"'1.0kn
Fig. 2
Fig. 3
9-29
FAIRCHILD. tLA555
TYPICAL APPLICATIONS (Cant'd)
ASTABLE OPERATION
When the circuit is connected as shown in Figure 4 (leads 2 and 6
and the discharge time (output LOW) by:
connected) it triggers itself and free runs as a multivibrator. The
= 0.693
t2
external capacitor charges through R 1 and R2 and discharges
through R2 only. Thus the duty cycle may be precisely set by the
ratio of these two resistors.
T
In the astable mode of operation, C1 charges and discharges between
1/3 VCC and 2/3 VCC. As in the triggered mode, the charge and
= t1 + t2 = 0.693
discharge times and therefore frequency are independent of the
1
f =T
Figure 5 shows actual waveforms generated in this mode of
operation.
+ 2R2) C1
1.44
=
(R1 + 2R2) C1
and may be easily found by Figure 6.
The duty cycle is given by:
The charge time (output HIGH) is given by:
= 0.693
(R1
The frequency of oscillation is then:
supply voltage.
tj
(R2) C1
Thus the total period T is given by:
R2
D=·--R1 + 2R2
(R 1 + R2) C1
t-VCC·5TO 15 V
0---------,----,--<>
'i<>-----i
OUTPUT 0 - - - - - - - 0 J
~A555
~ Ir'
CONTROL
VOLTAGE
00l~F
1
Y
~
r
Fig. 4
FREE RUNNING FREQUENCY
AS A FUNCTION OF
Rl, R2 AND Cl
OUTluT VOL1AGE -
51
V!DIV
J
J
CAPACITOR VOLTAGE
1
J
1.0V/DIV
RlwR2~4.8kf!,Cl~O.1~F,RL
lkf!
Fig. 5
Fig, 6
9-30
IJA556
DUAL TIMING CIRCUIT
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The "A556 Timing Circuits are very stable controllers for producing
accurate time delays or oscillations. In the time delay mode, the delay time is precisely controlled by
one external resistor and one capacitor; in the oscillator mode, the frequency and dutY cycle are both
accurately controlled with two external resistors and one capacitor. By applying a trigger signal, the
timing cycle is started and an internal flip-flop is set, immunizing the circuit from any further trigger
signals. To interrupt the timing cycle a reset signal is applied, ending the time-out.
CONNECTION DIAGRAM
14-PINDIP
(TOP VIEW)
PACKAGE OUTLINES 6A 9A
PACKAGE CODES D P
The output, which is capable of sinking or sourcing 200 mA, is compatible with TTL circuits and can
drive relays or indicator lamps.
The "A556 Dual Timing Circuit is a pair of 555s for use in sequential timing or applications requiring
multiple timers.
DISCHARGE
THRESHOLD
•
•
•
•
•
•
•
MICROSECONDS THROUGH HOURS TIMING CONTROL
ASTABLE OR MONOSTABLE OPERATING MODES
ADJUSTABLE DUTY CYCLE
200 rnA SINK OR SOURCE OUTPUT CURRENT CAPABILITY
TTL OUTPUT DRIVE CAPABILITY
TEMPERATURE STABILITY OF 0.005% PER °c
NORMALLY ON OR NORMALLY OFF OUTPUT
CONTROL 3
VOLTAGE 4
RESET
OUTPUT
__.
OUTPUT
TRIGGEA
GND
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Power Dissipation
Operating Temperature Ranges
"A556 DC/PC
"A556DM
Storage Temperature Range
Pin Temperature (Soldering)
(10 s) Plastic DIP (9A)
(60s) Ceramic DIP (6A)
-....
TRIGGER
+18V
600mW
ORDER INFORMATION
PART NO.
TYPE
"A556DC
"A556
"A556
"A556DM
"A556PC
"A556
O°C to +70°C
_55°C to +125°C
_65°C to +150°C
260°C
300°C
BLOCK DIAGRAM
j------T------~vcc
DISCHARGE --(~----------....,
THRESHOLD --(~---I
--I
CONTROL VOLTAGE --(~.....
RESET --(~-+---,
OUTPUT --(~-+--...I
TRIGGER -~~---I
I
I
I
I
I
I
I
I
I
r------------<>-- DISCHARGE
1-__-<)__
,----1--0--
RESET
'-----l'--<)-- OUTPUT
1-__-<)_- TRIGGER
GND~ _ _ _ _ _ _ ~ _ _ _ _ _ _ _.J
9-31
THRESHOLD
1---1~-<)-- CONTROL VOLTAGE
I
FAIRCHILD • ILA556
ELECTRICAL CHARACTERISTICS: T A= 25°C, VCC= +5.0 V to +15 V, unless otherwise specified
I'A556DM
CHARACTER ISTICS
TEST CONDITIONS
MIN
Supply Voltage
TYP
4.5
VCC = 5.0 V, RL =
I'A556DC/PC
MAX
18
MIN
TYP
4.5
MAX
UNITS
16
V
6.0
10
6.0
12
mA
VCC = 15 V, RL = 00
LOW State (Note 1)
20
22
20
28
mA
Initial Accuracy
RA =2 kn to 100 kn
0.5
1.5
0.75
Drift with Temperature
C = O.lI'F (Note 2)
30
100
50
ppm/"C
0.05
0.2
0.1
%V
Supply Current (Total)
00
Timing Error (Monostable)
Drift with Supply Voltage
%
Timing Error (Astable)
Initial Accuracy
RA, RB = 2 kn to 100 kn
1.5
2.25
%
Drift with Temperature
C = O.lI'F (Note 2)
90
150
ppm/"C
Drift with Supply Voltage
Threshold Voltage
Threshold Current
Trigger Voltage
0.15
0.3
%V
2/3
2/3
X VCC
nA
30
100
30
VCC = 15 V
4.8
5.0
5.2
5.0
VCC = 5.0 V
1.45
1.67
1.9
1.67
V
0.5
j.l.A
Note 3
Trigger Current
0.5
Reset Voltage
0.4
Reset Current
0.7
1.0
0.4
0.1
0.7
100
V
1.0
V
mA
0.1.
VCC-15V
9.6
10
10.4
9.0
10
11
V
VCC = 5.0 V
2.9
3.33
3.8
2.6
3.33
4.0
V
ISINK = 10mA
0.1
0.15
0.1
0.25
V
ISINK = 50mA
0.4
0.5
0.4
0.75
V
ISINK = 100 mA
2.0
2.25
2.0
2.75
ISINK = 200 mA
2.5
Control Voltage Level
VCC=15V
Output Voltage (LOW)
V
V
2.5
VCC - 5.0V
0.1
ISINK - 8.0 mA
V
0.25
0.25
ISINK = 5.0 mA
0.35
V
ISOURCE = 200 mA
VCC-15V
Output Voltage (HIGH)
12.5
12.5
V
V
ISOURCE = 100 mA
VCC-15V
13.0
13.3
·12.75
13.3
VCC= 5.0V
3.0
3.3
2.75
3.3
V
100
ns
Rise Time of Output
100
Fall Time of Output
100
Discharge Leakage Current
100
20
100
Initial Timing Accuracy
0.05
0.1
Timing Drift with Temperature
±10
ns
20
100
0.1
0.2
nA
Matching Characteristics (Note 4)
Drift with Supply Voltage
0.1
±10
0.2
0.2
NOTES:
1. Supply current when output is H IG H is typicaUv 1.0 rnA less.
2. Tested at Vee = 5 V and Vee = 15 V.
3. This will determine the maximum value of RA + AS for 15 V operation. The maximum total R
=
20 Mil.
4. Matching characteristics refer to the difference between performance characteristics of each timer section.
9-32
%
ppm/"C
0.5
%V
FAIRCHILD • JLA556
TYPICAL PERFORMANCE CURVES
MINIMUM PULSE WIDTH
REQUIRED FOR TRIGGERING
0
,
V
0
5
°v
5~ p-
-
,l- f---
-L
--- -;::::.
~
,!-S'C
HIGH OUTPUT VOL TAGE
AS A FUNCTION OF
OUTPUT SOURCE CURRENT
TOTAL SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE
°v
k:
~r-
/'
;V
V
V
0
V
8
6
V
,
0
8
6
,
0
: -5_1~_lcJqr
O
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE
X Vee
LOW OUTPUT VOLTAGE
AS A FUNCTION OF
OUTPUT SINK CURRENT
LOW OUTPUT VOLTAGE
AS A FUNCTION OF
OUTPUT SINK CURRENT
0
VCC~
5
25"C
,
I
v
_'If,oC
0
Vee
~
LOW OUTPUT VOLTAGE
AS A FUNCTION OF
OUTPUT SINK CURRENT
10 V
VCC- 15V
-
(
1
J
/'
,
,
25°C
,
0.0
•
/
V
V
,
..0
DELAY TIME
AS A FUNCTION OF
SUPPLY VOLTAGE
5
5
0
0
\
\
5
---
-- --
I
0
5
--r5
- -- -
)
0
O=ff ~ ~\
~r;
-r,;:c
0-
0
5
PROPAGATION DELAY
AS A FUNCTION OF
VOLTAGE LEVEL OF
TRIGGER PULSE
DELAY TIME
AS A FUNCTION OF
AMBIENT TEMPERATURE
5
0
25
50
75
AMBIENT TEMPERATURE -'C
9-33
100
OA
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE - X Vee
FAIRCHILD e/LA556
EQUIVALENT CIRCUIT (One Half of ",A556)
FM
THRESHOLD
OUTPUT
TR!GGEROo''''------/---t::
RESETo-''''----i::DISCHARGE
00':;:"'--,
R5
10k
R6
R9
lOOk
5k
GNOo-'--~~-/~---~~-4-~---~---~-4---~
TYPICAL APPLICATIONS
MONOSTABLE OPERATION
until the set time has elapsed, even if it is triggered again during
this interval. The duration of the output HIGHstate is given by
t = 1.1 Rlel and is easily determined by Figure 3. Notice that since
the charge rate and the threshold level of the comparator are both
directly proportional to supply voltage, the timing interval is inde·
pendent of supply. Applying a negative pulse simultaneously to the
Reset terminal (lead 4) and the Trigger terminal (lead 6) during the
timing cycle discharges the external capacitor and causes the cycle
to start over. The timing cycle now starts on the positive edge of the
reset pulse. During the time the reset pulse is applied, the output
is driven to its LOW state.
In the monostable mode, the timer functions as a one-shot. Referring
to Figure 1 the external capacitor is initially held discharged by a
transistor inside the timer.
When a negative trigger pulse is applied to lead 6, the flip-flop is
set, releasing the short circuit across the external capacitor and
drives the output HIGH.The voltage across the capacitor, increases
exponentially with the time constant T = Rlel. When the voltage
across the capacitor equals 2/3 Vee, the comparator resets the
flip-flop which then discharges the capacitor rapidly and drives the
output to its LOW state. Figure 2 shows the actual waveforms
generated in this mode of operation.
The circuit triggers on a negative-going input signal when the level
reaches 1/3
Vee.
When Reset is not used, it should be tied high to avoid any
possibility of false triggering.
Once triggered, the circuit remains in this state
+VCC~5TO 15Vo--------~----_,
14
TRIGGER
OUTPUT
Fig. 1
t~O
TIME DELAY AS A FUNCTION
OF R1 AND Cl
1 ms/DIV
-
INPUT - 2.0 V/DIV
I
Ir
I
l
I
U
OUTPUT VOLTAGE - 5.0 V/DIV
l
!1
J I
CAPACITOR VOLTAGE
/
~
I I
I
/
/
~
/
2.0 V!DIV
Al
~9.1
kr:!. Cl
~
0.01 /.IF. AL
~
1.0kr:!
Fig. 2
Fig. 3
9-34
FAIRCHILD • JLA556
TYPICAL APPLICATIONS (Cant'd)
ASTABLE OPERATION
When the circuit is connected as shown in Figure 4 Ileads 2 and 6
and the discharge time loutput LOW) by:
connected) it triggers itself and~free runs as a multivibrator. The
t2
external capacitor charges through R 1 and R2 and discharges
through R2 only. Thus the duty cycle may be precisely set by the
ratio of these two resistors.
T
In the astable mode of operation, C1 charges and discharges between
1/3 VCC and 2/3 VCC. As in the triggered mode, the charge and
discharge times and therefore frequency are independent of the
supply voltage.
= q + t2 = 0.6931R1 + 2R2) C1
The frequency of oscillation is then:
1
f
Figure 5 shows actual waveforms generated in this mode of
operation.
1.44
=T = ;:1R:-:1:-+-=2R=-2:::)-=C=-=1
and may be easily found by Figure 6.
The duty cycle is given by:
R2
D=--R1 + 2R2
The charge time loutput HIGH) is given by:
t1
= 0.693 IR2) C1
Thus the total period T is given by:
= 0.693 (R 1 + R2) C1
+VCC~5TO
15
VO----------~----__t--O
1
R1
4
14
5
OUTPUT
1
1/2 556
R2
,r' r -cJ
r
2
CONTROL
7
v~~iASEI
11
Fig.4
FREE RUNNING FREQUENCY
AS A FUNCTION OF
R1, R2 AND C1
t~O.5msfDIV
OUTluT VOLlAGE - s1 V/DIV
I
I
I
I
0,001 L.._1-...-J1-...-J>--,-'''--:-:",~-::'
CAPACITOR VOLTAGE
Rl
= R2 = 4.8
1.0 VfDIV
k.l1, C1
0.' Hz
= 0.1
I'F, RL
=1
1 0 Hz
10 Hz
100 Hz
1.0 kHz
10 kHz
FREE RUNNING FREQUENCY
k.l1
Fig. 6
Fig. 5
9-35
100 kHz
IJA2240
PROGRAMMABLE TIMER/COUNTER
FAIRCHILD LINEAR INTEGRATED CIRCU ITS
GENERAL DESCRIPTION - The ,uA2240 Programmable Timer/Counter is a monolithic controller capable of producing accurate microsecond to five day time delays. Long delays, up to three
years, can easily be generated by cascading two timers. The timer consists of a
time~base
oscillator,
programmable 8-bit counter and control flip-flop. An external resistor capacitor (RC) network sets
the oscillator frequency and allows delay times from 1 RC to 255 RC to be selected. In the astable
mode of operation, 255 frequencies or pulse patterns can be generated from a single RC network.
These frequencies or pulse patterns can also easily be synchronized to an external signal. The trigger, reset and outputs are all TIL and DTL compatible for easy interface with digital system. The
timer's high accuracy and versatility in producing a wide range of time delays makes it ideal as a
CONNECTION DIAGRAM
16-PIN DIP (TOP VIEW)
PACKAGE OUTLINES 7B, 9B
PACKAGE CODE D P
T.
Vee
direct replacement for mechanical or electromechanical devices.
•
•
•
•
•
•
•
•
REGULATOR
OUTPUT
ACCURATE TIMING FROM MICROSECONDS TO DAYS
PROGRAMMABLE DELAYS FROM 1 RC TO 255 RC
TTL, DTL AND CMOS COMPATIBLE OUTPUTS
TIMING DIRECTlY PROPORTIONAL TO RC TIME CONSTANT
HIGH ACCURACY - 0,5%
EXTERNAL SYNC AND MODULATION CAPABILITY
WIDE SUPPLY VOLTAGE RANGE
EXCELLENT SUPPLY VOLTAGE REJECTION
TlME--8ASE
OUTPUT
RESISTOR
CAPACITOR
INPUT
MOOULATION
INPUT
TRIGGER
INPUT
RESET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Output Current
Output Voltage
ONO
18 V
10 mA
18 V
5 mA
Regulator Output Current
Maximum Power Dissipation, Note 1
Package Code D (Ceramic)
Code P (Plastic)
Operating Temperature Range Package
Military (,uA2240)
Commercial (,uA2240C)
750 mW
650 mW
-55°C to +125°C
ODC to 70°C
ORDER INFORMATION
TYPE
PART NO.
,uA2240
,uA2240DM
,uA2240C
,uA2240DC
,uA2240C
,uA2240PC
BLOCK DIAGRAM
-- .- - - - - T - - - I
r-------------I
T.
.T
5 kll
TB
I·
~~~~
-- -- ---~~~~~------ -- ---,--
°'28
--C~~~~;R
--" -+-----~I ;3~-~~g~
NOTE 1: Above 25°C ambient derate linearly at 6.2 mW;oC for Package Code D and at 5.3 mWjOC for Package Code P.
9-36
FAIRCHILD. jlA2240
ELECTRICAL CHARACTERISTICS: See Test Circuit Fig. 28. VCC ~ 5 V, TA ~ 25°C, R ~ 10 kn, C ~ 0.1 ).IF, unless otherwise noted
CONDITIONS
CHARACTERISTICS
UNITS
GENERAL CHARACTERISTICS
Supply Voltage
For VCC <:; 4.5 V, Short Pin 15
to Pin 16
15
4.0
4.0
15
V
Supply Current
Total Circuit
VCC - 5 V, VTR - 0, VRS - 5 V
VCC = 15 V, VTR = 0, V RS = 5 V
Counter Only
Regulator Output, V Reg
See Test Circuit, Figure 29
3.5
6.0
4.0
7.0
mA
12
16
13
18
mA
1
Measured at Pin 15, V CC = 5 V
4.1
4.4
VCC = 15 V, See Test Circuit,
Figure 30
6.0
6.3
1.5
6.6
mA
3.9
4.4
5.8
6.3
6.8
V
5.0
V
TIME BASE SECTION
Timing Accuracy (Note 2)
V RS = 0, VTR = 5 V
0.5
2.0
0.5
V
150
300
200
0.2
0.08
= 5V
I
00C <:; TJ <:; 75°C
Temperature Drift
CC
'
VCC = 15 V
Supply Drift
VCC ~ 8 V, See Figure 23
Max Frequency
R = 1 kO, C = 0.007 /1F
Modulation Voltage Level
Measured at Pin 12
VCC = 5 V
I
80
0.05
100
130
3.00
3.50
Recommended Range
of Timing Components
ppm/oC
80
0.3
130
4.0
2.80
10.5
VCC=15V
3.50
%
ppm;oC
%/V
kHz
4.20
10.5
V
V
See Figure 20
Timing Resistor, R
0.001
10
0.001
10
MO
Timing Capacitor, C
0.007
1000
0.01
1000
/1F
TRIGGER/RESET CONTROLS
Trigger
Measured at Pin 11, VRS = 0
Trigger Threshold
Trigger Current
1.4
1.4
2.0
8.0
VRS = 0, VTR = 2 V
2.0
V
10
/1A
Impedance
25
25
kO
Response Time (Note 3)
1.0
1.0
/1S
Reset
Measured at Pin 10, VTR =
a
Reset Threshold
Reset Current
1.4
Impedance
Response Time (Note 3)
COUNTER SECTION
See Test Circuit Figure 30
Max Toggle Rate
V RS = 0, VTR = 5 V
Measured at Pin 14
0.8
Input Impedance
Input Threshold
Output:
Rise Time
Fall Time
2.0
1.4
1.0
2.0
10
8.0
VTR = 0, VRS = 2 V
V
/1 A
25
25
kO
0.8
0.8
/1S
1.5
1.5
MHz
20
20
kO
1.4
V
180
180
ns
180
180
ns
4.0
mA
1.4
1.0
Measured at Pins 1 through 8
RL = 3 kO, CL = 10 pF
Sink Current
VOL <:; 0.4 V
Leakage Current
V OH =15V
3.0
5.0
0.01
2.0
8.0
NOTES;
2. Timing error solely introduced by pA2240, measured as % of ideal time base period of T = 1.00 Re.
3. Propagation delay from application of trigger (or reset) input to corresponding state change in counter output at Pin 1.
9-37
0.01
15
/1A
II
FAIRCHILD. pA2240
FUNCTIONAL DESCRIPTION
(Figure 1 and Block Diagram, page 1)
When power is applied to the J.lA2240 with no trigger or reset inputs, the circuit starts with all outputs HIGH. Application of a positive-going trigger pulse to TRIG, pin 11, initiates
the timing cycle. The Trigger input activates the time-base
oscillator, enables the counter section and sets the counter
outputs LOW. The time-base oscillator generates timing pulses with a period T = 1 RC. These clock pulses are counted by
the binary counter section. The timing sequence is completed
when a positive-going reset pulse is applied to R, pin 10.
outputs are connected back to the Reset terminal (switch 51
open), the circuit operates in an astable or free-running
mode, following to a trigger input.
Important Operating Information
•
Once triggered, the circuit is immune from additional trigger
inputs until the timing cycle is completed or a reset input is
applied. If both the reset and trigger are activated simultaneously, the trigger takes precedence.
Ground connection is pin 9.
•
Reset R (pin 10) sets all outputs HIGH.
•
Trigger TRIG (pin 11) sets all outputs LOW.
•
Time-base TBO (pin 14) can be disabled by bringing the
RC input (pin 13) LOW via a 1 k resistor.
•
Normal Time-base Output TBO (pin 14) is a negativegoing pulse greater than 500 ns.
Note: Under the conditions of high supply voltages (VCC
> 7 V) and low values of timing capacitor (C < 0.1 J.lF, the
Figure 2 gives the timing sequence of output waveforms at
various circuit terminals, subsequent to a trigger input. When
the circuit is in a Reset state, both thetime-baseandthecounter sections are disabled and all the counter outputs are HIGH.
pulse width of TBO may be too narrow to trigger the counter section. This can be corrected by connecting a 300 pF
capacitor from TBO (pin 14) to ground (pin 9).
In most timing applications, one or more of the counter outputs are connected to the Reset terminal with 51 closed (Figure 3). The circuit starts timing when a trigger is applied and
automatically resets itself to complete the timing cycle when
a programmed count is completed. If none of the counter
•
Reset (pin 10) stops the time-base oscillator.
•
Outputs 00' .. 0128 (pins 1-8) sink 2 mA current with
VOL ';;0.4 V.
•
For use with external clock, minimum clock pulse amplitude should be 3 V, with greater than 1 J.lS pulse duration.
13
11
12
TRIG
pA2240
VREG
15
10
Vee~Pin16
GND
14 1
2
Fig. 1.
3
4
5
6
7
~
Pin 9
8
Logic Diagram
r----------~-VCC
W1
_~
__________
~t
TRIGGER
RL
INPUT
(pIN 11)
10 k
TIME BASE
~y~~~~
I111111111111111111111111
COUNTER
OUTPUTS
~tPIN'
h.nnn.nn....c_
h
TRIGGER
..n..
I
13
11 TRIG
t PIN2
h~......LD~-,----,DL----,-_....D~--,_ t PIN 3
.01 pF
C
I
12
MOO
RC
tJA2240
15
..n..
GND
.7 k
<-_ _ - - - . - t
Pin 9
TRIGGER
-I1--
PIN 5
o--t-+-+-+-.............'-'......---"-jr--- OUTPUT
51
1T < TO < 255T
WHERE T "" Re
Timing Diagram of Output Waveforms
~
20 k
'_tPIN.
h_-'-_______
Fig. 2.
Vee ~ Pin 16
VREG
RESET
Fig. 3.
9-38
~
-l To I-
Basic Circuit Connection for Timing Applications
Monostable: 81 Closed
Astable: 81 Open
FAIRCHILD. pA2240
where
CIRCUIT CONTROLS
Counter Outputs (00 ... 0128' pins 1 thru 8)
The binary counter outputs are buffered open-collector type
stages, as shown in the block diagram on page 1. Each output is capable of sinking 2 mA at 0.4 V VOL' In the Reset
condition, all the counter outputs are HIGH or in the nonconducting state. Following a trigger input the outputs
change state in accordance with the timing diagram of Figure
2. The counter outputs can be used individually, or can be
connected together in a wired-OR configuration, as described
in the Programming section.
m is an integer, 1 ~ m ~ 10
Figure 5 gives the typical pull-in range for harmonic synchronization for various values of harmonic modulus, m. For
m < 10, typical pull-in range is greater than ±4% of timebase frequency.
RC Terminal (pin 13)
The time-base period T is determined by the external RC network connected to RC, pin 13. When the time base is triggered, the waveform at pin 13 is an exponential ramp with a period T = 1.0 RC.
Reset and Trigger Inputs (R and TRIG, pins 10 and 11)
The circuit is reset or triggered with positive-going control
pulses applied to pins 10 and 11 respectively. The threshold
level for these controls is approximately two diode drops
('" 1.4 V) above ground. Minimum pulse widths for reset and
trigger inputs are shown in Figure 22. Once triggered, the circuit is immune to additional trigger inputs until the end of the
timing cycle.
Time-8ase Output (T80, pin 14)
The time-base output is an open-collector type stage as shown
in the block diagram, page, 1, and requires a 20 kO pull-up
resistor to pin 15 for proper circuit operation. In the Reset
state, the time-base output is HIGH. After triggering, it produces a negative-going pulse train with a period T = RC, as
shown in the diagram of Figure 2. The time-base output is
internally connected to the binary-counter section and can
also serve as the input for the external clock signal when the
circuit is operated with an external time base. The counter
section triggers on the negative-going edge of the timing or
clock pulses generated at TBO, pin 14. The trigger threshold
for the counter section is'" +1.4 V. The counter section can
be disabled by clamping the voltage level at pin 14 to ground.
Modulation' and Sync Input (MOD, pin 12)
The oscillator time-base period, T, can be modulated by applying a dc voltage to MOD, pin 12 (see Figure 25). The timebase oscillator can be synchronized to an external clock by
applying a sync pulse to MOD, pin 12, as shown in Figure 4.
Recommended sync pulse widths and amplitudes are also
given.
The time base can be synchronized by setting the time-base
period T to be an integer mUltiple of the sync pulse period,
Ts' This can be done by choosing the timing components R
and C at pin 13 such that:
When using high supply voltages (VCC > 7 V) and a smallvalue timing capacitor (C < 0.1 pF), the pulse width of the
time-base output at pin 14 may be too narrow to trigger the
counter section. This can be corrected by connecting a 300 pF
capacitor from pin 14 to ground.
T = RC = (Ts/m)
±20
~
IE
w
±16
~
Tp
-I f-
n
~
0.3T
i=
< Tp < 0.8T
±12
~
0
"'"
n-=}vpp
0...1 L-J L-L
ui
I--Ts-j
±8
z
:z
j
~
±4
I
\
~
........
........... ....
t10
12
RATIO OF TIME-BASE PERIOD TO
SYNC-PULSE PERIOD - (TITs)
Fig. 4.
Fig. 5. Typical Pull-in Range for Harmonic Synchronization
Operation with External Sync. Signal
9-39
II
FAIRCHILD • pA2240
Vee
Vee
Vee
Rl
10 k
47 k
e
Vee =Pin16
....n....
GND = Pin 9
RESET
--~----r------------------+--~-V~-+~~~4-4-+-+-----~--OUTPUT
....n....
Fig. 6.
Cascaded Operation for Long Delays
Vee
Vee
Vee
47 k
RL
30 k
NO Vee CONNECTION REQUIRED
ON IlA2240 #2
C
+-_______-++-,
TRIGGER'----.____
Vee = Pin
TRIG
16
GND = Pin 9
pA2240 #1
RESET
....n....
L.--------------+--'lNY------21T---.~1
PINS 1, 3. AND 5 SHORTED
C. 4 PIN PATTERN
~~
3T~5T"I""I"
Fig. 10.
"1~~1"5T"I~;I"
21T
85T-
Binary Pulse Patterns Obtained by Shorting Various Counter Outputs
9-41
FAIRCHILD • pA2240
Vee
Vee
RC
MOD
Vee
= Pin
GND
= Pin
1f
~
-l~I-
RC WAVEFORM
TIME BASE OUTPUT
rYYYYYYl/ /fYYYYYYYI
IIIIII
Ij /
O,OUTPUTnIU-U/ /
IIIIIIII
LIlJlJlS
J"lSLj
j-----I1JL
I..
I
256 RC
"
j '"fl'"tj /-ILJ.---
256 RC
"
I
~/j-FL
1.---256RC
Fig. 11.
Continuous Free-run Operation Examples of Output
9-42
..
I
FAIRCHILD • /lA2240
of the complex pulse patterns that can be generated. The
pulse pattern repeats itself at a rate equal to the period of the
highest counter bit connected to the common output bus. The
minimum pulse width contained in the pulse train is determined by the lowest counter bit connected to the output.
For low power operation with supply voltages of 6 V or less,
the internal time base section can be powered down by connecting Vee to pin 15 and leaving pin 16 open. In this configuration, the internal time base does not draw any current
and the overall current drain is reduced by "'" 3 mAo
OPERATION WITH EXTERNAL CLOCK
The pA2240 can be operated with an external clock or time
base by disabling the internal time-base oscillator and applying the external clock input to TBO, pin 14. The recommended
circuit connection for this application is shown in Figure 12.
The internal time base is de-activated by connecting a 1 kO
resistor from Re, pin 13, to ground. The counters are triggered on the negative-going edges of the external clock pulse.
For proper operation, a minimum clock pulse amplitude of
3 V is required. Minimum external clock pulse width must be
;;, 1 ps.
FREQUENCY SYNTHESIZER
The programmable counter section of the pA2240 can be
used to generate 255 discrete frequencies from a given timebase output setting using the circuit connection of Figure 13.
The circuit output is a positive pulse train with a pulse width
equal to T, and a period equal to (N + 1) T where N is the programmed count in the counter. The modulus N is the total
count corresponding to the counter outputs connected to the
output bus. For example, if pins 1, 3 and 4 are connected together to the output bus, the total count is N = 1 + 4 + 8 = 13;
and the period of the output waveform is equal to (N + 1) T
or 14 T. In this manner, 255 different frequencies can be synthesized from a given time-base setting.
Vee
Vee
Vee
Vee
= Pin
RL
4.7 k
16
GND = Pin 9
3.
Re
TRIGGER
TRIG
JL
VREG
J.lA2240
1•
RESET
J"L
500 pF
EXTERNAL
CLOCK
INPUT
n..rLJ'L
MOD
,----jTRIG
tJA2240
VREG
I
o
N
Vee
= Pin
........W..-+-+-+-+--+--+--+--+---...-OUTPUT
OUTPUT
51 OPEN: ASTABLE OPERATION
10 •
51 CLOSED: MONOSTABlE
T'" RC
1.:; N";; 255
Fig. 12.
Operation with External Clock
Fig. 13.
Frequency Synthesis from Internal Time-Base
REFERENCE
Vee
I
"1
Vee
3.
C ",;;o.1 Ji F
5.1 k
Re
TRIG
,.
I'A2240
VREG
20.
J500 pF
Vee = Pin 16
GND
= Pin
9
OUTPUT
Fig. 14.
16
GND = Pin 9
Frequency Synthesis by Harmonic Locking to an External Reference
9-43
...fl....IL
.~
T(N+1)
II
FAIRCHILD. I1A2240
SYNTHESIS WITH HARMONIC LOCKING
The harmonic synchronization feature of the IlA2240 time
base can be used to generate a wide number of discrete frequencies from a given input reference frequency. The circuit
connection for this application is shown in Figure 14 (see
Figures 4 and 5 for external sync waveform and harmonic
capture range). If the time base is synchronized to (m)th
harmonic of input frequency where 1 .;:; m .;:; 10, the frequency fO of the output waveform in Figure 14 is related to the input reference frequency fR as
The circuit of Figure 14 can be used to generate frequencies
which are not harmonically related to a reference input. For
example, by selecting the external RC to set m = 10 and setting N = 5, a 100Hz output frequency synchronized to 60 Hz
power line frequency can be obtained.
STAIRCASE GENERATOR
The IlA2240 timer/counter can be interconnected with an
external operational amplifier and a precision resistor ladder
to form a staircase generator as shown in Figure 15. Under
Reset condition, the output is LOW. When a trigger is applied,
the op amp output goes HIGH and generates a negative-going
staircase of 256 equal steps. The time duration of each step
is equal to the time-base period T. The staircase can be
stopped at any level by applying a disable signal to pin 14,
through a steering diode, as shown in Figure 15. The count
is stopped when pin 14 is clamped at a voltage level';;;; 1.0 V.
m
(N
+ 1)
where m is the harmonic number, and N is the programmed
counter modulus. For a range of 1 .;:; N .;:; 255, the circuit of
Figure 14 can produce 2550 different frequencies from a
single fixed reference.
Vcc
R
c
AC
TRIGGER
MOD
TRIG
SL
,uA2240
RESET
00
SL
04
02
08
VREG
016
064
032
0128
Vee = Pin 16
20 k
GND = Pin 9
a:
N
_Fig. 15.
a:
Staircase Generator
Vee
e
I
Re
2.
STROBE
MOD
flA2240
VREG
RTBO 0 0 02 0 4 Os O'fb320640128
INPUT
20 k
Vee = Pin 16
~N
ANALOG INPUT
GND=~n9
--+---------1
BISTABLE LATCH
Fig. 16.
Digital Sample and Hold Circuit
9-44
FAIRCHILD. JlA2240
DIGITAL SAMPLE AND HOLD
Figure 16 shows a digital sample and hold circuit using the
.uA2240. Circuit operation is similar to the staircase generator described in the previous section. When a strobe input is
applied, the RC low-pass network between the Reset and the
Trigger inputs resets the timer, then triggers it. This strobe
input also sets the output of the bistable latch to a HIGH state
and activates the counter.
ANALOG-TO-DIGITAL CONVERTER
Figure 17 shows a Simple 8-bit AID converter system using
the .uA2240. Circuit operation is very similar to that of the
digital sample and hold system of Figure 16. In the case of
AID conversion, the digital output is obtained in parallel
format from the binary-counter outputs with the output at
pin 8 corresponding to the most significant bit (MSB). Recycle time is = 6 ms.
The circuit generates a staircase voltage at the op amp output. When the level of the staircase reaches that of the analog input to be sampled, the comparator changes state, activates the bistable latch and stops the count. At this point, the
voltage level at the op amp output corresponds to the sampled analog input. Once the input is sampled, it is held until
the next strobe signal. Minimum recycle time of the system
is = 6 ms.
DIGITAL TACHOMETER TIME BASE
A digital tachometer requires a time-base generator to supply
two pulse outputs at specific intervals, e.g., every second. The
first pulse is a command (load) to transfer the accumulated
counts in the counter section into latches (memory); the second resets the counter to zero. A simple adjustable time base,
accurate to approximately ±O.5%, can be implemented using
the circuit in Figure 18.
VCC
~
1
.J1...
STROBE
C = .01 pF
rifI
MOD
RC
TRIG
jJA2240 #1
00
R
TSO
INPUT
VREG
-
02 04 Os 01t320640128
20 k
YYY
128R
64 R
I
1
32R
16R
8R
:'-SCALE
ADJUST
DIGITAL OUTPUTS
•
4R
2R
""'>~~
OP AMP
ANALOG
INPUT
~
+
R
r--
f-s
BISTABLE
LATCH
'-R
p-
vee ~
Pin 16
GND
Pin 9
~
i---.
Fig. 17.
+5V
+5V
Analog-to-Digital Converter
+5 V
TIMING DIAGRAM
10k
(.)
10 k
(b)
vee
GND
0
0
...-___
Pin 16
Pin 9
(e)
~~:~~:ER
RESET
7410
Fig. 18.
Simple Time Generator for a Digital Tachometer
9-45
FAIRCHILD • pA2240
TYPICAL ELECTRICAL CHARACTERISTICS
SUPPLY CURRENT AS A
FUNCTION OF
SUPPLY VOLTAGE
IN RESET CONDITION
TIME BASE PERIOD AS A
FUNCTION OF EXTERNAL RC
RECOMMENDED RANGE OF
TIMING COMPONENT VALUES
10M~_
./
V~I
/
/
/
I
I
o
o
TIMING CAPACITOR -
~F
TIME BASE PERIOD
Fig. 19
Fig. 20
Fig. 21
MINIMUM TRIGGER PULSE
WIDTH AS A FUNCTION OF
TRIGGER AND
RESET AMPLITUDE
TIME BASE PERIOD DRIFT
AS A FUNCTION OF
SUPPLY VOLTAGE
MINIMUM
TRIGGERjRETRIGGER
TIMING AS A FUNCTION OF
TIMING CAPACITOR
3.0
0
+7S'C
+25~C
"* +2.0
,
'a 2.5
,
I
:;
~
O'C
~
~+1. 0 \
;;;
~ 2.0
\
o
o
~
r--...
+7S'C
r-....
+25'C-
~
0
i"-....
~
~
-1. 0
O'C
1.0
1.0
R: ~~kn
- r---
0
1.5
2.0
2.5
10
TRIGGER OR RESET AMPLITUDE - V
SUPPLYVOLTAGE-V
TIMING
- "F
Fig. 23
Fig. 24
NORMALIZED CHANGE IN
TIME BASE PERIOD
AS A FUNCTION OF
MODULATION VOLTAGE
TIME BASE PERIOD AS
A FUNCTION
OF TEMPERATURE
TIME BASE PERIOD AS
A FUNCTION
OF TEMPERATURE
5
+2.0
'2. 0
vee -
5V
VCC~15V
C ~ O.lI'F
C - 0.1 "F
0
0
Vee" 5 v
5
+-/
I
0
'--V
0
CAPACITO~
Fig. 22
/
V
X
I
+1.0
o~
~
0
I---
~
kn
"0
R~10MI~
0
-3 0
R~l
"'25
100
MODULATION VOL:TAGE - V
TEMPERATURE -
Fig. 25
Fig. 26
9-46
'c
-1.0
- ~~
R"lOMr;",
~
-2. 0
-3. 0
100
TEMPERATURE -'C
Fig. 27
FAIRCHILD. j1A2240
TEST CIRCUITS
Vcc
Vee = Pin 16
Gnd = Pin 9
VTR
±-
MOD
RC
Trig
tJA2240
vAS
±-
Vreg _
RIBO 0 0 02 0 4 Os 01~320640128
Fig. 28.
Generalized Test Circuit
Vee = Pin 16
Gnd = Pin 9
I
MOD
RC
VTR ~- Trig
Vreg ~ vee = 4 V
JJA2240
i'
10kil
Fig. 29.
-
,_~._~-:
-
10kil
Test Circuit for Low Power Operation
(Time Base Powered Down)
Vcc = Pin 16
Gnd = Pin 9
I
MOD
AC
VTR! -
Trig
pA2240
VAS
INPUT
SIGNAL
....n..n.rL
~
-
Vreg -
!
VR
ArBo 0 0 02 0 4 Oa O't320640128
9
+
3
\J ------1
Vcc
Fig. 30. Test Circuit for Counter Section
9-47
•
~A7391
DC MOTOR SPEED CONTROL CIRCUIT
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION - The /lA 7391 is designed for precision, closed-loop, motor
speed control systems. It regulates the speed of capstan drive motors in automotive and
portable tape players and is useful in a variety of industrial control applications, e.g.,
floppy disc drive systems, data cartridge drive systems. The device is constructed .using
the Fairchild Planar' epitaxial process.
CONNECTION DIAGRAM
12-PIN POWER PACKAGE
(TOP VIEW)
PACKAGE OUTLINE 9W
PACKAGE CODE P6
The IlA7391 compares actual motor speed to an externally presettable reference voltage. The motor speed is determined by frequency to voltage conversion of the input signal provided by tachometer generator. The result of the comparison controls the duty
cycle of the pulse width modulated switching motor drive output stage to close the system's negative feedback loop.
MOTOR
DRIVER
I-I
12
STAll TIMER
INPUTS
1"1
11
DRIVER
MOTOR DRIVE
TACH INPUT (-)
Thermal and over-voltage shutdown are included for self-protection, and a "stall-timer"
feature allows the motor to be protected from burn-out during extended mechanical
jams.
OUTPUT
GND
TAB
MOTOR DRIVE
OUTPUT
TACH INPUT (+)
v-
PULSE TIMING
•
•
•
•
•
•
•
PRECISION PERFORMANCE - FREQUENCY-TO-VOLTAGE CONVERSION STABILITY
TYPICALLY 0.1% FOR V+ FROM 10 V TO 16 V; 0.3% FOR CASE TEMPERATURE
FROM -40°C TO +B5°C
HIGH CURRENT PERFORMANCE - 3.5 A STARTING SURGE CURRENT AND 2 A
RUNNING CURRENT TO A DC MOTOR
WIDE RANGE TACHOMETER INPUT - 100 mVp-p TO 1.0 Vp-p
LOW EXTERNAL PARTS COUNT
THERMAL SHUTDOWN, OVER-VOLTAGE AND STALL PROTECTION
INTERNAL REGULATOR
WIDE SUPPLY VOLTAGE RANGE - 6.3 V TO 16 V
REGULATOR
PULSE OUTPUT
OUTPUT
ORDER INFORMATION
TYPE
PART NO.
pA7391
pA7391PC
BLOCK DIAGRAM
PULse TIMING
~ r--
,---
(+1
()~
I
4
II
I
1
I
I
I
PULSE
GENERATOR
OUTPUT
7
DRIVER
v-
1
I
VOLTAGE
REGULATOR
VOLTAGE REGULATOR
SECTION
...1.'t--
SUPPLY
VOLTAGE
v
v8
MOTOR
"-
I
I
I~
I
FREQUENCY TO
I
VOLTA~~CCT~~~EATER
I
MO;EOC~,~~VE
--------------1---------
I
I
:
2
I
03
b"
1
':'"
I
!REGULATOR
I
I
I
-:!:-
INPUTS
(-I
ill
3
I
PULSE
OUTPUT
6
TACHOMETER
INPUTS
,--;---,---r--<
_~ SPEED
"~",~;;C,~O;;;;,:"""~'_~
f_ ADJUST
I
I
II
THERMAL
SENSOR
I-
I
1
I
I
i
v-
I
OVER VOLTAGEJSENSOR
I
STALL TIMING
~~~E~~~~
I
-:l:.TAB
---------
~GND
I
I
I
I
I
I
II
PROTECTIVE
CIRCUITS
I
I
I
I
I
12
I
STA" TIMER
I
~'
I
I
I-
9
-'L
I
I
L_______________________ ~ _________________ J
*Planar is a patented Fairchild process.
9-48
FAIRCHILD • j.LA7391
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+), Vs
24 V
Regulator Output Current, 17
Voltage Applied to Pin 5 (Tachometer Pulse Timing)
15 mA
7V
Voltage Applied Between Pins 3 and 4 (Tachometer Inputs)
DC Voltage Applied to Pin 11 (Driver)
±6V
24 V
DC Voltage Applied to Pins 9 or 10 (Motor Drive Output)
Continuous Current through pins 9 and 10:
Motor Drive Output ON
Repetitive Surge Current through Pins 9 and 10:
Motor Drive Output ON
Motor Drive Output OFF
Repetitive Surge Current through Pin 11
V+
2.0A
3.5 A
2.0A
300 mA
Power Dissipation
Internally Limited
Storage Temperature Range
Operating Temperature Range
-55°C to +150 o C
-40°C to +S5°C
Lead Temperature (Soldering, 10 s)
260°C
THERMAL DATA
8JC
Thermal Resistance Junction to Case (tab) (max)
8JA
Thermal Resistance Junction to Ambient (max)
**Obtained with tabs soldered to a printed circuit board having a minimum area of copper surrounding the tabs.
ELECTRICAL CHARACTERISTICS: V+
= 14.5 V, TA = 25°C,
unless otherwise noted
VOLTAGE REGULATOR SECTION: (TEST CIRCUIT 1)
CHARACTERISTICS
CONDITIONS
Power Supply Current
Excluding Current into
Pins 9,10 and 11
MIN
Regulator Output Voltage
4.5
v
Regulator Output Line Regulation (.!::.V7)
V+ from 10 to 1 6 V
V+ from 6.3 V to 16 V
Regulator Output Load Regulation (.!::.V7)
17 from 10 mA to
ELECTRICAL CHARACTERISTICS: V+
= 14.5 V, TA = 25°C,
a
TYP
MAX
7.5
10
5.0
5.5
V
6.0
12
20
50
mV
mV
40
UNITS
mA
mV
unless otherwise noted
FREQUENCY TO VOLTAGE CONVERTER SECTION: (TEST CIRCUIT 2)
CHARACTERISTICS
CONDITIONS
MIN
Tachometer (-) Input Bias Voltage
MAX
2.4
Tachometer (+) Input Bias Current
V4=V3
Tachometer Input Positive Threshold
(V4 - V3)
Tachometer Input Hysteresis
Pulse Timing ON Resistance
TYP
1.0
V
10
J1A
10
25
50
mVpk
20
50
100
mVp _p
300
500
50
55
V5 = 1 V
Pulse Timing Switch Threshold
UNITS
45
Output Pulse Rise Time
0.3
Output Pulse Fall Time
0.1
Pulse Output LOW Saturation (V6)
0.13
Pulse Output HIGH Saturation (V7 - V6)
J1S
J1S
0.25
V
0.12
0.2
V
-260
-180
J1A
Pulse Output HIGH Source Current
V6= 1 V
Frequency-to-Voltage Conversion Supply Voltage
Stabi Iity (Note 1)
VFV = 0.25 V7 (Note 2)
V+ from 10 V to 1 6 V
0.1
%
Frequency-to-Voltage Conversion Temperature
Stability (Note 3)
VFV = 0.25 V7 (Note 2)
TA from -40°C to +85°C
0.3
%
9-49
-340
n
%V7
I
FAIRCHILD. /-LA7391
ELECTRICAL CHARACTERISTICS: V+ = 14.5 V, TA = 25°C, unless otherwise noted
MOTOR DRIVE SECTION: (TEST CIRCUIT 3)
CONDITIONS
CHARACTERISTICS
MIN
TYP
Input Offset Voltage
0.1
Input Bias Current
Common Mode Range
0.8
Driver Saturation
IS+IlO=2A,Ill = 175 rnA
Driver Leakage Current
Vll = 16V
Motor Drive Output Saturation
IS + II 0 = 2 A. III = 55 rnA
Motor Drive Output Leakage
V8 = Vs = VlO = 16 V
Flyback Diode Leakage
VS=VlO= 1 V
Flyback Diode Clamp
IS + 110 = 2 A
Motor Drive Output Off
1.S
0.6
MAX
UNITS
±20
mV
10
/lA
2.5
V
2.5
V
5.0
/lA
1.1
V
100
/lA
30
/lA
1.6
2.5
V
TYP
MAX
ELECTRICAL CHARACTERISTICS: V+ = 14.5 V, TA = 25°C, unless otherwise noted
PROTECTIVE CIRCUITS: (TEST CIRCUIT 4)
MIN
UNITS
CHARACTERISTICS
CONDITIONS
Thermal Shutdown Junction Temperature
Note 4
Overvoltage Shutdown
Note 4
18
21
24
Stall Timer Threshold Voltage
Note 5
2.5
2.S
3.5
V
Stall Timer Threshold Current
Note 5
0.3
3.0
/lA
DC
160
V
NOTES:
1. Frequency-ta-Voltage Conversion, Supply Voltage Stability is defined as:
[
VFV( 16
V7(16
V~
viJ
_ [VFV( 10 V)]
V7(10 V)
.,. rVFV( 14.5
V 7(14.5
L
V~ x
vd
100%
2. VFV is the integrated de output voltage from the pulse generator (Pin 6)
3. Frequency-ta-Voltage Conversion Temperature Stability is defined as:
4.
5.
"Driver" and "Motor Drive" circuitry is disabled when these limits are exceeded. If the condition continues for the duration set by the external stall timer
components, the circuit is latched off until reset by temporarily opening the power supply input line.
If stall timer protection is not required, Pin 12 should be grounded.
9-50
REGULATOR OUTPUT
PULSE OUTPUT
STALL TIMER
6
12
R11
9k
Q1'
"T1
R30
1 k
~
:D
o
'f'
:I:
Tr~~~~~C------------+----+-+-----j------,
I"'"
C
~
•
1:
»
......
Co)
U)
.....
DRIVER
11
10} MOTOR
(+)~
DRIVE
OUTPUTS
•
R2.
2.6 k
TACHOMETER
INPUTS
9
GNO
1~ .)
(,I
(-) <>------'VV'1r.- - - - - - - - - - - - - - - - '
3
MOTOR DRIVER INPUTS
EQUIVALENT CIRCUIT
II
FAIRCHILD • MA7391
TYPICAL APPLICATION USING MAGNETIC TACHOMETER
330 kO
ctL
RS
9.1 kO
SPEED
ADJUST
100 kn
10 kO
.01~F
±
1
12
2
11
750
2 kO
~
~
TAB TAB
-5
r---- 4
RF
100 kO
i
10
3
~
9
.01"F
~
I
I
I
I
I
8
6
r
-
7
I----
~h
CF
J5
I
I
Rp
'::"
100 kO
I
I
~
b
•
TACHOMET ER
If ~ NOMIN At TACHOMETER
FREQUE NCVI
TYPICAL COMPONENT VALUES:
Cp =
1
4 Rpf
CF = 10 Cp to 1000 Cp depending on system requirements
2 x stall time-out
CS = - - ' - - - - RS
RMotor~ 5
n
MOTOR SPEED ACCURACY AS A
FUNCTION OF SUPPLY VOLTAGE
(REFER TO APPLICATION
SCHEMATIC)
+2
I I LI I I I I
Vfl I I I I I I
o
"*I
>
(J
..
a:
-2
/
@V+ = 14.5 V, TA = 25°C
(J
(J
«
MOTOR:
TELEX TYPE 9100 DC MOTOR
MOTOR SPEED = 1500 RPM
TACHOMETER FREQUENCY'" 200 Hz
-6
::J
MOTOR LOAD:
TORQUE = 0.1 oz-in (72 gram-em)
-10
C
COMPONENT VALUES (TYPICAL
APPLICATION CIRCUIT):
ttl
"CI) -14
a:
CF'" 1 pF
RF=1QOkn
Cp = .015 pF
Rp=1QOkn
RS 330 kO
Cs
1}.iF
~
C
=
=
::; -18
-22
o
I I I I I I I I
12
4
16
SUPPLY VOLTAGE - V
9-52
10VTO l6V
20
24
FAIRCHILD. MA7391
REGULATOR OUTPUT VOLTAGE
AS A FUCTION OF
SUPPLY VOLTAGE
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
12
>
10
~
v,.....
"E
,
"':;
C
I-
w
I-
:::>
I-
'/
()
~
:::>
0
I
II
a:
4
0
I
:::>
UI
I-
TJ = 25°C
:3:::>
TJ
'a:w"
I
oL
o
12
4
16
SUPPLY VOLTAGE
20
~
24
'':;""
0
>
.
:::>
4
12
16
20
24
SUPPLY VOLTAGE - V
TACHOMETER INPUT HYSTERESIS
AS A FUNCTION OF
JUNCTION TEMPERATURE
58
E
,
,/'
5.2
./
5.1
5.0
V
:::>
0
a: 4.9
0
I-
:3:::>
o
>
5.3
II-
25°C
I
V
5.4
w
=
I
o
REGULATOR OUTPUT VOLTAGE
AS A FUNCTION OF
JUNCTION TEMPERATURE
>,
II
.
/
a:
a:
:::>
..
I
4
>
Z
/
4.8
iii
V
w
54
IUI
52
I-
~
50
ffi
48
ffi
>
:J:
/
~
/
56
UI
V+;;=; 14.5 V
..,...-
..,...- V
~
~
V
V+=14.5V
I-
c
/"
y V
46
:J:
a: 4.7
()
"
44
I-
4.6
~~
0
~
w
n
100
42
~~
1~1W
0
~
w
DRIVER ON CURRENT
AS A FUNCTION OF
DRIVER ON VOLTAGE
DRIVER ON VOLTAGE
AS A FUNCTION OF
JUNCTION TEMPERATURE
1W
2.3
2.2
"
E 300
>
/
1
,
I-
Z
w
a:
a:
~ 200
"'"
V+~14.~V
Ig+I10~2A
2.1
w
2.0
0
>
z
111
.....
':;
z
...........
1.9
r-.....
0
o
100
I
o
1OO1~
JUNCTION TEMPERATURE - °C
400
a:
w
>
~
c
n
JUNCTION TEMPERATURE - °C
/
/
-........
a: 1.8
v+ =
14.5 V
TJ
25°C
=
..........
w
~~I1~ ~ 10f11
o
>
a:
c
-
I---
175 rnA
=
.........
1.7
t'-...
1.6
1.5
-50
4
DRIVER ON VOLTAGE - V
-25
0
25
50
75
100
125 150
JUNCTION TEMPERATURE - °C
9-53
•
FAIRCHILD •
~A7391
MOTOR DRIVE OUTPUT ON
CURRENT AS A FUNCTION
OF MOTOR DRIVE OUTPUT
ON VOLTAGE
4
I
111 - 200 rnA
Z
/
3
~
:0
(J
Z
...0
...
:0
Il.
2
w
1
a:
0
:0
"
0/
0
0.2
0.4
/
0
>
-r
10mA
./
... V
:0
~
V
/
20.62
...0
...~O.60
~ ~V
>
...0
~ 0.66
'~O.64
"
2~ rnA
J V'
:0
>
V': AomA
V
~V V
0
a:0
0.68
10~mA
"...
w
a:
a:
MOTOR DRIVE OUTPUT ON
VOLTAGE AS A FUNCTION
OF JUNCTION TEMPERATURE
0.58
>
./
a:
00.56
V+""14.5V
TJ = 25°e
a:
V+=14.5V
15 0 .54
Ig+Il0~2A
0
:0
0.6
0.8
1.0
1.2
1.4
111 i'751mA
0.52
--50 -25
1.6
0
25
50
75
100
125 150
MOTOR DRIVE OUTPUT ON VOLTAGE - V
JUNCTION TEMPERATURE - °C
FLYBACK DIODE (03)
CURRENT AS A FUNCTION OF
FLYBACK DIODE VOLTAGE
OVERVOlTAGE SHUTDOWN VOLTAGE
AS A FUNCTION OF
JUNCTION TEMPERATURE
2
25
>
II
"...
z
I
>
/
I
:0
(J
0
0
23
0
w
a:
a:
w
24
w
"'"!:;
1
Z
0
0
...
"en
II
Ci
"
"!:;'"
i~= ~:~~ V_
1-
1
>
a:
1
w
18
>
0
1
17
- 50 -25
2
"!:;
3.2
0
>
0
6J:
3.0
2.8
~
a:
J:
>- 2.6
~
"
150
0.8
'" '"
"'"
...
v+1~ 14.~ V
0.7
~
a: 0.6
a:
:0
U
"'I'-..
<3
J:
"~
~
~
>- 2.2
1\
0.5
0
2.4
2.0
-50
125
STALL TIMER THRESHOLD
CURRENT AS A FUNCTION
OF JUNCTION TEMPERATURE
~
'"
100
STALL TIMER THRESHOLD
VOLTAGE AS A FUNCTION
OF JUNCTION TEMPERATURE
a:
i=
75
50
JUNCTION TEMPERATURE - 0C
3.4
w
to
25
0
FLYBACK DIODE VOLTAGE - V
3.6
>
--
19
0
V
0
20
w
1/
0
21
J:
I
U
""'~
22
'!:
0.4
a:
J:
>- 0.3
ffi
:0 0.2
i=
~
~
"
0.1
>en
-25
0
25
50
75
100
125
150
0
-50
v+I.- 14.k V
\
'" ~
-25
0
"- "-.
25
50
r-
75
100
125
JUNCTION TEMPERATURE - °C
JUNCTION TEMPERATURE - °C
9-54
150
FAIRCHILD. ILA7391
TEST CIRCUIT 1
12
11
3
10
TAB TAB
4
REGULATOR VOLTAGE
-=
TEST CIRCUIT 2
20kO
•
TACH INPUT
VOLTAGES
(-I
(+)
1000
12
10kO
2
11
3
10
0.1 #F
1000
TAB TAB
TACH
INPUT
VOLTAGE
ADJUST
V~ 0.3 Vp_p
AC
fNOM ~ 1000 Hz
OC
-=
4
TACH
INPUT
5
8
6
7
100ka
+
VFV
(INTEGRATED
FREQ·TO·VOLTAGE
CONVERTER
OUTPUT VOLTAGE)
PULSE
OUTPUT
VOLTAGE
J1#F
100kO
-=- 14.5 V
J-
PULSE
TIMING
VOLTAGE
J
9-55
.OO25#F
FAIRCHILD. MA7391
TEST CIRCUIT 3
20kO
MOTOR ORIVER
INPUT VOLTAGES
1-)
1+)
1000
+
10V
ORIVER
VOLTAGE
+
-=1000
+
MOTOR ORIVE
OUTPUT VOLTAGE
3A FLYBACK
~IOOETEST
~
-=-
12
I
760
-
15 V
+
11
10kO
FLYBACK
INPUT
VOLTAGE
ADJUST
3
10
70
30W
100kO
TAB
3A MOTOR
DRIVE
OUTPUT
TEST
TAB
-=-
-=4
FLYBACK
DIODE
LEAKAGE
+
6
-=-
7
COMMON
MODE
VOLTAGE
ADJUST
10kO
-=-
I
I
TEST CIRCUIT 4
STAll TIMER VOLTAGE
12
11
3
10
-=-
TAB TAB
1 kO
"::"
4
9
V+
+
7
"::"
9-56
r"
+
+
1V
5pF
FAIRCHILD • J.!A7391
MOUNTING INSTRUCTIONS
The thermal power dissipated in the circuit may be removed by soldering the tabs to an area of copper on the printed cir-
cuit board. During soldering the tabs temperature must not exceed 260°C and the soldering temperature time must not be
longer than 10 seconds.
MAXIMUM POWER DISSIPATION
AS A FUNCTION OF
AMBIENT TEMPERATURE
6.0
WITH INFINITE
5.0
r---- f----.WITH
3!:
I
Z
a
4.0
"iii
-t- -+
3.0
0
a: 2.0
w
\:\
IN FREE AIR
3!:
~
1.0
o
r--..
!
-t-
50
r-----
\
1--r--- ~ \
\
lO'C/W
eCA
Q.
U>
\)
\
HEAT SINK
HAVING
;:
V~TSINK
1\
-
..
.........
.\
:\\
--
~
o
50
100
150
200
AMBIENT TEMPERATURE - °C
II
MAXIMUM POWER DISSIPATION
AND TOTAL THERMAL RESISTANCE
AS A FUNCTION OF COPPER
AREA OF PC BOARD
PC BOARD
3!:
10
100
8.0
80
T
l
1
z
a
;: 6.0 I'\.
"iii
Q.
'"0
a:
f--
/!
~A
~~
2.0
rr
o
o
60
~ i" 1--- -- I---
4.0
~
aQ.
I I
- IPDlA~ e-
TTA[
10
40
~ 7r°C) r~ 1--- ._- 20
30
;::
,.iii'"-<
"
Z
m
I
40
COPPER DIMENSION - mm(l)
9-57
-<
i:i
:ll
;:
I
20
r---o
50
!?
:;
pA7392
DC MOTOR SPEED CONTROL CIRCUIT
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION-The IlA7392 is designed for precision, closed-loop, motor
speed control systems. It regulates the speed of capstan drive motors in automotive
and portable tape players and is useful in a variety of industrial and military control
applications, e.g., floppy disc drive systems and data cartridge drive systems. The device is constructed using the Fairchild Planar> epitaxial process.
The IlA7392 compares actual motor speed to an externally presettable reference voltage. The motor speed is determined by frequency to voltage conversion of the input
signal provided by the tachometer generator. The result of the comparison controls
the duty cycle of the pulse width modulated switching motor drive output stage to
close the system's negative feedback loop.
CONNECTION DIAGRAM
14-PIN DIP
(TOP VIEW)
PACKAGE OUTLINE SA, 9A
PACKAGE CODES D P
Thermal and over-voltage shutdown are included for self-protection, and a "stalltimer" feature allows the motor to be protected from burn-out during extended mechanical jams.
The IlA7392 is a low current compliment to the IlA7391 for those applications requiring
less current and also to drive high current output stages for very high current applications.
MOTOR
DRIVER
(.)r~'
STALL TIMER
11...... '
INPUTS
(-I[
TACH INPUT ( ) [
2
13 JNlC
3
12 ]
GND[ 4
TACH INPUT C·I[ 5
~ULSE TIMING[ 6
• PRECISION PERFORMANCE-FREQUENCY-TO-VOLTAGE CONVERSION STABILITY TYPICALLY 0.1'10 FOR V+ FROM 10 V TO 16 V; 0.3'10 FOR CASE TEMPERATURE FROM -40°C
TO +85°C
• HIGH CURRENT PERFORMANCE-1.0 A STARTING SURGE CURRENT AND 300 mA RUNNING CURRENT TO A DC MOTOR
• WIDE RANGE TACHOMETER INPUT-100 mVp-p TO 1.0 Vp-p
PULSE OUTPUT[ 7
11
OUTPUT EMITTER
J~8~~~TDRIVE
10 ]CLAMPING DIODE
9 JV8
J
~~~~b~TOR
• LOW EXTERNAL PARTS COUNT
• THERMAL SHUTDOWN, OVER-VOLTAGE AND STALL PROTECTION
• INTERNAL REGULATOR
• WIDE SUPPLY VOLTAGE RANGE-6.3 V TO 16 V
• EMITTER OF OUTPUT STAGE AVAILABLE FOR EASE IN DRIVING POWER TRANSISTOR
OUTPUT STAGES
• CLAMPING DIODE AVAILABLE ON SEPARATE PIN
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+), V9, V10, Vll
Regulator Output Current, 18
Voltage Applied to Pin 6 (Tachometer Pulse Timing)
Voltage Applied Between Pins 3 and 5 (Tachometer Inputs)
Continuous Current through Pins 11 and 12 Motor Drive Output ON
Repetitive Surge Current through Pins 11 and 12 (Motor Drive ON)
Repetitive Surge Current through Pins 10 and 11 (Motor Drive OFF)
Power Dissipation
Storage Temperature Range
Operating Temperature Range (I'A7392)
Operating Temperature Range i1lA7392C)
Pin Temperature (Soldering 10 Sl
*Planar is a patented Fairchild process
9-58
ORDER INFORMATION
TYPE
PART NO.
I'A7392
I'A7392C
!lA7392C
!lA7392DM
j.l.A7392DC
/LA 7392PC
24 V
15 mA
7 V
±6 V
0.3 A
1.0 A
0.3 A
Internally Limite'd
-55°C to +150°C
-55°C to +125°C
-40° C to +85° C
260°C
FAIRCHILD • pA7392
J.lA7392 and J.lA7392C
ELECTRICAL CHARACTERISTICS: V+
= 14.5
V, TA
= 25°C,
unless otherwise noted
VOLTAGE REGULATOR SECTION: (TEST CIRCUIT 1)
CHARACTERISTICS
CONDITIONS
Power Supply Current
Excluding Current into Pin 11
MIN
4.5
Regulator Output Voltage
Regulator Output Line Regulation (Il.Va)
V+ from 10 V to 16 V
V+ from 6.3 V to 16 V
Regulator Output Load Regulation (Il. Va)
la from 10 mA to 0
ELECTRICAL CHARACTERISTICS: V+
= 14.5
V, TA
= 25°C,
UNITS
TYP
MAX
7.5
10
5.0
5.5
V
6.0
12
20
50
mV
mV
40
mA
mV
unless otherwise noted
FREQUENCY TO VOLTAGE CONVERTER SECTION: (TEST CIRCUIT 2)
CONDITIONS
CHARACTERISTICS
MIN
Tachometer (-) Input Bias Voltage
TYP
MAX
2.4
= V3
Tachometer (+) Input Bias Current
V5
Tachometer input Positive Threshold
(V5 - V3)
1.0
10
20
Tachometer Input Hysteresis
V6
Pulse Timing ON Resistance
=1V
45
Pulse Timing Switch Threshold
V
10
I'A
25
50
mVpk
mVpk-pk
50
100
300
500
n
50
55
%Va
Output Pulse Rise Time
0.3
Output Pulse Fall Time
0.1
I's
I's
Pulse Output LOW Saturation (V7)
0.13
0.25
Pulse Output HIGH Saturation (Va - V7)
0.12
0.2
-260
-180
=1V
VFV = 0.25
-340
UNITS
V
V
Pulse Output HIGH Source Current
V7
Frequency-to-Voltage Conversion Supply Voltage
Va (Note 2)
V+ from 10 V to 16 V
0.1
%
VFv = 0.25 Va (Note 2)
TA from -40° C to +85° C
0.3
%
Stability (Note 1)
Frequency-to-Voltage Conversion Temperature
Stability (Note 3)
ELECTRICAL CHARACTERISTICS: V+
= 14.5 V,
TA
= 25°C,
I'A
unless otherwise noted
MOTOR DRIVE SECTION: (TEST CIRCUIT 3)
CHARACTERISTICS
CONDITIONS
MIN
TYP
Input Offset Voltage
0.1
Input Bias Current
0.8
Common Mode Range
Motor Drive Output Saturation
Motor Drive Output Leakage
Flyback Diode Leakage
Flyback Diode Clamp Voltage
= 300mA
V11 = V10 = 16 V
V10 = 16 V, V11 = 0
111 = 300mA
1.3
111
V
Motor Drive Output Off
9-59
1.1
MAX
UNITS
±20
mV
10
I'A
2.5
V
1.6
V
5
I'A
30
I'A
1.3
V
II
FAIRCHILD .• pA7392
J.lA7392, ~7392C
ELECTRICAL CHARACTERISTICS: V+ = 14.5 V, TA = 25°C unless otherwise noted
PROTECTIVE CIRCUITS: (TEST CIRCUIT 4)
CHARACTERISTICS
CONDITIONS
Thermal Shutdown Junction Temperature·
Note 4
Overvoltage Shutdown
Note 4
18
21
24
V
Stall Timer Threshold Voltage
Note 5
2.5
2.9
3.5
V
Stall Timer Threshold Current
Note 5
0.3
3.0
p.A
TYP
MAX
UNITS
7.5
12
MIN
TYP
MAX
160
UNITS
°C
J.lA7392 ONLY
ELECTRICAL CHARACTERISTICS: V+ = 14.5 V, -55°C S TA S +125°C, unless otherwise noted
VOLTAGE REGULATOR SECTION: (TEST CIRCUIT 1)
CHARACTERISTICS
CONDITIONS
Power Supply Current
Excluding Current into Pin 11
MIN
4.5
mA
5.0
6.0
V
Regulator Output Line Regulation (aVa)
V+ from 10 V to 16 V
V+ from 6.3 V to 16 V
6.0
12
20
50
mV
mV
Regulator Output Load Regulation (aVa)
la from 10 mA to 0
40
100
mV
TYP
MAX
UNITS
Regulator Output Voltage
FREQUENCY TO VOLTAGE CONVERTER SECTION: (TEST CIRCUIT 2)
CHARACTERISTICS
CONDITIONS
MIN
Tachometer (-) Input Bias Voltage
2.4
Tachometer (+) Input Bias Current
Vs =V3
Tachometer I nput Positive Threshold
(Vs - V3)
Tachometer Input Hysteresis
Pulse Timing ON Resistance
10
20
V6 = 1 V
Pulse Timing Switch Threshold
45
Output Pulse Rise Time
V
1.0
15
p.A
25
50
mVpk
mVp-p
50
100
300
670
n
50
55
%Va
0.3
Pulse Fall Time
p's
0.1
p's
Pulse Output LOW Saturation (V7)
0.13
0.25
V
Pulse Output HIGH Saturation (Va - V7)
0.12
0.2
V
-260
-150
p.A
Pulse Output HIGH Source Current
V7 = 1 V
Frequency-to-Voltage Conversion Supply Voltage
FFV = 0.25 Va (Note 2)
V+ from 10 V to 16 V
0.1
%
VFv = 0.25 Va (Note 2)
TA from -40°C to +85°C
0.3
%
Stability (Note 1)
Frequency-to-Voltage Conversion Temperature
Stability (Note 3)
9-60
-370
FAIRCHILD • J.LA7392
MA7392 ONLY
ELECTRICAL CHARACTERISTICS ConI. : v+ = 14.5 V, -55'C 2: TA oS +125'C, unless otherwise noted.
MOTOR DRIVE SECTION: (TEST CIRCUIT 3)
CHARACTERISTICS
CONDITIONS
MIN
TYP
Input Offset Voltage
Input Bias Current
0.1
Common Mode Range
Motor Drive Output Saturation
Motor Drive Output Leakage
Flyback Diode Leakage
Flyback Diode Clamp Voltage
0.8
= 300mA
V11 = V10 = 16 V
V10 = 16 V, V11 = 0 V
111 = 300mA
111
1.3
Motor Drive Output Off
MAX
UNITS
±30
mV
10
I'A
2.5
V
1.6
V
10
I'A
30
I'A
1.1
1.3
V
TYP
MAX
PROTECTIVE CIRCUITS: (TEST CIRCUIT 4)
CHARACTERISTICS
CONDITIONS
Thermal Shutdown Junction Temperature
Note 4
Overvoltage Shutdown
Note 4
18
Stall Timer Threshold Voltage
Note 5
1.8
Stall Timer Threshold Current
Note 5
MIN
160
UNITS
'C
21
24
V
2.9
4.0
V
0.3
4.0
I'A
NOTES:
1. Frequency-to-Voltage Conversion, Supply Voltage Stability is defined as:
~==:;-iX
100%
2. VFV is the integrated dc output voltage from the pulse generator (Pin 7)
3. Frequency-to-Voltage Conversion Temperature Stability is defined as:
l_
[VFvI85' Cl
[VB(85' cil
[VFVI-40' Cil -;- IVFV(25' C.I] X
VBi-40' CI
VBI25' CI
I
100%
4. "Motor Drive" circuitry is disabled when these limits are exceeded. If the condition continues for the duration set by the external stall timer components,
the circuit is latched off until reset by temporarily opening the power supply input line.
5. If stall timer protection is not required, Pin 14 should be grounded.
THERMAL DATA
OJA
THERMAL RESISTANCE, JUNCTION TO AMBIENT
PLASTIC (9A)
CERAMIC (6A)
9-61
TYP
MAX
70
100
80
120
°CIW
°CIW
FAIRCHILD • MA7392
BLOCK DIAGRAM
r--_~~---""'-o
r
\I
PULSE TIMING
J:
rr-=
.
6
O~
:2 (-)
7
0
I
•
f"\J
(+)5
/<>
~
I
() 3
PULSE
GENERATOR
I
I
I
votfi~~~~~l~TER:
:
1
________
I
8
r
-=
I REGg~~3~
I
I
1
1
V,
(+) 1
9
~ COMPARATORL
L...-J
I
!
I
VOLTAGE
REGULATOR
- ; ; D3
I
I
D~;;;R
OUTPUTS
~
A,
9' 'I
11
1
II
~
1
MOTOR DRIVE
I
1
I
THERMAL
SENSOR
V+
1
1
1
_
_
_
_
_
_
_
_
L
r-
1
121
DUTPUT
-=
EMITTER
1
PROTECTIVE
CIRCUITS
I
1
STALL TIMINGl_
THRESHOLD
AND LATCH
STALL TIMER
:
t
:
I
I
r
1M
1
I
OVER VOLTAGEL
SENSOR
I
1
v+
CLAMPING
-1
:
VOLTA~~C~~g~LATOR
I
1
-=
~,,=-TI~N _ _ _ _ 1 _ _ _ _S,=T~N_
J.
I
1
> ~[;~5~T
I
INPUTS
~
DRIVER
INPUTS
PULSE
A
TACHOMETER
rM-O-T-O-R-'V'V'v....
I
SUPPLY
VOLTAGE
I
I
1.
1
-r
L _______________________________________
:
~
TYPICAL PERFORMANCE CURVES
OVERVOLTAGE SHUTDOWN VOLTAGE
AS A FUNCTION OF
JUNCTION TEMPERATURE
STALL TIMER THRESHOLD
CURRENT AS A FUNCTION
OF JUNCTION TEMPERATURE
0.8 r---;---,--,--,--r--r-,---,
STALL TIMER THRESHOLD
VOLTAGE AS A FUNCTION
OF JUNCTION TEMPERATURE
3.6 r---,---r-----r-,----,-,--,.--,
>
~ 24~-+-+--+-+-~-~-~~
'1
3.4~
"~
23~-+-+--+-+--4-~-~~
2
22~-+-+--+-+--4-~-~~
3.2
3.0
:;!
2'
2.8 ~-+-+----+""+-~+-t--j
g
~r-
"
r--
~
~ 20~-+-+--+-+--4-~-r_~
~_
~W
15
'9~-+-+--+-+--4-~-~~
V+=14.5V
'"
i \
\
V+ = 14.5 V
u 0.5 ~-I\c-+--+-+--I-~-r_~
I---+---l--+---+--+"'----",j-----f---l
'8~-+-+--+-+--4--r-r_-1
2.21--+-+-+--+--+-+~--"f-----l
,77 .5~0,------,2:!::5,------:-0-,2::'::5,-----5;:';0,------,~75;-:-;'0:::0----:-;'2:::5--::"50
2.05'-0--2"'5--'--0-2:':5,-----5='0,------=75=-':-::0':-0-"'20.:5-----::"50
JUNCTION TEMPERATURE - °C
1
:;
~ 0.6 H\r+-+--+-+--4-~-~~
2.61--+-r_-+-t-~~r__t_-~_I
2.4
~ 0.7
JUNCTION TEMPERATURE - °C
9-62
!
9
"
04
"",
i=
0.3
~-+-+-11'--"--+--4-~-~~
~
02
I----"~_+__t_,~-=-+-+___j
>= 0.1 ~-+-+---+-+--4--r-r_~
-:::l
~
°5~0-~25;--:-0-2::'::5,-----::'::50;-~7~5----:-;'O:::0----:-;'2:::5--::"50
JUNCTION TEMPERATURE -- cC
FAIRCHILD • MA7392
TYPICAL PERFORMANCE CURVES (Cont'd.)
REGULATOR OUTPUT VOLTAGE
AS A FUNCTION OF
SUPPLY VOLTAGE
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
REGULATOR OUTPUT VOLTAGE
AS A FUNCTION OF
JUNCTION TEMPERATURE
5.4
6
12
>
5
10
5.3
V
I
w
CJ
I
....... f-""'
~
5.2
./
~ 5. 1
...::>
J
~ 5.0
II
I
I
I
TJ - 25°C
I I
I I
I I
o II
o
,.
12
a: 4.9
20
o
24
I
o
12
1.
I
~
'">
"...::>
~
""
;!
:;
4.6 50 -25
24
0
25
50
75
100
125 150
JUNCTION TEMPERATURE - °C
FLYBACK DIODE (03) CURRENT
AS A FUNCTION OF FLYBACK
DIODE VOLTAGE
600
5.
"I
700
E
54
./
52
V
50
~ 500
~ 400
o
v+
~
!
= 14.5 V
4.
300
V+ = 14.5V
200
0
44
42
/
/
0:
::>
....- V
48
600
!Z
V V
~
~
= 14.5 V
a:: 4.7
20
58
iii0:'"
v+
4.8
&:l
SUPPLY VOLTAGE - V
TACHOMETER INPUT HYSTE'RESIS
AS A FUNCTION OF
JUNCTION TEMPERATURE
E
::J
//
I
SUPPLY VOLTAGE - V
>
~
Tt - 25°C
I
1
V
V
o
/'
100
50
25
25
50
75
100 125
o
150
J
o
JUNCTION TEMPERATURE - °C
=I TA =roc
MOTOR DRIVE OUTPUT ON
VOLTAGE AS A FUNCTION
OF AMBIENT TEMPERATURE
1.46
.. '600
>
E
11400
~
!Z
1.44
~ 1.42
~1200
g
!!i
~1000
o
~ 1.40
/
~ 80Q
~
0600
!:;
~ 1.38
/
~
~
iE
/
~400
DO
/
FlVBACK DIODE VOLTAGE - V
MOTOR DRIVE OUTPUT ON CURRENT
AS A FUNCTION OF MOTOR DRIVE
OUTPUT ON VOLTAGE
~200
TJ
/
/
c
~~ 1.32
V+ = 14.5Y
TJ = TA = 25°C
I I
1.36
1.34
..
. /V
/'"
./
V
V+ = 14.5V
111 = 300 mA_
V
1.30
-50
/
TJi TA
25
25
50
75
100
AMBIENT TEMPERATURE _ °C
MOTOR DRIVE OUTPUT ON VOLTAG~ - Y
9-63
I
125 150
I
FAIRCHILD • J.lA7392
TYPICAL APPLICATION USING MAGNETIC TACHOMETER
330 kO
ch
RS
9.1 kO
SPEED
ADJUST
100 kn
lQkO
.01"F
±
2 kO
-==-
1
14-
2
13
3
12~
~4
11
~5
10
-6
RF
100 kO
9
1l.
I
I
I
I
~8
-=
F
±\
I
8-
7
:r
j
Rp
100 kO
10VT016V
I
I
~
b
•
.1
TACHOMET ER
(f~ NOMIN AL TACHOMETER
FAEQUE NCYI
rO.S,uF
TYPICAL COMPONENT VALUES:
Cp= _ _
4 Rpt
Ct
Cs
= 10 Cp to 1000 Cp depending on
= 2 X stall time-out
system requirements
RS
RMotor 2:':
5 !1
TEST CIRCUIT 1
TEST CIRCUIT 2
20 kO
TACH INPUT
14
VOLTAGES
(-I
13
(+1
loon
14
12
10 kO
13
11
loon
12
10
TACH
INPUT
VOLTAGE
ADJUST
REGULATOR VOLTAGE
11
v=
0.3 V p_p
AC
fNOM =: 1000 Hz
DC
-=
10
TACH
INPUT
100 kO
VFVO--r-~~~-t---L~__~~
(INTEGRATED
FREQ·TO·VOLTAGE
CONVERTER
OUTPUT VOLTAGE)
PULSE
I1J1F
OUTPUT 0---------'
VOLTAGE
9-64
100 kO
-=-+ 14.5 V
l
PULSE
.....- - - - - - - - - - - -......-{) TIMING
VOLTAGE
.0025/iF
J
FAIRCHILD • J.LA7392
TEST CIRCUIT 3
20 kO
MOTOR DRIVER
INPUT VOLTAGES
1+1
1000
10
+
v-=-
+
1000
+
MOTOR DRIVE
FLYBACK
~IODETEST
OUTPUT VOLTAGE
I~I
~
-=-
14
15 V
13
10 kO
flY BACK
INPUT
VOLTAGE
ADJUST
43 n
10w
100 kG
MOTOR
U~
MOTOR
DRIVE
OUTPUT
rEST
MOTOR
DRIVER
OUTPUT
10
LEAKAGE
FLYBACK
DIODE
LEAKAGE
+
COMMON
MODE
VOLTAGE
-=-
14.5 V
I 1
10kO
ADJUST
•
TEST CIRCUIT 4
STALL TIMER VOLTAGE
r-------------------~v+
+
-=
9-65
+
5 pF
DATA TRANSMISSION INFORMATION
SECTION 1 -
INTRODUCTION ....................................................... 10-3
SECTION 2 - DATA TRANSMISSION LINES AND THEIR CHARACTERISTICS
Transmission Line Model ........................................................
Input Impedance of a Transmission Line ..........................................
Phase Shift and Propagation Velocity for the Transmission Line ...................
Summary - Characteristic I mpedance and Propagation Delay .....................
10-4
10-5
10-7
10-8
SECTION 3 - REFLECTIONS: COMPUTATIONS AND WAVEFORMS
The Initial Wave ................................................................
Cut Lines and a Matched Load ..................................................
Kirchoff's Laws and Line-Load Boundary Conditions .............................
Fundamental Principles .........................................................
Tabular Method for Reflections - The Lattice Diagram ...........................
Limitations of the Lattice Diagram Method .......................................
Reflection Effects for Voltage-Source Drivers ....................................
Reflection Effects for Matched-Source Drivers ...................................
Reflection Effects for Current-Source Drivers ....................................
Summary - Which are the Advantageous Combinations? ........................
Effect of Source Rise Time on Waveforms .......................................
10-10
10-11
10-12
10-13
10-14
10-16
10-17
10-17
10-19
10-22
10-23
SECTION 4 - LONG TRANSMISSION LINES AND DATA SIGNAL QUALITY
Factors Causing Signal Wave-shape Changes ....................................
Influence of Loss Effects on Primary Line Parameters ............................
Variations in Zo, a (w) and Propagation Velocity .................................
Signal Quality - Terms .........................................................
Signal Quality Measurement - The Eye Pattern ..................................
Estimation of Signal Quality - In Lieu of Eye Pattern Measurements ........... '"
Other Pulse Codes and Signal Quality ...........................................
10-28
10-29
10-30
10-31
10-33
10-34
10-35
SECTION 5 - FORMS OF OPERATION
Single-Ended vs Differential .....................................................
Modes of Operation ............................................................
Standardized Interfaces .........................................................
Selecting Line Drivers and Receivers ............................................
System Considerations .........................................................
10-48
10-49
10-53
10-55
10-56
SECTION 6 -
SATISFYING EIA STANDARDS RS-422 AND RS-423 .................... 10-58
Section 1
INTRODUCTION
Digital signals transmitted any distance, only a few inches in
some cases or up to several miles, must enter the analog world
of transmission lines before arriving at their digitial destinations. Therefore, special attention should be given to the
interface between the digital and analog areas- often one of
the least understood considerations in a system design.
Interface problems occur every time a digital signal is sent
from a printed circuit board and, indeed, transmission line
theory must often be considered when connecting devices on
the same board when using very high -speed logic such as ECL
or Schottky TTL. This section is intended to shed some light on
this important design procedure- interfacing of systems (or
subsystems) for the transmission of information from one
location to another via line drivers, transmission lines and
line receivers.
Section two discusses the general characteristics of transmission lines and their derivations. Here, using a transmission
line model, the important parameters of characteristic impedance and propagation delay are developed in terms of their
physical and electrical parameters.
The third section explores another important characteristicreflection coefficient. This concept is combined with the
material in section two to present graphical and analytical
methods for determining the voltages and currents at any
point on a line with respect to distance and time after signal
application. The effects of various source resistances and line
termination methods on the transmitted signal are discussed.
In section four, the logical progression from the ideal transmission line to the real world of the long transmission line with
its attendant losses and problems is made; specifically, the
methods to determine the practicality of a certain length of
line at a given data rate is discussed. Transmission line effects
on various data formats are examined as well as the effects of
several types of sources (drivers) on signal quality. A practical
means is given to measure signal quality for a given transmission line using readily available test equipment. This, in
turn, leads to a chart that provides the designer a way to predict
the feasibility of a proposed data -transmission circuit when
twisted - pair cable is used. A method to estimate signal quality
on coaxial-cable interconnections is also discussed.
To design a data transmission interface, the systems designer
must be familiar with several subjects. He needs a good
understanding of the effects of pulse excitation on transmission lines, knowledge about the various fundamental forms
and modes of data -transmission -line circuit operation, and
familiarity with the problems encountered when operating
with long transmission lines. He must also have a good working knowledge of line drivers and line receivers, their electrical
characteristics, and how and where these devices should
be used.
This section is not intended to be a textbook in the formal
sense, nor is it a 'cookbook' of applications since each system
must be designed based on its unique requirements. It is
presented as a refresher on the basics of pulse transmission
line theory combined with methods for determining signal
quality and feasibility of the particular data transmission
system. Only those areas that directly affect the transmission
of digital signals are covered. This section contains the
essential elements to aid the system designer in making an
informed decision regarding the quality of data received at the
end of a transmission line.
Section five describes the various combinations of forms and
modes of operation in data -transmission systems. Also
described are the circuits that conform to industry standardsEIA RS232C, MIL STD l88C and IBM 360/370 I/O interfaces.
A selection guide for available line drivers and receivers integrated circuits and some helpful suggestions for incorporating
them into a system complete the section.
In section six, new EIA standards of RS -422 and RS -423
specifications are discussed.
10-3
I
Section 2
DATA TRANSMISSION LINES AND THEIR CHARACTERISTICS
INTRODUCTION
A data transmission line is composed of two or more conductors transmitting electrical signals from one location to another. A parallel transmission line is shown in Figure 2-1. To
show how the signals (voltages and currents) on the line relate to as yet undefined parameters, a transmission line model
is needed.
TRANSMISSION LINE MODEL
Because the wires A and B could not be ideal conductors, they
therefore must have some finite resistance. This resistance/
conductivity is determined by length and cross-sectional area.
Any line model, then, should possess some series resistance
representing the finite conductivity of the wires. It is convenientto establish this resistance as a per-un it-length parameter.
Similarly, the insulating medium separating the two conductors could not be a perfect insulator because some small leakage current is always present. These currents and dielectric
losses can be represented as a shunt conductance per unit
length of line. To facilitate development of later equations,
conductance is the chosen term instead of resistance.
wires as described by Coulomb's law.
E
-q-
(2.2)
4trEr2
where E is the electric field in volts per meter, q is the charge
in Coulombs, E is the dielectric constant, and r is the distance
in meters. These free charges, accompanied by a voltage,
represent a capacitance (C = q/V); so the line model must include a shunt capacitive component. Since total capacitance
is dependent upon line length, it should be expressed in a capacitance per-un it-length value.
It is known that a current flow in the conductors induces a
magnetic field or flux. This is determined by either Ampere's
law
(2.3)
I
or the Biot-Savart law
If the voltage between conductors A and B is not variable with
time, any voltage present indicates a static electric field between the conductors. From electrostatic theory it is known'
that the voltage V produced by a static electric field E is given
by
v
ft·dl
(2.1)
This static electric field between the wires can only exist if
there are free charges of equal and opposite polarity on both
CONDUCTOR A
dB
MIdi X r
= radius vector (meters)
= length vector (meters)
= current (amps)
B = magnetic flux density (Webers per
H = magnetic field (amps per meter)
~ = permeability
where r
1
-~~,.
CONDUCTOR B
I =
I =
E=
H
CURRENT FLOW
LINE LENGTH
ELECTRIC FIELD
MAGNETIC FIELD
=
Fig. 2-1.
Infinite Length Parallel Wire Transmission Line
10-4
(2.4)
4trr 3
meter)
For consistency, the circuit shown in Figure 2-2c will be used
throughout the remainder of this chapter. Figure 2-3 shows
how a transmission line model is constructed by series connecting the short sections into a ladder network.
If the magnetic flux (Q> ) linking the two wires is variable with
time, then according to Faraday's law
v
= dct>
(2.5)
dt
A small line section can exhibit a voltage drop - in addition
to a resistive drop-due to the changing magnetic flux (r~,"~
I'
-!-
I
Fig. 2-3.
.!-
I
.!-
I
I
.!
A Transmission Line Model Composed of Short, Series Connected Sections
lin
----"-IR
IL
IR
lL
IR
lL
'CE£3Dr~"."
I-
Fig. 2-4.
I
.!-
-I'
I
I
-!
Series Connected Sections to Approximate a Distributed Transmission Line
10-5
(2.7)
I
o
1
2
3
4
I~I-I
1--1-1-1-1-1-1-1-1
a
b
Fig. 2-5.
Cascaded Network to Model Transmission Line
Since it is assumed that the line model in Figure 2-5a is infinite in length, the impedance looking into any cross section
should be equal. that is, Zl =Z2 =Z3' etc. So Figure 2-5a can
be simplified to the network in Figure 2-5b where Zo is the
characteristic impedance of the line and Zin must equal this
impedance (Zin =ZO). From Figure 2-5b,
Zin = Z
s
ZOZp
= Zo
Zo + Zp
+ ---
such that the wl and wC terms are much larger respectively
than the Rand G terms, Zs = j w ! land Zp =1/ j w I C can be
used to arrive at a lossless line value of
=/f
Zo
(2.14)
In the lower frequency range,~
(2.9)
~ '" 1 kHz
27T
Multiplying through both sides by (ZO + Zp) and collecting
terms yields
the Rand G terms dominate the impedance giving
zo=~
(2.10)
which may be solved by using the quadratic formula to give
A typical twisted pair would show an impedance versus
applied frequency curve similar to that shown in Figure 2-6.
(2.11)
Zo
The Zo becomes constant above 100 kHz, since this is the
region where the wl and wC terms dominate and Equation
2.13 reduces to Equation 2.14. This region above 100 kHz
is of primary interest, since the frequency spectrum of the
fast rise/fall time pulses sent over the transmission line have
a fundamental frequency in the 1-to-50 MHz area with harmonics extending upward in frequency. The expressions for
2
Substituting in the definition of Zs and Zp from Equations 2.7
and 2.8, Equation 2.11 now appears as
Zo
I(R + jwL)
2
J 12(R + jwL)2
±
2
R +jwL
+ 4--G + jwC
(2.12)
10.000
Now, as the section length is reduced, all the parameters
(IR, Il, IG,and IC)decreaseinthesameproportion. This
is because the per-un it-length line parameters R, l, G, and C
are constants for a given line. By sufficiently reducing I,
the terms in Equation 2.12 which contain I as multipliers
will become negligible when compared to the last term
5000
2000
BELDEN 9270
1\
1000
\
1\
500
R +jwL
G +jwC
200
which remains constant during the reduction process. Thus
Equation 2.12 can be rewritten as
100
Zo =
mg
+jWL
--.-
G +JwC
--
= V ZsZp
50
(2.13)
w
"......
I
I
20
10
1k
particularly when the section length I is taken to be very
small. Similarly, if a high enough frequency is assumed,
27T
(215)
5k 10k
50k lOOk
FREQUENCY
> 100 kHz
Fig. 2-6.
10-6
I
500kl M
~
5 M 10 M
Hz
Characteristic Impedance versus Frequency
P
Vin
0---"":'-""
I ~D"o.~
o
, = 150, 300, 450, 1050, 2100, 3750 It.
24 AWG lWISTED PAIR Ro"'96Q
10 mA/div
Yout
Yout
o
2 V/div
t r =10ns 0
iin
tI
iin
5 1"\
u
1-'-1
2 V/div
2 ps
Fig. 2-7.
Input Current Into a 96n Transmission Line for a 2 V Input Step for Various Line Lengths
Zo in Equations 2.13, 2.14 and 2.15 do not contain any ref·
erence to line length, so using Equation 2.14 as the normal
characteristic impedance expression, allows the line to be
replaced with a resistor of RO = Zo n neglecting any small
reactance. This is true when calculating the initial voltage
step produced on the line in response to an input current step,
or an initial current step in response to an input voltage step.
Figure 2-7 shows a 2 V input step into a 96n transmission
line (top trace) and the input current required for line lengths
of 150, 300, 450, 1050, 2100, and 3750 feet, respectively
(second set of traces). The lower traces show the output volt·
age waveform for the various line lengths. As can be seen,
maximum input current is the same for all the different line
lengths, and depends only upon the input voltage and the
characteristic resistance of the line. Since RO = 96n and
vin = 2 V, then iin = vin/RO ~ 20 mA as shown by Fig·
ure 2-7.
=~ x
10 ns
.06 /LF
where C is the total capacitance of the line (C = C per foot x
length of line) and dv/dt is the slew rate of the input Signal.
If the 3750·foot line, with a characteristic capacitance per
unit length of 16 pF/ft is used the formula Ctotal (C x I )
would yield a total lumped capacitance of .06 jJF. Using this
C(dv/dt) = i formula with (dv/dt = 2 Vll0 ns) as in the scope
=
12 A
This is clearly not the casel Actually, since the line impedance
is approximately lOOn, 20 mA are required to produce 2 V
across the line. If a signal with a ri!le time long enough to
encompass the time delay of the line is used, (tr »t) then the
C(dv/dt) = i formula will yield a reasonable estimate of the
peak input current required. In the example, if the dv/dt is
2 V120 jJS, (tr = 20 jJs > t = 6 I-Is) then i = 2 V 120 I-IS x 0.06 I-IF
= 6 mA. which is verified by Figure 2-8.
There will probably be some phase shift and loss of signal v2
with respect to v1 because of the reactive and resistive parts
of Zs and Zp in the model (Figure 2-5bj. Each small section
of the line ( I ) will contribute to the total phase shift and am·
plitude reduction if a number of sections are cascaded as in
Figure 2-5a. So, it is important to determine the phase shift
and signal amplitude loss contributed by each section.
2 V/div 0
10 mA/div 0
tr= 20fJs
Yout
=
PHASE SHIFT AND PROPAGATION VELOCITY FOR
THE TRANSMISSION LINE
C(dv/dt) = i
iin
I
Figure 2-8 shows that C(dv/dt) = i only when the rise time
encompasses the capacitance to be lumped. The maximum
input current requirement will be with a fast rise time step,
but the line is essentially resistive, so vin/iin = RO = Zo will
give the actual drive current needed. These effects will be
discussed later in Chapter 3.
A popular method for estimating the input current into a line
in response to an input voltage is the formula
Vin
photo would yield
2 V/div 0
1-3750 It.-I
Ro=96Q,
a =1.6ns/lt.
Fig, 2-8. Input Current Into Line with Controlled Rise Time t.>2t
10-7
I
Using Figure 2-5b. v2 can be expressed as
(2.16)
and keeping in mind thev'ZsYP value will be much less than
one because the section length is allowed to become very
small, the higher order expansion terms can be neglected,
thereby reducing Equation 2.24 to
"II
V ZsYp
=
V (R + jwL)
= I
(G + jwC)
(2.26)
or
Zs(Zp + Zo) + ZpZO
(2.17)
If Equation 2.26 is divided by the section length,
ZpZo
"I
and further simplification yields
~
V2
[~
+ ~J
Zo
Zp
= 1 + Zs
(2.18)
Remember that a per-un it-length constant, normally called
Y is needed. This shows the reduction in amplitude and the
change in the phase per unit length of the sections.
(2.19)
Since
v2 = vI eXP(.-'Yl
vI exp(-"'I) + vI exp(-j(3l)
(2.20)
=
~'
= V (R
~~ ]
= In eXP("'1 + j(3l)
"'I + j(31 = "II
(2.21)
Thus, taking the natural log of both sides of Equation 2.18
Substituting Equation 2.13 for Zo and Yp for 1/Zp
(2.23)
(2.28)
Equation 2.28 shows that the lossless transmission line has
one very important property: signals introduced on the line
have a constant phase shift per unit length with no change in
amplitude. This progressive phase shift along the line actually represents a wave traveling down the line with a velocity
equal to the inverse of the phase shift per section. This
velocity is
v
w
1
(3
ViE
Yp = I(G + jwC)
SUMMARY - Characteristic Impedance and
Propagation Delay
Every transmission line has a characteristic impedance ZO'
and both voltage and current at any point on the line are related by the formu la
=
o
(2.24)
By using the series expansion for the natural log:
In (1 +
r)
=
r - r":' + r!...
2
'" r
for small
-etc.
(2.25)
I
/R+jwL
G+jwC
Since R«j w Land G«j wC for most lines atfrequencies above
100 kHz, the characteristic impedance is best approximated
by the loss less line expression
The propagation constant, Y , shows that signals exhibit an
amplitude loss and phase shift with the latter actually a velocity of propagation of the signal down the line. For lossless
lines, where the attenuation is zero, the phase shift per unit
length is
3
r
10-8
~
In terms of the per-unit-Iength parameters LRCG,
Z
will be very small compared to the constantv'Y /Zs = 1/Z0,
since the expression for Zo does not contain a reference to the
section length I . So Equation 2.23 can be rewritten as
(2.29)
for loss less lines. Because the LRCG parameters of the line
are independent of frequency except for those upper frequency constraints previously discussed, the signal velocity given
by Equation 2.29 is also independent of signal frequency. In
the practical world with long lines, there is in fact a frequency
dependence of the signal velocity. This causes sharp edged
pulses to become rounded and distorted. More on these long
line effects will be discussed in Chapter 3.
Zo =
Now when allowing the section length I to become small,
(2.27)
the propagation constant per unit length is obtained. If the
resistive components Rand G are further neglected byassuming the line is reasonably short, Equation 2.26 can be reduced
to read
where v1 exp(-O"/) is the signal attenuation and v1 exp(-j~l)
is the change in phase from v1 to v2'
In [
+ jwL) (G + jwC)
(3
This really represents a signal traveling down the line with a
velocity
For a more detailed discussion of characteristic impedances
and propagation constants,the reader is referred to the references below.
w
Hamsher, D.H. (editor); Communications System Engineering
Handbook; Chapter 11, McGraw-Hili, New York, 1967.
This velocity is independent of the applied frequency.
The larger the LC product of the line, the slower the signal
will propagate down the line. A time delay per unit length
can also be defined as the inverse of v
and a total propagation delay for a line of length
7~18~IVLC
Reference Data for Radio Engineers, fifth edition; Chapter 22;
Howard T. Sams Co., New York, 1970.
(2.30)
Matick, R.F.; Transmission Lines for Digital and Communications Networks; McGraw-Hili, New York, 1969.
(2.31)
Metzger, G. and Vabre, J.P.; Transmission Lines with Pulse
Excitation; Academic Press, New York, 1969.
as
I
10-9
Section 3
REFLECTIONS: COMPUTATIONS AND WAVEFORMS
INTRODUCTION
Substituting vin/RO for iin and collecting terms shows
In Section 2 it was determined that transmission lines have
two important properties: one, a characteristic impedance
relating instantaneous voltages and currents of waves traveling along the line and, two, a wave propagation velocity or
time delay per unit length. In this chapter, both Zo and [,
are used to compute the line voltages and currents at any
point along the line and at any time after the line signal is
applied. Also, concepts of reflections and reflection coefficients are explored along with calculating methods for voltages and currents.
U'
In -
v6flO
RO
j
(3.2)
+RsJ
This shows that both source and characteristic resistances act
as voltage dividers for the source voltage V. Figure 3-2 shows
voltage and current steps for the various source resistances.
Source resistances of less than Ra produce initial voltage
steps on the line which are greater than half the compliance
of the source voltage, V. A matched source (RS = Ra) produces voltage steps exactly half of V and source resistances
greater than Ra produce an initial voltage step less than one
half V in magnitude. Generators can be classified into three
categories:
THE INITIAL WAVE
Section 2 also showed that for most practical purposes,
where fast rise and fall time signals are concerned, the characteristic impedance of the line actually behaves as a pure
resistance (RO =y'L/C).
• Voltage source types where RS
•
Matched source types RS
•
Current source types RS
< RO
= RO
Figure 3-1 a shows a generator comprised of a voltage source
(magnitude V), a source resistance of RS ohms, and a switch
closing at time t = 0 connected to a lossless, infinite length
transmission line having a characteristic resistance, RO'
Because the relationship of vin to iin is known as vin = RO iin'
the lossless transmission line can be replaced with a resistor
as shown in Figure 3-1b. The loop equation is
> RO
Waveforms of these types will be discussed more fully in
section 4 on long line effects. Suffice to say that initial voltage wave amplitude depends greatly on source resistance.
Voltage source type drivers produce higher amplitude initial
voltage waves in the line than either matched source or current source type drivers .
(3.1 )
..
Zo
Fig. 3-18.
~ RO ~~
.------------- -
V
2
Fig. 3-1 b.
Generator Driving an Infinite Transmission Line
RS < RO
~--------------------- RS~RO
t------------- -
V
2 RO
RS > RO
o
Thevenin Equivalent for Initial Wave
_------------ _
RS < RO
1------------- -
RS ~ RO
1-____________ -
RS > RO
o
Fig. 3-2.
Voltage/Current Steps for Three Source Resistances
10-10
Applying Kirchoff's laws to point x in Figure 3-4, the current
to the load is
CUT LINES AND A MATCHED LOAD
In examining an infinite, loss less line (Figure 3-3), it is already
known that the ratio of line voltage to current is equal to the
characteristic resistance of that line. The line is lossless, and
the same voltages and currents should appear at point x down
the line after a time delay of xli. If the line at point x is cut,
and a resistor of value RO is inserted, there would not be a
difference between the cut, terminated finite line and the infinite line. The Vx and ix waves see the same impedance
(RO) they were launched into at time t = 0, and indeed, the
waves are absorbed into RL (= RO) after experiencing a
time delay of T = x Ii. So, from an external viewpoint, an infinite-length lossless line behaves as a finite-length lossless
line terminated in its characteristic resistance.
(3.6)
and voltage across the load is
To find the ratio of vr to Vx so that it can be ascertained how
much power is absorbed by the load, and how much is not
absorbed (therefore, reflected), substitute vx/RO for ix and
vr/RO for ir into Equation 3.6.
.
'L
(3.8)
(3.9)
RO
The minus sign associated with vr/RO means, in this case,
that the reflected voltage wave vr travels in the -x direction
toward the generator.
Collecting like terms of Equation 3.9 yields
Vx(~o
Figure 3-4 shows power available at the line end is derived by
(This is assuming in-phase current
-
~J= Vr(R~
-
~J
(3.10)
So,
= ix • Vx =
vx 2
(3.3)
RO
Vx (RL + RO\
The power absorbed by the load will be
v
=
L
Ur
RO
RO
[ Power available at] = [Power absorbed] + [Power not absorbed]
by the load
by the load
the line end
P
_
RO
3.8 yields
The principle of energy conservation, widely known and accepted in the sciences, applies as well to transmission line
theory; therefore, energy (as power) must be conserved at
boundaries between line and load. This is expressed in an
English language equation as follows.
Px
Vx
=
Rearranging Equation 3.7 and substituting for iL in Equation
KIRCHOFF'S LAWS AND LINE-LOAD BOUNDARY
CONDITIONS
the following formula.
and voltage).
(3.7)
vL = iLRL = Vx + vr
L
•i
L
=
=
Vx
(
RL -RO)
RO+RL
(3.11)
J
v 2
~
RoRL
and the desired relation for vr/vx is
(3.4)
RL
RL-R O
vr
while power not absorbed by the load is represented by
(3.12)
v2
= v • i =...!.-
P
r
r
r
This ratio is defined as the voltage reflection coefficient of
the load PVL
Vr
(3.5)
RO
Here, the r subscript stands for reflected (not absorbed) power, voltage or current, respectively.
Vx
(3.13)
'x
'5
t =0
PVL '"
rr:r>----_-+--f
_>'N'IT
~-'S
-'x x
.51
- - V ' R:'ORO
r - - - I
o
'51
r - - - I
o
a
I'---r-I-_ _
(too
I 0
RS' RO
--
-'s
-'s
V '~
--
·x L . . . - - , - - t - - - - - - - - - _
Fig. 3·3.
~
ts
,i
I
IX
t
--V'-RS~RO
'x
RQ. b
'L
'"-ltTI"'
IR
~"'-Il
'-'x
RS.RO
x8)
Voltages and Current on an Infinite Length Line
Fig. 3-4.
10-11
Boundary Conditions at the Line/Load Interface
A similar derivation for currents shows
the initial voltage is
RO
V
RO +Ro
2
V--(3.14)
PIL
Also assume RL
efficient is
For the remainder of the chapters. the
reflection coefficient is dropped. and
the voltage reflection coefficient of the
ing Kirchoff's laws to the source-line
reflection coefficient of the source is
v or i subscript on the
PL is assumed to be
load. Similarly. applyinterface. the voltage
Ps
=3
RO' then the load voltage reflection co3RO-RO
P
=
L
=
3R O + RO
v
V
4
-
+-
2
V
4
(3.19)
3V
4
(3.20)
The reflected voltage wave vr generated at t = x 8 = T travels
back down the line toward the source arriving at the source
at time t = 2x8 = 2T . This wave will be absorbed without
generating another reflection because RS was picked to equal
RO' making Ps equal to zero. The source voltage is now
When a traveling wave vx ' ix meets a boundary such as the
line load interface. a reflected wave is instantaneously generated so that Kirchoff's laws are satisfied at the boundary
conditions. This is the direct result of the conservation of
energy principle. Referring again to Figure 3-4. the effects
of three different termination resistance RL values are shown.
V
V
3V
2
4
4
v+v=-+r
S
Case 1. RL = RO
In this case. RL is equal to the characteristic resistance of the
line. Using Equation 3.13. the voltage reflection coefficient
of the load PL is
o
(3.18)
and the load voltage is
The current reflection coefficient of the source has the same
magnitude as PS. but is opposite in algebraic sign.
o
1
+2
The voltage wave arriving at point x at time t = x8 generates
a reflected voltage wave of magnitude
(3.15)
2RO
(3.17)
(3.21)
and equilibrium is achieved.
If the circuit in Figure 3-4 is analyzed using simple circuit
theory and neglecting the transmission line effects. it is easily
seen that
(3.16)
3V
4
Since vr/vx = PL. then vr = PL Vx = 0 and no reflection is
generated. This agrees with the discussion of cut lines and
matched load where a line terminated in its characteristic
impedance behaves the same as an infinite line. All power
delivered by the line is absorbed into the load. The waveforms appear as shown in Figure 3-5. The wave starting at
the source at time t =0 is reproduced at point x down the line
after a time delay of t =x 8 = T
(3.22)
This agrees exactly with Equation 3.21 and will always be
the case. After all reflections cease and the circuit reaches
equilibrium. the steady state voltages and currents on the
line are the same as those produced using simple dc circuit
analysis. Waveforms for RL > RO (specifically RL = 3 RO)
appear in Figure 3-6.
Case 2. RL > RO
To simplify this case. assume that RS
's
's
II
=RO'
In general. the case where RL > RO is viewed in the following
manner. Because the line is capable of delivering more pow-
This means that
V
"
': iu=~~. s - - 4 _ 3':L
RO
RO + RS
t
IL.......L.-...._____
R~I~l===-~=R=~:===~::::~::~::::~::==~~R:o::=:
1
,~ L----+4~_=_-=--=-:-=-:=:=
V
RO + AS
"t
I
'L~--V
----.--
iii:
'L~I+ - - - _ "
Fig. 3-5.
3~
~
-RO'RS
-1
t
..
~ 1L--,__
V
AO + AS
--,,--"~
V
4R
-t-__ _OT'_ _, '_ _"r-_--r,
t
Waveforms for RL = RO
2.
Fig. 3-6.
10-12
3r
RS
=RO'
4T
RL
5<
=3
RO
6T
t
t
V
4
er than can be instantaneously absorbed by the load, the excess power is returned to the source and absorbed in the
source resistor (assuming RS = RO)'
This agrees with the result of Equation 3.27. The waveforms
for Case 3 (RL < RS) appear in Figure 3-7.
An upper limit on the voltage reflection coefficient is found
by allowing RL to go to infinity. In this case, Equation 3.13
goes to +1.
An interpretation of the actions occurring when load resistance is less than the characteristic line resistance is as follows: when power available at the line end is less than the
power the load can absorb, a signal is sent back to the source
saying, in essence, "send more power".
Case 3, RL < RO
:In this case, again set RS = RO and allow RL to equal RO/3.
The initial wave, as before, is
RO
V
Us = V - - 2
Ro + Rs
and the load voltage reflection coefficient is
It has been shown that a ratio of line and load resistance ( P)
can be used to calculate the voltages and currents in terms of
a wave arriving at the boundary, possibly generating a reflected, reverse-traveling wave to satisfy the conservation of energy principle at the line-to-Ioad boundary. This ratio is
(3.23)
Ro
3'-R O
3+
RB -Ro
PB = RB + RO
(3.24)
2
RO
RO
V
V
= PL '2 = -4
(3.25)
which starts propagating back toward the source at time
t = T. The load voltage at time t = T is
V
4
The forward traveling wave, vx' plus the reflected wave, vp
is equal to the load voltage (V L )· Since vr is P L v x ' this
can be expressed as
(3.26)
+-
The (-V/4) reflected wave arrives back at the source at time
t = 2 T. Because RS is set equal to RO' Ps is, then, equal
to zero and no reflected wave will be generated. The voltage
at the source is now
V
- +
2
V
4
+0
=
V
4
(3.30)
This quantity (1 + P) can be defined as the voltage transmission coefficient of the load and it is known that
UL
-;;
(3.27)
(3.31 )
= (1 + PLY
x
The cases with various load resistances can be summarized.
From a dc circuit analysis, the steady state voltage is
Circuit at time t
delay time)
Condition
v:
1
~1
(3.29)
where RB represents the resistance into the boundary, RB
is RS when considering the source-to-line interface and RB
would be RL when considering the line-to-Ioad interface.
It is obvious that if discussing impedances, then Zs would
be substituted for RS in Equation 3.29, and there may be
some phase angle between the voltage and current waves.
Therefore, the reflected voltage wave vr is
ur
(3.28)
=T
(one line
v
V
4
2
=0
No reflection is produced-circuit
reaches steady state immediately .
2. RL>RO
PL>O
Positive voltage reflection-wave
is sent back toward source. Voltage at load is higher than steady
stage voltage (overshoot).
3 . RL < RO
PL <0
Negative voltage reflection-wave
is sent back toward source. Voltage at load is lower than steady
state voltage (undershoot).
1. RL
•
= RO
PL
t
~
4 RO
:!...2 RO
•
t
FUNDAMENTAL PRINCIPLES
Before examining the algorithm for keeping track of reflections, there are two principles to keep in mind .
~ 1~,-_~r-
~
4~~0
__- r____TI____
2T
3T
____-rI__
4T
~.
t
5T
Fig. 3-7.
10-13
•
Energy (as power) is conserved at boundary conditions (as
explored previously)
•
The principle of linear superposition applies. This means
any arbitrary excitation function can be broken down into
step functions, or ramps. The reaction of the circuit to each
part can be analyzed, and the results can be added together
when finished. This means that a positive pulse of duration t is examined by superimposing two step functions,
•
DESIRED
D
'01
FUNCTION
II,
POSITIVE
UNIT STEP
NEGATIVE
UNIT STEP
-
Fig. 3-8.
f (t)
=u (t -
11) - u (t - t2)
•
I, (t) = u (t -
in the down direction, to represent the location on the line under examination. Because voltages at the source and load
ends of the transmission line are normally of primary interest,
two time scales are necessary. Drawing arrows from one time
scale to the other as in Figure 3-10 shows the direction oftravel of the waves during a specific time interval. Since the main
concern is only with the waveforms at the line ends, time
scales are ruled off in multiples of the time delay of the line
T. If a unit-step type wave is launched from the source at
time t = 0+, it is known that the magnitude of the wave will
persist unchanged until a wave arrives back from the load
after a round trip delay time of two line delays. The source
time scale then is incremented in multiples of 2mT where
m = 0, 1, 2, 3, . . . likewise, the first wave arrives at the
load after a single time delay, so the first increment ruling
on the load time scale is T, or one time delay of the line. Because the subsequent waves arrive back at the load in increments of 2 t ,the load time scale is ruled off in multiples of
(2m + 1) t where m = 0,1,2,3, . . . The operation of the lattice diagram is discussed using the example in Figure 3-10b
which is the lattice diagram for the associated circuit.
I
t,)
,
Superposition of Simple Waveforms to Form
More Complex Excitations
~
I::!:..
positive
negative
wave
traveling in
wave
traveling in
+x direction
+x direction
~i
i .....
~
+L
positive
wave
traveling in
negative
wave
traveling in
-x direction
-x direction
~i
i .....
time t
= 0- (just before the switch
closes)
Direction of Current Flow in Top Conductor
Fig. 3-9.
The voltages at the source and load are equal with a magnitude
of IIjnitial.Assume that no initial voltage is present. So,
in this case, the voltage at the source and load equals zero.
Sign Conventions for Waves
one positive and one negative, starting after a delay of t
(Figure 3-8). It also means the voltage at any point on the
line is the sum of initial voltage plus the sum of all voltage
waves that have arrived at or passed through the point up
to and including the time of examination. Also, the current on the line is, at any point. the sum of initial current
plus any forward or reverse traveling currents passing the
point up to and including the time the current is examined.
o
Vinitiai
time t
=0+ (just after the switch
has closed)
The first wave vi(l) is launched at the source and begins to
travel toward the load end of the line. As previously mentioned, a voltage divider action between RS and RO is used
to derive the magnitude of the initial voltage wave.
It has also been established that the steady state solution for
voltages and currents on the line can be found by simple dc
circuit analysis.
In examining reflection effects for the remainder of this book,
the following conventions are used.
At this time, the voltage at the source is the sum of the initial
voltage plus the voltage wave vi(l) just generated.
A voltage or current wave traveling toward the point of interest will have the subscript "i" for incident wave.
RO
us(O+) = Us (0-) + ui(1) = 0 + V - - RO + Rs
A voltage or current wave traveling away from the point of
interest will have the subscript "r" for reflected wave,
Because the switch closure represents a step function, the
source voltage remains at this level until a wave returns
after reflecting from the load at time t = 2 T
The subscript "s" means the parameter applied to the
source (vS for the voltage at the source, etc.), and
time t =
T
The incident voltage wave vi(l) now arrives at the load
and generates a reflected voltage wave
The subscript "L" means the parameter applied to the load
(vL for the voltage at the load, etc.)
ur (1)
Sign conventions for voltage waves and their associated
currents are shown in Figure 3-9.
= PLu,·(i);
P
RL -Ro
L - RL + Ro
where P L is the voltage reflection coefficient of the load.
The reflected voltage wave v r(l) immediately starts traveling back toward the source becoming the incident voltage wave vi(2) which arrives back at the source at t = 2 T .
The voltage at the load is now the sum of the initial voltage
plus the incident voltage wave vi(1) that just arrived plus the
reflected voltage wave that is just departing.
TABULAR METHOD FOR REFLECTIONS - THE
LATTICE DIAGRAM
The waves going up and down the line can be monitored by
drawing a time scale, as a vertical line with time increasing
10-14
RO
V - - - + ui(2) + Psui(2)
RO + Rs
Ro
VR - - + ui(2) (1 + Ps)
0+ Rs
time t
Again, because of the step function excitation, the load voltage remains unchanged until the new wave arrives at time
t = 37 .
= 3T
vi(3) arrives at the load generating v r(3)
ur (3)
= PL ui(3)
v r (3) departs back toward the source becoming vi(4) to the
source. The load voltage is now
time t = 27
ud3)
vjl2) now arrives at the source and generates a reflected
voltage wave v r(2) of magnitude
time t
=
ud1J + ui(3) (l + PLY
=4T
When vi(4) arrives at the source and generates v r (4), then
ur (4)
where PSis the source voltage reflection coefficient.
The reflected voltage wave v r (2) starts back toward the load
end of the line and becomes the incident voltage wave vi(3)
arriving at the load at time t = 37 . The voltage at the source
is now the sum of the voltage that was there plus the incident
voltage wave just arrived plus the reflected voltage wave just
departed for the load.
(4~
= Ps ui(4)
starts back toward the load to become vi(5) to the load. The
load voltage is now
ud4) = ud2) + uj(4) (1 + PLY
This process can continue ad infinitum or until no measurable
changes are detected. The reflection process at that time is
considered complete and the line assumes a steady state condition. Steady state conditions can be found by applying
simple dc circuit theory to source load circuits.
~.
,ell
'-----_-'"7'5--<0>------------------ '-'L
(a) Line Circuit to be Analyzed
LOAD
SOURCE
v S (2) =
vr(2):=
,vs(m}
Vs
Ps
:=
v~m):=
(0+) + vi(2) + Ps vi(2j
vi(2j:= Vi(3)
vL(m) = v L (m-2J + vj(mj (1 + PL)
Vs (m-2J + vi(m) (1 + P 5)
Ps
vrlm) = PL vi(m):= Vi (m+1)
vi(m) = Vi (m+l)
mODO
m EVEN
(b) Lattice Diagram
Fig. 3-10.
Reflection Bookkeeping with the Lattice Diagram
10-15
Summarizing this lattice diagram method, any time t = m T
and m > 1, the following relationships exist:
A similar expression of summation can be developed for the
voltage (or current) at any point along the line at any time.
If m is odd, the vi(m) wave is arriving at the load and gener·
ates a reflected wave
Because the lattice diagram is tabular in method, a computer
program can be written relieving the designer of bookkeeping
and repetitive calculations. A BASIC computer program for
lattice diagrams appears in Figure 3-13.
This becomes vi(m+l) as it starts toward the source.
voltage at the load at time t = m T will be
The
LIMITATIONS OF THE LATTICE DIAGRAM METHOD
Before using the lattice diagram to explore reflection effects
with various source and load characteristics, it is necessary
to pause at this point and examine the models used by the
lattice diagram.
This is the sum of the voltage that was there before the wave
arrived, i.e., vL(m-2), plus the wave arriving vi(m) and the
reflected wave vr(m) departing.
First, both the line driver and receiver are simulated either by
a constant input or output resistance. The source has two
voltage sources and a switch representing the internal source
voltage at a time less than zero and equal to (or greater than)
zero. The receiver is represented by a single resistor shunting
the line end opposite the driver site. The line itself is represented by its characteristic resistance RO and its total oneway time delay ( T). This is equal to length times propagation
delay per unit length. This model is shown in Figure 3-".
If m is even, the vi(m) wave is arriving at the source and generates a reflected wave
This becomes vi(m+l) as it starts toward the load. The voltage at the source is now
vs(m)
= vs(m - 2) + vj(m) (1 + Ps)
Because most data communication circuits are voltage types,
that is, the receiver senses the line voltage to decide if a logic
One or logic Zero is present, the primary interest is in voltages
at the source and load as a function of time. Major exceptions
include the current loops used in teletypewriters, telegraphs,
and burglar alarm systems. The majority of data communications circuits used in computers, peripherals, and general
controllers are voltage types.
This is the sum of the voltage that was present vs(m-2) plus
the incident wave arriving vi(m) plus the reflected wave departing vr(m).
The voltage and current at the source end of the line for a lossless line can be expressed as a summation.
RO
vs(t)
t
(3.32)
=---.
The lattice diagram method cannot easily use source or receiver currentlvoltage relationships that are non-linear; i.e.,
not purely resistive. For non-linear current/voltage character-
Rs + Ro
1
00
e(t)u(t)+ (l + - ) ~
Ps n =1
is(t)
= -1- - .
Rs + Ro
(3.33)
DRIVER
RECEIVER
~
TRANSMISSION LIN'
~
1-1-- -----.011
where eft) is the generator voltage as a function of time, and
iu(t) IS the unit step function.
Likewise, the load voltage and load current for the loss less
line can be expressed as a summation.
RO
=---.
(3.34)
~
Rs + Ro
RO'
~~'S_ _ _ _ _ _ _ _ __
DRL
1
=---.
Rs +Ro
(3.35)
Fig. 3-11.
10-16
Model used for lattice Diagram Method
to 3 T may cause breakdown of the input circuitry of a receiver, depending on the receiver voltage rating. The undershoot
at t = 3 T to 5 T can reduce the noise immunity of a receiver
or even cause a logic level misinterpretation - an error in the
data. These waveforms are shown in Figure 3-12a.
istics such as found in diodes, a graphic method can be used
called the reflection diagram or the Bergeron* method.
Signals exchanged using lattice diagrams are of the unit step
variety. When ramps or more complex waves are exchanged,
the complexity of the bookkeeping increases dramatically.
Additionally, the lines are presumed to be lossless, although a
constant line attenuation factor could be accommodated without excessive bookkeeping. These limitations should be kept
in mind when examining various source and load resistance
combinations and their reflection characteristics.
If RL is less than RO' then PL is negative and a wave arriving
at the load generates a reflection opposite in polarity to the
incident wave. This causes the voltage at the source to overshoot steady state voltage at t = O. Each reflection returning
from the load causes the source voltage to continually step
down toward the steady state voltage VSS. These steps last
for 2 T , or one round trip delay. Load voltage starts an increasing step-up waveform towards VSS at time t =T , with
steps again taking one round trip delay, 2 T . A line receiver
placed in the middle of the line sees an entirely different
waveform - dampened oscillations much like the load voltage in Figure 3-12a. This is caused by the negative signs of
both source and load voltage reflection coefficients. Each
time an incident wave arrives at either source or load, the
reflected wave generated at that time has a sign opposite to
the sign of the incident voltage wave. The voltage at a distance half way down the line is composed of these forward
and reverse traveling waves arriving at that point commencing
at time t = 0.5 T , and with each new wave passing that point
after one line delay ( T). These waveforms are shown in Figure 3-12c.
There are three classes of source resistance, RS < RO' RS = RO
and RS > RO. There are also three classes of load resistance,
RL < RO' RL = RO and RL >RO. This gives nine types of single
driver, single receiver line circuits. Each circuit will be examined in turn to determine reflection effects for these combinations with evaluations of each combination for voltage type
communications.
REFLECTION EFFECTS FOR VOLTAGE SOURCE
DRIVERS
Initial waves launched by a voltage source type driver (RS < RO)
are greater than one-half the magnitude of the internal voltage source. Referring to Figure 3-11, the initial voltage wave
is derived as follows.
vp)
(3.36)
The optimum load resistance for voltage signal communications on transmission lines driven by a low impedance source
(RS < RO) is equal to the characteristic line resistance. Large
signal line voltages are produced and there are no reflection
effects complicating the waveforms (Figure 3-12b).
while the voltage at the source at t = 0+ is
However, a matched load (R L =RO) is a dc load on the driver,
thus it increases system power dissipation. But, it does preserve signal fidelity and amplitude allowing use of multiple
bridging receivers (Rin»RO) along the line.
If the receiver switching point is at the mean of the driver
voltage swing, the initial wave always has sufficient magnitude to indicate the correct logic state as it passes the receiver
site. This maximizes the noise margins of the receiver.
Since RS < RO' the source voltage reflection coefficient PS
is less than zero. Any voltage waves, then, arriving back atthe
source are changed in sign, reduced in amplitude (assuming
RS > 0 n), and sent back toward the load. If the load resistance equals the characteristic line resistance (RL = RO), the
voltage reflection coefficient of the load is
o
2RO
The unterminated case (R L > RO) reduces dc driver loading
and also reduces system power dissipation over the matched
load case. The unterminated case does, however, allow the
load signal to exhibit pronounced overshoot and undershoot
around the steady state voltage. If the load signal undershoot
places the receiver in its threshold uncertainty region, data
errors result. There is a way to" civi lize" the voltage waveform
of the unterminated line load by trading off signal rise time
versus line time delay. This is discussed later.
o
No reflections, therefore, are generated at the load. The voltage wave produced at the source is reproduced at the load
after a time delay of T = lUi , and the line assumes a steady
state condition. Figure 3-12b illustrates the source and load
voltage waveforms for this case.
The final case of RS < RO and RL < RO is not generally
useful in terms of voltage signals produced (Figure 3-12c.)
Systems using this case consume more power than the previous two cases and have no particular advantage for voltage mode communications.
If RL is greater than RO' PL is positive. Waves arriving at the
load generate the same polarity reflections as the arriving
waves. Ps and PL are of opposite signs, so a dampened oscillatory behavior of the load voltage is expected. The oscillation period or ringing is 4 T . The overshoot of vL from t = T
REFLECTION EFFECTS FOR MATCHED-SOURCE
DRIVERS
In all three cases under discussion here, the initial voltage
produced by the driver onto the line is
*A French hydraulic engineer, L.J.B. Bergeron developed the method to study
the propagation of water hammer effects in hydraulics. See references,
RO
(Vo+-VO-)-R
R
0+
Chapter 2.
10-17
S
RL = RO
RL>RO
Vat ..... _ _
Vat
RL
s
P = 00
Vss
RS = RO
',Is'
RS=l00Q
RL = loon
Vat
2,
6,
4,
8,
6,
4'
8,
2,
4,
(d)
6,
r
n
vSOURCE
v LOAD
Vss
I_
t
2,
8,
(e)
4,
t
8'
6'
(f)
RL=1000U
RS = 1000
Ps=
~J
PL=+818
Va'
Va'
RS-l000Q
-I
RL = 100 Q
Ps = +.818
RL = RO
RS>RO
\Is'
vL
I- - - - -
- -
-
- - - - - -
Vss
',Is'
vL
Va'
1
RS=1000Q
RL
RL = 10 U
P = +.818
s
< RO
PL = -.818
PL = 0.0
I
\Is·
vL
VSimaxi = 0 09 V
---V LOAD
1
2T
6,
4'
,--r--:=::::;:::::;::::::;:;-;::2,
8T
4T
6,
V I (max)" 0.0165 V
Vss
8T
2T
(h)
(g)
T
=a
tvo+ ovt
=1
jvo-=oovj
vSDURCE
r'MIDLiNE 'LOAD r
RL
!~ TRANSMISSION UNE-l----.-)
1_ _/12 ____ 1
Fig. 3-12.
4~_
(i)
RO = tOOll
RS
Vss = 0.099 V
I'
Source and Load Voltage Waveforms for Various RS and RL
6y
8T
will be close to +1.0. Because source resistance is set equal to
line resista nce, P S becomes zero, the reflected voltage wave
from the load is absorbed by the source at time t = 2 T , and
steady state conditions prevail. Waveforms for this case are
shown in Figure 3-12d, This is called back matching or series
termination.
since RS = RO' The voltage at the source at time t = 0+ is
vs(O+)
~
vs(O-) + v;(1)
~
RL
VO- • - R
R + Vj(1)
L + s
(3.39)
Assume, for clarity, that initial voltage (VO-) is zero, thus
Equation 3.39 simplifies to
Vs (0+)
The main advantage of series termination is a great reduction in steady state power consumption when compared with
the parallel terminated case (RS« RO' RL =RO)' At the same
time, series termination provides the same Signal fidelity to a
receiver placed at the line end. Compare the load voltage
waveforms for the two cases in Figure 3-12b and 3-12d. The
main disadvantage to series termination is that receivers
placed along the line see a waveform similar to that shown
for the source in Figure 3-12d. That is, receivers along the
line see the VO+/2 initial wave as it passes that point on the
line, and do not see a full signal swing until the load end reflection passes that point. Consequently, receivers along the
line do not see a signal sufficient to produce the valid logic
state output until the load reflection returns. Depending on
actual line length and receiver characteristics, the receiver
may even oscillate, having been placed in its linear operation
region. With the benefit, then, of reducing system power,
the series termination method has a constraint of allowing
only one line receiver located at the line load end. The parallel termination method should be used if other receivers along
the line are required.
(3.40)
Since RS = RO' Ps is equal to zero. This means that
load-generated reflections due to load mismatch are absorbed
at the source when, at time t = 2 T ,the reflected wave arrives back at the source. The line then assumes a steady state
throughout. This back match or series termination effect of a
matched source allows a wide latitude in choice of load resistance without sacrificing the signal fidelity of the load voltage
waveform.
If the load resistance equals the characteristic line resistance
RL = RO' then PL equals zero and no load site reflections
are generated. The initial voltage wave arrives at the load at
time t = T (one line delay) and voltages (and currents) on the
line immediately assume steady state conditions (see Figure
3-12e). The optimum receiver threshold here is one-half the
steady state voltage or VO+/4. The main advantage over the
voltage source type driver with matched load case (RS < RO'
RL = RO) is that RS and RL resistance tolerances may be relaxed without incurring much signal ringing. This effect is
due primarily to the termination provided by both line ends,
rather than just one line end. Any reflected voltage wave on
either system is attenuated by the product of Ps and P L for
each round trip line delay time. Since the Ps PL product
for the fully matched case is smaller than the PS PL product for the single matched case, the reflections are attenuated and die out in fewer round trips. For example, if 20%
tolerance resistors are used in both cases, Ps and PL values
for the fully matched case become 0.0 ± 0.0909, which is a
Ps PL product of ± 0.0033. This means that after one round
trip (2 T ), the reflection amplitude starting back toward the
load would be less than 0.33% of the initial wave.
The final case of matched source drivers is with the use of a
load resistance less than the characteristic line resistance.
The waveforms for this case are shown in Figure 3-12f. A
line receiver with a threshold of V 014 placed at the source
responds like a positive, edge triggered one-shot and produce
a pulse in response to a +V 12 initial wave of 2 T duration.
Aside from its use as a one-shot, this circuit doesn't seem to
offer any advantages for voltage mode communications.
REFLECTION EFFECTS FOR CURRENT-SOURCE
DRIVERS
The name current source drivers is somewhat of a misnomer,
and might be more properly called current-limited voltage
source drivers. True current source drivers such as the 75110
are normally used in conjunction with parallel termination
resistors to create a matched source.
Using RS = 10 n, RL = 100 n, and RO = 100 n as for Figure 3-12a, shows the same 20% tolerances applied to the single matched case
-0.8519 .;;; Ps .;;; -0.7857
and
-0.0909 .;;; PL
IPSPL I .;;;
.;;;
The current source drivers (RS > RO) discussed resemble true
current sources in the respect that their output resistance is
usually much greater than the characteristic line resistance.
The initial voltage step produced on the line is thus usually
small vi(l) = (i!!(1 )RO)' This is due to the voltage divider
action of the driver source resistance and the characteristic
line resistance.
+0.0909
0.0774
The voltage reflection amplitude after one round trip is a
maximum of 7.7% of the initial wave.
The choice between using the single and fully matched system should be carefully considered because the fully matched
system does sacrifice signal voltage magnitude to get a decreased dependence on absolute resistor values.
Voltage waveforms for a current source type driver either
step up to VSS' reach steady state after 2 T , or execute
a dampened oscillation around VSS' depending on whether
the load resistance RL is greater, equal, or less than RO' respectively. The second case RL = RO provides signals much the
same as the other two cases where RL = RO' that is, the
source voltage steps immediately to VSS' with the load voltage following after one line time delay. Here the amplitude of
If the load resistance for a matched driver circuit is made
much greater than the line resistance, the initial wave arriving at the load at time t = T will be almost doubled since PL
10-19
....
iii
the signal is much smaller than previous matched load cases.
Since the current source type drivers (75109/110) have
high off-state impedances, they allow multiple drivers on the
line to produce a data bus or party line. This aspect will be
discussed in more detail in Chapter 5. Waveforms for the
matched load case are shown in Figure 3-12h.
O.~
2.;
:..,
0./3390
0.172HH
4 ')
0
0.13440
0.11288
_ _ _ _ _ __
+0.313%
+0.000';
2odl!l.----D....2QH~.B....-_±.O
... .,?'OJ'"O._ _ _ _ _ __
,.;
".,
0.24170
O.241W
+0.000%
. 0.21206
0.27243
+0.136%
~ •..31J09.J---'l_3D~Y..3 _ _ +.u.LlOCl:L--.-. _ _ _ __
O.J2100
0.32137
+0.097%
Y.:>
0.30190
O.3,IW)
+0.000%
10'2
0 LL13Y--D...-1IIf.66. _ _+Ll..JlLI£Tx<-'_ _ _ _ __
II.:>
O.39'J7/
O.39'JT/
+0.000%
12.~
O.41'J12
0.41~36
+0.0:>7%
~.A.D"l-.O..A3.l':l..3----".o..":OIUOOU:X"-_ _ _ _ __
14.~
O.''bOIB
0.4";038
+0.04:'%
I~.:-J
0.46602
0.46002
+0.000%
e.,
-.l.t..L...!:L...........1..a:l3~'O!,)~"O""D3..6"t
O.4Y3')9
D.':l0032
D.5
IB.j
) 9 ~I
2'O.:-J
21.;
The RL> RO case is of interest because it is representative
of DTL driving a transmission line with the output going from
LOW to HIGH. DTL has a high value RS' (2 kn or 6 kn ) in
the HIGH logic state. Since both RS and RL are greater than
RO*' both Ps and PL are positive. A small voltage step
starts from the source at t = 0+; its magnitude is
=
RO = 100 ohm" Rl = 4000 ohms)
.904/02 IlIIOL=
.9; 1220 TAU= -13.32'0
1"10 19"OkG.2...........·\t..s~.6u66.0L- _ _ _ _ __
,/HO
VAPPX
"'DIH'
0.04/62
0604d20
+1.220%
~...D.22'U-....il~!l9292-.....±Jl..DOO,"'t
The case RL < RO really provides no useful advantage for
voltage mode communications. The negative sign for PL
and the positive sign for Ps lead to dampened oscillatory
behavior, or ringing. The maximum perturbation takes place
at the source end of the line. Waveforms for this case are similar to those shown in Figure 3-12a, and are shown to scale in
Figure 3-12i. With the given values used to produce the figure, the maximum amplitude ringing appears at the source
line end.
uP)
= 2000 ohms,
Table (a). (RS
HHOS=
..Y..li I ) =
TIME
a
O.49J99
O.~00117
.!llaO~.l.d~'_~+U0l...l:0[l00U:'''--
O.':l2801
0.,3B"II
0.:'2,380
0.03877
TQble(b). (RS
HHOS=
VIC 1)=
RO
v---
J.:lMF
0.,
Ro + Rs
I.~
2 '1
3.':l
4.5
? 'j
(>.0
7.:
Upon arrival at the load at time t = 7 , this initial wave generates a positive voltage reflection since P L >0. The voltage
reflection arrives back at the source site at time t = 2 7 . Since
Ps is also positive, another positive voltage reflection is
launched back toward the load. The process repeats, and the
source and load voltages both execute a step-up approach
toward steady state voltage VSS' These waveforms are
shown in Figure 3-12g.
9.0
= 500 ohms,
• "l391JO
.13043:>
_ _ _ _ __
+0.024%
+o.oom,
RO = 75 ohms, Rl = 10 kilohm,)
kHOL=
,SS=
.985 I I 2 TAU= -0.303;6
.952331
_ _ _ _ _ _ __
0.1,3043
0.13971
+7..112%
0.25893
0.25893
+0.000%
a 'i53.~.3606.tL-±..L9.o9"'%_ _ _ _ _ __
0.44''146
0.44/46
+O.OO()%
0.51661
0.;2153
+0.952%
0 58473
0 "SA.t.7,,3_-"+.uO....LJ!00.lt0.l2%'--_ _ _ _ __
O. 03~09
0.63807
+0. ~64%
0.68409
0.68469
+O.OOO~~
1IA.P.."'Pli.Xcc--"%.ujl.l-I",FF~
'/lHT)
~
10.'
_ _ _ _ _ __
+O.ooox.
+0.030%
...;Z2.L:b__'l_.12.J9L-.±O...36J""%~_ _ _ _ __
0.1;14/
0.78416
0.'15147
0.78006
+0.000:<
+0.242%
______________
0.83128
+0. Ion
O. [34904
+0.000%
~_li6320~___'l ... 86420----+-'l--1J]% _ _ _ _ _ __
15.,
0.87/14
0.B7114
+0.000%
16.,
0.8B744
0.88818
+0.083%
I"?
0 d9~L~.9-----D.,89..L~9. _ _t..O.-.Oao:+~ _ _ _ _ __
I~.~
0.90?IO
O.YO:Jo3
+O.O~9~h
19.,
0.91249
0.91249
+0.000%
2!l..!L-ll •.9J_190_ .o~. 9~334----+~Q...Q42"t'--_ _ _ _ __
21.0
0.Y23:J4
0.n:J34
+0.000%
~_~~0~~4~DDOz%
12.,
13.:>
In examining voltage at the line midpoint (x = Q/2), a step-up
type waveform is seen which is the sum of all the incident
voltage waves passing the line midpoint up to the time of
examination. The midpoint voltage is expressed as follows.
0.82990
0.84904
rable (e). BASIC Program U.ting
for t = n + 0.57 with n = O,l,2,3,etc. VSS in Equation 3.41
is the steady state line voltage
Too
l-'HINT'ENfEH IfS,IW,RL'.
110 HIIPJ'C i-?1,tW,!l2
:32 t: ~~ ~ :g=:~g!; ~ ~2L'I:"'~LUg~l---------and T is a time constant given by
T
27
= - .,--...,---
140
vl=~O/(RI+HO)
::2
~~~2~~UV:~;~;~P~'~)------------------
110 l-'1'iltJT'tlIWS=',Pl ;'RHOL=';P2;'TAU=';KI
I hO hi I ,oJ!" ".~_LIt.l.;~V-"S"'5-'"':..;·..,v""9'___ _ __
190 v=>i
200 PHINt"TI.'AE
v.!HT)
VAPPX
%i)lFF'
2.lD..H.l.lL.:L=.D....'>:..lIL2Jl...:LSrEPc.L'_ _ __
220 v2=,Y*( I .-EXP( n+ .Ol/KI»
no "=100.*(,2-/)/,
(3.42)**
In (psPL)
with 7 being one line delay ( 7 = I 0 ).
Equation 3.41 provides an exact solution for odd multiples of
n (n = 1,3,5 .. ,so t = 1.5T , 3.57, 5.57 . . . ), while it
approximates vm(t) for even multiples of n (n = 0,2.4 . . . ,
so t = 0.57 , 2.57, 4.57 . . . ). The closer the Ps PL
product is to 1, the better Equation 3.41 predicts vm(t),
particularly for even multiples of n. To illustrate the fitting,
the two tables in Figure 3-13 are generated by the BASIC
language computer program (Table C) and their data is plotted in Figure 3-14.
2110
\-:i:/\-,.J·'JSi.c:.~~+"2_..__l!__-_ __
2:=,0 Hlfi.1r -If.lift##1f
260 vI
I *P2
=,
-#.#.#fI.##
+###.#.'1#%
URO and RL >RO case provides no definite advantages as voltage mode communication is concerned, This
case, in fact, poses a definite hazard to high speed data communications because the reflections cause, in effect, a slow,
exponential signal transition, Because line delay is a factor,
longer lines will only increase the effect.
= tOOo
Ps
=+0.90472
T
= 13.331
't =+095122
Rl = 4 k 11
Vss = 0.666 Vat
0.90 Vss -
o
10
AO" 75 n
RS~500Q
12
20
Ps::: +073913
T= 6.30t
PL=+098511
-- ---- -
18
16
14
--- -- --- -- --- --- -
-
--VSS=0952381
Vss
2
01 Vss
12
10
14
16
18
20
tiT
t=O
RS
Ls
LM
J
RL
I" TRANSMISSION LINE IRo, 8 ) -I
vMX II) = VSS
Fig. 3-14,
~
- exp [-II +O,5T)IT
1)
-2 T
1=
In I Ps PLI
Approximation of Midline Voltage with RS> RO and RL >RO
10-21
reflection effects of Case 1 but, at the same time, does
require a driver circuit to have its internal current limits
set at greater values than those required to produce the desired signal level into the minimum line resistance used.
Thus, this case requires power buffer gates such as the
9N40 or 9S 140 or specific line driver devices such as the
9612, 96149621 or 8T13123. Ordinary TTL, except for
the above mentioned circuits, has too Iowa current limit
point to adequately drive 50 n lines.
SUMMARY - Which are the Advantageous
Combinations?
In examining the basic combinations of source, line and load
resistances, and typical waveforms characteristic of each
case, advantageous combinations can be determined. The
primary results are tabulated in Figure 3-15. Those combinations generally used in voltage mode communications circuits
are as follows.
1. Unterminated case (RS «RO' RL» RO). This situation
provides low steady state power dissipation and large
signal levels, but also shows pronounced "ringing" effects.
The "ringing" can be reduced by controlling signal rise/fall
time versus T, or by clamping diodes to limit load signal
excursions. This case is representative of TTL circuits and
is thus widely employed.
3. The series terminated or backmatched driver case RS = RO
Rt-»RO provides a low steady state power dissipation
system for use with one receiver located at the load end of
the line. The positive reflection coefficient of the load is
used to approximately double the initial wave arriving at
the load. Setting RS = RO terminates the reflected wave
when it arrives back at the source site after two line delays,
and the line then assumes steady state conditions. The use
of other receivers located along the line is not recommended, because they will not see the full driver signal swing
until the reflection from the load passes their particular
2. The parallel terminated case (RS «RO' RL = RO) provides
large signal levels, and excellent signal fidelity. However,
it is power consuming with most of that power dissipated
in the load resistor. This case is useful for cleaning up the
Configuration
Name (if any)
(Driver)
Source
(Receiver)
Load
Resistance
Resistance
Unterminated
«
RO
»
Parallel
«
RO
~
terminated
RO
Optimum
Signal
Line Receivers
Threshold
Allowed at Other
Than Load End
of Line?
Ringing pronounced
0.5 VSS
Yes
Excellent fidelity
0.5 VSS
Yes
Characteristics
Receiver
Comments
Undershoot may
cause data errors
Load resistor
RO
consumes power
PL
«
RO
~
(VSS)2
-RL
Awful - different
«
RO
signals at each
point on the line
NA
No
Not generally useful
RO
Load signal excellent
0.5 VSS
No
consumption over
parallel termination
Excellent fidelity
0.25 VSS
Yes
on resistors allowed
for same fidelity as
parallel termination
NA
NA
for data"is useful as
pulse generator
0.5 VSS
Yes
Low power com sumption. Increased delay
due to signal 'rise' times
0.5 VSS
Yes
Produces only small
signal voltages compared with other
methods. Uses current
sinking drivers such as
the 75110A, 75112
NA
NA
Not generally useful
Reduced power
Series terminated
or back matched
driver
~
RO
»
Fully matched
~
RO
~
~
RO
< RO
Greater tolerances
»
RO
»
RO
RO
»
RO
~
»
RO
< RO
RO
Load signal like
a one-shot
Exponential like
signal waveforms
Small signal amplitude.
Excellent fidelity
Not generally useful
Very small signal
amplitudes, also
ringing
Fig. 3-15. Summary of Effects
10-22
(shown as solid lines) are the superposition of the waves represented by the dotted lines. With the exception of a slight
rounding of the edges, the actual waveforms for the circuit,
shown in the oscilloscope photograph in Figure 3-17, closely
approximate the waveforms predicted by theory.
bridging points. Such receivers could malfunction, as they
would see a voltage very close to their threshold, and perhaps even place the line receiver in its linear operating
region. This could make the line receiver sensitive to oscillatory, parasitic feedback. If these contraints are acceptable, the series termination method can be used to good
advantage in providing the same signal fidelity and signal
amplitude as with the parallel termination method, while
at the same time, contributing a significant savings in
steady state power consumption.
If the source excitation is adjusted so that its O-to-1 00% rise
time tr is equal to 2 T , each of the Vi + vr and ii + ir waveforms must be modified to include this rise time. The waves
will have the same final value as predicted by the lattice diagram, but they now require two line time delays to reach this
final value. The vl, Vs and is waveforms consist of the
superposition of these linear ramps. Because each wave
reaches its final value just as a new wave arrives, their superposition converts the square edged vl' vs and is waveforms
into triangular waveforms. This is shown in Figure 3-18. The
accompanying oscilloscope photograph shows the close correspondence between the actual and theoretical waveforms
whereas an additional oscilloscope photograph in Figure 3-18
shows the actual waveforms for the case where tr = T. Not
surprisingly, the tr = T case changes the vl' Vs and is
waveforms of the tr «T case into trapezoidal forms because
each arriving wave reaches its final value well before a new
wave arrives.
4. The fully matched case RS = RO' Rl = RO not only provides excellent signal fidelity all along the line, but also
has reduced signal amplitude over that of the parallel terminated case. Additionally, the power consumption is
somewhat less than the parallel termination case and the
power is divided equally by the source and load. The primary advantage of the fully matched system is that termination resistor tolerances can be relaxed somewhat with·
out incurring large amounts of ringing. This is because both
the source and load act as line terminations.
EFFECT OF SOURCE RISE TIME ON WAVEFORMS
Previously, it was assumed that the source-produced signal
rise time was always much less than the line time delay ( T ).
Because the waveforms for the source and load voltage were
the superposition of incident and reflected waves occurring
at their proper times, and because the shape of each wave was
a square edged step function, the resultant source and load
waveforms were thus also square edged, or ideal in nature.
In many practical cases, particularly when line length is short,
the source excitation possesses a finite, and non-negligible,
rise time. Therefore, depending on the ratio of rise time to
line delay, it is possible to have a new wave start arriving at
the point of interest before the previous wave can reach its
final value. The net waveform for voltage or current at that
point, then, would consist of the superposition of two or more
waves during their time of overlap. To study the superposition
effect on Signal waveforms, the source excitation is represented as a simple linear ramp rise to its final value of VO+' so
e(t)
e(t)
and
e(t)
If the source excitation is adjusted such that its rise time
equals three line delays tr = 3 T , the Vi + vr and ii + ir waves
overlap for a period of time equal to T. That is, each wave
reaches only 2/3 of its final value when a new wave starts
arriving. Considering the waveform, the load voltage from
time T to 3 T is
Starting at t
= 3 T, the wave
Vi(3) = vi(l)PSPL e(t -
3 T).
begins arriving from the source, and the load voltage then is
the superposition of these two waves. Because vi(3) is a negative wave ( Ps <0), the algebraic sum of the last third of the
first wave and the first third of the second wave vi(3) arriving
at the load causes the load voltage to reduce in amplitude
from the (t r « T) case. likewise, the source voltage and source
current show reduced amplitudes over the ideal case, due to
the overlap period of the waves arriving at the source.
a for
t < 0
Vo+ . tit r for a ,,; t,,; tr
Vo+fort>t r
where tr represents the O-to-1 00% source rise time. The circuit model and its lattice diagram are shown in Figure 3-16.
The values of RS' RO and Rl were chosen to equal those of an
actual circuit on hand, allowing the theoretical waveforms,
obtained by graphical superposition, to be compared with the
measured response of an actual circuit.
Theoretical and actual waveforms for the tr = 3 T case are
shown in Figure 3-19. Notice that load voltage perturbations
and source current is requirements are reduced from those
of the tr« T case. Similarly, the ratio of tr to T , can be
successively increased. This results in reduced ringing on the
load voltage and reduced source current due to the overlapping of more and more Vi + vr (or ii + ir) waves. Actual
and theoretical waveforms for tr equal to 4 T , 6 T and 8 T
are shown in Figures 3-20, 3-21 and 3-22, respectively. In
each case, as the tr to T ratio is increased, the instantaneous
source and load voltages become more equal. The source
current is also reduced so that the circuit exhibits fewer reflection effects and the transmission line itself can be considered
as a simple interconnection from dc circuit theory.
Figure 3-17 shows the load voltage vl, source voltage Vs
and source current is waveforms versus time for a circuit
with a source rise time very much less than T. The actual
waveforms for vl' vs and is are composed of the superposition of both incident and reflected waves in their proper time
sequence. In the figures, these waves are shown as dotted
lines. Each wave represents the sum of the incident wave
plus its reflection. The resultant vl, Vs and is waveforms
10-23
I
words, if the stub's time delay is made very short when compared to the tr of the signal at the stub line location, the
stub reflections will have a minimal effect on the line signals.
A stub length to generate a tr: T ratio of greater than 8: 1 is
usually considered adequate to negate the stub reflections.
Using the tr: T ratio to reduce reflection effects has many
practical advantages in digital design. The low source and
high input resistance of TTL or ECl circuits allows one gate to
drive many receiving gates. The reflection effects of this unterminated combination, however, can cause data errors or
at least lead to reduced noise immunity due to the pronounced
load voltage undershoot. Since the rise and fall times of
these devices are easily measured, a maximum line length
can be set such that ttie resulting tr to T ratio provides
the desired reduction in ringing. This is the primary basis for
the wiring rules of each logic family and, usually, the tr to T
ratio is chosen somewhere between 3:1 and 4:1. As an example, the rise and fall time for normal TTL (9N/74N series)
is t1 0%-90% = 6 ns. When this is converted to an equivalent
linear 0 to 100% time, tr = 8 ns. A common propagation
delay of 1.7 ns/ft, in combination with the requirement
that tr = 3 T , gives the maximum line length of approximately 18 inches. This corresponds with the published recommendation of the various manufacturers for the 9N/74N
series TTL circuits. A similar computation of the rise and fall
times for other logic families yields their respective line length
recommendations. The faster families require shorter line
lengths for the same tr to T ratio, and slower logic families
allow relatively longer line length. This ratio can also be
used to make stubs or taps on lines "disappear". In other
The third primary application of the tr to T ratio for controlling reflection effects is that used in some standard data
communications interfaces such as EIA-RS232-C. Here, driv··
er slew rate is explicitly controlled. This, along with the implied maximum interconnect cable length serves to produce
a tr: T ratio of 3: 1 or greater. This, in turn, reduces the reflection effects inherent in a voltage source driver, unterminated line system. The main disadvantage of using the tr: T
ratio to control reflection effects is in the overall time for the
signal representing the data to rise above the receiver threshold level. With the parallel terminated method, the minimum
time delay was T or one line delay. When the tr: T ratio
is used, an additional delay time of approximately 0.5 tr is
added to the line delay yielding, therefore, a greater effective signal propagation delay. This increased delay mayor
may not be acceptable in the desired system so the trade-off
between ease of usage of the unterminated case must be
weighed against the increased effective signal delay over
that delay obtainable with the terminated case.
Source
Load
Vi + vr
ii + ill
(rnA)
Vs
(V)
is
(rnA)
t
Vi + vr
in (T)
(V)
1.8500
-10.10
3
-1.5500
0.9599
8.87
5
1.2986
-15.90
1.0458
- 7.03
7
-0.0720
13.32
0.9738
6.29
10
0.0603
-11.17
1.0341
12
-0.0505
9.36
14
0.0424
16
0.0355
i j + ir
(rnA)
vL
(V)
iL
(rnA)
0.40
1.8500
0.40
-0.34
0.3000
0.06
0.28
1.5986
0.35
-1.0881
-0.24
0.5106
0.11
9
0.9116
0.20
1.4222
0.31
- 4.87
11
-0.7638
-0.17
0.6584
0.14
0.9836
4.48
13
0.6399
0.14
1.2983
0.28
- 7.84
1.0259
- 3.36
15
-0.5362
-0.12
0.7622
0.16
6.57
0.9904
3.21
17
0.4492
0.10
1.2114
0.26
in (T)
(V)
0
0.9400
12.53
0.9400
12.53
2
0.1224
-22.64
1.0624
4
-0.1026
18.97
6
0.0859
8
5.4
's
-.
Q
RG58.7/U
75 Q COAX
T:::
Ps
Fig. 3-16.
0
-
--t
'L
vL
4625Q
70 ns
P L =+ 0.96809
086658
Transmission Line Model and Its Lattice Diagram
10-24
>
I
Vi(l)
'2
w
":;'"
0
>
'1
,--
'i
"g
I
13r
'"
:L
'1
5r 17r
'2
>
I
w
'2
:;
+1
"'"
0
>
~ Vs
------------t
cc
::>
0
'"
t
I
vj(3) + v r (3)
~
>
9r Ill! 13r 15t" 17"[
L ___L_-_-...=--...=--...=---=-:-_
_____________ _
DOTTED LINES ARE
vj(n) (1 + PsI WAVES
ARRIVING AT LOADTHEIR SUM IS THE
LOAD VOLTAGE vL(tl
(SOLID LlNEI
21
4T
6T
at
lOt 121: 14t 16t
SOME WAVES
OMITTED FOR
CLARITY
} 0.5 V
-1
>'"
} 10mA
'20
'"I
E
>-
'10
~
cc
cc
0
::>
u
ij
-10
a:
I
IL-
::>
0
'"
-20
L______ _
______
~
DOTTED LINES ARE
ij(n) (1 + PsI WAVES
AT SOURCE. THEIR
SUM IS THE SOURCE
CURRENT INTO THE LINE is (t)
(SOLID LINE)
o
27 47 67
87 107127147167
7
=
70 ns
(RG 59A/u)
__ _
L ______________ _
-'" -30
ij(2)(1 + PsI
Fig. 3-17.
Waveforms for tr = 2«7
>
I
w
"'"
:;
0
>
0
0
-2
>
I
w
~
~
w
u
a:
::>
o
'"
'"I
-1
20
E
10
>-
~
~
0
\
::>
u
w
u -10
\
\
\
a:
::>
0
\
\
-20
'"I
.-'" -30
o
L _______________ _
2t 4 T 6t
8T lOr 12r 14r 16T
Fig. 3-18.
Waveforms for tr = 27
10-25
>
I
- -------- ---
/~-
/
w
'~"
0
>
0
"g
-1
3T'\ 5.
<:
~
'\
7r",9T
l1t'13~
lsr'17t
'''------====="
,'-------------
-2
>
>
I
w
"'~
§i
w
i!
o
o=>
'"I
2T
41"
6t
8t
lOr 12t 14. 16t
SOME WAVES OMITTED
FOR CLARITY
-1
20
r-----------
10
--r~~~~--~-~
_L __
835 ....... /"..-
-1/
//
I
/------
/
..,/'
.,.-
o~f_,,~_f~~~~~f=~~..
61\ 8t 1Oe·12! 14T'16!
2" 4
\
~
-10
\
\
=>
\
o
\
-20
f/)
-'"
\
"
~--
,' - - - -' -------------
\~------------.
-30
Fig. 3-19.
>
I
/
r---------------
/
w
/
'"
~
0
>
....
0
3t',~t
0
<:
g
-1
>'
-2
Waveforms for t, = 3 T
...
---
7t '~: l1T '1~~ 15t
17T .......
'-----
"'- ---~= === ===
...
>
I
w
'"~
0
>
~
oc
+-f''-1~-.,-r-:;,-T-=-::-r.:-~-::,::-c:-:_:-r_=-:::-r.-=_=-:,:-::-~-~
-2.. 4r 6T 8. lOr 12t 14. 16t
,
=>
0
'"I
t
I
SOME WAVES OMIITED
FORC~RITY
-1
>'"
20
,,;----.------_
-r----.=====
__ ..t.. _ _ _
/
/
/
/
/
/
/
///
Fig. 3-20.
Waveforms for tr = 4T
10-26
>
I
w
'~"
0
>
0
......
31: '5~ ......7t
Cl
-1
.......
.......
-....
-- ----
9"t,..!~..... 13T"1~~~~=
-------
..... _--------
-2
>
I
w
'':;
w
U
a:
0
::J
o
0
Vl
I
2"[
4t
61:
lOt" 12r 14T 16t
8"[
-1
>Vl
I
/ //
.----------
__-".., -_-
_----o-<~------_-
w
CJ
~
0
/
Waveforms for tr = 67
/
>
0
"g
-2
"-
o
2r
4r
6t
"-
"-
I
-------
aT 101" 121" 141" 16t
-1
'(G/C), the distortionless line is only of historical
interest, and it is not possible to satisfy the (R/L)=(G/C)
condition over a sufficiently wide bandwidth to allow a proper
transm ission of short duration pulses. Over a lim ited frequency
range such as that encountered in telephony (0-4 kHz), the L
term can be increased by either adding lumped inductances
at fixed intervals along the line or by winding a magnetic
material (as a thin tape) around the conductors of the line
throughout its length. Lumped loading is commonly applied
to long telephone circuits to reduce the signal attenuation
over a narrow frequency range; however this linearity is at
the expense of in-band attenuation and non-linear delay distortion. The distributed loading method has been tried, but
the mechanical characteristics of the magnetic materials
have made the winding process very difficult. In any event,
neither method allows short pulses to retain their wave
shapes. The interest in line loading to produce the Heavyside
condition for pulse transm ission is therefore largely academ ic.
Engineers designing data transmission circuits are not usually
interested in the esoterica of lossy transmission line theory.
Instead, they are concerned with the following question: given
a line length of x feet and a data rate of n bps, does the system
work-and if so-what amount of transition jitter is
expected? To answer this question using analytical methods is
quite difficult because evaluation of the expressions representing the line voltage or current as a function of position and
time is an involved process. The references at the end of this
section provide a starting point to generate and evaluate
analytical expressions for a given cable.
The effects on the LRCG line parameters, the variations in
ZO' a (wI, and propagation velocity as a function of applied
frequency are discussed later in this section. Using an empirical approach to answer the "how far- how fast" question
involves only easily made laboratory measurements on that
selected cable. This empirical approach, using the binary eye
pattern as the primary measurement tool, enables the construction of a graph showing the line length/data rate/signal
quality trade -offs for a particular cable. The terms describing
signal quality are discussed later in this section. The technique of using actual measurements from cables rather than
theoretical predictions is not as subject to error as the
analytical approach. The only difficulties in the empirical
method are the requirements for a high quality, real time (or
random sampling) oscilloscope and, of course, the requisite
amount of transmission line to be tested.
The following sections discuss the origins of the second-order
effects-skin effect, proximity effect, radiation loss effect,
and dielectric loss effect-and their influence on the LRCG
transmission line parameters.
Also discussed in this chapter are commonly used pulse
codes and ways to estimate coaxial cable signal quality in lieu
of eye pattern measurements.
•
10-28
Skin Effect This phenomenon is based on two facts: a
current flow in any real conductor produces an electric
field given by Ohm's Law; the current distribution and/
current density redistribution reduces the effective crosssectional area of the conductor, thereby increasing the perunit-length line resistance. This effect is a function of the
conductor diameters, the separation of the conductors
from each other, and frequency. The analytical evaluation
of the proximity effect is quite complicated and except for
certain limited cases (see Arnold" and Dwight12), no general rule of thumb expressions have been proposed. The
proximity effect is not present in coaxial cables because of
their circular symmetry. The proximity effect is a significant contributor to signal losses particularly in cases of a
twisted pair or parallel wire lines.
or magnetic field distribution in a conductor is frequency
depe.ndent. For dc current in a single isolated conductor,
the current density is uniform across the conductor. When
alternating current is used, the current density is not
uniform across the conductor. Instead, the current tends
to concentrate on the conductor surface. Current density
continuously increases from the conductor center to its
surface, but for practical purposes, the current penetration
depth, d, is assumed as a dividing line for current density.
The current is assumed to flow in a imaginary cylinder of
thickness d with a constant current density throughout
the cylinder thickness. Distribution of current densities
for both actual and assumed models is shown in Figure 4-1.
•
It can be seen that for classical skin effects, the penetration depth is given by
1
d=K-(4.1 )
..JT
v'
where K=l /
71J10 ,f.l = magnetic permeability of the
conducting material expressed in henries per unit length,
and 0 = conductivity of the conducting material. For
MKS(SI) units and for a copper conductor
o
f.l
=
5.85 x 10 7 (n meterr 1
471 x 10- 7 (H/meter)
Both twisted pair and parallel wire lines exhibit radiation
losses and these losses contribute to the effective per-unitlength line resistance. Radiation loss is dependent to a
large extent on the characteristics of the materials close
to the line; so radiation loss is quite difficult to' calculate,
but can be measured if necessary.
in which case, d would be the penetration depth expressed
in meters.
Because the skin effect reduces the equivalent conductor
cross-sectional area, increasing frequencies cause an increase in the effective resistance per unit length of the line.
This in turn leads to signal attenuation increasing with
frequency. If the frequency response of a cable is plotted
on log-log graph paper, log dB, or Nepers vs log frequency,
the curve slope will be 0.5 if the cable losses are primarily governed by classical skin effects. The slope of the
attenuation curve,. along with the attenuation at a particular frequency, can be used to estimate coaxial cable transient response as a function of length},'
•
•
_13
-----113
de
de
ACTUAL
ROUND CON aUCTOR
Dielectric Loss Effect: Dielectric losses result from leakage
currents through the dielectric material. This causes an
increase in the shunt conductance per unit length and
produces signal attenuation. Fortunately, for most dielectric materials in common use, this loss is very small
particularly for frequencies below 250 MHz. For most
practical purposes, then, dielectric losses may be neglected as they are usually overshadowed by skin effect losses.
INFLUENCE OF LOSS EFFECTS ON PRIMARY
LINE PARAMETERS
Resistance Per Unit Length, R. It is composed of a basic dc
resistance term Rdc plus the contributions of skin effect,
proximity effect and radiation loss effect. For coaxial lines,
the proximity and radiation loss effects are negligible in most
Proximity Effect: This is a current density redistribution in
a conductor due to the mutual repulsion (or attraction)
generated by currents flowing in nearby conductors. The
current density at those points on the conductor close to
neighboring conductors varies from the current density
when the conductor is isolated from other conductors. This
DISTRIBUTIONS
Radiation Loss: Radiation losses cause an apparent rise
in resistance per unit length increasing with frequency.
The mechanism of radiation loss is energy dissipation
either as heat or magnetization via eddy currents in nearby
metallic or magnetic masses, with the eddy currents in·
duced by line currents. Coaxial cables do not exhibit this
effect because the signal magnetic field is confined between the shield and the outside of the center conductor.
Ideally, the magnetic field produced by shield current cancels the field produced by current in the center conductor
(for points outside the shield).
~
_----'~==~H~
MODEL
DISTRIBUTIONS
lMHz
1 MHz
----'I~
100 MHz
CURRENT
DENSITY
ALONG
CROSS
SECTION
Fig. 4-1.
Current Distributions Across and Conductor for Several Frequencies
10-29
I
cases, so the primary contribution is made by the skin effect.
Thus the resistance per unit length becomes
20
(4.2)
"'-
L
where O
~ 400
,/'
z
~
>
z
~I--'
" a1
-
V
o
~
~
~
V
II
300
I
200
~
100
.001
"
10k
Fig. 4-4.
1M
100k
FREQUENCY -
10M
1k
10k
Fig. 4-5.
Attenuation vs Frequency
10-31
1M
100 k
FREQUENCY -
Hz
10M
Hz
Propagation Velocity vs Frequency
lions on the binary bit stream recovered by the line receiver.
For example, the sink decoder may extract the clock rate from
the data or perhaps detect and correct errors in the data. From
the optional sink decoder, the recovered binary data passes to
the information sink-the destination for the information
source data.
ing task is to ensure that a particular bit arriving at its destination is interpreted in the proper context. To achieve this,
both the sender and receiver of the data must accomplish the
five following requirements.
1.
Agree upon the nominal rate of transmission; or how
many bits are to be emitted per second by the sender.
2.
Agree upon a specified information code providing a oneto-one mapping ratio of information-to-bit pattern and
vice versa.
3.
Establish a particular scheme whereby each bit can be
properly positioned within a byte by the receiver of the
data (assuming that bit-serial transmission is used).
4.
Define the protocol (handshaking) sequences necessary
to ensure an orderly flow of information.
5.
Agree to the electrical states representing the logic values of each bit and the particular pulse code to be used.
Assume for the moment that the source encoder and sink decoder are "transparent"; that is, they will not modify the
binary data presented to them in any way. Line driver signals, then, have the same tim ing as the original bit stream.
The data source emits a new bit every tB seconds. The pulse
code produced by the source encoder and line driver is called
Non-Return to Zero (NRZ), a very common signal in TTL logic
systems. A sample bit pattern with its NRZ representation is
shown in Figure 4-7a. The arrows at the top represent the
ideal instants, or the times the signal can change state. The
term unit interval is used to express the time duration of the
shortest signaling element. The shortest signaling element
for NRZ data is one bit time IB' so the unit interval for NRZ
data is also tB. The rate at which the signal changes is the
modulation rate (or signaling speed), and baud is the unit of
modulation rate. A modulation rate of one baud corresponds
to the transmission of one unit interval per second. Thus the
modulation rate, in baud, is just the reciprocal of the time for
one unit interval. A unit interval of 20 ms, therefore, means
the signaling speed is 50 baud. The reason for differentiating
between the information rate in bits per second (bps) and the
modulation rate in baud will be clarified after examining
some of the other pulse codes later in this chapter.
These are by no means all of the points that must be agreed
upon by sender and receiver-but these are probably the most
important. Items 2, 3 and 4 are more or less "software" type
decisions, because the actual signal flow along the transm ission line is usually independent of these decisions. Because
items 1 and 5 are much more dependent on the characteristics of line drivers, line receivers, and transmission lines, they
are the primary concern here.
Figure 4-6 represents the components of a typical data transmission system. The information source can be a computer
terminal or a digitized transducer outout, or any device emitting a stream of bits at the rate of one bit every tB seconds.
This establishes the information rate of the system at 1/tB
bits per second. The information source in the figure feeds a
source encoder which performs logic operations not only on
the data, but also on the associated clock and, perhaps, the
past data bits. Thus, the source encoder produces a binary
data stream controlling the line driver. The line driver interfaces the source internal logic levels (TTL, MOS, etc.) with
transmission line current/voltage requirements. The transmission line conveys signals produced by the line driver to the
line receiver. The line receiver makes a decision on the signal
logic state by comparing the received signal to a decision
threshold level, and the sink decoder performs logic opera-
Fig. 4-6.
NRZ data should always be accompanied by a clock signal,
Figure 4-7b, which tells the receiver when to sample the data
signal and thus determine the current logic state. For the example in Figure 4-7b, the falling edge of the clock corresponds to the middle of the data bits, so it could be used to
transfer the line receiver data output into a binary latch. The
falling edge of the clock is thus the sampling instant for the
data. The line receiver does have a decision threshold or
slicing point so that voltages above that threshold level produce one logic state output, while voltages below the threshold produce the other logic state at the receiver output. The
receiver may incorporate positive feedback to produce hysteresis in its transfer function. This reduces the possibility of
oscillation in response to slow rise or fall time signals applied
to the receiver inputs.
Data Transmission System
10-32
val. A 25% isochronous distortion means that the peak-topeak time jitter of the transition is .25 unit interval (max).
Previously in this chapter, it was stated that the fast rise and
fall times of signals, corresponding to the transitions between
data bits, are rounded out and slowed down by a real transmission line. Each transition of the signal applied to the line
by the line driver is transformed to a rounded out transition
by the dispersion and attenuation of the transmission line.
The resultant signal at the load end of the line consists of the
superposition of these transformed transitions. The waves
arriving at the load end of the line are shown in Figure 4-7c
and their superposition is shown in Figure 4-7d. It is assumed
that the line is terminated in its characteristic resistance so
that reflections are not present. The receiver threshold level
is shown here, superimposed on the resultant load signal, and
the re-converted data output of the line receiver is shown in
Figure 4-7e along with the ideal instants for the data transitions (tick marks).
Another type of received-signal time distortion can occur if
the decision threshold point is misplaced from its optimum
value. If the receiver threshold is shifted up toward the One
signal level, then the time duration of the One bits shortens
with respect to the duration of the Zero bits, and vice versa.
This is called bias distortion in telegraphy and can be due to
receiver threshold offset (bias) and/or asymmetrical output
levels of the driver. This effects is shown in Figure 4-8.
Bias distortion and characteristic distortion (intersymbol
interference) together are called systemic distortion, because
their magnitudes are determined by characteristics within the
data transmission system. Another variety of time distortion
is called fortuitous distortion and is due to factors outside the
data transmission system such as noise and crosstalk, which
may occur randomly with respect to the signal timing.
Comparing the original data (Figure 4-7a) to the recovered
data (Figure 4-7e) shows that the actual recovered data transitions may be displaced from their ideal instants (tic marks
on Figure 4-7e). This time displacement of the transitions
is due to a new wave arriving at the receiver site before the
previous wave has reached its final value. Since the wave
representing a previous data bit is interfering with the wave
representing the present data bit, this phenomenon is called
intersymbol interference (in telegraphy it is called characteristic distortion). The intersymbol interference can be red'uced
to zero by making the unit interval of the data signal quite
long in comparison to the rise/fall time of the signal at the
receiver site. This can be accomplished by either reducing
the modulation rate for a given line length, or by reducing
the line length for a given modulation rate.
SIGNAL QUALITY MEASUREMENT-THE EYE PATIERN
To examine the relative effects of intersymbol interference on random NRZ data and a "dotting"* pattern, see
Figure 4-9. The top two waveforms represent the NRZ data
and dotting pattern as outputs into two identical long transmission lines. The middle two traces illustrate the resultant
signals at the line outputs and the bottom two traces show
the data output of the line receivers. The respective thresholds are shown as dotted lines on the middle two traces. The
arrows indicate the ideal instants for both data and dotting
signals.
Notice that the dotting signal (0) is symmetrical, i.e.. every
One is preceded by a Zero and vice versa, while the NRZ data
is random. The resultant dotting signal out of the line is also
symmetrical. Because, in this case, the dotting half-cycle
time is less than the rise/fall time of the line, the resultant
signal out of the line (E) is a partial response-it never reach-
Signal quality is concerned with the variance between the
ideal instants of the original data signal and the actual transition times for the recovered data signal.
For synchronous signaling, such as NRZ data, the isochronous
distortion of the recovered data is the ratio of the unit interval to the maximum measured difference irrespective of sign
between the actual and theoretical significant instants. The
isochronous distortion is, then, the peak-to-peak time jitter
of the data signal expressed as a percentage of the unit inter-
*The term dotting pattern is from telegraphy and means an alternating sequence of 1·bits and a·bits (the "dot dot dot" etc.). Note that an NRZ dotting
pattern generates a signal which has a 50% duty cycle and a frequency of
112 tB (Hz).
-I '. fa ~
~ a ~
1
1
~
1
+1
~ a ~
1
•
1
t~
+1
""'00"""
a) NRZ DATA
t
b) CLOCK
S.mp'm, 00"",
c) WAVEFRONTS
DUE TO EACH
DATA TRANSITION
d) RESULTANT
LOAD SIGNAL
~.. '.-~~-
-
•
-
..
-
*
-
~
'"
-
e) LINE RECEIVER
DATA OUTPUT
Fig. 4-7.
NRZ Signaling
10-33
3750ft 1M bd
.....
,,~"""'"
~
TP-PVC 24 AWG
-
II
I
IDEAL INSTANTS
+
o
o
+
NRZ DATA
....-- POSITIVE BIAS
SIGNAL OUT OF
LINE - INPUT TO
LINE RECEIVER
. . . - OPTIMUM THRESHOLD
________ NEGATIVE BIAS
SLICING AT
OPTIMUM THRESH
RECEIVER
DATA
OUTPUT
SLICING WITH
POSITIVE BIAS
SLICING WITH
NEGATIVE BIAS
Fig. 4-8.
NRZ
DATA
Bias Distortion
DODING
PADERN
TRANSMISSION LINE
LENGTH ( I )
LENGTH ( I )
~Ot'*O~'t'+'tO+'.'
Fig. 4-9.
TRANSMISSION LINE
.'*
.Ot'tO.'tOt'tO~'tOt't
Comparison of NRZ Random Data and "Dotting" Signals
es its final level before changing. The dotting signal, due to
its symmetry, does not show intersymbol interference in the
same way that a random NRZ signal does. The intersymbol
interference in the dotting signal shows up as a uniform displacement of the transitions as shown in Figure 4-9f. The
NRZ data shows intersymbol interference, in its worst light,
due to its unpredictable bit sequence. Thus, whenever feasibility of a data transm iss ion system is to be tested, a random
data sequence should be used. This is because a symmetri-
cal dotting pattern or clock signal cannot always show the
ef·fects of possible intersymbol interference.
A very effective method of measuring time distortion through
a data transmission system is based on the eye pattern. The
eye pattern, displayed on an oscilloscope, is simply the
superposition-over one unit interval-of all the Zero-to-One
and One-to-Zero transitions, each preceded and followed by
various combinations of One and Zero, and also constant One
10-34
and Zero levels. The name eye pattern comes from the resemblance of the open pattern center to an eye. The diagramatic
construction of an eye pattern is shown in Figure 4-10. The
data sequence can be generated by a pseudo-random sequence generator (PRSG), which is a digital shift register
with feedback connected to produce a maximum length sequence. The PRSG, requiring only two devices (Figure 4-11),
generates a sequence that repeats after 22°_1 bits. Feedback
connections for PRSG shift registers from 4 to 20 bits in length
are shown in Figure 4-12.
Severa I featu res of the eye pattern make it a usefu I tool for
measuring data signal quality. Figure 4-13 shows a typical
binary eye pattern for NRZ data. The spread of traces crossing the receiver threshold level (dotted line) is a direct measure of the peak-to-peak tmnsition jitter---isochronolls distilr-
INPUT
TO LINE
CONSTANT
'ONE' BITS
VOH
CONSTANT
'ZERO' BITS
VOL
0
o
ISOLATED
0_1
TRANSITION
ISOLATED
1_0
TRANSITION
ISOLATED
o
OUTPUT SIGNAL
FROM LINE
1 0
r-
~~
"L-
~
\
Jl
~
f'-
x=r
1------1
~
)<'""'" )C"
1--1
ISOLATED
1 0 1
SUPERIMPOSING
ALL THE ABOVE
SIGNALS
1 UNIT
INTERVAL
1 UNIT
INTERVAL
Fig. 4-10.
BINARY EYE
PATTERNS
Formation of an Eye Pattern by Superposition
•
'H
1--29614 LINE DRIVER
08
TEST POINTS
O~~~~T ~::NEUNDtERTEST~
TO OSCillOSCOPE
HORIZONTAL
TRIGGER
INPUT
o-A"
')
t--'-~--!--I-
t
070-
Vee
NOTE FREQUENCY OF CLOCK
GENERATOR IS ALSO THE NRZ
t
t
+50 v
LINE LENGTH
• I
DATA BIT RATE IN BITS PER
SECOND
USE DIFFERENTIAL PROBE ACROSS
TEST POINTS AND WIDE BANDWIDTH
DIFFERENTIAL INPUT OSCILLOSCOPE
TO DISPLAY EYE PATIERN
Vee
22k
INITIALIZE
--1
FEEDBACK LOGIC EOUATION
DATA INPUT -
l
Qne
020
7
017-020 + 017e020
TO
STAGE 1
SEQUENCE LENGTH'" 220 -1
Fig. 4-11.
= 1048575 BITS
Bench Set-up to Measure Data Signal Quality
10-35
2500 pc POT
FOR TERMINATION
Zeros, and any overshoot or undershoot is easily discernible.
The termination resistor is adjusted so that the eye pattern
transitions exhibit the minimum perturbations (Figure4-14b).
The resistor is then removed from the transmission line, and
its measured value is the characteristic resistance of the line.
tion in a synchronous system-of the data signal. The rise and
fall time of the signal can be conveniently measured by using
the built-in 0% and 100% references produced by long strings
of Zeros and Ones. The height of the trace above or below the
receiver threshold level at the sampling instant is the noise
margin of the system. If no clear transition-free space in the
eye pattern exists, the eye is closed. This indicates that errorfree data transm iss ion is not possible at that data rate and
line length with that particular transmission line without resorting to equalizing techniques. In some extreme cases,
error-free data recovery may not be possible even when using
equalizing techniques.
By using the eye pattern to measure signal quality at the load
end of a given line, a grapl'\ can be constructed showing the
tradeoffs in signal quality-peak-to-peak jitter-as a function
of line length and modulation rate for a specific pulse code.
An example graph for NRZ data is shown in Figure 4-15. The
graph was constructed using eye pattern measurements on a
24 AWG twisted pair line (PVC insulation) driven by a differential voltage source driver (9614) with the line parallelterminated in its characteristic resistance (96 ,0.). The oscilloscope photographs in Figure 4-16 show the typical eye patterns for NRZ data with various amounts of isochronous
distortion. The straight lines represent a "best fit" to the
actual measurement points. Since the twisted pair line used
was not specifically constructed for pulse service, the graph
The eye pattern can also be used to find the characteristic
fesistance of a transmission line. The 2500.: printed circuittype potentiometer termination resistor (Figure 4-11) can be
adjusted to yield the minimum overshoot and undershoot of
the data signal. Figure 4-14 shows the NRZ data eye patterns
for RT>RO' RT = RO and RT Raj
OPTIMUM RECEIVER
THRESHOLD LEVEL
FOR MINIMUM
b. TERMINATED CASE (RT = Raj
JITTER
LOGIC ZERO LEVEL ----.
(0% REFERENCE)
!~~~~!!:~"~!!!!
tt!s
c. OVERTERMINATION (RTl.. '1t-<:."
."-"-. . . . .
~
III . . ,..
RECOMMENDED
OPERATING
REGION
E--
60 40
1
: : ;·tJ~:-----'
: : : NRi-data prob~bly
- "se "me of .,gnal a' ,~a, dos:an,el~+
rCable resistance
causes signal
200
I' I
r· (approximates 2 times the 10-900/0
4000ft
10 600 400
I
Id
100ft
~ '",'- 2 ,,>[(..'1. ",-, ~f'..I",
I
.'.~
4 "
,,~.
30 ft b-24 AWG twisted pair, PVC insulation
E-Zo
=96,
. I
td ~ 1.7 ns/ft
Data from cables of 150 ft to 3750 ft
10 ft
10k
20
40 60 lOOk
200
....
400 600
1M
1
I
I I I
,",I""
MODULATION RATE -
'. ~"
6
10M
20
II
40 60
100M
BAUD
Fig. 4-15. Signal Quality as a Function of Line Length and Modulation Rate for Terminated 24 AWG Twisted Pair (PVC Insulation)
• • • • •,'~I.jJ\I• • ~N~ERSYMBOL
"."if~'• • 10%J1TIER
• • • • • • • • • •150"IoJITIER
INTERFERENCE
lUi = 4 Ir
.1111•••••••
111
NO
INTER SYMBOL
INTERFERENCE
lUI =
2
111l1lil1li•••••••120% JITIER
• • • • • • • • • •1100% JlTIER
Ir
11
' ••••~I••••1 5% JITIER
• • • • •w• • • • • •
30% JITIER
EYE IS CLOSED
ERROR FREE RECOVERY
OF NRZ DATA
PROBABLY NOT POSSIBLE
t
ONE BIT TIME
(ONE UNIT INTERVAL)
Fig. 4-16.
Eye Patterns for NRZ Data Corresponding
to Various Peak·to·Peak Transition Jitter
probably represents a reasonably good worst·case condition
insofar as signal quality vs line length is concerned. Twisted
pair lines with polyethylene or Teflon® insulation have shown
better performance at a given length than the polyvinyl chloride insulation. Likewise. larger conductors (20 AWG, 22
AWG) also provide better performance at a given length.
Thus. the graph in Figure 4·15 can be used to estimate feasi·
bility of a data transmission system when the actual cable to
be used is unavailable for measurement purposes. The
arbitrary cutoff of 4000 feet on the graph was due to an observed signal amplitude loss of 6 dBV (112 voltage) of the
24 AWG line at that distance. The cutoff of 10 Mbaud is
based on the propagation delays of the typical TIL line drivers
and receivers. Field experience has shown that twisted pair
transmission systems using TIL drivers and receivers have
operated essentially error-free when the line length and modulation rate are kept to within the shaded recommended
operating region shown in Figure 4-15. This has not preclud·
ed operation outisde this region for some systems. but these
systems must be carefully designed with particular attention
paid to defining the required characteristics of the line. the
driver. and the receiver devices. The use of coaxial cable
instead of twisted pair lines almost always yields better per·
formance. i.e., greater modulation rate at a given line length
10·37
ESTIMATION OF SIGNAL QUALITY IN
LIEU OF EYE PATTERN MEASUREMENTS
and signal quality. This is because most coaxial cable has a
wider bandwidth and reduced attenuation at a given length
than twisted pair line (one notable exception is RG 174/U
cable). In the next section, a method is discussed that allows
a rough estimation of the maximum "safe" modulation rate
for a given length of a particular coaxial cable when actual
eye pattern measurements cannot be made on that cable.
In many design situations it is not always convenient to measure signal quality using the eye pattern. This can be caused
by lack of equipment, time, or unavailability of the transmission line to perform the necessary measurements. In such
cases, the following rule of thumb applies: the unit interval
should be greater than twice the 10 to 90% rise or fall time
of the line, i.e.,
It should be remembered that, in some ways, the eye pattern
gives the minimum peak-to-peak transition jitter for a given
line length, type, pulse code, and modulation rate. This is
because the eye pattern transition spread is the result of intersymbol interference and reflection effects (if present) and
this minimum jitter is only obtainable if the following conditions are met.
•
The One and Zero signal levels produced by the line driver
are symmetrical, and the line receiver's decision threshold
(for NRZ signaling) is set to coincide with the mean of those
two levels.
•
The line is perfectly terminated in its characteristic resistance to prevent reflections from altering the signal threshold crossings.
•
The time delays through driver and receiver devices for
both logic states is symmetrical and there is no relative
skew in the delays (difference between L --+ Hand H --+ L
propagation delays =0). This is especially important when
the device propagation delays become significant fractions
of the unit interval for the applicable modulation rate.
tui ~ 2t 10 _90 %
Eye patterns that meet this criterion show that adherence to
this rule will keep the peak-to-peak jitter to less than 5% of
the unit interval. If the 10% to 90% rise time cannot be easily
measured-as is the case with coaxial cables whosedom inant
loss mechanism is simple skin effect-then the 10 to 80%
rise time may be used instead of the 10 to 90% rise time.
The corresponding peak-to-peak jitter, due to intersymbol
interference with the tui ~2 tlO-80% rule, is usually less
than 10%. In any event, if the unit interval is less than the 0
to 50% rise time of the signal at the line end (tui
to-50%),
then the error-free recovery of NRZ data is not possible without using equalizing techniques. Sometimes, changing to a
pulse code which allows partial response recovery will enable
data transmission at an otherwise unusable line length-speed
combination. When actual eye pattern measurements cannot
be made, an estimate of feasibility can still be obtained by calculating the signal transition time.
<
N.S. Nahman 2 ,4 presented a simple method to predict the
transient response of a coaxial cable from the cable attenuation. The procedure was based on a graphical analysis technique allowing prediction of the step response of a network
from a graph of the imaginary part of the transfer function,
in this case the imaginary part of 'Y (s). The normalized step
responses (Figure 4-18) are plotted with the abscissa in normalized time (x)
If anyone of these conditions is not satisfied, the signal quality is reduced (more distortion). The effects of receiver bias
or threshold ambiguity and driver offset can be determined
by location of the decision threshold(s) on the oscillograph of
the eye pattern for that driver/cable modulation rate combination. For eye patterns displaying more than 20% isochronous distortion, the slope of the signal in the transition
region is relatively small. Therefore, a small amount of bias
results in a large increase in net isochronous distortion. See
Figure 4-17 for a graphic illustration of this effect. In the
interest of conservative design practices, systems should always be designed with less than 5% transition spread in the
eye pattern. This allows the detrimental effects due to bias to
be minimized, thus simplifying construction of line drivers
and receivers.
x
a
and
1
21fta
t = real time,
I
ISOCHRONOUS DISTORTION (10) =
~ x
100%
'"'
105011
BIAS
Fig. 4-17.
t/a
(4.5)
where
10% POSITIVE
BIAS
NO
~
210011
0%
5% ID
20"10 ID
10%
12% 10
36% 10
Receiver Bias Effect on Total Isochronous Distortion
10-38
(4.6)
0.9
1.0
0.8
m=o.8 m
0.9
m-
0.7
0.8
0.6
.
g
0.5
0.4
0.3
~
0.8
.
g
-s. ~ ~
P\
~ E/V 17 L
m,j,/V V V 1/
~V V V V
o
0.1
0
'I; V
0.6
~
0.5
V
m=~
~
m
=0.5
-
m:: 0.4
r--
I-V l-
m = 0.7
m=O.6
0.4
m:: 0.5
0.2
'( ~ V V
0.7
l4 ~
m - 0.9
m
=p
Dot VVt-::::r-
\
0.1
0.3
/'
0.2
0.3
0.4
0.5
0.6
OJ
0.8
0.2
o. 1
o
0.9
1.0
o
9
10
'1
12
x == t/a
x:: t/a
Fig. 4-18.
Normalized Step Responses for
fm Law Coaxial Cables (After Nahman 2 )
It (f 0) ~ attenuation of the coaxial cable in nepers at frequency (fiji) for length I. If CY (fO) is known in dB, then
division by 8.686 will convert the dB/length into nepers/
length (1 neper = 8.686 dB).
factoring out the cable length to produce
1
1
a
m ~ slope of the attenuation vs frequency curve for the par·
ticular coaxial cable when plotted on log-log graph paper
(log dB vs log frequency).
=
~
] []1
-m
cos (m1f/2)
(4.7)
m
•
I
where CY, (fO) is now the attenuation (in nepers per unit
length and is the line length. The time for the line signal to
rise to 50% is obtained by combining Equations 4.5 and 4.7
(Equations 5 and 7 in Reference 4).
log
where f2
f1 and a (f2) is the attenuation at frequency
(12), and log is the common (base 10) logarithm.
where X50% is obtained from Figure 4-18 or the table in Figure 4-19. Likewise, combining the expressions for x, 0% and
X80% and subtracting gives
Slope m will have a range of O3) can encode more than one bit of information
per receiver decision', but these schemes are seldom applied
to baseband Signaling due to the complexities of the driver
and receiver circuits (especially for M>3). M-ary schemes,
however, are applied to high speed non-baseband data transmission systems using modems. The price to be paid for the
increased bit-packing with multi-level signaling is decreased
immunity to noise relative to a binary system. This is because
a smaller relative threshold displacement (or amount of noise)
is required to produce a signal representing another logic
state in the M-ary schemes.
and
t 1O-80 % = 7.29 • flO;;] .51
344.2 ns
If the desired modulation rate is 1 Mbaud (tui = 1.0 fJs) and
the line length is 1000 feet, then the system using RG59/U
cable would probably operate satisfactorily. Be aware, however, that if the single slope (m) does not accurately approximate the actual attenuation characteristic of the coaxial
cable, then Nahman's method will show considerable error in
predicting the signal transition time. RG174/U is a coaxial
cable with an attenuation characteristic that has a slope in
the 0.3 to 0.65 range depending on the frequency. Thus the
method cannot be accurately applied to RG174/U cable.
In general, the binary class of pulse codes can be grouped
into four categories;
Also, Nahman's method cannot be applied to commonly available twisted pair or parallel wire lines. This is because knowledge of either the I ine attenuation or its phase characteristics
is not normally sufficient to completely specify the transfer
function. Thus, the previously mentioned Bode condition is
not satisified, and the analysis previously used cannot be applied satisfactorily.
•
Non-Return to Zero (NRZ)
•
Return to Zero (RZ)
*Jt can be shown that, for M levels, the information per receiver decision will
be S:::; 1092 M bits/decision. Thus, three levels theroetically yield 1.58 bits;
four levels yield 2 bits of informatio~ eight levels vield bits. etc.
a
10-40
•
Phase Encoded (PE) (sometimes called Split Phase)
•
Multi-Level Binary (MLB). (The MLB scheme uses three
levels to convey the binary data, but each decision by the
line receiver yields only one bit of information.)
state, and the other signal level corresponding to the opposite
logic state. In NRZ-M or NRZ-S signaling, however, a change
in signal level at the start of a bit interval corresponds to one
logic state and no change in signal level at the start of a bit
interval corresponds to the opposite logic state. For NRZ-M
pulse codes, a change in signal level at the start of the bit
interval indicates a logic One (Mark), while no change in signal level indicates a logic Zero (Space). NRZ-S is a logical
complement to NRZ-M. A change in signal level means a logic
Zero and no change means logic One. With NRZ-M and NRZ-S
pulse codes, therefore, there is no direct correspondence
between signal levels and logic states as there is with NRZ-L
signaling. Any of the NRZ pulse codes may, of course, be
used in unipolar or polar form. The NRZ codes are shown in
Figure 4-20, along with their generation algorithms*, signal
levels vs time, and their general power density spectrum.
A secondary differentiation among the pulse codes is concerned with the algebraic signs of the signal levels. If the
signal levels have the same algebraic sign for their voltages
(or currents) and differ only in their magnitudes, the signaling is called unipolar. A very common example of unipolar
signaling is TIL or ECL logic. TIL uses two positive voltages
to represent its logic states, while ECL uses two negative
voltages for its logic states. The complement of unipolar
signaling is polar signaling. Here, one logic state is represented by a signal voltage or current having a positive sign
and the other logic state is represented by a signal with a
negative sign. For binary signals, the magnitude of both signals should be equal, ideally. Their only difference should be
in the algebraic signs. This allows the receiver to use ground
as its decision threshold reference.
The degradation in signal quality caused by intersymbol interference for NRZ-L signaling was discussed earlier. Since
the minimum signaling element (unit interval) for all three
NRZ pulse codes is equal to tB' the previous signal quality
discussion for NRZ-L also applies equally to NRZ-M and
NRZ-S pulse codes. The following is a capsule summary ofthe
previous discussion on NRZ signal quality.
Non-Return to Zero (NRZ) Pulse Codes
There are three NRZ pulse codes: NRZ - Level (NRZ-L), NRZMark (NRZ-M), and NRZ - Space (NRZ-S). NRZ-L is the same
pulse code as previously discussed. In NRZ-L signaling, data
is represented by a constant signal level during the bit time
interval. with one signal level corresponding to one logic
*The generation algorithm showing the sequence of signal levels on the line,
represented by the set {b n} is determined by the sequence of input logic
state~, represented by the set {an}' See Bennet 14 for detailed usage of this
notation.
UNIPOLAR
NRZ-L
PO~R
0
--------------+-------~----_+--------------+_----~------
NRZ-L
-
UNIPOLAR
NRZ-M
0 --------"
GENERAL POWER SPECTRUM
FOR NRZ CODES
UNIPOLAR
NRZ-S
LINE SIGNAL SEQUENCE (bn )
DATA TO
BE SENT
"
UNIPOLAR
NRZ-l
POLAR
NRZ-L
UNIPOLAR
UNIPOLAR
NRZ-S
NRZ-M
OR
OR
OR
OR
1-'8-1
1-'8-1
1-'8---1
'"
'8
'8
'8
a n =l
bn = +
bn = +
b n = (-) b n-l
an = 0
bn = 0
b n :=
-
Fig. 4-20.
'8
b n = b n _l
b n = (-) b n-l
Non-Return to Zero (NRZ) Pulse Codes
10-41
II
•
When ts is less than the 0-50% rise or fall time of the signal at the line end, the open space in the eye pattern closes,
thereby indicating error-free data transmission is unlikely.
•
When ts is less than the 10-90% rise or fall time of the
line end signal, some intersymbol interference is present
and thus, some time jitter in the transitions of the recovered data will be present.
(PPM) uses a pulse of ts/4 duration beginning at the start of
the bit interval to indicate a logic Zero, and a ts/4 pulse beginning at the middle of the bit interval to indicate a logic
One. Pulse Duration Modulation (PDM) uses a ts/3 duration
pulse for a logic Zero and a (2/3) ts pulse for a logic One, with
the rising edge of both pulses coinciding with the start of the
bit interval. PDM with tS/4 pulse widths is also used but better results are usually obtained with the ts/3, 2 ts/3 scheme.
NRZ codes are simple to generate and decode because no
precoding or special treatment is required. This simplicity
makes them probably the most widely used pulse codes, with
NRZ-L the leader by far. NRZ-M has been widely used in
digital magnetic recording where it is usually called NRZI
for Non-Return to Zero, Invert-on-Ones. In terms of the four
desirable features for a pulse code listed at the start of this
section, however, none of the NRZ codes are all that greatNRZ codes do possess a strong dc component, and have
neither intrinsic clocking, nor error detection features. Even
so, their power frequency spectra are used as references for
comparison with other pulse codes.
The reason for differentiating between information rate and
modulation rate can now be further clarified. Each of the RZ
pulse codes in Figure 4-21 has the same information rate;
ie., lIts bits per second. Their respective minimum signaling elements (unit intervals) however, are all less than ts
so the modulation rate for the RZ pulse code is greater than
the information rate. Remember that with NRZ signaling,
the unit interval and the bit time interval are equal in duration, so the information rate in bps is equal to the modulation rate in bauds. For isochronous NRZ signaling, the
measures bps and baud are both synonymous and interchangeable.
Return to Zero (RZ) Pulse Codes
The RZ group of pulse codes are usually simple combinations
of NRZL data and its associated single or double frequency
clock. Sy combining the clock with data, all RZ codes possess
some intrinsic synchronization feature. Three representative
RZ pulse codes are shown in Figure 4-21. Unipolar RZ is
formed by performing a logic AND between the NRZ-L data
and its clock. Thus a logic Zero is represented by the absence
of a pulse during the bit time interval, and a logic One is represented by a pulse as shown. Pulse Position Modulation
Inspection of unipolar RZ signaling reveals that the unit interval is 1/2 bit interval (tui = tS/2). When this unit interval
is less than the 0-50% rise or fall time of the line, the data is
likely to be unrecoverable. With a fixed modulation rate, the
price paid to include clocking information into unipolar RZ is
reduced information rate over that for NRZ signaling. Likewise, for PPM with its unit interval of tS/4, the information
rate reduces to 114 that of NRZ data under the same conditions. This is because the maximum modulation rate is determined by the 50% rise time of the line which is constant
UNIPOLAR
RZ
UNIPOLAR
PPM
UNIPOLAR
POM
LINE SIGNAL SEOUENCE (b n)
DATA TO
BE SENT
UNIPOLAR
PULSE POSITION
MODULATION
UNIPOLAR
RETURN TO ZERO
"
UNIPOLAR
PULSE POSITION
MODULATION
0 _ __
GENERAL POWER SPECTRUM FOR RZ CODES
t8 /2
bn
=
bn
= (0) {
t8/3
t8/4
< tB/21 b n
t8/2 ,,;; t < ts
bn
(+J{O';;;
t
= (+J {t8/2":;; t ' ;
< t8/2
= (0)( 0,;;; t
3tS/4
bn
=
(+J
3tB/41
, bn
=
t
< 2tS/3
{OJ {2t8/3";;: t
< t8
< t < t8
{o.,.;; t';;; t8/4
b n = (0) {t8/4
b n "'- (+J{ 0,;;;
< t < ts
I
b,o(+1{0""B/3
bn
=
(O){ t8/3';; t8
Figure 4·21. Return to Zero (RZ) Pulse Codes.
10-42
for a given length and type of line. PDM has a unit interval of
t8/3 so, for a given maximum modulation rate, the resulting
information rate is 113 that of NRZ data.
change indicates a logic Zero. For Bi 4> -5, no signal level
change in the middle of the bit interval means a logic One,
while a change means a logic Zero.
The preceding argument should not be taken as strictly correct-since the actual intersymbol interference patterns for
the three RZ codes discussed differ somewhat from the pattern with NRZ codes. A random sequence of NRZ data can
easily consist of a long sequence of Zeros followed by a single
One and then a long sequence of Zeros, so the t50% limit can
be accurately applied. Unipolar RZ, in response to the same
long data sequence, produces a t8/2 pulse, so the t50%
argument can be applied here too. With PPM and PDM, the
maximum time that the line signal can be in one state is quite
reduced from the NRZ case. For PPM, this time is 1.25 tB
(010 data sequence) while for PDM, it is .67 tB (see Figure
4-21). With PPM and PDM, then, the line signal may never
reach the final signal levels that it does with NRZ data. So,
the PPM and PDM signals have a head start, so to speak, in
reaching the threshold crossing of the receiver. Because of
the reduced time that PDM and PPM signal levels are allowed
to remain at one signal level, their signaling may still operate
at a modulation rate Slightly above that where the NRZ data
shows 100% transition jitter. Even with this slight correction
to the previous discussion, the RZ group of pulse codes still
sacrifice information rate in return for synchronization. The
PPM scheme appears to be a poor trade in this respect, since
PDM allows a greater information rate while retaining the
self-clocking feature. Unipolar RZ, because it provides no
clocking for a logic Zero signal, is not generally as useful as
PDM for baseband data transmission. However, unipolar RZ
is used in older digital magnetic tape recorders.
In Bi ¢ -L (also called Manchester Code), a positive-going
transition at the middle of the bit interval means a logic Zero,
while a negative-going transition there indicates a logic One.
The fourth member of the PE family is Delay Modulation
(DM)15.'6 sometimes referred to as Miller code. Here logic One
is represented by a mid-bit interval signal level change, and a
logic Zero is represented by a signal level change at the end of
the bit interval if the logic Zero is followed by another logic
Zero. If the logiC Zero is immediately followed by a logic One,
no signal level transition at the end of the first bit interval is
used. The waveforms encoding algorithms, and general
power density spectra for the PE pulse code family are shown
in Figure 4-22.
A brief inspection of the signal waveforms for the three Biphase pulse codes reveals that their minimum signaling element has a duration of one-half bit interval (tui = tB/2); the
longest duration of either signal level is one bit interval.
Similarly, DM is seen to have a minimum signaling element
of one bit interval (tui = tB) and the maximum duration of
either signal level is two bit intervals (produced by a 101 pattern). Biphase codes should exhibit eye closure (they would
not be recoverable without equalization) when tui
to-50%'
So, a 50% jitter on NRZ signaling approximately corresponds
to the Biphase codes non-operation point. Biphase codes,
therefore, provide one-half the information rate of NRZ signals at a given maximum modulation rate. This is in exchange
for synchronization information and a dc-free spectrum when
used in polar form.
:s
Examination of RZ codes shows only one more desirable
feature than NRZ codes: clocking. RZ codes still have a dc
component in their power density spectrum (Figure 4-21)
and their bandwidth is extended (first null at 2/tB) over that
of NRZ (first null 1/tB)' RZ codes do not have any intrinsic
error detection features.
DM should have essentially the same intersymbol interference
characteristics as NRZ, since the unit interval is the same for
both codes. DM may perform slightly better than NRZ, because the maximum duration of either signal level is two bit
intervals. Overall, DM is better coding scheme than the Bi ¢.
It does not require as much bandwidth as Bi cp and still possesses the desirable dc response and synchronization qualities.
Phase Encoded (PE) Pulse Codes
The PE group of pulse codes uses signal level transitions to
carry both binary data and synchronization information. Each
of the codes provides at least one signal level transition per
bit interval aiding synchronous recovery of the binary data.
Simply stated, Biphase-Level (Bi ¢ -L) code is binary phase
shift keying (PSK) and is the result of an Exclusive-OR logic
function performed on the NRZ-L data and its clock; it is further required that the resultant signal be phase coherent
(i.e., no glitches). Biphase-Mark (Bi ¢ -M) and Biphase-Space
(Bi ¢ -5) codes are essentially phase coherent, binary frequency shift keying (FSK). In Bi ¢-M, a logic One is represented
by a constant level during the bit interval (one-half cycle of the
lower frequency 1/(2 tB)' while a logic Zero is represented by
one-half cycle of the higher frequency 1/tB' In Bi ¢-S, the
logic states are reversed from those in Bi¢ -M. Another way of
thinking of Bi4> -M or Bi 4> -5 is as follows.
•
•
Both Bi ¢ and DM are good choices for digital magnetic
recording'6; Bi ¢ is widely used in disc memory equipment,
and DM is rapidly gaining acceptance where high bit packing
densities are desired. Overall scoring, in terms of the four
desirable characteristics, shows the PE pulse codes with three
primary features; bandwidth compression, no dc, and intrinsic
synchronization.
The Bi ¢ family does not possess any intrinsic error detection
scheme. DM does possess the capability of detecting somebut not all-single bit errors. This detection process is accomplished by checking to see if a single level persists longer
than two bit intervals, in which case, an error is indicated.
DM detection requires two samples per bit interval.
Change Signal level at the end of each bit interval regardless of the logic state of the data.
Multi-Level Binary (MLB) Pulse Codes
The pulse codes in the MLB group discussed have a common
characteristic of using three signal levels (expressed in shorthand notation as +, 0, -) to represent the binary information,
but each receiver decision yields only one bit of information.
These are sometimes called pseudoternary codes to distinquish them from true ternary codes wherein each receiver
decision can yield 1.58 information bits.
Change signal level at the middle of each bit interval to
mean a particular logic state.
In Bi ¢ -M (sometimes called diphase), a mid-bit interval
change in signal level indicates a logic One (Mark), while no
*Delay Modulation 15 ,16 has a maximum of 2 t8 wjthout a signal level transition.
10-43
II
POLAR
BIPHASE
LEVEL
f\:
I
~BlPHASE~
POLAR
BIPHASE-S
L.....J
o
L.....J
L--...J
L.....J
~
L.....J
GENERAL POWER SPECTRUM FOR SPLIT PHASE CODES
l:::i
DELAY
MOD(~~TION
~+:::::::t:::::~:::f::~I::::::!I::=t::~::j::::I::::::~I::=t::~
J
I
====1
L=;=J
LINE SIGNAL SEQUENCE (b n )
DATA TO
BE SENT
B(PHASE
LEVEL
I
an
BIPHASE
MARK
;~
1
BIPHASE
SPACE
,
,
o'r-L.OR
0
;~
,
0
,
,--.r-
0
0
tui
I
,
0
,
OR
;~
I--'s----I
'B/2
O--.r-
;r---L-
OR
I
'B/2
o'~
OR
OR
0
0
I---'s----I
DELAY
MODULATION
I--ts~
I--- 's----l
I
I
'B/2
'B
if final value of b n -1
an'" 1
bn
~
bn
< , < 's/2
{t8/2 ~ t ~ t8
1+11 0
bn '" (-)
*
~
I-I b n _,'
"""complement of
final level of
last b n
*TRANSITION ONLY IF FOLLOWED
BY ANOTHER "0" (ak + 1 = O)
"
"
0
then
and
(+)
=
bn~(+1 {O<,--+---O-.~+__---------------'---------"t_t_------___(f__------------<
DATA
OUTPUT
8
DATA
DATA
OUT
OUT
SHIELD OR COMMON GROUND RETURN
b. Differential, Unipolar (Single Supply)
117511010R 75109)
INHIBIT
li2 7510710R 7[,108)
DATA
OUTPUT
DATA
INPUT
SHIELD OR COMMON GROUND RETURN
c. Differential. Unipolar (Dual Supply)
Fig. 5-4.
Simplex Distribution Bus
10-50
line driver's characteristics. Figure 5-5 shows three sets of
Ie drivers and receivers connected with their respective,
proper temination networks. HGilf-duplex operation may also
use either Single-ended or differential form with polar or
unipolar drivers.
full-duplex operation using frequency division multiplexing
(FDM) techniques is widely used. The most common example
of the FDM full-duplex operation, the 103 type modem, uses
frequency shift keying (FSK) and two frequency bands to
keep the data paths separate.
Full-Duplex operation is simultaneous, two-way data flow
between two ports. It is not usually feasible in baseband signalling, although some bridge-type circuitry has been used'
The difficulty in baseband full-duplex operation is the separation of the signal levels produced by the two drivers operating on the loop simultaneously. However, non-baseband,
The logical extension to half-duplex operation is mUltiplex
sometimes called a data bus or party line (Figure 5-6). Multiplex operation is non-simultaneous data flow among three or
more ports connected to the same physical transmission line.
Like simplex and half-duplex modes, multiplex operation
may be used in single-ended or differential form with polar
or unipolar drivers.
PORT
PORT
ENABLE
ENABLE
~ DATA
DATA
OUT
OUT
816
6
a. Single-Ended, Unipolar
PORT
PORT
ENABLES
ENABLES
DATA
DATA
"
"
t--+I~---4-~~ELD OR
COMMON GROUND
RETURN
DATA
OUT
DATA
OUT
•
t5V -'5V
b. Differential. Unipolar (Dual Supply)
1,29614
1 29614
-5V
b
I
8
J
t
I
I
}----I~
-:='
IVVISTED PAIR
TRANSMISSION LINE
-=-
DATA
OU1
c. Differential, Unipolar, (Single Supply)
Fig. 5-5.
Half-Duplex Modes of Operation
10-51
PORT 1
PORT 2
PORT 5
PORT 3
PORT 7
S'i'R6BE
STRciB'E
PORT 1
PORT 7
DATA OUT
PORT 1
DATA OUT
PORT 7
a. Single-Ended. Unipolar
RECEIVER 4
LOCATION 2
DRIVER 1
DRIVER 3
75110(OR 75109)
DRIVERS
b. Differential. Unipolar (Dual Supply)
Fig. 5-6.
Multiplex (Data Bus) Operation
The primary advantage of multiplex operation over simplex
operation is reduction of wire costs-one physical transmission line can serve where several were once required.
The disadvantages of multiplex mode include increased complexity of driver circuits to include an "off" state, and the
added logic required to implement bus protocol or "handshaking".
5) Transmitting port receives the acknowledgement, and
releases control of the bus so that other ports may
pass their data.
The overall bus operation is either polled or asynchronous.
In polled operation, a central bus controller addresses each
port in turn to ask if any data is waiting to be sent. If the addressed port has no traffic, it signals no data and the controller inquires at the next port. If the port has some data, then
the controller gives a go ahead to the port; data is sent, and
the controller then inquires at the next port.
Particularly, when multiplex operation is desired, consideration must be given to the following areas:
•
The protocol or handshaking required for a particular port
on the bus to send data must be designed. The protocol
sequence usually involves the following operations.
In asynchronous operation, any port having data essentially
"holds up its hand" and waits for a go-ahead signal to ripple
down the series enabling logic. The priority for a particular
port is determined by the ports proximity to the master control port which sends a go-ahead down the enable logic chain
at regular time intervals. This scheme is well suited to busorganized minicomputers. The Digital Equipment Corporation's Unibus® and Omnibus® architectures are excellent
examples.
1) The port must signal a desire to use the bus (interrupt).
2) Bus controller must acknowledge interrupt and send
go ahead command.
3) Port assumes control of bus and sends data, perhaps
preceded by the code to indicate the recipients(s) of
the following data.
•
4) Receiving portIs) must acknowledge receipt of data.
10-52
The effect of powered-down drivers and receivers on normal bus operation must also be considered. Integrated
circuit drivers and receivers contain paraSitic diodes that
transaction length, and the number of transactions per
port per unit time, are known 7 •
are normally reverse biased when the power supply is on.
Unless special design techniques are used, these diodes
can become forward-biased when the unit is powereddown causing the bus to malfunction.
STANDARDIZED INTERFACES
There are two main ways the interface electrical characteristics become standardized. The first, and probably most
common, is informal adoption via proliferation of devices
Excellent
having the specified electrical characteristics.
examples of this informal method are provided by TTL and
ECl logic levels, and loading rules. The input/output electrical characteristics of these two logic families have become
"standards" because many different manufacturers make
devices which can be easily interconnected.
• The protocol timing must include sufficient time delays
to allow for the different port-to-port signal propagation
delays.
•
Both physical ends of the transmission line comprising a
channel for the bus must be terminated to prevent spurious
signal levels due to reflections.
•
Stubs or taps from the main transmission line should be
kept to a minimum length. A daisy chain wiring method is
preferable to a tap-off method. If stubs must be used,
then to cause the least perturbations on the line, the stub
length should be controlled such that the propagation delay of the stub is less than 1/8 of the Signal rise or fall
time at the stub-to-line connection point.
•
Informal standards may also be born when an equipment
manufacturer announces a product that other competing
manufacturers wish to directly connect to their respective
products. If the original manufacturer of the product has a
large share of the market place (and a large number of competitors) an "instant standard" can eaSily arise. A good example of this is the IBM 360/370 I/O interface (channel to
control unit)', which is standardized primarily because, first,
IBM has a large share of the computer market place; and
second, a large number of manufacturers are interested in
selling "plug compatible" peripheral devices. Thus, one
company's electrical interface may become an informal standard in a very short time. Likewise, minicomputer manufacturers, such as DEC, may have their in-house interface
characteristics for their Unibus® and Omnibus® "standardized" via the wide application of their products, and the proliferation of competitive add-on manufacturers.
If a 3-state driver system is used (logic Zero, logic One
and off or driver in high impedance state), some means
must be provided to detect the difference between a driver
sending data and the all-drivers-off condition. In the 2state bus system, this problem does not occur because a
logic Zero (usually a HIGH) indicates either a logic Zero
or that no port is currently sending. A logic One (usually
a lOW) on a 2-state system then indicates a port is transmitting a logic One and the receiver should interpret it as
such.
Formal interface standards are usually issued either by collective associations of manufacturers (EIA), U.S. Government
and military (FIPS, DCA), international organizations (CCITT,
ISO), or other interested organizations (IEEE, ANSI). These
standards usually arise when two different pieces of equipment that may be built by two or more different manufacturers must interface, as in data terminals and data modems,
or when a government organization is setting up a system
which requires interface uniformity. Adherence to the standards is usually voluntary.
However, if a manufacturer
wishes to sell products in the application area encompassed
by the standard, it behooves him to comply if at all feasible.
In the past, formal standards have usually adopted the electrical characteristics of a pre-existing interface, especially if
the usage of such electrical characteristics was widespread
at the time the standard was drafted. The resultant standard
is then mostly a blessing given to one set of interface specifications, rather than an optimal, more general solution to
data communications interface problems. lately, both the
national and international standards organizations have been
seeking greater intercourse with one another, with an effort
to produce fewer different electrical interface standards, and
ascertain the optimum technical solution to satisfy the greatest number of application requirements. Interoperability and
compatibility with pre-existing equipment is a primary requirement in any new standard, consequently much work is
devoted to this task.
• The data format must also be considered:
Parallel operation is fast but expensive, since it requires
one transmission line and the associated interface for
every bit of the word (or byte) transmitted in parallel.
Serial operation is slower, but requires only one transmission line and interface per port. This saving may, however,
be partially offset by the need for a parallel-to-serial converter at the transmitting site, and a serial-to-parallel
converter at the receivi ng site.
The parallel structure is commonly used for rapid exchange
of data over short distances; e.g., within a computer or
between a computer and peripherals. The serial structure
is used for communications over long distances, as between
a terminal and its controller.
•
A final consideration concerns polled operation of a
multiplex system. The amount of time necessary to address and receive acknowledgement from a port must be
weighed against the volume of data the ports normally
send, and the total number of ports on the bus. If there is
a large number of ports on the bus, most of the time
might be used by the polling operation with very little
time devoted to actual exchange of information. A large
number of ports combined with a high relative volume of
traffic expected per port can lead to data backing up at
each port waiting to be sent, and an overall reduction in
information throughout. In a real time system where fast
response is essential, serious consideration should be given
to splitting up a single large bus into several satellite
busses, each with its own polling controller and protocol
with respect to the central bus. Queuing theory can be
used to estimate the throughput on a bus structure when
many variables, including the number of ports, the mean
The majority of requests for standardized interface devices
are currently for EIA RS232-C (and CCITT V.24), Mil-STDl88C (low level), and IBM 360/370 I/O. The EIA interface3
and CCITT V.244 are intended for use between data terminal
equipment (DTE) and data communications equipment (DCE).
The two standards have essentially the same electrical specifications, but differ in Signal lead nomenclature. Both standards also specify the protocol to be used between the DTE
10-53
II
need for an external capacitor for each driver. Second, the
logic function performed by the 9616 is AND-OR-INVERT
(AOI), instead of the usual NAND structure. The AOI still allows the "SPACE-~Ring" of two data signals as provided by
the NAND type drivers, while activation of the NOR (Inhibit)
input to the 9616 forces the driver to a MARK state (called
MARK Hold) regardless of the logic states of the data inputs.
The latter feature of the 9616 enables the protocol sequence
to easily be initiated or terminated without requiring the
extra logic gate needed by NAND type drivers performing the
same function. More discussion on EIA RS232-C and the
9616/9617 devices is presented in Fairchild Application
Note 320. The usage of the 9616/9617 devices as an RS232C interface is shown in Figure 5-8.
and DCE. The interface is a simplex, single-ended, polar,
unterminated type with line length and slew rate limiting
used for control of reflection effects. The implied maximum
cable length is 50 feet, and all signals are referenced to a
common signal return lead. The maximum modulation rate
on the interface is 20 kbaud. The primary electrical characteristics of the interfaces are listed in Figure 5-7.
Fairchild manufactures one triple driver (9616) and two receivers (9617 and 9627) to meet the requirements for this
application. The 9616 triple EIA/MIL line driver has two
particularly valuable features making it easier to use than
other currently available EIA interface drivers. First, the
9616 has internal slew rate limiting which eliminates the
EIA RS-232-C
Limits
Characteristic
MIN
Driver output voltage
Open circuit
V OH
VOL
-25
Driver output voltage
Loaded output
VOH
VOL
5
-15
Units
MAX
Section
in
Standard
MIL-STD-188C
(low level) Limits
Notes
25
V
V
2.6
15
-5
V
V
2.6
3 kU";RL";7 kU
2.5
-2 V"VO,,2 V
MIN
MAX
5
-7
7
-5
Units
V
V
Section
in
Standard
Notes
7.2.2.1
1
1.2.1.2
IOUT,,10mA
Driver output resistance
Power on
100
RO
RO
Power off
300
-500
Driver output short
Circuit current
Driver output slew rate
All interchange circuits
Control circuits
Rate and timing circuits
+500
30
6
6
4
Receiver input resistance RIN
Receiver open circuit
input bias voltage
rnA
2.6
V/us
V/ms
27(5)
2.7(3)
2.7(4)
2.7(4)
V/ms
%UI
3
7
-2
+2
V
2.4
V
V
2.3
3
2.4
-100
+100
rnA
7.2.1.2
5
15
O/OUI
7.2.1.3
6
3 V"VIN,,25 V
7.2.1.4
2
mod rate
,,200 kbaud
Receiver input threshold
Output
Output
= MARK
=SPACE
-3
+100
-100
~A
7.2.1.6
3
~A
NOTES:
1. Ripple ~ 0.5%, VOH' VOL matched to within 10% of each other.
2. Waveshaping required on driver output such that the signal rise or fall time is 5 to 15% of the unit interval at the applicable modulation rate (7.2.1.3).
3. Balance between marking and spacing (threshold) currents actually required shall be within 10% of each other (7.2.1.6).
Fig. 5-7.
Electrical Characteristics of EIA RS-232-C and MIL-STO-188C (Low level)
I
~
1/39616
DATA 1
DATA 2
EIARS232C
. . - - INTERFACE
INHIBIT
;:,
Vec
VEE
12 V± 10%_
~~
...L _.
139617
~ DATA OUT
)
SIGNAL COMMON
RETURN
J.12 V:;: 10°0
I
~}(r
(CIRCUIT AB)
RESP
HYST
)}---,
...L J... c'
-=
I
~~~~~~~~!SeEo:~RNoO~SO:TlONAL
IMMUNITY OF RECEIVER
Fig. 5-8.
EIA RS-232-C Interlace Application
10-54
MIL-STD-188C low level interface" devices are often requested in conjunction with RS232-C capability. Fortunately, the
two standards have overlapping specifications (See Figure 57) so that one driver designed to satisfy the electrical requirements in MIL-STD-188C also satisfies the electrical requirements in RS232-C. The notable exception is the 5 to 15%
driver signal waveshaping requirement in 188C. The 9616
was designed with both specifications in mind, so only an
external capacitor on the 9616 output (as shown in Figure
5-9) is needed to perform the required waveshaping for MILSTD-188C at the desired modulation rate.
Where EIA RS232C and MIL-STD-188C (low level) are primarily intended for use on DTE-DCE interfaces, and are
formal standards, the IBM 360/370 1/0 interface is probably the best known example of an informal standard interface. The 1/0 interface 2 is the communications link between
a channel in the System 360 or System 370 computer and the
various 1/0 control units. The interface specification delineates electrical characteristics, information formats, and control sequences to pass information between the channel and
the peripheral control unit. The primary electrical characteristics are shown in Figure 5-10. The interface is a multipex' single-ended, unipolar variety designed to operate with
up to 10 ports on a double terminated 95
transmission line
of either coax or tri-lead 6 cable. The 8T23 and 8T24 devices
satisfy the requirements in the IBM document 2 for bus
drivers and bus receivers respectively. Their use is shown in
Figure 5-11.
The electrical characteristics for the receiver in both standards are somewhat different (see Figure 5-7) in input resistance and threshold levels, but both standards are satisfied by the 9627 dual EIAIMIL interface receiver. Option
strapping on the 9627 allows the user to choose the receiver
input resistance (either 3 to 7 kn or >6 kn) and threshold
levels. The 10% threshold matching requirement MIL-STD188C can be met with the 9627 by a trimming network as
shown in Figure 5-9.
SELECTING LINE DRIVERS AND LINE RECEIVERS
Selecting a line driver-transmission line-line receiver to
meet a particular system criterion is a much easier task
1 / 69N04/7404
DATA
INPUT
Vee = +12
VEE =-12V
Vee = +12 V± 10%
VEE = 12 V ± 10%
Fig. 5-9.
'WAVE SHAPING
CAPACITOR
IF REQUIRED
MIL-STD-188C Low Level Interface Application
Characteristic
MIN
Driver output voltage
Zero state
One state
Receiver input thresholds
Receiver input current
Receiver input resistance
TRIMMING NETWORK ATTACHED TO 9627
ALLOWS SETTING OF INPUT THRESHOLDS TO
MEET 10% MATCHING REQUIREMENT
0.7
IIH
IlL
-0.24
Receiver input operating
Voltage range
Units
0.15
V
lOUT = 240 ~A
5.85
7.0
V
V
V
lOUT = -59.3 mA
lOUT = -30 ~A
lOUT = -123 mA
3.11
VIH
V IL
RIN
MAX
4
1.7
V
V
0.42
mA
mA
20
kn
7
6
V
V
-0.15
-0.15
Conditions
Notes
1
2
3
VIN = 3.11 V
VIN = 0.15 V
power on in receiver
power off in receiver
Neither drivers nor receivers will cause spurious noise on the line during a power·up or power-down sequence.
NOTES:
1. Current flow out of driver (2 term inators, 10 receivers).
2. Current flow out of driver (one receiver, no terminator).
3. Current flow out of driver during over-voltage interval to driver.
Fig. 5-10.
Electrical Characteristics for IBM System 360/370 Channel 110 Interface 2
10-55
P55
XE
POD
IS POWER OFF DISABLE
XE IS TRANSMIT ENABLE
DATAINPUTD
POD
XE
D
POD
XE
D
POD
XE
POD
D
XE
D
POD
XE
D
POD
XE
D
...
,I
I
I
I
DO
I
I
DO
I
ONE BIT SLICE OF liD BUS IS SHOWN
Fig. 5-11.
IBM 360/370 Channel 110 Interface Application
complished by connecting the shield of the line to the
ground pins of ICs connected to the line.
than initially choosing the target system characteristics. The
former is a relatively simple process of comparing the device
characteristics to the design goals. The latter is a difficult
matter because of the large number of variables involved.
Designing from scratch, however, is not an impossible task.
The primary choices to be made are as follows:
•
Simplex or multiplex operation of the lines.
•
Single-ended or differential operation.
•
Pulse code.
•
Signal quality vs line length trade-off for particular pulse
codes selected.
•
Line termination method.
SYSTEMS CONSIDERATIONS
The following points should be considered when using transmission line interface circuitry.
•
•
•
Data rates above 10 Mbaud will usually require ECl to be
used instead of n l types for the drivers and receivers, because of the 20 to 50 ns propagation delays in the n l
compatible devices.
•
Liberal use of .01 to .1 jJF capacitors to decouple the power
supplies feeding line drivers and receivers is recommended. One capacitor per power supply for every two to four
devices is usually sufficient.
REFERENCES
With these choices in mind, Figure 5-12 was constructed to
recommend the optimum Fairchild devices for the particular
applications constraints.
•
DO
IS HELD LOW WHEN A PORT IS BEING POWERE'D-UP OR POWERED·DOWN THIS
~VENTS SPURIOUS DATA FROM ENTERING THE BUS AFTER POWER SUPPLY IS UP,
POD IS SET HIGH, ALLOWING THE PORT TO TRANSMIT DA1A WHEN XE IS HIGH
I
I
•
DO
POD
The most limiting factor to data rate with long lines (> 50
feet) is usually the rise and fall time of the cable. The use
of the eye pattern allows easy measurement of signal quality (amount of time jitter).
Differential forms are preferable to single-ended forms
where high noise environments are present. Opto -isolators
and transformers offer high common mode operating
ranges and ground isolation. With transformers, a dc-free,
self-clocking code such as Bil/l (digital binary phase modulation) is useful.
The total number of ports on a multiplex system should be
restricted so that the parallel combination of the input
impedance of receivers and the output impedances of disabled drivers is greater than the characteristic resistance
of the transmission line.
Ground returns are necessary for proper operation of integrated circuit line drivers and receivers. This may be ac10-56
1.
R. Gaiser; "Two-Wire DC Baseband System for Two-Way
Simultaneous Data Transmission at High Speeds", Conference Record of 1970 International Conference on
Communications; paper 70-CP-283-COM, pp. 16-33 to
16-41.
2.
IBM System 360 and System 370 1/0 Interface Channel
to Control Unit Original Equipment Manufacturers Information; IBM document GA22-6974-1, July 1972.
3.
EIA RS-232-C; Interface Between Data Terminal Equipment and Data Communication Equipment Employing
Serial Binary Data Interchange; Electronic Industries
Association, August 1969.
4.
CCln, White Book, Volume VIII; International Telecommunication Union, 1969, recommendation V.24 (revised
and reissued as V.28).
5.
Mll-STD-188C, Department of Defense; low level Interface, section 7.2, November 1969.
6.
J.T. Kolias; "TRI-lEAD: A New Interconnection Scheme
for Computers", Electronic Packaging and Production,
February 1972, pp. 80-90.
7.
J. Martin; Systems Analysis for Data Transmission, Prentice-Hail. New York, 1972.
Standard
Recommended
Driver/Receiver
Interface
Fig.
Comments
EIA RS 232-C
9616, 1488,
75150
9617,1489,
75154
o to 20,000 bps. maximum cable length implied in standard is 50'.
5.8
MIL STD 188C
9616
9627
Use capacitor from 9616 output to ground to provide wave-shaping at
applicable modulation rate.
5-9
IBM 360 I/O
8T23,
75123
8T24,
75124
Recommended maximum of 10 ports on bus.
5-11
Single-Ended Simplex
Line
Length
(feet)
Maximum
Data Rate
(NRZ Data)
0-2'
20M bps
2 - 20'
10M bps
Line*
Type and Zo
SW ] >90
TP
COAX
n
TP
]
TPS
>90 n
COAX
COAX
20 - 500'
Recommended
Driver IReceiver
~50n
10M bps@ 20'
TPS ] >50
0.5M bps@500' COAX -
n
Comments
Fig.
Obey loading rules.
TTL
Gate
TIL
Gate
Unterminated line.
9009
or
7440
TTL
Gate
Use parallel terminated line with more than
one receiver. Use series terminated line
with only one receiver.
5·1
9S140
TTL
Gate
Use parallel terminated line with more than
one receiver. Use series terminated line
with only one receiver.
5·1
8T13,75121
8T14,75122
Use parallel terminated line.
5-3
> 500'
Not recommended. Use balanced differential form to gain system noise immunity.
Single-Ended Multiplex
0-2'
10M bps
SW
Open
Collec·
tor TTL
TTL
Gate
Use wired-AND with low value ( < 1 kQ )
collector pull up resistor.
Obey loadi ng
rules.
2 - 20'
. 10M bps
TP
COAX ] >75 n
8T13,75121
or
8T23,75123
8T14,75122
or
8T24,75124
Single +5 V supply . Use parallel term ination at both ends of bus.
20 - 500'
10M bps@20'
COAX >95 n
0.5M bps@500'
8T23,75123
8T24,75124
Use parallel termination at both ends of bus.
Single +5 V supply required.
> 500'
5-6d
5·11
5-11
Not recommended. Use balanced differen·
tial form to gain system noise immunity.
Differential Simplex
0-50'
10M bps
50 - 4,000' Use signal
quality graph.
TP ]
TPS
TPS
>50 n
>80n
>50n
>80 n
9612
9614
9613/15
9613/15
Use parallel termination.
ply required.
75110A/
112
75107/
108
Split parallel termination.
supplies required.
9612
9614
9613/15
9613/15
Use parallel termination.
ply required.
75110A/
112
75107/
108
Use split parallel termination.
-5 V supplies required.
> 4,000'
Single +5 V sup-
5-3b
5-4b
+5 and -5 V
5-3c
Single +5 V sup-
5·3b
5-4b
+5 V and
5·3c
Cable loss exceeds 6 dBV. Perhaps nonbaseband techniques should be used, (i.e.,
MODEMS).
Differential Multiplex
0-50'
15M bps
50 - 4,000' Use signal
qual ity graph.
TP
TPS
>90 n
TP ]
TPS
>90
TPS
>90 n
n
75110A/
112
75107/
108
Use split parallel termination at each end of
line. Requires +5 V and -5 V supplies.
5-6b
9614
9615
Connect as shown in half duplex differential
circuit. Requires single +5 V supply.
5-5c
75110A/
112
75107/
108
Use split parallel termination at each end of
line. Requires +5 and -5 V supplies.
5-6b
> 4,000'
Cable loss exceeds 6 db V. Perhaps non·
baseband techniques should be used, (i.e ..
MODEMS).
'SW - Single Wire over Ground Connection
TP - Twisted Pair
Fig. 5-12.
TPS - Shielded Twisted Pair
COAX - Coaxial Cable
Selection Guide for Line Drivers/Line Receivers
10-57
Section 6
SATISFYING EIA STANDARDS RS-422 AND RS-423
The Electronic Industries Association, EIA, has this year released new standards for binary digital interfaces between Data Communication Equipment (modems), and Data Terminal Equipment (CRT Terminals, teletypewriters, etc.). These standards are RS-422, Electrical Characteristics of Balanced Voltage
Digital Interface Circuits, and RS-423, Electrical Characteristics of Unbalanced Voltage Digital Interface
Circuits. RS-423 replaces the electrical section of RS-232-C, the existing EIA standard, and expands its
capabilities to include operations at higher data rates and over greater distances. RS-422 incorporates a
technology not covered by RS-232-C, defining a balanced, differential, high speed interface. The following table provides a brief comparison of the recommended maximums for these standards.
EIA
Standard
Cable Length
(Recommended Maximum)
Data Rate
(Recommended Maximum)
RS-232-C
RS-423
RS-422
50 ft.
4000 ft. @ 1 Kbps
4000 ft. @ 100 Kbps
20 Kbps
100 Kbps @ 40 ft.
10 Mbps @ 40 ft.
Development of RS-422 and RS-423 was initiated during 1973 when the existing standard, RS-232-C
was due for review. (EIA reviews its standards on a five year cycle). At this time it was decided to bring
out a new standard that would eliminate the deficiencies of RS-232-C and to reconcile it with the standards CCITT V. 24 (now revised to V. 28) and MIL-STD-188C with the hope that one standard or very
similar standards would cover the military, international and commercial areas. In addition, it was intended that the resulting standard should be readily implemented with integrated circuitry and should
facilitate an orderly transition from existing RS-232-C equipment without forcing obsolescence or expensive retrofits. At this time the structure of standards at EIA was evolving such that three separate
standards, electrical, functional and mechanical, together would replace RS-232-C .
....
0
z
w
z
0
LOAD
I~ J
OW
a:
oJ
GENERATOR ~ ~
~o
A
I
oJ::;
IDa:
«w
0 ....
AS: Generator Interface
A'S': load Interface
RECEIVER
A'
Rt
C:
C':
Rt
Vg:
Cable Termination Resistance (Optional)
Generator Circuit Ground
load Circuit Ground
Ground Potential Difference
8'
Vg
-=-
-=-
Fig. 6-1
RS-422 Balanced Interface Circuit
10-58
There are several areas for improvement in the electrical section of RS-232-C. It has been felt that
the driver and receiver circuits as well as the interchange circuit, in general, were underspecified.
More specifically, the voltage levels of the interchange signals are larger than necessary or desirable at
± 15 V. The maximum cable length was too short at 50 feet, the data rate was too low at 20 kilobits-persecond, and no provision for multiple receivers was provided. Additionally, the low common mode
operating range and susceptibility to crosstalk made some applications risky. The interconnecting cable,
itself, was only addressed in terms of length and capacitance.
The influence of RS-422 and RS-423 has been pervasive. The proposed Federal Standards 1020 and
1030 accept RS-422 and RS-423, respectively, without change. The proposed MIL-STD-188-114 incorporates RS-422 and RS-423 with only a minor addition. These standards are also being utilized by
ANSI, the Public Data Networks Interface, and at the international level they are included in CCITT provisional recommendations X.26 (unbalanced) and X.27 (balanced).
RS-422 Driver (Balanced)
RS-422 allows either a unipolar or a polar driver. The unipolar approach offers a potentially cheaper
system as its operation requires only a single power supply but at the expense of introducing a common
mode component to the signal. The polar approach offers the potential of minimizing any common mode
signal, but requires two power supplies for operation.
The generator or driver specified in RS-422 is a circuit with low impedance, balanced, voltage source
outputs that provide a differential signal voltage in the range of 2 to 6 volts. (Refer to Figure 6-1). The two
LIMITS
RS-422 DRIVER CHARACTERISTICS
MIN
Output Voltage - Open Circuit: Vo, Voa, Vob
(See Figure 6-2)
V
V
V
IVtl
2.0
0.5Vo
(IVtl-IVtl)
-0.4
0.4
V
Vos
-3.0
3.0
V
IVosl}
-0.4
0.4
V
Isa
Isb
-150
-150
150
150
mA
mA
Ixa
Ixb
-100
-100
100
100
/-LA
/-LA
20
20
0.1 tb
0.1 tb
ns
ns
ns
ns
{[Vosl -
Output Short Circuit Current: Isa, Isb
(See Figure 6-4)
Output Leakage Current - Power Off: Ixa, Ixb
(See Figure 6-5)
(-0.25 V ~ Vx ~ 6.0 V)
Transition Time - Differential: tr, tf
(See Figure 6-6)
6.0
6.0
6.0
-6.0
-6.0
-6.0
Output Offset Voltage: Vos
(See Figure 6-3)
Output Offset Voltage Matching Error:
(See Figure 6-3)
(Vos is the output offset voltage of the
opposite binary state.)
UNITS
Vo
Voa
Vob
Output Voltage - Terminated: Vt
(See Figure 6-3)
Output Voltage Matching Error:
(See Figure 6-3)
(Vt is the output voltage of the
opposite binary state.)
MAX
tb < 200 ns
tb :3 200 ns
10-59
tr
tf
tr
tf
V
V
I
signal states are defined as the MARK or OFF state, where terminal A is negative with respect to terminal S, and the SPACE or ON state, where terminal A is positive with respect to terminal S. A summary of
the specifications is contained in the preceeding table.
Fig. 6-2 Output Voltage - Open Circuit - Test Circuit
(RS-422)
A
son
±1%
Vas
-=c
50 n
±1%
B
Fig. 6-3 Output Voltage - Terminated - Test Circuit
(RS-422)
Fig. 6-4
Output Short Circuit Current - Test Circuit
(RS-422)
10-60
A
-0.25 V ,,;,Va ";'6.0 V
B
Fig. 6-5 Output Leakage Current - Power Off - Test Circuit
(RS-422)
RS-422 DRIVER
Fig_ 6-6 Switching Test Circuit
(RS-422)
In addition, the standard requires that the differential signal change monotonically in the transition region, defined as between the 10% and 90% pOints of the signal change, that any overshoot or undershoot be less than 10% of V ss , and at no time outside of the transition region shall the instantaneous
magnitude of Vt be greater than 6 volts or be less than 2 volts.
The fault conditions that a driver must withstand without damage, under either a power-on or power-off
condition are:
a.
b.
c.
d.
Driver output open circuit
Differential output short circuit
Output short circuit to ground
Output short circuit to any other lead included in RS-422 and RS-423.
These fault conditions imply that the driver must withstand a 150 milliampere source with a voltage
range of ±10 volts (signal plus common mode) being connected to its outputs.
(I I
I)
The terminated output requirement Vt ~ 0.51 Vo limits the combined output impedance of the differential outputs to less than 100 ohms. Variations in the total output impedance between output states
are also limited. The output voltage matching specification Vt
Vt ~ 0.4 V) restricts the change to
(I I - I I
10-61
I
less than 20 ohms in the case of the open circuit output voltage magnitudes being equal. An output offset
requirement ( Vos ~ 3.0 V) limits the amount of common mode signal the driver can generate. This requirement in conjunction with the offset matching specification further limits any mismatch between the
voltage levels or impedances of the two outputs. The output current range has a specified maximum
(lis ~150 mAl and an implied minimum of 20 milliamperes required by the combination of the minimum
signal (2.0 V) into a 100 ohm load.
I
I
I
The monotonicity requirement places a unique restriction on differential output circuits. It should be
noted that unless the transitions of the individual outputs overlap, a flat or zero-slope region develops in
the differential transition. While a zero-slope region, in itself, may not violate the monotonicity requirement, any ringing or system noise occurring at this point in time could. This requirement can be satisfied
if the individual transition times are kept longer than the device propagation delays; but, this eventually
compromises the system's maximum data rate. Closely matched propagation delays would permit high
speed operation while insuring a monotonic differential signal.
RS-423 Driver (Unbalanced)
The generator or driver specified in RS-423 is a circuit with a low impedance, unbalanced, voltage
source output that provides a signal of 4 to 6 V in magnitude. (Refer to Figure 6-7). The two Signal
states are defined as the MARK or OFF state when the A terminal of the driver is negative with respect to
terminal C and the SPACE or ON state when the A terminal is positive with respect to terminal C. A
summary of specifications is contained in the following table.
LIMITS
RS-423 DRIVER CHARACTERISTICS
Output Voltage - Open Circuit: Vo
(See Figure 6-8)
MIN
MAX
UNITS
Vo(space)
Vo(mark)
4.0
-6.0
6.0
-4.0
V
V
IVtl
4.0
0.9 Vo
Is
-150
150
mA
Ix
-100
100
p.,A
tr
tf
tr
tf
100
100
0.1 tb
0.1 tb
300
300
0.3 tb
0.3 tb
p.,s
p.,s
p.,s
p.,s
Output Voltage - Terminated: Vt
(See Figure 6-9)
Output Short Circuit Current: Is
(See Figure 6-10)
Output Leakage Current - Power Off: Ix
(See Figure 6-11)
(-6.0 V ~ Vx ~ 6.0 V)
Transition Times: tr, tf
(See Figure 6-12)
tb> 1.0 ms
tb
~
1.0 ms
V
V
In addition, the standard requires that the signal change monotonically in the transition region, defined
as the 10% to 90% portion of the signal change, that any overshoot or undershoot be less than 10% of
the signal amplitude, and that at no time, after the transition region is traversed, shall the instantaneous
magnitude of Vss be greater than 6 V or less than 4 V.
The fault conditions this driver must withstand in either a power-on or power-off condition are:
a.
b.
c.
d.
Driver output open circuit
Output short circuit to ground
Output short circuit to signal return
Output short circuit to any other lead included in RS-422 or RS-423
10-62
tiw
Zw
~
iil
GENERATOR
I~(j
A
~
LOAD
I
RECEIVER
AC:
A'B":
C:
C':
V g:
A'
RS-423 DRIVER
C
B'
Generator Interface
Load Interface
Generator Circuit Ground
Load Circuit Ground
Ground Potential Difference
-=
Fig.6-7
RS-423 Unbalanced Interface Circuit
RS-423 DRIVER
-=
Fig. 6-8 Output Voltage - Open Circuit (RS-423)
Test Circuit
C
-=
Fig_ 6-9 Output Voltage - Terminated - Test Circuit
(RS-423)
-=
Fig. 6-10 Output Short Circuit Current Test Circuit
(R5-423)
10-63
•
-6.0 V O'(Vx ",6.0 V
Fig. 6-11 Output Leakage Current - Power Off - Test Circuit
(RS-423)
Fig.6-12 Switching Test Circuit
(RS-423)
As with the balanced driver, this implies that the unbalanced driver must withstand a 150 mA source with
a voltage range of ± 10 V being connected to its output
(I I
The unbalanced driver output impedance is established by the terminated output specification Vt
>0.9 Vo). Since there are no output matching or offset requirements, there are no restrictions on output
impedance or voltage levels matching between output states. If, however, the driver requires an external
waveshaping method which incorporates an external resistor, then a mismatch between states in the
output impedance could be of consequence. The output current range has a specified maximum (lis
~ 150 mA) and an implied minimum of 7.8 milliamperes required by the combination of a minimum signal
(4.0 V) into a 450 n load.
I
Since this is not a differential output device, the monotonicity requirements are not as complex as in the
case of the balanced driver. However, concern must be given to the amount of crossover distortion permitted during transitions.
RS-422/RS-423 Receiver
The standards RS-422 and RS-423 are written to have identical receiver specifications such that a
single device design could satisfy both standards. Such a receiver would operate in the balanced system
(RS-422) between the differential outputs of the driver and in the unbalanced system (RS-423) between
the driver output and the signal common return. The receiver specified in RS-422 and RS-423 is a differential circuit with balanced input impedance larger than 4 kilohms and a differential input threshold
magnitude less than 200 mV over a ±7 Vcommon mode range. A summary of the specifications is
contained in the following table.
10-64
LIMITS
RS-422/RS-423 RECEIVER CHARACTERISTICS
Input Current: lia, lib
(See Figure 6-14) (-10 V ~Via ~10 V; Vib=O)
(-10 V ~Vib ~10 V; Via=O)
(Iia and lib must be in the shaded portion of the graph.)
Differential Input Voltage - Threshold Balance:
(See Figure 6-16)
(-7.0 V ~Vcm ~7.0 V)
Differential Input Voltage - Operating Range:
(See Figure 6-17)
Maximum:
(See Figure 6-14)
mA
mA
Vth
-200
200
mV
Vth Bal
Vth Bal
-400
400
mV
Vdiff
Vdiff
Vdiff max
Vdiff max
-6,0
6.0
V
-12.0
12.0
V
Via
Vib
-10
-10
10
10
V
V
Input Voltage - Maximum:
(See Figure 6-17)
C
UNITS
I
lia
lib
Differential Input Voltage - Threshold: Vth
(See Figure 6-15)
(-7.0 V ~ Vcm ~7.0 V)
Differential Input Voltage (See Figure 6-17)
MAX
MIN
RS-422 SYSTEM
-=
C'
-=
A'
---'-'-<>-
A
A'
C
B'
B'
----"-0.C'
-=
-=
(Load Circuit Ground)
RS-423 SYSTEM
Fig. 6-13 RS-422/RS-423 Receiver
c'
Fig. 6-14 Input Current - Voltage Test Circuit
(RS-422/RS-423)
10-65
-=
II
Fig.6-15 Differential Input Voltage - Threshold (RS-4221RS-423)
-7.0 V ",Vern "'7.0 V
Test Circuit
-=
Fig. 6-16 Differential Input Voltage - Threshold Balance -
Test Circuit
(RS-422/RS-423)
-=
Fig. 6-17
Input Voltage Test Circuit
(RS-422/RS-423)
The graph used to specify the input current voltage characteristic of the receiver limits the input resistance to be greater than 4 kilohms when there exists a ± 3 V bias in the driver. Permitting an internal
bias allows receivers to be designed that require only a single power supply for operation. The input balance requirement restricts not only the input threshold accuracy of the receiver, but also any mismatch
of its input resistance.
New Products
Efforts are ongoing at Fairchild to develop a family of products satisfying these standards. The first of
these announced products are:
9634 Dual 3-State Differential Line Driver (RS-422 Driver)
9638 Dual Differential Line Driver (RS-422 Driver)
9636A Dual Single-Ended Line Driver (RS-423 Driver)
9637A Dual Differential Line Receiver (RS-422/RS-423 Receiver)
10-66
VOLTAGE COMPARATORS
DATA ACQUISITION
LINE CIRCUITS- DRIVERS,
RECEIVERS ANI) TRANSCEIVER'S
"
'
PER.lPHERAL Ar')ID DISPLAY DRIVERS
MEMORY INTERFACE
ORDER INFORMATION, DICE POLICY AND PACKAGE OUTLINES
Order Information .................................................................... 11-3
Dice Policy ........................................................................... 11-4
Package Outlines ................................................................... " 11-6
ORDER INFORMATION
Three basic units of information are contained in the code.
9636A
T
Device Type
Package Type
C
Temperature Range
DEVICE TYPE
This group of al pha numeric characters defines the data sheet which specifies the device functional and electrical characteristics.
PACKAGE TYPE
One letter represents the basic package style.
D
F
H
J
K
Dual In·line Package (Hermetic, Ceramic)
Flatpak (Hermetic)
Metal Can Package
Metal Power Package (TO-66 Outline)
P
R
T
U
Metal Power Package (TO-3 Outl ine)
Dual In·line Package (Molded)
Mini DIP (Hermetic, Ceramic)*
Mini DIP (Molded)
Power Package (Molded, TO-220 Outline)
*Refer to individual data sheets for details. For special requirements, contact factory.
Different outlines exist within each package style to accommodate various die sizes and number of leads. Specific dimensions
for each package can be found in the PACKAGE OUTLINES section of this catalog.
TEMPERATURE RANGE
Two basic temperature grades are in common use:
C = Commercial/Industrial/Consumer
M
Military
_55°C to +125°C
_55°C to + 85°C
O°C to +70/75°C
-20°C to +85°C
-40°C to +60°C
_40° C to +85° C
Exact values and conditions are indicated on the individual data sheets.
EXAMPLES
1.
IlA710FM
This number code indicates a IlA710 Voltage Comparator in a flatpak with military temperature rating capability.
2.
IlA725EHC
This number code indicates a IlA725 Instrumentation Operational Amplifier, electrical option E, in a metal can with a
commercial temperature rating capability.
3.
IlA725E HCG
This number code indicates the identical device as in example 2. Except it has a gold plated kovar header; the standard
header is tin dipped.
DEVICE IDENTIFICATION/MARKING
All Fairchild standard catalog linear circuits will be marked as the following example:
MA710DC
F Date Code
UNIOUE 38510 PROCESSING
Additional processing to Fairchild Unique 38510 specifications is indicated by noting the appropriate requirements (08,
OC) after the standard order code.
Detailed ordering procedures are provided in the OEM price list.
MATRIX VI PROGRAM
Additional screening to the Fairchild Matrix VI program is indicated by the OM or OR suffix to the standard order code.
OLD ORDER CODES
Devices may continue to be purchased against old order codes (Example: U5R7723393; now 723HC). However, all products
will be marked with new order codes unless otherwise specified.
11-3
I
DICE POLICY
GENERAL INFORMATION
Fairchild linear integrated circuits, constructed using the Fairchild Planar· epitaxial process, are
available in dice form incorporating these features:
•
•
•
•
•
Commercial or Military Selection (Military Limits Probed at 25°C)
M I L-STD-883, Method 2010.2, Condition B Visual
Gold Backing
Glass Passivation
Protective Packaging
ELECTRICAL CHARACTERISTICS
Each die electrically tested at 25°C to guarantee commercial dc parameters.
Military grade dice are guardband tested at 25°C dc to guarantee military temperature range
operation.
QUALITY ASSURANCE
All Fairchild linear dice are 100% visually inspected and conform to MI L-STD-883, Method 2010.2,
Condition B. In addition, quality control visually inspects the dice to a given sampling plan.
Each die is gold backed to aid die attach. Most diec are available with glass paSSivation coating with
only the bonding pads exposed.
SHIPPING PACKAGES
Linear dice are packaged in containers with an anti-static sheet inserted between the lid and the
dice. This sheet guards against electrostatic damage during shipment and storage.
The clear plastic carrier allows visual inspection of all the packaged dice. Each carrier is heat sealed
within a transparent bag. A small piece of dehydrator paper with humidity indicating color is
inserted in each bag prior to sealing.
ORDER INFORMATION
Each linear integrated circuit die has a unique order code which describes the device type, the dice
designation and type of electrical tests performed. The dice designation is denoted by a "C" and
wafer designation is denoted by a "W." Examples follow:
Generic Type
Dice
Order Code
Wafer
Order Code
IlA741 C'·
IlA3045
75450B
IlA101A
IlA796C
IlA741CC
IlA3045CC
75450BCC
J,LA101ACC
IlA796CC
IlA741WC
IlA3045WC
75450BWC
IlA101AWC
IlA796WC
··Some device types imply a military or commercial range by the generic type. Where this does not
occur the suffix should be:
XM Military Grade Die or XC Commercial Grade Die
11-4
SPECIAL CHIP PROCESSING
If there is a need for additional testing or processing, Fairchild will negotiate with the customer to
meet his requirements.
PRODUCT AVAILABLE IN DICE FORM
Please refer to FSC OEM Price List for product available in die form.
·Planar is a patented Fairchild process.
II
11-5
FAIRCHILD PACKAGE OUTLINES
In Accordance with
JEDEC (TO-39) OUTLINE
.370 (9.40)
.335 ( 8 ' 5 1 ) M ' 3 6 0 ( 8 ' 9 0 )
'31~1~:OO)~
.040 (1.02)
MAX.
SEATING
PLANE
L
f
.
...
3'PINS
.019 (0.483)
.016 (0.406)
DIA.
nnn
--r
DIA.
BF
---t
.2:& (6.60)
.2
(6.09)
NOTES:
Pins are gold-plated kovar
Pin 3 connected to case
50 mil kovar header
Package weight is 1.23 grams
.500 (12.70)
MIN.
U U U------=:r--
1----1-- .200 (5.08) T.P.
5K
.100 (2.54)T.P:
NOTES:
Pins are gold-plated kovar
Pin 3 connected to case
50 mil kovar header
Package weight is 1.23 grams
METAL
45° T.P .
.034 (0.864)
.028 (0.771)
~ ~.040
(1.02)
.029 (0.737)
In Accordance with
JEDEC (TO-220) OUTLINE
'<:]
.500 (12.70! MIN.
t:r=~::::::::::::¥-
2
.145 (3.68)
.141D(i:i~8)
I=r=:=:::;;;;;;;;;~:=;+
(6.73)
(5.97)
~~~~~G~_·_'6_0_(L:·_06_)·f_L~~'~'
~.~---~I-t.055 (1.40)
:nlll (4.83)
(2.66)
.055 (1.40) .0 5 (2.41)
.045 (1.14)
.190(!.83).L~r---~Lt
~
1.2.10 ~
fL 195
r'--"' m
I-'.
--.
tr:::::::::::====::::::::r-
:J
NOTES:
Package is silicone plastic with boron
nickel-plated copper tab and pins
Mechanically interchangable with TO-66
Center pin is electrical contact with
the mounting tab
Package weight is 2.1 grams
GH
.110 (2.79)
.090 (2.28) ~
+~ .&;5
(1.14)
. 0 (.508)
.&~O (.762)
.
EC
5 (.381)
SECTION
x-x
NOTES:
Package is silicone plastic with nickelplated copper tab and pins
Center pin is electrical contact with the
mounting tab
Package weight is 2.1 grams
'Mechanically interchangable with TO-66
All dimensions in inches (bold) and millimeters (parentheses)
11-6
FAIRCHILD PACKAGE OUTLINES
In Accordance with
JEDEC TO-92 OUTLINE
r·
JEDEC TO-3 OUTLINE·
2 0S (5.2011
.175 (4.451
DIA.
.32518.131
.20515.21 I
I
0
~
~
.135 13.431
MAX .
,~
I=TING
SEATING
PLANE
~
I
I
~
31 - g
. 210.--t.3
.170 (4.321
.500(12.701
MIN.
1_.875122.291-1
MAX OIA.
~
PLAN~
.312 (7.921 MIN.
~3 PINS
.019 (0.4831
.016 (0.4061
DIA.
PINNO.2~
.225 15.71)
.205 15.201
r------+--.13~i~.431
T-l
.440 (11.181
.050 (1.271
T.P.
.420
(
-~:~~~:~~~g:1
'I~ -:mg~~~:
/~
,I --,<,."
~~/-
/1 ---/(f'i I
\
I __}
(10.671~q.;
J_______ "\ _~I
/
COLLECTOR
I
GLASS
BASE
~
/
COMMON
/
.161 (4.091
'-
\
21 ~U~~~I
.188 (4 78) MAX.
2 PLACES
'---- 525 (13 341 MAX
PIN NO 1
GJ
105 (2 671
080 (2031
NOTES:
Pins are gold-plated or solder dipped
alloy 52
Pins 1 and 2 electrically isolated from case
Case is third electrical connection
Aluminum package with copper slug, pins
are soldered in
Package weight is 7.4 grams
Aluminum cap (may be dome-type,
depending prod. line)
"Except pin diamater
EI
NOTES:
Pins are tin-plated copper
Package material is transfer molded
thermosetting plastic
ECB configuration
Package weight is 0.25 gram
In Accordance with JEDEC (TO-3)
OUTLINE-4-PIN
I--I I
.32518.131
.205 15.211
I
1.500138.11
1.480137.591
.835121.211
.805 120.451
--+-1
I-- I
I
1-.1
I
SEATING
PLANE
[
~II
.048 11.221 DIA
I--- .038 10.961
PINNa. 1
GK
.
NOTES:
Pins are gold-plated or solder dipped alloy
52
All pins electrically isolated from case
Package weight is 7.4 grams
"Except number of pins and pin diameter
'.
I------t-::~~ :~~~:;
PIN NO.2
2 HOLES
.151 13.841
.161 14.091
.470111.941
DIA. PIN
CIRCLE
.18814.781
2 PLACES
PIN NO.3
All dimensions in inches (bold) and millimeters (parentheses)
11-7
FAIRCHILD PACKAGE OUTLINES
In Accordance with
JEDEC (TO-91) OUTLINE
10-PIN CERPAK
JEDEC TO-39 OUTLINE*
.335 18.509)
.31518001)
-
~~: j
-
0::;~1.0!6)gl
.029 I 737)
---:::L
SEATING
PLANE
J: . ':IIo===j~~!:~:
t-~-=~~-l-~~~!i~~~i
__
-r
· -.,85.
t14699)
-+
.15?13810)
.37019.39) -+1-----'~I
.250IS.35)
I
3 PINS
~
.0191.483) I
.01S 1.406)'
~
~
.500112.70) MIN.
~
1
-.1._
l
1
DIA.
1----1-.2001508) T.P.
P~
PIN NO.1
T-.034
.028
NO.2
L
I
.260IS.60)
I
.240 16.10)-+j
t
.085 CO.216)
.07510.191 )
3F
-----METAL
.04011.016)
.029 I 737)
~
I
I
r---
.370 19.39)
NOTES:
Pins are tin plated 42 alloy
Hermetically sealed alumina package
Cavity size is .130 diamater
Package weight is 0.26 grams
.~'V--~
""
TYP.
DOS 1.152)
I.
\'0/
L.035 1.889)
.0041:(92)
PIN NO.3
45 0 T.P.
.-1
I
)..--~.~- .250 IS.35)
1
He
NOTES:
Pins are gold-plated kovar
Pin 3 connected to case
Package weight is 1.23 grams
50 mil kovar header
'Dimensions same as JEDEC TO-39 except
for can height
In Accordance with
JEDEC (TO-SS) OUTLINE
14-PIN CERPAK
•
Ie'
1
14
I·
~
I
.019 (0.483)
.010 (1.270)
7
.015(0.381) ~
=::::.J
TYP.
8
1
.260 (6. 604)
.240 (6. 096)
1
I
TYP.
.370 (9.398)
.250 (6.350)
.006 (0.152)
.004 (0.102)
31
NOTES:
Pins are tin-plated 42 alloy
Hermetically sealed alumina package
Pin 1 orientation may be either tab or dot
Cavity size is .130
Package weight is 0.26 gram
t4~==~:~~~~:~~~
!
I .260 (6.604) I
t
.025(0635)
r--.240 (6096) ---j
.065 (1.651)
TYP.
.050 (1.270)
All dimensions in inches (bold) and millimeters (parentheses)
11-8
FAIRCHILD PACKAGE OUTLINES
16-PIN CERPAK
24-PIN FLATPAK
1
.475 112.061
.425 110.801
I-
16
I
T
.050
1012 7) :
TYP. I
.409 (1.039)
,3 71 (0942)
~'
.019(0,048)
,015 (0.0381
T~~'350
.05011.271--1
TYP.
I--
8
I
.250
(088911
II
.006 (0 015)
,004 (0.0101
.019 10.481
-II-- .015 10.381
~,350
9~
,250
(0.889)
(0~~.5)
(0635)
TYP,
t=====j
I===~
' - I- - - - - '
.00510,131
.004 10.101
.283 (0.719)
I
~-.247 (0.627)1
.06411.621
~'141
*=-tiO 000000o~
f--
.028 10,711
.025 10.641
.38019,651
I
.37019.401--1
.075 (0.191)
,060 (0.152)
!
,
.024 (0.061)
TYP .
4L
NOTES:
Pins are alloy 42
Package weight is 0.4 gram
Hermetically sealed beryllia package
3M
NOTES:
Pins are gold-plated kovar
Package material is kovar
Cavity size is .120 x .235 (3.05 x 5.97)
Package weight is 0.8 gram
II
All dimensions in inches (bold) and millimeters (parentheses)
11-9
FAIRCHILD PACKAGE OUTLINES
In Accordance with
JEDEC (TO-99) OUTLINE
rr ~~;:~1
lOlA.
58
j-_-.-_
11 . 0 1 6 Q
.040
MAX.
L
SEATING=r-~
PLANE
I
8 PINS
.019104831
.016104061
OIA.
NOTES:
Pins are gold-plated kovar
Seven pins thru leads No.4 connected
to case
15 mil kovar header
Package weight is 1.22 grams
.185 14.6991
.16514.1911
f
nn n nn .04~~X0161
UU U UU - - -
.500 (12.701
MIN.
5L
NOTES:
Pins are gold-plated kovar
Eight pins thru
15 mil kovar header
Package weight is 1.22 grams
.10012.5401
T.P.
=1
;,H
JEDEC TO-101 OUTLINE
.33518.511
.305 (7.75) DIA. -
.37019.40)
-.33518.511 DIA .
.185 14.70)
'04~~~~2)~R19)
I_--t.
SEATING
PLANE
50
NOTES:
Pins are solder dipped to the seating plane .
Twelve pins thru
'Similar to JEDEC TO-101
Package weight is 1.4 grams
.500
.04~~~~2)
12 PINS
.020 (0.51)
.016 10.41)
n~~' ~ ~n (12.701 MIN.
,.......------l1
U___ 1.
__
.115
12.92) T.P .
....-~--:
.230
\
45
15.84) T.P.
2~.o"O"o.6
GLASS
~7
3~'
T.P.
All dimensions in inches (bold) and millimeters (parentheses)
11-10
FAIRCHILD PACKAGE OUTLINES
In Accordance with
JEDEC (TO-100) OUTLINE
.370 (9.398)
.335 (8.509) ---jt~===!j~-".3=35 (8.509)
.305 17.747)
SE
f
.040
NOTES:
Pins are gold-plated kovar
Ten pins thru
15 mil kovar header
Package weight is 1.32 grams
.260 (6.60)
(1016~~~;;:;:;;:;;;;;:;::J~.2~4[0((6=.~10=)_~
MAX.
u
H
.-
t
SEATING
- - - - - . - - - - - - -~PLANE
I
10 PINS
:g~t\~:~~:
.230
lm~~~~m~ .04~~X016) .50t~\~~70)
SF
(5.842)-+~--.
T.P.
NOTES:
Pins are gold-plated kovar
Nine pins through, pin 5 connected
to case
15 mil kovar header
Package weight is 1.32
.115(2.921)
T.P.
GLASS
-.------1
i
10
36°
T.P.
0 (
0
/,P
7
_&
~~~9
V
8
INSULATING STANDOFFSHAPE MAY VARY
.045 (1.143)
.029 (0.737)
.034 (0.864)
.028 (0.711)
JEDEC TO-3 OUTLINE*
JEDEC TO-100 OUTLINE
.335 (S.509)
.305 (7.747)
1F
+
= r 3 7.335
0 (9.39S)
(S.509)
+-----rr--;--,-'--------1.,-;-;-
r
~
.040
.185 (4.699)
1. 165 (4.191)
'_L!
Lt_ _~
~ ______ t_,.gATING
(1.016~
MAX.
-.----
~
SEATING
-tr--=P';:'LA""N""E~
.280 (7.11)
_~ ~ ~ ~~
.2-,-----r
(6.6_0)
PLANE
m~~~~~m .040
(1.016) .500 (12.70)
MAX.
MIN.
.020 10.511
.016 (0.41)
DIA.
. 230
I
I
10 PINS
.100(254)
.085 (2.16)
.375 (953)
.350 (8.90)
II
t
.030 (0.76) DIA. TYP .
10 PINS
-II-'-'
(5.S42)-+o---~
T.P.
.115 (2.921)
T.P.
GLASS
6
.159 (404)
.154 (3.91)
1
\10
36°
T.P.
V
.034 (0.864)
.028 (0.711)
DIA. 2 PLACES
7
~~~
8
INSULATING STANDOFF SHAPE MAY VARY
~76(4.47)
R MAX .
2 PLACES
.045 (1.143)
.029 (0.737)
.500 (1270)
DIA. TYP.
SG
SH
NOTES:
Pins are gold-plated kovar
Twelve pins thru
'Similar to JEDEC ,0-101
Package weight is 1.08 grams
NOTES:
Package material is nickel-plated CRS
Pin material is alloy 52
Glass material is corning 9010
Pin, post and base gold-plated
'Except height and number of pins
All dimensions in inches (bold) and millimeters (parentheses)
11-11
•
FAIRCHILD PACKAGE OUTLINES
In Accordance with
JEDEC (TO-100) OUTLINE
In Accordance with
JEDEC (TO-99) OUTLINE
r
p:335l8.5TI,.
1
"
,,,,,"~4~]~
I
·370 (9.40) DIA
.335 (8.51)
.305 (7.75) DIA.
PLANE
'-1-_ _ _ _ _->+_.370 (9.40) DIA
,-
.185 (4.70)
.165 (4.19)
~llflAJ1Jr
.335 (8.509)
.230
(5.84) T.P.
II
.
I
.30~\~:47) ~Il
J,
.040 (1.016)
MAX.
l
.500
.O~~ ~ ~ ~~ ~MIN.
.019 (0.48) DIA
.
.016 (0.41)
TYP. f:nifNS
.335 (8.51)
T
SEATING
PLANE
I
,
.185 (4.699)
.165 (4.191)
t
!
~
i
.~:C:~~51)_nn n nn .0~lk?2) .50~\~270)
UU U UU
t
.115
(2.92) T.P.
.016 (0.411
DIA .
GLASS
GLASS
.100 (2.54) T.P.
INSULATING
STANDOFF SHAPE MAY VARY
51
NOTES:
Pins are solder dipped to the seating plane
Ten pins thru
High RTH package
15 mil kovar header
Package weight is 1.32 grams
5M
NOTES:
Pins are solder dipped to seating plane
Eight pins thru
15 mil kovar header
Package weight is 1.22 grams
5N
NOTES:
Pins are solder-dipped to the seating plane
Nine pins through, pin 5 connected to case
15 mil kovar header
Package weight is 1.32 grams
5T
NOTES:
Pins are gold-plated kovar
Eight pins thru
'Dimensions similar to JEDEC TO-100
except for 8 pins spaced 45° apart.
Package weight is 1.22 grams.
5Q
NOTES:
Pins are solder dipped to the seating plane
Ten pins thru
15 mil kovar header
Package weight is 1.32 grams
5U
NOTES:
Pins are gold-plated kovar
Ten pins through
High RTH package
15 mil kovar header
Package weight is 1.32 grams
All dimensions in inches (bold) and millimeters (parentheses)
11-12
FAIRCHILD PACKAGE OUTLINES
JEDEC TO-96 OUTLINE·
.370 (9.398)
.
.335 (8.509) ii;====~t...:.:=.33=;.5 (8.509)
.305 (7.747)
.040
.260 (6.601
(1.016~fI-Jr;r;;;:;:;;:;;:;;:;;:;:j~.2=-4[0t.(6:::.~10~1
MAX.
**
...-LL
T
=r
I
SEATING
--PLANE
.
---.-------
10 PINS
.020 (0.511
.016 (0.411
~~
5R
m~~~~rnJ .040 (1.016) .500 (12.70)
MAX.
.230 (5.842)--+-0-------1
T.P.
NOTES:
Pins are gold-plated kovar.
Nine pins thru, Pin No.5 is connected
to case
15 mil kovar header
Package weight is 1.32 grams.
-Dimensions similar to JEDEC TO-96
except for standoff.
MIN.
.115 (2.921)
T.P.
GLASS
1
\10
36°
T.P. '. ~
~9
V
Y//
7
8
INSULATING STANDOFFSHAPE MAY VARY
.045 (1.143)
.029 (0.737)
.034 (0.864)
.028 (0.711)
In Accordance with
JEDEC TO-78 OUTLINE
-I
~H~
.30517.75)
DIA .
DIA.
.040 11.9161~---'MAX.
.185 14.691
L
SEATING
PLANE
6 PINS
.020
.016 (0.5081
<0.4061
t
DIA.
:105(4.f9j
~
...
5Z
t
J~~ ~ ~~
NOTES:
Pins are gold plated kovar.
Six pins thru.
Pins 2 and 6 are omitted.
Package weight is 0.95 gram.
.500112.701
MIN.
I
___
,
All dimensions in inches (bold) and millimeters (parentheses)
11-13
•
PACKAGE OUTLINES
In Accordance with
JEDEC (TO-116)
14-PIN HERMETIC DUAL IN-LINE
r---.
IA A
786 119.939)-----J
,.760 (19.05) ,
A A
I
6A
NOTES:
Pins are intended for insertion in hole rows
on .300" (7.6201 centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020" 10.508) diameter pin
Pins are alloy 42
Package weight is 2.0 grams
.110
.090
(2.794)
(2.286)
TYP.
16-PIN HERMETIC DUAL IN-LINE
68
.026 (.635) R
NOM.
NOTES:
Pins are tin-plated 42 alloy
Pins are intended for insertion in hole rows
on .300" centers (7.62)
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 inch diameter
pin 10.51)
Hermetically sealed alumina package
Cavity size is .110 x .140 (2.79 x 3.561
Package weight is 2.0 grams
'The .037-.027 dimension does not apply to
the corner pins
.110 (2.794)
.090 (2.286)
TYP
All dimensions in inches (bold) and millimeters (parentheses)
11-14
FAIRCHILD PACKAGE OUTLINES
24-PIN DUAL IN-LINE
t----1.290 132.7661---1
1/\1\1\/1.235 131.3691 ~I\I\I\
I
1
1211109 8 7 6 5 4 3 2 1
.570114.4781
.515113.0811
L
131415161718192021222324
-=-i ~.065 11.6511
.04511.1431
i
----1
6N
L
NOTES:
Pins are tin-plated 42 alloy
Package material is alumina
Pins are intended for insertion in hole rows
on .600 (15.24) centers
They are purposely shipped with "positive'·
misalignment to facilitate insertion
Cavity size is .230 x .230 (5.84 x 5.84)
Package weight is 6.5 grams
.100 12.5401
.04011.0161
.190 14.8261
.14013.5561
t
~;::;;::;:;:;::;;:::;::;:;;J
(--.-~~
II
.037 10.9401
.020 10.5081
.027 10.686dl-.016 10.4061
STANDOFF
WIDTH
a-PIN DUAL IN-LINE
.384 (9.7541
~ .376 (9.5501-1
14
.025 R (0.6351
.271 (6.8831
. 245 (6.2231
NOM .
6T
L!T"5~.,....,....,r-r'-r'
.00~\~12~L_
.
-J'L-I L·0~5(1.6511
.020 (0.5081 .0 5 (1.1431
.016 (0.4061
t
.200 (5.0811i=;::::::r=;::::r=1=i=il
l~
.165 (4.1911
.125 (3.1751
.011 (0.279)
09 (0229)
NOTES:
Pins are tin-plated kovar
Pins are intended for insertion in hole rows
on .300" centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 inch diameter pin
Hermetically sealed alumina package
Cavity size is .110 x .140
Package weight is 1.0 grams
.110 (2.7941
.090 (2.2861
~--~:~~g :U~ci:
All dimensions in inches (bold) and millimeters (parentheses)
11-15
II
FAIRCHILD PACKAGE OUTLINES
In Accordance with
14-PIN DUAL IN-LINE
(JEDEC TO-116 OUTLINE)
r---.
I 1\ 1\
785 (19.939)---1
,.755(19.177),
1\ 1\ I
7A
NOTES:
Pins are tin-plated 42 alloy
Pins are intended for insertion in hole rows
on .300" (7.62) centers.
They are purposely shipped with "positive"
misalignment to facilitate insertion.
Board-drilling dimensions should equal
your practice for a conventional .020"
(0.51) diameter pin .
Hermetically sealed alumina package.
Cavity size is .130 x .250 (3.30 x 6.35)
'Similar to JEDEC TO-116 except for
package width.
Package weight is 2.2 grams .
I
. 219 (5.563)
,~~J~i
rI'L
~I
. 100 12.54)
.110 (2.794)
.090 (2.286)
.037 (.940)
:o27(686)
STANDOFF
WIDTH
I
.020 (.508)
.016 (.406)
16-PIN DUAL IN-LINE
1------
:~:;g~~~: - - - - I
-t
78
.291(0.739)
. 265(0.673)
:---- .025 R (0.064)
NOM .
L L.,-r-,-"T""1-r""'T""'T"'T-r-r-~,.....J
-
II
.065 (0.165)
-.045(0.114)
-:~~~lg;~;:l
I
: '020(0'051)~
f
t
.219 (0.556) R=;H'=t=::r'Hr==i=r=;:::r;::::r=t==r1=l
1
. 170 0 ·432)
.165 (0.419)
.100 (0.254)
!!,
(0.279)_
~~ .110
.090 (0.229)
TYP.
MI N .
,Lt
I
:Ij
,--1SEATING
PLANE
.045(0.114)
:~~~
(0.028)
".
(0.023)
NOTES:
Pins are tin-plated 42 alloy
Pins are intended for insertion in hole rows
on .300" (7.72) centers.
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 inch diameter
pin (0.51)
Hermetically sealed alumina package
Cavity size is .130 x .230
'The .037-.027 (0.94-0.69) dimension does
not apply to the corner pins
Package weightis 2.2 grams
--~~.020(0.051)
.015(0.038)~ .375 (0.953) ~
.037(0.094)
.027(0.069)
STANDOFF
WIDTH
.016(0.041)
NOM.
All dimensions in inches (bold) and millimeters (parentheses)
11-16
FAIRCHILD PACKAGE OUTLINES
14-PIN QUAD IN-LINE
(JEDEC TO-116 OUTLINE)'·
1--_._____ .785119.94)
I
.750119.051
i
17
.025 10.64) R.
NOM.
. 271 16.881
.24516.221
1_
7F
NOTES:
Pins are tin-plated kovar
Board-drilling dimensions should equal
your practice for .020 (0.51) inch
diameter pin
Hermetically sealed alumina package
Cavity size is .110 x .140 (2.79 x 3.56)
'This is a 6A package with the pins formed
in assembly
'---r--r-'-'--""--'-r-r-T--.---r--,-,-,r-'
1~.065
II
11.651
.04511.141
----j
-1
r
.02010.511
.01610.41 I
: .01510.381
.185 14.70Ib=>=r='==='=r=lc::::::r=='::=i-r=l=r~.,
M~_I
I _
r-
i.'
,
I
MIN.
~I~ S,EATING d'
I
--~I I I
'.220 IS 591
0
45
I,
.13813511'
-1_.01110281
.04511 141 .11813 oOIL .420110671 ] ' .00910 231
.01510381
'.38019651 - ,
I---
-.18014571,
Ali dimensions in inches (bold) and millimeters (parentheses)
11-17
II
FAIRCHILD PACKAGE OUTLINES
14-PIN DUAL IN-LINE
(METAL CAP)
1
~'765
.740
(19.431
(18.801
I
.470 (11.941----1
.440 (11.181
7N
.320 (0.811
RADIUS
.065 (1.6S)J
.045 (1.14)
L
.310 (7.87)
.290 (7.37)
.095 (241)
.285 (724)
~mm'025(~)
L
~)
jL
t-
t !~:~':G
II
.125 (318)'
.
MIN.
~
.110 (2.791
H
)}---'-...L--q
NOTES:
Pins are gold-plated kovar
Package material is alumina
Pins are intended for insertion in hole rows
on .300" centers (7.62)
They are purposely shipped "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 (0.51) inch
diameter pin
Low temperature seal
Cavity size is .170 x .215 (4.32 x 5.46)
Package weight is 1.3 grams .
.020 (0511
--11- •
016 (041)
.
.034 (0.861
.030 (0.761
STANDOFF WIDTH
:09012.291
3-PIN SINGLE SIDE POWER PLASTIC MINIDIP
(3.81)
.150
r=
110
(2642)
n
Ir
.398
(10.11 )
~--I .125 DIA. HOLE
.125'·
(3.18)
,
t
(3.18)
-.--f.L......=~I.r-_-+-+----.1_.1 ~
n---i-.
1-------- (;~~)
I
~
"1'r'::T--.--~--
l~=rTfT;:;=~)NDICATING
-
MARK,
NO.1 PIN
,~,Jl ,~,
... ,,'" JI~
.026 10.66)
BY (U-1)
NOTES:
Pins are tin plated copper
Package weight is 0.6 gram
Package material is plastic
Tab is electrically insulated from pins
This package is intended to be mounted with
the tab flush with the top of the P.C. board
or heat sink. A No.4 screw may be used to
secure the package. Thermal compound
is recommended.
All dimensions nominal.
.032 (0.81)
JILl
.100 (2.54)-..1
i.-
All dimensions in inches (bold) and millimeters (parentheses)
11-18
FAIRCHILD PACKAGE OUTLINES
3-PIN SINGLE SIDE POWER PLASTIC MINIDIP
.11012791--i
TTi-
--1
1--.3451876 1
I .2701
r16.B61
I
I I
i.026 10.661
_=-----=-It ~
.375 .360
19.53119.141
NOTES:
Pins are tin plated copper
Package weight is 0.6 grams
Package material is plastic
Center pin is electrical contact with
mounting tab
For detailed package configuration, refer
to FSB-90717
All dimensions nominal
1
INDICATING
MARK, NO.1 PIN
I
1.33018.381-1
.135
.015
(3rf~~~50~
• I (6.351
8Y (U-2)
.020
======tI(= )F=~t.1
1-1'~----.385 (25.021-----~·
.
4-PIN SINGLE SIDE POWER PLASTIC MINIDIP
.125
(3.181
.150
(3.811
(U
.250
.021
10 531
NOTES:
Package is plastic with tin-plated copper
pins
Board-drilling dimensions should equal
your practice for .033 (0.84) inch
diameter pins
Package weight is 0.6 gram
Tab is electrically insulated from pins
This package is intended to be mounted with
the tab flush with the top of the PC board
or heat sink. A No.4 screw may be used to
secure the package. Thermal compound
is recommended .
1.040
(26 421
1
_ ("~~161
8Z (U-1)
1
INDICATING
MARK, NO.1 PIN
I
=Ii
All dimensions in inches (bold) and millimeters (parenthesesl
11-19
•
FAIRCHILD PACKAGE OUTLINES
4-PIN SINGLE SIDE POWER PLASTIC MINIDIP
-l~ r'OO~~1
.125
13.181
.150
13.811
f-'-
8Z (U-2)
NOTES:
Package is plastic with tin-plated pins
Board-drilling dimensions should equal
your practice for .033 (0.84) inch
diameter pin
Package weight is 0.6 gram
Tab is electrically insulated from pins
I
I
.250
16.351
~~--.-
INDICATING
MARK, NO.1 PIN
.530
113(61
.021
10.531
In Accordance with
14-PIN ·PLASTIC DUAL IN-LINE
(JEDEC TO-116 OUTLINE)
r---.nOI19.561~
I
A A r" .740 (18.80) A A
I
9A
-
.065 (1.851
.045 11.141
~
NOTES:
Pins are tin plated kovar
'Package material varies depending on
the product line
Pins are intended for insertion in hole rows
on .300" (7.621 centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
.
.020 (0.511 your practice
for. 0 2 0 (0.5081 .inC h
.110 (2.801
.090 12.29)
.050 11.271
.040 11.021
'3'017'87)
.290
(7.37) ~
_--..r .01010.25) diameter pin
f~:='01510'38R=
- f
""Notch or ejector hole varies depending
.~~~81
NOM.
on the product line
SEATING t
.....l
Package weight is 0.9 gram
PLANE
!
.15013.81)~"
I
I
~
.100 12.54) .110 (2.80)
.09012.29)
TYP.
l
I
--r
~~
I
.020 10.51)
.018(0.41)
.011 10.281
.D09 (0.23)
~
.37519.52)
NOM.
~
STANDOFF .03710.941
WIDTH
.027 (0.69)
All dimensions in inches Ibold) and millimeters (parentheses)
11-20
FAIRCHILD PACKAGE OUTLINES
16-PIN PLASTIC· DUAL IN-LINE
r.-.. _____
Ir
.760 119.301_---------!
.740118.801
-,
r"1
I
n
1--
98
.04511.14)
.0351.89)
.26016.60l
.240 16.101
--I 16
J_ '-r-r-r-r-r-,----,---::;=-,..,-ro·--=,.-:,::...,....,...,..
.11012.79)
.09012.29)
1.
310 17
87)~20I 51)
:~:~~NG ~
Jl ~AU'A;"~"
-1-b-t::~i:l08)- ~
~~~---
I
I
TYP.
I
t
.1181300
I
.110(279) I
I
.090(229)--+---1
I
.037 (94)
.027(69)
STANDOFF WIDTH
II
I
-jl--I
.0201.51)
.010 1.25)
\<,.
,
0
t
.0~S~64),
Y.
NOTES:
Pins are tin-plated kovar or alloy 42 nickel.
Pins are intended for insertion in hole rows
on .300" (7.62) centers
Pins purposely have a "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 inch (0.51)
diameter pin
Package weight is 0.9 gram
'Package material varies depending on the
product line
"'The .037-.027 (0.94-0.69) dimension does
not apply to the corner pins
"Notch or ejector hole varies depending on
the product line
1.~20 15 5!li I ~t~·<'
,.180(457),
'.0111.28)
L420110.67)'--J
' . 3 8 0 19.65)
,
.0091.23)
14-PIN PLASTIC QUAD IN-LINE
(JEDEC TO-116 OUTLINE·)
.045 (114 1
.03510891
9C
NOTES:
Package is epoxy with tin-plated kovar pins
Board-drilling dimensions should equal
your practice for .020 (0.51) inch
diameter pin
Package weight is 0.9 gram
'This is a 9A package with the pins formed
in assembly. Only the notched and epoxy
version is used
.03710941
.02710691
STANDOFF
WIDTH
All dimensions in inches (bold) and millimeters (parentheses)
11-21
II
FAIRCHILD PACKAGE OUTLINES
16-PIN MOLDED QUAD IN-LINE
9D QUAD PACKAGE FOR ALL
TAA, TBA, TDA TYPES
90
.11012.791
.09012.291
.05011.271
.04011.021
-h.
310 17'871~0201.511
.29017.371
.0161.411
:~:~~NG
fmm""~'~--'
,_,
'I'
I
__ ,
'I
':'
t
TYP. I
.20015.081
Jl I- J [
,':'
.11012.791
.0371.941
.09012.291-1---1
.0271.691
.
STANDOFF WIDTH
0.,
_'
':'
~
.0201.511
.0101.251
'1- -t138J511
NOTES:
Pins are tin-plated copper
Pins are intended for insertion in hole rows
on ,300" (7.62) centers
Board-drilling dimensions should equal
your practice for .020 inch <0.51)
diameter pin
Package weight is 0.9 gram
• Package material varies depending on the
product line
"The .037-.027 (0.94-0.69) dimension does
not apply to the corner pins
-
I'
.0~~~641,
.11813.00
\'0°
0
.22015.591
1 -"' .
1.:8014.5; 1
1,1
.011 1.281
L420 110.67I---=.1if. .009 1.231
'.38019.651'
1
.
14-PIN PLASTIC DUAL IN-LINE
(WITH COPPER SLUG)
9H
L.O~2Q:11
.260 (6.601
.240 (6-'0)
.070 (1781
'-6---CT=-="==r=-=c=,...=,=",==,=..,=",=-=,,=cr-d .,,~.
.---" --i.
--.
I l
~~:;:;:
~C:]f': ~:
NOTES:
Pins are gold-plated kovar
Board-drilling dimensions should equal
your practice for .020 (0.51) inch
diamater pin
Package material is epoxy with copper slug
Package weight is 0.9 gram
~
.11__ .01110.281
.00910231
.150 (381)
.100 (2.541
.110 (2.791
.090 (2.291
TYP.
All dimensions in inches (bold) and millimeters (parentheses)
11-22
FAIRCHILD PACKAGE OUTLINES
14-PIN PLASTIC DUAL IN-LINE
(COPPER SLUG AND HEAT BRACKET)"
_ DRILL FOR
4 - 40NC - 28 THREAD
9J
.420 (1067)
.400 (10.16)
PIN 1410
-
1.010 (25.651
.990 (2515)
:~~g~~:
-
.125 (3 1S1
"REF~
.560 (14,221
- - _..- .540 (13 721
i
-
,
.200 (5.081
.015 (0381
NOM.
MAX.
~EATING
I
, PLANE
::~~:~g~~:
(?9~~1
II
NOTES:
Pins are gold-plated kovar
Package material is epoxy with copper slug
and tin-plated copper bracket
Board-drilling dimensions should equal
your practice for .020 (0.51) diameter pin
• Package is the same as 9H except that a
heat bracket is attached
1~4.321.
~81)
t
r --
:~~ i~:~~(
-- - :~~~ :g:~~:
~ ~
.110 (2791
~090 (2291 TYP.
----,
--
TYP.
:~~~ :~.~~:--
.037 (0.941 STANDOFF
.027 (0.691 WIDTH
1.200 (30481 __
1.160 (2946)
.083 (2111
.073 (1 851
8-PIN PLASTIC DUAL IN-LINE
.393 (9 982).......j
363 (9 220)
,
I-
'256~Cl
u
.236(5994)
.065(1651)
5
.055 (1 397)
TYP. 4 PLACES
.190(4.826)
MAX
8
~ ~
~.
.150(3810)
.130 (3.302)
---'t'--_ _--._-=.L..!==-ll,,r-;
t
f
rr
9T
.30R. NOM. (7620)
.197(5004)
NOM
375 (9525)]
r
NOM.
310 (7 874)
·290 (7 366)l
I"
'I I
~I
-L- __;..--,-.,-=-......
1
10· NOM. 1YP.
2 PLACES
:-1
7" NOM.1YP.
r-#====t<.\
.035 (0.889)
NOM.
~
.011 (0.279)~-.039(0.991) .009(0.229)
I
.150(3.810)
.100 (2.540)
.110 (2.794)
.090 (2.286)
6~5
NOTES:
Pins are tin or gold-plated kovar
Package material is plastic
Pins are intended for insertion in hole rows
on .300" (7.62) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 (0.51) inch
diamater pin
Package weight is 0.6 gram
NOM.
TYP. 4 PLACES
TYP.
All dimensions in inches (bold) and millimeters (parentheses)
11-23
III
FAIRCHILD PACKAGE OUTLINES
4-PIN POWER MINIDIP
iLEADNO.l
9V (T1)
~I~;o~)-:l-
NOTES:
Package is plastic with tin-plated copper
pins
For detailed package configuration refer to
FSD-90669
Package weight is 0.6 gram
T-1 package can be soldered to the PC
board through .0230" x .020 (0.584 x 0.51)
slots. Double or single-sided boards may
be used.
~:;=;:=::l==r:::;=-;;_~_·:r35)
r·
375
19.52)~100
~b=20-;::-1O.5::-:-;1)"t
H
50
MIN . .140 13.56)
~d=
_____ n n
••15013.81)
t :JI ~
.230 .........:
15.84)
-
I
-
.018 10.46)
.300
-17.62)-'
1
I
1..------
I
---.1
.680117.27)
4-PIN POWER MINIDIP
.109
12.771
DIA.
9V (T2)
rLEAD NO.1
t
NOTES:
Package is plastiC with tin-plated copper
pins and wings
For detailed package configuration refer
to FSD-90670.
Package weight is 0.6 gram
T-2 package is intended to be mounted with
the tabs flush with the top of the PC board.
Either No.2-56 screws or No.2 rivets may
be used to secure the package. Single or
double-sided PC boards may be used.
Thermal compound is recommended .
.030
10.761
U
50
I
-..; 1_
.018
10.461
i ,
.10ci 12.541
~
..--
.140 -
.3~056}
----
'~~!
(7 62)--'
1---- 11~6706)
~*~
I. t 1.12~
·1
___ I
13.181
'
I
(2~~071 ------~-I
All dimensions in inches (bold) and millimeters (parentheses)
11-24
FAIRCHILD PACKAGE OUTLINES
4-PIN POWER MINIDIP
~LEADNO.1
9V (T3)
NOTES:
Package is plastic with tin-plated copper
pins and wings
Package weight is 0.6 gram
T-3 package is intended for applications
with an external heat sink. A No.2
mounting hole is provided for case of
mounting. The tab may be bent to any
convenient angle .
.230
15.841
'250~~
~16.351
j 10'
~.375~
19521
I
qI
~
I
11-'0
I
0
"J
I]
j
:too 12.541
I
-~
•
.020
'0511
!
I
.~
!
!
~
'
1\'" tJr""
I
.020
10.51
I
~.018
\
=:;=1
.140
13.561
.15013.811
I
?
I
MIN
10.461
I
'
m.,"
I
.500'
11271----j
12-PIN POWER PLASTIC DUAL IN-LINE
1-----.750(1901~,________J
.250
.250
I
1.-163511-(635)---1
I
I
I
I
r
I
I
.100
12541
iF"~,=,,!,J,==c=!~~f--"'o',l~.093
(2 361
9W (P3)
NOTES:
Package is plastic with tin plated copper
pins and wings
For detailed package configuration refer
to FSB-90698
Package weight is 0.9 gram
All dimensions in inches (bold) and millimeters (parentheses)
11-25
FAIRCHILD PACKAGE OUTLINES
12-PIN POWER PLASTIC DUAL IN-LINE
I-I
.250
.2.0
.09'
(6.35)-
(6,35)
(2.36)
DIA .
.035
(0.89)
k
.650
LIf=iT'nFrr===rrrAr+~IT
9W (P4)
1.000
'T
NOTES:
Package is plastic with tin-plated copper
pins and wings
For detailed package configuration refer
to FSB-90699
Package weight is 0.9 gram
~I~_I
I L
I _____ _
___
,--_~
~'4'~+ , '~ ,
(3.58)
DIA.
.088 (2.24)
-L====rrI'====1kF==
I I
'''12541~ ~
12-PIN POWER PLASTIC DUAL IN-LINE
9W (PS)
NOTES:
Package is plastic with tin-plated copper
pins and wings
For detailed package configuration refer
to FSD-90740.
Package weight is 0.9 gram
(20571
All dimensions in inches (bold) and millimeters (parentheses)
11-26
PACKAGE OUTLINES
12-PIN PLASTIC DUAL IN-LINE
n n n
DO 0
__________
~ _:---:-);;;-.093 12.361 DIA.
Y
16351
itrq-uc::===rtn:f'-oj~
I. J L,... "",
'u
JUl. ".. ".."",
9W (P6)
.750 (19.051--=--F
mum
.02010.51) , . 3 1 0
.015
10~8)
---r.
J~
.020
(10.51)
0
!~
_ .150
(3.81)
UI
--J
I'025~, ~~?~~-Li
T
~
I
140 (356)
.135113.43)
.125 (3.18)
NOTES:
Package is plastic with tin-plated copper
pins and wings
Package weight is 0.9 gram
The heat sinking tabs are electrically connected to the most negative potential pin
,
L
(~~:)--I-
.300 (7.62)
J
.100 (2.54)
I
All dimensions in inches (bold) and millimeters (parentheses)
11-27
FAIRCHILD FIELD SALES OFFI
REPRESENTATIVES AND DISTR
FAIRCHILD FIELD SALES OFFICES,
REPRESENTATIVES AND DISTRIBUTORS
Field Sales Offices .................................................................... 12-3
Representatives ....................................................................... 12-5
Distributors ........................................................................... 12-6
FAIRCHILD SEMICONDUCTOR SALES OFFICES
UNITED STATES AND CANADA
ALABAMA
Huntsville Office
Executive Plaza
Suite 107
4717 University Drive, NW,
Huntsville, Alabama 35805
Tel: 205-837-8906
ARIZONA
Phoenix Office
4414 N. 19th Avenue 85015
Suite G
Tel: 602-264-4948 TWX: 910-951-1544
CALIFORNIA
Los Angeles Office"
Crocker Bank Bldg.
15760 Ventura Blvd. Suite 1027
Encino 91436
Tel: 213-990-9800 TWX: 910-495-1776
Santa Ana Office'
2101 E, 4th Street 92705
Bldg. B. Suite 185
Tel: 714-558-1881 TWX: 910-595-1109
Santa Clara Office"
3333 Bowers Avenue
Suite 299
Santa Clara, 95051
IN.DIANA
Ft. Wayne Office
2118 Inwood Dri .... e 46805
Suite 111
Tel: 219-483-6453 TWX: 810-332-1507
NEW MEXICO
Alburquerque Office
2403 San Mateo N.E. 87110
Plaza 13
Tel: 505-265-5601 TWX: 910-379-6435
Indianapolis Office
Room 205
7202 N. Shadeland 46250
Tel: 317-849-5412 TWX: 810-260-1793
NEW YORK
Melville Office
275 Broadhol1ow Road 11746
Tel: 516-293-2900 TWX: 510-224-6480
KANSAS
Kansas City Office
Corporate Woods
10875 Grandview, Suite 2255
Overland Park 66210
Tel: 913-649-3974
Poughkeepsie Office
19 Da .... is Avenue 12603
Tel: 914-473-5730 TWX: 510-248-0030
MARYLAND
Columbia Office'
1000 Century Plaza
Suite 225
Columbia, Maryland 21044
Tel: 301-730-1510 TWX: 710-826-9654
MASSACHUSETTS
Boston Office'
888 Worcester Street
Wellesley Hills 02181
Tel: 617-237-3400 TWX: 710-348-0424
Tel: 408-987-9530 TWX: 910-338-0241
FLORIDA
Ft. Lauderdale Office
Executive Plaza
Suite 300-8
1001 Northwest 62nd Street
Ft. Lauderdale, Florida 33309
Tel: 305-771-0320 TWX: 510-955-4098
Orlando Office·
Crane's Roost Office Park
303 Whooping Loop
Altamonte Springs 32701
Tel: 305-834-7000 TWX: 810-850-0152
ILLINOIS
Chicago Office
The Tower - SUite 610
Rolling Meadows 60008
Tel: 312-640-1000
MICHIGAN
Detroit Office'
Johnston Building, Suite 24
20793 Farmington Road
Farmington Hills 48024
Tel: 313-478-7400 TWX: 810-242-2973
Fairport Office
260 Perinton Hills Office Park
Fairport 14450
Tel: 716-223-7700
OHIO
Dayton Office
4812 Frederick Road 45414
Suite 105
Tel: 513-278-8278 TWX: 810-459-1803
PENNSYLVANIA
Philadelphia Office
2500 Office Center
2500 Maryland Road
Willow Grove, Pennsylvania 19090
Tel: 215-657-2711
TEXAS
Dallas Office
13771 N. Central Expressway 75231
Suite 809
Tel: 214-234-3391 TWX: 910-867-4757
MINNESOTA
Minneapolis Office'
7600 Parklawn Avenue
Room 251
Edina 55435
Tel: 612-835-3322 TWX: 910-576-2944
Houston Office
6430 Hiltcroft 77081
Suite 102
Tel: 713-771-3547 TWX: 910-881-8278
NEW JERSEY
Wayne Office'
580 Valley Road 07490
Suite 1
Tel: 201-696-7070 TWX: 710-988-5846
CANADA
Toronto Regional Office
FairChild Semiconductor
, 590 Matheson Blvd .. Unit 26
Mississauga, Ontario L4W lJ1, Canada
Tel: 416-625-7070 TWX: 610-492-4311
·Field Application Engineer
I
12-3
FAIRCHILD SEMICONDUCTOR
INTERNATIONAL SALES OFFICES
AUSTRALIA
Fairchild Australia Ply Ltd.
72 Whiting Street
Artarmo" 2064
New South Wales
Australia
Tel: Sydney (02)-438-2733
(mailing address)
P.O. Box 450
North Sydney 2060
New South Wales
Australia
AUSTRIA AND EASTERN EUROPE
Fairchild ElectronicS
A-l01O Wien
Schwedenplatz 2
Tel: 0222 635821 Telex: 75096
BRAZIL
Fairchild Semicondutores Ltda
Caix8 Postal 30407
AUB Alagoas, 663
01242 Sao Paulo, Brazil
Tel: 66-9092 Telex: 011-23831
Cable: FAIRLEe
FRANCE
Fairchild Camera & Instrument S.A.
121, Avenue d'ltalie
75013 Paris, France
Tel: 331-584-5566
Telex:: 0042 200614 or 260937
GERMANY
Fairchild Camera and Instrument (Deutschland)
Daimlerstr 15
8046 Garching Hochbruck
Munich, Germany
Tel: (089) 320031 Telex: 524831 fair d
Fairchild Camera and Instrument (Deutschland)
Koenigsworther Strasse 23
3000 Hannover
W-Germany
Tel: 0511 17844 Telex: 09 22922
Fairchild Camera and Instrument (Oeutschland)
Postrstrasse 37
7251 Leonberg
'W-Germany
Tel: 07152 41026 Telex: 07 245711
MEXICO
Fairchild Mexicana S.A.
Blvd. Adolofo Lopez Mateos No. 163
Mexico 19, D.F.
Tel: 905-563-5411 Telex: 017-71-038
Fairchild Camera and Instrument (Deutschland)
Waldluststrasse 1
8500 Nuernberg
W-Germany
Tel: 0911 407005 Telex: 06 23665
SCANDINAVIA
Fairchild Semiconductor AB
Svartengsgatan 6
S-11620 Stockholm
Sweden
Tel: 8-449255 Telex: 17759
HONG KONG
Fairchild Semiconductor IHK) Ltd.
135 Hoi Bun Road
Kwun Tong
Kowloon, Hong Kong
Tel: K-890271 Telex: HKG-531
SINGAPORE
Fairchild Semiconductor Pty'Ltd.
No. 11, Lorang 3
Toa Payoh
Singapore 12
Tel: 531-066 Telex:'FAIRSIN-RS 21376
ITALY
Fairchild Semiconduttori, S.P.A.
Via Flamenia Vecchia 653
00191 Roma, Italy
Tel: 06 327 4006 Telex: 63046 (FAIR ROM)
TAIWAN
Fairchild Semiconductor (Taiwan) Ltd.
Hsietsu Bldg., Room 502
47 Chung Shan North Road
Sec. 3 Taipei, Taiwan
Tel: 573205 thru 573207
Fairchild Semiconduttori S.P.A.
Via Rosellini, 12
20124 Milano, Italy
Tel: 02 6 88 74 51 Telex: 36522
JAPAN
Fairchild Japan Corpqration
Pola Bldg.
1-15-21, Shibuya
Shibuya-Ku, Tokyo 150
Japan
Tel: 03 400 8351 Telex: 242173
KOREA
Fairchild Semikor Ltd.
K2 219-6 Gari Bong Dong
Young Dung Po-Ku
Seoul 150-06, Korea
Tel: 85-0067 Telex: FAIRKOR 22705
(mailing address)
Central P.O. Box 2806
12-4
BENELUX
Fairchild Semiconductor
Paradijslaan 39
Eindhoven. Holland
Tel: 00-31-40-446909 Telex: 00-1451024
UNITED KINGDOM
Fairchild Camera and Instrument (UK) Ltd.
Semiconductor Division
230 High Street
Potters Bar
Hertfordshire EN6 5BU
England
Tel: 0707 51111 Telex: 262835
Fairchild Semiconductor Ltd.
17 Victoria Street
Craigshill
Livingston
West Lothian. Scotland - EH54 5BG
Tel: Livingston 0506 32891 Telex: 72629
FAIRCHILD SEMICONDUCTOR SALES REPRESENTATIVES
UNITED STATES AND CANADA
ALABAMA
CARTWRIGHT & BEAN, INC.
2400 Bob Wallace Ave., Suite 201
Huntsville, Alabama 35805
Tel: 205-533-3509
MINNESOTA
PSI COMPANY
720 W. 94th. Street
Minneapolis, Minnesota 55420
Tel: 612-884-1777 TWX: 910-576-3483
CARTWRIGHT & BEAN. INC
8705 Unicorn Drive
Suite a120
Knoxville, Tennessee 37919
CALIFORNIA
CEL TEC COMPANY
18009 Sky Park Circle Suite B
Irvine, California 92715
Tel: 714-557-5021 TWX: 910-595-2512
MISSISSIPPI
CARTWRIGHT & BEAN, INC.
P.O. Box 16728
5150 Keele Street
Jackson, Mississippi 39206
TEXAS
TECHNICAL MARKETING
3320 Wiley Post Road
Charrollton. Texas 75220
Tel: 214-387-3601 TWX: 910-860-5158
Tel: 615-693-7450
Tel: 601-981-1368
CELTC COMPANY
7867 ConvoY,Court, Suite 312
San Diego, California 92111
Tel: 714-279-7961 TWX: 910-335-1512
MAGNA SALES. INC.
3333 Bowers Avenue
Suite 295
Santa Clara. California 95051
Tel: 408-985-1750 TWX: 910-338-0241
COLORADO
SIMPSON ASSOCIATES. INC.
2552 Ridge Road
Littleton, Colorado 80120
Tel: 303-794-8381 TWX: 910-935-0719
CONNECTICUT
PHOENIX SALES COMPANY
389 Main Street
Ridgefield, Connecticut 06877
Tel: 203-438-9644 TWX: 710-467-0662
MISSOURI
B.C. ELECTRONIC SALES, INC.
300 Brookes Drive, Suite 206
Hazelwood, Missouri 63042
Tel: 314-731-1255 TWX: 910-762-0600
NEW JERSEY
LORAC SALES. INC.
580 Valley Road
Wayne, New Jersey 07470
Tel: 201-696-8875 TWX: 710-988-5846
NEW YORK
LORAC SALES, INC.
550 Old Country Road, Room 410
Hicksville, New York 11801
Tel: 516-681-8746 TWX: 510-224-6480
TRI-TECH EL~CTRONICS. INC.
3215 E. Mai n Street
Endwell. New York 13760
Tel: 607-754-1094 TWX: 510-252-0891
FLORIDA
LECTROMECH. INC.
303 Whooping Loop
Altamonte Springs, Florida 32701
Tel: 305-831-1577 TWX: 810-853-0262
TRI-TECH ELECTRONICS, INC.
590 Perinton Hills Office Park
Fairport, New York 14450
Tel: 716-223-5720
LECTROMECH, INC.
1350 S. Powertine Road, Suite 104
Pompano Beach. Florida 33060
Tet: 305-974-6780 TWX: 510-954-9793
TAl-TECH ELECTRONICS, INC.
6836 E. Genesee Street
Fayetteville, New York 13066
Tel: 315-446-2881 TWX: 710-541-0604
LECTROMECH. INC.
2280 U.S. Highway 19 North
Suite 119 Bldg. L
Clearwater, Florida 33515
Tel: 813-726-0541
TRI-TECH ELECTRONICS. INC.
19 Davis Avenue
Poughkeepsie. New York 12603
Tel: 914-473-3880
GEORGIA
CARTWRIGHT & BEAN. INC.
P.O. Box 52846 (Zip Code 30355)
90 W. Wieuca Square, Suite 155
Atlanta, Georgia 30342
Tel: 404-255-5262 TWX: 810-751-3220
ILLINOIS
MICRO SALES. INC.
2258-8 Landmeir Road
Elk Grove Village. Illinois 60007
Tel: 312-956-1000 TWX: 910-222-1833
INOIANA
LESLIE M. DEVOE COMPANY
4215 E. 82nd Street Suite 0
Indianapolis. Indiana 46250
Tel: 317-842-3245 TWX: 810-260-1435
KANSAS
B.C. ELECTRONIC SALES. INC.
P.O. Box 12485. Zip 66212
8190 Nieman Road
Shawnee Mission. Kansas 66214
Tel: 913-888-6680 TWX: 910-749-6414
B.C. ELECTRONIC SALES
6405 E. Kellogg
Suite 14
Wichita, Kansas 67207
Tel: 316-884-0051
MARYLAND
DELTA III ASSOCIATES
1000 Century Plaza Suite 225
Columbia, Maryland 21044
Tel: 301-7»1510 TWX: 710-826-9654
MASSACHUSETTS
SPECTRUM ASSOCIATES. INC.
NORTH CAROLINA
CARTWRIGHT & BEAN. INC.
1165 Commercial Ave.
Charlotte, North Carolina 28205
Tel: 704-377-5673
CARTWRIGHT & BEAN. INC.
P.O. Box 18465
3948 Browning Place
Raleigh. North Carolina 27609
Tel: 919-781-6560
OHIO
THE LYONS CORPORATION
4812 Frederick Road. Suite 101
Dayton, Ohio 45414
Tel: 513~278-0714
THE LYONS CORPORATION
6151 Wilson Mills Road, Suite 101
Highland Heights. Ohio 44143
Tel: 216-461-6288
OKLAHOMA
TECHNICAL MARKETING
9717 E. 42nd Street, Suite 221
Tulsa. Oklahoma 74101
Tel: 918-622~5984
OREOON
OUADRA CORPORATION
19145 S.W. Murphy CI.
Aloha, Oregon 97005
Tel: 503-225-0350 TWX: 910-449-2592
PENNSYLVANIA
BGR ASSOCIATES
2500 Office Center
2500 Maryland Road
Willow Grove, Pennsylvania 19090
Tel: 215-657-3301
888 Worcester Street
Wellesley, Massachusetts 02181
Tol: 617-237-2796 TWX: 710-348-0424
MICHIOAN
RATHSBURG ASSOCIATES
18821 E. Warren Avenue
Detroit. Michigan 48224
Tel: 313-882~1717 Telex: 23~5229
TENNESSEE
CARTWRIGHT & BEAN. INC.
P.O. Box 4760
560 S. Cooper Street
Memphis. Tennessee 38104
Tal: 901-276-4442
12-5
TECHNICAL MARKETING
6430 Hillcrott, Suite 104
Houston, Texas 77036
Tel: 713-777-9228
UTAH
SIMPSON ASSOCIATES. INC.
P.O. Box 151430
Salt Lake City, Utah 84n5
Tel: 801-571-7877
WASHINGTON
QUADRA CORPORATION
14825 N.E. 40th Street
Suite 340
Redmond, Washington 98052
Tel: 206-883-3550 TWX: 910-449-2592
WISCONSIN
LARSEN ASSOCIATES
10855 West Potter Road
Wauwatosa. Wisconsin 53226
Tet: 414-258-0529 TWX: 910-262-3160
CANAOA
R.N. LONGMAN SALES, INC. (L.S.I.)
1715 Neyerside Drive
Suite 1
Mississauga, Ontario, L5T 1C5 Canada
Tel: 416-625-6770 TWX: 610-492-8976
R.N. LONGMAN SALES, INC. (L.S.U
16891 Hymus Blvd.
Kirkland, Quebec
H9H 3L4 Canada
Tel: 514-694-3911
TWX: 610-422-3028
FAIRCHILD SEMICONDUCTOR FRANCHISED DISTRIBUTORS
UNITED STATES AND CANADA
ALABAMA
HALLMARK ELECTRONICS
4739 Commercial Drive
Huntsville, Alabama 35805
Tel: 205-837-8700 TWX: 810-726-2187
HAMILTON/AVNET ELECTRONICS
4692 Commercial Drive
Huntsville, Alabama 35805
Tel: 205-837-7210
Telex: None-use HAMAVLECB DAL 73-0511
(Regional Hq. in Dalias, Texas)
HAMIL TON/AVNET ELECTRONICS
5921 N. Broadway
Denver, Colorado 80216
Tel; 303-534-1212 TWX: 910-931-0510
t1AMIL TON/AVNET ELECTRONICS
3901 N. 25th Avenue
Schiller Park, Illinois 60176
Tel: 312-678-6310 TWX: 910-227-0060
CONNECTICUT
CRAMER ELECTRONICS
35 Dodge Avenue
Wharton BroOk Industrial Center
North Haven, Connecticut 06473
KIERULFF ELECTRONICS
85 Gordon Street
Elk Grove Village, Illinois 60007
Tel: 312-640-0200 TWX: 910-227-3166
Tel: 203-239-5641
ARIZONA
HAMILTON/AVNET ELECTRONICS
2615 S. 21st Street
Phoenix, Arizona 85034
Tel: 602-275-7851 TWX: 910-951-1535
HAMIL TON/AVNET ELECTRONICS
643 Danbury Road
Georgetown, Connecticut 06829
Tel: 203-762-0361
TWX: None - use 710-897-1405
(Regional Hq. in Mt. Laurel, N.JJ
KIERULFF ELECTRONICS
4134 East Wood Street
Phoenix, Arizona 85040
Tel: 602-243-4101
HARVEY ELECTRONICS
112 Main Street
Norwalk, Connecticut 06851
Tel: 203-853-1515
LIBERTY ELECTRONICS
8155 North 24th Ave.
Phoenix, Arizona 85021
Tel: 602-249-2232 TWX: 910-951-4282
SCHWEBER ELECTRONICS
Finance Drive
Commerce Industrial Park
Danbury, Connecticut 06810
Tel: 203-792-3500
CALIFORNIA
AVNET ELECTRONICS
350 McCormick Avenue
Costa Mesa, California 92626
Tel: 714-754-6111 (Orange County)
213-558-2345 (Los Angeles)
TWX: 910-595-1928
FLORIDA
ARROW ELECTRONICS
1001 Northwest 62nd Street
Suite 402
Ft. Lauderdale, Florida 33309
Tel: 305-776-7790
BELL INDUSTRIES
Electronic Distributor Division
1161 N. Fair Oaks Avenue
Sunnyvale, California 94086
Tel: 408-734-8570 TWX: 910-339-9378
ARROW ELECTRONICS
115 Palm Bay Road N.W
Suite 10 Bldg. #200
Palm Bay, Florida 32905
Tel: 305-725-1408
ELMAR ELECTRONICS
2288 Charleston Rd.
Mountain View, California 94042
Tel: 415-961-3611 TWX: 910-379-6437
CRAMER ELECTRONICS
345 North Graham Avenue
Orlando, Florida 32814
Tel: 305-894-1511
HAMILTON ELECTRO SALES
10912 W. Washington Blvd.
Culver City, California 90230
Tel: 213-558-2121 TWX: 910-340-6364
HALLMARK ELECTRONICS
1302 W. McNab Road
Ft. Lauderdale, Florida 33309
Tel: 305-971-9280 TWX: 510-956-3092
HAMIL TON/AVNET ELECTRONICS
575 E. Middlefield Road
Mountain View, California 94040
Tel: 415-961-7000 TWX: 910-379-6486
HALLMARK ELECTRONICS
7233 Lake Ellenor Drive
Orlando, Florida 32809
Tel: 305-855-4020 TWX: 810-850-0183
HAMILTON/AVNET ELECTRONICS
8917 Complex Drive
San Diego, California 92123
Tel: 714-279-2421
Telex: HAMAVELEC SDG 69-5415
HAMIL TON/AVNET ELECTRONICS
N.W. 20th Avenue
Ft. Lauderdale, Florida 33309
Tel: 305-971-2900 TWX: 510-954-9808
INTER MARK ELECTRONICS INC.
4040 Sorrento Valley Blvd.
San Diego, California 92121
Tel: 714-279-5200
St. Petersburg. Florida 33702
INTERMARK ELECTRONIC INC.
1802 East Carnegie Avenue
Santa Ana, California 92705
Tel: 714-540-1322
LIBERTY ELECTRONICS
124 Maryland 'Street
EI Segundo, California 90245
Tel: 213-322-8100 TWX: 910-348-7111
LIBERTY ELECTRONICS/SAN DIEGO
8248 Mercury Court
San Diego, California 92111
Tel: 714-565-9171 TWX: 910-335-1590
COLORADO
CENTURY ELECTRONICS
8155 West 48th Avenue
Wheatridge, Colorado 80033
fel: 303-424-1985 TWX: 910-938-0393
CRAMER ELECTRONICS
5465 East Evans Place at Hudson
Denver, Colorado 80222
Tel: 303-758-2100
ELMAR ELECTRONICS
6777 E. 50th Avenue
Commerce City. Colorado 80022
Tel: 303-287-9611 TWX: 910-936-0770
68~
HAMILTON/AVNET ELECTRONICS
3197 Tech Drive, North
SCHWEBER ELECTRONICS
2830 North 28th Terrace
Hollywood, Florida 33020
Tel: 305-927-0511 TWX: 510-954-0304
GEORGIA
ARROW ELECTRONICS
3406 Oak Cliff Road
Doraville, Georgia 30340
Tel: 404-455-4054
HAMILTON/AVNET ELECTRONICS
6700 Interstate 85 Access Road, Suite 1 E
Norcross, Georgia 30071
Tel: 404-448-0800
Telex: None - use HAMAVLECB DAL 73-0511
(Regional Hq. in Dallas, Texas)
LYKES ELECTRONICS CORP
6447 Atlantic Blvd.
Norcross, Georgia 30071
Tel: 404-449-9400
ILLINOIS
HALLMARK ELECTRONICS INC.
180 Crossen Avenue
Elk Grove Village, Illinois 60007
Tel: 312-437-8800
12-6
SCHWEBER ELECTRONICS, INC.
1275 Bummel Avenue
Elk Grove Village, Illinois 60007
Tel: 312-593-2740 TWX: 910-222-3453
SEMICONDUCTOR SPECIALISTS, INC.
(mailing address)
O'Hare International Airport
P.O. BOx 66125
Chicago, Illinois 60666
(shipping address)
195 Spangler Avenue
Elmhurst Industrial Park
Elmhurst, Illinois 60126
Tel: 312-279-1000 TWX: 910-254-0169
INDIANA
GRAHAM ELECTRONICS SUPPL Y. INC
133 S. Pennsylvania SI.
Indianapolis, Indiana 46204
Tel: 317-634-8486 TWX: 810-341-3481
KANSAS
HALLMARK ELECTRONICS, INC.
11870 W. 91st Street
Shawnee Mission, Kansas 66214
Tel: 913-888-4746
HAMILTON/AVNET ELECTRONICS
9219 Guivira Road
Overland Park, Kansas 66215
Tel: 913-888-8900
Telex: None -use HAMAVLECB DAL 73-0511
(Regional Hq. in Dallas, Texas)
LOUISIANA
STERLING ELECTRONICS CORP
4613 Fairfield
Metairie, Louisiana 70002
Tel: 504-887-7610
Telex: STERLE LEC MRIE 58-328
MARYLAND
HALLMARK elECTRONICS, INC.
6655 Amberton Drive
Baltimore, Maryland 21227
Tel: 301-796-9300
HAMILTON/AVNET ELECTRONICS
(mailing address)
Friendship International Airport
P.O. Box 8647
Baltimore, Maryland 21240
(shipping address)
7235 Standard Drive
Hanover, Maryland 21076
Tel: 301-796-5000 TWX: 710-862-1861
Telex: HAMAVLECA HNVE 87-968
PIONEER WASHINGTON ELECTRONICS, INC.
9100 Gaither Road
Gaithersburg, Maryland 20760
Tel: 301-948-0710 TWX: 710-828-9784
SCHWEBER ELECTRONICS
9218 Gaither Road
Gaithersburg, Maryland 20760
Tel: 301-840-5900 TWX: 710-828-0536
MASSACHUSETTS
CRAMER ELECTRONICS
85 Wells Avenue
Newton Centre, Massachusetts 02159
Tel: 617-964-4000
GERBER ELECTRONICS
852 Providence Highway
U.S. Route 1
Dedham, Massachusetts 02026
Tel: 617-329-2400
HAMIL TON/AVNET ELECTRONICS
100 E. Commerce Way
Woburn, Massachusetts 01801
Tel: 617-933-8000 TWX: 710-332-1201
FAIRCHILD SEMICONDUCTOR FRANCHISED DISTRIBUTORS
UNITED STATES AND CANADA
HARVEY ELECTRONICS
44 Hartwell Avenue
Lexington, Massachusetts 02173
Tel: &17-861-9200 TWX: 710-326-6617
SCHWEBER ELECTRONICS
213 Third Avenue
Waltham, Massachusetts 02154
Tel: 617-890-8484
HAMILTON/AVNET ELECTRONICS
2450 Byalar Dnve S.E.
Albuquerque, New Mexico 87119
Tel: 505-765-1500
TWX: None - use 910-379-6486
(Regional Hq, in Mt. View, Ca. )
NEW YORK
ARROW ELECTRONICS
900 Broadhollow Road
MICHIGAN
HAMIL TON/AVNET ELECTRONICS
32487 Schoolcraft
livoOla, Michigan 48150
Tel: 313-522-4700 TWX: 810-242-8775
PIONEER/DETROIT
13485 Stamford
Livonia, Michigan 48150
Tel: 313-525-1800
R-M ELECTRONICS
4310 Roger B. Chaffee
Wyoming, MiChigan 49508
Tel: 616-531-9300
SCHWEBER ELECTRONICS
33540 Schoolcraft
Livonia, Michigan 48150
Tel: 313-525-8100
SHERIDAN SALES CO.
24543 Indoplex Drive
Farmington, Michigan 48024
Tel: 313-477-3800
MINNESOTA
HAMILTON/AVNET ELECTRONICS
7449 Cahill Road
Edina, Minnesota 55435
Tel: 612-941-3801
TWX: None - use 910-227-0060
(Regional Hq. in Chicago, 111.1
SCHWEBER ELECTRONICS
7402 Washmgton Avenue S.
Eden Prairie, Minnesota 55344
Tel: 612-941-5280
SEMICONDUCTOR SPECIALISTS, INC
8030 Cedar Avenue S.
Minneapolis, Minnesota 55420
Tel: 612-854-8841 TWX: 910-576-2812
Farmingdale, New York 11735
Tel: 516-694-6800
CRAMER ELECTRONICS
129 Oser Avenue
Hauppauge, New York 11787
Tel: 516-231-5682
CRAMER ELECTRONICS
6716 Joy Road
E. Syracuse, New York 13057
Tel: 315-437-6671
COMPONENTS PLUS, INC.
40 Oser Avenue
Hauppauge, LI., New York 11787
Tel: 516-231-9200 TWX: 510-227-9869
HAMILTON/AVNET ELECTRONICS
167 Clay Road
Rochester, New York 14623
Tel: 716-442-7820
TWX: None-use 710-332-1201
(Regional Hq. in Burlington, Ma.)
HAMILTON/AVNET ELECTRONICS
6500 Joy Road
E. Syracuse, New York 13057
Tel: 315-437-2642 TWX: 710-541-0959
HAMIL TON/AVNET ELECTRONICS
70 State Street
Westbury, 1.I., New York 11590
Tel: 516-333-5800 TWX: 510-222-8237
ROCHESTER RADIO SUPPLY CO., INC.
140 W. Main Street
(P.O. Box 19711 Rochester, New York 14603
Tel: 716-454-7800
SCHWEBER ELECTRONICS
Jericho Turnpike
Westbury, L.I., New York 11590
Tel: 516-334-7474 TWX: 510-222-3660
MISSOURI
HALLMARK ELECTRONICS, INC,
13789 Rider Trail
Earth City, Missouri 63045
Tel: 314-291-5350
JACO ELECTRONICS. INC.
145 Oser Avenue
Hauppauge. 1.I., New York 11787
Tel: 516-273-1234 TWX: 510-227-6232
HAMILTON/AVNET ELECTRONICS
396 Brookes Lane
Hazelwood, MiSSOUri 63042
reI: 314-731-1144 TWX: 910-762-0606
SUMMIT DISTRIBUTORS. INC.
916 Main Street
Buffalo. New York 14202
Tel: 716-884-3450 TWX: 710-522-1692
NEW JERSEY
HAMIL TON/AVNET ELECTRONICS
218 Little Falls Road
Cedar Grove, New Jersey 07009
Tel: 201-239-0800 TWX: 710-994-5787
NORTH CAROLINA
CRAMER ELECTRONICS
938 Burke Street
Winston Salem, North Carolina 27102
Tel: 919-725-8711
HAMILTON/AVNET ELECTRONICS
113 Gaither Drive
East Gate Industrial Park
Mt. Laurel, N.J. 08057
Tel: 609-234-2133 TWX: 710-897-1405
HAMIL TON/AVNET
2803 Industrial Drive
Raleigh, North Carolina 27609
Tel: 919-829-8030
SCHWEBER ELECTRONICS
43 Belmont Drive
Somerset, N.J. 08873
Tel: 201-469-6008 TWX: 710-480-4733
HALLMARK ELECTRONICS
1208 Front Street. Bldg. K
Raleigh, North Carolina 27609
Tel: 919-823-4465 TWX: 510-928-1831
STERLING ELECTRONICS
774 Pfeiffer Blvd.
Perth Amboy, N.J. 08861
Tel: 201-442-8000 Telex: 138-679
RESCO
Highway 70 West
Rural Route 8, P.O. Box 116-B
Raleigh, North Carolina 27612
Tel: 919-781-5700
WILSHIRE ELECTRONICS
102 Gaither Drive
Mt. laurel, N.J. 08057
Tel: 215-527-1920
PIONEER/CAROLINA ELECTRONICS
103 Industnal Drive
Greensboro, North Carolina 27406
Tel: 919-273-4441
WILSHIRE ELECTRONICS
1111 Paulison Avenue
Clifton, N.J. 07011
Tel: 201-365-2600 TWX: 710-989-7052
OHIO
HAMILTON/AVNET ELECTRONICS
761 Beta Drive. Suite E
Cleveland, Ohio 44143
Tel: 216-461-1400
TWX: None - use 910-227-0060
(Regional Hq. in Chicago. III.)
NEW MEXICO
CENTURY ELECTRONICS
11728 Linn Avenue
Albuquerque, New Mexico 87123
Tel: 505-292-2700 TWX: 910-989-0625
12-7
HAMIL TON/AVNET ELECTRONICS
118 West park Road
Dayton, Ohio 45459
Tel: 513-433-0610 TWX: 810-450-2531
PIONEER/CLEVELAND
4800 E 13151 Street
Cleveland, OhIO 44105
Tel: 216-587-3600
PIONEER/DAYTON
1900 T roy Street
Dayton, Ohio 45404
Tel: 513-236-9900 TWX: 810-459-1622
SCHWEBER ELECTRONICS
23880 Commerce Park Road
Beachwood, Ohio 44122
Tel: 216-464-2970 TWX: 810-427-9441
SHERIDAN/CLEVELAND
Unit 28
Versaplex Bldg.
701 Beta Drive
Cleveland, Ohio 44143
Tel: 216-461-3300 TWX: 810-427-2957
SHERIDAN SALES CO.
(mailing address)
P.O. Box 37826
Cincinnati, Ohio 45222
(shipping addressl
10 Knollcrest Drive
Reading, Ohio 45237
Tel: 513-761-5432 TWX: 810-461-2670
SHERIDAN SALES COMPANY
2501 Neff Road
Dayton, Ohio 45414
Tel: 513-223-3332 TWX: 810-459-1732
OKLAHOMA
HALLMARK ELECTRONICS
4846 S. 83rd East Avenue
Tulsa, Oklahoma 74145
Tel: 918-835-8458 TWX: 910-845-2290
RADIO INC. INDUSTRIAL ELECTRONICS
1000 S. Main
Tulsa, Oklahoma 74119
Tel: 918-587-9123
PENNSYLVANIA
HALLMARK ELECTRONICS, INC.
458 Pike Road
Huntingdon Valley. Pennsylvania 19006
Tel: 215-355-7300 TWX: 510-667-1727
PIONEER/DELEWARE VALLEY ELECTRONICS
141 Gibraltar Road
Horsham, Pennsylvania 19044
Tel: 215-674-4000 TWX: 510-665-6778
PIONEER ELECTRONICS, INC.
560 Alpha Drive
Pittsburgh, Pennsylvania 15238
Tel: 412-782·2300 TWX: 710-795·3122
SCHWEBER ELECTRONICS
101 Rock Road
Horsham, Pennsylvania 19044
Tel: 215-441·0600
SHERIOAN SALES COMPANY
4297 Greensburgh Pike
Suite 3114
Pittsburgh, Pennsylvania 15221
Tel: 412-351-4000
SOUTH CAROLINA
DIXIE ELECTRONICS, INC.
P.O. Box 408 (Zip Code 29202)
1900 Barnwell Street
Columbia. South Carolina 29201
Tel: 803-779-5332
TEXAS
ALLIED ELECTRONICS
401 E. 8th Street
Fort Worth, Texas 76102
Tel: 817-336-5401
CRAMER ELECTRONICS
13740 Midway Road, Suite 700
Dallas. Texas 75240
Tel: 214-661-9300
HALLMARK ELECTRONICS CORP.
10109 McKalla Place Suite F
Austin, Texas 78758
Tel: 512-837-2814
HALLMARK ELECTRONICS
9333 Forest Lane
Dallas. Texas 75231
Tel: 214-234-7300
FAIRCHILD SEMICONDUCTOR FRANCHISED DISTRIBUTORS
UNITED STATES AND CANADA
HALLMARK ELECTRONICS, INC.
8000 Westglen
Houston, Texas 77063
CAM GARD SUPPL Y L TO.
Rookwood Avenue
Fredericton, New Brunswick, E3B 4Y9, Canada
Tel: 713-781-6100
Tel: 506-455-8891
HAMILTONIAVNET ELECTRONICS
4445 Sigma Road
Dallas, Texas 75240
CAM GARD SUPPLY L TO.
15 Mount Royal Blvd.
Moncton, New Brunswick, E1C aNS, Canada
Tel: 214-661-8661
Tel: 506-855-2200
Telex: HAMAVlECB DAl 73-0511
HAMIL TONIAVNET ELECTRONICS
3939 An n Arbor
Houston, "Tex8s 77042
Tel: 713-780-1771
Telex: HAMAVLECB HOU 76~2589
SCHWEBER ELECTRONICS, INC.
14177 Proton Road
Dallas, Texas 75240
Tel: 214-661-5010 TWX: 910-860-5493
SCHWEBER ELECTRONICS, INC.
7420 Harwin Drive
Houston, Texas 77036
Tel: 713-784-3600 TWX: 910-881-1109
STERLING ELECTRONICS
4201 Southwest Freeway
Houston. Texas 77027
Tel: 713-627-9800 TWX; 901-881-5042
Telex: STELECO HOUA 77-5299
UTAH
CENTURY ELECTRONICS
2258 S. 2700 West
Salt Lake City, Utah 84119
Tel; 801-972-6969 TWX: 910-925-5686
HAMIL TONJAVNET ELECTRONICS
1585 W. 2100 South
Salt Lake City, Utah 84119
Tel: 801 -972-2800
TWX: None - use 910-379-6486
(Regional Hq. in Mt. View, Ca')
WASHINGTON
HAMIL TONIAVNET ELECTRONICS
'3407 Northrup Way
Bellevue, Washington 98005
Tel: 206-746-8750 TWX: 910-443-2449
LIBERTY ELECTRONICS
1750 132nd Avenue N.E.
Bellevue, Washington 98005
Tel: 206-453-8300 TWX: 910-444-1379
RADAR ELECTRONIC CO., INC.
168 Western Avenue W.
Seattle, Washington 98119
Tel: 206-282-2511 TWX; 910-444-2052
WISCONSIN
HAMIL TONJAVNET ELECTRONICS
2975 Moorland Road
New Berlin, Wisconsin 53151
Tel: 414-784-4510
MARSH ELECTRONICS. INC.
1563 S. 100 Street
Milwaukee, Wisconsin 53214
Tel: 414-475-6000
CANADA
CAM GARD SUPPLY LTD.
640 42nd Avenue S.E.
Calgary, Alberta, T2G 1 Y6, Canada
TeJ: 403-287-0520 Telex: 03-822811
CAM GARD SUPPLY LTD.
10505 111th Street
Edmonton, Alberta TSH 3E8, Canada
Tel: 403"'26-1805 Telex: 03-72960
CAM GARD SUPPLY LTD.
4910 52nd Street
Red Deer, Alberti, T4N 2C8, Canada
Tel: 403-346-2088
CAM GARD SUPPLY LTD.
3065 Robie Street
Halifax, Nova Scotia, B3K 4P6, Canada
Tel: 902-454-8581 Telex: 01-921528
CAM GARD SUPPLY L TO.
1303 Scarth Street
Regina, Saskatchewan, S4A 2E7, Canada
Tel: 306-525-1317 Telex: 07-12667
CAM GARD SUPPLY LTD.
1501 Ontario Avenue
Saskatoon, Saskatchewan, S7K lS7, Canada
Tel: 306-652-6424 Telex; 07-42825
ELECTRO SONIC INDUSTRIAL SALES
(TORONTO) LTD.
1100 Gordon Baker Rd.
Willowdale. Ontario, M2H 383, Canada
Tel: 416-494-1666
Telex: ESSCO TOR 06-22030
FUTURE ELECTRONICS CORPORATION
130 Albert Street
Ottawa, Ontario, K1P 5G4, Canada
Tel: 613-232-7757
FUTURE ELECTRONICS CORPORATION
44 Fasket Drive, Unit 24
Rexdale, Ontario, M9W 1K5, Canada
Tel: 416-677-7820
FUTURE ELECTRONICS CORPORATION
5647 Ferrier Street
Montreal, Quebec, H4P 2K5, Canada
Tel: 514-735-5775
HAMILTONIAVNET INTERNATIONAL
(CANADA} LTD.
6291 Dorman Rd., Unit 16
Mississauga, OntariO, L4V 1H2, Canada
Tel: 416-677-7432 TWX: 610-492-8867
HAMILTONIAVNET INTERNATIONAL
(CANADA) LTD.
1735 Courtwood Crescent
Ottawa, OntariO, K1Z 5L9, Canada
Tel: 613-226-1700
HAMILTONIAVNET INTERNATIONAL
(CANADA) L TO.
2670 Paulus Street
St. Laurent, Quebec, H4S 1G2, Canada
Tel: 514-331-6443 TWX; 610-421-3731
RAE. INDUSTRIAL ELECTRONICS, LTD.
1629 Main Street
Vancouver, British Columbia, V6A 2W5, Canada
Tel: 604-687-2621 TWX: 610-929-3065
Telex: RAE-VCR 04-54550
SEMAD ELECTRONICS LTD.
625 Marshall Ave., Suite 2
Dorval, Quebec, H9P 1E1, Canada
Tel: 514-636-4614 TWX: 610-422-3048
SEMAD ELECTRONICS LTO.
105 Brisbane Road
Downsview, Ontario M3J 2K6, Canada
Tel: 416-635-9880 TWX: 610-492-2510
SEMAD ELECTRONICS LTD.
1485 Laperriere Avenue
Ottawa, Ontario, K1Z 758, Canada
Tel: 613-722-6571 TWX: 610-562-8966
CAM GARO SUPPLY LTD.
825 Notre Dame Drive
Ka mlooP8, Britllh Columbia, V2C 5N8, Canada
Tel: 604-372-3338
CAM GARD SUPPLY LTD.
1777 Ellice Avenue
Winnepeg, Manitoba. R3H OW5, Canada
Tel: 204-786-8401 Telex: 07-57622
12-8
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