1981_Standard Microsystems 1981 Standard

User Manual: 1981_StandardMicrosystems

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INDEX
PART NUMBER .....

PAGE
3

FUNCTIONAL .....

4-7

CROSS REFERENCE .....

8-9

GENERAL INFORMATION
FACILITIES/CUSTOM CAPABILITIES .....

10-14

QUALITY ASSURANCE. . . . .

15-16

DATA COMMUNICATION PRODUCTS .....

17-118

CRT DISPLAY ..... 119-160

TABLE
OF
CONTENTS

PRINTER ..... 161-174

BAUD RATE GENERATOR ..... 175-204

KEYBOARD ENCODER ..... 205-218

MICROPROCESSOR PERIPHERAL ..... 219-250

ORDERING INFORMATION
PACKAGE DATA ..... 252-253
REPRESENTATIVES AND DISTRIBUTORS ..... 254-255

PART NUMBER INDEX
PART NUMBER
COM 1553A
COM 1671
FOC 1791
FOC 1792
FOC 1793
FOC 1794
COM 1863
COM 2017
COM 2017H
ROM 2316E
KR 2376XX
COM 2502
COM 2502H
COM 2601
COM 2651
FOC 3400
CCC 3500
KR 3600XX
ROM 36000
CG 4103
ROM 4732
SR 5015XX
SR 5015-80
SR 5015-81
SR 5015-133
COM 5016
COM 5016T
SR 5017
SR 5018
COM 5025
COM 5026
COM 5026T
CRT 5027

PAGE
19
35
241
241
241
241
51
59
59
221
207
59
59
67
75
231
243
211
227
163 .
223
167
167
167
167
177
177
171
171
77
179
179
121
3

PART NUMBER

PAGE

COM 5036
COM 5036T
CRT 5037
COM 5046
COM 5046T
CRT 5047
CRT 5057
FOC 7003
CRT 7004A
CRT 7004B
CRT 7004C
CRT 8002A
CRT 8002B
CRT 8002C
COM 8004
COM 8017
COM 8018
COM 8046
COM 8046T
COM 8116
COM 8116T
COM 8126
COM 8126T
COM 8136
COM 8136T
COM 8146
COM 8146T
COM 8251A
COM 8502
CRT 9006
CRT 9007
CRT 96364A/B

181
181
121
183
183
129
121
239
155
155
155
145
145
145
89
95
51
189
189
191
191
193
193
195
195
197
197
103
95
135
131
137

FUNCTIONAL INDEX
~ Data Communication Products
Part
Number
COM 1553A
COM 1671

COM 1863

COM 2017

COM 2017H

COM 2502

COM 2502H

COM 2601

Jill][

Name
MIL-STD1553A UART
ASTRO

UART

USRT

COM 2651(1) USART/PCI

COM 5025

COM 8004

COM 8017

COM 8018

COM 8251A

COM 8502

(1)

Multi-Protocol
USYNRT

32 Bit CRC
Generator/
Checker
UART

UART

USART

UART

Description
MIL-STD-1553 (Manchester) Interface
Controller
Asynchronous/Synchronous
Transmitter/Receiver, Full Duplex,5-8
data bit, IX or 32X clock
Universal Asynchronous Receiver/
Transmitter, Full Duplex,5-8 data bit,
1, 1'12, 2 stop bit, enhanced distortion
margin
Universal Asynchronous Receiver
Transmitter, Full Duplex,5-8 data bit,
1, IV" 2 stop bit
Universal Asynchronous Receiver/
Transmitter, Full Duplex, 5-8 data bit,
1, 1'12, 2 stop bit
Universal Asynchronous Receiver/
Transmitter, Full Duplex, 5-8 data bit,
1,2 stop bit
Universal Asynchronous Receiver/
Transmitter, Full Duplex,5-8 data bit,
1,2 stop bit
Universal Synchronous Receiver/
Transmitter, STR, BSC, Bi-sync
compatible
Universal Synchronous/Asynchronous
Receiver/Transmitter, Full Duplex, 5-8
data bits; 1, 1 V" 2 stop bit, IX, 16X,
64X clock
SDLC, HDLC, ADCCP, Bi-sync, DDCMP
compatible, automatic bit stuffingl
stripping, frame detection/generation,
CRC generation/checking, sync detection
Companion device to COM 5025
for 32 bit CRC
Universal Asynchronous Receiver/
Transmitter, Full Duplex,5-8,data bit,
1, 1 V" 2 stop bit
Universal Asynchronous Receiver/
Transmitter, Full Duplex,5-8 data bit,
1, 1'12, 2 stop bit, enhanced distortion
margin
Universal Synchronous/Asynchronous
Receiver/Transmitter, Full Duplex, 5-8
data bit, 1, 1'12, 2 stop bit
Universal Asynchronous Receiver/
Transmitter, Full Duplex,5-8 data bit,
1,2 stop bit

For future release

Baud Rate
1 MB
1 MB

40KB

Power
Supplies

Package

Page

40 DIP

19-34

40 DIP

35-50

40 DIP

51-58

+5, -5, +12

25 KB

+5,-12

40 DIP

59-66

40KB

+5,-12

40 DIP

59-66

25 KB

+5,-12

40 DIP

59-66

40KB

+5, -12

40 DIP

59-66

250 KB

+5, -12

40 DIP

67-74

28 DIP

75-76

40 DIP

77-88

1 MB

1.5 MB

+5, +12

2.0MB

20 DIP

89-94

40KB

40 DIP

95-102

40KB

40 DIP

51-58

64 KB (sync)
9.6 KB (async)

28 DIP

103-118

40KB

40 DIP

95-102

CHARACTEB. GBlDIBATOB.
Part lI'umber
CG 4103(3)

Description

Max Access Time

Power SuppUes

5x7x64

1.2 p,sec

+5, -12 or +12

SHIFT BBGISTBB.
Part lI'umber
SR 5015-XX

Description

SR 5015-80
SR 5015-81
SR 5015-133

Quad
Mask
Quad
Quad
Quad

SR 5017

Quad 81 Bit

SR 5018

Quad 133 Bit

I'eature

StatiC Shift. Register
Programmable Length
80 Bit Static
81 Bit Static
133 Bit Static

Max
Clock I'req.

Power
Supply

Package

Page

1 MHz

16 DIP

167-170

1 MHz

16 DIP

171-174

Load, Recirculate,
Shift Controls,

Shift Left/Shift
Right, Recirculate
Controls, Asynchronous clear

Microprocessor Peripheral

fI!IIlIIIt

B.OM

Part lII'umber

Description

Access Time

Power Supply

Package

Page

ROM2316E '1 1!31

16K ROM; 16,384 bits
organized 2048x8

450nsec

24 DIP

221-222

ROM 4732'31

32K ROM; 32,768 bits
organized 4096x8

460nsec

24 DIP

223-226

ROM 36000'11131

64K ROM; 65,536 bits
organized 8192x8

250nsec

24 DIP

227-230

~ PLOPPT DISK
Part
lI'umber

Description

Write
Pre-comPower
Sector
IBM
I'ormat Density Compatible pensation SuppUes

FDC
FDC
FDC
FDC
FDC

1791(1) Floppy Disk
1792'1 , Controller/Formatter
1793(1)
1794(1.
3400
Floppy Disk Data Handler
provides serial/parallel interface, sync detection
FDC 700t ' ) Floppy Disk
Controller/Formatter

Soft
Soft
Soft
Soft
Hard

Soft

Double
Single
Double
Single
NA.

Yes
Yes
Yes
Yes
NA.

External
External
External
External
No

Single/
Double

Yes

Internal

+5,
+5,
+5,
+5,
+5,

+12
+12
+12
+12
-12

Package

Page

DIP
DIP
DIP
DIP
DIP

241-242
241-242
241-242
241-242
231-238

40 DIP

239-240

40
40
40
40
40

CASSBTTB/CAB.TB.IDGB
Part lI'umber
CCC 3500

Description

Max
Data Rate

Cassette/Cartridge Data Handler

250K bps

(1)For future release
(3)May be custom mask programmed

I'eatures
Sync byte detection,
Read While Write

Power
Supply

Package

Page

+6, -12

40 DIP

243-250

Baud Bate Generator
put frequencies simultaneously for full duplex
communication.
Baud Rate Generators providing all standard baud
rates from various popular crystal frequencies are
available. In addition the baud rate generator may
be custom mask programmed for other divisors.

All Baud Rate Generators are programmable
dividers capable of providing 16 output frequencies' for UARTs or USARTs from either an on-chip
crystal oscillator or an external frequency input.
"T" versions utilize an external frequency input
only. Dual Baud Rate Generators provide two out'except as noted

Part Number
COM 5016

Description
Dual Baud Rate Generator

COM 5016T
COM 5026

Dual Baud Rate Generator
Single Baud Rate Generator

COM 5026T
COM 5036

Single Baud Rate Generator
Dual Baud Rate Generator

COM 5036T

Dual Baud Rate Generator

COM 5046

Single Baud Rate Generator

COM 5046T

Single Baud Rate Generator

COM 8046

Single Baud Rate Generator

COM 8046T

Single Baud Rate Generator

COM 8116

Dual Baud Rate Generator

COM 8116T

Dual Baud Rate Generator

COM 8126

Single Baud Rate Generator

COM 8126T

Single' Baud Rate Generator

COM 8136

Dual Baud Rate Generator

COM 8136T

Dual Baud Rate Generator

COM 8146

Single Baud Rate Generator

COM 8146T

Single Baud Rate Generator

Peatures
On-chip oscillator or external
frequency input
External frequency input
On-chip oscillator or external
frequency input
External frequency input
COM 5016 with additional
output of input frequency -i- 4
COM 5016T with additional
output of input frequency -i- 4
COM 5026 with additional
output of input frequency -i- 4
COM 5026T with additional
output of input frequency -i- 4
32 baud rates; IX, 16X, 32X
clock outputs; single + 5 volt
supply
COM 8046 with external
frequency input only
Single +5 volt version of
COM 5016
Single + 5 volt version of
COM 5016T
Single + 5 volt versiop. of
COM 5026
Single +5 volt version of
COM 5026T
Single + 5 volt version of
COM 5036
Single +5 volt version of
COM 5036T
Single + 5 volt version of
COM 5046
Single + 5 volt version of
COM 5046T

Power
Supplies
+5, +12

Package
18 DIP

Page
177-178

+5, +12
+5, +12

18 DIP
14 DIP

177-178
179-180

+5, +12
+5, +12

14 DIP
18 DIP

181-182

+5, +12

18 DIP

181-182

+5, +12

14 DIP

183-188

+5, +12

14 DIP

183-188

16 DIP

189-190

16 DIP

189-190

18 DIP

191-192

18 DIP

191-192

14 DIP

193-194

14 DIP

193-194

18 DIP

195-196

18 DIP

195-196

14 DIP

197-198

14 DIP

197-198

179-180

Keyboard Encoder
Part Number 1'1'0. of ][eys
KR-2376 XX(3)
88
KR-3600 XX(3)
90

Modes
3
4

Standard Ponts
Power
Peatures
Description
Supplies Package
8uff1lt
+5, -12
40 DIP
ASCII
2 Key Rollover -ST
-ST
+5, -12
40 DIP
2 Key or
ASCII
N Key Rollover -STD
ASCII
-PRO
Binary Sequential

(3)May be custom mask programmed

Page
207-210
211-218

CR! Display
nAC~
Part.umber

De.cription

TIIIDTG COBTllOLLBBB

CRT 6047
CRT 6067
CRT9007(l)
CRT 96364A/B

proVides all of the
timing and control
for interlaced and
non-interlaced CRT
displaur
CRT Video processor
and controller
complete CRT
processor

Clock

Power
SuppU.

programmable

4 MHz

+6,+12

PacJmCe
40 DIP

121-128

balanced beam interlace

programmable

4 MHz

+6,+12

40 DIP

121-128

fixed format

80 column
24 row

4 MHz

+6,+12

40 DIP

129-130

line-lock

programmable

4 MHz

+6,+12

40 DIP

121-128

sequential or rowtable driven memol'l'_
on-chip cursor and
write control

programmable

4 MHz

40 DIP

131-134

1.6 MHz

28 DIP

137-144

CRT 6027
CRT 6037

Diaplay
I"ormat

J'eanre.

64 column
16 row

Pace

VDAC™ DISPLAY COBTBOLLBBS
Pan l'I'umber
CRT 8002A(2,3)

CRT 8002B(2,3)

CRT 8002C(2,3)

Description

Display

PrOvides complete
display and attributes control for
alphanumeric and
graphics display.
ConSists of 7x11x128
character generator,
video shift register,
latches, graphics and
attributes circuits.

7x 11 dot matriX,
wide graphics,
thin graphics,
on-chip cursor

.Attribute.
reverse video
blank
blink
underline
strike -thru

Ku:
Clock

Power
Supply

Package

Pace

28 DIP

145-154

20 MHz

16 MHz

10 MHz

CJl.AB.ACTBB GElUIBATOB8
Pan l'I'umber
CRT 7004A(34)
CRT 7004B(34)

De.cription
7x11x 128 character generator,
latches, video shift register

CRT 7OO4C(34)

Xaz
I"requency
20 MHz

Power Supply

Package

Page

16 MHz

24 DIP

166-159

10 MHz

BOW BUFFEB
Pan .umber
CRT 9006-83 '11

X_
Bow Length

De.cription
8 bit wide serial cascadable row buffer memory
for CRT or printer

CRT 9006-135

Power Sullply

Package

Page

24 DIP

135-136

63 characters
135 characters

(1 )For future release
(2)Also available as CRT 8002A,B,C-001 Katakana
CRT 8002A,B,C-003 6X7 dot matrix

be custom mask programmed
'Also available as CRT 7004A,B,C-003 5X7
dot matrix

(3)Maur
,4

SMC CROSS REFERENCE GUIDE
Description

UART (1'12 8B)**

AMI

E.A.

81883

Harris

Intel

AY
86850*

UART (N-Channel)**
UART (N-Channel)*

81602

U8RT

S2350*

AY3-1015

HM6402

AY3-1015

HM6403*

IM6·
8251*

A8TRO
PCI
U8ART

8251A
F3846*
F6856*

Multi-Protocol,
U8YNRT
Dual Baud Rate Gen.
8ingle Baud Rate Gen.

HD4702*
HD6405*

F4702*

88 Key KB Encoder

AY 5-2376
EA2007*
2030*
2007*

90 Key KB Encoder

Character Generator

AY 5-3600

88564*

Character Generator
Character Generator
8hift Register

Inte

AY 5-1013A

UART (1, 2 8B)**
UART (N-Channel)**

G.I.

Fairchild

88499

RO 5-22408*

82182/3/5

Shift Register
CRT Controller

8275*

ROM

868332

ROM

84264*

8332

RO 3-9332
R03-9364

* Functional Equivalent
**Most UART's are interchangeable; consult the factory for detailed information on interchangeability.

2332*

IM6<

VlOS
nnology

Mostek

Motorola

National

NEe

MM5303*

pPD369*

Signetics

MC6850*

Solid
State
Scientific

Synertec

T.I.

W.O.

TMS6011

TR1602

TR1402

TR1983*

TR1863

INS1671

UC1671

2651

INS8251

pPD8251A

pPD379*

2652

SD1933*

BR1941L

81009*

MM5740*

pPD364*

TMS5001

MCM66700*
MC6570*

DM8678*

2609*

M5240*

TMS4103

5054*

2532*

TMS3113*
TMS3114*

SND5037

MC14411*

31004*
32027*

MK2002

MK1007*

MK3807

MC6845*

MCM8332

332
364*

MK36000

MM5307*

MC1132*

MCM68A364*

DP8350*

MM52864*

2536

SCR1854

SND5025

::!~Q5027

6545*

TMS9927

pPD2332

2632

SY2332

TMS4732

pPD2364*

2664*

SY2364*

TMS4764*

Innovation in microelectronic technology is
the key to growth at Standard Microsystems.
Since its inception, Standard Microsystems has been a leader in creating
new technology for metal oxide semiconductor large scale integrated
(MOS/LSI) circuits.
For example, while the first MOS/LSI processes were P-channel, it
was recognized very early that an N-channel process would greatly improve
switching speeds and circuit density. However, the fundamental problem
of parasitic currents needed to be solved. The research and development
staff at Standard Microsystems recognized this problem and directed its
energy toward the development of its now-famous COPLAMOS® technology. COPLAMOS® defines a self-aligned, field-doped, locally oxidized
structure which produces high-speed, high-density N-channel IC's.
In addition, on-chip generation of substrate bias, also pioneered by
Standard Microsystems, when added to the COPLAMOS® technology,
results in the ability to design dense, high-speed, low-power N-channel
MOS integrated circuits through the use orone external power supply voltage.
Again recognizing a need and utilizing its staff of qualified process
experts, Standard Microsystems developed the CLASP®process. The need
was for fast turnaround, easily programmable semi-custom LSI technology.
The development was CLASp,® a process that utilizes ion implantation to
define either an active or passive device which allows for the presence of a
logical 1 or 0 in the matrix of a memory or logic array. This step is accomplished after all wafer manufacturing steps are performed including metalization and final passiviation layer formation. Thus, the wafer can be tested
and stored until customer needs dictate the application, a huge saving in
turnaround time and inventory costs.
These innovations in both process and circuit technology have
received widespread industry recognition. In fact, many of the world's
most prominent semiconductor companies have been granted patent and
patent/technology licenses covering various aspects of these technologies.
The companies include Texas Instruments, IBM, General Motors, ITT and
Western Electric.

Our engineering staff follows the principle
that "necessity is the mother of invention~'
This philosophy led Standard Microsystems Corporation to COPLAMOS~
CLASP® and other innovative developments. It also brings companies to
us to solve tough problems that other suppliers can't.
But it's a philosophy that involves more than just developing the
next generation of MOS/LSI devices.
Such exploration, for example, helped Standard Microsystems
recognize the need for communication controllers to handle the latest
data communication protocols. As a result, Standard Microsystems was
the first to introduce a one-chip LSI controller for HOLC protocolsthe COM 5025.
The COM 5025 is so versatile it can actually provide the receiver/
transmitter functions for all the standard bit and byte oriented synchronous
protocols, including SOLC, HOLC, ADCCp, bi-sync and OOCMP.
In another area, CRT display systems have traditionally required a
great deal of support circuitry for the complex timing, refresh and control
functions.
This need led the engineers at Standard Microsystems to develop
the CRT 5027 Video Timer and Controller (VTAC®) that provides all these
functions on a single chip. This left the display, graphics and attributes control
spread over another 20 or 30 SSI, MSI and LSI devices. Standard Microsystems combined all these functions in the CRT 8002 Video Display
Attributes Controller VDACM). The COPLAMOS®process was used to
achieve a 20 MHz video shift register, and CLASP®was used for fast
turnaround of character font changes through its last stage programmability.
So from 60 to 80 integrated circuits, Standard Microsystems reduced
display and timing to 2 devices, drastically reducing the cost and size of
today's CRT terminal.
Achievements like these help keep Standard Microsystems custom
and standard products in the forefront of technology with increased speeds
and densities, and a lower cost per function.

I
•

Improvements in processing and manufacturing
keep pace with advances in semiconductors.
With the phenomenal growth of the electronics industry, innovation is,
of course, highly desirable. But if the products are to perform as deSigned,
they also have to be reliable.
That's why at Standard Microsystems we take every means to insure
the utmost quality and dependability. Consequently, "state-of-the-art"
applies not only to our products, but to the way we manufacture them.
In wafer fabrication, the latest equipment and techniques are employed.
In addition to conventional processing equipment, we use ion implantation
technology extensively. We also use plasma reactors for much of our etching
and stripping operations to maintain tight tolerances on process parameters.
To make plastic packaging immune to moisture, we use a process that
deposits a protective (passivating) layer of silicon nitride on the device surface.
Standard Microsystems processes include high and low voltage
P-channel metal gate, N-channel silicon gate (COPLAMOS®), high-speed
N-channel silicon gate with depletion mode devices, and CLASP® In general,
these processes have been engineered so that they are also compatible
with most industry standard processes.
One obvious advantage our total capability gives customers, is that
they can bring us their project at any stage in the development process.
For instance, they may already have gone through system definition. Or
they may have gone all the way to prototype masks, and only want production runs.
It makes no difference to Standard Microsystems. We can enter the
process at any level.
Our full service capability lets us make full use of the technologies
we develop. We can produce any quantity of semiconductors customers
may require. And we can offer them one of the fastest turnaround times
in the industry.

SMC microcircuits are built under the
industry's most carefully controlled conditions.
Standard Microsysfems uses the latest equipment and techniques for
assembly - just as it does for processing. Automatic wire-bonding which
we introduced recently to expand Standard Microsystems' capacity is a
typical example.
However, nothing is left to chance. To make sure every IC performs
the way it should, each product is subjected to 37 quality control checks
during assembly. Every run that comes out of wafer fabrication is analyzed
to insure that all of its DC electrical characteristics are within specifications.
Standard Microsystems' computerized analysis techniques, in fact, are
second to none in the industry.
Tightly-controlled QC measures include die and pre-seal inspection
and wire-pull, among others. Assembled parts are further subjected to
vigorous mechanical tests including centrifuge, temperature cycling, and
hermeticity testing.
Naturally, to perform all these tests properly requires adequate
personnel. That's why 35% of all Standard Microsystems production technicians are assigned to the Quality Control Department.
Many tests are computer-controlled. In addition, we use dedicated
equipment designed to simulate the customers' systems requirements.
Thanks to the dedication of Standard Microsystems' highly-motivated
technical staff and well-trained production personnel, Standard Microsystems has one of the highest product yields in the industry.

SMC can supply standard microcircuits
or custom-design them to your requirements.
The product mix at Standard Microsystems is approximately half custom
products and half standard products.
This makes Standard Microsystems the ideal company to ta:lk with
if you're undecided which direction to take.
As a matter of fact, a combination of custom and standard may
actually be best for you.
Since our processes are industry compatible, we can enter a program
at any level: 1. Complete system design and definition; 2. Artwork generation; 3. Wafer processing.
If you need quick turnaround on mask-proerammable options, we
can also combine COPLAMOS®technologywith CLASp®(which stands
for COPLAMOS®Last Stage Programmable), to provide the solution.
As for standard products Standard Microsystems makes one of the
widest lines of standard MOS 7LSI circuits for data communications and
computer peripherals in the industry.
Standard Microsystems custom circuits have found their way into
such industrial, computer, and aerospace applications as computer
peripherals, modems, telecommunications, data communications, home
entertainment, word processing, pay Tv, and many other consumer and
industrial uses. In fact, Standard Microsystems has created over 100
different custom designs for the above applications.
Standard or custom LSI? Bring your requirements to Standard
Microsystems. We'll give you an unbiased recommendation as to which
is the best route for you to take.

Quality Assurance
It is well understood at Standard Microsystems that
for an integrated circuit to be attractive to a system
designer, it must provide not only state-of-the-art circuit
function, but do so with a high degree of reliability.
The manufacture of reliable quality product is no accident. Although testing is necessary to flag problems as
soon as possible, it is an old adage that quality cannot be
tested into a product, but must be designed in and built in.
The design of a reliable product is assured by adherence to tested and proven design rules. Before any
change in design rules or processing steps is accepted for
production, sample runs are exhaustively evaluated for
both basic reliability and consistent manufacturability.

The manufacturing flow is closely monitored byquality
assurance to insure not only that all potential failures
are identified and rejected, but that proper standards are
met for the processing itself. Clean room standards,
calibrations and work methods are all monitored.
In addition, test and field failures are analyzed in conjuction with design and process engineering to monitor
and correct any possible flaws in either design or
manufacture.
Product flow and screening for standard devices is
shown on the following flow charts. In addition,
MIL-STD-883 level B screening may be done on request.

STANDARD PROCESSING
INCOMING WAFERS
INSPECTION

AH purchased materials
are inspected to written
specifications.

WAFER
FABRICATION
IN-PROCESS INSPECTION

Wafers are 100%
inspected at each major
manufacturing step.
Wafers are electrically
tested for key processing
parameters before release
from wafer processing.
Each die is electrically
tested. Dice not meeting
electrical requirements are
inked.

DIE SEPARATION

100% DIE INSPECTION
MOLDED PACKAGES

HERMETIC PACKAGES

DIE ATTACH

DIE ATTACH
INSPECTION

Random sample of
packages are centrifuged
at 30KG to test die attach
strength.

DIE ATTACH!NSPECTION

2 wires on every
part are pulled.

WIRE PULL
SAMPLE

Samples are tested
periodically for pull until
breakage.

WIRE PULL SAMPLE

PRE-SEAL INSPECTION: bond position,
wire dress, workmanshio.

PRE-ECAPSULATION INSPECTION,
bond position, wire dress,
workmanship.

TEMPERATURE CYCLE

LEAD FORM

100% TEMPERATURE CYCLE

100% CENTRIFUGE

100% FINE LEAK

100% GROSS LEAK

VISUAL INSPECTION

FINAL TEST

HIGH TEMPERATURE
CONTINUITY

Q.C.AUDIT

FINAL TEST

Q.C.AUDIT

VISUAL INSPECTION

PACK

STOCK

SHIP

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COM 1553A
JLPC FAMILY
Preliminary Data

MIL-STD-1553A "SMART®"
FEATURES

PIN CONFIGURATION

o Support of MIL-STD-1553A
o Operates as a: Remote Terminal Responding
Bus Controller Initiating
o Performs Parallel to Serial Conversion when
Transmitting
o Performs Serial to Parallel Conversion when
Receiving
o Compatible with HD-15531 Manchester Encoder/
Decoder
o All Inputs and Outputs are TTL Compatible
o Single +5 Volt Supply
o COPLAMOS® N Channel MaS Technology
o Available in PC Board Form from Grumman

"0" MSG FlG 1

40GND

'0" WRD FlG 2

39 SDCST

IVWF 3

37 AD1

TX INT 6

36AD2
3SAD3

CMD SYN 7

34AD4

DTA SYN 8

33 ADS

RCV NRZ 9

32 R.DE

SWE 10

31 D7

POR 11

30 DB

IA 12

29 OS

RCV ClK 13

Aerospace Corporation

3BVcc

DTA AVl 4
Rev INT 5

2804

VW14

27 D3

SEND DATA 1S

26 D2

DTA RQST 16

2501

MSG COMPlT 17

2400

TX ENA 18

23 TDE

TX elK 19

22TX MODE

XMIT NRZ 20

PACKAGE: 40-pin D.I.P.

GENERAl. DESCRIPTION
The COM 1553A SMART® (Synchronous Mode Avionics
Receiver/Transmitter) is a special purpose COPLAMOS
N-Channel MaS/LSI device designed to provide the
interface between a parallel 8-bit bus and a MIL-STD1553A serial bit stream.
The COM 1553A is a double buffered serial/parallel and
parallel/serial converter providing all of the "hand
shaking" required between a Manchester decoder/
encoder and a microprocessor as well as the protocol
handling for both a MIL-STD-1553 bus controller and
remote terminal.
The COM 1553A performs the following functions in
response to a 16 bit Command Word. It provides address
detection for the first five bits of the serial data input.
If all 1's appear in the address field, a broadcast signal
is generated. The sixth bit is decoded as mode: transmit
or receive. The next five bits are decoded for zero
message flag and special flags in the subaddress/mode
field. The last five bits (word-count field) are decoded
determining the number of words to be received or
transmitted.
When receiving data sync the COM 1553A performs a
serial to parallel conversion, buffers the 16 bit message

word, and formats it into two parallel (8 bit) bytes for
presentation to the I/O bus under processor or hard
wired logic control.
In the transmit mode the COM 1553A takes two parallel
8 bit data words from the I/O bus and serially transmits
the resultant 16 bit word to the Manchester encoder.
This is done under the control of Send Data. To facilitate
data transfer the COM 1553A provides all necessary
buffering and storage for transmitted and received data.
It also provides all necessary hand shaking, control
flags and interrupts to a processor or hard wired logic
terminal. See block diagram 1.
The COM 1553A can be set up as either a remote terminal or a bus controller interface.
The COM 1553A is compatible with Harris' HD-15531
CMOS Manchester Encoder-Decoder chip and interfaces directly with it. A 3 device kit consisting of: SMC's
COM 1553A, Harris' HD-15531 and Circuit Technology's
CT1231 forms a complete system interface for the
message structure of MIL-STD-1553A. See block
diagram 2.
Note: All terminology utilized in this data sheet is
consistent with MIL-STD-1553.

BLOCK DIAGRAM 1

TERMINAL {AD1
ADDRESS
AD5
CMD SYNC
DATA SYNC
VALID WORDTX ENABLE
SEND DATA
DATA REQ
DATA AVAil

...J

«
z

H---"TD0

CONTROL
LOGIC

I/O SELECT

Q(I)
I- =>
} &3 co

I
I

a: «

-I-

-lD7

~C3

I-

RCVINTERROPT

::2:1(1)5
x => a:

D
Z
(!)

iREcEi~---------CO~A~SYNC

~;~:~;{

DIJ-D7

DATA SYNC

ENCODER/~R~C~V~N~RZ~____~I

DECODER

"0" MESSAGE FLG
"0" WORD FlG
INVALIO WORD FlG

RCV ClK

P:..:-..:::::::..:.-----I~I

hM~E?,;S~S9iA~G~E~C~OffM;;ip;fliiET¥;E.-----1

B
DATA REQUEST
DATA AVAil
RCVINTERRUPT
TXINTERRUPT
READ DATA ENBl
TAKE DATA ENBl

XMIT NRZ
TX ClK
TX ENABLE

II:
W
f-

SEND DATA
TRANSMIT

()

::;;

TERMINAL
ADDRESS

BLOCK DIAGRAM 2

PROCESSOR
INTERFACE

DESCRIPTION OF PIN FUNCTIONS

PIN NO.

NAME

SYMBOL

FUNCTION

"0" MESSAGE FLAG

0MF

The ZERO MESSAGE FLAG output is set when the 7th
through 11th bits of the NRZ serial input data in a command
envelope (see figure 1) are zero. 0MF is an open drain output.

"0" WORD FLAG

0WF

The ZERO WOR D FLAG output is set when the 12th th rough
16th bits of the NRZ serial input data in a command envelope (see
figure 1) are zero. 0WF is an open drain output.

INVALID WORD
FLAG

IVWF

The INVALID WORD FLAG output is set when the word just
received has an invalid parity bit or invalid format. IVWF is an open
drain output.

DATA AVAILABLE

DTA AVL

DATA AVAILABLE is set when a word received is ready to be read.
When the COM 1553A is the bus controller, DTA AVL occurs on
command, status or data words. When the COM 1553A is a remote
terminal, DTA AVL is set only on data words. DTA AVL is an open
drain output.

RECEIVE INTERRUPT

RCVINT

RECEIVE INTERRUPT is set to zero when the 6th bit follO~
command sync is a zero and thefirst5 bits match AD1-AD5. RCV INT
is reset to one by fA or POR, or if the line is not active for 32
receive clocks.

TRANSMIT INTERRUPT

TXINT

TRANSMIT INTERRUPT is set to zero when the 6th bit following a
command sync ~ a one, and thefirst5 bits match AD1-AD5. TXINT is
reset to one by IA or POR.

COMMAND SYNC

CMD SYN

COMMAND SYNC is an input from the Manchester decoder and
must be high for 16 receive clocks enveloping the receive NRZ data
of a command word.

DATA SYNC

DTA SYN

DATA SYNC is an input from the Manchester decoder and must be
high for 16 receive clocks enveloping the receive NRZ data of a
data word.

RECEIVER NRZ

RCV NRZ

Receiver serial inputfrom Manchester decoder. Data must bestable
during the rising edge of the receive clock.

STATUS WORD
ENABLE

SWE

SWE is the output enable for the following open drain outputs:
0MF
0WF
IVWF
DTA AVL
DTARQ
MSG CPLT

POWER ON RESET

POR

POWER ON RESET. Active low for reset.

INTERRUPT ACKNOWLEDGE

RECEIVE CLOCK

VALID WORD

INT, REC INT, 0MF, 0WF and BRD CST. iA may occur
between the trailing edges of receive clocks 6 and 10, orbetweenthe
leading edge of receive clock 12 and the falling edge of receive clock
15, or after the falling edge of clock 17.

fA resets TX

RCV CLK

The RECEIVE CLOCK is synchronous with the Receiver NRZ input
during the command sync or data sync envelopes.

This input is driven by the VALID WORD output of the Manchester
Decoder. VW should occur immediately after the rise of the first
RCV CLK following the fall DATA SYNC or COMMAND SYNC.

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

NAME

SEND DATA

DATA REQUEST

MESSAGE COMPLETE

SYMBOL

FUNCTION

SEND DATA is a "handshake" signal received from the Manchester
encoder indicating that the encoder is ready for the COM 1553A to
transmit data. SD will bracket 16 transmit data clocks. The contents
of the transmitter buffer will be transferred into the transmit register
when SD is low.

DTA RQST

DATA REQUEST is an open drain output which is set high when
the transmitter holding register is ready to accept more data.

MSG CMPLT

In the receive mode the MESSAGE COMPLETE output is set low
when the appropriate nlJmber of data words have been received. In
the transmit mode. MSG CMPLT indicates that the appropriate
number of command. status or data words have been transmitted.
When the COM 1553A is a bus controller. MSG CMPLT will be
asserted low when 33 command status or data words have been
transmitted. MSG CMPLT is an open drain output.

TRANSMIT ENABLE

TXENA

A TRANSMIT ENABLE signal will be sent to the Manchester
Encoder to initiate transmission of a word. TXENA is generated
under thefollowing conditions:
1) COM 1553A is a bus controller: A TXMODE pulse will setTXENA.
A second TXMODE pulse will reset TXENA.
2) COM 1553A is a remote terminal. A Transmit Command from the
Controller will cause a TRANSMIT INTERRUPT (see pin 6). When
this is acknowledged by a TXMODE pulse from the system. TXENA
will beset.
TXENA will then be reset by either
A) Send Data Command associated with the last data word.
B) a second TXMODE pulse.
3) COM 1553A is a remote terminal. The falling edge of a DATA
SYNC associated with the last data word of a message while in the
receive mode. TXENA will be reset during the next SEND DATA
envelope.

TRANSMIT CLOCK

TXCLK

Transmitter shift clock.

TRANSMIT NRZ

BUS CONTROLLER

TRANSMIT MODE

24-31
32

33-37

XMIT NRZ
BC

Serial data output to the MancheSter Encoder.

Be determines whether the COM 1553A is acting as bus controller
(BC = 0) or as a remote terminal (BC = 1).

TXMODE

TXMODE is a system input controlling transmi.ssion. See TXENA
(pin 18).

TAKE DATA ENABLE

TDE

TDE is an input from the system initiating transmission. Two TDE
pulses are required for each 16 bit data word. one for each 8 data
bits placed on D0-D7.

DATA BUS

D0-D7

Bidirectional 8 bit Data Bus to the system. D0 is the LSB. D0-D7
present open drain outputs.

READ DATA ENABLE

RDE

RDE is an input from the system instructing the COM 1553A to place
the received data onto D0-D7. Two RDE pulses are required per 16
bit data word. one for each 8 bits.

AD5-AD1

AD1-AD5 provide addressing to the COM 1553A. Each input has a
pull-up resister allowing simple switching to ground to select the
user address.

ADDRESS

POWER SUPPLY

BROADCAST

GROUND

VCC
BDCST
GND

+5 Volt supply.
BDCST is set low when a "broadcast" command word (th~address
bits all set to "one") is being received. BDCST is reset by IA.
Ground

OPERATION ... RECEIVE MODE
The COM 1553A is considered in the receive mode when
TXENA = O. The most significant bit of both command
and data words is received first.

If 32 clocks are received after the rising edge of CMD
SYN or DTA SYN an "Idle Line Reset" condition exists.
This implieS that a new CMD SYN or DTA SYN has not
yet been received within 16 clocks of the fall of the
previous sync signal. The "Idle Line Reset"will reset the
following signals:
REC INT
"0" MSG FLG
fXii'\j"T
"0" WRD FLG
BRD CST

Message reception is initiated when CMD SYN goes
high. The next 16 receive clocks are used to shift serial
data into RCV NRZ.
The first 5 bits of a command word designate a remote
terminal address. These 5 bits are compared with AD1-5.
Should the address bits compare, the sixth bit is
examined. If it is a zero, a RECEIVE INTERRUPT is generated. If it is a one, a TRANSMIT INTERRUPT is
generated.
Bit fields 7-11 and 12-16 are examined for all zeros. All
zeros in bit field 7-11 denotes a "ZERO MESSAGE" and all
zeros in bit field 12-16 denotes a "ZERO WORD."
Receipt of a data word is indicated when DTA SYN
goes high.
When DTA SYN or CMD SYN goes low, the.contents of
the 16 bit receive register are loaded into the receive
buffer. The buffer is organized into two groups of 8 bits
each. The most significant 8 bits (byte 1) will be enabled
onto the 8 bit data bus on receipt of the first RDE pulse
(RDE1). The second byte will be enabled on receipt
of the second RDE pulse (RDE2).

When the commanded number of data words have been
received, a MESSAGE COMPLETE signal is generated.
As the transmitter and receiver registers operate
independently, the COM 1553A will receive its own
transmission. The following signals are inhibited duriJ;lg
transmission:

A DATA AVAILABLE is generated for data words only.
However, data will be available on D0-D7 for both command and data words.

BC =0

RECINT
XMT INT
BRD CST
0WF
0MF
JAM MESSAGE ERROR*

DAT AVL
IVWF
RECINT
XMTINT
0MG
'lJ.NF
BRD CST
JAM MESSAGE ERROR*

*JAM MESSAGE ERROR is an internal signal. See
OPERATION ... TRANSMIT MODE.

OPERATION ... TRANSMIT MODE
The COM 1553A is considered in the transmit mode
when TXENA = 1. This is caused by a TXMODE pulse
(see description of pin functions, pin 18). The TXMODE
pulse in turn is a system response to a transmit
command from the receiver.

the least significant 2 bits of the first 8 bit byte, and a
TDE2 will load all 8 bits of the second byte. Note that
these TDE pulses must be sent (and data presented)
before the first SD = 1 response from the Manchester
Encoder.
A JAM ADDRESS occurs when 1) a transmit command
is addressed to the COM 1553A 2) A TXMODE pulse is
received and 3) a valid word signal is received. Upon a
JAM ADDRESS the COM 1553A will load its address into
the first 5 bits of the transmit register.
Alternatively, a JAM ADDRESS will also occur at the
fall of the last data sync after valid receive command
has been detected.
The JAM ADDRESS function will be inhibited if a "0"
word and "0" message condition exists in the command
word. The JAM ADDRESS will be reset by the leading
edge of SEND DATA.
The JAM MESSAGE ERROR function occurs when, in
the receive mode, a data word isnot followed by a
VALID WORD signal. JAM MESSAGE ERROR consists
of loading a one in the sixth bit location of the transmit
shift register (the message error location).

When the Manchester Encoder receives TXENA = 1, it
will respond with SEND DATA = 1. The COM 1553A will
then send the system a DATA REQUEST.
Data is loaded into the transmitter data buffer from the
8 bit data bus by pulsing TDE. The 8 most significant
bits are loaded in by the first TDE pulse (TDE1), the 8
least significant bits by the second TDE pulse (TDE2).
When SEND DATA (pin 15) is low, the transmitter shift
register inputs will follow either the transmit buffer
output, JAM ADDRESS or JAM MESSAGE ERROR signals. When SEND DATA is high, the shift register parallel
inputs are disabled and the shift register contents are
shifted out in NRZ form using the 16 negative edges in
the send data envelope.
To facilitate transmission of the status word from a
remote terminal, the COM 1553A will "jam" the first
(most significant) 6 bits of the status word into the
transmit register when BC is high. These bits will
automatically be sent at the first SEND DATA pulse. In
general for MIL-STD-1553A the remaining 10 bits will
normally be all zeros and will automatically be sent out
as such. If it is desired to send additional status
information (for MI L-STD-1553B), a TDE1 pulse will load

JAM MESSAGE ERROR is inhibited when the transmit
command word contains "0" Message and "0" Word
fields.
When the commanded number of data words has been
transmitted a MESSAGE COMPLETE signal will be
generated.

GENERAL OPERATION NOTES
1. BUS CONTROLLER. When BC = 0, signifying that the COM 1553A is the bus controller the following is true:
A. DTA AVL is generated on the rising edge of the 17th receive clock following a Command Sync or Data Sync. This
allows the bus controller to receive command, status or data words regardless of theiraddress.
B. TXENA is contingent only on ;l"XMODE. A bus controller can therefore transmit whenever it desires.
C. The jam functions are inhibited.
2. INVALID WORD FLAG. When BC = 0, IVWF will be set if the Valid Word input (from the Manchester decorder) does
not go high following receipt of all words. This includes words received from the same device's transmitter. (This
provides a validity test of the controller transmission).
When BC = 1, IVWF will be set if Valid Word does not go high following receipt of all command and address words
addressed to the terminal.
IVWF will be set for the following conditions:
Message type
Transit Group

Receive Group

Receive/Transmit
Group (this
terminal addressed
to receive)
Receive/Transmit
group (this terminal
addressed to
transmit)

IVWF generated
yes
no
no
yes
yes
no
yes
no
no
yes
no
no
yes
no
no
no

Terminal is
receiving
transmitting
transmitting
receiving
receiving
transmitting
receiving
receiving
receiving
receiving
transmitting
receiving
receiving
transmitting
transmitting
receiving

Word
Transmit command
Status word
Data word
Receive command
Data word
Status word
Receive command
Transmit command
Status word
Data word
Status word
Receive command
Transmit command
Status word
Data word
Status word

3. POWER ON RESET. During power-up, paR is a low to high exponential with a minimum low time, after the
supply is within specified limits, of 10 microseconds. paR may also occur asynchronously anytime after power
has stabilized.
paR initializes the following outputs:
0MG
0WF
BRD CST
XMT INT

RECINT
MSG CMPLT
IVW
ROE

TOE
DTA AVL
TXENA
DTA RQ

The following circuit may be used to implement paR.
TO OTHER SYSTEMS

10K

2mfd

I
IN914 or equiv.

4. WORD COUNT: Word count is decoded as follows:
01 02 03 04
o 0 0 0
o 0 0 1
1 1 1 1
o 0 0 0

05
1
0
1
0

Word Count
1
2
31
32

TRANSMIT TIMING FIGURE 1

1---18 --1-19--1- 20--1
TXCLK

TXENA

~
,--------~I~\------,

SEND DATA

XMITNRZ

____________1"1.0----16 transmit e'oeks------<.~I_ _ _ _ __
_

MSB

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ........................................................ -SsoC to +12SoC
Storage Temperature Range ......................................................... -Sso C to +1S0° C
Lead Temperature (soldering, 10 sec.) ......................................................... +32SoC
Positive Voltage on any Pin, with respect to ground .............................................. +8.0V
Negative Voltage on any Pin, with respect to ground .............................................. -0.3V

'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes
or "glitches" on their outputs when the AC power is switched on and off. I n addition, voltage transients on the
AC power line may appear on the DC output. If this possibility exists it is suggested thata clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA = -SsoC to 12SoC, Vee = +S ±S%, unless otherwise noted)
PARAMETER
DC CHARACTERISTICS
Input Voltage Levels
Low Level, VIL
, High Level, VIH
Output Voltage Levels
Low Level VOL
High Level VOH
Low Level VOL
Output Leakage, ILo
Input Current, AD1-ADS
Output Capacitance
Input Capacitance
Power Dissipation

MIN

TYP

MAX

UNIT

0.8

V
V

0.4

V
V
V

3.0
3.0

4.0
60
S
10

COMMENTS

IOL = -1.6 mA, except open drain
IOH = 100 fJA, except open drain
IOL = -1.6 mA, open drain output

0.4
10

fJA

10
2S
SOO

fJA VIN
pf
pf
mW

= OV

PARAMETER
AC CHARACTERISTICS
Clock Frequency
Clock Duty Cycle
Rise and fall t~~ l~b~DE
TXMODE,
,
rise and fall times, all
other inputs
receiver clock-NRZ
receiver clock-sync delay
receiver clock-VW delay
VW reset delay
transmit clock-TX ENA delay
TX ENA pulse width
transmit clock-send data set-up
transmit clock-send data hold time
transmit clock fall to NRZ
transmit clock rise to NRZ
TX MODE pulse width
TX MODE to TX ENA delay
VALID word to TX ENA delay
Data sync to TX ENA delay
TX ENA reset delay
DATA SET -up time
TDE pulse width
Data Hold time
Cycle time
DTA RQST Delay
Output Enable time
RDE Pulse width
receive cycle time
Flag delay time
Output disable time
SEND DATA delay
TDE off delay
TDE1'deiay
SYN toRDE
RDEtoSYN
Status word Enable
Status word Disable
Flag delay time
VW delay time
IVWF delay time
DTA AVL delay time
DTA RQST delay time
BRD CST delay time
BRD CST pulsewidth
flag reset delay
Interrupt delay
IA pulse width
Interrupt pulse width
Flag reset time
DTA A\(L reset delay
IVWF reset delay
MSG CMPLT turn-on delay
MSG CMPLT turn-on delay

SYMBOL

MIN

TYP

MAX

UNIT

N,tA

9S0
45

1000
50

1020
55

KHz

tr, tf

tr, tl
tRN
tSR
tRV
tvs
hx

50
65
S5
100
500

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

txw

hs
tST
hN
tNT
tMW
tMX
tvx
tDX
tsx
tD1
tD2
tD3
t~

tD5
tDS
tD7
tDa
tD9
tD10
tD11
tD12
tD13
tD14
to15
tSE
tSD
tCF
tcv
tCI
tCD
tSR
tRB
tBW
tlB
tRI
tlA
bw

25
60
40
140

a
95
150

750
750
750
750
100
150
100
450
450
100
150
450
450
100
2.5
1.5
500
500

16000

17000

,3.5

JJS
JJS
ns
ns

2.5
100
100
1
90
450
500
450
2
1
750
1.5

JJS
ns
ns

JJs
ns
ns
ns
ns

JJs
JJs
ns

JJs
ns

150
1

JJs

tFR
tRD
tllV
tMR
tMF

450
750
750
1.5
1.5

COMMENTS

ns
ns
ns

JJS
JJS

figure3B
figure3B
figure3B
figure3C
figure4A
figure4A
figure4B
figure4C
figure4B
figure4B
figure5A
figure5B
figure5B
figure5C
figure5C
figure6A
figure6A
figure6A
figure6A
figure6A
figure6B
figure6B
figure6B
figure6B
figure6B
figure6C
figure6C
figure6C
figure6D
figure6D
figure SA
figure SA
figureSB
figureSB
figureSB
figureSB
figureSC
figureSC
figureSD
figure SD, SE
figureSD
figureSD
figureSD
figure SF
figure SF
figure SF
figure 9A, 9B
figure9A,9C

RECEIVE TIMING FIGURE 2
RcvelK

.-------------~Ir\----------------~

CMD SYNC

.--------~\ !~-----------,

DATA SYNC

RNRZ

________

~_M_SB__

L __ _

____

_4I::~--~--~----~--lS-B~------

~------------------------~I~!----------------------------~'-=

RECEIVER INPUT TIMING FIGURE 3

TRANSMITTER TIMING FIGURE 4

Rev elK

TXCLK

COMMAND!
DATA SYNC

TXENA
~

f--'"

112 CLOCK CYCLE

!..

-.~

ANAZ

Rev elK

CMD/DATA SYNC

-,..

.--

TXCLK

- -

,..

,,,~

SEND DATA

_h.~

1--'.'_

XNRZ

3C
CMD/DATA SYNC

TXCLK

SEND DATA

TRANSMIT ENABLE (TXENA) TIMING FIGURE 5
SA

I II------,U

I_::;U:;=
TXENA

----------I.-x~-+I--~~

5B*
BC=1

R.g~~~T : I 51 61 71al 91101111121131141151161
*CMDSYNC

-t

1J.1Smin

TX MODE, NEGATIVE TRANSITION WILLI
OCCUR IN CROSS-HATCHED AREA.

I
I ~xxxxxxxx)l
I

-l I+- 1 J.IS min
VALID WORD

r-uI

II , - - - - - - \

l\-,.:!.I"""",,"O"

I
I

_ _ _ _ _ _ _ _ _ _ _ _-+l----Y.FO.6J.1S typ

1-1..

_ _ _ _ _ _ _ _ _ _ _-l---1...J:
TXENA
LAST DATA
SEND

I
I

i ~I"

----------~! ~

5C**

BC=1
DATA SYNC
RCV BIT TIMES

----.J

) ~
) ~

L-

I 1 I 2 I ~ ~ I 15

I H=
II
I

I
I
I

IDX-l

TXENA

~~
I
(rJ

SEND DATA

**THIS IS THE LAST DATA WORD BRING RECEIVED. THIS TERMINAL PREVIOUSLY
HAD RECEIVED A REC CMD WORD WITH OUR ADDRESS AND A REC/XMIT BIT =
DURING THIS MESSAGE SEQUENCE. TX ENABLE IS SET BY MSG CMPLT
FUNCTION AND RESET BY RECEIPT OF SEND DATA.

DATA BUS TIMING FIGURE 6

D~D7 ----K=========~B~IT~S~~~7========~r_------~------~========~B~IT~S~~~1~5========~r_--------DTA RQST

_Ioo~-+---I.~_""""'"

1+---------1.---------+1

-I.~

~D7 -------~==~BI~TS~~~7~~r-----------------------------_i==~B~IT~S~~~1~5==}_----------------------DTA AVL

IVW
_ I ........

...---!+-------I.--------!+---I,,-----<....- - - - - - " " - - - - - - . 1

IA RESETS FIGURE 7

DATA BUS TIMING FIGURE 6

TXENA
SEND DATA

,~,.,,

r--

It 12' 3 I 4 I 5 1617 I 8 t 91101111121131141151161171181191201

REC eLK

_______
,

l - '_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

CMDSYN~
BAD CST

TOE

~STATE

I 'fi5E1

r-,

STATE

111

II
"0" MSG FLG

. ,,-+I--loo,--1
"0" WRD FLG

NOTE: SEND DATA RISING EDGE INITIALIZES TDE TO TDE1 STATE
INVWFLG
OTA AVL

(DATASYNC=l)

TX INT OR AEC INT

IIII

kk:d
II I
, I
~III

IIII III
III
II III
11111

I~IIIII

I
I II

11111

I'~
II

I I !! !\ ji i i I i~bl
~,I---

-----------l'dl

II II

I
I 1
J

~ ------------~~~~1--1~~~~1--~~~~7

RISES FALLS

CMDSYN

RISES FALLS

@ill:;

FAllS

DTASYN

lA OCCURRING DURING ZONE A RESETS: BRD CST, TX INT, REC INT
lA OCCURRING DURING ZONE B RESETS: BRD CST, TX INT, REC INT, "0" MSG FLG,
lA OCCURRING DURING ZONE C RESETS: BRD CST, TX INT, REC INT, "0" MSG FLG,
''O''WRDFLG,

STATUS FLAGS FIGURE 8

L'---t.J-------;sbl-----

STATUS BITS

REC elK

o MSG FlG
rJ WRD FLG

vw
IVWF

DTA AVL

Notes: 1. SWE =0
_
2. IVWF and DTA AVL reset by RDE2 or REG elK 14 of the
next word

SEND DATA

DTARQ

REC eLK

80
TXINT, REC tNT

::~:~~g ~tg, ________...,r----=_t"_~
___________
}J

DTAAVl

IVWF

ROE

-----.~j"RDE2
If ROE Is not used to reset IVWF and RDE, then they are
reset by ReV elK 14 as shown below.

f+--t3---+--t4 ------1-+--15 ---+--'6---1
Rev eLK
DTA AVL

IVWF

~
t ..

MESSAGE COMPLETE FIGURE 9
BUS CONTROLLER MODE

~ ~rl--------------~IIr----------------l~
I:
- - - - - 1 I r - \_.....J\

MSG CMPlT

!-I

9A
SEND DATA

'----~il\-\-1'----

~~_____~\~rl.-.~I.-----

-----lr-I

HI.,

'WORD COUNTER IS PRESET TO 33
"MSG CMPlT SET I.. MAX AFTER RISE OF 33RD SEND
DATA PULSE

REMOTE TERMINAL, RECEIVE COMMAND RECEIVED
im

CMDSYNC

RCV ClK 16

LJl

DTA SYNC

,r-JI--/t..

MSG CMPlT

..I

'WORD COUNTER PRESET TO COUNT IN COMMAND WORD
"MSG CMPLT GENERATED BY lAST DATA SYNC OF
THE MESSAGE GROUP

REMOTE TERMINAL, TRANSMIT COMMAND RECEIVED
r------------~Irl---------------

BC~

CMDSYNC

RCV ClK

SEND DATA

~~I- - - - - - - - -

ul
I
I
I
I
I
I

r--1
11Jr---n~..-

-----ll

MSG CMP[T

t.,
'WORD COUNTER PRESET TO TRANSMIT COMMAND WORD FIELD
PLUS 1. THIS ALLOWS FOR THE STATUS WORD.
"MSG CMPLT GENERATED BY THE LAST SEND DATA OF
THE TRANSMIT MESSAGE GROUP.

TYPtCAL SY$T'EMOPERATtON

'SEE FIGURE 7 FOR ALLOWABLE TIMES TO SEND iA

OPEN DRAIN OUTPUT
FIGURE 10

INTERNAL LOGIC

DfI-D7 INPUTI OUTPUT
FIGURE 11
Vee

INTERNAL LOGIC

~
OTHER OUTPUTS
FIGURE 12
Vee

INTERNAL LOGiC

.-+--1

Circuit diagrams utilizing SMC products are included as a means of Illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checkad and is believad to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

COM1671
J,LPC FAMILY

Asynchronous/Synchronous Transmitter-Receiver

ASTRO
FEATURES
D SYNCHRONOUS AND
ASYNCHRONOUS
Full Duplex Operations
D SYNCHRONOUS MODE
Selectable 5-8 Bit Characters
Two Successive SYN Characters Sets
Synchronization
Programmable SYN and DLE Character
Stripping
Programmable SYN and DLE-SYN Fill
D ASYNCHRONOUS MODE
Selectable 5-8 Bit Characters
Line Break Detection and Generation
1-, 1112-, or 2-Stop Bit Selection
Start Bit Verification
Automatic Serial Echo Mode
D BAUD RATE-DC TO 1M BAUD
D 8 SELECTABLE CLOCK RATES
Accepts 1X Clock and Up To 4 Different
32X Baud Rate Clock Inputs
Up to 47% Distortion Allowance With 32X
Clock
D SYSTEM COMPATIBILITY
Double Buffering of Data
8-Bit Bi-Directional Bus For Data, Status,
and Control Words
All Inputs and Outputs TTL Compatible
Up To 32 ASTROS Can Be Addressed
On Bus
On-Line Diagnostic Capability
D ERROR DETECTION
Parity, Overrun and Framing

PIN CONFIGURATION
VBB
IACKI

iAcKb
FiPLY
iNTR
OALj/j
OAL1

DAL4
!iA[5
DA[![

!5A[7t
(n'm) el)[
~[

(Imnl) CEC
Mi$C[
{Vss)GNO[

1
2
3
4
5
6
7
8

'-'

10
9
0
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33

PVDD

32
31
30
29
28
27
26
25
24
23
22
21

R2
R1

PRE

PCA (1m)
BA (TSO)

Cii (em

l5B (1XTC)
DO (1XRC)
R4
R3

OF{~)

cc (trnIl)
B~

(ASI)

m3
104
105

mi
Il56
Vee

D COPLAMOS® n-Channel Silicon
Gate Technology
o Pin for Pin replacement for
Western Digital UC1671 and
National INS 1671
D Baud Rate Clocks Generated by
COM5036 @ 1X and
COM5016-6 @ 32X
APPLICATIONS
Synchronous Communications
Asynchronous Communications
Serial/Parallel Communications

General Description
The COM1671 (ASTRO) is a MOS/LSI device which performs the functions of interfacing a serial data communication
channel to a parallel digital system. The device is capable of full duplex communications (receiving and transmitting) with
synchronous or asynchronous systems. The ASTRO is designed to operate on a multiplexed bus with other bus-oriented
devices. Its operation is programmed by a processor or controller via the bus and all parallel data transfers with these
machines are accomplished over the bus lines.
The ASTRO contains several "handshaking" signals to insure easy interfacing with modems or other peripheral devices
such as display terminals. In addition, a programmable diagnostic mode allows the selection of an internal looping feature
which allows the device to be internally connected for processor testing.
The COM1671 provides the system communication designer with a software responsive device capable of handling
complex communication formats in a variety of system applications.

DAlBUS
CONTROL

COMMUNICATION
CHANNEl CONTROL

CLOCK
CONTROL

Organization
Data Access Lines - The OAL bus is an 8-bit bi-directional port over which all address, data, control, and status
transfers occur. In addition to transferring data and control words the OAL bus also transfers information
related to addressing of the device, reading and writing requests, and interrupting information.
Receiver Buffer - This 8-bit parallel register presents assembled received characters to ,the OAL bus when
requested through a Read operation.
Receiver Register - This 8-bit shift register inputs the received data at a clock rate determined by Control
Register 2. The incoming data is assembled to the selected character length and then transferred to the
Receiver Buffer with logic zeroes filling out any unused high-order bit positions.
Syn Register - This 8-bit register is loaded from the OAL bus by a Write operation and holds the synchronization
code used for receiver character synchronization. It serves as a fill character when no new data is available
in the Transmitter Buffer during transmission. This register cannot be read onto the OAL bus. It must be loaded
with logic zeroes in all unused high-order bits.
Comparator - The 8-bit comparator is used in the Synchronous mode to compare the assembled contents of
the Receiver Register and the SYN register or the OLE register. A match between the registers sets up
stripping of the received character, when programmed, by preventing the data from being loaded into the
Receiver Buffer. A bit in the Status Register is set when stripping is effected. The comparator output also enables
character synchronization of the Receiver on two successive matches with the SYN register.

OLE Register - This 8-bit register is loaded from the OAL bus by a Write operation and holds the OLE character
used in the Transparent mode of operation in which an idle transmit period is filled with the combination
DLE-SYN pair of characters rather than a single SYN character. In addition the ASTRO may be programmed to
force a single DLE character prior to any data character transmission while in the transmitter transparent mode.
Status Register - This 8-bit register holds information on communication errors, interface data register status,
match character conditions, and communication equipment status. This register may be read onto the DAL bus
by a Read operation.
Control Registers - There are two 8-bit Control Registers which hold device programming signals such as mode
selection, clock selection, interface signal control, and data format. Each of the Control Registers can be
loaded from the DAL bus by a Write operation or read onto the DAL bus by a Read operation. The registers are
cleared by a Master Reset.
Transmitter Buffer - This 8-bit parallel register holds data transferred from the DAL bus by a Write operation.
This data is transferred to the Transmitter Register when the transmitter section is enabled and the Transmitter
Register is ready to send new data.
Transmitter Register - This 8-bit shift register is loaded from the Transmitter Buffer, SYN register, or OLE
register. The purpose of this register is to serialize data and present it to the serial data output.

Astro Operation

Asynchronous Mode
Framing of asynchronous characters is provided by a Start bit (logic 0) at the beginning of a character
and a Stop bit(s) (logic 1) at the end of a character. Reception of a character is initiated on recognition
of the first Start bit by a positive transition of the receiver clock, after a preceding Stop bit(s). The Start
and Stop bits are stripped off while assembling the serial input into a parallel character.
The character assembly is completed by the reception of the Stop bit(s) after reception of the last
character bit (including the parity bit, if selected). If the Stop bit(s) is a logic 1, the character is
determined to have correct framing and the ASTRO is prepared to receive the next character. If the Stop
bit(s) is a logic 0, the Framing Error Status flag is set and the Receiver assumes this bit to be the Start
bit of the next character. Character assembly continues from this point if the input is still a logic 0 when
sampled at the theoretical center of the assumed Start bit. As long as the Receiver input is spacing, all
zero characters are assembled and error flags and data received interrupts are generated so that line
breaks can be determined. After a character of all zeroes is assembled along with a zero in the Stop
bit(s) location, the first sampled logic one is determined as a Stop bit and this resets the Receiver
circuit to a Ready state for assembly of the next character.
In the Asynchronous mode the character transmission occurs when information contained in the
Transmitter Buffer is transferred to the Transmitter Register. Transmission is initiated by the insertion
of a Start bit, followed by the serial output of the character (including the parity bit, if selected), then the
insertion of a 1,1.5, or 2 bit length Stop condition. If the Transmitter Buffer is full, the next character
transmission starts after the transmission of the Stop bit(s) of the present character in the Transmitter
Register. Otherwise, the Mark (logic 1) condition is continually transmitted until the Transmitter
Buffer is loaded.

Synchronous Mode
Framing of characters is carried out by a special Synchronization Character Code (SYN) transmitted
at the beginning of a block of characters. The Receiver, when enabled, searches for two contiguous
characters matching the bit pattern contained in the SYN register. During the time the Receiver is
searching, data is not transferred to the Receiver Buffer, status bits are not updated, and the Receiver
interrupt is not activated. After the detection of the firstSYN character, the Receiver assembles
subsequent bits into characters whose length is determined by the contents of Control Register 2. If,
after the first SYN character detection, a second SYN character is present, the Receiver enters the
Synchronization mode until the Receiver Enable Bit is turned off. If a second successive SYN character
is not found, the Receiver reverts back to the Search mode.
In the Synchronous mode a continuous stream of characters are transmitted once the Transmitter
is enabled. If the Transmitter Buffer is not loaded at the time the Transmitter Register has completed
transmission of a character, this idle time will be filled by a transmission of the character contained in
the SYN register in the Non-transparent mode, or the characters contained in the DLE and SYN registers
respectively while in the Transparent mode of operation.

Astro Operation
Receiver

The Receiver Data input is clocked into the Receiver Register by a 1X Receiver Clock from a modem
Data Set, or by a local32X bit rate clock selected from one of four externally supplied clock inputs.
When using the 1X clock, the Receiver Data is sampled on the positive transition of the clock in both
the Asynchronous and Synchronous modes. When using a 32X clock in the Asynchronous mode, the
Receiver Sampling Clock is phased to the Mark-To-Space transition of the Received Data Start bit and
defines, through clock counts, the center of each received Data bit with + 0%, -3% at the positive
transition 16 clock periods later.
In the Synchronous mode the Sampling Clock is phased to all Mark-To-Space transitions of the
Received Data inputs when using a 32X clock. Each transition of the data causes an incremental
correction of the Sampling Check by 1/32nd of a bit period. The Sampling clock can be immediately
phased to every Mark-To-Space Data transition by setting Bit 4 of Control Register 1 to a logic one,
while the Receiver is disabled.
When the complete character has been shifted into the Receiver Register it is transferred to the
Receiver Buffer; the unused, higher order bits are filled with logic zero's. At this time the Receiver
Status bits (Framing Error/Sync Detect, Parity Error/OLE Detect, Overrun Error, and Data Received)
are updated in the Status Register and the Data Received interrupt is activated. Parity Error is set, if
encountered while the Receiver parity check is enabled in the Control Registers. Overrun Error is
set if the Data Received status bit is not cleared through a Read operation by an external device when
a new character is transferred to the Receiver Buffer. This error flag indicates that a character has
been lost; new data is lost while the old data and its status flags are saved.
The characters assembled in the Receiver Register that match the content of the SYN or the
OLE register are not loaded into the Receiver Buffer, and the DR interrupt is not generated, if Bit 3 of
Control Register 2 (CR23) or Bit 4 of Control Register 1 (CR14) are set respectively, and SYN Detect and
OLE Detect are set with the next non SYN or non OLE character. When both CR23 and CR14 are set
(Transparent mode), the DLE-SYN combination is stripped. The SYN comparison occurs only with the
character received after the OLE character. If two successive OLE characters are received only the
first OLE character is stripped. No parity check is made while in this mode.

Transmitter

Information is transferred to the Transmitter Buffer by a Write operation. Information can be loaded
into this register at any time, even when the Transmitter is not enabled. Transmission of data occurs
only when the Request to Send bit is set to a logic 1 in Control Register 1 and the Clear To Send input is
logic O.lnformation is normally transferred from the Transmitter Buffer to the Transmitter Register
when the latter has completed transmission of a character. However, information in the OLE register
may be transferred prior to the information contained in the Transmitter Buffer if the Force OLE signal
condition is enabled (Bits 5 and 6 of Control Register 1 set to a logic 1). The control bit CR15 must be
set prior to loading of a new character in the Transmitter Buffer to insure forcing the OLE character
prior to transmission of the data character. The Transmitter Register output passes through a flip-flop
which delays the output by one clock period. When using the 1X clock generated by the Modem Data
Set, the output data changes state on the negative clock transition and the delay is one bit period.
When using a local32X clock the the transmitter section selects one of the four selected rate inputs and
divides the clock down to the baud rate. This clock is phased to the Transmitter Buffer Empty Flag
such that transmission of characters occurs within two clock times of the loading of the Transmitter
Buffer, when the Transmitter Register is empty.
When the Transmitter is enabled, a Transmitter interrupt is generated each time the Transmitter
Buffer is empty. If the Transmitter Buffer is empty, when the Transmitter Register is ready for a new
character, the Transmitter enters an idle state. During this idle time a logic 1 will be presented to the
Transmitted Data output in the Asynchronous mode or the contents of the SYN register will be
presented in the Synchronous Non-transparent mode (CR16 =0). In the Synchronous Transmit
Transparent mode (CR16 = 1), the idle state will be filled by DLE-SYN character transmission in that
order. When entering the Transparent mode OLE must precede the contents of the Transmitter Buffer.
This is accomplished by setting of Bit 5 of Control Register 1.
If the transmitter section is disabled by a reset of the Request to Send, any partially transmitted
character is completed before the transmitter section of the ASTRO is disabled. As soon as the Clear
To Send goes high the transmitted data output will go high.
When the Transmitter parity is enabled~ the selected Odd or Even parity bit is inserted into the last
data bit of the character in place of the last bit of the Transmitter Register. This limits transfer of
character information to a maximum of seven bits plus parity or eight bits without parity. Parity cannot
be enabled in the Synchronous Transparency mode.

Input/Output Operations
All Data, Control, and Status words are transferred over the Data Access Lines (DAL 0-7). Additional input
lines provide controls for addressing a particular ASTRO, and regulating all input and output operations. Other
lines provide interrupt capability to indicate to a Controller 'that an input operation is requested by the ASTRO.
All input/ output terminology below is referenced to the Controller so that a Read or input takes data from the
ASTRO and places it on the DAL bus, while a Write or Output places data from the DAL bus into the ASTRO.
A Read or Write operation is initiated by the placement of an eight-bit address on the OAL bus by the
Controller. When the Chip select signal goes to a logic 0 state, the ASTRO compares Bits 7-3 of the DAL bus
with its hard-wired ID code (Pins 17, 22, 24, 25, and 26) and becomes selected on a Match condition. The ASTRO
then sets its Fi'PLV line low to acknowledge Its readiness to transfer data. Bit 0 must be a logic 0 in Read or
Write operation. A setup time must exist between CS and the RE or WE signals to allow chip selection prior to
read/write operations.
Read
Bits 2-0 of the address are used to select ASTRO registers to read from as follows:
Blt82-0
Selected Regl8ter
000
Control Register 1
010
Control Register 2
100
Status Register
110
Receiver Buffer
When the Read Enable (RE) line is set to a logic 0 condition by the ControHer the ASTRO gates the contents
of the addressed register onto the DAL bus. The Read operation terminates, and the device becomes unselected,
when both the Chip Select and Read Enable return to a logic 1 condition. Reading of the Receiver Buffer clears
the Data Received Status bit. The data is removed from the DAL bus when the RE signal returns to the logic
high state.
Write
Bits 2-0 of the address are used to select ASTRO registers to be written into as follows:
Bits 2-0
Selected Register
000
Control Register 1
010
Control Register 2
100
SYN and DLE Register
110
Transmitter Buffer
When the Write Enable (WE) line is set to a logic 0 condition by the Controller the ASTRO gates the data
from the DAL bus into the addressed register. If data is written Into the Transmitter Buffer, the TBMT Status bit
is cleared to a logic zero.
The 100 address loads both the SYN and DLE re·gisters. After writing into the SYN register the device Is
conditioned to write into the DLE if followed by another Write pulse with the 100 address. Any intervening
Read or Write operation with other addresses or other ASTROs resets this condition such that the next 100 will
address the SYN register.
Interrupts
The following conditions generate interrupts:
Data Received (DR)
Indicates transfer of a new character to the Receiver Bufferwhile the Receiver is enabled.
Tran8miHer Buffer Empty (TBMT)
Indicates that the Transmitter Buffer is empty while the Transmitter is enabled. The first interrupt occurs when
the Transmitter becomes enabled if there is an empty Transmitter Buffer, or after the character is transferred
to the Transmitter Register making the Transmitter Buffer empty.
Carrier On
Indicates?0I1~

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STANDARD MICROS\ISTEMS
35M1tcusIlllid..~H.Y.11787

15161273-3100
WI! _ _ OI011 .......... SOllllOl1
_1WX-510·227-889B
_ oflQllS.

C;:ircuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore. such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and :upply the best product possible.

COM 1863
COM 8018
J.1PC FAMILY

Universal Asynchronous Receiver/Transmitter
UART
PIN CONFIGURATION
FEATURES

voo

o Compatible with TR1863 timing
o High accuracy 32X clock mode: 48.4375% Receiver Distortion

Immunity and improved RDA/ROR operation
High Speed Operation-62.5K baud, 200ns strobes
Single +5V Power Supply
Direct TTL Compatibility-no interfacing circuits required
Input pull-up options: COM 8018 has low current pull-up
resistors; COM 1863 has no pull up resistors
Full or Half Duplex Operation-can receive and transmit
simultaneously at different baud rates
Fully Double Buffered-eliminates need for precise external
timing
Improved Start Bit Verification-decreases error rate
046.875% Receiver Distortion Immunity
o Fully Programmable-data word length; parity mode; number
of stop bits: one, one and one-half, or two
o Master Reset- Resets all status outputs and Receiver Buffer
Register
Three State Outputs-bus structure oriented
Low Power-minimum power requirements
Input Protected-eliminates handling problems
Ceramic or Plastic DIP Package-easy board insertion
Baud Rates available from SMC's COM 8046, COM 8116,
COM 8126, COM 8136, COM 8146 baud rate generators

'HIACC
Gnd

mJE"
ROB
RO?
R06
ROS
R04
R03
R02
ROl
RPE
RFE
ROR

o
o
o
o
o
o
o

o
o
o
o
o

SWE
RCP
ROAR
ROA
RSI

TCP
POE
NOBl
NOB2
NSB
NPB
CS
TOB
TO?
T06
TOS
T04
T03
T02
TOl
TSO
TEOC

T15S
TBMT
MR

PACKAGE: 40-Pin D.I.P.

FUNCTIONAL BLOCK DIAGRAM
TOl T02 T03 T04 TOS T06 TO? TOB

TOS

TSO

GENERAL DESCRIPTION

TCP

The Universal Asynchronous ReceiveriTransmitter is an
MaS/LSI monolithic circuit that performs all the receiving and
transmitting functions associated with asynchronous data
communications. This circuit is fabricated using SMC's
patented COPLAMOS@ technology and employs depletion
mode loads, allowing operation from a single +5V supply. The
duplex mode, baud rate, data word length, parity mode, and
number of stop bits are independently programmable through
the use of external controls. There may be 5,6,7, or 8 data
bits, odd/even or no parity, and 1 or 2 stop bits or 1.5 stop bits
when utilizing a 5-bit code. These programmable features
provide the user with the ability to interface with all
asynchronous peripherals.

CS
NPB
NSB
NOB2
NOBl
POE

TEOC
SWE
TBMT
RPE
RFE
ROR
RDA
ROAR

Voo

I---'+-*-i HIACC'
Gnd

'If pin 2 is taken to a logic 1 the COM 1863 or the COM 8018 will
operate in a high accuracy mode. If pin 2 is connected to -12V,
GND, a valid logic zero, or left unconnected, the high accuracy
feature is disabled, and the UART will operate in a 16X clock
mode.

ROE

DESCRIPTION OF OPERATION - TRANSMITTER
commences. TEOCgoes low, TSO goes low (the
start bit), and TBMT goes high indicating that the
data in the data bits buffer register has been loaded
into the transmitter shift register and that the data
bits buffer register is available to be loaded with
new data.
If new data is loaded into the data bits buffer register
at this time, TBMT goes low and remains i n this state
until the present transmission is completed. One
full character time is available for loading the next
character with no loss in speed oftransmission. This
is an advantage of double buffering.
Data transmission proceeds in an orderly manner:
start bit, data bits, parity bit (if selected), and the
stop bit(s). When the last stop bit has been on the
line for one bit time TEOC goes high. If TBMT is
low, transmission begins immediately. If TBMT is
high the transmitter is completely at rest and, if
desired, new control bits may be loaded prior to the
next data transmission.

At start-up the power is turned on, a clock whose
frequency is 16 or 32 times the desired baud rate is
applied, and master reset is pulsed. Under these
conditions TBMT, TEOC, and TSO are all at a high
level (the line is marking).
When TBMT and TEOC are high, the control bits
may be set. After this has been done the data bits
may be set. Normally, the control bits are strobed
into the transmitter prior to the data bits. However,
as long as minimum pulse width specifications
are not violated, TDS and CS may o~cur simultaneously. Once the data strobe (TD ) has been
pulsed,the TBMT signal goes low, indicating that
the data bits buffer register is full and unavailable to
receive new data.
If the transmitter shift register is transmitting previously loaded data the TBMT signal remains low.
If the transmitter shift register is empty, or when it is
through transmitting the previous character, the
data in the buffer register is loaded immediately into
the transmitter shift register and data transmission

TRANSMITTER BLOCK DIAGRAM

CONTROL
STROBE

1t---1~--

DATA STROBE

TRANSMITTER
BUFFER
EMPTY
16X

32X

SERIAL
OUTPUT

CLOCK

ENDOF
CHARACTER
HIACC

DESCRIPTION OF OPERATION-RECEIVER
33/64 bit times (in the 32X mode, HIACC = 1), a
genuine start bit is verified. Should the line return
to a marking condition prior to a 1/2 bit time, the
start bit verification process begins again. A mark
to space transition must occur in order to initiate
s~art bit verification. Once a start bit has been
verified, data reception proceeds in an orderly
manner: start bit verified and received, data bits
received, parity bit received (if selected) and the
stop bit(s) received.

At start-up the power is turned on, a clock whose
frequency is 16 or 32 times the desired baud rate is
applied and master reset is pulsed. The data
available (RDA) signal is now low. There is one set
of control bits for both the receiver and transmitter.
Data reception begins when the serial input line
transitions for mark (high) to space (low). If the
RSI line remains spacing for 15/32 to 17/32 bit
times (in the 16X mode, HIACC = 0) or 31/64 to

If the received parity bit is incorrect, the parity
error flip-flop of the status word buffer register is
set high, indicating a parity error. However, if the
no parity mode is selected, the parity error flipflop is unconditionally held low, inhibiting a parity
error indication. If a stop bit is not received, the
framing error flip-flop is set high, indicating a fra.
ming error.
On the negative RCP edge preceding the stop-bit
center sample, internal logic looks at the data
available (RDA) signal. ~' al~his instant, the RDA
signal is high, or the D
signal is low, the

receiver assumes that the previously received
character has not been read out and the over-run
flip-flop is set high. The only way the receiver is
aware that data has been read out is by having the
data available reset low.
Subsequently the RDA output goes high indicating
that all outputs are available to be examined. The
receiver shift register is now available to begin receiving the next character. Due to the double buffered receiver, a full character time is available to
remove the received character.

RECEIVER BLOCK DIAGRAM
FRAMING
ERROR
PARITY ERROR
TRANSMITTER
BUFFER EMPTY

OVER RUN
DATA
AVAILABLE

BITS FROM
HOLDING _____________
CONTROL
REGISTER

J:::::::;:::::~~~~~==========~~::::l

SERIAL
INPUT

16X or 32X
CLOCK

HIACC--------L-------------------'

DESCRIPTION OF PIN FUNCTIONS

PIN NO.

SYMBOL

FUNCTION

NAME

VDO

Power Supply

+5 volt Supply

HIACC

High Accuracy
Mode

Enables 32X clock and improved RDA/ROR operation.
See NOTE on high accuracy mode.

GND

Ground

RDE

Received Data
Enable

A low-level input enables the outputs (RD8-RD1) of the
receiver buffer register.

5-12

RD8-RD1

Receiver Data
Outputs

These are the eight 3-state data outputs enabled by RDE.
Unused data output Ii nes, as selected by NDB1 and NDB2,
have a lOW-level output, and received characters are right
justified, i.e. the LSB always appears on the RD1 output.

RPE

Receiver Parity
Error

This 3-state output (enabled by SWE) is at a high-level if
the received character parity bit does not agree with the
selected parity.

RFE

Receiver Framing
Error

This 3-state output (enabled by SWE) is at a high-level if
the received character has no valid stop bit.

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

NAME

FUNCTION

ROR

Receiver Over
Run

This 3-state output (enabled by SWE) is at a high-level if
the previously received character is not read (RDA output
reset not completed) before the present character is
transferred into the receiver buffer register.

SWE

Status Word
Enable

A low-level input enables the outputs (RPE, RFE, ROR,
RDA, and TBMT) of the status word buffer register.

RCP

Receiver Clock

This input is a clock whose frequency is 16 times (16X) or
32 times (32X) the desired receiver baud rate.

ROAR

Receiver Data
Available Reset

A low-level input resets the RDA output to a low-level.

Ri5AR must have gone low and come high again before
ROR is sampled to avoid overrun indication.

RDA

Receiver Data
Available

This 3-state output (enabled by SWE) is at a high-level
when an entire character has been received and transferred
into the receiver buffer register.

RSI

Receiver Serial
Input

This input accepts the serial bit input stream. A high-level
(mark) to low-level (space) transition is required to initiate
data reception.

Master Reset

This input should be pulsed to a high-level after power
turn-on. This sets TSO, TEOC, and TBMT to a high-level
and resets R DA, RPE, RFE, ROR and R D1-R 08 to a low-level.

TBMT

Transmitter
Buffer Empty

This 3-state output (enabled by SWE) is at a high-level
when the transmitter buffer register may be loaded with
new data.

TDS

Transmitter
Data Strobe

A low-level input strobe enters the data bits into the
transmitter buffer register.

TEOC

Transmitter End
of Character

TSO

Transmitter
Serial Output

This output serially provides the entire transmitted
character. TSO remains at a high-level when no data is
being transmitted.

26-33

TD1-TD8

Transmitter
Data Inputs

There are 8 data input lines (strobed by TDS) available.
Unused data input lines, as selected by NDB1 and NDB2,
may be in either logic state. The LSB should always be
placed on TD1.

Control Strobe

A high-level input enters the control bits (NDB1, NDB2,
NSB, POE and NPB) into the control bits holding register.
This line may be strobed or hard wired to a high-level.

NPB

No Parity Bit

A high-level input eliminates the parity bit from being
transmitted: the stop bit(s) immediately follow the last data
bit. In addition, the receiver requires the stop bit(s) to follow
immediately after the last data bit. Also, the RPE output is
forced to a low-level. See pin 39, POE.

This output appears as a high-level during the last half
clock cycle of the last stop bit. It remains at this level
until the start of transmission of the next character or
for one-half of a TCP period in the case of continuous
transmission.

DESCRIPTION OF PIN FUNCTION
PIN NO.

SYMBOL

NAME

FUNCTION

NSB

Number of
Stop Bits

37-38

NDB2,
NDB1

Number of Data
Bits/Character

POE

Odd/Even Parity
Select

TCP

Transmitter
Clock

This input selects the number of stop bits. A low-level input
selects 1 stop bit; a high-level input selects 2 stop bits.
Selection of two stop bits when programming a 5 data bit
word generates 1.5 stop bits.
These 2 inputs are internally decoded to select either 5,6,7,
or 8 data bits/character as per the following truth table:
data bits/character
NDB2 NDB1
L
L
5
L
H
6
7
H
L
H
8
H
The logic level on this input, in conjunction with the NPB
input, determines the parity mode for both the receiver and
transmitter, as per the following truth table:
NPB POE
MODE
odd parity
L
L
H
even parity
L
H
X
no parity
X = don't care
This input is a clock whose frequency is 16 times (16X) or
32 times (32X) the desired transmitter baud rate.

TRANSMITTER TIMING8 BIT, PARITY, 2 STOP BITS

TRANSMITTER START-UP

TDS

~----------~~
IIII I II

TBMT

TSD

START BIT DETECT AND VERIFY

RECEIVER TIMING8 BIT, PARITY, 2 STOP BITS

~~A2I

RSI

III II II

ll-___-y,___'e_"-Jter,samPle

GENTER BIT
SAMPLE

minimum continuous low
required for start·bit verification

RECEIVER TIMING DETAIL
6
14

8
16

7
15

9
17

10
18

_16X

-32X

RCP
RDA
(HIACC
(HIA'::"CA= 1,:o_=-=-=-=--=-=--=-=-===-=-=-~1:;:=____________

=01:===========;-_--;____________

R~~:D8,
§
APE, RFE

_16X

_32X

RC~--'LrLSL-

.... -ID~T~a}~R~~1 STOP1 STOP 21 START

5
13

9
17

--'X"-o___________

____________

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ..................................................... 0° C to + 70° C
Storage Temperature Range .................................................... -55°C to +150° C
Lead Temperature (soldering, 10 sec.) ..................................................... +325° C
Positive Voltage on any Pin, with respect to ground ........................................... +8.0V
Negative Voltage on any Pin (except Pin 2), with respect to ground .......................... -0.3V
Negative Voltage on Pin 2, with respect to ground ......................................... -13.2V
Stresses above those listed may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or at any other condition above
those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system powersupplies, it is important
that the Absolute Maximum Ratings not be exceeded or device failure can result. Some
power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power is
switched on and off. In addition, voltage transients on the AC power line may appear on the
DC output..If this possibility exists it is suggested that at clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA = 0° C to 70° C, VDD = +5V ±5%, unless otherwise noted)

/0-0- __________ ,,_ .. _

------------------------------r-----r----,-----,----,---------I

Parameter

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, VIL
High-level, VIH
OUTPUT VOLTAGE LEVELS
Low-level, VOL
High-level, VOH
INPUT CURRENT
Low-level, IlL
INPUT LEAKAGE
OUTPUT CURRENT
Leakage,lLo
Short circuit, los"
INPUT CAPACITANCE
All inputs, CIN
OUTPUT CAPACITANCE
All outputs, COUT
POWER SUPPLY CURRENT
Icc
A.C. CHARACTERISTICS
CLOCK FREQUENCY
PULSE WIDTH
Clock
Master reset
Control strobe
Transmitter data strobe
Receiver data available reset
INPUT SET-UP TIME
Data bits
Control bits
INPUT HOLD TIME
Data bits
Control bits
ENABLE TO OUTPUT DELAY
Receive data enable
Status word enable
OUTPUT DISABLE DELAY

Min.

Typ.

Max.

Unit Comments/
"'_

0.8

V
V

0.4

V
V

300
±10

pA
(J.A

VIN = GND, COM 8018 only
COM 1863 only

±10
40

(J.A
mA

SWE = RDE = VIH, 0:5 VOUT:5 +5V
VOUT =OV

2.0
2.4

IOL= 1.6mA
10H = -100pA

SWE = RDE = VIH

All outputs = VOH, All inputs = VDD
= +25°C, See Timing Diagrams
MHz RCP, TCP
mA

1.0

0.45
500
200
200
200

(J.s

ns
ns
ns
ns

RCP, TCP
MR
CS
TDS
RDAR

0
0

ns
ns

TD1-TD8
NPB, NSB, NDB2, NDB1, POE

0
0

ns
ns

TD1-TD8
NPB, NSB, NDB2, NDB1, POE
Load = 20pf +1 TTL input
RDE: TpD1, TpDo
SWE: TpD1, TpDo
RDE, SWE

250
250
250

ns
ns
ns

"Not more than one output should be shorted at a time_
NOTES: 1. If the transmitter is inactive (TEOC and TBMT are at a high-level) the start bit will appear on the TSO line'within
1'12 clock period (TCP) after the trailing edge of TDS.
2. The start bit (mark to space transition) will always be detected within one RCP clock period, guaranteeing
a maximum start bit slippage of ±1/32 or ±1/64 of a bit time_
3_ The 3-state output has 3 states: 1) low impedance to VDb 2L1ow impedance to GND 3) high impedance OFF ""
10M ohms The "OFF" state is controlled by the SWE andliDE inputs.

DATAICONTROL TIMING DIAGRAM
VIH
VIL

TSET=X
V,H

DATA INPUTS
tr = .f=2O ns
TSET-UP 2:0
THOLO

VIL

2!O

~:: _

FTPW-===i,~

~~;T~__~__________________~______~

CONTROL INPUTS

NOTES ON COM 8018 AND COM 1883
HIGH-ACCURACY AND IMPROVED
RDAIROR MODE
The HIACC mode is enabled by applying Ii logic
"one" to pin 2. If this pin Is left unconnected, or
connected to GND, -12V, or a logic "zero," the
HIACC mode is disabled. The HIACC Input has an
internal pull-down resistor.
When the HIACC mode is selected, the TX and RX
halves both operate on 32X instead of 16X clocks.
Also, RDA is notched during the one half receiver
clock cycle preceding the stop bit center sample
when j:\D1-RD8 and ROR are changing.
Whether or not the HIACC mode Is selected, RDA
must be low and ROAR must have returned high to
avoid setting ROA. If ROAR is held low past the
stop-bit center sample, RDA will go high aiter ROAR
returns high.
The maximum current HIACC will supply If connected to -13.2V is 3.SmA.
.

"Inpul informalion (Dala/Conlrol) need onl~valid during
Ihe lasl Tpw, min lime of Ihe inpul slrobes (TOS, CS).

IMPROVED RDAIROR OPERATION
TIMING DIAGRAMS

OUTPUT TIMING DIAGRAM

" \RD1-RD8, and ROR determined
""

OUTPUTS
(RD1-RD8, RDA,
RPE, ROR, RFE, TBMT)

Stop bit center sample

VOH

RCP

VOL

RDA
NOTE: Waveform drawings nOllo scale for clarily.

E~~I---------

ADDITIONAL TIMING INFORMATION

ROR _ _ _ _ _

ROAR al last possible moment
and not gel ROR .

2OOno
~D1-R08,

and ROR determined
Slop-bit cenler sample

VOL
VOL

RCP

3OOno - - - - - - . ,

RDA

_
-9:

TCP~

ROR _ _ _ _ _...l

TCP

on•

TEOC

TSO-----"'\

RD1-RD8, and ROR determined

VOL

RCP
TCP

RDA

'---___...JI
...JI

L--_ _ _

ROR _ _ _ _ _..J

VOH

TBMT _________

..J.

Protection against missing the ROR flag

FLOW CHART- TRANSMlnER

FLOW CHART-RECEIVER

1. TURN POWER ON

2. PULSE MASTER RESET
3. SELECT BAUD RATE-16X or 32X elK

SET CONTROL BITS-PULSE CS

SET/RESET RFE
SET/RESET RPE

Circuit

diagr~ms utilizing SMC products are included as a means of illustrating typical semiconductor applica-

tions; consequently complete information sufficient for construction purposes is not necessarily given. The

devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and :upply the best product possible.

COM2502
COM2017
COM2502/H
COM2017/H
Universal Asynchronous Receiver/Transmitter
UART
Pin Configuration
FEATURES

Vee
Voo

D Direct TTL Compatibility- no interfacing circuits

Gnd

required

Im"E

D Full or Half Duplex Operation-can receive and
transmit simultaneously at different baud rates

D Fully Double Buffered-eliminates need for precise
external timing

D Start Bit Verification - decreases error rate
D Fully Programmable- data word length, parity mode,
number of stop bits; one, one and one-half, or two

D High Speed Operation-40K baud, 200ns strobes
D Master Reset- Resets all status outputs

ADB
AD7
AOB
ADS
AD4
AD3
AD2
AD1
APE
AFE
AOA
~
ACP
ADAR
ADA
ASI

TCP
POE
NDB1
NDB2
NSB
NPB
CS
'tDB
TD7
TD6
TDS
TD4
TD3
TD2
TD1
TSO
TEOC

TIm
TBMT
MA

PACKAGE: 40-Pin D.I.P.

D Tri-State Outputs - bus structure oriented
D Low Power- minimum power requirements

Functional Block Diagram

D Input Protected-eliminates handling problems

TD1 TD2 TD3 TD4 TDS TD6 TD7 TD8

D Ceramic or Plastic Dip Package-easy board insertion

TSO

TEOC
SWE

GENERAL DESCRIPTION

The Universal Asynchronous Receiver/Transmitter is
an MOS/LSI monolothic circuit that performs all the
receiving and transmitting functions associated with
asynchronous data communications. This circuit is
fabricated using SMC's P-channellow voltage oxidenitride technology. The duplex mode, baud rate, data
word length, parity mode, and number of stop bits are
independently programmable through the use of external controls. There may be 5, 6, 7 or8 data bits, odd/even
or no parity, and 1, or 2 stop bits or 1.5 stop bits when
utilizing a 5-bit code from the COM 2017 or COM 2017/H.
The UART can operate in either the full or half duplex
mode. These programmable features provide the user
with the ability to interface with all asynchronous
peripherals.

TBMT
APE
AFE
AOA
ADA
RDAA

Vee
VDD
Gnd

DESCRIPTION OF OPERATION- TRANSMITTER
At start-up the power is turned on, a clock whose
frequency is 16 times the· desired baud rate is
applied and master reset is pulsed. Under these
conditions TBMT, TEOC, and TSO are all at a high
level (the line is marking).
When TBMT and TEOC are high, the control bits
may be set. After this has been done the data bits
may be set. Normally, the control bits are strobed
into the transmitter prior to the data bits. However,
as long as minimum pulse width specifications
are not violated, fDS and CS man-g~cur simultaneously. Once the date strobe
) has been
pulsed the TBMT signal goes low, indicating that
the data bits buffer register is full and unavailable to
receive new data.
If the transmitter shift register is transmitting previously loaded data the TBMT Signal remains low..
If the transmitter shift register is empty, or when it is
through transmitting the previous character, the
data in the buffer register is loaded immediatelyinto
the transmitter shift register and data transmission

commences. TSO goes low (the start bit), TEOC
goes low, the TBMT goes high indicating that the
data in the data bits buffer register has been loaded
into the transmitter shift register and that the data
bits buffer register is available to be loaded with
new data.
If new data is loaded into the data bits buffer register
at this time, TBMT goes low and remains in this state
until the present transmission is completed. One
full character time is available for loading the next
character with no loss in speed of transmission. This
is an advantage of double buffering.
Data transmission proceeds in an orderly manner:
start bit, data bits, parity bit (if selected), and the
stop bit(s). When the last stop bit has been on the
line for one bit time TEOC goes high. If TBMT is
low, transmission begins immediately. If TBMT is
high the transmitter is completely at rest and, if
desired, new control bits may be loaded prior to the
next data transmission.

TRANSMITTER BLOCK DIAGRAM

CONTROL
STROBE

M----1~-- DATA STROBE

TRANSMITTER
BUFFER
EMPTY

16xT
CLOCK

SERIAL
OUTPUT

END OF
CHARACTER

DESCRIPTION OF OPERATION-RECEIVER
ing condition priortoa 1/2 bit time, the start bit verification process begins again. A mark to space
transition must occur in order to initiate start bit
verification. Once a start bit has been verified, data
reception proceeds in an orderly manner: start bit
verified and received, data bits received, parity bit
received (if selected) and the stop bit(s) received.
If the transmitted parity bit does not agree with the
received parity bit, the parity error flip-flop of the

At start-up the power is turned on, a clock whose
frequency is 16 ti mes the desired baud rate is applied
and master reset is pulsed. The data available (ADA)
signal is now low. There is one set of control bits for
both the receiver and transmitter.
Data reception begins when the serial input line
transitions from mark (high) to space (low). If the
ASIline remains spacing fora1/2 bittime,agenuine
start bit is verified. Should the line return to a mark-

status word buffer register is set high, indicating a
parity error. However, if the no parity mode is selected, the parity error flip-flop is unconditionally
held low, inhibiting a parity error indication. If a
stop bit is not received, due to an improperlyframed
character, the framing error flip-flop is set high,
indicating a framing error.
Once a full character has been received internal
logic looks at the data available (RDA) signal. If, at
this instant, the RDA signal is high the receiver
assu mes that the previously received character has

not been read out and the over-run flip-flop is set
high. The only way the receiver is aware that data
has been read out is by having the data available
reset low.
At this time the RDA output goes high indicating
that all outputs are available to be examined. The
receiver shift register is now available to begin receiving the next character. Due to the double buffered receiver, a full character time is available to
remove the received character.

RECEIVER BLOCK DIAGRAM
FRAMING
ERROR
ROB RD7 Roe RD5 RD4 ROO RD2 RDl

BITS FROM
CONTROL
HOLDING _____________
REGISTER

J:::::::;:::::~::~~~==========~~::::l

SERIAL
INPUT

16xR
CLOCK

DESCRIPTION OF PIN FUNCTIONS

PIN NO.

SYMBOL

NAME

FUNCTION

Vce

Power Supply

+5 volt Supply

Voo

Power Supply

-12 volt Supply

GND

Ground

ROE

Received Data
Enable

A low-level input enables the outputs (RD8-RD1) of the
receiver buffer register.

5-12

RD8-RD1

Receiver Data
Outputs

These are the 8 tri-state data outputs enabled by ROE.
Unused data output lines, as selected by NDB1 and NDB2,
have a low-level output, and received characters are right
justified, i.e. the LSB always appears on the RD1 output.

RPE

Receiver Parity
Error

This tri-state output (enabled by SWE) is at a high-level if
the received character parity bit does not agree with the
selected parity.

RFE

Receiver Framing
Error

This tri-state output (enabled by SWE) is at a high-level if
the received character has no valid stop bit.

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

NAME

FUNCTION

ROR

Receiver Over
Run

This tri-state output (enabled by SWE) is at a high-level if
the previously received character is not read (RDA output
not reset) before the present character is transferred into
the receiver buffer register.

SWE

Status Word
Enable

A low-level input enables the outputs (RPE, RFE, ROR,
RDA, and TBMT) of the status word buffer regjster.

RCP

Receiver Clock

This input is a clock whose frequency is 16 times (16X) the
desired receiver baud rate.

RDAR

Receiver Data
Available Reset

A low-level input resets the RDA output to a low-level.

RDA

Receiver Data
Available

This tri-state output (enabted by SWE) is at a high-level
when an entire character has been received and transferred
into the receiver buffer register.

RSI

Receiver Serial
Input

This input accepts the serial bit input stream. A high-level
(mark) to low-level (space) transition is required to initiate
data reception.

Master Reset

This input should be pulsed to a high-level after power
turn-on. This sets TSO, TEOC, and TBMT to a high-level
and resets RDA, RPE, RFE and ROR to a low-level.

TBMT

Transmitter
Buffer Empty

This tri-state output (enabled by SWE). is at a high-level
when the transmitter buffer register may be loaded with
new data.

TDS

Transmitter
Data Strobe

A low-level input strobe enters the data bits into the
transmitter buffer register.

TEOC

Transmitter End
of Character

This output appears as a high-Ieveleachtimea full character
is transmitted. It remains at this level until the start of
transmission of the next character or for one-half of a TCP
period in the case of continuous transmission.

TSO

Transmitter
Serial Output

This output serially provides the entire transmitted
character. TSO remains at a high-level when no data is
being transmitted.

26-33

TD1-TD8

Transmitter
Data Inputs

There are 8 data input lines (strobed by TDS) available.
Unused data input lines, as selected by NDB1 and NDB2,
may be in either logic state. The LSB should always be
placed on TD1.

Control Strobe

A high-level input enters the control bits (NDB1, NDB2,
NSB, POE and NPB) into the control bits holding register.
This line may be strobed or hard wired to a high-level.

NPB

No Parity Bit

A high-level input eliminates the parity bit from being
transmitted; the stop bit(s) immediately follow the last data
bit. In addition, the receiver requires the stop bit(s) to follow
immediately after the last data bit. Also, the RPE output is
forced to a low-level. See pin 39, POE.
:lJR

DESCRIPTION OF PIN FUNCTION
PIN NO.

SYMBOL

NAME

FUNCTION

NSB

Number of
Stop Bits

This input selects the number of stop bits. A low-level input
selects 1 stop bit; a high-level input selects 2 stop bits.
Selection of 2 stop bits when programming a 5 data bit word
generates 1.5 stop bits from the COM 2017 or COM 2017/H.

37-38

NDB2,
NDB1

Number of Data
Bits/Character

These 2 inputs are internally decoded to select either 5, 6, 7,
or 8 data bits/character as per the following truth table:
NDB2 NDB1
data bits/character
L
L
5
L
H
6
H
L
7
H
H
8

POE

Odd/Even Parity
Select

The logic level on this input, in conjunction with the NPB
input, determines the parity mode for both the receiver and
transmitter, as per the following truth table:
NPB POE
MODE
L
L
odd parity
L
H
even parity
X
H
no parity
X = don't care

Transmitter
Clock

This input is a clock whose frequency is 16 times (16X) the
desired transmitter baud rate.

TCP

TRANSMITTER TIMING-8 BIT, PARITV, 2 STOP BITS

TDS

TBMT

__________

~r--

TRANSMITTER START-UP
TCP

TDS
TSO

M---,
~
S

Upon data transmission initiation, orwhen6ttransmitting at 100% line utilization, the start bit will be placed
on the TSO line at the high to low transition of the TCP clock following the trailing edge of TOS.

RECEIVER TIMING-8 BIT, PARITY, 2 STOP BITS
RSI
CENTER BIT
SAMPLE
RDA"

~~-S

·· .. ·ID~T~a}~R~~1

STOP' STOP

----I /oE--- - -------- ----- - - -II

21 START

1/16 Bit time

RDA*'
·The ADA line was previously not reset (RDR = high-level).

·'The ADA line was previously reset (ROA:::: low-level).

START BIT DETECT/VERIFY
RCP
RSI

~~Beg;nVerifY

If the ASI line remains spacing for a 1/2 bit time, a genuine start bit is verified. Should the line return to a
marking condition prior to a 1/2 bit time, the start bit verification process begins again.

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ...................................................... 0° C to +70° C
Storage Temperature Range ................................................ ; ... -55° C to +150.° C
Lead Temperature (soldering, '0 sec.) ................ , ............... ; .................... +325°C
Positive Voltage on any Pin, Vcc ...•.....••..•••••••....••.........•••••.••.••••••.•.••.•••. +O.3V
Negative Voltage on any Pin, Vcc ............................................................. -25V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.

ELECTRICAL CHARACTERISTICS (TA = 0° C to 70° C, Vcc = +5V ±5%, Voo = -12V ±5%, unless otherWise noted)
Parameter
D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, VIL
High-level; VIH
OUTPUT VOLTAGE LEVELS
L.ow-Ievel, VOL
High-level, VOH
INPUT CURRENT
Low-level, ilL
OUTPUT CURRENT
Leakage,ILo
Short circuit, los"
INPUT CAPACITANCE
All inputs, CIN
OUTPUT CAPACITANCE
All outputs, COUT
POWER SUPPLY CURRENT
Icc

Min.

Typ.

Max.

Unit

0.8
Vcc

V
V

0.4

V
V

'.6

see note 4

""'"1
10

pA
mA

SWE = ROE
VOUT=OV

VIN =Vcc, f= 1MHz

SWE=RDE=VIH, f= 1MHz

28
28

mA
mA

Voo
Vcc-1.5

2.4

0.2
4.0

100

A.C. CHARACTERISTICS
CLOCK FREQUENCY
(COM2502, COM20i7)
(COM2502H, COM2017H)
PULSE WIDTH
Clock
Master reset
Control strobe
Transmitter data strobe
Receiver data available reset
INPUT SET-UP TIME
Data bits
Control bits
INPUT HOLD TIME
Data bits
Control bits
STROBE TO OUTPUT DELAY
Receive data enable
Status word enable
OUTPUT DISABLE DELAY

Conditions

IOL=1.6mA
IOH=100pA

== VIH, 0::;; VOUT::;; +5V

All outputs = VOH, All inputs = Vee

TA=+25°C
400
640

DC
DC
1
500
200
200
200

•

~O
~O
~O
~O

350
350
350

KHz RCp, TCP
KHz RCP, TCP
ps
ns
ns
ns
ns

Rt)AFi

ns
ns

TD1-TDB
NPB, NSB, NDB2, NDB1, POE

ns
ns

TD1-TD8
NPB, NSB, NDB2, NDB1, POE
Load =.20pf +1 TTL input
ROE: Tpo1, Tpoo
SWl::Tpo1, Tpoo
RDE,SWE

ns
ns
ns

RCp, TCP
MR
CS

TOS"

"Not more than one output should be shorted at a time.
NOTES: 1. If the transmitter is inactive (TEOC and TBM'r are sta high-level) the start bitwiUappearon the TSO line within
one clock period (TCP) after the trai ling edge of TOS.
2. The start bit (mark to space transition) will alWays be detected within one clock period of RCP. guaranteeing
a maximum start bit slippage of 1/16th of a bit time.
3. The tri-stateoutput has3 states: 1) 10wimpedancetoVcc ~impedancetOGND 3)high impedanceOFF5!!
10M ohms. The "OFF" state is controlled by the SWE and..
inputs.
.
4. Under steady state conditions nO currentflows for TTL or MOS interfacing. (COM 2502 or COM 2502IH)

DATA/CONTROL nMING DIAGRAII

TDS

DATA INPUTS

tr=H=20ns
TSET-UP2:0
THOLD 2:0

CONTROL INPUTS

*Input information (DatalControl) need only ~valid during
the last Tpw, min time of the input strobes (T , CS).

OUTPUT nMING DIAGRAM

Outputs Disabled
OUTPUTS
(RD1-RD8, RDA,
RPE, ROR, RFE, TBMT)

VOH
VOL

TPOI, TpDO

NOTE: Wavefonn drawings not to scale for clarity.

ROAR
- - - - - . . 1 + - - - - 200ns - - _ _ . , . - - - -

V1L

TDS

TMBT
RDA

V1H

----------

1 + - - - - 300ns - - - - - + I

VOL

FLOW CHART-TRANSMITTER

FLOW CHART-RECEIVER

1. TURN POWER ON
2. PUL.SE EXTERNAL RESET
3. SEL.ECTBAUDRATE-1SlCClK

seT CONTROL BITS-PULSE CS

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

COM 2601

Universal Synchronous Receiver/Transmitter
USRT
FEATURES

PIN CONFIGURATION

o STR, BSC - Bi-sync and interleaved bi-sync
modes of operation
o Fully Programmable-data word length, parity

TBMT
TSO

o
o
o

o
o
o
o
o
o

.....,
Vee

mode, receiver sync character, transmitter
sync character
Full or Half Duplex Operation - can receive and
transmit simultaneously at different baud rates
Fully Double Buffered-eliminates need for
precise external timing
Directly TTL Compatible- no interface
components required
Tri-State Data Outputs- bus structure oriented
IBM Compatible-internally generatedSCR
and SCT signals
High Speed Operation-250K baud, 200ns
strobes
Low Power-300mW
Input Protected-eliminates handling problems
Dip Package-easy board insertion

Gnd

SCT
Voo
DBl
DB2
DB3
DB4
DB5
DB6
DB7
DBa
RR

1
2
3
4
5
6
7
8
9

RPE

10
11
12
13
14
15
16

SCR
TSS
TCP
TDS [

18
19
20

:~ cs

POE
NDBl
NPB
NDB2

38
37
38

RD1
RD2

33· RD3
32
RD4
RD5
RD6

30
31
29
28
27

RD7

RDB
ROR

RDA

25
24

ROE

RCP

22
21

RSI
1lSS

ROAR

PACKAGE: 4O-Pin D.I.P.

FUNCTIONAL BLOCK DIAGRAM
DB8 OB7 DB6 085 DB4 DB3 DB2 081

APPLICATIONS

OBi-Sync Communications

TDSr=2O _ _....

o Cassette 1/0
o Floppy Disk 1/0

T85

TIMING

AND
CONTROL

GENERAL DESCRIPTION

TRANSMITTER

The Universal Synchronous Receiver ITransmitter
is an MOS/LSI monolithic circuit that performs all
the receiving and transmitting functions .
associated with synchronous (STR, BSC, Bi-sync,
and interleaved bi-sync) data communications.
This circuit is fabricated using SMC's P-channel
low voltage oxide-nitride technology, allowing
all inputs and outputs to be directly TTL
compatible. The duplex mode, baud rate, data
word length, parity mode, receiver sync character,
and transmitter sync character are independently
programmable through the use of external
controls. The USR/T is fully double buffered and
internally generates the sync character received
an~ sync character transmitted Signals. These
programmable features provide the user with the
abilityto interface with all synchronous peripherals.

RR
RCP

SCR

RPE

ROR
RDA
ROAR

RSIr-~~
1

ROB AD7 R06 RDS R04 ROO ROO RD1

Vee

Voo

Gnd

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

NAME

FUNCTION

Vcc

Power Supply

+5 volt Supply

TBMT

Transmitter
Buffer Empty

This output is at a high-level when the transmitter data
buffer register may be loaded with new data.

TSO

Transmitter
Serial Output

This output serially provides the entire transmitted
character. This character is extracted from the transmitter
data buffer register provided that a TDS pulse occurs during
the presently transmitted character. If TDS is not pulsed,
the next transmitted character wi II be extracted from the
transmitter sync register.

GND

Ground

SCT

Sync Character
Transmitted

This output is set high when the character loaded into the
transmitter shift register is extracted from the transmitter
sync register, indicating that the TDS was not pulsed during
the previously transmitted character. This output is reset
low when the character to be transmitted is extracted from
the transmitter data buffer register. This can only occur if
TDS is pulsed.

Voo

Power Supply

-12 volt Supply

DB1-DB8

Data Bus Inputs

This 8 bit bus inputs information into the receiver sync
register under control of the RSS strobe, into the transmitter
sync register under control of the TSS strobe, and into the
transmitter data buffer register under control of the TDS
strobe. The strobes operate independently of each other.
Unused bus inputs may be in either logic state. The LSB
should always be placed on DB1.

ReceiverReset

This input should be pulsed to a high-level after power
turn-on. This resets the RDA, SCR, ROR, and RPE outputs
to a low-level. The transition of the RR input from a highlevel to a low-level sets the receiver into the search mode
(bit phase). In the search mode the serially received data bit
stream is examined on a bit by bit basis until asynccharacter
is found. A sync character is found, by definition, when the
contents of the receiver sync register and the receiver
shift register are identical. When this occurs the SCR output
is set high. This character is then loaded into the receiver
buffer register and the receiver is set into the character
mode. In this mode each character received is loaded into
the receiver buffer register.

RPE

Receiver
Parity Error

This output is a high-level if the received character parity
bit does not agree with the selected parity.

7-14

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

NAME

FUNCTION

SCR

Sync Character
Received

This output is set high each time the character loaded into
the receiver buffer register is identical to the character in
the receiver sync register. This output is reset low the next
time the receiver buffer register is loaded with a character
which is not a sync character.

TSS

Transmitter Sync
Strobe

A high-level input strobe loads the character on the DB1DB8 lines into the transmitter sync register.

TCP

Transmitter Clock

The positive going edge of this clock shifts data out of
the transmitter shift register, at a baud rate equal to the
TCP clock frequency.

TDS

Transmitter Data
Buffer Strobe

A high-level input strobe loads the character on the DB1DB8 lines into the transmitter data buffer register.

RSS

Receiver Sync
Strobe

A high-level input strobe loads the character on the DB1DB8 lines into the receiver sync register.

RSI

Receiver Serial Input

This input accepts the serial bit input stream.

RCP

Receiver Clock

The negative-going edge of this clock shifts data into the
receiver shift register, at a baud rate equal to the RCP
clock frequency.

RDAR

Receiver Data
Available Reset

A high-level input resets the RDA output to a low-level.

RDE

Received Data
Enable

A high-level input enables the outputs (RD8-RD1) of the
receiver buffer register

RDA

Receiver Data
Available

This output is at a high-level when an entire character has
been received and transferred into the receiver buffer
register.

ROR

Receiver OverRun

This output is at a high-level if the previously received
character is not read (RDA not reset) before the present
character is transferred into the receiver buffer register.

28-35

RD8-RD1

Receiver Data
Output

These are the 8 tri-state data outputs enabled by RDE.
Unused data output lines, as selected by NDB1 and NDB2,
have a low level output, and received characters are right
justified, i.e. the LSB always appears on the RD1 output.

36,38

NDB2,
NDB1

Number of Data
Bits

These 2 inputs are internally decoded to select either 5,6,7,
or 8 data bits/character as per the following truth table:
NDB2 NDB1
L
L
L
H
L
H
H
H

data bits/character
5
6
7
8

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

NAME

NPB

No Parity Bit

A high-level input eliminates the parity bit from being
transmitted. In addition, it is necessary that the received
character contain no parity bit. Also, the RPE output is
forced to a low-level. See pin 40, POE.

Control Strobe

A high-level input enters the control bits (NDB1, NDB2,
POE, and NPB) into the control bits register. This line may
be strobed or hard wired to a high-level.

POE

Odd/Even Parity
Select

The logic level on this input, in conjunction with the NPB
input, determines the parity mode for both the reciever and
transmitter, as per the following table:

FUNCTION

NPB
L
L
H

POE
L
H

MODE
odd parity
even parity
no parity
X = don't care

ADDITIONAL TIMING INFORMATION
(Typical Propagation Delays)
Transmitter

TCP
OUTPUT

--+---~~

VOH
VOL

OUTPUT
TBMT
SCT
TSO

TPDO

TPD1

Nil

2:0

1.0
1.0

1.5
1.0

TPDO

!w.

UNITS
ps
ps
ps

TPD1

Receiver

OUTPUT

VOH

OUTPUT

_VJl.L ___
TPDO

Ai5i\

Nil

ROR
RPE
SCR
RD1-RD8

2.0
2.0
2.0
2.5

1.0
2.5
2.5
2.5
2.5

UNITS
ps
ps
ps
ps
ps

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ............................................... O°C to +70°C
Storage Temperature Range ............................................. -55° C to +150° C
Lead Temperature (soldering, 10 sec.) .............................................. +325°C
Positive Voltage on any Pin, Vcc ..................................................... +0.3V
Negative Voltage on any Pin, Vcc .................................................... -25 V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
ELECTRICAL CHARACTERISTICS (TA = 0° C to 70° C, Vcc = +5V ±5%, VDD = -12V ±5%, unless otherwise noted)
Parameter
D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, VIL
High-level, VIH
OUTPUT VOLTAGE LEVELS
Low-level, VOL
High-level, VOH
INPUT CURRENT
Low-level, IlL
OUTPUT CURRENT
Leakage,lLo
Short circuit, los"
INPUT CAPACITANCE
All inputs, CIN
OUTPUT CAPACITANCE
All outputs, COUT
POWER SUPPLY CURRENT
Icc
IDD
A.C. CHARACTERISTICS
CLOCK FREQUENCY
PULSE WIDTH
Clock
Receiver reset
Control strobe
Transmitter data strobe
Transmitter sync strobe
Receiver sync strobe
Receiver data available
reset
INPUT SET-UP TIME
Data bits
Control bits
INPUT HOLD TIME
Data bits
Control bits
STROBE TO OUTPUT DELAY
Receive data enable
OUTPUT DISABLE DELAY

Min

Typ

VDD
Vcc-1.5

Unit

0.8

V
V

Vcc

0.2
2.4

Max

Conditions

0.4

V
V

1.6

see note 1

-1
10

p.A
mA

ROE = VIL, 0 :::;VOUT:::; +5V
VOUT=OV

VIN=VCC, f= 1MHz

RDE=VIL,f=1MHz

28
28

250

TA=+25°C
KHz RCP, TCP

4.0

10L= 1.6mA
10H = -1OOtiA

1All outputs = VOH

200
200
200
200

tis
tis
ns
ns
ns
ns

RCP, TCP
RR
CS
TDS
TSS
RSS

200

ROAR

>0
>0

ns
ns

DB1-DB8
NPB, NDB2, NDB1, POE

>0
>0

ns
ns

DB1-DB8
NPB, NDB2, NDB1, POE
Load = 20pf +1 TTL input
ROE: TpD1, TpDo
ROE

1
1

180
100

250

ns
ns

"Not more than one output should be shorted at a time.
NOTES:
1. Under steady state condition no current flows for TTL or MOS interfacing. A switching current of 1.6 mA
maximum flows during a transition of the input.
2. The three-state output has 3 states:
1) low impedance to Vcc
2) low impedance to GND
3) high impedance OFF '= 10M ohms
The OFF state is controlled by the ROE input.

DESCRIPTION OF OPERATION-RECEIVERlTRANSlllTTER
The input clock frequency for the receiver is set at
the desired receiver baud rate and the desired
receiver sync character (synchronous idle character) is loaded into the receiver sync register. When
the Receiver Reset input transitions from a highlevel to a Iow-fevel the receiver is set into the search
mode (bit phase). In the search mode the serially
received data bit stream is examined on a bit by bit
basis until a sync character is found. A sync character is found, by definition, when the contents of the
receiver sync register and the receiver shift register
are identical. When this occurs the Sync Character
Received output is set high. This character is then
loaded into the receiver buffer register and the
receiver is set into the character mode. In this mode
each character received is loaded into the receiver
buffer register. The receiver provides flags for R~
ceiver Data Available, Receiver Over Run, Receiver
Parity Error, and Sync Character Received. Full
double buffering eliminates the need for precise
external timing by allowing one full character time
for received data to be read out.
The input clock frequency for the transmitter is set

at the desired baud rate and the desired transmitter
sync character is loaded into the transmitter sync
register. Interna/Iogic decides if the character to be
transmitted out of the transmitter shift register is
extracted from the transmitter data register or the
transmitter sync register. The next character transmitted is extracted from the transmitter data register
provided that a Transmitter Data Strobe pulse
occurs during the presently transmitted character.
If the Transmitter Data Strobe is not pulsed. the next
transmitted character is extracted from the transmitter sync register and the Sync Character Transmitted output is settoa high level. Full double buffering eliminates the needfor precise external timing by
allowing one full character time to load the next
character to be transmitted.
There may be 5, 6, 7, or 8 data bits and oddIeven
or no parity bit. All inputs and outputs are directly
TTL compatible. Tn-state data output levels are
provided for the bus structure oriented signals.
Input strobe widths of 2OOns, output propagation
delays of 250ns, and receiver/transmitter rates of
250K baud are achieved.

FLOW CHART - TRANSMITTER

TURN powER. ON
SET CONTROL BITS-PULSE cs
SET SYNC CHARACTER ONTO THE DATA BUS-PULSE TSS
saECT BAUD RATE-TCP

LOAD TRANSMITTER SHIFT
REGISTER FROM TRANSMITTER
DATA REGISTER
SCT=O
TBMT=1

LOAD, TRANSMITTER, SHIFT
REGISTER,. FROM TRANSMITl"ER
SYNC REGISTER
SCT=1

Ft.OW CHART-RECEIVER

TURN POWER ON
SELECT CONTROL BlTS-1'IJLS£ CS
SET RECEIVER SYNCCHARAC"ER ONTO DATA BUS-PULSERSS
PULSERR -SETS RECE1VER INTO SEARCH MODE. RDA = -RDR = RPE = SCR = 0

SHIFT 1 BIT INTO THE RECEIVER SHIFT REGISTER

SET THE RECEIVER INTO THE CHARACTER MODE
SCR=l

LOAD THE RECENEO CHARACTER INTO THE RECEIVER BUFFER.REGISTER-RDA = 1
EXAMINE OUTPUTS. PULSE RDAR. RDA = 0
.IF DESIRED, SET NEW -RECEIVER SYNC CHARACTER ONTO DATA BUS-PULSE RSS

SHIFT 1 BITINTO THE RECEIVER SHIFT REGISTER

DO THE
CONTENTS OF THE
RECEIVER SHIFT -REGISTER
COMPARETOTHECQNTENTS

SET SOR = 1

OF l:HE-R,EOEIV£R

smc REGISTER
?

YES

USRT TIMING DIAGRAM
TCP

n __________ :
I
TBMT ________- ,
TDS------~~

nil.. Note 1
1
WIr----------------------------

~I----------------~·

Note 1

L - ._ _ _ _ _ _ _ _ _ _ _ _....

SCT ______________________~:r__,

L-----------~Ir_----------------~rf
I
TSO :='1-=--.1- _-L-_T_-r_-L- J_ 1. _1_-J- _-C_I_- I - -I -1-_-C_l_-J.-_-L~
,I
,

~ Sync Character

------+14----

Data Character

------+I

RCP

] -= C =1::::' I -= [

RSI

,...1
T ·h-h - -_I _-1-_ 1-+ r
- ...1 - r - - - -+ -

I+----- sync Character ~~: Data Character

~If

L,--1i I- -I - 1

-1- T

- -

1 Data Character

-l- -

RR~------------------~'--LI--rl----------~,--~I__~I----------~I~
I

"""::----+:___~I------------....jn Note f

ROAR ________________________

I
,
1
1
l i
L-----------------+----'t-r - J Note 3

ROR -----,

RPE

L...JL--I,•

_ .J

Note 3

-~
',-.---------------------I:~,r-I---j,.11-------------hlll
-p
Note 3

NOTE 1

I
I

-= =- ~r::::. TI -= =- -=- -=- -= -= -: : . ~ -=-~:

=1 c Jr =
The transmitter shift register is
loaded with the next character
at the positive clock transition
corresponding to the leading
edge of the last bit of the
current character on the TSO
output. TBMT is set high
approximately two microseconds after this clock transition.
If it is desired that the next
character be extracted from
the transmitter data register
the leading edge of the TOS
should occur at least one
microsecond prior to this
clock transition.

II -~

~ __________ ~

SCR --.,

RD1-8 _

I
1r--11

DAi

NOTE 2
In order to avoid an ROR
indication the leading edge of
the ROAR pulse should occur
at least one microsecond prior
to the negative clock transition
corresponding to the center
of the first bit after the last data
bit on the RSI input.

NOTE 3
The RCR, RPE, SeR and R01ROS outputs are set to their
correct levels approximately
two microseconds after the
negative clock transition
corresponding to the center of
the first bit after the last data
bit on the RSlinput. The ROA
output is set high atthe next
negative clock transition.
The solid waveforms correspond to a control register
setting of 5 data bits and a
parity bit. The dashed waveforms are for a setting of 6 data
bits and no parity bit.

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconducto~ applications·; consequently complete Information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

COM 2651*
COM 2651-1*
COM 2651-2*
jLPCFAMILY

Programmable Communication Interface.
PCI
FEATURES
D Synchronous and Asynchronous Full Duplex or

PIN CONFIGURATION

Half Duplex Operations

D Re-programmable ROM on-chip baud
D

rate generator
Synchronous Mode Capabilities
- Selectable 5 to 8-Bit Characters
- Selectable 1 or 2 SYNC Characters
-Internal Character Synchronization
- Transparent or Non-Transparent Mode
-Automatic SYNC or DLE-SYNC Insertion
-SYNC or DLE Stripping
- Odd, Even, or No Parity
- Local or remote maintenance loop back mode
Asynchronous Mode Capabilities
- Selectable 5 to 8-Bit Characters
-3 Selectable Clock Rates (1 X, 16X, 64X the
Baud Rate)
- Line Break Detection and Generation
-1, 1'h, or 2-Stop Bit Detection and Generation
- False Start Bit Detection
- Odd, Even, or No Parity
- Parity, Overrun, and framing error detect
- Local or remote maintenance loop back mode
- Automatic serial echo mode
Baud Rates
- DC to 1.OM Baud (Synchronous)
- DC to 1.OM Baud (1 X, Asynchronous)
- DC to 62.5K Baud (16X, Asynchronous)
- DC to 15.625K Baud (64X, Asynchronous)
Double Buffering of Data

D2 1

28 D1

D3 2
RxD 3

27 DO

GND 4

26 Vee
25 RxC

D4 5

24 DTR

D5 6

23 RTS

D6 7

22 DSR

D7 8

21 RESET

TxC 9
A110
CE11

AO 12
R/W13

RxRDY 14

20 BRCLK
19TxD
18 TxEMT/DSCHG
17CTS
16DCD
15 TxRDY
Package: 28-pin D.I.P.

D Internal or External Baud Rate Clock
D
D
D
D

-16 Internal Rates:50 to 19,200 Baud,or
45.5 to 38,400 for COM 2651-2
Single +5 volt Power Supply
TTL Compatible
No System Clock Required
Compatible with 2651, INS2651

GENERAL DESCRIPTION
The COM 2651 is an MaS/LSI device fabricated
Asynchronous Receiver/Transmitter (USART)
using SMC's patented COPLAMOS® technology
designed for microcomputer system data comthat meets the majority of asynchronous and
munications. The USART is used as a peripheral
synchronous data communication requirements,
and is programmed by the processor to comby interfacing parallel digital systems to asynmunicate in commonly used asynchronous and
chronous and synchronous data communication
synchronous serial data transmission techniques
channels while requiring a minimum of processor
including IBM Bi-Sync. The USART receives serial
data streams and converts them into parallel data
overhead. The COM 2651 contains a baud rate
generator which can be programmed to either
characters for the processor. While receiving serial
accept an external clock or to generate internal
data, the USART will also accept data characters
transmit or receive clocks. Sixteen different baud
from the processor in parallel format, convert them
rates can be selected under program control when
to serial format and transmit. The USART will signal the processor when it has completely received
operating in the internal clock mode. The on-chip
baud rate generator can be ROM reprogrammed to
or transmitted a character and requires service.
accommodate different baud rates and different
Complete USART status including data format
starti ng frequencies.
errors and control signals is available to the
The COM 2651 is a Universal Synchronous/
processor at any time.
'FOR FUTURE RELEASE

...ox

...J
0

0:
W

a:
W

...en en... ...
aw aw aen
w
a:
a:

0
u
w
...J
0

>
en

0:
W

a:
W

......

u
w
0:

C!l

I II

...a:Z

~l!i
0C!l

w
wa:
:::C!l
Wz
uwO
O:...J
0
J:

a:
W
wti;
>-C!l
Ww
ua:
::!t

:E
en

~
:E

V
...J
0
0:

~ffi

IOu.
<:

O:C!l::>z
o

u
0

...J
::;:0
wo:
0'"
oz

::;:8

c:5

~">.

><:

...J
U
0:
the primary
BOPmodeWllh a bit ncJAX dBtalength, CAe CClTT initiahedto all 1'5.
This output lndicatesthe status oil the TOP.. TXACT wiOgo hi!jh afterasserfiAg
0
TXENA andTSOM millSidenlly with the 'first TSObit TIIisolllpulwill reset one
half Clock after thebytedwlingwhiChTXENAisdropped.

Empty

TSA

TranlHRiller Status

Available
37

lXENA

Transmiller Enable

1'90

TransmilterSerial

TCP

OUtput
Tr.ansrMlerOiock

USB..

Thisi~8IlCIIp'Is1heserialbitlllputstream.

This output is set high. for 1 clock time of the
RCP. each time a sync or !lag Charader isreoeived.
1'his0UlpUt is asset:Ied lIIIIen the ADP presents the first d_ CharacteroUIIe
.messag& to tile contrOller. In the BOP mode the firstdalacharacteristhefirsl
non-flagcharader(addtessbyte).lntheOCPmode: 1. ifstrip-syncisset the
first non-synccharacteris thefirst data dulTacIer 2. if lIIrip-syIIc is not set; the
first data charaderis the character following the secondSYIIC.ln the BOP
mode 1he1railin,g ~R.AGresetsRXACT.lntheCCPmodeRXACT
isn_MHt,it can be deeredviaRXENA.
This output is set high when the RDP bas assetnbIed an entire character and
transfernid it into Ihe,/ADB. This output is reset by 18lIding the ROB.
ThisOUlpUt is set high: 1. CCP-in 1he event of receiwroverrun !ROR)
or parity_~ seIecIedl.2. BOP-in the event of ROR, ORe _
(ilsetected)

TIIisootpui is at a high teve1 when the 1'DB
ortheTX:StallilsandOolldrdRegist8rmaybeloadedwilh
the newdata.lBMT =0 on
write accesstoTDBor TX Status and
CoRoiI Register. T9MTftIlumshigh wilen the TDSRisloaded.
TEAR bit, indicating 1ransmitter'undeIfIow.
Reset by MR or lISSIII'IicInd TSOM.

an,

A~ teve1inpllltallowsthe'~d1ransmilter

data.
ThiS'OUIp\It is 'lhetmnsnlilledcharacter.

1iIaio_ _

TheposilivegmingedgeofthisdoCkshiltsdataOlllGf1he
IrlInSniiIIershillregisler.

Select

&temaIly RSI is disabled and 1SO=1.

IntemaII,RSlbeooIIIesTSOandRCP~ 'lCP.

Definition of Terms

RSOM
REOM
OB1.
DB11
)B12-14
OB15

ROR
A,B,C
EARCHK

Receiver Start 0I.Message-read anty bit. In BOP mode anty, goes high when first non-flag (address bytel
character loaded into ROB. II is cleared When the saoond byte is loaded into the ROB.
Receiver End 01 Messag8-f'88d only bit. In BOP mode only, set high when last byte of data loaded into ROB, or
when an ABORT cllarac:tar is received. It is cleared on reading of Receiver Status Register or dropping of RXENA.
Received ABORT or GO AHEAD character, reed only bit. In BOP mode only, if LM=O this bills set on ~ving an
ABORT character; if LM= 1 this bit is set on receiving a GO AHEAD character. ThIs is c::Iearad on reading 01
Receiver Status Register or dropping of RXENA.
Receiver Over RuI1-f'8ad only bil Set high when received data trallsfanad into ROB and p!Wious data has not
bean read, Indicating failure to SlllVice RCA within one character time. Cleared on reading 01 Rec:eiver Status
flegistar or dropping of RXENA.
Assembled Bit Count-.-d only bits. In BOP mode only, examine when REOM=1. ABC=O, massageterminatad
statad bOundaJy. ABC=XXX, message terminated (by FLAG or GA) on unstatad boundary, binary value of ABC
= number of valid bits available in ROB (right hand jusliliad).
Emir Check-raad only billn BOP set high if CRC selected and received in error, examine when REOM= 1. In
CCP mode: 1. set high JI parity selected and received in error, 2. if CRC seIec:Ied (tasted at end 01 each byte) ERR
CHI< = t if CRC GOOD, EAR CHK = 0 if CRC NOT GOOD. Controller mustdelerrnine the last byte 01 the

message.
088

0B9

DB1,

OB11
OB15

088-1'

OB11
0812
0813
DB14

0815

TransrniIter Start 01 ~/R bit. Provided TXENA-1, TSOM initiates start 01 message. In BOP, TSOM-1
generates FlAG and continues to send FlAG's until TSOM=O, then begin data. In CCP: 1. IDlE=O, transmit out 01
SYNC register, continue until TSOM=O, then begin data. 2.IDlE= 1 transmit out of TOB. In BOP mode Ihara is also
a Special Space Sequence 01 18-0's initiated by TSOM=1 and TEOM= 1. SSS is followed by FlAG.
TEOM
Transmit End of~W/R bil Used to terminate a message. In BOP mode, TEOM= 1 sends CRC, then
FlAG;ifTXENA=1 andTEOM=1 continue to send FlAG's, ifTXENA=O and TEOM=1 MARKline.lnCCP: 1.
IDlE=O, TEOM= 1 send SYNC, if TXENA= 1 and TEOM=1 continue to send SYNC's, if TXENA=O and TEOM=1
MARK line. 2.IDlE=1, TEOM=1, MARKIne.
TXAB
TransrnitterAbort-:W/Rbilln BOP mode only, TXAB=1 finish prasentcharacterthen: 1.IDlE=0, lransrniiABORT
2.101.E=1, transmit FlAG.
TXGA
Transmit Go Ahead-W/R bit. In BOP mode only, modifies charac:tar called for by TEOM. GA sent in place of FlAG.
Allows loop IIImIination-GA character.
TERR
TnmsmillerError-.-d only bit. Underflow, set high when TOB not loaded in !imato maintain continuous
transmission. In BOP automatically1ransmil: 1. IDLE=O, .ABORT 2. 10LE= 1, FlAG. In COP automatically transmit:
1.IDlE=0, SYNC 2. IDlE= 1, MARK. Cleared by TSOM.
X,Y,Z
Z
Y
X
-W/RbiIs. Thesa aratheerrorcontrol bits.
o
0
0
X'8+ X'2+ Xs + 1 CCITT-Initialize to "1"
o
II
1
X'"+ X'2+ xs+ 1 CCITT-Inilialize to "0"
o
1
0
Not.usec:I
o
1
1
)(18+ x t5 + X2+ 1-CRC16
1
0
0
Odd Parity--CCP Only
1
0
1
Even Parity-CCP Only
1
1
0
NotUsed
1
1
1
Inhibit all error detection and transmission
Note: Do not modify XYZ untI both data paths are ilia
IDLE
IDLE mode select-W/R bit. Affects transmiIter only. In BOP-'COIIIroIthe type of character sent when TXAB
asserted or in the event·of data undeIftow_ In CCP-controIs the method alinilial SYNC chaRIcter transmission and
underflow, "1" = transmit SYNCfrorn TDB., "O"=transmil SYNC·frorn SYNC/ADDRESS register.
SaoondaJy.Address Mode-WJR bit. In BOP mode only--afler FlAG looks for addrassmatch prior to activating
SEC ADD
ROP, if no match found, begin FlAGseerch again. SEC ADD bit should not be set if EXADD= 1 or EXCON= 1.
STRIP SYNC/lOOP Strip Sync or Loop Moda-W/R bit. Effects f8CIIiver only. In BOP mode-aIlowsrecognilionoi a GAcharactar.1n
CCP-rtersecand SYNC, strip SYNC; when firsI data characterdelacted, set RXACT=1, stop stripping.
PROTOCOL
PROTOCOl-W/flbit. BOP=O, CCP=1
"APA
All Parties Addrass-WlR ,bit. If selected, modlies saoondary mode so that the secondary address or 8-1 's will
TSOM

aclivatethe RDP.

OB13-15

TXDl

088-1.

RXDI..

DB11

0812

EXCON

Transmitter Data lengIh-W/R bits.
TXDl3 TXDl2 TXDU
lENGTH
o
0
0
Eigtrtbits percharactar
1
1
1
Sevenbitsper1lharacler
1
1
0
Six bits percharader
1
0
1
FIV8'bitspercharacter
1
II
0
Four bits percharacler*
o
1
1 Three bits per character·
o
1
0
Twobits per charac:Ier"
o
0
1 One bit per c:haracter"
·Fordata lenglhonly, notto·beusec:lfor SYNC character (CCP mode).
Receiver Data lengIh-WlRbiIs.
RXDl3 RXDl2 RXDl1
LENGTH
o
11
0
Eight bits per character
1
1
1
Sevenbitspercharacter
1
1
0
Six bilspercharacter
1
0
1 Rvebits per character
1
II
11 Foui"bilsperdlanldar
o
1
1 1"'-bits perdlanldar
o
1
,·0 Twobitspercharader
11
0
1 Onebil per dlaradar
Extended Control FIIiId--W/RbiI. In raceiveronly; if set, will receive controIliaId as two8-bil bytes. Exc:on bit should
nut be set if SEC ADD =1.
.
Extended Address Flllkl-W/Rbil In f8CIIiveronly; lSB 01 addrass·bym tasted for a "1".ft NO--conti_ JllC8iving
addrassbytes. ifYESgoinlD·controI,IiaIrlEXAOObiiShouldnutbe set if SEC ADD =1.

"Nota: Product manU'lactufed before 1Q79 may not have thisfeature.

Ii;

":!i

5!'
a; II:
Ii;

~g
.,0

i-g

F ..

Register Bit Assignment Chart 1
REGISTER
Receiver Data
Buffer
(Read OnlyRight JustifiedUnused Bits=O)
Transmitter Data
Register
(ReadlWriteUnused Inputs=X)'

DPfl7

DPfl6

Dpj5

DPIrJ4

DP83

DPJf1

DPfIfI

RD7

RDS

RD4

RD3

RD2

RD1

ROlf

Sync/Secondary
Address
(ReadlWriteRight JustifiedUnused Inputs=X)

SSA7

LSB

MSB

TD7

T06

TDS

TD4

TD3

TD2

TD1

LSB

MSB
SSA6

SSAS

SSA4

SSA3

SSA2

SSA1

SS~

LSB

MSB

DP13

DP12

DP11

DP1;

DPJ9

DPja

Receiver Status
(Read Only)

ERRCHK

ROR

RAB/GA·

REOM

RSOM

TXStatus
and Control
(Read/Write)

TERR
(Read Only)

O·

TXGA

TXAB

TeOM

TSOM

SEC ADD

IDLE

EXADD

EXCON

RXDL3

RXDt.:2

RXDL1

DP15

Mode Control
(ReadlWrite)

*APA

Data Length
Select
(ReadlWrite)

TXDL3

PROTOCOL STRIP
SYNC/
LOOP
TXDL2

TXDL1

• Note: Product manufactured before 1Q79 may not have this feature.

o
o

X
X
X

Register
Receiver Status Register and Receiver Data Buffer
Transmitter Status and Control Register and Transmitter Data Buffer
Mode Control Register and SYNC/Address Register
Data Length Select Register

X = don't care

2) BYTE OP = 1, data port 8 bits wide
A1
A'I
A2

o
o
o

Register
Receiver Data Buffer
Receiver Status Register
Transmitter Data Buffer
Transmitter Status and Control Register
SYNC/Address Register
Mode Control Register

o
Data Length Select Register

BOP TRANSMITTER OPERATION

CCP TRANSMITTER OPERATION

(PROCESSOR LOAD OR MASTER RESET)

(PROTOCOL

= 1; XYZ = CRC 16)

YES

CCP RECEIVER TIMING
RCP

~/SlJl.S\S~

~W/A=1

n~EAD

...J

--.JC

SFR

RDA

RSA

AXACT

L£ATA 1

READ

---"

~
~SYNC

RSI

W/R=O W/R=O

JlJLEAD

n~EAD

..J

~TX

s-LSL

----;Cl

_I "

SYNC----+-j

=r-

DATA 1

_---.J'-_

L-

ETX

1
1
1
1
1

W/R=O

NOTE 1
DPENA
(nol clock edge related)

RXENA

J~f

L
1
1

=:c= =c

CRC

1
1

j;"07E2

----lI

ROR

r -_ tII =

1__
NOTE 2

NOTE 3

---

ERR CHK
NOTE 1- Mode set for CCP with CRG selected
NOTE 2-11 overrun had occured-no READ STX
NOTE 3-ERR CHK must be sampled before nex.t byte or before AXENA brought low

())

-I>-

CCP TRANSMITTER OPERATION
TCP

TXENA

~~
lL___
I
I

-----',--NOTE 1
MODE SYNC

DPENA

T8MT

TSO

I
1I

II T50M::1
I

(not clock edge related)

"Lr

1
1

T50M::1

rf1--P'

FIRST SYNC

SENT

LOAD

TSOM:::O

LOAD
DATA 1

STX

~NOTE2--+-l

SECOND SYNC

LOAD

ETX

TEOM=1

SENT

r-y /s-rl

rJl-rl~

I
J

1
1

LJ
~SYNC

NOTE I-Mode is CCP with CRG selected
NOTE 2-Trailing edge of DPENA must occur at least one*half
clock pulse prior to TBMT=1 to avoid underrun

~
I

_I"

SYNC

~
_I

DATA

ETX

CRC

..--J

MARK

BOP RECEIVER TIMING

~ lSLJ~ u~

Rep

u#-u->Y' U
W/R=O
AddressByte

W/R=O
ReadStatus

not clock edge rela.1ed

RXENA.

~
777777:T77777T.7777i1-- FLAG •••

WBa

RS'

ULJ~L>Y'L~LJ-P'LJLrU

RDA

RSA

]

AXACT

~.LL

W/R=O
ConIroiByte

-+ .n. ~

W/R-'" 1

DPENA~

SFR

W/R,.,O
WfR=O
o.ta9yte#1 Data Byte #2

••• FLAG-----l

IControi
Byte

Data
Byte #1

---,0.;;'-:-

r=#4

sLJ

~FLAG

•••

LILflfi

~
~

S-~

RSCM

---.r-L

REOM

co
c.n

WIR=O
ReadStatus

---J:"L-

EEL l
~j HOTE2

_ _ _ _ __

W/R=O
OataByte#.

-.lL ~ .JL -1UL
,,
'--l __

I l

W/R=O
Data8yte#3

ERR,CHK, ABC,
ROR, AABlGA

r;'~E2

NOTE 1-11 required ~but not done In this example
NOTE 2-11 no OPENA to read Data Byte #2.

,r-----', __ _

___ 1

BOP TRANSMITTER OPERATION

~JUUtJlf
~>Y'LJLJL//JU//UlSl /.JUUL
, ,
r,
/,

TCP

...

TXENA~'"
TSOM=1

I:,
: : TSOM=O

~ress:

~NoIe'-I
not cIocM; edge related '
i

OPENA

I
TBMT

f{Zl

TXACT~

r--L

TSO~
Note 1-Trailing edge of OPENA must occur at least on&-haif clock
pulse prior to TBMT =1. To avoid underrun.

~01

Load

OataLengt1l

OataByte

fL ---.lL

Jly;--

TEOM=1

-.JL

J
~

Address Byte

~LAG"

Com'" Byte

[L8st Data Byte

---r::;::- CRCI

r---

~I~

.. -----l

MARK

AC TIMING DIAGRAMS

TCP~
TBMT

Hi---.!

R C P \'--_ _

I~o~r
RXACT

~j-

RDA.RSA ~

W/R=1

to Transmitter

' -_ _

DPENA

Registers

DPENA

W/R=O

to Receiver
Registers

' -_ _

300 ns

TBMT

RDA.RSA~

TCP

-=U==300

TSO

ns. min

Resets: RDP-RDA. RSA.
RXACT. receiver
into search
mode (for FLAG)
Note: Unless otherwise specified all times are maximum.

Data Port Timing

READ FROM USYNR/T

WUa
I.'----T.--.I-..-T-.o"-,,,-.-I..--T"-.I

t~~~WR_'1I//1/X

WRITE TO USYNR/T

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ...............................................................O°C to + 70°C
Storage Temperature Range ............................................................... - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................... + 325°C
Positive Voltage on any Pin, with respect to ground .....................................................+ 18.0V
Negative Voltage on any Pin, with respect to ground ..................................................... -0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transients on the AC power line may appear on the DC output. For example, the
bench power supply programmed to deliver + 12 volts may have large voltage transients when the
AC power is switched on and off. If this possibility exists it is suggested that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vce= +5V ±5%, Voo= + 12V±5%, unless otherwise noted)
Parameter
D.C. CharacteristiCS
INPUT VOLTAGE LEVELS
Low Level, VIL
High Level, VIH
OUTPUT VOLTAGE LEVELS
Low Level, VOL
High Level, VOH
INPUT LEAKAGE
Data Bus
All others
INPUT CAPACITANCE
Data Bus, CIN
Address Bus, CIN
Clock, CIN
All other, CIN
POWER SUPPLY CURRENT
Icc
100
A.C. Characteristics
CLOCK-RCP, TCP
frequency
PWH
PWL

t"tt

DPENA, TwoPENA
Set-up Time, TAs
ByteOp, W/R
A2, AI, Ao
Hold Time, TAH
Byte Op, WIR,
A2, AI, Ao
DATA BUS ACCESS, TOPA
DATA BUS DISABLE DELAY, Topo
DATA BUS SET-UPTIME, TOBS
DATA BUS HOLD TIME, TosH
MASTER RESET, MR

Min.

Typ.

2.0

Unit

0.8
Vee

V
V

0.4

IOL=1.6ma
IOH= 4O!La

50.0

!La
!La

0",VIN",5v, DPENA=·O orW/R=1
VIN=+5v

2.4
5.0

Commenta

Max.

pf
pf
pf
pI
70
90

ma
ma
TA=25°C

DC
325
325

1.5
10

250
0

50 !LS

MHz
ns
ns
ns
ns
ns
ns

150
100
0
100
350

ns
ns
ns
ns
ns

Receiver Data
and
Receiver Status
Access Sequence

_readl"9,.8I,,,.,,,,,..,',_lmAandfilSA.

NO
Y£S

BOP R,ECEIVEROPERATION

CCP RECEIVER OPERATION

PROCESSOR U'AJj)

OR'M.R.

TEST'MADE N=iJ!ER 8'RXCLKS

"RXCU

Clock Low Pulse Width

112

1.35
tcy-90

ns
ns

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

tR, tF

Clock Rise and Fall Time

tOTx

TxD Delay from Falling Edge oflXC

tSRx

Rx Data Set-Up Time to Sampling Pulse

tHRx

Rx Data Hold Time to Sampling Pulse

fTx

Transmitter Input Clock Frequency
1X Baud Rate
16X Baud Rate
64X Baud Rate

hpw

hPD

fRx

tRPW

tRPD

hxRDY

DC
DC
DC

kHz
kHz
kHz

Transmitter Input Clock Width
1X Baud Rate
16X and 64X Baud Rate

12
1

tCY
tCY

Transmitter Input Clock Pulse Delay
1X Baud Rate
16X and 64X Baud Rate

15
3

tCY
tCY

Receiver Input Clock Frequency
1X Baud Rate
16X Baud Rate
64X Baud Rate

DC
DC
DC

64
310
615

kHz
kHz
kHz

Receiver Input Clock Pulse Width
1X Baud Rate
16X and 64X Baud Rate

12
1

tCY
tCY

Receiver Input Clock Pulse Delay
1X Baud Rate
16X and 64X Baud Rate

15
3

tCY
tCY

TxRDY Pin Delay from Center of last Bit

hxROY CLEAR TxRDY I from Leading Edge of WR
tRxRDY

64
310
615

RxRDY Pin Delay from Center of last Bit

tRxRDY CLEAR RxRDY I from Leading Edge of RD

TEST CONDITIONS

tCy

Note 7

150

Note 7

tCY

Note 7

150

Note 7

tiS

Internal SYNDET Delay from Rising
EdgeofRxC

tCY

Note 7

tES

External SYNDET Set-Up Time Before
Falling Edge of RxC

tCY

Note 7

hxEMPTY

TxEMPTY Delay from Center of Data Bit

tCY

Note 7

twc

Control Delay from Risl!!.9....Edge of
WRITE (TxEn, DTR, RTS)

tCY

Note 7

tCR

Control to READSet-UpTime(DSR, CTS)

tCY

Note 7

NOTES: 1. AC timings m2sured VOH= 2.0, VOL=0.8, and with load circuit of Figure 1.
2. Chip Select (CS) and Command/Diiiii (C/D) are considered as Addresses.
3. Assumes that Address is valid before RD!.
4. This recovery time is for RESET and Mode Initialization. Write Data is allowed only when TxRDY = 1. Recovery Time between
Writes for Asynchronous Mode is 8 tCY and for Synchronous Mode is 16 tCY.
5. The TxC and RxC frequencies have the following limitations with respect to elK.
For 1X Baud Rate, frx or fAX $1/(30 tcv)
For 16X and 64X Baud Rate, frx or fAX $ 1/(4.5 tcv)
6. Reset Pulse Width = 6 tcv minimum; System Clock must be running during RESET.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
+20

2V
4200
1N914

Typical ~ Output
Delay Versus
~ Capacitance (pF)

6KO

+10

-10

f';PEC

Figure 1.

-2
-100

TEST LOAD CIRCUIT

113

-50

+50

"CAPACITANCE (pF)

+100

WAVEFORMS

System Clock Input

CLOCK <>

Transmitter Clock" Data

'fif 11. MOOEi

Til: 116xMODEi

Tx DATA

~
.

===x

______________

Receiver Clock" Data

RxDATA

RxC (lx MODE)

RxC (16x MODE)

INT SAMPLING

PULSE

114

Write Data Cycle (CPU - USART)

11---1~r---------------

TxRDY _ _ _ _~/

tTxRDY CLEAR

~ ------------------~~~I--------------

l-t

tow

----1:j two

_ _ _ _~O~O~N~'T~CA~R~E~_<=~~~~~--~O~O~N~'T~C~AR~E~DATA STABLE

DATA IN (D.B.)

------------__~

~r----------

~ --------------~~

~r-------

c/o

' - ________---T

Read Data Cycle (CPU

-'1

USART)

~r_------------

RxRoY _ _ _ _

I~'ROYCLEARI

Jtr-------

iiii -------------------.,:~

---lI

tRR-

l-tRO

l-toF

DATA OUT (o.B.1 _ _ _--E.OA~T~Ac':F:!!LO~A~T:......__ _+-t~~~~~>...!O~A~T~A~FL!:!:O~A:!.T

C/D

----------'--+-------t----'----

Write Control or Output Port Cycle (CPU - USART)

OTR,RTS ---------------~X
INOTE #1)
. ~.- - - - - -

I- tww -i
~

1_ tow

DATA IN 10.B.1

----------:-tl==ljc-------I-tAW

.../11

CIO _ _ _ _ _ _ _ _

t ------------twc =.j
::I two

----------------~~

_____________~I----

HtWA

1\'--______

tAW
~,rtW~A~----~~--------~y

NOTE #1: TWC INCLUDES THE RESPONSE TIMING OF A CONTROL BYTE.

115

Read Control or Input Port (CPU

DSR,CTS
(NOTE~1i

USART)

__________~,

~,__________~-------------------------

___
I-_'cR----"II- 'RR _1,--__
~
X
-ij 1- 'RD

DATA OUT

'OF

(0,8,)

CID ________________

tRAfI

JII

--I

'AR

I--

'RA

I--

-----------~~----------~y---NOTE #1: TCR INCLUDES THE EFFECT OF

ffi ON THE TxENBL CIRCUITRY.

Transmitter Control & Flag Timing (ASVNC Mode)

'T,EMPTY
Tx EMPTY

11J:------'"
I'----+--~

Tx READY

(PIN)

CID
WrSBRK

WR
Tx DATA
DATA CHAR 2

DATA CHAR 1

EXAMPLE FORMAT

DATA CHAR 3

7 BIT CHARACTER WITH PARITY & 2 STOP BITS.

Receiver Control & Flag Timing (ASYNC Mode)
,---<

BREAK DETECT

- r:-

OVERRUN ERROR

(STATUSBlT)
Rx ROY

'-------

~
CHAR 2

tR"ROY

LOST

1..--

RdOATA

c/o
WrERR

-drR>eEnt

V
I,J

W',RxEn!

RxE';t--

-v--

I,J

>---

RJ(OATA

DATA CHAR 1

DATA CHAR 2

DATA CHAR 3

EXAMPLE FORMAT'" 7 BIT CHARACTER WITH PARITY & 2 STOP 8ITS.

116

e-'-NM

BR-EAK

Transmitter Control & Flag Timing (SYNC Mode)

TH READY
(STATUS BIT!

READY

(PIN)

U-tj

MARKING STATE

Wr DATA

~ilOAf~
CHAR 1
11

EXAMPLE FORMAT

23'

WrDATA

CHAR 3

C~iR

23.

SYNC CHAR 2

...

012'

•

CHAR J
012

wrCOMMA~

AT~\

s !c\
CHAR 1
0'

W,COMMAND
SBRK,

W,OATA

DATA
CHAR 2

~'---

'---<

i,.--.

f\
W, DATA

r--<

_ I r - U-~L-

CID

OATA~

CHAR4

0123'

WrDATA

~5I~~

MARKING
STATE

SPACING
STATE

MAR
STATE

DATA
CHAR 5

, "

SYNC
CHAR

. ....

m
2

an CHARACTER WITH PARITY, 2 SYNC CHARACTERS

Receiver Control & Flag Timing (SYNC Mode)

SYNDET

(PIN) NOTE

---!

___________

SYNDEr (S,B)

------------------~'

-+______-+-+__-lUl.JUUU\.
)( " .)(],." x •

1 ,2]"3]"- :: 0 1 l

0 , ~2X1A-X: 0 1 2 3 _

0 1 2

1•

r~~-r~-+----

U,:-hlJ\,J

DATA
CHAR 3

CHAR2

'--r--

I--

EXIT HUNT MODE
SET SYNC DET

0 1 2 J

•

0 1 2 ]

)(

EXIT HUNT MODE
SET SYN DET (STATUS BITJ

NOTE "1 INTERNAL SYNC, 2 SYNC CHARACTERS, 5 BITS, WITH PARITY
NOTE ::2: EXTERNAL SYNC, 5 BITS, WITH PARITY

117

0 1

0(,

SET SYNDET (STATUS BIT)

APPLICATION OF THE COM8251A

Asynchronous Serial Interface to CRT Terminal,
DC to 9600 Baud

Synchronous Interface to Terminal or Peripheral Device

SYNCHRONOUS
TeRMINAL
OR PERIPHERAL

DEVICE

Asynchronous Interface to Telephone Lines

Synchronous Interface to Telephone Lines

...,NE

PHONE
LINE

LINE

INTER·

INTER·
FACE

SYNC
MOOEM

FACE

TELEPHONE

TELEPHONE'
LINE

COM8251A Interface to pP Standard System Bus

ADDRESS BUS

CONTROL BUS

i75R

i70W

RESET

DATA BUS

•
~
CIfl

D,-Do

II1f

II1II

RESET

CLK

-'"
~dCROSVSTEMS
we IIIIP_OIIIII'CDqIIIItIanSO'jlll canllllP_flf'j11115.

118

a·

'nAC~

CB! Display

TIMDJ'G COlf'l'llOLLBBB

CHAR A.CTEB GlIIlUIB.ATOBS

BOW BUFPlIIB

1 )For future release
2)Also available 'as CRT 8002A,B,C-OOl Katakana
CRT 8002A,B,C-003 5X7 dot matrix

be custom mask programmed
'Also available as CRT ?004A,B,C-003 5X?
dot matrix

(3)May
,4

119

120

CRT 5027
CRT 5037

CRT 5057*
f.,Lpc FAMILY
CRT Video Timer and Controller
VTAC®

ourmmnPtltfnn so you can keep ahead of yours.

FEATURES

PIN CONFIGURATION

o Fully Programmable Display Format
o

o
o

o
o
o
o
o
o
o
o
o

Characters per data row (1-200)
Data rows per frame (1-64)
Raster scans per data row (1-16)
Programmable Monitor Sync Format
Raster Scans/ Frame (256-1023)
"Front Porch"
Sync Width
"Back Porch"
I nterlace/ Non-I nterl ace
Vertical Blanking
Lock Line Input (CRT 5057)
Di rect Outputs to CRT Monitor
Horizontal Sync
Vertical Sync
Composite Sync (CRT 5027, CRT 5037)
Blanking
Cursor coincidence
Programmed via:
Processor data bus
External PROM
Mask Option ROM
Standard or Non-Standard CRT Monitor Compatible
Refresh Rate: 60Hz, 50Hz, ...
Scrolling
Single Line
Multi-Line
Cursor Position Registers
Character Format: 5x7, 7x9, ...
Programmable Vertical Data Positioning
Balanced Beam Current Interlace (CRT 5037)
Graphics Compatible

A2
A3
CS
R3
R2·
GND
R1
Ril
OS
LLIICSYN
VSYN
DCC

Voo
Vee
HSYN
CRY
BL
DB7
DB6
DB5

'--"
[ 1
2
3
[ 4
[ 5
[ 6
7
[ 8
[
10
C 9
0
[ 11
[ 12
[ 13
[ 14
[ 15
[ 16
17
18
19
20

39
38
37
36
35
34
33

32
31
30
29
28
27
26
25
24
23
22
21

H0
H1
H2

PH3
PH4
PH5

H6
H71DR5
DR4
DR3
DR2
DR1
DR0

P
P
PDB~
PDB1
PDB2
PDB3
DB4

PACKAGE: 40-Pin D.I.P.

o Split-Screen Applications

o
o
o
o
o
o
o

Horizontal
Vertical
Interlace or Non-Interlace operation
TTL Compatibility
BUS Oriented
High Speed Operation
COPLAMOS® N-Channel Silicon
Gate Technology
Compatible with CRT 8002 VDACTM
Compatible with CRT 7004

GENERAL DESCRIPTION
The CRT Video Timer and Controller Chip (VTAC)® isa user programmable40-pin COPLAMOS® nchannel MOS/LSI
device containing the logic functions required to generate all the timing signals for the presentation and formatting of
interlaced and non-interlaced video data on a standard or non-standard CRT monitor.
With the exception of the dot counter, which may be clocked at a video frequency above 25 MHz and therefore not
recommended for MOS implementation, all frame formatting, such as horizontal, vertical, and composite sync, characters
per data row, data rows per frame, and raster scans per data row and per frame are totally user programmable. Thedata row
counter has been designed to facilitate scrolling.
Programming is effected by loading seven 8 bit control registersdirectlyoffan8bitbidirectionaldata bus. Fourregister
address lines and a chip select line provide complete microprocessor compatibility for program controlled set up. Thedevice
can be "self loaded" via an external PROM tied on the data busas described in the OPERATION section. Formatting can also
be programmed by a single mask option.
In addition to the seven control registers two additional registers are provided to store the cursor character and data
row addresses for generation of·the cursor video signal. Tne contents of these two registers can also be read out onto the
bus for update by the program.'
Three versions of the VTAC® are available. The CRT 5027 provides non-interlaced operation with an even or odd
number of scan lines per data row, or interlaced operation with an even number of scan lines per data row. The CRT 5037
may be programmed for an odd or even number of scan lines per data row in both interlaced and non-interlaced modes.
Programming the CRT 5037 for an odd number of scan lines per data row eliminates character distortion caused by the
uneven beam current normally associated with odd field/even fieldinteJlacing of alphanumeric displays.
The CRT 5057 provides the ability to lock a CRT's vertical refresh rate, as controlled by the VTAC's® vertical sync
pulse, to the 50 Hz or 60 Hz line frequency thereby eliminating the so called "swim" phenomenon. This is particularly
well suited for European system requirements. The line frequency waveform, processed to conform to the VTAC's®
specified logic levels, is applied to the line lock input. The VTAC® will inhibit generation of vertical sync until a zero to
one transition on this input is detected. The vertical sync pulse is then initiated within one scan line after this transition
rises above the logic threshold of the VTAC.®
To provide tne pin required for the line lock input, the composite sync output is not provided in the CRT 5057.
'FOR FUTURE RELEASE

121

Description of Pin Functions
Pin No.
25-18

Input!
Output

Symbol

Name

DB~-7

Data Bus

3
CS
39,40,1,2 A¢-3
9

DCC

38-32

H~-6

7,5,4

RI-3

1/0

Chip Select
Register
JAddress
Data Strobe

H7/DR5

DOT Counter
Carry
Character
Counter Outputs
Scan Counter
Outputs
H7/DR5

Scan Counter LSB

26-30

DR~-4

17
15
11
10

BL
HSYN
VSYN
LLI

Data Row
Counter Outputs
Blank
Horizontal Sync
Vertical Sync
Composite Sync Outputl
Line Lock Input

CRV
Vee
Voo

Cursor Video
Power Supply
Power Supply

16
14
13

CSYNI

o
o

0
0
0
Oil

0
PS
PS

Function
Data bus. Input bus for control words from microprocessor or
PROM. Bidirectional bus for cursor address.
Signals chip that it is being addressed
Register address bits for selecting one of seven control
registers or either of the cursor address registers
Strobes DB¢-7 into the appropriate register or outputs the
cursor character address or cursor line address onto the data bus
Carry from off chip dot counter establishing basic character
clock rate. Character clock.
Character counter outputs.
Three most significant bits of the Scan Counter; row select
inputs to character generator.
Pin definition is user programmable. Output is MSB of
Character Counter if horizontal line count (REG.0) is ~128;
otherwise output is MSB of Data Row Counter.
Least significant bit of the scan counter. In the interlaced mode with an even number of scans per data row,
R0 will toggle at the field rate; for an odd number of
scans per data row in the interlaced mode, R0 will toggle
at the data row rate.
Data Row counter outputs.
Defines non active portion of t11:lrizontal and vertical scans.
Initiates horizontal retrace.
Initiates vertical retrace.
Composite sync is provided on the CRT 5027 and CRT 5037.
This output is active in non-interlaced mode only. Provides a true
RS-170 composite sync wave form. For the CRT 5057, this pin is
the Line Lock Input. The line frequency waveform, process~d to
conform to the VTAC'sl!l specified logic levels, is applied to this pin.
Defines cursor location in data field.
+ 5 volt Power Supply
+ 12 volt Power Supply

31.40.1,2
IEIIEf

::::.~======~;=~:E~~~~__________________~______~____________~~~~~________~
14

BLOCK DIA~RAM

122

13
+12v

GND

Operation
The design philosophy employed was to allow the device to interface effectively with either a microprocessor based or
hardwire logic system. The device is programmed by the user in one of two ways; via the processor data bus as part of the
system initialization routine, or during power up via a PROM tied on the data bus and addressed directly by the Row Select
outputs of the chip. (See figure 4). Seven 8 bit words are required to fully program the chip. Bit assignments for these words
are shown in Table 1. The information contained in these seven words consists of the following:
Horizontal Formatting:
Characters/Data Row

A 3 bit code providing 8 mask programmable character lengths from 20 to 132.
The standard device will be masked for the following character lengths; 20, 32,
40, 64, 72, 80, 96, and 132.

Horizontal Sync Delay

3 bits assigned providing up to 8 character times for generation of "front porch".

Horizontal Sync Width

4 bits assigned providing up to 15 character times for generation of horizontal
sync width.

Horizontal Line Count

8 bits assigned providing up to 256 ct'>aracter times for total horizontal formatting.

Skew Bits

A 2 bit code providing from a 0 to 2 character skew (delay) between the
horizontal address counter and the blank and sync (horizontal, vertical,composite)
signals to allow for retiming of video data prior to generation of composite video
signal. The Cursor Video Signal is also skewed as a function of this code.

Vertical Formatting:
Interlaced/Non-interlaced

This bit provides for data presentation with odd/even field formatting for interlaced systems. It modifies the vertical timing counters as described below.
A logic 1 establishes th~ interlace mode.

Scans/Frame

8 bits assigned, defined according to the following equations: Let X = value of 8
assigned bits.
1) in interlaced mode-scans/frame = 2X + 513. Therefore for 525 scans,
program X = 6 (00000110). Vertical sync will occur precisely every 262.5 scans,
thereby producing two interlaced fields.
Range = 513 to 1023 scans/frame, odd counts only.
2) in non-interlaced mode-scans/frame = 2X + 256. Therefore for 262 scans,
program X = 3 (00000011).
Range = 256 to 766 scans/frame, even counts only.
In either mode, vertical sync width is fixed at three horizontal scans (~ 3H).

Vertical Data Start

8 bits defining the number of raster scans from the leading edge of vertical
sync until the start of display data. At this raster scan the data row counter is
set to the data row address at the top of the page.

Data Rows/Frame

6 bits assigned providing up to 64 data rows per frame.

Last Data Row

6 bits to allow up or down scrolling via a preload defining the count of the last
displayed data row.

Scans/Data Row

4 bits assigned providing up to 16 scan lines per data row.

Additional Features
Device Initialization:
Under microprocessor control-The device can be reset under system or program control by presenting a 1010 address
on A3-f/. The device will remain reset at the top of the even field page until a start command is executed by presenting a 1110
address on A3-jil'.
Via "Self Loading"-In a non-processor environment, the self loading seguence is effected by presenting and holding the
1111 address on A3-0, and is initiated by the receipt of the strobe pulse (OS). The 1111 address should be maintained long
enough to insure that all seven registers have been loaded (in most applications under one millisecond). The timing
sequence will begin one line scan after the 1111 address is removed. In processor based systems, self loading is initiated by
presenting the jil'111 address to the device. Self loading is terminated by presenting the start command to the device which
also initiates the timing chain.
Scrolling-In addition to the Register 6 storage of the last displayed data row a "scroll" command (address Wll)
presented to the device will increment the first displayed data row count to facilitate up scrolling in certain applications.

123

Control Registers Programming Chart
Horizontal Line Count:
Characters/Data Row:

Total Characters/ Line = N + 1, N = 0 to 255 (DBO = LSB)
DB2 DB1
DBO
o
0
0
20 Active Characters/Data Row
o
0
1
32
o
1
0
40
o
1
1
64
1
0
0
72

1
1
Horizontal Sync Delay:
Horizontal Sync Width:
Skew Bits

0
1

1
0

80
96

1
1
1
132
= N, from 1 to 7 charactertimes (DBO = LSB) (N = 0 Disallowed)
= N, from 1 to 15 character times (DB3 = LSB) (N = 0 Disallowed)
Sync/Blank Delay
Cursor Delay
DB7 DB6
(Character Times)

o
o

0
o
1
1
1
2
1
1
2
2
8 bits assigned, defined according to the following equations:
Let X = value of 8 aSSigned bits. (DBO = LSB)
1) in interlaced mode-scans/frame = 2X + 513. Therefore for 525 scans,
program X 7' 6 (00000110). Vertical sync will occur precisely every 262.5
scans, thereby producing two interlaced fields.
Range = 513 to 1023 scans/frame, odd counts only.
2) in non-interlaced mode-scans/frame = 2X + 256. Therefore for 262
scans, program X = 3 (00000011).
Range = 256 to 766 scans/frame, even counts only.
In either mode, vertical sync width is fixed at three horizontal scans (= 3H).
N = .number of raster lines delay after leading edge of vertical sync of
vertical start pOSition. (DBO = LSB)
Numberofdata rows = N+1, N=Oto 63 (DBO=LSB)
N = Address of last dsplayed data row, N = 0 to 63, ie; for 24 data rows,
program N = 23. (DBO = LSB)
Register, 1,DB7=1 establishes Interlace.
Interlace Mode
CRT 5027: Scans per Data Row = N + 1 where N = programmed number of
data rows. N = Oto 15. Scans per data row must be even counts only.
CRT 5037, CRT 5057: Scans per data Row = N + 2. N = 0 to 14, odd or even
counts.
Non-Interlace Mode
CRT 5027, CRT 5037, CRT 5057: Scans per Data Row = N + 1, odd or
even count. N = 0 to 15.
1

Scans/Frame

Vertical Data Start:
Data Rows/Frame:
Last Data Row:
Mode:
Scans/Data Row:

DEi~I-t>q---_-------i*

... ..

SMC
CAT 5027, CAT 5037
or CAT 5057
VTAC@

DB7 ~Q---+-t+t-i-++p---(>t=::l

L..:fA''-TA,-,Ar'-OA;:..'_ _ _...J

Figure 4.

32x'8PROM

HARRIS HM-7602

5
SlOAO

OR EQUIVALENT

HAl 1----1---'

HA~

(from system:)

SELF LOADING SCHEME
FORVTAC® SET-UP

HA21-----"Hrl

t---t--HH

HA'I--+5

'---------'

ROW SELECTS
TO CHARACTER GENERATOR

124

0
0
0

0
0
1

Select/Command

Description

Load Control Register 0
Load Control Register 1
Load Control Register 2
Load Control Register 3
Load Control Register 4
Load Control Register 5
Load Control Register 6
Processor Initiated Self Load

0
1
0

See Table 1

Command from processor instructing
VTAC® to enter Self Load Mode (via external PROM)

Read Cursor Line Address
Read Cursor Character Address
Reset

Up Scroll

o 0

Load Cursor Character Address'
Load Cursor Line Address'
Start Timing Chain

Non-Processor Self Load

Resets timing chain to!Q[! left of page. Reset
is latched on chip by OS and counters are
held until released by start command.
Increments address of first displayed data
row on page. ie; prior to receipt of scroll
command-top line = 0, bottom line = 23.
After receipt of Scroll Command-top line =
1, bottom line = O.

Receipt of this command after a Reset or
Processor Self Load command will release
the timing chain approximately one scan line
later. In applications requiring synchronous
operation of more than one CRT 5027 the
dot counter carry should be held low during
the OS for this command.
Oevic~_~.ljll begin self load via PROM
when OS goes low. The 1111 command
should be maintained on A3-1Il long
enough to guarantee self load. (Scan
counter should cycle through at least
once). Self load is automatically terminated and timing chain initiated when the
all "1 's" condition is removed, independent of OS. For synchronous operation
of more than one VTAC®, the Dot Counter
Carry should be held low when the command is removed.

'NOTE: During Self-Load, the Cursor Character Address Register (REG 7) and the Cursor Row Address
Register (REG 8) are enabled during states 0111 and 1000 of the R3-R0 Scan Counter outputs respectively.
Therefore, Cursor data in the PROM should be stored at these addresses.
TABLE 1
BIT ASSIGNMENT CHART
HORIZONTAL LINE COUNT

REG_Ill I I
MODE: INTERLACEDI
NON INTERLACE,o
i

iII

H SYNC:: WIDTH

I~I

SKEW BITS

REG31

H SYNC DELAY

DATA ROWS/FRAME

ill I 51 I i I 101 REG6!......1.L. . . .L.-1~. .J. .I. . .LI. . . Li- -'I- 'I. :. . .J~1
SCAN LINES/FRAME

,...c';=:;::::::;=~i~;=;=;::::L,

REG"7I s l I 131 ~ I REG4171
'

SCANSIDATAROW

REG21 I~ I

CHARACTERSIDATAROW

LAST DISPLAYED DATA ROW

CURSOR CHARACTER ADDRESS

I I I ~ I REG?I ~ I

VERTICAL DATA START

I I I I I" I
CURSOR ROW ADDRESS

I; IITTI I REGslr;;=1:;::::::;::~'::::::r1==ilrl?:"'011 REGB!...-I. L. . . . L-I~-,-I.....!..I........i---,I~I~~q
125

AC TIMING DIAGRAMS

FIGURE 1 VIDEO TIMING

r--I--_---'"\-1,If- I

DOT COUNTER

IL---------------------------------------JI

CARRY

I~-----------~------IPWL------------------~-+-------PWH----~-~I

H¢-7
H SYNC, V SYNC, BLANK,
CURSOR VIDEO,
COMPOSITE SYNC
t-o----TDH 1

------,ol

FIGURE 2 LOAD/READ TIMING

Ds------------------------------------~

FIGURE 3 SCAN AND DATA ROW COUNTER TIMING

H SYNC------.J

-- -- -- -

-- -- -

t- -- -- -- \ 1 I r - - - - - - -

R8-3

IL ____ _

~TDEL 3 * -

*RI/l-3 and DRIIl-5 may change prior to the falling edge of H sync
CAT 5067 LINE LOCK
LINE LoeK IN
(60HZ, ~HZl

CRT 5057 LOGIC
.THRE$HOLD

+-' L...+_ _ _ _ _ _.lML..._ _ _ _ _ _ _-'

VERTtg-'J;.SYNC _ _ _ _

HSYNC

I
~~------~~i~·~~~~-------~--'-------------~·'L-----_______
LINE

LOCK

OUT

PROGRAM: SCANS/FRAME TO BE GREATER THAN fUNE~MlN.X H

126

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ...............................................................O°C to + 70°C
Storage Temperature Range .............................................................. - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................... +325°C
Positive Voltage on any Pin, with respect to ground .................................................... + 1B.OV
Negative Voltage on any Pin, with respect to ground .................................................... -0.3V
• Stresses above those listed may cause permanent damag~ to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
.
NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "'glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transient~ on the AC power line may appear on the DC output. For example, the
bench power supply programmed to deliver + 12 volts may have large voltage transients when the
AC power is switched on and off. If this possibility exists it is suggested that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vcc= +5V ±5%, Voo= + 12V ±5%, unless otherwise noted)
Parameter

Min.

Typ.

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level, V,L
High Level, V,H
Vcc-1.5
OUTPUT VOLTAGE LEVELS
Low Level-VOL for Rrl-3
Low Level-VOL all others
High Level-VoHfor RIIJ-3, DB0-7
2.4
High Level-VoH all others
2.4
INPUT CURRENT
Low Level, ilL (Address, CS only)
Leakage, IlL (All Inputs except Address, CS)
INPUT CAPACITANCE
Data Bus, C,N
10
DS, Clock, C,N
25
All other, C,N
10
DATA BUS LEAKAGE in INPUT MODE
IDe
POWER..,UPPLY CURRENT
Icc
BO
100
40
A.C. CHARACTERISTICS
DOT COUNTER CARRY
frequency
0.2
PWH
35
PWL
215
tr,tf
10
DATA STROBE
PWf5S
150ns
ADDRESS, CHIP SELECT
Set-uptime
125
Hold time
50
DATA BUS-LOADING
Set-uptime
125
Hold time
75
DATA BUS-READING
TOEL2
TOEL4
5
OUTPUTS: Hrl-7, HS, VS, BL, CRV,
CS-TOELl
OUTPUTS: Rr1-3, DRr6-5
TOEL3
*RI/I-3 and DRI/I-5 may change prior to the falling edge of H sync

Max.

Unit

Comments,

O.B
Vcc

V
V

0.4
0.4

V
V

IOL=3,2ma
10L =1,6ma
IOH=80/La
IOH=40/La

250
10

pA
pA

V,N =O.4V
O$NIP6Ncc

15
40
15

pF
pF
pF

100
70

mA
mA

O.4V"';; V ,N "';; 5.25V

TA = 25°C
4.0

MHz
ns
ns
ns

Figure
Figure
Figure
Figure

1
1
1
1

Figure 2

10l-'s
ns
ns

Figure 2
Figure 2

ns
ns

Figure 2
Figure 2

ns
ns

Figure 2, CL=50pF
Figure 2, CL=50pF

125

Figure 1, CL=20pF

750

Figure 3, CL=20pF

125

Restrictions
1. Only one pin is available for strobing data into the device via the data bus. The cursor X and Y coordinates are therefore
loaded into the chip by presenting one set of addresses and outputed by presenting a different set of addresses. Therefore
the standard WRITE and READ control signals from most microprocessors must be "NORed" externally to present a single
strobe (DS) signal to the device.
2. In interlaced mode the total number of character slots assigned to the horizontal scan must be even to insure that vertical
sync occurs preCisely between horizontal sync pulses.

127

General Timing
HORIZONTAL TIMING
START OF LINE N

START OF LINE N+'

Vt=:IIZZZZIZZ~(://~~??ZZZZIOI;uJ
n
lzzzm
. CHARACTERS PER DATA LINE

HORIZONTAL SYNC DELAY
(FRONT PORCH)
HORIZONTAL SYNC WIDTH
HORIZONTAL LINE COUNT=H
VERTICAL TIMING
START OF FRAME M OR ODD FIELD
START OF FRAME M+' OR EVEN FIELD
SCAN LINES PER F R A M E - - - - - - - - - . . , " I

I-

~
I_

VERTICAL DATA
START

rzzz

VOIIIIIIIIIZZIIIIIIIIIIIIIIIIJ r-l
=oj_
I ~
·ACTIVE VIDEO=
DATA ROWS PER FRAME

VERTICAL SYNC
=3H

Composite Sync Timing

VOH

"VSYN:~O_l+!
":~'--------Ir--__-tr:::,,_,=--=--=--=--=-:n~~~~~~nL-__1L
~
I~: :
_____

_ _ _ _ _ _ __

:---H --+l-o---H ----+1:
VOH

Vertical Sync Timing
--------FRAME M

Iil

DATA ROW COUNTER

~e~~~~I~SBt~~l

COUNT"\

•

"1L-__,;;--_----'
[VERTICAL DATA START SCAN;o (REG 5)

llllWJUWW.llJIJ
VERTICAL
SYNC
EXAMPLE BASED ON: Non-Interlaced (Reg 1, Bit 7 = 0). 24 data rows, 10 scans/data row

Start-up, CRT 5027
When employing microprocessor controlled loading of the CRT 5027'5 registers, the following sequence of instructions is necessary:

COMMAND

ADDRESS
1
1
0

0
1

1
0
0

1
1
0

0
0
0

Start Timing Chain
Reset
Load Register 0

0
0

Load Register 6
Start Timing Chain

The sequence of START RESET LOAD START is necessary to insure proper initialization of the
registers.
This sequence is not required if register loading is via either of the Self Load modes. This sequence
is optional with the CRT 5037 or CRT 5057.
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. FUrthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent f.ights of SMC or others. SMC reserves the right to make changes_~
at any time in order to improve design and supply the best product possible.

128

CRT 5047
f.,Lpc

FAMILY

Preprogrammed CRT Video Timer and Controller
VTAC®
FEATURES

PIN CONFIGURATION

o Preprogrammed (Mask-Programmed) Display Format
o

80 Characters Per Data Row
24 Data Rows Per Frame
9 Scan Lines Per Data Row
Preprogrammed Monitor Sync Format
262 Scan Lines Per Frame
6 Character Times for Horizontal Front Porch
8 Character Times for Horizontal Sync Width
6 Character Times for Horizontal Back Porch
16 Scan Lines for Vertical Front Porch
3 Scan Lines for Vertical Sync Width
27 Scan Lines for Vertical Back Porch
Non-I nterlace
15.720KHz Horizontal Scan Rate
60Hz Frame Refresh Rate
Fixed Character Rate
1.572MHz Character Rate (636.13ns/Character)
11.004MHz Dot Rate (90.88ns/Dot) for 7 Dot
Wide Character Block

A2
A3

Al
M

GND
Rl

o Character Format
5 X 7 Character in a 7 X 9 Block
o Compatible with CRT 8002B-003 VDACTM
o Compatible with CRT 7004B-003
o May be mask-programmed with other display formats

CSVN

H6
H7/0R5

VSYN

DR4

DCC
VDD

DR3

Vee
HSYN

DRl

DR2
DR~
DB~

CRV
BL

DBl

DB7

DB2

DB6

DB3

DB5

DB4

PACKAGE: 40-pin D.I.P.

GENERAL DESCRIPTION
The two chip combination of SMC's CRT 5047 and
CRT 8002B-003 effectively provide all of the video electronics for a CRT terminal. This chip set along with a
pC form the basis for a minimum chip count CRT
terminal.
The CRT 5047 Video Timer and Controller is a special
version of the CRT 5037 VTAC® which has been ROMprogrammed with a fixed format. It is especially effective
for low-cost CRT terminals using an 80 X 24 display
format with a 5 X 7 character matrix. The use of a fixed
ROM program in the CRT 5047 eliminates the software
overhead normally required to specify the display
parameters and simplifies terminal software design.
The Cursor Character Address Register and the Cursor
Row Address Register are the only two registers acces-

sible by the processor. The CRT 5047 is easily initialized
by the following sequence of commands:
Reset

Load Control Register 6

Start Timing Chain

The parameters of the CRT 5047 have been selected to
be compatible with most CRT monitors. The horizontal
timing is programmed so that when the two character
skew delay of the CRT 8002 VDAC™ is taken into account,
the effective timing is: Horizontal Front Porch -four
characters, and Horizontal Back Porch-eight characters.
Figure 1 shows the contents of the internal CRT 5047
registers. Other mask-programmed versions of the CRT
5037 are available. Consult SMC for more information.
129

VTAC® WORK SHEET

1. H CHARACTER MATRIX (No. of Dots): . _5_
2. V CHARACTER MATRIX
(No. of Horiz. Scan Lines): ............ _7_
3. H CHARACTER BLOCK (Step 1 +
Desired Horiz. Spacing = No. in Dots): .. _7_
4. V CHARACTER BLOCK (Step 2 +
Desired Vertical Spacing = No. in
9
Horiz. Scan Lines): ..........•......... _ _
5. VERTI~AL F~AME (REFRESH) RATE
60
(Freq. In Hz) .......................... _ _
6. DESIRED NO. OF DATA ROWS: ........ ~
7. TOTAL NO. OF ACTIVE "VIDEO
DISPLAY" SqAN LI.NES (Step 4 x
216
Step 6 = No. In HOflz. Scan Lmes): ..... _ _
8. VERT. ~YNC DELAY (No. in Horiz.
16
Scan Lines): •... : ..... : ........ .' ...... _ _
9. VERT. SYNC (No. In HOflz. Scan Lines;
T= 190.8 liS"): ...•.....•. : ....• : ....... _3_
10. VERT. SCAN DELAY (No. In HOflz.
27
Scan Lines; T= 1.718 ms"): ............ _ _

REG. #

ADDRESS
A3 AO

0000
0001

11. TOTAL VERTICAL FRAME (Add steps
262
7 thru 10 = No. in Horiz. Scan Lines): .. ' - 12. HORIZONTAL SCAN LINE RATE
15720
(Step 5 x Step 11 = Freq. in KHz): ...... _ ' 13. DESIRED NO. OF CHARACTERS
80
PER HORIZ. ROW: .................... - 14. HORIZ. SYNC DELAY (No. in Character 6
Time Units; T = 3.817 liS""): ..•...•.... _ _
15. H~RI.Z. ~Yr~9bNo:.!n. Character Time
8
Units, T -_.-JIS ) .................. _ 16. HORIZ. SCAN DELAY (No. in Character 6
Time Units; T = 3.817 liS""): .•......... _ 17. TOTAL CHARACTER TIME UNITS IN (1)
HORIZ. SCAN LINE (Add Steps 13
100
thru 16): ............................. ' - 18. ~HARA~TER R~TE (Step 12 x Step 17 1.572
- Freq. In MHz). . ..................... _ 19. ~LOCK .(DOT) ~ATE (Step 3 x Step 18 11.004
- Freq. In MHz) ...................... ' - "Vertical Interval
""Horizontal Interval

FUNCTION

BIT ASSIGNMENT

HEX.

DEC.

HORIZ. LINE COUNT 100

10111110101011111

INTERLACE 0
H SYNC WIDTH+
H SYNC DELAY ___

10111010101111101

0010

SCANS/DATA ROW _9_
CHARACTERS/ROW ~

IxI11010101110111

0011

SKEW CHARACTERS ~
DATAROWS~

10101011101111111

-17-

0100

SCANS/FRAME ~
X =_3_

10101010101011111

0101

VERTICAL DATA START
= 3 + VERTICAL SCAN DELAY:

0110

SCANDELAY~
DATASTART~

fOT O I0111111111 0 1 -1E-

LAST DISPLAYED DATA ROW
(= DATA ROWS)

Ixlxl

1- - -

"Register 6 has an initialization option. It is loaded with the data contained in Register3 by a "Load Register6" command.
The "Up Scroll" command can be used to effect scrolling operations.

Figure 1: CRT 5047 Mask Programmed Registers

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However. no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any 1ime in order to improve design and supply the best product possible.

r'--'~""-

P/:i

CRT 9007*
JlPC FAMILY

'"'~

<~,.1!l.1
" ""l~:""--~
·"-4/:ill
........

~- .... ~......,

.................-.-.....~

CRT Video Processor and Controller
VPAC
FEATURES

PIN CONFIGURATION

o Fully Programmable Display Format
o

o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o

Characters per Data Row (8-240)
Data Rows per Frame (2-256)
Raster Scans per Data Row (1-16)
Programmable Monitor Sync Format
Raster Scans/Frame (4-2048)
Front Porch - Horizontal (Negative or Positive)
-Vertical
Sync Width - Horizontal (1-128 Character Times)
- Vertical (2-256 Scan Lines)
Back Porch - Horizontal
-Vertical
Direct Outputs to CRT Monitor
Horizontal Sync
Vertical Sync
Composite Sync
Composite Blanking
Cursor Coincidence
Binary Addressing of Video Memory
Row-Table Driven or Sequential Video Addressing Modes
Programmable Status Row Position and Address Registers
Bidirectional Partial or Full Page Smooth Scroll
Attribute Assemble Mode
Double Height Data Row Mode
Double Width Data Row Mode
Programmable DMA Burst Mode
Configurable with a Variety of Memory Contention
Arrangements
Light Pen Register
Cursor Horizontal and Vertical Position Registers
Maskable Pr.ocessor Interrupt Line
Internal Status Register
Three-state Video Memory Address Bus
Partial or Full Page Blank Capability
Two Interlace Modes: Enhanced Video and Alternate
Scan Line

V07
VOS
VOS
V04
V03
V02
VOl
V00

INT
SlC/Sl3
SlO/Sl2
CSYNCllPSTB
WBEN/Sll/CSYNC
OMARISl0
m/ACK

i5RB
VlT

RSi'
GNO

VA13
VA12
VAll
VA 10
VAg
VAS
VA7
VA6
VAS
VA4
VA3
VA2
VAl
VA0
CURS
CBlANK

HS
Vs
CClK
+SV

o Ability to Delay Cursor and Blanking with respect to
Active Video
o ROM Version for Vital Screen Parameters
o Programmable for Horizontal Split Screen Applications
o Graphics Compatible
o Ability to Externally Sync each Raster Line, each Field
o Single +5 Volt Power Supply
o TTL Compatible on All Inputs and Outputs
o One Pin Processor Interface
o VT-100 Compatible
o RS-170 Interlaced Composite Sync Available

GENERAL DESCRIPTION
the video dispay is designated by its own address. This
provides the user with greater flexibility than sequential
addressing since the rows of characters are linked by
pointers instead of residing in sequential memory locations.
Operations such as data row insertion, deletion, and replication are easily accomplished by manipulating pOinters instead
of entire lines. The row table itself can be stored in memory
in a linked list or in a contiguous format.
The VPAC works with a variety of memory contention
schemes including operation with a Single Row Buffer
such as the CRT 9006 (Figure 2), a Double Row Buffer
(Figure 3), or no buffer at all, in which case character
addresses are output during' each displayable scan line.
Useraccessable internal registers provide such features as
light pen, interrupt enabling, cursor addressing, and VPAC
status. Twelve of these registers are used for screen formatting
with the ability to define over 200 characters per data row and
up to 256 data rows per frame. These 12 registers contain the
"vital screen parameters". An alternate high volume version
of the chip contains these parameters in ROM such that
chip initialization is unnecessary.

The CRT 9007 VPAC is a next generation video processor/
controller-an MOS LSI integrated circuit which supports
either sequential or row-table driven memory addressing
modes. As indicate'd by the features above, the VPAC
provides the user with a wide range of programmable
features permitting low cost implementation of high performance CRT systems. Its 14 address lines can directly
address up to 16K of video memory. This is equivalent to
eight pages ofan80character by 24 line CRT display. Smooth
or jump scroll operations may be performed anywhere
within the addressable memory. In addition, status rows can
be defined anywhere on the screen.
In the sequential video addressing mode, a Table Start
Register shown in Figure 1 points to the address of the
first characterof the first data row on the screen. It can
be easily changed to produce a scrolling effect on the screen.
By using this register in conjunction with two auxiliary
address registers and two sequential break registers, a
screen roll can be produced with a stable status row held
at either the first or last data row position.
In the row-table driven video addressing mode each row in
·For Future Release

131

CHARIHORIZ PERIOD

CURSOR, BLANK SKEW

SCANLINESIDATAROW

CHAR/DATA ROW
HORIZOELAY

HOAIZ SYNC WIDTH
VEAT SYNC WIDTH

DATA ROWS/FRAME

SCAN LINES/FRAME

DMA ~UAST. O~~Y_ COUNT

VD7-0/'----------"

CURS

.....

I\)

VA13-0

14 BIT ADDRESS BUS

CBLANK
CCLK
TIMING
AND
CONTROL

cs-----------'
RST

Figure 1. CRT9007 Block Diagram

~~ll~ll

-----gs~~~7 '

PROCESSOR
pP/pC

AD DR

A
MEMORY

......

w
w

",M~

~ATA

HOLD
RD WR

F~~~

TSC

I
I

INT

RST +5V GND

CSYNC

LPSTB
T

VPAC

C BLANK

"
A

I ..

f--

\IS
VD7-0

D
A
T
A

SL3 SL2 SL.1 SL0

VLT

R3 R2

WREN CLRCNTCKEN CLK

R1 R0

CURSOR VSYNC

DOUT7-0

CRT 9006
SINGLE
ROW BUFFER
DIN 7-0

OE
OF

,-------

CRT 8002
VDAC™

DOT
I
CLOCK
'
GENERATOR I

RETBL

VDC

A7-0

Figure 2. VPAC Configuration With Single Row Buffer

II
LD/SA

ATTRIBUTES

'CCLK

CURS

B
U
S

CRT 9007

VA13-0

ADDRESS BUS

1! !

VIDEO

TO
MONITOR

1-0

::EOZ_I-Oa:

r -0:-

g::;

",0

.... o~

g~~
w

'---,~

~ z jg1

..J

'"
"
..J

...J

~
g
0:

::J
0

t---<~

~
il'i

'--~

i'"

i
0:

~wW

ffi~
0:::J",
~8~·
0:

r---- •g !!

..J

'-----...J

0
..J
0
1:

0:>
0

«
0

'"w~

III

§~
.... 0.

ll!

~I---- ~<~
rn
t)~

0:
::J
0

,-8

§
~

:;;

0:
0

0
Z

0
w
0

--~ '"
~

~--

0
0
>

I§

, ::.
0«1-«

"'::J",

:UL ~
0

, ::. ' ::.
>

0:
0

::;
w
::;

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequelitly complete information sufficient for construction purposes is not necessarily given. The

devices described any license under the patent rights of SMC or others. SMC reserves the right to make ch/lnges
at any time in order to improve design and supply the best product possible.

134

(l"

CRT 9006-135
CRT 9006-83*
J.1PC FAMILY

Single Row Buffer
SRB
FEATURES:

PIN CONFIGURATION

o Low Cost Solution to CRT Memory Contention Problem
o Provides Enhanced Processor Throughput for CRT
Display Systems
o Provides 8 Bit Wide Variable Length Serial Memory
o Permits Active Video on All Scan Lines of Data Row
o Dynamically Variable Number of Characters per Data Row... 64,80, 132, ... up to a Maximum of 135
o Cascadable for Data Rows Greater than 135 Characters
o Stackable for Invisible Attributes or Character
Widths of Greater than 8 Bits
o Three-State Outputs
o 4MHz Typical Read/Write Data Rate
o Static Operation
o Compatible with SMC CRT 5037, CRT 9007, and other
CRT Controllers
o 24 Pin Dual In Line Package
0+5 Volt Only Power Supply
o TTL Compatible Inputs and Outputs
o Available in 135 Byte Maximum Length (CRT 9006-135)

DOUT3

GND

DOUT2

DOUT4

DOUT1

DOUTS

DOUT0

DOUT6

ClK

DOUT7

WREN

ClRCNT

CKEN

DIN7

DIN0

DIN6

DIN1

DINS

DIN2

DIN4

DIN3

+sv
Package: 24-pin D.I.P.

APPLICATIONS:

o CRT Data Row Buffer
o Block-Oriented Buffer
o Printer Buffer
o Synchronous Communications Buffer
o Floppy Disk Sector Buffer

or 83 Byte Maximum Length (CRT 9006-83)

GENERAL DESCRIPTION
The SMC Single Row Buffer (SRB) provides a low cost solution to memory contention between the system processor and
CRT controller in video display systems.
The SRB is a RAM-based buffer which is loaded with character
data from system memory during the first scan line of each
data row. While data is being written into the RAM it is also
being output through the multiplexer onto the Data Ouput

(DOUT) Lines. During subsequent scan lines in the data row,
the system will disable Write Enable (WREN) and cause data
to be read out from the internal RAM for CRT screen refresh,
thereby releasing the system memory for processor access
for the remaining N-1 scan lines where N is the number of
scan lines per data row. The SRB enhances processor throughput and permits a flicker-free display of data.

eLK
CKEN

OCTAL
2T01
MUX

3-STATE

L
U A

T T
P e

,-------v

DOUT7-0

D1N7·0

Single Row Buffer Block Diagram
'FOR FUTURE RELEASE

135

1-0

~
01:
...
z

:eOZ-I-Oa::

o::;

"'~

ggffi r-Oi!j

~---r--------'=-~

z
:s'"
III

:50
0

C!J

rJr-+-+---,J,--,
-J

'---+-t-"I~

l-c()>-t-t--+j~
en
0:

::>

en r----t-+-I~
:; 1----+-+-..11<
en

...z

en!I----+-+--I~
0:

en J----t-+-+j2

0 ...

0:0:
:'0

0"':

~§

0: ...
00:

L-..!:;

3~1.L AVldSIO

3NI1~i

~ ~} r-! ~",,':1."
~ ~~~~

"z"-

ffi

I~ :" JLJ
511------Vy

STAN~RD MICROSVSTEMS

rION

35 Marcus BML,HaI.Q:IaIo. N,Y.t1787
(516}273·31110 TWlC-51O-227-889B

welleeP_DfIU~"IOIIC31I1eeP_DfjlU$.

Circuit diagrams utilizing SMC products are Included as a means of Illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reServes the right to make changes
at any time in order to improve design and supply the best product possible.

136

CRT 96364 A
CRT96364B
f.,LPC FAMILY
Preliminary Specifications

CRT Controller
PIN CONFIGURATION

FEATURES
D Single +Sv power supply
D 16 line x 64 character display
D On chip sync oscillator
D Complete cursor control
D Automatic scrolling
D Erase functions built in
D Performs character entry during horizontal sync
D Internal blinking cursor
D Page linking logic built in
D LS-TTL compatible
D Compatible with CRT 8002, CRT 7004

28 Vee

27 EOP

26 CSYN

25 C2

24 C1

23 C0

22 A4

21 A3

DCC

20 A2

DCE 10

19 A1

R0 11

18 A0

R1 12

17W

R2 13

16 DS
15 CRV

GND 14

PACKAGE: 28-Pin D.i.P.

GENERAL DESCRIPTION
The CRT 96364AI B is a CRT Controller which
controls all of the functions associated with a
16line x 64 character video display. Functions
include CRT refresh, character entry, and cursor
management.
The CRT 96364A/B contains an internal oscillator
which produces the composite sync output. The
CRT 96364 B generates a 60 Hz vertical sync while
the CRT 96364A generates a SO Hz vertical sync.

Standard functions such as ERASE PAGE, ERASE
LINE, and ERASE TO END OF LINE make the CRT
96364A/B easy to interface to any computer or
microprocessor, or to use as a stand-alone
video processor.
The CRT 96364A/B requires only +SV power at
less than 100 mAo It is manufactured in COPLAMOS®
N channel silicon gate technology.
C0

CRY

GND

Vee

,.
Dec

137

DCE

CSYN

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

NAME

SYMBOL

1
2

Crystal in
Crystal out

Page Select

4-8

Memory
Address

FUNCTION
Pin one is the sync clock input. It may be driven directly from a TTL
gate or from a parallel mode crystal connected between pins one
and two. When a crystal is used, a 10 Mflresistor should be
connected in parallel. For standard 60 Hz line operation, a 1.018 MHz
frequency source or crystal is required (with the CRT 96364 B). For
50 Hz line operation, the CRT 96364 A requires a 1.008 MHz crystal.
PS proviqes automatic page selection when two pages of memory
are used. A "zero" output indicates selection of page 1; a logic "one"
indicates page 2.

A9-A5

Upper order memory address lines; A6-A9 determine which lines of
text are being refreshed or written. A5 along with AS-A4 determine
the character position.

Character
Clock

DCC

Character clock input. Addresses are changed on the trailing edge
of DCC.

Dot Clock
Enable

DCE

A logic zero from DCE is used to inhibit oscillation of the dot clock
for retrace blanking.

Row Address

R0-R2

Character Generator row addresses. Blanks are generated by forcing
RS~R2 to "000". During character entry, R2 gates data into memory
to contrDI the erase function. Row addressing follows the sequence
0-1-2-3-4-5-6-7-0-0-0-G-inCl"ement text line-D-1-2-etc.

Ground

GND

Ground

Cursor

CRV

Cursor video output. Indicates cursor location by a 2 Hz
blinking underline.

Data Strobe

The rising edge of DS strobes the appropriate C0-C2 control word
into the CRT 96364A1B.

Write

A positive going signal which indicates that the CRT 96364 AI B is
allowing a memory write. W is approximately 4 ps, and occurs
during H sync. Memory address lines are latched at the cursor
address during W.

11-13

18-22

Memory
Address

A!/l-A4

Lower order memory addresses. Af/l-A4 plus A5 (pin 8) determine the
character position.

23-25

Command
Inputs

C!/l-C2

Command inputs are strobed into the CRT 96364 AI B by DS. Functions
are as follows:
(

Function

Page erase and cursor home (top-left)
Erase to end of line and return cursor (to left)
Line feed (cursor down)
No operation'
Cursor left (one position)
Erasure of cursor-line
Cursor up (one position)
Normal character. Write signal is generated
and cursor position is incremented
• In order to suppress non-displayed characters

0
0
0
0
1
1
1
1

0
0
1
1
0

0
1
0
1

1
1

Positive logic compVS~N6nc output. Horizontal sync is generated
during VSYNC and
time. A vertical sync output may be
generated by logically "ANDing" CSYN and DCE.

Composite
Sync

End of Page

EOP

This output is used to increment an external page counter when
using more than one page of memory.

Power Supply

Vee

+ 5 volt supply.

CSYN

138

•

0
1

OPERATION
The CRT 96364A1B provides all of the control
functions required by a CRT display with a
minimum of external circuitry.
The cursor and erase commands may be decoded from the data bus by a low cost 256 x 4
PROM. The CRT 96364A1B then provides t!:J.e
necessary cursor movement and gates the
memory for writing or erasing. Erase is controlled by providing a write signal to RAM, and

gating "zeros" to the RAM input bus. Use of an
external PROM allows user selection of control words.
The RAM write command, "W", is generated
during horizontal retrace. At this time, the RAM
address is set to the cursor address. Immediately following the write command, the RAM
addresses revert to refresh addressing and
the cursor is shifted one character.

CURSOR
The cursor location is indicated by an alternating high on pin 15 (CRV) at row 7, and a low
on pin 15 with RO-R2 forced low at rows 0-6.
These alternate at a 2 Hz rate. If CRV is used to

force the display on, the result will be a blink
of the cursor character position alternating with
an underline at a 2 Hz rate.

CHARACTER ENTRY
When a Normal Character code (C2, C1 , C0 = 1,
1, 1) and a Data Strobe are received, the write
command will be generated during horizontal
retrace. If, at the end of the horizontal retrace,
the cursor is at the last position on a line, a car-

riage return and line feed will automatically
occur. When the cursor is at the last position
of the last line, a carriage return and up-scroll
will automatically occur.

EXTRA FUNCTIONS
By using the fourth bit of the decoder PROM as
a write enable signal, and properly programming the PROM, the additional commands. of
Home Cursor, Return Cursor, and Roll Scrt;len
may be generated. This is done by inhibiting the

W signal to the page memory and inputting the
control codes, respectively, of Page Erase and
Home Cursor, Erase to end of line and Return
Cursor, and Line Feed.

SCROLLING
Scrolling of the screen text will occur under
any of the following characteristics:
1. Inputting a line feed command when the
cursor is at the bottom. line of the screen.
2. Inputting a character when the cursor is
at the bottom right hand side of the screen.
Scrolling will result in the entire top line of the

screen being erased and all of the remaining
lines shifting up. Alternatively, a Roll (defined
as all of the lines shifting up with the previous top line reappearing at the bottom of the
screen) may be performed by inhibiting the
write signal to the page memory as described
in "Extra Functions."

139

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range " " " " " " " " " " " " " " " " " " " ' , ' , ' , " " " " " " " " " ,O°C to, + 70°C
Storage Temperature Range " " " " " " " " " " " " " " " " " ' , " , ' , " , ' , ' , ' ......... ," ,-55°C to +150°C
Lead Temperature (soldering, 10 sec,) , '" , , '" , , , "" , , '" " , " , , , " , " , , , , , , , , ,,' " " ,:,' '" '" '" ,+325°C
Positive Voltage on any Pin, with respect to ground " " " " " " " " " " " " " " " " " " , ' , " " " " " ' " + 7,OV
Negative Voltage on any Pin, with respect to ground " " " " " " " " " " " " ' , ' , " " , ' , " " " " " " " ' " -O,3V
*Stresses above those listed may cause permanent damage to the device, This is a stress rating only and functional
operaiTonof tnediiviCe at fnese or afany ofheTcondHion-above'thoselnrncated'inth-e
operational sections of this specificiifion is nol'implied,
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vcc= +5V±5%, unless otherwise noted)
Parameter
D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS (except DCC)
Low-level, V,l
High-level, V,H
INPUT VOLTAGE LEVELS-DCC
Low-level, V,l
High-level, V ,H
OUTPUT VOLTAGE LEVELS (DCE Only)
Low-level, VOL
High-level, VOH
OUTPUT VOLTAGE LEVELS (except DCE)
Low-level, VOL
High-level, VOH
INP(if CURRENT
Low-level, III
INPUT CAPACITANCE
All inputs, C,N (except DCE)
C'N (DCC Only)
POWER SUPPLY CURRENT
Icc

Min.

Typ.

Max.

V
V

0.65

V
V

0.4

V
V

IOl =1.9 rnA
IOH=-100p.A

0.4

V
V

IOL =0.36 rnA
IOH=-100p.A

p.A

3.5

2.2

5
25

pF
pF

100

excluding DCC
excluding DCC

0.65
2.2

120

V,N=GND
V,N=GND

AC CHARACTERISTICS
PARAMETERS

SYMBOL

Frequency of control clock DCC
Crystal Frequency CRT 96364A
CRT 963648
DCC pulse width

VALUES
MIN.

tocc
t,
tf

Refresh memory address access time

ns
20

200

250
250

ns
ns
ns

200
300
200
100
64

tcps

UNIT
MHz
MHz
MHz

200

tCA
t CRO

Character memory address access time
PS access time (read)

MAX.

1.6
1.008
1.018

focc
fx
fx

Rise and fall times

TYP.

1000
250

CRV access time

tCRV

DCE access time (high to low)
SYNC period

tOCE
tps

SYNC pulse width

twp

JlS

DCE access time (low to high level)

tsc
tsp

11
1

Jls

tsw
tpw

,500

f.IS

EOP pulse width
Address to rising edge of DCE delay

troP

Falling, edge of DCE to Address delay
Row to rising edge of DCE delay
Falling edge of DCE to row delaY
PS to rising edge of DCE delay

tOA
t RO

JlS
JlS
JlS
JlS

EOP access time (high to low level)
W access time (lOW to high)
W pulse width

tAO

tOR
tpso

140

0
0
0
0
0

ins;
ns
JlS

1.5
1000

2.1
1
2.1
1

JlS
ns

JlS
JlS

LINE TIMING

~r-S ~ ~

DCC

(DISPLAY POSITION IN PARENTHESES)

-l . . . toc,

DCE

.....

-l

I-t"
(2)

All-AS

(3)

(4)

(63)

....

...... to-

(1)

(0)

I-to.

(CHARACTER ADDRESS)

A6-A9

(Y)

(Y+l)

(LINE ADDRESS)

r'"

t", ..
CRV

R0,R1

1+'"

t"o ..

.....

+-t"o

--t"o

,;,

......

I--t..
.~

-::j

.t=t.
I'

t", .....
PS

teov

;

+-t",

-BLANK PERIOD

A
I

DISPLAY PERIOD

, SYNC TIMING

-I 1+1.-- ,,---1'1
Iw.

CSYN

-l
L - -_ _ _----'-

r-I~

-,L-____--'r----'L-____--'r----L

DCE

tEQji

FRAME TIMING
CSYN
DCE

141

DATA INPUT TIMING
Asynchronous Operation
PARAMETER
DS Pulse Width
Cf/l-C2 Set Up Time
Cf/l-C2 Hold Time
Minimum Strobe Period
(Operation Execution Time)

SYMBOL

MIN
0.5
1
90

t.w
tCD'
tDse

Value
TYP

MAX

UNIT
/-IS
f.IS

/-IS

to,

FUNCTION

Page Erase & Cursor Home
Erase to End of Line & Return Cursor
Line Feed (Cursor Down)
No Operation
Cursor Left
Erasure of Cursor Line
Cursor Up
Normal Character

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
"Will increase to 8.3 ms when text scroll occurs. See "ScrOlling" for conditions.

Cf/l
0
1
0
1
0
1
0
1

132
4.2
130"
80
80
8.3
80
130"

ms
ms
/-IS
/-IS
/-IS
ms
/-IS
/-IS

MAX

UNIT
/-IS

Synchronous Operation
PARAMETER
DS Pulse Width
CO-C2 Set-Up Time
CO-C2 Hold Time
DS Set Up Time
Minimum Strobe Period
(Operation Execution Time)

SYMBOL

MIN
0.5
1
16
1

t.w
tCDS

tDse
tSDS

Value
TYP

pS
f.IS

/-IS

tDS

FUNCTION

Page Erase & Cursor Home
Erase to End of Line & Return Cursor
Line Feed (Cursor Down)
No Operation
Cursor Left
Erasure of Cursor Line
Cursor Up
Normal Character

0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
..
.. .
"Will Increase to 8.3 ms when text scroll occurs. See "Scrolling" for conditions

CIIl
0
1
0
1
0
1
0
1

132
4.2
64"
64
64
8.3
64
64"

ms
ms
/-IS
/-IS
/-IS
ms
/-Is
f.J.s

DATA INPUT TIMING
ASYNCHRONOUS OPERATION

OS
C8-C2

SYNCHRONOUS OPEHATION
CSYN

os --.......,
C8-C2

---~H--+----Jt------_I\-_----"'------"",--

142

MULTIPLE PAGE DISPLAY

4 PAGE DISPLAY

When linking two or more pages, the
EOP and RS signals may be used to
allow a "moving window" text display.
PS (Page Select) indicates the end of
page location. If a scroll has occurred,
PS will show the transition from the
end of line 15 of page P and the beginning of line 0 of page P + 1.
Display Area
line 14
line 15

PageP

lineO
line 1
line2

Page P+1

DECREMENT PAGE
(NEGATIVE PULSE)

A11-----,
A10

r----;--RS

74LSS3

74LS193

+5
V"

OND

Load

B3
B2

27
EOP
CRT 96364A1B

To properly maintain the memory
address when t!!Iisplaying more than
two pages, EOP pulses low at the
point in time when page P is scrolled
completely off the screen. At this time,
RS will remain low for the entire frame
since page P + 1 is now the only
displayed page.
The circuit at the right will allow
scrolling through 4 pages of memory.

AS
A7-----'
A6-----~

A5---_----I
A4---------I
A3----------I
A2-----------I
Al------------I
A0------------------~

TYPICAL SYSTEM APPLICATION

~------------~

143

Clear

§~
~~

5i.

j:
l!I

E! "'.
~ ~~

Jii
!!{
IiJ
a%~

i:lU

~g&ag:Q

~£.~~~g.
_cn

a.c. ...

(')~

...

745128
287

23
24

ICS

5.~§Olg~
CD::T::J
ro
~ ~S·~~ 3"

1413

m~a._()Ol

-ogoo3

16
10
1

"0"
STR

a ~ g~~

Vco

Q
a.g.g.roccn

~~g ~g.~

c~p..L

~~.s::-co
Cn~~~~ .~. .
~~s~~g·
cn
(0 co co

RASTER
SCAN
COUNTER

~ ADDRESS

R9-3

TIMING
FROM
DOT COUNTER
OR
CHARACTER
CLOCK

"r>-

_Gl

VDAC
CRT 8002

RETRACE
BLANKING
SERIAL
OUTPUT

CRT 5027 VTAC
CRT 8002 VDAC
IJP CONFIGURATION

r - - - - - - - - - - - I - V D C (to chip)

Vcc

500n

CP EXTERNAL - - - - I

Ir~~------

__--~CLK

QI------LD/SH (to chip)

74S74
LOAD/SHIFT EXTERNAL-------lD

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applica~
tions; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

152

CRT 8002-001
(KATAKANA)

CODING INFORMATION

CRT Video Display-Controller
Video Generator VDACTM

THIN GRAPHICS MODE

WIDE GRAPHICS MODE

C7 C6 C5 C4 C3 C2 Cl

Cfl~F

BF ...

All
RJI

R2
R3

:: f7~~H.....:)IH~-+-4-+1

Rl/1'

E--l

All
R12
R13

NOTE

LL..CL...CL...4-4L~:.y;...q

R14

R15
R14

NOTE. WhenAl = ",", the underline
row/rows are deleted.
When Al = "0", the underline,
jf selected. will appear

NOTE: Unselected raster line rows
are always filled with ones.

R15 L -_ _ _ _ _ _ _ _ _ _ _ _ _ _

BF=back fill

ATTRIBUTES
Underline
Underline will be a single horizontal line at row R1t
Cursor
Cursor will be a blinking reverse video block, blinking at 3.75 Hz

153

Blink Rate
The character blink rate will be 1.875 Hz
Strike-Thru
The strike-thru will be a double line at rows R5 and R6

CRT 8002-003
(5X7 ASCII)

35 Marcus Blvd., Hauppauge, NY 11787
(516) 273-3100 TWX-510-227-8B98

CODING INFORMATION

our competition so '/OU can keep ahead Of yours.

CRT Video Display-Controller
Video Generator VDACTM

WIDE GRAPHICS MODE

THIN GRAPHICS MODE
A9

Al
A2
A3
A4
A5
R6

H+~*~:-+*~

A5
A6

:: 17-777>'777

/U-''-''-<.L.LLL..<.L<......L.L..L..j
Al0

Al1
A12

Al1

Note: A1t ·A15 are

alwayslmed with ones.

A12

A13

A14

A15

ATTRIBUTES
Underline
Underline will be a single horizontal line at R8
Cursor
Cursor will be a blinking reverse video block, blinking at 3.75 Hz

154

Blink Rate
The character blink rate is 1.875 Hz
Strlke-Thru
The strike-thru will be a single horizontal line at R4

CRT 7004
jLPCFAMILY

Dot Matrix Character Generator
128 Characters of 7 x 11 Bits
FEATURES
D On chip character generator (mask programmable)
D

D
D
D
D
D
D
D
D
D

128 Characters
7 x 11 Dot matrix block
On chip video shift register
Maximum shift register frequency
CRT 7004A
20M Hz
CRT 70048
15MHz
CRT 7004C
10MHz
Access time
400ns
No descender circuitry required
On chip cursor
On chip character address buffer
On chip line address buffer
Single + 5 volt power supply
TTL compatible
MaS N-channel silicon-gate COPLAMOS@ process
CLASP@technology-ROM
Compatible with CRT 5027 VTAC@
Enhanced version of CG5004L-1

GENERAL DESCRIPTION
SMC's CRT 7004 is a high speed character generator with a high speed video
shift register designed to display 128
characters in a 7 x 11 dot matrix. The
CRT 7004 is an enhanced, pin for pin
compatible, version of SMC's CG5004L-1.
It is fabricated using SMC's patented
COPLAMOS@ and CLASp@ technologies
and employs depletion mode loads,
allowing operation from a single + 5v
supply. This process permits reduction of
turn-around time for ROM patterns.
The CRT 7004 is a companion chip to
SMC's CRT 5027 VTAC@. Together these
two chips comprise the circuitry required
for the display portion of a CRT video
terminal.

PIN CONFIGURATION
NC

24 GND

23 PE

Vee
LS

22 NC

21 VDC

5
6

20 CUR

18 LCI

PRST
L1

19 AS

CLR
L2

17 A7

16 A6

L8 10
A1 11

14 A4

A2 12

13 A3

PACKAGE: 24-Pin D.I.P.

FUNCTIONAL BLOCK DIAGRAM

Line Address

Character
Address
Lower Case
Inhibit

Cursor

~~r;~I~-_~~~~~~~~~~~=~~=~~~~=:==:=J
Clock

Preset-------------.....J
Clear-----------------'

155

Serial

Output

MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range ...............................................................O°C to + 70°C
Storage Temperature Range ............................................................... -55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................... +325°C
Positive Voltage on any Pin, with respect to ground .................................................... + B.OV
Negative Voltage on any Pin, with respect to ground ...........................•........................ -0.3V
• Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transients on the AC power line may appear on the DC output. If this possibility
exists it is suggested that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vcc= +5V:!:5%, unless otherwise noted)
Parameter
D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, VIL
High-level, VIH
INPUT VOLTAGE LEVELS-CLOCK
Low-level, VIL
High-level, VIH
OUTPUT VOLTAGE LEVELS
Low-level, VOL
High-level, V OH
INPUT CURRENT
Leakage,I L

Min.

Typ.

Unit

O.B

V
V

excluding VDC
excluding VDC

O.B

V
V

See AC Timing Diagram

0.4

V
V

IOL =0.4 mA, 74LSXX load
IOH= -20pA

100
10

p.A

VIN

O~VIN~VCC' All others

10
20
25

pF
pF
pF

@1MHz
@1MHz
@1MHz

100

2.0

4.3

2.4

INPUT CAPACITANCE
Data
Pi:
CLOCK
POWER SUPPLY CURRENT
Icc

Comments

Max.

= O. LS, AS, A1-A7, Cursor LCI

,.,:~~'I"
.__"_';:l,l~,':;;·",·

...,....

SYMBOL
VDC

PARAMETER
Video Dot Clock Frequency

CRT 7004A

CRT 7004B

CRT 7004C

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

1.0

UNITS
MHz

PWH

VDC - High Time

13.5

PWL

VDC-LowTime

13.5

tcyAS

Address strobe to PE high

400

533

BOO

tcyLS

Line strobe to PE high

t" t f

Rise, fall time

PE set-up time

PE hold time

AS pw

Address strobe pulse width

LSpw

Line strobe pulse width

tSET-UP

Input set-up time

t HOLD

Input hold time

tpdl , tpdo

Output propagation delay

1.0

1.0
10

1.0

15
45

156

P.S

15
60

ns
90

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
1
2

FUNCTION

NAME
No Connection
Serial Output

SYMBOL
NC
SO

3
4

Vee
LS

Power Supply
Line Strobe

PRST

Preset

6,8,9,10

L1, L2,
L4,L8

Line Address

CLR

Clear

A1-A7

Character Address

LCI

Lower Case Inhibit

Address Strobe

CUR

Cursor"

21
22
23

CLK
NC
PE

Clock
No Connection
Parallel Enable

GND

Ground

11-17

The output of the dynamic shift register is clocked out
on this pin. The serial input to this shift register is
internally grounded; thus zeros are shifted in while
data is shifted out.
+ 5 volt supply
A positive pulse on this input enters data from the L1,
L2, L4, L8 lines into the line address holding register.
The LS input may be left open, in which case itis pulled
up to Vee by an internal resistor. Data on the L 1 to L8
inputs is then entered directly into the register without
any latching action.
A high level on this input forces the last stage of the
shift register and the serial output to a logic high.
A binary number N, on these four inputs address the Nth
line olthe character fontfor N = 1-11. " lines 0, 12, 13,
14 or 15 are addressed, the parallel inputs to the shift
register are all forced low.
A high level on this input forces the last stage of the shift
register and the serial output to a logic low and will be
latched (for a character time) by PE. Clear overrides
preset.
The seven-bit word on these inputs is decoded internally
to address one of the 128 available characters.
A high level on this input transforms the address of a
lower case character into that of the equivalent upper
case character. This is internally achieved by forcing
A6 low whenever A7 and LCI are high.
A positive pulse on this input enters data from the A1-A7,
LCI and CUR inputs into the holding register. The AS
input may be left open, in which case it is pulled up to
Vee by an internal resistor. The data on the A1-A7, LCI
and CUR inputs Is then entered directly into the register
without any latching action.
A high level on this input causes the cursor pattern to be
superimposed on the pattern of the character addressed,
i.e., the two patterns are OR-ed to generate the parallel
inputs to the shift register. The standard cursor is
presented as a double underscore on rows 10 and 11.
Frequency at which video (SO) is shifted.
A high level on this input loads the word at the output of
the ROM into the shift register. The PE input must then
be brought low again to allow the shift register to clock
out this word.
Ground

r-',+PWo+~+PW'l
ClK

4.3v

iI!
I -1',1-

PE _ _ _-iIII-_______

Al-A7.CUR.
lCI

so (Video)

~j'L'

~~..:.L...I-----------:::
I f---AS~---I

~1=

~.....j
'I

O.8v

-j"r-!

!
As _ _--ifl

~'"'

"'~I---::::

I~'·

.....j'oo,,1-- 0.8v
2.4v

0.4v

-I

AC TIMING DIAGRAM

157

£51

XTAL
R

74160
DOT
COUNTER
(-;- N)
CP

CARRY
CHARACTER CLOCK

DCC

7404

H SYNC HORIZ. SYNC

CHIP SELECT
DATA STROBE

C SYNC

VTAC
CRT 5027

~~~60SITE
BLANKING

CHARACTER ROW
DRS-5

CHARACTER
ADDRESS
BUS

ADDRESS BUS
ASCII
DATA
BUS

CRT 7004
VIDEO DOT
CLOCK

RETRAC
BLANKING
SERIAL
OUTPUT

DATA
OUT
·OR 1 PORT RAM
WITH BI-DIRECT
PORT

158

TIMING
FROM
DOT COUNTER
OR
CHARACTER
CLOCK

HS-7

DATA BUS

-t

;;:

VIDEO

8 CHARACTER COLUMN

()

r;=============;t:::~Ae-3

MICROPROCESSOR

V SYNC VERT. SYNC
ADDRESS BUS

CRT 5027 VTAC
CRT 7004 VDAC
J.tp CONFIGURATION

7 1/82/1

CLOCK

AS .",...,-----'C,H'--_ _ _----'

' - -_ _ _----'C6H

LSflYJ~-----------------------------------------------------

PRESET _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--l

_______'r_l~____________

CLEAR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - l

SO VIDEO
7 DOT FI ELD ---'''--''''-'''-'''--'''---''''--'><-.l>L.J'''---'''---'''-'''--''''--'''--''''-.l>L..1>L.J

SO VIDEO
8 DOT FI ELD ---'''--''''--''''---''''--''''---'''--''''-"'--''''-'''--'''-''''--'''---'''---'''-"'--'''--'

BF= BackFill

TYPICAL VIDEO OUTPUT

Vee

r----.,.------~ClK

(to chip)

500\)

CP EXTERNAL----t

r--.----~~~ClK

QI-----t_ PE (to chip)

74S74
lOAD/SHIFT,EXTERNAL------ID

NOTE
The differences between the CRT 7004 and CG5004l-1 are detailed below:
CG5004L-1
1. If both the Preset and Clear inputs are
brought high simultaneously the Serial
Output is disabled and may be wire-ORed.
2. All Inputs V'H = Vee - 1.5v

CRT 7004
1. Clear overrides Preset, no output disable is
possible.

2. All inputs (except ClK) V'H = 2.0v, min.
ClK V'H = 4.3v, min.
3. SO VOL = O.4v @ IOL = O.4mA 74lSXX load
4. Shift Register is dynamic
5. Clear di rectly forces the output low and will
be latched (for a character time) by PE.

3. SO VOL = O.4v@ IOL = 0.2mA
4. Shift Register is static
5. Clear-directly forces the output low; when
released, the output is determined by the
state of the shift register output.
6. General Timing Differences-See Timing
Diagram

6. General Timing Differences-See Timing
Diagram
159

CRT 7004-003
(5 X 7 ASCII)
CODING INFORMATION

Dot Matrix Character Generator

The Cursor for the CRT 7004-003 is presented as a double underscore on Rows 8 and 9.

160

(3)May

be custom mask programmed

161

162

4100 Series

CG4103

CHARACTER GENERATOR
2240-Bit Programmable (ROM) 64 Characters of 5 x 7 Bits

FEATURES
o Static Operation, no clocks required.
o 2240-Bit Capacity, fully decoded·
o 64 Characters of 35 Bits (5 x 7)
o Column by Column Output-Column
Scan
o TTL Compatible
o Wired "OR" Capability for memory
expansion
o Power Supplies: +14v, -14v or +12v,
-12v, or +5v, -12v
o Eliminates need for + 12v power supply
o Single mask custom programming

PIN CONFIGURATION
011

28 Chip Enable (M)

NC 2

27 A1

023

26 A2

NC 4.

25 A3

035

24 A4

NC 6

23 As

04 7

22 Cs

NC 8

21 C4

Os 9

20 C3

NC 10

19 C2

06 11

18 C1

NC 12

17 Vss
16 A6
15 VGG

07 13
Voo 14

APPLICATIONS
o Matrix Printers
o Vertical Scan Alphanumeric Displays
o Billboard and Stock Market Displays
o Strip Printer
o LED Matrix Arrays

= No Connection

BLOCK DIAGRAM

ffi

II:

~Aa

01
02 ~
CHARACTER
ADDRESS
DECODE

~ As

ROM
MEMORY
MATRIX
(2240 Bils)

OUTPUT
BUFFERS

COLUMN
SELECT

03 ~

Os --~"""~

'---.1----<.

INPUT A.>----t---t.~

t-----<..

INPUT C

RECIRC. INPUT 0

'-.1---4..--< REC. CONTROL 0
INPUT B

INPUT 0

CLOCK

167

CLEAR

General Description
The SMC SR 5015-XXX is a quad static shift register family fabricated using SMC's COPLAMOS® N channel silicon gate
process which provides a higher functional density and speed on a monolithic chip than conventional MOS technology, The
COPLAMOS® process provides high speed operation, low power dissipation, low clock input capacitance, and single +5 volt
power supply operation.
These shift registers can be driven by either PL circuits or by MOS circuits and provide driving capability to MOS or PL
circuits. This device consists of four separate static shift registers with independent input and output terminals and logic for
loading, recirculating or shifting information. The SR 5015-80, SR 5015-81, and SR 5015-133 are respectivelytlO, 81, and
133 bit quad shift registers.
The recirculate control pin is common for registers A, B, and C. Register D has an independent recirculate control pin as
well as a recirculate input pin.
A clear pin has been provided that will cause the shift register to be cleared when the pin is at Vee. A single PL clock is
required for operation.
The transfer of data into the register is accomplished on the low-to-high transition of the clock with the recirculate control
low. For long term data storage the clock may be stopped and held in either logic state. Recirculate occurs when the
recirculate control is high. Output data appears on the low-to-high transition of the clock pulse.
Bits 81 and 133 are available for flag storage.
This device has been designed to be used in high speed buffer storage systems and small recirculating memories.
Special custom configurations are achieved via single mask programming in lengths of 1 to 134 bits.
MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ................................................................O°C to + 70°C
Storage Temperature Range ............................................................... - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................... +325°C
Positive Voltage on any Pin, with respect to ground ...................................................... +8.0V
Negative Voltage on any Pin, with respect to ground ..................................................... -0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vee= +5V±5%, unless otherwise noted)
Parameter
D.C. Characteristics
INPUT VOLTAGE LEVELS
Low Level, VIL
High Level, VIH
OUTPUT VOLTAGE LEVELS
Low Level, VOL
High Level, VOH
INPUT LEAKAGE CURRENT
CLOCK, CLEAR
All Other
POWER SUPPLY CURRENT
A.C. Characteristics
CLOCK
PWH
PWL
Transition, tr, It
Repetition Rate, 1IT
t Delay
INPUT DATA
to, set-up
to, hold
PWo
OUTPUT DATA
to,ACC
RECIRCULATE CONTROL
tR, set-up
tR, hold
PWR
CLEAR
PWeLEAR

Min.

Typ.

Vec-l.5

Vee-l.5

Max.

Unit

0.8
Vee

V
V

0.4

V
V

1.0

25
10
80

pf
pf
ma

4.0

Comments

IOL=1.6ma
IOH=100~a

VIN=Vee

TA=+25°C
300
600

ns
ns
0.02

0
300

1.0
1.0

100
200
300

MHz
ns
ns
ns
ns

200
200
300
500

350

ns
ns
ns
ns

168

TIMING DIAGRAMS

Clock

PWD

to, set-up

~ to, hold

Input Data - - - - - - '
\p,ACC

Output Data

_________~r~·)----~~
.

~
1-J::ij-

Recirculate

Control

tR set-up

tR hold

PWR

PWclear

Clear~'"

Description ot Pin Functions
Symbol

Name

Function

Input A

RECABC

Recirculate ABC

ClR

Clear

4
5
6
7
8
9

B
OB
GNO
Vee
Oc
ClK

InputB
OutputB
GNO
+5 Volt
OutputC
Clock Input

10
11
12

C
NC
RECO

InputC
NC
Recirculate
Control 0

Input signal which is either high or low depending on what
word is to be loaded into shift register.
Input signal when high disconnects inputs from registers
and connects outputs to inputs, thus recirculating
data. Recirculates only A, B, C outputs.
Input signal when high forces outputs to a low state
immediately and clears all the registers.
Input signal for B register.
Output signal for B register.
Power supply Ground.
5 volt power supply.
Output signal for C register.
Input signal which is normally low and pulses high to
shift data into the registers. The data is clocked in on
low to high edge of clock.
Input signal for C register.

13
14
15

00
RID

Input 0
Output 0
Recirculate
Input 0
Output A

Pin No.

Input signal which is normally low and, when goes high,
disconnects Input 0 to register and connects
Recirculate Input 0 to register.
Input signal for 0 register.
Output signal for 0 register.
Input signal which is the input to the 0 register
when Recirculate Control.O is high: RECO= 1.
Output signal for A register.

169

APPLICATIONS
Line Buffer for CRT Display ... 80 Characters per line.

D·

SR5015·80

I=l
D,

VidOOf ock

J
D,

PAGE
MEMORY

ll- '--

... W
D,

... ::::::J
D,

Serial Data Output
To Monitor Electronics

... -1

SMC
CGS004L·1

UA'r.;-

CURSOR
MEMORY

~.L~

CURf

L..

... f-I
SR5015-80

I--

DECODES t - r-

RECIRCULATE

BCD

I COUNTER
SCAN I
End of Lt Clock

Line Buffer for Matrix Printer ... 132 Characters per line.
elK
- . SR5015-133

---J
0,

---J
CHARACTER
GENERATOR
ROM(s)
SMC CG4100
SERIES

-I
D.

]

INTERFACE
OR
MEMORY

W
0,

I-j

=/'0_-

Sqlenoid Driv8t'S

I-j
0,

J
,

-__

End of Line

SR5015-133

eli<

REC

L--<

From System Timing

~~~~~:~~~r rna:c~:a~i:~~~~~;r~~su~~di~~O~!~i~e~d~~o':n~~!~~~~~!ep~~~:::ort~~nZ~~~~~~~~

devices described any license undar the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

170

SR 5017
SR5018
Quad Static Shift Right/Shift Left Shift Register
Last In First Out Buffer
LIFO

FEATURES
o COMPLAMOS@ N-Channel Silicon
Gate Technology.
o Quad 81 bit or Quad 133 bit
o Directly Compatible with PL, MOS
o Operation Guaranteed from DC to
1.0MHz
o Recirculate logic on-chip
o Single + 5.0V power supply
o Low clock input capacitance
o Single phase clock at PL levels
o Clear function
o 16-pin Ceramic DIP Package

APPLICATIONS
OBi-Directional Printer
o Computers-Push Down
Stack-LIFO
o Buffer data storage-memory buffer
o Delay lines-delay line processing
o Digital filtering

PIN CONFIGURATION

1 "-../16 ~
15 )
2

INPUT 0
RID

RECD
GND

14 ~
13

INPUTC

OUTPUT A

INPUTB

LJRCON

OUTPUTB

INPUT A

RECABC

CLOCK

OUTPUT 0

CLEAR

OUTPUTC

Vee

o Telemetry Systems
o Terminals
o Peripheral Equipment

BLOCK DIAGRAM
OUTPUT A

R.EC CClNTROLABC

INPUT A

OUTPUTC

>-.......-L.)
'--..1---<. INPUT 0

">-+----L

t-----<. RECIRC.INPUT D

'--..............-< REC. CONTROL D
INPUT B

>--------1

,,"--.J---'

L/RCONTROL>---------T-;~~~~

CLOCK

171

CLEAR

INPUt 0

General Description
The SMC SR5017 and SR 5018 are quad 133 (SR 5017) and quad 81 (SR 5018) bit static shift registers utilizing SMC's
COPLAMOS® N channel silicon gate process. The COPLAMOSII> process provides high speed operation, low power
dissipation, low clock input capacitance, and requires only a single +5 volt power supply.
These shift registers can be driven by either T2L circuits or by MOS circuits and provide driving capability to MOS to T2L
circuits.
This device consists of four separate static shift registers with independent input and output terminals and logic for
loading, recirculating or shifting information right or left. This shift lett/shift right (LIR Control) control Input is common to all
registers.
The recirculate control input is common for registers A, B, and C. Register 0 has an independent recirculate control input
as well as a Recirculate Input.
A Clear input has been provided that will cause the shift register to be cleared when the input is at Vee. A single T2L clock,
input is required for operation.
The transfer of data into the register is accomplished on the low-te-high transition of the clock with the recirculate control
low. For long term data storage the clock may be stopped and held in either logic state. Recirculate occurs when the
recirculate control is high. Outpui data appears on the low-to-high transition of the clock pulse.
Bits 81 or 133 are available for flag storage.

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ...............................................................O·C to + 70·C
Storage Temperature Range ............................................................... -55·C to + 150·C
Lead Temperature (soldering, 10 sec.) ................................................................ + 325·C
Positive Voltage on any Pin, with respect to grQund .....................................................+8.0V
Negative Voltage on any Pin, with respect to ground ............. .' ...................................... -0.3V
• Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
ELECTRICAL CHARACTERISTICS (TA=O·C to 700C, Vee= +5V±5%, unless otherwise noted)
Parameter
D.C. Characteristics
INPUT VOLTAGE LEVELS
Low Level, VIL
High Level, VIH
OUTPUT VOLTAGE LEVELS
Low Level, VOL,
High Level, VOH
INPUT LEAKAGE CURRENT
CLOCK, CLEAR
All Other
POWER SUPPLY CURRENT
A.C. Characteristics
CLOCK
PWH
PWL
TranSition, tr, tf
Repetition Rate, 1fT
tOeJay
INPUT DATA
to, set-up
to, hold
PWo
OUTPUT DATA
to,ACC
RECIRCULATE CONTROL
tR, set-up
tR, hold
PWR
CLEAR
PWCLEAR

Min.

Typ.

Veo-1.5
Vco-1.5

Max.

Unit

0.8
Vee

V
V

0.4

V
V
Il-a
pf
pf
ma

4.0
1.0
25
10
100

Comments

IOL=1.6ma
IOH=1001l-a
VIN=Vec

TA=+25"C
300
600
1.0
1.0

0.02
0
500

ns
ns
Il-S
MHz
ns
ns
ns
ns

150
150
300
350

200

200
300
500

ns
ns
ns

Il-S

172

Timing Diagram

I '

Clock

pWo

to,

set~up ~ to, hold

tnput Data - - - - - - - "

It~,A~1
Output Oata -----------~~/~--~--~
'

Recirculate
Control

~
1-J:j.jtR set·up

tR hold

PWR

Shift Left/Shift Right

Control
R - - -_ _ ~;:,::;::"'_'

PWclear
\.
Clear~'"

Description of Pin Functions
Symbol

Name

D
RID

InputD
Recirculate
InputD
OutputD
Clear

00
ClR
OA
URCON

Pin
1
2
3
4

Output A
Shift left/Shift
Right Control
Input A

ClK

Clock Input

Vee
RECABC

5 Volt
Recirculate
ABC

9
10

OutputB
InputB
InputC
OutputC
GND
Recirculate
Control D

11
12
13
14
15
16

B
C
Oe
GND
RECD

5
6

Function
Input signal for b register.
Input signal which is the inpllt to the D register when recirculate
control D is high: RECD = 1.
Output signal for D register.
Input signal when high forces outputs to a low state immediately
and clears all the registers.
Output signal for A register.
Input signal which is low for loading data and for shifting right.
When UR CON is high, the register will shift left,
Input signal which is either high or low depending on what word
is to be loaded into shift register.
Input signal which is normally low and pulses high to shift data
into the registers. The data is clocked in on low to high
edge of clock.
5 volt power supply.
Input signal when high disconnects inputs from registers and
connects outputs to inputs, thus recirculating data. Recirculates
only A, B, C outputs.
Output signal for B register.
Input signal for B register.
Input signal for C register.
Output signal for C register.
Ground.
Input signal which is normally low and, when goes high,
disconnects Input D to register and connects RECIRCULATE
INPUT D to register.

173

Logic Diagram

REC

ABC "---<~.r-""

APPLICATION
Line Buffer for Bidirectional Matrix Printer ... 80/132 characters per line
ClK

SA'S017/SA 5018

,.---1.
D,

..... --I

CHARACTER
GENERATOR
ROM(s)
SMC CG4100
SERIES

--I
D.

I
I

INTERFACE
OR
MEMORY

:LIj=

D.
~

r-t

To Print Head

Solenoid Drivers

,-r--I

I
I

.... ,........

End otLine

...1, ~R 5017/SR 5018
ClK

DATA ENTRY
AND LOOP CONTROL
LOGIC
LJ""ii"CON
REC

~CROSVSTEMS
-~==.=~~.=
"'1I!Ip_0I1U1III'!IIIfIIDn""",,,",1I!Ip_0I,...

..... From System Timing

information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and :upply the best product possible.

174

Baud Bate Generator

(3lMay be custom mask programmed

175

put frequencies simultaneously for full duplex
communication.
Baud Rate Generators providing all standard baud
rates from various popular crystal frequencies are
available. In addition the baud rate generator may
be custom mask programmed for other divisors.

176

COM 5016
cOM5016T

Dual Baud Rate Generator
Programmable Divider
FEATURES
D On chip crystal oscillator or external
frequency input
D Choice of 2 x 16 output frequencies
D 16 asynch ronousl synchronous baud rates
D Direct UART/USRTI ASTRO/USYNRT
compatibility
D Full duplex communication capability
D TTL, MaS compatibility

PIN CONFIGURATION
XTALlEXT1 1
+5v 2

\..J

18 XTALlEXT2
17 fr

f. 3

16 TA

RA 4

15 Ts

Rs 5

14 Tc

Rc 6

13 To

Ro 7

12 STT

STR 8
+12v 9

11 GND
10 NC

BLOCK DIAGRAM
sn
T,
T,

REPROGRAM MABLE
FREQUENCY SELECT
ROM

XTAUEXT,

DIVIDER

•2

t•

XTAl

CLOCK

BUFFER

XTALlEXT2

R,
R,
Rc

A ,+12V
A
A GND

+5V
STR

177

General Description
The Standard Microsystems COM 5016 Dual Baud Rate Generator/Programmable Divider is an N-channel
COPLAMOS® MaS/LSI device which, from a single crystal (on-chip oscillator) or input frequency is capable of generating 32
externally selectable frequencies.
The COM 5016 is specifically dedicated to generating the full spectrum of 16 asynchronous/synchronous data communication frequencies as shown in Table 1. One of the sixteen output frequencies is externally selected by four address inputs,
on each of the independent dividers, as shown in Table 1.
Internal re-programmable ROM allows the generation of other frequencies from other crystal frequencies or input
frequencies. The four address inputs on each divider section may be strobe (150ns) or DC loaded. As the COM 5016 is adual
baud rate generator, full duplex (independent receive and transmit frequencies) operation is possible.
The COM 5016 is basically a programmable 15-stage feedback shift register capable of dividing any modulo up to
(2 1 5-1).

By using one of the frequency outputs it is possible to generate additional divisions of the master clock frequency by
cascading COM 5016's. The frequency output is fed into the XTAUEXT input on a subsequent device. In this way one crystal
or input frequency may be used to generate numerous output frequencies.
The COM 5016 can be driven by either an external crystal or TTL logic level inputs; COM 5016T is driven by TIL logic
level inputs only.

Description of Pin Functions
Pin No.

Symbol

Name

XTAL/EXTl

2
3
4-7
8

Crystal or
External Input 1
Power Supply
Vee
Receiver Output
fR
Frequency
RA, RB, Re, RD Receiver-Divisor
Select Data Bits
Strobe-Receiver
STR

10
11
12

V DD
NC
GND
STT

Power Supply
No Connection
Ground
StrobeTransmitter

13-16

TD, Te, T B, TA

XTALlEXT2

TransmitterDivisor
Select Data Bits
Transm itter
Output
Frequency
Crystal or
External Input 2

Function

This input is either one pin of the crystal package or one polarity
of the external input.
+5 volt supply
This output runs at a frequency selected by the Receiver divisor
select data bits.
The logic level on these inputs, as shown in Table 1, selects the
receiver output frequency, fRo
A high level input strobe loads the receiver data (R A, RB, Re, RD) into
the receiver divisor select register. This input may be strobed or
hard-wired to a high level.
+ 12 volt supply
Ground
A high level input strobe loads the transmitter data (TA, T B, Te, TD)
into the transmitter divisor select register. This input may be
strobed or hard-wired to a high level.
The logic level on these inputs, as shown in Table 1, selects the
transmitter output frequency, fT'
This output runs at a frequency selected by the Transmitter divisor
select data bits.
This input is either the other pin of the crystal package or the
other polarity of the external input.

For electrical characteristics, see page 185.

178

COM 5026
cOM5026T

Baud Rate Generator
Programmable Divider
FEATURES
D On chip crystal oscillator or external
frequency input
D Choice of 16 output frequencies
D 16 asynchronous/ synchronous baud rates
D Direct UART/USRTI ASTRO/USYNRT
compatibility
D TTL, MaS compatibility

PIN CONFIGURATION

XTAL/EXT1 1

"-.../

14 fouT

XTAL/EXT2 2

13 A

+5v 3

12 B

NC 4

11 C

GND 5

10 D

NC 6

+12v 7

BLOCK DIAGRAM

A
B

REPROGRAMMABLE
FREQUENCY SELECT

C
ROM

XTAL/EXT1
-;-2

DIVIDER

XTAL

CLOCK

BUFFER

XTALlEXT2

+5V

179

,l
GND

+12V

fOUT

GENERAL DESCRIPTION
The Standard Microsystems COM 5026 Baud Rate Generator/Programmable Divider is an N-channel COPLAMOS@
MaS/LSI device which, from a single crystal (on-chip oscillator) or input frequency is capable of generating 16 externally
selectable frequencies.
The COM 5026 is specifically dedicated to generating the full spectrum of 16 asynchronous/synchronous data communication frequencies as shown in Table 1. One of the sixteen output frequencies is externally selected by four address inputs,
as shown in Table 1.
Internal re-programmable ROM allows the generation of other frequencies from other crystal frequencies or input
frequencies. The four address inputs may be strobe (150ns) or DC loaded.
The COM 5026 is basically a programmable 15-stage feedback shift register capable of dividing any modulo up to (2'L 1).
By using the frequency output, it is possible to generate additional divisions of the master clock frequency by
cascading COM 5026's. The frequency output is fed into the XTALJEXT input on a subsequent device. In this way one crystal or
input frequency may be used to generate numerous output frequencies.
The COM 5026 can be driven by either an external crystal or TTL logic level inputs; COM 5026T is driven by TTL logic level
inputs only.

Description of Pin Functions
Pin No.

Symbol

Name

Function

XTALJEXT1

Crystal or
External Input 1

This input is either one pin of the crystal package or one polarity
of the external input.

XTALJEXT2

Crystal or
External Input 2

This input is either the other pin of the crystal package or the
other polarity of the external input.

Vee

Power Supply

+5 volt Supply

4,6,8

No Connection

GND

Ground

VDD

Power Supply

+ 12 volt Su pply

Strobe

A high-level strobe loads the Input Address (AA, As, Ae, AD)
into the Input Address register. This input may be strobed or
hard wired to a high-level,

AD. Ae. As. AA

Input Address

The logic level on these inputs. as shown in Table 1, selects
the output frequency.

fouT

Output
Frequency

This output runs at a frequency as selected by the Input Address.

10-13
14

For electrical characteristics, see page 185.

180

COM 5036
cOM5036T

Dual Baud Rate Generator
Programmable Divider
FEATURES

PIN CONFIGURATION

D On chip crystal oscillator or external

XTAL/EXT1 1

frequency input

D Choice of 2 x 16 output frequencies

18 XTALlEXT2

\.......I

+5v 2

016 asynchronous/synchronous baud rates
o Direct UART/USRT/ ASTRO/USYNRT
compatibility
Fu" duplex communication capability
o High frequency reference output
TTL, MaS compatibility

o
o

17 fT

fR 3

16 TA

RA 4

15 Ta

Ra 5

14 Tc

Rc 6

13 To

Ro 7

12 STT

STR 8

11 GND

+12v 9

10 fx/4

BLOCK DIAGRAM
STT

T.
T.

REPROGRAM MABLE
·FREQUENCY SELECT

XTAUEXT1

DIVIDER

XTAL

1,/4

CLOCK
BUFFER

XTALlEXT2

DIVIDER

R.
R.
Rc
Ro

A GND
A +12v
A

+5v
STR

181

General Description
The Standard Microsystems COM 5036 Dual Baud Rate Generator/Programmable Divider is anN-channel COPLAMOS® MOS/LSI device which, from a single crystal (on-chip oscillator) or input frequency is capable of generating 32
externally selectable frequencies.
The COM 5036 is specifically dedicated to generating the full spectrum of 16 asynchronous/synchronous data communication frequencies as shown in Table 1. One of the sixteen output frequencies is externally selected by four address inputs,
on each of the independent dividers, as shown in Table 1.
Internal re-programmable ROM allows the generation of other frequencies from other crystal frequencies or input
frequencies. The four address inputs on each divider section may be strobe (150ns) or DC loaded. As the COM 5036 is a dual
baud rate generator, full duplex (independent receive and transmit frequencies) operation is possible.
The COM 5036 is basically a programmable 15-stage feedback shift register capable of dividing any modulo up to
(2 1 5-1).
By using one of the frequency outputs it is possible to generate additional divisions of the master clock frequency by
cascading COM 5036's. The frequency output is fed into the XTAUEXT input on a subsequent device. In this way one crystal
or input frequency may be used to generate numerous output frequencies.
The COM 5036 can be driven by either an external crystal or TTL logic level inputs; COM 5036T is driven by TTL logic
level inputs only.
The COM 5036 provides a high frequency reference output at one-quarter (1/4) the XTAUEXT input frequency.

Description of Pin Functions
Pin No.

Symbol

Name

XTAL/EXT1

2
3
4-7
8

Crystal or
External Input 1
Power Supply
Vee
Receiver Output
fR
Frequency
RA, Rs, Re, Ro Receiver-Divisor
Select Data Bits
Strobe-Receiver
STR

10
11
12

Voo
fx/4
GND
STT

Power Supply
fx/4
Ground
StrobeTransmitter

13-16

To, T e, T s, TA

XTALlEXT2

TransmitterDivider
Select Data Bits
Transmitter
Output
Frequency
Crystal or
External Input 2

Function

This input is either one pin of the crystal package or one polarity
of the external input.
+ 5 volt supply
This output runs at a frequency selected by the Receiver divisor
select data bits.
The logic level on these inputs, as shown in Table 1, selects the
receiver output frequency, fRO
A high level input strobe loads the receiver data (R A, Rs, Re, Ro) into
the receiver divisor select register. This input may be strobed or
hard-wired to a high level.
+ 12 volt supply
% crystal/clock frequency reference output.
Ground
A high level input strobe loads the transmitter data (TA' T s, T e, To)
into the transmitter divisor select register. This input may be
strobed or hard-wired to a high level.
The logic level on these inputs, as shown in Table 1, selects the
transmitter output frequency, fT'
This output runs at a frequency selected by the Transmitter divisor
select data bits.
This input is either the other pin of the crystal package or the
other polarity of the external input.

For electrical characteristics, see page 185.

182

COM 5046
cOM5046T

Baud Rate Generator
Programmable Divider
FEATURES
o On chip crystal oscillator or external
frequency input
o Choice of 16 output frequencies
o 16 asynchronous/ synchronous baud rates
o Direct UART/USRTI ASTRO/USYNRT
compatibility
o High frequency reference output
o TTL, MaS compatibility

PIN CONFIGURATION

XTALJEXT1 1

14 fOUT

\...J

XTALJEXT2 2

13 A

+5v 3

12 B

NC 4

11 C

GND 5

10 D

NC 6

+12v 7

fx/4

BLOCK DIAGRAM

A
B
C
D

XTALlEXT1

1
~ D-LATCH h DECODE
AND
~
~ CONTROL

FREQUENCY

r,;

REPROGRAMMASLE
FREQUENCY SELECT
ROM

----- -----

DIVIDER

XTAL

CLOCK

BUFFER

XTALlEXT2

fOUT

>+4

fx/4

+5.

183

,l.

GND

+12.

GENERAL DESCRIPTION
The Standard Microsystems COM 5046 Baud Rate Generator/Programmable Divider is an N-channel COPLAMOS®
MaS/LSI device which, from a single crystal (on-chip oscillator) or input frequency is capable of generating 16 externally
selectable frequencies.
The COM 5046 is specifically dedicated to generating the full spectrum of 16 asynchronous/synchronous data communication frequencies as shown in Table 1. One of the sixteen output frequencies is externally selected by four address inputs;
as shown in Table 1.
Internal re-programmable ROM allows the generation of other frequencies from other crystal frequencies or input
frequencies. The four address inputs may be strobe (150ns) or DC loaded.
The COM 5046 is basically a programmable 15-stage feedback shift register capable of dividing any modulo up to

(21L1).
By using the frequency output, it is possible to generate additional divisions of the master clock frequency by cascading
COM 5046's. The frequency output is fed into the XTAUEXT input on a subsequent device. In this way one crystal or input
frequency may be used to generate numerous output frequencies.
The COM 5046 can be driven by either an external crystal or TTL logic level inputs; COM 5046T is driven by TIL logic
level inputs only.
The COM 5046 provides a high frequency reference output at one-quarter (1/4) the XTAUEXT input frequency.

Description of Pin Functions
Pin No.

Symbol

Name

Function

XTAUEXT1

Crystal or
External Input 1

This input is either one pin of the crystal package or one polarity
of the external input.

XTALJEXT2

Crystal or
External Input 2

This input is either the other pin of the crystal package or the
other polarity of the external input.

Vcc

Power Supply

+ 5 volt Supply.

4,6

No Connection

GND

Ground

Voo

Power Supply

+ 12 volt Supply.

fX/4

Reference
Frequency

High frequency reference output@ (1/4) fiN

Strobe

A high-level strobe loads the Input Address (AA, AB, Ac, Ao)
into the Input Address register. This input may be strobed or
hard wired to a high-level,

Ao. Ac. AB. AA

Input Address

The logic level on these inputs. as shown in Table 1, selects
the output frequency.

fouT

Output
Frequency

This output runs at a frequency as selected by the Input Address.

10-13

For electrical characteristics, see page 185.

184

ELECTRICAL CHARACTERISTICS COM5016, COM5016T, COM5026, COM5026T,
COMS036, COM5036T, COM5046, COM5046T
MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ...............................................................O'C to + 70'C
Storage Temperature Range .............................................................. -SS'C to + 1S0'C
Lead Temperature (soldering. 10 sec.) .............................................................. +32S'C
Positive Voltage on any Pin. with respect to ground .................................................... + 18 .OV
Negative Voltage on any Pin. with respect to ground .................................................... -0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.

ELECTRICAL CHARACTERISTICS (TA=O'C to 70'C. Vcc = + SV:t S%. VDD = + 12V :tS%. unless otherwise noted)
Parameter

Min.

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level. V'L
High-level. V,H
OUTPUT VOLTAGE LEVELS
Low-level.VoL

Max

Unit

Comments

0.8
Vce

V
V

excluding XTAL inputs

0.4
O.S

V
V
V

10L
1.6ma
10L
3.2ma
10H = 100J,.tA

0.3

VIN = GND. excluding XTAL inputs

S
8

10
10

VIN = GND. excluding XTAL inputs
Series 7400 unit loads

28
12

4S
22

mA
mA

Typ.

2.0

High-level. VOH
INPUT CURRENT
Low-level. III
INPUT CAPACITANCE
All inputs. C'N
EXT INPUT LOAD
POWER SUPPLY CURRENT
lee
IDD
A.C. CHARACTERISTICS
CLOCK FREQUENCY
PULSE WIDTH
Clock
Strobe
INPUT SET-UP TIME
Address
INPUT HOLD TIME
Address
STROBE TO NEW FREQUENCY DELAY

Vee-1.S

4.0

MHz

S.0688

1S0

SO
SO
3.S

=
=

TA = +2S'C
XTAL. EXT

SO% Duty Cycle :tS%
See Note 1.

See Note 1.

ns
J,.ts

= 1 II'N (18)

Note1: Input set-up time can be decreased to ~ Ons by increasing the minimum strobe width by SOns to a total 01 200ns.
TIMING DIAGRAM

----+---r---+':l.....------------""'\.
,,

NOTE 1

STROBE (ST)

V , L - - -....- - - J

V,H
ADDRESS
V,L
*Address need only be valid during the last Tpw, Min time of the input strobe.

185

Crystal Operation
COM5016
COM5036

r---1D

External Input Operation
COM5016/COM5016T
COM5036/COM5036T

5.0688 MHz

crystal

74XX

TTL

74XX-totem pole or open collector output (external
pull-up resistor required)

External Input Operation
COMS026/COMS026T
COM5046/COM5946T

Crystal Operation
COMS026
COMS046

74XX

TTL

74XX-totem pole or open collector output (external
pull-up resistor required)

For ROM re-programming SMC has a computer program available whereby the customer
need only supply the input frequency and the desired output frequencies.
The ROM programming is automaticaliy generated.

Crystal Specifications
User must specify termination (pin, wire, other)
Prefer: HC-18/U or HC-25/U
Frequency -

5.0688 MHz, AT cut

Temperature range O°C to 70°C
Series resistance <50 n
Series Resonant
Overali tolerance ± .01 %
or as required

186

Crystal manufacturers

(Partial List)

Northern Engineering Laboratories
357 Beloit Street
Burlington, Wisconsin 53105
(414) 763-3591
BuloYa Frequency Control Products
61-20 Woodside Avenue
Woodside, New York 11377
(212) 335-6000
CTS Knights ,Inc.
101 East Church Street
Sandwich. Illinois 60548
(815) 786-8411
Crystek Crystals Corporation
1000 Crystal Drive
Fort Myers, Florida 33901
(813) 936-2109

APPLICATIONS INFOnMATION
+5.0v

Charge pump techniques
using the + 5 volt power
supply can be used to
generate the + 12 volt
power supply required.
The + 12 volt power
supply offigure 1 will
supply the 22 mill i- amps
that is typically required.

+12v
OUT
12v

280n

1 Otlf
.

Figure 1

100pf

VOLTAGE CHARGE PUMP
SUPPLY FOR +12v SUPPLY

To Chip Power
Supply Pin

From Power
Supply

When powering this device from laboratory - - - - - - - - . - - - - - - - - . . - - or system power supplies, it is important
that the Absolute Maximum Ratings not be
exceeded or device failure can result. Some
power supplies exhibit voltage spikes
or "glitches" on their outputs when the AC
power is switched on and off. In addition,
voltage transients on the AC power line
may appear on the DC output. For example,
the bench power supply programmed to
1N914
Typ.
deliver + 12 volts may have large voltage
transients when the AC power is switched
on and off. If this possibility exists it is
suggested that the clamp circuit of figure 2
or a Semtech'bi-polarity silicon transient
Figure 2
suppressor such as the 1 N611 0 be used.
·SEMTECH CORPORATION
652 Mitchel Road
Newbury Park, California 91320
2.13-628-5392

187

OVER-VOLTAGE
PROTECTION
CIRCUIT

~~lCROSVS1EMSj

COM5016, COM5016T,COM5026, COM5026T,
COM5036, COM50~6t, COM5046, COM5046T

-~~=.~:~.=
wellelp_Of .... ~SO'jIIU ... IIeIp_Of'jlll'$.

Baud Rate Generator Output Frequency Options
Table 1.

(16X clock)

Table 2.

CRYSTAL FREQUENCY = 5.0688 MHz

CRYSTAL FREQUENCY

Tr'mlt/_ve

Add.....
Baud
DCBARate

Add,...
Baud
DCBARate

50/50 8338
50/504224
50/50 2880
0.018 50/502355
50/502112
50/50 1056
50/50 528
50/50 264
50/50 176
0.253 50/50 158
SO/50 132
50/50 88
50/50 86
50/50 44
48/52 33.
3.125 50/50 16

o
o
o
o
o

Erro,

o
o
o
o
o

0 0 0
50
0.8 KHz
0 0 1
75
1.2
0 1 0 110
1.76
2.152
0 1 1 134.5
2.4
1 0 0
lSO
4.8
0101300
9.6
0110600
o 1 1 1 1200 19.2
28.8
1 0 0 0 1800
10012000
32.0
10102400
38.4
10113600
57.6
76.8
11004600
11017200 115.2
11109600 153.8
1 1 1 1 19.200 307.2

0.8 KHz
1.2
1.76
2.1523
2.4
4.8
9.8
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8

CRYSTAL FREQUENCY
T'·mlt/R....ve
Add....

50
o 0 0 1 75
o 0 1 0 110
o 0 1 1 134.5
o 1 0 0 150
0101200
0110300
o 1 1 1 600
1 0 0 0 1200
1 0 0 1 1600
10102400
10113600
11004800
11017200
11109600
1 1 1 1 19.200

32XCI_

1.6KHz
2.4
3.52
4.304

4.8
6.4
9.8
19.2
38.4

57.6
76.8
115.2
153.6
230.4
307.2
614.4

1.6KHz
2.4
3.52.
4.306
4.8 .
6.4
9.6
19.2
38.4
57.6
76.8
115.2
153.6
230.4
316.8
633.6

Percent
Error

Frequency

18XCIock

T,'mltJAecelve

Add....
Baud
DCBARate

Divisor

0.8 KHz·
000050
0.8 KHz
o 0 0 1 75
1.2
1.2
o 0 1 0 110
1.76012
1.76
o 0 1 1 134.5 2.152
2.15228
2.4
2.4
o 1 0 0 150
0101300
4.8
4.8
9.6
0110600
9.6
19.2
o 1 1 1 1200
19.2
28.8
1 0 0 0 1600
28.8
10012000
32.0
32.0
10102400
38.4
38.4
57.6
10113800
57.6
76.8
76.8
11004800
11017200
115.2
115.2
11109600
153.6
153.8
307.2
1 1 1 1 19200
307.2

Error

Theoretical
F....u.noy

50/50
,
SO/SO
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
5O/SO
50/50
,

50/506144
50/504096
'
2793
50150 2284
50/502048
SO/SO 1024
50/50 512
50/50 256
'
171
SO/50 154
5D!50 128
85
5D!50 ~
50/50 32
SO/50
16

18X Clock

P..... nt

E,ror

0.01
0.02
0.01
0.24

731
733
735
737
741
743·
745
751
SO/50 6970
, 5569
5433
50/504752
,
4289
50/501920
50/501564
,
301

OUTPUT FREQUENCY OPTIONS

5018/5016T
5028/5026T
5036/5036T
5048/5046T

Divisor

2818.
2141
1920
960
480
240
160
144
120
80
60
40
30
15

-0.01
-0.19
-0.28
0.39
-0.77
-

=5.0688 MHz

Actual
F....u.noy

18XCIock

DuhNumber

Pert No.

Error

(16Xclock)

6.93406 KHz
0 0 0
6.91514
0 0 1
6.89633
o 0 1 0
o 0 1 1
6.87761
o 1 0 0
6.64049
6.82207
o 1 0 1
o 1 1 0
6.80376
o 1 1 1
6.74940
100045.45 0.7272 KHz 0.72723
0.91018
100156.68 0.91008
101058.30 0.93260
0.93290
101166.68 1.06856
1.06686
1 1 0 0 74.20 1.18720
1.18735
2.64000
1 1 0 1 165.00 2.64000
1 1 1 0 200.00 3.20000
3.20000
16.83980
1 1 1 1 1050.00 18.80000

g~gg ~~
0.007
0.01

0.8KHz .
1.2
1.7589
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
57.8258
76.8
114.306
153.6
307.2

Duty
Cyci.
% Dlvlaor

Percent

o
o

(16Xclock)

'.cent

18XCIock

CRYSTAL FREQUENCY

8;3.

CRYSTAL FREQUENCY = 4.808 MHz
Actual

Frequency

18XClock

Table 4.

50/503168
50/502112
50/501440
.08
1177
50/50 1058
50/50 792
50/50 528
50/50 264
50/50 132
50/50 88
50/50 68
50/50 44
,
33
50/50 22
3.125 50/50 16
3.125 50150
8

Table ••

Receive
Addrese
Baud
DCBARate

Actual

Frequency

0 0 0
50
0.8 KHz
0 0 1
75
1.2
.1.76
0 1 0 110
0 1 1 134.5
2.152
1 0 0 150
2.4
0101300
4.8
0110600
9.6
o 1 1 1 1200 19.2
1 0 0 0 1800
28.8
10012000
32.0
10102400
38.4
57.6
10113600
76.8
11004600
11017200 115.2
11109600 153.6
1 1 1 1 19.200 307.2

=5.0688 MHz

Actual

F_enoy

Baud
DCBARate

Theoretical

(32Xclock)

Table 3.

Tr'niItJR_ve

'wcent

(16Xclock)

=4.9152 MHz

Table 1

Table 2

Tobie 3

S10
STD
S10
STD

-5
-5
N/A
N/A

-6

-6
N/A

N/A

TableS

N/A
-30
N/A
N/A

N/A
N/A
-80"
N/A

'When Duty CyCle Is not exacUy 50%. It Is 50% ± ·10%.
"Output appears on III (pin 3) only.... Output frequency selection via FlA. Ra. Re. RD.

188

COM 8046
cOM8046T

Baud Rate Generator
Programmable Divider
FEATURES

PIN CONFIGURATION

o On chip crystal oscillator or external

frequency input
Single + 5v power supply
Choice of 32 output frequencies
32 asynchronous/synchronous baud rates
Direct UART/USRT/ ASTRO/USYNRT
compatibility
D Re-programmable ROM via CLASp®
technology allows generation of other
frequencies
D TTL, MaS compatible
D 1X Clock via fo/ 16 output
D Crystal frequency output via fx and fx/4
outputs
D Output disable via FENA

D
D
D
D

XTAL/EXT1 1
XTALlEXT2 2
+5v 3
fx 4
GND 5
fo/16 6

FENA 7
E 8

\......../

~16

15
14
13
12
11
10

A
B

C
D
ST
fx/4

9 NC

BLOCK DIAGRAM
ST>----,

REPROGRAM MABLE
FREQUENCY SELECT

B
C

DIVIDER
ROM

D
E

fo
XTALlEXT1
XTALlEXT2

XTAL

CLOCK
BUFFER

DIVIDER

fo/16
FENA

,l ).
+sv

fx/4

GND

189

General Description
The Standard Microsystems COM 8046 is an enhanced version of the COM 5046 Baud Rate
Generator. It is fabricated using SMC's patented
COPLAMOS® and CLASp® technologies and employs depletion mode loads, allowing operation from
a single + 5v supply.
The standard COM 8046 is specifically dedicated to
generating the full spectrum of 16 asynchronousl
synchronous data communication frequencies for 1X,
16X and 32X UARTI USRTI ASTRal USYNRT devices.
The COM 8046 features an internal crystal oscillator
which may be used to provide the master reference
frequency. Alternatively, an external reference may be
supplied by applying complementary TTL level signals to pins 1 and 2. Parts suitable for use only with an
external TTL reference are marked COM 8046T. TTL
outputs used to drive the COM 8046 or COM 8046T
should not be used to drive other TTL inputs, as noise
immunity may be compromised due to excessive
loading.
The reference frequency (fx) is used to provide two
high frequency outputs: one at fx and the other at
fx/4. The fx/4 output will drive one standard 7400
load, while the fx output will drive two 74LS loads.
The output of the oscillatorlbuffer is applied to the
divider for generation of the output frequency f o. The
divider is capable of dividing by any integer from 6

to 2" + 1, inclusive. If the divisor is even, the output
wilt be square; otherwise the output will be high
longer than it is low by one fx clock period. The output
of the divider is also divided internally by 16 and made
available at the fo/16 output pin. The fo/16 output will
drive one and the fo output will drive two standard
7400 TTL loads. Both the fo and fo/16 outputs can be
disabled by supplying a low logic level to the FENA
input pin. Note that the FENA input has an internal
pull-up which will cause the pin to rise to approximately Vee if left unconnected.
The divisor ROM contains 32 divisors, each 19 bits
wide; and is fabricated using SMC's unique CLASp®
technology. This process permits reduction of turnaround-time for ROM patterns.
The five divisor select bits are held in an externally
strobed data latch. The strobe input is level sensitive:
while the strobe is high, data is passed directly
through to the ROM. Initiation of a new frequency is
effected within 3.51's of a change in any of the five
divisor select bits; strobe activity is not required.
This feature may be disabled through a CLASP® programming option causing new frequency initiation to
be delayed until the end of the current fo half-cycle
All five data inputs have pull-ups identical to that
of the FENA input, while the strobe input has no
pull-up.

Description of Pin Functions
Pin No.

Symbol

Name

Function

XTALlEXT1

This input is either one pin of the crystal package or one polarity
of the external input.
This input is either the other pin of the crystal package or the other
polarity of the external input.
+ 5 volt supply
Crystall clock frequency reference output
Ground
1X clock output
A low level at this input causes the fa and fo/16 outputs to be
held high. An open or a high level at the FENA input enables the
fo and fo/16 outputs.
Most significant divisor select data bit. All open at this input is
equivalent to a logic high.
No connection
% crystall clock frequency reference output.
Divisor select data strobe. Data is sampled when this input is high,
preserved when this input is low.
Divisor select data bits. A = LSB. An open circuit at these inputs
is equivalent to a logic high.
16X clock output

XTALlEXT2

3
4
5
6
7

Vee
fx
GND
fo/16
FENA

Crystal or
External Input 1
Crystal or
External Input 2
Power Supply
fx
Ground
fo/16
Enable

9
10
11

NC
fx/4
ST

NC
fx/4
Strobe

12-15

D,C,B,A

For electrical characteristics, see page 199.

190

COM 8116
COM 8116T
Dual Baud Rate Generator
Programmable Divider
FEATURES

PIN CONFIGURATION

o On chip crystal oscillator or external
frequency input
o Single +5v power supply

XTAL/EXT1 1
+5v 2

D Choice of 2 x 16 output frequencies

fR 3

D 16 asynchronousl synchronous baud rates
D Direct UART/USRTI ASTRal USYN RT
compatibility
D Full duplex communication capability
ORe-programmable ROM via CLASp®
technology allows generation of other
frequencies
o TTL, MaS compatibility
D Com pati ble with COM 5016

\..J

18 XTALlEXT2
17 fT
16 TA

RA 4

15 T.

R. 5

14 Tc

Rc 6

13 To

Ro 7

12 STT

STR 8
NC 9

11 GND
10 NC

BLOCK DIAGRAM
STT

TA
REPROGRAMMABLE
FREOUENCY SELECT
ROM

T.
Tc
To

XTAUEXTl

DIVIDER

.. 2

DIVIDER

XTAL

CLOCK
BUFFER

XTAUEXT2

RA
R.
Rc
Ro

A
A GND

-5v
STR

191

General Description
The Standard Microsystem's COM 8116 is an enhanced version of the COM 5016 Dual Baud Rate
Generator. It is fabricated using SMC's patented
COPLAMOS® and CLASp® technologies and employs depletion mode loads, allowing operation from
a single +5v supply.
The standard COM 8116 is specifically dedicated to
generating the full spectrum of 16 asynchronousl
synchronous data communication frequencies for
16X UART/USRT devices. A large number of the frequencies available are also useful for 1X and 32X
ASTRO/USYNRT devices.
The COM 8116 features an internal crystal oscillator
which may be used to provide the master reference
frequency. Alternatively, an external reference may be
supplied by applying complementary TTL level signals to pins 1 and 18. Parts suitable for use only with
an external TTL reference are marked COM 8116T.
TTL outputs used to drive the COM 8116 or COM
8116T XTAL/EXT inputs should not be used to drive

other TTL inputs, as noise immunity may be compromised due to excessive loading.
The output of the oscillator/buffer is applied to the
dividers for generation of the output frequencies fr, fRO
The dividers are capable of dividing by any integer
from 6 to 2" + 1, inclusive. If the divisor is even, the
output will be square; otherwise the output will be
high longer than it is low by one fx clock period.
Each of the two divisor ROMs contains 16 divisors,
each 19 bits wide, and is fabricated using SMC's
unique CLASp® technology allowing up to 32 different divisors on custom parts. This process permits
reduction of turn-around time for ROM patterns.
Each group of four divisor select bits is held in an
externally strobed data latch. The strobe input is level
sensitive: while the strobe is high, data is passed directly through to the ROM. Initiation of a new frequency is effected within 3.51's of a change in any of
the four divisor select bits (strobe activity is not required). The divisor select inputs have pull-up resistors; the strobe inputs do not.

Description of Pin Functions
Pin No.

Symbol

2
3
4-7
8

Crystal or
External Input 1
Power Supply
Vee
Receiver Output
fR
Frequency
RA, RB, Re, Ro Receiver-Divisor
Select Data Bits
Strobe-Receiver
STR

10
11
12

NC
NC
GND
STT

No Connection
No Connection
Ground
StrobeTransmitter

13-16

To, Te, T B, TA

XTALlEXT2

TransmitterDivisor
Select Data Bits
Transmitter
Output
Frequency
Crystal or
External Input 2

Function

Name

XTALlEXT1

Ground
A high level input strobe loads the transmitter data (TA , T B, Te, To)
into the transmitter divisor select register. This input may be
strobed or hard-wired to a high level.
The logic level on these inputs, as shown in Table 1, selects the
transmitter output frequency, fT'
This output runs at a frequency selected by the Transmitter divisor
select data bits.
This input is either the other pin of the crystal package or the
other polarity of the external input.

For electrical characteristics, see page 199.

192

COM 8126
COM 8126T

Baud Rate Generator
Programmable Divider
FEATURES

PIN CONFIGURATION

o On chip crystal oscillator or external
frequency input

o Single + 5v power supply

XTAL/EXT1 1

o Choice of 16 output frequencies
016 asynchronous/synchronous baud rates

"-J

tOUT

XTAL/EXT2 2

13 A

+Sv 3

12 B

NC 4

11 C

o DirectUART/USRT/ ASTRO/USYNRT

compatibility
ORe-programmable ROM via CLASp®
technology allows generation of other
frequencies
o TTL, MaS compatibility
o Compatible with COM 5026

10 D

GND 5
NC 6

NC 7

BLOCK DIAGRAM

REPROGRAMMABLE
FREQUENCY SELECT

B
C

ROM

XTALlEXT1
DIVIDER

XTAL

fOUT

~
~------------~
CLOCK
BUFFER

L -__________________- - - '

XTALlEXT2

+5v

193

GND

General Description
The Standard Microsystem's COM 8126 is an enhanced version of the COM 5026 Baud Rate
Generator. It is fabricated using SMC's patented
COPLAMOS® and CLASp® technologies and employs depletion mode loads, allowing operation from
a single + 5v supply.
The standard COM 8126 is specifically dedicated to
generating the full spectrum of 16 asynchronous/
synchronous data communication frequencies for
16X UART/USRT devices. A large number of the frequencies available are also useful for lX and 32X
ASTRO/USYNRT devices.
The COM 8126 features an internal crystal oscillator
which may be used to provide the master reference
frequency. Alternatively, an external reference may be
supplied by applying complementary TTL level signals to pins 1 and 2. Parts suitable for use only with
an external TTL reference are marked COM 8126T.
TTL outputs used to drive the COM 8126 or COM
8126T XTALlEXT inputs should not be used to drive
other TTL inputs, as noise immunity may be com-

promised due to excessive loading.
The output of the oscillator/buffer is applied to the
divider for generation of the output frequency. The
divider is capable of dividing by any integer from 6
to 2" + 1, inclusive. If the divisor is even, the output
will be square; otherwise the output will be high
longer than it is low by one fx clock period.
The divisor ROM contains 16 divisors, each 19 bits
wide, and is fabricated using SMC's unique CLASp®
technology. This process permits reduction of turnaround time for ROM patterns. The four divisor select
bits are held in an externally strobed data latch. The
strobe input is level sensitive: while the strobe is high,
data is passed directly through to the ROM. Initiation
of a new frequency is effected within 3.5",s of a
change in any of the four divisor select bits (strobe
activity is not required). This feature may be disabled
through a CLASp® programming option causing new
frequency initiation to be delayed until the end of the
current fOUT half-cycle. The divisor select inputs have
pull-up resistors; the strobe input does not.

Description of Pin Functions
Pin No.

Symbol
XTALlEXTl

XTALlEXT2

3
4,6,7,8
5
9

Vee

NC
GND
ST

10-13

D,C,B,A

fOUT

Name

Function

Crystal or
External Input 1
Crystal or
External I nput 2
Power Supply
No Connection
Ground
Strobe

Divisor Select
Data Bits
Output
Frequency

Ground
A high level strobe loads the input data (A, B, C, D) into the input
divisor select register. This input may be strobed or hard-wired to
a high level.
The logic level on these inputs as shown in Table 1, selects the
output frequency.
This output runs at a frequency selected by the divisor select
data bits.

For electrical characteristics, see page 199.

194

COM 8136
COM 8136T

Dual Baud Rate Generator
Programmable Divider
FEATURES

o On chip crystal oscillator or external
frequency input
o Single + 5v power supply
o Choice of 2 x 16 output frequencies
o 16 asynch ronousl synchronous baud rates
o Direct UART/USRTI ASTRO/USYNRT
compatibility
o Full duplex communication capability
o High frequency reference output

PIN CONFIGURATION
XTALlEXT1 1

18 XTALlEXT2

+5v 2

ORe-programmable ROM via CLASP®
technology allows generation of other
frequencies
o TTL, MaS compatibility
o Compatible with COM 5036

17 fT

fR 3

16 TA

RA 4

15 T,

R, 5

14 Tc

Rc 6

13 TD

RD 7

12 STT

STR 8

11 GND

NC 9

10 fx/4

BLOCK DIAGRAM
STT

T,
T,

REPROGRAMMABLE
FREQUENCY SELECT

Tc
To

XTAL/EXT1

DIVIDER

XTAL

1X/4

CLOCK

BUFFER

XTALIEXT2

DIVIDER

A A

+5v

195

GND

General Description
The Standard Microsystem's COM 8136 is an enhanced version of the COM 5036 Dual Baud Rate
Generator. It is fabricated using SMC's patented
COPLAMOS® and CLASP® technologies and employs depletion mode loads, allowing operation from
a single +5v supply.

The output of the osc.illator I buffer is applied to the
dividers for generation of the output frequencies fT' fRO
The dividers are capable of dividing by any integer
from 6 to 2" + 1, inclusive. If the divisor is even, the
output will be square; otherwise the output will be
high longer than it is low by one fx clock period.

The standard COM 8136 is specifically dedicated to
generating the full spectrum of 16 asynchronousl
synchronous data communication frequencies for
16X UART/USRT devices. A large number of the
frequencies available are also useful for 1X and 32X
ASTRO/USYNRT devices.

The reference frequency (fx) is used to provide a high
frequency output at fx/4.

The COM 8136 features an internal crystal oscillator
which may be used to provide the master reference
frequency. Alternatively, an external reference may be
supplied by applying complementary TTL level signals to pins 1 and 18. Parts suitable for use only with
an external TTL reference are marked COM 8136T.
TTL outputs used to drive the COM 8136 or COM
8136T XTAL/EXT inputs should not be used to drive
other TTL inputs, as noise immunity may be compromised due to excessive loading.

Each of the two divisor ROMs contains 16 divisors,
each 19 bits wide, and is fabricated using SMC's
unique CLASp® technology allowing up to 32 different divisors on custom parts. This process permits
reduction of turn-around time for ROM patterns. Each
group of four divisor select bits is held in an externally
strobed data latch. The strobe input is level sensitive: while the strobe is high, data is passed directly
through to the ROM. Initiation of a new frequency is
effected within 3.51's of a change in any of the four
divisor select bits (strobe activity is not required).
The divisor select inputs have pull-up resistors; the
strobe inputs do not.

Description of Pin Functions
Pin No.

Symbol

2
3
4-7
8

Function

Name

XTAL/EXT1

Crystal or
External I nput 1
Power Supply
Vee
Receiver Output
fR
Frequency
RA, RB, Re, Ro Receiver-Divisor
Select Data Bits
Strobe-Receiver
STR

9
10
11
12

NC
fx/4
GND
STT

No Connection
fx/4
Ground
StrobeTransmitter

13-16

To, Te, TB, TA

XTALlEXT2

TransmitterDivider
Select Data Bits
Transmitter
Output
Frequency
Crystal or
External Input 2

This input is either one pin of the crystal package or one polarity
of the external input.
+ 5 volt supply
This output runs at a frequency selected by the Receiver divisor
select data bits.
The logic level on these inputs, as shown in Table 1, selects the
receiver output frequency, fRo
A high level input strobe loads the receiver data (R A, RB, Re, Ro) into
the receiver divisor select register. This input may be strobed or
hard-wired to a high level.
Y4 crystall clock frequency reference output.
Ground
A high level input strobe loads the transmitter data (TA, T B, Te, To)
into the transmitter divisor select register. This input may be
strobed or hard-wired to a high level.
The logic level on these inputs, as shown in Table 1, selects the
transmitter output frequency, fT'
This output runs at a frequency selected by the Transmitter divisor
select data bits.
This input is either the other pin of the crystal package or the
other polarity of the external input.

For electrical characteristics, see page 199.

196

COM 8146
COM 8146T

Baud Rate Generator
Programmable Divider
FEATURES
D On chip crystal oscillator or external

PIN CONFIGURATION

frequency input

D Single + 5v power supply
D Choice of 16 output frequencies
D 16 asynchronous/synchronous baud rates

XTAUEXT1 1

'-J

~14 fouT

XTAUEXT2 2

13 A

+5v 3

12 B

D Direct UART /USRT / ASTRO/USYNRT
com pati bi Iity
D High frequency reference output
D Re-programmable ROM via CLASP®
technology allows generation of other
frequencies
D TTL, MaS compatibility
D Compatible with COM 5046

NC 4

11 C

GND 5

10 0

NC 6

NC 7

afx/4

BLOCK DIAGRAM

FREQUENCY
DECODE
h
~ D-LATCH h AND
D~
f----v' CONTROL f---v'

B
C

r---XTAUEXT1

REPROGRAMMABLE
FREQUENCY SELECT
ROM

.... ~

>DIVIDER

XTAL

t--

r---- four

CLOCK
BUFFER

XTAUEXT2

>+4

fx/4

A A

+5v

197

GND

General Description
The Standard Microsystem's COM 8146 is an enhanced version of the COM 5046 Baud Rate
Generator. It is fabricated using SMC's patented
COPLAMOS~ and CLASP® technologies and employs depletion mode loads, allowing operation from
a single + 5v supply.

The output of the oscillator/buffer is applied to the
divider for generation of the output frequency. The
divider is capable of dividing by any integer from 6 to
21• + 1, inclusive. If the divisor is even, the output will
be square; otherwise the output will be high longer
than 'it is low by one fx clock period.

The standard COM 8146 is specifically dedicated to
generating the full spectrum of 16 asynchronous/
synchronous data communication frequencies for
16X UART/USRT devices. A large number of the frequencies available are also useful for 1X and 32X
ASTRO/USYNRT devices.

The reference frequency (fx) is used to provide a high
frequency output at fx/4.

The COM 8146 features an internal crystal oscillator
which may be used to provide the master referenc!,!
frequency. Alternatively, an external reference may be
supplied by applying complementary TTL level signals to pins 1 and 2. Parts suitable for use only with an
external TTL reference are marked COM 8146T. TTL
outputs used to drive the COM 8146 or COM 8146T
XTAL/EXT inputs should not be used to drive other
. TTL inputs, as noise immunity may be compromised
due to excessive loading.

The divisor ROM contains 16 divisors, each 19 bits
wide, and is fabricated using SMC's unique CLASp®
technology. This process permits reduction of turnaround time for ROM patterns. The four divisor select
bits are held in an externally strobed data latch. The
strobe input is level sensitive: while the strobe is high,
data is passed directly through to the ROM. Initiation
of a new frequ·ency is effected within 3.51's of a
change in any of the four divisor select bits (strobe
activity is not required). This feature may be disabled
through a CLASp® programming option causing new
frequency initiation to be delayed until the end of the
current fOUT half-cycle. The divisor select inputs have
pull-up resistors; the strobe input does not.

Description of Pin Functions
Pin No.

Symbol

Name

Function

XTAL/EXT1

Crystal or
External Input 1
Crystal or
External Input 2
Power Supply
No Connection
Ground
fx/4
Strobe

XTALlEXT2

3
4,6,7
5
8
9

Vee

NC
GND
fx/4
ST

10-13

D,C,B,A

fOUT

Divisor Select
Data Bits
Output
Frequency

Ground
V4 crystal! clock frequency reference output.
A high level strobe loads the input data (A, B, C, D) into the input
divisor select register. This input may be strobed or hard-wired to
ahigh level. .
The logic level on these inputs as shOwn in Table 1, selects the
output frequency.
This output runs at a frequency selected by the divisor select
data bits.

For electrical characteristics, see page 199.

198

ELECTRICAL CHARACTERISTICS COM8046, COM8046T, COM8116, COM8116T, COM8126,
COM8126T, COM8136, COM8136T, COM8146, COM8146T

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ...............................................................O°C to + 70°C
Storage Temperature Range .............................................................. - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) . . . . . . . . . . . . . . . . . . . .
. ................................. +325°C
Positive Voltage on any Pin, with respect to ground .................................................... + 8.0V
Negative Voltage on any Pin, with respect to ground .................................................... -0.3V
"Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this 'specification is not implied.
NOTE: When powering this device Irom laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device lailure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and 011.
In addition, voltage transients on the AC power line may appear on the DC output. II this possibility
exists it is suggested that a clamp circuit be used,
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vcc= + 5V:!: 5%, unless otherwise noted)
Parameter

Max.

Unit

0.8

V
V

excluding XTAL inputs

0.4
0.4
0.4

V
V
V
V

IOL = 1.6mA, lor Ixl 4,10 /16
10L = 3.2mA, lor 10' IR' IT
IOL = 0.8mA, lor Ix
IOH=-100I'A; lor lx, IOH=-50I'A

-0.1

V'N=GND, excluding XTAL inputs

10
10

V'N=GND, excluding XTAL inputs
Series 7400 equivalent loads

0.01

7.0

MHz

0.01

5.1

MHz

150

Min.

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, V"
High-level, V'H
OUTPUT VOLTAGE LEVELS
Low-level, VOl

High-level, VOH
INPUT CURRENT
Low-level, I"
INPUT CAPACITANCE
All inputs, C'N
EXT INPUT LOAD
POWER SUPPLY CURRENT
Icc
A.C. CHARACTERISTICS
CLOCK FREQUENCY, I'N

STROBE PULSE WIDTH, t pw
INPUT SET-UP TIME
tDS
INPUT HOLD TIME
tOH
STROBE TO NEW FREQUENCY DELAY

Typ.

2.0

3.5

5
8

Comments

TA= +25°C
XTAL/EXT,50% Duty Cycle :!:5%
COM 8046, COM 8126, COM 8146
XTAL/EXT,50% Duty Cycle :!:5%
COM 8116, COM 8136

200
50
3.5

ns
I'S

@ Ix=5.0 MHz

TIMING DIAGRAM

I-o------tpw --------0-1

STROBE

I---------to,

DIVISOR
SELECT
DATA

---------..1

V'H

199

Crystal Operation
COM 8116
COM 8136

....---10

External Input Operation
COM 8116/COM 8116T
COM 8136/COM 8136T

5.0688 MHz
crystal

74XX
TTL

74XX-totem pole or open collector output (external
pull-up resistor required)

Crystal Operation
COM 8126
COM 8146
COM 8046

External Input Operation
COM 8126/COM 8126T
COM 8146/COM 8146T
COM 8046/COM 8046T
74XX

74XX

TTL

74XX-totem pole or open collector output (external
pull-up resistor required)

Crystal Specifications
User must specify terminatIOn (pin, wire, other)
Prefer: HC-18/U or HC-25/U
Frequency - 5.0688 MHz, AT cut
Temperature range O°C to 70°C
Series resistance <50 n
Series Resonant
Overall tolerance:!: .01 %
or as required

Crystal manufacturers

(Partial List)

Northern Engineering Laboratories
357 Beloit Street
Burlington, Wisconsin 53105
(414) 763-3591

Bulova Frequency Control Products
61-20 Woodside Avenue
Woodside, New York 11377
(212) 335-6000

CTS Knights Inc.
101 East Church Street
Sandwich, Illinois 60548
(815) 786-8411

Crystek Crystals Corporation
1000 Crystal Drive
Fort Myers, Florida 33901
(813) 936-2109

200

COM 8046
cOM8046T

Table 2
REFERENCE FREQUENCY = 5.068800MHz
Divisor
Select

EDCBA
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010

10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

Desired
Baud
Rate
50.00
75.00
110.00
134.50
150.00
200.00
300.00
600.00
1200.00
1800.00
2400.00
3600.00
4800.00
7200.00
9600.00
19200.00
50.00
75.00
110.00
134.50
150.00
300.00
600.00
1200.00
1800.00
2000.00
2400.00
3600.00
4800.00
7200.00
9600.00
19200.00

Clock
Factor
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X

Desired
Frequency
(KHz)
1.60000
2.40000
3.52000
4.30400
4.80000
6.40000
9.60000
19.20000
38.40000
57.60000
76.80000
115.20000
153.60000
230.40000
307.20000
614.40000
0.80000
1.20000
1.76000
2.15200
2.40000
4.80000
9.60000
19.20000
28.80000
32.00000
38.40000
57.60000
76.80000
115.20000
153.60000
307.20000

Div1sor
3168
2112
1440
1177
1056
792
528
264
132
88
66
44
33
22
16
8
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16

201

Actual
Baud
Rate
50.00
75.00
110.00
134.58
150.00
200.00
300.00
600.00
1200.00
1800.00
2400.00
3600.00
4800.00
7200.00
9900.00
19800.00
50.00
75.00
110.00
134.52
150.00
300.00
600.00
1200.00
1800.00
2005.06
2400.00
3600.00
4800.00
7200.00
9600.00
19800.00

Actual
Frequency
(KHz)
1.600000
2.400000
3.520000
4.306542
4.800000
6.400000
9.600000
19.200000
38.400000
57.600000
76.800000
115.200000
153.600000
230.400000
316.800000
633.600000
0.800000
1.200000
1.760000
2.152357
2.400000
4.800000
9.600000
19.200000
28.800000
32.081013
38.400000
57.600000
76.800000
115.200000
153.600000
316.800000

Deviation
0.0000%
0.0000%
0.0000%
0.0591%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
3.1250%
3.1250%
0.0000%
0.0000%
0.0000%
0.0166%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.2532%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
3.1250%

COM 8116
C"OM8116T
COM 8126
COM 8126T

COMa136
COM 8136T
COM 8146
COM 8146T
Table 1

REFERENCE FREQUENCY = 5.068800MHZ
(STANDARD PART)
Divisior
Select

OCBA

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Desired
Baud
Rate
50.00
75.00
110.00
134.50
150.00
300.00
600.00
1200.00
1800.00
2000.00
2400.00
3600.00
4800.00
7200.00
9600.00
19200.00

Clock
Factor
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X

Desired
Frequency
(KHz)
0.80000
1.20000
1.76000
2.15200
2.40000
4.80000
9.60000
19.20000
28.80000
32.00000
38.40000
57.60000
76.80000
115.20000
153.60000
307.20000

Divisor
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16

Actual
Baud
Rate
50.00
75.00
110.00
134.52
150.00
300.00
600.00
1200.00
1800.00
2005.06
2400.00
3600.00
4800.00
7200.00
9600.00
19800.00

Actual
Frequency
(KHz)
0.800000
1.200000
1.760000
2.152357
2.400000
4.800000
9.600000
19.200000
28.800000
32.081013
38.400000
57.600000
76.800000
115.200000
153.600000
316.800000

Deviation
0.0000%
0.0000%
0.0000%
0.0166%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.2532%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
3.1250%

Table 2

REFERENCE FREQUENCY = 4.915200MHz
(COM81 __ -5)
Divisor
Select

OCBA

0000
0001
0010
0011
0100
0101
0110 0111
1000
1001
1010
1011
1100
1101
1110
1111

Desired
Baud
Rate
50.00
75.00
110.00
134.50
150.00
300.00
600.00
1200.00
1800.00
2000.00
2400.00
3600.00
4800.00
7200.00
9600.00
19200.00

Clock
Factor
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X

Desired
Frequency
(KHz)
0.80000
1.20000
1.76000
2.15200
2.40000
4.80000
9.60000
19.20000
28.80000
32.00000
38.40000
57.60000
76.80000
115.20000
153.60000
307.20000

Divisor
6144
4096
2793
2284
2048
1024
512
256
171
154
128
85
64
43
32
16

202

Actual
Baud
Rate
50.00
75.00
109.93
134.50
150.00
300.00
600.00
1200.00
1796.49
1994.81
2400.00
3614.11
4800.00
7144.19
9600.00
19200.00

Actual
Frequency
(KHz)
0.800000
1.200000
1.758983
2.152000
2.400000
4.800000
9.600000
19.200000
28.743859
31.916883
32.000000
57.825882
76.800000
114.306976
153.600000
307.200000

Deviation
0.0000%
0.0000%
0.0100%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.1949%
0.2597%
0.0000%
0.3921%
0.0000%
0.7751%
0.0000%
0.0000%

RSI

RCP

COM 8017
COM 2017

DUAL
BAUD RATE GENERATOR

UART
fT

TCP

TSO

Typical UART-Dual Baud Rate Generator Configuration
Full Duplex-Split Speed

.---------1 R•
.-----...,.--I~

BA 1 - - - - _ T 5 0

R,
COM 1871

ASTRO

BB I - - - - - R 5 1

Typical ASTRO-Baud Rate Generator Configuration

XTAL

.------1

1------.
R

~>-----I~XTAL/EXT1

"'--~-XTAL/EXT2

Typical External Oscillator Hook·Up

L..._ _ _ _ _ _ To System

+v
XTALlEXT1

--L
c=:JXTAL

COM 8XXX

To System

50-100pF
XTAL/EXT2

Generation of Communication Reference Frequency and
System Clock from a single crystal

~CROSVSTEMS
I

_M==·~~&.=
we _ _
_ _ ofllllR

Circuit diagrams utilizing 5MC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
informalion has been carefully checked and Is believed to be entirely reliable. However. no responsibility Is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

203

204

Keyboard Encoder

3)May be custom mask programmed

205

206

KR2376-XX
Keyboard Encoder Read Only Memory
FEATURES

PIN CONFIGURATION

D Outputs directly compatible with TTUDTL or

D
D
D
D
D
D

Frequency Control A

Vee

MOS logic arrays.

Frequency Control B

D External control provided for output polarity
selection.
External control provided for selection of odd
or even parity.
Two key roll-over operation.
N-key lockout.
Programmable coding with a single mask
change.
Self-contained oscillator circuit.
Externally controlled delay network provided
to eliminate the effect of contact bounce.
One integrated circuit required for complete
keyboard assembly.
Static charge protection on all input and
output terminals.
Entire circuit protected by a layer of glass
passivation.

Frequency Control C

Shift Input

X2
X3

Keyboard
Matrix

Outputs

Control I "put

'"I

Parity Invert Input

Parity Output

Data Output 88
Data Output B7

Data Output B6

Oats Output 85

Data Output 84

Data Output 83

Data Output 82

Keyboard

Data Output 81

Matrix

Strobe Output

Inputs

Ground

VGG

Strobe Control Input

Data & Strobe
Invert Input

Yl0

PACKAGE: 40-Pin D.I.P.

GENERAL DESCRIPTION
The SMC KR2376-XX is a 2376-bit Read Only Memory
with all the logic necessary to encode single pole
Single throw keyboard closures into a usable 9-bit
code. Data and strobe outputs are directly compatible
with TTLlDTL or MOS logic arrays without the use of

any special interface components.
The KR2376-XX is fabricated with low threshol::t,
P-channel technology and contains 2942 P-channel
enhancement mode transistors on a single monolithic
chip, available in a 40 pin dual-in-line package.

TYPICAL CONNECTION OF KR2376-XX
YO Y1 Y2 Y3 Y4 Y5 V6

va yg

V10

Yl0

35
34
33
32

X5
X6
X7

(~8
SPST
YO ____
V1 KEYBOARD SWITCHES

I
\

--",,/

Fig. 1

DATA OUTPUTS

207

TYPICAL SWITCH

MAXIMUM GUARANTEED RATINGSt
Operating Temperature Range ............................................... 0 0 C to +70 0 C
Storage Temperature Range ............................................• -65 0 C to +150 0 C
GND and VGG, with respect to Vcc ........................................... -20V to +0.3V
Logic Input Voltages, with respect to Vcc ..................................... -20V to +0.3V

t Stresses above those listed may cause permanent damage to the device. This is astress rating only
and functional operation of the device at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
ELECTRICAL CHARACTERISTICS
(TA = 0 0 C to +70 0 C, Vcc = +5V ±0.5V, VGG = -12V ±1.0V, unless otherwise noted)
Characteristics

CLOCK
DATA INPUT
Logic "0" Level
Logic "1" Level
Input Capacitance
INPUT CURRENT
*Control, Shift & YO
thru Y10
*Control, Shift & YO
thru Y10
Data Invert, Parity Invert
DATA OUTPUT & X OUTPUT
Logic "0" Level
Logic "1" Level
POWER CONSUMPTION
SWITCH CHARACTERISTICS
Minimum Switch Closure
Contact Closure Resistance
between X1 and Y1
Contact Open Resistance
between X1 and Y1

Min

Typ

Max

Unit

100

KHz see fig.1 footnote (**) for typical
R-C values

V
V
pf

+0.8
Vcc-1.5

Conditions

100

140

I1A

VIN=+5.0V

30
.01

50
1

I1A
I1A

VIN = Ground
VIN = -5.0V to +5.0V

+0.4

V
V
mW

IOL = 1.6mA (see fig. 7)
IOH = 1OOl1A
Nom. Power Supp. Voltages
(see fig. 8)

Vcc-1.0
140

200

see timing diagram-fig. 2
300
1 x 107

Ohm
Ohm

*Inputs with Internal Resistor to VGG

DESCRIPTION OF OPERATION
The KR2376-XX contains (see Fig. 1), a 2376-bit
ROM, 8-stage and 11-stage ring counters, an 11-bit
comparator, an oscillator circuit, an externally
controllable delay network for eliminating the effect
of contact bounce, and TTUDTL/MOS compatible
output drivers.
The ROM portion of the chip is a 264 by 9-bit
memory arranged into three 88-word by 9-bit
groups. The appropriate levels on the Shift and
Control inputs selects one of the three 88-word
groups; the 88-individual word locations are
addressed by the two ring counters. Thus, the ROM

address is formed by combining the Shift and
Control I nputs with the two ri ng counters.
The external outputs of the 8-stage ring counter
and the external inputs to the 11-bit comparatorare
wi red to the keyboard to form an X-Y matrix with the
88-keyboard switches as the crosspoints. In the
standby condition, when no key is depressed, the
two ring counters are clocked and sequentially
address the ROM; the absence of a Strobe Output
indicates that the Data Outputs are 'not valid' at
this time.

208

When a key is depressed, a single path is completed
between one output of the 8-stage ring counter
(XO thru X7) and one input of the 11-bit comparator
(YO-Y10). After a number of clock cycles, a condition
will occur where a level on the selected path to the
comparator matches a level on the corresponding
comparator input from the 11-stage ring counter.
When this occurs, the comparator generates a
signal to the clock control and to the Strobe Output
(via the delay network). The clock control stops the
clocks to the ring counters and the Data Outputs

(81-89) stabilize with the selected 9-bit code,
indicated by a 'valid' signal on the Strobe Output.
The Data Outputs remain stable until the key is
released.
As an added feature two inputs are provided for
external polarity control of the Data Outputs. Parity
Invert (pin 6) provides polarity control of the Parity
Output (pin 7) while the Data and Strobe Invert
Input (pin 20) provides for polarity control of Data
Outputs 81 thru 88 (pins 8 thru 15) and the Strobe
Output (pin 16).

SPECIAL PATTERNS

Since the selected coding of each key is defined
during the manufacture of the chip, the coding can
be changed to fit any particular application of the
keyboard. Up to 264 codes of up to 8 bits (plus one
parity bit) can be programmed into the KR2376-XX

ROM covering most popular codes such as ASC11,
E8CD1 C, Selectric, etc., as well as many specialized
codes. The ASC11 code is available as a standard
pattern. For special patterns, use Fig. 9.

TIMING DIAGRAM

Y KEYBOARD
MATRIX OUTPUT

STROBE OUTPUT

VOl f - - - - - - - - - - - - - l

L-:r/#s I-VALID---I

MINIMUM SWITCH CLOSURE

=SWITCH BOUNCE

(88'~)

+ STROBE DELAY + STROBE WIDTH

~~~~
MAXIMUM
EXPECTED

DETERMINED DETERMINED BY MINIMUM TIME
BY FREQUENCY EXTERNAL RC
REQUIRED BY
OF OPERATION
EXTERNAL
CIRCUITRY
(EXTERNAL RC)

Fig. 2
POWER SUPPLY CONNECTIONS FOR
TTLlDTL OPERATION
~12V

TTL/DTL [
LOGIC OR
SMCLOW
VOLTAGE
MOS LOGIC

+5V

OUTPUT DRIVER & "X" OUTPUT STAGE
TO KEYBOARD

Gnd

TTL/DTL
LOGIC OR
SMCLOW
VOLTAGE
MOS LOGIC

OUTPUTS

INPUTS
KR2376-XX

POWER SUPPLY CONNECTIONS FOR
MOS OPERATION

r~~~OUT
INL
r
Vee

V••

INPUTS

OUTPUTS
KR2376-XX
~

Vee

"Y" INPUT STAGE FROM KEYBOARD

-17V

FROM HIGH OR [
LOW VOLTAGE
MOS OR TTL/DTL
REFERENCED
TO -5V

~JV.NO

TO HIGH
OR LOW
VOLTAGE
MOS

_ _ _ _...J

Fig. 3

"Y"
KEYBOARD
INPUT

~
T
.

/'
STATIC CHARGE
PROTECTION DEVICE

T
Vee

COUNTER
INPUT

Flg.4

209

TO
INTERNAL
GATING

STROBE
DELAY
VS.C 1
.0025¢

.002pf

(.J

.0015¢

.00111f

(.J

.5OOpf

200

/
w
(.J

120

(.J

R • 680KQ
TA '" 25°C
Nom. Supp. Voltage-

160
Nolm.

.\'Nom. $upp. Voltage

40
00

TYP. POWER
CONSUMPTION
VS. TEMPERATURE

RI'loo~Q
TA=25°C

"a. 160

/
I

TYP. OUTPUT
ON RESISTANCE
VS. GATE
BIAS VOLTAGE

OSCILLATOR
FREQUENCY
VS.C 2

I 120

~ 150

iii

§
a:

'" -

r--

DELAY - msec

100

0 35

FREQUENCY - KHz

Fig. 5

Vee

.......

~ 140

, 80 1-+-I---l7~

r-...

=+5V

=-12V

VaG

130

120

slupp,l VOlt~ge

......

20 30 40

Vas - Volts

TEMPERATURE - °C

Fig.7

Fig.8

Fig. 6

t"---

DATA (B1-B8) INVERT
TRUTH TABLE

CODE ASSIGNMENT CHART
KR2376-ST
8 Bit ASCII. odd parity

DATA & STROBE
CODEDATA
INVERT INPUT ASSIGNMENT OUTPUTS
(Pin 20)
CHART
(81-B8)

STROBE INVERT
TRUTH TABLE
DATA & STROBE
INVERT INPUT
(Pin 20)

INTERNAL
STROBE

STROBE
OUTPUT
(Pin 16)

PARITY INVERT
TRUTH TABLE
PARITY
INVERT INPUT
(Pin 6)

CODE
ASSIGNMENT
CHART

PARITY
OUTPUT
(Pin7)

MODE SELECTION
S C=N
S C=S

5 c=c
S C = INVALID (SPURIOUS DATA)

Fig. 9
s
e1 B2 83 B4 85 86 B7 88
~ICi
.xO
i

l-J.-~--------.Y9

if"" PARITYBIT

123456789

___ --...-..... NORMAL

i/l-L-----------_a_-- --+ SHIFT

i---- ----.----- --+ CONTROL

(Code representative of key depression at

N =Normal Mode
S = Shift Mode
C = Control Mode

• =Output logic "1" (see data 81-88)
logic "1" = +S.OV

location XO-Y9 and proper mode selection)

Logic ''0''

=Ground

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications: Gonsequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey. to the p'urchaserof the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

210

KR3600-XX
KR3600-ST
KR3600-STD
KR3600-PRO
Keyboard Encoder Read Only Memory
FEATURES

PIN CONFIGURATION

• Data output directly compatible with TTL
• N Key rollover or lockout operation
• Quad mode
• Lockout/rollover selection externally selected as option
• On chip-master/slave oscillator
• All 10 output bits available
• Fully buffered-data outputs
• Output enable provided as option
• Data compliment control provided as option
• Pulse or level data ready output signal provided as an option
• Any key down output provided as an option
• Contact bounce circuit provided to eliminate contact bounce
• Static charge protection on all input/ outputs
';Pin for Pin replacementfor GI AY-5-3600

Function
Option
Option

Option As.;:';~ent
Option ( Chart"
Option'
Data Output B9
Data Output B8
Data Output B7
Data Output B6
Data Output B5
Data Output B4
Data Output B3
Data Output B2
Data Output B1

GENERAL DESCRIPTION

Voo

The SMC Microsystems KR3600-XX is a Keyboard Encoder
containing a 3600 bit read only memory and all the logic
necessary to encode single pole single throw keyboard
closures into a 10 bit code.
The KR3600-XX is fabricated with a low voltage p channel
technology and contains the equivalent of 5000 transistors on a
monolithic chip in a 40 lead dip ceramic package.

Data Ready

y y

•

y •

••

x,
x,
x,
x.
x.
x.
x,
x.

See

Delay Node Input
Vee
Shill Input
Control Input
V66

V.
V.
V,
V.
V.
V.

V.
V,
V,
V,
PACKAGE: 40-Pin D.I.P.

BLOeK DIAGRAM

012145""-

r----- or 18 ' 12' z, 2Z ~23 24 Z5 2S

...

... ....zI+
~

I
I

TTTTTTT

I
I
I
I
I

~~*

"'*

'0 BIT COMPARATOR

'~.-!ll+

------------,
1
I,

I,.
,.----¥'4DAT. "EADY

10 STAGE

RING COUNTER

5"'":;811~~Li~~Li~~~
IL
I =:

11
IY~
I

~~R

STROeE OE'LAY

::C2**

~------~-4-4__~_~~I~i:~.~______~~~t-~~t4-+~t4-r+-

tf-

COUNTER

L~'-~~~-r~~------i
LJ.

~~~::::~~~,~::::::~::::~~~~:t~~:t+=

110 1fT X 10 !CIVI X 4 Il001)

LJ.J.J.

OUTPUT DATA BU"E"

!! LJ. L 11

COII~w.+--+I________-oj
(amorn

____

I.,

~::::::~ 'I.~~ ~-4-4---~H~------='-----+---i-+~t4-+~H-

HOD liT ROil

-1

~
TlM'NG L
t'"tulT 1 ~
L'::===~~::::fT"T*:!*:.
"Z',.
EMNEcKMOIIYOEyOEO

r-i
1:= '"

EXTERNAL CLOCK
INPUT (OPTION)

'----

~::~:~::::~''';.~:::::::~~::::t:::~:t~:t~:t~:tt:

•
~::t:t:::!·~zt~::::::~~:::~~:::t~:~t~~t~:~t:
I
•

L
I

TTL/DTL/IIOS

~~~~rJtRS

I .
I

CHIP ENAlLE (OPTION)

L-----.hhhh+.o+,t..r,.t..t- ___________ ...t--LOtKOUTIROLLOW" (OI'T'OIII
·ll-t-t-.r.l1.~l

NOTE:

REFE" TO FIG. I FOR OPTION PIN Sl:LECTIOII •
• "1 (lOOK!1.). CI
PROVIDES APPROX. 50KHZ CLOCK "'EG•

,4,.F)

•• CI (SOOnS DELAY I CW) R2 SUPPLIED INTEIUtAU.Y.

211

• • *DtODES NDSSMY fOR COMPLETE aKEY ItOLLOV£'" (MllIlATION.

DESCRIPTION OF OPERATION
The KR3600 contains a 3600 bit ROM, 9-stage and 10-stage ring counters, a 10 bit comparator, timing
circuitry, a 90 bit memory to store the location of encoded keys for n key rollover operation, an externally controllable
delay network for eliminating the effect of contact bounce, an output data buffer, and TTLlDTLlMOS compatible
, outputd rivers.
The ROM portion of the chip is a 360 by 10 bit memory arranged into four 90-word by 1O-bit groups. The
appropriate levels on the Shift and Control Inputs selects one cif the lour 90-word groups; the 90-individual word
locations are addressed by the two ring counters. Thus, the ROM address is formed by combining the Shift and Control
Inputs with the two ring counters.
The external outputs of the 9-stage ring counter and the external inputs to the 10-bit comparator are wired to
the keyboard to, form an X-Y matrix with the 90-keyboard switches as the crosspoints. In the standby conditions, when
no key is depressed, the two ring counters are clocked and sequentially address the ROM, thereby scanning the key
switches for key closures.
When a key is depressed, a single path is completed between one output of the 9-stage ring counter (XO thru
X8) and one input of the 10-bit comparator (Yo-Yg). After a number of clock cycles, a condition will occur where a
level on the selected path to the comparator matches a level on the corresponding comparator input from the
1O-stage ring counter.
N KEY ROLLOVER - When a match occurs, and the key has not been encoded, the switch bounce delay network
is eriabled. lithe key is still depressed althe end of the selected delay time, the code forthe depressed key is transferred
to the output data buffer, the data ready signal appears, a one is stored in the encoded key memory and the scan
sequence is resumed. If a match occurs at another key location, the sequence is repeated thus encoding the next key.
If the match occurs for an already encoded key, the match is not recognized. The code of the last key encoded
remains in the output data buffer.
N KEY LOCKOUT - When a match occurs, the delay network is enabled. If the key is still depressed at the end of
the selected delay time, the code for the depressed key is transferred to the output data buffer, the data ready signal
appears and the remaining keys are locked out by halting the scan sequence. The scan sequence is resumed upon
key release. The output data buffer stores the code of the last key encoded.
SPECIAL PATTERNS-Since the selected coding.of each key and all the options are defined during the
manufacture of the chip, the coding and options can be changed to fit any particular application of the keyboard. Up
to 360 codes of up to 10 bits can be programmed into the KR3600 ROM covering most popular codes such as ASCII,
EBCDIC, Selectric, etc., as well as many specialized codes.

Pin 1

Pin2

Pin3

Pin4

PinS

Pin 1

Pin2

Pin3

Pin4

PinS

CUSTOM CODING INFORMATION
The custom coding information for SMC's
3600 Bit Keyboard Encoder ROM should
be transmitted to SMC. The Truth Table
should be completed on the format supplied.

CC
AKO
B10
LO/RO
CE
Internal Clock
External Clock

LEGEND
= Complement Control
= Any Key Down Output
= B10 (Data) Output

= Lockout/Rollover

= Chip Enable

= Self Contained Oscillator
= External Frequency Source

OPTION SELECTION/PIN ASSIGNMENT

FIGURE 1

212

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ............................................... .
ooe to +70 0 e
Storage Temperature Range ................................................. . -55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ......................................... .
+325°e
Positive Voltage on any Pin, Vcc .............................................. .
+0.3V
Negative Voltage on any Pin, Vcc ............................................. .
-25 V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other condition above those indicated in the
operational sections of this specification is not implied.
ELECTRICAL CHARACTERISTICS
(TA=Ooe to 70°C, Vcc= +5V ±5%, VGG =-12V ±1.0V, Voo=GND, unless otherwise noted)

Min

Typ··

Max

Units

Clock Frequency

100

KHz

External Clock Width

I'S

Vee
Vee-1.5

+0.8
Vee+0.3

V
V

150

220

I'A

V'N= +5V

40
600
900
1500
3000
8
6
5
2

250
1300
2000
2000
10,000
30
25
20
10
0.5

500
4000
6500
14,000
23,000
60
50
45
30
5

! 0111111001
: 1101111001
NUL 0000000001
• 0101011001
! 1000011001
7 1110111001
u 1010110101
j 0101010101
n 0111010101
= 1011111000
< 0011111001
P 0000110101
o 0000111001
& 0110011001
# 1100011001
8 0001111001
i 1001010101
k 1101010101
m 1011010101
/ 1111011001
' 1110011001
LF 0101000000
= 1011111001
FF 0011001001
( 0001011001
9 1001111001
01111010101
I 0011010101
• 0011011001
· 0111011001
: 1101111001
I 1011100101
- 1011011001
00000111001
9 1001111001

Options:
Internal oscillator (pins 1, 2, 3)
Any key down (pin 4) positive output
N key rollover only

Shift

Control

Shift Control

8-12345678910

0011111001
1000100101
1.000000101
0101100101
1001000001
0001000101
+ 1101011001
> 0111111001
@ 0000000101
! 1000011001
@ 0000000101
W 1110100101
S 1100100101
X 0001100101
RS 0111100001
% 1010011001
I 1011100101
SIllll00000l
" 0111100101
" 0100011001
# 1100011001
E 1010000101
D 0010000101
C 1100000101
- 1111100100
$ 0010011001
L 0011000101
US 1111100001
& 0110011001
[ 1101100101
$ 0010011001
R 0100100101
F 0110000101
SP 0000011000
( 0001011000
CR 1011000001
[ 1101111101
VT 1101000000
' 1110011001
" 0100011001
% 1010011001
T 0010100101
9 1110000101
V 0110100101
ETX 1100000001
I 1011111101
? 1111111001
- 1011111001
) 1001011001
SP 0000011001
> 0111111001
Y 1001100101
H 0001000101
B 0100000101
• 0101011001
> 0111111001
+ 1101011001
NUL 0000000001
• 0101011001
! 1000011001
& 0110011001
U 1010100101
J 0101000101
N 0111000101
= 1011111000
< 0011111001
P 0000100101
) 1001011001
& 0110011001
# 1100011001
• 0101011001
I 1001000101
K 1101000101
M 1011000101
? 1111111001
" 0100011001
LF 0101000000
+ 1101011001
< 0011111001
( 0001011001
( 0001011001
01111000101
L 0011000101
,0011011001
· 0111011001
: 0101111001
[ 1101100101
- 1111100101
o 0000111001
) 1001011001
Q
A
Z
HT
H

1
q
a
z
HT
H

1000111011
1000111111
1000011111
0101111111
1001000001
0001000101
+ 1101011001
SO 0111000001
NUL 0000000001
SOH 1000000001
20100111011
w 1110111111
s 1100111111
x 0001111111
RS 0111100001
% 1010011001
CR 1011000001
SI 1111000001
SO 0111000001
STX 0100000001
3 1100111011
e 1010011111
d 0010011111
c 1100011111
- 1111100100
$ 0010011001
L 0011000101
US 1111100001
ACK 0110000001
DEL 1111111101
4 0010111011
r 0100111111
f 0110011111
SP 0000011000
CAN 0001100000
CR 1011000001
[ 1101111111
VT 1101000000
BEL 1110000001
" 0100011001
5 1010111011
t 0010111111
G 1110011111
v 0110111111
ETX 1100000001
I 1011111111
? 1111111011
- 1011011001
) 1001011001
SP 0000011001
60110111011
Y 1001111111
h 0001011111
b 0100011111
: 0101111011
> 0111111011
: 1101111011
NUL 0000000001
• 0101011001
I 1000011001
7 1110111011
u 1010111111
j 0101011111
n 0111011111
= 1011111010
< 0011111011
P 0000111111
00000111011
& 0110011001
# 1100011001
80001111011
i 1001011111
k 1101011111
m 1011011111
/ 1111011001
' 1110011001
LF 0101000000
= 1011111001
FF 0011000001
( 0001011001
9 1001111011
01111011111
I 0011011111
.0011011001
.0111011001
: 1101111001
I 1011100101
- 1011011001
o 0000111001
HT 1001000001

Pulse data ready Signal
Internal resistor to Voo on shift and control pins
KR3600-STD outputs provides ASC II bits 1-6 on Bl-B6, and bit 7 on B8

215

SUB
DLE
@
P
I
H

0101100001
0000100001
0000000101
0000100101
1001000101
0001000111
+ 1101011011
SO 0111000011
NUL 0000000001
SOH 1000000001
ETB 1110100001
" 0011100101
A 1000000101
Q 1000100101
FS 0011100001
% 1010011011
CR 1011000001
SI1111000011
SO 0111000001
STX 0100000001
NAK 1010100001
DC3 1100100001
B 0100000101
R 0100100101
" 0111100100
$ 0010011011
L 0011000111
US 1111100011
ACK 0110000001
DEL 1111111101
DC4 0010100001
ENQ 1010000001
C 1100000101
SP 0000011000
BS 0001000000
M 1011000101
K 1101000101
VT 1101000010
BEL 1110000001
" 0100011011
STX 0100000001
EOT 0010000001
D 0010000101
S 1100100101
ETX 1100000001
N 0111000101
[ 1101100101
- 1011011011
) 1001011011
SP 0000011011
SOH 1000000001
DCl 1000100001
E tOl0000l0l
T 0010100101
SYN 0110100001
Z 0101100101
Y 1001100101
NUL 0000000001
• 0101011011
! 1000011011
ETX 1100000001
BEL 1110000001
F 0110000101
U 1010100101
- 0111111100
W 1110100101
J 0101000101
DC2 0100100001
& 0110011011
# 1100011011
ESC 1101100001
ACK 0110000001
G 1110000101
V 0110100101
' 1110011001
" 0100011001
GS 1011100000
+ 1101011001
FF 0011000011
( 0001011011
EM 1001100001
I 1011100101
X 0001100101
,0011011011
. 0111011011
: 0101111001
[ 1101100101
- 1111100101
o 0000111001
HT 1001000001

KR3600-ST
Normal

Shill

Control

Shift/Control

B-123458789

B-123456789

00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

\ 000001101
= 101111010
DC3 110010010
- 101101001
BS 000100010
0000011.001
• 011101001
000000000
000000000
000000000
/111101010
• 011101001
? 001101010
m 101101110
n 011101110
b 010001110
v 011011110
c 110001101
x 000111101
z 010111110
LF 010100001
\ 001110101
DEL 111111110
[ 110110110
7 111011010
8000111010
9 100111001
000000000
000000000
000000000
: 110111010
1001101101
k 110101110
j 010101101
h 000101110
9 111001110
'011001101
d 001001110
s 110011110
a 100001110
.000000000
{ 110111101
GR 101100010
' 111001001
4001011010
5 101011001
6011011001
000000000
000000000
000000000
P 000011110
0111101101
i 100101101
u 101011110
Y 100111110
t 001011101
r 010011101
• 101001101
w 111011101
q 100011101
000000000
000000000
DC2 010010001
000000000
1 100011010
2 010011010
3 110011001
000000000
000000000
000000000
0000011001
9 100111001
8000111010
7 111011010
6 011011001
5 101011001
4001011010
3110011001
2 010011010
1 100011010
000000000
000000000
000000000
000000000
000000000
SP 000001010
000000000
DCl 100010001
HT 100100001
ESC 110110001

- 011111101
+ 110101001
DC3 110010010
- 111110101
BS.0001000l0
o 000011001
• 011101001

NU L 000000001
GS 101110001
DC3 110010010
CA 101100010
BS 000100010
0000011001
• 011101001
000000000
000000000
000000000
ST 111100001
SO 011100010
FF 001100001
CA 101100010
SO 011100010
STX 010000010
SYN 011010010
ETX 110000001
CAN 000110001
SUB 010110010
LF 010100001
FS 001110010
DEL 111111110
ESC 110110001
7 111011010
8 000111010
9100111001
000000000
000000000
000000000
ESC 110110001
FF 001100001
VT 110100010
LF 010100001
BS 000100010
BEL 111000010
ACK 011000001
EOT 0010000W
DC3 110010010
SOH 100000010
000000000
ESC 110110001
GA 101100010
BEL 111000010
4 001011010
5 101011001
6 011011001
000000000
000000000
000000000
DEL 000010010
SI 111100001
HT 100100001
NAK 101010010
EM 100110010
DC4 001010001
DC2 010010001
ENQ 101000001
ETB 111010001
DCl 100010001
000000000
000000000
DC2 010010001
000000000
1 100011010
2 010011010
3 110011001
000000000
000000000
000000000
DLE 000010010
EM 100110010
CAN 000110001
ETB 111010001
SYN 011010010
NAK 101010010
DC4 001010001
DC3 110010010
DC2 010010001
DCl 100010001
000000000
000000000
000000000
000000000
000000000
NUL 000000001
000000000
DCl 100010001
HT 100100001
ESC 110110001

AS 011110001
VT 110100010
DC3 110010010
US 111110010
BS 000100010
0000011001
.011101001
000000000
000000000
000000000
US 111110010
AS 011110001
FS 001110010
CR 101100010
SO 011100010
STX 010000010
SYN 011010010
ETX 110000001
CAN 000110001
SUB 010110010
LF 010100001
FS 001110010
DEL 111111110
GS 101110001
7 111011010
8 000111010
9100111001
000000000
000000000
000000000
SUB 010110010
FF 001100001
VT 110100010
LF 010100001
BS 000100010
BEL 111000010
ACK 011000001
EOT 001000010
DC3 110010010
SOH 100000010
000000000
GS 101110001
GR 101100010
STX 010000010
4001011010
5 101011001
6011011001
000000000
000000000
000000000
DEL 000010010
SI 111100001
HT 100100001
NAK 101010010
EM 100110010
DC4 001010001
DC2 010010001
ENQ 101000001
ETB 111010001
DCl 100010001
000000000
000000000
DC2 010010001
000000000
1 100011010
2010011010
3 110011001
000000000
000000000
000000000
HT 100100001
BS 000100010
LF 010100001
ACK 011 000001
RS 011110001
ENQ 101000001
EOT 001000010
ETX 110000001
NU L 000000001
SOH 100000010
000000000
000000000
000000000
000000000
000000000
NUL 000000001
000000000
DCl 100010001
HT 100100001
ESC 110110001

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89

Options. Pm 1,2, 3-lnternal oscillator
Pin 4-Lockout (logic II, roil over (logic 0)
Pin 5-Any key d9wn output

ggggggggg
000000000
? 111111001
> 011111010
< 001111001
M 101100101
N 011100101
B 010000101
V 011010101
C 110000110
X 000110110
Z 010110101
LF 010100001
: 001111110
DEL 111111110
I 101110110
7 111011010
8000111010
9 100111001
000000000
000000000
000000000
: 010111001
L 001100110
K 110100101
J 010100110
H 000100101
G 111000101
F 011000110
D 001000101
S 110010101
A 100000101
000000000
I 101111101
GR 101100010
" 010001001
4 001011010
5 101011001
6011011001
000000000
000000000
000000000
P 000010101
o 111100110
I 100100110
U 101010101
Y 100110101
T 001010110
A 010010110
E 101000110
W 111010110
Q 100010110
000000000
000000000
DC2 010010001
000000000
1 100011010
2010011010
3 110011001
000000000
000000000
000000000
I 100101010
( 000101001
• 010101010
& 011001010
A 011110110
% 101001010
$ 001001001
# 110001010
@ 000000110
! 100001001
000000000
000000000
000000000
000000000
000000000
SP 000001010
000000000
DCl 100010001
HT 100100001
ESC 110110001
All outputs complemented

216

KR3600-PRO
XV
DO.
0.1
0.2
03
04

0.5
06
0.7
0.8
0.9
10.
11
12
13
14
15
16
17
18
19
20

21
22
23
24
25
26
27
28
29
3D
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
46
49
50.
51
52
53
54
55
56
57
58
59
60.
61
62
63
64

65
66
67
68

69
70.
71
72
73
74
75
76
77
78
79
60
81
82
83
64
85
.86
87
88
89

Normal

Shift

Control

Shift/Control

0.0.0.0.0.0000.
0.000.0.0001
0.000.0.0010.
0.000.0.0011
0.000.0.0.10.0.
0.000.0.0.10.1
'0.000.0.0.110.
Doonoolll
0.0000.1000.
0.0000.1001
0.000010.10.
0.000010.11
0.0000.110.0.
0.0000.110.1
000001110.
0.00001111
0.000.10000.
0.0001000.1
0.00010010
0.000.10.0.11
0.000.10.10.0.
0.0.0.0.10.10.1
0.0.0.0.10.110.
0.0.0.0.10.111
0.0.0.0.110.0.0.
0.0.0.0.110.0.1
0.0.0.0.110.10.
0.0.0.0.110.11
0.000.11100
0.000.1110.1
0.000.11110.
0.000.11111
0.001000.0.0.
0.001000.0.1
0.00100010.
0001000.11
00010010.0.
000.10010.1
00010.0.110.
0.0.0.10.0.111
0.0.0.10.10.0.0.
000.10.10.0.1
0.0.0.10.10.10.
0.0.0.10.10.11
0.0.0.10.110.0.
0.0010.110.1
0.0010.1110.
0.0010.1111
0.0011000.0.
0.00110.0.0.1
0.00110.0.10.
0.00110.0.11
0.00110.10.0.
0.00110.10.1
0.00110.110.
000110.111
0.0.0.1110.0.0.
0.0.0.1110.0.1
0.0.0.1110.10.
0.0.0.1110.11
0.0.0.111100
0.0.0.11110.1
0.0.0.111110.
0.0.0.111111
10.0.000000.
10.0.0.0.000.1
10.0.000010.
10.0.000011
100000.10.0.
100000.10.1
100000.110.
100000.111
10.0.001000.
1000.0.10.0.1
10.0.0010.10.
1000010.11
1000.0.110.0.
10.000.110.1
10.0.001110.
10.0.0.0.1111
10.0.0.1000.0.
10.0.0.10.0.0.1
10.0.0.10.0.10.
1000.10.0.11
10.0.0.10.10.0.
1000.10.10.1
1000.10.110.
1000.10.111
1000.110.0.0.
1000.110.0.1

0.0.1000.0.0.0.
0.0.1000.0.0.1
0.0.1000.0.10.
0.0.1000.0.11
0.0.1000.100
0.0.1000.10.1
001000.110.
0.0.1000.111
0.0.1001000
0.0.10010.0.1
0.0.10010.10.
0.0.10010.11
0010.0.1100
0010.0.110.1
0010.0.1110.
0.0.10.0.1111
0010.10.0.00
0010.10.0.0.1
0010.10.0.10.
0010.10011
0010.10.10.0.
. 0010.10.10.1
0010.10.110.
0010.10.111
0010.110.0.0.
0010.110.0.1
0010.110.10.
0010.110.11
0010.1110.0.
0.0.10.1110.1
0010.11110.
0010.11111
00110.0.0.0.0.
00110.0.0.0.1
0.0.110.0.0.10.
0011000.11
00110.0.100
00110.0.10.1
00110.0.110.
00110.0.111
00110.10.0.0.
00110.10.0.1
00110.10.10.
00110.10.11
00110.110.0.
00110.110.1
00110.1110.
0.0.110.1111
001110.0.0.0.
001110.0.0.1
001110010.
001110.0.11
00111010.0.
001110.10.1
001110.110.
001110.111
0011110.0.0.
0011110.0.1
0011110.10.
0.0.11110.11
00111110.0.
00111110.1
001111110.
001111111
10.10.0.0.0.0.0.
10.1000.0.0.1
10.1000.0.10.
10.1000.0.11
10.10.0.0.10.0.
10.1000.10.1
10.10.0.0.110.
10.10.0.0.111
10.10010.0.0.
10.10010.0.1
10.10010.10.
10.10010.11
10.1001100'
10.100110.1
10.1001110.
10.1001111
10.10.10.0.00
10.10.10.0.0.1
10.10.10.0.10.
10.10.10.0.11
10.10.10.100
lD1D1(HDl
10.10.10.110.
10.10.10.111
10.10.110.00
10.10.110.0.1

0.10.0.0.0.0.0.0.
nlDDOODDl
0.10.0.0.0.0.10.
0.10.0.000.11
0.10.00010.0.
0.10.00010.1
0.10.000110.
0.10.000111
0.10.0.0.10.0.0.
0.10.0010.0.1
0.10.0010.10.
0.10.0010.11
0.10.0.0.110.0.
0.10.0.0.110.1
0.10.0.0.1110.
0.10.0.0.1111
0.10.0.10000
0.10.0.1000.1
0.10.0.10010.
0.10.0.10011
0.10.0.10.10.0.
0.10.0.10.10.1
0.10.0.10.110.
0.10.0.10.111
0.10.0.110.0.0.
0.10.0.110.0.1
0.10.0.110.10.
0.100110.11
0.10.0.1110.0.
0.10.0.1110.1
0.10011110.
0.10.0.11111
0.10.1000.0.0.
0.10.10000.1
0.10.100010.
0.10.1000.11
0.10.10010.0.'
0.10.10010.1
0.10.10.0.110.
0.10.100111
0.10.10.10.0.0.
0.10.10.1001
0.10.10.10.10.
0.10.10.10.11
0.10.10.110.0.
0.10.10.110.1
0.10.10.1110.
0.10.10.1111
0.10.11000.0.
0.10.11000.1
0.10.110010.
0.10.110011
0.10.110.10.0.
0.10.110.10.1
0.10.110.110.
0.10.110.111
0.10.1110.0.0.
0.10.1110.0.1
0.10.1110.10.
0.10.1110.11
0.10.11110.0.
0.10.11110.1
0.10.111110.
0.10.111111
110.0.0.0000
110.0.0.0001
110.0.0.0010.
11000.0011
11000.0.10.0.
11000010.1
110.000110.
110.0.0.0.111
110.0.0.10.0.0.
110.0.0.10.0.1
110.0.0.10.10.
110.0.0.10.11
110.0.0.110.0.
110.0.0.110.1
110.0.0.1110.
110.0.0.1111
110010000
11001000.1
110010010.
110010011
110.0.10.10.0.
110010.10.1
110.0.10.110.
110.0.10.111
110.0.11000.
110.0.11001

0.110.0.0.0.0.0.
0.110.0.0.0.0.1
0.110.0.0.0.10.
0.110.0.0.0.11
0.110.0.0.10.0.
0.110.0.0.10.1
0.110.0.0.110.
0.110.0.0.111
0.110.0.10.0.0.
0.110.0.1001
0.110.0.10.10.
0.110010.11
0.110.0.1100
0.1100110.1
0.11001110.
0.11001111
0.110.10.0.00
0.110.10.0.0.1
0.110.10.0.10.
0.110.10.0.11
0.110.10.100
0.110.10.10.1
0.110.10.110.
0.110.10.111
0.110.110.00
0.110.110.0.1
0.110.110.10.
0.110.110.11
0.110.11100
0.110.1110.1
0.110.11110.
0.110.11111
0.111000.00
0.111000.0.1
0.111000.10.
0.111000.11
0.11100100
0.1110010.1
0.11100110.
0.11100111
0.1110.1000
0.1110.1001
0.1110.10.10.
0.1110.10.11
0.1110.1100
0.1110.110.1
0.1110.1110.
0.1110.1111
0.11110.0.00
0.11110.0.0.1
0.11110.0.10.
0.11110.0.11
0.11110.100
0.11110.10.1
0.11110.110.
0.11110.111
0.11111000
0.111110.0.1
0.111110.10.
0.111110.11
0.11111100
0.1111110.1
0.11111110.
0.11111111
1110.000.00
1110000.0.1
1110000.10.
1110000.11
111000100
11100010.1
111000110.
111000111
1110010.00
1110010.0.1
1110010.10.
1110010.11
11100110.0.
11100110.1
111001110.
111001111
1110.10.0.0.0.
1110.10.0.0.1
1110.10.0.10.
11,10.10.0.11
1110.10.100
1110.10.10.1
1110.10.110.
1110.10.111
1110.11000
1110.11001

Options:
Internal oscillator (pins I, 2, 3)
Lockout/rollover (pin 4), with internal resistor to VDD
Lockout is logic 1

Any key down (pin 5), positive output
Pulse data ready
Internal resistor to VDD on shilt & control pins

217

DESCRIPTION
The KR 3600 PRO is a MaS/LSI device intended tosimplify
the interface of a microprocessor to a keyboard matrix.
Like the other KR 3600 parts, the KR 3600 PRO contains all
of the logic to de-bounce al)d encode keyswitch closures,
while providing either a 2-key or N-key rollover.

Bits 2 and 3 indicate the mode as follows:
Bit2
Bit3
0
Normal
o
1
Shift
1
0
Control
1
1
Shift Control
For maximum ease of use and flexibility, an internal
scanning oscillator is used, with pin selection of N-key
lockout (also known as 2-key rollover) and N-key rollover.
An "any-key-down" output is provided for such uses as
repeat oscillator keying.
Figure 1 shows a PROM-encoded 64 key, 4 mode application, using a 256x8 PROM, and Figure2afull90key,4 mode
application, utilizing a 512x8 PROM.
If N-key rollover operation is desired, it is recommended
that a diode be inserted in series with each switchasshown.
This prevents "phantom" key closures from resulting if
three or more keys are depressed simultaneously.

The output of the KR 3600 PRO is a simple binary code
which may be converted to a standard information code
by a PROM or directly by a microprocessor. This permits
a user maximum flexibility of key layout with simple
field programming.
The code in the KR'3600 is shown in Table I. The format
is simple: output bits. 9, 8, 7, 6, 5, 4 and 1 are a binary
sequence. The count starts at XO, YO and increments
through XOY1, XOY2 ... X8Y9. Bit 9 is the LSB; bit 1 is
the MSB.

FIGURE 1
KR 3600 PRO TYPICAL APPLICATION
64 KEY, 4 MODE

FIGURE 2
KR 3600 PRO TYPICAL APPLICATION
90 KEY, 4 MODE

Any Key Down

Rollover

+5~'--4
Lockout X0

X139

"'"

X3 31

X, 39
X238

X3 37
X436
X5 35

XS 35

"34
YO

X6 34

" "

Y2 19

Y320

Y4 21
YS 22
VB 23

Y1 24

r----E

,-,i;-,\-

~.32

Data Ready

Lockout :)(0 40

""
-------E:

Any Key Down

-Rollover

+5~~4

Data Ready

er-.7.2L.t..

'4~NC

,,"
,,"
,,"
,,"

,"'

", j

A3.

"'5

,"'

AS"

6 .9

A1 19

•
~

----E
vo

11~
12.2L.,..

Y320
Vol 21

Y5 22

13.2L...,..

V6 23

14!!!......-

Y7 24

...5

,,"

","'
,
6·'

Y8 25

typical SWItch

lyplCelswltch

(N-keyrollover)

(2-keyrolloverj

~ ~/~-

-(\' _.. '::'-[:
(N·'"",,~,( \(2""""~'(

14 ~ '~+5V

+5V

218

6~
7~

"
"Y2 "
"

.2:!.....

,o~

A2,
A3

.ff
AS 19
A6 18
A7 17

AS 16

af2L.9~

11~
• 12r

'3~
14~

Microprocessor Peripheral
~

BOM

~ J'LOPPy DIll[

CA 88JlftJII/CAllTBIDGB

219

220

ROM 2316E*
IlPC FAMILY

2048 X 8-Bit Static Read-Only Memory
16K ROM
FEATURES

D
D
D
D
D
D
D
D
D

D
D

PIN CONFIGURATION

2048 x 8 Organization
All Inputs and Outputs TTL-Compatible
Fully Static (No Clocks, No Refresh)
Single +5v Power Supply
Maxi mu m Access Ti me ... 450ns
Minimum Cycle Time .. .450ns
Low Power Dissipation
Three-State Outputs for Wire-OR Expansion
Industry Standard 24 pin 01 P Pin Out
Pin Compatible with Intel 2316E and
GI R03-9316
Three programmable chip select inputs for Chip
Select Flexibility
Automated Custom Programming-FormatsMedia
COPLAMOS@N-Channel MOS Technology

24 Vee
23A8

A6 2
A5 3
A4 4

22A9
21 CS30rCS3

A3 5

20 CS1 orCS1
19A10
18CS2orCS2

A2 6

A1 7
A0 8
01 9
0210
0311

1708
1607
1506
1405
1304

GND12

PACKAGE: 24-pin D.I.P.

GENERAL DESCRIPTION
for OR-tieing multiple devices on a common bus, facilitating easy memory expansion. Three chip select controls allow data to be read. These controls are programmable, providing additional system decode flexibility
allowing eight 16K ROMs to be OR-tied without external decoding. The data is always available, it is not
dependent on external CE clocking.
The ROM 2316E is designed for high-density fixedmemory applications such as logic function generation and microprogramming.

The ROM 2316E is a 16,384-bit read-only memory
organized as 4096 words of 8-bit length. This makes
the ROM 2316E ideal for microprocessor based systems. The device is fabricated using N-channel silicongate technology for high speed and simple interface
with bipolar circuits.
All inputs can be driven directly by Series 74 TTL circuits without the use of any external pull-up resistor.
Each output can drive one Series 74 or 74S load without external resistors. The data outputs are three-state

BLOCK DIAGRAM
DATA OUTPUTS

CS1

CS2

CS3

t
t
t
I
~
'----_ _ _ _---'r----

01-08

CHIP SELECT LOGIC

X DECODE

Y DECODE

'FOR FUTURE RELEASE

221

OUTPUT BUFFERS

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ......•...•.....•.•.••.•.•••............. 0° C to + 70° C
Storage Temperature Range •....••..•....•..•..••.••..•.••.......... -55°C to +1'50°C
Lead Temperature (soldering, 10 sec.) •..•...•••..•.•..•.....•.........•.•.•••. +325°C
Positive Voltage on any Pin, with respect to ground •••...••................•..... +7.0V
Negative Voltage qn any Pin, with respect to ground ......••..•...•.....•...•.•... -:-0.3V
* Stresses above those Iisted may cause permanent da mage to the device. Th is is a stress rati ng
only and functional operation of the device at these or at any other condition above those
indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important
that the Absolute Maximum Ratings not be exceeded or device failure can result. Some
power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power is
switched on and off. In addition, voltage transients on the AC power line may appear on the
DC output. If this possibility exists it is suggested that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA = O°C to 70°C, Vee = +5V ±5%, unless otherwise noted)
D.C.

CHARA~~:;':~;CS

Min.

IN~~:_I~~~~t.~E LEVELS

High-level, V,H
OUTPUT VOLTAGE LEVELS
Low-level, VOL
High-level, VOH
INPUT CURRENT
LoW-level, I,L
OUTPUT CURRENT
10L
INPUT CAPACITANCE
All inputs, C'N
OUTPUT CAPACITANCE
All Outputs, COUT
POWER SUPPLY CURRENT
Ice

Typ.

Max.

Unit

0.65

2.0

V
V

10L = 2.0mA
10H = -200/LA

/LA

OV:5 V,N:5 Vcc

±10

/LA

Chip Deselected

10-

1 Series 74 TTL load,
CL= 100 pF
450

tares)

Previous output data valid after
address change, tpvx
Output disable time from chip
select, t pxz

ADDRESSES
V,L

:, ...

~,,,

V,H
CS1, CS2
V'L
VOH
01-08

450

ns
ns

200

450

200

..."

tC(rd)

ADDRESSES VALID

,
,

I
I

\taIOS)

~t.lad)~

(

ADDRESSES VALID

Y!//i

II
I t.-tal.d)~
tpvx"': ~
,I
VALID

.. ,,

t'I"')
'

,, ,,
,,
,' ,,

HI-Z

VOL

:~~~~:";":,\;";:"",,,,,,

0.4
2.4

Read cycle time, t Wd )
Access time from address, talad)
Access time from chip select,

V,H

:tJ\\~,~~1,<\,

A.C. CHARACTERISTICS

READ CYCLE TIMING

Comments

XNOTVALlDX

II,,

+-l
VALID

;..-tpxz

~'HI-Z-

diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applicaSTANDARD MICROSVSTEMS Circuit
tions; consequently complete information sufficient for construction purposes is not necessarily given. The
_
nlN
~~~~~~i~~r rnS:c~~;a~i;:~W~~~he~~;~~u~~4~~o~~~~~~d~e~~cii~~~!~r~~~!ep~~ha~~~rot"tj,:~:,,~~~i~~I~tlt~~
35Mim1sBMl,HauppllJge.N.Yn7\l1
(5181273-31DO·1W)(·5111·227-88118

Wl!1Ieop_ofIUQlll'llell!llnSO'jIIUtalllIeop-..solpn.

devices described any license under the patent rights of SMC or others, SMC reserves the right to make changes
at any time in order to improve design and :upply the best product possible,

222

ROM 4732
jLPCFAMILY

4096 X 8-Bit Static Read-Only Memory
32KROM
FEATURES

PIN CONFIGURATION

o 4096 x 8 Organization
o All Inputs and Outputs TTL-Compatible
o Fully Static (No Clocks, No Refresh)
o Single +5v Power Supply
o Maximum Access Time .. .450ns
o Minimum Cycle Time .. .450ns
o
o

Typical Power Dissipation ... 580mW
Three-State Outputs for Wire-OR Expansion
Industry Standard 24 pin DIP Pin Out
Pin Compatible with TMS 4732, TMS 4700,
TMS 2708 and Intel 2316E
o Two programmable chip select inputs for Chip
Select Flexibility
Automated Custom Programming-FormatsMedia
D COPLAMOS® N-Channel MOS Technology

o
o
o

A7 1
A6 2

24 Vee

AS 3
A4 4

22A9

A3 5

20CS1orCS1

A2 6
A1 7

19A10
18A11

A0 8

1708
1607

23A8
21 CS2orCS2

01 9
0210
0311

1506
1405

GND12

1304

PACKAGE: 24-pin D.I.P.

GENERAL DESCRIPTION
The ROM 4732 is a 32,768-bit read-only memory
organized as 4096 words of 8-bit length. This makes
the ROM 4732 ideal for microprocessor based
systems. The device is fabricated using N-channel
silicon-gate technology for high speed and simple
interface with bipolar circuits.
All inputs can be driven directly by Series 74 TTL
circuits without the use of any external pull-up
resistor. Each output can drive one Series 74 or 74S
load without external resistors. The data outputs
are three-state for OR-tieing multiple devices on a
common bus, facilitating easy memory expansion.
Two chip select controls allow data to be read.

These controls are programmable, providing
additional system decode flexibility allowing four
32K ROMs to be OR-tied without external decoding.
The data is always available, it is not dependent
on external CE clocking.
The ROM 4732 is designed for high-density fixedmemory applications such as logic function
generation and microprogramming. Systems
utilizing 1024 x 8-bit ROMs or 1024 x8-bit EPROMs
can expand to the 4096 x 8-bit ROM 4732 with
changes only to pins 18,19, and 21. Toupgradefrom
the 2316E, simply replace CS2 with A 11 on pin 18.

BLOCK DIAGRAM
DATA OUTPUTS

01-08
CS1 ~I
CHIP SELECT LOGIC
CS2----L.J
~L..._ _ _ _ _ _ _

I
-'r---

Y DECODE

X DECODE

223

OUTPUT BU FFERS

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ......................•.................. O°C to + 70° C
Storage Temperature Range ......................................... -55°C to +150°C
Lead Temperature (soldering, 10 sec.) ......................................... +325°C
Positive Voltage on any Pin, with respect to ground •..••• , ........................ +7.0V
Negative Voltage on any Pin, with respect to ground .............................. -0.3V
• Stresses above those I isted may cause permanent damage to the device. Th is is a stress rati ng
only and functional operation of the device at these or at any other condition above those
indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system powersupplies, it is important
that the Absolute Maximum Ratings not be exceeded or device failure can result. Some
power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power is ,
switched on and off. In addition, voltage transients on the AC power line may appear on the
DC output. If this possibility exists it is suggested that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS
(TA =O°C to 70°C, Vee =+5V ±5%, unless.otherwise noted)
Parameter

Min.

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, VIL
High-level, VIH
OUTPUT VOLTAGE LEVELS
Low-level, VOL
High-level, VOH
INPUT CURRENT
Low-level, IlL
OUTPUT CURRENT
IOL
INPUT CAPACITANCE
All inputs, CIN
OUTPUT CAPACITANCE
All Outputs, COUT
POWER SUPPLY CURRENT
lee

Typ.

Max.

Unit

0.65

V
V

0.4

V
V

oV :::;VIN

±10

Chip Deselected

150

2.0

2.4

A.C. CHARACTERISTICS

Comments

IOL =2.0mA
IOH =-~OO~A
:::;Vee

1 SerieS 74 TTL load,
CL= 100 pF
450

Read cycle time, t*d)
Access time from address, talad)
Access time from chip select,
ta(CSj

Previous output data valid after
address change, tpvx
Output disable time from chip
select, t pxz

450

ns
ns

200

450

200

READ CYCLE TIMING
VIH
ADDRESSES
VIL

ADDRESSES VALID

VIH

VIL

CS1, CS2

tel"')

VOH

ADDRESSES VALID

I I

,I' ,I
,,
,I j,
'

tale,)

~
~talad)---'"

01-08

tel"')

YIJJ1

I'
I I..-talad)~
tPilx.J ~
I
HI-Z-

HI-.Z
VOL

224

Description of Pin Functions
PIN NO.

SYMBOL

NAME

INPUT/
OUTPUT

1, 2, 3, 4, 5, 6,
7,8,18,19,22,
23

A7, A6, A5, A4,
A3,A2,A1,A0,
A11, A10, A9,
A8

Addresses

The 12-bit positive-logic address is
decoded on-chi p to select one of 4096
words of 8-bit length in the memory
array. A0 is the least significant bit and
A11 the most significant bit of the
word address. The address valid
interval determines the device
cycle time.

9,10,11,13,
14, 15, 16, 17

01, 02, 03, 04,
05, 06, 07, 08

Data
Outputs

The eight outputs must be enabled by
both chip select controls before the
output word can be read. Data will
remain valid until the address is
changed or the outputs are disabled
(chip deselected). When disabled,
the three-state outputs are in a
high-impedance state. 01 is considered the least significant bit, 08
the most significant bit. The outputs will drive TTL circuits without
external components.

GND

Ground

GND

20,21

CS1, CS2

Chip
Select

Vee

Power
Supply

225

FUNCTION

Ground

Each chip select control can be programmed during mask fabrication to
be active with either a high or a low
level input. When both chip select
signals are active, all eight outputs
are enabled and the eight-bit
addressed word can be read. When
either chip select is not active, all
eight outputs are in a highimpedance state.
,

+5 volt power supply

PROGRAMMING DATA
PROGRAMMING REQUIREMENTS: The ROM 4732 is a fixed program memory in which the
programming is performed via computer aided techniques by SMC at the factory during the
manufacturing cycle to the specific customer inputs supplied in the punched computer card
format below. The device is organized as 4096 S-bit words with address .locations numbered!D to
4095. The S-bit words can be coded as a 2-digit hexadecimal number between 00 and FF. All data
words and addresses in the following format are coded in hexadecimal numbers. In coding, all
binary words must be in positive logic before conversion to hexadecimal. Q1 is considered the
least significant bit and QS the most significant bit. For addresses, A0 is least significant bit and
A11 is the most significant bit.
Every card should include the SMC Custom Device Number in the form ROXXXX (4 digit number
to be assigned by SMC) in column 75 through SO.
PROGRAMMABLE CHIP SELECTS: The chip select inputs shall be programmed according
to the data punched in columns 73 and 74. Every card should include in column 73 a 1 if the output
is to be enabled with a high level at CS2 or a 0 (zero) to enable the output with a low level at CS2.
The column 74 entry is the same for programming CS1.
PROGRAMMED DATA FORMAT: The format for the cards to be supplied to SMC to specify
that data to be programmed is provided below. The card deck for each device consists of12Scards
with each card containing data for32 memory locations.

HEXADECIMAL FORMAT
CARD COLUMN
Hexadecimal address of first word on the card
1 to 3
4
5t06S
69, 70

71,72
73
74
75, 76
77 to SO

Blank
Data. Each S-bit memory byte is represented by two ASCII characters to
represent a hexadecimal value of '00' or 'FF'.
Checksum. The checksum is the negative of the sum of ailS-bit bytes in the
record from column 1 t06S, evalua\e modul0256 (carry from high order bit
ignored). (For purposes of calculating the checksum, the value of Column
4 is defined to be zero.) Adding together, modulo 256, ailS-bit bytes from
Column 1 to 6S (Column 4 = 0), then adding the checksum, results inzero.
Blank
One (1) or zero (0) for CS2
One (1) or zero (0) for CS1
RO
XXXX (4 digit number assigned by SMC)

ALTERNATIVE INPUT MEDIA
In addition to the preferred SO column "IBM Card," customers may submit their ROM bit patterns
on 9-track SOD-BPI mag tape, S-channel perforated paper tape, EPROM, ROM, etc. Where one
of several nationwide time sharing services is mutually available, arrangements may be made
with the factory to communicate the ROM definition data directly through the service computer.
Format requirements and other information required to use alternative input media may be
obtained through SMC sales personnel.

ALTERNATIVE DATA FILE FORMATS
In addition to the standard SMC format, it is possible to furnish data to SMC in other formats if
prearranged with the factory. Non-standard formats may be acceptable. Contact SMC
sales personnel.

226

ROM 36000*
ILPC FAMILY

8192 X 8-Bit Static Read-Only Memory
64KROM
FEATURES

PIN CONFIGURATION

D 8192 X 8 Organization
D All Inputs and Outputs TTL-Compatible

24 Vee

D Edge Activated"
D Single +5V±10% Power Supply

A6 2

23 A8

AS 3

22 A9

D
D
D
D
D
D
D
D
D
D

A4 4

21 A12

A3 5

A2 6

19 A10

18 A11

Maximum Access Time ... 250ns
Minimum Cycle Time ... 375ns
Low Power Consumption ... 220mW max active
Low Standby Power Dissipation ... 35mW typical
Three-State Outputs for Wire-OR Expansion
Industry Standard 24 Pin DIP Pin Out
Pin Compatible with MOSTEK MK36000-4
On-Chip Address Latches
Outputs drive 2 TTL loads and 100pf
COPLAMOS® N-Channel MOS Technology

A0 8

17 08

9
0210

1607

0311

1405

GND 12

1304

1506

PACKAGE: 24-pin D.I.P.

BLOCK DIAGRAM

DATA OUTPUTS

aI-as
CE_

CHIP ENABLE LOGIC
,OUTPUT BUFFERS

Y DECODE

X DECODE

'FOR FUTURE RELEASE

"Trademark of MOSTEK Corporation

227

GENERAL DESCRIPTION
The ROM 36000 is a new generation N-channel
silicon gate MOS Read Only Memory, organized as
,8192 words by 8 bits. As a state-of-the-art device,
the ROM 36000 incorporates advanced circuit
techniques designed to provide maximum circuit
density and reliability with the highest possible
performance, while maintaining low power dissipation and wide operating margins.

device and system reliability.

The ROM 36000 utilizes what is fast becoming an
industry standard method of device operation. Use
of a static storage cell with clocked control'
periphery allows the circuit to be put into an
automatic low power standby mode. This is
accomplished by maintaining the chip enable
(CE) input at a TTL high level. In this mode, P9wer
dissipation is reduced to typically 35mW, as
compared to unclocked devices which draw full
power continuously. In system operation, a device
is selected by the CE input, while all others are
in a low power mode, reducing the overall system
power. Lower power means reduced power supply
cost, less heat to dissipate and an increase in

The edge activated chip enable also means greater
system flexibility and an increase in system speed.
The ROM 36000 features onboard address latches
controlled by the CE input. Once the address.ll0ld
time specification has been met, new address data
can be applied in anticipation of the next cycle.
Outputs can be wire- 'OR'ed togethe(, and a
specific device can be selected by utilizing the CE
input with no bus conflict on the outputs. The CE
input allows the fastest access times yet available
in 5 volt only ROM's and imposes no loss in system
operating flexibility over an unclocked device.
Other system oriented features include fully TTL
compatible inputs and outputs. The three state
outputs, controlled by the
input, will drive a
minimum of 2 standard TTL loads. The ROM 36000
operates from a single +5 volt power supply with a
wide ±10% tolerance, providing the widest operating margins available. The ROM 36000 is packaged
in the industry standard 24 pin DIP.

ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Terminal Relative to Vss ........................................... -0.5V to +7V
Operating Temperature TA (Ambient) ............................................. O°C to +70°C
Storage Temperature-Ceramic (Ambient) .................................... -65°C to +150°C
Power Dissipation ...................................................................... 1 Watt
'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
f~'-""--""""""""""-""l

····"····
I
L
...__._.....--,._........_.........._..l
»'"

ELECTRICAL CHARACTERISTICS (TA
Parameter
Power Supply Voltage
Input Logic 0 Voltage
Input Logic 1 Voltage

= O°C to 70°C, Vee = +5V ±10%,. unless otherwise noted)
Symbol

Min.

Typ.

Max.

Unit

Notes

Vcc
Vil
VIH

4.5
-0.5
2.0

5.0

5.5
0.8
Vcc

Volts
Volts
Volts

mA
mA
JiA
JiA
Volts

1
7
2
3

DC ELECTRICAL CHARACTERISTICS
Vcc Power Supply Current (Active)
Vcc Pqwer Supply Current (Standby)
Input Leakage Current
Output Leakage Current
Output Logic "0" Voltage
@ lOUT = 3.3mA
Output Logic "1" Voltage
@ lOUT = -220JiA

Icc1
Icc2
II(l)
10(l)
VOL
VOH

228

7
-10
-10

2.4

10
10
0.4

Volts

Parameter

Symbol

Min.

tc
tCE
tAC
tOFF
tAH
tAS
tp

375
250

Typ.

Max.

Unit

Notes

4
4
4
4

AC ELECTRICAL CHARACTERISTICS
Cycle Time
CE Pulse Width
CE Access Time
Output Turn Off Delay
Address Hold Time Referenced to CE
Addre~s Setup Time Referenced to GE
CE Precharge Time

250
60
60

125

ns
ns
ns
ns
ns

CAPACITANCE
Input Capacitance
Out p ut Ca p acitance

5
7

CI
CO

pF
pF

5
5

NOTES:

1. Current is proportional to cycle rate. leCI is measured atthe specified
minimum cycle time.
2. VIN

5. Capacitance measured with Boonton Meter or effective capacitance
calculated from the equation:
AQ
C = J;.V with J;.V = 3 volts

= OV to 5.5V.

6. A minimum 100ps time delay is required after the application of
Vee (+5) before proper device operation is achieved.

3. Device unselected; Your = OV to 5.5V.
4. Measured with 2 TTL loads and 100pF. transition times

= 20n5.

CE high.

TIMING DIAGRAM
tc
CHIP ENABLE

V,H
V,L

V,H
ADDRESS

V,L

VOH
DATA OUTPUT V O L - - - - -

OPERATION
The ROM 36000 is controlled by the chip enable
(GE) input. A negative going edge at the CE input
will activate the device as well as strobe and latch
the inputs into the onchip address registers. At

access time the outputs will become active and
contain the data read from the selected location.
The outputs will remain latched and active until
CE is returned to the inactive state.

PROGRAMMING
Standard Microsystems Corporation will accept
data input in the form of 8K, 16K, 32K and 64K
EPROMS and 8K, 16K, 32K and 64K ROMS. If

other programming media is preferable, please
consult the factory.

229

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applicati<;ms; consequent.1y,

complete inlormation sufficient lor construction purposes Is not necessarily given. The information has been carefully checked
and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies ..Furthermore, such information

does not convey to the purchaser of the semiconductor devices descri.bed any license under the patent rights 01 SMC or others.
SMC reserves the right to make changes at any time in order to improve design and to supply the best product possible.

"'
230

FDC3400
ILPC FAMILY

Floppy Disk

Hard Sector Data Handler
HSDH
FEATURES

PIN CONFlllURATION

o Hard-Sectored Operation - performs all data
operations
o Single or Double Density Operationrecording code independent
o Minifloppy or Standard Floppy compatible
o Programmable Sync Byte
o Internal Sync Byte Detection and Byte Framing
o Fully Double Buffered
o Data Overrun/Underrun Detection
o Dual Disk Operation - Write on one disk drive
while simultaneously reading from another
o Tri-State Output Bus for processor
compatibility
o TTL Compatible I nputs and Outputs

ses

WDS

ACK
RORR
ADE
ADA
ADL
AD7
AD6
ADS
AD4
AD3
AD2

WCK
seD
34

AG
WD7

W06

'~D!~

WD5

WD4
WD3
WD2

WD'

woe

VDD

WDU

GND

WD
WDA

PACKAGE: 40-Pin D.I.P.

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

:~.:::E!iii:mEiil!C::=~====:::::;--;=====:;l

The FDC3400 is an MOS integrated circuit which
simplifies the dat~ interface between a processor
and a floppy disk drive. During a write operation,
the HSDH receives data from the processor
and shifts it out bit-serially to the floppy disk data
encoding logic. Similarly, during a read operation
the HSDH receives a bit-serial stream of read
data from the floppy disk data separator,
establishes byte synchronizl;ltion by detecting
the sync byte, and transfers data on a byte by
byte basis to the processor.
The HSDH detects data overrun and underrun
conditions and indicates these conditions on its
status lines. A data underrun causes write data
to be written onto the disk from a special
programmable fill register until new datil is
entered into the write data buffer or until the
write operation is ended.
Separate read and write data registers permit
simultaneous read and write operations on two
different drives for enhanced system throughput.
The HSDH is fully double buffered and all inputs
and outputs are TTL compatible.
ROE' _ _ _ _ _ _ _ _ _ _ _- - - '

231

DESCRIPTION OF OPERATION
Prior to reading or writing on the disk, the read/write
head must be positioned and loaded onto the desired
track.
Write Operation

The Write Clock is set at the desired bit rate (usually
125, 250, or500KHz), and the desired fill byte is written
into the Write Fill Register: After the external logic
makes the write enable to the drive active, the first
byte to be written should be loaded into the Write Data
Register. This byte is then loaded into the Write Output
Register and shifted out bit serially to the external write
encoding logic. The first bit shifted out of each byte
is the LSB. Whenever a byte is transferred from the
Write Data Register to the Write Output Register, Write
Data Request becomes active and requests another
byte from the processor. If new data is hot loaded into
the Write Data Register before the Write Output Register becomes empty, then the Write Output Register
is loaded with data from the Write Fill Register and
the Write Data Underrun status line is set. WDU is reset
the next time WDS is pulsed. At the end of the write
operation, the processor should return the external
write enable line to an inactive state.
Read Operation

The Read Clock i's set at the desired bit rate (usually
125, 250, or 500KHz) .and the desired sync byte is
loaded into the Sync Byte Register. When the processor wishes to read a sector of data it causes a
transition on the Read Gate input to set the read
logic into a sync byte search mode. In the search
mode the serial read data bit stream is examined on
a bit by bit basis until a sync byte is found. A sync
byte is found, by definition, when the contents of the
Sync Byte Register and the Read Input Register are
identical. When this occurs the Sync Byte Detected
output is set high. This byte is then loaded into the
Read Data Register and the read logic is set into the

byte mode. In this mode each byte read is loaded into
the Read Data Register and Read Data Request is
made active high for each byte. The processor responds to each Read Data Request by enabling the
output bus with Read Data Enable, reading the data
byte from the Read Data Register, and resetting Read
Data Request by pulsing Read Data Request Reset.
If the processor fails to respond to Read Data Request
within one byte time, the Read Data Lost status line is
set. When the processor has read the required amollnt
of data it may reset Read Gate to an inactive-high level.
System Operation - Additional Features

Automatic Sector Fill
In some applications, such as the end of a logical file,
the system buffer may contain less than a full sector
of data. In this case the processor need supply only
this data to the FDC3400. The FDC3400 will then underrun, setting the Write Data Underrun Status line and
thereby causing the remainder of the sector to fill with
bytes taken from the Write Fill Register. This operation
continues until the processor returns the disk's write
enable signal to an inactive level.
Byte Search
After byte synchronization has been established during
a read operation, the processor may load a different
byte into the Sync Byte Register. Whenever that byte
occurs in the data being read, the Sync Byte Detected
status line will go high. This feature permits the procesSor to search for the occurence of a specific byte
while reading a sector.
MuitipleJ3yte Synchronization
Some systems use two or more contiguous sync
bytes to .establish byte synchronization. For these applications, the number of Read Data Requests received while Sync Byte Detected remains active-high
may be counted by the processor to establish valid
synchronization.

FLOW DIAGRAM - WRITE DATA
TURN POWER ON
APPLY WCK
SET FILL BYTE ONTO WRITE DATA INPUT LINES - PULSE FBS
SET FIRST DATA BYTE ONTO WRITE DATA INPUT LINESPULSE WDS

WRITE 1 BIT

SET NEXT DATA
BYTE ONTO WRITE
DATA INPUT LlNESPULSE WDS
WDR~O

LOAD WRITE OUTPUT REGISTER
FRIllM WRITE DATA REGISTER

LOAD WRITE OUTPUT
REGISTER FROM WRITE
FILL REGISTER

WDU~O
WDR~1

WDU~1

232

FLOW DIAGRAM - READ DATA
TURN POWER ON
APPLY RCK
SET SYNC BYTE ONTO WRITE DATA INPUT LINES - PULSE SBS
PULSE RG - SETS READ LOGIC INTO SYNC BYTE
SEARCH MODE, RDR = RDL = SBD = 0

SHIFT 1 BIT INTO THE READ INPUT REGISTER

SET THE READ LOGIC INTO
THE BYTE MODE, SBD ~ 1

TRANSFER THE CONTENTS OF THE READ INPUT
REGISTER TO THE READ DATA REGISTER, RDR ~ 1

SHIFT 1 BIT INTO THE READ INPUT REGISTER

EXAMINE RDL, SBD
SET CONTENTS OF READ
DATA REGISTER ONTO
READ DATA OUTPUT LINES
VIA RDE. PULSE RDRR, RDR

SET SBD

YES

SETSBD

YES

233

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
1

SYMBOL
RD

NAME
Read Data

RCK

Read Clock

RDRR

ROE

Read Data
Request Reset
Read Data
Enable

RDR

Read Data
Request

RDL

Read Data Lost

RD7-RD0

Read Data
Output

7-14

15-19
20
21
22

NC
Vee

NC
WDR

Power Supply
Write Data
Request

Write Data

24
25

GND
WDU

Ground
Write Data
Underrun

Voo

WD0-WD7

Power Supply
Write Data
Input

Read Gate

SBD

Sync Byte
Detected

26
27-34

FUNCTION
The Read Data input accepts the serial data stream
from the floppy disk data separator.
The negative-going edge of the Read Clock input
shifts Read Data into the Read Input Register.
An active-high pulse input on the Read Data Request
Reset input resets the RDR output to a low level.
An active-high level on the Read Data Enable line
gates the outputs of the Read Data Register onto the
Read Data Output lines.
The Read Data Request output is made active-high when
an assembled byte is transferred from the Read Input
Register to theRead Data Register.
The Read Data Lost output is made active-high, if the
byte presently in the Read Data Register is not read
(RDR not reset) by the processor before the next byte is
loaded into the Read Data Register.
When enabled by RDE the tri-state Read Data Output
lines present the data in the Read Data Register to the
processor. When ROE is inactive-low the RD7-RDf/Jlines
are held at a high-impedance state.
Not Connected
+ 5 volt supply
Not Connected
The Write Data Request output is made active-high
when the Write Data Register becomes empty and
requires a data byte. It is reset to a low level when WDS
occurs to load the Write Data Register. If WDR is not
serviced by the time the next byte is required by the
Write Output Register, the byte stored in the Write Fill
Register is written onto the disk and the WDU line is
made active high.
The Write Data output presents the serial stream of data
to the external write data encoder. Each byteis normally
provided from the Write Data Register provided that a
WDS pulse occurs during the presently written byte.
If WDS is not pulsed, the next byte to be written will be
extracted from the Write Fill Register.
Ground
The Write Data Underrun output is set active-high when
the processor fails to respond to the WDR signal
within one byte time. When WDU occurs the data
written on the disk is extracted from the Write Fill
Register. This line is reset when WDSis pulsed.
12 volt supply
The Write Data Input lines present information to the
Write Data Register, the Write Fill Register, and the
Sync Byte Register under control of their respective
strobes. The strobes operate independently of each
other. The LSB should always be placed on WD0.
I nls Input snould be pUlse_o to a nlgn-Ievel aTter
power turn on to reset RDR, SBD, and RDL to an inactivelow level. The high-to-Iow transition of RG sets the read
logic into the sync byte search mode. In this mode
the serial Read Data stream is examined on a bit by bit
basis until a sync byte is found. A sync byte is found by
definition when the contents of the Sync Byte Register
and the Read Input Register are identical. When this
occurs the SBD output is set active-high. The sync byte
just read is then transferred into the Read Data Register;
RDR is set high, and the read logic is set into the byte
mode. In this mode each byte read is transferred into
the Read Data Register.
The Sync Byte Detected output is set active-high each
time the byte loaded into the Read Data Register is
identical to the byte in the Sync Byte Register. This
output is reset low the next time the Read Data Register
is loaded with a byte which is not a sync byte.

234

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
37

SYMBOL
FBS

NAME
Fill Byte
Strobe

WCK

Write Clock

WDS

Write Data
Strobe

SBS

Sync Byte
Strobe

FUNCTION
The Fill Byte Strobe is an active-high input strobe which
loads the byte on the WD0-WD71ines into the Write
Fill Register.
Each positive-going edge of this clock shifts one bit
out of the Write Output Register onto WD.
The Write Data Strobe is an active-high input strobe
which loads the byte on the WD0-WD7Iines into the
Write Data Register.
The Sync Byte Strobe is an active-high input strobe
which loads the byte on the WD0-WD7 lines into the
Sync Byte Register.

HSDH TIMING DIAGRAM

WCK

Notet n't-Ii ____

...In

WDS _ _ _ _ _ _ _
WDR

~_ _ _ __rI~'N~o~te~t--------------------,L1r-----

I ~

WDU
WD

:CT:I::C:T::T==C:::T::-=t=.:::c_:::T::-_:T'::-_::I::-'::-I'::-_::C:-J.::-.::-r.::-.::-c_::T-=-_-l.-_-J_-_-L~-CI~l~~L~J~~
,.
DATA BYTE
• , •
DATA BYTE'
• , •
FILL BYTE
_I

RCK
RD

:::I::::::C:::::I::::::CJ::::::I:::T:::T:::r==C::::T':~I:::::::C:::::J::::::[:::J::::::I::::::dJ_LI:::::::C:::J::::I::::::'::::::J::::::dT:
I'
i
-IlL__________________________+-________________-+!__r-________________-+i__
SYNC BYTE

RG
ADR

, ,.

DATA BYTE

.,.1

DATA BYTE

:~~~------__,
I Ir----------~~IL.________________..w1
I Note 3
W
I

RDRR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---'n~!N-o-te-2-------------~ir-RDL

-,L__________________________________________~I------------------~!r-

SBD

IL.______________________--li Note 3

NOTE 1
The Write Output Register is
loaded with the next byte at the
positive clock transition corresponding to the leading edge
of the last bit of the current byte
on the WD output. WDR is set
high approximately two microseconds after this clock transition. If it is desired that the
next byte be extracted from the
Write Data Register the leading
edge of the WDS should occur
at least one microsecond prior
to this clock transition.

NOTE 2
In order to avoid an RDL indication the leading edge of the
RDRR pulse should occur at
least one microsecond prior to
the negative clock transition
corresponding to the center of
the first bit after the last bit
of the previous byte on the
RD input.

236

NOTE 3
The RDL, SBD and RDO-RD7
output are set to their correct
levels approximately two microseconds after the negative
clock transition corresponding
to the center of the first bit after
the last bit of the previous byte
on the RD input. The RDR
output is set high at the next
negative clock transition.

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ........................................................ O°C to + 70°C
Storage Temperature Range ...................................................... -SsoC to + 1S0°C
Load Temperature (soldering, 10 sec.) ..................................................... +32SoC
Positive Voltage on any Pin, Vee ............................•................................. + 0.3V
Negative Voltage on any Pin, Vee ............... ; .............................................. -2SV
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the
operational sections of this specification is not implied.

ELECTRICAL CHARACTERISTICS (T,=O°C to 70°C, Vee = +SV ±S% Voo= -12V±S%, unless otherwise noted)
Parameter

Min.

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, VIL
High-level, V,H

Unit

0.8
Vee

V
V

0.4

V
V

1.6

See note 1

-1
10

I'A
mA

VOUT=OV

V,N = Vee, f=1MHz

RDE=VIL,f=1MHz

28
28

mA
mA

2S0
SOO

KHz
KHz

RCK,WCK
RCK, WCK, FDC3400-1

1
O.S
1
200
200
200
200

I'S
I'S
I'S
ns
ns
ns
ns

RCK,WCK
RCK, WCK, FDC3400-1
RG
WDS
FBS
SBS
RDRR

WD0-WD7

W00-WD7
Load = 20pf+ 1 TTL input
ROE: TpDI, TpD<)

2.4

0.2
4.0

INPUT CAPACITANCE
All inputs, C'N
OUTPUT CAPACITANCE
All outputs, COUT
POWER SUPPLY CURRENT
Icc

100
A.C. CHARACTERISTICS
CLOCK FREQUENCY
PULSE WIDTH
Clock
Read Gate
Write Data Strobe
Fill Byte Strobe
Sync Byte Strobe
ReadData Request Reset
INPUT SET-UP TIME
Write Data Inputs
INPUT HOLD TIME
Write Data Inputs
STROBE TO OUTPUT DELAY
Read Data Enable
OUTPUT DISABLE DELAY

Conditions

Max.

Voo
Vee-1.S

OUTPUT VOLTAGE LEVELS
Low-level, VOL
High-level, VOH
INPUT CURRENT
Low-level, III
OUTPUT CURRENT
Leakage, ILo
Short circuit, los··

Typ.

IOL=1.6mA
10H= -1001'A

RDE=VIL,O~VouT~

+SV

All outputs = VOH
T,= +2SoC

DC
DC

180
100

2S0
2S0

ns
ns

•• Not more than one output should be shorted at a time.

NOTES:
1. Under steady state condition no current flows for TTL or MOS interfacing.
A switching current of 1.6mA maximum flows during a high to low transition of the input.
2. The tri-state output has 3 states:
1) low-impedance to Vee
2) low-impedance to GNO
3) high-impedance OFF
10M ohms
The OFF state is controlled by the ROE input.

237

ROE

+5V -12V GND

I I I

CLOCK

VOD GND
WCK

DATA BUS

Ir
;---

-y

HSDH STATUS

--.J

TRISTATE
BUFFER

READ DATA REO
READ DATA LOST

ENABLE

SYNC BYTE DETECTEO

'----

WRITE OATA STROBE
PROCESSOR

FILL BYTE STROBE

ADDRESS BUS

CONTROL BUS

SYNC BYTE STROBE

ADDRESS·
AND
CONTROL
DECODER

READ GATE
READ DATA ENABLE
READ OATA REQUEST RESET

WRITE CLOCK
WRITE

WRITE DATA

OATA

WRITE DATA

ENCODER

RDil-7
RCK

WRITE OATA REO
WRITE DATA UNDERRUN

'--

WDIH

WDR

READ CLOCK
READ DATA

READ
DATA
SEPARATOR

READ DATA

WDU
RDR
RDL

FDC3400

SBD
WDS
FBS
SBS
RG
ROE
RDRR

r---

FLOPPY
DISK
DRIVE

I\)

(,)

READY
INDEX

TRISTATE
BUFFER
DRIVE STATUS ENABLE

SECTOR
TRACK 00
WRITE PROTECT

DIRECTION
STEP
HEAD LOAD
WRITE GATE

OUTPUT
LATCHES

DRIVE SELECT 1
DRIVE SELECT 2
DRIVE SELECT 3

DRIVE CONTROL STROBE

DRIVE SELECT 4

TYPICAL CCC 3500 INTERFACE TO PROCESSOR AND CASSETTE/CARTRIDGE DRIVE

-------------

TO OTHER
DAISY-CHAINED DRIVES,
IN SYSTEM

FOC 7003*
J.1PC FAMILY

P~
Floppy Disk Controller
FOC II
FEATURES

PIN CONFIGURATION

D FULLY PROGRAMMABLE DATA FORMATS
Single or Double Density IBM Soft-Sectored Format
(uptoSOOK bps)
Number of Sectors (up to 128)
Numberof Bytes per Sector (up to 8K)
D DATA OPERATIONS
Automatic Sector Search and Verification
Macro Read/Write Commands-Seek/Read or
Seek/WritelVerify in One Command
Multiple Sector Read/Write-via Sector Count Register
Fully Double Buffered
Write Data Verification
String Search Command-Compares Data in
Memory to Data on the Disk
Internal Address Mark Detection
CRC Data Error Checking
Data Overrun/Underrun Detection
Write Protect Capability
Write Precompensation Outputs
Optional Internal Write Precompensation
D TRACK MOTION OPERATION
Seek Command-Moves Head to Desired Track
Programmable Track-to-Track Seek Time
Selectable Head Settling Time
Programmable Head Load Delay
Up to 2S6 Tracks per Side
Programmable Head Unload Delay
Two Track Registers and Two Head Unload Timers
for Control of Two Drives
D SYSTEM INTERFACE
8-Bit Bi-Directional Three-State Bus for Transfer of
Data, Status, and Control
Byte-Oriented DMA or Programmed I/O Data Transfer
Interrupts System at Completion of Operation

D3
D2
D1

+5V

R/iN
DXACK
A0
A1
A2
A3
IDX
LATE
EARLY
WRDATA
WRENA
RDGATE
RDDATA (
RDCLK [

~
~
~
~

1
2
3
4
5
6
7
8

'-'

10
90
11
12
13
14
15
16

17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

P
P
P

D4
D5
D6
D7
SEL0
SEL1
SEL2
INT
RESET
LDHD0
LDHD1
DIR
DXRQ
STEP
GND
TRK00
TGT43
READY
4MHz

PACKAGE: 40 pin D.I.P.

Read/Write on one Drive while Seeking on another
for Enhanced System Throughput
Three On-Chip Status Registers
TTL Compatible Inputs and Outputs
+S Volt Only Operation
FLOPPY DISK INTERFACE
Controls up to 4 Double-Sided Drives
Compatible with Standard (8") Floppy Disk Drives
Compatible with Mini-Floppy (S'I4') Disk Drives

GENERAL DESCRIPTION
The FDC 7003 is a 40 pin DIP COPLAMOS® n-channel depletion-load MOS/LSI device which performs the complex interface function between a processor and a Floppy Disk Drive. The
FDC offers many features which reduce computer service
overhead resulting in greater system throughput. Forexample,
the controller performs track seek/verify, write and write
verification without processor intervention. Enhanced system
throughput is offered by the ability to seek on one drive
while reading or writing on another.
The device is capable of reading, writing, and initializing
diskettes in single or double density. It is compatible with
both the single density and double density IBM soft-sectored
formats. The FDC provides the system designer with the
flexibility needed to accommodate various disk data formats.
The number of bytes per sector, the number of sectors per
track and the number of tracks per side are fully programmable.
The FDC interfaces to a processor via an 8-bit bi-directional
three-state bus. This assures efficient data transfer and
processor compatibility. Three addressable internal Status
Registers provide complete status information to the proces-

sor. The processor operates upon the FDC via eight registers
which are used during command execution: a Command
Register, a Data Register, two Current Track Registers, a Seek
Track Register, a Current Sector Register, a Sector Count
Register, and a Compare Count Register. Four additional
control registers permit customizing the FDC to the selected
drive and modes of operation.
The following command functions are available:
Restore Step-Out Seek
Read Data
Step
Step-In
Track Verify Compare Data
Write Data
Read Address Format Track
Write Verify Read Track
Software Reset
The FDC will interface to both the standard (8") floppy disk
drive and the minifloppy (S'I4")drive. Compatibility with the
products of several manufacturers is assured by the inclusion
of a wide range of programmable Track-te-Track Seek Times
and Head Load Times.
The FDC requires +S volts only and all inputs and outputs
are TTL compatible.

-FOR FUTURE RELEASE

239

FDC 7003 REGISTER TABLE
07

STATUS REGISTER A
INT

R/W ,
DONE

SEEK
DONE

INDEX
DET

R/W
READY' COMPARE 'ILLEGAL ,
. CHG
FOUND
STATUS

STATUS REGISTER S
WR
PROT

ID
RNF

DATA
RNF

CRC
ERROR

DATA
LOST

DATA
AM1

TRACK I
ERROR

DATA
AM0

STATUS REGISTER C
DXRQ

R/W
BUSY

SEEK
BUSY

INDEX

READY I

TRACK
ZERO

LDHD1

LDHD0

COMMAND
CONTROL A

STEP INTERVAL

SEEK LATENCY

CONTROLS

HEAD UNLOAD DELAY

HEAD LOAD LATENCY

CONTROLC
INT
I
ENABLE

MFM

SEEK
I INDEX I READY I
INT ENA
OVERLAP
INT ENA

SEL2

SEL1

SEL0
I

CONTROLD
HALF
SPEED

IRESERVE9 INTERNAL I MODIFY I
PRECOMP
TGT43

IBM
LEN

GAP2
LEN

FF/4E
LEN

I DEL DATA I
INT ENA

CURRENT TRACK.
CURRENT TRACK 1
SEEK TRACK
RESERVED
COMPARE COUNT
SECTOR COUNT
SIDE

CURRENT SECTOR
DATA

FDC 7003 COMMAND STRUCTURE
COMMANO REGISTER
CONTENTS
COMMANO
RESTORE
SEEK
TRACK VERIFY
STEP IN
STEP OUT
STEP

07 06 05 04 03 02 01

0 0
0
0 0 1 0 h
0 1 0 0 0
0
0
0
0
0
0
0

COMMANO REGISTER
CONTENTS

COMMANO

v 0 0
v 0 0

READ TRACK DATA ONLY
READ TRACK CLK/DATA
FORMAT TRACK AUTO
FORMAT TRACK CLK/DATA
READ ADDRESS

0 0
v u 0
v u 0
v u 0

SOFTWARE RESET
READ DATA
COMPARE DATA
WRITE DATA
WRITE VERIFY

0
0

07 06 05 04 03 02 01

1 0
1
1

1 0
1 0
1 0

0 0 0
1

0
0
0

o
1 0
S 0

R3 R2 R1 R0

m f
h m 0 0
h m a, "0
1 h m a, "0

Circuil diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given, The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies, Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others, SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

240

FOC 1791*
FOC 1792*
FOC 1793*
FOC 1794*
J.1.PC FAMILY

Floppy Oisk Controller/Formatter
FOC
FEATURES

PIN CONFIGURATION

o SOFT SECTOR FORMAT COMPATIBILITY
o AUTOMATIC TRACK SEEK WITH VERIFICATION
o ACCOMMODATES SINGLE AND DOUBLE
o

o
o

'-'

NC ( 1
2
3
4
RE
Ao ; 5
6
A,
DALO' ( 7
5A[1' ( 8
DAL 2' (
10
DAL 3' ( 9
0
DAL 4' [ 11
DAL 5' ( 12
DAL 6' ( 13
DAL 7' ( 14
STEP [ 15
DIRC [ 16
EARLY ( 17
LATE ( 18
MR [ 19
GND [ 20

We(

DENSITY FORMATS
IBM 3740 Single Density (FM)
IBM System 34 Double Density (MFM)
READ MODE
Single/Multiple Record Read with Automatic Search
or Entire Track Read
Selectable 128 Byte or Variable Length Record
WRITE MODE
Single/Multiple Record Write with Automatic Sector
Search
Entire Track Write for Diskette Initialization
PROGRAMMABLE CONTROLS
Selectable Track to Track Stepping Time
Side Select Compare
SYSTEM COMPATIBILITY
Double Buffering of Data 8 Bit Bi-Directional Bus for
Data, Control and Status
DMA or Programmed Data Transfers
All Inputs and Outputs are TTL Compatible
On-chip Track and Sector Registers/Comprehensive
Status Information
WRITE PRECOMPENSATION (MFM AND FM)

40
39
38
37
36
35
34
33

+12V
INTRO
DRO
DDEN"
WPRT

piP

P TROO
P

WF
READY
32
31
WD
30
WG
29
TG43
28
HLD
27 P RAW READ
26 ~ RCLK
25
RG
24
CLK
23
HLT
22
TEST
21
+5V

'TRUE BUS FOR FDC 1793 and FDC 1794
"MUST BE LEFT OPEN FOR FDC 1792 and FOC 1794
PACKAGE: 40 pin D.I.P.

o WINDOW EXTENSION (IN MFM)
o INCORPORATES ENCODING/DECODING
AND ADDRESS MARK CIRCUITRY
o COMPATIBLE WITH FD1791 , FD1792, FD1793,
FD1794

GENERAL DESCRIPTION

The FDC 179X is an MOS/LSI device which performs the
functions of a Floppy Disk Controller/Formatter in a
single chip implementation. The basic FDC 179X
chip design has evolved into four specific parts:
FDC 1791, FDC 1792, FDC 1793 and the FDC 1794.
This FDC family performs all the functions necessary
to read or write data to any type of floppy disk drive.
Both 8" and 5114" (mini-floppy) drives with single or
double density storage capabilities are supported.
These n-channel MOS/LSI devices will replace a large
amount of discrete logic required for interfacing a host
processor to a floppy disk.
The FDC 1791 is IBM 3740 compatible in Single density
mode (FM) and System 34 compatible in double density
mode (MFM). The FDC 1791 contains enhanced features necessary to read/write and format a double

density diskette. These include address mark detection,
FM and MFM encode and decode logic, window extension, and write precompensate.
The FDC 1793 is identical to the FDC 1791 except the
DAL lines are TRUE for systems that utilize true
data busses.
The FDC 1792 operates in the single density mode only.
Pin 37 (DDEN) of the FDC 1792 must be left open for
proper operation. The FDC 1794 is identical to the
FDC 1792 except the DAL lines are TRUE for systems
that utilize true data busses.
The processor interface consists of an 8 bit bidirectional
bus for data, status, and control word transfers. This
family of controllers is configured to operate on a
multiplexed bus with other bus-oriented devices.

'FOR FUTURE RELEASE

241

System Block Diagram

K...

RAW READ

..~

DATA (8)

RClK
RG

lATE

EARLY

CS
C

F
l

M
P
U
T
E
R

~ 10K

P
P
Y

FLOPPY DISK
CONTROllER/
FORMATTER

I
N
T
E
R
F
A
C
E

0
I
S
K

WPRT
WFNFOE

+5V

R
I

TRoa

V
E

< 10K

10K?

READY
- -

TG43

~>
ORO

STEP

INTRO

DIRC

ClK

+5V

HlD

-----

lDDEN

HlT
GND

VDD

Vee

l l

+12

ONE SHOT
(IF USED)

+5V

242

CCC3500
ILPC FAMILY

Cassette/Cartridge Data Handler
CCDH
FEATURES

PIN CONFIGURATION

D Facilitates Magnetic Tape Cassette or

'-'

Cartridge to Processor Interfacing
D Performs All Data Operations
D Up to 250K bps Data Transfer Rate
D Recording Code Independent
D Compatible with Standard and Mini Cassettes
D Compatible with Standard and Mini 3M-type
Cartridges
D Read-While-Write Operation for Write
Verification In Dual Gap Head Systems
D Programmable Sync Byte
D Internal Sync Byte Detection and Byte Framing
D Fully Double Buffered
D Data Overrun!Underrun Detection
D Tri-State Output Bus for Processor
Compatibility
D TTL Compatible Inputs and Outputs

RD
RCK
RDRR
RDE
RDR
RDL
RD7
RD6
RD5
RD4

40
3.

38
37
36

35
34
33

1~D:~

RD3

RD2~

12
13
14

29
26
27
26
25
24
23
22
21

RI;)1

RD'
NO
NC
NO

15
16
17

NO
NO

SBS

WOS
WCK
FBS
SBD
RG
WD7
W06
WD5
WD4
WD3
WD2
W01
WDe

voo
WDU
GND
WD

~WDR
NC

PACKAGE: 4O-Pin D.I.P.

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

The CCC 3500 is an MOS integrated circuit which
simplifies the data interface between a
processor and a magnetic tape cassette or
cartridge drive. During a write operation the
CCDH receives data from the processor and
shifts it out bit serially to the cassette! cartridge
data encoding logic. Similarly during a read
operation the CCDH receives a bit-serial stream
of read data from the cassette! cartridge data
recovery circuit, establishes byte synchronization by detecting the sync byte, and transfers
data on a byte by byte basis to the processor.
The CCDH detects data overrun and underrun
conditions and indicates these conditions on its
status lines. A data underrun causes data from a
special programmable fill register to be written
onto the cassette! cartridge until new data is
entered into the write data buffer or until the
write operation is ended.
Separate read and write data registers permit
simultaneous read and write operations. Drives
with dual gap heads may utilize this read-whilewrite feature for write data verification thereby
enhanCing system throughput and reliability.
The CCDH is fully double buffered and all inputs
and outputs are TTL compatible.

243

DESCRIPTION OF OPERATION
Write Operation

After power-on, the Write Clock is set at the desired bit
rate and the desired fill byte is written into the Write
Fill Register. After the external control logic has
caused the tape to come up to operating speed and
ac!ivated the write enable signal, the first byte to be
wntten should be loaded into the Write Data Register.
This by~e is then I
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